1989_IDT_High_Performance_CMOS_Data_Book 1989 IDT High Performance CMOS Data Book
User Manual: 1989_IDT_High_Performance_CMOS_Data_Book
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Integrated
Device lechnology
/
High Performance CMOS
DATA BOOK SUPPLEMENT
1989
FAST LOGIC
FAST LOGIC
Product Selector and Cross Reference Guides
Technology/Capabilities
Quality and Reliability
Static RAMs
Multi-Port RAMs
FIFO Memories
Digital Signal Processing (DSP)
Bit-Slice lVIicroprocessor Devices (MICROSlICE™) and EDC
Reduced Instruction Set Computer (RISC) Processors
logic Devices
Data Conversion
ECl Products
Subsystems Modules
Application and Technical Notes
Package Diagram Outlines
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _._-------_ ..
Integrated Device Technology, Inc.
HIGH-SPEED CMOS
DATA BOOK
3236 Scott Boulevard, Santa Clara, California 95054
Telephone: (408) 727-6116 • TWX: 910-338-2070 • FAX: (408) 492-8674
Printed in U.S.A. 3/89
til 1989 Integrated Device Technology, Inc.
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CONTENTS OVERVIEW
Integrated Device Technology's Data Book Supplement is comprised of new/revised data
sheets, application notes and package drawings to its 1988 Data Book. Only new or revised.
data sheets are contained in the supplement. The data sheets for those products whose specification have not changed are in the 1988 Data Book. Customers, with both the Data Book
Supplement illJQ 1988 Data Book, now have a complete specification set of IDT's advanced
CMOS products.
The supplement's table of contents contains a listing of all of IDT's products. Products
which are in the supplement will have their page number listed as "Sx-yy", where:
S
data sheet is in supplement
x
section where data sheet resides
yy
page number within the section
Products which are boldfaced, and have their page numbers listed as "x-yy", can be found
in the 1988 Data Book.
The block diagram on the cover of this book pictorially illustrates the multiple product lines
offered by Integrated Device Technology, a recognized leader in high-speed CMOS technology.IDT's broad line of products enables us to provide a complete CMOS solution to designers of high-performance digital systems. Our products include industry standard devices as
well as products with speed, lower power, package and/or architectural benefits that allow the
designer to achieve significantly improved system performance.
Use this book to find ordering information: Start with the Ordering Information chart at
the back of each data sheet, or Cross Reference Guides (p S1-23) along with Package Diagram Outline Index (p S15-3), to compose the complete IDT part number. Reference data on
our Technology Capabilities and Quality Commitments are included in separate sections (S2,
S3, respectively).
Use this book to find product data: Start with the Table of Contents, organized by product
line (p Sii), or with the Numeric Table of Contents across all product lines (p Sxiv); for a more
complete summary of product line offerings, use the Product Selector Guide (p S1-2). These
indexes will direct you to the page on which the complete technical data sheet can be found,
and may in some cases refer you to related Application or Technical Notes (p S 14-1). Data
sheets may be of the following type:
ADVANCE INFORMATION -contain initial descriptions, subject to change, for products that
are in development, including features and block diagrams.
PRELIMINARY -contain descriptions for products soon to be or recently released to production, including features, pinouts and block diagrams. Timing data are based on simulation or
initial characterization and are subject to change upon full characterization.
FINAL-contain minimum and maximum limits specified over the complete supply and temperature range for full production devices.
New products, product performance enhancements, additional package types and new
product families are being introduced frequently. Please contact your locallDT sales representative to determine the latest device specifications, package types and product availability.
Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in
order to Improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described
herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of /DT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical Implant into the body or (b) support or
sustain life and whose failure to perform, when properly used in accordance with Instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect its safety or effectiveness.
.
CEMOS, BiCEMOS, MICROSLlCE, Flexishift and SPC are trademarks of Integrated Device Technology, Inc.
SPC (Serial Protocol Channel) has a patent pending.
FAST is a trademark of Fairchild Semiconductor Co.
Z-80 is a registered trademark of Zilog, Inc.
Si
SUMMARY TABLE OF CONTENTS
CONTENTS
PAGE
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Disclaimer
Life Support Policy
Table of Contents
Summary Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . ..
Alphanumeric Listing by Product Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Numerical Index .....................................................................................
Si
Sii
Siii
Sxiii
Product Selector and Cross Reference Guides
Part Number Description.. . . . . . . .. . . .... . . . . . . . . . . . .. . . ... . . . . . . . . . . . . .. .. . .. . . . . . . . . ... . . .. . . . ....... . ... S1-1
Product Selector Guide ................................................................................... S1-2
Cross Reference Guides
Static RAM............... ............................ .... . ............... ... ........................
Multi-Port RAMs .....................................................................................
FIFO ..................................................... ,..........................................
Digital Signal Processing .................. . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MICROSLICE™ and EDC ...................... ~............... .......................................
Data Conversion .........................................................................'............
ECl ............................................................ ;..................................
Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S1-23
S1-35
S1-36
S1-37
S1-39
S1-40
S1-41
S1-42
Technology/Capabilities
IDT... leading the CMOS Future.................... ......... ........ ........ ................ ... . ...........
lOT Military and DESC-SMD Program .......................................................................
Radiation Hardened Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOT Leading CEMOS ™ Technology ..................... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Surface Mount Technology ............................................................................
State-of-the-Art Facilities and Capabilities. . . . . .. . . .. . . .. .. . . .. . . . .. . . . . . . . . . . .. . .. . . ... . ... . . . . . .... .. ....
Superior Quality and Reliability ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S2-1
S2-2
S2-3
S2-4
S2-6
S2-7
S2-8
Quality and Reliability
lOT Commitment to Quality .............................. : ............ ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Monolithic Hermetic Package Processing Flow ............................................................
Monolithic Plastic Package Processing Flow ..............................................................
Module Assembly Hermetic Packaging Processing Flow ....................................................
Radiation ToleranVEnhanced/Hardened Products for Radiation Environments . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
Static RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Multi-Port RAMs ........................................................................................
FIFO Memories .............,............................ ..... ..... .................................. ....
Digital Signal Processing ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S3-1
S3-2
S3-4
S3-6
S3-9
S4-1
S5-1
S6-1
S7-1
Bit-Slice Microprocessor Devices (MICROSLICE TM) and Error Detection and Correction. . . . . . . . . . . . . . . . . . . . . . . . ..
Reduced Instruction Set (RISe) Processors ................................................................
logic Devices.... . . . . . .. ... . . .. ..... . . . . . . . . . . . .. . .. .. . ... . . ... . . . . . . . . . . . . ... . . . . . . .. . . . . . . . . . . .. . . . ..
Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ECl Products ..........................................................................................
Subsystems Modules. . . . . . .. . . .... . . . . . . ... . . .. . .. . . . . .. . ...... . . . . . .. .. ... . . . . . .. .. . .. . ... . . .. ... . . . . . ..
S8-1
S9-1
S10-1
S11-1
S12-1
S13-1
Application and Technical Notes. . . .. . . . . . . .. . .. . . .. . . . . .. . . ..... . ... . . . .. . .. . . . .. . . .. . ... . . . . . ... .. . .. . ..
Package Diagram Outlines ........................................... :. .. . .. . . . . . . . .. . ... . . . . . . . . .. .... ..
S14-1
S15-1
Sii
TABLE OF CONTENTS
CONTENTS
PAGE
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Disclaimer
Life Support Policy
SI
Table of Contents
Summary Table of Contents ........................................................................... .
Alphanumeric Listing by Product Line ................................................................... .
Numerical Index .................................................................................... .
Sii
Sili
Sxiii
Product Selector and Cross Reference Guides
Part Number Description ................................................................................. .
Product Selector Guide .................................................................................. .
S1-1
S1-2
Cross Reference Guides
Static RAM ......................................................................................... .
Multi-Port RAMs .................................................................................... .
FIFO .............................................................................................. .
Digital Signal Processing ............................................................................. .
MICROSLICE ™ and EDC ............................................................................ .
Data Conversion .................................................................................... .
ECl .............................................................................................. .
Subsystems ........................................................................................ .
S1-23
S1-35
S1-36
S1-37
S1-39
S1-40
S1-41
S1-42
Technology/Capabilities
IDT... leading the CMOS Future ........................................................................... .
S2-1
lOT Military and DESC-SMD Program ..................................................... ; ................ .
Radiation Hardened Technology· .............................. , ........................................ .
S2-2
S2-3
S2-4
S2-6
S2-7
S2-8
lOT leading CEMOS ™ Technology ........................................................................ .
Surface Mount Technology ............................................................................ .
State-of-the-Art Facilities and Capabilities ................................................................ ;
Superior Quality and Reliability ........................................................................ .
Quality and Reliability
lOT Commitment to Quality ............................................................................... .
Monolithic Hermetic Package Processing Flow ........................................................... .
Monolithic Plastic Package Processing Flow ............................................................. .
Module Assembly Hermetic Packaging Processing Flow ................................................... .
Radiation ToleranVEnhanced/Hardened Products for Radiation Environments .................................. .
CONTENTS
OUTPUT
ORGANIZATION
S3-1
S3-2
S3-4
S3-6
S3-9
PAGE
Static RAMs
lOT 6167
lOT 7187
lOT 71257
x1
x1
x1
16K (16K x 1) CMOS SRAM (Power Down) .............................. .
64K (64K x 1) CMOS SRAM (Power Down) ...••••••...•.•.....•..•.•••
256K (256K x 1) CMOS SRAM (Power Down) (14-74) ..................... .
S4-1
84-11
S4-19
lOT 6168
lOT 71681
x4
x4
S4-28
lOT 71682
x4
lOT 6177
lOT 6178
lOT 61970
lOT 7177
lOT 7178
lOT 6198
lOT 7188
lOT 7198
lOT 71981
lOT 71982
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
16K (4K x 4) CMOS SRAM (Power Down) (14-74) ........................ .
16K (4K x 4) CMOS SRAM (Separate I/O-Output Follows
Input at Write) (14-36, 14-74) .................................... .
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write)
(14-36, 14-74) ................................................. ;
CMOS High-Speed Static RAM Cache-Tag (4K x 4) ...................... .
16K (4K x 4) CMOS Cache-Tag SRAM (14-47) .......................... .
CMOS Static RAM With Output Enable 16K (4K x 4) ...................... .
CMOS High-Speed Static RAM Cache-Tag 16K (4K x 4-8it) ................ .
High-Speed Static RAM Cache 16K(4K x 4-8it) .......................... .
64K (16K x 4) CMOS SRAM (with Output Enable) (14-74) ................. .
64K (16K x 4) CMOS SRAM (Power Down) .............................. .
64K (16K x 4) CMOS SRAM (2 CS and OE) (14-74) ..................... ..
64K (16K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) .... .
64K (16K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) ......... .
S4-39
84-39
S4-50
84-52
S4-59
S4-65
S4-67
S4-69
S4-78
S4-86
S4-96
84-96
sm
/'
/
/'
TABLE OF CONTENTS (CON'T.)
CONTENTS
lOT 61592
lOT 61593
lOT 61594
OUTPUT
ORGANIZATION
x4
x4
x4
lOT 61595
x4
lOT 71598
lOT 61298
lOT 71258
lOT 71281
lOT 71282
IOT7MP456
x4
x4
x4
x4
x4
x4
CMOS Synchronous Static RAM with Transparent Outputs 64K (16K x 4-Bit) ...
CMOS Synchronous Static RAM with Output Registers 64K (16K x 4-Bit) ......
CMOS Synchronous Static RAM with Output Registers and OE
.
64K (16K x 4-Bit) ................................................
CMOS Synchronous Static RAM with Transparent Outputs and
OE 64K (16K x 4-Bit) .............................................
CMOS Static RAM with Latched Addresses 64K (16K x 4-Bit) ................
256K (64K x 4) CMOS SRAM (with Output Enable) (14-36) .................
256K (64K x 4) CMOS SRAM (14-74) ...................................
256K (64K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) .....
256K (64K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) ..........
256K (64K x 4) CMOS SRAM (Plastic SIP) Module ........................
PAGE
$4-106
$4-108
$4-110
S4-112
$4-114
S4-115
$4-125
S4-134
S4-134
S13-177
1017MP564
x5
80K (16K x 5) CMOS SRAM (Plastic SIP) Module .......................
13-29
IOT7MC4018
x6
64K x 6 CMOS Static RAM Ceramic SIP Module. .........................
S13-158
lOT 8M824
lOT 8MP824
lOT 6116
lOT 7164
lOT 7165
lOT 71C65
lOT 7174
lOT 71564
lOT 71578
lOT 71256
IOT7M812
IOT7MP6025
IOTSM856
lOT 7MP400SL
lOT 71583
x8
x8
x8
x8
x8
x8
xS
x8
xS
xS
xS
x8
x8
x8
x8
1Megablt (128K x 8) CMOS SRAM Module.............................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) Module. . . . . ..... .... . ..
16K (2K x 8) CMOS SRAM (14-74) .....................................
64K (8K x 8) CMOS SRAM (Power Down) (14-74) .........................
64K (8K x 8) Resettable CMOS SRAM....................... ............
64K (8K x 8) SRAM (Resettable CMOS I/O) ..............................
64K (8K x 8) CMOS Cache-Tag SRAM (14-47) ...........................
CMOS Static RAM with Latched Addresses 64K (8K x S-Bit) .................
CMOS Static RAM with Exclusive-Or Latched Addresses 64K (SK x S-Bit) .. . . ..
(32K x 8) CMOS SRAM (Power Down) (14-74) ............................
512K (64K x 8) CMOS SRAM Module...................................
512K (64K x 8) Synchronous SRAM (Plastic SIP) Module. ... ... . . . . . .... . ..
256K (32K x 8) Low-Power CMOS SRAM Module.......................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) Module ...................
High-Speed Static RAM Organized as 32K x S . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13-107
13-86
$4-143
$4-:154
$4-163
S4-172
S4-181
S4-191
S4-192
$4-193
S13-17
S13-189
13-113
S13-183
$4-202
IOT7169
10171259
lOT 71509
IOT7M912
x9
x9
x9
x9
CMOS High-Speed Static RAM SK x 9 ..................................
High-Speed Static RAM Organized as 32K x 9 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Speed Static RAM Organized as 32K x 9 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
512K (64K x 9) CMOS SRAM Module...................................
$4-204
S4-205
S4-207
S13-17
lOT 7186
IOTSMP628
lOT 71502
lOT 71586
lOT 8M628
IOT7M656
IOT7MC4005
lOT 8MP656
lOT 8M656
IOT7MB4009
lOT 8M612
lOT SMP612
IOT7M624
lOT 8M624
lOT 8MP624
.IOT 7M4016
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
64K (4K x 16) CMOS SRAM (Power Down) ........................ ~ . . . . .. S4-209
128K (8K x 16) CMOS SRAM (Plastic SIP) Module ........................ S13-195
CMOS Static RAMS 64K (4K x 16-Bit) Registered RAM with SPC™ .......... $4-218
CMOS Static RAMS 64K (4K x 16-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S4-242
128K (8K x 16) CMOS SRAM Module..................... ......... .... 13-99
256K (16K x 16) CMOS SRAM Module .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S13-8
256K (16K x 16) CMOS Static RAM Ceramic Dual SIP Module. .............. S13-152
256K (16K x 16) CMOS SRAM (Plastic SIP) Module ....................... S13-195
256K (16K x 16) CMOS SRAM Module....... ....................... ... 13-99
512K 2(16K x 16) CMOS Static RAM FR-4 DIP Module .. :. .. . . . . . . . . . . . . . .. S13-92
512K (32K x 16) CMOS SRAM Module.............. ................... 13-92
512K (32K x 16) CMOS SRAM (Plastic SIP) Module..................... 13-74
1 Megabit(64K x 16) CMOS SRAM Module.............................. S13-1
1 Megabit (64K x 16) CMOS SRAM Module ............................ 13-92
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) Module. . . . . . . . . . . . . . . .. 13-74
4 Megabit (256K x 16) CMOS SRAM Module... ........................ .. S13-23
IOT7M6001
x20
Dual, Multiplexed 16K x 20 SRAM Module........... ....................
S13-35
IOT7MC4032
lOT 7M4017
x32
x32
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) Module .................
2 Megabit (64K x 32) CMOS SRAM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S13-164
S13-29
IOT7MB6039
IOT7MB6049
x60
x60
Dual (16K x 60) Data/Instruction Cache Module for 10T79R3000 CPU. ... . . . ..
Dual (16K x 60) Data/Instruction Cache Module for 10T79R3000 CPU
(Multiprocessor) (S14-6) . . . . . . .. . .. . . .. . . . . . .. . . ... . ......... . . ...
S13-105
Siv
S13-135
TABLE OF CONTENTS (CON'T.)
CONTENTS
OUTPUT
ORGANIZATION
lOT 7MB6044
lOT 7MB6043
lOT 7MB6051
x64
x64
x64
lOT 7MB6040
lOT 7MB6042
PAGE
S13-133
S13-131
x64
Dual (4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU. . . . ... ...
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU.... . . . ...
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) ...................... '. . . ... . . .... .. .. . . . . . ......
Dual (16K x 64) Data/Instruction Cache Module For General CPUs ...........
x112
8K x 112 High-Speed Writable Control Store w/SPC™ .....................
S13-117
S13-138
S13-111
Multl·Port RAMs
lOT 7130
lOT 7140
lOT 70104
lOT 7010
lOT 70101
lOT 70105
lOT 7132
lOT 7142
lOT 71321
lOT 71421
lOT 7012
lOT 70121
lOT 70125
lOT 71322
lOT 7133
lOT 7143
lOT 7134
lOT 71342
lOT 7024
lOT 7005
lOT 7025
lOT 7006
lOT 7M134
lOT 7M135
lOT 7M144
lOT 7M145
lOT 7M137
IOT7050S/L
lOT 7052
8K (1K x 8) Dual-Port RAM (MASTER) (14-260, 14-9, 14-68, S14-63) ....................
8K (1K x 8) Dual-Port RAM (SLAVE) (14-260, 14-9, 14-68, S14-63) .........•............
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) ..................
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) ..................
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) ....... . .... . . . . ..
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14;..63) ..................
16K (2K x 8) Dual-Port RAM (MASTER) (14-260,14-9,14-68, S14-63) ...................
16K (2K x 8) Dual-Port RAM (SLAVE) (14-260,14-9, 14-68, S14-63) .....................
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) (14-260, 14-9, 14-68, S14-63) .........
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) (14-260, 14-9, 14-68, S14-63) . . .. . ... . ..
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) .......... :.......
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ...........
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) . . . . . . . . . ..
16K (2K x 8) Dual-Port RAM (w/Semaphores) (14-260, 14-9, 14-68, S14-63) ..............
32K (2K x 16) Dual-Port RAM (MASTER) (14-260,14-9, 14-68, S14-63) ..................
32K (2K x 16) Dual-Port RAM (SLAVE) (14-260, 14-9, 14-68, S14-63) ....................
32K (4K x 8) Dual-Port RAM (14-260, 14-9, 14-68, S14-63) .. . . .. ... .. .. . . .. .. ... . .. . ...
32K (4K x 8) Dual-Port RAM (w/Semaphores) (14-260, 14-9, 14-68, 14-139, S14-63) .......
High-Speed 4K x 16 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ..... ~'....
High-Speed 8K x 8 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ...........
High-Speed 8K x 16 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ..........
High-Speed 16K x 8 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ..........
64K (8K x 8) Dual·Port RAM Module ..............................................
128K (16K x 8) Dual·Port RAM Module ............................................
64K (8K x 8) Dual·Port RAM Module (SLAVE) .. . . . . . . . .... ... .. . . . . . . .. . .. . .. . . . . . ..
128K (16K x 8) Dual·Port RAM Module (SLAVE) .. ' . . . . . . . ..... . ... . . .. .. .. . . ...... ..
256K (32K x 8) Dual·Port RAM Module ............................................
High-Speed 1K x 8 Four-Port Static RAM. . .. . ...... .. . . . . . ........ . . . ... .. . . . .......
High-Speed 2K x 8 Four-Port Static RAM. . . . . . . . .. . . . . .. ... . . . ... . . ... .. .. . . ... . . . ..
S5-1
S5-1
S5-18
S5-18
S5-19
S5-19
S5-20
S5-20
S5-35
S5-35
S5-51
S5-52
S5-52
S5-53
S5-65
S5-65
S5-79
S5-87
S5-100
S5-103
S5-106
S5-109
13-125
13-125
13-142
13-142
13-135
S5-112
S5-121
FIFO Memories
lOT 7200
lOT 7201A
lOT 7202SNLA
lOT 72021
lOT 72031
lOT 72041
lOT 7203
lOT 7M203
lOT 7204
IDT7M204
lOT 72B04
lOT 72045
lOT 72055
IDT7205
IDT7M205
IDT7206
IDT7M206
IDT72103
256 x 9 FIFO (14-1, 14-251, 14-254, 14-257) . . . . .. . . . . . . . ... . . .... . . .. . . .. . . . .. . .. ..
512 x 9 FIFO (14-1, 14-251, 14-254, 14-257) . .. . .. . .... . . .... .. . .. . . . ... .. . . . . . .....
CMOS Parallel First-In/First-Out FIFO 1024 x 9-Bit ....................................
CMOS Parallel FIFO with Flags and OE-1K x 9, 2K x 9, 4K x 9 .........................
CMOS Parallel FIFO with Flags and OE-1 K x 9, 2K x 9, 4K x 9 .........................
CMOS Parallel FIFO with Flags and OE-1K x 9, 2Kx 9, 4K x 9 .........................
2K x 9 FIFO (14-251, 14-56, 14-68) . . . ... . .. . . . . . . . . . . ... . .... . . . . .. ... .. . . . . . .....
CMOS Parallel In-Out FIFO Module 2K x 9·Bit & 4K x 9-Bit ................. . .... . . . ..
4K x 9 FIFO (14-251, 14-56, 14-68) ....... , . . . . . . . . .. . . . . .... . . .. . .. . .. .. . . ........
CMOS Parallel In-Out FIFO Module 2K x 9·Blt & 4K x 9-Bit ................. . . . . . . .. ..
BiCMOS Parallel First-In/First-Out FIFO 4K x 9-Bit ....................•...............
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Bit ..... ~ . .. ... .... . . . . . . .. ..
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Blt . . . . .. . . ... . . ... . . ... . ....
CMOS Parallel First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit . . . . . . . . . . . . . . . . . . . . . . . . . ..
8K x 9 FIFO Module ................................................•...........
CMOS Parallel First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit . . . . . . . . . . . . . . . . . . . . . . . . . ..
16K x 9 FIFO Module ...........................................................
2K x 9 Parallel-Serial FIFO (14-146) . ... . . .. . . .. .. . . . . . ... . . ... . . . ... . .... . . . . . . . . ..
S6-1
S6-1
S6-14
S6-27
S6-27
S6-27
S6-41
13-146
S6-41
13-146
S6-54
S6-55
S6-55
S6-56
13-157
S6-56
13-157
S6-57
Sv
TABLE OF CONTENTS (CON'T.)
PAGE
CONTENTS
lOT 72104
lOT 72105
lOT 72115
lOT 72125
lOT 72131
lOT 72141
lOT 72132
lOT 72142
lOT 72215M/S
lOT 72225M/S
lOT 72401
lOT 72402
lOT 72403
lOT 72404
lOT 72413
lOT 7252
lOT 72520
lOT 7MB2001S
IOT7MB2002
lOT 72521
Digital Signal Processing
lOT 7209
lOT 7210
lOT 7212
lOT 7213
lOT 7216
lOT 7217
IDT7243
lOT 7317
lOT 7320
lOT 7321
lOT 7381
lOT 7383
lOT 7384
4K x 9 Parallel-Serial FIFO (14-146) ..... . . . . .. . .... . ... ..... . . ... . . . . . . . .. ... . . . ...
256 x 16,512 x 16, 1024 x 16 Parallel-to-Serial CMOS FIFO ............................
256 x 16,512 x 16, 1024 x 16 Parallel-to-Serial CMOS FIFO ............................
256 x 16,512 x 16, 1024 x 16 Parallel-to-Serial CMOS FIFO ............................
2048 x 9-Bit & 4096 x 9-Bit Parallel-to-Serial CMOS FIFO (14-146) .. . .. . . . . . . . .. . .. . . . ...
2048 x 9-Bit & 4096 x 9-Bit Parallel-to-Serial CMOS FIFO (14-146) .......... . . . . . . . . . .. ..
2048 x 9-Bit Serial to Parallel CMOS FIFO (14-146) ...................................
2048 x 9-Bit Serial to Parallel CMOS FIFO (14-146) ...................................
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO. . . . . . . . . . . .. . .. . .. . . . . .. . . . . . . ...
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO ............... " . . . . . . . . . ... . . . ..
64 x 4 FIFO with Output Enable ...................................................
64 x 5 FIFO with Output Enable ...................................................
64 x 4 FIFO with Output Enable. .......... ............................ .... ... .....
64 x 5 FIFO with Output Enable ...................................................
CMOS Parallel 64 x 5 FIFO (with Flags) ..... ..... ........................... ........
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO ..............................................
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO ..............................................
8K x 36 FIFO Module ......................................... " ............ '" ..
36 to 9 BiFIFO Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1K x 18-Bit CMOS BiFIFO ..... ........... ...... .............. . .. . ....... ... ......
S6-57
S6-83
S6-83
S6-83
S6-95
S6-95
S6-109
S6-109
S6-122
S6-122
S6-123
S6-123
S6-123
S6-123
S6-134
S6-145
S6-145
S13-76
S13-85
S6-165
12 x 12 Parallel MUltiplier-Accumulator. . . . .. . .. . . .. . . . . . .. . .. . . . . . . . . . . . . . . . . . . . ..
16 x 16 Parallel Multiplier-Accumulator. . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . .. . . . . . .. . ..
12 x 12 Parallel Multiplier. . . . . . . . . . . . . . . . . . . ... . . . . . . . . .. . ... . . . . . . . . .. . . . . . . . . ..
12 x 12 Parallel Multiplier (Single Clock) ...........................................
16 x 16 Parallel Multiplier. . . . . . . . . . . . . ... . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . ....
16 x 16 Parallel Multiplier (32-Bit Output) ..........................................
16 x 16 Parallel Multiplier-Accumulator (19-Blt Output) ..................... '" . . . . . ..
16 x 16 Parallel Multiplier (32-Bit Output) (S14-12) ....................................
16-Bit CMOS Multilevel Pipeline Registers (S14-12) ...................................
16-Bit CMOS Multilevel Pipeline Registers (S14-12) ...................................
16-Bit CMOS Cascadable ALU (S14-12) ............................................
16-Bit CMOS Cascadable ALU (S14-12) ............................................
16-Bit CMOS Cascadable ALU ....................................................
7-1
7-9
7-20
7-20
7-55
7-55
7-9
S7-1
S7-9
S7-9
S7-15
S7-15
S7-23
Bit-Slice Microprocessor Devices (MICROSLICE 'M) and Error Detection and Correction
lOT 39C01
4-Bit Microprocessor Slice (14-56) . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . ...
Carry-Lookahead Generator ............................. , . .. . . .. . . . . .. . . . . . . ....
lOT 39C02
lOT 39C03
4-Bit Microprocessor Slice (14-56) ...............................................
IDT 39C10
12-Bit Sequencer (14-56,14-197) . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . ....
lOT 49C25
Microcycle Length Controller. ......... . ... ........... ............. . ... ..........
lOT 49C402
16-Bit Microprocessor Slice (14-41, 14-56, 14-197, 14-200, 14-203) .....................
lOT 49C403
16-Bit Microprocessor Slice W/SPC'M (14-41,14-56,14-154,14-197, S14-1) .............
lOT 49C404
32-Bit Microprogram Microprocessor W/SPC'M ....................................
lOT 49C41 0
16-Bit Sequencer (14-56, 14-86, 14-197, 14-200) . . . . . . . . . . . . . . . . . . . .. . . . . .. . .. . . . . ...
lOT 49C411
20-Bit Interruptable Sequencer W/SPC'M ..........................................
. lOT 39C60
16-Bit Cascadable EOC (14-22, S14-49) ............................................
lOT 49C460
32-Bit Cascadable EOC (14-22, S14-49) ........... ..................... ... ..........
lOT 49C465
32-Bit Flow-Thru Error Detection and Correction Unit ..................................
Svi
8-1
8-12
8-16
8-63
8-117
S8-1
S8-13
8-182
S8-45
8-208
S8-56
S8-83
S8-108
TABLE OF CONTENTS (CON'T.)
CONTENTS
PAGE
Reduced Instruction Set (RiSe) Processors
RISC CPU Processor (S14-9, S14-67, S14-72, S14-78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S9-1
IDT 79R2000A
IDT 79R2010A
RISC CPU Write Buffer (S14-9, S14-67, S14-72, S14-78) .............................. S9-8
IDT 79R2020A
RISC CPU Write Buffer (S14-9, S14-67, S14-72, S14-78) .............................. S9-14
IDT 79R3000
RISC CPU Processor (S14-9, S14-67, S14-72, S14-78) ........... ~ ........ " . . . .. . . . .. S9-20
IDT 79R3010
RISC Floating-Point Accelerator (FPA) (S14-9, S14-67, 814-72, S14-78) . . . . . . . . . . . . . . . . .. S9-39
IDT 79R3020
RISC CPU Write Buffer (S14-9, S14-67, S14-72, S14-78) .............................. S9-52
IDT SPP
System Programmer's Package (SPP) (S14-9, S14-67, 814-72, S14-78) . .. . .. . . . . . . . . . . .. S9-66
IDT 7RS201
R3000 MAC (( Board (S14-9, S14-67, S14-72, S14-78) ................................ S9-68
M/120
RISComputer'" Development System (S14-9, S14-67, 814-72, S14-78) . .. . .. . . . . . . .. . . .. S9-71
M/2000
RISComputer'" Development System (S14-9, S14-67, 814-72, S14-78) .... ............. .S9-73
Logic Devices
IDT FBT Series
54/7 4FBT240
54/7 4FBT241
54/74FBT244
54/74FBT245
54/74FBT373
54/74FBT374
54/7 4FBT540
54/74FBT541
54/74FBT821
54/7 4FBT823
54/74FBT827
54/7 4FBT841
54/74FBT843
IDT FCTXXXCT
54/74FCT240CT
54/74FCT241 CT
54/74FCT244CT
54/74FCT245CT
54/7 4FCT373CT
54/74FCT374CT
54/74FCT540CT
54/74FCT541CT
54/74FCT646CT
54/74FCT821CT
54/74FCT823CT
54/74FCT827CT
54/74FCT841 CT
54/74FCT843CT
54/74FCT845CT
IDT FCTXXXT/AT
54/74 FCT240T/AT
54/74FCT241T/AT
54/74 FCT244T/AT
54/74FCT245T/AT
54/74 FCT373T/AT
54/74 FCT374T/AT
54/74FCT540T/AT
54/74FCT541T/AT
54/74 FCT646T/AT
54/74FCT821T/AT
54/74FCT823T/AT
54/74 FCT827T/AT
Ultra High-Speed BiCMOS Logic .................................................. S10-1
Inverting Octal Buffer/Line Driver .............................................. S10-82
Non-Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-86
Non-Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-86
Non-inverting Octal Bidirectional Transceiver .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-92
Octal Transparent Latch ..................................................... S10-105
Non-Inverting Octal D Flip-Flop ........................ :...................... S10-109
Inverting Octal Buffer. . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . ... . ... .. . . . . . . . . . ... S10-122
Non-Inverting Octal Buffer... . . . . . . . . . .. . . . .. . . . . . . . ... . . . . . . ... .. . . .. . . . .. ... S10-122
10-Bit Non-Inverting Register ................................................. S10-152
10-Bit Inverting Register ..................................................... S10-152
10-Bit Non-Inverting Buffer ................................................... S10-158
10-Bit Non-Inverting Latch. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . ... . . . . .. . . . .. S10-171
9-Bit Non-Inverting Latch ..... , ........... " , . .. . . .. . . . . . . . .. . . . .. . . . . ... . . . .. S10-171
Ultra High-Speed CMOS Logic................ .... ..... ..... ........ ... ........... S10-3
Inverting Octal Buffer/Line Driver .............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-82
Non-Inverting Octal Buffer/Line Driver. . .. . . . . . . .. . . . ... . . . . . . . . . . .. . . . . . ... . . .. S10-86
Non-Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-86
Non-Inverting Octal Bidirectional Transceiver. .. . .. . . .. . . . . . . . . . . . . .. . . .. . . . . . . .. S10-92
Octal Transparent Latch ..................................................... S10-105
Non-Inverting Octal D Flip-Flop ............................................... S10-109
Inverting Octal Buffer. . . . . . . .. . . ... . . .. . . . . . . . .. . . . . . . . . . ... . . . .. . . . . . . . . . . .. S10-122
Non-Inverting Octal Buffer. . . . .. . . .. . . ... . . . . . .. . .. . . . . . . . ... . . . ... . . .. . . . . . .. S10-122
Octal Tr~nsceiver/Register ................................................... S10-140
10-Bit Non-Inverting Register ................................................. S10-152
10-Bit Inverting Register ......................................................S10-152
10-Bit Non-Inverting Buffer ........................................... '.' . . . . .. S10-158
10-Bit Non-Inverting Latch. . . . . . . . . . . . .. . . . .. . . . . . . . .. . . . . . . . .. . .. . . . . . . .. . ... S10-171
9-Bit Non-Inverting Latch. . .. . . . . . . . . . .. . . . .. . .. . . . . .. . . . . . . . .. . .. . . . . . . .. .... S10-171
Bus Interface Latches ...................................... ;................ S10-171
High-Speed CMOS Logic........... ..... .... ..... ................................ S10-6
Inverting Octal Buffer/Line Driver. . .. . . . .. . . . . . . . .. . . . . . . . . . . . ... .. . . . . . . ... ... S10-82
Non-Inverting Octal Buffer/Line Driver. . .. . . . . . . . .. . . . . . . . . . .. . . .. .. . . . . . . . . . . .. S10-86
Non-Inverting Octal Buffer/Line Driver. . .. . . . . . . .. . . . . . . . . . . .. . ... .. . . . .. . . . . ... 510-86
Non-Inverting Octal Bidirectional Transceiver. . . . . . ... . . . . . . . ... ... .. . . ... . .. . ... S10-92
Octal Transparent Latch ..................................................... S10-105
Non-Inverting Octal D Flip-Flop ..................................... ;......... S10-109
Inverting Octal Buffer ............................................ ; .... . ... ... S10-122
Non-Inverting Octal Buffer. . . . . . . . . . . . .. . . . . . . ... . . . . . . .. . ... . . . .. . . . . . .... ... S10-122
Octal Transceiver/Register ................................................... S10-140
10-Bit Non-Inverting Register ...............................................'.. S10-152
10-Bit Inverting Register ..................................................... S10-152
10-Bit Non-Inverting Buffer ................................................... S10-158
Svii
TABLE OF CONTENTS (CON'T.)
PAGE
CONTENTS
54/74 FCT841 T/AT
54/74FCT843T/AT
lOT 54/74FCT151T/AT
lOT 54/74FCT157T/AT
lOT 54/74FCT251T/AT
lOT 54/74FCT257T/AT
lOT 54/74FCT620T/AT
lOT 54/74FCT621T/AT
lOT 54/74FCT622T/AT
lOT 54/74FCT623T/AT
lOT 29FCT52A/B
lOT 29FCT53A/B
lOT 29FCT520A/B
lOT 29FCT521A/B
lOT 39C8XXX
lOT 49FCT601
lOT 49FCT618
lOT 49FCT661
lOT 49FCT804/A
lOT 49FCT818/A
lOT 54/74FCT138/A
lOT 54/74FCT139/A
lOT 54/74FCT161/A
lOT 54/74FCT163/A
lOT 54/74FCT182/A
lOT 54/74FCT191/A
lOT 54/74FCT193/A
lOT 54/74FCT240/A
lOT 54/74FCT241/A
lOT 54/74FCT244/A
lOT 54/74FCT245/A
lOT 54/74FCT273/A
lOT 54/74FCT299/A
lOT 54/74FCT373/A
lOT 54/74FCT374/A
lOT 54/74FCT377/A
lOT 54/74FCT399/A
lOT 54/74FCT521/A
lOT 54/74FCT533/A
lOT 54/74FCT534/A
lOT 54/74FCT540/A
lOT 54/74FCT541/A
lOT 54/74FCT543/A
lOT 54/74FCT573/A
lOT 54/74FCT574/A
lOT 54/74FCT640/A
lOT 54/74FCT645/A
lOT 54/74FCT646/A
lOT 54/74FCT648/A
lOT 54/74FCT651/A
lOT 54/74FCT652/A
lOT 54/74FCT821A/B
lOT 54/74FCT822A/B
lOT 54/74FCT823A/B
lOT 54/74FCT824A/B
lOT 54/74FCT825A/B
lOT 54/74FCT826A/B
lOT 54/74FCT827A/B
10-Bit Non-Inverting Latch ....................... , ....................... , .. .. S10-171
9-Bit Non-Inverting Latch ...................................... '.......... , .. .. S10-171
Fast CMOS 8-lnput Multiplexer (14-209) ............................................ S10-9
Fast CMOS Quad 2-lnput Multiplexer .................. ',' .. . . . . . .. . . . . . . . .. .. . .. .. .. S10-14
Fast CMOS 8-lnput Multiplexer (3-State) (14-209) ..................................... S10-19
Fast CMOS Quad 2-lnput Multiplexer (14-209) ....................................... S10-24
Fast CMOS Octal Bus Transceiver (3-State) .......................................... ' S10-29
Fast CMOS Octal Bus Transceiver (Open Collector) ............................ . . . . . .. S10-35
Fast CMOS Octal Bus Transceiver (Open Collector) ................................... S10-35
Fast CMOS Octal Bus Transceiver (3-State) ..................................... , .... S10-29
Non-Inverting Octal Register Transceiver .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-40
Inverting Octal Register Transceiver ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-40
Multilevel Pipeline Register .:..................................................... S10-45
Multilevel Pipeline Register ....................................................... S10-45
IOT39C8XXX Family ................................................. ,.... ....... 10-11
16-Bit Bidirectional Latch. . . . . . . . . ..... ... . . ... . . . . . . . . .. . . ... . . .. . . . . . ... ..... .. 10-12
16-Blt Register with SPCTM ....................................................,.. 10-13
16-Blt Synchronous Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-29
High-Speed Tri-Port Bus Multiplexer (14-209) ........................................ S10-51
Octal Register with SPCTM (14-154, 14-209) ......................................... SlO-59
1-of-8 Decoder .'................................................................ S10-73
DuaI1-of-4 Decoder' ............................................................ ,10-48
Synchronous Binary Counter w/Asynchronous Master Reset.. . .... . . .. . . . . . . . .. ... .. 10-52
Synchronous Binary Counter w/Synchronous Reset ................................ 10-52
Carry-Lookahead Generator ...................................... , . . . .. . . .. .. . .... S10-77
Up/Down Binary Counter w/Preset and Ripple Clock ............... , ........... , ., .. 10-62
Up/Down Binary Counter w/Separate Up/Down Clocks. . . . . .. . .... . .. . . . . . ... ..... .. 10-67
Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-82
Non-Inverting Octal Buffer/Line Driver .................. , ... . . .. . . . . . .. . . . . . .. ... .. .. S10-86
Non-Inverting Octal Buffer/Line Driver. .. .. ... . . . .. . ....... . .. . .. .. . . .. . . . . .. . .•..... S10-86
Non-Inverting Octal Bidirectional Transceiver ........ , ............................... : S10-92
Octal 0 Flip-Flop w/Buffered Asynchronous Master Reset .............................. S10-96
Universal Shift Register w/Common Parallel I/O Pins ............................•..... S10-100
Octal Transparent Latch. . . . . . ... . . . . . .. ... .. ... . . . . . .... . .. . ... .. .. . . . . . .. ..... .. S10-105
Non-Inverting Octal 0 Flip-Flop.. . . . . . ... ... . . .. . . . . . . . . . .. . .. . . . ... . . . . . . . . .. . .. .. S10-109
Octal 0 Flip-Flop w/Clock Enable.. ...... ......... .......................... ....... S10-113
Quad Dual-Port Register ............................................... ,... ....... S10-117
8-Blt Comparator ................................ '..................... ... ....... 10-113
Octal Transparent Latch... ............ ..............•................. ... ....... 10-117
Octal 0 Flip-Flop ............................. : ...................... ',' . . .• . . . .. 10-121
Inverting Octal Buffer ............................................................ S10-122
Non-Inverting Octal Buffer ........................... , .... .. . . . . . . .. . . . . . . . .. . .. .. S10-122
Octal Latched Transceiver ........................... , ........... , . . . . . . . . . .. . .. .. S10-126
Octal Transparent Latch ........................................ ,. . . .. . . .. .. . .... 10-135
Octal 0 Register .......................................... ;.................... 10-139
Inverting Octal Bidirectional Transceiver. .. .. . . . . .. . . . . ..... . ... . . . . . . . . . . . ... ..... .. S10-132
Octal Bidirectional Transceiver .................................................... S10-136
Non-Inverting Octal Register Transceiver .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-140
Inverting Octal Register Transceiver ................................................ S10-140
Inverting Octal Register Transceiver .................................... ;. .. . .. . .. .. S10-146
Non-Inverting Octal Register Transceiver ............................................ S10-146
10-Bit Non-Inverting Register .......................... ; .................... _. . .. .. S10-152
10-Bit Inverting Register ..............................•.......... , . . . . . . . . . •. ... .. S10-152
9-Bit Non-Inverting Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S10-152
9-Bit Inverting Register. . . . . . . . . . . . . . . . . .. . .. . . . . . . . . .... . . .. . . . . . . . . .. . ... •. ... .. S10-152
8-Bit Non-Inverting Register. . .... . . . . . .. .. . .. . .. . . . . . . ... . ... . . . . . . . . . . ... . .. ... .. S10-152
8-Bit Inverting Register. . ... . . . . . . ... .. . .. . .. . . . . . . . . .. . . . . . .. . .... . . .. . . .. .. . .. .. S10-152
10-Bit Non-Inverting Buffer. . . . . . . . . . . . . . .. . .. . . . . ... . .... .. .. . . . . .. . . ... ... •. . .. .. S10-158
Sviil
TABLE OF CONTENTS (CON'T.)
CONTENTS
lOT 54/74FCT828NB
lOT 54/74FCT833NB
lOT 54/74FCT834NB
lOT 54/74FCT841NB
lOT 54/74FCT842NB
lOT 54/74FCT843NB
lOT 54/74FCT844NB
lOT 54/74FCT845NB
lOT 54/74FCT846NB
lOT 54/74FCT853NB
lOT 54/74FCT854NB
lOT 54/74FCT861NB
lOT 54/74FCT862NB
lOT 54/74FCT863NB
lOT 54/74FCT864NB
lOT 54AHCT138
lOT 54AHCT139
lOT 54AHCT161
lOT 54AHCT163
lOT 54AHCT182
lOT 54AHCT191
lOT 54AHCT193
lOT 54AHCT240
lOT 54AHCT244
lOT 54AHCT245
lOT 54AHCT273
lOT 54AHCT299
lOT 54AHCT373
lOT 54AHCT374
lOT 54AHCT377
lOT 54AHCT521
lOT 54AHCT533
lOT 54AHCT534
lOT 54AHCT573
lOT 54AHCT574
lOT 54AHCT640
lOT 54AHCT645
PAGE
S10-158
S10-163
S10-163
S10-171
S10-171
S10-171
S10-171
S10-171
S10-171
S10-163
10-Bit Inverting Buffer. . . . . . . . . ... . .. ..... . . . . • . . . ... . .. ... .. . ... . ... . .. . . . . . . . . ..
8-Bit Transceiver w/Parity . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ..... .. . . ... . .... . . . . . . ..
8-Bit Transceiver w/Parity ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-Bit Non-Inverting Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . .. . . . . .. . . ..
10-Bit Inverting Latch ............................................................
9-Bit Non-Inverting Latch. . . .. . . . . . .. . . . . . .. . . . . . . .. . .... . . . . . . ... . .. . .. . . . . ... . ..
9-Bit Inverting Latch .................................................•....... ~ . ..
8-Bit Non-Inverting Latch. . . . . . . .. . .. . . . . . . . . .. . . . . . . . .. . . . . . . ... . . ... . . . . . . . . . . ..
8-Bit Inverting Latch .............................................................
8-Bit Transceiver w/Parity . . . . . . . .. . .... .. . . . . .. . . . .. . . .. ... . . . .... .... . . . . . . . .. . ..
8-Bit Transceiver w/Parity .................................. ; . . . . . . . . . . . . . . . . . . . . ..
10-Bit Non-Inverting Transceiver. .. . .. . .. . . . . . .. . . . . . . . . . ... . . . ... . ... . . . .. . . . . . . ..
10-Bit Inverting Transceiver. . . .. .. . .. . . . . . . . . .. . . . . . . . . . . .. ... ... . ... . .. .. . . . . . ...
9-Bit Non-Inverting Transceiver. . .. . .. . . .. . . . . . . . . . . . . .. . .. . ... ... . ... . .. . . . . . . . ...
9-Bit Inverting Transceiver ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-of-8 Decoder ................................................................
DuaI1-of-4 Decoder. . . . . . . . . ... . .. . . . . . . . . . . . . . . . . . . . . .. ... .. . . ... . .. . . . . . . . . ..
Synchronous Binary Counter w/Asynchronous Master Reset.. ... ... . ... . .. .. . . .... . ..
Synchronous Binary Counter w/Synchronous Reset ................................
Carry-lookahead Generator ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Up/Down Binary Counter w/Asynchronous Presetting.. . . . . .. . . . ... . ... . . . .. . . .. . . ..
Up/Down Binary Counter w/Separate Up/Down Clocks. . . . ... . . . ... . ... . . ... . . . . . . ..
Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer/Line Driver ............................................
Octal Bidirectional Transceiver... . .. . . . . . . . . . . . . . . . . . . . . . . .. . ... . ... . .. . . . . . . . . ..
Octal 0 Flip-Flop ...............................................................
Universal Shift Register .........................................................
Octal Transparent latch. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . .. . . . .... ...
Non-Inverting Octal 0 Flip-Flop ............. ;....................................
Octal 0 Flip-Flop w/Clock Enable ................................................ ".
8-Bit Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent latch. .. . . . ... . .. . . . . . . . . . . . . . . . . . . . . .. . . . ... . ... . .... . . . . . . ..
Inverting Octal 0 Flip-Flop. . . . .. . . .. . . . . . . . . . . . . . . . . . . . . .. ... . . . . ... . .. .. . . . .. ...
Octal Transparent latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . .. . . . . . . . . ..
Octal 0 Register .... ;;.........................................................
Inverting Octal Bidirectional Transceiver ..........................................
Non-Inverting Octal Bidirectional Transceiver. . . . . . .. . . . . . .. ... ... . ... . . ... . . . . . . ..
CMOS Testing Considerations .......... : ..................................... ~. . ..
Common Test Circuits and Waveforms .. ; . . . . . . . . . . . . . . ... . . . . . . . .. . . . . . . . . . . . .. . . ..
S10-178
S10-178
S10-178
S10-178
10-198
10-202
10-206
10-206
10-211
10-216
10-220
10-225
10-229
10-233
10-237
10-241
10-245
10-249
S10-184
10-257
10-261
10-265
10-269
10-273
10-281
10-285
S10-188
S10-189
Data Conversion
lOT 75C18
lOT 75C19
lOT 75MB38
lOT 75C458
. lOT 75C48
lOT 75C58
lOT 75MB58
8-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-Bit Video DAC.. .... ....... ... .......... .... .................. ........ ........
Triple 8-Bit Video DAC Module (14-266) ......................................... ,..
Triple 8-Bit PaietteDAC ™ •• ••••••• .••••••• ••••• .••••• •••••••••••••••..• .••••••• •••
8-Bit Flash ADC ................................................................
8-Bit Flash ADC w/Overflow Output ................................................
Complete Flash ADC Digitizing System Module ......................................
11-1
11-12
S11-1
S11-11
S11-24
S11-34
S11-44
ECl Products
lOT 10490
lOT 10490M
lOT 100490
lOT 10494
lOT 10494M
lOT 100494
lOT 10496LL
lOT 100496LL
lOT 10496RL
High-Speed BiCMOS ECL Static RAM 64K (64K x 1-Bit) .. .......... .... ................
High-Speed BiCMOS ECL Static RAM 64K (64K x 1-Bit) MIL-STD-883 Compliant ...........
64K (64K x 1) BiCMOS SRAM with ECL I/O ..........................................
High-Speed BiCMOS ECL Static RAM (64K (16K x 4-Bit) ...... ;........................
High-Speed BiCMOS ECL Static RAM 64K (16K x 4-Bit) MIL-STD-883 Compliant ...........
High-Speed BiCMOS ECL Static RAM 64K (16K x 4-Bit) . . . . . . . . . . . . . ... . . . . . . . . . . . . .. ..
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) STRAM ......... ;.....
High-Speed BiCMOS ECL Self-Timed Static RAM 64K (16K x 4-Bit) ......................
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) STRAM ...............
S12-1
S12-6
S12-11
S12-16
S12-21
S12-26
S12-31
S12-38
S12-45
Six
S10~163
TABLE OF CONTENTS (CON'T.)
PAGE
CONTENTS
lOT 100496Rl
lOT 10497
lOT 100497
lOT 10498
lOT 100498
lOT 10504
lOT 100504
lOT 10506ll
lOT 100506ll
lOT 10506Rl
lOT 100506Rl
lOT 10507
lOT 100507
lOT 10508
lOT 100508
Subsystems Modules
IDT7M134
IDT 7M135
IDT7M137
IDT 7M144
IDT7M145
IDT7M203
IDT7M204
IDT7M205
IDT7M206
IOT7M624
IOT7M656
IOT7M812
IOT7M912
IDT7M824
IDT7M820
IDT7M821
IDT7M822
IDT7M823
IDT7M825
IDT7M826
IDT7M827
IDT7M828
IDT7M856
IOT7M4016
IOT7M4017
IOT7M6001
IOT7M6032
IOT7M6052
IDT7MB624
lOT 7MS2001S
IOT7MS2002
IOT7MS4009
IOT7MS6036
IOT7MS6039
IOT7MS6040
IOT7MS6042
IOT7MS6043
IOT7MS6044
IOT7MS6049
IOT7MS6051
High-Speed SiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Sit) STRAM ...............
High-Speed SiCMOS ECl Static RAM 64K (16K x 4-Sit) with Synchronous Write. . . . . . . . . ...
High-Speed SiCMOS ECl Static RAM 64K (16K x 4-Sit) with Synchronous Write. . . . . . ... ...
High-Speed SiCMOS ECl Static RAM 64K (16K x 4-Sit) with Conditional Write. . . . . .. ... ...
High-Speed SiCMOS ECl Static RAM 64K (16K x 4-Sit) with Conditional Write. . . . ..... . . ..
High-Speed SiCMOS ECl Static RAM (256K (64K x 4-Sit) .;............................
High-Speed SiCMOS ECl Static RAM (256K (64K x 4-Sit) ..............................
High-Speed SiCMOS ECl Self-Timed Static RAM 256K (64K x 4-Sit) .....................
High-Speed SiCMOS ECl Self-Timed Static RAM 256K (64K x 4-Sit) .....................
High-Speed BiCMOS ECl Self-Timed Static RAM 256K (16K x 4-Bit) .....................
High-Speed BiCMOS ECl Self-Timed Static RAM 256K (16K x 4-Bit) .....................
High-Speed BiCMOS ECl Static RAM 256K (16K x 4-Bit) with Synchronous Write. . . .. .. • . ..
High-Speed BiCMOS ECl Static RAM 256K (16K x 4-Bit) with Synchronous Write. . . . . . . . . ..
High-Speed BiCMOS ECl Static RAM 256K (64K x 4-Bit) with Conditional Write. . . ..... . . ..
High-Speed BiCMOS ECl Static RAM 256K (64K x 4-Bit) with Conditional Write. . . . . . . . . . ..
S12-51
S12-57
S12-57
S12-63
S12-63
S12-70
S12-70
S12-72
S12-72
S12-74
S12-74
S12-76
S12-76
S12-78
S12-78
64K (8K x 8) Dual-Port RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
128K (16K x 8) Dual-Port RAM ...................................................
256K (32K x 8) Dual-Port RAM ...................................................
64K (8K x 8) Dual-Port RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
128K (16K x 8) Dual-Port RAM ...................................................
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Blt ...........................
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Blt ...........................
8K x 9 FIFO ...................................................................
16K x 9 FIFO ..................................................................
1 Megabit (64K x 16) CMOS SRAM ..... ...... .... . ..... ........ . ...... .... .........
256K (16K x 16) CMOS SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
512K (64K x 8) CMOS SRAM . . ......... ..... . ......... .... ............. ... .. ......
512K (64K x 9) CMOS SRAM ........... . ..... ... ...... ................. ...........
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family. . . . . . . .. ... . ..
128K x 8 SRAM w/Latched Address, latched Data In, Latched Data Out. . . . . . . . . ... ...
128K x 8 SRAM w/Latched Address, Registered Data In, Registered Data Out. . .. ... ...
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out. . . . . . . .. . ...
128K x 8 SRAM w/Latched Address, Latched Data In, Registered Data Out ............
128K x 8 SRAM w/Registered Address, Registered Data In, Registered Data Out .......
128K x 8 SRAM w/Reglstered Address, Registered Data In, Latched Data Out. . . . . . . ...
128K x 8 SRAM w/Registered Address, Latched Data In, Registered Data Out. . . . . . . . ..
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out.. . . . . . . . . . ..
256K (32K x 8-Bit) CMOS Static RAM .....................'........................
4 Megabit (256K x 16) CMOS SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2 Megabit (64K x 32) CMOS SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual, Multiplexed 16K x 20 SRAM ........ ..... ... ...... .... .... . ..... . .............
16K x 32 High-Speed Writable Control Store W/SPC™ .................................
4K x 80 Writable Control Store Static RAM Module With On-Board Sequencer. . . . . . . . ... ...
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ....................................
8K x 36 FIFO Module........ ........ . ...... ...... . .. .... .... . ..... ... ...........
36 to 9 BIFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2 (16K x 16) CMOS Static RAM FR-4 Dip Module .....................................
128K x 16 Shared Port RAM. . . . .. . . . . . .. . . . . . .. . . . . . .. . . . . . . .. . . . . . . . . . . . . .. . . . . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU. . . . . . . . . . . . . . . . . . . ..
Dual (16K x 64) Data/Instruction Cache Module For General CPUs .......................
8K x 112 High-Speed Writable Control Store w/SPC ™ .................................
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU.. . .. . . . . . . . . . . . . . . . ..
Dual (4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU.. . . . . . . . . . . . . . . . . . . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) (S14-6) ............. , ....................... , . . . .. . . . . . . . . ...
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU (Multiprocessor) ..... ...
13-125
13-125
13-135
13-142
13-142
13-146
13-146
13-157
13-157
S13-1
S13-8
S13-17
S13-17
13-168
13-172
13-175
13-178
13-181
13-184
13-187
13-190
13-193
13-63
S13-23
S13-29
S13-35
S13-41
S13-55
13-1
S13-76
S13-85
S13-92
S13-98
S13-105
S13-111
S13-117
S13-131
S13-133
Sx
S13-135
S13-138
TABLE OF CONTENTS (CON'T.)
PAGE
CONTENTS
IDT7MC156
IDT7MC4001
IDT7MC4005
IDT7MC4018
IDT7MC4032
IDT7MP156
IDT7MP456
IDT7MP564
IDT 7MP4008L
IDT7MP6025
lOT 8M612
lOT 8M624
lOT 8M628
lOT 8M656
lOT 8M824
lOT 8M856
lOT 8MP612
lOT 8MP624
IDT8MP656
IDT8MP628
lOT 8MP824
256K x 1 CMOS SRAM (Ceramic SIP) ........... " . . ... .... ..... . ... . ...... .... .....
1 Megabit (1024K x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) . . . . . . . . . . . . . . . . . . . . . ..
256K (16K x 6) CMOS Static RAM Ceramic Dual SIP Module ............... '" .... ......
64K x 6 CMOS Static RAM Ceramic SIP Module ............ , .......... ...... . ... ... ..
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ....................................
256K (256K x 1) CMOS SRAM (Plastic SIP) ..........................................
256K (64K x 4) CMOS SRAM (Plastic SIP) ...........................................
80K (16K x 5) CMOS SRAM (Plastic SIP) ..........................................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ......................................
512K (64K x 8) Synchronous SRAM (Plastic SIP) . . . . . . . . . . . .. . . . . . . . . . . .. .. . . . . . . . .. ..
S12K (32K x 16) CMOS SRAM ................ '" . ... ..... ...... .... ...... .... .....
1 Megabit (64K x 16) CMOS SRAM ...............................................
128K (8K x 16) CMOS SRAM ..... . .. . . ... . ..... . ... ..... ..... . ... ....... .... .....
256K (16Kx 16) CMOS SRAM ....................................................
1 Megabit (128K x 8) CMOS SRAM ...............................................
256K (32K x 8) Low-Power CMOS SRAM ..........................................
512K (32K x 16) CMOS SRAM (Plastic SIP) ........................................
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) ....................................
256K (16K x 16) CMOS SRAM (Plastic SIP) ..........................................
128K (8K x 16) CMOS SRAM (Plastic SIP) ...........................................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ....................................
Application and Technical Notes
Technical Notes
TN-02
Build a 20 MIP Data Processing Unit ............................................. .
TN-03
Using the IDT49C402A ALU ..................................................... .
TN-04
Using High-Speed 8K x 8 RAMs ................................................. .
TN-OS
FCT-Fast, CMOS TTL-Compatible Logic .......................................... .
TN-OS
Designing with FIFOs .......................................................... .
TN-07
Fast RAMs Give Lowest Power .................................................. .
TN-08
Operating FIFOs on Full and Empty Boundary Conditions .......................... .
TN-09
Cascading FIFOs or FIFO Modules .............................................. .
TN-l0
Dual-Port RAM Address Arbitration Metastability Testing ........................... .
TN-11
Cache Timing for the 68020 .................................................... .
TN-12
Using lOT's Video DACs in 5V Only Systems ...................................... .
TN-13
Cache Timing for the 80386 .................................................... .
TN-14
Expand Your IDT49C403 ........................................................ .
TN-16
Programmable Length Shift Registers Using RAMs and Counters ....................... .
TN-18
Using the IDT7MB6049 Cache Module ............................................. .
Application Notes
AN-Ol
Understanding the IDT7201/7202 FIFO .. ,. . . . . . . . . .. . . . .. . . . . . . . .. . ..... . . . . . .. . ..
AN-02
Dual-Port RAMs Simplify Communications in Computer Systems (Rev. 1) .. . . . . . . . . . . ..
AN-03
Trust Your Data with a High-Speed CMOS 16-, 32-, or 64-Blt EDC . . . .. . . .. . . . . . . . . . . ..
AN-04
High-Speed CMOS TTL-Compatible Number-Crunching Elements for Flxed- and
Floating-Point Arithmetic ....................................................
AN-OS
Separate I/O RAMs Increase Speed and Reduce Part Count. . . . . . . . . . ... .. . . . . . . . . ..
AN-06
16-Blt CMOS Slices - New Building Blocks Maintain Microcode Compatibility Yet
Increase Performance ......................................................
AN-07
Cache Tag RAM Chips Simplify Cache Memory Design..... ...... ........... ........
AN-08
CMOS Breathes New Life Into Bit-Slice. . . . . . . . . . . . . . . . . .. . . . . .. . . . . . .. . . . . . . . . . . ..
AN-09
Dual-Port RAMs Yield Bit-Slice Designs Without Microcode. . . . ... . . .. . .. . . . . . . . . . . ..
AN-10
Low-Power and Battery Back-Up Operation of CMOS Static RAMs. . . . . . .. . . . . . . . . . . ..
AN-11
A Powerful New Architecture for 32-Bit Bit-Slice Microprocessor .....................
AN-12
Using the IDT721264/65 Floating-Point Chip Set. . . . .. .. . .. . . . ... . . . . . .. . . . . . . . . . . ..
AN-13
The IDT49C04 32-Bit Microprogram Microprocessor....... .........................
AN-14
Dual-Port RAMs with Semaphore Arbitration. . ... . . . . .. ... .. . ... . .. . . .. . . . . . .. . . . ..
Using the IDT721 03/04 Serial-Parallel FIFO ........................................
AN-1S
Sxi
S13-140
S13-146
S13-152
S13-158
S13-164
S13-171
S13-177
13-29
S13-183
S13-189
13-92
13-92
13-99
13-99
13-107
13-113
13-74
13-74
S13-195
S13-195
13-86
14-200
14-203
14-207
14-209
14-251
14-253
14-254
14-257
14-260
14-264
14-266
14-268
S14-1
S14-4
S14-6
14-1
14-9
14-22
14-30
14-36
14-41
14-47
14-56
14-68
14-74
14-86
14-95
14-111
14-139
14-146
TABLE OF CONTENTS (CON'T.)
CONTENTS
AN-16
AN-17
AN-18
AN-19
AN-20
AN-22
AN-23
AN-24
AN-25
AN-26
AN-27
AN-28
.AN-30
SPC™ Provides Board and System Level Testing Through a Serial Scan Technique.....
FIR Filter Implementation Using FIFOs and MACs ..................................
High-Performance Controllers Need Microprogramming. . . ... . . . . . . . . .. . . . .. . . .. . . ..
RISC and the Memory Hierarchy. .. . .. . . . . ... . . . . . . . . . . . . . . .. .. . . ... .. . .. . . . . .. ....
Static RAM Timing............ ................................... .. ... ... . ......
Performance Advantages with lOT's Flagged FIFOs ...................................
High-Performance Fixed-Point Fast Fourier Transform Processor. . . . . . . . . . . . . . . . . . . . . . . ..
Designing with the IDT49C460 and IDT39C60 Error Detection and Correction Units.. . ... ...
The Key Advantages of Multi-Port Static RAMs .......................................
Interrupt Latency and Handling in the IDT79R3000 ....................................
Cache Design Considerations Using the IDT79R3000 . . . . . . . .... . . . . . . . . .. . . . . . . . . .. . ..
Using the IDT79R3000 in a Multiprocessor Organization. . .. . . . . . . .. . . .. . .. . .. . .. . .. ....
The Complete High Performance Cache System for the 80386 Microprocessor ... . . . . . . . . ..
PAGE
14-154
14-193
14-197
S14-9
S14-12
S14-26
S14-31
S14-49
S14-63
S14-67
S14-72
S14-78
S14-83
Package Diagram Outlines
Thermal Performance Calculations for lOT's Packages. . .. .. . .. . . . . .. ..... . . . .. .. . . . ..... . ... .. . .. . .. . .. . . .. S15-1
Package Diagram Outline Index ........................................................................ S15-3
Package Diagram Outlines. ..... . .. . .. . . . . .. . . . . . . . .. .. . ..... . .. . . .. . . . . .. . . . ... . . . . . . . . •. . . . . . . . . ..... S15-6
Sxll
NUMERICAL TABLE OF CONTENTS
PART#
100490
100494
100496ll
100496Rl
100497
100498
100504
100506ll
100506Rl
100507
100508
10490
10490M
10494
10494M
10496ll
10496Rl
10497
10498
10504
10506ll
10506Rl
10507
10508
29FCT52
29 FCT520
29FCT521
29FCT53
39C01
39C02
39C03
39C10
39C60
39C8XXX
49C25
49C402
49C403
49C404
49C410
49C411
49C460
49C465
49FCT601
49FCT618
49FCT661
49FCT804
49FCT818
54AHCT138
54AHCT139
54AHCT161
54AHCT163
54AHCT182
54AHCT191
54AHCT193
54AHCT240
54AHCT244
54AHCT245
54AHCT273
64K (64K x 1) 8iCMOS SRAM with ECl I/O ..........................................
High-Speed 8iCMOS ECl Static RAM (64K (16K x 4-8it) ...............................
High-Speed 8iCMOS ECl Self-Timed Static RAM 64K (16K x 4-8it) STRAM ...............
High-Speed 8iCMOS ECl Self-Timed Static RAM 64K (16K x 4-8it) STRAM ...............
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) with Synchronous Write............
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) with Conditional Write.............
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) . . . . . .. . ..... .. . .... . . . . . . . . . ..
High-Speed 8iCMOS ECl Self-Timed Static RAM 256K (64K x 4-8it) .....................
High-Speed 8iCMOS ECl Self-Timed Static RAM 256K (64K x 4-8it) .......•.............
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) with Synchronous Write...........
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) with Conditional Write............
High-Speed 8iCMOS ECl Static RAM 64K (64K x 1-8it) ...............................
High-Speed 8iCMOS ECl Static RAM 64K (64K x 1-8it) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) ................................
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) Mll-STD-883 Compliant ...........
High-Speed 8iCMOS ECl Self-Timed Static RAM 64K (16K x 4-8it) STRAM ...............
High-Speed 8iCMOS ECl Self-Timed Static RAM 64K (16K x 4-8it) STRAM ...............
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) with Synchronous Write. . . . . . . . . . ..
High-Speed 8iCMOS ECl Static RAM 64K (16K x 4-8it) with Conditional Write. . . . . . . . . . . ..
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Speed 8iCMOS ECl Self-Timed Static RAM 256K (64K x 4-8it) .....................
High-Speed 8iCMOS ECl Self-Timed Static RAM 256K (64K x 4-8it) .............'........
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) with Synchronous Write. . . . . . . . . ..
High-Speed 8iCMOS ECl Static RAM 256K (64K x 4-8it) with Conditional Write ............
Non-Inverting Octal Register Transceiver ....................•.......................
Multilevel Pipeline Register .................................... :..................
Multilevel Pipeline Register .......................................................
Inverting Octal Register Transceiver ................................................
4-Bit Microprocessor Slice (14-56) ...... ~ . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . ..
Carry-Lookahead Generator ....................... '" .............. , ... " . . .....
4-Bit Microprocessor Slice (14-56) ...................... ~ ...... , . .. .. . . . . .... ....
12-Bit Sequencer (14-56, 14-197) ................... '" . .. .. . . . . . . .. .. . . . . . . . .....
16-8it Cascadable EDC .. '......................................... , .. . .. . .. . . .. ..
IDT39C8XXX Family ............................................................
Microcycle Length Controller ....................................................
16-8it Microprocessor Slice ................................ , .. ... . .. ... .. . . . . . .• ..
16-8it Microprocessor Slice W/SPC™ ...............................................
32-Bit Microprogram Microprocessor w/SPC ...... " . ... ... .. . . . . . . .. . . . . . . . . .. ....
16-8it Sequencer ............................................................ ~ .,
20-Blt Interruptable Sequencer w/SPC ............................................
32-8it Cascadable EDC ..........................................................
32-8it CMOS Fiow-Thru Error Detection and Correction Unit. . . . . . . . . ... ... . . . . . ... . . ...
16-Blt Bidirectional Latch. . . . . . . . .. . . . . . . . . . . . . . . ..... ... .. . .. ... ... . . . . . . . ......
16-Bit Register with SPC™ ......................................................
16-Bit Synchronous Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Speed Tri-Port 8us Multiplexer ................................. ,. . . . . . ... . . . ..
Octal Register with SPCTM ........................................................
1-of-8 Decoder .............................................................•..
DuaI1-of-4 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Binary Counter w/Asynchronous Master Reset. . . . . . . . . . .. . . . . . . . .. ....
Synchronous Binary Counter w/Synchronous Reset ................................
Carry-Lookahead Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . ..
Up/Down Binary Counter w/Asynchronous Presetting ............................ , ..
Up/Down Binary Counter w/Separate Up/Down Clocks. . . . .. . .. . . .. . . .. . . . . . ... . . . ..
Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer/Line Driver ........................ ~ . . . . . . . . . . . . . . . . . ..
Octal Bidirectional Transceiver ...... " ..................•....... " .. . . . . . . . . . . . ..
Octal D Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . .. . . .. . . . .. . . .. . . ..
Sxiii
PAGE
S12-11
S12-26
S12-38
S12-51
S12-57
S12-63
S12-70
S12-72'
S12-74
S12-76
S12-78
S12-1
S12-6
S12-16
S12-21
S12-31
S12-45
S12-57
S12-63
S12-70
S12-72
S12-74
S12-76
S12-78
S10-40
S10-45
S10-45
S10-40
8-1
8-12
8-16
8-63
S8-56
10-11
8-117
S8-1
S8-13
8-182
S8-45
8-208
S8-83
sa-108
10-12
10-13
10-29
S10-51
S10-59
10-198
10-202
10-206
10-206
10-211
10-216
10-220
10-225
10-229
10-233
10-237
NUMERICAL TABLE OF CONTENTS (CON'T.)
PART#
54AHCT299
54AHCT373
54AHCT374
54AHCT377
54AHCT521
54AHCT533
54AHCT534
54AHCT573
54AHCT574
54AHCT640
54AHCT645
54/74FBT240
54/74FBT241
54/74FBT244
54/74FBT245
54/74FBT373
54/74FBT374
54/74FBT540
54/74FBT541
54/74FBT821
54/74FBT823
54/74FBT827
54/74FBT841
54/74FBT843
54/74FCT138
54/74FCT139
54/74FCT151
54/74FCT157
54/74FCT161
54/74FCT163
54/74FCT182
54/74FCT191
54/74FCT193
54/74FCT240
54/74 FCT241
54/74FCT244
54/74 FCT245
54/74FCT251
54/74FCT257
54/74FCT273
54/74FCT299
54/74FCT373
54/74 FCT374
54/74FCT377
54/74FCT399
54/74FCT521
54/74FCT533
54/74FCT534
54/74FCT540
54/74FCT541
54/74FCT543
54/74FCT573
54/74FCT574
54/74 FCT620
54/74FCT621
54/74 FCT622
54/74 FCT640
54/74FCT645
54/74 FCT646
Universal Shift Register .........................................................
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal D Flip-Flop ...................... ;...........................
Octal D Flip-Flop w/Clock Enable................................. .................
8-Blt Comparator. . . . ... .. . .. ... . . . . .. . ...... . . . . . .•.. . . . . . .. .. . ... .... . ........
Octal Transparent Latch. . . ... ... . . . . . . .. .. . . . ... . . ... . . .. . . . . .. . . .. . . .. . . ... . ...
Inverting Octal D Flip-Flop. .. . ... . ... . . . . . . . . . .. .. . . . . . .... ..... . ... . ... . . . . . . . ..
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal 0 Register ...............................................................
Inverting Octal Bidirectional Transceiver ..........................................
Non-Inverting Octal Bidirectional Transceiver. . . ... . . . . . . ... . . .. .. . . . . . . .. . . . . . . . ..
Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . ... . . . . . . ... .. .... .. . . . ... . . . .. . . ..
Non-Inverting Octal Buffer/Line Driver ............... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer/Line Driver. . . . . . . .. . . . . . . . . ... ... .. ..... . ... . .. . . . . .... ..
Non-inverting Octal Bidirectional Transceiver. ... .. . . . . . ... . .. . . . ... . . ... ... . . .. ......
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal D Flip-Flop. .. . . . . . . . . .. . . . . .. . . . . .. . ... . . . . .. . .. . . . ... .. . . ....
Inverting Octal Buffer. . . . .... . .. . . . . . . . . . . . . . . .... . . . . . ... . . . . .. . .. . . . ... . ... . . ..
Non-Inverting Octal Buffer ........................................................ '
10-Bit Non-Inverting Register.. . . . . . .. . . . . .. . . . . ... . . . . . . .. . .. . . .. . .. . . . .. . .... . . ..
10-Bit Inverting Register. ..... . . . . . .. . . . . . . . . . . .. .. . . . . . .... . . ... . .. . . . ... ... . . . ..
10-8it Non-Inverting Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-Bit Non-Inverting Latch... . . . . .... ... . . . . . . . . . . .. . .. . .. . . ..... . . . . . ... . . . . . . . ..
9-Bit Non~lnverting Latch. .. . . . . ... .. . . . . . . . .. . . . . ... . . . .. ....... . .. . . ... . . . . . . . ..
1-of-8 Decoder .................................................................
DuaI1-of-4 Decoder. . .. . . . . . . .. . . . ... . . .. ... . . . . . ... . . . . . ..... . .. . . ... . . . . .. . ..
Fast CMOS 8-lnput Multiplexer ....................................................
Fast CMOS Quad 2-lnput Multiplexer. . . . . . ...... . . . . . ... . .. . . .... . . ... . ... . . . .. . . ..
Synchronous Binary Counter w/Asynchronous Master Reset. . . ... .. ..... ... . . . . . . . ..
Synchronous Binary Counter w/Synchronous Reset ................................
Carry-Lookahead Generator. .. . .. . . . . . . . . . .. . . . .. . . . . .. . .. . . . . .. . ....... . . .. .. . . ..
Up/Down Binary Counter w/Preset and Ripple Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Up/Down Binary Counter w/Separate Up/Down Clocks. . . . ... . . . . . . ... . . . . . . ..... ...
Inverting Octal Buffer/Line Driver... . . . . . . . . ... . . . . . . . . .. . . . . . ..... .. . . . . .. . .. .. . ...
Non-Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . .... . . . . . . .... ... . . . . . ... ..
Non-Inverting Octal Bidirectional Transceiver ...... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Fast CMOS 8-lnput Multiplexer (3-State) . . . . ... . . . . . . . . ... . .. . . ..... ... . . . .. . . . .. . ...
Fast CMOS Quad 2-lnput Multiplexer.............................. .................
Octal D Flip-Flop w/Buffered Asynchronous Master Reset ..............................
Universal Shift Register w/Common Parallel I/O Pins ..................................
Octal Transparent Latch. .. . . . . . . . . .. .. . . . . . . . . . . . . . . . . . ... . . . . . . ... . . ... . . . . . . . ..
Non-Inverting Octal D Flip-Flop. .. . . . . . . . .... . .. . . . . .. . . . .. . ... . . . ... . . . . . . ..... ...
Octal D Flip-Flop w/Clock Enable....................... .......... ........ .........
Quad Dual-Port Register...... ................... . ............... .................
8-Bit Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal D Flip-Flop. . . . . . . . . . . . . . .... . . ... . . . . . . . . . . . . . . ... . .. . .. ..... ... . . . . . . . ..
Inverting Octal Buffer. . . .. . .. ... . . . . . . . . . . . . . . . . . . . . . . . . . . .... . . .. . . . . . . . .. ... ...
Non-Inverting Octal Buffer. . . . . . . .... . . . . . . . . .. . . .. . . . ..... . . . . . . ... .. . . . . . .. . . ...
Octal Latched Transceiver. . .. ... . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . ... . ..
Octal Transparent Latch ........ ~ .... . . . . . . . . . . . . . . . . . .. .. . . . . .. .. . .. . .. . . . . . . . ..
Octal D Register .............................................................. '.
Fast CMOS Octal Bus Transceiver (3-State) . . . . . . . . . . . . . .. .. . . . . . . . . .. . . . . .. . ........
Fast CMOS Octal Bus Transceiver (Open Collector) ...................................
Fast CMOS Octal Bus Transceiver (Open Collector) ...................................
Inverting Octal Bidirectional Transceiver. . . . . . . . . . . . .. . . . . .. . . . .. ... .. . .. . . . . . . . . . . ..
Octal Bidirectional Transceiver ....................................................
Non-Inverting Octal Buffer. . . . .. . .. . .. . . . . . . . . . . . . . . .. .. . . . .. . . . . .. . .. .. . . ..... . ..
Sxiv
PAGE
10-241
10-245
10-249
S10-184
10-257
10-261
10-265
10-269
10-273
10-281
10-285
S10-82
S10~86
S10-86
S10-92
S10"':105
S10-109
S10-122
S10-122
S10-152
S10-152
S10-158
S10-171
S10-171
S10-73
10-48
S10-9
S10-14
10-52
10-52
S10-77
10-62
10-67
S10-82
S10-86
S10-86
S10-92
S10-19
S10-24
S10-96
S10-100
S10-105
S10-109
S10-113
S10-117
10-113
10-117
10-121
S10-122
S10-122
S10-126
10-135
10-139
S10-29
S10-35
S10-35
S10-132
S10-136
S10-140
NUMERICAL TABLE OF CONTENTS (CON'T.)
PAGE
PART#
54/74FCT648
54/74FCT651
54/74FCT652
54/74FCT821
54/74 FCT822
54/74FCT823
54/7 4FCT824
54/7 4FCT825
54/74 FCT826
54/74 FCT827
54/7 4FCT828
54/74 FCT833
54/74FCT834
54/7 4FCT841
54/7 4FCT842
54/74 FCT843
54/74FCT844
54/7 4FCT845
54/7 4FCT846
54/74FCT853
54/74FCT854
54/7 4FCT861
54/74FCT862
54/74 FCT863
54/74 FCT864
6116
61298
61592
61593
61594
61595
6167
6168
6177
6178
61970
6198
7005
7006
7010
70101
70104
70105
7012
70121
70125
7024
7025
7050S/L
7052S/L
71256
71257
71258
71259
71281
71282
Inverting Octal Register Transceiver ................................................
Inverting Octal Register Transceiver ................................................
Non-Inverting Octal Register Transceiver.. . . .. . . . . . . . . ... . .. .. . . .. . . ... . .. . . . . . .. . ..
10-Bit Non-Inverting Register .. " .............................. '" ..... " ... . ... . ..
10-Bit Inverting Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-Bit Non-Inverting Register ... " ..... '" ...................... " ...... " . . . . . . .. ..
9-Bit Inverting Register ....... " ...... '" ..................... '" ..... " . .. . ... . ..
8-Bit Non-Inverting Register ... " . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . .. .. . . ... . ..
8-Bit Inverting Register. . . . . . . . . ... . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . .. . . .. . . . . . . . ..
10-Bit Non-Inverting Buffer .................... " .............. '" ..... " . . . . . .. . ..
10-Bit Inverting Buffer ........................................ '" . . .. . .. . . .. ... . ..
8-Bit Transceiver w/Parity . . . . . . . ... .. . . . . . .. . . . ... . . .. . . . . .. . . . . . . . .. . . . . . . . . . . . ..
8-Bit Transceiver w/Parity ............................................. " . . . . . ... ..
10-Bit Non-Inverting Latch .... " ...................................... " . . . . ... . ..
10-Bit Inverting Latch ............................................................
9-Bit Non-Inverting latch .... '" ...... '" ............ '" ...... " . . . .. . . . . . .. . ... ..
9-Bit Inverting Latch ......................................... '" ..... " . . . . . .. . ..
8-Bit Non-Inverting latch ............. " . . .. . . . .... . ... . .. . . . . . . . .. .. . .... . . . .. ...
8-Bit Inverting Latch ...............................................•.............
8-Bit Transceiver w/Parity ............................................. " . .. . .... ..
8-Bit Transceiver w/Parity . . . . . .. ... . . . . . . ... . . . . ... . ... . . . . . . . . . . . . ... .... . . . .. . ..
10-Bit Non-Inverting Transceiver ...... '" ...................... " ....•. " . . .. . . . . ..
10-Bit Inverting Transceiver .......................................................
9-Bit Non-Inverting Transceiver ................... , ............ '" ..... " . .. . . .. . ..
9-Bit Inverting Transceiver .................... " ....................•. " .. . . . .. . ..
16K (2K x 8) CMOS SRAM ........................................................
256K (64K x 4) CMOS SRAM (with Output Enable) ....................................
CMOS Synchronous Static RAM with Transparent Outputs 64K (16K x 4-Bit) ...............
CMOS Synchronous Static RAM with Output Registers 64K (16K x 4-Bit) ..................
CMOS Synchronous Static RAM with Output Registers and Output Enable 64K (16K x 4-Bit) ..
CMOS Synchronous Static RAM with Transparent Outputs and Output Enable 64K
(16K x 4-Bit) ......... ~.... ... ....... ..........................•. ... .........
16K (16K x 1) CMOS SRAM (Power Down)...........................................
16K (4K x 4) CMOS SRAM (Power Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS High-Speed Static RAM Cache-Tag (4K x 4) ................................ :..
16K (4K x 4) CMOS Cache-Tag SRAM ..............................................
CM08 Static RAM With Output Enable 16K (4K x 4) ...................................
64K (16K x 4) CMOS SRAM (with Output Enable) .....................................
High-Speed 8K x 8 Dual-Port Static RAM............. ................... ............
High-Speed 16K x 8 Dual-Port Static RAM .............................•........ '" ..
High-Speed 1K x 9 Dual-Port Static RAM ............................................
High-Speed 1K x 9 Dual-Port Static RAM ............................................
High-Speed 1K x 9 Dual-Port Static RAM. . . . . .. . . . . . . . . . . . .. . . . . .. . .. .•. . . . . . . . ... ..
High-Speed 1K x 9 Dual-Port Static RAM ................ '.. ..... ......... ............
High-Speed 2K x 9 Dual-Port Static RAM ............................................
High-Speed 2K x 9 Dual-Port Static RAM ..............................•.............
High-Speed 2K x 9 Dual-Port Static RAM ............................................
High-Speed 4K x 16 Dual-Port Static RAM............................... ............
High-Speed 8K x 16 Dual-Port Static RAM ........................................ ;..
High-Speed 1K x 8 Four-Port Static RAM ............................................
High-Speed 2K x 8 Four-Port Static RAM ..............................•.............
256K (32K x 8) CMOS 8RAM (Power Down) ..........................................
256K (256K x 1) CMOS SRAM (Power Down) .........................................
256K (64K x 4) CMOS SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Speed Static RAM Organized as 32K x 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CM08 SRAM (Separate I/O-Output Follows Input at Write) .................. ............
CMOS SRAM (Separate I/O-Output High Z at Write) ...................................
Sxv
810-140
S10-146
S10-146
810-152
810-152
S10-152
810-152
810-152
810-152
S10-158
810-158
S10-163
810-163
810-171
S10-171
S10-171
810-171
810-171
810-171
810-163
810-163
S10-178
S10-178
810-178
810-178
S4-143
84-115
S4-106
84-108
84-110
84-112
S4-1
84-28
84-50
84-52
84-59
84-69
S5-103
S5-109
S5-18
S5-19
85-18
85-19
S5-51
S5-52
S5-52
S5-100
S5-106
S5-112,
S5-121
84-193
84-19
84-125
84-205
84-134
84-134
NUMERICAL TABLE OF CONTENTS (CON'T.)
PART#
7130
7132
71321
71322
7133
7134
71342
7140
7142
71421
7143
71502
71509
71564
71578
71583
71586S
71598
7164
7165
71681
71682
7169
7174
7177
7178
7186
7187
7188
7198
71981
71982
71C65
7200
7209,
7210 .
7212
7213
7216
7217
7243
7201A
72021
7202SA/LA
7203
72031
7204
72041
72045
7205
72055
7206
72103
72104
72105
72115
72125'
72131
72132,
8K (1 K x 8) Dual-Port RAM (MASTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16K (2K x 8) Dual-Port RAM (MASTER) .................. ~ .. .. . . .. . . . .. . . . . . . . .. . . . ..
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) ...................................
16K (2K x 8) Dual-Port RAM (w/Semaphores) . . . . . . . . . . . . .. ... . . .. .. . .. . . . . .. . . .. .. . ..
32K (2K x 16) Dual-Port RAM (MASTER) ... ............... ...........................
32K (4K x 8) Dual-Port RAM. . . . . . . . . . . . . . . . . . .. . . . . . . .. ... . . .... . ..... .. . . . . . . . . ..
32K (4K x 8) Dual-Port RAM (w/Semaphores) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8K (1K x 8) Dual-Port RAM (SLAVE) ..............•.................................
16K (2K x 8) Dual-Port RAM (SLAVE) ...............................................
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) .....................................
32K (2K x 16) Dual-Port RAM (SLAVE) ..............................................
CMOS Static RAMs 64K (4K x 16-Bit) Registered RAM with SPC™ .......................
High-Speed Static RAM Organized as 32K x 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Static RAM with Latched Addresses (64K (8K x 8-Bit) ............................
CMOS Static RAM with Exclusive-OR Latched Addresses 64K (8K x 8-Bit) .................
High-Speed Static RAM Organized as 32K x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Static RAMS 64K (4K x 16-Bit) Latched Cache-RAM .............................
CMOS Static RAM with Latched Addresses 64K (16K x 4-Bit) . ...........................
64K (8K x 8) CMOS SRAM (Power Down) ...................... .".....................
64K (8K x 8) Resettable CMOS SRAM ....... ............. ........ ...... .............
16K (4K x 4) CMOS SRAM (Separate I/O-Output Fo"ows Input at Write) ..................
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) ........................
CMOS High-Speed Static RAM 8K x 9 ..............................................
64K (8K x 8) CMOS Cache-Tag SRAM ..............................................
CMOS High-Speed Static RAM Cache-Tag 16K x 4-Bit) .............................. :.
High-Speed Static RAM Cache 4K x 4 ......•.......................................
64K (4K x 16) CMOS SRAM (Power Down) ... ....... ...... ........ ...................
64K (64K x 1) CMOS SRAM (Power Down) ........... ;.... ...........................
64K (16K x 4) CMOS SRAM (Power Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K,(16K x 4) CMOS SRAM (2 CS and OE) ............. ~............................
64K (16K x 4) CMOS SRAM (Separate I/O-Output Fo"ows Input at Write) . . . . . .. . . . ... . ...
64K (16K x 4) CMOS SRAM (Separate I/O-Output High Z,at Write) ......................
64K (8K x 8) SRAM (Resettable CMOS I/O) .................... ~ ~ . . . . . . . . . . . . . . . . . . ..
256 x 9 FIFO ............................... ;. . . . . . . . .. . .. . . . . .... . . . . . . ... . . ...
12 x 12 Parallel Multiplier-Accumulator. . . ... . . . . . .. . ... .. ... . .. . . . ... . ... .. ... . . ..
16 x 16 Parallel Multiplier-Accumulator. . . . . . ... . . . .. ... .. .. . .. . . . . . . . . .. . . . .... ...
12 x 12 Parallel Multiplier. . . . . . . . . . . . . ... . . . .. . . . . . . . . ... . . .. . . . . . . . . . . . . . . . . ....
12 x 12 Parallel Multiplier (Single Clock) ...........................................
16 x 16 Parallel Multiplier... ..... .. . . . . . . ... . .. . . . . ... .. ... . ... . ... ... . . ..... . . ..
16 x 16 Parallel Multiplier (32-8It Output) ..........................................
16 x 16 Parallel Multiplier-Accumulator (19-8It Output) . . . .. . . . . . . . . . . . . . . . . . . . . . . . . ..
512 x 9 FIFO. . . . . .. . .. . .. . ... .... . . . . . . .. . . . .. .. . . . . .. . .. . . . . ... . . . . . . . . . . . ....
CMOS Para"el FIFO with Flags and OE-1 K x 9, 2K X 9, 4K x' 9. . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Para"el First-In/First-Out FIFO 1024 x.9-Bit. . . . . . . . .. .. ... . .. . .. . .. . . . . ..... . ...
2K x 9 FIFO ..................... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Parallel FIFO with Flags and OE-1 Kx 9, 2K X 9, 4K x 9 . . . . . . . . . . . . . . . . . . . . . . . . ..
4K x 9 FIFO ................................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CMOS Parallel FIFO with Flags and OE-1K x 9, 2K x 9, 4K x 9........ ..................
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Bit ........ .. . . .... . ..... . . ..
CMOS Parallel First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit ...........................
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Bit ..........................
CMOS Para"el First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit ...........................
2K x 9 Parallel-Serial FIFO ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4K x 9 Parallel-Serial FIFO ............................................... . . . . . . . ..
256 x 16, 512 x 16, 1024 x 16 Para"el-to-Serial CMOS FIFO. . •. ... . .. . ... . . . . . . . .. . . ....
256 x 16, 512 x 16, 1024 x 16 Para"el-to-Serial CMOS FIFO .. .. ... ... . ... . . . . . . . . . . . ....
256 x 16, 512 x 16, 1024 x 16 Para"el-to-Serial CMOS FIFO. . • . . . . • . . . . . . . . . . . . . . . . . . . ..
2048 x 9-Bit & 4096 x 9-Bit Parallel-to-Serial CMOS FIFO.... . . ... . ... ... . . . .. . . ... .....
2048 x 9-Bit & 4096 x 9-Bit Serial to Parallel CMOS FIFO. . .. .. .. . . ... . .. . . . . . . . . . . . . ...
Sxvl
PAGE
S5-1
S5-20
S5-35
S5-53
S5-65
S5-79
S5-87
S5-1
S5-20
S5-35 ,
S5-65
S4-218
S4-207
S4-191
S4-192
S4-202
S4-242
S4-114
S4-154
S4-163
S4-39
S4-39
S4-204
S4-181
S4-65
S4-67
S4-209
S4-11
S4-78
S4-86
S4-96
S4-96
S4-172
S6-1
7-1
7-9
7-20
7-20
7-55
7-55
7-9
S6-1
S6-27
S6-14
S6-41
S6-27
S6-41
S6-27
S6-55
S6-56
S6-55·
S6-56
S6-57
S6-57
S6-83
S6-83
S6-83
S6-95
S6-109
NUMERICAL TABLE OF CONTENTS (CON'T.)
PART#
72141
72142
72215
72225
72401
72402
72403
72404
72413
7252
72520
72521
72B04
7317
7320
7321
7381
7383
7384
75C18
75C19
75C458
75C48
75C58
75MB38
75MB58
79R2000A
79R2010A
79R2020A
79R3000
79R3010
79R3020
7M134
7M135
7M137
7M144
7M145
7M203
7M204
7M205
7M206
7M820
7M821
7M822
7M823
7MS24
7MS25
7MS26
7M827
7MS28
7M856
7MB624
7M4016
7M4017
7M6001
7M6032
7M6052
7M624
2048 x 9-Bit & 4096 x 9-Bit Parallel-to-Serial CMOS FIFO ................ . . . . . . . . . . . . . ..
2048 x 9-Bit & 4096 x 9-Bit Serial to Parallel CMOS FIFO. . .. . . . .. . .. . ... .. . . . . . . . . . . . ..
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO ..................................
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO ..................................
64 x 4 FIFO with Output Enable.................. .•... .............................
64 x 4 FIFO with Output Enable............... ... ............. .....................
64 x 4 FIFO with Output Enable.................. ................... ...............
64 x 5 FIFO with Output Enable....................... ..... ........................
CMOS Parallel 64 x 5 FIFO (with Flags) .............................................
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO ..............................................
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO ..............................................
1K x 18-Bit CMOS BiFIFO ........................................................
BiCMOS Parallel First-In/First-Out FIFO 4K x 9-Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16 x 16 Parallel Multiplier (32-Bit Output) ............................................
16-Bit CMOS Multilevel Pipeline Registers ..........•................. '" . . . . . . .... ..
16-Bit CMOS Multilevel Pipeline Registers.......... ......... ......... ...............
16-Bit CMOS Cascadable ALU ....................................................
16-Bit CMOS Cascadable ALU ....................................................
16-Bit CMOS Cascadable ALU ....................................................
8-Bit Video DAC.............................. ................... ...............
9-Bit Video DAC.. ... ...... ...... ............. . .................. ...............
Triple 8-Bit PaletteDAC™ .........................................................
8-Bit Flash ADC ................................................................
8-Bit Flash ADC w/Overflow Output ................................................
Triple 8-Bit Video DAC .......................... .................. ...............
Complete Flash ADC Digitizing System............ .................. ...............
RISC CPU Processor ............................................................
RISC CPU Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RISC CPU Write Buffer ............. '" . ... . . . . . . .. . . ... . . . . . .. .... ... . .. . . ..... ..
RISC CPU Processor ............................................................
RISC Floating-Point Accelerator (FPA) ..............................................
RISC CPU Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K (SK x 8) Dual-Port RAM ........ '" ..................................... '" . ..
128K (16K x S) Dual-Port RAM ...................................................
256K (32K x 8) Dual-Port RAM ...................................................
64K (SK x 8) Dual-Port RAM ....................................... '" . .. . . .. .. . ..
12SK (16K x S) Dual-Port RAM ...................................................
CMOS Parallel In-Out FIFO Module 2K x 9-Blt & 4K x 9-Blt ...........................
CMOS Parallel In-Out FIFO Module 2K x 9-Blt & 4K x 9-Blt ...........................
8K x 9 FIFO ...................................................................
16K x 9 FIFO ..................................................................
128K x S SRAM w/Latched Address, Latched Data In, Latched Data Out ......... " . . ..
12SK x S SRAM w/Latched Address, Registered Data In, RegIstered Data Out .... " .. ..
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out.. . . . . ..... ..
128K x 8 SRAM w/Latched Address, Latched Data In, RegIstered Data Out ............
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family.. . . .. . . . . .. . ..
128K x 8 SRAM w/Reglstered Address, Registered Data In, RegIstered Data Out .......
128K x 8 SRAM w/Reglstered Address, Registered Data In, Latched Data Out .... " . ...
128K x 8 SRAM w/Reglstered Address, Latched Data In, Registered Data Out. . . ..... ..
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out. . .. . . . .... ..
256K (32K x 8-Blt) CMOS Static RAM .............................................
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ... .. .. . ... . . .. . . . . .. .. . . . . .. . .. . ...
4 Megabit (256K x 16) CMOS SRAM ................................................
2 Megabit (64K x 32) CMOS SRAM . . .. . . . . .. . . . .. . . . . . .. .. . . . . .. . .. . .. . . .. .. .. .. . ..
Dual Multiplexed 16K x 20 SRAM ..................................................
16K x 32 High-Speed Writable Control Store W/SPC™ .................................
4K x 80 Writable Control Store Static RAM Module With On-Board Sequencer.. ............
1 Megabit (64K x 16) CMOS SRAM .................................................
Sxvii
PAGE
S6-95
S6-109
S6-122
S6-122
S6-123
S6-123
$6-123
S6-123
S6-134
S6-145
S6-145
S6-165
S6-54
S7-1
S7-9
S7-9
S7-15
S7-15
S7-23
11-1
11-12
S11-11
S11-24
S11-34
S11-1
S11-44
S9-1
S9-8
S9-14
S9-20
S9-39
S9-'"52
13-125
13-125
13-135
13-142
13-142
13-146
13-146
13-157
13-157
13-172
13-175
13-178
13-181
13-168
13-184
13-187
13-190
13-193
13-63
13-1
S13-23
S13-29
S13-35
S13-41
S13-55
S13-1
NUMERICAL TABLE OF CONTENTS (CON'T.)
PART#
7M656
7M812
7M912
7MB2001S
7MB2002
7MB4009
7MB6036
7MB6039
7MB6040
7MB6042
7MB6043
7MB6049
7MB6051
7MC156
7MC4001
7MC4005
7MC4018
7MC4032
7MP156
7MP4008L
7MP456
7MP564
7MP6025
7RS201
8M612
8M624
8M628
8M656
8M824
8M856
8MP612
8MP624
8MP628
8MP656
8MP824
256K (16K x 16) CMOS SRAM ................................. , . . . . . . . . . . . . . . . . . ..
512K (64K x 8) CMOS SRAM .. .... ...... ......... ......... ...... ........ ... .......
512K (64K x 9) CMOS SRAM .. .... ...... ... ...... ..... .......... ... ........ .......
8K x 36 FIFO Module. ....... .......... ......... ... ............ ........ ... .......
36 to 9 BiFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2 (16K x 16) CMOS Static RAM FR-4 Dip Module.............. ..... .... ....... .......
128K x 16 Shared Port RAM. . . . .. . . . . . . . .. . . . ... . .. . . . . .. . . .. . . . .. . . . . . . . .. .. . .. ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU. . . . .. . . ... .. . .. ... ..
Dual (16K x 64) Data/Instruction Cache Module For General CPUs ................ .......
High-Speed Writable Control Store W/SPC™ . . .. . . . . . .. . . . . . . . . . . . . . .. . . . . . .. . .... . ..
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU.. . . . . . . . . .. .. . .. .. . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU (Multiprocessor) .......
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 (Multiprocessor) ............
256K x 1 CMOS SRAM (Ceramic SIP) ..... ... ...... ... ....................... .......
1 Megabit (1024 x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) .............. ... .......
256K (16K x 6) CMOS Static RAM Ceramic Dual SIP Module ......... .... ........ .......
64K X 6 CMOS Static RAM Ceramic SIP Module.... .............. .......... ... .......
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ....................................
256K (256K x 1) CMOS SRAM (Plastic SIP) ..........................................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ......................................
256K (64K x 4) CMOS SRAM (Plastic SIP) ...........................................
8DK (16K x 5) CMOS SRAM (Plastic SIP) Module ...................................
512K (64K x 8) Synchronous SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ... ..
R3000 MAC" Board ......... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
512K (32K x 16) CMOS SRAM Module... ... ................................ .......
1 Megabit (64K x 16) CMOS SRAM Module ........................................
128K (8Kx 16) CMOS SRAM Module..............................................
256K (16K x 16) CMOS SRAM Module... ........ ......... .... .............. .......
lMegabit (128K x 8) CMOS SRAM Module ....................... '........... .......
256K (32K x 8) Low-Power CMOS SRAM Module ...................................
512K (32K x 16) CMOS SRAM (Plastic SIP) Module .................................
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) Module ......... ; . . . . . . . . . . .. .. .. ...
128K (8K x 16) CMOS SRAM (Plastic SIP) ............................................
256K (16K x 16) CMOS SRAM (Plastic SIP) ...................... ;...................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sxviii
PAGE
S13-8
S13-17
S13-17
S13-76
S13-85
S13-92
S13-98
S13-105
S13-111
S13-117
S13-131
S13-135
S13-138
S13-140
S13-146
S13-152
S13-158
S13-164
S13-171
S13-183
S13-177
13-29
S13-189
S9-68
13-92
13-92
13-99
13-99
13-107
13-113
13-74
13-74
S13-195
S13-195
13-86
Product Selector and Cross Reference Guides
lOT PACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION
4. A device speed identifier, when applicable, is either alpha characters, such as "A" or "8", or numbers, such as 20 or 45. The
speed units, depending on the product, are in nanoseconds or
megahertz.
5. A package identifier, composed of one or two alpha characters.
The data sheet should be consulted to determine the packages
available and the package identifiers for that particular product.
6. A temperature/process identifier. The product is available in
either the commercial or military temperature range, processed
to a commercial specification, or the product is available in the
military temperature range with full. compliance to MILSTD-883. Many of IDT's products have burn-in included as part
of the standard commercial process flow.
7. A special process identifier, composed of alpha characters, is
used for products which require radiation enhancement (RE) or
tolerance (RT).
IDT's part number identifies the basic product, speed, power,
package(s) available, operating temperature and processing
grade. Each data sheet has a detailed description, using the
part number, on ordering the proper product for the user's application. The part number is comprised of a series of alpha-numeric
characters:
1. An "IDT" corporate identifier for Integrated Device Technology,
Inc.
2. A basic device part number composed of alpha-numeric
characters.
3. A device power identifier, composed of one or two alpha characters, is used to identify the power options. In most cases, the
following alpha characters are used:
"S" or "SA" is used for the standard product's power.
"L" or "LA" is used for lower power than the standard product.
Example:
lOT
XXX.. .xXX
~
X ..x
~
-2L
~
Special Process
ProcessfTemperature*
Package*
Speed
Power
Device Type*
* Field Identifier Applicable To All Products
ASSEMBLY LOCATION DESIGNATOR
MIL-STD-883C COMPLIANT DESIGNATOR
IDT uses various locations for assembly and are identified by an
alpha character in the last letter of the date code marked on the
package. Presently, the assembly location alpha character is as
follows:
A = Anam, Korea
I = USA
P = Penang, Malaysia
IDT ships military products which are compliant to the latest revision of MIL-STD-883C. Such products are identified by a "C
designation on the package. The location of this designator is
specified by internal documentation at lOT.
H
S1-1
• Fabricated with lOT's advanced CEMOSTM dual-well, oxide-isolated, ion-implanted technology with feature sizes
down to submicron.
• Proprietary ESD protection circuitry is designed into all inputs and outputs to ensure that they will withstand repeated applications of ESD stress and do not exhibit the degradation found in many other MaS or bipolar products.
• lOT products are designed, manufactured and tested to the highest standards of quality and reliability
- they begin with stringent design rules derived for use in high-reliability programs
- they are manufactured with a dedicated commitment to reliable workmanship
- rigid controls are employed throughout wafer fab, device assembly and test
• All military grade products are manufactured in compliance with the latest revision of Mll-STD-883, Class B.
• Military module assemblies are constructed using screened lOT monolithic products and receive additional
burn-in and electrical test screening to assure package integrity and mechanical reliability .
• Monolithic products are available in ceramic and plastic packages. The various packages available are DIPs,
Pin Grid Arrays, lCCs, SOICs and Flatpacks
• All products operate from a single 5V power supply.
• Inputs and outputs, depending on the product, are directly TTL, CMOS or ECl-compatible.
• Alpha-particle induced soft error protection for static RAMs.
• Latch-up protection circuitry.
• Radiation Enhanced ('RE) or Radiation Tolerant ('RT) versions of lOT products available. Parameters/Speed
options of lOT's military product data sheets are applicable for most 'RT & 'RE devices (consult factory).
• lOT has purchased/installed equipment for Total Dose testing. The lOT Total Dose Test plan exposes a sample
of die on a wafer to a particular Total Dose level. Only wafers with sampled die that pass Total Dose level test
are assembled and used for order (consult factory for more details on Total Dose sample testing).
• Radiation Enhanced devices processed on Epi wafers are qualified by lOT's Total Dose test plan sample die
testing of 10K Rads Total Dose [RADs(Si)] or greater (consult factory for higher Total Dose levels).
• Radiation Tolerant devices are qualified by lOT's Total Dose plan sample die testing of 10K Rads Total Dose
[RADs(Si)].
• Manufactured in compliance with the latest revision of Mll-STD-883, Class B or Class S.
Boldface indicates an improved lOT feature.
The availability column shows the above date when limited production quantities will be available.
CAll in the data book page column means that the data sheet has not been included in the data book; a copy,
when available, may be obtained from lOT or from its sales offices.
CMOS, MICROSLlCE, SPC, Flexishift, PaletteDAC, BiCEMOS, CacheRAM and BiFIFO are trademarks of Integrated Device
Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Company.
UNIX is a trademark of AT&T.
51-2
• R2000A and R3000 are code compatible
• Highest performance CMOS RISC processors
available
Q
• Floating Point Accelerator conforms with IEEE
754-1985 standard
Flexible architecture can be tailored to wide set of
price/performance needs
• Write-Buffer enhances CPU performance by
allowing memory "write-through" during run cycles
• Applications range from embedded control to multiprocessing systems
• R2000A available in 12.5 and 16.7MHz clock rates
• Efficient pipelining assists in obtaining an execution
rate of one instruction per cycle
• R3000 available in 16.7, 20, and 25MHz clock rates
• Optimizing compilers for C, Pascal, FORTRAN,
Ada, PU1, and Cobol
Typical
Power
(mW)
Avail.
Part Number
Description
IDT79R3000
RISC CPU Processor, 20 mips @ 25MHz, On-chip
Cache Control, Memory Management Unit, 64-Entry
Translation Lookaside Buffer, Thirty-two 32-bit General
Purpose Registers
1500
NOW
IDT79R3010
RISC Floating-Point Accelerator, 7 MFLOPS single
precision UNPACK, 4 MFLOPS double precision
UNPACK
2000
NOW
IDT79R3020
RISC CPU Write Buffer
100
NOW
IDT79R2000A
RISC CPU Processor, 10 mips @ 16.7MHz, On-chip
Cache Control, Memory Management Unit, 64-entry
Translation Lookaside Buffer, Thirty-two 32-bit
General Purpose Registers
1500
NOW
IDT79R2010A
RISC Floating-Point Accelerator, 4 MFLOPS single
precision UNPACK, 2 MFLOPS double precision
UNPACK
-
2000
NOW
IDT79R2020A
RISC CPU Write Buffer
100
NOW
R3000/2000A Development Systems
Model Number
Description
Avail.
7RS201*
R3000 NuBus Card for Macintosh, Code
development and debugging environment
for single-user
Q2'89
8104**
M/120-3 Mid-range multiple user development
system. Rated at 9 mips processing power
with 12.5MHz CPU
NOW
8102
M/120-5 Same as 8104 except rated at
12 mips with 16.7MHz CPU
NOW
8305
M/2000-6 High-end multi-user development
system with 20MHz R3000 CPU
NOW
8302
M/2000-8 Same as 8305 except rated at 20 mips with 25MHz CPU
• Note:
•• Note:
All development systems (NuBus Card and MISeries) come standard with RISClos (UNIX) and C compiler software .
Additional memory, disk peripherals, tape peripherals and interface options are available from lOT.
S1-3
- - - - - - - - - - - - .. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
R3000/2000A Software
Model Number
Description
Avail.
3103C-E
FORTRAN RISCompiler and runtimes
NOW
3104C-E
Pascal RISCompiler and runtimes
NOW
3105C-E
COBOL RISCompiler and runtimes
NOW
3106C-E
Ada RISCompiler and runtimes
NOW
3107C-E
PU1 RISCompiler and runtimes
NOW
3120C-SCR
System Programmer's Package (SPP) Source
license and software
NOW
Integrated RiSe Solutions
high-performance workstations. lOT components
typically used for cache and· memory interface in the
R3000 system include:
lOT is committed to provide a complete Integrated
RISC Solution by combining expertise in silicon process
technology with leadership products in development
systems and software. Long an industry leader in
producing the fastest Static RAMs for cache memory
application and high speed logic for memory interface,
lOT also offers a low-cost development system for
R3000 designs. An R3000 CPU board that is hosted in
the Macintosh" (P/N I0T7RS201) comes complete with
RISC/os (Mips UNIX operating system), the C language
compiler, and debugging software tools.
Cache •
Memory.
•
•
•
IDT6116
IDT71586
IDT7198
1DT7164
IDT71258
2K x 8 SRAM
4K x 16 Latch/SRAM
16K x 4 SRAM
8K x 8 SRAM
64K x 4 SRAM
Bus
.IDT74FCT373A
Interface. IDT74FCT374A
Logic
• 1DT74FCT240A
• IDT74FCT244A
.IDT74FCT646A
.IDT74FCT823A
lOT Components for Cache and Memory Interface
lOT offers a broad range of cache RAMs and
high-speed logic to complement the R2000/R3000
RISC components and provide a fully integrated
approach to RISC design. SRAMs available include
densities from 16K to 1 Megabit and feature access
times as low as 20 nanoseconds (ns) for standard
CMOS and 1Ons for BiCEMOS/ECL SRAMs.
20ns Access Time
35ns Access Time
20ns Access Time
25ns Access Time
25ns Access Time
Octal Latch
Octal Register
Octal Buffer
Octal Buffer
Bi-directional Latch
9-bit Register
RISC Subsystem Modules and Peripheral Support
lOT is introducing a number of R3000 CPU
subsystem modules as well as high-speed SRAM
cache-modules target~d for RISC-based systems.
These surface mount modules decrease motherboard
complexity and thereby decrease overall system cost.
Because lOT modules and their components are fully
tested, the need for component testing is eliminated. All
individual components are selected and tested for their
SUb-system speed-timing compatibility. Modules also
expedite system development and therefore decrease
time-to-market.
Oevices specifically developed for RISC systems
include lOT's new 71586 4K by 16 latched SRAM. This
combination device helps eliminate propagation delay
in the cache-logic interface and thereby boost system
speed. These standard and proprietary devices can be
configured by cache size and speed to match a wide
variety of applications from embedded control to
Sl-4
RISC Modules and Peripheral Components
Peripheral Support
.IDT49C460
• IDT49C465
·IDT7252
Cache Memory Modules
Standard Versions:
• IDT7MB6039
·IDT7MB6042
• IDT7MB6044
Multi processing:
CPU Communication Devices
32-bit EDC
32-bit FLOWTHRU - EDCTM
Bi-directional FIFO Peripheral Interface Card (32-bit bus to 8-bit bus)
Dual 16K x 60
Dual8K x 60
Dual4K x 60
• IDT7MB6049
• IDT7MB6051
Dual 16K x 60
Dual8Kx 60
.IDT7202
·IDT7203
·IDT7204
·IDT7205
·IDT7130
·IDT7132
1K x 9 FIFO
2Kx 9 FIFO
4Kx 9 FIFO
8K x 9 FIFO (in development)
1K x 8 Dual-Port DRAM with interrupts
2K x 8 Dual-Port SRAM
2K x 16 Dual-Port SRAM
4K x 8 Dual-Port SRAM
4K x 8 Dual-Port with Semaphores
• IDT7133
·IDT7134
·IDT71342
S1-5
-
• DESC SMD (Standard Military Drawing) program
eliminates the need for multiple source control
drawings. IC manufacturers, primes, and DOD
share the same specification format. The benefits
are improved availability to a military drawing,
stable data sheet parameters, and a listed DESC
SMD product
• SMD numbers forthe following packages
• DESC SMD numbers, pending or listed, for 64 IDT
products
-SRAM
-
-
LCC
Sidebraze DIPs
Flatpacks
Status
OESCSMO No.
6116
6167
7187
6198/7198/7188
6168
7164
71256
71682L
71256S
71258S
71258L
71257L
71257S
61298L
6116
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
LISTED
PENDING
PENDING
5962-88643
5962-89517
7130/7140
713217142
7133S/7143S
7133U7143L
LISTED
LISTED
LISTED
LISTED
7201 LA
7216L
72404
7217L
7203S
7202L
7210
72403L
LISTED
LISTED
LISTED
LISTED
PENDING
PENDING
PENDING
PENDING
39C10B/C
39C01C/D
49C460AlB
39C60/A
LISTED
LISTED
LISTED
LISTED
49C410/A
49C402/A
LISTED
PENDING
75C48
LISTED
54 FCT244/A
54FCT245/A
54FCT299
54FCT373/A
54FCT374/A
54FCT377/A
54FCT138/A
54FCT240/A
54FCT273/A
54FCT861
54FCT827AlB
54FCT841
54FCT533
54FCT182/A
54FCT821/A
54FCT645
54FCT640
54FCT534
54FCT521/A
54FCT845A1B
54FCT161/A
54FCT573
54FCT823A1B
54FCT163/A
54FCT825A1B
54 FCT863A1B
29FCT520A
54FCT646
54FCT139/A
54FCT824
LIST/PEND
LIST/PEND
LISTED
LISTED
PENDING
LIST/PEND
LIST/PEND
LIST/PEND
LIST/PEND
PENDING
PENDING
PENDING
PENDING
PENDING
LISTED
PENDING
PENDING
PENDING
PENDING
LISTED
LIST/PEND
LISTED
LISTED
LISTED
LISTED
PENDING
PENDING
PENDING
PENDING
PENDING
LOGIC
5962-87630
5962-87629
5962-86862
5962-87644
5962-87628
5962-87627
5962-87654
5962-87655
5962-87656
5962-87704
5962-87667
5962-88575
5962-88608
5962-88543
5962-88675
5962-88640
5962-88639
5962-88656
5962-88657
5962-88674
5962-88661
5962-88736
MICROSLICE
5962-87708
5962-88535
5962-88533
5962-88613
Status
OCP
5962-88743
OSP
5962-87531
5962-86873
5962-86846
5962-87686
5962-88669
5962-89536
5962-88733
5962-89523
lOT Part No.
MICROSLICE ~continued~
SMP
5962-86875
5962-87002
5962-88610
5962-88665
Cerpacks
CERDIPS
lOT Part No.
SRAM
84036
84132
5962-86015
5962-86859
5962-86705
5962-85525
5962-88552
5962-88611
5962-88662
5962-88681
5962-88545
5962-88544
5962-88725
5962-89524
5962-88740
-
• IDT has a direct modem link to DESC to minimize
turnaround time for pending SMDs
DSP
MICROSLICE
OESC SMO No.
DATA CONVERSION
HIGH SPEED FCT/FCTA LOGIC
S1-6
• Extremely fast access times
• Three-state outputs
• Low power consumption
• Available in military and commercial temperature
ranges
• 2V data retention battery backup on all low-power
devices
Part Number
Max. Speed (ns)
Com'l.
Mil.
Description
Typical
Power
(rnW)
Avail.
225
225
NOW
02'89
225
275
300
NOW
02'89
02'89
225
300
300
NOW
02'89
02'89
MONOLITHIC
IDT6167
IDT6168
IDT71681
16K (16K x 1)
16K (4K x 4)
20
15
15
12
25
20
20
15
15
12
16K (4K x 4) with separate data inputs and outputs;
outputs track inputs during write mode
25
20
20
15
12
16K (4K x 4) with separate data inputs and outputs;
outputs in high-impedence state during write mode
25
20
20
15
15
12
225
300
300
NOW
02'89
02'89
15
IDT71682
IDT6116
16K (2K x 8)
25
25
20
15
225
275
NOW
NOW
IDT7187
64K (64K x 1)
03'89
04'89
64K (16K x 4)
300
350
03'89
04'89
IDT6198
64K (16K x 4) with output enable (OE) for
added system flexibility
300
350
03'89
04'89
IDT7198
64K (16K x .1l..9utput enable (OE) and second
chip select (CS 2 ) for added system flexibility
and memory control
20
15
20
15
20
15
20
15
250
300
IDT7188
25
20
25
20
25
20
25
20
300
350
03'89
04'89
IDT71981
64K (16K x 4) with separate data inputs and
outputs; outputs track inputs during write mode
03'89
04'89
64K (16K x 4) with separate data inputs and
outputs; outputs in high-impedence state during
write mode
20
15
20
15
300
350
IDT71982
25
20
25
20
300
350
03'89
04'89
IDT7164
64K (8K x 8)
30
25
25
20
250
250
NOW
03'89
250
250
NOW
03'89
250
250
NOW
03'89
300
300
NOW
02'89
300
300
NOW
02'89
350
350
350
NOW
02'89
04'89
350
350
350
NOW
02'89
04'89
350
350
03'89
04'89
IDT7165
IDT71C65
IDT7186
IDT71586
IDT71257
IDT71258
IDT61298
64K (8K x 8) with asynchronous clear and
high-speed chip select
35
30
30
25
64K (8K x 8) with CMOS compatible I/O
35
30
30
25
64K (4K x 16)
64K (4K x 16) with address latches
45
35
35
25
45
35
35
25
256K (256K x 1)
35
35
35
30
25
35
35
35
35
30
25
30
25
256K (64K x 4)
35
256K (64K x 4) with output enable (OE)
for added system flexibility
S1-7
Max. Speed (ns)
Mil.,
Com'l.
Typical
Power
(mW)
Avail.
Part Number
Description
IDT71281
256K (64K x 4) with separate data inputs and
outputs; outputs track inputs during write mode
35
35
30
25
350
350
03'89
04'89
IDT71282
256K (64K x 4) with separate data inputs and
outputs; outputs in high-impedence state during
write mode
35
35
30
25
350
350
03'89
04'89
IDT71256
256K (32K
35
35
30
25
250
250
NOW
04'89
IDT71027
1 Megabit (1024K
45
35
500
1990
IDT71028
1 Megabit (256K
45
35
500
1990
45
35
500
1990
15
12
12
10
300
300
02'89
04'89
IDT71024
IDT6178
x8)
x 1)
x 4)
1 Megabit (128K x 8)
16K (4K x 4) cache-tag with cache address
comparator and asynchronous clear
IDT61970
16K (4K x 4) with output enable (OE)
20
15
15
12
300
300
02'89
02'89
IDT7174
64K (8K x 8) with cache address comparator,
asynchronous clear and high-speed chip select
45
35
35
25
250
250
NOW
04'89
IDT71502
64K (4K x 16) registered RAM for writable control
store use; has on-board serial load, parity,
breakpoint and trace logic
35
25
350
NOW
STANDARD RAM MODULES
For additional RAM sizes and configurations from 80K to 4 Megabit, see page 9, High-Speed CMOS Module Products
S1-8
Typical
Power
(mW)
Avail.
8
420
NOW
8
320
NOW
8
600
02'89
Max. Speed (ns)
Com'l.
Mil.
Part Number
Description
IOT10490
64K (64K x 1) with Eel 10K compatible 1/0
IOT100490
64K (64K x 1) with Eel 1OOK compatible 110
IOT10494
64K (16K x 4) with Eel 10K compatible 110
IOT100494
64K (16K x 4) with Eel 1OOK compatible 110
8
500
02'89
IOT10496Rl
64K (16K x 4) with Eel 10K compatible 1/0 and
self-timed mode (STRAM), reg. input
10
800
02'89
IOT100496Rl
64K (16K x 4) with Eel 1OOK compatible liD and
self-timed mode (STRAM), reg. input
10
700
02'89
IOT10496ll
64K (16K x 4) with Eel 10K compatible 1/0 and
self-timed mode (STRAM), latch input
10
800
2H'89
IOT100496ll
64K (16K x 4) with Eel 1OOK compatible liD and
self-timed mode (STRAM), latch input
10
700
2H'89
IOT10497
64K (16K x 4) with Eel 10K compatible 110 and
synchronous-write mode
12
800
2H'89
IOT100497
64K (16K x 4) with Eel 1OOK compatible liD and
synchronous-write mode
12
700
2H'89
IOT10498
64K (16K x 4) with Eel 10K compatible liD and
conditional-write mode
12
800
2H'89
IOT100498
64K (16K x 4) with Eel 1OOK compatible liD and
conditional-write mode
12
700
2H'89
S1-9
15
15
• 'MC' type ceramic SIP modules are constructed
using monolithic RAMs in LCC packages on a vertically mounted substrate. This packaging configuration allows for very low profile modules with high
packing density.
• High density solutions
• 'M' type ceramic RAM modules are built with monolithic RAMs in LCC packages surface mounted onto
multilayered, co-fired ceramic substrates using
lOT's high-reliability vapor phase ref low soldering
process.
• Custom solutions are available to achieve the optimum system integration and performance.
• 'MP' and 'MB' type commercial plastic modules are
built using monolithic RAMs in SMD plastic packages, surface mounted onto epoxy laminate (FR4)
substrates.
Part Number
Max. Speed (ns)
Com'l.
Mil.
Description
Typical
Power
(mW)
Avail.
35
825
NOW
35
825
NOW
STANDARD RAM MODULES
IDT8MP628
128K (8K x 16) plastic SIP RAM module
IDT8M628
128K (8K x 16) RAM module with
monolithic pinout
IDT7MP156
256K {256K x 1~ elastic SIP RAM module
IDT7MC156
256K (256K x 1) static RAM module
{ceramic SIP~
45
25
600
NOW
35
25
600
NOW
IDT7MP456
256K (64K x 4) plastic SIP RAM module
25
1200
NOW
IDT7M856
256K (32K x 8) RAM module with monolithic
pinout
40
30
950
NOW
IDT8M856
256K (32K x 8) RAM module with monolithic
pinout (low-power)
45
35
350
NOW
IDT7MC4005
256K (16K x 16) static RAM module
(ceramic SIP)
35
25
2235
NOW
IDT8MP656
256K (16K x 16) plastic SIP RAM module
35
825
NOW
IDT8M656
256K (16K x 16) RAM module with monolithic
pinout
45
35
825
NOW
IDT7M656
256K (16K x 16, 32K x 8, 64K x 4) RAM module
customer configurable organization
25
20
3200
Q2'89
IDT7M812
512K (64K x 8) RAM module offering maximum
addressable memory required by 8-bit MPs
35
25
2400
NOW
IDT7M912
512K (64K x 8) RAM module offering maximum
addressable memory required by 8-bit MPs
with parity
35
25
2700
NOW
IDT8MP612
512K (32K x 16) plastic SIP RAM module
40
875
NOW
IDT8M612
512K 932K x 16) RAM module with monolithic
pinout
50
40
750
NOW
IDT7MC4032
512K (16K x 32) RAM module with separate
I/O (ceramic dual SIP)_
35
25
1400
NOW
IDT7MC4001
1 Megabit (1 024K x 1) static RAM module
(ceramic SIP)
TBD
45
675
NOW
IDT8MP824
1 Megabit (128K x 8) plastic SIP RAM module
40
500
NOW
IDT8M824
1 Megabit (128K x 8) RAM module
with monolithic pinout
50
40
550
NOW
IDT8MP624
1 Megabit (64K x 16) plastic SIP RAM module
40
875
NOW
IDT8M624
1 Megabit (64K x 16) RAM module
with monolithic pinout
50
40
875
NOW
IDT7M624
1 Megabit (64K x 16, 128K x 8, 256K x 4) RAM
module - customer configurable organization
35
25
4800
NOW
51-10
Max. Speed (ns)
Mil.
Com'l.
Part Number
Description
IDT7MB4009
512K (2 x 16K x 16) dual banked plastic RAM
OIP module
IDT7M4017
2 Megabit (64K x 32) RAM module
IDT7MP4008
4 Megabit (512K x 8) RAM module (plastic SIP)
IDT7M4016
4 Megabit (256K x 16) RAM module
50
TBD
Typical
Power
(mW).
Avail.
25
3100
NOW
40
6200
NOW
40.
1950
NOW
45
6200
NOW
APPLICATION SPECIFIC MODULES - Synchronous RAM Modules
IDT7MP6025
512K (64K x 8) registered static RAM module
35
3500
NOW
IDT7M824
1 Megabit (128K x 8) RAM module with registered
buffered-latched address and 1/0's
60
45
1500
NOW
IDT7M6001
32K x 20 double buffered RAM module with
registered,· multiplexed address
55
45
3750
NOW
25
4500
NOW
35
8000
NOW
45
35
4125
NOW
APPLICATION SPECIFIC MODULES - Writable Control Store Modules
IDT7M6032
16K x 32 high-speed writable control store
with SPCTM
IDT7MB6042
8k x 112 hig h-speed writable control store
with SPCTM
IDT7M6052
4K x 80 high-speed writable control store with
onboard sequencer
30
APPLICATION SPECIFIC MODULES - Dual-Port Modules
IDT7M134
64K (8K x 8) dual-port RAM module
60
45
950
NOW
IDT7M144
64K (8K x 8) functions as slave with
IDT7M 134 to provide 16-bit words or wider;
pin compatible with IDT7M134
60
45
950
NOW
IDT7M135
128K (16K x 8) dual-port RAM module
60
45
1600
NOW
IDT7M145
128K (16K x 8) functions as slave with IDT7M135
to provide 16-bit words or wider; pin
compatible with IDT7M135
60
45
1600
NOW
IDT7M137
256K (32K x 8) dual-port RAM module where
on-chip arbitration is not needed
60
55
1375
NOW
IDT7MB6036
128K x 16 shared port RAM module
70
2100
02'89
10W
NOW
APPLICATION SPECIFIC MODULES - Cache Modules
IDT7MB6039
Dual (16K x 60) data and instruction cache
for MIPS R2000/R3000
25MHz
IDT7MB6040
Dual (16K x 64) general purpose cache
25MHz
10W
NOW
IDT7MB6043
Dual (8K x 60) data and instruction cache
for MIPS R2000/R3000
20MHz
TBO
CALL
IDT7MB6044
Dual (4K x 60) data and instruction cache
for MIPS R2000/R3000
20MHz
TBO
CALL
IDT7MB6049
Dual (16K x 60) data and instruction cache
for multiprocessor MIPS R2000/R3000 systems
25MHz
10W
02'89
IDT7MB6051
Dual (8K x 64) data and instruction cache
for multiprocessor MIPS R2000/R3000 systems
20MHz
TBO
CALL
S1-11
Part Number
Max. Speed (ns)
Mil.
Com'l.
Description
Typical
Power
(mW)
Avail.'
APPLICATION SPECIFIC MODULES - FIFO Modules
IDT7M203
2K x9 FIFO moduie using four IDT7201 s
50
40
550
NOW
IDT7M204
4K
x9 FIFO module using four IDT7202s
50
40
550
NOW
IDT7M205
8K x 9 FIFO module using four IDT7203s
50
40
840
NOW
IDT7M206
16K x 9 FIFO module using four IDT7204s
50
40
840
NOW
IDT7MB2001
8K x 18 BiFIFO module or
8K x 36/16K x 18 unindirectional FIFO module
40
3000
NOW
IDT7MB2002
4K x 36 to 16K x 9 BiFIFO module w/transceiver
45
3400
NOW
IDT7MB2012
4K x 36 to 16K x 9 FIFO
45
1700
NOW
IDT7MB2022
16K x 9 to 4K x 36 FIFO
45
1700
NOW
51-12
• High speed, low power
• Fully asynchronous operation from any port
• Independent read or write access to any memory
locations from any port
• Several handshaking options (busy, interrupt,
semaphores and combinations)
• Each port has separate controls, address and 1/0
• Automatic power-down feature controller by CE
• On-chip arbitration logic (except for IDT7134 and
IDT7M137)
• 2V data retention battery back-up on all low-power
devices
Part Number
Max. Speed (ns)
Mil.
Com'l.
Description
Typical
Power
(mW)
Avail.
DUAL-PORT RAMs
IDT7130
8K (1 K x 8) industry's most popular
dual-Eort SRAM
45
35
325
NOW
IDT7140
8K (1 K x 8) functions as slave with IDT7130
to provide 16-bit words or wider; pin compatible
with IDT7130
45
35
325
NOW
IDT7132
16K (2K x 8) fastest available speeds in this
industry standard product; now multiple sourced
45
35
325
NOW
IDT7142
16K (2K x 8) functions as slave with IDT7132
to provide 16-bit words or wider; pin compatible
with IDT7132
45
35
325
NOW
IDT71321
16K (2K x 8) high-speed dual-port with interrupt
output
45
35
325
NOW
IDT71421
16K (2K x 8) functions as slave with IDT71321
to provide 16-bit words or wider; pin compatible
with IDT71321
45
35
325
NOW
IDT71322
16K (2K x 8) with Semaphores
45
35
500
NOW
IDT7133
32K (2K x 16)
55
45
375
NOW
IDT7143
32K (2K x 16) functions as slave with IDT7133
to provide 32-bit words or wider
55
45
375
NOW
IDT7134
32K (4K x 8) high speed operation in systems
where on-chip arbitration is not needed
45
35
500
NOW
IDT71342
32K (4K x 8) with Semaphores
45
35
500
NOW
IDT7024
64K (4K x 16) with busy, interrupt, semaphore
and master/slave select, all on one device
45
30
750
JUL'89
IDT7005
64K (8K x 8) with busy, interrupt, semaphore
and master/slave select, all on one device
45
35
750
JUL'89
IDT7025
128K (8K x 16) industry's largest monolithic
dual-port RAM with all the handshaking operations
(busy, interrupt, semaphores and master/slave) on
one device
45
30
750
JUN'89
IDT7006
128K (16K x 8) with busy, interrupt, semaphore
and master/slave select, all on one device
45
35
750
JUL'89
FOUR-PORT RAMs
IDT7050
8K (1 K x 8) four-port SRAM offers increasedsystem performance in multiprocessor systems
that have a need to communicate in real time
35
25
750
MAY'89
IDT7052
16K (2K x 8) four-port SRAM offers added
benefits for high-speed systems in which mUltiple
access is required in the same cycle
35
25
750
APR'89
S1-13
• High speed, low power FIFO products
SYNCHRONOUS FIFOS
• TTL compatible
• Ultra high performance -
• All products MIL-STD-883 compliant
• Separate READIWRITE enable clock inputs
20ns
• Programmable almost-empty, almost-full flags
INDUSTRY STANDARD FIFOS
• Seven x9 pin-compatible versions
BIDIRECTIONAL FIFOS
• Asynchronous, simultaneous read and write
• Simple width and depth expandibility
• Matches different bus widths: 16-bit to 8-bit buses
and 32-bit to 8-bit buses
• Space efficient packaging
• REQ/ACK interface built on-chip
• Full, empty and half-full flags
• 8 programmable status flags (offset and polarity)
STANDARD X18 FIFOS
PARALLEL/SERIAL FIFOS
• x18 word widths
• Dedicated configurations in space efficient
packages
• Asynchronous, simultaneous read and write
• Multiple flags almost-full
• User configurable -
Full, empty, half-full, almost-empty,
• Multiple flags - Full, almost-full, full - 1, empty,
almost-empty, empty + 1 and half-full
FLAGGED FIFOS
• Multiple flags almost-full
PIS, SIP, PIP or SIS
• FLEXISHIF"pM allows for easy programmable serial
word widths
Full, empty, half-full, almost-empty,
• Incorporate output enable
Part Number
Max. Speed (ns)
Mil.
Com'l.
Description
Typical
Power
(mW)
Avail.
INDUSTRY STANDARD FIFOS
10172401
64 x 4 (replaces 67401)
35MHz
45MHz
175
NOW
10172402
64 x 5 (replaces 67402)
35MHz
45MHz
175
NOW
10172403
64 x 4 with OE (replaces 67403)
35MHz
45MHz
175
NOW
10172404
64 x 5 with
DE' (replaces 67404)
35MHz
45MHz
175
NOW
10172413
64 x 5 with l)E', Half-Full, Almost-Empty,
Almost-Full flags (replaces 67413)
35MHz
45MHz
300
NOW
1017200
256 x 9, 28-pin 300 mil OIP
30
25
312
NOW
1017201A
512 x 9 with Half-Full Flag
30
25
312
NOW
1017202A
1K x 9 with Half-Full Flag
30
25
312
NOW
1017203
2K x 9 with Half-Full Flag
40
35
375
NOW
1017204
4K x 9 with Half-Full Flag
40
35
375
NOW
10172B04
4K x 9 BiCEMOS with Half-Full Flag
20
15
TBO
03'89
1017205
8K x 9 Half-Full Flag
50
50
TBO
04'89
1017206
16K x 9 with Half-Full Flag
50
50
TBO
04'89
STANDARD x18 FIFOS
10172045
4K x 18 with Flags
50
50
TBO
04'89
10172055
8K x 18 with Flags
50
50
TBO
04'89
51-14
Part Number
Max. Speed (ns)
Com'l.
Mil.
Description
Typical
Power
(mW)
Avail.
FLAGGED FIFOs
IDT72021
1K x9 with Half-Full, Almost-Empty,
Almost-Full flags and OE
30
25
312
NOW
IDT72031
2K x 9 with Half-Full, Almost-Empty
Almost-Full flags and OE
40
35
375
NOW
IDT72041
4K x 9 with Half-full, Almost-Empty,
Almost-Full flags and OE
40
35
375
NOW
IDT72052
8K x 9 with Flags
50
50
TBD
04'89
IDT72062
16K x 9 with Flags
50
50
TBD
04'89
SYNCHRONOUS FIFOS
IDT72215
512 x 18 Synchronous FIFO
25
20
TBD
03'89
IDT72225
1K x 18 Synchronous FIFO
25
20
TBD
03'89
BIDIRECTIONAL FIFOs
IDT7251
512 x 18 - 1K x 9 Bidirectional FIFO
40
35
450
03'89
IDT72510
512 x 18 - 1K x 9 Bidirectional FIFO
40
35
450
03'89
IDT72511
512 x 18 - 512 x 18 Bidirectional FIFO
40
35
450
03'89
IDT7252
1K x 18 - 2K x 9 Bidirectional FIFO
40
35
350
03'89
IDT72520
1K x 18 - 2K x 9 Bidirectional FIFO
40
35
350
03'89
IDT72521
1K x 18 - 1K x 18 Bidirectional FIFO
40
35
350
03'89
IDT7MB2001
8K x 36 FIFO/SK x 18 BIFIFO
IDT7MB2002
4K x 36 to 9 BIFIFO
40
NOW
TBD
NOW
PARALLEL/SERIAL FIFOS
IDT72103
2K x 9 configurable Parallel/Serial 1/0,
multiple flags, 50MHz serial rate and
FLEX ISH IFfTM
40
35
450
NOW
IDT72104
4K x 9 configurable Parallel/Serial 1/0,
multiple flags, 50MHz serial rate and
FLEXISHIFl'M
40
35
450
NOW
IDT72105
256 x 16 Dedicated Parallel-to-Serial I/O, 50 MHz
serial shift rate, multiple flags
TBD
25
450
03'S9
IDT72115
512 x 16 Dedicated Parallel-to-Serial I/O, 50 MHz
serial shift rate, multiple flags
TBD
25
450
03'89
IDT72125
1K x 16 Dedicated Paraliel-to-SeriaII/O, 50 MHz
serial shift rate, multiple flags
TBD
25
450
03'S9
IDT72131
2K x 9 dedicated Parallel-to-Serial 1/0,
50 MHz serial rate, multiple flags and
FLEXISHIFl'M
40
35
450
APR'89
IDT72132
2K x 9 dedicated Serial-to-Parallel 1/0,
50MHz serial rate, multiple flags and
FLEXISHIFl'M
40
35
450
APR'89
IDT72141
4K x 9 dedicated Parallel-to-Serial 110,
50MHz serial rate, multiple flags and
FLEXISHIFl'M
40
35
450
NOW
IDT72142
4K x 9 dedicated Serial-to-Parallel 1/0,
50MHz serial rate, multiple flags and
FLEXISHIFl'M
40
35
450
APR'89
S1-15
• High-speed, low power OSP building blocks
PARALLEL MACs
• TTL-compatible
• All products MIL-STO-883 compliant
• Selectable accumulation, rounding, and pre-loading
• Extended product output for multiple accumulations
• Pre-load function allows output register to be
present
ADVANCED DSP BUILDING BLOCKS
• Very fast 50MHz components
• All devices perform subtraction and
double-precision addition and multiplication
• Supports both 16- and 32-bit integer formats
• Advanced ALU features for OSP performance
PARALLEL MULTIPLIERS
• Configures for easy array expansion
• User-controlled option for transparent output
register mode
• Round Control for the MSP
Part Number
Max. Speed (ns)
Com'l.
Mil.
Description
Typical
Power
(mW)
Avail.
ADVANCED DSP BUILDING BLOCKS
1017320
16-bit eight-level Pipeline Register
15
12
150
03'89
1017321
16-bit seven-level Pipeline Register
15
12
150
03'89
1017317
16 x 16-bit Parallel Multiplier with 32-bit output
25
20
250
02'89
1017381
16-bit Cascadable ALU
25
20
150
NOW
1017383
16-bit Cascadable ALU
25
20
150
NOW
MACs
1017209
12 x 12-bit, replaces TOC1 009J
55
45
200
NOW
1017210
16 x 16-bit with 35-bit output, replaces TOC1010J
30
25
225
NOW
1017243
16 x 16-bit with 19-bit output, replaces TOC1 043
55
45
225
NOW
MULTIPLIERS
1017212
12 x 12-bit, replaces MPY012H
40
35
150
NOW
1017213
12 x 12-bit with single clock architecture
40
35
150
NOW
1017216
16 x 16-bit, replaces Am29516
25
20
200
NOW
1017217
16 x 16-bit with single clock architecture,
replaces Am29517
25
20
200
NOW
S1-16
CMOS MICROPROGRAMMABLE
MICROPROCESSOR FAMILY
CMOS ERROR DETECTION AND CORRECTION
FAMILY
• IDT49C400 products offer dramatically improved
system performance through innovative
architectures
• Provides soft and hard error checking and
correcting scheme for high-density, high-reliability
memory systems
• IDT3900 products are pin-compatible, microcodecompatible, performance-enhanced AM2900 family
replacements
• Corrects all single bit errors; detects all double bit
errors
• Faster than bipolar equivalent circuits: 20-40%
faster
• Lower power than bipolar equivalent circuits:70-80% less power
• Higher output drive than bipolar equivalent circuits
Typical
Power
Part Number
Description
Max. Speed (Com'l.)
(mW)
Avail.
= 40ns
= 30ns
= 22ns
A,B addr to Y = 67ns
A,B addr to Y = 54ns
A,B, addr to Y = 47ns
125
NOW
NOW
NOW
150
NOW
NOW
350
NOW,
NOW
Q3'89
MICROPROCESSORS
IDT39C01C
IDT39C01D
IDT39C01E
4-bit JlP Slice replaces Am2901 B/C, Am29C01,
CY7C901
IDT39C03A
IDT39C03B
4-bit JlP Slice replaces Am2903/A
IDT49C402
IDT49C402A
IDT49C402B
16-bit JlP Slice, quad 2901 with 8
additional destination functions and
64 x 16 register file capacitysuperset of Am29C1 01, CY7C91 01, WSI59016
IDT49C403
IDT49C403A
16-bit JlP Slice, quad 2903/29203 with
64 x 16 register file, 40 registers, word!
byte control, byte swap and SPCTM
A,B, addr to Y = 49ns
A,B, addr to Y = 41 ns
450
NOW
NOW
IDT39C10B
IDT39C10C
12-bit Sequencer with 33-deep stack replaces Am 291 O/A, CY7C910
D to Y = 20ns
D to Y = 12ns
150
NOW
NOW
IDT49C410
IDT49C410A
16-bit Sequencer with 33-deep stack
address up to 64K microcode
D to Y = 20ns
D to Y = 12ns
150
NOW
NOW
A,B addr to Y
A,B addr to Y
A,B addr to Y
A,B, addr to Y = 37ns
A,B, addrto,Y = 28ns
SEQUENCERS
ERROR DETECTION AND CORRECTION
IDT39C60
IDT39C60-1
IDT39C60A
IDT39C60B
16-bit Cascadable EDC replaces Am2960, -1 ,A; N2960
MC74F2960, -1,A
Detect Time =
Detect Time =
Detect Time =
Detect Time
32ns
25ns
20ns
18ns
265
NOW
NOW
NOW
Q3'89
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
32-bit Cascadable EDC functional equivalent to DP8402;
AS/ALS632
Detect Time =
Detect Time =
Detect Time =
Detect Time
40ns
30ns
25ns
16ns
300
NOW
NOW
NOW
NOW
IDT49C465
32-bit Flowthru EDCTM two separate bidirectional 32-bit buses;
expandable to 64-bit
Detect Time = 20ns
100
03'89
=
=
SUPPORT CIRCUITS
IDT39C02A
IDT49C25
IDT71502
Carry Look Ahead Generator
Microcycle Length Controller
4K x 16 Registered RAM for Writable Control Store
S1-17
• High speed -
FLASH AID CONVERTERS
low power
• IDT75C48 is pin and function compatible with TRW
1048 with half the power consumption, on-chip
Error Detection and Correction, extended analog
input range and improved output characteristics
• Available in military and commercial temperature
ranges
• Produced with advanced CEMOSTM highperformance technology
• IDT75C58 has enhanced features such as overflow
output and three state control which allows stacking
two devices for 9-bit resolution
VIDEODACs
• IDT75C18 is pin and function compatible with TRW
1018 with half the power consumption
• IDT75MB58 is a complete Flash ADC module
product with input buffer amplifier. reference
voltage generator and optimized layout and
decoupling
• IDT75C19 is world's first CMOS 9-bit video DAC
• IDT75C451/7/8 PalletteDACTM is pin and function
compatible with Brooktree BT451 17/8 with reduced
power consumption and faster speed grades. MILSTD-883 compliant devices ,are available
• IDT75MB38 is a triple 8-bit, 125MHz module with
on-board voltage reference
Typical
Power
Part Number
Description
Replaces
TDC1018
(mW)
Avail.
400
NOW
400
NOW
DAC
IDT75C18
8-bit, 125MHz Video DAC with ECl inputs
IDT75C19
World's first 9-bit, 125MHz Video DAC
IDT75M838
Triple 8-bit, 125MHz Video DAC Module
TDC1318,8T109
1500
NOW
IDT75C451
Triple 4-bit, 165MHz PaletteDACTM
8T451
1000
NOW
IDT75C457
Single a-bit, 165MHz PaletteDACTM
8T457
1000
03'89
IDT75C458
Triple 8-bit, 165MHz PaletteDACTM
8T458
1000
NOW
TDC1048
ADC
IDT75C48
8-bit, 20MHz Flash ADC
500
NOW
IDT75C58
8-bit, 20MHz Flash ADC with overflow output
500
NOW
IDT75MB58
Complete Flash Module using IDT75C58
800
NOW
51-18
• FCTXXXA devices 35%-50% faster then FAS"p M
with equivalent output drive but at dramatically
lower CMOS power over full temperature and
voltage supply extremes
• Meet JEDEC Standard No. 18
• FCT devices same speed and output drive as
FAS"pMbut at dramatically lower CMOS power
• Substantially lower input current levels than
FAS"pM, ALS or 298000 (5J.LA max.)
• 54/74FCT8XXA devices same speed and output
drive as 29800, but dramatically lower CMOS
power
• JEDEC standard pinout for DIP and LCC
• Both CMOS and TTL output compatible (eliminates
need for pull-up resistors when driving CMOS static
RAMs)
• Pin-compatible with industry standard MSllogic
• Devices formerly designated 39CXXX are now
designated 54/74FCT8XXXA or 29 FCTXXXA
• 54/74FCT8XXB devices 30%-40% faster than
29800 with equivalent output drive, but at
dramatically lower CMOS power
FCTB Family of Devices
Typical
Power
(mW)
Avail.
Part Number
Description
Max. Speed (ns)
Mil.
Com'!.
IDT29FCT52B
Non-inverting Octal Registered Transceiver
8.0
7.5
10.0
NOW
IDT29FCT53B
Inverting Octal Registered Transceiver
8.0
7.5
10.0
NOW
IDT29FCT520B
Multilevel Pipeline Register
8.0
7.5
10.0
NOW
IDT54/74FCT521 B
8-Bit Comparator
7.3
5.5
10.0
NOW
IDT54/74FCT821 B
10-Bit Non-inverting Register
8.5
7.5
10.0
NOW
IDT54/74FCT823B
9-Bit Non-inverting Register
8.5
7.5
10.0
NOW
IDT54/74FCT824B
9-Bit Non-inverting Register
8.5
7.5
10.0
NOW
IDT54/74FCT825B
8-Bit Non-Inverting Register
8.5
7.5
10.0
NOW
IDT54/74FCT827B
1O-Bit Non-inverting Buffer
6.5
5.0
10.0
NOW
IDT54/74FCT833B
8-Bit Transceiver w/Parity
10.0
7.0
10.0
NOW
IDT54/74FCT841 B
10-Bit Non-inverting Latch
7.5
6.5
10.0
NOW
IDT54/74FCT843B
9-Bit Non-inverting Latch
7.5
6.5
10.0
NOW
IDT54/74FCT844B
9-Bit Inverting Latch
9.0
10.0
NOW
IDT54/74FCT845B
8-Bit Non-inverting Latch
7.5
6.5
10.0
NOW
IDT54/74FCT853B
8-Bit Transceiver w/Parity
10.0
7.0
10.0
Q3'S9
IDT54/74FCT861 B
1O-Bit Non-inverting Transceiver
6.5
6.0
10.0
NOW
IDT54/74FCTS63B
9-Bit Non-inverting Transceiver
6.5
6.0
10.0
NOW
IDT54/74FCTS64B
9-Bit Inverting Transceiver
6.5
5.5
10.0
NOW
Typical
Power
(mW)
Avail.
FCTA Family of Devices
Max. Speed (ns)
Mil.
Com'l.
Part Number
Description
IDT29FCT52A
Non-inverting Octal Registered Transceiver
11.0
10.0
10.0
NOW
IDT29FCT53A
Inverting Octal Registered Transceiver
11.0
10.0
10.0
NOW
IDT29FCT520A
Multilevel Pipeline Register
16.0
14.0
10.0
NOW
IDT49FCTS1SA
Octal Register with SPCTM
10.0
9.0
10.0
NOW
IDT54/74FCT138A
1-of-S Decoder
7.8
5.S
10.0
NOW
IDT54/74FCT139A
Dual 1-of-4 Decoder
7.8
5.9
10.0
NOW
S1-19
Typical
Power
(mW)
Avail.
Part Number
Description
Max. Speed (ns)
Mil.
Com'l.
IDT54174FCT161 A
Synchronous Binary Counter
7.5
7.2
10.0
NOW
IDT54174FCT163A
Synchronous Binary Counter
7.5
7.2
10.0
NOW
IDT54/74FCT182A
Carry Lookahead Generator
10.7
7.0
10.0
NOW
IDT54/74FCT191 A
Up/Down Binary Counter
10.5
7.8
10.0
03'89
IDT54/74FCT193A
Up/Down Binary Counter
6.9
6.5
10.0
03'89
IDT54/74FCT240A
Inverting Octal Buffer/Line Driver
5.1
4.8
10.0
NOW
IDT54/74FCT241 A
Non-inverting Octal Buffer/Line Driver
5.1
4.8
10.0
NOW
IDT54/74FCT244A
Non-inverting Octal Buffer/Line Driver
5.1
4.8
10.0
NOW
IDT54/74FCT245A
Non-inverting Buffer Transceiver
4.9
4.6
10.0
NOW
IDT54/74FCT273A
Octal D Flip-Flop
8.3
7.2
10.0
NOW
IDT54/74FCT299A
Octal Universal Shift Register
9.5
7.2
10.0
NOW
IDT54/74FCT373A
Octal Transparent Latch
5.6
5.2
10.0
NOW
IDT54/74FCT374A
Octal D Register
7.2
6.5
10.0
NOW
IDT54/74FCT377A
Octal D Flip-Flop
8.3
7.2
10.0
NOW
IDT54/74FCT399A
Ouad Dual-Port Register
7.5
7.0
10.0
NOW
IDT54/74FCT521 A
8-Bit Identity Comparator
9.5
7.2
10.0
NOW
IDT54/74FCT533A
Octal Transparent Latch
5.6
5.2
10.0
NOW
IDT54/74FCT534A
Octal D Flip-Flop
7.2
6.5
10.0
NOW
IDT54/74FCT540A
Octal Inverting Buffer/Line Driver
5.1
4.8
10.0
NOW
IDT54/74FCT541A
Octal Non-inverting Buffer/Line Driver
5.1
4.8
10.0
NOW
IDT54/74FCT543A
Non-inverting Octal Registered Transceiver
7.5
6.5
10.0
NOW
IDT54/74FCT573A
Octal Transparent Latch
5.6
5.2
10.0
NOW
IDT54/74FCT574A
Octal D Register
7.2
6.5
10.0
NOW
IDT54/74FCT640A
Octal Inverting Buffer Transceiver
5.3
5.0
10.0
NOW
IDT54/74FCT645A
Octal Non-inverting Buffer Transceiver
4.9
4.6
10.0
NOW
IDT54174FCT646A
Octal Non-inverting Transceiver/Register
7.7
6.3
10.0
02'89
IDT54/74FCT648A
Octal Inverting Transceiver/Register
6.3
5.6
10.0
02'89
IDT54/74FCT651 A
Octal Non-inverting Transceiver/Register
10.0
02'89
IDT54/74FCT652A
Octal Inverting Transceiver/Register
10.0
02'89
IDT54/74FCT821 A
10-Bit Non-inverting Register
12.0
12.0
10.0
NOW
IDT54/74FCT824A
9-Bit Non-inverting Register
12.0
12.0
10.0
NOW
IDT54/74FCT843A
9-Bit Inverting Register
12.0
12.0
10.0
NOW
IDT54/74FCT825A
8-Bit Non-inverting Register
12.0
12.0
10.0
NOW
IDT54/74FCT827A
1O-Bit Non-inverting Buffer
10.0
8.0
10.0
NOW
IDT54/74FCT833A
8-Bit Transceiver w/Parity
14.0
10.0
10.0
NOW
IDT54/74FCT841A
10-Bit Non-inverting Latch
11.0
9.5
10.0
NOW
IDT54/74FCT843A
9-Bit Non-inverting Latch
11.0
9.5
10.0
NOW
IDT54/74FCT844A
9-Bit Inverting Latch
12.0
10.0
10.0
NOW
IDT54/74FCT845A
8-Bit Non-inverting Latch
11.0
9.5
10.0
NOW
IDT54174FCT853A
8-Bit Transceiver w/Parity
14.0
10.0
10.0
03'89
IDT54/74FCT861A
1O-Bit Non-inverting Transceiver
10.0
8.0
10.0
NOW
IDT54/74FCT863A
9-Bit Non-inverting Transceiver
10.0
8.0
10.0
NOW
IDT54/74FCT864A
9-Bit Inverting Transceiver
9.5
7.5
10.0
NOW
51-20
._----------
FCT i;=amily of Devices
Max. Speed (ns)
Mil.
Com'l.
Typical
Power
(mW)
Avail.
20.0
02'89
20.0
02'89
20.0
02'89
Part Number
Description
IDT49FCT601
16-Bit Bidirectional Latch w/Byte-Swap
IDT49FCT618
16-Bit Register with SPCTM
IDT49FCT661
16-Bit Synchronous Binary Counter
IDT49FCT818
Octal Register with SPCTM
14.0
12.5
10.0
NOW
IDT54/74FCT138
1-of-8 Decoder
12.0
9.0
10.0
NOW
IDT54/74FCT139
Dual 1-of-4 Decoder
12.0
9.0
10.0
NOW
IDT54/74FCT161
Synchronous Binary Counter
11.5
11.0
10.0
NOW
IDT54/74FCT163
Synchronous Binary Counter
11.5
11.0
10.0
NOW
IDT54/74FCT182
Carry Lookahead Generator
16.5
10.0
10.0
NOW
IDT54/74FCT191
Up/Down Binary Counter
16.0
12.0
10.0
01'89
14.0
12.5
IDT54/74FCT193
Up/Down Binary Counter
10.5
10.0
10.0
01'89
IDT54/74FCT240
Inverting Octal Buffer/Line Driver
9.0
8.0
10.0
NOW
IDT54/74FCT241
Non-inverting Octal Buffer/Line Driver
7.0
6.5
10.0
NOW
IDT54/75FCT244
Non-inverting Octal Buffer/Line Driver
7.0
6.5
10.0
NOW
IDT54/74FCT245
Non-inverting Buffer Transceiver
7.5
7.0
10.0
NOW
IDT54/74FCT273
Octal D Flip-Flop
15.0
13.0
10.0
NOW
IDT54/74FCT299
Octal Universal Shift Transceiver
14.0
10.0
10.0
NOW
IDT54/74FCT373
Octal Transparent Latch
8.5
8.0
10.0
NOW
IDT54/74FCT374
Octal D Register
11.0
10.0
10.0
NOW
IDT54/74FCT377
Octal D Flip-Flop
15.0
13.0
10.0
NOW
IDT54/74FCT399
Ouad Dual-Port Register
11.5
10.0
10.0
NOW
IDT54/74FCT521
8-Bit Identity Comparator
15.0
11.0
10.0
NOW
IDT54/74FCT533
Octal Transparent Latch
12.0
10.0
10.0
NOW
IDT54/74FCT534
Octal D Flip-Flop
11.0
10.0
10.0
NOW
IDT54/74FCT540
Octal Inverting Buffer/Line Driver
9.5
8.5
10.0
NOW
IDT54/74FCT541
Octal Non-inverting Buffer/Line Driver
9.0
8.0
10.0
NOW
IDT54/74FCT543
Octal Non-inverting Octal RegisteredTransceiver 10.0
8.5
10.0
NOW
NOW
IDT54/74FCT573
Octal Transparent Latch
IDT54/74FCT574
Octal D Register
IDT54/74FCT640
Octal Inverting Buffer Transceiver
8.5
8.0
10.0
11.0
10.0
10.0
NOW
8.0
7.0
10.0
NOW
NOW
IDT54/74FCT645
Octal Non-inverting Buffer Transceiver
11.0
9.5
10.0
IDT54/74FCT646
Octal Non-inverting Transceiver/Register
11.0
9.0
10.0
NOW
IDT54/74FCT648
Octal Inverting Transceiver/Register
9.0
8.0
10.0
Q2'89
IDT54/74FCT651
Octal Non-inverting Transceiver/Register
10.0
9.0
10.0
02'89
IDT54/74FCT652
Octal Inverting Transceiver/Register
10.0
9.0
10.0
02'89
S1-21
, - - - - - - - - - - - - - - - - - - - - - - - _....•,----_.
AHCT Family of Devices
Max. Speed (ns)
Com'l.
Mil.
Typical
Power
(mW)
Avail.
Part Number
Description
IDT54AHCT138
1-of-8 Decoder
27.0
3.5
NOW
IDT54AHCT139
Dual 1-of-4 Decoder
25.0
3.5
NOW
IDT54AHCT161
Synchronous Binary Counter
20.0
3.5
NOW
IDT54AHCT163
Synchronous Binary Counter
20.0
5.0
NOW
IDT54AHCT182
Carry Lookahead Generator
20.5
3.5
.NOW
IDT54AHCT191
Up/Down Binary Counter
22.0
5.0
NOW
IDT54AHCT193
Up/Down Binary Counter
19.0
3.5
NOW
IDT54AHCT240
Inverting Octal Buffer/Line Driver
12.0
3.5
NOW
IDT54AHCT244
Non-inverting Octal Buffer/Line Driver
13.0
3.5
NOW
IDT54AHCT245
Non-inverting Buffer Transceiver
15.0
3.5
NOW
IDT54AHCT273
Octal D Flip-Flop
17.0
3.5
NOW
IDT54AHCT299
Universal Shift Register
17.0
3.5
NOW
IDT54AHCT373
Octal Transparent Latch
19.0
3.5
NOW
IDT54AHCT374
Octal D Register
18.0
3.5
NOW
IDT54AHCT377
Octal D Flip-Flop
20.0
3.5
NOW
IDT54AHCT521
8-Bit Identity Comparator
17.0
3.5
NOW
IDT54AHCT533
Octal Transparent Latch
24.0
3.5
NOW
IDT54AHCT534
Octal D Flip-Flop
18.0
3.5
NOW
IDT54AHCT573
Octal Transparent Latch
15.0
3.5
NOW
IDT54AHCT574
Octal D Register
15.0
3.5
NOW
IDT54AHCT640
Octal Inverting Buffer Transceiver
14.0
3.5
NOW
IDT54AHCT645
Octal Non-inverting Buffer Transceiver
15.0
3.5
NOW
S1-22
t;)
Integrated Device1echnoIogy.lnc.
AMO
AM2167-35DC
AM2167-35LC
AM2167-35PC
AM2167-45/BRA
AM2167 -45/BUC
AM2167-45DE
AM2167 -55/BRA
AM2167 -55/BUC
AM2167-55DE
AM2167 -70/BRA
AM2167 -70/BUC
AM2167-70DE
AM2168-35DC
AM2168-35LC
AM2168-35PC
AM2168-45/BRA
AM2168-45/BUC
AM2168-45DE
AM2168-45LE
AM2168-55/BRA
AM2168-55/BUC
AM2168-55DE
AM2168-55LE
AM2168-70/BRA
AM2168-70/BUC
AM2168-70DE
AM2168-70LE
AM2169-40DC
AM2169-40LC
AM2169-40PC
AM2169-50/BRA
AM2169-50DC
AM2169-50DE
AM2169-50LE
AM2169-50PC
AM2169-70/BRA
AM2169-70DE
AM2169-70LE
AM2130-10/BUC
AM2130-10/BXC
AM2130-10DC
AM2130-10DCB
AM2130-10JC
AM2130-10LC
AM2130-10LCB
AM2130-10PC
AM2130-10PCB
AM2130-12/BUC
AM2130-12/BXC
AM2130-70/BXC
AM2130-70DC
AM2130-70DCB
AM2130-70JC
AM2130-70LC
AM2130-70LCB
AM2130-70PC
AM2130-70PCB
AM9128-12/BJA
STATIC RAM
CROSS REFERENCE GUIDE
lOT
IDT6167SA35D
IDT6167SA35L
IDT6167SA35P
IDT6167SA45DB
IDT6167SA45LB
IDT6167SA45DM
IDT6167SA55DB
IDT6167SA55LB
IOT6167SA55DM
IDT6167SA70DB
IDT6167SA70LB
IDT6167SA70DM
IDT6168SA35D
IDT6168SA35L
IDT6168SA35P
IDT6168SA45DB
IDT6168SA45LB
IDT6168SA45DM
IDT6168SA45LM
IDT6168SA55DB
IDT6168SA55LB
IDT6168SA55DM
IDT6168SA55LM
IDT6168SA70DB
IDT6168SA70LB
IDT6168SA70DM
IDT6168SA70LM
IDT6168SA20D
IDT6168SA20L
IDT6168SA20P
IDT6168SA25DB
IDT6168SA25D
IDT6168SA25DM
IDT6168SA25LM
IDT6168SA25P
IDT6168SA30DB
IDT6168SA30DM
IDT6168SA30LM
IDT7130S100L52B*
IDT7130S100CB
IDT7130S100C
IDT7130S100C
IDT7130S100J*
IDT7130S100L52*
IDT7130S100L52*
IDT7130S100P
IDT7130S100P
IDT7130S120L52B*
IDT7130S120CB
IDT7130S70CB
IDT7130S70C
IDT7130S70C
IDT7130S70J*
IDT7130S70L52*
IDT7130S70L52*
IDT7130S70P
IDT7130S70P
IDT6116SA120DB
NOTES:
A lower case ""x .... indicates the packages of the
AMD part are unknown."
All AM99 series parts have 2 Volt data retention
capability.
AMO CONT.
lOT
AMO CONT.
lOT
AM9128-12/BUC
AM9128-15/BJA
AM9128-15/BUC
AM9128-70DE
AM9128-90/BJA
AM9128-90/BUC
AM99C164-35x
AM99C164-45x
AM99C165-35x
AM99C165-45x
AM99C328-45x
AM99C328-55x
AM99C641-25DC
AM99C641-25LC
AM99C641-25PC
AM99C641-35DC
AM99C641-35LC
AM99C641-35PC
AM99C641-45/BWA
AM99C641-45/LMC
AM99C641-45DC
AM99C641-45DE
AM99C641-45LC
AM99C641-45LE
AM99C641-45PC
AM99C641-55/BWA
AM99C641-55/LMC
AM99C641-55DE
AM99C641-55LE
AM99C641-70/BWA
AM99C641-70/LMC
AM99C641-70DE
AM99C641-70LE
AM99C68-45/BRA
AM99C68-55/BRA
AM99C68-55DMB
AM99C68-70/BRA
AM99C68-70DM B
AM99CL68-45/BRA
AM99CL68-55/BRA
AM99CL68-70/BRA
AM99C88-10/BUC
AM99C88-10/BXC
AM99C88-12/BUC
AM99C88-12/BXC
AM99C88-15/BUC
AM99C88-15/BXC
AM99C88-20/BUC
AM99C88-20/BXC
AM99C88-70/BUC
AM99C88-70/BXC
AM99C88-70DE
AM99C88-70LC
AM99C88-70LE
AM99C88H-35x
AM99C88H-45/x
AM99CL88-10/BUC
AM99CL88-10/BXC
AM99CL88-12/BUC
AM99CL88-12/BXC
AM99CL88-15/BUC
AM99CL88-15/BXC
AM99CL88-70/BUC
IDT6116SA120L32B
IDT6116SA150DB
IDT6116SA150L32B
IDT6116SA70D
IDT6116SA90DB
IDT6116SA90L32B
IDT7188L35x
IDT7188L45x
IDT6198L35x
IDT6198L45x
IDT71256L45x
IDT71256L55x
IDT7187L25C
IDT7187L25L22
IDT7187L25P
IDT7187L35C
IDT7187L35L22
IDT7187L35P
IDT7187L45CB
IDT7187L45L22B
IDT7187L45C
IDT7187L45CM
IDT7187L45L22
IDT7187L45L22M
IDT7187L45P
IDT7187L55CB
IDT7187L55L22B
IDT7187L55CM
IDT7187L55L22M
IDT7187L70CB
IDT7187L70L22B
IDT7187L70CM
IDT7187L70L22M
IDT6168LA45DB
IDT6168LA55DB
IDT6168LA55DB
IDT6168LA70DB
IDT6168LA70DB
IDT6168LA45DB
IDT6168LA55DB
IDT6168LA70DB
IDT7164L100L32B
IDT7164L100DB
IDT7164L120L32B
IDT7164L120DB
IDT7164L150L32B
IDT7164L150DB
IDT7164L200DB
IDT7164L200L32B
IDT7164L70L32B
IDT7164L70DB
IDT7164L70DM
IDT7164L45L32
IDT7164L70L32M
IDT7164L35x
IDT7164L45xB
IDT7164L100L32B
IDT7164L100DB
IDT7164L120L32B
IDT7164L120DB
IDT7164L150L32B
IDT7164L150DB
IDT7164L70L32B
AMGGCL88-70/BXC
AMGGCS88-10/BUC
AM99CS88-10/BXC
AM99CS88-12/BUC
AM99CS88-12/BXC
AM99CS88-15/BUC
AMGGCS88-15/BXC
AM99CS88-20/BUC
AM99CS88-20/BXC
AM99CS88-70/BUC
AMGGCS88-70/BXC
IDT7164L70DB
IDT7164L1OOL32B
IOT7164L1000B
IDT7164L120L32B
IDT7164L120DB
IDT7164L150L32B
IDT7164L1500B
IDT7164L2OOL32B
IDT7164L2OODB
IDT7164L70L32B
IDT7164L70DB
Sl-23
CYPRESS
lOT
CY6116-35PC
CY6116-35DC
CY6116-35LC
CY6116-35DM B
CY6116-35LMB
CY6116-45PC
CY6116-45DC
CY6116-45LC
CY6116-45DMB
CY6116-45LMB
CY6116-55DMB
CY6116-55LMB
CY7C128-25DC
CY7C128-25LC
CY7C128-25PC
CY7C128-25SC
CY7C128-35DC
CY7C128-35DMB
CY7C128-35LC
CY7C128-35LMB
CY7C128-35PC
CY7C128-35SC
CY7C128-45DC
CY7C128-45DMB
CY7C128-45LC
CY7C128-45LMB
CY7C128-45PC
CY7C128-45SC
CY7C128-55DMB
CY7C128-55LM B
CY7C130-45LC
CY7C130-45PC
CY7C130-55DC
CY7C130-55LC
CY7C130-55PC
CY7C132-35DC
CY7C132-35LC
CY7C132-35PC
CY7C132-45DC
CY7C132-45LC
CY7C132-45PC
CY7C132-55DC
CY7C132-55LC
CY7C132-55PC
CY7C140-45DC
CY7C140-45LC
CY7C140-45PC
CY7C140-55DC
CY7C140-55LC
IDT6116SA35P
IDT6116SA35D
IDT6116SA35L28
IDT6116SA35DB
IDT6116SA35L28B
IDT6116SA45P
IDT6116SA45D
IDT6116SA45L28
IDT6116SA45DB
IDT6116SA45L28B
IDT6116SA55DB
IDT6116SA55L28B
IDT6116SA25TD
IDT6116SA25L24
IDT6116SA25TP
IDT6116SA25S0
IDT6116SA35TD
IDT6116SA35TDB
IDT6116SA35L24
IDT6116SA35L24B
IDT6116SA35TP
IDT6116SA35S0
IDT6116SA45TD
IDT6116SA45TD B
IDT6116SA45L24
IDT6116SA45L24B
IDT6116SA45TP
IDT6116SA45S0
IDT6116SA55TD B
IDT6116SA55L24B
IDT7130S45L52
IDT7130S45P
IDT7130S55C
IDT7130S55L52
IDT7130S55P
IDT7132S35C
IDT7132S35L52
IDT7132S35P
IDT7132S45C
IDT7132S45L52
IDT7132S45P
IDT7132S55C
IDT7132S55L52
IDT7132S55P
IDT7140S45C
IDT7140S45L52
IDT7140S45P
IDT7140S55C
IDT7140S55L52
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
CYPRESS CONT.
lOT
CYPRESS CONT.
CV7C164L-45DMB
CV7C164L-45LC
CV7C164L-45LMB
CV7C164L-45PC
CV7C166-25DC
CV7C166-25PC
CV7C166-35DC
CV7C166-35DM B
CV7C166-35LC
CV7C166-35LMB
CV7C166-35PC
CV7C166-450C
CV7C166-450MB
CV7C166-45LC
CV7C166-45LMB
CV7C166-45PC
CV7C166L-250C
CV7C166L-25PC
CV7C166L-350C
CV7C166L-350MB
CV7C166L-35LC
CV7C166L-35LMB
CV7C166L-35PC
CV7C166L-45DC
CV7C166L-450MB
CV7C166L-45LC
CV7C166L-45LMB
CV7C166L-45PC
CV7C167-25PC
CV7C167-25DC
CV7C167-25LC
CV7C167-35PC
CV7C167 -350C
CV7C167 -35LC
CV7C167-350MB
CV7C167-35LMB
CV7C167-45LC
CV7C167-45DMB
CV7C167-45LMB
CV7C167L-250C
CV7C167L-25LC
CV7C167L-25PC
CV7C167L-350C
CV7C167L-35LC
CV7C167L-35PC
CV7C168-25DC
CV7C168-25LC
CV7C168-25PC .
CV7C168-25SC
CV7C168-350C
CV7C168-35DMB
CV7C168-35LC
CV7C168-35LM B
CV7C168-35PC
CV7C168-35SC
CV7C168-450MB
CV7C168-45LMB
CV7C168L-250C
CV7C168L-25LC
CV7C168L-25PC
CV7C168L-25SC
CV7C168L-350C
CV7C168L-35LC
CV7C168L-35PC
CV7C168L-35SC
NOTES:
CV7C169-250C
An asterisk .*. indicates the lOT part is NOT pin CV7C169-25LC
for pin compatible.
CV7C169-25PC
*The CV7C161/162 come in a 300 mil package
CV7C169-350C
vs. 400 mil 10171981/982.
CV7C169-35DMB
CV7C169-35LC
CV7C169-35LMB
CV7C169-35PC
CV7C169-40DC
CV7C169-40DMB
CV7C140-55PC
CV7C142-35DC
CV7C142-35LC
CV7C142-35PC
CV7C142-45DC
CV7C142-45LC
CV7C142-45PC
CV7C142-55DC
CV7C142-55LC
CV7C142-55PC
CV7C161-250C*
CV7C161-350C*
CV7C161-350M B*
CV7C161-35LC*
CV7C161-450C*
CV7C161-45DMB*
CV7C161-45LC*
CV7C161-45LMB*
CV7C161 L-250C*
CV7C161L-350C*
CV7C161 L-350MB*
CV7C161 L-35LC*
CV7C161 L-35LMB*
CV7C161L-45DC*
CV7C161 L-450MB*
CV7C161 L-45LC*
CV7C161L-45LMB*
CV7C162-25DC*
CV7C162-350C*
CV7C162-35LC*
CV7C162-35LM B*
CV7C162-450C*
CV7C162-45DMB*
CV7C162-45LC*
CV7C162-45LMB*
CV7C162L-250C*
CV7C162L-35DC*
CV7C162L-350MB*
CV7C162L-35LC*
CV7C162L-35LMB*
CV7C162L-450C*
CV7C162L-45DMB*
CV7C162L-45LC*
CV7C162L-45LMB*
CV7C164-25DC
CV7C164-25PC
CV7C1647"350C
CV7C164-350MB
CV7C164-35LC
CV7C164-35LM B
CV7C164-35PC
CV7C164-45DC
CV7C164-450MB
CV7C164-45LC
CV7C164-45LMB
CV7C164-45PC
CV7C164L-250C
CV7C164L-25PC
CV7C164L-350C
CV7C164L-35DMB
CV7C164L-35LC
CV7C164L-35LMB
CV7C164L-35PC
CV7C164L-450C
ID17140S55P
ID17142S35C
ID17142S35L52
ID17142S35P
ID17142S45C
ID17142S45L52
ID17142S45P
ID17142S55C
I017142S55L52
I017142S55P
I0171981S25C
I0171981S35C
I0171981S35CB
10171981 S35L
I0171981S45C
ID171981S45CB
I0171981S45L
I0171981S45LB
I0171981L25C
ID171981L35C
ID171981 L35CB
ID171981 L35L24
ID171981 L35L24B
ID17198LS45C
10171981 L45CB
ID171981 L45L24
10171981 L45L24B
ID171982S25C
I0171982S35C
I0171982S35L
I0171982S35LB
I0171982S45C
ID171982S45CB
ID171982S45L
ID171982S45LB
I0171982L25C
I0171982L35C
I0171982L35CB
I0171982L35L
I0171982L35LB
I0171982L45C
I0171982L45CB
I0171982L45L
I0171982L45LB
ID17188S25C
I017188S25P
I017188S35C
I017188S35CB
I017188S35L
I017188S35LB
I017188S35P
I017188S45C
I017188S45CB
I017188S35L
I017188S45LB
I017188S45P
ID17188L25C
I017188L25P
ID17188L35C
ID17188L35CB
I017188L35L
I017188L35LB
I017188L35P
I017188L45C
lOT
CYPRESS CONT.
IDT
ID17188L45CB
ID17188L35L
ID17188L45LB
ID17188L45P
IDT6198S25C
IDT6198S25P
IDT6198S35C
IDT6198S35CB
IOT6198S35L
IOT6198S35LB
IDT6198S35P
IDT6198S45C
IDT6198S45CB
IDT6198S45L
IDT6198S45LB
IDT6198S45P
IOT6198L25C
IOT6198L25P
IDT6198L35C
IDT6198L35CB
IDT6198L35L
IDT6198L35LB
IDT6198L35P
IDT6198L45C
IDT6198L45CB
IDT6198L45L
IDT6198L45LB
IDT6198L45P
IDT6167SA25P
IDT6167SA250
IDT6167SA25L
IDT6167SA35P
IDT6167SA35D
IDT6167SA35L
IDT6167SA35DB
IDT6167SA35LB
IDT6167SA35L
IDT6167SA450B
IDT6167SA45LB
IDT6167LA250·
IOT6167LA25L
IOT6167LA25P
IDT6167LA350
IDT6167LA35L
IDT6167LA35P
IDT6168SA250
IDT6168SA25L
IOT6168SA25P
IOT6168SA25S0
IOT6168SA350
IDT6168SA35DB
IDT6168SA35L
IDT6168SA35LB
IDT6168SA35P
IDT6168SA35S0
IOT6168SA450B
IOT6168SA45LB
IDT6168LA250
IDT6168LA25L
IOT6168LA25P
IOT6168LA25S0
IOT6168LA350
IOT6168LA35L
IOT6168LA35P
IOT6168LA35S0
IOT6168SA150
IDT6168SA15L
IOT6168SA15P
IDT6168SA20D
IDT6168SA20DB
IDT6168SA20L
IDT6168SA20LB
IDT6168SA20P
IDT6168SA20D
IDT6168SA20DB
CV7C169-40LC
CV7C169-40LMB
CV7C169-40PC
CV7C169L-25DC
CV7C169L-25LC
CV7C169L-25PC
CV7C169L-35DC
CV7C169L-35LC
CV7C169L-35PC
CV7C170-25PC
CV7C170-250C
CV7C170-35PC
CV7C170-350C
CV7C170-350MB
CV7C170-45PC
CV7C170-450C
CV7C170-45DMB
CV7C171-250C
CV7C171-25LC
CV7C171-25PC
CV7C171-350C
CV7C171-350MB
CV7C171-35LC
CV7C171-35LMB
CV7C171-35PC
CV7G171-450C
CV7C171-450MB
CV7C171-45LC
CV7C171-45LMB
CV7C171-45PC
CV7C171L-25DC
CV7C171L-25LC
CV7C171L-25PC
CV7C171L-350C
CV7C171 L-35LC
CV7C171 L-35PC
CV7C172-250C
CV7C172-25LC
CV7C172-25PC
CV7C172-350C
CV7C172-350MB
CV7C172-35LC
CV7C172-35LMB
CV7C172-35PC
CV7C172-450C
CV7C172-450MB
CV7C1.72-45LC
CV7C172-45LMB
CV7C172-45PC
CV7C172L-25DC
CV7C172L-25LC
CV7C172L-25PC
CV7C172L-350C
CV7C172L-35LC
CV7C172L-35PC
CV7C185-350C
CV7C185-35PC
CV7C185-450C
CV7C185-45DMB
CV7C185-45PC
CV7C185L-350C
CV7C185L-35PC
CV7C185L-450C
CV7C185L-450MB
CV7C185L-45PC
CV7C185L-550MB
CV7C186-350C
CV7C186-35PC
CV7C186-45DC
CV7C186-45DMB
CV7C186-45PC
CV7C186-550MB
CV7C186L-35DC
CV7C186L-35PC
CV7C186L-45DC
IDT6168SA20L
IDT6168SA20LB
IDT6168SA20P
IDT6168LA15D
IDT6168LA15L
IDT6168LA15P
IDT6168LA20D
IOT6168LA20L
IOT6168LA20P
IOT61970S25P
IOT61970S25D
IOT61970S35P
IOT61970S35D
IOT61970S35DB
IOT61970S45P
IOT61970S45D
IOT61970S45DB
I0171681SA25D
10171681 SA25L
10171681 SA25P
10171681 SA350
I0171681SA350B
10171681 SA35L
10171681 SA35LB
I0171681SA35P
I0171681SA450
I0171681SA450B
1017.1681 SA45L
I0171681SA45LB
I0171681SA45P
10171681 LA25D
I0171681LA25L
10171681 LA25P
I0171681LA35D
10171681 LA35L
I0171681LA35P
I0171682SA25D
I0171682SA25L
I0171682SA25P
I0171682SA350
I0171682SA350B
I0171682SA35L
I0171682SA35LB
I0171682SA35P
I0171682SA45D
I0171682SA450B
I0171682SA45L
I0171682SA45LB
I0171682SA45P
I0171682LA25D
I0171682LA25L
I0171682LA25P
I0171682LA350
I0171682LA35L
I0171682LA35P
I017164S35TD
I017164S35TP
I017164S45TD
I017164S45TDB
I017164S45TP
I017164L35TD
I017164L35TP
I017164L45TD
I017164L45TDB
I017164L45TP
I017164L55TDB
I017164S350
I017164S35P
I017164S450
I017164S45DB
I017164S45P
I017164S55DB
I017164L35D
I017164L35P
I017164L45D
S1-24
- - . _ .. __. _ - - - - - - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
CYPRESS CONT.
lOT
CYPRESS CONT.
lOT
EDI CONT.
lOT
CY7C186L-45DMB
CY7C186L-45PC
CY7C186L-55DMB
CY7C187-25DC
CY7C187-25PC
CY7C187 -35DC
CY7C187-35DMB
CY7C187-35LC
CY7C187-35LMB
CY7C187-35PC
CY7C187 -45DC
CY7C187-45DMB
CY7C187-45LC
CY7C187-45LMB
CY7C187-45PC
CY7C187L-25DC
CY7C187L-25PC
CY7C187L-35DC
CY7C187L-35DMB
CY7C187L-35LC
CY7C187L-35LMB
CY7C187L-35PC
CY7C187L-45DC
CY7C187L-45DMB
CY7C187L-45LC
CY7C187L-45LMB
CY7C187L-45PC
CY7C191-25PC
CY7C191-25DC
CY7C191-25LC
CY7C191-35PC CY7C191-35DC
CY7C191-35LC
CY7C191-35DMB
CY7C191-35LMB
CY7C191-45PC
CY7C191-'45DC
CY7C191-45LC
CY7C191-45DMB
CY7C191-45LM B
CY7C192-25PC
CY7C192-25DC
CY7C192-25LC
CY7C192-35PC
CY7C192-35DC
CY7C192-35LC
CY7C192-35DMB
CY7C192-35LM B
CY7C192-45PC
CY7C192,..45DC
CY7C192-45LC
CY7C192-45DM B
CY7C192-45LM B
CY7C194-25PC
CY7C194-25VC
IDT7164L45DB
IDT7164L45P
IDT7164L55DB
IDT7187S25D
IDT7187S25P
IDT7187S35D
IDT7187S35DB
IDT7187S35L22
IDT7187S35L22B
IDT7187S35P
IDT7187S45D
IDT7187S45DB
IDT7187S45L22
IDT7187S45L22B
IDT7187S45P
IDT7187L25D
IDT7187L25P
IDT7187L35D
IDT7187L35DB
IDT7187L35L22
IDT7187L35L22B
IDT7187L35P
IDT7187L45D
IDT7187L45DB
IDT7187L45L22
IDT7187L45L22B
IDT7187L45P
IDT71281S25P
IDT71281S25D
IDT71281S25L
IDT71281 S35P
IDT71281S35D.
IDT71281S35L
IDT71281 S35DB
IDT71281S35LB
IDT71281S45P
IDT71281 S45D
IDT71281S45L
IDT71281S45DB
IDT71281 S45LB
IDT71282S25P
IDT71282S25D
IDT71282S25L
IDT71282S35F:'
IDT71282S35D
IDT71282S35L
IDT71282S35DB
IDT71282S35LB
IDT71282S45P
IDT71282S45D
IDT71282S45L
IDT71282S45DB
IDT71282S45LB
IDT71258S25P
IDT71258S25Y
IDT71258S25D
IDT71258S25L
IDT71258S35P
IDT71258S35Y
IDT71258S35D
IDT71258S35L
IDT71258S35DB
IDT71258S35LB
IDT71258S45P
CY7C194-45VC
CY7C194-45DC
CY7C194-45LC
CY7C194-45DMB
CY7C194-45LMB
CY7C196-25PC
CY7C196-25VC
CY7C196-25DC
CY7C196-25LC
CY7C196-35PC
CY7C196-35VC
CY7C196-35DC
CY7C196-35LC
CY7C196-35DMB .
CY7C196-35LM B
CY7C196-45PC
CY7C196-45VC
CY7C196-45DC
CY7C196-45LC
CY7C196-45DMB
CY7C196-45LM B
CY7C197 -25PC
CY7C197-25VC
CY7C197 -25DC
CY7C197-25LC
CY7C197-35PC
CY7C197 -35VC
CY7C197 -35DC
CY7C197-35LC
CY7C197-35DMB
CY7C197-35LMB
CY7C197-45PC
CY7C197-45VC
CY7C197 -45DC
CY7C197-45LC
CY7C197-45DMB
CY7C197-45LMB
CY7C198-35PC
CY7C198-45DMB
CY7C198-45DC
CY7C198-45PC
CY7C198-55DC
CY7C198-55DMB.
CY7C198-55PC
IDT71258S45Y.
IDT71258S45D
IDT71258S45L
IDT71258S45DB
IDT71258S45LB
IDT61298S25P
IDT61298S25Y
IDT61298S25D
IDT61298S25L
IDT61298S35P
IDT61298S35Y
IDT61298S35D
IDT61298S35L
IDT61298S35DB
IDT61298S35LB
IDT61298S45P
IDT61298S45Y
IDT61298S45D
IDT61298S45L
IDT61298S45DB
IDT61298S45LB
IDT71257S25P
IDT71257S25Y
IDT71257S25D
IDT71257S25L
IDT71257S35P
IDT71257S35Y
IDT71257S35D
IDT71257S35L
IDT71257S35DB
IDT71257S35LB
IDT71257S45P
IDT71257S45Y·
IDT71257S45D
IDT71257S45L
IDT71257S45DB
IDT71257S45LB
IDT71256S35P
IDT71256S45DB
IDT71256S45D
IDT71256S45P
IDT71256S55D
IDT71256S55DB
IDT71256S55P
EDI8464C45LB
EDI8464C55LB .
EDI8802L550B
EDI8802L700B
EDI8802L850B
EDI8802L1000B
EDI8802L1200B
EDI8802L1500B
EDI8802L55LB
EDI8802L70LB
EDI8802L85LB
EDI8802L100LB
EDI8802L120LB
EDI8802L150LB
EDI8802H550B
EDI8802H700B
EDI8802H850B
ED18802H1000B
EDI8802H1200B
EDI8802H1500B
EDI8802H55LB
EDI8802H70LB
EDI8802H85LB
EDI8802H100LB
EDI8802H120LB
EDI8802H150LB
EDI8808C35CB
EDI8808C45CB
EDI8808C55CB
EDI8808C350B
EDI8808C450B
EDI8808C550B
EDI8808C35LB
ED18808C45LB
EDI8808C55LB
EDI8808C-70LPKMHR
EDI8808C-10LPKMHR
EDI8808C.,.12LPKMHR
EDI8808C-15LPKMHR
EDI8832C55CB
EDI8832C-70KMHR
EDI8832C-85KMHR
EDI8832C-10KMHR
EDI8832C.,.12KMHR
EDI8832C-15KMHR
EDI8832C55LB
EDI8832C-70JMHR
EDI8832C-85JMHR
EDI8832C-10JMHR
EDI8832C-12JMHR
EDI8832C-15JMHR
IDT71258S45LB
IDT71258S55LB
IDT6116LA55TDB
IDT6116LA70TDB
IDT6116LA85TDB
IDT6116LA90TDB
IDT6116LA120TDB
IDT6116LA150TDB
IDT6116LA55L32B
IDT6116LA70L32B
IDT6116LA85L32B
IDT6116LA90L32B
IDT6116LA120L32B
IDT6116LA150L32B
IDT6116SA55TDB
IDT6116SA70TDB
IDT6116SA85TDB
IDT6116SA90TDB
IDT6116SA120TDB
IDT6116SA150TDB
IDT6116SA55L32B
IDT6116SA70L32B
IDT6116SA85L32B
IDT6116SA90L32B
IDT6116SA120L32B
IDT6116SA150L32B
IDT7164S35DB
IDT7164S45DB
IDT7164S55DB
IDT7164S35TCB
IDT7164S45TCB
IDT7164S55TCB
IDT7164S35L32B
IDT7164S45L32B
IDT7164S55L32B
IDT7164L70DB
IDT7164L100DB
IDT7164L120DB
IDT7164L150DB
IDT71256S55DB
IDT71256S70DB
IDT71256S85DB
IDT71256S100DB
IDT71256S120DB
IDT71256S150DB
IDT71256S55L32B
IDT71256S70L32B
IDT71256S85L32B
IDT71256S100L32B
IDT71256S120L32B
IDT71256S150L32B
EDI
EDI8164C250B
EDI8164C350B
EDI8164C450B
EDI8164C550B
EDI8164P450B
EDI8164P550B
EDI8164C25LB
EDI8164C35LB
CY7C194~25DC
EDI8164C45LB
CY7C194-25LC
EDI8164C55LB
CY7C194-35PC
EDI8164P45LB
CY7C194-35VC
EDI8164P55LB
CY7C194-35DC
EDI8416C250B
CY7C194-35LC·
EDI8416C350B
CY7C194-35DM B
EDI8416C450B
CY7C194-35LM B
EDI8416C550B
CY7C194-45PC
EDI8416P250B
EDI8416P350B
NOTES:
EDI8416P450B
. An asterisk "*" indicates the IDT part is NOT pin EDI8416P550B
for pin compatible.
ED18417C350B
*The CY7C161/162 come in a 300 mil package
ED18417C450B
vs. 400 miIIDT71981/982.
ED18417C550B
EDI8417C35LB
ED18417C45LB
EDI8417C55LB
EDI8464C450B
EDI8464C550B
lOT
IDT7187S25DB
IDT7187S35DB
IDT7187S45DB
IDT7187S55DB
IDT7187L45DB
IDT7187L55DB
IDT7187S25LB
IDT7187S35LB
IDT7187S45LB
IDT7187S55LB
IDT7187L45LB
IDT7187L55LB
IDT7188S25CB
IDT7188S35CB
IDT7188S45CB
IDT7188S55CB
IDT7188L25CB
IDT7188L35CB
IDT7188L45CB
IDT7188L55CB
IDT7198S35CB
IDT7198S45CB
IDT7198S55CB
IDT7198S35LB
IDT7198S45LB
IDT7198S55LB
IDT71258S45CB
IDT71258S55CB
FUJITSU
lOT
MB81C67-35
MB81C67-45
MB81C67-45-W
MB81C67-55
MB81C67-55-W
MB81C68-35C
MB81C68-35P
MB81C68-35Z
M B81 C68,..45-W
MB81C68-45C
MB81C68-45P
MB81 C68-45Z
MBB1C68-55-W
MB81C68A-25C
MB81 C68A-25P
MBB1 C68A-25Z
MB81C68A-30C
MB81C68A-30P
MB81C68A-30Z
MB81C68A-35C
MB81C68A-35P
IDT6167SA35P
IDT6167SA35P
IDT6167SA45xM
IDT6167SA35P
IDT6167SA55xM
IDT6168SA35L
IDT6168SA35P
IDT6168SA35D
IDT6168SA45xM
IDT6168SA35L
IDT6168SA35P
IDT6168SA35D
IDT6168SA55xM
IDT6168SA25L
IDT6168SA25P
IDT6168SA25D
IDT6168SA25L
IDT6168SA25P
IDT6168SA25D
IDT6168SA35L
IDT6168SA35P
:.
S1-25
-_ ... _--------_... _..
----
STATIC RAM CROSS REFERENCE GUIDE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUJITSU CONT.
IDT
HITACHI
IDT
INMOS
lOT
MB81C68A-35Z
MB81C69A-25C
MB81C69A-25P
MB81C69A-25Z
MB81C69A-30C
MB81C69A-30P
MB81C69A-30Z
MB81C69A-35C
MB81C69A-35P
MB81C69A-35Z
MB81C71-35
MB81C71-45C
MB81C71-45Z
MB81C71-55C
MB81C71-55Z
MB81C74-25x
MB81C74-35x
MB81C75-35
MB81C75-45
MB81C75-55
MB81C78-45
MB81C78-55
MB81C78-70
MB81 C78A-35CV
MB81C78A'-35P
M B81 C78A-35PF
MB81C81-35
MB81C81-45
MB81C81-55
MB81C84-45
MB81C84-55
MB8416A-12x
MB8416A-12x
M B8416A-12x
MB8464-15-W
MB8464-15-W
MB8464-20-W
MB8464-20-W
MB8464A:"'10-W
MB8464A-10-W
MB8464A-15-W
MB8464A-15-W
MB8464A-70x
MB8464A-70x
MB8464A-70x
MB84256-10
MB84256-10
MB84256-10
IOT6168SA35D
IDT6168SA15L
IDT6168SA15P
IDT6168SA15D
IDT6168SA15L
IDT6168SA15P
IDT6168SA15D
IDT6168SA20L
IDT6168SA20P
IDT6168SA20D
IDT7187S35P
IDT7187S45L22
IDT7187S45D
IDT7187S45L22
IDT7187S45D
IDT7188S25x
IDT7188S35x
IDT7198S35P
IDT7198S45P
IDT7198S45P
IDT7164S45P
IDT7164S45P
IDT7164S45P
IDT7164S35L22
IDT7164S35P
IDT7164S35S0
IDT71257S35P
IDT71257S45P
IDT71257S55P
IDT71258S45P
IDT71258S55P
IDT6116LA45P
IDT6116LA45D
IDT6116LA45TP
IDT7164S150DM
IDT7164S150L32M
IDT7164S200DM
IDT7164S200L32M
IDT7164L100DM
IDT7164L100L32M
IDT7164L150DM
IDT7164L150L32M
IDT7164L45L32
IDT7164L45P
IDT7164L45S0
IDT71256L70L
IDT71256L70P
IDT71256L70S0
HARRIS
lOT
HM1-6516B-8
HM1-65162-8
HM1-65162B-8
HM1-65162C-8
HM1-65162S-5
HM4-65162-8
HM4-65162C-8
HM4-65162S-5
HM1-65262-8
HM1-65262B-8
HM4-65262-8
HM4-65262B-8
HM1-65642-8
HM4-65642-8
IDT6116SA120DB
IDT6116LA90DB
IDT6116LA70DB
IDT6116SA90DB
IDT6116LA45D
IDT6116LA90DB
IDT6116SA90LB
IDT6116LA45L
IDT6167SA70DB
IDT6167SA70DB
IDT6167SA70LB
IDT6167SA70LB
IDT7164L150DB
IDT7164L150L32B
HM6116-2
HM6116FP-2
HM6116LFP-2
HM6116LP-2
HM6116P-2
HM6116ALP-12
HM6116ALSP-12
HM6116AP-12
HM6116ASP-12
HM6167H-45
HM6167H-55
HM6167HCG-45
HM6167HCG-55
HM6167HLP-45
HM6167HLP-55
HM6167HP-45
HM6167HP-55
HM6168H-45
HM6168H-55
HM6168HLP-45
HM6168HLP-55
HM6168HP-45
HM6168HP-55
HM62256LFP-10SL
HM62256LFP-8
HM62256LP-10SL
HM62256LP-8
HM62256P-8
HM6264FP-10
HM6264LFP-10
HM6264LFP-10L
HM6264LP-10
HM6264LP-10L
HM6264LP-10SL
HM6264P-10
HM6264AFP-12
HM6264ALFP-12
HM6264ALSP-12
HM6264ASP-12
HM6267CG'-35
HM6267CG-45
HM6267LP-35
HM6267LP-45
HM6267P-35
HM6267P-45
HM6268LP-25
HM6268LP-35
HM6268P-25
HM6268P-35
HM6287CG-45
HM6287CG-55
HM6287CG-70
HM6287LP-45
HM6287LP-55
HM6287LP-70
HM6287P-45
HM6287P-55
HM6287P-70
HM6288P-35
HM6288P-45
HM6288P-55
HM65256AP-12
HM6716
HM6716-30
HM6787
HM6787-30
HM6787CG
HM6787CG-30
HM6788
HM6789
HM6789-30
IDT6116SA45D
IDT6116SA45F
IDT6116LA45S0
IDT6116LA45P
IDT6116SA45P
IDT6116LA45P
IDT6116LA45TP
IDT6116LA45P
IDT6116LA45TP
IDT6167SA35D
IDT6167SA35D
IDT6167SA35L
IDT6167SA35L
IDT6167LA35P
IDT6167LA35P
IDT6167SA35P
IDT6167SA35P
IDT6168SA35D
IDT6168SA35D
IDT6168LA35P
IDT6168LA35P
IDT6168SA35P
IDT6168SA35P
IDT71256L70P
IDT71256L70S0
IDT71256L70P
IDT71256L70P
IDT71256S70P
IDT7164S45S0
IDT7164L45S0
IDT7164L45S0
IDT7164L45P
IDT7164L45P
IDT7164L45P
IDT7164S45P
IDT7164S45S0
IDT7164L45S0
IDT7164L45TC
IDT7164S45TC
IDT6167SA35L
IDT6167SA35L
IDT6167LA35P
IDT6167LA35P
IDT6167SA35P
IDT6167SA35P
IDT6168LA25P
IDT6168LA35P
IDT6168SA25P
IDT6168SA35P
IDT7187S45L
IDT7187S45L
IDT7187S45L
IDT7187L45P
IDT7187L45P .
IDT7187L45P
IDT7187S45P
IDT7187S45P
IDT7187S45P
IDT7188S35P
IDT7188S45P
IDT7188S55P
IDT71256S70P
IDT6116SA25TD
IDT6116SA30TD
IDT7187S25C
IDT7187S30C
IDT7187S25L22
IDT7187S30L22
IDT7188S25C
IDT6198S25C
IDT6198S30C
IMS1400P-35
IMS1400S-45M
IMS1400S-55M
IMS1400S-70M
IMS1400W-35
IMS1400W-45M
IMS1400W-55M
IMS1400W-70M
IMS1403P-25
IMS1403P-35
IMS1403S-25
IMS1403S-35
IMS1403W-25
IMS1403W-35
IMS1420S-55M
IMS1420S-70M
IMS1420W-55M
IMS1420W-70M
IMS1423P-25
IMS1423P-35
IMS1423S-25
IMS1423S-35
IMS1423S-35M
IMS1423S-45M
IMS1423S-55M
IMS1423W-25
IMS1423W-35
IMS1423W-35M
IMS1423W-45M
IMS1423W-55M
IMS1433x-35
IMS1600S-45
IMS1600S-55M
IMS1600S-70M
IMS1600W-45
IMS1600W-55M
IMS1600W-70M
IMS1620S-45
IMS1620S-55M
IMS1620S-70M
IMS1624S-45
IMS1624S-55M
IMS1624S-70M
IMS1624W':"45
IMS1624W-55M
IMS1624W-70M
IMS1630S-45
IMS1800x-35
IMS1820P-35
IMS1820P-45
IMS1820P-55
IMS1830x-45
IDT6167SA35P
IDT6167SA45DB
IDT6167SA55DB
IDT6167SA70DB
IDT6167SA35L
IDT6167SA45LB
IDT6167SA55LB
IDT6167SA70LB
IDT6167SA25P
IDT6167SA35P
IDT6167SA25D
IDT6167SA35D
IDT6167SA25L
IDT6167SA35L
IDT6168SA55DB
IDT6168SA70DB
IDT6168SA55LB
IDT6168SA70LB
IDT6168SA25P
IDT6168SA35P
IDT6168SA25D
IDT6168SA35D
IDT6168SA35DB
IDT6168SA45DB
IDT6168SA55DB
IDT6168SA25L
IDT6168SA35L
IDT6168SA35LB
IDT6168SA45LB
IDT6168SA55LB
IDT6116SA35
IDT7187S45C
IDT7187S55CB
IDT7187S70CB
IDT7187S45L
IDT7187S55LB
IDT7187S70LB
IDT7188S45C
IDT7188S55CB
IDT7188S70CB
IDT6198S45C
IDT6198S55CB
IDT6198S70CB
IDT6198S45L
IDT6198S55LB
IDT6198S70LB
IDT7164S45D
IDT71257S35x
IDT71258S35P
IDT71258S45P
IDT71258S55P
IDT71256S45x
NOTE:
A lower case ·x" indicates the speed and/or
package of the part are unknown."
S1-26
MATRA-HARRIS
lOT
HM1-2064-2
HM1-2064-5
HM1-2064-8
HM3-2064-5
HM3-2064U-5
HM4-2064-2
HM4-2064-5
HM4.;.2064:"8
HMT-2064-5
HMT-2064U-5
HM1-6116-2
HM1-6116-5
HM1-6116-8
HM1-6116L-2
HM1-6116L-5
HM1-6116L-8
IDT7164L150DM
IDT7164L45D
IDT7164L150DB
IDT7164L45P
IDT7164L45P
IDT7164L150L32M
IDT7164L45L32
IDT7164L150L32B
IDT7164L45S0
IDT7164L45S0
IDT6116SA90DM
IDT6116SA45D
IDT6116SA120DB
IDT6116LA90DM
IDT6116LA45D
IDT6116LA120DB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
MATRA-HARRIS
CONT.
lOT
HM3-6116-5
HM3-6116L-5
HM4-6116-2
HM4-6116-5
HM4-6116-8
HM4-6116L-2
HM4-6116L-5
HM1-65161-2
HM1-65161-5
HM1-65161-8
HM3-65161-5
HM4-65161-2
HM4-65161-5
HM4-65161-8
HM1-65163-2
HM1-65163-5
HM1-65163-8
HM3-65163-5
HM4-65163-2
HM4-65163-5
HM4-65163-8
HM1-65261-2
HM1-65261-5
HM1-65261-8
HM1-65261 B-2
HM1-65261B-5
HM1-65261B-8
HM1-65261C-2
HM1-65261C-5
HM1-65261C-8
HM1-65261S-2
HM1-65261S-5
HM1-65261S-8
HM3-65261-5
HM3-65261 B-5
HM3-65261C-5
HM3-65261S-5
HM4-65261-2
HM4-65261-5
H M4-65261-8
H M4-65261 B-2
H M4-65261 B-5
H M4-65261 B-8
HM4-65261C-2
HM4-65261 C-5
HM4-65261 C-8
HM4-65261S-2
HM4-65261S-5
HM4-65261S-8
HM1-65263-2
HM1-65263-'-5
HM3-65263-5
HM4-65263-2
HM4-65263-5
HM1-65641-2
HM1-65641-5
HM1-65641-8
HM1-65641S-2
HM1-65641S-5
HM1-65641S-8
HM3-65641-5
HM4-65641-2
HM4-65641-5
HM4-65641-8
HM1-65681-2
HM1-65681-5
HM1-65681-8
IDT6116SA45P
IDT6116LA45P
IDT6116SA90L32M
IDT6116SA45l32
IDT6116SA120L32B
IDT6116LA90l32M
IDT6116LA45l32
IDT6116LA90DM
IDT6116LA45D
IDT6116LA90DB
IDT6116LA45P
IDT6116LA90L32M
IDT6116LA45L32
IDT6116LA90L32B
IDT6116LA85DM
IDT6116LA45D
IDT6116LA85DB
IDT6116LA45P
IDT6116LA55LM
IDT6116LA45L
IDT6116LA45LB
IDT6167LA85DM
IDT6167LA35D
IDT6167LA85DB
IDT6167LA70DM
IDT6167LA35D
IDT6167LA70DB
IDT6167SA100DM
IDT6167SA35D
IDT6167SA100DB
IDT6167SA70DM
IDT6167SA35D
IDT6167SA70DB
IDT6167LA35P
IDT6167LA35P
IDT6167SA35P
IDT6167SA35P
IDT6167LA85LM
IDT6167LA35L
IDT6167LA85LB
IDT6167LA70LM
IDT6167LA35L
IDT6167LA70LB
IDT6167SA 1OOLM
IDT6167SA35L
IDT6167SA100LB
IDT6167SA70LM
IDT6167SA35L
IDT6167SA70LB
IDT6167LA55DM
IDT6167LA35D
IDT6167LA35P
IDT6167LA55LM
IDT6167LA35L
IDT7164L85DM
IDT7164L45D
IDT7164L85DB
IDT7164L55DM
IDT7164L45D
IDT7164L55DB
IDT7164L45P
IDT7164L85L32M
IDT7164L45L32
IDT7164L85L32B
IDT6168LA85DM
IDT6168LA35D
IDT6168LA85DB
NOTE:
A lower case "x" indicates the speed and/or
package of the part are unknown."
MATRA-HARRIS
CONT.
IDT
HM1-65681 B-2
HM1-65681 B-5
HM1-65681C-2
HM1-65681C-5
HM1-65681C-8
HM1-65681S-2
HM1-65681S-5
HM1-65681S-8
HM3-65681-5
H M3-65681 B-5
HM3-65681C-5
HM3-65681S-5
HM4-65681-2
HM4-65681-5
HM4-65681-8
HM4-65681 B-2
H M4-65681 B-'-5
HM4-65681C-2
HM4-65681C-5
HM4-65681C-8
HM4-65681S-2
HM4-65681S-5
HM4-65681S-8
HM1-65682-2
HM1-65682-5
HM1-65682-8
HM3-65682-5
HM4-65682-2
HM4-65682-5
HM4-65682-8
HM1-65728K-5
HM1-65728M-2
HM1-65728M-5
HM1-65728M-5
HM1-65728N-2
HM1-65728N-2
HM1-65728N-5
HM1-65728N-5
HM3-65728K-5
HM3-65728M-5
HM3-65728N-5
HM4-65728K-5
HM4-65728M-2
HM1-65767H-5
HM1-65767K-2
HM1-65767K-5
HM1-65767K-8
HM1-65767M-2
HM1-65767M-5
HM1-65767M-8
HM3-65767H-5
HM3-65767K-5
HM3-65767M-5
HM4-65767H-5
HM4-65767K-2
HM4-65767K-5
HM4-65767K-8
HM4-65767M-2
HM4-65767M-5
HM4-65767M-8
HM1-65768H-5
H M1-65768K-2
HM1-65768K-5
HM1-65768K-8
HM1-65768M-2
HM1-65768M-5
H M1-65768M-8
HM3-65768H-5
HM3-65768K-5
HM3-65768M-5
HM4-65768H-5
HM4-65768K-2
H M4-65768K-5
HM4-65768K-8
HM4-65768M-2
IDT6168LA70DM
IDT6168LA35D
IDT6168SA85DM
IDT6168SA35D
IDT6168SA85DB
IDT6168SA70DM
IDT6168SA35D
IDT6168SA70DB
IDT6168LA35P
IDT6168LA35P
IDT6168SA35P
IDT6168SA35P
IDT6168LA85LM
IDT6168LA35L
IDT6168LA85LB
IDT6168LA70LM
IDT6168LA35L
IDT6168SA85LM
IDT6168SA35L
IDT6168SA85LB
IDT6168SA70LM
IDT6168SA35L
IDT6168SA70LB
IDT6168LA55DM
IDT6168LA35D
IDT6168LA45DB
IDT6168LA35P
IDT6168LA55LM
IDT6168LA35L
IDT6168LA55LB
IDT6116SA35D
IDT6116SA45DM
IDT6116SA45D
IDT6116SA45L24
IDT6116SA55DM
IDT6116SA55L24M
IDT6116SA45D
IDT6116SA45L24
IDT6116SA35TP
IDT6116SA45TP
IDT6116SA45TP
IDT6116SA35L24
IDT6116SA45L24M
IDT6167SA25D
IDT6167SA35DM
IDT6167SA35D
IDT6167SA35DB
IDT6167SA45DM
IDT6167SA35D
IDT6167SA45DB
IDT6167SA25P
IDT6167SA35P
IDT6167SA35P
IDT6167SA25L
IDT6167SA35LM
IDT6167SA35L
IDT6167SA35LB
IDT6167SA45LM
IDT6167SA35L
IDT6167SA45LB
IDT6168SA25D
IDT6168SA35DM
IDT6168SA35D
IDT6168SA35DB
IDT6168SA45DM
IDT6168SA35D
IDT6168SA45DB
IDT6168SA25P
IDT6168SA35P
IDT6168SA35P
IDT6168SA25L
IDT6168SA35LM
IDT6168SA35L
IDT6168SA35LB
IDT6168SA45LM
MATRA-HARRIS
CONT.
lOT
HM4-65768M-5
HM4-65768M-8
HM1-65769H-5
HM1-65769K-2
HM1-65769K-5
HM1-65769K-8
HM1-65769M-2
HM1-65769M-5
HM1-65769M-8
HM3-65769H-5
HM3-65769K-5
HM3-65769M-5
HM4-65769H-5
HM4-65769K-2
HM4-65769K-5
HM4-65769K-8
HM4-65769M-2
HM4-65769M-5
HM4-65769M-8
IDT6168SA35L
IDT6168SA45LB
IDT6168SA15D
IDT6168SA20DM
IDT6168SA20D
IDT6168SA20DB
IDT6168SA25DM
IDT6168SA25D
IDT6168SA25DB
IDT6168SA15P
IDT6168SA20P
IDT6168SA25P
IDT6168SA15L
IDT6168SA20LM
IDT6168SA20L
IDT6168SA20LB
IDT6168SA25LM
IDT6168SA25L
IDT6168SA25LB
MICRON
MT5C1601-15
MT5C1601-20
MT5C1601-25
MT5C1601-30
MT5C1601-35
MT5C1601DJ-15
MT5C1601 DJ-20
MT5C1601DJ-25
MT5C1601DJ-3O
MT5C1601 DJ-35
MT5C1601 EC-15
MT5C1601 EC-20
MT5C1601 EC-25
MT5C1601 EC-30
MT5C1601 EC-35
MT5C1601-15L
MT5C1601-20L
MT5C1601-25L
MT5C1601-30L
MT5C1601-35L
MT5C1601DJ-15L
MT5C1601 DJ-20L
MT5C1601 DJ-25L
MT5C1601 DJ-3OL
MT5C1601 DJ-35L
MT5C1601 EC-15L
MT5C1601 EC-20L
MT5C1601 EC-25L
MT5C1601 EC-3OL
MT5C1601 EC-35L
MT5C1604-15
MT5C1604-20
MT5C1604-25
MT5C1604-35
MT5C1604DJ-15
MT5C1604DJ-20
MT5C1604DJ-25
MT5C1604DJ-35
MT5C1604EC-15
MT5C1604EC-20
MT5C1604EC-25
MT5C1604EC-35
MT5C1604-15L
MT5C1604-20L
MT5C1604-25L
MT5C1604-35L
MT5C1604DJ-15L
.MT5C1604DJ-20L
MT5C1604DJ-25L
MT5C1604DJ-35L
MT5C1604EC-15L
MT5C1604EC-20L
MT5C1604EC-25L
lOT
IDT6167SA15P
IDT6167SA20P
IDT6167SA25P
IDT6167SA3OP
IDT6167SA35P
IDT6167SA15Y
IDT6167SA20Y
IDT6167SA25Y
IDT6167SA3OY
IDT6167SA35Y
IDT6167SA15L
IDT6167SA20L
IDT6167SA25L
IDT6167SA30L
IDT6167SA35L
IDT6167LA15P
IDT6167LA20P
IDT6167LA25P
IDT6167LA3OP
IDT6167LA35P
IDT6167LA15Y
IDT6167LA20Y
IDT6167LA25Y
IDT6167LA3OY
IDT6167LA35Y
IDT6167LA15L
IDT6167LA20L
IDT6167LA25L
IDT6167LA3OL
IDT6167LA35L
IDT6168SA15P
IDT6168SA20P
IDT6168SA25P
IDT6168SA35P
IDT6168SA15Y
IDT6168SA20Y
IDT6168SA25Y
IDT6168SA35Y
IDT6168SA15L
IDT6168SA20L
IDT6168SA25L
IDT6168SA35L
IDT6168LA15P
IDT6168LA20P
IDT6168LA25P
IDT6168LA35P
IDT6168LA15Y
IDT6168LA20Y
IDT6168LA25Y
IDT6168LA35Y
IDT6168LA15L
IDT6168LA20L
IDT6168LA25L
S1-27
....
__._._-._-_._--_._-----------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
MICRON CONT.
lOT
MICRON CO NT.
lOT
MICRON CO NT..
lOT
MT5C1604EC-35L
MT5C1605-15
MT5C1605-20
MT5C1605-25
MT5C1605-30
MT5C1605-35
MT5C1605DJ-15
MT5C1605DJ-20
MT5C1605DJ-25
MT5C1605DJ-30
MT5C1605DJ-35
MT5C160SEC-15
MT5C1605EC-20
MT5C1605EC-25
MT5C1605EC-30
MT5C1605EC-35
MT5C1605-15L
MT5C1605-20L
MT5C1605-25L
MT5C160S-30L
MT5C1605-35L
MT5C1605DJ-15L
MT5C1605DJ-20L
MT5C1605DJ-25L
MT5C1605DJ-30L
MT5C1605DJ-3SL
MT5C1605EC-15L
MT5C1605EC-20L
MT5C1605EC-25L
MT5C1605EC-30L
MT5C1605EC-35L
MT5C1608-15
MT5C1608-20
MT5C1608-25
MT5C1608-30
MT5C1608-35
MT5C1608DJ-15
MT5C1608DJ-20
MT5C1608DJ-25
MT5C1608DJ -30
MT5C1608DJ-35
MT5C1608EC-15
MT5C1608EC-20
MT5C1608EC-25
MT5C1608EC-30
MT5C1608EC-35
MT5C1608-15L
MT5C1608-20L
MT5C1608-25L
MT5C1608-30L
MT5C1608-35L
MT5C1608DJ-15L
MT5C1608DJ-20L
MT5C1608DJ-25L
MT5C1608DJ-30L
MT5C1608DJ-35L
MT5C1608EC-15L
MT5C1608EC-20L
MT5C1608EC-25L
MT5C1608EC-30L
MT5C1608EC-35L
MT5C6401-15
MT5C64D1-20
MT5C6401-25
IDT6168LA35L
IDT6198SA15P
IDT6198SA20P
IDT6198SA25P
IDT6198SA30P
IDT6198SA35P
IDT6198SA15Y
IDT6198SA20Y
IDT6198SA25Y
IDT6198SA30Y
IDT6198SA35Y
IDT6198SA15L
IDT6198SA2OL
IDT6198SA25L
IDT6198SA30L
IDT6198SA35L
IDT6198LA15P
IDT6198LA20P
IDT6198LA25P
IDT6198LA30P
IDT6198LA35P
IDT6198LA15Y
IDT6198LA20Y
IDT6198LA25Y
IDT6198LA30Y
IDT6198LA35Y
IDT6198LA15L
IDT6198LA20L
IDT6198LA25L
IDT6198LA30L
IDT6198LA35L
IDT6116SA15TP
IDT6116SA20TP
IDT6116SA25TP
IDT6116SA30TP
IDT6116SA35TP
IDT6116SA15Y
IDT6116SA20Y
IDT6116SA25Y
IDT6116SA30Y
IDT6116SA35Y
IDT6116SA15L28
IDT6116SA20L28
IDT6116SA25L28
IDT6116SA30L28
IDT6116SA35L28
IDT6116LA15TP
IDT6116LA20TP
IDT6116LA25TP
IDT6116LA30TP
IDT6116LA35TP
IDT6116LA15Y
IDT6116LA20Y
IDT6116LA25Y
IDT6116LA30Y
IDT6116LA35Y
IDT6116LA15L28
IDT6116LA20L28
IDT6116LA25L28
IDT6116LA30L28
IDT6116LA35L28
IDT7187S15P
IDT7187S2DP
IDT7187S25P
MT5C6401-30
MT5C6401-35
MT5C6401C-15
MT5C6401 C-20
MT5C6401 C-25
MT5C6401 C-30
MT5C6401 C-35
MT5C6401DJ-15
MT5C6401DJ-20
MT5C6401 DJ-25
MT5C6401 DJ-30
MT5C6401 DJ-35
MT5C6401EC-15
MT5C6401 EC-20
MT5C6401 EC-25
MT5C6401 EC-30
MT5C6401 EC-35
MT5C6401-15L
MT5C6401-20L
MT5C6401-2SL
MT5C6401-30L
MT5C6401-35L
MT5C6401C-15L
MT5C6401 C-20L
MT5C6401 C-25L
MT5C6401 C-30L
MT5C6401 C-3SL
MT5C6401DJ-15L
MT5C6401 DJ-20L
MT5C6401 DJ-25L
MT5C6401 DJ-30L
MT5C6401 DJ-35L
MT5C6401 EC-15L
MT5C6401 EC-20L
MT5C6401 EC-25L
MT5C6401 EC-30L
MT5C6401 EC-35L
MT5C6404-15
MT5C6404-20
MT5C6404-25
MT5C6404-30
MT5C6404-35
MT5C6404C-15
MT5C6404C-20
MT5C6404C-25
MT5C6404C-30
MT5C6404C-35
MT5C6404DJ-15
MT5C6404DJ-20
MT5C6404DJ-25
MT5C6404DJ-30
MT5C6404DJ-35
MT5C6404-15L
MT5C6404-20L
MT5C6404-25L
MT5C6404-30L
MT5C6404-35L
MT5C6404C-15L
MT5C6404C-20L
MT5C6404C-25L
MT5C6404C-30L
MT5C6404C-35L
MT5C64D4DJ-15L
MT5C6404DJ-20L
MT5C6404DJ-25L
MT5C6404DJ-30L
MT5C6404DJ-35L
MT5C6405-15
MT5C6405-2D
MT5C6405-25
MT5C6405-30
MT5C6405-35
MT5C6405C-15
MT5C6405C-20
MT5C6405C-25
IDT7187S30P
IDT7187S35P
IDT7187S15C
IDT7187S20C
IDT7187S25C
IDT7187S30C
IDT7187S35C
IDT7187S15Y
IDT7187S20Y
IDT7187S25Y
IDT7187S30Y
IDT7187S35Y
IDT7187S15L22
IDT7187S20L22
IDT7187S25L22
IDT7187S30L22
IDT7187S35L22
IDT7187L15P
IDT7187L20P
IDT7187L25P
IDT7187L30P
IDT7187L35P
IDT7187L15C
IDT7187L20C
IDT7187L25C
IDT7187L30C
IDT7187L35C
IDT7187L15Y
IDT7187L20Y
IDT7187SL25Y
IDT7187L30Y
IDT7187L35Y
IDT7187L15L22
IDT7187L20L22
IDT7187L25L22
IDT7187L30L22
IDT7187L35L22
IDT7188S15P
IDT7188S20P
IDT7188S25P
IDT7188S30P
IDT7188S35P
IDT7188S15C
IDT7188S20C
IDT7188S25C
IDT7188S30C
IDT7188S35C
IDT7188S15Y
IDT7188S20Y
IDT7188S25Y
IDT7188S30Y
IDT7188S35Y
IDT7188L15P
IDT7188L20P
IDT7188L25P
IDT7188L30P
IDT7188L35P
IDT7188L15C
IDT7188L20C
IDT7188L25C
IDT7188L30C
IDT7188L35C
IDT7188L15Y
IDT7188L20Y
IDT7188L25Y
IDT7188L30Y
IDT7188L35Y
IDT7198S15P
IDT7198S20P
IDT7198S25P
IDT7198S30P
IDT7198S35P
IDT7198S15C
IDT7198S20C
IDT7198S25C
MT5C6405C-30
MT5C6405C-35
MT5C6405DJ-15
MT5C6405DJ-20
MT5C6405DJ-25
MT5C6405DJ-30
MT5C6405DJ-35
MT5C6405-15L
MT5C6405-20L
MT5C6405-25L
MT5C6405-30L
MT5C6405-35L
MT5C6405C-15L
MT5C6405C-20L
MT5C6405C-25L
MT5C6405C-30L
MT5C6405C-35L
MT5C6405DJ-15L
MT5C6405DJ-20L
MT5C640SDJ-25L
MT5C6405DJ-30L
MT5C6405DJ-35L
MT5C6408-20
MT5C6408-25
MT5C6408-30
MT5C6408-35
MT5C6408C-20
MT5C6408C-25
MT5C6408C-30
MT5C6408C-35
MT5C6408DJ-20
MT5C6408DJ-25
MT5C6408DJ-30
MT5C6408DJ-35
MT5C6408EC-20
MT5C6408EC-25
MT5C6408EC-30
MT5C6408EC-35
MT5C6408-20L
MT5C6408-25L
MT5C6408-30L
MT5C6408-35L
MT5C6408C-20L
MT5C6408C-25L
MT5C6408C-30L
MT5C6408C-35L
MT5C6408DJ-20L
MT5C6408DJ-25L
MT5C6408DJ-30L
MT5C6408DJ-35L
MT5C6408EC-20L
MT5C6408EC-25L
MT5C6408EC-30L
MT5C6408EC-35L
MT5C2561-25
MT5C2561-30
MT5C2561-35
MT5C2561-45
MT5C2561-55
MT5C2561 C-25
MT5C2561 C-30
MT5C2561C-35
MT5C2561 C-45
MT5C2561 C-55
MT5C2561 DJ-25
MT5C2561 DJ-30
MT5C2561 DJ-35
MT5C2561 DJ-45
MT5C2561 DJ-55
MT5C2561 EC-25
MT5C2561 EC-30
MT5C2561 EC-35
MT5C2561 EC-45
MT5C2561 EC-55
MT5C2561-25L
IDT7198S30C
IDT7198S35C
IDT7198S15Y
IDT7198S20Y
IDT7198S25Y
IDT7198S30Y
IDT7198S35Y
IDT7198L15P
IDT7198L20P
IDT7198L25P
IDT7198L30P
IDT7198L35P
IDT7198L15C
IDT7198L20C
IDT7198L25C
IDT7198L30C
IDT7198L35C
IDT7198L15Y
IDT7198L20Y
IDT7198L25Y
IDT7198L30Y
IDT7198L35Y
IDT7164S20TP
IDT7164S25TP
IDT7164S30TP
IDT7164S35TP
IDT7164S20TC
IDT7164S25TC
IDT7164S30TC
IDT7164S35TC
IDT7164S20Y
IDT7164S25Y
IDT7164S30Y
IDT7164S35Y
IDT7164S20L32
IDT7164S25L32
IDT7164S30L32
IDT7164S35L32
IDT7164L20TP
IDT7164L25TP
IDT7164L30TP
IDT7164L35TP
IDT7164L20TC
IDT7164L25TC
IDT7164L30TC
IDT7164L35TC
IDT7164L20Y
IDT7164L25Y
IDT7164L30Y
IDT7164L35Y
IDT7164S20L32
IDT7164S25L32
IDT7164S30L32
IDT7164S35L32
IDT71257S25P
IDT71257S30P
IDT71257S35P
IDT71257S45P
IDT71257S55P
IDT71257S25C
IDT71257S30C
IDT71257S35C
IDT71257S45C
IDT71257S55C
IDT71257S25Y
IDT71257S30Y
IDT71257S35Y
IDT71257S45Y
IDT71257S55Y
IDT71257S25L
IDT71257S30L
IDT71257S35L
IDT71257S45L
IDT71257S55L
IDT71257L25P
NOTE:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
S1-28
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
MICRON CONT.
MT5C2561-30L
MT5C2561-35L
MT5C2561-45L
MT5C2561-55L
MT5C2561C-25L
. MT5C2561 C-30L
MT5C2561 C-35L
MT5C2561 C-45L
MT5C2561 C-55L
MT5C2561 DJ-25L
MT5C2561 DJ-30L
MT5C2561 DJ-35L
MT5C2561 DJ-45L
MT5C2561DJ-55L
MT5C2561 EC-25L
MT5C2561 EC-30L
MT5C2561 EC-35L
MT5C2561 EC-45L
MT5C2561 EC-55L
MT5C2564-25
MT5C2564-30
MT5C2564-35
MT5C2564-45
MT5C2564-55
MT5C2564C-25
MT5C2564C-30
MT5C2564C-35
MT5C2564C-45
MT5C2564C-55
MT5C2564DJ-25
MT5C2564DJ-30
MT5C2564DJ-35
MT5C2564DJ-45
MT5C2564DJ-55
MT5C2564EC-25
MT5C2564EC-30
MT5C2564 EC-35
MT5C2564EC-45
MT5C2564EC-55
MT5C2564-25L
MT5C2564-30L
MT5C2564-35L
MT5C2564-45L
MT5C2564-55L
MT5C2564C-25L
MT5C2564C-30L
MT5C2564C-35L
MT5C2564C-45L
MT5C2564C-55L
MT5C2564DJ-25L
MT5C2564DJ-30L
MT5C2564DJ-35L
MT5C2564DJ-45L
MT5C2564DJ-55L
MT5C2564EC-25L
MT5C2564EC-30L
MT5C2564EC-35L
MT5C2564EC-45L
MT5C2564EC-55L
MT5C2565-25
MT5C2565-30
MT5C2565-35
MT5C2565-45
MT5C2565-55
MT5C2565C-25
MT5C2565C-30
MT5C2565C-35
lOT
ID171257L30P
ID171257L35P
ID171257L45P
ID171257L55P
ID171257L25C
ID171257L30C
ID171257L35C
ID171257L45C
ID171257L55C
ID171257L25Y
ID171257L30Y
ID171257L35Y
ID171257L45Y
ID171257L55Y
ID171257L25L
ID171257L30L
ID171257L35L
ID171257L45L
ID171257L55L
ID171258S25P
ID171258S30P
ID171258S35P
ID171258S45P
ID171258S55P
ID171258S25C
ID171258S30C
ID171258S35C
ID171258S45C
ID171258S55C
ID171258S25Y
ID171258S30Y
ID171258S35Y
ID171258S45Y
ID171258S55Y
ID171258S25L
ID171258S30L
ID171258S35L
ID171258S45L
ID171258S55L
ID171258L25P
ID171258L30P
ID171258L35P
ID171258L45P
ID171258L55P
ID171258L25C
ID171258L30C
ID171258L35C
ID171258L45C
ID171258L55C
ID171258L25Y
ID171258L30Y
ID171258L35Y
ID171258L45Y
ID171258L55Y
ID171258L25L
ID171258L30L
ID171258L35L
ID171258L45L
ID171258L55L
IDT61298S25P
IDT61298S30P
IDT61298S35P
IDT61298S45P
IDT61298S55P
IDT61298S25C
IDT61298S30C
IDT61298S35C
NOTE:
A lower case ·x" indicates the speed and/or
package of the part are unknown."
MICRON CONT.
MT5C2565C-45
MT5C2565C-55
MT5C2565DJ-25
MT5C2565DJ-30
MT5C2565DJ-35
MT5C2565DJ-45
MT5C2565DJ-55
MT5C2565EC-25
MT5C2565EC-30
MT5C2565EC-35
MT5C2565EC-45
MT5C2565EC-55
MT5C2565-25L
MT5C2565-30L
MT5C2565-35L
MT5C2565-45L
MT5C2565-55L
MT5C2565C-25L
MT5C2565C-30L
MT5C2565C-35L
MT5C2565C-45L
MT5C2565C-55L
MT5C2565DJ-25L
MT5C2565DJ-30L
MT5C2565DJ-35L
MT5C2565DJ-45L
MT5C2565DJ-55L
MT5C2565EC-25L
MT5C2565EC-30L
MT5C2565EC-35L
MT5C2565EC-45L
MT5C2565EC-55L
MT5C2568-25
MT5C2568-30
MT5C2568-35
MT5C2568-45
MT5C2568-55
MT5C2568C-25
MT5C2568C-30
MT5C2568C-35
MT5C2568C-45
MT5C2568C-55
MT5C2568DJ-25
MT5C2568DJ-30
MT5C2568DJ-35
MT5C2568DJ-45
MT5C2568DJ-55
MT5C2568EC-25
MT5C2568EC-30
MT5C2568EC-35
MT5C2568EC-45
MT5C2568EC-55
MT5C2568-25L
MT5C2568-30L
MT5C2568-35L
MT5C2568-45L
MT5C2568-55L
MT5C2568C-25L
MT5C2568C-30L
MT5C2568C-35L
MT5C2568C-45L
MT5C2568C-55L
MT5C2568DJ-25L
MT5C2568DJ-30L
MT5C2568DJ-35L
. MT5C2568DJ-45L
MT5C2568DJ-55L
MT5C2568EC-25L
MT5C2568EC-30L
MT5C2568EC-35L
MT5C2568EC-45L
MT5C2568EC-55L
lOT
MITSUBISHI
lOT
IDT61298S45C
IDT61298S55C
IDT61298S25Y
IDT61298S30Y
IDT61298S35Y
IDT61298S45Y
IDT61298S55Y
IDT61298S25L
IDT61298S30L
IDT61298S35L
IDT61298S45L
IDT61298S55L
IDT61298L25P
IDT61298L30P
IDT61298L35P
IDT61298L45P
IDT61298L55P
IDT61298L25C
IDT61298L30C
IDT61298L35C
IDT61298L45C
IDT61298L55C
IDT61298L25Y
IDT61298L30Y
IDT61298L35Y
IDT61298L45Y
IDT61298L55Y
IDT61298L25L
IDT61298L30L
IDT61298L35L
IDT61298L45L
IDT61298L55L
ID171256S25TP
ID171256S30TP
ID171256S35TP
ID171256S45TP
ID171256S55TP
ID171256S25D
ID171256S30D
ID171256S35D
ID171256S45D
ID171256S55D
ID171256S25Y
ID171256S30Y
ID171256S35Y
ID171256S45Y
ID171256S55Y
ID171256S25L32
ID171256S30L32
ID171256S35L32
ID171256S45L32
ID171256S55L32
ID171256L25TP
ID171256L30TP
ID171256L35TP
ID171256L45TP
ID171256L55TP
ID171256L25D
ID171256L30D
ID171256L35D
ID171256L45D
ID171256L55D
ID171256L25Y
ID171256L30Y
ID171256L35Y
ID171256L45Y
ID171256L55Y
ID171256L25L32
ID171256L30L32
ID171256L35L32
ID171256L45L32
ID171256L55L32
M5M21 C67P-35
M5M21 C67P-45
M5M21 C67P-55
M5M21 C68P-35
M5M21 C68P-45
M5M21 C68P-55
M5M5165FP-70
M5M5165FP-70L
M5M5178P-45
M5M5178P-55
M5M5187AD-25
M5M5187AD-35
M5M5187 AP-25
M5M5187AP-35
M5M5187P-45
M5M5187P-55
M5M5188AD-25
M5M5188AD-35
M5M5188AP-25
M5M5188AP-35
M5M5188P-45
M5M5188P-55
M5M5257P-35
M5M5257P-45
M5M5257P-55
M5M5258P-35
M5M5258P-45
M5M5258P-55
IDT6167LA35P
IDT6167LA35P
IDT6167LA35P
IDT6168LA35P
IDT6168LA35P
IDT6168LA35P
ID17164S45S0
ID17164L45S0
ID17164L45P
ID17164L45P
ID17187L25L22
ID17187L35L22
ID17187L25P
ID17187L35P
ID17187L45P
ID17187L55P
ID17188L25L22
ID17188L35L22
ID17188L25P
ID17188L35P
ID17188L45P
ID17188L45P
ID171257S35P
ID171257S45P
ID171257S55P
ID171258S35P
ID171258S45P
ID171258S55P
MOTOROLA
lOT
S1-29
MCM2016HN45
MCM2167P45
MCM4180P25
MCM6164P45
MCM6168P35
MCM6206P45
MCM6206P55
MCM6207P25
MCM6207P35
MCM6207L25
MCM6207L35
MCM6208P25
MCM6208P35
MCM6208L25
MCM6208L35
MCM6268P25
MCM6268P35
MCM6287P35
MCM6287P45
MCM6287P25
MCM6288P25
MCM6288P35
MCM6288P45
MCM6290P25
MCM6290P35
MCM6292C25
MCM6292C35
MCM6293P25
MCM6293P35
MCM6294P25
MCM6294P35
MCM6295C25
MCM6295C35
IDT6116SA45TP
IDT6167SA45P
IDT6178S20P
ID17164S45P
IDT6168SA35P
ID171256S45P,
ID171256S55P
ID171257S25P
ID171257S35P
ID171257S25C
ID171257S35C
ID171258S25P
ID171258S35P
ID171258S25C
ID171258S35C
IDT6168SA25P
IDT6168SA35P
ID17187S35P
ID17187S45P
ID17187S25P
ID17188S25P
ID17188S35P
ID17188S45P
IDT6198S25P
IDT6198S35P
IDT61592S25D
IDT61592S35D
IDT61593S25P
IDT61593S35P
IDT61594S25P
IDT61594S35P
IDT61595S25D
IDT61595S35D
NEC
lOT
5PD4311 C-35
5PD4311 C-45
5PD4311 C-55
5PD4311 D-35
5PD4311 D-45
5PD4311D-55
5PD4314C-35
IDT6167SA35P
IDT6167SA35P
IDT6167SA35P
IDT6167SA35D
IDT6167SA35D
IDT6167SA35D
IDT6168SA35P
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
NEC CONT.
lOT
5PD4314C-45
5PD4314C-55
5PD43256C-10
5PD43256C-10L
5PD43256G-10
5PD43256G-10L
5PD4361 C-45
5PD4361 C-45L
5PD4361 C-55
5PD4361 C-55L
5PD4361 C-70
5PD4361 C-70L
5PD4361 K-40
5PD4361 K-45
5PD4361 K-55
5PD4362C-45
5PD4362C-55
5PD4362C-70
5PD4364C-12
5PD4364C-12L
5PD4364G-12
5PD4364G-12L
5PD446C
5PD4464C-x
5PD4464G-x
IDT6168SA35P
IDT6168SA35P
IDT71256S70P
IDT71256L70P
IDT71256S70S0
IDT71256L70S0
IDT7187S45P
IDT7187L45P
IDT7187S45P
IDT7187L45P
IDT7187S45P
IDT7187L45P
IDT7187S35L22
IDT7187S45L22
IDT7187S45L22
IDT7188SA45P
IDT7188SA45P
IDT7188SA45P
IDT7164S45P
IDT7164L45P
IDT7164S45S0
IDT7164L45S0
IDT6116LA45P
IDT7164L45P
IDT7164L45S0
PERFORMANCE
lOT
P4C116-25DC
P4C116-25JC
P4C116-25PC
P4C116-30DC
P4C116-30JC
P4C116-30PC
P4C116-35DC
P4C116-35DM
P4C116-35DM B
P4C116-35JC
P4C116-35PC
P4C116L-25DC
P4C116L-25JC
P4C116L-25PC
P4C116L-30DC
P4C116L-30LC
P4C116L-30PC
P4C116L-35CC
P4C116L-35CM
P4C116L-35CMB
P4C116L-35LC
P4C116L-35LM
P4C116L-35LM B
P4C116L-35PC
P4C164-25CC
P4C164-25LC
P4C164-25PC
P4C164-25JC
P4C164-30CC
P4C164-30LC
P4C164-30PC
P4C164-30JC
P4C164-35CC
P4C164-35CM
P4C164-35CMB
P4C164-35LC
P4C164-35LM
IDT6116SA25TD
IDT6116SA25Y
IDT6116SA25TP
IDT6116SA30TD
IDT6116SA30Y
IDT6116SA30TP
IDT6116SA35TD
IDT6116SA35TDM
IDT6116SA35TDB
IDT6116SA35Y
IDT6116SA35TP
IDT6116LA25TD
IDT6116LA25Y
IDT6116LA25TP
IDT6116LA30TD
IDT6116LA30Y
IDT6116LA30TP
IDT6116LA35TD
IDT6116LA35TDM
IDT6116LA35TDB
IDT6116LA35L24
IDT6116LA35L24M
IDT6116LA35L24B
IDT6116LA35TP
IDT7164S25TC
IDT7164S25L28
IDT7164S25TP
IDT7164S25Y
IDT7164S30TC
IDT7164S30L28
IDT7164S30TP
IDT7164S30Y
IDT7164S35TC
IDT7164S35TCM
IDT7164S35TCB
IDT7164S30L28
IDT7164S35L28M
NOTE:
A lower case "x· indicates the speed and/or
package of the part are unknown.'
PERFORMANCE
CONT.
lOT
PERFORMANCE
CONT.
lOT
P4C164-35LMB
P4C164-35PC
P4C164-35JC
P4C164-45CM
P4C164-45CM B
P4C164-45LM
P4C164-45LM B
P4C164L-30CC
P4C164L-30LC
P4C164L-30PC
P4C164L-30JC
P4C164L-35CC
P4C164L-35CM
P4C164L-35CMB
P4C164L-35LC
P4C164L-35LM
P4C164L-35LMB
P4C164L-35PC
P4C164L-35JC
P4C164L-45CM
P4C164L-45CMB
P4C164L-45LM
P4C164L-45LMB
P4C168-20DC
P4C168-20PC
P4C168-20JC
P4C168-25DC
P4C168-25DM
P4C168-25DMB
P4C168-25JC
P4C168-25PC
P4C168-35DC
P4C168-35DM
P4C168-35DMB
P4C168-35JC
P4C168-35PC
P4C168-45DM
P4C168-45DMB
P4C168L-20DC
P4C168L-20JC
P4C168L-20PC
P4C168L-25DC
P4C168L-25DM
P4C168L-25DMB
P4C168L-25JC
P4C168L-25PC
P4C168L-35DC
P4C168L-35DM
P4C168L-35DMB
P4C168L-35JC
P4C168L-35PC
P4C168L-45DM
P4C168L-45DMB
P4C1681-20DC
P4C1681-20LC
P4C1681-20PC
P4C1681-25DC
P4C1681-25CM
P4C1681-25CMB
P4C1681-25LC
P4C1681-25LM
P4C1681-25LMB
P4C1681-25PC
P4C1681-35DC
P4C1681-35CM
P4C1681-35CM B
P4C1681-35LC
P4C1681-35LM
P4C1681-35LMB
P4C1681-35PC
P4C1681-45DC
P4C1681-45CM
P4C1681-45CMB
P4C1681-45LC
P4C1681-45LM
IDT7164S35L28B
IDT7164S35TP
IDT7164S35Y
IDT7164S45TCM
IDT7164S45TCB
IDT7164S45L28M
IDT7164S45L28B
IDT7164L30TC
IDT7164L30L28
IDT7164L30TP
IDT7164L30Y
IDT7164L35TC
IDT7164L35TCM
IDT7164L35TCB
IDT7164L30L28
IDT7164L35L28M
IDT7164L35L28B
IDT7164L35TP
IDT7164L35Y
IDT7164L45TCM
IDT7164L45TCB
IDT7164L45L28M
IDT7164L45L28B
IDT6168SA20D
IDT6168SA20P
IDT6168SA20Y
IDT6168SA25D
IDT6168SA25DM
IDT6168SA25DB
IDT6168SA25Y
IDT6168SA25P
IDT6168SA35D
IDT6168SA35DM
IDT6168SA35DB
IDT6168SA35Y
IDT6168SA35P
IDT6168SA45DM
IDT6168SA45DB
IDT6168LA20D
IDT6168LA20Y
IDT6168LA20P
IDT6168LA25D
IDT6168LA25DM
IDT6168LA25DB
IDT6168LA25Y
IDT6168LA25P
IDT6168LA35D
IDT6168LA35DM
IDT6168LA35DB
IDT6168LA35Y
IDT6168LA35P
IDT6168LA45DM
IDT6168LA45DB
IDT71681SA20D
IDT71681SA20L
IDT71681SA20P
IDT71681SA25D
IDT71681SA25DM
IDT71681SA25DB
IDT71681SA25L
IDT71681SA25LM
IDT71681SA25LB
IDT71681SA25P
IDT71681SA35D
IDT71681SA35DM
IDT71681SA35DB
IDT71681SA35L
IDT71681SA35LM
IDT71681SA35LB
IDT71681SA35P
IDT71681SA45D
IDT71681SA45DM
IDT71681SA45CB
IDT71681SA45L
IDT71681SA45LM
P4C1681-45LMB
P4C1681-45PC
P4C1681L-20DC
P4C1681 L-20LC
P4C1681 L-20PC
P4C1681 L-25DC
P4C1681 L-25CM
P4C1681 L-25CMB
P4C1681 L-25LC
P4C1681 L-25LM
P4C1681 L-25LMB
P4C1681 L-25PC
P4C1681 L-35DC
P4C1681 L-35CM
P4C1681 L-35CM B
P4C1681 L-35LC
P4C1681 L-35LM
P4C1681 l;-35LM B
P4C1681 L-35PC
P4C1681 L-45DC
P4C1681 L-45CM
P4C1681 L-45CMB
P4C1681 L-45LC
P4C1681 L-45LM
P4C1681 L-45LM B
P4C1681 L-45PC
P4C1682-20CC
P4C1682-20LC
P4C1682-20PC
P4C1682-25CC
P4C1682-25CM
P4C1682-25CM B
P4C1682-25LC
P4C1682-25LM
P4C1682-25LMB
P4C1682-25PC
P4C1682-35CC
P4C1682-35CM
P4C1682-35CMB
P4C1682-35LC
P4C1682-35LM
P4C1682-35LMB
P4C1682-35PC
P4C1682-45CC
P4C1682-45CM
P4C1682-45CM B
P4C1682':'45LC
P4C1682-45LM
P4C1682-45LMB
P4C1682-45PC
P4C1682L-20CC
P4C1682L-20LC
P4C1682L-20PC
P4C1682L-25CC
P4C1682L-25CM
P4C1682L-25CMB
P4C1682L-25LC
P4C1682L-25LM
P4C1682L-25LMB
P4C1682L-25PC
P4C1682L-35CC
P4C1682L-35CM
P4C1682L-35CMB
P4C1682L-35LC
P4C1682L-35LM
P4C1682L-35LMB
P4C1682L-35PC
P4C1682L-45CC
P4C1682L-45CM
P4C1682L-45CM B
P4C1682L-45LC
P4C1682L-45LM
P4C1682L-45LMB
P4C1682L-45PC
P4C187-20CC
IDT71681 SA45LB
IDT71681 SA45P
IDT71681 LA20D
IDT71681 LA20L
IDT71681 LA20P
IDT71681 LA25D
IDT71681LA25DM
IDT71681 LA25DB
IDT71681 LA25L
IDT71681 LA25LM
IDT71681 LA25LB
IDT71681 LA25P
IDT71681LA35D
IDT71681 LA35DM
IDT71681LA35DB
IDT71681LA35L
IDT71681LA35LM
IDT71681 LA35LB
IDT71681 LA35P
IDT71681 LA45D
IDT71681LA45DM
IDT71681 LA45CB
IDT71681 LA45L
IDT71681 LA45LM
IDT71681 LA45LB
IDT71681 LA45P
IDT71682SA20D
IDT71682SA20L
IDT71682SA20P
IDT71682SA25D
IDT71682SA25DM
IDT71682SA25DB
IDT71682SA25L
IDT71682SA25LM
IDT71682SA25LB
IDT71682SA25P
IDT71682SA35D
IDT71682SA35DM
IDT71682SA35DB
IDT71682SA35L
IDT71682SA35LM
IDT71682SA35LB
IDT71682SA35P
IDT71682SA45D
IDT71682SA45DM
IDT71682SA45CB
IDT71682SA45L
IDT71682SA45LM
IDT71682SA45LB
IDT71682SA45P
IDT71682LA20D
IDT71682LA20L
IDT71682LA20P
IDT71682LA25D
IDT71682LA25DM
IDT71682LA25DB
IDT71682LA25L
IDT71682LA25LM
IDT71682LA25LB
IDT71682LA25P
IDT71682LA35D
IDT71682LA35DM
IDT71682LA35DB
IDT71682LA35L
IDT71682LA35LM
IDT71682LA35LB
IDT71682LA35P
IDT71682LA45D
IDT71682LA45DM
IDT71682LA45CB
IDT71682LA45L
IDT71682LA45LM
IDT71682LA45LB
IDT71682LA45P
IDT7187S20C
Sl-30
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
PERFORMANCE
CONT.
lOT
P4C187-20PC
P4C187-20LC
P4C187-20JC
P4C187-25CC
P4C187-25CM
P4C187-25CMB
P4C187-25PC
P4C187-25LC
P4C187-25CM
P4C187-25CMB
P4C187-25JC
P4C187-30CM
P4C187-30CMB
P4C187-30LM
P4C187-30LMB
P4C187 -35CM
P4C187 -35CM B
P4C187-35LM
P4C187-35LMB
P4C187L-20CC
P4C187L-20PC
P4C187L-20LC
P4C187L-20JC
P4C187L-25CC
P4C187L-25CM
P4C187L-25CMB
P4C187L-25PC
P4C187L-25LC
P4C187L-25CM
P4C187L-25CMB
P4C187L-25JC
P4C187L-30CM
P4C187L.;.30CMB
P4C187L-30LM
P4C187L-30LMB
P4C187L-35CM
P4C187L-35CM B
P4C187L-35LM
P4C187L-35LMB
P4C188-20CC
P4C188-20PC
P4C188-20LC
P4C188-20JC
P4C188-25CC
P4C188-25CM
P4C188-25CMB
P4C188-25LC
P4C188-25LM
P4C188-25LMB
P4C188-25PC
P4C188-25JC
P4C188-30CC
P4C188-30CM
P4C188-30CMB
P4C188-30LC
P4C188-30LM
P4C188-30LMB
P4C188-30PC
P4C188-30JC
P4C188-35CC
P4C188-35CM
P4C188-35CMB
P4C188-35LC
P4C188-35LM
P4C188-35LMB
P4C188-35PC
P4C188-35JC
P4C188-45CM
P4C188-45CMB
P4C188-45LM
IOT7187S20P
IDT7187S20L22
IDT7187S20Y
IDT7187S25C
IDT7187S25CM
IDT7187S25CB
IDT7187S25P
IDT7187S25L22
IDT7187S25CM
IDT7187S25CB
IDT7187S25Y
IDT7187S30CM
IDT7187S30CB
IDT7187S30L22M
IDT7187S35L22B
IDT7187S35CM
IDT7187S35CB
IDT7187S35L22M
IDT7187S35L22B
IDT7187L20C
IDT7187L20P
IDT7187L20L22
IDT7187L20Y
IDT7187L25C
IDT7187L25CM
IDT7187L25CB
IDT7187L25P
IDT7187L25L22
IDT7187L25CM
IDT7187L25CB
IDT7187L25Y
IDT7187L30CM
IDT7187L30CB
IDT7187L30L22M
IDT7187L35L22B
IDT7187L35CM
IDT7187L35CB
IDT7187L35L22M
IDT7187L35L22B
IDT7188S20C
IDT7188S20P
IDT7188S20L
IDT7188S20Y
IDT7188S25C
IDT7188S25CM
IDT7188S25CB
IDT7188S25L
IDT7188S25LM
IDT7188S25LB
IDT7188S25P
IDT7188S25Y
IDT7188S30C
IDT7188S30CM
IDT7188S30CB
IDT7188S30L
IDT7188S30LM
IDT7188S30LB
IDT7188S30P
IDT7188S30Y
IDT7188S35C
IDT7188S35CM
IDT7188S35CB
IDT7188S35L
IDT7188S35LM
IDT7188S35LB
IDT7188S35P
IDT7188S35Y
IDT7188S45CM
IDT7188S45CB
IDT7188S45LM
NOTE:
A lower case "x· indicates the speed and/or
package of the part are unknown.·
PERFORMANCE
CONT.
lOT
PERFORMANCE
CONT.
IDT
P4C188-45LMB
P4C188-55CM
P4C188-55CMB
P4C188-55LM
P4C188-55LMB
P4C188L-20CC
P4C188L-20PC
P4C188L-20LC
P4C188L-20JC
P4C188L-25CC
P4C188L-25CM
P4C188L-25CMB
P4C188L-25LC
P4C188L-25LM
P4C188L-25LMB
P4C188L-25PC
P4C188L-25JC
P4C188L-30CC
P4C188L-30CM
P4C188L-30CM B
P4C188L-30LC
P4C188L-30LM
P4C188L-30LMB
P4C188L-30PC
P4C188L-30JC
P4C188L-35CC
P4C188L-35CM
P4C188L-35CMB
P4C188L-35LC
P4C188L-35LM
P4C188L-35LMB
P4C188L-35PC
P4C188L-35JC
P4C188L-45CM
P4C188L-45CMB
P4C188L-45LM
P4C188L-45LM B
P4C188L-55CM
P4C188L-55CMB
P4C188L-55LM
P4C188L-55LMB
P4C198-20CC
P4C198-20LC
P4C198-20PC
P4C198-20JC
P4C198-25CC
P4C198-25CM
P4C198-25CMB
P4C198-25LC
P4C198-25LM
P4C198-25LMB
P4C198-25PC
P4C198-25JC
P4C198-30CC
P4C198-30CM
P4C198-30CMB
P4C198-30LC
P4C198-30LM
P4C198-30LMB
P4C198-30PC
P4C198-30JC
P4C198-35CC
P4C198-35CM
P4C198-35CMB
P4C198-35LC
P4C198-35LM
P4C198-35LMB
P4C198-35PC
P4C198-35JC
P4C198-45CM
P4C198-45CMB
P4C198-45LM
P4C198-45LMB
P4C198-55CM
P4C198-55CMB
IDT7188S45LB
IDT7188S55CM
IDT7188S55CB
IDT7188S55LM
IDT7188S55LB
IDT7188L20C
IDT7188L20P
IDT7188L20L
IDT7188L20Y
IDT7188L25C
IDT7188L25CM
IDT7188L25CB
IDT7188L25L
IDT7188L25LM
IDT7188L25LB
IDT7188L25P
IDT7188L25Y
IDT7188L30C
IDT7188L30CM
IDT7188L30CB
IDT7188L30L
IDT7188L30LM
IDT7188L30LB
IDT7188L30P
IDT7188L30Y
IDT7188L35C
IDT7188L35CM
IDT7188L35CB
IDT7188L35L
IDT7188L35LM
IDT7188L35LB
IDT7188L35P
IDT7188L35Y
IDT7188L45CM
IDT7188L45CB
IDT7188L45LM
IDT7188L45LB
IDT7188L55CM
IDT7188L55CB
IDT7188L55LM
IDT7188L55LB
IDT6198S20C
IDT6198S20L
IDT6198S20P
IDT6198S20Y
IDT6198S25C
IDT6198S25CM
IDT6198S25CB
IDT6198S25L
IDT6198S25LM
IDT6198S25LB
IDT6198S25P
IDT6198S25Y
IDT6198S30C
IDT6198S30CM
IDT6198S30CB
IDT6198S30L
IDT6198S30LM
IDT6198S30LB
IDT6198S30P
IDT6198S30Y
IDT6198S35C
IDT6198S35CM
IDT6198S35CB
IDT6198S35L
IDT6198S35LM
IDT6198S35LB
IDT6198S35P
IDT6198S35Y
IDT6198S45CM
IDT6198S45CB
IDT6198S45LM
IDT6198S45LB
IDT6198S55CM
IDT6198S55CB
P4C198-55LM
P4C198-55LMB
P4C198L-20CC
P4C198L-20LC
P4C198L-20PC
P4C198L-20JC
P4C198L-25CC
P4C198L-25CM
P4C198L-25CMB
P4C198L-25LC
P4C198L-25LM
P4C198L-25LMB
P4C198L-25PC
P4C198L-25JC
P4C198L-30CC
P4C198L-30CM
P4C198L-30CMB
P4C198L-30LC
P4C198L-30LM
P4C198L-30LMB
P4C198L-30PC
P4C198L-30JC
P4C198L-35CC
P4C198L-35CM
P4C198L-35CMB
P4C198L-35LC
P4C198L-35LM
P4C198L-35LMB
P4C198L-35PC
P4C198L-35JC
P4C198L-45CM
P4C198L-45CMB
P4C198L-45LM
P4C198L-45LMB
P4C198L-55CM
P4C198L-55CMB
P4C198L-55LM
P4C198L-55LMB
P4C1981-20CC
P4C1981-20LC
P4C1981-20PC
P4C1981-20JC
P4C1981-25CC
P4C1981-25CM
P4C1981-25CMB
P4C1981-25LC
P4C1981-25LM
P4C1981-25LMB
P4C1981-25PC
P4C1981-25JC
P4C1981-30CC
P4C1981-30CM
P4C1981-30CMB
P4C1981-30LC
P4C1981-30LM
P4C1981-30LMB
P4C1981-30PC
P4C1981-30JC
P4C1981-35CC
P4C1981-35CM
P4C1981-35CM B
P4C1981-35LC
P4C1981-35LM
P4C1981-35LMB
P4C1981-35PC
P4C1981-35JC
P4C1981-45CM
P4C1981-45CMB
P4C1981-45LM
P4C1981-45LMB
P4C1981-55CM
P4C1981-55CM B
P4C1981-55LM
P4C1981-55LM B
P4C1981L-20CC
IDT6198S55LM
IDT6198S55LB
IDT6198L20C
IDT6198L20L
IDT6198L20P
IDT6198L20Y
IDT6198L25C
IDT6198L25CM
IDT6198L25CB
IDT6198L25L
IDT6198L25LM
IDT6198L25LB
IDT6198L25P
IDT6198L25Y
IDT6198L30C
IDT6198L30CM
IDT6198L30CB
IDT6198L30L
IDT6198L30LM
IDT6198L30LB
IDT6198L30P
IDT6198L30Y
IDT6198L35C
IDT6198L35CM
IDT6198L35CB
IDT6198L35L
IDT6198L35LM
IDT6198L35LB
IDT6198L35P
IDT6198L35Y
IDT6198L45CM
IDT6198L45CB
IDT6198L45LM
IDT6198L45LB
IDT6198L55CM
IDT6198L55CB
IDT6198L55LM
IDT6198L55LB
IDT71981S20C
IDT71981S20L
IDT71981S20P
IDT71981S20Y
IDT71981S25C
IDT71981S25CM
IDT71981S25CB
IDT71981S25L
IDT71981S25LM
IDT71981 S25LB
IDT71981S25P
IDT71981S25Y
IDT71981S30C
IDT71981S30CM
IDT71981S30CB
IDT71981S30L
IDT71981S30LM
IDT71981 S30LB
IDT71981S30P
IDT71981S30Y
IDT71981S35C
IDT71981S35CM
IDT71981S35CB
IDT71981S35L
IDT71981S35LM
IDT71981S35LB
IDT71981S35P
IDT71981S35Y
IDT71981S45CM
IDT71981S45CB
IDT71981S45LM
IDT71981S45LB
IDT71981S55CM
IDT71981S55CB
IDT71981S55LM
IDT71981S55LB
IDT71981L20C
S1-31
STATIC RAM CROSS REFERENCE GUIDE
PERFORMANCE
CONT.
IDT
P4C1981L-20LC
P4C1981L-20PC
P4C1981L-20JC
P4C1981L-25CC
P4C1981L-25CM
P4C1981L-25CMB
P4C1981 L-25LC
P4C1981L-25LM
P4C1981L-25LMB
P4C1981 L-25PC
P4C1981L-25JC
P4C1981L-30CC
P4C1981L-30CM
P4C1981 L-30CMB
P4C1981L-30LC
P4C1981 L-30LM
P4C1981 L-30LMB
P4C1981 L-30PC
P4C1981L-30JC
P4C1981 L-35CC
P4C1981 L-35CM
P4C1981 L-35CM B
P4C1981 L-35LC
P4C1981 L-35LM
P4C1981 L-35LMB
P4C1981L-35PC
P4C1981 L-35JC
P4C1981 L-45CM
P4C1981L-45CMB
P4C1981L-45LM
P4C1981 L-45LMB
P4C1981L-55CM
P4C1981L-55CMB
P4C1981L-55LM
P4C1981L-55LMB
P4C1982-20CC
P4C1982-20LC
P4C1982-20PC
P4C1982-20JC
P4C1982-25CC
P4C1982-25CM
P4C1982-25CMB
P4C1982-25LC
P4C1982-25LM
P4C1982-25LMB
P4C1982-25PC
P4C1982-25JC
P4C1982-30CC
P4C1982-30CM
P4C1982-30CMB
P4C1982-30LC
P4C1982-30LM
P4C1982-30LM B
P4C1982-30PC
P4C1982-30JC
P4C1982-35CC
P4C1982-35CM
P4C1982-35CM B
P4C1982-35LC
P4C1982-35LM
P4C1982-35LM B
P4C1982-35PC
P4C1982-35JC
P4C1982-45CM
P4C1982-45CMB
P4C1982-45LM
P4C1982-45LMB
P4C1982-55CM
P4C1982-55CMB
P4C1982-55LM
IDT71981 L20L
IDT71981L20P
IDT71981 L20Y
IDT71981L25C
IDT71981L25CM
IDT71981L25CB
IDT71981 L25L
IDT71981 L25LM
IDT71981 L25LB
IDT71981 L25P
IDT71981L25Y
IDT71981L30C
IDT71981L30CM
IDT71981 L30CB
IDT71981 L30L
IDT71981 L30LM
IDT71981 L30LB
IDT71981 L30P
IDT71981 L30Y
IDT71981 L35C
IDT71981 L35CM
IDT71981 L35CB
IDT71981L35L
IDT71981 L35LM
IDT71981 L35LB
IDT71981 L35P
IDT71981 L35Y
IDT71981 L45CM
IDT71981 L45CB
IDT71981 L45LM
IDT71981 L45LB
IDT71981 L55CM
IDT71981L55CB
IDT71981 L55LM
IDT71981L55LB
IDT71982S20C
IDT71982S20L
IDT71982S20P
IDT71982S20Y
IDT71982S25C
IDT71982S25CM
IDT71982S25CB
IDT71982S25L
IDT71982S25LM
IDT71982S25LB
IDT71982S25P
IDT71982S25Y
IDT71982S30C
IDT71982S30CM
IDT71982S30CB
IDT71982S30L
IDT71982S30LM
IDT71982S30LB
IDT71982S30P
IDT71982S30Y
IDT71982S35C
IDT71982S35CM
IDT71982S35CB
IDT71982S35L
IDT71982S35LM
IDT71982S35LB
IDT71982S35P
IDT71982S35Y
IDT71982S45CM
IDT71982S45CB
IDT71982S45LM
IDT71982S45LB
IDT71982S55CM
IDT71982S55CB
IDT71982S55LM
NOTE:
A lower case ·x· indicates the speed and/or
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PERFORMANCE
CONT.
lOT
P4C1982-55LMB
P4C1982L-20CC
P4C1982L-20LC
P4C1982L-20PC
P4C1982L-20JC
P4C1982L-25CC
P4C1982L-25CM
P4C1982L-25CMB
P4C1982L-25LC
P4C1982L-25LM
P4C1982L-25LMB
P4C1982L-25PC
P4C1982L-25JC
P4C1982L-30CC
P4C1982L-30CM
P4C1982L-30CMB
P4C1982L-30LC
P4C1982L-30LM
P4C1982L-30LMB
P4C1982L-30PC
P4C1982L-30JC
P4C1982L-35CC
P4C1982L-35CM
P4C1982L-35CM B
P4C1982L-35LC
P4C1982L-35LM
P4C1982L-35LMB
P4C1982L-35PC
P4C1982L-35J C
P4C1982L-45CM
P4C1982L-45CMB
P4C1982L-45LM
P4C1982L-45LMB
P4C1982L-55CM
P4C1982L-55CMB
P4C1982L-55LM
P4C1982L-55LM B
P4C198A-20CC
P4C198A-20PC
P4C198A-20LC
P4C198A-20JC
P4C198A-25CC
P4C198A-25CM
P4C198A-25CM B
P4C198A-25LC
P4C198A-25LM
P4C198A-25LMB
P4C198A-25PC
P4C198A-25JC
P4C198A-30CC
P4C198A-30CM
P4C198A-30CMB
P4C198A-30LC
P4C198A-30LM
P4C198A-30LMB
P4C198A-30PC
P4C198A-30JC
P4C198A-35CC
P4C198A-35CM
P4C198A-35CMB
P4C198A-35LC
P4C198A-35LM
P4C198A-35LMB
P4C198A-35PC
P4C198A-35JC
P4C198A-45CM
P4C198A-45CMB
P4C198A-45LM
P4C198A-45LMB
P4C198A-55CM
P4C198A-55CMB
P4C198A-55LM
P4C198A-55LMB
IDT71982S55LB
IDT71982L20C
IDT71982L20L
IDT71982L20P
IDT71982L20Y
IDT71982L25C
IDT71982L25CM
IDT71982L25CB
IDT71982L25L
IDT71982L25LM
IDT71982L25LB
IDT71982L25P
IDT71982L25Y
IDT71982L30C
IDT71982L30CM
IDT71982L30CB
IDT71982L30L
IDT71982L30LM
IDT71982L30LB
IDT71982L30P
IDT71982L30Y
IDT71982L35C
IDT71982L35CM
IDT71982L35CB
IDT71982L35L
IDT71982L35LM
IDT71982L35LB
IDT71982L35P
IDT71982L35Y
IDT71982L45CM
IDT71982L45CB
IDT71982L45LM
IDT71982L45LB
IDT71982L55CM
IDT71982L55CB
IDT71982L55LM
IDT71982L55LB
IDT7198S20C
IDT7198S20P
IDT7198S20L
IDT7198S20Y
IDT7198S25C
IDT7198S25CM
IDT7198S25CB
IDT7198S25L
IDT7198S25LM
IDT7198S25LB
IDT7198S25P
IDT7198S25Y
IDT7198S30C
IDT7198S30CM
IDT7198S30CB
IDT7198S30L
IDT7198S30LM
IDT7198S30LB
IDT7198S30P
IDT7198S30Y
IDT7198S35C
IDT7198S35CM
IDT7198S35CB
IDT7198S35L
IDT7198S35LM
IDT7198S35LB
IDT7198S35P
IDT7198S35Y
IDT7198S45CM
IDT7198S45CB
IDT7198S45LM
IDT7198S45LB
IDT7198S55CM
IDT7198S55CB
IDT7198S55LM
IDT7198S55LB
packa 9e of the Part are unknown:
S1-32
PERFORMANCE
CONT.
lOT
P4C198AL-20CC
P4C198AL-20PC
P4C198AL-20LC
P4C198AL-20JC
P4C198AL-25CC
P4C198AL-25CM
P4C198AL-25CMB
P4C198AL-25LC
P4C198AL-25LM
P4C198AL-25LMB
P4C198AL-25PC
P4C198AL-25JC
P4C198AL-30CC
P4C198AL-30CM
P4C198AL-30CMB
P4C198AL-30LC
P4C198AL-30LM
P4C198AL-30LMB
P4C198AL-30PC
P4C198AL-30JC
P4C198AL-35CC
P4C198AL-35CM
P4C198AL-35CMB
P4C198AL-35LC '
P4C198AL-35LM
P4C198AL-35LMB
P4C198AL-35PC
P4C198AL-35JC
P4C198AL-45CM
P4C198AL-45CMB
P4C198AL-45LM
P4C198AL-45LMB
P4C198AL-55CM
P4C198AL-55CMB
P4C198AL:..55LM
P4C198AL-55LMB
IDT7198L20C
IDT7198L20P
IDT7198L20L
IDT7198L20Y
IDT7198L25C
IDT7198L25CM
IDT7198L25CB
IDT7198L25L
IDT7198L25LM
IDT7198L25LB
IDT7198L25P
IDT7198L25Y
IDT7198L30C
IDT7198L30CM
IDT7198L30CB
IDT7198L30L
IDT7198L30LM'
IDT7198L30LB
IDT7198L30P
IDT7198L30Y
IDT7198L35C
IDT7198L35CM
IDT7198L35CB
IDT7198L35L
IDT7198L35LM
IDT7198L35LB
IDT7198L35P
IDT7198L35Y
IDT7198L45CM
IDT7198L45CB
IDT7198L45LM
IDT7198L45LB
IDT7198L55CM
IDT7198L55CB
IDT7198L55LM
IDT7198L55LB
SARATOGA
SSM6116-20SC
SSM6116-20EC
SSM6116-20PC
SSM6116-20DC
SSM6116-25SC
SSM6116-25SB
SSM6116-25EC
SSM6116-25PC
SSM6116-25DC
SSM6116-35SC
SSM6116-35SB
SSM6116-35EC
SSM6116-35PC
SSM6116-35DC
SSM6116-45SB
SSM6167-20CC
SSM6167-25CC
SSM6167-25CB
SSM6167-35CC
SSM6167-35CB
SSM6167-45CB
SSM6168-20SC
SSM6168-20EC
SSM6168-20PC
SSM6168-25SC
SSM6168-25SB
SSM6168-25EC
SSM6168-25PC
SSM6168-35SC
SSM6168-35SB
SSM6168-35EC
SSM6168-35PC
SSM6168-45SB
SSM6171-20SC
lOT
IDT6116SA20D
IDT6116SA20Y
IDT6116SA20P
IDT6116SA20S0
IDT6116SA25D
IDT6116SA25DB
IDT6116SA25Y
IDT6116SA25P
IDT6116SA25S0
IDT6116SA35D
IDT6116SA35DB
IDT6116SA35Y
IDT6116SA35P
IDT6116SA35S0
IDT6116SA45DB
IDT6167SA20D
IDT6167SA25D
IDT6167SA25DB
IDT6167SA35D
IDT6167SA35DB
IDT6167SA45DB
IDT6168SA20D
IDT6168SA20Y
IDT6168SA20P
IDT6168SA25D
IDT6168SA25DB
IDT6168SA25Y
IDT6168SA25P
IDT6168SA35D
IDT6168SA35DB
IDT6168SA35Y
IDT6168SA35P
IDT6168SA45DB
IDT71681SA20D
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
SARATOGA CONT.
lOT
SARATOGA CONT.
lOT
SONY
lOT
SSM6171-20EC
SSM6171-20PC
SSM6171-20DC
SSM6171-25SC
SSM6171-25S8
SSM6171-25EC
SSM6171-25PC
SSM6171-25DC
SSM6171-35SC
SSM6171-35S8
SSM6171-35EC
SSM6171-35PC
SSM6171-35DC
SSM6171-45SB
SSM6172-20SC
SSM6172-20EC
SSM6172-20PC
SSM6172-20DC
SSM6172-25SC
SSM6172-25S8
SSM6172-25EC
SSM6172-25PC
SSM6172-25DC
SSM6172-35SC
SSM6172-35S8
SSM6172-35EC
SSM6172-35PC
SSM6172-35DC
SSM6172-45S8
SSM7161-20SC
SSM7161-20PC
SSM7161-25SC
SSM7161-25SB
SSM7161-25PC
SSM7161-35SC
SSM7161-35SB
SSM7161-35PC
SSM7161-45SB
SSM7162-20SC
SSM7162-20PC
SSM7162-25
SSM7162-25SC
SSM7162-25S8
SSM7162-25PC
SSM7162-35SC
SSM7162-35S8
SSM7162-35PC
SSM7162-45S8
SSM7162L-25
SSM7164-20SC
SSM7164-20PC
SSM7164-25
SSM7164-25SC
SSM7164-25S8
SSM7164-25PC
SSM7164-35SC
SSM7164-35SB
SSM7164-35PC
SSM7164-45SB
SSM7164L-25
SSM7166-20SC
SSM7166-20PC
SSM7166-25SC
SSM7166-25S8
SSM7166-25PC
SSM7166-35SC
SSM7166-35SB
SSM7166-35PC
SSM7166-45SB
SSM7187-25
IDT71681SA20Y
IDT71681SA20P
IDT71681 SA20S0
IDT71681SA25D
IDT71681SA25D8
IDT71681SA25Y
IDT71681SA25P
IDT71681SA25S0
IDT71681SA35D
IDT71681SA35D8
IDT71681 SA35Y
IDT71681SA35P
IDT71681 SA35S0
IDT71681SA45DB
IDT71682SA20D
IDT71682SA20Y
IDT71682SA20P
IDT71682SA20S0
IDT71682SA25D
IDT71682SA25D8
IDT71682SA25Y
IDT71682SA25P
IDT71682SA25S0
IDT71682SA35D
IDT71682SA35D8
IDT71682SA35Y
IDT71682SA35P
IDT71682SA35S0
IDT71682SA45D8
IDT71981SA20D
IDT71981SA20P
IDT71981SA25D
IDT71981SA25DB
IDT71981 SA25P
IDT71981SA35D
IDT71981SA35DB
IDT71981SA35P
IDT71981SA45DB
IDT71982SA20D
IDT71982SA20P
IDT71982S25C
IDT71982SA25D
IDT71982SA25D8
IDT71982SA25P
IDT71982SA35D
IDT71982SA35D8
IDT71982SA35P
IDT71982SA45D8
IDT71982L25C
IDT7164SA20TC
IDT7164SA20TP
IDT7164S25TC
IDT7164SA25TC
IDT7164SA25TCB
IDT7164SA25TP
IDT7164SA35TC
IDT7164SA35TCB
IDT7164SA35TP
IDT7164SA45TCB
IDT7164L25TC
IDT6198SA20D
IDT6198SA20P
IDT6198SA25D
IDT6198SA25D8
IDT6198SA25P
IDT6198SA35D
IDT6198SA35D8
IDT6198SA35P
IDT6198SA45DB
IDT7187S25C
SSM7187L-25
SSM7188-20SC
SSM7188-20PC
SSM7188-25
SSM7188-25SC
SSM7188-25S8
SSM7188-25PC
SSM7188-35SC
SSM7188-35S8
SSM7188-35PC
SSM7188-45SB
SSM7188L-25
SSM7198-20SC
SSM7198-20PC
SSM7198-25
SSM7198-25SC
SSM7198-25SB
SSM7198-25PC
SSM7198-35SC
SSM7198-35SB
SSM7198-35PC
SSM7198-45S8
SSM7198L-25
SSL4180-15SC .
SSL4180-15PC
SSL4180-20SC
SSL4180-20SM
SSL4180-20PC
SSL4180-25SC
SSL4180-25SM
SSL4180-25PC
SSL4180-35SM
SSL4181-15SC
SSL4181-15PC
SSL4181-20SC
SSL4181-20SM
SSL4181-20PC
SSL4181-25SC
SSL4181-25SM
SSL4181-25PC
SSL4181-35SM
IDT7187L25C
IDT7188SA20D
IDT7188SA20P
IDT7188S25C
IDT7188SA25D
IDT7188SA25D8
IDT7188SA25P
IDT7188SA35D
IDT7188SA35D8
IDT7188SA35P
IDT7188SA45DB
IDT7188L25C
IDT7198SA20D
IDT7198SA20P
IDT7198S25C
IDT7198SA25D
IDT7198SA25DB
IDT7198SA25P
IDT7198SA35D
IDT7198SA35D8
IDT7198SA35P
IDT7198SA45D8
IDT7198L25C
IDT6178SA15D
IDT6178SA15P
IDT6178SA20D
IDT6178SA20D8
IDT6178SA20P
IDT6178SA25D
IDT6178SA25DB
IDT6178SA25P
IDT6178SA35D8
IDT7178SA15D
IDT7178SA15P
IDT7178SA20D
IDT7178SA20DB
IDT7178SA20P
IDT7178SA25D
IDT7178SA25DB
IDT7178SA25P
IDT7178SA35DB
CXK5416P-35
CXK5416P-45
CXK5416P-55
CXK5464P-45
CXK5464P-55
CXK5464P-70
CXK5814P-35
CXK5814P-45
CXK5814P-55
CXK5818PN-10
CXK5818M-10
CXK58256P-10
CXK58256M-10
CXK5864AP-70L
CXK5864AM-70L
CXK5865P-45L
CXK5865P-55L
IDT6168LA35P
IDT6168LA35P
IDT6168LA35P
IDT7188L45P
IDT7188L45P
IDT7188L45P
IDT6116LA35TP
IDT6116LA45TP
IDT6116LA45TP
IDT6116L45P
IDT6116L45S0
IDT71256L70P
IDT71256L70S0
IDT7164L45P
IDT7164L45S0
IDT7164L45P
IDT7164L55P
SGS-THOMSON
lOT
MK41H67N-20
MK41H67N-25
MK41H67N-35
MK41H68N-20
MK41H68N-25
MK41H68N-35
MK41H78N-20
MK41H78N-25
MK41H78N-35
MK41 H80N-20
MK41H80P-20
MK41 H87N-25
MK41H87N-35
MK41H87N-45
IDT6167S20P
IDT6167S25P
IDT6167S35P
IDT6168L20P
IDT6168L25P
IDT6168L35P
IDT61970S20P
IDT61970S25P
IDT61970S35P
IDT6178S20P
IDT6178S20D
IDT7187S25P
IDT7187S35P
IDT7187S45P
NOTE:
A lower case ·x· indicates the speed and/or
package of the part are unknown:
S1-33
TI
lOT
SMJ61 CD16-25M
SMJ61 CD16-35M
SMJ61 CD16-45M
SMJ64C16-25M
SMJ64C16-35M
SMJ64C16-45M
SMJ68CE16-25M
SMJ68CE16-35M
SMJ68CE16-45M
SMJ61 CD64-25M
SMJ61 CD64-35M
SMJ61 CD64-45M
SMJ64C64-25M
SMJ64C64-35M
SMJ64C64-45M
SMJ68CE64-25M
SMJ68CE64-35M
SMJ68CE64-45M
SMJ61 CD256-35M
SMJ61 CD256-45M
SMJ61 CD256-55M
SMJ64C256-35M
SMJ64C256-45M
SMJ64C256-55M
SMJ68CE256-45M
SMJ68CE256-55M
SMJ68CE256-70M
SMJ69CE72-25M
SMJ69CE72-35M
SMJ69CE72-45M
SMJ69CE288-35M
SMJ69CE288-45M
SMJ69CE288-55M
IDT6167-258
IDT6167-35B
IDT6167-458
IDT6168-25B
IDT6168-358
IDT6168-458
IDT6116-258
IDT6116-358
IDT6116-458
IDT7187-258
IDT7187-358
IDT7187-458
IDT7188-258
IDT7188-358
IDT7188-458
IDT7164-25B
IDT7164-358
IDT7164-45B
IDT71257-35B
IDT71257-458
IDT71257-55B
IDT71258-358
IDT71258-458
IDT71258-55B
IDT71256-458
IDT71256-558
IDT71256-70B
IDT7169-258
IDT7169-358
IDT7169-458
IDT71259-358
IDT71259-458
IDT71259-55B
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATIC RAM CROSS REFERENCE GUIDE
TOSHIBA
IDT
VTI
lOT
TM M2018AD-25
TM M2018AP-25
TM M2018AD-35
TMM2018AP-35
TMM2068AP-25
TMM2068AP-35
TC55417P-35
TC55417P-45
TC5562P-45
IDT6116SA25TD
IDT6116SA25TP
IDT6116SA35TD
IDT6116SA35TP
IDT6168SA25P
IDT6168SA35P
IDT6198S35P
IDT6198S45P
ID17187S45P
VT16H4-35
VT16H4-45
VT16H4-55
VT20C18-20
VT20C18-25
VT20C18-35
VT20C19-25
VT20C19-35
VT20C68-20
VT20C68-25
VT20C68-35
VT20C68-45
VT20C69-20
VT20C69-25
VT20C69-35
VT20C69-45
VT2130
VT65KS4-25·
VT65KS4-35CC
VT65KS4-45CC
VT65KS4-55CC
VT7132-55
VT7132-70
VT7132-90
VT7132A-35
VT7132A-45
VT7142-55
VT7142-70
VT7142-90
VT7142A-35
VT7142A-45
ID171981-35
ID171981-45
ID171981-45
ITD6116SA20TP
ITD6116SA25TP
ITD6116SA35TP
IDT6116SA15TP
IDT6116SA20TP
IDT6168SA20P
IDT6168SA25P
IDT6168SA35P
IDT6168SA35P
IDT6168SA12P
IDT6168SA15P
IDT6168SA20P
IDT6168SA25P
ID17130SA100P
ID17188S25P
ID17188S35C
ID17188S45C
ID17188S45C
ID17132SA55D
ID17132SA70D
ID17132SA90D
ID17132SA35D
ID17132SA45D
ID17142SA55D
ID17142SA70D
ID17142SA90D
ID17142SA35D
ID17142SA45D
VITELIC
V61C16P35
V61C16P35L
V61C16P45
V61C16P45L
V61C16P55
V61C16P55L
V61C16S35
V61C16S35L
V61C16S45
V61C16S45L
V61C16S55
V61C16S55L
V61C32P70
V61C32P70L
V61C32P90
V61C32P90L
V61C34P90
V61C62P45
V61C62P45L
V61C62P55
V61C62P55L
V61C62P70
V61C62P70L
V61C64P45
V61C64P45L
V61C64P55
V61C64P55L
V61C64P70
V61C64P70L
V61C67P35
V61C67P35L
V61C67P45
V61C67P45L
V61C67P55
V61C67P55L
V61C68P35
V61C68P35L
V61C68P45
V61C68P45L
V61C68P55
V61C68P55L
IDT
IDT6116SA35P
IDT6116LA35P
IDT6116SA45P
IDT6116LA45P
IDT6116SA45P
IDT6116LA45P
IDT6116SA35TP
IDT6116LA35TP
IDT6116SA45TP
IDT6116LA45TP
IDT6116SA45TP
IDT6116LA45TP
IDT7132SA70P
IDT7132LA70P
IDT7132SA90P
IDT7132LA90P
IDT71322S90P
IDT7188S45P
IDT7188L45P
IDT7188S45P
IDT7188L45P
IDT7188S45P
IDT7188L45P
IDT7164S45P
IDT7164L45P
IDT7164S45P
IDT7164L45P
IDT7164S45P
IDT7164L45P
IDT6167SA35P
IDT6167LA35P
IDT6167SA35P
IDT6167LA35P
IDT6167SA35P
IDT6167LA35P
IDT6168SA35P
IDT6168LA35P
IDT6168SA35P
IDT6168LA35P
IDT6168SA35P
IDT6168LA35P
NOTE:
A lower case "x" indicates the speed and/or
package of the part are unknown.·
S1-34
t;J
Integrated Device~ Inc.
CYPRESS
CY7C130-35PC
CY7C130-35DC
CY7C130-35LC
CY7C130-35JC
CY7C130-45PC
CY7C130-45DC
CY7C130-45LC
CY7C130-45JC
CY7C130-45DMB
CY7C130-45LM B
CY7C130-55PC
CY7C130-55DC
CY7C130-55LC
CY7C130-55JC
CY7C130-55DMB
CY7C130-55LM B
CY7C132-35PC
CY7C132-35DC
CY7C132-35LC
CY7C132-35JC
CY7C132-45PC
CY7C132-45DC
CY7C132-45LC
CY7C132-45JC
CY7C132-45DMB
CY7C132-45LMB
CY7C132-55PC
CY7C132-55DC
CY7C132-55LC
CY7C132-55JC
CY7C132-55DMB
CY7C132-55LMB
CY7C140-35PC
CY7C140-35DC
CY7C140-35LC
CY7C140-35JC
CY7C140-45PC
CY7C140-:-45DC
CY7C140-45LC
CY7C140-45JC
CY7C140-45DMB
CY7C140-45LMB
CY7C140-55PC
CY7C140-55DC
CY7C140-55LC
CY7C140-55JC
CY7C140-55DMB
CY7C140-55LMB
CY7C142-35PC
CY7C142-35DC
CY7C142-35LC
CY7C142-35JC·
CY7C142-45PC
CY7C142-45DC
CY7C142-45LC
CY7C142-45JC
CY7C142-45DMB
CY7C142-45LMB
CY7C142-55PC
CY7C142-55DC
CY7C142-55LC
CY7C142-55JC
CY7C142-55DMB
CY7C142-55LM B
MULTI-PORT PRODUCTS
CROSS REFERENCE GUIDE
lOT
IDT7130SA35P
IDT7130SA35C
IDT7130SA35L48
IDT7130SA35J
IDT7130SA45P
IDT7130SA45C
IDT7130SA45L48
IDT7130SA45J
IDT7130SA45CB
IDT7130SA45L48B
IDT7130SA55P
IDT7130SA55C
IDT7130SA55L48
IDT7130SA55J
IDT7130SA55CB
IDT7130SA55L48B
.IDT7132SA35P
IDT7132SA35C
IDT7132SA35L48
IDT7132SA35J
IDT7132SA45P
IDT7132SA45C
IDT7132SA45L48
IDT7132SA45J
IDT7132SA45CB
IDT7132SA45L48B
IDT7132SA55P.
IDT7132SA55C
IDT7132SA55L48
IDT7132SA55J
IDT7132SA55CB
IDT7132SA55L48B
IDT7140SA35P
IDT7140SA35C
IDT7140SA35L48
IDT7140SA35J
IDT7140SA45P
IDT7140SA45C
IDT7140SA45L48
IDT7140SA45J
IDT7140SA45CB
IDT7140SA45L48B
IDT7140SA55P
IDT7140SA55C
IDT7140SA55L48
IDT7140SA55J
IDT7140SA55CB
IDT7140SA55L48B
IDT7142SA35P
IDT7142SA35C
IDT7142SA35L48
IDT7142SA35J
IDT7142SA45P
IDT7142SA45C
IDT7142SA45L48
IDT7142SA45J
IDT7142SA45CB
IDT7142SA45L48B
IDT7142SA55P
IDT7142SA55C
IDT7142SA55L48
IDT7142SA55J
IDT7142SA55CB
IDT7142SA55L48B
AMO
lOT
VLSI
lOT
AM2130-55PC
AM2130-55DC
AM2130-55LC
AM2130-55JC
AM2130-70PC
AM2130-70DC
AM2130-70LC
AM2130-70JC
AM2130-70/BXC
AM2130-10PC
AM2130-10DC
AM2130-10LC
AM2130-10JC
AM2130-10/BXC
AM2130-12/BXC
AM2140-55PC
AM2140-55DC
AM2140-55LC
AM2140-55JC
AM2140-70PC
AM2140-70DC
AM2140-70LC
AM2140-70JC
AM2140-70/BXC
AM2140-10PC
AM2140-10DC
AM2140-10LC
AM2140-10JC
AM2140-10/BXC
AM2140-12/BXC
IDT7130SA55P
IDT7130SA55C
IDT7130SA55L52
IDT7130SA55J
IDT7130SA70P
IDT7130SA70C
IDT7130SA70L52
IDT7130SA70J
IDT7130SA70CB
IDT7130SA100P
IDT7130SA100C
IDT7130SA100L52
IDT7130SA100J
IDT7130SA100CB
IDT7130SA120CB
IDT7140SA55P
IDT7140SA55C
IDT7140SA55L52
IDT7140SA55J
IDT7140SA70P
IDT7140SA70C
IDT7140SA70L52
IDT7140SA70J
IDT7140SA70CB
IDT7140SA100P
IDT7140SA100C
IDT7140SA100L52
IDT7140SA100J
IDT7140SA1OOCB
IDT7140SA120CB
VT7132A-35PC
VT7132A-45PC
VT7132-55PC
VT7132-55QC
VT7132-70PC
VT7132-70QC
VT7132-90PC
VT7132-90QC
VT7142A-35PC
VT7142A-45PC
VT7142-55PC
VT7142-55QC
VT7142-70PC
VT7142-70QC
VT7142-90PC
VT7142-90QC
IDT7132SA35P
IDT7132SA45P
IDT7132SA55P
IDT7132SA55J
IDT7132SA70P
IDT7132SA70J
IDT7132SA90P
IDT7132SA90J
IDT7142SA35P
IDT7142SA45P
IDT7142SA55P
IDT7142SA55J
IDT7142SA70P
IDT7142SA70J
IDT7142SA90P
IDT7142SA90J
51-35
. _ - - - - - - - - - - - - - - - - - - - _ . _ - - - _ .. -----
t;)
FIFO 'CROSS'REFERENCE GUIDE
Inresmted Device1edmoIogy.1nc.
LARGE FIFOs
SMALL FIFOs
AMD
lOT
AMD
lOT
67401
57401AJB
57401BJB
57401JB
67401AJ
67401 AN
67401BJ
67401J'
67401N
C57401AJB
C57401BJB
C57401JB
C57L401DJB
C67401AJ
C67401AN
C67401BJ
C67401J
C67401N
C67L401DJ
C67L401DN
67402
57402AJB
57402BJB
57402JB
67402AJ
67402AN
67402BJ
67402J
67402N
C57402AJB
C57402BJB
C57402JB
C57L402DJB
C67402AJ
C67402AN
C67402BJ
C67402J
C67402N
C67L402DJ
C67L402DN
67C4013
67C4013-10N
67C4013-10J
67C4013-15N
67C4013-15J
67C4023
67C4023-10N
67C4023-10J
67C4023-15N
67C4023-15J
67411
57411JB
67411AJ
67411J
67412
57412JB
67412AJ
67412J
67413
57413JB
67413AJ
67413J
72401
72401L15DB
72401L25DB
72401L10DB
72401L15D'
72401L15P
72401L25D
72401L10D
72401L10P
72401L15DB
72401L25DB
72401L10DB
72401L15DB
72401L15D
72401L15P
72401L25D
72401L10D
72401L10P
72401L15D
72401L15P
72402
72402L15DB
72402L25DB
72402L10DB
72402L15D
72402L15P
72402L25D
72402L10D
72402L10P
72402L15DB
72402L25DB
72402L10DB
72402L15DB
72402L15D
72402L15P
72402L25D
72402L10D
72402L10P
72402L25D
72402L15P
72403
72403L10P
72403L10D
72403L15P
72403L15D
72404
72404L10P
72404L10D
72404L15P
72404L15D
72401
72401L25DB
72401L35D
72401L25D
72402
72402L25DB
72402L35D
72402L25D
72413
72413L25DB
72413L35D
72413L25D
67C4'SOl
67C4501-35J
67C4501-35N
67C4501-35NL
67C4501-50J
67C4501-50N
67C4501-50N L
67C4501-65J
67C4501-65N
67C4501-65NL
67C4501-80J
67C4501-80N
67C4501-80NL
67C4S02
67C4502-35J
67C4502-35N
67C4502-35NL
67C4502-50J
67C4502-50N
67C4502-50NL
67C4502-65J
67C4502-65N
67C4502-65NL '
67C4502-80J
67C4502-80N
67C4502-80NL
67C4S03
67C4503-35N .
67C4503-50N
67C4503-65N
67C4503-80N
7201
7201SA35D
7201SA35P
7201SA35J'
7201SA50D'
7201SA50P
7201SA50J
7201SA65D
7201SA65P
7201SA65J
7201SA80D
7201SA80P
7201SA80J
7202
7202SA35D
7202SA35P
7202SA35J
7202SA50D
7202SA50P
7202SA50J
7202SA64D
7202SA65P
7202SA65J
7202SA80D
7202SA80P
7202SA80J
7203
7203S35P
7203S50P
7203S65P
7203S80P
CYPRESS
7C401
7C401-10DC
7C401-10DMB
7C401-10LC
7C401-10LMB
7C401-10PC
7C401-15DC
7C401-15DMB
7C401-15LC
7C401-15LMB
7C401-15PC
7C402
7C402-10DC
7C402-10DMB
7C402-10LC
7C402-10LMB
7C402-10PC
7C402-15DC
7C402-15DMB
7C402-15LC
7C402-15LMB
7C402-15PC
7C403
7C403-10DC
7C403-10DMB
7C403-10LC
7C403-10LMB
7C403-10PC
lOT
72401
72401L10D
72401L10DB
72401 L10L
72401L10LB
72401L10P
72401L15D
72401L15DB
72401L15L
72401L15LB
72401L15P
72402
72402L10D
72402L10DB
72402L10L
72402L10LB
72402L10P
72402L15D
72402L15DB
72402L15L
72402L15LB
72402L15P
72403
72403L10D
72403L10DB
72403L10L
72403L10LB
72403L10P
S1-36
CYPRESS CONT.
lOT
7C403-15DC
7C403-15DMB
7C403-15LC
7C403-15LMB
7C403-15PC
7C403-25DC
7C403-25DMB
7C403-25LC
7C403-25LMB
7C403-25PC
7C404,
7C404-10DC
7C404-10DMB
7C404-10LC
7C404-10LMB
7C404-10PC
7C404-15DC
7C404-15DMB'
7C404-15LC
7C404-15LMB
7C404-15PC
7C404-25DC
7C404-25DMB
7C404-25LC
7C404-25LMB
7C404-25PC
72403L15D
72403L15DB
72403L15L
72403L15LB
72403L15P
72403L25D
72403L25DB
72403L25L
72403L25LB
72403L25P
72404
72404L10D
72404L10DB
72404L10L
72404L10LB
72404L10P
72404L15D
72404L15DB
72404L15L
72404L15LB
72404L15P
72404L25D
72404L25DB
72404L25L
72404L25LB
72404L25P
DALLAS
DS2009
DS2009-35
DS2009-50
DS2009-65
DS2009-80
DS2010
DS2010-35
DS2010-50
DS2010-65
DS2010-80
DS2011
DS2011-35 '.
DS2011-50
DS2011-65
DS2011-80
MOSTEK
MK4S01
MK4501-10N
MK4501-12N
MK4501-65N
MK4501-80N .
TI
SN74ACT7201
SN74ACT7201A-35N
SN74ACT7201 A-50N
SN74ACT7202
SN74ACT7202-35N
SN74ACT7202-50N ,
lOT
7201
7201SA35P
7201SA50P
7201SA65P
7201SA80P
7202
7202SA35P
7202SA50P
7202SA65P
7202SA80P
7203
7203SA35P
7203SA50P
7203SA65P
7203SA80P
lOT
7201
7201S80P
7201S120P
7201S65P
7201S80P
lOT
7201
7201LA35P
7201LA50P
7202
7202L35P
7202L50P
:
t;)
Intesrated Device1echnoIogy. Inc.
DSP DIVISION'
DIGITAL SIGNAL PROCESSING
CROSS REFERENCE GUIDE
CYPRESS CONT.
ANALOG DEVICES
lOT
ADSP-1009
ADSP-1009JD
ADSP-1009KD
ADSP-1009SD
ADSP-1009TD
ADSP-1012
ADSP-1012JD
ADSP-1012KD
ADSP-1012SD
ADSP-1012TD
ADSP-1010
ADSP-1010AKD
ADSP-1010AKG
ADSP-1010JD
ADSP-1010JG
ADSP-1010KD
ADSP-1010KG
ADSP-1010SD
ADSP-1010SG
ADSP-1010TD
ADSP-1010TG
ADSP-1016
ADSP-1016AKD
ADSP-1016AKG
ADSP-1016JD
ADSP-1016JG
ADSP-1016KD
ADSP-1016KG
ADSP-1016SD
ADSP-1016SG
ADSP-1016TD
ADSP-1016TG
7209
7209L135C.
7209L135C
7209L170CB
7209L170CB
7212
7212L115C
7212LL115C
7212L140CB
7212L140CB
7210
7210L75C
7210L75G
7210L165C
7210L165G
7210L165C
7210L165G
7210L200CB
7210L200GB
7210L200CB
7210L200GB
7216
7216L75C
7216L75G
7216L140C
7216L140G
7216L140C
7216L140G
7216L185CB
7216L185GB
7216L120CB
7216L120GB
CYPRESS
lOT
7C510
7C510-45DC
7C510-45GC
7C510-45LC
7C510-45PC
7C510-55DC
7C510-55DMB
7C510-55GC
7C510-55GMB
7C510-55LC
7C510-55LMB
7C510-55PC
7C510-65DC
7C510-65DMB
7C510-65GC
7C510-65GMB
7C510-65LC
7C510-65LMB
7C510-65PC
7C510-75DC
7C510-75DMB
7C510-75GC
7C510-75GMB
7C510-75LC
7C510-75LMB
7C510-75PC
7C516
7C516-38DC
7210
7210L45D
7210L45G
7210L45L
7210L45P
7210L55D
7210L55DB
7210L55G
7210L55GB
7210L55L
7210L55LB
7210L55P
7210L65D
7210L65DB
7210L65G
7210L65GB
7210L65L
7210L65LB
7210L65P
7210L75D
7210L75DB
7210L75G
7210L75GB
7210L75L
7210L75LB
7210L75P
7216
7216L35D
7C516-38GC
7C516-38LC'
7C516-38PC
7C516-42DMB
7C516-42GMB
7C516-42LMB
7C516-45DC
7C516-45GC
7C516-45LC
7C516-45PC
7C516-55DC
7C516-55DMB
7C516-55GC
7C516-55GMB
7C516-55LC
7C516-55LMB
7C516::'55PC
7C516-65DC
7C516-65DMB
7C516-65GC
7C516-65GMB
7C516-65LC
7C516-65LMB
7C516-65PC
7C516-75DC
7C516-75DMB
7C516-75GC
7C516-75GMB
7C516-75LC
7C516-75LMB
7C516-75PC
7C517
7C517-45DC
7C517-45GC
7C517-45LC
7C517-45PC
7C517-55DC
7C517-55DMB
7C517-55GC
7C517-55GMB
7C517-55LC
7C517-55LMB
7C517-55PC
7C517-65DC
7C517-65DMB
7C517-65GC
7C517-65GMB
7C517-65LC
7C517-65LMB
7C517-65PC
7C517-75DC
7C517-75DMB
7C517-75GC
7C517-75GMB
7C517-75LC
7C517-75LMB
7C517-75PC
LOGIC DEVICES
LMA1009
LMA 1009DC-45
LMA 1009GC-45
LMA 1009DMB-55
LMA1009GMB-55
LMA1009DC-75
7216L35G
7216L35L
7216L35P
7216L40DB
7216L40GB
7216L40LB
7216L45D
7216L45G
7216L45L
7216L45P
7216L55D
7216L55DB
7216L55G
7216L55GB
7216L55L
7216L55LB
7216L55P
7216L65D
7216L65DB
7216L65G
7216L65GB
7216L65L
7216L65LB
7216L65P
7216L75D
7216L75DB
7216L75G
7216L75GB
7216L75L
7216L75LB
,7216L75P
7217
7217L45D .
7217L45G
7217L45L
7217L45P
7217L55D
7217L55DB
7217L55G
7217L55GB
7217L55L
7217L55LB
'7217L55P
7217L65D .' .
7217L65DB
7217L65G
7217L65GB
7217L65L
7217L65LB
7217L65P
7217L75D
7217L75DB
7217L75G
7217L75GB
7217L75L
7217L75LB
7217L75P
lOT
7209
7209L45C
7209L45G
7209L55CB
7209L55GB
7209L65C
51-37
- - _...... _ - - - - - - - - - -
LOGIC DEVICES
CONT.
LMA1009GC-75
LMA1009DC-90
LMA1009GC-90
LMA1009DMB-95
LMA1009GMB-95
LMA1009DMB-115
LMA1009GMB-115
LMA2009
LMA2009KC-45
LMA2009KM B-55
LMA2009KC-55
lOT
LMA2009KMB~65
.
LMA2009KC-75
LMA2009KC-90
LMA2009KM B-95
LMA2009KMB-115
LMA1010
LMA1010PC-45
LMA1010DC";45
LMA1010GC-45
LMA1010PC-55
LMA1010DC-:-55
LMA1010GC-55
LMA1010DBM-55
LMA1010GMB-55
LMA 101 OPC-65
LMA1010DC-65
LMA1010GC-65 .
LMA1010DMB-65
LMA1010GMB-65
LMA1010DMB-75
LMA1010GMB-75
LMA1010PC
LMA1010DC
LMA1010GC
LMA1010DMB
LMA1010GMB
LMA2010
LMA2010JC-45
LMA2010KC-45: .
LMA2010JC-55
LMA2010KC-55
LMA2010KMB-55
LMA2010JC-65
LMA2010KC-65
LMA2010KMB-65
LMA2010KMB-75
LMA2010JC
LMA2010KC .
LMA2010KMB
LMA1043
LMA 1043PC-45 .
LMA 1043DC-45
LMA 1043GC-45
LMA1043PC-55 .
LMA 1043DC-55
LMA1043GC-55
LMA 1043DMB-55
LMA1043GMB-55
LMA 1043PC-65
LMA 1043DC-65
LMA 1043GC-65
LMA1043DMB-65 .
LMA1043GMB-65
LMA1043DMB-75
LMA1043GMB-75
lOT
7209L65G
7209L65C
7209L65G
7209L75CB
7209L75GB
7209L75CB
7209L75GB
7209
7209L45L
.7209L55LB
.7209L45L
7209L55LB
7209L65L
7209L65L
7209L75LB
7209L75LB
7210
7210L45P
7210L45C
7210L45G
7210L55P
7210L55C
7210L55G
7210L55CB
7210L55GB
7210L65P
7210L65C
7210L65G
7210L65CB
7210L65GB
7210L75CB
7210L75GB,
7210L100P
,7210L100C
7210L100G
7210L120CB
7210L120GB
7210
7210L45J
7210L45L
7210L55J
7210L55L
7210L55LB
7210L65J
7210L65L
7210L65LB
7210L75LB
7210L100J
721 OL1 OOL
7210L120LB
7243
7243L45P
7243L45D
7343L45G
7243L55P
7243L55D
. ,7243L55G
7243L55DB
7243L55GB
7243L65P
'7243L65D
7243L65G '
7243L65DB
7243L65GB
7243L75DB
7243L75GB
DIGITAL SIGNAL PROCESSING CROSS REFERENCE GUIDE
.
DSP DIVISION CONT.
LOGIC DEVICES
CONT.
LMA1043PC
LMA1043DC
LMA1043GC
LMA1043DMB
LMA1043GMB
LMA2043
LMA2043JC-45
LMA2043KC-45
LMA2043JC-55
LMA2043KC-55
LMA2043KMB-55
LMA2043JC-65
LMA2043KC-65
LMA2043KMB-65
LMA2043KMB-75
LMA2043JC
LMA2043KC
LMA2043KMB
LMU12
LMU12DC-35
LMU12DC-45
LMU12DMB-45
LMU12DMB-55
LMU12DC-65
LMU12DMB-75
LMU12DC
LMU12DMB
LMU16
LMU16PC-45
LMU16DC-45
LMU16GC-45
LMU16PC-55
LMU16DC-55
LMU16GC-55
LMU16DMB-55
LMU16GMB-55
LMU16PC-65
LMU16DC-65
LMU16GC-65
LMU16DMB-65
LMU16GMB-65
LMU16DMB-75
LMU16GMB-75
LMU16PC
LMU16DC
LMU16GC
LMU16DMB
LMU16GMB
LMU216
LMU216JC-45
LMU216KC-45
LMU216JC-55
LMU216KC-55
LMU216KMB-55
LMU216JC-65 .
LMU216KC-65
LMU216KMB-65
LMU216KMB-75
LMU216JC
LMU216KC
LMU216KMB
LMU17
LMU17PC-45
LMU17DC-45
LMU17GC-45
LMU17PC-55
LMU17DC-55
LMU17GC-55
LMU17DMB-55
LMU17GMB-55
LMU17PC-65
LMU17DC-65
IDT
7243L100P
7243L100D
7243L100G
7243L120DB
7243L120GB
7243
7243L45J
7243L45L
7243L55J
7243L55L
7243L55LB
7243L65J
7243L65L
7243L65LB
7243L75LB
7243L100J
7243L100L
7243L120LB
7212
7212L35C
7212L45C
. 7212L40CB
7212L55CB
7212L45C
7212L55CB
7212L70C
7212L90CB
7216
7216L45P
7216L45C
7216L45G
7216L55P
7216L55C
7216L55G
7216L55CB
7216L55GB
7216L65P
7216L65C
7216L65G
7216L55CB
7216L55GB
7216L75CB
7216L75GB
7216L65P
7216L65C
7216L65G
7216L90CB
7216L90GB
7216
7216L45J
7216L45L
7216L55J'
7216L55L
7216L55LB
7216L65J
7216L65L
7216L65LB
7216L75LB
7216L75J
7216L75L
7216L90LB
7217
7217L45P
7217L45C
7217L45G
7217L55P
7217L55C
7217L55G
7217L55CB
7217L55GB
7217L65P
7217L65C
LOGIC DEVICES
CONT.
lOT
TRWCONT.
LMU17GC-65
LMU17DMB-65
LMU17GMB-65
LMU17DMB-75
LMU17GMB-75
LMU17PC
LMU17DC
LMU17GC
LMU17DMB
LMU17GMB
LMU217
LMU217JC-45
LMU217KC-45
LMU217JC-55
LMU217KC-55
LMU217KMB-55
LMU217JC-65
LMU217KC-65
LMU217KMB-65
LMU217KMB-75
LMU217JC
LMU217KC
LMU217KMB
7217L65G
7217L55CB
7217L55GB
7217L75CB
7217L75GB
7217L65P
7217L65C
7217L65G
7217L90CB
7217L90GB
7217
7217L45J
7217L45L
7217L55J
7217L55L
7217L55LB
7217L65J
7217L65L
7217L65LB
7217L75LB
7217L75J
7217L75L
7217L90LB
TMC2010
TMC2010C1C
TMC2010C1C
TMC2010C1F
TMC2010C1G
TMC2010J3A
TMC2010J3C
TMC2010J3F
TMC2010J3G
TMC2110
TMC2110C1C
TMC2110C1C
TMC2110C1F
TMC2110C1G
TMC2110J3C
TMC2110J3C
TMC2110J3F
TMC2110J3G
TRW
.IDT
MPY012
MPY012HJ1A
MPY012HJ1C
MPY012HJ1G
MPY016
MPY016HJ1A
MPY016HJ1C
MPY016HJ1G
MPY016KJ1A
MPY016KJ1A1
MPY016KJ1C
MPY016KJ1C1
MPY016KJ1G
MPY016KJ1G1
TMC216H
TMC216HC1A
TMC216HC1C
TMC216HC1G
TMC216HJ3A
TMC216HJ3C
TMC216HJ3G
TDC1009
TDC1009C1A
TDC1009C1F
TDC1 009J1 A
TDC1009J1C
TDC1009J1F .
TDC1009J1G
TDC1010
TDC1010C1A
TDC1010C1F
TDC1010J1A
TDC1010J1C
TDC1010J1F
TDC1010J1G
TDC1043
TDC1043C1C
TDC1043C1G
TDC1043J3C
TDC1043J3G
TMC2009
TMC2009C1A
TMC2009C1C
TMC2009C1F
TMC2009C1G
TMC2009J3A
TMC2009J3C
TMC2009J3F
TMC2009J3G
7212
7212L140CB
7212L115C
7212L115C
7216
7216L185CB
7216L140C
7216L140C
.7216L45CB
7216L45CB
7216L45C
7216L35C
7216L45C
7216L35C
7216
7216L185LB
7216L140L
7216L140L
7216L185CB
7216L140C
7216L140C
7209
7209L170LB
7209L170LB
7209L170CB
7209L135C
7209L170CB
7209L135C
7210
7210L200LB
7210L200LB
7210L200CB
7210L165C
7210L200CB
7210L165C
7243
7243L100L
7243L100L
7243L100C
7243L100C
7209
7209L170LB
7209L135L
7209L120LB
7209L135L
7209L170CB
7209L135C
7209L120CB
7209L135C
Sl-38
lOT
7210
7210L165L
7210L200LB
7210L200LB
7210L165L
7210L200CB.
7210L165C
7210L200CB
7210L165C
7210
7210L100L·
7210L120LB
7210L120LB
7210L100L
7210L100C
7210L120CB
7210L120CB
7210L100C
t;)
MICROSLICE CROSS REFERENCE GUIDE
IntesJated Devlce~Inc.
AMO
lOT
AMO (CONT.)
\DT
CYPRESS
lOT
2901B
2901C
2901 CDC
2901CDCB
2901CLC
2901CPC
2901CPCB
2901C/BOA
2901C/BUA
2901C/BUC
29C01
29C01DC
29C01DCB
29C01PC
29C01PCB
29C01/BOA
29C01/BUA
29C01-1
29C01-1DC
29C01-1DCB
29C01-1PC
29C01-1PCB
2903
2903A
2903ADC
2903ADCB
2903ALC
2903ADMB
2903A/BXC
2903ALMB
2910 or -1
2910A
2910ADC
2910ADCB
2910ALC
2910APC
2910APCB
2910A/BOA
2910A/BUC
29Cl0A
29C10ADC
29C10AJC
29C10AJCB
29C10ALC
29C10APC
29C10APCB
29C10A/BOA
29C10A/BUA
29Cl0A-1
29C10A-1DC
29C10A-1DCB
29C10A-1JC
29C10A-1JCB
29C10A-1PC
29C10A-1PCB
29C101
29C111
39C01C
39C01C
39C01CD
39C01CD
39C01CL
39C01CP
39C01CP
39C01CDB
39C01CLB
39C01CLB
39C01C
39C01CD
39C01CD
39C01CP
39C01CP
39C01CDB
39C01CLB
39C01C
39C01CD
39C01CD
39C01CP
39C01CP
39C03A
39C03A
39C03AC
39C03AC
39C03AL
39C03ACB
39C03ACB
39C03ALB
39C10B
39C10B
39C1oBD
39C1oBD
39C1oBL
39C1oBP
39C1oBP
39C1DBDB
39C1oBLB
39Cl0B
39C1oBD
39C1oBJ
39C10BJ
39C1oBL
39C1OBP
39C10BP
39C1oBDB
39C1oBLB
39C10C
39C10CD
39C1oCD
39C1oCJ
39C10CJ
39C10CP
39C1OCP
49C402
49C410
29C660
29C660A
29C660B
29C660C
2960
2960DC
2960DCB
2960JC
2960JCB
2960LC
2960PC
2960PCB
2960/BXC
2960/BUC
29C60
29C60DC
29C60DCB
29C60JC
29C60LC
29C60LCB
2960-1
2960-1DC
296o-1DCB
2960-1JC
2960-1JCB
2960-1LC
2960-1 PC
2960-1 PCB
2960-1/BXC
2960-1/BUC
29C60-l
29C6o-1DC
29C60-1DCB
29C60-1JC
29C60-1LC
29C60-1LCB
29C6o-1PC
29C60-1PCB
29C60-1/BXC
2960A
2960ADC
2960ADCB
2960AJC
2960ALC
2960APC
2960APCB
29C60A
29C60ADC
29C60ADCB
29C60AJC
29C60ALC
29C6oALCB
29C60APC
29C60APCB
29C6oA/BXC
29C60A/BUA
49C460
49C460A
49C460B
49C460C
39C60
39C6oC
39C6oC
39C60J
39C60J
39C6oL
39C6OP
39C6OP
39C6oCB
39C6oLB
39C60
39C6oC
39C6oC
39C60J
39C6o L
39C60 L
39C60-1
39C6o-1C
39C6o-1C
39C60-1J
39C60-1J
39C6o-1L
39C6o-1P
39C6o-1P
39C60-1CB
39C6o-1LB
39C60-1
39C6O-1C
39C6O-1C
39C60-1J
39C60-1L
39C60-1L
39C6O-1P
39C6O-1P
39C60-1CB
39C60A
39C60AC
39C60AC
39C60AJ
39C60AL
39C60AP
39C60AP
39C60A
39C60AC
39C60AC
39C60AJ
39C60AL
39C60AL
39C60AP
39C60AP
39C60ACB
39C60ALB
2901C
2901 CDC
2901CPC
2901CDMB
7C901-31
7C901-31DC
7C901-31LC
7C901-31PC
7C901-32DMB
7C901-32LMB
7C901-23
7C901-23DC
7C901-23LC
7C901-23PC
7C901-27DMB
7C901-27LMB
7C910
7C910-90
7C91 0-99
2910A
2910ADC
2910AJC
2910ALC
2910APC
2910ADMB
2910ALMB
7C91 0-50
7C910-S0DC
7C910-S0JC
7C910-S0LC
7C910-S0PC
7C910-S1DMB
7C910-S1LMB
7C910-40
7C910-40DC
7C910-4oJC
7C910-40LC
7C910-40PC
7C910-46DMB
7C910-46LMB
7C9101
39C01C
39C01CD
39C01CP
39C01CDB
39C01C
39C01CD
39C01CL
39C01CP
39C01CDB
39C01CLB
39C01D
39C01DD
39C01DL
39C01DP
39C01DDB
39C01DLB
39C10B
39Cl0B
39C10B
39C10B
39C10BD
39C10BJ
39C10BL
39C10BP
39C10BDB
39C10BLB
39C10B
39C10BD
39C1oBJ
39C10BL
39C10BP
39C10BDB
39C10BLB
39C10C
39C10CD
39C10CJ
39C10CL
39C1oCP
39C10CDB
39C10CLB
49C402
NOTES:
1. Bold text indicates a functional equivalent.
2. Plain text indicates a plug-in replacement.
Sl-39
t;)
Integrated DevIce~Inc.
DATA CONVERSION
CROSS REFERENCE GUIDE
TRW
lOT
PARAMETERS
TDC1018B7C
TDC1018B7G
TDC1018C3C
TDC1018C3G
TDC1018J7C
TDC1018J7G
TDC1048J6C
TDC1048J6G
TDC1048J6F
TDC1048J6A
TDC1048J6V
TDC1048C3C
TDC1048C3G
TDC1048C3F
TDC1048C3A
TDC1048C3V
TDC1048B6C
TDC1048B6G
TDC1048N6C
TDC1318B5C
TDC1318B5G
TDC1318J5C
TDC1318J5G
IDT75C18S125D
IDT75C18S125D
IDT75C18S125L
IDT75C18S125L
IDT75C18S125D
IDT75C18S125D
IDT75C48S20D
IDT75C48S20D
IDT75C48S20M
IDT75C48S20M
IDT75C48S20DB
IDT75C48S20L
IDT75C48S20L
IDT75C48S20LM
IDT75C48S20LM
IDT75C48S20LB
IDT75C48S20D
IDT75C48S20D
IDT75C48S20P
IDT75MB38P
IDT75MB38P
IDT75MB38P
IDT75MB38P
VDAC, Single 8-bit, CERDIP, Comm'l Temp Range
VDAC, Single 8-bit, CERDIP, Comm'l wI Bum-in
VDAC, Single 8-bit, LCC, Comm'l Temp Range
VDAC, Single 8-bit, LCC, Comm'l wI Bum-in
VDAC, Single 8-bit, Sidebraze, Comm'l Temp Range
VDAC, Single 8-bit, Sidebraze, Comm'l wI Bum-In
Flash ADC, 1/2 LSB, Sidebraze, Comm'l Temp Range
Flash ADC, 1/2 LSB, Sidebraze, Comm'l wI Bum-In
Flash ADC, 1/2 LSB, Sidebraze, Extended Temp Range
Flash ADC, 1/2 LSB, Sidebraze, Extended, High-Rei
Flash ADC, 1/2 LSB, Sidebraze, MIL-883
Flash ADC, 1/2 LSB, LCC, Comm'l Temp Range
Flash ADC, 1/2 LSB, LCe, Comm'l wI Bum-In
Flash ADC, 1/2 LSB, LCC, Extended Temp Range
Flash ADC, 1/2 LSB, LCC, Extended, High-Rei
Flash ADC, 1/2 LSB, LCC, MIL-883
Flash ADC, 1/2 LSB, CERDIP, Comm'l Temp Range
Flash ADC, 1/2 LSB, CERDIP, Comm'l wI Bum-in
Flash ADC, 1/2 LSB, Plastic, Comm'l Temp Range
VDAC, Triple 8-bit, CERDIP, Comm'l Temp Range
VDAC, Triple 8-bit, CERDIP, Comm'l wI Bum-in
VDAC, Triple 8-bit, Sidebraze, Comm'l Temp Range
VDAC, Triple 8-bit. Sidebraze, Comm'l wI Bum-in
ANALOG DEVICES
lOT
PARAMETERS
AD9048JN
AD9048KN
AD9048SE
AD9048SQ
AD9048TE
AD9048TQ
IDT75C48SB20P
IDT75C48S20P
IDT75C48SB20LM
IDT75C48SB20DM
IDT75C48S20LM
IDT75C48S20DM
Flash
Flash
Flash
Flash
Flash
Flash
DATEl
lOT
PARAMETERS
ADC304
IDT75C48S20P
Flash ADC, 1/2 LSB, Plastic, Comm'l Temp Range
ADC,
ADC,
ADC,
ADC,
ADC,
ADC,
3/4 LSB,
1/2 LSB,
3/4 LSB,
3/4 LSB,
1/2 LSB,
1/2 LSB,
Plastic, Comm'l Temp Range
Plastic, Comm'l Temp Range
LCC, Extended Temp Range
Sidebraze, Extended Temp Range
LCC, Extended Temp Range
Sidebraze, Extended Temp Range
SONY
lOT
PARAMETERS
CXA1096P
IDT75C48S20P
Flash ADC, 1/2 LSB, Plastic, Comm'l Temp Range
BROOKTREE
lOT
PARAMETERS
BT108BC
BT109KC
BT451KG125
BT451KG110
BT451KG80
BT457KG125
BT457KG110
BT457KG80
BT458KG125
BT458KG110
BT458KG80
BT458SG/883
IDT75C18S125D
IDT75MB38P
IDT75C451S125G
IDT75C451S110G
IDT75C451S80G
IDT75C457S125G
IDT75C457S110G
IDT75C457S80G
IDT75C458S125G
IDT75C458S110G
IDT75C458S80G
IDT75C458S110G
VDAC, Single 8-bit, CERDIP, Comm'l Temp Range
VDAC, Triple 8-bit, CERDIP, Comm'l Temp Range
PaletteDAC™, Triple 4-bit, PGA
PaletteDACTM, Triple 4-bit, PGA
PaletteDACTM, Triple 4-bit, PGA
PaletteDACTM, Single 8-bit. PGA
PaletteDACTM, Single 8-bit, PGA
PaletteDACTM, Single 8-bit, PGA
PaletteDAC™, Triple 8-bit. PGA
PaietteDAC TM, Triple 8-bit, PGA
PaletteDAC™, Triple 8-bit, PGA
PaletteDAC™, Triple 8-bit, PGA, 883 Compliant
AMD
lOT
PARAMETERS
AM81C458
IDT75C458S110G
PaletteDAC™, Triple 8-bit. PGA
HONEYWEll
lOT
PARAMETERS
HDAC10180
IDT75C18S125D
VDAC, Single 8-bit, CERDIP, Comm'l Temp Range
S1-40
---_._._--------------------------
t;)
Intesrated Device1echnology.1nc.
ECl PRODUCTS GROUP
CROSS REFERENCE GUIDE
FUJITSU
lOT
MBM10490-15C
MBM10490-25C
MBM10494-12C
MBM100490-15C
MBM100490-25C
MBM100494-12C
IOT10490S150
IOT10490S200
IOT10494S100
IOT100490S150
IOT100490S200
IOT100494S100
HITACHI
lOT
HM10490-12
HM10490-15
HM10490-20
HM10494-10
HM100490-15
HM 100490-20
HM100494-10
IOT10490S120
IOT10490S150
IOT10490S200
IOT10494S100
IOT100490S150
IOT100490S200
1OT1 00494S 100
SARATOGA
lOT
SSM10494-15
SSM10494-20
SSM100494-15
SSM100494-20
IOT10494S150
IOT10494S150
IOT100494S150
IOT100494S150
S1-41
~
Intesrated Devlce1echnology. Inc.
CYPRESS/MULTICHIP
CYM 1420HD-45C
CYM 1420HD-45C
CYM1420HD-55C
CYM 1420HD-55C
CYM 1420HD-70C
CYM1420HD-70C
CYM1421HD-70C
CYM1421 HD-70C
CYM1421HD-85C
CYM1421 HD-85C
CYM1421HD-100C
CYM1421 HD-100C
CYM1460PS-45C
CYM 1460PS-55C
CYM1461 PS-70C
CYM 1461 PS-85C
CYM1461PS-100C
CYM 161 OHD-XXX
CYM1610HD-XXX
CYM1610HD-XXX
CYM 1611 HV-25C
CYM1611 HV-35C
CYM1611 HV-45C
CYM1611 HV-55C
CYM1620HD-45C
CYM1620HD-55C
CYM1620HD-70C
CYM1620HD-70C
CYM1621 HD-25C
CYM1621 HD-30C
CYM1621HD-35C
CYM1621HD-45C
CYM1621 HD-55C
CYM1621HD-65C
CYM1641HD-35C
CYM1641HD-45C
CYM1641 HD-55C
CYM1821 PZ-25C
CYM1821PZ-30C
CYM1821PZ-35C
CYM1821PZ-45C
CYM1822HV-25C
CYM1822HV-30C
CYM1822HV-35C
CYM1822HV-45C
CYM1830HD-45C
CYM1830HD-55C
CYM1830HD-70C
SUBSYSTEMS
CROSS REFERENCE GUIDE
lOT PIN
SIMILAR
PART
lOT PIN
DIRECT
EQUIVALENT
8M824S45C
8M824S45N
8M824S55C
8M824S45N
8M824S60C
8M824S60N
8M824S70C
8M824S70N
8M824S85C
8M824S85N
8M824L100C
8M824L100N
7MP4008S45S
7MP4008S55S
7MP4008S70S
7MP4008L85S
7MP4008L100S
8M656S40C
8M656S50C
8M656S70C
7MC4005S25CV
7MC4005S35CV
7MC4005S45CV
7MC4005S55CV
8M624S45C
8M624S50C
8M624S60C
8M624S70C
ORG/PACKAGE
1024K(128KX8)
32 PIN DIP
512KX 8
36 PIN SIP
16KX 16
40 PIN DIP
16K X 16
36 PIN DSIP
64KX 16
28 PIN DIP
8M624.8MP624
7M624S30C
7M624S35C
7M624S45C
7M624S55C
7M624S65C
7M4016S35C
7M4016L45C
7M4016L55C
1024K (64K X 16)
(128KX 8)
(256KX4)
40 PIN DIP
256K X 16
48 PIN DIP
7MC4032S25CV
7MC4032S30CV
7MC4032S30CV
7MC4032S40CV
7MC4032S25CV
7MC4032S30CV
7MC4032S35CV
7MC4032S45CV
7M4017S45C
7M4017S55C
7M4017S70C
16KX 32
88 PIN DSIP
16K X 32
88 PIN DSIP
64KX 32
60 PIN DIP
81-42
SUBSYSTEMS CROSS REFERENCE GUIDE
DENSE PAC
lOT PIN
SIMILAR
PART
lOT PIN
DIRECT
EQUIVALENT
DPS1024-XXX
7M624
DPS1026-XXX
7M624
DPS1027-35C
7M624S35C
DPS16X5-XXX
7MP564
DPS16X17-25
-35
-45
-55
DPS257-XXX
7MC4005S25CV
7MC4005S35CV
7MC4005S45CV
7MC4005S55CV
7M656
DPS32H8-XXX
DPS40256-XXX
DPS41257-XXX
DPS41288-70
-85
-100
DPS6432-55
DPS6432-70
DPS8645-XXX
7M856
8M856
8M824S70C
8M824L85C, N
8M824L100C, N
7M4017S55C
7M4017S70C
7MP456
DPS8808-XXX
7M864
8M856
EDH816H64C-35CC
EDH816H64C-45CC
EDH816H64C-55CC
EDH816H64C-70CC
EDH816H64C-35CMHR
EDH816H64C-45CMHR
EDH816H64C-55CMHR
EDH816H64C-70CMHR
EDI8M1664C60CC
EDI8M 1664C70CC
EDI8M1664C85CC
EDI8M1664C100CC
EDI8M1664C70CB
EDI8M1664C85CB
EDI8M 1664C1 OOCS
EDI8M8128C60CC
EDI8M8128C70CC
EDI8M8128C80CC
EDI8M8128C90CC
EDI8M8128C100CC
EDI8M8128C120CC
---------
256K(16KX16)
(32KX8)
(64KX4)
40 PIN DIP
256K(32KX8)
28 PIN DIP
2048K(64K X 32)
60 PIN DIP
256K(64KX4)
28 PIN SIP
64K(8KX8)
28 PIN DIP
lOT PIN
SIMILAR
PART
7M624S35C
7M624S45C
7M624S55C
7M624S65C
7M624S35CB
7M624S45CB
7M624S55CB
7M624S65CB
8M624S60C
8M624S70C
8M624S70C
8M624S70C
8M624S70CB
8M624S85CS
8M624S100CS
8M824S50C
8M824S50C
8M824S50C
8M824S50C
8M824S50C
8M824S50C
7MB624, 8MP624
ORG/PACKAGE
64K X 16
40 PIN DIP
64KX 16
40 PIN DIP
JEDEC PIN-OUT
8M824SXXN,8MP824S
51-43
----
1024K(256KX4)
(128KX8)
(64KX16)
42 PIN DIP
1024K(256KX4)
(128KX8)
(64KX16)
40 PIN DIP
1024K(256KX4)
(128KX8)
(64KX16)
40 PIN DIP
64K(16KX5)
28 PIN SIP
16KX16
36 PIN DSIP
1024K(128KX8)
32 PIN DIP
lOT PIN
DIRECT
EQUIVALENT
EDI
ORG/PACKAGE
1024K(128KX8)
32 PIN DIP
SUBSYSTEMS CROSS REFERENCE GUIDE
EDI
EDIBMB12BC150CC
EDIBMB12BC70CB
EDIBMB12BCBOCB
EDIBMB12BC90CB
EDIBMB12BC100CB
EDIBMB12BC120CB
EDIBMB12BC150CB
EDIBMB12BP90CC
EDIBMB12BP100CC
EDIBM812BP120CC
EDI8MB128P150CC
EDI8M812BP9OCB
EDI8M812BP100CB
EDI8M812BP120CB
EDI8M812BP150CB
EDH816H64C-55
EDHB16H64C-70
EDHB16H16C-25CC-Z
EDHB16H16C-35CC-Z
EDHB16H16C-45CC-Z
EDHB16H16C-25
EDHB16H16C-35
EDHB16H16C-45
EDHB16H16C-55
EDI8MB64C60CC
EDI8MB64C70CC
EDI8MB64CBOCC
EDI8MB64C90CC
EDI8MB64C100CC
EDI8MB64C120CC
EDI8MB64C150CC
EDI8MB64C70CB
EDI8MB64CBOCB
EDI8MB64C90CB
EDI8MB64C100CB
EDI8MB64C120CB
EDI8MB64C150CB
EDHBB32HC-45CMHR
EDHB832HC-45CMHR
EDHB4H64C-35CC-D3
EDHB4H64C-45CC-D3
EDHB4H64C-55CC-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CMHR-D3
EDHB4H64C-35CMHR-D3
EDH84H64C-35CC-S
EDHB4H64C-45CC-S
EDH84H64C-55CC-S
EDH81 H256C-55
EDH81 H256C-70
EDH8BOBHC-55
EDH8BOBHC-70
EDH8BOBA-10
EDH8BOBA-12
EDH80BBA-15
EDH8BOBC-10
EDH8BOBC-12
EDH8BOBC-15
EDH8B08CL-20
lOT PIN
SIMILAR
PART
lOT PIN
DIRECT
EaUIVALENT
BMB24S50C
BMB24S70CB
BMB24S70CB
BMB24SB5CB
BMB24S100CB
BMB24S100CB
BMB24S100CB
BMB24L70C
8M824L70C
8MB24L70C
8MB24L70C
BM824LXXN.8MPB24LXXS
ORG/PACKAGE
1024K(128KX8)
32 PIN DIP
LOW POWER
BMB24.8MP824
7M624S55CB
7M624S65CB
7M656L. BM656
7MC4005S25CV
7MC4005S35CV
7MC4005S45CV
7MC4005S55C
7MB12S55C
7MB12S55C
7M812S55C
7MB12S55C
7MB12S55
7M812S55C
7M812S55C
7MB12S65CB
7MB12S65CB
7M812S85CB
7M812S100CB
7MB12S100CB
7M812S100CB
7MB56S45CB
7MB56S55CB
1024K(128KXB)
40 PIN DIP
16K X 16
36 PIN ZIP
16K X 16
36 PIN DSIP
64KX8
32 PIN DIP
8MB56L
7MP456
7MP456S35S
7MP456S45S
7MP456S55S
7MC156S55CS
7MC156S70CS
32KXB
2B PIN DIP
64KX4
24 PIN DIP
64KX4
2B PIN SIP
7MP156
BMB64L55CB
BMB64L75CB
7MB64LB5CB
7MB64L120CB
7MB64L150CB
8MB64LB5CB
BMB64L120CB
BM864L150CB
BMB64L150CB
S1-44
256K(256KX1)
2B PIN SIP
64K(BKXB)
2B PIN DIP
SUBSYSTEMS CROSS REFERENCE GUIDE
EDI.
EDH8808CL-25
EDH8808AL-20
EDH8808AL-25
EDH8832C-12
EDH8832C-15
EDH8832C-20
EDH8832C-12
EDH8832C-15
EDH8832C-20
EDH8832HC-70
EDH8832HC-85
(see part number guide)
MISC VENDORS
lOT PIN
SIMILAR
PART
lOT PIN
DIRECT
EQUIVALENT
8M864L150CB
7M864L150CB
7M864L150CB
8M856L85C
8M856L85C
8M856L85C
8M856L100CB
8M856L100CB
8M856L100CB
7M856S65CB
7M856S75CB
256K(32KX8)
28 PIN DIP
lOT PIN
SIMILAR
PART
lOT PIN
DIRECT
EQUIVALENT
AEP
AEPSS512K8-85
AEPSS512K8-10
AEPSS512K8-12
AEPSS512K8-10SL
AEPSS512K8-12SL
HARRIS
HM-8808. A
7MP4008S70S
7M134.7M144
7M135.7M145
HM-92560
7M856. 8M656
MICROELECTRONICS
MS12808 (100ns)
MS12808 (120ns)
MS12808 (150ns)
ORG/PACKAGE
512Kx 8
36 PIN SIP
7MP4008S70S
7MP4008S70S
7MP4008L100S
7M P4008L1OOS
HM-8816HB. H
HITACHI
HM66204-120ns
HM66204-150ns
HM62256P-8
HM62256P-10
HM62256P-12
HM62256LP-8
HM62256LP-10
H M62256LP-12
INOVA
S128K8-70C
S128K8-85C
S128K8-85M
S128K8-100M
S128K8-120M
S32K8-55C
S32K8-70C
S32K8-85C
S32K8-70M
S32K8-85M
S32K8-100M
MARCONI
SF63000
ORG/PACKAGE
8M824S50C
8M824S50C
7M856S85C
7M856S85C
7M856S85C
8M856L85C
8M856L85C
8M856L85C
8M824SXXN.8MP824
8M824S50C
8M824S50C
8M824S85CB
8M824S100CB
8M824S100CB
7M856S50C
7M856S70C
7M856S85C
7M856S65CB
7M856S75CB
7M856S90CB
8M824SXXN.8MP824
8M856L
7M4016
7MP4008
8M824S50C
8M824S50C
8M824SSOC
8M824SXXN.8MP824
8KX8
28 PIN DIP
JEDEC
16KX8
28 PIN DIP
JEDEC
256K (32K X 8)
(16K X 16)
SYNCHRONOUS
48 PIN DIP
128KX 8
32 PIN DIP
JEDEC
32KX8
28 PIN DIP
32KX8
28 PIN DIP
LOW POWER
128K X 8
32 PIN DIP
JEDEC
32KX8
28 PIN DIP
JEDEC
8M856LXXCB
S1-45
1 MEG (256K X 16)
(512KX 8)
48 PIN DIP
128 KX 8
32 PIN DIP
JEDEC
SUBSYSTEMS CROSS REFERENCE GUIDE
MISC VENDORS
. MITSUBISHI
MH12808TNA (100ns)
MH12808TNA (120ns)
MH51208S1N (70ns)
MH51208S1N (85ns)
MH51208S1N (100ns)
MH51208S1N (120ns)
MOSAIC
MS1256CS (25ns)
MS1256CS (35ns)
MS8128SC
MOSEL
MS88128 (100ns)
MS88128 (120ns)
MS88128 (150ns)
NEC
MC-120
SARATOGA
SSMM91256 (20ns)
SSMM91256 (25ns)
SSMM91256 (30ns)
SSMM91256 (35ns)
SSMM91257, 258, 259
lOT PIN
SIMILAR
PART
IDT PIN
DIRECT
EQUIVALENT
8M824SXXN,8MP824
8M824S50C
8M824S50C
7MP4008S70C
7MP4008S70C
7MP4008S70C
7MP4008S70C
128KX8
32 PIN DIP
512KX 8
64 PIN SIP
7MP156,7MC156
256KX 1
25 PIN SIP
8M824S50C
8M 824S50C
8M824S50C
8M824SXXN, 8MP824
128KX 8
32 PIN DIP
128KX 8
32 PIN DIP
8M824S50C
8M824SXXN 8MP824
8M824
7M856
7M656, 8M656, 8MP656
7MC4005
7MC4032
SSMM91512, 513, 514
VALTRONIC
XXX (120ns)
VITAREL
VMS10A24 (100ns)
VMS10A24 (150ns)
VMS10A24 (200ns)
VMS32K8 (45ns)
VMS32K8 (55ns)
VMS32K8 (70ns)
VMS128K8M (55ns)
VMS128K8M (60ns)
ZYREL
Z108-10
Z108-15
Z108L-10
Z108L-15
ORG/PACKAGE
7M85685C
128K X 8
32 PIN DIP
256K (32K X 8)
38 PIN ZIP
256K (16K X 16)
38 PIN ZIP
512K (16K X 32)
60 PIN ZIP
32KX8
28 PIN DIP
(64K X 16)
(128KX 8)
(64KX8)
40 PIN DIP
32KX8
28 PIN DIP
8M824S50C
8M824S50C
8M824S50C
7M856S45C
7M856S50C
7M856S70C
8M824S50C
8M824S50C
8M824SXXN,8MP824
7M624, 7MB624,
8M624, 8MP624
8M856L
8M824S50C
8M824S50C
8M824L6OC
8M824L60C
8M824SXXN,8MP824
128K X 8
32 PIN DIP
1 MEG (128K X 8)
32 PIN DIP
8M824LXXN, 8MP824L
(LOW POWER)
8M824SXXN,8MP824
S1-46
Product Selector and Cross Reference Guides
Technology/Capabilities
Quality and Reliability
Static RAMs
MultimPort RAMs
FI
Men10ries
Digital Signal Processing (DSP)
Bit-Slice Microprocessor Devices (MICROSLICE™) and EDC
Reduced Instruction Set Computer (RiSe) Processors
Logic Devices
Data Conversion
Eel Products
Subsystems IViodules
Application and Technical Notes
Pacl 2.5kg)
2019
IDTSPEC
I
(> 3.0 grams)
2011·
I
2010
INCOMING·
LIDS (SAMPLE)
CONDo B
I
PRE-CAP VISUAL
SAMPLE
2010
COND: B
I
IDTSPEC
I
,
IDT SPEC PROVIDES LOT TRACEABILITY
1008
STABILIZATION BAKE
CONDo C, 24HR/150oC
I
1010
CONDo C,10CYCLES
-65°.CTO +150°C
2001
CONDo Eo Y1 Direction
> 30kg (PKG < 5g)
:> 20kg (PKG ~ 5g)
I
I
FINE LEAK TEST
1014
.,
GROSS LEAK TEST
1014
CONDo A or B,
<5.0 X 10-8ATM/CC/SEC.
. CONDo C
I
IDTSPEC
HERMETICITY SAMPLE:
(SEE NOTE 3)
PRE BURN-IN
ELECTRICAL TEST
FINE LEAK'
1014
CONDo A or B
,
<5.0X 10-8
IDT,SPEC ATM/CC/SEC.
5004
+
DC, AC, FUNCTIONAL@ +25°C
(SEE NOTE 2)
SEE FINAL PROCESSING FLOW ON PAGE 3-3 FOR REMAINDER OF OPERATIONS AND NOTES
S3-2
GROSS LEAK'
COND.C
Monolithic Hermetic Package Final Processing Flow
Operation
MIL-STD-883
Test Method
Military
Compliant
Commercial
Military
Temp. Range
Commercial
Temp. Range
Burn·ln
1015/0 at +125"C
Min. or Equivalent
100%
160 Hours
100%
16 Hours
100%
16 Hours
Post Burn-in Electrical: Static (DC), Functional and
Switching (AC) (2)
lOT Spec.
100%
+25, -55 &
+125°C
100%
+125°C
100%
+70°C
Percent Defective Allowed (PDA) (4)
5004 or lOT Spec.
5%
10%
10%
Group A Electrical: Static (DC). Functional and
Switching (AC) (2)
5005 & lOT Spec ..
Sample
-55 & +125°C
Sample
+125°C
Sample
+70°C
Mark/Lead Straighten
100%
100%
lOT Spec.
100%
+ 25 ° C Electrical (2)
lOT Spec.
100%(5)
100%
100%
Final Visual/Pack
lOT Spec.
100%
100%
100%
Quality Conformance Inspection
5005 (Group B. C. D)
Yes
-
-
Quality Shipping Inspection
(Visual/Plant Clearance)
lOT Spec.
Sample
Sample
Sample
NOTES:
1. All screens are 100% unless otherwise noted.
2. All electrical test programs are per the applicable lOT test specification.
3. This hermeticity sample is performed after all lead finish operations.
4. If a lot fails the 5% PDA but is ~10%. the lot may be resubmitted to burn-in one time only to the same time and temperature conditions as
first submission. The subsequent post burn-in electrical test at +25°C will be performed to a PDA of 3%.
5. lOT performs a 100% electrical test at +25°C with a 2% PDA limit at this pOint to satisfy group A requirements. and considers this to be
equivalent to the group A requirement of an LTPD of 2. with an accept number of O. If a lot fails the 2% PDA limit. it may be rescreened
one time only to a tightened PDA limit of 1.5%.
6·0
Quality sample inspection
S3-3
Post Mold Cure: Plastic encapsulated devices are baked
to insure an optimum plastic seal so as to enhance moisture barrier characteristics.
Pre-Burn-In Electrical: Each product is 100% electrically
7.
tested at an ambient temperature of +25°C to lOT data
sheet or the customer specification.
Burn-In: Except for MSI Logic family devices where it may
8.
be obtained as an option, all Commercial Grade plastic
package products are burned-in 16 hours at + 125°C (or
equivalent), utilizing the same burn-in circuit conditions as
the Military Grade product.
Post-Burn-In Electrical: After burn-in, 100% of the plastic
9.
product is electrically tested to lOT data sheet or customer
specifications at the maximum temperature extreme. The
minimum temperature extreme is tested periodically on an
audit basis.
10. M ark: All product is marked with product type and lot code
identifiers.
11. Quality Conformance Inspection: Samples of the plastic
product which have been processed to 100% screening
requirements are subjected to the Periodic Quality Conformance Inspection Program. Where indicated the test
methods are patterned after MIL-STO-883 criteria.
6 •.
SUMMARY
MONOLITHIC PLASTIC PACKAGE PROCESSING FLOW
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods refer to MIL-STD-883 unless otherwise
stated.
.
1;
Wafer Fabrication: Humidity, temperature and particulate contamination levels are controlled and maintained
according to criteria patterned after Federal Standard 209,
Clean Room and Workstation Requirements. All critical
workstations are maintained at Class 100 levels or better.
. Topside silicon nitride passivation is applied to all wafers
for better moisture barrier characteristics.
Wafers from each wafer fabrication area are subjected to
scanning electron microscope analysis on a periodiC
basis.
2.
Ole-Sort Visual Inspection: Wafers are cut and separated
and the individual die are 100% visually inspected to strict
internal criteria.
3.
Die Push Test: To ensure die attach integrity, product
samples are routinely subjected to die push tests.
4.
Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull tests to ensure the integrity of
the lead bond process.
5.
Pre-cap Visual: Before the package is molded, 100% of
the product Is visually inspected to criteria patterned after
MIL-STO-883, Method 2010, Condition B.
S3-4
Monolithic Plastic Package Processing Flow
(SEE NOTE 1)
OPTICAL INSPECTION SAMPLE
INCOMING LEAD FRAME VIS/DIM/
SAMPLE
INCOMING DIE ATTACH EPOXY
SAMPLE
Q
DIE ATTACH PUSH TEST SAMPLE
Q
LEAD BOND PULL TEST SAMPLE
INCOMING GOLD WIRE
SAMPLE
INCOMING MOLDING COMPOUND
SAMPLE
PRE-CAP OPTICAL SAMPLE INSPECTION
CHEMICAL DEFLASH
POST MOLD CURE
MECHANICAL DEFLASH
TRIM/FORM/SINGULATION
SOLDER DIP
OPEN/SHORT TEST SAMPLE
EXTERNAL VISUAL
BURN-IN BIASED/DYNAMIC AT + 125°C.
16 HRS. MINIMUM (OR EQUIVALENT)
ON ALL PRODUCTS
EXCEPT MSI LOGIC FAMILY DEVICES
(FCT. AND 39C800).
ON WHICH IT MAY BE OBTAINED AS
AN OPTION.
PRE-BURN-IN ELECTRICAL TEST +25°C (SEE NOTE 2)
ELECTRICAL TEST QUALITY SAMPLE + 70°C (SEE NOTE 2)
GATE
NOTES:
1)
All screens are 100% unless otherwise noted.
2)
All electrical test programs are per the applicable IDT test specification.
3)
4)
IDT performs a 100% electrical test at +25°C with a 5% PDA limit at this point.
®
= Quality sample inspection
S3-5
2.
SUMMARY
MODULE ASSEMBLY HERMETIC PACKAGE
PROCESSING FLOW(1)
3.
Refer to the Module Assembly Hermetic Package Processing'
Flow diagram. All test methods refer to MIL-STD-883 unless
otherwise stated.
Components
1.
2.
3.
4.
Military Grade Class B monolithic microcircuIt products utilized in Module Assembly products are
manufactured and screened in compliance with the
applicable demanding criteria of MIL-STO-883. (See the
Monolithic Hermetic Package Processing Flow diagram.)
Commercial Grade monolithic microcircuit products
utilized in Module Assembly products differ from Military
Grade only in the bum-in time and electrical test
temperatures.
Passive components such as chip capacitors are
obtained from qualified vendors to the applicable military
and lOT specifications.
5.
6.
7.
Modules
1.
Module Assembly: The active and passive components
and substrates used in the assembly of modules must
pass incoming inspection requirements. The components
are then mounted onto the substrate using the reflow
solder vapor phase technique.
8.
Pre-Burn-In Electrical Test: Each module Is 100%
electrically tested at an ambient temperature of + 25°C to
lOT data sheet or the customer specification.
.Burn-In: 100% of Military Grade module product is
burned-In under the dynamic electrical conditions of
Method 1015, Condition 0, for 44 ± 4 hours at a TA of
+ 125°C. Commercial Grade module products do not
require bum-in.
Post-Burn-In Electrical: After bum-in, 100% of the
Class B Military Grade product is electrically tested to lOT
data sheet or customer specifications over the -55°C to
+ 125° C temperature range. Commercial Grade products
are sample tested to the applicable temperature extremes.
PDA Calculation: A POA (Percent Oefective Allowed) of
5% is imposed on all Military module products for the
25°C parameters after completion of bum-in.
Mark: All product is marked with product type and lot code
identifiers. MIL-STO-883 compliant Military Grade products are identified with the required compliancy code
letter.
Quality Conformance Tests: Samples of the Military
Grade product which have been processed to 100%
screening tests are routinely subjected to the Quality
Conformance Inspection requirements of MIL-STO-883
applicable to Module Assembly products.
External Visual: Product is 100% visually inspected prior
to shipment to the applicable criteria for modules as
required by MIL-STO-883.
NOTE:
1. For quality requirements beyond Class B levels, such as SEM analysis, X-ray inspection, Particle Impact Noise Detection (PIND) test, Class S
screening or other customer specified screening flows, please contact your Integrated Device Technology sales representative.
S3-6
Module Assembly Hermetic Package Processing Flow
MOTHER BOARD
INCOMING
INSPECTION
( SAMPLE)
PACKAGE CLEAN
COMPONENT
INCOMING
INSPECTION
(SAMPLE)
LCC SOLDER DIP
BOTTOM COMPONENT MOUNT
REFLOW SOLDER
VAPOR PHASE
PACKAGE CLEAN
TOP COMPONENT MOUNT
REFLOW SOLDER
VAPOR PHASE
PACKAGE CLEAN
BUMPER APPLICATION
FINAL VISUAL INSPECTION
EXTERNAL VISUAL
PRE BURN-IN
ELECTRICAL TEST
DC, AC, FUNCTIONAL @ 25°C
SEE FINAL PROCESSING FLOW ON PAGE 3-8 FOR REMAINDER OF OPERATIONS AND NOTES
S3-7
- - - - --------_ ....
__-_._---_.
..
Module Assembly Hermetic Package Flna.1 Processing Flow
Commercial
Operation
MIL-STD-883
Test Method
Military
Compliant
Military
Temp. Range
Commercial
Temp. Range
Burn-In
1015/D at + 125 "C
Min. or Equivalent
100%
44 ± 4 Hours
-
-
Post Burn-in Electrical: Static (DC), Functional and
Switching (AC) (2)
IDTSpec.
100%
+25, -55 &
+125°C
100%
+125°C
100%
+70°C
Percent Defective Allowed (PDA) (3)
5004
5%
-
-
Group A Electrical: Static (DC), Functional and
Switching (AC)(2)
IDTSpec.
Sample
-55 & +125°C
Sample
+125°C
Sample
+70°C
Mark/Lead Straighten
IDTSpec.
100%
100%
100%
+ 25 ° C Electrical (2)
IDTSpec.
100%(4)
100%
100%
Final Visual/Pack
IDTSpec.
100%
100%
100%
Quality Conformance Inspection
(Note 5)
Yes
-
-
Quality Shipping Inspection
(Visual/Plant Clearance)
IDTSpec.
Sample
Sample
Sample
NOTES:
1.
2.
3.
4.
5.
6.
All screens are 100% unless otherwise noted.
All electrical test programs are per the applicable IDT test specification.
If a lot fails the 5% PDA but is .::;:10%, the lot may be resubmitted to burn-in one time only to the same time and temperature conditions as
first submission. The subsequent post burn-in electrical test at +25°C will be performed to a PDA of 3%.
IDT performs a 100% electrical test at + 25° C with a 5% PDA limit at this paint to satisfy group A requirements, and considers this to be
equivalent to the group A requirement of an LTPD of 5, with an accept number of 1. If a lot fails the 5% PDA limit, it may be rescreened
one time only to a tightened PDA limit of 3%.
lOT presently utilizes QCI tests patterned after method 5005. A new method for module products is under development by the military.
0
Quality sample inspection
S3-8
RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
Neutron Irradiation will cause structural damage to the silicon
lattice which may lead to device leakage and, ultimately, functional
failure.
INTRODUCTION
The need for high-performance CMOS integrated circuits in
military and space systems is more critical today than ever before.
The lower power dissipation that is achieved using CMOS technology, along with the high complexity and density levels, makes
CMOS the nearly ideal component for all types of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may be
encountered. The implication of a device failure within a military or
space system clearly is critical. lOT has made a significant contribution toward providing reliable radiation-tolerant systems by
offering integrated circuits with enhanced radiation tolerance. Radiation environments, lOT process enhancements and device tolerance levels achieved are described below.
THE RADIATION ENVIRONMENT
There are four different types of radiation environments that are
of concern to builders of military and space systems. These environments and their effects on the device operation, summarized in
Figure 1, are as follows:
Total Dose Accumulation refers to the total amount of accumulated gamma rays experienced by the devices in the system, and is
measured in RADS(SI) for radiation units experienced at the silicon
level. The physical effect of gamma rays on semiconductor devices is to cause threshold shifts (Vt shifts) of both the active transistors as well as the parasitic field transistors. Threshold voltages
decrease as total dose is accumulated; at some point, the device
will begin to exhibit parametric failures as the inpuVoutput and
supply currents increase. At higher radiation accumulation levels,
functional failures occur. In memory circuits, however, functional
failures due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of radiation,
usually photons or electrons, experienced by devices in the system due to a pulse event, and is measured in RADS(SI) per second.
The effect of a high dose rate or burst of radiation on CMOS integrated circuits is to cause temporary upset of logic states and/or
CMOS latch-up. Latch-up can cause permanent damage to the
device.
Single Event Upset (SEU) is a transient logic state change
caused by high-energy ions, such as energetic cosmic rays, striking the integrated circuits. As the ion passes through the silicon,
charge is created either through ionization or direct nuclear collision. If collected by a circuit node, this excess charge can cause a
change in logic state of the circuit. Dynamic nodes that are not actively held at a particular logic state (dynamic RAM cells for example) are the most susceptible. These upsets are transient, but can
cause system failures known as "soft errors."
RADIATION
CATEGORY
PRIMARY
PARTICLE
SOURCE
EFFECT
Total Dose
Gamma
Space or
Nuclear
Event
Permanent
DoseRate
Photons
Nuclear
Event
Temporary
Upset of Logic
State or
Latch-Up
SEU
Cosmic
Rays
Space
Temporary
Upset of
Logic State
Neutron
Neutrons
Nuclear
Event
Device Leakage
Due to Silicon
Lattice Damage
Figure 1.
DEVICE ENHANCEMENTS
Of the four radiation environments above,lDThas taken considerable data on the first two, Total Dose Accumulation and Dose
Rate. lOT has developed a process that significantly improves the
radiation tolerance of its devices within these environments. Prevention of SEU failures is usually accomplished by system-level
considerations, such as error checking and correction (ECC) circuitry, since the occurrance of SEUs is not particularly dependent
on process technology. Through lOT's customer contracts, SEU
data has been gathered on some devices. Little is yet known about
the effects of neutron-induced damage. For more information on
SEU testing, contact lOT's Radiation Hardened Product Group.
Enhancements to lOT's standard process are used to create radiation enhanced and tolerant processes. Field and gate oxides
are "hardened" to make the device less susceptible to radiation
damage by modifying the process architecture to allow lower temperature processing. Device implants and Vts adjustments allow
more Vt margin. In addition to process changes lOT's radiation enhanced process utilizes epitaxial substrate material. The use of epi
substrate material provides a lower substrate resistance environment to create latch-up free CMOS structures.
S3-9
• Radiation Enhanced process uses Epi wafers and is able to provide memory devices that are qualified by IDT's Total Dose test
plan for levels of 10K RADs Total Dose [RADs/Si]. 'RE nonmemory devices are qualified by IDT's Total Dose test plan for
levels of 30K RADs Total Dose [RADs (Si)]. Higher Total Dose
levels are possible for more information contact IDT's Radiation
Hardened Product Group.
• Radiation Tolerant process uses standard wafer material and is
able to provide devices (memory and non-memory) that are
qualified by IDTs Total Dose test plan to 10K RADs Total Dose
[RADs (Si)).
RADIATION HARDNESS CATEGORIES
Radiation Enhanced ('RE) or Radiation Tolerant ('RT) versions
of lOT products follow lOT's military product data sheets whenever
possible (consult factory). lOT's Total Dose Test plan exposes a
sample of die on a wafer to a particular Total Dose level. This Total
Dose Test plan qualifies each 'RE or 'RT wafer to a Total Dose level.
Only wafers with sampled die that pass Total Dose level tests are
assembled and used for orders (consult factory for more details on
Total Dose sample testing).
The 'RE and 'RT process enhancements enable IDT to offer
integrated circuits with varying grades of radiation tolerance, or
radiation "hardness", as shown in Figure 2.
TYPE OF
RADIATION
Total Dose
Dose Rate
(Latchup)
UNITS
RADs (Si)
[Rate: 10K RADs (Si)/min.]
RADs(Si)/sec.
[pulse width = SOns]
MEMORY
PRODUCT TYPES
MEMORY+
LOGIC
LOGIC
lOT
PROCESS
~6K
~6K
~15K
Standard
~10K
~10K
~10K
Tolerant
~10K*
~10K*
~30K*
Enhanced
1.0ES
Standard
1.0ES
Tolerant
>2.4El0
>2.4El0
>2.4El0
--------------No Latchup--------------
Enhanced
* Note: consult IDT s Radiation Hardened Product Group for higher Total Dose level considerations.
Figure 2.
Integrated Device Technology can provide radiation tolerant!
enhanced versions of any of its products. Consult IDT's Radiation
Hardened Product Group for product availability/ordering information.
Please contact your local IDT sales representative or factory
marketing to determine availability and price of any IDT product
processed in accordance with one of these levels of radiation
hardness.
.
CONCLUSION
There has been widespread interest within the military and
space community in lOT's CMOS product line for its radi'!tion
hardness levels, as well as its high-performance and low power
dissipation. To serve this growing need for CMOS circuits that
must operate in a radiation environment, IDT has created a separate group within the company to concentrate on supplying products for these applications. Continuing research and development
of process and products, including the use of in-house radiation
testing capability, will allow Integrated Device Technology to offer
continuously increasing levels of radiation-tolerant solutions.
S3-10
Static RAMs
-_.,--,-,-_.,,_ .. - - _ . , .. ....., . -.. _ . - . _
,
........ _'
SRAM INTRODUCTION
Integrated Device Technology is the major U.S. supplier of highperformance Static Random Access Memories. Leading edge
CEMOS and BiCEMOS process technology, coupled with
advanced design techniques, enables IDT to supply our military
and commercial customers" with production volumes of the
industry's fastest SRAMs. IDT is committed to providing our
customers with early access to innovative Circuit designs, taking
full advantage of this advanced process technology. This results in
the broadest range of SRAM speeds, densities and organizations
available in today's market.
Integrated with performance leadership at IDT is a commitment
to provide our customers with a wide selection of SRAM organizations. 16K, 64K and 256K devices are offered in x1, x4 and x8
organizations. This year, these offerings will be expanded to
include x16 and x9 devices, as well as 1 Megabit densities. To
further match IDT SRAMs with system architectural needs, several
devices are available with separate inputs and outputs, additional
control features and functions.
Leadership products offered by IDT include BiCEMOS devices,
incorporating both TTL and ECLcompatible inputs and outputs, as
well as CEMOS devices offering true CMOS I/O levels. These
products confirm our charter to offer technology to system designers in its most friendly and usable form.
Cache is an area of strong emphasis for IDT. It is critical for
RISC-based systems, and most microprocessors require caches
since DRAM speeds have not kept up with microprocessor
speeds.
IDToffers the largest Cache-Tag RAM in the industry, the 7174
(8K x 8); and the fastest Cache-Tag RAM in the industry, the 6178
(4K x 4). IDT also has the most complete line of Data RAMs available anywhere. The 71586 with latched addresses is the industry's
first specialty RAM intended for cache data storage.
Our fast standard RAMs with Output Enable are also used as
Data RAMs, with specifications optimized for the fastest
IDT79R3000 applications.
Our intensive and innovative process technology development
effort has resulted in truly outstanding advances in device performance. Over the past 7 years, as an example, our 2K x 8 SRAM has
been redesigned in successively advanced CEMOS processes,
progressing from 2~ geometries to less than 1~. This resulted in
access time being improved by about a factor of 10, to the currently
available 15 nanosecond devices. This continuing dedication to
advancement will result in 1 Megabit CEMOS devices and 256K bit
BiCEMOS devices this year.
IDT's advanced SRAMs are available in a wide variety of
packages, ranging from commercial surface mount through DIPs
and LCCs to· military flatpacks. This continually expanding
package offering is in direct response to critical second-level
interconnect issues confronting today's system designer. Our
commitment to technology extends to advanced, cost-effective
packaging techniques.
Both" commercial and military versions of all IDT SRAMs are
available. Our military devices are manufactured and processed
strictly in conformance with all the administrative, processing and
performance requirements of MIL-STO-883. Having anticipated
increased military radiation resistance requirements, all devices
are also offered with special radiation resistant processing and
guarantees. As a leading supplier of military SRAMs, IDT provides
performance and quality levels second to none. Our commercial
products, in fact, share most processing steps with military
devices.
IDT's continuing commitment to cutting edge technology and
performance will assure the availability of SRAMs most compatible
with the exacting needs of teday's systems. Look to IDT SRAMs for
performance, technology, quality and imaginative solutions to
memory system problems.
TABLE OF CONTENTS
CONTENTS
OUTPUT
ORGANIZATION
PAGE
Static RAMs
lOT 6167
lOT 7187
lOT 71257
x1
><1
x1
16K (16K 1) CMOS SRAM (Power Oown).·;.. ............... ...... ......
64K (64K x 1) CMOS SRAM (Power Oown) ............................
256K (256K x 1) CMOS SRAM (Power Oown) (14-74) .......•..............
S4-1
S4-11
S4-19
lOT 6168
lOT 71681
x4
x4
S4-28
lOT 71682
x4
lOT 6177
lOT 6178
lOT 61970
. lOT 7177
lOT 7178
lOT 6198
IOT7188
IOT7198 .
lOT 7198.1
lOT 71982
lOT 61592
IOT61593 .
lOT 61594
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
lOT 61595
x4
lOT 71598
lOT 61298
lOT 71258
lOT 71281
lOT 71282
IOT7MP456
x4
x4
x4
x4
x4
x4
16K (4K x 4) CMOS SRAM (Power Oown) (14-74) ... . . . . . . . . . . . . . . .. . .. ...
16K (4K x 4) CMOS SRAM (Separate I/O-Output Follows
Input at Write) (14-36, 14-74) ............. '.... ~ ... :. . . . . . . . . . . . . ..
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write)
(14-36, 14-74) • . . . . . . . . . . ... . . . . . • . • • ... . . ... . . . . . . . . . . . . . . ... . • . . .•
CMOS High-Speed Static RAM Cache-Tag (4K x 4) .............••.•.....•
16K (4K x 4) CMOS Cache-Tag SRAM (14-47) ............... ;...........
CMOS Static RAM With Output Enable 16K (4K x 4) ... ;...................
CMOS High-Speed Static RAM Cache-Tag 16K (4K x 4-Bit) ... .............•
High-Speed Static RAM Cache 16K(4K x 4-Bit) .. ~ . . . • .. . . . . . . . . • ... . . . . ..
64K (16K x 4) CMOS SRAM (with Output Enable) (14-74) ............•.....
64K (16K x 4) CMOS SRAM (Power Oown) ....................... : . .. . . ..
64K (16K x 4) CMOS SRAM (2 CS and 0E)(14-74) .......... : .............
64K (16K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) ..•..
64K (16K x4) CMOS SRAM (Separate I/O-Output High Z at Write) •.•......•
. CMOS Synchronous Static RAM with Transparent Outputs 64K (16K x 4-Bit) ..•
CMOS Synchronous Static RAM with Output Registers 64K (16K x 4-Bit) ......
CMOS Synchronous Static RAM with Output Registers and OE
64K (16K x 4-Bit) ..•..........•.......•.................... ~ . . . ..
CMOS Synchronous Static RAM with Transparent Outputs and
OE 64K (16K x 4-Bit) .............................................
CMOS Static RAM with Latched Addresses 64K (16K x 4-Bit) .......•.... ~...
256K (64K x 4) CMOS SRAM (with Output Enable) (14-36) .•...•....••.....
256K (64K x4) CMOS SRAM (14-74) ...................................
256K (64K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) .....
256K (64K x 4) CMOS SRAM (Separate I/O·Output High Z at Write) ..........
256K (64K x 4) CMOS SRAM (Plastic SIP) Module ..•...............•.....
IOT7MP564
x5
aOK (16K x 5) CMOS SRAM (Plastic SIP) Module .......................
13-29
IOT7MC4018
x6
64K x 6 CMOS Static RAM Ceramic SIP Module •................•........
S13-158
lOT aM824
lOT aMP824
lOT 6116
lOT 7164
lOT 7165
lOT 71C65
lOT 7174
lOT 71564
lOT 71578
lOT 71256
IOT7M812
IOT7MP6025
lOT aM856
lOT 7MP4008L
lOT 71583
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
x8
xa
x8
x8
1 Megabit (128K x 8) CMOS SRAM Module.............................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) Module.................
16K (2K x 8) CMOS SRAM (14-74) .....................................
64K (8K x 8) CMOS SRAM (Power Oown) (14-74) ........ .................
64K (8K x 8) Resettable CMOS SRAM ....... .............. .......... ....
64K (8K x 8) SRAM (Resettable CMOS I/O) ..............................
64K (8K x 8) CMOS Cache-Tag SRAM (14-47) ...........................
CMOS Static RAM with Latched Addresses 64K (8K x 8-Bit) ..... ............
CMOS Static RAM with Exclusive-Or Latched Addresses 64K (8K x 8-Bit) ......
(32K x 8) CMOS SRAM (Power Oown) (14-74) ............................
512K (64K x 8) CMOS SRAM Module.......................... .........
512K (64K x 8) Synchronous SRAM (Plastic SIP) Module....... ...•.. .•....
256K (32K x 8) Low-Power CMOS SRAM Module ....••.................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) Module .......•.........••
High-Speed Static RAM Organized as 32K x a . . . . . . . . . . . . . . • . . . . . . • . . . . ..
13-107
13-86
S4-143
S4-154
S4-163
S4-172
S4-181
S4-191
S4-192
S4-193
S13-17
S13-189
13-113
S13-183
S4-202
IOT7169
lOT 71259
lOT 71509
IOT7M912
x9
x9
x9
x9
CMOS High-Speed Static RAM 8K x 9 .........•.•........•...........••
High-Speed Static RAM Organized as 32K x 9 . . . . . . . • . . . . . . . • . . . . . . . • . . ..
High-Speed Static RAM Organized as 32K x 9 . . . . . . . . • • . . . . . . . . . . . • . . . . ..
512K (64K x 9) CMOS SRAM Module ...................................
S4-204
S4-205
S4-207
S13-17
IOT7186
IOT8MP628
lOT 71502
x16
x16
x16
64K (4K x 16) CMOS SRAM (Power Oown) ...............................
128K (8K x 16) CMOS SRAM (Plastic SIP) Module ..•.•.......•...........
CMOS Static RAMS 64K (4K x 16-Bit) Registered RAM with SPC ™ ••••••••••
S4-209
S13-195
S4-218
x
S4-39
S4-39
S4-50
S4-52
S4-59
S4-65
S4-67
S4-69
S4-78
S4~86
S4-96
S4-96
S4-106
S4-108
S4-110
S4-112
S4-114
S4-115
S4-125
S4-134
S4-134
S13-177
TABLE OF CONTENTS (CON'T.)
CONTENTS
IDT 71586
lOT SM62S
IDT7M656
IDT7MC4005
IDT SMP656
lOT SM656
IDT7MB4009
lOT SM612
lOT SMP612
IDT7M624
lOT SM624
lOT SMP624
IDT7M4016
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
CMOS Static RAMS 64K (4K x 16-Bit) .... . . . . . . . . . . . . . . . . . . • . . . . . . . . . . ..
12SK (SK x 16) CMOS SRAM Module............................ ......
256K (16K x 16) CMOS SRAM Module..................................
256K (16K x 16) CMOS Static RAM Ceramic Dual SIP Module ............ '"
256K (16K x 16) CMOS SRAM (Plastic SIP) Module .......................
256K (16Kx 16) CMOS SRAM Module.................................
512K 2(16K x 16) CMOS Static RAM FR-4 DIP Module. . . . . . . . . . . . . . . . . . . ..
512K (32K x 16) CMOS SRAM Module ....................•......... '"
512K (32K x 16) CMOS SRAM (Plastic SIP) Module .....................
1 Megabit (64K x 16) CMOS SRAM Module ..............................
1 Megabit (64K x 16) CMOS SRAM Module............. .... ... ........
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) Module.................
4 Megabit (256K x 16) CMOS SRAM Module . . .. . .. .. .. .. . . .. .. .. .. .. . ...
PAGE
$4-242
13-99
S13-S
S13-152
S13-195
13-99
S13-92
13-92
13-74
S13-1
13-92
13-74
S13-23
IDT7M6001
x20
Dual, Multiplexed 16K x 20 SRAM Module................. ..............
S13-35
IDT7MC4032
IDT7M4017
x32
x32
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) Module ....•............
2 Megabit (64K x 32) CMOS SRAM Module ..............................
S13-164
S13-29
IDT7MB6039
IDT7MB6049
x60
x60
Dual (16K x 60) Data/Instruction cache Module for IDT79R3000 CPU. . . .. . . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) (S14-6) .. . . .. .. . . . . . . . . . . .. .. .. . .. . . .. . . . . .. . . ...
S13-105
IDT7MB6044
IDT7MB6043
IDT7MB6051
x64
x64
x64
S13-133
S13-131
IDT7MB6040
x64
Dual (4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU ....... '"
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU. . . . .. . . ..
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
Dual (16K x 64) Data/Instruction Cache Module For General CPUs ... ........
IDT7MB6042
x112
8K x 112 High-Speed Writable Control Store W/SPC™ .....................
S13-117
S13-135
S13-138
S13-111
t;J
Intesrated Device1echnoIogy.1nc.
lOT 6167SA
lOT 6167LA
CMOS STATIC RAM
16K (16K x 1-BIT)
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
- Military: 15/20/25/35/45/55/70/85/100ns (max.)
- Commercial: 12/15/20/25/35ns (max.)
• Low power consumption
- IDT6167SA
Active: 200mW (typ.)
Standby:100j.lW (typ.)
- IDT6167LA
Active: 150mW (typ.)
Standby:10j.lW (typ.)
• Battery backup operation - 2V data retention voltage
(IDT6167LA only)
• Available in 20-pin CERDIP and plastic DIP, 20-pin Flatpack or
CERPACK, 20-pin SOIC and 20-pin lead less chip carrier
• Produced with advanced CEMOS ™ high-performance
technology
• CEMOS process virtually eliminates alpha particle soft-error
rates
• Separate data input and output
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-84132 is pending listing on
this function. Refer to Section 2/page 2-4.
The IDT6167 is a 16,384-bit high-speed static RAM organized as
16K x 1. The part is fabricated using IDT's high-performance, highreliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories.
Access times as fast as 12ns are available with maximum power
consumption of only 660mW....IJ1e circuit also offers a reduced
power standby mode. When CS goes high, the circuit wil!.J!.utomatically go to, and remain in, a standby mode as long as CS remains high. In the standby mode, the device consumes less than
10j.lW, typically. This capability provides significant system-level
power and cooling savings. The low-power (LA) version also offers
a battery backup data retention capability where the circuit typically consumes only 1j.1W operating off a 2V battery.
All inputs and the output of the IDT6167 are TTL-compatible and
operate from a single 5V supply, thus simplifying system designs.
Fully static asynchronous circuitry is used, which requires no
clocks or refreshing for operation, and provides equal access and
cycle times for ease of use.
The IDT6167 is packaged in a space-saving 20-pin, 300 mil
Plastic DIP or CERDIP, plastic 20-pin SOIC, 20-pin flatpack or
CERPACK and 20-pin leadless chip carrier, providing high boardlevel packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
ROW
SELECT
16,384-BIT
MEMORY ARRAY
GND
COLUMN 1/0
--------~r_------~--+_----------------------~~--Do~
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated DevIce Technology. Inc.
JANUARY 1989
DSC-l007/1
54-1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SA/IDT6167LA CMOS STATIC RAM (16K x 1-BIT)
PIN CONFIGURATIONS
DOUT
DIP/SOIC/FLATPACK/CERPACK
TOP VIEW
A7
~ ~ I~
c:l
J
LCC
TOP VIEW
LOGIC SYMBOL
PIN NAMES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE .MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
S4-2
Ao-A 13
Address Inputs
DIN
DATA IN
CS
Chip Select
DOUT
DATA OUT
WE
Write Enable
GND
Ground
Vee
Power
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SA/IDT6167LA CMOS STATIC RAM 16K(16Kx l-BIT)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLVVOLTAGE
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
GRADE
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
Input High Voltage
2.2
-
Military
V1H
V1L
6.0
V
Commercial
Input Low Voltage
-0.5(1)
-
0.8
V
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V
O°Cto +70°C
OV
5.0V
Vcc
± 10%
± 10%
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
v.cc --
50V +10%
-
TEST CONDITION
PARAMETER
MIN.
Ilu l
Input Leakage Current
Vcc = Max., V1N = GND to Vee
MIL.
COM'L.
-
IILol
Output Leakage Current
Vcc = Max.
CS = "'IH ' VOUT = GND to 'tc
MIL.
COM'L.
-
Output Low Voltage
10L = 8mA Vee, = Min.
VOL
6167SA12(4)
SYMBOL
PARAMETER
POWER
-
IDT6167LA
MIN. TYP.(l) MAX.
-
10
5
-
10
5
-
-
0.4
-
-
2.4
-
2.4
VOH
10H = -4mA, Vcc = Min.
Output HIGH Voltage
NOTE:
1. Typical limits are at Vcc = 5.0V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS (1) Vcc
IDT6167SA
TYP.(l) MAX.
-
UNIT
-
5
2
J..lA
5
2
J..lA
-
0.4
V
-
V
-
= 50V +10% VLC = 02V VHC = 'tc - 02V
6167SA15
6167LA15
6167SA20/25
6167LA20/25
6167SA35
6167LA35
6167SA45(5) 6167SA55(5) 6167SA70(5)
6167LA45(5) 6167LA55(5) 6167LA70(5)
UNIT
COM'L MIL COM'LMIL COM'L MIL COM'LMIL COM'L MIL COM'LMIL COM'LMIL
Icc1
ICC2
Operating Power
Supply Current
CS =V11o
Outputs Open.
Vee = Max.•
f = 0(3)
Dynamic
Operating Current
CS = V1L
Outputs Open.
Vcc = Max.•
f = fMAX(3)
SA
-
90
90
90
90
90
90
90
-
90
-
90
-
90
55
60
55
60
55
60
-
60
-
60
-
60
120
130
100 110/100
100
100
-
100
-
100
-
100
100
110
65
70
-
65
-
60
-
60
50
50
35
35
-
35
-
35
-
35
mA
LA
- :::::::}:);:;::
,':
SA
::
;:::::.
:
;,'
140:::: ~:ttf:~:
.:.:::::::::::;:;;::{;.
mA
.......;.;:;;;;;;;;;;:;
LA
-
80nO 85n5
.:.:.:.:.:.:.:.:.:.:.:.:.
ISB
ISBI
Standby Power
Supply Current
(TTL Level)
CS ~VIH.
Vcc = Max.•
Outputs Open
f = fMAX (3)
Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHC •
Vee = Max.,
"'IN ~VHC or
V1N :5 VLC f = 0(3)
SA
50
35
35
mA
.:.:::::::::::::::::::::.
LA
-
35
35
5
10
30/25 30/25
20
20
-
20
-
20
5
10
-
10
-
10
-
15
::::::;){;;)::::
SA
10 ::::::::::1.::::;;::
5
10
-
10
mA
LA
-
-
0.9
2
0.05
2/0.9
0.05
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 85n'8 and 100ns Military devices
3. f = fMAX (All Inputs cycling at f = 1/tRcl. f = 0 means no address control lines change.
4. O°C to + 70°C temperature range only.
5. -55°C to + 125°C temperature range only.
S4-3
0.9
-
0.9
-
0.9
-
0.9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SAJIDT6167LA CMOS STATIC RAM (16Kx 1-Bm
DATA RETENTION CHARACTERISTICS
(L Version Only) VLC = 0.2V, VHC = VCC - O.2V
SYMBOL
VDR
ICCDR
TEST CONDITION
PARAMETER
MIN.
-
Vcc for Data Retention
I
Data Retention Current
MIL.
COM'L.
tCDR
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
Il u l(3)
Input Leakage Current
CS !::'VHC
\'IN ~ VHC or::; VLC
TYP.(1)
V cc @
2.0V
3.0V
MAX.
Vcc @
2.0V
2.0
-
-
-
-
-
0.5
1.0
200
300
-
0.5
1.0
20
30
-
ns
-
-
2
~A
DATA RETENTION MODE
VCC
\'IH
.AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
~
2550
5V
480n
DATA OUT
30pF*
~
2550
Figure 1. Output Load
4800
5pF*
Figure 2. Output Load
(for t HZ • t LZ • twz arid tow)
* Including scope and jig.
S4-4
J.l.A
-
0
LOW Vee DATA RETENTION WAVEFORM
DATAoUT
V
t R'c(2)
NOTES:
1. TA= +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
UNIT
3.0V
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SA/IDT6167LA CMOS STATIC RAM 16K (16Kx 1-BIT)
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
6167SA12(1)
PARAMETER
SYMBO
MAX.
MIN.
(Vcc = 5.0V ±10%, AI/Temperature Ranges)
6167SA15
6167LA15
MIN.
MAX.
6167SA20/25
6167LA20/25
MAX.
MIN.
6167SA35/45 (2) 6167SA55 (2)/70(2)
6167LA35/45(2) 6167LA55(2~70(2)
MIN.
MAX. MIN.
MAX.
UNIT
READ CYCLE
t Rc
Read Cycle Time
12
tAA
t ACS
Address Access Time
-
Chip Select Access Time
-
15
-
20/25
-
35/45
-
55{70
-
::::::::,,::;:"'12
-
15
-
20/25
-.
35/45
55{70
ns
12
-
15
-
20/25
-
35/45
-
55{70
ns
:.\,:::.:;
.:::=:,:;:::::::-
ns
tOH
Output Hold from Address Change
3:2:::::;;'::=
-
5
-
5
3
-
5
5
-
5
-
ns
3':::':';::::::::
-
5
Chip Deselect to Output in Low Z(3)
-
3
tLZ
tHZ
Chip Select to Output in High Z(3)
p:::::{
8
-
10
-
10
-
15/30
-
40
ns
tpu
Chip Select to Power Up Time (3)
-
0
-
0
-
0
-
0
-
ns
tpD
Chip Deselect to Power Down Time(3) .:;;'{:"":
12
-
15
-
20/25
-
35
-
55{70
ns
::::::6.::/
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 85 and 100ns Military devices.
3. This parameter guaranteed but not tested.
TIMING WAVEFORM OF READ CYCLE NO.1
(1,2)
f=
t~I')
PR~OUS:§ t~ j
ADDRESS
DATA OUT
XX
~_____
*,.....----D-A-T-A-V-A-L-ID-----
TIMING WAVEFORM OF READ CYCLE NO.2 (1,3)
)4---------
t RC (5)
--------~
t LZ (4)
DATA OUT
HIGH IMPEDANCE
Vcc
c3~~~~i-
tPu~_
Icc
IS9
-
-
-
-
-
-
_ _ _
tPD=t
-
-
......- - - - - - -
NOTES:
1.
2.
3.
4.
5.
wr=. is High for READ Cycle.
CS is low for READ cycle.
Address valid prior to or coincident with CS transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
S4-5
IDT6167SA/lDT6167LA CMOS STATIC RAM (16Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
6167SA12(1)
PARAMETER
SYMBOL
MIN.
MAX.
(Vcc = 5.0V ±10%. All Temperature Ranges)
6167SA15
6167LA15
MIN.
MAX.
6167SA20/25
6167LA20/25
MIN.
MAX.
6167SA35/45 (2) 6167SA55 (2)/70(2)
6167LA35/45(2) 6167LA55(2)/70(2)
MIN.
MAX. MIN.
MAX.
UNIT
WRITE CYCLE
-
0
-
6
-
7
-
8
-
15/30
-
40
ns
-
0
-
0
-
0
-
0
-
ns
twc
Write Cycle Time
12
:::}::::;::;::
15
tcw
Chip Select to End of Write
12
/({::::""
15
tAW
Address Valid to End of Write
12
.::::::::);::::-
15
t AS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
.t ow
Data Valid to End of Write
12 .:::;::::::::::: 0 ::::::::\\:. 10.::::.:··::::::t:
-
tOH
Data Hold Time
twz
Write Enable to Output in High Z (3)
tow
Output Active from End of Write (3)
0
·::~:~t:}:::·
of~::,:::,):'
f::;::::::::::::'
::0':\::::.
0
13
0
10
30/45
-
55170
30/40
-
45/55
0
-
0
0
-
20/20
15/20
15/20
0
15/20
0
12/15
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 85 and 100n5 Military devices.
3. This parameter guaranteed but not tested.
S4-6
30/40
0
30
0
17/20
ns
0
-
45/55
35/40
0
25/30
ns
ns
ns
ns
ns
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SAlIDT6167LA CMOS STATIC RAM 16K (16Kx l-Bm
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1,2,3)
twc
ADDRESS
~
---./
) 1/I\..
K
tAW
~
r\..
f4-- t AS
twp
I-
tWA
~v
~'"
j4-tWZ(5)-
tow (5)
.....
./
DATA OUT
./
~
'"
I+--tow
"-,I K
tOH - -
VALID
DATA
)~
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(1,2,3,4)
twc
ADDRESS
~
---./
~K
K
tAw
~I/
'l\.
j4--tAS
tWA
tcw
f 4 - - t ow
) VI\.
DATA IN
VALID
I-
t OH DATA
~I.I
)"
NOTES:
1.
2.
3.
4.
5.
wr:. or CS must be high during all address transitions.
A write occurs during the overlap (tw~ of a low CS and a low Wf!..
tWA is measured from the earlier of CS or Wf!. going high to the end of the write cycle.
If the CS low transition occurs simultaneously with or after the ~ low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
S4-7
"
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SAJIDT6167LA CMOS STATIC RAM (16Kx l-BIT)
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
1.2
l
1.3
Q)
~ 1.1
\
~
~ 0.9
Q)
~ 1.0
~
~
"~
0.7
~ 0.9
35
45
~
o
...Y
"'-~
55
75
85
0.7
25
35
0
o
...Y
"'""
0.8
0.5
25
\
't:J
T~ = 25 J
T! = 25 C
Vee = 5.0V
1\
1.1
1\
't:J
t
T! = 25 C
Vee = 5.0V
1\
Icc vs. Supply Voltage
Icc vs. tAA '(35"s Device)
ISB vs. tAA (35"s Device)
1.5
45
'"
55
1.0
V
~
75
.5
4.0
85
5.0
tAA(ns)
tAA(ns)
ISB vs.Temperature
T
Vee = 5.0V
I
Vee = 5.0V
TA = 25°C
1.2
~--+--+-----+---t
1.5
1.0
t----+---:~+---+---I
1.0
1.1
o
...Y
140
6.0
Vee (V)
ISB vs. Supply Voltage
Icc vs. Temperature
V
V
.5
4.0
~
/
1.0
~
~
...... ~
./
0.9
5.0
-60
6.0
140
Vee (V)
ISB1 vs. Supply Voltage
1.2
TA = J25 0 C-
~---+---I---~---4
/
V
~
. ; 10.0
TA
1.0
~---+-~+--~---I
6.0
-60
140
Vee (V)
S4-8
~
10.0
1.0
5.0
5.0)
= 25°C-
'" ,
V"
lK
100
"
"'N
icc =1
lOOK
10K
0.8
0.7
4.0
100.0
ISB1 vs.
~
1.1
0.9
ISB1 vs. Temperature
o
.J
2
3
V1N (V)
4
5
6
IDT6167SA/IDT6167LA CMOS STATIC RAM 16K (16Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
ICCDR
vs. Temperature
t AA • tACS
vs. Supply Voltage
TA =
100.0 I----+---+---+---i
VCCDR = 2V
15 C
0
1.2
~ 10.0 t----+---+---~--;
""
15
0.9
1.0 t----+----,tf---f---;
0.8
-60
140
4.0
5.0
6.0
VccM
vs. Temperature
t AA • t ACS
t AA • t ACS
vs. Output Loading
I
Vcc = 5V
/
1.2
U)
U
/
1.1
~
j
/
1.0
0.9
/'
/
1.3
U)
V
Jj
/'
1.2
1.1
1.0
0.8
0.9
-60
140
0
100
200
C L (pF)
TRUTH TABLE
MODE
CS
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
Read
L
H
DATA OUT
Active
Write
L
L
HighZ
Active
CAPACITANCE (TA= +25°C, f
SYMBOL
CIN
COUT
PARAMETER(1)
Input Capacitance
Output Capacitance
= 1.0MHz)
CONDITIONS
MAX.
UNIT
VIN = OV
7
pF
VOUT= OV
7
pF
NOTE:
1. This parameter is determined by device characterization and is not
production tested.
S4-9
300
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SA/IDT6167LA CMOS STATIC RAM (16K xl-BIT)
ORDERING INFORMATION
lOT
XXX)(
Device Type
A
Power
999
A
A
Speed
Package
Process/
Temperature
Range
y:~k
P
L------------i
o
L
SO
E
F
Y
12
15
20
25
-I
L -_ _ _ _ _ _ _ _ _ _ _
________________________
~I
SA
ILA
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Flatpack
SOJ
Commercial Only
~~
55
70
85
100
~
Commercial (O°C to
Military
Military
Military
Military
Military
Only
Only
Only
Only
Only
Speed in Nanoseconds
Standard Power
Low Power
6167
16K (16K x 1-Bit) CMOS Static RAM
S4-10
t;)
IntegIated DevIce'Jechn6logy.Inc.
lOT 71875
lOT 7187L
CMOS STATIC RAM
64K (64K x 1-BIT)
FEATURES:
DESCRIPTION:
• High speed (equal access and cycle time)
- Military: 25/30/35/45/55!70/85ns (max.)
- Commercial: 15/20/25/30/35/45ns (max.)
• Low power consumption
- 10T7187S
Active: 300mW (typ.)
Standby: 1OO~w (typ.)
- 10T7187L
Active: 250mW (typ.)
Standby: 30~w (typ.)
• Battery backup operation - 2V data retention (L version only)
• JEOEC standard high-density 22-pin plastic and hermetic DIP,
24-pin plastic SOIC, 22-pin and 28-pin lead less chip carrier and
24-pin flatpack and CERPACK
• Produced with advanced CEMOS ™ high-performance
technology
• Separate data input and output
• Input and output directly TIL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STO-883, Class B
• Standard Military Orawing# 5962-86015 is pending listing on
this function. Refer to Section 2/page 2-4.
The 10T7187 is a 65,536-bit high-speed static RAM organized as
64K x 1.lt is fabricated using lOT's high-performance, high-reliability technology, CEMOS. Access times as fast as 15ns are available
with maximum power consumption of 880mW.
Both the standard (S)and low-power (L) versions ofthe 10T7187
provide two standby modes-lsB and ISB1. ISB provides low-power
operation (358mW max.); ISBl provides ultra-low-power operation
(5mW max.). The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30~W.
Ease of system design is achieved by the I 0T7187 with full asynchronous operation, along with matching access and cycle times.
The device is packaged in an industry standard 22-pin, 300 mil
plastic or hermetic DIP, 24-pin plastic SOIC, 22- and 28-pin leadless chip carriers, or 24-pin flatpack or CERPACK.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
LOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
A
Ao
DATA IN
Al
Vcc
A
GND
A
A2
A
A3
A4
A
Ae
A7
As
65,536:-BIT
MEMORY ARRAY
ROW
SELECT
A
A5
DATAoUT
Ag
A 10
All
A
A
es
A12
A 13
A14
A 15
DATA OUT
AA
A
A
A
A
A
A
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC-l025/1
S4-11
91
•
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7187S/IDT7187L CMOS STATIC RAM 64K (64Kx 1-BIT)
PIN CONFIGURATIONS
Ao
Al
A2
A3
A4
Vee
A15
A5
A6
All
A10
A14
A13
A12
A7
DATA OUT
NC
A5
As
A7
DATAoUT
As
As
DATA IN
WE"
CS
GND
WE"
.;:
:J
0
A14
A13
A12
NC
A3
A4
A12
All
AlO
A5
As
A7
DATAoUT
NC
A10
FLATPACKICERPACK
TOP VIEW
20 [:
3
LJUii LlU
32W2S27
4
1
2S [
lS [
A14
A13
Al
18 [
:J
A12
A2
] 5
All
A3
:J
S
24 [
A12
AlO
A4
] 7
23 [
All
15 [:
14 [:
As
A8
NC
A5
]
]
22 [
NC
s
21[
A10
As
A7
]
]
10
11
20
£:
DATA OUT
]
18 [
12
13 14 15 16 17
As
As
NC
~
oct
~
Address Inputs
DATA IN
Data Input
CS
Chip Select
DATAoUT
Data Output
Write Enable
GND
Ground
Vee
Power
TslAS
TSTG
PT
lOUT
<.)
Z
Z
IUl Z
10 oei"
~
o
28-PIN LCC
TOP VIEW
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to. + 7.0
V
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
Operating
Temperature
Oto +70
-55 to +125
°C
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
Temperature
0
CJ
WE
TA
IS [
nnnnn
\!lI
I!:
PIN NAMES
VTERM
l28-2
S
22-PIN LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
A14
A13
16 [
0
RATING
Terminal Voltage
with Respect to
GND
cs
INDEX
ttU~~
1
~ CJ~~
SYMBOL
As
As
DATA IN
oct ~.£
l22-1 17[
Ao-A15
All
GND
SOIC/SOJ
TOP VIEW
10
A14
A13
WE"
CS
DIP
TOP VIEW
Vce
A15
Ao
Al
A2
As
As
DATA IN
GND
0
NC
Vcc
A15
Ao
Al
A2
A3
A4
-55 to +125
-65 to +150
Power Dissipation
1.0
1.0
W
DC Output Current
50
50
mA
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vce
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
\IH
\IL
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
S4-12
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto + 70°C
OV
5.0V ± 10%
Vee
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I DT7187S/1 DT7187L CMOS STATIC RAM 64K (64K xl-BIT)
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%
SYMBOL
PARAMETER
TEST CONDITION
lIu l
Input Leakage Current
Vee = Max., VIN = GND to Vee
IlLOI
Output Leakage Current
\bo
~
VOL
Output Low Voltage
VOH
Output High Voltage
MIN.
MIL.
COM'L.
= Max.
= VIH , VOUT = GND to Voo
IOL = 10mA, Veo = Min.
IOL = 8mA, Voo = Min.
IOH = -4mA, Voo = Min.
MIL
COM'L.
IDT7187S
TYP.(l) MAX.
-
-
2.4
-
10
5
-
MIN.
-
10
5
-
0.5
-
0.4
-
-
2.4
IDT7187L
TYP.(l) MAX.
-
UNIT
5
2
~
5
2
~
-
0.5
V
0.4
V
-
-
V
NOTE:
1. TypicallimitsareatVcc = 5.0V, +25°Cambient.
DC ELECTRICAL CHARACTERISTICS(l)
Voo = 5.0V ±100/0, VLO = 0.2V, VHO = Voo - 0.2V
7187S15
SYMBOL
PARAMETER
7187S20
POWER
7187S25
7187L25
7187S30/35
7187L30/35
COM'L MIL. COM'L.MIL. COM'L.MIL COM'L
1001
1002
ISB
ISBl
Operating Power
Supply Current
CS = VIL,
Outputs Open
Veo = Max.,
f = 0(2)
Dynamio
Operating Current
CS = VIL,
Outputs Open,
Veo = Max.,
f = fMAX(2)
Standby Power
Supply Current
(TTL Level)
CS ~VIH,
Voo = Max.,
Outputs Open
f = f MAX (2)
Full Standby
Power Supply
CUrrent (CMOS
Level)
CS ~ VHO ,
Voo= Max.,
"'IN ~VHO or
"'IN'S VLO , f = 0(2)
S
13~:::~~::::::::::::1.
:::.:.-
..:.,.:.,.,.
L
120
140
7187S45/55(3)
7187L45/55(3)
MIL COM'L
7187S70
7187L70
7187S85
7187L85
UNIT
MIL. COM'LMIL COM'L.MIL
90
105
90
105
90
105
105
70
85
70
85
70
85
85
85
120
130
110
120
110
120
120
120
100
110
95/90
110/100
85
95
90
90
55
55
45
50
45
50
50
50
105
..':':
mA
:ill:~;~::j::::::::~~~i
:;::::::?:::::{~~::/:
....:.:::::::::::::
S
~~~:·i:i!:·::!~·:::~
155
175
mA
;:::;:::;:; ;:~:~:~:~:~
L
iJI::::::::;:;;;;;::
S
tJIri:;:;:;:::~:::
6.5.
.:.:.:::::::.:::::::::::::::::
60
65
;1it
mA
::;:; ;:;:;:;:;:;:;:;:;:;:::
L
45
50
40/35
45/40
30/25
35/30
28
28
15
20
15
20
15
20
20
20
:;:::
::::\:)/i~:~:~:~:~
S
20
25
mA
L
NOTES:
1. All values are maximum guaranteed values.
2. f = fMAX (All inputs except Chip Select cycling at f
3. -55°C to + 125°C temperature range only.
0.3
1.5
0.3
1.5
0.3
1.5
= 1/tRd. f = 0 means no address or control lines change.
S4-13
1.5
1.5
IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K xl-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(L Version Only) VLC = 0.2V, VHC = Vee - 0.2V
TYP.(1)
SYMBOL
VDR
leeDR
TEST CONDITION
PARAMETER
MIN.
-
Vee for Data Retention
I
MIL.
COM'L.
Data Retention Current
t eDR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
Ilu l (3)
Input Leakage Current
CS~
\'IN
VHC
~ VHC ors VLC
Vee @
2.0V
3.0V
MAX.
Vee @
2.0V
3.0V
-
-
-
10
15
600
900
10
15
150
225
2.0
-
-
-
-
0
t RC (2)
-
NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output load
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
:q
5V
DATAoUT
2550
5V
480n
DATA OUT
30pF*
~
2550
Figure 1. Output load
4800
5pF*
Figure 2. Output Load
(for tHZ. t LZ • twz and tow)
* Including scope and jig.
84-14
UNIT
V
IlA
-
ns
2
IlA
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7187S/IDT7187LCMOS STATIC RAM 64K (64Kx 1-BIT)
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, All Temperature Ranges)
7187S85(2)
7187S25/30 . 7187S35/45 7187S55(2) 7187S70(2)
7187L8S(2) UNIT
7187L25/30
7187L35/45 7187L55 (2) 7187L70(2)
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX. MIN.
MAX.
7187S 15(1)/20
SYMBOL
PARAMETER'
MIN.
READ CYCLE
t Rc
Read Cycle Time
tAA
Address Access Time
t ACS
Chip Select Access Time
;.;:~:~::::::::-
15/20
-
25/30
-
35/45
-
55
-
70
-
85
-
-
25/30
-
35/45
-
55
-
70
-
85
ns
35/45
-
55
-
70
-
85
ns
5
:\:H5/20
:':::::15/20
.........
.','
25/30
-
5
-
5
5
-
5
5
-
-
5
-
5
-
5
-
5
-
ns
-:::.::::':\:
6
-
12/15
-
17/20
-
30
-
30
-
40
ns
g:.{:).
-
0
-
0
-
0
-
0
-
0
-
ns
15/20
-
20/30
-
30/35
-
35
-
35
-
40
ns
tOH
Output Hold from Address Change
5
tLZ
Chip Select to Output in Low Z (3)
5
tHZ
Chip Deselect to Output in High Z (3)
t pu
Chip Select to Power Up Time (3)
tpD
Chip Deselect to Power Down
Time(3)
:::::;:::;::;::
.::::::~.~:~::.;
::::;.;:::::
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS
(1,2)
_E~t"C'"
~-
tAA ------------~.'
-----tOH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.2 (1,3)
~------------
~-----
t RC (5)
-----------~
t ACS --------.j
tLZ (4)
DATA OUT
DATA VALID
HIGH IMPEDANCE
Vcc SUPPLY
CURRENT
~----~~~~~~~~~~~~
NOTES:
1.
2.
3.
4.
5.
ns
WE is High for READ Cycle.
CS is low for READ cycle.
Address valid prior to or coincident with CS transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
S4-15
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K xl-BIT)
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, All Temperature Ranges)
7187S85(2)
7187S35/45 7187S55(2) 7187S70(2)
7187S25/30
7187L85 (2) UNIT
7187L35/45 7187L55(2) 7187L70(2)
7187L25/30
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.
MAX. MIN.
MAX. MIN.
7187S15(1)/20
PARAMETER
SYMBOL
MIN.
WRITE CYCLE
12/1 E(::~~:::~::~::· -
20
-
20/25
-
0
-
0
15/20
-
15/25
5
-
5
-
6/8
-
12/15
-
15/30
-
30
-
30
-
40
ns
-
0
-
0
-
0
-
0
-
0
-
ns
twc
Write Cycle Time
12/15
tcw
Chip Select to End of Write
12/15
tAW
Address Valid to End of Write
12/15
t AS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
tOH
Data Hold Time
twz
Write Enable to Output in High
0
:.:.:::: :x::.
)t:::::::~
:':':.:.'
.:::::;::::::::? -
04::;:
8/tit:=:::;:::~tr::::··
Z(3)
Output Active from End of Write (3)
tow
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
-
.iiit::::;
:t:::it.
35/45
20/22
-
0
-
0
25/30
20/22
S4-16
25/40
25/40
-
70
50
50
-
55
0
-
0
35
-
0
-.
25
ns
65
-
0
-
ns
-
45
0
5
-
ns
-
-
85
40
0
-
30
-
35
5
-
5
-
55
55
65
ns
ns
ns
ns
ns
I OT7187S/1 OT7187L CMOS STATIC RAM 64K (64K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)
(1,2,3)
~----------------------twc----------------------~
ADDRESS
~-------------------
------------------~
t AW
t AS -~------------
t WZ
twp
-------.t
(5)
DATA OUT
_
_tDH~._
_. h - _ t D W
f--
DATA IN
~
DATA VALID
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)
(1,2,3,4)
twc
ADDRESS
~
---./
<
)(
tAW
"~
_ t AS -
./V
tWR
tcw
______________________
--
.~-tD-w---.-I.---tD-H~:-------
f--
DATA VALID
~
NOTES:
1.
2.
3.
4.
5.
wr::. or CS must be high during all address transitions.
A write occurs during the overlap (tw~ of a low CS and a low ~.
tWR is measured from the earlier of CS or wrc. going high to the end of the write cycle.
If the CS low transition occurs simultaneously with or after the wrc. low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
S4-17
IDT7187S/IDT7187L CMOS STATIC RAM 64K (64Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
MODE
CS
WE
Standby
H
Read
Write
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
OUTPUT
POWER
X
HighZ
Standby
CIN
Input Capacitance
L
H
DoUT
Active
COUT
Output Capacitance
L
L
HighZ
Active
CONDITIONS
MAX.
8
pF
VOUT= OV
8
pF
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.
ORDERING INFORMATION
IDT
xxxxx
A
Device Type
Power
999
Speed
A
A
Package
Processl
Temperature
UNIT
= OV
\'IN
RMy:rMk.
D
P
..............................--~
~
C
L
SO
E
F
Y
1....-------------1
15
20
25
30
35
45
55
70
85
"-_ _ _ _ _ _ _ _ _ _ _ _---11 S
IL
~..........----------------------------~--~7187
S4-18
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Ceramic DIP
Plastic DIP
Sidebraze DIP
Leadless Chip Carrier (specify 22 or 28 pins)
Small Outline IC
CERPACK
Flatpack
Small Outline (J-Bend)
~~~:~:~ g~:~ }
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (64K x 1-Bit)
t;)
CMOS STATIC RAM
256K (256K x 1-BIT)
Integrated DevIce"lechnol6sy.Inc.
PRELIMINARY
lOT 712575
lOT 71257L
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
- Military: 25/35/45/55/70ns (max.)
- Commercial: 20/25/35/45/55ns (max.)
The I DT71257 is a 262, 144-bit high-speed static RAM organized
as 256Kx 1.lt is fabricated using IDT's high-performance, high-reliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories.
Access times as fast as 20ns are available with typical power
consumption of only 350mW. The IDT71257 offers a reduced
power standby mode, 1561, which enables the designer to greatly
reduce device power requirements. This capability provides significant system level power and cooling savings. The low-power
(L) version also offers a battery backup data retention capability
where the circuit typically consumes only 1OO~W operation off a 2V
battery.
All inputs and outputs of the IDT71257 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The IDT71257 is packaged in a 24-pin 300 mil DIP, a 24-pin
SOIC, and a 28-pin Leadless chip carrier, providing high boardlevel packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
• Low-power operation
-IDT71257S
Active: 400mW (typ.)
Standby: 400~W (typ.)
-IDT71257L
Active: 350mW (typ.)
Standby: 100~W (typ.)
• Battery backup operation - 2V data retention (L version only)
• Produced with advanced CEMOS ™ high-performance
technology
•
•
•
•
Single 5V (±10%) power supply
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in high-density industry standard 24-pin, 300 mil DIP,
24-pin SOIC, and LCC.
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATION
Ao
Al
FUNCTIONAL BLOCK DIAGRAM
Ao
Vcc
A17
Ale
A2
A1S
A14
A13
A12
All
Al0
As
DIN
A3
A4
As
A6
A7
As
DOUT
wr=.
~GND
ADDRESSES
DECODER
A17
CS
DATAoUT
cs
GND
262,144-BIT
MEMORY ARRAY
DIP/SOle
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
S4-19
JANUARY 1989
D5C-l016/1
I DT71257S/1 DT71257L CMOS
STATIC RAM 256K (256K Xl-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOGIC SYMBOL
Ao
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
DIN
Al
A2
A3
A4
A5
A6
Militruy
Commercial
A7
A8
A9
SYMBOL
Al0
All
A12
A13
A14
A15
A16
VTERM
wr:.
~
INDEX
ULJIIUU
32U2827
A7
:J
:J
:J
:J
:J
:J
A8
:] 10
NC
A3
A4
A5
A6
DATA OUT
NC
1
4
26
r:
6
24 [:
7
23 [:
A14
L2S-2
9
22 [:
A13
21 [:
A12
5.0V
O°Cto +70oC
OV
5.0V
Vee
RATING
Terminal Voltage
with Respect to
GND
± 10%
± 10%
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
20 CAll
:J
11
19
r:
A10
:J
12
18 [:
NC
RECOMMENDED DC OPERATING CONDITIONS
13 14 15 16 17
SYMBOL
nnnnn
!U 0 IUl
j3: Z
(!l
z
(!)
IU-ic(
I-'
c(
o
LCC
TOP VIEW
PIN NAMES
Ao - A17
Addresses
DIN
Data Input
CS
Chip Select
WE
Write Enable
DOUT
GND
Data Output
Vee
Power
MIN.
TYP.
MAX.
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
-
6.0
V
-
O.S
V
Input Low Voltage
2.2
-0.5(1)
UNIT
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
Ground
DC ELECTRICAL CHARACTERISTICS
SYMBOL
OV
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speCification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NC
A16
A15
25 [:
5
8
GND
-55°C to + 125°C
ABSOLUTE MAXIMUM RATINGS
DOUT
A17
AMBIENT
TEMPERATURE
PARAMETER
Vee = 5.0V ±10%
IDT71257S
MIN.
MAX.
TEST CONDITIONS
-
10
5
-
10L = SmA, Vee = Min.
/lui
Input Leakage Current
Vee = Max., VIN = GND to Vee
MIL.
COM'L.
IILol
Output Leakage Current
Vcc= Max.
CS = VIH , VOUT = GND to Vee
MIL.
COM'L.
VOL
Output Low Voltage
VOH
Output High Voltage
IDT71257L
MIN.
MAX.
UNIT
-
5
2
J.lA
10
5
-
5
2
J.lA
-
0.4
-
0.4
V
10L = 10mA, Vee = Min.
-
0.5
-
0.5
V
10H = -4mA, Vee = Min.
2.4
-
2.4
-
V
S4-20
I DT71257S/I DT71257L CMOS
STATIC RAM 256K (256K xl-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (1) (VCC =
SYMBOL
POWER FUNCTION
PARAMETER
5V ±10%, VLC = 0.2V, VHC = VCC - 0.2V)
71257S20
71257L20
71257S25(4)
71257L25(4)
71257S35
71257L35
71257S45
71257L45
71257S55
71257L55
71257S70
71257L70
UNIT
COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL COML. MIL.
ICCI
ICC2
Operating Power
Supply Current
CS = VIL,
Outputs Open,
Vcc = Max., f = 0(3)
S
L
Dynamic Operating
Current
CS = VIL,
Outputs Open,
S
L
Vcc = Max., f = f MAX (3)
Standby Power
Supply Current
(TTL Level)
IS8
READ
70
-
60
70
50
60
50
60
50
60
WRITS2)
120
110
120
100
110
100
110
100
110
-
110
READ
50
-
40
50
30
40
30
40
30
40
-
40
WRIT8 2)
110
-
100
110
90
100
90
100
90
100
-
100
READ
170
-
160
170
150
160
150
160
150
160
-
160
WRITS2)
170
-
160
170
150
160
150
160
150
160
-
160
READ
150
-
140
150
130
140
130
140
130
140
140
WRIT8 2)
150
-
140
150
130
140
130
140
130
140
-
35
-
35
35
35
35
35
35
35
35
-
35
S
60
mA
140
mA
CS~\iH'
IS81
mA
Vcc = Max.,
Outputs Open,
f = fMAX(3)
L
20
-
20
20
20
20
20
20
20
20
-
20
Full Standby Power
Supply Current
(CMOS Level)
S
30
-
30
35
30
35
30
35
30
35
-
35
CS ~ VHC ' Vcc= Max.
f = 0(3)
L
1.5
-
4.5
1.5
4.5
1.5
4.5
mA
1.5
1.5
4.5
-
4.5
NOTES:
1. All values are maximum guaranteed values.
2. Write cycle current specifications are included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
read cycles to write cycles is extremely high. When comparing these figures to those on other data sheets, we recommend that the read cycle data is used
(especially where "Average" current consumption figures are specified).
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of l/tRC' f = 0 means no input lines change.
4. Preliminary data for military devices only.
CAPACITANCE
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CONDITIONS
CIN
MAX.
UNIT
VIN = OV
Input Capacitance
11
pF
COUT
Output Capacitance
VOUT= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
TRUTH TABLE
(VLC = 0.2V, VHC = Vcc - 0.2V)
WE
CS
X
H
OUTPUT
Hi-Z
MODE
Standby (IS8)
X
VHC
Hi-Z
Standby (IS81)
H
L
DOUT
Read
L
L
Hi-Z
Write
NOTE:
1.
H = "'H' L = VIL, X = Don't Care
S4-21
I DT71257S/1 DT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC ;" Vcc - 0.2V
SYMBOL
VOR
ICCDR
TEST CONDITIONS
PARAMETER
-
Vcc for Data Retention
Data Retention Current
t COR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
CS ~VHC
MIN.
I MIL.
I COM'L.
TYP.(1)
V ee @
2.0V
3.0V
-
-
-
-
-
50
75
2000
3000
50
75
500
750
-
-
-
-
ns
-
-
-
ns
0
t RC (2)
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
5V
DATAOLrr
~
2550
4800
DATAoLrr
30pF*
~
2550
480n
5pF*
Figure 2. Output Load
(for tOLZ' tCLZ. tOHZ'
tWHZt tCHZ. tow)
Figure 1. Output Load
*Including scope and jig.
S4-22
UNIT
2.0
NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter Is guaranteed, but not teste~.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
MAX.
Vee@
2.0V
3.0V
V
J.LA
1DT71257S/IDT71257L CMOS
STATIC RAM 256K (256K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Ncc = 5V ±10%. All Temperature Ranges)
71257S20(1)
71257L20(1)
MIN. MAX
71257S25
71257L25
MIN. MAX.
71257S35
71257L35
MIN. MAX.
71257S45
71257L45
MIN. MAX.
71257S55
71257L55
MIN. MAX.
71257S70(2)
71257L70(2)
MIN. MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
20
-
25
-
35
-
45
-
55
-
70
-
ns
tAA
Address Access Time
20
-
35
-
45
ns
-
35
-
45
-
70
25
-
55
Chip Select Access Time
-
25
t Acs
-
70
ns
tcLZ
Chip Select to Output in Low Z (3)
5
0
-
ns
0
-
5
0
-
5
0
-
5
Chip Select to Power Up Time (3)
-
5
t pu
-
tpD
Chip Deselect to Power Down Time(3)
20
-
45
-
55
-
70
ns
10
13
-
35
Chip Deselect to Output in High Z(3)
-
25
tCHZ
-
15
-
20
-
25
-
30
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
-
5
-
ns
20
5
0
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
S4-23
0
55
ns
IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~
.......- - - - - - - - - tRc
ADDRESS
----------%;'""
. -1-----
""~'r--:----:--------:----:-----tAA-::::::::::::::~
1ooI'r------ tAos -----~
14----- t CLZ (4) -----I~
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
(1,2)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.3 (1,3)
DATA OUT
NOTES:
wr:.
1.
is high for read cycle.
2. Device is continuously selected, CS = V1L •
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state with 5pF load (including scope and jig).
S4-24
-to-H
-------
IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256K xl-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
0lcc = 5V ±10%, All Temperature Ranges)
71257S20(1) 71257S25
71257L20(1) 71257L25
MIN. MAX. MIN. MAX.
71257S35
71257L35
MIN. MAX.
71257S45
71257L45
MIN. MAX.
71257S55
71257L55
MIN. MAX.
71257S70(2)
71257L70(2)
MIN. MAX
UNIT
WRITE CYCLE
twc
Write Cycle Time
20
tcw
Chip Select to End of Write
20
tAW
Address Valid to End of Write
20
-
20
-
30
-
40
20
30
40
20
-
40
40
0
-
0
-
20
30
-
-
50
-
60
-
60
-
ns
50
50
-
60
-
ns
0
-
0
-
ns
50
60
-
ns
ns
ns
tWR
Write Recovery Time
0
-
0\
-
0
-
0
-
0
-
0
-
tWHZ
Write Enable to Output in High Z (3)
-
13
-i
13
-
15
-
20
-
25
-
30
ns
tDW
Data Valid to End of Write
15
-
15
20
-
30
-
0
0
0
-
0
5
-
5
-
5
-
ns
0
-
35
Data Hold Time
-
25
tDH
-
t As
Address Set-up Time
0
twp
Write Pulse Width
20
Output Active from End of Write (3)
tow
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
5
5
S4-25
30
0
0
5
ns
ns
IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1
(WE CONTROLLED TIMING)
(1,2,3)
two
ADDRESS
)K
~(
tAW
~~
)1'
t AS
twp
tWR-':'
"
/'
_tWHZ(5~
-
tOW--./
DATAoUT
·------IC::F
tow
.1.
I
tOH
TJMING WAVEFORM OF WRITE CYCLE NO.2 (1,2,3,4)
(CS CONTROLLED TIMING)
two
ADDRESS
~(
)(
---./
tAW
'~
~V
t AS
tWR
tow
-
/rt'
-----II::f= t~
NOTES:
1. WE or ~ must be high during a/l address transitions.
2. A write oocurs during the overlap (tow or tw~ of a low ~ and a low WE.
3. tWR is measured from the earlier of ~ or WE going high to the end of the write cycle.
4. If the ~ low transition occurs simultaneous with or after the WE low transit/on, the outputs remain In the high Impedance state.
5. Transition Is measured ±200mV from steady state with a 5pF load (Including scope and jig).
S4-26
IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)
MILITARY· AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
Device Type
A·
Power
999
A
A
Speed
Package
Processl
Temperature
Range
y:Mk
L--_ _ _ _ _ _ _~
.
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant with MIL-STD-883, Class B
P
L
C
SO
Y
Plastic DIP
Leadless Chip Carrier
Sidebraze DIP
Small Outline IC (gull-wing)
Small Outline IC O-bend)
20
25
35
45
55
70
Commercial Only
) Spoed", Nano.."""',
Military Only
IL
1S
LOw Power
Standard Power
: 71257
256K (256K x 1-Bit) Static RAM
S4-27
_ _ _ 0_ _ _ -
_ _- - - _ . _ - - - - - - - - - - -
_ _ _ _ • • _0 _ _ ••••• _
••••
lOT 6168SA
lOT 6168LA
CMOS STATIC RAM
16K (4K x 4-BIT)
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
- Military: 15/20/25/35/45/55/70/85/100ns ,(max.)
- Commercial: 12/15/20/25/35ns (max.)
• Low power consumption
- IDT6168SA
Active: 225mW (typ.)
Standby: 100~W (typ.)
-IDT6168LA
Active: 225mW (typ.)
Standby: 10~W (typ.)
• Battery backup operation-2V data retention voltage
(IDT6168LA only)
• Available In high-density 20-pin CERDIP and plastic DIP,
20-pin SOIC, 20-pin Flatpack and CERPACK and 20-pin
leadless chip carrier
• Produced with advanced CEMOS ™ high-performance
technology
• CEMOS process virtually eliminates alpha particle soft-error
rates
• Bidirectional data input and output
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state outputs
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-86705 is listed on this
function. Refer, to Section 2/page 2-4.
The IDT6168 is a 16,384-bit high-speed static RAM organized as
4K x 4. It is fabricated using IDT's high-performance, high-reliability technology-CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques, provides a
cost effective alternative to bipolar and fast NMOS memories.
Access times as fast as 12ns are available with maximum power
consumption of only 550mW. The circuit also offers a reduced
power standby mode. When CS goes high, the circuit will automatically go to, and remain in, a standby mode as long as CS remains high. In the standby mode, the device consumes less than
10~W, typically. This capability provides significant system-level
power and cooling savings. The low-power (LA) version also offers
a battery backup data retention capability where the circuit typically consumes only 1~W operating off a 2V battery.
All inputs and outputs of the IDT6168 are TTL-compatible and
operate from a single 5V supply, thus simplifying system designs.
Fully static asynchronous circuitry is used, which requires no
clocks or refreshing for operation, and provides equal access and
cycle ti mes for ease of use.
The IDT6168 is packaged in either a space saving 20-pin, 300
mil CERDIP or plastic DIP, 20-pin flatpack or CERPACK, 20-pin
SOIC, or 20-pin lead less chip carrier, providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
LOGIC SYMBOL
Ao
A,
A2
A3
A4
A5
Ae
A7
As
A9
A,o
All
~
1/01
A
Vee
GND
DECODE
1/0z
16,384-BIT
MEMORY ARRAY
liDs
1104
WE
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-lOO8/-
S4-28
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4Kx 4·BIT)
PIN CONFIGURATIONS
~.t-»J
Ao
Al
A2
A3
Vee
A4
As
A5
1/04
1/0:3
All
A10
A3
A10
Ag
A4
As
A5
A6
1/04
1/0:3
A7
I/O:!
A2
Ag
A6
A7
I/O:!
CS
1/01
GND
VIr=.
911
Fu~~gLCC
TOP VIEW
DlP/SOIC/FLATPACK/CERPACK
TOP VIEW
RECOMMENDED DC OPERATING CONDITIONS
PIN NAMES
Ao-All
Address Inputs
1/01 -1/04
Data Input/Output
CS
Chip Select
Power
WE
Write Enable
Vee
GND
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA
RATING
Terminal Voltage
with Respect to
GND
Operating
Temperature
SYMBOL
Ground
MIN.
TYP.
MAX.
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
UNIT
VtH
Input High Voltage
2.2
-
6.0
V
VtL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Oto +70
-55 to +125
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
TSIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
Commercial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating can·
ditions for extended periods may affect reliability.
S4-29
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6168SA/lDT6168LA CMOS STATIC RAM 16K (4Kx 4-BIT)
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%
SYMBOL
Ilul
IILol
TEST CONDITION
PARAMETER
Input Leakage Current
Vee = Max., VIN = GND to Vee
Output Leakage Current
Vee = Max.
~ = VIH , VOUT = GND to Vee
MIN.
MIL.
COM'L.
-
MIL.
COM'L.
-
-
-
IOL = 10mA, Vee = Min.
VOL
Output Low Voltage
IOL = SmA, Vee = Min.
2.4
VOH
IOH= -4mA, Vee = Min.
Output High Voltage
. NOTE:
1. Typieallimits are at Vee = 5.0V. + 25°C ambient.
IDT6168SA
TYP.(l) MAX.
-
IDT6168LA
MIN. TYP.(1) MAX.
UNIT
-
5
2
J.l.A
-
-
-
5
2
J.l.A
0.5
-
-
0.5
V
0.4
-
-
0.4
V
-
2.4
-
-
V
-
10
2
-
-
10
2
DC ELECTRICAL CHARACTERISTICS (1)
Vee = 5.0V ±10%, VLe = 0.2V, VHe = Vee -0.2V
SYMBOL
leel
lec2
ISB
ISBl
,PARAMETER
Operating Power
Supply Current
CS = VILOutputs Open
Vee = Max.,
f = 0(3)
Dynamic
Operating Current
CS = VILOutputs Open,
Vec = Max.,
f = fMAX(3)
Standby Power
Supply Current
(TTL Level)
CS ~VIH,
Vee = Max .•
Outputs Open,
f = f MAX(3)
120
90
100
90
100
90
100
-
100
-
-
-
70
SO
70
SO
70
80
-
SO
165
-
145
165
120
120
110
120
100
110
-
LA
-
-
-
-
100
110
90
100
SO
90/80
SA
65
-
55
60
45
45
35,
45
30
35
110
LA
-
SA
-
100
mA
.
-
SO
110
-
110
-
SO
-
SO
-
35
-
35
.
mA
LA
-
-
-
-
30
35
25
30
20
25
-
20
-
20
SA
20
-
20
30
20
20
2
10
2
10
-
10
-
10
mA
LA
(3)
0
-
. 110
SA
mA
Full Standby
Power Supply
Current (CMOS
level)
CS ~ VHe ,
Vee= Max.,
\'IN ~ VHC or
\'IN:S VLC , f =
6168SA35/45(4) 6168SA55 6168SA70(2)
6168SA25
6168SA20
6168LA35/45(4) 6168LA55 6168LA70(2) UNIT
6168LA25
6168LA20
6168SA15
POWER 6168SA12
COM'L. MIL. COM'L. MIL COM'L.MIL. COM'L MIL. COM'L MIL.
COM'L. MIL. COM'L MIL
-
-
-
-
0.5
5
0.05
0.3
0.05
0.3
c
NOTES:
1. All values are maximum guaranteed values.
2. Also available 85 and lOOns military devices.
3. f = fMAX (All inputs except Chip Select cycling at f = l~d. f = 0 means no address or control lines change.
4. -55°C to + 125°C temperature range only.
S4-30
-
0.3
-
0.3
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
DATA RETENTION CHARACTERISTICS (LA Version Only)
PARAMETER
SYMBOL
VDR
ICCDR
TEST CONDITION
IDT6168LA
TYP(1)
MIN.
-
V
MIL.
0.5(2)
1.0(3)
100(2)
150(3)
~
COM'L.
-
0.5(2)
1.0(3)
20(2)
30(3)
~
CS ~ Vcc -0.2V
\1N
t CDR(5)
Chip Deselect to Data Retention Time
t R(5)
Operation Recovery Time
~
Vcc -0.2V or::; 0.2V
-
-
0
-
t RC (2)
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
\1H
AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
DATAoUT
~
2550
5V
480n
DATAoUT
30pF*
~
2550
Figure 1. Output Load
4800
5pF*
Figure 2. Output Load
(for t HZ' tu. twz and tow)
* Including scope and jig.
S4-31
ns
ns
NOTES:
1. TA = +25°C
2. atVee = 2V
3. atVcc = 3V
4. t RC = Read Cycle Time
5. This parameter is guaranteed but not tested.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
UNIT
-
2.0
Vee for Retention Data
Data Retention Current
MAX.
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4Kx 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBO
PARAMETER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vcc = 5.0V ±10%, All Temperature Ranges)
6168SA12(3) 6168SA15
MIN. MAX. MIN. MAX.
6168SA20/25 6168SA35/45(1) 6168SA55(1) 6168SA70(1)
6168LA20/25 6168LA35/45 (1) 6168LA55(1) 6168LA70(1) UNIT
MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX.
READ CYCLE
tRc
Read Cycle Time
12
-
15
-
20/25
-
35/45
-.
tM
Address Access Time
12
-
15
-
20/25
-
35/45
tAcs
Chip Select Access Time
-
12
-
15
-
20/25
-
tOH
Output Hold from Address Change
3
3
-
5
tLZ
Chip Select to Output in Low z(2)
3
-
3
-
5
-
tHZ
Chip Deselect to Output in High Z(2)
-
7
-
8
-
tpu
Chip Select to Power Up Time(2)
0
-
0
-
tpD
Chip Deselect to Power Down Time (2)
-
12
-
15
55
-
70
-
ns
55
-
70
ns
35/45
-
55
-
70
ns
5
-
5
-
5
-
ns
5
-
5
-
5
-
ns
10
-
15
-
25
-
30
ns
0
-
0
-
0
-
0
-
ns
-
20/25
-
35/40
-
50
-
60
ns
NOTES:
1. -55°C to +25°C temperature range only. Also available 85 and 100ns military devices.
2. This parameter Is guaranteed but not tested.
3. O°C to + 70°C temperature range only.
S4-32
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K X 4-81T)
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
1(1.2)
-Gt~
DATA OUT
tAA
-------~
••
PREVIOUS DATA VALID
TIMING WAVEFORM OFREAD CYCLE NO.
DATA VALID
2(1.3)
1-.--------- t
t-------
tACS
RC(5) ----------~
-----..-j
tLZ (4)
DATA OUT
DATA VALID
HIGH IMPEDANCE
VCC SUPPLY
CURRENT
~
____
~~~~~~~~t~~~~
NOTES:
1.
2.
3.
4.
5.
6.
WE is High for READ Cycle.
"CS is low for READ cycle.
Address valid prior to or coincident with "CS transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
This parameter is guaranteed and not 100% tested.
S4-33
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBO
PARAMETER
(Vcc = 5.0V ±100/0, All Temperature Ranges)
6168SA20/25 6168SA35/45(1) 6168SA55(1) 6168SA70(1)
6168SA12 (4) 6168SA15 6168LA20/25 6168LA35/45(1) 6168LA55 (1) 6168LA70(1) UNIT
MAX. MIN.
MAX. MIN. MAX. MIN. MAX.
MIN. MAX MIN. MAX. MIN.
WRITE CYCLE
twc
Write Cycle Time
12
-
15
-
20
tcw
Chip Select to End of Write
12
-
15
20
tAW
Address Valid to End of Write
12
-
15
-
t AS
Address Set-up Time
0
-
0
twp
Write Pulse Width
12
-
tWR
Write Recovery Time
0
tow
Data Valid to End of Write
30/40
20
-
-
0
-
0
15
-
20
-
30/40
-
0
-
0
-
0
8
-
9
10
15/20
30/40
30/40
-
50
-
60
-
ns
50
-
60
-
ns
50
-
60
-
ns
-
0
-
0
-
ns
50
-
60
-
ns
0
-
0
-
ns
25
-
ns
-
tOH
Data Hold Time
0
-
0
-
0
-
0/3
-
3
-
3
-
ns
twz
Write Enable to Output in HighZ(2)
-
5
-
6
-
7
-
13/20
-
25
-
30
ns
tow
Output Active from End of Write!2)
0
-
0
-
0
-
0
-
0
-
0
-
ns
20
NOTES:
1. -55°C to + 125°C temperature range only. Also available 85 and 100ns military devices.
2. This parameter is guaranteed but not tested.
3. The specification for t OH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and ow values will
vary over voltage and temperature, the actual tOH will always be smaller than the actual ow.
4. O°C to + 70°C temperature range only.
S4-34
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1.2.3)
ADDRESS
~<-----------------------------')~-----------~.............................................-tAW""'''''''''''----'''''--'''''--~
_ t AS
~,
/~
'---------------------------~
_
t (6)_
WZ
DATA OUT
-----------~C,~. •._. _____._. .•
,.~ .~----------------+_-------t-OW-(-6)-~----__C~~~>- -.~
. ••• ••• -(4-)••....
_(4_)_
•• _____••
__________________________________
-K~-tO-,W---D-AT-:-V-:-L-ID---tO_H_~~-----------------
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(1.2.3.5)
two
ADDRESS
~
----/
<
)(
tAW
~tAS
"
/V
tWR
tow
t=tow
------------------------------------I 1K
~
TA (tc)
1.2
en
'\
~ 10.0 t - - - - t - - t - - + t - - - I
\
100
J~
J
~
.... 1.0
~
1.0 1----+--+-+---f----1
10.0
1.0
o
.J
2
Supply Voltage
100.0 I - - - - + - - l - - - - f - - - . I
A
10K
VS.
II
j
Vee = 5.0V_
TA = 25°C
100K
t AA • t ACS
I CCDR VS. Temperature
IS81 VS. V 1N
3
V1N (V)
4
5
6
.8
4.0
-60
"
5.0
Vee (V)
t AA • tACS \IS. Temperature
t AA • tACS vs. Output Loading
1.2
1.2
en
en
()
()
~
~
j
j
1.0
1.0
.8
1...--_--1.._ _.1.-_--1.._ _.....1
o
100
C L (pF)
S4-37
200
6.0
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4Kx 4-81T)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXX)(
A
Device Type
f.5OW9r
999
Sp d
A
A
Package
Process/
Temperature
Range
y:mnk
'---------i
~
P
D
L
SO
F
E
Y
12
15
20
25
______________--;35
45
55
70
90
100
~
______________________~ISA
ILA
~--------------------------~6168
S4-38
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class 8
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
Flatpack
CERPACK
Small Outline (J-8end)
Commercial Only
Military Only
Military Only
Military Only
Military Only
Military Only
Standard Power
Low Power
16K (4K x 4-8it)
Speed in Nanoseconds
t;)
Integrated Device'JechnoIosy.lnc.
Separate Data Inputs and Outputs
DESCRIPTION:
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Separate data inputs and outputs
IDT71681SNLA: outputs track inputs during write mode
IDT716821SNLA: high impedance outputs during write mode
High-speed (equal access and cycle time)
- Military: 15/20/25/35/45/55/70/85/100ns (max.)
- Commercial: 12/15/20/25/35/45ns (max.)
Low power consumption
- IDT71681/2SA
Active: 225mW (typ.)
Standby: 100llW (typ.)
- IDT71681/2LA
Active: 225mW (typ.)
Standby: 10llW (typ.)
Battery backup operation - 2V data retention (L version only)
High-density 24-pin 300-mil CERDIP and plastic DIP, 24-pin
Flatpack and CERPACK, 24-pin SOIC (gull-wing or J-bend)
and 28-pin leadless chip carrier
Produced with advanced CEMOS ™ high-performance
technology
CEMOS process virtually eliminates alpha particle soft-error
rates
'
The IDT71681/IDT71682 are 16,384-bit high-speed static RAMs
organized as 4K x 4. They are fabricated using IDT's highperformance, high-reliability technology-CEMOS. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost effective alternative to bipolar and fast
NMOS memories.
Access times as fast as 12ns are available, with maximum
power consumption of only 550mW. These circuits also offer a reduced power standby mode (lsB). When CS goes high, the circuit
will automatically go to, and remain in, this standby mode as long
as CS remains high. In the ultra-low-power standby mode (ISB1),
the devices consume less than 10llW, typically. This capability provides significant system-level power and cooling savings. The lowpower (L) versions also offer a battery backup data retention capability where the circuit typically consumes only 11lW operating off a
2V battery.
All inputs and outputs of the IDT71681/IDT71682 are TTLcompatible and operate from a single 5V supply, thus simplifying
system designs. Fully static asynchronous circuitry is used, which
requires no clocks or refreshing for operation, and provides equal
access and cycle times for ease of use.
The IDT71681/IDT71682 are packaged in either space-saving
24-pin 300 mil DIPs, SOICs, Flatpacks, CERPACKS, or 28-pin
leadless chip carriers, providing high board-level packing densities.
Military grade product is manufactured in compliance with the
. latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Three-state output
Static operation: no clocks or refresh required
Military product compliant to MIL-STD-883, Class B
LOGIC SYMBOL
lOT 71681 SA/LA
lOT 71682SA/LA
CMOS STATIC RAMS
16K (4K x 4-BIT)
FUNCTIONAL BLOCK DIAGRAM
A
Vee
GND
DECODE
16.384-BIT
MEMORY ARRAY
I/O
L ________ J
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY.1989
DSC-1022/-
1989 Integrated Develce Technology. Inc.
S4-39
9
~
1DT71681 SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vcc
Ao
Al
A2
A3
A4
INDEX
All
A10
Ag
A8
D4
A5
Ae
A7
Dl
D2
D3
Y4
Ae
Y3
Y2
Yl
~
A7
Dl
12 13 14 15 le 17 18
~
GND
:J e
:J 7
:J 8
:J 9
:J 10
:J 11
nnnnnnn
DIP/SOIC/FLATPACK/CERPACK
TOP VIEW
LCC
TOP VIEW
RECOMMENDED DC OPERATING CONDITIONS
PIN NAMES
Ao-All
Address Inputs
Dl - D4
DATA IN
MIN.
TYP.
MAX.
UNIT
CS
Chip Select
~
DATA OUT
Vcc
Supply Voltage
4.5
5.0
5.5
V
WE
Write Enable
Ground
GND
Supply Voltage
0
0
0
V
Vcc
Power
"IH
Input High Voltage
2.2
-
6.0
V
"IL
Input Low Voltage
-0.5(1)
-
0.8
V
-Y4
GND
ABSOLUTE MAXIMUM RATINGS
SYMBOL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
PARAMETER
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
(1)
COMMERCIAL
VTERM
RATING
Terminal Voltage
with Respect to
GND
SYMBOL
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
S4-40
AMBIENT
TEMPERt\TURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
IDT71681SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
v.ee --
50V +10%
SYMBOL
TEST CONDITION
PARAMETER
MIL.
COM'L.
Vee = Max., ~N = GND to Vee
Ilu l
lriput Leakage Current
IlLOI
Output Leakage Current
VOL
Output Low Voltage
IOL = 8m A, Vcc = Min.
-
IOH= -4mA. Vcc = Min.
2.4
Vee =
MIL.
COM'L.
Max.
~ = '-"H, VOUT= GNDtoVee
10L = 10mA, Vec = Min.
VOH
Output High Voltage
IDT71681SA
IDT71682SA
TYP.(1) MAX.
MIN.
10
5
-
-
IDT71681LA
IDT71682LA
MIN. TYP.(l) MAX.
5
2
0.4
-
-
2.4
10
5
0.5
UNIT
J.LA
-
5
2
~A
-
0.5
V
-
0.4
V
-
-
V
NOTE:
1. Typicallimits are at Vcc = 5.0V, + 25°C ambient.
DC ELECTRICAL CHARACTERISTICS(l)
Vec = 50V -+10% VLC = 02V VHC = Vcc - 02V
ISYMBOL PARAMETER
ICCl
ICC2
Operating Power
Supply Current
CS = VIL,
Outputs Open,
Vcc = Max.,
f = 0(3)
Dynamic
Operating Current
CS = VIL ,
Outputs Open,
Vcc = Max.,
f = fMAX(3)'
Standby Power
Supply Current
(TIL Level)
ISB
SA
110
-
110
120
71681x20
71682x20
COM'L. MIL.
90
100
71681x25
71682x25
71681x35
71682x35
COM'L. MIL.
COM'L. MIL.
90
100
90
100
71681x55(6) 71681x70(2,6
71682x55(6) 71682x70(2,6 UNIT
COM'L. MIL. COM'L. MIL.
COU'L. MIL.
71681x45
71682x45
90
100
-
100
-
100
mA
LA
-
-
-
-
70
80
70
80
70
80
80
-
80
-
80
SA
165
-
145
165
120
120
110
120
100
110 100
110
-
110
-
110
LA
-
-
-
-
100
110
90
100
80
90
70
80
-
80
-
80
SA
65
-
55
65
45
55
35
45
30
35
30
35
-
35
-
35
70
mA
mA
CS ~ "'H'
Vcc = Max.,
Outputs Open
f = f MAX (3)
ISBl
71681x12 71681x15
POWER 71682x12 71682x15
COM'L.MIL. COM'L. MIL.
Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHC'
Vcc= Max.,
VIN ~VHC or
VIN:S VLC ' f = 0(3)
LA
-
-
-
-
30
35
25
30
20
25
20
25
-
20
-
20
SA
20
-
20
30
20
30
2
10
2
10
2
10
-
10
-
10
mA
LA
-
- -
-
0.5
5
0.05
0.3
0.05
0.3 0.05
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 85ns and lOOns Military devices.
3. At f
fMAX address and data inputs are cycling at the maximum frequency of read cycles of l/tRC . f
4. "x' in part numbers indicates power rating (SA or LA).
5. O°C to + 70°C temperature range only.
6. -55°C to + 125°C temperature range only.
=
S4-41
0.3
-
0.3
-
= 0 means no input lines change.
0.3
IDT71681 SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS
(L Version Only)
VOR
IDT71681LA -1DT71682LA
TYP,(1)
MAX.
MIN.
TEST CONDITION
PARAMETER
SYMBOL
Vcc for Data Retention
MIL.
ICCDR
tCOR(5)
t R(5)
CS ~ Vcc - 0.2V
~ VCC - 0.2V
or S 0.2V
Data Retention Current
\'IN
COM'L.
Chip Deselect to Data Retention Time
O~eration Recoverv Time
2.0
-
-
. 0.5(2)
-
0
-
t RC (4)
-
1.0(3)
20(2)
30(3)
-
DATA RETENTION MODE
Vee
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
:
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
DATAoUT
~
2550
..
5V
4800
DATAoUT
30pF*
~
2550
Figure 1. Output Load
4800
5PF*
Figure 2. Output Load
(for t HZ ' tLZ' twz and tow)'
* Including scope and jig.
S4-42
150(3)
1.0(3)
LOW Vee DATA RETENTION WAVEFORM
V
100(2)
0.5(2)
NOTES:
1. TA = +25°C
2. atV~c= 2V
3. at Vcc = 3V
4. t RC = Read Cycle Time
5. This parameter is guaranteed but not tested.
UNIT
J.lA
J.lA
ns
ns
1DT71681SAjLA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4K X 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(4) Nee =
SYMBOL
PARAMETER
5V ±10%. All Temperature Ranges)
71681x12(1) 71681x15
71681x35
71681x45 71681 x55 (2) 71681x7O<2
71681x20
71681x25
71682x12(1) 71682x15
71682x35
71682x45 71682x55(2) 71682x70(2 UNIT
71682x20
71682x25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
tRC
Read Cycle Time
12
-
15
-
20
-
25
-
35
-
45
-
55
-
70
-
ns
tAA
Address Access Time
-
12
-
15
-
20
-
25
-
35
-
45
-
55
70
ns
t ACS
Chip Select Access
Time
-
12
-
15
-
20
-
25
-
35
-
45
-
55
-
70
ns
tOH
Output Hold from
Address Change
3
-
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Select to
Output in Low Z (3)
3
-
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to
Output in High Z (3)
-
7
-
7
-
9
-
10
-
15
-
20
-
25
-
30
ns
t pu
Chip Select to Power
Up Time(3)
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tpD
Chip Deselect to
Power Down Time (3)
-
10
-
15
-
20
-
25
-
35
-
40
-
50
-
60
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
4. ·x· in part numbers represents SA or LA.
S4-43
IDT71681 SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4K x 4.BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1,2)
t
R
C(5)
----------~~
......- -
ADDRESS
tM ---------~.~'
DATA OUT
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
2(1,3)
14--------- t RC (5) ---------.j
t LZ (4)
DATA OUT
DATA VALID
HIGH IMPEDANCE
Vcc SUPPLY
CURRENT
~-----~-J,-------~-tro=1,,-_
NOTES:
1.
2.
3.
4.
5.
WE" is High for READ Cycle.
~ is low for READ cycle.
Address valid prior to or coincident with ~ transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
84-44
IDT71681SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4Kx 4-Bm
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(4)
SYMBOL
PARAMETER
(Ycc = 5V -+10%. All Temperature Ranges)
71681x12(1) 71681x15
71681x25
71681x45 71681x55(2) 71681x70(2
71681x35
71681x20
71682x12(1) 71682x15
71682x45 71682x55(2) 71682x70(2 UNIT
71682x20
71682x25
71682x35
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
WRITE CYCLE
-
20
-
20
-
30
-
40
-
50
-
60
-
ns
20
-
20
-
25
-
35
-
50
-
60
-
ns
15
-
20
-
20
-
25
-
35
-
60
0
-
0
-
0
0
-
0
20
30
-
35
ns
0
0
0
-
0
-
0
-
40
-
-
25
0
-
-
ns
20
-
0
15
-
-
50
0
0
-
ns
9
-
10
-
10
-
15
-
20
-
25
-
ns
-
0
-
0
-
3
-
20
3
-
3
-
3
-
ns
40
ns
15
10
-
10
-
0
twc
Write Cycle Time
12
tcw
Chip Select to
End of Write
tAW
Address Valid to
End of Write
15
t AS
Address Set-up Time
twp
Write Pulse Width
tWR
Write Recovery Time
0
tDW
Data Valid to
End of Write
8
-
tDH
Data Hold Time
0
-
0
t ly
Data Valid to Output
Valid (71681 only)(3)
-
12
-
15
-
20
-
25
-
30
-
35
-
35
-
10
"
ns
twy
Write Enable to OutFut
Valid (71681 only)(3
-
12
-
15
-
20
-
25
-
30
-
35
-
35
-
40
ns
twz
Write Enable to Output
in HIGH Z (71682 onlyj3)
-
5
-
6
-
7
-
7
-
13
-
20
-
25
-
30
ns
tow
Output Active from End
of Write (71682 only) (3)
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
4. "x" in part numbers represents SA or LA.
S4-45
0
-
IDT71681 SAl LA AND IDT71682SA/LA
CMOS STATIC RAM 16K(4Kx4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
twc
ADDRESS
~{
~{
//// //
'\. '\.'\.
tAW
t WR twp
~~
'\. ~~
}£
: - - t AS -
tow
"
I
DATA IN
!.DATA OUT (6)
J\.
- t ly twv
'If
DATA UNDEFINED
DATA OUT (5)
"
DATA VALID
J\.
I.
t OH -
DATA VALID
J~
I tow (2. 4)
t WZ (4=:f
~
~
DATA UNDEFINED
I'
HIGH IMPEDANCE
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
t
wC
(3)
II
j(
ADDRESS
'II"
--11\.
- t AS
tcw
~~
)'£
tAW
"
...'\.
t WR -
)1'////// //h
'\.'\.'\.'\.
tow
'(
DATA IN
DATA VALID
- tly twv
DATA OUT (5)
I--DATA OUT (6)
;K
DATA UNDEFINED
tOH
"
j'\.
DATA VALID
t wZ (4)
'\.
DATA UNDEFINED
I
NOTES:
1.
2.
3.
4.
5.
6.
-
wr= or CS must be high during all address transitions.
If CS goes high simultaneously with M high. the outputs remain in the high impedance state.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±200 mV from steady state voltage with specified loading in Figure 2.
For IDT71681 only.
For IDT71682 only.
S4-46
HIGH IMPEDANCE
IDT71681 SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K(4Kx4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
SYMBOL
(TA= ...25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
OUTPUT
POWER
X
HighZ
Standby
CIN
Input Capacitance
L
H
DoUT
Active
COUT
Output Capacitance
Write (1)
L
L
DIN
Active
Write (2)
L
L
HighZ
Active
MODE
CS
WE
Standby
H
Read
MAX.
UNIT
\IN = OV
8
pF
VOUT= OV
8
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
NOTES:
1. For IDT71681 only.
2. For IDT71682 only.
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
Icc vs. Supply Voltage
Icc vs. Temperature
T~ = +25tC
u
1.0
V
V
5.0
TA = +25°C
1.5 I - - - - t - - _ t _ - - i - - - I
1.5
1.0
1----t~~_t_--i--4
1.0
.5
L...-_--1_ _....L..._ _..L.-_--l
.5
u
...Y
.5
4.0
I
Vee = 5.0V
1.5
...Y
ISB vs. Supply Voltage
6.0
-60
40
140
V
V
4.0
TA (0C)
Vee (V)
ISB vs. Temperature
ISB1 vs. Supply Voltage
Vee = 5.0V
6.0
ISB1 vs. Temperature
Tl = +25!C
1.5
5.0
Vee (V)
100.0 1 - - - - 4 - - 4 - - - + - - - 1
1.2
OJ
ill
_U)
_U)
1.0
1.0
0.5 '------'---'---"'-----'
-60
40
140
TA (0C)
0.8
4.0
V
ffi 10.0
/
1----4--4---+-1---1
1.0 ) - - - - t - - - : z " " t - - - i - - - i
5.0
6.0
-60
Vec (V)
S4-47
- - - - - - - - - - - - _ . _ - - - - - - .. _--
140
, IDT71681 SA/LA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
JVee = 15.0V,I.,.--
100K
TA = +25°C
VJ
~ 10.0 I - - - - t - - t - - + t - - - - i
\
100
~
J:
~
.... 1.0
1.0 I - - - - t - + - t - - - t - - - - i
10.0
.J
o
(tc)
1.2
V ~ i'\
1K
1.0
TA
100.0 1 - - - - t - - t - - - t - - " 1 I
A
10K
~
tAA • tACS vs. Supply Voltage
ICCDR vs. Temperature
vs. V1N
isB1
2
3
V1N
4
5
6
.8
4.0
140
-60
""
5.0
M
VeeM
W\ • ~cs vs. Temperature
tAA • ~cs vs. Output Loading
1.2
1.2
VJ
VJ
J:
J:
}
}
1.0
1.0
.8
L..--_--'-_ _.L...-_-"-_ _-'
o
'100
C L (pF)
S4-48
200
6.0
~
...•..--.-.••........ - - - - - - -.. - - - - - - - - - - -
IDT71681SNLA AND IDT71682SA/LA
CMOS STATIC RAM 16K (4Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxxx
999
A
A
Device Type
Speed
Package
Process!
Temperature
Range
Y:,ank
Commercial (O°C to
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Small Outline IC (J-Bend)
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC (Gull-Wing)
CERPACK
Flatpack
Y
L -____________
~
P
D·
L
SO
E
F
Commercial Only
12
15
20
25
L -_ _ _ _ _ _ _ _ _ _---I 35
45
~
________________________
~I
Speed in Nanoseconds
55
70
85
100
Military
Military
Military
Military
SA
Standard Power
Low Power
ILA
L----------~
__________I
+ 70°C)
Only
Only
Only
Only
16K (4K x 4-Bit) Outputs Follow Inputs
16K (4K x 4-Bit) High Impedance Outputs
71681
71682
84-49
..-
-.- ... ....-.- ...-- ........
~
_ - - _ ....._..
"----.~
... -.
HIGH-SPEED STATIC RAM
Cache TAG 16K(4K x 4-BIT)
Inresrated Device1echnoIogy. Inc.
ADVANCE
INFORMATION
lOT 6177
FEATURES:
DESCRIPTION:
• High-speed address to Match comparison time
- Military: 15ns
- Commercial: 12ns
• High-speed address access time·
- Military: 15ns
- Commercial: 12ns
• Low-power operation
- IDT61778
- Active: 300mW (typ.)
• Produced with advanced CEMOS ™ high-performance
technology
The IDT6177 is a high-speed cache address comparator subsystem consisting or a 16384-bit static RAM organized as 4K x 4.
Cycle Time and Compare Access Time are equal. The IDT6177
features an on board 4 bit comparator that compares RAM contents
and current input data. The result is an active high on the MATCH
pin. The MATCH pins or severallDT6177's can be wired-ORed together to provide enabling or acknowledging signals to the data
cache or processor thus eliminating logic delays and increasing
system throughput.
The IDT6177 is fabricated using IDT's high-performance, high
reliability technology - CEMOS ™ address to compare and data to
compare access times as fast as 12ns~
All inputs and outputs of the IDT6177 are TTL-compatible
except MATCH, which is open drain. The device operates from a
single 5V supply and fully static asynchronous circuitry is used,
requiring no clocks or refreshing for operation.
The IDT6177 is packaged in either a 22 pin, 300 mil plastic or
ceramic DIP package, and 24 pin SOJ.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
•
•
•
•
Open drain MATCH output
Standard 22 pin plastic or ceramic DIP, 24 pin SOJ
Static operation: no clocks or refresh required
Military product 100% compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
••
•
••
ADDR
DECODE
•
•••
16,384-BIT
MEMORY ARRAY
" •••• ·11
•
,4.,
COLUMN I/O
I'...
I
.......
r
,4
CONTROL
r--
~ COMPARATOR
..
CLEAR
MEMORY
ARRAY
4.,
'"
MATCH
(OPEN DRAIN)
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
eSC-1OS8/-
84':'50
._---------------._--_. _.- ..._--
IDT61n HIGH-SPEED STATIC RAM Cache TAG 16K (4Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Ao
Vee
Ao
Vee
Al
A2
A3
A4
As
All
Al
A 10
A2
A3
All
A 10
Ag
Ag
As
A4
As
NC
ern
A6
A7
1/°4
I/~
"ITE
~
ern
1/°4
1/03
1/0 2
1/01
A6
A7
1/°2
1/01 -
GND
As
NC
"ITE
WE
MATCH
MATCH
GND
DIP
TOP VIEW
TRUTH TABLE
"(5"E
WE
CI:R
DIP
TOP VIEW
MATCH
FUNCTION
H
H
H
Valid
Match Cycle
Write Cycle
L
X
H
Invalid
H
L
H
Invalid
Read Cycle
X
X
L
Invalid
Clear Cycle
X = Don't Care
S4-51
-----_ - - - ..
HI
G
Integrated Dev1ce1edmology.1nc.
CMOS STATIC RAM
16K (4K X 4-BIT)
CACHE-TAG RAM
PRELIMINARY
lOT 6178S
FEATURES:
DESCRIPTION:
• High-speed Address to Match comparison time
- Military: 15ns
- Commercial: 12ns
• High-speed address access time
- Military: 15ns
- Commercial: 12ns
• Low-power operation
-IDT6178S
Active: 300mW (typ.)
• Produced with advanced CEMOS 1M high-performance
technology
• Input and output TTL compatible
• Standard 22 pin plastic or ceramic DIP, 24 pin SOJ
• Static operation: no clocks or refresh required
• Military product 100% compliant to MIL-STD-883, Class B
The IDT6178 is a high-speed cache address comparator subsystem consisting of a 16384-bit static RAM organized as 4K x 4.
Cycle Time and Compare Access Time are equal. The IDT6178
features an onboard 4 bit comparator that compares RAM contents
and current input data. The result is an active high on the MATCH
pin. The MATCH pins of severallDT6178's can be nanded together
to provide enabling or acknowledging signals to the data cache or
processor.
The IDT6178 is fabricated using IDT's high-performance, highreliability technology - CEMOS ThO • Address to compare and Data
to compare access times as fast as 12ns.
All inputs and outputs of the IDT6178 are TTL-compatible and
the device operates from a single 5V supply. Fully static asynchronous circuitry Is used, requiring no clocks or refreshing for
operation.
The IDT6178 is packaged in either a 22 pin, 300mil plastic or
ceramic DIP package, and 24 pin SOJ.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
F'UNCTIONAL BLOCK DIAGRAM
···
·
···
··
ADDR
DECODE
4
,
I
I'-..
II ..... "
COLUMN 1/0
I
,4
r
~
CONTROL
Y-..
16.384-BIT
MEMORY ARRAY
CLEAR
MEMORY
ARRAY
4...
COMPARATOR
MATCH
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-1030/1
S4-52
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6178S CMOS STATIC RAM 16K (4Kx 4-81T) CACHE-TAG RAM
PIN CONFIGURATIONS
Vee
All
Ao
Al
A2
A3
A4
As
Ae
A7
Ao
A1
A2
A3
A4
As
NC
As
A7
Al0
Ag
As
ern
1/04
1/03
1/02
C5E"
WF:.
Al0
Ag
As
NC
CUi",
1/04
1/03
1/02
DE"
1/01
GND
Vce
All
VIr=.
MATCH
DIP
TOP VIEW
[I
1/01
MATCH
GND
SOJ
TOP VIEW
PIN NAMES
Ao- All
Address
~
Write Enable
1/01-1/04
Data Input/Output
C5E"
Output Enable
MATCH
Match
ern
Power
Vee
Power
GND
Ground
TRUTH TABLE
WE
DE
ern
MATCH
H
H
H
Valid
Match Cycle
MODE
L
X
H
Invalid
Write Cycle
H
L
H
Invalid
Read Cycle
X
X
L
Invalid
Clear Cycle
X = DON'T CARE
AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Output Load for Match Cycle
GND to 3.0V
5ns
1.5V
1.5V
See Figures 2 & 3
See Figure 1
5V
MATCH OUT
~
85n
5V
16on
1/0 OUT
30pF*
Figure 1
~
2550
5V
48on
1/0 OUT
3OpF'
Figure 2
~
255fi
48on
5pF*
Figure 3
(for tOLZ' t OHZ ' t WHZ ' tow)
* Including scope and jig
54-53
- - _..
__. _ - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT6178S CMOS STATIC RAM 16K (4Kx 4-BIT) CACHE-TAG RAM
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage with
Respect to GND
VTERM
RECOMMENDED DC OPERATING CONDITIONS
(1)
VALUE
UNIT
':'0.5 to +7.0
V
. RATING
SYMBOL
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
'0
V
SYMBOL
UNIT
TA
Operating Temperature
-55 to + 125
°C
TalAs
Temperature Under Bias
-65 to +135
°C
V1H
Input High Voltage
2.2
-
6.0
V
°C
V1L
Input Low Voltage
-0.&1)
-
O.S
V
Storage Temperature
TSTG
Pr
-65 to + 150
Power Dissipation
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
W
1.0
DC Output Current
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indipated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
'Iu'
II
Lo
VOL
ICC2
5.0V ± 10%
2.4
= SmA (1/0 1 -
1104 )
IOL = 10mA (1/0c 1/0 4 )
Output Low Voltage
Output High Voltage
IOH
PARAMETER
Operating Power Supply Current
Outputs Open Vcc = Max., f = 0
= fMAX
MAX.
IOT6178S15
MAX.
110
110
J.lA
10
J.lA
0.4
V
0.5
V
0.4
V
0.5
V
-
V
IOT6178S20
MAX.
V
UNIT
110
COM'L.
90
90
90
MIL.
1S0
160
160
COM'L.
160
140
140
S4-54
UNIT
10
(Vee = 5.0V ±10%)
IOT617SS12
MAX.
MIL.
Vee
IOT617SS
MIN.
= -12mA (Match)
IOL
Dynamic Operating Current
Outputs Open Vcc = Max., f
OV
2.4
<:5E' = '-"H' VOUT = OV to Vee
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
ICCl
O°Cto +70°C
IOH = -4mA (1/0 1 - 110 4 )
Output Leakage Current
IOL
SYMBOL
5.0V ± 10%
= 24mA (Match)
= 30mA (Match)
Vcc = 5.5V, V1N = OV to Vec
10L
VOH
OV
-
Input Leakage Current
'
GNO
-55°C to + 125°C
(Vcc = 5.0V ±10%)
TEST CONDITIONS
PARAMETER
AMBIENT
TEMPERATURE
mA
--
- - _ ..__
..
_---
.. _ .....
_._-_
..
----_.. _...- - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6178S CMOS STATIC RAM 16K (4Kx 4-BIT) CACHE-TAG RAM
AC ELECTRICAL CHARACTERISTICS 0Icc =
PARAMETER
SYMBOL
5.0V ±10%, All Temperature Ranges)
IDT6178S12 (1)
MIN.
MAX.
IDT6178S15
MAX.
MIN.
IDT6178S20
MIN.
MAX.
UNIT
MATCH CYCLE
tADM
Address to Match Valid
-
12
-
20
Data Input to Match Valid
-
11
-
15
tDAM
13
-
15
ns
t MHO
Match Valid Hold From 01:
0
-
0
-
0
-
ns
ns
tOEM
OE" High to Match Valid
-
12
-
15
-
.20
ns
tMHw
Match Valid Hold From ~
0
-
0
-
0
-
ns
tWEM
~ High to Match Valid
-
12
-
15
-
20
ns
t MHCLR
Match Valid Hold From
0
-
0
-
0
-
ns
ern
tMHA
Match Valid Hold From Address
3
-
3
-
3
tMHD
Match Valid Hold From Data
3
-
3
-
3
NOTE:
1. O°Cto +70°Ctemperature range only.
TIMING WAVEFORM OF MATCH CYCLE
ADDRESS
1/01-4
VALID READ DATAoUT
MATCH
MATCH VALID'
MATCH
NO MATCH
S4-55
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6178S CMOS STATIC RAM 16K (4K x 4-BIT) CACHE-TAG RAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vcc = 5.0V ±10%. All Temperature Ranges)
IDT6178S12 (3)
MAX.
MIN.
IDT6178S15
MIN.
MAX.
IDT6178S20
MIN.
MAX.
UNIT
READ CYCLE
tRc
Read Cycle Time
12
-
15
-
20
-
ns
tAA
Address Access Time
-
12
15
ns
Output Enable Access Time
-
8
-
20
tOE
-
15
ns
tOH
Output Hold From Address Change
3
3
-
ns
Output Low Z Tlme(1, 2)
2
2
-
3
tOLZ
-
2
-
ns
tOHZ
Output High Z Tlme(l, 2)
-
7
-
9
-
12
ns
10 .
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with load (Figures 1 & 2).
2. This parameter Is guaranteed but not tested.
3. 0 - 70°C only.
TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
t Rc
ADDRESS
I:
DATAoUT
tAA
tOH
~xxJ
S4-56
tOH
t
IDT6178S CMOS STATIC RAM 16K (4Kx 4-BIT) CACHE-TAG RAM
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vcc = 5.0V ±10%, All Temperature Ranges)
IOT6178S 12 (3)
MAX.
MIN.
IOT6178S15
MIN.
MAX.
IOT6178S20
MIN.
MAX.
UNIT
WRITE CYCLE
twc
Write Cycle Time
12
-
15
-
20
-
ns
tAW
Address Valid to End of Write
10
12
-
14
ns
0
-
-
14
-
ns
0
-
ns
-
12
-
ns
0
-
ns
t As
Address Set-up Time
0
-
twp
Write Pulse Width
10
-
12
tWR
Write Recovery Time
0
-
0
10
0
ns
tDW
Data Valid to End of Write
8
tDH
Data Hold Time
0
tWHZ
Write Enable to Output in High Z(1. 2)
-
6
-
7
-
9
ns
tow
Output Active From End of Write (1. 2)
0
-
0
-
0
-
ns
0
NOTES:
1. Transition is measured ±200mV from low or high impedance with load (Figures 1 & 2).
2. This parameter guaranteed but not tested.
3. O°C to + 70°C temperature range only.
TIMING WAVEFORM OF WRITE CYCLE
(1,3)
twc
ADDRESS
DATA OUT
NOTES:
wr:.
1.
must be high during all address transitions.
2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
3. 'O'E' is continuously high or low. If ~ is low during a WE controlled write cycle, the write pulse width must be the greater of twpor (tWHZ+ t DW ) to
allow the I/O drivers to turn off and data to be placed on the bus for the required t DW ' If OE' is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp .
4. Transition is measured ±200mV from steady state.
S4-57
~~--
.., - - - - - - - - - - - ' - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6178S CMOS STATIC RAM 16K (4Kx 4-BIT) CACHE-TAG RAM
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ±10%, All Temperature Ranges)
I
PARAMETER
SYMBOLI
CLEAR CYCLE
t ClPW
t ClRC
I
I
ern Pulse Width (2)
I
ern High to WE Low
I
IDT6178S12 (1)
I
MAX.
MIN.
25
-
,5
-
IDT6178S15 . I
IDT6178S20
I
MIN.
MIN.
MAX.
MAX.
I
30
r
5
-
I
I
-
40
5
UNIT
I
I
NOTES:
1. O°C to + 70°C temperature range only.
2. Recommended duty cycle of 10% maximum.
TIMING WAVEFORM OF CLEAR CYCLE
tCLPW---~
xxxxxxxxxxxxxy~-----tc_~c==t~
ORDERING INFORMATION
S
999
A
A
Power
Speed
Package
Process!
Temperature
y:~nk
P
1.---------1 C
Y
12
--1 15
20
1 . -_ _ _ _ _ _ _ _ _ _
1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _--/ S
1 . -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - /
S4-58
6178
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP'
Small Outline (J bend)
Speed in Nanoseconds
Standard Power
16K (4K x 4-Bit)
Cache~Tag
RAM
ns
ns
IntesratedDevice~lnc.
CMOS STATIC RAM
WITH OUTPUT ENABLE
16K (4K x 4-BIT)
PRELIMINARY
IDT61970S
IDT61970L
techology, combined with innovative circuit design techniques,
provide a cost effective approach for memory intenSive
applications.
The IDT61970 features two memory control functions: chip
select (CS) and output enable (OE). These two functions greatly
~nhance the IDT61970's overall flexibility in high-speed memory
applications. This feature makes the IDT61970 ideal for use in
cache memory applications.
.
Access times as fast as 12ns are available, with typical power
consumption of only 300mW. The IDT61970 offers a reduced
power standby mode, I S81, which enables the designer to considerably reduce device power requirements. This capibility
significantly decreases system power and cooling levels, while
greatly enhancing system reliability. The low power (L) version
also offers a battery backup data retention capibility where the
circuit typically consumes only 10jJW when opperating from a 2
volt battery.
All inputs and outputs are TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along with
matching access and cycle times, favor the simplified system
design approach.
The IDT61970 is packaged in either a space saving 22-pin,
300-mil ceramic or plastic DIP, or a 24-pin SOJ, providing high
board level packing densities.
Military grade product is manufactured in compliance with the
latest reviSion of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliabilty.
FEATURES:
• High Speed (equal access and cycle times)
- Military 20/25/35/45/55
- Commercial 12/15/20/25/35/45
• Low power consumption
- IDT61970S
Active: 300mW (typ)
Standby: 100,.JW (typ)
- IDT61970L
Active: 300mW (typ)
Standby: 10jJW (typ)
• Battery backup operation - 2V data retention (IDT61970L
only)
• Available in 22-pin ceramic or plastic DIP and 24-pin SOJ
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Produced with advanced CEMOS ™high-performance
technology
• Separate Output Enable control
• Military product compliant to MIL-STD-883
DESCRIPTION:
The IDT61970 is a 16,384-bit high speed static RAM organized
as 4096 x 4 bits. It is fabricated using IDT's high-performance,
high-reliability technology-CEMOS™. This state-of-the-art
FUNCTIONAL BLOCK DIAGRAM
16K-BIT
MEMORY
ARRAY
_t t .t
j
r---
~~
INPUT/
OUTPUT
~f:S[
-tfl
~K
r
I"
CONTROL
LOGIC
~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-1058/-
84-59
. .----------.-.-.-.- .. , - - - - .
-~~-
--------_._------------- ._---
91
..
IDT61970S/L CMOS STATIC RAM
WITH OUTPUT ENABLE 16K (4K x 4)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC DIAGRAM
Ao
A'l
A2
A3
A4
A5
Vee
All
A 10
Ag
Aa
NC
As
A7
1/03
1/04
CS
1/0 2
1/01
~
wr=.
GND
1/01
Ao
Al
A2
A3
A4
A5
As
A7
Aa
Ag
A10
All
CS
DIP
TOP VIEW
1/0z
1/0:3
1/04
~
wr=.
PIN NAMES
Ao- A11
Address
wr=.
Write Enable
1/01 - 1/04
Vee
GND
Data Input/Output
~
Output Enable
Power
CS
Chip Select
Ground
NC
No Connection
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
(1)
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to + 125
°C
TBIAS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
W
DC Output Current
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
Ilu l
liLa I
PARAMETER
Input Leakage Current
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
IDT61970S
MIN.
MAX.
TEST CONDITIONS
IDT61970L
MIN.
MAX.
UNIT
10
-
5
COM·L.
-
2
-
2
Vee Max.
MIL.
-
10
-
5
CS = VIH • Vee = GND to Vee
COM'L.
-
2
-
2
0.5
0.5
0.4
-
0.4
V
2.4
-
2.4
-
V
Vee = Max.; VIN = GND to Vee
MIL.
IOL = 10mA Vee = Min.
IOL= 8mA \Ce = Min.
IOH = -4mA, Vee = Min.
S4-60
J.lA
J.lA
V
----------
... ---~
...
IDT61970S/L CMOS STATIC RAM
WITH OUTPUT ENABLE 16K (4K x 4)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (1)
VCC = 5.0V ±10%, VLC = 0.2V, VHC = VCC -0.2V
61970SA12
SYMBOL
61970SA15
POWER
PARAMETER
61970SA20
61970LA20
61970SA25 61970SA35/45(4) 61970SA55
61970LA25 61970LA35/45(4) 61970LA55
COM'L MIL COM'L MIL COM'LMIL COM'L MIL COM'L
ICC1
ICC2
ISB
ISB1
Operating Power
Supply Current
CS = VIL,
Outputs Open
Vcc = Max.,
f = 0(3)
SA
110
-
110
120
90
100
90
90
100
MIL
UNIT
COM'L MIL
-
100
100
mA
Dynamic
Operating Current
CS = Vlu
Outputs Open,
Vee = Max.,
f = fMAX(3)
LA
-
-
-
-
70
80
70
80
70
80
-
SO
SA
165
-
145
165
120
120
110
120
100
110
-
110
LA
-
-
-
-
100
110
90
100
SO
90/80
-
SO
SA
65
-
55
60
45
45
35
45
30
35
-
35
mA
Standby Power
Supply Current
(TIL Level)
CS ~VIH,
Vec = Max.,
Outputs Open,
f = f MAX(3)
mA
Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHC ,
Vcc= Max.,
LA
-
-
-
-
30
35
25
30
20
25
-
20
SA
20
-
20
30
20
20
2
10
2
10
-
10
LA
-
-
-
-
0.5
5
0.05
0.3
0.05·
0.3
-
0.3
mA
VIN ~ VHC or
(3)
VIN S VLC ' f = 0
NOTES:
1. All values are maximum guaranteed values.
2. Also available S5 and 100ns military devices.
3. f = fMAX (All inputs except Chip Select cycling at f =
4. -55°C to + 125°C temperature rang~ only.
1/~d.
f = 0 means no address or control lines change.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
UNIT
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
V
-0.5(1)
-
6.0
Input Low Voltage
O.S
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
12ns
15n5
20/25ns
35/45ns
55ns
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN, MAX. UNIT
READ CYCLE
t RC
Read Cycle Time
12
-
15
-
20/25
-
~5/45
-
55
-
ns
tAA
Address Access Time
-
12
15
-
20/25
35/45
-
55
ns
ns
tOE
Output Enable Access Time
-
S
-
15
-
15
-
20
tOLZ
Output Low Z Time(1. 2)
2
-
2
-
2
-
2
-
2
-
ns
tOHZ
Output High Z Time(1, 2)
-
7
-
9
-
12
-
15
-
15
ns
tOH
Output Hold from Address Change
3
-
3
-
3
-
3
-
3
-
ns
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with load.
2. This parameter is guaranteed, but not tested.
S4-61
- - - _...
_._ _-_..... - - - - - ..
10
IDT61970S/L CMOS STATIC RAM
WITH OUTPUT ENABLE 16K (4K x 4)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NUMBER 1
ADDRESS
~:
__=-~t_AA-=-__
tR_C-=._-_------l-t~---
DATA OUT
TIMING WAVEFORM OF READ CYCLE NUMBER 2
1. .__
.. - - - - - - - -
tRC ---------.t
ADDRESS
1~•.-------tAA------~
~r----tOH------~
DATA OUT
S4-62
IDT61970S/L CMOS STATIC RAM
WITH OUTPUT ENABLE 16K (4Kx 4)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
12n5
15n5
20/25ns
35/45ns
55ns
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
PARAMETER
SYMBOL
UNIT
WRITE CYCLE
20/25
-
35/45
14/20
30/40
0
-
-
0
-
0
14/20
-
30/40
-
50
0
0
17/20
-
20
3
-
3
-
t AS
Address Set-Up Time
0
-
twp
Write Pulse Width
10
-
12
tWR
Write Recovery Time
'0
tow
Data Valid to End of Write
8
-
9.
tOH
Data Hold Time
0
-
0
-
tWHZ
Write Enable to Output in High
-
6
-
7
-
9
-
13/20
-
25
ns
tow
Output Active from End of Write (1. 2)
0
-
0
-
0
-
0
-
0
-
ns
twc
Write Cycle Time
12
tAw
Address Valid to End of Write
10
Z(1. 2)
15
12
0
0
10/13
55
-
ns
50
-
ns
ns
3
-
0
ns
ns
ns
ns
NOTES:
1. Transition is measured ±200mV from low or high impedance voltage with load.
2. This parameter is guaranteed, but not tested.
TIMING WAVEFORM OF WRITE CYCLE
II~.~-------------twc------------~·~I
.
ADDRESS
---~----------~--tAW
I'-t~~
~+---"'---~ ~: I~
DATA OUT
DATA
IN
I
I
I~tow =-1I
tWR
':
I ~~
tOH
tow~
--------------------------------------KI<::-VA-L-I-D-D-A-TA~~~~~~~~
I
NOTES:
1. WE must be high during all address transitions.
2. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the inputs must not be applied.
3. '01:" is continuously high or low. If '01:" is low during a WE controlled write cycle, the write pulse width must be the greater of Wp or (tWHZ + tow) to
allow the I/O drivers to turn off and data to be placed on the bus for the required tow .If DE: is high during a ~ controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified t wP '
4. Transition is measured + /-200mV from steady state.
54-63
IDT61970S/L CMOS STATIC RAM
WITH OUTPUT ENABLE 16K (4K x 4)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
xxxxx
999
Speed
Device Type
A
Process!
T.m~~:'~k
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
MIL-STD-883. Class B
'"-______---1,IP
~
L..----------------I
~
____________________________
12
15
20
25
35
45
55
~IS
IL
L..-----------------------i~
S4-64
61970
Plastic DIP
Sidebraze DIP
Small Outline (J bend)
Commercial Only }
Speed in Nanoseconds
Military Only
Standard Power
Low Power
16K (4K x 4-Bit) CMOS Static RAM
HIGH-SPEED STATIC RAM
Cache TAG 16K(4K x 4-BIT)
Intesrated Device~lnc.
ADVANCE
INFORMATION
lOT 7177
FEATURES:
DESCRIPTION:
• High-speed address to Match comparison time
The 1017177 is a high-speed cache address comparator subsystem consisting of a 16384-bit static RAM organized as 4K x 4.
Cycle Time and Compare Access Time are equal. The 1017177
features an onboard 4-bit comparator that compares RAM
contents and current input data. The result is an active high on the
MATCH pin. The MATCH pins of several 1017177's can be
wiretl-ORed together to provide enabling or acknowledging
signals to the data cache or processor, thus eliminating logic
delays and increasing system throughput. The 7177's CE can be
used to accommodate deeper than 4K cache systems.
The 1017177 is fabricated using lOT's high-performance, highreliability technology - CEMOS TM. Address to compare and data to
compare access times as fast as 12ns.
All inputs and outputs of the 1017177 are TTL-compatible
except MATCH, which is open drain. The 7177 features an extra
GNO. pin which significantly reduces noise. The device operates
from a single 5V supply and Fully static asynchronous circuitry is
used, requiring no clocks or refreshing for operation.
The 1017177 is packaged in either a 24 pin, 300 mil plastic or
ceramic OIP package, and 24 pin SOJ.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
-
Military: 15ns
- Commercial: 12ns
• High-speed address access time
- Military: 15ns
- Commercial: 12ns
• Low-power operation
- IDT7177S
- Active: 300mW (typ.)
• Produced with advanced CEMOS ™ high-performance
technology
•
•
•
•
•
•
Open drain MATCH output
CE for depth expansion
Two ground pins to reduce noise
Standard 24 pin plastiC or ceramic DIP, 24 pin SOJ
Static operation: no clocks or refresh required
Military product 100% compliant to MIL-STO-883, Class B
FUNCTIONAL BLOCK DIAGRAM
••
•••
ADDR
DECODE
•••
•
16.384-BIT
MEMORY ARRAY
II •••• ·11
1/01-1/04
•
I
r
,4
.
...
"-4
COLUMN 110
.......
,4.,
CONTROL i " -
CLEAR
MEMORY
ARRAY
,4L
COMPARATOR
MATCH
(OPEN DRAIN)
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-1061/-
S4-65
I 0T7177 HIGH-SPEED STATIC RAM Cache TAG 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
AD
Vee
Vee
Al
All
All
A2
A3
A4
A5
A6
A7
AID
AID
Ag
Ag
As
As
~
~
ern
ern
1/04
1/03
1/02
1/°4
1/°3
1/0 2
1/01
MATCH
GND
1/°1
CE"
MATCH
GND
GND
DIP
TOP VIEW
DIP
TOP VIEW
TRUTH TABLE
CE
'WE
OE
ern
L
H
H
H
Valid
Match Cycle
L
L
X
H
Invalid
Write Cycle
MATCH
FUNCTION
L
H
L
H
Invalid
Read Cycle
L
X
L
Invalid
Clear Cycle
H
X
X
X
X
Invalid
HighZ
X = Don't Care
84-66
(;)
Integrated Dev1ce1edmology.1nc.
ADVANCE
INFORMATION
lOT 7178
HIGH-SPEED
STATIC RAM Cache TAG
16K(4K x 4-BIT)
FEATURES:
DESCRIPTION:
• High-speed address to Match comparison time
- Military: 15ns
The IDT7178 is a high-speed cache address comparator subsystem consisting of a 16384-bit static RAM organized as 4K x 4.
Cycle Time and Compare Access Time are equal. The IDT7178
features an onboard 4 bit comparator that compares RAM contents
and current input data. The result is an active high on the MATCH
pin. The MATCH pins of several IDT7178's can be NANDed together to provide enabling or 8tknowledging signals to the data
cache or processor. The 7178's CE can be used to accommodate
deeper than 4K cache systems.
The IDT7178 is fabricated using IDT's high-performance, highreliability technology-CEMOS TM. Address to compare and data
to compare access times as fast as 12ns.
All inputs and outputs of the IDT7178 are TTL-compatible. The
IDT7178 features an extra Gnd. pin which significantly reduces
noise. The device operates from a single 5V supply and Fully static
asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT7178 is packaged in either a 24 pin, 300 mil plastic or
ceramic DIP package, and 24 pin SOJ.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class S, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
- Commercial: 12ns
• High-speed address access time
- Military: 15ns
- Commercial: 12ns
• Low-power operation
-IDT7178S
- Active: 300mW (typ.)
• Produced with advanced CEMOS ™ high-performance
technology
• Inputs/Outputs TTL compatible
• CE for depth expansion
• Two ground pins to reduce noise
• Standard 24 pin plastic or ceramic DIP, 24 pin SOJ
• Static operation: no clocks or refresh required
• Military product 100% compliant to MIL-STD-883, Class S
FUNCTIONAL BLOCK DIAGRAM
Ao
Al
•••
•
•
•••
•
ADDR
DECODE
•
16,384-BIT
MEMORY
ARRAY
I I • • •
,4
1
COLUMN I/O
.........
I
,...,
4
,,-
..
..
··1
r
CLEAR
MEMORY
ARRAY
CONTROL
,
~
4",
,
COMPARATOR
MATCH
CEM08 is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
1969 Integrated Device Technology, Inc.
DSC-l062/-
84-67
._---- ._--_._
..
__.
_ ..
__ __ _----- ... __ ._-_.. _ - - .
..
IDT7178 HIGH-SPEED STATIC RAM Cache TAG 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Ao
Vee
Ao
Vee
Al
A2
A3
A4
A5
Ae
A7
All
AlO
Al
A2
A3
A4
A5
NC
All
A 10
Ag
Ae
A7
1104
DE
1102
1101
Ag
As
~
1/04
1/°3
1/° 2
1/°1
~
~
CE
~
1/03
~
MATCH
GND
GND
As
NC
GND
MATCH
DIP
TOP VIEW
DIP
TOP VIEW
TRUTH TABLE
CE
WI:
OE
'CI:'R
L
H
H
H
Valid
Match Cycle
L
L
X
H
Invalid
Write Cycle
Read Cycle
MATCH
FUNCTION
L
H
L
H
Invalid
L
X
X
L
Invalid
Clear Cycle
H
X
X
X
Invalid
HighZ
X = Don't Care
S4-68
Integrated DeviceTechnology. Inc.
CMOS STATIC RAM
64K (16K x 4-BIT)
lOT 6198S
lOT 6198L
ity technology-CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective approach for memory intensive applications. Timing parameters have been specified to meet the speed demands of the
fastest 10T79R3000 RISC processors.
The IOT6198 features two memory control functions: chip select
(CS) and output enable (OE). These two functions greatly enhance the IOT6198's overall flexibility in high-speed memory
applications.
Access times as fast as 15ns are available, with typical power
consumption of only 300mW. The IOT6198 offers a reduced power
standby mode, 18B1, which enables the designer to considerably
reduce device power requirements. This capability significantly
decreases system power and cooling levels, while greatly enhancing system reliability. The low-power version (L) also offers a battery backup data retention capability where the circuit typically
consumes only 30~W when operating from a 2 volt battery.
All inputs and outputs are a TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along with
matching access and cycle times, favor the simplified system design approach.
The IOT6198 is packaged in either a 24-pin THINOIP, 24-pin
plastic DIP, 28-pin lead less chip carrier or 24-pingull-wing or
J-bend small outline IC, providing improved board-level packing
densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FEATURES:
• Optimized for fast RISC processors including the 10T79R3000
• Output Enable (OE) pin available for added system flexibility
• High-speed (equal access and cycle times)
- Military: 20/25/30/35/45/55/70/85ns (max.)
- Commercial: 15/19/20/25/30/35/45ns (max.)
• Low-power consumption
- IOT6198S
Active: 350mW (typ.)
Standby: 100~W (typ.)
-IOT6198L
Active: 300mW (typ.)
Standby: 30~W (typ.)
• JEOEC compatible pinout
• Battery back-up operation-2V data retention (L version only)
• 24-pin THINOIP, 24-pin plastic DIP, high-density 28-pin
leadless chip carrier and 24-pin SOIC (gull-wing and J-bend)
• Produced with advanced CEMOS Thl technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STO-883, Class B
DESCRIPTION:
The IOT6198 is a 65,536-bit high-speed static RAM organized as
16K x 4.lt is fabricated using lOT's high-performance, high-reliabil-
FUNCTIONAL BLOCK DIAGRAM
Ao
DECODE
65,536 BIT
MEMORY ARRAY
COLUMN I/O
CEMOS is a trademark of Integrated Device Technology, Inc.
I MILITARY
AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
DSC-1010/1
S4-69
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JDT6198S/IDT6198L CMOS STATIC RAM 64K (16K x 4-BIT)
PIN CONFIGURATIONS
Ao
Al
A2
A3
A4
Vcc
A13
A5
As
NC
1104
INDEX
U LJ ;; U L..
32U2627
A12
All
A 10
As
A7
As
110:3
~
t5E'
11°1
we.
GND
4
26 [:
NC
5
25 [:
A13
A3
:J
:J
24
C
A12
A4
]
s
7
23 [:
A5
As
:J
:J
22 [:
All
A 10
21 [:
As
A7
As
liD.!
1
]
Al
A2
CS"
]
:J
:J
s
L28-2
s
10
11
12
20[:
1/04
lS [:
16 [:
110:3
liD.!
13 14 15 lS 17
nnnnn
DIP/SOIC
TOP VIEW
~~~~g
LCC
TOP VIEW
LOGIC SYMBOL
A3
A4
A5
AS
A7
As
As
A 10
All
A12
A 13
lID.!
"0:3
~
VTERM
we.
Write Enable
t5E'
Output Enable
1/01-4
Data Input/Output
Vec
GND
Power
Ground
-0.5 to +7.0
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
Oto +70
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
-55 to +125
MIN.
TYP.
MAX.
UNIT
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
6.0
V
V1L
Input Low Voltage
-:-0.5(1)
-
0.8
V
SYMBOL
-0.5 to + 7.0 . V
Operating
Temperature
TA
Address Inputs
Chip Select
we.
ABSOLUTE MAXIMUM RATINGS
RATING
Terminal Voltage
with Respect to
GND
AO- 13
CS
1/°4
cs
SYMBOL
PIN NAMES
1/°1
Ao
Al
A2
°C
PARAMETER
NOTE:
1. V1L min. = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.
GRADE
Military
Commercial
S4-70
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6198S/IDT6198L CMOS STATIC RAM 64K (16K x 4-BI1)
DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL
\lui
TEST CONDITIONS
PARAMETER
Vec = Max., VIN
Input Leakage Current
IlLOI
Output Leakage Current
VOL
Output Low Voltage
= GND to Vcc
= Max.
CS" = VIH ' VOUT = GND to Vee
10L = 10mA, Vec = Min.
10L = 8mA, Vec = Min.
10H = -4mA, Vec = Min.
MIN.
MIN.
IDT6198L
TVP.(t) MAX.
UNIT
MIL.
-
-
10
-
-
5
).LA
COM'L.
-
-
5
).LA
5
-
5
-
-
2
10
-
2
).LA
).LA
MIL.
Vee
IDT6198S
TVP.(t) MAX.
COM'L.
VOH
Output High Voltage
NOTE:
1. Typical limits are at Vec = 5.0V, +25°C ambient.
-
0.5
-
V
-
0.4
-
-
0.5
-
0.4
V
2.4
-
-
2.4
-
-
V
DC ELECTRICAL CHARACTERISTICS(t)
Vee = 5.0V ±10%, V LC
SYMBOL
= 0.2V, VHC = Vee -0.2V
PARAMETER
POWER
Operating Power
~PIY Current
lecl
ICC2
IS8
IS81
C = VIL.
Outputs Open.
Vee = Max.• f = 0(3)
Dynamic~erating
CUrrent. S = VIL.
Outputs Open.
Vec = Max.•
f = f MAX (3)
Standby Power
Supply Current
(TTL Level)
CS"~ VIH •
Vec = Max.,
Outputs Open f = f MAX(3)
Full Standby Power
Supply Current
(CMOS Level)
CS~ VHC '
Vcc = Max.•
VIN ~ VHCor
VIN $ VLe • f = 0(3)
6198525
6198519/20(2
6198L25
6198515
COM'L. MIL. COM'L. MIL. COM'L. MIL.
S
135
,:':':\Ii""
L
-
S
180':'" .::.::.j;:
"';':,:.;:::::
L
-
S
~~::;:.::...:'.::...:~
:::::::'::::5::"::
6198530/35
6198L30/35
COM'L. MIL
6198545/55 (4)
6198L45/55(4)
COM'L MIL
6198570/85
6198L70/85
UNIT
COM'L MIL
120
140
100
125
100
110
100
110
-
110
-
-
85
110
85
95
85
95
-
95
155
175
135
155
125
140
.125
140
-
140
-
-
125
145
100
110
-
1101105
60
70
55
60
50/45
55/50
45
50
-
50
-
-
45
50
40/35
45/40
30
35
-
35
20
25
15
20
15
20
15
20
-
20
mA
......:.::::.;..
mA
::::::.....
115/105125/115
......
.....:::::::::::;::::;:;:
L
:::;::::::;:::/:i-
,~t:!i -
S
L
.t:::,ji:;·;;.:::::: -
mA
mA
-
-
0.5
1.5
0.5
1.5
0.5
1.5
-
1.5
NOTE5:
1. All values are maximum guaranteed values.
2. Preliminary data for Military devices only.
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC ' f = 0 means no input lines change.
4. -55°C to + 125°C temperature range only.
54-71
- - - - _....... _--_._.--_._.
__
....
----.
- .... _-----_ ....... -._.
__. _ - - - - - - - - -
IDT6198S/IDT6198L CMOS STATIC RAM 64K (16Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLc
= 0.2V, VHc = Vcc
SYMBOL
VOR
- 0.2V
PARAMETER
TEST CONDITION
-
Vcc for Data Retention
!ceoR
t CDR (3)
Chip Deselect to Data Retention Time
t R (3)
Operation Recovery Time
Ilu l
Input Leakage Current
(3)
I
MIL
Data Retention Current
CS ;::VHC
\'IN ;:: VHC or:5 VLC
TYP.(1)
Vcc @
2.0V
3.0V
MIN.
COM'L.
2.0
-
-
-
-
-
10
15
600
900
-
10
15
150
225
-
0
t RC (2)
-
. NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
DATAoLrr
~
2550
Figure
5V
4800
DATAOLrr
30pF*
~
2550
1. Output Load
4800
5pF*
Figure 2. Output Load
(for toLZ,t CLZ ' tOHz,
t wHz , t CHZ ' tow)
* Including scope and jig.
S4-72
MAX.
Vcc @
2.0V
3.0V
UNIT
V
J.lA
-
ns
2
J.lA
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6198S/IDT6198L CMOS STATIC RAM 64K (16K X 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBO
PARAMETER
(Vcc = 5.0V ±10%, All Temperature Ranges)
6198S15(1)
MIN. MAX.
6198S19/20
MIN. MAX.
6198S25
6198L25
MIN. MAX.
6198S30/35
6198L30/35
MIN. MAX.
6198S45/55 (2) 6198S70(2)/85(2)
6198L45/55 (2) 6198L70 (2~85 (2) UNIT
MIN.
MAX. MIN.
MAX.
t Rc
Read Cycle Time
15
~}t':~::.
20
-
25
-
30/35
-
45/55
-
70/85
-
ns
tAA
Address Access Time
r(:1?::
-
19/20
-
25
-
45/55
-
70/85
ns
Chip Select Access Time
::::::{:1~
-
20
-
25
-
29/35
t Acs
-
30/35
-
45/55
-
70/85
ns
tCLZ
Chip Select to Output in Low Z(3)
5
:::::=;::t:i
5
-
5
-
5
-
5
-
5
-
ns
ns
tOE
Output Enable to Output Valid
-
;:;;;;;;;;:;;;)~
-
9
-
11
-
15/18
-
25/35
-
45/55
tOLZ
Output Enable to Output in Low Z(3)
5'::::\':::::::;:-
5
-
5
-
5
-
5
-
5
-
ns
tCHz
Chip Select to Output in High Z(3)
-;:;:;:::;:::::::/7
2
8
2
10
2
12/14
15/20
-
25/30
ns
tOHZ
Output Disable to Output in High Z(3)
-::;:::;:;;:;iJ
7
2
8
2
9
2
12/15
-
15/20
-
25/30
ns
tOH
Output Hold from Address Change
s::=dt/i -
5
2
0
0
0
0
0
-
ns
-
-
5
g;::t::::::;;
-
5
Chip Select to Power Up Time(3)
-
5
tpu
-
t pD
Chip Deselect to Power Down Time (3)
15
-
20
-
25
-
30/35
-
45/55
-
70/85
ns
.:Ply
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
S4-73
--------_
..
_-_ _--_ _._-_
..
..
.. _.....
ID.T6198SfiDT6198L CMOS STATIC RAM 64K (16K x 4-BIT)
TIMING WAVEFORM OF READ CYCLE NO.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1(1)
~----------------....
ADDRESS
~
..
tRC
------------------~
.....
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...;._--'
""-~-----------
tAA
---------..1.. '
14-----
14------ t
ACS
tOE
----i----t
/ O f - - - - tCLZ (5) -------!~
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
~----- t ACS -----~
DATA OUT
,
ICC -
-
-
-
-
-
-
1
-t: -1':r-------------------
Vce SUPPLY"
CURRENT ISB _ _ _ _ _ _ _--'
NOTES:
1. WE Is High for Read Cycle~
2. Device' is continuously selected, ~ = V11,.
3. Address valid prior to or coincident with ~ transition low.
4. ~ = V1L
5. Transition is, measured ±200mV from steady state.
\
S4-74
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6198S/IDT6198L CMOS STATIC RAM 64K (16K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
-
(Vcc;" 5 o.V +10.%. All Temperature Ranges)
6198525
6198S15(1) 6198519/20(4 6198L25
MIN. MAX. MIN. MAX. MIN. MAX.
PARAMETER
twc
Write Cycle Time
14
::::::::-.
17
tcw
Chip Select to End of Write
14
:(}«:.:
17
tAW
Address Valid to End of Write
14
t AS
Address Set-up Time
o ::::::\t~
0
twp
Write Pulse Width
Write Recovery Time
14::::::::::t:::Q·::,,;\:::t -
17
tWR
0
tWHZ
Write Enable to Output in High Z (3)
tDw
Data Valid to End of Write
tDH
Data Hold Time
}:q':;:'::
tow
Output Active from End of Write (3)
's
:;:;;::::7
::::
•...•.:..
:~{:{:
~.
17
-
6198530/35
6198L30/35
MIN. MAX.
-
6198S45/55 (2)
6198L45/55 (2)
MIN.
MAX.
-
20
-
22/30
20
22/25
20
-
0.
-
0
-
20
-
35/50
-
0
-
22/25
-
0
-
0.
-
22/25
40/50
35/50
35/50
0
6198S70(2)/85(2)
6198L70(2~85(2)
MIN.
UNIT
MAX.
60/75
-
ns
60/75
-
ns
60/75
ns
60/75
-
0
-
ns
0
ns
ns
5
-
6
-
7
-
10.
-
15/25
-
30/40
ns
-
10
-
13
-
13/15
-
20/25
30/35
0.
-
0
-
0
0.
-
ns
5
-
5
-
5
-
ns
0.
5
5
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Preliminary data only for military devices.
S4-75
--_._---,.. -------_.,.....__ .._.. _-_.__ ._--..._ - - - - - - - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6198S/IDT6198L CMOS STATIC RAM 64K (16Kx 4-81T)
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1,2,3,7)
ADDRESS
14-----------tAW -,----------I-.t
---+-""
twp (7)
.....--_toW(B)_-~
DATA OUT
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)(1,2,3,5,8)
twc
ADDRESS
~
----./
K
)K
tAW
I - - - t AS
~
I
/~
t
cW
(7)
tWR
tow
/
DATA IN
I'
tOH
"-
'1
NOTES:
1.
2.
3.
4.
5.
6.
7.
wr:. or CS
must be high during all address transitions.
A write occurs during the overlap (tcw or twp ) of a low CS and a low
tWR is measured from the earlier of CS or
going high to the end of the write cycle.
During this period, the 110 pins are in the output state, and input Signals must not be applied.
If the CS low transition occurs simultaneously with or after the VIr:. low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state.
If C5E" is low during a VIr:. controlled write cycle, the write pulse width must be the larger of twp or (tWHZ + tow) to allow the I/O drivers to tum off
and data to be placed on the bus for the required tow. If OE is high during an WE controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP .
8. C5E" =
wr=.
wr=..
\IH
S4-76
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6198S/IDT619BL CMOS STATIC RAM 64K (16Kx 4-BIT)
CAPACITANCE(TA= +25°C, f = 1.0MHz)
TRUTH TABLE
CS
MODE
WE
OE
I/O
POWER
Standby
H
X
X
HighZ
Standby
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Read
L
H
H
HighZ
Active
SYMBOL
CIN
PARAMETER(1)
Input Capacitance
CONDITIONS
MAX.
UNIT
7
pF
VIN = OV
VOUT= OV
COUT
Output Capacitance
7
pF
NOTE:
1. This parameter is determined by device characterization: but is not
production tested.
ORDERING INFORMATION
IDT
xxxx
Device Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
Range
Y:,ank
C
P
1.---------1 L
SO
Y
15
19
20
25
30
35
45
55
70
85
~
______________________--II S
I L
~------------------------------------~ 6198
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8
Sidebraze THINDIP (300 mil.)
Plastic DIP
Leadless Chip Carrier
Small Outline IC (Gull Wing)
Small Outline IC (J-bend)
Commercial Only
Commercial Only
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
16K x 4-Bit
54-71
--------
------_._---_._------------- --------------------------
.. f;) .
l~tegratedDevice~lnc.
lOT 71885
lOT 7188L
CMOS STATIC RAM
64K (16K x 4-8IT)
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle times)
- Military: 20/25/30/35/45/55170/85ns (max.)
- Commercial: 15/20/25/30/35/45ns (max.)
• Low power consumption
- 10T7188S
Active: 350mW (typ.)
Standby: 100~W (typ.)
-10T7188L
Active: 300mW (typ.)
Standby: 30~W (typ.)
• Battery backup operation - 2V data retention
(L version only)
• Available in high-density industry standard 22-pin, 300 mil
ceramic and plastic DIP, 24-pin SOIC, 24-pin Flatpack and
CERPACK
• Produced with advanced CEMOS ™ technology
• Single 5V (±.10%) power supply
• Inputs/outputs TTL-compatible
• Three-state outputs
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STO-883, Class B
The 1017188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using lOT's high-performance, highreliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory intensive applications.
Access times as fast as 15ns are available, with typical power
consumption of only 300mW. The 1017188 offers a reduced power
standby mode, ISB1, which enables the deSigner to greatly reduce
device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing
system reliability. The low-power version (L) version also offers a
battery backup data retention capability where the circuit typically
consumes only 30~W operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a
Single 5V supply. Fully static asynchronous circuitry, along with
matching access and cycle times, favor the simplified system design approach.
The 1017188 is packaged in 22-pin, 300 mil ceramic and plastic
DIPs, 24-pin SOICs, flatpacks and CERPACKs, providing excellent
board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
LOGIC SYMBOL
A
GND
DECODE
IIO:!
110:3
65.536-BIT
MEMORY ARRAY
A
COLUMN 1/0
~--~~~--------------------------------------~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated DevIce Technology. Inc.
JANUARY 1989
OSC-l026/1
84-78
- ----
-----------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT7188S/IDT7188L 64K (16Kx 4-BIT) CMOS STATIC RAM
PIN CONFIGURATIONS
Ao
Al
A2
A3
A4
Ao
Al
A2
A3
A4
Vee
A13
Vee
A13
A5
A12
All
A10
Ag
1/04
1/0:3
A6
A7
As
1/04
1/0:3
CS
1I0z
CS
I/Oz
NC
GND
1/01
NC
GND
1/01
A12
All
A10
Ag
A5
NC
A6
A7
As
wr:.
wr:.
FLATPACK/CERPACK/SOIC
TOP VIEW
SOIC
TOP VIEW
DIP
TOP VIEW
NC
j
RECOMMENDED DC OPERATING CONDITIONS
PIN NAMES
Ao-AI3
Address Inputs
1/01 -1/04
Data I/O
CS
Chip Select
Power
WE
Write Enable
Vee
GND
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
SYMBOL
Ground
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TslAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
MIN.
TYP.
MAX.
Vee.
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
'v\H
'v\L
Input High Voltage
2.2
-
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
UNIT
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 2011s.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
Vee
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
- conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con. ditions for extended periods may affect reliability.
S4-79
------------------- ---- --.. ---------- --- --- ---- -------------------_._--._---_.-
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7188S/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAM
DC ELECTRICAL CHARACTERISTICS
-
Vee = 50V +10%
SYMBOL
Ilul
IILol
TEST CONDITION
PARAMETER
MIN.
Input Leakage Current
Vee = Max.• VIN = GND to Vee
MIL.
COM·L.
Output Leakage Current
Vee = Max.
~ = VIH • VOUT = GND to Vee
MIL.
COM·L.
Output Low Voltage
VOH
Output High Voltage
NOTE:
1. Typical limits are at Vee = 5.0V.
-
-
-
10L = 8mA. Vee = Min.
-
10H= -4mA. Vee = Min.
2.4
10L = 10mA. Vee = Min.
VOL
-
IDT7188S
TYP.(l) MAX.
MIN.
10
5
-
10
5
-
-
IDT7188L
TYP.l1) MAX.
-
0.4
-
-
-
2.4
-
0.5
UNIT
5
2
J.LA
5
2
J.l.A
0.5
V
. 0.4
V
-
V
+ 25° C ambient.
DC ELECTRICAL CHARACTERISTICS (1)
Vee = 5.0V ±10%. VLe = 0.2V. VHC = Vee - 0.2V
7188S15
SYMBOL
PARAMETER
7188S20
POWER
7188S25
7188L25
7188S30/35
7188L30/35
COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL
leel
lec2
IS9
IS91
Operating,.Power
Supply Clirrent
CS = VIL•
Outputs Open
Vee = Max .•
f = 0(2)
Dynamic
Operating Current
CS = VIL•
Outputs Open.
Vee = Max .•
f =,;fMAX(2)
Standby Power
Supply Current
(TIL Level)
CS ~VIH.
Vec = Max.•
Outputs Open
f = fMAX(2)
Full Standby
Power Supply
Current (CMOS
Level)
OS ~ VHC '
Vec= Max.•
"'N ~ VHe or
"'N S VLe
f = 0(2)
S
120
140
7188S45/55(3)
7188L45/5S(3)
7188S70
7188L70
7188S85
7188L85
UNIT
COM'L MIL. COM'L MIL. COM'L MIL
100
125
100
110
100
110
110
110
85
110
85
95
85
95
95
95
135
155
125
140
125
140
140
140
125
145 1151105125/115
100
110
110
105
55
60
45
50
50
50
mA
L
S
155
175
mA
L
S
60
70
50/45 55/50
mA
L
S
20
25
45
50
15
20
40/35 45/40
15
20
30
35
35
35
15
20
·20
20
mA
L
0.5
1.5
0.5
1.5
0.5
1.5
1.5
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRe. f = 0 means no input lines change.
3. -55°C to + 125°C temperature range only.
S4-80
1.5
IDT7188S/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V LC
= O.2V. VHC = Vcc
- O.2V
TVP.(1)
SYMBOL
VDR
ICCDR
TEST CONDITION
PARAMETER
-
Vcc for Data Retention
Data Retention Current
t CDR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
ilu l(3)
Input Leakage Current
CE ?VHC
VIN ~ VHC or ~ VLC
Vcc @
2.0V
3.0V
MIN.
I MIL.
I COM·L.
MAX.
Vcc@
2.0V
3.0V
2.0
-
-
-
-
-
10
15
600
900
10
15
150
225
UNIT
V
J.lA
-
-
ns
t RC (2)
-
-
2
J.lA
0
ns
NOTES:
1. TA = 25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vcc
VDR 2: 2V
4.5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
DATA OUT
~
2550
5V
4800
DATAoUT
30pF*
~
2550
Figure 1. Output Load
4800
5pF*
Figure 2. Output Load
(for t HZ' tu. twz and tow)
* Including scope and jig.
S4-81
----
._------.------_.._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDT7188S/IDT718~L
64K (16K x 4-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ±10%. All Temperature Ranges)
7188S20(4)
7188S15(1)
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MIN.
MAX.
MIN.
7188S35/45 7188S55/70(2) 7188S85(2)
7188L35/45 7188 L55/70 (2) 7188L85(2) UNIT
MIN.
MAX. MIN. MAX. MIN. MAX.
7188S25/30
7188L25/30
MIN.
MAX.
PARAMETER
MAX.
READ CYCLE
tRC
Read Cycle Time
15
:.)~:.
20
-
25/30
-
35/45
-
55{70
-
85
ns
Address Access Time
-
20
-
35/45
-
55{70
ns
-....:·:,:::::::15
:
-
20
25/30
-
35/45
-
55{70
-
85
Chip Select Access Time
-
25/30
tACS
-
::::'1:5
-
tM
85
ns
tOH
Output Hold from Address Change
5:;;;:::::::::' -
5
-
5
-
5
-
5
5
Chip Selection to Output in Low
Z(3)
5,:::::;::;::' -
5
-
5
-
5
-
5
5
-
ns
tLZ
-
tHZ
Chip Deselect to Output in High
Z(3)
i::::-:/
7
-
8
-
10/12
-
14
-
20/25
-
30
ns
tpu
Chip Select to Power Up Time (3)
.iQ\:i
-
0
-
0
-
0
-
0
-
0
-
ns
tpD
Chip Deselect to Power Down Time(3)
"S::'
15
-
20
-
25/30
-
35/45
-
55{70
-
85
ns
NOTES:
1. O°C to -70°C temperature range only.
2. -55°C to -125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Preliminary data only for military devices.
TIMING WAVEFORM OF READ CYCLE NO.
1(1.2)
t
RC
(5)
----------..,~~......._ -
ADDRESS
tM ------~.'
DATA OUT
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
2(1,3)
t---------\4------
t AcS
t RC (5)
---------~
-----~
DATA OUT
HIGH IMPEDANCE
Vcc SUPPLY
CURRENT
NOTES:
wr=
1.
is high for READ Cycle.
2. CS is low for READ cycle.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state voltage.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
S4-82
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7188S/IDT7188L 64K (16Kx 4-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ±10%, All Temperature Ranges)
7188S15(1)
SYMBOL
7188S20(4)
PARAMETER
MIN. MAX.
MIN.
MAX.
7188S35/45
7188S25/30
7188L25/30
7188L35/45
MAX.
MIN. MAX.
MIN.
7188S55/70(2)
7188L55/70(2)
MAX.
MIN.
7188S85(2)
7188L85(2) UNIT
MIN. MAX.
WRITE CYCLE
twc
Write Cycle Time
14
.\~ ..
17
-
20/22
-
30/40
-
50/60
tcw
Chip Select to End of Write
14
:t::~~:::
17
20/22
14
:';'::+'
17
t AS
Address Set-up Time
O::::::{::~
0
-
50/60
Address Valid to End of Write
twp
Write Pulse Width
14:::::::::::::::::~
17
-
20/22
Write Recovery Time
o .':::i\::::-
0
-
0
0
-
50/60
tWR
tDW
Data Valid to End of Write
""':.:':(
10
13/15
-
25/35
tAW
-
15/20
-
25/30
tDH
Data Hold Time
twz
Write Enable to Output in High
tow
Output Active from End of Write (3)
z(3)
.::
20/22
0
25/35
0
50/60
0
-
75
-
75
75
75
0
-
ns
-
ns
ns
ns
ns
(t:,::::.::i: -
0
-
0
-
0
-
0
-
0
-
61:::::·
5
-
6
-
7/10
-
10/15
-
25/30
-
40
ns
-
5
-
5
-
5
-
5
-
5
-
ns
::::5\:,:·
-
NOTES:
1. O°C to -70 o e temperature range only.
2. -55°e to -125°e temperature range only.
3. This parameter is guaranteed but not tested.
4. Preliminary data only for military devices.
S4-83
-----.-------_._----
25/35
0
0
35
ns
ns
ns
IDT7188S/IDT7188.L 64K (16K x 4-BIT) CMOS STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3)
ADDRESS
~---------
---------.-t
tAW
104----
tow (6)
DATA OUT
_ ______________________________
DATA IN
~t:==-tD-w-----.-I.----t-DH-==:1~______________
IC
--=>r
DATA VALID
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(1,2,3,5)
twc
ADDRESS
~
--./
)K
K
tAW
I - - - tAS
-
~V
"to\.
tWR
tcw
_ __________________________________
-
~~-t-Dw------.~I-.----tD-H-~~-------------
DATA IN
L
DATA VALID
-./I-
NOTES:
1.
2.
3.
4.
5.
6.
~ or CS must be high during all address transitions.
A write occurs during the overlap (t wp ) of a low CS and a low ~.
tWR is measured from the earlier of CS or W'C. going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals should not be applied.
If the CS low transition occurs simultaneously with or after the ~ low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state.
S4-84
........
-.------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I DT7188S/1 DT7188L 64K (16K x 4-BIT) CMOS STATIC RAM
CAPACITANCE
TRUTH TABLE
SYMBOL
(TA= +25°C, f = 1.0MHz, Vcc = oV)
PARAMETER(1)
MODE
CS
WE
I/O
POWER
Standby
H
X
HighZ
Standby
CIN
Input Capacitance
Read
L
H
DOUT
Active
COUT
Output Capacitance
Write
L
L
DIN
Active
CONDITIONS
MAX.
'-"N= OV
6
pF
VOUT= OV
6
pF
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.
ORDERING INFORMATION
lOT
xxxxx
Device Type
A
Power
999
A
Speed
Package
UNIT
A
Process/
Temperature
-y:'~k
o
P
C
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _~
SO
Y
F
E
Y
'--------------1
15
20
25
30
35
45
55
70
85
S
I L
L - -_ _ _ _ _ _ _ _ _ _ _ _~I
--I 7188
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
S4-85
Commercial (O°C to
+ 70°C) .
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Ceramic DIP
Plastic DIP
Sidebraze DIP
Small Outline IC (Gull Wing)
Small Outline IC (J-Bend)
Flatpack
CERPACK
Small Outline (J-Bend)
Commercial onlY}
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (16K x 4-Bit)
t;J
lOT 71985
IOT7198L
CMOS STATIC RAMS
. 64K (16K x 4-8IT)
Integrated Devlce1echnology.1IiC.
. Added Chip Select and Output Enable Controls
FEATURES:
DESCRIPTION:
• Optimized for fast RISC processors, including
IDT79R3000
• Fast Output Enable (OE) pin available for added system
flexibility
• Multiple Chip Selects (CS 1 , CS 2 ) simplify system design and
operation
• High speed (equal access and cycle times)
- Military: 20/25/30/35/45/55/70/85ns (max.)
- Commercial: 15/19/20/25/30/35/45ns (max.)
• Low power consumption
- IDT7198S
Active: 350mW (typ.)
Standby: 100pw (typ.)
- IDT7198L
Active: 300mW (typ.)
Standby: 30pw (typ.)
• Battery back-up operation - 2V data retention (L version only)
• 24-pin THINDIP, 24-pin plastic DIP, high-density 28-pin
lead less chip carrier, 24-pln SOIC, flatpack and CERPACK
• Produced with advanced CEMOS ™ technology
• Bidirectional data Inputs and outputs
• Inputs/outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-86859 is pending listing on
this function. Refer to Section 2/page 2-4.
The IDT7198 is a 65,536 bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT's high-performance, highreliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory Intensive applications. Timing
parameters have been specified to meet the speed demands ofthe
fastest IDT79R3000 RISC processors.
The IDT7198 features three memory control functions: Chip
Select 1 (CS 1 ), Chip Select 2 (CS 2 ) and Output Enable (OE).
These three functions greatly enhance the IDT7198's overall
flexibility in high-speed memory applications.
Access times as fast as 15ns are available, with typical power
consumption of only 300mW. The IDT7198 offers a reduced power
standby mode,lsBl, which enables the designer to considerablyreduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing
system reliability. The low-power version (L) also offers a battery
backup data retention capability where the circuit typically
consumes only 30pW when operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from
a single 5 volt supply. Fully static asynchronous circuitry, along
with matching access and cycle times, favor the simplified system
design approach.
The 1DT7198 is packaged In either a 24-pin ceramic DIP,24-pin
plastic DIP, 28-pin leadless chip carrier, 24-pln SOIC and 24-pin
flatpack or CERPACK. providing improved board-level packing
densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
o
FUNCTIONAL BLOCK DIAGRAM
A
Vcc
GND
65,536-BIT
MEMORY ARRAY
DECODER
A.
COLUMN I/O
~
01:-~~....,
CEMOS Is a trademark of Integrated Device Technology, Inco
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inco
JANUARY 1989
DSC-l02711
S4-86
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT1198L CMOS STATIC RAM 64K (16K x 4-81T)
Both chip selects, Chip Select 1(CS 1) and Chip Select 2 (CS 2 ),
must be in the active-low state to select the memory. If either chip
select is pulled high, the memory will be deselected and remain in
the standby mode.
_
The fast output enable function (OE) is also a highly desirable
feature of the IDT7198 high-speed common 110 static RAM. This
function is designed to eliminate problems associated with data
bus contention by allowing the data outputs to be controlled
independent of either chip select. Its speed permits further decreases in bverall read cycle timing.
.
These added memory control features provide improved
system design flexibility, along with overall system speed
. performance enhancements.
MEMORY CONTROL:
The IDT7198 64K high-speed CEMOS static RAM incorporates
two additional memory controifeatures (an extra chip select and an
output enable pin) which offer additional benefits in many system
memory applications.
:.
. _
_
The dual chip select feature (CS 1 , CS 2 ) now brings the
convenience of improved system speeds to the large memory
designer by reducing the extemal logic required to perform
decoding. Since external decoding logic is reduced, board space
is saved, system speed is enhanced by approximately 10-20ns
and system reliability improves as a result of lower parts count.
(See technical note 1 "Using Two Chip Selects on the IDT7198.")
PIN CONFIGURATION
Ao
Vee
Al
A2
A13
cO
« z ~
INDEX
LJUIIULJ
3 2 U 2S 27
1
A12
All
AlO
Ag
A3
A4
As
As
26 C
2S [:
NC
A13
C
C
A12
24
23
L28-2
CS 2
As
<:;51
1/04
1/0:3
1/0.!
~
I/~
GND
wr=.
A7
LOGIC SYMBOL
J3 ~
22 [:
21 [:
20 [:
19
IS
13 14 IS IS 17
.
DIP/SOIC/FLATPACKICERPACK
TOP VIEW
nnnnn
~ ~~~ g
LCC
TOP VIEW
All
AlO
Ag
c
1/04
1/0:3
C
I/Oz
Ao
AI
A2
A3
A4
As
As
A7
As
Ag
AlO
All
A12
A13
1/01
I/Oz
1/0:3
1/04
CS1CS2~·wr=.
PIN NAMES
Ao-AI3
Address Inputs
OE
Output Enable
CS 1
Chip Select 1
1/01 -1/04
Data I/O
CS2
Chip Select 2
Vee
Power
WE
Write Enable
GND
Ground
S4-87
- - - - - _ .._---_._----------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BI1)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-:55 to + 125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
-55 to +125
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
-
6.0
V
,VIL
Input Low Voltage
-0.5(1)
-
O.S
V
SYMBOL
°C
PARAMETER
UNIT
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
OOCto +70 o C
OV
5.0V ± 10%
Vee
DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL
TEST CONDITION
PARAMETER
MIN.
Ilul
Input Leakage Current
Vce = Max., V1N = GND to Vee
MIL.
COM'L.
IILol
Output Leakage Current
C'S' =
Vec = Max.
V1H , VOUT = GND to Vec
MIL.
COM'L.
IOL = 10mA, Vce = Min.
VOL
Output Low Voltage
VOH
Output High Voltage
10L = SmA, Vee = Min.
IOH= -4mA, Vce= Min.
-
S4-88
MIN.
IDT7198L
TYP.(l) MAX.
-
0.4
-
-
2.4
-
-
10
5
-
-
-
-
10
5
2.4
NOTE:
1. Typical limits are at Vec = 5.0V, +25°C ambient.
IDT7198S
TYP.(1) MAX.
0.5
-
UNIT
5
2
J..lA
5
2
J..lA
0.5
V
0.4
V
-
V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BIT)
DC ELECTRICAL CHARACTERISTICS(l)
Vcc = 5.0V ±10%. VLC = 0.2V. VHC = VCC - 0.2V
SYMBOL
PARAMETER
ICCl
Operating Power
Supply Current
CS = VIL•
Outputs Open
Vcc = Max.•
f = 0(2)
POWER
7198815
7198S19/20
7198S25
7198L25
7198S30/35
7198L30/35
COM'L. MIL. COM'L.MIL. COM'L.MIL COM'L
Icc2
Dynamic
Operating Current
CS = VIL•
Outputs Open.
Vcc = Max.•
f = fMAX (2)
Standby Power
Supply Current
(TTL Level)
ISB
ISBl
CS ;::\{H'
Vcc = Max.•
Outputs Open
f = fMAX (2)
Full Standby
Power Supply
Current (CMOS
Level)
CS;:: VHC •
Vcc= Max.,
'-"N ;::VHC or
VIN :s VLC ' f = 0(2)
S
7198S45/55(3)
7198L45/55(3)
MIL COM'L
7198S70(3)
7198L70(3)
7198S85(3)
7198L8S<3) UNIT
MIL COM'L. MIL. COM'LMIL.
120
140
100
125
100
110
100
110
-
110
-
110
-
-
85
110
85
95
85
95
-
95
-
95
155
175
135
155
125
140
125
140
-
140
-
140
mA'
L
-i'iii:::::III:::':::
S
18~:::::::::::::::·i
}{:::::::::;:::;::::
L
S
L
S
L
JiiIi::I:::::t
:::::::::::::::;:.:.:.:.,
7iif
n::::::::fi,'r
'~:i!
!Ei~!; -
mA
-
-
125
145 115/105 125/115
60
70
55
60
50/45
55/50
100
110
-
110
-
105
45
50
-
50
-
50
mA
-
-
45
50
40/35
45/40
30
35
-
35
-
35
20
25
15
20
15
20
15
20
-
20
-
20
mA
-
-
0.5
1.5
0.5
1.5
0.5
1.5
-
1.5
-
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC' f = 0 means no input lines change.
3. -55°C to + 125°C temperature range only.
'
84-89
1.5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16Kx 4-BIT)
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
VOR
I
MIN.
TEST CONDITION
PARAMETER
SYMBOL
-
Vcc for Data Retention
I MIL.
COM'L.
ICCDR
Data Retention Current
t CDR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
/lui (3)
Input Leakage Current
CS~
\'IN
VHC
~ VHC or:::; VLC
'.
NOTES:
1. TA = +25°C
2. t RC := Read Cycle Time
.
3. Thi~ parameter is guaranteed but not tested.
TYP.(1)
Vee @
2.0V
3.0V
MAX.
Vee@
2.0V
3.0V
2.0
-
-
-
-
-
10
15
600
900
10
15
150
225
-
0
t RC (2)
-
2
J.LA
AC TEST CONDITIONS
DATAoUT
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
:q
2550
:q
5V
4800
DATA OUT
30pF*
2550
Figure 1. Output Load
4800
5pF*
Figure 2. Output Load
(for tCU1. 2. tOUt t CHZ1, 2. t oHZ'
tow and tWHZ)
* Including scope and jig.
S4-90
~
ns
DATA RETENTION MODE
5V
V
-
LOW Vee DATA RETENTION WAVEFORM
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
UNIT
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(ycc = 5V ±10%. All Temperature Ranges)
7198S55(2) 7198S70(2) 7198S85(2)
7198S25/30
7198S35/45
7198LSS(2) 7198L70(2) 7198L8S(2)
7198L25/30
7198L35/4S
UNIT
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.
MAX. MIN.
MAX. MIN.
7198S15(1)19/20(5)
MIN.
READ CYCLE
.:::::\\::%::,
Read Cycle Time
tAA
Address Access Time
):l§!.l~/20
25/29
35/45
tACS1.2
Chip Select-1. 2 Access Time (3)
/hSi29120
25/30
35/45
t CLZ1 . 2
Chip Select-1. 2 to Output in
,.
Low Z(4)
tOE
Output Enable to Output Valid
toLZ
Output Enable to Output in
LOWZ(4)
15/20/20
5
. ·::::::{:::::I::::~
25/30
55
t RC
5
'5
-
5
11/18
;::::/?}J/9/9
.:;::::; .:.;.:::;:;:{
35/45
5
-
70
5
ns
70
85
ns
55
70
85
ns
5
5
35
20/25
85
55
5
5
45
5
ns
55
5
ns
ns
:;:;:i:;:;:;
:;.:.
tCHZ1.2
Chip Select-1. 2 to Output in
High Z(4)
- ::t:::r:::::;:::::::7/8/8
10/12
14
20
25
30
ns
tOHZ
Output Disable to Output in
High Z(4)
.
.
-::::;::::::;:::::;:::r 7/8/8
9/12
15
20
25
30
ns
tOH
Output Hold from Address
Change
$.:i::{:::::::t::
5
5
5
5
5
ns
tpu
Chip Select to Power Up Time (4)
m:;:I:{::::::'
0
0
0
0
0
ns
tpD
Chip Deselect to Power Down
Time(4)
::::biii:i:::::::=:' 15/20/20
25/30
35/45
55
70
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. 80th chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.
5. Preliminary data only for military devices.
S4-91
----- .
__._----------_.
--_ .... _.
__ ._-- ._-_.__ _-_._--_. -_.. _---_...
..
_.. _-.------_._-_.
85
ns
91
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16Kx 4·BIn
TIMING WAVEFORM OF READ CYCLE NO.
~
1(1)
I-----------
ADDRESS
tRC
-------------i-.j
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __'
...~I__------- tAA
.. I
....- - - - tOE
f o 4 - - - - - t ACS1 ' t ACS2 ---+----~
tCLZ1 ' tCLZ2 (5)
DATA
---~
OUT
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
ADDRESS
~::=~-tAA-tRC
DATA
OUT
-*-.=tCH ~
- - = = =r:-=-=_-= -~-=~ =-~-=~_-= t=OH= = = = =:)lc:I=~= = = = ='=~= = = = = :~:
..
, .. I
1:======
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
f o 4 - - - - - - tAcs1 ' t ACS2 - - - - . . - /
t CHZ1
tCLZ1 ' tCLZ2 (5)
DATA
OUT
Vee SUPPLY
Icc
CURRENT
ISB
NOTES:
1.
is High for Read Cycle.
2. Device is continuously selected, CS 1 = V 1L ,CS 2 = V1L•
3. Address valid prior to or coincident with CS 1 and or CS2 transition low.
4. DE" = ~L
5. Transition is measured ±200mV from steady state.
wr:.
54-92
' tCHZ2 (5)
fo4----...j
--------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I DT7198S/1 DT7198L CMOS STATIC RAM 64K (16K x 4-BI1)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(\bc = 5V ±10%, All Temperature Ranges)
7198S85(2)
7198S55(2) 7198570(2)
7198S25/30
7198S35/45
7198L55 (2) 7198L70(2)
7198L85(2)
7198L25/30
7198L35/45
UNIT
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX. MIN.
MAX.
7198S15(1)19/20(5
PARAMETER
MIN.
WRITE CYCLE
twc
Write Cycle Time
t CW1 . 2
Chip Select to End of Write
(3)
13/17/17
tAW
Address Valid to End of Write
13/17/17
.:::;b::::::: 20/22
.::t}~::~ 20/22
13/17/17
tAs
Address Set-up Time
twp
Write Pulse Width
t wR1 . 2
Write Recovery Time
tWHZ
Write Enable to Output High
tow
Data Valid to End of Write
tOH
Data Hold Time
tow
Output Active from End of
Write (4)
.............i-;.I.
....::.:..:::.
::::::::}t::::~
0
13/17/17..::':
0
Z(4)
-
8I1o.Mf';}
';':::::::::'
.:9 ::.,.;.:.;
.{:~:::::;.::::'
25/35
50
-
60
-
75
50
60
50
-
75
-
-
60
75
-
ns
ns
ns
0
-
0
-
ns
60
75
-
ns
ns
0
-
0
-
0
0
0
-
5/6/6
-
7/10
-
10115
-
25
-
30
-
40
ns
-
13
-
15/20
25
-
ns
0
0
0
5
-
5
-
5
-
5
-
ns
-
-
35
-
-
30
0
-
0
20/22
-
25/35
-
-
-
:::/~~~~ ;:;:;. .:::;:::::::::::;;
30/40
-
-
:;;::;::;:.,
....;...
20/22
-
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Both chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.
5. Preliminary data only for military devices.
S4-93
0
25/35
0
50
0
5
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K X 4-81T)
TIMIt:JG WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1, 2, 3,7)
ADDRESS
t+-------------.t AW - - - - - - - - - - . \
---+-,
t wp
DATA OUT
------c }.• . •. •. . •. .{•
<:.!~)
(7)
.). . . . . . ..
_ _ _ _ _
-f(~t~
• I.,
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)(1,2,3,5,a)
twc
ADDRESS
~
-./
)K
K
tAW
CS 1'
cs 2
~V
"r\.
I + - - tAS
tWR
tcw
_________________
~
~~-t-ow---.-'.---to-H-~~-------
NOTES:
wr=.,
1.
C51 or CS 2 must be high during all address transitions.
2. A write occurs during the overlap (wp) of a low C51, a low CS 2 and a low~.
3. tWR is measured from the earlier of CS1 , CS2 or
going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the C5 low transition occurs simultaneously with or after the
low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV from steady state.
7. If DE" is low during a
controlled write cycle, the write pulse width must be the greater of twp or (tWHZ + tow) to allow the I/O drivers to tum off
controlled write cycle, this requirement does not apply and the
and data to be placed on the bus for the required tow. If DE" is high during a
write pulse can be as short as the specified twP.
8. DE" = V,H
wr=.
wr=.
wr=.
wr=.
S4-94
IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
MODE
CAPACITANCE
CS1 CS2 WE
OE
1/0
SYMBOL
POWER
Standby
H
X·
X
X
HighZ
Standby
Standby
X
H
X
X
HighZ
Standby
Read
L
L
H
L
DOUT
Active
Write
L
L
L
X
DIN
Active
Read
L
L
H
H
HighZ
Active
CIN
(TA= +25°C,f = 1.0MHz, Vcc= OV)
PARAMETER(1)
CONDITIONS
MAX.
UNIT
\IN = OV
7
pF
Input Capacitance
COUT
Output Capacitance
7
pF
VOUT= OV
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.
ORDERING INFORMATION
lOT
xxxxx
999
Device Type
Speed
A
Package
A
Process/
Temperature
Range
y:1Mk
'----------i
D
P
C
L
SO
Y
E
F
15
19
20
25
30
'----------------------~ 35
45
55
70
85
IsL
~----------------------__il
~--------------------------------------~ 7198
S4-95
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Ceramic DIP
Plastic DIP
Sidebraze DIP
Leadless Chip Carrier
Small Outline IC (Gull Wing)
Small Outline IC (J-bend)
CERPACK
Flatpack
Commercial Only
Commercial Only
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (16K x 4-Bit)
t;)
CMOS STATIC RAMS
64K (16K x 4-BIT)
IntegratedDevice~lnc.
lOT 71981S/L
lOT 71982S/L
Separate Data Inputs and Outputs
FEATURES:
DESCRIPTION:
• Optimized for fast RISC processors including the
IDT79R3000
• Separate data Inputs and outputs
• IDT71981S/L: outputs track inputs during write mode
• IDT71982S/L: high Impedance outputs during write mode
• High speed (equal access and cycle time)
- Military: 20/25/30/35/45/55170/85ns (max.)
- Commercial: 15/19/20/25/30/35/45ns (max.)
• Low power consumption
- 1DT71981/2S
Active: 350mW (typ.)
Standby: 100jJw (typ.)
- IDT71981/2L
Active: 300mW (typ.)
Standby: 30jJw (typ.)
• Battery backup operation-2V data retention (L version only)
• High-density 28-pin hermetic and plastic DIP, 28-pin lead less
chip carrier, 28-pin SOIC
• Produced with advanced CEMOS ™ high-performance
technology
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B
The IDT71981/IDT71982 are 65,536-bit high-speed static RAMs
organized as 16K x 4. They are fabricated using lOT's highperformance, high-reliability technology-CEMOS. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost effective alternative to bipolar and fast
NMOS memories. Timing parameters have been specified to meet
the speed demands of the fastest IDT79R3000 RISC processors.
Access times as fast as 15ns are available with typical power
consumption of only 300mW. These circuits also offer a reduced
power standby mode (ISB). When CS 1 goes high, the circuit will
automatically go to, and remain in, this standby mode. In the ultralow-power standby mode (ISB1), the devices consume less than
2.5mW, typically. This capability provides significant system-level
power and cooling savings. The low-power (L) versions also offer a
battery backup data retention capability where the circuit typically
consumes only 30jJW operating off a 2V battery.
All inputs and outputs of the IDT71981/IDT71982 are TTL-compatible and operate from a single 5V supply, thus simplifying system designs. Fully static asynchronous circuitry is used, which
requires no clocks or refreshing for operation, and provides equal
access and cycle times for ease of use.
The IDT71981/IDT71982 are packaged in either space-saving
28-pin, 400 mil hermetiC DIPs, 28-pin 300 mil plastic DIP, 28-pin
SOIC or 28-pin lead less chip carriers, providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class S, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
---r--,
Vee
GND
ROW
SELECT
A
65,536 BIT
MEMORY ARRAY
----i
--D
DD-tr~r;~~~
COLUMN I/O
y
Y
CS1
Y
CS2--======~~~
--------,
'----i-i>-Y
IDT71982 ONLY I
vr
L _ _ _ _ _ _ _ _ _ _ .J
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-1028/1
1989 Integrated Device Technology, Inc.
S4-96
--------
------------------ -
--------------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K x 4-BI1)
PIN CONFIGURATIONS
INDEX
LJUIIUU
32U2S27
]
1
4
A4
:] 5
As
:] e
Ae
] 7
A7
]
s
As
Dl
]
]
9
D2
:] 11
CSl
] 12
L28-2
10
DIP/SOIC
TOP VIEW
LCC
TOP VIEW
LOGIC SYMBOL
Ao
Al
A2
A3
A4
As
Ae
A7
As
Ag
A 10
All
A12
A 13
PIN NAMES
Y4
Y3
'12
VTERM
RATING
Terminal Voltage
with Respect to
GND
Address Inputs
D 1-D4
Yl-Y4
DATA IN
Chip Selects
WE
Write Enable
GND
Ground
OE
Output Enable
Vee
Power
DATA OUT
V,
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Ao-A13
CS 1• CS 2
-0.5 to +7.0
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
Pr
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
PARAMETER
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
UNIT
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
-
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
DoC to +70°C
OV
5.0V ± 10%
Vee
S4-97
-------------------------------------- ,-----,-
----,,---
._---
, MILITARY AND COMMERCIAL TEMPERATURE RANGES
:IDT7HJ81/IDT71982 CMOS STATIC RAMS 64K (16Kx 4·BIT)
DC ELECTRICAL CHARACTERISTICS
Vee = 50V -+10%
SYMBOL
TEST CONDITION
PARAMETER
MIN.
Ilul
Input Leakage, Current
Vee = Max., VIN = GND to Vee
MIL.
COM'L.
-
IILol
Output Leakage Current
Vee = Max.
~ = VIH , VOUT = GND to Vee
MIL.
COM'L.
10L= 8mA, Vee = Min.
-
10L = -4mA, Vee = Min.
2.4
10L = 10mA, Vee = Min.
VOL
Output Low Voltage
VOH
Output High Voltage
NOTE:
1. Typical limits are at Vee = 5.0V,
IDT71981/2S
TYP.(l) MAX.
-
IDT71981/2L
MIN. TYP51) MAX.
-
10
5
-
UNIT
-
5
2
,.,.A
-
5
2
,.,.A
-
0.5
V
0.4
-
0.4
V
-
2.4
-
-
V
10
5
0.5
+ 25°C ambient.
DC ELECTRICAL CHARACTERISTICS (1)
Vee = 5.0V ±10%, VLe = 0.2V, VHe = Vee - 0.2V
71981/2S15
POWER
SYMBOL PARAMETER
71981/2
S19/20
71981/2S25 71981/2S30/35 71981/2S45/55(3) 71981/2S70 71981/2S85
71981/2L25 71981/2L30/35 71981/2L45/55(3) 71981/2L70 71981/2L85 UNIT
COM'LMIL. COM'L.MIL COM'LMIL COM'L.
ICCl
lee2
ISB
ISBl
Operating Power
Supply Current
CS = VIL,
Outputs Open
Vee = Max.,
f = 0(2)
Dynamic
Operating Current
CS = VIL,
Outputs Open,
Vee = Max.,
f = fMAX(2)
Standby Power
Supply Current
(TTL Level)
CS ~ VIL,
Vee = Max.,
Outputs Open
f = f MAX(2)
Full Standby.
Power Supply
Current (CMOS
Level)
CS ~ Ytie,
Vcc= Max.,
\'IN ~VHe or
\'IN ~ VLe , f = 0(2)
MIL COM'L
MIL COM'LMIL COM'LMIL
S
l~~;}}?)f:
120
140
100
125
100
110
100
110
-
110
-
110
L
li.~: ·: I: i: : :i·:·:·i
-
-
85
110
85
95
85
95
-
95
-
95
155
175
135
155
125
140
125
140
-
140
-
140
-
-
125
145 115/105125/115 100
110
-
110
-
105
60
70
55
60
50
-
50
-
50
S
~:~~:::::;:;::::::i:;
mA
..
;:;:;:;:;:;:;:;:;:;:;:::;:;:::::;:
L
:::@::::I::::::::::[
.................................
::::~::::::;:
S
:::
mA
~:~:~:~:::::
IE
50/45
55/50
45
mA
::: :.;.:.:::::.:.:.:.:.:.:.:.:::
.:;:::;:;:;:::;:;:;:;:;:;:;:;::::::
L
:::Z::?t?tl·j
S
!~~
.::.
L
-
-
45
50
40/35
45/40
30
35
-
35
-
35
20
25
15
20
15
20
15
20
-
20
-
20
.:.:.:.::.:
mA
:.:.:.:.;.;.:.;.:.:.".:.,
-
-
I
0.5
1.5
0.5.
1.5
0.5
"
1.5
-
1.5
-
NOTES.
1. All values are maximum guaranteed values.
2. At f = fMAX address and data Inputs are cycling at the maximum frequency of read cycles of 1ltRe. f = 0 means no Input lines change.
3. -55°C to + 125°C temperature range only.
S4-98
1.5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) Vt.c
= 0 2V
SYMBOL
VDR
t
CDR
(3)
- 0 2V
TEST CONDITIONS
PARAMETER
,
Vcc for Data Retention
ICODR
t
= \bc
VHC
(3)
R
Ilu l (3)
-
MIN.
I
MIL.
COM'L.
Data Retention Current
CS~
Chip Deselect to Data Retention Time
\'IN
Operation Recovery Time
VHC
~ VHC or:s VLC
Input Leakage Current
TYP.(1)
Vee @
·2.0V
3.0V
MAX.
Vee @
2.0V
3.0V
2.0
-
-
-
-
-
10
15
600
900
10
15
150
225
-
-
-
-
-
ns
-
-
2
JlA
DATA RETENTION MODE
4.5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
:q
5V
DATA OUT
2550
:q
5V
480n
DATAoUT
30pF*
2550
Figure 1. Output Load
-J.1A
0
LOWVCC DATA RETENTION WAVEFORM
VDR ~ 2V
V
t RC (2)
NOTES:
1. TA = +25°C
2. .t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
Vcc
UNIT
4800
5pF*
Figure 2. Output Load
(for t CLZ1 , 2. tOLZ> t oHZ1 , 2. t OHZ '
tow and t WHZ )
* Including scope and jig.
S4-99
-----------------_.-----_._----------------
ns
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Read Cycle Time
tACS1.2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vee = 5V ±100/0, All Temperature Ranges)
71981/2S15(1) 71981/2S25/30 71981/2S35/45 71981/2S5s(2) 71981/2S70<2) 71981/2S85(2
/19/20
71981/2L25/30 71981/2L35/45 71981/2L55(2) 71981/2L70(2) 71981/2LB5(2 UNIT
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX.
15120/20::::;:::I~::::::TI
55
35/45
25/30
Address Access Time
25/29
35/45
Chip Select-1, 2 Access Time (3)
25/30
35/45
Chip Select-1, 2 to Output in
Low Z (4)
5
Output Enable to Output Valid
5
85
ns
55
70
85
ns
55
ns
5
35
5
45
5
5
ns
5
ns
Chip Select-1, 2 to Output in
High Z(4)
10/12
14
20
25
30
ns
Output Disable to Output in
High Z(4)
9/12
15
20
25
30
ns
Output Hold from Address
Change
5
5
5
5
5
Chip Select to Power Up Time (4)
o
o
o
o
o
Chip Deselect to Power Down
Time (4)
25/30
35/45
55
NOTES:
1.
2.
3.
4.
ns
70
5
20/25
11/18
Output Enable to Output in
Low Z (4)
-
85
70
55
O°C to + 70°C temperature range only. Data for 20ns devices is preliminary for military temperature range.
-55°C to + 125°C temperature range only.
Both chip selects must be active low for the device to be selected.
This parameter guaranteed but not tested.
S4-100
70
ns
ns
85
ns
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K x 4-81T)
TIMING WAVEFORM OF READ CYCLE NO.1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1)
ADDRESS
1'4-----
tOE
t OLZ (5)----t!'I
1 ' 4 - - - - - t ACS1 ' t ACS2 - - - t - - - I - t
tCLZ1 ' tCLZ2 (5) - - - - * I
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
=i:
t RC
..
DATA OUT
(1,2,4)
i ;J
tAA
tOH
t
tOH
-1
)1('
TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)
1 ' 4 - - - - - - t ACS1 ' t ACS2 - - - - - t o o l
t CHZ1 ' tCHZ2 (5)
tCLZ1 ' tCLZ2 (5)
DATA OUT
Vcc
t,ul~f
Icc
SUPPLY
CURRENT
-----------
ISB
NOTES:
WE is High for Read Cycle.
2. Device is continuously selected, CS 1 = V IL ' CS 2 = V1L•
3. Address valid prior to or coincident with
1 ' and or CS2 transition low.
4. OE' = \IL
5. Transition is measured ±200mV from steady state.
6. This parameter is guaranteed but not tested.
1.
cs
S4-101
/4------I-.{
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT71981/IOT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)
AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ±10%. All Temperature Ranges)
71981/2S15(1) 71981/2S25/30 71981/2S35/45 71981/2S592) 71981/2S70<2) 71981/2S85(2
/19/20
71981/2L25/30 71981/2L35/45 71981/2L55(2) 71981/2L70(2) 71981/2L85(2 UNIT
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX.
MIN.
PARAMETER
SYMBOL
WRITE CYCLE
13/17/17:: :::.:.
twc
Write Cycle Time
20/22
30/40
50
60
75
ns
tCW1,2
Chip Select to End of Write
20/22
25/35
50
60
75
ns
tAW
Address Valid to End of Write
20/22
25/35
50
60
75
ns
o
o
o
o
o
ns
20/22
25/35
50
60
75
ns
Address Set-up Time
Write Pulse Width
Write Recovery Time
tWHZ
Write Enable to Output High Z
0
(3, 5)
Data Valid to End of Write
-
;::::::::::::::::::::
-
o
.;:\\\;::;:;: 5/6/6
8/1 od~t::::::::
o
7/10
o
10/15
-
o
25
o
30
ns
40
ns
'13
15/20
25
30
35
ns
Data Hold Time
o
o
o
o
o
ns
Output Active from End of
Write (3,5)
5
5
5
5
5
ns
tlY
Data Valid to Output Valid (3,4)
twv
Write Enable to Output Valid (3, 4)
'.':'::.:::'
12/15
20/25
30/35
12/15
20/25
30/35
-
40
45
50
ns
40
45
50
ns
NOTES:
1. O°C to + 70°C temperature range only. Data for 20ns devices is preliminary for military temperature range.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
4. For IDT71981S/L only.
5. For IDT71982S/L only.
S4-102
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1)
~-----------------twc""'--------------~
ADDRESS
~-------------tAW""'------------~
i+------t wP (2) ______~
DATA IN
DATA OUT
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,5)
twc
ADDRESS
~(
jK
f--
tcw
'\. '\. ~ 1\
t WR1 ,2(3)
(4)
' \ ' \ '\.
~I\
~~/
f7////
}'t.
f----
tAW
tAs-
11'1
t
WH
\4-
tow-
~K,
DATA IN
DATA UNDEFINED
DATA OUT (8)
DATA UNDEFINED
j 4 - t OH
DATA VALID
I----
twv
DATA OUT (7)
tOH
1 4 - tow (6)_ I -
Z(6)
-
"'II
JI\.
t ,y
~I/
~
DATA VALID
,
(9)
~
1\--'
S4-103
..........
__
....
_..- ........ _....._ - - - -
.......... _..
-_ .....-..- - . - - -
...._ ...
_ - - - - - - _..._._-- ............ .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71981/1DT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WE CONTROLLED, OE LOW)
(1,5)
twc
)(
ADDRESS
)(
f4-
t WR1 .2(3)
L/LLL//
'\.'\. "~
tAW
tWp(2)
I
t:" ""~,,
t AS -
)'£
tDW
"
t DH -
"
DATA VALID
),-
),-
~ t-- t ly -
I--- twv -
(
DATA UNDEFINED
DATA our (7)
I-- tWHZ (6)
DATA OUT (8)
DATA UNDEFINED
_
DATA VALID (9)
,
NOTES:
1. WE' or ~ 1, or ~2 must be high during all address transitions.
2. A write occurs during the overlap (twp ) of a low WF:., a low ~ 1 and a low CS2 .
3. twR is measured from the earlier of CS1• CS2 or WE' going high to the end of the write cycle.
4. If the CS1 and or CS2 low transition occurs simultaneously with the WE' low transitions or after the WE'transition, outputs remain in a high
impedance state.
5. 01: is continuously low (01: = VIL).
6. Transition Is measured ±200mV from steady state.
7. For ID171981 only.
8. For ID171982 only.
9. DATAoUT = DATAIN
TRUTH TABLE
MODE
CAPACITANCE
CSl CS2 WE
OE
OUTPUT
POWER
Standby
H
X
X
X
HighZ
Standby
Standby
X
H
X
X
HighZ
Standby
Read
L
L
H
L
DouT
Active
Write (1)
L
L
L
L
DIN
Active
Write (1)
L
L
L
H
High Z
Active
Write (2)
L
L
L
X
HighZ
Active
Read
L
L
H
H
HighZ
Active
SYMBOL
CIN
(TA= +25°C. f = 1.0MHz, Vcc = OV)
PARAMETER(l)
Input Capacitance
CONDITIONS
MAX.
UNIT
"'N= OV
7
pF
COUT
Output Capacitance
7
pF
Vour= OV
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
NOTES:
1. For ID171981 only.
2. For ID171982 only.
S4-104
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)
ORDERING INFORMATION
lOT
xxxxx
A
Device Type
Power
999
Speed
A
Package
A
RMy:Mk
Process/
Temperature
13
P
'--_ _ _ _ _ _ _-/ C
L
SO
Y
I...--_ _ _ _ _ _ _ _ _ _~
~
________________________
~I
I
15
19
20
25
30
35
45
55
70
85
S
L
' - - - - - - - - - - - - - - - - - - - - - 11I 71981
71982
54-105
-_._-_._--... _ - - - - - - - - - - - - - - - - - - -
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8
Ceramic DIP (300 mil)
Plastic DIP (300 mil)
Sidebraze DIP (400 mil)
Leadless Chip Carrier
Small Outline IC (Gull Wing)
Small Outline IC (J-Bend)
Commercial Only
Commercial Only
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (16K x 4-Bit)
64K (16K x 4-Bit) High Impedance Outputs
Intesrated Device1echnoIogy. Inc.
'CMOS SYNCHRONOUS
STATIC RAM WITH
TRANSPARENT OUTPUTS
64K (16K x 4-8IT)
ADVANCE
INFORMATION
lOT 615925
lOT 61592L
FEATURES:
DESCRIPTION:
• 16K x 4-8it Organization
• High-speed Cycle Time'
- Commercial: 25ns
- Military: 30ns
• Address, Data, Sand W Registered Inputs
• External Clock Control
• Transparent Latched Outputs
• Internal Self-Timed Write Pulse Generation
• Separate I/O
• TTL-Compatible Input and Output
• High Output Drive Capability
• Produced with Advanced CEMOS ™ High-Performance
Technology
• low Power-Consumption and High Reliability
• Single 5 Volt Power Supply
• Military Product is Mll-STD-883, Class 8 Compliant
• Wide Variety of Packages Available
The IDT61592 is a 65,536-bit high-speed, synchronous static
RAM organized as 16K x 4. It features the input registers and transparent latched outputs needed for low chip-count cache data RAM
and writeable control store designs.
All inputs have positive-edge triggered, non-inverting registers
controlled by the external clock input (ClK), allowing precise cycle
control. When ClK is low, the device output becomes transparent,
permitting access to RAM data within the same cycle. When ClK is
high, the output data is latched.
The device features internally self-timed write operations, which
are triggered by the rising edge of the external clock input. This
eliminates the need for external write pulse generation and allows
greater flexibility for incoming signals.
The IDT61592 is fabricated using IDT's high-performance
CEMOS ™ technology, which features extremely low power consumption and high-reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
16Kx4
HIGH-SPEED
STATIC RAM
ROW
DECODERS
COLUMN I/O
~---OO
COLUMN
DECODERS
>--+---0 1
WRITE PULSE
GENERATOR
CLK--------------__--~~________~
OUTPUT
LATCHES
">--1---0 3
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated DevIce Technology, Inc.
JANUARY 1989
DSC-l051/-
S4-106
IDT61592S/IDT61592L CMOS SYNCHRONOUS
STATIC RAM WITH TRANSPARENT OUTPUTS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
As
Vcc
A4
A6
A7
A3
As
Ae
A 10
A2
Al
Ao
D3
D2
All
A12
A 13
03
O2
DO
Dl
01
00
W
'S"
ClK
GND
GND Q
DIP
TOP VIEW
TRUTH TABLE
s
w
Oo-~
l
l
Z
l
H
X
Data Out
H
Z
FUNCTION
Write
Read
Deselected
NOTE:
H = High, l = low, X = Don'teare, Z = High Impedance
54-107
t;J
IntegratedDevIce~]nc.
CMOS SYNCHRONOUS
STATIC RAM WITH
OUTPUT REGISTERS
64K (16K x 4-BIT)
ADVANCE
INFORMATION
lOT 615935
lOT 61593L
FEATURES:
DESCRIPTION:
• 16K x 4-8it Organization
• High-speed Cycle Time
- Commercial: 25ns
- Military: 30ns
• High-speed Clock Access Time
- Commercial: 10ns
- Military: 13ns
• Address, Data, Sand W Registered Inputs
• Registered Outputs
• Internal Self-Timed Write Pulse Generation
• Separate I/O
• TTL-Compatible Input and Output
• High Output Drive Capability
• Produced with Advanced CEMOS ™ High-Performance
Technology
• low Power-Consumption and High Reliability
• Single 5 Volt Power Supply
• Military Product is Mll-STD-883, Class 8 Compliant
The IDT61593 is a 65,536-bit high-speed, synchronous static
RAM organized as 16K x 4. It features the registered inputs and outputs needed for low chirrcount cache data RAM and writeable
control store designs.
All inputs have positive-edge triggered, non-inverting registers
controlled by the external clock input (ClK), allowing precise cycle
control. All outputs are also registered. At the rising edge of ClK,
the RAM data from the previous ClK high cycle is clocked into the
output registers. This feature is ideal in pipelined applications.
The device features internally self-timed write operations, which
are triggered by the rising edge of the external clock input. This
eliminates the need for external write pulse generation and allows
greater flexibility for incoming signals.
The IDT61593 is fabricated using IDT's high-performance
CEMOS ™ technology, which features extremely low power consumption and high-reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
ROW
DECODERS
16Kx4
HIGH-SPEED
STATIC RAM
DATA
COLUMN I/O
">----0 0
COLUMN
DECODERS
OUTPUT
REGISTER
CLK-----------t--~~~~~~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC-l052/-
S4-108
IDT61593S/IDT61593L CMOS SYNCHRONOUS
STATIC RAM WITH OUTPUT REGISTERS 64K (16Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
As
Vee
A4
Ae
A7
As
Ag
A 10
A3
A2
A1
AD
D3
D2
A11
A12
A 13
Q3
Q2
Q1
Qo
Do
D1
S
W
ClK
GND
GNDa
DIP
TOP VIEW
TRUTH TABLE (1)
s
W
00-0 3
FUNCTION
l
l
Z
Write
l
H
Data Out
Read
X
H
Z
Deselected
NOTE:
1. H = High, l = low, X = Don'tcare, Z = High Impedance
S4-109
~
Intesrated Device1echnobgy.1nc.
CMOS SYNCHRONOUS
STATIC RAM WI OUTPUT
REGISTERS AND OE
64K (16K x 4-BIT)
ADVANCE.
INFORMATION
lOT 615945
lOT 61594L
FEATURES:
DESCRIPTION:
• 16K x 4-Bit Organization
• High-speed Cycle Time
- Commercial: 25ns
- Military: 30ns
• High-speed Clock Access Time
- Commercial: 10ns
- Military: 13ns
• Address, Data and W Registered Inputs
• External Clock Control
• Registered Outputs
• Output Enable
• Internal Self-Timed Write Pulse Generation
• Separate I/O
• TTL-Compatible Input and Output
• High Output Drive Capability
• Produced with Advanced CEMOS ™ High-Performance
Technology
• Low Power-Consumption and High Reliability
• Single 5 Volt Power Supply
• Military Product is Mll-STD-883, Class B Compliant
• Wide Variety of Packages Available
The IDT61594 is a 65,536-bit high-speed, synchronous static
RAM organized as 16K x 4.ltfeatures the registered inputs and outputs needed for"low chip-countcache data RAM and writeable
control store designs.
All inputs have positive-edge triggered, non-inverting registers
controlled by the external clock input (ClK), allowing precise cycle
control. All outputs are also registered. At the rising edge of ClK,
the RAM data from the previous ClK high cycle is clocked into the
output registers. This feature is ideal in pipelined applications.
The output enable (OE) facilitates designs using asynchronous
bus control.
The device features internally self-timed write operations, which
are triggered by the rising edge of the external clock input. This
eliminates the need for external write pulse generation and allows
greater flexibility for incoming Signals.
The IDT61594 is fabricated using IDT's high-performance
CEMOS ™ technology, which features extremely low power consumption and high-reliability.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
16Kx 4
HIGH-SPEED
STATIC RAM
ROW
DECODERS
DATA
w
COLUMN I/O
WRITE
ENABLE
REGISTER
WRITE PULSE
CLK ____________~~--~--:G=EN~E~R~A~TO~R~
--------------------~
.>-----0 0
COLUMN
DECODERS
OUTPUT ENABLE
BUFFER
OUTPUT
REGISTERS
r-------------------------------------~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated DevIce Technology, Inc.
JANUARY 1989
DSC-1053/-
S4-110
IDT61594S/IDT61594l CMOS SYNCHRONOUS STATIC RAM
WITH OUTPUT REGISTERS AND OUTPUT ENABLE 64K (16K x 4-BI1)
PIN CONFIGURATION
Vee
A5
A6
A4
A7
A3
As
Ag
A 10
Al
Ao
A2
D3
D2
All
A12
A'3
03
Do
01
O2
01
00
OE:
elK
W
GND
GNDQ
DIP
TOP VIEW
TRUTH TABLE
W
Q O-Q3
FUNCTION
l
HighZ
Write
H
Data Out
Read
H = High. L = Low
S4-111
MILITARYANDCOMMERCIAl TEMPERATURE RANGES
t;)
Integrated Device lechnoIogy. Inc.
CMOS SYNCHRONOUS
STATIC RAM WI
TRANSPARENT OUTPUTS
AND OE 64K (16K X 4-BIT)
ADVANCE
INFORMATION
lOT 61595S
lOT 61595L
FEATURES:
DESCRIPTION:
• 16K x 4-Bit Organization
• High-speed Cycle Time
- Commercial: 25ns
- Military: 30ns
• Address, Data and W Registered Inputs
• Extemal Clock Control
• Transparent Latched Outputs
• Output Enable
• Internal Self-Timed Write Pulse Generation
The IDT61595 is a 65,536-bit high-speed, synchronous static
RAM organized as 16K x 4. It features the registered inputs and outputs needed for low chip-count cache data RAM and writeable
control store designs.
All inputs have positive-edge triggered, non-inverting registers
controlled by the external clock input (ClK) , allowing precise cycle
control. When ClK is low, the device output becomes transparent,
permitting access to RAM data within the same cycle. When ClK is
high, the output data is latched.
The output enable (OE) facilitates designs using asynchronous
bus control.
The device features intemally self-timed write operations, which
are triggered by the rising edge of the external clock input. This
eliminates the need for external write pulse generation and allows
greater flexibility for incoming signals.
The IDT61595 is fabricated using lOT's high-performance
CEMOS ™ technology, which features extremely low power consumption and high-reliability.
•
•
•
•
•
•
•
•
Separate I/O
TTL-Compatible Input and Output
High Output Drive Capability
Produced with Advanced CEMOS ™ High-Performance
Technology
low Power-Consumption and High Reliability
Single 5 Volt Power Supply
Military Product is Mll-STD-883, Class B Compliant
Wide Varietr of Packages Available
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
16Kx4
HIGH-SPEED
STATIC RAM
ROW
DECODERS
DATA
w
COLUMN I/O
WRITE
ENABLE
REGISTER
>----0 0
COLUMN
DECODERS
>--1---0 ,
WRITE PULSE·
OUTPUT
LATCHES
CLK ______________~--~~-G=E=N~E~R=A~TO=R~
____________________
~
OUTPUT ENABLE
BUFFER
~
__________________
~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Inlegrated Device Technology, Inc.
JANUARY 1989
OSC-l054/-
S4-112
IDT61595S/IDT61595LCMOS SYNCHRONOUS STATIC RAM WITH
TRANSPARENT OUTPUTS AND OUTPUT ENABLE 64K(16Kx4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
Vee
A4
A3
A2
Al
Ao
D3
O2
03
O2
01
00
As
A6
A7
As
A9
A 10
All
A12
A 13
Do
01
~
W
ClK
GND
GNOa
DIP
TOP VIEW
TRUTH TABLE
W
0 0 -03
FUNCTION
L
High Z
Write
H
Data Out
Read
H = High. l = low
S4-113
._--------
....._--_.-
._-_.._._- .._...__. _ - - - - - - - - - - - - - - -
--------
~
Integrated DevIce~Inc.
CMOS STATIC RAM WITH
LATCHED ADDRESSES
64K (16K x 4-BIT)
ADVANCE
INFORMATION
lOT 715985
lOT 71598L
FEATURES:
DESCRIPTION:
• High-Speed Address Access Time
- Military: 20/25/35ns
- Commercial: 15/20/25ns
• On-Board Address Latches
• Low-Power Consumption and High-Reliability
• Battery Back-Up Operation: 2-Volt Data Retention
(L Version Only)
• Produced with Advanced CEMOS ™ High-Performance
Technology
• Single 5V (±10%) Power Supply
• Input and Output Directly TIL Compatible
The 71598 is 65,536-bit high-speed static RAM organized as
16K x 4 with intemal address latches. It is fabricated using lOT's
high-performance, high-reliability CEMOS ™ technology.
Address access times as fast as 15ns are available with typical
power consumption of only 300mW. The 71598 excels in cache applications because of the on-chip address latches, which reduce
system part count. This device is the preferred solution with 64K
Byte Caches including the Intel 80386 and MIPS applications. The
low-power (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 10~W operating off a 2V battery.
.
All inputs and outputs of the 10171598 are TIL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
•
•
•
•
Three-State Output
Bidirectional Data Inputs and Outputs
Static Operation No Clocks or Refresh Required
Military Product Compliant to MIL-STD-883. Class B
FUNCTIONAL BLOCK DIAGRAM
64K-BIT
MEMORY
ARRAY
ALEN - - - - - - - - "
110 --------r"-~
110 -------.,r---t--~
INPUTI
OUTPUT
110 -----r---t--t---.t
I/O
----.----l---I--.j-~
~--~
R/W--~
~-----------------~
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
19a9 Integrated Devtce Technology. Inc.
JANUARY 1989
05C-l057/-
S4-114
t;J
Integrated Dev1ce1echnology.1nc.
PRELIMINARY
.IOT 612985
lOT 61298L
CMOS STATIC RAM
256K (64K x 4-BIT)
FEATURES:
DESCRIPTION:
• Fast Output Enable (OE) pin available for added system
flexibility
The IDT61298 is a 262,144-bit high-speed static RAM organized
as 64K x 4. It is fabricated using IDT's high-performance, high-reliability technology-CEMOS. This' state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory intensive applications.
The IDT61298 features two memory control functions: Chip
Select (CS) and Output Enable (OE). These two functions greatly
enhance the IDT61298's overall flexibility in high-speed memory
applications.
Access times as fast as 20ns are available with typical power
consumption of only 350mW. The IDT61298 offers a reduced
power standby mode, 1591, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly
enhancing system reliability. The low-power (L) version also offers
a battery backup data retention capability where thecircuittypically consumes only 100~W when operating from a 2V battery.
All inputs and outputs are TTL-compatible and the device operates from a single 5 volt supply. Fully static asynchronous circuitry, .
along with matching access and cycle times, favor the simplified
system design approach.
The IDT61298 is packaged in a 28-pin sidebraze or plastic
300mil DIP plus an SOIC, providing improved board-level packing
densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
• High speed (equal access and cycle times)
- Military: 25/35/45/55/70ns (max.)
- Commercial: 20/25/35/45/55ns (max.)
• Low power consumption
- IDT61298S
Active: 400mW (typ.)
Standby: 400~w (typ.)
- IDT61298L
Active: 350mW (typ.)
Standby:
100~w
(typ.)
• Battery back-up operation-2V data retention (L version only)
• JEDEC standard pinout
• 28-pin DIP
• Produced with advanced CEMOS ™ technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
A
GND
DECODER
262,144- BIT
MEMORY ARRAY
A
I/O
COLUMN I/O
I/O
I/O
I/O
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
oSC-1006/1
S4-115
IDT61298S/IDT61298L CMOS STATIC RAM 256K (64K x 4-81T)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
LOGIC SYMBOL
NC
Ao
Vee
Al
Ao
Al
A2
A1S
A2
A14
A 13
A3
A12
A4
All
A 10
NC
As
A6
A7
A3
A4
As
A6
A7
A6
A9
A 10
A11
A12
A 13
A14
A 1S
NC
A6
A9
1/04
CS
1/0z
1/0:3
~
I/~
GND
WE
II~
DIP
TOP VIEW
CS
PIN NAMES
Ao-A 1S
Address Inputs
1101-4
CS
Chip Select
\be
Power
WE
Write Enable
GND
Ground
OE
Output Enable
Data Input/Output
S4-116
1I0z
110:3
1104
~
WE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT61298S/IOT61298L CMOS STATIC RAM 256K (64Kx 4-BIT)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
V
Operating
Temperature
Oto +70
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
TA
-55 to +125
SYMBOL
°C
PARAMETER
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
UNIT
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Military
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL
PARAMETER
TEST CONDITIONS
Ilu l
Input Leakage Current
Vee = Max.• VIN
IILol
Output Leakage Current
Vee
~
VOL
Output Low Voltage
, VOH
Output High Voltage
= GND to Vee
= Max.
= VIH • VOUT = GND to Vee
10L = 10mA. Vee = Min.
10L = 8mA. Vee = Min.
10L = -4mA, Vee = Min.
MIN.
MIL.
COM·L.
MIL.
COM'L.
NOTE:
1. Typical limits are at Vee = 5.0V, +25°C ambient.
S4-117
-
-
IOT61298S
TYP,kXJ-.I-=-=-_~==t~
-r
=
j::=%
TIMING WAVEFORM OF READ CYCLE NO.3 (1, 3, 4)
tCHZ (5)
~--_
DATA OUT
Vcc
SUPPLY
CURRENT
Icc
________
~~~~t~~
ISB
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V1L •
3. Address valid prior to or coincident with ~ transition low.
4. DE"
= \'IL
5. Transition is measured ±200mV from steady state.
S4-121
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT61298S/IDT61298L CMOS STATIC RAM 256K (64K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBO
PARAMETER
(VCC = 5V ±10%, All Temperature Ranges)
61298S20(1) 61298S25 (4)
61298L20(1) 61298L25 (4)
MIN.
MAX. MIN.
MAX.
61298S35
61298L35
MIN. MAX.
61298S45
61298L45
MIN.
MAX.
61298S55
61298L55
MAX.
MIN.
61298S70(2)
61298L70 (2) UNIT
MIN.
MAX.
WRITE CYCLE
0
-
13
-
13
-
15
-
20
-
25
-
30
ns
-
15
20
-
25
0
-
0
0
5
-
5
5
-
5
-
5
-
5
-
ns
0
-
35
-
-
30
0
-.
-
twc
Write Cycle Time
20
-
20
tcw
Chip Select to End of Write
20
-
20
tAW
t AS
Address Valid to End of Write
20
20
Address Set-up Time
0
twp
Write Pulse Width
20
tWR
Write Recovery Time
0
-
tWHZ (3)
Write Enable to Output In High Z
-
tow
Data Valid to End of Write
15
tOH
Data Hold Time
Output Active from End of Write
tow
(3)
0
20
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested. .
4. Preliminary data for military devices only.
S4-122
30
-
40
30
40
30
-
0
-
0
-
30
0
40
0
40
50
-
60
-
ns
50
-
60
-
ns
50
60
60
0
-
0
-
ns
50
-
ns
0
0
0
ns
ns
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT61298S/IDT61298L CMOS STATIC RAM 256K (64Kx 4-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CON.TROLLED TIMING) (1,2,3,7)
twc
ADDRESS.
~
-.I
)(
KtAW
~
i\.
~tAS
twp
tWR
(7)
~"
"
-
-tWHZ(6)tow
' · ( 4 ) } •.••)),..
(4)
DATA OUT
.1..
DATA IN
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)
(1,2,3,5)
twc
ADDRESS
==> (
f4- t AS
)(
tAW
-
~V
'~
tcw
____________________________________
tWR
-
K~-t-ow------.-I.-----tO-H-~~-------------
NOTES:
1.
2.
3.
4.
5.
WE or CS must be high during all address transitions.
wr=..
A write occurs during the overlap (tcw or twp ) of a low CS and a low
tWR is measured from the earlier of CS or
going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CS low transition occurs simultaneously with or after the
low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
7. IfOi:' is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (WHZ+ tow) to allow the I/O drivers to tum off and data to be
placed on the bus for the required t ow. If Oi: is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twp .
wr=.
wr=.
S4-123
IDT61298S/IDT61298LCMOS STATIC RAM 256K(64Kx4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
SYMBOL
(TA= +25°C. f = 1.0MHz)
PARAM ETER (1)
MODE
CS
WE
OE
I/O
POWER
Standby
H
X
X
HighZ
Standby
CIN
Input Capacitance
Read
L
H
L
DOUT
Active
COUT
Output Capacitance
Write
L
L
X
DIN
Active
Read
L
H
H
HighZ
Active
CONDITIONS
MAX.
\IN = OV
11
pF
VOUT= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
ORDERING INFORMATION
lOT
61298
Device Type
999
Speed
A
A
Package
Process/
Temperature
Range
Y:,onk
C
P
V
20
25
'--------------i
~
UNIT
______________
~
~---------------------1
S4-124
35
45
55
70
S
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant with MIL-STO-883. Class B
Sidebraze DIP
Plastic DIP
Small Outline IC (J-8end)
Commercial Only )
Speed in Nanoseconds
Military Only
L
Standard Power
Low Power
61298
64Kx 4-Bit
~
CMOS STATIC RAM
256K (64K x 4-BIT)
Integrated Device~lnc.
PRELIMINARY
lOT 71258S
lOT 71258L
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
- Military: 25/35/45/55/70ns (max.)
- Commercial: 20/25/35/45/55/ns (max.)
The IDT71258 is a 262,144-bit high-speed static RAM organized
as 64K x 4. It is fabricated using IDT's high-performance, high-reliability CEMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a costeffective alternative to bipolar and fast NMOS memories.
Access times as fast as 20ns are available with typical power
consumption of only 350mW. The IDT71258 offers a reduced
power standby mode, IS91, which enables the designer to greatly
reduce device power requirements. This capability provides significant system level power and cooling savings. The low-power
(L) version also offers a battery backup data retention capability
where the circuit typically consumes only 100}JW operation off a
2V battery.
All inputs and outputs of the IDT71258 are TIL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The IDT71258 is packaged in a 24-pin 300 mil DIP, a 24-pin
SOIC (gull-wing or J-Bend), a 28-pin Lee, and a 24-pin Cerpack
providing high board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
• Low-power operation
-IDT71258S
Active: 400mW (typ.)
Standby: 400}JW (typ.)
- IDT71258L
Active: 350mW (typ.)
Standby: 100}JW (typ.)
• Battery backup operation-2V data retention (L version only)
• Produced with advanced CEMOS ™ high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TIL-compatible
• Static operation: no clocks or refresh required
• Available in high-density industry standard 24-pin, 300 mil DIP,
24-pin SOIC (gull-wing and J-Bend), 28-pin LCC, and a 24~pin
Cerpack
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATION
Ao
Vcc
Al
A15
A14
A13
A2
A3
A4
A5
FUNCTIONAL BLOCK DIAGRAM
Ao
As
A7
As
DECODER
ADDRESSES
A12
All
Al0
1/0 4
Vcc
262,144-BIT
GND
MEMORY ARRAY
{
A15
1/0 3
A9
1/0 2
1/0 1
cs
INPUT
DATA
CONTROL
WE
GND
DIP/SOIC/CERPACK
TOP VIEW
PIN NAMES
Ao - A15
Addresses
1/0 1 - 1/04
Data Input/Output
CS
Chip Select
WE
Write Enable
GND
Ground
Vee
Power
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-l017/-
S4-125
91
~
I DT71258S/1 DT71258L CMOS
STATIC RAM 256K (64K x 4·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
LOGIC SYMBOL
GRADE
Ao
Al
A2
A3
A4
A5
A6
A7
As
Ag
A 10
All
A12
A 13
A14
A 15
Military
1/0 1
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Commercial
Vee
1/0 2
1/0 3
ABSOLUTE MAXIMUM RATINGS
1/0 4
~
SYMBOL
WE
C(.f~:»~
INDEX
I
I
I
"
...........
I
I
I
I
I
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TelAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTo
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
I
...........
3 2 L.l 28 27
1
RATING
A15
A14
A13
A12
L28-2
13 14 15 16 17
All
A10
RECOMMENDED DC OPERATING CONDITIONS
1/0 4
1/0 3
1/0 2
SYMBOL
nnnnn
Za Z : :,
OQO~6
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
-
6.0
V
-
0.8
V
Input Low Voltage
2.2
-0.5(1)
UNIT
NOTE:
1. VIL = -3.0V for pulse width less than 2Ons.
DC ELECTRICAL CHARACTERISTICS.
Vce = 5.0V ±10%
SYMBOL
PARAMETER
IDT71258S
MIN.
MAX.
TEST CONDITIONS
10
5
10
5
IOL = SmA, Vee = Min.
-
0.4
-
0.4
V
IOL = 10mA, Vee = Min.
-
0.5
-
0.5
V
IOH = -4mA, Vee = Min.
2.4
-
2.4
-
V
lIu l
Input Leakage Current
Vee = Max., VIN = GND to Vee
IILol
Output Leakage Current
Vee= Max.
CS = '-'IH' VOUT = GND to Vee
MIL.
COM'L.
Output Low Voltage
VOH
Output High Voltage
UNIT
-
MIL.
COM'L.
VOL
1DT71258L
MIN.
MAX.
S4-126
-
5
2
J.LA
-
5
2
J.LA
-
----------------------------IDT712585/1DT71258L CMOS
STATIC RAM 256K (64K x 4-BI1)
MILITARY AND COMMERCIAL TEMPERATURE RANGE5
DC ELECTRICAL CHARACTERISTICS(1)
PARAMETER
SYMBOL
POWER
rlcc = 5V ±10%, VLC = 0.2V, VHC = vcc - 0.2V)
FUNCTION
71258520
71258L20
71258525(4) 71258535
71258L2S(4) 71258L35
71258S45
71258L45
71258555
71258L55
71258570
71258L70
UNIT
COM'LMIL. COM'LMIL COM'LMIL COM'LMIL. COM'LMI~ COM'LMIL
ICCI
Icc2
ISB
ISBI
Operating Power
Supply. Current
CS = VIL,
Outputs Open,
Vcc = Max., f = 0(3)
S
L
Dynamic Operating
Current
CS = VIL,
Outputs Open.
Vcc = Max., f = f MAX (3)
S
L
READ
60
-
60
60
50
60
50
60
50
60
-
WRIT82)
110
-
110
110
100
110
100
110
100
110
110
READ
40
40
40
30
40
30
40
30
40
-
WRIT82)
160
-
READ
140
-
140
WRITE(2)
140
-
140
140
130
140
130
140
130
140
-
-
35
-
35
35
35
35
35
35
35
35
-
WRITS2)
100
READ
160
·60
mA
40
100
100
90
100
90
100
90
100
160
160
150
160
150
160
150
160
160
160
150
160
150
160
150
160
-
160
140
130
140
130
140
130
140
140
35
100
160
mA
140
Standby Power
Supply Current
(TTL Level)
S
CS ~VIH'
Vcc = Max., Outputs
Open f = fMAX (3)
L
-
20
-
20
20
20
20
20
20
20
20
-
20
Full Standby Power
Supply Current
(CMOS Level)
S
-
30
-
30
35
30
35
30
35
30
35
-
35
mA
mA
CS ~VHC' Vcc= Max.,
f = 0(3)
-
L
-
1.5
1.5
4.5
1.5
4.5
1.5
4.5
1.5
4.5
-
4.5
NOTES:
1. All values are maximum guaranteed values ..
2. Write cycle current specifications are included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
read cycles to write cycles is extremely high. When comparing these figures to those on other data sheets, we recommend that the read cycle data is used
(especially where "Average" current consumption figures are specified).
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of ItRc, f = 0 means no input lines change.
4. Preliminary data for military devices only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
CIN
Cour
CONDITIONS
Input Capacitance
Output Capacitance
MAX.
VIN = OV
11
Vour= OV
11
NM~
1.
UNIT
pF
)
I
pF
This parameter is determined by device characterization but is but production tested.
TRUTH TABLE (VLC = 0.2V, VHC = VCC - 0.2V)
WE
CS
1/0
MODE
X
H
Hi-Z
Standby (ISB)
Standby (ISB1)
X
V HC
Hi-Z
H
L
Dour
Read
L
L
DIN
Write
NOTE:
1.
H = "IH' L
= VIL' X = DON'T CARE
54-127
- - - _.. _...
__ __
.
.... _----_.
__._--
__._--------.__
.
..
_-----
._...
_-_..._--_.__.._ - - - - -
IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 02V VHC = Vcc - 02V
SYMBOL
VDR
ICCDR
MIN.
TEST CONDITIONS
PARAMETER
-
Vcc for Data Retention
Data Retention Current
t CDR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
CS ~VHC
I
I
TVP.(1)
Vee @
3.0V
2.0V
1.
-
-
-
-
MIL.
-
50
75
2000
3000
COM'L.
-
50
75
500
750
0
-
-
-
-
ns
-
ns
t RC (2)
TA = +25°C
t RC = Read Cycle Time
This parameter is guaranteed but not tested.
LOW Vce DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
4.5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
Sns
1.SV
1.SV
See Figures 1 & 2
SV
DATA OUT
~
2S5O
:q
SV
480n
DATA OUT
30pF*
2S5O
480n
SpF*
Figure 2. Output Load
(for tOUt tcu. toHz.
tWHZ, tCHZ.
Figure 1. Output Load
tow
*Including scope and jig.
S4-128
UNIT
2.0
NOTES:
2.
3.
MAX.
Vee @
2.0V
3.0V
V
J.LA
1DT71258S/IDT71258L CMOS
STATIC RAM 256K (64Kx 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Vcc = 5V ±10%, All Temperature Ranges
71258S20(1) 71258S25
71258S35
71258L20(1)
71258L35
71258L25
MAX. MIN. MAX. MIN. MAX.
MIN.
71258S70(2)
71258S45
71258S55
71258L70 (2)
71258L45
71258L55
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
20
-
25
-
35
-
45
-
55
-
70
-
ns
tAA
Address Access Time
-
20
25
ns
45
-
70
20
-
55
-
-
45
Chip Select Access Time
-
35
t Acs
-
70
ns
tCLZ
Chip Select to Output in Low Z (3)
5
5
5
-
5
-
5
5
-
0
0
-
ns
0
-
35
-
45
55
-
70
ns
15
-
20
-
25
-
30
ns
-
5
-
5
-
5
-
ns
25
t pu
Chip Select to Power Up Time(3)
0
-
0
-
t pD
Chip Deselect to Power Down Time(3)
-
20
-
25
tCHZ
Chip Deselect to Output in High Z(3)
-
10
-
13
-
tOH
Output Hold from Address Change
5
-
5
-
5
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed, but not tested.
S4-129
0
35
55
ns
1DT71258S/IDT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
I-----------
ADDRESS
~
tRc
----------t~
.
~--~-~----~---------------------tAA-----------------.-I--~------
~----- tACS ' - - - - - - . 1
~---- t CLZ (4) ----:--~
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
(1,2)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.3 (1,3)
DATA OUT
NOTES:
1.
2.
3.
4.
~ is high for read cycle.
Device is continuously selected. ~ = '-'JL'
Address valid prior to or coincident with CS transition low.
Transition is measured ±200mV from steady state with 5pF load (including scope and jig).
S4-130
--to-H--------~---
1DT71258S/IDT71258L CMOS
STATIC RAM 256K (64Kx 4.BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBO
Vee = 5V ±10%, All Temperature Ranges
71258S20 (1) 71258S25
71258S35
71258L20 (1) 71258L25
71258L35
MIN.
MAX. MIN. MAX. MIN. MAX.
PARAMETER
71258S70 (2)
71258S45
71258S55
71258L70 (2)
71258L45
71258L55
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
WRITE CYCLE
twc
Write Cycle Time
20
-
20
-
30
-
40
tcw
Chip Select to End of Write
20
-
20
-
30
-
40
tAW
Address Valid to End of Write
20
20
-
30
-
40
t AS
Address Set·up Time
0
0
-
0
-
0
twp
Write Pulse Width
20
-
20
-
30
-
40
tWR
Write Recovery Time
0
-
0
-
0
-
0
-
tWHZ
Write Enable to Output in High Z (3)
-
13
-
13
-
15
-
-
20
-
25
0
-
0
tDW
Data Valid to End of Write
15
-
15
tDH
Data Hold Time
0
0
tow
Output Active from End of Write (3)
5
-
5
5
5
0
-
20
-
-
0
-
25
-
30
ns
30
-
35
0
-
0
-
ns
5
-
5
-
ns
50
50
50
0
50
60
60
60
0
60
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. OOC to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed, but not tested.
S4-131
- - - - _ . _ - - - - - - - - - - - - - - - - - - - - - - - - - - - _..._--_ .•...
IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64K X 4-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3,1I)
~--------------~--------twe----------------------~
ADDRESS
_____________________________)~____________
~K
......- - - - - - - - - tAW -----------------~
---+--
/'t'
'-------------------------------------+-----,
I-- t
t AS --~----------- twp
-------------..j
WR -
~~
/V
'-----------------~
I--- tWHZ ( 6 ) _
~---tow ---~
DATA OUT
-----------<~<
.. . . . . . . . . _
. . . . . . . . . (~).)
"i~:l·----------------+-----------IC~""'.:._.__(~)
-------+- Y
L-t--+----iH >- Y
L-t--H>-Y
"---H>-Y
WE
L. _ _ _ _ _ _ _ _ _ _ .l
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology, Inc.
JANUARY 1989
OSC-l01811
S4-134
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71281/IDT71282 CMOS STATIC RAM 256K (64Kx 4-BIT)
PIN NAMES
PIN CONFIGURATIONS
Ao
AI
Vee
A1S
A2
A3
A4
A14
A13
A12
As
Ae
A7
As
A9
All
A10
04
Ao-AIS
Address Inputs
CS
Chip Select
WE
Write Enable
Vee
Power
0 1 -04
Y1 -Y4
GND
DATA IN
DATA OUT
Ground
LOGIC SYMBOL
03
Y4
Y3
Y2
01
O2
CS
Y1
wr=.
GND
DIP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
.. RATING
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
-0.5 to +7.0
-0.5 to +7.0
-55 to +125
SYMBOL
V
°C
MIN.
TYP.
MAX.
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
UNIT
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 2Ons.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
S4-135
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71281{IDT71282 CMOS STATIC RAMS 256K (64K x 4-BIT)
DC ELECTRICAL CHARACTERISTICS (for all speeds)
Vcc = 50V +10%
SYMBOL
TEST CONDITION
PARAMETER
MIN.
IDT71281/2S
TYP,
~~
I
L32-1
Aa
A9
nnnnnnn
"'0
g'" ga
DIP/SOle
TOP VIEW
()
z
000
:::::::::::::::::-
LCC
TOP VIEW
CAPACITANCE
SYMBOL
PIN NAMES
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
MAX.
UNIT
VIN = OV
8
pF
VOUT= OV
8
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
OE'
Output Enable
Data Input/Output
RESEj"(l)
Memory Reset
CS1, CS2
Chip Select
GND
Ground
~
Write Enable
\be
Power
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect to
GND(2)
TA
Operating
Temperature
Oto +70
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
DC
TSTG
Storage
Temperature
-55 to +125
-65 to +150
DC
-0.5 to +7.0
Address
I/Ol-I/Oa
NOTE.
1. A 1KCl pull-up resistor on the "RESET input is required for added
noise immunity.
(1)
COMMERCIAL
Ao - A12
-0.5 to +7.0
-55 to +125
SYMBOL
V
DC
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All inputs and Vce pin. Data pins I/O, - I/Oa must not be taken above
Vee + 1.0V.
MIN.
TYP.
MAX.
UNIT
Vce
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
"'H
Input High Voltage
70% of vee
-
5.5(2)
V
Input Low Voltage
-0.5(1)
-
30% of vee
V
"'L
NOTES:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. If VIH = 5.5V, Vcc = 4.5V, there is risk of latch up.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
S4-173
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V
± 10%
O°Cto +70 0 C
OV
5.0V
± 10%
Vee
IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K(SKx a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±100/0
SYMBOL
TEST CONDITIONS
PARAMETER
MIN.
lIu l
Input Leakage Current
Vee = Max., VIN = GND to Vee
MIL.
COM'L.
IILol
Output Leakage Current
Vee= Max.
~1= \1H, VOUT = GND to Vee
MIL.
COM'L.
VOL
Output Low Voltage
10L = BmA, Vee = Min.
MIL.
IOL = 10mA, Vee = Min.
COM'L.
Output High Voltage
-
10
5
-
0.44
4.4
10
5
0.5
IOH = -6mA, Vee = 4.5V
COM'L.
3.7
-
IOH = -6mA,Vee= 4.5V
MIL.
3.B
-
IOH = -50pA, Vee = 4.5V
VOH
IDT71C65S
IDT71C65L
MAX. MIN.
MAX.
-
UNIT
5
2
J.1A
5
2
J.1A
0.44
V
0.5
V
3.7
-
V
3.B
-
V
4.4
V
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±100/0, VLe = 0.2V, VHe = Vec -0.2V, VIH = Vee-0.8V, \1L = 0.8V
SYMBOL
PARAMETER
POWER
IDT71C65S30
IDT71 C65L30
COM'L
MIL
IDT71C65S55
IDT71C65S35
IDT71C65S45
IDT71C65L5S
IDT71C65L35
IDT71C65L45
COM'L
MIL COM'L
MIL COM'L
MIL
170
20
-
3
5
-
5
20
15
20
-
20
1
0.2
1
-
1
leel (2)
Operating Power Supply Current
Vec = Max., f = 0(3)
S
95
-
95
105
95
105
L
85
85
95
85
95
ICC2 (2)
Dynamic Operating Current
Outputs Open, Vee = Max., f = f MAX (3)
S
160
-
160
170
160
170
L
135
-
125
135
115
125
Standby Power Supply Current
1) CS2S\1L,and~~\1H,f = f MAX (3)
2) ~1 ~ \1H,VCC = Max., Outputs Open,
CS2 ~ "'H' f = f MAX(3), ~ ~ \1H
S
20
-
20
20
20
ISB
L
3
-
3
5
S
15
-
15
L
0.2
-
0.2
ISBl
Full Standby Power Supply Current
1) CS 2 SVLC , ~~VHC, f = 0(3)
2) ~1 ~VHC' CS2 ~VHC' ~ ~ VHC
f = 0(3)
105
UNIT
mA
95
mA
120
20
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. CS 2 = \1H , ~1 = \1L
3. At fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1ltRC • f = 0 means no input lines change.
S4-174
IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (SK X S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V. VHC = Vcc - 0.2V
·TYP,<1)
SYMBOL
VOR
ICCOR
TEST CONDITION
PARAMETER
-
Vcc for Data Retention
Data Retention Current
tCOR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Ilul
Input Leakage Current(3)
1) l1ESET>'vI
- HC. CS 1 >'vI
- HC·
CS 2 ~ VHC
2) CS2 :5VLC ' ~~ VHC
Vee@
2.0V
3.0V
MIN.
I MIL.
I COM'L.
MAX.
Vee @
2.0V
3.0V
2.0
-
-
-
-
-
10
15
200
300
10
15
60
90
-
-
ns
-
ns
0
-
-
t RC (2)
-
-
-
-
NOTES:
1.TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
4. During data retention all 1/0 pins have to be :5 VLC or ~ VHC but :5 VCC.
LOW Vce DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vec
CS 1
VOR ;::: 2V
rJr)~~r)~~--,-______~V~O~R________-J
AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA OUT
GND toVcc
5ns
2.5V
2.5V
See Figures 1 and 2
----'1
DATAoUT - - - . . ,
130
1 5PF*
PF*
I
Figure 1. Output Load
Figure 2. Output Load
(for t CLZt • t CLZ2 • t oLZ • t CHZt • t CHZ2•
tOHZ. tOW,tWHV
* Including scope and jig.
S4-175
UNIT
2
V
v. A
v.A
IDT71 C65S/lDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SK x S.BIT)
AC ELECTRICAL CHARACTERISTICS (\bc
= 5V ±10%, All Temperature Ranges)
IDT71 C65S30(1)
I DT71 C65L30(1)
MIN.
MAX.
PARAMETER
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT71 C65S35
1DT71 C65L35
MIN.
MAX.
1DT71 C65S45
IDT71C65L45
MIN.
MAX.
I DT71 C65S55(4)
1DT71 C65L55(4)
MIN.
MAX.
UNIT
READ CYCLE
t AC
Read Cycle Time
30
-
35
-
45
-
55
-
tAA
Address Access Time
-
30
35
-
55
ns
Chip Select 1 Access Time (2)
20
35
-
40
ns
t ACS2
Chip Select 2 Access Time (2)
-
35
40
-
45
t ACS1
-
45
-
55
ns
tCLZl
Chip Select 1 to Output in Low Z
(3)
0
-
0
-
0
-
0
ns
tClZ2
Chip Select 2 to Output in Low Z
(3)
5
-
5
-
5
-
5
-
tOE
Output Enable to Output Valid
-
20
-
25
-
35
-
40
ns
toLZ
Output Enable to Output in Low
Z (3)
0
-
0
-
0
-
0
-
ns
t CHZ1
Chip Select 1 to Output in High
Z (3)
-
15
-
20
-
30
ns
Chip Select 2 to Output in High
Z (3)
-
15
-
20
25
-
30
ns
tOHZ
Output Disable to Output in High
-
15
-
20
-
25
tCHZ2
25
-
30
ns
tOH
Output Hold from Address Change
5
5
-
5
0
0
0
-
0
-
ns
Chip Select to Power Up Time (3)
-
5
t pu
-
tpD
Chip Deselect to Power Down Time(3)
-
30
-
35
-
45
-
55
ns
Z(3)
NOTES:
1. OOC to + 70°C temperature range only.
2. Both chip selects must be active for the device to be selected.
3. This parameter is guaranteed but not tested.
4. -55°C to +125°C temperature range only.
S4-176
25
ns
ns
ns
IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SKx S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (1)
ADDRESS
~
tRC
------------l~
____________________________________________
1oo~1--------- tAA
.. '
1 4 - - - - - tOE
~'-J;,..-'_
~
. . . - - - - - - t ACS2
----1~
---I-----.,.j
1 4 - - - - - t ClZ2 ( 5 ) - - - - - . , . j
cs,
1+------- t ACS ,
14-----
----\----.(
tCLZl (5) _ _ _--.,.j
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
~DRE~ ~=~-tAA-tRC1-'"_1- tOH~
-~------ ---->k..-j'><>d< '~ ~
tOH
DATA ",
o
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
CS,
tCHZ2 (5)
DATA OUT
CURRENT
Icc
-------
ISB
NOTES:
1.
is High for Read Cycle.
2. Device is continuously selected, CS, = V1L• CS 2 = V1H •
3. Address valid prior to or coincident with CS 1 transition low and CS 2 transition high.
wr=.
4.
OE:
=
\IL
5. Transition is measured ±200mV from steady state.
S4-177
IDT71 C65S/lDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (8K X 8-BIT)
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vee = 5V ±10%. All Temperature Ranges)
IOT71 C65S30 (1)
IDT71 C65L30 (1)
MAX.
MIN.
IDT71C65S35
IDT71C65L35
MAX.
MIN.
IDT71C65S45
1OT71C65L45
MIN.
MAX.
I DT71 C65S55 (2)
1OT71 C65L55 (2)
MIN.
MAX.
UNIT
WRITE CYCLE
twe
Write Cycle Time
30
tCWl
Chip Select 1 to End of Write
20
tCW2
Chip Select 2 to End of Write
25
-
35
-
45
20
25
30
-
-
55
-
30
50
0
-
40
-
50
ns
tAW
Address Valid to End of Write
25
t AS
Address Set-up Time
0
-
twp
Write Pulse Width
25
-
30
tWRl
Write Recovery Time (CS 1. M)
0
0
0
0
0
-
0
Write Recovery Time (CS 2)
-
0
t wR2 .
-
-
0
-
ns
tWHZ
Write Enable to Output In High Z (3)
-
10
-
12
-
15
-
20
ns
tow
Data to Write Time Overlap
15
18
0
tOH2
Data Hold From Write Time (CS 2)
5
-
5
5
-
5
tow
Output Active from End of Write (3)
5
-
5
-
5
-
5
-
ns
0
-
30
Data Hold From Write Time (CS1 • M)
-
25
tOHl
-
.
30
0
0
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
S4-178
-
40
40
50
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1DT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (SK X S-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1(1)
~-----------------twc------------------~
ADDRESS
CS 1
DATA OUT
TIMING WAVEFORM OF WRITE CYCLE NO.
2(1.6)
~----------------twc----------------~
ADDRESS
1--.
1 4 - - - - tcw ------....
CS 1
DATAoUT
NOTES:
1. WE or CS 1• or CS 2 must be inactive during all address transi~ions.
2. A write occurs during the overlap (twFl of a low WE. a low CS 1 and a high CS 2 .
3. t WR1 •2 is measured from the earlier of CS1 or WE going high or CS 2 going low to the end of write cycle.
4. During this period. I/O pins are in the output state so that the input signals must not be applied.
5. If the CSl low transition or CS2 high transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high
impedance state.
6. <51:" is continuously low (OE = "'d.
7. DATAouT is the same phase of write data of this write cycle.
8. If CSl is low and CS 2 is high during this period, I/O pins are in the output state. Data input signals must not be applied.
9. Transition is measured ±200mV from steady state.
S4-179
IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (SK X S-BIT)
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ±10%, All Temperature Ranges)
IIDT71C65S30(1) I IDT71C65S35 I
IDT71C65S45
IIDT71C65S55(2) I
IDT71C65L30(1)
IDT71C65L35
IDT71C65L45
IDT71C65L55(2)
MIN.
MAX. MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
PARAMETER
SYMBOL I
MILITARY AND COMMERCIAL TEMPERATURE RANGES
UNIT
~(3)
t RSPW
t RSR
I
I
~ Pulse Width(4)
I
I
~Highto~Low
- I
- I
55
5
- I
- I
65
5
80
10
- I
- I
100
10
- I
- I
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°Cto + 125°C temperature range only.
3. A 1KCl pull-up resistor to Vcc on the RESrr pin is required for added noise immunity.
4. Maximum 10% duty cycle applies.
RESET TIMING
~)oII-------- tRSPW-------}~
·r~~~~"~j __
~
XXXXXXXXXXXXXXXXXXXXY
ORDERING INFORMATION
lOT
xxxx
Device Type
A
Power
999
Speed
A
A
Package
Process!
Temperature
Range
y:'Mk
P
L -_ _ _~_______
-
SO
30
Commercial onlY}
~~
55
L----------------------i SL
'---------------------------------1 71C65
S4-180
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze THINDIP
Leadless Chip Carrier
Small Outline IC
TC
iL
L--_ _ _ _ _ _ _ _ _ _ _~
+ 70°C)
Commercial (O°C to
Speed in Nanoseconds
Military Only
Standard Power
Low Power
64K (SK x 8-Bit) CMOS I/O Resettable RAM
ns
ns
IntesratedDevice~Inc.
CMOS STATIC RAM
64K (8K x 8-BIT)
CACHE-TAG RAM
lOT 71745
FEATURES:
DESCRIPTION:
• High-speed address to MATCH comparison time
- Military: 25/35/45/55ns (max.)
- Commercial: 20/25/35/45ns (max.)
• High-speed address access time
- Military: 25/35/45/55ns (max.)
- Commercial: 20/25/35/45ns (max.)
• High-speed chip select access time
- Military: 15/20/25/30ns (max.)
- Commercial: 10/15/20/25ns (max.)
• Low-power operation
- IDT7174S
Active: 300mW (typ.)
• High-speed asynchronous RAM Clear on Pin 1
(Reset Cycle Time = 2 x tAA)
• MATCH Output on Pin 26
• Produced with advanced CEMOS ™ high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Standard 28-pin DIP (600 mil and 300 mil), 28-pin SOIC (gullwing or J-bend), 32-pin LCC and PLCC
• Military product compliant to MIL-STD-883, Class B
The IDT7174 is a high-speed cache address comparator subsystem consisting of a 65,536-bit static RAM organized as 8K x 8
and an 8-bit comparator. A single IDT7174 can map 8K cache
words into a 1 megabyte address space by comparing 20 bits of
address organized as 13 word cache address bits and 7 upper
address bits. Two IDT7174s can be combined to provide 28 bits of
address comparison, etc. The IDT7174 also provides a single RAM
clear control, which clears all words in the internal RAM to zero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The I DT7174 can also be used as an 8K x 8
high-speed static RAM.
The IDT7174 is fabricated using lOT's high-performance, highreliability technology-CEMOS. Address access times as fast as
20ns, chip select times of 10ns and address-to-comparison times
of 20ns are available with maximum power consumption of
825mW.
All inputs and outputs of the IDT7174 are TTL-compatible and
the device operates from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for
operation.
The IDT7174 is packaged in a 28-pin DIP (600 mil and 300 mil), a
28-pin SOIC (gull-wing or J-bend) and 32-pin LCC and PLCC, providing high board level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
ROW
CENTER
256
x 256
MEMORY ARRAY
A
RESET - - - - - - - - - 0 >-------~
I/O ......----""7------1
WE
MATCH (OPEN DRAIN)
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
OSC-1040/-1
1989 Integrated Device Technology. Inc.
S4-181
91
~
1DT7174S CMOS STATIC RAM
64K (SK x S-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
G
81 w t:
I
INDEX~ ~....«.-......«.-.....a:..-..Z.........>.......3.......,.....
::E.--.
Iii
~
Vcc
A12
A7
Ae
A5
A4
A3
A2
Al
Aa
WE
... ~ ~ u
MATCH
Ae
A9
All
LJUU;;UUU
30
29 [:
A6
26 [
A9
AlO
] 7
27 [:
All
OS
]6
I/0e
]9
I/O e
]10
1/0 7
1/05
1/04
GND
32 31
] e
OE
1/0 1
1/02
1/03
3 2 U
4
]
5
1
J32-1
&
L32-1
] 11
] 12
] 13
14 15 le
DIP/SOIC
TOP VIEW
17
16 19
26 [:
NC
25[:
m:,
24 [:
23 [
OS
22 [
'21 [
1/06
1/07
Ala
20
nnnnnnn
LOGIC SYMBOL
Aa
Al
A2
A3
A4
A5
Ae
A7
Ae
A9
Ala
All
A12
LCC/PLCC
TOP VIEW
1/0 1
1/02
1/03
1/04
1/05
I/0e
1/0 7
I/0e
MATCH
PIN NAMES
R'ESET
OS
rn:
WE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA
RATING
Terminal Voltage
with Respect to
GND
Operating
Temperature
Oto +70
Address
WE
1/01-6
Data Input/Output
DE
Output Enable
CS
Chip Select
GND
Ground
RESET
Memory Reset
Vce
Data/Memory Match (Open Drain)
MATCH
Write Enable
Power
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
-0.5 to +7.0
Aa-12
MILITARY
-0.5 to +7.0
-55 to +125
UNIT
V
°C
TBiAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage(1)
2.2
-
6.0
V
V1HR
RESET Input High
Voltage
2.5(2)
-
6.0
V
V1L
Input Low Voltage
-0.5(3)
-
0.8
V
SYMBOL
PARAMETER
UNIT
NOTES:
1. All inputs except RESET.
2. When using bipolar devices to drive the RESET input. a pullup resistor
of 1kfi-1okfi is usualiy required to assure this voltage.
3. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
S4-182
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
IDT7174S CMOS STATIC RAM
64K (SKx S-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%
TEST CONDITIONS
PARAMETER
SYMBOL
Ilul
IILol
Input Leakage Current
Vee = Max., V1N
Output Leakage Current(2)
Vee = Max.
CS = V1H , VOLrr
IOL
10L
Output Low Voltage
VOL
IOL
10L
VOH
= GND to Vee
MIN.
-
MIL.
COM'L.
MIL.
COM'L.
= GND to Vee
MIL.
= 1BmA MATCH
COM'L.
= 22mA MATCH
= 10mA, Vee = Min. (All outputs except MATCH)
= BmA, Vee = Min. (All outputs except MATCH)
= -4mA, Vee = Min.
UNIT
MAX.
-
10
5
J.I.A
-
10
5
J..lA
0.5
V
-
0.5
V
-
-
IOH
(Except MATCH)
Output High Voltage
IDT7174S
TYP.(1)
-
-
0.5
V
-
0.4
V
2.4
-
-
V
NOTES:
1. Typical limits are at Vee = S.OV, +25°C ambient.
2. Data and MATCH
DC ELECTRICAL CHARACTERISTICS (1)
Vee = 5.0V ±10%
IDT7174S20
COM'L MIL
PARAMETER
SYMBOL
ICC2
IDT7174S25(2)
COM'L MIL
IDT7174S35
COM'L MIL
IDT7174S45
COM'L MIL
IDT7174S55
COM'L MIL
110
125
110
125
125
mA
Dynamic Operating Current
Outputs Open, Vee = Max., f
150
170
140
150
145
mA
= fMAX
NOTES:
1. All values are maximum guaranteed values.
2. Military values are preliminary only.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3
5V
5V
DATAoLrr
UNIT
Operating Power Supply Current
Outputs Open, Vee = Max., f = 0
~
2550.
5V
4Bon
, 3 0PF
Figure 1. Output Load
DATAoLrr
~
2550.
4Bon
MATCH
--t!
RL
lOOpF
5pF*
Figure 2. Output Load
(for tou tou, t cHZ ' to HZ ,
toW,tWHZ)
* Including scope and jig
S4-183
RL = 2000 (COM'L.)
= 2700 (MIL.)
Figure 3. Output Load for MATCH
IDT7174S CMOS STATIC RAM
64K (8K x B-BIT) CACH E-TAG RAM
DATA
MI.LITARY AND COMMERCIAL TEMPERATURE RANGES
-
16/
/
,~
20/
ADDRS
.I V13
"
Logic 1
5V
IDT7174
CACHETAG
RAM
~
CLEAR - - . .
~
....
.IVa
.IVa
,f
,f
IDT7164
CACHEDATA
RAM
IDT7164
CACHEDATA
RAM
,
+
16-BIT
MICROPROCESSOR
<
,)/ 7
-...
,~
DATA
ADDRS
MAIN
MEMORY
MATCH
WAIT
Y
+
-....
MEMORY READM'RITE
CONTROL LOGIC
~
CACHE READM'RITE
MAIN MEMORY READM'RITE
Figure 4. Example of Cache Memory System Block Diagram
NOTES:
1. For more information, see application note AN-07 ·Cache-Tag RAM Chips Simplify Cache Memory Design".
2. RL = 2000 (commercial) or 2700 (military)
AC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ±10%, All Temperature Ranges)
1DT7174S20{l)
PARAMETER
SYMBOL
IDT7174S25
IDT7174S35{l)
1DT7174S45
1DT7174S55 (2)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
25
.j::
35
-
45
-
55
-
25
30
30
40
50
-
ns
0
-
ns
50
0
0
-
ns
0
-
-
-
ns
20
10
-
15
-
20
-
25
ns
13
-
15
2
-
ns
2
-
25
-
-
20
2
5
-
ns
UNIT
WRITE CYCLE
twe
Write Cycle Time
20
tew
Chip Select to End of Write
12
tAW
Address Valid to End of Write
15
t AS
twp
Address Set-up Time
0
Write Pulse Width
15
tWR
Write Recovery Time (CS, WE)
0
tWHZ
Write Enable to Output in High Z (3)
-
tDW
Data to Write Time Overlap
tDH
Data Hold From Write Time
::::\:.
15
.::/::;:::::'
20
?:::::....:::::::::::::.
·:::dt:,::;.::::/··· .::f::::}}:: t",,· 0
..:
:. r:\d~l··
. <:::::.·tf::::,··:::·
19:::;:~1LZC'
.::):::g::{:::::,::;:> "::\$
-
Output Active from End of Write (3)
tow
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Preliminary data for -55°C to + 125°C temperature range only.
-
5
54-184
0
30
5
0
40
2
5
ns
ns
ns
IDT7174S CMOS STATIC RAM
64K (8K x 8-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (1)
~-----------twc----------~
ADDRESS
~---------tAW--------~
~---twP (2)
----.I
DATAoUT
DATA IN
VALID DATA IN
TIMING WAVEFORM OFWRITE CYCLE NO.2 (1,6)
~----------twc----------~
ADDRESS
~-------=-.---
tAW --------+1
-----+-T'iI--r-~~"""'IIf'-'\. t-ol-----t wP (2) _ _ _ _. - j _ - - - - - - - - -
DATA OUT
ttDW
tDH~
---------------------I'.
. ::::::;;:::::~§;£:.:::.
- . ::;::;;::;::;{td5
ns
. :::~;::::t:i\:;':"::: -
5
5
5
5
ns
'5;::::::::·
MATCH Valid Hold From Data
t MHO
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Preliminary data for -55°C to + 125°C temperature range only.
5
5
5
5
ns
tMHA
.'
MATCH TIMING
i
ADDRESS
CS
*
t AOM
OE
M
RESET
DATA
VALID READ DATAoUT
MATCH
NO MATCH
S4-186
IOT7174S CMOS STATIC RAM
64K (8K x 8-BIT) CACH E-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ±10%, All Temperature Ranges)
SYMBOL
10T7174S45
PARAMETER
MIN.
MAX.
10T7174S55 (2)
MIN.
MAX.
UNIT
RESET
RESET Pulse Width
(3)
RESET High to WE Low
80
100
ns
10
10
ns
NOTES:
1. ooe to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Recommended duty cycle 10% maximum.
4. Preliminary Information for -55°C to + 125°C temperature range only.
RESET TIMING
~14--_ -_tRSPW==~
-_
WE
xXXXXXXXXxxxxxxXXXXXY
CAPACITANCE(1) (TA= +25°e, f = 1.0MHz)
SYMBOL
e lN
PARAMETER(1)
Input Capacitance
CONDITIONS
VIN = OV
TRUTH TABLE
MAX.
UNIT
WE
CS
OE
8
pF
X
X
X
X
H
H
L
H
COUT
Output Capacitance
VOUT= OV
8
pF
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.
RESET
MATCH
I/O
FUNCTION
L
H
-
Reset all bits to low
X
H
H
High Z
H
H
L
DIN
No MATCH
L
H
H
H
DIN
MATCH
H
L
L
H
H
DOUT
Read
L
L
X
H
H
DIN
Write
Deselect chip
5V
IDT7174
CMOS Gate
Bipolar Gate
Driving the RESET pin with CMOS logic.
Driving the RESET pin with bipolar logic.
Figure 4.
S4-187
- - - - - - - - - - - - _ . _ - - - - - - - - - - - - _.. _..•..... _ - -
IDT7174S CMOS STATIC RAM
64K (BKx B-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vcc
=
5.0V ±10%, All Temperature Ranges)
IDT7174S25
IDT7174S35 (4)
MIN.
MAX.
MIN.
·d\.
35
-
45
-
55
-
ns
-
35
45
ns
25
-
55
20
-
30
ns
-
0
-
0
-
0
-
ns
12
-
20
-
25
-
30
ns
-
3
-
3
-
3
-
ns
13
ns
20
-
25
15
-
20
12
-
15
7::::::;;;:;::\:;;:::::::8
-
25
ns
-
5
-
5
-
5
-
5
-
ns
I DT7174S20 (1)
PARAMETER
MAX.
MIN.
MAX.
1DT7174S45
IDT7174S55 (2)
MIN.
MIN.
MAX.
MAX.
UNIT
READ CYCLE
t Rc
Read Cycle Time
20
-
25
tAA
Address Access Time
-
20
-
t ACS
Chip Select Access Time
-
10
tCLZ
Chip Select to Output in Low Z
0
-
tOE
Output Enable to Output Valid
-
tOLZ
Output Enable to Output in Low
10 ..:::::::: I:):::::;:'
...,::::::::::::::::::.;.' 3
tCHZ
Chip Select to Output in High
2(3)
2(3)
tOHZ
Output Disable to Output in High
tOH
Output Hold from Address Change
Z(3)
3
-
,':',
:\/:::::::::'1'2
1.:::::;::'0::(::::;:·'
..;;={::::;:::9::):·
·K:::::::..
.: ::)~§..:':"
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Preliminary information for -55°C to + 125°C temperature range only.
S4-188
IDT7174S CMOS STATIC RAM
64K (8K x 8-BIT) CACH E-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1
(1)
~--------------tRC------------~
ADDRESS
1+-------- tACS -------t---~
1+------- tCLZ (5) ________ 1
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
(1,2,4)
ADDRESS
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.3
(1,3,4)
DATA OUT
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, ~ = V IL •
3. Address valid prior to or coincident with OS'transition low.
4. O'E = V1L
5. Transition is measured ±200mV from steady state.
S4-189
IDT7174S CMOS STATIC RAM
64K (SKx S-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
DeV~ype
:
Y
999
A
A
Speed
Package
Process!
Temperature
' Mk
RM
TP
P
TC
~...................................~ D
J
L
SO
y
~""'--""''''''''''''''''''''''''''''''''''''--4
20
25.
35
45
55
~--------------------------4IS
I
.....- -...........................................................................--t 7174
~--
S4-190
.
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B,
Method 5004
Plastic DIP, 300 mil.
Plastic DIP, 600 mil.
THINDIP (Sidebraze)
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Small Outline IC (gull-wing)
Small Outline IC (J-bend)
Commercial onlY}
Speed in Nanoseconds
Military Only
Standard Power
64K (8K x a-Bit) Cache-Tag RAM
t;)
Intesrated Device~Inc.
ADVANCE
INFORMATION
lOT 71564S
lOT 71564L
CMOS STATIC RAM
WITH LATCHED
ADDRESSES
64K (8K x 8-BIT)
FEATURES:
DESCRIPTION:
• High-Speed Address Access Time
- Military: 25/35/45ns
- Commercial: 20/25/35ns
• On-Board Address Latches
• Low-Power Consumption and High-Reliability
• Battery Back-Up Operation: 2-Volt Data Retention
(L Version Only)
• Produced with Advanced CEMOS TM High-Performance
,
Technology
• Single 5V (±10%) Power Supply
• Input and Output Directly TIL Compatible
• Three-State Output
• Static Operation No Clocks or Refresh Required
• Military Product Compliant to MIL-STD-883, Class B
The 71564 is 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using IDT's high-performance, high-reliability
CEMOS ™ technology.
Address access times as fast as 20ns are available with typical
power consumption of only 250mW. The 71564 excels in cache
applications because of the on-chip address latches, which reduces system part count. This device is the preferred solution with
64K Byte Caches in systems requiring address latches, ie. the
IDT79R3000.
The low-power (L) version also offers a battery backup data
retention capability where the circuit typically consumes, only
10~W operating off a 2V battery.
All inputs and outputs ofthe IDT71564 are TIL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
FUNCTIONAL BLOCK DIAGRAM
A12
Al1
AlO
Ag
As
A7
As
A5
A4
A3
A2 A1
Ao
A
0
0
R
E
S
S
64K-BIT
MEMORY
L
A
T
C
H'
ALEN
1/00-1/0 7
....
~--
CONTROL
LOGIC
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY .1989
DSC-1055/-
1989 Integrated Device Technology, Inc.
S4-191
_ _ _ _ _ _ _ _ _ • _ _ _ _ _ 00 _ _ _ _ _ _
00
_ _ _ _ _ _
- - - - - - - - - - - - - - - - - - - - -
~
IntegratedDevIce~ Inc.
CMOS STATIC RAM
EXCLUSIVE-OR LATCHED
ADDRESSES 64K (8K x 8-BIT)
ADVANCE
INFORMATION
lOT 71578S
lOT 71578L'
FEATURES:
DESCRIPTION:
• High-Speed Address Access Time
- Military: 25/35/45ns
- Commercial: 20/25/35ns
• On-Board Address Latches
• Exclusive-Or on the Least Significant Bit
• Low-Power Consumption and High-Reliability
• Battery Back-Up Operation: 2-Volt Data Retention
(L Version Only)
,
• Produced with Advanced CEMOS ™ High-Performance
Technology
• Single 5V (±10%) Power Supply
• Input and Output Directly TTL Compatible
• Three-State Output
• Static Operation No Clocks or Refresh Required
• Military Product Compliant to MIL-STD-883, Class B
The 71578 is 65,536 bit high-speed static RAM organized as 8K
x 8. It is fabricated using lOT's high-performance, high-reliability
CEMOS ™ technology.
Address access times as fast as 20ns are available with typical
power consumption of only 250mW. The 71578 excels in cache
applications because of the on-chlp address latches, which reduce system part count. An exclusive-or function on the least
significant address bit simplifies implementation of "burst-mode"
cache, refills. This device is the preferred solution with 64K Byte
Caches for the Intel 80386. The low-power (L) version also offers a
battery backup data retention capability where the circuit typically
consumes only 10mW operating off a 2V battery.
All inputs and outputs ofthe IDT71578 are TTL-compatible and
operation is from a single 5V supply, simplifying system deSigns.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
FUNCTIONAL BLOCK DIAGRAM
A 12
A 11
---.
---.
A 10 - - - '
Ag - - - .
A8 - - - .
A7 - - - .
64K-BIT
MEMORY
A6 - - - .
As - - - .
A4 - - - .
A3 - - - .
A2 - - - .
A1 ---.
Ao - - - .
ALEN - - - - - - - '
INV
-------------1
WE--'"
CONTROL
LOGIC
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-1056/-
S4-192
I
~
Intesrated Device1echnoIogy. Inc.
lOT 712565
lOT 71256L
CMOS STATIC RAM
256K (32K x a-BIT)
ized as 32K x 8.lt is fabricated using IDT's high-performance, highreliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective altemative to bipolar and fast NMOS memories. Timing parameters have been specified to meet the speed demands of
the fastest ID179R3000 RISC processors.
Address access times as fast as 19ns are available with power
consumption of only 300mW (typ.). The circuit also offers a reduced power standby mode. When CS goes high, the circuit will
automatically go to, and remain in, a low-power standby mode as
long as CS remains high. In the full standby mode, the low-power
device consumes less than 15j.LW, typically. This capability provides significant system level power and cooling savings. The lowpower (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 5j.LW when
operating off a 2V battery.
All inputs and outputs of the ID171256 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The ID171256 is packaged in a 28-pin gull-wing or J-bend
SOIC, a 28-pin 600 mil CERDIP or plastic DIP, 28-pin Cerpack and
32-pin lead less chip carrier and PLCC, providing high board-level
packing densities.
The ID171256 military RAM is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally suited
to military temperature applications demanding the highest level of
performance and reliability.
FEATURES:
• Optimized for fast RISC processors including the ID179R3000
• High-speed address/chip select time
- Military: 30/35/45/55170/85/100ns (max.)
- Commercial: 19/20/25/30/35/45/55170ns (max.)
• Low-power operation
- ID171256S
Active: 300mW (typ.) .
Standby: 200j.LW (typ.)
- ID171256L
Active: 250mW (typ.)
Standby: 15j.LW (typ.)
• Battery Backup operation-2V data retention
• Produced with advanced high-performance CEMOS ™
technology
• Single 5V(±10%) power supply
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Available in standard 28-pin CERDIP and plastic DIP (600 mil),
28-pin SOIC, 28-pin Cerpack and 32-pin LCC and PLCC
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-88552 is pending listing on
this function. Refer to.Section 2/page 2-4.
DESCRIPTION:
The ID171256 is a 262,144-bit high-speed static RAM organ-
FUNCTIONAL BLOCK DIAGRAM
~Vcc
Ao
ROW
DECODER
512x 512
MEMORY ARRAY
~GND
COLUMN I/O
INPUT
DATA
CIRCUIT
COLUMN DECODER
::;EMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated DevIce Technology. Inc.
JANUARY 1989
D5O-l015/-1
S4-193
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
II
II
L.J
L..I
I I
L...I
I
I
I
I
I I
L.J
3 2 U
I I
L...I
I I
L...I
32 31 30
1
J32-1
&
L32-1
14 15 16
17
A8
29 [
18 19
28 [
A9
27 [
An
26[
NC
25 [
OE
24 [:
A10
23 [:
OS
22 [
1/0 8
21 [
1/0 7
20
nnnnnnn
DIP/SOIC/Cerpack
TOP VIEW
N
'"
0
U
.... '"
CD
QQzzQQQ
--C)
--LCC/PLCC
TOP VIEW
PIN NAMES
LOGIC SYMBOL
Ao - A14
Addresses
1/01-1/08
Data Input/Output
CS
WE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Write Enable
OE
Output Enable
GND
Ground
Vce
Power
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1)
COMMERCIAL
. Chip Select
GRADE
Military
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
Vee
OV
5.0V ± 10%
OV
5.0V ± 10%
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TerAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
MIN.
TYP.
MAX.
PT
Power Dissipation
1.0
1.0
W
Vee
Supply Voltage
4.5
5.0
5.5
V
lOUT
DC Output Current
50
50
mA
GND
Supply Voltage
0
0
0
V
Commercial
O°Cto +70°C
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
VrH
Input High Voltage
2.2
-
6.0
V
VrL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
S4-194
UNIT
1DT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V +10%,
VLe = 0.2V, VHe = Vee -0.2V
IDT71256S
MAX.
MIN.
TEST CONDITIONS
PARAMETER
SYMBOL
MIL.
Vee = Max.; VIN = GND to Vee
Ilul
Input Leakage Current
IILol
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
PARAMETER
-
10
5
Vee = Max.
MIL.
-
10
CS = VIH , VOUT = GND to Vee
COM'L.
-
5
UNIT
MAX.
-
5
JJ.A
2
J,lA
-
5
2
JJ.A
JJ.A
-
0.4
-
0.4
V
10L = 10mA, Vee = Min.
-
0.5
-
0.5
V
10H = -4mA, Vee = Min.
2.4
-
2.4
-
V
IoL
= SmA, \(::0 = Min.
DC ELECTRICAL CHARACTERISTICS(l,3) Vee =
SYMBOL
COM'L.
IDT71256L
MIN.
5V±10%, VLe = 0.2V, VHO = Vee -0.2V
POWER FUNCTION 71256x19/20 71256x25
COM'L. MIL. COM'L. MIL.
71256x30/35
MIL.
COM'L.
71256x45/55
MIL.
COM'L.
71256x70 71256xB5/100 UNIT
COM'L. MIL. COM'L. MIL.
..
leel
Operating Power
Supply Current
CS = '.'JL,
Outputs Open,
Veo = Max., f = 0
Dynamic Operating
Current
le02
ISB
ISBI
S
L
Standby Power
Supply Current
(TTL Level)
CS? VIH
Voe = Max.,
f = f MAX (4)
Outputs Open.
Full Standby Power
Supply Current
(CMOS Level)
CS ;? VHC
Voc = Max., f = 0
100
-
100
-
READ
100
-
WRITE (2)
100
-
READ
200
WRITE (2)
200
READ
200
WRITE (2)
200
S
cs = "IL'
Outputs Open,
Voo= Max.,
f = f MAX (4)
READ
WRITE (2)
L
S
:::3tk::.:. . ~
85
-
70
145/130 155/135 115/105125/115 95
105
-
90
20
-
20
30
40
30
40
100
90
100
90
100
1§;:::::?L
15
20
15
20
15
20
80
90
80
90
80
90
170/155 1S0/165
140
150
140
150
165/150 175/165
140
150
140
"';':'80: :~{ -
-:: {iP:%!' -:::::.' .':::. '::t:W5 ;::/%0
.ii:::;;::::
30t:iii··:::.!:!:
150/135 160/145 110/90 120/100 75
40
90
;{ I@{I~::::
....:.; ::.
150
-
30
-
::::j~O";";';
-
40
100
20
90
150
150
S
L
:1
4
Lt::
:~g: f:1.i :; :;~/
5
:::::i:~d {):::-
mA'
i::::::;::'
!::::: 20
-
20
20
20
20
20
·:::t::\::::}::::
L
mA
mA
3
-
3
3
3
3
3
3
-
3
15
-
15
20
15
20
15
20
-
20
0.4
-
0.4
1.5
0.4
1.5
0.4
1.5
0.4
1.5
mA
NOTES:
1. All values are maximum guaranteed values.
2. Write oycle current specifications are included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
Read cycles to Write cycles is extremely high. When calculating total current consumption, the designer should weight these figures by the percentage of
·On" time as well as the antiCipated ratio of Read to Write cycles (usually greater than 90%).
3. ·x· in part numbers indicates power rating (S or L).
4.
fMAX = 1/tRO
S4-195
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLO = 0.2V, VHO = Vcc - 0.2V
SYMBOL
VOR
IOCOR
TEST CONDITION
PARAMETER
MIN.
-
VOO for Data Retention
MIL
CS ~VHO
t COR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
COM'L.
-
-
2.0
I
Data Retention Current
TYP.(1)
Vcc @
2.0V
3.0V
-
-
0
-
t RO (2)
-
-
NOTES:
1. TA = +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCO
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
Sns
1.SV
1.SV
See Figures 1 and 2
SV
DATAOLrr
~
2550
5V
480n
DATAoLrr
30pF*
~
2550
Figure 1. Output Load
4800
5pF*
Figure 2. Output Load
(for tOlZ.t OlZ ' t OHZ '
t WHZ ' t CHZ ' tow)
* Including scope and jig.
S4-196
MAX.
Vcc @
2.0V
3.0V
-
-
500
800
120
200
-
-
UNIT
V
J..l.A
ns
ns
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vcc = 5V± 10%. All Temperature Ranges)
71256S19/20(3) 71256S25(3) 71256S30/35
71256L20(3) 71256L25(3) 71256L30/35
MIN. MAX. MIN. MAX. MIN. MAX.
71256S45/55 71256S70 71256S85/100(1)
71256L45/55 71256L70 71256L85/100(1) UNIT
MIN.
MAX. MIN. MAX. MIN.
MAX.
READ CYCLE
t RC
Read Cycle Time
20
-
tAA
Address Access Time
19/20
-
25.:::.
-
30/35
-
45/55
-
70
-
85/100
-
ns
-
29/35
45/55
70
85/100
ns
tACS
Chip Select Access Time
-
tcLZ
Chip Select to Output in Low 2(2)
5
tOE
Output Enable to Output Valid
-
toLZ
Output Enable to Output in Low 2(2)
2
tCHZ
Chip Deselect to Output in High 2(2)
- .:.::/ijB
-
11
tOHZ
Output Disable to Output in High 2(2)
2;{:::f:;:::::·:· 8
2
10
-
5
-
5
Output Hold from Address Change
tOH
NOTES:
1. -55°C to + 125°C temperature range only.
2. This parameter is guaranteed. but not tested.
3. O°C to + 70°C temperature range only.
20
.;. :'\t::·:·
25
-
30/35
45/55
-
70
-
85/100
ns
1:::{::5
-
5
-
5
-
5
-
5
-
ns
-
11
-
13/15
-
20/25
-
30
-
35/40
ns
2
-
2
-
0
-
0
-
0
-
ns
-
15
ns
30
-
35/40
20/25
-
30
12/15
-
20/25
2/2
35/40
ns
-
5
-
5
-
5
-
ns
1Q;=::m:::: .
..:-."j:::::;::-:"
.:..;.-
5
.:,::
-
.{}.:::::.·::·25
S4-197
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS
(1)
~=_--==_-==_-_tAA=_tR_C-=--=--=--._,-=--=--=---.l%=-'OH_ _
.....---- tOE
-----.,~
.....- - - - -
tA~S '----t-----.,~
.....---- tCLZ
(5)--_--i~
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2 (1.2,4)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.3 (1.3.4)
DATA OUT
NOTES:
1.
2.
3.
4.
5.
WE is High for Read Cycle.
Device is continuously selected, CS = \tiL.
Address valid prior to or coincident with CS transition low.
OE = \lL
Transition is measured ±200mV from steady state with 5pF load (including scope and jig).
S4-198
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32Kx S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
(VCC = 5V~ 10%, All Temperature Ranges)
71256S 19/20(4 71256S25(4) 71256S30/35
71256L2Q(4)
71256L25(4) 71256L30/35
MIN. MAX. MIN. MAX. MIN. MAX.
71256S45/55 71256S70 71256SS5/100(2)
71256L45/55 71256L70 71256L85/100(2) UNIT
MIN. MAX. MIN. MAX. MIN.
MAX.
WRITE CYCLE
twc
Write Cycle Time
20
-
tcw
ehip Select to End of Write
15
tAW
Address Valid to End of Write
15
t AS
Address Set-up Time
0
-
twp
Write Pulse Width
15
25.::..
....;::;.
..20·
;.: ..:.:•.....
Write Recovery Time
tWHZ
Write to Output in High
Z(3)
45
0
-
0
-
20/25
-
30
-
35/40
ns
20/25
-
30
-
35/40
-
0
-
0
-
ns
0
3
-
3
-
3
-
ns
5
-
5
-
ns
45/55
-
70
40/50
-
60
25/30
40/50
60
0
-
0
25/30
-
30/35
23/30
-
35/40
0
.:::::::'¢::::::::.
0
-
0
-
0
-
-
\::. .10-
-
11
-
15
-
-
.;::)~(r:·
'::::, Ii~:::::b
'.'
tWR
-
-
-
;;!'::;:...• :::::
13
-
-
0
-
5
-
1J:::::::::::\/:" -
tow
Data to Write Time Overlap
tOH1
Data hold from Write Time (WE")
tOH2
Data hold from Write Time (C5)
3
tow
Output Active from End of Write (3)
5
·::iii-r:: · ·
....
. 20
-
3
NOTES:
1. For the ooe to 70 0 e temperature range,
30ns speed grade, tow = 14ns.
35ns speed grade, tow;' 15ns.
Over the -55°e to + 125°e temperature range,
30ns speed grade, tow = 17ns.
35ns speed grade, tow = 18ns.
2. -55°e to + 125°e temperature range only.
3. This parameter is guaranteed, but not tested.
4. ooe to + 70 0 e temperature range only.
S4-199
14/18(1)
0
3
5
5
0
85/100
70/80
70/80
0
50/55
ns
ns
ns
ns
ns
ns
ns
IDT71256S AND 1DT71256L
CMOS STATIC RAM 256K (32Kx S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)
(1,2,3,5,7)
ADDRESS
.....__~________::::~-------------tw~7)
------------~~~~~--------------------_+_
DATA oUT
DATA IN
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)
(1,2,3,5)
~----------------------twc----------------------~
ADDRESS
~--------------------tAW------------------~
1*------------ t cw (7) ____________
....... ..........................................-----
,-
~
~
DATA IN
NOTES:
WE or CS must be high during all address transitions.
A write occurs during the overlap (tcw or twp ) of a low ~ and a low WE.
t wRis measured from the earlier of'CS or WE going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the C'S low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ+ tow) to allo~ the I/O drivers to tum off and
data to be placed on the bus forthe required tow. If OEis high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified twp .
1.
2.
3.
4.
5.
6.
S4-200
IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x S-BIT)
CAPACITANCE
SYMBOL
CIN
COUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(TA= +25°C. f = 1.0MHz)
PARAMETER(1)
Input Capacitance
Output Capacitance
CONDITIONS
MAX.
UNIT
VIN = OV
11
pF
VOUT= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
TR UTH TABLE
VLC = 0.2V. VHC = Vcc - 0.2V
FUNCTION
WE
CS
OE
1/0
X
H
X
Hi-Z
Standby (Isal
X
VHC
L
X
Hi-Z
Standby (IS81)
H
H
Hi-Z
H
L
L
DATAoUT
Read
L
L
X
DATAIN
Write
Output Disable
NOTE:
1. H = \'tH. L = VIL• X = DON'T CARE
ORDERING INFORMATION
IDT
XXXX
A
Device Type
Power
999
Speed
A
A
Package
Process/
Temperature
Ran~:rMk
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Y
P
D
L . . - - - - - - - - - - - l i SO
J
L
E
19
20
25
30
35
45
55
70
85
100
IL
I
Small Outline IC (J-bend)
Plastic DIP
CERDIP
Small Outline IC (gull-wing)
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Cerpack
Commercial Only
Commercial Only
Commercial Only
Speed in Nanoseconds
Military Only
Military Only
S
Low Power
Standard Power
71256
256K (32K x 8-Bit) Static RAM
S4-201
------------_._-
.t;J
HIGH-SPEED
STATIC RAM
ORGANIZED AS 32K x 8
Intesrated DevIce'Jechnolosy. Inc.
ADVANCE
INFORMATION
lOT 71583
FEATURES:
DESCRIPTION:
• 32K x 8 Parity checking Static RAM
The 10171583 is a294,912-bit high-speed static RAM organized
as 32K x 8. It is fabricated using lOT's high-performance highreliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories.
Address access timesas fast as 25ns are available with power
consumption of only 450mW (typ.). The circuit also offers a reduced power standby mode. When CS goes high, the circuit will
automatically go to, and remain in, a low-power standby mode as
long as CS remains high. In the full standby mode, the low-power
device consumes less than 200mW (typ.). This capability provides
significant system level power and cooling savings. The low-power
(L) version also offers a battery backup data retention capability
where the circuit typically consumes only 20~W when operating off
a 2V battery.
All inputs and outputs ofthe 10171583 are TIL-compatible and
operation is from a single 5V supply, simplifying system deSigns.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The 10171583 is packaged in a 32-pin 300mil side-brazed,
32-pin 300mil Plastic DIP, and 32-pin SOIC.
The 10171583 military RAM is manufactured in compliance with
the latest revision of MIL-STO-883, Class B, making it ideally suited
to military temperature applications demanding the highest level of
performance and reliability.
• High-speed address/chip select time
- Military: 35/45/55
- Commercial: 25/35/45
• Low power operation
-10171583S
Active: 450mW (typ.)
Standby: 300mW (typ.)
-10171583L
Active: 350mW (typ.)
Standby: 200mW (typ.)
• Three chip selects plus one Output Enable pin
• Address latches, activated by positive-true Latch Enable
• Single 5V (±10%) power supply
• Input and output directly TIL-compatible
• Battery back-up operation-2V data retention
• Available in 32-pln side-brazed and plastic DIP (300mil)
and 32-pln SOIC
• Military product is fully compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
L
A
T
C
294,912-BIT
MEMORY
H
ALE----'
I/01-I/OIR----r"+---f
CONTROL
LOGIC
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated DevIce Technology, Inc.
DSC-l063/-
S4-202
._.•.._._-_._-_ ... _-_ ..__... - _ . _ - - - - - -
JANUARY 1989
IDT71583 HIGH-SPEED
STATIC RAM ORGANIZED AS 32Kx 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOGIC SYMBOL
PIN CONFIGURATION
CS3
Vee
1/°1
1/°2
1/0 3
ALE
A14
CS2
.1/° 4
Ae
As
A4
A3
A 13
Aa
Ag
A2
Al
Ao
1/°1
'DE"
A12
A7
1/°5
1/0 6
1/°7
I/Oa
1/°2
1/0 3
1/°4
GND
CST
CS2
CS3
~
DE PE"
ALE
TRUTH TABLE
WE
CS1
CS2
X
H
X
X
X
X
L
X
X
X
H
L
H
L
CS3 OE
I/O
fiE
MODE
X
Hi-Z
Hi-Z
Standby (IS81)
X
X
Hi-Z
Hi-Z
Standby (IS81)
H
X
Hi-Z
Hi-Z
Standby (IS81)
H
L
H
Hi-Z
Hi-Z
Output Disable
L
H
L
L
DOUT
Dour
Read
L
H
L
X
DIN
DIN
Write
NOTES:
1. CS2 and CS3 are used for conditional write.
2. When ALE (Address Latch) is H (HIGH) address function in "flow
through" manner (Standard RAM Function).
When ALE is L (LOW) addresses are latched.
S4-203
~
All
A12
CST
PE '
I/O a
1/°7
I/O e
1/°5
~
ADVANCE
INFORMATION
lOT 7169S
lOT 7169L
CMOS HIGH-SPEED
STATIC RAM 8K X 9-BIT
Integrated Devlce"Jechnolosy.lnc.
FEATURES:
DESCRIPTION:
• 8192-words x 9-bits organization
The IDT7169 is a 73728-bit high-speed static RAM organized as
8K x 9.lt is fabricated using IDT's high-performance, high reliability
CEMOS technology.
The IDT7169 offers address access times as fast as 35ns. The
ninth bit is optimized for parity check.
All inputs and outputs of the IDT7169 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
The IDT7169 is packaged in an industry standard 28-pin DIP
and LCC, along with a 32-pin LCC package.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class 8, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
• JEDEC standard 28-pin package
• Fast access time:
- Commercial: 35/45
- Military: 45/55
• 8attery backup operation-2V data retention voltage
(L version only)
• Produced with advanced CEMOS ™ high-performance
technology
• Single 5V power supply
• Input and output directly TTL compatible
• Static operation: no clocks or refresh required
• Military product available compliant to MIL-STD-883, Class 8
PIN CONFIGURATION
~oUU 81\lJ~
Z>
8u 8~~~U
Z
:!
000
INDE
WWWWWjjWWWWW
PIN NAMES
Ao-All
Addresses
1100-1/015
Data Input/Output
CE
Chip Enable
WE
Write Enable
OE
Output Enable
UB
Upper Byte Enable
LB
GND
Lower Byte Enable
Vee
Power
D12
Dll
Dl0
D9
D8
GND
NC
D7
D6
D5
D4
6 5 4 3 2 .... 444342 41 40
1
39[:
:J 7
38[:
:l 8
37[
:l 9
36[:
:1 10
35[
:111
L44-1
34r:
:l 12
&
33[
:J 13
J44-1
32[
:l 14
31[
:l 15
30[:
:l 16
29[
:l 17
181920 2122 232425262728
NC
NC
All
Al0
A9
GND
NC
A8
A7
A6
A5
nnnnnnnnnr.n
Ground
LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
V.
Operating
Temperature
Oto +70
TB1AS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
TA
-55 to +125
SYMBOL
°C·
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
\oIH
\oiL
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
S4-210
AMBIENT
TEMPERATURE
GND
Vee
-55°C to + 125°C
OV
5.0V
OOCto +70 o C
OV
5.0V
± 10%
± 10%
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1OT7186S/IOT7186L CMOS STATIC RAM 64K (4K X 16-BIT)
DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL
UNIT
MIN.
MAX.
MIN.
MAX.
10
10
5
5
J-IA
J-IA
5
5
J-IA
J-IA
0.5
-
0.4
0.5
V
V
-
2.4
-
V
Ilu l
Input Leakage Current
Vee = Max., VIN = GND to Vee
MIL.
COM'L.
IILOI
Output Leakage Current
Vee= Max.
CE = VIH , VOUT = GND to Vee
MIL.
COM'L.
VOL
Output Low Voltage
10L = 6mA, \be = Min.
IOL = 8mA, Vee = Min.
-
VOH
Output High Voltage
10H = -4mA, Vce = Min.
2.4
DC ELECTRICAL CHARACTERISTICS
IDT7186L
IOT7186S
TEST CONOITION
PARAMETER
10
10
0.4
(1)
Vce = 5V ± 10%, VLC = 0.2V, VHC = Vec - 0.2V
SYMBOL
PARAMETER
POWER
1OT7186S25
1DT7186L25
COM'L MIL.
IOT7186S35
10T7186L35
COM'L MIL.
Operating Power Supply Current
CE = VIL ' Outputs Open,
Vcc = Max., f = 0 (2)
S
160
L
135
:!!!;:;:~!!!;::
125
S
190:t(:::::~
170
lec2
Dynamic Operating Current
CE=V IL , Outputs Open,
Vce = Max., f = fMAX(2)
IS6
Standby Power Supply Current
(TTL Level) CE ~ \'IH, (2)
Vec = Max., f = fMAX
Outputs Open
leel
IS61
Full Standby Power Supply
CCl'rent (CMOS Level)
CE? VHe , VIN <;:, V Le orVIN;::: V He
Vce = Max., f=0(2)
,::;:::?f::::'
140
10T7186S45 10T7186S55 10T7186S7,0
10T7186L45 10T7186L55
10T7186L70'
COM'L MIL COM'L MIL COM'L MIL
130
150
145
115
135
115
200
160
190
160
160
130
UNIT
130
150
mA
135
115
135
mA
190
160
190
mA
150
...•...•..;...:;::
L
160:::::::::~:~:~:::;-
150
180
140
170
140
170
140
170
mA
S
):::'~:::~:::::'::r -
40
40
40
40
40
40
40
40
mA
6
6
6
6
6
6
6
6
mA
L
~:::::::,:::f:
-
S
~:::::::::;:.::
-
15
20
15
20
15
20
15
20
mA
L
:~.·i: : : ·:
-
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
mA
NOTES.
1. All values are maximum guaranteed values.
2. At f = fMAX' address and data input are cycling at the maximum frequency of read cycles of 1~e. f = 0 means no input lines change.
S4-211
IDT7186S/IDT7186L CMOS STATIC RAM 64K (4Kx 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = O.2V. VHC = Vcc - O.2V
SYMBOL
VOR
PARAMETER
TEST CONDITIONS
-
Vee for Data Retention
ICCDR
Data Retention Current
I
MIL
t COR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
Ilu l (3)
Input Leakage Current
CE :?VHC
VIN ~ VHC or S VLC
TVP.(l)
Vcc @
2.0V
3.0V
MIN.
COM'L.
2.0
-
-
-
0
t RC (2)
-
MAX.
Vcc @
2.0V
3.0V
-
-
-
600
900
200
300
UNIT
V
J.IA
-
-
-
-
-
ns
-
2
2
J.IA
ns
NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
AC TEST CONDITIONS
CAPACITANCE
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
:q
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER
MAX.
UNIT
Input Capacitance
VIN = OV
12
pF
Cvo
Input/Output .
Capacitance
VOUT= OV
12
pF
5V
DATA OUT
2550
CONDITIONS
CIN
:q
5V
6040
DATAoUT
30pF*
2550
Figure 1. Output Load
6040
5pF*
Figure 2. Output Load
(for tow. tWHZ • tCHZ • tCLZ •
t BHZ ' t BLZ • t OHZ ' t oLZ )
* Including scope and jig.
S4-212
._---------
-~--------------------------------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I 0T7186S/I 0T7186L CMOS STATIC RAM 64K (4K x 16-Bln
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vcc -- 5V +10%
All Temperature Ranges)
-
1DT7186S25(1)
IDT7186L25(1)
MIN.
MAX.
PARAMETER
10T7186S35
1DT7186L35
MIN.
MAX.
IOT7186S45
IOT7186L45
MIN. MAX.
10T7186S55
1DT7186L55
MIN.
MAX.
10T7186S70
IOT7186L70
MAX.
MIN.
UNIT
REAOCYCLE
t AC
Read Cycle Time
25
';::::\;;,;::::-
35
-
45
-
55
-
70
-
ns
tM
Address Access Time
;';"""'25-"'"
-
45
-
55
ns
,:::(::::@$.";:'"
35
-
45
-
55
-
70
Chip Enable Access Time
-
35
t ACE '
-
70
ns
tAB
Upper/Lower Byte Enable
Access Time
-
;()(::::~;i:·;:;:
-
18
-
20
-
25
-
30
ns
tcLZ
Chip Enable to Output in Low Z (2)
5
;;;:;:;;;;;;:;:;:;';;:7;=:::
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
{;:::{;::::::h;~'
-
18
-
20
-
25
-
30
ns
tBLZ
Upper/Lower Byte Enable to
Output in Low Z(2)
5
5
-
5
-
5
-
ns
toLZ
Output Enable to Output in Low Z (2)
5
-
5
-
5
5;::\/:;::;::;:;:;;?~.
tCHZ
Chip Disable to Output in High
- .::;:;:;:;:;:;:;:;:,::;,:::)5
18
Output Disable to Output in High
18
-
20
tOHZ
-
tOH
Output Hold from Address Change
5
-
tBHZ
Upper/Lower Byte Enable to
Output in High Z(2)
'1:::::::::'::':::.:;:;::::.;:::'15
-
18
tpu
Chip Enable to Power Up Time
9/:::::::::;;:::::::::::::: -
0
-
0
-
0
-
0
-
ns
tpD
Chip Disable to Power Down Time
ill::::;::::::::::;:;;;;;;:;: 25
-
35
-
45
-
55
-
70
ns
Z (2)
Z(2
-,.:.:.:.,..,
5:;;:;::
-
:t~~J:~:~~::;;;::::::::;:·
.:=::::;15
.....,.,:':':':::
-
5
-
5
-
ns
25
ns
25
-
30
20
-
30
ns
5
-
5
-
5
-
ns
-
20
-
25
-
30
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. This parameter is guaranteed but not tested.
S4-213
- - - - - - - - - - - - - - - - _ ..__ . __._--
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7186S/IDT7186L CMOS STATIC RAM 64K (4Kx 16-BIT)
TIMING WAVEFORM OF READ CYCLE NO.1
~DRE$
---t--
(1)
=i14--_-_-_-_
-_tRC
.'
tAA
~
,~
tOE
00
or
rn
'~
~
t OLl (5)
tAB
t AcE
tCLl
~,
r
t OHZ (5)
{
t
~
t BLl (5)
"~
t OH ( 5 ) -
t
I
BHZ
(5)
CHZ
(5)
(5)
~
DATAoUT
,~
~
TIMING WAVEFORM OFREAD CYCLE NO.2 (Continuously Enabled Read)
~
(1,2,4,8)
ADDRESS
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.3 (CE Controlled Read W/Power-Up/Down Timing) (1,3,4,8)
'~
/r
t AcS
I
tCLl (5)
DATA OUT
ISB
---------::1'
.-
tpD
'~
cr
arm =
/
I~
NOTES:
1. ~ is High for Read Cycle.
2. Device is continuously selected, 'CE' = VII"
3. Address valid prior to or coincident with
transition low.
4. ~ = V1L
5. Transition is measured ±200mV from steady state with 5pf load (including scope and jig).
6. DB
,
I~
t pu
Vee SUPPLY
CURRENT
- tCHZ ( 5 ) -
V1L
S4-214
-------- - .... -,,---•.
....
-~
.. -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7186S/IDT1186L CMOS STATIC RAM 64K (4Kx 16-BIT)
AC ELECTRICAL CHARACTERISTICS Nee =
SYMBOL
PARAMETER
5V ±10% All Temperature Ranges)
IDT1186S25 (1)
IDT1186L25 (1)
MIN.
MAX.
IDT1186S35
IDT7186L35
MIN. MAX.
IDT1186S45
IDT1186L45
MIN. MAX.
IDT1186S55
IDT1186L55
MIN.
MAX.
IDT1186S70
IDT1186L70
MIN.
MAX.
UNIT
twc
Write Cycle Time
25
35
45
55
70
ns
tcw
Chip Enable to End of Write
20
30
40
50
60
ns
taw
Upper/Lower Byte Enable to
End of Write "
20
30
40
50
60
ns
tAW
Address Valid to End of Write
20
t
Address Set-up Time
0 ...:::::: :::::::::.: -
AS
tDH
Data Hold from Write Time
.:::::: r::::;;;::
tow
Output Active from End of Write
:,:::::::~
t,:
,:,:::::::::::::::;
..::::::::)}'.'
.::::::::::~:::::>::'
30
-
40
-
50
-
60
ns
0
-
0
-
0
-
0
ns
3
3
3
3
ns
5
5
5
5
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. This parameter is gUaranteed but not tested.
S4-215
- - - - - ... _--" ........._-".
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT7186S/IDT7186L CMOS STATIC RAM 64K (4Kx 16-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)
(1,2,3,7,8)
ADDRESS.
tw~7) ------.j
._------------_+_
1 4 - - - - tow ----...,~
DATA OUT
___________________
~~-t-DW----.!-.---tD-H-~~-----------
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)
(1,2,3,5,8)
twc
ADDRESS
: : )<
)(
! 4 - t AS
tAW
~
~~
tWA
tcw
I
~
______________________________~~-t-DW------.~I.-----tD-H-~~------------
TIMING WAVEFORM OF WRITE CYCLE NO.3, (UB or LB CONTROLLED TIMING)
(1,2,3,5,9)
twc
ADDRESS
: : )K
)K
DB
or
[8
I+--
t AS
tAW
~
~V'
tWA
tBW
I
f--
____________________________________~~-t-Dw------.~).-----tD-H-~
NOTES:
1.
wr:.. cr, or both 00 and [8 must be high during all address transitions.
cr
2. A write occurs during the overlap (tBW' tow or twp ) of a low DB or [8, a low
and a low Wl:.
3. tWA is measured from the earlier of 00, [8, CE" or wr:. going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
cr, 09', or rn low transition occurs simultaneously with or after the wr:. low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
7. If DE is low during a ~ controlled write cycle, the write pulse width must be the larger of twp or (tWHZ+ tDW) to allow the 110 drivers to tum off and
data to be placed on the bus for the required tDW. If
is high during an wr:. controlled write cycle, this requirement does not apply and the
or:
write pulse can be as short as the specified t wp .
8. 00 or[B V,L
9.
cr =
=
V,L
S4-216
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7186S/IDT7186L CMOS STATIC RAM 64K (4K X 16-BIT)
TRUTH TABLE
(1)
OUTPUTS
INPUTS
MODE
m
WE
DE
DB
H
X
X
X
X
Hi-Z
Hi-Z
L
X
X
H
H
Hi-Z
Hi-Z
Both Bytes Deselected
L
L
X
L
H
Hi-Z
Write to Upper Byte Only
L
L
X
H
L
L
L
X
L
L
DATA IN
L
H
L
L
H
DATA OUT
L
H
L
H
L
L
H
L
L
L
L
H
H
X
X
CE
1/0 8 - 1/015
1/00 - 1/°7
DATA IN
Hi-Z
Hi-Z
DATA OUT
Deselected, Powered Down
DATA IN
Write to Lower Byte Only
DATA IN
Write to Both Bytes (Word Write)
Hi-Z
Read Upper Byte Only
DATA OUT
Read Lower Byte Only
DATA OUT
Read Both Bytes (Word Read)
Hi-Z
Hi-Z
Outputs Disabled
NOTE:
1. H=High, L=Low, X=Don't Care, Hi-Z= High Impedance'
ORDERING INFORMATION
IDT
xxxxx
A
Device Type
Power
999
Speed
A
Package
A
Process!
Temperature
Range
y:'Mk
~----------------I
L
P
C
J
25
35
~----------------------~ 45
55
70
Commercial (O°C to
Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B,
Leadless Chip Carrier
Plastic DIP
Sidebraze DIP
Plastic Leadless Chip Carrier
Commercial Only }
Speed in Nanoseconds
Standard Power
Low Power
64K (4K x 16-Bit)
S4-217
+ 70°C)
~
Integrated Device'1echnology.lnc.
CMOS STATIC RAM
64K (4K x 16-BIT)
REGISTERED RAM w/SPC
lOT 715025
lOT 71502L
lM
FEATURES:
DESCRIPTION:
• 4K x 16 RAM with registered outputs, serial or parallel load and
readback capability in only 48 pins
• Serial Protocol Channel allows serial load and read back of RAM
over a 4-wire channel
• RAM address counter speeds RAM load and readback
• Outputs may be programmed to be registered or non-registered
in groups of 8 bits
• Initialize register allows initial microword selection
• Synchronous and asynchronous output enables allow for depth
expansion and bus driving
• Programmable chip selects enable depth & width expansion
without any external decode logic
The IDT71502 Registered RAM is a 65,536 bits high speed static
RAM organized as 4K x 16, with a high speed register at the RAM
outputs and serial load and readback capability using the IDT Serial Protocol Channel, SPC ™.
This device is the first in a family of multifeatured RAM's with a
built-in Serial Protocol Channel SPC ™ letting the user set the best
configuration for his system:
• SELF-ADDRESSING RAM
• WRITABLE CONTROL STORE
• LOGIC ANALYZER/RECORDER
The 71502 is fabricated usinq IDT's high-performance, highreliability technology-CEMOS M. This technology gives the
71502 the combination of low power, high speed, and high density
that makes it a cost effective solution.
The IDT71502 is available with address set up before clock
times as fast as 25ns. These times are available with a maximum
power consumption of only 1.6W.
All inputs and outputs of the IDT71502 are TTL-compatible, and
the device operates from a single 5V supply. Fully static, asynchronous circuitry is used, requiring no clocks (with the exception of the
register clock) or refreshing for operation.
The IDT71502 is packaged in plastic and ceramic versions of
either a 48-pin, 600 mil DIP; a 48-pin leadless chip carrier, or a
52-pin plastic lead less chip carrier providing high board level
packing densities.
The IDT71502 is 100% processed in compliance to the test
methods of MIL-STD-883, Method 5004.
• Breakpoint comparator supports system diagnostics
• Parity check on outputs for high reliability designs
• High-speed (address set-up before clock)
- Military: 35/45/55ns (max.)
- Commercial: 25/35/45ns (max.)
• Low-power consumption
- IDT71502S - Active: 750mW (typ.)
- IDT71502L - Active: 600mW (typ.)
'i. Input and output directly TTL-compatible
.• Standard 48-pin DIP, 48-pin LCC and 52-pin PLCC.
• Military product 100% compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
SERIAL -...."e.----~
J . . - - - - , ; L - - - _ SERIAL
DATA IN
1-----------1
DATA OUT
ADDRESS--~'---L-----~--~
12
RAM ARRAY
RAM ADDRESS
~------,,::::
tAW
Address Valid to End of Write
25
t wcw
Chip Select To End Of Write
25:;:::::::::::::;:·
tWDH
RAM Write Data Hold Time
O.::::::::::::;.:}
5\::\):
tWR
Write Recovery Time
twz
Write Enable to Output Hi-Z
tow
Output Active from End of Write (3. 6)
;:+t:::"::
(3. 6)
.:\:&::?
35
-
45
-
25
-
30
-
-
50
-
60
-
50
60
-
0
0
ns
80
0
ns
ns
ns
ns
ns
-
5
-
5
-
5
-
15
-
15
-
20
-
20
ns
-
5
-
5
-
5
-
ns
ns
ns
NOTES:
1. 0 ° C to + 70 ° C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Pipelined address access set-up time.
'-"H'
5. OE" =
6. Transition is measured ±500mV from steady state with 5pF load (including scope and jig).
TIMING WAVEFORM OF WRITE CYCLE (1)
twc
ADDRESS
~K
)K.
t wcw , tAW
~i\.
~
~--
/'
'r\.
r---
tDW
tWDH_
"'
DATA IN
"-
1'_t
DATAovr
t WR -
twp
tWAS
»»)~»»~~~~)~
WZ
(2)
~tow"'
"'
NOTE:
1. A write occurs during the overlap of both CS and WE low.
2. Transition is measured ±500mV from steady state with 5pF load (including scope and jig).
S4-225
....
__._-._.. _........ _._-._--_._--._-----_._-------------------
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K X 16-BIT) REGISTERED RAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vcc = 5V ±10%. All Temperature Ranges)
I DT71502S25 (1. 4)
IDT71502L25(1.4)
MIN.
MAX.
PARAMETER
IDT71502S45 (4) IDT71502S55 (2. 4)
I DT71502 L55 (2. 4)
IDT71502L45 (4)
MIN.
MAX. MIN.
MAX.
1DT71502S35 (4)
IDT71502L35(4)
MIN.
MAX.
UNIT
TRACE WRITE CYCLE
...:.:;.
.:.::.
t lWC
Trace Write Cycle Time
40
t lWDS
Trace Write Data Set-up Time
8
:::,;:::::4;"
tlWDH
Trace Write Data Hold Time
2
t lWs
Trace Write Enable Set-up Time
8
:::):::::::=:,:::it:::::::: -
t TCS
Trace Write Chip Select Set-up Time
8,:::::::::::::::::'
,f:::::::!/::'
tlWH
Trace Write Enable Hold Time
t TcH
Trace Write Chip Select Hold Time
.'::::2:,'"
-
50
10
2
10
-
10
-
2
2
65
12
2
12
12
2
2
-
80
15
2
-
15
-
15
2
2
-
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. OOC to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.
4. Pipelined address access set-up time.
TIMING WAVEFORM OF TRACE WRITE CYCLE (1)
~---------------------tlWC----------------------~
~-------- tcwH----------~---------tCWL --------~~
CLOCK
DATA IN
WE
NOTE:
1. A write occurs if both CS and
WE are low at the clock low-to-high transition
AC TEST CONDITIONS (Read and Write Cycles)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
5V
~
DATAouT1
PAR
2550
4800
5V
BKPT-!
3OpF*.
(5pF for
toz. tsoz. twz. tow)
2200
30pF*
1
Figure 2. Output Load
(for BKPT pin)
*Includes scope and jig.
Figure 1. Output Load, Parity Output
S4-226
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K X 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SPC AC ELECTRICAL CHARACTERISTICS (1)
VCC = 5V ±10%, All Temperature Ranges
IDT71502S/L (1)
PARAMETER
SYMBOL
UNIT
MIN,
MAX,
ns
ns
tSCLK
SCLK Period
100
tscw
SCLK Pulse Width
40
t SDS
Serial Data Set-up Time
20
tSDH
Serial Data Hold Time
2
-
tscD
Clock to serial Data Output Delay
-
30
t SPD
Serial Data-In-to-Out Delay, Stub Mode
-
20
ns
tCMLH
Command/Data Set-up Time, Low-to-High (2)
20
ns
tCMHL
Command Set-up Time, High-to-Low (Execution Time)(2)
35
tCMH
Command/Data Hold Time(2)
5
-
tCSCD
Command/Data to Serial Data Output Delay (1st Bit Only)
-
45
ns
ns
ns
ns
ns
ns
NOTES:
1. These specifications apply to all speed grades of the product.
2. c/B cannot change while SCLK is high.
TIMING WAVEFORM OF SPC CHANNEL
tSCLK
tscw
SCLK
t scw -
'~
JV
SERIAL DATAIN
,
.1
tSDS
' \ : t SPD SERIAL DATA OUT
)K
I~
,,,::,>'<
"".",.",'.,
tSCD
)(
tCSCD
tCMHL- '
tCMH
c/o
tSDH
-
I
~r--
'~
/11'
tCMH
~,
tCMLH -
~V
COMMAND
EXECUTE TIME
(REFERENCE)
AC TEST CONDITIONS (SPC)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
GND to 3.0V
5ns
1.5V
1.5V
See Figure 3
so
~
2550
4800
30pF*
Figure 3. Output Load for Serial Output
*Includes scope and jig.
S4-227
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SPC FUNCTIONAL BLOCK DIAGRAM
COMMAND~(C/~) - - - - , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
SERIAL DATA IN
(SI)
SERIAL DATAoUT
(SO)
SERIAL CLOCK (SClK) ---.--I--------L-.J
t------+---'----.
......- - - - - . . . , . . - - - - - . . . .
MUX ENABLES
AND REGISTER
STROBES, ETC.
DATA
ClK
16
DIAGNOSTIC DATA
TOIFROM CHIP
SPC COMMAND FORMAT
o
4 3
7
SPC Command Code
4 bits
SPC Register Code
4 bits
SPC COMMAND CODES
COMMAND
CODE
READ/WRITE
FUNCTION
0
Read
Read Register
Uses Register Select Field
Uses Register Select Field
ACTION
NOTES
1
Write
Write Register
2
Read
Read Register and Increment Initialize Counter
Serial RAM Read
3
Write
Write Register and Increment Initialize Counter
Serial RAM Write
4-C
-
D
Write
Stub Diagnostic
Broadcast Commands
E
Write
Serial Diagnostic
Serial Commands
F
-
No-Op
Guaranteed No-Op
-
Reserved (No-Op)
SPC REGISTER CODES
REGISTER
CODE
0
1
READ/WRITE
FUNCTION
REGISTER
NOTES
R/W
Initialize Counter
-
R/W
RAM Output (or Input if reading)
-
2
R/W .
Pipeline Register
3
R/W
Break Mask Register
4
A/W
Break Data Register
+ Status Register
-
5
R/W
6
Rd Only
1/015 - 1/00 (Data Pins)
Data Pins of Chip
7
Rd Only
RAM Address
Address Going into RAM
8-F
-
Set-up
Reserved (unused)
84-228
Break Multiplexer, Trace Mode, etc.
-
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATUR.E RANGES
REGISTERED RAM DATA FLOW BLOCK DIAGRAM
r-----------------------------------------~
SPR READ DATA BUS
1
1
1
SERIAL
DATAIN
1
~:f----::~~rs;ERiALi;RciTc5i5OL:REGiSilli1_~----_t_----'
1
SERIAL .
DATA OUT
1
1
1 TRACE
1
1
1
1
1
I.
ADDRESS -r--------:>"--..t
t-if----t..;... BREAKPOINT
COMPARE
cr 1 LEVEL 4----....-+-1
cro lEVEL 4-----...-1-+-1
FLOW 15-8
FLOW 7-0
BREAK ON ADDRS
BREAK PIPE
TRACE
mTT -L--t~--r----I-;;;;~~
ClK
4---r++t-t
4---.-+-+++-1
4---,-+-+-+--I-+-t
4--r-i-+-+-+--t-L-t
.....+-I-+-+-+-+--t
......--,_....
~--+r----+-r--~
POWER
UP
at
~--r---~
STATUS BITS
1... _ _ _ _ _ _ _ _ _ _ _ _ _
RAM DATA 1NJOUT
PARITY
S4-229
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP REGISTER FORMAT
BIT
NAME
TYPE (1)
FUNCTION
POWER-UP
VALUE
15
CE
RO
Chip Enable State: NOR of All Chip Enable Pins
0
14
SOE FF
RO
SOE FF State: 1 = Output Enabled. 0 = Output Disabled
0
13
SOE Pin
RO
SOE Pin State: 1 = High. 0 = Low
0
12
OEPin
RO
OE Pin State: 1 = High. 0 = Low
0
11
WE Pin
RO
WE Pin State: 1 = High. 0 = Low
0
10
INITPin
RO
INIT Pin State: 1 = High. 0 = Low
0
9
BP Compare
RO
Breakpoint Comparator Output: 1 = Compare Valid
0
8
BP Pin
RO
BP Pin State: 1 = High. 0 = Low
0
7
CS 1 Level
RNI
CS1 is Low Active; 1 = CS 1 is High Active
0
6
CS o Level
ANI
o=
o=
CS o is Low Active; 1 =. CS o is High Active
0
5
Non-Reg High
RNI
Set Pipeline Register Bits 15-8 to Flow-Through Mode
0
4
Non-Reg Low
RNI
Set Pipeline Register Bits 7-0 to Flow-Through Mode
0
3
-
-
(Unused)
0
o=
Breakpoint on Pipeline Register Output. 1 = Breakpoint on RAM
Address Inputs
0
2
BC Address
RNI
1
BC Pipelined
RNI
Set Breakpoint Output MUX for Pipeline FF Output
0
ANI
Set for Trace Mode: 1/015-0 to Pipeline Register. Pipeline Register to RAM.
Initialize Counter as Address. Write with Clock Pulse
0
0
Trace Mode
NOTE:
1. RO means Read Only. RNI means ReadNirite.
S4-230
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
GENERAL DESCRIPTION
register. This is the normal operating mode, where all the shift registers in a system are connected into one long shift register. The
SPC logic in the 10171502 is automatically set to the Serial mode
by power up. The Stub command sets the latch and causes the serial output data to be taken from the serial input. In this mode, the
serial data is passed directly from one chip to the next so that all
command registers have the same data at their serial inputs. This
allows a broadcast mode where all command registers in a system
can be loaded with the same command at the same time.
The 10171502 Registered RAM consists of a 4K x 16-bit RAM
plus a 16-bit pipeline register and is designed for microcode
writable control store use. A serial shift register system, the Serial
Protocol" Channel (SPC), is included on-chip for serial load and
read-back of the RAM data. A RAM address counter is also provided to speed up RAM load and read-back. The SPC serial shift
register is also configured to be used as a diagnostic register. The
shift register can read all status conditions on the chip such as the
RAM output, pipeline register output, data output pin state and
RAM load/read counter value. A breakpoint comparator is
included to support the diagnostic function. This breakpoint
comparator can be used to detect a particular bit pattern in the
RAM address or pipeline register outputs.
The 10171502 Registered RAM includes features to support
control store applications. These include synchronous output
enable and an initialize register for selecting the initial value of the
pipeline register. A parity output is provided which indicates the
parity of the contents of the pipeline register. The parity output can
be used to provide parity check control for high-reliability systems.
The 10171502 Registered RAM can also be used as a trace RAM
for recording external data. In this mode, the data I/O pins are
inputs and data is clocked into the RAM using the Initialize register
as the address counter. The Trace mode, in combination with the
breakpoint comparator, allows the 10171502 Registered RAM to
be used as a one-chip logic analyzer.
RAM Load/Readback Logic
The RAM write pulse is generated by an internal one-shot triggered by the clock. Data is written into the RAM immediately
following pipeline register load and the Initialize Counter is incremented by the trailing edge of the write pulse. Using an internally
generated write pulse makes RAM writing independent of clock
high and low times. A timing diagram ofthe RAM clocking is shown
in the Trace Mode Clock Timing Diagram (Figure 5).
A detailed block diagram of the ID171502 Registered RAM,
showing the various internal registers and the load and read back
paths, is shown in the Registered RAM Data Flow Block Diagram.
In addition to the logic shown in the Functional Block Diagram on
the first page of the data sheet, there is an Initialize Counter for
loading and initializing the RAM, Break Data and Mask registers for
the Breakpoint Comparator and multiplexers at the input to the
Pipeline register for allowing data from the data I/O pins to be
clocked into the Pipeline register in the Trace mode before being
written into the RAM. The data flow block diagram also shows the
various multiplexers for routing data for breakpoint and read back
use.
RAM Operation
After power up, and in its typical operating mode, the 10171502
Registered RAM is set for pipelined read and direct (non-pipelined)
write. Data may be directly written into the RAM by driving the
address and data inputs and strobing the Write Enable input. Data
is read from the RAM by driving the address lines and clocking the
pipeline register.
The RAM may also be read and written by the Serial Protocol
Channel (SPC). This is the typical path for loading the RAM after
power up.
Initialize Counter
The Initialize Counter provides the Initial address to the RAM after reset of the part. A pulse applied to the Initialize pin causes the
Initialize Counter to be gated to the RAM address and the RAM data
to be preset into the pipeline register. This provides an initial value
in the pipeline register before the first clock pulse arrives. The
Initialize Counter can be reset to zero at power up of the chip and
can be loaded with a value other than zero by the SPC. Once
loaded with a value by the SPC, this value is used in further Chip
reset operations.
Serial Protocol Channel
The Serial Protocol Channel (SPC) logicconsistsofa 16-bitdata
shift register, an S-bit command register and clock logic consisting
of gates and a flip-flop. A block diagram of the command decode
logic is shown for reference. The command decode logic decodes
and executes the command in the command shift register using
the clock from the clock logic. The command is divided into two
four-bi.t fields. The most significant four bits of the command register define the command to be executed: read, write, etc. The least
significant four bits define the register to be read or written. (NOTE:
The data to the SPC is shifted in LSB first.)
The SPC is connected to the outside world through four wires.
These wires consist of serial data in and out, a shift clock and a
command/data line. When the command/data line is high, commands are shifted from the serial data in to the command register
by the clock. When the command/data line is low, data is shifted
into the data shift register by the clock. When the command/data
line transitions from high (command) to low (data), a clock pulse is
generated internally to the command decode logic. This pulse
lasts from the beginning of the high-to-Iow transition to the next
serial clock pulse and is used to execute the command in the
command register.
Two of the defined commands are Serial and StUb. These commands control a latch which determines the source of the serial
data out in the command mode. The Serial command causes the
data output to be taken from the last stage of the command shift
Set-up Register
The Set-up Register is a 16-bit register used to set the chip operating mode and to read back chip operating status conditions. A
command word written into the Set-up Register sets 7 latches
" which control the chip operating conditions. Reading the Set-up
Register provides the current status of these 7 latches and various
other signals on the Chip. At power up, the 7 latches are cleared to
zero and the Initialize counter is cleared to zero. The format of the
Set-up Register is shown in the Set-up Register Format table.
. The Set-up Register has 7 latches which determine the operatIng mode of the chip. These are CS 1 , CSa, Non-Reg Hi~ NonReg Lo~, BC RAM, Break P~and Trace. The CS 1 and CS a bits
determine the polarity of the CS 1 and eSa Chip enables. The NonReg High and Low bits setthe upper and lower bytes of the Pipeline
Register to a flow-through mode, respectively. The BC RAM bit
determines the source of the data for breakpoint comparison,
either the Pipeline Register or the RAM address. The Break Pipe
latch switches the breakpoint pin multiplexer from the comparator
to the buffer flip-flop. The trace latch sets the chip into the Trace
mode.
S4-231
- - - - - - - - - - - - - - - _.. _.
__ _---_
...
....... _...
91
J
IDT11502S/IDT11502L CMOS STATIC RAM
64K (4Kx 16·BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Power Up State
Power up is defined as taking Vee from below 1.0 volts to
5.0 volts nominal. This generates power up reset, an Internal signal
which resets several registers on the chip. After power up, the
IDT715021s in the following state:
• Set-up Register cleared to zero
• Initialize Counter cleared to zero
• Breakpoint Mask Register cleared to equal (Breakpoint output
high)
Note that taking Vee from 5.0 volts to 2.0 volts and back to
5.0 volts will not cause power up reset.
Set-up Register: Programmable Chip Enable
The chip enable function Is programmable by bits In the Set-up
Register. The logiC for this is shown in Figure 1. The bits in the Setup Register define the active state of each chip enable: high or low.
This allows up to four RAMs to be cascaded in depth with no
external decoders required (16K x 16 bits of RAM).
• SOE Flip-Flop cleared to outputs off
}-...,.._ _ _ _ _ _ _ _ _•
cr
TO~
FLIP-FLOP
BREAKPOINT
COMPARATOR
~o
WRITE FROM SPR - - - - - - - {
Figure 1. Chip Enable Logic Block Diagram
S4-232
)---_~~
WRITE To RAM
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Set-up Register: Non-Registered Outputs
Two bits of the Set-up Register, Non-Reg Hi and Non-Reg La,
can be setto cause the Pipeline Register bits 15-9 and 7-0, respectively, to be set to the flow-through mode. In the flow-through
mode, both latches of the register are open and the register acts
like a simple buffer with its outputfollowing its input. This allows the
user to have some non-registered bits in microcode applications.
The output circuit consisting ofthe Pipeline Register, the ~nchro
nous Output Enable (SOE), and the Output Enable (OE), has
some special logic to support this mode, as shown in Figure 2.
NON-REG HI
Also, activating the Initialize pin causes the Pipeline Register to be
put in the flow-through mode. Figure 2 shows the Pipeline Register
as two latches operated in the MASTER/SLAVE configuration. The
clock input will cause the latch pair to work as a regist~r. If the Initialize pin is activated, both registers will be placed in the flowthrough mode by the OR gates. Also, if either Non-Reg bit is set, its
corresponding S-bit portion of the register will be placed in the
flow-through mode.
RAM DATAoUT
MUX
NON-REG
15-8
La
RAM DATAoUT
MUX
7-0
INITIALIzE
MASTER
LATCH
SLAVE
LATCH
CLOCK~r---~----~~---------------------+------~~
sot~~-------+-r------------~------~r-----~r-----------~
ot----------------------~---------+--------------~
~------------------------~--------~------------------~
DATAoUT
15-8
DATA OUT
7-0
Figure 2. Output logic Block Diagram
When in the flow-through mode, the output enable flip-flop for
that half must also be in the flow-through mode for external chip
expansion to work properly. A non-registered RAM bit must be enabled by a non-registered output enable, while a registered bit
must be enabled by a synchronous output enable. This is done by
using the non~stered bit to control a multiplexer which selects
between the SOE flip-flop input and output as the source of the
output enable.
S4-233
IDT715028/1DT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Set-up Register: Breakpoint Comparator Control
The Breakpoint Comparator (BC) provides a masked 16-bit
comparison of the various data paths that can be read by the SPC.
It consists of an equal-comparator and .the Break Data and Mask
registers, as shown in Breakpoint Comparator Logic Block Diagram (Figure 3). The BC compares the data from the chip against
the data In the Break Data Register and activates the Breakpoint
Compare output if the two are equa/. The Mask Register enables
comparison: if a bit in the Mask Register is a one, comparison is
enabled on the corresponding bit in the Break Data Register. If it is
zero, the comparison on the that bit is disabled: Le., forced to
equal.
The Breakpoint output is an open drain type to allow width expansion of the Breakpoint Comparison. For example, if two
IDT71502 chips have their breakpoint pins tied together to the
same load resistor, both breakpoint comparators must be valid
before the output can rise. The result is a 32-bit comparison.
A selectable flip-flop is provided for the Breakpoint Output. This
allows pipeline registered bits, non-registered bits and address
bits to be used in comparison with the same timing. Breakpoint
comparison is commonly performed on the pipeline register outputs. These outputs are valid after the clock; Le. for the current
cycle. Address inputs and non-pipe lined outputs are valid before
the clock, representing address and data for the next cycle,
respectively. If address or non-pipelined outputs are to be used in
breakpoint comparison, a flip-flop delay must be added so that
they will be valid after the clock in the same manner as pipelined
bits. The selectable flip-flop provides this delay so that all
breakpoint comparison outputs are valid in the current cycle.
The Breakpoint output driver is enabled by the SOE Flip-Flop to
allow depth expansion of the comparison. SOE must be low prior
to clock going high whether in pipelined mode or not.
TO/FROM SPC
RAM ADDRESS INPUTS - -......
PIPELINE REGISTER --~...
1....--..-...
RAM ADDRESS SELECT
(SET-UP REGISTER BIT) ----~
BREAKPOINT
COMPARE
CLOCK----------------~
BREAKPOINT PIPELINE __________________________--'
(SET-UP REGISTER BIT)
Figure 3. Breakpoint Comparator Logic Block Diagram
Set-up Register: .Trace Mode Operation
When the trace bit In the Set-up Register is set, the chip Is in the
Trace mode. In this mode, data from the chip data pins,
1/0 15 - 1100 , is written into sequential locations in the RAM . The
address for the RAM comes from the Initialize Counter, which is incremented after each RAM write. The Trace mode is used to record
external data events in the same manner as a logic analyzer. The
Trace mode recording sequence is as follows:
1. Data from the 1/0 pins is written into the Pipeline Register by the
clock.
2. Data in the Pipeline Register is written into the RAM by a oneshot driven by the trailing edge of the clock. The RAM address
comes from the Initialize Counter.
3. The Initialize Counter is incremented by the trailing edge of the
RAM write pulse.
Trace operation requires both WE and CS to be active. If either
is inactive (high), the Initialize Register will not be incremented and
data will not be written into the RAM. The Pipeline Register will be
loaded, however. This allows the write enable to be used for skippingwords. A timing diagram of this logic is shown in the Trace
Mode Sequence Timing Diagram (Figure 4).
The RAM write pulse is generated by an internal one-shot triggered by the clock. Data is written into the RAM Immediately
following pipeline register load and the Initialize Counter is incremented by the trailirig edge of the write pulse~ Using an intemally
generated write pulse makes RAM writing independent of clock
high and low times. A timing diagram of the RAM clocking is shown
in the Trace Mode Clock Timing Diagram (Figure 5).
84-234
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLOCK
cr. WE"
SyNC WE
TCLK
(RAM WRITE)
-Wl
i
I
I
PIPELINE REGISTER
INPUT
~
I
PIPELINE REGISTER
OUTPUT
=x
X
X
~
D
I
B
I
i
I
5
~
C
I
Al
I
i
INITIALIZE COUNTER
(RAM ADDRESS)
~
I
I
I
i
B
i
I
X
I
C
i
~
E
F
I
X
X
D
I
i
n
fl
i
I
I
i
I
I
I
I
i
~
I
C
lE
i
X
6
I
i
X
7
Figure 4. Trace Mode Sequence Timing Diagram
CLOCK
TCLK
(RAM WRITE)
I
PIPELINE REGISTER
INPUT
PIPELINE REGISTER
OUTPUT
!
j
DATA X
+
_ __
b....,..!__
-+!_-IX DATA X +
D_A_TA_X
_ _-r-____________
i
INITIALIZE COUNTER
(RAM ADDRESS)
~t-_D_A_TA_X_+_2
1
i
1
i
--Il_--I:~_N__---,Xi} >X__N_+_1_ _ _ _....: _ _ _ __
i
RAM DATA
OLD
lx:::/:.
===================
····=:=====:'X:======D=A=TA=X============
Figure 5. Trace Mode Clock Timing Diagram
S4-235
[I
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Parity Output
The Parity Output pin is generated from a 16-bit parity tree,. as
shown in the Parity Tree Logic Block Diagram (Figure 6). Even parity is used. Parity is generated on the contents of the Pipeline Register. The parity output driver is three-state and is enabled by the
SOE Flip-Flop to allow depth expansion of the parity output.
The Parity Output always reflects the parity of the registered
value. Additional flip-flops and multiplexers are included in the
parity tree to cover the case of non-registered outputs. If one or
REGISTER BIT 15
REGISTER BIT 14
REGISTER BIT 13
REGISTER BIT 12
REGISTER BIT 11
REGISTER BIT 10
REGISTER BIT 9
REGISTER BIT 8
REGISTER BIT 7
REGISTER BIT 6
REGISTER BIT 5
REGISTER BIT 4
REGISTER BIT 3
REGISTER BIT 2
REGISTER BIT 1
REGISTER BIT 0
both bytes of the Pipeline Register are set to the Non-Registered
mode, a flip-flop pipeline delay is added to the corresponding byte
parity chain to make the result of that byte parity calculation the
same as If the Pipeline Register was not in the Non-Pipelined
mode. SOE must be low prior to the clock going high in pipelined
or non-pipelined mode.
~l9
~l9
CLOCK
NON-REGISTER HI BYTE
OUTPUT DRIVER
D--{{-
~l9
~l9
PARITY OUTPUT
'S'OE" FLIP-FLOP
NON-REGISTER La BYTE
Figure 6. Parity Tree Logic Block Diagram
S4-236
..-..- - - ..-..
-~~-~~~~~-~---------~~~----------
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
REGISTERED RAM APPLICATIONS
Using' the Registered RAM in Writable Control
Stores
16-bit microprogram-controlled system using the IDT71502 is
shown in Writable Control Store Using Registered RAM (Figure 7).
The system shown uses four IDT71502 Registered RAM chips to
provide 4K x 64 bits of microcode writable control store.
The IDT71502 Registered RAM is designed expressly for efficient use in writable control stores. A simplified block diagram of a
16-BIT DATA BUS
BOARD
DIAGNOSTIC ACCESS
-.
CONDITION
CODE TEST
LOGIC
,
I
,f
IDT39C10A
MICROPROGRAM
SEQUENCER
MICROCODE
LOAD LOGIC
•,
IDT71502
REGISTERED
RAM
BITS 16-31
IDT71502
REGISTERED
RAM
BITS 0= 15
,
IDT71502
REGISTERED
RAM
BITS 32-47
+
SYSTEM CONTROL BITS
j
IDT71502
REGISTERED
RAM
BITS 48-63
+
+
~
-;u
-ga;
01::
....... 1::
CJ) 01\1
en ... .c:
a. U
~
,
...
IDT49C402
REGISTER
AND ALU
Figure 7. Writable Control Store Using Registered RAM
Using the Parity Output
The parity output can be used in conjunction with an additional
IDT71502 Registered RAM to provide parity checking for control
stores. This is shown in the Parity Check in a Writable Control Store
System (Figure 8) block diagram. The parity outputdriver is gated
Serial Protocol Channel TN
-
v
V
IDT71502
4Kx 16
REGISTERED
RAM
#0
by the SOE Flip-Flop. This allows simple depth expansion of the
parity function by paralleling the parity outputs in the same manner
as the data outputs, as shown in the Parity Check in a Depth Expanded Writable Control Store System (Figure 9) block diagram.
---
~
V
IDT71502
4Kx 16
REGISTERED
RAM
IOT71502
4Kx 16
REGISTERED
RAM
#7
PARITY BITS
....>-
....>-...
1\1
-...
1\1
a.
a.
t
8-BIT
COMPARATOR
IOT74FCT521 A
,
...
PARITY
ERROR
,~
-----
,
"
CONTROL BITS 112-127
CONTROL BITS 0-15
Figure 8. Parity Check In a Writable Control Store System
S4-237
..
-.---....
---------~-------~----
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K X 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SERIAL PROTOCOL CHANNEL
---v
y
-~=~
10T71502
4Kx 16
REGISTERED
RAM
10T71502
4Kx 16
REGISTERED
RAM
10T71502
4Kx 16
REGISTERED
RAM
#7
PARITY BITS
#0
------
BANKO
I
I
--
--\I
V
Y
-f----
IDT71502
4Kx 16
REGISTERED
RAM
IDT71502
4Kx 16
REGISTERED·
RAM
IDT71502
4Kx 16
REGI3TERED
RAM
#0
#7
PARITY BITS
BANK 1
-f----
,
...>-
...>-
-..
..
-
III
Q.
8-BIT
COMPARATOR
IDT74FCT521 A
III
Q.
+----"
CONTROL BITS 0-15
,~
"
CONTROL BITS 112-127
Figure 9. Parity Check In a Depth Expanded Writable Control Store System
S4-238
..
~
PARITY
ERROR
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-B1n REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Using Trace Mode as a Logic Analyzer
The Trace mode allows the IDT71502 to be used as an on-board
logic analyzer for system diagnostics. It is particularly powerful
when used in conjunction with the Breakpoint function. In the
Trace mode, data is recorded in sequential locations in the RAM as
controlled by the Trace Counter. Since the incoming data is
clocked into the pipeline register, the set-up and hold times are
short and compatible with capturing changing bus data, for example. A block diagram of a system with an IDT71502 used in the
Trace mode is shown in Diagnostic Bus Monitoring Using Trace
Mode (Figure 10).
The Breakpoint outputs from the IDT71502 devices in a system
can be used to control the Trace mode writing. The Breakpoint
outputs are open drain types which provide a wire-AND function
when connected together to a single pull-up resistor. By tying the
Breakpoint outputs for the writable control store RAMs and the
trace RAM, a breakpoint comparison can be made over the full
, microcode word plus the data bus contents. This comparison can
be used to enable the trace write so that only data which occurred
at the Breakpoint times is recorded. This allows recording the data
that was on the bus during each instance of an I/O write, for
example.
BOARD
DIAGNOSTIC ACCESS
MICROCODE
LOAD LOGIC
16-BIT DATA BUS
CONDITION
CODE TEST
LOGIC
'
....
c
o
a.
.:.:
IU
CD
...
m
IDT71502
REGISTERED
RAM
IDT71502
REGISTERED
RAM
IDT71502
REGISTERED
RAM
IDT71502
REGISTERED
RAM
o
o
....o
...o
a..
-;u
...CD
C/)
IDT49C402
REGISTER
AND ALU
SYSTEM CONTROL BITS
Figure 10. Diagnostic Bus Monitoring Using Trace Mode
S4-239
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Serial Loading of the IDT71502 Using the SPC
In order to use the 10T71502 in writable control store applications, it must be loaded with the microprogram before use. This is
done using the Serial Protocol Channel (SPC). Loading the RAM
over the SPC can be done in several ways. The microcode can be
loaded from a central microprocessor, which can perform both
microcode load and system diagnostics at power up, or it can be
,loaded using dedicated load logic.
An example of a design of this dedicated load logic is shown In
the Microcode Load Logic Example (Figure 11). The purpose of
this example is to show how one goes about designing this logic.
This example shows an approach which loads the RAMs with data
from a single EPROM. The load logic gets the SPC command and
data information from the EPROM. It Is controlled by single byte instructions from the same EPROM. The format of these instructions
is shown in Microcode Load Logic Instruction Formats (Figure 12),
and a map of the typical contents of the EPROM is shown in
Microcode Load EPROM Memory Map (Figure 13).
The load logic consists of a 16-bit address counter, an 8-bit shift
register, a 4-bit byte counter and a PAL containing a 2-bit instruction register. The logic In the PAL interprets the 2-bit load instructions to cause bytes of command or data information to be loaded
into the 10T74 FCT299 shift register and shifted to the SPC. The two
10T74FCT161 counters are used to count the bytes being sent and
the 8 bits in each byte.
POW~~S~~ _ _ _ _ _ _-r-R...;;.ES_E;.;..T~. . .
CLOCK
SERIAL DATA
TO IDT71502S
SERIAL CLOCK
COMMAND/DATA
END OF LOAD
Figure 11. Microcode Load Logic Example
I I I
BYTE COUNT
LOAD COMMAND
I I
BYTE COUNT
LOAD COMMAND
USING SLOW CLOCK
BYTE COUNT
LOAD DATA
BYTE COUNT
STOP, END OF LOOP
0
0
I
0
II I
0
II I
Figure 12. Microcode Load Logic Instruction Formats
S4-240
IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EPROM
ADDRESS
0000
EPROM Data
o
I I
0001
COMMAND BYTE 0
0002
COMMAND BYTE 1
0003
COMMAND BYTE 2
0004
COMMAND BYTE 3
0005
J
1
I
0
8
0006
DATA BYTE 0
0007
DATA BYTE 1
OOOB
DATA BYTE 7
OOOC
01
0
I
OOOD
LOAD 4 COMMAND BYTES
4
0
LOAD 8 DATA BYTES
4
LOAD 4 COMMAND BYTES
COMMAND BYTE 0
ETC.
xxxx
I I
o
STOP, END OF LOOP
Figure 13. Microcode Load EPROM Memory Map
ORDERING INFORMATION
IDT
xxxx
A
999
A
A
Device Type
Power
Speed
Package
Process/
Temperature
Range
y:,"k
C
L-_ _ _ _ _ _ _ _ _ _ _ _ _
~
J
25
Commercial only }
35
45
55
Military Only
L
S
L---------------------;71502
S4-241
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Sidebraze DIP
Plastic DIP
48-Lead LCC
52-Lead PLCC
P
L - - - - - - - - - I L48
L--------------l
Commercial (O°C to
.
Speed in Nanoseconds
Low Power
Standard Power
64K (4K x 16-Bit) Registered RAM
t;)
CMOS STATIC RAM
64K (4K x 16-BIT)
LATCHED CacheRAM™
Integrated DevJce~ Inc.
I
.1
lOT 71586
FEATURES:
DESCRIPTION:
• Wide 4K x 16 Organization
• High-speed access
- Commercial: 24/35/45/55ns (max.)
- Military: 35/45/55ns (max.)
• Intemal fast 12-bit address latch (5ns set-up & hold times)
• Best fit for popular cache configurations:
- Intel 82385 cache controller (for 80386)
- ID179R3000 RISC CPU Instruction & data caches
- Chips & Technologies 82C307 cache controller (for 80386)
• Fast Output Enable - 10ns (max.)
• Separate enables for upper and lower bytes
• Packaged in 40 pin, 600 mil CERDIP or plastic DIP, or 44 pin
PLCC
The 10171586 Is a fast 4K x 16 latched address CMOS static
RAM designed to enhance cache memory designs. This device offers improved circuit board densities over designs using traditional
RAM architectures in caches for the Intel 80386/82385 the Chips &
Technologies 82C307, and the ID179R3000 RISC CPU.
The 10171586 boasts a fast address access time down to 24ns
(max.), a very fast 10ns (max.) Output Enable pin, and short set-up
and hold times (5ns max.) on the address input latch. All of these
features help the 10171586 to make the most efficient use of
CPU-local buses.
Fabricated using IDT's·CEMOS ™ high-performance technology, the 10171586 achieves this high throughput at a typical operating power of only 300mW.
All inputs and outputs of the ID171586 are TTL-compatible, and
the device operates from a standard 5V supply, simplifying system
design. The ID171586 is offered in a 40 pin CERDIP or plastic DIP,
or a 44 pin plastic lead less chip carrier, providing high board level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
All
A
10
----"
A9
A8
A7
A6
LATCH t - - - - t
As
65,536-BIT
MEMORY
A4
A3
A2
Al
Ao
ALEN
-----.I
WE
----t
~u - - - - t
~L - - . - I
OE
CONTROL
LOGIC
cr
CEMOS and CacheRAM are trademarks of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
QSC-l042/1
1989 Integrated DevIce Technology. Inc.
54-242
IDT7l586 CMOS STATIC RAM
64K (4K X l6-BIT) LATCHED CacheRAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
INDE
WUUUU!!w:....:uuw
:J 7 6 5 4 3
D12
Dll
Dl0
D9
D8
GND
NC
D7
De
Ds
D4
:J 8
:J 9
:l 10
:l 11
:l 12
:l 13
:l 14
:J 15
? '":
444342 41 40 [
39
38[
37[
38[
35[
J44-1
34[
:l Ie
NC
NC
All
Al0
A9
33[:
GND
NC
32[:
31[:
A8
A7
3D£:
Ae
As
:l 17
29[:
181920 2122 232425262728
nnr'!!""!nnnnnnn
PLCC
TOP VIEW
DIP
TOP VIEW
PIN NAMES
Ao -All
Address Inputs
Do - D15
Data Input/Output
cr
Chip Enable/Power-Down
~
Upper Byte Select
CSt.
Lower Byte Select
~
Write Enable
or=
ALEN
SPEED SELECTION
I DT79R3000
SPEED
GND
Ground
Vcc
Power
SUGGESTED
IDT7l586
-
16MHz
71586555
12MHz
20MHz
71586S45
16MHz
25MHz
71586535
20-25MHz
33MHz
71586525
Output Enable
Address latch Enable
80386
SPEED
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
(1)
Military
VALUE
UNIT
-0.5 to +7.0
V
VTERM
Terminal Voltage with
Respect to GND
TA
Operating Temperature
-55 to +125
TBIAS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
°C
Pr
Power Dissipation Plastic
Hermetic
1.5
2.0
W
W
lOUT
DC Output Current
50
mA
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V
O°C to +70°C
OV
5.0V
Vee
± 10%
± 10%
°C
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
Vce
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
-
6.0
V
V1L
Input Low Voltage
-0.5V(I)
-
0.8
V
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
S4-243
UNIT
IDT71586 CMOS STATIC RAM
64K (4Kx 16-BIT) LATCHED CacheRAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE
RANGE (Vce-- 50V -+10%)
SYMBOL
Ilu l
PARAMETERS
VOH
JlA
-
10
JlA
0.4
10L = SmA, Vee= Min.
-
10H = -4mA, Vee = Min.
2.4
a: = \'IH ,'6ur = OVtoVee ,
Vce= Max.
Output High Voltage
UNIT
10
Output Leakage Current
Output Low Voltage
(Do - 0 15)
MAX.
-
Vee = 5.5V, V1N = OV to Vcc
IILol
VOL
MIN.
TEST CONDITIONS
Input Leakage Current
10L = 6mA, Vee= Min.
V
0.5
-
V
I
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) Vce=
IDT71586S25
SYMBOL
PARAMETER
Operating Power
Supply Current
IDT71586S45
1DT71586S55
TEST CONDITIONS
UNIT
COM'L
lee
5.0V ±10%, VLe = 0.2V, ~e = ~e - 0.2V
IDT71586S35
CE = \'IL
Outputs Open
Vee= Max., f = 0(2)
MIL
130
,t::Et:
COM'L
MIL
COM'L
MIL
COM'L
MIL
130
150
130
150
130
150
240
290
240
290
240
290
•.......•.
Ice2
Dynamic Operating
Current
CE =\'IL
Outputs Open
Vee = Max., f = fMAX (2)
Standby Power
Supply Current
(TTL Level Inputs)
CE ~VIH
Outputs Open
Vee = Max., f = fMAX (2)
Full Standby Power
Supply Current
(CMOS Level Inputs)
CE ~VHe
\'IN s: VLe or V1N ~ VHC
Vee = Max., f = 0(2)
·:·;::·:t:.
240
.::::::'::':;:;;;;:'
mA
ISB
ISBl
70··?;ii::!i::::::::· _
70
70
70
70
70
70
15
20
15
20
15
20
.,}::,::,:,/?
..::::::::':"::?
-
NOTES.
1. All values are maximum guaranteed values.
2. At f = fMAl( , address and data Inputs are cycling at the maximum frequency of read cycles of 1It RC • f = 0 means no input lines change.
S4-244
1DT71586 CMOS STATIC RAM
64K (4K X 16-BIT) LATCH ED Cache RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
:q
+5V
DATA OUT
255Q
604Q
DATA OUT
30pF*
255Q
Figure 1. Output Load
SYMBOL
C IN
(TA= +25°C f = 10MHz)
PARAMETER(1)
Input Capacitance
6040
5pF*
Figure 2. Output Load
(for t OHZ ' t BHZ' t CHZ ' feLZ
t BLZ • t eLZ • t WHZ ' and few)
*Including scope and jig
CAPACITANCE
:q
+5V
CONDITIONS
MAX.
UNIT
VIN = OV
12
pF
Input/Output Capacitance
VOUT= OV
12
pF
CliO
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
S4-245
0)-
~~...
",g:
~
~
)CO)
"'0
9'::
010
~
.3:
~
~
!j;~
cwr:A.
-1-1
COEA
82385
CACHE
CONTROLLER
0-
:::cO
CALEN
com
•
•
A2
• r-....
•
•
A13
m:D
c»
0::
~
,
•
•
~
:r
CD
ALEN
AO
/' •
V
•
•
A11
OE" M
~
CS[
IDT71586
LATCHED 4Kx 16
CacheRAM
ALEN
AO .
/ •
CE"
(Bank A
Most Significant
Data Bits)
~
•
V A11•
./
\.
'\..
M
CSO
IDT71586
LATCHED 4K x 16
CacheRAM
:D
»
CS[
CE"
(Bank A
Least Significant
Data Bits)
DO • • • 015
./
OE"
::
~
DO • • • 015
en
""~
""
0)
/ /./
00 • • • 015
./
016 ... 031
80386
CPU
•
• /
A2
•
• /
•
A13
•
•
'\.
DO • • • 015
""-
AO
•
•
•
CE"
(Bank B
Most Significant
Data Bits)
A11
ALEN
i'-.
IDT71586
LATCHED 4Kx 16
CacheRAM
OE"
M
CSO
J
CS[
I
~
'"
'\.
DO • • • 015
IDT71586
LATCHED 4Kx 16
AO
CacheRAM
•
•
•
A11
ALEN
(Bank B
Least Significant
Data Bits)
DE
WE
CSO
::
r=
~:D
a:
esc
~
-<
»
z
c
o
a
::
::
m
:D
o
>
r-I
m
::
"tI
m
:D
~
c:
:D
m
:D
»
z
!i).
m
en·
01~o
~::j
LBEO
82A306
CONTROL
BUFFER
0;0
~~
.::fen
!j;en
-t-t
O~
:xmO
o:g
CWEO
CFIDO
CALE
CRI)f
0>
11)::
CWET
"
()
•
•
A2
•
•
82C307
CACHE
CONTROLLER
....
~
"en
)(~
'[BE""f
[8E2
'["B"E3
~
•
A13
• l"•
/
V
ALEN
AO
•
•
A11
•
DE WE
CSU
::I"
CD
esc
IDT71586
LATCHED 4Kx 16
CacheRAM
/
cr
(Bank 0
Most Significant
Data Bits)
~
ALEN
AO
•
•
V A11•
DE
WE CSU
IDT71586
LATCHED 4Kx 16
CacheRAM
esc
:g
>
::
CE'
(Bank 0
Least Significant
Data Bits)
DO • • • 015
./
DO • • • 015
./
en
~
I
N
~
/ //
DO • • • 015
/
016 ••• 031
•
• /
A2
•
• V
•
A13
80386
CPU
•
•
'\.
'\.
"\..
DO • • • 015
"'"'-
AO
•
•
•
(Bank 1
Most Significant
Data Bits)
A11
ALEN
~
IDT71586
LATCHED 4K x 16
CacheRAM
DE
WE
CSU
cr
esc
~
'"
'\..
DO • • • 015
IDT71586
LATCHED 4Kx 16
AO
CacAeRAM
·••
(Bank 1
Least Significant
Data Bits)
.
A11
ALEN
OE:
WE
CSU
::
;::
~
:g
CE'
esc
-<
>
z
o
8
::
::
m
:g
o
;;
r-
-t
m
::
"U
m
:g
~
c:
:g
m
Figure 4. Example Cache for Intel 80386 using 10171586 Latched Cache RAM and Chips & Technologies 82C307.
:g
>
z
Cil
In
en
01~c
IWr
IRd
""::1
""g:
XOI
'i:-
lelk
-0
9'3:
•
•
AdrLo(2)
•
•
•
AdrLo(13)
•
•
Data(O)
•
•
•
Data(15)
"
"'"
I
/
V
•
•
•
wr=. csa esc
I
cr
\J
~
V
ALEN DE
AO
IDT71586
LATCHED 4K X 16
Cache RAM
CE H
A11
(Most Significant
Instruction Bits)
•
•
•
V
/
/
ala
I
esc
ALEN OE' WE CSU
AO
IDT71586
LATCHED 4Kx 16
CacheRAM
/ •
•
•
A11
V
DO ••• D15
DO ••• D15
/
I
r
I
wr=. csu
ALEN DE
CS[
AO
IDT71586
LATCHED 4K x 16
CacheRAM
H
A11
(Least Significant
Instruction Bits)
3:
>-1
/
(Instruction Tag
Address Bits)
ALEN DE" WE CSU CS[
AO
IDT71586
LATCHED 4Kx 16
CacheRAM
CEH
A11
(Instruction Parity.
Tag. & Valid Bits)
/ •
•
CE H
•
V
V
\;
DO ••• D15
DO ••• D11 D12 D13 D14 D15
/
/
/
IDT79R3000
Data Bus
Tao Bus
Tan/Data Paritv
en
~
I
~
Data(16)
~
V
•
•
• /
Data(31)
co
/
Tag(12)
•
•
•
Tag (27)
Tag (28)
Tag (29)
Tag (30)
Tag(31)
TagP(O)
TagP(1)
TagP(2)
TagV
DataP(O)
DataP(1)
DataP(2)
DataP(3)
?§
~
~
~
AO
•
•
\ A•11
1\
(Least Significant
Data Bits)
WE
a:
_1\
csu esc
AO
•
•
•
A11
IDT71586
LATCHED 4K X 16
cacheRAM
(Most Significant
Data Bits)
ALEN Oi:
AO
•
•
•
~\
CE'
A11
WE CSU CS[
T
I 1
\
CD
):0
3:
~..
:>
~
<
~.,;
~~
H ,V
:>
~
:.
~
DO ••• D11 D12 D13 D14 D15
\
IDT71586
LATCHED 4K x 16
Cache RAM
(Data Tag
Address Bits)
ALEN OE
g.
:zJ
\\
DO ••• D15
DO ••• D15
IDT71586
LATCHED 4K X 16
CacheRAM
ALEN Oi:
'\\
~
DO • • • D15
\
~...
>
\
\
m:zJ
C):o
03:
Q)
/
AdrLo Bus
CPU
-I~
0-
:1:0
AO
•
~
_\
WE CSU CS[
l 1-
\J
•
•
A11
IDT71586
LATCHED 4Kx 16
CacheRAM
(Data Parity.
Tag. & Valid Bits)
ALEN OE'
~
3:
;:::
CE"
-
~:zJ
-<
):0
Z
C
CSU CS[
--
83:
3:
m
:zJ
o
);
r-
-I
3:
m
~
m
:zJ
~
C
:zJ
DClk
m
DRd
:zJ
):0
Z
DWr
-----
- - -
Figure 5. Example Instruction and Data Caches for IDT79R3000 using IDT71586 Latched Cache RAM.
Ii)
om
en
IDT71586 CMOS STATIC RAM
64K (4K x 16-BIT) LATCHED Cache RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vcc = 5V ±10%, All Temperature Ranges)
I DT71586S25(1)
PARAMETER
MAX.
MIN.
IDT71586S35(1)
IDT71586S45
IDT71586S55
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
55
UNIT
READ CYCLE
35
-
45
/,{")""ji,,,:{'
10
-
12
10
::)::::::::'::7:,:'{
10
-
15
/,/:,':/\:t,,:;:-
5
5
4
,:;:;;:;:;:;:;:::{,::7.}
5
-
5
Address Latch Hold Time
-
12
5
5
-
tAA
Address Access Time (4)
-
':'::::::":""":i~
35
45
-
55
t AcE
Chip Enable Access Time
tAB
Upper/Lower Byte Chip Select Access Time
=~
45
25
t AC
Read Cycle Time
25
tCH
ALEN High Time (3)
10
tCl
t AS
ALEN Low Time (3)
Address Latch Set-Up Time
tAH
':;::'::::::::.,-
5
15
tOE
Output Enable to Output Valid
- ,',::t:t,\t::::10
-
13
-
15
-
tCLZ
Chip Enable to Output in Low Z (2. 3)
3:::::{)},}}"",-
3
-
3
-
3
tBLZ
Upper/Lower Byte Chip Select to
Output in Low Z (2. 3)
3:1':::':::',ilil:':I;,:,,:,:',
3
-
3
-
3
toLZ
Output Enable to Output in Low Z (2. 3)
:tt:::::t:::tt:,: -
t CHZ '
Chip Disable to Output in High Z (2. 3)
::::::::;:::;;;;;.,;.;,j::}
tBHZ
Upper/Lower Byte Chip Select to
Output in High Z (2. 3)
tOHZ
Output Disable to Output in High Z (2. 3)
20
35
15
20
55
18
-
2
-
2
-
2
-
-
25
-
30
-
35
-
15
ns
,.,',',',',:,:,;,:;:;::
tOH
Output Hold from Address Change
tpu
Chip Enable to Power Up Time (3)
tpD
Chip Disable to Power Down Time (3)
(4)
;iR.)}::)}::
·20
-
25
-
30
.}f;;;;::::;':':;:;;:::::::'
4
-
9
-
13
'::,::@,,:t::::::::::::::
-
3
-
3
-
0
-
0
-
3
,:,}Q):,
::::::'4\\,:::::?
0
-
25
-
35
-
45
-
55
35
NOTES:
1. O°C to + 70°C temperature range only.
2. Transition is measured ± 200mV from low or high impedance voltage with load (Figures 1&2).
3. This parameter is guaranteed, but not tested.
4. This measurement depends on the combination of ALEN high plus an address change. This combination may either happen at the rising edge
of ALEN, or during an address change after ALEN has become high.
S4-249
IDT71586 CMOS STATIC RAM
64K (4K x 16-BIT) LATCH ED CacheRAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE (1)
~-------------------tRC------------------~~
~-------tCH--------~~-------- tcL--------~
,.-------""
ALEN
ADDRESS
VALID ADDRESS 2
~---------+--- tOE------~~
~~----~_+--- tAcE------~
----------------~-
~------- t M (2) 1---1------------""*1
DATA OUT
Vcc Supply
Current
Icc
-.- - - - - - - - - - - -,1"7'----------------""
ISB
NOTES:
1.
Is high throughout a read cycle.
2. The parameter tM is measured either from the first low to high transition of ALEN after the read address has become valid. or from the
stabilization of the read address during the period when ALEN is high. whichever occurs last.
3. The parameter tOH is measured either from the first low to high transition of ALEN after the an address change. or from an address change during
the period when ALEN is high. whichever occurs first.
4. This transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
wr:
S4-250
IDT71586 CMOS STATIC RAM
64K (4K x 16-BIT) LATCHED CacheRAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vcc = 5V ±10%, All Temperature Ranges)
IDT71586S25(1)
IDT71586S35(1)
MIN.
MIN.
MAX.
MAX.
IDT71586S45
MAX.
MIN.
IDT71586S55
MIN,
MAX.
UNIT
WRITE CYCLE
twc
Write Cycle Time
25
35
-
45
-
55
tCH
ALEN High Time
10
.':':::':':'. -
::::\\::::::::::..
10
-
12
-
15
tCl
ALEN Low Time
10
:\:::::~::::::::s
10
-
12
-
15
t AS
tAH
Address Latch Set-Up Time
Address Latch Hold Time
5
4
.:.:.:.:.:.:.:.:.:.:... ::::::':::::::1-
5
5
-
5
5
-
5
5
tAW
Address Valid to End of Write (3)
25:;:;:;:;::::::)\\""
35
-
45
-
55
t ASW
Address Set-Up Time(3)
0 ..:::::.::::::::;::::::: -
0
-
0
-
0
..
r-~ttWc~wp__-r_w_n_'te__p_ul_se_W
__id_th__________________r-_~~~m~-_---+--22-55-------_--~--3300-----------+--44-00----------;
Chip Enable to End of Write
20}{{::::::~:::::::'
Upper/Lower Byte Chip Select to End of
Write
25
Write Recovery Time (3)
o
30
13
Data Hold from Write Time
o
20
15
Data Set-Up Time
40
o
Write to Output in High Z (2)
Output Active from End of Write (2)
ns
-
25
15
18
.0
o
o
5
5
5
NOTES:
1. O°C to + 70°C temperature range only.
2. Transition is measured ± 200mV from low or high impedance voltage with load (Figures 1&2). This parameter is guaranteed, but not tested.
3. This measurement depends on the combination of ALEN high plus an address change. This combination may either happen at the rising edge
of ALEN, or during an address change after ALEN has become high.
- - - - - - - - - - - - - - - - - - - - _ . _.....
S4-251
_-- _--------.
__ __
..
.
....... .
IDT71586 CMOS STATIC RAM
64K (4Kx 16.BIT) LATCHED CacheRAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1, 2)
~--------------------twe------------------~
~--------teH--------~~-------- teL----------~
ALEN
ADDRESS
CSu
or
CSL
_ _ _ _ _ _ _ _ _ _ _ ~----- twp(7)---------~ ~--------------------
DATA OUT
(5)
NOTES:
1. W'C.."CE. or both CSu and CS L must be high during address transitions.
2. A write occurs during the overlap (t BW • tew or twp) of a low CSu or CSL. a low CE". and a low W'C..
3. The parameter tWR is measured from the earlier of CSu • CSL• Ci:. or VIr=. going high either to the first low to high transition of ALEN after an
address change. or to an address change during the period when ALEN is high. whichever occurs first.
4. The parameters tASW and tAW are measured either from the first low to high transition of ALEN after the write address has become valid. or from
the stabilization of the valid write address during the period when ALEN is high. whichever occurs first.
5. During this period the I/O pins are in the output state. and input signals must not be applied.
6. This transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
7. If OE" is low during a
controlled write cycle. the write pulse width must be the larger of twpor (tWHZ + tow) to allow the I/O drivers to tum off
controlled write cycle. this requirement does not apply and the
and data to be placed on the bus for the required tow. If OE" is high during a
write pulse can be as short as the specified t wp .
wr:.
wr:.
S4-252
IDT71586 CMOS STATIC RAM
64K (4K X 16-BIT) LATCHED Cache RAM
, MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING) (1,2)
twc
,
tCH
ALEN
---.-./11'
~tAS
jK
ADDRESS
tCl
"
~V
tAH
VALID ADDRESS
tcw
)/
'f\.
tAW (4)
CSu
'f\.
or
CSl
I-- t WR (3)_
t ASW (4)
"110..
1
tow
tOH
~ VALIDDATA
INPUT ~
I'
/I
TIMING WAVEFORM OF WRITE CYCLE NO.3, (CSu or CSLCONTROLLED TIMING)(1,2)
twc
tCH
ALEN
----./
tCl
~
'f\.
~
~tAS
ADDRESS
:K
V
tAH
VALID ADDRESS
'" f\.
tAw (4)
"' f\..
~
tsw
/
I-- t WR (3)_
t ASW (4)
"'"
1
~
"
tow
tOH _I
VALID INPUT
DATA
,I
/I
NOTES:
1.
or both CSu and CS l must be high during address transitions.
2. A write occurs during the overlap (tsw. tcw or t wp ) of a low CSu or CSl • a low
and a low WE".
3. The parameter tWR is measured from the earlier of CSu • CSl •
or WE" going high either to the first low to high transmon of ALEN after an
address change. or to an address change during the period when ALEN is high. whichever occurs first.
4. The parameters tAsW and tAW are measured either from the first low to high transition of ALEN after the write address has become valid. or from
the stabilization of the valid write address during the period when ALEN is high. whichever occurs first.
wr=. cr.
cr.
a:.
54-253
IDT71586 CMOS STATIC RAM
64K (4Kx 16-BIT) LATCHED CacheRAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE (1)
OUTPUTS
INPUTS
CE
WE
OE
CSu
CSL
ALEN
08 - 0 15
MODE
DO - 0 7
H
X
X
X
X
-
Hi-Z
Hi-Z
Deselected, powered-down (Isa).
X
X
X
H
H
Hi-Z
Hi-Z
Deselected.
-
-
H
-
Hi-Z
Hi-Z
-
H
X
X
-
-
-
-
-
-
L
L
X
L
H
L
L
X
L
L
L
X
H
L
L
X
H
L
L
X
L
L
X
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
Ou~uts
disabled.
Address latch transparent.
Address latch closed.
Hi-Z
Write to upper byte of current address.
Hi-Z
Write to upper byte of latched address.
H
DATA IN
H
L
DATA IN
L
H
Hi-Z
DATA IN
Write to lower byte of current address.
L
L
Hi-Z
DATA IN
Write to lower byte of latched address.
L
L
H
DATA IN
DATA IN
Write to both bytes of current address (Word Write).
L
L
L
DATA IN
DATA IN
Write to both bytes of latched address (Word Write).
L
H
H
DATAoUT
HI-Z
Read upper byte of current address.
L
H
L
DATAoUT
Hi-Z
Read upper byte of latched address.
H
L
H
Hi-Z
DATAoUT
Read lower byte of current address.
H
L
L
Hi-Z
DATAoUT
Read lower byte of latched address.
L
L
H
DATAoUT
DATAoUT
Read both bytes of current address (Word Read).
L
L
L
DATAoUT
DATA OUT
Read both bytes of latched address (Word Read).
NOTE:
1. H = HIGH
L = LOW
X = Don't Care
- = Unrelated
Hi-Z = High Impedance
ORDERING INFORMATION
IDT
Device Type
X
Power
X
X
Package
Process!
Temperature
Range
Y:,onk
D
~--------------~ P
J
~
25
______________________-I 35
45
55
~----------------------------~S
L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
71586
84-254
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Method 5004, Class B
CERDIP
Plastic DIP
Plastic Leadless Chip Carrier
Commercial only
1
Speed in Nanoseconds
Standard-Power
Latched CacheRAM
Multi-Port RAMs
---_._------_._-----------------_._-
MULTI-PORT RAMS
Integrated Device Technology has emerged as the leading
multi-port RAM supplier by combining advanced CEMOS technology with innovative circuit design. With system performance advantages as a goal, we have brought system design expertise together with circuit and technology expertise in defining dual-port
and four-port RAM products. Our dual-port memories are now
industry standards.
The synergistic relationship between advanced process technology, system expertise and unique design capability add value
beyond that normally achieved. As an example, our dual-port
memories provide arbitration along with a completely tested solution to the metastability problem. Various arbitration techniques
are available to the designer to prevent contention and system wait
states. On-chip hardware arbitration, "semaphore" token passing
or software arbitration allow the most efficient memory to be
selected for each application. At IDT, innovation counts only when
it provides system advantages to the user.
Both commercial and military versions of alilDT memories are
available. Our military devices are manufactured and processed
strictly in conformance with all the administrative processing and
performance requirements of MIL-STD-883. Because we anticipated increased military radiation resistance requirements, all devices are also offered with special radiation resistant processing
and guarantees. As the leading supplier of military specialty RAMs,
IDT provides performance and quality levels second to none.
Our commercial dual-port and four-port memories, in fact, share
most processing steps with military devices.
)
/
TABLE OF CONTENTS
PAGE
CONTENTS
Multi-Port RAMs
IDT7130
IDT7140
IDT70104
IDT7010
IDT70101
IDT70105
IDT7132
IDT7142
IDT71321
IDT71421
IDT7012
IDT70121
IDT70125
IDT71322
IDT7133
IDT7143
IDT7134
IDT71342
IDT7024
IDT7005
IDT7025
IDT7006
IDT7M134
lOT 7M135
IDT7M144
lOT 7M145
IDT7M137
IDT7050S/L
IDT7052
8K (1K x 8) Dual-Port RAM (MASTER) (14-260, 14-9, 14-68, S14-63) ....................
8K (1K x 8) Dual-Port RAM (SLAVE) (14-260,14-9, 14-68, S14-63) ......................
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) .... ;.............
High-Speed 1K x 9 Dual-Port Static RAM (14-260,14-9, 14-68, S14-63) ..................
High-Speed 1K x 9 Dual-Port. Static RAM (14-260, 14-9, 14-68, S14-63) ..................
High-Speed 1K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63) ..................
16K (2K x 8) Dual-Port RAM (MASTER) (14-260,14-9, 14-68, S14-63) ...................
16K (2K x 8) Dual-Port RAM (SLAVE) (14-260, 14-:-9, 14-68, S14-63) .....................
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) (14-260,14-9,14-68, S14-63) .........
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) (14-260, 14-9, 14-68, S14-63) ...........
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, S14-63)·. . .. . . . . . . . . . . . ...
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ...........
High-Speed 2K x 9 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ...........
16K (2K x 8) Dual-Port RAM (w/Semaphores) (14-260, 14-9, 14-68, S14-63) ..............
32K (2K x 16) Dual-Port RAM (MASTER) (14-260, 14-9, 14-68, S14-63) ..................
32K (2K x 16) Dual-Port RAM (SLAVE) (14-260,14-9,14-68, S14-63) ....................
32K (4K x 8) Dual-Port RAM (14-260, 14-9, 14-68, S14-63) . . . . . . . .. . . . . . . . . .. .. . . .. . . ..
32K (4K x 8) Dual-Port RAM (w/Semaphores) (14-260, 14-9, 14-68, 14-139, S14-63) .......
High-Speed 4K x 16 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ..........
High-Speed 8K x 8 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ...........
High-Speed 8K x 16 Dual-Port Static RAM (14-260, 14-9, 14-68, 14-139, S14-63) ..........
High-Speed 16K x 8 Dual-Port Static RAM (14-260, 14"-9, 14-68, 14-139, S14-63) ..........
64K (8K x 8) Dual-Port RAM Module .....................•........................
128K (16K x 8) Dual-Port RAM Module ............................................
64K (8K x 8) Dual-Port RAM Module (SLAVE) . . . .. . . . ....... ........ . . . . . . . . . . . . ....
128K (16K x 8) Dual-Port RAM Module (SLAVE) . . .. .. . . . .... ..... . .. . .. .. . . . . . . . ....
256K (32K x 8) Dual-Port RAM Module ............................................
High-Speed 1K x 8 Four-Port Static RAM ............................................
High-Speed 2K x 8 Four-Port Static RAM ............................................
S5-1
S5-1
S5-18
S5-18
S5-19
S5-19
S5-20
S5-20
S5-35
S5-35
S5-51
S5-52
S5-52
S5-53
SS-65
S5-65
S5-79
S5-87
S5-100
S5-103
S5-106
S5-109
13-125
13-125
13-142
13-142
13-135
S5-112
S5-121
(;)
lOT 7130SA/LA
lOT 7140SA/LA
CMOS DUAL-PORT RAMS
Integrated Devicelechnology.lnc.
8K (1 K x 8-BIT)
FEATURES:
• Standard Military Drawing# 5962-86875
• High-speed access
- Military: 45/55/70/90/100/120ns (max.)
DESCRIPTION:
The IDT7130/IDT7140 are high-speed 1K x 8 dual-port static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT7140 "SLAVE" dual-port in 16-bit-or-moreword width systems.
Using the lOT MASTER/SLAVE dual-port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-Chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology, these devices typically operate on only 325mW of power at
maximum access times as fast as 35ns. Low-power (LA) versions
offer battery backup data retention capability, with each dual-port
typically consuming 200J.1.W from a 2V battery.
The IDT7130/7140 devices are packaged in 48-pin sidebraze or
plastic DIPs, 48- or 52-pin LCCs, 52-pin PLCCs, and 48-lead
flatpacks.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
- Commercial: 25/30/35/45/55/70/90/100ns (max.)
• Low-power operation
- IDT7130/40SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- IDT7130/40LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to 16-or-morebits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
•
•
•
•
•
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation - 2V data retention
TTL-compatible, single 5V±10% power supply
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
RANl----~------cr--~______________~
RiW R
CEl---+~------a
CE R
DEL ----d----./
O'ER
A9l
A7l
•
•
IIOOl
A9R
A7R
110 OR
1I07L
1/07R
lIDSVl (l)
tillSVR(l)
A6l
A6R
•
ROW
SELECT
MEMORY
ARRAY
ROW
SELECT
AOL
AOR
ABR
AOl
INTJ2)
~
ARBITRATION
INTERRUPT
LOGIC
_______________________~
AOR
crR
RIWR
INT (2)
R
NOTES:
1. IDT7130 (MASTER): "BO'SY is open drain output ~nd requires pullup resistor.
IDT7140 (SLAVE): BITSYis input.
2. Open drain output: requires pullup resistor.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
DSC-1000/1
© 1989 Integrated Device Technology. Inc.
S5-1
- - - - - - - - - _.._..._.-------------------------------------
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE$
PIN CONFIGURATIONS
L.J L.I L..I L..I •..J I I
L,
L~
L..I L.I
,-' LoJ LJ
6 5 4 3 2 I I 484746 45 44 43
42::
41 C
40 I:
39 C
38 [
371:
L4~-11
36 ::::
F48-1
35[
34 ::
33 C
32::
J 18
31 C
1920 21 222324 2526 272829 30
,.., ,.., " r,
r~
r, r, ,., " r, ro' ,..,
48-PIN LCC/FLATPACK
TOP VIEW
DIP
TOP VIEW
I~.J
~I~
1~~g~~~~~~~§~
INDEX~
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
7 6 5 4 3 2
AlL
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
1I0 0L
1I0 1L
I/02L
1I0 3L
:::8
:::9
J 10
J 11
J 12
J 13
J 14
U 525150 494847
1
J52-1
&
L52-1
J 15
J 16
J 17
J 20
21 22 23 24 25 26 27 28 29 3031 32 33
ot:R
46
45
44
43
42
41
40
39
38
37
36
35
34
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/0 7R
r, ,.., r, " .-, r, ,., r., r., ,., r, r, r,
.J .J .J .J()
0
~
~
~
~ ~
~ ~
2 OOOOOOO
0000Z
::::.::::::::::::::: C!J::::::::::::::::::::::::::-::::
52-PIN LCC/PL.CC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TS1AS
Temperature
Under Bias
TSTG
Storage
Temperature
lOUT
DC Output Current
(1)
. COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
V
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
-0.5 to +7.0
o to
-55 to + 125
DC
-55 to +125
-65 to +135
DC
-55 to +125
-65 to +150
DC
50
50
mA
+70
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
UNIT
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
-
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GRADE
Military
Commercial
S5-2
AMBIENT
TEMPERATURE
GND
Vcc
-55°C to + 125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
1DT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Vee = 5.0V ±10%)
SYMBOL
PARAMETER
1DT7130SA
IDT7140SA
MIN.
MAX.
TEST CONDITIONS
IDT7130LA
IDT7140LA
MIN.
MAX.
UNIT
Output Leakage Current
CE = "iH, VOUT = OV to Vee
-
10
-
5
J1A
VOL
Output Low Voltage (1/00- 1/07)
IOl = 4.0mA
-
0.4
-
0.4
V
VOL
Open Drain Output Low
Voltage (BUSY, INT)
10l = 16mA
-
0.5
-
0.5
V
VOH
Output High Voltage
IOH= -4mA
2.4
-
2.4
-
V
i1ul
Input Leakage Current
Vee = 5.5V, "iN = OV to Vee
-
IILOI
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) (Vee
SYMBOL
PARAMETER
TEST CONDITION
VERSION
MAX.
-
ISB2
Standby Current
(One Port- TTL
Level Inputs)
SA
CEl or CE R ;::: V1H MIL.
LA
Active Port Outputs
Open,1 = 1MAX (4)
COM'L. ~
ISB3
SA
Both Ports CE land MIL.
LA
Full Standby Current
CE R ;::: Vee -0.2V
(Both Ports - All
CMOS Level Inputs) "iN ~ Vce -0.2V or COM'L. ~
"iN ~ 0.2V, 1 = 0(5)
One Port CEl or
SA
MIL.
CE R ;::: Vcc-0.2V
LA
Full Standby Current
V1N ~ Vec -0.2V or
(One Port-All
CMOS Level Inputs, "iN ~ 0.2V
1 = 0(5»)
Active Port Outputs COM't.. ~
Open, 1 = 1MAX (4)
TYP.
MAX.
TYP.
MAX.
230
185
190
145
65
55
65
45
135
110
120
85
30
10
-
-
-
75
75
-
250
180
75
75
24.0
.·,:,470....
75
75
195
155
-
-
-
-
-
-
-
25
25
65
45
25
25
25
25
65
45
-
-
-
-
155
110
40
40
130
95
-
-
-
75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2
15
5
1.0
0.2
15
4
1.0
0.2
15
4
-
-
-
-
-
-
40
35
125
95
45
42
137
105
40
35
115
90
40
35
105
80
~
SA
MIL.
LA
CEl and CE R ;::: V1H
1 = 1MAX (4)
COM'L. ~
MAX.
7130 x 45
7140 x 45
-
COM'L.
Standby Current
(Both Ports- TTL
Level Inputs)
7130 x 35(2)
7140 x 35(2)
-
-
ISB1
J1A
= 5.0V ±10%)
7130 x 30(2)
7140 x 30(2)
TYP.
5
-
SA
LA
CE = "il
Outputs Open
1 = 1MAX (4)
ISB4
TYP.
MIL.
Dynamic Operating
Current (Both Ports
Active)
Icc
7130 x 25(2)
7140 x 25(2)
10
-
170
120 ..
50
50
-
-
1.2
0.4
.i'\"::4g::'}
:-;:-
-
.·ts::\} . 0.4
1.2
:::.:::"'::\",:!E:;::
;f~~d~
.:"(~:;:\:
150
115
::{:::":t;;·:;·::~~
.(,;:;::::m::,:::::t:. --
ir~\:::; :::,:;::
.:::..
.::ft:;~t\:f.:::
-
UNIT
mA
mA
mA
mA
mA
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. At 1 = 1MAX, address and data inputs (except Output Enable) are cycling at the maximum frequency 01 read cycle of 1/tRC, and using "AC TEST
CONDITIONS" 01 input levels 01 GND to 3V.
5. 1 = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
S5-3
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K X S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) (Continued) (Vee ='5.0V ±10%)
TEST CONDITION
VERSION
Dynamic Operating
Current (Both Ports
Active)
CE =\'Il
Outputs Open
f = f MAX (4)
MIL.
SA
COM'L.
~
IS81
Standby Current
(Both Ports - TTL
Level Inputs)
SA
MIL.
LA
CEl and CE R ;::: \'IH
f = f MAX (4)
COM'L. ~
IS82
Standby Current
(One Port- TTL
Level Inputs)
SA
CEl or CE R ;::: VIH MIL.
LA
Active Port Outputs
Open, f = f MAX (4)
COM'L. ~
IS83
SA
Both Ports CE land MIL.
LA
Full Standby Current
CE
~ Vee -0.2V
R
(Both Ports - All
;:::
Vee
-0.2V
or
V
IN
CMOS Level Inputs)
VIN $. 0.2V, f = 0(5) COM'L. ~
ISB4
One Port CEl or
SA
MIL.
LA
CE R ;::: Vee-0.2V
Full Standby Current
\'IN
~
Vee
-0.2V
or
(One Port-All
CMOS Level Inputs, \'IN ~ 0.2V
f,= 0(5»)
•
Active Port Outputs COM'L. ~
Open, f = fMAX (4)
PARAMETER'
SYMBOL
7130x 55
7140 x 55
LA
7130 x 90
7140 x 90
7130 x 100
7140 x 100
7130 x 120(3)
7140 x 120(3) UNIT
TYP.
MAX.
TYP.
MAX.
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
230
185
180
140
65
55
65
45
135
110
115
85
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
225
180
180
135
65
55
60
40
135
110
110
85
30
10
65
65
65
65
25
25
25
25
10
40
40
40
1.0
0.2
200
160
180
130
65
45
55
35
125
100
110
75
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
190
155
180
130
65
45
55
35
125
100
110
75
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
190
155
180
130
65
45
55
35
125
100
110
75
30
10
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
40
35
120
90
40
35
115
85
40
35
110
80
40
35
110
80
40
35
110
80
40
35
100
75
40
35
100
75
,40
35
95
70
40
35
95
70
40
35
95
70
TYP.
Icc
7130 x 70
7140 x 70
MAX. TYP.
MAX.
TYP. MAX.
mA
mA
mA
mA
mA
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. At f = fMAX' address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of 1/tRe, and using ·AC TEST
CONDITIONS· of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
DATA RETENTION CHARACTERISTICS
SYMBOL
VDR
lecDR
PARAMETER
(L Version Only)
IDT7130LA/IDT7140LA
Typ.(1)
MAX.
MIN.
TEST CONDITIONS
Vec for Data Retention
Data Retention Current
-
Ir MIL.
COM'L.
t eDR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
-
-
-
100
4000
j.tA
-
100
1500
IlA
2.0
Vce = 2.0V, CE ;::: Vee -0.2V
0
\'IN ;::: Vee -0.2V or \'IN:5 0.2V
t
NOTES:
1. Vee = 2V, TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
S5-4
UNIT
RC
(2)
V
-
-
ns
-
-
ns
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
GND to 3.0V
Sns
1.SV
1.SV
See Figures 1, 2 & 3
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
SV
DATAoUT
~
7750.
:
SV
12S00
~
DATA OUT.
775!1
100pF* .
30pF for 2Sns, 30ns,
~sns and 4Sns versions)
Figure 1. Output Load
12S00
SpF*
Figure 2; Output Load
(for tHZ,tLZ,t wz , and tow)
* Including scope and jig.
----I
SV
BUSY
or
INT
l
2700
'OOPF'
Figure 3. BUSY and INT
Output Load
Figure 4. BUSY and INT
Output Load (for 25ns and
3~ns versions)
. * Including scope and jig.
S5-5
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (5)
7130
7140
MIN.
PARAMETER
SYMBOL
X
X
7130 X 30(2)
7140 x 30(2)
MAX.
MIN.
25(2)
25(2)
MAX.
7130 X 35<2)
7140 x 35<2)
MIN.
MAX.
7130
7140
MIN.
X
X
45
45
MAX.
UNIT
READ CYCLE
t Rc
Read Cycle Time
25
-
30
tAA
t ACE
Address Access Time
25
-
Chip Enable Access Time
-
25
-
t AOE
Output Enable Access Time
-
12
0
tOH
Output Hold From Address Change
tLZ
Output Low Z Time
tHZ
Output High Z Time (1.4)
tpu
Chip Enable to Power Up Time
tpD
Chip Disable to Power Down Time (4)
0
(1.4)
.
-
45
-
ns
-
35
-
45
ns
-
35
-
45
ns
15
-
25
-
30
ns
::::\:{)\:: .. ·:30
:::::.·4:.::\::::::\:::
.:;:-'.:::@:: :\::\0"':::·
-
0
5
5
-
ns
-
-
0
0
-
12
-
15
-
20
ns
-
0
-
0
-
0
-
ns
50
-
50
-
50
-
50
ns
100
7130
7140
MIN.
..:::::\:. "#,\.:::
~::::;::,<:::::::::n::;:::::··:::::'"1o
(4)
35
=z::.~t.
30
':.:.::::::;:::::"':'::::;;:::;:.
25
tAW
35
1.
25
tAs
twz
~". :.:}::: \{{:::::.
-
30
-
30
45
-
ns
35
ns
35
-
0
-
ns
ns
0
-
0
-
0
-
ns
10
-
12
-
15
-
20
ns
-
0
-
0
-
0
-
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (7)
7130 x 55
7140 x 55
MIN.
MAX.
PARAMETER
SYMBOL
7130 x 70
7140 x 70
MAX.
MIN.
7130 x 90
7140 x 90
MIN. MAX.
7130 x 100
7140 x 100
MIN.
MAX.
7130 x 120(3)
7140 x 120(3)
MIN.
MAX.
UNIT
WRITE CYCLE
70
-
90
50
-
85
40
-
50
-
85
0
-
0
-
0
40
50
-
55
0
-
0
30
-
40
twc
Write Cycle Time(5)
55
tEW
Chip Enable to End of Write
40
tAW
Address Valid to End of Write
tAs
Address Set-up Time
twp
Write Pulse Width(6)
0
-
55
-
-
0
-
0
-
40
-
40
-
-
100
-
90
90
120
-
ns
100
-
ns
100
-
ns
0
ns
tWR
Write Recovery Time
0
tow
Data Valid to End of Write
20
-
tHZ
Output High Z Time(l.
-
30
-
35
-
40
-
40
-
40
ns
tOH
Data Hold Tme
0
-
0
-
0
-
0
-
0
-
ns
twz
Write Enabled to Output in High Z(l. 4)
-
30
-
35
-
40
-
40
-
50
ns
tow
Output Active From End of Write(l. 4)
0
-
0
-
0
-
0
-
0
-
ns
4)
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, t wc = tSM + twp6. Specified for ~ at high (refer to "Timing Waveform of Write Cycle", Note 7).
7. ·x" in part numbers indicates power rating (S or L).
CAPACITANCE
SYMBOL
CIN
C
OUT
(TA= +25°C, f = 1.0MHz)\
PARAMETER(1)
input Capacitance
'
Output Capacitance
CONDITIONS
MAX.
UNIT
= OV
11
pF
Vour= OV
11
pF
VIN
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
S5-8
65
ns
ns
ns
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)
(1,2,3,7)
twc
ADDRESS
~
-----./
<
"K
/
i
tAW
~ r\.
t
I - tAS
Rm
t
(7)
tWR
WP
/'
"I'-.
-
/
(6)-
HZ
,
-t
(6)-
HZ
~twi6)_
tow
~r-
(4)
DATA OUT
~tow
t OH -
-'
"
.......
./
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)
(1,2,3,5)
twc
ADDRESS
~(
)(
tAW
1
/'
tEW
-tAs-11
Rm
tow
"
I'
tWR
tOH
,
'1
NOTES:
1. RiW must be high during all address transitions.
2.
3.
4.
5.
6.
7.
cr
A write occurs during the overlap (tEW or t wp ) of a low
and a low RiW.
tWR is measured from the earlier of CE or RiW going high to the end of the write cycle.
During this period, the 110 pins are in the output state and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or twz + tow to allow the 110 drivers to turn off and
data to be placed on the bus for the required tow. If DE is high during an RNi controlled write cycle, this requirement does not apply and the write
pulse can be as short as the specified t wP .
S5-9
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANG.ES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (8)
7130 X 30(1)
7130 x 2~~l
7140 X 30(1)
SYMBOL
PARAMETER
7140
MIN.
7130 x 35(1)
7140 X 35(1)
MIN.
MAX.
2
X
MAX.
MIN.
MAX.
7130 X 45
7140 x45
MIN.
MAX.
UNIT
BUSY TIMING (FOR MASTER IDT7130 ONLy)
t3US'Y Access Time to Address
troS? Disable Time to Address
t3US'Y Access Time to Chip Enable
25
30;..
..:......
35
35
ns
teDA
t eAc
20
. : : : : :. ··25\::.
30
35
ns
':::;:::::::;:::::::::25
30
30
ns
t eDc
BUSY Disable Time to Chip Enable
20
- .
'.: :
25
25
25
ns
tWDD
Write Pulse to Data Delay (3)
50
h::::::::}:::::.·:::::·
55
60
70
ns
tDDD
Write Data Valid to Read Data Delay (3)
tAPS
Arbitration Priority Set-up Time (4)
teDD
t3US'Y Disable to Valid Data(5)
teM
20
"EIDS? Input(6)
Write to
tWH
Write Hold After "EIDS? (7)
tWDD
Write Pulse to Data Delay(9)
tDDD
Write Data Valid to Read Data Delay(9)
{~:~b::::{~~::'
30
N9.t~¥
0
30
35
::::::\:::5::::
5
BUSY INPUT TIMING (FOR SLAVE IDT7140 ONLy)
twe
·:\I::\~~:::::·
:::;:.
5
Note 5
ns
ns
Note 5
Note 5
ns
'::::::j:::.
":::'"
.::::::::::;:~::.
45
5
::::~r
1§(:::::::~::.:·::::~::;:::·
I.:{:(J;:/:\}:."
..::\;
0
0
0
20
20
20
ns
ns
50
55
60
70
ns
30
30
35
45
ns
120(2)
120(2)
MAX.
UNIT
60
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (5)
SYMBOL
PARAMETER
7130 X 55
7140 X 55
MIN.
MAX.
7130 X 70
7140x 70
MIN.
MAX.
7130 X 90
7140 X 90
MIN.
MAX.
7130 X 100
7140 X 100
MIN.
MAX.
7130
7140
MIN.
X
X
BUSY TIMING (FOR MASTER IDT7130 ONLy)
-
45
-
45
40
-
40
-
45
35
45
50
-
50
-
60
ns
60
ns
60
ns
140
ns
-
30
-
30
80
-
90
Write Data Valid to Read Data Delay(3)
-
55
-
70
-
90
100
-
120
ns
Arbitration Priority Set-up Time (4)
5
-
5
-
5
-
5
-
5
-
ns
rIDS? Disable to Valid Data(5)
-
Note 5
-
Note 5
-
Note 5
-
Note 5
-
Note 5
ns
-
0
-
0
20
-
ns
20
-
0
20
120
-
140
ns
100
-
120
ns
t eDc
tWDD
Write Pulse to Data Delay (3)
tDDD
tAPS
teDD
teDA
t eAc
45
-
rIDS? Access Time to Address
rIDS? Disable Time to Address
rIDS? Access Time to Chip Enable
rIDS? Disable Time to Chip Enable
teM
-
35
45
100
50
50
120
BUSY INPUT TIMING (FOR SLAVE IDT7140 ONLy)
twe
Write to "EIDS? Input(6)
0
-
0
tWH
Write Hold After troS? (7)
20
-
20
tWDD
Write Pulse to Data Delay (9)
80
tDDD
Write Data Valid to Read Data Delay(9)
-
-
55
90
70
-
100
90
-
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Port-to-port delay through RAM cells from writing port to reading port. refer to "Timing Waveform of Read With "EIDS? (For Master IDT7130 only)".
4. To ensure that the earlier of the two ports wins.
5. teDD is a calculated parameter and is the greater of O. t WDD- twp (actual or t DDD - twp (actual)).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
8. ·x· In part numbers indicates power rating (S or L).
.
9. Port-to-port delay through RAM cells from w~iting port to reading port. refer to "Timing Waveform of Read With Port-to-Port Delay (For Slave IDT7140
Only)".
S5-10
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K X S-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY
(1,2,3)
(FOR MASTER IDT7130 ONLy)
twc
W
If
MATCH
J~
J
~
twp
If
~
J
t--tow
~~
DATAINR
tOH
X
VALID
JI\
I
t APS(1) .1
i,)
MATCH
I::.
t SOA -
'--- ~
BOSYL
t soo-
t
twoo
DATAoUTL
tood4)
-E
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. (5"E' at La for the reading port.
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY
(1,2,3)
(FOR SLAVE IDT7140 ONLy)
twc
ADDRR
~IJ
MATCH
JI\
K
twp
J
V
\
J
t--tow
DATAINR
-J-I\.
VALID
I tOH
X
I
ADDRL
MATCH
twoo
--
. ~~ VALID
DATAoUTL
tO~~
NOTES:
1. Assume i3US'? input at HI for the writing port, and 'O!: at La for the reading port.
2.
3.
Write Cycle parameters should be adhered to, to ensure proper writing.
Device is continuously enabled for both ports.
TIMING WAVEFORM OF ~:E~t:1Y INPUT (F~~ S;FNL~
S5-11
---------_.
- - - -..............- - - - - - - - - - - - - -
1DT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
CE L VALID FIRST:
ADDR
LAND R
BUSY R
=x
>C
ADDRESSES MATCH
~,~~. ["~J-
CER VALID FIRST:
ADDR
LAND R
BUSYl
=x
ADDRESSES MATCH
~,~_{ . ["~J-
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION
(1)
LEFT ADDRESS VALID FIRST:
~--- t RC OR twc ------i~
ADDRl
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDRR
BUSY R
RIGHT ADDRESS VALID FIRST:
~--- t Rc
OR twc ------i~
ADDRESSES MATCH
ADDRl
BUSYl
ADDRESSES DO NOT MATCH
1-9_______t_BDA=~~---
NOTE:
1.
CE l = CE R= "'Il
S5-12
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
7130 X 3~~~
7140 X 30
MIN.
MAX.
7130 X 2~~~
7140 X 25
MIN.
MAX.
PARAMETER
7130 X 35(1)
7140 X 35(1)
MAX.
MIN.
7130 X 45
7140 x45
MIN.
MAX.
UNIT
INTERRUPT TIMING
t AS
Address Set-up Time
0
-
tWR
Write Recovery Time
0
-
tiNS
Interrupt Set Time
tlNR
Interrupt Reset Time
0
··:,;::r
0
'.:.:::' ::9,:,;/\ )\:;:.:::::-<:,. .:i
0
30
-
- '.':':':'. : : ,: : : :t. .g5\(
\i:Y{'::\:":;:;:':':'-
::,,:: .;:
-
25
30
-
0
-
ns
0
-
ns
35
-
40
ns
35
40
ns
100
100
MAX.
7130
7140
MIN.
120(2)
120(2)
MAX.
UNIT
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
7130 X 55
7140 X 55
MAX.
MIN.
PARAMETER
7130x 70
7140 X 70
MIN.
MAX.
7130 X 90
7140 X 90
MIN. MAX.
7130
7140
MIN.
X
X
X
X
INTERRUPT TIMING
t AS
Address Set-up Time
0
-
0
0
0
-
0
-
0
0
-
0
Write Recovery Time
-
0
tWR
tiNS
Interrupt Set Time
-
45
-
50
-
60
45
-.
50
-
55
Interrupt Reset Time
tiNA
NOTES.
0
1. O°C to + 70 e temperature range only.
2. -55°e to + 125°e temperature range only.
3. "x" in part numbers indicates power rating (S or L).
55
-
60
TIMING WAVEFORM OF INTERRUPT MODE
-
ns
-
70
ns
-
70
ns
0
(1,2)
LEFT SIDE SETS INTR :
~---------twc--------~
WRITE 3FF
INTA
~_tINS
_ _ _ _ _ _ _ _ _ _ _ __ _
~G~S~:LMA~R~S~~~N~T~R~:~~~~~~~~~~~:~t_w~A~~=====R_E~A_~_:_ff____~~
Rm"~
OE R
INTR
\\\\\\SSS\\\\\S."-S\\\\\\_
.
l=
-.j
I
jltlNR
----------------------------------------
NOTES:
1. eEL = CE A= \\l
2. IN\ and INTR are reset to VOH during power up.
S5-13
.------_.... _--_ ...•... _ - - - - - - - - - - - - -
- - _...._---_....
--------
ns
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT) .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT MODE
(1,2)
.RIGHT SIDE SETS INT L :
~--------------------- twc--------------------~
WRITE 3FE
ADDRR
~_tINS-------------
INTl
LEFT SIDE CLEARS INTL:
ADDRl
~-. t
jr-
RC
~K..K.~""'-JI'-K..K.~""'-JI'-K..K...K..;""'-JI"-.~~~t-w-R----RE-A-D-3-F-E-----1--
NOTES:
1. CEl = CE R= "Il
2. INTR and INTL are reset (high) during power up.
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RIGHT
RiW ----------e-----------_____~ RiW
BUSY
IDT7130
RiW
Riifi
-BU-S-Y MASTER -BU-S-Y 1-------.....------+------- BUSY
+5V
+5V
NOTE:
1. No arbitration in IDT7140 (SLAVE). BUSY-IN inhibits write in IDT7140 (SLAVE).
S5-14
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The 10T7130/40 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The I 0T7 130/40 has an automatic
power down feature controlled by CEo The CE controls on-Chip
power down circuitry that permits th~espective port to go into a
standby mode when not selected (CE high). When a port is enabled, access to the entire mem0!y'?rray is permitted. Each port
has its own Output Enable control (OE). In the read mode, the port's
l5E turns on the output drivers when set LOW. Non-contention
REAO/WRITE conditions are illustrated in Table I.
The interrupt flag (INT) permits communication between ports
or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port.
The left port interrupt flag (INT Ll is set when the right port writes to
memory location 3FE (HEX). The left port clears the interrupt by
reading address location 3FE. Likewise, the right port interrupt flag
(INTA) is set when the left port writes to memory location 3FF (HEX)
and to clear the interrupt flag (INTA ), the right port must read the
memory location 3FF. The message (8 bits) at 3FE or 3FF is userdefined. If the interrupt function is not used, address locations 3FE
and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation.
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to Sns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.
S5-15
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-Chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CELand CE A for access; or (2)
if the CEs are low before an address match, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table III). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its
operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one
will activate its BUSYL while another activates its BUSYA signaL
Both sides are now busy and the CPUs will wait indefinitely for their
port to become free.
To avoid this "Busy Lock-Out" problem, lOT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has BUSY inputs which allow an
interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed, until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold ti me past BUSY to ensure that a write takes place after the contention is resolved. This timing is inherent in all dual-port memory
systems where more than one Chip is active at the same time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to BOSY from the
MASTER.
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READ/WRITE CONTROL(4)
LEFT OR RIGHT PORT
OE
CE
R/W
(1)
FUNCTION
DO-7
X
H
X
Z
Port Disabled and in Power Down
Mode. ISB2 or ISB4
X
H
X
Z
CE R '" CE L = H. Power Down
Mode.lsB1 or ISB3
L
L
X
DATA IN
H
L
L
DATA OUT
H
L
H
Data on Port Written Into Memory (2)
Data in Memory Output on Port (3)
High Impedance Outputs
Z
NOTES:
1.
2.
3.
4.
AOL -A9L"" AOR-A9R
If BUSY = L. data is not written.
If BUSY = L. data may not be valid. see tWDD and tDDD timing.
H = HIGH. L = LOW. X = DON'T CARE. Z = HIGH IMPEDANCE
TABLE ii-INTERRUPT FLAG (1,4)
RIGHT PORT
LEFT PORT
FUNCTION
CE R
OE R
X
X
X
X
X
L(2)
L
L
3FF
H(3)
Reset RiQht INTR FlaQ
L (3)
L
L
3FE
X
X
X
X
Set Left INfL Flag
H(2)
X
X
CE l
OE L
AOl - A9l
INTl
L
L
X
X
X
X
X
3FF
X
X
X
X
X
X
X
·L
L
3FE
R/WL
R/W R
NOTES:
1. Assumes BUSYL = BUSYR = H.
2. If BUSY L = L. then NC.
3.
4.
INTR
AOl -ASR
X
Set Right INT R Flag
Reset Left INT L Flag
If BUSYR = L. then NC.
H = HIGH. L= LOW, X = DON'T CARE, NC= NO CHANGE
TABLE III-ARBITRATION (2)
LEFT PORT
FLAGS
RIGHT PORT
(1)
FUNCTION
CEl
AOl - A9l
CE R
BUSYl
A OR - A9R
BUSYR
H
X
H
H
No Contention
Any
H
X
X
H
L
H
L
H
H
No Contention
X
L
Any
H
H
No Contention
H
H
No Contention
L-PortWins
L
"" AOR-A9R
"" AOL -A9L
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
L
LV5R
H
L
RV5L
L
RV5L
L
H
R-PortWins
Same
L
Same
H
L
Arbitration Resolved
Same
L
Same
L
H
Arbitration Resolved
L-PortWins
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R
= AOR-A9R
LL5R
= AOL -A9L
H
L
RL5L
= AOR-A9R
RL5L
= AOL -A9L
L
H
R-PortWins
LW5R
= AOR-A9R
LW5R
= AOL -A9L
H
L
Arbitration Resolved
LW5R
= AOR-A9R
LW5R
= AOL -A9L
L
H
Arbitration Resolved
NOTE:
1. INT Flags Don't Care.
2. X = DON'T CARE. L = LOW. H = HIGH
LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW ~ 5ns before Right CEo
RL5L = Right CE = LOW ~ 5ns before Left CEo
LW5R = Left and Right CE = LOW within 5ns of each other.
S5-16
IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL·PORT RAMS 8K (1 K x 8.BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
Device Type
A
Power
999
A
A
Speed
Package
Process/
Temperature
Range
Y:,aok
P
C
J
L - - - - - - - - - l L48
L52
F
L-_____________________
~
25
30
35
45
55
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL·STD·883, Class B
Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
48·Pin Leadless Chip Carrier
52· Pin Leadless Chip Carrier
Flatpack
g~~~:~~::: g~:~
Commercial Only
1
Speed in Nanoseconds
70
90
100
120
Military Only
L - ._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I
~
I
SA
Low Power
Standard Power
---jl
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
S5-17
7130
7140
8K (1 K x 8·Bit) MASTER Dual·Port RAM
8K (1 K x 8·Bit) S~VE Dual·Port RAM
Integrated Device1echnoIogy.1nc.
HIGH-SPEED
1K X 9 DUAL-PORT
STATIC RAM WITH BUSY
ADVANCE
INFORMATION
lOT 7010
lOT 70104
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 35/45/55/70ns (max.)
The IDT701 0/1 DT70 104 are high-speed 1K X 9 dual port static
RAMs. The IDT7010 is designed to be used as a stand-alone 9-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT70104 "SLAVE" dual-port in 18-bit-or-more word width systems. Using the lOT MASTER/SLAVE dual-port RAM approach in
18 bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
80th devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
The devices utilize a 9-bit wide data path to allow for control!
data and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking.
Fabricated using lOT's CEMOS'" high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 25ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---JjW from a 2V battery.
The IDT701 0/701 04 devices are packaged in 48-pin sidebrazed
or plastic DIPs, 48- or 52-pin LCCs and 52-pin PLCCs. The military
devices are processed 100% in compliance to the test methods of
MIL-STD-883, method 5004.
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
- IDT7010/70104S
Active: ---mW(typ.)
Standby: --mW(typ.)
- IDT7010/70104L
Active: ---mW(typ.)
Standby: ---mW(typ.)
• Fully asynchronous operation from either port
• Each port has a 9-bit wide data path. The 9th bit could be
used as the parity bit.
• MASTER IDT7010 easily expands data bus width to 18 bits or
more using SLAVE IDT70104 chip
• On-chip port arbitration logic (IDT7010 only)
• BUSY output flag on Master; BUSY input on Slave
• Battery backup operation - 2V data retention
• TTL compatible, signal5V (±10%) power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class 8
FUNCTIONAL BLOCK DIAGRAM
RtWL
~L=====!~[)----I
OE
L
(fOaL
(f08R
I/OoR
(fOOL
'-----------...1-+ l3OS'i'R(I)
(I)BDS'i\-~----------I
ASL - 1 - - - - + 1
ASR
A OL -1----"--+1
AOR
A9L
----,,.--~===~-___,-- A9R
AOL
ARBITRATION
~L - - - t I
LOGIC
N L _ _-tl(IDTlOl00NLY) H - - -
~R
OE
AOR
RtWL
RtWR
R
NOTE:
1. 7010(MASTER): BUSY is open drain output and requires pullup resistor.
70104(SLAVE): BUSY is input.
CEMOS is a trademark of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-l047/-
1989 Integrated Device Technology, Inc.
S5-18
Intesrated Device1echnoIosy.Inc.
HIGH-SPEED
1K x 9 DUAL-PORT
STATIC RAM WITH
INTERRUPT AND BUSY
ADVANCE
INFORMATION
lOT 70101
lOT 70105
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
- IDT70101/70105S
Active: ---mW(typ.)
Standby: --mW(typ.)
- IDT70101/70105L
Active: ---mW(typ.)
Standby: ---mW(typ.)
• Fully asychronous operation from either port
• Each port has a 9-bit wide data path. The 9th bit could be
used as the parity bit.
• MASTER IDT70101 easily expands data bus width to 18 bits
or more using SLAVE IDT70105 chip
• On-chip port arbitration logic (IDT70101 only)
The IDT70101/IDT70105 are high-speed 1K x 9 dual-port static
RAMs. The IDT701 01 is designed to be used as a stand-alone 9-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT70105 "SLAVE" dual-port in 18-bit-or-more word width systems. Using the IDT MASTER/SLAVE dual-port RAM approach in
18 bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
80th devices provide two independent ports with separate control, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
The devices utilize a 9-bit wide data path to allow for data/control and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 25ns. Low-power (L) versions offer, battery backup data retention capability with each port typically
consuming ---',JW from a 2V battery.
.
The IDT701 01/70105 devices are packaged in 52-pin LCCs and
52-pin PLCCs. The military devices are processed 100% in compliance to the test methods of MIL-STD-883, method 5004.
• BUSY output flag on Master; BUSY input on Slave
•
•
•
•
•
INT (INTERRUPT) flag for port-to-port communication
Battery backup operation - 2V data retention
TTL compatible, signal5V (± 10%) power supply
Available in popular hermetic and plastic packages
Military product compliant to MIL-STD-883, Class 8
FUNCTIONAL BLOCK DIAGRAM
RtWl
CEl=====~!:~
Oi:
l
__,
I/OSR
I/08l
I/Ool
IIOOR
L -_ _ _ _ _ _ _- . . _
(1) BUSYl + - 4 . , - - - - - - - - - - '
BUSy (I)
R
A 6l -+---:----+1
AOl -+---"---+1
A6R
AOR
A9l---:~-.r===~----:~- A9R
AOl
ARBITRATION (3)
AOR
eEL - - - o f INTERRUPT 1 + - - - CE'R
OE l
lOGIC
DE'R
RtWl
(1~1J~~OI
RtWR
INT~)------------~
NOTES:
1. 70101 (MASTER): BUSY is open drain output and requires pullup resistor. 70105(SLAVE): BUSY is input.
2. TNT is open drain output and requires pullup resistor.
3. Arbitration Logic is for IDT70101 (master).
lNi~2)
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-l048/-
1989 Integrated Device Technology. Inc.
S5-19
lOT 7132SA/LA
lOT 7142SA/LA
CMOS DUAL-PORT RAM
16K .(2K x a-BIT)·
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70/90/100/120ns (max.)
- Commercial: 25/30/35/45/55/70/90/100ns (max.)
• Low-power operation
The 10T7132/10T7142 are high-speed 2K x 8 dual-port static
RAMs. The 10T7132 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
10T7142 "SLAVE" dual-port in 16-bit-or-moreword width systems.
Using the lOT MASTER/SLAVE dual-port RAM approach In 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
80th devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology, these devices typically operate on only 325mW of power at
maximum access times as fast as 35ns. Low-power (LA) versions
offer battery backup data retention capability, with each dual-port
typically consuming 200I-lW from a 2V battery.
The 10T7132/7142 devices are packaged In 48-pin sidebraze
or plastic OIP, 48- or 52-pin LCC, 52-pin PLCC, and a 48-lead
flatpack.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class 8.
~10T7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- 10T7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER 10T7132 easily expands data bus width to 16-or-more
bits using SLAVE 10T7142
• On-chip port arbitration logic (10T7132 only)
•
•
•
•
•
•
a
BUSYoutput flag on 10T7132; BUSY input on 10T7142
Battery backup operation-2V data retention
TIL-compatible, single 5V±10% power supply
Available In popular hermetic and plastic packages
Military product compliant to MIL-STO-883, Class 8
Standard Military Orawlng# 5962-87002
FUNCTIONAL BLOCK DIAGRAM
R/W L
CE L
D------+~-~+=~
(jEL
A10L
A7L
_____I
•
R/WR
CE R
\....--I:>----
OER
r----r.+-----
Al0R
A7R
IIOoL
1-......- - - - - IIOoR
I/07L
I-..;....e>------ II07R
IDSVL(l)
IDSVR(l)
r--,--+--...:.:....---
A6L
•
ROW
SELECT
A6R
ROW
SELECT
1 4 - - t - - - - - AOR
AOL
""--_---Ii
A10L ------I~I
ARBITRATION
....- - - - - A10R
AOL ------I.~I
LOGIC
....- - - - - AoR
CE L
------I.~I
R/W L ------I.~I
(IDT7132
ONLy)
......
....- - - - -
CE R
"'"1------ R/WR
~--~....I
NOTES:
"1.
IDT7132 (MASTER): tmSVis open drain output and requires pullup resistor.
IDT7142 (SLAVE): BITSY is input.
CEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
OSC-l00l/1
1989 Integrated Device Technology, Inc.
S5-20
IDT7132SA/LA AND 1DT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
L..I L.J L.J L.J 1-' I I L.J L.J L.J
6 5 4
loJ L.J LJ
3 2 I I 48 47 46 45 44 43
':
42:::
41 [
40 [
L48-1
&
F48-1
J 13
J 14
J 15
J 16
J17
37[
36[
35[
34 :::
33[
32:::
31 C
J 18
1920 21222324252627282930
,.,
,.., r, " r., r, r, r, ,., r, r1 ,.,
48-PIN LCC/FLATPACK
TOP VIEW
DIP
TOP VIEW
LJ LJ LJ LJ LJ L.J I I L.J LJ LJ LJ LJ LJ
7
8 5 4
3 2
LJ
1
5251 50 49 48 47
46:::
45 :::
44 :::
OER
AOR
A1R
43C A2R
J 12
J 13
J52-1
&
L52-1
J 14
J 15
J 16
J17
J 18
J 19
J20
21 22 23 24 25 26 27 28 29 3031 32 33
42 :::
41 :::
40:::
39 :::
38::
37::
36:::
35 ::
M[
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NtC
It07R
52-PIN LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
lOUT
DC Output Current
50
50
mA
Military
Commercial
AMBIENT
TEMPERATURE
-55°C to +125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V
Vcc
± 10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
-
6.0
V
-
0.8
V
Input Low Voltage
-0.5(1)
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
S5-21
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Vee = 5.0V±10%)
SYMBOL
IDT7132SA
1DT7142SA
MIN.
MAX.
TEST CONDITIONS·
PARAMETER
IILlI
Input Leakage Current
Vee = 5.5V, ~N = OV to Vee
Output Leakage Current
CE = ~H ,VOUT = OVto Vec
-
10
Illol
VOL
Output Low Voltage (1/00- 1/07)
10l = 4mA
-
VOL
Open Drain Output Low
Voltage (BUSY)
IOl = 16mA
VOH
Output High Voltage
10H= -4mA
0.4
-
-
0.5
2.4
-
10
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) (Vee =
SYMBOL
PARAMETER
TEST CONDITION
7132 x 25(2)
7142 x 25(2)
VERSION
TYP.
MIL.
SA
LA
Dynamic Operating
Current (Both Ports
Active)
CE = \ll
Outputs Open
f = f MAX (4)
Standby Current
(Both Ports - TIL
Level Inputs)
SA
MIL.
LA
CE l and CE R ~ \lH
f = f MAX (4)
COM'L.
ISB2
Standby Current
(One Port-TIL
Level Inputs)
SA
CEl or CE R ~ V1H MIL.
LA
Active Port Outputs
Open, f = f MAX (4)
COM'L.
ISB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CE land
CE R~ Vee -0.2V
\IN ~ Vee -0.2V or
\IN $. 0.2V, f = 0(5)
Icc
ISB1
ISB4
COM'L.
E:
E:
MIL.
COM'L.
7132 x
7142 x
MAX.
-
TYP.
-
-
250
180
75
5
IJ.A
5
IJ.A
0.4
V
-
0.5
V
2.4
-
V
5.0V ±10%)
30(2)
30(2)
MAX.
-
7132 x 35(2)
7142 x 35(2)
TYP.
-
MAX.
-
7132 x 45
7142 x 45
TYP.
MAX.
230
185
190
145
65
55
65
45
135
110
120
85
30
10
-
75
75
195
155
-
-
::m:::::::::::::';:::: 65
25
25
65
45
,}:\:;,
-
-
-
-
155
110
40
40
130
95
-
-
-
75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2
1.2
0.4
15
5
1.0
0.2
15
4
1.0
0.2
15
4
~fe;,!j
--
-
-
--
40
35
125
95
150
115
45
42
137
105
40
35
115
90
40
35
105
80
-
75
75
-
--
25
25
65
45
-
-
-
:'.
'::;:;::..
-
:'-
45
1\\
50
50
SA
LA
-
A~}
E:
1.2
0.4
.:(: : ·:. ':1':·:':t'
- ;: ; j~ t;:;: >':"::::;:;:;::-:.,
,:;:::~gi,;;"::::;;;;(
(}:,
'::::::;:;:;:'240.:·'
~~'
E:
E:
UNIT
-
-
170·": I::;\:~
120,,:::::
One Port CE l or
SA
MiL.
CE R ~ Vee-0.2V
LA
Full Standby Current
\IN ~ Vee -0.2V or
(One Port-All
CMOS Level Inputs, \IN ~ 0.2V
1 = 0(5»)
Active Port Outputs COM'L.
Open, f = fMAX (4)
IDT7132LA
IDT7142LA
MIN.
MAX.
UNIT
mA
mA
mA
mA
mA
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. At f = fMAX' address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of 1/tRe, and using "AC TEST
CONDITIONS" 01 input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
S5-22
1DT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1) (Continued) (Vcc
SYMBOL
7132 x 55
7142 x 55
TEST CONDITION
VERSION
Dynamic Operating
Current (80th Ports
Active)
CE =VIL
Outputs Open
f = f MAX (4)
MIL.
Standby Current
(80th Ports- TIL
Level Inputs)
CE L and CE R ~ \.'IH
f = f MAX (4)
IS92
Standby Current
(One Port-TIL
Level Inputs)
SA
CE L or CE R ~ VIH MIL.
LA
Active Port Outputs
Open, f = f MAX (4)
COM'L.
IS93
SA
80th Ports CE Land MIL.
LA
Full Standby Current
CE R~ Vee -0.2V
(80th Ports-All
CMOS Level Inputs) \.'IN ~ Vec -0.2V or
\.'IN ~ 0.2V, f = 0(5) COM'L.
PARAMETER
Icc
IS91
IS94
COM'L.
rt
MIL.
SA
LA
COM'L.
rt
rt
rt
One Port CE L or
SA
MIL.
LA
CE R ~ Vee- 0 .2V
Full Standby Current
VIN ~ Vee -0.2V or
(One Port-All
CMOS Level Inputs, \.'IN So 0.2V
f = 0(5)
Active Port Outputs COM'L.
Open, f = fMAX (4)
rt
= 5.0V ±10%)
7132 x 90
7142 x 90
7132 x 100
7142 x 100
7132 X 120(3)
7142 x.120(3) UNIT
MAX.
TYP.
MAX.
TYP.
MAX.
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
230
185
180
140
65
55
65
45
135
110
115
85
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
225
180
180
135
65
55
60
40
135
110
110
85
30
10
65
65
65
65
25
25
25
25
10
40
40
40
1.0
0.2
200
160
180
130
65
45
55
35
125
100
110
75
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
190
155
180
130
65
45
55
35
125
100
110
75
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
190
155
180
130
65
45
55
35
125
100
110
75
30
10
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
40
35
120
90
40
35
115
85
40
35
110
80
40
35
110
80
40
35
110
80
40
35
100
75
40
35
100
75
40
35
95
70
40
35
95
70
40
35
95
70
TYP.
SA
LA
7132 x 70
7142 x 70
MAX. TYP.
MAX. TYP.
mA
mA
mA
mA
mA
NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. At f = fMAX' address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of l/tRc and using "AC TEST
CONDITIONS" of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
DATA RETENTION CHARACTERISTICS
SYMBOL
VDR
leeDR
(LA Version Only)
PARAMETER
TEST CONDITIONS
Vee for Data Retention
Data Retention Current
2.0
Vee = 2.0V, CE
\.'IN
t CDR (3)
1DT7132LA/IDT7142LA
Typ.(l)
MIN.
MAX.
~Vec -0.2V
~Vee -0.2Vor\.'lNSo
0.2V
I MIL. I COM'L. -
Chip Deselect to Data Retention Time
0
t
t (3)
Operation Recovery Time
R
NOTES:
1. Vec = 2V, TA = +25°C
2. t Re = Read Cycle Time
3. This parameter is guaranteed but not tested.
S5-23
Re
(2)
UNIT
-
-
V
100
4000
J.lA
100
1500
J.lA
-
-
ns
-
ns
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VOR
Vee
~
2V
4.5V
AC TEST CONDITIONS
~----------------~--------------------.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to3.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3
5V
DATA OUT
~
7750
5V
125ro
DATA OUT
100pF*
30pF for 25ns, 30ns,
~
'775n
~5ns and 45ns versions)
Figure 1. Output Load
125ro
5pF*
Figure 2. Output Load
(for t HZ ' t LZ • twz. and tow)
* Including scope and jig.
5V
~ 270il
BUSY
----j
l'OOP"
Figure 3. BUSY Output Load
(IOT7132 only)
Figure 4. BUSY
Output Load (for 25ns and
30ns versions)
* Including scope and jig.
S5-24
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(S)
PARAMETER
SYMBOL
7132 x 25 (2)
7142 x 25 (2)
MIN.
MAX.
7132
7142
MIN.
X
X
7132 x 35(2)
7142 X 35(2)
MIN.
MAX.
30(2)
30(2)
MAX.
7132 x 45
7142 x 45
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
25
-
30
tAA
t AcE
Address Access Time
25
-
t AOE
Output Enable Access Time
-
tOH
Output Hold From Address Change
0
-
tLZ
Output Low Z Time (1,
0
tHZ
Output High Z Time (1, 4)
tpu
Chip Enable to Power Up Time (4)
tpD
Chip Disable to Power Down Time (4)
Chip Enable Access Time
4)
25
35
-
45
-
-
35
-
45
ns
45
ns
30
ns
-
0
0
5
-
ns
5
-
-
12
-
15
-
20
ns
0
-
0
-
0
-
ns
-
50
-
50
-
50
ns
.::-:-{:
..:::..
(:::?@.9:::::"
\/\::::.::::: 30
"1,"~:::t:::{t::··::·
'.'
12
.:(:
15
:\:?W?::··
.::. :1::::::' :::::.:::: 0
. ·:::::::::::'\:)0':'
.Q::::)::L(h::,:"::::::" i1::('"
50
-
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(S)
SYMBOL
PARAMETER
7132 x 55
7142 x 55
MIN.
MAX.
7132 x 70
7142 x 70
MIN.
MAX.
35
25
ns
ns
(Continued)
7132 x 90
7142 x 90
MIN. MAX.
7132 x 100
7142 x 100
MIN.
MAX.
7132 x 120(3)
7142 x 120(3)
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
55
-
70
-
90
-
100
-
120
-
ns
tAA
t ACE
Address Access Time
-
55
70
-
90
-
120
ns
55
70
-
90
100
ns
Output Enable Access Time
35
-
40
-
40
-
120
t AoE
-
-
100
Chip Enable Access Time
-
60
ns
tOH
Output Hold From Address Change
0
-
0
-
10
-
10
10
Output Low Z Time (1, 4)
5
-
5
-
5
-
5
5
-
ns
tLZ
-
tHZ
Output High Z Time (1, 4)
-
30
-
35
-
40
-
40
-
40
ns
tpu
Chip Enable to Power Up Time (4)
0
-
0
-
0
-
0
-
0
-
ns
tpD
Chip Disable to Power Down Time (4)
-
50
-
50
-
50
-
50
-
50
ns
\
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4, This parameter guaranteed but not tested.
5. ·x" in part numbers indicates power rating (S or L).
TIMING WAVEFORM OF READ CYCLE
NO.~,
EITHER SIDE
S5-25
(1,2,4)
40
ns
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
•
~
(1,3)
•
tACE
j'l
~
,
~tHZ-
- tAOE -
I- .
'\
tHZ ....
. - tLZ --DATA OUT
CURRENT
..
~c
I
I
\
\
..,
.-tpu~
~
VALlOOATA
-
•
tLZ
_ t po -
1
_ _ _ _ _ _ _ _ _ _ _"' 50%
Iss
NOTES:
1. RNi is high for Read Cycles.
2. Device is continuously enabled, CE = V1L •
3. Addresses valid prior to or coincident with CE transition low.
4. OE = \IL
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (7)
SYMBOL
PARAMETER
7132 x 25(2)
7142 x 25(2)
MIN.
MAX.
7132 x 30(2)
7142 x 30(2)
MIN.
MAX.
7132 x 35(2)
7142 x 35(2)
MIN.
MAX.
7132 x 45
7142 x 45
MIN.
MAX.
UNIT
WRITE CYCLE
-
-
45
30
-
35
30
-
35
-
0
0
-
30
-
35
0
-
0
20
-
20
-
-
12
-
15
-
20
ns
0
-
0
-
0
-
ns
10
-
12
-
15
-
20
ns
-
0
-
0
-
0
-
ns
Write Cycle Time(5)
25
tEW
Chip Enable to End of Write
20
tAw
Address Valid to End of Write
20
tAS
Address Set-up Time
0
twp
Write Pulse Width (6)
20
tWR
Write Recovery Time
0
tow
Data Valid to End of Write
12
tHZ
Output High Z Time(l. 4)
-
tDH
Data Hold Tme
O.:.:::;:,:,::::;:\:t::,},;:;·-
twz
Write Enabled to Output in High Z(l. 4)
tow
Output Active From End of Write (1. 4)
'0:::.
30
25
25
0
.::::::::\::::::.:::;:::.
.?5\}:i?:::::··::::
l)~\. ·O'):···:::·
·:tt::::::: [t::\5
. :""t:::,:::J(f';
.:::/'3:/"\:(:::::::'
.::{{\
(:?::::\::; '.: :.:.
35
twc
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, t wc = tSM + twp.
6. Specified for DE: at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. ·x" in part numbers indicates power rating (S or L).
S5-26
-
ns
ns
ns
ns
ns
ns
ns
IDT7132SA/LA AND 1DT7142SA/LA
CMOS DUAL·PORT RAM 16K (2K x a·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (7)
7132 X 55
7142 X 55
MIN.
MAX.
PARAMETER
SYMBOL
7132 X 70
7142x 70
MIN.
MAX.
7132 X 90
7142 X 90
MIN. MAX.
7132 X 100
7142 X 100
MIN.
MAX.
7132 X 120(3)
7142 X 120(3)
MIN.
MAX.
UNIT
WRITE CYCLE
90
0
-
50
-
55
-
0
-
30
-
30
-
35
twc
Write Cycle Time(S)
55
-
70
tEW
Chip Enable to End of Write
40
-
50
tAW
Address Valid to End of Write
40
Address Set-up Time
0
-
50
t AS
twp
Write Pulse Width
40
-
tWR
Write Recovery Time
0
tDW
Data Valid to End of Write
20
tHZ
Output High Z Time(l. 4)
-
100
0
-
40
-
40
-
-
40
-
40
85
85
0
90
90
0
55
0
120
-
ns
100
ns
40
-
-
40
ns
ns
100
0
65
0
ns
ns
ns
ns
ns
tDH
Data Hold Tme
0
-
0
-
0
-
0
-
0
-
twz
Write Enabled to Output in High Z(l. 4)
-
30
-
35
-
40
-
40
-
50
ns
tow
Output Active From End of Write(l. 4)
0
-
0
-
0
-
0
-
0
-
ns
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, t wc = tSM + tWf>
6. Specified for OE at high (Refer to "Timing Waveform of Write Cycle", Note 7)
7. "x" in part numbers indicates power rating (S or L).
CAPACITANCE
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS
MAX.
UNIT
. VIN = OV
11
pF
VOUT= OV
11
pF
NOTE:
1. This parameter is sampled and not 100% tested.
S5-27
IDT7132SA/LA AND JDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)
(1,2,3,7)
twc
ADDRESS
~
---./
)K
K
•
t
(6)HZ
/V
~,
•
tAW
•
_ t AS
RNi
t
(7)
tWR
Wp
/~
',,-
¥
-
t HZ.
-
+-twt)-
•
DATA OUT
tow
"'·(4)./~ "-
(4)
_tow
t OH
-
"
./
./
'"
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)
(1,2,3,5)
~----------------------twc----------------------~
ADDRESS
~--------------------tAW ------------------~
,---+----------------
--~~.-------------tEW------------~1
NOTES:
1.
2.
3.
4.
5.
6.
7.
RNi must be high during all address transitions.
A write occurs during the overlap (tEW or twp ) of a low CE' and a low RIW.
tWR is measured from the earlier of cr or R/W going high to the end of the write cycle.
During this period, the I/O pins are in the output state and input signals must not be applied.
If the CE low transition occurs Simultaneously with or after the RiW,Iow transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
If OE is low during a RNi controlled write cycle, the write pulse width must be the larger of twp or (twz+ tow) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tow. If DE is high during an RNi controlled write cycle, this requirement does not apply and the write
pulse can be as short as the specified t wp .
S5-28
-------------------_
.... -
.•...
_--
IOT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(S)
SYMBOL
PARAMETER
7132 X 35(1)
7142 x 35(1)
MIN.
MAX.
1132 x 30(1)
7142 x 30(1)
MIN.
MAX.
7132 X 25(1)
7142 x 25(1)
MIN.
MAX.
7132 x 45
7142 x 45
MIN.
MAX.
UNIT
BUSY TIMING (FOR MASTER IOT7132 ONLy)
tSM
"!3U"SY Access Time to Address
-
25
tSDA
t SAC
tillS? Disable Time to Address
20
tDDD
Write Data Valid to Read Data Delay(3)
-
tAPS
Arbitration Priority Set-up Time (4)
5
tBDD
tillS? Disable to Valid Data(S)
-
t BDC
"!3U"SY Access Time to Chip Enable
tffiS'7 Disable Time to Chip Enable
tWDD
Write Pulse to Data Delay (3)
-
~Q
./:,:,::::'25.\.
-
20
'::<:"/:":"25
"'iiii:::}il::'" 25
.:t=::::::'i}:::::::{
50
55
::::ib2i:::,'
30
30
~':::".::; litt:,6'=;::"
20
~~~::~.
BUSY INPUT TIMING (FOR SLAVE IOT7142 ONLy)
·:tt::;:;:
tWB
Write to "!3U"SY Input(6)
0
tWH
Write Hold After 'EITJS? (3)
15.iitt:::.,.·+:/:"
tWDD
Write Pulse to Data Delay (9)
tDDD
Write Data Valid to Read Data Delay(9)
[,:,,::,
-
.
Note 5
-
35
-
30
-
5
35
ns
35
ns
30
-
30
ns
25
-
25
ns
60
70
ns
35
-
45
ns
-
5
-
ns
-
Note 5
-
Note 5
ns
-
0
-
ns
20
-
ns
60
-
70
ns
35
-
45
ns
.':::;\:.
(}t:_
0
-
0
-
20
-
20
50
-
55
30
-
30
-
.:"t'jif<}'
"\~(
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(S)
SYMBOL
PARAMETER
7132 x 55
7142 x 55
MIN.
MAX.
7132 x 70
7142 x 70
MIN.
MAX.
7132 x 90
7142 x 90
MIN.
MAX.
7132 x 100
7142 x 100
MIN.
MAX.
7132 x 120(2)
7142 x 120(2)
MIN.
MAX.
UNIT
BUSY TIMING (FOR MASTERIDT7132 ONLY)'
tSDC
BUSY Access Time to Address
'EiUS'? Disable Time to Address
'EITJS? Access Time to Chip Enable
'EITJS? Disable Time to Chip Enable
tWDD
Write Pulse to Data Delay(3)
-
tDDD
Write Data Valid to Read Data Delay(3)
-
55
-
tAPS
Arbitration Priority Set-up Time (4)
5
-
5
-
5
-
5
-
5
-
ns
tSDD
'l3DSY Disable to Valid Data(5)
-
Note 5
-
Note 5
...;
Note 5
-
Note 5
-
Note 5
ns
-
0
-
0
20
-
0
20
-
0
20
20
-
ns
-
90
-
100
140
ns
70
-
90
120
ns
tBM
tBDA
t BAC
90
-
45
-:-
45
-
45
40
40
-
45
45
90.
-
100
70
-
35
30
80
35
30
45
100
-
120
ns
50
50
50
50
120
60
ns
60
ns
60
ns
60
ns
140
ns
BUSY INPUT TIMING (FOR SLAVE 1OT7142 ONLy)
tWB
Write to tffiS'7 Input(6)
0
tWH
Write Hold After ~(7)
20
tWDD
Write Pulse to Data Delay (9)
tDDD
Write Data Valid to Read Data Delay (9)
-
80
55
-
120
100
-
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With 'I3OS'Y (For Master IDT7132 only)".
4. To ensure that the earlier of the two ports wins.
5. t BDO is a calculated parameter and is the greater of 0, t WDo- twp (actual or tDDD - twp (actual)
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
8. ·x· in part numbers indicates power rating (S or L).
9. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With Port-to-Port Delay (For Slave IDT7142
Only)".
S5-29
.. _ - - - - ...
_----
- - - - - - ...._.-........-
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (1,2,3~FOR MASTER IDT7132 ONLy)
ADDRR
'I
,
MATCH
.~
..
\
twp
~
'I
~
~
,
DATAINR
W
VALID
j~
JI\
tAPS(1) J
X,
ADDRL
MATCH
)
t=.
t SDA ---
'-K
BTISYL
t sDD---
f
-
tWDD
DATAoUTL
-:{ VALID
J_
t DD '(4)
NOTES:
1. To ensure that the earlier of the two ports wins.
2. Write Cycle parameters should be adhered to, to ensure proper writing.
3. Device is continously enabled for both ports.
4. ~ at LO for the reading port.
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY (1, 2, 3)(FOR SLAVE IDT7142 ONLy)
•
twc
ADDRR
'If
'If
MATCH
J\
J\
• 'I
twp
-'
J
\
·~tDwDATAINR
~~
J'/\
~
X
VALID
I
MATCH
tWDD
DATAoUTL
t DDu
NOTES:
1. Assume 80S? input at HI for the writing port, and DE at LO for the reading port.
2.
3.
Write Cycle parameters should be adhered to, to ensure proper writing.
Device is continously enabled for both ports.
S5-30
-p
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION.
CE L VALID FIRST:
ADDR
LAND R
=:x
>C
ADDRESSES MATCH
~.~-* (.'00-*_
CER VALID FIRST:
ADDR
LAND R
=:x
>C
ADDRESSES MATCH
~.~-{ (.=-*TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION
LEFT ADDRESS VALID FIRST:
1 . . - - - - t RC OR twc
------;~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
RIGHT ADDRESS VALID FIRST:
1 . . - - - - t RC OR twc ------;~
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
NOTE:
S5-31
(1)
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
RIGHT
LEFT
~
RNi
RNi
IDT7132
MASTER
.~+5V
,.
-
BUSY
BUSY
RNi
+5V -.,/\/\/"
IDT7142
SLAVE (1)
~ BUSY
RNi
BUSY
-~
NOTE:
1. No arbitration in IDT7142 (SLAVE). BUSY-IN inhibits write in IDT7142 (SLAVE).
FUNCTIONAL DESCRIPTION:
The IDT7132/42 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. These devices have an automatic
power-down feature controlled by CEo The CE controls on-chip
power-down circuitry that permits the respective port to go into a
standby mode when not selected (CE' high). When a port is enabled, access to the entire memory array is permitted. Each port
has its own Output Enable control (DE). In the read mode, the port's
turns on the output drivers when set LOW. Non-contention
READ/WRITE conditions are illustrated in Table I.
m:
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to Sns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between ~and CE A for access; or (2)
55-32
if the CEs are low before an address match, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table II). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip Includes a hardware arbitrator, and the addresses for each Chip arrive at the same time, it is possible that one
will activate its BUSYL while another activates its BUSYA Signal.
Both sides are now busy and the CPUs wi II wait indefinitely for their
port to become free.
To avoid this "Busy Lock-Out" problem, IDT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has i30SV inputs which allow an
Interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed, until after the tillS? input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past 'SUS? to ensure that a write cycle takes place after
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to 80S? from the
MASTER.
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE 1- NON-CONTENTION
READ/WRITE CONTROL
LEFT OR RIGHT PORT (1)
R/W
CE
OE
FUNCTION
DO-7
X
H
X
Z
Port Disabled and in Power Down
Mode, ISB2 or ISB4
X
H
X
Z
CE R = CE l = H, Power Down
Mode,lsB1 or ISB3
L
L
X
DATA IN
Data on Port Written Into Memory(2)
H
L
L
DATA OUT
Data in Memory Output on Port (3)
H
L
H
High Impedance Outputs
Z
NOTES:
1. AOl-A1Dl*AoR-A1DR
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tBDD timing.
H = HIGH, L= LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
TABLE II-ARBITRATION (2)
FLAGS (1)
RIGHT PORT
LEFT PORT
FUNCTION
CE l
AOL - A 10L
CE R
H
X
H
X
H
H
No Contention
L
Any
H
H
H
No Contention
H
X
L
X
Any
H
H
No Contention
H
H
No Contention
L-PortWins
A OR - A 10R
L
'" AOR-A10R
'" AOl -A1DL
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
BUSYL
BUSYR
L
LV5R
L
LV5R
H
L
L
RV5L
L
RV5L
L
H
R-PortWins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R
= A OR-AlOR
LL5R
= AOL -A1DL
H
L
L-PortWins
RL5L
= AOR- A10R
RL5L
= AOl -A10L
L
H
R-PortWins
LW5R
= AOR-A1DR
LW5R
= AOl -A1DL
H
L
Arbitration Resolved
LW5R
= AOR-A1DR
LW5R
= AOL -A1Dl
L
H
Arbitration Resolved
NOTES:
1. X = DON'T CARE, L = LOW, H = HIGH
2. LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW ~ 5ns before Right CEo
RL5L = Right CE = LOW ~ 5ns before Left CEo
LW5R = Left and Right CE = LOW within 5ns of each other.
S5-33
- - - - - - - - - - - - - - .-.._---
IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
De~ype
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
y:rank
P
L -______________
~
C
JL
F
L -______________________
~
25
35
45
55
Commercial (OOC to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP (600 mil)
Plastic Leaded Chip Carrier
Leadless Chip Carrier-indicate 48- or 52-pin
Flatpack
Commercial Only
1
Speed in Nanoseconds
70
90
100
120
L -____________________________
SA
ILA
~I
L -______________________________________
~
7132
7142
S5-34
Military Only
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
- - - - - _.. _ - - - - - _ . - . _ - - - . _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
t;)
CMOSDUA~PORTRAMS
lOT 71321 SA/LA
lOT 71421 SA/LA
16K (2K x 8-BIT)
WITH INTERRUPTS
Integrated Device'Jechnology.lnc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 25/30/35/45/55ns (max.)
• Low-power operation
- I0T71321/421SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- I0T71321/421 LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
The I0T71321/I0T71421 are high-speed 2K x 8 dual-port static
RAMs with internal interrupt logic for interprocessor communications. The I0T71321 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM, together with the
I0T71421 "SLAVE" dual-port, in 16-bit-or-more 'word width systems. Using the lOT MASTER/SLAVE dual-port RAM approach in
16-or-more-bit memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology, these devices typically operate on only 325mW of power at
maximum access times as fast as 25ns. Low-power (LA) versions
offer battery backup data retention capability with each port typically consuming 200jJ.W from a 2V battery.
The I0T71321/71421 devices are packaged in 52-pin LCCs and
PLCCs. Military grade product is manufactured in compliance with
the latest revision of MIL-STO-883, Class B.
• Two INT flags for port-to-port communications
• MASTER I0T71321 easily expands data bus width to
16-or-more-bits using SLAVE I0T71421
• On-chip port arbitration logic (I0T71321 only)
•
•
•
•
•
•
BUSY output flag on I0T71321; BUSY input on I0T71421
Fully asynchronous operation from either port
Battery backup operation-2V data retention
TTL-compatible, single 5V ±10% power supply
Available in popular hermetic and plastic packages
Military product compliant to MIL-STO-883, Class B
FUNCTIONAL BLOCK DIAGRAM
RlWL
L
cr
'CE R
OE L
OE R
A10L
A7L
RlWR
•
A10R
A7R
•
I/OOL
I/OoR
I/07L
I/07R
NJS'iL(l)
NJS'iR(l)
A6L
A6R
MEMORY
ARRAY
ROW
SELECT
ROW
SELECT
AOL
AOR
A10L
AlaR
AOL
Ci: L
RIWL
------I~I
..
ARBITRATION
AND INTERRUPT
LOGIC
AOR
1+------ crR
RlWR
INT L(2)
INT (2)
R
NOTES:
1. IDT71321 (MASTER): BOSl is open drain output and requires pullup resistor. IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pull up resistor.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-l031/1
1989 Integrated Device Technology. Inc.
S5-35
IiII
IDT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN. CONFIGURATIONS
.J.J.J
~
.J.J
8:.J
a:~a:
a:B:
a: a:
j~~~ ii:~J3~ii: ~1
LJ
7
J52-1
&
L52-1
40C
39 C
3SC
37C
36C
3se
Jro
MC
~; ~~ ~~ ~~ ~~ ~~ ~; ~~ ~~ ~~ ;; ;~ ;~
LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +150
°C
lOUT
DC Output Current
50
50
rnA
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input Low Voltage
Input High Voltage
2.2
-0.5(1)
-
6.0
V
-
0.8
V
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
SS-36
UNIT
IDT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
(Vee = 5.0V ±10%)
IDT71321SA
IDT71421SA
MIN.
MAX.
TEST CONDITION
10l = 4mA
-
VOL
Open Drain Output LoW
Voltage (BUSY/I NT)
10l = 16mA
-
VOH
Output High Voltage
10H= -4mA
2.4
IILlI
Input Leakage Current
Vee = 5.5V, \'IN = OV to Vee
Illol
Output Leakage Current
CE = \'IH'VOur = OV to Vce .
VOL
Output Low Voltage (1/00- 1/0 7 )
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
TEST CONDITIONS
VERSION
CE =\'Il
Outputs Open
f = fMAX (4)
MIL.
lee
Dynamie Operating
Current (Both Ports
Aetive
IS91
Standby CUrrent
(Both Ports-TIL
Level Inputs)
CE land CE R ::? \'IH
f = fMAX (4)
IS92
Standby Current
(One Port-TIL
Level Inputs)
CEl or CE R ::? V1H
Active Port Outputs
Open, f = fMAX (4)
IS93
SA
Both Ports CE Rand MIL.
LA
Full Standby Current
CEl::' V -0.2V
(Both Ports-CMOS
\'IN ::? Vee -0.2V or
Level Inputs)
\'IN s: 0.2V, f = 0(5) COM'L. ~
IS94
PARAMETER
MIL.
One Port CEl or
CE R ::? Vee-O.2V
Full Standby Current
\'IN ::? Vce -0.2V or
(One Port-CMOS
\'IN ~ 0.2V
Level Inputs
f = 0(5~
Active Port Outputs
Open, f = fMAX (4)
MIL.
MIL.
5
J.lA
-
5
J.lA
0.4
0.4
V
0.5
-
0.5
V
-
2.4
-;-
V
TYP.
TYP. MAX. TYP.MAX TYP. MAX. TYP. MAX.
MAX.
75170 .::250/240
75170 ;}fSO/iro
75
75
195
155
LA
25/25"
:::;:;;:6~/65
25/25, :.:.:...45/45
25
25
65
45
SA
LA
50/4i:f ;;;:170/155
50/46 :.....120/110
40
40
130
95
..
:::;::;:;::;:::;:;:::::....
~::::::::::::::.:::::::
1.zhi2{ ;;;,15/15
0.1(.0.4 ;::::: 5/5
15
4.0
LA
:~:~6i45;;;
{4o/42
75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2
230
185
190
145
65
55
65
45
135
110
120
85
30
10
65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2
230
185
180
140
65
55
65
45
135
110
115
85
30
10
1.0
0.2
15
4.0
1.0
0.2
15
4.0
40
35
125
95
40
35
120
90
40
35
115
80
40
35
100
75
65
65
225
180
25
25
65
55
40
40
135
110
1.0
0.2
30
10
40
35
mA
mA
mA
110
80
mA
150/137
115/105
40
35
115
90
NOTES:
1. ·x· in part numbers indicates power rating (SA or LA).
2. O°C to + 7.o°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. At f = fMAX' address and data inputs (except Output Enable) are eycling at the maximum frequency of read cycle of 1/tRO and using
"AC Test Conditions· of input levels of GND to 3'./.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
S5-37
UNIT
mA
1.0
0.2
SA
COM'L.~
-
10
71321x3S(2) 71321x45 71321x55 71321x70(3)
71421x35(2) 71421x45 71421x55 71421x70(3)
SA
COM'L.~
10
(1) (Vee = 5.0V ±10%)
LA
COM'L.~
UNIT
71321x25/30
71421x25/30
SA
COM'L.~
IDT71321LA
IDT71421LA
MIN.
MAX.
HI
IDT71321 SA/LA AND IDT71421 SA/LA
. CMOS DUAL-PORT RAMS 16~(2Kx8-BIT) WITH INTERRUPTS
DATA RETENTION CHARACTERISTICS
SYMBOL
VOR
ICCOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(L Version Only)
PARAMETER
IDT71321LA!IDT71421LA
TYP.(I)
MIN.
MAX.
TEST CONDITION
Vcc for Data Retention
Vcc = 2.0V, CE <:= Vee -0.2V
Data Retention Current
t COR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
\-IN
<:= Vcc -0.2V or
\-IN
I MIL.
I COM'L.
~ 0.2V
2.0
-
-
V
-
100
4000
J..lA
100
1500
J..lA
0
-
-
ns
-
t RC (2)
NOTES:
1. Vcc = 2V, TA = +25°C
2. t Rc = Read Cycle Time
3. This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.SV
1.5V
See Figures 1, 2 & 3
5V
DATAoUT
~
n50
.
5V
125ro
DATA OUT
100pF*
~
n50
.
30J)F
&;,
30,for
35, & 45 ns
versions)
Figure 1. Output Load
qpF*
S\}
~ 2700
__
BUSYOrINT~
l'OOPF
125ro
Figure 2. Output Load
(for tHZ.tLZ.tWZ ' and tow)
5V
_
~ 2700
Preliminary
BUSYOrINT~
130P'"
O
Figure 3. BUSY and INT
Output Load
Figure 4. BUSY and INT
Output Load (for 25n5 and
30ns versions)
* Including scope and jig.
S5-38
UNIT
ns
1DT71321 SA/LA AND 1DT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2KxS-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
71321x25/30 (2)
71421x25/30 (2)
MIN.
MAX.
71321x35(2)
71421x35(2)
MAX.
MIN.'
71321x45
71421x45
MAX.
MIN.
71321x70(3)
71321x55
71421x70(3)
71421x55
MAX. MIN.
MAX. MIN.
UNIT
READ CYCLE
35
-
45
-
55
-
70
-
-
35
-
45
55
-
70
ns
35
-
45
55
ns
-
30
35
-
70
25
-
40
ns
:::::::}?\::::. :' -
0
-
0
0
-
0
5
-
5
5
-
5
-
ns
0/0:::::::::::::;::::::::0' -
-
-
15
-
20
-
30
-
35
ns
t RC
Read Cycle Time
tAA
t ACE
Address Access Time
Chip Enable Access Time
t AoE
Output Enable Access Time
tOH
Output Hold From Address Change
0/0
tLZ
Output Low Z Time(l, 4)
tHZ
Output High Z Time(1, 4)
tpu
Chip Enable to Power Up Time(4)
q)Q+::::::i
tpD
Chip Disable to Power Down Time(4)
::2:;:;,::::::.:
25/30
:i:::::"':F.:.
{<~9.1:30
-
,.~::::::::~/30
:::::::,:,:':W2/15
-;i\:::;::/,::::::';: 10/12
-
0
-
0
-
0
-
0
-
ns
-
50
-
50
-
50
-
50
ns
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
DATA OUT
(1,2,4)
tz,0A:;uq
~ ;__
E. t~~
'REV""
ns
50/50
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. "x' in part numbers indicates power rating (S or L).
ADDRESS
ns
g g ~_______
DA_T_A_VA_L_ID_ _ _ _ _
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
r-------
~
(1,3)
tAcE-----.I
DATA OUT
r - - - - - tLZ ---i~
~
tpU3
tpD
Icc _ _ _ _ _ _ _ _ _ _ _~__- - - - - - - - - - - - - - - - CURRENT
_ _ _ _ _ _ _ _ _ _...,j 50%
50%
Iss
NOTES:
1. RiW is high for Read Cycles.
2. Device is continuously enabled, CE = \IL'
3. Addresses valid prior to, or coincident with, CE transition low.
4. OE = V1L
S5-39
IDT71321 SA/LA AND IDT71421 SA/LA
. CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
PARAMETER
SYMBOL
71321x 25/30(2)
71421x 25/30(2)
MAX.
MIN.
71321x 35(2)
71421x 35(2)
MIN;
MAX.
71321x 45
71421x 45
MIN.
MAX.
71321x 55
71321x 7()(3)
71421x 55
71421x 7013)
MIN.
MAX. MIN.
MAX.
UNIT
WRITE CYCLE
two
t '
Write Cycle Time(S)
tAW
t AS
Address Valid to End of Write
EW
·twp
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
25/30
35
45
55
70
ns
20/25 :rt::::~::::. .~.::::~:·
....:.;:::::.:.....
. 20/25 ;:::::::.:.;...... """"1-:::
30
35
40
50
ns
30
35
40
50
ns
0/0 ;:::::::::::::;::::::::::;;.
0
0
0
0
ns
20/25:,;;;;::::::}<::::;:;
30
35
40
50
ns
0/0 ;:"{,:,:,,:::;::;:;::::::=::'
0
0
0
0
ns
12115:::,'t::=:::::::;::::=::-.
20
20
20
30
.:::::::::):::::
tWR
Write Recovery Time
tow
Data Valid to End of Write
tHZ
Output High Z Time(1.4)
tOH
Data Hold Time
oICK,),:,,::.'·:;;::::'·
twz
Write Enabled to Output in
High Z(1.4)
};::::,:~::g\:t;::;;:::'
tow
Output Active From End of Write(1.4
--<:::;:::::::.:::·:'·:::::::::to/12
0/0
::::.:.
-
20
15
0
0
20
15
10/12
0
0
NOTES:
1. Transition is measured ±500mV from low or high voltage with load (Figures 1, 2 and 3).
2. OOC to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, twc = tBAA + t wp .
6. ·x· in part numbers indicates power rating (Sor L).
S5-40
0
0
0
ns
ns
35
30
0
ns
35
30
ns
ns
IDT71321SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
,
two
ADDRESS
~
~
)K
K
tAw
~ r\.
~
I+-- t AS
"",
t
(7)
tWR
WP
/'1'
i
-
tHZ(6)~
'1"
'
,
_tWi6)~
, tow
~
(4)
DATA OUT
f 4 - t ow
-
t OH -
/'
DATA IN
(4):~
......
",
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING (1,2,3,5)
~------------------------------~-------------------twc-----------------------------------------------~~
ADDRESS
--~~-------------------------------tEW---------------------------~
Rm
DATA IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
WE must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low RiW.
tWR is measured from the earlier of
or RiW going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RiW controlled write cycle, the write pulse must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off data to
be placed on the bus for the required tow. If O"E is high during an RlW controlled write oycle, this requirement does not apply and the write pulse
can be as short as the specified twp .
cr
S5-41
--------._-,-----",-,- , ' - - ' " " ' ' ' - - ' ' - - - - - - - - - - , - _ . , , - - - - ' - - - - - -
IDT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
71321x25/30(1)
71421x25/30(1)
MAX.
MIN.
71321x35(1)
71421x35(1)
MIN.
MAX.
71321x45
71421x45
MIN.
MAX.
71321x70(2)
71321x55
71421x70(2)
71421x55
MAX. MIN.
MIN.
MAX.
UNIT
BUSY TIMING (For Master IDT71321 only)
":~§!9.9.
::;:;;?,9.{?~
35
35
45
45
ns
30
35
40
40
ns
BUSY Access Time to Chip Enable
""'20/25
30
30
35
35
ns
BUSY Disable Time to Chip Enable
:'i(@p125
25
25
30
30
ns
Write Pulse to Data Delay (3)
::::::'::,:,:)~();55
60
70
80
90
ns
Write Data Valid to
Read Data Delay (3)
..':':::":::::':'Jb/30
35
45
55
70
taAA
BUSY Access Time to Address
tSDA
BUSY Disable Time to Address.
t SAC
t SDC
tWDD
tDDD
tAPS
t SqD
Arbitration Priority Set-up Time (4)
::::::::::::;::::.:.;.'
5/5:':'::
BUSY Disable to Valid Data(S)
tws
tWH
Write Hold After BUSY (7)
tWDD
Write Pulse to Data Delay (9)
tDDD
Write Data Valid to Read
Data Delay(9)
:.:.::::::.....
:':':'.
5
5
:':Note 5
NoteS
5
NoteS
5
NoteS
ns
NoteS
ns
:.:.:.;:;:;:::
BUSY TIMING (For Slave IDT71421 only)
Write to BUSY input (6)
::;::::;::::::::.,
.::;::::~:::::
?!r:::::::::'::,:·
1~'
~O,,({
/:,~ [[[::'::::::::
li::;:::,t\::,;'
0
0
0
0
ns
20 .
20
20
20
ns
50/55
60
70
80
30/30
35
45
55
90
ns
70
ns
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
.
' .
3. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read with BUSY (For Master IDT71321 only)"
4. To ensure that the earlier of the two ports wins.
5. taDD is 8 calculated parameter and is the greater of 0, tWDD - twp (actual) or tDDD - tDW (actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
8. "x· in part numbers indicates power rating (S or L).
9. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveforms of Read with Port-to-port delay
(For Slave IDT71421 only)" .
.
55-42
IDT71321 SAl LA AND IDT71421 SAl LA
CMOS DUAL-PORT RAMS 16K{2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSY (1,2,3)(FOR MASTER IDT71321)
twc
''I
''I
MATCH
J~
J~
twp
J[""
\
'I
J
~tDW
~I
DATAIN R
J~
f4-
tDH
'I
VALID
J\
t APS -
'\\
i!X
MATCH
/
I'--
t SDA -
t SDD -
-~
"-~
_J
~
tWDD
~"-
DATAoUT L
-.J~
VALID
tDD~1
NOTES:
1. To ensure that the earlier of the two port wins.
2. Write Cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. C
~t~q r:teOO=1_
CE R VALID FIRST:
ADDR
LAND R
BUSYL
::x
ADDRESSES MATCH
>C
~-t04C=i----lr:-t~J-.~-==
S5-44
IDT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2KxS-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION (FOR MASTER
IDT71321 ONLy) (1)
LEFT ADDRESS VALID FIRST:
~--- t Ac OR twc ----1~
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
.---tMA~~_____________tB_DA_-_-_-_-_~_;r~_____________
RIGHT ADDRESS VALID FIRST:
' - - - - - t AC OR twc ------i~
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
.---tMA~~_____________tB_DA_-_-_-_-_-_;r~______________
NOTE:
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
71321SA/LA25/30(1)
71421SA/LA25/30(1)
MAX.
MIN.
71321 SA/LA35 (1)
71421 SA/LA35 (1)
MIN
MAX.
71321SA/LA45
71421 SA/LA45
MIN.
MAX.
71321 SA/LA55 71321SA/LA70(2)
71421SA/LA55 71421SA/LA70(2)
MAX.
MIN.
MIN.
MAX.
UNIT
INTERRUPT TIMING
t AS
Address Set-up Time
0
tWA
Write Recovery Time
0
tiNS
Interrupt Set Time
.7:\::::::::::::=:-:'
tiNA
Interrupt Reset Time
0
-
0
-
0
0
-
0
-
0
25/30
-
35
-
40
25/30
-
35
-
40
-
.,,;:f<.
.:::. ::,::t::;:::>·:
·ttC~
-
0
-
ns
0
-
ns
45
-
50
ns
45
-
50
ns
NOTES:
1. 0 ° C to + 70 ° C temperature range only.
2. -55°C to + 125°C temperature range only.
S5-45
...
_-------------
IDT71321SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF INTERRUPT MODE (1,2)
LEFT SIDE SETS INT R :
twc
WRITE 7FF
ADDRl
t AS
RiW l
..
INTR
f"
NOTES:
CE l = CE R = \Il
2. INTl and INTR are reset to VOH during power up.
1.
S5-46
IDT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K(2KxS-Bln WITH INTERRUPTS
TIMING WAVEFORM OF INTERRUPT MODE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(1,2)
RIGHT SIDE SETS INTL :
two
ADDRR
-CEo
-cOO(
WRITE 7FE
~
t AS
tWR
"}'f.
-''\.
tiNS
-'
LEFT SIDE CLEARS INTL :
ADDRl
OE l
INTl
.Ji..\\~'\.:.......l'\~S\~\....Jt,.\~\~'\.JI...'\~\:.......l\~'\'\~'\~\~\~\~\:.......l\~\\~___
--J/
_
.j
_
~/''"
_________________l=-___
NOTES:
1. GEL = CE R = Vil
2. Tf\ITRand TNTl are reset (high) during power up.
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RNi
BUSY
------~~
RIGHT
RNi
IDT71321
RNi
RNi
-BU-S-Y MASTER -BU-S-Y 1 - -___-+--- BUSY
+5V
+5V-'''''''-RNi ~--+-----'
IDT71421
SLAVE (1)
BUSY
NOTE:
1. No arbitration in IDT71421 (SLAVE). BUSY-IN inhibits write in IDT71421 (SLAVE).
S5-47
---------------- ----_._-----
1DT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT71321/421 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. These devices have an automatic
power down feature controlled by CEo The CE controls on-chip
power down circuitry that permits the respective port to go into a
standby mode when not selected (CE high). When a port is enabled, access to the entire mem0!Yilrray is permitted. Each port
has its own Output Enable control (OE).ln the read mode, the port's
turns on the output, drivers when set LOW. Non-contention
READ/WRITE conditions are illustrated in Table I.
The interrupt flag (INT) permits communication between ports
or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTd is set when the right port writes to
memory location 7FE (HEX). The left port clears the interrupt by
reading address location 7FE. Likewise, the right port interrupt flag
(INTR) is set when the left port writes to memory location 7FF (HEX)
and to clear the interrupt flag (INTRl, the right port must read the
memory location 7FF. The message (8 bits) at 7FE or 7FF is userdefined. Ifthe Interrupt function is not used, address locations 7FE
and 7FF are not used as mall boxes but as part of the random access memory. Refer to Table II for the interrupt operation.
rn:
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is Important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port wi II
have access when BUSY goes inactive.
I
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CEl and CE Rfor access; or (2)
if the CEs are low before an address matCh, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table III). In either mode of arbitration, the delayed port's BUSYflag
is set and will reset when the port granted access completes its
operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width tosixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one
will activate its L 8USY while another activates its R 8USY signal.
Both sides are now busy and the CPUs wi II wait indefinitely for their
'
,
port to become free.
To avoid this "Busy Lock-Out" problem, IDT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
, the MASTER, is used. The SLAVE has BUSY" inputs which allow an
interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BUSY to ensure that a write cycle takes place after
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to"8USV from the
MASTER.
CAPACITANCE
TRUTH TABLES
SYMBOL
TABLE I-NON-CONTENTION
READ/WRITE CONTROL<4)
LEFT OR RIGHT PORT (1)
R/W
CE
OE
00-7
H
X
Z
Port Disabled and in Power Down
Mode, ISS2 or Iss4
X
H
X
Z
CE R = CEl = H, Power Down
Mode, Iss1 or ISS3
L
L
X
DATA IN
Data on Port Written Into Memory(2)
H
L
L
DATA OUT
Data in Memory Output on Port (3)
H
L
H
Z
CIN
Input CapaCitance
COUT
Output Capacitance
CONDITIONS
MAX.
UNITS
VIN = OV
11
pF
VOlll:= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not production tested.
FUNCTION
X
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
High Impedance Outputs
NOTES:
1. AOl - AWL ~ AOR - AlOR
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see twoo and tsoo timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
S5-48
IDT71321SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2KxS-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE II-INTERRUPT FLAG (l, 4)
RIGHT PORT
LEFT PORT
CE l
OE l
AOl - A 10l
INTl
L
L
X
X
X
X
X
7FF
X
X
X
X
X
X
X
L
L
7FE
R/W L
FUNCTION
CE R
OE R
X
X
X
X
X
L(2)
L
L
7FF
H(3)
Reset Right I NTR Flag
L (3)
L
L
7FE
X
X
X
X
Set Left I NTL Flag
H(2)
X
X
R/W R
INTR
AOl -A 1OR
X
Set Right INT R Flag
Reset Left INT l Flag
NOTES:
1. A~s BUSYl = BUSYR = H.
2. If BUSY l = L, then NC.
3. If BUSYR = L, then NC.
4. H = HIGH, L= LOW, X = DON'T CARE, NC= NO CHANGE
TABLE 111- ARBITRATION (2)
LEFT PORT
FLAGS (l)
RIGHT PORT
FUNCTION
CE l
CE R
AOl - A 10l
AOl - A10R
BUSYL
BUSYR
H
X
H
H
Any
H
X
X
H
L
H
H
No Contention
H
X
L
Any
H
H
No Contention
H
H
No Contention
L
t- AOR-AlOR
t- AOl -A10L
L
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
LV5R
L
LV5R
H
L
L-PortWins
L
RV5L
L
RV5L
L
H
R-PortWins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R
= AOR-AlOR
LL5R
= AOL-Al0L
H
L
L-PortWins
RL5L
= AOR-AlOR
RL5L
= AOl -Al0L
L
H
R-PortWins
LW5R
= AOR- A l0R
LW5R
= AOL -Al0L
H
L
Arbitration Resolved
LW5R
= AOR-Al0R
LW5R
= AOL-Al0L
L
H
Arbitration Resolved
NOTES:
1. INT Flags Don't Care.
2. X = DON'T CARE, L = LOW, H= HIGH
LV5R = Left Address Valid ~ 5ns before right address.
RV5L= Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left
= LOW ~ 5ns before Right
RL5L = Right
= LOW ~ 5ns before Left
LW5R = Left and Right CE = LOW within 5ns of each other.
cr
cr
cr.
cr.
.
S5-49
IDT71321SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxx
Devic~
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
y:rMk
J
~--------------~ L
25
30
35
~--------------------~ 45
55
70
LA
'------------------~ SA
'------------------------i
71321
71421
Commercial (OOC to
PLCC
LCC
Commercial Only
Only
Commercial
Commercial Only
1.
Speed in Nanoseconds
Military Only
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
wI Interrupt·
16K (2K x 8-Bit) SLAVE Dual-Port RAM
wI Interrupt
S5-50
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Intesrated Device TechnoIogy.Inc.
ADVANCE
INFORMATION
IDT 7012
HIGH-SPEED
2K X 9 DUAL-PORT
STATIC RAM
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
- IDT7012S
Active: ---mW(typ.)
Standby: --mW(typ.}
- IDT7012L
Active: ---mW(typ.}
Standby: ---mW(typ.}
• Fully asychronous operation from either port
• Each port has a 9-bit wide data path. The 9th bit could be
used as the parity bit.
.
The IDT7012 is an extremely high-speed 2K x 9 dual port static
RAM designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those systems
which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides
simunltaneously access the same dual-port location.
The IDT7012 provides two independent ports with separate
control, address and I/O pins that permit independent,
asychronous access for reads or writes to any location in memory.
It is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An
automatic power down feature controlled by CE permits the onchip circuitry of each port to enter a very low standby power mode.
The IDT7012 utilizes a 9-bit wide data path to allow for control
and parity bits at the user's option. This feature is especially useful
in data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
.
Fabricated using IDT's CEMOS TM. high-performance technology, these devices typically operate on only -~-mW of power at
maximum access times as fast as 25ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---';JW from a 2V battery.
The IDT7012 is packaged in 48-pin sidebrazed or plastic DIPs,
48- or 52-pin LCCs and 52-pin PLCCs. The military devices are
processed 100% in compliance to the test methods of MILSTD-883, method 5004.
•
•
•
•
Battery backup operation-2V data retention
TTL compatible, signal5V (± 10%) power supply
Available in popular hermetic and plastic packages
Military product compliant to MIL-STD-883, Class B
(;II
FUNCTIONAL BLOCK DIAGRAM
RiW l
RIWR
GEL
OE: l
CE'R
OE'R
A10l
All
A10R
A7R
I/0al
II0aR
I/00l
110 OR
A6l
AOl
A6R
AOR
CEMOS is a trademark of Integrated Device TechnologY,lnc.
JANUARY 1989
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© t 9a9 Integrated Device Technology. Inc.
DSC-t049/-
S5-51
----------_...
_
...
_---------_.
fi
Integrated Devk:e1echnoIogy.Inc.
HIGH-SPEED 2K X 9
DUAL-PORT STATIC RAM
WITH BUSY & INTERRUPT
ADVANCE
INFORMATION
IDT 70121
IDT 70125
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 35/45/55/70ns (max.)
The IDT70121/IDT70125 are high-speed 2K x 9 dual port static
RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT70125 "SLAVE" dual-port in 18-bit-or-more word width systems. Using the IDT MASTER/SLAVE dual-port RAM approach in
18 bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
The IDT70121 utilizes a 9-bit wide data path to allow for Data!
Control and parity bits at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 25ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---mW from a 2V battery.
The IDT70121/70125 devices are packaged In 52-pin LCCs and
52-pin PLCCs. The military devices are processed 100% in compliance to the test methods of MIL-STD-883, method 5004.
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
- IDT70121/70125S
Active: ---mW(typ.)
Standby: ---mW(typ.)
- IDT70121/70125L
Active: -~-:-mW(typ.)
Standby: ---mW(typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18 bits
or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
• BOSY output flag on Master; BUSY Input on Slave
• iNiflag for port-to-port communication
• BattelY backup operation-2V data retention
• TIL compatible, signal5V (± 10%) power supply
• Available In popular hermetic and plastic packages
• Military produCt compliant to MIL-STD-883, class B
FUNCTIONAL BLOCK DIAGRAM
R~L --~------~~----~
~L=====~{)~--I
'Ot:
L
-Al0L -~--+--...,
A7L
fl08L
flOoL
flOoR
'---------f--
BDS?L(l)-.,.--------+'
ABL -+~~-+I
AOL -+----"'---+1
tmS?R(l)
ABR
AOR
Al0L
-~~-.r====:;.---:-- Al0R
AOL
ARBITRATION
_crL ------tl- INTERRUPT
OE'L
LOGIC
R~L
AOR .
~R
at: R
R~R
1NT~2)
NOTE:
1. 70121 (MASTER~8~";Y is open drain output and requires pullup resistor.
70125(SLAVE):
is input.
2. TNT is open drain output and requires pullup resistor.
CEMOS Is a trademark of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Devtce Technology. Inc.
JANUARY 1989
DSC-l05O/-
S5-52
~
lOT 713225'
lOT 71322L
CMOS DUAL-PORT RAM
16K (2K X 8-BIT)
WITH SEMAPHORE
Integrated Device1echnoIogy.Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 35/45/55/70ns (max.)
• Low-power operation
- ID171322S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- ID171322L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation-2V data retention
• TIL-compatible, single 5V(±10%) power supply
• Available in a variety of plastic and hermetic packages for both
through hole and surface mount applications
• Military product compliant to MIL-STD-883, Class B
The ID171322 is an extremely high-speed 2K x8 dual-port static
RAM with full on-chip hardware support of semaphore signalling
between the two ports.
The ID171322 provides two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in memory. To assist in arbitrating between ports, a fully independent semaphore
logic block is provided. This block contains unassigned flags
which can be accessed by either side; however, only one side can
control the flag at any time; An automatic power down feature, controlled by CE and 'S"EM, permits the on-chip circuitry of each port
to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, this device typically operates on only 500mW of power at
maximum access times as fast as 35ns. Low-power (L) versions offer battery backup data retention capability, with each port typically consuming 200jJ.W from a 2V battery.
The ID171322 is packaged in a 48-pin sidebraze or plastic DIP
or 52-pin LCC and PLCC. Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class B.
(;W
FUNCTIONAL BLOCK DIAGRAM
MEMORY
ARRAY
~
-
-
"*
SEM L
AOL - A10L
SEMAPHORE
LOGIC
...
,
~
-
--
LEFT SIDE
ADDRESS
DECODE
LOGIC
RIGHT SIDE
ADDRESS
DECODE
LOGIC
-..
SEMR
AOR - AIOR
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-l032/-1
S5-53
--------------------_._-----_.. _-._-._--
IDT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x S-BIT) WITH SEMAPHORES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
c5'£~ul~~,.u' 8~~liuz ~
INDEX~ ~.....nlU
...........a:....Rn.......,........
.,,...-- 1I0sR-I/OI5R
I/OOL-1I07L ---,<'--------L.:.:.:J--L...:;,.;.--''-.r, n/>L..~:......J--L.::.::.:J---4-----'T-- 1I0oR-I/07R
1IDSVL(I)
lIDSV (I)
r:-:--k-----i---- A7R
AOL
.....--1--- AOR
---+---1.,.
A10L ------II~
NOTES:
1. IDT7133 (MASTER): BUSY is open drain
output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
2. LB = LOWER BYTE
US = UPPER BYTE
R
AOL - - - - - - . t
CEL------.t
01\-------.t
RANLUB - - - - - . . .
. RIWLLB ----~
A10R
ARBITRATION
LOGIC
(IDT7133
ONLy)
1+----- AOR
1+-----Cl:R
1+------ OE R
RANRUB
R/W RLB
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-l033/1
1989 Integrated Device Technology. Inc.
S5-65
IDT7133S/LAND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
11
53
.10
A8L
55
09
DIP
TOP VIEW
A lOL
44
51
A6L
50
A5L
48
A3L
46
AIL
tiO'SYL
52
49
47
45
43
A7L
A4L
A2l
cr R
41
eEL
AOL
40
42
AOR
38
A2R
36
A4R
39
37
35
34
A5R - A6R
tiO'SYR AlA
A3R
54
A9l
32
A8R
33
A7R
08
56
57
RIWlLB OE: L
30
Al0R
31
A9R
59
58
Vee (l) RIWLUB
28
RIWRlE
29
07
06
61
I/O IL
05
62
63
1/0 3l 1/0 2l
24
25
1/0 14R 1/0 15R
04
65
1/0 5L
64
1/0 4l
23
22
1/012R 1/013R
03
67
1/0 7l
66
1/0 6l
21 _
20
110 lOR 1/0 11R
02
68
I/0 Sl
1
1/09l
01
•
Pin 1 /
Designator
A
G68-1
&
PG68-1 (PPGA)
60
1/0 0l
3
1/0 11L
2
4
1/01Ol 1/0 12l
B
C
5
1/0 13l
7
9
11
1/015l GND(2) I/O I R
6
'8
1/014l Vee (1)
D
E
13
1/0 3R
15
1/0 5R
18
1/0 8R
16
1/06R
17
I/0jR
10
I/O OR
12
1/02R
14
1/04R
F
G
H
K
PGA TOP VIEW (Ceramic or Plastic)
NOTES:
1. Both Vee pins must be connected to the supply to assure
reliable operation.
2. Both GND pins must be connected to the supply to assure
reliable operation.
3. UB = Upper Byte; LB = Lower Byte.
IDID
.- 3
-I-J-I-I....J
~
....J-I-I....J-~~...J-l
co ...... (o~...,C"')C\I-08
~o~...J...J
ggggggggg>~~ ~~<~
9 8 7 6 5 4 3 2 1 686766 6564 6362 61
1/09l
1/01OL
1/0 11l
1/012L
1/0 13l
1/014L
1/015l
Vee (l)
GND(2)
I/OOR
I/O IR
1/02R
1/0 3R
1/04R
1/05R
1/0 6R
1/0 7R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
J68-1
&
L68-2
2728 29303132 3334 353637383940414243
~ ~ ~ ~ ~ ~ ~ ffifS ~ ~ a: ~ ~ ffi ~ ~
00 ~ ~ ~ ~ ~ ~o ~~ ~ Vee -0.2V MIL.
Full Standby Current V, >-v,
-0.2V or
(One Port-All CMOS IN - ee
_
(5) \'IN ::; 0.2V
Level Inputs, 1 - 0
Aetive Port Outputs COM'L.
Open, 1 = f MAX (4)
CE =\'Il
Outputs Open
f = fMAX(4)
75
75
rnA
-
S
170
45
160
45
155
L
150
40
140
40
135
S
L
150
45
140
45
140
45
135
130
40
120
40
120
40
115
rnA
NOTES:
1. O°C to + 70°C temperature range only.
2. Vee= 5V, TA = +25°C
3. ·x" in part numbers indicates power rating (S or L).
4. At 1 = fMAX' address and data inputs (except Output Enable) are cycling atthe maximum frequency 01 read cycle of 1/tRc, and using "AC TEST CONDITIONS" of input levels of GND to 3V.
5. f = 0 means no address or control lines ehange. Applies only to inputs at CMOS level standby.
S5-68
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K(2Kx 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(1)
(L Version Only) VLC = 02V V HC = VCC - 0 2V
VOR
IDT7133S/UIDT7143S/L
MIN.
MAX.
TEST CONDITION
PARAMETER
SYMBOL
Vee for Data Retention
I MIL.
I COM'L.
leeoR
Data Retention Current
Vcc = 2.0V
t COR (3)
Chip Deselect to Data Retention Time
"'N 2:: VHCor ~ VLC
t R(3)
Operation Recovery Time
lu(3)
Input Leakage Current
CE~ VHc
UNIT
2.0
-
V
-
4000
J.lA
1500
J.lA
0
-
ns
t RC (2)
-
ns
2
J.lA
-
NOTES.
1. Vcc = 2V, TA = +'2soC.
2. t RC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vce DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.SV
tR
AC TEST CONDITIONS
GNDto 3.0V .
5ns
1.5V
1.5V
See Figures 1, 2, & 3
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
:q
SV
DATAoUT
7750.
DATA OUT
Figure 1. Output Load
:q
BUSY.
.
7750.
5pF*
Figure 2. Output Load
(for tLZ.t HZ ' twz.t ow )
* Including scope and jig.
55-69
---±~
.
5V 12sm
12SCX1
30pF*
5V
2700
f
PFO
Figure 3. BUSY Output
Load
(IDT7133 only)
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
IDT7133S/L45 (2)
I DT7143S/L45 (2)
COM'LONLY
MIN.
MAX.
PARAMETER
IDT7133S/L55
IDT7143S/L55
MIN.
MAX.
IDT7133S/L70
IDT7143S/L70
MIN.
IDT7133S/L90
I DT7143S/L90
MIN.
MAX.
UNIT
MAX.
READ CYCLE
t RC
Read Cycle Time
45
,,::::,:,::::::::
55
-
70
-
90
-
ns
tAA
t AcE
Address Access Time
45
-
70
ns
55
-
70
90
ns
35
-
40
-
90
Output Enable Access Time
-
55
t AOE
-
tOH
Output Hold From Address Change
0
-
10
-
tLZ
Output Low Z Time(l. 3)
5
-
5
-
5
-
ns
tHZ
Output High Z Time(1. 3)
20
-
20
-
25
-
25
ns
tpu
Chip Enable to Power Up Time (3)
-
0
-
0
-
0
-
ns
tpo
Chip Disable to Power Down Time (3)
50
-
50
-
50
-
50
ns
Chip Enable Access Time
.::..'::::'41:;:-:'
.::;::::'::"\30
O::::::::'\}:::; 5 ::::::::;:;;;;::;::.. .+:;;;::::::)::.
.i!)ti:t
.::::::(:~
0
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (see Figures 1. 2 & 3).
2. O°C to + 70°C temperature range only.
3. This parameter is guaranteed but not tested.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
(1.2,4)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
(1,3)
1 - + - - - - - tAcE------I~1
----~I
L
DATA OUT
....- - - tLZ---~
po
tpU--t Icc __________________~--------------------------------·~
CURRENT
_____________---' 50%
50%
Iss
1
NOTES:
1. RiW is high for Read Cycles.
2. Device is continuously enabled, CE = "'tL'
3. Addresses valid prior to or coincident with CE transition low.
4. OE = V1L
S5-70
40
ns
.
ns
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
PARAMETER
SYMBOL
I DT7133S/L45 (2)
I DT7143S/L45 (2)
MIN.
MAX.
IDT7133S/L55
1DT7143S/L55
MIN.
MAX.
IDT7133S/L70
IDT7143S/L70
MIN.
MAX.
IDT7133S/L90
IDT7143S/L90
MIN.
MAX.
UNIT
WRITE CYCLE
twc
Write Cycle Time(4)
45
tEW
Chip Enable to End of Write
30
tAW
Address Valid to End of Write
30
t AS
Address Setup Time
0
twp
Write Pulse Width(6)
30
tWR
Write Recovery Time
0
tow
Data Valid to End of Write
15 .:::::::::::::t;::;:::-_
20
-
tHZ
Output High Z Time(1·3)
-·::::::::::::::::}i 20
-
20
tDH
Data Hold Time (5)
twz
Write Enable to Output in High Z(1·3)
tow
Output Active From End of Write(1.3.5)
~:}}:::..
.:::h:\::::::::
.:::::::i:::::::::;:··
·:::;::;::::;2::::'
.::;;:;;:;:::::::;L'
3t::::::~
~\(t:::):
.::S@::::::::::
'::::::::l:(::::.
55
40
40
0
40
0
70
-
90
50
85
0
-
25
-
30
-
-
25
-
25
ns
50
0
50
85
0
55
0
ns
ns
ns
ns
ns
ns
ns
-
5
-
5
-
5
-
ns
20
-
20
-
25
-
25
ns
-
5
-
5
-
5
-
ns
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (see Figures 1, 2 & 3).
2. O°C to + 70°C temperature range only.
.
3. This parameter is guaranteed but not tested.
4. For MASTER/SLAVE combination. twc = tBAA + tWR + t wp ·
5. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature. the actual tDH will always be smaller than the actual tow.
6. Specified for 'DE' at high (Refer to "Timing Waveform of Write Cycle", Note 7).
S5-71
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (R/W CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS
~
--./
<
)(
t
(6)-
HZ
/V
tAW
~
~V
i\.
~tAS-
t
"'-,
Rm(8)
(7)
tWR
Wp
f--
/V
~twt)tow
DATAo~
/.
/.
(4)
r--tOW
-
t OH -
'"
1/
"'-
WRITE CYCLE NO.2 (CE CONTROLLED TIMING)
.(4)/.~
./
(1,2,3,5)
twc
ADDRESS
~
)K
-----./ (
tAW
_t
AS
1
1
~V
tWR
tEW
f--
Rm(8)
,
DATA IN
I'
tow
tOH
'-I
/1
NOTES:
1.
2.
3.
4.
5.
6.
7.
RNi or CE must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low C'E and a low R!W.
tWR is measured from the earlier of
or R!W going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.
Transition Is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If OE is low during a R!W controlled write cycle, the write pulse width must be the larger of twp or ( twz + tow) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tow. If ~ is high during an RiW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP '
8. Rm for either upper or lower byte.
cr
55-72
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2Kx 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
PARAMETER
IDT7133S/L45 (1)
IDT7143S/L45 (1)
MIN.
MAX.
1DT7133S/L55
I DT7143S/L55
MAX.
MIN.
IDT7133S/L70
IDT7143S/L70
MIN.
MAX.
IDT7133S/L90
IDT7143S/L90
MIN.
MAX.
-
UNIT
BUSY TIMING (For MASTER IDT7133)
·::::::::::4?
-
50
-
55
.: : : : : : . ~q.
-
45
::{(So
-
40
BUSY Access Time to Chip Enable
-
35
-
35
tsoc
BUSY Disable Time to Chip Enable
-
::::}:::::::i~::?5
-
30
-
30
twoo
Write Pulse to Data Delay (2)
:::::::::)})::80
-
80
Write Data Valid to Read Data Delay (2)
:::; ::::::;:;:;::::::::·55
-
55
tsoo
BUSY Disable to Valid Data(3)
-
Note 4
-
90
tOOD
-
tAPS
Arbitration Priority Set Up Time (4)
-
5
-
-
0
30
-
30
tSAA
BUSY Access Time to Address
tSOA
t SAC
BUSY Disable Time to Address
BUSY INPUT TIMING (For SLAVE IDT7143)
tws
Write to BUSY (5)
tWH
Write Hold After BUSY (6)
t woD
Write Pulse to Data Delay (7)
...........:.;..
.:::::::::::::::::: I'V'" 4
Et':::::::::::::::::::::
~.:
.
:;::/
55
ns
45
ns
45
ns
45
ns
100
ns
70
-
90
ns
Note 4
-
Note 4
ns
5
-
10
-
ns
0
-
0
-
ns
30
-
ns
100
ns
90
ns
..:..
.{!i:::;:·:::::::::::
.::::::~ ft':::::::=
:;:i:;:::::l }::';:::
80
-
80
::::::::::/4:::::
Write Data Valid to Read Data Delay (7)
55
55
tO~~
NOTES:
1. O°C to + 70°C temperature range only.
2. Port-to-port delay through RAM cells from writing port to reading port,
refer to "TIMING WAVEFORM OF READ WITH BUSY (For Master IDT7133)"
3. tSOD is calculated parameter and is greater of 0, twoo - twp (actual) or tOOD - tow (actual).
4. To ensure that the earlier of the two ports wins.
5. To ensure that the write cycle is inhibited during contention.
6. To ensure that a write cycle is completed after contention.
7. Port-to-port delay through RAM cells from writing port to reading port,
refer to "TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY (For Slave IDT7143)"
55-73
-
90
70
-
IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH BUSy(l.2. 3)(For MASTER IDi7133)
two
~t
ADDRR
"J\
MATCH
J~
,
twp
Jr
\
..
J
1 4 - tow
J'IJ\
~t"'''i;
tOH
'"
VALID
J~
MATCH
)
t BoA -
__ l-
~ ~\
BUSYl
t BoO -
J
twoo
DATAoUT l
NOTES:
1. To ensure that the earlier of the two p arts wins.
2. Write cycle parameters should be adhered to for ensuring proper writing.
3. Device Is oontinously enabled for both ports.
4. OE' at LO for the reading port.
-~
VALID
J~
VALID
tOOo!4)
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(l. 2. 3)(For SLAVE IDT7143)
two
"
''I
MATCH
J\
J\
twp
Jr
~
J
'I
~tow
:Jf-
DATAIN R
J~
tOH
"
VALID
J\
MATCH
ADDRl
twoo
'"
DATAoUT l
tO~~
NOTES:
1. Assume BUS? input at HI for the writing port. and OE: at LO for the reading port..
2. Write oycle parameters should be adhered to for ensuring proper writing.
3. Device is continously enabled for both ports.
TIMING WAVEFORM OF WRITE WITH BUSY INPUT (For SLAVE IDT7143)
twp------------~
Rm
~t~
~
[_tWH_
_ _ _ _I
S5-74
1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
eEL VALID FIRST:
ADDR
LAND R
=x
>C
ADDRESSES MATCH
~'~l t:"OC=1eE R VALID FIRST:
ADDR
LAND R
BUSY L
=x
>C
ADDRESSES MATCH
~'~l t:'~J-
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION (1)
LEFT ADDRESS VALID FIRST:
~--- tRcORtwc----~
ADDRL
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDRR
.aAA9____tBD_A-=--=--.l~--RIGHT ADDRESS VALID FIRST:
~--- tRcORtwc----~
ADDRR
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDRL
NOTE:
1.
GEL
= CE R = V1L
S5-75
--------,,---"--
---------
1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2KX 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT7133/43 pravides twa parts with separate cantral, address and I/O pins that permit independent access far reads ar
writes to. any lacatian In me mary. The devices have an autamatic·
pawer dawn feature cantralled by CEo The CE cantrals an-chip
pawer dawn circuitry that permits the respective part to. go. into. a
standby mode when nat selected (CE high). When a part is enabled, access to. the entire mema!YJlrray is permitted. Each part
has its own Output Enable cantrol (OE). In the read made, the part's
~ turns an the autput drivers when set LOW. Nan-cantentian
READ/WRITE canditians are illustrated in Table I.
.
arbitrates between the left and right addresses far access (refer to.
Table II). In either made af arbitratian,.the delayed part's BUSY flag
is set and will reset when the port granted access campletes its ap. eratian.
ARBITRATION·LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitratian lagic will resalve an address match ar a chip enable match dawn to. 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set far the delayed
part.
.
The BUSY flags are pravided far the situatian when bath parts
simultaneausly access the same me mary lacatian. When this situatian accurs,an-chip arbitratian lagic will determine which part has
access and sets the delayed part's BUSY flag. BUSY is set at
speeds that permit the processor to. hald the operatian and its respective address and data. It is impartant to. nate that the aperatian
is invalid far the part that has BUSY set LOW. The delayed part will
have access when BUSY gaes inactive.
Cantentian accurs when bath left and right parts are active and
both addresses match. When this situation accurs, the an-chip arbltratian laglc determines access. Twa mades af arbltratlan are
pravided: (1) if the addresses match and are valid befare CE, anchip cantrallagic arbitrates between CELand CE R far access; ar (2)
if the CEs are law befare an address matCh, an-chip cantrallagic
DATA BUS WIDTH EXPANSION,
MASTERISLAVE DESCRIPTION:
Expanding the data bus width to. 32 bits ar mare in a dual-part
RAM system implies that several chips will be active at the same
time. If each chip includes a hardware arbitratar, and the addresses
far each Chip arrive at the same time, it is passible that ane will activate its BUSYL while anather activates its BUSYR signal. Bath sides
are naw busy and the CPUs will wait indefinitely far their part to. became free.
.
.
To. avaid this "Busy Lack-Out" problem, IDT has developed a
MASTER/SLAVE approach where anly ane hardware arbitratar, in
the MASTER, is used. The SLAVE has BUSY inputs which allaw an
interface to. the MASTER with no. external campanents and with a
speed advantage aver ather systems.
When expanding dual-part RAMs in width, the writing af the
SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
cantentian situatian. Canversely, the write pulse must extend a
hold time past BUSY to. ensure that a write cycle takes place after
the cantentian is resalved. This timing is inherent in all dual-part
memary systems where mare than ane chip is active at the same
time.
The write pulse to. the SLAVE shauld be delayed by the maximum arbitratian time af the MASTER. If, then, a cantentian accurs,
the write to. the SLAVE will be inhibited due to. BUSY fram the
MASTER.
TABLE I-NON-CONTENTION READ/WRITE CONTROL(4)
LEFT OR RIGHT PORT (1)
FUNCTION
CE·
OE
X
X
H
X
X
X
H
X
Z
L
L
L
X
DATAIN
DATAIN
Data on Lower Byte and Upper Byte Written into Memory(2)
L
H
L
L
DATAiN
DATAoUT
Data on Lower Byte Written into MemorY,2)Oata in Memory Output on Upper Byte (3)
H
L
L
L
DATA OUT
DATA IN
Data in Memory Output on Lower Byte~3)Data on Upper Byte Written into Memory(2)
L
H
L
H
DATA IN
Z
Data on Lower Byte Written into Memory(2)
H
L
L
H
Z
DATA IN
Data on Upper Byte Written into Memory(2)
H
H
L
L
H
H
L
H
R/WLB
R/WUB
.1/0 0 - 7
'Z
DATA OUT
Z
1/0 8 - 15
Z
Z
DATA OUT
Z
Port Disabled and in Power Down mode, ISB2 or ISB4
CE R= CE L = H. Power Down Mode. ISBl or ISB3
Data in Memory Output on Lower Byte and Upper Byte(3)
High Impedance Outputs
NOTES:
1.
2.
3.
4.
AOL - A10L ~ AOR - Al0R
If BUSY = L, data is not written.
If BUSY = L. data may not be valid, see twoo and tO~~ timing.
H = High, L = Low, X = D.on't Care, Z = High Impedance, LB
= Lower Byte, US = Upper Byte
S5-76
1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K X 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE II-ARBITRATION
\
FLAGS (1)
RIGHT PORT
LEFT PORT
CE L
FUNCTION
BUSYL
BUSYR
AOL - A 10L
CER
H
X
H
X
H
H
No Contention
L
Any
H
X
H
H
No Contention
H
X
L
Any
H
H
No Contention
H
H
No Contention
A oR - A1DR
L
f. AOL -AlOL
t- AOR-Al0R
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
LV5R
L
LV5R
H
L
L-PortWins
L
RV5L
L
RV5L
L
H
R-PortWins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
= AOL -Al0L
= AOL-Al0L
= AOL-Al0L
= AOL -Al0L
H
L
L-PortWins
L
H
R-PortWins
H
L
Arbitration Resolved
L
H
Arbitration Resolved
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
= AOR-AlOR
= AOR-Al0R
= AOR-Al0R
= AOR-Al0R
LL5R
RL5L
LW5R
LW5R
LL5R·
RL5L
LW5R
LW5R
NOTE:
1. X = Don't Care, L = Low, H = High
LV5R = Left Address Valid :::: 5ns before right address
RV5L = Right Address Valid :::: 5ns before left address
Same = Left and Right Address match within 5ns of each other
CAPACITANCE
SYMBOL
LL5R = Left CE = LOW :::: 5ns before Right CE
RL5L = Right
= LOW :::: 5ns before Left ~
LW5R = Left and Right CE = LOW within 5ns of each other
cr
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CIN
Input Capacitance
Caul
Input/Output
Capacitance
CONDITIONS
VIN = OV
VI/O = OV
MAX.
UNIT
11
pF
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
S5-77
- - - - - _••...._--_ ...- - - - _.._--_._.
IDT7133S/L AND 1DT7143S/L
CMOS DUAL-PORT RAM 32K (2K X 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT MASTER/SLAVE DUAL-PORT MEMORY, SYSTEMS
LEFT
RIGHT
-
RNi
-/\./V\r
-...
BUSY
+5V
RNi
---
RNi
IDT7133
MASTER
BUSY
+5V
-~
RNi
IDT7143
SLAVE(1)
~ BUSY
/\.IV'-
BUSY
~
, NOTE:
1. No arbitration in IDT7143 (SLAVE). BUSY-IN inhibits write in IDT7143 (SLAVE).
ORDERING INFORMATION
IDT
xxxx
999
Speed
Device Type
A
A
Package
Process/
Temperature
Range
y:'Mk
XC
Militaty (-55°C t~ + 125°C)
Compliant to MIL-STD-883, Class B
PG
Sidebraze Shrink-DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Ceramic Pin Grid Array
Plastic Pin Grid Array
45
Commercial Only
J
~--------------~ ~
1
~--------------------~I
Commercial (O°C to + 70°C)
1
Speed in Nanoseconds
55
70
90
~
____________________~IL
,S
7133
~--------------------------------------~ 7143
S5-78
Low Power
Standard Power
32K (2K x 16-Bit) MASTER Dual-Port RAM
32K (2K x 1B-Bit) SLAVE Dual-Port RAM
t;)
Integrated Deviceledmology.lnc.
CMOS DUAL-PORT RAM
32K (4K x 8-BIT)
lOT 7134S
lOT 7134L
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 45/55/70ns (max.)
- Commercial: 35ns (max.) Preliminary
• Low-power operation
- IDT7134S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT7134L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in several popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
The IDT7134 is an extremely high-speed 4K x 8 dual-port static
RAM designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those systems
which cannot tolerate wait states or are designed to be able to
externally arbitrate or withstand contention when both sides
simultaneously access the same dual-port RAM location.
The IDT7134 provides two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the
user's responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high~performance teChnology, these dual-ports typically operate on only 500mW of power at
maximum access times as fast as 35ns. Low-power (L) versions
offer battery backup data retention capability, with each port
typically consuming 200~W from a 2V battery.
The I0T71 34 is packaged in either a sidebraze or plastic 48-pin
DIP, 48-pin or 52-pin LCC, and 52-pin PLCC. Military grade
product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
R~L--~---------a
CE L ---4-+-------O
DEL -------a_.I
....E-------------------'.. I/OoRCOLUMN
AOL - A"L --------__~
LEFT SIDE
ADDRESS
DECODE
LOGIC
I/07R
COLUMN
I/O
1/0
MEMORY
ARRAY
RIGHTSIDE
ADDRESS
DECODE
LOGIC
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-l034/-
S5-79
5
IDT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
....
a:
6,................
~::o I~
:a:
: a:
~
c:(1Oc:(c:(z
10>10a:1~ 0Zc:(c:(
""0
)U,/ 0)U,/
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
7 6 5 4 3 2
U 525150 49 4B 47
J52-1
&
L52-1
J
2~1
222324252627 2B
.... oJ""
OER
46:::
45:::
44[
43[
42 :::
41 :::
40:::
39 :::
3BC
371:
36:::
35:::
1
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ABR
ASR
NC
II0 7R
3031 32 3334:::
29
""00 a: a: a: a: a: a: a:
oooozzooooooo
CJ::::::::::::::::::::::::::::::::-
:::::::::::::::::
LCC/PLCC
TOP VIEW
DIP
TOP VIEW
wuuw:....::::....:wuuuw
6 5 4 3 2 LJ 4B 47 46 454443
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output Current
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
o to
AlL
A2L
A3L
A4L
A 5L
A6L
A7L
+70
-55 to +125
°C
42[
41[
40[
39[
3B [
37[
L4S-1
36(:
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
1.5
1.5
W
50
50
mA
AOR
A1R
A2R
A3R
A4R
A5R
A6R
~:~: ~~:
I/OoL ] 16
33[
I/0 1L ] 17
32[
31
I/02L ] l~S 20 21 22 23 24 25 26 2726 2930 [
ASR
I/07R
I/06R
nnnr-:nnnnnnnn
LCC
TOP VIEW
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
SYMBOL
1
]8
]9
] 10
] 11
] 12
] 13
~~~ :~::
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
]7
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V
O°Cto +70°C
OV
5.0V
Vec
± 10%
± 10%
RECOMMENDED DC OPERATING CONDITIONS
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CIN
Input Capacitance
COUT
Output CapaCitance
SYMBOL
CONDITIONS
MAX.
PARAMETER
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
V
Input Low Voltage
-0.5(1)
-
6.0
VIL
O.S
V
UNIT
UNIT
VIN = OV
11
pF
VOUT= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
S5-S0
IDT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
(Vcc = 5.0V ±10%)
IDT7134S
MIN.
MAX.
TEST CONDITIONS
PARAMETER
IDT7134L
MIN.
MAX.
UNIT
Ilu l
Input Leakage Current
Vee = 5.5V, "'IN = OV to Vee
-
10
-
5
J..I.A
IILOI
Output Leakage Current
CE = "'IH,VoUT = OV to Vee
10
-
5
J..I.A
0.4
-
0.4
10l = BmA
-
0.5
-
0.5
IOH= -4mA
2.4
-
2.4
-
VOL
Output Low Voltage
VOH
Output High Voltage
10l = 6mA
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1)
-~"',
SYMBOL
.0:
PARAMETER.!
\
Icc
IS81
IS82
IS83
IS84
TEST CONDITION VERSION
Dynamic Operating" CE =V1l
Current (Both Ports Outputs Open
f = f MAX (3)
Active)
Standby Current
(Both Ports - TIL
Level Inputs)
CEl and CER ~ "'IH
f = fMAX(3)
Standby Current
(One Port- TTL
Level Inputs)
CE lor CE R ~ V1H
Active Port Outputs
Open, f = fMAX (3)
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
S
L
r
r
r
S
L
S
L
S
Both Ports CE land MIL.
L
Full Standby Current CE R ~ Vce-0.2V
~oth Ports - All
MOS Level Inputs) "'IN ~ Vee -0.2V or COM'L.S
"'IN :::; 0.2V, f = 0(3)
L
One Port CE l or
CE R ~ Vec- 0 .2V
Full Standby Current
(One Port-All CMO!: "'IN ~ Vee -0.2V or
V1N :::; 0.2V,
Level Inputs)
Active Port Outputs
Open, f = f MAX (3)
MIL.
S
L
COM'L.
r
IDT7134x35 (4)
TYP.(2) MAX.
-
-
-
:::\:::::::.
::.::::;;:;:~~.
:{:::::::\;::
:::::::\)7.5
"45
= ;: : : : : : : : : : :
=;··:::::··::::::.::ng
....;-:::,::::::::;.;.
_:::;::tt::::::::::-
-
:::::::::::::::::::=J.~
:;:;:;:;::;:;::;:;:.:;:::
4.:;":I:::::::::::= -
:;[;:I/::::::::: -
V
V
(Vee = 5.0V ±10%)
IDT7134x45
TYP.(2)
MAX.
IDT7134x55
TYP.(2)
MAX.
IDT7134x70
TYP.(2)
MAX.
100
100
100
100
25
25
25
25
50
50
50
50
1.0
0.2
240
200
200
160
70
50
70
40
160
130
130
100
30
10
100
100
100
100
25
25
25
25
50
50
50
50
1.0
0.2
230
180
200
160
70
50
70
40
150
120
130
100
30
10
100
100
100
100
25
25
25
25
50
50
50
50
1.0
0.2
230
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
50
45
130
100
50
45
120
90
50
45
120
90
45
45
110
90
45
45
110
90
45
45
110
90
lBO
200
160
70
50
70
40
150
120
130
100
30
10
UNIT
mA
mA
mA
mA
mA
,:::k::::::::::::::·
120
100
NOTES:
1. "x· in part number indicates power rating (S or L).
2. Vec = 5V, TA = +25°C
3. fMAX = l/tRc = All inputs cycling at f = litRe (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS
level standy I S83 .
4. O°C to 70°C temperature range.
S5-81
IDT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
VDA
TEST CONDITION
PARAMETER
SYMBOL
Vcc for Data Retention
Vcc = 2V
ICCDA
CE ~VHC
~ VHC or::; VLC
Data Retention Current
\'IN
t CDA (3)
Chip Deselect to Data Retention Time
t A(3)
Operation Recovery Time
MIN.
TYP.(1)
MAX.
UNIT
2.0
-
-
V
100
4000
100
1500
-
-
ns
-
ns
I MIL.
I COM'L. 0
t AC (2)
NOTES:
1. Vec =.2V, TA = +25°C
2. tAC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
'tC
4.5V
tA
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
:q
5V
DATA OUT
7750
:q
5V
12500
DATA OUT
30pF*
7750
Figure 1. Output Load
12500
5pF*
Figure 2. Output Load
(for t LZ • t HZ ' twz .tow)
*Including scope and jig.
S5-82
J.l.A
1DT7134S AND 1DT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
IDT7134S55
IDT7134S70
IDT7134S35 (3) IDT7134S45
IDT7134L55
1DT7134L70
IDT7134L35 (3) IDT7134L45
MAX. MIN.
MIN.
MAX. MIN.
MAX. MIN.
MAX.
PARAMETER
UNIT
READ CYCLE
t RC
Read Cycle Time
35
tAA
Address Access Time
-
tAcE
Chip Enable Access Time
t AOE
Output Enable Access Time
-
tOH
Output Hold From Address Change
tLZ
.~
:.:.:
..;.;.:;....
/$$.;::'
::::\3$
::;:::::::'·::'20
45
-
55
-
70
-
ns
-
45
55
-
70
ns
45
-
55
-
70
ns
25
-
30
-
40
ns
5
5
5
-
ns
5
-
-
30
-
40
ns
Output Low Z Time(1. 2)
5 :.:::::%\:':5 .:.::.::::::::;::- -
5
-
tHZ
Output High Z Time(l. 2)
-::{::;;..::;:::.
-
25
t pu
Chip Enable to Power Up Time(2)
Jfi::;::=:
-
0
-
0
-
0
-
ns
t pD
Chip Disable to Power Down Time(2)
"':':::::;:'::.
50
-
50
-
50
-
50
ns
20
5
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. O°C to + 70°C temperature range only.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
(1,2,4)
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
(1,3)
~----- t A c E - - - -....1
DATA OUT
1 - + - - - - tLZ ---~
~
tpu __
t P D - L '.
lcc __________________~~---------------------------------.
CURRENT
__________
50%
50%
ISB
NOTES:
1. RiW is high for Read Cycles.
2. Device is continuously enabled. CE = ~L'
3. Addresses valid prior to or coincident with CE transition low.
4. DE = V1L
S5-83
ns
IDT7134S AND 1DT7134L
CMOS DUAL-PORT RAM 32K (4K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
IDT7134S35 (5) IDT7134S45
IDT7134L35 (5) IDT7134L45
MAX MIN.
MAX
MIN.
PARAMETER
IDT7134S55
IDT7134L55
MAX
MIN.
IDT7134S70
IDT7134L70
MIN.
MAX
UNIT
WRITE CYCLE
twc
Write Cycle Time
35
::::::;:,::::::::.
45
-
55
-
70
tEW
Chip Enable to End of Write
30
::;;;;:;:::.(.::::
40
50
-
60
tAW
Address Valid to End of Write
30
50
60
tAs
Address Set-up Time
0
-
twp
Write Pulse Width
50
-
60
tWR
Write Recovery Time
0
-
0
tow
Data Valid to End of Write
tHZ
Output High Z Time (1.2)
~~
tOH
Data Hold Time(3)
3
twz
Write Enabled to Output in
High Z(I.2)
::::?:::=::g:
0
30
::'::::::}::::;;;:;.
40
0
::;::;:;:;:;:;::::!-
0
-
20
-
25
-
30
-
-
20
-
25
-
30
ns
3
-
3
-
3
-
ns
-
20
-
25
-
30
ns
::::::;:;?4~
::::::::::::::::::;:;
.:.:."
-
::::::::::;:;;;::;;;;·20
J::;::{)t
tow
Output Active From End of Write(I.2.3)
3::::::: }:;::;:;:.
twoo
Write Pulse to Data Delay (4)
tooo
Write Data Valid to Read Data Delay (4)
1f::;
-
40
0
0
ns
ns
ns
ns
ns
ns
ns
-
3
-
3
-
3
60
-
70
-
80
-
90
ns
55
-
70
ns
35
45
ns
~
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. The specification for tOH must be met by the device supplying write data to the RAM under all operating conditions. Although tOH and tow values will vary
over voltage and temperature. the actual tOH will always be smaller than the actual tow.
4. Port-to-Port delay through RAM cells from writing port to reading port. refer to "TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY"
5. O°C to 70°C temperature range only.
6. Specified for
at high (Refer to "TIMING WAVEFORM OF WRITE CYCLE", Note 7).
m=
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAy(1)
twc
~'l
"
MATCH
J~
)\
twp
If
Jr-
~
J
I'--~r-
DATAIN R
ADDRL
J\
t ow VALID
MATCH
~,
J
twoo
J~
DATAoUT L
tODo
NOTE:
1. Write cycle parameters should be adhered to for ensuring proper writing.
S5-84
VALID
1DT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,4,8,7)
twc
ADDRESS
~
~
)(
K
t
(6)-
HZ
f
tAw
~
.~V
~
r--- t AS
t
""',
Rm
(7)
tWR
Wp
~V
-
_ t wi 6 ) _
tow
L · ( 4 ) · ....... ·•• ~ ~
(4)
DATA OUT
~tDW
t DH -
'"
/
DATA IN
1'-
./
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING
(1,2,3,5)
~-----------------------twc----------------------~~
ADDRESS
~---------------------tAW------------------~
,---~------------------
r---------------
tEW
------------.-1
Rm
DATA IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
Rm must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low C'E and a low Rm.
tWR is measured from the earlier of
or Rm going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + t DW ) to allow the I/O drivers to turn off
data to be placed on the bus for the required t DW ' If
is high during an RiW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wp .
cr
rn:
55-85
1017134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 1- NON-CONTENTION
READ/WRITE CONTROL
FUNCTIONAL DESCRIPTION:
The IDT7134 provides two ports with separate control, address
and I/O pins that permit Independent access for reads or writes to
any location in memory. These devices have an automatic power
down feature controlled by CEo The CE controls on-chip power
down circuitry that permits the respective port to go Into standby
mode when not selected (CE high). When a port is enabled, access
to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. Non-contention READ/WRITE
conditions are Illustrated In the table below.
LEFT OR RIGHT PORT (1)
FUNCTION
R/W
CE
OE
X
H
X
Z
Port Disabled and in Power Down
Mode.ls82 or IS84
X
H
X
Z
CE R = CE l = H. Power Down
Mode. IS81 Or IS83
L
L
X
DATA IN
Data on Port Written Into Memory
H
L
L
DATAoLrr
Data in Memory Output on Port
X
X
H
00-7
Z
High Impedance Outputs
NOTE:
1. AOl -A11l""AOR-A11R
H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
ORDERING INFORMATION
IDT
XXXX
A
Device Type Power
999
A
A
Speed
Package
Process!
Temperature
Range
I·
I
Blank
~B
P
C
' - - - - - - - - - - ; JL52
L48
1
35
45
~---------------------~I 55
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP
PLCC
LCC
LCC
Commercial onlY}
.
Speed in Nanoseconds
70
~
______________________-;I
L
IS
~-----------------I1·7134
S5-86
Low Power
Standard Power
32K (4K x 8-Bit) Dual-Port RAM
CMOS DUAL-PORT RAM
32K (4K x a-BIT)
WITH SEMAPHORE
Intesrated Device1echnoIogy.Inc.
lOT 713425
lOT 71342L
DESCRIPTION:
FEATURES:
The IDT71342 is an extremely high-speed 4K x 8 dual-port static
• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 35/45/55/70ns (max.)
• Low-power operation
- IDT71342S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT71342L
Active: 500mW (typ.)
Standby: 1mW (typ.)
RAM with full on-chip hardware support of semaphore signalling
between the two ports.
.
The IDT71342 provides two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in memory. To
assist in arbitrating between ports, a fully independent semaphore
logic block is provided. This block contains unassigned flags
which can be accessed by either side; however, only one side can
control the flag at a!:!Y.!Lme. An automatic power down feature, controlled by CE and SEM, permits the on-chip circuitry of each port
to enter a very low standby power mode (both CE and SEM high).
Fabricated using IDT's CEMOS ™ high-performance technology this device typically operates on only 500mW of power at maximum access times as fast as 35ns. Low-power (L) versions offer
battery backup data retention capability, with each port typically
consuming 200j.lW from a 2V battery. The device is packaged in
either a hermetic 52-pin lead less chip carrier or a 52-pin PLCC.
The IDT71342 military devices are manufactured in compliance
with the latest revision of MIL-STD-883, Class B.
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation - 2V data retention
• TIL-compatible; single+5V(±10%) power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
--.-.
g--
\
LV
1/0 0L-1/0 7L
-
...
~ ~
COLUMN
1/0
~ COLUMN
I/O
~
MEMORY
ARRAY
~
~
SEMAPHORE
LOGIC
~
...
-
~
-
-
-...
-
~
RIGHT SIDE
ADDRESS
DECODE
LOGIC
r
~
1-
-
LEFT SIDE
ADDRESS
DECODE
LOGIC
~
-
~
AOR - A11R
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-1035/1
1989 Integrated Device Technology. Inc.
S5-87
5
1OT71342S AND IOT71342L CMOS
DUAL-PORT RAM 32K (4K X a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
INDEX
OE R
44;:
431:
421:
41t
40 I:
39 I:
38 C
37 C
361:
35 C
J52-1
&
L52-1
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ABR
A9R
NC
!10 7R
LCC/PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
lOUT
CAPACITANCE
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
o to
-55 to +125
°C
-55 to +125
-65 to + 135
°C
-55 to +125
-65 to + 150
°C
Power Dissipation
1.5
1.5
W
DC Output Current
50
50
mA
+70
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
SYMBOL
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS
MAX.
UNIT
VIN = OV
11
pF
VOUT= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not production tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Military
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V
O°Cto +70°C
OV
5.0V
Vee
± 10%
± 10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
Vce
GND
MIN.
TYP.
MAX.
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
. Supply Voltage
0
0
0
V
-
6.0
V
0.8
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5(1)
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
S5-88
UNIT
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(VCC = 5.0V ±10%)
SYMBOL
10L = 6mA
-
10L = 8mA
-
IOH= -4mA
2.4
IILlI
Input Leakage Current
Vee = 5.5V, ~N = OV to Vee
IILol
Output Leakage Current
CE = ~H' VOLrr
VOL
Output Low Voltage
VOH
Output High Voltage
IDT71342S
MIN.
MAX.
TEST CONDITIONS
PARAMETER
= OV to
Vee
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
Icc
lee1
ISB1
ISB2
ISB3
ISB4
PARAMETER
TEST CONDITION
VERSION
Dynamic Operating
Current (Both Ports
Active)
CE = V1L
Qillputs Open
SEM = Don't Care
f = f MAX (3)
Dynamic Operating
Current
(Semaphores
Both Sides)
CE =~H
SEM =~L
Outputs Open
f = f MAX (3)
Standby Current
(Both Ports - TTL
Level Inputs)
MIL.
CE L = CER~~H
SEM L = SEM R ~~H
COM'L
f = f MAX (3)
Standby Current
(One Port- TTL
Level Inputs)
CE L or CE R ~ V1H MIL.
Active Port Outputs
Open, f = fMAX (3)
SEM L =SEMR ~ ~H COM'L
Full Standby Current
(Both PortsAll CMOS Level
Inputs)
MIL.
COM'L
S
L
S
L
MIL.
S
L
COM'L
S
L
S
L
S
L
S
L
IDT71342L
MIN.
MAX.
10
-
5
JlA
10
-
5
JlA
0.4
0.4
0.5
-
-
2.4
-
.~. : :~:~:'~: ~;4.?: :;
V
0.5
V
(1) (Vee = 5.0V ±10%)
IDT71342x35(4) IDT71342x45
IDT71342x55
TYpF) MAX. TYP.(2)
MAX. TYP.(2)
MAX.
-
UNIT
IDT71342x70
TYP.(2)
MAX•
100 .:.... 2
100 ::;:;;LA~~g,:
100
100
100
100
240
200
200
160
100
100
100
100
230
180
200
160
100
100
100
100
230
180
200
160
= ~: : : :~:,:,: : ·k;.:.,:
85
·85
130
110
85
85
130
110
85
85
130
110
85M::::::::~:::~:~~'
85
85
85
130
100
85
85
130
100
85
85
130
100
=;\~\'~!dA:':
j~-
t:::m::~::::~::~~~
~~
~~.
~~
~g
~g
70
40
160
130
25
25
50
50
70
40
150
120
25
25
50
50
70
40
150
120
S
L
=/"~'{\I~:m;
~~~
25
25
50
50
50
50
130
100
50
50
130
100
50
50
130
100
Both Ports CE Land
MIL.
CE R ~ Vee -0.2V
~N ~ Vee -0.2V or
~N :5 0.2V
SEM L = SEM R ~ COM'L
Vee -0.2V, f = 0(3)
S
L
',,;:.:::. ::."::.:.::;:;"2
..,.,.':':':'::::::::;
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
One Port CE L or
MIL.
CE R ~ Vee -0.2V
Full Standby Current ~N ~ Vee -0.2V or
(One Port-All CMOS
~N :5 0.2V,
Level Inputs)
Active Port Outputs COM'L
Open, f = f MAX (3)
S
L
50
45
130
100
50
45
120
90
50
45
120
90
45
45
110
90
45
45
110
90
45
45
110
90
25
25
iiliZ
. .;'::;:;:;:;:;::::::.:.:<
.~.:::::::·::·::::::::::::::4v
:):mL}~:
mA
mA
mA
mA
::::
S
L
UNIT
.,)
r
mA
.:-:::::::::::::;:::,,;
S
L
1 :1: ;:;~:l l~·~.·:·:~: : :=
4g~~:
4s
:Ii:·: :;:;,:;:;:~ g
rnA
NOTES:
1. ·x· in part numbers indicates power rating (S or L).
2.
3.
4.
Vee = 5V, TA = +25°C
fMAX = 1It Re = All inputs cycling atf = 1It Rc(exeept Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby,lsB3 ·
O°C to + 70°C temperature range only.
S5-89
....••- - - - - -..
- - - - - - - - - - - - - - - _ . -----------------_.
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(L Version Only) VLC = 0.2V, VHC
SYMBOL
VDR
ICCDR
= Vcc -
0.2V
TEST CONDITION
PARAMETER
Vcc = 2V
CS ~VHC
\'IN ~ VHC ors VLC
Data Retention Current
t CDR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
TYP!')
MIN.
-
Vcc for Data Retention
I
I
MIL.
COM'L.
-
-
100
4000
100
1SOO
0
-
-
ns
t RC (2)
-
-
ns
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
GNDto 3.0V
Sns
1.SV
1.SV
See Figures 1 & 2
SV
DATAoUT
~
77S!l
SV
12S0n
DATA OUT
30pF*
~
775!l
Figure 1. Output Load
12S0n
SpF*
Figure 2. Output Load
(for tLZ,tHz, twz,t ow )
* Including scope and jig.
S5-90
UNIT
-
NOTES:
1. Vcc = 2V, TA = +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference LevelS
Output Load
MAX.
2.0
V
J..l.A
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
1DT71342S35 (5)
IDT71342L35 (5)
MIN.
MAX.
PARAMETER
SYMBOL
IDT71342S45
1DT71342L45
MIN.
MAX.
'IDT71342S55
IDT71342L55
MIN.
MAX.
IDT71342S70
IDT71342L70
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
35
45
-
55
-
70
-
tAA
Address Access Time
-
::?~&.:::::
-
45
55
ns
Chip Enable Access Time (3)
. .:.::~s:::
-
45
55
70
ns
Output Enable Access Time
-
25
-
30
-
70
tACE
t AoE
-
40
ns
tOH
Output Hold From Address Change
5
5
-
5
-
ns
tLZ
Output Low Z Time (1.2)
5
. }:::::~:::::::I
5
-
5
-
5
-
ns
tHZ
Output High Z Time (1.2)
-
{::;):{::20
-
25
-
30
-
40
ns
tpu
Chip Enable to Power Up Time (2)
0
tpD
Chip DIsable to Power Down TIme (2)
-
tsop
SEM Flag update Pulse (at: or SE1Vf)
twoo
tO~~
:}b:::::::.
: : :. <:20'
:::::){~:
5
.......:.;.::::::::;:
,::::::;::::;
ns
:;:;'-
0
-
0
-
0
-
ns
i:>::::::::::::;: 50
-
50
-
50
-
50
ns
15.:::::::;:;::::::: -
15·
-
20
-
20
-
ns
Write Pulse to Data Delay (4)
-.:::::::::i(;i:i: 60'
-
70
-
80
90
ns
Write Data Valid to Read Data Delay(4)
-,:\:}:::::::::
-
45
-
55
-
70
ns
35
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM. CE = "'L' SEM = "'H' To access semaphore, CE = "'H' SEM = V1L•
4. Port to Port delay through RAM cells from writing port to a reading port.
5. O°C to + 70°C temperature range only.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
(1,2,4)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
(1,3)
--r.----- tAcE-----l-.j
CE or
gm(5)
+-----.l~--
t AoE
tLZ~
1~----tLZ---~
Icc
CURRENT
;L
~~~r---~----------~
DATA OUT
__
tPU--fJ-::L _ _
- _ t p o~
------J....
50%
Iss
NOTES:
1. RNi is high for Read Cycles.
2. Device is continuously enabled, CE =
This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = V1L
5. To access RAM, CE = "'L' SEM = "'H' To access' semaphore, CE = \1H' SEM = V1L•
50%
"'L'
~5-91
. _ - - - - - - - - - - - - - - - - - - _ . _ - - - - - - - _ . _ - - - - - - - - - - - - - _...•... - ...- .. -.---
IDT71342S AND IDT71342L CMOS
DUAL-PORT ,RAM 32K (4K x S-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY
(1,2)
twc
ADDRR
'If
J~
'I
MATCH
J\
twp
RiWR
1
J,
\
J
.J tOH
tow
J'{.
DATAIN R
J~
t
VALID
I
MATCH
ADDRL
twoo
jt
DATAoUT L
J\
tO~~
NOTES:
1. Write Cycle parameters should be adhered to, to ensure the proper writing.
2. Device is continously enabled for both ports.
55-92
VALID
IDT71342S AND 1DT71342L CMOS
DUAL-PORT RAM 32K (4K X S-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
IDT71342S35 (5)
IDT71342L35 (5)
MIN.
MAX.
IDT71342S45
IDT71342L45
MIN.
MAX.
IDT71342S55
IDT71342L55
MIN.
MAX.
IDT71342S70
IDT71342L70
MIN.
MAX.
UNIT
WRITE CYCLE
tEW
Write Cycle Time
45
55
70
Chip Enable to End of Write (3)
40
50
60
ns
Address Valid to End of Write
40
50
60
ns
ns
Address Set-up Time
o
o
o
ns
Write Pulse Width
40
50
60
ns
Write Recoverv Time
o
o
o
ns
20
25
30
ns .
Data Valid to End of Write
Output High Z Time(1.2)
20
Data Hold Time (4)
3
25
3
20
Write Enable to Output in
High Z(1·2)
30
ns
30
ns
3
25
ns
Output Active From End of Write (1.2,4)
3
3
3
ns
SEM Flag Write to Read Time
10
10
10
ns
SEM Flag Contention Window
10
10
10
ns
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM, CE = '-'iL' SEM = '-'iH' To access semaphore, CE = "IH' SEM = V1L. This condition must be valid for entire tEWtime.
4. The specification for t DH must be met by the device supplying write data to the RAM under alii operating conditions. Although tDH and tDH values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tow.
5. O°C to + 70°C temperature range only.
S5-93
._-_... _-_..__....
__
.......
_-------------
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
twc
ADDRESS
~
~
<
)K
t
(6)_
HZ
/V
CEor
SEM (8)
RiW
~
,
tAW
/V
_ t AS
t
(7)
tWR
Wp
/~
",,-
-
~twt)tow
DATA OUT
(4)
./,:
_tow
DATA IN
t OH
(4)::)<~ ~
-
./
"
"
./
, TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING(1,2,3,5)
~...............- -.....- -.....- -..........--twc--------""'--""'------""'~
ADDRESS
CEor
SEM (8)
--~+-----.....-------tEW--------""'--~
RiW
DATA IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
RNi must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low Ci: or srIVl' and a low Rfill.
tWR is measured from the earlier of cr or R/'W (or SEM or Rfill) going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE or SEM low transition occurs simultaneously with or after t~e RNi low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RNi controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tow. If OE" is high during an RfiJ controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP .
8. To access RAM, CE = 'v'IL' SEM = 'v'IH. To access semaphore, CE = 'v'IH' SEM = VIL • Either condition must be valid for the entire tEW time.
S5-94
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . -..- _
.•.
IDT71342S AND IDT71342L CMOS
DUAL·PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
.•.•..-.
__.. _
.......
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
(1)
DATA a
RiW
1 4 - - - - - Write Cycle
-----.j----
Test Cycle
(Read Cycle)
NOTE:
1. CE = V1H for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION
(1,3,4)
A OA - A2A
SIDE (2) "A"
RIWA
SEM A
MATCH
ft~,
X
A OB - A2B
SIDE (2) "S"
RIWB
SEM B
NOTES:
1. DOR = DOL = V1l , CE R = CE l = V1H , semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. Either side "A" = left and side "S" =right, or side "A" = right and side "S" = left.
3. This parameter is measured from the point where RNiA or SEM A goes high until RNi B or SEM B goes high.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
S5-95
1DT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The eight semaphore flags reside within the IDT71342 in a
separate memory space from the dual-port RAM. This address
space is accessed by placing a low input on the SEM pin (which
acts as a chip select for the semaQbore flags) and using the other
control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins
Ao - A2. When accessing the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do Is used. If a low
level is written into an unused semaphore location, that flag will be
set to a zero on that side and a one on the other (see Table II). That
semaphore can now only be modified by the side showing the
zero. When a one Is written into the same location from the same
side, the flag will be set to a one for both sides (unless a semaphore
request from the other side is pending) and then can be written to
by both sides. The fact that the side which is able to write a zero into
a semaphore subsequently locks out writes from the other side is
what makes semaphore flags useful In interprocessor communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side
will be stored in the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data
bits so that a flag that is a one reads as a one in all data bits and a
flag containing a zero reads as all zeros. The read value is latched
Into one side's output register when that side's semaphore select
(SEM) and output enable (OE) signals go active. This serves to
~isallow the semaphore from changing state In the middle of a read
cycle due to a write cycle from the other side. Because of this latch,
a repeated read..2!. a semaphore in a test loop must cause either
signal (SEM or OE) to go inactive orthe output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to
write a zero into a semaphore location. If the semaphore is already
in use, the semaphore request latch will contain a zero, yet the
semaphore flag will appear as a one, a fact which the processor will
verify by the subsequent read (see Table II). As an example, assume a processor writes a zero to the left port at a free semaphore
location. On a subsequent read, the processor will verify that it has
written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will fail,
as will be verified by the fact that a one will be read from that semaphore on the right side during a subsequent read. Had a sequence
of READ/WRITE been used Instead, system contention problems
could have occurred during the gap between the read and write cycles.
It is important to note that'a failed semaphore request must be
followed by either repeated reads or by writing a one Into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 3. Two semaphore request latches feed into a semaphore flag. Whichever latch
is first to present a zero to the semaphore flag will force its side of
the semaphore flag low and the other side high. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side's semaphore request latch have been written
to a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one Is written Into the first side's request
latch. The second side's flag will now stay low until its semaphore
request latch is written to a one. From this it is easy to understand
that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can
hang up until a one is written into that semaphore request latch.
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast dual-port 4K x 8 CMOS static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or
right side of the,dual-port RAM to claim a privilege over the other
processor for functions defined by the system designer's software.
As an example, the semaphore can be used by one processor to
Inhibit the other from accessing a portion of the dual-port RAM or
any other shared resource.
The dual-port RAM features a fast access time, and both ports
are completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right
port. Both ports are identical in function to standard CMOS static
RAMs and can be read from, or written to, at the same time with the
only possible conflict arising from the simultaneous writing of, or a
simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the nonsemaphore portion of the dual-port RAM. These devices have an
automatic power-down feature controlled by CE, the dua!:E2!:!
RAM enable, and SEM, the semaphore enable. TheCEand SEM
pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the
condition which Is shown in Table I where CEand SEM are both
high.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed systems which are software controlled or software Intensive. These
systems can benefit from a performance increase offered by the
IDT71342's hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
Software handshaking between processors offers the maximum
in system flexibility by permitting shared resources to be allocated
in varying configurations. The IDT71342 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility In system architecture.
An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never
incurred in either processor. This can prove to be a major advantage in very high-speed systems.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are independent ofthe dual-port RAM. These latches can be used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphores provide a hardware assist for a
use assignment method called "Token Passing Allocation." In this
method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to
use this resource, it requests the token by setting the latch. This
processor then verifies its success In setting the latch by reading it.
If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch,it determines
that the right side processor had 'set the latch first, has the token
and is using the shared resource. The left processor can then either
repeatedly request that semaphore's status or remove its request
for that semaphore to perform another task and occasionally
attempt again to gain control of the token via the set and test
sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active low. A token is requested by
writing a zero into a semaphore latch and is released when the
same side writes a one to that latch.
S5-96
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K X S-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 1- NON·CONTENTION READ/WRITE CONTROL
LEFT OR RIGHT PORT (1)
FUNCTION
DO~7
R/W
CE
SEM
OE
X
H
H
X
Z
H
H
L
L
DATA OUT
X
X
X
H
Z
...J
H
L
X
Port Disabled and in Power Down
Mode
Data in Semaphore Flag
Output on Port
Output Disabled
DATA IN
Port Data Bit Do Written Into
Semaphore Flag
H
L
H
L
DATA OUT
Data In Memory Output on Port
L
L
H
X
DATA IN
Data On Port Written. Into Memory
X
L
L
X
-
Not Allowed
NOTE:
1. AOL - A 10L t- AOR - A 10R
H = HIGH. L = LOW. X = DON'T CARE. Z
= Low-to-High transition
...J
= HIGH IMPEDANCE
TABLE II-EXAMPLE SEMAPHORE·PROCUREMENT SEQUENCE
FUNCTION
Do - 0 7 LEFT
STATUS
Do - 07 RIGHT
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
No change. Right side has no write
access to semaphore
Right Port Writes "0" to Semaphore
0
1
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
No change. Left port has no write
access to semaphore
Left Port Writes "0" to Semaphore
1
0
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
S5-97
IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Ing a zero 'into Semaphore 1. If it succeeded in gaining control, it
would lock out the left side.
Once the left side was finished with its task, it would write a one
to Semaphore 0 and may then try to gain access to Semaphore 1.lf
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was
able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would
allow the two processors to swap 2K blocks of dual-port RAM with
each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
dual-port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait
states. With the use of semaphores, once the two devices had determined which memory area was "off limits" to the CPU, both the
CPU and the I/O devices could access their assigned portions of
memory continuously without any wait states.
Semaphores are also useful in application~ where no memory
"WAIT" state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In
this case, block arbitration is very important. For this application
one processor may be responsible for building and updating a
data structure. The other processor then reads and interprets that
data structure. If the interpreting processor reads an incomplete
data structure, a major error condition may exiSt. Therefore, some
sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and
then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data
structure, thereby guaranteeing a consistent data structure.
The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same
time. The semaphore logic is specially designed to resolve this
problem. If simultaneous requests are made, the logic guarantees
that only one side receives the token. If one side is earlier than the
other in making the request, the first side to make the request will
receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other.
One caution that should be noted when using semaphores Is
that semaphores alone do not guarantee that access to a resource
is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily
happen. Code integrity is of the utmost importance when semaphores are used instead of slower, more restrictive hardware intensive schemes.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power up. Since any
semaphore request flag which contains a zero must be reset to a
one, all semaphores on both sides should have a one written into
them at initialization from both sides to assure that they will be free
when needed.
USING SEMAPHORES - Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT71342's dual-port RAM. Say
the 4K x 8 RAM was to be divided into two 2K x 8 blocks which were
to be dedicated at anyone time to servicing either the left or right
port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be
defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 2K of dual-port
RAM, the processor on the left port could write and then read a zero
Into Semaphore O. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 2K. Meanwhile, the right processor would attempt to perform the same function. Since this processor was attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore O. At this pOint, the software could choose to
try and gain control of the second 2K section by writing, then read-
LPORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
Do - - - - 1 D
WRITE
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D 1 - - - - Do
--~
WRITE
SEMAP~~~6 ~~------~----~
SEMAPHORE
READ
SEMAPHORE LATCH
FIGURE 3. IDT71342 Semaphore Logic
S5-98
10171342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
A
999
A
A
Device Type
Power
Speed
Package
Process/
Temperature
~y:'Mk
J
L52
PLCC
LCC
Commercial onlY}
L
Low Power
Standard Power
71342
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
35
45
55
70
S
S5-99
Commercial (O°C to
Speed in Nanoseconds
. 32K (4K x a-Bit) Dual-Port RAM w/Semaphore
~
IntesratedDevIce~Inc.
ADVANCE
INFORMATION
lOT 7024
HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70/90ns (max.)
- Commercial: 30/35/45/55/70/90ns (max.)
• Low-power operation
-IDT7024S
Active: ---mW (typ.)
Standby: --mW (typ.)
-IDT7024L
Active: ---mW (typ.)
Standby: ---mW (typ.)
• Separate upper-byte and lower-byte control for multiplexed
bus compatibility.
• IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave chip select when cascading more
than one device
• On-chip port arbitration logic
• Versatile pin-select for Master or Slave:
MiS = H for BUSY output flag on Master
MiS = L for BUSY input on Slave
The IDT7024Is a high-speed 4K x 16 dual-port static RAM. The
IDT7024 is designed to be used as a stand-alone 64K-bit dual-port
RAM or as a combination MASTER/SLAVE dual-port RAM for
32-bit-or-more word width systems. Using the IDT MASTER/
SLAVE dual-port RAM approach in 32 bit or wider memory system
applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 30ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---~W from a 2V battery.
The IDT7024 is packaged in plastic as well as ceramic 84-pin
PGA and 84-pin quad flatpack. The military devices are processed
100% in compliance to the test methods of M IL-STD-883, method
5004.
• INT flag for port-ta-port communication
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asychronous operation from either port
• Battery backup operation-2V data retention
• TIL compatible, single 5V (±10%) power supply
• Available in 84-pin PGA
FUNCTIONAL BLOCK DIAGRAM
R/WL ~t==::::g~
U£3 L
A
llL
A10L
====+::j::::;-'
r.=t:::::t:===
'IIOBL -1I015L
1I0oL-I/07l - - - + - - 1
lIDSY'L(l) -..,_ _ _ _ _ _--1
A9L
AOL
A11R
AlaR
I/OBR -
r--~--.,
-r--:--.....
. . -------t--
lID 15R
I/00R -lID 7R
lIDSY'R(l)
A9R
-+-=--.....
AOR
R/W L
~L
NOTES:
fIi1T L
1. (MASTER): lIDSY' is output; (SLAVE): lIDSY' is input.
2. LB = Lower Byte.
UB = Upper Byte.
CEMOS is a trademark of Integrated Device TechnologY,lnc.
MIS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated ~evice Technology. Inc.
JANUARY 1989
05C-1045/-
S5-100
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7024 HIGH-SPEED 4Kx 16 DUAL-PORT STATIC RAM
PIN NAMES
LEFT PORT RIGHT PORT
NAMES
60
58
51
55
63
61
54
1/0 7l 1I0Sl 1/04l 1/0 2l 1I00l "O"E'l ~L
D3 l
46
Alll
45
A 10l
42
A1L
10
59
49
62
66
64
56
1/010L 1I0 8l 1/0 6l 1I0 3l 1I0 ll TIS"l
CE"l
47
NC
44
A9l
43
A8l
40
ASl
09
65
67
110 m I/0Sl
S2
Rflh
41
A6l
39
A4l
08
69
68
1I0 13L 1I0 12L
38
A3l
37
A2l
07
73
72
71
I/o,SL 1I0 14L Vee
Chip Enable
CE"R
CE"l
11
RflVl
RflVR
Read/Write Enable
OE: L
~R
Output Enable
AOl-lll
AOR-llR
Address
1/0 0L-15l
1/0 0R-1SR
Data Input/Output
~L
OBL
~R
ffi3R
Upper Bit Select
LBL
03R
Lower Bit Select
Tf\JTl
lNTR
Interrupt Flag
troS'7l
~R
Busy Flag
Semaphore Enable
S7
GND
33
Vee
Power
GND
Ground
04
MiS
Master or Slave
Select
03
14
82
1
2
S
8
10
I/0 eR 1/0 9R 1/0 lOR 1/0 13R 1/01SR R/WR UB"R
17
20
02
AllR
01
4
84
3
6
9
I/0eR I/0llR 1/0 12R 1/014R "O"E'R
16
NC
05
70
74
GND GND
77
1/02R
80
1/04R
INPUTS
CE:
R/W
OE
H
X
X
DB
11
7
GND GND
83
1/0 7R
B
C
$EM I/O a - 1/0 15
D
L
L
X
X
X
X
X
L
L
H
DATAIN
DATAIN
L
H
L
L
H
H
DATA OUT
Hi-Z
Read Upper Byte Only
L
H
L
H
L
H
Hi-Z
DATA OUT
Read Lower Byte Only
L
H
L
L
L
H
DATAoUT
DATAoUT
Read Both Bytes
X
X
H
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
L
L
L
X
X
H
Hi-Z
Hi-Z
Deselected: Power Down
H
H
H
Hi-Z
Hi-Z
Deselected: Power Down
L
H
H
DATA IN
Hi-Z
Write to Upper Byte Only
H
L
H
Hi-Z
DATA IN
Write to Lower Byte Only
Write to Both Bytes
H
H
L
X
X
L
DATA OUT
DATA OUT
X
H
L
H
H
L
DATA OUT
DATAoUT
Read Data in Sema. Flag
X
X
X
X
X
X
L
DATA IN
DATA IN
Write DINO into Sema. Flag
H
H
L
DATA IN
DATA IN
Write DINO into Sema. Flag
L
X
L
-
Not Allowed
L
L
-
-
Not Allowed
H
X
L
S
S
X
X
L
X
Note:
1. AOL - A13R -4 A OR - A 13R
31
M~
15
13
30
~
27
A1R
23
ASR
2S
A3R
A8R
22
AeR
24
A4R
18
Al0R
19
ASR
21
A7R
12
D3R CE"R
36
All
26
A2R
S'm R
E
F
G
84-PIN PGA
TOP VIEW
MODE
1/00 -1/0 7
35
34
AOl Tf\JTl
28
29
AOR lNTR
OUTPUTS
m
32
GND
78
Vee
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
L
~
7024
4Kx16DPR
IN 84-PIN PGA
75
I/OOR
76
1/01R
79
1/03R
81
I/OSR
06
A
X
53
Vee
50
48
H
K
L
Note:
1. All Vce pins have to be connected to
power supply.
2. All GND pins have to be connected
ground supply.
Read Data in Sema. Flag
TRUTH TABLE: ARBITRATION OPTIONS
OPTIONS
INPUTS
OUTPUTS
LB M/S SEiVi BUSY 1Nf
X
L
Output
H
H
L
X
Signal
H
H
CE
L
L
DB
Busy Logic Slave
L
L
X
L
L
X
Interrupt Logie
L
L
X
L
L
Semaphore Logic*
H
H
X
X
Busy Logic Master
L
L
H
H
Input
Signal
-
X
X
X
H
H
-
Output
Signal
X
X
H
L
L
L
H
Hi-Z
-
*Inputs Signals are for Semaphore Flags set and test (Write and Read)
operations
S5-101
,-"--,,,,,--
---------
IDT7024 HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXX)(
Device Type
A
Power
999
A
A
Speed
Package
Process!
Temperature
Range
Y:,onk
L...-_ _ _ _ _ _ __j
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-8TD-883, Method 5004, Class B
PG
G
84-pin Plastic PGA Commercial Only
84-pin PGA
30
35
45
Commercial onlY}
Commercial Only
Speed in Nanoseconds
~----------------------~55
70
90
~
_______________________________jS
L
~--------------------------------------~7024
S5-102
Standard Power
Low Power
64K (4K x 16) Dual-Port RAM
-
._---------...- - - - - - - - - - - - - - - - - - - - - - - - - - - -
t;)
Integrated DevicelechnoIogy,Inc.
ADVANCE
INFORMATION
.IDT 7005
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70/90/100/120ns (max.)
- Commercial: 35/45/55/70/90/100ns (max.)
• Low-power operation
-IDT7005S
Active: ---mW (typ.)
Standby: -:---mW (typ.)
-IDT7005L
Active: ---mW (typ.)
Standby: ---mW (typ.)
• IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave chip select when cascading more
than one device
The IDT7005 is a high-speed 8K x 8 dual-port static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit dual-port
RAM or as a combination MASTER/SLAVE dual-port RAM for
16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE dual-port RAM approach In 16-bit or wider memory system
applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 35ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---jJW from a 2V battery.
The IDT7005 is packaged in plastic as well as ceramic 68-pin
PGA, 68-pin PLCC, and 68-pin LCC. The military devices are processed 100% in compliance to the test methods of MIL-STD-883,
method 5004.
• On-chip port arbitration logic
• Versatile pin-select for Master or Slave
MiS = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• TNT flag for port-to-port communication
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asychronous operation from either port
• Battery backup operation - 2V data retention
• TTL compatible, Single 5V (±10%) power supply
• Available in 68-pin PGA
FUNCTIONAL BLOCK DIAGRAM
R~l --~-------1r1~----~
~l=====!=~)---~
~l
1I07R
1I0ol
(l)BOS'?l
110 OR
--.,-----------------1
BOSYR(l)
A9l --/------+1
AOl --/-------+1
A9R
AOR
-----.r====~-___::,..._-- A12R
----=-----tf ARBITRATION
AOR
cr
INTERRUPT
......
A'2l
AOl
DE: ~ -------01 SE~~~gRE
~~
R~l
R~R
NOTE:
MIS
1. (MASTER~8~~Y is output.
(SLAVE):
is input.
CEMOS is a trademark of Integrated Device Technology,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
OSC-1043/-
55-103
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7005 HIGH-SPEED 8K ic 8 DUAL-PORT STATIC RAM
PIN NAMES
11
NAMES
LEFT PORT RIGHT PORT
~L
CE"R
Chip Enable
R/WL
Read/Write Enable
ITE"L
R/WR
ITE"R
Output Enable
AOL-12L
AOR-12R
Address
1/0 0L-7L
IIOoR-7R
Data Input/Output.
~L
~R
Semaphore Enable
mTL
mTR
Interrupt Flag
mmYL
lffiS?R
Busy Flag
MIS
Master or Slave
Select
Vcc
Power
GND
Ground
52
A6L
09
55
A9L
54
A8L
32
A7R
33
A6R
56
57
A llL Al0L
30
08
A9R
31
ABR
07
59
Vcc
06
61
NC
05
~L
63
OUTPUTS
MODE
H
X
X
H
HI-Z
H
H
L
L
DATA OUT
X
.X'
H
X
Hi-Z
H
.s
X
L
DATA IN
L
H
L
H
DATA OUT
Read Memory
L
L
X
H
DATA IN
Write to Memory
L
X
X
L
-
Deselected: Power Down
26
27
GND A12R
62
CE"L
24
NC
Read Data in Sema. Flag
Write DINO into Sema. Flag
NotAlIowed
OUTPUTS
SE1V'r
BU'S'Y
1m
-
Busy Logic Master
L
H
H
Output
Signal
Busy Logic Slave
L
L
H
Input
Signal
-
Interrupt Logic
L
X
H
-
Output
Signal
Semaphore Logic·
H
H
H
L
L
L
H
Hi-Z
-
25
NC
23
22
~F ~R
21
20
ITE"R R/WR
18
19
13
15
\6c 1I04 R 1I0 7R NC
C
D
E
F
G
H
J
Note:
1. All Vco pins have to be connected to power supply.
2. Ali GND pins have to be connected to ground supply.
TRUTH TABLE: ARBITRATION OPTIONS
MIS
60
NC
B
Outputs Disabled
INPUTS
7005
8Kx8 DPR
IN 68-PIN PGA
68
1
3
9
5
7
11
1I0 1L 1I0 2L II04L GND 1I07L GND 1I0 1R
4
10
2
6
8
12
14
16
17
1I0 3L 1/0 5L 1I06L Vee 1/00R 1/0 2R 1/0 3R 1/0 5R 1I0 6R
Note:
1. AOL - Am ~ AOR - A12R
CE
28
29
AllR A 10R
58
A12L
68-PIN PGA
TOP VIEW
R/W
OPTIONS
~
65
64
DEL R/W L
67
66
1I00L NC
A
TRUTH TABLE: NON·CONTENTION
READ/WRITE CONTROL
CE
38
A3R
34
ASR
04
1/00 -1/0 7
40
48
44
42
38
AOL ~ M~ mTR A1R
. 39
47
45
43
37
A2R
AOR
AlL mTL GND
48
A2L
35
A4R
01
(1)
49
A3L
53
A7L
02
01: SE1\ir
50
A4L
10
03
INPUTS
51
A5L
-
• Inputs Signals are for Semaphore Flags set and test (Wnte and Read)
operations
S5-104
K
L
- - . - - - _ .. _ - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7005 HIGH-SPEED 8Kx 8 DUAL-PORT STATIC RAM
ORDERING INFORMATION
IDT
XXXX
Device Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
Range
y:rank
~__________~IPG
IG
35
45
55
~-------------1 70
90
100
120
~
______________________
~Is
IL
L--_ _ _ _ _ _ _ _ _ _ _ _,.--_ _ _ _ _
~
7005
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, MethOd 5004, Class 8
68-pin Plastic PGA Commercial Only
68-pin PGA
Commercial onlY)
Speed In Nanoseconds
Military Only
Standard Power
Low Power
64K (8K x 8) Dual-Port RAM
S5-105
--------------_._..._---------_ .._ - - - - - - - - - - - -
ADVANCE
INFORMATION
lOT 7025
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
.t;)
Integrated Dev1ce1echnology.1nc.
FEATURES:
• Fully asychronous operation from either port
• Battery backup operatlon-2V data retention
• High-speed access
- Military: 45/55/70/90ns (max.) .
• TTL compatible, single 5V (±10%) power supply
• Available in 84-pin PGA
- Commercial: 30/35/45/55/70/90ns (max.)
• Low-power operation
-IDT7025S
Active: ---mW (typ.)
DESCRIPTION:
The IDT7025 is a high-speed 8K x 16 dual-port static RAM. The
IDT7025 is designed to be used as a stand-alone 128K-bit dualport RAM or as a combination MASTER/SLAVE dual-port RAM for
32-bit-or-more word systems. Using the IDT MASTER/SLAVE
dual-port RAM approach in 32 bit or wider memory system applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate contrOl, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power. mode.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 30ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---jJW from a 2V battery.
The IDT7025 is packaged in plastic as well as ceramic 84-pin
PGA and 84-pin quad flatpack. The military devices are processed
100% in compliance to the test methods of M IL-STD-883, method
5004.
Standby: --mW (typ.)
-IDT7025L
Active: ---mW (typ.)
Standby: ---mW (typ.)
• Separate upper-byte and lower-byte control for multiplexed
bus compatibility
• IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave chip select when cascading more
than one device
• On-chip port arbitration logic
• Versatile Pin-Select for Master or Slave:
MIS = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• INT flag for port-to-port communication
• Full on-chip hardware support of semaphore signaling
between ports
FUNCTIONAL BLOCK DIAGRAM
RmL~~===r~
lffi"L -
A 12L
A'0L
____~
=~c:::j::t:::;l
r-;:::t::t=:::!==
I
I
1I0aL -1I0'5L
A'0R
I/OsR-1/0'5R
1I0oL-1I07L ---+----1
SDSYL~----------~ r--~;""'.,
A9L
AOL
A 12R
-+----....
-+---=---....
I/00R - 1/07R
~R(I)
1+----,,-+- A 9R
1+----:;-+- A OR
L..-----------r--
NOTES:
1. (MASTER): l3lJSY is output. (SLAVE): BUSY is input.
2. LB = Lower Byte.
UB = Upper Byte.
CEMOS is a trademark of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-l046/-
1989 Integrated Device Technology. Inc.
55-106
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IDT7025 HIGH-SPEED 8Kx 16 DUAL-PORT STATIC RAM
PIN NAMES
LEFT PORT RIGHT PORT
NAMES
11
48
1/0 7l 1/0 5l 1/04l 1/02l 1/00l rn=l SEM l
rn l
46
Alll
45
AlOl
42
A7L
10
66
64
62
59
56
I/0lOl 1/0 8l 1/0 6l 1/0 3l I/0 ll
47
A12l
44
A9l
43
A8l
40
A5l
09
67
65
1/0llL 1/0 9l
41
A6l
39
A4l
08
69
68
1/0 13l 1I0 12L
38
A3l
37
A2l
07
72
71
1/015l 1/0 14l
BOSYL
35
AOl
TNil
32
GND
31
M.5
36
All
28
AOR
TNiR
crl
CE R
Chip Enable
RiW l
RfiJR
Read/Write Enable
rn=l
C51:: R
Output Enable
AOl-12l
AOR-12R
Address
I/OOl-15l
I/OOR-15R
Data InpuVOutput
S8J L
SEM R
Semaphore Enable
OBL
DBR
Upper Bit Select
03 L
LBR
Lower Bit Select
TfJTl
INTR
Interrupt Flag
BUSYl
BUSYR
Busy Flag
05
Master or Slave
Select
04
Mis
Vee
Power
GND
Ground
06
63
61
60
58
55
57
GND
22
A6R
24
A4R
01
3
84
4
6
9
1/08R 1/0 llR 1/0 12R 1/014R rn=R
16
A12R
18
AlOR
19
A9R
21
A7R
D
X
X
X
X
X
H
H
L
L
X
L
H
Hi-Z'
Write to Upper Byte Only
L
L
X
H
L
H
Hi-Z
DATA IN
Write to Lower Byte Only
Write to Both Bytes
Hi-Z
1/°0- 1/°7
Hi-Z
H
Hi-Z
Hi-Z
H
DATAIN
L
L
X
L
L
H
DATA IN
DATAIN
L
H
L
L
H
H
Hi-Z
L
H
L
H
L
H
DATA OUT
Hi-Z
DATA OUT
Read Lower Byte Only
L
H
L
L
L
H
DATA OUT
DATA OUT
Read Both Bytes
X
X
H
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
H
H
L
X
X
L
DATA OUT
DATA OUT
X
H
L
H
H
L
DATA OUT
DATA OUT
Read Data in Sema. Flag
Read Upper Byte Only
Read Data in Sema. Flag
X
X
X
L
DATAIN
DATA IN
Write DINO into Sema. Flag
X
....r
....r
X
H
H
L
DATA IN
DATA IN
Write DINO into Sema. Flag
L
X
X
L
X
L
-
Not Allowed
L
Note:
X
X
X
L
L
-
-
Not Allowed
AOR - A12R
TRUTH TABLE: ARBITRATION OPTIONS
INPUTS
OUTPUTS
[8 MIS SEM BUSY TNT
H
H
Output
X
L
L
H
H
Signal
X
Busy Logie Slave
L
L
X
L
L
X
Interrupt Logic
L
L
X
L
L
X
Semaphore Logic*
H
H
X
X
X
X
L
L
H
H
X
Input
Signal
-
X
H
H
-
Output
Signal
H
L
L
L
H
Hi-Z
-
SE"M R
13
cr R
E
F
G
H
K
L
84-PIN PGA
TOP VIEW
Note:
MODE
1. All Vee pins have to be connected
to power supply.
Deselected: Power Down
2. All GND pins have to be connected
to ground supply.
'
Deselected: Power Down
C
X
Busy Logic Master
25
A3R
20
X
DB
23
A5R
A8R
OUTPUTS
CE
L
L
27
AIR
17
H
OPTIONS
26
A2R
AllR
[8
=f.
30
~
82
1
2
5
8
10
14
1/0 6R 1/09R 1/010R 1/0 13R 1/015R RfiJR DBR
15
[BR
12
29
34
02
B
7
11
GND GND
DB
1. AOl - A12l
52
RfiJ l
81
83
1/05R 1/0 7R
OE
H
53
Vee
03
R/W
H
50
7025
8K X 16 DPR
IN 84-PIN PGA
CE
SEM 1/08 - 1/0 15
49
OB l cr l
33
70
74
75
I/OOR GND GND
76
77
78
I/O IR 1/02R Vee
79
80
1/03R 1/04R
A
(1)
51
73
Vee
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
INPUTS
54
*Inputs Signals are for Semaphore Flags set and test (Write and Read)
operations
S5-107
IDT7025 HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXX><
Oevice Type
A
Power
999
Speed
A
A
Package
Processl
Temperature
Range
Y:,ank
'--_ _ _ _ _ _ _---1
L-._ _ _ _ _ _ _ _ _ _ _~
L-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
S5-108
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Method 5004. Class B
PG
G
84-pin Plastic PGA Commercial Only
84-pin PGA
30
35
45
55
70
90
Commercial onlY}
Commercial Only
S
L
Standard Power
Low Power
7025
128K (8K x 16) Dual-Port RAM
Speed in Nanoseconds
Integrated Device1echnology.lnc.
ADVANCE
INFORMATION
lOT 7006
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 45/55/70/90/100/120ns (max.)
- Commercial: 35/45/55/70/90/100ns (max.)
• Low-power operation
-IDT7006S
Active: ---mW (typ.)
Standby: ---mW (typ.)
-IDT7006L
Active: ---mW (typ.)
Standby: ---mW (typ.)
• IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave chip select when cascading more
than one device
• On-chip port arbitration logic
• Versatile pin-select for Master or Slave:
MiS = H for BUSY output flag on Master
MiS = L for BUSY input on Slave
The IDT7006 is a high-speed 16K x 8 dual-port static RAM. The
·IDT7006 is designed to be used as a stand-alone 128K-bit dualport RAM or as a combination MASTER/SLAVE dual-port RAM for
16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE dual-port RAM approach in 16 bit or wider memory system
applications results in full-speed, error-free operation without the
need for additional discrete logiC.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asychronous
access for reads or writes to any location in memory. An automatic
power down feature controlled by CE permits the on-chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS Tlot high-performance technology, these devices typically operate on only ---mW of power at
maximum access times as fast as 35ns. Low-power (L) versions offer battery backup data retention capability with each port typically
consuming ---JjW from a 2V battery.
The IDT7006 is packaged in plastic as well as ceramic 68-pin
PGA, 68-pin LCC, and 68-pin PLCC. The military devices are processed 100% in compliance to the test methods of MIL-STD-883,
method 5004.
• INT flag for port-to-port communication
• Full on-chip hardware support of semaphore Signaling
between ports
• Fully asychronous operation from either port
• Battery backup operation-2V data retention
• TTL compatible, single 5V (±10%) power supply
• Available in 68-pin PGA
FUNCTIONAL BLOCK DIAGRAM
R/WL--r-~==~[)----~
CEL=====~~~__~
~L
A13L - - : ; - - t - - - ,
AWL ----=:o--t--,
II07L
I/07R
I/OOL
IIOOR
805)\(1) - , . - - - - - - - - - - '
lmSY'R(l)
A9L -+---:--+1
AOL -.+--=---+1
A9R
AOR
A 13L
----::---.r===~-___::--- A13R
AOL ---"----tI ARBITRATION
CE L
INTERRUPT
~ L --~ SE~~~~c"RE
RtWL
AOR
CE R
~R
R/W R
~R
lNiR
NOTE:
1. (MASTER): tmSY is output.
(SLAVE): BDS'Y is input.
CEMOS is a trademark of Integrated Device Technology,lnc.
MIS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
1989 Integrated Device Technology. Inc.
DSC-l044/-
S5-109
'-'--"-"'---
---_._-_._----
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7006 HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
PIN NAMES
LEFT PORT RIGHT PORT
11
NAMES
ct:L
ct: R
Chip Enable
RfliL
RfliR
Read/Write Enable
~L
~R
Output Enable
AOL-13L
AOR-13R
Address
1I0 0L-7L
I/O oR-7R
Data InpuVOutput
SEM L
~R
Semaphore Enable
INTL
INTR
Interrupt Flag
tITJS'YL
tITJS'YR
Power
GND
Ground
Mm
Master or Slave
Select
56
AWL
30
A9R
31
A8R
07
59
Vcc
58
A12L
28
AllR
A1DR
06
61
NC
60
A 13L
05
63
~L
cr L
04
65
OE'L
Rflh
MODE
X
X
H
Hi-Z
Deselected: Power Down
H
H
L
L
DATA OUT
Read Data in Sema. Flag
X
X
H
X
Hi-Z
X
L
DATA IN
H
L
H
DATA OUT
Read Memory
L
X
H
DATA IN
Write to Memory
L
X
X
L
-
Not Allowed
Note:
1. AOL - A13R -f. A OR - A 13R
TRUTH TABLE: ARBITRATION OPTIONS
L
24
NC
OUTPUTS
~
IDJS?
TNT
H
Output
Signal
-
H
Input
Signal
-
Interrupt Logic
L
X
H
-
Output
Signal
Semaphore Logic*
H
H
H
L
L
L
H
Hi-Z
-
*Inputs Signals are for Semaphore Flags set and test (Write and Read)
operations
S5-110
25
A 13R
23
22
~F CE'R
21
20
OE'R RflVR
67
66
1I00L NC
68
1
18
7
9
11
13
15
3
5
II0 1L I/0 2L II0 4L GND II07L GND I/0 1R \bc II0 4R II0 7R
4
2
6
8
10
12
14
17
16
II0 3L II0 5L II06L Vcc I/OoR I/02R I/0 3R II05R II0 6R
Outputs Disabled
L
L
62
B
29
26
27
GND A12R
64
Write DINointo Sema. Flag
L
Busy Logic Slave
7006
16Kx8DPR
IN 68-PIN PGA
37
A2R
C
D
E
F
G
H
Note:
1. All Vcc pins have to be connected to power supply.
2. All GND pins have to be connected to ground supply.
H
H
~
68-PIN PGA
TOP VIEW
OUTPUTS
L
34
A5R
57
AllL
~
Busy Logic Master
35
A4R
08
C51:
Mis
39
AOR
36
33
A6R
R/W
INPUTS
A3R
32
A7R
CE
CE
45
43
TNTL GND
40
36
TNTR A1R
54
A8L
TRUTH TABLE: NON-CONTENTION
READ/WRITE CONTROL
OPTIONS
47
AlL
42
M~
55
A9L
A
S
49
A3L
ImS?l
09
01
H
46
AOL
52
A6L
02
1/00 - 1/0 7
48
A2L
50
53
A7L
03
INPUTS(l)
A4L
10
Busy Flag
Vcc
44
51
A5L
K
19
NC
L
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7006 HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
ORDERING INFORMATION
IDT
xxxx
Device Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
Range
y:mnk
'-------------1
'-----------------l
'---------------------l
'------------------------1
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Method 5004, Class B
PG
G
68-pin Plastic PGA Commercial Only
68-pin PGA
35
45
55
70
90
100
120
Commercial onlY)
Military Only
S
L
Standard Power
Low Power
7006
128K (16K x 8) Dual-Port RAM
Speed in Nanoseconds
S5-111
-----_. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
&J
ADVANCE
INFORMATION
lOT 7050S
lOT 7050L
HIGH-SPEED
1K x 8 FOUR-PORT
STATIC RAM
Integrated DevIceTechrtology. Inc.
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 30/35/45ns (max.)
The 1017050 Is a high-speed 1K x 8 four-port static RAM designed to be used in systems where multiple access In a common
RAM Is required. This four-port static RAM offers Increased system
performance in multiprocessed systems that have a need to communicate in real time and also offers added benefit for high-speed
systems In which multiple access is required in the same cycle.
The 1017050 is also an extremely high-speed 1K x 8 four-port
static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be
able to externally arbitrate or withstand .contention when all ports
simultaneously access the same four-port RAM location.
The 1017050 provides four independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the
user's responsibility to ensure data integrity when simultaneously
accessing the same memory location from all ports. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology, these four ports typically operate on only ---mW of power at
maximum access times as fast as 25ns. Low-power (L) versions
offer battery backup data retention capability, with each port
typically consuming ---J!W from a 2V battery.
The 1017050 Is packaged In either a ceramic or plastic 108-pln
PGA and 132-pin quad flatpack. Military grade product Is manufactured in compliance with the latest revision of MIL-STO-883,
Class B.
- Commercial: 25/30/35/45ns (max.)
• Low-power operation
- 10T7050S
Active: ---mW (typ.)
Standby: ---mW (typ.)
- 10T7050L
Active: ---mW (typ.)
Standby: ---mW (typ.)
• Fully asynchronous operation from each of the four ports: P1,
P2,P3,P4
• Versatile control for write-inhibit: separate BUSY input to
control write-inhibit for each of the four ports
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available In several popular hermetic and plastic packages for
both through-hole and surface mount
• Military product compliant to MIL-STO-883, Class B
FUNCTIONAL BLOCK DIAGRAM
0--...-- RIW P4
R!WP1---n
CE" P1 ---+-...0
(jE"P1
[r.-f---
---a
n----OEP4
t4-------- 1/00 P4
1100 P1 - 1Iq. P104-----'-----.I
~ P1
CE" P4
--;======:;'
-II~
P4
.';::====::;-- ~ P4
PORT 1
AoP1-AsP1------~~~~~lr~
Ao P4 - As P4
LOGIC
MEMORY
ARRAY
PORT 2
PORT 3
14---...--1 ADDRESS
AoP2-AsP2------~~ ~~EJ~ ~-.~~
DECODE
LOGIC
LOGIC
.....--~--....
t4----
Ao P3 - Ag P3
~ P2 ~======~
1100 P2 - 1107
t4-------- 1/00 P3 - II~ P3
P'~--------------~
OEP2
----a
D----OEP3
D-4>-t---CE" P3
CE" P2 ---+-+0
'-----_L~*--
R!WP2-~-U
RIW P3
CEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE
©
RANGE~
JANUARY 1989
OSC-l068/-
1989 Integrated Device Technology. Inc.
S5-112
IDT70S0S AND IDT70S0L
HIGH-SPEED 1 K X 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
SYMBOL
Address Lines - Port 1
AO P2 - A9 P2
Address Lines - Port 2
AO P3 - A9 P3
Address Lines - Port 3
AO P4 - A9 P4
Address Lines - Port 4
1/00 P1 - 1/07 P1
Data I/O - Port 1
1/00 P2 - 1/07 P2
Data I/O - Port 2
1/00 P3 - 1/07 P3
Data I/O - Port 3
1/00 P4 - 1/07 P4
Data I/O - Port 4
R!WP1
Read/Write - Port 1
RtW P2
Read/Write - Port 2
RtW P3
Read/Write - Port 3
R!WP4
Read/Write - Port 4
GND
Ground
CE P1
Chip Enable - Port 1
CEP2
Chip Enable - Port 2
CE P3
Chip Enable - Port 3
CE P4
Chip Enable - Port 4
Output Enable - Port 1
DEP2
Output Enable - Port 2
DE P3
Output Enable - Port 3
DE P4
Output Enable' - Port 4
BUSY P1
Write Disable - Port 1
BUSY P2
Write Disable - Port 2
BUSY P3
Write Disable - Port 3
BUSY P4
Write Disable - Port 4
Vcc
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
80
NC
77
A7
P2
83
78
~Ot:P2 A8
P2
P2
87::::: :86::::· 82
A2'A1 CE:P2
Pt: ·P1
90::::, 88::,·
.~~
.
:,A3
74
A5
P2
76
NC
79
A9
P2
72
A3
P2
73
A4
P2
75
A6
P2
69
AO
P2
70
A1
P2
71
A2
P2
68
AO
P3
67
A1
P3
66
A2
P3
65
A3
P3
64
A4
P3
62
A6
P3
63
A5
P3
61
NC
60
A7
P3
59
A8
P3
57
NC
54
RtW 12
P3
56
53
Ot: P3!IDS? 11
P3
~ p::~11:.5.2p24·
... !.•
P4
58
A9
P3
:85·
'::AO':·
52::,:. 49....
•. ~~...~t.~t.
~r,~r :NQ:
P1··· ::Pl
10
47,::::
09
48.::. 46:,: 45:::::·
IDT7050
108 Pin PGA
95::: 94'
93
AIL . '. Ap7.1.'. •'. . .• Vcc
,pt·
08
44
GND
43 ... 42:::::
A7
AS: 07
.P4:': ··p4
35..
37,:
TOP VIEW
. DE P1
SYMBOL
81
R!W
P2
84
PIN NAME
AO P1 - A9 P1
99·,·:
f../W
100102
Yss~P4RtW
05
: :,::,::,::: ·::P4:::
101::103:. 106
1/01 GND
31
GND
1IDSY
:,pr:
:'~:ilOO
104::: 1O!):: , 1:::::::. 4
8
12
17
21
25
1/021/031106 Vee GND Vee
Vee GND Vec
P1:: :: P.l: ·,P1
107. 2
5
7
10
13
16
19
22
1/041107 1/00 1/02 1/04 1106 1101 1/03 1/05
P2
::P1':: :Pl::
P2
P2
P2
P3
P3
P3
108: 3
6
11
14
15
18
9
20
1/05 NC 1/01 1/03 1105 1/07 1/00 1/02 1/04
P1
P2
P2
P2
P2
P3
P3
P3
A
B
C
o
E
F
G
H
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
CAPACITANCE
(1)
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
+70
34
36 ...
1/07 troSY 04
P4 . P4
28 ..... 32
33
1I02 1/05 1106 03
,,:P4:: P4:: P4::·
24
29,:::: 30:::,
·'PJ:
COMMERCIAL
o to
38:::
:: Pl':· ::P1· .. ::P1··
-55 to +125
°C
Temperature
Under Bias
-55 to +.125 . -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
loUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
P3
23
1/06
P3
K
1103 1104 02
.P4 ·P4:
26
27::
1/00 1101 01
:P4: 'P4::
L
M
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
SYMBOL
1/07
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS
MAX.
UNIT
VIN = OV
11
pF
Vour= OV
11
pF
NOTE:
1, This parameter is determ.ined by device characterization but is not
production tested.
'
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
Vee
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vec
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
SS-113
1DT70S0S AND IDT70S0L
HIGH-SPEED 1Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
(Vee = 5.0V ±10%)
IDT70S0S
MIN.
MAX.
TEST CONDITIONS
PARAMETER
10L = 4mA
0.4
10H= -4mA
2.4
-
Input Leakage Current
Vee = 5.5V, '-"N = OV to Vee
IILol
Output Leakage Current
CE = '-"H, VOUT = OV to Vee
VOL
Output Low Voltage
VOH
Output High Voltage
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1,2)
SYMBOL
lee1
Icc2
ISB
IS81
PARAMETER
TEST CONDITION
-
-
lIu l
VERSION
Operating Power
Supply Current
(All Ports Active)
CE ='-"L
Outputs Open
f = 0(4)
MIL.
Dynamic Operating
Current (All Ports
Active)
CE = '-"L
Outputs Open
f = fMAX (5)
MIL.
Standby Current
(All Ports - TTL
Level Inputs)
CE ~ V1H
f = fMAX (5)
COM'L.
COM'L.
MIL.
COM'L.
All Ports
MIL.
Full Standby Current
CE ~ Vce -0.2V
(80th Ports-All CMOS
V1N ~ Vee -0.2V or
Level Inputs)
V S 0.2V, f = 0(4) COM'L.
1N
S
L
S
L
S
L
S
l
S
L
S
L
S
L
S
L
IDT7050x25 (3)
MAX.
TYP.
-
300
250
350
_295
-
85
~O_
5
1.5
10
10
-
-
-
UNIT
5
Jl.A
-
5
Jl.A
0.4
V
2.4
-
V
(Vee = 5.0V ±10%)
IDT7050x30
TYP.
MAX.
-
IDT7050L
MIN.
MAX.
IDT70S0x3S
1DT70S0x45
MAX. TYP.
TYP.
MAX.
360
300
300
250
400
335
340
285
115
85
80
65
15
4.5
-
5
1.5
-
-
-
360
300
300
250
395
330
335
280
110
80
75
60
15
4.5
-
360
·300
300
250
390
325
330
275
105
75
70
55
15
4.5
5
1.5
-
5
1.5
UNIT
mA
mA
mA
mA
NOTES:
1.
2.
3.
4.
5.
·x· in part number indicates power rating (S or L).
Vce = 5V, TA = + 25°C for TYP.
O°C to + 70°C temperature range only.
f = 0 means no address or control lines change.
At f = fMAX' address and data inputs (except Output Enable) are cycling at the maximum frequency of read cycle of 14Re' and using· AC Test Conditions· of input levels of GND to 3V.
S5-114
IDT7050S AND 1DT7050L
HIGH-SPEED 1Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(L Version Only) VLC = 0.2V, VHC
SYMBOL
VDR
ICCDR
= Vcc -
0.2V
TEST CONDITION
PARAMETER
Vcc for Data .Retention
I MIL.
I COM'L.
Vcc = 2V
Data Retention Current
t cOR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
CE ~VHC
~N ~ VHC or:::; VLC
MIN.
TYP.(1)
2.0
-
-
-
1800
-
600
0
t RC (2)
NOTES:
1. VCC = 2V, TA = +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
'bc
~
'71 Zllt
DATA RETENTION MODE~
4.5V.
VOR
~ 2V
tco1
VI H '
OR
V
•
4.5V
tRl
1"--~-r~H-S. . S-\-\
. . . S-'
.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to3.0V
Sns
1.SV
1.SV
See Figures 1 & 2
SV
DATAoUT
~
7750
.
5V
12S00
DATA OUT
30pF*
~
7750
Figure 1. Output Load
12500
SpF*
Figure 2. Output Load
(for tLZ.t HZ' twz.tow)
*Including scope and jig.
S5-115
MAX.
UNIT
V
/J.A
-
ns
-
ns
IDT7050S AND IDT7050L
HIGH-SPEED 1K x 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL
"
PARAMETER
IDT7050S25 (1, 3)
IDT7050L25 (1, 3)
MAX.
MIN.
IDT7050S30
IDT7050L30
MIN.
MAX.
IDT7050S35
IDT7050L35
MAX.
MIN.
IDT7050S45
IDT7050L45
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
25
-
30
-
35
-
45
-
ns
tAA
Address Access Time
25
-
45
ns
35
-
45
ns
t AOE
O,utput Enable Access Time
-
35
Chip Enable Access Time
-
30
t ACE
-
25
-
30
ns
tOH
Output Hold From Address Change
0
0
-
ns
3
3
5
-
0
Output Low Z Time (1. 2)
-
0
tLZ
-
5
-
ns
tHZ
Output High Z Time(l. 2)
-
15
-
15
-
15
-
20
ns
t pu
Chip Enable to Power Up Time (2)
0
-
0
-
0
-
0
-
ns
tpD
Chip Disable to Power Down Time(2)
-
20
-
30
-
50
-
50
ns
25
15
30
20
, NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter Is guaranteed but not tested.
3. OOC to + 70°C temperature range only.
TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE
ADDRESS
DATA OUT
lZt ~
(1,2,4)
t~,.......---_t,·to"~.
,",,"O",OA:;uq XX~______
~
D_A_TA_V_A_UD_ _ _ _ _
TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE
(1,3)
DATA OUT
CURRENT
~--- tLZ - -___~
~
tpD
t
loo _ _ _ _ _ _ _ _ _
pu_~_1~----------------
t
50%
'
IS8
NOTES:
1. RiW is high for Read Cycles.
2. Device Is continuously enabled, CE = \IL'
3. Addresses valid prior to or coincident with CE transition low.
4. DE = V1L
S5-116
50%
.'
",--'-_ ..
__.. , - - , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDT70S0S AND IDT70S0L
HIGH·SPEED lKx 8 FOUR·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
PARAMETER
SYMBOL
I DT7050S2S(1)
IDT7050L25(1)
MIN.
MAX.
IDT7050S30
IDT7050L30
MIN.
MAX.
IDT7050S35
IDT7050L35
MIN.
MAX.
IDT7050S45
IDT7050L45
MIN.
MAX.
UNIT
WRITE CYCLE
30
20
-
Address Set-up Time
0
-
0
twp
Write Pulse Width (3)
20
-
25
tWR
Write Recovery Time
5
-
5
tow
Data Valid to End of Write
15
-
15
-
tHZ
Output High Z Time(1,2)
-
15
-
tOH
Data Hold Time
0
-
0
twz
Write Enabled to Output in
High Z(1.2)
-
15
tow
Output Active From End of Write (1.2)
0
-
twoo
Write Pulse to Data Delay(4)
-
tO~~
Write Data Valid to Read Data Delay(4)
35
-
35
-
ns
0
-
ns
35
-
ns
5
-
ns
5,
-
20
-
20
-
ns
15
-
15
-
20
ns
-
0
-
0
-
ns
-
15
-
15
-
20
ns
0
-
0
-
0
-
ns
40
-
50
-
60
70
ns
-
30
-
35
-
40
-
45
ns
-
0
-
0
-
0
-
ns
20
-
20
-
20
-
ns
twc
Write Cycle Time
25
tEW
Chip Enable to End of Write
20
tAw
Address Valid to End of Write
tAS
25
25
35
30
30
0
30
45
ns
ns
BUSY INPUT TIMING
twa -
Write to BuSY (5)
0
tWH
Write Hold After 1fLj"Sy" (6)
15
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. Specified for'C5E at high (refer to "Timing Waveform of Write Cycle". Note 7).
4. Port-to-port delay through RAM cells from writing port to reading port. refer to "Timing Waveform of Read with Port-to-Port Delay·.
5. To ensure that the write cycle is inhibited during contention.
,6. To ensure that a write cycle is completed after contention.
7. DoC to + 70°C temperature range only.
S5-117
- - - - - - - - - - - - - - - - - - - - - - - -------------- -----,,----
IDT7050S AND IDT7050L
HIGH-SPEED 1Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
ADDRESS
twc
=>K
)(
t
f
tAw
~ i\.
,
~tAS-"
Rm
....
t
(7)
tWR
Wp
/
V
(6)HZ
-
_twt)tow
"
(4)
DATA OUT
I-tow
~ I--
./
'"
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING
• (4)
"
./
DATA IN
'"
t OH -
(1,2,3,5)
~-----------------------twc----------------------~~
ADDRESS
1..-------------- tEW ------------.j
Rm
NOTES:
1.
2.
3.
4.
5.
6.
7.
RiW must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low Rl'W.
tWR is measured from the earlier of
or Rl'W going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.
Transition is measured ±SOOmV from steady state with a SpF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to tum off
data to be placed on the bus for the required tow. If C5E is high during an R!W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wp .
cr
55-118
--- --------------------------------------------------
IDT7050S AND IDT7050L
HIGH·SPEED 1Kx 8 FOUR·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY (1,2,3)
twc
)(
)(
MATCH
twp
~'"
)(
DATA 1NP1
~,
ADDR P2, P3, or P4
VALID
/~
MATCH
I
tWDD
)E
DATA p2, P3, or P4
tDDD
NOTES:
1. Assume B'DSY input at HI and CE at LO for the writing port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for any of the reading ports which has its DE at LO.
TIMING WAVEFORM OF WRITE WITH BUSY INPUT
twp
R/W
BUSY
-{1M
rlWH~
/
S5-119
------ -------------------------"----'--
IDT7050S AND IDT7050L
HIGH-SPEED 1Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I-READ/WRITE CONTROL
FUNCTIONAL DESCRIPTION:
The IDT7050 provides four ports with separate control, address
and I/O pins that permit independent access for reads or writes to
any location in memory. These devices have an automatic power
down feature controlled by CEo The CE controls on-chip power
down circuitry that permits the respective port to go into standby
mode when not selected (CE high). When a port is enabled, access
to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. READ/WRITE conditions are Illustrated in the table below.
ANY PORT (1)
R/W
CE
OE
FUNCTION
DO-7
X
H
X
Z
X
H
X
Z
Port Disabled and in Power Down
Mode
~Pl
= ~P2 = ~P3 = ~P4' = H
Power Down Mode, IS91 or IS9
Data on Port Written Into Memory (2,3)
L
L
X
DATA IN
H
L
L
DATA OUT Data in Memory Output on Port
X
X
H
Z
High impedance Outputs
NOTES:
1. H = HIGH, L == LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
2. If"l3US? = LOW, data is not written.
3. For valid write operation, no more than one port can write to the same
address location at the same time.
S5-120
G
Integrated DevIceKxhnology.Inc.
ADVANCE
INFORMATION
lOT 7052S
lOT 7052L
HIGH-SPEED
2K x 8 FOUR-PORT
STATIC RAM
FEATURES:
DESCRIPTION:
• High-speed access
- Military: 30/35/45ns (max.)
The IDT7052 is a high-speed 2K x 8 four-port static RAM de.:
signed to be used in systems where multiple access to a common
RAM is required. This four-port static RAM offers increased system
performance in multiprocessed systems that have a need to communicate in real time and also offers added benefit for high-speed
systems in which multiple access is required in the same cycle.
The1DT7052 is also an extremely high-speed 2K x 8 four-port
static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be
able to externally arbitrate or withstand contention when all ports
simultaneously access the same four-port RAM location.
The IDT7052 provides four independent 'ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the
user's responsibility to ensure data integrity when simultaneously
accessing the same memory location from all ports. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, this four port RAM typically operates on only ---mW of power
at maximum access times as fast as 25ns. Low-power (L) versions
offer battery backup data retention capability, with each port
typically consuming ---jl.W from a 2V battery.
The IDT7052 is packaged in either a ceramic or plastic 108-pin
PGA and 132-pin quad flatpack. Military grade product is manufactured .in compliance with the latest revision of MIL-STD-883,
Class B.
- Commercial: 25/30/35/45ns (max.)
• Low-power operation
- IDT7052S
Active: ---mW (typ.)
Standby: ---mW (typ.)
- IDT7052L
Active: -..,-mW (typ.)
Standby: ---mW (typ.)
• Fully asynchronous operation from each of the four ports: P1,
P2, P3,P4
• Versatile control for write-inhibit: separate BUSY input to
control write-inhibit for each of the four ports
• Battery backup operation-2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in several popular hermetic and plastic packages for
both through-hole and surface-mount
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
R!W P1
cr P1
---<11.--(1
n---.---
--+-IK.l
D-....-f--- crP4
OE"P1---a
0----
--------.t
1/00 P1 - 1/0 7 P1 __
I30SY P1
Ao P1 ~ A 10 p1
QE"P4
1/00 P4 - 1/07 P4
-;::===;- BUSV P4
-;======:;
-----i...
R!W P4
PORT 1
ADDRESS
DECODE
LOGIC
PORT 4
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
PORT 2
Ao P2 - A 10 P2 - - - -...... ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
BlJS? P2 -=::::::::~
....- - - - - - - - . 1/00 P3 -1/0 7 P3
lIDo P2 - 1/0 7 P2
QE"P2---(]
[ } - - - - 'QE"P3
C1: P2 ---+-+-n
R!W P2 ---4'--U
D-1I.....r-- cr P3
u--+--- R!W P3
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
080-1069/-
1989 Integrated Device Technology, Inc.
S5-121
1DT7052S AND IDT7052L
HIGH-SPEED 2K x 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Address Lines - Port 1
AD P2 -A1D P2
Address Lines - Port 2
AD P3 -A1D P3
Address Lines - Port 3
AD P4 -A1D P4
Address Lines - Port 4
1/00. Pl - 1/07 P.l
Data I/O - Port 1
1/00. P2 - 1/07 P2
Data 1/0- Port 2
1/00. P3 - 1/07 P3
Data I/O - Port 3
1/00. P4 - 1/07 P4
Data I/O - Port 4
RtW Pl
Read/Write - Port 1
RtWP2
Read/Write - Port 2
RtWP3
Read/Write - Port 3
RtWP4
Read/Write - Port 4
GND
Ground
~Pl
Chip Enable - Port 1
CEP2
Chip Enable - Port 2
CE P3
Chip Enable - Port 3
CEP4
Chip Enable - Port 4
OE Pl
Output Enable - Port 1
t)EP2
Output Enable - Port 2
OE P3
OE P4
BOSY Pl
Output Enable - Port 3
Write Disable - Port 1
BUSY P2
Write Disable - Port 2
BOSY P3
Write Disable - Port 3
BUSY P4
Write Disable - Port 4
Vee
Power
GND
Ground
VTERM
RATING
Terminal Voltage
with Respect to
GND
80.
77
74
A7
A5
P2
P2
83
78
76
'lIDS'? ~P2 A8 A1D
P2
P2
P2
79
87:'::::: :86::: 82
A2 :A1 CEP2 A9
P2
Pi' PI
90.:::::: 88::::: :85:::::
'AS:: :::A3'::
NC
::Pl:::' ::P1':::
.~~ ..
$1.::::: 89
92.:
:Al0 :::A6'" ::A4:::
PI :Pl ... :PF
95::::::
93
:'AS:
Vee
::Pl,:: pi'
96
$7::::: 98:
A9
NC cgP1
:::Pt::
99::::. 10.0. :10.2:::
91;.u
A/W
::Pt":
'O'E': IlaC)
Pl .. ::Pl:::
10.1:::: 103:
BUSY .::1101
P:1:
::Pl'
10.4::· 10.5
1102 1103
::pt;: ':'p,.:,:
10.7·: 2.:::::::
1/04 1/01
Output Enable - Port 4
ABSOLUTE MAXIMUM RATINGS
SYMBOL
81
RtW
P2
84
PIN NAME
SYMBOL·
AD Pl -A1D Pl
'PL
PI
10.8, 3
1105 NC
Pl:
A
10.6
GND
1:::::::' 4
1/06
::PF
5
1/00.
P2
6
1/01
P2
B
C
Vee
7
1/02
P2
9
1/03
P2
D
57
60
54
A7
NC
RtW 12
P3
P3
59
53
70.
Al
A1D
A4
A8
P3 'lIDS'? 11
P3
P2
P3
P3
P3
71
62
58
55
51::,.: 50.<:
A9 -crP3 At. A2
A2
A6
10
P2
P3
P3
P4: :P4::
49::::· 47:;::::
52"
::AD"
A3
As 0.9
:P4 '::P4:::
MAX.
UNIT
2.0
-
-
V
0
t RO (2)
NOTES:
1. Vce = 2V, TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested .
. LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
'to
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
Sns
1.SV
1.5V
See Figures 1 & 2
SV
DATAoLrr
~
77S0.
SV
12S00
DATAoLrr
~OPF*
~
77S0
Figure 1. Output Load
12500
SpF*
Figure 2. Output Load
(for tLZ.t HZ ' twz.tow)
*Including scope and jig.
S5-124
1800
600
-
J.lA
ns
ns
IDT7052S AND IDT7052L
HIGH-SPEED 2K X 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
IDT7052S25 (3)
IDT7052L25 (3)
. MIN.
MAX•
PARAMETER
SYMBOL
IDT7052S30
IDT7052L30
MIN.
MAX.
IDT7052S35
IDT7052L35
MIN.
MAX.
IDT7052S45
I DT7052L45
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
25
-
30
-
35
-
45
-
ns
tAA
Address Access Time
-
25
-
30
-
35
45
ns
tAcE
Chip Enable Access Time
25
-
30
45
ns
Output Enable Access Time
15
-
20
-
35
t AoE
-
-
30
ns
to~
Output Hold From Address Change
0
:...
0
-
0
0
Output Low Z Time (1. 2)
3
-
3
-
5
5
-
ns
tLZ
-
tHZ
Output High Z Time(l. 2)
-
15
-
15
-
15
-
20
ns
tpu
Chip Enable to Power Up Time (2)
0
-
0
-
0
-
0
-
ns
t pD
Chip Disable to Power Down Time(2)
-
20
-
30
-
50
-
50
ns
25
ns
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. DoC to 70°C temperature range only.
TIMING WAVEFORM OF READ CYCLE NO.1, ANY PORT(l,2,4)
ADDRESS
DATA OUT
=t=,
~
_o",DA::;q
;c_ _
t'OO=:Lr
4XX
XX ~_______
DA_T_A_VA_U_D_ _ _ _ _
TIMING WAVEFORM OF READ CYCLE NO.2, ANY PORT(l,3)
~----- tAcE----..,"'·1
------1
DATA OUT
PU. . .
1 + - - - - tLZ ---~
t
CURRENT
l
IS8
NOTES:
1. Rm is high for Read Cycles.
2.
3.
4.
tPD-L
Icc _ _ _ _ _ _ _ _ _ _~~------------------_ _ _ _ _ _ _ _--'
50%
50%
,I
i
Device is continuously enabled, CE = ~L'
Addresses valid prior to or coincident with CE transition low.
DE = V1L
S5-125
IDT7052S AND IDT7052L
HIGH-SPEED 2Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
PARAMETER
SYMBOL
IDT7052S25 (7)
IDT7052L25 (7)
MIN.
MAX.
IDT7052S30
IDT7052L30
MAX.
MIN.
IDT7052S35
1DT7052L35
MAX.
MIN.
1DT7052S45
1DT7052L45
MIN.
MAX.
UNIT
WRITE CYCLE
-
45
-
ns
35
ns
35
0
-
-
30
-
35
5
5
-
15
-
20
-
-
ns
5
-
20
-
ns
-
15
-
15
-
15
-
20
ns
Data Hold Time
0
-
0
-
0
-
0
-
ns
Write Enabled to Output in
High Z(1.2)
-
15
-
15
-
15
-
20
ns
twc
Write Cycle Time
25
Chip Enable to End of Write
20
-
30
tEW
tAW
Address Valid to End of Write
20
-
25
t As
Address Set-up Time
0
0
twp
Write Pulse Width (3)
20
-
25
tWR
Write Recovery Time
5
-
tow
Data Valid to End of Write
15
tHz
Output High Z Time(1.2)
tOH
twz
25
-
35
30
30
0
ns
ns
ns
tow
Output Active From End of Write (1.2)
0
-
0
-
0
-
0
-
ns
twoo
Write Pulse to Data Delay(4)
-
40
50
ns
-
30
35
40
-
70
Write Data Valid to Read Data Delay(4)
-
60
tOOD
-
45
ns
-
0
-
0
20
-
ns
20
BUSY INPUT TIMING
tWB
Write to gm'y
tWH
Write Hold After f:mS'Y (6)
(5)
0
-
0
15
-
20
ns
NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. Specified for '()E" at high (refer to "TIMING WAVEFORM OF WRITE CYCLE", Note 7).
4. Port-to-port delay through RAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY".
5. To ensure that the write cycle is inhibited during contention.
6. To ensure that a write cycle is completed after contention.
7. O°C to + 70°C temperature range only.
S5-126
1OT7052S AND IDT7052L
HIGH·SPEED 2Kx 8 FOUR·PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
twc
ADDRESS
~
--.J
)K
K
t
(6)-
HZ
/V
tAW
~~
~tAS·-"
"
t
(7)
tWR
Wp
/~
-
_twt)tow
/ . ( 4 ) ·••••••••• ·.~ I--
(4)
DATA OUT
~tDW
t DH -
'"
/.
DATA IN
"-
./
TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING
(1,2,3,5)
..................................................--twc--..................................................~
~
ADDRESS
.............................................--tAW ..............................~..........~
~
.~------
tEW ..............................-..J
DATA IN
NOTES:
1.
2.
3.
4.
5.
6.
7.
Rm
must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low
and a low RlW.
tWR is measured from the earlier of
or RlW going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (twz + t DW) to allow the I/O drivers to tum off
data to be placed on the bus for the required t DW ' If
is high during an RIW controlled write cycle, this reqUirement does not apply and the
write pulse can be as short as the specified t wP '
cr
cr
rn:
55-127
- - - - -.....- - - - - - - - - - - - - - - - - - - - - . - . - - - -...
----.-----.------~
IDT7052S AND IDT7052L
HIGH-SPEED 2K x 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY (1,2,3)
twc
)(
)(
MATCH
tow
~\.
)(
DATA 1NP1
VALID
/~
MATCH
ADDR p2• P3. or P4
twoo
)~
DATA OUT P2. P3 or P4
tODD
NOTES:
1. Assume tmS'Y' input at HI and
at LO for the writing port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for any of the reading ports which has its ()E' at LO.
cr
TIMING WAVEFORM OF WRITE WITH BUSY INPUT
~---------------twp-.------------~
R/VV
S5-128
10T7052S AND 10T7052L
HIGH,SPEEO 2Kx 8 FOUR-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I-READ/WRITE CONTROL
FUNCTIONAL DESCRIPTION:
The IDT7052 provides four ports with separate control, address
and 1/0 pins that permit independent access for reads or writes to
any location in memory. These devices have an automatic power
down feature controlled by CEo The CE controls on-chip power
down circuitry that permits the respective port to go into standby
mode when not selected (CE high). When a port is enabled, access
to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on
the output drivers when set LOW. READ/WRITE conditions are illustrated in the table below.
ANY PORT (1)
FUNCTION
R/W
CE
OE
X
H
X
Z
X
H
X
Z
L
L
X
DATA IN
DATA OUT Data in Memory Output on Port
H
L
L
X
X
H
00-7
Z
Port Disabled and in Power Down
Mode
CE"Pl = CE"P2 = CE"P3 = CE"P4, = H
Power Down Mode, I SB or I SBl
Data on Port Written Into Memory (2.3)
High Impedance Outputs
NOTES:
1. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE
2. If BUS'? = LOW, Data is not written.
3. For valid write operation, no more than one port can write to the same
address location at the same time.
55-129
FIFO Memories
-----------------
FIFO MEMORIES
Integration of IDT's high-speed static RAM technology with
Internal support logic yields high-performance, high-density FIFO
memories. A FI FO is used as a memory buffer between two
asynchronous systems with simultaneous read/write access. The
data rate between the two systems can be regulated by monitoring
the status flags and throttling the read and write accesses. Since
these FIFOs are built with an internal RAM pointer architecture,
there is no fall-through time between a write to a memory location
and a read from that memory location. System performance is
significantly improved over the shift register-based architecture of
previous FIFO deSigns which are handicapped with long
fall-through times.
IDT offers the widest selection of monolithic FIFOs, ranging
from shallow 64 x 4 and 64 x 5 to the high-density 4K x 9. Shallow
FIFOs regulate data flow in tightly coupled computational engines.
High density FI FOs store large data blocks in networking, telecommunication and data storage systems. The IDT7200 FIFO family
(256 x 9 through the 4K x 9 FIFOs) are all pin and function
- - - - - - - - - - - - - - ----------_._-_ .........-_...
compatible, making density upgrades simple. All IDT FIFOs can
be cascaded to greater word depths and expanded to greater word
widths with no external support logic.
A variety of packages are available: standard plastic DIP and
CERDIP, surface mount ceramic LCC, PLCC and SOIC and highreliability Flatpack. Increasing board density is the overwhelming
goal of the IDT's package development efforts, as demonstrated
by the introduction of the 300 mil THINDIP.
The Parallel-Serial FIFO incorporates a serial input and a serial
output shifter for serial-to-parallel bus interface. The Parallel-Serial
FIFO also offers six status flags for flexible data throttling.
FIFO modules, composed of four LCe devices mounted on a
multi-layer co-fired ceramic substrate, increase densities to
16K x 9 which are pin-compatible with current monolithic versions.
IDT is committed to offering FIFOs of increasing density and
speed and enhanced architectural innovations, such as Flexishift
and the BiFIFO, for easier system interface.
TABLE OF CONTENTS
CONTENTS
FIFO Memories
lOT 7200
lOT 7201A
lOT 7202SNLA
lOT 72021
lOT 72031
lOT 72041
lOT 7203
IDT7M203
lOT 7204
IDT7M204
lOT 72B04
lOT 72045
lOT 72055
lOT 7205
IDT7M205
lOT 7206
IDT7M206
lOT 72103
lOT 72104
lOT 72105
IOT72115
lOT 72125
lOT 72131
lOT 72141
lOT 72132
lOT 72142
IOT72215
lOT 72225
lOT 72401
lOT 72402
lOT 72403
lOT 72404
lOT 72413
lOT 7252
lOT 72520
lOT 7MB2001S
IOT7MB2002
lOT 72521
PAGE
256 x 9 FIFO (14-1, 14-251, 14-254, 14-257) .................................. ; .. . .. S6-1
512 x 9 FIFO (14-1, 14-251, 14-254, 14-257) ........................................ S6-1
CMOS ParalleIFirst-ln/First-Out FIFO 1024 x 9-Bit .................................... SS-14
CMOS Parallel FIFO with Flags and OE-1 K x 9, 2K x 9, 4K x 9 ......................... S6-27
CMOS Parallel FIFO with Flags and OE-1K x 9, 2K x 9, 4K x 9 ................. ........ S6-27
CMOS Parallel FIFO with Flags and OE-1K x 9, 2K x 9, 4K x 9 ......................... S6-27
2K x 9 FIFO (14-251, 14-56, 14-68) ............................................. ~.. S6-41
CMOS Parallel In-Out FIFO Module 2K x 9-Blt & 4K x 9-Blt ........................... 13-146
4K x 9 FIFO (14-251, 14-56, 14-68) .. .. . .. .. . . . . . .. .. .. . .. . . .. . . . .. . . . .. . . .. .. .. ... S6-41
CMOS Parallel In-Out FIFO Module 2K x 9-Blt & 4K x 9-Blt ..................•........ 13-146
BiCMOS Parallel First-In/First-Out FIFO 4K x 9-Bit ...................................• S6-54
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Bit.. . .. . . . . .. .. . .. .. . . . ..... S6-55
CMOS Parallel First-In/First-Out FIFO 4K x 18-Bit & 8K x 18-Bit . . . . . . . . . . . . . . . . . . . . . . . . .. SS-55
CMOS Parallel First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit ... " .. . . . . . .. . . ..... . . . ... SS-56
8K x 9 FIFO Module ............................................................ 13-157
CMOS Parallel First-In/First-Out FIFO 8K x 9-Bit & 16K x 9-Bit ..... .. . . . . . . . . .. .... . ... .. S6-56
16K x 9 FIFO Module ...................•....................................... 13-157
2K x 9 Parallel-Serial FIFO (14-146) .............................. ........ .......... S6-57
4K x 9 Parallel-Serial FIFO (14-146) ........................................ " . . . ... S6-57
256 x 16,512 x 16, 1024 x 16 Parallel-ta-Serial CMOS FIFO ............................ S6-83
256 x 16,512 x 16, 1024 x 16 Parallel-ta-Serial CMOS FIFO ............................ S6-83
256 x 16,512 x 16, 1024 x 16 Parallel-ta-Serial CMOS FIFO ............................ S6-83
2048 x 9-Bit & 4096 x 9-Bit Parallel-ta-Serial CMOS FIFO (14-146) . ... . . .. .. .. . . . . .. ..... S6-95
2048 x 9-Bit & 4096 x 9-Bit Parallel-ta-Serial CMOS FIFO (14-146) ..... . . . . . . .. .. . . . . .. .. S6-95
2048 x 9-Bit Serial to Parallel CMOS FIFO (14-146) ................................... SS-109
2048 x 9-Bit Serial to Parallel CMOS FIFO (14-146) ................................... S6-109
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO ...................... '" .. . . ... .. S6-122
1024 x 18-Bit 512 x 18-Bit CMOS Synchronous FIFO. . ... . . ..... .... .. . .. . . . . . . . . . . . .. S6-122
64 x 4 FIFO with Output Enable ................................................... S6-123
64 x 5 FIFO with Output Enable................................. .................. S6-123
64 x 4 FIFO with Output Enable........................ ..... ...................... S6-123
64 x 5 FIFO with Output Enable...... ..... ....... ...... ............ ........ ....... S6-123
CMOS Parallel 64 x 5 FIFO (with Flags) ............................................. S6-134
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO .............................................. S6-145
1K x 18-Bit-2K x 9-Bit CMOS BiFIFO .............................................. S6-145
8K x 36 FIFO Module............... ......... ............... ..... ................ S13-76
36 to 9 BiFIFO Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S13-85
1K x 18-Bit CMOS BiFIFO ........... ........................ ..................... S6-165
fQ
lOT 7200S/L
IDT 7201 SA/LA
CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO
256 x 9-BIT & 512 x 9-BIT
Intesrated Device1echnology. Inc.
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory
The IDT7200/7201A are dual-port memories that utilize a special First-In/First-Out algorithm that loads and empties data on a
first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for
unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use
of the Write (W) and Read (R) pins. The devices have a read/write
cycle time of 35ns (28.5MHz).
The devices utilize a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking. It also features
a Retransmit (RT) capabili.!Y,that allows for reset of the read nnilnt""r _ _
to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
The IDT7200/1 A are fabricated using IDT's high-speed CEMOS
technology. They are designed for those applications requiring
asynchronous and simultaneous read/writes in multiprocessing
and rate buffer applications.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
• 256 X 9 organization (IDT7200)
• 512 x 9 organization (IDT7201A)
• Low power consumption
• Ultra high speed-35ns cycle time (28.5MHz)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• IDT7200 and IDT7201A are pin and functionally compatible with
Mostek MK4501, but with Half-Full Flag capability in single
device mode
• Master/Slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and Full warning flags
• Auto retransmit capability
• High-performance CEMOS ™ technology
• Available in plastic DIP, CERDIP, 300 mil THINDIP, LCC, PLCC
and Flatpack
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87531 is pending listing on
this function. Refer to Section 2/page 2-4.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
w
DATA INPUTS
(Do-Os)
Ds
D3
D2
D1
Vcc
D4
Ds
D6
D7
Do
IT/RT
Xl
FF
00
01
O2
03
Os
GND
0
Q otXla: ~ ~cJ~
I
I
L....I
I
I
~
I
I
L.....I
3 2
I I
II
I I
L...I
I I
L...J
J32-1
&
L32-1
XO/R"F
07
06
26
25
24
23
[:
[:
[:
[:
22 [:
21 [:
05
04
DIP/SOIC/FLATPACK
TOP VIEW
W
I I
L-.I
27 [:
AS
EF
R
I I
L...I
32 31 30
1
29 [:
28 [:
~~~~~~~
D6
D7
NC
FL/RT
RS
EF
XO/HF
07
06
W~fr
•
BUFFERS ..(J..
DATA OUTPUTS
(Oo-Oa)
R
OO@~~aO
CONSULT FACTORY FOR CERPACK PINOUT
(!J
t - - - - 1 - - . EF
LCC/PLCC
TOP VIEW
L.,..,;;~~I---t--Ft=
_-_...
.....
Xl-----.t
1-----. ><07Rl=
CEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
OSC-2000/1
1989 In1egrated Device Technology. Inc.
S6-1
---
-_
..
__.._.. ----.-.- .. - ••..
-.--------------~
IOT7200/7201A CMOS PARALLEL
FIRST·IN/FIRST-OUT FIFO 256x 9·BIT & 512 X 9·BIT
ABSOLUTE MAXIMUM RATINGS
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
(1)
RATING
COMMERCIAL
MILITARY
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55 to +125
TSTG
Storage
Temperature
-55 to +125
SYMBOL
-65 to + 135
-65 to +155
UNIT
SYMBOL
Input Leakage Current
(Any Input)
ILO (2)
5.5
V
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
'-"H
Input High
Voltage Commercial
2.0
-
-
V
'-"H
Input High
Voltage Military
2.2
-
-
V
Input Low
Voltage
Commercial
and Military
-
-
O.S
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
= SV ±
10%, TA
IDT7200S/L
I OT7201 SA/LA
MILITARY
tA
30,40n5
=
MAX.
=
MIN.
TYP.
MAX.
= -SSOCto
=
MIN.
-10
10
-
2.4
-
-
0.4
-
-
-
14d4)
-
-
20
10
jJA
10
jJA
-
2.4
-
-
V
-
0.4
-
-
0.4
V
-
50
SO
-
70
100
mA
-
5
S
-
S
15
mA
-1
Output Leakage Current
-10
-
10
-10
-
10
VOH
Output Logic "1" Voltage
10H = -2mA
2.4
-
-
2.4
-
VOL
Output Logic "0" Voltage
10L = SmA
-
-
0.4
-
lecl(3)
Active Power Supply Current
-
-
125(4)
-
-
15
= RS = FURT = \IH
MAX.
-10
10
=
UNIT
-
-
(R
MIN. TYP.
-10
-10
.
MAX.
=
1
1
A'yera~ Sta..!}9by £u~nt
TYP.
1DT7200S/L
I OT7201 SA/LA
MILITARY
tA
50,65,
80, 120n5
-
-
(3)
+ 12S°C)
IOT7200S/L
IOT7201 SA/LA
COMMERCIAL
tA
50,65,
80, 120n5
-1
lec2
UNIT
5.0
(1)
IL
+70°C; Military: \(;e
MIN. TYP.
IU(l)
MAX.
4.5
V.
10T7200S/L
IDT7201SA/LA
COMMERCIAL
tA
25,35n5
PARAMETER
SYMBOL
TYP.
Military
Supply Voltage
°C
DC ELECTRICAL CHARACTERISTICS
= S.OV ±10%, TA = O°Cto
MIN.
Vcc
°C
DC Output Current
50
50
mA
lOUT
NOTE:
.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
(Commercial: Vee
PARAMETER
lee3(L)(3)
Power Down Current
(All Input = Vec -0.2V)
-
-
500
-
-
900
-
-
500
-
-
900
jJA
I CC3(S)(3)
Power Down Current
(All Input == Vcc -0.2V)
-
-
5
-
-
9
-
-
5
-
-
9
mA
NOTES:
1. Measurements with O·.4~ V 1N ~ Vee.
2.
~"'H. 0.4 ~ VOUT~ \be
3. Icc measurements are made with outputs open.
4. Tested at f = 20 MHz.
R
S6-2
IDT7200/7201A CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 256 X 9·BIT & 512 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
= 5V ±1
1.
2.
3.
4.
5.
=OOCto +70 o C; Mil
Timings referenced as in AC Test Conditions.
Pulse widths less than minimum value are not allowed.
Values guaranteed by design, not currently tested.
Only applies to read data flow·through mode.
·x· in part rating indicates power rating (S/SA or LJLA).
S6-3
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
5V
GND to 3.0V
5ns
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
CIN
TO
OUTPUT
PIN
See Figure 1
68cn
30pF*
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
1.1K
1.5V
1.5V
CONDITIONS
Input Capacitance
VIN = OV
COUT
Output Capacitance
VOUT= OV
NOTE.
1. This parameter is sampled and not 100% tested.
MAX.
UNIT
8
pF
8
pF
Figure 1. Output Load
*Includes jig and scope capacitances.
pointer is blocked from R so external changes in
the FIFO when it is empty.
SIGNAL DESCRIPTIONS
INPUTS:
R will not affect
FIRST LOAD/RETRANSMIT (FLIRT)
DATA IN (Do-Da)
This is a dual-purpose input. In the Depth Expansion Mode, this
pin is grounded to indicate that it is the first loaded (see Operating
Modes). In the Single Device Mode, this pin acts as the retransmit
input. Th~ Single Device Mode is initiated by grounding the Expansion In (XI).
The IDT7200/7201A can be made to retransmit data when the
Retransmit enable control (RT) input is pulsed 10w.. A retransmit
operation will set the internal read pointer to the first location and
~I not affect the write pointer. Read enable (R) and Write enable
(W) must be in the high state during retransmit. This feature is useful when less than 256/512 writes are performed between resets.
The retransmit feature is not compatible with the Depth Expansion
Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers.
Data inputs for 9-bit wide data.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken
to a low state. During reset, both internal read and write pointers are
set to the first location. A reset is required after power up before a
write operation.,£an take place. Both the Read enable (R) and
Write enable (W) inputs must be in the high state during the
window shown in Figure 2, (i.e., tRSS before the rising edge of
RS) and should no~hange until tRsR after the rising ed~ of
RS. Half-Full Flag (HF) will be reset to high after Reset (RS).
EXPANSION IN (XI)
WRITE ENABLE (W)
This input Is a dual-purpose pin. Expansion In (XI) is grounded
tQjndicate an operation in the single device mode. Expansion In
(XI) is connected to Expansion Out (XO) of the previous device in
the Depth Expansion or Daisy Chain Mode.
A w!!!.e cycle is initiated on the fall ing edge of this input if the Full
Flag (FF) is not set. Data set-up and holdtimes must be adhered to
with respect to the rising edge of the Write enable (W). Data is
stored in the RAM array sequentially and independently of any ongoing read operation.
After half of the memory is filled and at the falling edge ofthe next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pointer and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is then reset by the rising edge of
the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read
operation, the Full Flag (FF) will go high aftertRFF, allowing a valid
write to begin:..YVhen the FIFO is full, th~nternal write pointer is
blocked from W, so external changes in W will not affect the FIFO
when it is full.
The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating
that the device is empty.
READ ENABLE (R)
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
A read cycle is initiated on the falling edge of the Read enable
(R) provided the Empty Flag (EF) is not set. The data is accessed
on a First-In/First-Out basis, independent of any ongoing write operations. After Read enable (R) goes high, the Data Outputs
(Oo-Oa) will return to a high impedance condition until the next
Read operation. When all the data has been read from the FI FO, the
Empty Flag (EF) will go low, allowing the "final" read cycle but inhibiting further read operations with the data outputs remaining in a
high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid
read can then begin. When the FIFO is empty, the internal read
This is a dual-purpose output. In the single device mode, when
Expansion In (XI) is grounded, this output acts as an indication of a
half-full memory.
After half of the memory is filled and at the falling edge of the next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pOinter and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is then reset by the rising edge of
the read operation.
In the Depth E~ansion Mode, Expansion In (Xi) is connected to
Expansion Out (XO) of the previous device. This output acts as a
OUTPUTS
FULL FLAG (FF)
The Full Flag (FF) will go low, Inhibiting further write operation,
when the write pointer is one location less than the read pointer,
indicating that the device is full. If the read pOinter is not moved after Reset (RS), the Full-Flag (FF) will go low after 256 writes forthe
IDT7200 and 512 writes for the IDT7201A.
EMPTY FLAG (EF)
S6-4
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST·OUT FIFO 256 X 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Data outputs for 9-bit wide da!.a. This data is in a high impedance condition whenever Read (R) is in a high state.
signal to the next device in the Daisy Chain by providing a pulse to
the next device when the previous device reaches the last location
of memory.
DATA OUTPUTS (Oo-Oa)
~-------------------------tRSC --------------------------~
w
NOTES:
1. EF. FF and HF may change status during Reset. but flags will be valid at t RSC '
2. IN and R = V1H around the rising edge of RS.
Figure 2. Reset
S6-5
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1 - - - - - tRc
----I~-tRpw
. . - tov
-I
DATAoUT VALID
):@(
.
tRHZ:-:::1
DATAoUT VALID
';(lj-----
I~-------twc-------~
I~----
t wpw ------!~
w
r,tos
-------~(
-D-A-T-A...;.IN-----)------«
DATAIN VALID
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
w
Figure 4. Full Flag From Last Write to First Read
LAST READ
DATAoUT
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
---t"ll~~~:!£)
Figure 5. Empty Flag From Last Read to First Write
S6-6
FIRST READ
)..----
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
....- - - - - - - - - - - - - t RTC
tRT
---------~-..j,...----+----
W."R"
NOTE:
1. EF. FF and
HF may change status during Retransmit. but flags will be valid at t RTC'
Figure 6. Retransmit
W
Figure 7. Empty Flag Timing
W
Figure S. Full Flag Timing
S6-7
----_.-------_._------- . - - - -
IDT7200/7201A CMOS PARALLEL
FIRST-INfFIRST-OUT FIFO 256 x 9-BIT & 512
x 9-BIT
HALF-FULL OR LESS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MORE THAN
HALF-FULL
HALF-FULL OR LESS
w
Figure 9. Half-Full Flag Timing
w
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
Figure 10. Expansion Out
t)(l ---~---
w
tXIR --~
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
Figure 11. Expansion In
S6-8
----------------------------------
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES·
trol in!?!:!.t is grounded (see Figure 12). In this mode the Half-FufJ
Flag .!!:!f), which is an active low output, is shared with Expansion
Out (XO).
OPERATING MODES
SINGLE DEVICE MODE
A single IDT720017201A may be used when the application
requirements are for 256/512 words or less. The IDT720017201A is
in a Single Device Configuration when the Expansion In (XI) con-
(fW)
HALF-FULL FLAG
WRITE
IDT
7201A
FULL FLAG
(a:) EMPTY FLAG
RESET
(J1r) RETRANSMIT
EXPANSION IN (Xl)
Figure 12. Block Diagram of Single 512x9 FIFO
WIDTH EXPANSION MODE
(EF ,FF and HF ) can be detected from anyone device. Figure 13
demonstrates an 18-bit word width by using two IDT7201 As.
Any word width can be attained by adding additional IDT7201As.
Word width may be increased simply by connecting the corresponding input control Signals of multiple devices. Status flags
(ti) READ
IDT
7201A
RESET----------~(~~)-.r
(E"F) EMPTY FLAG
(J1r) RETRANSMIT
(Q) DATAoUT
NOTE:
1. Flag detection is accomplished by monitoring the
connect any output control signals together.
FF. EF and the Hi= signals on either (any) device used in the width expansion configuration. Do not
Figure 13. Block Diagram of 512x18 FIFO Memory Used In Width ExpansIon Mode
S6-9
-------------------------------------------
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 X 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL :rEM PERATURE RANGES
each system, (I.e., FF is monitored on the device where W is used;
EF is monitored on the device where R is used). Both DepthEx~
pans ion and Width Expansion may be usedinthis mode.
DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted: a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 17), the FIFO permits the reading of a single word
after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tNns after the rising edge of W, called
the first write edge, and it remains on the bus until the R line is
raised from low-ta-high, after which the bus would go into a threestate mode after tRHZ ns. The EF line would have a pulse showing
temporary d~-assertion and then would be asserted. In the interval
of time that R is low, more words can be written to the FIFO (the
subsequent writes after the first write edge will de-assert the Empty
Flag); however, the same word (written on the first write edge) presented to the output bus as the read pointer, would not be incremented when R is low. On toggling R, the other words that are written to the FIFO will appear on the output bus as in the read cycle
timings.
In the write flow-through mode (Figure 18), the FI FO permits the
writing of a single word of da.!.a immediately after reading one word
of data from a full FIFO. The R line causes the FF to be de-asserted
butthe W line, being low, causes itto be asserted again in anticipation of a new data word. On the rising edge of W, the new word is
loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
For additional information refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech Note 6:
"Designing with FIFOs."
DEPTH EXPANSION (DAISY CHAIN) ~ODE
The IDT7200/7201A' can easily be adapted to applications
where the requirements are for greater than 256/512 words.
Figure 14 demonstrates Depth Expansion using three
IDT7200/720 1As. Any depth can be attained by adding additional
IDT7200/7201As. The IDT7200/7201A operates in the Depth Expansion configuration when the following conditions are met:
1. The first device must be designed by grounding the First Load
(FL.) control Input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full F~ (FF)
and Empty Flag (EF). This requires the ORing of all EFs and
ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion Mode.
For additional information refer to Tech Note 9: "Cascading
FIFOs or FIFO Modules".
COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 15).
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing IDT7200/7201As as shown in Figure 16. Care,'
must be taken to assure that the appropriate flag is monitored by
TABLE I-RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INTERNAL STATUS
INPUTS
MODE
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0,
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment (1)
Increment (1)
X
X
X
HF
NOTE.
1. Pointer will Increment if flag is high.
TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
INPUTS
MODE
INTERNAL STATUS
OUTPUTS
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
0
(1)
Location Zero
Location Zero
1
(1)
Location Zero
Location Zero
0
0
1
Reset All Other Devices
0
0
ReadtWrite
1
X
(1)
X
X
X
X
Reset First Device
NOTES:
Xi is connected to XC of previous device. See Figure 14.
Reset Input FLIRT First Load/Retransmit,
Empty Flag Output,
1
1.
Rs =
=
EF =
S6-10
FF= Full Flag Output, Xi = Expansion Input, HF = Half-Full Flag Output.
-----------------------
I DT7200/7201 A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT
W
0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1>«:>
9,
I
.I
J=F
9, ..
I
)
I
rr-v
~
ron:
-
t-
lOT
7201A
_
4~
l..-
J=F
9..L.A
I
AS
~
~
9-,
~
Q)
.I
-y!f
r;
r
Vee
H
~
9..LA
r-r4
I-.-
R"
~
~
r'-
...
EF'
K
,)
-
lOT
7201A
r:
J
~
r--
I-t--
I--
l-
~
lOT
7201A
I-to--
r~~
Figure 14. Block Diagram of 1536 x 9 FIFO Memory (Depth Expansion)
0 9 -0 17
0 0 -Os
0 9 -0 17
0 0 -Os
, W,11S
IDT7201A
DEPTH
EXPANSION
BLOCK
..e.
I0T720 1A
OEPTH
EXPANSION
BLOCK
;:.
....c::
Do -Os
•••
-I
r-
•••
;:.
0 9 -017
DIS -ON
• • • __
D....
{N_-S_l_-D_N--I
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13_
Figure 15, Compound FIFO Expansion
S6-11
IDT720 1A
DEPTH
EXPANSION
BLOCK
IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
14-----
'Fie
I-----t~. ~e
lOT
7201 A
t - - - - - - We
Oa
0-8
SYSTEM A
SYSTEM B
De
lOT
'Fi A - - - - - . ! 7201 A
0-8
14----- we
WA~----i
~A ~----I
1------ ~a
L..._ _....
Figure 16. Bidirectional FIFO Mode
w
DATA OUT
Figure 17. Read Data Flow-Through Mode
S6-12
IDT7200/7201A CMOS PARALLEL
FIR5T-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
DATA IN
VALID
I- t o s - I
~J
DATA OUT
- - - - - - - - - I m D A T A O U T VALID
)@_--------
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
XXXX
Devi e Type
A
Power
999
Speed
A
Package
A
Process!
Temperature
Range
y:'Mk
L-.._ _ _ _ _ _ _
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
SOIC
Plastic Dip
CERDIP
Sidebraze THINDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Plastic THINDIP
Cerpack
25
30
35
Commercial Only
Military Only
Commercial Only
Military Only
40
Access Time (tA)
Speed in Nanoseconds
50
65
80
120
~
________________________IISA
ILA
L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- (
* "A" to be included for 7201 ordering part number only.
56-13
+ 70°C)
SO
P
D
TC
__I J
L
TP
XE
L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Commercial (O°C to
7200
7201
Standard Power·
Low Power·
256 x 9-Bit FIFO
512 x 9-Bit FIFO
1
~
lOT 7202SA/LA
CMOS PARALLEL
FIRST-IN/FIRST-OUT
FIFO 1024 x 9-BIT
Integrated DevIce'Jechnology.Inc.
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory
The IDT7202A Is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-In/firstout basis. The device uses Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load and unload data. Data is toggled in and out of the device through the use
of the Write CN} and Read (R) pins. The device has a read/write cycle time of 35ns (28.5MHz).
The device utilizes a 9-blt wide data array to allow for control and
parity bits at the user's option. This feature Is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking. It also features
a Retransmit (RT) capabil~that allows for reset of the read pointer
to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
The IDT7202A is fabricated using IDT's high-speed CEMOS
technology. It Is designed for those applications requiring asynchronous and simultaneous read/writes In multiprocessing and
rate buffer applications. The 1024 x 9 organization of the IDT7202A
allows a 1024 deep word structure without the need for expansion.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
• 1024 x 9 organization
• Low power consumption
• Ultra high speed-35ns cycle time (28.5MHz)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin compatible with Mostek MK4501, but with Half-Full Flag
capability
• Allows for deep word structure (1024) without expansion
• Half-Full Flag capability In single device mode
• Master/Slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and Full warning flags
• Auto retransmit capability
• High-performance CEMOS ™ technology
• Available in Plastic DIP, CERDIP, 300 mil THINDIP, LCC, PLCC
and Flatpack
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATIONS
w
'Icc
08
03
04
05
D6
O2
Dl
Do
'5([
D7
~
'E'F"
W/R'F
00
01
07
06
05
O2
03
08
04
GND
~
DATA INPUTS
(D o-D 8 )
oa[3~~bO
INDEX
F"C/Jir
l='F'
FUNCTIONAL BLOCK DIAGRAM
W
ULJUiiUUU
4 3 2 ..... 3231 30
1
29
28
27
26
J32-1
25
J=1! :1 9
&
L32-1
24
0 0 :1 10
23
0 1 :1 11
22
NC :J 12
O2 :1 13 14 15 16 17 18 19 2021
r1r1nnr-:r-:r.
D2
Dl
Do
'5([
:J
:J
:J
:J
5
6
7
8
I:
I:
I:
D6
D7
NC
I: F"C/fIT
I: AS
I: 'E'F"
I: XO/i=W
I: 0 7
I: 0 6
1024"'-!1........10.01.~
THREESTATE
BUFFERS
DATA OUTPUTS
(0 0 -08 )
OO~~IC:Oo'"
01 P/SOIC/FLATPACK
TOP VIEW
.C!l
LCC/PLCC
TOP VIEW
t----I---'E'F"
J=1!
L...::':';;~l------t---
CONSULT FACTORY FOR CERPACK PINOUT
.....
J----- }m7H'F
_---'
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-2002/1
S6-14
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
(1)
RATING
COMMERCIAL
MILITARY
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
UNIT
TA
Operating
Temperature
o to +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Storage
Temperature
TSTG
-55 to + 125
-65 to +155
SYMBOL
V
°C
mA
DC Output Current
50
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
UNIT
Vee
Military
Supply Voltage
4.5
5.0
5.5
V
Vee
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
"'H
Input High
Voltage Commercial
2.0
-
-
V
"'H
Input High
Voltage Military
2.2
-
-
V
"'e
Input Low
Voltage
Commercial
and Military
-
-
O.S
V
1
)
PARAMETER
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc= S.OV ±10%, TA = OOCto +70°C; Military: Vcc = SV ± 10%, TA = -SSOCto + 12S°C)
SYMBOL
IDT7202SA/LA
COMMERCIAL
tA = 25, 35ns
PARAMETER
MIN. TYP.
IU(l)
Input Leakage Current
(Any Input)
ILo (2)
Output Leakage Current
VOH
VOL
MAX.
IDT7202SA/LA
MILITARY
tA = 30,40ns
MIN. TYP.
1
-10
-10
-
10
Output Logic "1" Voltage
10H = -2mA
2.4
-
Output Logic "0" Voltage
10L = SmA
-
-1
MAX.
IDT7202SA/LA
COMMERCIAL
tA
50,65,
80, 120ns
=
MIN. TYP.
MAX.
IDT7202SA/LA
MILITARY
tA
50,65,
80, 120ns
=
MIN. TYP.
-
-
10
-1
-
1
-10
-10
-
10
-10
-
10
-10
-
2.4
-
-
2.4
-
-
2.4
-
0.4
-
-
0.4
-
-
0.4
UNIT
MAX.
10
JlA
10
JlA
-
V
0.4
V
I
(3)
Active Power Supply Current
-
-
125<4)
-
-
14(4 )
-
50
SO
-
70
100
mA
I
(3)
A'yerage Sta.!}flby £u~nt
(R = W = RS = FLIRT = "IH
-
-
15
-
-
20
-
5
S
-
8
15
mA
(L)(3)
I
cc3
Power Down Current
(All Input = Vcc -0.2V)
-
-
500
-
-
900
-
-
500
-
-
900
JlA
Icc3 (S)(3)
Power Down Current
(All Input = Vcc -0.2V)
-
-
5
-
-
9
-
-
5
-
-
9
mA
CC1
CC2
NOTES:
1. Measurements with 0.4::5 V1N ::5VCC •
2. R 2:"'IH. 0.4::5 VoUT ::5 \be
3. Icc measurements are made with outputs open.
4. Tested at f = 20 MHz
S6-15
IDT7202SA/LA CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 1024 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
=
1.
2.
3.
4.
5.
SV ±10%, T
= OOC to + 70°C; Mi
Timings referenced as in AC Test Conditions.
Pulse widths less than minimum value are not allowed.
Values guaranteed by design, not currently tested.
Only applies to read data flow-through mode.
"x· in part rating indicates power rating (SA or LA).
S6-16
IDT7202SA/LA CMOS PARALLEL
: FIRST~IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
5V
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
1.1K
TO
OUTPUT
PIN
68m
30pF*
(TA= +25°C, f = 1.0MHz)
PARAM ETER (1)
SYMBOL
5ns
1.5V
1.5V
See Figure 1
C 1N
Input Capacitance
COUT
Output Capacitance
CONDITIONS
MAX.
UNIT
V1N = OV
8
pF
Vour= OV
8
pF
Figure 1. Output Load
NOTE:
1. This parameter is sampled and not 100% tested.
*Includes jig and scope capacitances.
pointer is blocked from R so external changes in
the FIFO when it is empty;
SIGNAL DESCRIPTIONS
INPUTS
R will not affect
FIRST LOAD/RETRANSMIT (FLIRT)
DATA IN (Do-Da) .
Data inputs for 9-bit wide data.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken
to a low state. During reset, both internal read and write pointers are'
set to the first location. A reset is required after power up before a
write operation,.£an take place. Both the Read Enable (R) and
Write Enable (W) inputs must be in the high state during the
window shown in Figure 2, (i.e., tRSS before the rising edge of
RS) and should no!,.2hange until tRSR after the rising ed~ of
RS. Half-Full Flag (HF) will be reset to high after Reset (RS).
This is a dual-purpose input. In the Depth Expansion Mode, this
. pin is grounded to indicate that it is the first loaded (see Operating
Modes). In the, Single Device Mode, this pin acts as the retransmit
input. The Single Device Mode is initiated by grounding the Expansion In (XI).
The IDT7202A can be ,made to retransmit data when the
Retransmit' Enable Control (RT) input is pulsed low. A retransmit
operation will set the internal read pointer to the first location and
will not affect the write pointer. Read Enable (R) and Write Enable
(W) must be in the high state during retransmit. This feature is useful when less than 1024 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion
Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers.
WRITE ENABLE (Vi )
E~PANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is grounded
t2., indicate an operation in the single device mode. Expansion In
(XI) is connected to Expansion Out (XO) of the previous device in
the Depth Expansion or Daisy Chain Mode.
A write cycle is initiated on the falling edge ofthis input if the Full
Flag (FF) is not set. Data set-up and hold times must be adhered to
with respect to the rising edge of the Write Enable (W). Data is
stored in the RAM array sequentially and independently of any ongoing read operation.
After half ofthe memory is fi lied and atthe falling edge of the next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pOinter and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is then reset by the rising edge of
the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read
operation, the Full Flag (FF) will go high after tRFF, allowing a valid
write to begin. When the FIFO is full, the internal write pointer is
blocked from W, so external changes in Wwill not affect the FIFO
when it is full.
OUTPUTS
FULL FLAG (FF)
The Full Flag (FF) will go low, inhibiting further write operation,
when the write pOinter is one location less than the read pointer,
indicating that the device is full. If the read pOinter is not moved after Reset (RS), the Full-flag (FF) will go low after 1024 writes.
EMPTY FLAG (EF)
The Empty Flag (EF) will go low, inhibiting further read operations, when the read pOinter is equal to the write pointer, indicating
that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (Xb/HF)
READ ENABLE (R)
This is a dual-purpose output. In the single device mode, when
Expansion In (XI) is grounded, this output acts as an indication of a
half-full memory.
After half of the memory is filled and althe falling edge of the next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pointer and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is then reset by the rising edge of
the read operation.
In the Depth ~ansion Mode, Expansion In (XI) is connected to
Expansion Out (XO) of the previous device. This output acts as a
signal to the next device in the Daisy Chain by providing a pulse to
A read cycle is initiated on the falling edge of the Read Enable
(R) provided the Empty Flag (EF) is not set. The data is accessed
on a First-In/First-Out baSis, independent of any ongoing write operations. After Read Enable (R) goes high, the Data Outputs
(00-08) will return to a high impedance condition until the next
Read operation. When all the data has been read from the FIFO, the
Empty Flag (EF) will go low, allowing the "final" read cycle but inhibiting further read operations with the data outputs remaining in a
high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high aftertwEFand a valid
Read can then begin. When the FIFO is empty, the internal read
S6-17
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
the next device when the previous device reaches the last location
of memory ..
Data outputs for 9-blt wide data. This data is in a high impedance condition whenever Read (R) is In a high state.
DATA OUTPUTS (00 -Os)
~------------------------------------tRSC ------------------------------------~
w
NOTES:
1. EF. FF and H'Fmay change status during Reset. but flags will be valid at t RSC '
2. Iii and R = V1H around the rising edge of RS.
Figure 2. Reset
S6-18
JDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO. 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
,.-----tRc
-----I~-
t RPW
___" , _ tA
-
tDv-1
DATAoUT VALID .
tRHZ
=I
~ DATAoUT VALID. )00-----
I~-------twc--------~
, . - - - - - t wpw - - - - . (
w
t;=
---------C(
t DS
-D-AT-A-1;..N-----,.)------«
DATAIN VALID
)>----
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
w
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
w
DATAOUT
---1~t-~~@~~
Figure 5. Empty Flag From Last Read to First Write
S6-19
._-----_._--_ ..
_--_ __._._------_. . - - - - - - - - - - - - - - - - - - ...
__
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1 - - - - - - - - - - - - - - t RTC
W.l1
FLAG VALID
NOTES:
1.
EF. FF and RF may change status during Retransmit. but flags will be valid at t RTC '
Figure 6. Retransmit
W
Figure 7. Empty Flag Timing
W
Figure S. Full Flag Timing
S6-20
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HALF-FULL OR LESS
MORE THAN
HALF-FULL
HALF-FULL OR LESS
w
Figure 9. Half-Full Flag Timing
w
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
Figure 10. Expansion Out
14-0--- tXI
w
---+---- tXIR --~
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
Figure 11. Expansion In
S6-21
-------------- -- - - _..----_._--
IDT7202SA/LA CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 1024 X 9·BIT
MILITARY AND COMMERCIALTEMPERATURE RANGES
grounded (see Figure 12). In this mode the Half·Fuli Flag .!!::!f).
which is an active low output. is shared with Expansion Out (XO).
OPERATING MODES
SINGLE DEVICE MODE
A single IDT7202A may be used when the application requirements are for 1024 words or less. The IDT7202A is in a Single Device Configuration when the Expansion In (xl) control input is
fW
(HALF-FULL FLAG)
WRITE
lOT
7202A'
FULL FLAG
(l!r)
RESET
(~S)
(~) EMPTY FLAG
(Fir) RETRANSMIT
EXPANSION IN QU)
-=
Figure 12. Block Diagram of Single 1024x 9 FIFO
WIDTH EXPANSION MODE
(EF .FF and HF ) can be detected from anyone device. Figure 13
demonstrates an 18-bit word width by using two IDT7202As. Any
word width can be attained by adding additional IDT7202s.
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags
(R") READ
RESET
lOT
7202A
--------1(AS)
(rr) EMPTY FLAG
(FIT) RETRANSMIT
-=
NOTE:
1. Flag detection is accomplished by monitoring the FF.
connect any output control signals together.
(0) DATAoUT
EF and the HF signals on either (any) device used in the width expansion configuration. Do not
Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used In Width expansion Mode
S6-22
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
system (Le., FF is monitored on the device where W is used; EF is
monitored on the device where R is used). Both Depth Expansion
and Width Expansion may be used in this mode.
DATA FLOW·THROUGH MODES
Two types of flow-through modes are permitted: a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 17), the FIFO permits the reading of a single word
after writing one word of data into an empty FIFO. The data is enabled on the bus in {twEF + tA)ns after the rising edge of W, called
the first write edge, and it remains on the bus until the R line is
raised from low-to-high, after which the bus would go into a threestate mode after tRHz ns. The EF line would have a pulse showing
temporary de-assertion and then would be asserted. In the interval
of time that R is low, more words can be written to the FIFO (the
subsequent writes after the first write edge will de-assert the Empty
Flag); however, the same word (written on the first write edge) presented to the output bus as the read pointer, would not be incremented when R was low. On toggling R, the other words that are
written to the FI FO will appear on the output bus as in the read cycle
timings.
In the write flow-through mode (Figure 18), the FIFO permits the
writing of a single word of da.!.a immediately after reading one word
of data from a full FIFO. The R line causes the FF to be de-asserted
but the W line, being low, causes it to be asserte..Q.again in anticipation of a new data word. On the rising edge of W, the new word is
loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
For additional information refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech Note 6:
"Designing with FIFOs".
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7202A can easily be adapted to applications where the
requirements are for greater than 1024 words. Figure 14 demonstrates Depth Expansion using three IDT7202As. Any depth can be
attained by adding additionaIIDT7202As. The IDT7202As operate
in the Depth Expansion configuration when the following conditions are met:
1. The first device must be designed by grounding the First Load
(FL.) control input.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full F.!gg (FF)
and Empty Flag (EF). This requires the ORing of all EFs and
ORing of all FFs (Le. all must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion Mode.
For additional information refer to Tech Note 9: "Cascading
FIFOs or FIFO Modules".
COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 15).
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing IDT7202As as shown in Figure 16. Care must
be taken to assure that the appropriate flag is monitored by each
TABLE 1- RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUTS
MODE
INTERNAL STATUS
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment (1)
Increment (1)
X
X
X
HF
NOTES.
1. Pointer will increment if flag is high.
TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
INPUTS
MODE
OUTPUTS
FL
XI
Read Pointer
Write Pointer
EF
FF
0
(1)
Location Zero
Location Zero
1
(1)
Location Zero
Location Zero
0
0
1
Reset All Other Devices
0
0
Read/Write
1
X
(1)
X
X
X
X
Reset First Device
NOTES:
Xi is connected to
As = Reset Input
1.
INTERNAL STATUS
RS
Xc of previous device. See Figure 14.
1
FURT = First Load/Retransmit. EF = Empty Flag Output. FF = Full Flag Output. Xi = Expansion Input, HF = Half-Full Flag Output.
S6-23
----------,,-------
----
[II
I
1DT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D
rorr
1m
-T
w
9.
I
...
1=F
~
.
I
T-y
IDT
7202A
\
I
T-y
----....
'--
J!F'
9.LA
'---
J1S"
.r.
-
'-
..
9.
I
.
~
Q)
F
Vee
,X:
~
~
{
'R
f4--
boo
---...
-T
~
}
~
f--
IDT
7202A
r:
IDT
7202A
--1
r-IT-
j
J
r-~
f--
-~
-
f--
r!E~
'-
r~
Figure 14. Block Diagram of 3072 x 9 FI FO Memory (Depth expansion)
0 0 -Qs
00
.W.~
Og -Q 17
•••
Qg -017
-Q s
IDT7202A
DEPTH
EXPANSION
BLOCK
IDT7202A
DEPTH
EXPANSION
BLOCK
..:. ,. ..... :::....
..:. ,. ..... ;::..
Do -Ds
f--
•••
IDT7202A
DEPTH
EXPANSION
BLOCK
Dg -D17
_ _ _D.::o_-_D_N~_ _ _ _ _ _ _ _
D::.g_-D....;.;.N_ _ _ _ _D..:1.::,s_-_D;,;.N_
• ••
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO expansion
S6-24
D(N-S) -DN
IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~B
WA
U B
FFA
,
IDT
7202A
FWB
t...
DA 0-8
OB 0-8
I
y
SYSTEM A
SYSTEM B
Ii
I(
0A 0-8
IDT
7202A
RA
DB 0-8
~
WB
HFA
EFA
"FF=B
Figure 16. Bidirectional FIFO Mode
W
DATA OUT
Figure 17. Read Data Flow-Through Mode
S6-25
, - - - - - - - - -----------_._-,--
IDT7202SAlLA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
DATA IN
VALID
DATA OUT
I
-tos-I
~J
-------~~DATAOUT VALID ~--------Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
999
Speed
A
Package
A
Process/
Temperature
Range
y:'Mk
SO
P
o
TC
--I J
L
TP
XE
L--_ _ _ _ _ _ _
~
____________________
25
30
35
~40
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
SOIC
Plastic Dip
CERDIP
Sidebraze THINDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Plastic THINDIP
Cerpack
Commercial Only
Military Only
Commercial Only
Military Only
Access Time (tA)
Speed in Nanoseconds
50
65
}
80
120
~
______________________~ISA
ILA
"'"-----------------------------------------1 7202
S6-26
Standard Power
Low Power
1024 x 9-Bit FIFO
CMOS PARALLEL
Intesrated Device1ecJmolosy.1nc.
FLAGGED FIFO WITH DE
1K x 9, 2K x 9, 4K x 9
lOT 72021
lOT 72031
lOT 72041
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory
• Bit organization
- IDT72021-1Kx9
- IDT72031 -2K x 9
- IDT72041 -4K x 9
• Ultra high speed
- IDT72021 -25ns access time, 35ns cycle time
- IDT72031 -35ns access time, 45ns cycle time
- IDT72041 -35ns access time, 45ns cycle time
• Low power CMOS
• Easily expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Functionally equivalent to IDT7202103/04 with Output Enable
(OE) and Almost Empty/Almost Full Flag (AEF)
• Four status flags: Full, Empty, Half-Full (single device mode),
and Almost-Empty/Almost-Full (7/8 empty or 7/8 full in single
device mode)
• Output Enable controls the data output port
• Auto-retransmit capability
• Available in 32-pin DIP and surface mount 32-pin LCC and
PLCC
• Military product compliant to MIL-STD-883, Class B
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs(First-ln/First-Out).
Data can be written into and read from the memory at independent
rates. The order of Information stored and extracted does not
change, but the rate of data entering the FIFO might be different
than the rate leaving the FIFO. Unlike a static RAM, no address information is required because the read and write pointers advance
sequentially. The IDT72021/031/041s can perform asynchronous
and simultaneous read and write operations. There are four status
flags (HF, FF, E~AEF) to monitor data overflow and underflow.
Output Enable (OE) is provided to control the flow oJ..data throu.9h
the output port. Additional k~ features are Wri~ (W), Read (R),
Retransmit (RT), First Load (FL), Expansion In (XI) and Expansion
Out (XO). The IDT72021/031/04 1s are designed for those applications requiring data control flags and Output Enable (OE) in mUltiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using lOT's highperformance CEMOS™ technology. Military grade product is
manufactured in compliance with the latest revision of MILSTD-883, Class B, for high reliability systems.
FUNCTIONAL BLOCK DIAGRAM
w
1------ "5<07FfF
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 In1egrated Device Technology, Inc.
0SC-2OO3/-2
S6-27
- - - - . _ - - _......
__ __._---_ __
....
JANUARY 1989
..
..•
[II
I
ID172021/031/041 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
Vcc
Vcc
W
D6
D3
D2
D1
Do
ULJUIIULJLJ
3 2 U 32 31 30
D4
D5
D6
4
D2 :1 5
D7
Do :1 7
D1
"FL/tIT
AS
m
m :J
AEF" :J
'O"E"
IT
AU
"F"F
00
:J
29 [:
D7
6
J32-1
&
L32-1
9
'O"E"
IT
RO/RF
07
11
O2 :1 13
14 15 16
05
04
R
GND
D6
"FLIRT
AS
0 1 :1 12
07
06
O2
03
06
GND
1
6
Fl= :1 10
xc/Rl!!·
00
01
:J
17 16 19 20
r-1
r-1
r-1
r-I
I
I
I
1'1
I
I
d' 0'"
I
,...,,....,
I
'"
06
r-.
I
~ ~ Ia: O~ 00()
CJ CJ
LCC/PLCC
PINOUT
DIP
TOP VIEW
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
I/O
DO-D8
Inputs
I
Data inputs for 9-bit wide data.
AS
Reset
I
When RS is set low. internal READ and WRITE pointers are set to the first location of the RAM array. fW and f!F" go
high. and AEF and EF go low. A reset is required before an initial WRITE after power-up. Rand W must be high
during 115 cycle.
W
Write
I
When WRITE is low. data can be written into the RAM array sequentially. independent of READ. In order for WRITE to
be active. "F"F must be high. When the FIFO is full (t=l=-Iow). the internal WRITE operation is blocked.
R
Read
I
When READ is low. data can be read from the RAM array sequentially. independent of WRITE. In order for READ to
be active. EF must be high. When the FIFO is empty (EF-Iow). the internal READ operation is blocked. 00-08
are in a high impedance condition.
IT/~T
First Load/
Retransmit
I
This is a dual purpose input. In the single device configuration
grounded). activating retransmit ("FLIRT-low)
will set the internal READ pOinter to the first location. There is no effect on the WRITE pOinter. Rand W must be
high before setting IT/RT low. Retransmit is not compatible with depth expansion. In the depth expansion
configuration. IT/RT-Iow indicates the first activated device.
m
Expansion In
I
In the single device configuration. XI is grounded. In depth expansion or daisy chain expansion.
to XC (expansion out) of the previous device.
rn=
Output Enable
I
When "()"E" is set low. the parallel output buffers receive data from the RAM array. When DE: is set high. parallel threestate buffers inhibit data flow.
1=F
Full Flag
0
When Fl= goes low. the device is full and further WRITE operations are inhibited. When ff is high. the device is not
full.
EF
Empty Flag
0
When EF goes low. the device is empty and further READ operations are inhibited. When EF is high. the device is
not empty.
~
Almost-Emptyl
Almost-Full Flag
0
When AEF" is low. the device is empty to 1/8 full or 7/8 to completely full. When AE"F is high. the device is greater
than 1/8 full. but less than 7/8 full.
XC/FW
Expansion OuV
Half-Full Flag
0
This is dual purpose output. In the single device configuration
grounded). the device is more than half full when
HF is low. In the depth expansion configuration (RO connected to ofthe next device). a pulse is sent from )(Q to
when the last location in the RAM array is filled.
Outputs
0
00 - 08
(m
(m
m
Data outputs for 9-bit wide data.
STATUS FLAGS
NUMBER OF WORDS
IN FIFO
lK
2K
4K
0
1-127
128-512
513-896
897-1023
1024
0
1-255
256-1024
1025-1792
1793-2047
2048
0
1-511
512-2048
2049-3584
3585-4095
4096
FF
AEF
HF
EF
H
H
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
L
H
H
H
H
H
S6-28
m
mis connected
10T72021/031/041 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO WITH FLAGS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
SYMBOL
MIN;
TYP.
MAX.
UNIT
-0.5 to +7.0
-0.5to +7.0
V
VCCM
Military Supply
Voltage
4.5
5.0
5.5
V
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
lOUT
DC Output Current
-55 to +125
-65 to +155
°C
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PARAMETER
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
Vll (l)
Input Low Voltage
Commercial &
Military
-
-
0.8
V
.,
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS -IDT72021
(Commercial: Vcc= 5.0V ±10%. TA = OOC to +70 o C; Military: Vcc= 5V ± 10%. TA = -55°C to +125°C)
SYMBOL
IOT72021
COMMERCIAL
tA
25,35ns
PARAMETER
IOT72021
MILITARY
tA
30,40ns
=
MIN. TYP.
lu(l)
Input Leakage Current
(Any Input)
-1
ILO (2)
Output Leakage Current
VOH
VOL
=
MAX.
MIN. TYP.
MAX.
1
-10
-10
-
10
Output Logic "1" Voltage
10H = -2mA
2.4
-
-
<::b::)::::::::.:.':i·o
2A:,··'·':~p.;;:::'::':· ..:.......:;::;::..
Output Logic ·0" Voltage
IOl = 8mA
-
-
0'1\,;':
I
(3)
CC1
Active Power Supply Current
-
-
.: :. .----
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
w
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
Figure 4. Full Flag From Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
w
DATAOUT---t-1-~~~~~~-1_--------+_----_+-~~~~~
Figure 5. Empty Flag From Last Read to First Write
S6-46
IDT7203/IDT7204 CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 2048 x 9·BIT & 4096
x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1....
- - - - - - - - - - - - - t RTC
tRT
-----------.1 , ____-+_ _ __
W.R
FLAG VALID
NOTE:
1. 1:F.
F1! and RF may change status during Retransmit. but flags will be valid at t RTO
Figure 6. Retransmit
W
Figure 7. Empty Flag Timing
W
Figure 8. Full Flag Timing
S6-47
- - - - - - - - - - - - - - - - - - - _ . _ _-_... _ - _ . _ - - - - - - - - - - - - - - - - - - - - - - - - - - ..
1DT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-81T & 4096
x 9-81T
HALF-FULL OR LESS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MORE THAN HALF-FULL
HALF-FULL OR LESS
w
Figure 9. Half-Full Flag Timing
w
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
Figure 10. Expansion Out
14----
w
tXI
--_-1+---- tXIR - - - - . t
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
Figure 11. Expansion In
S6-48
1017203/IOT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 X 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
in a Single Oevice Configuration when the Expansion In (xi) control ine!:!! is grounded (see Figure 10). In this mode, the Half-Full
Flag llif), which is an active low output, is shared with Expansion
Out (XO).
OPERATING MODES:
SINGLE DEVICE MODE
A single 1017203/7204 may be used when the application requirements are for 2048/4096 words or less. The 1017203/7204 are
(HALF-FULL FLAG)
WRITE
DATA IN
IDT
7203/04
(EF) EMPTY FLAG
FULL FLAG
RESET
(Ai) RETRANSMIT
EXPANSION IN (Xl)
Figure 12. Block Diagram of Single 2048 x 9/4096 x 9 FIFO
WIDTH EXPANSION MODE
Word width ma.y be increased simply by connecting the corres.ES!nding input control signals of multiple devices. Status flags
(EF, FF and HF) can be detected from anyone device. Figure 13
demonstrates an 18-bit word width by using two 1017203/72045.
Any word width can be attained by adding additional
1017203/7204s.
DATA IN (D)
(Fl) READ
lOT·
(EF) EMPTY FLAG
7203/72041-------.-.
...
FUt-L_L_F_LA_G_ _....:...........:...._ _-I720'fJ204
RESET _ _---..:.(_RS--')_ _--.l1-
(liT) RETRANSMIT
(0) DATA OUT
NOTE:
Flag detection Is accomplished by monitoring the w,E"F and RF signals on either (any) device used In the width expansion configuration. Do not connect any
output control signals tog,ether.
Figure 13. Block Diagram of 2048 x 18/4096 x 18 FIFO Memory Used In Width Expansion Mode
S6-49
1DT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
must be taken to assure that the appropriate flag is monitored by
each systems (i.e. FF is monitored on the device wtlere W is used;
EF is monitored on the device where R Is used). Both Depth Expansion and Width Expansion may be used in this mode.
DATA FLOW-THROUGH MODES
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7203/7204 can easily be adapted to applications when
the requirements are for greater than 2048/4906 words. Figure 14
demonstrates Depth Expansion using three IDT7203/7204s. Any
depth can be attained by adding additional IDT7203/7204. The
IDT7203/7204 operates In the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the First Load
(Fl.) control input.
2. All other devices must have
Two types of flow-through modes are permitted, a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 17), the FIFO permits a reading of a single word after
writing one word of data into an empty FIFO. The data is enabled
onthe bus in (tWEF + tAl ns after the rising edgeofW, called the first
write edge, and it remains on the bus until the R line is raised from
low-to-high, after which the bus would go into a three-state mode
after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted. In the interval of time that
R was low, more words can be written to the FIFO (the subsequent
writes after the first write edge will deassert the empty flag); however, the same word (written on the first write edge), presented to
the output bus as the read pointer, would not be incremented when
R is low. On toggling R, the other words that welre written to the
FIFO will appear on the output bus as In the read cycle timings.
In the write flow-through mode (Figure 18), the FIFO permits the
writing of a single word of data immediately after reading one word
of data from a full FIFO. The R line causes the FF to be deasserted
but the W line being low causes it to be asserted again in anticipation of a new data word. On the riSing edge ofW, the new word is
loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data In the FIFO and to increment the write
pointer.
For additional information, refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech Note 6:
"Designing with FIFOs".
FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (Xi) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full ~ (FF)
and Empty Flag (EF). This requires the ORing of all EFs and
ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: "Cascading
FIFOs or FIFO Modules".
COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 15).
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing IDT7203/7204s as shown in Figure 16. Care
TRUTH TABLES
TABLE I-RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/wIDTH EXPANSION MODE
INPUTS
MODE
Reset
Retransmit
Read/Write
INTERNAL STATUS
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
0
1
Location Zero
Location Zero
Increment(1)
Location Zero
Unchanged
Increment(1 )
0
X
X
1
1
0
0
0
1
1
X
0
X
X
X
X
HF
NOTE:
1. Pointer will Increment if flag is high ..
TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
MODE
Reset First Device
Reset all Other Devices
Read/Write
INPUTS
INTERNAL STATUS
OUTPUTS
AS'
FL
XI
Read Pointer
Write Pointer
EF
FF
0
0
0
(1)
1
(1)
1
X
(1)
X
Location Zero
Location Zero
X
0
1
Location Zero
Location Zero
NOTE:
1. Xi is connected to XO of previous device. See Figure 12.
RS = Reset Input. FLiRT = First Load/Retransmit. EF = Empty Flag Output. FF
S6-50.
()
1
X
X
= Full Flag Output. Xi = ExpanSion Input. HF' = Half-Full Flag Output
1DT7203/1DT7204 CMOS PARALLEL
FIRST-INjFIRST-OUT FIFO 2048 x 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
D
...
Fi=
9,
.I
I
9, L
I
I
"T-y
~
....
~-
I:
IDT
7203/04
g,L
-
I
T-y
~
...
-
FF
-
9il.
I
'RS
-
J. _..!.
Figure 14. Block Diagram of 6,144
00
IDT720317204
DEPTH
EXPANSION
BLOCK
r
Vee
-.....
[-i
r-E-
.
~
~
1-1--
~
-
e
_\
.: J
~
nusT'Y
-...
W
r--=IDT
7203/04 I - I---
r~
x 9/12,288 x 9
FIFO Memory (Depth Expansion)
Og -017
-Os
0 0 -Os
R.W.AS
.
0)
I
~
~
~
IDT
7203/04
R
9.
t:
"F"F-
\~
-
~
~
roo:
Iw
•••
O(N-S)-ON
Og -017
IDT7203/04
DEPTH
EXPANSION
BLOCK
O(N-S)-ON
•••
_ _ _D.::.o_-_D~N_·_ _ _ _ _ _ _ _
D:.,9_-_D:.:.,N_ _ _ _....:.::...-:.:._ • • •
IDT7203/04
DEPTH
EXPANSION
BLOCK
D(N-S)-DN
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure.15. Compound FIFO Expansion
S6-51
- - - - - - - - - _ . _.. _._---------_. . _ - - - - _._.... _----_.. _-_ .._.._ - - - - _ . _ - - - - - - - - - - - - - - -
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096
x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-
...
WA
-..,
FFA
DA
0-8
,
~
.....
IDT
7203/04
0e
V
'Fi"e
~e
FIFe
0-8
SYSTEM B
SYSTEM A
A
0A
'Fi"A
FWA
~A
I(
0-8
----
...
IDT
7203/04
De
0-8
'i
--
We
...
-
~
Figure 16. Bidirectional FIFO Mode
W
DATA OUT
Figure 17. Read Data Flow-Through Mode
S6-52
FFe
IOT7203/IOT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-81T & 4096 X 9-81T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
. DATA IN
VALID
I- t o s - I
~J
~ATAOIJfVAUD';I:!ll;)--------
- - . . ; . . . - - - -.....
DATAoUT
Figure 18, Write Data Flow-Through Mode
ORDERING INFORMATION
IDT
xxxx
999
Speed
Device Type
A
A
Package
Process/
Temperature
Range
y:~nk
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
L -______________
~
XE
P
D
J
L
L-.---------------i
~
35 Com'l onlY}
40 Mil Only
50
Access Time (tA)
65
Speed in Nanoseconds
80
120
____~~____________~Is
IL
L-__________________________________
Cerpack
Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
~7203
7204
Standard Power
Low Power
2048 x 9-Bit FIFO
4096 x 9-Bit FIFO
S6-53
...
__.._._._--_._.------_ .._... ..
....................
_......._---_.---------------------------------
t;)
Intesrated Devlce1echnology.1nc.
ADVANCE
INFORMATION
lOT 72804
BiCMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO
4K x 9-BIT
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT72B04 is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/firstout basis. The device uses Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load and unload data. Data is toggled in and out of the device through the use
of the WRITE (IN) and READ (R) pins. The device has a read/write
cycle time of 25ns (40MHz).
The device utilizes a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking. It also features
a RETRANSMIT (RT) capability that allows for reset of the read
pointer to its initial poSition, when AT is pulsed low, to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes.
The IDT72B04 is fabricated using IDT's high-speed BiCEMOS
sub-micron technology. It is designed for those applications
requiring asynchronous and simultaneous read/writes in mUltiprocessing and rate buffer applications. The 4K x 9 organization
allows a 4096 deep word structure without the need for expansion.
Military grade product is manufactured In compliance with the
latest revision of MIL-STD-883, Class B.
First-In/First-Out dual-port memory
4K x 9-bit organization
Low power consumption
Ultra high speed: 15ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin-compatible with IDT7200/01/02/03/04 FIFO family
Half-Full Flag capability in single device mode
MASTER/SLAVE multiprocessing applications
Bidirectional and rate buffer applications
Empty and Full warning flags
Auto retransmit capability
High-performance submicron BiCEMOS ™technology
Available in 28-pin plastic DIP, CERDIP and 32-pin surface
mount LCC and PLCC
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DATA OUTPUTS
w
Vcc
Da
D3
D2
D4
D5
D6
Dl
Do
D7
: (D o,..D 8 )
INDEX
FL/~i
m
tfS
U
~
00
'5!nOICC .... LO
O>!n z
00
0z
~
LCC/PLCC
TOP VIEW
1-----+---. U
L...:.~;....J----r---~
L...-_ _- - I I - - - - - - .
'58 0... 0'"
00
£:
£:
£:
£:
£:
£:
£:
£:
£:
De
07
NC
mlir
~
~
XC57FW
07
De
1~~~ mrriTT-rrl
W~fr
•
BUFFERS
...(J.
DATA OUTPUTS
(0 0 -0 8 )
oo~~~ao
0'
z
~
1-----+--_ "EF'
~~~r----+--~'FJ=
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-2006/-
86-56
lOT 72103
lOT 72104
CMOS PARALLEL-SERIAL
FIFO 2048 x 9-BIT
& 4096 x 9-BIT
t;)
Integrated DevIceTechnoIogy.Inc.
FEATURES:
DESCRIPTION:
• 35ns parallel port access time
• 50MHz serial input/output port frequency
• Serial-to-Parallel, Parallel-to-Serial, Serial-to-Serial and
Parallel-to-Parallel operations
• Easily expandable in depth and width
• Programmable wordlengths from 4 bits to any bit width using
Flexishift ™ for serial operations without using any additional
components
• Multiple status flags: Full, Almost-Full (1/8 from full), Full-MinusOne, Empty, Almost-Empty (1/8 from empty), Empty-Plus-One
and Half-Full
• Asynchronous and simultaneous read and write operations
• Dual-ported zero fall-through time architecture
• Output enable control provided for parallel output port
• Retransmit capability in single device mode
• High-performance CEMOS ™ technology
• Available in 40-pin ceramic and plastic DIP, 44-pin LCC and
J-Leaded PLCC
• Military product compliant to MIL-STO-883, Class B
The 10172103/72104 are high-speed Parallel-Serial FIFOs that
are ideally suited for serial communications, high-density media
storage and local area networks.
The devices have four ports: two 9-bit parallel ports and the
other two for serial input and serial output. A variety of operations
can be performed: Serial-to-Parallel, Parallel-to-Serial, Serial-toSerial and Parallel-to-Parallel. The Parallel-Serial FIFOs can expand in depth or width for any of these modes.
A unique feature that enhances the bandwidth is the handling of
serial word lengths that are not a multiple of 9. The 10172103/72104
can be configured to handle serial word lengths from 4 bits to words
of any length using multiple devices. This feature is provided without using any additionallCs. For example, a user-can configure a
4K x 24 FIFO by using three devices to generate internal increments to the read/write pointers every 24 cycles.
A number of flags are provided to monitor the status of the FIFO.
These include Full, Almost-Full (when the FIFO is more than 7/8
full), Full-Minus-One (when the FIFO has one or zero locations left),
Empty, Almost-Empty (when the FIFO is less than 1/8 full), EmptyPlus-One (when there is only one or zero samples left in the FIFO)
and Half-Full.
Read and Write controls are provided to permit asynchronous
and simultaneous operations. An Output Enable control is provided on the parallel output port. Expansion control pins XO and
Xi are provided to allow cascading for deeper FIFOs.
The 10172103/72104 are manufactured using lOT's CEMOS
technology. Military grade product is manufactured in compliance
with the latest revision of MIL-STO-883, Class B.
APPLICATIONS:
•
•
•
•
•
•
•
•
High-Speed Data Acquisition Systems
Local Area Network Buffers
Remote Telemetry Buffers
Serial Link Buffers
High-Speed Parallel Bus-to-Bus Serial Communications
Magnetic Media Controllers
Single Chip Video Frame Buffers
FAX/Printer Buffers
FUNCTIONAL BLOCK DIAGRAM
SICP
DATA INPUTS
(Do-Os)
SIX -----.r----IIS~E~R;';'IA;:;L:-I~N~P;-;UT;---'
SERIAL INPUT -----~
CIRCUITRY
~/PI -----~~S~E~R~IA~U~P~A~R~A~LL~E~L~:r~~~~~
SO/PO -----~
CONTROL
w -----~
POINTER
~==~
WRITE
r
--.1-!
EXPANSION
LOGIC
!L ~
FLAG
LOGIC
!-=2:..r-__~ 'EMPTY / FU[[
t----'--. ALMOST -EMPTY/FULL
~==:t----- HALF-FULL
....----'R
IT/~ =:IL._____EO_ES_GE_16____.......
Xi
r-----~12~--. ~~~1~+1
SOCP
+
XC
OUTPUT ENABLE
(OE)
SERIAL OUTPUT
CIRCUITRY
SOX
SERIAL OUTPUT
DATA OUTPUTS
(Oo-Os)
CEMOS and Flexishift are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-2009/-1
19S9 Inlegrated Device Technology, Inc.
S6-57
IOT721 03/10172104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
c
t5 cr C'C' O'S: >8rfc ocfD
fD
INDEX
SOCP
sox
"STI"/PO
'5-
FULL
FLAG
SER IALDATA OUT
Figure 13. A 3K x 32 Parallel-to-Serlal FIFO using the IDT72125
ORDERING INFORMATION
IDT
xxxxx
999
A
D6viceType
Speed
Package
L...-._ _
~
____
~
Plastic THINDIP (300mil)
Sidebraze THINDIP (300mil)
Small Outline (Gull Wing)
TP
TC
SO
L...-.--------------i
L...-.----------------------i
S6-94
25
50
80
120
'W
(50MHz
(40MHz
(28MHz
(25MHz
serial
serial
serial
serial
shift rate)
shift rate)
shift rate)
shift rate)
1
Parallel Access lime (tA)
L
Lew Pewer
72105
72115
72125
256 x 16-8it Parallel-te-Serial FIFO
512 x 16-8it Parallel-te-Serial FIFO
1024 x 16-8it Parallel-te-Serial FIFO
. - --.--.._ - - - - - - - - - - - - - - - - - - -
t;)
IntegJated DevlcehhnoIogy.lnc.
CMOS PARALLEL-TO-SERIAL
FIFO 2048 x 9-BIT
& 4096 x 9-BIT
lOT 72131
lOT 72141
FEATURES:
DESCRIPTION:
• 35ns parallel port access time
The IDT72131/72141 are high-speed, low power parallel-toserial FIFOs. These FIFOs are ideally suited to serial communications applications, tape/disk controllers, and local area networks
(LANs). The IDT72131/72141 can be configured with the IDT's
serial-to-parallel FIFOs (IDT72132/72142) for bidirectional serial
data buffering.
The FIFO has a 9-bit parallel input port and a serial output port.
Wider and deeper parallel-to-serial data buffers can be built using
multiple IDT72131/72141 chips. IDT's unique Flexishift ™ serial
expansion logic (SOX, NR) makes width expansion possible with
no additional components. These FIFOs will expand to a variety of
word widths including 8,9,16, and 32 bits. The IDT72131/141 can
also be directly connected for depth expansion.
Five flags are provided to monitor the FIFO. The full and empty
flags prevent any FIFO data overflow or underflow conditions. The
almost-full (7/8), half-full, and almost-empty (1/8) flags signal
memory utilization within the FIFO.
The ID172131/72141 is fabricated using IDT's high-speed submicron CEMOS ™ technology. N1i1itary grade product is manufactured in compliance with the latest revision of MIL-STD-883;
Class B.
• 50MHz serial port shift rate
• Easily expandable in depth and width
• Programmable word lengths including 7-9, 16-18, and 32-36
bits using Flexishift ™ serial output without using any additional
components
.
• Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full,
Almost-Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write operations
• Dual-ported zero fall-through time architecture
• Retransmit capability in single device mode
• Produced with high performance, low-power CEMOS ™
technology
• Available in 28-pin ceramic and plastic DIP, 32-pin LCC and
J-Ieaded PLCC
• Military product compliant to MIL-STD-883, Class B
[II
I
FUNCTIONAL BLOCK DIAGRAM
Do - D8
FLAG
LOGIC
•••
RAM ARRAY
2048 x 9
4096 x 9
w
•••
NEXT READ
POINTER
~-I
-..JL..-_
RESET
_ LOGIC
_ _......
rLf n I
04,06,07,08
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology, Inc.
JANUARY 1989
D5C-2029/-
S6-95
....... _. __ ._---_.
__... _-_.._-_._._--_._.._ - - - - - - - - - - - - - - - - - - - -
IDT72131/IDT72141 CMOS
: PARALLEL·SERIAL FIFO 2048 x 9·BIT & 4096 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.PIN CONFIGURATIONS
W
Vee
04
05
03
O2
06
01
Da
0
INDEX~
WUUIIUUL!
07
0 1 :15
m
SOX :la
SOCP :19
SO :I 10
Arr :I 11
J=1=' :J 12
NC :I 13
~
><07HF'
GND
06
Arr
~
04
06
1
3231 30
J32-1
&
L32-1
29 £:
26 r:
27 [:
26[
14151617 la 19 20
25 £:
24 £:
23 £:
22£:
21 r:
07
06
T=ImT
~
NC
~
~
GND
NC
nnnnnnn
0;
~a~~ood'
C)
.
l"Jt{
GND
L.I
m :17
AS
SOX
SOCP
. SO
4 3 2
Do :J 6
T=ImT
Do
00'0'8: ~O'd'
LCC/PLCC
TOP VIEW
DIP
TOP VIEW .
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
1/0
Do - Da
Inputs
I
Data inputs for 9·bit wide data.
~
Reset
I
When ~ is set low. internal READ and WRITE pOinters are setto the first location of the RAM array. FW and ~ go
high. and A'EF and ~ go low. A reset is required before an initial WRITE after poweNW' Wmust be high and
SCOP low during ~ cycle. SOCP must have also completed its serial word so that
is high.
W
Write
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag (~) is not set. Data set·up arid hold times must
be adhered to with respectto the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
SOCP
Serial Output
Clock
I
A serial bit read cycle is initiated oil the rising edge of SOCP if the Empty Flag (~) is not set. In both Depth and
Serial Word Width Expansion modes. all of the SOCP pins are tied together.
l"Jt{
Next Read
I
To program the Serial Out data word width. connect l"Jt{ with one of the Data Set pins (04 • 0 6 • 0 7 and Oa). For
example. l"Jt{.- 07 programs for a 8-bit Serial Out word width.
FE/liT
First Load!
Retransmit
I
This is a dual purpose input. In the Single device configuration
grounded). activating retransmit (roliT-low)
will setthe internal READ pOinter to the firstlocation. There is no effect on the WRITE pOinter. SOCP and W must be
high before setting IT/Ai low. Retransmit is not compatible with depth expansion. In the depth expansion configuration. FE!liT grounded indicates the first activated device.
m
Expansion In
I
In the single device configuration. is grounded. In depth expansion or daisy chain expansion.
XC) (expansion out) of the previous device.
SOX
Serial Output
Expansion
I
In the Serial Output Expansion mode. SOX is tied high on the device that will source the lower order bits ofthe serial
word. The device or devices that source the next higher order serial bits have their SOX pin tied to the 0 6 pin afthe
device that will source the next lower order bits of the serial word. Data is then clocked out least significant bit first.
For Single device operation. SOX is tied high.
SO
Serial Output
0
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first. In the Serial Width
Expansion mode the SO pins are tied together and each SO pin is tristated at the end of the byte.
~
Full Flag
0
When i=!= goes low. the device is full and further WRITE operations are inhibited. When ~is high. the device is not
full.
~
Empty Flag
0
When ~ goes low. the device is empty and further READ operations are inhibited. When ~ is high. the device is
not empty.
A"rr
Almost-Empty!
Almost-Full Flag
0
When A'EF is low. the device is empty to 1/8 full or 7/8 to completely full. When A'EF is high. the device is greater
than 1/8 full. but less than 7/8 full.
XC)/FW
Expansion Out!
Half-Full Flag
0
This is dual purpose output. In the single device co~uration
grounded). the device is more than half full
when HF is low. In the depth expansion configuration (
connected to of the next device). a pulse is sent from
XC) to
when the last location in the RAM array is filled.
0
The appropriate DataSet pin (0 4 .0 6 • 070rOa) is connected to ~to program the Serial Out data word width.
For example: 06 .l"Jt{ programs a 7·bit word width. 06 • ~ programs a 9-bit word width. etc.
Data Set
04. 0 a.
07 and 08
(m
m
a
m
Vee
Power Supply
Single Power Supply of 5V.
GND
Ground
Single Ground at 10V.
(m
mis connected to
m
.
S6-96
'~'I
IDT72131/IDT72141 CMOS
PARALLEL-SERIAL FIFO 2048 x 9·BIT &.4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATUS FLAGS
NUMBER OF WORDS
IN FIFO
m=
~
"F'F
"E"F
IDT72141
IDT72131
0
0
H
L
H
L
1-255
1-511
H
L
H
H
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L·
H
2048
-4096
L
L
L
H
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
COMMERCIAL
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
SYMBOL
DC Output Current
50
mA
.50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
UNIT
VeeM
Military Supply
Voltage
PARAMETER
4.5
5.0
5.5
V
Vee
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
Commercial
2.0
-
-
V
VIH
Input High Voltage
Military
2.2
-
-
V
VIL (I)
Input Low Voltage
Commercial &
Military
-
-
0.8
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: \bc= 5V ±10%, TA = O°C to + 70°C: Military: Vcc= 5V ±10%, T.o. = -55°C to + 125°C)
IlL (1)
Input Leakage Current (Any Input)
IDT72131/IDT72141
COMMERCIAL
MIN.
MAX.
TYP.
-1
1
IOL(2)
Output Leakage Current
-10
-
10
-10
-
10
VOH
Output Logic "1" Voltage
2.4
204
V
004
0.4
V
90
140
-
-
-
VOL
-
-
-
Output Logic "0· Voltage.
100
160
mA
-
8
12
-
12
25
mA
-
2
4
mA
-
8
-
-
12
mA
SYMBOL
PARAMETER
ICCI (3)
Power Supply Current
ICC2 (3)
Average Standby Current ..... _ . __ ...
(A = W = R'ST = F[/tIT = VIH)'
IOC3 (L) (3, 4)
Power Down Current
ICC3 (S) (3,
Power Down Current
4)
,',:1
,-
-
NOTES:
1. Measurements with OAS VIN SVOUT'
2. R ~VIH' 004 SVOUT S\bc
3. Icc measurements are made with outputs open.
4.
'RS = "FCIRT = W = R = V ce-0.2V: all other inputs
~ Vce -0.2V or S 0.2V
S6-97
IDT72131/IDT72141
MILITARY
MIN.
TYP.
MAX.
-10
10
-
UNIT
~A
~A
1DT72131/IDT72141 CMOS
··PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (1)
+ 70°C' Military' Vcc =
5V +10%
TA = -55°C to + 125°C)
MILITARY ANI . COMMERCIA
COM'L
MIL
72131x80
72131x120
72131x40
72131x50
72131x65
72131x35
72141x80
72141x120
72141x40
72141x50
72141x65
72141x35
MIN.
MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
(Commercial' Vce = 5V +10% TA =OoC to
PARAMETER
SYMBOL
ts
Parallel Shift Frequency
-
22.2
-
20
tsocp
Serial-Out Shift Frequency
-
50
-
50
-
-
20
-
0
-
50
40
-
PARALLEL INPUT MODE TIMINGS
.t
Data Set-up Time
DS
tDH
Data Hold Time'
18
0
twc
Write Cycle Time
twpw
Write Pulse Width
45
35
tWA
tWEF
Write Recovery Time
10
Write High to ~ High
-
tWFF
Write Low to ~ Low
tWF
t WPF
Write Low to Transitionfng W,
AE"F
Write Pulse' Width After ~ High
..
-
10
-
-
35
35
-
-
7
MHz
28
25
MHz
-
40
-
40
-
ns
-
'10
-
10
ns
140
120
-
20
-
20
-
60
-
60
ns
60
ns
100
140
ns
15
-
12.5
40
-
33
30
-
30
5
-
10
80
65
-
100
80
60
45
-
65
50
15
-
15
UNIT
-
45
65
-
80
-
10
ns
. ns
ns
-
30
30
-
45
-
35
-
40
-
50
-
65
-
80'
-
120
-
ns
50
60
60
-
SERIAL OUTPUT MODE TIMIMGS
tSOHZ
SOCP Rising Edge to SO at
.
High Z(l)
5
16
5
16
5
26
5
20
5
25
5
35
ns
tSOLZ
SOCP Rising Edge to SO at
LOWZ(l)
5
22
5
22
5
22
5
22
5
30
5
35
ns
t SOPD
SOCP Rising Edge to Valid Data'
on SO
-
18
-
18
-
18
-
22
-
30
-
35
ns
tsox
SOX Set-up Time to SOCP
Rising Edge
5
-
5
-
5
-
5
-
5
-
ns
Serial In Clock Width High/Low
8
-
8
-
5
tsocw
10
10
-
15
-
15
ns
SOCP Rising Edge
(Bit 0 - First Word) to ~ Low
20
-
25
30
-
-
tSOCEF
-
-
30
30
ns
tSOCFF
SOCP Rising Edge to ~ High
-
30
65
ns
SOCP Rising Edge to
30
-
35
tSOCF
65
ns
-
40
-
ns
tAEFSO
fW. AEF. High Recovery Time SOCP After 1:F!
35
High
25
35
-
-
-
40.
-
50
-
50
-
60
40
60
-
50
-
65
,....
80
-
120
-
100
-
140
-
80
-
120
ns
120
-
20
-
ns
100
140
ns
140
ns
ns
RESET TIMINGS
t ASC
Reset Cycle Time
45
-
50
-
65
-
80
tAs
Reset Pulse Width
35
-
40
-
50
-
65
35
-
40
-
50
-
10
-
15
-
65
10
15
-'.
-
45
-
50
65
-
80
45
-
50
-
65
-
Reset Set-up Time
tASS
Reset Recovery Time
t ASA
t ASF1
Reset to E"F' and AE""F Low
t
'
Reset to fW and ~ High'
ASF2
RETRANSMIT TIMINGS
~
80
-
100
-
ns
tATC
Retransmit Cycle Time
45
-
50
-
80
-
100
-
140
-
Retransmit Pulse Width
35
-
40
-
65
tAT
50
65
-
120
-
ns
Retransmit Set-up Time
35
-
40
-
50
65
80
ns
10
-
10
-
15
-
-
Retransmit Recovery Time
15
20
-
120
tATA
-
80
tATS
-
20
-
ns
-
35
-
40
.-
50
-
80
120
ns
40
50
65
-
80
-
120
-
-
-
-
-
65
35
80
-
120
-
ns·
ns
10
-
10
15
-
15
-
ns
DEPTH EXPANSION MODE DELAYS
t XOL
Read/Write to ~ Low
~
80
20
ns
t XOH
Read/Write to ~ High
tx
mPulse Width
mRecovery Time
35
-
40
tXIA
10
10
t XIS
"5<'1 Set-up Time
15
-
15
NOTE: 1. Guaranteed by desig.n minimum times,not tested.
~
S6-98
-
65.
10
15
-
15
50
10
-
-
.
ns
'I
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72131/IDT72141 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
AC TEST CONDITIONS
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
SYMBOL
5000
D.U.T~
4OpFOr
CONDITIONS
MAX.
UNIT
10
pF
C our
. Vour= OV
. 12
Output Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
pF
C IN
·
Input Capacitance
VIN = OV
fSV
Figure A. Output Load.
(TA= +25°C, f = 1,OMHz)
PARAMETER(l)
.
*Includes jig and scope capacitances.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The data is written into the FIFO in parallel through the Do-a input
data lines. A write cycle is initiated on the falling edge of the Write
(iii) signal provided the Full Flag (FF) is not asserted. If the Vi sig- .
nal changes from HIGH-to-LOW and the Full Flag (FF) is already
set, the write line is inhibited internally from incrementing the write
pointer and no write operation occurs.
Data set-up and hold times must be met with respect to the rising edge of Write. The...Qata is written to the RAM at the write pointer.
On the rising edge of W, the write pointer is incremented. Write operations can occur simultaneously or asynchronously with read
operations.
twc
twpw
w
~
tWR
K
"/
IL
~
1/
~
I"
/
tos
1
tOH
Figure 1. Write Operation
Serial Data Output
(NR).
The serial word is shifted out Least Significant Bit first, that is the
first bit will be Do, then 01 and so on upto the serial word width. The
serial word width must be programmed by connecting the appropriate Data Set line (04, 06, 07, or Oa) to the NR input. The Data
Set lines are taps off a digital delay line. Selecting one of these
taps, programs the width of the serial word to be read and shifted
out.
The serial data is output on the SO pin. The data is clocked out
on the rising edge of SOCP providing the Empty Flag (EF) is not
asserted. If the Empty Flag is asserted then the next data word is
inhibited from moving to the output register and being clocked out
by SOCP. NOTE: SOCP should not be clocked while the Empty
Flag is low. If it is, then two things will occur. One, invalid data will
be read by SOCP and two, SOCP will be out of sync with Next Read
S6-99
[II
I
IDT72131/1DT72141 CMOS
PARALLEL-SERIAL FIFO 2048
X
9-BIT & 4096
X
9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
14----1/tsocp ---~
n-1
~.
SOCP
SOX
SO
tSOHZ
14-----.j
SO
Figure 2. Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
o
ADDITIONAL
READS
n-1
o
SOCP
w
Figure 3. Full Flag from Last Write to First Read
S6-100
FIRST WRITE
n-1
---
----------------------------_.
IOT72131/IOT72141 CMOS
PARALLEL-SERIAL FIFO 2048 X 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES·
NO READ
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
w
NOTE.1
soep
SO
Figure 4. Empty Flag from Last Read to First Write
NOTE:
1.
soep should not be clocked until ~ goes high.
w
tWEF
-~---
tSOCEF
n-1
NOTE 1 :
~
soep
SO
Figure 5. Empty Boundry Condition Timing
NOTE:
1.
soep should not be clocked until EF" goes high.
S6-101
- - - - - ._ ... _---_ .. _----_._-------_..... -----
IDT72131/IDT72141 CMOS
PARALLEL·SERIAL FIFO 2048
x 9·BIT & 4096 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
o
n-1
~--------
SOCP
w
DATA IN
DATAIN
so
VALID
DATAoUT VALID
Figure 6. Full Boundry Condition Timing
w
f""""-----'/
HALF·FULL (1/2)
HALF·FULL
HALF·FULL
+
1
SOCP
ALMOST FULL (7/8 FULL
ALMOST·EMPTY
(1/8 FULL-1)
+
1)
1/8 FULL
Figure 7. Half Full, Almost Full and Almost Empty Timings
S6-102
7/8 FULL
ALMOST·EMPTY
(1/8 FULL-1)
IDT72131/IDT72141 CMOS
PARALLEL·SERIAL FIFO 2048
X
9·BIT & 4096
X
9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~-----------------------------tA~--------------------------------~
~-----------------------tAS--------------------------~
w
HF.~
Figure 8. Reset
NOTES:
1. ~,'F'F and ffi! may change status during Reset, but flags
be valid at t
2. NFi is set high by SOCP staying low at the completion of a serial word.
will
ASC '
Figure 9. Retransmit
NOTE:
1. E'F.~.
HF and "FF may change status during Retransmit, but flags will be valid at t ATC'
S6-103
.....
- ..
__ _ - - .•.
10172131/IOT72141 CMOS
, PARALLEL·SERIAL FIFO 2048 x 9·BIT & 4096 X 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
w
SOCP
Figure 10. Expanslon·Out
\ + - - - - tXI ----~II--- tXIR ---~
w
SOCP
----Irll'--Figure 11. Expansion·ln
S6-104
·111
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72131/1DT72141 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
lines (04, Os) go low and a new serial word is started. The DataSet
lines then go high on the equivalent soep clock pulse. This continues until the 0 line connected to NR goes high completing the
serial word. The cycle is then repeated with the next LOW-ta-HIGH
transition of soep.
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SOX line is tied HIGH and not used.
On the first LOW-to-HIGH of the soep clock, all of the Data Set
PARALLEL DATA IN
DO-7
so
SERIAL OUTPUT CLOCK -~-.t SOCP
SERIAL DATA OUTPUT
GND
Vee - - - . I SOX
0
2
3
4
5
6
7
2
0
4
3
5
6
7
0
soep
\
06
\
07
\
1\
NR\
r-\
/
''-
/
\
/
04
/
\
I'r-'L
Figure 12. Eight-Bit Word Single Device Configuration.
TRUTH TABLES
TABLE 1: RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
MODE
INPUTS
INTERNAL STATUS
RS
FL
XI
READ POINTER
Reset
Retransmit
0
X
1
0
0
0
Read/Write
1
1
0
Location Zero
Location Zero
Increment(1)
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
S6-105
OUTPUTS
AEF, EF
1=F
HF
Location Zero
0
1
Unchanged
Increment(1)
X
X
1
X
X
X
X
WRITE POINTER
[I
1DT72131/IDT72141 CMOS
'PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case,word widths at more than 9 bits can be
achieved by using more than one device. By tying the SOX line at
the' least significant device HIGH and the SOX at the subsequent
most significant. When the Data Set line which is connected to the
SOX input of the next device goes HIGH, the Do ofthat device goes
HIGH, thus cascading from one device to the next. The Data Set
line of the most significant bit programs the serial word width by
being connected to all NR inputs.
The Serial Data Output (SO) of each device in the serial word
must be tied together. Since the SO pin is three stated, only the device which is currently shifting out is enabled and driving the 1-bit
bus.
devices to the appropriate Data Set lines of the previous devices, a
cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of soep, all the lines go
LOW. Just as in the standalone case, on each corresponding clock
cycle, the equivalent Data Set line goes HIGH in order at least to
PARALLEL DATA IN
16-BITS WIDE
GND
'+----1 SO
DO-B
....----..... socp
SERIAL OUTPUT CLOCK
FIFO #2
Vee
7
0
socp
~~DO~J:gf1
FIFO #2
~~J'~I&~#2
FIFO #1
AND FIFO #2
8
~
"
"
l,
9
14
10
15
0
/\f\J\
I
,
II
"
ii1
II
l,
~
~
Figure 13. Width Expansion for 16·bit Parallel Data In. The Parallel Data In Is tied to DO-80f FIFO #1 and 00-8 of FIFO #2
56-106
IDT72131/1DT72141 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-81T & 4096 x 9-81T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (xi) pin of the next device.
4. Externallo'gic is needed to generate a composite Full Flag (FF)
and Empty FI~ (EF). This requires the OR-ing of all EFs and
OR-ing of ~FF ~.e .• all must be set to generate the correct
composite FF or EF).
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion mode.
Depth Expansion (Daisy Chain) Mode
The IDT72131/41 can be easily adapted to applications where
the requirements are for greater than 2048/4096 words. Figure 14
demonstrates Depth Expansion using three IDT72131/41. Any
depth can be attained by adding additional IDT72131/41. The
IDT72131/41 operates in the Depth Expansion configuration when
the following conditions are met:
1. The first device must be designated by grounding the First Load
(FI.) control input.
2. All other devices must have FL in the high state.
r.:=====;--;:::==::t===
DO-7
~---'~r-----+-----
W
FI/FIT
IDT72141
SOCP~-----'--+-----------------~
SO~----~--'-------------~
Figure 14. An 12K x 8 Parallel-In Serial-Out FI FO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
MODE
Reset-First Device
Reset all Other Devices
Read/Write
INPUTS
INTERNAL STATUS
OUTPUTS
'F[
Xl
READ POINTER
WRITE POINTER
'E'F
"F'F
0
"0
0
(1)
Location Zero
Location Zero
1
1
(1)
Location Zero
Location Zero
1
X
(1)
X
X
0
0
X
'FfS
NOTES:
1. Xl is connected to )«5 of previous device.
2. fiS = Reset Input. FI/RT = First Load/Retransmit, ~ = Empty Flag Output.
56-107
F'J!
= Full Flag Output.
XI
= Expansion Input
1
X
IOT72131/IOT72141 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxxx
Device Type
.A·
Power
A
Process/
Temperature
999
Speed
-y:rMk
~
__________
~
____
1--_ _ _ _ _ _ _ _ _ _ _--..,
S6-108
Military (-55°C to + 125°C)
Compliant to MIL-STD-883,.Class B
J
L
Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
35
40
·50
65
80
120
(50MHz serial shift rate)
(50MHz serial shift rate)
(40MHz serial shift rate)
(33MHz serial shift rate)
(28M Hz serial shift rate)
(25MHz serial shift rate)
S
L
Standard Power
Low Power
72131
72141
2048 x 9-Bit Parallel-Serial FIFO
4096 x 9-Bit Parallel-Serial FIFO
P
~
,Commercial (O°C to + 70°C)
D
}
Parallel Access Time (t
)
A
Intesrated Device1echnoIosy.Inc.
CMOS SERIAL-TO-PARALLEL
FIFO 2048 x 9 BIT & 4096 x 9 BIT
lOT 72132
lOT 72142
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT72132/72142 are high-speed, low-power serial-toparallel FIFOs. These FIFOs are ideally suited to serial communications applications, tape/disk controllers, and local area
networks (LANs). The I DT72132/72142 can be configured with the
lOT's parallel-to-serial FIFOs (IDT72131/72141) for bidirectional
serial data buffering.
The FIFO has a serial input port and a 9-bit parallel output port.
Wider and deeper serial-to-parallel data buffers can be built using
multiple IDT72132/72142 chips. lOT's unique FlexishiftTM serial
expansion logic (SIX, NW) makes width expansion possible with
no additional components. These FI FOs will expand to a variety of
word widths including B, 9, 16, and 32 bits. The IDT72132/142 can
also be directly connected for depth expansion.
Five flags are provided to monitor the FIFO. The full and empty
flags prevent any FIFO data overflow or underflow conditions. The
Almost-Full (7/B), Half-Full, and Almost-Empty (1/B) flags signal
memory utilization within the FIFO.
The IDT72132/72142 is fabricated using lOT's high-speed
submicron CEMOS ™ technology. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883,
Class B.
35ns parallel port access time
50 MHz serial port shift rate
Easily expandable in depth and width
Programmable word lengths including 8, 9, 16-18, and 32-36
bits using FlexishiffM serial input without any additional components
• Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full,
Almost-Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write operations
• Dual-ported zero fall-through time architecture
• Retransmit capability in single device mode
• Produced with high-performance, low-power CEMOS™
technology
• Available in a 2B-pin ceramic and plastic DIP, 32-pin LCC and
J-Ieaded PLCC
.
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SI
El§
FLAG
·LOGIC
.
~
AEF
::
RAM
ARRAY
2048 x 9
4096 x9
liS --t
RESET
rr!1rr ---I.._L_O_G_IC_.....
)(l - - ' EXPANSION
-,
LOGIC
LtD I
,-
CEMOS and Flexishift are trademarks of Integrated Device Technology, Irlc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
OSC-203O/-
1989 Integrated DeVice Technology. Inc.
86-109
1DT72132/72142 CMOS
SERIAL·TO·PARALLEL FIFO 2048 x 9·BIT & 4096 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vcc
07
uuu~
ZZZ
INDEX
08
8 .... '"
:>00
UWUIIWUW
4 3 2
FI:/m
GND
)(J
NC
liS"
SI
AE'F
FF
SICP
SIX
00
0 1
LiE"
EF
W/FfF
O2
03
:I 5
:16
:17
:I 8
:19
:110
:111
:J 12
:I 13
1
3231 30
J32-1
&
L32-1
1415 1617 181920
r.
GND
L..I
i i :i
29[:
28
27
26
25
24
23
22
21
£:
£:
[:
[;
[:
FI:/lir
liS"
SI
SICP
SIX
LiE"
£: EF
[:
W/FfF
£:
GND
,n :-: :-; :-:
a~lQ:.ol()ooo'"
08
c:l
0,
LCC/PLCC
TOP VIEW
DIP
TOP VIEW
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
I/O
SI
Serial Input
I
Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input (SI) pins are tied
together and SIX plus D7, 08 determine which device stores the data.
liS"
Reset
I
When AS is set low. internal READ and WRITE pointers are set to the first location of the RAM array. FfF and FF go
high. and AE:J= and U go low. A reset is required before an initial WRITE after power-up. ~ must be high
during a AS cycle.
NW
Next Write
I
To program the Serial In word width, connect NW with one of the Data Set pins (07. 08)
SICP
Serial Input Clock
I
Serial data is read into the serial input register on the rising edge of SICP. In both Depth and Serial Word Width
Expansion modes. all of the SICP pins are tied together.
I
When READ is low, data can be read from the RAM array ~uentiallY, independent of SICP. In order for READ
to be active, EF must be high. When the FIFO is empty ( -low). the internal READ operation is blocked and
00 - 08 are in a high impedance condition.
~
Read
FI:/liT
First Load/
Retransmit
I
This is a dual purpose input. In the single device configuration ()(J grounded). activating retransmit (FI:fRT·low)
will setthe internal READ pOinter to the firstlocation. There is no effect on the WRITE pointer. SOCP and W must be
high before setting
low. Retransmit is not possible in depth expansion. In the depth expansion configuration, FI:/RT grounded indicates the first activated device.
.
)(J
Expansion In
I
W (expansion out) of the previous device.
SIX
Serial Input
Expansion
I.
In the Expansion mode, SIX pin is tied high on the device that will source the lower order bits of the serial
word. The device or devices that source the next higher order serial bits have their SIX pin (or pins) tied to the
08 pin of the device that will source the next lower order.bits of the serial word. For Single device operation,
SIX is tied high.
DE"
Output Enable
I
When OE" is set low, the parallel output buffers receive data from the RAM array. When DE" is set high, parallel
three state buffers inhibit data flow.
rom
In the single device configuration, )(J is grounded. In depth expansion or daisy chain expansion, )(J is connected to
00- 08
Data Output
0
Data outputs for 9·bit wide data .
FF
Full Flag
0
When ~ goes low, the device is full and data must not be clocked in by SOCP. When FF is high, the device is not
full.
EF
Empty Flag
0
When "El= goes low, the device is empty and further READ operations are inhibited. When EF is high. the device is
not empty.
AEF=
Almost·Empty/
Almost·Full Flag
0
When AE:J= is low. the device is empty to 1/8 full or 7/8 to completely full. When AE'F is high, the device is greater
than 1/8 full, but less than 7/8 full.
W/lW
Almost·Empty/
Almost-Full Flag
0
07,08
Data Set
0
Vcc
Power Supply
Single power supply of 5V.
GND
Ground
Single ground of OV.
This is a dual purpose output. In the single device configuration ()(J grounded). the device is more than half full
when FW is low. In the depth expansion configuration (><0 connected to)(J ofthe next device). a pulse is sentfrom
><0 to )(J when the last location in the RAM array is filled.
The appropriate Data Set pin (07. 08) is connected to
example: 07 - NW programs a 8-bit word width, 08 -
S6-110
NW to program the Serial In data word width.
NW programs a 9-bit word width, etc.
For
IOT72132/72142 CMOS
SERIAL·TO·PARALLEL FIFO 2048 x 9·BIT & 4096 x 9·BIT
JI
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATUS FLAGS
NUMBER OF WORDS
IN FIFO
..
~
0
0
H
L
H
L
1-511
H
L
H
H
-"
256-1024
512-2048
H
H
H
H
1025-1792
2049-3584
H
H
L
H
1793-2047
3585-4095
H
L
L
H
2048
4096
L
L
L
H
SYMBOL
RATING
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
TSTG
~
R'F
1-255
ABSOLUTE MAXIMUM .RATINGS (1)
TB1AS
~
IOT72142
IOT72132
COMMERCIAL
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
SYMBOL
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Oto +70
-55 to + 125
°C
-55 to +125
-55 to +125
-65 to +135
-65 to +150
MIN.
TYP.
MAX.
UNIT
Military Supply
Voltage
4.5
5.0
5.5
V
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V '
1H
Input High Voltage
Commercial
2.0
-
-
V
V1H
Input High Voltage
Military
2.2
-
-
V
V1L (1)
Input Low Voltage
Commercial &
Military
-
-
0.8
V
?C
°C
DC Output Current
50
50
mA
lOUT
NOTE:
1.. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-.
INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cyc.le.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vec= 5V ±10%. TA = O°C to + 70°C; Military: Vcc= 5V ±10%', TA = -55°C to + 125°C)
SYMBOL
IOT72132/IOT72142
COMMERCIAL
TYP.
MAX.
1
. PARAMETER
MIN.
-1
MIN.
-10
10T12132/10T12142
MILITARY
TYP.
MAX.
10
UNIT
IIL(l)
Input Leakage Current (Any Input)
IOL(2)
Output Leakage Current
-10
-
10
-10
-
10
JlA
VOH '
Output Logic "1" Voltage
2.4
-
-
2.4
-
-
V
Output Logic "0' Voltage.
-
-
0.4
-
-
0.4
V
Power Supply Current
-
90
140
-
100
160
mA
ICC2 (3)
Average Standby Current
(f:i = W ";'RST = FI/tIT = V1H )
-
8
12
-
12
25
mA
Icc3 (L) (3. 4)
Power Down Current
-
-
2
-
-
8
-
mA
Power Down Current
-
4
ICC3 (S)(3. 4)
12
mA
-VOL
: ICCl
(3)
.-
NOTES:
1. Measurements with 0.4 ~ V1N ~VOUT'
2. R ~VIH' 0.4 ~VOUT ~Vcc
3. Icc measurements are made with outputs open.
4.
RS = FLIRT = R = Vcc -0.2V; all other inputs ~ Vcc -0.2V or ~ 0.2V
56-111
JlA
1DT72132/72142 CMOS
SERIAL-TO·PARALLEL FIFO 2048
X
9-BIT & 4096
X
9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (1)
(Commercial' Vee = 5V +10% TA =OoC to +70 o C; Military: Vee = 5V +10%, TA = -55°C to +125°C)
MILITARY AND COMMERCIAL
COM'L
MIL
PARAMETER
SYMBOL
72132x35
72142x35
MIN. MAX.
- 22.2
72132x40
72142x40
MIN. MAX.
20
72132x50
72142x50
MIN. MAX.
-
10
-
7
MHz
-
28
-
25
MHz
65
-
80
-
120
ns
15
-
20
-
20
65
-
80
-
120
-
ns
80
10
-
100
-
10
140
10
ns
-
-
-
-
-
ns
-
30
-
30
-
35
-
35
ns
5
-
5
-
5
-
5
-
ns
15
-
15
-
20
-
25
-
30
ns
-
5
-
5
-
5
-
5
-
ns
-
20
-
22
-
25
-
30
-
35
ns
12
-
15
-
15
-
20
-
20
-
ns
-
0
-
0
-
5
5
-
5
5
5
-
ns
10
-
10
-
5
-
15
-
15
-
ns
-
65
-
80
-
80
-
80
ns
-
50
-
60
-
60
ns
-
80
-
80
-
80
ns
15
-
20
-
20
-
ns
-
60
-
60
60
ns
60
-
60
-
60
ns
80
-
100
-
140
ns
80
-
120
-
ns
100
-
140
ns
80
80
-
120
120
20
-
20
-
100
-
140
ns
140
ns
140
20
-
15
50
-
50
-
40
tA
Access Time
-
35
-
40
-
50
tAA
tAPw
Read Recovery Time
10
-
10
-
15
Read Pulse Width
35
-
40
-
50
-
t AC
Read Cycle Time
-
50
5
-
Read Pulse Low to Data Bus at Low Z(1)
45
5
-
tALZ
-
65
10
tAHZ
Read Pulse High to Data Bus at High Z(1)
-
20
-
25
tDV
Data Valid from Read Pulse High
5
-
5
-
tOEHZ
Output Enable to High-Z (Disable)(1)
-
15
-
tOELZ
Output Enable to Low-Z (Enable)(1)
5
-
5
t AoE
Output Enable to Data Valid (Oo-s)
-
20
t SIS
Serial Data in Set-up Time to SICP
Rising Edge
12
-
tSIH
Serial Data in Hold Time to SICP
Rising Edge
0
-
0
tSIX
SIX Set-Up Time to SICP Rising Edge
5
5
tSICW
Serial in Clock Width High/Low
8
-
8
-
tSICEF
SICP Rising Edge (Bit 0 - First Word)
to EF High
-
45
-
50
tSICFF
SICP Rising Edge (Bit 0 - First Word)
torr Low
-
30
-
35
-
40
tSlCF
SICP Rising Edge to HF,.~
-
45
-
50
-
65
tAFFSI
Recovery Time SICP After FF
Goes High
15
-
15
-
15
-
tREF
Read Low to
30
-
35
-
45
tAFF
Read
-
30
-
35
-
45
tRF
Arr
-
45
-
50
-
65
tAPE
t Rsc
Read Pulse Width After 8! High
35
-
40
-
50
Reset Cycle Time
45
50
-
65
tAs
Reset Pulse Width
35
tRss
Reset Set-up Time
35
40
40
-
t ASR
Reset Recovery Time
10
-
10
tRSF1
Reset to
-
45
t As F2
E1= and AEF Low
Reset to HF and ff High
-
tRTe
Retransmit Cycle Time
tAT
Retransmit Pulse Width
tRTS
Retransmit Set-up Time
tATA
Retransmit Recovery Time
Read/Write to W Low
txOL
t XOH
Read/Write to
W
High
UNIT
33
-
-
FfF" and
72132x120
72142x120
MIN. MAX.
12.5
Parallel Shift Frequency
Serial-In Shift Frequency
Read High to Transitioning
72132x80
72142x80
MIN. MAX.
-
ts
tSICP
E1= Low
High to 1=F High
72132x65
72142x65
MIN. MAX.
-
50
50
-
65
65·
-
15
-
15
-
-
50
-
65
-
80
45
-
50
-
65
80
45
-
50
-
-
-
65
35
-
40
-
50
35
-
40
-
50·
10
-
10
-
15
-
-
35
-
40
-
-
35
-
40
tXI
)(f Pulse Width
35
-
40
tXIA
t XIS
)(f Recovery Time
10
10
)(f Set-up Time
16
-
-
15
-
NOTE:
1. Guaranteed by design minimum times, not tested.
S6-112
65
80
100
ns
ns
ns
ns
ns
80
-
100
65
-
80
65
-
80
15
-
20
-
50
-
65
-
80
-
120
ns
-
50
-
65
-
80
-
120
ns
50
-
65
-
80
-
120
ns
10
-
10
-
10
-
10
15
-
15
-
15
-
15
-
120
120
ns
ns
ns
ns
ns
ns
IDT72132/72142 CMOS
SERIAL-TO-PARALLEL FIFO 2048
·il
X
9-BIT & 4096
X
9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
SOOO
Input Pulse Levels .
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
SYMBOL
CIN
D.U.T.~
GND to 3.0V
3ns
1.SV
1.SV
See Figure 1
'OWI .• ··1'·5V
(TA= +2S0C, f = 10MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS
VIN = OV
Output Capacitance
Vour= OV
Cour
NOTE: .
1. This parameter is sampled and not 100% tested.
MAX,
UNIT
10
pF
12
pF
Figure A. Output Load.
*Includes jig and scope capacitances.
The serial word is shifted in Least Significant Bit first. Thus, when
the FIFO is read, the Least Significant Bit will come out on 00 and
the second bit is on 01 and so on. The serial word width must be
programmed by connecting the appropriate Data Set line (07, 08)
to the NW input. The data set lines are taps of a digital delay line.
Selecting one of these taps, programs the width of the serial word
to be read in.
FUNCTIONAL DESCRIPTION
Serial Data Input
The serial data is input on the SI pin. The data is clocked in on
the rising edge of SICP providing the Full Flag (FF) is not asserted.
If the Full Flag is asserted then the next data word is inhibited from
moving into the RAM array. NOTE: SICP should not be clocked
while the Full Flag is low. If it is, then the input data will be lost.
SICP.
SIX
51
Figure 1; Write Operation
Parallel Data Output
A read cycle is initiated on the falling edge of Read (R) provided
the Empty Flag is not set. The output data is accessed on a first-in!
first-out basis, Independent of the ongoin9. write operations. The
data is available tA after the fallinQedge of R and the output bus 0
goes into high impedance after R goes HIGH.
.
Alternately, the user can access the FIFO by keeping R LOW
and en~bling data on the bus by asserting Output Enable (OE).
When B is LOW, the OE signal enables data on the output bus.
When B is LOW and OE is HIGH, the output bus is three-stated.
When R is HIGH, the output bus is disabled irrespective of OE.
~---------------------------------------------------------------------- t RC ----------------------------------------------------------------
104-------------------------------- t RPW -------------------,-....,.,-----------+-1---------------------- tRR -----------------------..1
tov
104------------.l tOEHZ
VALID
DATA
00-8
Figure 2. Read Operation
S6-113
.
---_._•._-_..__.... __. _ - - - - -
IDT72132/72142 CMOS
SERIAL·TO·PARALLEL FIFO 2048 X 9·81T & 4096 X 9·81T
DOUBLE READ
SAME DATA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIRST READ .
INCREMENTED
NO DATA OUT
READ POINTER
INCREMENTED
NO DATA OUT
READ POINTER
SAME DATA
Figure 3. Read and Output Enable Timings
LAST WRITE
NO WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
NOTE 1
SICP
NOTE:
1. SICP should not be clocked until ~ goes high.
Figure 4. Full Flag from Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
SICP
tSICEF
Figure 5. Empty Flag from Last Read to First Write
S6-114
FIRST READ
-----------------------------------------
1DT72132/72142 CMOS
SERIAL-TO-PARALLEL FIFO 2048
x 9-BIT& 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES·
FIRST SERIAL-IN WORD - -....joooIl-I--SECOND SERIAL-IN WORD
1
~
0
~
SICP
DATA OUT
Figure 6. Empty Boundry Condition .Timing
SICP
n-1
Note 1
SI
DATA OUT
NOTE:
1. SICP must remain low until after FF goes high.
Figure 7. Full Boundry Condition Timing
S6-115
1DT72132/72142 CMOS
SERIAL-TO-PARALLEL FIFO 2048 x 9-BIT & 4096 X 9-BIT
o
n-2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
n-1
I'J\----------
SICP
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
ALMOST FULL (7/8 FULL
+ 1)
1/8 FULL
7/8 FULL
ALMOST-EMPTY
(1/8 FULL-1)
Figure 8. Half Full, Almost Full and Almost Empty Timings
~---------------------------- tRSC------------------------------~
~----------------------tRS------------------------~
------~
r----------~---
SICP
NOTE:
1. EF=, t=J= and HF may change status during Reset, but flags will be valid at t RSC '
Figure 9. Reset
S6-116
-----------,.,---
.-.-~--------------,-----------------
1DT72132/72142 CMOS
SERIAL-TO-PARALLEL FIFO 2048 x 9-BIT & 4096 X 9~BIT
I
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~------------------------------- tRTc----------------------~
NOTE:
1. 8!'.
AE"F'. FW and FF may change status during Retransmit. but flags will be valid at t RTC'
Figure 10. Retransmit
WRITE TO LAST PHYSICAL LOCATION
o
1
n-1
SICP
READ FROM LAST
PHYSICAL LOCATION
Figure 11. Expansion-Out
--------+1011_---
tXIf~ ----i~
n-1
SICP
~l
Figure 12. Expansion-In
S6-117
1DT72132/72142 CMOS
SERIAL·TO-PARALLEL FIFO 2048 x 9·BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
lines (D7' D8) go low and a new serial word is started. The Data Set
lines then go high on the equivalent SICP clock pulse. This continues until the D line connected to NW goes high completing the serial word. The cycle is then repeated with the next LOW-te-HIGH
transition of SICP.
OPERATING CONFIGURATIONS
Single Device Configuration
In the standalone case, the SIX line is tied HIGH and not used.
On the first LOW-te-HIGH of the SICP clock, both of the Data Set
SERIAL DATA IN
SI
PARALLEL DATA OUTPUT
SERIAL INPUT CLOCK----t SICP
Vcc
-----+I
GND
SIX
07 08
o
2
4
3
5
7
6
8
o
2
3
4
5
6
7
8
o
SICP
-J1
\~----------------~I
D7~~____________________
08
\
'-
~
-,------------------------------------~I
,_________________________~~_____'r--\.~
~~-------------------------------------~;--\~----------------------------------~
Figure 13. Nine·Bit Word Single Device Configuration
TRUTH TABLES
TABLE 1: RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
MODE
Reset
Retransmit
Read/Write
INPUTS
INTERNAL STATUS
'FrS
Fe
Xi
READ POINTER
0
1
1
X
0
0
0
0
Location Zero
Location Zero
Location Zero
Unchanged
1
Increment( 1)
NOTE:
1. Pointer will increment if appropriate flag is HIGH.
S6-118
WRITE POINTER
Increment(1)
OUTPUTS
AEF, EF
1=1=
HF
0
X
X
1
X
X
1
X
X
-------------"-.-.-~-------------
IOT72132/72142 CMOS
SERIAL-TO-PARALLEL FIFO 2048 x 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
On the first LOW-ta-HIGH clock edge ofSICP, both the DataSet
lines go LOW. Just as In the standalone case, on each corresponding clock cycle, the equivalent Data Set line goes HIGH in order of
least to most significant.
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can be
achieved by using more than one device. By tying the SIX line of
the least significant device HIGH and the SIX of the subsequent
devices to the appropriate Data Set lines of the previous devices, a
cascaded serial word is achieved.
SERIAL DATA IN
SERIAL-IN
CLOCK
Vee
-
I
•
~7W
SI
SICP
SI
SICP
FIFO #1
~
SIX
NW
8
PARALLEL
8 DATA OUT
00-7
FIFO #2.
SIX
NW
D7
D7
I
7
0
SICP
8
9
10
\
ilI
De OF FIFO #2.
AND NW TO
FIFO #1
AND FIFO #2.
\
U
15
0
/V\J\
f\J\
D8 OF FIFO #1
AND SIX OF
FIFO #2
14
I
II,
'IL
Figure 14. Serial-In to Parallel-Out Data of 16 Bits
86-119
1DT72132/72142 CMOS
SERIAL·TO·PARALLEL FIFO 204Bx 9·BIT & 4096 x·9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Depth Expansion (Daisy Chain) Mode
2. All other devices must have in the high state.
The IDT72132142 can be easily adapted to applications where
the requirements are for greater than 2048/4096 words. Figure 15
demonstrates Depth Expansion using three IDT72132/42. Any
depth can be attained by adding additional IDT72132/42. The
IDT72132/42 operates in the Depth Expansion configuration when
the following conditions are met:
1. The first device must be designated by grounding the First Load
(FL) control input.
3. The Expansion Out (XO) pin and Expansion In
. device must be tied together.
(xi) pin of each
a
4. External logic is needed to generate composite Full Flag (FF)
and Empty Flag (EF). This requires the OR·ing of ails and OR·
ing of all FFs (i.e., all must be set to generate the correct com·
posite (FF) or (EF).
5. The Retransmit (Ri) function and Half·Full Flag
available in the Depth Expansion mode.
(RF) are not
0 0- 7
0 0- 7
t.
~
Vee
SIX
IDT72142
SIX
IT/RT
IDT72142
SICP
Vee
SOX
SI
SICP
SI
Figure 15. An BK x B Serial·ln Parallel·Out FIFO
TABLE 2: RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
MODE
INPUTS
INTERNAL STATUS
OUTPUTS
RS
FL
Xi
READ POINTER
WRITE POINTER
EF
FF
0
(1)
Location Zero
Location Zero
1
(1)
Location Zero
Location Zero
0
0
1
Reset all Other Devices
0
0
Read/Write
1
X
(1)
X
X
X
X
Reset-First Device
NOTE:
1. liS
= Reset Input. FLIRT = First Load/Retransmit, EF= = Empty Flag Output, FF = Full Flag Output, "5
04 (IDT72402 and
IDT72404)
t
OUTPUT
CONTROL
LOGIC
READ POINTER
00-3
SO
OR
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
© 1989 Integrated Device Technology, Inc.
DSC-2011/1
S6-123
-,--_._----
,-----
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72402
IDT72404
IDT72401
IDT72403
NC/~(1)
NC/CTI: (2)
Vee
SO
OR
IR
SI
Do
D1
D2
SI
Qo
D3
GND
Vee
SO
OR
IR
Qo
Q1
Do
D1
Q2
D2
Q1
O2
Q3
D3
Q3
MR
Q4
D4
GND
MR
DIP/SOIC
TOP VIEW
DIP/SOIC
TOP VIEW
-
~
i;
§
~!!; z ::?g
INDEX
LJUIIULJ
3 2 LJ 20 19
:J
:J
6
]7
:J
1
4
:]5
Consult
Factory
L20-2
14 [:
8
9 10 11 12 13
(!)
LCC
TOP VIEW
NOTES:
1. Pin 1: NC-No Connection IDT72401'
OE -IDT72403
2. Pin 1: NC-No Connection IDT72402
OE -IDT72404
::?g
NC
LJU;;ULJ
3 2 LJ 20 19
1
]4
18
OR
:J 5
Qo
Q1
r:
OR
17 [:
Qo
]6
Consult
Factory
16 [:
Q1
]7
L20-2
15[
Q2
14 [:
Q3
:J 8
Q2
9 10 11 12 13
nnnnn
oo~oo
z
z
~
~!!; 0z
INDEX
nnnnn
Cerpack (IDT72404 Only)
Vc~
CTI:
NC
IR
NC
so
SI
OR
Do
D1
D2
D3
Qo
Q1
Q2
Q3
Q4
D4
GND
MR
TOP VIEW
S6-124
oo~ao
z
z
(!)
LCC
TOP VIEW
..
1OT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BITand 64 X S-BIT
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(1)
RATING
COMMERCIAL
MILITARY
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
VTERM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
UNIT
TA
Operating
Temperature
oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-55 to +135
°C
Storage
Temperature
-55 to +125
TSTG
-55 to +150
MIN •
. TYP.
MA)e;
UNIT
Vcc
Military
Supply Voltage
4.5
5.0
5.5
V
Vce
Commercial
Supply Voltage
4.5
5.0
5.5
V
. GND
Supply Voltage,
PARAMETER
SYMBOL
V
°C
0
0
0
V
"IH
Input High Voltage
2.0
-
-
V
"IL (1)
Input High Voltage
-
-
O.S
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
mA
50
DC Output Current
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
.specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. .
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vce
SYMBOL
= S.OV ±10%, TA = O°C to + 70°C; Military: \bc = SV ±
PARAMETER
VIC (1)
Input Clamp Voltage
IlL
Low-Level Input Current
IIH
. High-Level Input Current
Vee
Vee
VOL
Low-Level Output Current
Vee
\bH
High-Level Output Voltage
Vee
IOS(2)
Output Short-Circuit Current
Vee
1HZ
Off-State Output Current
(IDT72403 and IDT72404)
Vec
III
Icc
(3,4) .
Supply Current .
Vee
10%, TA
= -SSoC to
+12S°C)
TEST CONDITIONS
MIN.
MAX.
-
= Max., GND 'S:VI'S:Vee
= Max., GND 'S:VI 'S: Vee
= Min., 10L = SmA
= Min., 10H = -4mA
= Max., Vo = GND
= Max., Vo = 2.4V
= Max., Vo = OAV
= Max.: f = 10MHz
-10
-
Vec
Commercial
Military
.
UNIT·
~A
-
+10
~A
-
0.4
V
2.4
-
V
-20
-90
mA
-
+20
~A
-20
.:...
~A
-
35
45
mA
-
.
NOTES.
1. FIFO is able to withstand a -1.5V undershoot for less than 10ns.
2. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
3. Icc measurements are made with outputs open. ~ is HIGH for IDT72403172404.
4. For frequencies greater than 10MHz, Icc = 35mA + (1.5mA x [f - 10MHz]) commercial, and Icc = 40mA + (1.5mA x [f - 10MHz]) military.
S6-125
._.. _---_.--.
__ -----_._---- ... _---_ ..-._--_...._----..
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS
(Commercial: Vcc = S OV +10%
TA = O°C to + 70°C' Military: Vcc
-
= SV -+
10% TA = -SSoC to + 12S°C)
MILITARY AND COMMERCIAL
COMMERCIAL
SYMBOL
PARAMETER
FIGURE
IDT72401L45
IDT72402L45
IDT72403L45
IDT72404L45
MIN.
MAX.
tS lH (I)
ShIft In HIGH Time
2
9
tSIl
Shift In LOW Time
2
11
t iDS
Input Data Set-up
2
0
tlDH
tsOH (I)
Input Data Hold Time
2
13
Shift Out HIGH Time
5
9
tSOl
Shift Out LOW Time
5
11
tMAw
Master Reset Pulse
8
20
t MAS
Master Reset Pulse to SI
8
10
tSIA
Data Set-up to IR
4
3
tHIA
Data Hold from IR
4
13
tSOA(4)
Data Set-up to OR HIGH
7
0
-
IDT72401 L35
IDT72402L35
IDT72403L35
IDT72404L35
MIN. MAX.
IDT72401L25
IDT72402L25
IDT72403L25
IDT72404L25
MIN.
MAX.
9
-
11
17
-
24
-
IDT72401L15
IDT72402L15
1DT72403L15
IDT72404L15
MIN.
MAX.
IDT72401L10
IDT72402L10 UNIT
IDT72403L10
IDT72404L10
MIN.
MAX.
11
-
11
-
ns
25
30
-
ns
0
-
0
-
0
15
-
20
30
9
11
24
-
25
25
-
25
10
-
-
10
-
25
,-
3
-
5
5
-
5
15
-
20
-
30
-
0
-
17
25
0
0
11
0
-
ns
40
-
ns
11
ns
30
-
0
-
ns
25
30
35
ns
ns
ns
ns
ns
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc= S.OV ±10%, TA = OOCto +70°C; Military: Vcc
= 5V ±
10%, TA = -SSOCto + 12S°C)
COMMERCIAL
SYMBOL
PARAMETER
IDT72401L45
FIGURE IDT72402L45
IDT72403L45
IDT72404L45
MIN.
MAX.
35
18
-
fiN
Shift In Rate
2
-
45
tiRl (1)
Shift In to Input Ready LOW
2
18
tiRH
Shift In to Input Ready HIGH
2
-
Shift Out Rate
5
45
(1)
MILITARY AND COMMERCIAL
IDT72401L35
IDT72402L35
I DT72403L35
IDT72404L35
MIN.
MAX.
18
IDT72401L25
I DT72402L25
IDT72403L25
IDT72404L25
MIN.
MAX.
-
25
28
35
-
18
20
18
20
IDT72401L15
IDT72402L15
IDT72403L15
IDT72404L15
MIN.
MAX.
1DT72401 L1 0
IDT72402L10 UNIT
IDT72403Ll0
IDT72404L10
MIN.
MAX.
15
-
10
MHz
35
-
40
ns
40
45
ns
10
MHz
40
ns
55
ns
ns
25
-
-
19
-
35
-
34
-
40
5
-
21
tORl(l) Shift Out to Output Ready LOW
5
tORH (1) Shift Out to Output Ready HIGH
5
-
5
5
-
5
-
5
-
5
-
-
25
-
35
55
-
55
ns
65
-
65
ns
35
35
-
35
25
-
35
25
-
-
fOUT
tODH
Output Data Hold (Previous Word)
t oDS
Output Data Shift (Next Word)
tPT
Data Throughput or "Fall-Through"
tMRoRl Master Reset to OR LOW
5
-
20
4,7
-
25
8
.:..
25
-
28
-
25
-
28
20
20
15
-
20
12
-
-
12
-
15
-
tMRIAH
Master Reset to IR HIGH
8
tMRQ
Master Reset to, Data Output LOW
8
OE" LOW
tHzO~·4 Output HIGH-Z from OE" HIGH
tOOE (3) Output Valid from
18
9
9
12
28
tlPH(2.4) Input Ready Pulse HIGH
4
9
-
9
-
11
top~2.4) Output Ready Pulse HIGH
7
9
-
9
-
11
40
35
'
11
11
15
30
40
ns
40
ns
40
ns
35
ns
30
ns
11
-
ns
11
-
ns
NOTES:
1. Since the FIFO is a very high-speed device, care must be exercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of O.l~F directly between Vcc and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like
speed grades.
3. IDT72403 and IDT72404 only.
4. Guaranteed by deSign but not currently tested.
S6-126
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
GNDto 3.DV
3ns
1.5V
1.5V
See Figure 1
SYMBOL
CIN
(TA= +25°C,f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS
VIN = OV
CoUT ' Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.
2. Characteri,zed values, not currenUy tested.
' MAX.
UNIT
5
pF
7
pF
ALL INPUT PULSES:
3.0V - - - - - - , ..,....._ _ _ _,,'
OUTPUT
10%
10%
<3ns
<3ns
GND---~.JI
*Includes jig and scope capacitances.
Figure 1. AC Test Load
SIGNAL DESCRIPTIONS
'INPUT READY (IR)
INPUTS:
DATA INPUT (0 0 - 3,4)
Data input lines. The IDT72401 and IDT72403 have a 4-bit data '
input. The IDT72402 and IDT72404 have a 5-bit data input.
When Input Ready is HIGH, the FIFO is ready for new input data
to be written to it. When IR is LOW the FIFO is unavailable for new
input data. Input Ready is also used to cascade many FIFOs to, gether, as shown in Figures 10 and 11 in the Applications section.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (00- 3• 4 ) contains valid
data. When OR is LOW, the FIFO is unavailable for new output
data. Output Ready is also used to cascade many FIFOs together,
as shown in Figures 10 and 11.
CONTROLS
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is
HIGH, data can be written to the FIFO via the 0 0 - 3,4 lines.
SHIFT OUT (SO)
Shift Out controls the output of data out of the FIFO. When SO is
HIGH, data can be read from the FIFO via the Data Output (00-3. 4)
lines.
MASTER RESET (MR)
I
Master Reset clears the FIFO of any data stored within. Upon
power up, the FIFO should be cleared with a Master Reset. Master
Reset is active LOW.
OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLy)
Output Enable is used to read FIFO data onto a bus. Output Enable is active LOW.
OUTPUTS
DATA OUTPUT (0 0- 3,4)
Data Output lines. The IDT72401 and IDT72403 have a 4-bit
data output. The IDT72402 and IDT72404 have a 5-bit data output.
S6-127
. - - - - - - . " ... -.._ , . , - - _.._ - - - - - - - - - -
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
Data Output
These 64 x 4 and 64 x 5 FIFOs are designed using a dual-port
RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer
and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the
Shift In (SI) control; the read pointer is incremented by the falling
edge of the Shift Out (SO). The Input Ready (IR) signals when the
FIFO has an available memory location; Output Ready (OR)..2!9nals when there is valid data on the output. Output Enable (OE)
provides the capability of three-stating the FIFO outputs.
Data is shifted out on the HIGH-to-LOW transition of Shift Out
(SO). This causes the internal read pointer to be advanced to the
next word location. If data is present, valid data will appear on the
outputs and Output Ready (OR) will go HIGH. If data is not present,
Output Ready will stay LOW indicating the FIFO is empty. The last
valid word read from the FIFO will remain at the FIFO's output
when it is empty. When the FIFO is not empty, Output Ready (OR)
goes LOW on the LOW-to-HIGH transition of Shift Out. Previous
data remains on the output until the HIGH-to-LOWtransition of Shift
Out (SO).
FIFO Reset
Fall-Through Mode
.-Ihe FIFO must be reset upon power up using the Master Reset
(MR) signal. This causes the FIFO to enter an empty state, signified
by Output Ready (OR) being LOW and Input Ready (IR) being
HIGH. In this state, the data outputs (0 0 - 3• 4 ) will be LOW.
The FIFO operates in a fall-through mode when data gets shifted
into an empty FIFO. After a fall-through delay the data propagates
to the output. When the data reaches the output, the Output Ready
(OR) goes HIGH. Fall-through mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO, a location
is available for new data. After a fall-through delay, the Input Ready
goes HIGH. If Shift In is HIGH, the new data can be written to the
FIFO.
Since these FIFOs are based on an internal dual-port RAM architecture with separate read and write pointers, the fall-through
time (tpT) is one cycle long. A word may be written into the FIFO on
a clock cycle and can be accessed on the next clock cycle.
Data Input
Data is shifted in on the LOW-to-HIGH transition of Shift In (SI).
This loads input data into the first word location of the FIFO and
causes Input Ready to go LOW. On the HIGH-to-LOW transition of
Shift In, the write pointer is moved to the next word pOSition and Input Ready (IR) goes HIGH, indicating the readiness to accept new
data. If the FIFO is full,lnput Ready will remain LOW until a word of
data is shifted out.
TIMING DIAGRAMS
1 + - - - - - - - 1 / fIN - - - - - " * I - - - - - - 1 / f IN - - - - - - . (
SHIFT IN
INPUT READY
INPUT DATA
Figure 2. Input Timing
56-128
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
,---
NOTE 2,,SHIFT IN
/
INPUT READY
INPUT DATA
L
_ _ _ _..I
NOTE 4
\
NOTE 1
-=
~
NOTE 3
NOTE
5-:J
---~\\.______________....ll-- ___ ~~E~~ __
STABLE DATA
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the first word.
3. Input Ready goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the Input Ready remains LOW.
NOTE: Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).·
Figure 3. The Mechanism of Shifting Data Into the FIFO
SHIFT OUT
NOTE 5
SHIFT IN
NOTE 1
INPUT READY
~---------tpT----------~~--
STABLE DATA _--IIJlVVVWMIVV'VVw\
INPUT DATA
NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented.
Figure 4. Data Is Shifted In Whenever Shift In and Input Ready are Both HIGH
S6-129
---------------------------------------_._--------_._-----
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-BIT and 64
X
S-BIT .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
i00i------ 1ItOUT -----++------ 1ItOUT
------.1
SHIFT OUT
OUTPUT READY
OUTPUT DATA
A-DATA
C-DATA
NOTE 1
NOTES:
1. This data is loaded consecutively A. B. C.
2. Data is shifted out when Shift Out makes a HIGH to LOW transition.
Figure 5. Output Timing
NOTE 2
NOTE 4
SHIFT OUT (71
OUTPUT READY
NOTE 3
NOTE 1
- - - - -" ~;-T~ ;-- -OUTPUT DATA
A-DATA
. . . .
B-DATA
- - -_ _ _ _ _---'I~\----- _ _ _-
NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. Read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.
.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
S6-130
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT
OUTPUT READY
DATA OUTPUT
~/_O_T_E_1
____________
::~~~~~_t_PT__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_~~
_ tOPH~----------
t_SOR~J~t4--________
_ ______________
DATA VALID
NOTE:
1. FIFO initially empty.
Figure 7. tpr and toPH Specification
MASTER RESET
INPUT READY
NOTE 1
~-----------tMRORL----------~
OUTPUT READY
~-------tMRS------~,-
______________________
SHIFT IN
tMRQ ----------~
DATA OUTPUT
NOTE:
1. Worst case, FIFO initially full.
Figure 8. Master Reset Timing
OUTPUT ENABLE
DATA OUT
NOTE:
1. High-Z transitions are referenced to the steady-state VOH - 500mV and VOL
instead of 30pF as shown in Figure 1.
+ 500mV levels on the output. ~ZOE
Figure 9. Output Enable Timing, 1DT72403 and IDT72404 Only
S6-131
is tested with 5pF load capacitance
IDT72401/02/03/04 CMOS
. PARALLEL FIFO·64 x 4-BITand 64 x
5~BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS
SI
IR
Do
D1
D2
D3
'SHIFT IN
INPUT READY
DATA OUT {
SI'
IR
Do
D1
D2
D3
OR
SO
00
01
O2
f'M\
03
~
00
01
O2
1VfR
1
,...
OUTPUT READY
SHIFT OUT
OR
SO
} DATAOUT
03
Y
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherenttiming ofthe
devices.
...
.
Figure 10. 128 x 4 Depth Expansion
IR
SI
Do
D1
D2
D3
SO
OR
00
01
O2
fJR
03
SO
OR
IR
SI
Do
D1
D2
D3
00
01
O2
03
1VfR
IR
SI
Do
D1
D2
D3
SO
OR
SHIFT OUT
00
01
O2
1VfR
03
COMPOSITE
INPUT READY
IR
SI
Do
D1
D2
D3
SO
OR
00
01
O2
fJR
SHiFT IN
IR
SI
Do
D1
D2
D3
03
SO
OR
00
01
O2
f'M\
03
IR
SI
Do
D1 ·
D2
D3
SO
OR
00
01
O2
03
1VfR
IR
SI
Do .
D1
D2
D3
SO
OR
00
01
O2
03
f'M\
IR
SI
Do
D1
D2
D3
SO
OR
COMPOSITE
. OUTPUT READY
00
01
O2
f'M\
IR
SI
Do
D1
D2
D3
03
SO
OR
06
01
,02
f'M\
03
NOTES:
1. When the memory is empty, the last word read will remain on the outputs until the Master Reset is strobed or a new data word falls through to the output.
However, OR will remain LOW, indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW
until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
3. If SO' is 'held HIGH while the'memory is empty and a: word is written into the input, that word will appear at the output after a fall-through time. OR will go
HIGH for one internal cycle (at least t ORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the
FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
4. When the Master Reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the Master Reset goes
HIGH, the data on the inputs will be written .into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the Master Reset
is ended, IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
5. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite Input and Output
Ready flags. This is due to the variation of delays of the FIFOs.
Figure 11. 192 x 12 Depth and Width Expansion
S6-132
-------------------------------------------_.
IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxx
xx
X
Device Type
Package
Process/
Temperature
Range
y:rank
E
D
'-----------i L
P
SO
45
35
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Cerpack (IDT72404 Only)
CERDIP
Leadless Chip Carrier
Plastic Dip
Small Outline IC
Commercial Only
} Shift Frnqueney (MH'i
' - - - - - - - - - - - - - - - 1 25
15
10
L -_ _ _ _ _ _ _ _ _ _ _ _ _-II
L
I
72401
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 72402
L
72403
72404
S6-133
Low Power
64x4
64 x 5
64 x 4
64 x 5
FIFO
FIFO
FIFO with Output Enable
FIFO with Output Enable
/
t;)
Integrated Device1echnoIosy.1nc.
lOT 72413
CMOS PARALLEL
64 x 5-BIT FIFO
WITH FLAGS
FEATURES:
DESCRIPTION:
• First-In/First-Out dual-port memory"":'45MHz
The IDT72413 is a 64 x 5,high-speed First-In/First-Out (FIFO)
that loads and empties data on a first-In/first-out basis. It is expandable in bit width. The IDT72413 25MHz and 35MHz versions are
cascadable in depth.
The FIFO has a Half-Full Flag, which signals when it has 32 or
more words in memory. The Almost-Full/Empty Flag is active
when there are 56 or more words in memory or when there are 8 or
less words in memory.
The IDT72413 is pin and functionally compatible to the MMI
67413. It operates at a shift rate of 45MHz. This makes it ideal for
us'e in high-speed data buffering applications. The IDT72413 can
be used as a rate buffer, between two digital systems of varying
data rates, in high-speed tape drivers, hard disk controllers, data
communications controllers and graphics controllers
The IDT72413 is fabricated using IDT's high-performance
CEMOS process. This process maintains the speed and high
output drive capability of TIL circuits in low-power CMOS.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
• 64 x 5 organization
• Low power consumption
- Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth at 25MHz and 35MHz
• Half-Full and Almost-Full/Empty status flags
• IDT72413 is pin and functionally compatible with the M M16?413
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CEMOS ™ technology
• Available in plastic DIP, CERDlP, LCC and SOIC
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATION
OE"
FUNCTIONAL BLOCK DIAGRAM
OUTPUT ENABLE
(ITE)
Vcc
AF/E
HF
IR
SI
Do
Dl
D2
D3
so
OR
00
01
02
03
04
D4
GND
~
64x5
MEMORY
ARRAY
FIFO
OUTPUT
STAGE
FLAG
CONTROL
LOGIC
HALF-FULL (HF)
ALMOST-FULL!
EMPTY (AF/E)
DATA OUT
(00-4)
MASTER
RESET
DIP/SOIC
TOP VIEW
LCC
(CONSULT FACTORy)
L20-2
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
OSC-2015/1
1989 Integrated Device Technology
S6-134
IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
COMMERCIAL
VTERM
Terminal Voltage
with Respect to
GND
TA
TB'AS
TsTo
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Military
Supply Voltage
4.5
5.0
5.5
V
Operating
Temperature
o to +70
-55 to +125
°C
Vccc
Commercial
Supply Voltage
4.5
5.0
5.5
V
Temperature
Under Bias
-55 to +125
-65 to +135
°C
GND
Supply Voltage
0
0
0
V
V'H
Input
High Voltage
2.0
-
-
V
V'L(1)
Input
Low Voltage
-
-
0.8
V
Storage
Temperature
-55 to +125
-65 to +150
°C
DC Output Current
50
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(Commercial: Vcc = 5V ±10%, TA =O°Cto +70°C, Military: Vee = 5V ±10%, TA = -55°C to + 125°C)
SYMBOL
PARAMETER
TEST CONDITIONS
~e(1)
Input Clamp Voltage
I'L
Low-Level Input Current
Vee
I'H
High-Level Input Current
Vee
= Max.; GND :5V,
= Max.; GND :5V,
VOH
los (3)
1HZ
ILZ
Icc (4)
Low-Level Output Voltage
High-Level Output Voltage
Output Short-Circuit Current
Off-State Output Current
Vee
Vee
Vee
Vee
Vee
Supply Current
= Min.
= Min.
-
UNIT'
-10
-
~A
:5 Vce
-
10
~A
-
0.4
V
2.4
-
V
I MIL.
I COM'L.
12mA
24mA
10L (IR. OR)(2)
8mA
10L (HF, AF/E)
8mA
10H (0 0- 4 )
-4mA
10H (IR, OR)
-4mA
10H (HF, AF/E)
-4mA
= Max.
Vo = OV
Vo = 2.4V
= Max.
Vo = O.4V
= Max.
= Max. Inputs LOW, OE: = HIGH,
Vee
f = 25MHz
MAX.
:5 Vec
10L (0 0 - 4 )
VOL
MIN.
MIL.
COM'L.
-20
-90
-
+20
-20
-
-
70
mA
~A
mA
60
mA
NOTES.
1. FIFO is able to withstand a -1.5V undershoot for less than 10ns.
2. Care should be taken to minimize as much as possible the DC and capacitive load on IR and OR when operating at frequencies above 25M Hz.
3. Not more than one output should be shorted at a time and duration of the short circuit test should not exceed one second. Guaranteed by design but not
currently tested.
4. Frequencies greater than 25M Hz, Icc = 60mA + (1.5mA x [f - 25M Hz]) commercial and 'cc = 70mA + (1.5mA x [f - 25M Hz]) military.
S6-135
- - - - - - - - - - - - - - - - - - - - - - - - _.. _ - - - - - - - - - - - - - - - - - - - - - -
IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING CONDITIONS.
(Commercial: Vee = 5V ±10%, TA =O°C to +70°C, Military: Vee = 5V ±10%,1A = -55°C to + 125°C)
COMMERCIAL
MILITARY AND COMMERCIAL
SYMBOL
tSIH(l)
tSIL(l)
tlDS
tlDH
tSOH(l)
tSOL
tMRW
tMRS(3)
PARAMETER
FIGURE
Shift In HIGH Time
Shift In LOW Time
Input Data Set-Up
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset to SI
1DT72413L35
MIN.
MAX.
IDT72413L45
MIN.
MAX.
-
9
2
2
2
2
5
5
8
8
11
0
13
9
11
20 .
20
-
9
17
0
15
9
17
30
35
-
IDT72413L25
MIN.
MAX.
16
20
0
25
16
20
35
35
UNIT
-
ns
-
ns
ns
ns
ns
ns
ns
ns
-
-
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ±10%, TA =OOCto +70°C, Military: Vee = 5V ±10%, TA = -55°C to + 125°C)
MILITARY AND COMMERCIAL
SYMBOL
fiN
tlRL (1)
t IRH (l)
PARAMETER
FIGURE
Shift In Rate
2
t
Shift In t
to Input Ready LOW
2
to Input Ready HIGH
2
Shift In
Shift Out Rate
fOUT
t ORL (l)
Shift Out
tORH (1)
Shift Out
t
t
5
to Output Ready LOW
5
to Output Ready HIGH
5
IDT72413L45
MIN.
MAX.
COMMERCIAL
1DT72413L35
MIN.
MAX.
IDT72413L25
MIN.
MAX.
UNIT
-
45
-
35
-
25
MHz
18
-
18
-
28
ns
-
18
-
20
45
-
18
18
35
18
20
-
25
ns
25
MHz
28
ns
25
ns
tODH(l)
Output Data Hold Previous Word
5
5
-
5
-
5
-
ns
t oDS
Output Data Shift Next Word
5
20
-
20
-
20
ns
tpT(3)
Data Throughput or "Fall-Through"
4, 7
-
25
28
40
ns
to Output Ready LOW
8
-
25
-
30
ns
to Input Ready HIGH
30
ns
30
ns
tMRAFE
t IPH (3)
8
-
25
-
28
-
40
ns
Input Ready Pulse HIGH
4
5
-
5
-
5
-
ns
tOPH(3)
Output Ready Pulse HIGH
7
5
-
5
-
5
-
ns
t ORD (3)
Output Ready
5
-
5
-
5
7
ns
tAEH
Shift Out
40
ns
tAEL
Shift In
40
ns
tAFL
Shift Out
tMRORL
tMRIRH(3)
tMRIRL (2)
tMRQ
tMRHF
tAFH
tHFH
tHFL
t pHZ (3)
t pLZ (3)
t pzJ3)
tpZH(3)
t
Master Reset t
Master Reset t
Master Reset t
Master Reset t
Master Reset t
Master Reset
t
28
8
-
25
-
28
Input Ready LOW
8
-
25
-
28
to Outputs LOW
8
-
20
25
to Half-Full Flag
8
-
25
-
28
to AF/E Flag
t
9
-
28
-
28
to AF/E
9
-
28
-
28
t
10
28
-
28
10
-
-
28
-
28
11
-
28
-
28
11
-
28
-
28
12
12
t
HIGH to Valid Data
to AF/E HIGH
to AF/E LOW
t to AF/E HIGH
Shift In t to HF HIGH
Shift Out t to HF LOW
Shift In
12
-
15
-
12
-
15
-
12
Output Disable Delay
12
Output Enable Delay
12
35
ns
40
ns
40
ns
-
40
ns
40
ns
15
-
15
-
20
ns
12
40
ns
15
ns
15
ns
20
ns
NOTES:
1. Since the FIFO is a very high-speed device, care must be taken in the design ofthe hardware and the timing utilized within the design. Device grounding and
decoupling is crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply
decoupling and grounding. A monolithic ceramic capacitor of 0.1jJF directly between Vcc and GND with very short lead length is recommended.
MAt
2. If the FIFO is not full, (IR = HIGH),
forces IR to go LOW, and
3. Guaranteed by design, but not currently tested.
MAt
causes IR to go HIGH.
S6-136
IDT72413 CMOS PARALLEL
64 X 5·BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STANDARD TEST LOAD
AC TEST CONDITIONS
DESIGN TEST LOAD
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
2KO
OUTPUT
CAPACITANCE
SYMBOL
CIN
30pF*
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS
VIN = OV
COUT
VOUT= OV
Output Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
2. Characterized values, not currently tested.
MAX.
UNIT
5
pF
7
pF
*Includes jig and scope capacitances.
RESISTOR VALUES FOR STANDARD TEST LOAD
IoL
R1
24mA
2000
3000
12mA
3900
7600
8mA
6000
12000
R2
Figure 1. Output Load
FUNCTIONAL DESCRIPTION:
DATA OUTPUT
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM
architecture as opposed to the traditional shift register approach.
This FIFO architecture has a write pointer, a read pointer and controllogic, which allow simultaneous read and write operations. The
write pointer is incremented by the falling edge of the Shift In (SI)
control; the read pointer is incremented by the falling edge of the
Shift Out (SO). The Input Ready (IR) signals when the FIFO has an
available memory location; Output Ready (OR) sJ9..nals when there
is valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
Data is shifted out on the HIGH-to-LOW transition of Shift Out
(SO). This causes the internal read pointer to be advanced to the
next word location. If data is present, valid data will appear on the
outputs and Output Ready (OR) will go HIGH. If data is not present,
Output Ready will stay LOW indicating the FIFO is empty. The last
valid word read from the FIFO will remain at the FIFO's output
when it is empty. When the FIFO is not empty, Output Ready (OR)
goes LOW on the LOW-te-HIGH transition of Shift Out.
FIFO RESET
The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the data
propagates to the output. When the data reaches the output, the
Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is completely
full. When data is shifted out of the full FIFO, a location is available
fornew data. After a fall-through delay, the Input Ready goes HIGH.
If Shift In is HIGH, the new data can be written to the FIFO. The fallthrough delay of a RAM-based FIFO (one clock cycle) is far less
than the delay of a shift register-based FIFO.
The FIFO must be reset upon power up using the Master Reset
(MR) signal. This causes the FIFO to enter an empty state signified
by Output Ready (OR) being LOW and Input Ready (IR) being
HIGH. In this state, the data outputs (00-4) will be LOW.
DATA INPUT
I
I
Data is shifted in on the LOW-to-HIGH transition of Shift In (SI).
This loads input data into the first word location of the FIFO and
causes the Input Ready to go LOW. On the H IGH-to-LOW transition
of Shift In, the write pointer is moved to the next word position and
Input Ready (IR) goes HIGH indicating the readiness to accept new
data. If the FIFO is full, Input Ready will remain LOW until a word of
data is shifted out.
FALL-THROUGH MODE
S6-137
1DT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT READY (IR)
SIGNAL DESCRIPTIONS:
When Input Ready is HIGH, the FIFO is ready for new input data
to be written to it. When IR is LOW, the FIFO is unavailable for new
input data. Input Ready is also used to cascade many FIFOs
together, as shown in Figure 13 in the Applications section.
INPUTS:
DATA INPUT (00-4)
Data input lines. The 10172413 has a 5-bit data Input.
OUTPUT READY (OR)
CONTROLS:
SHIFT IN (51)
Shift In controls the input of the data into the FIFO. When SI is
HIGH, data can be written to the FIFO via the 00-4 lines. The data
has to meet set-up and hold time requirements with respect to the
rising edge of SI.
SHIFT OUT (SO)
Shift Out controls the output data from the FIFO.
MASTER RESET (MR)
When Output Ready is HIGH, the output (00-4) contains valid
data. When OR is LOW, the FIFO is unavailable for new output
data. Output Ready is also used to cascade many FIFOs together,
as shown in Figure 13 in the Applications section.
OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a bus.
Output Enable is active LOW.
ALMOST-FULl/EMPTY FLAG (AFE)
Master Reset clears the FIFO of any data stored within. Upon
power up, the FIFO should be cleared with a Master Reset. Master
Reset is active LOW.
HALF-FULL FLAG (HF)
Half-Full Flag signals when the FIFO has 32 or more words in it.
Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or
more words) or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (00-4)
Data output lines, three-state. The 10172413 has a 5-bit output.
TIMING DIAGRAMS
~------ 1/flN -----!~------1/fIN -----~
SHIFT IN
INPUT READY
INPUT DATA
Figure 2. Input Timing
S6-138
-----------------
IDT72413 CMOS PARALLEL
64 x 5·BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN(7)
----..I,'1--NOTE 2,,-
/
~ NOTE 4
\~--~------------------
NOTE 1
NOTES~
NOTE 3
INPUT READY
INPUT DATA
NOTE 6
\'--______________________..1-'- - - - - - - ~ - -
_ _ _ _ STABLE DATA
NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the FIFO.
3. Input Ready goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).
FIgure 3. The Mechanism of Shifting Data Into the FIFO
SHIFT OUT
NOTES
SHIFT IN
INPUT READY
! 'I""_t---------
NOTE
tpT
NOTE 4~
---------to~.,.- t lPH ~"'_ _ _ _ _ _ _ _ __
INPUT DATA
STABLE DATA
NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pOinter is incremented. Shift In should not go LOW until (t PT + t IPH )'
~
-
Figure 4. Data Is Shifted In Whenever Shift In and Input Ready are-Both HIGH
S6-139
--_. .. _ - - - - - - - - - - - - - - - __
IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
14------ 1 IfOUT -----0!4-----SHIFT OUT
OUTPUT READY
OUTPUT DATA
B-DATA
C-DATA
NOTE 1
NOTES:
1. This diagram is loaded consecutively, A, B, C.
2. Output data changes on the falling edge of SO after a valid Shift Out sequence, Le., OR and SO are both high together.
Figure 5. Output Timing
NOTE 4
SHiFT OUT(7)
OUTPUT READY
NOTE 3
NOTE 1
- - - - -"
OUTPUT DATA
A-DATA
. . . .
~;-T;;-
- --
B-DATA
------------------------------------~'~\~-------------------
NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. Read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after toRons.
6. If the FIFO has only one word loaded (A-DATA), Output Ready stays LOW and the A-DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
S6-140
IDT72413 CMOS PARALLEL
64 X 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
SHIFT IN
SHIFT OUT
1 4 - - - 1 .- - - , - -
OUTPUT READY
tpT
~~
-t-/____________________
NOTE 1
to PH
~
-1'1....-----
NOTE:
1. FIFO initially empty.
Figure 7. tpT and t OPH Specification
MASTER RESET
NOTE 1
INPUT READY
NOTE 1
OUTPUT READY
SHIFT IN
~...............-tMRS--...............~Ir_-----------------
DATA OUTPUTS
HALF-FULL FLAG
ALMOST FULU
EMPTY FLAG
NOTE:
1. FIFO is partially full.
Figure 8. Master Reset Timing
S6-141
._._---..
_ _--------------- _
...
....................-
IDT72413 CMOS PARALLEL
64 X 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING DIAGRAMS (Continued)
r
SHIFT OUT
ALMOST FULL/EMPTY
NOTE:
SHIFT IN
:OTE1~=4
_______________t_AE_H____________
~t~------t-SI-H~
1. FIFO contains 9 words (one more than Almost-Empty).
Figure 9. tAEH and tAEL Specifications
SHIFT IN
ALMOST FULL/EMPTY
SHIFT OUT
NOTE:
1. FIFO contains 55 words (one short of Almost-Full).
Figure 10. tAFH and tAFL Specifications
SHIFT IN
HALF-FULL
SHIFT OUT
~--------tHFL----------~
NOTE:
1. FIFO contains 31 words (one short of Half-Full).
Figure 11. tHFL and tHFH Specifications
3V
OV
1.5V
WAVEFORM 1 (1)
WAVEFORM 2(2)
O.5V.
VOL
O.5Vt
VOH
1.5V
NOTES:
1. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 12. Enable and Disable
S6-142
IDT72413 CMOS PARALLEL
64 x 5·BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APPLICATIONS'
HF c::5E" AF/E
IR
SI
OR
Do
~
01
D1
D2
O:!
D3
Os
04
D4
so
MR
HFc::5E" AF/E
IR
SO
SI
OR
Do
~
01
D1
D2
O:!
03
D3
04
D4
MR
COMPOSITE
INPUT READY
HFOE
IR
SI
Do
D1
D2
D3
D4
SHIFT IN
COMPOSITE
OUTPUT READY
AF/E
SO
OR
~
01
O:!
Os
MR
04
MASTER RESET'
NOTE:
1. FIFOs are expandable in width. However. in forming wider words two external gates are required to generate composite Input and Output Ready flags. This
requirement is due to the different fall-through times of the FIFOs.
Figure 13. 64x15 FIFO with IDT72413
8-BITS
8-BITS
TWO
SYSTEM 1
1-----...
IDT72413
64x8
SI
ENBLSI ....- - - - I I R
~T_--------~
SYSTEM 2
1-----...
SO
OR I + - - - - - t 10RDY
~----~~--~
~--------~~
INTERRUPT
INTERRUPT
HALF·FULL FLAG
NOTE:
1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.
Figure 14. Application for IDT72413 for Two Asynchronous Systems
S6-143
1DT72413 CMOS PARALLEL
64 x 5·BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SHIFT IN
INPUT READY
SI
IR
OR
SO
SI
IR
OR
SO
00
.0
Do
Dl
D2
D3
D4
00
01
DATA Dill {
Do
Dl
D2
D3
D4
1
O2
03
04
MR
1
OUTPUT READY
SHIFT OUT
O2
MR
} DATA Dill
03
04
Y
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherenttiming ofthe
devices.
Figure 15. 128 x 5 Depth Expansion
ORDERING INFORMATION
IDT
XXXX
Device Type
xx
X
Package
Process/
Temperature
Range
Y:,ank
P
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
SO
Plastic Dip
CERDIP
Leadless Chip Carrier
Small Outline IC
45
Commercial Only
o
'------------i L
~--------------------~35
} Shift Frequency (MHz)
25
~---------------__4 L
'-----------------------1
S6-144
72413
Low Power
64 x 5-Bit FIFO with Flags
t;)
1K x 18-BIT -2K x 9-BIT
PRELIMINARY
lOT 7252
lOT 72520
CMOS BiFIFO
Intesrated Deviceledmology.lnc.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bidirectional First-In/First-Out (FIFO) memory
Side-by-side 1K x 18-bit and 2K x 9-bit FIFO organization
35ns access time
Facilitates processor-to-peripheral and processor-to-processor communication
Matches bus widths: 16-bit to 8-bit and 32-bit to 8-bit buses
Asynchronous and simultaneous read and write operations
Parity check and generate
Width expandable to 36-bits
Hardware Reread and Rewrite
Hardware Load Reread and Load Rewrite for IDT72520
Hardware Reset for IDT72520
Build-in pass-through path
On-chip DMA for easy peripheral interfacing
Available in 48-pin DIP for IDT7252 and 52-pin LCC and
PLCC for IDT72520
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7252 and IDT72520 BiFIFOs are compact, highly integrated solutions for simplifying data transfer between two
processors or a processor and peripheral of different bus
bandwidths. With access speed of 35ns, the BiFIFO can quadruple
system performance of th,e peripheral interface by eliminating
mismatched bus widths. The BiFIFO can handle data transfer between 16-bit to 8-bit, 32-bit to 8-bit buses and 32-bit to 16-bit buses.
Both ports can be operated concurrently, essentially operating
as two FIFOs in one chip. PortA is organized in 1Kx 18-bitandport
B is organized is 2K x 9-bit, with the ninth bit of this FIFO used for
parity check or generate. A unique data pass through mode allows
for synchronous communication between two devices. To improve
system performance when interfacing to peripherals which.§!:!Eport DMA operations, a Request (REO) and Acknowledge (ACK)
handshake is included.
Four external flag pins can be used to configure and access any
one of sixteen internal flags (Four in each FIFO for both positive
and negative polarity). The four internal flags are Empty,
Empty + Offset, Full and Full-Offset. The offset value and flag polarity can be determined by the users.
The BiFIFO incor~tesa Reread (RER) and Rewrite{REW).
Upon si9!:§!lng the RER input, the read pointer is reset with the
value of RER pointer and data is read~in. With signaling REW,
the write pointer is reset with value of REW pointer and data is written again. These internal read and write pointers can be set by the
user through a control register. In addition, the IDT72520 has hardware Load Reread, Load Rewrite and Reset capabilities.
The BiFIFO is available in a 48-pin DIP for IDT7252, and 52-pin
LCC and PLCC for IDT72520. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883,
Class B.
FUNCTIONAL BLOCK DIAGRAM
REA
APORT
ACCESS
CONTROL
BPORT
ACCESS
CONTROL
PROGRAMMABLE
FLAG
LOGIC
m:w
LDRER t
LDREW t
~""'----""~-II. Dao -Da8
18
FLG A
FLG a
FLG c
FLG D
Wa ort5Sl'"
"I1aor RIWat:.
COMMAND
STATUS
CON. REGO
CON. REG1
CON. REG2
CON. REG3
CON. REG4
CON. REGS
CON. REG6
CON. REG?
REO
ACJ<
eLK
A Option as Motorola Interface Mode.
t Available In IDT72S20
CEMOS and BiFIFO are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-2016/-2
1989 Integrated Device Technology. Inc.
S6-14S
[II
•
MILITARY AND COMMERCIAL TEMPERATURE RANGES.
IDT7252/1DT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
PIN CONFIGURATIONS
tfER
RfNA
'GSA
DAO
DA1
DA2
DA3
~
REO
DAll
DA12
DA13
ClK
DBO
DBl
DB2
DB3
DB4
RfNB
Vee
ITSB
GND
D B5
DB6
DB7
Dea
FLG A
FLG B
FLGe
FLGo
DA4
DA5
DA6
DA7
DA16
GND
Vee
ITSA
GND
DAB
DA9
DA10
DAll
DA12
DA13
DA14
DA15
DA17
DA4
DA3
DA10
ACT<
DA14
DA15
DA17
Ao
Al
FLG A
FLG B
L52-1
&
J52-1
DA2
DAl
DAO
'GSA
RfNA
~
'FlEW
REO
ACR
FLGe
FLGo
CLK
DBO
A l·
Ao
PLCC/LCC
TOP VIEW
DIP
TOP VIEW
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
1/0
Data A
I/O
Data inputs & outputs for 16-bits of the 18-bit Port A.
DA16 - DA17
Parity A
I/O
DA16 is parity bit for DAO - DA7. ~17is the parity bit for DAB - DA15 .
DBO- DB7
Data B
I/O
Data inputs & outputs for 8 bits of the 9-bit Port B.
DBB
Parity B
I/O
DBB is parity bit for D BO - DB7·
~A
Chip Select
I
Port A is access when chip select is LOW.
D"SA
Data Strobe
I
Port A is accessed when
ITSB
DataSrobe
I/O
R/WA
Read/Write
I
Controls Read or Write operation of Port A when D"SA is LOW.
R/WB
Read/Write
I/O
Controls Read or Write operation of Port B when ITSB Is lOW.
m=R
REW
Reread
I
Rewrite
I
Loads Write pointer with value of REW pointer when LOW.
DAO - DA1 5
DSA is LOW. thereby activating Read or Write based upon selection of R/WA-
Port B is accessed when ITS B is LOW.
Loads Read pOinter with value of Am pointer when LOW.
LDRER
Load Reread
I
Saves the Read pointer value in the Reread pOinter. Active HIGH input pin for ID172520. IDT7252 access
through internal register only.
lDREW
load Rewrite
I
Saves the Write pointer value in the Rewrite Pointer. Active HIGH input pin for ID172520. ID17252 access
through internal register only.
~
Reset
I
ID172520 is reset through hardware pin. power up or through bit on register. Reset for IDT7252
is performed on power up or through software command. During reset. both internal Read and Write
pOinters are set to the first location.
REO
Request
I
Port B input signal requesting a data transfer between B port and Peripheral through DMA handshake.
ACT<
Acknowledge
0
DMA handshake response to the active signal from REO input.
CLK
Clock
I
Input clock pin (70% duty cycle max.).
Ao. Al
Address
I
With CS A lOW. address lines and R/WA select one of the 6 modes. FIFO A- > B. FIFO B- > A. Direct
pass-through path. configuration registers. status register. and command register.
FlG A - FlG o
Flags
0
These four pins output four of sixteen flags (Empty. Empty + Offset. Full. Full-Offset) for A- > B. and for
B- > A in two polarities. Flags are programmed via the configuration registers.
Vee
Power Supply
Two power supply pins. 5V.
GND
Ground
Three GND pins at OV for ID17252. Four GND pins at OV for ID172520.
S6-146
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT7252/IDT72520 1 K x 18-BIT -2K x 9-BIT CMOS BIFIFO
RECOMMENDED DC OPERATING CONDITIONS·
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
RATING
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
MILITARY
COMMERCIAL
UNIT
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
4.5
5.0
5.5
V
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
Military Supply
Voltage
Oto +70
-55 to +125
°C
Vccc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
'-"H
Input High Voltage
Commercial
2.0
-
-
V
'-"H
Input High Voltage
Military
2.2
-
-
V
'-"L (1)
Input low Voltage
Commercial &
Military
-
-
0.8
V
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
mA
50
DC Output Current
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
. conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial'Vcc -- 5V -+10% TA - O°C to + 70°C' Military' Vcc - 5V -+10% TA -- -55°C to +125°C)
IDT7252L
1DT72520L
PARAMETER
COMMERCIAL
SYMBOL
TA = 35. 50, 80ns
MIN.
MAX.
TYP.
IIL(I)
-1
1
Input leakage Current (Any Input)
-
IDT7252L
IDT72520L
MILITARY
TA = 40, 50, 80ns
TYP.
MAX.
MIN.
-
-
0.4
V
160
-
120
170
mA
8
12
-
12
25
mA
-
2
-
-
4
mA
-10
IOL(2)
Output leakage Current
-10
-
10
-10
VOH
Output logiC "1" Voltage IOUT= -1mA
2.4
-
-
2.4
VOL
Output logic "0" Voltage lOUT = 4mA
-
-
0.4
ICC1 (3)
Average Vcc Power Supply Current
-
90
ICC2 (3)
Average Standby Current
(R = W = RST = FDRT = VIH )
-
ICC3(L)(3)
Power Down Current
(All Input = Vcc = -0.2V)
-
10
J.LA
10
J.LA
-
V
NOTES:
1. Measurements with 0.4 ~ '-"N ~ VOUT '
2. R ~ '-"H, 0.4 ~ VOUT ~ Vcc
3. Icc measurements are made with outputs open.
5V
AC TEST CONDITIONS
Input Pulse levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output load
CAPACITANCE
SYMBOL
CIN (3)
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
D.U.T
PARAMETER
Input Capacitance
COUT (2.3) Output Capacitance
:d
6800
UK
_ 30pF*
Figure 1. Output Load
(TA= +25°C, f = 1.0MHz)(1)
CONDITIONS
MAX.
UNIT
VIN = OV
8
pF
Vour= OV
12
pF
*Includes jig and scope capacitances.
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
3. Characterized values, not currently tested.
S6-147
UNIT
MILITARY ANDCOMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1 K x 18-BIT -2K x 9-BIT CMOS BiFIFO
AC.ELECTRICAL CHARACTERISTICS
(Commercial'Vcc -- 5V +10%
TA -- O°C to +70°C' Military' Vcc - 5V +10% TA -- -55°C to +125°C)
MIL.
MILITARY AND COMMERCIAL
COM'L.
SYMBOL
PARAMETER
7252x40
7252x50
7252x35
72520x40
72520x50
72520x35
MAX. MIN.
MAX.
MIN.
MAX. MIN.
7252x80
72520x80
MIN.
MAX.
UNIT
FIGURE
TIMINGS (A-Side 18-Bit)
taA
Access Time
35
-
40
-
50
-
80
--
ns
1
taRLZ
Read Pulse Low to Data Bus
at LowZ
5
-
5
-
5
-
10
-
ns
1.6
taRHZ
Read Pulse High to Data Bus
at High Z
-
20
-
25
-
30
-
30
ns
1.6
taDv
Data Valid from Read Pulse
High
5
-
5
-
5
-
5
-
ns
1.6
taRc
Read Cycle Time
45
-
65
-
100
-
ns
1
Read Pulse Width
35
-
50
taRPW
40
-
50
80
1
Read Recovery Time
10
-
10
-
15
ns
1
tasl
CS . A • A • R/W Set-Up Time
5
5
-
5
-
10
ns
1
taHl
CS • A. A • R/W Hold Time
5
-
-
ns
taRR
-
5
5
-
10
-
ns
1
taDs
Data Set-Up Time
18
-
20
-
30
40
-
ns
1.2
ns
1.2
taDH
Data Hold Time
0
-
0
-
5
ta wc
Write Cycle Time
45
-
50
-
65
tawpw
Write Pulse Width
35
40
Write Recovery Time
10
10
-
50
tawR
-
-
15
-
tawRCOM
Write Recovery Time after
Command
35
-
40
-
50
-
56-148
20
10
100
ns
1
ns
1.2
20
-
ns
1
80
-
ns
2
80
IDT7252/IOT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial· Vcc= 5V +10% TA = O°Cto +70°C· Military· Vcc= 5V +10% TA = -55°C to + 125°C)
COM'L.
SYMBOL
PARAMETER
MIL.
MILITARY AND COMMERCIAL
7252x35
7252x40
7252x50
72520x35
72520x40
72520x50
MAX. MIN.
MAX. MIN.
MAX.
MIN.
7252x80
72520x80
MIN.
MAX.
UNIT
FIGURE
TIMINGS (B-Slde 9-Blt)
tb A1
Access Time With No Parity
35
42
48
-
50
Access Time With Parity
-
40
tb A2
60
-
-
ns
3
90
ns
3·
tb RLZ
Read Pulse Low to Data Bus at
LowZ
5
-
5
-
5
-
10
-
ns
3.6
tb RHZ
Read Pulse High to Data Bus at
High Z
-
20
-
25
-
30
-
30
ns
3.6
tb ov
Data Valid from Read Pulse
High
5
-
5
-
tb Rc
5
-
10
-
ns
3,6
Read Cycle Time
45
Read Pulse Width
35
40
tb RR
Read Recovery Time
10
10
tb S1
R/W Set-Up Time
5
-
50
tb RPW
-
65
-
100
-
ns
3
-
50
-
80
-
ns
3
15
ns
3
10
-
ns
3
-
5
-
5
10
-
ns
3
18
-
20
30
40
3
-
0
-
ns
0
ns
3
Data Set-Up Time With Parity
22
25
3
0
-
ns
Data Hold Time With Parity
-
ns
3
100
-
ns
3
50
-
20
5
-
tb H1
R/W Hold Time
5
tb OS1
Data Set-Up Time With No Parity
tb OH1
Data Hold Time With No Parity
tb os2
tb OH2
80
-
ns
3
15
-
20
-
ns
3
5
80
tbwc
Write Cycle Time
45
-
50
tbwpw
Write Pulse Width
35
40
tbWR
Write Recovery Time
10
-
10
-
tbOSBH
Am. REW,
LDRER, LDREW
Set-Up and Recovery Time
10
-
10
-
15
-
15
-
ns
4
tbPER
Parity Error
25
-
25
-
30
-
30
-
ns
8
25
40
-
ns
5
16
-
ns
5
16
5
ns
5
5
-
ns
5
-
ns
5
25
-
35
-
ns
5
0
5
35
5
65
10
45
10
REQ-ACK (B-Slde 9-Blt)
tb CKC
Clock Cycle Time
17.5
-
20
tb CKH
Clock Pulse HIGH
6
-
8
tbCKL
Clock Pulse LOW
6
8
tbREOS
Request Set-Up Time
5
-
tbREOH
Request Hold Time
5
-
5
-
tbACKL
Delay From Rising Clock Edge
to ACK Switching
18
-
20
-
5
S6-149
10
10
10
10
MILITARY AND COMMERCIAL TEMPERATURERANGES
IDT7252/IDT72520 lKx 18·BIT-2Kx 9·BIT CMOS BIFIFO
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee= 5V ±10%, TA = O°C to + 70°C; Military: Vec =
5V ±10%, TA = -55°C to
COM'L
PARAMETER
SYMBOL
MIL
+ 125°C)
MILITARY AND COMMERCIAL
7252x35
7252x50
7252x40
72520x35
72520x50
72520x40
MIN.
MAX. MIN.
MAX.
MAX. MIN.
7252x80
72520x80
MAX.
MIN.
UNIT
FIGURE'
BYPASS MODE
tb BYA
B- > A Bypass Access
20
25
30
40'
ns.
tb BYD
B- > A Bypass Delay
15
17
20
30
ns
6
tb BYH
B- > A Data Hold
5
5
5
10
ns
6
tb BYA
A- > B Bypass Access
20
25
30
40
ns
6
tb BYD
A- > B Bypass Delay
15
17
20
30
ns
6
5
5
"
10
ns
6
tb BYH
A- > B Data Hold
FLAGS TIMINGS
6
tb REF
ti LOW to ~ LOW
35
35
45
60
ns
7
tb wEF
W HIGH to ~ HIGH
35
35
45
60
ns
7
tb RFF
ti HIGH to ~ HIGH
35
35
45
60
ns
7
tb WFF
W LOW to Ft= LOW
35
35
45
60
ns
7
tb RAEF
ti Low to Almost ~ LOW
50
50
60
75
ns
7
tb WAEF
W High to Almost ~ High
50
50
60
75
ns
7
tb RAFF
ti High to Almost J!J= High
50
50
60
75
ns
7
tb WAFF
W Low to Almost Ft= Low
50
50
60
75
ns
7
NOTE:ti or W is Internal signal derived from DSA & RIWA or USB & RIWB.
S6-150
--------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT7252/IDT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
----~
V----
~I
X~-
I
I
~I------------------------------------~----------~I
~~:--------~------------------~I------~~
,~I----------------------~"r---
!1~ tas1 - ,I
!1
1
taH1 - ,
READ
CSA=
0; A1 = 0, Ao= 0
RiWA= 1
~1-~-----------------------taRc------------------------~_1
~taRR
1
----_I
.1
1
I
~~I_ _ _ _ _ _ _ _ _ _ta_R_PW_ _ _ _ _ _ _ _~·V
1
1
1
Output: D A (17:0)
1
~
- I
L-,,,,, ~DQQq
i
1
"-- taDV -1
1
I-
'------
I~--________________.!____~~~~I
·1
taA
2pOa
~
tbAl
:
I
I
I~-------
~~----~
!.~I
I
tbov----1
I
I
-I
r--- tbRHZ-.,
Case 2: When access controls RiWsand USs are programmed as "FiB and Ws
Ws = 1
Rs
DB (8:0) With Parity
~1.~------------------------tbRc-------------------------~
.. 1
I
I
I..
I
--~~.
1/r-------~l
,---------------- tbRPW-----------·~r
:
' - - tbRLZ
I
II
I
tb~R----".1
bcx>a
~
I
I
tbA2
-I
:
!.I
I
I
~~----~
tb ov----1
I
r--- tbRHZ-.,I
Figure 3. Read and Write Timings (B-Side)
56-152
~~________
1DT7252/IDT72520 1K x 18-BIT -2K x 9-BIT CMOS BIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Case 1: Access controls are RtWe and DSe
--1
~~I_ __ _
I
I
----+f_:
~:I--"-1--1_ _---tIM-I
'FfE"R: or REW
toseH
toseH
LDRER or LDREW
Case 2: Access controls RtWe and DSe pins are programmed as]:fe and We
WeorRe
--J
I
I
R'ERorREW
:4
-I
I
toseH
~
II
-:
I
[II
I
I
LDRER or LDREW
I
toseH
I
Figure 4. Reread, Rewrite, Load Reread, Load Rewrite Timings (B-Slde)
I.
2 to 5 cycles:------..Irl
~tCKC-"':
I+- tcKH
I
CLK
REQ
t
-1.~
:
I
tREOS
I
I
I
--I, - tcKL --tI
----..If
I
~ 1 cycle-e- - _..:...-
I
1 to 2 CYCles--J
I
I
I
I
I
I
~
I
~I------~----------~-----------------------I
I
~
I
tREOH
I
I
------------------~--~
,
I
I
I
I
I
I
\!~
DSe
I
I
I
I
I
I
I
I
I tAcKL-",
I+-
~
r- tACKL....,I r-,
tAcKL- ,
I
I
I
I
~
-------------------------------------~:----~
r
:t-
1
r-- tACKL--1
0Sa
r-r-/1
I
r--
: "
I
Note: Depends on the Intel or Motorola mode bit, BiFIFO either generates
I
r-tACKL-i
and R~ or]:fe and
WB
Figure 5. Request and Acknowledge Timings (B-Slde Only)
S6-153
__..._- ...........-
.
... _.-.........
__
_-_._. __ ._. __ __ ---_._ ..... .__.._ - - - - - - .
..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1 K X 18-BIT -2K X 9-BIT CMOS BIFIFO
BYPASS
A-B
CSA
A, = 1, Ao = 1
RtWA= 1
i00i_1-----
ta BYH ----.-.I_I
-----,~I------------------.~!________~~
DB
(8:0)
I
----~:--------------,---i====:====::===========:,:======
1
I
1
:
1'-
I
1
I
I
I
I
~XXXI'r--+-!--¥"======:Xi:XXX:==J. . .- ·1
I-I
l.- ta ov--l
I
I
I taBYO 1
I
I
I.- ta RLZ-.,
I
I·
j4-taRHZ~
-I
taBYA
A-B
CSA=O
A,
= 1. Ao = 1
R/WA= 0
I.
tbBYH
-----_~,
------~~~I----__------------!~------~V
1
I
I
--------~I---------D-a-ta-A-----,-----X~--D-a-ta-B----~l----------------,-----I
DB
(8:0)
:
1
(XXXX
\ . - tbRLZ-.i
1
I-
:
I
tbBYA
I
Da~A
I
I"
1
1
-I
~
-I
tbBYD
Figure 6. Bypass Timings
S6-154
1
1
I
I
I
\.- tbov-+i
I
DataB
--
~XXXJ)-1
1
j4---tbRHZ
I
-I
MILITARY AND COMMERCIAL TEMPERATURERANGE5
IDT7252/1DT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
FIFO B -
A: Empty and Full Flags
RtWA= 1
l
,
I (
)
Read FIFO
f------I
L-_w_rit_e_F_IF_O_...Ir~L._w_rit_e_F_IF_O_
...
,,
/1
'l5Sa
' J - I-----I
I
H
I
tWFF
I
I
I
I
r--t
I
"
I
I
I
I
I
r
1.--1
I
i
I
teeF
tWEF
I
Note: tRAEF' tWAEF • t RAFF • tWAFF are the same to the above timings.
FIFO B - A: Empty and Full Flags
R/Wa = 1
'l5Sa
RJWA
DSA
~
~
l
;
,
II
Read FIFO
I
I
I
I
I
I
I
'I
Write FIFO
Write FIFO
II
},
I
I
I
I
I
I
I
I
~
I tWFF I
I
I
r----I
tREF
I
j
II
},
~
tWEF
Note: t RAEF• tWAEF • t RAFF. tWAFF are the same to the above timings.
Figure 7. Flag Timings
56-155
:. I
I
I
1---1
:rI tRFF I
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IDT7252/1DT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
PARITY ERROR
Set Parity Error: Flag A is programmed to output read or write parity error on B side
L>Se
Flag A
Clear Parity Error: By issuing a command on A side
:
Flag A
1
I
I
""'1-1---- tpER - - - -....1
Figure 8. Parity Timings (B-Side Only)
S6-156
IDT7252/IDT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BiFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED BLOCK DIAGRAM
CONFIG. REG. 5 - - - . -
~TRc~I~~~
INTERNAL
CONTROL
PORT B
CONTROL
FIFO
(A TO B)
1Kx 18
READ
PORT
9-BIT PORTB
Deo - DBa
18-BIT PORT A
DAD - DA17
1
...t-!.........1-_,.a"""__I -..
1a
FLAGS
READ
PORT
FLAG LOGIC
PROGRAMMABLE
L--_ _ _ _--II+-----'-~
FIFO
(BTOA)
1Kx 18
WRITE
PORT
COMMAND
STATUS
CON. REG 0
CON. REG. 1
CON. REG. 2
CON. REG. 3
CON. REG. 4
CON. REG. 5
CON. REG. 6
CON. REG. 7
S6-157
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1 K x 18-BIT -2K x 9-BIT CMOS BIFIFO
full-offset) per FIFO, can be multiplexed Into four flag pins.
• Parity: Parity generate or check on port B.
• Pass-Through: On-chip transceiver to pass through the FIFOs
for direct and synchronous communication between two data
ports.
• Odd Byte: 8 bits can be read Into port B without using FIFO. An
odd byte written into B port can be accessed by reading
STATUS register.
These features can be selected by programming a set of six Intemal Configuration Registers or by "executing a command" from
port A. There are six possible modes of operation from port A, depending on GSA, and A1 and Ao pins:
1. Port A disabled (GSA =0).
2. FIFO access.
3. Direct access to port B, pass through FIFOs.
4. Program Configuration Registers.
5. Read Status Registers.
6. Carry out a command.
FUNCTIONAL DESCRIPTION
FIFOs are used to link processors and peripherals together
asynchronously to transfer data. Often the data on each side must
be passed in both directions and requires two FIFOs arranged
side-by-slde. Furthermore,CPUs are usually 16 or 32 bits wide
while peripherals' width is typically 8-bit, causing a mismatch in
bus bandwidths. The BiFIFO is an integrated solution to this class
of applications: offering both asynchronous bidirectional data buffering and bus matching capabilities.
The BiFIFO contains two 1K by 18 FIFOs connected side by
side to two data ports: A and B. Port A is 18-bit wide while port B,
with a 2-to-1 multiplexer, Is 9-bit wide. A word (2 bytes) written Into
port A requires two reads from port B to retrieve both bytes. Similarly, a word is sent Into port B one byte at a time and read as a
whole word form A side.
The BiFIFO also contains several innovative, programmable
features:
• Width Expansion: Width expandable to match 32-bit to 8-bit
buses configuration by using two BiFIFOs, programmed as
"Master" and "Slave" devices; or match 32-bit to 16-bit buses
configuration by using 2 BiFIFOs.
Reset
• DMA Style Handshake: Option available on port B side to
control read and write activities when connected to peripherals
with REQUEST and ACKNOWLEDGE kind of handshake.
• Block Transmit: Capability to Reread and Rewrite from port B.
• Flags: Four empty, full and programmable flags (empty + offset,
IDT72520 can be reset through hardware pin, power up or
through bit on register. Reset for IDT7252 is performed on power
up or through software command, no hardware pin is available.
During reset, both Internal Read and Write pOinters are set to the
first location.
Width Expansion
., ~ D (31 :0) & PARITY
36 •
,,
~.
18 •
vD
r
a.
, ;D (15:0) & PARITY
(31:16) & PARITY
18 •
DA (17:0)
DA (17:0)
BiFIFO
(MASTER)
-...
L>SB
R/WB
CK
ACR
DB (8:0)
REO
..
--=---
...
,~
BiFIFO
(SLAVE)
....
L>SB
....
CK
R/W B
DB (8:0)
.
4~,
~,
9
I
, ,9
"
CLOCK
GENERATOR
.~,
II
I
REO
" l'
9
"
ACR [)SB R/W B
PERIPHERAL
"
DB (8:0)
I
Figure 9. 32-Blt to 8-Blt BIFIFO EXPANSION (peripheral mode)
S6-158
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1 K x 18-BIT -2K x 9-BIT CMOS BIFIFO
In the 32-8 expansion configuration (for both CPU and peripheral modes) the byte arrangement on the A side and data access on
the 8 side is as follows:
A SIde:
The byte arrangement: (BYTE-ORDER bit in CONFIG. register is programmed as 0)
D (31:24)
BYTE 3
I
D (15:8)
BYTE 1
D (23:16)
BYTE 2
D (7:0)
BYTE 0
SLAVE BiFIFO
MASTER BiFIFO
B SIde:
I
The order of data being accessed: (SLAVE BiFIFO is always read or written first)
'[)gB
DB (8:0)
~....._ _BYT_E_O_ _...X..._ _B_YT_E_1_ _...X,.._ _B_YT_E_2_,--,X~_ _B_YT_E_3____X,.._ _ _ _ __
devices such as CPUs which can generate read and write strobes,
or less intelligent devices such as peripherals which require that
read and write strobes be generated for them (see Figure 10).
DMA Style Handshake Mechanism
There are two operational modes for the 8-bit (port 8) interface.
The modes are tailored to facilitate connection with intelligent
R/WB
RtWA
t5SA
CPU INTERFACE MODE
CPU
BiFIFO
16
CPU
8
,
,
R/WB
RtWA
DMA MODE
(Peripheral Interface)
'[)gB
'[)gA
CPU
'[5gB
BiFIFO
REO
PERIPHERAL
ACR
16/3~
8
L
Figure 10. Interface Modes
The 8iFIFO responds to an active signal on the REQ input by
strobing the ACK and DS B lines and asserting the RiWB output. All
timing is relative to a shift register clock generated by ClK or ClK
divided by two. When in the DMA (peripheral) mode and the passthrough buffers are used for synchronous transfer, the read/write
strobe from the A port are passed through to the 8 port.
In the Generate mode, the ninth bit of data on the 8 side of the
A- > 8 FIFO is ignored and the Parity Check is disabled. The parity
generate circuit output is placed on the ninth bit of the Data 8 bus
output during a data transfer from the A- > 8 FIFO On writing into
the 8- > A FIFO from the Data 8 bus the parity is generated and
stored.
The pass-through bus is treated in the same way thatthe FIFO
data is treated.
a
Parity
The 8iFIFO supports parity in two fashions: Check or Generate
In the parity check mode, the parity check circuitry monitors
data passed through the Data 8 bus and sets the parity error flag.
While transferring data from the Data 8 bus into the 8- > A FIFO, an
error sets the Write Parity error flag. Transferring the data from the
A- > 8 FIFO through the Data 8 bus, an error sets the Read Parity
error flag. The OR of these two flags is available as an option for
output on the flag A pin.
Pass-Through (Synchronous Access)
The 8iFIFO includes a unique data path that bypasses the
FIFOs such that a processor can talk synchronously with the peripheral to initialize it and then communicate asynchronously via
the FI FOs. The parity generate and check circuitry (if selected) also
comes into play during the synchronous transfer of data via the
pass-through buffers. When in the peripheral (DMA) pass-through
S6-159
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IOT7252/IOT72520 1 K x 18-BIT -2K x 9-BIT CMOS BiFIFO
REGISTER DESCRIPTION
mode, the DSs and R/Ws pins are outputs and reflect the action of
the DS Aand R/WA inputs. Only lower byte DA (16) and DA (7:0) are
passed-through to Os (8:0). In the 32-8 expansion configuration,
when using the bypass mode, the Master device should be in DMA
mode while the Slave should be in CPU mode, so that only the
Master's transceiver is activated. During regular FIFO read and
write modes, both master and slave should be in DMA mode. REQ
should be low during initialization of BiFIFO and peripheral.
CSA
Address Control
The address lines indicate the resource to be accessed. There
are six items that can be accessed: the FIFO B- > A, FIFO A- > B,
8-bit data bus, the flag configuration registers, status and command (see Table 1).
WRITE
READ
Al
Ao
0
0
0
FIFO B->A
FIFO A->B
0
0
1
8-bit bus direct
8-bit bus direct
0
1
0
Configuration Register
Configuration Register
0
1
1
Status
Command
1
X
X
X
X
-
Note: Port B use DSs and R1W3 in the same way that Port A generates
internal strobes.
Table 1. Address Control for Port A.
Command Register
registers in an idle condition. The command port format and a list
of commands is shown in Table 2. The commands are accessed
through the command port (AI, Ao = 11).
The command feature allows the user to direct the BiFIFO to do
something in real-time rather than setting up configuration
15
I
12 11
XXXX
I
8 7
Opcode
I
Opcode
3 2
XXXXX
I
Operand (1)
0/
I
Reset BiFIFO functions (see operands)
1
Select Configuration Register (see Table 3)
2
Load Read point with Reread pOinter value
3
Load Write pOinter with Rewrite pOinter value
4
Load Reread pOinter with Read pOinter value
5
Load Rewrite pointer with Write pointer value
6
Set DMA transfer direction (see operand)
7
Select Status register format (operand)
8
Increment read pointer on B side
9
Increment write pointer on B side
A
Clear write parity Error flag
B
Clear read parity Error flag
000
Function
No operation
-----------------f-----001
Reset FIFO B- > A (Read, Write, and Rewrite
pointers)
-----------------f-----010
Reset FIFO A- > B (Read, Write, and Reread
-~~~~------------f-----011
Reset B->A and A->B
-----------------f-----100
_
__________
f-----101
-~~~~~-----------f----110
No operation
Function
0
Operands (1)
\
~e~e~R~O~i~~ry
r----111
~
XXO
----XX1
XXO
-----XX1
-----------------Reset all (2)
Write FIFO B->A
-----------------Read FIFO A- > 8
Status format 0 (see Table 7)
-------------~---Status format 1 (see Table 7)
NOTES:
1. If o~erands are ':1?t shown for opcode, then they are in
don t care condition.
2. Reset both FIFOs, REO, Configuration Registers 0,1 ,2,3,5,7.
Reset Configuration Register 4 to default. D MA direction
B--A. Clear parity error flags. Select Status Format O.
Table 2. Command Function and Operand
Configuration Registers
Several configuration registers control the BiFIFO operation
(Table 3). The configuration registers are accessed by executing a
command to pOint to a particular location, then reading or writing
the content via address 2 (AI, Ao = 10). On reset, all registers, except Register 4 (Table 3, 4), default to Zero.
56-160
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1Kx 18-BIT-2K x 9-BIT CMOS BiFIFO
Operands
000
001
Selection
10
15
o
9
A- > B Empty
Reg 0:
15
10
9
15
10
9
Reg 2:
011
Reg 3:
100
Reg 4:
101
Reg 5:
Offset
o
A- > B Full - Offset
Reg 1:
010
+
o
B- > A Empty
10
15
+
Offset .
o
9
B- > A Full - Offset
15
12
7
8
11
Flag 0
4
Flag C
o
3
Flag B
Flag A
o
15
I
General Control
o
15
110
Reg 6:
111
Reg 7:
Reserved
o
15
Parity Function
Note: 0110 0100 0010 0000 is default for Register 4. All others default to O.
Table 3. Configuration Registers
Configuration Registers 0 through 3:
These program the offset for the almost empty and almost full flags. The
values in these registers are unsigned positive numbers.
Configuration Register 4:
This is used to select internal flags for the external flag pins A through D.
The register is divided into four fields of four bits each. The four bit fields not
only select which flag to output but also the polarity at the output. This creates an easier interface to processors and peripherals (see Table 4).
SEL
SELECTED FLAG
0000
Empty A->B
0001
!:mpty
0010
~
+
1000
Offset A- > B
0011
Full - Offset A- >
0100
Empty B->A
+
0101
Empty
0110
'FLilT1r->A
0111
FulHJffset
SELECTED FLAG
SEL
8
Offset B- > A
8- >"A
Empty A->B
Empty
1010
Full A-> B
Offset A- > B
1011
Full - Offset A- > B
1100
Empty B->A
+
1101
Empty
1110
Full B->A
1111
Full-Offset B->A
Table 4. Flag Polarity and Selection Codes
56-161
+
1001
Offset B- > A
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IDT7252/IDT72520 1 K x la·BIT -2K x 9·BIT CMOS BIFIFO
Configuration Register 5:
FUNCTION
BIT
0
1
This contains fields to control various functions (see Table 5) .. '
Select: DS e & RN/e or Re & We
Byte order of 16·bit word
0
Provides the strobes as R e & We (Intel Mode)
1
DS e & RN/ e (Motorola Mode)
0
Lower byte DA (7:0) of a word is read or written
first on Port B
1 - - ~------------------
~- ~------------------
Higher byte DA (15:8)
1
2
Enable Reread
Disable Reread
0
~- ~-----------------Enable Reread
1
3
Enable Rewrite
~-
4
REO polarity
~-
5
ACK polarity
1 - - ~------------------
6-7
REO/ACK Timing
1 - - ~--~---------------
0
1
0
1
Disable Rewrite
~-----------------Enable Rewrite
REO active HIGH
~-----------------REO active LOW
0
ACK active LOW
ACK active HIGH
1
.A. & ACR T
.A. & ACR T
4 clock cycle between REO .A. & ACR T
5 clock cycle between REO .A. & ACR T
00
2 clock,cycle between REO
01
3 clock cycle between REO
10
-------------------11
0
Read and write strobe: 1 cycle LOW
-------------------Read and write strobe: 2 cycle LOW
1
8
Read & Write Strobe
9
Clock Frequency (Internal)
-- -------------------
10
Interlace Mode Select
~-
Expansion Mode
1-- ~------------------
0
CLK signal generates the REO/ACK sequence
1
CLK Signal divided by two
0
1
CPU interlace mode
~-----------------DMA (peripheral interlace) mode
00
11-12
Standalone mode
01
Reserved
10
Expanded least significant (Slave)
1-- ~------------------
11
(Expanded most significant (Master)
Note: All default to O.
13
Unused
14
Unused
15
Unused
Table 5. Register 5 Format
Configuration Register 6:
This register is unused.
S6-162
------~
--
-----~-------
- ----.----..-------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT7252/10172520 1Kx 18·BIT-2Kx 9·BIT CMOS BIFIFO
Configuration Register 7:
BIT
0-7
This is used to select parity functions (Table 6).
FUNCTION
Unused
8
Parity in Control
B->A
Disable Parity Generate; Enable Parity Check
0
1-1------------------Enable Parity Generate. Disable Parity Check
9
Parity Out Control
A->B
Disable Parity Generate. Enable Parity Check
1-~-----------------Enable Parity Generate. Disable Parity Check
1
10
Parity
Odd/Even
0
Odd
1-~-----------------Even
1
11
Select Parity Error
on Flag A pin
0
No Parity Error
1-~-----------------1
Parity Error
15-12
1
0
Note: All default to O.
Unused
Table 6. Parity Function
Status Register
There are two formats for the status register (Table 7) which are
selected using the Select Status Format command (opcode 7 of
Table 2). Once a format has been selected it remains in force until
reprogrammed by the select command.
Bit
Status Register Format 0
Bit
Status Register Format 1
0
0
Reserved
1
1
Reserved
2
2
Reserved
3
DMA Direction
4
4
A->B Empty
5
5
A- > B Empty
6
6
B->A Full
3
Even Byte Latch Bits 0-7
+
Offset
7
B- > A Full - Offset
8
Valid Bit
8
Valid Bit
9
Write Parity Error
9
Write Parity Error
10
Read Parity Error
10
Read Parity Error
11
Status Format: 0
11
Status Format: 1
12
A->B Full
12
A->B Full
13
A- > B Full - Offset
13
A- > B Full - Offset
14
B->A Empty
14
B->A Empty
15
B- > A Empty + Offset
15
B- > A Empty
7
I
I
I
I
I
Note: All default to O.
Table 7. Status Register Format
S6-163
+
Offset
IDT7252/IDT72520 1Kx 18-BIT-2Kx 9-BIT CMOS BIFIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
On reset and the default condition, the format 0 is selected.
Once a format has been selected, the register is read via address
Al ,Ao =11.
In format 0, bits 0 through 7 are the contents of the odd byte
latch. Taken together with the valid bit (bit 8), the processor can
determine if there is a byte written into the BiFIFO and what the
byte is. When Bit 8 = 0, a byte is written into the BiFIFO but not yet
in the B- >A FIFO memory.
In format 1, bits 0 through 2 are reserved. Bit 3 is the DMA direction selected via the command register: 0 for A- > Band 1 for
B- > A. Bits 4 to 7 reflect the status FIFOs on the Data B side.
The reset of the bits are the same for format 0 and 1. Bit 9 is the
Write Parity Error flag active High. The Write Parity Error flag is
associated with data written into the B->A FIFO on the Data B
bus. Bit 10 is the Read Parity Error flag active High. The Read Parity Error flag is associated with data read from theA- > B FIFO on
the Data B bus. The parity error flag once set remain set until
cleared using the clear parity error commands. Bit 11 is the status
format selected. The status format verifies the present Status
Register Format the user is in. Bits 12to 15 reflect the Data Aside
of the FIFOs.
ORDERING INFORMATION
IDT
XXXX
Device Type
A
Power
999
Speed
A
Package
A
Process/
Temperature
9
Ran..._e_ _ _ _ _ _-I :LANK
Commercial (O°C to + 70°C)
1
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8
1
C
~------------------~
~
____________________
~
JP
L
35
40
Sidebraze (600 mil)*
Plastic DIP*
Plastic Leaded Chip Carrier +
Leadless Chip Carrier+
Access Time (fA)
Commercial OnlY}
Military Only
Speed in Nanoseconds
50
80
~--------------------------~II
L
Low Power
7252
1K x 18-8it & 2K x 9-8it 8iFIFO in 48-pin
package
1K x 18-8it & 2K x 9-8it 8iFIFO with added
hardware in 52-pin packages
72520
*IDT7252 Only
+ IDT72520 Only
S6-164
t;)
1K x 18-BIT
Integrated Deviceledmology.lnc.
PRELIMINARY
lOT 72521
CMOS BiFIFO
processor and peripheral. With access speed of 35ns, the BiFIFO
can improve system performance of the peripheral interface by virtue of its concurrent transfer capability. The BiFIFO can handle
data transfer between 16-bit to 16-bit or 32-bit to 32-bit buses.
Both ports, organized in 1K x 18-bit, can be operated concurrently, essentially operating as two FIFOs in one chip. A data passthrough mode allows for command and status transfer between
two devices. To improve system performance when interfacing to
peripherals which support DMA operations, a Request (REO) and
Acknowledge (ACK) handshake is included.
Four external flag pins can be used to configure and access any
one of sixteen internal flags (four in each FIFO with both positive
and negative polarity). The four internal flags. are Empty,
Empty + Offset, Full and Full-Offset. The offset value and flag polarity can be programmed through internal registers.
The BiFIFO incorporates Reread (RER) and Rewrite (REW).
The internal read and write pointers can be set by the user through
a control registe~n Signaling the RER input, the read pointer is
set with value of RER pointer and data is read again. With signaling
REW , the write pointer is set with value of REW pointer and data is
written again. These internal read and write pointers can be set by
the user through a control register. In addition, the BiFIFO has
hardware Load Reread, Load Rewrite and Reset capabilities.
The BiFIFO is available in a 68-pin PGA and 68-pin LCC and
PLCC packages. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FEATURES:
• Bi-directional First-In/First Out (FIFO) memory
• Back-to-back 1K x 18-bit FIFO organization
• 35ns access time
• Facilitates processor-to-peripheral and processor-to-processor
communication
• Matches bus widths: 16-bit to 16-bit and 32-bit to 32-bit buses
• Asynchronous and simultaneous read and write operations
• Width expandable to 36 bits
• Six general purpose programmable I/O pins
• Hardware Reread and Rewrite
• Hardware Load Reread and Load Rewrite for data
retransmission
•
•
•
•
•
Hardware Reset
Built-in pass-through path
On-chip DMA for easy peripheral interfacing
Available in 68-pin PGA, and 68-pin LCC and PLCC
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72521 BiFIFO is a compact, highly integrated solution
for simplifying data transfer between two processors or a
FUNCTIONAL BLOCK DIAGRAM
GSA
DS A
RflJ A
Ao.1
APORT
ACCESS
CONTROL
BPORT
ACCESS
CONTROL
1Kx 18
FIFO
A -> B
16
"FfER
We
tie
ro:w
LDRER
LDREW
1Kx 18
FIFO
B -> A
~I-~
FLGA
FLGe
FLGc
FLGo
PROGRAMMABLE
FLAG
LOGIC
16
______________
~-I~PROG~~SMABLE
COMMAND
STATUS
CON. REGO
CON. REG1
CON. REG2
CON. REG3
CON. REG4
CON. REG5
CON. REG6
CON. REG?
PIOo -PI05
RESET
LOGIC
DMA
INTERFACE
CONTROL
~~.
REa
ACK
CLK
CEMOS and BiFIFO are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1969 Integrated Device Technology, Inc.
\
JANUARY 1989
OSC-2016/2
S6-165
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101"72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
PIN CONFIGURATIONS
Ao DA15 DA13 DA11
DB13 DB14 DB17 FLGB FLGc
INDEX
WUWWWUUUliUUUUUUUU
DB11 DB12 DB15 FLGA FLGc
A1
DB9 DB10
DA9 DA10
GND DB8
PI03 DAB
~B GND
GND
LD
RER
Vec
r5SA
DB7 DB16
GND
~
DB5 DB6
PI02
LD
REW
DB3 DB4
DA7 DA16
DB2 DB1
CLK REO ~ R/WA PIOri DAO DA2 DA5 DA6
R/WB Vec
,
DBO
G68-1
ACR R"EW
9 8 7 6 5 4 3 2 U 68 67 66 65 64 63 62 61
] 10
1
60 [:
:1 11
59 [:
]12
~ [:
] 13
57 [:
]14
~ [:
] 15
55 [:
] 16
~ [:
J 6 8 - 1 5 3 [:
~ :1 17
]
18
&
52
[:
Vec
L68-2
51 [:
USA ] 19
ro[:
GND ]~
~[:
LDRER ]~
~[:
PI03 ]~
U[:
DA8 ]~
~[:
DA9 ]~
~[:
DA10 ]~
U[:
PI04 ]~
272829 30 313233343536 37 3839 40414243
DA17 DA14 DA12 PI05 PI04
DAS
DA6
DA7
DA16
PI02
LDREW
GND
DB2
DB3
DB4
DBS
DB6
DB7
DB16
R/WB
Vee
~B
GND
GND
DB8
DB9
DB10
DB11
DB12
GND GSA PIOl DA1 DA3 DM
PGA
TOP VIEW
LCC/PLCC
'TOPVIEW
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
I/O
DAO - DA17
Data A
1/0
Data inputs & outputs for 18-bit Port A.
1/0
Data inputs & outputs for 18-bit Port B.
D BO - DB17
Data B
GSA
Chip Select
I
Port A is accessed when chip select is LOW.
~A
Data Strobe
I
Port A Is accessed when ~A is LOW. thereby activating Read or Write based upon selection of R!WA-
~B
Data Srobe
1/0
R!WA
ReadIWrite
I
Controls Read or Write operation of Port A when ~A Is LOW.
I/O
Controls Read or Write operation of Port B when ~B is LOW..
Port B is accessed when US B is LOW.
R!WB
ReadIWrite
~
Reread
I
R"EW
Rewrite
I
Loads Write pOinter with value of R"EW pointer when LOW.
LDRER
Load Reread
I
Saves the Read pointer value in the Reread pointer.
LDREW
Load Rewrite
I
Saves the Write pOinter value in the Rewrite Pointer.
~
Reset
I
Reset is performed through hardware pin. power 'up Or by a bit in an internal register. During reset. both
internal Read and Write pOinters are set to the first location
I
Loads Read pOinter with value of REA pOinter when LOW.
REO
Request
ACR
Acknowledge
0
DMA handshake response to the active signaL from REO input.
Port B input signal requesting a data transfer between B port and Peripheral through DMA handshake.
CLK
Clock
I
Input clock pin (70% duty cycle max.).
Ao.Al
Address
I
With GSA LOW. address lines and RIWA select one of the 6 mbdes. FIFO A->B. FIFO B->A. Direct
pass-through path. configuration registers. status register. and command register.
FLG A - FLG D
Flags
0
These four pins output four of sixteen flags (Empty. Empty + Offset. Full. Full-Offset) for eitherA- > B. or
for B- > A in two polarities. Flags are programmed via the configuration registers.
Six general purpose programmable pins as either input or output ports.
PIOo - PI05
Program Bits
Vee
Power Supply
Two power supply pins. SV.
GND
Ground
Five GND pins at OV.
I/O
",
S6-166
...
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
SYMBOL
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature'
Oto +70
-55 to +125
°C
TslAs
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-65 to + 155
-55 to +125
MIN.
TYP.
MAX.
UNIT
Military Supply
Voltage
4.5
5.0
5.5
V
Vccc
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
"'IH
Input High Voltage
Commercial
2.0
-
-
V
"'IH
Input High Voltage
Military
2.2
-
-
V
"'IL (1)
Input Low Voltage
Commercial &
Military
-
-
O.S
V
°C
-mA
50
DC Output Current
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
I
dfuncf
rIon 0 fth e deVlcea
·
tth eseor any 0 th er
rati ngonyan
lonai
opera
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PARAMETER
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc= 5V ±10%, TA = O°C to + 70°C; Military: Vee = 5V ±10%, TA = -55°C to + 125°C)
IDT72521L
COMMERCIAL
TA = 35, 50, SOns
MIN.
TYP.
MAX.
PARAMETER
SYMBOL
MIN.
-
V
0.4
V
160
-
120
170
mA
S
12
-
12
25
mA
-
2
-
-
4
mA
Input Leakage Current (Any Input)
-1
-
1
-10
IOL(2)
Output Leakage Current
-10
-
10
-10
VOH
Output Logic "1" Voltage 10UT= -1mA
2.4
-
2.4
VOL
Output Logic "0· Voltage lOUT = 4mA
0.4
leel(3)
Average Vee Power Supply Current
-
90
lee2(3)
Average Standby Current
(if = W = RST = FLtRT
-
lee3(L)(3)
Power Down Current
(All Input = Vee = -O.2V)
-
10
~
10
~
NOTES:
1. Measurements with 0.4 ~ "'IN ~ VOUT.
2. R;:: "'IH' 0.4 ~ VOUT ~ Vee
3. Icc measurements are made with outputs open.
5V
lAC TEST CONDITIONS
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
D.U.T
CAPACITANCE
I SYMBOL
I
I
CIN (3)
PARAMETER
COUT (2.3) Output Capacitance
1.1K
30pF*
Figure 1. Output Load
(TA= +25°C, f = 1.0MHz)(1)
Input Capacitance
~
6800
[
CONDITIONS
MAX.
UNIT
VIN = OV
8
pF
VOUT= OV
12
pF
* Includes jig and scope capacitances.
NOTES:
I
1. This parameter is sampled and not 100% tested.
'~. With output deselected.
3. Characterized values, not currently tested.
I
S6-167
--------_._... _._-------_._._----
UNIT
-
IIL(l)
= VIH)
IDT72521L
MILITARY
TA = 40, 50, SOns
. MAX.
TYP.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT72521 CMOS BIDIRECTIONAL FIRST·IN/FIRST·OUT FIFO
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vec== 5V ±10%. TA == O°C to + 70°C; Military: Vee ==
PARAMETER
SYMBOL
FIG.
5V ±10%. TA == -55°C to
+ 125°C)
COM'L.
MIL
72521x35
MAX.
MIN.
72521x40
MIN.
MAX.
MILITARY AND COMMERCIAL
72521x50
MIN.
MAX.
72521x80
MIN.
MAX.
UNIT
TIMINGS (A·Slde 18·Blt)
taA
Access Time
1
35
-
40
-
ns
1,6
5
-
5
5
-
80
Read Pulse Low to Data Bus at Low Z
-
50
taRLZ
110
-
ns
taRHZ
Read Pulse High to Data Bus at High Z
1.6
-
20
-
25
-
30
-
30
ns
taov
Data Valid from Read Pulse High
1.6
5
5
5
-
5
-
ns
50
-
65
-
100
50
-
80
-
10
10
30
-
40
-
5
-
10
-
ns
65
-
100
ns
-
20
-
ns
80
-
ns
ta RC
Read Cycle Time
1
45
-
taRPW
Read Pulse Width
1
35
-
40
taRR
Read Recovery Time
1
10
-
10
taSl
GSA. A l • Ao. R/WA Set-Up Time
1
5
5
taHl
GSA. Al • Ao. R/WA Hold Time
1
5
-
5
taos
Data Set-Up Time
1.2
18
-
20
taOH
Data Hold Time
1.2
0
-
0
tawe
Write Cycle Time
1
45
-
50
tawpw
Write Pulse Width
1.2
35
40
taWR'
Write Recovery Time
1
10
-
tawRCOM
Write Recovery Time after Command
2
35
-
40
S6-168
10
-
15
5
5
50
15
50
20
80
ns
ns
ns
ns
ns
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
AC ELECTRICAL CHARACTERISTICS
(Commercial'Vcc = 5V +10% TA = O°C to + 70°C' Military' Vcc =
PARAMETER
SYMBOL
FIG.
-
5V +10% TA = -55°C to
COM'L.
72521x35
MIN.
MAX.
+ 125°C)
MILITARY AND COMMERCIAL
MIL.
72521x40
MIN.
MAX.
72521x50
MIN.
MAX.
72521x80
MIN.
MAX.
.
TIMINGS (B-Side 9-Bit)
tb A
Access Time
tb RLZ
Read Pulse Low to Data Bus at Low Z
UNIT
40
-
50
-
80
5
-
5
-
5
-
3
35
3,6
10
-
ns
ns
tb RHZ
Read Pulse High to Data Bus at High Z
3,6
-
20
-
25
-
30
-
30
ns
tb DV
Data Valid from Read Pulse High
3,6
5
5
-
5
3
45
50
65
100
tb RPW
Read Pulse Width
3
35
-
40
-
-
ns
Read Cycle Time
-
5
tb RC
-
-
ns
ns
ns
ns
tb RR
Read Recovery Time
3
10
10
15
-
20
tb S1
RiW BSet-Up Time
3
5
-
-
5
-
5
-
10
tb H1
R/WB Hold Time
3
5
-
5
5
-
10
tb DS
Data Set-Up Time
3
18
-
20
-
-
30
-
40
-
tb DH
Data Hold Time
3
0
0
-
5
-
10
-
ns
tbwc
Write Cycle Time
3
45
-
50
65
-
100
-
ns
50
-
80
-
ns
15
20
-
ns
50
80
ns
ns
tbwpw
Write Pulse Width
3
35
Write Recovery Time
3
10
-
40
tbWR
10
-
4
10
-
10
-
15
-
15
-
ns
-
20
25
-
40
-
ns
10
16
10
-
16
-
ns
8
-
5
-
10
10
tbDsBH
tfrn, l1EW, LDRER, LDREW
Set-Up and Recovery Time
REQ-ACK (B-Side 9-Bit)
tb CKC
Clock Cycle Time
5
17.5
tb CKH
Clock Pulse HIGH
5
6
tbCKL
Clock Pulse LOW
5
6
tbREQS
Request Set-Up Time
5
5
-
tbREQH
Request Hold Time
5
5
-
5
-
5
-
tbACKL
Delay From Rising Clock Edge
to ACK Switching
5
18
-
20
-
25
-
S6-169
8
ns
5
-
ns
35
-
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee= 5V ±10%, T A= O°C to + 70°C; Military: V ce=
5V ±10%, T A= -55°C to
COM'L
PARAMETER
SYMBOL
FIG.
+ 125°C)
MIL
MILITARY AND COMMERCIAL
72521x40
72521x35
MIN.
MAX. . MIN.
MAX.
72521x50
MIN.
MAX.
72521x80
MIN.
MAX.
UNIT
BYPASS MODE
ta BYA
B- > A Bypass Access
6
20
25
30
40
ns
ta BYD
B- > A Bypass Delay
6
15
17
20
30
ns
taBYH
B- > A Data Hold
6
5
5
5
10
ns
tb BYA
A- > B Bypass Access
6
20
25
30
40
ns
tb BYD
A- > B Bypass Delay
6
15
17
20
30
ns
tb BYH
A- > B Data Hold
6
5
5
5
10
ns
FLAGS TIMINGS
tREF
Ii LOW to EJ! LOW
7
35
35
45
60
ns
tWEF
W HIGH to EJ! HIGH
7
35
35
45
60
ns
tRFF
Ii HIGH to J=J: HIGH
7
35
35
45
60
ns
tWFF
WLOWto~LOW
7
35
35
45
60
ns
tRAEF
Ii Low to Almost ~ LOW
7
50
50
60
75
ns
tWAEF
W High to Almost EJ! High
7
50
50
60
75
ns
tRAFF
Ii High to Almost ~ High
7
50
50
60
75
ns
tWAFF
W Low to Almost ~ Low
7
50
50
60
75
ns
PROGRAMMABLE I/O TIMINGS
t plOA
Pia Access Time
8
25
B- > A Set-Up Time
8
5
-
25
t plOS
t ploH
B- > A Hold Time
8
5
-
5
NOTE:
10 Ii or W is internal Signal derived from USA & R/WA or L>SA & R/WBo
S6-170 .
5
-
30
-
30
-
ns
10
-
10
-
ns
10
-
10
-
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
I
I
----,~
CSA
V""--
I
~I------------------------------------~I~----------~I
___ ______________________________
~I~
~I
_________~X~---
~~:---------------------------------------:-----------~~
,~I------------------------~"r---
DSA
I
1
:r-tasl - . ,
I
!I
taHl - . . ,
READ
CSA=O; Al = O. Ao= O""'I~t--------------
1
R/WA =1
.1
taRC
I . - - taRR
----.....,1
~~
DSA
.1
I
-1I
taRPW
I
1
~
I
'---------
1
I
'--------------t---m-----..I
Y
'KXXX
ilt-----
Output: DA(17:0)
~------------._ _......~"-I.::I~K..~A
I
14- taov~
1
I-- taRLZ - ,
1
,-
-I
taA
'
1
~taRHZ-"
WRITE
~,~t--------------tawc----------~-,
,
I
,
'
"'1"--- tawR---·"1
~~I----~:------------------------~:I
____~~
'
-
DSA
.
----~I~--~'~'~::::~---------------ta-w-p-w.:-------__-_-_-__
t- taSl --,
Input: DA(17:0)
:
,
-_-_-~~r-----4---~~~:----
I
••
,
---------------------------~~~------~:------~~~--------
r-taos ~ taOH--1
Note: Refer to Address Control (Table 1) for other selection
Figure 1. Read and Write Timings (A-Side)
Al = 1. Ao = 1
\.
ITSA
Opcode DA (15:0)
Operand DA (7:0)
1
:
V
\
__
------~I~twPw----J!Ir---~:-------------1
~
~~------------------~~~---+.---tWRCOM ----------~-------1
~.!
------I~
1
:
:
I+" ta os ~ ta OH --1
Figure 2. Carry Out Command Timing (A-Side Only)
S6-171
MI LlTARY AN D COMMERCIAL TEM PERATU RE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
Case 1: When access controls are R/WBand DS B
WRITE
I.
R/WB
.1
tbwc
1
1
1
I-
1
1
~'
OSB
I
~.
1
tbwpw
~
°B(8:0)
~
I
-J
i
I
1
1
1
1
.(
tb H1
r-- tbSl ~
-I
1
1
1
1
1
tbwR
1
!
~tbDs~tbDH~
Case 2: When access controls R/W B and DSB are programmed as RBand WB
~I·~.............................................--tbwc--..................................................~·~I
RB=l
____________
1
1
1
r
1 - t b W R - . iI
~I
I
~~'~.::::::::::::~-t-b-W-PW---------------·~f
:
°B(8:0)
1
~~------
1
1
-------------------------------------------~~--------i~------~'~,---------r-- tbDs
·1·
tbDH----,
Case 1: When access controls are R/WBand lJS B
READ
R/WB =1
DSB
OB(8:0)
~1-~.......................................................--tbRC--............................................................~·1
1
1
I.
1
tbRR .....---I.~'
~r4-------------- tbRPW .....- - - - - - - .vr------------~~
l~·--------------------------------~i
1
I :\~-------
:. . bcx>a
' - - tbRLZ
----J
1
I.
tbA
:
I
I .
1
.,
-
1
~~-----~1
tbDV--+j
1
r---tbRHZ~
Case 2: When access controls R/WB and OS Bare programmed as liBand WB
WB =1
~1.~.......................................................--tbRC--............................................................~·,
1
,
1
------..,~.,
I.
tbRR
:
1
.,
tbRPW--.....- -.....- - -...
·V~-------~~
,~·--------------------------------~i
~~-------
°B(8:0)
:
I.1
I.
tbRLZ
bcx>a
----J
tbA
I
~~------
I'---------...L.I.-----~
tb DV--+j
,
.,
1
1
I
r---tbRHZ~
Figure 3. Read and Write Timings (B-Side)
S6-172
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
Case 1: Access controls are R/WBand 158B
~I
--.J
I
-----.I-II--_ _---:-1--~.:
~orREW
14-:.
tOSBH
tOSBH
LDRER or LDREW
Case 2: Access controls RIWB and
WBor R"B
Am or"REW
-1
:.
I
I
I
·1I
I
I
LDRER or LDREW
15SBpins are programmed as RBand WB
I·
I
I
I
-I
I
I
I
I
I
I
tOSBH
~I
I
tOSBH
t
Figure 4. Reread, Rewrite, Load Reread, Load Rewrite Timings (B-Side)
I.
2 to 5 cycles-----..,j_1
I
/--t
J4- tcKH
I
ClK
-----If
I
CKC - . ,
---Ir-
I
tCKL - ,
t
I
I
L.-I 1 cycle-e_ _.~114_- 1 to 2 CYCles-J1
I
I
I
I
I
I
I
I
I
Lr--1
L~
f
REO
I
I
I
I
I
------------------------~--~~~I----~I________~--~~
r
~:
I
I
R/WB
I
--------------------------------~I------~:----~:------,~I----~----~~
r- ~
rI-tACKL
tACKL- - ,
I
tACKL- ,
I
I
r
RB
i
~
WB
i
\1J--
~
I
~
lte: Depends on the Intel or Motorola mode bit, BiFIFO either generates J:>S"B and R/WB or R"B and
tACKL--1
:r-
"
tACKL--t
WB in th~}Request and Acknowledge mode
Figure 5. Request and Acknowledge Timings (B-Slde Only)
S6-173
I
l.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IOT72521 CMOS BIDIRECTIONAL FIRST·IN/FIRST·OUT FIFO
BYPASS
A-B
~A
Al=O; Ao = 1
R/WA =1
~A
DB (8:0)
,
rP"lf"'"x'K""xx"'W""'7'lI'----+l_ _ ~i......--.i----'X
:
,
I~,
I taBYO 1
1
1
~I
" - - taRLZ---!
,-
I
I1_ _~I~_ _II _ _.....;_ _ _ _I
I
ta BYA
~ taOV---\
XXX )1--I
I
1
( 4 - - ta RHZ - - - 1
A-B
~A=O
Al=0;Ao=1
tbBYH -----r,.ll
!.
~A
------,'~'---------------__,
~:________
~V
,
I
-------~l---------D-a-ta-A------,----X~-D-a-ta-B----~:-'- - - - - - - - - - - - - - - - - - - ,
'I~---I------~I------~I----~--TI------I
. DB(8:0)
:
I.--
,
,-
I
~
[:-XXX~--XII~D-I.+-A-~
tbRLZ---I
I
tbBYA
I
I
III
I1
III
tbBYO I
Figure 6. Bypass Timings
S6-174
¥xXX )1----
, I
Data B
. I+- tbov--t
1
t - - - tbRHZ
.
.
1
I
~I
- - - - - - - - - - - - - - - - - - - _ . _ - - - - - - - - - - _.. _ . _ - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
FIFO B -
A: Empty and Full Flags
R/WA =1
II
DSA
),
l
Read FIFO
"
Write FIFO
R/WB
Write FIFO
""
ITSB
I
I
I
I
~
rF
r:,
I
I
I
E"F
I
I
H
I tWFF I
Ii
I
r---J
tREF
I
I
I
I
tWEF
I
I..--i
: r
I tRFF
I
Note: t RAEF• tWAEF • t RAFF • tWAFF are the same to the above timings.
FIFO B - A: Empty and Full Flags
R/WB =1
l
,,
If
ReadFIFO
1-------'
Write FIFO
[)SA
"
I
I
I
;
Write FIFO
,
II
I
I
I
IT
I
I
rF
I
I
I
k--...I
I
I
i
~
tREF
I
I
;
~
tWEF
,
I tWFF I
It
l I
I
I
~
I tRFF I
:~
Note: t RAEF• tWAEF • t RAFF • tWAFF are the same to the above timings.
Figure 7. Flag Timings
S6-175
- - - - -_ .... _._...-
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
1DT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
PROGRAMMABLE INPUT/OUTPUT (PIO)
A -
B: Write Into Register 6
\~----------------------~:--~I
\~
ImA
__________________
I
~1-------------
Data A
Input DA (i)
Output Pia (i)
I
I
i
,
Data A
Note: (i) is any number from 0 to 5
A -
B:
Read from Register 6
I
'[)SA
----------------~~~I._______
~+:---------------J/
tP_IO_A________
I
Output D A (i)
Input PIO (i)
I
----------':----c(XXXI"'--___
I
I
I
I
I
D_a_ta_A_ _ _- - ' I - - - - -
Data A
I
I
....
1·1---t~....I·~-- tploH
I
~
tplOS
Note: (i) is any number from 0 to 5
Figure 8. Programmable I/O Timings
S6-176
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
• Pass-Through: On-chip transceiver to pass through the FIFOs
for direct and synchronous communication between two data
ports.
These features can be selected by programming a set of six internal Configuration Registers or by "executing a command" from
port A. There are six possible modes of operation from port A, depending on CSA , A 1 and AO pins:
1. Port A disabled ( CSA =0)
2. FIFO access.
3. Direct access to port B, pass through FIFOs.
4. Program Configuration Registers.
5. Read Status Registers.
6. Carry out a command.
FUNCTIONAL DESCRIPTION
FIFOs are used to link processors and peripherals together
asynchronously to transfer data. Often the data on each side must
be passed in both directions and requires two FIFOs arranged
side-by-side. The BiFIFO is an integrated solution to this class of
applications offering asynchronous bidirectional data buffering.
The BiFIFO contains two 1K by 18 FIFOs connected side by side to
two data ports: A and B.
The BiFIFO also contains several innovative, programmable
features:
• DMA Style Handshake: Option available on port B side to
control read and write activities when connected to peripherals
with REQUEST and ACKNOWLEDGE kind of handshake.
• Block Transmit: Capability to Reread and Rewrite from port B.
• Flags: Four empty, full and programmable flags (empty+
offset, full-offset) per FIFO, can be multiplexed into four flag
pins.
• Programmable I/O: Six general purpose programmable pins
each can be an output or input or input ports.
DMA Style Handshake Mechanism
There are two operational modes for the 8-bit (port B) interface.
The modes are tailored to facilitate connection with intelligent devices such as CPUs which can generate read and write strobes, or
less intelligent devices such as peripherals which require that read
and write strobes be generated for them (see Figure 9).
RiVlA
CPU INTERFACE MODE
DSA
CPU
RiVl B
BiFIFO
16
CPU
16
,
"
RiVlA
DMA MODE
(Peripheral Interface)
DSs
RiVl B
DSB
DSA
CPU
BiFIFO
REO
PERIPHERAL
ACJ<
16/33-
16/
Figure 9. Interface Modes
The BiFIFO responds to an active signal on the REQ input by
strobing the ACK and DSB lines and asserting the RiWB output. All
timing is relative to a shift register clock generated by ClK or ClK
divided by two. When in the DMA (peripheral) mode and the pass'through buffers are used for a synchronous transfer, the read/write
strobe from the A port are passed through to the B port.
Reset
I
The IDT72521 can be reset through hardware pin, power up or
through bit on register. During reset, both internal Read and Write
pointers are set to the first location.
Programmable I/O
There are six programmable I/O pins: PIO (5:0). When programmed as inputs, PIO (5:0) can be read from port A's DA (5:0).
When PIO (5:0) are outputs, any data written into DA (5:0) will show
up on PIO (5:0). The data direction is individually selectable by programming the Register 7 (see Figure 10).
I
S6-177
----------
._ .....
_---_.
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST·OUT FIFO
WRITE DATA (REG. 6)
PIO 0-5
Q
DA 0-5 - - - - - - - - - -.....- - - - - -.. D
-------+--:-------D
RESET
Q I---~
1 - - - - - - - - 1... D
WRITE DIRECTION MASK
(REG. 7)
~
DiRECTioN MAsK
(REG. 7)
1---4 Y
D
LE
READ DATA
LATCH CLOSED WHEN
LE IS LOW AND READING
(REG. 6)
Figure 10. Programmable Input/Output
Pass-Through (Synchronous Access)
of BiFIFO and peripheral.
The BiFIFO includes a unique data path that bypasses the
FIFOs such that a processor can talk synchronously with the peripheral to initialize it and then communicate asynchronously via
the FIFOs. The parity generate and check circuitry (if selected) also
comes into play during the synchronous transfer of data via trie
pass-throuilb buffers. ~hen in the peripheral (DMA) pass-through
mode, the DSB and R/WB pins are outputs and reflect the action of
the DSA and RtWA inputs. REO should be low during initialization
REGISTER DESCRIPTION
CSA
A1
Ao
Address Control
The address lines indicate the resource to be accessed. There
are six items that can be accessed: the FIFO B- > A, FIFO A- > B,
B-bit data bus, the flag configuration registers, status and command (see Table 1).
WRITE
READ
0
0
0
FIFO B->A
FIFO A->B
0
0
1
18-bit bus direct
18-bit bus direct
0
1
0
Configuration Register
Configuration Register
0
1
1
Status
Command
1
X
X
X
X
Note: Port Buses DSB and RIWB in the same way that Port A generates
internal strobes.
Table 1. Address Control for Port A.
Command Register
The command feature allows the userto direct the BiFIFO to do
something in real-time rather than setting up configuration
registers in an idle condition. The command port format and a list
of commands is shown in Table 2. The commands are accessed
through the command port (Al , Ao = 11).
S6-178
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
15
8 7
12 11
I XXXX I
Opcode
I
Opcode
3 2
XXXXX
I
0
l
Operand )
Function
0
Reset BiFIFO functions (see operands)
1
Select Configuration Register (see Table 3)
2
Load Read pOint with Reread pointer value
3
Load Write pOinter with Rewrite pointer value
4
Load Reread pOinter with Read pointer value
5
Load Rewrite pointer with Write pointer value
6
Set DMA transfer direction (see operand)
7
Reserved
8
Increment read pointer on B side
9
Increment write pOinter on B side
A
Reserved
B
Reserved
I~
~
'"
OperandJl)
Function
No operation
000
f---001
f---010
f---011
f---100
f---101
f---110
f---111
-------------------Reset FIFO 8->A (Read, Write, and Rewrite pointers)
-------------------Reset FIFO A- > 8 (Read, Write, and Reread pOinters)
-------------------Reset B->A and A->B
-------------------Reset REO circuitry
-------------------No operation
-------------------No operation
-------------------Reset all (2)
XXD
---XX1
t
Wnte F'FO B->A
----------------Read FIFO A- > B
NOTES:
1. If operands are not shown for opcode, then they are in don't care
condition.
2. Reset both FiFOs, REO, Configuration Registers 0,1,2,3,5,7. Reset
Configuration Register 4 to default. DMA direction B-+A. Clear Parity
Error flags.
Table 2. Command Function and Operand
Configuration Registers
command to point to a particular location, then reading or writing
the content via address 2 (Al, Ao =10). On reset, all registers except Register 4 (Tables 3, 4) default to Zero.
Several configuration registers control the BiFIFO operation
(Table 3). The configuration registers are accessed by executing a
Operands
000
Selection
15
10
9
0
Reg 0:
A- > B Empty
15
001
Reg 1:
010
Reg 2:
011
Reg 3:
100
Reg 4:
101
Reg 5:
10
10
9
0
9
0
B- > A Empty
15
10
0
12
8
11
Flag D
4
7
Flag C
Flag B
3
0
Flag A
0
General Control
15
0
Reg 6:
I/O Output Control
15
0
Reg 7:
0100
Offset
9
15
NOTE: 0110
+
B- > A Full - Offset
15
111
Offset
A- > B Full - Offset
15
110
+
I/O Direction Control
0010 0000 is default for Register A. All others default to O.
Table 3, Configuration Registers
S6-179
MILITARVANDCOMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
Configuration Registers 0 through 3:
Configuration Register 4:
SEL
0000
These program the offset for the almost empty and almost full flags. The
values in these registers are unsigned positive numbers.
This is used to select internal flags for the external flag pins A through D.
The register is divided into four fields of four bits each. The four bit fields not
. only select which flag to output but also the polarity at the output. This creates an easier interface to processors and peripherals (see Table 4).
SELECTED FLAG
SEL
Empty A->8
+
0001
Empty
0010
Full A->8
0011
0100
0101
Empty
0110
0111
1000
+
1001
Empty
1010
Full A->8
Full - Offset A- > 8
1011
Full - Offset A- > 8
Empty 8->A
1100
Empty 8->A
1101
Empty
Full 8->A
1110
Full 8->A
Full-Offset 8- > A
1111
Full-Offset 8- > A
+
Offset A- > 8
SELECTED FLAG
Empty A->8
Offset 8- > A
Table 4. Flag Polarity and Selection Codes
S6-180
+
Offset A- > 8
Offset 8- > A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
Configuration Register 5:
This contains fields to control various functions (see Table 5).
FUNCTION
BIT
Provides the strobes as RB & WB (Intel Mode)
0
-----------------
:--
0
Select: DS B & RNiB or RB & WB
1
Unused
2
Enable Reread
:--
3
Enable Rewrite
-1
4
REO polarity
I- - - - - - - -REO active lOW
1
5
ACK polarity
0
f-1
1------------------ACK active HIGH
6-7
REa/ACK Timing
00
f-01
1------------------3 clock cycle between REO A. & ACK T
10
f-11
1------------------5 clock cycle between REO A. & ACK T
DS B & RNiB (Motorola Mode)
1
Disable Reread
0
------------------Enable Reread
1
0
Disable Rewrite
------------------Enable Rewrite
REO active HIGH
0
-
-
-
-
-
-
-
-
-.--
ACK active lOW
2 clock cycle between REO
A. & ACK T
4 clock cycle between REO
A. & ACK T
8
Read & Write Strobe
0
Read and write strobe: 1 cycle lOW
f-- I----------~-------Read and write strobe: 2 cycle lOW
1
9
Clock Frequency (Internal)
0
f-1
------------------ClK signal divided by two
0
10
Interface Mode Select
,..--
CPU interface mode
-------~----------DMA (peripheral interface) mode
ClK signal generates the REa/ACK sequence
1
Note: All default to O.
11-15
Unused
Table 5. Register 5 Format
Configuration Register 6:
The configuration register 6 is used to store data to be output on the I/O
pins. Data to be output is written into the bit position: 0 to 5. The bit positions
6 through 15 are unused. This register can only be written.
15
6
5
BIT 6-15 ARE UNUSED
Table 6. I/O Output Control
S6-181
4
3
2
o
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
Configuration Register 7:
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
This configuration register7 is the mask register which is used to control the
direction of the I/O pins. This register can be read or written from the A side.
Each bits ofthe register 6 controls the direction of the 110 pin respectively. A
logic zero selects the corresponding 110 pin as an Input. A logic one selects
the 110 pin as an output. The default is logic zero.
15
5
6
4
3
2
o
BIT 6-15 ARE UNUSED
Table 7. 1/0 Direction Control
Status Register
Bit othrough 2 are unused. Bit 3 is the DMA direction selected via
the command register: 0 for A- > Band 1 for B- > A. The bit 4
through 7 are flag status which are: Empty A- > B, Empty + Offset
Bit
A- > B, Full-Offset B- > A and Full B- > A. The bits 8 through 11 are
unused. The status bits for the Data A side of the FI FOs are found in
bits 12 to 15: Full-Offset A->B, Full A->B, Empty B->A, and
Empty + Offset B-. > A.
Status Register
0
Reserved
1
Reserved
2
Reserved
3
DMA Direction
4
A->B Empty
5
A- > B Empty
6
B->A Full
7
B- > A Full - Offset
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
A->B Full
+ Offset
13
A- > B Full - Offset
14
B->A Empty
15
B- > A Empty
+ Offset
Table 8. Status Register Format·
S6-182
IDT72521 CMOS BIDIRECTIONAL FIRST-IN/FIRST-OUT FIFO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXXX
Device Type
A
Power
999
Speed
A
Package
A
Process!
Temperature
Ran(L.._e_ _ _ _ _ _-I1 :LANK
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliance to MIL-STD-883, Class B
-1 JG
1...-_ _ _ _ _ _ _ _ _ _
L
35
'-----------------i
40
Pin Grid Array
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Commercial Only }
Military Only
50
80
I...------------------~ L
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 72521
Low Power
1Kx 18-bit BiFIFO
S6-183
Access Time (tA)
Speed in Nanoseconds
----.-.. - ... ----..
..
------------~
Digital Signal Processing (DSP)
- - - . - - . _ - ...
_-_ __ __
...
.....
...............-.....
.
DIGITAL SIGNAL PROCESSING
Digital Signal Processing (DSP) building block components
ease the high bandwidth digital processing of analog signals using
complex algorithms. Integrated Device Technology's advances in
VLSI design and CMOS technology have accelerated development of high-speed DSP building block components which
address similar advances in DSP algorithms. All IDT DSP
components are designed with a three-bus architecture, ideal for
high bus bandwidth systems.
- - - _..._._----._---------_.
Fixed-point multipliers, multiplier-accumulators, mUlti-level
pipeline register files and DSP arithmetic-logic units offer
high-performance functions for 12-bit and 16-bit data. IDT offers
the fastest fixed-point building blocks in the industry for the most
demanding DSP system requirements.
IDT's goal is to provide the highest level of integration and
highest performance components for the most demanding DSP
systems.
TABLE OF CONTENTS
CONTENTS
Digital Signal Processing
lOT 7209
lOT 7210
lOT 7212
lOT 7213
lOT 7216
IDT 7217
lOT 7243
IDT7317
IDT7320
IDT7321
IDT7381
IDT7383
IDT7384
PAGE
12 x 12 Parallel Multiplier-Accumulator. . . . . . . . . . . . . .. . . . . . . . . . . . . • . . . . . . .. . . . . .... 7-1
16 x 16 Parallel Multiplier-Accumulator ............................................ 7-9
12 x 12 Parallel Multiplier ............................... ;. . ... . . . . . . . . . .. . .. .. ... 7-20
12 x 12 Parallel Multiplier (Single Clock) ................................ . . . . . . . . . .. 7-20
16 x 16 Parallel Multiplier ................................................... , . . .. 7-55
16 x 16 Parallel Multiplier (32-Blt Output) .......................................... 7-55
16 x 16 Parallel Multiplier-Accumulator (19-Blt Output) . . . . . . .. . . . . . . . . . . .. . . . . . . . .. .. 7-9
16 x 16 Parallel Multiplier (32-8it Output) (S14-12) .................................... S7-1
16-8it CMOS Multilevel Pipeline Registers (S14-12) .....................•....•.......• S7-9
16-8it CMOS Multilevel Pipeline Registers (S14-12) ....•.............................• S7-9
16-8it CMOS Cascadable ALU (S14-12) ............................................ S7-15
16-8it CMOS Cascadable ALU (S14-12) ............................................ S7-15
16-81t CMOS Cascadable ALU .................................................•.• S7-23
Intesrated Device lechnoIogy. Inc.
16 x 16-BIT PARALLEL
CMOS MULTIPLIER
WITH 32-BIT OUTPUT
PRELIMINARY
lOT 7317
FEATURES
DESCRIPTION
• 16 x 16-bit parallel multiplier with 32-bit output available
immediately
The IDT7317 is high-speed, low-power 16 x 16-bit multiplierthat
has double the throughput of comparable devices by virtue of a full
32-bit output product bus. The Most Significant Product (MSP) and
Least Significant Product (LSP) can be independently enabled on
an external 16-bit bus or simultaneously enabled on an external
32-bit bus. IDT's high-performance CEMOS ™ technology produces very fast (20ns) clocked multiply times.
The output structure includes a programmable one-bit shifterfor
improved dynamic range algorithms using block floating point.
This multiplier offers flexible configurations for clocked and
flowed-through multiplications.
The IDT7317 is ideal for digital signal processing (DSP) applications requiring single-cycle 32-bit integer products. Some typical
applications for this multiplier are 1-D and 2-D fast Fourier transforms (FFT), matrix multiplications, FIR and IIR filtering.
Military versions of the IDT7317 are manufactured in
compliance· with the latest revision of MIL-STD-883, Class B for
high-reliability systems.
• 20ns clocked multiply time
• Low power consumption: 400mW Max.
• One clock and three register enables
• Unsigned, Two's Complement or Mixed-Mode operations
• Flexible output scaling shifter
• Pipeline or Flow-through modes
• TTL-compatible inpuVoutput
• Three-state outputs
• Produced with advanced submicron CEMOS ™
technology
• Available in 84-pin PLCC and 84-lead Pin Grid Array (PGA)
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
FTX
I+-------I-----FTY
EN? --------------------~
FTP
.....------------~--- SHO-2
'----~r-----'
GND
Vee
OE"M
P16-31
PO- 15
OE[
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
OSe-2026/-1
1989 Integrated Device Technology, Inc.
S7-1
IDT731716 x 16-BIT PARALLEL
CMOS MULTIPLIER WITH 32-BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11
10
.""
9
8
Index Mark
7
Consult
Factory
6
5
4
3
2
A
C
B
D
E
F
G
K
H
L
PGATOPVIEW
~a.ffi ~
0
o
~ a.0a:-a."'a."'a....a.IOa.CD({'"a.coa.(l)a¥a:=a.Ta!~ Ii:
wwwwwwwuuwuwwwuwuuuuu
nnnnroooM~ooM~~~~OO~M~~~M
Vee
:J 75
:J 76
:177
Xo
Xl
X2
X3
X4
X5
Xe
X7
X8
X9
XlO
XII
X 12
X 13
X 14
X 15
XM
:178
:179
:1 80
:J 81
:182
:J 83
:1 84
FTX
£NX
ClK
:::J
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
Pin 1 Designator
1
/
J84-1
[
I:
[
I:
[
[
[
I:
I:
[
[
[
[
:12
:13
:J 4
I:
:15
I:
:16
[
:17
[
:J 8
36[
:J 9
35 I:
:1 10
34 [
:J 11
33 [
12 13 14 15 16 17 18 1920 21 2223242526272829 30 31 32
~n~~~~~nnnnnnnnnnnnnn
o
Z
~
t >'0>- >'
10
lO:'ffi g
~ ~"'>-'">- >'~'>-co>'(l)r>-'"Y"r>-~r
0 ~ '" '" ...
PLCC TOP VIEW
S7-2
~
SH2
SH I
SHo
P'6
P,7
P'8
P'9
P20
~1
22
R
~
~5
~6
ij~
~30
P:Jl
om
Vee
- - - - - - - - - - - - _....._._----_ .....
./
IDT7317 16 x 16-BIT PARALLEL CMOS
MULTIPLIER WITH 32-BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
I/O
Xo - X 15
I
Sixteen multiplicand data inputs.
XM
I
Mode control for X data Input port. A LOW designates unsigned data Input and a HIGH designates two'S complement
data input.
Yo - Y,5
I
Sixteen multiplier data inputs.
YM
I
Mode control for Y data input port. A LOW designates unsigned data input and a HIGH designates twO's complement
data input.
elK
00
Em
I
The rising edge of the clock loads all registers.
I
Register enable for the X data input port along with the XM pin.
I
Register enable for the Y data input port along with the YM pin.
ENP
I
Register enable for the P output product.
FTX
I
When this control is HIGH. the X register is transparent; X input data and XM are not clocked.
FlY
I
When this control is HIGH. the Y register is transparent; Y input data andYM are not clocked.
FTP
I
When this control is HIGH. the P register is transparent; P output data is not clocked.
SHo - SH z
I
Controls output product shifting. Shifting is controlled as follows:
SH 2 SH 1 SHo
~
I
ACTION
0
X
X
no shift.
1
0
0
arithmetic shift left (up) by 1 position with 0 fill.
1
0
1
logical shift left (up) by 1 position with 0 fill.
1
1
0
arithmetic shift right (down) by 1 position with sign extension.
1
1
1
logical shift right (down) by 1 position with 0 fill.
Three-state enable for most significant product (P1e - P31 ).
Three-state enable for least significant product (Po- PI5 ).
DEL
I
Po - ~5
0
Sixteen least significant product outputs.
PIe - P31
0
Sixteen most significant product outputs.
Vce
Two power pins at
GND
Four ground pins.
+ 5V potential nominal.
87-3
---------_ .. _----_.
IOT731716 x 16-BIT PARALLEL
CMOS MULTIPLIER WITH 32-BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
RATING
COMMERCIAL
MILITARY
-0.5 to +7.0
-0.5 to +7.0
Terminal Voltage
with Respect to
GND
UNIT
Operating
Temperature
Oto +70
TalAs
Temperature
Under. Bias
-55 to +125
-65 to +135
Tsm
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
50
50
mA
TA
-55 to +125
MIN.
TYP.
MAX.
UNIT
VCCM
Military Supply Voltage
4.5
5.0
5.5
V
Vcc
Commercial Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.0
-
-
V
Input Low Voltage
-
-
0.8
V
PARAMETER
SYMBOL
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating con.
ditions for extended periods may affect reliability.
CAPACITANCE
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYP.
UNIT
CIN
Input Capacitance
VIN = OV
10
pF
COUT
Output Capacitance
VOUT= OV
12
pF
NOTE:
1. This parameter is sampled at initial characterization and is not
100% tested.
.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MILITARY
TYP!1) MAX. MIN.
TYP!1) MAX.
MIN.
UNIT
0.1
5
-
0.1
10
Hi Z, Vcc = Max., VOUT = 0 to Vcc
-
0.1
5
-
0.1
10
/J. A
Operating Power Supply Current
Outputs Open; f = 20MHz
-
30
60
30
80
mA
ICC01
Quiescent Power Supply Current
VIN ~ VIH ' VIN
35
15
45
mA
Quiescent Power Supply Current
VIN ~ Vcc -0.2V, VIN ~ 0.2V
-
15
ICC02
Icc If (2.3)
2
10
2
15
mA
4
-
6
mAIMHz
VOH
Output High Voltage
Vcc = Min., IOH = -2.0mA
2.4
-
-
-
2.4
-
-
V
VOL
Output Low Voltage
Vcc = Min .. IOL = 4mA
-
-
0.4
-
-
0.4
V
Ilu l
Input Leakage Current
Vcc = Max., VOUT = 0 to Vcc
IlLOI
Output Leakage Current
ICC(2)
~
VIL
Increase in Power Supply Current MHz Vcc = Max., f > 20M Hz
/J. A
NOTES:
1. Typical implies Vcc = 5V and TA = + 25°C.
2. Icc is measured at 20MHz and VIN = 0 to 3'1. For frequencies greater than 20M Hz, the following equation are used; for the commercial range,
Icc = 60 + 4(f-20)mA; for the military rang"), Icc = 80 + 6(f-20)mA; f is the operating frequency in MHz.
3. These limits are guaranteed but not tested ..
S7-4
IDT7317 16 x 16-BIT PARALLEL CMOS
MULTIPLIER WITH 32-BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
SYMBOL
7317L20
MAX.
MIN.
35
PARAMETER
IYcc = 5V ± 10%. TA = O°C to + 70°C)
7317L35
MAX.
MIN.
55
-
7317L55
MIN.
MAX.
75
7317L75
MIN.
MAX.
100
-
t MUC
Unlocked Multiply Time(2)
t MC
Clocked Multiply Time(2)
-
20
-
35
-
55
-
75
tso
X.Y Input Data Set-up Time(2)
8
-
10
-
13
18
tHo
X.V Input Data Hold Time(2)
2
-
2
-
2
-
tpWH
Clock Pulse Width High(2)
9
-
10
-
15
tpWL
Clock Pulse Width LOW(2)
9
-
10
-
15
-
tpop
Clock Output to P (2)
18
-
25
-
30
tENA
3-State Enable Time(l)
18
-
25
t OIS
3-State Disable Time (1)
-
15
-
22
-
25
tSE
Clock Enable Set-up Time(2)
8
-
8
Clock Enable Hold Time(2)
2
-
8
tHE
2
-
2
30
2
8
2
20
20
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
35
ns
30
ns
NOTE:
1. Transition is measured + 500mV from steady-state voltage with loading specified in Figure 1. Vx = 0 V and 2.6 V.
2. IOL = 3.2 mA and 10H = -0.8 mA during AC tests.
AC ELECTRICAL CHARACTERISTICS- MILITARY
SYMBOL
IYcc = 5V ± 10%. T A= -55°C to + 125°C)
7317L25
MAX.
MIN.
38
PARAMETER
7317L40
MIN.
MAX.
60
7317L65
MIN.
MAX.
85
7317L90
MIN.
MAX.
125
-
t MUC
Unlocked Multiply Time (2)
t MC
Clocked Multiply Time (2)
-
25
-
40
-
65
-
90
-
20
25
15
-
15
3
-
3
15
-
25
-
30
-
tso
X.V Input Data Set-up Time (2)
12
X.V Input Data Hold Time (2)
2
-
15
tHO
tSE
Clock Enable Set-up Time (2)
12
-
15
tHE
Clock Enable Hold Time(2)
2
3
tPWH
Clock Pulse Width High(2)
10
-
12
3
3
3
tpWL
Clock Pulse Width Low(2)
10
-
12
-
15
tpop
Clock Output to P (2)
-
20
-
25
tENA
3-State Enable Time(1)
-
20
25
30
t OIS
3-State Disable Time (1)
-
18
-
-
22
-
30
25
UNIT
DATA
INPUT
-
4O PF
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
-'0
~tstt"~
.
y
Figure 1. AC Output Test Load
for tOls and tENA)
STATE
THREE--J=
CONTROL
CLOCK _ _ _ _ _ _ _ _ . , _ _ _ _ _ _ _ _ 3V
INPUT
1.5V
_ _ _ _ _ _ _..J - - - - - - - - OV
OUTPUT
THREESTATE
t~s
j
VOH -0.5
ns
ns
= 2.0V except
Ft~,
IGH-I MPEDANCE
HIGH-IMPEDANCE
Figure 3. Three-State Control Timing Diagram
S7-5
ns
35
VOL +0.5
Figure 2. Set-Up And Hold Time
ns
ns
40
V,
CI x
ns
ns
TO
500n
OUTPUT ~
PIN
~ __ l
1
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
ns
ns
40
NOTE:
1. Transition is measured + 500mV from steady-state voltage with loading specified in Figure 1. Vx = 0 V and 2.6 V.
2. 10L = 3.2 mA and 10H = -0.8 mA during AC tests.
AC TEST CONDITIONS
ns
ns
f1I
IDT731716 x 16·BIT PARAllEL
CMOS MULTIPLIER WITH 32·BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
l-tpWH-1
ClK
______~I
~I
______~
INPUTX. Y
OUTPUT P
Figure 4.IDT7317 Timing Diagram
ClK
1··---tMc-1
------~I
------______
Of-------~D .!l~~V~ ~~A!!D~~,
DATA
TO X.V
REGISTERS
DATA OUTPUT
TO MSP. lSP
REGISTERS
Of--------D ~~C!!~ ~S!:~~L~
DATA
TO X.V
REGISTERS
DATA OUTPUT
TO MSP. LSP
REGISTERS
Figure 5. Simplified Timing Diagram-Typical Application
S7-6
IDT7317 16 x 16-81T PARALLEL CMOS
MULTIPLIER WITH 32·81T OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
SIGNAL
~+-~~~~~~~~~~~~~~~~~~+-~~~+-~~r-;-~--r-~-+~r-~-;--+--r-+~
DIGIT VALUE
lSP
MSP
Figure 6. Fractional Two's Complement Notation
BINARY POINT
SIGNAL
~~~~~~~~~~~~~~~~~~~~~~~~+-~~~~~~~~~~~~~~+-~~~
DIGIT VALUE
MSP
lSP
Figure 7. Fractional Unsigned Magnitude Notation
BINARY POINT
SIGNAL
DIGIT VALUE
MSP
Figure 8. Fractional Mixed Mode Notation
BINARY POINT
SIGNAL
2
0
DIGIT VALUE
SIGNAL
2
0
Po
DIGIT VALUE
SIGNAL
DIGIT VALUE
lSP
MSP
Figure 9. Integer Two's Complement Notation
S7-7
IDT731716 x 16·BIT PARALLEL
CMOS MULTIPLIER WITH 32·BIT OUTPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
SIGNAL
DIGIT VALUE
~-'----'-_"'---L---L_"'---L----'_"'--....L----'_-'--L._~-'--~ DIGIT VALUE
MSP
LSP
Figure 10. Integer Unsigned Magnitude Notation
BINARY POINT
MSP
LSP
Figure 11. Integer Mixed Mode Notation
ORDERING INFORMATION
lOT
XXX)(
XX
x
Device Type
Power
Process/
Temperature
Range
11.-..-----11
'--------------1
:LANK
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL·STD·883. Class B
J
Plastic Leaded Chip Carrier
Pin Grid Array
G
'-----------------1
20 }
~~
Commercial (tMc>
L
7317
S7-8
~~
65
90
75
Low Power
16 x 16 Multiplier
}
Military (tMC>
- - - - - - - - - ------_.-
Integrated Device1echnology.1nc.
PRELIMINARY
lOT 7320
lOT 7321
16-BIT CMOS
MULTILEVEL
PIPELINE REGISTERS
FEATURES:
DESCRIPTION
• IDT7320: Eight 16-bit high-speed pipeline registers
The IDT7320 and IDT7321 are multilevel pipeline registers. With
IDT's high-performance CEMOS technology, the IDT7320 and
IDT7321 have access times of 12ns.
The IDT7320 contains eight 16-bit registers which can be
configured as one 8-level, two 4-level, four 2-level or eight 1-level
pipeline registers.
The IDT7321 contains seven 16-bit registers and a direct
feed-through path. The seven registers can be configured as one
7-level, a 4-level plus a 3-level, three 2-level or seven 1-level
pipeline registers.
An eight-to-one output multiplexer allows data to be read from
anyone of the registers or from the feed-through path on the
IDT7321. Three input control pins (SELo - SEL2) select which of the
multiplexer inputs are directed to the output (Yo - YI5).
These pipeline registers are ideal for high throughput, vectororiented operations such as those in digital signal processing
(DSP). The IDT7320 and IDT7321 can also be used as quick
access scratch pad registers for general purpose computing.
The two pipeline registers are packaged in 48-pin plastic and
ceramic DIPs for through-hole designs as well as 52-pin PLCC and
LCC for surface mount designs. Military grade product is manufactured in compliance with. the latest revision of MIL-STD-883,
Class B.
• IDT7321: Seven 16-bit high-speed pipeline registers plus a
direct feed-through path
o 12ns to 20ns access time
• Programmable multilevel register configurations
• Powerful instruction set: transfer, hold, load directly
• Functionally replaces four Am29520s
• Applications as temporary address storage or programmable
pipeline registers for DSP products
• Coefficient storage for FIR filters
Three-state outputs
II
• TTL-compatible
o Produced with advanced submicron CEMOS ™
high-performance technology
• Available in 48-pin plastic and ceramic DIP and 52-pin
surface mount PLCC and LCC
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
Do -
~5
Do -
16
~5
16
SEloSEl2
SEloSEl2
at --------------~
at --------------~
I~
ClK ----.:;;..._ _......
GND'
Vcc
I~
ClK ---;;""_ _- '
Yo -115
IDT7321
1017320
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-2032/-
1989 Integrated Device Technology, Inc.
S7-9
IDT7320/1DT7321 16-BIT CMOS
MULTILEVEL PIPELINE REGISTERS
MI LlTARY AN D COM M ERCIAL TEM PERATURE RANGES
PIN CONFIGURATIONS
INDEX
UUUULU'IUULJ
7
6 5 4
3 2
U
D3 :18
D4
D5
D6
D7
GND
Vee
D8
D9
D l0
Dll
D12
NC
52 51 50
1
:19
:110
:1 11
:112
:113
:J 14
:115
:116
:117
:],8
:119
JS2-1
&
LS2-1
:1 20
21 22 23 24 25 26 27 28 29 30 31 32 33
nnnnnnnnnnnnn
PLCC/LCC
TOP VIEW
DIP
TOP VIEW
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
I/O
Sixteen-bit data input port.
Do - D 15
I
Yo - Y15
0
10 -13
I
Four control pinS to select the register operation performed.
SElo - SEl2
I
Three control pins to select the register appearing at the output.
ClK
I
Clock input.
CEN
I
Clock enable control pin. When this pin is low. the instruction 10 - 13 is performed on the registers.
When high. no register operation occurs.
<:>e
I
Output enable control pin. When this pin is high. the output port F is in a high impedance state. When
low. the output port F is active.
Sixteen-bit data output port.
Vee
Power supply pin. SV.
GND
Ground pins. OV.
IDT7320 OUTPUT SELECTION
IDT7321 OUTPUT SELECTION
SEL 2
SEL 1
SELo
YOUTPUT
SEL 2
SEL 1
SELo
0
0
0
A -+ Yo - Y15
0
0
0
YOUTPUT
0
0
1
B -+ Yo - Y15
0
0
1
B -+ Yo - '115
0
1
0
C -+
Yo - '115
-+ Yo - "15
0
1
0
C -+ ~ - '115
A -+ Yo - 't15
Yo - "15
0
1
1
D
0
1
1
D -+
1
0
0
E -+ Yo - Y15
1
0
0
E -+ Yo - Y15
1
0
1
F -+ Yo - Y15
1
0
1
F -+ Yo - Y15
1
1
0
G -+
1
1
0
G -+
1
1
1
H
Yo - "15
-+ Yo - "15
1
1
1
Do - D15 -+ Yo
S7-10
Yo -
~5
- ~5
IDT7320/IDT7321 16-BIT CMOS
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7320 INSTRUCTION TABLE
FUNCTION
MNEMONIC
PIPELINE LEVELS
13
12
11
10
0
0
0
0
LDA
Do - D 15 -+ A
1
0
0
0
1
LDB
Do - D 15 -+ B
1
0
0
1
0
LDC
Do - D15 -+ C
1
0
0
1
1
LDD
Do - D15 -+ D
1
0
1
0
0
LDE
Do - D 15 -+ E
1
0
1
0
1
LDF
Do - D 15 -+ F
1
0
1
1
0
LDG
Do - D 15 -+ G
1
0
1
1
1
LDH
Do - D15 -+ H
1
1
0
0
0
LSHAH
Do - D15 -+ A -+ B -+ C-+D-+ E-+F-+G-+H
8
1
0
0
1
LSHAD
Do - D15 -+ A -+ B -+ C -+ D
4
1
0
1
0
LSHEH
Do - D15 -+ E -+ F -+ G -+ H
4
1
0
1
1
LSHAB
Do - D15 -+ A -+ B
2
1
1
0
0
LSHCD
Do - D15 -+ C -+ D
2
1
1
0
1
LSHEF
Do - D15 -+ E -+ F
2
1
1
1
0
LSHGH
Do - D15 -+ G -+ H
2
1
1
1
1
HOLD
Hold All Registers
-
IDT7321 INSTRUCTION TABLE
MNEMONIC
FUNCTION
PIPELINE LEVELS
13
12
11
10
0
0
0
0
LDA
Do - D 15 -+ A
0
0
0
1
LDB
Do - D 15 -+ B
1
0
0
1
0
LDC
Do - D15 -+ C
.1
1
0
0
1
1
LDD
Do - D15 -+ D
1
0
1
0
0
LDE
Do - D 15 -+ E
1
0
1
0
1
LDF
Do - D 15 -+ F
1
0
1
1
0
LDG
Do - D 15 -+ G
1
0
1
1
1
HOLD
Hold All Registers
-
1
0
0
0
LSHAG
Do - D15 -+ A -+ B -+ C -+ D -+ E-+F-+G
7
1
0
0
1
LSHAD
Do - D15 -+ A -+ B -+ C -+ D
4
1
0
1
0
LSHEG
Do - D15 -+ E -+ F-+G
3
1
0
1
1
LSHAB
Do - D15 -+ A -+ B
2
1
1
0
0
LSHCD
Do - D15 -+ C -+ D
2
1
1
0
1
LSHEF
Do - D15 -+ E -+ F
2
1
1
1
0
LDG
Do - D15 -+ G
1
1
1
1
1
HOLD
Hold All Registers
-
S7-11
IDT7320/IDT732116-BIT CMOS
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7321 PIPELINE CONFIGURATIONS
IDT7320 PIPELINE CONFIGURATIONS
Four 2-Level
Eight 1-Level
c£J
cb
cb
cb
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
c£J dS
cb c£j
c6 c:=E.
cb
~' ~'
14
: f';
One7-Level
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
SYMBOL
V
VCCM
Military Supply Voltage
4.5
5.0
5.5
V
Vee
Commercial Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
V1L
Input High Voltage
2.0
-
V
Input Low Voltage
-
-
0.8
V
-0.5 to +7.0
Operating
Temperature
Oto +70
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
50
50
rnA
TA
Three 2-Level
One 4-Level, One 3-Level
One 8-Level
Two 4-Level
Seven 1-Level
-55 to +125
°C
MIN. TYP. MAX. UNIT
PARAMETER
CAPACITANCE (TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
C IN
Input Capacitance
COUT
Output Capacitance
CONDITIONS
TYP.
UNIT
'-"N= OV
10
pF
VOUT= OV
12
pF
NOTE:
1. This parameter is sampled at initial characterization and is not
100% tested.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
Typ.(1) MAX.
MIN.
MIN.
MILITARY
TYP.(1) MAX.
UNIT
lIul
Input Leakage Current
Vee = Max., VOUT = 0 to Vce
-
0.1
5
10
pA
Output Leakage Current
Hi Z, Vee = Max., VOUT = 0 to Vec
-
0.1
5
-
0.1
IILOI
0.1
10
pA
2.4
-
-
2.4
-
-
V
-
0.4
-
-
0.4
V
Icc
Operating Power Supply Current
Outputs Open; f = 67MHz
leeol
Quiescent Power Supply Current
VIN ;;::; VIH, VIN ::;; "IL
leeo2
Quiescent Power Supply Current
'-"N;;::; Vec - 0.2V, \{N ::;; 0.2V
VOH
Output High Voltage
Vee = Min., 10H = -15.0mA (COM'L.),
10H= -12.0mA (MIL.)
VOL
Output Low Voltage
Vee = Min., 10L = 24.0mA (COM'L.),
10L = 20.0mA (MIL.)
NOTE:
1. Typical implies Vee = 5V and TA = +25°C.
S7-12
IDT7320/IDT732116-BIT CMOS
MULTilEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
(Vcc = 5V ± 10%. TA = O°C to
7320L10
7321L10
PARAMETER
MAX.
MIN.
MAX.
-
12
-
15
12
15
ns
3
-
4
ns
1
2
4
-
-
5
-
ns
-
2
-
2
-
ns
. :.: ..z.:.:::::::}::··:·
-
-
9
-
10
ns
...:::::;:.
-
-
8
-
9
ns
4
-
5
ns
-
4
-
5
-
-
-
12
-
15
ns
ClK to Yo - Y'5 Propagation Delay
-
-
-
.::;::-
.:.>::::;:::::::::/..,:::..:::
-.
(::t:::::::::::;:::::::~i::\:::·
Do - ~5 to ClK Setup Time
Do - 0'5 to ClK Hold Time
10 - 13 to ClK Hold Time
DE Enable Time
DE Disable Time
::::::£:::t\:· .:::.:\;:::::::?:..
.f:::· ..:::::::::;:;;: .
ClK Pulse Width HIGH
-
ClK Pulse Width lOW
-
ClK Period
i;:::::.:::::::;:·
AC ELECTRICAL CHARACTERISTICS - MILITARY
MIN.
ClK to Yo - Y'5 Propagation Delay
-
SElo - SElz to Yo - Y'5 Propagation Delay
-
Do - 0'5 to ClK Hold Time
10 10 -
h to ClK Setup Time
h to ClK Hold Time
ns
ns
ns
(Vcc = 5V ± 10%. TA = -55°C to 125°C)
7320112
7321 L12
PARAMETER
Do - 0'5 to ClK Setup Time
UNITS
MIN:
SElo - SElz to Yo - Y'5 Propagation Delay
h to ClK Setup Time
7320L15
7321115
MAX.
MIN.
10 -
+ 70°C)
7320112
7321L12
7320L15
7321115
MAX.
.::::::::;:-
::::)::;;:;:::::::t-.::\.
:. :::. :\\(( ··:·:··..·::i(::;::::::>
·:(:S:::::?:::· .::t::··:::::;)~·
::::::;::·::::.::::;:·.::. :::i;:::::t:::· -
7320L20
7321L20
MAX.
-
15
-
20
15
-
20
ns
4
-
5
-
ns
2
5
2
MIN.
UNITS
MIN.
MAX.
ns
3
-
ns
6
-
ns
3
-
ns
-
13
ns
13
ns
ns
DE Enable Time
DE Disable Time
.:%::.·'::t::::·
-
-
-
ClK Pulse Width HIGH
-
-
5
-
6
-
5
6
-
ns
-
-
15
-
20
ns
ClK Pulse Width lOW
ClK Period
AC TEST CONDITIONS
Input Pulse levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output load
-
To Output
GNDto 3.0V
3ns
1.5V
1.5V
See Figure 1
Pin
10
9
o-r...-vvv----.l
5000
O F
4 P
J
~~_______________~.
Vx
Figure 1. AC OutQl.Jt Test load (VX = 2.0V except for
DE enable/disable)
S7-13
1DT7320/IDT732116-BIT CMOS
MULTILEVEL PIPELINE REGISTERS
MILITARVANDCOMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
xxxx
Device Type
XX
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
~
B
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
P
C
J
L
Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
BLANK
I
__________________________
~
.12
15
S7-14
} Commercial
~~ }
Military
L
Low Power
7320
7321
16-Bit 8-Level Pipeline Register
16-Bit 7-Level Pipeline Register
_
...
--
---------
~
16-BIT CMOS
CASCADABLE ALU
PRELIMINARY
lOT 7381
lOT 7383
IntegratedDevice~lnc.
FEATURES:
DESCRIPTION:
• High-performance 16-bit Arithmetic Logic Unit (ALU)
The IDT7381 and IDT7383 are high-speed cascadable
Arithmetic Logic Units (ALUs). Both three-bus devices have two
input registers, ultra-fast 16-bit ALUs and 16-bit output registers.
With IDT's high-performance CEMOS technology, the
IDT7381/7383 can do arithmetic or logic operations in 20ns. The
IDT7381 functionally replaces four 54/74S381 four-bit ALUs in a
68-pin package.
The two input operands, A and B, can be clocked or fed through
for flexible pipelining. The F output can also be set into clocked or
flow-through mode. An output enable is provided for three-state
control of the output port on a bus.
. The IDT7381 has three function pins to select 1 of 8 arithmetic or
logic operations. The two Rand S selection pins determine
whether A, B, F or 0 are fed into the ALU. This ALU has carry out,
propagate and generate outputs for cascading using carry
look-ahead.
The IDT7383 has five function pins to select 1 of 32 arithmetic or
logic operations and the R, S input selections to the ALU. The R
andSALU inputscanbeA, B, F,OoraIl1s. ThisALU has a carry out
pin for cascading.
The IDT7381 and IDT7383 are available in 68-pin PLCC, LCe or
PGA packages. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B, for
high reliability systems.
• 20ns to 55ns clocked ALU operations
• Ideal for radar, sonar or image processing applications
• IDT7381:
- 54/74S381 instruction set (8 functions)
- Replaces Gould S614381 or Logic Devices L4C381
- Cascadable with or without carry look-ahead
• IDT7383:
- 32 advanced ALU functions
• - Cascadable without carry look-ahead
• Pipeline or flow-through modes
• Internal feedback path fC?r accumulation
• Three-state outputs
• TIL-compatible
• Produced with advanced submicron CEMOS ™ highperformance technology
• Available in 68-lead PGA and 68-pin surface mount PLCC,
LCC
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
8 0- 15
AO- 15
80-15
P.------:r--.........- -.........---,
G
..---~
<;6~---\
OVF~----~
z----~
~
FTF
. .--t-+-\--
. .__~+-__
____~---J
N
10-2
OVF..-----~
z.----~~
----------t--..
EN'F
~~---1
-------1"
FTF
GND
Vce
~ -------~
..---~
<;6 ..-----\
~
5 10-4
__~--__J
. .__~+-__
-----~G'~~I.--..u
---~__.,.-..
.......
'-
GND
Vcc
~ ------------~
IOT7381
~
FO- 15
IDT7383
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
© 1969 Integrated Device Technology, Inc.
. _ - - - _•.........
OSC-2033/-
__ _._--..
S7-15
._----_._-----_._.- ....
__
-._----_._
...•.
.. _..
_-
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7381/1DT738316-BIT CMOS CASCADABLE ALU
PIN CONFIGURATIONS
1DT7383
IDT7381
INDEX
INDEX
~~1~~1~~U~~~~~~~~
~iii~1~~U~~~~~~~~
A9
Al0
All
"A 12
A13
A14
A15
elK
Vee
GND
C 16
15
G
Z
OVF
~
FTF
:l10
:111
A9
A10
All
A12
A13
A14
A15
ClK
Vee
GND
C 1a
NC
N
1
00 C B7
59 [: B6
:l~
~ C B5
57 [: B4
:1 13
seC
B3
:) 14
55 [: B2
:l 15
54 C Bl
:1 16
53 [:
]17
J68-1
52 [:
&
:J 18
51 [: Nm
l68-2
]19
50 C FTAB
:120
49 [: RSl
:)21
48 [: RSo
:122
47 [: 12
:123
46 r: 11
:124
45 [: 10
:)25
:1 26
44 [: Co
2728293031 323334353637383940414243
~
Z
OVF
El'JF
FTF
:1 10
] 11
] 12
:J 13
:) 14
:J 15
:J 16
] 17
:1 18
:J 19
:) 20
:J 21
:)22
:J 23
:) 24
:J 25
:) 26
1
[:
[:
[:
[:
~ [:
55 [:
54 [:
B7
Ba
B5
B4
B3
B2
Bl
53 C !iL
&
52 [: ENA
l68-2
51 [: E"NB
50 [: FTAB
49 [: 14
48 [: 13
47 [: 12
46 [: 11
45 [: 10
44 [: Co
272829 30 31323334353637383940414243
J68-1
nnnnnnnnnnnnnnnnn
nnnnnnnnnnnnnnnnn
PLCC/LCC
TOP VIEW
PLCC/LCC
TOP VIEW
11
00
59
58
57
B7
B6
B4
B2
So rnt3 RSl
12
10
B5
B3
Bl
ENA FTAB RSo
11
Co
Fo
10
B7
Ba
B4
B2
So E'm
14
12
10
B9
B8
B5
B3
Bl ENA FTAB
13
11
Co
Fo
11
10
B9
B8
09
Bll
BlO
F2
Fl
09
Bll
BlO
F2
Fl
08
B13
B12
F4
F3
08
B13
B12
F4
F3
07
B15
B14
Fe
F5
07
B15
B14
Fe
F5
06
Al
Ao
F8
F7
06
Al
Ao
F8
F7
.
G68-1
G68-1
05
A3
A2
FlO
F9
05
A3
A2
FlO
F9
04
A5
A4
F12
Fl1
04
A5
A4
F12
Fl1
03
A7
A6
F14
F13
03
A7
A6
F14
F13
02
A8
A9
F15
02
A8
A9
OE"
F15
•
All
A13
A15 Vee
C16
G
OVF
~
Al0 A12
A14
ClK GND
j5
Z
rnr=
FTF
G
H
J
K
B
C
D
E
F
Pin 1"
Designator
•
l
All
Al0 A12
B
C
Vee
C 16
N
OVF
A14 ClK GND
NC
Z
Em: FTF
G
H
A13
D
A15
E
F
Pin 1
Designator
PGA
TOP VIEW
PGA
TOP VIEW
S7-16
J
K
l
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT7381/IDT7383 CMOS 16-BIT CASCADABLE ALU
PIN DESCRIPTIONS
IDT7381 AND IDT7383 PINS
PIN NAME
DESCRIPTION
I/O
Ao - A 15
I
Sixteen-bit data input port.
Bo - B15
I
Sixteen-bit data input port.
'ENA
I
Register enable for the A input port; active low pin.
i:NB
I
Register enable for the B input port; active low pin.
FTAB
I
Flow-through control pin. When this pin is high, both register A and B are transparent.
Fo - F15
0
Sixteen-bit data output port.
~
I
Register enable for the F output port; active low pin.
FTF
I
Flow-through control pin. When this pin is high, the F register is transparent.
ClK
I
Clock input.
'O't:
I
Output enable control pin. When this pin is high, the output port F is in a high impedance state. When low,
the output port F is active.
Co
I
Carry input. This pin receives arithmetic carries from less significant AlU components in a cascaded configuration.
C16
0
Carry output. This pin produces arithmetic carries to more significant AlU components in a cascaded configuration.
OVF
0
This pin indicates a two's complement arithmetic overflow.
Z
0
This pin indicates a zero output result.
Vee
Power supply pin, 5V.
GND
Ground pin, OV.
IDT7381 PINS
PIN NAME
RS o - RS 1
10 -12
DESCRIPTION
I/O
I
Two control pins used to select input operands for the Rand S multiplexers.
I
Three control pins to select the AlU function performed.
15
0
Indicates the carry propagate output state of the AlU.
G
0
Indicates the carry generate output state of the AlU.
IDT7381 RAND S MUX TABLE
IDT7381 ALU FUNCTION TABLE
RS 1
RS o
R MUX
S MUX
10
0
A
F
12
0
11
0
0
0
0
1
A
0
0
0
1
F =
1
0
0
B
0
1.
0
F=R+"S+Co
1
1
A
B
0
1
1
F = R + S + Co
1
0
0
F = RxorS
1.
0
1
F = RorS
1
1
0
F = RandS
1
1
1
F = all1's
FUNCTION
F=O
S7-17
- - - - - - - - - _.._.__..._.•.
__. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
R+
S + Co
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7381/IDT7383 16·BIT CMOS CASCADABLE ALU
PIN DESCRIPTIONS (Continued)
IDT7383 PINS
PIN NAME
DESCRIPTION
I/O
10 -14
N
I
Five control pins to select the ALU function performed.
0
The sign bit of an ALU operation.
IDT7383 ALU FUNCTION TABLE
FUNCTION
14
13
12
11
10
0
0
0
0
0
0
0
0
0
1
F = A or B
0
0
0
1
0
F=A+13orCo
0
0
0
1
1
F = A + B + Co
0
0
1
0
0
0
0
1
0
1
F=A+Co
F = AorF
0
0
1
1
0
F=A-1+Co
0
0
1
1
1
F=A+Co
0
1
0
0
0
F=A+F+Co
0
1
0
0
1
F = A or F
0
1
0
1
0
F=A+~+Co
0
1
0
1
1
F=A+F+Co
0
1
1
0
0
F=F+B+Co
0
1
1
0
1
F = AorB
0
1
1
1
0
F=F+'B"+Co
0
1
1
1
1
F = ~ + B.+ Co
1
0
0
0
0
F = AxorB
1
0
0
0
1
F = A and B
1
0
0
1
0
F=AandB
1
0
0
1
1
F = A xnor B
1
0
1
0
0
F=AxorF
1
0
1
0
1
F=AandF
1
0
1
1
0
F=AandF
1
0
1
1
1
F = all 1's
1
1
0
0
0
F=B+Co
1
1
0
0
1
F = AandH
1
1
0
1
0
F='B"+Co
1
1
0
1
1
F=B-1+Co
1
1
1
0
0
F = F + Co
1
1
1
0
1
F = Aor'B"
1
1
1
1
0
F=F-1+Co
1
1
1
1
1
F=~+Co
F=A+B+Co
S7':"18
--------_.. __.._ - - - - - - - - - - - - - - - -
IDT7381/IDT7383 CMOS 16~BIT CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
RATING
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
RECOMMENDED DC OPERATING CONDITIONS
COMMERCIAL
MILITARY
UNIT
SYMBOL
-0.5 to +7.0
-0.5 to +7.0
V
VCCM
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
50
50
mA
MIN.
TYP.
MAX.
UNIT
Military Supply
Voltage
4.5
5.0
5.5
V
Vee
Commercial
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PARAMETER
0
0
0
V
\lH
Input High Voltage
2.0
-
-
V
\lL
Input Low Voltage
-
-
O.S
V
CONDITIONS
TYP.
UNIT
VIN = OV
10
pF
VOUT= OV
12
pF
CAPACITANCE (TA= +25°C, f = 1.0MHz)
PARAMETER (1)
SYMBOL
CIN
COUT
Input CapaCitance
Output Capacitance
NOTE:
1. This parameter is sampled at initial characterization and is not
100% tested.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
Ilu l
Input Leakage Current
Vcc = Max., VOUT = 0 to Vcc
IILol .
Output Leakage Current
Hi Z, Vcc = Max.• VOUT
Icc
Operating Power Supply Current
Outputs Open; f = 25 MHz
= 0 to Vcc
COMMERCIAL
MILITARY
MIN. TYP.(l) MAX. MIN. Typ.(l) MAX.
-
0.1
5
-
0.1
5
30
60
UNIT
-
0.1
10
0.1
10
~A
30
SO
mA
~A
Iccal
Quiescent Power Supply Current
VIN ~ VIH ' VIN :::;; \lL
-
15
35
-
15
45
mA
ICC02
Quiescent Power Supply Current
VIN ~ Vcc -0.2V, VIN :::;; 0.2V
-
2
10
-
2
15
mA
VOH
Output High Voltage
Vcc = Min., 10H= -4.0mA
2.4
-
-
2.4
V
Output Low Voltage
Vcc = Min., 10L = S.OmA
-
-
0.4
-
-
-
VOL
0.4
V
NOTE:
1. Typical implies Vcc = 5V, TA =
+25°C
S7-19
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT7381/IDT7383 16-BIT CMOS CASCADABLE ALU
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
(Vee =. 5V ± 10%. TA = O°C to
+ 70°C)
MAXIMUM COMBINATIONAL PROPAGATION DELAYS
TO OUTPUT
7381L20
7383L20
FLAGS(2)
Fo - F15
FROM INPUT
7381 L25
7383L25
FLAGS(2)
Fo - F15
7381L40
7383L40
FLAGS (2)
Fo - F15
7381L55
7383L55
FLAGS(2)
Fo - F15
UNITS
FTAB = 0, FTF = 0
ClK
9
18
11
23
18
36
25
50
ns
Co
-
13
16
-
26
ns
18
23
-
36
-
36
-
-
50
ns
10 - 14 , RS O' AS, (1)
= 0, FTF
FTAB
=1
ClK
18
18
23
23
36
36
50
50
ns
Co
14
13
18
16
28
26
39
36
ns
20
18
25
23
40
36
55
50
ns
Ao- A,s. 8 0- B'5
-
16
-
20
-
32
-
44
ns
ClK
9
-
11
-
18
-
25
-
ns
Co
-
13
16
-
26
-
36
ns
18
-
23
-
36
-
50
ns
Ao- A,s. 8 0- B 15
17
16
21
20
34
32
47
44
ns
ClK
-
-
-
-
-
-
-
-
ns
Co
14
13
18
16
28
26
39
36
ns
10 - 14 , RS O' AS 1 (1)
20
18
25
23
40
36
55
50
ns
10 -14 , RS O' AS,(1)
= 1,FTF
FTAB
=0
10 - 14 • RS o• AS 1(1)
= 1, FTF = 1
FTAB
MINIMUM SETUP AND HOLD TIMES RELATIVE TO CLOCK (CLK)
7381L20
7383L20
INPUT
7381L25
7383L25
SETUP
HOLD
Ao- A15. 80- 815
4
0
5
0
8
Co
13
0
16
0
26
10 - 14 • ASO. AS1(1)
19
0
24
0
38
ENA.ENB.~
4
0
5
0
8
FTAB
FTAB
SETUP
7381L40
7383L40
HOLD
SETUP
7381L55
7383L55
HOLD
UNITS
SETUP
HOLD
0
11
0
ns
0
36
0
ns
0
52
0
ns
0
11
0
ns
ns
=0
=1
Ao- A 15. 8 0- 8'5
20
0
25
0
40
0
55
0
Co
20
0
25
0
40
0
55
0
ns
10 - 14 , AS O' AS1(1)
20
0
25
0
40
0
55
0
ns
ENA.ENS.~
-
-
-
-
-
-
-
-
ns
MINIMUM CLOCK CYCLE TIMES AND
PULSE WIDTHS
PARAMETER
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
7381L20 7381L25 7381L40 7381L55
7383L20 7383L25 7383L40 7383L55
UNITS
PARAMETER
7381 L20 7381L25 7381L40 7381L55
7383L20 7383L25 7383140 7383L55
UNITS
Clock lOW Time
5
6
10
14
ns
Enable Time
8
10
16
22
ns
Clock HIGH Time
5
6
10
14
ns
Disable Time
8
10
16
22
ns
20
25
40
55
ns
Clock Period
NOTES:
1. ForIDT7381. pins 10-1 2 , AS o• AS 1apply. ForIDT7383. pins 10-14 apply.
2. Flags are P. G. OVF. Z. C,6 for IDT7381. Flags are N. OVF. Z. C 16
for IDT7383.
S7-20
MILITARY AND COMMERCIAL TEMPERATURE RANGES·
IDT7381/IDT7383 CMOS 16·BIT CASCADABLE ALU
AC ELECTRICAL CHARACTERISTICS-MILITARY (Vee
= 5V ± 10%. TA = O°Cto +70°C)
MAXIMUM COMBINATIONAL PROPAGATION DELAYS
TO OUTPUT
7381L25
7383L25
FLAGS(2)
Fo - F1S
FROM INPUT
7381L30
7383L30
FLAGS(2)
Fo - fts
7381L40
7383L40
FLAGS(2)
Fo - fts
7381L55
7383L55
FLAGS(2)
Fo - fts
UNITS
=0
FT AB = 0, FTF
ClK
15
29
17
36
22
43
30
60
ns
Co
-
21
-
25
-
31
-
43
ns
29
-
36
-
43
-
60
ns
ns
10 - 14 , RS O' RS 1(1)
FTAB = 0, FTF = 1
ClK
29
29
36
36
43
43
60
60
Co
23
21
28
25
34
31
47
43
ns
10 - 14 , RS O' RS1(1)
33
29
39
36
48
43
66
60
ns
AO- A15 • BO- 8 15
-
26
-
31
-
38
-
53
ns
ClK
15
-
17
-
22
-
30
-
ns
Co
-
21
25
-
31
ns
36
-
43
-
43
29
-
60
ns
Ao- A15. 8 0- 8 15
28
26
33
31
41
38
56
53
ns
ClK
-
-
-
-
-
-
-
-
ns
FTAB = 1, FTF
=0
10 - 14 • RS o. RS1(1)
FTAB = 1, FTF = 1
Co
23
21
28
25
34
31
47
43
ns
10 -1 4 , RS O' RS1(1)
33
29
39
36
48
43
66
60
ns
MINIMUM SETUP AND HOLD TIMES RELATIVE TO CLOCK (ClK)
7381L25
7383L25
INPUT
SETUP
7381L40
7383L40
7381L30
7383L30
HOLD
SETUP
HOLD
SETUP
7381L55
7383L55
HOLD
UNITS
SETUP
HOLD
FTAB = 0
Ao- A15. 80- 815
7
0
8
0
10
0
13
0
ns
Co
21
0
25
0
31
0
43
0
ns
10 - 14 • RS o• RS 1(1)
31
0
37
0
46
0
62
0
ns
~.
7
0
8
0
10
0
13
0
ns
ENA.
EliJF
FTAB = 1
Ao- A15 • 8 0- 8 15
33
0
39
0
48
0
66
0
ns
Co
33
0
39
0
48
0
66
0
ns
10 -1 4 , RS O• RS 1(1)
33
0
39
0
48
0
66
0
ns
El'JA. EN B. Ef\J"F
-
-
-
-
-
-
-
-
ns
MINIMUM CLOCK CYCLE TIMES AND
PULSE WIDTHS
PARAMETER
MAXIMUM OUTPUT ENABLE/DISABLE TIMES
7381L25 7381L30 7381L40 7381L55
7383L25 7383L30 7383L40 7383L55
UNITS
PARAMETER
7381L25 7381L30 7381L40 7381L55
7383L2S 7383L30 7383L40 7383LSS
UNITS
Clock LOW Time
6
8
10
14
ns
Enable Time
13
16
19
26
ns
Clock HIGH Time
6
8
10
14
ns
Disable Time
13
16
19
26
ns
Clock Period
25
30
40
55
ns
NOTES:
1. For IDT7381. pins 10-1 2, RS o• RS 1apply. For IDT7383. pins 10- 14 apply.
2. Flags are P. G. OVF. Z. ~6 for IDT7381. Flags are N. OVF. Z. C 16
for IDT7383.
S7-21
IDT7381/IDT7383 16-BIT CMOS CASCADABLE ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
To Output
GNOto 3.0V
3ns
1.5V
1.5V
See Figure-1
Pin
5000'
O'-I--...--.....'VV'v--'l
40 pF
1"1-------..1
v,
Figure 1. AC OutQljt Test Load 0/x = 2.0V except for
DE" enable/disable)
ORDERING INFORMATION
lOT
xxxx
x
X
OeviceType
Package
Process/
Temperature
~~~IMk
J
'-----------\ L
G
20
25
40
55
L
7381
7383
S7-22
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Pin Grid Array
}
Commercial
, Low Power
16-BitALU
16-Blt ALU
25
30
40
55
}
Military
t;)
Integrated DeviceTechnology.Inc.
16-BIT CMOS
CASCADABLE ALU
ADVANCE
INFORMATION
lOT 7384
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT7384 is a high-speed cascadable Arithmetic Logic Unit
(ALU). This three-bus device has a 4-level pipeline register on one
input port (A port) and a single input register on the other input port
(B port). An ultra-fast 16-bit ALU, a funnel shifter with merge capabilities, and three accumulators make up the heart of the IDT7384.
With lOT's high-performance CEMOS ™ technology, the IDT7384
can do arithmetic or logic operations in 20ns. Results of ALU operations can be scaled, rounded, or bit reversed for FFT address
generation using the IDT7384 output stage.
The two input operands, A and B, can be clocked or fed through
for flexible pipelining. The F accumulators can also be set into
clocked or flow-through mode. The A port has a 4-level pipeline
register that can be configured as 1 four-level, 2 two-level, or
4 single-level pipelines. The three LDAO-LDA2 control pins set the
configuration and the register loaded.
The IDT7384 has five function pins to select 1 of 32 arithmetic or
logic operations and the R, S input selections to the ALU. The R
and S ALU inputs can be A, B, F, or all1's. This ALU has a carry out
pin for cascading. Three accumulators are provided on the
IDT7384 for intermediate result storage.
The IDT7384 funnel shifter will do logical shifts, rotates, and
rotates with merges. The 16-bit R-multiplexer and 8-multiplexer
inputs can be concatenated in either order for 32-bit logical shifts.
A 16-bit result is extracted at the funnel shifter output. The Rmultiplexer input can be rotated or rotated and merged with the F·
feedback bus using the S-multiplexer input as a mask.
The output stage of this ALU can round the F result up or down
by one bit. The F result can also be arithmetically or logically
shifted by one bit under the IDT7384 output control (FSO-FS5). Bit
reversal can be performed on the F result to generate fast Fourier
transform (FFT) addresses.
An output enable is provided for three-state control of the output
port on a bus.
The IDT7384 is available in 84-pin PLCC or PGA packages. Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B for high reliability systems.
High-performance 16-bit Arithmetic Logic Unit (ALU)
20ns to 55ns clocked ALU operations
Ideal for radar, sonar, or image processing applications
Includes flexible funnel shifter
Pipeline or flow-through modes
MUlti-level pipeline register on one input port
Three accumulators with an internal feedback path
Scaling shifter on output stage for dynamic range control
Rounding on output stage
Bit reversal on output stage for FFT address generation
Three-state outputs
TTL-compatible
Produced with advanced submicron CEMOS ™ technology
Available in 84-lead PGA and 84-pin surface mount PLCC
Military product compliant to MIL-STD-883, Class B
CEMOS is a trademark of Integrated Device Technology, Inc.
jMILlTARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
DSC-2036/-
S7-23
I
JANUARY 1989
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT73B4 16·BIT CMOS CASCADABLE ALU
FUNCTIONAL BLOCK DIAGRAM
BO-B15
AO-A15
16'~
'}16
LDAOLDA2
3
AREG
FILE
-T-
<
[H
AO
•• - - A1- - - - ----A2----- - - - A3 - - - - •
-rt
,4
ABOAB3
1
'\
1
-,
AMUX
BMUX
FFFFH
~
1
I
~
I
R MUX
~
S MUX
~I
FUNNEL
SHIFTER
-
\\
N/G
C16
OVF/P
\
Z
\
FENOFEN1
-'1
,2
,
~r
-' -
H
F REG 1
<
rt
-
J
1
SI016
,
MSW/
[SW
T
I
•
BIT REV
~
-
1
-I
5
,
'\
10-1 4
CO
I
~rt
--I
F REG2
1
2
FSOFS5 7'
•
MUX
I;-
I
I
16-BIT ALU
161FSOFS1
CL K
FFFFH
I
I
BREG
T
FREG3
_I
MUX
<~,
I
1
1
r
-~
FMUX
-.'"
ROUND
I
1
~~
• • •1
YMUX
~O~Z
o
Q~~~~
w
PLCC
TOP VIEW
FS 3
FS 1
FS o
SIOO
FS 4
OE
FS 5
F14
F15
Fll
F12
FlO
F8
F 13
F9
F7
F6
F5
F4
F3
F2
Fa
Z
C16
GND
A 15
A12
Ala
A9
A8 1
FS 2 SI016 OVF/
P
A 13
A14
All
A8 3
A8 2
A8
N/G"
Vee
ClK
A8 0
A7
A6
A5
Al
A3
A2
Ao
8 15
A4
8 12
8 13
8 14
8 10
8 11
lDA2
89
GS4-1
PIN 1 DESIGNATOR
./
14
FEN1
F1
F8 1
Co
12
MSW/
lSW FE NO
F8 0
10
11
13
ENS
82
GND
81
84
87
lDA1
88
80
83
85
86
lDAO
PGA
TOP VIEW
S7-25
----
._-------------------
Bit-Slice Microprocessor Devices (MICROSLICE™) and EDC
._._._-----_ ....... -_.......
_---
BIT-SLICE MICROPROCESSOR DEVICES (MICROSLICE)
AND MEMORY SUPPORT
MICROSLICE
MEMORY SUPPORT
Microprogrammable microprocessor building blocks offer the
system designer the ultimate in system hardware and software
performance and flexibility. Integrated Device Technology through
architectural enhancements and high-performance, low power
CEMOS technology advance bit-slice performance levels far beyond competitive components.
The IDT49C400 building block family exemplify this performance leadership, providing increased circuit density over bipolar
building blocks at equivalent and faster speeds. Featured in this
product family are the world's fastest 16-bit microprocessors and
sequencers. Also, IDT manufactures pin-compatible CMOS 2900
products, the IDT39COO family, which offer speed upgrades of up
to 50% faster than equivalent bipolar components.
In addition to providing high performance and increased levels
of integration,low power CMOS technology permits the aggressive
adaptation of surface mount packages, especially 25mil center
pin to pin spacing packages. The IDT49C402 is the first product
available in a 25mil center 68-pin ceramic quad flatpack, with a
footprint 9f 0.470 square inches, 53% smaller than a Pin Grid Array
or a Plastic Leaded Chip Carrier (PLCC).
Error Detection and Correction (EDC) plays a major role in
ensuring data integrity for large, high-speed memory arrays. lOT
pioneered CMOS EDC units in 1986 with the introduction of the
39C60, 16-bit EDC, detecting errors in 20ns maximum. The Industry standard IDT49C460 has established a new level for high performance EDC, with 16ns maximum detect times. And the
IDT49C460 is the only 32-bit EDC cascadable to 64-bit, ideal for today's high bandwidth memory systems.
With the announcement ofthe Flow-thru EDC'" IDT49C465,IDT
has established the next industry standard for high performance
memory error detection and correction. Using a flow through architecture, memory system data correction throughput is effectively
doubled in 64-bit applications.
IDT will continue to introduce speed upgrades to existing products and offer new architectural enhancements to improve system
performance.
-_.. _ - - _ . _ - - - - - - - - - - - -
TABLE OF CONTENTS
CONTENTS
PAGE
Bit-Slice Microprocessor Devices (MICROSLICE TM) and Error Detection and Correction
4-Blt Microprocessor Slice (14-56) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
lOT 39C01
lOT 39C02
Carry~Lookahead Generator. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . ... . . . .. . . . . . . ... . . .. ..
"lOT 39C03
4-Blt Microprocessor Slice (14-56) ............ ;..................................
lOT 39C10
12-Blt Sequencer (14-56,14-197) . . . . . . .. . . . . . . . . ... .. . . . .. . . . . . . . . . .. . . .. ..... . ..
lOT 49C25
Mlcrocycle Length Controller............................. ............ ...........
lOT 49C402
16-Bit Microprocessor Slice (14-41, 14-56, 14":197, 14-200, 14-203) .....................
lOT 49C403
16-Bit Microprocessor Slice W/SPC™ (14-41, 14-56, 14-154, 14-197, S14-1) .............
lOT 49C404
32-Blt Microprogram Microprocessor W/SPC™ ....................................
lOT 49C410
16-Bit Sequencer (14-56,14-86,14-197,14-200) .. ................ ......... ..........
lOT 49C411
20-Blt Interruptable Sequencer W/SPC™ ..........................................
lOT 39C60
16-Bit Cascadable EDC (14-22, S14-49) ............................................
lOT 49C460
32-Bit Cascadable EDC (14-22, S14-49) ............................................
lOT 49C465
32-Bit Flow-Thru Error Detection and Correction Unit ..................................
8-1
8-12
8-16
8-63
8-117
S8-1
S8-13
8-182
S8-4S
8-208
S8-56
S8-83
S8-108
16-BIT CMOS
MICROPROCESSOR SLICE
Integrated Device lechnology.lnc.
lOT 49C402
lOT 49C402A
lOT 49C402B
MICROSLICE ™ PRODUCT
FEATURES:
DESCRIPTION:
• Functionally equivalent to four 2901s and one 2902
• IDT49C402B 55% faster than four 2901Cs and one 2902A
• Expanded two-address architecture with independent, simultaneous access to two 64 x 16 register files
• Expanded destination functions with 8 new operations allowing
Direct Data to be loaded directly into the dual-port RAM and Q
Register
The IDT49C402s are high-speed, fully cascadable 16-bit CMOS
microprocessor slice units which combine the standard functions of
four 2901s and a 2902 with additional control features aimed at enhancing the performance of bit-slice microprocessor designs.
The IDT49C402s include all of the normal functions associated
with standard 2901 bit-slice operation: (a) a 3-bit instruction field (10,
I" 12) which controls the source operand selection for the ALU; (b) a
3-bit microinstruction field (13, 14, 15) used to control the eight possible functions of the ALU; (c) eight destination control functions
which are selected by the microcode inputs (16, h, 18); and (d) a tenth
microinstruction input, Ig, offering eight additional destination control functions. This Ig input, in conjunction with 16, 17 and 18, allows for
shifting the Q Register up and down, loading the RAM or Q Register
directly from the D inputs without going through the ALU and new
combinations of destination functions with the RAM A port output
available at the Y output pins of the device.
Also featured is an on-chip dual-port RAM that contains 64 words
by 16 bits-four times the number of working registers in a 2901.
The IDT49C402s are fabricated using CEMOS, a CMOS technology designed for high performance and high reliability. These performance enhanced devices feature both bipolar speed and bipolar
output drive capabilities while maintaining exceptional microinstruction speeds at greatly reduced CMOS power levels.
• Clamp diodes on all inputs provide noise suppression
• Fully cascadable
• 68-pin plastic and ceramic PGA, Shrink-DIP (600 mil, 70 mil centers), LCC (25 and 50 mil centers) and Ceramic Quad Flatpack
(25 mil centers)
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
RAMo
CLOCK
0
1
2
ALU
SOURCE
3
4
5
ALU
FUNCTION
z
Q
I-
U
6
7 DESTINATION
8
CONTROL
9
w
=>8
READ ADDRESS
~U
Zw
_0
0
ex:
()
~
DIRECT DATAIN
CARRY IN
MSS
DATAour
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
I MILITARY
©
AND COMMERCIAL TEMPERATURE RANGES
88-1
I
JANUARY 1989
DSC-9011/-1
1989 Integrated Device Technology. Inc.
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
'!EO
O~~~~~~~~~~~Ua~~~
9 8 7 6 5 4 3 2 1 68 67 68 65 6lI 63 62 61
O2
03
04
05
06
07
GND
08
09
0 10
0 11
0 12
0 13
0 14
0 15
Y15
Y14
10
11
12
13
14
15
16
17
18
19
20
21
Pin 1 indicator
for PLCC
A3
A2
Al
Ao
13
14
15
10
11
12
~
22
Bo
Bl
B2
B3
23
24
25
26
B4
LCC/PLCC
TOP VIEW
DIP
TOP VIEW
9 8 76 5 4 3 2
O2
17
18
19
MSS
RAM 15
0 15
Cn +16
PIOVR
G/F15
F=O
Y9
YlO
Yll
Y12
Y13
Y14
0 3
0 4
0 5
0 6
0 7
GND
08
09
010
01 1
0 12
0 13
0 14
0 15
Y15
Y 14
10
11
12
13
14
15
16
17
18
19
PIN
1
1 686766 6564 636261
•
60
~
59
IDENTIFICATION
58
57
56
OE-68
50
49
48
47
46
45
44
2728 29303132 3334 3536 37 383940 414243
PGA
TOP VIEW
CEROUAD
TOP VIEW
S8-2.
55
54
53
52
51
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/AJB 16-BIT CMOS MICROPROCESSOR SLICE
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
I/O
Aa- A 5
I
Six address inputs to the register file which selects one register and displays its contents through the A port.
8o- B5
I
Six address inputs to the register file which selects one of the registers in the file, the contents of Which is displayed through
the B port. It also selects the location into which new data can be written when the clock goes LOW.
.
10-1 9
I
Ten instruction control lines which determine what data source will be applied to the ALU I (0. 1.2), what function the ALU will
perforlT'! 1(3. 4, 5). and what data is to be deposited in the Register or the register file 1(6. 7, 8. 9). Ori~inal 2901 destinations are
selected if 19 is disconnected. In this mode, proper 19 bias Is controlled by an Intemal pullup resistor to Vee.
Da-D15
I
Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU,
the LSB.
Ya-Y 15
0
Sixteen three~state output lines which, when enabled, display either the sixteen outputs of the ALU or the data on the A port of
the register stack. This Is determined by the destination code I(B, 7, 8. 9).
G/F15
0
A multipurpose pin which indicates the carry generate (<3) function at the least significant and intermediate slices or as F15 the
most significantALU output (sign bit). G/F15 selection is controlled by the MSS pin. If MSS = HIGH, F15 is enabled. If MSS =
LOW, G is enabled.
=0
0
Open drain output which goes HIGH if the Fa -F1S ALU outputs are all LOW. This indicates thatthe result of an ALU operation is
zero (positive logic).
F
Cn
a
a Register or RAM. Do is
I
Carry-in to the Intemal ALU.
C n +1B
0
Carry-out of the internal ALU.
0 15
I/O
Bidirectional lines controlled by 1(6.7,6.9). Both are three-state output drivers connected to the TTL-compatible inpu~. .
When the destination code on 1(6. 7. 6. 9) indicates an up shift, the three-state outputs are enabled, the MSB of the 0 Register IS
available on the 0 15 pin and the MSB of the ALU output is available on the RAM 15 pin. When the destination code indicates a
down shift, the pins are the data inputs to the MSB of the 0 Register and the MSB of the RAM.
I/O
Both bidirectional lines function identically to 0 15 and RAM 15 lines except they are the LSB of the
RAM 15
00
RAMo
OE
a Register and RAM.
I
Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs are enabled.
P/OVR
0
A multipurpose pin which indicates the carry propagate (P) output for performing a carry lookahead operation or overflow
(OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVR, at the most significant end of the word, indicates
that the result of an arithmetic two's complement operation has overflowed into the sign bit. P/OVR selection is controlled by
the MSS pin. If MSS = HIGH, OVR is enabled. If MSS = LOW, P is enabled.
CP
I
The clock input. LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock LOW time is
internally the write enable time for the 64 x 16 RAM which compromises the master latches of the register file. While the clock is
LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM outputs. Synchronous .
MASTER-SLAVE operation of the register file is achieved by this.
MSS
I
When HIGH, enables OVR and F,5 on the P/OVR and G/F15 pins. When LOW, enables G and P on these pins. If left open,
internal pullup resistor to Vcc provides declaration that the device is the most significant slice.
DEVICE ARCHITECTURE:
The IDT49C402 CMOS bit-slice microprocessor is configured
sixteen bits wide and is cascadable to any number of bits (16, 32, 48,
64). Key elements which make up this 16-bit microprocessor slice
are the (1) register file (64 x 16 dual-port RAM) with shifter, (2) ALU
and (3) 0 Register and shifter.
REGISTER FILE-A 16-bit data word from one of the 64 RAM
registers can be read from the A port as selected by the 6-bit A ad"
dress field. Simultaneously, the same data word, or any other word
from the 64 RAM registers, can be read from the B port as selected
by the 6-bit B address field. New data is written into the RAM register
location selected by the B address field during the clock (CP) LOW
time. Two sixteen-bit latches hold the RAM A port and B port during
the clock (CP) LOW time, eliminating any data races. During clock
HIGH these latches are transparent, reading the data selected by the
A and B addresses. The RAM data input field is driven from a four~
input multiplexer that selects the ALU output or the D inputs. The
ALU output can be shifted up one position, down one position or not
shifted. Shifting data operations involve the RAM15 and RAMo I/O
pins. For a shift up operation, the RAM shifter MSB is connected
to an enabled RAM15I/O output while the RAMo I/O input is selected
as the input to the LSB. During a shift down operation, the RAM
shifter LSB is connected to an enabled RAMo I/O output while the
IRAM<5 110 inpul is selected as the input to the MSB.
ALU - The ALU can perform three binary arithmetic and five logic
operations on the two 16-bit input words Sand R. The S input field is
driven from a 3-input multiplexer and the R input field is driven from
a 2-input multiplexer with both having a zero source operand. Both
multiplexers are controlled by the 1(0.1,2) inputs. This multiplexer
configuration enables the user to select various pairs of the A, B, 0,
and "0" inputs as source operands to the ALU. Microinstruction
inputs 1(3,4.5) are used to select the ALU function. This high-speed
ALU cascades to any word length,providing carry-in (C n), carry-out
(C n +16) and an open-drain (F =0) output. When all bitsoftheALU
are zero, the pull-down device of F
0 is off, allowing a ~ire-OR of
this pin over all cascaded devices. Multipurpose pins G/F15 and
f5/0VR are aimed at accelerating arithmetic operations. For intermediate and least significant slices, the MSS pin is programmed
LOW, selecting the carry-generate (G) and carry-propagate (f5'j output functions to be used by carry lookahead logic. Forthe most significant slice, MSS is programmed high, selecting the sign-bit (F15)
and the two's complement overflow (OVR) output functions. The
sign bit (F15) allows the ALU sign bit to be monitored without enabl ing the three-state ALU outputs. The overflow (OVR) output is high
when the two's complement arithmetic operation has overflowed
into the sign bit as logically determined from the Exclusive-OR of
the carry-in and carry-out of the most significant bit of the ALU, The
ALU data outputs are available at the three-state outputs Y(a-15) or as
58-3
-----,
... ,
._.._--_ .. -
o
=
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
Inputs to the RAM register file and 0 Register under control of the
1(6,7, 8, 9) Instruction Inputs,
a REGISTER-The 0 Register Is a separate 16-blt file Intended
for multiplication and division routines and can also be used as an
accumulator or holding register for other types of applications. It Is
driven from a 4-lnput multiplexer. In the no-shift mode, the multiplexer enters the ALU F output or Direct Data into the 0 Register. In
either the shift up or shift down mode, the multiplexer selects the 0
Register data appropriately shifted up or down. The 0 shifter has
ALU SOURCE OPERAND CONTROL
12
10
11
ALU FUNCTION CONTROL
MICROCODE
MNEMONIC
OCTAL
CODE
R
S
15
OCTAL
CODE
ALU
FUNCTION
SYMBOL
L
L
L
0
A
0
ADD
L
L
L
0
R Plus S
R+S
L
L
H
1
A
B
SUBR
L
L
H
1
S Minus R
S-R
ZO
L
H
L
2
0
0
SUBS
L
H
L
2
R Minus S
R-S
ZB
L
H
H
3
0
B
OR
L
H
H
3
RORS
RVS
ZA
H
L
L
4
0
A
AND
H
l
l
4
RANDS
R"S
DA
H
L
H
5
D
A
NOTRS
H
l
H
5
RANDS
R"S
DO
H
H
L
6
D
0
EXOR
H
H
L
6
REX-OR S
R'V'S
DZ
H
H
H
7
D
0
EXNOR
H
H
H
7
REX-NOR S
R'V'S
I S,4,3,I:z,1,O
0
0
0
0
5
6
0
0
0
0
3
4
7
1
1
1
1
2
2
2
2
13
AB
OCTAL
2
2
2
1
14
AO
ALU ARITHMETIC MODE FUNCTIONS
1
1
1
2
o
ALU SOURCE
OPERANDS
MICROCODE
MNEMONIC
two ports, 00 and 015, which operate comparably to the RAM shifter.
They are controlled by the 1(6,7,8,9) Inputs,
The clock input of the IDT49C402 controls the RAM,O Register
and A and B data latches. When enabled, the data is clocked into the
Register on the LOW-to-HIGH transition. When the clock is HIGH,
the A and B latches are open and pass data that is present at the
RAM outputs. When the clock is LOW, the latches are closed and
retain the last data entered. When the clock is LOW and 1(6. 7. 8,9) define the RAM as the destination, new data will be written into the RAM
file defined by the B address field.
Cn
FUNCTION
ADD
A+O
A+B
D+A
D+O
ADD·
plus one
A+0+1
A+B+1
D+A+1
D + 0 + 1
PASS
0
B
A
D
Increment
0+1
B+1
A + 1
D + 1
Decrement
0-1
B-1
A-1
D -1
PASS
0
B
A
D
2's com).
(Negate
-0
-B
-A
-D
Subtract
(2's Comp.)
O-A
B-A
A-D
O-D
A-O
A-B
D-A
D-O
7
2
1's Compo
-0 -1
-B -1
-A -1
-D -1
0
o -A-1
1
B-A-1
A-D-1
0- D-1
A- 0-1
A-B-1
D-A-1
D - 0-1
5
6
0
1
5
6
OCTAL
FUNCTION
2
3
4
7
ALU LOGIC MODE FUNCTIONS
=H
GROUP
2
3
4
Cn
GROUP
0
1
=L
Subtract
(1'S Comp.)
15,4,3,
4
4
4
4
3·
3
3
3
6
6
6
6
7
7
7
7
7
7
7
7
S8-4
12,1,0
0
1
5
6
GROUP
AND
A"O
A"B
D" A
D"O
OR
AVO
AVB
DVA
DVO
EX-OR
A'V'O
A'V'B
D'V'A
D'V'O
EX-NOR
A'V'O
~
D'V'A
D'V'O
0
1
5
6
0
1
5
6
0
1
5
6
2
3
4
7
6
6
6
6
3
4
7
3
3
3
3
3
4
7
0
INVERT
B
A
D
PASS
0
B
A
D
PASS
0
B
A
D
·ZERO"
0
0
0
0
MASK
A"O
A"B
B"A
0"0
2
2
4
4
4
4
3
4
7
2
5
0
5
1
5
5
5
6
FUNCTION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
SOURCE OPERAND AND ALU FUNCTION MATRIX (1)
12,1,OOCTAl
OCTAL
15,4,3
0
AlU
FUNCTION
2
1
5
4
3
6
7
AlU SOURCE
A,B
0,0
O,B
O,A
D,A
D,O
D,O
A+O
A+B
0
B
A
D+A
D+O
D
A,O
0
Cn = L
R Plus S
Cn = H
A + 0 + 1
A+B+1
0+1
B+1
A + 1
D+A+1
D + 0 + 1
D + 1
0- A-1
B-A-1
0-1
B-1
A-1
A - D-1
0- D-1
-D -1
1
Cn = L
S Minus R
Cn = H
O.-A
B-A
0
B
A
A-D
O-D
-D
A-O -1
A-B-1
-0 - 1
-B -1
-A -1
D - A-1
D - 0-1
D -1
2
Cn = L
R Minus S
Cn = H
A-O
A-B
-0
-B
-A
D-A
D-O
D
3
RORS
AVO
AVB
0
B
A
DVA
DVO
D
4
RANDS
AAO
AAB
0
0
0
DA A
DAO
0
5
RANDS
AAO
AAB
0
B
A
DA A
DAO
0
6
REX-OR S
A'V'O
A'V'B
0
B
A
D'V'A
D'V'O
D
7
REX-NOR S
A'V'O
A'V'B
0
B
A
D'V'A
D"V'O
D
NOTE:
1. + = Plus; - = Minus; A = AND;'V'= EX-OR; V = OR
ALU DESTINATION CONTROL(1)
RAM
FUNCTION
MICROCODE
MNEMONIC
I
16
HEX
CODE SHIFT
19
18
17
OREG
H
L
L
L
8
NOP
H
L
L
H
9
RAMA
H
L
H
L
A
o REGISTER
FUNCTION
RAM
SHIFTER
Y
OUTPUT
RAM ,s
Q
SHIFTER
0 '5
LOAD
SHIFT
X
NONE
NONE
F-+O
F
X
X
X
X
X
NONE
X
NONE
F
X
X
X
X
NONE
F-+B
X
NONE
A
X
X
X
X
X
NONE
RAMF
H
L
H
H
B
NONE
F-+B
RAMOD
H
H
L
L
C
DOWN
F/2-+B
LOAD
DOWN 0/2-+0
RAMo
00
F
X
X
X
X
F
Fa
IN '5
00
iN '5
RAMD
H
H
L
H
D
DOWN
F/2-+B
X
NONE
F
Fa
IN '5
00
RAMOU
H
H
H
L
E
UP
2F-+B
UP
20-+0
F
INa
F'5
INa
RAMU
H
H
H
H
F
UP
2F-+B
X
NONE
F
INa
F'5
X
X
0
'5
0 '5
DFF
L
L
L
L
0
NONE
D-+B
NONE
F-+O
F
X
X
X
X
DFA
L
L
L
H
1
NONE
D-+B
NONE
F-+O
A
X
X
X
X
FDF
L
L
H
L
2
NONE
F-+B
NONE
D-+O
F
X
X
X
X
FDA
L
L
H
H
3
NONE
F-+B
NONE
D-+O
A
X
X
X
X
XODF
L
H
L
L
4
X
NONE
DOWN 0/2-+0
F
X
X
00
IN
DXF
L
H
L
H
5
NONE
D-4B
X
NONE
F
X
X
00
X
H
H
L
6
X
NONE
UP
20-+0
F
X
X
INa
0,5
XOUF
L
Existing 2901
Functions
'5
New Added
IDT49C402
Functions
XDF
L
H
H
7
NONE NONE D-+O
H
X
F
X
X
X
0,5
NOTE:
1. X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
B = Register Addressed by B inputs.
UP is toward MSB; DOWN is toward LSB.
S8-5
.
__ _-_ ...._.. _ - - _ . __._-----_.
..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A1B 16-BIT CMOS MICROPROCESSOR SLICE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
CIN
COUT
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +150
°C
PT.
Power Dissipation
1.5
1.5
W
lOUT
DC Output Current
50
50
mA
(TA= +25°C, f =1.0MHz)
PARAMETER(l)
CONDITIONS
Input Capacitance
Output Capacitance
TYP.
UNIT
"IN = OV
5
pF
VOUT = OV
7
pF
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS may cause permanent damage to the device. This Is a stress ratIng only and functional operation of the devIce at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Vce = 5.0V ± 5% (Commercial)
Vec = 5.0V ± 10% (Military)
TA = O°C to + 70°C
TA = -55°C to + 125°C
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MAX.
UNIT
Input HIGH Level
Guaranteed Logic High Level (4)
2.0
-
-
V
"IL
Input LOW Level
Guaranteed Logic Low Level (4)
-
-
0.8
V
IIH
Input HIGH Current
Vee = Max., VIN = Vee
0.1
5
~A
IlL
Input LOW Current
Vee = Max., "IN = GND
IoH = -300~A
VOH
Output HIGH Voltage
Vee = Min.
"IN = "IH or "IL
IcH = -12mA MIL.
IoH = -15mA COM'L.
VOL
Output LOW Voltage
Vec = Min.
"IN = "IH or"lL
Off State (High Impedance)
Output Current
Vee = Max.
los
Output Short Circuit Current
Vee = Min., VOUT = OV
-5
~A
Vce
4.3
-
V
2.4
4.3
VLC
IcL = 300~A
-
GND
-
0.3
0.5
IoL = 24mA COM'L.
-
0.3
0.5
-0.1
-10
0.1
10
-15
-30
-
Vo = Vee (Max.)
(3)
-0.1
VHe
. 2.4
IoL = 20mA MIL.
Va = OV
loz
MIN.
TYP.(2)
"IH
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment. Guaranteed by design.
S8-6 .
V
~A
mA
IDT49C402/AIB 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = 0 C to + 70 C
TA = -55°C to +125 0 C
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL
ICCOH
ICCOL
ICCT
ICCD
Vcc
Vcc
= 5.0V ±5% (Commercial)
= 5.0V±10% (Military)
TEST CONDITIONS
PARAMETER
MIN.
TYP.(2)
MAX.
Quiescent Power Supply Current
CP = H (CMOS Inputs)
Vcc = Max.
VHC '.S VIH ,VIL '.S VLC
fcp = 0, CP = H
MIL.
-
150
265
COM'L.
150
215
Quiescent Power Supply Current
CP = L (CMOS Inputs)
Vcc = Max.
VHC $ VIH, VIL '.S VLC
fcp = 0, CP = L
MIL.
-
80
135
COM'L.
-
80
110
Quiescent Input Power Supply(S)
Current (per Input @ TIL High)
Vcc = Max. VIH = 3.4V, fcp = 0
Dynamic Power Supply Current
Vcc = Max.
VHC $ VIH , \1L ~ V LC
Outputs Open,
= L
rn:
Vcc = Max., fcp = 10MHz
Outputs Open, DE = L
CP = 50% Duty cycle
VHC ~ VIH , VIL ~ VLC
ICC
(1)
Total Power Supply Current
rnA
rnA
MIL.
-
0.3
0.6
COM'L.
-
0.3
0.5
MIL.
-
2.0
3.0
COM'L.
-
2.0
2.5
MIL.
-
135
255
COM'L.
-
135
190
MIL.
-
145
265
COM'L.
-
145
200
(6)
Vcc = Max., fcp = 10MHz
Outputs Open,
= L
CP = 50% Duty cycle
\1H = 3.4V, VIL = O.4V
rn:
UNIT
mAl
Input
mAl
MHz
rnA
NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccoH, then dividing by the total number of inputs.
6. Total Supply Current isthe sum ofthe Quiescent current and the Dynamic current (at either CMOS orTIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = IccoH(CDH) + IccoL (1 - CD H) + ICCT (NT X DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fcp = Clock Input frequency
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the OUT power pins.
S8-7
3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a static environment. To allow fortesting
and hardware-induced nOise, lOT recommends using VIL $ OV
and VIH ;::: 3V for AC tests.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
CYCLE TIME AND CLOCK CHARACTERISTICS
IDT49C4028
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
COM'L
The tables below specify the guaranteed performance of the
IDT49C4028 overthe-55°C to +125°CandOOCto +70°Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.
CL
F'' '
I{
Minimum Clock LOW Time)},::::.:::
I
~~+-_9_-+_n_s~
,/}0i8t+1
9
ns
Minimum Clock Period./::m::':=:::",,:..·:24
20
ns
Minimum Clock HIGH Time ..
COMBINATIONAL PROPAGATION DELAYS (1)
UNIT
Read-Modify-Write Cycle (from
~
selection of A. B registers to end
ns
of cycle)
;:;:;:;:;+'---+-----l
Maximum Clock Frequency to
L:,:;:::;.:·.·': Ii,:::::".
shift Q (50% duty cycle.
[))'4?·.
49
MHz
I = C32 or E32)
{::
··"......:.;::::'qi%~\,:_ _--+ _ _~
= 50pF
TO OUTPUT
FROM INPUT
UNIT
MIL COM'L MIL COM'L. MIL COM'L. MIL. COM'L. MIL. COM'L :~fm; ¢d'~m~; MIL. COM'L MIL. COM'L
A, B Address
31
28
29
26
31
28
31
28
28
26{):::::$i:<:::::'Z8:
32
29
ns
D
26
23
23
21
23
21
25
22
22
24
23
ns
Cn
22
20
20
18
19
17
15
2QI\:,@F m::::::::23
l.tr14,:::.::"22(:-:· 20
18
17
ns
10.1.2
13. 4. 5
28
28 .
26
26
28
27
26
25
27
27
25
25
23
24
22
22
21
~~::-f+,t;:;;:28+--=2=-6-+...:2==6-+....:2=-4:""'-'~_I-_-+---.:..n::::.s--l
(~8
22
26
25
23
ns
~~------~~-"":=-~~4-~--~~~~~~~~~~~~444=4-~-4~~~-4---+----~~~
~i~s
AXX.
::
-,,:'I!J$'.J,,~,
:
J
16
14
1.
ns
ns
":':::::'J:"a:::::::~}}/~·-l-_I-_+_+-_--J._-+__.J-_~
1XX, 3XX)
Clock
16
27
25
25
22
26
24
27
.:?$:,,::::J7~:.
23
27
25
27
25
20
18
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK::'(CP INPUT)
CP:
INPUT
'::';:;:':HolbTIME
····::::::{:Xf.::fE'if'H~L
SET-UP TIME
BEFORE H-+L
MIL.
COM'L.
A, B Source Address
10
9
B Destination Address
10
~,: : ,: .~: : :~: t·
D
SET-UP TIME
BEFORE L-+H
MIL.
::: I\::'::'\~W:;)::'::'
1(3)
20, 9
COM'L
+ TPWL(4)
HOLD TIME
AFTER L-+H
MIL
UNIT
COM'L
2
ns
ns
,---D_o_n_o_tcrh_a_ng~:-2~-~-2-(5-)-'-1-0-a-O-(-5)~----+----~-~
2
1
ns
2
b',";:'-)-'
Cn
14
0
0
ns
10.1.2
24
0
O·
ns
24
0
0
ns
0
0
ns
26
13.4.5
16,7,8,9
10
Do not change (2)
12
10
0
0
ns
RAMo, 15. Qo. 15
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable priorto the H -+ L transition to allow time to access the source data before the latches close. The A address may then be
changed, The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L-+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM .It includes all
the time from stable A and B addresses to the clock L -+ H transition, regardless of when the H ~ L transition occurs. TPWLis the minimum clock Low
time.
5. First value is direct path (DATA IN ~ RAM/Q Register), Second value is indirect path (DAT~N -+ ALU -+ RAM/Q Register).
6. Guaranteed by design.
S8-8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
CYCLE TIME AND CLOCK CHARACTERISTICS
IDT49C402A
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
MIL(6)
The tables below specify the guaranteed performance of the
IDT49C402A over the -SSoC to + 12SoCandO°Cto + 70°Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.SV signal level. The inputs switch between OV and 3V with
Signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.
COMBINATIONAL PROPAGATION DELAYS (1)
COM'L
UNIT
Read-Modify-Write Cycle (from
selection of A. B registers to end
of cycle)
28
24
ns
Maximum Clock Frequency to
shift 0 (50% duty cycle.
I = C32 or E32)
35
41
MHz
ns
Minimum Clock LOW Time
13
11
Minimum Clock HIGH Time
13
11
ns
Minimum Clock Period
36
31
ns
CL = SOpF
TO OUTPUT
FROM INPUT
(MSS = H)
(MSS.= L)
G,P
Y
F15
Do
RAMo
RAM 15
F=O
C n +16
OVR
Q15
UNIT
MIL COM'L MIL. COM'L MIL. COM'L. MIL COM'L MIL. COM'L MIL COM'L MIL. COM'L MIL COM'L
A. B Address
41
37
39
35
41
37
41
37
37
34
41
37
40
36
-
D
32
29
29
26
29
26
31
28
27
25
32
29
28
26
-
Cn
28
25
-
-
26
24
25
23
20
18
29
26
23
21
-
ns
ns
ns
1o, 1.2
35
32
30
27
35
32
34
31
29
26
35
32
30
27
13.4.5
35
32
28
26
34
31
34
31
27
25
35
32
28
26
-
16. 7. 6. 9
25
23
-
-
-
-
-
-
-
-
-
-
20
18
20
18
ns
A Bypass
ALU (I = AXX.
1XX.3XX)
30
27
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
34
31
31
28
33
30
34
31
30
27
34
31
34
31
25
23
ns
Clock
J
ns
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUn
~
CP:
~
SET-UP TIME
I
INPUT
A. B Source Address
B Destination Address
I
HOLD TIME
AFTER H~L
BEFOREH~l
MIL
COM'L
11
10
D
11
_(1)
Cn
-
1o. 1.2
13.4.5
-
-
16.7.6.9
11
10
RAMo. 15.00.15
-
-
MIL
2(3)
COM'L
1(3)
SET-UP TIME
BEFORE L~H
MIL
21. 10
COM'L
+
TPWL(4)
Do not change (2)
10
-
-
12/22 (5)
10/20 (5)
HOLD TIME
AFTER L~H
UNIT
MIL
COM'L
2
1
ns
2
1
ns
2
1
ns
17
15
0
0
ns
-
28
25
0
0
ns
-
-
28
25
0
0
ns
0
0
ns
-
-
0
0
ns
-
Do not change (2)
12
11
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
I
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable priorto the H ~ L transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e .• if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
'4. The set-up time prior to the clock L~ H transition is to allow time for data to be accessed. passed through the ALU and returned to theRAM. It includes all
the time from stable A and B addresses to the clock L~ H transition. regardless of when the H ~ L transition occurs.
I
5. First value is direct path (DATAIN ~ RAM/O Register). Second value is indirect path (DAT~N ~ ALU ~ RAM/O Register).
6. Guaranteed by design.
S8-9
.,.,.. ____ ,__.0- ___ .._, ..... ,_ _ _ .____._ _ _ _ ....__ ...
"
...
__._._
....•.
_-_.__._--"-,..-
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BITCMOS MICROPROCESSOR SLICE
CYCLE TIME AND CLOCK CHARACTERISTICS
IDT49C402
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
MILl6)
The tables below specify the guaranteed performance of the
IDT49C402 overthe-SSOC to +12SoCandO°Cto +70°Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.
COM'L
UNIT
Read-Modify-Write Cycle (from
selection of A, B registers to end
..
of cycle)
50
.' 48
Maximum Clock Frequency to
shift 0 (50% duty cycle,
I = C32 or E32)
20
21
MHz
ns
Minimum Clock LOW TIme
30
30
ns
Minimum Clock HIGH TIme
20
20
ns
Minimum Clock Period
50
48
ns
COMBINATIONAL PROPAGATION DELAYS (1) CL = SOpF
TO OUTPUT
FROM INPUT
(MSS = H)
(MSS.= L)
Y
~,P
F15
00
0 15
RAMo
RAM 15
F=O
C n +16
OVR
UNIT
MIL COM'L MIL COM'L MIL COM'L. MIL. COM'L MIL COM'L. MIL COM'L MIL COM'L MIL COM'L
-
ns
-
ns
-
ns
ns
-
-
18
20
18
ns
-
-
-
-
ns
41
37
25
23
ns
A, B Address
52
47
47 .
42
52
47
47
42
38
34
52
47
44
40
D
35
32
34
31
35
32
34
31
27
25
35
32
28
26
Cn
29
26
-
-
29
26
27
25
20
18
29
26
23
21
10,1,2
41
37
30
27
41
37
38
35
29
26
41
37
30.
27
-
13,4,5
40
36
28
26
40
36
37
34
27
25
40
36
28
26
16,7,8,9
26
24
-
-
-
-
-
-
-
-
-
-
20
A Bypass
ALU (I = AXX,
1XX,3XX)
30
27
-
-
-
-
-
-
-
-
-
-
42
38
41
37
42
38
41
37
30
27
42
38
Clock
J
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
~
CP:
'INPUT
SET-UPTIME
BEFORE H-tL
MIL
COM'L
A, B Source Address
20
18
B Destination Address
20
_(1)
18
13,4,5
-
-
16,7,8,9
12
11
RAMo, 15, 00,15
-
-
D
Cn
10,1,2
~
-
HOLD TIME
AFTER H-tL
MIL
2(3)
COM'L
1 (3)
SET-UPTIME
BEFORE L-tH
MIL
50, 20
COM'L
+ TPWL(4)
Do not change (2)
-
-
-
-
-
-
30/40 (5)
26/36(5)
-
UNIT
MIL
COM'L
2
1
ns
2
1
ns
2
1
ns
35
32
0
0
ns
45
41
.0
0
ns
45
41
0
0
ns
0
0
ns
0
0
ns
Do not change (2)
-
HOLD TIME
AFTER L-tH
12
11
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist
2, Certain signals must be stable during the entire clock LOW time to avoid erroneous operation,
3. Source addresses must be stable prior to the H -t Ltransition to allow time to access the source data before the iatches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L-t H transition is to allow time for data to be accessed, passed through the ALU and returned tothe RAM. It includes all
the time from stable A and B addresses to the clock L-t H transition, regardless of when the H -t L transition occurs.
5. First value is direct path (DATAIN -t RAM/O Register). Second value is indirect path (DATAIN -t ALU -t RAM/O Register).
6. Guaranteed by design.
58-10
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C402B
OUTPUT ENABLE/DISABLE TIMES
(e l
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
= SpF, measured to O.SV change of VOUT in nanoseconds)
ENABLE
MIL
COM'L
I
)(Q'EJ:: :\:: :. ::J::::: :J(/ ::/.:::: n::::::: 2& {::::tl::/:::-:U:Ii:f{:: m:::/) Air::{:'"' I): {()i ii:::::}
INPUT
OUTPUT
I
DISABLE
MIL
COM'L
GND to3.0V
WIns
1.5V
1.5V
See Figure 1
IDT49C402A
OUTPUT ENABLE/DISABLE TIMES
(e l = SpF, measured to O.SV change of VOUT in nanoseconds)
ENABLE
INPUT
OUTPUT
OE
Y
DISABLE
MIL.
I
COM'L
MIL
I
COM'L
22
I
20
20
I
18
IDT49C402
OUTPUT ENABLE/DISABLE TIMES
(e l
= SpF, measured to O.SV change of VOUT
INPUT
OUTPUT
OE
Y
TEST LOAD CIRCUIT
in nanoseconds)
ENABLE
DISABLE
MIL.
I
COM'L
MIL.
I
COM'L.
25
I
23
25
I
23
Figure 1. Switching Test Circuit (All Outputs)
INPUT/OUTPUT INTERFACE CIRCUIT
Vee.
ESD
PROTECTION
OUTPUTS
OUTPUTS
Figure 2. Input Structure (All Inputs)
Figure 3. Output Structure
(All Outputs Except F
0)
=
S8-11
_._---_._-_._-------
_._-_ __
..
.
Figure 4. Output Structure
(F = 0)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C402/A/B 16-BIT CMOS MICROPROCESSOR SLICE
CRITICAL SPEt=D PATH ANALYSIS
Critical speed paths are for the IDT49C402A versus the equivalent bipolar circuit implementation using four 2901Cs and one
2902A is shown below.
The IDT49C402A operates faster than the theoretically achievable values of the discrete bipolar Implementation. Actual speed
values for the discrete bipolar circuit will increase due to on-chip!
off-chip circuit board delays.
TIMING COMPARISON: IDT49C402A vs 2901 C w/2902A
16-BIT
JlP SYSTEM
+ 2902A
DATA PATH
(COM'L)
AB ADDR -+ F
=0
DATA PATH
(MIL)
AB ADDR -+ RAMo, 15
AB ADDR -+ F
=0
UNIT
AB ADDR -+ RAMo, 15
<::71
<::71
<::83.5
<::83.5
ns
IDT49C402A
37
36
41
40
ns
Speed Savings
34
35
42.5
43.5
ns
Four 2901 Cs
TIMING COMPARISON: IDT49C402 vs 2901C w/2902A
16-BIT
JlP SYSTEM
Four 2901 Cs
+ 2902A
DATA PATH
(COM'L)
AB ADDR -+ F = 0
DATA PATH
(MIL.)
UNIT
AB ADDR -+ RAMo, 15
ABADDR -+ F=O
AB ADDR -+ RAM o• 15
<::71
<::71
<::83.5
<::83.5
ns
IDT49C402
47
40
52
44
ns
Speed Savings
24
31
31.5
39.5
ns
ORDERING INFORMATION
IDT
XXXXXX
Device Type
x
X
Package
Process/
Temp·y:~NK
SHRINK-DIP Sidebraze
PLCC
Leadless Chip Carrier (50 mil centers)
Leadless Chip Carrier (25 mil centers)
Pin Grid Array
Plastic Pin Grid Array
Ceramic Quad Flatpack (25 mil centers)
XC
J
L
~--------------~
XL
G
PG
QE
BLANK
~--------------------~ A
~------------------------------~
Commercial
(O°C to + 70°C)
Military
(-55°C to + 125°C)
Compliant to MIL-STO-883, Class B
B
Standard Speed
High-Speed
Very High-Speed
49C402
16-Bit Microprocessor Slice
S8-12
t;)
Integrated Device~lnc.
16-BIT CMOS
MICROPROCESSOR
SLICE
lOT 49C403
lOT 49C403A
FEATURES:
DESCRIPTION:
• Monolithic 16-bit CMOS J.lP Slice
• Replaces four 2903As/29203s and a 2902A
The IDT49C403 is a high-speed, fullycascadable 16-bit CMOS
microprocessor slice. It combines the standard function of four
2903s/29203s and one 2902 with additional control features aimed
at enhancing the performance of all bit-slice microprocessor
designs.
Included in this extremely low power, yet fast IDT49C403 device
are 3 bidirectional data buses, 64 word x 16-bit two-port expandable RAM, 4 word x 16-bit Q Register, parity generation, sign extension, multiplication/division and normalization logic. Additionally,
the lOT49C403 offers the special feature of enhanced byte support
through both word/byte control and byte swap control.
The IDT49C403 easily supports fast 100ns microcycles and will
enhance the speed of all existing quad 2903A/29203 systems by
50%. Being specified at an extremely low 250mA, the IDT device offers an immediate system power savings and improved
reliability.
Also featured on the IDT49C403 is an innovative diagnostics
capability known as Serial Protocol Channel (SPC). This on-chip
feature greatly simplifies the task of writing and debugging
microcode, field maintenance debug and test, along with system
testing during manufacturing.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
• Fast
- 50% faster than four 2903As/29203s and a 2902
• Low power CMOS
- Commercial: 250mA (max.)
- Military: 275mA (max.)
• Performs binary and BCD Arithmetic
• Expanded two-address architecture with independent,
simultaneous access to two, expandable 64 x 16 register files
•
•
•
•
•
•
•
•
•
Word/Byte Control
Expanded 4 x 16 Q Register
Performs Byte Swap and Word/Byte Operation
Fully cascadable without the need for additional carry
lookahead
Incorporates three 16-bit Bidirectional Busses
Includes Serial Protocol Channel (SPC TM)
- Flexible on-chip diagnostics
- Serially monitors all pin states
- Reads and Writes to Register File
High Output Drive
- Commercial: 16mA (max.)
- Military: 12mA (max.)
Available in 108-pin PGA
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
A
ADDRESS
ADDRESS
DA
DB
B
-----+----.
010
ALU
STATUS
o
SIO _ _-l---~==:t:=.J
SPC
CONTROL
SLICE
CONTROL
--11222:':2.1--.:
y
CEMOS, SPC and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
050-9012/-1
S8-13
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
DETAILED BLOCK DIAGRAM
A 0-5
6
BO- 5
CP
CP
DEB'
. DA -
o 15
~' _ _ _--I _ _1-,6f-_ _ _- '
16
DB o- 15
10
16
Cn
C n + 16
GIN
SIOo
]5/0VR
SI015 ~----+--------L.
01~5~-------r--------~--------~--------~
0100
0 0- 1
16
Z
(O.D)
SDI
SERIAL.I------<
PROTOCOL
. CHANNEL
YO- 15
SDO
S8-14
DCMP
SCLK
C/O'
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE
PIN CONFIGURATION
M
(@) @ @ @ @ @ @ @ @ @ @ (@)
L
@ @ @ @ @ @ @ @ @ @ @ @
K
@ @ @ @ @ @II@ @ @ @ @ @
J
@ @ @
n
Al
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
82
83
NAME
PIN
NO.
N/C
Vee
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
DEB
DB5
DB3
DBO
GND
la
16
GIN
Yo
Vee
12
11
Cn
r-----J
L _____ ,
I
I
I
I
I
I
.10B-PIN
I
I
P.GA
I
I
I
I
BOTTOM
VIEW
I
I
I
I
I
I
I1. _ _ _ _ _ _ _ _ _ _ _ .JI
@ @ @
@ @ @
H
@ @ @
G
@ @ @
F
@ @ @
E
@ @ @
D
@ @ @
c
@ @ @ @ @ @ @ @ @ @ @ @
B
@ @ @ @ @ @ @ @ @ @ @ @
A
~'(@)'. @ @ @ @ @ @ @ @ @ @ (@)
NAME
DB7
DB4
DBl
MSS
17
Cn + 16
P/OVR
Y1
Y3
DB8
14
GND
10
D86
DB2
@ @ @
@ @ @
@ @ @
@ @ @
.
2
PIN
NO.
II
II
3
4
5
6
7
8
9
10 11
12
PIN
NO.
NAME
PIN
NO.
NAME
PIN
NO.
NAME
PIN
NO.
NAME
PIN
NO.
NAME
PIN
NO.
C7
C8
C9
C10
C11
C12
D1
D2
D3
D10
D11
D12
E1
E2
E3
DCMP
El0
E11
E12
F1
F2
F3
F10
F11
F12
G1
G2
G3
G10
G11
G12
W/S
OEY
SIOo
GND
DB15
DB14
0100
SI015
01015
OEA
DAO
DA1
Yg
Ya
GND
Hl
H2
H3
H10
H11
H12
J1
J2
J3
J10
J11
J12
K1
DA2
DA3
DA5
Y13
Y11
Y10
DA4
DA6
Al
SDI
Y 14
K4
K5
K6
DA8
DA12
WE
Ml0
M11
M12
K7
So
K2
Ao
A3
L7
L8
L9
L10
L1l
L12
M1
M2
M3
M4
M5
M6
M7
M8,
M9
Is
lEN
Y2
Ys
Y6
DB11
DB9
13
Y4
Y7
Z
DB13
D812
D810
K3
Y12
DA7
K8
K9
K10
K11
K12
L1
L2
L3
L4
L5 ..
L6
N/C
B4
WRITE
GND
SDO
Y1S
A2
A4
DA9
DA11
DA14
I:SS
B2
Bs
01
SCLK
ci5
Vee
As
DA10
DA13
DA15
GND
. CP
Bl
B3
S8-15
- - - _.._--_ ..._---_.__.•.-......_._ ... _... -
_._ _----_.
...
__
..
NAME
Q:,
Vee
N/C
MILITARY AND COMMERCIAL TEMPERA.TURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
PIN DESCRIPTION
PIN NAME
DESCRIPTION
I/O
Ao-5
I
Six address inputs to the RAM containing the address of the RAM word appearing at output port A.
BO- 5
I
Six address inputs to the RAM which selects one of the words in the RAM, the contents of which is displayed through
the B port. It also selects the location into which new data can be written when the WE input and CP input are low.
DA o- 15
I/O
Sixteen bi-directional data pins acting as operands R for entering external data into the ALU. OA 0 is the LSB. The OA
lines also function as an external output for RAM port A.
DBo- 15
I/O
Sixteen bi-directional data pins for entering external data into the ALU. The DB lines act as either RAM port B output
data, or as input operands S to the ALU.
WE
I
The RAM write enable input, which when LOW causes the Y I/O port data to be written into the RAM when the CP input
is low. When ~ is HIGH writing data into the RAM is inhibited.
OEA
I
Output enable, which, when HIGH selects 0Ao-15 as the ALU R operand, and, when LOW, selects RAM output A as the
ALU R operand and the OA O- 15 output data.
OEB
I
Output enable, which, when HIGH selects 080-15 as the ALU S operand, and, when LOW, selects RAM output 8 as the
ALU S operand and the OB O- 15 output data.
SIOo
SI015
I/O
Bidirectional serial shift inputs/outputs for the ALU shifter. SICb is an input and SI0 15 is an output during a shift-up operation.
SI015 is an input and SIOo is an output during a shift-down operation. Refer to Tables 4 (a, b, c, d) and 5 for an exact
definition of these pins.
0100
01015
I/O
Bidirectional serial shift inputs/outputs for the Q registers shifter. They operate like SIOo and SI015 pins. Refer to
Tables 4 (a, b, c, d) and 5 for an exact definition of these pins.
Cn
I
Carry-in input to the ALU.
lEN
I
Instruction enable input. When LOW, it enables writing into the ~ister and the Sign Compare flip-flop. When HIGH,
the Q register and the Sign Compare flip-flop are in hold mode. lEN does not affect WRITE, but internally disables the
RAM write enable.
LSS
I
Input Rin, when held LOW, causes the chip to act as either stand alone slice (SA) or the least significant slice (LSS),
When LSS is held HIGH, the chip acts as either an intermediate slice or most significant slice.
MSS
I
Input pin, when held LOW, programs the chip to act as either stand alone slice (SA) or the most significant slice (MSS),
and holding it HIGH programs the chip to act either as an intermediate slice (IS) or the least significant slice (LSS).
WRITE
0
The WRITE signal is LOW when an instruction which causes data to be written into the RAM is being executed. This pin
pin.
is normally connected to the
Cn + 16
0
This output indicates the carry out of the ALU. Refer to Tables 6a and 6b for an exact definition of this pin.
Z
I/O
wr:.
An open drain bidirectional pin. When HIGH it indicates that all outputs are LOW. Z is used as an input pin for some
special functions. Refer to Tables 6a and 6b for an exact definition of this pin.
G/N
0
OEY
I
A control input pin. When LOW the ALU shifter output data is enabled onto the YO- 15 lines. When HIGH the YO- 15
three-state output buffers are disabled.
CP
I
Clock input. The Sign Compare flip-flop and the Q register are clocked on the LOW-to-HIGH transition of the CP Signal.
When WE and CP are LOW, data is written into the RAM.
TJ/OVR
0
P indicates the carry propagate function at the least significant and intermediate slices, and indicates the conventional
two's complement overflow, OVA. signal at the most significant slice. Refer to Tables 6a and 6b for an exact definition
of this pin.
YO- 15
I/O
G indicates the carry generate function at the least significant and intermediate slices, and indicates the sign, N, of the
ALU result at the most significant slice. Refer to Tables 6a and 6b for an exact definition of this pin.
Sixteen bi-directional data pins. Controlled by CJEY input, the ALU shifter output data can be enabled onto these lines, or
external data is written directly into the RAM using these lines as data inputs.
10- 8
I
The nine instruction inputs used to select the IOT49C403 operation to be performed.
0 0- 1
I
Two address pins to select one of the four Q registers.
W/S
I
Word/eyt8 control pin. Used only in the standard function mode, it selects Word mode when held HIGH and Byte mode
when held LOW. Must be tied HiGH when the special functions are being used.
SOl
I
Serial Data Input pin, used for receiving diagnostic data and commands from a host system or from the SOO pin of a
cascaded processor.
SOO
0
Serial Data Output pin, used for transmitting diagnostic data and commands to a host system or a cascaded processor
via its SOl ph
c/O
I
Input pin, when LOW defines the bit pattern being received at the SOl pin as Data, and when HIGH defines the incoming
pattern as a Command for executing diagnostic functions. This pin should be tied HIGH when the diagnostics feature is
not being used.
SCLK
I
Input pin used for clocking in diagnostic data and command information at the SOl pin. This pin should be tied LOW
when the diagnostics function is not being used.
DCMP
0
Output pin, which, when HIGH indicates that the internal comparison between the Y or Q bus data and the data from
the diagnostics data register resulted in a TRUE (they were equal). This feature is used for breakpOint detection. It is an
open-drain pin and can be wire AND with other OCMP pins.
S8-16
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Table 2 IDT49C403 ALU Functions(l)
ALU FUNCTIONS
14
13
12
11
10
DEVICE ARCHITECTURE
The IDT49C403 CMOS microprocessor slice is configured sixteen bits wide and is cascadable to any number of bits (32, 48, 64,
etc.). Key elements which make up this sixteen-bit microprocessor
slice are: (1) the RAM file (a 64 x 16 dual-port RAM) with latches on
both outputs. (2) a high-performance ALU with shifter, (3) a flexible
Q register file (4 x 16 bits) with shifter input, (4) a nine-bit instruction
decoder, and (5) Serial Protocol Channel.
The IDT49C403 incorporates Serial Protocol Channel (SPC TM).
For system testing and debugging purposes SPC is a method by
which data can be entered into and extracted from a device
through a serial data input output, thus providing access to all internal registers.
REGISTER FILE
The Register File is composed of 64 x 16 bit RAM locations. The
RAM data is read from the A-port as controlled by the 6-bit A address field input. Simultaneously, data can be read from the B port
as defined by the 6-bit B address field input. If the same address is
applied at both the A input field and the B input field, identical data
will appear at the two respective output ports. Data is written into
the RAM when WE,IEN and the clock CP are LOW. Both the RAM
output data latches are transparent while CP is HIGH and latch the
data when CP is LOW. The three-state output enable OEB allows
RAM B port data to be read at the DB I/O port, while OEA performs
the same function for the A port data at the DA I/O port.
New data is written into the RAM word defined by the B address
field. External data at the Y I/O port can be written directly into the
RAM, or the ALU shifter output data can be enabled onto the Y I/O
port and written into the RAM.
The ALU can perform seven arithmetic and nine logic operations on the two 16-bit input words Sand R. Multiplexers at the ALU
inpu~ow selection of various pairs of ALU source operands.
The OEA input selects either external DA data or RAM A port output
data as the 16-bit R source operand. The OEB and 10 inputs provide selection of either RAM B port output, external DB data orthe
Q register file output as the 16-bit S source operand. Also, during
certain ALU operations, zeroes are forced at the ALU operand inputs. Thus, the ALU can operate on data from two external sources,
from an external and an internal source," or from two internal
sources. Ta~ shows all possible pairs of source operands as
selected by OEA, OEB, and 10 inputs.
10
OEB
ALU OPERAND R
L
L
Ram Output A
Ram Output B
L
L
H
Ram Output A
DBo-15
ALU OPERAND S
Register
L
H
X
Ram Output A
Q
H
L
L
DAo-15
Ram Output B
H
L
H
DAo-15
DB o- 15
Q Register
H
H
X
DAo-15
NOTE:
1. L = LOW, H = HIGH, X =DON'T CARE
L
L
L
L
L
H
f1
L
L
L
H
X
F=S-R-1+c"
L
L
H
L
X
F = R-S-1+ c"
L
L
H
H
X
F=R+S+C n
L
H
L
L
X
F=S+C n
L
H
L
H
X
F=S+C n
L
H
H
L
L
Reserved Special Functions
L
H
H
L
H
F=R+C n
L
H
H
H
L
Reserved Special Functions
L
H
H
H
H
F=R+C n
= HIGH
H
L
L
L
L
Special Functions
H
L
L
L
H
f1
H
L
L
H
X
FI =R ANDS
H
L
H
L
X
Ii
H
L
H
H
X
FI =R I EXCLUSIVE OR SI
H
H
L
L
X
H
H
L
H
X
f1
f1
H
H
H
L
X
=LOW
= RI EXCLUSIVE NOR SI
=R I AND SI
=R I NORSI
FI =R I NAND SI
The IDT49C403 may be cascaded in either a ripple carry or
carry lookahead fashion. When configured as cascaded ALUs, the
IDT49C403s must be programmed to be a most significant slice
(MSS), an intermediate slice (I~ or a least significant sli~ (LSS) of
the array. The carry generate, G, and carry propagate, P, signals
that are necessary in a cascaded system are available as outputs
on the IDT49C403 least significant and intermediate slices.
The IDT49C403 provides a carry-out Signal C n + 16 which is
available as an output of each slice. The carry-in, C n , and carry-out.
Cn + 16. are both active HIGH. Two other status outputs are generated by the ALU. These are the negative, N. and the overflow, OVR.
The N output indicates positive or negative results, while the OVA
output indicates that the arithmetic operation performed exceeded
!be available two's complement range. Thus the pins G/N and
P/OVR indicate carry generate or propagate on the least significant
and intermediate slice. and sign and overflow on the most significant slice.
Refer to Tables 6a and 6b for an exact definition of these four
signals.
Table 1. ALU Operand Sources(l)
L
L
L
H
H
H
H
X
~ =R I ORS I
NOTE:
1. L=LOW, H=HIGH, i=Oto 15, X=Don'tCare
ALU
OEA
Special Functions
L
L
ALU DESTINATION CONTROL
The following tables show how the shifter at the output of the
ALU should function for non-special instructions. The main addition with respect to the IDT39C203 is the built in byte capability.
The 49C403 has two write enables internally. One for the upper
byte and one for the lower by!e. The enables are controlled by the
instruction decode. external WE and the wis input. For convenience to the user. the unused bits~ the Y bus (MSB ....... 8) are
zero during ~eration. The WE input must be directly connected to the WRITE output. or indirectly through some amount of
gating (Le .• expansion RAM decoding gates).
The ALU performs special functions when instruction bits 13,12,
h, and 10 are LOW. Table 5 defines these special functions and the
operation which the ALU performs for each instruction. When the
ALU executes instructions other than the special functions, the operation is defined by instruction bits 14, 13,12, and 11. Table 2 defines
the operation as a function of these four instruction bits.
S8-17
- - - - - - - - - - - - - - - - _ .. _._._-----_
..........
_._. __.. .
_ _._-_ _-_...
..
..
_ ..
_-----------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
shift operation shifts the data around the most significant (Sign) bit
of the most significant slice and a logical shift operation shifts the
data through the most significant bit. Figure 1 shows these shift
patterns. The SIOo and SI015 are bidirectional serial shift input/output pins. During a shift-up operation, SIOo is generally an input
while SI015 is an output, whereas during a shift-down operation
SIOo is generally an output while SI015 acts as an input. Refer to
Tables 4 (a, b, c, d) and 5 for an exact definition of these pins.
The ALU shifter also provides sign extension and parity generating/checking capabilities. Under instruction control, the SIOo
(Sign) input can be extended through Yo, Yl, Y2, .....YI5and propagated to the SI015 output. A cascadable, five-bit parity generator/
checking generates parity for the Fo, Fl, F2, ..•.• F15 ALU outputs
and SI015 input and, under instruction control, is made available at
the SIOo output.
The sign extend function is an exception to the rule with regard
to the internal byte write enables. When executed, all of the write
In the SA and LSS slices,
enables are active, irrespective of
the contents of bit 7 is replicated on bits 8 to 15 and SI015 in the byte
mode. In the word mode bit 15 is placed on S1015. In this wayan
8-bit word (byte) or a 16-bit word can be extended to the entire
width of the native data path. Extends of larger words than these,
such as 24 and 32 bits, can be achieved by steering the MSS and
LSS inputs of the IS slices to inform which device has the sign bit to
extend. As Sign Extend requires internal gating of the write enables
to the upper and lower portions of RAM, the instruction will not work
with locations in memory expansion RAM.
wis.
ALU SHIFTER
The ALU shifter shifts the ALU output data under instruction
control. It can shift up one bit position (2F), shift down one bit position (F/2), or pass the ALU output non-shifted (F). An arithmetic
r--~+--"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""":. :.~r SIO
)/r
o
o
SIOo
~~~----------------------------~~o
Figure 1. IDT49C403 Arithmetic and Logical Shift Operations
Table 5 defines the special functions and the operation the ALU
shifter performs for each instruction. For instructions other than the
special functions, the ALU shifter operation is determined by instruction bits Ie, 17, Is, and 15. Table 4 (a, b, c, d) defines the ALU
shifter operation as a function of these four bits.
shifts. It can shift-up the data one bit position (20) or down one bit
position (0/2). For a shift-up operation, 0100 acts as an input while
01015 acts as an output; whereas, for a shift-down operation, 0100
is an output and 01015 is an input. By connecting 01015 otthe most
significant slice to SIOo of the least significant slice, double-length
arithmetic and logical shifting is possible with cascaded
IDT49C403s.
The 00 and 01 inputs enable selection of anyone of the four
16-bit register files. Once a specific register has been selected,
access to the other three
registers is disabled and can be
gained only after changing 00 and 01 levels to enable a different a
register.
Table 5 defines the special functions and the operations which
register and shifter perform for selected instruction inputs.
the
While executing instructions other than the special functions, the a
register and shifter operation is controlled by instruction bits Ie, 17, IS/
and 15. Table 4 (a, b, c, d) defines the
register and shifter
operation as a function of these four bits.
WORD/BYTE CONTROL AND BYTE SWAP
In addition to the special ALU functions, the IDT49C403 also
provides ~Word and Byte control and Byte Swap features.
The W/B pin at the Instruction Decoderinput selects ALU operation on either a Word or a Byt~. When W/B is HIGH, the ALU operates on a Word and, when W/B is LOW, the ALU operates on a Byte.
Table 4 (a, b, c, d) showsJhe ALU Destination Controls for Word
and Byte operations for each instruction mode.
The Byte Swap special function allows the positions of the Upper and Lower bytes to be swapped before entering them as the
ALU S operand. The ALU function then adds C n to this swapped
word as its F output. Table 5 shows the instruction set that allows
the ALU to operate the Byte Swap feature.
a
a
a
I
a
INSTRUCTION DECODER
Q REGISTER FILE
The internal control signals necessary for the operation of the
IDT49C403 are generated by the instruction decoder as a function
.QUhe ni.lliLlnstruction inputs, lo-e; the in~ruction enable input,
lEN; the LSS input; the MSS input; the W/B input arid the WRITE
output.
The WRITE output is LOW when an instruction which writes data
into the RAM is executed. Refer to Tables 4 (a, b, c, d) and 5 for
a
The register is a separate 4-word by 16-bit file intended primarily for multiplication and division routines and can also be used
as an accumulator or holding register for other types of applications. The ALU output, F, can be loaded into the register and/or
the register output can be selected as one of the ALU S operands. The shifter at the input to the a register performs only logical
a
a
a
S8-18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
a definition of the WRITE output as a function of the instruction
inputs.
When lEN is HIGH, the Q rEill!§ter and Sign Compare Flip-Flop
contents are preserved. When I EN is LOW, the WRITE output is enabled and the Q register and Sign Compare Flip-Flop can be written according to the IDT49C403 instruction. The Sign Compare
Flip-Flop is an on-chip flip-flop which is used during a divide operation. See Figure 2.
~~
SPECIAL
FUNCTION
AORC
TEN
0
Q
~ ~~~PARE
Figure 2. Sign Compare Flip-Flop
SLICE POSITION PROGRAMMING
The IDT49C403 can be programmed to operate in either a cascaded application or in the standalone mode. Table 3 shows its
four programmed modes.
Table 3. SLICE Programming
SLICE PROGRAM INPUTS
MSS
LSS
MODE OF OPERATION
LOW
LOW
Stand Alone Slice (SA)
LOW
HIGH
Most Significant Slice (MSS)
HIGH
HIGH
Intermediate Slice (IS)
HIGH
LOW
Least Significant Slice (LSS)
ment, non-restoring divide operation. They provide single and
double-precision divide operations and can be performed in "n"
clock cycles (where "n" is the number of bits in the quotient).
The unsigned multiply special function and the two two's complement multiply special functions can be used to multiply two
n-bit, unsigned or two's complement numbers respectively, in 'n'
clock cycles. During the last cycle of the two's complement multiplication, a conditional subtraction rath9r than addition is performed due to the fact that the sign bit of the multiplier carries negative weight.
The sign/magnitude-two's complement special function can
be used to convert number representation systems. A number
expressed in sign/magnitude representation can be converted to
the two's complement representation, and vice-versa, in one clock
cycle.
Incrementing an unsigned or two's complement number by one
or two is easily accomplished using the increment by one or two
special function.
In addition to BCD arithmetic special functions to add or subtract two BCD numbers, a BCD divide by two adjust instruction
can be used to obtain a valid BCD representation after shifting a
number down by one bit.
The BCD/Binary conversion special function instructions permit
single and double-precision algorithms to convert from BCD-taBinary and from Binary-ta-BCD.
The Byte Swap feature allows the swapping of Lower and Upper
bytes of a word before presenting them as the ALU S operand. The
ALU then adds the carry C n to this swapped word to form its F output. This feature functions only for the ALU S operand.
SERIAL DIAGNOSTICS
The Serial Protocol Channel 1M (SPC) is a flexible on-chip feature of the IDT49C403 and is a set of pins by which data can be
entered into and extracted from a device through a serial data input
and output port.
SPC can be used at many points in the Iife of a product for diagnostic purposes such as system level design debug and development; system test during manufacturing and field maintenance debug and test. It allows for observation of critical signals deep within
the system. During system test, when an error is observed, these
signals may be modified in order to zero in on the fault in the system. Serial diagnostics is primarily a scheme utilizing only four
pins to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults.
SPECIAL FUNCTIONS
Seventeen special functions are provided on the IDT49C403
which permit the implementation of the following operations:
• Single and Double Length Normalization
• Two's Complement Division
• Unsigned and Two's Complement Multiplication
• Conversion Between Two's Complement and Sign/Magnitude
Representation
• Incrementation and Decrementation by One or Two
Detailed SPC Architecture of the IDT49C403 BitSlice Microprocessor
The IDT49C403, a quad Am2903/29203 16-bit microprocessor
slice, which includes an ALU and register file, is one of the devices
on which IDT has incorporated the Serial Protocol Channel. The
implementation of SPC on the IDT49C403 is shown in Figure 3.
Only four SPC pins (SDI, SDO, SCLK and C/O) are used to
serially access the I/O pad cells, as well as the internal ALU
registers and buses. To control or monitor a section (such as the
ALU), the appropriate command is loaded into the SPC command
register. The desired function is then executed and the status
information captured in the data register. The status information
can then be serially shifted out and observed to verify proper
system functionality.
• BCD Add, Subtract, and Divide by Two
• Single and Double-precision BCD-to Binary and Binary-to-BCD
Conversion
• Byte Swap
Adjusting a single-precision or double-precision floating-point
number in order to bring its mantissa within a specified range can
be performed using the single-length and double-length normalization operations.
Three special functions can be used to perform a two's comple-
S8-19
[;II
•
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
1/0 PAD CELL
RAM
-D
Q
REG
MUX
C/O'
COMMAND
DATA
SOl
SCLK
SDO
Figure 3. Conceptual Diagram of IDT49C403 Die Incorporating SPC Scan Path
The block diagram in Figure 4 shows the detailed SPC architecture for the IDT49C403. It primarily consists of serial registers for
command. data. addresses and decode/control logic. The SPC
command register consists of a four-bit field (signals 4-7) and four
discrete control lines (signals 3. 2. 1.0). The four-bit field coordinates the transfer of data between RAM and the SPC data register.
as well as controls an on-chip break detect mechanism. The other
discrete signals control the serial scan path through the I/O cells.
The SPC data register is in series with a RAM address register
and I/O pad scan. The SPC data register is connected to the internal bus to gain access to the RAM register file as well as a data
break point feature. The point of connection is the Y bus from the
ALU back into the RAM.
S8-20
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-81T CMOS MICROPROCESSOR SLICE
SDIr>~------------------------~r---S~P;C~C~O~M;'M;'A~N;D~R~E;G:IS~T~ER;---~--------~
SDO
7-4
c/o
BYPASS
SCLK
READ
Figure 4. Internal Organization of the SPC
The multiplexer at the output transmits information via the SDO
pin selecting data from either the SPC data register and the I/O
pads or the command string from the SPC command register.
IDT49C403 SPC Command Opcodes
The SPC command register consists of an 8-bit field, as shown
in Figure 5. Bit 1 enables the READ function of the I/O pad cells. Bit
3 enables the BYPASS function to bypass the I/O pad cells and
scan out only the RAM address and data registers. Bits 0 and 2 are
reserved. Bits 4 through 7 form the opcode field for reading and
writing into the device.
The 4-bit command opcode field gives 16 possible command
opcodes. The first 8 are reserved for writing data from the SPC data
register into the registers and RAM on the device. The second
8 opcodes are reserved for reading data from registers and RAM
into the 16-bit SPC data register.
COMMAND OPCODES
OPCODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FUNCTION
Write RAM
Write a Registers
Write Break Control
Write Break Data
Reserved
Reserved
Reserved
Reserved
L...-_ _ _ _ _ _
RESERVED
READ
' - - - - - - - - - - RESERVED
' - - - - - - - - BYPASS
}
Read RAM
Read a Registers
Read Break Control
Read Break Data
ViewY
Reserved
Reserved
NOP
COMMAND
OPCODES
Figure 5. SPC Command Register and Opcodes for the IDT49C403
S8-21
-------------_.__.-.._----- .. __ .
---_._ .._-._--_ ... _---_.. _..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
The command with opcode 0 causes a write to the internal
device RAM. Opcode 1 is used to write to the Q registers.
Opcodes 2 and 3 are used to write data from SPC data register into
the break data register and break control registers, respectively.
Opcodes 4 through 7 are reserved opcodes.
Opcode 8 is used for reading RAM data into the SPC data register. Opcode 9 is used to read a value out of the Q registers. (Here,
also, the address register supplies the address of the Q register to
be accessed). Opcodes 10 and 11 are used for reading the break
control register and the break data register, respectively.
Opcode 12 is used to strobe data from the Z bus into the 16-bit
diagnostics data register. Opcodes 13 and 14 are reserved opcodes. The last opcode, 15, is a no-operation opcode. This opcode .
can be used to scan the data in and out of the I/O pad cells and use
the device in a pass-through mode (in a cascaded application)
without affecting normal device operation.
All the reserved opcodes, if executed, perform a no-operation;
however, they should not be relied upon to always perform NOPs
as future upgrades may make use of reserved opcodes.
lowered and the SCLK line is raised. This is the strobe which
actually clocks the data into the RAM or register in the device.
Pad Cell Scan Path
Each I/O cell on the IDT49C403 contains a flip-flop which can
be used to store the state of that cell and then be scanned out.
Figure 6 shows the logic configuration. The READ line is enabled
by a bit in the SPC command register and gated by the XFER signal; thus loading the scan flip-flops in parallel. The SCLK is then
used to scan the data out of the SOO pin in series with the address
and SPC data registers.
SDO
INTERNAL
CORE CIRCUITRY
Accessing the Contents of the IDT49C403 Register File
To read data from the device's internal RAM or other logic circuitry into the SPC data register, the address and don't care bits
(for the SPC data register) are shifted in. The command is shifted
into the SPC command register. The command register must be
decoded to determine what data paths are to be steered in order to
get data into the SPC data register. The. read strobe, generated by
the strobe logic, must then strobe this data (in parallel) into the SPC
data register. The data can now be shifted out via the SDO pin and
its contents disassembled and observed.
To perform the write operation, address and data must first be
shifted into the SPC data register. The command is then shifted into
the SPC command register via the command mode. This register
provides information as to what data paths are to be steered. The
address is supplied by the address register in the data scan path.
The write strobe is then generated between the time the C/O line is
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
01015·
SI015
0100
SIOO
OEY
Z
W/B
Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO
fEN
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SCLK
SDI
READ
Figure 6. Serial Scan In the I/O Cell
The BYPASS bit in the SPC command register selects whether
the shifting of the I/O cells will be bypassed such that only the RAM
address and data registers are scanned out. When the READ bit is
HIGH, data is transferred from the pins to the scan register when
SCLK transitions HIGH after C/O has transitioned LOW. The
BYPASS bit in the command register is active HIGH so that a HIGH
level bypasses scanning the I/O cells.
Figure 7 shows the order in which the I/O pad cells are scanned.
The clocking will shift out the data on the Y15 pin first and continue
in series until the WRITE pin is shifted out last.
n-IN
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
CN16
15
16
17.
18
DCMP
MSS
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OEB
CN
10
11
12
13
14
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
OEA
DAO
DA1
DA2
DA3
DA4
DA5
DA6
DA7
AO
A1
A2
A3
A4
A5
DA8
DA9
DA10
DA11
Figure 7. Shift Order of I/O Pad Cells
S8-22
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
DA12
DA13
DA14
DA15
[SS
CP
~
BO
B1
B2
. B3
B4
B5
00
01
wroTE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Y
Q
MUX
TO
DIAGNOSTIC
DATA
~------~------~--------------~
REGISTER
2
Figure 8. Breakpoint Detect Circuitry
Breakpoint Detection on the IDT49C403
latched equal-to, Vee or GND. The latched equal-to input into the
multiplexer gives the user the ability to pipeline the match signal,
thus shortening the system cycle time in the diagnostics mode.
The Vee and GND inputs to the multiplexer allow the programmer
to disable the break compare feature by forcing the DCMP pin
either LOW or HIGH, respectively.
When a match is made, the DCMP line goes HIGH. Thus, if any
one slice in a cascade application does not matCh, the wire-ANDed
DCMP will be low. Selecting Vee via the multiplexer will disable
matches altogether. To select GND, disable anyone slice from the
comparison.
Figure 9 shows the format of the break data and break control
register. The break data pattern is 16 bits wide, with bit 16 being the
most significant bit and last to be shifted in. The Break Control register contains three fields. Bits 0 and 1 control th~ DCMP output and
bit 2 selects between the Y and the Q bus to be compared with the
break data register. Bits 3 to 15 are reserved for future expansion.
Figure 8 shows the diagnostics breakpoint detection circuit on
the IDT49C403. This circuit is designed to allow the user to monitor
certain key data buses and detect the data patterns on the Y and Q
buses. When a data pattern is detected, a breakpoint compare signal is generated on the DCMP pin and is used to halt the system
operation. The DCMP is an open drain signal and should be wireORed with DCMP lines of other similar devices and monitored by
the main sequencer in the system. The breakpoint detection
mechanism thus allows for an easier debug of microcode with regard to the data path.
At the heart of the breakpoint detection circuit is a comparator
which compares data from the break data register with data from
either the Y bus orthe Q bus. The break control register determines
which of the two buses is selected for a comparison. The break
control register also steers a multiplexer at the output of the
comparator. This multiplexer selects between the equal-to signal,
BREAK DATA
REGISTER FORMAT
15
I
BREAK CONTROL
REGISTER FORMAT
0
BREAK DATA PATIERN
15
I
3
2
BUS
SEL
1
BREAK POINT CONTROL ACCESS
BUS SEL
BUS
0
Y
1
Q
DCMP CONTROL
0
0
1
1
0
1
0
1
DCMP STATUS
LOW
PIPELINED
NON-PIPELINED
HIGH
Figure 9. Breakpoint Control Registers and Opcodes
S8-23
0
DCMP
CONTROL
I
IDT49C403/A 16-81T CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The SPC version allows data to be transferred into and out of a
device and can also accommodate addresses and commands usIng the same number of pins. This is accomplished with a reconfiguration of the function of the diagnostic pins and internal logic.
With this vastly expanded capability, SPC can conveniently be
used in RAMs, peripherals an complex logic functions. These new
capabilities allow the user to monitor and modify all of the storage
elements and pins ofa device. With a simple hardware interface
and appropriate software, any type personal or mini computer
can be turned Into a development system for lOT parts with serial
diagnostics.
Figure 10 shows the Serial Protocol Channel being used with a
writable control store in a microprogrammed design. The control
store can be initialized through the SPC path. A register with SPC is
used for the instruction register gOing into the IOT49C410 (16-bit
microprogram sequencer) as well as data registers around the
IOT49C403. In this way, the designer may use the Serial Protocol
Channel to observe ard modify the microcode coming out of the
writable control store, as well as observing and being able to modify data and instructions in the overall machine.
The block diagram of the diagnostics ring shows how the devices with diagnostics are hooked together In a serial ring via the
SOl and SOO signals. The diagnostiCS signals may be generated
through registers which are hooked up to a microprocessor. This
microprocessor could conceivably be an IBM PC.
--------------,
WCS
IDT7198
(16Kx4)
,
1_ _ _ _ _ _ - -
Figure 10. Typical Microprogram Application with SPC
S8-24.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Table 4a ALU Destination Control (Word Mode) for
18 17 16 15
10,
111 12 or 13
= HIGH, lEN = LOW
a
SIO ,s
ALU SHIFTER
FUNCTION
HEX
MSS
SA
L
L
L
L
Arith. F/2 --+ Y
0
L
L
L
H
Log. F/2--+ Y
1
L
L
H L
Arith. F/2 --+ Y
2
L
L
H H
Log. F/2--+ Y
3
L
H L
L
F--+ Y
4
L
H L H
F--+ Y
5
L
H H L
F--+ Y
6
L
H H H
F--+ Y
7
SIOo
LSS
IS
~
Input
WRITE
REGISTER
AND SHIFTER
FUNCTION
010
010 0
'5
Fo
L
Hold
Z
Z
I
I
L
Hold
Z
Z
L
Log. 0/2 --+ 0
Input
L
Log. 0/2 --+ 0
Input
00
00
Parity
L
Hold
Z
Z
H
Log. 0/2 --+ 0
Input
00
H
F--+Q
Z
Z
L
F--+ Q
Z
Z
L
Hold
Z
Z
Z
H L
L
L
Arith. 2F --+ Y
8
~4
~4
H L
L
H
Log. 2F--+ Y
9
~5
~5
L
Hold
Z
H L
H L
Arith. 2F --+ Y
A
F,4
F,4
L
Log. 20 --+0
0 ,5
Input
H L
H H
Log. 2F--+ Y
B
~5
~5
L
Log. 20--+0
0 15
Input
H H L
L
F--+ Y
C
H H L
H
F--+ Y
0
H H H L
H H H H
Sign Extend
1
F
18 17 16 15
L L L L Arith. F/2--+Y
MSS
IS
Z
0 '5
Input
Z
Z
Z
Z
L
Hold
1'15
L
Hold
= HIGH , lEN = LOW
HEX
SA
Z
Log. 20--+0
SiCa
SIOo
LSS
SA
•
Fo
Input
Hold
H
F15
SIO,S
0
H
SiCa
Table 4b ALU Destination Control (Byte Mode) for 10, 1, , 12 or 13
ALU
SHIFTER
FUNCTION
Input
!
E
F--+ Y
F
'5
F'5
MSS
IS
SIO'5 SIO'5
1
a
010,5
REGISTER
0100
I
WRITE AND SHIFTE
\ FUNCTION MSS/ISI SAlLssl MSS/IS ISA/LSS
LSS
Hold
~
Z
Fo
L
I
I
L
Hold
L
Log. 0/2--+0
Input ~
L
Log. 0/2--+0
Input -
L
Hold
Z
H
Log. 0/2--+0
Input
H
F--+O
Z
L
F--+O
L
Hold
Z
L L L H Log. F/2--+Y
1
L L H L Arith. F/2--+Y
2
L L H H Log. F/2--+Y
3
L H L L
F--+Y
4
L H L H
F--+Y
5
L H H L
F--+Y
6
L H H H
F--+Y
7
H L L L Arith. 2F--+Y
8
F6
H L L H Log. 2F--+Y
9
F,
~
L
Hold
H L' H L Arith. 2F--+Y
A
F6
F6
L
Log. 20--+0
0100
H L H H Log. 2F--+Y
B
F7
F7
L
Log. 20--+0
0100
H H L L
F--+Y
C
H
Hold
Z
H H L H
F--+Y
0
H
Log. 20--+0
0100
H H H L Sign Extend
E
L
Hold
Z
•
HH.HH
F
L
Hold
Z
~
F--+Y
Parity
1
SIOo
SICb
.-fL
-
Parity
I
Input
~
1
Parity = F'5 If/' 1i4 ...... If/' F3 If/' F2 If/' F1 If/' Fo If/' SIO'5
If/' = Exclusive OR
~
I 010 15 I
I 01015 I
00
00
~
I
~ 010,5
I
00
~
I
I
07
07
I
I
Input-
I
07
I
Input-
Input~
L = LOW
H = HIGH
Z = High Impedance
SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice
S8-25
- - - - - _.. _---_.
__. _ - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
= HIGH, lEN = LOW
Table 4c. ALU Destination Control for 10. 11, 120r 13
SI01S
'a '7 '6 '5
ALUSHIFTER
FUNCTION
SA
HEX
Y1S
MSS
IS
LSS
Y14
MSS
SA
IS
LSS
SA
MSS
IS
LSS
Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word
•
Input
L L
L L
Arlth.
F/2-+Y
0
L L
L
Log.
F/2-+Y
1
L L
H L
Arlth.
F/2-+Y
2
L L
H H
Log.
F/2-+Y
L H
L L
F-+Y
L H
L H
F-+Y
5
L H
H L
F-+Y
a
L H
H H
F-+Y
7
H L
L L
Arlth.
2F-+Y
a
Fa
F14
H L
L H
Log.
2F-+Y
9
F7
F15
H L
H L
Arlth.
2F-+Y
A
Fa
F14
H L
H H
Log.
2F-+Y
B
F7
F
H H
L L
F-+Y
C
H H
L H
F-+Y
'0
H
H H
H L
H H
H H
Sign Extend
F-+Y
~
0
0
~
~
~
~
~
3
~
~
4
F15
F15
E
F
SIOO
~
~
~
I
j j
~
F 15
F 15_
Table 4c. ALU Destination Control for 10.
~,
12 or 13
F7
j
ALU SHIFTER
FUNCTION
HEX
SA
F15
~
0
~
~
~
.!..!§..
F14
F15
0
~
~
F14
I'r
F14
F14
~
~
~
~
~
-'-
F15
~
~
F15
F15
j
f--
r£L.
0
SIOo SIOO SIOo SIOO
0
0
F15
F15
F 3
'l'
i---
F15
F7
0
t-"-
~
F14
!!
1
~
F14
F14
F14
SIOO SIOO SIOO SIOO F7
r£l.
0
0
0
F14
F14
0
!
= HIGH, lEN = LOW (cont'd.)
Ya
IS
MSS
~
SI015 0
11
r£.!!.
Y13-9
'a '7 '6 '5
0
F 4
~
~
SlOt 5
111 1[ 1 II [~ 1
F15
r-£L
J
15
~
SIOO
0
LSS
SA
Y7
MSS
IS
LSS
SA
MSS
IS
LSS
Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word
L L
L L
Arlth. F/2-+Y
0
L L
L H
Log.
F/2-+Y
1
L L
H L
Amh. F/2-+Y
2
L L
H H
Log.
F/2-+Y
3
L H
L L
F-+Y
4
L H
L H
F-+Y
5
L H
H L
F-+Y
a
L H
H H
F-+Y
7
H L
L
H L
L H
Log.
H L
Arlth. 2F-+Y
e
2F-+Y
9
H L
Arlth. 2F-+Y
A
Log.
L
H L
H H
2F-+Y
B
H H
L
L
F-+Y
C
H H
L
H
F-+Y
0
H H
H L
H H
H H
Sign Extend
F-+Y
0
Fl+l
a
F'+l
0
F'+l
o
F'+l
0
Fg
0
Fg
0
Fg
0
Fg
...!i.
Fa
0
Fa
0
F7
--'-
1111111
1 r j'
1 1 1 1 1 1 1 II11 1 111
1 1 1 1 II II ~ i 'j 1 ! r
j j
SI015
~
~
~
-
SI015
F,
F,
F,
F,
Fa
Fe
Fe
F'_l
F,-l
F,-l
F,-l
F7
F7
F7
Fe
F7
SI015
F7
F7
F7
F7
F7
:-'Fa
F6
..!§...
..£.§...
~
,..:z..
F6
r-5F,
F,
E
F7
F
0
j
r.!L
F,
SIOo SIOo SIOO SIOo
o·
F,
F,
0
F,
r-2
Fe
Fe
j j
fo--
F7
0
~
0
S8-26
~
Fe
SIOO SIOO SIOo SIOo
a
Fa
Fe
0
Fe
F7
0
F7
Fa
r-2F7
F7
jjj
r-2F7
SIOo SIOo SIOo SIOo
0
F7
0
F7
F7
F7
jj
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Table 4c. ALU Destination Control (cont'd.) for 10. ~, 12 0r
= HIGH, lEN = LOW
13
VS_1
Vs
18 17 16 15
ALU SHIFTER
FUNCTION
SA
HEX
IS
MSS
SA
LSS
Vo
MSS
LSS
IS
SA
IS
MSS
LSS
Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word
L L
L
L
Arlth.
F/2-+V
0
L L
L
H
Log.
F/2-+Y
1
L L
H L
Arlth.
F/2-+Y
2
51015
L L
H H
Log.
F/2-+V
3
F7
J
Fe
Fe
F5
F5
L H L
L
F-+Y
4
L H
H
F-+V
5
L H H L
F-+V
e
L H H H
F-+Y
7
H L
L
L L
Arlth.
2F-+Y
8
H L
L
Log.
2F-+Y
9
H L
H L
Arlth.
2F-+Y
A
H L
H H
Log.
2F-+Y
H
SlOt5 F7
B
J J
F-+Y
C
Fe
H H L
H
F-+Y
0
H H
Sign Extend
F-+Y
510 15 F7
F7
1
0
FI+1 FI+1
0
FI+1
FI+1 Fi+1 Fi+1
1
F7
51015
F7
J J J
Fe
Fe
Fe
Fe
FI
FI
F5
F5
F5
F5
FI_1
FI_1
J
F1
0
F1
F1
0
F1
F1
F1
J J J J J
FI
FI
I--'--
L
H H
o
F7
1 JJJ
! j 1 ! ! ! ! j ! ! ! j ! j 1 !!!
H H L
H H H L
0
F7
E
F
1
~
F6
J J
Fe
Fe
FI
0
F6
F6
J J
FI
0
FO
FO
J J J J J
----'-
FI
FI
Fo
FI
a
Table 4c. ALU Destination Control (cont'd.) for 10,1 1, 12 0r
13
= HIGH , lEN = LOW
SIO o
18 17 16 15
ALU SHIFTER
FUNCTION
HEX
L L L L
Arith.
F/2-+Y
0
L L L H
Log.
F/2-+Y
1
L L H L
Arith.
F/2-+Y
2
F/2-+Y
3
L H L L
F-+Y
4
LH L H
F-+Y
5
L L H H Log.
L H H L
F-+Y
6
L H H H
F-+Y
7
H L L L
Arith.
2F-+Y
8
H L L H Log.
2F-+Y
9
H L H L
2F-+Y
A
Arith.
H L H H Log.
HH L L
2F-+Y
8
F-+Y
C
D
H H L H
F-+Y
HH H L
Sign Extend
E
H H H H
F-+Y
F
SA
MSS
LSS
Word
Byte
Word
Byte
Word
Byte
Word
Fa
Fo
SI0 15
Fo
SI0 15
Fo
Fa
Fa
Parity
Parity
Parity
Parity
Parity
1---'---
Parity
..
Input
S8-27
----------------------------------
IS
Byte
FO
J J J
~
~
FO
FO
Fo
FO
51 00 SIOO SIOO
51°0 SIOo 5 100 5100
SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice
= 1 to 6 (for F 5-1)
i = 9 to 14 (for F13-~
I
FO
J
FO
jjjj
FI
FI
Fo
5100
510 0 SIOO 510 0 510 0
0
FI
FI_1 F I_1 FI-1 510 0 SIOo
~
l
FI
!j
F6
SIOO SIOO 5100 510 0
0
1
J J J J J
~
Fe
FI-1
FI
a
Fo
FO
FO
jj
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Table 4d. ALU Destination Control for 10, 1 12 or 13
"
010
0,5
15
o REGISTER
18 17 16 Is
= HIGH, lEN = LOW
~ND SHIFTER HEX
FUNCTION
I
MSS/IS
SA/LSS
Byte 1Word 1 Byte 1 Word
..
L L L L Hold
0
Z
L L L H Hold
1
Z·
L L H L Log. 0/2-+0
2
Input
..
.
L L H H Log. 0/2-+0
3
Input
..
L H L L Hold
4
Z
L H L H Log. 0/2-+0
5
Input
L H H L F-+O
6
Z
L H H H F-+O
7
H L L L Hold
8
H L L H Hold
9
H L H L Log. 20-+0
A
I
H L H H Log. 20-+0
B
HH L L Hold
C
H H L H Log. 20-+0
D
HH H L Hold
E
Z
H H H H Hold
F
Z
MSS/IS
Byte Word
Byte Word
Byte Word
...
Hold
..
..
Table 4d. ALU Destination Control for 10' 111 12 or 13
o REGISTER
FUNCTION
MSS/IS
I
~
I---
I--
Hold
rbHold
I--
~
~
~
~
~
~
~
~
~
I--
I---
I---
Hold
I Hold
Hold
I--
Hold
I--
Hold
I---
Hold
I--
~
I--
I--
~
~
Hold
Hold
I---
~
~
~
I--
I--
I---
Hold
Hold
Hold
Hold
Hold
~
~
r--
Hold
~
~
Hold
09
09
~
~
~
~
~
~
I---
I--
Hold
f--
~
Hold
07
07
I---
t-
~
Hold
I--
r------
Hold
I-Hold
r------
~
Hold
Hold
~
~
~
Hold
~
Hold
Hold
Hold
~
= HIGH, lEN = LOW (cont'd.)
07
18 17 16 15 P.ND SHIFTER HEX
r------
I--
Hold
..
Hold
I--
I--
~
~
..
Hold
~
~
~
Hold
Byte Word
~
~
Hold
SA/LSS
Byte Word
.....--09
r------
~
~
Hold
MSS/IS
~
..--
101015
Hold
0100 1 0 15 1 0 7 10 ,5
..
Hold
..--
~
..
Z
Word
101015
Hold
0100 1 0 15 1 0 7 1 0 15
0 15
0100 1 0 15 1 0 7
Byte
..--
Hold
..
T
SA/LSS
SA/LSS
..
08
0 ,4-9
MSS/IS
MSS/IS
Byte Word 1 Byte 1 Word
..
I
SA/LSS
MSS/IS
1
Byte Word 1 Byte Word
..
1
L L H L Log. 0/2-+0
2
L L H H Log. 0/2-+0
3
L H L L Hold
4
L H L H Log. 0/2-+0
5
0 8 10 10 15 1 0 8
L H H L F-+O
6
F7
0'+1
F,
L H H H F-+O
7
F7
F,
...
Fo
..
Hold
0 8 1010 151 0 8
0 8 1010151 0 8
Hold
0'+1
..
0'+1
Hold
H L L L Hold
8
Hold
Hold
H L L H Hold
9
Hold
Hold
H L H L Log. 20-+0
A
06
0,-1
H L H H Log. 20-+0
B
06
0,-1
HH L L Hold
C
Hold
Hold
H H L H Log. 20-+0
D
06
0,-1
H H H L Hold
E
Hold
Hold
H H H H Hold
F
Hold
Hold
Parity = F15 'V' F14 ...... 'V' F3 'V' F2 'V' F1 'V' Fo 'V' SIO 15
'V' = Exclusive OR
01
..
Hold
...
0 1
Fo
..
..
..
..
..
..
..
..
I
Byte Word
Z
Z
..
..
MSS/IS
..
Hold
0
L L L H Hold
Hold
T SA/LSS
Byte Word 1 Byte 1Word
L L L L Hold
Hold
010 0
00
0 6- 1
SA/LSS
01
Hold
010 0
010 0
Hold
010 0
Hold
Hold
.. 010 151 00
.. 010151 0 0
.
Z
.. 010 15 1 0 0
..
..
..
..
..
..
.
..
..
..
58-28
SA/LSS
I Byte IWord
..
..
..
..
..
.
Z
..
I
...
Input
Input
Z
Input
..
.
...
Z
....
Z
...
Z = High Impedance
SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice
I = 1 to 6 (for 0 6- 1)
I = 9 to 14 (for 0 14-9)
I
M'ILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
Table 5. Special Functions (7)
HEX
14
HEX
13 12 I, 10
0
L
0
1
L
0
18 17 16 15
1
H
0
2
L
0
3
L
0
SPECIAL
FUNCTION
Unsigned Multiply
o REGISTER
S10'5
ALU SHIFTER
SIOO & SHIFTER 010'5 0100 WRITE
FUNCTION MSS OTHER
FUNCTION
SLICES
F=S+C n ifZ=L
Log F/2-+Y
HZ
Input
Log 0/2-+0 Input 0 0
L
Fo
(1)
F=R+S+C n if Z=H
ALU
FUNCTION
BCD-to-Binary
(4)
Conversion
Multiprecision
(4)
BCD-to-Binary
Two's Complement F=S+C n if Z=L
Multiply
F=R+S+C n if Z=H
Decrement by
F=S-2+C
n
One or Two
Log F/2-+Y
Input
Input
Fo
Fo
Log 0/2-+0 Input 0 0
Hold
HZ
L
Log F/2-+Y
Input
Input
Log F/2-+Y
(2)
HZ
Input
00
L
Log 0/2-+0 Input 0 0
Fo
L
F-+Y
Input
Input
Parity
Hold
HZ
HZ
L
4
L
0
Increment by
One or Two
F=S+1 +Cn
F-+Y
Input
Input
Parity
Hold
HZ
HZ
L
4
H
0
Byte Swap + C n
F= (SLB, SUB)+Cn
F-+Y
Input
Input
Parity
Hold
HZ
HZ
L
0
F=S+C n ifZ=L
F/2 -+Y
(3)
F="S+C n if Z=H
Log F/2-+Y
F=S+C n if Z=L
(2)
F=S-R-1+C n if Z=H
Input
Input
Parity
Hold
HZ
HZ
L
6
L
0
Sign/Magnitude
Two's Complement
Two's Complement
Multiply, Last Cycle
7
L
0
BCD Divide by Two
8
L
0
Single Length
Normalize
Binary-to-BCD
Conversion
Multiprecision
Binary-to-BCD
5
L
9
L
0
9
H
0
HZ
Input
Fo
F-+Y
Input
Input
Parity
Hold
F-+Y
F'5
F'5
HZ
Log 20-tO
0 15 Input
L
(5)
Log 2F-+Y
F15
F15
Input
Log 20-tO
0 15 Input
L
(5)
Log 2F-+Y
F15
F15
Input
Hold
HZ
Input
L
Log 2F-+Y
R15 V
F'5
F15
Input
Log 20-+0
0 15 Input
L
F-+Y
0
0
HZ
Hold
HZ
L
F'5
Input
Log 20-+0
(4)
F=S+C n
Double Length
Normalize and
First Divide Op
F=S+C n
F=R+S+CnBCD (6)
Log 0/2-+0 Input 0 0
A
L
0
B
L
0
BCD Add
0
Two's Complement F=S+R+C n ifZ=L
Divide
F=S-R-1+C n ifZ=H
Log 2F-+Y
R15
VF
0
BCD Subtract
F=R-S-1 +CnBCD (6)
F-+Y
0
0
HZ
Hold
F-+Y
F15
F'5
HZ
Log 20-tO
F=S-R-1 +CnBCD (6)
F-+Y
0
0
HZ
Hold
C
D
L
L
E
L
0
Two's Complement
F=S+R+C n ifZ=L
Divide Correction
F=S-R-1 +C n if Z=H
and Remainder
F
L
0
BCD Subtract
HZ
HZ
HZ
0 15 Input
HZ
HZ
0 15 Input
HZ
HZ
L
L
L
L
L
L
NOTES:
1. At the most significant slice only, the C n+ 16 signal is internally gated to the Y output.
2. At the most significant slice only, F'5 'V' OVR is internally gated to the Y output.
3. At the most significant slice only, S'5 'V' F15 is generated at the Youtput.
4. On each nibble, F = S if magnitude of S is less than 8, and F = S minus three if magnitude of S is 8 or greater.
5. On each nibble, F = S if magnitude of S is less than 5, and F = S plus three if magnitude of S is 5 or greater. Addition is modulo 16.
6. Additions and Subtractions are BCD adds and subtracts. Results are undefined if R or S are not in valid BCD format.
7. The 0 register cannot be used explicitly as an operand for any Special Functions, It is defined implicitly within the functions.
8. BCD Nibble propagate: PNI = (1541 + 0 + P41+3) (P41 +0 + ~I+~ (P41 + 0 + (341+1 + P41+2)
BCD Slice propage:
P = PN 3 PN 2 PN 1 PN o
9. BCD Nibble generate: 00 1 = (341+3((341+0 + (341+' + P41 + 2) ((341+0 + (341+1) (P41 + 1 + G.:1+2l (~1+3 + ~I+' .1541 +2 , ~,+ol
BCD Slice generate:
G = GN3 V GN 2 PN 3 V GN, PN 2 PN3 V GN 0 PN, PN2 PN 3
L = LOW
LB = Lower Byte
H = HIGH
UB = Upper Byte
HZ = High Impedance
'V' = Exclusive OR
Parity = SI015 'V' F15 'V' F14 'V' F13 'V' ...... 'V' Fo
S8-29
----.
--------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE
Table 6a. IDT49C403 Status Outputs (Word Mode)
HEX
HEX
18 17 16 15 14 13 12 11
X
10
GI
PI
(1=0 to 15) (1=0 to 15)
P/OVR
C n +1S
MSS/SA
= L)
OTHER
SLICES
MSS
ISS
LSS
SA
fM
fM
fM
0
F15
G
f (Y)
C n+15 'V' C n+16
P
F15
G
fM
f (y)
f (Y)
fM
C n+15 'V' C n+16
P
F15
G
f(Y)
f (Y)
fM
fM
GVPC n
C n+ 15 'V' C n+ 16
P
F15
G
feY)
f (Y)
fM
fM
GVPC n
C n+ 15 'V' C n+ 16
P
F15
G
f(Y)
fM
fM
fM
GV PCn
C n+15 'V' C n+16
P
F15
G
f(Y)
f (Y)
fM
fM
GVPC n
C n+15 'V' C n+16
P
F15
G
fM
f (Y)
fM
fM
RI
GVPC n
C n+15 'V' C n+16
P
F15
G
fM
f (Y)
fM
fM
0
1
0
0
0
F15
G
fM
f (Y)
fM
f (Y)
RI A SI
1
0
0
0
F15
G
fey)
f (Y)
f (Y)
f(Y)
RI A SI
RIVSI
0
0
0
F15
G
fM
f (Y)
fM
fM
1
0
H
0
0
X
1
X
RIASI
RIVSI
GVPC n
X
2
X
RI A SI
RIVSI
GVPC n
X
3
X
RI ASI
RIVSI
X
4
X
0
SI
X
5
X
0
SI
X
6
X
0
RI
X
7
X
0
X
X
X
8
H
9
X
X
0
Z (OEY
GIN
OTHER
SLICES MSS/SA
X
A
B
X
RI A SI
RIVSI
0
0
0
F15
G
fM
f (Y)
fM
fM
X
C
X
RI A SI
1
0
0
0
F15
G
fM
f (Y)
f (Y)
f (Y)
X
D
X
RI A SI
1
0
0
0
F15
G
feY)
f (Y)
fM
fM
X
E
X
RI A SI
1
0
0
0
F15
G
f(Y)
f(Y)
fM
fM
X
F
X
RI A SI
1
0
0
0
F15
G
feY)
f(Y)
f (Y)
f (Y)
0
L
OlfZ=L
RI A SI
IfZ=H
Silf Z=L
RIVSI
IfZ=H
GVPC n
C n+15 'V' C n+16
p
F15
G
Input
Input
00
00
1
0
L
0
SI
GVPC n
C n+ 15 'V' C n+ 16
P
F15
G
f(Y)
f(Y)
f (Y)
f (Y)
1
8
L
0
SI
0
0
0
F15
G
feY)
feY)
fM
fM
2
0
L
OlfZ=L
RI A SI
ifZ=H
Silt Z= L
RIVSI
ifZ=H
GV PCn
C n+ 15 'V' C n+ 16
p
F15
G
Input
Input
00
00
3
0
L
(6)
(7)
GVPC n
C n+ 15 'V' C n+ 16
P
F15
G
f(Y)
f(Y)
f (Y)
f (Y)
4
0
L
(1)
(2)
GV PCn
C n+ 15 'V' C n+ 16
P
F15
G
fM
t (Y)
tM
f (Y)
4
8
L
(1)
(2)
GVPC n
C n+ 15 'V' C n+ 16
P
F15
G
feY)
t(Y)
f(Y)
feY)
0
SlifZ=L
Silt Z=H
GVPCn
Cn+15 'V' Cn+16
j5
F,5 ifZ =L
F15'V'S15
ItZ=H
G
S15
Silf Z=L
RIVSI
ItZ=H
GVPC n
C n+15 'V' C n+16
j5
F15
G
Input
0
5
0
L
6
0
L
RI A SI
IfZ=H
7
0
L
0
SI
GV PCn
C n+ 15 'V' C n+ 16
P
F15
G
feY)
f (Y)
f (Y)
f(Y)
8
0
L
0
SI
(4)
02 'V' 0 1
P
0 15
G
t(O)
t(O)
t(O)
f (a)
C n+15 'V' C n+16
o IfZ=L
Input Input
S15
Input
00
00
9
0
L
0
SI
GVPC n
j5
F15
G
f (a)
f(0)
f(O)
f(O)
9
8
L
0
SI
0
0
0
F15
G
f (a)
f(O)
t(O)
f (a)
A
B
0
L
0
SI
(3)
F2 'V' F1
P
F15
G
(5)
(5)
(5)
(5)
0
L
Ri A SI
RIVSI
GV PCn
(8)
(8)
F15
(9)
feY)
f(Y)
f (Y)
f(Y)
C
0
L
RI A Si
IfZ=L
RI A SI
IfZ=H
RIVSI
IfZ=L
RIVSI
IfZ=H
GVPC n
Cn+ 15 'V' Cn+ 16
P
F15
G
D
0
L
RI A Si
RIVSi
GV PCn
C n+15 'V' Cn+16
(8)
F15
(9)
RIVSI
IfZ=L
RIVSI
IfZ=H
GV PCn
Cn+ 15 'V' Cn+ 16
p
F15
G
RIVSI
GVPC n
C n+ 15 'V' C n+ 16
(8)
F15
(9)
E
0
L
RIA SI
IfZ=L
Ri A SI
IfZ=H
F
0
L
AI
A SI
Sign
Sign
Compare
Compare
Input
Input
FF
FF
Output
Output
feY)
f(Y)
f(Y)
f (Y)
Sign
Sign
Compare
Compare
Input Input
FF
FF
Output
Output
fey)
f (Y)
f(Y)
f (Y)
Continued next page
S8-30
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-81T CMOS MICROPROCESSOR SLICE
NOTES:
1. If LSS is LOW. Go = So and G1.2.3....• 15 = O.lf LSS is HIGH. GO.1.2.3....• 15 = 0
2. If LSS is LOW. Po = 1 and Pl. 2. 3....• 15 = Sl. 2. 3....• 15. If LSS is HIGH. PI = SI
3. At the most significant slice. C n+ 16 = 0 15"iJ' 014. At other slices C n+ 16 = G V PCn
4. At the most significant slice. C n + 16 = F15"iJ' F14. At other slices Cn+ 16 = G V PCn
5. Z = 0 0 0 102 0 3 ... 015Fo Fl F2 F3 ... F 15
V = OR
A = AND
"iJ' = Exclusive-OR
P = P15P14 ...... P3P2Pl Po
G = G 15 V G 14P15 V G 13P14 'i5 V G 12P13 P14 ~5
6.
7.
8.
If LSS is LOW. Go = 0 and G l . 2. 3..... 15 = Sl. 2.3..... 15· If LSS is HIGH. Go. 1. 2. 3.· . ·.15 = So. 1.2.3.· ..• 15
If LSS is LOW. Po = So and Pl. 2.3.. ··• 15 = 1. If LSS is HIGH. po. 1. 2. 3.. · .• 15 = 1
V GllP12P13P14'i5 V ...... V G 1P2 P3 P4 ... P15
BCD Nibble propagate: J5N 1 = (1541 + 0 + 1541 + 3) (P41+0 + ~I+~ (1541 + 0 + G 41 + 1 + ~1+2)
BCD Slice propagate:
P = PN 3 PN2 PNl PNo
9
BCD Nibble generate·
BCD Slice generate:
GN I = G41+3(G41+0 + <341 + 1 + 1541 + 2 ) (<341 + 0 + G 41 + 1) (P41 + 1
G = GN3 V GN2 PN3 V GN 1 PN2 PN3 V GN o PN 1 PN2 PN 3
+ ~I+:J
(P.t1+3
+ ~I+l
• P41 + 2 • ~I+ol
f M = Yo Yl Y2 '13 ...... '1,5
f (0) = 0 0 0 1 0 2 03 •••. •• 0 15
=
L = LOW
0
H = HIGH = 1
Table 6b. IDT49C403
Status Outputs (8yte Mode)
HEX
Is 17 16 15
HEX
14 13 12 11
I
X
0
H
01
GIN
P/OVR
(I=Oto7)
PI
(I=Oto7)
C n+7
0
1
0
0
MSS/SA
OTHER
SLICES MSS/SA
0
Z(OEY
= L)
OTHER
SLICES
MS
ISS
LSS
SA
F7
G
f(Y)
f (Y)
fM
fM
X
1
X
Ri A Si
RiVSi
GVPC n
C n+7 "iJ' C n+8
P
F7
G
f(Y)
f(Y)
f(Y)
f (y)
X
2
X
Ri A Si
RiVSI
GVPC n
C n+7 "iJ' C n+8
P
F7
G
f(Y)
f(Y)
f (y)
fM
X
3
X
Ri A Si
RiVSi
GVPC n
C n+7 "iJ' C n+8
P
F7
G
fM
f(Y)
fM
f{Y)
X
4
X
0
Si
GVPC n
C n+7 "iJ' C n+8
P
F7
G
f(Y)
fM
f(Y)
fM
X
5
X
0
Si
GV PCn
C n+7 "iJ' C n+8
P
F7
G
f(Y)
f (Y)
fM
fM
X
6
X
0
Ri
GV PCn
C n+7 "iJ' C n+8
P
F7
G
f(Y)
f (y)
fM
fM
X
7
X
0
Ri
GVPC n
C n+7 'V" C n+8
P
F7
G
f(Y)
f(Y)
f (y)
f (Y)
X
8
H
0
1
0
0
0
F
G
f(Y)
f(Y)
f (Y)
f (Y)
X
9
X
Ri A Si
1
0
0
0
F
G
f(Y)
f (Y)
f (y)
fM
X
A
X
Ri A Si
RiVSi
0
0
0
F
G
f(Y)
f(Y)
f (y)
f (Y)
X
B
X
Ri A Si
RiVSi
0
0
0
F
G
fM
f(Y)
f(Y)
f (Y)
X
C
X
Ri A Si
1
0
0
0
F
G
f(Y)
f(Y)
f(Y)
f (Y)
X
D
X
Ri A Si
1
0
0
0
F
G
f(Y)
f(Y)
f(Y)
f(Y)
X
E
X
Ri A Si
1
0
0
0
F
G
f(Y)
f (Y)
f(Y)
f(Y)
X
F
X
Ri A Si
1
0
0
0
F
G
f(Y)
f(Y)
f(Y)
f (Y)
NOTES:
f (y) = Yo Y l '12 '13 . . . . . . Y7
f(0) = 0 0 0 10 2 0 3 . . . . . . 0 7
L = LOW = 0
H = HIGH = 1
V = OR
A = AND
"iJ'
P
G
= Exclusive OR
= P7 Pe· ..... PiP2 Pl Po
= G 7 V G6 P7 V G5 Pe P7 V G4 PS P6 P7
V G 3P4 P5 Pe P7 V ...... V G l P2 P3 P4 ... P7
S8-31
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to + 7.0
UNIT
SYMBOL
V
TA
Operating
Temperature
o to + 70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
PT
Power Dissipation
1.5
1.5
W
lOUT
DC Output Current
50
50
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
C OUT
Output Capacitance
TYP.
UNIT
VIN = OV
10
pF
VOUT = OV
15
pF
CONDITIONS
NOTE:
1. This parameter is sampled and not 100% tested.'
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Vee = S.OV ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VlC = 0.2V
VHe = Vee - 0.2V
SYMBOL
VIH
"'l
IIH
III
MIN.
TYP,!2)
MAX.
UNIT
Input HIGH Level(4)
2.0
-
-
V
Input LOW Level (4)
-
-
0.8
V
0.1
5
pA
pA
TEST CONDITIONS (1)
PARAMETER
Input HIGH Current
Vee = Max., "'N = Vee
Input LOW Current
Vee = Max., "'N = OV
-
-0.1
-5
VHe
Vee
-
10H = -6mA MIL.
2.4
4.3
10H = -8mA COM'L.
2.4
4.3
10l = 300pA
-
GND
10L = 12mA MIL.
-
0.3
Vle
0.5
10L = 16mA COM'L.
0.3
0.5
Vo = OV
-
-40
Vo = Vee (max.)
-
-
-15
-
-
10H = -300pA
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Vee = Min.
VIN = VIH or "'l
Vee = Min.
"'N = "'H or"'L
loz
los
Off State (High Impedance)
Output Current
Vee = Max.
Output Short Circuit Current
Vee = Min., VOUT = OV
(3)
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typicaj values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment. Guaranteed by Design.
58-32
-
V
V
pA
40
mA
~
~--
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
..~----.------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Cont'd)
Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)
TA = O°C to + 70°C
TA = -55°C to +125°C
VlC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS
PARAMETER
ICCOH
Quiescent Power Supply Current
CP = H (CMOS Inputs)
Vcc = Max.
VHC :5 V1N • \'IN :5 VlC
fcp = 0, CP = H
ICCOl
Quiescent Power Supply Current
CP = L (CMOS Inputs)
Vcc = Max.
VHC :5 V1N , V1N :5 VlC
fcp = 0, CP = L
ICCT
Quiescent Input Power Supply (5)
Current (per Input @ TTL High)
VCC
Dynamic Power Supply Current
Vcc = Max.
VHC :5 \'IN • \'IN :5 VlC
Outputs Open. OE = L
ICCD
TYP.(2)
MAX.
UNIT
-
150
250
mA
-
50
100
mA
-
0.3
0.5
-
3.6
7.7
COM'L.
3.6
5.2
MIL.
-
136
252
COM'L.
-
136
227
MIL.
-
150
275
COM'L.
-
150
250
= Max. V1N = 3AV, fcp = 0
Vcc = Max .• fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC :5 V1N , \'IN :5 VlC
Icc
MIN.
(1)
MIL.
mA/lnput
mA/MHz
Total Power Supply Current (6)
mA
Vcc = Max .• fop = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
\'IH = 3AV. \'Il = OAV
NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3AV, subtracting out ICCOH' then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CDH) + ICCOl (1 - CDH) + ICCT(NT x D H) + ICCD (fcp)
CDH = Clock duty cycle high period.
DH = Data duty cycle TTL high period (\1N = 3AV).
NT = Number of dynamic inputs driven at TTL levels.
fcp = Clock input frequency.
S8-33
---~
..- . - -........
-----
----_._ .. ....•....
~
-~--~----~
----
...... ---..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403A GUARANTEED COMMERCIAL AND
MILITARY RANGE PERFORMANCE
Table 8 Enable/Disable Times All Functions
Table 7 Clock and Write Pulse Characteristics All Functions
COM'L
MIL
UNIT
ns
Minimum Clock High Time
10
ns
Minimum Time CP and WE both Low to Write
10
ns
DISABLE
COM'L MIL
UNIT
OEy
Y
12
1»20{
10
1.·>12·••• ·•·
ns
OE B
DB
14
'.22
12
.13.
ns
OEA
DA
15
1<22
13
14'.
ns
18
SID
23
<25
12
1«13 • ·....
ns
18
010
16
124
21
"·22"
ns
Ie. 7. 6. 5
010
17
1<28
19
>,22
ns
21
li3t>
19
1)22/
ns
NOTE:
C L = 5.0pFforoutputdisabletests. Measurement Is made to a 0.5Vehange
on the output.
010
14.3.2.1.0
10
Minimum Clock Low Time
ENABLE
MIL.
COM'L
TO
FROM
The tables below specify the guaranteed performance of the
IDT49C4a3A over the commercial operating range of a to + 7aoC
with Vee from 4.75 to 5.25V, and over the military operating range
of -55 to + 125°C with Vee from 4.5 to 5.5V. All data are in
nanoseconds, with input switching between a and 3Vat 1V/ns and
measurements made at 1.5V. All outputs have maximum DC load.
NOTE:
Guaranteed by Design.
Table 9. Set-up and Hold Times All Functions
tpWL
I
I
FROM
HOLD
SET-UP
HOLD
SET-UP
WITH RESPECT TO COM'L MIL COM'L MIL COM'L MIL. COM'L MIL
Y
CP
-
.2. .
WE HIGH
CP
7
~ .•...
WE LOW
CP
-
n
8
2
\4
ns
2
-
2
)2
ns
Prevent Writing
-
10
0
0
ns
Write into RAM
2
+
?
A. BSouree
CP
11
2
-
CP
6
(3)
(3)
B Destination (3)
lEN
6
~
~
2
B Destination (3)
WE
6
~
~
2
010 0 . 15
CP
-
5
lB. 7.6.5
CP
-
-
lEN HIGH (3)
CP
7
(~
lEN LOW (3)
CP
14.3.2.1.0
CP
-
16
:',"
CP
-
-
8
)
2
CP
-
-
28
.... ,
0
en
COMMENTS
-
B Destination (3)
0 0 .01
UNIT
;:"
I
[
Store Yin RAM/O (1)
ns
Latch Data from RAM Out
ns
Write Data into B Address
&
ns
Write Data into B Address
?
ns
Write Data into B Address
) ..).;
ns
Shift 0
((}i
ns
Write into 0 and RAM (2)
-
(
ns
Prevent Writing into 0 and RAM (2)
10
H
ns
Write into 0 and RAM
i
g
ns
Write into 0 and RAM (2)
ns
Write into 0
9
ns
ALU Carry In to RAM
.•
23
0
NOTES:
1. The intemal V-bus to RAM set-up condition will be met 5ns after valid Y output (OEy= 0)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. The writing of data is controlled by CPo lEN. and WE; all must be LOW in order to write. The set-up time of B destination address is with respecttothe last of
these three inputs to go LOW. and the hold time is with respect to the first to go HIGH.
4. A· - ' implies this path does not exist.
S8-34
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
STANDARD AND INCREMENT (SF-4) /DECREMENT (SF-3) BY ONE OR TWO
INSTRUCTIONS
TO
FROM
SLICE
V
Com'l. MII. Com'l. Mil.
A, BAddr
Any
J
41
Q,
C n =18
P
OVR
N
Z
I
44
DA,DB
44
42
47
47
L'
I;
5
1
I
DA, DB
Cn
Any
Any
34
28
27
28
>.
t
-
15
29
Any
38
23
32
I
34
36
••,>
22
3E
'
26
" - 12 - If;
~~
26
23
..
48
\
36
If
i2
I.")
-
-
~
42
I,
I~
MSS
Any
43
>
44
39
-
T -
18
I 25
51
54
'~ 38
21
.'
21
-
Any
- Ii
( -
21
-
17
I
-
1< .'.,
\/
1.0
48
52
I~
:0
24
I~
IT-
I?i
28
0
26 L3C
36
2:
-
i~
-
3
~"
-
46
ILO
ns
26 130
26
30
ns
37
-
-
;
37
I}
20
I{/
h-
•
••••
'1 I,~
-
)
li
1<
1
>
ns
•••••
IS3
I?/
27
1<
I">
?
51° 0 ,15
UNIn
81°0
PARITY
Com'l. Mil.
I·······.··
24
7
-
20
20
40
'.:
24
i::.":
<
39
<
<
-
:>.
-
21
81°15
I
41 I
.::.:
-
~
Any
-
<
Ii
..
...
CP
81°0
I:{
:::::
'."'"
IS-O
0100,15
WRITE
Com'l. MII. Com'l. MII. Com'l. MII. Com'l. MII. Com'l. Mil. Com'l. MR. Com'l. Mn • Com'l. MII. Com'l. Mil.
19
""::
I~o
I
I.'.'.
140
......
41
41
';
51
1
t4~
kL -
I
II
.~.
iko
.>;0
1:/
';3
16
ns
.
ns
ns
ns
MULTIPLY INSTRUCTIONS
FROM
SLICE
V
Com'l.
N
Z
Mil.
Com'l.
A, BAddr
Any
49
53
DA,DB
Any
41
34
Cn
Any
32
18
IS-o
Any
46
38
OVR
DA,DB
Mil.
34
24
CP
31
ns
ns
Unsigned Multiply
SFO: F=S+CnlfZ=L
F=S+R+Cn If Z=H
Y15=Cn+ 16 (MSS)
Z=QO (LSS)
Y=Log F/2
Q=LogQ/2
Two's Complement Multiply
SF 2: F=S+CnlfZ=L
F=S+R+Cn If Z=H
V15=F15 V OVR (MSS)
Z=QO(LSS)
V=Log F/2
Q=LogQ/2
Two's Complement Mu~lplY Last Cycle
SF 6: F= S+CnlfZ=L
F=S-R-1+Cn IfZ=H
Y15=OVR V F15 (MSS)
Z=QO(LSS)
Y=Log F/2
Q=Log Q/2
NOTES:
1.
A - _. means the delay path does not exist
2. An ••• means the output may be enabled or disabled by the Input; refer to function table.
3. This specification Is not tested.
S8-35
--_..
__ _ - - - - - - - - - - - - - - ..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
BCD INSTRUCTIONS F-1
D&
FROM
SLICE
Y
A. B Addr
Any
49
53
DA. DB
Any
41
34
Cn
Any
32
18
25
NOTE:
1.
Binary to BCD and mUltipreclslon Binary to BCD Instructions only
BCD to Binary conversion (SF 1)
BCD divide by two (SF 7)
Binary to BCD conversion (SF 9)
BCD add (SF B)
BCD substract (SF F)
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SF-5)
FROM
Com'l.
A. BAddr
Any
49
DA, DB
Any
41
Cn
Any
18-0
Any
46
CP
Any
52
z
G,P
Y
SLICE
MB.
Mil.
Com'l.
N
Mil.
Com'l.
5056
Z
(OEy=
lOW)
SIOO.15
SF 5: F=S+Cnlf Z=L
~15S=+s~g~~1~ (MSS)
ZaS15 (MSS)
V=F
C=C
N=F15; Z=L
N=F15 ...,.S15; ZaH
NOTES:
1.
A - _. means the delay path does not exist.
.
2.
An ••• means the output may be enabled or disabled by the Input; refer to function table.
3.
This specification Is not tested.
S8-36
OVR
DA, DB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE
IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS
C & E)
FROM
Y
SLICE
Com'l.
A, BAddr
Any
49
DA. DB
Any
41
Cn
Any
32
18-0
Any
46
CP
1.
2.
Only 1st divide and normalization
Only two's complement divide and two's complement divide correction
Double Length Normalize and First Divide Op
SFA: F=S+Cn
~1~i~~~~~~RI5
(MSS)
Cn+ 16=F15 'V' F14 (MSS)
OVI.l.=,I;Z.~llMSS.L.
Z=OO 010203 ... 015 FO Fl F2 F3 ... F15
Y=Log 2F
0= Log 20
Two's Complement Divide
SFC: F=S+R+Cn II Z=L
TWo's Complement DMde Correction and Remainder
SFE: S=Cn II Z=L
~IOS-~-; +~ ~f5=(~SS)
Z=~15 ~~15 (MSS) Irom previous cycle
Y=Log2F
0=Log20
~:'t115+~nRI:g(M~) Irom previous cycle
Y=F
O=Log20
SINGLE LENGTH NORMALIZATION
Y
FROM
Com'L
A. BAddr
Any
49
DA. DB
Any
41
en
Any
32
OVR
DA,DB
Mil.
18 - 0
NOTES:
1.
2.
3.
A "-" means the delay path does not exist.
An "0" means the oU1put may be enabled or disabled by the Input; refer to function table.
This specification Is not tested.
S8-37
----_... _ - " " - - - - - - - - - - - - -
- - - - - - - . --_ ....-._... _-
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403 GUARANTEED COMMERCIAL AND
MILITARY RANGE PERFORMANCE
Table 11. Enable/Disable Times All Functions
FROM
The tables below specify the guaranteed performance of the
lOT49C403 over the commercial operating range of 0 to 70 °C with
'tc from 4.75 to 5.25V, and over the military operating range of -55
to + 12SoCwith Vccfrom 4.5to S.SV. All data are in nanoseconds,
with input switching between 0 and 3V at 1VIns and measurements
made at 1.SV. All outputs have maximum DC load.
Table 10. Clock and Write Pulse Characteristics All Functions
COM'L.
MIL.
UNIT
12
1/13
ns
Minimum Clock High Time
12
1(13
ns
Minimum Time CP and WE both Low to Write
12
1\13
ns
DISABLE
COM'L. MIL.
1··.<1 ..•.•..
UNIT
OEy
Y
15
>24C
12
OE B
DB
17
.·26)
15
16
O~
DA
18
•..·26/
16
••. 17
ns
la
SIO
28
'302
15
16
ns
la
QIO
20
.. 29
25
27
ns
la. 7. 6. 5
QIO
21
·•... 34<)
22
26
ns
QIO
25
'
22
26
37
I
ns
ns
ns
NOTE:
C L = 5.0pF for output disable tests. Measurement is made to a 0.5V change
on the output.
14.3.2.1.0
Minimum Clock Low Time
ENABLE
COM'L
MIL.
TO
NOTE:
Guaranteed by design.
Table 12. Set-up and Hold Times All Functions
t pWL
1
I
WITH RESPECT TO
FROM
SET-UP
COM'L. MIL.
HOLD
SET-UP
HOLD
COM'L. MIL. COM'L. MIL. COM'L. MIL.
UNIT
COMMENTS
V
CP
-
1>2<
-
./S
10
hi
2
J2
ns
WE HIGH
CP
8
}9<)
2
-
).:::-<
2
>2<
ns
Prevent Writing
WE LOW
CP
-
1< S
-
>2\
:.;:.<
12
13<
0
.0
ns
Write into RAM
Store V in RAM/Q (1)
A. 8 Source
CP
14
[··.it?}
2
\ii
-
.::C:}
-
-
ns
Latch Data from RAM Out
8 Destination (3)
CP
7
1&>
(~
>~<
(~
\~ '...
2
2
ns
Write Data into 8 Address
8 Destination (3)
lEN
7
Ii)
(3)
«~
(3)
/{~
2
2
ns
Write Data into B Address
. B Destination (3)
WE
7
H.~\
(~
~>
2
2 •.
ns
Write Data into B Address
QIO O• 15
CP
6
t
.:
ns
ShiftQ
CP
-
L,--
la, 7, 6. 5
-
[.-.
~
'::-?
27
30
ns
Write into Q and RAM
lEN HIGH (3)
CP
8
U(
(3)
(:3)'
I·' i· .••'.·
ns
Prevent Writing into Q and RAM
lEN LOW
CP
[--
-
I:>
10
111
.......
ns
Write into Q and RAM
CP
-
CP
-
1«--·'
-
CP
-
I···.·.jc· •.
-
1_--<
--
(3)
14,3,2,1,0
Q o• Q1
en
1
••.•
8
1<7
1·• 9·.·.·
7.
(3)
1· ••• ·•• -::'•••••
••
0
0
1
19
21
ns
Write into Q and RAM
10
11
2
2
ns
Write into Q
34
36
0
0
ns
ALU Carry In to RAM
•
(2)
(2)
(2)
NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid V output (OEy= 0)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. The writing of data is controlled by CP. IEN. and WE; all must be LOW in order to write. The set-up time of B destination address is with respectto the last of
these three inputs to go LOW. and the hold time is with respect to the first to go HIGH.
4. A" _. implies this path does not exist.
S8-38
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE
IDT49C403 GUARANTEED MILITARY AND COMMERCIAL RANGE PERFORMANCE
STANDARD AND INCREMENT (SF-4) /DECREMENT (SF-3) BY ONE OR.TWO INSTRUCTIONS
TO
FROM
SLICE
Y
Com'l, MII. Com'l. Mil.
::::.
::
A. BAddr
Any
49
:s
Any
40
:j
53
157
. ',.
34
34
I~
35
Any
33
I
- I:;
21
18
I
Any
46
39
39
.:'.
CP
Any
51
47
53
1
4
i"
.
'51
')
.'
I.~.
27
DA,DB
56
1
<>);
56
ji
WRITE
~~,
40
32 .•.
~
-
...~
i
-
j
:.:,.,
Z
-
28
.. ,"
51 ·.E
4
>
62
-
i
<
65
16,7
ro~t
Any
26
1>9.
SIO O• 15
Any
r·
•~0
25
- I
26
2J
46
I.
-
-
20
....... :...
I
26
' I'
./
-
!
12
24
-
I>
~
-
SI015
<
!~
- Ie
i·
29
63
67
ns
33
33
37
55
59
ns
j~
32
34
32
34
ns
' .."
.
-
29
L
32
I,:····
34
I.>
43 146
34
-
-
-
..
;<
.
45
147
49
-
'.::
Ie
I .....
.:~
26
24
:
......
23
26
,'
!56
ns
53
ns
49
'.........
1<
......
I.
,""
47
I>
-
-
45
1.4j
..... :.
iT
.. '.
.~
I:?
•••••••••••••
I
54
I··
I
I>
-
48
,
•. :,:<'
I>
~.
SIOO
UNITS
PARITY
Com'l. MR.
...
29
I":
-
.••
I·'·,
11
1',...,.:
21 '2~
50
I'
I~
-
is
S....
>
<
1 - 1--
.<
.E
'.. ':' ...'...
It
-
:.,
<
24
1<.'·
~I
....
MSS
SIOO
QI00,15
I···'··'
-
.,.,..-:
.:".
.i/
..~.
"
-4.~'.:
43
,: ...
47
.\ ....
".'>
32
1,•
1·'".,,·,·,
18-0
;
43
I>
Cn
-?
BE
56
50 I
I'·:',
,
DA, DB
OVR
N
Com'l. Mil • Com'l. MII. Com'l. MII. Com'l. MII. Com'l. MII. Com'l. Mil. Com'l. Mil. Com'l. MR. Com'l. Mil.
.':
I··:·,
d
53
Z
G,P
Cn =16
-
<.:':
.:.
ns
,.. :.
19
23
ns
•••••••
MULTIPLY INSTRUCTIONS (SF-O, 2 & 6)
TO
FROM
SLICE
Y
Com'l.
Cn =16
Mil.
Com'l.
Mil.
0, P
Com'l.
N
Z
Mil.
Com'l.
Mil.
Com'l.
OVR
Mil.
Com'l.
DA, DB
Mil.
Com'l.
Mil.
Wiffi'E
Com'l.
Mil.
~IOO, 15
SIOo
Com'l.
A. B Addr
Any
59
ns
DA. DB
Any
48
ns
Cn
Any
40
ns
18-0
Any
55
ns
ns
Unsigned Multiply
SFO: F=S+CnlfZ=L
F=S+R+Cnlf Z=H
Y15=Cn + 16 (MSS)
Z=QO (LSS)
Y=Log F/2
Q=LogQ/2
Two's Complement Multiply
SF 2: F=S+CnlfZ=L
F=S+R+Cn If Z=H
Y15=F15 VOVR (MSS)
Z=QO(LSS)
Y=Log F/2
Q=LogQ/2
Two's Complement Mulliply Last Cycle
SF 6: F= S+CnlfZ=L
F=S-R-1 +Cn If Z=H
Y15=OVRV F15 (MSS)
Z=QO(LSS)
Y=Log F/2
Q=Log Q/2
NOTES:
1.
A • - - means the delay path does not exls\.
2.
An •• - means the output may be enabled or disabled by the Input; refer to function table.
3.
This speCification Is not tested.
S8-39
_.. _ - - - - _.. _........ -
.....
_-_._-------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403 GUARANTEED MILITARY AND COMMERCIAL RANGE PERFORMANCE
BCD INSTRUCTIONS
y
FROM
SLICE
A. B Addr
Any
59
DA. DB
Any
48
Cn
Any
40
e n =18
NOTE:
I.
Binary to BCD and multi precision Binary to BCD Instructions only
BCD to Binary conversion (SFI)
BCD divide by two (SF7)
Binary to BCD conversion (SF9)
BCD add (SFB)
G,P
FROM
SLICE
A. BAddr
Any
59
DA.DB
Any
48
41
Cn
Any
40
22
18-0
Any
55
47
Y
SF 5: F=S+Cn II Z=L
F=S+Cn IIZ=H
Y15=St5 'V' F15 (MSS)
Z=SI5(MSS)
BCD substract (SFF)
WRITE
Z
Y=F
Q=Q
N .. F15;Z=L
N=FI5 'V'SI5; Z=H
NOTES:
I.
A • _. means the delay path does not exist.
2.
An
means the output may be enabled or disabled by the Input; refer to function table.
3.
This specification Is not tested.
·0·
S8-40
QIOO,15
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403 GUARANTEED MILITARY AND COMMERCIAL RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SF-A, C & E)
TO
FROM
SLICE
v
G,P
z
OVR
N
010 0,15
DA,DB
SI015
UNIT
Mil.
A. BAddr
Any
ns
DA. DB
Any
ns
Cn
Any
ns
18-0
Any
ns
ns
NOTES:
1.
Only 1st divide and normalization
2.
Only two's complement divide and two's complement divide correction
Double Length Normalize and First Divide Op
SFA: F=S+Cn
N=FI5 (MSS)
SIOI5=FI5 'Q'R15 (MSS)
C n + 16=F15 'Q'F14 (MSS)
Two's Complement Divide
SFC: F=S+R+C n If Z=L
F=S-R-l+Cn IfZ=H
SIOI5=~(MSS)
Z= ~ (MSS) from previous cycle
V=Log 2F
Q=Log20
~~~'£l~tM~S~lmFo Fl F2 F3 •.. F15
Two's Complement Divide Correction and Remainder
SFE: S=Cn IfZ=L
~:,RFg~nHll;~~s) from previous cycle
Y=F
O=Log2Q
V=Log 2F
Q=Log2Q
SINGLE LENGTH NORMALIZATION (SF-B)
TO
FROM
SLICE
v
G,P
z
N
OVR
010 0,15
SI015
UNIT
ns
ns
ns
ns
ns
ns
NOTES:
1.' A· - ' means the delay path does not exist.
2.
An ••• means the output may be enabled or disabled by the Input refer to function lable.
3.
This specification Is not tested but Is guaranteed by correlation to lhe Standard Function Table.
S8-41
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
CLK
SCLK
ci15
SOl
SOO
Figure 11. IDT49C403 SPC Timing Waveforms
IDT49C403/A SPC AC TIMING
SYMBOL
MIN.
MAX.
tpD
SCLKTOSOO
PARAMETERS
TEST CONDITIONS
3
15
ns
t pD
3
50
ns
ts
Cil5to SOO
Ci15to SCLK
5
CLKto c!t5
20
ts
SOl toSCLK
10
tH
Cil5to SCLK
tH
CLKto SCLK
tH
SOl toSCLK
5
tw
Pulse Width SCLK
20
tCYC
SCLK Period
50
tE
Execution, C!t5 to SCLK
50
-
ns
ts
RL = 500n
CL = 50pF
5
5
CMOS TESTING CONSIDERATIONS
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the VILand VIH levels not to be met until the noise has
settled. To allow for this testinglboard induced noise, lOT recommends using VIL S OV and VIH ~ 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.
There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vcc current changes. Capacitor lead length must be short and
as close to the OUT power pins as possible.
2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
improper device operation and possible latchup.
S8-42
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
IDT49C403 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION
OUTPUTS
INPUTS
Figure 13. Output Structure (All Outputs)
Figure 12. Input Structure (All Inputs)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
Wins
1.5V
1.5V
See Figure 15
Figure 14. Open Drain Structure
SWITCHING WAVEFORMS
INPUTS 3.0V
OV-----"
CLOCK 3.0V
OV
CLOCK
TO
OUTPUT 14_ _ _ _ _.:
DELAY
OUTPUTS
TEST LOAD CIRCUIT
TEST
SWITCH
Open Drain
Disable Low
Enable Low
Closed
All Other Outputs
Open
DEFINITIONS
C L = Load capacitance includes jig and probe capacitance
R T= Termination resistance: should be equal to ZOUT
of the pulse generator
Figure 15. Test Load Circuit
S8-43
I.
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
49C403
Device Type
x
X
x
Speed
Package
Process!
Temperature
Range
Y:'OOk
'------------1 G
Blank
'----------------; A
S8-44
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Pin Grid Array
Standard Speed
High Speed
- - - - - - - - - - - - - - - - - - - - - - - - - - _ . ---_._--_._----
t;)
lOT 49C410
lOT 49C410A
16-BIT CMOS
MICROPROGRAM
SEQUENCER
Integrated Device1echnoJosy.1nc.
MICROSLICE ™ PRODUCT
FEATURES:
DESCRIPTION:
• 16-bit wide address path
- Address up to 65,536 words of microprogram memory
• 16-bit loop counter
- Pre-settable down-counter for counting loop iterations and
repeating instructions
• Low-power CEMOS TM
-Icc (max.)
Military: 90mA
Commercial: 75mA
The lOT49C41 Os are architecture and function code compatible
to the 2910A with an expanded 16-bit address path, thus allowing
for programs up to 65,536 words in length. They are microprogram
address sequencers intended for controlling the sequence of execution of microinstructions stored in microprogram memory. Besides the capability of sequential access, they provide conditional
branching to any microinstruction within their 65,536 microword
range.
The 33-deep stack provides microsubroutine retum linkage and
looping capability. The deep stack can be used for highly nested
microcode applications. Microinstruction loop count control is
provided with a count capacity of 65,536.
During each microinstruction, the microprogram controller provides a 16-bit address from one of four sources: 1) the
microprogram address register ijJPC), which usually contains an
address one greater than the previous address; 2) an extemal (direct) input (D); 3) a register/counter (R) retaining data loaded during a previous microinstruction; or 4) a last-in/first-out stack (F).
The IDT49C410s are fabricated using CEMOS, a CMOS technology deSigned for high performance and high reliability.
The IDT49C410s are pin-compatible, performance-enhanced,
easily upgradable versions of the 2910A.
The IDT49C41 Os are available in 48-pin DIPs (600 mil x 100 mil
centers or space-saving 400 mil x 70 mil centers), 52-pin PLCCand
48-pin flatpacks.
• Fast
-IDT49C410 meets 2910A speeds
- IDT49C410A 30% speed upgrade
• 33-c1eep stack
- Accommodates highly nested microcode
• 16 powerful microinstructions
- Executes 16 sequence control instructions
• Available in 48-pin 600 mil plastic and sidebraze, 48-pin 400 mil
SHRINK-DIP, 52-pin PLCC and 48-pin Flatpack
• Three enables control branch address sources
• Four address sources
• 2910A instruction compatibility
• Military product available compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88643 is listed for this
function
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
RLD
r=~------------~
DECREMENT/
HOLD/LOAD
R=O
CI
DIP
TOP VIEW
OE
~~----l--+--+----~
CEMOS and MICROSLICE are trademarks of
Integrated Device Technology, Inc.
'Vi
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
1989 Integrated Device Technology. Inc.
DSC-9014/-1
S8-45
_
..
_-_ _--_ _..
...
----_._-_ ...... _--_.....
_- _----- . _ - - - - - - - - - - _ _._-_
...
..
..... _..
_----_.__ ... __ .. _---_.._--_ ....- . -..- -
IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
7
6
5
4
3
2
1 52 51 50 49 48 47
VECT
46
NC
PC
45
01
44
MAP
13
12
Vee
43
DO
42
Yo
CI
CP
GNO
OE
Yll
41
J52-1
11
40
39
10
CCEN
CC
RLD.
FULL
NC
Yl
38
37
36
35
34
L2=============:J
011
Yl0
0 10
1314 15 16 17 18 1920 21 22 23 24
FLATPACK
TOP VIEW
PLCC
TOP VIEW
IDT49C410 PIN DESCRIPTIONS
0,
1/0
DESCRIPTION
I
Direct input to register/counter
and multiplexer, Do is LSB.
I,
I
Selects one of sixteen instructions.
CC
I
Used as test criterion. Pass test is a
LOW on CC.
CCEN
I
Whenever the signal is HIGH, CC
is ignored and the part operates
as though CC were true (LOW).
CI
I
Low order carry input to inc rem en- .
ter for microprogram counter.
RLD
I
When LOW forces loading of register/counter regardless of instruction or condition.
OE
I
Three-state control of V, outputs.
CP
I
Triggers all intemal state changes
at LOW-to-HIGH edge.
YI
0
Address to microprogram
memory. Yo is LSB, Y15 is MSB.
FULL
0
Indicates that 33 items are on the
stack.
PL
0
Can select #1 source (usually
Pipeline Register) as direct input
source.
MAP
0
Can select #2 source (usually
Mapping PROM or PLA) as
direct input source.
VECT
0
Can select #3 source (for
example, Interrupt Starting
Address) as direct input source.
01
Yl
34
30
29
Do
Yo
CI
CP
GNO
OE
28
27
Yll
011
26
YIO
010
33
32
31
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAME
36
35
S8-46
25
-----------------------------------------
IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
linkage (the value contained in the microprogram counter). On the
microprogram cycle following the PUSH, this new return linkage
data that was in the microprogram counter is now at the new location pointed to by the stack pointer. Thus, any time the multiplexer
looks at the stack, it will see this data on top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. Ifthe pop occurs, the stack pointer is
decremented at the next LOW-to-HIGH transition of the clock. A
pop decrements the stack pointer which is the equivalent of removing the old information from the top of the stack.
The IDT49C410s are designed so that the stack pointer linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack c~ow to a full 33 locations. After a
depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information
at the top of the stack will be destroyed butthe stack pointer will not
end around. It is necessary to initialize the stack pointer when
power is first turned on. This is performed by executing a RESEr
instruction (instruction 0). This sets the stack pointer to the stack
empty position -the equivalent depth of O. Si milarly, a pop from an
empty stack may place unknown data on the Y outputs, but the
stack pointer is designed so as not to end aroun~. "f!1us, the. stack
pointer will remain at the 0 or stack empty location If a pop IS executed while the stack is already empty.
The IDT49C41 Os' internal 16-bit register/counter is used during
microinstructions eight, nine and fifteen. During these instructions,
the 16-bit counter acts as a down counter and the terminal count
(count = 0) is used by the internal instruction .~LA as an input to
control the microinstruction branch test capability. The deSign of
the internal counter is such that, if it is pre loaded with a number N
and then this counter is used in a microprogram loop, the actual
sequence in the loop will be executed N + 1 times. Thus, it is possible to load the counter with a count of 0 and this will result in the
microcode being executed one time. The 3-way branch microinstruction, instruction 15, uses both the loop counter and the exter- 1:IIo......:~~,;.j.
nal condition code input to control theJinal source address from
the Y outputs of the microprogram sequencer. This 3-way branch
may result in the next address coming from the D inputs, the stack
or the microprogram counter.
The IDT49C410s provide a 16-bit address at the Y outputs that
are under control of the OE input. Thus, the outputs can be put in
the three-state mode, allowing the writable control store to be
loaded or certain types of external diagnostics to be executed.
In summary, the IDT49C410s are the most powerful
microprogram sequencers currently available. They provide t~e
deepest stack, the highest performance and the lowest power diSsipation for today's microprogrammed machine deSign.
PRODUCT DESCRIPTION
The IDT49C410s are high-performance CMOS microprogram
sequencers that are .intended for use. in. very high-speed
microprogrammable microprocessor applications. !he sequencers allow for direct control of up to 64K words of microprogram.
The heart of the microprogram sequencer is a 4-input multiplexer that is used to select one of four address sources te:> select
the next microprogram address. These address sources Include
the register/counter, the direct input, the microprogram counter or
the stack as the source for the address of the next microinstruction.
The register/counter consists of sixteen D-type flip-flop~ which
can contain either an address or a count. These edge-tnggered
flip-flops are under the control of a common clock enable as well as
the four microinstruction control inputs. When the load control
(RDL) is LOW, the data at the D-inputs is loaded into this regist~r on
the LOW-to-HIGH transition ofthe clock. The output of the reglster/
counter is available at the multiplexer as a possible next address
source for the microcode. Also, the terminal count output associated with the register/counter is available at the internal instruction
PLA to be used as a condition code input for some of the
microinstructions. The IDT49C410s contain a microprogram
counter that usually contains the address of the next microinstruction compared to that currently being executed. The
microprogram counter actually consists of a 16-bit incrementerfollowed by a 16-bit register. The microprogram counter. will increment the address coming out of the sequencer gOing to the
microprogram memory if the carry-in inpu~ to this cou~ter is HIGH;
otherwise, this address will be loaded Into the n:'lcroprogram
counter. Normally, this carry-in input is set to the logic HIGH state
so that the incrementer will be active. Should the carry input be set
LOW the same address is loaded into the microprogram counter.
This i~ a technique that can be used to allow execution of the same
microinstruction several times.
There are sixteen D-inputs on the IDT49C41 Os that go directly to
the address multiplexer. These inputs are used to provide a branch
address that can come directly from the microcode or some other
external source. The fourth input available to the multiplexer for
next address control is the 33-deep, 16-bit wide LIFO stack. The
LIFO stack provides return address linkage for subroutines and
loops. The IDT49C41Os contain a built-in stack pOinterthat always
points to the last stack location written. This allows for stack .reference operations, usually called loops, to be performed Without
popping the stack.
The stack pointer internal to the IDT49C410s is actually an up/
down counter. During the execution of microinstructions one, four
and five, the PUSH operation may occur depending on the s~ate of
the condition code input. This causes the stack pointerto be Incremented by one and the stack to be written with the required return
58-47
--------,,--
-,---------
IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIGURE 1. IDT4941 0 FLOW DIAGRAMS
o Jump Zero (JZ)
1 Cond JSB PL (CJS)
2 Jump Map (JMAP)
66
65F18
68
69
70
3 Cond Jump PL (CJP)
~h·
69
65~8
66
67
68
68
N
REGISTER/
COUNTER
30
31
32
33
34
A
5
66
67
6
67 • 5 h
68·
35
6 •
20
21
36
8 Repeat Loop. CNTR ¢. 0 (RFCT)
66
67
68
~
.
STACK
(PUSH)
REGISTER/
COUNTER
N
11 Cond Jump PL & POP (CJPP)
9 Repeat PL. CNTR :f. 0 (RPCT)
:p
65
66
67 [ e r - - I - - -.... 40
14 Continue (CONT)
:t
67
68
10 Cond Return (CRTN)
COUNTER
(LDCT)
STACK
67
65
41
42
66
67
r
68
69
70
12 LD CNTR & Continue (LDCT)
STACK
(PUSH)
68
69
70
71
30
31
68
69 •
7.0
5 Cond JSB R/PL (JSRP)
STACK
7 Cond JUMP R/PL (JRP)
66
65
:
STACK
6 Cond Jump Vector (CJV)
69
66
67
4 Push/Cond LD CNTR (PUSH)
25
26
65~
STACK
40
41
42
43
67
~
66
30
31
32
33
34
35
36
• 37
COUNTER
•
67 .
13 Test End Loop (LOOP)
68
15 Three-Way Branch (TWB)
~
66
67
65
66
67
68
69
~
67
N
72
73
S8-48
STACK
(PUSH)
REGISTER/
COUNTER
68
69
70
71
72
STACK
(PUSH)
IDT49C410/A 16-81T CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 OPERATION
The IDT49C41 Os are CMOS pin-compatible implementations of
the Am2910 and Am2910A microprogram sequencers. The
IDT49C410 sequencers are functionally identical except that they
are 16 bits wide and provide a 33-deep stack to give the
microprogram mer more capability in terms of microprogram subroutines and microprogram loops. The definition of each
microprogram instruction is shown in the table of instructions. This
table shows the results of each instruction in terms of controlling
the multiplexer which determines the Y outputs and in controlling
the signal,§Jhat can be used to enable various branch address
sources. (PL,MAP, VECT). The operation of the register/counter
and the 33-deep stack after the next LOW-ta-HIGH transition ofthe
clock are also shown. The internal multiplexer is used to select
which of the internal sources is used to drive the Y outputs. The actual value loaded into the microprogram counter is either identical
to the Youtput orthe Youtputvalue is incremented by 1 and placed
in the microprogram counter. This function is under the control of
the carry input. For each of the microinstruction inputs, only one of
the three outputs (PL, MAP or VECT) will be LOW. Note that this
function is not determined by any of the possible condition code
inputs. These outputs can be used to control the three-state selection of one of the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the conditional instructions. These are fully defined in the table of instructions. The RLD input can be used to load the internal register/
counter at anytime. When this input is LOW, the data atthe D inputs
will be loaded into this register/counter on the LOW-ta-HIGH transition of the clock.Thus, the RLD input overrides the internal hold or
decrement operations specified by the various microinstructions.
The OE input is normally LOW and is used as the three-state enable for the Y outputs. The internal stack in the IDT49C410s is a
last-in/first-out memory that is 16 bits in width and 33 words deep. It
has a stack pointer that addresses the stack and always points to
the value currently on the top of the stack. When instruction 0 (RESET) is executed, the stack pointer is initialized to the top of the
stack which is, by definition, the stack empty condition. Thus, the
contents of the top of the stack are undefined until the forced PUSH
occurs. A pop performed while the stack is empty will not change
the stack pointer in any way; however, it will result in unknown data
at the Y outputs.
By definition, the stack is full any time 33 more PUSHes than
pops have occurred since the stack was last empty. When this happens, the FU LL flag will go LOW. This signal first goes LOW on the
microcycle after the 33 pushes occur. When this signal is LOW, no
additional pushes should be attempted or the information on the
top of the stack will be lost.
THE IDT49C410 INSTRUCTION SET
INSTRUCTION 0JUMP 0 (JZ)
This instruction is used at power-up time or at any restart sequence when the need is to reset the stack pointer and jump to the
very first address in microprogram memory. The Jump 0 instruction does not change the contents of the register/counter..
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will be
contained in the pipeline register and presented at the D inputs. If
the condition code test is passed, a branch is taken to the subroutine. Referring to the flow diagram for the IDT49C41 Os shown in figure 1, we see that the content of the microprogram counter is 68.
This value is pushed onto the stack and the top of the stack pointer
is incremented. If the test is failed, then this conditional Jump to
Subroutine instruction behaves as a simple continue. That is, the
contents of microinstruction address 68 are executed next.
INSTRUCTION 2JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction opcode.
This is typically accomplished by using a mapping PROM as an
input to the D inputs on the microprogram sequencer. The JMAP .
instruction branches to the address appearing on the D inputs. In
the flow diagram shown in Figure 1, we see that the branch actually
will be to the contents of microinstruction 85 and this instruction
will be executed next.
INSTRUCTION 3CONDITIONAL JUMP PIPELINE (CJP)
The simplest branching control available in the IDT49C410
microprogram sequencers is that of Conditional Jump to Address.
In this instruction, the jump address is usually contained in the microinstruction pipeline register and presented to the D inputs. If the
test is passed, the jump is taken. If the testfails, this instruction executes as a simple continue. In the example shown in the flow diagram of Figure 1, we see that, if the test is passed, the next microinstruction to be executed is the contents of address 25. If the
test is failed, the microcode simply continues to the contents of the
next instruction.
This data sheet contains a block diagram of the IDT49C410
microprogram sequencers. As can be seen, the devices are controlled by a 4-bit microinstruction word (13-10). Normally, this word
is supplied from one 4-bit field of the microinstruction word associated with the entire state machine system. These four bits provide
for the selection of one of the sixteen powerful instructions associated with selecting the address of the next microinstruction. Unused Y outputs can be left open; however, the corresponding most
significant D inputs should be tied to ground for smaller
microwords. This is necessary to make sure the internal operation
of the counter is proper should less than 64K of microcode be implemented. As shown in the block diagram, the internal instruction
PLA uses the four instruction inputs, as well as the CC, CCEN and
the internal counter = 0 line for controlling the sequencer. This
internal instruction PLA provides all of the necessary internal control signals to control each particular part of the microprogram
sequencer. The next address at the Y outputs of the IDT49C410s
can be from one of four sources. These include the internal
INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition independent of the conditional testing, the microprogram counter is
pushed on to the stack. If the conditional test is passed, the counter
will be loaded with the value on the D inputs to the sequencer. If the
S8-49
---------------.----.---------
microprogram counter; the last-in/first-out stack; the register/
counter and the direct inputs.
The following paragraphs will describe each instruction associated with the IDT49C41 Os. As a part of the discussion, an example
of each instruction is shown in Figure 1; The purpose of the examples is to show microprogram flow. Thus, in each example the microinstruction currently being executed has a circle around it. That
is, this microinstruction is assumed to be the contents of the pipeline register at the output of the microprogram memory. In these
drawings, each of the dots refers to the time that the contents of the
microprogram memory word would be in the pipeline register and
is currently being executed.
IDT49C410!A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
counter instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15):
test fails, the contents of the counter will not change. The PUSH/
Conditional Load Counter Instruction is used in conjunction with
the loop instruction (Instruction 13), the repeat file based on the
IDT49C410 INSTRUCTION OPERATIONAL SUMMARY
13-10
=
CC
COUNTER
TEST
STACK
X
X
X
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC
0
JZ
X
1
CJS
PASS
FAIL
2
JMAP
X
3
CJP
4
PUSH
5
,JSRP
6
CJV
7
JRP
8
RFCT
X
X
9
RPCT
X
X
10
CRTN
11
CJPP
12
LDCT
X
13
LOOP
PASS
FAIL
X
X
X
X
X
14
CONT
X
X
lWB
PASS
PASS
FAIL
FAIL
=0
NOT = 0
=0
NOT = 0
15
NC
MNEMONIC
No Change; DEC
=
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
P.~SS
FAIL
PASS
FAIL
PASS
FAIL
X
X
X
X
X
X
X
X
X
X
X
=0
NOT = 0
=0
NOT = 0
X
X
ADDRESS
SOURCE
0
D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK
REGISTER!
COUNTER
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
ENABLE
SELECT
PL
PL
PI:
MAP
PL
PI:
PL
PI:
PL
Pi:
VECT
VECT
PL
PI:
PL
PI:
PL
Pi:
PL
Pi:
PL
Pi:
PL
PL
N~
Pi:
NC
NC
DEC
NC
DEC
PL
PL
Pi:
PI:
Pi:
Decrement
INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE R/PL
(JSRP)
the conditional test is failed, no branch is taken but rather the
microcode simply continues· to the next sequential microinstruction. When this instruction is executed, the VECT output is
LOW unconditionally. Thus, an external 16-bit field can be enabled
on to the D inputs of the microprogram sequencer.
Subroutines may be called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register. In
this instruction, the contents of the microprogram counter are
pushed on the stack and the branch address for the subroutine call
will be taken from either the internal register/counter or the external
pipeline register presented to the D inputs. If the conditional test is
passed, the subroutine address will be taken from the pipeline register. If the conditional test fails, the branch address is taken from
the internal register/counter. An example of this is shown in the flow
diagram of Figure 1.
INSTRUCTION 7CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline register always causes a branch in microcode. This jump will be to one
of two different locations in the microcode address space. If the test
is passed, the jump will be to the address presented on the D inputs
to the microprogram sequencer. If the conditional test failS, the.
branch will be to the address contained in the internal
reg ister/counter.
INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)
INSTRUCTION 8REPEAT LOOP COUNTER NOT EaUAL TO 0
(RFCT)
The Conditional Jump Vector instruction is similar to the Jump
Map instruction in that it allows a branch operation to a microinstruction, as defined from some external source. This instruction is
similar to the Jump Map instruction except that it is conditional.
The Jump Map instruction is unconditional. If the conditional test is
passed, the branch is taken to the new address on the D inputs. If
This instruction utilizes the loop counter and the stack to implement microprogrammed loops. The start address for the loop
would be initialized by using the PUSH/conditional load counter
S8-50
--
_.__ _ - - - - - - ._...
- -.....
_--_ _._.....
...... _...
-
IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INSTRUCTION 13TEST END OF LOOP (LOOP)
instruction. Then, when the repeat loop instruction is executed, if
the counter is not equal to 0, the next microword address will be
taken from the stack. This will cause a loop to be executed as
shown in the Figure 1 flow diagram. Each time the microcode sequence goes around the loop, the counter is decremented. When
the counter reaches 0, the stack will be popped and the microinstruction address will be taken from the microprogram counter.
This instruction performs a timed wait or allows a single sequence
to be executed to the desired number of times. Remember, the actual number of loops performed is equal to the value in the counter
plus 1.
The Test End of Loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the conditional test input is failed, the loop branch address will be that on the
stack. Since we may go around the loop a number if times, the
stack is not popped. If the conditional test input is passed, the loop
is terminated and the stack is popped. Notice that the loop instruction requires a PUSH to be performed at the instruction immediately prior to the loop return address. This is necessary in order to
have the correct address on the stack before the loop operation.
Forthis reason, the stack pointer always points to the last thing written on the stack.
INSTRUCTION 9REPEAT PIPELINE, COUNTER NOT EQUAL TO 0
(RPCT)
INSTRUCTION 14CONTINUE (CONT)
This instruction is another technique for implementing a loop
using the counter. Here, the branch address for the loop is contained in the pipeline register. This instruction does not use the
stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be taken
from the D inputs of the microprogram sequencer. When the
counter reaches 0, the internal multiplexer will select the address
source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.
The Continue instruction is a simple instruction whereby the address for the microinstruction is taken from the microprogram
counter. This instruction simply causes sequential program flow to
the next microinstruction in microcode memory.
INSTRUCTION 15THREE WAY BRANCH (TWB)
The Three Way Branch instruction is used for looping while waiting for a conditional event to come true. If the event does not come
true after some number of microinstructions, a branch is taken to
another microprogram sequence. This is depicted in Figure 1
showing the I DT49C410 flow diagrams and is also described in full
detai I in the IDT49C410s' instruction operational summary. Operation Of. the instruction is such that., any time the external conditional
test input is passed, the next microinstruction will be that associated with the program counter and the loop will be left; the stack is
aiso popped. Thus, the external test input overrides the other possibilities. Should the external conditional test input not be true, then
the rest of the operation is controlled by the internal counter. If the
counter is not equal to 0, the loop is taken by selecting the address
on the top of the stack as the address out of the Y outputs of the
IDT49C410s. In addition, the counter is decremented. Should the
external conditional test input be failed and the counter also have
counted to 0, then this instruction Uti mes out". The result is that the
stack is popped and a branch is taken to the address presented to
the D inputs of the IDT49C41 0 microprogram sequencers. This address is usually provided by the external pipeline register.
INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating subroutines. The fact that it is conditional allows the subroutine either
to be ended or continue. If the conditional test is passed, the address of the next microinstruction will be taken from the stack and it
will be popped. If the conditional test failS, the next microinstruction address will come from the internal microprogram
counter. This is depicted in the flow diagram of Figure 1.lt is important to remember that every subroutine call must somewhere be
followed by a return from subroutine call in order to have an equal
number of pushes and pops on the stack.
INSTRUCTION 11 CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a technique for exiting a loop from within the middle of the loop. This is
depicted fully in the flow diagrams forthe IDT49C41Os as shown in
Figure 1. The conditional test input for this instruction results in a
branch being taken if the test is passed. The address selected will
be that on the D inputs to the microprogram sequencer and since
the loop in being terminated, the stack will be popped. Should the
test be failed on the conditional test inputs, the microprogram will
simply continue to the next address as taken from the
microprogram counter. The stack will not be affected if the conditional test input is failed.
Ell
I
I
CONDITIONAL TEST
Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inputs associated with the conditional test input. These include the CCEN and
the CC inputs. The CCEN input is a condition code enable. Whenever the CCEN input is HIGH.J!1e CC input is ignored and the device operates as though the CC input were true (LOW). Thus, a fail
of the external test condition can be defined as CCEN equals LOW
and CC equals HIGH. A pass condition is defined as a CCEN
equal to HIGH or a CC equal to LOW. It is important to recognize
the full function of the condition code enable and the condition
code inputs in order to understand when the test is passed or
failed.
INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)
The Load Counter and Continue instruction is used to place a
value of the D inputs in the register/counter and continue to the next
microinstruction.
S8-51
..
__._._-_
.. _...
_--_._---
....
_._._. __._--
..
__
..•..••. _..
__.- _--_._---_._---_•. .•.. ... _----_._'-",._-_._-"..._.
•.
_
_
IDT49C410/A 16-81T CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
CAPACITANCE
(1)
COMMERCIAL
RATING
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°c
TSIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°c
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
CIN
V
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
30
30
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS
VIN = OV
COUT
Output CapaCitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.
TYP.
UNIT
5
pF
7
pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
TEST CONDITIONS (1)
PARAMETER
Output HIGH Level
Guaranteed Logic High Level
Output LOW Level
Guaranteed Logic Low Level
IlL
Input HIGH Current
Vee = Max.. \'IN = Vee
IlL
Input LOW Current
Vee = Max., VIN = GND
"'H
"'L
VOH
Output HIGH Voltage
Vee = Min.
\'IN = VIH or\1L
(4)
(4)
Output LOW Voltage
\'IN = VIH or\1L
loz
Off State (High Impedance)
Output Current
Vee = Max.
los
Output Short Circuit Current
Vee = Min., VOUT = OV (3)
TYP.(:!)
MAX.
UNIT
2.0
-
V
-
-
0.8
V
-
0.1
S
)JA
)JA
-
-0.1
-S
10H = -300)JA
VHe
VHe
-
10H = -12mA MIL.
2.4
4.3
10H = -1SmA COM'L.
2.4
4.3
-
10L = 300)JA
-
GND
VLC
10L = 20mA MIL.
-
0.3
O.S
10L = 24mA COM'L.
-
0.3
O.S
Vo =0
-
-0.1
-10
Vo = Vee (Max.)
-
0.1
10
-30
-
-
Vee = Min.
VOL
MIN,
NOTES:
1. For conditions shown as max. or min .. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
S8-52
V
V
)JA
mA
IDT49C410/A 16·BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vcc - 0 2V
Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)
TEST CONDITIONS
PARAMETER
SYMBOL
MIN.
(1)
TYP.(2) MAX.
UNIT
Quiescent Power Supply Current
CP = H (CMOS Inputs)
Vcc = Max.
VHC :::; V1H ' \IL :::; VLC
fc = 0, CP = H
-
35
50
mA
Icccl
Quiescent Power Supply Current
CP = L (CMOS Inputs)
Vcc = Max.
VHC :::; V1H ' \IL :::; VLC
fcp = 0, CP = L
-
35
50
mA
ICCT
Quiescent Input Power Supply
Current (per Input @TTL High)(5)
Vcc
-
0.3
0.5
mAl
Input
ICCD
Dynamic Power Supply Current
Vcc = Max.
VHC :::; V1H , V1L :::; \tc
Outputs Open, DE = L
-
1.0
3.0
1.0
1.5
-
45
80
45
65
-
50
90
50
75
ICCCH
Icc
Total Power Supply Current(6)
= Max., '-'iN = 3.4V, fcp = 0
Vcc = Max., fcl" = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC < ~H , VIL < VLC
Vee = Max., fcl" = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC :::; V1H , VIL :::; VLC
MIL.
COM'L.
MIL.
COM'L.
MIL.COM'L.
mAl
MHz
mA
NOTES:
5. ICCCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IcccH, then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS orTTLinput levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = IcccH (CD H)
+
IccCl
(1 - CDH)
+
ICCT (NT X DH)
+
ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (\IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input Frequency
CMOS TESTING CONSIDERATIONS
3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the Vil and VIH levels not to be met until the noise has
settled. To allow for this testinglboard induced noise, lOT recommends using Vil :::; OV and VIH ~ 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.
There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vee current changes. Capacitor lead length must be short and
as close to the OUT power pins as possible.
2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
improper device operation and possible latchup.
58-53
IDT49C410/A 16-81T CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410
ACELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
IDT49C410A
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
t(h)
t(S)
INPUTS
MIL.
COM'L.
MIL.
t(h)
t(e)
INPUTS
UNIT
COM'L.
UNIT
COM'L.
MIL.
COM'L.
MIL
DI-+R
6
7
0
0
ns
DI-+R
16
16
0
0
ns
DI-+PC
13
15
0
0
ns
DI-+PC
30
30
0
0
ns
10- 3
23
25
0
0
ns
10 - 3
35
38
0
0
ns
CC
15
18
0
0
ns
CC
24
35
0
0
ns
CCEN
15
18
0
0
ns
CCEN
24
35
0
0
ns
CI
6
7
0
0
ns
CI
18
18
0
0
ns
RLD
11
12
0
0
ns
RLD
19
20
0
0
ns
PL, VECT, MAP
FULL
II. COMBINATIONAL DELAYS
y
INPUTS
COM'L.
MIL.
COM'L.
II. COMBINATIONAL DELAYS
MIL.
COM'L.
MIL.
INPUTS
UNIT
PL, VECT, MAP
Y
COM'L.
MIL.
COM'L.
FULL
COM'L.
MIL.
-
ns
-
ns
DO-11
12
15
-
-
-
-
ns
DO-11
20
25
-
-
-
10 - 3
20
25
13
15
-
-
ns
10 - 3
35
40
30
35
CC
16
20
-
-
-
-
ns
CC
30
36
-
-
-
CCEN
16
20
CP
OE(1)
28
33
10/10
13/13
UNIT
MIL.
ns
ns
-
-
-
ns
CCEN
30
36
-
-
22
25
ns
40
46
-
-
31
35
ns
-
-
-
ns
CP
OE (1)
25/27
25/30
-
-
-
-
ns
NOTE:
1. Enable/Disable. Disable times measure to 0.5V change on output voltage level with C L = 5pF.
NOTE:
1. Enable/Disable. Disable times measure bO.5V change on output voltage level with C L = 5pF.
III. CLOCK REQUIREMENTS
III. CLOCK REQUIREMENTS
COM'L.
MIL.
UNIT
COM'L
MIL
UNIT
Minimum Clock LOW Time
18
20
ns
Minimum Clock LOW Time
20
25
ns
Minimum Clock HIGH Time
17
20
ns
Minimum Clock HIGH Time
20
25
ns
Minimum Clock Period
35
40
ns
Minimum Clock Period
50
51
ns
SWITCHING WAVEFORMS
INPUTS 3.0V
OV----""'"
CLOCK 3.0V
OV
INPUT TO
CLOCK
I"'-~ OUTPUT
TO
DELAY
OUTPUT I_-------;~
DELAY
OUTPUTS
S8-54
IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION
OUTPUTS
INPUTS
Figure 2. Output Structure
Figure 1. Input Structure
TEST LOAD CIRCUIT
TEST
SWITCH
Open Drain
Disable Low
Enable Low
Closed
All other Outputs
Open
DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the
Pulse Generator
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Figure 3. Switching Test Circuits
GND to 3.0V
Wins
1.5V
1.5V
See Figure 3
ORDERING INFORMATION
IDT
49C410
Device Type
X
X
x
Speed
Package
Process/
Temperature
Range
y:Wnk
'--------------i
P
XC
C
J
F
L - - - - - - - - - - - - - - - - - l Blank
A
S8-55
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Plastic DIP
Sidebraze SHRINK-DIP
Sidebraze DIP
PLCC
Flatpack
16-Bit Microprogram Sequencer
Fast 16-Bit Microprogram Sequencer
Integrated Device1echnology.lnc.
16-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
lOT 39C60
lOT 39C60-1
lOT 39C60A
lOT 39C60B
MICROSLICE ™ PRODUCT
• Pin-compatible to all versions of the 2960
• Military product available compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88613 available for this
function
FEATURES:
• Low power CEMOS ™
- Military: 100mA (max.)
- Commercial: 85mA (max.)
• Fast
- Data in to error detect
IDT39C60A: 20ns (max.), IDT39C60B: 16ns (max.)
IDT39C60-1: 25ns (max.)
IDT39C60: 32ns (max.)
- Data in to corrected data out
IDT39C60A: 30ns (max.), IDT39C60B: 25ns (max.)
IDT39C60-1: 52ns (max.)
IDT39C60: 65ns (max.)
• Improves system memory reliability
- Corrects all single-bit errors; detects all double and some
triple-bit errors
DESCRIPTION:
The IDT39C60family are high-speed, low-power, 16-bit Error Detection and Correction Units which generate check bits on a 16-bit
data field according to a modified Hamming Code and correct the
data word when check bits are supplied. When performing a read
operation from memory, the IDT39C60s will correct 100% of all
single bit errors, will detect all double bit errors and some triple bit
errors.
The IDT39C60s are easily cascadable from 16 bits up to 64 bits.
Sixteen-bit systems use 6 check bits, 32-bit systems use 7 check
bits and 64-bit systems use 8 check bits. For all three configurations,
the error syndrome is made available.
All parts incorporate 2 built-in diagnostic modes. Both simplify
testing by allowing for diagnostic data to be entered into the device
and to execute system diagnostic functions.
The IDT39C60s are pin-compatible, performance-enhanced
functional replacements for all versions of the 2960. They are fabricated using CEMOS, a CMOS technology designed for highperformance and high-reliability. The devices are packaged in
either 48-pin DIPs and 52-pin PLCC and LCCs.
Military grade product is manufactured in compliance to the
latest revision of MIL-STD-883, Class B.
• Cascadable
- Data words up to 64 bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Available in 48-pin DIP, 52-pin PLCC and LCC
,FUNCTIONAL BLOCK DIAGRAM
LEoUT
OE BYTE 0
CI?o-e
DATA 0-7
DATA 8-15
OE BYTE 1
SCO-6
LEOIAG
CODE ID
DIAG MODE
PASSTHRU
GENERATE
CORRECT
r:~t~~=:r=:::::--.,
c=~~---t
c=~----t
....
r---:~--
C~--"""
CONTROL
LOGIC
____- l
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC-9016/1
S8-56
·
_. ._-_.._ - - . _ - - - - - - - - - __
IDT39C60/-1/A/B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
CORRECT
DATA15
DATA14
DATA 13
DATA12
LEIN
LEolAG
01: BYTE 1
DATA 11
DATA 10
DATA 9
DATAs
GND
DATA 7
DATA 6
DATA 5
DATA 4
'OE" BYTEo
LEoUT
DATA 3
DATA 2
DATAl
DATA 0
SC l
PASSTHRU
DIAG MODEl
DIAG MODEa
CODE ID2
CODE IDl
CODE IDo
GENERATE
CB6
CBo
CB5
CB4
CB3
Vee
CB 2
CBl
MULT ERROR
~
O1:se
SCo
SC5
SC3
SC2
SC4
Sea
INDEX
(1'
L.:L.:UWUUiIUUU WWL..
7 6 5 4 3
:] s
:] 9
:110
:1 11
DATA 9 :1 12
DATAs
GND
DATA 7
DATA 6
DATA 5
DATA 4
Oi: BYTEo
LE 01AG
0'1: BYTE 1
DATA 11
DATA 10
Vee
52 51 50 49 48 47
46 [:
45 C
1
PIN 1
INDICATOR
FOR PLCC
43
42
41
40
39
3S
37
36
35
J52-1
&
L52-1
C
[:
[:
c
[:
[:
26
27 28
29 30
31 32 33
CBs
CBo
CB5
CB4
CB3
Vee
CB 2
C CBl
[:
[:
34 [:
21 22 23 24 25
GND
GENERATE
MuLT ERROR
'E"R'R'OR
O'I:sc
nnnnnnnnnnnnn
DIP
TOP VIEW
(600 mil x 100 mil CENTERS)
PLCC/LCC
TOP VIEW
(750 mil x 750 mil)
S8-57
._.._._-_._._---_._--------
IDT39C60/-1/Al8 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT'
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
I/O
I/O
DESCRIPTION
16 bidirectional data lines. They provide inputto the Data Input Latch and receive output from the Data Output Latch. DATAo is
the least significant bit; DATA15 the most significant.
CB O- 6
I
Seven check bit inputlines. The check bitlines are used to input check bits for error detection. Also used to input syndrome bits
for error correction in 32- and 64-bit configurations.
LEIN
I-
Latch Enable - Data Input Latch. Controls latching of the input data. When HIGH. the Data Input Latch and Check Bit Input
Latch follow the input data and input check bits. When LOW. the Data Input Latch and Check Bit Input Latch are latched to their
previous state.
GENERATE
I
Generate Check Bits input. When this input is LOW. the EDC is in the Check Bit Generate mode. When HIGH. the EDC is in the
Detect mode or Correct mode. In the Generate mode. the circuit generates the check bits or partial check bits specific to the
data in the Data Input Latch. The generated check bits are placed on the SC outputs. In the Detect or Correct modes the EDC
detects single and multiple errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit
Input Latch. In Correct mode. single-bit errors are also automatically corrected - corrected data is placed at the inputs of the
Data Output Latch. The syndrome result is placed on the SC outputs and indicates. in a coded form. the number of errors and
the bit-in-error.
SCo-e
0
Syndrome/Check Bit outputs. These seven lines hold the check/partial check bits when the EDC is in Generate mode and will
hold the syndrome/partial syndrome bits when the device is in Detect or Correct modes. These are 3-state outputs.
orsc
I
Output Enable- Syndrome/Check Bits. When LOW. the 3-state output lines SC o- e are enabled. When HIGH. the SC outputs
are in the high impedance state.
EmmR
0
Error Detected output. When the EDC is in Detect or Correct mode. this output will go LOW if one or more syndrome bits are
asserted. meaning there are one or more bit errors in the data or check bits. If no syndrome bits are asserted. there are no errors
detected and the output will be HIGH. In Generate mode. ~ is forced HIGH. (In a 54-bit configuration. rnm5J1 must be
implemented externally.)
MOLT ERROR
0
Multiple Errors Detected output. When the EDC is in Detect or Correct mode this output. if LOW. indicates thatthere are two or
more bit errors that have been detected. If HIGH. this indicates that either one or no errors have been detected. In Generate
mode. MOC'f ERROR is forced HIGH. (In a 64-bit configuration. NiOCT ERROR must be implemented externally.)
CORRECT
I
Correct input. When HIGH. this signal allows the correction network to correct any single-bit error in the Data Input Latch (by
complementing the bit-in-error) before putting it into the Data Output Latch. When LOW. the EDC will drive data directly from
the Data Input Latch to the Data Output Latch without correction.
LEoUT
I
Latch Enable - Data Output Latch. Controls the latching of the Data Output Latch. When LOW. the Data Output Latch is latched
to its previous state. When HI GH. the Data Output Latch follows the output of the Data Input Latch as modified by the correction
logic network. In Correct mode. single-bit errors are corrected by the network before loading into the Data Output Latch. In
Detect mode. the contents of the Data Input Latch are passed through the correction network unctlanged into the Data Output
Latch. The inputs to the Data Output Latch are disabled with its contents unchanged if the EDC is in Generate mode.
or BYTEo
or BYTE 1
I
Output Enable - Bytes 0 and 1. Data Output Latch. These lines control the 3-state outputs for each ofthe two bytes ofthe Data
Output Latch. When LOW. these lines enable the Data Output Latch and. when HIGH. these lines force the Data Output
into the high impedance state. The two enable lines can be separately activated to enable only one byte of the Data Output
ata time.
PASSTHRU
I
Pass Thru input. This line. when HIGH. forces the contents of the Check Bit Input Latch onto the Syndrome/Check Bit outputs
(SCo-e) and the unmodified contents of the Data Input Latch onto the inputs of the Data Output Latch.
DIAG MODEo_1
I
Diagnostic Mode Select. These two lines control the initialization and diagnostic operation of the EDC.
CODE IDo-2
I
Code Identification inputs. These three bits identify the size of the total data word to be processed and which 16-bit slice of
larger data words a particular EDC is processing. The three allowable data word sizes are 16. 32. and 64 bits and their respective
modified Hamming codes are designated 16/22. 32/39 and 64172. Special CODE ID input 001 (ID2 .ID1. IDol is also used to
instructthe EDC thatthe signals CODE IDo-2. DIAG MODEo-1. CORRECT and PASSTHRU are to be taken from the diagnostic
latch rather than the control lines.
LE DIAG
I
Latch Enable - Diagnostic Latch. The Diagnostic Latch follows the 16-bit data on the input lines when HIGH. When LOW. the
outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch holds diagnostic check bits and internal control signals for CODE IDo-2. DIAG MODEo-l. CORRECT and PASSTHRU.
PIN NAME
DATAo- 15
S8-58
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
DETAILED PRODUCT DESCRIPTION
The IDT39C60 EDC Unit is a powerful 16-bit cascadable slice
used for check bit generation, error detection, error correction and
diagnostics. As shown in the Functional Block Diagram, the device
consists of the following:
The IDT39C60 EDC Unit contains the logic necessary to generate check bits on a 16-bit data input according to a modified Hamming code. The EDC can compare internally generated check bits
against those read with the 16-bit data to allow correction of any
single bit data error and detection of all double and some triple bit
errors. The IDT39C60 can be used for 16-bit data words (6 check
bits), 32-bit data words (7 check bits) or 64-bit data words (8 check
bits).
-
Data Input Latch
Data Output Latch
Diagnostic Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Control Logic
CODE AND BYTE SELECTION
The 3 code identification pins, 102-0, are used to determine the
data word size from 16, 32 or 64 bits and the byte position of each
16-bit IDT39C60 EDC device.
Code 16/22 refers to a 16-bit data field with 6 check bits.
Code 32/39 refers to a 32-bit data field with 7 check bits.
Code 64/72 refers to a 64-bit data field with 8 check bits.
The 102-0 of 001 is used to place the device in the Internal Control
mode as described later in this section.
Table 1 defines all possible identification codes.
DATA INPUT/OUTPUT/DIAGNOSTIC LATCHES
The LEIN, Latch Enable input, controls the Data Input Latch which
can load 16 bits of data from the bidirectional DATA lines. The
input data is used for either check bit generation or error detection/
correction.
The 16 bits of data from the DATA lines can be loaded into the
Diagnostic Latch under control of the Diagnostic Latch Enable,
LEDIAG, giving check bit information in one byte and control information in the other byte. The Diagnostic Latch is used when in Internal
Control mode or in one of the Diagnostic modes.
The Data Output Latch is split into 2 bytes and enabled onto the
DATA lines through separate byte control lines. The Data Output
Latch stores the result of an error correction operation or is loaded
directly from the Data Input Latch under control of the Latch Enable
Out (LEouT). The PASSTHRU control input determines which data is
loaded.
CHECK AND SYNDROME BITS
The IDT39C60 provides either check bits or syndrome bits on the
three-state output pins SCo-a. Check bits are generated from a
combination of the Data Input bits, while syndrome bits are an Exclusive-OR of the check bits generated from read data with the read
check bits stored with the data. Syndrome bits can be decoded to
determine the single bit in error or that a double error was detected.
Some triple bit errors are also detected. The check bits are labeled:
Co, Cl, C2, C3, C4
for the 8-bit cor,figuration
Co, Cl, C2, C3, C4, Cs
for the 16-bitconfiguration
Co, Cl, C2, C3, C4, Cs, Ca
for the 32-bit configuration
Co, Cl, C2, C3, C4, Cs, Ca, C7
forthe 64-bit configuration
Syndrome bits are similarly labeled So through S7.
CHECK BIT GENERATION LOGIC
This block of combinational logic generates 7 check bits using a
modified Hamming code from the 16 bits of data input from the Data
Input Latch.
SYNDROME GENERATION LOGIC
This logic compares the check bits generated through the Check
Bit Generator with either the check bits in the Check Bit Input Latch
or 7 bits assigned in the Diagnostic Latch.
Syndrome bits are produced by an exclusive-OR of the two sets
of bits. A match indicates no errors. If errors occur, the syndrome
bits can be decoded to indicate the bit in error, whether 2 errors were
detected or 3 or more errors.
ERROR DETECTION/CORRECTION LOGIC
The syndrome bits generated by the Syndrome Logic are decoded and used to control the ERROR and MULT ERROR outputs.
If one or more errors are detected, ERROR goes low. If two or more
errors are detected, both ERROR and MULT ERROR go low. Both
outputs remain high when there are no errors detected.
For single bit errors, the correction logic will complement (correct) the bit in error, which can then be loaded into the Data Out
Latches under the LEouT control. If check bit errors need to be corrected, then the device must be operated in the Generate mode.
, CONTROL LOGIC
The control logic determines the specific mode of operation, usually from external control signals. However, the Internal Control
mode allows these signals to be provided from the Diagnostic
Latch.
CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the IDT39C60.
The Diagnostic mode pins, DIAG MODE1-0, define 4 basic areas of
operation, with GENERATE, CORRECT and PASSTHRU, further
dividing operation into 8 functions with the 102-0 defining the ninth
mode as the Internal mode.
Generate mode is used to display the check bits on the outputs
SCo-a. The Diagnostic Generate mode displays check bits as stored
in the Diagnostic Latch.
Detect mode provides an indication of errors or multiple errors on
the outputs ERROR and MULT ERROR. Single bit errors are not
corrected in this mode. The syndrome bits are provided on the outputs SCo-a. For the Diagnostic Detect mode, the syndrome bits are
generated by comparing the internally generated check bits from
the Data In Latch with check bits stored in the diagnostic latch rather
than with the check bit latch contents.
Correct mode is similar to the Detect mode except that single bit
errors will be complemented (corrected) and made available as input to the Data Out Latch. Again, the Diagnostic Correct mode will
correct single bit errors as determined by syndrome bits generated
from the Data Input and contents of the Diagnostic Latch.
The Initialize mode provides check bits for all zero bit data. Data
In Latch is set and latched to a logic zero and made available as
input to the Data Out Latch.
The Internal mode disables the external control pins DIAG
MODE1-0, CORRECT, PASSTHRU and CODE 10 to be defined by
the Diagnostic Latch. When in the internal control mode, the data
loaded into the diagnostic latch should have the CODE 10 different from 001 as this would represent an invalid operation.
sa-59
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 2.
DIAGNOSTIC MODE CONTROL
TABLE 1.
HAMMING CODE AND SLICE IDENTIFICATION
CODE
102
CODE
ID1
CODE
100
HAMMING CODE
AND SLICE SELECTED
DIAG
MODE1
DIAG
MODEo
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 16/22
Internal Control Mode
Code 32/39, Bytes 0 and 1
Code 32/39, Bytes 2 and 3
Code 64f72, Bytes 0 and 1
Code 64f72, Bytes 2 and 3
. Code 64f72, Bytes 4 and 5
Code 64f72, Bytes 6 and 7
0
0
Non·diagnostlc mode. The EDC functions
normally in all modes.
0
1
Diagnostic Generate. The contents of the
Diagnostic Latch are substituted for the
normally generated check bits when in the
Generate mode. The EDCfunctions normally in
the Detect or Correct modes.
1
0
Diagnostic Detect/Correct In the Detect or
Correct mode, the contents of the Diagnostic
Latch are substituted forthe check bits normally
read from the Check Bit Input Latch. The EDC
functions normally in the Generate mode.
1
Initialize. The outputs of the Data Input Latch
are forced to zeroes and the check bits gener·
ated correspond to the all zero data. The latch is
not reset. a functional difference from the
Am2960.
1
DIAGNOSTIC MODE SELECTED
TABLE 3.
IDT39C60 OPERATING MODES
OPERATING
MODE
GEf\JERATE
PASS·
CORRECT THRU
DM1
DMO
Generate
0
1
0
0
Detect
0
0
0
1
1
0
0
Correct
0
0
0
1
1
1
PASSTHRU
0
0
1
0
1
0
X
Diagnostic Generate
0
1
0
Diagnostic Detect
Diagnostic Correct
Initialization Mode
Internal Mode
1
1
1
0
0
1
0
1
1
X
X
DATA OUT LATCH
(LEoUT = HIGH)
SCO-8
(01: sc = LOW)
-
Check Bits Generated from Data
In Latch
0
~
MOCT
ERROR
High
Data In Latch
Syndrome Bits Data In/Check
Bit Latch
Error Dep(1)
0
Data In Latch with
Single Bit Correction
Syndrome Bits Data In/Check
Bit Latch
ErrorDep
X
1
Data In Latch
Check Bit Latch
High
X
0
Check Bits from Diagnostic Latch
High
Error Dep
0
1
X
-
0
Data In Latch
Syndrome Bits Data In/Diagnostic
Latch
0
Data In Latch with
Single Bit Correction
Syndrome Bits Data In/Diagnostic
Latch
Error Dep
X
Data In Latch
Set to 0000
Check Bits Generated from Data
In Latch (0000)
-
102-0 = 001 (Control Signals 102-0, DIAG MODE1-Q, CORRECT and PASSTHRU
are taken from the Diagnostic Latch)
NOTE:
1. ERROR DEP (Error Dependent): ~ will be low for Single or multiple errors, with MuLt
for no errors.
S8-60
ERROR low for double or multiple errors. Both signals are high
IDT39C60/-1/AIB 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A single IDT39C60 EDC Unit, connected as shown in Figure 2,
provides all logic needed for single bit error correction and double
bit error detection of a 16-bit data field. The identification code 16/22
indicated 6 check bits are required. The CBs pin is, therefore, a
"Don't Care" and 102, 101, 100 = 000.
16-BIT DATA WORD CONFIGURATION
Figure 1 indicates the 22-blt data format for two bytes of data and
6 check bits.
DATA
BYTEl
15
I
BYTEo
87
I
Co
0
USES MODIFIED HAMMING CODE 16/22
16 DATA BITS WITH 6 CHECK BITS
Figure 1. 16-Bit Data Format
INPUT CHECK BITS
FOR 16-81T CONFIGURATION
~-------------------~-------------T-I-E-T-O'\
Co
DATAo--1S
Cl
C2
C3
C4
Cs
IDT39C60 EDC
Vee
000
CODE ID
--------------'y-----------------------,)
SYNDROME/CHECK BIT OUTPUTS
Figure 2. 16-Bit Configuration
Table 4 indicates the data bits participating in the check bit generation. For example, check bit CO is the Exclusive-OR function or
the 8 data input bits marked with an X. Check bits are generated and
output in the Generate and Initialization mode. Check bits are
passed as stored in the PASSTHRU or Diagnostic Generate mode.
Table 3 describes the operating modes available. The output pin
SCa, is forced high for either syndrome or check bits since only
6 check bits are used for the 16/22 code.
TABLE 4. 16-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART(l)
I
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
PARTICIPATING DATA BITS
0
Cl
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
1
2
3
X
X
X
X
X
4
5
X
X
7
X
X
X
8
9
X
X
X
X
X
X
6
X
X
X
X
X
X
X
X
11
X
12
13
X
X
X
X
10
15
X
X
X
X
14
X
X
X
X
X
X
X
X
X
X
X
X
NOTE:
1. The check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X· in the table.
Syndrome bits are generated by an Exclusive-OR of the generated check bits with the read check bits. For example, SX is the XOR
of check bits CX from those read with those generated. Table 5
indicates the decoding of the six syndrome bits to indicate the bit in
error for a single bit error or whether a double or triple bit error was
detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple error
detection, the data available as input to the Data Out Latch is not
defined.
Table 6 defines the bit definition for the Diagnostic Latch. As defined in Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCo-s
outputs. The Internal mode substitutes the indicated bit position for
the external control signals.
S8-61
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 6.
DIAGNOSTIC LATCH LOADING-16-BIT FORMAT
TABLE 5.
SYNDROME DECODE TO BIT-IN-ERROR
(16-BIT CONFIGURATION)
I
SYNDROME
BITS
r--
HEX S3
DATA BIT
INTERNAL FUNCTION
HEX
0
1
2
3
0
Diagnostic Check Bito
S5
S4
0
0
0
1
1
0
1
1
1
Diagnostic Check Bit1
2
Diagnostic Check Bit2
S2
S1
So
0
*
C4
C5
T
3
Diagnostic Check Bit3
4
Diagnostic Check Bit4
0
0
0
0
1
0
0
0
1
CO
T
T
14
5
2
0
0
1
0
C1
T
T
M
6,7
Diagnostic Check Bit 5
Don't Care
3
0
0
1
1
T
2
8
T
8
CODE IDo
4
0
1
0
0
C2
T
T
15
9
CODE ID1
5
0
1
0
1
T
4
10
T
10
CODE ID2
6
0
1
1
0
T
3
9
T
11
DIAG MODE o
DIAG MODE1
7
0
1
1
1
M
T
T
M
12
8
1
0
0
0
C3
T
T
M
13
CORRECT
9
1
0
0
1
T
5
11
T
14
PASS THRU
A
1
0
1
0
T
6
12
T
15
Don't Care
B
1
0
1
1
1
T
T
M
C
1
1
0
0
T
7
13
T
D
1
1
0
1
0
T
T
M
E
1
1
1
0
M
T
T
M
F
1
1
1
1
T
M
M
T
NOTES:
* = No errors detected
# = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected
DATA
m= BYTE 1
m= SIGNAL - - - - I m= BYTE 0
CHECK BITS
vcc
IDT39C60
MOLt ERROR
SCO-4
SYNDROMES/
CHECK BITS
Figure 3. 8-Blt Configuration
S8-62
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT DATA WORD CONFIGURATION
Two IDT39C60 EDC Units, connected as shown in Figure 5, provide all logic needed for single bit error correction and double bit
error detection of a 32-bit data field. The Identification code 32/39
indicates 7 check bits are required. Table 1 gives the ID2, ID1, IDo
values needed for distinguishin~e 0/1 from byte 2/3. Valid
syndrome, check bits and the ERROR and MULT ERROR signal
come from the byte 2/3 unit. Control signals not indicated are connected to both units in parallel. The OEsc always enables the SCO-6
outputs of byte 0/1, but must be used to select data check bits or
syndrome bits fed back from the byte 2/3 for data correction modes.
Data In bits 0 through 15 are connected to the same numbered
inputs of the byte 0/1 EDC unit, while Data In bits 16 through 31 are
connected to byte 2/3 Data Inputs 0 to 15, respectively.
Figure 4 indicates the 39-bit data format of 4 bytes of data and
7 check bits. Check bits are input to the byte 0/1 unit through a
tri-state buffer unit such as the IDT74FCT244. Correction of single
bit errors of the 32-bit configuration requires a feedback of syndrome bits from byte 2/3 into the byte 1/0 unit. The MUX shown on
the functional block diagram is used to select the CBo-6 pins as the
syndrome bits rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 32/39
configuration.
Syndrome bits are generated by an Exclusive-OR of the generated check bits with the read check bits. For example, Sn is the XOR
of check bits Cn from those read with those generated. Table 7 indicates the decoding of the 7 syndrome bits to determine the bit in
error for a single bit error or whether a double or triple bit error was
detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple error
detection, the data available as input to the Data Out Latch is not
defined.
Performance data is provided in Table 8 in relating a single
IDT39C60 EDC with the two cascaded units of Figure 5. As indicated, a summation of propagation delays is required from the cascading arrangement of EDC units.
Table 9 defines the bit definition for the Diagnostic Latch. As
defined in Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCO-6 outputs. The Internal mode substitutes the indicated bit position for the
.
external control signals.
Table 10 indicates the Data Bits participating in the check bit
generation. For example, check bit Co is the Exclusive-OR function
of the 16 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization mode. Check bits are
passed as stored in the PASSTHRU or Diagnostic Generate mode.
TABLE 7.
SYNDROME DECODE TO BIT-IN-ERROR (32-BIT)
I HEX
S
SYNDROME S:
BITS
S4
r-HEX S3 S2 Sl So
0
0 0 0 0
1615
5
1
0
1
1
1
0
7
1
1
1
6
*
C4
C5
T
C6
T
T
30
0
1
CO
T
T
14
T
M
M
T
2
0
0
1
0
C1
T
T
M
T
2
24
T
3
0
0
1
1
T
18
8
T
M
T
T
M
4
0
1
0
0
C2
T
T
15
T
3
25
T
5
0
1
0
1
T
19
9
T
M
T
T
31
6
0
1
1
0
T
20
10
T
M
T
T
M
7
8
0
1
1
0
1
0
1
0
M
T
T
M
M
T
T
4
5
26
27
M
C3
T
T
9
1
0
0
1
T
21
11
T
M
T
T
M
A
1
0
1
0
T
22
12
T
1
T
T
M
B
1
0
1
1
17
T
T
M
T
6
28
T
C
D
1
1
1
1
0
0
0
1
T
13
T
T
M
M
T
T
7
T
29
M
M
23
T
E
1
1
1
0
16
T
T
M
T
M
M
T
1 1 1 1
T
M
T
M
NOTES:
* = No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected
0
T
T
M
T
T
TABLE 8.
KEY AC CALCULATIONS
FOR THE 32-BIT CONFIGURATION
32-BIT
PROPAGATION DELAY
TO
DATA
Check Bits Out
(DATA to SC)
DATA
Corrected
DATA Out
(DATA toSC) + (CBtoSC, Code ID 011)
(CB to DATA, CODE ID 010)
Syndromes Out (DATA to SC)
~for
32 Bits
(DATA to SC)
011)
+ (CB to SC, CODE ID 011)
+
+ (CB to SC, CODE ID 011)
+ (CB to ~, CODE ID
MOLT ERROR (DATA to SC) + (CB to MOLT ERROR.
for 32 Bits
CHECK BITS
0
USES MODIFIED HAMMING CODE 32/39
32 DATA BITS WITH 7 CHECK BITS
Figure 4. 32-Bit Data Format
S8-63
COMPONENT DELAY
FROM IDT39C60
AC SPECIFICATIONS
FROM
BYTE 0 1 Co
8 7
4
1
0
0
F
DATA
24 23
3
0
1
1
0
DATA
31
2
0
1
0
0
DATA
BYTE 1
1
0
0
1
1
DATA
BYTE 3 1 BYTE 21
0
0
0
0
CODE ID 011)
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
DATA 16-31
DATAo-1S
~
'Co
-.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 9.
DIAGNOSTIC LATCH LOADING-32-BIT FORMAT
INPUT C~ECK BITS
r - - - ,
Cl C 2 C3 C4 C s Ce
' I 1/8 OF I
I
IIDTFCT240
I
-.
I
I
I
~
I'\7 V V '\7'\7 V '\7
1
L. _ _ _ J
ID174FCT244
t---
DATA
CBo CB l CB 2 CB 3 CB 4 CBs CBe
IDT39C60 EDC
BYTE OAND 1
Ol:sc
Il-
CODE ID I-010
SC o SC l SC 2 SC 3 SC 4 SC SC e
s
"------J
DATA
CBo CB l CB 2 CB 3 CB 4 CBs CB 6
IDT39C60 EDC
BYTE 2AND 3
Ci'E"sc
CODE ID I-011
SC o SC l SC 2 SC3 SC 4 SCs SC e
MOLt ERROR
rnROl=l
Jml
DATA BIT
INTERNAL FUNCTION
0
Diagnostic Check Bito
1
Diagnostic Check Bitl
Ol:sc
~
MOLt ERROR
2
Diagnostic Check Bit2
3
Diagnostic Check Bit3 '
4
Diagnostic Check Bit4
5
Diagnostic Check Bits
6
Diagnostic Check Bite
7
Don't Care
8
Slice 0/1 - CODE IDo
9
Slice 0/1-CODE IDl
10
Slice 0/1-CODE ID2
11
12
Slice 0/1-DIAG MODE o
Slice 0/1-DIAG MODE 1
13
Slice 0/1-CORRECT
14
Slice 0/1- PASSTHRU
15
Don't Care
16-23
Don't Care
24
Slice 2/3-CODE IDo
25
Slice 2/3-CODE IDl
26
Slice 2/3-CODE ID2
27
Slice 2/3-DIAG MODE o
Se/Ce
so/Co
S2/C 2
S4/C 4
\..
Sl/Cl
S3/C3
Ss/Cs
/
28
Slice 2/3-DIAG MODE 1
"V""'"
29
Slic~2/3-CORRECT
SYNDROME/CHECK BIT OUTPUTS
30
Slice 2/3-PASS THRU
31
Don't Care
Figure 5. 32-Bit Configuration
TABLE 10. 32-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART
PARTICIPATING DATA BITS
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
Cl
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
0
2
3
X
C4
Even (XOR)
Cs
Ce
Even (XOR)
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
Cl
Even (XOR)
X
Even (XOR) ,
1
X
X
X
6
7
8
9
X
X
X
X
X
X
X
4
X
X
X
X
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
X
X
X
X
X
X
11
X
12
13
X
X
X
X
10
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
30
31
X
PARTICIPATING DATA BITS
X
X
22
23
24
25
X
X
X
X
X
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
X
X
Ce
Even (XOR)
X
X
X
X
X
X
S8-64
X
X
X
X
X
X
28
29
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IDT39C60/-1/AIB H)-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Syndrome bits are generated by an Exclusive-OR of !he generated check bits with the read check bits. For example, Sn IS the XOR
of check bits Cn from those read with those generated._ Table 11
indicates the decoding of the 8 syndrome bits to determine the
bit in error for a single bit error or whether a double or triple bit error
was detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple error
detection, the data available as input to the Data Out Latch is not
defined.
Performance data is provided in Table 12 in relating a single
IDT39C60 EDC with the four units of Figure 7. Delay through the
Exclusive-OR gates and the 3-state buffer must be Included.
Table 13 indicates the Data Bits participating in the check bit
generation. For example, check bit Co is the Exclusive-OR function
of the 32 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization mode. In the
PASSTHRU mode, the contents of the check bit latch are passed
through the external Exclusive-OR gates and appear inverted at
the outputs labeled Co to C7.
Table 14 defines the bit definition for the Diagnostic Latch.As
defined in Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCo-a outputs. The Internal control mode substitutes the indicated bit pOSition
for the external control signals.
64-BIT DATA WORD CONFIGURATION
The IDT39C60 EDC Units connected with the MSI gates, as
shown in Figure 6, provide the logic needed for single bit error correction and double bit error detection of a 64-bit data field. The Identification code 64/72 is used, indicating 8 check bits are required.
Check bits and Syndrome bits are generated external to the
IDT39C60 EDC using Exclusive-OR gates. For error correction, the
syndrome bits must be fed back to the CBo-a inputs. Thus, external
tri-state buffers are used to select between the check bits read in
from memory and the syndrome bits being fed back.
The ERROR signal is low for one or more errors detected. From
any of the 4 devices, MULT ERROR is low for some double bit errors
and for all three bit errors. Both are high otherwise. The DOUBLE
ERROR signal is high only when a double bit error is detected.
Figure 6 indicates the 72-bit data format of eight bytes of data and
8 check bits. Check bits are input to the various units through a
tri-state buffer such as the IDT74FCT244. Correction of single bit
errors of the 64-bit configuration requires a feedback of syndrome
bits as generated external to the IDT39C60 EDC; The MUX ~hown
on the functional block diagram is used to select the CBo-a pins as
the syndrome bits rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 64/72
configuration.
USES MODIFIED HAMMING CODE 64/72
64 DATA BITS WITH 8 CHECK BITS
Figure 6. 64-Bit Data Format
TABLE 11. SYNDROME DECODE TO BIT-IN-ERROR (64-BIT CONFIGURATION)
r HEX
r--
HEX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
S7
SYNDROME S8
BITS
S5
S4
S3 S2 S1 So
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0
0
0
1
1
1
1
1
1
1
0
0
00
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
1
0
1
0
F
1 1 1 1
NOTE:
* = No errors detected. T
0
0
0
0
0
0
0
0
1
2
0
0
1
0
1
0
0
1
1
4
0
1
0
0
3
7
0
8
9
A
B
C
D
1
1
1
1
0
1
1
0
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
6
0
1
5
0
*
C4
C5
T
C6
T
T
62
C7
T
T
46
T
CO
C1
T
C2
T
T
T
18
T
19
T
T
8
T
9
14
M
T
15
T
T
T
M
T
M
M
M
56
T
57
T
T
T
M
T
M
34
T
35
T
T
T
50
T
51
T
M
40
T
41
T
T
T
M
M
M
T
T
47
M
T
10
T
T
11
12
T
13
T
M
M
T
T
M
T
T
T
M
33
T
M
T
36
37
T
T
38
T
T
58
59
T
T
60
T
M
C3
T
T
17
T
20
T
T
21
22
T
23
49
T
M
T
52
53
T
T
54
T
T
42
43
T
T
44
T
M
16
T
T
T
M
T
T
M
M
M
T
T
T
32
39
M
T
61
M
T
T
T
T
T
48
55
M
T
45
M
T
M
M
= Two errors detected.
Number
M
T
63
T
T
M
M
T
M
M
M
M
T
T
M
= The number of the single bit-In-error.
S8-65
--------------------------
M
M
T
T
M
M
T
M
T
T
M
0
1
T
T
M
M
T
T
1
T
M
0
T
(.,
M
T
T
2
T
3
4
T
T
5
6
T
7
T
T
M
= Three or more errors detected
E
1
F
1
1
1
0
1
1
1
M
T
T
T
24
T
25
30
26
T
T
27
28
T
29
T
T
M
M
T
31
T
T
M
M
T
T
M
T
M
M
T
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
OE"sc
IDT74FCT244
rI
-~
~I
~ "f'<
MILITARY AND COMMERCIAL TEMPERATURE RANGES
063-48
~
047-32
~S ~413~2~1 ~o~~S -0
031-16
"'\ "'\/"'\/""'\/""\/'\
16
16
16
16
111
I
~1-11
~I
:rirc
I~
I
IL I--_.J
CBe CBS CB4 C~ CB2 CBl CBo 0
CBe CBs CB4 c~ c~ CBl CBo 0
J-=
OE"sc
r
~
IOT39C60
BYTE 6 ANO 7
sc,sc,sc, sc, SO, sc,
I'
Ib-= OE"sc BYTE
IDT39C60
4 AND 5
CBe CBS CB4 C~ CB2 CBl CBo 0
u;:
-=
so6SOSSC4 SC3 SC2 SCI sCo
OE"sc
CBe CBS CB4 C~ C~ C~ CBo 0
J OE"sc
IDT39C60
BYTE 2AND 3
-
SC6 sCs SC4 SC3 SC2 SC I SOo
IDT39C60
BYTE 0 AND 1
S06 SOSSC4 SC3 SC2 SCI SOo
I
l\ID[T
~
L---
'---
I
:U~
1
S 4 /C 4
:U~
'{9XOR
'{9XOR
'{9XOR
\!S4 /C 4
_\!Ss/Cs
S3/C3
Jl
XOR
Ss/C 5
I
~I
I I
1
S3/C3
'{9XOR
Sa/Ca
S IC
a a
L..I..'F
NORt~
~OR
S2/C2
S2/C2
-Jil
\{9XOR
SllC7
S7/C7
0
NOR
~
DOUBLE ERROR
NOTES.
1. In PASSTHRU mode the contents of the Check Latch appear on the XOR outputs inverted.
2. In Diagnostic Generate mode the contents of the Diagnostic Latch appear on the XOR outputs inverted.
Figure 7. 64-Bit Configuration
TABLE 12. KEY AC CALCULATIONS FOR THE
64-BIT CONFIGURATION
64-BIT
PROPAGATION DELAY
COMPONENT DELAY
FROM IDT39C60
AC SPECIFICATIONS
FROM
TO
DATA
Check Bits Out
(DATA to SC)
DATA
Corrected
DATA Out
(DATA to SC) + (XOR Delay) + (Buffer
DELAY) + (CB to DATA, CODE ID 1xx)
DATA
DATA
Syndromes
(DATA to SC)
~for
(DATA to SC)
Delay)
64-Bits
+
+
+
(XOR Delay)
(XOR Delay)
(XOR Delay)
+
(NOR
DATA
for 64-Bits
MOLT ERROR
(DATA to SC) + (XOR Delay) + (Buffer
Delay) + (CB to MOLT ERROR, CODE
ID 1xx)
DATA
DOUBLE
ERROR for
64-Bits
(DATA to SC) + (XOR Delay)
(XOR/NOR Delay)'
+
S8-66
:
t-
\{9XOR
Sl /C l
Sl /C l
~
XOR~
So/C o
So/C o
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 13 64-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART (1)
PARTICIPATING DATA BITS
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
C1
Even (XOR)
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
Ce
Even (XOR)
X
X
X
X
X
X
X
X
C7
Even (XOR)
X
X
X
X
X
X
X
X
GENERATED
CHECK BITS
PARITY
16
17
18
19
20
21
Co
Even (XOR)
X
X
X
X
X
0
X
1
2
3
X
X
X
X
X
4
X
X
6
7
X
X
X
X
8
9
X
X
X
X
X
X
X
X
X
X
10
11
X
12
13
X
X
X
X
X
X
X
5
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
28
29
30
31
PARTICIPATING DATA BITS
22
23
X
X
X
24
25
X
X
X
X
Cl
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ce
Even (XOR)
X
X
X
X
X
X
X
X
C7
Even (XOR)
X
X
X
X
X
X
X
X
GENERATED
CHECK BITS
PARITY
42
43
46
47
Co
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
PARTICIPATING DATA BITS
32
Ce
Even (XOR)
C7
Even (XOR)
GENERATED
CHECK BITS
PARITY
X
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
Even (XOR)
Even (XOR)
Ce
Even (XOR)
C7
Even (XOR)
35
X
X
38
39
X
X
X
X
X
36
X
X
X
X
X
X
37
X
X
40
X
X
X
X
X
X
X
X
X
X
41
X
44
45
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
58
59
60
61
62
63
X
X
X
X
X
X
X
X
X
PARTICIPATING DATA BITS
Co
Cs
X
34
X
48
C4
33
49
50
X
X
X
52
54
55
X
X
X
X
X
X
X
X
X
53
X
X
56
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTE:
1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an ·X· in the table.
S8-67
57
X
X
X
X
X
X
51
IDT39C60/-1/A/B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 14.
DIAGNOSTIC LATCH LOADING-64-BIT FORMAT
DATA BIT
INTERNAL FUNCTION
DATA BIT
0
Diagnostic Check Bit 0
31
Don't Care
1
Diagnostic Check Bit 1
32-37
Don't Care
2
Diagnostic Check Bit 2
38
3
Diagnostic Check Bit3
39
Don't Care
4
Diagnostic Check Bit 4
40
Slice 4/5-CODE IDo
5
Diagnostic Check Bits
41
Slice 4/5-CODE ID1
Don't Care
42
Slice 4/5-CODE ID2
8
Slice 0/1 - CODE IDo
43
Slice 4/5 - DIAG MODEo
9
Slice O/1-CODE IDl
44
Slice 4/5-DIAG MODEl
10
Slice 0/1 - CODE ID2
45
Slice 4/5-CORRECT
11
Slice O/1-DIAG MODE o
46
Slice 4/5- PASSTHRU
12
Slice O/l-DIAG MODEl
47
Don't Care
13
Slice O/1-CORRECT
48-54
14
Slice 0/1 - PASSTHRU
55
6,7
INTERNAL FUNCTION
Diagnostic Check Bite
Don't Care
Diagnostic Check Bit7
15
Don't Care
56
Slice 6/7 - CODE IDo
16-23
Don't Care
57
Slice 6/7-CODE IDl
24
Slice 2/3-CODE IDo
58
Slice 6/7-CODE ID2
25
Slice 2/3-CODE IDl
59
Slice 6/7 - DIAG MODEo
26
Slice 2/3-CODE ID2
60
Slice 6/7 - DIAG MODE 1
27
Slice 2/3-DIAG MODEo
61
Slice 6/7 -CORRECT
28
Slice 2/3-DIAG MODEl
62
Slice 6/7 - PASSTHRU
29
Slice 2/3-CORRECT
63
Don't Care
30
Slice 2/3-PASSTHRU
Some multiple errors will cause a data bit to be inverted. For
example. In the 16·blt mode where bits 8 and 13 are in error. the
syndrome 111100 (So. ~. ~ S3 S4. Ss) is produced. The bit·ln-error
decoder receives the syndrome 11100 (So. Sl. ~ Ss. SJ which it
decodes as a single error in data bit 0 and inverts that bit. Figure 8
indicates a method for Inhibiting correction when a multiple error
occurs.
DATA
CHECK BITS
·IDT39C60
Figure 8. Inhibition of Data Modification
S8-68
CORRECT
IOT39C60/-1/A1B H).. BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
the value of the inputs and the intemal states. Be sure to carefully
read the following definitions of symbols before examining the
tables.
FUNCTIONAL EQUATIONS
The following equations and tables describe in detail how the
output values of the IDT39C60 EDC are determined as a function of
DEFINITIONS
DI
-+- DATAl if LE IN is HIGH or the output of bit i of the Data Input Latch if LE IN is LOW
C I -+- CB I if LEIN is HIGH or the output of bit i of the Check Bit Latch if LE IN is LOW
DLI -+- Output of bit I of the Diagnostic Latch
SI
-+- Intemallygenerated syndromes (same as outputs of SCI if outputs enabled)
PA -+- Do e Dl e D2 e 0 4 e De e D8 e 010e 0 12
PB -+- Do e 0 1 e D2 e 0 3e D4 e Ds e De e D7
PC -+- D8 e Og e 010e 0,1 e 0,2 e 013e 0 14
PD -+- Do e ~ e 0 4 e 0 7e 0 9 e D10 e D13 e D15
PE -+- Do e 0 1 e D5 e Dee 0 7 e Dll e 012e 0 13
PF -+- 02e D3e 04e D 5e Dae o14 e D15
PG 1 -+- 0 1 e D4 e Oa e 0 7
PG 2 -+- Dl e D2 e 0 3 e D5
PG3 -+- 0 8 e De e Dll e 0 14
PG 4 -+- D 10 e D 12 e 013e D 15
Error Signals
~: -+- (S6. (101 + 10 2 )) • "SO. &l . ~ . 52 • 51 • SO + GENERATE + INITIALIZE + PASSTHRU
MOLT ERROR:
(16 and 32..Bit Modes) -+- ((S6· 10 1 ) E6 S5 E6 S4 E6 S3 S2 E6 S1 E6 SO) (ERROR) + TOME + GENERATE
MOLT ERROR: (64.. Bit Modes) -+- ~ + GENERATE + PASSTHRU + INITIALIZE
e
+ PASSTHRU + INITIALIZE
TABLE 15. TOME (THREE OR MORE ERRORS)(1)
I
HEX
0
0
0
0
0
Sa
HEX
SYNDROME(2) 55
BITS
S4
S3
52 ~ So
0
8
0
0
0
1
9
0
0
1
2
A
0
1
0
3
B
0
1
1
4
C
1
0
0
5
0
1
0
1
2
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
3
0
1
0
1
4
0
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
6
7
1
1
1
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
F
1
1
1
1
1
1
1
1
1
1
NOTES:
1. 56,55, ... SO are internal syndromes except in Modes 010,100,101,110,111 (CODE 102, 101, 100}·ln these modes, the syndromes are input over the
check bit lines. 56 -+- C6, 55 -+- C5, ... S1 -+- C1, SO -+- CO.
2. The 56 internal syndrome is always forced to 0 in CODE 10 000.
6
E
7
SC OUTPUTS
Tables 16. 17. 18. 19.20 show how outputs SCo-e are generated in each control mode for various CODE IDs (internal control mode not
applicable).
TABLE 16. GENERATE MODE (Check Bits)
GENERATE
MODE (CHECK BITS)
500 -+-
CODE 102.. 0
100
000
010
011
PG 2 e PG 3
PG 1e PG 3
PG 2 e PG 4
e CBo
SCI -+-
PA
PA
PA e CBl
5C2 -+-
J5I5
J5I5
PG 2 e PG 3
101
PG 2 e PG 3
110
111
PG 1e PG 4
PG 1e PG 4
PA
PA
PA
PA
m
PO
PO
PO
PE
5C3 -+-
J5E
J5E
PO e CB2
PE e C B3
J5E
PE
PE
SC4 -+-
PF
PF
PF e CB4
PF
PF
PF
PF
SC5 -+-
PC
PC
PC e CB5
PC
PC
PC
PC
SCa -+-
1
PB
PC e CBa
PB
PB
PB
PB
S8-69
IDT39C60/-1/A/B 16·81T CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 17. DETECT AND CORRECT MODES (Syndromes)
DETECT AND CORRECT
MODES (SYNDROMES)
SC o +-
011
(1)
000
010
PG2 ffi PG 3
ffi CO
PG 1 ffi PG 3
ffi CO
PG 2 ffi PG 4
ffi CBo
CODE ID2-0
100
PG 2 ffi PG 3
ffi CO
101
110
111
PG 2 ffi PG 3
PG 1 ffi PG 4
PG 1 ffi PG 4
SCI +-
PA ffi Cl
PA ffi Cl
PA ffi CBl
PA ffi Cl
PA
PA
PA
SC2 +-
~ffi C2
~ffi C2
PD ffi CB2
~ffi C2
PD
PD
PD
PE
SC3 +-
~ffi C3
~ffi C3
PE ffi CB3
~ffi C3
PE
PE
SC4 +-
PF ffi C4
PF ffi C4
PF ffi CB4
PF ffi C4
PF
PF
PF
SCs +-
PC ffi C5
PC ffi C5
PC ffi CBs
PC ffi C5
PC
PC
PC
PB
PB ffi C6
PB ffi C6
PB
SCe +1
PB ffi C6
PC ffi CBe
NOTE:
1. In CODE ID2- o 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
TABLE 18 DIAGNOSTIC DETECT AND CORRECT MODE
DIAGNOSTIC
DETECT AND CORRECT
MODE
SC o +-
CODE ID2-0
000
010
PG2 ffi PG 3
ffi OLo
PG 1 ffi PG 3
ffi OLo
011
(1)
PG 2 ffi PG 4
ffi CBo
100
101
110
111
PG 2 ffi PG 3
ffi OLo
PG 2 ffi PG 3
PG 1 ffi PG 4
PG 1 ffi PG 4
SCl +-
PA ffi OLl
PA ffi OLI
PA ffi CBl
PA ffi OLI
PA
PA
PA
SC2 +-
~ffi OL2
fSD ffi OL2
PD ffi CB2
J5D ffi OL2
PD
PD
PD
SC3 +-
~
OL3
J5E ffi OL3
PE ffi CB3
PE" ffi
OL 3
PE
PE
PE
SC4 +-
PF ffi OL4
PF ffi OL4
PF ffi CB4
PF ffi OL4
PF
PF
PF
SCs +-
PC ffi OLs
PC ffi OLs
PC ffi CBs
PC ffi OLs
PC
PC
PC
PB
PB ffi OLe
PB ffi OL7
ffi
PB
SCe +1
PC ffi CBe
PBffiOLe
NOTE:
1. In CODE ID2_0 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
TABLE 19. DIAGNOSTIC GENERATE MODE
DIAGNOSTIC
GENERATE MODE
CODE ID2-0
000
010
011
100
101
110
111
SCo +-
DLo
DLo
CBo
DLo
1
1
1
SCl +-
DLI
DLI
CBl
DLl
1
1
1
SC2 +-
DL2
DL2
CB2
DL2
1
1
1
SC 3 +-
DL3
DL3
CB 3
DL3
1
1
1
SC 4 +-
DL4
DL4
CB 4
DL4
1
1
1
SC s +-
DLs
DLs
CBs
DLs
1
1
1
DLe
CBe
1
1
DLe
DL7
101
110
111
SC e +-
1
(1)
NOTE:
1. In CODE ID2- 0 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
TABLE 20. PASSTHRU MODE
PASSTHRU
MODE
011
(1)
CODE ID2-0
100
000
010
SCo +-
Co
Co
CBo
Co
1
1
1
SCI +-
C1
Cl
CB 1
C1
1
1
1
1
SC2 +-
C2
C2
CB2
C2
1
1
SC 3 +-
C3
C3
CB 3
C3
1
1
1
SC 4 +-
C4
C4
CB 4
C4
1
1
1
SC s +-
Cs
Cs
1
1
1
1
Cs
Ce
CBs
SC e +-
CBe
1
1
Ca
Ca
NOTE:
1. In CODE ID 2- o 011 the Check Bit Latch is forced transparent; the Data Latch operates normally.
58-70
IDT39C60/-1/A/B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
TABLE 21. CODE 102-0
52
51
0
0
0
1
1
0
1
S5
S4
53
0
0
0
-
-
1
0
0
= 000
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 22. CODE 102-0
(1)
0
0
1
1
1
0
0
0
1
0
1
1
1
-
11
14
-
1
0
1
1
-
-
5
1
1
1
2
6
8
12
-
-
3
7
9
13
15
0
4
-
10
-
-
C6
Cs
C4
TABLE 23. CODE 102-0
52
51
0
0
0
1
1
0
1
1
56
55
54
53
= 011
0
1
1
1
1
0
1
1
1
1
-
11
14
8
12
-
-
0
0
1
0
0
0
1
1
1
1
1
1
0
0
-
-
-
5
1
2
6
C2
C1
0
0
0
1
1
0
1
1
0
0
0
0
-
3
7
9
13
15
0
4
-
10
-
-
0
-
= 101
-
5
2
6
-
3
0
4
1
0
0
-
11
0
1
8
12
-
1
0
9
13
15
1
1
10
-
-
0
0
0
1
0
Co
C6
Cs
C4
C3
14
1
0
0
0
1
0
0
1
1
0
1
0
1
-
-
-
-
5
-
1
2
6
-
3
7
0
4
-
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
1
1
1
0
0
0
0
C2
C1
0
0
-
11
14
-
-
5
1
8
12
-
-
-
-
0
1
2
6
1
0
9
13
15
7
10
-
-
-
3
1
-
-
1
0
4
-
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
TABLE 26. CODE 102-0
(1)
1
1
1
0
0
0
0
C1
(1)
0
1
1
1
NOTE:
1. Unlisted en combinations are no correction.
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
1
TABLE 24. CODE 102-0 = 100 (1)
(1)
0
0
0
1
NOTE:
1. Unlisted S combinations are no correction.
Co
C6
Cs
C4
C3
0
1
= 010
NOTE:
1. Unlisted en combinations are no correction.
0
0
0
0
TABLE 25. CODE 102-0
0
1
C2
-
NOTE:
1. Unlisted S combinations are no correction.
~
0
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
C2
C1
-
11
14
0
12
-
-
0
8
0
1
7
9
13
15
-
1
0
-
10
-
-
-
1
1
Co
C6
C5
C4
C3
= 110
0
1
0
0
1
0
0
0
0
0
1
0
1
0
-
1
(1)
0
1
0
1
0
1
0
-
5
-
11
14
-
2
6
8
12
-
-
3
7
9
13
15
0
4
-
10
-
-
-
1
NOTE:
1. Unlisted en combinations are no correction.
NOTE:
1. Unlisted en combinations are no correction.
TABLE 27. CODE 102-0 = 111
Co
C6
C5
C4
C3
0
1
1
0
0
0
1
1
0
1
1
1
0
1
0
(1)
0
1
1
1
1
C2
C1
0
0
-
11
14
0
1
8
12
-
1
0
9
13
15
-
1
1
10
-
-
-
-
NOTE:
1. Unlisted en combinations are no correction.
58-71
1
1
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
-
-
-
5
1
2
6
0
1
1
-
3
7
0
4
-
IDT39C60/-1/A/B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
30
30
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
VIN = OV
5
pF
VOUT= OV
7
pF
MAX.
UNIT
V
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Vee == 5.0V ± 5% (Commercial)
Vce = 5.0V ± 10% (Military)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
"'IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
"'IL
Input LOW Level
Guaranteed Logic Low Level (4)
-
-
O.S
V
IIH
Input HIGH Current
Vce = Max., "'IN = Vce
-
0.1
5
J.lA
IlL
Input LOW Current
Vce = Max., "'IN = GND
VOH
VOL
loz
Output HIGH Voltage
Output LOW Voltage
Off State (High Impedance)
Output Current
Vcc
VIN
= Min.
= VIH or VIL
Vcc
\'IN
= Min.
= "'IH or"'lL
Vee
= Max.
(4)
= -300J.lA
10H = -6mA MIL.
10H = -6mA COM'L.
10L = 300J.lA
10L = SmA MIL.
10L = 8mA COM'L.
Vo = OV
Vo =Vcc (max.)
10H
-
-0.1
-5
J.lA
VHC
Vee
2.4
4.3
'V
2.4
4.3
-
-
GND
VLC
0.3
0.5
-
0.3
0.5
-
-0.1
-10
-
0.1
10
-20
Vcc = Min., VOUT = OV (3)
Output Short Circuit Current
los
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under DC Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment. Guaranteed by design.
S8-72
-
V
J.lA
mA
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
V,HC - V.CC - 02V
VCC = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)
TEST CONDITIONS
PARAMETER
SYMBOL
= Max.
ICCQ
Quiescent Power Supply Current
(CMOS Inputs)
Vcc
VHC
fop
ICCT
Quiescent Input Power Supply (5)
Current (per Input @ TIL High)
VCC
Dynamic Power Supply Current
Vcc = Max.
VHC :S VIN, \iN :S VLC
Outputs Open. OE = L
ICCD
Icc
Total Power Supply Current
(6)
(1)
:s \iN' \iN
= .Max., \iN = 3.4V, fop = 0
=0
:S VLC
VCC = Max., fop = 10MHz
Outputs Open, OE = L
50% Duty Cycle
\iN = 3.4V, \iN = O.4V
TYP.(2)
MAX.
UNIT
-
3.0
5.0
mA
0.3
0.5
mA/lnput
COM'L.
-
MIL.
5.0
8.5
5.0
7.0
-
53
90
COM'L.
-
53
75
MIL.
-
60
100
COM'L.
-
60
85
MIL.
Vcc = Max., fOf> = 10MHz
Outputs Open, OE = L
50% Duty Cycle
VHC < \iN, VIN < VLC
MIN.
mA/MHz
mA
NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCQ, then dividing by the t.otal number of inputs.
6. Total Supply Current Is the sum of the Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCQ
+
ICCT (NT X DH)
+
ICCD (fop)
DH = Data duty cycle TIL high period (\IN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fop = Operating frequency
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test
environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capaCitor sizes be experimented with. Capacitors should be poSitioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the DUT power pins.
3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupling between power and ground planes Is necessary. The ground
plane must be sustained from the performance board to the DUT
interface board and wiring unused interconnect pins to the
ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a static environment. To allow fortesting
and hardware-induced noise, IDT recommends using VIL :S OV
and VIH ~ 3V for AC tests.
S8-73
IDT39C60/-1/A/B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vcc
ESD
PROTECTION
INPUTS
OUTPUTS
Figure 10. Input Structure (All Inputs)
Figure 11. Output Structure
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
TEST LOAD CIRCUITS
GND t03.0V
Wins
1.5V
1.5V
See Figure 12
TEST
Open Drain
Disable Low
Enable Low
SWITCH
All Other Outputs
Open
Closed
DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to louT of the
Pulse Generator
S8-74
-----"-----------------~
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60B over the commercial operating range of O°C to + 70°C,
with Vcc from 4.75V to 5.25V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC load.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = 50pF
FROM INPUT
DATA o- 15
DATAo-1S
l:'RROR
18
25(1)
18
CBO-6
(CODE 102- 0
000,011)
CB O_6
12
22
MuLT ERROR
SET-UP
TIME
DATA 0-15
LEIN
5
CBO-6
LEIN
5
17
DATA 0-15
LEoUT
FROM INPUT
CBO-6
(CODE 102-0 010,
100,101,110,111)
12
GENERATE
13
(CODE 10010, 100,
101,110,111)
GENERATE
CORRECT
20
DIAG MODE
19
k;
PASSTH 8U):;;\::::;
PASSTHRU
(Not Internal
Control Mode)
16
19
CODE 10 2- 0
22
24
LEIN
(From latched
to transparent)
20
22
DATA 0-15
\\::~...
0
i;::::'·<·
I'·
21
0
26
0
22
0
LEoUT
22
0
LEoUT
22
0
LEoUT
25
0
LEoUT
28
0
LE D1AG
5
3
.<,;;,.
.<:2
LI;;~:":;";;;
CBO-6
16
22
HOLD
TIME
,:.:·.?1\· . : .
LEoUT
(CODE 10000,011)
16
CORRECT
(Not Internal
Control Mode)
DIAG MODE
(Not Internal
Control Mode)
TO
(LATCHING
DATA)
TO OUTPUT
SCO-6
OUTPUT ENABLE/DISABLE TIMES
LEoUT
(From latched
to transparent)
Output disable tests performed with C L = 5pF and measured to
O.5V change of output voltage level.
11
INPUT
28
20
22
33
24
27
OUTPUT
ENABLE
DISABLE
InternaIC6rttr~l>
Mod~iXgbii6t
( FrQm·lhl¢tJ~d
to tran~p¥.~ht)
24
MINIMUM PULSE WIDTHS
11
int~ffi~jlCbntrol
ModEgbATA o_15
(Via Diagnostic
Latch)
24
33
24
27
NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 51ns (fmax = 19.6MHz)
NOTE:
1. DATAIN to Corrected OATAoUT measurement requires timing as shown
below.
IDT39C60B COMMERCIAL-DATAIN TO CORRECTED DATAoUT TIMING
TIMING PARAMETER
FROM
TO
MIN./
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
DATA in Set-up to LE in = Low
DATA in Hold to LE in = Low
Min.
Min.
(Two cycles shown)
LE in = High to DATA out
*
S8-75
= (Memory/System dep~nd~nt)
Max.
(II
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60A over the commercial operating range of O°C to + 70°C,
with Vee from 4.7SV to S.2SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = SOpF
FROM INPUT
DATA o- 15
CBO-6
(CODE ID2-0
000, all)
TO OUTPUT
8CO-6
20
14
DATA 0-15 'ElfRC5R
30(1)
20
25
20
MOLT
23
23
CB O_6
(CODE ID2-0 010,
100,101,110,111)
14
18
20
23
GEf\JERATE
15
25
14
CORRECT
(Not Internal
Control Mode)
-
20
-
DIAG MODE
(Not Internal
Control Mode)
22
25
18
DATA 0-15
LEIN
5
3
CBO-6
LEIN
5
3
DATA 0-15
LEoUT
24
2
LEoUT
21
a
17
CBO-6
(CODE ID ala,
101.110.111)
lOa,
LEoUT
21
a
-
GE:NERAiE
LEoUT
26
CORRECT
LEoUT
22
DIAG MODE
LEoUT
22
PASSTHRU
LEoUT
22
CODE ID2-0
LEoUT
25
LEIN
LEoUT
28
a
a
a
a
a
a
DATAo-15
LEolAG
5
3
21
CODE ID2-0
23
28
25
28
LEIN
(From latched
to transparent)
22
32
22
25
LEoUT
(From latched
to transparent)
-
21
OUTPUT ENABLE/DISABLE TIMES
13
-
Output disable tests performed with CL = SpF and measured to
O.SV change of output voltage level.
-
OUTPUT
ENABLE
DISABLE
DE" BYTEo.
DE" BYTE 1
DATA o- 15
24
21
DE"sc
SCO-6
24
21
INPUT
LE 01AG
(From latched to
transparent; Not
Internal Control
Mode)
22
Internal Control
Mode: LE DIAG
(From latched
to transparent)
28
Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)
HOLD
TIME
all)
22
18
SET-UP
TIME
CBO-6
(CODE ID 000,
PASSTHRU
(Not Internal
Control Mode)
25
TO
(LATCHING
DATA)
FROM INPUT
ERROR
32
38
22
28
25
31
MINIMUM PULSE WIDTHS
I
28
38
28
12
LE 1N • LEoUT' LEolAG
31
NOTES:
Device Mode = "Correct"
System Type = ·Correct Always·
Min. Period = 61ns (fmax = 16.4MHz)
NOTE:
1. DATAIN to Corrected DATAouT measurement requires timing as shown
below.
IDT39C60A COMMERCIAL-DATA IN TO CORRECTED DATA OUT TIMING
(Two cycles shown)
TIMING PARAMETER
TO
FROM
MIN.!
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
Dtr~~7nS~~~t~0 L~Ei~n == L~O:
Min.
Min.
LE in = High to DATA out
* = (Memory/System dependent)
88-76
Max.
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60A over the military operating range of -55 0 C to + 125 oC,
with Vcc from 4.5V to 5.5V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC load.
COMBINATIONAL PROPAGATION DELAYS
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
C L = 50pF
TO OUTPUT
FROM INPUT
DATA o- 15
SC O_6
22
DATA 0-15 ERROR
35(1)
24
27
5
LEIN
5
3
DATA 0-15
LEoUT
27
2
CBO-6
(CODE ID 000,011)
LEoUT
24
0
21
CBO-6
(CODE ID 010, 100,
101,110,111)
LEoUT
24
0
-
GENERAiE(2)
LEoUT
29
0
CORRECT
LEoUT
25
0
DIAG MODE
LEoUT
25
0
PASSTHRU
LEoUT
25
0
CODE ID2-0
LEoUT
28
0
LEIN
LEoUT
30
0
DATA 0-15
LEolAG
5
3
17
20
24
27
GENERATE
20
28(2)
18
CORRECT
(Not Internal
Control Mode)
-
25
-
DIAG MODE
(Not Internal
Control Mode)
25
21
27
24
PASSTHRU
(Not Internal
Control Mode)
25
28
21
24
CODE ID 2- 0
26
31
28
31
LEIN
(From latched
to transparent)
24
37
26
29
LEoUT
(From latched
to transparent)
-
OUTPUT ENABLE/DISABLE TIMES
16
-
Output disable tests performed with CL = 5pF and measured to
O.5V change of output voltage level.
-
INPUT
LE 01AG
(From latched to
transparent; Not
Internal Control
Mode)
24
Intemal Control
Mode: LE OIAG
(From latched
to transparent)
30
Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)
3
LEIN
CB O- 6
(CODE ID2-0 010,
100,101,110,111)
28
HOLD
TIME
CBO-6
17
24
SET-UP
TIME
DATA 0-15
CBO-6
(CODE ID2-0
000,011)
28
TO
(LATCHING
DATA)
FROM INPUT
MOLT ERROR
37(2)
43(2)
26
32
29
35
30
32
ENABLE
DISABLE
OEBYTE o'
OE BYTE 1
DATA o_15
28
25
OEsc
SCO-6
28
25
MINIMUM PULSE WIDTHS
I
43(2)
OUTPUT
12
LE1N, LEoUT' LEolAG
35
NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 70ns (fmax = 14.3MHz)
NOTE:
1. DATAIN to Corrected DATAouT measurement requires timing as shown
below.
IDT39C60A MILITARY-DATA IN TO CORRECTED DATAoUTTIMING
(Two cycles shown)
TIMING PARAMETER
FROM
TO
MIN.!
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
DtI~~7nS~~~t~OL~Ei~n == L~~w
Min.
Min .
. LE in = High to DATA out
Max.
* = (Memory/System dependent)
S8-77
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60-1 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60-1 over the commercial operating range of 0° C to + 70°0,
with Vee from 4.7SV to S.2SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = SOpF
TO OUTPUT
FROM INPUT
DATAo-15
SCo-s
28
DATA 0-15 ~
52(1)
25
50
CBO-6
(CODE ID2- 0
000, 011)
23
CB O_6
(CODE ID2-0 010,
100,101,110,111)
28
34
29
34
GEI\IERATE
35
63
36
55
CORRECT
(Not Internal
Control Mode)
-
45
-
-
DIAG MODE
(Not Internal
Control Mode)
PASSTHRU
(Not Internal
Control Mode)
50
36
50
78
44
23
59
47
75
29
46
CODE 102-0
61
90
60
80
LEIN
(From latched
to transparent)
39
72
39
59
LEoUT
(From latched
to transparent)
SET-UP
TIME
HOLD
TIME
7
DATA o_15
LEIN
6
CBO-6
LEIN
5
6
DATA o_15
LEouT
34
5
C B O-6
(CODE ID 000, 011)
LEoUT
35
a
CB O- 6
(CODE ID 010,100,
101,110,111)
LEoUT
27
a
a
GENERATE
LEoUT
42
CORRECT
LEoUT
26
1
DIAG MODE
LEoUT
69
PASSTHRU
LEoUT
26
CODE ID2-0
LEoUT
81
a
a
a
LEIN
LEoUT
51
5
DATAo-15
LEalAG
6
8
OUTPUT ENABLE/DISABLE TIMES
-
31
-
Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage level.
-
INPUT
LE OIAG
(From latched to
transparent; Not
Internal Control
Mode)
45
Internal Control
Mode: LE OIAG
(From latched
to transparent)
67
Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)
TO
(LATCHING
DATA)
FROM INPUT
fiiiOL'i' ERROR
78
96
45
66
65
86
96
66
ENABLE
DISABLE
Oi: BYTE o'
Oi: BYTE 1
DATA 0-15
30
30
OE:sc
SCO-6
30
30
MINIMUM PULSE WIDTHS
I
67
OUTPUT
15
LEIN, LEoUT' LEolAG
86
NOTES:
Device Mode = ·Correct"
System Type = ·Correct Always"
Min. Period = 92ns (fmax = 10.9MHz)
NOTE:
1. DATA IN to Corrected DATAour measurement requires timing as shown
below.
IDT39C60-1 COMMERCIAL-DATA IN TO CORRECTED DATAouT TIMING
TIMING PARAMETER
FROM
TO
MIN.!
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
D61~~7nS~~~tb\~Ei~n == L'o~
Min.
Min.
LE in = High to DATA out
= (Memory/System dependent)
Max.
(Two cycles shown)
*
58-78
IDT39C60/-1/A1B 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60-1 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60-1 over the military operating range of-55°Cto + 125°C,
with Vee from 4.5V to 5.5V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = SOpF
TO
(LATCHING
DATA)
TO OUTPUT
FROM INPUT
DATA o- 15
SCO-6
31
DATA 0-15 ERROR
59(1)
28
MOLT
56
7
LEIN
5
7
DATA 0-15
LEoUT
39
5
CBO-6
(CODE 10 000, 011)
LEoUT
38
0
62
CBO-6
(CODE 10010, 100,
101,110,111)
LEoUT
30
0
-
GE:f\lERATE: (2)
LEoUT
46
0
CORRECT
LEoUT
28
1
DIAG MODE
LEoUT
84
0
30
38
31
37
GE:f\lERATE:
38
69(2)
41
CORRECT
(Not Internal
Control Mode)
-
49
-
DIAG MODE
(Not Internal
Control Mode)
58
PASSTHRU
(Not Internal
Control Mode)
39
51
65
34
50
90
54
CODE 102-0
69
100
68
90
LEIN
(From latched
to transparent)
39
82
43
66
LEoUT
(From latched
to transparent)
-
33
-
-
PASSTHRU
LEoUT
30
0
CODE 10 2- 0
LEoUT
89
0
LEIN
LEoUT
59
5
DATAo-15
LEDIAG
7
9
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL = 5pF and measured to
0.5V change of output voltage level.
INPUT
LE D1AG
(From latched to
transparent; Not
Internal Control
Mode)
50
Internal Control
Mode: LE DIAG
(From latched
to transparent)
75
Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)
7
LEIN
CB O- 6
(CODE 102- 0 010,
100,101,110,111)
89
HOLD
TIME
CBO-6
25
25
SET-UP
TIME
DATA 0-15
CB O- 6
(CODE 102- 0
000.011)
55
FROM INPUT
ERROR
88(2)
106(2)
49
74
72
96
106(2)
74
"C5"E"sc
OUTPUT
ENABLE
DISABLE
DATA 0-15
35
35
SCO-6
35
35
MINIMUM PULSE WIDTHS
I
75
DE BYTE o'
DE BYTE 1
15
LEIN, LEoUT, LEDIAG
96
NOTES:
Device Mode = "Correct"
System Type = "Correct Always"
Min. Period = 104ns (fmax = 9.6MHz)
NOTE:
1. DATAIN to Corrected OATAoUT measurement requires timing as shown
below.
IDT39C60-1 MILITARY-DATA IN TO CORRECTED DATAoUT TIMING
TIMING PARAMETER
FROM
TO
MIN.!
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
Dtl~~7nS~~~I\~OL~Ei~n == L~~w
Min.
Min.
LE in = High to DATA out
= (Memory/System dependent)
Max.
(Two cycles shown)
*
S8-79
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60 over the commercial operating range of O°C to + 70°C,
with Vee from 4.75V to 5.25V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC load.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
CL = 50pF
TO
(LATCHING
DATA)
TO OUTPUT
FROM INPUT
DATA 0-15
SC O_8
32
DATA 0-15 ~
65(1)
32
fJlOCi
50
CBo_s
(CODE 102- 0
000.011)
28
CBo_s
(CODE 102-0 010.
100.101,110.111)
28
45
29
34
GI:I\lERATE
35
63
36
55
CORRECT
(Not Internal
Control Mode)
-
45
-
-
DIAG MODE
(Not Internal
Control Mode)
50
56
78
29
59
47
75
PASSTHRU
(Not Internal
Control Mode)
36
44
CODE ID2-0
61
90
60
80
LEIN
(From latched
to transparent)
39
72
39
59
LEoUT
(From latched
to transparent)
-
31
-
-
46
SET-UP
TIME
HOLD
TIME
7
DATA 0-15
LEIN
6
CBo-s
LEIN
5
6
DATA o- 15
LEoUT
44
5
CBo-s
(CODE ID 000. 011)
LEoUT
35
0
CBo-s
(CODE ID 010. 100.
101.110.111)
LEoUT
27
0
0
GI:f:lI:I1ATI:
LEoUT
42
CORRECT
LEoUT
26
1
DIAG MODE
LEoUT
69
0
PASSTHRU
LEoUT
26
0
CODE ID2-0
LEoUT
81
0
LEIN
LEoUT
51
5
DATA 0-15
LEolAG
6
8
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL = 5pF and measured to
O.5V change of output voltage level.
INPUT
LE OIAG
(From latched to
transparent; Not
Internal Control
Mode)
45
Internal Control
Mode: LE DIAG
(From latched
to transparent)
67
Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)
29
FROM INPUT
ERROR
78
96
45
66
65
86
96
66
rn=se
ENABLE
DISABLE
DATA o- 15
30
30
SCo-s
30
30
OUTPUT
MINIMUM PULSE WIDTHS
I
67
~BYTEo.
~BYTE1
15
LEIN, LEoUT. LE OIAG
86
NOTES:
Device Mode = ·Correct"
System Type = ·Correct Always·
Min. Period = 105ns (fmax = 9.5MHz)
NOTE:
1. DATAIN to Corrected DATAoUT measurement requires timing as shown
below.
IDT39C60 COMMERCIAL-DATA/N TO CORRECTED DATAoUT TIMING
sa-80
(Two cycles shown)
TIMING PARAMETER
FROM
TO
MIN.!
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA in to Corrected DATA out
Max.
Max.
Max.
DATA in Set-up to LE in = Low
DATA in Hold to LE in = Low
Min.
Min.
LE in = High to DATA out
• = (Memory/System dependent)
Max.
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60 over the military operating range of -55°C to + 125°C,
with Vee from 4.SV to S.SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.
COMBINATIONAL PROPAGATION DELAYS
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
c L = SOpF
TO OUTPUT
FROM INPUT
DATA o- 15
C B o-6
(CODE ID2_0
000. 011)
SC O_6
35
30
DATA 0-15
73(1)
61
"EtrnCrn
36
31
~OCT
TO
(LATCHING
DATA)
FROM INPUT
ERROR
56
50
SET-UP
TIME
HOLD
TIME
DATA o- 15
LEIN
7
7
CBO-6
LEIN
5
7
DATA o- 15
LEouT
50
5
CBO-6
(CODE ID 000, 011)
LEoLrr
38
0
CBo-6
(CODE ID2-0 010.
100,101,110.111)
30
50
31
37
GENERATE
38
69(2)
41
62
LEoLrr
30
0
CORRECT
(Not Internal
Control Mode)
CBO-6
(CODE ID 010. 100,
101, 110, 111)
-
49
-
-
GENERATE (2)
LEoUT
46
a
CORRECT
LEoUT
28
1
DIAG MODE
LEoLrr
84
0
PASSTHRU
LEoLrr
30
0
CODE ID2-Q
LEOLrr
89
0
LEIN
LEoLrr
59
5
DATA 0-15
LEolAG
7
9
DIAG MODE
(Not Internal
Control Mode)
58
89
65
90
PASSTHRU
(Not Internal
Control Mode)
39
51
34
54
CODE ID 2- 0
69
100
68
90
LEIN
(From latched
to transparent)
44
82
43
66
LEOLrr
(From latched
to transparent)
-
OUTPUT ENABLE/DISABLE TIMES
-
Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage leve\.
-
INPUT
LEolAG
(From latched to
transparent; Not
Internal Control
Mode)
50
Internal Control
Mode: LE OIAG
(From latched
to transparent)
75
Internal Control
Mode: DATAo-15
(Via Diagnostic
Latch)
33
88(2)
106(2)
49
74
72
96
75
74
ENABLE
DISABLE
DATAo-15
35
35
OE"sc
SCo-e
35
35
MINIMUM PULSE WIDTHS
I
106(2)
OUTPUT
(5"E BYTE o,
(5"E BYTE 1
15
LEIN, lEoUT, LEolAQ
96
NOTES:
, DeVice Mode ". ·Correct·
System Type = ·Correct Always·
Min. Period = 118ns (fmax = 8.5MHz)
NOTE:
1. DATAIN to Corrected DATAoLrr measurement requires timing as shown
below.
:
IDT39C60 MILITARY-DATA IN TO CORR,ECTED DATAoUT TIMING
TIMING PARAMETER
FROM
TO
MIN,I
MAX.
OEbyte = High to DATA out Disabled
OEbyte = Low to DATA out Enabled
DATA In to Corrected DATA out
Max.
Max.
Max.
DATA in Set-up to LE In = Low
DATA in Hold to LE in
Low
Mlp.
M".
(Two cycles shown)
=
*=
58';'81
=
LE In
High to DATA out
(Memory/System dependent)
Max.
IDT39C60/-1/A/B 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxxx
x
Device Type
Process!
Temperature
Range
y:rank
P
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
L
Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
39C60
39C60-1
39C60A
39C60B
16-Bit EDC Unit
Fast 16-Bit EDC Unit
Very-fast 16-Bit EDC Unit
Ultra-Fast 16-Bit EDC Unit
C
J
S8-82
~
Intesrated Device~lnc.
32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
lOT 49C460
lOT 49C460A
lOT 49C460B
lOT 49C460C
DESCRIPTION:
FEATURES:
• Fast
The IDT49C460s are high-speed, low-power, 32-bit Error Detection and Correction Units which generate check bits on a 32-bit
data field according to a modified Hamming Code and correct the
data word when check bits are supplied. The lOT49C460s are performance-enhanced functional replacements for 32-bit versions of
the 2960. When performing a read operation from memory, the
lOT49C460s will correct 100% of all single bit errors and will detect
all double bit errors and some triple bit errors.
The lOT49C460s are easily cascadable to 64-bits. Thirty-two-bit
systems use 7 check bits and 64-bit systems use 8 check bits. For
both configurations, the error syndrome is made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be entered
into the device and to execute system diagnostic functions.
They are fabricated using CEMOS ™ , a CMOS technology designed for high-performance and high-reliability. The devices are
packaged in a 68-pin PGA, both ceramic and plastic, LCC (25 mil
and 50 mil centers), PLCC and Ceramic Quad Flatpack.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
. performance and reliability.
Correct
- IDT49C460C
Detect
16ns (max.)
- IDT49C460B
- IDT49C460A
25ns (max.)
30ns (max.)
36ns (max.)
- IDT49C460
40ns (max.)
49ns (max.)
24ns (max.)
30ns (max.)
• Low-power CMOS
- Commercial: 95mA (max.)
- Military: 125mA (max.)
• Improves system memory reliability
- Corrects all single bit errors, detects all doubie and some
triple-bit errors
• Cascadable
- Data words up to 64-bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Functional replacement for 32- and 64-bit configurations of the
2960
• Available in PGA, PPGA, LCC, PLCC and Ceramic Quad Flatpack
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
CBO-7 L-~~~------------------------------------------~
DATA 0-31
OE BYTE
0-3 r=)-+-+~
...---_ _ _..:1'
SC0-7
OEsc
ERROR
MULT ERROR
LE DIAG
C>----f---------J
LEoUT/GENERATE r::>--~-'----,
CORRECT L-~---"
CONTROL
LOGIC
CODE IDl.O ~)---T--"
DIAG MODE,. 0 .-:)----,~-......._ _ _ ___
CEMOS and MICROSLICE are trademarks of Integrated Device Technology,
IFlC.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-901711
1989 Integrated Device Technology. Inc.
S8-83
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
~O
ww
00 ~ 0
0000
o
:!:!UjUj
~~ ~ 88
M
~
co .... co
I()~
08~~oouufoooooooO~
0
'"
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 6261
Vee 10
D2 11
D3 12
D4 13
D5 14
D6 15
D7 16
D8 17
GND 18
D9 19
D l o 20
Dll 21
D12 22
D13 23
D14 24
D15 25
DEl 26
DESIGNATES
PIN 1 FOR
PlCC ONLY
J68-1,
l68-1
MULTERROR
GND
2728293031323334353637383940414243
~m~~M~-OO_~Mv~~
0
mmmmmmmmuuuuuuuu~
uuuuuuuucncncncncncncnci510
10
11
12
13
14
15
16
PlCC/lCC
TOP VIEW
PIN 1 IDENTIFICATION
D24
D23
D22
D21
D20
D19
D18
QE-68
Vee
D17
17
18
19
20
21
22
23
24
25
26
CORRECT
~
MOLT ERROR
GND
2728293031323334353837383940414243
D20
OEse
D27
SC7
SC8
SCo
SC 4
SC3
SCz
SCI
SCo
CBo
CB 1
CBz
CB3
CB4
CBo
CB8
D28
D29
D28
D3l
D30
CODE IDo
OE 3
DIAG MODE o
CODE IDI
lEIN
DIAG MODEl
Do
CEo
Dl
PGA
TOP VIEW
S8-84
D16
Pl,~/GENERATE
CERQUAD
TOP VIEW
IDT49C460/AIB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
I/O
I/O
32 bidirectional data lines. They provide input to the Data Input Latch and Diagnostic Latch and also receive output from the
Data Output Latch. DATAois the LSB; DATA 31 is the MSB.
CBO-7
I
Eight check bit input lines. Used to input check bits for error detection and also used to input syndrome bits for error correction in 64-bit applications.
LEIN
I
Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input Latch are
latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input latch follow the Input data
and input check bits.
I
A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the check bits or
partial check bits specific to the data in the Data Input Latch. The generated check bits are placed on the SC outputs. Also,
when LOW, the Data Out Latch is latched to its previous state.
DATA 0-31
LEoUT/
GENERATE
When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple errors, and
generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch. In the Correct Mode,
single bit errors are also automatically corrected and the corrected data is placed at the inputs of the Data Output Latch. The
syndrome result is placed on the SC outputs and indicates in a coded form the number of errors and the specific bit-in-error.
When HIGH, the Data Output Latch follows the output of the Data Input Latch as modified by the correction logic network. In
Correct Mode, single bit errors are corrected by the network before being loaded into the Data Output Latch. In Detect Mode,
the contents of the Data Input Latch are passed through the correction network unchanged into the Data Output Latch. The
Data Output Latch is disabled, with its contents unchanged, if the EDC is in the Generate Mode.
SC0-7
0
Syndrome Check Bit outputs. Eight outputs Which hold the check bits and partial check bits when the EDC is in the Generate
Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct modes. All are 3-state
outputs.
OEro
I
Output Enable-Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state. When LOW,
all SC output lines are enabled.
ERROR
0
In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When HIGH, no errors
have been detected. This pin is forced HIGH in the Generate Mode.
MULT ERROR
0
In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level indicates that
either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.
CORRECT
I
The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input Latch (by
complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will drive data directly
from .the Data Input Latch to the Data Output Latch without correction.
OE BYTE0-3
I
Output Enable - Bytes 0, 1,2,3. Data Output Latch. Control the three-state output buffers for each of the four bytes of the Data
Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH, they force the Data Output
Latch buffer into the high impedance mode. One byte of the Data Output Latch is easily activated by separately selecting the
four enable lines.
DIAG MODE 1. 0
I
Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.
CODE 101. 0
I
These two code identification inputs identify the size of the total data word to be processed. The two allowable data word sizes
are 32 and 64 bits and their respective modified Hamming Codes are deSignated 32/39 and 64(12. Special CODE I~.o input
01 is also used to instruct the EDC that the Signals CODE 10 1 0' DIAG MODEl 0 and CORRECT are to be taken from the
Diagnostic Latch rather than from the input control lines.'
.
I
This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the input lines.
When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch holds diagnostic
check bits and internal control signals for CODE 10 1. 0 , DIAG MODE 1. 0 and CORRECT.
LE 01AG
S8-85
.-------
.......
_._.. __..-.... __ - - - - - ..
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EDC ARCHITECTURE SUMMARY
ERROR DETECTION LOGIC:
The IDT49C460s are high-performance cascadable EDCs
used for check bit generation, error detection, error correction and
diagnostics. The function blocks for this 32-bit device consist of
the following:
• Data Input Latch
• Check Bit Input Latch
• Check Bit Generation Logic
• Syndrome Generation Logic
• Error Detection Logic
• Error Correction Logic
• Data Output Latch
• Diagnostic Latch
• Control Logic
This part of the device decodes the syndrome bits generated
by the Syndrome Generation Logic. With no errors in either the input data or check bits, both the ERROR and MULT ERROR outputs are HIGH. ERROR will go low if one error is detected. MULT
ERROR and ERROR will both go low if two or more errors are detected.
DATA INPUT/OUTPUT LATCH:
DATA OUTPUT LATCH AND OUTPUT BUFFERS:
The Latch Enable Input, LE IN' controls the loading of 32 bits of
data to the Data In Latch. The data from the DATA lines can be
loaded in the Diagnostic Latch under control of the Diagnostic
Latch Enable, LE olAG , giving check bit information in one byte and
control information in another byte. The Diagnostic Latch is used
In the Internal Control Mode or in one of the diagnostic modes.
The Data Output Latch has buffers that place data on the DATA
lines. These buffers are split into four 8-bit buffers, each having
their own output enable controls. This feature facilitates byte read
and byte modify operations.
The Data Output Latch is used for storing the result of an error
correction operation. The latch is loaded from the correction logic
under control of the Data Output Latch Enable, LE oUT • The Data
Output Latch may also be directly loaded from the Data Input
Latch in the PASSTHRU mode. The Data Output Latch buffer is
§QIjt into 4 individual buffers which can be enabled by
OEo-3 separately for reading onto the bidirectional data lines.
CHECK BIT INPUT LATCH:
Eight check bits are loaded under control of LE N' Check bits
are used in the Error Detection and Error Correct ibn modes.
CHECK BIT GENERATION LOGIC:
Ghis generates the appropriate check bits forthe 32 bits of data
in the Data Input Latch. The modified Hamming Code is the basis
for generating the proper check bits.
SYNDROME GENERATION LOGIC:
In both the Detect and Correct modes, this logic does a comparison on the check bits read from memory against the newly
generated set of check bits produced for the data read in from
memory. Matching sets of check bits mean no error was detected.
If there is a mismatch, one or more of the data or check bits is in
error. Syndrome bits are produced by an exclusive-OR of the two
sets of check bits. Ident';11 sets of check bits means the syndrome bits will be all zer~ If an error results, the syndrome bits
can be decoded to determine the number of errors and the specific bit-in-error.
ERROR CORRECTION LOGIC: .
In single error cases, this logic complements (corrects) the single data bit-in-error. This corrected data is loaded into the Data
Output Latch, which can then be read onto the bidirectional data
lines. If the error is resulting from one of the check bits, the correction logic does not place corrected check bits on the syndrome/
check bit outputs. If the corrected check bits are needed, the EDC
must be switched to the Generate Mode.
DIAGNOSTIC LATCH:
The diagnostic latch is loadable, under control of the Diagnostic Latch Enable, LEoIAG. from the bidirectional data lines. Check
bit information is contained in one byte while the other byte contains the control information. The Diagnostic Latch is used for
driving the device when in the Internal Control Mode, or for supplying check bits when in one of the diagnostic modes.
CONTROL LOGIC:
Specifies what mode the device will be operating in. Normal
operati on is when the control logic is driven by external control inputs. In the Internal Control Mode, the control signals are read
from the Diagnostic Latch. Since LE OUT and GENERATE are controlled by the same pin, the latching action (LE OUT from high to
low) of the Data Output Latch causes the EDC to go into the Generate Mode.
S8-86
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED PRODUCT DESCRIPTION
The I DT49C460 EDC units contain the logic necessary to generate check bits on 32 bits of data input according to a modified Hamming Code. The EDC can compare internally generated check bits
against those read with the 32-bit data to allow correction of any
single bit data error and detection of all double (and some triple) bit
errors. The IDT49C460s can be used for 32-bit data words (7 check
bits) and 64-bit (8 check bits) data words.
TABLE 2.
DIAGNOSTIC MODE CONTROL
CORRECT
X
WORD SIZE SELECTION:
X
DIAG
MODE1
0
0
DIAG
MODEo
0
1
Diagnostic Generate. The contents
of the Diagnostic Latch are substituted for the normally generated
check bits when in the Generate
Mode. The EDCfunctions normally in
the Detect or Correct modes.
Diagnostic Detect/Correct. In either
mode, the contents of the Diagnostic
Latch are substituted for the check
bits normally read from the Check Bit
Input Latch. The EDC functions normally in the Generate Mode.
The 2 code identification pins. CODE ID1.0 are used to determine the data word size that is 32 or 64 bits. Table 5 defines all possible slice identification codes. They also select the Internal Control Mode.
CHECK AND SYNDROME BITS:
The IDT49C460s provide either check bits or syndrome bits on
the three-state output pins. SC0-7' Check bits are generated from a
combination of the Data Input bits. while syndrome bits are an exclusive-OR ofthe check bits generated from read data with the read
check bits stored with the data. Syndrome bits can be decoded to
determine the single bit in error or that a double (some triple) error
was detected. The check bits are labeled:
Co.
Co.
c,. Cz. G.3, C4 , Cs, C 6
c" ~, G.3, C4, Cs, Ce. C 7
DIAGNOSTIC MODE SELECTED
Non.diagnostlc Mode. Normal
EDC function in this mode.
X
1
0
1
1
1
Initialize. The Data Input Latch out·
puts are forced to zeros and
iatched upon removal of initialize
Mode.
0
1
1
PASSTHRU.
for the 32-bit configuration
for the 64-bit configuration
Syndrome bits are similarly labeled
&
through S7.
TABLE 3.
IDT49C460 OPERATING MODES
OPERATING
MODE
Generate
Detect
DM1
DMo
GENERATE
CORRECT
DATA OUT LATCH
SCO-7
(OEsc
LOW)
=
Check Bits Generated from
Data In Latch
EBRQR
MULT ERROR
0
0
1
0
0
X
0
0
1
1
0
Data In Latch
Syndrome Bits Data Inl
Check Bit Latch
Error Dep(2)
1
1
Data In Latch wI
Single Bit Correction
Syndrome Bits Data Inl
Check Bit Latch
ErrorDep
0
LE OUT
=
LOW(l)
High
0
0
1
PASSTHRU
1
1
1
0
Data In Latch
Check Bit Latch
High
Diagnostic Generate
0
1
0
X
-
Check Bits from Diagnostic Latch
High
0
Data In Latch
Syndrome Bits Data Inl
Diagnostic Latch
ErrorDep
Syndrome Bits Data Inl
Diagnostic Latch
ErrorDep
-
-
Correct
Diagnostic Detect
0
1
1
0
Diagnostic Correct
1
0
1
1
Data In Latch wI
Single Bit Correction
Initialization Mode
1
1
1
1
Data In Latch
set to 0000
Intemal Mode
CODE 101.0
= 01
(Control Signals CODE 101. 0, DIAG MODEl. 0 , and CORRECT are taken from Diagnostic Latch.)
NOTES:
1. In Generate Mode, data is read into the EDC unit and the check bits are generated. The same data is written to memory along with the check bits. Sincatha
Data Out Latch is not used in the Generate Mode, LEoUT (being LOW since it is tied to Generate), does not affect the writing of check bits.
2. Error Dep (Error Dependent): ERROR will be low for single or multiple errors, with MOL I ERROR low for double or multiple errors. Both signals are high for
no errors.
S8-87
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODE SELECTION:
Tables 2 and 3 describe the 9 operating modes of the
IDT49C460s. The Diagnostic Mode pins-DIAG MODEo,1-define four basic areas of operation. GENERATE and CORRECTfurtherdivide operation into 8 functions, with CODE 101. 0 defining the
ninth mode as the Internal Mode.
Generate Mode is used to display the check bits on the outputs
SCO- 7' The Diagnostic Generate Mode displays check bits as
stored in the Diagnostic Latch.
Detect Mode provides an indication of errors or multiple errors
on the outputs ERROR and MULT ERROR. Single bit errors are not
corrected In this mode. The syndrome bits are provided on the outputs SCo...7' Forthe Diagnostic Detect Mode, the syndrome bits are
generated by comparing the intemally generated check bits from
the Data In Latch with check bits stored in the diagnostic latch
rather than with the check bit latch contents.
Correct Mode is similarto the Detect Mode exceptthat Single bit
errors will be complemented (corrected) and made available as input to the Data Out Latches. Again, the Diagnostic Correct Mode
will correct single bit errors as determined by syndrome bits generated from the data input and contents of the diagnostic latches.
The Initialize Mode provides check bits for all zero bit data. Data
Input Latches are set, latched to a logic zero and made available
as input to the Data Out Latches.
The Intemal Mode disables the extemal control pins DIAG
MODEo, 1 and CORRECT to be defined by the Diagnostic Latch.
Even CODE 101,0, although extemally set to the 01 code, can be
redefined from the Diagnostic Latch data.
DATA INPUT
DATA 32-83
TABLE 5. SLICE IDENTIFICATION
CODE 10 1
0
0
1
1
CODE 10 0
SLICE SELECTED
0
32-8it
Intemal Control Mode
64-8it, Lower 32-8it (0-31)
64-8it. Upper 32-8it (32-63)
1
0
1
DATA 0-31
32
DATA
IDT49C460
(LOWER 32 BITS)
32
CODE 10 1,0
SC O- 7
8
DATA
IDT49C460
IDT49C460
(UPPER 32 BITS)
0,0
CODE IDl,O
MULT
ERROR
OEsc I + - - i - - - - '
CODE 10 1,0
'"ERROR"
+- 1,1
SC0-7
8
MOO'
'"ERROR"
SYNDROME/
CHECK81TS
Figure 1. 32-Blt Configuration
Figure 2. 64-Blt Configuration
DATA
CHECK !3ITS
Ce
31
24.23
1615
87
0
Figure 3. 32-Blt Data format
DATA
CHECK BITS
Figure 4. 64-81t Data Format
/
('
S8-88
IDT49C460/AlB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT DATA WORD CONFIGURATION:
XOR of check bits C n from those read with those generated.
Table 7 Indicates the decoding ofthe seven syndrome bits to Identity the bit-In-error for a single bit error or whether a double or triple
bit error was detected. The all zero case Indicates no errors
detected.
In the Correct Mode, the syndrome bits are used to complement
(correct) single bit errors In the data bits. For double or multiple
error detection, the data available as input to the Data Out Latch is
not defined.
Table 4 defines the bit definition for the Diagnostic Latch. As defined In Table 3, several modes will use the diagnostic check bits
to determine syndrome bits or to pass as check bits to the
SC0-7 outputs. The Internal Mode substitutes the indicated bit
position for the external control signals.
A single IDT49C460 EDC unit, connected as shown in Figure 1,
provides all the logic needed for single bit error correction and
double bit error detection of a 32-bit data field. The Identification
code indicates 7 check bits are required. The CB 7 pin should be
HIGH.
Figure 3 indicates the 39-bit data format for .two bytes of data
and 7 check bits. Table 3 describes the operating mode available.
Table 6 indicates the data bits participating in the check bit generation. For example, check bit CO is the exclusive-OR function of
the 16 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization Mode. Check bits
from the respective latch are passed, unchanged, in the Pass Thru
or Diagnostic Generate Mode.
Syndrome bits are generated by an exclusive-OR or thegenerated check bits with the read check bits. For example, Sn is the
TABLE 4.
32-BIT DIAGNOSTIC
LATCH CODING FORMAT
BIT 0
BIT 1
BIT 2
BIT3
BIT4
BIT 5
BIT6
BIT7
BIT 8
BIT9
BIT 10
BIT 11
BIT 12
BIT 13-31
CBo DIAGNOSTIC
CB 1 DIAGNOSTIC
CB 2 DIAGNOSTIC
CB 3 DIAGNOSTIC
CB 4 DIAGNOSTIC
CBs DIAGNOSTIC
CBe DIAGNOSTIC
CB 7 DIAGNOSTIC
CODE IDo
CODE IDl
DIAG MODE o
DIAG MODEl
CORRECT
DONTCARE
TABLE 6. 32-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART
I
PARTICIPATING DATA BITS
GENERATED
CHECK BITS
PARITY
Co
C1
Even (XOR)
X
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Cs
Even (XOR)
Ce
Even (XOR)
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
Cl
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
0
1
X
2
3
X
X
4
6
7
8
9
X
X
X
X
X
X
X
X
X
Even (XOR)
X
X
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
X
X
X
X
X
X
11
X
12
13
X
X
X
X
10
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
30
31
X
PARTICIPATING DATA BITS
22
X
X
23
24
25
X
X
X
X
X
X
X
X
X
X
X
X
X
28
29
X
X
X
X
X
X
X
X
X
X
X
X
C4
Even (XOR)
X
X
Cs
Even (XOR)
X
X
X
X
X
X
X
X
Ce
Even (XOR)
X
X
X
X
X
X
X
X
X
X
X
58-89
- - - - - - - - - - - - - - - - - - _ . _ - - _ .__._-----
-_.
--_._----_._---
----------.----
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
the bit in error for a single bit error or wrether a double or triple bit
error was detected. The all zero case indicates no errors detected.
In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or multiple error detection, the data available as Input to the Data Out
Latch is not defined.
Tables 8A and 8B define the bit definition for the Diagnostic
Latch. As defined in Table 3, several modes will use the Diagnostic Check Bits to determine syndrome bits or fo pass as check bits
to the SC O_70utputs. The Internal Mode substitutes the indicated
bit position for the external control signals.
Performance data Is provided In Table 10, relating a Single
IDT49C460 EDC with the two cascaded units of Figure 2. As indicated, a summation of propagation delays is required from the
cascading arrangement of EOC units.
TABLE 7.
SYNDROME DECODE TO BIT-IN-ERROR (32-BIT)
I HEX 0 1 2 3 4 5 6 7
Sa
Ss
S4
SYNDROME
BITS
~
HEX S3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
S2
Sl
So
0
0
0
0
0
*
C4
C5
T
C6
T
T
30
1
0
0
0
1
CO
T
T
14
T
M
M
T
2
0
0
1
0
C1
T
T
M
T
2
24
T
3
0
0
1
1
T
18
8
T
M
T
T
M
4
0
1
0
0
C2
T
T
15
T
3
25
T
5
0
1
0
1
T
19
9
T
M
T
T
31
6
0
1
1
0
T
20
10
T
M
T
T
M
7
0
1
1
1
M
T
T
M
T
4
26
T
8
1
0
0
0
C3
T
T
M
T
5
27
T
TABLE SA.
64-BIT DIAGNOSTIC LATCH-CODING FORMAT
(DIAGNOSTIC DETECT AND CORRECT MODE)
9
1
0
0
1
T
21
11
T
M
T
T
M
A
1
0
1
0
T
22
12
T
1
T
T
M
BIT
B
1
0
1
1
17
T
T
M
T
6
28
T
M
0
1
2
3
4
5
C
1
1
0
0
T
23
13
T
M
T
T
D
1
1
0
1
M
T
T
M
T
7
29
T
E
1
1
1
0
16
T
T
M
T
M
M
T
1
T M
M
F
1
1
1
T
NOTES:
* = No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected
0
T
T
M
6
7
8
9
10
11
12
13-31
32-39
40
41
42
43
44
45-63
64-BIT DATA WORD CONFIGURATION:
Two IDT49C460 EDC units, connected as shown in Figure 2,
provide all the logic needed for single bit error correction and double bit error detection of a 64-bit data field. Table 5 gives the
CODE IDI. a values needed for distinguishing the upper 32 bits
from the lower 32 bits. Valid syndrome, check bits and the ERROR
and MULT ERROR signals come from the IC with the CODE
ID1,O = 11. Control signals not indicated are connected to both
units in parallel. The EDCwiththe CODE ID1,O = 10 has the OEsc
grounded. The OEsc selects the syndrome bits from the EDC with
CODE 101, a = 11 and also controls the check bit buffers from
memory.
Data In bits 0 through 31 are connected to the same numbered
inputs of the EDC unit with CODE ID1,O = 10, while Data In bits 32
through 63 are connected to Data Inputs 0 to 31, respectively, for
the EDC unit with CODE ID1,O = 11.
Figure 4 indicates the 72-bit data format of 8 bytes of data
and 8 check bits. Check bits are input to the EDC unit with CODE
ID1.0 = 10 through a three-state buffer unit such as the
IDT74FCT244. Correction of single bit errors of the 64-bit configuration requires a feedback of syndrome bits from the upper EDC
unit to the lower EDC unit. The M UX shown on the functional block
diagram is used to select the CB 0-7 pins as the syndrome bits
rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 64/72
.
configuration.
Table 11 indicates the data bits participating in the check bit
generation. For example, check bit CO is the exclusive-OR function
orthe 32 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization modes. Check bits are
passed as stored in the PASSTHRU or Diagnostic Generate
modes.
Syndrome bits are generated by an exclusive-OR of the generated check bits with the read check bits. For example, s" is the
XOR of check bits Cn from those read with those generated.
Table 9 indicates the decoding ofthe 8 syndrome bits to determine
S8-90
INTERNAL FUNCTION
CBo DIAGNOSTIC
CBl DIAGNOSTIC
CBz DIAGNOSTIC
CB3 DIAGNOSTIC
CB 4 DIAGNOSTIC
CBs DIAGNOSTIC
CBs DIAGNOSTIC
CB7 DIAGNOSTIC
CODE IDa LOWER 32-BIT
CODE IDI LOWER 32-BIT
DIAG MODEa LOWER 32-BIT
DIAG MODEl LOWER 32-BIT
CORRECT LOWER 32-BIT
DON'T CARE
DON'T CARE
CODE IDa UPPER 32-BIT
CODE IDI UPPER 32-BIT
DIAG MODEo UPPER 32-BIT
DIAG MODEl UPPER 32-BIT
CORRECT UPPER 32-BIT
DON'T CARE
TABLE SB.
64-BIT DIAGNOSTIC LATCH-CODING FORMAT
(DIAGNOSTIC GENERATE MODE)
BIT
'.
0-7
8
9
10
11
12
13-31
32
33
34
35
36
37
38
39
40
41
42
43
44
45-63
INTERNAL FUNCTION
DON'T CARE
CODE IDa LOWER 32-BIT
CODE IDI LOWER 32-BIT
DIAG MODE a LOWER 32-BIT
DIAG MODE 1 LOWER 32-BIT
CORRECT LOWER 32-BIT
DON'T CARE
CBo DIAGNOSTIC
CB 1 DIAGNOSTIC
CBz DIAGNOSTIC
CB3 DIAGNOSTIC
CB4 DIAGNOSTIC
CBs DIAGNOSTIC
CBe DIAGNOSTIC
CB7 DIAGNOSTIC
CODE IDa UPPER 32-BIT
CODE IDI UPPER 32-BIT
DIAG MODEa UPPER 32-BIT
DIAG MODEl UPPER 32-BIT
CORRECT UPPER 32-BIT
DON'T CARE
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 9. SYNDROME DECODE TO BIT-IN-ERROR (64-BIT CONFIGURATION)
I
SYNDROME
BITS
0
0
0
0
1
2
3
4
5
0
0
0
0
0
0
0
0
1
0
1
6
0
7
0
8
9
A
B
C
0
E
F
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
2
3
4
5
6
7
8
~
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Sa
Ss
S4
r--
HEX S3 S2 S1
HEX
So
0
A
B
C
0
E
F
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
T
30
9
1
*
C4
C5
T
C6
T
C7
46
T
M
M
T
T
14
T
M
M
40
T
M
M
T
T
T
T
18
8
T
T
M
T
T
T
T
T
T
T
T
M
34
T
M
50
T
CO
C1
T
M
56
62
1
0
1
0
1
T
T
M
M
T
T
M
T
2
24
C2
T
T
15
3S
57
T
M
T
T
9
T
T
T
T
M
41
19
T
63
51
T
T
M
M
T
31
T
T
47
T
3
25
T
0
1
0
1
0
1
0
1
0
1
T
M
20
T
10
M
T
T
T
36
T
M
T
T
52
T
42
26
M
T
T
37
59
T
53
43
T
T
T
T
T
T
5
27
T
T
T
M
49
T
T
M
T
T
T
M
M
M
33
T
M
M
M
T
T
4
58
M
T
T
T
T
M
6
28
T
C3
T
T
M
T
21
11
T
T
22
12
T
17
T
T
M
T
38
60
T
T
54
44
T
23
13
T
T
T
T
T
39
61
55
T
T
M
T
M
M
M
T
T
48
T
45
T
M
M
M
M
T
T
M
16
T
M
T
T
32
M
T
M
T
NOTES:
= No errors detected
Number = The number of the single bit-in-error
*
T
T
M
M
M
T
M
T
T
M
1
T
T
M
T
7
29
M
0'
T
T
T
M
T
T
M
T
M
M
T
T = Two errors detected
M = Three or more errors detected
TABLE 10.
KEY AC CALCULATIONS FOR THE 64-BIT CONFIGURATION
64-BIT
PROPAGATION DELAY
FROM
COMPONENT DELAY FOR IDT49C460 AC SPECIFICATIONS
TO
DATA
Check Bits Out
DATA
Corrected DATA Out
DATA
Syndromes Out
DATA
ERROR for 64 Bits
DATA
MULT ERROR for 64 Bits
+
+
(DATA TO SC) +
(DATA TO SC) +
(DATA TO SC) +
(DATA TO SC)
(DATA TO SC)
(CB TO SC, CODE 10 11)
(CB TO SC, CODE ID 11)
+
(CB TO DATA, CODE 1010)
(CB TO SC, CODE 10 11)
(CB TO ERROR, CODE 10 11)
(CB TO MULT ERROR, CODE ID 11)
S8-91
------------------,-,---------------------------------
IDT49C460/AlB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 11. 64-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODING
PARTICIPATING DATA BITS
GENERATED
CHECK BITS
PARITY
Co
Even (XOR)
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
Ca
Even (XOR)
X
X
X
X
X
X
X
X
C7
Even (XOR)
X
X
X
X
X
X
X
X
GENERATED
CHECK BITS
PARITY
16
17
18
19
20
21
Co
Even (XOR)
X
X
X
Ct
Even (XOR)
X
X
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
0
1
2
3
X
X
X
X
X
4
7
X
X
8
9
X
X
X
X
X
X
X
6
X
X
X
X
5
X
X
X
X
X
X
11
X
12
13
X
14
15
X
X
X
X
X
10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
28
29
30
31
PARTICIPATING DATA BITS
X
24
25
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C4
Even (XOR)
X
X
C5
Even (XOR)
X
X
X
X
X
X
X
X
Ce
Even (XOR)
X
X
X
X
X
X
X
X
C7
Even (XOR)
X
X
X
X
X
X
X
X
GENERATED
CHECK BITS
PARITY
42
43
46
47
Co
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
Cs
Even (XOR)
Ca
Even (XOR)
C7
Even (XOR)
GENERATED
CHECK BITS
PARITY
~
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
PARTICIPATING DATA BITS
32
C4
Even (XOR)
Even (XOR)
C7
Even (XOR)
33
X
34
X
35
X
X
36
38
39
X
X
X
X
X
X
X
X
X
37
X
X
X
X
X
40
X
X
X
X
X
X
X
X
X
X
41
X
44
4S
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
58
S9
62
63
X
PARTICIPATING DATA BITS
48
C5
Cs
X
X
X
X
X
X
23
X
X
X
22
X
49
X
50
S1
X
X
S2
54
55
X
X
X
X
X
X
X
56
X
X
X
X
X
X
Even (XOR)
X
X
X
X
X
X
X
X
NOTE:
The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table.
S8-92
57
X
X
X
X
X
53
X
60
61
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IDT49C460/AlB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SC OUTPUTS
The tables below indicate how the SCo-7 outputs are generated
in each control mode for various CODE IDs (Internal Control Mode
not applicable).
GENERATE
CODE 10i
00
CODE 101.0
10
11
CORRECTI
DETECT
00
0
10
11
SC o
i-
PHO
PH1
PH2 EB CBo
SC o
i-
PHOro CO
PH1
ffi
SCI
SC 2
i-
PA
PB
PA
PB
SCI
SC2
PA EB C1
PA
EB
i-
PB EB C2
PB EB C2
PA EB CBl
PB EB CB2
SC 3
i-
PC
PC
PA EB CB 1
PB EB CB 2
PC EB CB 3
i-
i-
SC3
i-
PC EB C3
PCEB C3
PC EB CB3
SC 4
i-
PO
PO
PO EB CB 4
SC4
i-
PO EB C4
PO EB C4
PC EB CB4
SC 5
i-
PE
PE
PE EB CB 5
SC5
i-
PE EB C5
PE EB CB5
SC e
i-
PF
PF
PF EB CBe
SCe
i-
PF EB C6
PE EB C5
PF EB C6
SC 7
i-
-
PF
PARTIAL
CHECK BITS
PG EB CB 7
FINAL
CHECK BITS
SC7
i-
-
PF EB C7
PARTIAL
SYNDROME
PG EB CB7
FINAL
SYNDROME
FINAL
CHECK BITS
DIAGNOSTIC
GENERATE
FINAL
SYNDROME
10
C1
PH2 EB CBo
PF EB CBe
CODE 101.0
11
DIAGNOSTIC
CORRECTI
DETECT
00
10
11
i-
PH2 EB CBo
CODE 101.0
00
CO
SCo
i-
DLO
DLO
DL32
SC o
PHO EB DLO
PH1 EB DLO
SCI
i-
DL1
DL1
DL33
SCI
i-
PA EB DL1
PA EB DL1
PA EB CBI
SC2
i-
DL2
DL2
DL34
SC2
i-
PB EB DL2
PB EB DL2
PB EB CB2
SC3
i-
DL3
DL3
DL35
SC3
i-
PC EB DL3
PC EB DL3
PC EB CB3
SC4
i-
DL4
DL4
DL36
SC4
i-
PO EB DL4
PO EB DL4
PO EB CB4
SC5
i-
DLS
DL5
DL37
i-
PE EB DL5
PE EB DL5
PE EB CB5
SCe
i-
DLB
DLB
DL38
SC5
SC e
i-
PF EB DL6
PF EB DL6
PF EB CBe
SC7
i-
-
DL7
PARTIAL
CHECK BITS
DL39
FINAL
CHECK BITS
SC7
i-
-
PF EB DL7
PARTIAL
SYNDROME
PG EB CB7
FINAL
SYNDROME
FINAL
CHECK BITS
PASSTHRU
SC o
i-
FINAL
SYNDROME
CODE 1D1.0
00
10
11
CO
CO
CBo
SCI
i-
C1
C1
CBl
SC 2
i-
C2
C2
CB2
SC3
i-
C3
C3
CB3
SC4
i-
C4
C4
CB4
SC5
i-
C5
C5
CB5
SC e
i-
C6
C6
CBe
SC7
i-
-
C7
CB7
S8-93
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA CORRECTION
FUNCTIONAL EQUATIONS
The tables below indicate which data output bits are corrected
depending upon the syndromes and the COOE ID!. oposition. The
syndromes that determine data correction are, in some cases, syndromes input externally via the CB inputs and, in some cases, syndromes input externally by that EOC (Si are the internal syndromes
and are the same as the value of the SCi output of that EOC if
enabled).
The equations below describe the lOT49C460 output values as
defined by the value of the inputs and internal states.
SYNDROME DECODE TO BIT CORRECTED
(32-BIT CONFIGURATION) CODE 10 1-0 = 00
I HEX 0 1 2 3 4 5 6
-HEX S3
0
1
2
3
0
0
0
4
5
0
0
0
6
7
0
0
8
1
9
A
B
C
1
1
1
1
1
1
1
D
SYNDROME
BITS
S2
0
0
0
S1
0
0
1
So
0
1
0
0
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
S6
S5
S4
1
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
- -
-
-
-
-
30
-
14
-
-
-
-
-
2
24
E
F
1
NOTE:
1.57 = 1 in CODE IDl,o = 00
8
-
-
-
-
-
15
-
3
25
-
9
-
-
-
-
31
-
-
4
·26
-
-
5
27
-
-
-
1
-
-
-
-
20
10
-
-
-
21
22
11
12
-
0
1
0
PC = 00 E9 01 E9 05 E9 06 EB 07 EB 011 E9 012 E9 013 E9
016 E9 017 E9 021 E9 022 EB 023 E9 027 E9 028 E9 029
0
0
1
- - - 18
- - 19
-
17
-
-
-
23
13
-
-
-
16
-
-
-
-
-
0
-
=
PA
00 E9 01 E9 02 E9 04 E9 06 E9 08 E9 010 E9 012 E9
016 E9 017 E9 018 E9 020 E9 022 E9 024 E9 026 E9 028
PB = 00 E9 03 E9 04 E9 07 EB 09 E9 010 EB 013 E9 015 EB
016 E9 019 E9 020 E9 023 E9 025 EB 026 E9 029 E9 031
7
1
1
1
0
0
0
DEFINITIONS
PO = 02 E9 03 E9 04 EB 05 EB 06 EB 07 EB 014 E9 015 ED
018 EB 019 EB 020 E9 021 EB 022 E9 023 E9 030 E9 031
PE = 08 ED 09 EB 010 E9 011 ED 012 E9 013 EB 014 E9 015
E9 024 E9 025 ED 026 EB 027 ED 028 E9 029 EB 030 E9 031
PF = 00 E9 01 E9 02 E9 03 ED 04 E9 05 ED 06 EB 07
E9 025 E9 026 E9 027 E9 028 E9 029 EB 030 EB 031
PG
EB
6
28
-
-
-
7
29
-
-
-
-
-
016
EB 017 EB
018
EB
019
EB
020
EB
021
ED
022
E9 023
=
PH1 = 01 E9 02 EB 03 E9 05 EB 08 EB 09 E9 011 E9 014 EB
017 E9 018 EB 019 EB 021 EB 024 E9 025 E9 027 E9 030
PH2 = 00
E9 016
031
-
-
= 08 E9 09 E9 010 E9 011 E9 012 EB 013 EB 014 E9 015
PHO
00 E9 04 EB 06 E9 07 EB 08 EB 09 E9 011 ED 014 EB
017 ED 018 E9 019 E9 021 EB 026 EB 028 E9 029 E9 031
-
-
E9 024
E9 04 EB 06 EB 07 EB 010 EB 012 E9 013 E9 015
E9 020 E9 022 EB 023 E9 026 EB 028 EB 029 E9
-
SYNDROME DECODE TO BIT CORRECTED (64-BIT CONFIGURATION)
I
SYNDROME
BITS
HEX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
57
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
C4
C5
-
C6
62
C7
-
-
46
-
14
-
-
-
-
-
-
-
-
30
56
50
40
-
-
-
34
-
-
-
-
-
-
-
-
24
-
57
-
51
41
-
-
2
35
-
31
63
-
47
-
-
-
-
3
4
36
58
-
-
52
-
37
59
-
-
53
42
43
-
-
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
33
-
-
49
-
38
60
-
-
-
-
-
-
Ss
S5
S4
~
.
HEX S3 S2 S1
0
0
0
0
1
0
0
0
0
0
2
1
So
0
1
0
CO
C1
-
-
0
0
0
1
0
1
0 ' 1
0
1
1
-
18
8
-
0
1
0
1
C2
-
-
15
-
19
20
9
10
-
C3
-
-
0
0
1
-
-
-
21
11
-
3
4
5
6
7
8
9
A
B
C
D
E
F
1
0
0
1
1
0
-
-
-
-
-
-
-
5
6
27
28
54
44
-
1
-
-
-
-
-
7
29
-
-
55
45
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
0
0
1
1
0
0
1
1
0
1
22
12
17
-
-
1
1
1
1
1
1
1
1
0
0
-
23
13
-
-
-
39
61
-
-
-
-
-
-
32
-
-
-
48
0
1
-
1
0
16
-
1
1
-
-
S8-94
26
-
1
1
-
-
-
-
-
-
-
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA= +25°C, f
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
Tft,
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
30
30
mA
PARAMETER(l)
CIN
Input Capacitance
COUT
Output Capacitance
= 1.0MHz)
TYP.
UNITS
VIN = OV
5
pF
VOUT= OV
7
pF
MAX.
UNIT
-
V
O.S
V
CONDITIONS
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IDC ELECTRICAL CHARACTERISTICS
Vee = 5.0V
Vcc = 5.0V
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vee - 0.2V
I SYMBOL
I
I
I
I
±
±
TEST CONDITIONS (1)
PARAMETER
MIN.
2.0
TYp,(2)
-
Input HIGH Level
Guaranteed Logie High Level
Input LOW Level
Guaranteed Logic Low Level (4)
IIH
Input HIGH Current
Vec = Max·,\'IN = Vee
-
0.1
5.0
JlA
IlL
Input LOW Current
Vce = Max·,\'IN = GND
-
-0.1
-5.0
JlA
VHe
2.4
Vcc
V
2.4
4.3
-
-
GND
0.3
U.;j
VLe
0.5
-
-0.1
0.1
-10.0
10.0
JlA
-30.0
-
-
mA
"'H
"'L
VOH
Vee
\'IN
Output HIGH Voltage
I
VOL
loz
Off State (High Impedance)
Output Current
Vcc = Max.
los
Output Short Circuit Current
Vce
I
(4)
-
IOH = -300J.l.A
IOH = -12mA MIL.
= Min.
= \'IH or \'IL
IOH
= -15mA COM'L.
= 300JlA
IOL
10L - 20mA MIL.
Vee = Min.
\'IN = \'IH or \'IL
Output LOW Voltage
I
I
5% (Commercial)
10% (Military)
-
IOL = 24mA COM'L.
Vo = OV
Vo - Vcc (Max.)
= Min., VOUT = OV (3)
~OTES:
I. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
!. Typical values are at Vce = 5.0V, + 25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
SS-95
- - - - - - - - _..
__._-_ __ ___ __._ __ - . _ - - - ..
..
..
..
....
..
4.3
V
U.b
IDT49C460/AlB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
Vee = 5.0V ± 5% (Commercial)
TA = -55°C to + 125°C
Vee = 5.0V ± 10% (Military)
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS
PARAMETER
Vcc
= Max.
'-"N' '-"N
loco
Quiescent Power Supply Current
(CMOS Inputs)
IOCT
Quiescent Input Power Supply
Current (per Input @TIL High)(5)
Vee
loco
Dynamic Power Supply Current
Vcc = Max.
S VLC
VHC S
Outputs Open, OE = L
VHC S
fop = 0
Total Power Supply Current (6)
MAX.
UNIT
-
3.0
5
mA
-
0.3
0.5
mAl
Input
MIL.
-
6
10
COM'L.
-
6
7
MIL.
-
60
110
COM'L.
-
60
80
MIL.
-
70
125
COM'L.
-
70
95
S VLC
= Max., V1N = 3.4V, fop = 0
'-"N, '-"N
Vec = Max., fop = 10MHz
Outputs Open, O"E = L
50% Duty cycle
loc
TYp'(2)
MIN.
(1)
VHC S
'-"N' '-"N
S VLC
Vec = Max.,f op = 10MHz
Outputs Open, OE = L
50% Duty cycle
'-"H = 3.4V, \IL = O.4V
mAl
MHz
mA
NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out Icco, then dividing by the total number of inputs.
6. Total Supply Current isthe sum ofthe Quiescent current and the Dynamic current (at either CMOS orTILinput levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = Iceo
+ ICCT (NT XDH) + ICCD (fop)
DH = Data duty cycle TIL high period ('-"N = 3.4V).
N~ = Number of dynamic inputs driven at TIL levels.
fop = Operating frequency in Megahertz.
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test
environment. Large output currents are being switched in very
short periods and proper testing demands that test set-ups have
minimized inductance and guaranteed zero lIoltage grounds~ The
techniques listed below will assist the user in obtaining accurate
testing results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may OSCillate, causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple powersupply lines and be placed as close as possible
to the DUT power pins.
S8-96
3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the DUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To allow
for testing and hardware-induced noise, IDT recommends using
V1L S OV and ~H;:: 3V for AC tests. .
--
-~
_...
_._-----------------
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460C over the OOC to + 70°C commercial temperature
range. All times are in nanoseconds and are measured at the 1.5V
signal level. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond. All outputs have maximum DC load.
Vcc equal to 5.0V ± 5%.
PROPAGATION DELAYS CL
= 50pF.
CORRECT
Not Intemal Control Mode
DIAG MODE
Not Intemal Control Mode
Intemal
Control
Mode
LEIN
From latched to transparent
J
LEDIAG
From latched to transparent;
Not Intemal Control Mode
J
15
19
ns
LEDIAG
From latched to
15
18
ns
DATA 0-31
Via Diagnostic Latch
13
16
ns
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
'Q'!; BYTE 0-3
'Q'!;sc
ENABLE
'-.
'-.
DISABLE
J
J
Output disable tests performed with CL = 5pF and
measured to 0 5V change of output voltage level
TO OUTPUT
DISABLE
MAX.
UNITS
MAX.
MIN.
DATA 0-31
10
23
10
19
ns
SCO-7
10
24
10
20
ns
MINIMUM PULSE WIDTHS
LE 1N • LE oUT • LE DIAG
58-97
--_. __ ._._._--_.
ENABLE
MIN.
. _ - - _.. - .._ - - - - "-'- ......
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460B over the O°C to + 70°C commercial temperature
range. All times are in nanoseconds and are measured at the 1.5V
signal level. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond. All outputs have maximum DC load.
Vee equal to 5.0V ± 5%.
PROPAGATION DELAYS c L = 50pF.
TO OUTPUT
FROM INPUT
SCO-7
ERROR
NiO[l' ERROR
UNITS
DATA 0-31
25
30
25
27
ns
CBO-7 (CODE ID 00,11)
14
30
17
20
ns
16
18
.../
-
12
~
CBO-7 (CODE ID 10)
LEoUT/G!:NERAiE
19
"-I
.../ I
ns
21
23
23
"-1
.../ I
23
ns
23
ns
21
-
CORRECT
Not Internal Control Mode
-
23
-
-
ns
DIAG MODE
Not Internal Control Mode
17
26
20
24
ns
CODE IDl.O
Internal
Control
Mode
DATAo-31
18
26
21
26
ns
LEIN
From latched to transparent
.../
27
38
30
3
ns
LEolAG
From latched to transparent;
Not Internal Control Mode
.../
15
29
19
22
ns
LEolAG
From latched to transparent
.../
16
32
19
24
ns
16
32
20
25
ns
SET-UP TIME
MIN,
HOLD TIME
MIN.
UNITS
LEIN
4
4
ns
LEIN
4
4
ns
LEoUTIGENERAiE
19
0
ns
LEouT/GENERAi!:
15
0
ns
LEoUT/GENERAiE
15
0
ns
LEoUT/GENERAT!:
11
-
ns
LEoUT/GENERAT!:
17
0
ns
LEoUT/GENERA iE
17
0
ns
LEoUT/GENERATE
20
-
ns
LEolAG
4
3
ns
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
TO
(LATCHING DATA)
FROM INPUT
"""""-
DATA 0-31
CBO-7
DATA 0-31
CBO-7 (CODE ID 00,11)
CBO-7 .(CODE ID 10)
/.../ "-
CORRECT
""1.../ "-
DIAG MODE
CODE ID1.0
LEIN
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
OE" BYTE 0-3
OE"sc
ENABLE DISABLE
""-
.../
.../
Output disable tests performed with C L = SpF and
measured to O.SV change of output voltage level.
TO OUTPUT
ENABLE
MIN.
MAX.
DISABLE
MIN.
MAX.
UNITS
DATA 0-31
10
23
10
19
ns
SCO-7
10
24
10
20
ns
MINIMUM PULSE WIDTHS
LE IN , LE oUT , LE OIAG
S8-98
---------------------------------------------------------------------------------------------------------IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460B over the -55°C to + 125°C military temperature
range. All times are in nanoseconds and are measured at the 1.5V
signal level. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond. All outputs have maximum DC load.
Vee equal to 5.0V ± 10%.
PROPAGATION DELAYS c L
I
= 50pF.
TO OUTPUT
FROM INPUT
ERROR
MUCi ERROR
UNITS
DATA 0-31
28
33
28
30
ns
CBO-7 (CODE ID 00,11)
17
33
20
23
ns
19
23
.../
-
15
'-
24
-
-
26
CBO-7 (CODE ID 10)
LEoUT/GEI\lERATE
CORRECT
Not Internal Control Mode
Internal
Control
Mode
DAT A o-31
SCO-7
DIAG MODE
Not Internal Control Mode
20
CODE ID1.0
21
22
24
'-I
.../ 1
26
26
ns
'-I
.../1
26
ns
26
ns
-
-
29
23
27
ns
29
24
29
ns
ns
LEIN
From latched to transparent
.../
30
41
33
36
ns
LEolAG
From latched to transparent;
Not Internal Control Mode
.../
18
32
22
25
ns
LEolAG
From latched to transparent
.../
19
35
22
27
ns
19
35
23
28
ns
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
SET-UP TIME
MIN.
HOLD TIME
MIN.
UNITS
LEIN
4
4
ns
LEIN
4
4
ns
23
0
ns
TO
(LATCHING DATA)
FROM INPUT
'"""""-
DATA 0-31
CBO-7
DATA 0-31
"""""-
LEoUT/GENERATE
CBO-7 (CODE ID 00,11)
"""""-
LEoUT/GENERA iE
18
0
ns
'-
LEoUT/GENERA TE
18
0
ns
""""""""""-
LEoUT/GENERA TE
14
-
ns
LEoUT/GENERATE
20
0
ns
LEouT/GENERATE
20
0
ns
LEoUT/GEI\lERATE
23
-
ns
LEolAG
4
3
ns
CBO-7 (CODE ID 10)
CORRECT
.../
DIAG MODE
CODE ID1,0
.../
LEIN
"""""-
"""""-
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
C5E" BYTE 0-3
'OE"se
ENABLE
""""""""""-
DISABLE
J
J
Output disable tests performed with C L = 5pF and
measured to 0.5V change of output voltage level.
TO OUTPUT
ENABLE
MIN.
DISABLE
UNITS
MAX.
MIN.
MAX.
21
ns
22
ns
DATA o_31
10
25
10
SCO-7
10
27
10
~
MINIMUM PULSE WIDTHS
12
LE 1N • LE oUT • LEolAG
S8-99
ns
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460A over the
to + 70 0
commercial temperature
range. All times are in nanoseconds and are measured at the 1.5V
signal level. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond. All outputs have maximum DC load.
Vee equal to 5.0V ± 5%.
ooe
e
PROPAGATION DELAYS c L = 50pF.
TO OUTPUT
FROM INPUT
SCO-7
ERROR
E~ROR
I'ViOCT
UNITS
DATA 0-31
27
33
ns
16
36
34
30
CBO-7 (CODE ID 00.11)
19
23
ns
CBO-7 (CODE ID 10)
16
20
19
21
-./
-
12
25
'-
'-I
21
-
-./ 1
25
CORRECT
Not Internal Control Mode
-
23
-
-
ns
DIAG MODE
Not Internal Control Mode
17
26
20
24
ns
LEouT/GE:NERATE
'-I
-./ I
ns
25
ns
25
ns
18
26
21
26
ns
LEIN
From latched to transparent
-./
27
38
30
33
ns
LEolAG
From latched to transparent;
Not internal Control Mode
-./
15
29
19
22
ns
LEolAG
From latched to transparent
-./
16
32
29
24
ns
16
32
20
25
ns
SET-UP TIME
MIN.
HOLD TIME
MIN.
UNITS
LEIN
5
4
ns
LEIN
5
23
4
ns
CODE ID1.0
Internal
Control
Mode
DATAo-31
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
TO
(LATCHING DATA)
FROM INPUT
DATA 0-31
CBO-7
DATA 0-31
CBO-7 (CODE ID 00,11)
CBO-7 (CODE ID 10)
CORRECT
DIAG MODE
CODE ID1,0
LEIN
'''''1-./ '''1-./ '-
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
OE" BYTE 0-3
OE"se
ENABLE
DISABLE
''-
-./
-./
0
ns
0
ns
LEouT/GENERA iE
15
15
0
ns
LEouT/GE:NERA iE
11
-
ns
LEoUT /GENERA iE
0
ns
LEoUT/GE:NERAiE
17
17
0
ns
LEouT/GE:NERA iE
25
-
ns
LEolAG
5
3
ns
LEouT/GENERAiE
LE OUT !GENERAiE
=
Output disable tests performed with C L
5pF and
measured to O.5V change of output voltage level.
TO OUTPUT
ENABLE
DISABLE
UNITS
MIN.
MAX.
MIN.
DATA 0-31
10
23
10
19
ns
SCO-7
10
24
10
20
ns
MINIMUM PULSE WIDTHS
LE 1N , LEo UT , LEolAG
S8-100
MAX.
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460A over the -SSoC to + 12SoC military temperature
range. All times are in nanoseconds and are measured at the 1.SV
signal level. The inputs switch between OV and 3V with signal transition rates of 1V per nanosecond. All outputs have maximum DC load.
Vee equal to S.OV ± 10%.
PROPAGATION DELAYS CL
= SOpF.
TO OUTPUT
FROM INPUT
MOLT
ERROR
UNITS
DATA 0-31
30
39
33
36
ns
CBO-7 (CODE ID 00,11)
19
37
22
26
ns
19
23
.../"
-
15
'--
24
-
-
26
CBO-7 (CODE ID 10)
LEouT/GE:filERATE
CORRECT
Not Internal Control Mode
Internal
Control
Mode
ERROR
DATAo-31
SCO-7
DIAG MODE
Not Internal Control Mode
20
CODE ID1.0
21
24
22
'--I
28
.../"1
28
'--I
.../"1
ns
28
ns
28
ns
-
-
ns
29
23
27
ns
29
24
29
ns
LEIN
From latched to transparent
.../"
30
41
33
36
ns
LEDIAG
From latched to transparent;
Not Internal Control Mode
.../"
18
32
22
25
ns
LEDIAG
From latched to transparent
.../"
19
35
22
27
ns
19
35
23
28
ns
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
TO
(LATCHING DATA)
FROM INPUT
SET-UP TIME
MIN.
HOLD TIME
- MIN.
UNITS
ns
DATA 0-31
'--
LEIN
5
4
CBO-7
'-'-'--
LEIN
LEoUT IGENERATE
5
4
ns
27
0
ns
LEouT/GENERATE:
18
0
ns
LEouT/GENERATE
18
0
ns
LEoUT/GEfilERATE
14
-
ns
LEoUT/GENERATE
20
0
ns
LEoUT/GENERAiE:
20
0
ns
LEouT/GENERATE
28
-
ns
LEDIAG
5
3
ns
DATA 0-31
CBO-7 (CODE ID 00,11)
'--
CBO-7 (CODE ID 10)
I.../" '-'--
CORRECT
DIAG MODE
'--
CODE ID1.0
I.../" '--
LEIN
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
DE BYTE 0-3
ot:se
ENABLE
DISABLE
'--
.../"
.../"
'--
Output disable tests performed with C L = SpF and
measured to O.5V change of output voltage level.
ENABLE
TO OUTPUT
MIN.
MAX.
DISABLE
MIN.
MAX.
UNITS
DATA o_31
10
25
10
21
ns
SCO-7
10
27
10
22
ns
MINIMUM PULSE WIDTHS
LE IN , LEoUT' LE DIAG
S8-101
-
------------
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
I DT49C460 over the 0 °c to + 70°C commercial temperature range.
All times are in nanoseconds and are measured at the 1.SV signal
level. The inputs switch between OV and 3V with signal transition
rates of 1V per nanosecond. All outputs have maximum DC load. Vcc
equal to S.OV ± S%.
PROPAGATION DELAYS c L
= SOpF.
TO OUTPUT
FROM INPUT
SCO-7
ERROR
MOLT ERROR
UNITS
ns
DATA 0-31
37
49
40
45
CBO-7 (CODE ID 00.11)
22
46
26
31
ns
CBO-7 (CODE ID 10)
22
30
26
29
ns
J"-
-
17
"""-
29
-
CORRECT
Not Internal Control Mode
-
31
-
-
ns
DIAG MODE
Not Internal Control Mode
23
35
27
33
ns
LEoUT /GENERATE
"""- I
30
"""- I
30
ns
J"-
30
J"-
30
ns
I
I
25
35
29
35
ns
LEIN
From latched to transparent
J"-
37
51
41
45
ns
LEolAG
From latched to transparent;
Not Internal Control Mode
J"-
21
38
26
30
ns
LEolAG
From latched to transparent
J"-
22
42
26
33
ns
22
42
27
34
ns
HOLD TIME
MIN.
UNITS
CODE ID1.0
Internal
Control
Mode
DATAo-31
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
TO
(LATCHING DATA)
FROM INPUT
DATA 0-31
CBO-7
DATA 0-31
CBO-7 (CODE ID 00,11)
CBo-7 (CODE ID 10)
CORRECT
IJ"-
DIAG MODE
CODE ID1.0
IJ"-
LEIN
"""""""""""""""""""""""""""-
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
~ BYTE 0-3
CJEsc
ENABLE
DISABLE
""""""-
J"J"-
SET-UP TIME
MIN.
LEIN
6
4
ns
LEIN
5
4
ns
LEoUT/GENERA iE
30
0
ns
LEoUT/GENERATE
20
0
ns
LEouT/GENERAiE
20
0
ns
LEouT/GENERAiE:
16
-
ns
LEoUT/GEI\iERAiE
23
ns
LEoUT/GENERAiE
23
0
0
LEoUT/GEI\iERAiE
31
-
ns
LE olAG
6
3
ns
ns
Output disable tests performed with C L = SpF and
measured to O.SV change of output voltage level.
TO OUTPUT
ENABLE
DISABLE
UNITS
MIN.
MAX.
MIN.
MAX.
DATA 0-31
10
27
10
23
ns
SCO-7
10
28
10
24
ns
MINIMUM PULSE WIDTHS
LE 1N , LEouT' LE olAG
S8-102
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460 over the -SSOCto + 12SoC military temperature range.
All times are in nanoseconds and are measured at the 1.SV signal
level. The inputs switch between OV and 3V with signal transition
rates of 1V per nanosecond. All outputs have maximum DC load. Vee
equal to S.OV ± 10%.
PROPAGATION DELAYS
CL
= SOpF.
TO OUTPUT
FROM INPUT
SC O-7
ERROR
DATAo-31
MULl' ERROR
UNITS
~
DATA 0-31
40
52
44
48
ns
CBO-7 (CODE ID 00, 11)
25
49
29
34
ns
CBO-7 (CODE ID 10)
25
33
.../"
-
20
'--
32
-
CORRECT
Not Internal Control Mode
-
34
-
-
ns
DIAG MODE
Not Internal Control Mode
26
38
30
36
ns
LEoUT/GENERA iE
\
\
CODE IDl.O
Internal
Control
Mode
32
29
'--I
33
.../"1
33
'--1
.../"1
ns
33
ns
33
ns
28
38
32
38
ns
LEIN
From latched to transparent
.../"
40
54
44
48
ns
LEDIAG
From latched to transparent;
Not Internal Control Mode
.../"
24
42
29
33
ns
LEDIAG
From latched to transparent
.../"
25
47
29
36
ns
25
47
30
37
ns
HOLD TIME
MIN.
UNITS
DATA 0-31
Via Diagnostic Latch
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
TO
(LATCHING DATA)
FROM INPUT
SET-UPTIME
MIN.
DATA 0-31
"-
LEIN
6
4
ns
CBO-7
'-'-'-'-'-'-'-'--
LEIN
5
4
ns
LEoUTf(jEI\IERATE
36
0
ns
LEoUTf(jEI\IERAiE
24
0
ns
LEoUT/GENERAiE
24
0
ns
LEoUT/GENERAiE
20
-
ns
LEoUT/GENERAiE
28
0
ns
LEoUT/GENERAiE
28
0
ns
LE oUTf(jENERATE
37
-
ns
LEDIAG
6
3
ns
DATA 0-31
CBO-7 (CODE ID 00,11)
CB O- 7 (CODE ID :10)
CORRECT
.../"
DIAG MODE
CODE ID1. 0
.../"
LEIN
DATA 0-31
OUTPUT ENABLE/DISABLE TIMES
FROM INPUT
OE' BYTE 0-3
OE'sc
ENABLE DISABLE
"-
"'-
.../"
.../"
Output disable tests performed with C L = SpF and
measured to O.SV change of output voltage level.
TO OUTPUT
ENABLE
DISABLE
UNITS
MIN.
MAX.
MIN •
MAX.
DATA 0-31
10
29
10
25
ns
SCO-7
10
30
10
26
ns
rMiN.l
MINIMUM PULSE WIDTHS
15
LE IN ' LE oUT , LE DIAG
ns
S8-103
--_... _._---._-----------
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C TIMING:
DATA SHEET PARAMETERS
GENERATE Mode
(from DETECT or CORRECT Mode)
PROPAGATION, DELAY
FROM
'
TO
MIN./MAX.
OEby"fe
trEbyfe = High to DATA out Disabled
C5EOytEi = High to DATA out Disabled
C5Ebyte = Low to DATA out Enabled
C5EOytEi = Low to DATA out Enabled
Min.
Max.
CB in to DATA out
Max.
Min.
Max.
valid DATA in
DATA bus
~-------16------~~
valid checkbits in
CBin
(CODE ID 1. 0 = 10)
LEin
LEout/GEN:'
(Generate mode)
LEout/GENERATE = Low to
ERRORfMERROR = High
LEout/GENERA TE = Low to SC out
Max.
Max.
18
DATA In to SC out
Max.
*LE in = High to SC out*
Max.
CB in to SC out
Max.
18
104------- 22* - - - - . {
(CODE ID 1,0 = 10)
""'I-f.----
(forced high)
14
-----I-.j
ERRfMERR
orsc =
OESC
OESC
OESC
High to SC out Disabled
= High to SC out Disabled
Min.
Max.
= Low to SC out Enabled
= Low to SC out Enabled
Min.
Max.
(check bits exit)
SCout
(don't care)
CORRECT
XXXXXXXXXXXXXXXXXXXXXXXXXXX
NOTES:
1. BOLD indicates critical parameters.
2. Valid "DATA" and valid "CBin" are shown to occur simultaneously, since both busses are latched and opened by the "LEin" input.
*Assumes DATA bus becomes input 4ns before LEin goes high.
S8-104
IDT49C460/AiB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C TIMING:
DATA SHEET PARAMETERS
DETECT or CORRECT Mode
(from GENERATE Mode)
OE>Yte
\SSS\t
,-
10
~20
.
MIN./MAX.
~ = High to DATA out Disabled
0'EJJyte= High to DATA out Disabled
Min.
Max.
0EbYt9
Min.
Max.
= Low to DATA out Enabled
OEbyte = Low to DATA out Enabled
(corrected DATA if Correct mode)
(DATA in if Detect mode)
valid DATA in
DATA bus
PROPAGATION DELAY
FROM
TO
~--------24--------~
CBin
DATA In to DATA out
Max.
CORRECT = High to DATA out
Max.
valid checkbits in
1-01----
16 ----to!
CORRECT
CB in to DATA out
Max.
CB in to DATA out
Max.
*LE in = High to DATA out*
Max.
LEouVGENERATE = High to DATA out
LEouVGENERAfE = High to
Max.
Max.
CODE 10 1. 0 = 00.11
CODEID1.0=10
....- - - - - - 28*
------~
LEin
LEou~
~=Low
LEouV''''G''''E''''N''''E''''R'TA....
f7'''E = High to ~ = Low
DATA in to 'E'R'ROR
= Low
Max.
Max.
CBinto~ = Low
Max.
*LE in = High to ~ = Low*
Max.
(Low = error)
DATA in to ~ = Low
Max.
CBinto~ = Low
Max.
*LE in = High to MERROR = Low*
Max.
(Low = error)
SCout
DATA in to SC out
Max.
CB in to SC out
Max.
OEsc = High to SC out Disabled
Min.
0ESc = High to SC out Disabled
Max.
0ESc = Low to SC out Enabled
0ESc = Low to SC out Enabled
Max.
(syndrome bits come out)
NOTES:
1. BOLD indicates critical parameters.
*Assumes NCB in" and/or "DATA in" are valid at least 4ns before "LE in" goes high.·
S8-105
Min.
IDT49C460/A/B/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C TIMING:
DATA SHEET PARAMETERS
SET-UP and HOLD Times
and Minimum PULSE WIDTHS
SET-UP/HOLD TIME
OF WITH RESPECT TO
MIN./MAX.
CBin
LEin
CB in Set-up to LE in = Low
Min.
CB in Hold to LE in = Low
Min.
LE in width
Min.
*LE in = High to LEout/GENERATE = Low*
Min.
DATA Set-up to LE in = Low
Min.
DATA Hold to LE in = Low
Min.
CB in Set-up to LEout/GENERATE = Low
Min.
CB in Set-up to LEout/GENERATE = Low
Min.
DATA Set-up to LEout/GENERATE = Low
Min.
LEout/GENERATE Width
Min.
CORRECT Set-up to
LEout/GENERATE = Low
Min.
DATA (in)
CODE ID = 00,11
CODE ID = 10
LEou~
CORRECT
________---J4= 6 ~'-_ _
t=8~
______....JI
NOTES:
1. BOLD indicates critical parameters.
* Enable to enable timing requirementto ensure that the last DATA word applied to "DATA in" is made available as "DATA out"; assumes that
"DATA in" is valid at least 4ns before "LE in" goes high.
S8-106
IDT49C460lAlB/C 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT/OUTPUT INTERFACE CIRCUIT
ESD
PROTECTION
INPUTS
OUTPUTS
Figure 11. Input Structure (All Inputs)
Figure 12. Output Structure
TEST LOAD CIRCUIT
Vcc
.--a7.0V
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All other outputs
Open
500.0
PULSE
GENERATOR
VIN
500.0
RT
Definitions:
C L = Load capacitance includes jig and probe capacitance.
R T = Termination should be equal to ZOUT of pulse generator.
Figure 13.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
Wins
1.5V
1.5V
See Figure 13
ORDERING INFORMATION
IDT
49C460
Device Type
X
X
X
Speed
Package
Process/
Temperature
Range
IL...-----l.I BLANK
B
L
L...-_ _ _ _ _ _ _
~
JG
PG
QE
L...-_ _ _ _ _ _ _ _ _ _ _~
Blank
A
B
C
~---------------~ 49C460
S8-107
---------._-_._--------
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Leadless Chip Carrier (50 mil centers)
Pin Grid Array
Plastic Leaded Chip Carrier
Plastic Pin Grid Array
Ceramic Quad Flat Pack
Standard Speed
High-Speed
Very High-Speed
Ultra-High-Speed
32-Bit E.D.C.
t;)
Integrated Dev1ce1OOmology.1nc.
32-BIT FLOW-THRU
ERROR DETECTION AND
CORRECTION UNIT
ADVANCE
INFORMATION
IDT 49C465
MICROSLICE TM PRODUCT
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT49C465 is a 32-bit, two-data bus, Flow-thru EDC TM unit.
The chip provides single-error correction, and multiple-error detection of both hard and soft memory errors. It can be expanded to
64-bit widths by cascading 2 units, without the need for additional
external logic. The Flow-thru EDC has been optimized for speed
and simplicity of control.
The EDC unit has been designed to be used in either of two configurations in an error correcting memory system. The bi-directional
configuration is most appropriate for systems using bl-directional
memory busses. A second system configuration utilizes external
octal buffers, and is particularly well suited for systems using memory with separate I/O busses.
32-bit Wide Flow-thru EDC Unit
Expandable to 64-bits
Single-chip 64-bit Generate Mode
Separate System and Memory Busses
On-chip Pipeline Register With External Control
Corrects All Single-bit Errors
Detects All Double-bit Errors, Some Multiple-bit Errors
Error Detection Time-20ns
Error Correction Time-25ns
Internal Syndrome Register
Four-bit Error Counter and:Error Data Register On-chip
Parity Generation on System Data Bus
Low Power CMOS-100mA typical
144-pln PGA & 164-pin Ceramic Quad Flatpack Packages
FUNCTIONAL BLOCK DIAGRAM
MDO- 31
CBO O_7
CSOE"
MOE
SYOO_7
PCBI
MLE
CBI
SDO- 31
~
PO- 3
PSEL
BEo-3
CODE ID 1,0
MODE 1,0
SOE"
SLE
SYNCLK
SCIJ
9
8 7
6 5
4
3
VSSO
ACCTYPEOUTO
ACCTYPEOUT1
ADDROUT7
ADDROUT6
DATAOUT3
DATAOUT2
DATAOUT1
DATAOUTO
DATAOUT8
ADDROUTO
ADD ROUT1
ADDROUT2
ADDROUT3
ADDROUT4
ADDROUT5
VSS1
2
.,
....
0
zz
.
00 z
i=i= W
00
cncn !:i0
(')
a.. a.. O~
1 6867 6665 646362 61
Index
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS3
MATCHIND
MATCHINC
MATCHINB
MATCHINA
LATCHERRADR
ADDRIN7
ADDRIN6
ADDRIN5
ADDRIN4
ADDRIN3
ADDRIN2
ADDRIN1
ADDRINO
DATAIN8
DATAIN7
VSS2
2728293031 32 333435363738394041 4243
PLCC
CEMOS is a trademark of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-7044/-
S9-14
-------------------------------------
IDT79R2020A RISC CPU WRITE BUFFER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1,3)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
"IN
Input Voltage (2)
-0.5 to +7.0
-0.5 to +7.0
V
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 5%
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V1N minimum = 3.0V for pulse width less than 15ns. V1N should not
exceed Vcc + 0.5 volts.
3. Not more than one output at a time should be shorted. Duration of the
short should not exceed 30 seconds.
S9-15
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------
Vee
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R2020A RISC CPU WRITE BUFFER
DC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE (fA = O°Cto·+
SYMBOL
PARAMETER
70°C, Vee
=
+5V± 5%)
TEST CONDITIONS
12.5 MHz
MIN.
MAX.
16.67 MHz
MIN.
MAX.
UNIT
VOH
Output HIGH Voltage
Vee = Min., IOH = -4rnA
3.5
-
3.5
-
V
VOL
Output LOW Voltage
Vee = Min.; IOL = 4rnA
-
0.4
-
0.4
V
V
Input HIGH Voltage (1)
2.4
-
2.4
-
"'L
Input LOW Voltage (2)
-
0.8
-
0.8
V
CIN
Input Capacitance
10
10
-
pF
COUT
Output Capacitance
10
-
10
-
pF
Icc
Operating Current
Vec = Max.
-
50
50
rnA
"'H
IIH
Input HIGH Leakage
'-"H = "cc
-
10
-
10
J-IA
IlL
Input LOW Leakage
VIL = GND
-10
-
-10
-
J-IA
loz
Output Tri-state Leakage
VOH = 2.4V, VOL = 0.5V
-40
40
-40
40
J-IA
NOTES:
1. VIH should not be held above Vee + 0.5 Volts.
2. VIL Min. = -3.0V for less than 15ns. VIL should not fall below -0.5V for longer periods.
DC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE (fA = -55°C to
SYMBOL
PARAMETER
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
+ 125°C Vec = +5V+10%)
-
TEST CONDITIONS
12.5 MHz
MIN.
MAX.
16.67 MHz
MIN.
MAX.
UNIT
Vec = Min., IOH = -4rnA
3.5
-
3.5
-
V
Vcc = Min., IOL = 4rnA
-
0.4
-
0.4
V
Input HIGH Voltage (1)
2.4
-
2.4
-
V
Input LOW Voltage (2)
-
0.8
-
0.8
V
CIN
Input Capacitance
10
-
10
10
-
10
-
pF
COUT
Output Capacitance
Icc
Operating Current
-
90
90
rnA
"'H
"'L
pF
IIH
Input HIGH Leakage
'-"H = 'be
10
-
10
J-IA
IlL
Input LOW Leakage
VIL ,;; GND
-10
-
-10
-
J-IA
loz
Output Tri-state Leakage
VOH = 2.4V, VOL = 0.5V
-40
40
-40
40
J-IA
Vee = Max.
NOTES:
1. VIH should not be held above Vee + 0.5 Volts.
2. VIL Min. = -3.0V for less than 15ns. VIL should not fall belOW -0.5V for longer periods.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R2020A RISC CPU WRITE BUFFER
AC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE (fA
= O°Cto + 70°C. Vee = +5V+
- 5%)
12.5 MHz
MAX.
MIN.
PARAMETER
SYMBOL
16.67 MHz
MIN.
MAX.
UNIT
12
-
8
-
ns
4
-
4
-
ns
Address 1:0 to Clock falling set-up
12
-
8
t4
Address 1:0 to Clock falling hold
4
-
4
ns
t5
Access Type 1:0 to Clock rising set-up
10
-
7
-
t1
t2
t3
Addrin (3:0) to Clock falling set-up
Addrin (3:0) to Clock falling hold
ns
ns
t6
Access Type 1:0 to Clock rising hold
4
-
ns
Addrin (7:4) to Clock rising set-up
10
-
3
t7
7
-
ns
t8
Addrin (7:4) to Clock rising hold
4
-
3
-:
ns
t9
Dataln (8:0) to Clock rising set-up
10
-
7
-
ns
no
Dataln (8:0) to Clock rising hold
4
3
-
ns
t11
WrtMem* to Clock rising set-up
14
-
10
-
ns
t12
WrtMem* to Clock rising hold
8
-
6
-
ns
t13
Request from Clock rising
-
35
-
32
ns
t14
Acknowledge to Clock rising set-up
15
12
-
ns
t15
Acknowledge to Clock rising hold
7
7
-
ns
t16
latchErrAdr rising to Acknowledge
5
-
5
-
ns
t17
WbFull* active from Clock rising
-
35
32
ns
t18
WbFull* inactive from Clock rising
-
35
-
32
ns
t19
OutEn to AddrOut (7:0). DataOut (8:0) valid
5
20
2
15
ns
t20
OutEn to AddrOut (7:0). DataOut (8:0) tn-state
5
20
2
15
ns
t21
MatchOut (ABCD) from Clock rising
-
35
-
25
ns
t22
Matchln (ABCD) from Clock rising set-up
15
Matchln (ABCD) from Clock rising hold
4
-
10
t23
3
-
ns
ns
t24
EnErrAdr* to Data (error latch) valid
5
20
2
15
ns
t25
EnErrAdr* to Data (error latch) tn-state
5
20
2
15
ns
t26
Address/Data out from Clock rising
-
35
-
32
ns
t27
Reset* to Clock rising. set-up
9
8
-
ns
t28
Reset* from Clock rising. hold
4
-
3
-
ns
t29
Reset* low pulse width
12
-
10
-
ns
t30
WbFull* High from Clock rising (after Reset*)
3
24
3
22
ns
t31
Request* High from Reset* low
3
22
3
20
ns
t32
Access Type 1:0 low from Reset* low
3
28
3
28
ns
t33
Match Out (ABeD) low from Reset* low
3
23
3
21
ns
S9-17
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R2020A RISC CPU WRITE BUFFER
AC ELECTRICAL CHARACTERISTICS - MILITARYTEMPERATURE RANGE (TA =
12.5 MHz
MIN.
MAX.
PARAMETER
SYMBOL
-55°C to + 125°C '6c= +5V +
- 10%)
16.67 MHz
MIN.
MAX.
UNIT
-
ns
-
ns
7
3
-
ns
7
-
ns
3
-
ns
ns
t1
Addrin (3:0) to Clock falling setup
12
-
8
t2
Addrin (3:0) to Clock falling hold
4
-
4
t3
Address 1:0 to Clock falling setup
12
-
8
t4
Address 1:0 to Clock falling hold
4
-
4
t5
Access Type 1:0 to Clock rising setup
10
t6
Access Type 1:0 to Clock rising hold
4
t7
Addrin (7:4) to Clock rising setup
10
t8
Addrin (7:4) to Clock rising hold
4
-
ns
ns
ns
t9
Dataln (8:0) to Clock rising setup
10
-
7
-
t10
Dataln (8:0) to Clock rising hold
4
3
-
ns
t11
WrtMem to Clock rising setup
14
10
-
ns'
t12
WrtMem to Clock rising hold
8
-
6
-
ns
t13
Request from Clock rising
-
35
-
32
ns
t14
Acknowledge to Clock rising setup
15
-
12
-
ns
t15
Acknowledge to Clock rising hold
7
7
-
ns
t16
LatchErrAdr rising to Acknowledge
5
-
5
-
ns
t17
WbFulJ active from Clock rising
35
ns
WbFulJ inactive from Clock rising
35
-
32
t18
-
32
ns
t19
OutEn to AddrOut (7:0). DataOut (8:0) valid
5
20
2
15
ns
t20
OutEn to AddrOut (7:0). DataOut (8:0) tri-state
5
20
2
15
ns
t21
MatchOut (ABCD) from Clock rising
-
35
-
25
ns
t22
Matchln (ABCD) from Clock rising setup
15
10
Matchln (ABCD) from Clock rising hold
4
3
-
ns
t23
-
t24
EnErrAdr to Data (error latch) valid
5
20
2
15
ns
ns
t25
EnErrAdr to Data (error latch) tri-state
5
20
2
15
ns
t26
Address/Data out from Clock rising
-
35
-
32
ns
t27
Reset· to Clock rising. set-up
9
-
ns
Reset· from Clock rising. hold
4
3
Reset· low pulse width
12
10
-
ns
t29
-
8
t28
t30
WbFulJ· High from Clock rising (after Reset·)
3
24
10
22
ns
t31
Request· High from Reset· low
3
22
10
20
ns
t32
Access Type 1:0 low from Reset· low
3
28
12
28
ns
t33
Match Out (ABCD) low from Reset· low
3
23
10
21
ns
S9-18
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R2020A RISC CPU WRITE BUFFER
ORDERING INFORMATION
IDT79R2020A
xx
x
x
Speed
Package
Process/
Temp. Range
59-19
Blank
'S'
Commercial
Military
'G'
'J'
68-Pin PGA
68-Pin PLCC
'12'
'16'
12.5 MHz
16.67 MHz
~
RISC CPU PROCESSOR
PRELIMINARY
lOT 79R3000
Integmted Device1echnoIosy.1nc.
FEATURES:
• Supports independent multiword block refill of both the instruction and data caches with variable block sizes.
• Supports concurrent refill and execution of instructions.
• Partial word stores executed as read-modify-write operations.
• 6 external interrupt inputs (up to 64 different sources), 2 software interrupts, with Single cycle latency to interrupt handler
routine.
• Flexible multiprocessing support on chip with no impact on
uniprocessor designs.
• Military product compliant to MIL-STD-883, Class B.
• Enhanced instruction set compatible version of the
IDT79R2000 RISC CPU.
• Full 32-bit Operation - Thirty-two 32-bit registers and all
instructions and addresses are 32-bit.
• Efficient Pipelining- The CPU's 5-stage pipeline design
assists in obtaining an execution rate approaching one
instruction per cycle. Pipeline stalls and exceptions are
handled precisely and efficiently.
• On-Chip Cache Control- The IDT79R3000 provides a high
bandwidth memory interface that handles separate external
Instruction and Data Caches ranging in size from 4 to
256 Kbytes each. Both the caches are accessed during a
single CPU cycle. All cache control is on-chip.
DESCRIPTION:
The IDT 79R3000 RISC Microprocessor consists of two tightlycoupled processors integrated on a single Chip. The first processor
is a full 32-bit CPU based on RISC (Reduced Instruction Set
Computer) principles to achieve a new standard of microprocessor
performance. The second processor is a system control
coprocessor, called CPO, containing a fully-associative 64 entry
TLB (Translation Lookaside Buffer), MMU (Memory Management
Unit) and control registers, supporting a 4 Gigabyte virtual memory
subsystem, and a Harvard Architecture Cache Controller
achieving a bandwidth of 200 Mbytes/second using industry
standard static RAMs.
This data sheet provides an overview of the features and
architecture of the 79R3000 CPU, Revision 2.0. A more detailed
description of the operation of the device is incorporated in the
"R3000 Family Hardware User Manual", and a more detailed
architectural overview is provided in the "mips RISCArchitecture"
book, both available from IDT. Documentation providing details of
the software and development environments supporting this
processor are also available from IDT.
• On-Chip Memory Management Unit-A fully-associative, 64
entry Translation Lookaside Buffer (TLB) provides fast address translation for virtual-to-physical memory mapping of
the 4 Gigabyte virtual address space.
• Coprocessor Interface-The IDT79R3000 generates all
addresses and handles memory interface control for up to
three additional tightly coupled external processors.
• Optimizing Compilers are available for C, Fortran, Pascal,
COBOL, Ada, and Pl/1.
• UNIX Tlol System V.3 and BSD 4.3 operating systems
supported.
• High-speed CEMOS Tlol technology.
• Instruction set compatible with the IDT79R2000 RISC CPU.
• 16.7MHz and 25MHz clock rates yield 12 and 20 MIPS
sustained throughput.
IDT79R3000 PROCESSOR
CONTROL
CPO
CPU
(System Control Coprocessor)
Exception I Control
Registers
Memory
Management
Unit Reigsters
General Registers
Local
Control
Logic
Translation
Lookaside
Buffer
(64 entries)
(32x32)
ALU
Shifter
Multiplier/Divider
Address Adder
PC Increment/Mux
Oata(32 +4)
ADDRESS(18)
CEMOS is a trademark of Integrated Device Technology. Inc.
UNIX is a registered trademark of AT & T.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 MIPS Computer Systems, Inc. All Rights Reserved.
JANUARY 1989
OSC-9021/1
S9-20
IDT79R3000 RISC CPU PROCESSOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 CPU Registers
The CPU registers are shown in Figure 2. Note that there is no
Program Status Word (PSW) register shown in this figure: the
functions traditionally provided by a PSW. register are instead
provided in the Status and Cause registers incorporated within the
System Control Coprocessor (CPO).
The lOT 79R3000 CPU provides 32 general purpose 32-bit
registers, a 32-bit Program Counter, and two 32-bit registers that
hold the results of integer multiply and divide operations. Only two
of the 32 general registers have a special purpose: register rO is
hardwired to the value "on, which is a useful constant, and register
r31 is used as the link register in jump-and-link instructions (return
address for subroutine calls).
General Purpose Registers
31
0
0
r1
r2
Multiply / Divide Registers
31
0
HI
31
0
I
I
•
•••
I
I
LO
Program Counter
31
r29
r30
r31
I
o
PC
Figure 2. IDT79R3000 CPU Registers
Instruction Set Overview
the compilers are able to fill these latency cycles with useful
instructions which do not require the result of the previous
Instruction. This effectively eliminates these latency effects.
The actual Instruction set of the CPU was determined after
extensive simulations to determine which instructions should be
implemented in hardware, and which operations are best
synthesized in software from other basic instructions. This
methodology resulted in the R3000 having the highest
performance of any available microprocessor.
All lOT 79R3000 instructions are 32 bits long, and there are only
three instruction formats. This approach simplifies instruction
decoding thus minimizing instruction execution time. The
79R3000 processor initiates a new instruction on every run cycle,
and is able to complete an instruction on almost every clock cycle.
The only exceptions are the Load instructions, and Branch
instructions which each have a single cycle of latency associated
with their execution. Note, however, that in the majority of cases
I-Type (Immediate)
31
26 25
21 20
16 15
I op I rs I rt
0
immediate
I
J-Type (Jump)
31
26 25
0
Ir -o-p=rl~----ta-rg-e-t------~I
R-Type (Register)
31
26 25
21 20
16 15
I op I rs ! rt
1110
rd
I
6 5
re !funct
0
I
Figure 3. IDT79R3000 Instruction Formats
The I0T79R3000 instruction set can be divided into the follow. ing groups:
• Load/Store instructions move data between memory and
general registers. They are alii-type instructions, since the only
addressing mode supported is base register plus 16-bit, signed
immediate offset.
The Load instruction has a single cycle of latency, which means
that the data being loaded is not available to the instruction
immediately after the load instruction. The compiler will fill this
delay slot with either an instruction which is not dependent on
the loaded data, or with a NOP instruction. There is no latency
associated with the store instruction.
S9-21
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3000 RISC CPU PROCESSOR
Loads and Stores can be performed on byte, half-word, word, or
unaligned word data (32 bit data not aligned on a mocful0-4
address). The CPU cache is constructed as a write-through cache.
• Computational Instructions perform arithmetic, logical and
shift operations on values in registers. They occur in both R-type
(both operands and the result are registers) and I-type (one
operand is a 16-bit immediate) formats.
Note that computational instructions are three operand instructions; that is, the result of the operation can be stored into a
different register than either of the two operands. This means
that operands need not be overwritten by arithmetic operations.
This results in a more efficient use of the large register set.
• Jump and Branch instructions change the control flow of a
program. Jumps are always to a paged absolute address
formed by combining a 26-bit target with four bits of the Program
counter (J-type format, for subroutine calls), or 32-bit register
byte addresses (R-type, for retums and dispatches). Branches
have 16-bit offsets relative to the program counter (I-type).·
S9-22
Jump and Link instructions save a retum address in Register 31.
The 79R3000 instruction set features a number of branch conditions. Included is the ability to compare a register to zero and
branch, and also the ability to branch based on a comparison
between two registers. Thus, net performance is increased
since software does not have to perform arithmetiC instructions
prior to the branch to set up the branch conditions.
• Coprocessor instructions perform ope~ations in the coprocessors. Coprocessor Loads and Stores are I-type. Coprocessor
computational instructions have coprocessor-dependent
formats (see coprocessor manuals).
• Coprocessor 0 instructions perform operations on the System
Control Coprocessor (CPO) registers to manipulate the memory
management and exception handling facilities of the processor.
• Special instructions perform a variety of tasks. including movement of data between special and general registers. system
calls. and breakpOint. They are always R-type.
Table 1 lists the instruction set of the IDT79R3000 processor.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
OP
DESCRIPTION
OP
Multiply/Divide Instructions
Load/Store Instructions
LH
LHU
LW
LWL
LWR
Load
Load
Load
Load
Load
Load
Load
SB
SH
SW
SWL
Store Byte
Store Halfword
Store Word
Store Word Left
SWR
Store Word Right
LB
LBU
DESCRIPTION
Byte
Byte Unsigned
Halfword
Halfword Unsigned
Word
Word Left
Word Right
MULT
MULTU
Multiply
Multiply Unsigned
DIV
DIVU
Divide
Divide Unsigned
MFHI
MTHI
MFLO
MTLO
Move From HI
Move To HI
Move From LO
Move To LO
J
JAL
JR
JALR
Jump
Jump and Unk
Jump to Register
Jump and Unk Register
BEQ,
Branch on Equal
Branch on Not Equal
Jump and Branch Instructions
I
Arithmetic Instructions
(ALU Immediate)
ADDI
ADDIU
SLTI
SLTIU
Add Immediate
Add Immediate Unsigned
Set on Less Than Immediate
Set on Less Than Immediate
Unsigned
BNE
BLEZ
BGTZ
BLTZ
BGEZ
ANDI
ORI
XORI
AND Immediate
OR Immediate
Exclusive OR Immediate
BLTZAL
BGEZAL
Branch on Less Than Zero and Unk
Branch on Greater than or Equal to
Zero and Unk
LUI
Load Upper Immediate
SYSCALL
System Call
Break
Branch on Less than or Equal to Zero
Branch on Greater Than Zero
Branch on Less Than Zero
Branch on Greater than or
Equal to Zero
Special Instructions
Arithmetic Instructions
(3-operand, register-type)
ADD
ADDU
SUB
SUBU
Subtract
Subtract Unsigned
SLT
SLTU
Set on Less Than
AND
AND
OR
Exclusive OR
NOR
OR
XOR
NOR
BREAK
Add
Add Unsigned
Coprocessor Instructions
Set on Less Than Unsigned
LWCz
SWCz
MTCz
Load Word from Coprocessor
Store Word to Coprocessor
Move To Coprocessor
MFCz
CTCz
Move From Coprocessor
Move Control to Coprocessor
CFCz
COPz
Move Control From Coprocessor
Coprocessor Operation
BCzT
BCzF
Branch on Coprocessor z True
System Control Coprocessor
(CPO) Instructions
Shift Instructions
SLL
SRL
SRA
SLLV
SRLV
SRAV
Branch on Coprocessor z False
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic
Shift Left Logical Variable
Shift Right Logical Variable
Shift Right Arithmetic Variable
MTCO
MFCO
Move To CPO
Move From CPO
TLBR
TLBWI
TLBWR
TLBP
Read indexed TLB entry
Write Indexed TLB entry
Write Random TLB entry
Probe TLB for matching entry
RFE
Restore From Exception
Table 1. IDT79R3000 Instruction Summary
S9-23
-------------,------------------,-------
------------.,.,,-- - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
and supports the virtual memory system and exception handling
functions of the IDT79R3000. The virtual memory system is
implemented using a Translation Lookaside Buffer and a group of
programmable registers as shown in Figure 4.
IDT79R3000 System Control Coprocessor (CPO)
The IDT79R3000 can operate with up to four tightly-coupled
coprocessors (designated CPO through CP3). The System Control
Coprocessor (or CPO). is incorporated on the IDT79R3000 chip
System Coprocessor
ENTRYH I
I
ENTRYLO
"
.
II
.::11
~
._--1
63
RANDOM
,
.~
~~~:~~l
TLB
;';V;«':v:«''''''''?
8
7
o
NOT ACCESSED BY RANDOM
Figure 4. The System Coprocessor Registers
o
Used with Virtual Memory System
EZJ Used with Exception Processing
System Control Coprocessor (CPO) Registers
REGISTER
The CPO registers shown in Figure 4 are used to control the
memory management and exception handling capabilities of the
IDT79R3000. Table 2 provides a brief description of each register.
EntryHi
EntryLo
Index
. Random
Status
Cause
EPC
Context
DESCRIPTION
High half of a TLB entry
Low half of a TLB entry
Programmable pOinter into TLB array
Pseudo-random pointer into TLB array
BadVA
Mode. interrupt enables. and diagnostic status Info
Indicates nature of last exception
Exception Program Counter
Pointer into kernel's virtual Page Table Entry array
Most recent bad virtual address
PRld
Processor revision Identification
Table 2. System Control Coprocessor (CPO) Registers
S9-24
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
64 entries, each of which maps a 4-Kbyte page, with controls for
read/write access, cacheablllty, and process identification. The
TLB allows each user to access up to 2 Gbytes of virtual address
space.
Figure 5 illustrates the format of each TLB entry. The Translation
operation involves matching the current Process ID (PID) and upper 20 bits of the address against PID and VPN (Virtual Page Number) fields in the TLB. When both match (or the TLB entry is
Global), the VPN is replaced with the PFN (Physical Frame
Number) to form the physical address.
TLB misses are handled in software, with the entry to be
replaced determined by a simple RANDOM function. The routine
to process a TLB miss in the UNIX environment requires only
10-12 cycles, which compares favorably with many CPUs which
perform the operation in hardware.
Memory Management System
The IDT79R3000 has an addressing range of 4 Gbytes. However, since most IDT79R3000 systems Implement a physical
memory smaller than 4 Gbytes, the IDT79R3000 provides for the
logical expansion of memory space by translating addresses
composed in a large virtual address space into available physical
memory address. The 4 GByte address space is divided into
2 GBytes which can be accessed by both the users and the kernel,
and 2 GBytes for the kernel only.
The TLB (Translation Lookaside Buffer)
Virtual memory mapping is assisted by the Translation
Lookaside Buffer (TLB). The on-chip TLB provides very fast virtual
memory access and is well-matched to the requirements of multitasking operating systems. The fully-associative TLB contains
TLB ENTRY FORMAT
63
44
43
VPN
38 37
TLBPID
32 31
0
,'---------..
V
12
I
X
PFN
ENTRYHI
11
10
9
8
~vH
7
0
0
7
I
ENTRYLO
VPN - Virtual Page number
TLBPID - Process ID
PFN - Physical frame number
N - Non-cacheable flag
D - Dirty flag (Write protect)
V - Valid entry flag
G - Global flag (ignore PID )
0- Reseryed
Figure 5. TLB Entry Format
IDT79R3000 Operating Modes
Exception (RFE) instruction is executed. The manner in which
memory addresses are translated or mapped depends on the
operating, mode of the IDT79R3000. Figure 6 shows the MMU
translation performed for each of the operating modes.
The IDT79R3000 has two operating modes: User mode and
Kernel mode. The IDT79R3000 normally operates in the User
mode until an exception is detected forcing it into the Kernel
mode. It remains in the Kernel mode until a Restore From
S9-25
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
MMU ADDRESS TRANSLATION
VIRTUAL - > PHYSICAL
~--------------------------~
Oxffffffff
-
KERNEL
MAPPED
CACHEABLE
(kseg2)
OxcOOOOOOO
OxaOOOOO
Ox800000
Ox7fffffff
KERNEL
UNMAPPED
UNCACHED
KERNEUUSER
MAPPED
CACHEABLE
(kuseg)
o
PHYSICAL
MEMORY
KERNEL
UNMAPPED
CACHED
(ksegO)
~
rV
~
3584MB
MEMORY
512MB
Figure 6. IDT79R3000 Virtual Address Mapping
User Mode-in this mode, a single, uniform virtual address
space (kuseg) of 2 Gbyte is available. Each virtual address is
extended with a 6-bit process identifier field to form unique virtual
addresses. All references to this segment are mapped through the
TLB. Use of the cache for up to 64 processes is determined by bit
settings for each page within the TLB entries.
Kernel Mode-four separate segments are defined in this
mode:
• kuseg-when in the kernel mode, references to this segment
are treated just like user mode references, thus streamlining
kernel access to user data.
• kseg2 - references to this 1 Gbyte segment are always mapped
through the TLB and use of the cache is determined by bit
settings within the TLB entries.
IDT79R3000 Pipeline Architecture
The execution of a single ID179R3000 instruction consists of
five primary steps:
1) IF
- Fetch the instruction (I-Cache).
2) RD
- Read any required operands from CPU registers
while decoding the instruction.
3) ALU
- Perform the required operation on instruction
operands.
4) MEM - Access memory (D-Cache).
5) we - Write back results to register file.
• ksegO-references to this 512 Mbyte segment use cache
memory but are not mapped through the TLB. Instead, they
always map to the first 0.5 GBytes of physical address space.
• kseg1-references to this 512 Mbyte segment are not mapped
through the TLB and do not use the cache. Instead, they are
hard-mapped into the same 0.5 GByte segment of physical address space as ksegO.
Each of these steps requires approximately one CPU cycle as
shown in Figure 7 (parts of some operations overlap into another
cycle while other operations require only 1/2 cycle).
S9-26
- - - ..... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
Instruction Execution
IF
I RD
II-Cache I RF
ALU
MEM
WB
D-CACHE WBJ
OP
I
~
one cycle
Figure 7. Instruction Execution Sequence
The IDT79R3000 uses a 5-stage pipeline to achieve an
instruction execution rate approaching one instruction per CPU
cycle. Thus, execution of five instructions at a time are overlapped
as shown in Figure 8.
.
IDT79R3000 Instruction Pipeline
(5-deep)
.
Instruction
Flow
Current
CPU
Cycle
Figure 8. IDT79R3000.lnstruction Pipeline
This pipeline operates efficiently because different CPU
resources (address and data bus accesses, ALU operations,
register accesses, and so on) are utilized on a non-interfering
basis.
for execution. This approach to achieving this goal incorporates a
number of RISC techniques including a compact and uniform
instruction set, a deep instruction pipeline (as described above),
and utilization of optimizing compilers. Many of the advantages
obtained from these techniques can, however, be negated by
an inefficient memory system.
Figure 9 illustrates memory in a simple microprocessor system.
In this system, the CPU outputs addresses to memory and reads
instructions and data from memory or writes data to memory. The
address space is completely undifferentiated: instructions, data,
and I/O devices are all treated the same. In such a system, a
primary limiting performance factor is memory bandwidth.
Memory System Hierarchy
The high performance capabilities of the IDT79R3000
processor demand system configurations incorporating
techniques frequently employed in large, mainframe computers
but seldom encountered in systems based on more traditional
microprocessors.
A primary goal of systems employing RISC techniques is to
minimize the average number of cycles each instruction requires
MicroRrocessor
(CPU)
Memory
(and I/O)
Figure 9. A Simple Microprocessor Memory System
S9-27
IDT79R3000 RISC CPU PROCESSOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 10 illustrates a memory system that supports the significantly greater memory bandwidth required to take full advantage of the IDT79R3000's performance capabilities. The key
features of this system are:
• External Cache Memory-Local, high-speed memory (called
cache memory) is used to hold instructions and data that is
repetitively accessed by the CPU (for example, within a program
loop) and thus reduces the number of references that must be
made to the slower-speed main memory. Some microprocessors provide a limited amount of cache memory on the CPU
chip itself. The external caches supported by the IDT79R3000
can be much larger; while a small cache can improve performance of some programs, significant improvements for a wide
range of programs require large caches.
• Separate Caches. for. data and Instructions - Even with
high-speed caches, memory speed can still be a limiting factor
because of the fast cycle time of a high-performance
microprocessor. The IDT79R3000 supports separate caches for
Instructions and data and alternates accesses of the two caches
during each CPU cycle. Thus, the processor can obtain data
and instructions at the cycle rate of the CPU using caches
constructed with commercially available IDT static RAM
devices.
In order to maximize bandwidth in the cache while minimizing
the requirement for SRAM access speed, the R3000 divides a
single-processor clock cycle into two phases. During one
phase, the address forthe data cache access is presented while
data previously addressed in the instruction cache is read;
during the next phase, the data operation is completed while the
Instruction cache is being addressed. Thus, both caches are
read in a single processor cycle using only one set of address
and data pins.
• Write Buffer-In order to ensure data consistency, all data that
is written to the data cache must also be written out to main
memory. The cache write model used by the IDT79R3000 is that
of a write-through cache; that is, all data written by the CPU is
immediately written into the main memory. To relieve the CPU of
... this responsibility (and the inherent performance burden) the
IDT79R3000 supports an interface to a write buffer. The
IDT79R3020 Write Buffer captures data (and associated
addresses) output by the CPU and ensures that the data is
passed on to main memory.
IDT79R3000
Microprocessor
Data
Address
Main Memory
Figure 10•. An IDT79R3000 System with a High-Performance Memory System
IDT79R3000 Processor Subsystem Interfaces
Figure 11 illustrates the three subsystem interfaces provided by
the IDT79R3000 processor:
• Cache control interface (on-chip) for separate data and instruction caches permits implementation of off-chip caches using
standard IDT SRAM devices. The 79R3000 directly controls the
cache memory with a minimum of external components. Both
the instruction and data cache can vary from 0 to 256K Bytes (64
K entries). The 79R3000 also Includes the TAG control logic
which determines whether or not the entry read from the cache
Is the desired data.
The 79R3000 cache controller Implements a direct mapped·
cache for high net performance (bandwidth). It has the ability to
refill multiple words when a cache miss occurs, thus reducing
the effective miss rate to less than 2% for large caches. When a
cache miss occurs, the 79R3000 can support refilling the cache
S9-28
in 1,4,8, 16, or 32 word blocks to minimize the effective penalty
of having to access main memory. The 79R3000 also Incorporates the ability to perform instruction streaming; while the
cache is refilling, the processor can resume execution once the
missed word is obtained from main memory. In this way, the
processor can continue to execute concurrently with the cache
block refill.
• Memory controller interface for system (main) memory. This
interface also includes the logiC and signals to allow operation
with a write buffer to further improve memory bandwidth. In addition to the standard full word access, the memory controller
supports the ability to write bytes and half-words by using partial
word operations. The memory controller also supports the ability to retry memory accesses if, for example, the data returned
from memory is Invalid and a bus error needs to be signalled.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3000 RISC CPU PROCESSOR
The two MP signals would be generated by a external logic
which utilizes a secondary cache to perform bus snooping functions. The 79R3000 does not impose an architecture for this secondary cache, but rather is flexible enough to support a variety of
application specific architectures and still maintain cache
coherency. Further, there is no impact on designs which do not
require this feature.
• Coprocessor Interface-The I0T79R3000 features a tightly
coupled co-processor interface in which all co-processors
maintain synchronization with the main processor; reside on the
same data bus as the main processor; and participate in bus
transactions in an identical manner to the main processor. The
I0T79R3000 generates all required cache and memory control
signals, including cache and memory addresses for attached
coprocessors. As a result, only the data bus and a few control
signals need to be connected to a coprocessor.
The interface supports three types of coprocessor instructions:
loads/stores, coprocessor operations, and processorcoprocessor transfers. Note that coprocessor loads and stores
occur directly between the coprocessor and memory, without
requiring the data to go through the CPU.
Synchronization between the CPU and external coprocessors is
achieved using a Phased-Lock Loop interface to the coprocessor. The coprocessor physical interface also includes
coprocessor condition signals (CpCondn), which are used in
coprocessor branch instructions, and a coprocessor busy
signal (CpBusy) which is used to stall the CPU if the
coprocessor needs to hold off subsequent operations.
Finally, a precise exception interface is defined between the
CPU and coprocessors using the external interrupt inputs of the
CPU. This allows a coprocessor exception, even if it was the result of a multi-cycle operation, to be traced to the precise
coprocessor operation which caused it. This is an important feature for languages which can define specific error handlers for
each task.
The interface supports up to four separate coprocessors.
Coprocessor 0 is defined to be the system control coprocessor,
and resides on the same chip as the CPU unit. Coprocessor 1 is
the Floating Point Accelerator, lOT 79R3010. Coprocessors 2
and 3 are available to support an interface to application specific functions.
Advanced Features
The I0T79R3000 offers a number of additional features such as
the ability to swap the instruction and data caches, facilitating diagnostics and cache flushing. Another feature isolates the caches,
which force cache hits to occur regardless of the contents ofthe tag
fields.
Further features of the I0T79R3000 are configured during the
last four cycles prior to the negation of the RESET input. These
functions include the ability to select cache sizes and cache refill
block sizes; the ability to utilize the multiprocessor interface;
whether or not instruction streaming is enabled; whether byte ordering follows "Big-Endian" or "Little-Endian" protocols, etc.
Table 3 shows the configuration options selected at Reset. These
are further discussed in the "Hardware User's Manual".
Backward Compatibility with 79R2000
The I0T79R3000 can be used in sockets designed for the
79R2000A. The pin-out of the 79R3000 has been selected to
ensure this compatibility, with new functions mapped onto
previously unused pins. The instruction set is compatible with that
of the 79R2000 at the binary level. As a result, code written for the
older processor can be executed. New features, such as block
refill, instruction streaming, etc. can be selectively disabled.
In most 79R2000A applications, the 79R3000 can be placed in
the socket with no modification to initialization settings. The
initialization of the 79R3000 includes whether or not the device
should operate as a 79R2000A. Systems using 79R2000A would
normally have this input configured so that the device would
default to this mode. Further application assistance on this topic is
available from lOT.
Multiprocessing Support
The I0T79R3000 supports multiprocessing applications in a
simple but effective way. Multiprocessing applications require
cache coherency across the multiple processors. The I0T79R3000
offers two signals to support cache coherency: the first, MPStall,
stalls the processor within two cycles of being received and keeps
it from accessing the cache. The second signal, MPlnvalidate,
causes the processor to write data on the data cache bus which
indicates the externally addressed cache entry is invalid. Thus, a
subsequent access to that location would result in a cache miss,
and the data would be obtained from main memory.
A Special Note on Packaging
Both the flat pack and the PGA packages for the 79R3000
incorporate separate power and ground planes to eliminate noise
associated with high frequency operation. This, coupled with the
numerous power and ground pins provided on the device, helps to
ensure very reliable operation.
INPUT
WCYCLE
X CYCLE
YCYCLE
ZCYCLE
IntO*
Int1*
In12*
Int3*
Int4*
IntS*
DBlkSizeO*
IBlkSizeO*
Reserved
Reserved
PhaseDelayOn*
R3000 Mode*
DBlkSize1*
IBlkSize1*
IStream
Store Partial
PhaseDelayOn*
R3000 Mode*
Extend Cache
Reserved
Reserved
MultiProcessor
PhaseDelayOn*
R3000 Mode*
BigEndian*
TriState*
NoCache*
BusDriveOn
PhaseDelayOn*
R3000 Mode*
Table 3: IDT79R3000 Mode Selectable Features
S9-29
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
Data BUB
Data Bus
Tag Bus
r---
-
rrr-
Data Bus
-
Tag Bus
Tag Bus
AdrLo Bus
_AdrLo Bus
'-.711~7
Tag
AdrLo
TagV
TagP
t
parent
Latch
Data
DataP
DClk
IClk
~'J
Data
Tag
IAdr
[15:2)
Instruction
Cache
OE*
-
WE* ~
IDT79R3000 Processor
with System Control
Coprocessor
DAdr
[15:2)
IAd*
DAd*
~
OE*
IWr
DWr*
~
WE*
Clk2xSys
'-../'~/'-./
--
Clk2xSmp 4 . XEn*
Clk2xAd
SysOut*
Clk2xPhi
AccTy[2:0)
Aeset*
MemAd*
Memory
Interface
1
parent
Latch
CpSync*
MemWr*
Aun*
Ad Busy
Exc*
WrBusy*
CpCond[O)
BusError*
"\.7'-.7
Tag
Data
Data
Cache
,......--
'-Y
------
3
Coprocessors
CpBusy
CpCond [3: 1)
Intr* [5:0)
Hardware
Interrupts
Figure 11. IDT79R3000 Subsystem Interfaces Example; 64 KB Cache
S9-30
1_
2r-
Clocks
I
I
--_._--_ .. - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDT79R3000 RISC CPU PROCESSOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
172-PIN CERAMIC FLATPACK
(Cavity Side View)
Data21
_ Data22
Data24
Data25
Data26
Data31
DataP3
Data27
Data28
XEn*
Data29
Data30
Exc*
Clk2xPhi
Gnd7
Gnd6
Clk2xSmp
VCC7
VCC6
Gnd5
Gnd4
Gnd3
VCC5
VCC4
VCC3
Gnd2
Gnd1
Clk2xSys
IRD1*
DRd1*
IWr1*
DWr1*
VCC2
VCC1
Clk2xRd
SysOut*
DClk
IClk
IRD2*
DRd2*
IWr2*
DWr2*
MemWr*
AdrLo2
AdrLo3
AdrLo4
AdrLo5
AdrLo6
AdrLo7
AdrLo8
AdrLo9
AdrLo10
AdrLo11
AdrLo12
AdrLo13
AdrLo14
VCC15
VCC16
VCC17
Gnd16
Gnd17
VCC18
VCC19
Gnd18
VCC20
VCC21
VCC22
AdrLo15
CpCondO
CpCond1
Resvd1
Gnd19
Gnd20
AdrLo16
AdrLo17
Int*O
Int*1
Int*2
Int*3
Int*4
Int*5
CpBusy
WrBusy*
RdBusy
BusError*
Reset*
S9-31
--------------------_._------_. ..._---------__
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
13PIN CONFIGURATION
144-Pin PGA (Top View)
2
3
4
5
6
7
VCC14
AdrLo
6
AdrLo
10
AdrLo
11
VCC12
AdrLo
14
AdrLo
15
B
AdrLo
3
Drd1*
AdrLo
7
AdrLo
9
AdrLo
12
Ird1*
C
AdrLo
0
AdrLo
4
VCC13
AdrLo
5
AdrLo
8
Gnd13
D
Data
1
AdrLo
2
E
DataP
0
F
10
11
12
13
14
15
CpCond AdrLo(l) AdrLo(l)
0
16
17
Intr*
2
Intr*
5
Wr
Busy*
Reset*
VCC10
AdrLo
13
CpCond
1
Intr*
1
Intr*
3
Cp
Busy
Bus
Error*
Dwr1*
Tag12
Tag15
Gnd12
VCC11
Intr*
0
Intr*
4
Rd
Busy
Gnd11
Tag13
Tag PO
Tag18
GndO
Tag14
Tag17
Tag19
Data
0
AdrLo
1
Tag16
Tag20
VCC9
VCCO
Data
7
Data
2
Gnd10
Tag21
Tag23
G
Data
4
Data
3
Gnd1
Gnd9
Tag22
TagP1
H
Data
6
Data
Data
8
VCC8
Tag25
5
Tag24
Data
10
DataP
1
Data
9
Tag28
Tag29
Tag26
K
Data
15
Data
11
Gnd2
Gnd8
W~
Tag27
L
VCC1
Data
12
Data
17
Acc
Typ2
Tag31
Tag30
M
Data
13
Data
16
DataP
2
Gnd7
Acc
Typ1
VCC7
N
Data
14
Data
18
Data
19
Gnd3
Data
24
Data
P3
VCC3
VCC4
Gnd5
Gnd6
Run*
TagV
P
Data
23
Data
20
IWr1*
Data
22
Data
26
Data
27
XEn*
Data
30
Clk2x
Sys
Clk2x
Rd
DClk
IRd2*
IWr2*
Cp
Sync*
Acc
TypO
Q
VCC2
Data
21
Data
25
Data
31
Data
28
Gnd4
Data
29
Excep
tion*
Clk2x
Phi
Clk2x
Smp
SysOut*
VCC5
IClk
DWr2*
VCC6
A
8
9
DRd2* MemWr* MemRd*
NOTE:
1. AdrLo 16 & 17 are multi-function pins which are controlled by mode select programming on interrupt pins at reset time.
AdrLo16: MP Invalidate, CpCond (2).
AdrLo17: MP Stall, CpCond (3).
S9-32
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
PIN DESCRIPTIONS
PIN NAME
Data (0-31)
..
I/O
DESCRIPTION
I/O
A 32-bit bus used for all Instruction and data transmission among the processor, caches, memory interface, and coprocessors.
A 4-bit bus containing even parity over the data bus.
DataP (0-3)
I/O
Tag (12-31)
I/O
A 20-bit bus used for transferring cache tags and high addresses between the processor, caches, and memory interface.
TagV
I/O
The tag validity indicator.
TagP (0-2)
I/O
A 3-bit bus containing even parity over the concatenation of TagV and Tag.
An 18-bit bus containing byte addresses used for transferring low addresses from the processor to the caches and memory
interface. (AdrLo 16: CpCond (2), AdrLo 17: CpCond (3) set by reset initialization).
AdrLo (0-17)
0
IRd1*
0
Read enable for the instruction cache.
IWr1*
0
Write enable for the instruction cache.
IRd2*
0
An identical copy of IRd1 * used to split the load.
IWr2*
0
An identical copy of IWr1 * used to split the load.
IClk
0
The instruction cache address latch clock. This clock runs continuously.
DRd1*
0
The read enable for the data cache.
DWr1*
0
The write enable for the data cache.
DRd2*
0
An identical copy of DRd1* used to split the load.
DWr2*
0
An identical copy of DWr1 * used to split the load.
DClk
0
The data cache address latch clock. This clock runs continuously.
XEn*
0
The read enable for the Read Buffer.
AccTyp (0-2)
0
A 3-bit bus used to indicate the size of data peing transferred on the data bus, whether or nota data transfer is oCcurring, and the
,\
.
.
.purpose of the transfer.
MemWr*
0
Signals the occurrence of a main memory write
MemRd*
0
Signals the occurrence of a main memory read.
Signals the occurrence of a bus error during a main memory read or write.
BusError*
I
Run*
0
Indicates whether the processor is in the run or stall state,
Exception*
0
Indicates that the instruction about to commit state should be aborted and other exception related information.
SysOut*
0
A reflection of the internal processor clock used to generate the system clock.
CpSync*
0
A clock which is identical to SysOut* and used by coprocessors for timing synchronization with the CPU.
RdBusy*
I
The main memory read stall termination signal. In most system designs RdBusy is normally asserted and is deasserted only to
indicate the successful completion of a memory read. RdBusy is sampled by the processor only during memory read stalls.
WrBusy*
I
The main memory write stall initiation/termination signal.
CpBusy
I
The coprocessor busy stall initiation/termination signal.
CpCond (0-1)
I
A 2-bit bus used to transfer conditional branch status from the coprocessors to the main processor.
CpCond (2:"3)
I
Conditional branch status from coprocessors to the processor. Function is provided on AdrL016/17 pins and is selected at
reset time.
MPStall
I
Multiprocessing Stall. Signals to the processor that it should stall accesses to the caches in a multiprocessing
environment. This is physically the same pin as CpCond2; its.use is determined at RESET initialization;
MPlnvalidate
I
Multiprocessing Invalidate. Signals to the processor that it should issue invalidate dataon the cache data bus.
The address to be invalidated is externally provided. This is the same pin as CpCond3; its use is determined at
RESET initialization.
Int* (0-5)
I
A 6-bit bus used by the merT'lOry interface and coprocessors to Signal maskable interruptS to the processor. At resettim~, mode
select values are read in.
Clk2xSys
I
The master double frequency input clock used for generating SysOut*..
Clk2xSmp
I
A double frequency clOCk input used to determine the sample point for data coming into the processor and coprocessors.
Clk2xRd
I
A double frequency clock input used to determine the enable time of the cache RAMs.
Clk2xPhi
I
A double frequency clock input used to determine the position of the internal phases, phase1 and phase2.
Reset*
I
Synchronous initialization input used to force execution starting from the reset memory address. Reset* must be deasserted
synchronously but asserted asynchronously. The deassertion of reset* must be synchronized by the leading edge of SysOut.
S9-33
.
-------------
- - - - - - - - - - - - - - _.._._-----_._---_._ ..-
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3000 RISC CPU PROCESSOR
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1,3)
COMMERCIAL
MILITARY
UNIT
-0.5 to + 7.0
-0.5 to +7.0
V
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
\'IN
Input Voltage (2)
-0.5 to +7.0
-0.5 to +7.0
V
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
OOC to + 70°C
OV
5.0V ± 5%
Vee
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not 'implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VIN minimum = 3.0V for pulse width less than 15ns.
VIN should not exceed Vcc + 0.5 Volts.
3. Not more than one output sould be shorted at a time. Duration of the
short should not exceed 30 seconds.
DC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE
SYMBOL
PARAMETER
TA
= O°Cto
+70°C Vee
TEST CONDITIONS
=
+50V +5%
16.67 MHz
MIN.
MAX.
20.0 MHz
MIN.
MAX.
25.0 MHz
MIN.
MAX.
UNIT
VOH
Output HIGH Voltage
Vec = Min, IOH = -4mA
3.5
-
3.5
-
3.5
-
VOL
Output LOW Voltage
Vec = Min, 10L = 4mA
-
0.5
-
0.5
-
0.5
V
VOHT
Output HIGH Voltage (4)
Vee = Min, 10H = -SmA
2.4
-
2.4
-
2.4
-
V
VOLT
Output LOW Voltage (4)
Vee = Min, 10L = SmA
V IH
Input HIGH Voltage(5)
V
-
O.S
-
O.S
-
O.S
V
2.0
-
2.0
-
2.0
-
V
V IL
Input LOW Voltage (1)
-
O.S
-
O.S
-
O.S
V
V IHS
Input HIGH Voltage (2, 5)
3.0
-
3.0
-
3.0
-
V
V ILS
Input LOW Voltage(l, 2)
V
10
pF
Output Capacitance
Icc
Operating Current
Vee = Max
575
C LD
Load Capacitance
-
50
-
0.4
C OUT
IIH
Input HIGH Leakage(3)
\'IH = Vee
-
10
-
0.4
Input Capacitance
-
0.4
C IN
10
-
10
10
50
10
10
640
Input LOW Leakage(3)
-10
VIL = Gnd
-10
-40
40
-40
40
Output Tri-state Leakage
VOH = 2.4V, VOL = 0.5V
loz
NOTES:
1. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 Volts for larger periods.
2. VIHS and VILS apply to Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi, CpBusy, and Reset*.
3. These parameters do not apply to the clock inputs.
4. VOHT and VOLT apply to the bidirectional data and tag busses only. Note that V IH and VIL also apply to these signals.
5. \'IH should not be held above Vee + 0.5 volts.
IlL
59-34
10
pF
700
mA
50
pF
10
~A
-10
-
~A
-40
40
~A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3000 RISC CPU PROCESSOR
DC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE TA = -55°C to
SYMBOL
PARAMETER
+125°C, Vee = +5.0V ±10%
TEST CONDITIONS
= Min, 10H = -4mA
= Min, IOL = 4mA
= Min, 10H = -SmA
= Min, 10L = SmA
16.67 MHz
MIN.
MAX.
UNIT
3.5
-
-
0.5
V
2.4
-
V
-
O.S
V
2.0
-
V
O.S
V
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VOHT
Output HIGH Voltage (4)
Vee
VOLT
Output LOW Voltage (4)
Vee
V IH
Input HIGH Voltage(5)
V IL
Input LOW Voltage(1)
-
V IHS
Input HIGH Voltage (2. 5)
3.0
-
V
V ILS
Input LOW Voltage(l. 2)
-
0.4
V
10
pF
CIN
Input Capacitance
COUT
Output Capacitance
Icc
Operating Current
C LD
Load Capacitance
IIH
Input HIGH Leakage(3)
IlL
Input LOW Leakage(3)
Vee
= Max
= Vee
VIL = Gnd
VOH = 2.4V, VOL = 0.5V
V1H
-10
Output Tri-state Leakage
-40
loz
NOTES:
1. VIL Min. = -3.0V for pulse width less than 15ns. "iL should not fall below -0.5 Volts for larger periods.
2. VIHS and VILS apply to Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi, CpBusy, and Reset'".
3. These parameters do not apply to the clock inputs.
4. VOHT and \bLT apply to the bidirectional data and tag busses only. Note that V IH and VIL also apply to these signals.
5. VIH should not be held above Vee + 0.5 volts.
S9-35
V
10
pF
675
mA
50
pF
10
IJA
-
IJA
40
IJA
"
1DT79R3000 RISC CPU. PROCESSOR
MILITARY AND CO'MMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE
TA
= O°Cto
+70°C vcc
TEST CONDITION
PARAMETER
SYMBOL
=
+50V +5%
16.67 MHz
MAX.
MIN.
20.0 MHz
MAX.
MIN.
25.0 MHz
MIN.
MAX.
UNIT
Clock
TCkHlgh
Input Clock High
Transition < 5ns
12.5
-
10
-
ns
TCkLow
Transition < 5 ns
12.5
-
10
-
8
Input Clock Low
8
-
ns
TCkP
Input Clock Period
Clk2xSys to Clk2xSmp
Clk2xSmp to Clk2xRd
Clk2xSmp to Clk2xPhi
30
0
0
500
tcyc/4
tcyc/4
tcyc/4
25
0
0
7
500
tcyc/4
tcyc/4
tcyc/4
20
0
0
5
500
tcyc/4
tcyc/4
tcyc/4
ns
ns
ns
ns
ns
9
Run Operation
TOEn
Data Enable(3)
-
-2
-
-2
-
-1.5
TOOls
Data Disable(3)
-
-1
-
-1
-
-0.5
ns
Toval
Data Valid
Load = 25pF
-
3
-
3
2
ns
TwrDly
Write Delay
Load = 25pF
-
5
-
4
-
3
ns
Tos
Data Set-up
9
-
8
6
-
ns
TRSDS
Reset Pin Set-up.
15
-
15
10
-
ns
TOH
Data Hold
-2.5
-
-2.5
-2.5
TCBS
13
-
11
9
-
ns
CpBusy Set-up
TCBH
CpBusy Hold
-2.5
-
-2.5
-
-2.5
-
ns
TAcTy
Access Type (1 :0)
Load = 25pF
-
7
6
-
5
ns
TAT2
Access Type (2)
Load = 25pF
-
17
14
-
12
ns
TMWr
Memory Write
Load = 25pF
-
27
-
23
-
18
ns
TExe
Exception
Load = 25pF
-
7
-
7
-
5
ns
20
ns
18
ns
18
ns
ns
Stall Operation
TSAVal
Address Valid
Load = 25pF
-
30
-
23
TSACTy
Access Type
Load = 25pF
27
Memory Read Initiate
Load = 25pF
27
-
23
TMAdl
-
23
-
TMRdt
Memory Read Terminate
Load = 25pF
-
7
-
7
-
5
ns
TSd
Run Terminate
Load = 25pF
-
17
-
15
-
11
ns
TRun
Run Initiate
Load = 25pF
-
7
6
-
4
ns
TSMWr
Memory Write
Load = 25pF
-
27
-
23
18
ns
TSEx
Exception Valid
Load = 25pF
-
20
-
18
-
15
ns
6
-
6
-
6
TckP
3000
-
3000
-
3000
128
-
128
-
128
-
TckP
0.5
2
0.5
1
0.5
1
ns/25pF
Reset Initialization
TRST
Reset Pulse Width
TrstPLL
Reset timing, Phase-lock on (5)
Trstcp
Reset timing, Phase-lock
Off(5)
TckP
Capacitive Load Deration
CLD
Load Derate
NOTES:
1. All timings are referenced to 1.5V.
2. The clock parameters apply to all four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, and Clk2xPhi.
3. This parameter is guaranteed by design.
4. These parameters reference timing diagrams shown in the "Hardware User's Manual.·
5. These parameters apply when the 79R3010 Floating Point Coprocessor is connected to the CPU.
S9-36
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3000 RISC CPU PROCESSOR
AC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE TA = -55°C to
SYMBOL
PARAMETER
+ 125°C, Vcc
= +5.0V -+10%
TEST CONDITION
16.67 MHz
MIN.
MAX.
UNIT
-
ns
500
tcyc/4
tcyc/4
tcyc/4
ns
ns
ns
ns
-2
ns
-1
ns
Clock
TCkHlgh
Input Clock High
Transition < 5ns
12.5
TCklow
Input Clock Low
Transition < 5 ns
12.5
TCkP
Input Clock Period
Clk2xSys to Clk2xSmp
Clk2xSmp to Clk2xRd
Clk2xSmp to Clk2xPhi
30
0
TOEn
Data Enable(3)
TOOls
Data Disable(3)
TOVal
Data Valid
Load
TWroly
Write Delay
Load
-
Tos
DataSet-up
TRSOS
Reset Pin Set-up
TOH
Data Hold
0
9
ns
Run Operation
= 25pF
= 25pF
3
ns
5
ns
9
-
ns
15
ns
13
-
-2.5
-
ns
-
7
ns
-
17
ns
27
ns
7
ns
30
ns
-2.5
TCBS
CpBusy Set-up
TCBH
CpBusy Hold
TAcTy
Access Type (1 :0)
TAT2
Access Type (2)
Load
TMWr
Memory Write
Load
TExe
Exception
Load
TSAVal
Address Valid
Load
TSAcTy
Access Type
Load
TMRdl
Memory Read Initiate
Load
Load
= 25pF
= 25pF
= 25pF
= 25pF
ns
ns
Stall Operation
TMRdt
Memory Read Terminate
Load
TSd
Run Terminate
Load
TRun
Run Initiate
Load
TSMWr
Memory Write
Load
TSEx
Exception Valid
Load
= 25pF
= 25pF
= 25pF
= 25pF
= 25pF
= 25pF
= 25pF
= 25pF
-
-
27
ns
27
ns
7
ns
17
ns
7
ns
-
27
ns
20
ns
Reset Initialization
TRST
Reset Pulse Width
6
-
TckP
TrstPll
Reset timing, Phase-lock on (5)
3000
-
TckP
Trstcp
Reset timing, Phase-lock off (5)
128
-
TckP
0.5
2
ns/25pF
Capacitive Load Deration
CLD
Load Derate
NOTES:
1. All timings are referenced to 1.5V.
2. The clock parameters apply to all four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, and Clk2xPhi.
3. This parameter is guaranteed by design.
4. These parameters reference timing diagrams shown in the "Hardware User's Manual:
5. These parameters apply when the 79R3010 Floating Point Coprocessor is connected to the CPU.
S9-37
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3000 RISC CPU PROCESSOR
ORDERING INFORMATION
IDT79R3000 -
~
Speed
__X__
Package
X
Process/
Temp. Range
S9-38
Blank
'B'
Commercial
Military
'G'
'F'
144-Pin PGA
172-pin Flat Pack
'16'
'20'
'25'
16.67 MHz
20.0 MHz
25.0 MHz
t;)
IntegratedDevIce~Inc.
RISC FLOATING-POINT
ACCELERATOR (FPA)
PRELIMINARY
lOT 79R3010
• Pin, function and software compatible with the IDT79R2010A
RISC FPA.
FEATURES:
• Hardware Support of Single- and Double-Precision Operations:
• Military product compliant to MIL-STD-883, Class B.
- Floating-Point Add
• 32-bit status/control register providing access to a" IEEEStandard exception handling.
- Floating-Point Subtract
- Floating-Point Multiply
- Floating-Point Divide
• Load/store architecture allows data movement directly between
FPA and memory or between CPU and FPA.
- Floating-Point Comparisons
• Overlapped operation of independent floating point ALUs.
- Floating-Point Conversions
DESCRIPTION:
• Sustained performance:
- 7 MFLOPS single precision UNPACK
The IDT79R3010 Floating-Point Accelerator (FPA) operates in
conjunction with the IDT79R3000 Processor and extends the
IDT79R3000's instruction set to perform arithmetic operations on
values in floating-point representations. The IDT79R3010 FPA,
with associated system software, fully conforms to the requirements of ANSI/IEEE Standard 754-1985, "IEEE Standard for Binary Floating-Point Arithmetic." In addition, the architecture fully
supports the standard's recommendations.
This data sheet provides an overview of the features and architecture of the 79R3010 FPA, Revision 2.0. A more detailed description of the operation of the device is incorporated in the "R3000
Family Hardware User's Manual", and a more detailed architectural overview is provided in the "mips RISC Architecture" book,
both available from lOT.
- 4 MFLOPS double precision UNPACK
• Cycle Time:
- 40ns (25MHz)
- 60ns (16.67MHz)
- 80ns (12.5MHz)
• Direct, high-speed interface with IDT79R3000 Processor.
• Supports Fu" Conformance With IEEE 754-1985 Floating-Point
Specification.
• Fu" 64-bit operation using sixteen 64-bit data registers.
• High-speed CEMOS ™ technology.
cache
data
Data Bus
(32)
operands
Register unit (16 X 64)
Reset'"
fraction
Run'"
(53)
FpBusy
FpInt'"
result
Control
unit
&
Clocks
round
(53)
(56)
(53)
(56)
Divide unit
FpCond
clocks
Multiply unit
PLLOn'"
A
B
result
Figure 1. IDT79R3010 Functional Block Diagram
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 MIPS Computer Systems. Inc. All Rights Reserved.
OSC-0022/1
S9-39
- - - - - - - - - - - - - - - - _ . _ - _ .. _._-
JANUARY 1989
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
resources of the FPA to appear to the systems programmers as an
extension of the CPU internal registers. The FPA registers are
shown in Figure 2.
IDT79R3010 FPA REGISTERS
The IDT79R3010 FPA provides 32 general purpose 32-bit registers, a Control/Status register, and a Revision Identification register. The tightly-coupled coprocessor interface causes the register
Generai Purpose Registers
(FGR/FPR)
63
32
o
31
FGR1
FGR3
FGRO
FGR2
FGR5
FGR4
Control/Status Register
31
••
•
FGR27
FGR26
FGR29
FGR28
FGR30
FGR31
0
IExceptions/Enables/Modes I
Implementation/Revision
Register
0
31
I
I
Figure 2. 1DT79R3010 FPA Registers
Floating-point coprocessor operations reference three types of
registers:
• Floating-Point Control Registers (FCR)
The FPA performs three types of operations:
• Loads and Stores;
• Moves;
• Two- and three-register floating-point operations.
• Floating-Point General Registers (FGR)
• Floating-Point Registers (FPR).
Load, Store, and Move Operations
Floating-Point General Registers (FGR)
Load, Store, and Move operations move data between memory
or the IDT79R3000 Processor registers and the IDT79R3010 FPA
registers. These operations perform no format conversions and
cause no floating-point exceptions. Load, Store, and Move operations reference a single 32-bit word of either the Floating-Point
General Registers (FGR) or the Floating-Point Control Registers
(FCR).
There are 32 Floating-Point General Registers (FGR) on the
FPA. They represent directly-addressable 32-bit registers, and can
be accessed by Load, Store, or Move Operations.
Floating-Point Registers (FPR)
The 32 FGRs described in the preceding paragraph are also
used to form sixteen 64-bit Floating-Point Registers (FPR). Pairs of
general registers (FGRs), for example FGRO and FGR1 (refer to
Figure 2) are physically combined to form a single 64-bit FPR. The
FPRs hold a value in either single- or double-precision floatingpoint format. Double-precision format FPRs are formed from two
adjacent FGRs.
Floating-Point Operations
The FPA supports the following single- and double-precision
format floating-point operations:
• Add
• Subtract
• Multiply
Floating-Point Control Registers (FCR)
• Divide
• Absolute Value
There are 2 Floating-Point Control Registers (FCR) on the FPA.
They can be accessed only by Move operations and include the
following:
• Control/Status register, used to control and monitor exceptions,
operating modes, and rounding modes;
• Move
• Negate
• Compare
In addition, the FPA supports conversions between single- and
double-precision floating-point formats and fixed-point formats.
The FPA incorporates separate Add/Subtract, Multiply, and Divide units, each capable of independent and concurrent operation.
Thus, to achieve very high performance, floating point divides can
be overlapped with floating point multiplies and floating point additions. These floating pOint operations occur independently of the
actions of the CPU, allowing further overlap of Integer and floating
point operations. Figure 3 illustrates an example of the types of
overlap permissible.
• Revision register, containing revision information about the
FPA.
COPROCESSOR OPERATION
The FPA continually monitors the IDT79R3000 processor instruction stream. If an instruction does not apply to the coprocessor, it Is Ignored; if an instruction does apply to the coprocessor,
the FPA executes that instruction and transfers necessary result
and exception data synchronously to the IDT79R3000 main processor.
59-40
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
2
DIV.S
Mt@~]
M%:gmmm
:::::::::::::::::::::::::::::::::::1
"""-'.........;:;....;:."-1
Only Load. Store. and Move operations
are permitted in FPA during these cycles.
~~~~~£~:tiE~~:~E:~~!f~~;;:~5
These cycles are free for integer operations in
the CPU.
Figure 3: Example of Overlapping Floating Point Operation
Exceptions
INSTRUCTION SET OVERVIEW
The IDT79R3010 FPA supports all five IEEE standard exceptions:
• Invalid Operation
• Inexact Operation
• Division by Zero
• Overflow
• Underflow
The FPA also supports the optional, Unimplemented Operation
exception that allows unimplemented instructions to trap to software emulation routines.
The FPA provides preCise exception capability to the CPU; that
is, the execution of a floating point operation which generates an
exception causes that exception to occur at the CPU instruction
which caused the operation. This precise exception capability is a
requirement in applications and languages which provide a
mechanism for local software exception handlers within software
modules.
AIIIDT79R3010 instructions are 32 bits long and they can be divided into the following groups:
• Load/Store and Move instructions move data between memory, the main processor and the FPA general registers.
• Computational instructions perform arithmetic operations on
floating point values in the FPA registers.
• Conversion instructions perform conversion operations between the various data formats.
• Compare instructions perform comparisons of the contents of
registers and set a condition bit based on the results. The result
of the compare operation is output on the FpCond output of the
FPA, which is typically used as CpCond1 on the CPU for use in
coprocessor branch operations.
Table 1 lists the instruction set of the IDT79R3010 FPA.
OP
Description
OP
Load/Store/Move Instructions
LWCI
SWCI
MTCI
MFCI
CTCI
CFCI
ADD.fmt
SUS.fmt
MUL.fmt
DIV.fmt
ASS.fmt
MOV.fmt
NEG.fmt
Load Word to FPA
Store Word from FPA
Move Word to FPA
Move Word from FPA
Move Control word to FPA
Move Control word from FPA
Conversion Instructions
CVT.S.fmt Floating-point Convert to Single FP
CVT.D.fmt Floating-point Convert to Double FP
CVT.W.fmt Floating-point Convert to fixed-point
Description
Computational Instructions
Floating-paint
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Floating-point
Add
Subtract
Multiply
Divide
Absolute value
Move
Negate
Compare Instructions
C.cond.fmt
Floating-point Compare
Table 1. IDT79R3010 Instruction Summary
S9-41 .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 Rise FLOATING POINT ACCELERATOR (FPA)
3) ALU -If the instruction is an FPA instruction, instruction execution commences during this pipe stage.
IDT79R3010 PIPELINE ARCHITECTURE
The IDT79R3010 FPA provides an instruction pipeline that parallels that of the IDT79R3000 processor. The FPA, however, has a
6-stage pipeline instead ofthe S-stage pipeline of the IDT79R3000:
the additional FPA pipe stage is used to provide efficient coordination of exception responses between the FPA and main processor.
The execution of a single IDT79R301 0 instruction consists of six
primary steps:
1) IF-Instruction Fetch. The main processor calculates the instruction address required to read an instruction from the 1Cache. No action is required of the FPA during this pipe
stage since the main processor is responsible for address
generation.
2) RD - The Instruction Is present on the data bus during phase
1 of this pipe stage and the FPA decodes the data on the bus
to determine if it is an instruction for the FPA.
4) MEM -If this is a coprocessor load or store instruction, the
FPA presents or captures the data during phase 2 of this pipe
stage.
S} WB - The FPA uses this pipe stage solely to deal with exceptions.
6} FWB - The FPA uses this stage to write back ALU results to
its register file. This stage Is the equivalent of the WB stage in
the IDT79R3000 main processor.
Each of these steps requires approximately one FPA cycle as
shown in Figure 3 (parts of some operations spill over into another
cycle while other operations require only 1/2 cycle).
Instruction Execution
IF
I
ll-Cache
I
ALU
RD
J RF
MEM
OP
D-Cache
WB
FWB
exceptions FpWB
"---v-----i
one cycle
Figure 4. Instruction Execution Sequence
The IDT79R30 10 uses a 6-stage pipeline to achieve an instruction execution rate approaching one instruction per FPA cycle.
Thus, execution of six instructions at a time are overlapped as
shown in Figure 5.
Instruction
Flow
Current
Cycle
Figure 5. 1DT79R3010 Instruction Pipeline
This pipeline operates efficiently because different FPA resources (address and data bus accesses, ALU operations, register
accesses, and so on) are utilized on a non-interfering basis.
S9-42
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
f1:op View)
11 10 9 8 7
Clk2xRd
FpSysin·
Data(31)
VCC1
Gnd1
DataP(3)
FpSysOut·
Clk2xSys
Clk2xSmp
Clk2xPhi
Reset·
FpSync·
VCC2
Gnd2
VCC3
Gnd3
PilOn·
VCC4
Gnd4
VCC5
Gnd5
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
6 543
.,
2 1 84 83 82 81 807978 77 7675
74
73
Index
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
333435363738394041424344454647484950515253
84-Pin J Bend CERQUAD
S9-43
Gnd13
DataP(1)
VCC12
Gnd 12
FpCond
FpBusy
Fplnt·
Exception·
Run·
Resvd2
Resvd1
VCC11
Gnd11
VCC10
Gndl0
FpPresent·
ResvdO
VCC9
Gnd9
VCC8
Gnd8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
PIN CONFIGURATION
84-PIN CPGA FOR 79R301 0
PIN GRID ARRAY (Cermamlc, Cavity Down}-BOTTOM VIEW
M
Vss
Vee
Data
17
DataP
1
Vss
FP
Cond
FPlnt·
Vss
Run·
Rsrvd
1
Vee
Vss
L
Data
21
Data
20
Data
18
Data
16
Vee
FPBusy
Exeeption
Vee
Rsrvd
2
FP
Present
.
Data
15
Data
14
K
Vss
Vee
Data
19
Rsrvd
0,
Vee
Vss
Data
23
Data
22
Data
13
Data
12
H
Data
24
DataP
2
Data
11
Data
10
G
Data
26
Data
25
Vee
Vss
F
Vss
Vee
Data
8
Data
9
E
Data
27
Data
28
Data
7
DataP
0
D
Data
29
Data
30
Data
5
Data
6
C
Vss
Vee
Clk2x
Rd
Data
2
Vee
Vss
B
Fp
Sysln·
Data
31
DataP
3
Vee
Clk2x
Sys
Vee
Clk2x
Phi
Vee
PilOn·
Data
1
Data
3
Data
4
A
Vss
Vee
FpSys
Out·
Vss
Clk2x
Smp
Vss
Reset·
Vss
FP
Syne·
Data
0
Vee
Vss
2
3
4
5
6
7
8
9
10
11
12
S9-44
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1/0
Data (0-31)
1/0
DataP (0-3)
0
A multiplexed 32-bit bus used for instruction and data transfers on phase 1 and phase 2. respectively.
A 4-bit bus containing even parity over the data bus. Parity is generated by the FPA on stores.
Input to the FPA which indicates whether the processor-coprocessor system is in the run or stall state.
Run*
I
Exception*
I
Input to the FPA which indicates exception related status information.
FpBusy
0
Signal to the CPU indicating a request for a coprocessor busy stall.
FpCond
0
Signal to the CPU indicating the result of the last comparison operation.
Fplnt*
0
Signal to the CPU Indicating that a floating-point exception has occurred for the current FPA instruction.
Reset*
I
Synchronous initialization input used to distinguish the processor-FPA synchronization period from the execution period.
Reset* must be synchronized by the leading edge of SysOut from the CPU.
PIIOn*
I
Input which during the reset period determines whether the phase lock mechanism is enabled and during the execution period
determines the output timing model.
FpPresent*
0
Output which is pulled to ground through an impedance of approximately O.Sk ohms. By providing an external pullup on this
line an indication of the presence or absence of the FPA can be obtained.
Clk2xSys
I
A double frequency clock input used for generating FpSysOut*.
Clk2xSmp
I
A double frequency clock input used to determine the sample point for data coming into the FPA.
A dOUble frequency clock input used to determine the disable point for the data drivers.
CIk2xRd
I
Clk2xPhl
I
A dOUble frequency clock input used to determine the position of the internal phases. phase 1 and phase 2.
FpSysOut*
0
Synchronization clock from the FPA.
FpSysln*
I
Input used to receive the synchronization clock from the FPA.
FpSync*
I
Input used to receive the synchronization clock from the CPU.
S9-45
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R30.10 RISC FLOATING POINT ACCELERATOR (FPA)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
with Respect to
GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1,3)
COMMERCIAL
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TalAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TsrG
Storage
Temperature
-55 to +125
-65 to +150
°C
Y,N
Input Voltage (2)
-0.5 to +7.0
-0.5 to +7.0
V
Commercial
AMBIENT
TEMPERATURE
-55°C to +125°C
GND
OV
5.0V
O°Cto +70°C
OV
5.0V ± 5%
Vee
± 10%
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratIng only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. \'IN minimum = 3.0V for pulse width less than 15ns.
Y,N maximum should not exceed Vcc + 0.5 Volts.
3. Not more than one output should be shorted at a time. Duration of the
short should not exceed 30 seconds;
DC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE
SYMBOL
(rA = O°Cto +70°C, Vcc = 5.0V ±5%)
TEST CONDITIONS
PARAMETER
16.67 MHz
MIN.
MAX.
20.0 MHz
MIN.
MAX.
25.0 MHz
MIN.
MAX.
UNIT
3.5
-
3.5
-
3.5
-
-
0.5
0.5
V
0.5
-
0.5
0.5
-
0.5
V
2.0
-
2.0
-
2.0
-
V
-
0.8
-
0.8
-
0.8
V
3.0
-
3.0
-
3.0
-
V
-
0.4
-
0.4
-
0.4
V
Input HIGH Voltage (4. B)
4.0
-
4.0
-
4.0
-
V
V,LC
Input LOW Voltage (1. 4)
-
0.4
V
-
10
10
-
0.4
Input Capacitance
-
0.4
C,N
10
pF
COLrr
Output Capacitance
Icc
Operating Current
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vcc
VOLFP
Output LOW Voltage (5)
Vcc
V,H
Input HIGH Voltage(B)
V,L
Input LOW Voltage (1)
V,HS
Input HIGH Voltage (2. B)
V,LS
Input LOW Voltage (1. 2)
V ,HC
= Min, 10H = -4mA
= Min, 10L = 4mA
= Min, 10L = 1.5mA
Vcc
= Max
= Vcc
C LD
Load Capacitance
I'H
Input HIGH Leakage(3)
\'IH
I,L
Input LOW Leakage(3)
V,L = Gnd
loz
Output Tri-state Leakage
VOH = 2.4V, VOL
= 0.5V
-
10
-
10
pF
675
-
750
mA
50
-
50
-
50
pF
10
-10
10
-10
10
jJA
-10
10
-10
10
-10
10
jJA
-40
40
-40
40
-40
40
jJA
-
10
-
625
-10
NOTES:
1. V,L · Min. = .-3.0V for pulse width less than 15ns. V,L should not fall below -0.5 Volts for longer periods.
2. V,HS and V,LS apply to Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi, CpBusy, and Reset*.
3. These parameters do not apply to the clock inputs.
4. V,HC and V,LC apply to Run* and Exception*.
5. VOLFP applies to the FPPresent* pin only.
6. V ,H and V,HS should not be held above Vee + 0.5 Volts.
S9-46
V
- - - - . - - - - - - - - - - - - - - •..._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
DC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE (TA = -55°C to
SYMBOL
+125°C, Vee
= 5.0V ±10%)
TEST CONDITIONS
PARAMETER
VOH
Output HIGH Voltage
Vcc
VOL
Output LOW Voltage
Vcc
VOLFP
Output LOW Voltage (5)
Vcc
VIH
Input HIGH Voltage(6)
= Min, 10H = -4mA
= Min,loL = 4mA
= Min, 10L = 1.5mA
16.67 MHz
UNIT
MIN.
MAX.
3.5
-
V
-
0.5
V
0.5
V
2.0
-
V
V
VIL
Input LOW Voltage (1)
-
0.8
VIHS
Input HIGH Voltage(2. 6)
3.0
-
V
VILS
Input LOW Voltage(" 2)
-
0.4
V
VIHC
Input HIGH Voltage (4, 6)
4.0
-
V
VILC
Input LOW Voltage(" 4)
0.4
V
10
pF
CIN
Input Capacitance
-
C OUT
Output Capacitance
-
10
pF
lee
Operating Current
-
720
mA
C LD
Load Capacitance
-
50
pF
IIH
Input HIGH Leakage(3)
-10
10
jJA
-10
10
jJA
-40
40
jJA
IlL
Input LOW Leakage(3)
loz
Output Tn-state Leakage
Vcc
= Max
= Vcc
VIL = Gnd
VOH = 2.4V, VOL = 0.5V
"'IH
NOTES:
1. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 Volts for longer periods.
2. VIHS and "'ILS apply to Clk2xSys, Clk2xSmp, Clk2xRd, Clk2xPhi, Cp8usy, and Reset*.
3. These parameters do not apply to the clock inputs.
4. V IHC and Vile apply to Run* and Exception*.
5. VOLFP applies to the FPPresent* pin only.
6. V IH and VIHS should not be held above Vee + 0.5 Volts.
S9-47
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
AC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE
SYMBOL
PARAMETER
(fA = O°Cto +70°C, Vcc = 5.0V ±50/0)
TEST CONDITION
16.67 MHz
MAX.
MIN.
20.0 MHz
MAX.
MIN.
. 25.0 MHz
MIN.
MAX.
UNIT
Clock
-
8
8
-
7
500
tcyc/4
tcyc/4
tcyc/4
20
0
0
5
500
tcyc/4
tcyc/4
tcyc/4
TCkHlgh
Input Clock High
Transition < 5ns
12
-
10
TCkLOW
Input Clock low
Transition < 5ns
12
-
10
TCkP
Input Clock Period
Clk2xSys to Clk2xSmp
Clk2xSmp to Clk2xRd
Clk2xSmp to Clk2xPhi
30
0
0
25
0
0
9
500
tcyc/4
tcyc/4
tcyc/4
ns
ns
,?
ns
ns
ns
ns
Timing Parameters
TO En
Data Enable(3)
-
-2
-
-2
-
-1.5
ns
TOOls
Data Disable(3)
0
-
0
-
0
-
ns
Toval
Data Valid
-
3
-
3
-
2
ns
Tos
Data Set-up
9
8
-
6
Reset Set-up
15
15
10
ToH
Data Hold
-2.5
-
-2.5
-
-2.5
-
ns
TRsDS
-
TFpCond
Fp Condition
35
-
25
ns
Fp Busy
13
ns
Fp Interrupt
35
-
10
TFplnt
25
ns
T~MOV
Fp Move To
-
35
-
30
TFPBUSY
-
30
-
25
ns
TExS
Exception Set-up
10
-
9
7
-
ns
TExH
Exception Hold
0
0
0
-
ns
TRuns
Run Set-up
10
-2
-2
-2
-
ns
Run Hold
-
7
TRunH
-
-
load = 25pF
15
40
9
ns
ns
ns
Reset Initialization
TrstPLL
Reset timing. Phase-lock on
3000
-
3000
-
3000
Reset timing, Phase-lock off
128
-
128
-
128
-
TckP
Trst
0.5
2
0.5
1
0.5
1
ns/25pF
TckP
Capacitive Load Deration
ClD
load Derate
NOTES:
1. All timings are referenced to 1.5V.
2. The clock parameters apply to all four 2xClocks: Clk2xSys, Clk2xSmp, Cik2xRd, and Clk2xPhi.
3. This parameter is guaranteed by design.
4. These parameters reference timing diagrams shown in the "Hardware User's Manual:
S9-48
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT79R3010 Rise FLOATING POINT ACCELERATOR (FPA)
AC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE erA = -55°C to
PARAMETER
SYMBOL
+125°C Vcc = 50V -+10%)
16.67 MHz
TEST CONDITION
MIN.
MAX.
UNIT
-
ns
30
0
0
9
500
tcyc/4
tcyc/4
~cyc/4
ns
ns
ns
ns
Clock
TCkHlgh
Input Clock High
Transition < 5ns
12
TCkLow
Input Clock Low
Transition < 5ns
12
TCkP
Input Clock Period
CIk2xSys to Clk2xSmp
Clk2xSmp to Clk2xRd
Clk2xSmp to Clk2xPhi
ns
Timing Parameters
TOEn
Data Enable(3)
-
-2
ns
Tools
Data Disable(3)
0
-
ns
Toval
Data Valid
-
3
ns
Tos
DataSet-up
9
-
ns
TRsOS
Reset Set-up
15
ns
TOH
Data Hold
-2.5
-
TFpCond
Fp Condition
-
35
ns
TFpBUS}'
Fp Busy
15
ns
TFPlnl
Fp Interrupt
-
40
ns
TFPMOV
Fp Move To
-
35
ns
TExS
Exception Set-up
10
ns
TExH
Exception Hold
0
TRuns
Run Set-up
10
TRunH
Run Hold
-2
-
Load = 25pF
ns
ns
ns
ns
Reset Initialization
TrstPLL
"Reset timing, Phase-lock on"
3000
-
TckP
Trst
"Reset timing, Phase-lock off"
128
-
TckP
0.5
2
ns/25pF
Capacitive Load Deration
CLD
Load Derate
NOTES:
1. All timings are referenced to 1.5V.
2. The clock parameters apply to all four 2xClocks: Clk2xSys, Clk2xSmp, Clk2xRd, and Clk2xPhi.
3. This parameter is guaranteed by design.
4. These parameters reference timing diagrams shown in the "Hardware User's Manual."
S9-49
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
84-LEAD CERQUAD (J BEND)
TOP VIEW
I
I
I
--, ---1-----
1.170
I
D1iO
1.138
~
I
I
I
I
~14-~D_D_DD_DD_D_DD~
1 ~'-------------14.
_ _
~
1.170 _ _ _ _ _ _ _ _ _+1
r.TIiO
.026
.032
f
.155
:200
l
1"1--------- 1.000 REF ------~
\+-_ _ _ _ _ .548
368
- - - - - t o o..I1
SIDE VIEW
S9-50
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3010 RISC FLOATING POINT ACCELERATOR (FPA)
PACKAGE DIMENSIONS
84-PIN PGA(CAVITY DOWN)
BOTTOM VIEW
TOP VIEW
.060
.080.
NOTE 6
INDEXMARKJ
NOTES:
1. All dimensions are in inches, unless otherwise specified.
2. BSC - Basic Pin Spacing between centers.
3. Symbol "M" represents the PGA matrix size.
4. Symbol"N" represents the number of pins.
5. Chamferred corners are lOT's option.
6. Cross hatched area indicates integral metallic heat sink.
ORDERING INFORMATION
IDT79R3010
-.29LSpeed
__X__
Package
X
Processl
Temp. Range
S9-51
Blank
'B'
Commercial
Military
'G'
'OJ'
84-Pin PGA
84-Pin ~-Bend Cerquad
'16'
'20'
'25'
16.67 MHz
20.0 MHz
25.0 MHz
(;)
Intesrated Devlce1echnoIogy. Inc.
RISC CPU
WRITE BUFFER
PRELIMINARY
lOT 79R3020
FEATURES
DESCRIPTION
• Temporary storage buffers to enhance the performance of the
IDT79R3000 RISC CPU processor
The IDT79R3020 Write Buffer enhances the performance of
IDT79R3000 systems by allowing the processor to perform write
operations during Run cycles instead of resorting to timeconsuming stall cycles. Each IDT79R3020 device handles an 8-bit
slice of address, and a 9-bit slice of data (one parity bit per byte);
thus, four IDT79R3020s provide 4-deep buffering of 32 bits of
address and 36 bits of data and parity. Figure 1 illustrates the
functional position of the Write Buffer in an IDT79R3000 system.
Whenever the processor performs a write operation, the Write
Buffer captures the output data and its address (including the
access type bits). The Write Buffer can hold up to four
data-address sets while it waits to pass the data on to main
memory. Transfers from the processor to the write buffers occur
synchronously at the cycle rate of the processor and the write
buffer signals the processor if it is unable to accept data. The write
buffer also provides a set of handshake signals to communicate
with a main memory controller and coordinate the transfer of write
data to main memory.
The sections that follow describe these IDT79R3020 Write
Buffer interfaces:
• the processor-Write Buffer interface
• Allows for write operations by the RISC CPU processor during
Run cycles
• Each Write Buffer has four locations to handle an 8-bit address
slice and a 9-bit data slice (including a parity bit)
• High-speed CEMOS ™ technology
• Pin, functionally and software compatible with the MIPS
Computer Systems R2020 Write Buffer
• Military product compliant to MIL-STD-883, Class B
• the Write Buffer-main memory interface
• a miscellaneous, Write Buffer-board control Interface.
AdrLor-----------------------------~~----~
& Tag
Main
Memory
Controller
IDT79R3000
Processor
Control
Signals ~:------~
Control
Signals
Data
[031 :00]
Figure 1. The IDT79R3020 Write Buffer In an IDT79R3000 System
CEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
050-9023/1
S9-52
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
connected to the Write Buffer to form a 32-bit physical address that
is captured by the buffers. Thirty-two bits of data, four bits of parity,
and two access type bits are also captured by the Write Buffer. The
paragraphs that follow describe the Write Buffer-processor
interface signals and the timing of processor-to-Write Buffer data
transfers.
WRITE BUFFER - IDT79R3000 PROCESSOR
INTERFACE
Figure 2 shows the signals comprising the Write Buffer interface
to the IDT79R3000 (all descriptions assume that four IDT79R3020
Write Buffers are used to implement a 32-bit, buffered interface).
The AdrLo bus and Tag bus bits from the processor are both
32
/
/
/
AccTypO
MemWr*
WrBusy*
I
v:-
Addrln7:0
>-
Address1 :0
Dataln8:0
....
..,.
AccTyp1
Clock
~
/
36,
Data Bus
and Parity
Processor
...
.~
Address Bus
(AdrLo & Tag)
IDT79R3000
-
J'>
SysOut*
..,.
-
AccTypO
AccTyp1
Write
Buffer
(x 4)
WtMem*
WbFull*
CpCondO ~-------
Request*
Figure 2. Write Buffer-IDT79R3000 Processor. Interface
Write Buffer-Processor Interface Signals
be tested by software to determine if there is any data in the Write
Buffer. Since Request* is deasserted ifthere is no data in the Write
Buffer, software can determine if a previous write operation (for
example, to an I/O device) has been completed before initiating a
read or read status operation from that device.
Clock
An inverted version of the IDT79R3000's SysOut* signal from
the IDT79R3000 processor that synchronizes data transfers. The
Write Buffer uses the trailing edge of Clock to latch the contents of
the AdrLo bus and uses the leading Clock edge to latch the
contents of the Data and Tag buses.
WbFull*
The Write Buffer asserts this signal to the IDT79R3000's
WrBusy* input whenever it cannot accept any more data; that is,
when the current write will fill the buffer or the buffer has all
address-data pairs occupied. The IDT79R3000 processor
performs a write-busy stall if it needs to store data while the
WbFull*/WrBusy* Signal is asserted.
Oataln8:0
Nine input data lines from the IDT79R3000 processor's Data bus
(eight bits of data and one bit of parity).
Addrln7:0
Data & Address Connections
Eight input address lines from the IDT79R3000 processor. The
address lines are taken from the AdrLo and Tag buses.
Figure 3 illustrates how four Write Buffers are connected to the
address and data outputs of the IDT79R3000 processor.
Address1:0
Address Inputs
The two least significant address bits from the IDT79R3000
processor. These two address bits must be connected to all four
Write Buffers and are used in conjunction with the access type
(AccTyp1:0) signals, the Position1:0 signals, and the BigEndian
signal to determine which byte(s) in a word are being written into a
particular Write Buffer.
Each Write Buffer device has eight address inputs (Adrln7:0).
The four low-order bits (Adrln3:0) are clocked into the device on the
trailing edge of the Clock signal and are taken from the
IDT79R3000's AdrLo bus. The four high-order bits (Adrln7:4) are
clocked into the device on the rising edge of the Clock signal and
are taken from the IDT79R3000's Tag bus.
Each device also has separate inputs (Address 1, AddressO) for
the two low-order bits from the AdrLo bus. These bits must be input
to each device since they comprise the byte pointer. Note in Figure
3 that the two low-order Adrln inputs (Adrln1 :0) to Write Buffer
device 0 are connected to ground since the Address1, AddressO
inputs already supply these bits to the device.
AccTypln1 :0
The access type signals from the IDT79R3000 processor spec itying the size of a data access: word, tri-byte, half-word, or byte.
WtMem*
This input is connected to the MemWr* signal from the
IDT79R3000 processor that is asserted whenever the processor is
performing a store (write) operation.
Data Inputs
Request*
Each Write Buffer device has nine data inputs that are clocked
into the device onthe leading edge of the Clock signal and are
taken from the IDT79R3000's Data bus. In Figure 3, each device
captures eight bits of data and one bit of parity. Also note that the
data bits assigned to each device correspond to the address bits
The primary purpose of this signal is to request access to
memory and is described later when the Write Buffer-Main Memory
Interface is discussed. The Request* signal can also be
connected to the CpCondO input of the IDT79R3000 and can then
59-53
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
simplifies system utilization of the "Read Error Address" feature
described later.
connected to the device. This arrangement Is required since data
selection is dependent on a combination of the AccType signals
and the two low order address bits. The arrangement also
-
Data & / ' Data Bus [35:00)
Parity ~
Tag
~ag Bus [31 :16)
....
Read
Buffer
Adrln7:4
:i2>
Adrln3:0
6
~
Data15:1~ Dataln3:0
~
I--
.......
-
too-
I\V
Address~
Write
Buffer
Data35,31 :29 Dataln8:4
3
~
System Data Bus
System Address Bus
Tag31::f8>
AdrLo15
Kl....
>
....
IDT79R3000
Processor
~
.A
>
v
AdrLo Bus [15:00)
AdrLo
>
....
Address1 :0
Position 1
PosltlonO
.,.,.... . >
DataOut
1== "1"
"1"
.....
Tag27:~ Adrln7:4
"
Address ~
r...
AdrLo11 :08> Adrln3:0
Write
Data33,27:2.9 Dataln8:4 Buffer
2
DataOut I.....
K
Data11:oD Dataln3:0
Posltlon1 ~"1"
.....
PosltlonO
:::
-
I--
...
~
":::>
Tag23:20
1
~ "0"
Address1 :0
Adrln7:4
Address
::::
1 1
>
'"
&
AdrLo07: 04> Adrln3:0
Write
.....
Buffer
Data34,23~ Dataln8:4 1
Data07~
.....
~
~
too-
.-
Dataln3:0
Address1 :0
Tag19:1i'> Adrln7:4
~
AdrLo03,09 Adrln3:2
1
......
Data32,
19f19
Adrln1 :0
.....
Address~
Write
Buffer
0
Dataln8:4
~
Data03:~
I
..
~
'>
,.,...
DataOut
Posltlon1 ~"O"
PosltlonO ~"1"
Dataln3:0
Address1 :0
Figure 3. Write Buffer Data and Address Line Connections
The Position1 and PositionO signals shown in Figure 3 specify
the nibble position within a halfword that each write buffer device
comprises.
S9-S4
DataOut
Posltlon1 ~·O"
PosltlonO ~"o·
>
......
>
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
Write Buffer - Processor Timing
When the WrtMem* signal is asserted, the low-order address
bits, and the Address 1:0 inputs, are latched on the trailing edge of
the Clock signal (m). The rising edge of Clock ([]Jj) is used to
latch the high-order address bits, the access type Inputs and the
contents of the data bus.
Transfers between the processor and the Write Buffers occur
synchronously: the Clock signal from the processor is Input to the
Write Buffers and used to clock the address and data information
into the Write Buffers' latches. Figure 4 illustrates the timing forthe
processor-Write Buffer interface.
Clock
WtMem*
Adrln3:0
(AdrLo)
Address1:0
AccType1:0
Adrln7:4
(Tag)
Dataln
Figure 4. Processor-Write Buffer Interface Timing
WRITE BUFFER - MAIN MEMORY INTERFACE
of the memory interface signals and the Clock signal is required,
the handshaking signals in this interface have no direct connection
to the operation of the Write Buffer-processor interface.
Figure 5 shows the signals comprising the Write Buffer interface
to main memory. This interface is essentially decoupled from the
Write Buffer-processor interface: although some synchronization
OutEn'"
....
32
AddrOut
I
Write
Buffer
(x 4)
"
/
~
AccTypO
~
~
AccTyp1
36,
DataOut
and Parity
/
I
-V
Main
Memory
Controller
...
Request'"
Acknowledge
~
-~
-,.
Clock
~
Figure 5. Write Buffer-Main Memory Interface
Write Buffer - Main Memory Interface Signals
OutEn*
Each Write Buffer provides the following signals that comprise
the interface to a main memory controller:
The memory controller asserts this write input to enable the
tri-state outputs of the IDT79R3020 address and data signals.
AddrOut 7:0
Request*
Eight address line output from each Write Buffer.
The Write Buffer asserts this signal to inform the main memory
system that it has data to be written to memory.
DataOut 8:0
Acknowledge
Nine data lines from each Write Buffer (eight bits of data and one
bit of parity).
The main memory system asserts this signal when it has
captured the data presented by the Write Buffer on the DataOut
lines.
AccTyp 1:0
The access type signals from the Write Buffer specifying the size
of a data access: word, tri-byte, half-word, or byte.
S9-55
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
The Write Buffer responds to this signal by discarding the
address-data pair that was just output.
The memory system can deassert the OutEn* signal to return
the Write Buffers' address and data outputs to their tristate
condition.
Since the Request* signal remains asserted, the memory
system asserts the OutEn* signal again to enable the next
address-data pair onto the system buses.
When memory system has accepted the second address-data
pair, it again asserts the Acknowledge signal. If the Write
Buffer is now empty, it responds to this signal by deasserting
the Request* signal.
Write Buffer - Main Memory Interface Timing
Figure 6 illustrates the timing for the transfer of data from the
Write Buffer to the main memory system. The sequence illustrated
in this figure Is as follows:
When the Write Buffer has a data-address pair for transfer to
the memory system, it asserts the Request* signal.
II] When memory system is ready to handle the Write Buffer data,
it asserts the OutEn* signal to enable the Write Buffers'
address and data outputs onto the system buses.
When memory system no longer requires the Write Buffer
address and data outputs, it asserts the Acknowledge
signal.
m
I1JI
Clock
Request*
Acknowledge
OutEn*
AddrOut
DataOut
)
Figure 6. Write Buffer-Main Memory Interface Timing
Note that the buffer's interface to main memory is not completely asynchronous: assertion of the Request* signal by the Write
Buffer is synchronized with the rising edge of Clock, and the Acknowledge signal input by main memory has a minimum set up
and hold time in relation to the Clock signal.
output, then gathering is inhibited and the buffer contents are presented to the main memory controller. Subsequent writes are then
placed In another buffer. No reliance should be placed In any
aspect of gathering (except that it only involves sequential writes to
the same word address) as It is not readily deterministic.
Non-sequential writes to the same word address are not gathered.
Note that gathering can require that two main memory controller
references be used to empty a single Write Buffer entry. For example, this can occur if Bytes 0 and 3 of a word are sequentially
written. Where order in writing is important, such as in I/O
controllers, software should avoid sequential accesses to the same
word. In cases where write-read access ordering is important but
reading of the write location is not desired, such as during I/O, then
a write followed by a write to a dummy location followed by a read
of the dummy location will insure the first write has occurred before
continuing. Alternatively, the REQUEST ·signal can be tested to
determine that the Write Buffer is empty.
MISCELLANEOUS WRITE BUFFER - BOARD
LOGIC INTERFACE
The Write Buffers support several functions that utilize signals
that do not fit neatly into the descriptions of either the processor or
main memory interfaces. These functions and signals typically involve miscellaneous logic on a CPU board and include the following:
• byte gathering
• configuration connections (Big Endian, Position 1:0)
• address matching logic
• error address latch logic
The sections that follow describe each of these categories.
Configuration Logic Connections
Because of their byte gathering capability, each buffer device
internally maintains a record of each valid byte in an address/data
pair. To do this, each device must have a way of determining which
data bits within a word it is handling. The following signals determine how the write buffers handle data that is written to the devices:
• Position 1, Position 0 - these signals (in conjunction with Big
Endian*) determine how each Write Buffer decodes the Address 1/0 and AccType 1/0 to determine if it should store the
data inputs. Refer to Figure 3 for an illustration of how data bits
are assigned to Write Buffer devices based on their position.
• Big Endian * - When asserted, byte 0 is the leftmost, most significant byte (big-endian): when deasserted, byte 0 is the rightmost,
least-significant byte (little-endian).
Byte Gathering
The Write Buffers perform byte (half-word, tri-byte and word)
gathering to decrease the number of write transfers to same location; that is, sequential writes to the same WORD address have
their data combined into the same address-data pair buffer.
Byte gathering is prohibited in the address-data pair that is currently available to the memory controller. Thus, the first write into
an empty Write Buffer will not have subsequent writes gathered into
it because it is currently available for output to memory. Writes to
the same location (byte) may be overwritten in the Write Buffer if the
gathering is not prohibited by the preceding rule.
The Write Buffers present address-data pairs to the main memory controller in the sequence in which they were received from the
processor except in the case of gathered data, where bytes or half
words can be collected and written to main memory in a single
write operation. If the address-data pair buffer is scheduled to be
• Address 1, Address 0 - these signals (taken from the AdrLo bus)
must be connected to all buffer devices since they determine
which byte within a word is being accessed.
S9-56
----------------------------------------------------------------------------------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
• AccType 1, AccType 0 - these Inputs signals specify the data
size of a write operation as shown in Table 1.
Access
Type
1
0
Address
1
0
1
o
0
o
0
1
(word)
1
0
(triple-byte)
o
1
0
(byte)
Bytes Accessed
31
Big-Endian
o
Little-Endian
31
o
0
0
(halfword)
o
Table 1 shows how these signals operate to specify how bytes
are saved within the Write Buffers.
o
o
o
o
o
:::::::::0: ::1:»1:: 1
1
r
11
:::::})2':: .:::::::: ::'»:3'=::
: : : : 1 I :::::::::::3:::::::'"
1
1:>1 »1 : 0
::·1 /:::::>2:::::;:::: : 1
1
o
Table 1. Byte Specifications for Write Operations
by the main memory controller to ensure that the Write Buffer is
emptied before the read access with the conflicting address has
been performed.
Figure 7 illustrates the Write Buffer signals involved in address
comparison logic. Each write buffer provides four output Signals
(MatchOut A, B, C, and D) which correspond to the four buffer
ranks (A, B, C, D) in each device as shown in Figure 1. These
MatchOut signals can be externally NAND'ed as shown in Figure 7
to determine if the address being input matches those in any rank
of the Write Buffer.
The lower two address bits of the device in position zero (as
determined by the two POSITION inputs) are inhibited; that is, they
are not stored directly as they are output on the AdrLo bus. Instead,
on output, the lower two address bits are generated from the
indication of the positions of the valid data bytes as determined by
above table.
MatchOutlMatchin Logic and Read Conflicts
Whenever the processor references main memory (either a write
or a read reference), the Write Buffers compare the word address
from the CPU with the word addresses stored in the buffers. If any
word address matches, the buffers asserts signals that can be used
Write Buffer 3
MatchlnA
MatchlnB
...-t-t--I MatchlnC
...-t-t-i--I MatchlnD
MatchOutA 1 - - - - - - - - - ,
MatchOutB I - - -___~
MatchOutC t---~~
MatchOutD
MatchlnA
Write Buffer 2
MatchlnA
MatchlnB
....-1--1--1 MatchlnC
e--I--I--I--I MatchlnD
L==::--;::::===::j
MatchOutA
MatchOutB I - -___~
MatchOutC
MatchOutD
MatchlnB
Write Buffer 1
MatchlnA
MatchlnB
e-+-+---I MatchlnC
....-1-+-+---1 MatchlnD
MatchlnC
MatchOutA I - - - - - - . J
MatchOutB I---__~
MatchOutC
MatchOutD
MatchlnD
Write Buffer 0
MatchlnA
MatchlnB
e - - - - l MatchlnC
e - - I - - - - l MatchlnD
MatchOutA 1 - - - - - . . . . 1
MatchOutB I------~
MatchOutC
MatchOutD
To ~ain ~ernory
Controller
CONFLICT
Figure 7. Write Buffer MatchOut/Matchln Logic
S9-57
IDT79R3020 RISC CPU WRITE BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Error Address Latch
The outputs of the NAND gates are fed into Write Buffers via the
Matchln A, B, C, and D signals and are used within each device as
part of the byte gathering logic. The NAND gate outputs can be
NAND'ed together as shown in Figure 7 with the resultant Signal
used (in conjunction with the processor's MEMRD signal) to alert
the main memory controller logic that there is a pending buffered
write that conflicts with a just-issued read. The main memory
controller can then delay the read access until the Request signal is
deasserted indicating that the Write Buffer has been emptied.
The write buffer incorporates an internal latch that can be loaded
with one of the buffered addresses and subsequently enabled out
onto the data lines. This feature can be used by error handling
routines to read an address back from the Write Buffer and analyze
or recover from certain bus errors. Figure 8 shows the signals
involved in operation of this latch.
IDT79R3020 Write Buffers
Error Address
Latch
Figure 8. The Write Buffer Error Address Latch
When the Latch ErrAddr signal is asserted, the address currently
available to the address outputs of the Write Buffer is latched into
the intemallatch.This address can then be output on the DataOut
lines by asserting the EnErrAdr signal so that the processor can
read the· address in as data. Refer to the AC specifications for
timing parameters of the signals associated with the error address
latch.
S9-58
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1.3)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBiAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
"IN
Input Voltage (2)
-0.5 to +7.0
-0.5 to +7.0
V
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 5%
Commercial
Vee
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = 3.0V for pulse width less than 15ns. V IN maximum
should not exceed Vec +0.5 volts.
3. Not more than one output should be shorted at a time. Duration to the
short should no exceed 30 seconds.
DC ELECTRICAL CHARACTERISTICSCOMMERCIAL TEMPERATURE RANGE (TA
SYMBOL
PARAMETER
= 0°Ct070°C. Vee = +5.0V ± 5%
16.67 MHz
MIN.
MAX.
TEST CONDITIONS
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
= Min. 10H = -4mA
= Min. IOL = 4mA
20.0 MHz
MIN.
MAX.
25.0 MHz
MIN.
MAX.
UNIT
3.5
-
3.5
-
3.5
-
V
-
0.4
-
0.4
-
0.4
V
V
V IH
Input HIGH Voltage(l)
2.4
-
2.4
-
2.4
-
V IL
Input LOW Voltage(2)
-
0.8
-
0.8
-
0.8
V
CIN
Input Capacitance
10
10
10
10
-
pF
Output Capacitance
-
10
COUT
-
pF
Icc
Operating Current
-
50
60
-
70
mA
Vce
= Max
IIH
Input HIGH Leakage
VIH = Vee
IlL
Input LOW Leakage
loz
Output Tri-state Leakage
= Gnd
VOH = 2.4V. VOL = 0.5V
VIL
DC ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE (TA = -55°C to 125°C. Vee =
SYMBOL
PARAMETER
10
-
10
-
10
-
10
JlA
-10
-
-10
-
-10
-
JlA
-40
40
-40
40
-40
40
JlA
+50 V -+ 10%
TEST CONDITIONS
= Min. 10H = -4mA
= Min. 10L = 4mA
16.67 MHz
MAX.
UNIT
3.5
-
V
-
0.4
V
MIN.
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
V IH
Input HIGH Voltage(l)
2.4
-
V
V IL
Input LOW Voltage(2)
-
0.8
V
CIN
Input Capacitance
10
-
pF
CO UT
Output Capacitance
10
-
pF
Icc
Operating Current
-
90
mA
hH
Input HIGH Leakage
VIH
-
10
JlA
IlL
Input LOW Leakage
VIL = Gnd
-10
-
JlA
40
JlA
Vee
= Max
= Vee
-40
Output Tri-state Leakage
VOH = 2.4V,VOL = 0.5V
loz
NOTES:
1. VIH should be held above Vee + 0.5 Volts.
2. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 Volts for longer periods.
S9-59
----
-----_.-------------
IDT79R3020 RISC CPU WRITE BUFFER
AC ELECTRICAL CHARACTERISTICS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(TA
= O°C to 70°C
Vee
PARAMETER
SYMBOL
= + 50 V -+
5%
16.67 MHz
MIN.
MAX.
20.0 MHz
MIN.
MAX.
25.0 MHz
MIN.
MAX.
UNIT
t1
Addrin (3:0) to Clock falling setup
8
-
7
-
Addrin (3:0) from Clock falling hold
4
-
4
-
6
t2
4
-
ns
t3
Address 1:0 to Clock falling setup
8
-
7
-
6
-
ns
t4
Address 1:0 from Clock falling hold
4
-
4
-
4
-
ns
t5
Access Type 1:0 to Clock rising setup
7
-
6
5
Access Type 1:0 from Clock rising hold
3
-
3
2
-
ns
t6
-
t7
Addrin (7:4) to Clock rising setup
7
-
5
-
5
-
ns
t8
Addrin (7:4) from Clock rising hold
3
-
3
-
2
-
ns
t9
Dataln (8:0) to Clock rising setup
7
-
5
-
5
-
ns
t10
Dataln (8:0) from Clock rising hold
3
-
3
2
-
ns
t11
WrtMem* to Clock rising setup
10
-
8
-
"1
-
ns
t12
WrtMem* from Clock rising hold
6
-
5
-
4
-
ns
t13
Request from Clock rising
-
32
-
30
-
27
ns
t14
Acknowledge to Clock rising setup
12
-
11
-
10
-
ns
t15
Acknowledge from Clock rising hold
7
-
6
-
5
ns
t16
Latch ErrAdr to Acknowledge rising
5
-
5
-
5
-
t17
WbFull* active from Clock rising
-
32
-
30
-
27
ns
t18
WbFull* inactive from Clock rising
-
32
-
30
-
27
ns
t19
OutEn to. AddrOut (7:0), DataOut (8:0) valid
2
15
2
15
2
15
ns
t20
OutEn to AddrOut (7:0), DataOut (8:0) tri-state
2
15
2
15
2
15
ns
ns
ns
ns
t21
MatchOut (ABCD) from Clock rising
-
25
-
24
-
23
ns
t22
Matchln (ABCD)
t~
10
-
9
-
8
-
ns
t23
Matchln (ABCD) from Clock rising hold
3
-
3
-
3
-
ns
t24
EnErrAdr* to Data (error latch) valid
2
15
2
15
2
15
ns
2
Clock rising setup
t25
EnErrAdr* to Data (error latch) tri-state
2
15
t26
Address/Data out from Clock rising
-
32
t27
Reset* to Clock rising, set-up
8
Reset* from Clock rising, hold
3
-
7
t28
t29
Reset low pulse width
10
-
. t30
15
2
15
ns
30
-
27
ns
-
5
1
-
ns
2
10
-
10
-
ns
ns
WbFull* High from Clock rising (after Reset*)
3
22
3
21
3
20
ns
t31
Request* High from Reset* low
3
20
3
19
3
18
ns
t32
Access Type 1:0 low from Reset* low
3
28
3
26
3
25
ns
t33
Match Out (ABCD) Low from Reset* low
3
21
3
20
3
20
ns
S9-60
---.-.-.-------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
AC ELECTRICAL CHARACTERISTICS - MILITARY TEMPERATURE RANGE (fA = -55°Cto 125°C Vee = + 5 OV -+
16.67 MHz
10%
MIN.
MAX.
UNIT
t1
Addrin (3:0) to Clock falling setup
8
-
ns
t2
Addrin (3:0) from Clock falling hold
4
-
ns
t3
Address 1:0 to Clock falling setup
8
t4
Address 1:0 from Clock falling hold
4
t5
Access Type 1:0 to Clock rising setup
7
t6
Access Type 1:0 from Clock rising hold
3
t7
Addrin (7:4) to Clock rising setup
7
t8
Addrin (7:4) from Clock rising hold
3
-
t9
Dataln (8:0) to Clock rising setup
7
-
ns
no
Dataln (8:0) from Clock rising hold
3
-
ns
t11
WrtMem* to Clock rising setup
10
-
ns
t12
WrtMem* from Clock rising hold
6
-
ns
t13
Request from Clock rising
-
32
ns
t14
Acknowledge to Clock rising setup
12
ns
t15
Acknowledge to Clock rising hold
7
t16
LatchErrAdr to Acknowledge rising
t17
WbFuU· active from Clock rising
32
ns
t18
WbFull· inactive from Clock rising
5
-
32
ns
t19
OutEn to AddrOut (7:0). DataOut (8:0) valid
2
15
ns
t20
OutEn to AddrOut (7:0). DataOut (8:0) tri-state
2
15
ns
t21
MatchOut (ABCD) from Clock rising
-
25
ns
t22
Matchln (ABCD) to Clock rising setup
10
-
ns
ns
PARAMETER
SYMBOL
ns
ns
ns
ns
ns
ns
ns
ns
t23
Matchln (ABCD) from Clock rising hold
3
t24
EnErrAdr· to Data (error latch) valid
2
15
ns
t25
EnErrAdr* to Data (error latch) tri-state
2
15
ns
t26
Address/Data out from Clock rising
-
32
ns
t27
Reset· to Clock rising. set-up
8
ns
t28
Reset· from Clock rising. hold
3
t29
Reset low pulse width
10
-
t30
WbFull·. High from Clock rising. (after Reset·)
3
22
ns
ns
ns
t31
Request· High from Reset· low
3
20
ns
t32
Access Type 1:0 Low from Reset· low
3
28
ns
t33
Match Out (ABCD) Low from Reset· low
3
21
ns
S9-61
...
_------_._--_ _ - - ..•
- - - - ------_...._._._----
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
Clock
I
WTMEM*
..,
..,
..,
Adrln3:0
(AdrLo)
t1
Ht12
t3
Ht2
8
I
AccType1:0
I
1\
t4
I..,
..,
Address1:0
\
~1
Adrln7:4
(Tag)
I
I
Dataln
t 5 H ts
"
I
t 7 H t8
"
...J t9~t10
H t 13
REQUEST*
.., t14 H t 15
Acknowledge
t 1S
LatchErrAdr
/---l
------------------------~/
,-------
Figure 9. Write Buffer Timing Specifications
Clock
I
\
\
WTMEM*
REQUEST*
WbFull*
Acknowledge
t17H
_____________
~t18
~f\~
____________________
Figure 10. WBFULL* Signal Timing Specifications
S9-62
IDT79R3020 RISC CPU WRITE BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.
OutEn*
DataOut
AddrOut
Figure 11. OUTEN* Timing Specifications
Clock
WTMEM*
MatchOut
(ABCD)
Matchln
(ABCD)
EnErrAdr*
DataOut
Error Latch Data Out
Figure 12. Match and Error Latch Timing Specifications
Clock
Address/Data
\
X
t
\
t 26
REQUEST*
Acknowledge
/
\
Figure 13. Address/Data Out
59-63
.1
X
/
\
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT79R3020 RISC CPU WRITE BUFFER
S8-Pin CPGA for R3020
Pin Grid Array (Ceramic) - Bottom View
CLOCK
ACC·
AC·
AD·
TYPEO KNOWL· DRESS1
EDGE
L
K
GND1
VCC1
ACC·
TYPE1
DATA·
INO
BIGEN·
AD·
EN·
DRESSO DIAN ERROR·
A~R
DATA·
IN2
DATA·
IN4
DATA·
IN6
VCC2
DATA·
IN1
DATA·
IN3
DATA·
IN5
GND2
DATA·
IN7
ADDR·
OUT5
ADDR·
OUT4
DATA·
INS
ADDR·
INO
H
ADDR·
OUT3
ADDR·
OUT2
ADDR·
IN1
ADDR·
IN2
G
ADDR·
OUT1
ADDR·
OUTO
ADDR·
IN3
ADDR·
IN4
F
DATA·
OUTS
DATA·
OUTO
ADDR·
IN5
ADDR·
IN6
E
DATA·
OUT1
DATA·
OUT2
ADDR·
IN7
LATCH·
ERR·
ADR
D
DATA·
OUT3
ADDR·
OUT6
MATCH· MATCH·
INA
INB
C
ADDR·
OUT7
ACC·
TYPE
OUT1
MATCH· MATCH·
INC
IND
ACC·
TYPE
OUTO
GNDO
B
A
DATA·
OUT7
DATA·
OUT4
RE·
MATCH· MATCH· RESET
PO·
QUEST OUTC
oUTA
SITIONO
*
vcca
2
DATA·
OUT5
3
VCC3
GND3
*
DATA· WBFULL MATCH· MATCH· WTMEM
OUTEN
PO·
OUT6
OUTO
OUTB
SITION1
*
4
*
*
5
6
* = TRI·STATE OUTPUT
35 INPUTS, 25 OUTPUTS
4VCC, 4 VSS
S9-64
7
S
9
10
11
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTI9R3020 RISC CPU WRITE BUFFER
PIN CONFIGURATION
Plastic Leaded Chip Carrier
(Top View)
9
VSSO
ACCTVPEOUTO
ACCTVPEOUT1
ADDROUT7
ADDROUT6
DATAOUT3
DATAOUT2
DATAOUT1
DATAOUTO
DATAOUT8
ADDROUTO
ADDROUT1
ADDROUT2
ADDROUT3
ADDROUT4
ADDROUT5
VSS1
8 7
6 5
."
2 1 68 67 66 65 64 63 62 61
4 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Index
VSS3
MATCHIND
MATCHINC
MATCHINB
MATCHINA
LATCHERRADR
ADDRIN7
ADDRIN6
ADDRIN5
ADDRIN4
ADDRIN3
ADDRIN2
ADDRIN1
ADDRINO
DATAIN8
DATAIN7
VSS2
2728293031 32333435363738394041 4243
ORDERING INFORMATION
IDT 79R3020
-
xx
X
X
Speed
Package
Process!
Temp. Range
'B'
Commercial
Military
'G'
, J'
68-Pln PGA
68-Pin PLCC
'16'
'20'
'25'
16.67 MHz
20.0 MHz
25.0 MHz
Blank
S9-65
!
)
SYSTEM PROGRAMMERS PACKAGE (SPP)
Integrated DevicelechnoIogy.Inc.
INTRODUCTION:
•
•
•
•
•
The System Programmer's package (SPP) provides tools for
software developers who need to write programs for an
IDT79R3000 processor that doesn't have Its own operating system
or a disk. The SPP consists of development commands (which you
use from your host development machine) and test machine standalone environment programs. Standalone programs can be diagnostics, your own operating system kernel, device drivers or embedded applications.
Debug monitor (dbgmon)
PROM code (3 versions)
UNIX system call subset
Device drivers in source form
Power on diagnostics suite
APPLICATIONS:
• Write and compile standalone programs on host development
machine
FEATURES:
• Debug standalone programs in an environment called "sable",
which simulates the processor
•
•
•
•
•
• Debug standalone programs on your test machine from the development machine
• Download the final product to the test machine
• Boot and run programs on the test machine
Standalone PROM system bring-up tool
Available in source form for customization
Provides sophisticated monitor capabilities for download
Links with symbolic debugger on host system
UNIX tools to compile, build and download
DEVELOPMENT ENVIRONMENT
Compile (sacc)
Run Debugger (pdbx or sdbx)
Download to test (no Ethernet)
Download from host (Ethernet)
Communicate with Test programs
Development Machine Console
Test Machine Console
Some Standalone Programs
The Simulation Environment
(sable)
Monitor & Standalone Shell
(sash)
Ethernet (download programs)
JANUARY 1989
©
DSO-0027/-
1989 Integrated Device Technology, Inc.
S9-66
The Simulation Environment (sable)
Sable runs on host development machines. It simulates the
processor, all machine instructions, cache, tran~lati,?n buffer behavior, a simple disk and a simple console terminal Interface.
Sable expedites development of standalone programs and operating systems because you can develop software without needing prototype hardware. Programs that you compile wit~ sacc and
saas run in the environment. To do source-level debugging of programs that run under sable, you need to use sdbx which is a version of dbx that works with sable.
The Standalone I/O Library (saio)
When you write programs on the development machine for the
standalone environment or for sable, you need to use the standalone I/O library (saio). These UNIX system-like routines support
access to disks, tape, Ethernet and UARTS. The library also provides most standard Iibc and stdio routines.
cess to remote machines. Typically, you will use bfsd to download
bootable images from the development machine to a test machine
that does not have a disk.
Bfsd services file requests from standalone programs built with
the standalone I/O (saio) library. You can use bfsd to boot operating system kernels, diagnostic programs and standalone programs.
The Monitor and Standalone Shell (sash)
. The PROM Monitor provides the tools to examine and change
PROM memory, download programs over serial lines (RS232),
boot programs from disk, tape and Ethernet, and alter configuration, power-up options in non-volatile RAM.
The standalone shell (sash) is a version of the PROM Monitor
that supports more devices, file system formats, and command,s
than the standard Monitor. You load the sash from the PROM Momtor,
The Simple-PROM
The Compiler System (sacc, saas, said)
The Simple-PROM is a simplified combination of the PROM
Monitor and Debug Monitor (dbgmon). It relies only on the presence of the processor and a UART, The simple-PROM makes no
other assumptions regarding hardware configurations and board
level features.
The Simple-PROM helps you develop board-level products
quickly for the processor. You can also customize the SimplePROM to your own environment.
To compile most programs (for example, diagnostics) that will
run in the standalone environment on the test machine or under sable, you can use sacc for C programs and saas for assembly language programs. Said links and loads the saio library for you.
These shell script commands reside in /usr/spp on the development machine.
Debuggers (sdbx, pdbx)
The Debug Monitor (dbgmon)
The SPP provides two versions of dbx (pdbx and sdbx) to help
you debug standalone programs. These versions provide all regular dbx features.
Use dbx to debug programs that execute on your local machine,
sdbx to debug programs running under sable, and pdbx ,to debu,g
programs on another machine (usually, your test machine). This
last method lets you use all the tools of the development environment to debug programs on real hardware. When you debug programs on the test machine, debugging information flows between
the development. machine and the test machine over an RS232
line.
The Debug Monitor (dbgmon) is the standalone environment
debugger. You can co-load dbgmon with any st~ndalone program
or operating system. The dbgmon lets you examine and alter memory and registers, set bre~kpoints, examine translation b~ffer entires, disassemble instructions and execute programs one Instruction at a time.
If you use the dbgmon with pdbx, you can do source-level, symbolic debugging of any standalone program or operating system
that runs on your test machine.
Bootfile Server Driver (bfsd)
The Ethernet bootfile server driver (bfsd) provides remote file ac-
S9-67
R3000 MAC II BOARD
Integrated Devlceledmology.lnc.
FEATURES:
• NuBus ™ card for a Macintosh or MAC IIx provides a standalone
single-user environment for code development for the·
IDT79R3000
• Utilizes IDT79R3000 32-bit Microprocessor
• Incorporates two caches of 16K words each for Instruction and
Data
• Supplied with UNIX ™ Operating System (RISC/os 1M) which includes such tools as:
- "C" Language Compiler
- IDT79R3000 assembler
- Symbolic Debugger
- Program Performance Profiler (Pixie)
• Systems Programmer Package available for execution on this
board Includes the following features:
- Instruction set simulator (Sable)
- CPU/FPU·diagnostics suite
- Host to target cross Symbolic Code debugger
- Cache performance evaluation tools
- Retargetable monitor PROM source code
• Other Languages available are:
- PL/1
- Pascal
- COBOL
- FORTRAN
-Ada
• Macintosh 1M Operating System User Interface accessible to users so that other Apple Macintosh tools can be operated.
DESCRIPTION:
This board is designed to run the UNIX operating systems,
compilers and tools in a single-user standalone mode for
development of code for the IDT79R3000. It is composed of a
ADVANCE
INFORMATION
IDT7RS201
IDT79R3000 32-bit microprocessor, 2 caches for instruction and
data as well asa Macintosh II NuBus interface. When inserted into a
Macintosh II, the IDT79RS201 board becomes an auxiliary processor responsible for running the UNIX operating system. The 68020,
in the Macintosh II mother board, acts as an I/O server and runs the
Macintosh OS. The main memory of the Macintosh II is accessible
to both processors and is used as communication memory as well
as for holding programs for both processors.
The IDT79RS201 incorporates a IDT79R3000 as well as two
caches. When a cache miss is encountered, the 32-bit NuBus interface is utilized to fetch the word from the shared memory of the
Macintosh II. Words stored in memory are automatically written
through the Macintosh II interface and into main memory. In this
manner, the IDT79RS201 board provides high performance in the
NuBus environment.
The Macintosh 68020 is used as an I/O processor to handle the
I/O requests of the UNIX operating system that is executed by the
IDT79RS201 board. Requests to the 68020 are made through
shared memory buffers which provide support for passing disk
blocks and character string data. The 68020 then serves the requests forthe disk I/O by executing device drivers in the Macintosh
OS. The user directed character I/O is handled by a terminal emulator running in parallel on the Macintosh II and serves to emulate a
character oriented CRT. Other serial I/O is passed on to the actual
serial I/O ports of the Macintosh II and allows for the downloading
of data into devices such as printers and PROM formatters.
The "C" compiler, that comes standard with the IDT79RS201', is
Kernighan/Ritchie (System V) and includes additional features
such as: Enumerations, Volatile data type, Function prototypes,
etc. The compiler incorporates some clarifications of hazy spots
from dpANS C. The source-level debugger, that comes with this
development package, allows the user to single-step and trace at
both the "C" level as well as the machine level for code development. The user Is allowed to create macros of frequently used debug sequences and keep a history of previous debug steps taken
for later re-execution. The performance profiling tools provided
allow the programer to produce histograms of procedure calls and
source-code statements. The profiler reports procedures and lines
of source-code that are not executed for test coverage purposes.
Macintosh II used as a development
system for IDT79R3000 by incorporating
an IDT7RS201 board and software
JANUARY 1989
© 1989 Integrated Device Technology, Inc.
DSC-9024/-
S9-68
-------------------------------------------
IDT7R5201 R3000 MAC II BOARD
System block diagram of R3000 board interfaced to the Macintosh II.
59-69
IDT7RS201 R3000 MAC II BOARD
System Programmer's Package (SPP) for
Software Development and System Integration
RISC Optimizing Compilers
The RISCompllers provide an effective programming environment with a family of compilers that share unique optimization
technology. The basic compiler and optimization techniques were
developed simultaneously with the RISC processor architecture
and instruction set.
A common goal was to increase computing performance and
efficiency. The resulting RISC hardware and software work
smoothly together to deliver a new level of excellence In program
development and execution.
Designed to run with the UNIX operating system, these
RISCompilers incorporate Industry standards in all areas. OptimizIng compilers now available include:
C·
.
Kernighan/Ritchie (System V)
Hazy spots clarified from dpANS C
Allows UNIX to be optimized
Function prototypes-graphics, etc
FORTRAN77 Fortran77, validated
Common extensions & dialects
DEC VMS features
FORTRAN66 compatibility features
Support for unaligned data items
Fast accurate math library
Pascal
Extensions dpANS where
appropriate
Separate compilation
Single and double precision floats
Bit manipulation
Interfaces well with C
COBOL 85
Shares library and compiler with PL/1
Decimal handled by tuned
subroutines
Based upon LPI-COBOL
Ada
Full Ada-ANSI-MIL STD 185A 1983
Current validation -1.9 ACVC,
UMIPS 3.0
Verdix Ada front end
UMIPS optimizing back-end.
PL/1
PL/1 Subset G
A few extensions like SELECT
Used to port 1.8 M line program
Based upon LPI-PL/1
The System Programmer's Package (SPP) is a powerful tool kit
.. for developing system software and Integrating hardware/software
on the target system. SPP provides everything needed to create
complete software systems in a native environment without prototype hardware. SPP features include:
• Simulation environment for developing software before hardware exists.
• UNIX tools to compile, simulate, build and download code
to the target hardware. There are sets of utilities for building
routines such as I/O drivers.
• Run-time routines to install/modify for the final product.
• Debug monitor for target hardware/software integration. Capabilities to examine and alter registers and memory, set
breakpoints and perform single-line assembly and disassembly.
• Applications profiling and cache usage simulator. Profiling
feature determines time spent in various parts of the program
helping to identify program bottlenecks.
NuBus is a trademark of Texas Instruments
Macintosh is a registered trademark of Apple Computer, Inc.
UNIX is a registered trademark of AT&T, Inc.
VMS is a registered trademark of Digital Equipment Corp.
RISC/os is a registered trademark of MIPS Computer Systems, Inc.
S9-70
-----------------------------------------------------------------------------------------------
M/120 RISComputer
Intesrated DeviceTechnology. Inc.
DEVELOPMENT SYSTEM
PRELIMINARY
INFORMATION
The M/120 RISComputer Development System
FEATURES:
• Development system that supports multiple users for software
development and debugging. Direct connections for up to 36
serial ports.
• Two basic types available:
- M/120-3 with 12MHz CPU rated at 9 mips processing power
- M/120-5 with 16.7MHz CPU rated at 12 mips processing
power
• All systems come standard with UNIXTM (RISC/osTM),
C language RISCompiler, and basic debugging tools.
• Optional optimizing compilers currently available include:
FORTRAN, Pascal, COBOL, PL/1, Ada
• System Programmer's Package (SPP) available for advanced
development environments
• Four AT slots provide for expansion with cost effective
peripherals.
• Third-party software available through Synthesis Software Solutions, Inc., an independent company providing software for
MIPSTM based systems
• Compact 23" high package for convenient location in the
workplace
• 8MB to 48MB main memory for large programs and multiple
users
• Integral Ethernet for high speed LAN connectivity
• SVID complaint UNIX operating system converging System V
and BSD
• Binary compatible with other MIPS M-Series RISComputers™
• Supports networking standards, including Ethernet, TCP/IP,
and Network File System (NFS"')
DESCRIPTION:
The M/120 development system provides a stable software development and debug environment for designing R3000 RISC
based systems. Utilizing the MIPS' port of UNIX (RISC/os), and
highly optimized RISCompilers, the development system allows
the user to begin software development and integration well in
advance of operational hardware.
All systems come standard with the RISC/os which includes the
assembler, the C optimizing compiler, and the linker, loader and
symbolic debugger. The RISC/os also includes the Network File
System (NFS) for networking support and utilities converging
UNIX System V.3 and BSD 4.3 versions of UNIX in order to support
the largest set of UNIX application programs.
The entire suite of MIPS language products is available on
M/120 systems. In addition to the C language, the M/120 supports
FORTRAN with VMS ™ extensions, Pascal, COBOL, Ada, and
PL/1. All these language compilers include multi-level optimizations designed to maximize program execution speed.
RISComputers is a registered trademark of MIPS Computer Systems, Inc.
RISC/os is a registered trademark of MIPS Computer Systems, Inc.
MIPS is a registered trademark of MIPS Computer Systems, Inc.
NFS is a registered trademark of Sun Microsystems.
UNIX is a registered trademark of AT&T.
VMS is a registered trademark of Digital Equipment Corp.
JANUARY 1989
©
DSC-9025/-
19891nlegralad Device Technology, Inc.
89-71
M/120 RISCOMPUTER DEVELOPMENT SYSTEM
RISC Optimizing Compilers
The RISCompilers provide an effective programming environment with a family of compilers that share unique optimization
technology. The basic compiler and optimization techniques were
developed simultaneously with its RISC architecture and instruction set. The resulting RISC hardware and software work smoothly
together to deliver a new level of excellence in program development and execution.
Designed .. to run' with the UNIX operating system, these
RISCompilers incorporate industry standards in all areas. Optimizing compliers now available include:
C
Kernighan/Ritchie (System V)
Hazy spots clarified from dpANS C
Allows UNIX to be optimized
Function prototypes-graphics, etc
FORTRAN77 Fortran77, validated
Common extensions & dialects
DEC VMS features
FORTRAN66 compatibility features
Support for unaligned data items
Fast accurate math library
Extensions dpANS where
Pascal
appropriate
Separate compilation
Single and double precision floats
Bit manipulation
Interfaces well with C
Shares library and compiler with PL/1
COBOL 85
Decimal handled by tuned
subroutines
Based upon LPI-COBOL
Ada
Full Ada-ANSI-MIL STD 185A 1983
Current validation -1.9 ACVC,
UMIPS 3.0
Verdix Ada front end '.
UMIPS optimizing back-end.
PL/1
PL 1 Subset G
A few extensions like SELECT
Used to port 1.8 M line program
Based upon LPI-PL/1
.
System Programmer's Package (SPP) for
Software Development and System Integration
The System Programmer's Package (SPP) is a powerful tool kit
for developing system software and integrating hardware/software
. on the target system. SPP provides everything needed to create
complete software systems in a native environment without prototype hardware. SPP features include:
• Simulation environment for developing software before hardware exists.
• UNIX tools to compile, simulate, build and download code
to the target hardware. There are sets of utilities for building
routines such as I/O drivers.
• Run-time routines to install/modify for the final product.
• Debug monitor for target hardware/software integration. Capabilities to examine and alter registers and memory, set
breakpoints and perform single-line assembly and disassembly.
'
• Applications profiling and cache usage simulator. Profiling
feature determines time spent in various parts of the program
helping to identify program bottlenecks.
M/120 Development System Configurations:
Model#
8102
Description
M/120-5 RISComputer
Development System includes:
• 16.7MHz CPU with Floating Point Accelerator
• 8MB main memory
• Ethernet controller
• SCSI controller
• 128K of 1&0 caches
• Four serial ports
• 328MB 5.25" disk
• 120MB cartridge tape
• Four AT bus slots
• Networking software
• RISC/os with C compiler
8101
Same as Model 8102, but with 156MB disk.
8114
Same as Model 8102, but with 16MB disk main
memory and console VDT.
8104
M/120-3 RISComputer Development System
with 12MHz CPU; other configuration items same
as Model 8102.
8103
Same as Model 8104, but with 156MB disk.
Note: Additional memory, disk peripherals, and interface options, such as Ethernet or serial I/O, are also available from
lOT.
S9-72
t;J
Intesrated Device1echnology. Inc.
M/2000 RISComputer
DEVELOPMENT SYSTEM
PRELIMINARY
INFORMATION
The M/2000 RISComputer Development System
FEATURES:
• High performance development system with connections for up
to 64 serial lines to support large projects doing software development and debugging of R3000-based designs
• Two basic types available:
- M/2000 -8 with 25MHz R3000 CPU rated at 20 mips
processing power
- M/2000 -6 with 20MHz R3000 CPU
• Each system includes the R3000, the R3010 FPA, and 128KB of
high-speed cache for instructions and data
• All systems come standard with MIPS'''' port of UNIX'" (RISC/
os"'), C language optimizing RISCompiler, and basic debugging tools
• Optional optimizing compilers currently available include:
FORTRAN, Pascal, COBOL, PL1, Ada
• System Programmer's Package (SPP) available for advanced
development environments
• Thirteen slots available for expansion with high performance
peripherals
• Third-party software available through Synthesis Software Solutions, Inc., an independent company providing software for
R3000-based systems
• 16MB to 128MB main memory for large programs and multiple
users
• SVID complaint UNIX operating system converging System V
.
and BSD
• Binary compatible with other MIPS M-Series RISComputers'"
• Supports networking standards, including Ethernet, TCP/IP:
and Network File System (NFS"')
DESCRIPTION:
The M/2000 development system provides a high performance
environment for software development and debugging to support
large projects designing R3000 RISC-based systems. Utilizing the
MIPS' port of UNIX (RISC/os), and highly optimizing RISCompilers, the development system allows the users to begin software
development and integration well in advance of operational
hardware.
All systems come standard with the RISC/os which includes the
assembler, the C optimizing compiler, and the linker, loader and
symbolic debugger. The RISC/os also includes the Network File
System (NFS) for networking support and utilities converging
UNIX System V.3 and BSD 4.3 versions of UNIX in order to support
the largest set of UNIX application programs.
The entire suite of MIPS language products is available on
M/2000 systems. In addition to the C language, the M/2000 supports FORTRAN with VMS ™ extensions, Pascal, COBOL, Ada,
and PL1. All these language compilers include multi-level optimizations designed to maximize program execution speed.
RISComputers is a registered trademark of MIPS Computer Systems, Inc.
RISC/os is a registered trademark of MIPS Computer Systems, Inc.
MIPS is a registered trademark of MIPS Computer Systems, Inc.
NFS is a registered trademark of Sun Microsystems.
UNIX is a registered trademark of AT&T.
VMS is a registered trademark of Digital Equipment Corp.
JANUARY 1989
©
DSC-9026/-
1989 Integrated Device Technology, Inc.
59-73
M/2000 RISCOMPUTER DEVELOPMENT SYSTEM
RISC Optimizing Compilers
System Programmer's Package (SPP) for
Software Development and System Integration
The RISCompliers provide an effective programming environment with a family of compilers that share unique optimization
technology. The basic compiler and opti mization techniques were
developed simultaneously with the RISC processor architecture
and instruction set.
A common goal was to increase computing performance and
efficiency. The resulting RISC hardware and software work
smoothly together to deliver a new level of excellence in program
development and execution.
Designed to run with the UNIX operating system, these
RISCompilers incorporate industry standards in all areas. Optimizing compilers now available include:
C
Kernighan/Ritchie (System V)
Hazy spots clarified from dpANS C
Allows UNIX to be optimized
Function prototypes-graphics, etc
FORTRAN77 Fortran77, validated
Common extensions & dialects
DEC VMS features
FORTRAN66 compatibility features
Support for unaligned data items
Fast accurate math library
Pascal
Extensions dpANS where
appropriate
Separate compilation
Single and double precision floats
Bit manipulation
Interfaces well with C
COBOL 85
Shares library and compiler with PU1
Decimal handled by tuned
subroutines
Based upon LPI-COBOL
Ada
Full Ada-ANSI-MIL STD 185A 1983
Current validation -1.9 ACVC,
UMIPS 3.0
Verdix Ada front end, UMIPS
optimizing back-end.
PU1
PL 1 Subset G
.
A few extensions like SELECT
Used to port 1.8 M line program
Based upon LPI-PU1
The System Programmer's Package (SPP) is a powerful toolkit
for developing system software and integrating hardware/software
on the target system. SPP provides everything needed to create
complete software systems in a native environment without prototype hardware. SPP features include:
• Si mulation environment for developing software before hardware exists.
• UNIX tools to compile, simulate, build and download code
to the target hardware. There are sets of utilities for building
routines such as I/O drivers.
• Run-time routines to install/modify for the final product.
• Debug monitor for target hardware/software integration. Capabilities to examine and alter registers and memory, set
breakpoints and perform single-line assembly and disassembly.
• Applications profiling and cache usage simulator. Profiling
feature determines time spent in various parts of the program
helping to identify program bottlenecks.
M/2000 Development System Configurations:
Model#
8302
8301
8304
8303
8305
8306
8307
8308
Description
M/2000-8 RISComputer
Development System includes:
• 25MHz CPU with Floating Point Accelerator
• 32MB main memory
• Two 715MB formatted disks
• 120MB cartridge tape
• 128KB of 1&0 cache
• Console port
• 13 slots for expansion
• Block mode Ethernet controller
• RISC/os with C compiler
Same as Model 8302, but without 1/2" tape drive.
Same as Model 8302, but with one 715MB disk
drive.
Same as Model 8304, but without 1/2" tape drive.
M/2000-6 RISComputer
Development System includes:
• 20MHz CPU with Floating Point Accelerator
• 32MB main memory
• One 715MB formatted 8" disk
• 120MB cartridge tape
• 128K of 1&0 caches
• Console port
• Ten VME bus slots
Three memory slots
• Block mode Ethernet controller
• RISC/os with C compiler
Same as Model 8305 but without 1/2"
mag tape drive.
Same as Model 8305 but with 16MB
main memory.
Same as Model 8306 but with
16MB main memory.
Note: Additional memory, disk peripherals, tape peripherals, and
interface options, such as Ethernet or serial I/O, are also available
from lOT.
59-74
Logic Devices
._--------------
LOGIC,PRODUCTS
INTRODUCTION
THE FBT LOGIC FAMILY
Integrated Device Technology offers leadership families of
MEMORY & BUS INTERFACE devices that take advantage of two
different IDT technology platforms.
The FCT (Fast CEMOS ™ TTL-compatible) logic family takes
advantage of IDT's leading edge CMOS technology. This technology utilizes sub 1 micron channel lengths and double layer metal
processing.
The FBT (Fast BiCEMOS ™ TTL-compatible) logic family is
manufactured using an advanced dual metal Bicmos technology
that combines sub 1 micron CMOS technology with high performance bipolar transistors.
This logic family is manufactured using an advanced
BiCEMOS, dual metal technology. This technology allows the
highest device speeds to be gained while minimizing sImultaneous switching noise and maintaining CMOS power levels. Key features of this family are:
• FBT series is 25% faster than FCTA speeds.
THE FCT LOGIC FAMILY
This logic family was designed to allow easy upgrade of older
bipolar 54/74F and AM29800 series designs to their performance
equivalents in CMOS. The FCT family comes in two versions; The
standard version (FCT) , and the low switching noise version
(FCTT). Each version has various speed grades. Key features of
this family are:
• FCT/FCTT is a direct replacement of FAST™ family products.
• FCTIFCTT is a direct replacement of AM29800 family products.
• FCTA series is up to 50% faster than FCT speeds.
• FCTAT series is equivalent to FCTA speed with improved
switching noise.
• FCTCTseries is 25% faster than FCTAlFCTATspeeds.
• FCTT series is equivalent to FCT speeds with low switching
noise.
• High output drive to 64mA (commercial) and 48mA (military).
• Substantially lower input current levels (5jJA maximum).
• Compliant with J EDEC Standard No.18 for 54/74FCTXXX logic.
• Excellent ESD and Latch-up immunity.
• Output drive to 64mA (Commercial) and 48mA (Military).
• CMOS power levels (5~W typical static).
• TTL compatible input and output levels.
• High output impedance in power-off state.
• JEDEC standard pinout for DIP, SOIC and LCC packages.
QUALITY
All IDT logic devices are manufactured and assembled on a
MIL-STD-883, Class B compliant line. Key features of the military
products include:
• Fully compliant to MIL-STD-883, Class B.
• Offer numerous devices to DESC drawings.
• Available in Radiation Tolerant and Enhanced versions.
• Packages include Hermetic DIP, LCC and CERPACK.
Commercial products are manufactured using the same production line and stringent quality requirements acquired from
building military products. All commercial products are available
in dual in-line as well as surface mount packages.
PRODUCT MATRIX
SWITCHING
NOISE
STANDARD
IMPROVED
FCTA
FCTAT
FBT/FCTCT
FCT
LOW
FCTT
ULTRA-HIGH
SPEED
I
HIGH
SPEED
SPEED GRADE
CEMOS and BiCEMOS are trademarks of Integrated Device Technology, Inc.
FAST is trademark of National Semiconductor.
I
FAST
TABLE OF CONTENTS
PAGE
CONTENTS
Logic Devices
IDT FBT Series
54/74FBT240
54/74FBT241
54/74FBT244
54/74FBT245
54/74 FBT373
54/74FBT374
54/74FBT540
54/7 4FBT541
54/74FBT821
54/74FBT823
54/74FBT827
54/74FBT841
54/74FBT843
IDT FCTXXXCT
54/74 FCT240CT
54/74FCT241 CT
54/74 FCT244CT
54/74FCT245CT
54/7 4 FCT373CT
54/7 4 FCT374CT
54/74FCT540CT
54/74FCT541 CT
54/74 FCT646CT
54/74FCT821CT
54/74 FCT823CT
54/74FCT827CT
54/74FCT841 CT
54/74 FCT843CT
54/74 FCT845CT
IDT FCTXXXT/AT
54/74 FCT240T/AT
54/74FCT241T/AT
54/74FCT244T/AT
54/74FCT245T/AT
54/74FCT373T/AT
54/74FCT374T/AT
54/7 4FCT540T/ AT
54/74FCT541T/AT
54/74FCT646T/AT
54/74FCT821T/AT
54/74FCT823T/AT
54/74FCT827T/AT
54/74 FCT841T/AT
54/74 FCT843T/AT
lOT 54/74FCT151T/AT
IDT 54/74FCT157T/AT
IDT 54/74FCT251T/AT
IDT 54/74FCT257T/AT
IDT 54/74FCT620T/AT
IDT 54/74FCT621T/AT
IDT 54/74FCT622T/AT
IDT 54/74FCT623T/AT
IDT 29FCT52A/B
IDT 29FCT53A/B
IDT 29FCT520A/B
IDT 29FCT521A/B
Ultra High-Speed BiCMOS Logic ..................................................
Inverting Octal Buffer/Line Driver ..............................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-inverting Octal Bidirectional Transceiver. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent Latch .....................................................
Non-Inverting Octal 0 Flip-Flop ........................................•......
Inverting Octal Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer ........... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-Bit Non-Inverting Register .................................................
10-Bit Inverting Register .....................................................
10-Bit Non-Inverting Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10-Bit Non-Inverting Latch ........... , ........................................
9-Bit Non-Inverting Latch ............ , . . •. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ultra High-Speed CMOS Logic ....................................................
Inverting Octal Buffer/Line Driver ..............................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-Inverting Octal Bidirectional Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
Octal Transparent Latch .........................................•...........
Non-Inverting Octal D Flip-Flop .....................•.........................
Inverting Octal Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transceiver/Register ...................................................
10-Bit Non-Inverting Register .................................................
10-Bit Inverting Register .....................................................
10-Bit Non-Inverting Buffer ............. .'.....................................
10-Bit Non-Inverting Latch. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-Bit Non-Inverting Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Interface Latches .......................................................
High-Speed CMOS Logic. . . . . .. . .. ... ..... ......... . .. . . .. . ....... . . . ... . . . . .....
Inverting Octal Buffer/Line Driver ..............................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-Inverting Octal Buffer/Line Driver ..........................................
Non-Inverting Octal Bidirectional Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent Latch .....................................................
Non-Inverting Octal D Flip-Flop ...............................................
Inverting Octal Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transceiver/Register ...................................................
10-Bit Non-Inverting Register .................................................
10-Bit Inverting Register .....................................................
-10-Bit Non-Inverting Buffer ...................................................
10-Bit Non-Inverting Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-Bit Non-Inverting Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Fast CMOS 8-lnput Multiplexer (14-209) ............................................
Fast CMOS Quad 2-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Fast CMOS 8-lnput Multiplexer (3-State) (14-209) ........ .. . . . . ... . . . .. . ... . . . . . . . . . ..
Fast CMOS Quad 2-lnput Multiplexer (14-209) .......................................
Fast CMOS Octal Bus Transceiver (3-State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Fast CMOS Octal Bus Transceiver (Open Collector) ...................................
Fast CMOS Octal Bus Transceiver (Open Collector) ...................................
Fast CMOS Octal Bus Transceiver (3-State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Register Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Inverting Octal Register Transceiver ................................................
Multilevel Pipeline Register .......................................................
Multilevel Pipeline Register ................ _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
S10-1
S10-82
S10-86
S10-86
S10-92
S10-105
S10-109
S10-122
S10-122
S10-152
S10-152
S10-158
S10-171
S10-171
S10-3
S10-82
S10-86
S10-86
S10-92
S10-105
S10-109
S10-122
S10-122
S10-140
S10-152
S10-152
S10-158
S10-171
S10-171
S10-171
S10-6
S10-82
S10-86
S10-86
S10-92
S10-105
S10-109
S10-122
S10-122
S10-140
S10-152
S10-152
S10-158
S10-171
S10-171
S10-9
S10-14
S10-19
S10-24
S10-29
S10-35
S10-35
S10-29
S10-40
S10-40
S10-45
S10-45
TABLE OF CONTENTS (CON'T.)
PAGE
CONTENTS
lOT 39C8XXX
lOT 49FCT601
lOT 49FCT618
lOT 49FCT661
IDT 49FCT804/A
IDT 49FCT818/A
IDT 54/74FCT138/A
lOT 54/7 4FCT139/A
lOT 54/74FCT161/A
lOT 54/74FCT163/A
IDT 54/74FCT182/A
lOT 54/74FCT191/A
lOT 54/74FCT193/A
IDT 54/74FCT240/A
IDT 54/74FCT241/A
IDT 54/74FCT244/A
IDT 54/74FCT245/A
IDT 54/74FCT273/A
IDT 54/74FCT299/A
IDT 54/74FCT373/A
IDT 54/74FCT374/A
IDT 54/74FCT377/A
IDT 54/74FCT399/A
lOT 54/74FCT521/A
lOT 54/74FCT533/A
lOT 54/74FCT534/A
IDT 54/74FCT540/A
IDT 54/74FCT541/A
IDT 54/74FCT543/A
lOT 54/74FCT573/A
lOT 54/74FCT574/A
IDT 54/74FCT640/A
IDT 54/74FCT645/A
IDT 54/74FCT646/A
IDT 54/74FCT648/A
IDT 54/74FCT651/A
IDT 54/74FCT652/A
IDT 54/74FCT821NB
IDT 54/74FCT822NB
IDT 54/74FCT823NB
IDT 54/74FCT824NB
IDT 54/74FCT825NB
IDT 54/74FCT826NB
IDT 54/74FCT827NB
IDT 54/74FCT828NB
IDT 54/74FCT833NB
IDT 54/74FCT834A/B
IDT 54/74FCT841NB
IDT 54/74FCT842NB
IDT 54/74FCT843NB
IDT 54/74FCT844A/B
IDT 54/74FCT845NB
IDT 54/74FCT846NB
IDT 54/74FCT853A/B
IDT 54/74FCT854NB
IDT 54/74FCT861NB
IDT 54/74FCT862NB
IDT 54/74FCT863NB
IDT39C8XXX Family ........................................................... .
16-Bit Bidirectional Latch ............................. '.......................... .
16-Bit Register with SPC T. . .••••...........•..••.....•...••.•..• '................•
16-Bit Synchronous Binary Counter .............................................. .
High-8peed Tri-Port Bus Multiplexer (14-209) ....................................... .
Octal Register with 8PC'M (14-154,14-209) ......................... , .............. .
1-of-8 Decoder ................................................................ .
Dual 1-of-4 Decoder ..................................................... '.' .... .
Synchronous Binary Counter w/Asynchronous Master Reset ........................ .
Synchronous Binary Counter w/Synchronous Reset ............................... .
Carry-Lookahead Generator ...................................................... .
Up/Down Binary Counter w/Preset and Ripple Clock ............................... .
Up/Down Binary Counter w/Separate Up/Down Clocks ............................. .
Inverting Octal Buffer/Line Driver .................................................. .
Non-Inverting Octal Buffer/Line Driver .............................................. .
Non-Inverting Octal Buffer/Line Driver .............................................. .
Non-Inverting Octal Bidirectional Transceiver ........................................ .
Octal D Flip-Flop w/Buffered Asynchronous Master Reset ............................. .
Universal 8hift Register w/Common Parallel I/O Pins ................................. .
Octal Transparent Latch ......................................................... .
Non-Inverting Octal D Flip-Flop ................................................... .
Octal D Flip-Flop w/Clock Enable ................................................. .
Quad Dual-Port Register ......................................................... .
8-Bit Comparator .............................................................. .
Octal Transparent Latch ................................... ; .................... .
Octal 0 Flip-Flop .............................................................. .
Inverting Octal Buffer ........................................................... .
Non-Inverting Octal Buffer ....................................................... .
Octal Latched Transceiver ....................................................... .
Octal Transparent Latch ........................................................ .
Octal 0 Register ............................................................... .
Inverting Octal Bidirectional Transceiver ............................................ .
Octal Bidirectional Transceiver ................................................... .
Non-Inverting Octal Register Transceiver ........................................... .
Inverting Octal Register Transceiver ............................................... .
Inverting Octal Register Transceiver ............................................... .
Non-Inverting Octal Register Transceiver ........................................... .
10-Bit Non-Inverting Register ..................................................... .
10-Bit Inverting Register ......................................................... .
9-Bit Non-Inverting Register ...................................................... .
9-Bit Inverting Register .......................................................... .
8-Bit Non-Inverting Register ...................................................... .
8-Bit Inverting Register .......................................................... .
10-Bit Non-Inverting Buffer ....................................................... .
10-Bit Inverting Buffer ........................................................... .
8-Bit Transceiver w/Parity ........................................................ .
8-Bit Transceiver w/Parity ......' .................................................. .
10-Bit Non-Inverting Latch ....................................................... .
10-Bit Inverting Latch ........................................................... .
9-Bit Non-Inverting Latch ........................................................ .
9-Bit Inverting Latch ............................................................ .
8-Bit Non-Inverting Latch ........................................................ .
8-Bit Inverting Latch ............................................................ .
8-Bit Transceiver w/Parity ........................................................ .
8-Bit Transceiver w/Parity ........................................................ .
10-Bit Non-Inverting Transceiver .................................................. .
10-Bit Inverting Transceiver ...................................................... .
9-Bit Non-Inverting Transceiver ................................................... .
10-11
10-12
10-13
10-29
810-51
810-59
810-73
10-48
10-52
10-52
810-77
10-62
10-67
810-82
810-86
810-86
810-92
810-96
810-100
810-105
810-109
810-113
810-117
10-113
10-117
10-121
810-122
810-122
810-126
10-135
10-139
810-132
810-136
810-140
810-140
810-146
810-146
810-152
810-152
810-152
810-152
810-152
810-152
810-158
810-158
810-163
810-163
810-171
810-171
810-171
810-171
810-171
810-171
810-163
810-163
810-178
810-178
810-178
([!J
TABLE OF CONTENTS (CON'T.)
CONTENTS
IDT 54j74FCT864NB
lOT 54AHCT138
lOT 54AHCT139
lOT 54AHCT161
lOT 54AHCT163
lOT 54AHCT182
lOT 54AHCT191
lOT 54AHCT193
lOT 54AHCT240
lOT 54AHCT244
lOT 54AHCT245
lOT 54AHCT273
lOT 54AHCT299
lOT 54AHCT373
lOT 54AHCT374
IDT 54AHCT377
lOT 54AHCT521
lOT 54AHCT533
lOT 54AHCT534
lOT 54AHCT573
lOT 54AHCT574
lOT 54AHCT640
lOT 54AHCT645
PAGE
9-Bit Inverting Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . ..
1-of-8 Decoder ................................................................
Dual 1~of-4 Decoder .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Binary Counter w/Asynchronous Master Reset. . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Binary Counter w/Synchronous Reset ................................
Carry-Lookahead Generator .;........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Up/Down Binary Counter w/Asynchronous Presetting ............................ '. ..
Up/Down Binary Counter w/Separate Up/Down Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Inverting Octal Buffer/Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Non-Inverting Octal Buffer/Line Driver ............................................
Octal Bidirectional Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal D Flip-Flop ...............................................................
Universal Shift Register .........................................................
Oct~TransparentLatch .........................................................
Non-Inverting Octal 0 Flip-Flop ..................................................
Octal D Flip-Flop w/Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-Bit Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Inverting Octal 0 Flip-Flop . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal Transparent Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Octal 0 Register .............................................. ;................
Inverting Octal Bidirectional Transceiver ..........................................
Non-Inverting Octal Bidirectional Transceiver ......................................
CMOS Testing Considerations ................................................... .'.
Common Test Circuits and Waveforms. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . ..
810-178
10-198
10-202
10-206
10-206
10-211
10-216
10-220
10-225
10-229
10-233
10-237
10-241
10-245
10-249
S10-184
10-257
10-261
10-265
10-269
10-273
10-281
10-285
S10-188
810-189
----_ ------------------------------------------------------------------------..
ULTRA HIGH-SPEED
SiCMOS LOGIC
Inresrated Device 1echnoIogy. Inc.
ADVANCE
INFORMATION
FBT SERIES
FEATURES:
DESCRIPTION:
• BiCEMOS ™ FBT series 25% faster than FCTA speeds
• Equivalent to FCTA output drive over full temperature and
voltage supply extremes
• tOl up to 64mA (Commercial) and 48mA (Military)
• CMOS power levels (1 mW typical static)
• TTL compatible input and output levels
• High output impedance in power-off state
• JEDEC standard pinout for DIP, SOIC and LCC packages
• Military Product Compliant to Mil-Std-883, Class B
The FBT series of BiCMOS devices are built using advanced
BiCEMOS, a dual metal BiCMOS technology. This technology is
designed to supply the highest device speeds while maintaining
CMOS power levels.
These devices meet true bipolar TTL output levels. A combination of reduced bipolar output swing and unique BiCMOS output
circuitry helps minimize simultaneous switching noise. The output
butters are designed to otter high output impedance in the poweroff state. This feature makes these devices· ideal for card edge
interface.
PRODUCTS TO BE OFFERED:
The following advanced information on our FBT series include
the Absolute Maximum Ratings and DC Electrical Characteristics.
For more detailed information on other specifications (Pin DescripIDT54/74FBT240 refer to
IDT54/74FBT241 refer to
IDT54/74FBT244 refer to
IDT54/74FBT245 refer to
IDT54/74FBT373 refer to
IDT54/74FBT374 refer to
IDT54/74FBT540 refer to
IDT54/74FBT541 refer to
IDT54/74FBT821 refer to
IDT54/74FBT823 refer to
IDT54/74FBT827 refer to
IDT54/74FBT841 refer to
IDT54/74FBT843 refer to
IDT54/74FCT240A specifications on
IDT54/74FCT241A specifications on
IDT54/74FCT244A specifications on
IDT54/74FCT245A specifications on
IDT54/74FCT373A specifications on
IDT54/74FCT374A specifications on
IDT54/74FCT540A specifications on
IDT54/74FCT541A specifications on
IDT54/74FCT821A specifications on
IDT54/74FCT823A specifications on
IDT54/74FCT827A specifications on
IDT54/74 FCT841 A specifications on
IDT54/74FCT843A specifications on
tion, Block Diagram, Truth Table, and Power Supply Characteristics), refer to data sheets in the 1989 Data Book Supplement.
Switching Characteristics are not available at this time.
page S10-82
page S10-86
page S10-86
page S10-92
page S10-105
page S10-109
page S10-122
page S10-122
page S10-152
page S10-152
page S10-158
page S10-171
page S10-171
BiCEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4063/-
1989 Integrated Device Technology, Inc.
510-1
---------_._._-----------------------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FBT SERIES ULTRA HIGH-SPEED BICMOS LOGIC
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
MILITARY
UNIT
-0.5 to +7.0
V
VTERM (3)
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
-0.5 to +5.5
-0.5 to +5.5
SYMBOL
V
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
Output Capacitance
VOUT= OV
S
12
pF
I/O Capacitance
VOUT= OV
S
12
pF,
C IN
Input CapaCitance
C OUT
ClIO
pF
NOTE:
1. This parameter is measured at characterization but not tested.
120
mA
DC Output Current
120
lOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vee terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to + 70°C; Vee = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
MIN.
TYP.(2)
MAX.
UNIT
'-"H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
'-"L
Input LOW Level
Guaranteed Logic Low Level
O.S
V
-10
Vo = 2.7V
-
Vo = .5V
-
-
SYMBOL
TEST CONDITIONS (1)
PARAMETER
IIH
Input HIGH Current
IlL
Input LOW Current
Vee = Max.
Except I/O Pins
VI = 2.7V
I/O Pins
Vee = Max.
Except I/O Pins
'Ii
1/0 Pins
= .5V
10ZH
High Impedance Output Current
10ZL
Vec = Max.
10
~A
60
~A
-60
50
-SO
~A
II
Input HIGH Current
Vee = Max. VI = 5.5V
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vee = MaxP), Vo = GND
-60
-150
-225
mA
10H = -6mA MIL.
10H = -SmA COM'L.
2.4
3.3
-
V
Output HIGH Voltage
Vee = Min.
VIN = '-"H or'-"L
10H = -12mA MIL.
10H = -15mA COM'L.
2.0
3.0
-
V
Output LOW Voltage
For Non-800
Series Devices
10L = 48mA MIL.
10L = 64mA COM'L.
-
0.3
0.55
V
10H= -15mA
2.4
3.3
V
Vee = Min.
VIN = '-"H or'-"L
10H= -24mA
2.0
3.0
-
10L = 32mA MIL.
10L = 4SmA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
100
~A
-
0.2
1.5
mA
VOH
VOL
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
For SOO Series Devices
VH
Input Hysteresis
Vce = 5V
10FF
Bus Leakage Current
Vee = OV Vo = 4.5V
Icc
Quiescent Power Supply Current
Vce = Max.
VIN = GND or Vce
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
S10-2
100
~A
V
Integrated Device1echnology.lnc.
HIGH-SPEED
CMOS LOGIC
ADVANCE
INFORMATION
FCTXXXCT
TTL OUTPUT ONLY SERIES
FEATURES:
DESCRIPTION:
• FCTXXXCT series 25% faster than FCTAT speeds
• CMOS devices with TRUE TTL input and output compatibility
- VOH = 3.3V (typ.)
- VOL = 0.3V (typ.)
The FCTXXXCT is a high-speed CMOS logic family designed
with true TTL level input and output voltages. The reduced voltage
swing (3.4 Volts rail to rail) results in lower AC switching noise.
Effectively, the FCTXXXCT products combine the high-speed, low
power advantages of CMOS logic products. FCTXXXCT is 25%
faster than FCTA and FCTXXXAT.
The FCTXXXCT series of CMOS devices are built using advanced CEMOS ThO, a dual metal CMOS technology. This technology is designed to supply the highest device speeds while maintaining CMOS power levels.
•
•
•
•
•
10L up to 64mA (Commercial) and 48mA (Military)
CMOS power levels (1 mW typical static)
JEDEC standard pinout for DIP, SOIC and LCC packages
Military Product Compliant to MIL-STD-883, Class B
Available in Rad Hard and Rad Tolerant Versions
Information on our FCTXXXCT series includes the Absolute
Maximum Ratings and DC Electrical Characteristics. For more detailed information on specifications (Pin Description, Block Diagram, Truth Table and Power Supply Characteristics), refer to the
appropriate data sheets in the 1989 Data Book Supplement.
Switching Characteristics are not available at this time.
Products to be offered:
IDT54/74FCT240CT refer to
IDT54/74FCT241CT refer to
IDT54/74FCT244CT refer to
IDT54/74FCT245CT refer to
IDT54/74FCT373CT refer to
IDT54/74FCT374CT refer to
IDT54/74FCT540CT refer to
IDT54/74FCT541CT refer to
IDT54/74FCT646CT refer to
IDT54/74FCT821CT refer to
IDT54/74FCT823CT refer to
IDT54/74FCT827CT refer to
IDT54/74FCT841CT refer to
IDT54/74FCT843CT refer to
IDT54/74FCT845CT refer to
IDT54/74FCT240/A page S10-82
IDT54/74FCT241/A page S10-86
IDT54/74FCT244/A page S10-86
IDT54/74FCT245/A page S10-92
IDT54/74FCT373/A page S10-105
IDT54/74FCT374/A page S10-109
IDT54/74FCT540/A page S10-122
IDT54/74FCT541/A page S10-122
IDT54/74FCT646/A page S10-140
IDT54/74FCT821/A page S10-152
IDT54/74FCT823/A page S10-152
IDT54/7 4FCT827/ A page S 10-158
IDT54/74FCT841/A page S10-171
IDT54/74FCT843/A page S10-171
IDT54/74FCT845/A page S10-171
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
OSC-4064/-
S10-3
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTFCTXXXCT HIGH-SPEED CMOS LOGIC
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
(2)
VTERM
(3)
RATING
Terminal Voltage
with Respect to
GND
Terminal Voltage
with Respect to
GND
-0.5 to + 7.0
-0.5 to Vcc
CAPACITANCE(TA =+25"C
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
V
-0.5 to Vcc
V
-55 to + 125
°C
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
o to
+70
f = 10MHz)
PARAMETER (1)
CONDITIONS
TYP.
MAX.
C IN
Input CapaCitance
6
10
pF
C OUT
Output CapaCitance
8
12
pF
CliO
I/O CapaCitance
= OV
VOUT = OV
VOUT = OV
8
12
pF
SYMBOL
VIN
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vcc terminals only.
3. Outputs and I/O terminals only.
S10-4
UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTFCTXXXCT HIGH-SPEED CMOS LOGIC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA =O°C to + 70°C; Vcc =5.0V±5%.
Military: TA' = -55°C to + 125°C; Vcc' == 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V·
VIL
Input LOW Level
Guaranteed Logic Low Level
-
-
O.S
V
-
5
-
15
1/0 Pins
-
Vo
-
-
10
-
-
-10
Except 1/0 Pins
. Vee = Max.
IIH
. Input HIGH Current
IlL
Input LOW Current
VI = 2.7V :
.
lozH
1/0 Pins
Except 1/0 Pins
Vcc = Max.
. VI = .5V
High Impedance Output Current
Vcc = Max.
=;'
2.7V
Vo = .5V
IOZL
-
-5
-
-15
~A
)JA
)JA
II
Input HIGH Current
Vcc = Max. VI =VcdMax.)
-
-
100
ViK
Clamp Diode Voltage
Vcc = Min., IN = -1SmA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = Max,(3l. Vo = GND
-60
-
-225
mA
IOH = -6mA MIL.
IOH = -SmA COM'L.
3.3
Output HIGH Voltage
Vcc = Min.
VIN = ViH or ViL
2.4
-
V
VOH
IOH = -12mA MIL.
IOL = -15mA COM'L.
2.0
3.0
-
V
IOL = 4SmA MIL.
IOL = 64mA COM'L.
-
0.3
0.55
V
IOL = 32mA MIL.
IOL = 4SmA COM'L.
-
0.3
0.5
V
VOL
Output LOW Voltage
Vce = Min.
VIN = ViH or ViL
)JA
Line Drivers
VOL
Vce = Min.
V1N = ViH or ViL
Output LOW Voltage
Standard, 3-State,
and SOO Series
VH
Input Hysteresis
Vce = 5V
-
200
-
mV
Icc
Quiescent Power Supply Current
Vcc = Max., ~ ~ GND or 'Ce
-
0.2
1.5
mAo
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit testshould riot exceed one second.
4. This parameter is guaranteed but not tested.
S10-5
------_._---_...._-_._-_ .... _ - - -
__._----_._-----------
.
Intesrated Device1echnoIogy.Inc.
HIGH-SPEED
CMOS LOGIC
ADVANCE
INFORMATION
FCTXXXT/AT
TTL OUTPUT ONLY SERIES
FEATURES:
• FCTXXXT series equivalent to FCT and FAST™ speeds and
drive
DESCRIPTION:
• FCTXXXATseries equivalent to FCTA speeds and drive
• CMOS devices with TRUE TTL input and output compatibility
The FCTXXXT and FCTXXXAT are high-speed CMOS logic
products designed with true TTL level input and output voltages.
The reduced voltage swing (3.4 Volts rail to rail) results in lower AC
switching noise. Effectively, the FCTXXXT and FCTXXXAT
products combine the high-speed, low power advantages of
CMOS logic products with the lower AC switching noise of tradi-.
tional Bipolar logic families.
The FCTXXXT and FCTXXXAT series of CMOS devices are built
using advanced CEMOS TM, a dual metal CMOS technology. This
technology is designed to supply the highest device speeds while
maintaining CMOS power levels.
- VOH
= 3.3V (typ.)
- VOL = 0.3" (typ.)
• 10L up to 64mA (Commercial) and 48mA (Military)
• CMOS power levels (1 mW typical static)
• JEDEC standard pinout for DIP, SOIC and LCC packages
• Military Product Compliant to MIL-STD-883, Class B
• Available in Rad Hard and Rad Tolerant Versions
Information on our FCTXXXT and FCTXXXAT series include the
Absolute Maximum Ratings and DC Electrical Characteristics. For
more detailed information on specifications (Pin Description,
Block Diagram, Truth Table and Power Supply and Switching
Characteristics), refer to the appropriate data sheets in the 1989
Data Book Supplement.
Products to be offered:
IDT54/74FCT240T/AT refer to
IDT54/74FCT241T/AT refer to
IDT54/74FCT244T/AT refer to
IDT54/74FCT245T/AT refer to
IDT54/74FCT373T/AT refer to
IDT54/74FCT374T/AT refer to
IDT54/74FCT540T/AT refer to
IDT54/74FCT541T/AT refer to
IDT54/74FCT646T/AT refer to
IDT54/74FCT821T/AT refer to
IDT54/74FCT823T/AT refer to
IDT54/74FCT827T/AT refer to
IDT54/74FCT841T/AT refer to
IDT54/74FCT843T/AT refer to
IDT54/74FCT240/A page S10-82
IDT54/74FCT241/A page S10-86
IDT54/74FCT244/A page S10-86
IDT54/74FCT245/A page S10-92
IDT54/74FCT373/A page S10-105
IDT54/74FCT374/A page S10-109
IDT54/74FCT540/A page S10-122
IDT54/74FCT541/A page S10-122
IDT54/74FCT646/A page S10-140
IDT54/74FCT821/A page S10-152
IDT54/74FCT823/A page S10-152
IDT54/74FCT827/A page S10-158
IDT54/74FCT841/A pageS10-171
IDT54/74FCT843/A page S10-171
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc
JANUARY 1989
DSC-4067/-
510-6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTFCTXXXT/AT HIGH-SPEED CMOS LOGIC
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
(2)
VTERM
(3)
RATING
Terminal Voltage
with Respect to
GND
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to Vee
CAPACITANCE (TA= +25"C, f
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
V
-0.5 to Vee
V
-55 to +125
°C
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
o to
+70
= 1.0MHz)
PARAMETER (1)
CONDITIONS
TYP.
MAX.
C IN
Input Capacitance
VIN = OV
6
10
pF
C OUT
Output Capacitance . VOUT = OV
8
12
pF
CliO
I/O Capacitance
VOUT = OV
8
12
pF
SYMBOL
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other.
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vee terminals only.
3. Outputs and I/O terminals only.
S10-7
UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTFCTXXXT/AT HIGH-SPEED CMOS LOGIC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to + 70°C; Vee = S.OV±5%
Military·TA = -55°C to +125°C·Vee = 50V+10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
\'IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
\'IL
Input LOW Level
Guaranteed Logic Low Level
-
-
O.B
V
IIH
Input HIGH Current
IlL
Input LOW Current
10zH
High Impedance Output Current
Vee = Max.
Except I/O Pins
-
-
5
VI = 2.7V
I/O Pins
-
-
15
Vee = Max.
Except I/O Pins
-
-
-5
VI = .5V
I/O Pins
-
-
-15
Vo = 2.7V
-
-
10
Vo = .5V
-
-
-10
-
-
100
Vee = Max.
10ZL
II
Input HIGH Current
Vee = Max. VI = Vee (Max.)
J.lA
J.lA
J.lA
J.lA
Clamp Diode Voltage
Vce = Min .• IN = -1BmA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = Max.(3), Vo = GND
-60
-
-225
mA
10H = -6mA MIL.
10H = -BmA COM'L.
3.3
Output HIGH Voltage
Vee = Min.
V IN = VIH or "'L
2.4
VOH
-
V
10H = -12mA MIL.
10L = -15mA COM'L.
2.0
3.0
-
V
10L = 4BmA MIL.
10L = 64mA COM'L.
-
0.3
0.55
V
10L = 32mA MIL.
10L = 4BmA COM'L.
-
0.3
0.5
V
-
200
-
mV
-
0.2
1.5
mA
"'K
VOL
Output LOW Voltage
Vcc = Min.
VIN = "'H or"'L
Line Drivers
VOL
Output LOW Voltage
Vec = Min.
VIN = "'H or "'L
Standard,3-State,
and BOO Series
VH
Input Hysteresis
Vcc = 5V
Icc
Quiescent Power Supply Current
Vcc = Max.,
\oN ;;::: GND or '(:;C
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-8
~
FAST CMOS
a-INPUT MULTIPLEXER
Intesrated Device'i!chnology.Jnc.
ADVANCE
INFORMATION
lOT 54/74FCT151T
lOT 54/74FCT151AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT151T equivalent to FAST™ speed
• IDT54/74FCT151AT 25% faster than FAST™ speed
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
•
10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT151T is an 8-input multiplexer built using advanced CEMOS TM, a dual metal CMOS technology. The FCT151T
has the ability to select one line of data from up to eight sources. It
can be used as a function generator to generate any logic function
of four variables. Both assertion and negation outputs are provided.
FUNCTIONAL BLOCK DIAGRAM
~
..I.
)-
~-
Is
I
....- W
I
~J
13
I
~
~
z
-:;:;Y
r
§JI
§-J0--
~-
f'
~
~
I--
)
~
~
t
So
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4019/-
1989 Integrated Device Technology. Inc.
510-9
---_._---------------_.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT151T/AT FAST CMOS 8-INPUT MULTIPLEXER
PIN CONFIGURATIONS
u u;; u u
3
11
]
4
10
]
5
:J
Z :J
20 19
1
L20-2
NC ] 6
Z
U
2
7
8
9
10 11
lSC
Is
17 [:
16
leC
lSC
17
14 [:
So
NC
12 13
nnnnn
lJJ zzCJ)CJ)
0 0
'" -
DIP/SOIC/CERPACK
TOP VIEW
(!J
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
TRUTH TABLE
DESCRIPTION
INPUTS
OUTPUTS
11 - 17
Data Inputs
S2
S1
SO
E
Z
Z
So - S2
Select Inputs
X
X
X
H
L
H
E"
Enable Input (Active LOW)
L
L
L
L
10
To
Z
Data Output
L
L
H
L
11
Tl
Z
Inverted Data Output
L
H
L
L
12
T2
L
H
H
L
13
T3
H
L
L
L
14
T4
H
L
H
L
Is
Ts
H
H
L
L
Ie
16
H
H
H
L
17
h
H = High Voltage Level
L = Low Voltage Level
X = Don't care
S10-10
--_._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .•
IDT54/74FCT151T/AT FAST CMOS 8-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to + 7.0
Terminal Voltage
V
(3) with Respect to
TERM
GND
-0.5 to Vcc
MILITARY
UNIT
-0.5 to +7.0
-0.5 to Vee
V
-55 to +125
°C
Operating
Temperature
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to + 150
°C
PT
Power Dissipation
0.5
0.5
W
+70
CIN
V
TA
o to
SYMBOL
(TA= +25°C f = 10MHz)
PARAMETER(l)
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
VOUT = OV
COUT
Output Capacitance
S
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
120
DC Output Current
120
mA
lOUT
NOTES:
1.. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vee terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to + 70°C; \Ce = 5.0V±5%
Military: TA = -55°C to +125°C; Vee = 50V+10%
MIN.
TYP.(2)
MAX.
'-"H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
Vil
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
IIH
Input HIGH Current
III
Input LOW Current
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee = MaxJ3),
SYMBOL
TEST CONDITIONS (1)
PARAMETER
Vec = Max.
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
\6
VI = \Ce
-
-
5
VI = 2.7V
-
-
5(4)
VI = O.4V
-
-
_5(4)
VI = GND
-
-
-5
-
-0.7
-1.2
V
-60
-
-225
mA
= GND
Vec = Min.
VIN = \'IH or'vk
Vcc = Min.
\'IN = \'IH or\'ll
UNIT
10H = -6mA MIL.
2.4
3.3
-
10H = -SmA COM'L.
2.4
3.3
-
10H = -12mA MIL.
2.0
3.0
-
10H = -15mA COM'L.
2.0
3.0
-
10l = 32mA MIL.
-
0.3
0.5
10l = 4SmA COM'L.
-
0.3
0.5
jJA
V
V
VH
Input Hysteresis
Vcc = 5V
-
200
-
mV
Icc
Quiescent Power
Supply Current
Vcc = Max.
\'IN = GND or\Cc
-
.2
1.5
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Ei,ectrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, + 25 ° C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-11
IDT54/74FCT151T/AT FAST CMOS 8-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
Icc
Quiescent Power Supply Current
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Currenr 4 )
Vcc= Max.
Outputs Open
'O'E A = OE'B = GND
One Bit Toggling
50% Duty Cycle
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
~ = GND
One Bit Toggling
ICCD
10
TYP,<2)
MAX.
-
.2
1.5
mA
-
0.5
2.0
mA
'-"N ~ VHC
'-"N ~ VLC
-
0.15
0.25
'-"N ~ VHC
'-"N ~ VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.0
5.0
TEST CONDITIONS(1)
Vcc = Max.
VIN ~ VHC ; VIN :S VLC
fl =0
MIN.
UNIT
mAl
MHz
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~I cc = Power Supply Current for a TTL High Input ~N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
IDT54/74FCT151T/AT FAST CMOS 8-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT151T
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
~toZ
tpLH
t pHL
Propagation Delay
~toZ
tpLH
tpHL
Propagation Delay
Eto Z
tpLH
tpHL
CONDITION(1)
TYp~3)
COM'L.
IDT54/74FCT151AT
COM'L.
MIL.
MIN.(2) MAX.
TYP!3)
MIN~2)
MAX.
MIL.
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
5.0
1.5
9.0
1.5
10
-
-
-
-
-
ns
7.7
1.5
10.5
1.5
11.5
-
-
-
-
-
ns
4.8
1.5
7.0
1.5
7.5
-
-
-
-
-
ns
Propagation Delay
Eto Z
5.4
1.5
9.5
1.5
11
-
-
-
-
-
ns
tpLH
t pHL
Propagation Delay
IN to Z
2.9
1.5
6.5
1.5
7.5
-
-
-
-
-
ns
tpLH
tpHL
Propagation Delay
IN toZ
5.2
1.5
7.5
1.5
9
-
-
-
-
-
ns
C L = 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXXT
Device Type
X
X
Package
Process/
Temperature
RMy:''"'
P
D
~-------------------; SO
L
E
L-________________________~I
I
~
________________________________
~I
151
151A
54
I 74
S10-13
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
8-lnput Multiplexer
Fast 8-lnput Multiplexer
-55°C to + 125°C
O°C to +70°C
FAST CMOS QUAD
2-INPUT MULTIPLEXER
Integrated Device"JechnoIogy.1nc.
PRELIMINARY
lOT 54/74FCT157T
lOT 54/74FCT157AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT157T equivalent to FAST™ speed
• IDT54174FCT157AT 25% faster than FAST™ speed
• Equivalent to FAST™ output drive over full temperature and
voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST ™ (5jJA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54174FCT157T/AT is a quad 2-input multiplexer built
using advanced CEMOS TM, a dual metal CMOS technology. Four
bits of data can be selected using the common Select and Enable
inputs. The four buffered outputs present the selected data in the
true (non-inverting) form. The 157 can also be used to generate any
four of the 16 different functions to two different variables.
FUNCTIONAL BLOCK DIAGRAM
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC-4060/-
S10-14
IDT54/74FCT157T/AT FAST CMOS
QUAD 2-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
u
<{
u
...s'cn z ~llJ
INDEX
..............
Vee
3
E
I
2 U
I
20 19
loe
11A
]4
18 [:
lo~
he
ZA
]5
17[
l1e
Ze
NC
10D
lOB
]7
110
119
:J
:J
6
L20-2
6
~ ~
ZD
ti
16[
NC
15 [:
Zc
14C
10D
~ti
alO cj 0
N Z Z N
0
Cl
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
TRUTH TABLE
DESCRIPTION
lOA - 10D
Source 0 Data Inputs
INPUT
OUTPUT
11A -110
Source 1 Data Inputs
E
S
10
II
E
Enable Input (Active LOW)
H
X
X
X
L
S
Select Input
L
H
X
L
L
ZA - ZD
Outputs
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
H = High voltage level
L = Low voltage level
X = Don't care
S10-15
Z
IDT54/74FCT157T/AT FAST CMOS
QUAD 2·INPUT MULTIPLEXER. .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
(2)
TERM
RATING
Terminal Voltage
with Respect to
GND
(3)
V
TERM
Terminal Voltage
with Respect to
GND
TA
-0.5.to + 7.0
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-:0.5 to +7.0
UNIT
SYMBOL
C IN
V
-0.5 to Vec
-0.5 to Vee
V
Operating
Temperature
o t6+70
-55 to + 125
°C
TalAs
Temperature.
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
PT
Power Dissipation
0.5
0.5
W
(TA= +25°C, f ,,;, 1.0MHz)
PARAMETER(l)
Input Capacitance
CONDITIONS TYP.
V1N = OV
MAX. UNIT
6
10
pF
COUT
VOUT= OV
8
Output Capacitance
12
pF
NOTE.
1. This parameter is measured at charCieterization but not tested.
mA
DC Output Current
120
120
lOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vee terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee - 0.2V
Commercial: TA = O°C to + 70°C; \fc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
~H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
~L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
5
Input HIGH Current
VI = \be
-
IIH
VI = 2.7V
-
-
5(4)
-
_5(4)
-5
Vee = Max.
VI = 0.5V
)JA
IlL
Input LOW Current
-
-
\lK
Clamp Diode Voltage
\be = Min., IN = -18mA
-
-0.7
-
V
los
Short Circuit Current
Vce = Max~3), Vo = GND
-60
-120
-
mA
10H = -6mA MIL.
2.4
3.3
-
Output HIGH Voltage
Vee = Min.
\IN = \lH or \lL
IOH = -8mA COM'L.
2.4
3.3
-
VOH
VOL
Output LOW Voltage
VH
Input Hysteresis
Icc
Quiescent Power
Supply Current
VI = GND
10H = -12mA MIL.
2.0
3.0
-
IOH = -15mA COM'L.
2.0
3.0
-
-
0.3
0.5
IOL = 48mA COM'L.
0.3
0.5
-
-
200
-
mV
-
0.2
1.5
mA
IOL = 32mA MIL.
Vee = Min.
VIN = VIHorV1L
Vee = Max.
\IN = GND or Vee
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-16
V
IDT54/74FCT157T/AT FAST CMOS
QUAD 2-INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
. Vee =
VIN ~
fl =
Max.
VHC ; V IN :5' VLC
0
Icc
Quiescent Power Supply Current
.6.lcc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
Vcc=: Max.
Outputs Open
~ = GND
One Bit Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
~ = GND
One Bit Toggling
Ic
TYP.(2)
MAX.
-
.2
1.5
mA
-
0.5
2.0
mA
'viN ~ VHC
'viN ~ VLC
-
0.15
0.25
'viN ~ VHC
'viN ~ VLC
(FCn
-
1.7
4.0
V IN = 3.4V
'viN = GND
-
2.0
5.0
TEST CONDITIONS (1)
PARAMETER
MIN.
:
UNIT
mAl
MHz
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
~ = GND
Four Bits Toggling
'viN ~ VHC (6)
VIN 2: VLC
(FCn
V IN = 3.4V(6)
VIN = GND
-
1.7
4.0(5)
-
2.7
8.0 (5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at Dti
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-17
---.- ----_._._-------_....__... _-_._--
._----
IDT54/74FCT157T/AT. FAST CMOS
QUAD 2·INPUT MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT157T
SYMBOL
t pLH
t pHL
PARAMETER
CON DITION (1)
·TYP!3)
Propagation Delay
IntoZn
tpLH
t pHL
Propagation Delay
EtoZn
tpLH
tpHL
Propagation Delay
Sto Zn
CL = 50pF
RL = soon
COM'L.
MIN.(2) MAX.
IDT54/74FCT157AT
MIL
MIN~2)
COM'L·.·
TYP!3)
MAX.
MIN.(2)
MAX.
MIL
MIN.(2)
4.5
1.5
6.0
1.5
7.5
-
-
-
-
-
ns
7.0
1.5
10.5
1.5
12.0
-
-
-
-
-
ns
7.5
1.5
11.0
1.5
12.0
-.
-
-
-
-
ns
NOTES:
1. See test circuit and waveforms
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXXT
Device Type
UNIT
MAX.
X
x
Package
Process/
Temperature
Range
Y:,ank
'------------i
'-----------------i
MIL-STD-883, Class B
P
D·
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPAK
157
151A
Quad 2-lnput Multiplexer
Fast Quad 2-lnput Multiplexer
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 54
74
S10-18
Commercial
-55°C to + 125°C
O°C to + 70°C
Intesrated Device1echnoIogy.Inc.
FAST CMOS 8-INPUT
MULTIPLEXER
(3-STATE)
PRELIMINARY
lOT 54/74FCT251T
lOT 54/7 4FCT251 AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT251T equivalent to FAST™ speed
• IDT54/74FCT251AT 25% faster than FAST"" speed.
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
The IDT54/74FCT251T is an 8-input multiplexer with 3-state
outputs built using advanced CEMOS TM, a dual metal CMOS
technology. The 251 has the ability to select one line of data from
up to eight sources. It can be used as a universal function
generator to generate any logic function of four variables. 80th
assertion and negation outputs are provided.
•
•
•
•
•
•
•
48mA (commercial) and 32mA (military)
CMOS power levels (5~W typo static)
TTL input and output level compatible
Substantially lower input current levels than FAST ™ (5~A max.)
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Enhanced versions
Military product compliant to MIL-STD-883, Class 8
10L =
FUNCTIONAL BLOCK DIAGRAM
...!.
...!.
)--
)-
§h---
15
k---i--.
----=::.....
I
...!.
:rJ
~
~z
'-~
I
~
...!.
10
>--
)-
>--
~
So
OE
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4062/-
1989 Integrated Device Technology. Inc.
510-19
IDT54/74FCT251T/AT FAST CMOS
a-INPUT MULTIPLEXER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
~-..,~
INDEX
~-='
ULJIIUW
3 2 U 20 19
11
]4
18 [:
Is
10
]s
17[
16
NC
]6
16 [:
NC
L20-2
Z
:J
7
lS [:
17
Z
] 8
14 [:
So
~~ti~~
0 u
~ C)z z
DIP/SOIC/CERPACK
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
men
LCC
TOP VIEW
TRUTH TABLE
INPUTS
DESCRIPTION
OUTPUT
So - S2
Select Inputs
S2
S1
So
~
Z
Z
DE"
3-State Output Enable Input
(Active LOW) ,
X
X
X
H
Z
Z
L
L
L
L
10
To
L
L
H
L
11
T1
10 -17
Multiplexer Inputs
Z
3-State Multiplexer Output
L
Complementary 3-State Multiplexer
Output
H
L
X
Z
S10-20
=
=
=
=
L
H
L
L
12
T2
L
H
H
L
13
T3
H
L
L
L
14
T4
H
L
H
L
Is
Ts
H
H
L
L
16
T6
H
H
H
L
17
h
High voltage level
Low voltage level
Don't care
High-impedance (OFF) state
IDT54/74FCT251T/AT FAST CMOS
8-INPUT MULTIPLEXER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
(2)
TERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
Terminal Voltage
V
(3)
TERM
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
-0.5 to Vce
-0.5 to Vcc
V
Oto +70
-55 to + 125
°C
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to + 125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
PT
Power Dissipation
0.5
0.5
W
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS TYP.
CIN
Input Capacitance
COUT
Output Capacitance
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
S
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
DC Output Current
120
120
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vce terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to + 70°C; "cc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vec = 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
'v'IL
Input LOW Level
Guaranteed Logic Low Level
IIH
Vee = Max.
IlL
Input LOW' Current
-
MAX.
UNIT
-
V
O.S
V
VI = 2.7V
-
VI =.0.5V
-
VI = GND
-
Vo = Vee
-
Vo = 2.7V
-
-10
-0.7
-1.2
V
mA
VI =Vce
Input HIGH Current
TYP.(2)
5
5(4)
-5(4)
~A
-5
10
Off State (High Impedance)
Output Current
Vee = Max.
VIK
Clamp Diode Voltage
Vee=Min., IN = -1SmA
-
los
Short Circuit Current
Vee = Max,!3), Vo = GND
-60
-
-225
10H = -6mA MIL.
2.4
3.3
-
10H = -SmA COM'L.
2.4
3.3
-
10H = -12mA MIL.
2.0
3.0
10L = -15mA COM'L.
2.0
3.0
-
10L = 32mA MIL.
-
0.3
0.5
0.3
0.5
-
200
-
mV
-
0.2
1.5
mA
loz
Vo= 0.5V
Vo= GND
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
VH
Input Hysteresis
Icc
Quiescent Power
Supply Current
Vee = Min.
VIN = '-"H or'-"L
Vee = Min.
VIN = '-"H or'-"L
10L = 48mA COM'L.
Vee = Max.
VIN = GND or Vee
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-21
10
-10
~A
V
IDT54/74FCT251T/AT FAST CMOS
8-INPUT MULTIPLEXER (3~STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLe = 0.2V; VHe = Vee - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
lee
Quiescent Power Supply Current
Vee = Max.
VIN ~ VHe ; VIN ::5 VLC
fl = 0
..6.lec
Quiescent Power Supply Current
TTL Inputs HIGH
Vce = Max.
VIN = 3.4V(3)
Dyn~mic Power Supply Current (4)
Vcc= Max.
Outputs Open
ot = GND
One Bit Toggling
50% Duty Cycle
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
f1 = 10MHz
50% Duty Cycle
OE' = GND
One Bit Toggling
ICCD
Ic
MIN.
TYP.(2)
MAX.
-
0.2
1.5
mA
-
0.5
2.0
mA
VIN ~ VHC
"'N ~ VLC
-
0.15
0.25
mAl
MHz
"'N ~ VHC
"'N ~ VLC
(FCT)
-
1.7
4.0
rnA
V IN = 3.4V
"'N = GND
-
2.0
5.0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ..6.lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.
..6.lee = Power Supply Current for a TTL High Input <'-"N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-22
UNIT
IDT54/74FCT251T/AT FAST CMOS
8-INPUT MULTIPLEXER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT251T
SYMBOL
CONDITION(1)
PARAMETER
TYp~3)
COM'L
MIN.(2) MAX.
IDT54/74FCT251AT
MIL.
COM'L
TYP!3)
MIN~2)
MAX.
MIL
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
SN toZ
5.9
1.5
9.0
1.5
9.5
-
-
-
-
-
ns
t pLH
t pHL
Propagation Delay
Sr-.J toZ
9.5
1.5
11.0
1.5
14
-
-
-
-
-
ns
tpHL
tpLH
Propagation Delay
IN to Z
4.0
1.5
7.0
1.5
8.0
-
-
-
-
-
ns
tpLH
tPHL
Propagation Delay
IN to Z
7.0
1.5
7.0
1.5
8.0
-
-
-
-
-
ns
tPZH
tPZL
Output Enable Time
ot:to Z
6.4
1.5
9.0
1.5
10.0
-
-
-
-
-
ns
tPHZ
tpLZ
Output Disable Time
C5E" to Z
5.0
1.5
7.5
1.5
8.5
-
-
-
-
-
ns
tPZH
tPZL
Output Enable Time
C5E" to Z
6.7
1.5
9.0
1.5
10.0
-
-
-
-
-
ns
tpHZ
tpLZ
Output Disable Time
01: to Z
4.5
1.5
7.0
1.5
7.0
-
-
-
-
-
ns
CL = 50pF
RL = 500n
NOTES:
1. See test circuit and waveforms
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = '5.0V. + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDT
IDTXXFCT
Temp. Range
XXXXT
Device Type
X
X
Package
Process/
Temperature
Range
Y:'Mk
P
D
' - - - - - - - - - - - - - / SO
L
E
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-/ 251
251A
"---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - 1 5 4
74
S10-23
Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPAK
8-lnput Multiplexer
Fast 8-lnput Multiplexer
-55°C to +125°C
O°C to + 70°C
Integrated OeviceK:mnoIogy. Inc.
FAST CMOS QUAD'
2-INPUTMULTIPLEXER
(3-STATE)
PRELIMINARY
lOT 54/74FCT257T
lOT 54/74FCT257AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT257T equivalent to FAST™ speed
The IDT54/74FCT257T/AT is a quad 2-input multiplexer built
using advanced CEMOS TM, a dual metal CMOS technology. Four
bits of data can be selected using the Common Data Select inputs.
The four outputs present the selected data in the true (non-inverting) form. The outputs may be switched to a high impedance state
with HIGH on Output Enable (OE) input, allowing for direct interface with bus-oriented systems.
'
• IDT54/74FCT257AT25% Faster than FAST™
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, .class B
FUNCTIONAL BLOCK DIAGRAM
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1969 Integrated Device Technology. Inc.
JANUARY 1989
DSC-4059/-
S10-24
------.---------------------------------------------------------------------------------------IDT54/74FCT257T/AT FAST CMOS
QUAD 2-INPUT MULTIPLEXER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
U
c(
INDEX
.2cnz
~
lac
11A
]4
18 [
lac
11e
ZA
:] 5
17[
NC
:]6
l1e
Ze
100
lOB
]7
110
11B
:] 8
L20-2
NC
15[
Ze
14[
100
9 10 11 12 13
.no U
N
Z
CJ
DIP/SOIC/CERPACK
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
16[
nnnnn
Zo
PIN NAMES
~~
U LJ ;; U L.l
3 2 U 20 19
Vee
Z
o
0
N'::
LCC
TOP VIEW
TRUTH TABLE
DESCRIPTION
INPUTS
OUTPUT
OE
S
10
11
ZN
3-State Output Enable Input (Active LOW)
H
X
X
X
Z
lOA - 100
Source 0 Data Inputs
L
H
X
L
L
11A- 11O
Source 1 Data Inputs
L
H
X
H
H
ZA-ZO
3-State Multiplexer Outputs
L
L
L
X
L
L
L
H
X
H
S
Common Data Select Input
OE'
H
L
X
Z
S10-25
= High voltage level
= Low voltage level
= Don't care
= High-impedance (OFF) state
IDT54/74FCT257T/AT FAST CMOS
aUAD 2-INPUT MULTIPLEXER (3-STATE)
ABSOLUTE MAXIMUM RATINGS
RATING
Terminal Voltage
V
(2) with Respect to
TERM
GND
SYMBOL
VTERM
(3)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
(1)
MILITARY
COMMERCIAL
-0.5 to + 7.0
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +Vcc
-0.5 to +Vcc
UNIT
SYMBOL
V
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
S
12
pF
NOTE:
1. This parameter is measured at characterization but. not tested.
V
TA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
120
120
mA
DC Output Current
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Input and VecTerminals Only.
3. Output and I/O Terminals Only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vec = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
"'H
"'L
TEST CONDITIONS (1)
PARAMETER
2.0
-
-
V
Guaranteed Logic Low Level
-
-
O.S
V
-
-
5
Input HIGH Current
VI = 2.7V
VI = 0.5V
Input LOW Current
VI = GND
Vo = 2.7V
los
VOH
-
5(4)
-
-5(4)
-
-5
-
10
-
10(4)
-
-10(4)
J.lA
Off State (High Impedance)
Output Current
Vcc = Max.
-
-
-10
Clamp Diode Voltage
Vcc = Min., IN = -1SmA
-
-0.7
-1.2
V
Short Circuit Current
Vcc = MaxP), Vo = GND
-60
-120
-
mA
Output HIGH Voltage
Vcc = Min.
VIN = VIH or "'IL
Vo = 0.5V
Vo = GND
"'K
UNIT
Guaranteed Logic High Level
Va = Vcc
loz
MAX.
Input HIGH Level
Vcc = Max.
IlL
TYp,(2)
Input LOW Level
VI = Vcc
IIH
MIN.
VOL
Output LOW Voltage
VH
Input Hysteresis
Icc
Quiescent Power Supply Current
10H = -6mA MIL.
2.4
3.3
10H = -SmA COM'L.
2.4
3.3
10H = -12mA MIL.
2.0
3.0
10H = -15mA COM'L.
2.0
3.0
-
-
0.3
0.5
0.3
0.5
10L = 32mA MIL.
Vcc = Min.
"'IN = "'IH or "'IL
10L = 4SmA COM'L.
Vcc = MAX., "'IN = GND or Vcc
V
200
-
mV
0.2
1.5
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-26
J.lA
--.-.. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - IDT54/74FCT257T/AT FAST CMOS
QUAD 2-INPUT MULTIPLEXER (3-STATE)
~-'-"--"""-"'--"'--'---.-.- . . -'. _..
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =
0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
Icc
Quiescent Power Supply Current
Vcc';' Max.
VIN ~ VHC ; VIN :5 VLC
fl = 0
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max,
VIN = 3.4V(3)
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
OE" = GND
One Bit Toggling
50% Duty Cycle
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OE" = GND
One Bit Toggling
Ic
.' MIN.
TYP.(2)
MAX•
-
0.2
1.5
mA
-
0.5
2.0
mA
\IN ~ VHC
\IN ~ VLC
-
0.15
0.25
mAl
\IN ~ VHC
. \IN ~ VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
\IN = GND
-
2.0
5.0
UNIT
MHz
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OE" = GND
Four Bits Toggling
\IN ~ ~c
\IN ~ VLC
(FCT)
-
1.7
4.0(5)
VIN = 3.4V
VIN = GND
-
2.7
8.0(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-27
_--_...
IDT54/74FCT257T/AT FAST CMOS
QUAD 2-INPUT MULTIPLEXER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT257AT
I DT54/74FCT257T
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
IN to 4.J
tpLH
. tpHL
Propagation Delay
StoZN
tpZH
tPZL
t HZ ·
tLZ
CONDITION (1)
TYP!3)
COM'L.
MIN.(2) MAX.
. MIL.
MIN!21
MAx:
COM'L.
TYPPI
MIL.
UNIT
MIN.(21
MAX.
MIN.(21
MAx.
4.5
1.5
5.0
1.5
8.0
-
-
-
-
-
ns
7.5
1.5
10.5
1.5
12.0
-
-
-
-
-
ns
Output Enable Time
6.0
1.5
8.5
1.5
10.0
-
-
-
-
-
ns
Output Disable Time
4.3
1.5
6.0
1.5
8.0
-
-
-
-
-
ns
CL ';" 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V. + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXXT
Device Type
X
X
Package
Process!
Temperature
Range
Y:,onk
P
D
' - - - - - - - - - - - - ; SO
L
E
'-----------------1
257
257A
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 54
74
S10:'28
Commercial
MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPAK
CMOS Quad 2-lnput Multiplexer (3-State)
Fast CMOS Quad 2-lnput Multiplexer (3-State)
-55°C to + 125°C
O°C to + 70°C
~
Integrated Device1echnoIogy.1nc.
PRELIMINARY
lOT 54/74FCT620T/AT
lOT 54/74FCT623T/AT
FAST CMOS OCTAL
BUS TRANSCEIVER
(3-STATE)
FEATURES:
DESCRIPTION:
• IDT54/74FCT620/623 equivalent to FAST TN speed
• IDT54/74FCT620AT/623AT 25% faster than FAST TN speed
• Equivalent to FAST TN output drive over full temperature and
voltage supply extremes
•
10L = 64mA (Commercial) and 48mA (Military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST TN (5~A max.)
The IDT54/74FCT623 is a non-inverting octal transceiver with
3-state bus-driving outputs in bOth the send and receive directions.
The outputs are capable of sinking 64mA and sourcing up to
15mA, providing very good capacitive drive characteristics.
These octal bus transceivers: are designed for asynchronous
two-way communication between data buses. The control function
implementation allows for maximum flexibility in timing.
The 'FCT620 is the inverting option of the 'FCT623.
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
Bl
B2
B3
[[!J
B4
B5
B6
B7
8a
'FCT620T
'FCT623T is the non-inverting option.
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4059/-
1989 Integrated Device Technology. Inc.
S10-29
IDT54/74FCT620T/AT AND IDT54/74FCT623T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
.««
'" ~ Cl
« u~
~
00
INDEX
Vee
L.J U II LJ U
3 2 U 20 19
GBA
Bl
B2
B3 .
A3
:J 4
la [:
Bl
A4
]5
17 [:
B2
:J a
:J 7
:J a
A5
B4
As
B5
Ba
B7
A7
B3
15 [:
B4
14C
B5
9 ·10 11 12 13
«"'0
z 00'" moo
...
<0
Cl
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
PIN NAMES
laC
nnnnn
Ba
DEFINITION OF FUNCTIONAL TERMS
L20-2
TRUTH TABLE
DESCRIPTION
ENABLE
INPUTS
'GBA
GAB
'FCT620
'FCT623
A Inputs or 3-State Outputs
L
L
B data to A bus
B Inputs of 3-State Outputs
H
H
g data to A bus
A data to B bus
H
L
Z
Z
H
g data to A bus
A data to B bus
B data to A bus
A data to B bus
GBA, GAB
Enable Inputs
Al - Aa
Bl - Ba
L
FUNCTION
H = High voltage level
L = Low voltage level
Z = High-impedance (OFF) state
S10-30
A data to B bus
IDT54/74FCT620T/AT AND IDT54/74FCT623T/AT
FASTCMOS OCTAL BUS TRANSCEIVER (3-STATE)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
VTERM (3)
Terminal Voltage
with Respect to
GND
TA
CAPACITANCE (TA= +25°C
(1)
COMMERCIAL
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMpERATURE RANGES
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
-0.5 toVcc
-0.5 to Vcc
V
Operating
Temperature
o to +70
-55 to + 125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
PARAMETER(1)
CIN
Input Capacitance
Cvo
Output Capacitance
f = 10MHz)
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
S
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI N GS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input & Vee terminals.
3. Output & 1/0 terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLe = 0.2V; VHC = Vec - 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vec = 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
-
V
O.S
V
VI = GND
-
Vo = Vce
-
-
\jH
Input HIGH Level
Guaranteed Logic High Level
2.0
\jL
Input LOW Level
Guaranteed Logic Low Level
-
IIH
VI = Vec
Input HIGH Current
(Except 1/0 pins)
VI = 2.7V
Vce = Max.
IlL
IIH
VI = 0.5V
Input LOW Current
(Except 1/0 pins)
Input HIGH Current
(1/0 pin only)
Vo = 2.7V
Vcc = Max.
Vo = 0.5V
-
5
5(4)
_5(4)
~A
-5
15
15(4)
-15(4)
~A
IlL
Input LOW Current
(1/0 pins only)
\jK
Clamp Diode Voltage
Vcc = Min., IN = -1SmA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = MaxP), Vo = GND
-60
-120
mA
10H = -6mA MIL.
2.4
3.3
Output HIGH Voltage
Vec = Min.
\1N = \1H or\1L
10H = -SmA COM'L.
2.4
3.3
10H = -12mA MIL.
2.0
3.0
10H = -15mA COM'L.
2.0
3.0
-
10L = 48mA MIL.
-
0.3
0.55
VOH
VOL
Output LOW Voltage
VH
Input Hysteresis
Icc
Quiescent Power Supply Current
Vo = GND
Vcc = Min.
\1N = VIH or\1L
10L = 64mA COM'L.
Vee = MAX., \1N = GND or Vcc
V
0.3
0.55
200
-
mV
0.2
1.5
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-31
-15
JDT54/74FCT620T/AT AND IDT54/74FCT623T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 2.0V; VHC = Vee - 0.2V
SYMBOL
PARAMETER
Icc
Quiescent Power Supply Current
Vee = Max.
VIN ;:: VHC ; VIN S VLC
f1 = 0
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
Ol:A= Ol:B= GND
One Input Toggling
50% Duty Cycle
ICCD
Vcc = Max.
Outputs Open
f1 = 10MHz
50% DU~YCle
Ol:A =
B = GND
One Bit Toggling
Ic
MIN.
TYP.(2)
MAX.
-
0.2
1.5
mA
-
0.5
2.0
mA
\'IN ;:: VHC
\'IN ;:: VLC
-
0.15
0.25
mAl
VIN ;:: VHC
\'IN ;:: VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.2
6.0
TEST CONDITIONS (1)
UNIT
MHz
mA
Total Power Supply Current(6)
VIN ;:: VHC (6)
\'IN ;:: VLC
(FCT)
Vcc = Max.
Outputs Open
f1 = 2.5MHz
50%DU~YCle
Ol:A =
B = GND
Eight Bits Toggling
VIN = 3.4V(6)
VIN = GND
-
3.95
7.8(5)
-
6.2
16.8(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (\'IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~I cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp "7 Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Input!; at fl
All curr~nts are in milliamps and all frequencies are in megahertz.
\
S10-32
--------------------------------------------
IDT54/74FCT620T/AT AND IDT54/74FCT623T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT620T
SYMBOL
PARAMETER
CONDITION(1)
TYp~3)
MIN.(2) MAX.
IDT54/74FCT620AT
(4)
COM'L
MIL
MIN!2)
TYp~3)
MAX.
COM'L
(4)
MIL
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
An to Bn
3.5
1.5
7.0
1.5
8.0
-
-
-
-
-
ns
tpLH
tpHL
Propagation Delay
Bn to An
3.5
1.5
7.0
1.5
8.0
-
-
-
-
-
ns
t pZH
t pZL
Output Enable Time
GBA to An
6.5
1.5
9.0
1.5
10.0
-
-
-
-
-
ns
t pHZ
tpLZ
Output Disable Time
'GBA to An
4.5
1.5
8.0
1.5
9.0
-
-
-
-
-
ns
tpZH
tpZL
Output Enable Time
GAB to Bn
6.5
1.5
9.0
1.5
10.5
-
-
-
-
-
ns
t pHZ
tpLZ
Output Disable Time
GAB to Sn
5.0
1.5
8.0
1.5
9.0
-
-
-
-
-
ns
~ =
50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V, + 25°C ambient and maximum loading.
4. These are preliminary numbers only.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT623T
SYMBOL
PARAMETER
CON DillON (1)
TYp~3)
MIN.(2) MAX.
IDT54/74FCT623AT
(4)
COM'L.
MIL
MIN~2)
TYp~3)
MAX.
COM'L
(4)
MIL
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
t pHL
Propagation Delay
An to Sn
4.0
1.5
7.5
1.5
9.0
-
-
-
-
-
ns
tpLH
tpHL
Propagation Delay
Sn to An
4.0
1.5
7.5
1.5
9.5
-
-
-
-
-
ns
t pZH
tpZL
Output Enable Time
'GSA to An
6.5
1.5
9.0
1.5
10.0
-
-
-
-
-
ns
t pHZ
t pLZ
Output Disable Time
'GBA to An
5.0
1.5
8.0
1.5
9.0
-
-
-
-
-
ns
t pZH
t pZL
Output Enable Time
GAS to Sn
6.5
1.5
9.0
1.5
10.5
-
-
-
-
-
ns
tpHZ
t pLZ
Output Disable Time
GAB to Sn
5.0
1.5
8.0
1.5
9.0
-
-
-
-
-
ns
CL = 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.
4. These are preliminary numbers only.
S10-33
IDT54174FCT620T/AT AND IDT54174FCT623T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
IDTXXFCT
Temp. Range
XXXXT
Device Type
x
Process/
Temperature
Range
Y:Mk
'------------1
'-----------------1
MIL-STD-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
620
620A
623
623A
Octal Bus Transceiver (Non-Inverting)
Fast Octal Bus Transceiver (Non-Inverting)
Octal Bus Transceiver (Inverting)
Fast Octal Bus Transceiver (Inverting)
'----------------------1 74
54
S10-34
Commercial
-55°C to + 125°C
O°C to + 70°C
t;)
Integrated Device1edmology.1nc.
FAST CMOS OCTAL
BUS TRANSCEIVER
(OPEN DRAIN)
PRELIMINARY
lOT 54/74FCT621T/AT
lOT 54/74FCT622T/AT
FEATURES:
DESCRIPTION:
• IDT54/74FCT621/622 equivalent to FAST™ speed
• IDT54/74FCT621/622A 25% faster than FAST™ speed
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
• IoL = 64mA (commercial) and 48mA (military)
• CMOS power levels (5}JW typo static)
• TTL input and output level compatible
• Substantially lower input current levels than FAST ™ (5}JA max.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT621 is an octal transceiver with non-inverting
Open-Drain bus compatible outputs in both send and receive directions. The outputs are capable of sinking 64mA, providing very
good capacitive drive characteristics. These octal bus transceivers
are designed for asynchronous two-way communication between
data buses. The control function implementation allows for
maximum flexibility in timing. The 'FCT622 is the inverting option
of the '621.
The dual-enable configuration can be used to disable the device and isolate the buses or, by simultaneously enabling GBA &
GAB, to store data.
FUNCTIONAL BLOCK DIAGRAM
GAS
Ae
GSA
-~--r--{]
A8-~-+--a
*'FCT622T is inverting option of the 'FCT621T
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
'FCT621T
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
,
1989 Integrated Device Technology, Inc.
510-35
DSC-4019/-
IDT54/74FCT621/622 FAST CMOS
OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
00
N
-« o~
««(!J ~ICJ
INDEX
GA8
A1
A2
A3
A4
A5
Ae
A7
Aa
GND
Vee
n8A
81
82
83
84
I 1'11.1' I
' - ' L....J I I
L....J
85
8e
87
8a
PIN NAMES
L....J
A3
A4
]4
81
:]5
17[:
82
A5
]e
1e [:
83
Ae
:] 7
15 [:
84
A7
:] a
14 [:
85
L20-2
10 11 12 13
~ nnnn
"'0
« z
(!J
DIP/SOIC/CERPACK
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
It
3 2 LJ 20 19
1
1a[
mmoo
....
10
LCC
TOP VIEW
TRUTH TABLE
FUNCTIION
ENABLE
INPUTS
GBA
GAB
'FCT621
'FCT622
A inputs or open drain outputs
L
L
8 data to A bus
8 inputs or open drain outputs
H
H
A data to 8 bus
g data to A bus
A data to b bus
H
L
OFF
OFF
H
8 data to A bus
A data to 8 bus
g data to A bus
A data to 8 bus
DESCRIPTION
GBA. GA8
Enable Inputs
A 1- Aa
8 1 - 88
L
H = High Voltage Level
L = Low Voltage Level
OFF = High if pull-up resistor is connected to Open-Collector output
S10-36
IDT54/74FCT621/622 FAST CMOS
OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
Terminal Voltage
VTERM (3) with Respect to
GND
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
-0.5 toVee
-0.5 toVee
V
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to + 125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C f = 10MHz)
PARAMETER(1)
C IN
Input Capacitance
CliO
I/O Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input and Vee terminals.
3. Output and 1/0 terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee - 0.2V
Commercial: TA = O°C to + 70°C; 'be = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
"'H
"'L
IIH
MIN.
TYPJ2)
MAX.
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
= 2.7V
-
5(4)
VI = 0.5V
-
-
-5(4)
= GND
= Vcc
-
-5
Vo = 2.7V
-
Vo = 0.5V
-
-0.7
-1.2
V
VOH = Vee (Max.)
-
-
20
~A
= 48mA MIL.
-
0.3
0.5
10L = 64mA COM'L.
-
0.3
0.5
-
200
-
mV
0.2
1.5
mA
TEST CONDITIONS (1)
PARAMETER
VI = Vee
Input HIGH Current
(Except 1/0 pins)
VI
Vee = Max.
IlL
IIH
IlL
Input LOW Current
(Except I/O pins)
VI
Vo
Input High Current
(I/O pins only)
Input Low Current
(I/O pins only)
Vee
= Max.
Vo
Clamp Diode Voltage
Vee = Min., IN = -18mA
10H
Output HIGH Current
Vee = Max.
'-'iN = VIH or VIL
VOL
Output LOW Voltage
Vec = Min.
'-'iN = '-'iH or '-'iL
"'K
VH
Input Hysteresis
Icc
Quiescent Power
Supply Current
10L
-
Vee = Max.
'-'iN = GND or\bc
= GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-37
UNIT
~A
15
15(4)
_15(4)
~A
-15
V
IDT54/74FCT621/622 FAST CMOS
OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC =. Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
MIN.
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN <::: VHC : VIN ~ VLC
fcp = fl = 0
-
.2
1.5
mA
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current<4)
Vcc= Max.
Outputs Open
GBA = GAB = GND or Vcc
One Bit Toggling
50% Duty Cycle
VIN <::: VHC
\'IN <::: VLC
-
0.15
0.25
mAl
\'IN <:::, VHC
\'IN <::: VLC
(FCT)
-
1.7
4.0
VIN = 3.4V
VIN = GND
-
2.2
6.0
\'IN <::: VHC
\'IN <::: VLC
(FCT)
-
3.2
6.5(5)
VIN = 3.4V
VIN = GND
-
5.2
14.5(5)
ICCD
Ic
Vcc = Max.
Outputs Open
GBA = GAB = GND or Vcc
One Bit Toggling
atf l = 10MHz
50% Duty Cycle
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
GSA = GAB = GND or Vcc
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc =. Quiescent Current
Alcc = Power Supply Current for a TIL High Input (\'IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-38
MHz
--_._.--------------------------------------------
IDT54/74FCT621/622 FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74 FCT621 A
IDT54/74FCT621
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
AtoB
tpLH
tpHL
Propagation Delay
BtoA
tpLH
tpHL
Prop~gation
t pLH
t pHL
Propagation Delay
GAB to B
CONDITION (1)
CL = 50pF
RL == 5000
Delay
GBAto A
TYp~3)
COM'L
MIN.(2) MAX.
COM'L.
MIL
MIN~2)
TYP!3)
MAX.
MIL
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
9.5
6.0
5.5
1.5
13.0
8.5
-
-
-
-
-
-
-
ns
9.0
5.5
5.5
1.5
12.5
8.0
-
-
-
-
-
-
-
ns
10.0
6.5
5.5
1.5
14.0
11.0
-
-
-
-
-
-
-
ns
12.0
6.5
6.0
1.5
17.0
10.0
-
-
-
-
-
-
-
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT622
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
AtoB
tpLH
tpHL
Propagation Delay
BtoA
tpLH
tpHL
Propagation Delay
GBAtoA
t pLH
tpHL
Propagation Delay
GAB to B
CONDITION(1)
CL = 50pF
RL = 5000
TYP~3)
COM'L.
MIN.(2) MAX.
IDT54/74FCT622A
MIL
MIN~2)
COM'L
TYP!3)
MAX.
MIL
MAX.
MIN.(2)
MAX.
11.0
4.0
8.0
1.5
13.5
6.0
-
-
-
-
-
-
-
ns
10.0
3.5
7.5
1.5
12.5
5.5
-
-
-
-
-
-
-
ns
10.5
6.0
8.0
1.5
12.5
10.5
-
-
-
-
-
-
-
ns
12.5
5.5
10.0
1.5
15.5
9.5
-
-
-
-
-
-
-
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
UNIT
MIN.(2)
XXX T
Device Type
Commercial
MIL-STD-883, Class B
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
621
621A
622
622A
Octal Bus Transceiver
Fast Octal Bus Transceiver
Octal Bus Transceiver (Inverting)
Fast Octal Bus Transceiver (Inverting)
P
o
' - - - - - - - - - - - - 1 SO
L
'-----------------1
'--_ _ _ _ _ _ _ _ _ _ _ _ _----:_ _ _ _ _--154
74
S10-39
-55°C to +125°C
O°C to + 70°C
fQ
Intesrated Device1echnology.lnc.
lOT 29FCT52A/B
lOT 29FCT53A/B
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
(Replaces
39C52/B and 39C53/B)
.DESCRIPTION:
FEATURES:
The IDT29FCT52 and IDT29FCT53 are a-bit registered traris~
ceivers manufactured using advanced CEMOS ™ , a dual-metal
CMOS technology. Two 8-bit back-to-back registers store data
.. flowing in both directions between two bidirectional buses. Sepa. rate clock, clock enable and 3-state output enable signals are pro. : vided for each register. Both A outputs and B outputs are guaranteed to sink 64mA.
The IDT29FCT52 is a non-inverting option of the IDT29FCT53.
• Equivalent' to AMD's Am2952/53 and Fairchild's 29F52/53 in
pinout/function
• IDT29FCT52A/53A equivalent to FAST ™ sReed;
IDT29FCT52B/53B 25% faster than FAST ™
• 10L = 64mA (commercial) and 48mA (military)
• Equivalent to FAST™ output drive over full temperature and
voltage supply extremes
• CMOS power levels (5)JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin DIP, SOIC, 28-pin LCC and PLCC with
JEDEC standard pinout
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
CPA
D)ELo~
CEA
D1
01
D2
O2
D3
031-~
D4
041-~
D,
a,~
D6
06
D7
07
Y
00
Do
L--<
01
D1
~
O2
D2
03
D3
04
D4
05
D5
06
D6
...
0 7 CECpD7
rI
CPS
.CE!':l
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Company
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
oSC-40oo/1
1989 Integrated Device Technology. Inc.
S10-40
IDT29FCT52A/B/IDT29FCT53A/B FAST
CMOS OCTAL_ REGISTERED _TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Vee
A7
A6
A5
A4
A3
A2
A1
23[
J28-1
L28-1
22[
:Je
21[
20[
Ao
OEA
CPB
:1
19[
11
12 13 14 15 16 17. _16
nnnnnnr:
CEB
« ~ 0z
11.
U
DIP/CERPACK/SOIC
TOP VIEW
"
~~&~
LCC/PLCC
TOP VIEW
PIN DESCRIPTION
NAME
I/O
DESCRIPTION
AO-7
I/O
Eight bidirectional lines carrying the A Register
inputs or B Register outputs.
REGISTER FUNCTION TABLE
(Applies to A or B Register)
INPUTS
D
INTERNAL
Q
CE
CP
.
BO-7
CPA
CEA
DEB
I/O
Eight bidirectional lines carrying the B Register
inputs or A Register outputs.
I
Clock for the A Register. When CEA is LOW,
data is entered into the A Register on the LOWto-HIGH transition of the CPA signal.
I
Clock Enable for the A Register. WhenCEA is
LOW, data is entered into the A Register on the
LOW-to-HIGH transition ofthe CPA signal. When
CEA is HIGH, the A Register holds its contents,
regardless of CPA signal transitions.
I
Output .Enable for the Ii. Register. When DEB is
LOW, the A Register outputs are enabled onto
the BO-7 lines. When DEB is HIGH,the BO-7 outputs are in the high impedance state.
CPB
I
Clock for the B Register. When CEB is LOW,
data is entered into the B Register ori the LOWto-HIGH transition of the CPB signal.
CEB
I
Clock Enable for the B Register. When CEB is
LOW, data is entered into the B Register on the
LOW-to-HIGH transition ofthe CPB signal. When
CEB is HIGH, the B Register holds its contents,
regardless of CPB signal transitions.
OEA
I
Output Enable for the BRegister. When OEA is
LOW, the B Register outputs are enabled onto
the AO-7 lines: When OEA is HIGH, the AO-7
outputs are in the high impedance state.
FUNCTION
.
X
X
H
NC
Hold Data
L
H
i
i
L
L
L
H
Load Data
OUTPUT CONTROL
OE INTERNAL
Q
Y-OUTPUTS
I DT29FCT52A/B IDT29FCT53A/B
H
X
Z
Z
Disable Outputs
L
L
L-H
L
H
H
L
Enable Outputs
S10-41
------------_.._-------------- ------_._--_._.
FUNCTION
-
---_._---_ _----------_
..
..
__. --
-_._--
IDT29FCT52A/B/IDT29FCT53A/B FAST
CMOS OCTAL REGISTERED TRANSCEIVERS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
Terminal Voltage
VTERM (3) with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATUR.E RANGES
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
-0.5 to +7.0
SYMBOL
V
-0.5 to Vcc
-0.5 to \bc
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lour
DC Output Current
120
120
mA
(TA= +25°C f = 1 OM Hz)
PARAMETER(1)
CIN
Input Capacitance
CliO
I/O Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
Vour= OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Input and Vcc terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA , = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
'-"H
VIL
TEST CONDITIONS (1)
PARAMETER
MAX.
UNIT
Guaranteed Logic High Level
2.0
-
-
V
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
VI = 2.7V(4)
-
VI = 0.5V(4)
-
-5
VI = GND
-
-
-
15
-15
-
-
-15
-0.7
-1.2
V
-60
-120
-
mA
VHC
VHC
Vcc
-300jJA'
-15mA MIL.
2.4
-
-24mA COM'L.
2.4
4.0
-
-
GND
VLC
-
GND
0.3
VLC
0.55
0.3
0.55
Input HIGH Current (Except I/O pins)
Vcc = Max.
IlL
Input LOW Current (Except I/O pins)
VI = Vcc
IIH
Input HIGH Current (I/O pins only)
VI = 2.7V(4)
Vcc ='Max.
VI = 0.5V(4)
IlL
Input LOW Current (I/O pins only)
'-"K
Clamp Diode Voltage
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = Max., (3) Va = GND
Output HIGH Voltage
Vcc = 3V, VIN = VLC or VHC ' 10H =
bH =
Vcc = Min.
10H =
'-"N = '-"H or '-"L
10H =
VOH
VI = GND
Vcc = 3V,
VOL
TYP.(2)
Input HIGH Level
VI = Vce
IIH
MIN.
Output LOW Voltage
'-"N
-32jJA
= VLC or VHC , 10L = 300jJA
bL = 300jJA
Vcc = Min.
'-"N = '-"H or'-"L
IoL = 48mA MIL.
10L = 64mA COM'L.
-
Vec
4.0
VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-42 '
5
jJA
-5
15
-
jJA
V
V
mV
----_._ •.._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I DT29FCT52A/B/IDT29FCT53A/B FAST
CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0 2V· VHG = Vcc - 0 2V
SYMBOL
P~RAMETER
TEST CONDITIONS
MIN.
(1)
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
Vcc ~ VHC ; '-"N ::5 VLC
fcp = fl = 0
-
0.001
1.5
rnA
.6.lcc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
'-"N = 3.4V(3)
-
0.5
2.0
rnA
Dynamic Power Supply Current
Vcc = Max.
Outputs Open
(5"E" = GND
One Input Toggling
50% Duty Cycle
'-"N ~ VHC (4)
'-"N ::5 VLC
-
0.15
0.25
rnA/MHz
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
DE = GND
One Bit Toggling
atfl = 5MHz
50% Duty Cycle
'-"N ~ VHC
'-"N ::5 VLC
(FCT)
-
1.5
4.0
'-"N = 3.4V
or
VIN = GND
-
2.0
6.0
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
DE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
'-"N
ICCD
Ic
Total Power Supply Current (6)
rnA
~
VHC (5)
VIN ::5 VLC
(FCT)
'-"N = 3.4V(5)
or
'-"N = GND
-
3.75
7.8
-
6.0
16.8
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + Icco (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-43
IDT29FCT52A/B/IDT29FCT53A/B FAST
CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT29FCT52A/53A
SYMBOL
t pLH
t pHL
Propagation Delay
CPA, CPB to Bn, An
t pZH
t pZL
OE"A or C5EB to An or Bn
t pHZ
tpLZ
Output Disable Time
OEA or C5EB to An or Bn
tsu
Set-up time HIGH or
LOW An, Bn to CPA, CPB
tH
Hold time HIGH or LOW
An, Bn to CPA, CPB
tsu
Set-up time HIGH or
LOW. CEA, CES to CPA,
CPS
tH
tw
CONDITIONS(1)
PARAMETER
Output Enable Time
CL = 50pF
RL = 5000
Hold time HIGH or LOW.
CEA, CEB to CPA, CPB
Pulse Width, HIGH or LOW
CPA or CPS
IDT29FCT52B/53B
MIL.
COM'L.
Typ.(3)
MIN.(2) MAX. MIN.(2) MAX.
TYPJ3)
COM'L.
MIL.
MIN.(2) MAX. MIN.(2) MAX.
UNIT
5.5
2.0
10.0
2.0
11.0
4.5
2.0
7.5
2.0
8.0
ns
5.5
1.5
10.5
1.5
13.0
4.5
1.5
8.0
1.5
8.5
ns
5.5
1.5
10.0
1.5
10.0
4.0
1.5
7.5
1.5
8.0
ns
1.0
2.5
-
2.5
-
1.0
2.5
-
2.5
-
ns
0.5
2.0
-
2.0
-
0.5
1.5
-
1.5
-
ns
-
3.0
-
3.0
-
-
3.0
-
3.0
-
ns
-
2.0
-
2.0
-
-
2.0
-
2.0
-
ns
-
3.0
-
3.0
-
-
3.0
-
3.0
-
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
ORDERING INFORMATION
IDT
29FCTXXX
Device Type
xx
X
Package
Process/
Temperature
Ray:''"'
L
SO
52A
53A
52B
53B
Non-inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver
Fast Non-inverting Octal Registered Transceiver
Fast Inverting Octal Registered Transceiver
J
S10-44
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Plastic Leadless Chip Carrier
Leadless Chip Carrier
Small Outline IC
P
D
E
1.--------------------1
Commercial (DOC to + 70°C)
t;)
MULTILEVEL
PIPELINE REGISTERS
Intesrated Device Technology. Inc.
PRELIMINARY
lOT 29FCT520A/B
lOT 29FCT521A/B
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29S20/21 bipolar Multilevel Pipeline
Registers in pinout/function, speeds and output drive over full
temperature and voltage supply extremes
• Four 8-bit high-speed registers
• Dual two-level or single four-level push-only stack operation
• All registers available at multiplexed output
• Hold, transfer and load instructions
• Provides temporary address or data storage
• 10L = 48mA (commercial), 32mA (military)
The IDT29FCTS20NB and IDT29FCTS21NB each contain four
8-bit positive edge-triggered registers. These may be operated as
a dual 2-level or as a single 4-level pipeline. A single 8-bit input is
provided and any of the four registers is available at the 8-bit,
3-state output.
These devices differ only in the way data is loaded into and between the registers in 2-level operation. The difference is illustrated
in Figure 1. In the IDT29 FCTS20A/B when data is entered into the
first level (I =20r I = 1), the existing data in the first level is moved to
the second level. In the IDT29FCTS21NB, these instructions simply cause the data in the first level to be overwritten. Transfer of data
to the second level is achieved using the 4-level shift instruction
(I =0). Transfer also causes the first level to change. In either part
I = 3 is for hold.
• CMOS power levels (SjJ.W typo static)
• Substantially lower input current levels than AMD's bipolar
(SjJ.Atyp.)
• TIL input and output level compatible
• CMOS output level compatible
• Manufactured using advanced CEMOS ™ processing
• Available in 300 mil plastic and hermetic DIP, as well as
LCC, SOIC and CERPACK
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
8
INSTRUCTION
10 .1 1
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4oo2/-1
1989 Integrated Device Technology, Inc
S10-45
IDT29FCT520A/B AND IDT29FCT521A/B
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN. CONFIGURATIONS
(INSTRUCTION) 10
(INSTRUCTION) 11
DO
D1
D~
D3
D4
D5
D6
I
1'1
'--'
D1
Yo
Y1
Y2
D2
Y3
D4
Y4
Y5
D5
De
NC
D3
Y6
Y7
D7
ClK
GND
~d'':..E~c8u)
INDEX
Vcc
So (MUX SEL)
S1 (MUXSEl)
:J 5
:J 6
:J 7
:J 8
4
'--'
I
I.
'--'
I
I
I
I
I"""
I
1'1
'--'
........
3 2 Ll 28 27 26
25[
24[
L28-1
:] 9
:J
10
:] 11
23[
221::
21[
20[
19[
Y2
Y3
Y4
Y5
12 13 14 15 16 17 18
nnnnnnn
C)E
... "'U
o:i@~ >->-z
Ul!)
LCC
TOP VIEW
DIP/CERPACK/SOIC
TOP VIEW
REGISTER SELECTION
PIN DESCRIPTION
PIN NO.(1)
3-10
DESCRIPTION
NAME
I/O
Do - D7
I
Register input port.
11
ClK
I
Clock input. Enter data into registers on lOW-to-HIGH transitions.
1.2
10. 11
I
Instruction inputs. See Figure 1
and Instruction Control Tables.
23.22
So. S1
I
Multiplexer select. Inputs either
registerA 1.A 2.B 1 0rB 2 datatobe
available at the output port.
13
OE
I
Output enable for 3-state output
port.
14-21
Y-7 - Yo
0
s,
So
Register
0
0
1
1
0
1
0
1
B2
B1
A2
A1
Register output port
NOTE:
1. DIP configuration.
SINGLE 4-lEVEl
DUAL 2-lEVEL
IDT29FCT520AlB
~
A2
G
G
0
G
1=2
IDT29FCT521 AlB
clJ
0
G
G
~ ~
82
A2
1= 1
0
G
cb
G
I = 1
1=2
NOTE:
1. I =3 for hold.
Figure 1. Data Loading in 2-Level Operation
S10-46
82
1=0
~
A2
82
1=0
NC
Yo
Y1
IDT29FCT520A/B AND IDT29FCT521A/B
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
SYMBOL
V
CIN
COUT
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
100
100
mA
-0.5 to +7.0
-0.5 to +7.0
(TA=·+25°C. f = 1.0MHz)
PARAMETER(l)
CONDITIONS TYP.
Input Capacitance
Output Capacitance
MAX. UNIT
VIN = OV
6
10
pF
VOUT = OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLe = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to + 70°C; 'te = 5.0V±5%
Military: TA = -55°C to + 125°C; Vce = 5.0V±10%
SYMBOL
"'H
"'L
IIH
MIN.
TYP.(2)
MAX.
UNIT
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
VI = Vcc
-
5
VI = 2.7V
-
-
5(4)
VI = 0.5V
-
-
-5(4)
-5
TEST CONDITIONS(l)
PARAMETER
Input HIGH Current
Vee = Max.
IlL
Input LOW Current
VI = GND
-
-
Vo = Vcc
-
-
10
Vo = 2.7V
-
-
10(4)
Vo = 0.5V
-
-
-10'4)
loz
Off State (High Impedance)
Output Current
Vce = Max.
-
-
-10
los
Short Circuit Current
Vce = Max!3). Vo = GND
-60
-120
-
Vcc = 3V, ~N = VLC or VHC • 10H = -32jJA
VHC
Vee
-
10H = -300jJA
VHC
Vce
-
10H = -12mA MIL.
2.4
4.3
-
10H = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
-
GND
VLC
-
0.3
0.5
0.3
0.5
Vo = GND
VOH
Output HIGH Voltage
Vec = Min.
VIN = VIH or ~L
Vce = 3V. ~N = VLC or VHC • 10L = 300jJA
10L = 300jJA
VOL
Output LOW Voltage
Vee = Min.
~N = ~Hor~L
10L = 32mA MIL.
10L = 48mA COM'L.
jJA
mA
V
V
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-47
IJA
IDT29FCT520A/B AND IDT29FCT521A/B
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS
PARAMETER
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC : VIN ~ VLC
fcp = fl = 0
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
= GND
One Input Toggling
50% Duty Cycle
ICCD
rn:
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at fl = 5MHz
50% Duty Cycle
Ic
(1)
MIN.
TYP.(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
2.0
rnA
'-"N ~ VHC
'-"N S VLC
-
0.15
0.25
rnA/MHz
'-"N ~ VHC
'-"N S VLC
(FCT)
-
2.3
4
VIN = 3.4V
or
VIN = GND
-
2.8
6
Total Power Supply Current (6)
rnA
Vec = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OE = GND
Eight Bits and
Four Controls Toggling
atfl = 5MHz
50% Duty Cycle
'-"N ~ VHC
'-"N S VLC
(FCT)
-
9.8
17.8(5)
VIN = 3.4V
or
VIN = GND
-
13.0
30.8(5)
NOTES:
1.. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples 01 the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcpf2 + '1 NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-48
IDT29FCT520A/B AND IDT29FCT521A/B
MULTILEVEL PIPELINE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT29FCT520B/21 B(4)
IDT29FCT520A/21A
SYMBOL
PARAMETER
CONDITIONS(1)
TYP(3)
COM'L
MIL
MIN.(2) MAX. MIN.(2) MAX.
TYP(3)
COM'L
MIL
MIN.(2) MAX. MIN52) MAX.
t pHL
t pLH
Clock to Data Output
7.0
2.0
14.0
2.0
16.0
2.0
7.5
t pHL
tpLH
So. Sl to Data Output
7.0
2.0
13.0
2.0
15.0
2.0
7.5
tsu
Set-up Time
Input Data to Clock
tH
Hold Time
Input Data to Clock
tsu
tH
6.0
2.5
2.0
2.0
2.0
Set-up Time
Instruction to Clock
5.0
6.0
4.0.(
Hold Time
Instruction to Clock
2.0
Output Disable Time
t pZH
tpZL
Output Enable Time
tw
:::::::8!6
ns
ns
........
5.0
t pHZ
t pLZ
2.6\::. 8.0
::JMt
UNIT
RL = 500n
CL = 50pF
6.0
1.5
2~Q
2.0
12.0
1.5
13.0
9.0
4.0
1.5
15.0
7.0
1.5
8.0
16.0
/:
h:; : :~':~:; : k'· -
.:::::\ I·: :!: ;~%·:~: :
.I: ·i~i;:; ;: ·: : :·
:.1::<:\£::·'
ns
ns
.::::::=8}::::
.:.:.....
I::::::::':
ns
2.0
ns
....;.;:::}::::::.
::;:;::::::.....
.:=
Clock Pulse Width
HIGH or LOW
-
1/:··.::~.~5 ::::::/7.0
j:j::::: I:;:·:· :.: j:·!~{:
: : : ji~: :!:'i:
7.5
1.5
7.5
ns
1.5
8.0
ns
I::
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ
RAMOE:
S1
7
Ao
so
Al
Ao
A2
A3
A4
Al
A2
A3
A4
Vcc
NC
Vce
GND
6 5 4
3 2
U 5251 50
494847
46[
45[
44 [
·43 [
42 [
41 [
40[
39[
38[
37[
1
J8
J9
J 10
J 11
J 12
J 13
J 14
J 15
J52-1
GND
NC
GND
A5
DAB
DCB
DCA
B5
J 2021 22 23 24 2526 2728 29 3031 32 3334 [
J19
B4
B6
36 [
35[
J 18
B3
B7
Vcc
A9
A8
A7
A6
J17
Bo
Bl
B2
Bg
B8
m
10
«
0
"'U 0
~
-
<"l
..
M10
«OOUUUZZUU~
000
10
'-!J0
Co
Cl
PLCC
TOP VIEW
C:i
DIP
TOP VIEW
LOGIC SYMBOL
~
INDEX~
0,-
~.o> "'@ .... '" 1()~I~UJ"\,1
~r-U
, -....CI)..-...CI)......
OC,..U...-..U....... ........U...-..U........
W"..I-J
....j.......
W.......
L.I LJ L.I L.J
6 5 4
Ao
J7
I.J
I I
I.J L.J L..I
L.J L.J L.I
3 2 I I 48 47 46 45 44 43
42[:
"I
41
Al
A2
A3
A4
Vce
GND
38 I:
37 [
L48-1
&
F48-1
] 14
J 15
J 16
J 17
J 18
36:::
35[
34 [
331:
32[
31 [
19 20 21 22 23 24 25 26 27 28 29 30
r-,·r, r, ,.., r, r, r, r-. r,
r1
r-, ,.,
48-PIN LCC/FLATPACK
TOP VIEW
S10-52
C
401:
39[
J9
J 10
J 11
J 12
J 13
A9
A8
A7
A6
A5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT804/A HIGH-SPEED TRI-PORT BUS MULTIPLEXER
PIN DESCRIPTION
DESCRIPTION
TYPE
NAME
AO - A9
I/O
A port 110
BO - B9
I/O
B port I/O
CO - C9
I/O
C port 110
RAM Ot:
0
Asserted (low) when B to A or B to C
paths are enabled
ITA
I
Active low enable for A port input latch
ITB
I
Active low enable for B port input latch
[E"c
I
Active low enable for C port input latch
SO - S1
I
Path selection inputs
DAB
I
Direction control for AB path
DCB
I
Direction control for CB path
DCA
I
Direction control for CA path
OEA
I
Output enable control for A port
OE B
I
Output enable control for B port
CfE"c
I
Output enable control for C port
GND 1 - 3
PWR
One ground for each port (Noisy ground)
GND4
PWR
Signal ground (Quiet ground)
VCC 1 - 2
PWR
+ 5V power supply
TRUTH TABLE-BUS CONTROL
OE
=0
LE
=0
S1
so
0
0
0
X
X
0
I
0
0
1
X
X
I
0
1
X
1
X
0
1
X
0
X
Z
Z
0
0
1
0
X
X
0
I
1
0
X
X
1
0
1
1
X
X
X
Z
DAB DCB DCA APORT BPORT CPORT RAM OE
Z
Z
H
I
H
L
I
0
L
Z
Z
Z
O.
H
I
H
Z
H
LATCH OPERATION
LE
OPERATION
0
Transparent
1
Port Data Latched
NOTE:
H = High, L = Low, I = In, 0 = Out, Z = High Impedance, X = Don't Care
S10-53
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT804/A HIGH·SPEED TRI·PORT BUS MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
(2)
RATING
Terminal Voltage
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
VTERM (3) with Respect to
GND
-0.5 to \6c
-0.5 to \6c
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
Output Capacitance
VOUT = OV
8
12
pF
I/O Capacitance
VOUT = OV
8
12
pF
CIN
Input Capacitance
COUT
CliO
NOTE:
1. This parameter is measured at characterization but not tested.
DC Output Current
120
mA
120
lOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.
2. Input and Vcc terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc • 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = ·55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
"'H
"'L
IIH
TEST CONDITIONS(l)
PARAMETER
Guaranteed Logic High Level
2.0
Input LOW Level
Guaranteed Logic Low Level
-
I~ut HIGH Current
( xcept I/O pins)
Vcc = Max.
IlL
Input LOW Current
(Except I/O pins)
IIH
Infcut HIGH Current
(I 0 pins only)
"'K
los
VI = Vcc
-
VI = 2.7V
-
VI = 0.5V
VI = GND
VI = Vcc
VI = 2.7V
Vcc = Max.
IlL
-
-
MAX.
UNIT
-
V
0.8
V
5
5(4)
-5(4)
15
15(4)
-15(4)
Vcc = Min., IN = -18mA
Short Circuit Current
Vcc = Max!3), Vo = GND
-60
-120
-
VI = GND
Output HIGH Voltage
Vcc = Min.
"'IN = "'IH orVIL
Output LOW Voltage
Vcc = Min.
"'IN = "'IH or "'IL
~A
-
-15
-0.7
-1.2
V
mA
VHC
Vcc
IOH = -300~A
VHC
Vcc
-
IOH = -12mA MIL.
2.4
4.3
-
IOH = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
10L = 300~A
-
GND
VLC
IOL = 32mA MIL.
-
0.3
0.50
IOL = 48mA COM'L.
-
0.3
0.50
VH
Input Hysteresis
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-54
~A
-5
Clamp Diode Voltage
Vcc = 3V, "'IN = VLC or VHC , IOL = 300~
VOL
TYP.(2)
-
VI = 0.5V
Infcut LOW Current
(I 0 pins only)
Vcc = 3V, "'IN = VLC or VHC ' IOH = ·32 ~
VOH
MIN.
Input HIGH Level
-
V
V
mV
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT804/A HIGH-SPEED TRI-PORT BUS MULTIPLEXER
POWER SUPPLY CHARACTERISTICS FOR 'FCT804
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
MIN.
TVP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; "'N ::5 VLC
fl = 0
-
0.001
1.5
mA
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
OEx = LEx = GND
One Bit Toggling
50% Duty Cycle
VIN ~ VHC
"'N ::5 VLC
-
0.15
0.25
mA!
MHz
"'N ~ VHC
\'IN ::5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN = GND
-
1.8
5.0
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50% D~Cycle
OEx = LEx = GND
One Bit Toggling
Ic
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% D~Cycle
OEx = LEx = GND
Ten Bits Toggling
\'IN ~ VHC (6)
VIN ::5 VLC
(FCT)
-
3.8
7.8(5)
VIN = 3.4V(6)
VIN = GND
-
6.3
17.8(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
510-55
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT804/A HIGH-SPEED TRI-PORT BUS MULTIPLEXER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT804A
IDT49FCT804
SYMBOL
PARAMETER
CONDITION(1)
MIL
COM'L
TYpJ3)
MIN.(2) MAX.
TYP,<3)
MIN~2)
MAX.
COM'L
MIN.(2)
MAX.
MIL
MIN.(2)
UNIT
MAX.
tpHL
t pLH
Propagation Delay
Port to Port
-
1.S
9.0
1.S
10.0
-
-
-
-
-
ns
tpHL
tpLH
Propagation Delay
LE to Port
-
1.S
12
1.S
13.0
-
-
-
-
-
ns
t pHL
tpLH
Propagation Delay
SO to S1 to Port
-
1.S
9.0
1.S
10
-
-
-
-
-
ns
tpZL
tpZH
Output Enable Time
Dxx or ~ to Port(4)
-
1.S
11.S
1.S
13.0
-
-
-
-
-
ns
tpLZ
tpHZ
Output Disable Time
Dxx or DE" to Port(4)
-
1.S
9
1.S
11
-
-
-
-
-
ns
tsu
Set-upTime
Port Data to LE
-
2
-
2.S
-
-
-
-
-
-
ns
tH
Hold time
Port Data to LE
-
2
-
2.S
-
-
-
-
-
-
ns
tpw
LE Pulse Width
HIGH or LOW
-
6
-
6
-
-
-
-
-
-
ns
CL = 50pF
RL = soon
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = S.OV, +2SoC ambient and maximum loading.
4. Dxx to port guaranteed but not tested.
S10-56
IDT49FCT804/A HIGH-SPEED TRI-PORT BUS MULTIPLEXER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SHARED RAM APPLICATION
128K x 8 SHARED RAM
its input from an extemal. arbiter/decoder (S1 = 0 and DAB. = DCB
= 1).
This application illustrates the use of IDT49FCT804 Bus MultIplexer in a shared memory application. In this example. two processors share a 128Kbyte memory bank. A pair of IDT49FCT804
multiplexers are used for address selection. The address busses
from the two processors are connected to A and C ports respectively. The B port serves as the memory address bus. With all Latch
Enable and Output Enable signals asserted. address from A or C
ports is routed to B port under the control of SO which receives
Two more IDT49FCT804 multiplexers route data between
the processor data busses connected to A and C ports and the
memory data bus connected to the B port. Again, address bus selection is under the control of input SO. Inputs DAB and DCB provide
direction control for READ and WRITE operations. The RAM OE
signal is asserted during the READ operation.
An extemal arbiter/decoder performs arbitration between two
processor requests and provides chip select & write enable signals
for the memory array.
128K X 8 SHARED RAM
LADDR
71256 : 32K X 8 SRAM
RADDR
LADDR
RADDR
CS, DS & RIW
CONTROLS
WRITE ENABLE
ARBITER/
DECODER
CHIP SELECT
71256
I/O (8: 15)
S10-57
71256
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT804/A HIGH-SPEED TRI-PORT BUS MULTIPLEXER
nected to the A port and the column address lines are connected to
the C port. All address signals are latched simultaneously in the A
and C port input latches. Under the control of path selection input
SO (S1 = LOW), the row and column addresses are sent sequentially to the DRAM array.
DRAM ADDRESS MULTIPLEXER APPLICATION
This application Illustrates the use of IDT49FCT804 Bus MUltiplexer for row and column addressing in a large DRAM array. In
this example, the full 10 bit capability of the Bus Multiplexer is used
to address a 1 MBit DRAM array. The row address lines are con-
DRAM ADDRESS MULTIPLEXER APPLICATION
RAM ARRAY
ADDRESS
BUS
LATCH ENABLE
SELECT
ORDERING INFORMATION
IDT49FCT
xxxx
Device Type
__x__
Package
x
Process/
Temperature
Range
-----II
1..-1
:Iank
MIL-STD-883. Class B
P
D
'----------------1 J
L
F
'----------------------1 804
804A
S10-58
Commercial
Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Ceramic Flatpack Chip Carrier
Tri-Port Bus Multiplexer
High Speed Tri-Port Bus Multiplexer
- -..._ . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
t;)
HIGH-SPEED
OCTAL REGISTER
WITH SPC
PRELIMINARY
IDT49FCT818
lOT 49FCT818A
lM
Integrated DeviceKxhooIosy. Inc.
FEATURES:
• High-speed, non-inverting 8-bit parallel register for any data
path, control path or pipelining application
• New, unique command capability which allows for multiplicity
of diagnostic functions
• High-speed Serial Protocol Channel (SPC ™ ) provides
- Controllability:
-
Serial scan in new machine state
Load new machine state "on the fly"
Temporarily force Y output bus
Temporarily force data out the D input bus (as in loading
WCS)
- Observability:
- Direct observe D and Y buses
- Serial scan out current machine state
- Capture machine state "on the fly"
• IOL = 32m A (commercial) and 24mA (military)
• CMOS power levels (5)JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49FCT818 is a high-speed, general purpose octal register with Serial Protocol Channel (SPC). The D-to-Y path of the octal
register provides a data path that is designed for normal system
operation wherever a high-speed clocked register is required.
The SPC command and data registers are used to observe and
control the octal data register for diagnostic purposes. The SPC
command and data registers can be accessed while the system is
performing normal system function. Diagnostic operations then
can be performed "on the fly", synchronous with the system clock,
or can be performed in the "single step" environment. The SPC
port utilizes serial data in and out pins (a concept originated at 18M)
which can participate in a serial scan loop throughout the system.
Here normal data, address, status and control registers are replaced with the IDT49FCT818. The loop can be used to scan in a
complete test routine starting point (data, address, etc). Then, after
a specified number of clock cycles, the data can be clocked out
.
and compared with expected results.
As well as diagnostic operations, SPC can be used for
initializing at power-on time functions such as Writable Control
Store (WCS).
• Substantially lower input current levels than 29818 and
54/74AS818 (5)JA max.)
• Available in plastic and sidebraze DIP, SOIC, LCC and
CERPACK
FUNCTIONAL BLOCK DIAGRAM
SOl
0,-0
SCLK
c/o
SERIAL
PROTOCOL
DATA
AND
COMMAND
REGISTERS
PARALLEL
DATA REGISTER
PCLK
OE"y
Y7- 0
SDO
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
19891ntegrated Device Technology, Inc.
JANUARY 1989
DSC-4oo3/-1
810-59
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE"y
INDEX
Vee
C/I)
SCLK
D7
D6
Y7
Ds
Ys
Y4
Y3
Y2
Y1
Ye
D4
D3
Dz
D1
:J s
Ds
:Je
D4
NC
:J 7
:J 8
D3
:Js
D2
D1
Yo
SDO
PCLK
Do
SDI
GND
De
:J 10
:J 11
12 13 14 15 1e 17 18
nnnnnnn
@~
0°
~ ~
DIP/CERPACK/SOIC
TOP VIEW
8
~C/)
Cl
>-0
LCC
TOP VIEW
TRUTH TABLE
LOGIC SYMBOL
SDI
SCLK
PCLK
OEy
D
X
X
X
H
X
L
H
H
L
L
L
Clock D toY
SDO
SCLK
X
X
X
X
PCLK
C/l)"
FUNCTION
Y
C/O
OE"y
S
S
HighZ Tri-state Y
Clock DtoY
H
S
X
X
X
X
Shift bit into SPC
Command register
L
S
X
X
X
X
Shift bit into SPC Data
register
L
S
H or L
(Static)
X
X
X
Execute SPC command
during time between
C/O &SCLK
NOTE:
H
HIGH Voltage Level
L
X
LOW Voltage Level
Don't Care
Z
High Impedance
L S
= Transition, H to L or L to H
PIN DESCRIPTION
PIN NAME
I/O
PCLK
I
DESCRIPTION
Parallel Data Register Clock
Parallel Data Register Input Pins (Do = LSB, D7 =" MSB)
D7- 0
I/O
Y7- 0
I/O
Parallel Data Register Output Pins (Vo = LSB, Y7 = MSB)
OEy
I
Output Enable for Y Bus (Overidden by SPC Inst. 8 & 14)
Serial Data In for SPC Operation. Data and command shifts in the Least Significant Bit first
SDI
I
SDO
0
C/O
I
Mode Control for SPC
SCLK
I
Serial Shift Clock for SPC Operations
Serial Data Out for SPC Operation. Data and command shifts out the Least Significant Bit first
S10-60
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC lOA
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-0.5 to +7.0
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
Operating
Temperature
Oto +70
-55 to +125
°c
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°c
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°c
W
mA
Power Dissipation
0.5
0.5
lOUT
DC Output Current
120
120
CIN
V
fA
PT
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input CapaCitance
CONDITIONS TYP.
MAX. UNIT
6
VIN= OV
10
pF
I/O Capacitance
8
12
pF
\bUT = OV
CliO
NOTE:
1. This parameter is guaranteed by characterization data and not
tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.OV±5%
Military: TA ;" -55°C to + 125°C; Vec = 5.OV±10%
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
-
V
0.8
V
VI = Vee
-
VI = 2.7V
VI = 0.5V
-
-
VI = GND
-
-
-5
VI = Vee
-
-
15
VI = 2.7V
-
-15(4)
'-"H
Input HIGH Level
Guaranteed Logic High Level
2.0
VIL
Input LOW Level
Guaranteed Logic Low Level
-
IIH
I~ut HIGH Current
( xeept I/O pins)
Vee = Max.
IlL
IIH
Input LOW Current
(Except I/O pins)
InJEut HIGH Current
(I 0 pins only)
5
5(4)
-5(4)
~A
-
-
'-"K
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vee = Max!3), Vo = GND
-60
-120
-
mA
Vec = 3V, VIN = VLC or VHC , IOH = -32~
VHC
Vee
-
IOH = -300~A
VHC
Vee
-
IOH = -12mA MIL.
2.4
4.3
-
IOH = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
Vee = Max.
IlL
VOH
InJEut LOW Current
(I 0 pins only)
Output HIGH Voltage
Vee = Min.
'-'iN = '-'iH or'-'iL
VI = 0.5V
-
VI = GND
Vee = 3V, \IN = VLe orVHe , IOL = 300~
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or '-'iL
~A
-15
IOL = 300~A
-
GND
VLC
IOL = 24mA MIL.
-
0.3
0.5
IOL = 32mA COM'L.
-
0.3
0.5
VH
Input Hysteresis on Clocks Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-61
15(4)
-
V
V
mV
IDT49FCT818/A HIGH·SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V LC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS
PARAMETER
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~VHC; "IN S VLC
fcp= fl = 0
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs .Open
ITE'y = GND
One Input Toggling
50% Duty Cycle
ICCD
Ic
Total Power Supply Current
(6)
Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OEy = GND
One BitToggling
atfl = 5MHz
50% Duty c~cle
SCLK = CI =
SDI = Vcc
Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OEy = GND
Eight Bits Toggling
atf l = 5MHz
50% Duty c~cle
SCLK = CI =
SDI = Vec
(1)
MIN.
TYP.(2)
MAX.
-
0.001
1.5
rnA
-
0.5
2.0
rnA
VIN ~ VHC
"IN S VLC
-
0.15
0.25
"IN ~ VHC
"IN S VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN = GND
-
2.0
6.0
mAl
MHz
rnA
VIN ~ VHC
"IN S VLC
(FCT)
-
3.75
7.8(5)
VIN = 3.4V
VIN = GND
-
6.0
16.8(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Ice DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input ("IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non·Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-62
UNIT
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT818A (3)
IDT49FCT818
SYMBOL
PARAMETER
CONDITION(1)
COM'L.
COM'L.
MIL.
MIL.
UNIT
MIN!2) MAX. MIN!2) MAX. MIN.(2) MAX. MIN!2) MAX.
tpHL
t pLH
T1
PCLK i toY
3.0
12.S
3.0
14.0
3.0
9.0
3.0
10.0
T2
SCLK i to SDO
3.0
20.0
3.0
22.0
3.0
14.0
3.0
1S.0
T3
SDI toSDO
(in stub mode)
3.0
20.0
3.0
22.0
3.0
14.0 \3.0
1S.0
T4
C/D! to Y
(OEy = Low
Inst. 8 & 14)
3.0
16.0
3.0
18.0
3.0
13.0~
14.0
TS
SCLK i to Y
(DEy = High,
Inst. 8)
3.0
20.0
3.0
22.0
3.0
T6
C/D to SDO
(Inst. 0,1,2 & 4)
3.0
12.S
3.0
14.0
3.0
t pZH
tpZL
tw
I.~:
t
,.:~;{
S1
D to PCLK i
2.S
-
3.0
C/O to SCLK i
12.0
-
14.0
-
12.0
S3
SDI toSCLK i
4.0
-
S.O
-
4.0
-:tii: :::§:O
S4
Yor D to C/D!
(Inst. 0, 2 & 4)
2.0
-
2.S
-
2.0
-
SS
C/[5 (Low) to
PCLK i
(Inst. 3 & 13)
8.0
-
9.0
S6
Yto PCLK i
(Inst. 3)
1.0
..;.
1.S
-
1.0
-
H1
D to PCLK i
2.0
-
2.S
2.0
}j}:: I:::~i§::' ::::(-
H2
C/D to SCLK!
12.0
-
14.0
-
12.0
:::<@I:J~.o:) t:;·-
H3
SDI toSCLK i
1.0
-
1.0
-
1.0
r<1;t.L. ..:::-
H4
Yor D to C/D!
(Inst. 0, 2 & 4)
2.0
-
2.S
-
2.0
!: -
2.0
-
2.S
-
2.0
-
2.0
-
2.S
-
2.0
HS
H6
t pHZ
t pLZ
!!!:~~I
~
S2
tsu
tH
1:I;'r:::?
10.0::
SCLK (Low) to
PCLK i
(Inst. 3 & 13)
C/D (Low) to
PCLK i
(Inst. 3 & 13)
-
2.S
CL = SOpF
RL = soon
8.0
OEy toY
3.0
2Z
SCLK ito D
(Inst. S & 9)
3.0
3Z
C/D ito DorY
(Inst. S & 9)
3.0
4Z
SCLK ito Y
(CiEy = High
Inst. 8 & 14)
SZ
-
S.O
-
10.0
3.0
11.0
13.0
3.0
14.0
13.0
3.0
14.0
3.0
13.0
3.0
14.0
ClQ to i to D or Y
(OEy = High
Inst. 14)
3.0
13.0
3.0
14.0
Z1
OEy to Y
3.0
11.0
3.0
12.0
3
Z2
C/D! to D
(Inst. S & 9)
3.0
14.0
3.0
1S.0
~.
Z3
CiQ! toY
(DEy = High
Inst. 14)
3.0
14.0
3.0
1S.0
3.0
7.0
2S.0
-
-
8.0
2S.0
-
7.0
2S.0
PCLK (High & Low)
ns
-
ns
"::,'
1Z
SCLK (High & Low)
~:i::!"
-
Yto PCLK i
(Inst. 3)
W2
~4.
:::::.
H7
W1
.::::.
ns
4.S
-
4.S :::
-
3:~1i
.q::
I::
9.0
11.0
f---
11.0
ns
11.0
f---
-
11.0
':::io
10.0
11.0
ns
3.0
-
11.0
::8.0
-
jS.~
-
2S.0
2S.0
2S.0
2S.0
W3 C/D (High)
NOTES:
1. See test circuit and waveforms.
3. Preliminary information only.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
510-63
ns
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH 5PC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
GENERAL AC WAVEFORMS FOR PARALLEL INPUTS AND OUTPUTS
PCLK
D
Y
GENERAL AC WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS
SCLK
I
SOl
:J,<
®I:
I
·1-
tsu
tH
SDO
Cil)
(DECODE)
(EXECUTE)
--------~ll~.--~\~.-·I®
tw
510-64
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED WAVEFORMS OF SERIAL PROTOCOL OPERATIONS
PARALLEL DATA REGISTER -
SPC Data (Inst. 1)
Y -
SPC Data (Inst. 0)
D -
SPC Data (Inst. 2)
SET SERIAL MODE (Inst. 11)
Status -
SPC Data (Inst. 4)
SET STUB MODE (Inst. 12)
SCLK
SCLK
C/1'5
C/l)
~~~----------~.+~
tsu
D. Y. CE.
PCLK
SDO
SDO
SPC Data CONNECT Y TO 0 (Inst. 5)
SPC Data -
SPC Data -
PARALLEL DATA REGISTER (Inst. 10)
Y (Inst. 8)
CONNECT 0 TO Y (Inst. 14)
0 (Inst. 9)
SCLK
SCLK
C/f5
C/f5
'D
Y
t~:I~
Y -
SPC Data
SYNCHRONOUS W/PCLK (Inst. 3)
SPC Data -
SCLK
SCLK
C/f5
C/f5
PCLK
PCLK
Y
S10-65
PARALLEL DATA REGISTER SYNCHRONOUS
W/PCLK (Inst. 13)
,
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED FUNCTIONAL BLOCK DIAGRAM
D
SDI
r---
-----------------------------,
SERIAL PROTOCOL COMMAND & DATA REGISTERS
I
I
I
I
cilS"
PCLK
A>----CJEy
SCLK
L _______________
~
___ _
y
SDO
The detailed block diagram consists of two main elements: the
parallel data register and the SPC data/command registers. The
main data path is from the 0 inputs down to the data register and
through to the Y outputs. This path is typically used during standard operations. For diagnostic or systems initialization, the internal SPC data path is used. This path allows access between the
SPC data and command registers and the standard data path, pins
and data register. The SPC data and command registers are accessed via the SOl, SDO, C/O and SCLK pins.
cilS"
register is used to control loading of data to and from the data register with other storage elements in the device.
With respect to executing an SPC command, there are four distinct phases: (1) data is shifted in, (2) followed by the command, (3)
the command is executed, and (4) data is shifted out. During the
data mode, data is simultaneously shifted into the serial data register while the data in the register is shifted out. During the command
mode, opcode-type information is shifted through the serial ports.
The command is executed when the last bit is shifted in and the
C/O line is brought low. The execution phase is ended with the next
serial clock edge.
SPCCOMMAND
REGISTER
XFER
(EXECUTE
SPC
COMMAND)
C/IS"
SDO
SPC DATA
REGISTER
SCLK - - - - - I I >
SCLK
C/IS"
SPC FUNCTIONAL DESCRIPTION
The Serial. Protocol Channel (SPC) has been optimized for the
minimum number of pins and the maximum flexibility. The data is
passed in on a Serial Data Input pin (SOl) and out on a Serial Data
Output pin (SDO). The transfer of the data is controlled by a Serial
Clock (SCLK) and a Command/Data mode input (C/O). These four
pins are the basic SPC pins. To the outside, the SPC appears as
two serial shift registers in parallel-one for command and the
other data. The serial clock shifts data and the Command/Data
(C/O) line selects which register is being shifted. The command
S10-66
SCLK
XFER
CD 10 CD
1
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SPC data and commands are shifted in through the SDI pin,
which is a serial input pin, and out through the SDO pin, which is a
serial output pin. Data and commands are shifted in Least Significant Bit first; Most Significant Bit last (Yo = LSB, Y 15 = MSB). Execution of SPC commands is performed by stopping the shift clock,
SCLK, and lowering the c/B line from high-to-Iow. Later the SCLK
may then be transitioned from low-to-high. SPC commands and
data can be shifted anytime, without regard for operation. During
the execution phase, care must be taken that there is no conflict
between the SPC operation and parallel operation. This means that
if the SPC operation attempts to load the parallel data register (opcode 10) while PCLK is in transition, the results are undefined. In
general, it is required that the PCLK be static during SPC operations. The synchronous commands (opcode 3 and 13), however,
allow the PCLK to run. In these operations, the high-to-Iow transition of the C/D line takes on the function of an arm signal in preparation for the next low-to-high transition of the PCLK.
SDI
SERIAL
PROTOCOL
SCLK
DATA
cio
SDO
There are 16 possible SPC opcodes. Fourteen of these are utilized, the other two are reserved and perform NO-OP functions. The
top eight opcodes, 0 through 7, are reserved for transferring data
into the SPC data register for shifting out. The lower eight opcodes,
8 through 15, are used for transferring data from the SPC data register to other parts of the device. Two of the commands are also
used for connecting the data in and out pins.
0
Data Register -+ SPC Data (Inst. 1)
SDI
D
SPCCOMMAND
1
Parallel Data Register to SPC Data Register
D to SPC Data Register
3
Y to SPC Data Register Synchronous w/PCLK
4
Status (DEy. PCLK) to SPC Data Register
5
Y
Y to SPC Data Register
2
6-7
PCLK
&
COMMAND
A>-----~y
SPC COMMANDS
OPCODE
Y -+ SPC Data (Inst. 0)
D
SERIAL
PROTOCOL
SCLK
C/O
Connect Y to D
Reserved (NO-OP)
8
SPC Data to Y (~ is overidden)
9
SPC Data to D
10
SPC Data to Parallel Data Register
11
Select Serial Mode
12
Select Stub Mode
13
SPC Data to Parallel Data Register Synchronous
w/PCLK
14
Connect D to Y (~ is overidden)
15
NO-OP
DATA
&
COMMAND
PCLK
REGISTERS
OE"y
SDO
iII
Y
D -+ SPC Data (Inst. 2)
SDI
Opcode 0 is used for transferring data from the Youtput pins into
the SPC data register. Opcode 1 transfers data from the output of
the register, befure the tri-state gate, into the SPC data register.
Opcode 2 transfers data from the D input pins into the SPC data
register.
D
SERIAL
PROTOCOL
SCLK
C/O
DATA
&
COMMAND
PCLK
JCr----~y
REGISTERS
SDO
S10-67
Y
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Opcode 3 transfers data on the Y pins to the SPC data register
on the next PCLK, thus achieving a synchronous observation of the
SPC data register in real time. This operation can be forced to repeat without shifting in a new command by pulsing C/Olow-highlow after each PCLK. As soon as data is shifted out using SCLK, the
command is terminated and must be loaded in again.
Opcode 5 connects Y to D. Opcodes6 and 7 are reserved,
hence designated NO-OP.
Connect Y to D (Inst. 5)
SDI
SERIAL
PROTOCOL
Y -+ SPC Data Synchronous w/PCLK (Inst. 3)
SDI
D
SCLK
D
C/O
SERIAL
PROTOCOL
DATA
&
COMMAND
PCLK
REGISTERS
OE"y
SCLK
DATA
&
C/O
SDO
COMMAND
Y
REGISTERS
SPC Data -+ Y (Inst. 8)
SDI
D
y
SDO
SERIAL
PROTOCOL
SCLK
PCLK
DATA
C/O
Opcode 4 is used for loading status into the SPC data register.
The format of bits is shown below.
7
6
&
COMMAND
Jr----OE"y
REGISTERS
o
5
SDO
OE"y
y
Opcode 8 is used for transferring SPC data directly to the Y pins.
When executing opcode 8, the state of OE y is a "do not care"; that
is, data will be output even if OE y = HIGH. Opcode 9 is used for
transferring SPC data to the D pins. Qperands 8 and 9 can be temporarily suspended by raising the C/D input and resumed by lowering the C/O. As soon as SCLK completes transition, the command is terminated.
Status -+ SPC Data (Inst. 4)
SDI
D
SDI
SERIAL
PROTOCOL
SERIAL
PROTOCOL
SCLK
SCLK
PCLK
DATA
Cio
C/O
COMMAND
OE"y
REGISTERS
SDO
PCLK
DATA
&
&
COMMAND
OEy
REGISTERS
y
SDO
S10-68
y
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC TOO
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Opcode 10 is used for transferring data from the SPC data register into the parallel data register, irrespective of the state of PCLK.
However, PCLK must be static between C/O going high-to-Iow and
SCLK going low-to-high.
STUB MODE
DEVICE #2
DEVICE #3
DEVICE #4
SDI--~---.---rr---r---~---.--~--.SDO
SPC Data -+ Parallel Data Register (Insl10)
SDI
D
SDI--~---r--~~---.--~~
SERIAL
PROTOCOL
SCLK
DATA
&
COMMAND
Cf[5
PCLK
1I-P~------~----~
Opcode 13 transfers data from the SPC data register to the parallel data register on the next PCLK. Opcode 14 connects the D bus
to the Y. Operation 14 can be temporarily suspended by raising the
C/O input and resumed by lowering the C/O input again, The operation is terminated by SCLK.
REGISTERS
SPC Data -+ Parallel Data Register Synchronous w/PCLK (Insl13)
SDO
Y
SOl
Opcodes 11 and 12 are used to set Serial and Stub Mode, respectively. After executing one of these opcodes, the device
remains in this mode until programmed otherwise. The Serial
mode is the default mode that the IDT49FCT818 powers up in. In
Serial mode, commands are shifted through the SPC command
register and then to the SDO pin. This is the typical mode used
when several varieties of devices that utilize the SPC access
method are employed on one serial ring.
SERIAL
PROTOCOL
SCLK
C/O
SERIAL MODE
DEVICE #1
SOl
DEVICE #2
DEVICE #3
DEVICE #4
o
PCLK
DATA
&
COMMAND
REGISTERS
mil
DEVICE #5
SDO
In Stub mode, SDI is connected directly to SDO. In this way, the
same diagnostic command can be loaded into multiple devices of
like type. For example, in four clock cycles the same command
could be loaded into 8 IDT49FCT818s (64-bit pipeline register).
Dissimilar devices must be segregated into serial scan loops of
similar type, as shown below. During the command phase, the serial shift clock must be slowed down to accommodate the delay
from SDI to SDO through all ofthe devices. The slower clock is typically a small tradeoff compared to the reduced number at. clock
cycles.
SDO
Connect D to Y (Insl14)
SOl
SCLK
PCLK
DATA.
&
COMMAND
REGISTERS
S10-69
o
SERIAL
PROTOCOL
cio
Note: The state of OEy is a "do not care;" that is, data will be output
even if OEy = High.
Y
SDO
.b--------
'Ol:y
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Opcodes 3 and 13 transfer data synchronous to the PCLK which
means that the high-to-Iow on the ci5 input is an arm signal. The
data and command can be shifted in while the PCLK is running.
The C/O line is dropped prior to the desired PCLK edge and raised
before the next edge. Instruction 13 can be repeated over many
times by leaving the C/O line low during multiple transitions of the
PCLK while not clocking SCLK. PCLK cycles can even be skipped
by raising the ci5 input during the desired clock periods. Instruction 3 can be repeated by pulsing the ciB high after each PCLK.
The ability to continuously execute a synchronous command
can provide major benefits. For example, the synchronous read
(Instruction 3, Y to SPC data) instruction could be clocked into the
SPC data register. Then, it could be continuously executed by
pulsing the C/O line high. When the whole system is stopped
(PCLK quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted out
and the current state of the parallel register can then be observed,
allowing for the observation oftwo states of the parallel register (the
current and the previous).
TYPICAL APPLICATION
In the block diagram of the typical application, the SPC data
register Is shown being used with a writable control store in a
microprogrammed design. The control store can be initialized
through the diagnostics path. The SPC data register is used for the
instruction register going into the IOT49C410, as well as for data
registers around the IOT49C403. In this way, the designer may use
the SPC data register to observe and modify the microcode coming out of the writable control store, as well as observing and being
able to modify data and instructions in the overall machine. The
IOT49C403 is a 16-bit version of the 2903A1203 which includes an
SPC port for diagnostic anq break point purposes.
The block diagram of the diagnostics ring shows how devices
with diagnostics are hooked together in a serial ring via the SOl and
SOO signals, The diagnostics signals may be generated through
registers which are hooked up to a microprocessor. This microprocessor could conceivably be an IBM PC.
c/o
SCLK
EXECUTE
(SPCCMO)
PCLK
TYPICAL MICROPROGRAM APPLICATION WITH SPC ™
rl
J
IR
(REG w/SPC)
49FCT818
SOl
SOO
I
OATAIN
(REG w/SPC)
49FCT818
I
t
rl
IOT49C410
SEQUENCER
SO
J
SOO
SOl
-
IOT49C403
~
ALU WIT
~w/SPCJ
REG I TER FILE
WCS
10T71981
S 01
t
PIPELINE REG
(REG w/SPC)
49FCT818
a
soo
SOil
1
I
S10-70
OATAoUT
(REG w/SPC)
49FCT818
r
~o
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
As companies like lOT continue to integrate more onto each device and put each device into smaller packages such as surface
mount devices, the board level testing becomes more complex for
the designer and the manufacturing divisions of companies. To
help this situation, serial diagnostics was invented. This allows for
observation of critical signals deep within the system. During system test, when an error is observed, these signals may be modified
in order to zero in on the fault in the system.
Serial diagnostics is primarily a scheme utilizing only a few pins
(4) to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults. It can be used at
many points in the life of a product: design debug and verification,
manufacturing test and field service. This document describes a
serial diagnostic scheme which was developed at lOT and will be
used in future VLSI logic devices designed by lOT.
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test
environment. Large output currents are being switched in very
short periods and proper testing demands that test set-ups have
minimized inductance and guaranteed zero voltage grounds. The
techniques listed below will assist the user in obtaining accurate
testing results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper device operation and possible latchup.
S10-71
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as pOSsible to the OUT power pins.
3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being
recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To allow
for testing and hardware-induced noise, it may be necessary to
use VIL::; OV and VIH ~ 3V for ATE testing purp~ses.
IDT49FCT818/A HIGH-SPEED OCTAL
REGISTER WITH SPC TM.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxx
Device Type
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class 8
P
'--_ _ _ _ _ _ _ _ _ _ _ _-; C
E
L
SO
'----------------------1
810-72
49FCT818
49FCT818A
Plastic DIP
Sidebraze DIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Octal Register with SPC ™
High-Speed Octal Register with SPC ™
~
Integrated Device'R!chnology.lnc.
FAST CMOS
1-0F-8 DECODER
lOT 54j74FCT138
lOT 54j74FCT138A
FEATURES:
DESCRIPTION:
• IDT54/74FCT138 equivalent to FAST ™speed;
IDT54/74FCT138A 35% faster than FAST ™
• Equivalent to FAST ™speeds and output drive over full
temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5~A max.)
• 1-of-8 decoder with enables
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
The IDT54/74FCT138 and IDT54/74FCT138Aare 1-of-8decoders built using advanced CEMOS TM, a dual metal CMOS technology. The IDT54/74FCT138 and IDT54/74FCT138A accept three binary weighted inputs (Ao, A1, A2) and, when enabled, provide eight
mutually exclusive active LOW outputs (00 -0,). The
IDT54/74FCT138 and IDT54/74FCT138A feature three enable inputs, two active LOW (E1' E2) and one active HIGH (E3). All outputs
will be HIGH unless E 1 and E2 are LOW and E3 is HIGH. This mUltiple enable function allows easy parallel expansion of the device to
a 1-of-32 (5 lines to 32 lines) decoder with just four
IDT54/74FCT138 or IDT54/74FCT138A devices and one inverter.
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87654 is listed on this
function. Refer to Section 2/page 2-4.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Ao
A1
A2
~1
~2
E3
07
GND
DIP/50lC/CERPACK
TOP VIEW
0
o 0
ci «0 0
z >10
INDEX
I
I'
~
A2 ]4
E:1 :J 5
NC ]6
1:2 :J 7
E3 ]8
I
L-I
I
I
II
1'1
L-I
I
L-I
3 2 Ll 20 19
1
18[
L.20-2
9 10 11 12 13
01
17 [:
O2
16 [:
15 [:
14 [:
03
NC
04
nnnnn
.... 0
o
<0
It)
z z 10 10
10 (!)
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
I MILITARY
AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
DSC-4005/-1
510-73
IDT54/74FCT138/A FAST
CMOS 1·0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
MILITARY
-0.5 to +7.0
V
-55 to +125
°c
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to + 125
-65 to + 135
°c
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°c
o to
+70
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C f = 1.0MHz)
PARAMETER(l)
SYMBOL
UNIT
CIN
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
COUT
VOUT= OV
8
12
pF
Output Capacitance
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V ±10%
MIN.
TYP.(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
= 2.7V
-
-
5(4)
VI = 0.5V
-
-
-5(4)
VI = GND
-
-
-5
-
-0.7
-1.2
V
-60
-120
-
mA
VHC
Vcc
-
VHC
"cc
-
2.4
4.3
-
SYMBOL
TEST CONDITIONS(l)
PARAMETER
VI = Vcc
IIH
Input HIGH Current
VCC
IlL
Input LOW Current
V,K
Clamp Diode Voltage
Vcc
los
Short Circuit Current
Vcc
Vcc
VOH
Output HIGH Voltage
VI
= Max.
= Min., IN = -18mA
= Max.(3), Vo = GND
= 3V, V,N = VLC or VHC ' 10H = -32 ~
10H
Vcc = Min.
'-'iN = '-'iH or'-'iL
=
10H
=
Vcc = 3V, V,N = VLC or VHC ' 10L
VOL
Output LOW Voltage
Vcc
'-'iN
-300~A
10H = -12mA MIL.
10L
= Min.
= '-'iH or '-'iL
10L
=
=
2.4
4.3
-
= 300~
-
GND
VLC
300~A
-
GND
VLC
-
0.3
0.5
-
0.3
0.5
-15mA COM'L.
32mA MIL.
IOL = 48mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-74
~A
V
V
IDT54/74FCT138/A FAST
CMOS 1-0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V: VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS
PARAMETER
(1)
MIN.
Typ.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
V1N :::: VHC : V1N :::; VLC
fl = 0
-
0.001
1.5
mA
.6.lcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
V1N = 3.4V(3)
-
0.5
2.0
mA
ICCD
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
-
0.15
0.3
mAl
V1N :::: VHC
\IN :::; VLC
(FCT)
-
1.5
4.5
V1N = 3.4V
V1N = GND
-
1.8
5.5
\IN :::: VHC
V1N :::; VLC
(FCT)
-
0.38
2.3(5)
-
0.63
3.3(5)
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
One Input Toggling
Ic
Total Power Supply Current
V1N :::: VHC
\IN :::; VLC
(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
One Input Toggling
V 1N = 3.4V
V1N = GND
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are atVcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-75
MHz
IOT54/74FCT138/A FAST
CMOS 1·0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION
PIN NAMES
Ao - A2
Address Inputs
E1 ,E 2
Enable Inputs (Active LOW)
E3
00 -
Enable Input (Active HIGH)
°
Outputs (Active LOW)
7
TRUTH TABLE
OUTPUTS
INPUTS
E1
E2
E3
Ao
A1
A2
00
01
O2
03
04
05
06
07
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
·H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54/74FCT138
SYMBOL
PARAMETER
tpLH
tpHL
Propagatio'l Delay
Ao to On
tpLH
tpHL
Prgpaga.!.ion Q.elay
El or E 2to On
tpLH
tpHL
PropagatioQ, Delay
E3 to On
CONDITION(1)
CL = 50pF
RL = 500n
TYP!3)
COM'L.
MIN.(2) MAX.
IOT54/74FCT138A
MIL.
MIN!2)
TYP.(3)
MAX.
MAX.
X
Package
UNIT
MAX.
1.5
9.0
1.5
12.0
4.5
1.5
5.8
1.5
7.8
ns
6.0
1.5
9.0
1.5
12.5
4.5
1.5
5.9
1.5
8.0
ns
6.0
1.5
9.0
1.5
12.5
4.5
1.5
5.9
1.5
8.0
ns
ORDERING INFORMATION
XXXX
Device Type
MIN.(2)
7.0
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
IDTXXFCT
Temp. Range
MIL.
COM'L.
MIN.(2)
X
P=~:,aok
Commercial
MIL-STD-883, Class B
L..-._ _ _ _ _ _ _ _--j
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _-j
S10-76
P
D
SO
Plastic DIP
CERDIP
Small Outline IC
E
L
CERPACK
Leadless Chip Carrier
138
138A
1-of-8 Decoder
Fast 1-of-8 Decoder
Intesrated Device1echnology.lnc.
lOT 54/74FCT182
lOT 54/74FCT182A
FAST CMOS
CARRY LOOKAHEAD
GENERATOR
FEATURES:
DESCRIPTION:
• IDT54/74FCT182 equivalent to FAST TMspeed;
IDT54/74FCT182A 30% faster than FAST ™
The IDT54/74FCT182 and IDT54/74FCT182A are high-speed
carry look ahead generators built using advanced CEMOS TM, a
dual metal CMOS technology. The IDT54/74FCT182 and
IDT54/74FCT182A are carry lookahead gene.r.ato~ th~t aC,.gept up
to four pairs of actlYe LQW Q?rry 'propagate (Po, P, , P 2, P 3) and
Carry Generate (Go, G" G 2 , G 3 ) signals and an active HIGH
carry input (Cn) and provides anticipated HIGH carries (Cn+y,
Cn+Z) across four groups of binary as!ders. These products al.§.o
have active LOW Carry Propagate (P) and carry generate (G)
outputs which may be used for further levels of lookahead.
• Equivalent to FAST ™speeds and output drive over full
temperature and voltage supply extremes
•
10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5}JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5}JA max.)
• Carry lookahead generator
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
PIN CONFIGURATIONS
INDEX
G,
P,
Go
Po
G3
P3
P
GND
Vcc
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
U U
3
Go ]4
Po
II U U
U,
1a[ G 2
17 [: C n
L20-2
] a
10-00
DIP/50lC/CERPACK
TOP VIEW
20 19
1
:] 5
NC ]6
G 3 ]7
P3
2
'6[
NC
'5 [:
Cn + x
14 [:
Cn+ y
~ICJ
aZcJ
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC-4008H
510-77
IDT54/74FCT182/A FAST CMOS
CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TS IAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
lOUT
DC Output Current
COMMERCIAL
-0,5 to +7,0
o to
MILITARY
-0,5 to + 7,0
V
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
O,S
0,5
W
120
120
mA
+ 70
SYMBOL
UNIT
(TA= +25°C, f = 1,OMHz)
PARAMETER(1)
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS TYP.
MAX, UNIT
VIN = OV
6
10
pF
VOUT= OV
8
12
pF
NOTE:
1, This parameter is guaranteed by characterization data and not tested,
NOTE:
1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device, This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied, Exposure to absolute maximum rating conditions for extended periods may affect reliability,
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = O,2V; VHC = Vcc - O,2V
Commercial: TA = O°C to + 70°C; 'tc = 5,OV±5%
Military: TA = -55°C to +125°C; Vcc =' S,OV±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN,
Typ.(2)
MAX.
UNIT
"IH
Input HIGH Level
Guaranteed Logic High Level
2,0
-
-
V
"IL
Input LOW Level
Guaranteed Logic Low Level
-
-
0,8
V
VI = 'tc
-
-
S
VI = 2,7V
-
-
5(4)
-
-S(4)
IIH
Input HIGH Current
Vcc = Max,
-
VI = GND
-
-
-S
-
-0,7
-1,2
V
Vcc = Max!3), Vo = GND
-60
-120
-
mA
Vcc = 3V, \IN = VLC orVHC • IOH = -32jJA
VHC
Vcc
-
IOH = -300j./A
VHC
Vcc
-
IOH = -12mA MIL.
2.4
4,3
IOH = -15mA COM'L.
2.4
4,3
-
-
GND
VLC
Input LOW Current
"IK
Clamp Diode Voltage
Vcc = Min" IN = -18mA
los
Short Circuit Current
VOH
Output LOW Voltage
Vcc = Min,
\IN = \lH or\lL
Vcc = 3V,\lN = VLC or VHC • 10L = 300jJA
VOL
Output HIGH Voltage
j./A
VI = O,5V
IlL
Vcc = Min,
\IN = V1H or \lL
10L = 300j./A
-
GND
VLC
10L = 32mA MIL.
-
0,3
O,S
IOL = 48mA COM'L.
-
0,3
0,5
NOTES:
1, For conditions shown as max, or min" use appropriate value specified under Electrical Characteristics for the applicable device type,
2, Typical values are at Vcc = 5,OV, +25°C ambient and maximum loading,
3, Not more than one output should be shorted at one time, Duration of the short circuit test should not exceed one second,
4, This parameter is guaranteed but not tested,
S10-78
V
V
IDT54/74FCT182/A FAST CMOS
CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN 2: VHC ; VIN ::; VLC
fl = 0
Alcc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Total Power Supply Current(5.6)
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
One Bit Toggling
Ic
(1)
MIN.
TVP.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
VIN 2: VHC
'lltN ::; VLC
-
0.15
0.3
mA!
MHz
'lltN 2: VHC
'lltN ::; VLC
(FCT)
-
1.5
4.5
mA
VIN = 3.4V
VIN = GND
-
1.8
5.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-79
---_._.._ - - - . _ - - - - - - - - - - - _ . _ - - - - - - - - - - - . - - - - .
"--"'-'._ ..
_.....
IDT54/74FCT182/A FAST CMOS
CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Cn
DESCRIPTION
. Carry Input
~,G2
Carry Generate Inputs (Active LOW)
<31
~
Carry Generate Input (Active LOW)
Carry Generate Input (Active LOW)
Pa, PI
P2
P3
Cn +x
Carry Propagate Inputs (Active LOW)
Carry Propagate Input (Active LOW)
Carry Propagate Input (Active LOW)
-
Cn + z
G
P
Carry Outputs
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
TRUTH TABLE
OUTPUTS
INPUTS
Cn
Go
Po
X
H
H
H
L
X
H
X
X
L
X
X
H
X
X
X
L
X
X
X
H
L
X
X
X
L
X
H
H
X
H
L
X
X
X
X
L
X
X
X
H
H
X
X
L
X
X
X
H
X
X
X
X
L
X
X
X
O2
01
03
J53
""
Cn+x
Cn+v
Cn + z
G
P
L
L
H J
H
H
H
H
H
L
X
X
X
X
X
L
L
X
H
H
H
X
H
L
X
X
X
X
X
X
L
L
X
X
X
X
X
H
H
H
H
X
X
X
X
X
L
X
L
152
X
X
X
X
L
H
X
X
X
X
X
X
L
L
H
L
L
L
H
H
H
H
H
L
X
X
X
X
X
X
X
L
L
L
H
H
H
X
X
H
H
H
L
X
X
X
X
X
X
L
L
H
X
L
L
L
L
H
H
H
H
X
X
H
H
H
H
H
L
X
X
X
X
X
X
X
L
L
L
X
X
X
H
X
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X == Don't Care
S10-80
H
H
H
H
L
L
L
L
H
H
H
H
L
IDT54/74FCT182/A FAST CMOS
CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT182
SYMBOL
PARAMETER
CONDITION(l)
TYP.(3)
COM'L.
MIN.(2) MAX.
IDT54/74FCT182A
MIL.
MINF)
MAX.
TYP.(3)
COM'L.
MIL.
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
t pLH
t pHL
Propagation Delay
C n to C n+y.
Cn+y. Cn+z
6.0
2.0
10.0
2.0
16.5
4.0
2.0
7.0
2.0
10.7
ns
t pLH
t pHL
Propagation Delay
Po . Pi . ~ . to
Cn+y. Cn+y. Cn+z
6.0
1.5
9.0
1.5
11.5
4.0
1.5
8.5
1.5
9.0
ns
6.0
1.5
9.5
1.5
11.5
4.0
1.5
8.5
1.5
9.0
ns
7.0
2.0
11.0
2.0
16.5
4.8
2.0
7.2
2.0
10.7
ns
7.5
2.0
11.5
2.0
16.5
5.0
2.0
7.6
2.0
10.7
ns
6.0
1.5
8.5
1.5
12.5
4.0
1.5
6.0
1.5
7.4
ns
t pLH
tpHL
pr~a9ation
O.
Delay
<31 , G2 to
Cn+x• Cn+y. Cn+z
tpLH
t pHL
Propa..9ation Delay
P 1 • P2 P3 to G
tpLH
tpHL
Prop~ati0l!Pelay
tpLH
tpHL
Propagation Delay
~ toP
CL = 50pF
RL = 500n
G n to G
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce =5.0V. +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXX)(
X
X
Device Type
Package
Process/
Temperature
R'"y:,"k
Commercial
MIL-STD-883. Class B
'------------1
510-81
- - - _....
- - - - ....__..._..... _----_..
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
182
182A
Carry Lookahead Generator
Fast Carry Lookahead Generator
.t;)
FAST CMOS OCTAL
BUFFER/LINE DRIVER
Integrated Device1echnoIogy. Inc.
lOT 54/74FCT240
lOT 54/74FCT240A
FEATURES:
DESCRIPTION:
• IDT54/74FCT240 equivalent to FAST™speed;
IDT54/74FCT240A 30% faster than FAST ™
• Equivalent to FAST ™output drive over full temperature and
voltage supply extremes
•
10L = 64mA (commercial) and 48mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5jJA max.)
• Octal buffer/line driver with 3-state output
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87655 is listed on this
function.
The IDT54/74FCT240/A are octal buffer/line drivers built using
advanced CEMOS TM, adual metal CMOS technology. The devices
are designed to be employed as memory and address drivers,
clock drivers and bus-oriented transmitter/receivers which provide
improved board density.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
OEA
Vee
DAo
OEB
080
0Aa
OE'A-----a
DBo
DAl
OB 1
OE B
CAl
DBl
DA2
082
CA2
DB2
CA3
DA3
083
DAo
CA o
OBo
DBo
DAl
CAl
OB 1
DBl
DA2
OA 2
OB 2
DB2
DA3
OA 3
OB 3
DB3
DB3
GND
DIP/SOIC/CERPACK
TOP VIEW
~cr~~~
INDEX
LJU"UU
3 2 Ll 20 19
DAl
:J 4
18 [:
CEil
]5
17 [:
DA2
:J 6
002
DA3
l20-2
16
c:
CAo
DBo
OA 1
]7
15 [:
:J 8
DBl
14 [:
OA 2
~~~(4~
~Om~a5"
t§ 0
0
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Inlegraled Device Technology. Inc.
JANUARY 1989
DSC-4013/-1
S10-82
IDT54/74FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS(1)
RATING
SYMBOL
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
COMMERCIAL
-0.5 to +7.0
o to
MILITARY
-0.5 to +7.0
V
-55 to +125
°C
-55 to +125
-65 to + 135
°C
-55 to +125
-65 to +150
°C
+70
SYMBOL
UNIT
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
COUT
Output Capacitance
CONDITIONS TYP,
MAX.
UNIT
VIN = OV,
6
10
pF
VOUT= OV
8
12
pF
NOTES:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military: TA = -55°C to +125°C' Vee = 50V +10%
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
~L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
IIH
Input HIGH Current
-
-
5(4)
VI
Vee
IlL
VI
= Max.
-
-
= GND
= Vee
= 2.7V
-
-
-5
-
-
10
-
-
10(4)
-
-
-10(4)
-
-0.7
-1.2
V
-60
-120
-
mA
VHC
Vcc
-
10H = -3OOIJA
VHC
Vcc
-
= -12mA MIL.
10H = -15mA COM'L.
or VHC ' 10L = 300IJA
2.4
4.3
-
VI
Vo
Vo
Off State (High Impedance)
Output Current
Vee
~K
Clamp Diode Voltage
Vee
los
Short Circuit Current
Vcc
Vcc
VOH
Output HIGH Voltage
Vcc
VOL
= Max.
Vo = 0.5V
Vo = GND
= Min., IN = -18mA
= Max!3), Vo = GND
= 3V, "iN = VLC or VHC ' 10H = -32J-lA
Vcc = Min.
"iN = VIH or "iL
10H
= 3V, "iN = VLC
10L
VCC = Min.
"iN = "i;or"iL
Output LOW Voltage
IJA
VI = 0.5V
_5(4)
Input LOW Current
loz
= Vee
= 2.7V
=
300J-lA
10L = 48mA MIL.
10L
= 64mA COM'L.
-
-10
2.4
4.3
-
-
GND
VLC
-
GND
VLC
-
0.3
0.55
0.3
0.55
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-83
- - - - - - - - , - - _......_-
IJA
V
V
IDT54/74FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER
SUPPLY CHARACTERISTICS FOR 'FCT240
/'
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS(1)
MIN.
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ;::: VHC ; VjN :5 VLC
fl = 0
-
0.001
1.5
mA
Alcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
OEA = OE B = GND
One Input Toggling
50% Duty Cycle
VjN ;::: VHC
VjN :5 VLC
-
0.15
0.25
VjN ;::: VHC
VjN :5 VLC
(FCT)
-
1.5
4.0
VjN = 3.4V
VIN = GND
-
1.8
5.0
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50% DI:!!Y..Cycie
OEA = OE B = GND
One Bit Toggling
Ic
mAl
MHz
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50%DI:!!Y..Cycle
OEA = OE B = GND
Eight Bits Toggling
VjN ;::: VHC (6)
VjN :5 VLC
(FCT)
-
3.0
6.5(5)
VIN = 3.4V(6)
VIN = GND
-
5.0
14.5(5)
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Valu~,s for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
.
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH '
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.'
S10-84
IDT54/74FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION
PIN NAMES
INPUTS
OEA• OE B
3-State Output Enable Input (Active LOW)
OEA , OE B
Dxx
Inputs
Oxx
Outputs
H
L
X
z
OUTPUT
D
L
L
H
L
H
L
H
X
Z
= HIGH Voltage Level
= LOW Voltage Levol
= Don't Care
= High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT240A
IDT54/74FCT240
SYMBOL
PARAMETER
tpLH
tpHL
Propagation Delay
Dn to On
tpZH
tpZL
Output Enable
Time
tpHz
tpLZ
Output Disable
Time
CON DITION (1)
C L = 50pF
RL = 500n
COM'L
TYP,(3)
MIN,(2) MAX,
MIL
TYP.!3)
MINl2) MAX,
COM'L
MIN,(2)
MIL
UNIT
MAX.
MIN.(2)
MAX.
5.0
1.5
8.0
1.5
9.0
3.5
1.5
4.8
1.5
5·1
ns
7.0
1.5
10.0
1.5
10.5
4.8
1.5
6.2
1.5
6.5
ns
6.0
1.5
9.5
1.5
12.5
4.3
1.5
5.6
1.5
5.9
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
A
Device Type
X
Package
Commercial
MIL-STD-883, Class B
P
D
' - - - - - - - - - - - - 1 SO
L
E
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _--1 240
240A
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-154
74
S10-85
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Inverting Octal Buffer/Line Driver
Fast Inverting Octal Buffer/Line Driver
-55°C to +125°C
O°C to + 70°C
t;J
FAST CMOS OCTAL
BUFFER/LINE DRIVER
Integrated DevIce~Inc.
lOT 54/74FCT241/A
lOT 54/74FCT244/A
FEATURES:
DESCRIPTION:
• IDT54/74FCT241/244 equivalent to FAST™speed
t
IDT54/74FCT241A/244A 35% faster than FAST M
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
• IOL = 64mA (Commercial), 48mA (Military)
• CMOS power levels (5j.1W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5j.1A max.)
• Octal buffer/line driver with 3-state output
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
• Standard Military Drawing# 5962-87630 is listed on this function. Refer to Section 2/page 2-4.
The IDT54/74FCT241/244 and IDT54/74FCT241A/244A are octal buffer/line drivers built using advanced CEMOS TM, a dual metal
CMOS technology. The devices are designed to be employed as
memory and address drivers, clock drivers and bus-oriented transmitter/ receivers which provide improved board density.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
~A
Vcc
DAo
OBo
DAI
OBI
DA2
OB2
DA3
OB3
GND
~s*
OAo
DBo
OA 1
DBI
OA 2
DB2
OA 3
DB3
~A - - - - - - - - 0
OE:s *
c8
0
L..J
< o
o
3 2
I
L..I
]4
]
I
1
m
DBo
DAI
OA 1
OBI
DBI
DA2
OA 2
OB2
DI3z
DA3
OA 3
08 3
DB3
20 19
5
DA2 ]6
OB2 ]7
DA3 ]8
OBo
DEs for 'FCT244
td~ ~~
..... .....
.....
OAo
*Q§ for 'FCT241
DIP/SOIC/CERPACK
TOP VIEW
INDEX
DAo
18 [:
17 [:
L20-2
~~fi~fi
16 [:
15 [:
14 [
OAo
DBo
OA 1
DBI
OA 2
arO m.?rii'
0 2 0 00
(!)
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integraled Device Technology.
Inc.
S10-86
JANUARY 1989
DSC-4020/-1
IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS(1)
RATING
SYMBOL
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
COMMERCIAL
-0.5 to +7.0
o to
MILITARY
-0.5 to +7.0
V
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to + 125
-65 to +150
°C
+70
SYMBOL
UNIT
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS TYP.
C IN
Input Capacitance
COUT
Output Capacitance
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMU,M RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V: VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C: Vcc = 5.0V±5%
Military: TA = -55°C to +125°C: Vcc = 5.0V±10%
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
-
-
5
VI = 2.7V
-
VI = 0.5V
-
-
Guaranteed Logic Low Level
ilL
Input LOW Current
-
Vo = 2.7V
Vo = 0.5V
-
Vo = GND
-
-
-10
-
-0.7
-1.2
V,
-60
-120
mA
Vcc = 3V, VIN = VLC orVHC • 10H = -32jJA
VHC
Vcc
-
IOH = -300~A
VHC
Vcc
-
IOH = -12mA MIL.,
2.4
4.3
IOH = -15mA COM'L.
2.4
4.3
-
GND
VLC
IOL = 300~A
-
GND
VLC
10L = 48mA MIL.
-
0.3
0.55
-
0.3
0.55
-
200
-
\lK
Vcc = Min., IN = -18mA
los
Short Circuit Current
Vcc = MaxP), Vo = GND
Vcc = Min.
\IN = VIH or \lL
Vcc = 3V, \IN = VLC or VHC • IOL = 300jJA
VH
Input Hysteresis on Clock Only
-5
10
10(4)
Clamp Diode Voltage
Output LOW Voltage
~A
_10(4)
Vcc = Max.
VOL
5(4)
_5(4)
-
Off State (High Impedance)
Output Current
Output HIGH Voltage
VI = GND
Vo = Vcc
V
-
loz
VOH
V
VI = Vcc
\lL
Input LOW Level
Vcc = Max.
UNIT
-
0.8
2.0
Input HIGH Current
MAX.
-
\lH
Guaranteed Logic High Level
IIH
TYP.(2)
-
Input HIGH Level
Vcc = Min.
\IN = \lH or \lL
10L = 64mA COM'L.
-
~A
V
mV
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-87
" " " - - , - - ,..
,'--,-"'--------------
---------
-----------
IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS FOR 'FCT241
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
'.
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; ~N ~ VLC
fl = 0
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
OEA = OE B = GND
One Input Toggling
50% Duty Cycle
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OEA = OE B = GND
One Bit Toggling
Ic
MIN.
TYP.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
~N ~ VHC
"'IN ~ VLC
-
0.15
0.25
mAl
'MHz
"'IN ~ VHC
"'IN ~ VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN = GND
-
1.8
5.0
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OEA = OE B = GND
Eight Bits Toggling
"'IN ~ VHC (6)
"'IN ~ VLC
(FCT)
-
3.0
6.5(5)
VIN = 3.4V(6)
~N = GND
-
5.0
14.5(5)
NOTES:
1. Forconditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these 'conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPLrrS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
'fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-88
IDT54/74FCT241A AND IDT54174FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS FOR 'FCT244
VLC = 0.2V: "HC = VCC - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1),
Icc
QUiescent Power Supply Current
Vec = Max.
VIN ~ VHC : '-"N :S VLC
fl = 0
~Iec
QUiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
OEA = DEB = GND
One Input Toggling
50% Duty Cycle
IceD
Vcc = Max.
Outputs Open
fl = 10MHz
50% Dy!y"Cycle
OEA = DEB = GND
One Bit Toggling
Ic
'-"N ~ VHC
~N :S VLC
~N ~ VHC
~N :S VLC
TYP.(2)
MAX.
-
0.001
1.5
mA
-
0.5
2.0
mA
-
0.15
0.25
mAl
MHz
-
1.5
4.0
-
1.8
5.0
MIN.
UNIT
(FCT)
VIN = 3.4V
~N = GND
mA
Total Power Supply Current(6)
~N ~
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Dy!y"Cycle
OEA = OE B = GND
Eight Bits Toggling
VHC (6)
~N :S VLC
(FCT)
-
3.0
6.5(5)
VIN = 3.4V(6)
VIN = GND
-
5.0
14.5(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input ~N = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. ,
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
,
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-89
IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
OEA, OE~l)
TRUTH TABLE FOR 'FCT241
INPUTS
DESCRIPTION
PIN NAMES
OUTPUT
D
OE B
OE A•
3-State Output Enable Input (Active LOW)
Dxx
Inputs
L
H
L
L
Oxx
Outputs
L
H
H
H
NOTE:
1. For' FCT241 use 0 Ea , and for 'FCT244 use 'O'E'So
H
L
X
Z
TRUTH TABLE FOR 'FCT244
INPUTS
L
L
L
L
H
H
X
Z
H
HIGH Voltage Level
LOW Voltage Level
H
L
OUTPUT
D
OEA.OEa
X
Z
Don't Care
High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FCT241
IDT54/74FCT241A (4)
IDT54/74FCT241
SYMBOL
I
,'"
PARAMETER
tplH
tpHl
Propagation Delay
On to On
tpZH
tpZl
Output Enable
Time
tpHZ
tpLZ
Output Disable
Time
CONDITION(l)
Cl = 50pF
Rl = 5000
COM'L.
TYP.(3)
MIN.(2) MAX.
MIL.
MIN~2)
TYP,(3)
MAX.
COM'L
MIN.(2)
MIL
UNIT
MAX.
MIN.(2)
MAX.
4.0
1.5
6.5
1.5
7.0
3.0
1.5
4.8
1.5
5.1
ns
5.5
1.5
8.0
1.5
8.5
4.0
1.5
6.2
1.5
6.5
ns
4.5
1.5
7.0
1.5
7.5
3.0
1.5
5.6
1.5
5.9
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
4. These numbers are preliminary only.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FCT244"
IDT54/74FCT244
SYMBOL
PARAMETER
tpLH
t pHl
Propagation Delay
On to On
tpZH
tpZl
Output Enable
Time
t pHZ
tpLZ
Output Disable
Time
CONDITION(l)
Cl = 50pF
Rl = 5000
TYP.(3)
COM'L
MIN.(2) MAX.
IDT54/74FCT244A
MIL
MIN~2)
MAX.
TYP!3)
COM'L
MIN.(2)
MAX.
MIL
MIN.(2)
UNIT
MAX.
4.5
1.5
6.5
1.5
7.0
3.1
1.5
4.8
,1.5
5.1
ns
6.0
1.5
8.0
1.5
8.5
3.8
1.5
6.2
1.5
6.5
ns
5.0
1.5
7.0
1.5
7.5
3.3
1.5
5.6
1.5
5.9
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
S10-90
IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temp. Range
A
Device Type
X
Package
X
Process
I ..
I Blank
~B
~
________________________________________
~
S10-91
Commercial
MIL-STO-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
241
241A
244
244A
Octal Buffer/Line Driver
Fast Octal Buffer/Line Driver
Octal Buffer/Line Driver
Fast Octal Buffer/Line Driver
54
-55°Cto+125°C
74
O°C to + 70°C
Intesrated Device1echnoIogy.1nc.
FAST CMOS
NON-INVERTING
BUFFER TRANSCEIVER
lOT 54/74FCT245
lOT 54/74FCT245A
FEATURES:
DESCRIPTION:
• IDT54/74FCT245 equivalent to FAST™speed;
IDT54/74FCT245A 35% faster thari FAST ™
• Equivalent to FAST TMoutput drive over full temperature
and voltage supply extremes
• 10L = 64mA (commercial) and 48mA (military) for both ports
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST Tht (5~A max.)
• Non-inverting buffer transceiver
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
• Standard Military Drawing# 5962-87629 is listed on this function. Refer to Section 2/page 2-4.
The IDT54/74FCT245 and IDT54/74FCT245A are 8-bit noninverting, bidirectional buffers built using advanced CEMOS T~ a
dual metal CMOS technology. These bidirectional buffers have
3-state outputs and are intended for bus-oriented applications. The
Transmit/Receive (T/R) input determines the direction of data flow
through the bidirectional transceiver. Transmit (active HIGH)
enables data from A ports to 8 ports. Receive (active LOW) enables
data from 8 ports to A ports. The Output Enable (OE) Input, when
HIGH, disables both A and 8 ports by placing them in High Z
condition.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
TItl
Ao
Al
A2
A3
A4
A5
As
A7
GND
Vcc
TItl
~
80
81
82
83
84
85
(19)
Ao
Al
(3)
Be
A2
0
(15)
~
A4
A7
GND
87
Be
85
3 2 U 20 19
1
18 [:
17 [:
le [:
L20-2
15 [:
14 [:
9 10 11 12 13
B2
(5)
B3
(6)
LJUIIULJ
]4
]5
]e
]7
]8
Bl
(4)
(16)
A3
ICr
So
(17)
Br
-- 0 ........ 0
«I-'>
~
(2)
(18)
DIP/SOIC/CERPACK
TOP VIEW
INDEX
(1)
(14)
Al
Ao
A5
B4
(7)
(13)
T/R
Ae
Vcc
B5
(8)
~
Be
(9)
nnnnn
A7
(11)
Br
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-4021/1
S10-92
IDT54/74FCT245/A FAST CMOS
NON-INVERTING BUFFER TRANSCEIVER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-0.5 to +7.0
Terminal Voltage
VTERM (3) with Respect to
GND
-0.5 to Vee
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
-0.5 to Vcc
UNIT
SYMBOL
CIN
V
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
VOUT= OV
pF
CliO
I/O Capacitance
8
12
NOTE:
1. This parameter is measured at characterization but not tested.
V
TA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
120
DC Output Current
120
mA
lOUT
NOTES:
1. Stresses greater thanthose listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Inputs and Vcc terminals only.
3. Outputs and 1/0 terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military'TA = -55°C to + 125°C' Vcc = 50V -+10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
"IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
"IL
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
5
VI = Vcc
-
VI = 2.7V
-
VI = 0.5V
-
VI = GND
IIH
VI = Vcc
I~ut HIGH Current
( xcept I/O pins)
VI = 2.7V
Vcc = Max.
IlL
VI = 0.5V
I~ut LOW Current
( xcept I/O pins)
VI = GND
-
5(4)
-5(4)
J-IA
-5
15
IIH
Input HIGH Current
(I/O pins only)
IlL
Input LOW Current
(I/O pins only)
-
-
-15
"IK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
-
-0.7
-1.2·
V
los
Short Circuit Current
Vcc = MaxP), Vo = GND
-60
-120
mA
Vcc = Max.
VOL
Output HIGH Voltage
Output LOW VOltaye
(Port A and Port B
Vcc = Min.
\'IN = \'IH or\'lL
-15(4)
VHC
Vcc
-
IOH =-300J-lA
VHC
Vcc
-
IOH = -12mA MIL.
2.4
4.3
-
IoH = -15mA COM'L.
Vcc = 3V, \'IN = VLC or VHC , 10H = -32J-1A
VOH
15(4)
2.4
4.3
-
Vcc = 3V, \'IN = \tc or VHC ' IoL = 300J-lA
-
GND
VLC
IOL = 300J-lA
-
GND
VLC
0.3
0.55
0.3
0.55
Vcc = Min.
\'IN = \'IH or\'lL
IoL = 48mA MIL.
IoL = 64mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-93
J-IA
V
V
IDT54/74FCT245/A FAST CMOS
NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS(1)
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN 2: VHC ; '-"N ::; VLC
fl = 0
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
BE = GND
T/~ = GND or Vcc
One Input Toggling
50% Duty Cycle
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50.Jo DI:!!Y. Cycle
T/R = OE = GND
One Bit Toggling
Ic
MIN.
TYP.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
"'N ~ VHC
"'N ::; VLC
-
0.15
0.25
"'N 2: VHC
"'N ::; VLC
(FCT)
-
1.5
4.0
-
1.8
5.0
. "'N 2: VHC (6)
"'N ::; VLC
(FCT)
-
3.0
6.5(5)
= 3.4V (6)
= GND
-
5.0
14.5(5)
VIN
VIN
= 3.4V
= GND
Total Power Supply Current(6)
mAl
MHz
mA
Vcc = Max.
Outputs Open
fl = 2.5MHz
50.Jo DI:!!Y. Cycle
T/R = OE = GND
Eight Bits Toggling
VIN
V1N
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN. = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHN r + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of.TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-94
IDT54/74FCT245/A FAST CMOS
NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OE
DESCRIPTION
Output Enable Input (Active LOW)
T/R
INPUTS
OE
TransmiVReceive Input
Ao-A7
Side A Inputs or 3-State Outputs
Bo-B7
Side B Inputs or 3-State Outputs
OUTPUTS
T/R
L
L
L
H
Bus A Data to Bus B
H
X
High Z State
Bus B Data to Bus A
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT245A
IDT54/74FCT245
SYMBOL
PARAMETER
CONDITION(1)
COM'L
Typ.(3)
MIN.(2) MAX.
MIL
COM'L
TYP.(3)
MIN~2)
MAX.
MIN.(2)
MIL.
UNIT
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
A to B, Bto A
5.0
1.5
7.0
1.5
7.5
3.3
1.5
4.6
1.5
4.9
ns
tpZH
tpZL
Output Enable Time
DE to A or B
6.0
1.5
9.5
1.5
10.0
4.8
1.5
6.2
1.5
6.5
ns
tpHZ
tpLZ
Output Disable Time
OEtoAor B
6.0
1.5
7.5
1.5
10.0
4.5
1.5
5.0
1.5
6.0
ns
tpzH
tPZL
Output Enable Time
T/R to A or B(4)
6.0
1.5
9.5
1.5
10.0
4.8
1.5
6.2
1.5
6.5
ns
tpHZ
t pLZ
Output EnableTime
T/R to A or B(4)
6.0
1.5
7.5
1.5
10.0
4.5
1.5
5.0
1.5
6.0
ns
CL = 50pF
RL = 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
4. This parameter is guaranteed but not tested.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
xxxx
Device Type
Commercial
MIL-STD-883, Class B
L..-------------1
P
D
SO
L
E
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _--1 245
245A
L..----------------------t
S10-95
54
74
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-inverting Buffer Transceiver
Fast Non-inverting Buffer Transceiver
-55°C to +125°C
O°C to + 70°C
t;)
FAST CMOS
OCTAL'D FLIP-FLOP
WITH CLEAR
Integrated Device~Inc.
lOT 54/74FCT273
lOT 54/74FCT273A
FEATURES:
DESCRIPTION:
• IDT54/74FCT273 equivalent to FAST™ speed;
IDT54/74FCT273A 45% faster than FAST ™
• Equivalent to FAST ™ output drive over full temperature
and voltage supply extremes
•
10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5JJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• Octal D flip-flop with clear
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87656 is listed on this
function. Refer to Section 21page 2-4.
The IDT54/74FCT273 and IDT54/74FCT273A are octal D flipflops built using advanced CEMOS TM, a dual metal CMOS technology. The IDT54/74FCT273 and IDT54/74FCT273A have eight
edge-triggered D-type fl ip-flops with individual D inputs and 0 outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state ofeach D input,
one set-up time before the LOW-to-HIGH clock tranSition, is transferred to the corresponding flip-flop's 0 output.
All outputs will be forced LOW in~endently of Clock or Data
inputs by a LOW voltage level on the M R input. The device is useful
for applications where the true output only is. required and the
Clock and Master Reset are common to all storage elements.
PIN CONFIGURATIONS
MR
Vcc
00
Do
D1
°1
°2
D2
D3
03
GND
o
INDEX
°7
D7
D6
06
Os
Ds
D4
0
Cl 0
~
>8 0...
ULJIILlU
D1 ]4
°1 ]s
0.! ]6
D2 ]7
D3 :] 8
04
3 2 U 20 19
1
18 [: D7
17 [: D6
16 [: 0 6
l20-2
1S [: Os
14 [: Ds
9 10 11 12 13
nnnnn
CP
o@fjoo
(!)
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
Do
D1
D2
D3
D4
Ds
D6
D7
CP
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1989
DSC-401S/-1
© 1989 In1egrated Device Technology. Inc.
S10-96
IDT54/74FCT273/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect te
GND
CAPACITANCE
(1)
COMMERCIAL
-0.5te +7.0
MILITARY
-0.5te +7.0
UNIT
SYMBOL
CIN
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS TYP,
VIN = OV
MAX, UNIT
6
10
pF
12
8
pF
COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; ~e = Vcc - .2
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military: TA = -55°C te + 125°C; Vee = 5.0V ±10%
SYMBOL
"'H
"'L
TEST CONDITIONS (1)
PARAMETER
TYP.(2)
MAX.
UNIT
-
-
V
0.8
V
Input HIGH Level
Guaranteed Logic High Level
2.0
Input LOW Level
Guaranteed Logie Low Level
VI = \be
IIH
MIN.
Input HIGH Current
VI = 2.7V
Vee = Max.
VI = 0.5V
-
-
-5
-0.7
-1.2
V
mA
5
5(4)
-5(4)
IlL
Input LOW Current
VIK
Clamp Diode Voltage
'Icc = Min., IN = -18mA
los
Short Circuit Current
'Icc = MaxP), Vo = GND
-60
-120
Vcc = 3V, \'IN = VLC or VHe , 10H = -32~A
VHC
Vcc
-
VOH
Output HIGH Voltage
VI = GND
VHC
Vce
-
10H = -12mA MIL.
2.4
4.3
-
10H= -15mA COM'L.
2.4
4.3
-
-
GND
VLC
GND
\tc
0.3
0.5
0.3
0.5
200
-
IOH
Vec = Min.
\'IN = \'IHorVIL
=
-300~A
Vcc = 3V, VIN = VLC or VHC , IoL = 300~A
VOL
10L = 300~A
Output LOW Voltage
Vee = Min.
\'IN = \'IH or\'lL
10L = 32mA MIL.
10L = 48mA COM'L.
VH
-
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-97
~A
V
V
mV
IDT54/74FCT273/A FAST CMOS
OCTAL ~ FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
-
v LC -- 0 2V' vHC - vcc - 0 2V
SYMBOL
TEST CONDITIONS
PARAMETER
Icc
Quiescent Power Supply Current
Vcc = Max;
'-'iN ;::: VHC : '-'iN :5 VLC
fcp = fl = 0
~Icc
Power Supply Current Per TIL
Inputs HIGH
Vcc = Max.
'-'iN = 3.4V(3)
Dynamic Power Supply Current (4)
ICCD
tvcc = Max.
Outputs Open
FlR = Vcc
One Bit Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp= 10MHz.
50% Duty Cycle
MR = Vcc
One BitToggling
at fl = 5MHz
50% Duty Cycle
MIN.
(1)
TYP.(2)
MAX.
-
0.001
1.5
mA
-
0.5
2.0
mA
'-'iN ;::: VHC
'-'iN :5 VLC
-
0.15 .
0.25
mA/MHz
'-'iN;::: VHC
'-'iN :5 VLC
(FCT)
-
1.5
4.0
'-'iN = 3.4V
or
'-'iN = GND
-
2.0
6.0
Total Power Supply Current (6)
Ic
UNIT
mA
Vcc = Max.
Outputs Open
fcp= 10MHz,
50% Duty Cycle
MR = Vcc
Eight Bits Toggling
fl = 2.5MHz
50% Duty Cycle
'-'iN;::: VHC
'-'iN :5 VLC
(FCT)
-
3.75
. 7.S(5)
'-'iN = 3.4V
or
'-'iN= GND
-
6.0
16.8(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD == Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency ,for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at 11
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Do - D7
Data Inputs
MR
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
00
-
0
7
TRUTH TABLE
DESCRIPTION
Data Outputs
INPUTS
OPERATING MODE
OUTPUT
MR
CP
~
Reset (Clear)
L
X
X
L
Load '1'
H
i
i
h
H
Ot.!
Load '0'
H
I
L
H = HIGH voltage steady state
h = HIGH voltage level one set-uptime prior to the LOW-to-HIGH cl~ck'
transition
.
L = LOW voltage level steady rate
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don't Care
i = LOW-to-HIGH clock transition
S10-98
IDT54/74FCT273/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT273
SYMBOL
PARAMETER
CONDITION(1)
TYP.(3)
COM'L
MIN.(2) MAX.
I DT54/74 FCT273A
MIL
MIN~2)
TYP.(3)
MAX.
COM'L
MIN.(2)
MAX.
MIL
MIN.(2)
UNIT
MAX.
tpLH
tpHL
Propagation Delay
Clock to Output
7.0
2.0
13.0
2.0
15.0
5.0
2.0
7.2
2.0
8.3
n.s
tpLH
tpHL
Propagation Delay
MR to Output
8.0
2.0
13.0
2.0
15.0
5.0
2.0
7.2
2.0
8.3
ns
tsu
Set-up Time
HIGH or LOW
Data to CP
3.0
3.0
-
3.5
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
Data to CP
1.0
2.0
-
2.0
-
1.0
1.5
-
1.5
-
ns
tw
Clock Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
3.0
6.0
-
6.0
-
ns
4.0
7.0
-
7.0
-
3.0
6.0
-
6.0
-
ns
3.0
4.0
-
5.0
-
1.5
2.0
-
2.5
-
ns
CL = 50pF
RL = 500n
'MR Pulse Width
tw
HIGH or LOW
tREM
Recovery Time
fVfR to CP
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
Commercial
MIL-STD-883, Class B
P
D
L - - - - - - - - - - - - - l SO
L
E
'--_ _ _ _ _ _ _--'-_ _ _ _ _ _--1 273
273A
S10-99
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Octal D Flip-Flop w/Clear
Fast Octal D Flip-Flop w/Clear
lOT 54/74FCT299
lOT 54/74FCT299A
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
Integrated Device1echnoIogy.1nc.
FEATURES:
DESCRIPTION:
• IDT54174FCT299 equivalent to FAST™speed;
IDT54/74FCT299A 25% faster than FAST ™
• . Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military).
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• . CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• a-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-86862 is listed on this
function. Refer to Section 2/page 2-4.
The IDT54174FCT299 and IDT54174FCT299A are built using
advanced CEMOS TM, a dual metal CMOS technology. The
IDT54174FCT299 and IDT54174FCT299A are 8-input universal
shift/storage registers with 3-state outputs. Four modes of operation are possible; hold (store), shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional outputs are
provided for flip-flops 00-07 to allow easy serial cascading. A
separate active LOW Master Reset is used to reset the register.
PIN CONFIGURATIONS
~~
INDEX
0
elf >0
~
CI)
UUI;ULJ
3
U
2
20 19
1
110 6 :J 4
110 4 :]5
110 2 ] 6
110 0 ]7
0 0 :J 8
L20-2
18 [:
DS 7
17 [:
07
1/0 7
110 5
110 3
16 [:
15 [:
14 [:
9
10 11
12 13
nnnnn
DIP/SOIC/CERPACK
TOP VIEW
.
~ zC/)o
0
0
a..
(!lo
g
FUNCTIONAL BLOCK DIAGRAM
SI
LCC
TOP VIEW
So
m~
0
D SO
CP
I
A
~Co:
00
R
--4>
1-0
2 -----'
r Ir -~
Ir Ir c-~
~
Illr ~ -, Illr ~
~9fI~~
~ [tr
CP
I
r\7
L
I
~Co:
A
CP
r - "l
ib
I b
I I~Co: I I~Co: I
t-- r\7t-110
CP
CP
r\7
t--
r\7
t--
0
I b
~Co:
r\7
CP
I
t--
~~>-r r;:-
~~~
r-"l
I b
~Co:
r\7
CP
I
t-1/0
5
I b
~Co:
&
CP
I )..
I rlCo : I
CP
t--
1106
1
11/07
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
OSC-4016/-1
S10-100
IDT54/74FCT299/A FAST CMOS
8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
RATING
SYMBOL
COMMERCIAL
UNIT
MILITARY
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to + 125
-65to+135
°C
Tsm
Storage
Temperature
-55 to +125
-65 to +150
°C
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
CIN
V
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS TYP.
Input Capacitance
VIN = OV
MAX. UNIT
6
10
pF
VOUT= OV
8
I/O Capacitance
12
pF
CliO
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C;
= 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
'tc
SYMBOL
"'H
VIL
TEST CONDITIONS(1)
MAX.
UNIT
Guaranteed Logic High Level
2.0
-
-
V
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
5
VI = 2.7V
-
-
5(4)
VI = 0.5V
-
-
-5(4)
VI = GND
-
-
-5
15
PARAMETER
IIH
Irrxut HIGH Current
( xcept I/O pins)
IlL
Irrxut LOW Current
( xcept I/O pins)
IIH
Infcut HIGH Currents
(I 0 pins only)
VI
Vcc = Max.
"'K
los
Infcut LOW Currents
(I 0 pins only)
Clamp Diode Voltage
Vcc = Min., IN = -18mA
Short Circuit Current
Vcc
=
=
Vcc
-
-
-
-
15(4)
VI = 0.5V
-
-
_15(4)
VI = GND
-
-
-15
=
Vee
Output HIGH Voltage
Vcc = Min.
"'N = VIH or VIL
Output LOW Voltage
VCC = Min.
"'N = "'Hor"'L
-0.7
-1.2
V
-120
-
mA
VHC
Vec
.:...
10H = -300~A
VHc
Vee
-
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
GND
VLC
10L = 300~A
-
GND
VLC
10L = 32mA MIL.
-
0.3
0.5
-
0.3
0.5
10L
=
48mA COM'L.
VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-101
~A
-
Vee = 3V, "'N = VLC orVHC , 10L = 300~
VOL
~A
-60
MaxP), Vo = GND
Vee = 3V, VIN = VLC or VHC , 10H = -32 ~
VOH
MIN.
VI = 2.7V
VI
Vec = Max.
IlL
TYP.(2)
Input HIGH Level
-
V
V
mV
IDT54/74FCT299/A FAST CMOS
8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; ~N
fcp = fl = 0
.o.lcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN
3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
OE, = OE2 = GND
MR = Vcc
So = S, = Vcc
DS o = DS, = GND
One Bit Toggling
50% Duty Cycle
ICCD
Ic
TVP.(2)
MAX.
-
0.001
1.5
mA
-
0.5
2.0
mA
~N ~ VHC
~N S VLC
-
0.15
0.25
mA!
MHz
\'IN ~ VHC
\'IN S VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN = GND
-
2.0
6.0
TEST CONDITIONS(1)
PARAMETER
s
VLC
=
Vcc = Max.
Outputs Open
fcp= 1.0MHz
50% D\;!!yCycle
OE, = OE:! = GND
MR = Vcc
So = S, = Vcc
DSo = DS 7 = GND
One Bit Toggling
atfl = 5MHz
50% Duty Cycle
MIN.
Total Power Supply Current(6)
mA
Vcc ;; Max.
Outputs Open
fcp= 10MHz
50% Du,!LCycle
OE, = OE2 = GND
MR
Vcc
Sa = S, = Vcc
DSa = DS7 = GND
Eight Bits Toggling
atfl = 2.5MHz
50% Duty Cycle
\'IN <:: VHC
\'IN S VLC
(FCT)
-
3.75
7.8(5)
VIN = 3.4V
VIN = GND
-
6.0
16.8(5)
=
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2.
3.
4.
5.
6.
UNIT
Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .o.lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.o.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-102
IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
INPUTS
DESCRIPTION
PIN NAMES
CP
Clock Pulse Input (Active Edge Rising)
DS o
Serial Data Input for Right Shift
RESPONSE
MR
S1
So
CP
L
X
X
'x
Parallel Load; I/O -+Qn-+Q n
Asynchronous Reset QO -Q 7 = LOv..
DS 7
Serial Data Input for Left Shift
H
H
H
I
SO,S7
Mode Select Inputs
H
L
H
I
Shift Right; DS o -+Q o • Q O-+Ql • etc
MR
Asynchronous Master Reset Input (Active LOW)
H
H
L
I
Shift Left; DS 7 -+Q7. Q7-+ Q 6. etc.
DEI' OE 2
1/00 - 1/0 7
3-State Output Enable Inputs (Active LOW)
H
L
L
X
Hold
Qo • Q 7
Serial Outputs
Parallel Data Inputs or 3-State Parallel OutputS
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT299A
IDT54/74 FCT299
SYMBOL
PARAMETER
CONDITION(l)
COM'L.
TYP.(3)
MIN.(2) MAX.
MIL.
TYP.(3)
MIN52) MAX.
COM'L.
MIL.
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
CPto Qo or Q 7
7.0
2.0
10.0
2.0
14.0
5.0
2.0
7.2
2.0
9.5
ns
tpLH
tpHL
Propagation Delay
CP to I/On
6.0
2.0
12.0
2.0
12.0
5.0
2.0
7.2
2.0
9.5
ns
tpHL
Propagation Delay
MAto Q o or Q7
7.0
2.0
10.0
2.0
10.5
5.0
2.0
7.2
2.0
9.5
ns
t pHL
Propagation Delay
MAto I/On
7.0
2.0
15.0
2.0
15.0
6.0
2.0
8.7
2.0
11.5
ns
tpZH
tpZL
Output Enable Time
~tol/On
8.0
1.5
11.0
1.5
15.0
5.5
1.5
6.5
1.5
7.5
ns
tpHZ
tpLZ
Output Disable Time
C5Eto I/On
5.5
1.5
7.0
1.5
9.0
4.0
1.5
5.5
1.5
6.5
ns
tsu
Set-upTime
HIGH or LOW
So orSl to CP
2.0
7.5
-
7.5
-
2.5
3.5
-
4.0
-
ns
tH
Hold Time
HIGH or LOW
So or Sl to CP
0
1.0
-
1.0
-
-1.5
1.0
-
1.0
-
ns
tsu
Set-up Time HIGH
or LOW I/On.
DSo or DS 7 to CP
0.5
5.5
-
5.5
-
2.5
4.0
-
4.5
-
ns
tH
Hold Time HIGH
or LOW I/On.
DS o or DS 7 to CP
0
1.5
-
1.5
-
1.0
1.5
-
1.5
-
ns
tw
CP Pulse Width
HIGH or LOW
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
tw
MR Pulse Width
LOW
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
tREM
Recovery Time
trnto CP
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
CL = 50pF
RL = 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
S10-103
IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
Commercial
MIL-STD-883. Class B
1..-----___- - - - - - - 1
-1).
\
S10-104
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
299
299A
8-lnput Universal Shift Register
Fast 8-lnput Universal Shift Register
54
-55°C to + 125°C
t;)
lOT 54/74FCT373
lOT 54/74FCT373A
FAST CMOS OCTAL
TRANSPARENT LATCH
Integrated. Device~Inc.
DESCRIPTION:
FEATURES:
ThI
• IDT54/74FCT373 equivalent to FAST speed;
IDT54/74FCT373A 35% faster than FAST Thl
• Equivalent to FAST Thl output drive over full temperature
and voltage supply extremes
• IoL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5}JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST TM (5}JA max.)
• Octal transparent latch with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87644 is listed on this
function. Refer to Sction 2/page 2-4.
The IDT54/74FCT373 and IDT54/74FCT373A are a-bit latches
built using advanced CEMOS TM, a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for busoriented applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up times is latched. Data~pears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the bus output
is in the high impedance state.
PIN CONFIGURATIONS
INDEX
DE"
Vcc
00
07
Do
D1
01
O2
D2
D3
03
GND
UUIIUU
D7
De
Oe
D1
]
01
:] 5
O2
]
05
D2 ] 7
D3 :] 8
Ds
D4
04
LE
4
e
3 2 LJ 20 19
1
18 [: Dr
L20-2
17C De
18 [: 0 8
1SC 05
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
S10-105
JANUARY 1989
DSC-4017/-
IDT54/74FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
0.5
W
120
mA
Power Dissipation
0.5
lOUT
DC Output Current
120
CIN
V
TA
PT
SYMBOL
UNIT
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
pF
Output Capacitance
8
12
VOUT= OV
. COUT
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
"'H
"'L
TEST CONDITIONS(1)
PARAMETER
MAX.
UNIT
Guaranteed Logic High Level
2.0
-
-
V
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
-
5
VI = 0.5V
-
VI = GND
Vo = Vee
Input HIGH Current
-
5(4)
-
_5(4)
-
-
-5
-
-
10(4)
-10(4)
-
-10
-0.7
-1.2
V
-60
-120
rnA
= VLe or VHC , 10H = -32~
VHe
Vee
-
10H = -300~A
VHe
Vce
10H = -12mA MIL.
2.4
4.3
10H= -15mA COM'L.
2.4
4.3
-
-
GND
Vle
VI = 2.7V
Vec = Max.
IlL
loz
Input LOW Current
Vo = 2.7V
Off State (High Impedance)
Output Current
.
Vee = Max.
Clamp Diode Voltage
Vcc = Min., IN = -18mA
Short Circuit Current
Vee = MaxP), Vo = GND
Vo = 0.5V
Vo = GND
"'K
los
Vee = 3V,
VOH
Output HIGH Voltage
'-"N
Vcc = Min.
'-"N = '-"H or '-"L
Vee = 3V,
'-"N
=' Vle or VHe , 10L = 300~
10l = 300~A
VOL
TYP.(2)
Input HIGH Level
VI = Vee
IIH
MIN.
Output LOW Voltage
--1
Vee = Min.
VIN = VIH or VIL
10L = 32mA MIL.
10L = 48mA COM'L
10
GND
VLC
0.3
0.5
0.3
0.5
VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-106
~A
-
~A
V
V
mV
IDT54/74FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0 2V· vHC = VCC - 0 2V
Vee
Quiescent Power Supply Current
Icc
bolcc
Power Supply Current Per TTL
. Inputs HIGH
Dynamic Power Supply Current(4)
ICCD
TYP.(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
2.0
rnA
VIN ?: VHC
~N :5 VLC
-
0.15
0.25
mAl
MHz
~N ?: VHC
~N :5 VLC
(FCT)
-
1.5
4.0
~N = 3.4V
VIN = GND
-
1.8
5.0
-
3.0
6.5(5)
-
5.0
14.5(5)
TEST CONDITIONS(1)
PARAMETER
SYMBOL
MIN.
= Max.
~N ?: VHC : ~N :5 VLC
fl = 0
Vcc
VIN
= Max.
= 3.4V(3)
Vcc = Max.
Outputs Open
OE = GND
LE = Vcc
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fl = 10MHz,
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling
rnA
Total Power Supply Current(6)
Ic
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling
VIN ?: VHC
VIN :5 VLC
(FCT)
~N = 3.4V
~N = GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived ~or use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + bolcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
bolcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
TRUTH TABLE
DESCRIPTION
INPUTS
OUTPUTS
Do - D7
Data Inputs
On
LE
OE
On
LE
Latch Enables Input (Active HIGH)
H
H
L
H
ITE
Output Enables Input (Active LOW)
L
H
L
L
3-State Latch Outputs
X
X
H
Z
00
-
07
H
L
X
Z
S10-107
= HIGH Voltage Level
= LOW Voltage Level
= Don't Care
= HIGH Impedance
IDT54/74FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT373
SYMBOL
. PARAMETER
CONDITION(1)
COM'L
TYP.(3)
MIN.(2) MAX.
IDT54174FCT373A
COM'L
MIL
TYP.(3)
MIN~2)
MAX.
MIN.(2)
MIL
UNIT
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
Dn to On
5.0
1.5
8.0
1.5
8.5
4.0
1.5
5.2
1.5
5.6
ns
tpZH
tpZL
Output Enable
Time
7.0
1.5
12.0
1.5
13.5
5.5
1.5
6.5
1.5
7.5
ns
tpHZ
tpLZ
Output Disable
Time
6.0
1.5
7.5
1.5
10.0
4.0
1.5
5.5
1.5
6.5
ns
t pLH
tpHL
Propagation Delay
LE to On
9.0
2.0
13.0
2.0
15.0
7.0
2.0
8.5
2.0
9.8
ns
tsu
Set-up Time
HIGH or LOW
Dn to LE
1.0
2.0
-
2.0
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
Dn to LE
1.0
1.5
-
1.5
-
1.0.
1.5
-
1.5
-
ns
tw
LE Pulse Width
HIGH or LOW
5.0
6.0
-
6.0
-
4.0
5.0
-
6.0
-
ns
CL = 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V. + 25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXX)(
Device Type
Commercial
MIL-STD-883. Class B
'------------1
'-----------------l
S10-108
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
373
373A
Octal Transparent Latch
Fast Octal Transparent Latch
54
-55°C to
+ 125°C
t;)
lOT 54/74FCT374
lOT 54/74FCT374A
FAST CMOS
OCTAL D REGISTER
(3-STATE)
IntegIatedDevIce~Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT374 equivalent to FAST™speed;
IDT54/74FCT374A 35% faster than FAST ™
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
•
10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5~A max.)
• Positive, edge-triggered Master/Slave, D-type flip-flops
• Buffered common clock and buffered common three-state
control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87628 is listed on this
function. Refer to Section 2/page 2-4.
The IDT54/74 FCT374 and IDT54/74FCT374A are 8-bit registers
built using advanced CEMOS TM, a dual metal CMOS technology.
These registers consist of eight D-type flip-flops with a buffered
common clock and buffered 3-state output control. When the out~
put enable (OE) input is LOW, the eight outputs are enabled. When
the OE input is HIGH, the outputs are In the three-state conditions.
Input data meeting the set-up and hold time requirements ofthe
D inputs is transferred to the 0 outputs on the LOW-ta-HIGH transition of the clock input.
PIN CONFIGURATIONS
o
INDEX
O'E"
Vcc
00
07
Do
Dl
01
O2
D2
D3
03
GND
D7
De
Oe
05
D5
D4
04
CP
0
o 0
~
8
>
~
0
UU;;ULJ
3 2 U 20 19
Dl
:J 4
18 [:
O2 :J e
D2 ]7
D3 ]8
D7
17E De
0 , ]5
leC
15 [:
14 [:
L20-2
Oe
05
D5
rnJ
9 10 11 12 13
nnnnn
o~&oo
"C!I
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
D2
D3
D4
D5
De
D7
CP
CLOCK
~
OUTPUT
ENABLE
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4018/-
1989 Integrated Device Technology, Inc.
S10-109
IDT54/74FCT374/A FAST CMOS
OCTAL 0 REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
MILITARY
-0.5 to +7.0
SYMBOL
UNIT
CIN
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
.,.65 to + 135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DCOutput Current
120
120
mA
(TA= +25°C f = 10MHz)
PARAMETER(1)
Input Capacitance
MAX. UNIT
CONDITIONS TYP.
VIN = OV
6
10
pF
COUT
pF
Output Capacitance . VOUT= OV
8
12
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military:TA = -55°C to +125°C;Vee = 5.0V±10%
SYMBOL
"'H
"'L
IIH
TEST CONDITIONS (1)
PARAMETER
loz
"'K
los
UNiT
Guaranteed Logic High Level
2.0
-
-
V
Guaranteed Logic Low Level
-
-
0.8
V
VI = Vec
-
-
5
VI = 2.7V
-
-
5(4)
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
Vee = Max.
Clamp Diode Voltage
Vee = Min., IN
Short Circuit Current
Vcc = MaxP!
Output HIGH Voltage
Vee = Min.
VrN = VrH or
-
-
VI = GND
-
-
-5
Vo = Vee
Vo = 2.7V
-
-
10(4)
Vo = 0.5V
-
-
_10(4)
Vo = GND
-
-
-10
-
-0.7
-1.2
V
-60
-120
-
mA
VHe
Vcc
-
IOH = -300JlA
VHC
\tc
-
10H = -12mA MIL.
2.4
4.3
-
= -18mA
Vo = GND
= VLC orVHc.l oH = -32JlA
\'IL
10H
Output LOW Voltage
= -15mA COM'L.
i
=
10
2.4
4.3
-
-
GND
VLC
-
GND
VLe
10L ~ 32mA MIL.
-
0.3
0.5
10L.7' 48mA COM'L.
-
0.3
0.5
10L
Vec = Min.
VrN = VrH or VrL
300JlA
VH
Input Hysteresis on Clock Only
'200
NOTES:
1. For conditions shown a~ max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vde = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-110
JlA
VI = 0.5V
_5(4)
Vcc = 3V. VrN = VLC or VHC . 10L = 300JlA
VOl:
MAX.
Input LOW Level
Vec = 3V, VrN
VOH
TYP.(2)
Input HIGH Level
Vce = Max.
IlL
MIN.
-
JlA
V
V
mV
IDT54/74FCT374/A FAST CMOS
OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ;:: VHC ; VIN :5 VLC
fcp = fl = 0
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
BE = GND
One Bit Toggling
50% Duty Cycle
ICCD
Ic
TVP.(2)
MAX.
-
0.001
1.5
mA
-
0.5
2.0
mA
VIN ~ VHC
VIN :5 VLC
-
0.15
0.25
MHz
VIN ~ VHC
VIN :5 VLC
(FCT)
-
1.5
4.0
V IN = 3.4Vor
VIN = GND
-
2.0
6.0
TEST CONOITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
fcp = 10MHz
~% Duty Cycle
OE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
MIN.
UNIT
mAl
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
"IN ~ VHC
VIN :5 VLC
(FCT)
-
3.75
7.8(5)
VIN = 3.4Vor
VIN = GND
-
6.0
16.8(5)
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
TRUTH TABLE
DESCRIPTION
INPUTS
FUNCTION
DI
CP
CLOCK
0,
0,
0,
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
-"
-"
-"
-"
L
H
L
H
L
H
Z
Z
H
L
H
L
The D flip-flop data inputs.
Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.
01
The register three-state outputs.
BE
Output Control. An active-LOW three-state control
used to enable the outputs. A HIGH level input
forces the outputs to the high impedance (off)
state.
OUTPUTS INTERNAL
OE
H
L
X
Z
....;If"'";
NO =
.
HIGH
LOW
Don't Care
High Impedance
LOW-to-HIGH transition
No Change
S10-111
------_.----------------------
IDT54/74FCT374/A FAST CMOS
OCTAL 0 REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT374A
I DT54/74FCT374
SYMBOL
PARAMETER
CONDITION(1)
MIL.
COM'L.
Typ.(3)
MIN.(2) MAX.
COM'L.
MIN!2)
MAX.
Typ.(3)
MIL
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
CPto On
6.6
2.0
10.0
2.0
11.0
4.5 .
2.0
6.5
2.0
7.2
ns
tpZH
tpZL
Output Enable
Time
9.0
1.5
12.5
1.5
14.0
5.5
1.5
6.5
1.5
7.5
ns
tpHZ
tpLZ
Output Disable
Time
6.0
1.5
8.0
1.5
8.0
4.0
1.5
5.5
1.5
6.5
ns
tsu
Set-upTime
HIGH or LOW
Dn to CP
1.0
2.0
-
2.5
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
Dn toCP
0.5
2.0
-
2.0
-
0.5
1.5
-
1.5
-
ns
tw
CP Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
CL = 50pF
RL = 500n
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
X
Package
X
Process/
Temperature
"y:,onk
'------------i
'-----------------1
S10-112
Commercial
MIL-STD-883. Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
374
374A
Octal D Register (3-state)
Fast Octal D Register
54
-55°C to + 125°C
74
O°C to + 70°C'
lOT 54/74FCT377
lOT 54/74FCT377A
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
Integrated Device1echnoJogy.1nc.
FEATURES:
• IDT54/74FCT377 equivalent to FAST™speed;
IDT54/74FCT377A 45% faster than FAST ™
• Equivalent to FAST ™output drive over full
temperature and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• Octal D flip-flop with clock enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87627 is pending listing on
this function. Refer to Section 2/page 2-4.
DESCRIPTION:
The IDT54/74FCT377 and IDT54/74FCT377A are octal D flipflops built using advanced CEMOS TM, a dual metal CMOS technology. The IDT54/74AFCT377 and IDT54/74FCT377A have eight
edge-triggered, D-type flip-flops with individual D inputs and 0
outputs. The common buffered Clock (C£2. input loads all flip-flops
simultaneously when the Clock Enable (eE) is LOW. The register is
fully edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop's 0 output. The CE input must be stable
only one set-up time prior to the LOW-to-HIGH clock transition for
predictable operation.
PIN CONFIGURATIONS
cr
INDEX
00
I
Do
D1
]4
°1
:]5
°2D2
]6
:J
D3
I
I
I
L..J
L..J
3
2
I
I
II
U
I
I
L..J
I
16 [:
L20-2
7
D7
E:
D6
16 [:
06
15 [:
05
E:
D5
17
:J 6
03
I
L..J
20 19
1
14
GND
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
D1
00
°1
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1969 In1egra1ed Device Technology. Inc.
JANUARY 1989
DSC-4019/-1
S10-113
----------------------------------_.-----------
IDT54/74FCT377/A FAST CMOS
OCTAL D FLlP·FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
-0.5 to +7.0
CAPACITANCE
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
CIN
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to + 125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
COUT
Vour= OV
Output Capacitance
8
12
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating can·
ditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc ·0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military'TA = ·55°C to + 125°C', V.cc -- 50V+10%
SYMBOL
"'H
"'L
MIN.
TYP,(2)
MAX.
UNIT
Input HiGH Level
Guaranteed Logic High Level
2.0
V
Input LOW Level
Guaranteed Logic Low Level
0.8
V
-
5
VI = 2.7V
-
-
-
-
5(4)
VI = 0.5V
-
-
_5(4)
VI = GND
-
-5
Vo = Vee
-
-
10
Vo = 2.7V
-
-
10(4)
-
_10(4)
TEST CONDITIONS (1)
PARAMETER
VI = Vcc
IIH
Input HIGH Current
Vec = Max.
IlL
loz
"'K
los
VOH
VOL
Input LOW Current
Off State (High Impedance)
Output Current
Vcc = Max.
Clamp Diode Voltage
Vee = Min., IN = -18mA
Short Circuit Current
Output HiGH VOlt~ge
Output LOW Voltflge
h
~~
..
jJA
jJA
Vo = 0.5V
-
Vo = GND
-
-
-10
-
-0.7
-1.2
V
Vce = MaxP), Vo = GND
-60
-120
mA
Vee = 3V, \'IN = VLC or VHe , 10H = ·32jJA
VHC
Vec
-
IOH = -300jJA
VHC
Vec
-
IOH = -12mA MIL.
2.4
4.3
-
IOH = -15mA COM'L.
Vee = Min.
\'IN = \'IH or \'IL
2.4
4.3
-
Vee = 3V, \'IN = VLe or VHC , 10L = 300jJA
-
GND
VLe
IOL = 300jJA
-
GND
VLC
0.3
0.5
0.3
0.5
Vee = Min.
\'IN = \'IH or\'lL
IOL = 32mA MIL.
10L = 48mA COM'L.
VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-114
-
V
V
mV
IDT54/74FCT377/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
MIN.
Typ.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; VIN ~ VLC
fcp = fl = 0
-
0.001
1.5
mA
bl cc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
CE = GND
One Bit Toggling
50% Duty Cycle
\IN ~ VHC
\IN ~ VLC
-
0.15
0.25
MHz
\IN ~ VHC
\IN ~ VLC
(AHCT)
-
1.5
4.0
V IN = 3.4Vor
VIN = GND
-
2.0
6.0
ICCD
Ic
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
mAl
mA
Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fcp = 1.0MHz
50% Duty Cycle
CE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
VIN ~ VHC
\IN ~ VLC
(AHCT)
-
3.75
7.8(5)
V IN = 3.4Vor
VIN = GND
-
6.0
16.8(5)
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + blcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
bl cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Do-D7
TRUTH TABLE
DESCRIPTION
OPERATING MODE
Data Inputs
CE
Clock Enable (Active LOW)
Load "1"
0 0 -0 7
Data Outputs
Load "0"
CP
Clock Pulse Input
Hold (Do Nothing)
INPUTS
OUTPUTS
CP
CE
i
i
i
I
h
I
I
L
h
H
X
X
No Change
No Change
X
~
D
0
H
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-H IGH Clock
Transition
L = LOW Voltage Level
= LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
Immaterial
X
i
S10-115
= LOW-to-HIGH Clock Transition
IDT54/74FCT377/A FAST CMOS
OCTAL 0 FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT377
SYMBOL
PARAMETER
CONDITION (1)
TYP~3)
COM'L.
MIN.(2) MAX.
I DT54/74FCT377A
MIL.
TYP!3)
MIN~2)
MAX.
COM'L.
MIL.
UNIT
MIN.(2)
MAX.
MIN.(2)
MAX.
tpLH
tpHL
Propagation Delay
CPto On
7.0
2.0
13.0
2.0
15.0
5.0
2.0
7.2
2.0
8.3
ns
tsu
Set-upTime
HIGH or LOW
Dr, to CP
1.0
2.5
-
3.0
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
Dr, to CP
1.0
2.0
-
2.5
-
1.0
1.5
-
1.5
-
ns
tsu
Set-up Time
HIGH or LOW
cr to CP
1.5
4.0
-
4.0
-
1.0
3.5
-
3.5
-
ns
tH
Hold Time
HIGH or LOW
CE to CP
3.0
1.5
-
1.5
-
1.0
1.5
-
1.5
-
ns
Clock Pulse
Width, LOW
4.0
7.0
-
7.0
-
4.0
6.0
-
7.0
-
ns
tw
CL = 50pF
RL = 500a
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
Commercial
MIL-STD-883, Class B
L...-----------I
P
D
E
SO
L
377
' - - - - - - - - - - - - - - - - - / 377A
S10-116
Plastic DIP
CERDIP
CERPACK
Small Outline IC
Leadless Chip Carrier
Octal D Flip-Flop w/Clock Enable
Fast Octal D Flip-Flop w/Clock Enable
~
Integrated Device'i!chnology. Inc.
FAST CMOS QUAD
DUAL-PORT REGISTER
lOT 54/74FCT399
lOT 54/74FCT399A
FEATURES:
DESCRIPTION:
• IDT54/74FCT399 equivalent to FAST™ speed;
IDT54/74FCT399A 30% faster than FAST ™
• Equivalent to FAST ™pinout/function and output drive over full
temperature and voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 16-pin DIP and SOIC, and 20-pin LCC
• Military product compliant to MIL-STD-883, Class B
• Product available in Radiation Tolerant and Enhanced versions
Both these devices are high-speed quad dual-port registers.
They select four bits of data from either of two sources (Ports) under
control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-ta-HIGH
transition of the Clock input (CP). The 4-bit D-type output register is
fully edge-triggered. The Data inputs (lox, 11X) and Select input (S)
must be stable only one set-up time prior to, and hold time after,
the LOW-to-HIGH transition of the Clock input for predictable
operation.
FUNCTIONAL BLOCK DIAGRAM
lOA
S
OA
IIA
loB
mil
OB
liB
loc
Oc
IIC
100
00
110
CP
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-4023/-1
S10-117
IDT54FCT399/AAND IDT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
u u;; u u
S
QA
3
2
LJ
20 19
lOA ] 4
lOA
IIA
11A
:1
NC
lIB
liB
lOB
lOB
QB
5
] 6
:1
:1
L20-2
18 [:
10D
17[
liD
NC
16 [:
7
15[
8
14 [
lie
loe
GND
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
LOGIC SYMBOL
PIN DESCRIPTION
PIN NAMES
S
S
CP
FUNCTIONAL TABLE
INPUTS
H =
L =
h =
=
X =
OUTPUTS
Q
S
I
10
11
I
X
L
I
h
X
H
h
X
I
L
h
h
X
H
HIGH Voltage Level
..)iiq'
LOW Voltage Level
HIGH Voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
LOW Voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
Immaterial
S10-118
DESCRIPTION
Common Select Input
CP
Clock Pulse Input (Active Rising Edge)
lOA -IOD
Data Inputs from Source 0
11A -110
Data Inputs from Source 1
QA - Q D
Register True Outputs
IDT54FCT399/A AND IDT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (1)
RATING
SYMBOL
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
lOUT
COMMERCIAL
-0.5 to + 7.0
o to
MILITARY
-0.5 to +7.0
CIN
V
-55 to + 125
°C
-55 to +125
-65 to + 135
°C
-55 to +125
-65 to + 150
°C
Power Dissipation
0.5
0.5
W
DC Output Current
120
120
mA
+70
SYMBOL
UNIT
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
Input Capacitance
CONDITIONS TYP.
VIN = OV
MAX. UNIT
6
10
pF
VOUT = OV
Output Capacitance
8
12
pF
COUT
NOTE:
1. This parameter is guaranteed by characterization data and not
tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = 0.2V; VHC = Vce - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vec = 5.0V ±10%
TEST CONDITIONS (1)
MIN.
Typ.(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
Vil
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
VI = \(::e
-
5
VI = 2.7v
-
-
5(4)
-
_5(4)
SYMBOL
IIH
PARAMETER
Input HIGH Current
Vee = Max.
III
"'K
los
Input LOW Current
VI = 0.5V
-
VI = GND
-
-
-5
Clamp Diode Voltage
Vee = Min., IN = -18mA
-
-0.7
-1.2
V
Short Circuit Current
Vee = Max~3), Vo = GND
-60
-120
mA
VHC
Vee
-
10H = -300~A
VHC
\(::e
-
10H = -12mA MIL.
2.4
4.3
-
10H = -15mA COM'L.
Vee = 3V, VIN = VLC or VHe , 10H = -32jJA
VOH
VOL
~A
Output HIGH Voltage
Output LOW Voltage
Vec = Min.
'-"N = VIHor'-"l
2.4
4.3
-
Vee = 3V, '-"N = Vle or VHe , 10l = 300~A
-
GND
Vle
10l = 300~A
-
GND
VlC
0.3
0.5
0.3
0.5
Vec = Min.
VIN = VIH or '-"l
IOl = 32mA MIL.
10l = 48mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-119
V
V
IDT54FCT399/A AND IDT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; '4tc = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS(1)
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; "IN :5 VLC
fcp == fl = 0
~Icc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
One Input Toggling
atf l = 5MHz
50% Duty Cycle
S = Steady State
Ic
MIN.
Typ.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
'-"N ~ VHC
'-"N :5 VLC
-
0.15
0.25
mA/MHz
'-"N ~ VHC
'-"N :5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN ~r GND
-
2.0
6.0
Total Power Supply Current (6)
mA
\bc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
Four Inputs Toggling
at fl = 5MHz
50% Duty Cycle
S = Steady State
'-"N ~ VHC
VIN :5 VLC
(FCT)
VIN
= 3.4V
VIN
= GND
or
-
3.75
7.75(5)
-
5.0
12.75(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6.l c = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number 'of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-120
IDT54FCT399/AAND I DT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54FCT399A
I DT54FCT399
(1)
(3)
COM'L
MIN.(2) MAX.
MIL
MIN.(2) MAX.
(3)
COM'L
MIN.(2) MAX.
MIL
MIN.(2) MAX.
t pLH
t PHL
Propagation_Delay
CPto Q orQ
6.8
3.0
10.0
3.0
11.5
4.0
2.5
7.0
2.5
7.5
ns
tsu
Set-UpTime
HIGH or LOW
In to CP
3.0
4.0
-
4.5
-
2.5
3.5
-
4.0
-
ns
tH
Hold Time
HIGH or LOW
In to CP
1.0
1.0
-
1.5
-
1.0
1.0
-
1.0
-
ns
tsu
Set-Up Time
HIGH or LOW
StoCP
8.0
9.0
-
9.5
-
7.0
8.5
-
9.0
-
ns
tH
Hold Time
HIGH or LOW
StoCP
0
0
-
0
-
0
0
-
0
-
ns
tw
CP Pulse Width,
HIGH or LOW (4)
4.0
5.0
-
7.0
-
3.5
5.0
-
6.0
-
ns
CL = 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V and + 25°C ambient and maximum loading.
4. This parameter is guaranteed but not tested.
ORDERING INFORMATION
IDTXX FCT
Temperature
Range
XXX)(
A
Device Type
Package
Commercial
MIL-STD-883, Class B
P
D
~----------------~
L
SO
E
' - - - - - - - - - - - - - - - - f 'I 399A
399
~
__________________~--------------~154
174
S10-121
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Quad Dual·Port Register
FAST Quad Dual-Port Register
-55°C to + 125°C
O°Cto +70°C
t;J
Intesrated Device Technology. Inc.
FAST CMOS
OCTAL BUFFER/
LINE DRIVER
PRELIMINARY
lOT 54/74FCT540/A
lOT 54/74FCT541/A
FEATURES:
DESCRIPTION:
• IDT54174FCT540/41 equivalent to FAST ™speed;
IDT54/74FCT540A/41A 30% faster than FAST ™
• Equivalent to FAST™ output drive over full temperature and
voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• Octal buffer/line driver with 3-state output
• Pinout arrangement for flow-through architecture
• CMOS power levels (5~W typo static)
• Substantially lower input current levels than FAST ™ (5~A max.)
• Available in CERDIP, Plastic DIP, LCC and SOIC
• TIL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT540/A and IDT54/74FCT541/A are octal
buffer/line drivers built using advanced CEMOS n", a dual metal
CMOS technology.
These devices are similar in function to the IDT54/74FCT240
and IDT54/74FCT241, respectively, except that the inputs and outputs are on opposite sides of the package. This pinout arrangement makes these devices especially useful as output ports for
microprocessors, allowing ease of layout and greater board
density.
FUNCTIONAL BLOCK DIAGRAM
OE"A-----,
00
PIN CONFIGURATIONS
~B
~-t---
00
)o--t---
01
)o--t---
02
»--t---
03
«
DS
04
Os
06
D6
~-t---
as
D7
GND
~-+---
06
07
I
1'1
3
2
I
I
~
U
20 19
:J
01
D4
04
............
00
02
03
)o--t---
)o--t---
OE"B
D3
m
o~~ ~~
INDEX
Vcc
OE"A
Do
D1
D2
4
]s
]6
D6
:J
:J
l20-2
7
8
18 [:
00
17[
01
16 [:
02
lS[
03
14 [:
04
~ ~ ~ ~~
~
.... 0
.....
OZO
(!)
DIP/SOIC/CERPACK
TOP VIEW
00
LCC
TOP VIEW
IDT54/74FCT540
OEA-----,
~B
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
00
DESCRIPTION
3-State Output Enable Input (Active LOW)
OEA. OEB
>--+--- 0 1
Dxx
Inputs
>--+---
Oxx
Outputs
O2
TRUTH TABLE
04
04
Ds
Os
INPUTS
OUTPUT
OEA.OEs
L
D
L
540
H
541
L
06
06
L
H
L
H
07
07
H
X
Z
Z
H = HIGH Voltage Level
L = LOW Voltage Level
IDT54/74FCT541
X = Don't Care
Z = High Impedance
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 In1egra1ed Device Technology. Inc.
S10-122
JANUARY 1989
DSC-4029/-1
IDT54/74FCT540/A and IDT54/74FCT541/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
COMMERCIAL
-0.5 to + 7.0
o to
+ 70
MILITARY
-0.5 to +7.0
V
-55 to + 125
°C
-55 to + 125
-65 to + 135
°C
-55 to + 125
-65 to + 150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
120
120
mA
(TA = +25°C, f = 1.0MHz)
PARAMETER(l)
CONDITIONS TYP.
SYMBOL
UNIT
CIN
Input CapaCitance
COUT
Output Capacitance
= OV
VOUT = OV
VIN
MAX. UNIT
6
10
pF
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLe = 0.2V; VHC = Vee - 0.2V
Commercial: TA = O°C to + 70°C; Vce = 5.0V±5%
Military: TA = -55°C to +125°C; Vee = 5.0V±10%
SYMBOL
TEST CONDITIONS(l)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
V
'-"H
Input HIGH Level
Guaranteed LogiC High Level
2.0
-
-
'-"L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
Vec
-
-
5
2.7V
-
-
5(4)
0.5V
-
-
-5(4)
-
-5
VI
=
=
VI
=
VI
=
GND
-
Vo
Vec
-
-
10
Vo
=
=
2.7V
-
-
10(4)
Vo
=
0.5V
-
-
-10(4)
Vo
=
GND
VI
IIH
Input HIGH Current
Vce
hL
=
Max.
Input LOW Current
loz
Off State (High Impedance)
Output Current
Vce
=
Max.
VIK
Clamp Diode Voltage
Vce
Min., IN
los
Short Circuit Current
Vee
=
=
Vce
=
3V, '-"N
VOH
Output HIGH Voltage
Output LOW Voltage
Max!3), Vo
=
= VLC
3V, '-"N
=
-
-10
-0.7
-1.2
V
-60
-120
mA
-32~
VHe
Vce
Vec
-
=
=
-300~A
VHe
10H
-12mA MIL.
2.4
4.3
-
10H
=
-15mA COM'L.
2.4
4.3
VLC
10H
=
VLe orVHC , 10L
=
300~
-
GND
-
..
300~A
=
=
GND
VLC
10L
48mA MIL.
-
0.3
0.55
10L
=
64mA COM'L.
-
0.3
0.55
10L
Vce = Min.
'-"N = '-"H or '-"L
=
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-123
~A
-
GND
orVHC • 10H
~A
-
-18mA
Vce = Min.
VIN = '-"H or"iL
Vce
VOL
=
V
V
IDT54/74FCT540/A and IDT54/74FCT541/A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS(l)
PARAMETER
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ;::: VHC ; "'N:5 VLC
fl = 0
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
C5EA = eJE B = GND
One Input Toggling
50% Duty Cycle
ICCD
Ic
MIN.
Typ.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
"'N ;::: VHC
"'N :5 VLC
-
0.15
0.25
mA/MHz
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OEA = DEB = GND
One Input Toggling
"'N ;::: VHC
"'N :5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN = GND
-
1.8
5.0
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OEA = DEB = GND
Eight Inputs Toggling
"'N ;::: VHC
"'N :5 VLC
(FCT)
-
3.0
6.5(5)
"'N = 3.4V
VIN = GND
-
5.0
14.5(5)
Total Power Supply Current (6)
mA
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. + 25 0 C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non·Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT540/541
(1)
(3)
t pLH
tpHL
Propagation Delay
Dn to On IDT54/74FCT540
t pLH
t pHL
On
Propagation Delay
to On IDT54/74FCT541
IDT54/74FCT540A/541A
COM'L.
MIL.
MIN.(2) MAX. MIN.(2) MAX.
(3)
COM'L.
MIL.
MIN.(2) MAX. MIN.(2) MAX.
5.0
2.0
8.5
2.0
9.5
3.5
2.0
4.8
2.0
5.1
ns
5.0
2.0
8.0
2.0
9.0
3.5
2.0
4.8
2.0
5.1
ns
CL = 50pF
RL = 5000
t pZH
t pZL
Output Enable Time
7.0
2.0
10.0
2.0
10.5
4.2
2.0
6.2
2.0
6.5
ns
tpHZ
tpLZ
Output Disable Time
6.0
2.0
9.5
2.0
12.5
4.0
2.0
5.6
2.0
5.9
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at 'Icc = 5.0V. + 25 0 C ambient and maximum loading.
S10-124
IDT54/74FCT540/ A and I DT54/74FCT541/ A
FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temperature
Ra ge
xxxx
A
A
Device Type
Package
Process
y:~k
P
D
~--------------~ E
L
SO
540
'----------------------------i1 541
540A
l 541A
~
________________________________~154
174
S10-125
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Non-Inverting Octal Buffer/Line Driver
Inverting Octal Buffer/Line Driver
Fast Non-inverting Octal Buffer/Line Driver
Fast Inverting Octal Buffer/Line Driver
-55°C to + 125°C
O°Cto +70°C
t;)
Intesrated Dev1ce1echnology.lnc.
PRELIMINARY
lOT 54/74FCT543
lOT 54/74FCT543A
FAST CMOS
OCTAL REGISTERED
TRANSCEIVER
FEATURES:
DESCRIPTION:
• IDT54/74FCT543 equivalent to FAST™speed;
IDT54/74FCT543A Is 25% faster than FAST ™
The IDT54/74 FCT543 and IDT54/74 FCT543A are non-inverting
octal transceivers built using advanced CEMOS T~ a dual metal
CMOS technology. These devices contain two sets of eight D-type
latches with separate Input and output controls for each set. For
data flow from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from Ao -A7 or to take data from
Bo-B7, as indicated in the Truth Table. With CEAB LOW, a LOW
signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition of the
LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is Similar, but uses the CEBA, LEBA and OEBA inputs.
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
•
10L = 64mA (commercial), 48mA (military)
• 8-bit octal latched transceiver
• Separate controls for data flow in each direction
•
•
•
•
•
•
Back-to-back latches for storage
CMOS power levels (5~W typo static)
Substantially lower input current levels than FAST ™(5~A max.)
TTL input and output level compatible '
CMOS output level compatible
Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
>---~~---e~--Bo
Ao--~~~------~-<
DETAILAx 7
~
---------------0
0---------------- OEAB
~ ------------~
~------------~
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-4030/1
S10-126
IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LEBA
'1 I
I
t
I
I
I I ......
LJLJLJ 1
4 3 2 U 28 27 26
Vec
CEBA
OEBA
~......,
2S[
24[
Bo
B1
Ao
A1
A2
A3
A4
As
B2
B3
B4
Bs
Ae
A7
CEAB
GND
J28-1
L28-1
Be
B7
12 13 14 1S 16
17
23[
Ao
OEBA
[E8A
22[
NC
21[
Vcc
20[
USA
18
nnnnnnn
"CEA13
OEAB
DIP/SOIC/CERPACK
TOP VIEW
LCC/PLCC
TOP VIEW
LOGIC SYMBOL
LEAB CEAB CEBA LEBA
Ao
A1
A2
A3
A4
As
A6
A7
OEBA
TRUTH TABLE
H
LEAS
X
PIN DESCRIPTIONS
For A-TO-B (Symmetric with B-TO-A)
LATCH
STATUS
INPUTS
CEAS
Bo
B1
B2
B3
B4
Bs
B6
B7
OEAB
OEAS
A-TO-B
X
Storing
Storing
OUTPUT
BUFFERS
Bo-B7
-
H
-
X
-
H
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous· A Inputs
..
OEAB.
High Z
X
-
PIN NAMES
High Z
* Before LEAB LOW-to-HIGH TranSition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown: B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
S10-127
DESCRIPTION
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
Ao-A7
A-to-B Data Inputs or B-to-A 3-State Outputs
Bo-~
B-to-A Data Inputs or A-to-B 3-State Outputs
IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER
ABSOLUTE MAXIMUM RATINGS
VTERM (2)
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
Terminal Voltage
VTERM (3) with Respect to
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
-0.5 to Vcc
o to
+70
CAPACITANCE
(1)
COMMERCIAL
RATING
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MILITARY
-0.5 to +7.0
-0.5 to Vcc
UNIT
SYMBOL
V
V
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
0.5
0.5
W
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CIN
Input Capacitance
CliO
I/O Capacitance
CONDITIONS TYP.
MAX.
UNIT
VIN = OV
6
10
pF
Vour= OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not
tested.
DC Output Current
100
mA
100
lOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposureto absolute maximum rating conditions for extended periods may affect reliability.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
MIN.
TYP.(2)
MAX.
UNIT
"IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
SYMBOL
IIH
TEST CONDITIONS(l)
PARAMETER
Vcc = Max.
Input LOW Current
(Except I/O pins)
IIH
Infcut HIGH Currents
(I 0 pins only)
Vcc = Max.
IlL
-
VI = GND
-
VI = Vcc
-
-
15
VI = 2.7V
VI = GND
-
-
15(4)
VI = 0.5V
-
-15
VI = Vcc
Input HIGH Current
(Except I/O pins)
IlL
VI = 2.7V
VI = 0.5V
-
Infcut LOW Currents
(I 0 pins only)
-
5
5(4)
_5(4)
J.(A
-5
_15(4)
J.(A
"IK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = Max!3), Vo = GND
-60
-120
-
mA
-
V
VHC
Vcc
10H = -300J.(A
VHC
Vcc
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
-
GND
VLI:~
Vcc = 3V, \IN = VLC or VHc .IoH = -32 J.IA
VOH
Output HIGH Voltage
Vcc = Min.
\IN = \lH or \lL
Vcc = 3V, \IN = VLC or VHC ' 10L = 300J.IA
VOL
Output LOW Voltage
10L = 300J.(A
Vcc = Min.
\IN = \lH or \lL
10L = 48mA MIUS)
GND
VLC
0.3
0.55
V
10L = 64mA COM'US)
0.3
0.55
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum IoL values per output, for 8 outputs turned on simultaneously. Total maximum 10L (all outputs) is 512mA for commercial and 384mA
for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.
S10-128
IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
MIN.
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; VIN :5 VLC
fcp = fl = 0
-
0.001
1.5
mA
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(4)
\.bc = Max.
Outputs Open
CE"AB & 0EAl3 = GND
CEBA = Vcc
One Input Toggling
50% Duty Cycle
'viN ~ Vl-ic
VIN :5 VLC
-
0.15
'0.25
mAl
'viN ~ VHC
'viN:5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4Vor
VIN = GND
-
2.0
6.0
ICCD
Ic
Total Pow~r Supply Current(6)
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CEAB & OEAB = GND
CEBA = Vcc
fcp = LEAB = 10MHz
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
Vcc= Max.
Outputs Open
fcp = 10MHz
50%DUty~
CEAB & OEA = GND
CEBA = Vcc
fcp = CEAB = 10MHz
Eight Bits Toggling
at fl = 5MHz
50% Duty Cycle
mA
VIN ~ VHC
'viN :5 VLC
(FCT)
-
3.75
12.75(5)
VIN = 3.4Vor
VIN = GND
-
6.0
21.75(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or, GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN ,= 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-129
MHz
IDT54!74FCT543 AND IDT54!74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT543A
I DT54/74FCT543
SYMBOL
t pLH
tpHL
tpLH
t pHL
PARAMETER
CONDITION(1)
Propagation Delay
Transparent Mode
TYP,<3)
COM'L.
COM'L.
MIL.
MIN.(2} MAX.
MIN.(2} MAX.
TYPP)
MAX.
MIN.(2)
2.5
5.0
2.5
8.5
2.5
10.0
-
2 .. 5
6.5
prL~a~Ation Delay
to An.
[EAt3to Bn
8.5
2.5
12.5
2.5
14.0
-
2.5
8
7.0
2.0
12.0
2.0
14.0
-
2
OEt3Aor~
to An or Bn
~orCEAt3
to An or Bn
Output Disable Time
tpHz
tpLZ
O!:BAor~to
{.
An or Bn
~orCEAt3to
5.5
2.0
9.0
2.0
13.0
-
3.0
-
3.0
-
-
2
An or Bn
tsu
tH
Set-up Time.
HIGH or LOW
An or Bn to
IT8J\ or l:EAB"
Hold Time.
HIGH or LOW
An or Bn to
IT8J\ or [EAt3
-::,:::::::
}::{
-
-
2.0
2.0
-
{~~b:·
<:}
I:i l! ! :t~:/
i:~!~:i' .
ns
ns
2
8.5
ns
-
2
-
ns
-
2
-
ns
:~,~1;
::\ ..
I:~;
~5:.
ns
10
.,9 q;:
CL = 50pF
RL = 500n
UNIT
MAX.
: . ,\~j~\
An to Bn or Bn to An
Output Enable Time
t pZH
tpZL
MIL
MIN~2)
\:'
... ::::;::
Ii
2
NOTES.
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test
environment. Large output currents are being switched in very
short periods and proper testing demands that test set-ups have
minimized inductance and guaranteed zero voltage grounds. The
techniques listed below will assist the user in obtaining accurate
testing results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper device operation and possible latch up.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be· distributed to
decouple power supply lines and be placed as close as possible to the DUT power pins.
3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being
recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To allow
for testing and hardware-induced noise, it may be necessary to
use V,L ~ OV and V,H ~ 3V for ATE testing purposes.
510-130
IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xx
Temperature
XX
Device Type
A
Package
A
Process
I
I Blank
~B
P
D
L
' - - - - - - - - - - - 1 SO
E
J
'--_ _ _ _ _ _ _ _ _ _ _ _ _--1 543
543A
54
'----------------------~ 74
S10-131
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Plastic Leadless Chip Carrier
Octal Registered Transceiver
Fast Octal Registered Transceiver
-55°C to + 125°C
O°Cto+70°C
"t;)
FAST CMOS OCTAL
INVERTING BUFFER
TRANSCEIVER
Intesrated Device'i!chnology.lnc.
lOT 54/74FCT640
lOT 54/74FCT640A
FEATURES:
DESCRIPTION:
• IDT54/74FCT640 7.0ns max. data to output;
IDT54/74FCT640A 5.0ns max. data to output
• Equivalent to FAST T.. output drive over full temperature and
voltage supply extremes
• IOL = 64mA commercial and 48mA military
• CMOS power levels (5,.JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST T.. (5~A max.)
• Inverting buffer transceiver
• JEDEC standard pinout for DIP. LCC and SOIC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
The IDT54/74FCT640 and IDT54/74FCT640A are 8-bit inverting
buffer transceivers built using advanced CEMOS T.., a dual metal
CMOS technology. These octal bus transceivers are designed for
asynchronous two-way communication between data buses. The
devices transmit data from the A bus to the 8 bus or from the 8 bus
to the A bus, depending u£Sln the level at the direction control (T/R)
input. The enable input (OE) can be used to disable the device so
the buses are effectively isolated.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
TIA
Vee
Ao
DE'
Al
So
A2
81
A3
82
A4
83
As
84
Ae
85
A7
Be
GND
~
TIA'
(19)
Ao
-
0
Ia:
I'
......
3
:] 4
f
I
L..I
......
~~
I
1'1'
I
I
2 U
1
I
L...I
Al
A2
A4
L..I
18 [:
Al
17 [:
Ao
leC
TiA
:] 7
15 [:
Vee
]8
14 [:
DE'
L20-2
9
(3)
(4)
(5)
(6)
20 19
]s
]e
(2)
(18)
A3
C{C{..-
OE'
"-"''---80
DIP/50lC/CERPACK
TOP VIEW
INDEX
(1)
As
Ae
(7)
(8)
10 11 12 13
nnnnn
(9)
A7
c(~alal"m
(11)
(!l
~
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a registered trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
510-132
JANUARY 1989
Dse-4033/1
IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES'
-0.5 to +7.0
Terminal Voltage
VTERM (3) with Respect to
GND
-0.5 to Vcc
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
-0.5 to Vcc
UNIT
SYMBOL
CIN
V
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
Input Capacitance
CONDITIONS TYP.
'vIN = OV
MAX. UNIT
6
10
pF
VOUT = OV
8
12
CliO
I/O Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
V
TA
(TA= +25°C f = 10MHz)
PARAMETER(l)
mA
DC Output Current
120
120
louT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Input and Vee terminals only.
3. Outputs and I/O terminals' only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLe = 0.2V; VHe = Vee -0.2V
Commercial: TA = O°C to + 70°C; 'te = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
'vIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
'vIL
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
VI = Vee
-
-
,5
VI = 2.7V
-
-
5(4)
VI = O.4V
-
-5(4)
VI = GND
-
-
-5
VI = Vee
-
VI = 2.7V
-
-
15(4)
VI = O.4V
-
-
_15(4)
VI = GND
-
-
-15
-
-0.7
-1.2
V
-60
-120
-
mA
-
IIH
l'fxut HIGH Current
( xcept I/O pins)
Vee = Max.
IlL
l'fxut LOW Current
( xeept I/O pins)
IIH
Input HIGH Current
(I/O pins only)
IlL
Input LOW Current
(I/O pins only)
VIK
Clamp Diode Voltage
Vee = Min., IN = -18mA
los
Short Circuit Current
Vee = Max. (3), Vo = GND
Vee = Max.
VOH
Output HIGH Voltage
Vee = Min.
"iN = "iH or"iL
VHe
Vee
VHe
\be
-
10H = -12mA MIL.
2.4
4.3
-
10H = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
10L = 300J,JA
-
GND
VLe
IOL = 48mA MIL.
-
0.3
0.55
IOL = 64mA COM'L.
-
0.3
0.55
Vee = 3V, "iN = VLe or VHe , 10L = 300JJA
VOL
Output LOW Voltage
Vee = Min.
"iN = VIH or"iL
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-133
15
10H = -300J,JA
Vee = 3V, "iN = VLe or VHe , 10H= -32 JJA
J,JA
J,JA
V
V
IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
TEST CONDITIONS
PARAMETER
SYMBOL
MIN.
(1)
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vcc = Max.
V1N ~VHC; "'IN ~ VLC
fl = 0
-
0.001
1.5
mA
.6.lcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
V1N = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
BE = GND
TIR = GND or Vcc
One Input Toggling
50% Duty Cycle
'-"N ~ VHC
'-"N ~ VLC
-
0.15
0.25
mAl
MHz
VIN ~ VHC
'-"N ~ VLC
(FCn
-
1.5
4.0
VIN = 3.4Vor
V1N = GND
-
1.8
5.0
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50.Jo D®, Cycle
TIR = OE = GND
One Bit Toggling
Ic
Total Power Supply Current
mA
(6)
'-"N ~ VHC
'-"N ~ VLC
(FCn
Vcc = Max.
Outputs Open
fl = 2.5MHz
50.Jo D~ Cycle
TIR = OE = GND
Eight Bits Toggling
V1N
VIN
= 3.4Vor
= GND
-
3.0
6.5(5)
-
5.0
14.5(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
·5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.1 cc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
INPUTS
OE
T/R
L
L
OPERATION
Bus B Data to Bus A
Output Enable Input (Active LOW)
TiA"
TransmiVReceive Input
L
H
Bus A Data to Bus B
Ao-A7
H
X
Isolation
Bo-B7
S10-134
DESCRIPTION
OE
Side A Inputs or 3-State Outputs
Side B Inputs or 3-State Outputs
IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT640A
IDT54/74FCT640
SYMBOL
tpLH
tpHL
PARAMETER
CONDITION(1)
Propagation Delay
A to B or B to A
tpZH
tPZL
Outpu1.Snable Tlme
for OE and T/R
t pHZ
tpLZ
Outpu!..Qisable T.!.me
for OE and T/R
C L = 50pF
RL = 500n
TYP~3)
COM'L
MIL
MIN.(2) MAX.
MIN!2)
Typ.(3)
MAX.
COM'L
MIL
MIN.(2)
MAX.
MIN.(2)
6.0
2.0
7.0
2.0
8.0
3.5
1.5
5.0
1.5
5.3
ns
11.0
2.0
13.0
2.0
16.0
4.8
1.5
6.2
1.5
6.5
ns
7.0
2.0
10.0
2.0
12.0
4.5
1.5
5.0
1.5
6.0
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at "cc = 5.0V. +25°C ambient and maximum loading.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
X
UNIT
MAX.
X
Package
Commercial
MIL-STD-883. Class B
~-----------------I
P
D
SO
L
E
L..------------------l
640
640A
-I 54
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
S10-135
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
.
Octal Inverting Buffer Transceiver
(equivalent to FAST™)
Octal Inverting Buffer Transceiver
(faster than FAST™)
-55°C to + 125°C
..
FAST cMos
NON-INVERTING
BUFFER TRANSCEIVER
t;)
Intesrated Device~loc
lOT 54/74FCT645
lOT 54/74FCT645A
FEATURES:
DESCRIPTION:
• IDT54/74FCT645 equivalent to FAST ™ speed;
IDT54/74FCT645A 35% faster than FAST ™
• Equivalent to FAST ™ output drive over full temperature
and voltage supply extremes
•
10L = 64mA (commercial) and 48mA (military)
• CMOS power levels (5}JW typo static)
• Substantially lower input current levels than FAST ™ (5}JA max.)
• Non-inverting buffer transceiver
• TTL input and output level compatible
• CMOS output level compatible
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT645 and IDT54/74FCT645A are 8-bit n6ninverting buffer transceivers built using advanced CEMOS ™,. a
dual metal CMOS technology. These non-inverting buffer transceivers are designed for asynchronous two-way communication
between data buses. The devices transmit data from the A bus to
the B bus or from the B bus to the A bus, depending upon the level
at the direction control (T/R) input. The enable input (OE) can be
used to disable the device so the buses are effectively isolated.
PIN CONFIGURATIONS
TIA
Vee
Ao
~
Al
Bo
A2
Bl
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
GND
B7
DIP/SOIC/CERPACK
TOP VIEW
INDEX
0 ICC
........
......
u
0
««I->
I
'"
~
~
3
A7
] 4
GND
]5
B7
]6
B6
]7
B5
]6
2
I I' "L....I
I
~
I
I
L....I
Ll 20 19
1
10 11
Al
Ao
16
L20-2
9
r:
17 [:
16
r:
T/R
15 [:
Vee
14 [:
DE
12 13
nnnnn
..t §?
c/J m
MAX.
COM'L.
MIL.
UNIT
MIN,(2) MAX. MINJ2) MAX.
tpLH
t pHL
Propagation Delay
Bus to Bus
7.0
2.0
8.0
2.0
9.0
-
2.0
5.6
2.0
6.3
ns
t pZH
tpZL
Output Enable Time
Enable to Bus &
DIR to Aor B
9.0
2.0
15.0
2.0
18.0
-
2.0
10.5
2.0
12.6
ns
t pHZ
tpLZ
Output Disable Time
Enable to Bus &
Direction to Bus
9.0
2.0
9.0
2.0
11.0
-
2.0
6.3
2.0
7.7
ns
7.0
2.0
9.0
2.0
10.0
-
2.0
6.3
2.0
7.0
ns
10.0
2.0
11.0
2.0
12.0
-
2.0
7.7
2.0
. 8.4
ns
CL = 50pF
RL = 500n
tpLH
t pHL
Propagation Delay
Clock to Bus
t pLH
t pHL
Propagation Delay
SBA or SAB to A or B
tsu
Set-up time HIGH
or LOW
Bus to Clock
3.0
4.0
-
4.5
-
-
2.0
-
2.0
-
ns
tH
Hold time HIGH
or LOW
Bus to Clock
1.0
2.0
-
2.0
-
-
1.5
-
1.5
-
ns
tpw
Pulse Width,
HIGH or LOW
4.0
6.0
-
6.0
-
-
5.0
-
5.0
-
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at \Co = 5.0V, + 25°C ambient and maximum loading.
4. These are preliminary numbers only.
S10-144
IDT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temperature
Range
xxxx
x
Device Type
Process/
Temperature
Range
-----II :,"k
1,--
P
D
~--------------------~ SO
L
E
646
646A
648
648A
~
____________________________________
~154
174
S10-145
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
. Leadless Chip Carrier
CERPACK
Non-inverting Octal Transceiver/Register
Fast Non-inverting Fast Octal Transceiver/
Register
Inverting Octal Transceiver/Register
Fast Inverting Fast Octal Transceiver/Register
(-55°C to + 125°C)
(O°C to + 70°C)
t;)
Integrated Devlceb:hnology.lnc.
PRELIMINARY
FAST CMOS
OCTAL TRANSCEIVER/
REGISTER
lOT 54/74FCT651/A
lOT 54/74FCT652/A
FEATURES:
DESCRIPTION:
• IDT54/74FCT651 and IDT54/74FCT652 are equivalent to
FAST ™ speeds
The IDT54/74FCT651/A and IDT54/74FCT652/A, built in
CEMOS ™ , consist of bus transceiver circuits, D-type flip-flops
and control circuitry arranged for multiplex transmission of data
directly from the data bus or from the internal storage registers.
GAS and GSA are provided to control the transceiver functions.
SAB and SBA control pins are provided to select either real-time or
stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. A low input level
selects real-time data and a high selects stored data.
Data on the A or B data bus, or both, can be stored in the internal
D flip-flops by low-ta-high transitions at the appropriate clock pins
(CPAB or CPBA), regardless of the select or enable control pins.
When SAB and SBA are in the real-time transfer mode, it is also
possible to store data without usin~ internal D-type flip-flops by
simultaneously enabling GAB and GSA. In this configuration, each
output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of bus lines
will remain at its last state.
• IDT54/74FCT651A and IDT54/74FCT652A 30% faster than
FAST ™ speeds
• Bidirectional bus transceiver and registers
• Independent registers forA and B buses
• Real-time data transfer or stored data transfer
• Choice of true and inverting data transfer
• 3-state outputs
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin 300 mil DIP, SOIC, 28-pin LCC and PLCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
IDT54174FCT652/A (Non-inverting)
CPAB
SAB
IDT54174FCT651/A (Inverting)
GAB
«
CPAB
«
m
SAB
GAB
m
(J)
(J)
(J)
(J)
::>
::>
::>
::>
m
m
m
m
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
OSC-4037/1
S10-146
IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
CPAB
SAB
Al
Vcc
CPBA
SBA
GBA
A2
A3
Bl
B2
A4
As
B3
B4
Bs
Ba
B7
GAB
Aa
A7
As
GND
...............
4
3
2
I
I
U~~~
:1 s
:16
]7
J28-1
L28-1
:1 s
:J 9
25 [
GAB
24 [:
SAB
23 [
CPAB
22[
NC
21 £:
lO[
Vce
CPBA
19[
SBA
Bs
LCC/PLCC
TOP VIEW
DIP/CERPACK/SOIC
TOP VIEW
LOGIC SYMBOL
PIN DESCRIPTION
CPAB
Al
A2
A3
A4 As
Aa
A7
As
DESCRIPTION
PIN NAMES
SAB
GAB
CPBA
SBA
GSA
AI-As
Data Register Inputs
Data Register A Outputs
B1-B s
Data Register B Inputs
Data Register B Outputs
CPAB,CPBA
Clock Pulse Inputs
SAB, SBA
Transmit/Receive Inputs
GAB,
GSA
Output Enable Inputs
FUNCTION TABLE
INPUTS
GBA
CPAB CPBA
SAB
SBA
L
L
H
H
H or L H or L
X
X
X
X
Input
X
H
H
H
H or L
X
X(2)
X
X
Input
Input
L
L
X
L
H or L
t
t
t
t
X
X
L
L
L
L
X
X
X
H or L
H
H
H
H
X
H or L
X
X
H
L
H or L H or L
t
t
t
OPERATION OR FUNCTION
DATA I/O
GAB
t
FCT651/A
FCT652/A
Input
Isolation
Store A and B Data
Isolation
Store A and B Data
Unspecified (1)
Output
Store A, Hold B
Store A in both registers
Store A, Hold B
Store A in both registers
Unspecified(1
X
X(2)
Output
Input
Input
Hold A, Store B
Store B in both registers
Hold A, Store B
Store B in both registers
X
X
L
H
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
L
H
X
X
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
Stored A Data to B Bus and
Stored B Data to A Bus
Al THRU As Bl THRU Bs
NOTES:
1. The data outputfunctions may be enabled or disabled by various signals at the GAB or GB'A inputs. Data input functions are always enabled, i.e., data atthe
bus pins will be stored on every low-to-high transition on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H
= HIGH, L = LOW,
X
= Don't Care, t
LOW-to-HIGH Transition
S10-147
IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED BLOCK DIAGRAM
1 OF 8 CHANNELS
FCT652
ONLY
I
I
I
I
I
I
J
FCT652
ONLY
---....y-----------------------~
TO 7 OTHER CHANNELS
~
GAB
'L
~
'G'!3A CPAB CPBA SAB SBA
L
X
X
X
GAB
l
H
REAL-TIME TRANSFER
BUS BTO BUS A
'G'!3A CPAB CPBA SAB SBA
H
X
X
L
L
Gl3A
H
X
H
CPAB CPBA SAB SBA
t
X
t
X
t
t
L
X
~
~
GAB
X
REAL-TIME TRANSFER
BUSATO BUS B
X
X
X
X
X
X
GAB
H
Gl3A
CPAB CPBA SAB SBA
L.HorL HorL H
H
TRANSFER
STORED DATA
TO A AND/OR B
STORAGE FROM
A AND/OR B
S10-148
IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
-0.5 to +7.0
Terminal Voltage
VTERM (3) with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-0.5 to Vee
MILITARY
-0.5 to +7.0
-0.5 toVcc
UNIT
SYMBOL
V
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
CliO
I/O Capacitance
CONDITIONS TYP.
MAX. UNIT
"'N = OV
6
10
pF
VOUT = OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
DC Output Current
120
120
mA
lOUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Input and Vce terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vec - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military'TA = -55°C to + 125°C' \be = 50V+10%
SYMBOL
VIH
"'L
IIH
TEST CONDITIONS(1)
PARAMETER
TYP.(2)
MAX.
UNIT
Guaranteed Logic High Level
2.0
-
-
V
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
VI
I~ut HIGH Current
( xcept I/O pins)
VI
Vce = Max.
IlL
MIN,
Input HIGH Level
VI
Input LOW Current
(Except I/O pins)
VI
= Vcc
= 2.7V
= 0.5V
= GND
= Vee
= 2.7V
-.
-
5(4)
-
-15
_5(4)
~A
-5
"'K
Clamp Diode Voltage
\bc
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc
-60
-120
mA
VHC
Vcc
VHe
Vcc
2.4
4.3
IIH
VI
In?cut HIGH Current
(I 0 pins only)
Vee
IlL
VOH
VOL
VI
= Max.
VI = 0.5V
In?cut LOW Current
(I 0 pins only)
Output HIGH Voltage
Output LOW Voltage
VI = GND
= Min., IN = -18mA
= Max~3), Vo = GND
Vce = 3V, '-"N = VLC or VHc .IoH = -32 ~
10H = -300~A
Vcc = Min.
10H = -12mA MIL.
'-"N = '-"H or '-"L
10H = -15mA COM'L.
Vcc = 3V, '-"N = VLe or VHC , 10L = 300~
10L
Vcc = Min.
VIN = '-"H or '-"L
=
300~A
10L = 48mA MIL.
10L = 64mA COM'L.
VH
-
Input Hysteresis on Clock Only
15
15(4)
-15(4)
2.4
4.3
-
-
GND
VLC
-
GND
VLe
-
0.3
0.55
-
0.3
0.55
-
200
-
~A
V
V
mV
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum IoL values per output, for 8 outputs turned on simultaneously. Total maximum 10L (all outputs) is 512mA for commercial and 384mA
for military. Derate 10L for number of outputs turned on simultaneously.
S10-149
...
_---------------------
IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
-
VLC - 0 2V· VHC = Vcc - 0 2V
SYMBOL
PARAMETER
TEST CONDITIONS (1)
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~ VHC ; '-"N ~ \tc
fcp = fl = 0
Alcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current(4)
Vcc= Max.
Outputs Open
GAB = GND
GSA = GND
SAB = CPAB = GND
SBA = Vcc
One Input Toggling
50% Duty Cycle
ICCD
Ic
Total Power Supply Current(5)
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
GAB = GND
GSA = GND
SAB = CPAB = GND
SBA = Vcc
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
MIN.
TYP.(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
'-"N ~ VHC
\'IN ~ VLC
-
0.15
0.25
mAl
MHz
\'IN ~ VHC
\'IN ~ VLC
(FCT)
-
1.5
4.0
VIN = 3AVor
VIN = GND
-
2.0
6.0
mA
\Cc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
GAB = GND
GSA = GND
SAB = CPAB = GND
SBA = Vcc
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
\'IN ~ VHC
\'IN ~ VLC
(FCT)
-
3.75
7.8(5)
VIN = 3AVor
VIN = GND
-
6.0
16.8(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input MN= 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPLrrS + IDYNAMIC
Ic = Icc + Alcc DHNT + Icco (fcp/2 + fl NI )
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3AV)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = DynamiC Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-150
IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/7 4FCT651 A/652A
IDT54/74FCT651/652
SYMBOL
CONDITION(1 1
PARAMETER
COM'L.
TYP.(31
MIN.(21 MAX.
MIL
MIN!21
COM'L
TYP.(31
MAX.
MIN.(21
MAX.
MIL
MIN.(21
UNIT
MAX.
tpLH
tpHL
Propagation Delay
Bus to Bus
8.0
2.0
9.0
2.0
10.0
-
-
-
-
-
ns
tpLH
tpHL
Propagation Delay
Clock to Bus
8.0
2.0
9.0
2.0
11.0
-
-
-
-
-
ns
tpLH
tpHL
Propagation Delay
SBA or SAB to A or B
10.0
2.0
11.0
2.0
12.0
-
-
-
-
-
ns
tpZH
tpZL
Output Enable Time
Enable to Bus
9.0
2.0
10.0
2.0
12.0
-
-
-
-
-
ns
t pHZ
tpLZ
Output Disable Time
Enable to Bus
9.0
2.0
10.0
2.'0
12.0
-
-
-
-
-
ns
tsu
Set-upTime
HIGH or LOW
Busto Clock
3.0
4.0
-
4.5
-
-
-
-
-
-
ns
tH
Hold Time
HIGH or LOW
Busto Clock
1.0
2.0
-
2.0
-
-
-
-
-
-
ns
tw
Pulse Width,
HIGH or LOW
4.0
6.0
-
6.0
-
-
-
-
-
-
ns
C L = 50pF
RL = 5000
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
ORDERING INFORMATION,
IDTXXFCT
xxx
Device Type
X
Package
x
Process/Temperature
y:l~k
Commercial
Compliant to MIL-STO-883, Class B
P
D
~
________________~ E
J
L
SO
651
652
~--------------------------~651A
652A
~
____________________________-4154
174
S10-151
Plastic DIP
CERDIP
CERPACK
Plastic Leadless Chip Carrier
Leadless Chip Carrier
Small Outline IC
Inverting Octal Transceiver/Register
Non-inverting Octal Transceiver/Register
Inverting Fast Octal Transceiver/Register
Non-inverting Fast Octal Transceiver/Register
-55°C to + 125°C
O°Cto +70°C
t;)
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
Integrated Device~Inc.
lOT 54/74FCT821A/B-
lOT 54/74FCT826A/B*
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29821-26 bipolar registers in pinout!
function, speeds and output drive over full temperature and
voltage supply ,extremes
The IDT54/74FCT800 series is built using advanced
CEMOS™, a dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider addressl
data paths or buses carrying parity. The IDT54/74FCT821 and
IDT54/74FCT822 are buffered, 10-bit wide versions of the popular
'374/'534 functions. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN)
and Clear (CLR) - ideal for parity bus interfacing in highperformance microprogrammed systems. The IDT54/74FCT825
and IDT54/74FCT826 are 8-bit buffered registers with all the '823/4
controls plus multiple enabl~OEl , OE2, OE3l.!9 allow multiuser
control of the interface, e.g., CS, DMA and RD/WR. They are ideal
for use as an output port requiring high IOl/loH.
All of the IDT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for lowcapacitance bus loading in the high impedance state.
• High-speed parallel registers with positive edge-triggered
D-type flip-flops
'
- Non-inverting CP-Y tpD = 7.5ns typo
- Inverting CP-Y tpD = 7.5ns typo
• Buffered common Clock Enable (EN) and asynchronous Clear
input (CLR)
• IOL = 48mA (commercial), 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5~W typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 series (5~A max.)
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
CLOCK
ENABLE
01
Do
EN
Yo
Yn- 1
Yl
PRODUCT SELECTOR GUIDE
10-BIT
I Non-inverting
I Inverting
DEVICE
9-BIT
8-BIT
54/74FCT821A/B 54/74FCT823A/B 54/74FCT825A1B
54/74FCT822A/B 54/74FCT824A/B 54/74FCT826A1B
CEMOS is a trademark of Integrated Device Technology, Inc.
*Advance information only for IDT54/74FCT822 and IDT54/74FCT826.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-4004/-1
1989 Integrated Device Technology, Inc.
S10-152
IDT54/74FCT821 A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/7 4FCTS21 /IDT54/7 4FCTS22 10-BIT REGISTERS
Vee
Do
Dl
od'~~-»~-;
INDEX
LJLJU;;UULJ
Yo
Y1
Y2
D2
D3
D4
Ds
06
4
08
09
GND
CP
3 2U282726
2S[
24 [
Y3
Y4
YS
Y6
Y7
Y8
Y9
D7
LOGIC SYMBOLS
D4
23 [
:17
NC :18
Os :19
22[
L28-1
21 [:
Y2
Y3
19[
UUU;;ULJU
4 3 2 U 28 27 26
1
2S[
O2 :1 s
24[
0 3 :16
23[
0 4 :17
Y2
Y3
Y4
20[
CP
DE"
12 13 14 lS 16 17 18
nnnnnnn
d'o@~~~>
C)
DIP/CERPACI(JSOIC
TOP VIEW
LCC
TOP VIEW
IDT54/7 4FCTS23/IDT54/7 4FCTS24 9-BIT REGISTERS
Vee
Do
Dl
O2
Yo
Y1
Y2
03
Y3
Y4
YS
D4
Os
D7
08
00
8o~
Z>'>'>-
22[
NC
CP
Ds
:19
21 [
06
D7
:110
20[
Ys
Y6
EN
19[
Y7
NC :18
Y6
Y7
Y8
D6
~o~o
INDEX
L28-1
:111
12 13 14 lS 16 17 18
ern
EN
nrnnnnn
GND
CP
d'~OOD..ffi>
ZZO
ern
DE"
C)
DIP/CERPACI(JSOIC
TOP VIEW
LCC
TOP VIEW
IDT54/7 4FCTS25/IDT54/7 4FCTS26 'S-BIT REGISTERS
DEl
Vee .
DE2
Do
0E"3
O2
Yo
Y1
Y2
03
D4
Os
Y3
Y4
Ys
D6
Y6
Y7
01
07
d'~~~-»~~
INDEX
UUUI;LJUU
4 3 2U282726
1
2S[
0 1 :1 s
24[
O2 :16
23[
0 3 :17
D4
Ds
D6
Y1
Y2
Y3
22[
NC
CP
:19
21 [
:110
20[
Y4
Ys
EN
19[
Y6
NC :18
L28-1
:1 11
12 13 14 lS 16 17 18
ern
crn
EN
nnnnnnn
DE"1
GND
CP
0 D..ffi ~
o... ~ 0ZZO
DE"2
C)
DIP/CERPACI(JSOIC
TOP VIEW
LCC
TOP VIEW
S10-153
D
Y
Y4
NC
YS
Y6
Y7
0 6 :110
0 7 :J 11
10
D
DE"3
IDTS4/74FCT821A/B·26A/B HIGH·PERFORMANCE
CMOS BUS INTERFACE REGISTERS
MILITARV AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
DESCRIPTION
I/O
DI
I
The D flip-flop data inputs.
ern
I
For both Inverting and non-Inverting registers, when
the clear input is LOW and at: is LOW, the Q I
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-ta-HIGH transition.
VI ,VI
0
The register three-state outputs.
EN
I
at:
I
Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the Q I output on the
LOW-ta-HIGH clock transition. When the clock
enable is HIGH, the QI outputs do not change state,
regardless of the data or clock input transitions.
Output Control. When the (jE' input is HIGH, the YI
are in the high impedance state. When the
input is LOW, the TRUE register data is present at
the YI outputs.
~uts
FUNCTION TABLES (1)
IDT54/74FCT821/23/25
INTERNAL
OUTPUTS
INPUTS
~
em rn
FUNCTION TABLES (1)
IDT54/74FCT822/24/26
0,
CP
QI
VI
L
H
Z
Z
High Z
INTERNAL
OUTPUTS
INPUTS
FUNCTION
OE
CCR
'EN
0,
H
H
X
X
L
L
L
H
CP
FUNCTION
Q,
V,
H
L
Z
Z
HighZ
H
H
X
X
L
L
L
H
H
L
L
L
X
X
X
X
X
L
L
Z
L
Clear
H
L
L
L
X
X
X
X
X
L
L
Z
L
Clear
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
Hold
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
Hold
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
t
t
t
t
L
H
L
H
Z
Z
L
H
Load
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
t
t
t
t
H
L
H
L
Z
Z
H
L
Load
+
X
NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change,
HIGH Transition, Z = High Impedance
+
X
NOTE:
t
= LOW-to-
1. H = HIGH,L = LOW,X = Don'tCare,NC = No Change,
HIGH Transition, Z = Hig~J!J1pedance
S10-1S4
t
= LOW-to-
IDT54/74FCT821A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
CIN
COUT
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
100
100
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
Output Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT = OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; \Cc = 5.0V±5%
Military: TA = -55°C to +125°C; Vcc = 5.0V±10%
MIN.
TYP,<2)
MAX.
UNIT
\IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
\Il
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
SYMBOL
IIH
TEST CONDITIONS(1)
PARAMETER
Input HIGH Current
Vcc = Max.
IlL
loz
-
VI = 2.7V
VI = GND
-
Vo = Vcc
-
Vo = 2.7V
-
Vo = 0.5V
-
-
-1<1 4)
Vo = GND
-
-
-10
VI = 0.5V
Input LOW Current
Off State (High Impedance)
Output Current
VI = Vcc
-
Vcc = Max.
5
5(4)
-5(4)
~A
-5
10
10(4)
~A
VIK
Clamp Diode Voltage
Vcc = Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = MaxP~ Vo = GND
-75
-120
mA
2.4
4.3
-
Vcc = 3V, VIN = VlC or VHC , 10l = 30~
-
GND
VlC
10l = 300~A
-
GND
VlC
10l = 32mA MIL.
-
0.3
0.5
10l = 48mA COM'L.
-
0.3
0.5
Vcc = 3V, "'N = VlC or VHC , 10H = -32~
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
VHC
Vcc
VHC
Vcc
= -15mA MIL.
2.4
4.3
loi-i = -24mA COM'L.
10H = -300~A
Vcc = Min.
VIN = "'H or Vil
10H
Vcc = Min.
"'N = VIH or"'l
VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-155
-
V
V
mV
IDT54/74FCT821 A/B·26A!B HIGH·PERFORMANCE
CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
Icc
Quiescent Power Supply Current
Alcc
Quiescent Power Supply Current
TIL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
:s
Total Power Supply Current (6)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
2.0
mA
VHC
VLC
-
0.15
0.25
mA!
MHz
\IN ~ VHC
'-"N :s VLC
(FCT)
-
1.5
4.0
-
2.0
6.0
'-"N ~ VHO
'-"N
VLC
(FCT)
:s
-
3.75
7.8(5)
VIN = 3.4Vor
VIN = GND
-
6.0
16.8(5)
MIN.
VLC
\bc = Max.
Outputs Open
DE = GND
One Bit Toggling
50% Duty Cycle
Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
atfl = 5MHz
50% Duty Cycle
Ic
TYP.(2)
TEST CONDITIONS(1)
Vcc = Max.
VIN ~ VHC ; \IN
fcp = fl = 0
Vcc= Max.
Outputs Open
fop = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle
\IN
~.
\IN
:s
VIN
VIN
= 3.4Vor
= GND
mA
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are atVcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alee DHNT + leeD (fcp/2 + ~ NI )
Icc = Quiescent Current
AI ee = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non·Register Devices)
fl = Input Frequency
.
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-156
IDT54/74FCT821A1B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS
MILITARV AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
tpLH
tpHL
TEST (1)
CONDITIONS
DESCRIPTION
PARAMETER
CL
RL
~agation
=
Delay Clock to VI
LOW)
I DT54/74FCT821 A-26A
I DT54/74FCT821 B-26B
COM'L
MIL
MIN.(2) MAX. MIN.(2) MAX.
COM'L.
MIL
MIN. (2) MAX. MIN.(2) MAX.
= 50pF
= 5000
= 300pF (3)
= 5000
UNIT
-
10
-
11.5
-
7.5
-
8.5
ns
tpLH
tpHL
(0
-
20
-
20
-
15
-
16
ns
tsu
Data to CP Set-up Time
4
-
4
3
-
3
-
ns
tH
Data CP Hold Time
2
-
2
-
1.5
-
1.5
-
ns
tsu
Enable (ENS) to CP
Set-upTime
4
-
4
-
3.0
-
3.0
-
ns
tsu
Enable (ENS) to CP
Set-upTime
4
-
4
-
3.0
-
3.0
-
ns
CL
RL
CL
RL
= 50pF
= 5000
tH
Enable (8iJ) Hold Time
2
-
2
-
0
-
0
-
ns
t pHL
Propagation Delay, Clear to Yj
-
14
-
15
-
9.0
-
9.5
ns
tsu
Clear Recovery (CLR S) Time
6
tPWH
Clock Pulse Width
tpWL
Clear (CLR
tpwL
tpZH
tpZL
=
-
6.0
-
6.0
-
ns
7
-
7
HIGH
7
-
6.0
-
6.0
-
ns
I LOW
7
-
7
6.0
-
6.0
-
ns
6
-
7
-
6.0
-
6.0
-
ns
-
12
-
13
-
8
-
9
ns
-
23
-
25
-
15
-
16
ns
-
9
-
10
-
6.5
-
7
ns
-
8
-
9
-
7.5
-
8
ns
I
LOW) Pulse Width
Output Enable Time ~
StoYI
tpZH
tPZL
tpHZ
tpLZ
Output Disable Time ~
tOYI
S
tpHz
tpLZ
= 50pF
= 5000
CL . = 300pF (3)
RL = 5000
CL = 5pF(3)
RL = 5000
CL = 50pF
RL = 5000
CL
RL
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
X
X
Package
Process
I
I Blank
~B
'-----------j
1 -_ _ _ _ _ _ _ _ _ _ _ _ _ _- - \
MIL-STD-883, Class B
P
D
E
L
SO
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
821A
821B
822A
822B
823A
823B
824A
824B
825A
825B
826A
826B
10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
1D-Bit Inverting Register
Fast 10-Bit Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
8-Bit Inverting Register
Fast 8-Bit Inverting Register
54
' - - - - - - - - - - - - - - - - - - - - - - - ; 74
S10-157
Commercial
-55°C to + 125°C
O°Cto +70°C
t;)
Integrated Device1echnology.1nc.
HIGH-PERFORMANCE
.CMOS BUFFERS
IDT 54/74FCT827A/B
IDT 54/74FCT828A/B*
FEATURES:
DESCRIPTION:
• Faster than AMD's Am29827 -28 series
• Equivalent to AMD's Am29827-28 bipolar buffers in pinout!
function, speeds and output drive over full temperature and
voltage supply extremes
• H[gh-speed buffers
- Non-inverting tpD = 3.5ns typo
- Inverting tpD = 4.0ns typo
•
10L = 48mA (commercial), 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 Series (5jJA max.)
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 Series is built using advanced
CEMOS ™ , a dual metal CMOS technology.
The IDT54/74FCT827A/B and IDT54/74FCT828A/B 10-bit bus
drivers provide high-performance bus interface buffering for wide
data/address paths or buses carrying parity. The 10-bit buffers
have NOR-ed output enables for maximum control flexibility. All
buffer data inputs have 200mV minimum input hysteresis to
provide improved noise rejection.
All of the IDT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for
low-capacitance bus loading in the high impedance state.
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT827A/B-IDT5474FCT828A/B 10-BIT BUFFERS
PRODUCT SELECTOR GUIDE
10-BIT BUFFER
I
I
Non-inverting
IDT54174FCT827AlB
Inverting
IDT54174FCT828A1B
CEMOS is a trademark of Integrated Device Technology, Inc.
*Advance information only for IDT54/74FCT828.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
05C-4010/-1
1989 Integrated Device Technology
S10-158
I DT54/74 FCT827 A/B-IDT54/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS
MILITARV AND COMMERCIAL TEMPERATURE RANGES
LOGIC SYMBOL
PIN CONFIGURATIONS
IOT54/74FCT827A/B/IOT54/7 4FCT828A/B
o~
INDEX
0E'1
Do
Vee
Vo
0
o~ 0
0
Z
~~.;
UUU;;ULJU
4 3 2 U2S272S
2S [:
V2
Y3
VI
V2
D2 :1 s
D3
D4
V3
V4
D4 :17
NC :1 8
Ds
Vs
21 [
Vs
~1
Ds
Ve
V7
Ds :] 9
De :1 10
20 [:
Vs
0E'2--~U
D7 :1 11
19
£:
V7
Dl
D2
D7
Ds
D9
GND
D3
:]6
24
£:
23 [
22
L28-1
£:
12 13 14 IS Ie 17 18
Vs
Y9
nnnnnnn
0E'2
OOaZ~>'>-
"'0 0
00
DIP/CERPACK/SOIC
TOP VIEW
'" '"
DO- 9 - - - - - - 1 ' - 1
:>--1--- VO- 9
V4
NC
00
LCC
TOP VIEW
PIN DESCRIPTION
NAME
I/O
OE'I
I
DESCRIPTION
DI
I
10-bit data input.
VI
0
10-bit data output.
When both are LOW the outputs are
enabled. When either one or both are HIGH
outputs are High Z.
the
FUNCTIONAL TABLES
IOT54/74FCT827A/B (NON-INVERTING)(l)
INPUTS
OUTPUT
eEl
0E 2
01
VI
L
L
L
L
L
H
L
H
H
X
X
H
X
X
Z
NOTE:
1. H = HIGH, L
Z
= LOW, X = Don't Care, Z
IDT54/74FCT828A/B (INVERTING)(l)
INPUTS
FUNCTION
OUTPUT
FUNCTION
O"E l
0E 2
01
VI
Transparent
L
L
L
L
L
H
H
L
Transparent
Three-State
H
X
X
H
X
X
Z
Z
Three-State
= High Impedance
NOTE:
1. H = HIGH, L = LOW, X
S10-159
= Don't Care, Z = High Impedance
I DT54/74FCT827A/B-IDT54/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS '.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
... Terminal Voltage
with Respect to
VTERM
GND
TA
Operating
Temperature
TSIAS
Temperature
Under Bias
TSTG
Storage
Temperature
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-0.5 to +7.0
o to
CAPACITANCE
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
CIN
COUT
-55 to + 125
°C'
-55 to +125
-65 to +135
°C
-55 to +125
-65 to +150
°C
+ 70
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
100
100
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
Input Capacitance
Output Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT = OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = DoC to + 70°C; 'bc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
TYPP)
MAX.
UNIT
"IH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
"IL
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
VI = Vcc
-
-
5
VI = 2.7V
-
-
5(4)
VI = 0.5V
-
-
-5(4)
VI = GND
-
-
-5
Vo = Vcc
-
10
Vo = 2.7V
-
-
10(4)
Vo = 0.5V
-
-
-1d4 )
Vo = GND
Input HIGH Current
IIH
Vcc = Max.
Input LOW Current
IlL
~A
loz
Off State (High Impedance)
Output Current
Vcc = Max.
-
-
-10
"IK
Clamp Diode Voltage
Vcc : Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = Max~3), Vo = GND
-75
-120
-
mA
Vcc = 3V, \'IN = VLC or VHC , IOH =-32~
VHC
Vcc
VOH
Output HIGH Voltage
Vcc = Min.
\'IN = \'IH or \'IL
IOH = -300~A
VHC
Vcc
10H = -15mA MIL.
2.4
4.0
IOH = -24mA COM'L.
2.4
4.0
-
-
GND
VLC
-
GND
VLC
0.3
0.5
0.3
0.5
Vcc = 3V, \'IN = VLC or VHC , 10L = 300~
VOL
.
'
10L = 300~A
Output LOW Voltage
Vcc = Min .
\'IN = \'IH or\'lL
10L = 32m A MIL.
IOL = 48mA COM'L.
VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-160
-
-
~A
V
V
mV
IDT54/74FCT827A/B-I DT54/74FCT828A1B
HIGH-PERFORMANCE CMOS BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = vcc - 0.2V
SYMBOL
TEST CONDITIONS (1)
PARAMETER
Icc
Quiescent Power Supply Current
Vcc = Max.
VIN ~VHC; "'tN ~ VLC
f, = 0
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
VIN = 3.4V(3)
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
~= GND
TIA = GND or Vcc
One Input Toggling
50% Duty Cycle
ICCD
Total Power Supply Current
TYP.(2)
MAX.
UNIT
mA
-
0.001
1.5
-
0.5
2.0
\'IN ~ VHC
\'IN ~ VLC
-
0.15
0.25
\'IN ~ VHC
\'IN ~ VLC
(FCT)
-
1.5
4.0
V'N = 3.4V
\'IN = GND
-
1.8
5.0
VIN ~ VHC
VIN ~ VLC
(FCT)
-
3.0
6.5(5)
VIN = 3.4V
VIN = GND
-
5.0
14.5(5)
..
Vcc = Max.
Outputs Open
f, = 10MHz
50% Duty Cycle
C51: = GND
One Bit Toggling
Ic
MIN.
mAl
MHz
mA
(6)
Vcc = Max.
Outputs Open
f, = 2.5MHz
50% Duty Cycle
DE = GND
Eight Bits Toggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQU'ESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (\'IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f, = Input Frequency
N, = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-161
._.._--_ ........._ - - - - - -
mA
I DT54/74FCT827A/B-IDT54174FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS
MILITARV AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54174FCT827A/28A
TEST (1)
CONDITIONS
DESCRIPTION
PARAMETER
tpLH
tpHL
Propagation Delay from 0 1 to Vi
IDT54/74 FCT827AlB (Non-inverting)
tpLH
tpHL
t pLH
tPHL
Propagation Delay from 0 1 to VI
IDT54/74FCT828A/B (Inverting)
tpLH
tpHL
tpZH
tPZL
Output Enable Time OE to VI
tpZH
tpZL
tpHZ
t pHL
Output Disable Time OE to VI
tpHZ
tpHL
IDT54/74FCT827B/28B
MIL
COM'L.
MIL
UNIT
MINP) MAX. MIN.(2) MAX. MIN.(2) MAX. MIN.(2) MAX.
= 50pF
= 500n
CL = 300pF(3)
RL = 500n
CL = 50pF
RL = 500n
CL = 300pF(3)
RL = 500n
CL = 50pF
RL = 500n
CL = 300pF(3)
RL = 500n
CL = 5pF(3)
RL = 500n
CL = 50pF
RL = 500n
CL
RL
COM'L.
-
8
-
9
-
5.0
-
6.5
ns
-
15
-
17
-
13.0
-
14.0
ns
-
9
-
10
-
5.5
-
6.5
ns
-
14
-
16
-
13.0
-
14.0
ns
12
-
13
-
8.0
-
9.0
ns
-
23
25
-
15.0
-
16.0
ns
-
9
-
10
-
6.0
-
7.0
ns
-
10
-
10
-
7.0
-
8.0
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
ORDERING INFORMATION
IDTXXFCT
xx
x
Device Type
Process
Y:Mk
P
D
L
SO
827A
828A
827B
828B
Non-inverting 10-Bit Buffer
Inverting 10-Bit Buffer
Fast Non-inverting 10-Bit Buffer
Fast Inverting 10-Bit Buffer
--1 54
1-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
74
S10-162
MIL-STD-883. Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
~--------------------~ E
'-----------------------------------i
Commercial
-55°C to + 125°C
O°C to + 70°C
lntesJated Device'irlmology. Inc:.
lOT
lOT
lOT
lOT
FAST CMOS
PARITY BUS
TRANSCEIVER
54/74FCT833A/B
54/74FCT834A/B*
54/74FCT853A/B
54/74FCT854A/B*
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29833-34 and Am29853-54 bipolar
parity bus transceivers in pinout/function, speeds and output
drive over full temperature and voltage supply extremes
The IDT54/74FCT833/34/53/54 are high-performance bus
transceivers designed for two-way communications. They each
contain an 8-bit data path from the R (port) to the T (port), a 8-bit
data path from the T (port) to the R (port), and a 9-bit parity checker/
generator. Two options are available: the IDT54/74FCT833/34 register option and the IDT54/74FCT853/54 latch option. With the register option, the error flag can be clocked and stored in a register
and read at the ERA output. The clear (ClA) input is used to clear
the error flag register. With the latch option, the error can be either
passed, stored, sampled or cleared at the error flag output by using
the EN and ClA controls.
The output enables OET and OER are used to force the port outputs to the high-impedance state so that the device can drive bus
lines directly. In addition, OERand OET can be used to force a parity error by enabling both lines simultaneously. This transmission
of inverted parity gives the designer more system diagnostic capability. The IDT54/74FCT833 and IDT54/74FCT853 are non-inverting, while the IDT54/74FCT834 and IDT54/74FCT854 present inverting data at the outputs. The devices are specified at 48mA and
32mA output sink current over the commercial and military temperature ranges, respectively.
• High speed bidirectional bus transceiver for processororganized devices
Non-inverting propagation delay = 7.0ns max.
Inverting propagation delay = 7.0ns max.
• Buffered direction three state control
• Error Flag with open-drain output
• 10L = 48mA(commercial) and 32mA (military)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 series (5~A max.)
• Available in Plastic DIP, CERDIP, lCC, PlCC and SOIC
• Product available in Radiation Tolerant and Enhanced
versions
• Military product compliant to Mll-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT833
(Device Shown Non-inverting)
I DT54/74FCT853
(Device Shown Non-inverting)
(1)
(1)
PARITY
ClK
NOTE:
1. Non-inverting buffer for IDT54/74FCT833/53, inverting buffer for
IDT54/74FCT834/54, note that the inverting device converts the positive logiC "R" bus levels to negative levels on"r bus.
CEMOS is a trademark of Integrated Device Technology, Inc.
*Advance information only for IDT54/74FCT834 and IDT54/74FCT854.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-4012Jl
S10-163
IDT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A/B AND.
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74 FCT853/54
IDT54/74 FCT833/34
IDT54/74FCT853/54
I DT54/74 FCT833/34
VCC
ITER
Ro
R1
R2
R3
R4
ITER
Ro
R1
R2
R3
To
T1
T2
T3
R5
R6
R7
ERR
ClR
GND
To
T1
T2
R5
R6
R7
Ta
T7
PARITY
ERR
OET
CLK
GND
cr:
~
0
Z>I-"II
••
,
~ o~ 0
o.
]5
]6
]7
]6
0
0
0
~
a:a:IOZ>1-"1-
INDEX
'-' ..... ....,
4 3 2 .,. 2627 26 [
25
24[
23[
J28-1
22[:
L28-1
21[
]9
20[
] 10
19[
:J 11
1213 14 15 1617 16
nnnnnnr1
.....,'-'....,::
T5
Ta
T7
PARITY
ClR
a:a:
••••••••
ERR
ClR
GND
NC
ClK
OE T
PARITY
0
0
~ o~ 0
INDEX
T3
T4
R4
T4
T5
cr:
VCC
ERR :J
R1
Ro
CIA]
OER GND :1
NC
NC]
EN:l
Vcc
To
OET:l
T1 PARITY :J
5
~ ~ ~ ~ ~6 ~ ~25 [..
6
7
J28-1
6
L28-1
9
21[
10
20[
11121314 15 1617 1619 [
nnnnnnn
ffiFdOO~~~
dt§Zdroa;
OET
EN
>->-
UUUIIUUU
D2
D3
:J s
:16
4
3
2 U
28 27 26
D4
:J7
NC
:1 a
Ds
Ds
D7
:19
21[
:J 10
20[
22[
L28-1
19[
:1 11
12 13 14 IS IS 17 IS
ern
PRE"
nnnnnnn
GND
LE
o ISU&Z
0 U
DIP/CERPACK/SOIC
TOP VIEW
Ys
Ys
Y7
LE
~
ern
OE
D- [
U
a:>-.,
LCC
TOP VIEW
IDT54/7 4FCT845/IDT54/7 4FCT846 8-BIT LATCHES
0E"1
0E"2
Do
Dl
D2
D3
Y2
Y3
D4
Y4
Ys
Ys
Y7
Ds
Os
D7
ern
d'~~~Jl~)?
INDEX
Vee
0E"3
Yo
Y1
~
GND
LE
Dl
D2
:J s
:16
D3
:1 7
NC
:J S
:J 9
D4
Ds
Ds
UUUIIUUU
4 3 2 U2S2726
L28-1
Y1
Y2
23[
Y3
NC
22[
21[
20[
:1 10
:J 11
19[
12 13 14 IS IS 17 IS
Y4
Ys
Ys
LE
PRE"
ern
nnnnnnn
OE 1
Q~OU
ZZ ~[~
0E2
C)
DIP/CERPACK/SOIC
TOP VIEW
2S[
24[
LCC
TOP VIEW
S10-172
0E"3
D
IDT54/74FCT841A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
DESCRIPTION
I/O
IDT54/74FCT841/43/45 (Non-inverting)
When ern is low, the outputs are LOW if~ is LOW.
When ern is HIGH, data can be entered into the
latch.
ern
I
01
I
The latch data inputs.
LE
I
The latch enable input. The latches are transparent
when LE is HIGH. Input data is latched on the HIGHto-LOW transition.
YI
0
The 3-state latch outputs.
C5"E:
I
The output enable control. When C5"E: is LOW, the
outputs are enabled. When OE is HIGH, the outputs
VI are in the high-impedance (off) state.
PRE:
I
Preset line. When PRE is LOW, the outputs are HIGH
if C5"E: is LOW. Preset overrides CCR.
IDT54/74FCT842/44/46 (Inverting)
When ern is low, the outputs are LOW ifC5"E" is LOW.
When CCR is HIGH, data can be entered into the
latch.
C'[R
I
01
I
The latch inverting data inputs.
LE
I
The latch enable input. The latches are transparent
when LE is HIGH. Input data is latched on the HIGHto-LOW transition.
VI
0
The 3-state latch outputs.
OE
I
The output enable control. When DE is LOW, the
outputs are enabled. When C5"E: is HIGH, the outputs
VI are in the high-impedance (off) state.
PRE"
I
Preset line. When PRE is LOW, the outputs are HIGH
if OE is LOW. Preset overrides ern.
FUNCTION TABLES (1)
IDT54/74FCT841/43/45
FUNCTION TABLES (1)
IDT54/7 4FCT842/ 44/ 46
INTER- OUTNAL
PUTS
INPUTS
INTER- OUTPUTS
NAL
INPUTS
FUNCTION
'C5E:
FUNCTION
0,
01
YI
X
X
X
Z
High Z
H
H
L
Z
High Z
H
L
H
Z
High Z
H
L
X
NC
Z
Latched (High Z)
L
H
H
L
L
Transparent
H
L
H
L
H
H
Transparent
H
L
L
X
NC
NC
L
L
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
Latched (High Z)
L
H
H
L
X
L
Z
Latched (High Z)
Latched (High Z)
H
L
H
L
X
H
Z
Latched (High Z)
CLR
PRE
DE
LE
01
01
YI
H
H
H
X
X
X
Z
High Z
H
H
H
H
H
H
H
L
L
Z
High Z
H
H
H
H
H
H
H
H
H
Z
High Z
H
H
H
H
H
H
L
X
NC
Z
Latched (High Z)
H
H
H
H
L
H
L
L
L
Transparent
H
H
H
H
L
H
H
H
H
Transparent
H
H
H
L
L
X
NC
NC
Latched
H
H
L
L
X
X
H
H
Preset
H
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
H
L
H
L
X
H
Z
CLR
PRE
LE
Latched
NOTE:
NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, i = LOW-toHIGH Transition, Z = High Impedance
·1. H= HIGH, L = LOW, X = Don't Care, NC = No Change, i = LOW-toHIGH Transition, Z = High Impedance
S10-173
_...__._-----_._--_._-----
.... _.......... _.. _-- .. --.--..
----------
---_
...
__..
_-_._..
_-_ ..
_-----
IDT54/74FCT841A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
CAPACITANCE
(1)
COMMERCIAL
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MILITARY
-0.5 to +7.0
UNIT
SYMBOL
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
lOUT
DC Output Current
100
100
mA
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
CIN
Input Capacitance
COUT
Output Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT = OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following conditions apply unless otherwise specified:
VLe = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to + 70°C; 'te = 5.0V±5%
Military: TA = -55°C to +125°C; Vce = 5.0V±10%
TEST CONDITIONS(l)
MIN.
TYP.(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
-
-
5
SYMBOL
PARAMETER
"'I
IIH
Input HIGH Current
"'I
=
2.7V
-
-
5(4)
"'I
= 0.5V
-
-5(4)
"'I
= GND
-
Vee = Max.
IlL
= \be
Input LOW Current
Vo = \be
Vo
loz
Off State (High Impedance)
Output Current
Vee
=
V,K
Clamp Diode Voltage
Vee
los
Short Circuit Current
Vee
= Min., IN =
= Max!3), \6
Max.
Vo
= 2.7V
= 0.5V
= GND
-
-1d4 )
jJA
-
-10
-1.2
V
= GND
-75
-120
-
mA
VHe
Vee = Min.
"'IN = "'IH or "'IL
Vee
"'IN
-
10
-0.7
Vee
-
InH = -300jJA
VHe
\be
-
10H = -15mA MIL.
2.4
4.3
-
'oH = -24mA COM'L.
2.4
4.3
-
-
GND
VLC
ioL = 300jJA
Output LOW Voltage
10(4)
-
Vee = 3V, "'IN = VLC or VHC • IOL = 300jJA
VOL
-
Vee = 3V, "'IN = VLC orVHc.l oH = -32jJA
Output HIGH Voltage
-5
-18mA
Vo
VOH
-
-
jJA
= Min.
= "'IHor VIL
ioL
10L
= 32mA MIL.
= 48mA COM'L.
-
GND
VLe
-
0.3
0.5
-
0.3
0.5
VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
S10-174
-
V
V
mV
IDT54/74FCT841 A/B-46A/B H IGH-P ERFOR MANCE
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =
0.2V; VHC = Vcc - 0.2V
SYMBOL
Icc
Alcc
ICeD
TEST CONDITIONS
PARAMETER
Quiescent Power Supply Current
Quiescent Power Supply Current
. TIL Inputs HIGH
Dynamic Power Supply Current (4)
Total Power Supply Current
MIN.
TYP.(2)
MAX.
UNIT
Vcc = Max.
VIN ~VHC; "IN ~ VLC
fl = 0
-
0.001
1.5
mA
Vcc = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
"IN ~ VHC
VIN ~ VLC
-
0.15
0.25
mAl
."IN ~ ~c
"IN~ VLC
(FCT)
-
1.5
4.0
VU:.j = 3.4Vor
VIN = GND
-
1.8
5.0
Vcc= Max;
Outputs Open
BE = GND
LE = \bc
One Input Toggling
50% Duty Cycle
\bc = Max.
Outputs Open
fl = 10MHz
!ill.% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling
Ic
(1)
MHz
mA
(6)
\bc = Max.
Outputs Open
fl = 2.5MHz
5..Q.% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling
"IN ~ ~c
VIN ~ VLC
(FCT)
-
3.0
6.5(5)
V IN = 3.4V
VIN .= GND
-
5.0
14.5(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
Alcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S10-175
IDT54/74 FCT841 A/B·46A/B HIGH·PERFORMANCE
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
, SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT841 B·46B
I DT54/74FCT841 A·46A
.TEST(1)
CONDITIONS
DESCRIPTION
PARAMETER
COM'L.
MIN.
tpLH
(IDT54174FCT841, 43. 45)
t pHL
CL
RL
Data (DI ) to Output (VI )
(LE = HIGH)
Data to LE Set·up Time
tH
Data to LE Hold Time
tpLH
(IDT54174FCT842, 44, 46)
t pHL .'
'"
tsu
Data to LE Set-up Time
tH
Data to LE Hold Time
tpLH
tpHL
tpLH .
tPHL
,
tpL~
Propagation Delay, Preset to VI
tsu
Preset Recovery (PRE" S) Time
tpHL
Propagation Delay, Clear to
tsu
Clear Recovery
tpwH
LE Pulse Width
HIGH
t pwL
Preset Pulse Width
LOW
tpWL
Clear Pulse Width
LOW
t pZH
tpZL
tpZH
t pZL
tpHZ
tpLZ
tpHZ
tpLZ
'11
L
Output Disable Time OE"
to '11
S
MIL.
MIN.
UNIT
MAX.
-
6.5
-
7.5
ns
-
13
-
15
-
13
-
15
ns
2.5
-
2.5
-
2.5
-
ns
3
-
2.5
-
2.5
2.5
2.5
-
ns
= 50pF
= 500n
-
10
-
12
-
8.0
-
9.0
ns
= 300pF(3)
= 500n
CL = 50pF
RL = 500n
C L = 50pF
RL = 500n
C L = 300pF(3)
RL = 500n
-
13
-
15
-
13
-
15
ns
2.5
-
2.5
-
2.5
-
2.5
-
ns
2.5
-
3
-
2.5
-
2.5
-
ns
-
12
-
13
-
8.0
-
10.5
ns
-
16
-
20
-
15.5
-
18
ns
-
12
-
14
8.0
-
10
ns
14
17
10
-
13
ns
10
11
ns
10
ns
ns
CL
RL
= 50pF
= soon
(CCAS) Time
Output Enable Time OE"
to VI
MAX.
10
CL
RL
Latch Enable (LE) to YI
MIN.
-
CL
RL
tpLH
tpHL
COM'L.
MAX.
9
= 300pF (3)
= 500n
CL = 50pF
RL = 500n
Data (DI ) to Output (VI )
(LE = HIGH)
MIN.
-
CL
RL
tpLfi
tpHL
tsu
= 50pF
= 500n
MAX.
MIL
CL
RL
= 50pF
= soon
CL
RL
= 50pF
= soon
= 300pF(3)
= soon
= 5pF (3)
= soon
= 50pF
= soon
CL
RL
CL
RL
CL
RL
-
13
-
14
-
-
14
-
17
-
10
-
4
-
5
4
-
4
5
-
7
-
4
-
4
4
-
5
-
4
-
4
-
-
11.5
-
13.0
-
8
-
8.5
ns
-
23
-
25
-
14
-
15
ns
-
9
-
10
-
6
-
6.5
ns
-
8
-
10
-
7.0
-
7.5
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.
S10-176
------
------------
IDT54/74FCT841 A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temp. Range
XXXX
Device Type
X
Package
Commercial
MIL-STD-883. Class B
P
D
........................................~ E
L
~
SO
841A
842A
843A
844A
845A
~""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''--l 846A
841B
842B
843B
844B
845B
846B
----........................................
.............................................
~
154
~
174
810-177
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
10-Bit Non-inverting Latch
10-Bit Inverting Latch
9-Bit Non-inverting Latch
9-Bit Inverting Latch
8-Bit Non-inverting Latch
8-Bit Inverting Latch
Fast 10-Bit Non-inverting Latch
Fast 10-Bit Inverting Latch
Fast 9-Bit Non-inverting Latch
Fast 9-Bit Inverting Latch
Fast 8-Bit Non-inverting Latch
Fast 8-Bit Inverting Latch
-55°C to
+ 125°C
~
lOT 54/74FCT861A/BlOT 54/74FCT864A/B*
(Replaces 39C861-64)
HIGH-PERFORMANCE
CMOS BUS
TRANSCEIVERS
Integrated DevIce'Jechnology.Inc.
FEATURES:
DESCRIPTION:
• Equivalent to AM D's Am29861-64 bipolar registers in pinouV
function, speeds and output drive over full temperature and
voltage supply extremes
• High-speed symmetrical bidirectional transceivers
- Non-inverting tpo = 5.5ns typo
- Inverting tpo = 6.0ns typo
• IoL = 48mA (commercial), and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5JJW typo static)
• lTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 Series (5JJA max.)
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 Series is built using advanced
CEMOS ™ , a dual metal CMOS technology.
The IDT54/74FCT860 Series bus transceivers provide highperformance bus interface buffering for wide data/address paths
or buses carrying parity. The IDT54/74FCT863/64 9-bit transceivers have NOR-ed output enables for maximum control flexibility.
All of the IDT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high impedance state.
FUNCTIONAL BLOCK DIAGRAM
IDT54/7 4FCT861 /IDT54/7 4FCT862 1O-BIT TRANSCEIVERS
PRODUCT SELECTOR GUIDE
DEVICE
10-BIT
I Non-inverting
I Inverting
9-BIT
IDT54174FCT861
IDT54174 FCT863
IDT54174 FCT862
IDT54174 FCT864
CEMOS is a trademark of Integrated Device Technology, Inc.
*Advance information only for IDT54174FCT862.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19891nlegrated Device Technology. Inc.
oSC-402211
S10-178
- - - - _.. -----_._._.- --------
JANUARY 1989
IDT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUSTRANSC8VERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDT54/7 4FCT863/IDT54/7 4FCT864 9-BIT TRANSCEIVERS
OER 1
OER 2
R8
PIN CONFIGURATIONS
IDT54/74FCT861/IDT54/74FCT862 10-BIT TRANSCEIVERS
LOGIC SYMBOLS
IDT54/74FCT861
INDEX
ULJU;;ULJU
432
LJ 282726
R2
:J
5
25
R3
:J
6
24 [
R4
:J 7
NC
:18
R5
:J 9
23
J28-1
l28-1
R6 :110
R7 :111
£:
£:
T2
T3
T4
22 [
NC
21 [:
T5
20 [
T6
19 [:
T7
T
12 13 14 15 16 17 18
nnnnnnn
a:"'(J)OO~t2'~
a: z z
(!j
DIP/CERPACK/SOIC
TOP VIEW
LCC/PLCC
TOP VIEW
IDT54/74FCT863
I DT54/7 4FCT863/IDT54/7 4FCT864 9-BIT TRANSCEIVERS
OER 1
Vee
Ro
To
Rl
T1
R2
T2
R3
T3
R4
T4
R5
T5
R6
R7
T6
R8
OER 2
GND
INDEX
ULJU;;UUU
432LJ282726
:J
:1
5
25 [
T2
6
24 [
T3
:J
:J
23 [
T4
8
22 [
NC
:J
9
7
T7
:J 10
T8
:J
0ET2
C5"E1' 1
DIP/CERPACK/SOIC
TOP VIEW
J28-1
l28-1
11
21 [
T5
20 [
T6
19 [
T7
12 13 14 15 16 17 18
nnnnnnn
a:~§~~~~
LCC/PLCC
TOP VIEW
S10-179
T
IDT54174FCT861A/B·64A/B HIGH·PERFORMANCE
CMOS BUS TRANSCEIVERS .
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
DESCRIPTION
I/O
IDT54/74FCT861/62
om
I
When LOW in conjunction with~, HIGH activates
the RECEIVE mode.
orr
I
When LOW in conjunction with
the TRANSMIT mode.
RI
I/O
1()"bit RECEIVE inpuVoutput.
1j
I/O
10·bit TRANSMIT inpuVoutput.
om, HIGH activates
IDT54/74FCT863/64
oml
I
When LOW in conjunction with C5ETj
activates the RECEIVE mode.
orrl
I
When LOW in conjunction with oml ' HIGH
activates the TRANSMIT mode.
RI
I/O
9·bit RECEIVE inpuVoutput.
1j
I/O
9-bit TRANSMIT inpuVoutput.
, HIGH
FUNCTION TABLES(1)
IDT54/74FCT861/63 (Non-inverting)
INPUTS
OET
~
L
L
OUTPUTS
om
Transmitting
L
Transmitting
L
N/A
Receiving
H
N/A
Z
Z
TI
RI
H
L
N/A
N/A
L
H
H
N/A
N/A
H
H
L
N/A
L
L
H
L
N/A
H
H
H
X
X
OUTPUTS
INPUTS
FUNCTION
OET
RI
NOTE:
1. H = HIGH, L
Applicable
FUNCTION TABLES (1)
IDT54/74FCT862/64 (Inverting)
TI
FUNCTION
RI
TI
RI
TI
H
L
N/A
N/A
H
Transmitting
H
H
N/A
N/A
L
Transmitting
H
L
N/A
L
H
N/A
Receiving
H
L
N/A
H
L
N/A
HighZ
H
H
X
X
Z
Z
= LOW, Z = High Impedance, X = Don't Care, N/A = Not
NOTE:
1. H = HIGH, L = LOW, Z
Applicable
S10-180
Receiving
Receiving
HighZ
= High Impedance, X = Don't Care, N/A =
Not
I DT54/74FCT861 A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM (2)
RATING
Terminal Voltage
with Respect to
GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
VTERM (3) with Respect to
GND
-0.5 to Vcc
-0.5 to Vee
V
TA
Operating
Temperature
Oto +70
-55 to + 125
°C
TalAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CIN
Input Capacitance
CliO
I/O Capacitance
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.
DC Output Current
100
100
mA
louT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposuretoabsolute maximum rating conditions for extended periods may affect reliability.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
TEST CONDITIONS (1)
PARAMETER
'-"H
Guaranteed Logic High Level
2.0
'-"L
Input LOW Level
Guaranteed Logic Low Level
-
IIH
Input HIGH Current
(Except I/O pins)
Vcc = Max.,
IlL
IIH
~
-
'-"
= 2.7V
-
-
= 0.5V
-
-
'-"
= Vcc
\j = 2.7V
Vcc = Max.,
\j = 0.5V
UNIT
-
V
0.8
V
5
-
~ = GND
Input HIGH Current
(I/O pins only)
:
MAX.
-
= Vcc
'-"
Input LOW Current
(Except I/O pins)
TYp,(2)
MIN.
Input HIGH Level
5(4)
"
-5(4)
-
-
-5
-
-
15·
-
-
15(4)
-
-15(4)
-
jJA
jJA
IlL
Input LOW Current
(I/O pins only)
-
-
-15
'-"K
Clamp Diode Voltage
Vcc = Min., IN = -18mA
-
-0.7
-1.2
V
los
Short Circuit Current
Vcc = Max!3), Vo = GND
-75
-120
-
mA
-
~
= GND
VHC
Vcc
= -300jJA
VHC
Vcc
-
ioH = -15mA MIL.
2.4
4.3
bH = -24mA COM'L.
2.4
4.3
-
GND
VLC
IoL = 300jJA
-
GND
VIr.
10L = 32mA MIL.
-
0.3
0.5
10L = 48mA COM'L.
-
0.3
0.5
Vcc = 3V, ~N = VLC orVHC.I OH = -32jJA
VOH
Output HIGH Voltage
IoH
Vcc = Min.
~N = ~H or~L
Vcc = 3V, \IN = VLC or VHC • 10L = 300jJA
VOL
Output LOW Voltage
Vcc = Min.
\IN = \lH or\lL
VH
200
Input Hysteresis on TI and R I Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but. not tested.
510-181
-
V
V
mV
IDT54174FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS(1)
MIN.
TYP.(2)
MAX.
UNIT
Icc
Quiescent Power Supply Current
Vec = Max.
VIN ~ VHC ; "IN :5 Xc
fl = 0
-
0.001
1.5
mA
~Icc
Quiescent Power Supply Current
TTL Inputs HIGH
Vec = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current (4)
Vcc= Max.
Outputs Open
OE = GND
TIR = GND or \bc
One Input Toggling
50% Duty Cycle
"IN ~ VHC
"IN :5 VLC
-
0.15
0.25
mAl
'''IN 2:' VHC
"IN :5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4Vor
VIN = GND
-
1.8
5.0
ICCD
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
Ic
Total Power Supply Current(6)
MHz
mA
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle.
OE = GND
Eight Bits Toggling
"IN ~ VHC
"IN :5 VLC
(FCT)
-
3.0
6.5(5)
VIN = 3.4V
VIN = GND
-
5.0
14.5(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are atVcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + IINPLrrS + IDYNAMIC
.
.
Ic = Icc + ~Icc DHNT + ICCD (fcpI2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number. of Inputs at fl
All currents are' in milliamps and all frequencies are in megahertz.
S10-182
IDT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT861 A-64A
PARAMETER
tpLH
tpHL
tpLH
tpHL
tpLH
t pHL
tpLH
t pHL
tpZH
t pZL
tpZH
tpZL
t pHZ
tpLZ
tpHZ
t pLZ
DESCRIPTION
TEST(1)
CONDITIONS
= 50pF
= 5000
= 300pF(3)
= 5000
CL = 50pF
RL = 5000
CL = 300pF (3)
RL = 5000
CL = 50pF
RL = 5000
CL = 300pF (3)
RL = 5000
CL = 5pF(3)
RL = 5000
CL = 50pF
RL = 5000
MIL
MIN!2) MAX. MIN.(2) MAX.
I DT54174FCT861 B-64B
COM'L
COM'L
MIL
MAX.
MIN.
MAX.
CL
Propagation Delay from
RL
RI toTI orlj to RI
IDT54174FCT861 /IDT54174FCT863 C
L
(Non-inverting)
RL
-
8
-
9
-
6.0
-
6.5
ns
-
15
-
17
-
13
-
14
ns
Propagation Delay from
RI toTI orlj to RI
IDT54174 FCT862/1DT5417 4 FCT864
(Inverting)
-
7.5
-
9.0
-
5.5
-
6.5
ns
-
14
-
16
-
13
-
14
ns
-
12
-
13
-
8.0
-
9.0
ns
-
20
-
22
-
15
-
16
ns
-
9
-
10
-
6
-
7
ns
-
10
-
10
-
7.0
-
8.0
ns
Output Enable Time OET to
lj or
to RI
om
Output Disable Time OET to
TI or OER to R I
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.
ORDERING INFORMATION
IDTXXFCT
Temp. Range
UNIT
MIN.
XXXX
Device Type
Commercial
MIL-STD-883, Class B
'------------i
'----------------1
S10-183
L
SO
Plastic DIP
CERDIP
CERPACK
Plastic Leadless Chip Carrier
Leadless Chip Carrier
Small Outline IC
861
862
863
864
10-Bit Non-Inverting Transceiver
10-Bit Inverting Transceiver
9-Bit Non-Inverting Transceiver
9-Bit Inverting Transceiver
P
D
E
J
t;)
Integrated Device"Rrlmolosy,Jnc.
HIGH-SPEED CMOS
OCTAL D FLIP-FLOP WITH
CLOCK ENABLE
lOT 54AHCT377
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical propagation delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5jJW typo static)
• 80th CMOS and lTL output compatible
• Substantially lower input current levels than ALS (5jJA max.)
• bctal D. flip-flop with clock enable
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8
The IDT54AHCT377 is an octal D flip-flop built using advanced
CEMOS TM, a dual metal CMOS technology. The IDT54AHCT377
has eight edge-triggered, D-type flip-flops with individual D inputs
and 0 outputs. The common buffered Clock (CPllnput loads all
flip-flops simultaneously when the Clock Enable (CE) is LOW. The
register is fully edge-triggered. The state of each D input, one setup time before the LOW-te-HIGH clock transition, is transferred to
the corresponding flip-flop's 0 output. The CE input must be stable
only one set-up time prior to the LOW-to-HIGH clock transition for
predictable operation.
PIN CONFIGURATIONS
a:
Q'c5'rtiJlo
INDEX
00
Do
01
01
•
I
I
I
L....I
L...J
. 3
2
O2
03
03
I'
I
I
L...J
I
I
L...J
U 20 19
1
0 1 ]4
0 1 ]s
O2
I
I
18 [:
17 [:
Oz
]6
O2
03
]7
lS[
]8
14[
16 [:
L20-2
07
06
06
05
Os
~~~~~
GND
o~5oo
(!:l
DIP/CERPACK
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
O2
03
04
Os
06
07
CEMOS is a trademark of Integrated Device Technology. Inc.
JANUARY 1989
MILITARY TEMPERATURE RANGE
© 1989 Integrated DevIce Technology, Inc.
DSC-4051/-1
510-184
IDT54AHCT377 HIGH-SPEED CMOS OCTAL
D FLIP-FLOP WITH CLOCK ENABLE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage with Respect
toGND
MILITARY TEMPERATURE RANGE
CAPACITANCE
(1)
(TA= +25°C f = 10MHz)
VALUE
UNIT
-0.5 to +7.0
V
C IN
Input Capacitance
COUT
Output Capacitance
TA
Operating Temperature
-55 to +125
°C
TalAs
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
PT
Power Dissipation
0.5
W
lOUT
DC Output Current
120
mA
'. -65 to +150
SYMBOL
PARAMETER(1)
CONDITIONS TYP.
MAX. UNIT
VIN = OV
6
10
pF
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above tl"!ose indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee = 5.0V ± 10%
VLC = 0.2V
VHe = Vee - 0.2V
SYMBOL
'-"H
'-"L
IIH
TEST CONDITIONS (1)
PARAMETER
TYP,(2)
MAX.
UNIT
V
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
Input HIGH Current
Vec = Max·.\'IN = Vcc
-
-
5.0
JlA
-
IlL
Input LOW Current
Vec = Max .• VIN = GND
Isc
Short Circuit Current
Vee = Max. (3)
VOH
Output HIGH Voltage
Vee = Min.
\'IN = \'IH or\'lL
-
= VLC or VHe • 10H = -32JlA
Vee = 3V. \'IN
I
I
10H = -150uA
10H = -1.0mA
Vee = 3V. \'IN = VLC or \l;c. 10L = 300 JlA
VOL
MIN.
Output LOW Voltage
Vee = Min.
\'IN = \'IH or\'lL
I
I
10L = 300)JA
10L = 14mA
-5.0
JlA
-60
-100 '
-
rrA
VHe
VHC
2.4
Vee
Vcc
4.3
-
-
-
GND
VLC
GND
VLC
0.4
-
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should riot exceed one second.
510-185
rrA
V
V
IDT54AHCT377 HIGH-SPEED CMOS OCTAL
D FLIP-FLOP WITH CLOCK ENABLE
MILITARY TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; ~C = Vee - 0.2V
SYMBOL
TEST CONDITIONS (1)
PARAMETER
MIN.
TYP.(2)
MAX.
UNIT
Vee = Max.
ICCQ
Quiescent Power Supply Current
VIN ~VHC; "'N ~ "tc
fcp = fl = 0
-
0.001
1.5
mA
ICCT
Quiescent Power Supply Current
TIL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
-
0.5
2.0
mA
Dynamic Power Supply Current(5)
Vee= Max.
Outputs Open
Ce = GND
One Bit Toggling
50% Duty Cycle
"'N ~ ~c
"'N ~ VLC
-
0.15
0.25
mAl
MHz
"'N ~ VHC
"'N ~ VLC
(AHCT)
-
0.15
1.8
VIN = 3.4Vor
VIN = GND'
-
0.65
3.8
ICCD
Icc
Vee = Max.
Outputs Open
fcp = 10MHz
§Q.% Duty Cycle
CE = GND
One Bit Toggling
at f I = 500kHz
50% Duty Cycle
mA
Total Power Supply Current (4)
Vcc = Max.
Outputs Open
fcp = 1.0MHz
§Q.% Duty Cycle
CE = GND
Eight Bits Toggling
atf l , = 250kHz
50% Duty Cycle
VIN ~ VHC
"'N ~ \tc
(AHCT)
(6)
VIN = 3.4Vor
VIN = GND
(6)
-
0.63
2.2
-
2.88
11.2
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); ,all other inputs at Vee or GND.
4. Icc = IOUIESCENT + IINPUTS + IDYNAMIC
Icc = leeQ + leeT DH NT + leeD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
S10-186
IDT54AHCT377 HIGH-SPEED CMOS OCTAL
D FLIP-FLOP WITH CLOCK ENABLE
MILITARY TEMPERATURE RANGE
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION
PIN NAMES
INPUTS
OPERATING MODE
CP
CE
OUTPUTS
0
0
Do-D7
Data Inputs
CE
Clock Enable (Active LOW)
Load "1"
t
I
h
0 0 -0 7
Data Outputs
Load "0"
j
I
I
L
CP
Clock Pulse Input
j
h
H
X
X
No Change
No Change
Hold (Do Nothing)
X
H
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
X = Immaterial
j
= LOW-to-HIGH Clock Transition
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TYP.
MIN.(2)
MAX.
Propagation Delay
CP to ON
10.0
2.0
20.0
ns
ts
Set-up Time
HIGH or LOW
DN to CP
5.0
2.0
-
ns
tH
Hold Time
HIGH or LOW
DN to CP
2.0
1.5
-
ns
ts
Set-upTime
HIGH or LOW
CE to CP
3.0
4.0
-
ns
tH
Hold Time
HIGH or LOW
CE to CP
2.0
1.5
-
ns
tw
Clock Pulse Width, LOW
7.0
7.0
-
ns
SYMBOL
tpLH
t pHL
PARAMETER
CONDITION(1)
CL = 50pF
RL = 5000
NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
ORDERING INFORMATION
IDTXXAHCT
Temp. Range
> - - - - - - - - ; . - - - < J OUT+
,..------7J 'v--''-----+--__------'----O OUT-
REFERENCE
AMPLIFIER
REFERENCE
r-------,
INTERNAL
FSADJ +o---~--._----------r_r_--~
--'1
IREF
To Internal
Voltage
Reference
1.25V Nom.
(Ref VCCA )
1
1
1
I
I
I
1
IL _ _ _ _ _ _ _ .J
I
1
I
I
I
I
I
'---t---------------------------------+-------------- VEEA
L ___
.J
Figure 4. Equivalent Output Circuit
r----------------------------------------------,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L
VEEA
RED
DAC
BLUE
DAC
FS ADJ+
FS ADJ+
FS ADJ+
FS ADJ-
FS ADJ-
\,...__---1 FS ADJ-
___________ _
FSADJ
Figure 5. FS ADJ Internal Circuitry
S11-5
GREEN
DAC
III
COMMERCIAL TEMPERATURE RANGE
IDT75MB38 CMOS TRIPLE 8-BIT VIDEO DAC MODULE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
SYMBOL
UNIT
POWER SUPPLY
VEED
Measured to VCCD
-7.0 to +0.05
V
VEEA
Measured to VCCD
-7.0 to + 0.05
V
AGND
Measured to VCCD
-0.5 to + 0.5
V
INPUT VOLTAGES
CONY, Data &
Controls
FSADj,
Applied Voltage(2)
Measured to VCCD
VEED to 0.5
V
Measured to VCCA
VEEA to 0.5
V
MIN.
TYP.
MAX.
UNIT
VEED
Digital Supply Voltage
(REF VCCD)
-4.9
-5.2
-5.5
V
VEEA
Analog Supply Voltage
(REF VcCA)
-4.9
-5.2
-5.5
V
VCCA
Analog Ground
Voltage (REF VCCD)
-0.1
0
+ 0.1
V
VEEAVEED
Supply Voltage
Differential
-0.1
0
+ 0.1
V
V1L
Input Voltage,
Logic LOW
-1.49
-
-
V
V1H
Input Voltage,
Logic HIGH
-
-
-1.045
V
RREF
Reference Current,
Video Std.
1100
1200
1300
n
TA
Ambient Temperature
0
-
70
°C
OUTPUT
Analog Output,
Applied Voltage(2)
Measured to VCCA
-2.0 to +0.4
V
50
mA
Analog Output,
Applied Current(3.4)
Short Circuit Duration
NOTE:
1. Minimum and maximum values allowed by + 5% variation given in
RS-343A and RS-170 after initial gain correction of device:
Unlimited
TEMPERATURE
Operating, Ambient
Commercial
Storage
Commercial
o to
+70
-55 to +125
PARAMETER
°C
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation ofthe device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect reliability. Absolute Maximum Ratings are limiting values applied individually while all other
parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the
device.
511-6.
---_._--_._-_ .._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDT75MB38 CMOS TRIPLE 8-BIT VIDEO DAC MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETERS
IEEA+
IEED
Supply Current
CI
Input Capacitance.
Data & Controls
Vocp
Compliance Voltage.
+ Output
VOCN
TEST CONDITIONS
MIN.
MAX.
UNIT
-
-
mA
-
15
pF
-1.2
+0.1
V
Compliance Voltage.
-Output
-1.2
+0.1
V
Ro
Equivalent Out R
20
-
Co
Equivalent Out C
-
20
pF
lop
Max. I. + Output
VEEA = Typ .. SYNC
OVERLAY = 1
30
-
mA
ION
Max. I. -Output(2)
VEEA
=
Typ .. SYNC
30
-
mA
hL
Input Current. Logic
LOW. Data & Controls
VEED
=
Max.: VI
=
-1.40V
-
600
J.lA
hH
Input Current. Logic
HIGH. Data & Controls
VEED
=
Max.: VI
=
-1.00V
-
600
J.lA
Ilc
Input Current. CONV
VEED
=
Max.: -2.5 < VI < -0.5
-
150
J.lA
VEEA
= VEED =
Max .•(1)Static
=
BLANK
=
1
=
0
kO
NOTES:
1. Worst case for all Data and Control States. No termination on I OUT+Or lour.
2. Green output only.
AC ELECTRICAL CHARACTERISTICS
Specifications over the Recommended Operating Conditions unless otherwise stated.
SYMBOL
PARAMETER
Fs
Max. Conversion Rate
tpWL
CONV LOW Time
tpwH
CONV HIGH Time
ts
Set-up Time. Data & Control
tH
Hold Time. Data & Control
tosc
CONV to OUT Delay
tSI
Current Setting Time
tRi
Current Rise Time
TEST CONDITIONS
I DT7M B5038X70
MIN.
MAX.
IDT7M B5038X1 00
MIN.
MAX.
IDT7MBS038X125
MIN.
MAX.
UNIT
Min.
-
70
-
100
-
125
Min.
6
-
5
4
-
ns
Min.
6
-
5
4
-
ns
Min.
8
-
6
-
5
-
ns
Min.
5
-
1
-
0
-
ns
Min.
-
14
-
10
-
8
ns
0.2%
0.8%
3.2%
-
-
-
-
10% to 90% of Full Scale
-
3.0
=
VEEA . VEED • =
V EEA . VEED . =
V EEA . VEED . =
V EEA . VEEO . =
V EEA . VEED . =
V EEA . VEED . =
VEEA . VEED •
Min.
S11-7
.-
-
MHz
-
-
-
-
ns
ns
ns
-
2.1
-
1.7
ns
-
-
-
iii
COMMERCIAL TEMPERATURE RANGE
IDT75MB38 CMOS TRIPLE 8-BIT VIDEO DAC MODULE
SYSTEM PERFORMANCE CHARACTERISTICS
Specifications over the Recommended Operating Conditions unless otherwise stated.
SYMBOL
PARAMETERS
TEST CONDITIONS
ELI
Linearity Error Integral
VEEA , VEED , IREF = Typ.
ELD
Linearity Error Differential
VEEA , VEED , IREF = Typ.
VEEA , VEED = Max. SYNC = BLANK = 0
OVERLAY = 1
IOF
Output Offset I
EG
Abs. Gain Error
TCG
Gain Error Tempco
DP
Differential Phase
Fs = 4 x NTSC
DG
Differential Gain
Fs = 4 x NTSC
PSRR
Power Supp. Rej. Ratio
VEEA , VEED , IREF = Typ.(1)
VEEA ' VEED , IREF = Typ.(2)
VEEA, VEED, IREF = Typ.
VEEA , VEED , IREF = Typ.
MIN.
MAX.
UNIT
-
0.2
%FS
0.2
%FS
-
±1.0
-
±5
%FS
-
%FS/oC
1.0
Deg.
PSS
Power Supp. Sensitivity
GC
Peak Glitch Charge (3. 4)
GI
Peak Glitch Current
GE
Peak Glitch Energy(4)
FT
Clock Feedthrough
Data Constant (5)
-
FT
Data Feedthrough
Clock Constant(5)
-
MDD
DAC to DAC Matching
CT
Crosstalk
VEEA , VEED , IREF = Typ.
VEEA • VEED • IREF = Typ.(5)
Source = 3.0 MHz. Full Grey Scale Sine Wave
~A
2.0
%
45
55
dB
dB
120
~VN
800
fc
1.2
mA
30
pV-Sec
-50
dB
-50
dB
5
%
50
dB
NOTES:
1. 20kHz. ±0.3V ripple superimposed on VEEA . VEED : dB relative to full gray scale.
2. 60Hz. ±0.3V ripple superimposed on VEEA . VEED: dB reltive to full gray scale.
3. fCoulombs = microamps x nanoseconds.
4. 37.50 load. Because glitches tend to be symmetric, average glitch area approaches zero.
5. dB relative to full gray scale, 250MHz bandwidth limit.
- - - - - - - - - - - - - - _ . __.. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --
S11-8
--
---- --- - - - -
1DT75MB38 CMOS TRIPLE 8-BIT VIDEO DAC MODULE
COMMERCIAL TEMPERATURE RANGE
VCCD
REDINP~ {
DATA
GREEN INP~ {
DATA
BLUE INP~ {
{
SYNC
BLANK
OVERLAY
CONTROL
INPUT DATA
FSADJ
gRED
lOUT - R
VIDEO
OUT
750
I OUT+ R
DOG
DlG
D2G
D3G
D4G
D5G
D6G
D7G (MSB)
DaB
D1B
D2B
D3B
D4B
D5B
D6B
D7B (MSB)
DATA
VCCA
DaR
D1R
D2R
D3R
D4R
D5R
D6R
D7R (MSB)
37.50
gGREEN
lOUT - G
VIDEO
OUT
IDT75MB38
750
I OUT+ G
gBLUE
lOUT - B
VIDEO
OUT
750
IOUT+ B
CLOCK
CONV
37.50
VEED
&
iii
VEEA
~
-5.2V
Figure 6. Typical Interface Circuit
S11-9
._------_
...
- - -..
IDT75MB38 CMOS TRIPLE 8-BIT VIDEO DAC MODULE
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
xxxx
X
X
Device Type
Power
Speed
X
Package
Process!
Temperature
Range
------II
L.!
Commercial (O°C to
BLANK
---1 P
Plastic DIP (Module)
L..-_ _ _ _ _ _ _ _
L..-_ _ _ _ _ _ _ _ _ _ _- - j
70
100
+ 70°C)
}
Speed in Megahertz
125
511-10
S
Standard Power
75MB38
Triple 8-Bit video DAC Module
- -...
_---------------------------------
.t;)
lOT 75C458
CMOS TRIPLE 8-BIT
PALETTEDAC™
Intesrated DeviceTechnology. Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
165/135/125/110/80MHz operating speed
Fixed pipeline delay: 9 clock cycles
50ns read access time
Integral and differential linearity < 1/2lSB
•
•
•
•
•
•
Triple 8-bit DACs
256 x 24 Dual-Ported Color Palette RAM
4 x 24 Dual-Ported Overlay Palette RAM
Multiplexed TTL pixel and overlay inputs
RS-343A compatible RGB outputs
CEMOS ™ monolithic construction
The IDT75C458 is a triple 8-bit video DAC with on-chip, dualported color palette memory. This chip is specifically designed for
the display of high resolution color graphics. The architecture
eliminates the ECl pixel interface by providing multiple TTl-compatible pixel ports and by multiplexing the pixel data on-Chip.
The IDT75C458 supports up to 259 simultaneous colors from a
palette of 16.8 million. Other features included on-chip are programmable blink rates, bit plane masking and blinking as well as a
color overlay capability. The IDT75C458 generates RS-343A compatible red, green, and blue video outputs which are capable of directly driving a doubly terminated 750 coaxial cable.
The IDT75C458 military DACs are manufactured in compliance
with the latest revision of Mll-STD-883, Class B, making them ideally suited to military temperature applications demanding the
highest level of performance and reliability.
• Single 5V power supply
• 84-pin PGA and PlCC packages
• Typical power dissipation: 1000mW
• Pin- and function-compatible with Brooktree BT458
• Military product is compliant to Mll-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
VREF
FSADJ
r - - - - - - - - - l ' - - - COMP
ill --+-------,
R
E
LATCH
A
D
>-+-- lOB
iii
OLa-Oll {A-E}
SYNC --+---~
BLINK REG
READ REG
TEST REG
ADDR REG
COMM REG
CO
C1
R/W
cr
CEMOS and PaletteDAC are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-5002/1
1989 Integrated Device Tehnology, Inc.
S11-11
.
--------_.-----------_._--_._._-------
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A
12
B
COMF AGND
C
D
E
F
G
H
K
J
L
M
VAA
P 7{D} P7{B} Pa{E} Pa{C} Pa{B} Ps{E} Ps{C
VAA
P7{E} P7{C} P7{A} PaiD} Pa{A} Ps{D} Ps{A} P4{C} P4{A}
11
lOB
AGND
10
lOG
FSADJ VREF
9
VAA
lOR
8
C1
R/W
7
VAA
CO
P4 {D
Ps{B} P4 {E}
P4 {B} S?NC
~
ill
CO<
ClK
VAA
VAA
G84-2
6
AGND
AmiD
P3{E} AGND
5
cr
D7
P3 {C} P3{D}
4
Da
Ds
P3{A} P3 {B}
f1 ALIGNMENT MARK
3
D4
D2
2
D3
Dl
Do
P2 {A} P2 {C} P2 {E}
Pl l{E
Po{B} Po{D} P l {A} Pl {D} P l {E} P2 {D}
Pl l{A Pl l{C Pll {D
Po {A} Po{C} Po{E Pl{B} P l {C} P2 {B]
Plo{B Plo{E Pll {B
Plo{A Olo{C Plo{D
PGA
TOP VIEW
§:2:~€3:§:2:~€ ~
P'i ~
1~1~3:§:2:~
~~~~~~~~~~JJddB~~~~~~
7~ 7:'; 7~ k/~s'glars~sirsrsrsrsrs:.rs~s~srs'isi s?:
P2 {A}
Pl {E}
Pl {D}
Pl {C}
Pl {B}
Pl {A}
Po {E}
- - - - - - - - - - - - - - - - - - - - - Po {D}
Po{C}
Po{B}
Po {A}
all {E}
all {D}
Oldc}
all {B}
all {A}
Olo{E}
Olo{D}
Olo{C}
Olo {B}
:J 7S
:J 7S
srS3 I:
S2 I:
] 77
Sl I:
:1 78
so I:
:1 79
49 I:
:J 80
48 I:
:1 81
47 I:
]-82--------------- - ----~----------4SI:
:J 83
4S I:
:J 84
44 I:
:::J 1
J84-1
43 I:
:1 2
42 I:
] 3
41 I:
:J 4
40 I:
:J s
39 I:
:1 s
38 I:
:17
37 I:
] 8
36 I:
:J 9
- 35 I:
:J 10
34 I:
33
ala {A} :I 1~2 13 14 151617181920 21 222324252627282930 3132 I:
nnnnnnnnnnnnnnnnnnnnn
S11-12
P4 {E}
Ps{A}
Ps{B}
Ps {C}
Ps {D}
Ps{E}
Ps {A}
-Ps {B} -- ------------------------------------Ps{C}
Ps{D}
Ps {E}
P7 {A}
P 7{B}
P 7{C}
P 7{D}
P 7{E}
VAA
AGND
VAA
AGND
VREF
MILITARY ANDCOMMERCIAL TEMPERATURE RANGES
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
GENERAL INFORMATION:
ADDRESS REGISTER
DATA
The IDT75C458 triple 8-bit PaietteDAC is a highly integrated
building block which interfaces a relatively low bandwidth frame
buffer memory to an analog RS-343A, high bandwidth output. To
decrease the frame buffer memory requirements, the IDT75C458
has a color lookup table (dual-port RAM) included on-chip.The basic functional blocks are the microprocessor bus interface, the
frame buffer memory interface and multiplexer, a dual-port RAM
with one R/W port and one high-speed R/O port and three 8-bit
video speed DACs.
X
$OO-$FF
$00
$01
$02
$03
$04
$05
$06
$07
MICROPROCESSOR BUS INTERFACE
The IDT75C458 supports a standard microprocessor bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port color palette RAM
and overlay registers allow color updating without contention with
the display refresh process.
The bus interface consists of eight bidirectional data pins,
Do - 0 7 , with two control inputs, CO and C1, a read/write direction
input, R/W, and a clock input, CE . All data and control information
are latched on the falling edge of CE, as shown in Figure 3. All
accesses to the chip are controlled by the data in the address
register combined with the control inputs CO, C1 and R/W,
depicted in the Truth Table (Table 1).
An access to a control register requires writing a 4 through 7 into
the address register (CO = C1 = 0) and then writing or reading data
to the selected register (CO=O, C1 = 1). When accessing the control registers, the address register is not changed, facilitating readmodify-write operations. If an invalid address is loaded into the
address register, data written is ignored or invalid data is read out.
It is also possible to access the color palette information. The
palette is organized as 256 addresses with 8 bits of red, blue and
green information. Additionally, there are four extra addresses
assigned to overlay information, yielding a total memory size of
260 x 24.
Access to the palette entries is, again, through the address register. The desired palette address is loaded into the address register, CO and C1 are modified to point to the color palette or overlay
and the information is read or written. In this case, however an
internal counter is used to access the red, green or blue color i~for
mati on. The first color palette or overlay access reads or writes red.
The next access is for green, while the third access is for blue. After
the third access, the address register is incremented, allowing the
reading or writing of the red information of the next palette address.
When writing, red and green information is temporarily stored in
registers and, during the blue cycle, all 24 bits are written.
The internal counter is reset by an access to the address or any
of the control registers. After setting the address register, it is possible to read or write the entire palette without accessing the address
register again. Some care is needed; only continuous reads or
writes are allowed and it is not possible to switch between the color
palette and overlay.
The color palette RAM and overlay registers are dual-ported
which allows simultaneous access from the MPU port (Do - 0 7 )
and the pixel port (Po - P7 {A-E}). If the pixel port is reading the
same palette entry as the MPU is writing, it is possible that the DAC
output may be invalid. It is recommended that the palette and overlay entries be updated during the blanking time.
C1
CO
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
ACCESS
Address Register
Color Palette
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3
Read Mask Register
Blink Mask Register
Command Register
Test Register
NOTE:
Control input CO = 1 enables the internal counter which accesses the red
green and blue colors individually and increments the address counte~
after the blue access. CO = 0 disables auto-increment of the address
register allowing read-modify-write operations.
Table 1. Truth Table for MPU Operations
FRAME BUFFER INTERFACE
The frame buffer interface consists of five 8-bit input ports which
correspond to five consecutive pixels. In addition, there are two
extra bits per port which may be used for overlay information. To
reduce the bandwidth requirements for the pixel data, the
IDT75C458 latches 4 or 5 pixels (the multiplex factor is
programmable to 4 or 5 by bit 7 of the command register) on each
rising edge of lD. The color and overlay information is internally
multiplexed at the pixel clock frequency, ClK, and sequentially
output. This arrangement allows pixel data to be transferred at a
rate 4 or 5 times slower than the pixel clock. Typically, lD is the
pixel clock divided by 4 or 5 and is used to clock data out of the
frame buffer memory.
As shown in Figure 2, sync, blank, color and overlay information
are latched on the rising edge of lD . Up to 40 bits of color information are input through Po - P7 {A-E} and up to 10 bits of overlay
information are input through ala - all {A-E}. Both sync and
blank have separate inputs, SYNC and BLANK, respectively. The
I DT75C458 outputs color information on each clock cycle. Four or
five pixels are output sequentially, beginning with the {A} information, then the {B} information, until the cycle is completed with the
{D} or {E} information. In this configuration, sync and blank times
are limited to multiples of four or five clock cycles.
The multiplexing factor, 4:1 or 5:1, is programmable from the
~ommand register, bit 7.ln the 4:1 mode, the {E} color and overlay
Inputs are not used and the lD clock should be CLOCK divided by
4. The {E} color and overlay inputs must be connected to a valid
logic level.
The overlay inputs (Olo - all) have the same timing as the pixel
inputs (Po - P7 ). It is possible to use additional bit planes or external
logic to control the overlay selection for cursor generation.
[(J
INTERNAL MULTIPLEXING
lD is typically ClK divided by four or five and it latches color
and overlay information on every rising edge, independent of ClK.
A digital Pll allows lD to be phase inde~ndent of ClK. The only
restriction is that only one rising edge of lD is allowed to occur per
four (4:1 multiplexing) or five (5:1 multiplexing) ClK cycles.
511-13
.....
_-----_..
_ .._ . _ - - - - - - - - - -
IDT75C458 CMOS TRIPLE 8-BIT PAlETTEDAC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Color Palette
Video Generation, DACs
On the rising edge of each ClK cycle, eight bits of color information (Po - P7) and two bits of overlay information (Olo - Ol, ) for
each pixel are processed by the read mask, blink mask and command registers. This information provides the address to the dualport color palette RAM. Note that Po is the lSB when addressing
the color palette RAM. The value stored at a selected address
determines the displayed color. In this way, 8 bits of information
can select from a palette of over 16 million with 256 simultaneous
displayed colors (plus 3 overlay colors). Through the use of the
control register, individual bit planes may be enabled or disabled
for display and/or blinked at one of four blink rates and duty cycles.
The blink timing is based on vertical retrace intervals which are
defined by at least 256 lD cycles since the last falling edge of
BLANK. The color changes during this normally blanked time.
The processed pixel data is then used to select which color palette entry or overlay register is used to provide color information.
Table' 2 illustrates the truth table used for color selection.
On every ClK cycle, the selected 24 bits of color information
(8 bits each of red, green and blue) from the Color Palette RAM are
presented to the three 8-bit D/A converters. The IDT75C458 uses a
5 x 3 segmented approach where the five MSBs of the input data
are decoded into a parallel "Thermometer" code which produces
thirty two "course" output levels. The remaining three lSBs of input
data drive three binary weighted current switches with a total contribution of one-thirty second of full scale. The MSB and lSB currents are summed at the output to produce 256 levels.
The SYNC and BLANK inputs are pipelined to maintained synchronization with the pixel data. Both inputs drive appropriately
weighted current switches which are summed at the output of the
DACs to produce the specific output levels required by RS-343, as
shown in Figure 3. Note that the sync information is only available
at the lOG (green) output and that the input data to the DAC sums
with the sync current. Table 3 details the output levels associated
with SYNC, BLANK and data.
Monitor Interface
CRG
Ol,
Olo
P7 - Po
1
1
0
0
0
0
$00
$01
1
0
x
x
x
0
0
0
1
1
0
0
1
0
1
$FF
$xx
$xx
$xx
$xx
The analog outputs of the IDT75C458 are high-impedance cur~
rent sources which are capable of directly driving a doubly terminated 750 coaxial cable to standard video levels. A typical output
circuit is shown in Figure 4.
PALETTE ENTRY
Color palette entry $00
Color palette entry $01
Color palette entry $FF
Overlay color 0
Overlay color 1
Overlay color 2
Overlay color 3
NOTE:
CR6 is bit 6 of the Command Register.
Description
S
B
DAe
data
lOa (rnA)
lOR. lOs
(rnA)
WHITE
DATA
DATA & SYNC
BLACK
BLACK & SYNC
BLANK
SYNC
1
1
0
1
0
1
0
1
1
1
1
1
0
0
$FF
data
data
$0
$0
X
X
26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0
19.05
data + 1.44
data + 1.44
1.44
1.44
0
0
NOTE:
Typical values with full scale lOG = 26.67mA. RSET = 5230,
VREF = 1.235V. S is SY'NC, B is etAfJR.
Table 2. Palette and Overlay Select
Table 3. Video Output Truth Table
lOa
mA
v
mA
v
19.05
0.714
26.67
1.000
NORMAL HIGH (WHITE)
..
--r--------------------- ------------------------ -256 "GRAY-LEVELS· -------------------------------------
1.44
9.954.
9.05
0.340
0.00
0.000
7.62
0.286
0.00
0.000
j
NORMAL LOW (BLACK)
----------------------.... _------Figure 1. Composite Video Output Waveform
Sll-14
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
Figure 2. Pixel Timing
L
ts
\
I
1~~~----------tH------------~1
R/W
CO, C1
III III
XXHXXXXI
.. 1+
I XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
HI-Z TO DATA BUS DRIVEN
~--------~
CHIP ENABLE TO DATA VALID
1/////////////
DATA VALID
-
CHIP DISABLE TO HI-Z
/\~-----------------------
~----------------ts--------------~-t;~
I
I
.1
.1
.1
IXXXXXXXXXXXXXXXXXxx
.x
xx
Figure 3. Data Bus Timing
COMP
VAA
+5.0V
iii
VREF
33J.lF
O.1J.lF
IDT75C458
OV
AnNO
FSADJ
RSET
lOB
VIDEO OUT
lOG
Figure 4. Typical Application
S11-15 .
1DT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
DESCRIPTION
PIN NAME
DATA BUS
Do - D7
8-bit, bidirectional data bus. Data Is input and output over this bus and the flow is controlled by Rm and cr. D7 is the most significant
bit.
CE"
Chip Enable input. The chip is enabled when this control pin is LOW. During a write cycle (Rm LOW), the data present on Do - D7 is
internally latched on the LOW-to-HIGH transition of this pin.
Rm
Read/Write Control input. The Read/Write input is latched on the HIGH-to-LOW transition of cr and determines the direction of the
bidirectional data bus Do - D 7.lf Rm is HIGH during the falling edge ofcr, a read cycle occurs. If Rm is lOW during the falling edge of
cr, a write cycle occurs and, additionally, Do - D7 are latched on the rising edge of cr..
CO,C1
Register Control inputs. CO and C1 determine which register or palette entry is accessed during a read or write cycle. These inputs are
latched on the HIGH-to-lOW transition of
cr.
PIXEL
ClK,
CD<
Pixel Clock inputs. These inputs are differential and may be driven by ECl operating from a +5V supply. The clock frequency is
normally the system pixel clock rate.
th
ill
Load Clock input. The load Clock is norma~~BK divided by 4 or 5 (determined by the Control Register, bit
. {A-E} and Olo - Ol1 {A-E}, I3IAl'Jl< and
are internally latched on the lOW-te-HIGH transition of
Po - P7 {A-E}
Pixel Input Data. These inputs provide the address input to the color palette RAM. The data stored at a particular address is the color
output by the DAC. Four or five consecutive pixels, as determined by bit 7 in the Command Register, are internally latched on the lOWto-HIGH transition of 1]5. The pixels are output sequentially, first {A} then {B}. After all four or five pixels have been output, the cycle
repeats. Unused inputs must be connected to a valid logic level.
Olo - Ol1 {A-E}
Pixel Overlay Inputs. The Overlay inputs have the same timing as Po - P7 and select between either the color palette or the overlay
palette. When the overlay palette is selected, the pixel information Po - Pr {A-E} is ignored. Bit 6 of the command register determines if
Overlay=O displays overlay color 0 or the color palette entry. See Table 2 for details.
~
Composite Blank Input. A lOW on this input forces the analog outputs (lOR' lOG' lOB) to the blanking level. The m:ANR input is
internally latched on the lOW-to-HIGH transition of 05. This input overrides all other pixel information.
SYNC
CompOSite Sync Input. A lOW on this input subtracts approximately 7mA from the lOG analog output and overrides no other pixel
information. For the correct SYNC level, this input should be lOW only when I3IAl'Jl< is also lOW. The ~ input is internally latched
on the lOW-to-HIGH transition of 05.
The pixel data, Po - P7
.
ANALOG
AGND
Analog Ground Power Supply, OV.
VAA
Analog Power Supply, 5V.
VREF
Voltage Reference Input, 1.235V. This input supplies a reference voltage for the DAC circuitry. Care must be taken to correctly decouple
this voltage because noise on this pin will couple directly to the DAC outputs.
FSADJ
Full-Scale Adjust Input. The current flowing from this pin to AGND is directly proportional to the full-scale analog output current. Normally, a resistor is connected between this pin and AGND . The voltage on this pin is approximately equal to V REF. The relationship
between the full-scale output current and RSET is:
lOG (mA) = 11.294 x VREF M/RSET (KO)
lOR' lOB (mA) = 8.067 x VREF M/RSET (KO)
lOG' lOR' lOB
Green, Red and Blue DAC current outputs.
COMP
Compensation Input. This pin provides the ability to compensate the internal reference operational amplifier.
S11-16
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
MILITARY AND COM MERCIAL TEM PERATU RE RANGES
INTERNAL REGISTERS
Command Register
Read Mask Register
The Command Register is accessed by reading or writing with
the Address Register = $06, CO = 0 and C1 = 1 {see Table 1).lt provides control over multiplexing and blink rate selection. The Command Register may be read or written at any time. CR7 (Command
Register bit 7) corresponds to D7 (Data Bus bit 7).
CRO
Olo display enable. This bit is ANDed internally with
the data from Olo prior to the palette selection. If
CRO is lOW, the internal Olo bits are set lOWallowing only overlay colors 0 and 2 to be selected.
CR1
Ol1 display enable. This bit is ANDed internally with
the data from Ol1 prior to the palette selection. If
CR1 is lOW, the internal Ol1 bits are set lOWallowing only overlay colors 0 and 1 to be selected.
CR2
Olo blink enable. If this bit is set HIGH, the Olo bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CRO
must be set HIGH for this function.
CR3
The Read Mask Register is accessed by reading or writing with
the Address Register = $04, CO=O and C1 = 1 (see Table 1). It
internally ANDs the pixel information with a bit from the register
before the color palette selection, effectively enabling (HIGH) or
disabling (LOW) the entire pixel plane. The Read Mask Register
may be read or written at any time. RMR7 (Read Mask Register
bit 7) corresponds to D7 (Data Bus bit 7).
Blink Mask Register
The Blink Mask Register is accessed by reading or writing with
the Address Register = $05, CO=O and C1 = 1 (see Table 1). Each
register bit causes the corresponding pixel bit (Po - P7 ) to internally
switch between the input value and 0 at the blink rate specified in
the Command Register. For this function to work, the corresponding enable bit in the Read Mask Register must be set HIGH. The
Blink Mask Register may be read or written at any time. BMR7
(Blink Mask Register bit 7) corresponds to D7 (Data Bus bit 7).
Test Register
The Test Register is accessed by reading or writing with the
Address Register = $07, CO=O and C1 = 1 (see Table 1). This
register allows the MPU to read the 24 input bits of the DACs. The
register bits are defined below.
Ol1 blink enable.lfthis bit is set HIGH, the Ol1 bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CR1
must be set HIGH for this function.
CR4, CR5
Blink Rate Select. These bits select blink rates based
on Vertical Sync cycles, defined as more than 256
LD cycles during BLANK.
CR6
Color Palette RAM enable. This bit specifies whether
to use the Color Palette or the Overlay Palette when
Olo = Ol1 = LOW.
CR7
Multiplex Select. This bit selects between 4:1
(CR7=0) or 5:1 (CR7= 1) multiplexing. When using
4:1 multiplexing, the {E} inputs are never used and
must be connected to a valid logic level.
CR7
CR6
CR5
CR4
CR3
CR2
TR7-TR4
TR3
TR2
TR1
TRO
Read data (one nibble of red, blue or green)
Upper (LOW) or Lower (HIGH) nibble select
Blue enable
Green enable
Red enable
The desired DAC is selected by setting only one color enable bit
(Do - D2 ) HIGH and the upper or lower nibble is selected with D3 .
After this write operation, a subsequent read yields the DAC data
on D7 - D4 and the previously written enable data on Do - D3 . For a
correct read, pixel and overlay data must remain constant for the
entire MPU read cycle. When BLANK is asserted, the Test Register
information D7 - D4 will be forced to zero. TR7 (Test Register bit 7)
corresponds to D7 (Data Bus bit 7).
CR1i
Y
~
.
0 d;,ob'. OLo
1 enable Olo
o disable Ol1
1 enable al1
' -_ _ _ _ _ _ _ _- \ 0 blinking of Olo disabled
1 blinking of Olo enabled
L -_ _ _ _ _ _ _ _ _ _ _- - \
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
'-----------------------1
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
0 blinking of al1disabled
1 blinking of al1enabled
0016 Vsync on /48 Vsync off
01 16 Vsync on /16 Vsync off
10 32 Vsync on /32 Vsync off
11 64 Vsync on /64 Vsync off
0 Use overlay color 0
1 Use color palette 0
04:1 Multiplex
1 5:1 Multiplex
COMMAND REGISTER DESIGNATIONS
S11-17
......_--"." .. -.."._-" ----_._- ._..__._._--"'--,,_._------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
RMR7
RMR6
RMR5
RMR4
RMR3
RMR
T
"1."0 ...
:::::~
.
1 enable P,
L...-----------I
0 disable P2
1 enable P2
L...-_ _ _ _ _ _ _ _ _ _ _ _-I
0 disable P3
1 enable P3
L...-_ _ _ _ _ _ _ _ _ _ _ _ _~_
__I
0 disable ~.
1 enable P4
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - I
0 disable Ps
1 enable Ps
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I
0 disable P
e
1 enable Pe
--I 0 disable P
7
1 enable P7
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
READ MASK REGISTER DESIGNATIONS
BMR7
BMR6
BMR5
BMR4
BMR3
BMR2
BMR1
. .1
BMRO
I .:Qd;,~e ~inklng
Po
1 enable Po blinking
o disable P,
blinking
1 enable P, blinking
'--_ _ _ _ _ _ _ _--1 0 disable P2 blinking
1 enable P2 blinking
'---------------1
o disable P3 blinking
1 enable P3 blinking
-I 0 disable P blinking
4
1 enable P4 blinking
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
------ --- ------.------------------- ------------ -------- -------------
-O-disableP~-blinkjng----
1 enable Ps blinking
-I 0 disable P blinking
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
e
1 enable Pe blinking
--I 0 disable P blinking
7
1 enable P7 blinking
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
BLINK MASK REGISTER DESIGNATIONS
Sl1-18
---------------------------
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
ABSOLUTE MAXIMUM RATINGS
(1)
RATING
SYMBOL
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
VALUE
UNIT
POWER SUPPLIES
VAA
Measured to AGND
-0.5 to +7.0
V
Measured to AGND
-0.5V to VAA + 0.5
V
Measured to AGND
INPUT VOLTAGE
Applied Voltage(2)
OUTPUT
Applied Voltage(2)
-0.5V to VAA + 0.5
V
Applied Current(2.3.4) Externally forced
-1.0 to +6.0
mA
Short
Circuit Duration
1.0
S
Single output
High to AGND
TEMPERATURE
Operating.
Ambient
Storage
°C
Military
-55 to +125
Commercial
o to +70
°C
Military
-65 to +150
°C
Commercial
-55 to +125
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect reliability. Absolute Maximum Ratings are limiting values applied individually while all other
parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is speCified as conventional current when flowing into the .
device.
iii
S11-19
-, ....
,._---_._-----
- - - - _ _._-_..--------,
..•
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITIONS
PARAMETER
VAA
Power Supply
Measured to AGND
IAA
Power Supply Current
VAA = Typ., Static
UNIT
MIN.
TYP.
MAX.
4.75
5.0
5.25
V
-
200
-
mA.
"'H(1)
Input Voltage HIGH
2.0
-
VAA +0.5
V
"'l(1)
Input Voltage LOW
AGND -O·5
-
O.S
V
VCIH
Clock Input Voltage HIGH
VAA -1.0
VAA +0.5
V
VCll
Clock Input Voltage LOW
AGND-0.5
-
-
-
VAA -1.6
1
jJA
-
-
1
jJA
IIH
III
Input Current HIGH
Input Current LOW
VOH
Output Voltage HIGH
VOL
Output Voltage LOW
loz
= 2.4V
VIN = O.SV
VAA = Min., 10H = -SOOjJA
VAA = Min., 10l = 6.4mA
"'N
2.4
-
Output 3-State Current
V
-
V
0.4
V
10
jJA
NOTE:
1. All digital inputs except ClK and CD<.
AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA=O°C to +70°C (Commercial Temperature Range)
TA = -55°C to + 125°C (Military Temperature Range)
VAA = 5.0V ±5%
TTL Inputs, Vil =O.8V, VIH =2.0V, rise/fall time <5ns
ClK Inputs, '-"H= VAA -1.0V, '-"l =VAA -1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
1DT75C458-165
SYMBOL
PARAMETER
IDT75C458-135
MIN.
MAX.
MIN.
MAX.
FClK
Clock Frequency
-
165
-
FLO
ill Clock Frequency
-
41
-
tcs
Control Set-up Time; CO, C1, R!W
0
o .:::::t : : :.
tCH
Control Hold Time; CO, C1, R!W
15
-
S}35
,:::
15,:::::::::
20 ".:.::
tCEH
ct: HIGH Time
20
-
tCEl
t CEZO
CE:LOWTime
30
-
,:@:\:::::
CE: to Data Bus Driven
10
-
10'::\}
CE: to Data Valid
-
30
CE: to Data Bus HI-Z
-
15
tWDS
Write Data Set-up Time
30
- <:: ::::)::::9.9.::
.i':::::.
~'fr
:::::;::::::::::::.
tCLKCY
Clock Cycle Time
6
..7:::::.::::;:
:::':'1.4
tCLKPl
Clock Pulse Width LOW
2.8
':':';'::::'!/
tCLKPH
t lDCY
Clock Pulse Width HIGH
2.8
·J.O
::::: 3.0
ill Cycle Time
ill Pulse Width
ill Pulse Width
24
)):h:::::.
...•:;
~
t}: -
~
tCED
t CEoZ
-tWDH- Write Data Hold -Time - - - - - 0
_
}::i:@1::::,::
-':::::\::
29
s::':s:::ilif
12
IDT75C458-125
IDT75C458-110
IDT75C458-80
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
125
-
110
-
SO
MHz
32
-
28
-
20
MHz
0
-
0
15
15
25
-
25
50
-
50
10
-
UNIT
0
-
ns
15
-
ns
ns
25
-
50
-
ns
10
-
ns
-
10
30
-
50
-
50
-
75
ns
15
15
-
15
-
15
ns
-
35
-
35
-
-- - - 0 -
--0-
-
50
-0--
-ns
-
-
9
-
12
-
-
ns
ns
8
3.2
4
-
3.2
-
4
31
-
13
-
13
3
5
ns
ns
ns
35
-
50
-
15
-
20
-
ns
-
15
20
-
2
2
-
ns
2
-
ns
5
tps
Pixel Data Set-up Time
10::::':: }:.::::
2'.:::: {
tpH
Pixel Data Hold Time
:yV':::::!:: I·::::::::::::
2
-
tAAD
Dynamic Supply Current
Commercial Temp.
):i;:.: ~ ::'!:'!j: 1\== 450
-
425
-
400
-
380
-
360
mA
tAAD
Dynamic Supply Current
Military Temp.
-
475
-
450
-
430
-
410
mA
t LOPH
t LDPl
HIGH
10"
LOW
{toN
12
3
'.:.
-::::::t::; ~'k
500
S11-20
3
4
ns
M ILiTARY AN D COM M ERCIAL TEM PERATU RE RANGES
IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™
ANALOG OUTPUT DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITIONS
PARAMETER
Res
Resolution
I LSB
LSB Current Size
MIN.
Lo
Voc
Output Compliance Voltage
RAOUT (2)
CAOUT (2)
Output Impedance
MAX.
UNIT
bits
1/2 LSB VERSION
-
1/4
±1/2
LSB
1 LSB VERSION
-
1/2
±1
LSB
1/2 LSB VERSION
-
1/4
±1/2
LSB
-1.0
-
1.2
1 LSB VERSION
LI
TYP.
8
-
69.1
-
jJA
1/2
±1
LSB
V
50
Output Capacitance
kO
8
f = 1MHz. lOUT = OmA
pF
12
10
jJA
EM
VREF Input Current
Matching Error (DAC to DAC)
-
2
5
%
PSRR
Power Supply Rejection Ratio
-
50
-
dB
IREF
Iw(1)
White Current
Measured to Blank
17.69
19.05
20.40
mA
Iw(1)
White Current
Measured to Black
16.74
17.62
18.50
mA
I B(1)
Black Current
Measured to Blank
0.95
1.44
1.90
mA
I BLANK
IBLANK (l)
Blank Current lOR. lOB
0
5
50
jJA
Blank Current lOG
6.29
7.62
8.96
mA
I SYNC
Sync Current lOG
0
5
50
jJA
NOTE:
1. RSET =5230. VREF =1.235V
2. This parameter is guaranteed but not tested in production.
ANALOG OUTPUT AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA = O°C to + 70°C (Commercial Temperature Range)
TA = -55 0Q to + 125°C (Military Temperature Range)
VAA = 5.0V ±5"10
TTL Inputs, V IL =O.8V, VIH =2.0V, rise/fall time <5ns
ClK Inputs, VIH = VAA -1.0V, "'L =VAA -1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
r------------r------------r------------r------------r------------,
IDT75C458-165
IDT75C458-135
IDT75C458-125
1DT75C458-110
IDT75C458-80
SYMBOL
PARAMETER
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP.
FCLK
Clock Frequency
tvo
Video Output Delay Time
15
1.5
165
1§::: ••.
tVT
Video Output Transition Time
ts
Video Output Skew (1)
0
tSI (2)
Video Output Settling Time
t.)
5Q.,••. Ijj>\·
FT(2)
Clock and Data Feedthrough
GE(2)
CT(2)
Glitch Energy
tvp
Pipeline Delay
-
<2
6
\ • 1:.-
./pi}: /·'106
g>
9
......
9
"1t
0
TYP. MAX. UNIT
80
15
1.8
<2
MAX MIN.
110
15
'\):f':
<. f{:: \. ···0
.:<60 •. }·
Crosstalk. DAC to DAC
125
1;35
2
<2
0
ns
2
0
<2
MHz
ns
15
<2
ns
7
8
8
12
ns
50
50
50
50
pV-s
50
50
50
50
pV-s
100
100
100
100
pV-s
9
NOTE:
1. C L = 10pF. 10%-90% pOints
2. This parameter is guaranteed but not tested in production.
S11-21
- - - - - - - - - - - - - - _ . _ - _....
9
9
9
9
9
9
clock
ill
IDT75C458 CMOS TRIPLE a-BIT PALETTEDAC ™
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 5. Video I/O Timing Diagram
tMPUCY
tCEH
tcs
tCH
CO,C1
.1
:X I
.II X
R/W
II
I
I
'I
II
tWDS
I
XXXXXXXXX
'I
XI XI
I
'I
I
XII
I
I
'XXXXXXI
[X
,x
,I
X IUXXXXXXX
.XXII
.XX
,xx
tWDH--i
III I
IXXXXI
:XXXXXXXXXXx
.Xl
. .1.
XXX
I
Figure 6. MPU WRITE Timing Diagram
tMPUCY
tCEH
------CE"-- ------------------
----.- . _ . _ - - - - - - - - - - - -
-_...•
--------_ .
._------_ .... _-
--------_._-- - -
tcs
tCH
CO, C1
:Xl
:I
R/W
:I
XXXXXXXXXXXXXXI
:I
[XXXXXXXXXXXX XX
..
t CED I-t-tCEZO
xx xx xx xxx x :1
I--tcEOZ"
'\
I
1/////////////
I\.'\'\'\'\'\'\'\'\'\'\'\'\
Figure 7. MPU READ Timing Diagram
511-22
[XX
:xx .UU
:I
:xx
:Xl
: UXX XX XXXXX XX XXX XXX XX XX
----------------
IDT75C45a CMOS TRIPLE a-BIT PALETTEDAC rio!
MILITARYANDCOMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
DeV~ype
x·
Process/
Temperature
Range
Y:LANK
'--_ _ _ _ _ _ _--I
G
J
~--~------------------~!~~}
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-B83. Class B
Pin Grid Array
PLCC
Speed in Megahertz
135
165
~----------------~------------~S
~--------~------------I 75C458
Standard Power
Triple 8-bit PaietteDAC ™
[[J
S11-23
.IOT 75C48
CMOS FLASH
AID CONVERTER
Integrated Device'i!chnology.lnc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT75C48 is a 30 MegaSample per Second (MSPS), fully
parallel, 8-bit Flash Analog to Digital Converter. The wide input
analog bandwidth of 10 MHz permits the conversion of analog input signals with full-power frequency components up to this limit
with no i~ut sample and hold. Low power consumption, due to
CEMOS T processing, virtually eliminates thermal considerations. The IDT75C48 is available in 28-pin plastic and hermetic
DIPs and a 28-pin LCC.
The IDT75C48 consists of a reference voltage generator, 255
comparators, encoding and EDC (Error Detection and Correction)
logic and an output data register. A single clock starts the conversion process and controls all internal operations. Two control inputs allow the output coding format to be programmed for straight
binary or offset two's complement in either the true or inverted
form.
The IDT75C48 military Flash ND Converters are manufactured
in compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.
o
•
•
•
•
•
•
•
8-bit resolution
30 MSPS conversion rate
Guaranteed no missing codes
Pin- and function-compatible with TRW 1048
Low power consumption: 500mW
Extended analog input range
On-chip EDC (Error Detection and Correction)
Improved output logic HIGH drive, no pull-up needed
No sample and hold required
Differential Phase < 1 Degree
Differential Gain < 2%
Selectable output formats
• TTL-compatible
• Available in 28-pin Plastic DIP, CERDIP and LCC
• Military product is compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
NMINV
NLiNV
VIN
CONV
1
RT
~~
R1
R
~~
>
R
R
~
R/2
~
~~
255 TO 8
ENCODE
+EDC
RM
----
R/?_
-
-
-~
~---
-.
LATCH
~
- _ . _ - - - - - - - - - - - - - - - - _.
-
R
R
>
~~
R
~
~
R2
RS
255 DIFFERENTIAL
COMPARATORS
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-4003/-1
S11-24
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT75C48 FLASH AID CONVERTER
PIN CONFIGURATIONS
INDEX
NMINV
D2
RM
D3
RB
AGND
VIN
VIN
VIN
VIN
VIN
AGND
RT
CONY
Da(LSB)
D4
DGND
Vee
VEE
VEE
VEE
Vee
DGND
NLiNV
D5
D6
I
I
~
DGND
:J 5
Voo
~6
:J 7
:J a
VEE :J 9
VEE
VEE
Vee
DGND
I
I
~
I
I
......
I
I
II
I
I
I
I
I
I
432L.l282726
L28-1
AGND
~[
V~
23[
VIN
VIN
22[
:1 10
:1
25 [
20[:
19[
11
12 13 14 15 16 17 18
nnnnnnn
~ocfoffi~~
::J
-l
Z
D7
Lce
DIP & SOIC
TOP VIEW
0
~o
o
TOP VIEW
Due to the unavoidable coupling with the clock and the input
signal, RT and RB should provide low AC impedance to ground.
For applications with a fixed reference, a bypass capacitor is
recommended.
GENERAL INFORMATION
The IDT75C48 has four functional sections: a comparator array,
a reference voltage generator, encoding logic with EDC and output
logic. The comparator array compares the input signal with 255 reference voltages to produce an N - of - 255 code. This is sometimes
called a "Thermometer" code because all of the comparators with
their reference voltage less than the input signal will be "on," while
those with their reference above the input will be "off."
The reference voltage generator consists of a string of precisely
matched resistors which generate the' 255 voltages needed by the
comparators. The voltages at the ends of the resistor string set the
maximum and minimum conversion range and are typically OV
and -2V, respectively.
The encoding logic converts the "Thermometer" code into binary or offset two's complement numbers and can invert either
code. Included in the encoding function is Error Detection and
Correction logic which ensures that a corrupted Thermometer
code is correctly encoded.
The output logic latches and holds the data constant between
samples. The output timing is designed for an easy interface to external latches or memories using the same clock as the ADC.
CONTROL
The IDT75C48 provides two function control pins, NMINV and
NLiNV. These controls are for steady state use and are usually tied
to the appropriate voltages. They control the output coding format
in either straight binary or offset two's complement. In addition,
both formats may be either true or inverted. These pins are active
low and perform the functions shown in Figure 1.
CONVERT
The IDT75C48 begins a conversion with every rising edge of the
convert signal, CONY. The analog inpl.!t signal is sampled on the
rising edge of CONY, while the outputs of the comparators are encoded on the falling edge. The next rising edge latches the encoder output which is presented on the output pins.
The input sample is taken within 15ns of the rising edge of
CONY and is called tSTO or the Sampling Time Offset. This delay
varies by a few nanoseconds from part to part and as a function of
temperature, but the short term uncertainty or jitter is less than
POWER
The IDT75C48 requires two power supply voltages, Vee and
VEE. Typically, VEE = -5.2V and Vee = + 5.OV. Two separate
grounds are provided, AGND and DGND, the analog and digital
grounds. The difference between AGND and DGND must not exceed
±O.1V and all power and ground pins must be connected.
REFERENCE
The IDT75C48 converts analog input signals that are within the
range ofthe reference (VRB ~ VIN ~ VRT) into digital form. VRB (Reference Bottom) and VRT (Reference Top) are applied across the
reference resistor chain and both must be within the range of
+ 2.1V to -2.1V. In addition, the voltage applied across the reference resistor chain (VRT-VRB) must be between 1.8V and 2.2V, with
VRT more positive than VRB. Nominally, VRT = O.OV and VRB = -2.0V.
The IDT75C48 provides a midpoint tap, RM, which allows the
converter to be adjusted for optimum linearity or a non-linear
transfer function. Adjustment of RM is not necessary to meet the
linearity specification. Figure 5 shows a circuit which will provide
approximately 1/2 LSB adjustment of the midpoint. The characteristic impedance of RM is about 1700 and this node should be
driven from a low impedance source. Any noise introduced at this
point will couple directly into the resistor chain, seriously affecting
performance.
Gaps.
If the maximum CONY pulse width HIGH time (tpWH) is exceeded, the accuracy of the input sample may be impaired. The
maximum CONY pulse width LOW time (tpWL) may be exceeded,
but the digital output data for the sample taken by the previous rising edge of CONY will be meaningless. It is recommended that
CONY be held LOW during longer periods of inactivity,
The digital output data is presented at tD, the Digital Output Delay Time, after the next rising edge of CONY. Previous output data
is held for the tHO (Output Hold Time) after the rising edge of CONY
to allow for non-critical timing in the external circuitry. This means
that the data for sample N is acquired while the converter is taking
sample N+2.
ANALOG INPUT
The IDT75C48 uses strobed, auto-zeroing, latching comparators. All five analog input pins must be connected together as close
to the package as possible.
If the analog input signal is within the reference voltage range,
the output will be a binary number between aand 255. An input signal above VRT will yield a full-scale positive output while an input
below VRB will cause a full-scale negative output.
S11-25
iii
1DT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STEP
BINARY
RANGE
OFFSET TWO'S
-2.0000V FS
7.8431 mV/STEP
-2.0480V FS
8.000mV/STEP
NMINV=1
NLlNV=1
NMINV=O
NLlNV=O
NMINV=O
NLlNV= 1
NMINV=1
NLlNV=O
000
001
O.OOOOV
-0.0078V
O.OOOOV
-0.0080V
00000000
00000001
11111111
11111110
10000000
10000001
01111111
01111110
127
128
129
-0.9961V
-1.0039V
-1.0118V
-1.0160V
-1.0240V
-1.0320V
01111111
10000000
10000001
10000000
01111111
01111110
11111111
00000000
00000001
00000000
11111111
11111110
254
255
-1.9921V
-2.0000V
-2.0320V
-2.0400V
11111110
11111111
00000001
00000000
01111110
01111111
10000001
10000000
Figure 1. Output Coding
SAMPLE N+2
DIGITAL OUTPUT
Figure 2. Timing Diagram
Vee
8100
TO OUTPUT PIN
...
o-_-+~-
40pF
1N3062
Figure 3. Output Load 1
S11-26
1DT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
VALUE
UNIT
POWER SUPPLY
Vcc
Measured to DGND
-0.5 to +7.0
V
VEE
Measured to AGND
+0.5 to -7.0
V
AGND
Measured to DGND
-0.5 to +0.5
V
CONV, NMINV, NLiNV
Measured to DGND
-0.5 to Vcc + 0.5
V
V 1N ,VRT,VRB
Measured to AGND
Vcc to VEE
V
VRT
Measured to VRB
-4.0 to +4.0
V
V
INPUT VOLTAGE
OUTPUT
Measured to DGND
-0.5 to Vcc + 0.5
Applied Current (2. 3, 4)
Externally forced
-3.0 to +6.0
Short Circuit Duration
Single output High to DGND
1.0
S
Military
-55 to +125
°C
Commercial
o to +70
°C
Military
-65 to +150
°C
Commercial
-55 to +125
°C
Applied Voltage
(2)
mA
TEMPERATURE
Operating.
Ambient
Storage
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational section ofthis specification is not implied. Exposureto Absolute Maximum Rating conditions
for extended periods may affect reliability. Absolute Maximum Ratings are limiting values
applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.
iii
S11-27
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT75C48 FLASH AID CONVERTER
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEMPERATURE RANGE
COMMERCIAL
MILITARY
TEST CONDITIONS
MIN.
NOM.
MAX.
MIN.
UNIT
NOM. MAX;
POWER SUPPLY
Vee
Positive Power Supply
4.75
5.0
5.25
4.5
5.0
5.5
V
VEE
Negative Power Supply
-4.9
-5.2
-5.5
-4.9
-5.2
-5.5
V
VAGND
Analog Ground Voltage (ref DGND )
-0.1
0
+0.1
-0.1
0
+0.1
V
Icc
Positive Supply Current
Vee = Max., Statie(l)
50
70
-
60
80
mA
lEE
Negative Supply Current
VEE = Max., Statie(l)
-
-25
-35
-
-25
-35
mA
V
DIGITAL INPUTS (CONV, NMINV, NLlNV)
VIL
Input Voltage, Logic LOW(4)
-0.5
-0.5
-
0.8
Input Voltage, Logic HIGH(4)
2.0
-
0.8
VIH
Vee +·1
2.0
-
Vee +.1
V
IlL
Input Current, Logic LOW
Vee = Max., ~L = 0.5 V
-
-
±10
-
-
±10
J.lA
IIH
Input Current, Logic HIGH
Vec = Max., VIH = 2.4 V
-
-
50
50
J.lA
CI
Digital Input Capacitance(4)
TA = +25°C, F = 1 MHz
-
15
-
-
J.lA
Vec = Max., VI = Vee
-
±10
Input Current, Max. Input Voltage
-
±10
II
15
pF
4.0
-
-
4.0
mA
-2
-2
mA
0.5
-
-
0.5
V
-
2.4
-
-
V
-
-
-50
mA
DIGITAL OUTPUTS
10L
Output Current, Logic LOW
-
10H
Output Current. Logic HIGH
-
VOL
Output Voltage, Logic LOW
Vec = Min., 10L = Max.
-
VOH
Output Voltage, Logic HIGH
Vec = Min., 10H= Max.
2.4
-
los
Output Short Circuit Current
Vec = Max.(2)
-
-
-50
REFERENCE
VRT
Most Positive Reference Voltage(3)
-0.1
0
+0.1
-0.1
0
+0.1
V
VRB
Most Negative Reference Voltage (3)
-1.9
-2.0
-2.1
-1.9
-2.0
-2.1
V
VRT- VRB
Reference Voltage Range
1.8
2.0
2.2
1.8
2.0
2.2
V
IREF
Reference Current (RT to RB)
VRT , VRB = Nom.
-
5
9
-
6
10
mA
RREF
Reference Resistance (R T to RB)
VRT , VRB = Nom.
250
400
-
200
330
-
Ohm
VRB
-
VRT
V
-
KOhm
ANALOG INPUT
~N
Input Voltage Range
VRB
Equiv. Input Resistance(4)
VRT , VRB = Nom., VIN = VRB
100
-
VRT
RIN
-
100
-
-
50
-
-
10
CIN
Equiv. Input Capacitance(4)
VRT , VRB = Nom., VIN = VRB
leB
Input Const. Bias Current
VEE = Max.
TA
Ambient Temperature, Still Air
0
-
70
-
Te
Case Temperature
-
-
-
-55
50
pF
10
J.lA
-
°C
+125
°C
NOTES:
- - - - - - - - - - - - - -- - - - - - - - - - - - - ----1:-Worst ease;-all digital inputs-and-outputs-lOW.
2. Output HIGH, one pin to ground, one second duration.
3. VRT must be more positive than VRB and the voltage reference must be within the specified range. Although the device is specified and tested with the
reference equal to OV and -2V, the part will operate with VRT up to + 2.1V. Likewise, the reference range may vary from 1.2V to 2.6V.
4. This parameter is guaranteed but not tested in production.
511-28 .
·_--_._---_.•. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IDT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS FOR IDT75C48 x 20 (20 MHz Version)
Specifications over the DC Electrical range unless otherwise stated_
SYMBOL
PARAMETER
TEMPERATURE RANGE
COMMERCIAL
MILITARY
TEST CONDITIONS
MIN.
TYP.
MAX.
MIN.
TYP.
UNIT
MAX.
Fs
Conversion Rate
20
30
-
20
30
-
MSPS
tpwL
CONV, Pulse Width Low(3)
18
-
100,000
18
100,000
ns
tpWH
CONV, Pulse Width HIGH(3)
22
-
20,000
22
-
20,000
ns
tsTO
Sampling Time Offset
-
10
0
-
15
ns
Vcc
= Min., VEE = Min_
Vcc
= Min., VEE = Min_
0
-
-
60
-
-
60
ps
= Min., VEE = Min., Load 1
= Min., VEE = Min_, Load 1
-
-
30
-
35
ns
5
-
-
5
-
-
ns
-
0.2
0.2
%FS
0.3
-
0.3
%FS
-
-
0.2
-
-
-
-
-
0.2
%FS
25
100
175
25
100
175
%Nom
EAP
Aperture Error (4)
to
Digital Output Delay
Vcc
tHo
Digital Output Hold Time
Vcc
I 1/2 LSB(2)
ELI
Linearity Error, Integral
VRT ,VRB
= Nom_
ELO
Linearity Error, Differential
VRT , VRB
= Nom.
CS
Code Size (1)
EOT
Offset Error, Top
V1N
-
10
45
-
10
45
mV
EOB
Offset Error, Bottom
V1N
-
-10
-30
-
-10
-30
mV
Tco
Offset Error, Temperature Coefficient (4)
-
-
±20
-
-
±20
'tJV/oC
BW·
Bandwidth, Full Power Input
7
12
-
5
10
-
MHz
-
-
20
-
-
20
nS
-
53
52
55
55
dB
dB
44
43
46
46
-
36.5
39
-
dB
li-R
NPR
= midpoint of code 0
= midpoint of code 255
V1N = VRB
. Transient Response, Full Scale(4)
Signal to Noise Ratio
SNR
I 3/4 LSB(2)
20 MSPS Conversion Rate,
10 MHz Bandwidth
Peak SignallRMS Noise
1.248 MHz Input
2.438 MHz Input
54
53
56
56
RMS Signal/RMS Noise
1.248 MHz Input
2.438 MHz Input
45
44
47
47
36.5
39
-
.5
1
-
_5
1
Degree
1
2
-
1
2
%
Noise Power Ratio
DC to 8 MHz White Noise
Bandwidth 4 Sigma Loading
1.248 MHz Slot
20 MSPS Conversion Rate
DP
Differential Phase Error
Fs
DG
Differential Gain Error
Fs
= 4 x NTSC
= 4x NTSC
dB
dB
NOTES:
1. Guarantees no missing codes_
2. See the ordering information section regarding the part number designation_
3. No damage to the part will occur if Max_ times are exceeded_ See the Convert Section for more information about the Conv Max. time limitations.
4. This parameter is guaranteed but not tested in production.
S11-29
[II
IDT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS FOR IDT75C48 x 30 (30 MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
SYMBOL
PARAMETER
TEMPERATURE RANGE
MILITARY
COMMERCIAL
TEST CONDITIONS
MIN.
TYP.
MAX.
MIN.
TYP.
UNIT
MAX.
Fs
Conversion Rate
30
40
-
30
40
-
MSPS'
tpwi.
CONV. Pulse Width Low
14
-
100,000
14
-
100,000
ns
tpWH
CONV, Pulse Width HIGH
14
-
20,000
14
-
20,000
ns
t STO
Sampling Time Offset
0
-
10
0
-
15
ns
-
-
60
60
ps
25
-
-
-
28
ns
5
-
-
5
-
-
ns
-
-
0.3
-
0.3
%FS
-
0.4
-
0.4
%FS
-
-
0.2
-
-
0.2
%FS
%Nom
Vee
= Min .• VEE = Min.
Vee
= Min .• VEE = 'Min.
= Min., VEE = Min., Load 1
= Min .• VEE = Min., Load 1
EAP
Aperture Error(4)
tD
Digital Output Delay
Vee
tHO
Digital Output Hold Time
Vee
I 3/4 LSB(2)
El.I
Linearity Error, Integral
VAT, VAB
= ,Nom.
ELD
Linearity Error, Differential
VAT, VAB
= Nom.
CS
Code Size (1)
25
100
175
25
100
175
EOT
Offset Error, Top
VIN = midpoint of code 0
-
10
45
-
10
45
mV
EOB
Offset Error, Bottom
VIN
-
-10
-30
-
-10
-30
mV
Teo
Offset Error, Temperature Coeffieient(4)
= midpoint of code 255
VIN = VAB
-
-
±20
-
-
±20
JJV!°C
BW
Bandwidth, Full Power Input
10
13
-
8
10
-
MHz
"lTR
Transient Response, Full Scale(4)
-
-
20
-
-
20
nS
-
49
48
53
52
-
dB
dB
Signal to Noise. Ratio
SNR
NPR
I 1 LSB(2)
'
30 MSPS Conversion Rate,
15 MHz Bandwidth
Peak SignalJRMS Noise
5 MHz Input
10 MHz Input
50
49
53
52
RMS SignalJRMS Noise
5 MHz Input
10 MHz Input
41
40
44
43
-
40
39
44
43
-
dB
dB
DC to 15 MHz White Noise
Bandwidth 4 Sigma Loading
5 MHz Slot
30 MSPS Conversion Rate
-
-
-
-
-
-
dB
-
.5
1
1
Degree
2
-
.5
1
1
2
%
Noise Power Ratio
DP
DifferentialPhase Error
Fs
DG
Differential Gain Error
Fs
= 4x NTSC
= 4x NTSC
-',
NOTES:
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number designation.
3. No damage to .the part will occur,if Max. times are exceeded. See the Convert Section for more information about the Conv Max. time limitations.
4. This parameter is guaranteed but not tested in production.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S11;..30
-
IDT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CALIBRATION
TYPICAL INTERFACE
The calibration of the IDT75C48 involves the setting of the 1st
and 255th comparator thresholds to the desired voltages. This is
done by varying the top and bottom voltages on the reference resistor chain, VRT and VRB, to compensate for any internal offsets.
Assuming a nominal OV to -2V reference range, apply -O.0039V (1/2
LSB from OV) to the analog input, continuously strobe the device
and adjust VRT until the converter output toggles between the
codes of 0 and 1. To adjust the 255th comparator, apply -1.996V
(1/2 LSB from -2V) to the analog input and adjust VRB until the converter output toggles between the codes 254 and 255.
The offset errors are caused by the parasitic resistance between
the package pins and the actual resistor chain on chip and are
shown as R1 and R2 in the Functional Block Diagram. The offset
errors, EOT and. EOB are specified in the AC Electrical Characteristics Table and indicate the degree of adjustment needed.
The previously described calibration scheme requires that both
ends Of the reference resistor chain be adjustable, Le., be driven by
operational amplifiers. A Simpler method is to connect the top of
the resistor chain, RT, to analog ground or OV and to adjust this end
of the range with the input buffer offset contro\. The offset error at
the bottom of the resistor chain results in a slight gain error, which
can be compensated for by varying the voltage applied to RB. This
is a preferred method for gain adjustment since it is not in the input
signal path. See Figure 4 for a detailed circuit diagram of this
method.
Figure 4 shows a typical application example for the I DT75C48.
The analog input amplifier is a bipolar wideband operational amplifier whose low impedance output directly drives the AID Converter. The input buffer amplifier is configured with a gain of minus
two which will convert a standard video input signal (1V p-p) to the
recommended 2V converter input range. All five V1N pins are connected together as close to the package as possible and the input
buffer feedback loop is closed at this pOint. Bipolar inputs, as well
as the calibration of the reference top, are accomplished using the
offset control. A band-gap reference is used to provide a stable
voltage for both the offset and gain contro\. A variable capacitor in
the input buffer feedback loop allows optimization of either the step
or frequency response and may be replaced by a fixed value in the
final version of the printed circuit board.
To ensure operation to the rated specifications, proper decoupiing is needed. The bypass capacitors should be located close to
the Chip with the shortest lead length possible. Massive ground
planes are recommended. If separate digital and analog ground
planes are used, they should be connected together at one point
close to the IDT75C48.
. The bottom reference voltage, VRB, is supplied by an inverting
amplifier buffered by a PNP transistor. The tranSistor provides a
low impedance source and is necessary to provide the current
flowing through the resistor chain. The bottom reference voltage
may be adjusted to cancel the gain error introduced by the offset
voltage, EOB, as discussed in the calibration section.
iII
_._-_..__.-
511-31
.------ ------- - - - - - - - _...__._-_......
... __
__
.
._------_._---_._------------
IDT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+SV--------~._----------------~------------._----~--_,
PARTS LIST
R1
@ ANALOG
~
INPUT
R7
10
20
21
R12
22
23
24
U4
Vee Vee
"iN
"iN
V1N
"iN
"iN
0 1 (MSB)
RB
O2
AGND
18
27
17
0.00
80.7!1
1KO
2KO
2200
2KO
1KO
2KO
2KO
10KO
20KO
270
C1-C4
CS-C14
C1S
10J..l.F
0.1J..1.F
1-6pF Variable
U1
U2
U3
U4
IDT7SC48
HA-2S39-S
uA741C
LM313
01
2N2907
L1,L2
Ferrite Bead
U1
IDT7SC48
26
R1
R2
R3
R4
RS
R6
R7
R8
R9
R10
R11
R12
03
D4
RT
D5
RM
D6
CONV
D7
D8 (LSB)
5,11
CLOCK
13
14
15
16
-S.2V
Figure 4. Application Example
RT
________ RM _ _ _ID.flSC~8--- ___________________________ _
RS
-2.00V
----~------------------I
Figure 5. Mid-Point Adjust
S11-32
IDT75C48 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxx
Device Type
X
Power
X
X
x
Speed
Package
Process/
Temperature
Range
y~LANK
P
D
'-------------------1 L
SO
'--______________________
~
20
30
k -________
~
____________________
L-______________________________________
~
~
SB
S
SC
75C48
Commercial (DOC to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP (600 mil)
Leadless Chip Carrier
Small Outline IC
MHz
MHz
Standard Power, 1/2 LSB Integral Linearity
Standard Power, 3/4 LSB Integral Linearity
Standard Power, 1 LSB Integral Linearity
Flash A/D Converter
ill
Sll-33
Integrated Device lechnology.lnc.
CMOS FLASH
AID CONVERTER
lOT. 75C58
FEATURES:
DESCRIPTION:
• 8-bit resolution
• 30 MSPS conversion rate
The IDT75C58 is a 30 MegaSample per Second (MSPS), fully
parallel, 8-bit Flash Analog to Digital Converter. The wide input
analog bandwidth of 10MHz permits the conversion of analog input signals with full-power frequency components up to this limit
with no input sample and hold. Low power consumption due to
CEMOS™ processing virtually eliminates thermal considerations.
The IDT75C58 is available in 28-pin plastic and hermetic DIPs and
a 28-pin LCC.
The IDT75C58 consists of a reference voltage generator, 256
comparators, encoding and EDC (Error Detection and Correction)
logic and an output data register. A single clock starts the conversion process and controls all internal operations. An additional
comparator detects an Overflow condition (VIN more positive than
Full-Scale + 1LSB) and activates the OVFL output. This output, together with two output enable inputs (OE1 and OE2), allow the
stacking of two IDT75C58s for 9-bit resolution with no external
components.
The IDT75C58 military Flash NO Converters are manufactured
in compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.
• Overflow Output
• Low power consumption: 500mW
• Guaranteed no miSSing codes
• Power-Down mode
• Extended analog input range
• On-chip EDC (Error Detection and Correction)
• Tri-state outputs
• Improved output logic HIGH drive, no pull-up needed
• No sample and hold 'required
• Differential Phase = 1 Degree
• Differential Gain
= 2%
• TTL-compatible
• Available in 28-pin CERDIP and Plastic DIP or LCC
• Military product is compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
CONV
VIN
I
RT
R1
R
~~5
R
~~4
R
~V
R ;R
0E'1
f-
:
256 TO 9
ENCODE
+EDC
128
~V
R/2
R/2 ~-
OVFL
.
R
--
1
256
-
-
-
~
LATCH
- - - - - - - - ------ - - - - - - - - - - - - -
~
---
127
~;::t/
:
:
2
R
~H?
R2
.... 0/
1
256 DIFFERENTIAL
COMPARATORS
J
OE2
I
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-5OO4/2
S11-34
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1DT75C58 FLASH AID CONVERTER
iD
PIN CONFIGURATIONS
en
::E
OE2
D7 (MSB)
INDEX
0
"OET
D6
D5
D4
DoNo
Vee
VEE
VEE
VEE
Vee
DoNO
DoNO
Vee
VEE
VEE
VEE
Vee
DoNO
RM
V1N
V1N
AGNO
RT
Vee
CONV
Do (LSB)
D3
D2
(0
,.-
";::
LJULJII'UUU
RB
AGNO
IBAdj
OVFL
N
W w· co
oooOOa:
LO
:1 5
432W282726
25[
:le
24[
23[
:17
:1 8
L28-1
22[
:19
21[
:1 10
20[
:1 11
19[
AGNO
IBAdj
RM
V1N
V1N
AGNO
RT
12 13 14 15 16 17 18
nnnnnnr.
iioooiD~8
D1
6
~
8::>
LCC 0°
TOP VIEW
DIP & SOIC
TOP VIEW .
GENERAL INFORMATION
The IDT75C58 has four functional sections: a comparator array,
a reference voltage generator, encoding logic with EDC and output
logic. The comparator array compares the input signal with 256 reference voltages to produce an N - of - 256 code. This is sometimes
called a "Thermometer" code because all of the comparators with
their reference voltage less than the input signal will. be "on" while
those with their reference above the input will be "off".
The reference voltage generator consists of a string of precisely
matched resistors which generate the 256 voltages needed by the
comparators. The voltages at the ends of the resistor string set the
maximum and minimum conversion range and are typically OV
and -2V, respectively.
Included in the encoding function is Error Detection and Correction logic which ensures that a corrupted Thermometer code is
correctly encoded.
The output logic latches and holds the data constant between
samples. The output timing is designed for an easy interface to
external latches or memories using the same clock as the ADC.
POWER
The IDT75C58 requires two power supply voltages, Vee and
VEE. Typically, VEE = -5.0V and Vee = + 5.0V. Two separate
grounds are provided, AGNO and DGNO, the analog and digital
grounds. The difference between AGNO and DGNO must not exceed
± 0.1V and all power and ground pins must be connected.
REFERENCE
The IDT75C58 converts analog input signals that are within the
range of the reference (VRB s. VIN :;. VRT) into digital form. VRB (Reference Bottom) and VRT (Reference Top) are applied across the
reference resistor chain and both must be within the range of
+ 2.1V to -2.1V. In addition, the voltage applied across the reference resistor chain (VRT-VRB) must be between 1.8V and 2.2V, with
VRT more positive than VRB. Nominally,VRT = O.OVand VRB = -2.0V.
The IDT75C58 provides a midpoint tap, RM, which allows the
converter to be adjusted for optimum linearity or a non-lineartransfer function. Adjustment of RM is not necessary to meet the linearity
specification. Figure 6 shows a circuit which will provide approximately 1/2 LSB adjustment to the midpoint. The characteristic impedance of RM is about 170n and this node should be driven from
a low impedance source. Any noise introduced at this point will
couple directly into the resistor chain, seriously affecting
performance.
S11-35
Due to the unavoidable coupling with the clock and the input
signal, RT and RB should provide low AC impedance to ground.
For applications with a fixed reference, a bypass capacitor is
recommended.
CONTROL
Two function control pins, OE1 and OE2 control the outputs with
the function shown in Table 1.
IB Adj
An analog control pin, IB Adj, controls the bias current in the
comparators. Normally, this pin is connected to analog ground. To
reduce the quiescent current, a "power-down" mode, IB Adj may
be connected to VEE. For somewhat better analog performance
at higher input frequencies, IB Adj may be connected to a voltage
between AGNO and Vee.
CONVERT
The IDT75C58 begins a conversion with every rising edge of the
convert signal, CONV; The analog input signal is sampled on the
rising edge of CONV, while the outputs of the comparators are encoded on the falling edge. The next rising edge latches the encoder output which is presented on the output pins.
The input sample is taken within 15ns of the rising edge of
CONV. This is called tSTO or the Sampling Time Offset. This delay
varies by a few nanoseconds from part to part and as a function of
temperature, but the short term uncertainty or jitter is less than
60ps. If the maximum CONV pulse width HIGH time (tpWH) is exceeded, the accuracy of the input sample may be impaired. The
maximum CONV pulse width LOW time (tPWL) may be exceeded,
but the digital output data for the sample taken by the previous rising edge of CONV will be meaningless. It is recommended that
CONV be held LOW during longer periods of inactivity.
The digital output data is presented at to. the Digital Output Delay Time, after the next rising edge of CONV. Previous output data
is held for the tHO (Output Hold Time) after the rising edge of CONV
to allow for non-critical timing in the external circuitry. This means
that the data for sample N is acquired while the converter is taking
sample N+2.
iii
1DT75C58 FLASH A/D CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ANALOG INPUT
The IDT75C58 uses strobed, auto-zeroing, latching comparators. 80th analog input pins must be connected together as close
to the package as possible. The input signal must remain within the
range of Vee to VEE to prevent damage to the device.
STEP
RANGE
OUTPUT
OVFL
O.OOOOV
-0.0080V
-0.0160V
11111111
11111111
11111110
1
0
0
-0.9961V
-1.0039V
-1.0118V
-1.0160V
-1.0240V
-1.0320V
10000000
01111111
01111110
0
0
0
-1.9921V
-2.0000V
-2.040V
-2.048V
00000001
00000000
0
0
-2.0000V FS
7.8125mV/Step
-2.0480V FS
8.000mV/Step
256
255
254
O.OOOOV
-0.0078V
-0.0156V
129
128
127
001
000
:
:
If the analog input signal is within the reference voltage range,
the output will be a binary number between 0 and 255. An input signal below VRB will yield a full-scale (all outputs low) output while an
input above VRT will cause an OVFL output.
:
:
:
:
:
:
:
:
Figure 1. Output Coding
SAMPLE N
ANALOG INPUT
SAMPLE N+2
DIGITAL OUTPUT
DATA
VWVWDATA
N
~N+1
Figure 2 .. Timing Diagram
Vee
ori,OE2
8100
To Output Pin
40pF
1N3062
Figure 3. Output, Enable/Disable Timing
OEl
OE2
Do - 0 7
Figure 4. Output Load 1
OVFL
0
1
Valid
Valid
1
1
High Z
Valid
X
0
High Z
High Z
Table 1. Function Control
S11-36
1DT75C58 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
VALUE
UNIT
-0.5 to +7.0
V
POWER SUPPLY
Measured to DGND
Vcc
VEE
Measured to AGND
-0.5 to -7.0
V
AGND
Measured to DGND
-0.5 to +0.5
V
CONV, OE1, OE2
Measured to DGND
-0.5 to Vcc + 0.5
V
V1N ,VAT ,VAS
Measured to AGND
Vcc to VEE
V
VAT
Measured to VAS
-4.0 to +4.0
V
Measured to DGND
-0.5 to Vcc + 0.5
Externally forced
-3.0 to +6.0
Single output High to DGND
1.0
INPUT VOLTAGE
OUTPUT
Applied Voltage
(2)
Applied Current (2.
3. 4)
Short Circuit Duration
V
mA
S
TEMPERATURE
Operating,
Ambient
Military
-55 to +125
Commercial
o to
Military
-65 to +150
°C
Commercial
-55 to +125
°C
+70
°C
°C
Storage
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational section ofthis specification is not implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect reliability. Absolute Maximum Ratings are limiting values
applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.
iii
Sll-37
1DT75C58 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEMPERATURE RANGE
COMMERCIAL
MILITARY
TEST CONDITIONS
MIN.
NOM.
MAX.
MIN.
UNIT
NOM. MAX.
POWER SUPPLY
Vee
Positive Power Supply
4.75
5.0
5.25
4.5
5.0
5.5
VEE
Negative Power Supply
-4.75
-5.2
-5.5
-4.5
-5.2
-5.5
V
VAGND
Analog Ground Voltage (ref DGND )
-0.1
0
+0.1
-0.1
0
+0.1
V
Icc
Positive Supply Current
Vee = Max., Static(1)
70
-
60
80
mA
Negative Supply Current
VEE = Max., Static(1)
-
50
lEE
-15
-25
-
-15
-25
mA
V
V
DIGITAL INPUTS (CONV, NMINV, NLlNV)
VIL
Input Voltage, Logic LOW(4)
-0.5
-0.5
-
0.8
Input Voltage, Logic HIGH(4)
2.0
-
0.8
VIH
Vee+· 1
2.0
-
Vee +.1
V
IlL
Input Current. Logic LOW
Vee = Max., VIL = 0.5 V
-
-
±10
-
-
±10
jJA
IIH
Input Current, Logic HIGH
Vec = Max., VIH = 2.4 V
±10
±10
jJA
Vec = Max., VI = Vee
50
-
50
jJA
Digital Input Capacitance(4)
TA = +25°C, F = 1 MHz
-
-
-
Input Current, Max. Input Voltage
-
-
II
15
-
-
15
pF
-
4.0
-
4.0
mA
-
-2
mA
jJA
CI
DIGITAL OUTPUTS
10L
Output Current. Logic LOW
Vee = Min., \/0= 0.4 V
-
10H
Output Current, Logic HIGH
Vee = Min., Vo = 2.4 V
-
loz
Output High Z Current (4)
Vee = Max.
-
5
-
-
5
-
VOH
Output Voltage, Logic HIGH
Vee = Min., 10H= Max.
2.4
-
-
2.4
-
-
V
VOL
Output Voltage, Logic Low
Vee = Min., 10L = Max.
-
0.5
-
V
Output Short Circuit Current
Vee = Max,(2)
-
-50
-
-
0.5
los
-
-50
mA
V
-2
REFERENCE
VRT
Most Positive Reference Voltage(3)
-0.1
0
+0.1
-0.1
0
+0.1
VRS
Most Negative Reference Voltage (3)
-1.9
'-2.0
-2.1
-1.9
-2.0
-2.1
V
VRT - VRS
Reference Voltage Range
1.8
2.0
2.2
1.8
2.0
2.2
V
IREF
Reference Current (RT to Rs)
RREF
Reference Resistance (RT to Rs)
VRT , VRS = Nom.
VRT , VRS = Nom.
-
5
9
-
6
10
mA
250
400
-
220
330
-
Ohm
VRS
-
VRT
VRS
-
V RT
V
100
-
100
-
KOhm
ANALOG INPUT
"rN
Input Voltage Range
RIN
Equiv. Input Resistance (4)
VRT , VRS = Nom., VIN = VRS
CIN
Equiv. Input Capaeitanee(4)
VRT, VRS = Nom., VIN = \Bs
-
-
50
-
les
Input Const. Bias Current
VEE = Max.
-
-
10
-
TA
Ambient Temperature, Still Air
0
-
70
-
-
Te
Case Temperature, ..
-
-
-
-55
-
..
50
pF
10
jJA
-
°C
+125
°C
NOTES:
1. Worst case, all digital inputs and outputs LOW.
2. Output HIGH, one pin to ground, one second duration.
3. VRT must be more positive than VRS and the voltage reference must be within the specified range. Although the device is specified and tested with the
reference equal to OV and -2V, the part will operate with VRT up to + 2.1V. Likewise, the reference range may vary from 1.2V to 2.6V.
4. This parameter is guaranteed but not tested in production.
S11,...38
1DT75C58 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS FOR IDT75C58 x 20 (20 MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
SYMBOL
TEMPERATURE RANGE
COMMERCIAL
MILITARY
TEST CONDITIONS
PARAMETER
MIN.
TYP.
MAX.
MIN.
TYP.
UNIT
MAX.
Fs
Conversion Rate
20
30
-
20
30
-
tpWL
CONV, Pulse Width Low(4)
18
100,000
18
-
100,000
ns.
tPWH
CONV, Pulse Width HIGH (4)
22
-
20,000
22
-
20,000
ns
t STo
Sampling Time Offset
EAP
Aperture Error (5)
Vcc = Min .. VEE = Min.
Vcc= Min .• VEE· = Min.
MSPS
0
-
10
0
-
15
ns
-
-
60
-
-
60
ps
-
30
-
ns
5
-
35
-
-
ns
tD
Digital Output Delay
Vce = Min., VEE = Min., Load 1
-
tHO
Digital Output Hold Time
Vec = Min., VEE = Min., Load 1
5
tHZ
Output Disable Time from High (5)
Vee = Min., VEE = Min., Load 1
-
5
10
-
5
10
ns
tLZ
Output Disable Time from Low(5)
Vee = Min., VEE
Min., Load 1
-
5
10
5
10
ns
tZH
Output Enable Time to High(5)
Vee = Min., VEE = Min., Load 1
-
12
18
12
-
ns
tZL
Output Enable Time to Low (5)
Vec
-
12
18
-
12
18
ns
-
-
0.2
-
-
0.2
%FS
-
-
0.3
-
-
0.3
%FS
-
0.2
-
-
0.2
%FS
=
7'
Min .. VEE = Min., Load 1
I 1/2 LSB(2)
I 3/4 LSB(2)
ELI
Linearity Error, Integral
VRT ,VRB = Nom.
ELD
CS
Linearity Error, Differential
VRT ,VRB = Nom.
Code Size(1)
25
100
175
25
100
175
%Nom
EOT
Offset Error, Top
V1N = midpoint code 255
-
10
20
-
10
20
mV
EOB
Offset Error, Bottom
V1N = midpoint code 0
-
-10
-20
-
-10
-20
mV
Eoo
Offset Error, OVFU 3)
-6
0
6
-6
0
6
mV
Teo
Offset Error, Temperature Coefficient (5)
V1N = VRT
V1N = VRB
-
-
±20
-
-
±20
jJV/oC
BW
Bandwidth, Full Power Input
7
12
-
5
10
-
MHz
'lTR
Transient Response, Full Scale(5)
-
-
20
-
-
20
nS
1.248 MHz Input
2.438 MHz Input
54
53
56
56
53
52
55
55
-
-
dB
dB
1.248 MHz Input
2.438 MHz Input
45
44
47
47
-
44
43
46
46
-
dB
dB
36.5
39
-
36.5
39
-
.5
1
-
1
2
Signal to Noise Ratio
SNR
Peak Signal/RMS Noise
RMS Signal/RMS Noise
20 MSPS Conversion Rate,
10MHz Bandwidth
Noise Power Ratio
DC to 10 MHz White Noise
Bandwidth 4 Sigma Loading·
1.248 MHz Slot
20 MSPS Conversion Rate
DP
Differential Phase Error
Fs = 4 x NTSC
-
.5
1
DG
Differential Gain Error
Fs = 4 x NTSC
-
1
2
NPR
-
dB
Degree
%
NOTES:
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number deSignation.
3. A OmV offset means 1 LSB above the 255th code threshold.
4. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
5. This parameter is guaranteed but not tested in production.
S11-39
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT75C58 FLASH AID CONVERTER
AC ELECTRICAL CHARACTERISTICS FOR IDT75C58 x 30 (30 MHz Version)
Specifications over the DC Electrical range unless otherwise stated.
SYMBOL
TEMPERATURE RANGE
COMMERCIAL
MILITARY
TEST CONDITIONS
PARAMETER
MIN.
TYP.
MAX.
MIN.
TYP.
UNIT
MAX.
Fs
Conversion Rate
30
40
-
30
40
-
MSPS
tpwl
CONV, Pulse Width Low(4)
14
100,000
14
ns
CONV, Pulse Width HIGH (4)
14
20,000
14
-
100,000
t PWH
-
20,000
ns
tsTO
Sampling Time Offset
0
-
10
0
-
15
ns
-
60
-
-
60
ps
25
-
28
ns
5
-
-
5
-
-
5
-
-
5
-
-
5
-
-
5
-
ns
-
12
-
12
-
ns
12
-
-
12
-
ns
-
-
0.3
-
-
0.3
%FS
-
-
0.4
-
%FS
-
0.2
-
-
0.4
-
0.2
%FS
25
100
175
25
100
175
%Nom
10
45
20
mV
-30
-
45
-10
-30
-20
mV
Vce
= Min., VEE = Min.
Vee
= Min., VEE = Min.
= Min., VEE
= Min., VEE
= Min., VEE
= Min., VEE
=. Min., VEE
= Min., VEE
EAP
Aperture Error (5)
tD
Digital Output Delay
Vee
tHO
Digital Output Hold Time
Vee
tHZ
Output Disable TIme from High (5)
Vee
tLZ
Output Disable TIme from Low (5)
Vee
tZH
Output Enable Time to High(5)
Vee
tZl
Output Enable Time to Low(5)
Vee
= Min., Load 1
= Min., Load 1
= Min., Load 1
= Min., Load 1
= Min., Load 1
= Min., Load 1
Ell
Linearity Error, Integral
VRT , VRB
= Nom.
ELD
Linearity Error, Differential
VRT,VAS
= Nom.
CS
Code Size (I)
1 3/4 LSB(2)
11 LSB (2)
ns
ns
EOT
Offset Error, Top
V IN
EOB
Offset Error, Bottom
VIN = midpoint code 0
-
Eoo
Offset Error, OVFU 3 )
V IN = VRT
-6
0
6
-6
0
6
mV
Teo
Offset Error, Temperature Coefficient (5)
VIN
-
-
±20
-
-
±20
,;N/oC
= midpoint code 255
= VRB
BW
Bandwidth, Full Power Input
10
13
-
8
10
-
MHz
lTR
Transient Response, Full Scale(5)
-
-
20
-
-
20
nS
49
48
53
52
-
dB
dB
40
39
44
43
-
-
-
-
dB
Signal to Noise Ratio
SNR
30 MSPS Conversion Rate,
15 MHz Bandwidth
Peak Signal/RMS Noise
5 MHz Input
10 MHz Input
50
49
53
52
RMS Signal/RMS Noise
5 MHz Input
10 MHz Input
41
40
44
43
-
Noise Power Ratio
DC to 15 MHz White Noise
Bandwidth 4 Sigma Loading
5 MHz Slot
30 MSPS Conversion Rate
-
-
-
DP
Differential Phase Error
Fs
-
.5
1
-
.5
1
Degree
DG
Differential Gain Error
Fs
-
1
2
-
1
2
%
NPR
= 4x NTSC
= 4 x NTSC
dB
dB
NOTES:
. 1. Guarantees no missing codes ...
2. See the ordering information section regarding the part number designation.
3. A OmV offset means 1 LSB above the 255th code threshold.
4. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
5. This parameter is guaranteed but not tested in production.
S11-40
- - - - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . - - - - -...------
IDT75C58 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CALIBRATION
TYPICAL INTERFACE
The calibration of the IDT75C58 involves the setting of the 1st
and 255th comparator thresholds to the desired voltages. This is
done by varying the top and bottom voltages on the reference resistor chain, VRT and VRB, to compensate for any internal offsets.
Assuming a nominal OV to -2V reference range, apply -O.0039V (1/2
LSB from OV) to the analog input, continuously strobe the device
and adjust VRT until the OVFL output toggles between 0 and 1. To
adjust the first comparator, apply -1.996V (1/2 LSB from -2V) to
the analog input and adjust VRB until the converter output toggles
between the codes 0 and 1.
The offset errors are caused by the parasitic resistance between
the package pins and the actual resistor chain on-chip and are
shown as R1 and R2 in the Functional Block Diagram. The offset
errors, EOT and EOB, are specified in the AC Electrical Characteristics and indicate the degree of adjustment needed.
The previously described calibration schemerequires that both
ends of the reference resistor chain be adjustable, i.e. be driven by
operational amplifiers. A simpler method is to connect the top of
the resistor chain, RT, to analog ground or OV and to adjust this end
of the range with the input buffer offset control. The offset error at
the bottom of the resistor chain results in a slight gain error which
can be compensated for by varying the voltage applied to RB. This
is a preferred method for gain adjustment since it is not in the input
signal path. See Figure 5 for a detailed circuit diagram of this
method.
Figure 5 shows a typical application example for the IDT75C58.
The analog input amplifier is a bipolar wideband operational amplifier whose low impedance output directly drives the AID Converter. The input buffer amplifier is configured with a gain of minus
two which will convert a standard video input signal (1 V p-p) to the
recommended 2V converter input range. Both VIN pins are connected together as close to the package as possible and the input
buffer feedback loop is closed at this point. Bipolar inputs, as well
as the calibration of the reference top, are accomplished using the
offset control. A band-gap reference is used to provide a stable
voltage for both the offset and gain control. A variable capacitor in
the input buffer feedback loop allows optimization of either the step
or frequency response and may be replaced by a fixed value in the
final version of the printed circuit board.
To ensure operation to the rated specifications, proper decoupiing is needed. The bypass capacitors should be located close to
the chip with the shortest lead length possible. Massive ground
planes are recommended. If separate digital and ground planes
are used, they should be connected together at one point close to
the IDT75C58.
The bottom reference voltage, VRB, is supplied by an inverting
amp Iifier buffered by a PNP transistor. The transistor provides a low
impedance source and is necessary to provide the current flowing
through the resistor chain. The bottom reference voltage may be
adjusted to cancel the gain error introduced by the offset voltage,
EOB, as discussed in the calibration section.
[[I
S11-41
- - - - - - .•...._-------_ _ - - - - - - - - - - - ..
1DT75C58 FLASHAJD CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
+5V----------.------------------1~----------~~--------_,
~~A-N-A-LOJVGR~1~~~~--~~~~~--+-~~~
7
C13
C15~.
INPUT
~
R7
PARTS LIST
18
6
Vee
Vee
10
Vee
21
A12
"iN
"iN
AM
IBAdj
OVFL
24
12
U1
IDT75C58
RB
AOND
RT
17
CONV
5.11
D7 (MSB)
D6
D5
D4
D3
D2
D1
Do (LSB)
3·
13
14
15
16
CLOCK---------r----~--+-------_+--------~
-5.2V·----------~------~~-----._---------------------~__I
Figure 5. Application Example
IDT75C58
Figure 6, Mid-Point Adjust
S11-42
'A1
A2
A3
A4
R5
A6
A7
. A8
A9
A10
R11
A12
0.00
80.70
1KO
2KO
2200
2KO
1KO
2KO
2KO
10KO
20KO
270
C1-C4
C5-C15
C16
10~F
0.1~F
U1
U2
U3
U4
IDT75C58
HA-2539-5
uA741C
LM313
Q1
2N2907
L1, L2
Ferrite Bead
1-6pF Variable
IDT75C58 FLASH AID CONVERTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLOCK
ANALOG
INPUT
OV
CONV
0Ef
V 1N
OE2
RT
~·OV
IDT75C58
.
00-0,
RB
I
ClK
'---
CONV
OE2 f--5V
V1N
OE1
IDT75C58
RT
-2V
LATCH
IN8
OVFl
.
RB
00-0,
0 8 I - - - 0 8 (MSB)
IN7
.
~ I---
INO
0; r - - -
:
:
Do (lSB)
Figure 7. Simplified 9-Bit Application
ORDERING INFORMATION
lOT
xxxx
X
X
Device Type
Power
Speed
X
Package
x
Process/
Temperature
Range
Y:LANK
16
I ~O
~--------------~
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~120
130
' - - - - - - - - - - - - - - - - - 11 ~B
I sc
~------------------------------------~:
S11-43
75C58
Commercial (O°C to
+ 70°C)
Military (-55°C to + 125°C)
Compliant to Mll·STO-883, Class B
Plastic Dip
CERDIP (600 mil)
lCC (450 mil square)
Small Outline IC
MHz
MHz
Standard Power, 1/2 lSB Integral Linearity
Standard Power, 3/4 lSB Intregral Linearity
Standard Power, 1 lSB Integral Linearity
Flash AID Converter
iII
Integrated Device1echnoIogy. Inc.
PRELIMiNARY
lOT 75MB58
COMPLETE FLASH
ADC DIGITIZING
SYSTEM MODULE
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
•
•
•
The IDT75MB58 is a complete, 20MSPS (Mega Samples per
Second) Analog to Digital Converter subsystem. This module
combines all of the components needed to digitize video speed
analog signals (10MHz full-scale analog input bandwidth) into
8-bit digital words.
The IDT75MB58 module consists of a buffer amplifier, reference
voltage generator and a 20MSPS Flash ADC all housed in surfacemount packages mounted on an FR4 plastic substrate. Combining
all analog functions with the Flash ADC significantly reduces
board space requirements as well as design costs.
Complete Analog to Digital Converter System
No External Buffer Amplifier or StH Required
20MHz Sampling Rate
10MHz Full Power Analog Input Bandwidth
Pin Strappable Unipolar or Bipolar Input Ranges
External Offset and Gain Adjust
TTL Compatible, Three State Outputs
Overflow Output Flag
±5V Power Supply Operation
1000mW Maximum Power Dissipation
24-pin, 600 mil Wide Plastic Module Construction
FUNCTIONAL BLOCK DIAGRAM
BUFFER OUT
VIN
OFFSET ADJ
REF 2
--REF
-.......,./v'~
-_e__---
1DT75C58
----~___ I\I~~
Do - D 7 • OVFL
RT
>-4--~
RB
RB
OE1
OE2
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
©
IB ADJ
----,.,,/'--.--
1'-1~'.~-~~1--
GAIN ADJ
CONV
DSC-5008/-
1989 Integrated Device Technology. Inc.
511-44
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
V1N
BUFFER OUT
AGND
OFFSET ADJ
GAIN ADJ
Vee (+S.OV)
OE2
REF 2
OE1
REF 1
RB
OVFL
V EEA (-S.OV)
D7 (MSB)
D6
IB ADJ
DS
DGND
D4
CONV
D3
DO (LSB)
D2
D1
24-PIN DIP
(TOP VIEW)
DESCRIPTION
The IDT75MB58 is a complete, 20MSPS (Mega Samples per
Second) Analog to Digital Converter subsystem. This module
combines all of the components needed to digitize video speed
analog signals (10MHz full-scale analog input bandwidth) into
8-bit digital words.
The IDT75MB58 module consists of a buffer amplifier, reference
voltage generator and a 20MSPS Flash ADC all housed in surfacemount packages mounted on an FR4 plastic substrate. Combining
all analog functions with the Flash ADC significantly reduces
board space requirements as well as design costs.
GENERAL INFORMATION
The IDT75MB58 consists of three functional blocks: The input
buffer amplifier, the reference voltage generator and the Flash Analog to Digital Converter.
For more information about the Flash ADC and the input buffer
amplifier, refer to the IDT75C58 and Harris HA2539 data sheets.
THEORY OF OPERATION
The input buffer amplifier has been designed to provide flat
response up to "'10 MHz full scale frequency. The input impedance is set at '" 1K Ohms with an input range of OV to + 1V. The
output of the amplifier isavailable, through a 500.0 isolation resistor, as a test point or for application circuits.
An internal 1.22V bandgap voltage reference is available to
derive the -2.00V for the Flash ADC's reference bottom (Rs) input.
The actual voltage input to the Rs generator may be supplied
externally to REF2, pin 21, but is usually strapped to the internal
reference REF1, Pin 20.
The conversion range of the IDT75MB58 is set by the voltages
applied to the top and bottom of the reference resistor ladder of the
Flash ADC, RT and Rs. RT is internally connected to analog ground
setting the top of the conversion range. Rs is connected to the
reference generator as described above. The gain of the module is
adjusted by varying VRS.
A conversion is initiated on every rising edge of ClK. At this ti me
a sample is taken of the buffered analog input signal. The 255 .
comparator outputs are latched and converted to binary code on
the falling edge of·ClK. Output data is presented, after a delay
time, on the next rising edge of ClK. The easiest way to register
the output data is on the third rising edge of ClK. The chip specifications guarantee a hold time for easy interface to an external
register.
iII
POWER
The IDT75C58 requires two power supply voltages, Vee and
VEE. Typically, VEE = -5.0V and Vee ~. +5.0V. Two separate
ground pins are provided, AGND and DGND, however, they are internally connected. It is recommended that a one ground system
be maintained and both AGND and DGND be connected together
under the device. If a two ground system is used, the analog
ground should be connected to AGND and the digital ground to
DGND.
REFERENCE
The IDT75MB58 contains all circuitry needed to generate the
negative reference voltage for the Flash ADC. A bandgap reference voltage, 1.22V, is available on REF1, pin 20. This voltage
is usually strapped to the reference voltage generator input REF2,
pin 21. The actual voltage applied to the Flash ADC is available on
RB, pin 19, isolated by a 500.0 resistance and is typically -2.00V.
S11-45
COMMERCIAL TEMPERATURE RANGE
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
ANALOG INPUT
but the digital output data for the sample taken by the previous
riSing edge of CONV will be meaningless. It is recommended that
CONV be held LOW during longer periods of inactivity.
The digital output data is presented at tD, the Digital Output
Delay Time, atter the next rising edge of CONV. Previous output
data is held for the tHO (Output Hold Time) after the rising edge of
CONV to allow for non-critical timing in the external circuitry. This
means that the data for sample N is acquired while the converter is
taking sample N + 2.
The analog input of the ID175MB58 drives a buffer amplifier,
configured with a gain of -2, which drives the Flash ADC. Typically, the analog input can accept either a unipolar 0 to + 1V or
bipolar ±O.5V input range. Other input ranges may be accommodated by attenuating the input Signal as shown below. The equations to determine R1 and R2 are:
INPUT~R1
VOLTAGE
(VR)
,
1
CALIBRATION
VIN
R2
Input Attenuator
R2 =
R1
ZIN -
1000 R2
R2
+
1000
Where VR is the desired input voltage range, ZIN is the desired
input impedance and 1000±1% is the constant input resistance of
the module.
Bipolar operation is obtained by leaving OFFSET ADJ, pin 23
open. Conversely, unipolar operation is possible with pin 23 connected to AGND. The OFFSETADJ pin is also used to set the accuracy of the system. Please refer to the calibration section for more
details.
The actual voltage applied to the Flash ADC is made available at '
BUFFER OUT, pin 24, through a 500n isolation resistor.
The ID175MB58 provides controls for adjusting the gain and
offset of the system. OFFSET ADJ, pin 23, varies the DC level of the
input buffer amplifier. When this pin is left open, a -O.5V offset is
introduced into the buffer amplifier allowing a ±O.5V bipolar input
signal to correctly drive the Flash ADC (translating the signal to a
OV to -2V range). When the OFFSET ADJ pin is connected to
AGND, no offset is introduced, accomodating a OV to 1V unipolar
input signal. The OFFSET ADJ pin can also be used to adjust the
DC accuracy of the Flash Modules. Two methods for trimming
unipolar offset are shown in Figure 1. The simpler method, shown
in Fig. 1a), depends on the absolute resistor stability over temperature. A more elegant approach, shown in b) reduces self-heating and dissipates less power.
Offset trim for Bipolar input signals is simpler and is shown in
Fig. 2. The range of adjustment is ± 75mV or approximately 19L5B.
GAIN ADJ, pin 22, varies the voltage applied to the reference
resistor ladder of the Flash ADC, effectively varying the gain of the
system. Note that larger gain decreases may be obtained by padding the analog input. A typical circuit for gain adjustment is shown
in Figure 3 while a more stable circuit is shown in Figure 4.
rb-G
CONTROL
L-GJ
Two function control pins, OE1 and OE2 control the outputs with
the function shown in Table 1. These inputs determine the HI-Z
status of the, data outputs and OVFL.
OFFSET ADJ
RB
A)
IB ADJ
An analog controllB Adj, pin 17, controls the bias current in the
comparators. Normally, this pin is connected to analog ground. To
reduce the quiescent current, a "power-down" mode, IB ADJ may
--- --- - ---- be connected to VEE. For somewhat better analog performance at
higher input frequencies, IB ADJ may be connected to a voltage between AGND and Vee.
REF 1
5K
OFFSET ADJ
CONVERT
The ID175MB58 begins a conversion with every rising edge of
the convert Signal, CONV. The analog input signal is sampled on
the rising edge of CONV, while the outputs of the comparators
are encoded on the falling edge. The next riSing edge latches the
encoder output which is presented on the output pins.
The input sample is taken within 15ns of the rising' edge of
CONV. This is called tSTO or the Sampling Time Offset. This delay
varies by a few nanoseconds from part to part and as a function of
temperature, but the short term uncertainty or jitter is less than
GOps. If the maximum CONV pulse width HIGH time (tpWH) is exceeded, the accuracy of the input sample may be impaired. The
maximum CONV pulse width LOW time (tpWL) may be exceeded,
RB
B)
Figure 1. Unipolar Offset Adjust Circuit
S11-46
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
COMMERCIAL TEMPERATURE RANGE
REF 1
REF 1
2K
/'·...-----iB
. . . . . ----0
5K
OFFSET ADJ
GAiN ADJ
1K
Figure 3. Gain Adjust Circuit
Figure 2. Bipolar Offset Adjust Circuit
1.2K
REF 1
2K
GAIN ADJ
8K
Figure 4. Gain Adjust Circuit (±10%)
S11-47
-----_.
__
..__ ...
_-----
iii
COMMERCIAL TEMPERATURE RANGE
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
OUTPUT
OVFL
O.OOOOV
0.0039V
0.0078V
11111111
11111111
11111110
1
0
0
-0.0039V
O.OOOOV
0.0039V
0.4961V
0.5000V
0.5039V
10000000
01111111
01111110
0
0
0
0.4961V
0.5000V
0.9961V
1.0000V
00000001
00000000
0
0
RANGE
STEP
BIPOLAR
±0.5VFS
3.90mV/Step
UNIPOLAR
OTO +1V FS
3.90mV/Step
256
255
254
-0.5000V
-0.4961V
-0.4922V
129
128
127
001
000
CODE
CENTERS
Figure 5. Output Coding
SAMPLE N
SAMPLE N+2
DIGITAL OUTPUT
DATA
VWVI/VDATA
N
~N+1
Figure 6. Timing Diagram
Vee
0ET.OE2
t HZ ' tu
8100
_________________ _
To Output Pin O---.---toIII---+
40pF
1N3062
Figure 7. Output, Enable/Disable Timing
Figure 8. Output Load 1
OE1
OE2
0
1
Valid
Valid
1
1
High Z
Valid
X
0
HighZ
High Z
Do - D7
OVFL
Table 1. Function Control
Sll-48
COMMERCIAL TEMPERATURE RANGE
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
RATING
VALUE
UNIT
POWER SUPPLY
Vee
Measured to AGND
-0.5 to + 7.0
V
VEE
Measured to AGND
+0.5 to -7.0
V
CONV, OE1, OE2
Measured to DGND
-0.5 to Vee + 0.5
V
VIN ,REF2
Measured to AGND
Vee to VEE
V
INPUT VOLTAGE
OUTPUT
Applied Voltage
Measured to DGND
-0.5 to Vee +0.5
Externally forced
·-3.0 to + 6.0
Single output High to DGND
1.0
Operating, Ambient
Commercial
o to
+ 70
°C
Storage
Commercial
-55 to +125
°C
(2)
Applied Current (2.
3. 4)
Short Circuit Duration
V
mA
S
TEMPERATURE
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect reliability. Absolute Maximum Ratings are limiting values
applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.
iii
Sll-49
-.---...- - - ...._._------_._..
..
_ ...-_ __.-----_._.__.-._------_ _ - - _ . - - - - - - - - - - - - - - ...
...
,
.,
COMMERCIAL TEMPERATURE RANGE
IDT75MB5B COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEMPERATURE RANGE
COMMERCIAL
TEST CONDITIONS
MIN.
UNIT
NOM.
MAX.
POWER SUPPLY
Vee
Positive Power Supply
4.75
5.0
5.25
VEE.
Negative Power Supply
-4.75
-5.0
-5.5
V
Icc
Positive Supply Current
Vee = Max., Static (1)
-
-
110
mA
lEE
Negative Supply Current
VEE = Max., Static(1)
-
-
-70
mA
0.8
V
V
DIGITAL INPUTS (CONV, OE1, OE2)
VIL
Input Voltage, Logic LOW(3)
-0.5
VIH
Input Voltage, Logic HIGH (3)
2.0
-
Vee+.1
V
IlL
Input Current, Logic LOW
Vee = Max., VIL = 0.5 V
-
-
±10
JJA
-
-
±10
JJA
-
50
JJA
15
pF
IIH
Input Current, Logic HIGH
Vee = Max., VIH = 2.4 V
II
Input Current, Max. Input Voltage
Vee = Max., VI = Vee
CI
Digital Input Capacitanee(3)
TA = +25°C, F = 1 MHz
DIGITAL OUTPUTS
IOL
Output Current, Logic LOW
Vee = Min., Vo = 0.4 V
4.0
mA
Output Current. Logic HIGH
Vee = Min., Vo = 2.4 V
-
-
IOH
-
-2
mA
loz
Output High Z Current (3)
Vee = Max.
-
5
-
JJA
VOH
Output Voltage, Logic HIGH
Vee = Min., 10H= Max.
2.4
-
V
VOL
Output Voltage, Logic Low
Vee = Mfn., I OL = Max.
-
-
0.5
V
REFERENCE
VREF1
Internal Reference Voltage
1.22
1.235
1.25
V
IREF1
Reference Source Current
-
-
2.0
mA
VRB
RB Voltage Range
-1.8
-2.0
-2.2
V
+0.5
V
985
1000
1015
KOhm
5
pF
0
-
70
°C
ANALOG INPUT
VIN
Input Voltage Range
RIN
Input Resistance (3)
CIN
Input Capacitance (3)
TA
Ambient Temperature, Still Air
OFFSET ADJ Pin Open
-0.5
VRT, VRB = Nom., VIN = VRB
NOTES:
1. Worst case, all digital inputs and outputs LOW.
2. Output HIGH, one pin to ground, one second duration.
3. This parameter is guaranteed but not tested in production.
Sll-50
------------------------------------------------------------------------
COMMERCIAL TEMPERATURE RANGE
1DT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
AC ELECTRICAL CHARACTERISTICS
Specifications over the DC Electrical range unless otherwise stated.
SYMBOL
TEMPERATURE RANGE
COMMERCIAL
TEST CONDITIONS
PARAMETER
MIN.
TYP.
UNIT
MAX.
Fs
Conversion Rate
20
30
-
MSPS
tpWL
CONV, Pulse Width LoW(4)
18
-
100,000
ns
tpWH
CONV, Pulse Width HIGH (4)
22
-
20,000
ns
t sTo
Sampling TIme Offset
-5
-
15
ns
Vee = Min., VEE = Min.
Vee = Min., VEE = Min.
EAP
Aperture Error(5)
-
-
60
ps
tD
Digital Output Delay
Vee = Min., VEE = Min., Load 1
-
30
ns
tHO
Digital Output Hold Time
Vee = Min., VEE = Min., Load 1
5
-
-
ns
tHZ
Output Disable TIme from High (5)
Vee = Min., VEE = Min., Load 1
-
5
10
tLZ
Output Disable Time from Low (5)
Vee = Min., VEE = Min., Load 1
-
5
10
tZH
Output Enable Time to High (5)
Vee = Min., VEE = Min., Load 1
12
18
ns
tZL
Output Enable Time to Low
Vee = Min., VEE = Min., Load 1
-
12
18
ns
ELI
Linearity Error, Integral
-
0.2
-
ELD
Linearity Error, Differential
-
0.2
CS
Code Size (1)
25
100
175
%Nom
EOSB
Offset Error, Bipolar, Unadjusted
-75
+75
mV
Eosu
Offset Error. Unipolar, Unadjusted
-60
-
+60
mV
Eoo
Offset Error, OVFU 3 )
-6
0
6
mV
BW
Bandwidth, Full Power Input
10
12
-
MHz
-8
-
+8
%FS
44
43
47
47
-
dB
dB
36.5
39
-
dB
-
.5
1
Degree
1
2
%
EG
(5)
NPR
"'N
= VRT
Gain Error. Unadjusted
Signal to Noise Ratio
SNR
VRB = Nom.
VRB = Nom.
RMS SignallRMS Noise
Noise Power Ratio
ns
%FS
%FS
20 MSPS Conversion Rate.
10 MHz Bandwidth
2.5 MHz Input
5 MHz Input
DC to 10 MHz White Noise
Bandwidth 4 Sigma Loading
1.248 MHz Slot
20 MSPS Conversion Rate
DP
Differential Phase Error
Fs = 4x NTSC
DG
Differential Gain Error
Fs = 4 x NTSC
NOTES:
1. Guarantees no missing codes.
2. See the ordering information section regarding the part number designation.
3. A OmV offset means 1 LSB above the 255th code threshold.
4. No damage to the part will occur if the Max. times are exceeded. See the Convert section for more information about the Conv Max. time limitations.
5. This parameter is guaranteed but not tested in production.
S11-51
------._ ... _-----_.. --------------------
iii
COMMERCIAL TEMPERATURE RANGE
IDT75MB58 COMPLETE FLASH ADC DIGITIZING SYSTEM MODULE
ORDERING INFORMATION
lOT
XXX)(
X
Device Type
Power
X
Speed
X
Package
x
Process/
Temperature
Range
YBlank
~--------------~ P
~----------------------~ 20
~------------------------------~
S
~------------------------------------~75MB58
Sll-52
Commercial (O°C to
Plastic
MHz
Standard Power
Flash AID Converter
+ 70°C)
Eel Products
_ _--_ _-_.__. _ . _ - - - - - _ . - ...
....
INTRODUCTION TO THE ECl PRODUCTS GROUP
The ECL Product Group is one of the newest product groups to
be created at Integrated Device Technology, Inc. The charter ofthe
group is to develop a leadership SiCMOS technology, create ECL-'
compatible products which drive and showcase that technology,
and understand the needs of ECL users with the aim of creating
products which more completely provide systems solutions.
The products offered by the ECL Products Group provide the
designer of high-speed emitter-coupled logic (ECL) systems with a
lower-power alternative to older bipolar ECL technologies. lOT
SiCMOS ECL memory products allow the designer to achieve
performance levels close to bipolar equivalents, yet with less engineering time and resources devoted to heat diSSipation and
thermal design. These products are ideal for cache, contrOl-store,
or, main memory applications in mini-supercomputer and highend workstation, or pattern generation and data capture in test
equipment.
This revolution in performance-density is achieved by lOT
through the development of a technology which combines highspeed CMOS with limited use of bipolar structures. Called
SiCEMOS ™ , the technology provides greater performance in
memory components by speeding up word-line drivers, sense
amplifiers, and input-output buffers. Bipolar structures on-Chip
also allow the option of ECL-compatible interfaces.
To build components with ECL interfaces in the past required
100% bipolar circuit deSigns. Full bipolar designs were limited in
density, however, by the high power dissipation of the chip: the
level of integration available to the designer of ECL systems has
thus been necessarily low when compared to CMOS. But in the
past, designers looking for performance sacrificed density and
solved power dissipation engineering problems in order to use
bipolar ECL components. Today, BiCMOS provides the highdensity and low cost of CMOS to ECL designers.
Integrated Device Technology has begun its family of SiCMOS
ECl components with the most density-intensive elements: memory. Because memories benefit in speed from bipolar word-line
drivers as mentioned above, larger (longer word-line) memories
benefit most from SiCMOS. Thus, lOT has begun building BiCMOS ECl SRAMs at the 64K-bit density, and will offer products
with ever greater levels of integration. These density enhancements will include 256K-bit memories and beyond, as well as
BiCEMOS is a trademark of Integrated Device Technology. Inc.
memories including on-chip logic to improve their use in computer
architectures.
The speed of memories, measured as access time, is also improved with the development of BiCMOS. Bipolar structures speed
up internal elements of already fast CMOS memories. Because it is
based on, and integrated Into, standard lOT CMOS, BiCMOS will
directly receive the benefits of enhancements made in Mure
CMOS technology generations. Speed improvements will be
achieved for both BiCMOS TTL and SiCMOS ECL memories, but
the ECL output buffer is a clear speed leader over TTL, implying
that ECL memories will in general out-perform TTL. In a system,
ECL logic elements out-perform TTL by as much as a factor of
three; lOT feels that ECL will win renewed interest as an interconnect standard for high-performance systems now that BiCMOS
allows CMOS densities at ECL speeds.
Military applications will also benefit from BiCMOS ECLcomponents. The low-power dissipation of SiCMOS allows ECL SRAMs
to be offered as fuly MIL-STD-883 compliant over the full -55°C to
+ 125°C temperature range. The high density and low power will
be ideal for high data rate applications such as RADAR, satellite
communication, and graphics.
The lower power dissipation of SiCMOS ECL, components
makes the job of designing with ECL much easier than with bipolar
ECL. System reliability goals are much easier to achieve because
these components create less heat in a system. Heat dissipation
techniques needed for system cooling benefit from a better starting
point, reducing the amount of time and resources needed to prove
a design. Power supply requirements are of course reduced. New
packaging options are realized, such as plastic DIP and surfacemount packages.
Integrated Device Technology believes that BiCMOS will be a
major technology for the coming years, and is dedicated to be the
leader. To do this we have created memory products to drive the
technology down the learning curve to provide our customers
cost-effective high-performance. We offer standard and leadership
ECL products implemented in high-performance SiCMOS. We
intend to work closely with our customers to create new standard
products which bring more of the advantages of BiCMOS speed,
integration, and lower power to ECL systems.
TABLE OF CONTENTS
PAGE
CONTENTS
ECl Products
lOT 10490
lOT 10490M
lOT 100490
lOT 10494
lOT 10494M
lOT 100494
lOT 10496ll
lOT 100496ll
lOT 10496Rl
lOT 100496Rl
lOT 10497
lOT 100497
lOT 10498
lOT 100498
lOT 10504
lOT 100504 .
lOT 10506ll
lOT 100506ll
lOT 10506Rl
lOT 100506Rl
lOT 10507
lOT 100507
lOT 10508
lOT 100508
High-Speed BiCMOS ECl Static RAM 64K (64K x 1-Bit) . . .. . . ... .... . .. .. ... . .. . . . . ....
High-Speed BiCMOS ECl Static RAM 64K (64K x 1-Bit) Mll-STO-883 Compliant. ..........
64K (64K x 1) BiCMOS SRAM with ECl I/O ..........................................
High-Speed BiCMOS ECl Static RAM (64K (16K x 4-Bit) ...............................
High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) Mll-STO-883 Compliant .;.........
. High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) . . . . . . . . . . . . . . . . .. .. . . .. . . . . .. ..
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) STRAM ...............
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) ......................
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) STRAM ...............
High-Speed BiCMOS ECl Self-Timed Static RAM 64K (16K x 4-Bit) STRAM ...............
High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) with Synchronous Write. . . . . . . . . . ..
High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) with Synchronous Write.. ..........
High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) with Conditional Write .. . . .. . . . . . ..
High-Speed BiCMOS ECl Static RAM 64K (16K x 4-Bit) with Conditional Write . . . . . . . . . . . ..
High-Speed BiCMOS ECl Static RAM (256K (64K x 4-Bit) ..............................
High-Speed BiCMOS ECl Static RAM (256K (64K x 4-Bit) ..............................
High-Speed BiCMOS ECl Self-Timed Static RAM 256K (64K x 4-Bit) ...•.................
High-Speed BiCMOS ECl Self~Timed Static RAM 256K (64K x 4-Bit) .....................
High-Speed BiCMOS ECl Self-Timed Static RAM 256K (16K x 4-Bit) .....................
High-Speed BiCMOS ECl Self-Timed Static RAM 256K (16K x 4-Bit) .....................
High-Speed BiCMOS ECl Static RAM 256K (16K x 4-Bit) with Synchronous Write. ..........
High-Speed BiCMOS ECl Static RAM 256K (16K x 4-Bit) with Synchronous Write ...... , . . ..
High-Speed BiCMOS ECl Static RAM 256K (64K x 4-Bit) with Conditional Write. . . . . . . . . . ..
High-Speed BiCMOS ECl Static RAM 256K (64K x 4-Bit) with Conditional Write............
S12-1
S12-6
S12-11
S12-16
S12-21
S12-26
S12-31
S12-38
S12-45
S12-51
S12-57
S12-57
S12-63
S12-63
S12-70
S12-70
S12-72
S12-72
S12-74
S12-74
S12-76
S12-76
S12-78
S12-78
PRELIMINARY
HIGH-SPEED BiCMOS
ECl STATIC RAM
64K (64K x 1-BIT)
IntesJated Device1echnobgy. Inc.
lOT 10490
FEATURES:
DESCRIPTION:
• 65,536-words x 1-bit organization
The IDT10490 is a 10K compatible 65,536-bit high-speed
BiCEMOS ™ ECl static RAM organized as 64K x 1.
The IDT10490 is available with address access times as fast
as 8ns with a typical power consumption of only 420mW. This
product offers the advantages of low-power operation, without sacrificing speed, by integrating a dense high~speed CMOS static
RAM with internal level conversion. This allows the designer to
reduce package count in an ECl system without increasing either
power dissipation or access time.
Designed for very high-speed appl ications, the I DT1 0490 is fully
compatible with standard ECl 10K logic levels and offers extremely fast access times. The address access time of 8ns and
write pulse width of 6ns assure that operations of this BiCEMOS
part will be as fast as those available with less dense parts requiring
external address decoding.
The IDT10490 is fabricated using IDT's high-performance,
high-reliability BiCEMOS technology. Operating power dissipation is extremely low compared with most ECl-compatible bipolar
devices, lowering power supply and cooling requirements.
• low power dissipation: 420mW (typ.)
• Fully compatible with 10K logic level
• Address access time: 8/10/12/15/20ns (max.)
• Write pulse width: 6ns (min.)
• Separate data input and output
• JEDEC standard high-density 22-pin CERDIP
PIN CONFIGURATIONS
DATAoUT
LOGIC SYMBOL
Vee
DATA IN
CS
Ao
Al
A2
A3
A4
As
A6
A7
A8
VEE
wr=.
A1S
A14
A13
A12
All
A10
A9
DIP
TOP VIEW
DATA IN
Ao
Al
A2
A3
A4
As
A6
A7
As
A9
AlO
All
A12
A 13
A14
A 1S
FUNCTIONAL BLOCK DIAGRAM
Ao
DECODER
DATAoUT
A 1s
~
DATA IN
65,536-BIT
MEMORY ARRAY
. ....
I/O CONTROL
DATA OUT
ill
cs
M
cs
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology, Inc.
DSC-8001/1
S12-1
--------_ ..
-------------------.._ - - - - -
-------------------------------------------
1DT10490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64K xl-BIT)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
CAPACITANCE
(t)
RATING
Terminal Voltage
with Respect to
GND
VALUE
UNIT
+0.5 to -7.0
V
TA
Operating
Temperature
Oto +75
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-65 to
+ 150
°C
PT
Power Dissipation
(TA= +25°C, f = 1.0MHz)
PARAMETER(t)
SYMBOL
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
-
UNIT
6
pF
6
pF
TRUTH TABLE (t)
1.0
W
-50
DC Output Current (Output High)
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CS
WE
H
L
L
DATA OUT
FUNCTION
X
L
Deselected
H
RAM Data
Read
L
L
Write
NOTE:
1. H = High, L = Low, X = Don't Care
DC ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RL = SOCHa -2.0V; T A = 0 to + 75°C for DIP, air flow exceeding 2m/sec)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP.(t)
MIN. (B)
MAX. (A)
UNIT
TA
-855
-840
-810
-720
mV
O°C
25°C
75°C
VOH
Output HIGH Voltage
\IN = VIHA or \lLB
-1000
-960
-900
VOL
Output LOW Voltage
\IN = VIHA or \lLB
-1870
-1850
-1830
-
-1665
-1650
-1625
mV
O°C
25°C
75°C
VOHC
Output Threshold HIGH Voltage
\IN = VIHBor \lLA
-1020
-980
-920
-
-
mV
O°C
25°C
75°C
VOLC
Output Threshold LOW Voltage
\IN = VIHB or VILA
-
-
-1645
-1630
-1605
mV
O°C
25°C
75°C
\lH
Input HIGH Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1145
-1105
::1045
-
-840
-810
-720
mV
O°C
25°C
75°C
VIL
Input LOW Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1870
-1850
-1830
-
-1490
-1475
-1450
mV
OOC
25°C
75°C
IIH
Input HIGH Current
VIN = VIHA
,
IlL
Input LOW Current
VIN = VILB
Supply Current
All inputs and outputs open
CS
-
Others
-
220
110
CS
0.5
Others
-50
-
90
-140
-80
-
lEE
NOTE.
1. Typical parameters are specified at VEE = -S.2V, TA = + 2SoC and maximum loading.
LOAD CONDITION
-
170
~A
~A
mA
INPUT PULSE
Test Circuit
Vcc·(GND)
-0.9V
son
-2.0V
Ji
-l·7V-n
DATA OUT
I
80%
tR
30PF *
tF
tR =tF = 2.0ns typo
"Includes probe and jig capacitance.
S12-2
---20%
1OT10490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K x 1-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(VEE = -5.2V ±5%, TA = 0 to
TEST'
CONDITION
PARAMETER
+ 75°C, air flow exceeding 2m/sec)
IDT10490S8 IDT10490S10
MAX.
MIN. MAX. MIN.
IDT10490S12
MIN.
MAX.
IDT10490S15
MIN.
MAX.
IDT10490S20
UNIT
MIN.
MAX.
READ CYCLE
t Acs
Chip Select Access Time
-
t ACS
Chip Select Recovery Time
tAA
Address Access Time
-
tOH
Data Hold from Address Change
-
-
3.5
",:::;;
.':"':'.:::'
·::::::~t::::::'
7-:::)::::: ',' 8
'::::~::::::"
-
10
-
-
3.5
5
5
5
-
10
5
-
10
12
-
-
3.5
10
ns
15
-
20
ns
-
3.5
-
ns
10
ns
TIMING WAVEFORM OF READ CYCLE NO.1
~----f%
~
-i.~1
~ '=
t ACS _ _ _
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
t_OH~~50-%
- - - - - -_ _
DATA OUT
__
RISE/FALL TIME
SYMBOL
PARAMETER
TEST CONDITION
tA
Output Rise Time
-
tF
Output Fall Time
-
-
512-3
IOT10490
TYP.
MIN.
I
I
2
2
MAX.
I
1
UNIT
-
ns
-
ns
IDT10490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64K x 1-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VEE
= -S.2V ±S%. TA = 0 to
+ 7SoC. air flow exceeding 2m/sec)
TEST CONDITION IDT10490S8 IDT10490S10
MIN. MAX. MIN.
MAX.
PARAMETER
SYMBOL
IDT10490S12
MIN.
MAX.
1DT10490S15
MIN.
MAX.
1DT10490S20 UNIT
MIN.
MAX.
WRITE CYCLE
8
10
10
15
ns
o
o
2
3
ns
S
S
S
7
ns
2
2
3
4
ns
o
o
2
3
ns
Address Hold Time
2
2
3
4
ns
twscS
Chip Select Set-up Time
o
o
2
3
ns
t WHCS
Chip Select Hold Time
2
2
3
4
tws
Write Disable Time
5
S
10
10
ns
Write Recovery Time
12
14
18
23
ns
t WSA = minimum
Write Pulse Width
t WSD
6
Data Set-up Time
Data Set-up to M
High
Data Hold Time
t WSA
Address Set-up Time
tw = minimum
:;.;:.:.:..... :.::
NOTES:
1. t WSD is specified with
ns
res~t to the falling edge of WE for compatibility with bipolar part specifications but this device actually only requires t WSD2 with
respect to rising edge of WE.
2. tWR = tWHA + t AA and thus can include a full access time if addresses change while Chip Select Is still low.
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATAoUT
S12-4
IDT10490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K x 1-BI1)
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
xxxxx
Device Type
999
Speed
A
A
Package
Process/
Temperature
RT__-1
Blank
'-----------1 D
10
8
12
15
20
'------------------; S
'-----------------------1
S12-5
10490
Commercial (O°C to +75°C)
CERDIP
} Speed in Nanoseconds
Standard Power
64K (64K x 1-Bit) BiCMOS ECl Static RAM
HIGH-SPEED SiCMOS
ECl STATIC RAM
64K (64K x 1-SIT)
Mll-STD-883 COMPLIANT
t;)
Integrated Device1echno1ogy.1nc.
FEATURES:
•
•
•
•
•
•
•
•
•
DESCRIPTION:
65,536-words x 1-bit organization
low power dissipation: 420mW (typ.)
Fully compatible with 10K logic level
Address access time: 15/20ns (max.)
Write pulse width: 10ns (min.)
Separate data input and output
JEDEC standard high-density 22-pin CERDIP
Mil-STO-883 Compliant
Operation over the full temperature range -55°C to
The IDT10490 is a 10K compatible 65,536-bit high-speed
BiCEMOS'" ECl static RAM organized as 64K x 1. It is manufactured, assembled, and tested by Integrated Device Technology,
Inc. in full compliance with Mll-STD-883, and operates over the full
temperature range of -55°C to + 125°C.
The IDT10490 is available with address access times as fast
as 15ns with a typical power consumption of only 420mW. This
product offers the advantages of low-power operation, without sacrificing::speed, by integrating a dense high-speed CMOS static
RAM .. vmtl internal level conversion. This allows the designer to
achi~k~Jthigh-performance ECl system with dramatically lower
+ 125°C
",:P9w.eYdti@P?tionthan bipolar equivalents, reducing power supply
/Ura:h9:ppolingjiequirements.
. ::::... "<::::}::};:>e$igqed for very high-speed applications, the IDT1 0490 is fully
'H:::::\\"cditjp.ifible with standard ECl 10K logic levels and offers ex"'\?:::"":HJr~m~ry fast access times. Applications include cache, control
'\//)"'smre, buffer, and main memory uses. The high density allows
"'\\;fe"ilVer address-decode delays, providing better system speed over
.-:".' smaller ECl memories.
LQdl~(§Vivl~:6:b::?'
PIN CONFIGURATIONS
voc· i:i"':';", ;" i . -'.,-:.,~..,
±*,------,
DATAOUT
DATA IN
Ao
A,
A2
A3
A4
As
A6
PRELIMINARY
lOT 10490M
cs
A2
A3
A4
A'4
As
A
'3
A6
A'2
Ao
\f,h '.,.'
WE
A,S
A7
1.
FUNCTIONAL BLbcK DIAGRAM
A7
A8
DECODER
65.536-BIT
MEMORY ARRAY
DATAoUT
Ag
A8
A,a
VEE
A'l
DIP
TOP VIEW
A'2
DATAIN - - - t - - - - - - i
DATA OUT
I/O CONTROL
A '3
A'4
A ,S
CS-4-----------------~
BiCEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
©
JANUARY 1989
1989 Integrated Device Technology, Inc.
D5C-8011/-
S12-6
1DT10490 HIGH SPEED BiCMOS
ECL STATIC RAM 64K (64K x 1-BIT)
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
(1)
VALUE
RATING
SYMBOL
MILITARY TEMPERATURE RANGE
UNIT
VTERM
Terminal Voltage
with Respect to
GND
+0.5 to -7.0
TA
Operating
Temperature
-55 to +125
°C
TBiAs
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to + 150
°C
PT
Power Dissipation
1.0
W
V
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
SYMBOL
C IN
Input Capacitance
COUT
Output Capacitance
CONDITIONS
TYP.
UNIT
6
pF
6
pF
-
TRUTH TABLE (1)
-50
DC Output Current (Output High)
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CS
WE
DATA OUT
FUNCTION
H
X
L
Deselected
L
H
RAM Data
Read
L
L
L
Write
NOTE:
1. H = High, L = Low, X = Don't Care
DC ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RL = 500 to -2.0V, TA = -55 to + 125°C for DIP, air flow exceeding 2m/sec)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. (B)
Typ.(l)
MAX. (A)
UNIT
TA
-855
-860
-810
-600
mV
-55°C
25°C
+125°C
VOH
Output HIGH Voltage
'-"N = VIHA or'-"LB
-1070
-960
-860
VOL
Output LOW Voltage
'-"N = VIHA or '-"LB
-1900
-1850
-1800
-
-1690
-1650
-1570
mV
-55°C
25°C
+125°C
VOHC
Output Threshold HIGH Voltage
'-"N = VIHB or '-"LA
-1090
-980
-830
-
-
mV
-55°C
25°C
+125°C
VOLC
Output Threshold LOW Voltage
'-"N = VIHB or '-"LA
-
-
-1670
-1630
-1550
mV
-55°C
25°C
+125°C
Input HIGH Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1213
-1105
-1005
-
-860
-810
-600
mV
-55°C
25°C
+125°C
VIL
Input LOW Voltage
Guaranteed Input Voltage'
High/Low for All Inputs
-1900
-1850
-1800
-
-1515
-1475
-1395
mV
-55°C
25°C
+ 125°C
Input HIGH Current
VIN = VIHA
-
-
220
IIH
-
110
CS
0.5
170
Others
-50
-
-140
-80
'-"H
IlL
Input LOW Current
lEE
Supply Current
CS
Others
V IN = V ILB
All inputs and outputs open
90
-
J.lA
J.lA
mA
NOTE:
1. Typical parameters are specified at VEE =-5.2V, TA = +25°C and maximum loading.
INPUT PULSE
LOAD CONDITION
Test Circuit
Vcc (GND)
-0.9V
j't
80%
tR =tF = 2.0ns typo
-2.0V
*Includes probe and jig capacitance.
S12-7
20%
---
-1.7V
1DT10490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64K x 1-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(VEE
= -5.2V ±5%, TA = '-55 to + 125°C, air flow exceeding 2m/sec)
TEST CONDITION
IDT10490S15
MAX.
MIN.
IDT10490S20
MIN.
MAX.
UNIT
READ CYCLE
t ACS
t RCS
Chip Select Access Time
-
-
Chip Select Recovery Time
tAA
Address Access Time
-
tOH
Data Hold from Address Change
-
3.5
5
ns
5
ns
15
-
20
ns
-
3.5
-
ns
5
5
TIMING WAVEFORM OF READ CYCLE NO.1
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
DATA OUT
_ t o "3 x x J - 5 0 %
RISE/FALL TIME
SYMBOL
PARAMETER
TEST CONDITION
tR
Output Rise Time
-
tF
Output Fall Time
-
-
S12-8
1DT10490
TYP.
MIN.
1
I
2
2
MAX.
I
I
UNIT
-
ns
-
ns
1DT10490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K x1-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(VEE
= -5.2V ±5%. TA = -55 to + 125°C. air flow exceeding2m/sec)
TEST CONDITION
1DT10490S15
MAX.
MIN.
IDT10490S20
MIN.
MAX.
UNIT
tw
Write Pulse Width
t wsA = minimum
10
-
13
-
ns
t WSD
Data Set-up Time
2
-
ns
Data Set-up to
5
7
Data Hold Time
tw = minimum
3
-
ns
tWHD
-
3
t WSD2
-
t WSA
Address Set-up Time
2
-
3
ns
tWHA
Address Hold Time
-
3
-
4
twscs
Chip Select Set-up Time
-
2
-
3
-
wr:. high
4
ns
ns
ns
t WHCS
Chip Select Hold Time
-
3
-
4
-
ns
tws
t wR (l)
Write Disable Time
-
-
10
10
ns
-
18
-
23
ns
Write Recovery Time
NOTE:
1. t WSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications. but this device actually only requires t WSD2
with respect to rising edge of WE.
2. tWR is defined as the time to reflect newly written data on the Data Outputs (00 to 03) when no new Address transition occurs.
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATAoUT
S12-9
10T10490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K xl-BIT)
MILITARY TEMPERATURE RANGE
ORDERING INFORMATION
lOT
XXXXX
999
Speed
Device Type
A
A
Package
Process/
Temperature
RM~8
Military (-55°C to
...................................~ 0
~
~.......................................................~ 15
20
...........................................................................~ S
~
...............................................................................................~ 10490
~
S12-10
+ 125°C)
CERDIP
} Speed in Nanoseconds
Standard Power
64K (64K x 1-Sit) SiCMOS ECL Static RAM
~
PRELIMINARY
.IDT 100490
HIGH-SPEED SiCMOS
Eel STATIC RAM
64K (64K x 1-SIT)
Intesrated Device1echnoIogy.Inc.
FEATURES:
DESCRIPTION:
• 65,536-words x 1-bit organization
The IDT100490 is a 100K compatible 65,536-bit high-speed
BiCEMOS ™ ECl static RAM organized as 64K x 1.
The IDT1 00490 is available with address access times as fast as
Bns with a typical power consumption of only 320mW. This product
offers the advantages of low-power operation, without sacrificing
speed, by integrating a dense high-speed CMOS static RAM with
internal level conversion. This allows the designer to reduce package count in an ECl system without increasing either power dissipation or access time.
Designed for very high-speed applications, the IDT100490 is
fully compatible with standard ECl 1OOK logic levels and offers extremely fast access times. The address access time of Bns and
write pulse width of 6ns assure that operations of this BiCEMOS
part will be as fast as those available with less dense parts requiring
external address decoding.
The IDT100490 is fabricated using lOT's high-performance,
high-reliability BiCEMOS technology. Operating power dissipation is extremely low compared with most ECl-compatible bipolar
devices, lowering power supply and cooling requirements.
• low power dissipation: 320mW (typ.)
• Fully compatible with 100K logic level
• Address access time: B/10/12/15/20ns (max.)
• Write pulse width: 6ns (min.)
• Separate data input and output
• JEDEC standard high-density 22-pin plastic DIP and CERDIP
and 24-pin Small Outline J-Bend IC
PIN CONFIGURATIONS
DATAoUT
lOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
Vcc
Ao
DATA IN
Ao
DATA IN
Al
Al
CS
A2
wr=.
A3
A15
A4
A5
A14
A13
A2
A3
A4
A5
Ae
A7
DECODER
Ae
A12
A7
All
As
As
AlO
Ag
VEE
Ag
AlO
All
WE
A12
A 13
A14
A 15
DATA IN
DIP, TOP VIEW
DATA OUT
Vcc
Ao
DATA IN
Al
CS
A2
A3
WE
NC
A4
A15
DATAoUT
A 15
65,536-BIT
MEMORY ARRAY
....
I/O CONTROL
DATA OUT
[fJI
CS
wr=.
CS
SOJ, TOP VIEW
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©
JANUARY 1989
DSC-8000/l
1989lntegrated Device Technology, Inc
512-11
IDT100490 HIGH SPEED BiCMOS
ECL STATIC RAM 64K (64K x 1·BIT)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
CAPACITANCE
(1)
UNIT
VALUE
RATING
Terminal Voltage
with Respect to
GND
+0.5 to -7.0
V
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
CIN
Input Capacitance
COUT
Output Capaoitanoe
CONDITIONS
TYP.
UNIT
6
pF
6
pF
-
TA
Operating
Temperature
Oto +85
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
cs
we
DATA OUT
FUNCTION
TSTG
Storage
Temperature
-65 to +150
-55 to +125
°C
H
X
L
Deselected
PT
Power Dissipation
1.0
W
L
H
RAM Data
Read
L
L
L
Write
lOUT
TRUTH TABLE (1)
I Hermetio
I Plastic
-50
DC Output Current (Output High)
mA
NOTE:
1. H = High, L = Low, X = Don't Care
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
oonditions above those indioated in the operational seotions of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(VEE
= -4.SV, RL = 500 to -2.0V, TA = 0 to + 85°C, air flow exceeding 2m/sec)
TEST CONDITIONS
TYP.(1)
MAX. (A)
UNIT
VOH
Output HIGH Voltage
\IN
= VIHA orVILB
-1025
-955
-880
mV
VOL
Output LOW Voltage
-1810
-1715
-1620
mV
VOHC
Output Threshold HIGH Voltage
\IN = VIHA orVILB
\IN = VIHB or VILA
-1035
-
mV
VOLC
Output Threshold LOW Voltage
-
-1610
mV
\lH
Input HIGH Voltage
-
-880
mV
\lL
Input LOW Voltage
-
-1475
mV
220
SYMBOL
PARAMETER
MIN. (B)
\IN = VIHB or VILA
Guaranteed Input Voltage High/Low
for All Inputs
Guaranteed Input Voltage High/Low
for All Inputs
Input HIGH Current
\IN
= VIHA
IlL
Input LOW Current
\IN
= VILB
lEE
Supply Current
All inputs and outputs open
-1165
-1810
-
CS
0.5
Others
-50
-
-120
-70
CS
IIH
-
Others
IJA
110
170
IJA
-
mA
NOTE:
1. Typical parameters are specified at VEE = -4.5V, TA = + 25 ° C and maximum loading.
LOAD CONDITION
INPUT PULSE
Test Circuit
Vcc (GNO)
-0.9V
DATA OUT
-1.7V
500
I
30pF*
1i
80010
----
t R = tF = 2.0ns typo
...J"
*Includes probe and jig capacitance.
S12-12
20%
1OT100490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K x 1-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(VEE = -4.5V ±5%. TA = 0 to +85°C. air flow exceeding 2m/sec)
TEST CONDITION
IDT100490S8 IDT100490S10 IDT100490S12 1OT1 00490S 15 IDT100490S20
UNIT
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
MIN.
READ CYCLE
t ACS
Chip Select Access Time
-
t RCS
Chip Select Recovery Time
tAA
Address Access Time
tOH
Data Hold from Address
Change
-
-
..
- <:::;;.;:...
3.p.;
10
-
-
' 3.5
-
5
-
5
8
-
-
3.5
:<':>
\::: ..
10
-
10
10
-
10
ns
12
-
15
-
20
ns
-
3.5
-
3.5
-
ns
5
5
ns
TIMING WAVEFORM OF READ CYCLE NO.1
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
DATA OUT
RISE/FALL TIME
SYMBOL
PARAMETER
tR
Output Rise Time
tF
Output Fall Time
TEST CONDITION
-
-
-
S12-13
1OT100490
TYP.
MIN.
I
I
2
2
UNIT
MAX.
1
I
-
ns
-
ns
\
1OT100490 HIGH SPEED BiCMOS
Eel STATIC RAM 64K (64K x 1-8IT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
(VEE
TEST CONDITION
= -4.5V ±5%, TA = 0 to + 85°C, air flow exceeding 2m/sec)
1OT100490S8 IDT100490S10 IOTl 00490S 12 1OT100490S15 IDT100490S20
UNIT
MAX; MIN.
MAX. MIN.
MAX. MIN.
MAX.
MAX. MIN.
MIN.
WRITE CYCLE
tw
t WSD(1)
Write Pulse Width
t WSA = minimum
6 .:::::::::::::::.:.. -
8
-
10
-
o ::<::::,:,:::}-
0
-
10
Data Set-up Time
0
-
2
t wsD2
Data Set-up to WE High
-
5 ::::;:::;:::::::::::::-
5
-
5
tWHD
Data Hold Time
-
2:::::-'::::/:':;: -
2
2
t WSA
Address Set-up Time
Address Hold Time
-
twscs
Chip Select Set-up Time
t WHCS
Chip Select Hold Time.
-
-
0
tWHA
2
tws
t WR (2)
Write Disable Time
-
-
-
-
5
-
-
12
Write Recovery Time
tw = minimum
-
:::::::::::::::::::::
:::::-:
::::::::::::=:::{:
/:::::m
::::::::::::;:;::::::.
:":':':::::::
2
0
-
15
-
ns
3
-
ns
5
-
7
-
ns
3
-
4
ns
2
3
4
-
3
-
ns
ns
3
0
-
2
-
2
-
3
-
4
-
-
5
-
10
-
10
ns
18
-
23
ns
0
2
14
ns
ns
NOTE:
1. tWSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires t WSD2
with respect to rising edge of WE.
2. tWR = tWHA + t AA and thus can include a full access time if addresses change while Chip Select is still low.
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATA~
DATAOUT
S12-14
IDT100490 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (64K xl-BIT)
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
xxxxx
999
A
A
Device Type
Speed
Package
Process!
Temperature
~L
Blank
Ip
l
L-..------i ~
8
10
~----------------------~ 12
Commercial (O°C to +85°C)
Plastic DIP
CERDIP
Small Outline Plastic J-Bend
} Speed In Nanosecond,
15
20
~--------------------~--------~: S
~---------------------___l
100490
512-15
-- -------------------------------------------
Standard Power
64K (64K xl-Bit) BiCMOS Eel Static RAM
t;)
Integrated Device1echnology. Inc.
HIGH-SPEED "SiCMOS'
ECl STATIC RAM
64K (16K X 4-BIT) .
PRELIMINARY
IDT10494
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
The IDT10494 Is a 65,536-bit high-speed BiCEMOS ™ ECl
static random access memory organized as 16K x 4, with inputs
and outputs fully compatible with ECl-10K levels.
Available with address access times as fast as 8ns, this device
exhibits a typical power consumption of only 600mW. It offers the
advantages of low-power operation, without sacrificing speed, by
integrating a dense high-speed CMOS static RAM with internal
level conversion. This allows the designer to reduce package
count in an ECl system without increasing either power dissipation or access time.
Designed for very high-speed applications, the IDT10494 offers
open emitter outputs and separate data input and output, as well as
extremely fast access times. The address access time of 8ns assures that operation of this BiCEMOS part will be as fast as with less
dense parts requiring external address decoding.
The devices are fabricated using lOT's high-performance, highreliability BiCEMOS technology. Operating power dissipation is
extremely low compared with most ECl-compatible bipolar devices, lowering power supply and cooling requirements.
16,384-words x 4-bit organization
Address access time: 8/10/15 ns (max.i
low power dissipation: 600mW (typ.)
Fully compatible with ECl logic levels
Separate data input and output
JEDEC standard through-hole and surface mount packages
LOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
Vcc
Ao
VEE
DECODER
A 13
65.536-BIT
MEMORY ARRAY
....
Do
Qo
SENSE AMPS
AND READ/WRITE
CONTROL
D1
D2
D3
Q1
Q2
Q3
WE
CS
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology. Inc.
DSC-8002/1
812-16
IDT10494 HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4·Bln
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
VTERM
CAPACITANCE
(1)
VALUE
RATING
Terminal Voltage
with Respect to
GND
SYMBOL
UNIT
+0.5 to -7.0
V
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTG
Storage
Temperature
-65 to +150
°C
PT
o to
+75
CIN
input Capacitance
C OUT
Output Capacitance
Power Dissipation
1.0
W
-50
mA
TYP.
UNIT
6
pF
6
pF
-
TRUTH TABLE (1)
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CS
Wi:
DATAoUT
FUNCTION
H
X
L
Deselected
L
H
RAM Data
Read
L
L
L
Write
NOTE:
1. H = High, L = Low, X = Don't Care
DC ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RL = 500 to -2.0V, TA = 0 to + 75°C for DIP, air flow exceeding
TEST CONDITIONS
PARAMETER
CONDiTIONS
°C
DC Output Current (Output High)
SYMBOL
(TA= +25°C f =1 OMHz)
PARAMETER(1)
SYMBOL
2m/sec)
MIN. (B)
TYp,<')
MAX. (A)
UNIT
TA
-855
-840
-810
-720
mV
O°C
25°C
75°C
VOH
Output HIGH Voltage
\IN = VIHA or VILB
-1000
-960
-900
VOL
Output LOW Voltage
\IN = VIHA or VILB
-1870
-1850
-1830
-
-1665
-1650
-1625
mV
O°C
25°C
75°C
VOHC
Output Threshold HIGH Voltage
\IN = VIHB or \lLA
-1020
-980
-920
-
-
mV
O°C
25°C
75°C
VOLe
Output Threshold LOW Voltage
\IN = VIHB or VILA
-
-
-1645
-1630
-1605
mV
O°C
25°C
75°C
\lH
Input HIGH Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1145
-1105
-1045
-
-840
-810
-720
mV
O°C
25°C
75°C
VIL
Input LOW Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1870
-1850
-1830
-
-1490
-1475
-1450
mV
O°C
25°C
75°C
Input HIGH Current
VIN = VIHA
-
-
220
IIH
CS
0.5
170
Others
-50
-
-160
-110
-
IlL
CS
Others
VIN = VILB
Input LOW Current
Supply Current
All inputs and outputs open
lEE
NOTE:
1. Typical parameters are specified at VEE = -5.2V. TA = + 25°C and maximum loading.
110
90
~A
~A
mA
INPUT PULSE
LOAD CONDITION
Test Circuit
Vee (GND)
-0.9V
j't
80%
20%
---
-1.7V
DATAoUT
500
-2.0V
1
tR
30PF *
tF
tR =tF = 2.0ns typo
*Includes probe and jig capacitance.
S12-17
1DT10494 HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RANGE
(VEE
= -5.2V ±5%. TA = 0 to + 75°C. air flow exceeding 2m/sec)
t ACS
Chip Select Access Time
-
,:. ?\:.
t RCS
Chip Select Recovery Time
-
tAA
Address Access Time
-
:::::)::,::::f::;;
. ;;.P::::<:::';· 8
tOH
Data Hold from Address Change
-
SYMBOL
1DT10494S10
MAX.
MIN.
IDT10494S8
MAX.
MIN.
PARAMETER
TEST
CONDITION
IDT10494S15
MIN.
MAX.
UNIT
READ CYCLE
;::(3·;····
-
-
5
-
5
5
5
ns
-
10
-
12
ns
3.5
-
3.5
-
ns
ns
READ CYCLE GATED BY CHIP SELECT
DATA OUT
READ CYCLE GATED BY ADDRESS
ADDRESS
DATA OUT
RISE/FALL TIME
SYMBOL
PARAMETER
tR
Output Rise Time
tF
Output Fall Time
TEST CONDITION
-
-
-
S12-18
IDT10494
TYP.
MIN.
I
I
2
2
MAX.
I
I
UNIT
-
ns
-
ns
IDT10494 HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
(VEE
= -5.2V ±5%, TA = 0 to + 75°C, air flow exceeding 2m/sec)
IDT10494S8
MAX,
MIN.
TEST
CONDITION
PARAMETER
IDT10494S10
MIN.
MAX.
IDT10494S15
MIN.
MAX.
UNIT
WRITE CYCLE
tw
Write Pulse Width
t wsD
Data Set-up Time
t wsD2 (1)
Data Set-up Time to
wr:. High
tWHD
Data Hold Time
t WSA
Address Set-up Time
tWHA
Address Hold Time
twscs
Chip Select Set-up Time
t WHcS
Chip Select Hold Time
tws
t WR (1)
Write Disable Time
-
0
-
5
2
Write Recovery Time
::}::;:;:::t:.
:\(\: -
idEe
:::::.;.:.:.:-:'"
tw = minimum
-
j£+
6
t WSA = minimum
;::::;:::;::::::
.:::/):):
::::::::::?
':::::::::f
8
-
10
-
2
-
ns
0
5
-
ns
ns
5
ns
-
2
-
3
-
0
2
-
ns
-
2
-
3
ns
-
0
-
2
-
2
-
3
-
-
5
-
5
ns
5
-
5
ns
ns
ns
NOTES:
1. t WSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires t WSD2
with respect to rising edge of
2. tWR is defined as the time to reflect the newly written data on the Data Outputs (Q to Q ) when no new Address transition occurs.
wr:..
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATAoUT
S12-19
...... -
-_..._-_._-_. ----_.... _,-------
IDT10494 HIGH·SPEED BICMOS
ECl STATIC RAM 64K (16K x 4·BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
Do
~
01
wr=
DZ
D3
NC
A 13
A12
All
A 10
00
01
Vec
Vee
VEE
O2
Ag
03
Ao
As
A7
Al
A6
Az
As
A4
A3
DIP
TOP VIEW
(400mll)
ORDERING INFORMATION
A
999
A
A
Power
Speed
Package
Process/
Temp~Brank
Commercial (O°C to
L....-_ _ _ _ _~Ic
I
L....-----_ _ _ _~I~o}
+ 75°C)
Sidebraze DIP
Speed in Nanoseconds
115
L..--_ _ _ _ _ _ _ _ _ _ _ _---jl
S
I
L---------------------Ir 10494
S12-20
Standard Organization
64K (16K x 4·Bit) BiCMOS ECl Static RAM
Integrated Device1echnoIogy.1nc.
HIGH-SPEED SiCMOS
ECl STATIC RAM
64K (16K X 4-SIT)
Mll-STD-883 COMPLIANT
ADVANCE
INFORMATION
IDT 10494M
DESCRIPTION:
FEATURES:
• 16,384-word x 4-bit organization
• low power dissipation: 600mW (typ.)
• Fully compatible with ECl-10K logic levels
•
•
•
•
•
•
•
The IDT10494 is a 10K compatible 65,536-bit high-speed
BiCEMOS'· ECl static RAM organized as 16K x 4. It is manufactured, assembled, and tested by Integrated Device Technology,
Inc. in full compliance with Mll-STD-883, and operates over the full
Address access time: 15/20ns (max.)
temperature range of -55°C to + 125°C.
Write pulse width: 10ns (min.)
The IDT10494 is available with address access times as fast
Open emitter output for ease of memory expansion
as 15ns with a typical power consumption of only 600mW. This
Separate data input and output
product offers the advantages of low-power operation, without sacJEDEC standard 28-pin DIP
rificing::$peed,by integrating a dense high-speed CMOS static
RAf\:1..
internal level conversion. This allows the designer to
Mll-STD-883 compliant
acKl~¥.~?)'igh-performance ECl system with dramatically lower
Operation over the full temperature range -55°C to + 125°C
.:J~qw.~i'dl$.~lpation than bipolar equivalents, reducing powersupply
.:::t:::~nc:fGQolinglequirements .
..::::>:..·:::::::::::::::::::P.:~igm~cifor very high-speed applications, the IDT1 0494 is fully
':::}{:::::}>:C6fuP9t1b1e with standard ECl-10K logic levels and offers ex·::t)::::::)::::~r~.rriery fast access times. Applications include cache, control
\@}t:stpre, buffer, and main memory uses. The high density allows fewer
::)@:address-decode delays, providing better system speed over
'. smaller ECl memories.
W:iib
LOGIC SYMBOL
Ao
Ao
AI
A2
A3
A4
As
Ae
A7
A8
A9
AlO
All
A12
A13
Qo
.
Q1
Q2
DECODER
65.536-BIT
MEMORY ARRAY
A 13
~
Q3
Do
Dl
D2
SENSE AMPS
AND READ/WRITE
CONTROL
D3
~
CS
CS
BiCEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
MILITARY TEMPERATURE RANGE
© 1989 Integrated Device Technology, Inc.
DSC-80 10/-
S12-21
IDT10494 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (16Kx 4-BIT)
MiliTARY TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
CAPACITANCE
(1)
VALUE
RATING
Terminal Voltage
with Respect to
GND
UNIT
+0.5 to -7.0
V
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
CONDITIONS
CIN
Input Capacitance
C OUT
Output Capacitance
TA
Operating
Temperature
-55 to +125
°C
TB1AS
Temperature
Under Bias
-65 to +135
°C
cs
WE
TSTG
Storage
Temperature
-65 to + 150
°C
H
PT
Power Dissipation
1.0
W
L
L
TYP.
UNIT
6
pF
6
pF
-
TRUTH TABLE (1)
DC Output Current (Output High)
-50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DATAoUT
FUNCTION
X
L
Deselected
H
RAM Data
Read
L
L
Write
NOTE:
1. H = High, L = Low, X = Don't Care
DC ELECTRICAL CHARACTERISTICS
(VEE = -52V RL = 500 to -2 OV TA = -55 to + 125°C for DIP air flow exceeding 2m/sec)
PARAMETER
SYMBOL
VOH
TEST CONDITIONS
Output HIGH Voltage
MIN. (B)
"IN = VIHA or"lLB
-1070
-960
-860
TYP.(1)
MAX. (A)
UNIT
TA
-855
-860
-810
-600
mV
-55°C
25°C
+125°C
..
,
VOL
Output LOW Voltage
"IN = VIHA or "ILB
-1900
-1850
-1800
-
-1690
-1650
-1570
mV
-55°C
25°C
+125°C
VOHC
Output Threshold HIGH Voltage
"IN = VIHB or "ILA
-1090
-980
-830
-
-
mV
-55°C
25°C
+125°C
VOLC
Output Threshold LOW Voltage
"IN = VIHB or "ILA
-
-
-1670
-1630
-1550
mV
-55°C
25°C
+125°C
Input HIGH Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1215
-1105
-1005
-
-860
-810
-600
mV
-55°C
25°C
+125°C
"'IL
Input LOW Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1900
-1850
-1800
-
-1515
-1475
-1395
mV
-55°C
25°C
+125°C
IIH
Input HIGH Current
VIN = VIHA
"IH
IlL
Input LOW Current
lEE
Supply Current
VIN = VILB
CS
-
Others
-
CS
0.5
Others
-50
-
-160
-110
All inputs and outputs open
220
-
110
170
90
~OTE:
1. Typical parameters are specified at VEE = -5.2V, TA = +25°C and maximum loading.
INPUT PULSE
LOAD CONDITION
Test Circuit
Vee (GND)
-0.9V
-1.7V
tR =tF = 2.0ns typo
VEE
-2.0V
*Includes probe and jiq capacitance.
S12-22
JlA
JlA
mA
IDT10494 HIGH SPEED BICMOS
ECl STATIC RAM 64K (16K X 4-BIT)
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
(VEE
= -5.2V ±5%, TA = :...55 to + 125°C, air flow exceeding 2m/sec)
t AcS
Chip Select Access Time
t AcS
Chip Select Recovery Time
tAA
Address Access Time
tOH
Data Hold from Address Change
I 0T1 0494S20
MAX.
MIN.
IDT10494S15
MAX.
MIN.
TEST CONDITION
-
UNIT
-
-
5
5
5
ns.
15
-
20
ns
TBD
-
TBD
-
ns
5
ns
TIMING WAVEFORM OF READ CYCLE NO.1
~---f%
~
r
tAcs----.j·1
tees
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
to_H~_50-%--
_______
DATA OUT
RISE/FALL TIME
SYMBOL
PARAMETER
TEST CONDITION
tA
Output Rise Time
-
tF
Output Fall Time
-
-
S12-23
IDT10494
TYP.
MIN.
I
I
2
2
MAX.
I
I
UNIT
-
ns
-
ns
1DT10494 HIGH SPEED BICMOS
ECl STATIC RAM 64K (16K x 4-BIT)
MiliTARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
(Vee = -5.2V ±5%, TA = -55 to
TEST CONDITION
tWHA
Address Hold Time
-
ns
4
ns
3
4
-
ns
ns
ns
twscs
Chip Select Set-up Time
-
2
-
3
-
ns
t WHCS
Chip Select Hold Time
3
-
4
-
ns
tws
t WR (l)
Write Disable Time
-
-
5
-
5
ns
-
5
-
5
ns
Write Recovery Time
-
ns
TBD
-
TBD
tw = minimum
-
3
2
Data Hold Time
-
3
-
10
-
Address Set-up Time
13
3
tWSA = minimum
Data Set-up Time
t WHO
UNIT
2
Write Pulse Width
twso
t WS02
tWSA
IDT10494S20
MIN.
MAX.
-
tw
Data Set-up to wr:. high
+ 125°C, air flow exceeding 2m/sec)
IDT10494S15
MIN.
MAX.
NOTE:
1. t\'(so is specified with respet to the falling edge of wr:. for compatibility with bipolar part specifications, but this device actually only requires t WS02
with respect to rising edge of wr:..
2. tWR is defined as the time to reflect newly written data on the Data Outputs (00 to 03) when no new Address transition occurs.
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATAOUT
S12-24
IDT10494 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIT)
MILITARY TEMPERATURE RANGE
PIN CONFIGURATION
DIP
TOP VIEW
(400mil)
ORDERING INFORMATION
lOT
XXXXX
A
Device Type
Power
999
Speed
A
Package
A
Process/
Temperature
-LB
~--------------~
~------------------------------~
C
Sidebraze DIP
15
20
} Speed in Nanoseconds
S
Standard Power
10494
64K (16K x 4-Sit) SiCMOS ECl Static RAM
S12-25
..
_-_._--_..,._-_
...
_.__......... - - - - - - - - - - - - - - - -
~
Intesrated DeviceTechnology. Inc.
PRELIMINARY
lOT 100494
HIGH-SPEED SiCMOS
ECl STATIC RAM
64K (16K x 4-SIT)
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
The IDT100494 is a 65,536-bit high-speed BiCEMOS ™ ECl
static random access memory organized as 16K x 4, with inputs
and outputs fully compatible with ECl-100K levels
Available with address access times as fast as Sns, this device
exhibits a typical power consumption of only 600mW. It offers the
advantages of low-power operation, without sacrificing speed, by
integrating a dense high-speed CMOS static RAM with internal
level conversion. This allows the designer to reduce package
count in an ECl system without increasing either power dissipation or access time.
Designed for very high-speed applications, the IDT100494
offers open emitter outputs and seperate data input and output, as
well as extremely fast access times. The address access time of
Sns assures that operation of this BiCEMOS part will be as fast as
with less dense parts requiring external address decoding.
The devices are fabricated using IDT's high-performance, highreliability BiCEMOS technology. Operating power dissipation is
extremely low compared with most ECl-compatible bipolar devices, lowering power supply and cooling requirements.
16,3S4-words x 4-bit organization
Address access time: S/10/15ns (max.)
low power dissipation: 500mW (typ.)
Fully compatible with ECl logic levels
Separate data input and output
JEDEC standard through-hole and surface mount packages
LOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
Ao -n.----1
Ao
A,
A2
A3
A4
As
Ae
A7
A8
A9
A,o
A"
A'2
A'3
~
00
DECODER
65.536-BIT
MEMORY ARRAY
0,
O2
03
SENSE AMPS
AND READ/wRITE
CONTROL
cs
BiCEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
© '989 In'egrated DevIce Technology. Inc.
OSC-8009/-
S12-26
1OT100494 HIGH SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
UNIT
VALUE
Terminal Voltage
with Respect to
GND
VTERM
CAPACITANCE
(1)
RATING
SYMBOL
+0.5 to -7.0
TA
Operating
Temperature
TBIAs
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation
1.0
lOUT
DC Output Current (Output High)
-50
I Hermetic
J Plastic
V
Oto +85
°C
-55 to +125
°C
-65 to +150
-55 to +125
°C
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
DIP
TYP.
MAX.
-
C IN
Input Capacitance
6
C OUT
Output Capacitance
6
SOJ
TYP.
MAX.
-
TBD
TBD
TRUTH TABLE (1)
cs
WE
DATA OUT
FUNCTION
H
X
L
Deselected
W
L
H
RAM Data
Read
mA
L
L
L
Write
NOTE:
1. H = High, L = Low, X = Don't Care
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(VEE
=
-4.5V, RL
= son to -2.0V, TA = 0 to
SYMBOL
+85°C, air flow exceeding 2m/sec)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOHC
Output Threshold HIGH Voltage
VOLC
Output Threshold LOW Voltage
"'H
Input HIGH Voltage
"'L
Input LOW Voltage
MIN. (B)
TEST CONDITIONS
PARAMETER
= VIHA or VILB
"'N
= VIHA or VILB
"'N
VIN = VIHB or VILA
= VIHB or VILA
Guaranteed Input Voltage High/Low
for All Inputs
V,N
Guaranteed Input Voltage High/Low
for All Inputs
IIH
Input HIGH Current
IlL
Input LOW Current
"'N = VILB
lEE
Supply Current
All inputs and outputs open
"'N
= VIHA
TYP.(1)
MAX. (A)
UNIT
-1025
-955
-880
mV
-1810
-1715
-1620
mV
-1035
-
-
mV
-1610
mV
-1165
-
-880
mV
mV
-
-1810
-
-1475
CS
-
-
220
Others
-
-
110
CS
0.5
-50
-
170
Others
-140
-110
-
jJA
jJA
-
mA
NOTE:
1. Typical parameters are specified at VEE = -4.5V. TA = +25°C and maximum loading.
LOAD CONDITION
INPUT PULSE
Test Circuit
Vcc (GND)
-0.9V
!i
80 %
---
-1.7V
30pF*
tR =tF
-2.0V
*Includes probe and jig capacitance.
S12-27
= 2.0ns typo
20%
IDT100494 HIGH SPEED BICMOS
ECl STATIC RAM 64K (16Kx 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
(VEE = -4.5V ±5%, TA = 0 to +85°C, air flow exceeding 2m/sec)
TEST CONDITION
IDT100494S8
IDT100494S10
MIN.
MAX.
IDT100494S15
MIN.
MAX.
UNIT
READ CYCLE
t Acs
Chip Select Access Time
t RCS
Chip Select Recovery Time
-
tAA
Address Access Time
-
tOH
Data Hold from Address Change
-
~:::::};::::
.:::::::::::.... 3
·/S ;:::t:: .{(:;:;::;;::;::L
.::;;% :;: : . :::::ti:;::;:t· 8
3 ·~S;:?·
-
3.5
5
ns
10
-
15
ns
-
3.5
-
ns
5
5
5
ns
TIMING WAVEFORM OF READ CYCLE NO.1
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
ADDRESS
DATA OUT
-------to-"~-50-%--
RISE/FALL TIME
SYMBOL
PARAMETER
TEST CONDITION
tR
Output Rise Time
-
tF
Output Fall Time
-
-
S12-28
IDT100494
TYP.
MIN.
J
I
2
2
MAX.
I
I
-
UNIT
ns
ns
1DT100494 HIGH SPEED BICMOS
ECl STATIC RAM 64K (16K X 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(VEE
= -4.5V -+5%, TA = Oto
+85°C, airflow exceeding 2m/sec) ,
IDT100494S8
TEST CONDITION
IDT100494S10
MIN.
MAX.
IDT100494S15
MIN.
MAX.
UNIT
WRITE CYCLE
tw
Write Pulse Width
t WSD
Data Set-up Time
t WSD2 (1)
Data Set-up to ~ High
tWHD
Data Hold Time
tWSA
Address Set-up Time
tWHA
Address Hold Time
twscs
Chip Select Set-up Time
tWHCS
Chip Select Hold Time
tws
t WR (2)
Write Disable Time
tWSA = minimum
8
-
10
(I,:'':::;:::':':::? i::2.::::::;:'·
0
-
2
f:::,,::~:::' it:':::i<'::
5
5
2
-
-
5
6,::/::::::::::::
-
":::~ ;\:::::::
tw = minimum
::2::;:::::::::
;:::::.::::.:.:.::::-
:::::=:::()::::: ,:}:j'::=::}i
,
Write Recovery Time
-
,\::::::}:::::' ,::\::::::::::),
I
::'::::::::::::::::(:i~/~:;::;:::::
"':::{::
/r,;::;,:::::::'
::;:;::::(:::::,:
:';::::::::.:.;.:.:'
2
0
2
0
5
3
-
ns
2
-
ns
3
-
ns
ns
5
ns
5
ns
2
3
-
ns
ns
ns
ns
NOTE:
1. t WSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires t wsD2
with respect to rising edge of WE.
'
2. tWR is defined as the time to reflect newly written data on the Data Outputs (00 to 03) when no new Address transition occurs.
TIMING WAVEFORM OF WRITE CYCLE
ADDRESS
DATAoUT
S12-29
IDT100494 HIGH SPEED BICMOS
ECl STATIC RAM 64K (16K X 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
Do
01
CS
02
03
00
NC
A 13
A12
All
A 10
~
01
Vee
Vcc
O2
03
VEE
Ag
Al
Aii
A7
A6
A2
A3
A5
A4
Ao
DIP
TOP VIEW
(400mll)
SOJ
TOP VIEW
(350mll)
ORDERING INFORMATION
lOT
xxxxx
999
A
A
Device Type
Speed
Package
Process!
Temperature
Range
~m,"k
~
______________
~
~--------------------~
C
Commercial O°C to +85°C
Y
Sidebraze DIP
Smail Outline Plastic J-Bend
8
10
} Speed in Nanoseconds
15
~----------------------------~
1...-____________________________________--1
S12-30
---------------------------
S
100494
Standard Power
64K (16K x 4-Bit) BiCMOS ECl Static RAM
~
Integrated Device1echnoIogy. Inc.
HIGH-SPEED SiCMOS ECl
SELF-TIMED STATIC RAM
64K (16K x 4-SIT)· STRAM
PRELIMINARY
IDT10496LL
FEATURES:
DESCRIPTION:
• 16,384-words x 4-bit organization
The IDT10496ll is a 65,536-bit high-speed BiCEMOS TM ECl
static random access memory organized as 16K x 4, with inputs
and outputs fully compatible with ECl 10K levels~ This device has
on-board self-timed circuitry to relax control timing, providing easier design and improved system level cycle times.
Clocked latches on inputs and outputs, and the self-timed write
operation, provide enhanced system performance over conventional RAMs by removing the need to control any write pulse width,
and relaxes timing of write enable (WE). Combined with address
access times as fast as 12ns, the IDT1 0496ll allows cycle times as
fast as 15ns.
The IDT10496ll is fabricated using IDT's high-performance,
high-reliability BiCEMOS technology. It offers the advantage of
low-power operation· without sacrificing speed by integrating a
dense, high-speed CMOS static RAM and logic with intemallevel
conversion. Power supply and cooling requirements are reduced,
while the fast access time assures that operation of BiCEMOS parts
will be as fast as with less dense parts requiring extemal address
decoding.
• Self-Timed, with latches on inputs and outputs
• Cycle time 13/15ns
• Address access time: 10/12ns (max.)
• low power dissipation: 800mW (typ.)
• Fully compatible with ECl logic levels
• Separate data input and output
• JEDEC standard through-hole and surface mount
packages
FUNCTIONAL BLOCK DIAGRAM
Vee
~
__-r______
~
__-r______
~B
A/r3
ClK
-ror--.---
COK~~------~--~--------------------~--------------~
* HOLD/CJF5'EN
BiCEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
©
DSC-8003/1
1989 Integrated Device Technology. Inc.
S12-31
- - - - - - - - - - - - - - - _ . _ .__ ....
_--_ _ - - - - - - - - - - - - - - - ...
IDT10496Ll HIGH·SPEED BICMOS
ECl SElF·TIMED STATIC RAM 64K (16Kx 4·BIT) STRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
CAPACITANCE
(1)
UNIT
VALUE
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL TEMPERATURE RANGE
+0.5 to -7.0
V
TA
Operating
Temperature
Oto +75
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
TSTO
Storage
Temperature
-65 to +150
°C
PT
1.0
Power Dissipation .
(TA= +25°C f = 10MHZ)
PARAMETER(l)
TYP.
CIN
Input Capacitance except ClK
4
Input Capacitance ClK
6
-
pF
CIN
COUT
I/O Capacitance
6
-
pF
SYMBOL
TRUTH TABLE (1)
~
WE
W
-50
DC Output Current (Output High)
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
H
X
l
H
l
l
DATAoUT(2)
ClK
\.F
\.F
\.F
MAX. UNIT
pF
FUNCTION
l
Deselected
RAM Data
Read
WRITE Data
Write
NOTES:
1. H = High. l = low, X = Don't Care
2. DATAoUT changes when ClK retums high.
DC ELECTRICAL CHARACTERISTICS
(VEE
= -S.2V, RL = 500 to -2.0V, T A = 0 to + 75°C for DIP, air flow exceeding 2m/sec)
SYMBOL
TEST CONDITIONS
PARAMETER
MIN. (B)
-1000
-960
\IN = VIHA or \lLB
TYP.(1)
MAX. (A)
UNIT
TA
-855
-840
-810
-720
mV
O°C
25°C
75°C
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
\IN = VIHA or \lLB
-1870
-1850
-1830
-
-1665
-1650
-1625
mV
O°C
25°C
75°C
VOHC
Output Threshold HIGH Voltage
\IN == \'JHB or \lLA
-1020
-980
-920
-
-
mV
O°C
25°C
75°C
VOLC
Output Threshold lOW Voltage
\IN = VIHB or \lLA
-
-
-1645
-1630
-1605
mV
O°C
25°C
75°C
\'JH
Input HIGH Voltage
Guaranteed Input Voltage
High/low for All Inputs
-1145
-1105
-1045
-
-840
-810
-720
mV
O°C
25°C
75°C
\'tL
Input lOW Voltage
Guaranteed Input Voltage
High/Low for All Inputs
-1870
-1850
-1830
-
-1490
-1475
-1450
mV
O°C
25°C
75°C
IIH
Input HIGH Current
VIN = VitiA
IlL
Input lOW Current
-900
CS
0.5
Others
-50
-200
-150
Others
VIN = VILB
-
-
CS
Supply Current
All inputs and outputs open
lEE
NOTE.
1. Typical parameters are specified at VEE = -5.2V. T A = + 25°C and maximum loading.
220
-
110
170
J,lA
J,lA
90
mA
INPUT PULSE
LOAD CONDITION
Test Circuit
Vee (GND)
-0.9V
!i
80 %
---
-1.7V
tR =tF = 2.0ns typo
-2.0V
*Includes probe and jig capacitance.
S12-32
20%
1OT10496LL HIGH-SPEED BiCMOS
ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT) STRAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER(1)
COMMERCIAL TEMPERATURE RANGE
(VEE = -5.2V ± 5%, TA = 0 to + 75°C, air flow exceeding 2m/sec)
IDT10496LL15
MIN.
MAX.
IDT10496LL13
MAX.
MIN.
TEST CONDITION
UNIT
READ CYCLE GATED BY ADDRESS(2)
tCYC
t M (3)
Address Access Time
tWL
Clock Low Pulse Width
tWH
Clock High Pulse Width
-
tSA
Set-up Time for Address
-
Cycle Time
13
Ll-
-
-
..:.. \,:::::\':::\:'
3
10
15
-
ns
-
12
ns
ns
..:,{::. ::"=::;,:;:)O
. ::?::(:":
.;:;:.
. .:.):(:::::::t::,:
3
-
12
-
ns
1
-
ns
tHA
Hold Time for Address
2
-
ns
"\/0'
-
Data Out Hold from Clock High
-
:,?::,::::=~::))
toH
-
0
-
ns
to~3.4)
Data Out Ready from Clock High
-
0
4
0
4
ns
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. Read Cycle is gated by address when tSA < tWL so that the access begins at the setting of the address.
3. Access time is the larger of tM or tSA +t oR'
4. tOR (max) is specified when all other gating conditions have been satisfied, specifically when tSA > tM (max) -tOR (max).
READ CYCLE GATED BY ADDRESS
~--------------tCYC--------------~
OUTPUT
LATCH OPEN
ClK
----~----------tWH-----------~
ADDR
DATA
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
--------~----+,
tOH
RISE/FALL TIME
SYMBOL
PARAMETER(1)
TEST CONDITION
tR
Output Rise Time
tF
Output Fall Time
-
IOT10496
-
S12-33
TYP.
MIN.
1
I
2
2
I
I
MAX.
UNIT
-
ns
ns
1DT10496ll HIGH-SPEED BiCMOS
ECl SELF-TIMED STATIC RAM 64K (16K x 4-BIT) STRAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER(1)
COMMERCIAL TEMPERATURE RANGE
(VEE = -5.2V ± 5%, TA = 0 to + 75°C, air flow exceeding 2m/sec)
IDT10496ll13
MAX.
MIN.
TEST CONDITION
IDT10496ll15
MIN.
MAX.
UNIT
READ CYCLE GATED BY CHIP SELECT (2)
tCYC
Cycle Time
-
13
t ACs/ 3)
Chip Select Access Time
-
-
tWL
Clock Low Pulse Width
3
tWH
Clock High Pulse Width
-
tscs
Setup Time for Chip Select
tHcS
-
15
-
ns
"{"'{:,,::::"\':,5
-
5
ns
-
3
ns
-
12
-
1
ns
.
Hold Time for Chip Select
-
. "".'\~:g:"'t:: '.,.:.'
-
2
tOH
Data Out Hold from Clock Hfgh
-
\:~::?'tf"
-
0
-
t OR(3.4)
Data Out Ready from Clock High
-
4
0
4
10
. ,.,.:':::::??t::. ··
.'\,"~:::::~~,:::;"">
. t",;;::~~~\,
0
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. Read Cycle is gated by Chip Select when tscs < tWL so that the access begins as the falling edge of Chip Select.
3. Access time Is the larger of tACS or tscs +t OR'
4. tOR (max) is specified when all other gating conditions have been satisfied, specifically when tscs > ~cs (max) -tOR (max) ..
READ CYCLE GATED BY CHIP SELECT
1+-------- tCYC -------~
OUTPUT
LATCH OPEN
ClK
--~~-----tWH-------~
DATA
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
S12-34
ns
ns
ns
ns
IDT10496LL HIGH-SPEED BICMOS
ECL SELF-TIMED STATIC RAM 64K (16Kx 4-BIT) STRAM
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER(1)
(VEE
COMMERCIAL TEMPERATURE RANGE
= -5.2V ± 5%, TA = 0 to
TEST CONDITION
+ 75°C, air flow exceeding 2m/sec)
IDT10496LL13
MIN.
MAX.
IDT10496LL15
MIN.
MAX.
UNIT
READ CYCLE GATED BY CLOCK(2)
tCYC
t ACLK(3)
Cycle Time
-
Clocked Access Time
-
tWL
Clock Low Pulse Width
tWH
Clock High Pulse Width
tOH
Data Out Hold from Clock High
t oR (3.4)
Data Out Ready from Clock High
-
13
....:::::=.-
",,<{::,,>::\}to
3
tACLK -tOR (max).
READ CYCLE GATED BY CLOCK
14--------
tCYC
---------t
OUTPUT
LATCH OPEN
CLK
--~~-----tWH----~
ADDR
DATA'
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
S12-35
ns
IDT10496ll HIGH-SPEED BICMOS
ECl SELF-TIMED STATIC RAM 64K (16K x 4-BI1) STRAM
AC ELECTRICAL CHARACTERISTICS
PARAMETER(1)
SYMBOL
COMMERCIAL TEMPERATURE RANGE
(VEE = -5.2V
± 5%, TA = Oto +75°C, airflow exceeding 2m/sec)
IDT10496LL13
MIN.
MAX.
TEST CONDITION
IDTl 0496LL15
MIN.
MAX.
UNIT
WRITE CYCLE (2)
tCYC
Cycle Time
-
13
-
15
-
ns
tAW (3)
Write Access Time
-
-
5
5
ns
t A01 (4)
Write Data Access Time
-
5
ns
tWL
Clock low Pulse Width
-
3
ns
10
ns
ns
tWH
Clock High Pulse Width
tscs
Set-up Time for Chip Select
tsWE
Set-up Time for Write Enable
tSA
Set-up Time for Address
-
tso
Set-up Time for Data In
-
t HCS
Hold Time for Chip Select
t HWE
Hold Time for Write Enable
tHA
Hold Time for Address
-
, ,t::;:::::"~"9.,,:
,:=::I:;:it "::;::,Z
1
-
1
I.:}:::;;::::::::::il:
-
1
-
1
-
2
2"
-
2
2
-
2
-
3
1
::,,}~:;:::':: ii:,;;;:;:'::;:-
,::::t::t:::::::',>
biJL
:::t;
::::::::::::;
~W:::::'
-
12
-
1
ns
ns
ns
ns
ns
ns
Hold Time for Data In
2
2
tHO
ns
NOTES:
1. Input and Output reference level is 50% pOint of waveform.
2. Data Hold tOH and Data Ready tOR are the same as for Read Cycle.
3. Access time is the larger of tAW or tSWE + tOR,
4. Access time is the larger of tADI or tSO+tOR'
5. tOR (max) is specified when all other gating conditions have been satisfied, specifically when tso > t AOI (max) - tOR (max) and tswE > tAW (max)tOR (max).
WRITE CYCLE
~--------------tCYC--------------~
OUTPUT
LATCH OPEN
ClK
----~--------tWH----------~
ADDR
DATA
IN
DATA
OUT
----r---r----f.,
INPUT DATA ON
OUTPUT LATCHES
S12-36
IDTt0496ll HIGH-SPEED BICMOS
ECl SELF-TIMED STATIC RAM 64K (16K x 4-BIT) STRAM
COMMERCIAL TEMPERATURE RANGE
CLOCK INPUT
The clock input circuit in the IDT10496ll has been designed to
accomodate both single-ended and differential mode operation.
Differential mode exhibits better rejection of common-mode noise
and is obtained by driving both true and complement elK lines
with a differential driver, as shown in Figure (a). Single-ended
operation is achieved as either falling-edge-active or rising edgeactive, as shown in Figures (b) and (e), respectively.
r-------,
1
1
CD< ...........~.-..,1
.-------,1
ClK
r-------,
ClK
CD<
1
1
1
-,I
r - - -_ _ _
1
1
-'I1
1 -_ _ _- - 1
L -_ _ _ _
.J
I... _ _ _ _ _ _ _ .J1
(b) Falling-Edge-Actlve
Single-Ended Mode
(c) RIslng-Edge-Active
Single-Ended Mode
I... _ _ _ _ _ _ _
(a) Differential Mode
LOGIC SYMBOL
Do 0,
Ao
A,
A2
A3
A4
A5
Ae
A7
As
Ag
ClK
PIN CONFIGURATION
O2 0 3
Qo
Q,
CS
wr:.
Do
0,
Vee
ClK
O2
CIJ<
03
NC
NC
Qo
Q,
Q2
A,o
A"
A'2
A'3
A'3
A'2
VEE
Vee
Vee
Q2
Q3
Q3
A"
A,o
Ag
Ao
A,
CIJ<
1
As
A7
As
A2
A3
A4
wr:. cs
A5
DIP
TOP VIEW
(400mil)
S12-37
t;J
Integrated DevicekhnoIogy. Inc.
PRELIMINARY
lOT 100496LL
HIGH-SPEED SiCMOS
ECl SELF-TIMED
STATIC RAM
64K (16K x 4-SIT) STRAM
FEATURES:
DESCRIPTION:
• 16,384-words x 4~bit organization
• Self-Timed, with latches on inputs and outputs
The IDT100496ll Is a 65,536-bit high-speed BiCEMOS ™ ECl
static random access memory organized as 16K x 4, with Inputs
and outputs fully compatible with ECl-100K levels. This device
has on-board self-timed circuitry to relax control timing, providing
easier design and Improved system level cycle times.
Clocked latches on inputs and outputs, and the self-timed write
operation, provide enhanced system performance over conventional RAMs by removing the need to control any write pulse width,
and relaxes timing of write enable (WE). Combined with address
access times as fast as 12ns, the IDT100496ll allows cycle times
as fast as 15ns.
The IDT100496ll is fabricated using IDT's high-performance,
high-reliability BiCEMOS technology. It offers the advantage of
low-power operation without sacrificing speed by integrating a
dense, high-speed CMOS static RAM and logic with intemal level
conversion. Power supply and cooling requirements are reduced,
while the fast access time assures that operation of BiCEMOS parts
will be as fast as with less dense parts requiring external address
decoding.
•
•
•
•
•
•
Cycle time 13/15ns
Address access time: 10/12ns (max.)
low power dissipation: 700mW (typ.)
Fully compatible with ECl logic levels
Separate data input and output
JEDEC standard through-hole and surface mount
packages
FUNCTIONAL BLOCK DIAGRAM
Vee
65,536-BIT
MEMORY ARRAY
~--~------~~~------~
B
Af'd
ClK ~~---+--'
crn~~------~~~--------------------+---------------~
* HOlD/Ql5El\j
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated DevIce Technology, Inc.
050-8006/-
S12-38
IDT100496ll HIGH·SPEED BICMOS
ECl STATIC RAM 64K (16Kx 4-BIT)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
CAPACITANCE
(1)
RATING
Terminal Voltage
with Respect to
GND
UNIT
VALUE
+0.5 to -7.0
V
TA
Operating
Temperature
Otc +85
°C
TBIAS
Temperature
Under Bias
-55 to +125
°C
Tsro
Storage
Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
(TA= +25°C, f = 1.0MHz)
PARAMETER (1)
TYP.
C IN
Input Capacitance except CLK
4
-
C IN
Input Capacitance ClK
6
C OUT
1/0 Capacitance
6
-
SYMBOL
MAX. UNIT
pF
pF
pF
TRUTH TABLE (1)
W
DC Output Current (Output High)
-50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
cs
m
H
X
l
H
L
L
ClK
\F
\F
\F
DATAoUT(2)
FUNCTION
L
Deselected
RAM Data
Read
WRITE Data
Write
NOTES:
1. H = High, L = low, X = Don't Care
2. DATAoUT changes when CLK retums high.
DC ELECTRICAL CHARACTERISTICS
(VEE = -4.5V, RL = 50Q to -2.0V, TA = 0 to + 85°C, airflow exceeding 2m/sec)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. (B)
TYP.(1)
MAX. (A)
UNIT
VOH
Output HIGH Voltage
\'IN = VIHA or V ILB
-1025
-955
-880
mV
VOL
Output LOW Voltage
\'IN = VIHA or V ILB
-1810
-1715
-1620
mV
VOHC
Output Threshold HIGH Voltage
\'IN
= VIHB or VILA
-1035
-
-
mV
VOLC
Output Threshold LOW Voltage
-
-
-1610
mV
\'IH
Input HIGH Voltage
\'IN = VIHB or VILA
Guaranteed Input Voltage High/Low
for All Inputs
-1165
-
-880
mV
\'IL
Input LOW Voltage
-1810
-1475
mV
-
Guaranteed Input Voltage High/Low
for All Inputs
IIH
Input HIGH Current
IlL
Input LOW Current
\'IN = VILB
lEE
Supply Current
All inputs and outputs open
\'IN = VIHA
~
0.5
-
Others
-50
-
-180
-110
cg
-
Others
-
220
110
170
~A
~A
mA
NOTE:
1. Typical parameters are specified at VEE = -4.5V, TA = + 25°C and maximum loading.
LOAD CONDITION
INPUT PULSE
Test Circuit
Vee (GND)
-.0'
-1.7V---~ ~
~%
-0.9V
30pF*
~ ~_2_00_YO_ _
tR =tF
-2.0V
·Includes probe and jig capacitance.
S12-39
= 2.0ns typo
IDT100496LL HIGH-SPEED BICMOS
ECL STATIC RAM 64K(16Kx 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VEE = -45V +SYMBOL
PARAMETER (1)
= 0 to
5% TA
+85°C air flow exceeding 2m/sec)
IDT100496LL13
MIN.
MAX.
TEST CONDITION
IDT100496LL15
.
MIN.
MAX.
UNIT
READ CYCLE GATED BY ADDRESS(2)
tCYC
t M (3)
Cycle Time
-
13
Address Access Time
-
tWL
Clock Low Pulse Width
-
tWH
Clock High Pulse Width
tSA
. Setup Time for Address
tHA
Hold Time for Address
tOH
Data Out Hold froniClock High
t OR(3.4)
Data Out Ready from Clock High
3
-
-
':'~':"
_it:~:::}10
-
. tM (max) - tOR (max).
READ CYCLE GATED BY ADDRESS
~--------------tCYC--------------~
OUTPUT
LATCH OPEN
ClK
--~~---------tWH--------~
ADDR
DATA
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
--------~----+,
. tDH
RISE/FALL TIME
SYMBOL
PARAMETER (1)
TEST CONDITION
tR
Output Rise Time
tF
Output Fall Time
-
-
S12-40
IOT100496
TYP.
MIN.
I
1
2
2
I
I
MAX.
UNIT
-
ns
ns
IDT100496ll HIGH-SPEED BICMOS
ECl STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER(1)
(VEE = -4.5V ± 5%, TA = 0 to
+ 85°C, air flow exceeding 2m/sec)
IDT100496lL13
MIN.
MAX.
TEST CONDITION
IDT100496LL15
MIN.
MAX.
UNIT
READ CYCLE GATED BY CHIP SELECT (2)
tCYC
Cycle Time
-
13
t Acsl 3)
Chip Select Access Time
-
tWL
Clock low Pulse Width
-
tWH
Clock High Pulse Width
-
tscs
Setup Time for Chip Select
-
t HCS
Hold Time for Chip Select
-
toH
Data Out Hold from Clock High
t oR(3.4)
Data Out Ready from Clock High
-
3
15
-
-
5
ns
-
3
ns
-
12
-
1
-
ns
':;:::;:;::"
.:.))::::::::::::;:::\::
10 . :',
-
.·::t?:;:::\::::):!S
:0::;;::::;::::::.
2
-
ns
'::::rcr
0
-
ns
0
4
0
4
ns
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. Read Cycle is gated by Address when tscs < tWL so that the access begins at the falling edge of Chip Select.
3. Access time is the larger of t ACS or tSCS+toR'
4. tOR (max) is specified when all other gating conditions have been satisfied, specifically when tscs > tACS (max) - tOR (max).
14-------- tcye - - - - - - - - . . /
OUTPUT
LATCH OPEN
ClK
--~~-----tWH----~
tscs
DATA
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
S12-41
ns
-
:J::::::::::)%::.
.::'i>:::g:::)/:
READ CYCLE GATED BY CHIP SELECT
ns
IDT100496LL HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIn
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER(1)
-
(VEE = -4.5V + 5%, TA = 0 to +85°C, air flow exceeding 2m/sec)
TEST CONDITION
1DT100496LL13
MIN.
MAX.
IDT100496Ll15
MIN.
MAX.
UNIT
READ CYCLE GATED BY CLOCK(2)
tCYC
t AcLK(3)
Cycle Time
tWL
Clock Low Pulse Width
tWH
Clock High Pulse Width
tOH
Data Out Hold from Clock High
t OR(3.4)
Data Out Ready from Clock High
Clocked Access Time
-
13
-
3
.. ,,::::,.
.:«:<:\:/:
-
~'.
19::::}::"
.)::9.\:):::
·':tf
-
15
-
ns
10
-
12
ns
-
3
-
ns
12
ns
0
-
4
0
4
ns
NOTES:
1.. Input and Output reference level is 50% point of waveform.
2. Read Cycle is gated by Address when tSA < tWL so that the access begins at the falling edge of Clock.
3. Access time is the larger of t ACLK or tWL + tOR.
4. tOR (max) is specified when all other gating conditions have been satisfied, specifically when tWL > tAcLK(max) - tOR (max).
READ CYCLE GATED BY CLOCK
104-------CLK
tCYC -------~
OUTPUT
LATCH OPEN
-~~-----tWH-----~
ADDR
DATA
OUT
PREVIOUS
CYCLE DATA
CURRENT
CYCLE DATA
S12-42
ns
IDT100496lL HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
PARAMETER(1)
SYMBOL
(VEE
= -4.5V ± 5%, TA = 0 to
TEST CONDITION
+85°C, air flow exceeding 2m/sec)
IDT1 00496lL13
MAX.
MIN.
IDT100496LL15
MIN.
MAX.
UNIT
WRITE CYCLE (2)
t cvc
Cycle Time
tAW (3)
Write Access Time
-
t A01 (4)
Write Data Access Time
-
-
tWL
Clock low Pulse Width
-
3
Clock High Pulse Width
-
10
:::::"'~:m::y::::,(~\:' '
-
1
(\,:;;:::
tSWE
Set-up Time for Write Enable
tSA
Set-up Time for Address
-
tso
Set-up Time for Data In
t HCS
Hold Time for Chip Select
t HWE
Hold Time for Write Enable
tHA
Hold Time for Address
1:,,':~\:,
;::j;::;::'::\':{),
"::'2
-
2
ns
5
ns
3
-
ns
-
12
-
ns
1
ns
-
1
-
1
-
2
-
,<{:;:'\\::: -
Set-up Time for Chip Select
::\:,::::':'~~:::):
ns
5
:t:·:::(~~§}?
tscs
,::::\~~,::::::~:(
-
-
:/)\9.:
tWH
-
15
-
13
1
2
2
ns
ns
ns
ns
ns
ns
2
2
ns
Hold Time for Data In
tHO
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. Data Hold t OH and Data Ready tOR are the same as for Read Cycle.
3. Access time is the larger of tAW or t SWE + tOR'
4. Access time is the larger of t AOI or t so+ tOR,
5. tOR (max) is specified when all other gating conditions have been satisfied, specifically when t so> t AOI (max).: t DR (max) and t SWE > t Aw<>OOOQQO(
CYCLE 2
ADDRESS
XX>QQ(
CYCLE 1
DATA
X><><>OOQQ(
OUTP~;E~TCH
CIT
DATAoUT
/
OUTPUT
DISABLE
OUTPUT LATCH
HELD
'\
OUTPUT DISABLE
(No Write Data 2)
S12-68
/
IDT10498 AND 1DT100498 HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16Kx 4-BIT) WITH CONDITIONAL WRITE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
Do
CS
Dl
D2
D3
~
OLE
A 13
A12
All
AlO
VEE
00
01
Vee
Vee
O2
Al
As
As
A7
As
A2
A3
A5
A4
03
Ao
DIP
TOP VIEW
(400mil)
S12-69
._-----_._-_._-_. - - - - - -
~
Integrated Device lechnology. Inc.
ADVANCE
INFORMATION
IDT 10504
IDT 100504
HIGH-SPEED BiCMOS
ECl STATIC RAM
256K (64K x 4-BIT)
FEATURES:
DESCRIPTION:
• 65,536-words x 4-bit organization
The IDT10504 and IDT100504are 262,144-bit high-speed
SiCEMOS ™ ECl static random access memories organized as
64K x 4, with inputs and outputs fully compatible with ECl-10K and
ECl-100K levels, respectively.
Available with address access times as fast as 12ns, this device
exhibits a typical power consumption of only 600mW. It offers the
advantages of low-power operation, without sacrificing speed, by
integrating a dense high-speed CMOS static RAM with internal
level conversion. This allows the designer to reduce package
count in an ECl system without increasing either power dissipation or access time.
Designed for very high-speed applications, the IDT10504 and
IDT1 00504 offer open emitter outputs and separate data input and
output, as well as extremely fast access times. The address access
time of 12ns assures that operation of this BiCEMOS part will be as
fast as with less dense parts requiring external address decoding.
The devices are fabricated using lOT's high-performance, highreliability BiCEMOS technology. Operating power dissipation is
extremely low compared with most ECl-compatible bipolar devices, lowering power supply and cooling requirements.
• Address access time: 12/15ns (max.)
• low power dissipation: 600mW (typ.)
• Fully compatible with ECl logic levels
• Separate data input and output
• JEDEC standard through-hole and surface mount packages
• Military version fully compliant to Mll-STD-883, class S.
LOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
DECODER
262.144-BIT
MEMORY ARRAY
A 15
Do
SENSE AMPS
AND READIWRITE
CONTROL
Dl
D2
D3
WE
CS
("l,
BiCEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-8004/-
S12-70
--------------------------------
IDT7MC4005 256K (16Kx 16) CMOS STATIC
RAM DUAL SIP MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
Do
'CS
D1
NC
NC
wr=
D2
D3
A 15
00
A14
A 13
°1
Vee
03
A12
VEE
A11
A10
Ao
A9
A1
A2
A3
A4
As
A7
As
Vee
°2
A5
DIP
TOP VIEW
(400mil)
S12-71
t;)
Integrated Device'JechnoIosy. Inc.
ADVANCE
INFORMATION
lOT 10506LL
lOT 100506LL
HIGH-SPEED SiCMOS
ECl SELF-TIMED STATIC
RAM 256K (64K x 4-SIT)
FEATURES:
DESCRIPTION:
• 65,536-words x 4-bit organization
• Self-Timed, with latches on Inputs and outputs
The IDT1 0506LL and IDT1 00506LL are 262,144-bit high-speed
BiCEMOS ™ ECL static random access memory organized as
64K x4, with Inputs and outputs fully compatible with ECL-10Kand
ECL-100K levels, respectively. These devices have on-board selftimed circuitry to relax control timing, providing easier design and
improved system level cycle times.
Clocked latches on inputs and outputs, and the self-timed write
operation, provide enhanced system performance over conventional RAMs by removing the need to control any write pulse width,
and relaxes timing of write enable (WE). Combined with address
access times as fast as 12ns, these devices allow cycle times as
fast as 15ns.
The IDT10506LL and IDT100506LL are fabricated using lOT's
high-performance, high-reliability BiCEMOS technology. They
offer the advantage of low-power operation without sacrificing
speed by integrating a dense, high-speed CMOS static RAM and
logic with internal level conversion. Power supply and cooling
requirements are reduced, while the fast access time assures that
operation of BICEMOS parts will be as fast as with less dense parts
requiring external address decoding.
• Cycle time 15/18 ns
• Address access time: 12/15 ns (max.)
• Low power dissipation: 800mW (typ.)
• Fully compatible with ECL logic levels
• Separate data input and output
• JEDEC standard through-hole and surface mount packages
FUNCTIONAL BLOCK DIAGRAM
Vcc
262.144-BIT
MEMORY ARRAY
Vee
'----t------If--t------I
B
NB
ClK ~~~-+----~-+------------------------~----------------~
CO<
* HOLD/opEN'
BiCEMOS is a trademark of Integrated Device Technology. Inc.
COMMERCIAL TEMPERATURE RANGE
©
JANUARY 1989
1989 Integrated Device Technology. Inc.
DSC-8013/-
S12-72
1DT10506Rl HIGH-SPEED BiCMOS ECl
SELF-TIMED STATIC RAM 256K (64Kx 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
LOGIC SYMBOL
Ao
Al
A2
A3
A4
A5
AS
A7
As
Ag
00
01
O2
we
Do
VBB
Dl
D2
D3
CO<
00
01
A14
A 13
Vee
Vee
A12
O2
All
AlO
Ag
elK
A 15
VEE
03
AlO
All
A12
A 13
A14
A 15
ClK
CS
Ao
03
CO<
Al
A2
A3
A4
we Cs
As
A7
As
A5
DIP
TOP VIEW
(400mil)
S12-73
- - - - - _ . _ - - - - - _..__ ..
_._..
__
.. ... _-------_._ .._......
,
---------
t;)
Intesrated Device1echnology.1nc.
HIGH-SPEED BiCMOS
ECl SELF-TIMED STATIC
RAM 256K (64K x 4-BIT)
ADVANCE
INFORMATION
lOT 10506RL
lOT 100506RL
FEATURES:
DESCRIPTION:
• 65,536-words x 4-bit organization
• Self-Timed, with registers on inputs and latches on outputs
The IDT10506Rl and IDT100506 are 262,144-bit high-speed
BiCEMOS ™ ECl static random access memory organized as
64K x 4, with inputs and outputs fully compatible with ECl-10K and
ECl-100K levels, respectively. These devices have on-board selftimed circuitry to relax control timing, providing easier design and
improved system level cycle times.
Clocked registers on inputs and latches on outputs, and the selftimed write operation, provide enhanced system performance over
conventional RAMs by removing the need to control any write
pulse width, and relaxes timing of write enable (WE). Combined
with address access times as fast as 12ns, these devices allow
cycle times as fast as 15ns.
The IDT10506Rl and IDT100506 are fabricated using lOT's
high-performance, high-reliability BiCEMOS technology. They
offer the advantage of low-power operation without sacrificing
speed by integrating a dense, high-speed CMOS static RAM and
logic with internal level conversion. Power supply and COOling
requirements are reduced, while the fast access time assures that
operation of BICEMOS parts will be as fast as with less dense parts
requiring external address decoding.
•
•
•
•
Cycle time 15/18 ns
Address access time: 12/15 ns (max.)
low power dissipation: 800mW (typ.)
Fully compatible with ECl logic levels
• Separate data input and output
• JEDEC standard through-hole and surface mount packages
FUNCTIONAL BLOCK DIAGRAM
Vee
262.144-BIT
MEMORY ARRAY
VBB
~--~------~--~------~
B
CLK --~~~~--~~~----------------------~~----------------~
CLK-~>--
* H0 LD/Ql5E1\j
BiCEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
© 1989 Integrated Device Technology, Inc.
ose-8014/-
812-74
1DT10506Rl HIGH-SPEED BICMOS ECl
SELF-TIMED STATIC RAM 256K (64K x4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN, CONFIGURATION
LOGIC SYMBOL
M
'C'S
Ao
Al
A2
A3
A4
A5
Ae
A7
AS
Ag
A10
All
A12
A13
A14
A15
Do
Vee
ClK
01
crR
A 15
00
O2
01
03
00
01
A14
A 13
Vee
Vee
A12
VEE
O2
All
A 10
Ag
O2
03
Ao
03
As
A7
A6
Al
A2
A3
A4
elK CO< WE 'C'S
As
DIP
TOP VIEW
(400mil)
S12-75
t;J
IntegratedDevlce~Inc.
HIGH-SPEED SiCMOS
EGl STATIC RAM
256K (64K x 4-SIT)
WITH SYNCHRONOUS WRITE
ADVANCE
INFORMATION
lOT 10507
lOT 100507
FEATURES:
DESCRIPTION:
• 65,535-words x 4-bit organization
The IDT10507 and IDT100507 are 262,144-bit high-speed
BiCEMOS ™ ECl static random access memories organized as
64K x 4, with inputs and outputs fully compatible with ECl-1 OK and
ECl-100K, respectively.
Available with address access times as fast as 12ns, these
devices exhibit a typical power consumption of only 800mW. They
offer the advantages of low-power operation, without sacrificing
speed, by integrating a dense high-speed CMOS static RAM with
internal level conversion. This allows the designer to reduce
package count in an ECl system without increasing either power
dissipation or access time.
Designed for synchronous applications, the IDT10507 and
IDT100507 include Data Capture logic which allows very tight
specifications for Input Data Set-Up and Hold with respect to the
trailing edge of WE. This allows relaxed timing or a pipeline stage
in the datapath. An output latch with enable allows control of output
hold time. Note that when OLE is tied low, the IDT10507 functions
exactly as an IDT10504 assynchronous SRAM.
The devices are fabricated using lOT's high-performance,
high-reliability BiCEMOS technology. Operating power dissipation is extremely low compared with most ECl-compatible bipolar
devices, lowering power supply and cooling requirements.
• Address access time: 12/15 ns (max.)
• low power dissipation: 800mW (typ.)
• Fully compatible with ECl logic levels
• Internal Circuitry Allows Synchronous Write Operation
• Tight Input Data Set-Up and Hold Timing
• JEDEC standard through-hole and surface mount packages
LOGIC SYMBOL
Do Dl
D z D3
Vee
Ao
Ao
Al
Az
A3
A4
A5
Ae
A7
As
Ag
A10
All
A1Z
A13
A14
A15
~
FUNCTIONAL BLOCK DIAGRAM
00
•
01
•
Oz
•
•
A 15
262,144-BIT
MEMORY ARRAY
•
•
03
Do
SENSE AMPS
AND READ/WRITE
CONTROL
Dl
Dz
CS
Q[E"
D3
~
CS
CIT
*HOLD/OfSB\J
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology, Inc.
DSC-8015/-
S12-76
1DT10506Rl HIGH-SPEED BiCMOS ECl
SELF-TIMED STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
CS
NC
we
Do
oct:
Dl
D2
D3
A 1S
00
01
A14
A 13
Vee
Vee
A12
O2
All
A 10
Ag
NC
VEE
03
Ao
Al
A2
A3
A4
As
A7
Ae
As
DIP
TOP VIEW
(400mil)
S12-77
~
Integrated Device1echnoIogy. Inc.
HIGH-SPEED SiCMOS
ECl STATIC RAM
256K (64K x 4-SIT)
WITH CONDITIONAL WRITE
ADVANCE
INFORMATION
lOT 10508
lOT 100508
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
The IDT10508 and IDT100508 are 262,144-bit high-speed
BiCEMOS ™ ECl static random access memories organized as
64K x 4, with inputs and outputs fully compatible with ECl-1 OK and
ECl-100K, respectively.
Available with address access times as fast as 12ns, these devices exhibit a typical power consumption of only 800mW. They
offer the advantages of low-power operation, without sacrificing
speed, by integrating a dense high-speed CMOS static RAM
with internal level conversion. This allows the designer to reduce
package count In an ECl system without Increasing either power
dissipation or access time.
Designed for cache applications, the I DT1 0508 and IOT1 00508
include Data Capture logic which allows very tight specifications
for Input Data Set-Up and Hold with respect to the trailing edge of
WE. This allows relaxed timing or a pipeline stage in the datapath.
An output latch with enable allows control of output hold time. Note
that when OLE is tied low, the IDT10507 functions exactly as an
IDT10504 asynchronous SRAM. The devices also incorporate
logic to terminate the Write Operation very late in the cycle by
removing CE, providing more time for cache-hit decision logic.
The devices are fabricated using lOT's high-performance, highreliability BiCEMOS technology. Operating power dissipation
is extremely low compared with most ECl-compatible bipolar
devices, lowering power supply and cooling requirements.
65,535-words x 4-bit organization
Address access time: 12/15ns (max.)
low power dissipation: 800mW (typ.)
Fully compatible with ECl logic levels
Internal Circuitry Allows Synchronous Write Operation
Tight Input Data Set-Up and Hold Timing
JEOEC standard through-hole and surface mount packages
LOGIC SYMBOL
FUNCTIONAL BLOCK DIAGRAM
Vee
Ao
•
•
•
•
•
VEE
262.144-BIT
MEMORY ARRAY
A 15
Do
00
01
01
O2
O2
D3
03
~
CS
()[E
*OPEN/HOIJ)
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©
JANUARY 1989
1989 Integrated Device Technology. Inc.
DSC-8016/-
S12-78
- - - - - - - - - --- ----- -------.---
-----------------_._._----
IDT10498 AND IDT100498 HIGH-SPEED BiCMOS
ECl STATIC RAM 64K (16Kx 4-BIT) WITH CONDITIONAL WRITE
---~
CS
WE
Do
Dl
D2
D3
00
01
~
NC
A1S
A14
A13
A12
Vee
Vee
VEE
O2
03
Ao
Al
A2
A3
A4
--------
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
--.- .. - -.- .....
All
A10
Ag
As
A7
As
As
DIP
TOP VIEW
(400mil)
S12-79
__ .... _._._-
._..__ ._.
...
_-------------
Subsystems Modules
- - - _.... ... _---._-------------_._--._---_
--------------_._._--------
SUBSYSTEM PRODUCTS INTRODUCTION
A unique combination of resources and experience sets the
Subsystems Division apart from its competitors. lOT's advanced
technology, multiple manufacturing plants and the backing of sister divisions allow us to offer a diverse range of module products
quickly and cost-effectively. In addition, our capabilities are flexible enough to include standard and custom modules, as well as a
complete, self-contained, U.S.-based military device assembly
and module operation.
lOT's subsystems provide a modular approach which allows
designers to meet several important criteria needed in a modern
electronics system. These features include:
High Performance
High Reliability
High Density
Low Power
Quick Design Time
Ease of Manufacture
Competitive Cost
High-performance CMOS products in surface mounted packages are combined with thermally matched substrates to produce
very dense and highly reliable modules. Conventional pins are
then attached to these modules so that they can be plugged into a
circuit board in a conventional through-hole manner.
This process allows production of a Megabit static RAM in a
standard size dual in-line package several years before the available technology can produce a comparable monolithic device. In
addition, an application specific product can be manufactured that
could not be easily or cost-effectively produced as a monolithic device. These ASIC products can include error detection, parity, address latching or buffering and wide words (x16 and x32).
Complete memory systems, such as megabyte-size highspeed caches or writable control stores, can also be produced on a
single plug-in module. Systems can now be designed with the major memory portions supplied as a single fully-tested high density
component. This approach gives customers access to surface
mount technology without the need to invest in special design,
manufacturing and testing facilities.
TABLE OF CONTENTS
PAGE
CONTENTS
Subsystems Modules
lOT 7M134
lOT 7M135
lOT 7M137
IDT7M144
IDT7M145
lOT 7M203
IDT7M204
lOT 7M205
lOT 7M20S
IDT7MS24
IDT7MS5S
IDT7M812
IDT 7M912
lOT 7M824
IDT7M820
lOT 7M821
lOT 7M822
lOT 7M823
lOT 7M825
IDT7M826
lOT 7M827
lOT 7M828
lOT 7M856
IDT 7M4016
IDT7M4017
IDT7M6001
IDT7MS032
IDT7M6052
lOT 7MB624
IDT 7MB2001S
IDT7MB2002
IDT7MB4009
IDT7MB6036
IDT7MB6039
IDT7MB6040
IDT7MBS042
IDT7MBS043
IDT7MBS044
IDT7MBS049
IDT7MBS051
IDT7MC156
IDT7MC4001
IDT7MC4005
IDT7MC4018
IDT7MC4032
IDT7MP156
IDT7MP456
lOT 7MP564
IDT 7MP4008L
IDT7MPS025
lOT 8M612
lOT 8MS24
lOT 8MS28
lOT 8M656
lOT 8M824
64K (8K x 8) Dual-Port RAM ... , . .. . .. . .. . . . .. . . .. . . . . . . . .. .. . .. ..... .. . . . .... ....
128K (16K x 8) Dual-Port RAM ...................................................
256K (32K x 8) Dual-Port RAM ...................................................
64K (8K x 8) Dual-Port RAM. . .. . ... . . . .. . . . . . . ... . . . . . . . . ... . . . .... . .. . . . .... ....
128K (16Kx8) Dual-Port RAM ...................................................
CMOS Parallel In-Out FIFO. Module 2K x 9-Blt & 4K x 9-Blt ...........................
CMOS Parallel In-Out FIFO Module 2K x 9-Blt & 4K x 9-Blt ...........................
8K x 9 FIFO ...................................................................
16K x 9 FIFO ..................................................................
1 Megabit (64K x 16) CMOS SRAM .................................................
25SK (16K x 16) CMOS SRAM . . . . . .. .. . . . . . . . . . .. . . . . . .. . .. .. . .. .. . .. .. . . . .. . .. ...
512K (64K x 8) CMOS SRAM ...... ,........ ... ..... ...............................
512K (64K x 9) CMOS SRAM .............................................. ........
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family. . . . . . . . . . . . . ..
128K x 8 SRAM w/Latched Address, Latched Data In, Latched Data Out ...............
128K x 8 SRAM w/Latched Address, Registered Data In, Registered Data Out. . . . . . ....
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out.. . . . ........
128K x 8 SRAM w/Latched Address, Latched Data In, Registered Data Out ............
128K x 8 SRAM w/Reglstered Address, Registered Data In, Registered Data Out .......
128K x 8 SRAM w/Registered Address, Registered Data In, Latched Data Out. . . . . . . . ..
128K x 8 SRAM w/Registered Address, Latched Data In, Registered Data Out. . .... ....
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out. . . . . . . . . . . ..
256K (32K x 8-Blt) CMOS Static RAM .............................................
4 Megabit (25SK x 16) CMOS SRAM ................................................
2 Megabit (64K x 32) CMOS SRAM . .. . .. . . . . . . . . . . . . . . . . . . .. .. . .. . .. . . .. . . . .. .. . ...
Dual, Multiplexed 16K x 20 SRAM ...................... ............................
16K x 32 High-Speed Writable Control Store W/SPC™ .................................
4K x 80 Writable Control Store Static RAM Module With On-BOard Sequencer..............
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ....................................
8K x 36 FIFO Module.............. ............................ ......... .........
36 to 9 BIFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2 (16K x 1S) CMOS Static RAM FR-4 Dip Module .....................................
128K x 16 Shared Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU. . . . .. .. . . . . . . . . . . . ..
Dual (16K x 64) Data/Instruction Cache Module For General CPUs .......... .............
8K x 112 High-Speed Writable Control Store W/SPC™ .................................
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU. . . . . .... . . . . . . . . . . . ..
Dual (4K x 64) Data/Instruction Cache Module for IDT79R3000 CPU. . . . . . . . . . . . . . . . . . . . ..
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU
(Multiprocessor) (S14-6) ........ ....... ......... ............ ......... .........
Dual (8K x 64) Data/Instruction Cache Module for IDT79R3000 CPU (Multiprocessor) ........
25SK x 1 CMOS SRAM (Ceramic SIP) . ....... .. ...... ..................... . .........
1 Megabit (1024K x 1) CMOS SRAM w/Separate i/O (Ceramic SIP) ..... ..................
25SK (16K x 6) CMOS Static RAM Ceramic Dual SIP Module.......... ......... .........
64K x 6 CMOS Static RAM Ceramic SIP Module............................ . .........
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ....................................
25SK (256K x 1) CMOS SRAM (Plastic SIP) ..........................................
256K (64K x 4) CMOS SRAM (Plastic SIP) ...........................................
80K (16Kx 5) CMOS SRAM (Plastic SIP) ..........................................
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ......................................
512K (64K x 8) Synchronous SRAM (Plastic SIP) . . . . . .. . . . ..... . . ... . .. . . . . . . . ... . . ...
512K (32K x 16) CMOS SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1 Megabit (64K x lS) CMOS SRAM ...............................................
128K (SK x lS) CMOS SRAM ....... ....... ... ..... ...................... . ........
256K (16K x lS) CMOS SRAM ...... ............................ ..... .............
1 Megabit(12SK x 8) CMOS SRAM ...............................................
13-125
13-125
13-135
13-142
13-142
13-146
13-146
13-157
13-157
S13-1
S13-8
S13-1.7
S13-17
13-168
13-172
13-175
13-178
13-181
13-184
13-187
13-190
13-193
13-63
S13-23
S13-29
S13-35
S13-41
S13-55
13-1
S13-76
S13-85
S13-92
S13-98
S13-105
S13-111
S13-117
S13-131
S13-133
S13-135
S13-138
S13-140
S13-146
S13-152
S13-158
S13-164
S13-171
S13-177
13-29
S13-183
S13-189
13-92
13-92
13-99
13-99
13-107
TABLE OF CONTENTS (CON'T.)
CONTENTS
Subsystems Modules
lOT 8M8S6
lOT 8MP612
lOT 8MP624
lOT 8MP656
lOT 8MP628
lOT 8MP824
PAGE
2S6K(32Kx8) Low-PowerCMOSSRAM ..........................................
512K (32K x 16) CMOS SRAM (Plastic SIP) ........................................
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) ....................................
256K (16K x 16) CMOS SRAM (Plastic SIP) ........•••.•.•..............••••..•...•••
128K (8K x 16) CMOS SRAM (Plastic SIP) ...•..........•...•.•....••...............•
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ....................................
13-113
13-74
13-74
S13-195
S13-195
13-86
-~----------.-.---
Integrated DeviceTechnology. Inc.
.. --..- . - . - - - - - - - - - - - - - - - - - - - - - -
1 MEGABIT CMOS
STATIC RAM MODULE
lOT 7M624S
FEATURES:
DESCRIPTION:
• High-density 1024K-bit CMOS static RAM module
• Customer-configured to 64K x 16, 128K x 8 or 256K x 4
The IDT7M624 is a 1024K-bit high-speed CMOS static RAM
constructed on a multi-layered ceramic substrate using 16
IDT7187 64K x 1 static RAMs in leadless chip carriers. Making four
chip select lines available (one for each group of 4 RAMs) allows
the user to configure the memory into a.64K x 16, 128K x 8 or 256K x
4 organization. In addition, extremely high speeds are achievable
by the use of IDT7187sfabricated in IDT's high-performance, highreliability technology, CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides the
fastest 64K static RAMs available.
The IDT7M624 is available with access times as fast as 25ns
commercial and 35ns military temperature range, with maximum
operating power consumption of only 12.3W (significantly less if
organized 128K x 8 or 256K x 4). The module also offers a standby
power mode of 5.7W (max.) and a full standby mode of 1.7W
(max.).
The IDT7M624 is offered in a 40-pin, 900 mil center sidebraze
DIP to take advantage of the compact IDT7187s in lead less chip
carriers.
All inputs and outputs of the IDT7M624 are TTL-compatible and
operate from a single 5V supply. (NOTE: Both GND pins need to be
grounded for proper operation.) Fully asynchronous· circuitry is
used, requiring no clocks or refreshing for operation, and providing
equal access times for ease of use.
Alii DT military module semiconductor components are compliant with the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.
• Fast access times
- Military: 35ns (max.)
- Commercial: 25ns (max.)
• Low power consumption
- Active: 4.8W (typ. in 64K x 16 organization)
- Standby: 1.6mW (typ.)
• Utilizes 16 IDT7187 high-performance 64K x 1 CMOS static
RAMs produced with IDT's advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in 40-pin, 900 mil center sidebraze DIP, achieving
very high memory density
• Pin-compatible with IDT7M656 (256K RAM module)
•
•
•
•
Single 5V(±10%) power supply
Dual GND pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
Modules available with semiconductor components compliant to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters
PIN CONFIGURATION
(llGND
_
D 15
CS(12-15)
D4
Vcc
DI1
CS(6-11)
Do
Ao
A 13
DlO
A12
Dl
All
AlO
D9
Ag
D2
As
A7
Ds
CS(0-3)
D3
GND(1)
~
AI
D14
A2
D5
A3
A4
D13
A5
D6
A6
A14
D12
CS(4-7)
D7
A15
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
AO-16
AO-AI6 --~~~-------,~-~--~--~----,
Address
DO- 15
Data InpuVOutput
CS
Chip Select
~
Write Enable
Vec
Power
GND
Ground
CSO- 3
-+f+-
25
tAW
Address Valid to End of Write
22
::::;:·:::r:·-
t AS
Address Set-up Time
.:::)??
35
30
45
40
twp
Write Pulse Width
2
20 ::::::::::.::::: -
20
-
25
-
30
tWR
Write Recovery Time
o .:i/(;:: -
0
-
0
-
0
tow
Data Valid to End of Write
15·:::·::::\::: -
20
20
-
25
S13-3
55
-
65
-
ns
50
-
55
ns
50
-
55
35
-
40
0
-
0
25
30
5
10
ns
ns
ns
ns
ns
ns
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1
(1,2)
tRC(S)
-----------~~......._ _
ADDRESS
tAA -------~.'
DATAoUT
PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.2 (1,3)
~--------
tRC,(S)
----------~
CSxx
t ACS
-----......,
DATA OUT
DATA VALID
HIGH IMPEDANCE
VCC SUPPLY
CURRENT
~~---:~~~~~~~~~~~~
NOTES:
WE is high for READ cycle.
2. CSxx is low for READ cycle.
3. Address valid prior to or coincident with CSxx transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled. not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
1.
S13-4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
ADDRESS
twc
-----.....
- - - /K
)(
tAW
~
)1"
\..
- tAS
....
t
,
-t
tOHZ
(7)
tWR
WP
(6)-
WHZ
(6)
f--
tow-i
~«(4)'" .) . . . ~
(4)
DATA OUT
________________~~------~~t=---------tow_
DATA IN
r-
j~
tOH
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)
twc
ADDRESS
~
----I
)K
K
tAw
~V
':\..
_ t AS
tWR
tcw
tow
DATA IN
"
I""
tOH
""
'I
NOTES:
1.' VIr=. or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low ~.
3. tWR is measured from the earlier of ~ or wr; going high to the end of write cycle.
4. During this period, 110 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the
low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
wr:.
S13-5
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
(TA= +25°C, f = 1.0MHz)
CS xx
WE
Standby
H
X
High Z
Standby
C IN
Input Capacitance
Read
L
H
DATA OUT
Active
C OUT
Output Capacitance
Write
L
L
High Z
Active
MODE
OUTPUT
SYMBOL
POWER
TEST
TYP,
UNIT
V IN = OV
130
pF
VOUT= OV
35
pF
CONDITIONS
NOTE:
1. This parameter is sampled and not 100% tested.
IDT7M624
64Kx 16 CONFIGURATION
Ao -A 15 - - - Ao -A15 - -_ _- - - - - _ - - - -.......- - - - - - .
CSO- 3
CS4 - 7
CS
~--~--------~~======~======~======~
eS a- 11
NOTE:
All chip selects tied together since, in a by 16 configuration, all chips are either on or off.
IDT7M624
128K X 8 CONFIGURATION
Do
Dl
D2
D3
D4
D5
D6
D7
Ao-A15 - - - - - - - - - - - - - - - - - Ao-A15
WE----'
Vcc - - - - ,
eS O- 3
eS 4- 7
eS a- 11
eS 12- 15
NOTE:
The chip selects are tied together in groups of two. The decoder uses the new higher order address pin (A 16 ) to determine which ofthe two banks of memory
are enabled.
S13-6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
IDT7M624
256K X 4 CONFIGURATION
A o -A 15 ------------------------------------
WE----...J
CSo-3
Vcc - - - ,
Vcc
cs,6 AOB
A18 OOB 0lB 02B 03B
CS S- 11
r:~
I I
II
----'r
I
CS1A AOA AlA 00
....A
__0_l_A_0_2A
___0_3_A_G_N_D
______
L . . . - -- - - - - - I
12 15
CS -
.
Do
NOTE:
Each chip is now controlled by the two higher order address pins A 16 and A 17.
ORDERING INFORMATION
IDT
xxxxx
A
999
A
A
Device Type
Power
Speed
Package
Process/
Temperature
Range
y:,"k
'------------------~
~
______________________
~
Commercial (O°C to
C
Sidebraze DIP
25
30
35
Commercial Only
Commercial Only
} Spe"" In Nana",,,,,,d,
45
55
65
'--------------------------------~S
L--------------------------------------J
S13-7
7M624
+ 70°C)
Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STD-883, Class B
Standard Power
1 Megabit (1024K-Bit)
(;)
Integrated Device1echnology.1nc.
lOT 7M656L
256K CMOS STATIC
RAM MODULE
FEATURES:
DESCRIPTION:
• High-density 256K-bit CMOS static RAM module
• Customer-configured to 16Kx16, 32Kx8 or 64Kx4
• Fast access times
- Military: 20ns
- Commercial: 15ns
• Low power consumption
- Active: 3.2mW (typ.) (in 16K x 16 organization)
- Standby: 0.16mW (typ.)
• Utilizes 16 IDT6167s high-performance 16K x 1 CMOS static
RAMs produced with lOT's advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder reflow
process
• Offered in 40-pin, 900 mil center sidebraze DIP, achieving very
high memory density
• Single 5V (±10%) power supply
• Dual Vcc and GND pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Module available with semiconductor components compliant
to MIL-STD-883, Class B.
The IDT7M656 is a 256K-bit high-speed CMOS static RAM constructed on a multilayered ceramic substrate using 16 IDT6167
(16Kx1) static RAMs in leadless chip carriers. Making 4 chip select
lines available (one for each group of 4 RAMs) allows the user to
configure the memory into a 16Kx16, 32Kx8 or 64Kx4 organization.
In addition, extremely high speeds are achievable by the use of
IDT6167s fabricated in lOT's high-performance, high-reliability
technology, CEMOS. This state-of-the-art technology, combined
with innovative circuit· design techniques, provides some of the
fastest 16K static RAMs available.
The IDT7M656 is available with access times as fast as 15ns
commercial and 20ns military temperature range, with maximum
operating power consumption of only 7.9W (significantly less if
organized 32Kx8 or 64Kx4). The RAM module also offers a
maximum standby power mode of 3.0W and a maximum full
standby mode of 176mW.
The IDT7M656 is offered in a high-density 40-pin, 900 mil center
sidebraze DIP to take full advantage of the compact IDT6167s in
leadless chip carriers.
All inputs and outputs of the IDT7M656 are TTL-compatible and
operate from a single 5V supply. (NOTE: Both Vcc pins need to be
connected to the 5V supply and both GND pins need to be
grounded for proper operation.) Fully asynchronous circuitry is
used requiring no clocks or refreshing for operation, and providing
equal access and cycle times for ease of use.
All lOT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-883,
Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
PIN CONFIGURATION
*GNO
FUNCTIONAL BLOCK DIAGRAM
Vcc*
011
DIS
CS(12-1S)
04
~(BOT)
Ao-AI3----~~~--------~--------~---------,
~-TOP----~~--------~--------H-------~
CSO-3----++~--------~+-------~~------~
CS(6-11)
DO
Ao
AI
A13
014
A2
A12
Os
01
010
A3
All
A l0
Og
Ag
A4
013
As
06
A6
WE"(TOP)
0 12
WE"-BOT--~~~======~======~~======~
CS8_11--~+-.-Hf--------""-++-------~++-------~
O2
A8
A7
o
~(0-3)
CS(4-7)
07
03
*Vcc
GNO*
DIP
TOP VIEW
PIN NAMES
Axx
CS xx
1. For module dimensions, please refer to module drawing M6 in the
packaging section.
~xx
Addresses
Chip Selects
Write Enable
Dxx
Vcc
GNO
OATAIN/OUT
Power
Ground
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-7012/1
S13-8
_._--_._
..
_---------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED DC OPERATING CONDITIONS
COMMERCIAL
RATING
SYMBOL
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
50
50
mA
-0.5 to +7.0
-0.5 to +7.0
DC Output Current
-55 to +125
MIN.
TYP.
MAX.
Vce
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
ViH
Input High Voltage
2.2
-
6.0
V
ViL
Input Low Voltage
-0.5(1)
-
O.S
V
SYMBOL
V
°C
PARAMETER
UNIT
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
°C
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vee= 50V +10%
TA = -55°C to + 125°C and O°C to + 70°C)
TEST CONDITIONS
PARAMETER
MIN.
IDT7M656L
TYP.(l)
MAXJ3)
UNIT
MAX.<4)
Ilu l
Input Leakage Current
Vce = 5.5V, VIN = OV to Vee
-
-
20
20
IILOI
Output Leakage Current
CS = VIH , VOUT = OV to Vee
-
-
20
20
J.lA
Icex16
Operating Current in X16 mode
CS xx = VIL , Output Open, Vee = 5.5V, f=fMAX
-
640
12S0
1920
mA
ICCX8
Operating Current in XS mode
CS xx = VIL , Output Open, Vee= 5.5V, f=fMAX
-
420
S40
1360
mA
Iccx4
Operating Current in X4 Mode
CS xx = VIL , Output Open, Vee = 5.5V, f=fMAX
-
310
620
10S0
mA
ISB
Standby Power Supply Current
CS xx ~Vee{TTL Level), Vee =5.5V, Output Open
-
200
400
SOO
mA
ISBl
Full Standby Power Supply
Current
CS xx ;;:: Vee -0.2V (CMOS Level
VIN ~ Vee -0.2V or < 0.2V
VOL
Output Low Voltage
10L =SmA
Output High Voltage
VOH
10H =-4mA
NOTES:
1. Vcc = 5V, TA=+25°C
2. ISBl max. at commercial temperature = 5.0mA
3. tAA = 25, 35, 55, 65ns
4. tAA = 15, 20ns
CIN
MODE
CS
WE
OUTPUT
POWER
H
X
HighZ
Standby
Read
L
H
DATA OUT
Active
Write
L
L
HighZ
Active
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
PARAMETER(l)
CONDITIONS
ViN = OV
160
0.4
0.4
V
-
2.4
V
rnA.
DATA OUT
MAX.
UNIT
200
pF
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
5V
(TA= +25°C, f = 1.0MHz)
Input Capacitance
-
15(2)
AC TEST CONDITIONS
Standby
SYMBOL
0.032
2.4
TRUTH TABLE
CAPACITANCE
-
J.lA
~
2550
COUT (2) Output Capacitance
60
pF
Vour= OV
NOTE:
1. This parameter is determined by device characterization, but is not
100% tested.
2. For each output, 16K x 16 mode.
5V
4S00
DATAoUT
30pF*
Figure 1. Output Load
~
2550
4800
5pF*
Figure 2. Output Load
(for t HZ ' t LZ • twz and tow)
* Including scope and jig.
S13-9
... _.. _.- .. - ....- ... - ....._-_ ..._-----_._ .. _ - - ......
_--_._--------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
AC ELECTRICAL CHARACTERISTICS
SYMBO
PARAMETER
(Vcc = 5V ±10%, All Temperature Ranges)
IDT7M656L15 IDT7M656L20 IDT7M656L25 IDT7M656L35
(COM'L ONLy)
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
MIN.
IDT7M656L55
MIN.
IDT7M656L65
MAX.
MIN.
MAX.
UNIT
READ CYCLE
-
25
-
35
-
55
-
65
-
20
25
-
65
ns
35
-
55
25
-
35
20
-
55
-
65
ns
-
5
-
5
-
5
-
5
-
ns
) (:::~)::
-
5
-
5
-
5
-
5
-
ns
:::::::~:.
15
-
15
-
20
-
40
-
40
. ns
-:'ii:ii:: :.:':;.'~
-
0
-
0
-
0
-
0
-
ns
~;.g\\ m?_
20
-
25
-
35
-
55
-
65
ns
25
35
-
65
-
55
-
ns
45
45
-
ns
-
5
-
ns
20
30
40
-
ns
0
-
0
-
55
5
-
55
25
-
0
-
ns
15
-
20
-
25
30
ns
t RC
Read Cycle Time
15
-
tM
Address Access Time
15
t ACS
Chip Select Access Time
-
tOH
Output Hold from
Address Change
3
- ;:!: : ~!: .: : : :
tLZ
Chip Selection to
Output in Low Z
5
-
tHZ
Chip Deselect to
Output in High Z
-
10 :\>
t pu
Chip Select to
Power Up Time
0
tpD
Chip Select to
Power Down Time
-
?9
;::,g:i})(
15
.:::"
ns
:t:n::,::::;
WRITE CYCLE
r}:;::
i::t.
..... ,,;::::::::;::
t AS
Address Set-up Time
2
twp
Write Pulse Width
13
tWR
Write Recovery Time
o }::)( &
0
-
tDW
Data Valid to End of Write
13:::'::::::::::L
15
-
tDH
Data Hold Time
5
tly'
Write Enable to
Output in HIGH Z
twv
Output Active from
End of Write
twc
Write Cycle Time
15
tcw
Chip Select to End of Write
15
tAW
. Address Valid to End of Write
15
::::;::::~\(
:::::;:...
~:::::
"';':'::::::::i/
20
20
20
2
17
20
30
35
5
5
35
0
ns
5
-
5
-
-
5
-
5
-
-:::;;'·:.1:11:::(/·
-
10
-
10
-
15
-
40
-
40
ns
&::::::::::::nw -
0
-
0
-
0
-
0
-
0
-
ns
{::/):>=-
513-10
5
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS
DATA OUT
(1,2)
-£
t
RC
(5)
-----------1~~""'-__
tAA ------------~.~'
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.2
DATA VALID
(1,3)
~---------------
t RC (5)
------------.j
CSxx
tLZ
DATAoUT
DATA VALID
_____ :~j_______~_teD=1'---_
HIGH IMPEDANCE
Vcc SUPPLY
CURRENT
~
NOTES:
1.
2.
3.
4.
5.
6.
WExx is High for READ cycle.
CSxx is low for READ cycle.
Address valid prior to or coincident with CSxx transition low.
Transition is measured ±500mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
For any given speed grade. operating voltage. and temperature. tHZ will be less than or equal to tLZ.
S13-11
--------------------
--"'-'
.
-_._._._-----------_ .. _----
_..
_--_
..__._--_ ..
_._--------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
ADDRESS
~--------------------tAw------------------~
tAS -----1~------------- tw~7) ------------~
----~-----------
~---------------------------
DATA OUT
DATA IN
____________________________________
~~-t-ow----------~~-----------------------
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3,5)
twc
ADDRESS
~K
)K
tAw
I - - - tAS
DATA IN
- '''"
/~
tWR
tcw
,
I'
tow
j.-
tOH
"fI
NOTES:
1. ~ or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low ~.
3. tWR is measured from the earlier of CS or ~ going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the ~ low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
S13-12
._----_._-----------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
DATA RETENTION CHARACTERISTICS
SYMBOL
VOR
leeDR
Nee= 50V +10%
TA = -55°C to +125°C and O°Cto +70°C)
MAX.
COM'L.
MAX.
MIL
UNIT
-
V
MIN.
TYP.
Vee for Retention Data
2.0
.01(2)
2.0(2)
Data Retention Current
-
6.0
.02(3)
3.0(3)
9.0
_.
-
ns
-
-
ns
TEST CONDITION
PARAMETER
CS xx ~ Vee - 0.2V
\'IN
teDR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
~
Vee - 0.2Vor ~ 0.2V
0
t Ae (4)
NOTES:
1. TA = +25°C.
2. at Vee = 2V
3. at Vee = 3V
4. t Ae = Read Cycle Time.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vce
S13-13
-
-
mA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
NORMALIZED TYPICAL PERFORMANCE CHARACTERISTICS
1.6
J
1.6
J
1.6
I,
Vee =4.5V
1.4
1.4
1.4
L
1.2
1.0
V
./'
/'"
1.0
0.8
0.6
4.5
....
1.2
/'
V
4.75
5.0
5.25
1
Vee =5.5V
TA= +25°C
0.8
Address Access Time vs.
Ambient Temperature
Supply Current vs.
Ambient Temperature
Supply Current vs. Voltage
5.5
0.6
-75
' '"
1.2
~
-25
1.0
'-
75
125
0.8
0.6
-75
~
V
~
""
-25
75
125
Vee (volts)
Stand-by-Power Supply
Current vs. Voltage
1.6
+A=
Stand-by-Power Supply Current
vs. Ambient Temperature
1.6
+2~oC /
1.4
Vee
,I
1.2
1.2
/
1.0
1.0
/
0.8
4.5
4.75
1000
"~'"
5.0
5.25
5.5
Vee (volts)
0.6
-75
-25
'L
~
25
TA (0C)
Address Access Time vs.
Capacitive Load
1.2
t=+2JOC
1.1
V
./
./
/
o
50
Capacitive Load (pf)
~
100
0.8
/
0.6
~5.5V
1.4
V
Full Stand-by Power Supply Current.
Data Retention Current vs.
Ambient Temperature
100
S13-14
10
~
75
1/
,
0.1
125
-50
o
50
TA (0C)
100
150
...
_._-_ .. _... _-._.
~--------------------------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
IDT7M656
16K x 16 CONFIGURATION(1,2)
Ao -A 13 - - - Ao -A 15
--_-..------1>------_._-------,
WE-TOP---~~----~r_---~~---__.
eS O- 3
eS 4_7
es
WE-BOT-~~~========~=======4~======~
eS S- 11
WE
NOTES:
1. All chip selects tied together since, in a by-16 configuration, all chips are either on or off.
2. The two write enables are tied together allowing control of the write enable for entire memory at one time (necessary) in a by-16 organization
since all chips are either writing or reading at any given time.
Do
32K X 8 CONFIGURATION (1,2)
01
O2
03
Ao-A13 - - - - - - - - - - - - - - - - - - - - - Ao -A 15
WE-TOP
WE----l
eS O- 3
Vee ---------,
eS 4- 7
WE
eS S- 11
eS1A AOA AlA 00A alA 02A 03A GND
cs~l-=
eS 12- 15
A14
04
05
06
07
NOTES:
1. All chip selects tied together in groups of two. The decoder uses the new higher order address pin (A14) to determine which of the two banks of
memory are disabled.
2. The two write enables are tied together for ease of layout. They could be controlled by the decoder similar to the chip selects but would save only a
minimal amount of power and add complexity to the layout.
64K X 4 CONFIGURATION (1,2)
Ao -A 13
WE
Ao -A 15
~-----------~--WE-TOP-~~~----~-------,4--------,
eS O- 3
-------.I
Vee~
Vee eS1S AOB AlB OOB alB 02B 03B
r:--"
--'1
--I
CS1A AOA AlA OO'-A__O
__
1A_O_2A_O_3_A_G_N_D_ _ _
I
I I
cs"~,,
, - - - I
01
Do
NOTES:
1. Each chip select is now controlled by the two higher order address pins A 14(neeessary in 64K deep memory).
2. Again the two write enables are tied together for ease of layout (the megabit part will only have one write enable pin).
S13-15
IDT7M656L 256K CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
xxxxx
Device Type
A
Power
999
Speed
A
Package
A
Process/
Temperature
R,ny:"nk
C
15
20
1 - - - - - - - - : - - - - - - - - - 1 25
35
55
65
L
1--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- 1 7M656
S13-16
Commercial (DOC to
+ 70°C)
Military (-55°C to + 125°C)
Semiconductor Components Compliant
to MIL-STD-883
Sidebraze DIP
Commercial onlY}
,
Speed in Nanoseconds
Low Power
256K
t;)
Intesrated Dev1ce1echnol6gy.1nc.
512K (64K x 8-BIT
or 64K x 9-BIT)
CMOS STATIC RAM MODULE
lOT 7M812
lOT 7M912
FEATURES:
DESCRIPTION:
• High-density 512K-bit CMOS static RAM module
• 64K x 8 (IDT7M812) or 64K x 9 (IDT7M912) configuration
The IDT7M812/IDT7M912 are 512K-bit high-speed CMOS
static RAMs constructed on a multi-layered ceramic substrate using 81DT7187 64K x 1 static RAMs (IDT7M812) or 91DT7187 static
RAMs (IDT7M912) in leadlesschipcarriers. Extremely high speeds
are achievable by the use of IDT71875 fabricated in lOT's highperformance, high-reliability technology, CEMOS. This state-ofthe-art technology, combined with innovative circuit design techniques, provides the fastest 64K static RAMs available.
The IDT7M812/IDT7M912 are available with access times as
fast as 2Sns commercial and 3Sns military temperature range, with
maximum operating power consumption of only 6.9W (IDT7M912,
64K x 9 option).The module also offers a standby power mode of
less than 3.2W (max.) and a full standby mode of 1.2W (max.).
The IDT7M812/IDT7M912 are offered in a high-density 40-pin,
600 mil centersidebraze DIPtotakefull advantage of the compact
IDT7187s in lead less chip carriers. The IDT7M912 (64K x 9) option
can provide more flexibility in system application for error detection, parity bit, etc.
All inputs and outputs of the IDT7M812/IDT7M912 are TTLcompatible and operate from a single SV supply. (NOTE: Both Vcc
pins need to be connected to the SV supply and both GND pins
need to be grounded for proper operation.) Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation, and
providing access and cycles times for ease of use.
Alii DT mi Iitary module semiconductor components are compliant to the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.
• Fast access times
- Military: 3Sns (max.)
- Commercial: 2Sns (max.)
• Low power consumption
- Active: 2.4W (typ. in 64K x 8 organization)
- Standby: 240~W (typ. in 64K x 8 organization)
• Utilizes 8 (IDT7M812) or 9 (IDT7M912) IDT7187 highperformance 64K x 1 CMOS static RAMs produced with IDT's
advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Available in 40-pin, 600 mil center sidebraze DIP, achieving
very high memory density
• Single 5V(±10%) power supply
• Dual Vcc and GND pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components
compliant to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
DIP
TOP VIEW
NOTES:
1. Both Vcc pins need to be connected to the 5V supply and both GND pins need to be grounded for proper
operation.
2. Pin 18 is Da and pin 23 is Ya in 64K x 9 (IDT7M912) option and both 18 and 23 are NC in 64K x 8
(IDT7M812) option.
3. For module dimensions. please refer to module drawing M5 in the packaging section.
Ao-A15
Address
Do-Da
Data Input
Yo-Ya
Data Output
CS
Chip Select
~
Write Enable
Vcc
Power
GND
Ground
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-7013/1
1989 Integrated Device Technology, Inc.
S13-17
IE
IDT7M812/IDT7M912 512K(64Kx 8-BIT or64Kx9-BIT)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
COMMERCIAL
RATING
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
-0.5 to + 7.0
MILITARY
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
UNIT
-0.5 to +7.0
GRADE
V
Military
o to
-55 to +125
°C
-55 to +125
-65 to +135
°C
-55 to + 125
-65 to +155
°C
+ 70
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°C to + 70°C
OV
5.0V ± 10%
Vee
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
50
mA
DC Output Current
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
UNIT
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
VIL
Input Low Voltage
2.2
-0.5(1)
-
6.0
V
-
0.8
V
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
DC ELECTRICAL CHARACTERISTICS
(Vec = 5.0V ±10%. TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
IDT7M912
TYP. MAX.(3) MAi.4 MIN.
Input Leakage Current
Vee = 5.5V; VlN
= GND to\'ce
20
IILOI
Output Leakage Current
Vee = 5.5V
CS = VIH. VOUT ,,;, GND to Vee
20
leel
Operating Power Supply
Current
CS = VIL • Output Open
Min. Duty Cycle = 100%
IILlI
540
1080
IDT7M812 (3)
(4
UNIT
TYP. MAX. MAX.
'::'~q:::::
iz.tt::
'r3~~
480
20
'20:.:.
~A
20
~Q<:'
~A
960
::,:,:,::::.:.:.:.
~1~8;
mA
:::::,:,::::.:.:.:.
lee2
Dynamic Operating Current
Min. Duty Cycle =; 100%
Output Open
.
540
1080
1530
480
960
1360
mA
ISB
Standby Power Supply
Current
CS?:"IH
Min. Duty Cycle = 100%
270
450
:;585
240
400
520·:
mA
ISBl
Full Standby Power Supply
Current
CS ;::; Vee -0.2V
VIN ;::; Vee -0.2V or :5 O.2V
0.2
180(2)
.·:.44$.
0.05
160 (2) :200:
10L = 10mA. Vee = Min.
0.5
":::::(y;s
0.5
0.4
:\::::{);4
0.4
:0:5
)'0;4:
V
10L =8mA. Vee = Min.
-
::t:':'::
-
':·b::::
V
VOL
Output Low Voltage
VOH
Output High Voltage
10H = -4mA. Vee = Min.
NOTES:
1. Typical limits are at Vee = 5.0V. + 25 ° C.
2. ISBl (max.) of IDT7M812/912 at commercial temperature = 80mA/90mA.
3. tAA = 30. 35. 45. 55ns
4. tAA = 25ns
S13-18
2.4
2.4
mA
V
IDT7M812/IDT7M912512K(64Kx8-BITor64Kx9-BIT)
CMOS STATIC RAM MODULE.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
5V
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1. 2 and 3
DATA OUT
~
255fl
48on
DATA OUT
30pF
~
255fl
Figure 1. Output Load
48on
5pF*
Figure 2. Output Load
(for t HZ , t LZ, twz, and tow)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%. TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL
PARAMETER
7M912S25
7M912S30
7M912S35
7M912S45
7M912S55
7M912S65
7M812S55
7M812S65
7M812S25
7M812S30
7M812S35
7M812S45
COM'L. ONLY COM'L. ONLY
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
READ CYCLE
-
30
-
35
-
45
-
55
-
65
-
ns
-
30
-
35
-
45
-
55
-
65
ns
65
ns
-
ns
5
-
ns
30
-
30
ns
0
-
0
-
ns
35
-
35
-
35
ns
t RC
Read Cycle Time
2~:::::::::::,.,..
tM
t ACS
Address Access Time
-i.::;::;:::::::::·:·:·:·:·:·25
tOH
Output Hold from Address Change
S)::::}}:-
5
-
5
-
5
-
5
-
5
tLZ
Chip Selection to Output in Low Z
5
-
5
-
5
-
5
-
tHZ
Chip Deselection to Output in High Z
5.::::::;::;:::;::::}(::_:·::::::::::;:)::20
-
25
-
25
-
30
-
tpu
Chip Selection to Power Up Time
0
-
0
-
0
-
t pD
Chip Selection to Power Down Time
-
30
-
35
-
Chip Select Access Time
WRITE CYCLE
-.;::::::::::..
:.::;';'.:
O:::::'::):::)L
:::::::::::::::::::::::::::::;;.,,,
&;.v
30
35
55
45
::::::::::::::::}}:;:::::
.... ;:;:::;:,:::,::::::::::::::::::
twc
Write Cycle Time
"Yo::';::::::::.:..
30
-
35
-
45
-
55
-
65
-
ns
tcw
Chip Selection to End of Write
2:3c}::·:::::::::'
28
-
35
-
40
-
50
-
55
-
ns
tAW
Address Valid to End of Write
23...
-
28
35
-
40
-
50
3
5
-
5
-
5
-
ns
Address Set-up Time
-
55
t AS
-
twp
Write Pulse Width
tWR
Write Recovery Time
-
ns
tow
Data Valid to End of Write
ns
tOH
Data Hold Time
5::::::::\::::·:-
twz
Write Enable to Output in High Z
Q::;::})::
tow
Output Active from End of Write
",:;:::::::/;:;,:::::::::::
.,.:..-
'>,,::::::::::::::::::})
0\ {:)1. ;::;::}}:;:::;:::;::::
20
_.....,..,........,.
3
25
30
30
0
-
0
20
-
20
-
5
-
5
-
0
25
0
0
-
0
0
S13-19
35
5
40
ns
ns
0
-
0
25
-
25
-
30
-
5
-
5
-
5
-
ns
25
0
30
0
30
0
35
ns
-
0
-
0
-
0
-
ns
I DT7M812/IDT7M912 512K (64Kx 8·BIT or 64K x 9·BIT)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CXCLE NO.1
ADDRESS
DATAoUT
(1,2)
-G
t
RC
(5)
-----------~~
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.2
......._ -
DATA VALID
(1,3)
14--------- t
RC (5) ---------~
t ACS ------.1
DATAoUT
DATA VALID
HIGH IMPEDANCE
SUPPLY
CURRENT
VCC
~----:~~~~~~~~~~~~
NOTES:
VIr=. is high for READ cycle.
2. CS is low for READ cycle.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
1.
S13-20
IDT7M812/IDT7M912 512K (64Kx 8-BIT or 64Kx9-BIT)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
ADDRESS
-----..,.
----/
twc
<
)(
tAW
~,
~r
t
- tAS
(7)
tWR
Wp
~fI"
..... :"00..
-t
tOHZ
-
(6)-
WHZ
(6)
-tow-l.
:"::.'. . «>:".'"
(4)
DATA OUT
tow_
(4)
<"./.. ". ""'\'" ~
tOH
----------~~--~>~~----~
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2, 3, 5)
twc
ADDRESS
~(
)(
tAW
~tAS
-
/V
'r\.
tWR
tcw
I,
I'
tDW
tOH
"'1
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
S13-21
I DT7M812/1 DT7M912 512K (64K x 8-BIT or 64K x 9-BIT)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
MODE
CS
WE
OUTPUT
SYMBOL
POWER
Standby
H
X
High Z
Standby
Read
L
H
DATA OUT
Active
Write
L
L
HighZ
Active
,
CIN
(TA= +25°C. f = 1.0MHz)
TEST
CONDITIONS
Input Capacitance
VIN = OV
COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.
TYP.
UNIT
80
pF
15
pF
ORDERING INFORMATION
IDT
xxxxx
Device Type
999
Speed
A
Package
A
Process/
Temperature
Range
Y:,onk
~----------------~
~
______________________
~
Commercial (O°C to
Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STD-883, Class B
C
Sidebraze DIP
25
30
35
Commercial Only
Commercial Only
}
45
55
65
~--------------------------~S
~__________________~__________________--I
S13-22
7M812
7M912
+ 70°C)
Standard Power
64Kx 8-Bit
64Kx 9-Bit
Spoed In Nanooocond,
. _ - - - - - - - - - - - - - - - - - _ ....•._... _-_._.._.
(;)
4 MEGABIT (256K x 16)
CMOS STATIC RAM
MODULE
Integrated Device'i!chnology.Jnc.
PRELIMINARY
lOT 7M4016
FEATURES:
DESCRIPTION:
• High-density 4 megabit (256K x 16) CMOS static RAM module
The IDT7M4016 is a 4-megabit high-speed CMOS static RAM
module constructed on a multi-layered ceramic substrate using
sixteen (256K x 1) static RAMs in leadless chip carriers. The
IDT7M4016 is an upgrade from the IDT7M624 (1024K RAM module) offering four times the memory density in the same size package. Making four chip select lines available (one for each group of
four RAMs) allows the user to configure the memory into a 256K x
16, 512K x 8 or 1024K x 4 organization.
The IDT7M4016 is packaged in a 48-pin, 900 mil wide sidebraze
DIP to take advantage of the compact leadless Chip carriers. This
enables four megabits of static RAM memory to be placed in less
than 2.2 square inches of board space.
All inputs and outputs of the IDT7M4016 are TIL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
All lOT military module semiconductor components are
compliant to the latest revision of MIL-STD~883, Class S, making
them ideally suited to applications demanding the highest level of
performance and reliability.
• Low power consumption
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Available in 48-pin, 900 mil wide ceramic sidebraze DIP
• 4X the density of the IDT7M624 (1024K RAM module) in the
same size package
• Multiple GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Inputs and outputs directly TIL-compatible
• Modules available with semiconductor components compliant
to MIL-STD-883, Class S
FUNCTIONAL BLOCK DIAGRAM
18
AO-17
-+-----1
4
4
4
256K x 1
256Kx 1
256K x 1
4
256K x 1
I/O
I/O
I/O
I/O
RAMS
RAMS
RAMS
RAMS
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology. Inc.
JANUARY 1989
DSC-7oo9/1
513-23
IDT7M40164 MEGABIT (256K x 16)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
PIN CONFIGURATION
Power
Vcc
GND
Ground
Ao-17
Addresses
D O- 15
Data Input/Output
~
Chip Select
WE:L
Write Enable (Lower Byte)
WE"u
Write Enable (Upper Byte)
RECOMMENDED DC OPERATING CONDITIONS
MIN.
TYP.
MAX.'
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
V
Input Low Voltage
-0.5(1)
-
6.0
V1L
O.S
V
SYMBOL
NOTE:
1. For module dimensions. please refer to module drawing
M9 in the packaging section.
ABSOLUTE MAXIMUM RATINGS
VrERM
RATING
Terminal Voltage
with Respect to
GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
(1)
COMMERCIAL
MILITARY
Military
UNIT
Commercial
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
Tsm
Storage
Temperature
-55 to +125
-65 to + 150
°C
lOUT
DC Output Current
50
50
mA
AMBIENT
TEMPERATURE
GND
Vee
-55°C to + 125°C
OV
5.0V ±10%
O°C to +70°C
OV
5.0V ±10%
Note:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±10%
SYMBOL
UNIT
Note:
1. V1L = -3.0V for pulse width less than 20ns.
DIP
TOP VIEW
SYMBOL
PARAMETER
PARAMETER
TEST CONDITIONS
\'IN =
MAX. \'IN =
Ilu l
Input Leakage (Address & Control)
Vcc = MAX.
GND to Vcc
lIu l
Input Leakage (Data)
Vcc =
GND to Vcc
IlLOI
Output Leakage
Vcc = MAX. CS = V1H .
Vour = GND to Vcc
VOL
Output Low Voltage
Vcc= MIN. 10L= SmA
VOH
Output High Voltage
Vcc= MIN. 10H= -4mA
S13-24
MAX.
UNIT
SO
/-LA
10
/-LA
-
10
/-LA
-
0.4
V
2.4
-
V
MIN.
-
IDT7M40164 MEGABIT (256Kx 16)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Vcc -- 5V +10%
IDT7M4016 (1)
IDT7M4016
MAX.
MAX.
MIL
UNIT
Operating Current
f = 0; CS :::;; V1L . Vec= MAX; Output Open
1760
-
1600
1760
mA
lec2
Dynamic Operating Current
Vec= MAX; CS
Output Open
2560
-
2400
2560
mA
IS8
Standby Current Supply
CS:::;;VIL
560
-
560
560
mA
IS81
Full Standby Supply Current
CS ;?: Vcc -0.2V,
480
-
480
480
mA
ICCl
TEST CONDITIONS
PARAMETER
SYMBOL
COM'L
:::;; \lL; f
= fMAX
\IN ;?: Vcc -0.2 or ::::;; 0.2V
MIL
COM'L
(2)
Notes:
1. 25ns
2. 35. 45. 55. 70ns
AC ELECTRICAL CHARACTERISTICS
Vcc= 5V ±10%
SYMBOL
7M4016S25
(COM'L ONLy)
MAX.
MIN.
PARAMETER
7M4016S45
7M4016S35.
MIN.
MAX.
MIN.
7M4016S55
MAX. MIN.
7M4016S70
(MIL ONLy)
MAX. MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
25
-
35
-
45
-
55
-
70
-
ns
tAA
t ACS
Address Access Time
-
25
-
35
45
-
55
ns
-
25
-
35
45
-
55
-
70
Chip Select Access Time
-
70
ns
t CLZ (1) Chip Select to Output in Low Z
t CHZ (l) Chip Deselect to Output in High Z
5
-
5
-
5
-
5
-
5
-
ns
-
13
-
20
-
25
30
ns
5
ns
25
5
0
-
0
-
45
-
55
-
70
ns
-
55
-
70
65
-
ns
55
65
-
ns
0
65
0
-
0
-
ns
55
-
ns
tOH
t pU(l)
Output Hold from Address Change
5
-
5
-
5
Chip Select to Power Up Time
0
-
0
-
0
-
t pO(l)
Chip Deselect to Power Down Time
-
25
-
35
-
ns
WRITE CYCLE
twc
Write Cycle Time
25
-
35.
-
45
tcw
Chip Selection to End of Write
25
35
-
45
tAW
Address Valid to End of Write
25
-
35
-
45
t AS
Address Set-up Time
0
-
0
0
twp
Write Pulse Width
25
35
0
-
0
-
tWR
Write Recovery Time
t WHZ (l) Write Enabled to Output in High Z
tow
Data to Write Time Overlap
tOH
t ow (1)
0
-
45
55
0
ns
ns
-
13
-
20
-
25
-
25
-
30
ns
12
-
15
20
-
35
0
0
0
5
5
-
5
-
5
-
0
Output Active From End of Write
-
-
ns
0
-
30
Data Hold from Write Time
-
5
-
ns
ns
Notes:
1. This parameter guaranteed but not tested.
5V
DATAOLrr
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
~
2550
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
5V
48on
30pF
Figure 1. Output Load
DATAoLrr
~
2550.
5pF*
Figure 2. Output Load
(for t CLZ1 ,2' tOLZo t CHZ1 ,2' t OHz ,
tow,tWHZ )
*Including scope and jig.
S13-25
48on
I DT7M4016 4 MEGABIT (256K x 16)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~
I----------
ADDRESS
tRc
-----------i%;~
~~~-----~----------~--~--~~-tAA-----------------·-I--------~
14------ t ACS --------t
~----
t CLZ (4)
----.,j
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.2
(1,2)
ADDRESS
DATA OUT
TIMING WAVEFORM OF READ CYCLE NO.3
(1,3)
DATA OUT
NOTES:
1. WE is high for read cycle.
2. Device is continuously selected, ~ = V1L •
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state with 5pF load (including scope and jig).
S13-26
--t-OH-------------
IDT7M40164 MEGABIT (256K x 16)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1
(WE CONTROLLED TIMING)
(1,2,3)
twc
ADDRESS
~(
)(
tAW
~,
/~
t AS
twp
"
_
t WR -
)'
tWHZ (5l---.,
-
tOW---
DATAoUT
tow
.1.
I
,
tOH
TIMING WAVEFORM OF WRITE CYCLE NO.2 (1,2,3,4)
(CS CONTROLLED TIMING)
twc
ADDRESS
~(
)(
---.-/
tAW
t AS
~V
"
tWR
tcw
fo--
)t'
.1.
NOTES:
1. ~ or CS must be high during all address transitions.
2. A write occurs during the overlap (tcw or twF) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or
going high to the end of the write cycle.
4. If the CS low transition occurs simultaneous with or after the ~ low transition, the outputs remain in the high impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
wr=.
513-27
IDT7M40164 MEGABIT (256K x 16)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE(TA=+25°C, F = 1.0MHz)
TRUTH TABLE
MODE
CS
WE
Standby
H
Read
Write
OUTPUT
POWER
X
High-Z
Standby
L
H
DATAoUT
Active
L
L
High-Z
SYMBOL
. Active
PARAMETER(1)
CONDITIONS
C1N(D)
Input Capacitance
(Data)
V(IN) = OV
C1N(A)
Input Capacitance
Address and Control
V(IN) = OV
COUT
Output Capacitance
V(OUT)
= OV
TYP.
UNIT
30
pF
200
pF
30
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
XXXX
A
Device Type Power
999
Speed
A
Package
A
Process/
Temperature
Range
Y:LANK
'-----------i C
L...-------------l
25
35
~g
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Semiconductor components
compliant to MIL-STD-883, Class B
Ceramic DIP
Commercial Only
.
1
Speed in Nanoseconds
70
'------...;."..----..,.-------l S
'--------------------~
S13-28
7M4016
Standard Power
256K x 16 Static Ram Module
t;)
Integrated DevIce~Inc.
2 MEGABIT (64K x 32)
CMOS STATIC RAM
MODULE
lOT 7M4017
FEATURES:
DESCRIPTION:
• High-density 2 megabit (S4K x 32) CMOS static RAM module
The IDT7M4017 is a 2 megabit (S4K x 32) high-speed static RAM
module constructed on a co-fired ceramic substrate using eight
IDT7125S 32K x 8 static RAMs in leadless chip carriers. On-board
decoders use A15 to select the upper or lower bank of RAMs. Four
chip selects control individual byte selection. Extremely fast
speeds can be achieved due to use of 25SK static RAMs and the
decoder fabricated in lOT's high-performance, high-reliability
CEMOS technology.
The IDT7M4017 is offered in a SO-pin, SOO mil center sidebraze
DIP which enables two megabits of memory to be placed in less
than 1.9 square inches of board space.
The IDT7M4017 is available with fast access times over the
commercial and military temperature ranges, with minimal power
consumption. The circuit also offers a reduced power standby
mode. When CS goes high, the circuit will automatically go to a
substantially lower power mode.
All inputs and outputs of the IDT7M4017 are TTL-compatible
and operate from a Single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
All lOT military module semiconductor components are
manufactured in compliance with MIL-STD-883, Class B, making
them ideally suited to applications demanding the highest level of
performance and reliability.
• Fast access times
- Military: 50ns (max.)
- Commercial: 40ns (max.)
• Individual byte selects
• Upper and lower word write enables
• CEMOS ™ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
•
•
•
•
Available in SO-pin, SOO mil wide ceramic sidebraze DIP
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Modules available with semiconductor components compliant
to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
DECODER
CS(O-3)
,8/
--C
64Kx32 RAM
W'C o --0
~1--C
I/O
"' .... 32
DATA
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
OSC-7010/-
513-29
IDT7M4017 2 MEGABIT (64Kx 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
PIN CONFIGURATION
Ao - A15
Addresses
1/00-31
Data Inputs/Outputs
CS"0
Chip Select for I/O 0-7
CS1
Chip Select for 1/08-15
CS 2
Chip Select for 1/016-23
CS"3
Chip Select for 1/024-31
wr=o
Write Enable for 1/00- 15
Write Enable for 1/0 16- 31
WE'1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
DIP
TOP VIEW
RATING
Terminal Voltage
with Respect to
GND
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-10to +85
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. For module dimensions, please refer to module drawing M11 in
the packaging section.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
-
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
UNIT
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
DC ELECTRICAL CHARACTERISTICS
(Vcc
= 5V ± 10%, T A = -55°C to
SYMBOL
+ 125°C and O°C to + 70°C)
PARAMETERS
MIN.
MAX.
UNIT
/lui
Input Leakage
(Address & Control)
Vcc = Max.
VIN = GND to Vee
TEST CONDITIONS
-
20
J.lA
I'ul
Input Leakage
(Data)
Vee = Max.
VIN = GND to Vee
-
10
J.lA
/lLol
Output Leakage
Vee = Max.
CS = VIH, VOUT = GND to Vee
-
10
J.lA
VOL
Output Low Voltage
Vce = Min., IOL = 8mA
-
0.4
V
VOH
Output High Voltage
Vec = Min., IOH = -4mA
2.4
-
V
S13-30
IDT7M4017 2 MEGABIT (64K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
0/cc
= 5V -+
10%, TA
= -55°C to
+ 125°C and O°C to + 70°C)
IDT7M4017
MAX.
TEST CONDITIONS
PARAMETERS
SYMBOL
UNIT
COM'L
MIL
460
500
mA
ICC1
Operating Current
F = 0, CS :::;;V1L
Vcc = Max.; Output Open
ICC2
Dynamic Operating
Current
Vcc = Max.; CS :::;; V1L; F = FMAX
Output Open
750
790
mA
ISB
Standby Supply Current
CS:::;;"IL
180
180
mA
ISB1
Full Standby Supply
Current
CS ~ Vcc - 0.2V
V1N ~ Vcc - 0.2V or :::;; 0.2V
135
175
mA
AC ELECTRICAL CHARACTERISTICS
0/cc
= 5V ±
10%, TA = -55°C to +125°Cand O°Cto +70°C)
SYMBOL
IOT4017S40
(COM'L ONLy)
MAX.
MIN.
PARAMETER
IDT7M4017S45 IOT7M4017S50 IDT7M4017S60 IOT7M4017S70
(COM'L. ONLy)
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
40
-
45
-
50
-
60
-
70
-
ns
tM
Address Access Time
-
40
-
45
50
-
60
ns
Chip Select Access Time
-
40
-
45
50
-
60
-
70
tAcs
-
70
ns
t CLZ (1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
t CHZ (1)
Chip Deselect to Output in High Z
-
15
-
20
-
20
-
25
-
25
ns
5
tOH
Output Hold from Address Change
5
5
-
5
0
0
-
-
Chip Select to Power Up Time
-
5
t pJ1)
0
-
0
-
0
-
ns
t pd 1)
Chip Deselect to Power Down Time
-
40
-
45
-
50
-
60
-
70
ns
ns
ns
WRITE CYCLE
twc
Write Cycle Time
40
-
50
-
70
35
40
-
45
-
60
Chip Selection to End of Write
-
45
tcw
55
60
tAW
Address Valid to End of Write
35
-
-
40
-
45
-
55
60
t AS
Address Set-up Time
5
-
5
10
-
10
10
-
ns
twp
Write Pulse Width
30
35
35
-
45
50
Write Recovery Time
0
0
0
-
0
0
-
ns
tWR
t WHZ (1)
-
-
-
-
Write Enable to Output in High Z
-
15
-
20
-
20
-
25
-
30
ns
tDW
Data to Write Time Overlap
15
-
20
-
20
-
25
30
-
ns
tDH
Data Hold from Write Time
3
-
3
3
3
-
ns
Output Active from End of Write
5
-
5
-
3
tow (1)
-
-
5
-
ns
5
5
ns
ns
ns
NOTE:
1. This parameter is guaranteed but not tested.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
DATAo.rr~.
255Q
+5V
Y30pF
4800
Figure 1. Output Load
DATAaUT
~
2550
S13-31
._ .. _....._-----_..---_...... -- ..
------
.. 5PF*
Figure 2. Output Load
(for tCLZ1,2,tOLZ,tCHZ1,2,toHZ,
tOW,tWHZ)
*Including scope and jig.
--_... -
4800
(
IDT7M4017 2 MEGABIT (64K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~
~---------------tRC--------------~
ADDRESS
___________________________________
joII---------tM -----~~I
1 4 - - - - - - tAcs-----~
1 4 - - - - - - t CLZ ( 5 ) _ - - - - r
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
DATAoUT
=1
2(1,2,4)
t RC
.1
tM
.1
tOH
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
EtO"
DATA VALID
3(1,3,4)
DATA OUT
NOTES:
1. WE Is High for Read Cycle.
_
2. Device Is continuously selected, CS = V,l,.
3. Address valid prlor"to or coincident with ~ transition low.
4. OE = V,L•
5. Transition Is measured ±5OOmV from steady state. This parameter Is sampled and not 100% tested.
S13-32
IDT7M40172 MEGABIT (64Kx 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (1)
1 4 - - - - - - - - - - - ' twc ---------~
ADDRESS
--------~
~----------
~---------tAW -----------~
14-------twP (2)
_____~
DATAoUT
TIMING WAVEFORM OFWRITE CYCLE NO.2
(1,6)
~--------------twc-------------~
ADDRESS
,...--------- few
-------!~
~---------~----~w -----------~
-----+---l~or_.......~_-,. ....-----twp(2)----~,...-+-------
DATA oUT
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5, If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. OE is continuously low (OE = \tid.
7. DATAoUT is the same phase of write data of this write cycle.
8. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be
applied to them.
9. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
S13-33
IDT7M40172 MEGABIT (64K x 32)
CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
(TA= +25°C, f = 1.0MHz)
PARAMETER (1)
CONDITIONS TYP. UNIT
MODE
CSx
WEx
OUTPUT
POWER
SYMBOL
Standby
L
X
X
Standby
C'N(D)
Input Capacitance (Data)
'-"N = OV
30
pF
Read
L
H
Dour
Active
C'N(A)
V,N = OV
100
pF
Write
L
L
D,N
Active
Input Capacitance
Address and Control
Gour
Output Capacitance
Vour = OV
30
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
lOT
xxxxx
999
A
A
Device Type
Speed
Package
Process/
Temperature
~:~k
~--------------~
L-______________________
~
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Semiconductor Components Compliant
to MIL-STD-883, Class B
C
Ceramic DIP
40
45
50
Commercial Only
Commercial Only
} Speed ;n Naoosooond'
60
70
~----------------------------~
L----------------------f
S13-34
S
Standard Power
7M4017
64K x 32 Static RAM Module
t;)
Integrated Device~Inc.
different address. This allows systems to be built that can perform
fast Fourier Transforms in either a decimation-in-time or a decimation-in-frequency configuration. Data read from Memory 1 can be
synchronously loaded into its output register, while data can be
written into a different location in Memory 2. Similarly, data can be
read from Memory 1 and Memory 2 in parallel from two different
addresses and -can be written into Memory 1 and Memory 2 at
unique addresses. Registers at the data input and data output provide fully synchronous pipe lined operation. The two memory systems are 20 bits wide and have multiplexed data input and data
output bits from the module data pins. By taking advantage of the
speed ofthe registers, data on the pins can run at a speed twice that
of the memory. That is, both output registers can be read or both
input registers can be loaded in a single memory cycle.
Two address sources are available to each address register to
the RAM. Address Source A or Address Source B may be selected
to load the edge triggered register for the 16K x 20-bit memory. The
IDT54/74 FCT399 is used for the two input multiplexer and address
registers for each 16K x 20 memory. All inputs and outputs of the
ID17M6001 are TTL-compatible and operate from a single 5V
supply.
The ID17M6001 is offered as a compact 92-pin quad in-line
(QIP) ceramic module. It is constructed using ceramic LCC components on a multilayer co-fired ceramic substrate and occupies
only 4.2 square inches of board space.
AIlIDT military module semiconductor components are compliant to the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
lOT 7M6001
DUAL MULTIPLEXED
16K x 20 SYNCHRONOUS
STATIC RAM MODULE
Dual 16K x 20 synchronous RAM
Edge triggered data input and data output registers
Edge triggered data address registers
Two address register sources individually selectable
Separate chip select and write enables to each memory array
Individual clock lines to each register
Dual high-performance 16K x 20 memories
Unique ping-pong operation capability
Assembled with lOT's high-reliability vapor phase solder reflow
process
Available in compact 92-pin ceramic sidebraze QIP (quad
in-line) package
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Military modules available with semiconductor components
compliant to MIL-STD-883, Class B
DESCRIPTION:
The ID17M6001 is a dual multiplexed 16K x 20 synchronous
RAM module. It utilizes ten ID171981 high-speed synchronous
memories, along with the appropriate input data, output data and
address registers. The device features the ability to be used in a
ping-pong mode. That is, data can be loaded into one memory array at one address and be read from the other memory array at a
FUNCTIONAL BLOCK DIAGRAM
REG
20/
D
/
Q~
CP
01
rr=~
16Kx20
RAM
A
REG
20L
DO
D
/
Q
20/
/
D00-19
ICP~
114
-D
REG
J
.--r--
Q 20
~:
16Kx20
RAM
A
DOl
CP
D
Q
REG
REG
Q
A
MUX
Q~
I~
Q
S2
D
/
114
CP
ACK 2
REG
20/
CP
D
ACK 1
Q
B
A
I
,/'14
,P"14
ADA0-13
ADB0-13
MUX
B
S1
I
CEMOS is a trademark of Integrated Device TechnologY,lnc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated DevIce Technology. Inc.
JANUARY 1989
DSC-7028/-1
513-35
IDT7M6001 DUAL MULTIPLEXED 16K x 20
SYNCHRONOUS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
PIN CONFIGURATION
GND
ADAo
ADA 1
ADA2
ADA3
ADA4
ADA5
ADAe
ADA7
ADAs
ADA9
ADA 10
ADA11
ADA12
ADA13
CKI 1
CK0 1
OF: 1
S1
ACK 1
U1
WE1
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
GND
ADBo
ADB1
ADB2
ADB3 '
ADB4
ADB5
ADBe
ADB7
ADBs
ADB9
ADB10
ADBll
ADB12
ADB13
CKI2
CK0 2
M31(1)
0E2
~
ACK 2
~2
Vee
Vee
Dlo
DI1
DI2
DI3
DI4
DI5
. Die
DI7
Dis
DI9
GND
DllO
Dill
DI12
DI 13
DI14
DI 15
DI 1e
DI17
DI1S
DI19
GND
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
Vee
DDo
D01
D0 2
D0 3
D0 4
DD5
DOe
D0 7
DOs
D0 9
GND
D010
D011
D012
D013
DOg
D0 15
D01e
D017
D01s
D019
GND
77
76
75
74
73
72
71
70
OF:1-0E'2
Data Out Register Output Enable
ADAo -ADA 13
A Address Inputs
ADB o-ADB 13
B Address Inputs
Dl o-D119
Data Inputs
DO o -D019
Data Outputs
CKI 1-CKI2
Data In Register Clock Input (Active Rising Edge)
ACK 1-ACK 2
Address Clock Input (Active Rising Edge)
S1-S2
Address MUX Select Input
WE1-WE2
Write Enable
CE'1-~2
RAM Select
CK01-CK02
Data Out Register Clock Input (Active Rising Edge)
FUNCTIONAL TABLE FOR ADDR MUX
NOTE:
1. For module dimensions, please refer to module drawing ",,31 in the
packaging s e c t i o n . .
C
INPUTS
H =
L =
h =
=
X =
RATING
SB
X
a
I
h
X
H
h
X
I
L
L
h
X
h
H
HIGH Voltage Level
LOW Voltage Level
HIGH Voltage Level one set-up time prior to the LOW-ta-HIGH
clock transition of ACK1, 2
LOW Voltage Level one set-up time prior to the LOW-to-HIGH
clock transition of ACK1, 2
Immaterial
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
OUTPUTS
SA
I
S12
I
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
mA
)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
-
6.0
V
0.8
V
Input Low Voltage
-0.5(1)
NOTE:
1. V1L (min.) = -3.OV for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
S13-36
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
IDT7M6001 DUAL MULTIPLEXED 16K x 20
SYNCHRONOU"S STATIC RAM MODULE.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
Vee = 5V -±10%
SYMBOL
PARAMETER
TEST CONDITIONS
= Max., \1N = GND to Vcc
= Max.,V1N = GND to Vcc
\be = Max., ~ = V1H,
VOUT = GND to \be
Vee = Min., IOL = 8mA
\be = Min., IOH = -4mA
lIu l
Input Leakage (Control)
Vcc
Ilu l
Input Leakage (Data & Address)
Vcc
IILol
Output Leakage
VOL
Output Low Voltage
VOH
Output High Voltage
UNIT
MIN.
MAX.
-
25
JlA
5
JlA
-
10
JlA
-
0.4
V
2.4
-
V
DC ELECTRICAL CHARACTERISTICS
-
Vee = 5V + 10%
IDT7M6001
SYMBOL
PARAMETERS
TEST CONDITIONS
= 0, CSX~VIL
= Max.; Output Open
\be = Max.; ~x ~ V1L; f = fMAl(
f
MAX.
UNIT
COM'L
MIL
1000
1150
mA
ICCl
Operating Current
Icc2
Dynamic Operating
Current
Output Open
1910
2035
mA
IS8
Standby Supply Current
CS::;;VIL
870
920
mA
IS81
Full Standby Supply
CUrrent
~x ~ Vcc - 0.2V
V1N ~ Vcc - 0.2V or ::;; 0"2V
440
490
mA
Vcc
S13-37
IDT7M6001 DUAL MULTIPLEXED 16Kx20
SYNCHRONOUS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±10%
7M6001S40
PARAMETER
SYMBOL
MIN.
7M6001S55
7M6001S45
MIN.
MAX.
MAX.
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
40
-
45
-
55
-
tCKO-DO
ts
CKOx to Output Valid
-
12
-
12
-
12
ns
Address Set-up Time
5
5
-
ns
Address Hold Time
5
5
-
5
tH
-
5
-
ns
tOE
Output Enable to Output Valid
-
15
-
15
-
15
ns
tcp
CKOx, ACKx Pulse Width
10
-
10
-
10
-
ns
tCS-CKO
Chip Select-1, 2 to CKOx
30
35
-
45
tOHZ
Output disable to Output in High Z
18
18
18
ns
10
-
-
10
-
ns
0
-
0
ns
ns
tsu
S to ACK set up time
10
tSH
t pU (l)
S to ACK to hold time
0
-
Chip Select to Power Up Time
0
-
0
-
0
-
t pD (1)
Chip Deselect to Power Down Time
-
40
-
45
-
55
ns
-
55
-
ns
5
ns
-
5
-
(1)
ns
ns
WRITE CYCLE
twc
Write Cycle Time
40
-
45
ts
Address, Din Set-up Time
5
5
tH
Address, Din hold Time
5
tAcK-WE
ACKx to Write Enable
12
twp
Write Pulse Width
25
-
tcp
CKlx, ACK Pulse Width
10
-
10
tcw
Chip Select to End of Write
25
-
30
t ACKW
ACK to End of Write
37
tCKlW
CKlx to End of Write
27
tsu
S to ACK set up time
10
S to ACK hold time
tSH
NOTE:
1. This parameter guaranteed but not tested.
0
-
CAPACITANCE
SYMBOL
12
35
42
-
29
-
32
10
-
10
0
-
0
30
-
12
10
35
47
ns
ns
ns
-
ns
-
ns
ns
ns
ns
ns
TRUTH TABLE
(TA= +25°C, f = 1.0MHz)
PARAMETER(l)
5
CONDITIONS
TYP.
UNIT
CIN(D)
Input Capacitance
Din and Address
VIN = OV
40
pF
CIN(C)
Input Capacitance
Control
VIN = OV
50
pF
COUT
Output Capacitance
VOUT= OV
40
pF
CE
OE
WE
CKO
CKI
POWER
Standby
H
X
X
X
X
Standby
Read
L
L
H
t
X
Active
Write
L
X
L
X
t
Active
Mode
NOTE:
1. This parameter is sampled and not 100% tested.
S13-38
IDT7M6001 DUAL MULTIPLEXED 16Kx 20
SYNCHRONOUS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE CYCLE
twc
,
V
ACK1,2
V
1\
I
~tH-=i
,~
ADDRESS
xX' '''I.'I.'iY.'i'I XXXXXXXXX ~
JI\
S
~
~tcp-
ts"
tsu ... I+- tSH
\
V
tsu
t=~~
,
twp
~
1\
"
t ACKW
I
tcw
1\
CE,2
j
f.
1/
tCKlW
"
CKI1,2
~
tcp-
ts
I~"
\
I=;
~
READ CYCLE
~------------------tRC ------------------~
ADDRESS
S
DOUT
'OE'1,2
513-39
IDT7M6001 DUAL MULTIPLEXED 16K x 20
SYNCHRONOUS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and2
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
5V
DATA OUT
~
2550
480n
DATAoUT
~
2550
30pF*
FIgure 1. Output Load
4800
5pF*
FIgure 2. Output Load
(for t cLZ1 ,2, t oLZ, t CHz1 ,2, t OHZ,
tow, and t WHZ )
* Including scope and jig.
ORDERING INFORMATION
IDT
XXX)(
Device Type
. 999
Speed
A
A
Package
Process/
Temperature
-~
Blank
B
CK
Commercial (O°C to + 70°C)
. Military (-55°C to + 125°C)
Semiconductor components compliant
to MIL-STD-883, class B
Ceramic alP
40
'-------------------'------1 45
}
Speed in N"",seoonds
55
~------------------------------~
'----------------------------------------1
S13-40
S
Standard Power
7M6001
Dual Multiplexed Synchronous Module
-_ ..
t;)
Integrated Device1echnoIogy. Inc.
lOT 7M6032
are connected to the 0 inputs of an lOT49FCT818. The device has
the serial data-in and serial data-output bits connected to form a
32-bit Serial Protocol Channel register. The module features four
separate output enables, one for each of the IDT49FCT818 registers. Thus, the Y outputs from the IDT49FCT818 registers may be
enabled or put into the high-impedance state on individual 8-bit
boundaries. The Command/Data (C/O), Serial Shift Clock (SCLK)
and Parallel Clock (PCLK) are .all bus organized across the four
IOT49FCT818 registers. The thirty-two register output bits, eight
from each device, are separately brought out to form a 32-bit wide
pipeline register on the Writable Control Store.
In normal operation, data from the 32-bit wide memory is loaded
into the IOT49FCT818 registers on the low-ta-high transition of
PCLK. Reading and writing of the memory by means of the Serial
Protocol Channel is performed using the IOT49FCT818. That is,
the data to be loaded can be shifted in the serial data input by using
the SCLK and a load command executed by shifting the proper
command word in the serial data input when the C/O line is in the
command m..9de. This command will then be executed by manipulating the C/O Iine and SCLK line. Data is then written into the RAM
by bringing the write enable line on the RAM memory from the high
state to the low state and back to the high state.
The I0T7M6032 is offered in a compact 64-pin 600 mil wide ceramic dual in-line module. It is constructed using ceramic LCC
components on a multilayer co-fired ceramic substrate and occupies less than 2 square inches of board space.
The semiconductor components used on all lOT military modules are manufactured in compliance with the latest revision of
MIL~STD-883, Class 8, making them ideally suited to applications
demanding the highest level of performance imd reliability.
FEATURES:
•
•
•
•
..
16K x 32 WRITABLE
CONTROL STORE
STATIC RAM MODULE
• 16K x 32 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC TM) -reading, writing and
interrogation
• 4 byte/wide output enables
• Separate chip select, write enable and output enable memory
controls
•
•
•
•
__._-_ _ - - - - - - - - - - - - - -
High fanout pipeline register
Fully width expandable
Designed for high-speed writable control store applications
Assembled with lOT's high-reliability vapor phase solder reflow
process
Compact 64-pin ceramic sidebraze DIP
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Military modules available with semiconductor components
manufactured in compliance to MIL-STD-883, Class 8
DESCRIPTION:
The IDT7M6032 is a 16K x 32-bit Writable Control Store (WCS)
RAM and pipeline register. It features eight IDT7198 16K x 4 highperformance static RAMs and four IDT49FCT818 Serial Protocol
Channel (SPC) registers. These devices are arranged to form the
16K x 32 Writable Control Store RAM with Serial Protocol Channel
for loading of the memory. The address lines, chip select, write
enable and output enable of the RAMs are all bused together to
form one large 16K x 32 memory. Each eight Data I/Os of the RAM
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
A 13 -Ao
14
A
16K x 32 RAM
. 8 - IDT7198s .
I/O
I/O
I/O
I/O
D
IDT49FCT818
D
IDT49FCT818
SDI
c/o
SDI
SCLK
D
IDT49FCT818
PCLK
Y
SDI
DE
Y
~
y
~
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1989 Integrated Device Technology. Inc.
JANUARY 1989
05C-7030/1
513-41
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
NOTE:
1. For module dimensions, please refer to module drawing M13 in the'
packaging section.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA
RATING
Terminal Voltage
with Respect to
GND
Operating
Temperature
-0.5 to +7.0
Oto +70
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
-0.5 to +7.0
-55 to +125
UNIT
SYMBOL
V
°C
TelAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
-
6.0
V
V1L
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
S13-42
AMBIENT
TEMPERATURE
-55°C to +125°C
GND
OV
5.0V
O°Cto +70°C
OV
5.0V
Vee
± 10%
± 10%
.-----------------------------------------~
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
..
__ . __._.__..•..__ ._--_._----
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
(TA= +25°C f = 10MHz)
PARAMETER(1)
CS
OE
WE
OUTPUT
POWER
SYMBOL
CONDITIONS
TYP.
Standby
H
H.
X
HighZ
Standby
C1N(D)
Input Capacitance
V1N = OV
15
pF
Standby
H
L
X
DOUT
Standby
C1N(A)
Input Capacitance
Address and Control
V1N = OV
60
pF
COUT
Output Capacitance
Vour= OV
10
pF
MODE
Read
L
L
H
DOUT
Active
Read
L
H
H
HighZ
Active
L
SPC(l)
Write
SPC(l)
L
NOTE:
1. This parameter is sampled and not 100% tested.
Active
NOTE:
1. See SPC Commands for proper execution of write cycle.
PIN DESCRIPTION
PIN NAME
DESCRIPTION
I/O
PCLK
I
Parallel Data Register Clock
Parallel Data Register Output Pins (Yo = LSB. Y3l = MSB)
YO- 3l
0
ut:y
I
Output Enable for Y Bus (Overidden by SPC Inst. 8 & 14)
SDI
I
Serial Data In for SPC Operation. Data and command shifts in the Least Significant Bit first
SDO
0
Serial Data Out for SPC Operation. Data and command shifts out the Least Significant Bit first
C/O
I
Mode Control for SPC
SCLK
I
Serial Shift Clock for SPC Operations
"CS
I
RAM Chip Select
WE
I
RAM Write Enable
A O- 13
I
Address Bus Pins
lmi:
I
Internal RAM Output Enable for D bus
S13-43
UNIT
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
25ns
PARAMETER
SYMBOL
/lui
Input Leakage Data
Bus~A
/ILOI
Output Leakage
~A
TEST CONDITIONS
Vcc
V1N
= Max.
= GNDtoVcc
Vcc = MaX. CS = V1H •
VOUT = GND to Vcc
35ns
30ns
45ns
55ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
20
-
20
-
20
-
20
-
20
-
20
-
20
-
20
-
20
-
20
-
900
-
800
-
800
-
800
-
800
-
1200
-
1150
-
1050
-
1050
-
1050
-
450
-
450
-
450
-
450
-
450
-
125
-
125
-
125
-
125
-
125
r
ICCl
Operating Current mA
f = O. CS = V1L
Vcc = Max; Output Open
Icc2
Dynamic Operating
Current mA
Vcc = Max; CS = \'IL;
F = !MAX Output Open
IS8
Standby Supply Curren
mA
CS
IS81
Full Standby mA
Supply Current
CS ~ \bc - 0.2V
\'IN > Vcc - 0.2V or < 0.2V
VOH
Output High Voltage
Vcc
= Min. IOH = -15mA
2.4
-
2.4
-
2.4
-
2.4
-
2.4
-
VOL
Output Low Voltage
Vcc
= Min. IOL = 32mA
-
0.4
-
0.4
-
0.4
-
0.4
-
0.4
I
= \fL
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
30ns
25ns
35ns
MIN.
MIN.
MAX.
MIN.
MAX.
35
MAX.
45ns
MIN.
MAX.
55ns
MIN.
MAX.
READ CYCLE
tAC
Address Valid to PCLK
25
-
30
tcs
CS Valid to PCLK
25
-
30
t OESU
roJI: Valid to PCLK Set Up
15
-
20
-
t pCY
PCLK to Output Valid
-
13
-
tOE
t OHZ (l)
~ Valid to Output Valid
2
13
~ Negated to Output in High Z
2
12
25
-
55
-
55
-
30
-
35
13
-
-
16
-
16
-
16
2
13
2
12
2
16
2
16
2
16
2
12
2
12
2
12
-
30
-
35
-
45
35
-
45
-
35
45
45
WRITE CYCLE
tAW
Address Valid to End of Write
20
-
25
tcw
CS
20
-
25
twp
Write Enable Pulse Width
18
t wcD
Cont/Dat to End of Write
22
25
t AS
Address Setup Time
-
Valid to End of Write
2
23
2
NOTE:
1. Guaranteed but not tested.
S13-44
30
28
28
2
30
-
40
30
-
35
-
2
-
2
-
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (1)
ADDRESS
~
_______x_ _
-~IOIII~f---------
t AC
I+----~
.'
t OESU - - - - - - . t
~------tcs------~
Y
PCLK
NOTES:
1. WE is High for Read Cycle.
2. Transition is measured ±200mV from steady state.
S13-45
I DT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
14---------- tAW - - - - - - - - - - . !
---+---.-.
t AS
c/o
- - + - - - - - - - twp (7) -------.j
-------~~------tWCD-----~
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)(1,2,3,4,5)
ADDRESS
~~
tAw
~~
~~
~tAS-
tcw
I
t WCD
~
c/o
NOTES:
1. WE, CS must be high during all address transitions.
2. A write occurs during the overlap (wp) of a low CS and a low
3. tWR is measured from the earlier of CS or
going high to the end of the write cycle.
4. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain In the high impedance state.
wr=.
5. ROE =
wr=..
"'H
S13-46
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
SPCTIMING
PARAMETER
SYMBOL
t pLH
tpHL
tsu
tH
25ns
MIN. MAX.
15
-
30ns
MIN.
MAX.
15
-
45ns
MIN. MAX.
22
UNIT
ns
45
ns
20
ns
25
-
25
ns
25
-
25
ns
15
ns
5
-
12
-
ns
5
-
5
ns
12
-
12
2
2
-
2
-
ns
2
ns
45
-
45
-
45
15
-
15
15
-
15
-
20
C/D Low to SDO
-
25
S2
C/D to SCLK High
15
15
-
15
S3
SDI to SCLK High
8
8
Y or D to C/D Low
5
S5
C/D to PCLK High
12
-
8
S4
S6
Y to PCLK High
5
H2
C/D from SCLK Low
12
H3
SDI from SCLK High
2
H4
Y or D from C/D Low
2
H5
SCLK High from PCLK High
2
-
SCLK High to SDO
T3
SDI to SDO (Stub Mode)
T4
C/D LowtoY
T5
SCLK High to Y
T6
15
15
-
22
25
55ns
MIN. MAX.
-
-
T2
22
45
20
12
-
12
5
-
5
12
12
2
-
2
-
2
-
-
2
-
2
-
3
-
3
-
3
-
-
20
-
20
-
20
ns
20
-
20
20
ns
20
-
20
-
20
ns
15
-
15
-
15
ns
35
-
35
-
ns
15
8
5
2
H6
C/D from PCLK High
2
-
2
H7
Y from PCLK High
3
-
3
15
15
-
15
t HZ (1.2)
2z,4z
SCLK High to D or Y High Z
t LZ (1.2)
3z,5z
C/D High to D or Y High Z
-
t ZHL (1.2)
Z2,Z3
C/O Low to 0 or Y Valid 22, 23
-
15
-
15
W1
PCLK (High & Low)
10
10
W2
SCLK (High & Low)
30
W3
C/D High
30
-
-
tw
35n.
MIN. MAX.
30
30
NOTE:
1. Guaranteed but not tested.
2. OE = \lH
S13-47
15
5
2
2
35
35
-
5
12
2
2
35
35
8
2
ns
ns
ns
ns
ns
ns
ns
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
GENERAL AC WAVEFORMS FOR PARALLEL INPUTS AND OUTPUTS
PCLK
Y
GENERAL AC WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS
SCLK
SDI
...!........./i
~
I
SDO
ctr5
>-I+--t,,"
(""b mOde§®
(DECODE)
'/
----~I.I.
(EXECUTE)
\:
~I~-
~.---------------~.~~
tw
S13-48
IDT7M6032 512K (16Kx 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED WAVEFORMS OF SERIAL PROTOCOL OPERATIONS
PARALLEL DATA REGISTER -
SPC Data (Inst. 0)
SPC Data (Inst. 2)
SET SERIAL MODE (Inst. 11)
Status -
SPC Data (Inst. 4)
SET SlUB MODE (Inst. 12)
SCLK
SCLK
C/!5
C/!5
~~~----------~.+®
tsu
\ ----t ----:·I-®-2-@1·,:I·'
su
D.y.m:.
PCLK
SDO
-Ft;;t pHL
SDO
SPC Data CONNECT Y TO D (Inst. 5)
SPC Data -
D (Inst. 9)
SCLK
c/!5
C/!5
D
Y
tZHL
tLZ
SPC Data
PARALLEL DATA REGISTER (Inst. 10)
SPC Data Y (Inst. 8)
CONNECT D TO Y (Inst. 14)
SCLK
Y -
SPC Data (Inst. 1)
Y D -
'HZ
:1 ag
SYNCHRONOUS W/PCLK (Inst. 3)
SPC Data -
SCLK
SCLK
C/I)
C/O
PCLK
PCLK
Y
S13-49
PARALLEL DATA REGISTER SYNCHRONOUS
W/PCLK (Inst. 13)
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED FUNCTIONAL BLOCK DIAGRAM
r--I
I
SOl
-----------------------------,
SERIAL PROTOCOL COMMAND & DATA REGISTERS
I
I
I
I
I
I
I
C/O
D
I
I
I
PCLK
-0----
SCLK
y
SDO
The detailed block diagram consists of two main elements: the
parallel data register and the SPC data/command registers. The
main data path is from the 0 inputs down to the data register and
through to the Y outputs. This path is typically used during standard operations. For diagnostic or systems initialization, the internal SPC data path is used. This path allows access between the
SPC data and command registers and the standard data path, pins
and data register. The SPC data and command registers are accessed via the SOl, SDO,
and SCLK pins.
cio
C/O"
SPCCOMMAND
REGISTER
register is used to control loading of data to and from the data register with other storage elements in the device.
With respect to executing an SPC command, there are four distinct phases: (1) data is shifted in, (2) followed by the command, (3)
the command is executed, and (4) data is shifted out. During the
data mode, data is simultaneously shifted into the serial data register while the data in the register is shifted out. During the command
mode, opcode-type information is shifted through the serial ports.
The command is executed when the last bit is shifted in and the
line is brought low. The execution phase Is ended with the next
serial clock edge.
cio
XFER
(EXECUTE
SPC
COMMAND)
C/O
SDO
SCLK
SPC DATA
REGISTE:R
SCLK
C/O
SPC FUNCTIONAL DESCRIPTION
The Serial Protocol Channel (SPC) has been optimized for the
minimum number of pins and the maximum flexibility. The data is
passed in on a Serial Data Input pin (SOl) and out on a Serial Data
Output pin (SDO). The transfer of the data is controlled by a Serial
Clock (SCLK) and a Command/Data mode input (C/O). These four
pins are the basic SPC pins. To the outside, the SPC appears as
two serial shift registers in parallel-one for command and the
other data. The serial clock shifts data and the Command/Data
(CiO) line selects which register is being shifted. The command
S13-50
ITEy
SCLK
XFER
CD 10 CD
1
IDT7M6032 512K (16Kx 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SPC data and commands are shifted in through the SOl pin,
which is a serial input pin, and out through the SOO pin, which is a
serial output pin. Data and commands are shifted in Least Significant Bit first; Most Significant Bit last (Yo = LSB, Y 15 = MSB). Execution of SPC commands is performed by stopping the shift clock,
SCLK, and lowering the C/o line from high-to-low. Later the SCLK
. may then be transitioned from low-to-high. SPC commands and
data can be shifted anytime, without regard for operation. During
the execution phase, care must be taken that there is no conflict
between the SPC operation and parallel operation. This means that
if the SPC operation attempts to load the parallel data register (opcode 10) while PCLK is in transition, the results are undefined. In
general, it is required that the PCLK be static during SPC operations. The synchronous commands (opcode 3 and 13), however,
allow the PCLK to run. In these operations, the high-to-Iow transition of the C/O line takes on the function of an arm signal in preparation for the next low-to-high transition of the PCLK.
SDI
Y ~ SPC Data (Inst. 0)
D
SERIAL
PROTOCOL
SCLK
DATA
CII)
SPC COMMANDS
PCLK
&
COMMAND
SDO
There are 16 possible SPC opcodes. Fourteen of these are utilized, the other two are reserved and perform NO-OP functions. The
top eight opcodes, through 7, are reserved for transferring data
into the SPC data register for shifting out. The lower eight opcodes,
8 through 15, are used for transferring data from the SPC data register to other parts of the device. Two of the commands are also
used for connecting the data in and out pins.
Y
a
OPCODE
SDI
D
SPCCOMMAND
0
1
Y to SPC Data Register
2
3
4
D to SPC Data Register
Y to SPC Data Register Synchronous w/PCLK
5
Connect Y to D
6-7
Data Register ~ SPC Data (Inst. 1)
SERIAL
PROTOCOL
Parallel Data Register to SPC Data Register
SCLK
DATA
C/f)
Status (OE y, PCLK) to SPC Data Register
8
SPC Data to Y (OE is overidden)
SPC Data to D
10
11
SPC Data to Parallel Data Register
12
Select Stub Mode
13
SPC Data to Parallel Data Register Synchronous
w/PCLK
OE'y
REGISTERS
Reserved (NO-OP)
9
PCLK
&
COMMAND
SDO
Y
Select Serial Mode
14
Connect D to Y (OE is overidden)
15
NO-OP
D ~ SPC Data (Inst. 2)
SDI
Opcode 0 is used fortransferring data from the Youtput pins into
the SPC data register. Opcode 1 transfers data from the output of
the register, before the tri-state gate, into the SPC data register.
Opcode 2 transfers data from the 0 input pins into the SPC data
register.
D
SERIAL
PROTOCOL
SCLK
DATA
c/f)
PCLK
&
COMMAND
'O-----OEy
REGISTERS
SDO
S13-51
Y
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Opcode 3 transfers data on the Y pins to the SPC data register
on the next PCLK, thus achieving a synchronous observation of the
SPC data register in real time. This operation can be fQ!ced to repeat without shifting in a new command by pulsing C/D low-highlow after each PCLK. As soon as data Is shifted out using SCLK, the
command Is terminated and must be loaded in again.
Opcode 5 connects Y to D. Opcodes 6 and 7 are reserved,
hence designated NO-OP.
Connect Y to D (Inst. 5)
SDI
SERIAL
PROTOCOL
Y -+ SPC Data Synchronous w/PCLK (Inst. 3)
SCLK
D
SDI
D
C/D'
SERIAL
PROTOCOL
DATA
&
COMMAND
PCLK
REGISTERS
0r:y
SCLK
DATA
&
COMMAND
C/L>
Y
SDO
REGISTERS
SPC Data -+ Y (Inst. 8)
D
SDI
SDO
Y
SERIAL
PROTOCOL
SCLK
PCLK
DATA
C/l)
Opcode 4 is used for loading status into the SPC data register.
The format of bits is shown below.
7
6
5
&
COMMAND
A)-----
REGISTERS
0r:y
0
loeYlpCLK~
SDO
Y
Opcode 8 is used for transferring SPC data directly to the Ypins.
When executing opcode 8, the state of OEy is a "do not care"; that
is, data will be output even if O'E y = HIGH. Opcode 9 is used for
transferring SPC data to the D pins. Qperands 8 and 9 can be temporarily suspended by raising the C/D input and resumed by lowering the C/[). As soon as SCLK completes tranSition, the command is terminated.
Status -+ SPC Data (Inst 4)
SDI
SPC Data -+ D (Inst 9)
D
SERIAL
PROTOCOL
SCLK
C/O
SCLK
DATA
&
COMMAND
PCLK
REGISTERS
0r:y
SDO
C/l5
DATA
&
COMMAND
PCLK
REGISTERS
0r:y
SDO
Y
S13-52
Y
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Opcode 10 is used for transferring data from the SPC data register into the parallel data register, irrespective of the state of PCLK.
However, PCLK must be static between
going high-ta-Iow and
SCLK going low-to-high.
cio
STUB MODE
DEVICE #2
DEVICE #3
DEVICE #4
SDI--4r--,---~---,--~4r--.---;-~SDO
SPC Data -+ Parallel Data Register (Inst10)
SDI
D
SDI--;----r---r~--r_--~~
SERIAL
PROTOCOL
SCLK
DATA
COM~AND '-~'----...----""
C/!5
PCLK
Opcode 13 transfers data from the SPC data register to the parallel data register on the next PCLK. Opcode 14 connects the 0 bus
to the Y. Operation 14 can be temporarily suspended by raising the
input and resumed by lowering the C/O input again. The operation is terminated by SCLK.
REGISTERS
cio
SPC Data ~ Parallel Data Register Synchronous w/PCLK (Inst13)
Y
SDO
SDI
Opcodes 11 and 12 are used to set Serial and Stub Mode, respectively. After executing one of these opcodes, the device remains in this mode until programmed otherwise. The Serial mode
is the default mode that the IOT49FCT818 powers up in. In Serial
mode, commands are shifted through the SPC command register
and then to the SOO pin. This is the typical mode used when several varieties of devices that utilize the SPC access method are employed on one serial ring.
SERIAL
PROTOCOL
SCLK
DATA
C/D
SERIAL MODE
DEVICE #1
SDI
DEVICE #2
DEVICE #3
DEVICE #4
D
COM~AND r-V~--"""T"--"';::;,;;;rREGISTERS
DEVICE #5
SDO
In Stub mode, SOl is connected directly to SOO. In this way, the
same diagnostic command can be loaded into multiple devices of
like type. For example, in four clock cycles the same command
could be loaded into 8 IOT49FCT818s (64-bit pipeline register).
Dissimilar devices must be segregated into serial scan loops of
similar type, as shown below. During the command phase, the serial shift clock must be slowed down to accommodate the delay
from SOl to SOO through all of the devices. The slower clock is typically a small tradeoff compared to the reduced number of clock
cycles.
SDO
Connect 0 to Y (Inst 14)
SDI
D
SERIAL
PROTOCOL
SCLK
C/D
PCLK
DATA
&
COMMAND
REGISTERS
SDO
S13-53
y
-0--------
OE"y
IDT7M6032 512K (16K x 32) WRITABLE
CONTROL STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The ability to continuously execute a synchronous command
can provide major benefits. For example, the synchronous read
(Instruction 3, Y to SPC data) instruction could be clocked into the
SPC data regi§!er. Then, it could be continuously executed by
pulsing the C/D line high. When the whole system is stopped
(PCLK quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted out
and the current state of the parallel register can then be observed,
allowing for the observation of two states of the para"el register (the
current and the previous).
As companies like IDT continue to integrate more onto each device and put each device into smaller packages such as surface
mount devices, the board level ,testing becomes more complex for
the designer and the manufacturing divisions of companies. To
help this situation, serial diagnostics was invented. This allows for
observation of critical signals deep within the system. During system test, when an error is observed, these signals may be modified
in order to zero in on the fault in the system.
Serial diagnostics is primarily a scheme utilizing only a few pins
(4) to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults. It can be used at
many points in the life of a product: design debug and verification,
manufacturing test and field service. This document describes a
serial diagnostic scheme which was developed at lOT and wi" be
used in future VLSI logic devices designed by lOT.
Opcodes 3 and 13 transfer data sY!lchronous to the PCLK which
means that the high-to-Iow on the C/D input is an arm signal. The
data and command can be shifted in while the PCLK is running.
The ci5 line is dropped priorto the desired PCLK edge and raised
before the next edge. Instruction 13 can be repeated over many
times by leaving the C/O line low during multiple transitions of the
PCLK while not clocking SCLK. PCLK cycles can even be skipped
by raising the C/O input during the desired clock periods. Instruction 3 can be repeated by pulsing the C/O high after each PCLK.
c/o
SCLK
EXECUTE
(SPCCMD)
PCLK
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DATAoUT
~
2550
:q
5V
4800
DATAoUT
30pF*
2550
Figure 1. Output Load
ORDERING INFORMATION
XXXXX
Device Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
RM~
~--------------~
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Blank
B
Commercial (O°C to + 70°C) Only
Military (-55°C to + 125°C)
Semiconductor Components
Compliant to MIL-STD-883.
Class B
C
Ceramic DIP
25
30
35
Commercial Only
}
45
55
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
'-------------------------1
813-54
S
7M6032
5pF*
Figure 2. Output Load
(for t oLZ • t cHZ ' t OHZ '
tWHZ and tow)
* Including scope andjig.
IDT
4800
Mil only
Standard Power
16K x 32 WCS Module
Spoed In NM"'OOOnd,
.-.-
..
--- .... -.-... _..._ - - - -
t;)
Integrated Device1ech.nolosy.lnc.
4K x 80 WRITABLE
CONTROL STORE STATIC
RAM MODULE WITH
ON-BOARD SEQUENCER
PRELIMINARY
lOT 7M6052
Since each of the RAMs have their own external output enabled,
either or both of these fields can be overridden from an external
source, i.e. by negating OE (0-1S). Y(0:1S) is placed in the Hi-Z
mode, allowing the 0 (0: 11) inputs to the sequencer to be driven
from an external source (Similarly forY(16:32), which includes the
I(0:3) field). The output from the sequencer drives the addresses of
all of the RAMs. All the control, clocks and flags of the sequencer
are connected directly to module pins for external control. (For
additional details on how the sequencer operates, please refer to
the IDT39C10 data sheet.) All controls and clocks, except for
output enables, parity and the serial data path, are bussed to all
RAMs and connected to module pins for external control. The
serial data path is daisy chained through the five RAMs to give an
80-bit SPC configuration. (For additional information on the RAM
operation, please refer to the IDT71S02 data sheet).
The WCS can be loaded using either the serial data path and the
SPC controls, or in parallel from the Y(0:79) pins, again using the
SPC controls. The address for the RAMs will either be from the internal counter in each RAM for loading sequential locations, or by
external control of the sequencer.
The parity output from each RAM is connected to a module pin
and also to an input of the on-board comparator. The five RAM
parities, together with 3 additional parity inputs (PAR_A to PAR_C),
are compared to PAR_P (tied to all 8 inputs of the other side of the
comparator) to generate PAR_OK
The semiconductor components used on all lOT milatary
modules are maufactured in compliance with the latest revision of
MIL-STD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
FEATURES:
• Serial Protocol Channel (SPC™) reading, writing and interrogation
• Separate chip select, write enable and output enable memory
controls
• High fanout pipeline register
• Fully width-expandable
• Designed for high-speed writable control store applications
• Assembled with lOT's high-reliability vapor phase solder reflow
process
• Compact 128-pin ceramic QIP (quad in-line package)
• Single SV (+/- 10%) power supply
• Inputs and outputs directly TTL-compatible
• Military modules available with semiconductor components
manufactured in compliance to MIL-STD-883, Class B
DESCRIPTION:
The IDT7M60S2 is a 4K x 80 Writable cOntrol Store with onboard sequencer, on a multilayer co-fired ceramic substrate, using
five IDT71S02 (4K x 16 registered RAMs), an IDT39C10 (12-bit sequencer) and an IDTS4/74FCTS21 (8-bit comparator) for parity
verification. The IDT7M60S2 is offered in a 128-pin, 600 mil wide
quad in-line package (QIP).
In normal operation (Read Mode), the 0(0:11) inputs of the sequencer are driven by the Y (0: 11) outputs of the first RAM and the
1(0:3) inputs are driven by the Y(16:19) outputs ofthe second RAM.
FUNCTIONAL BLOCK DIAGRAM
SDI
ADDR
CONT
12.,
/
D
,4.,
I
39C10
Y
FLAGS
CONT
5x71502
YO-79
PAR
PAR (X)
SDO
5.,
"
FCT521
PAR_X
PAR OK
f
PAR. P
CEMOS and SPC are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated Device Technology, Inc.
JANUARY 1989
DSC--7035/-
513-55
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PINOUT CONFIGURATION
GND
Y(O)
Y(2)
Y(4)
Y(6)
Y(8)
~10)
~12)
(14)
PAIJ0.15)
<51:(0.15)
PAR-OK
C/O
~
Y(16)
Y(18)
Y(20)
Y(22)
Y(24)
Y(26)
Y(28)
Y(30)
PAR (16.31)
~(m
rorr
Y(32)
Y(34)
Y(36)
Y(38)
Y(40)
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
72
73
74
75
76
GND
Y(l)
Y(3)
Y(5)
Y(7)
Y(9)
Y(11)
y(13)
Y(15)
SOUT
PAR A
PAR-B
PAR-C
CLKY(17)
GND
Y(19)
Y(21)
Y(23)
Y(25)
Y(27)
Y(29)
Y(31)
PAR P
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Vee 128
~79) 127
~77) 126
~75) 125
~73) 124
(71) 123
~69) 122
(67) 121
~65) 120
SIN 119
CSo 118
117
116
SCLK 115
114
113
~59) 112
~57) 111
.1,55) 110
(53) 109
~51) 108
107
PAR (~~ 106
-CI 105
CC 104
CP 103
CCEN 102
~ 101
~47) 100
99
-1,45)
98
l.J"8l 97
~
M32(1)
MAP
V'ECT
Y(33)
Y(35)
~37)
~39)
J,41)
G~681
m
cc
Vee
Y(78)
Y(76)
~74)
V~~)
Y(68)
Y(66)
Y(6~
~9)
(64·79)
BKPT
TNiT
SOE'
Y62)
Y(61)
~60)
~~:~
~54)
(52)
y(50)
Y(4~
b~ (48-63)
~48.63)
b'i:;
(32·47)
32-47)
~46)
(44)
42
Y(
GN
b
alP
TOP VIEW
NOTE:
1. For module dimensions, please refer to module drawing M32 in the
packaging section.
PIN DESCRIPTIONS
NAME
FUNCTION
'CS 0- 2
Chip Select
WE
Write Enable
sm:
Synchronous Output Enable
CLK
Clock (to register)
INlT
Initialize
BKPT
Breakpoint Detect
PAR 0-79
Parity
SIN
SOUT
SPC Serial DATA IN (l)
SCLK
SPC Clock (1)
CIl5
SPC Command/oa:ta(1)
GND
Ground
Vee
Power
PIN DESCRIPTIONS
PIN NAME
1/0
I
Tristates internal address bus for
71502s.
CC
I
Used as test criterion. Pass test is a
LOW on CC'.
CCEN
I
Whenever the signal is HIGH, CC Is
Ignored and the part operates as
though CC'were true (LOW).
CI
I
Low order carry input to incrementer
for microprogram counter.
RLD
I
When LOW forces loading of register/counter regardless of instruction
or condition.
OE (0-79)
I
CP
I
YI
0
Address to microprogram memory.
Yo is LSB, Y79 is MSB.
FULL
0
Indicates that 33 items are on the
stack.
Pi:
0
Can select #1 source (usually Pipeline Register) as direct input source.
t1Af5
0
Can select #2 source (usually Mapping PROM or PLA) as direct input
source.
VE"Cf
0
Can select #3 source (for example,
Interrupt Starting Address) as direct
input source.
PAR_OK
0
5 RAM parity bits, together with
3 parity inputs are compared to
generate PAR OK.
PAR_P
I
Generated from ail 8 inputs from
the other side of the comparator.
PAR IN
I
Parity input
PAR (A-C)
I
Parity inputs combined with the on
board parity with the 71502 to generate
parity across 8 bits for parity O.K.
SPC Serial DATA oUT (l)
NOTE:
1. The Serial Protocol Channel (SPC) is
discussed at length in IDT Application Note 16.
S13-56
DESCRIPTION
~
Three-state control of YI outputs.
Triggers all internal state changes at
LOW-to-HIGH edge.
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
Commercial
50
mA
DC Output Current
50
loUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA=
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V
Vee
±
10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
-
6.0
V
O.S
V
-0.5(1)
Input Low Voltage
UNIT
V
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
+25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYP.
UNIT
C1N(D)
Input Capacitance
(Data)
V1N = OV
15
pF
C1N(A)
Input Capacitance
(Control)
V1N = OV
50
pF
COUT
Output Capacitance
(Data)
VOUT= OV
15
pF
SYMBOL
AMBIENT
TEMPERATURE
-55°C to + 125°C
NOTE:
1. This parameter is sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V -+ 10%
SYMBOL
PARAMETERS
TEST CONDITIONS
Vcc = Max.
V1N = GND to Vcc
COM·L.
COM'L.
MIL.
COM'L.
MIL.
!lui
Input Leakage
(Address & Control)
Ilul
Input Leakage
(Data)
Vcc = Max.
V1N = GND to Vcc
MIL.
!lLOI
Output Leakage
Vcc = Max.
CS = VIH, VOUT = GND to Vcc
VOL
Output Low Voltage
Vcc = Min., IOL = SmA
VOH
Output High Voltage
Vcc = Min., IOH = -4mA
MIN.
MAX.
UNIT
-
20
50
~A
-
-
5
10
5
10
0.4
2.4
-
7M6052S45
COM'L. MIL.
7M6052S55
COM'L MIL
-
~A
~A
V
V
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V -+ 10%
SYMBOL
PARAMETER
TEST CONDITIONS
7M6052S25
7M6052S35
COM'L.ONLY COM'L. MIL.
UNIT
ICCl
Operating CUrrent
f = 0, CS = V1L
Vcc = Max.; Output Open
850
825
925
825
925
825
925
mA
ICC2
Dynamic Operating
Current
Vcc = Max.; CS = V1L
f = fMAX' Output Open
1350
1300
1400
1225
1300
1175
1250
mA
S13-57
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±10%
READ CYCLE
SET UP AND HOLD TIMES W.R.T. CLK (NOTE 1)
7M6052S35
7M6052S25
SYMBOL
7M6052S45
PARAMETER
7M6052S55
UNITS
tS
tH
tS
tH
tS
tH
tS
Address A(0:11)
25
0
35
0
45
0
55
0
ns
tcs
ChipSelCS
10
-
12
15
10
-
12
-
ns
Sync OE SOE
-
20
ts
-
MAX.
UNITS
tAS. tAH
15
tH
20
ns
PARAMETER
Prop Delay ClK to Y(0:9)
SET UP AND HOLD TIMES W.R.T. CP (NOTE 2)
(For All Speed Grades)
PARAMETER
COMBINATION DELAYS
(For All Speeds)
tS
tH
UNITS
Data 0(0:11) to REG/CNT
6
0
ns
0(0:11) to A(0:11)
12
ns
Data 0(0:11) to PROG CNT
13
0
ns
1(0:3) to A(0:11)
20
ns
Instruction 1(0:3)
23
0
ns
1(0:3) to source con7
12
ns
Test FlagCC
15
0
ns
CCtoA(0:11)
16
ns
15
0
ns
ccrntoA(0:11)
16
ns
Carry in CI
6
0
ns
CP to A(0:11)
28
ns
Reload RlO
11
0
ns
CP to FU[[
22
ns
OE'toA(0:11)
10
ns
Test Flag EN
CErn
READ CONTROL
7M6052S25
SYMBOL
PARAMETER
tOE
ASYNC
toz
ASYNC
tsoE
SYNC
tsoE
SYNC
tpAR
Individual Parity
t pAR -
OK
7M6052S35
7M6052S45
MIN.
MAX.
MIN.
MAX.
-
14
-
14
-
22
-
35
-
30
30
40
-
45
-
17
17
S13-58
7M6052S55
UNITS
MIN.
MAX.
MIN.
MAX.
17
-
25
-
25
-
30
17
30
ns
35
ns
35
ns
45
-
55
ns
55
-
65
ns
22
30
ns
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7M6052S35
7M6052S25
PARAMETER
SYMBOL
MIN.
7M6052S55
7M6052S45
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
50
UNITS
MAX.
tlW
INIT Pulse Width
35
-
40
35
-
40
50
-
-
INIT REC TIME
-
60
tlR
60
-
ns
tlNIT
INIT REC to Y(0;79)
-
50
-
55
-
70
-
85
ns
ns
CLOCKS
7M6052S25
PARAMETER
7M6052S45
7M6052S35
7M6052S55
UNITS
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
25
-
25
-
ns
20
-
ns
ClK High Min
15
-
15
-
20
ClK low Min
15
-
15
20
CP High Min
20
-
20
-
CP low Min
20
-
20
-
20
20
20
ns
ns
WRITE CYCLE
7M6052S25
SYMBOL
7M6052S35
7M6052S45
7M6052S55
PARAMETER
MIN.
MAX.
twc
Write CYC Time
40
tWAS
Address SU
2
tw
Write Pulse Width
tow
t WOH
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
-
50
-
65
2
-
5
25
-
30
50
Data to End of Write
17
20
25
-
30
Data Hold Time
0
0
-
0
CS to End of Write
25
30
-
50
tWR
Write Recovery
5
5
-
5
tAW
Addr Valid to End of Write
30
35
-
55
-
0
t wcw
-
-
-
80
-
5
60
60
5
65
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
SPC ALL SPEEDS
SYMBOL
PARAMETER
MIN.
tSCLK
SClK Period
100
tscw
SCLK Pulse Width
45
tsos
Serial Data Set-up Time
20
MAX.
-
UNITS
ns
ns
ns
tSOH
Serial Data Hold Time
5
-
ns
tsco
Clock to Serial Data Output Delay
35
ns
120
ns
tspo
Serial Data-In-to-Out Delay, Stub Mode
-
tCMLH
t CMHC
Command/Data Set-up Time, Low-to-High(2)
20
-
ns
Command/Set-Up Time, High-to-Low (Execution Time)(2)
40
-
ns
tCMH
Command/Data Hold Time(2)
20
-
ns
NOTES:
1. Since A(0:11) are being driven by the O/P of the 39C10 the delays from the sequencer must be added to the A(0:11) set time.
2. D (0:11) and I(0:3) are being driven by the O/P of two 71502s, Y (0: 11 ) and Y(16:19), therefore the delay of ClK to Y (0:79) must be added to the set up time for
the approximate parameters.
S13-59
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE (1)
twc
ADDRESS
~
~K
)K
t wcw
~t\.
/
/..- t WRtwp
tWAS
'r\.
/"
.1 ..
DATA IN
NOTE:
A write occurs during the overlap of both CS and
1.
W'C.
low.
TIMING WAVEFORM OF READ CYCLE
ADDRESS
~x
DATA VALID
'6-79
elK
The following descriptions are supplemental. Selected portions of the 39C10 and the 71502 data sheets are attached for further understanding of the 7M6052.
513-60
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 PRODUCT DESCRIPTION
The IDT39C10s are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed microprogrammable microprocessor applications. The sequencers allow for direct control of up to 4K words of microprogram.
The heart of the microprogram sequencers is a 4-input mUltiplexer that is used to select one of four address sources to select
the next microprogram address. These address sources include
the register/counter, the direct input, the microprogram counter or
the stack as the source for the address of the next microinstruction.
The register/counter consists of twelve D-type flip-flops which
can contain either an address or a count. These edge-triggered
flip-flops are under the control of a common clock enable, as well
as the four microinstruction control inputs. When the load control
(RLD) is LOW, the data at the D inputs is loaded into this register on
the LOW-to-HIGH transition of the clock. The output of the register/
counter is available at the multiplexer as a possible next address
source for the microcode. Also, the terminal count output associated with the register/counter is available at the internal instruction
PLA to be used as a condition code input for some of the microinstructions. The IDT39C10s contain a microprogram counter that
usually contains the address of the next microinstruction compared to that currently being executed. The microprogram counter
actually consists of a 12-bit incrementer followed by a 1.2-bit register. The microprogram counter will increment the address coming
out of the sequencer going to the microprogram memory if the
carry-in input to this counter is HIGH; otherwise, this address will
be loaded into the microprogram counter. Normally, this carry-in
input is set to the logic HIGH state so that the incrementer will be
active. Should the carry-in input be set LOW, the same address is
loaded into the microprogram counter. This is a technique that can
be used to allow execution of the same microinstruction several
times.
There are twelve D-inputs on the IDT39C10s that go directly to
the address multiplexer. These inputs are used to provide a branch
~ddress that can come directly from the microcode or some other
external source. The fourth input available to the multiplexer for
next address control is the 33-deep, 12-bit wide LIFO stack. The
LIFO stack provides return address linkage for subroutines and
loops. The IDT39C10s contain a built-in stack pointer that always
points to the last stack location written. This allows for stack refer..:
ence operations, usually called loops, to be performed without
popping the stack.
The stack pointer internal to the IDT39C10s is actually an up/
down counter. During the execution of microinstructions one, four
and five, the PUSH operation may occur depending on the state of
the condition code input. This causes the stack pointer to be incremented by one and the stack to be written with the required return
linkage (the value contained in the microprogram counter). On the
microprogram cycle following the PUSH, this new return linkage
data that was in the microprogram counter is now at the new location pointed to by the stack pointer. Thus, any time the multiplexer
looks at the staCk, it will see this data on the top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. If the pop occurs, the stack pointer is
decremented at the next LOW-ta-HIGH transition of the clock. A
pop decrements the stack pointer which is the equivalent of removing the old information from the top of the stack.
The IDT39C10s are designed so that the stack pointer linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack can grow to a full 33 locations. After a
depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information
at the top ofthe stack will be destroyed butthe stack pointer will not
end around. It is necessary to initialize the stack pointer when
power is first turned on. This is performed by executing a RESET
instruction (Instruction 0). This sets the stack pointer to the stack
empty position - the equivalent depth of zero. Similary, a pop from
S13-61
an empty stack may place unknown data on the Youtputs, but the
stack pointer is designed not to end around. Thus, the stack pointer
will remain at the 0 or stack empty location if a pop is executed
while the stack is already empty.
The IDT39C10s' internal 12-bit register/counter is used during
microinstructions eight, nine and fifteen. During these instructions,
the 12-bit counter acts as a down counter and the terminal count
(count = 0) is used by the internal instruction PLA as an input to
control the microinstruction branch test capability. The design of
the internal counter is such that, if it is pre loaded with a number N
and then this counter is used in a microprogram loop, the actual
sequence in the loop will be executed N + 1 times. Thus, it is possible to load the counter with a count of 0 and this will result in the
microcode being executed one time. The 3-way branch microinstruction, Instruction 15, uses both the loop counter and the external condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way branch
may result in the next address coming from the D inputs, the stack
or the microprogram counter.
The IDT39C1 Os provide a 12-bit address at the Y outputs that are
under control of the OE input. Thus, the outputs can be put in the
three-state mode, allowing the writable control store to be loaded
or certain types of external diagnostics to be executed.
. In summary, the IDT39C10s are the most powerful microprogram sequencers currently available. They provide the deepest
staCk, the highest performance and the lowest power dissipation
for today's microproQrammed machine design.
IDT39C10 OPERATION
The IDT39C10s are CMOS pin-compatible implementations of
the Am291 0 & 291 OA microprogram sequencers. The IDT39C1 O's
microprogram is functionally identical except that it provides a
33-deep stack to give the microprogrammer more capability in
terms of microprogram subroutines and microprogram loops. The
definition of each microprogram instruction is shown in the table of
instructions. This table shows the results of each instruction in
terms of controlling the mUltiplexer, which determines the Y outputs, and in controlling the signals that can be used to enable various branch address sources (PL, MAP, VECT). The operation of
the register/counter and the 33-deep stack after the next LOW-taHIGH transition of the clock are also shown. The intemal multiplexer is used to select which of the internal sources is used to drive
the Y outputs. The actual value loaded into the microprogram
counter is either identical to the Y output or the Y output value is
incremented by 1 and placed in the microprogram counter. This
function is under the control of the carry input. For each of the microinstruction inputs only one of the three outputs (PL, MAP,
VECT) will be LOW. Note that this function is not determined by
any of the possible condition code inputs. These outputs can be
used to control the three-state selection of one of the sources for
the microprogram branches.
Two inputs, CC and CCEN, can be used to control the conditional instructions. These are fully defined in the table of instructions. The RLD input can be used to load the internal register/
counter at any time. When this input is LOW, the data at the D inputs
will be loaded into this register/counter on the LOW-ta-HIGH transition of the clock. Thus, the RLD input overrides the internal hold or
decrement operations specified by the various microinstructions.
The OE input is normally LOW and is used as the three-state enable for the Y outputs, The internal stack in the I DT39C1 Os is a lastin/first-out memory that is 12-bits in width and 33 words deep. It has
a stack pointer that addresses the stack and always points to the
value currently on the top of the stack. When instruction 0 (RESET)
is executed, the stack pointer is initialized to the top of the stack
which is, by definition, the stack empty condition. Thus, the contents of the top of the stack are undefined until the forced PUSH
occurs. A pop performed while the stack is empty will not change
iEJ
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
the stack pointer in any way; however, it will result in unknown data
at the Y outputs.
By definition, the stack is full any time 33 more pushes than pops
have occurred since the stack was last empty. When this happens,
the Full Flag will go LOW. This signal first goes LOW on the
microcycle after the 33 pushes occur. When this signal is LOW, no
additional pushes should be attempted or the information on the
top of the stack will be lost.
input to the D inputs on the microprogram sequencer. The JMAP
instruction branches to the address appearing on the D inputs. In
the flow diagram shown in Figure 1, we see that the branch actually
will be to the contents of microinstruction 85 and this instruction
will be executed next.
THE IDT39C10 INSTRUCTION SET
The simplest branching control available In the IDT39C10
microprogram sequencers is that of conditional jump to address.
In this instruction, the jump address is usually contained in the microinstruction pipeline register and presented to the D Inputs. If the
test is passed, the jump is taken while, if the test fails, this Instruction executes as a simple continue. In the example shown in the
flow diagram of Figure 1, we see that if the test is passed, the next
microinstruction to be executed is the content of address 25. If the
test is failed, the microcode simply continues to the contents of the
next instruction.
This data sheet contains a block diagram of the IDT39C10
microprogram sequencers. AS can be seen, the devices are controlled by a 4-bit microinstruction word (13 - 10). Normally, this word
is supplied from one 4-bit field of the microinstruction word associated with the entire state machine system. These four bits provide
for the selection of one of the sixteen powerful instructions associated with selecting the address of the next microinstruction. Unused Y outputs can be left open; however, the corresponding most
significant D inputs should be tied to ground for smaller microwords. This is necessary to make sure the internal operation of the
counter is proper should less than 4K of microcode be implemented. As shown in the block diagram, the internal instruction
PLA uses the four instruction inputs aswell as the CC, CCEN and
the internal counter = 0 line for controlling the sequencer. This internal instruction PLA provides all of the necessary internal control
Signals to control each particular part ofthe microprogram sequencer. The next address at the Y outputs of the IDT39C10s can be
from one of four sources. These include the internal microprogram.
counter, the last-In/first-out stack, the register/counter and the
direct. inputs.
The following paragraphs will describe each instruction associated with the IDT39C1 Os. As a part of the discussion, an example of
each instruction is shown in Figure 1. The purpose of the examples
is to show microprogram flow. Thus, in each example the mIcroinstruction currently being executed has a circle around it. That
is, this microinstruction is assumed to be the contents of the pipeline register at the output of the microprogram memory. In these
drawings, each of the dots refers to the time that the contents of the
microprogram memory word would be in the pipeline register and
is currently being executed.
INSTRUCTION 3CONDITIONAL JUMP PIPELINE (CJP)
INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition independent of the conditional testing, the microprogram counter is
pushed on to the stack. Ifthe conditional test is passed, the counter
will be loaded with the value on the D inputs to the sequencer. Ifthe
test fails, the contents of the counter will not change. The PUSH/
Conditional Load Counter instruction is used in conjunction with
the loop instruction (Instruction 13), the repeat file based on the
counter instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).
INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE
R/PL (JSRP)
This instruction Is used at power up time or at any restart sequence when the need is to reset the stack pointer and jump to the
very first address In microprogram memory. The Jump 0 instruction does not change the contents of the register/counter.
Subroutines may be called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register. In
this instruction the contents of the microprogram counter are
pushed on the stack and the branch address for the subroutine call
will be taken from either the internal register/counter orthe external
pipeline register presented to the D inputs. If the conditional test is
passed, the subroutine address will be taken from the pipeline register. If the conditional test fails, the branch address is taken from
the internal register/counter. An example of this is shown in the flow
diagram of Figure 1.
INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)
The Conditional Jump to Subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will be
contained in the pipeline register and presented at the D inputs. If
the condition code test is passed, a branch is taken to the subroutine. Referring to the flow diagram for the I DT39C1 Os shown in Figure 1, we see that the content of the microprogram counter is 68.
This value is pushed onto the stack and the top of stack pointer is
incremented. If the test is failed, this Conditional Jump to Subroutine instruction behaves as a simple continue. That is, the content
of microinstruction address 68 is executed next.
The Conditional Jump Vector instruction is similar to the Jump
Map instruction in that it allows a branch operation to a microinstruction as defined from some external source, except that it is
conditional. The Jump Map instruction is unconditionaL If the conditional test is passed, the branch is taken to the new address on
the D inputs. If the conditional test is failed, no branch is taken but
rather the microcode simply continues to the next sequential microinstruction. When this instruction is executed, the VECT output
is LOW unconditionally. Thus, an external 12-bit field can be enabled on to the D inputs of the microprogram sequencer.
INSTRUCTION 2JUMP MAP (JMAP)
INSTRUCTION 7CONDITIONAL JUMP R/PL (JRP)
This sequencer. instruction can be used to start different·
microprogram routines based on the machine instruction opcode.
This is typically accomplished by using a mapping PROM as an
The Conditional Jump register/counter or external pipeline register always causes a branch in microcode. This jump will be to one
oftwo different locations in the microcode address space. If the test
INSTRUCTION 0JUMP 0 (JZ)
813-62
· IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INSTRUCTION 12lOAD COUNTER AND CONTINUE (lDCT)
is passed, the jump will be to the address presented on the D inputs
to the microprogram sequencer. If the conditional test falls, the
branch will be to the address contained in the intemal register/
counter.
The Load Counter and Continue instruction is used to place a
value on the D inputs in the register/counter and continue to the
next microinstruction.
INSTRUCTION 8REPEAT lOOP COUNTER NOT EQUAL TO 0
(RFCT)
INSTRUCTION 13TEST END OF lOOP (lOOP)
This instruction utilizes the loop counter and the stack to implement microprogrammed loops. The start address for the loop
would be initialized by using the PUSH/Conditional Load Counter
instruction. Then, when the repeat loop instruction is executed, if
the counter is not equal to 0, the next microword address will be
taken from the stack. This will cause a loop to be executed as
shown in the Figure 1 flow diagram. Each time the microcode sequence goes around the loop, the counter is decremented. When
the counter reaches 0, the stack will be popped and the microinstruction address will be taken from the microprogram counter.
This instruction performs a timed wait or allows a single sequence
to be executed the desired number of times. Remember, the actual
number of loops performed is equal to the value in the counter plus
The Test End of Loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the conditional test input is failed, the loop branch address will be that on the
stack. Since we may go around the loop a number of times, the
stack is not popped. If the conditional test input is passed, then the
loop is terminated and the stack is popped. Notice that the loop instruction requires a PUSH to be performed at the instruction immediately prior to the loop return address. This is necessary so as to
have the correct address on the stack before the loop operation. It
is forthis reason that the stack pointer always points to the last thing
written on the stack.
INSTRUCTION 14CONTINUE (CONT)
1.
INSTRUCTION 9REPEAT PIPELINE COUNTER NOT EQUAL TO 0
(RPCT)
Continue is a simple instruction where the address for the microinstruction is taken from the microprogram counter. This instruction simply causes sequential program flow to the next microinstruction in microcode memory.
This instruction is another technique for implementing a loop
using the counter. Here, the branch address for the loop is contained in the pipeline register. This instruction does not use the
stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be taken
from the D inputs of the microprogram sequencer. When the
counter reaches 0, the internal multiplexer will select the address
source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.
INSTRUCTION 15THREE WAY BRANCH (1WB)
The Three-Way Branch instruction is used for looping while
waiting for a conditional event to come true. If the event does not
come true after some number of microinstructions, then a branch is
taken to another microprogram sequence. This is depicted in Figure 1 showing the IDT39CW's flow diagram and is also described
in full detail in the IDT39C10's instruction operational summary.
Operation of the instruction is such that any time the extemal conditional test input is passed, the next microinstruction will be that
associated with the program counter and the loop will be left. The
stack is also popped. Thus, the extemal test input overrides the
other possibilities. Should the external conditional test input not be
true, the rest ofthe operation is controlled by the internal counter. If
the counter is not equal to 0, the loop is taken by selecting the address on the top of the stack as the address out of the Y outputs of
the IDT39C10s. In addition, the counter is decremented. Should
the external conditional test input be failed and the counter also
have counted to 0, this instruction "times out". The result is that the
stack is popped and a branch is taken to the address presented to
the D inputs of the IDT39C10 microprogram sequencers. This address is usually provided by the extemal pipeline register.
INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating subroutines. The fact that it is conditional allows the subroutine either
to be ended or to continue. If the conditional test is passed, the
address of the next microinstruction will be taken from the stack
and it will be popped. If the conditional test fails, the next microinstruction address will come from the internal microprogram
counter. This is depicted in the flow diagram of Figure 1.lt is important to remember that every subroutine call must somewhere be
followed by a return from subroutine call in order to have an equal
number of pushes and pops on the stack.
INSTRUCTION 11 CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The Conditional Jump Pipeline and Pop instruction is a technique for exiting a loop from within the middle of the loop. This is
depicted fully in the flow diagram for the IDT39C10s as shown in
Figure 1. The conditional test input for this instruction results in a
branch being taken if the test is passed. The address selected will
be that on the D inputs to the microprogram sequencer and, since
the loop is being terminated, the stack will be popped. Should the
test be failed on the conditional test inputs,the microprogram will
simply continue to the next address as taken from the
microprogram counter. The stack will not be affected if the conditional test input is failed.
CONDITIONAL TEST
Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inRuts associated with the conditional test input. These include the CCEN and
the ~ inputs. The CCEN input is a condition code enable. Wh,enever the CCEN input is HIGH, the ~ input is ignored and the device operates as though the ~ input were true (LO'!'{). Thus, a fail
of the external test condition can be defined as CCEN equalS LOW
and ~ equals HIGH. A pass condition is defined as a CCEN equal
to HIGH or a ~ equal to LOW. It is important to recognize the full
function of the condition code enable and the condition code inputs in order to understand when the test is passed or failed.
S13-63
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTION OPERATIONAL SUMMARY
13- 10
MNEMONIC
CC
COUNTER
TEST
0
JZ
X
X
1
CJS
PASS
FAIL
X
X
2
JMAP
X
X
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
X
X
=0
NOT = 0
=0
NOT = 0
3
CJP
4
PUSH
5
JSRP
6
CJV
7
JRP
8
RFCT
X
X
9
RPCT
X
X
10
CRTN
X
X
11
CJPP
PASS
FAIL
PASS
FAIL
12
LDCT
X
13
LOOP
PASS
FAIL
X
X
X
14
CONT
X
X
TWB
PASS
PASS
FAIL
FAIL
=0
NOT = 0
=0
NOT = 0
15
X
X
X
X
X
X
X
X
X
X
STACK
ADDRESS
SOURCE
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP,
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC
0
D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK
NC = No Change; DEC = Decrement
S13-64
REGISTER!
COUNTER
NC
NC
NC
NC
.'NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC
ENABLE
SELECT
]5[
PL
]5[
MAP
]5[
]5[
PL
]5[
PL
Pi:
VEcr
VEeT
]5[
]5[
PL
]5[
Pi:
Pi:
]5[
PC
]5[
PC
Pi:
]5[
PC
'P[
PL
Pi:
]5[
]5[
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIGURE 1. IDT39C10B
FLOW DIAGRAMS
.
.
o Jump Zero (JZ)
2 Jump Map (JMAP)
1 Cond JSB PL (CJS)
65~
66
67
68
:HSTACK
67
40
68
41
69
42
70
43
4 Push/Cond LD CNTR (PUSH)
3 Cond Jump PL (CJP)
65h
66
67 •
68
.
69
67
68
35
36
8 Repeat Loop. CNTR "F- 0
~
66
N
20
21
(~FCT)
65
( e ) - - + - - - - t _ 40
65t
66 •
67
68
30
31
32
33
34
A
5
66
67
6 •
.
30
31
9 Repeat PL, CNTR "F- 0 (RPCT)
10 Cond Return (CRTN)
(PUSH)
REGISTER!
COUNTER
11 Cond Jump PL & POP (CJPP)
STACK
66 (PUSH)
14 Continue (CONT)
REGISTER/
COUNTER
STACK
68
69 •
70
66
67
68
69
70
71
.
N
7 Cond JUMP R/PL (JRP)
66
65h
:
67
5 Cond JSB R/PL (JSRP)
65~8
STACK
66
25
26
6 Cond Jump Vector (CJV)
67 •
68
69
85
86
41
42
65pCOUNTER
66
(LDCT)
65
67
68
r
66
67
68
69
70
12 LD CNTR & Continue (LDCT)
65
66 •
67
68
N
COUNTER
13 Test End Loop (LOOP)
.
15 Three-Way Branch (TWB)
65
66
67
68
69
30
31
32
33
34
35
36
37
7
f$1
N
72
73
S13-65
STACK
(PUSH)
REGISTER/
COUNTER
65
66
67
68
69
70
71
72
STACK
(PUSH)
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTIONS
13 - 10 MNEMONIC
NAME
REG!
CNTR
CONTENTS
CCEN =
FAIL
LOW and
CC =
Y
STACK
HIGH
'C'C'EN =
PASS
HIGH or
CC =
Y
STACK
LOW
REG!
CNTR
ENABLE
0
JZ
Jump Zero
X
0
CLEAR
0
CLEAR
HOLD
PL
1
CJS
Cond JSB PL
X
PC
HOLD'
D
PUSH
HOLD
JS[
2
JMAP
Jump Map
X
D
HOLD
D
HOLD
HOLD
MAP
3
CJP
Cond Jump PL
X
PC
HOLD
D
HOLD
HOLD
JS[
4
PUSH
PUSH/Cond Ld Cntr
PC
PUSH
PC
PUSH
Note 1
PL
5
JSRP
Cond JSB R/PL
X
X
R
PUSH
D
PUSH
HOLD
JS[
6
CJV
Cond Jump Vector
X
PC
HOLD
D
HOLD
HOLD
VECT
7
JRP
Cond Jump R/PL
X
R
HOLD
F
HOLD
DEC
1S[
40
F
HOLD
F
HOLD
DEC,
PL
JS[
8
9
RFCT
RPCT
Repeat Loop, CNTR '" 0
=0
PC
POP
PC
POP
HOLD
40
D
HOLD
D
HOLD
DEC
PL
=0
X
PC
HOLD
PC
HOLD
HOLD
JS[
PC
HOLD
F
POP
HOLD
PL
PC
HOLD
D
POP
HOLD
JS[
Repeat PL, CNTR 4 0
10
CRTN
Cond RTN
11
CJPP
Cond Jump PL & POP
12
LDCT
LD Contr & Continue
X
X
PC
HOLD
PC
HOLD
LOAD
PL
13
LOOP
Test End Loop
X
F
HOLD
PC
POP
HOLD
JS[
14
CONT
Continue
15
lWB
X
PC
HOLD
PC
HOLD
HOLD
PL
+-0
F
HOLD
PC
POP
DEC
'J5[
=0
D
POP
PC
POP
HOLD
Pi:
Three-Way Branch
NOTE:
1. If CCEN = LOW and CC = HIGH, hold; else load. X = Don't Care
S13-66
~~~~~~~~~~~~-
--.. -.------- ..
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
-.-.-----~--------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71502 DESCRIPTION
SPC FUNCTIONAL BLOCK DIAGRAM
COMMAND DATA (C/O) --~--------------------------~
SERIAL DATA IN
(SI) ---+-------,---------------...----~
SERIAL DATAoUT
(SO)
SERIAL CLOCK (SCLI<) - - r - - t - - - - - L - - . /
I-------t-----!~
I....-----""T""-----..I
MUX ENABLES
AND REGISTER
STROBES, ETC.
DATA
CLK
16
DIAGNOSTIC DATA
TO/FROM CHIP
SPC COMMAND FORMAT
o
4 3
7
SPC Command Code
4 bits
SPC Register Code
4 bits
SPC COMMAND CODES
COMMAND
CODE
READ/WRITE
FUNCTION
0
Read
Read Register
ACTION
NOTES
Uses Register Select Field
1
Write
Write Register
Uses Register Select Field
2
Read
Read Register and Increment Initialize Counter
Serial RAM Read
Write and Increment Initialize Counter
Serial RAM Write
3
Write
4-C
-
D
Write
Stub Diagnostic
Broadcast Commands
E
Write
Serial Diagnostic
Serial Commands
F
-
No-Op
Guaranteed No-Op
-
Reserved (No-Op)
SPC REGISTER CODES
REGISTER
CODE
READ/WRITE
FUNCTION
0
R/W
Initialize Counter
-
1
R/W
RAM Output
-
REGISTER
NOTES
2
R/W
Pipeline Register
3
R/W
Break Mask Register
4
R/W
Break Data Register
5
R/W
Set-up
6
Rd Only
Y15 -Yo (Data Pins)
Data Pins of Chip
7
Rd Only
RAM Address
Address Going into RAM
8-F
-
+ Status Register
Reserved (unused)
S13-67
Break Multiplexer, Trace Mode, etc.
-
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
REGISTERED RAM DATA FLOW BLOCK DIAGRAM
SPR READ DATA BUS
....--_ _ _ _ _ _ _ _ _ _ _ _ _ SERIAL
SERIAL
DATA IN
--~~lrsi~;;U;Ra;:roCOi:Ri~mRl.."L-----+_-.--J
DATA OUT
TRACE
ADDRESS
------:"'-'""~
wr=. - - - - - - < I
.-----~-:::-:::ll__I___--_ BREAKPOINT
COMPARE
1.. _ _ _
_ _ _. _ _ J
I - - t - - -..... 'Cl: 1 LEVEL
I--t---;-~ CE"o LEVEL
I--t----,,..-I-~ FLOW 15-8
SET-UP I--t--r-IH-~ FLOW 7-0
REGISTER
BREAK ON ADDRS
mrr--+~-.-----r;;;;.;-~
~~~H-~
......- - , _....
C[K ----,,------r.----~
BREAK PIPE
TRACE
POWER
UP
~ ----~r-----~
1--_ _ _.L..1.....L..Z-L..lt....L.._ STATUS BITS
RAM DATA OUT
PARITY
S13-68
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP REGISTER FORMAT
BIT
NAME
TYPE (1)
FUNCTION
POWER-UP
VALUE
15
CE
RO
Chip Enable State: NOR of All Chip Enable Pins
0
14
SOE FF
RO
0
13
SOE Pin
RO
12
OEPin
RO
7
CS 1 Level
ANI
6
CS o Level
ANI
= Output Enabled, 0 = Output Disabled
SOE Pin State: 1 = High, 0 = Low
OE Pin State: 1 = High, 0 = Low
WE Pin State: 1 = High, 0 = Low
INIT Pin State: 1 = High, 0 = Low
Breakpoint Comparator Output: 1 = Compare Valid
BP Pin State: 1 = High,O = Low
o = CS1 is Low Active; 1 = CS1 is High Active
o = CSo is Low Active; 1 = CSo is High Active
5
Non-Reg High
ANI
Set Pipeline Register Bits 15-8 to Flow-Through Mode
4
Non-Reg Low
ANI
Set Pipeline Register Bits 7-0 to Flow-Through Mode
0
3
-
-
(Unused)
0
2
BC Address
ANI
Address Inputs
0
1
BC Pipe lined
R/W
Set Breakpoint Output MUX for Pipeline FF Output
0
ANI
Set for Trace Mode: '1'15-0 to Pipeline Register, Pipeline Register to RAM,
Initialize Counter as Address, Write with Clock Pulse
0
11
WE Pin
RO
10
INITPin
RO
9
BP Compare
RO
8
BP Pin
RO
0
Trace Mode
SOE FF State: 1
o = Breakpoint on Pipeline Register Output, 1 = Breakpoint on RAM
NOTE:
1. RO means Read Only. ANI means Read/Write.
S13-69
..
__ .._---_._-_._ _.
._
..
__ ....
_-------------
0
0
0
0
0
0
0
0
0
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71502 GENERAL DESCRIPTION
The IDT71502 Registered RAM consists of a 4K x 16-bit RAM
plus a 16-bit pipeline register and is designed for microcode
writable control store use. A serial shift register system, the Serial
Protocol Channel (SPC), is included on-chip for serial load and
read-back of the RAM data. A RAM address counter is also provided to speed up RAM load and read-back. The SPC serial shift
register is also configured to be used as a diagnostic register. The
shift register can read all status conditions on the chip such as the
RAM output, pipeline register output,data output pin state and
RAM load/read counter value. A breakpoint comparator is
included to support the diagnostic function. This breakpoint
comparator can be used to detect a particular bit pattern in the
RAM address or pipeline register outputs.
The IDT71502 Registered RAM includes features to support
control store applications. These include synchronous output
enable and an initialize register for selecting the initial value of the
pipeline register. A parity output is provided which indicates the
parity of the contents of the pipeline register. The parity output can
be used to provide parity check control for high-reliability systems.
The IDT71502 Registered RAM can also be used as a trace RAM
for recording external data. In this mode, the data I/O pins are
inputs and data is clocked into the RAM using the Initialize register
as the address counter. The Trace mode, in combination with the
breakpoint comparator, allows the IDT71502 Registered RAM to
be used as a one-chip logic analyzer.
register. This is the normal operating mode, where all the shift registers in a system are connected into one long shift register. The
SPC logic in the IDT71502 is automatically set to the Serial mode
by power up. The Stub command sets the latch and causes the serial output data to be taken from the serial input. In this mode, the
serial data is passed directly from one chip to the next so that all
command registers have the same data at their serial inputs. This
allows a broadcast mode where all command registers in a system
can be loaded with the same command at the same time.
RAM Load/Readback Logic
The RAM write pulse is generated by an internal one-shot triggered by the clock. Data is written into the RAM immediately
following pipeline register load and the Initialize Counter is incremented by the trailing edge of the write pulse. Using an internally
generated write pulse makes RAM writing independent of clock
high and low times. A timing diagram of the RAM clocking is shown
in the Trace Mode Clock Timing Diagram (Figure 5).
A detailed block diagram of the IDT71502 Registered RAM,
showing the various internal registers and the load and readback
paths, is shown in the Registered RAM Data Flow Block Diagram.
In addition to the logic shown in the Functional Block Diagram on
the first page of the data sheet, there is an Initialize Counter for
loading and initializing the RAM, Break Data and Mask registers for
the Breakpoint Comparator and multiplexers at the input to the
Pipeline register for allowing data from the' data I/O pins to be
clocked into the Pipeline register in the Trace mode before being
written into the RAM. The data flow block diagram also shows the
various multiplexers for routing data for breakpoint and readback
use.
.
RAM Operation
After power up, and in its typical operating mode, the IDT71502
Registered RAM is set for pipelined read and direct (non-pipelined)
write. Data may be directly written into the RAM by driving the
address and data inputs and strobing the Write Enable input. Data
is read from the RAM by driving the address lines and clocking the
pipeline register.
The RAM may also be read and written by the Serial Protocol
Channel (SPC). This is the typical path for loading the RAM after
power up.
Initialize Counter
The Initialize Counter provides the initial address to the RAM after reset of the part. A pulse appl:Gd to the Initialize pin causes the
Initialize Counterto be gated to the RAM address and the RAM data
to be preset into the pipeline register. This provides an initial value
in the pipeline register before the first clock pulse arrives. The
Initialize Counter can be reset to zero at power up of the chip and
can be loaded with a value other than zero by the SPC. Once
loaded with a value by the SPC, this value is used in further chip
reset operations.
Serial Protocol Channel
The Serial Protocol Channel (SPC) logicconsistsofa 16-bitdata
shift register, an 8-bit command register and clock logic consisting
of gates and a flip-flop. A block diagram of the command decode
logic is shown for reference. The command decode logic decodes
and executes the command in the command shift register using
the clock from the clock logic. The command is divided into two
four-bit fields. The most significant four bits of the command register define the command to be executed: read, write, etc. The least
significant four bits define the register to be read or written. (NOTE:
The data to the SPC is shifted in LSB first.)
The SPC is connected to the outside world through four wires.
These wires consist of serial data in and out, a shift clock and a
command/data line. When the command/data line is high, commands are shifted from the serial data in to the command register
by the clock. When the command/data line is low, data is shifted
into the data shift register by the clock. When the command/data
line transitions from high (command) to low (data), a clock pulse is
generated internally to the command decode logic. This pulse
lasts from the beginning of the high-to-Iow transition to the next
serial clock pulse and is used to execute the command in the
command register.
Two of the defined commands are Serial and StUb. These commands control a latch which determines the source of the serial
data out in the command mode. The Serial command causes the
data output to be taken from the last stage of the command shift
Set-up Register
The Set-up Register is a 16-bit register used to set the chip operating mode and to read back chip operating status conditions. A
command word written into the Set-up Register sets 7 latches
which control the chip operating conditions. Reading the Set-up
Register provides the current status of these 7 latches and various
other signals on the Chip. At power up, the 7 latches are cleared to
zero and the Initialize counter is cleared to zero. The format of the
Set-up Register is shown in the Set-up Register Format table.
The Set-up Register has 7 latches which determine the operating mode of the chip. These are CS 1 , CS o, Non-Reg Hi~ NonReg Low, BC RAM, Break P~ and Trace. The CS 1 and CSo bits
determine the polarity of the CS 1 and CSo chip enables. The NonReg High and Low bits setthe upper and lower bytes ofthe Pipeline
Register to a flow-through mode, respectively. The BC RAM bit
determines the source of the data for breakpoint comparison,
either the Pipeline Register or the RAM address. The Break Pipe
latch switches the breakpoint pin multiplexer from the comparator
to the buffer flip-flop. The trace latch sets the chip into the Trace
mode.
513-70
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Power Up State
Note that taking Vee from 5.0 volts to 2.0 volts and back to
5.0 volts will not cause power up reset.
Power up is defined as taking Vee from below 1.0 volts to
5.0 volts nominal. This generates power up reset, an internal signal
which resets several registers on the chip. After power up, the
IDT71502 is in the following state:
• Set-up Register cleared to zero
• Initialize Counter cleared to zero
• Breakpoint Mask Register cleared to equal (Breakpoint output
high)
Set-up Register: Programmable Chip Enable
The chip enable function is programmable by bits in the Set-up
Register. The logic for this is shown in Figure 1. The bits in the Setup Register define the active state of each chip enable: high or low.
This allows up to four RAMs to be cascaded in depth with no
external decoders required (16K x 16 bits of RAM).
• SOE Flip-Flop cleared to outputs off
CE"
} - - r -_ _ _ _ _ _ _ _ _~TO"SCJE
FLIP-FLOP
BREAKPOINT
COMPARATOR
~o
WRITE FROM SPR
--------c
Figure 1. Chip Enable logic Block Diagram
513-71
1----11...
WRITE TO RAM
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Set-up Register: Non-Registered Outputs
Two bits of the Set-up Register, Non-Reg Hi and Non-Reg La,
can be setto cause the Pipeline Register bits 15-9 and 7-0, respectively, to be set to the flow-through mode. In the flow-through
mode, both latches of the register are open and the register acts
like a simple butferwith its output following its input. This allows the
user to have some non-registered bits in microcode applications.
The output circuit consisting ofthe Pipeline Register, the ~chro
nous Output Enable (SOE), and the Output Enable (OE), has
some special logic to support this mode, as shown in Figure 2.
NON-REG HI
Also, activating the Initialize pin causes the Pipeline Register to be
put in the flow-through mode. Figure 2 shows the Pipeline Register
as two latches operated in the MASTER/SLAVE configuration. The
clock input will cause the latch pair to work as a register. If the Initialize pin is activated, both registers will be placed in the flowthrough mode by the OR gates. Also, if either Non-Reg bit is set, its
corresponding 8-bit portion of the register will be placed in the
.
flow-through mode.
RAM DATAoUT
MUX
NON-REG LO
15-8
RAM DATAoUT
MUX
7-0
INITIALIzE
MASTER
LATCH
SLAVE
LATCH
CLOCK~----~---+-r~------------------~~----~~
~~-.-------+-r------------~------~~----~~----------~
UE--------------------~+---------+_------------~
~----------------------~--------+---------------~
DATA OUT
15-8
DATA OUT
7-0
Figure 2. Output Logic Block Diagram
When in the flow-through mode, the output enable flip-flop for
that half must also be in the flow-through mode for external chip
expansion to work properly. A non-registered RAM bit must be enabled by a non-registered output enable, while a registered bit
must be enabled by a synchronous output enable. This is done by
using the non~stered bit to control a multiplexer which selects
between the SOE flip-flop input and output as the source of the
output enable.
S13-72
- - - - _.•..
IDT1M6052 4Kx 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
_-_ ..._..
_.- ..-
------------
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CLOCK
I
I
CE".WE'
I
I
I
I
SyNC WE
I
I
I
TCLK
(RAM WRITE)
-Wl
I
PIPELINE REGISTER
INPUT
~
I
PIPELINE REGISTER
OUTPUT
=x
INITIALIZE COUNTER
(RAM ADDRESS)
I
I
I
~
C
C
I
I
I
I
I
I
I
6
I
FI
I
I
I
X
D
I
I
n
fl
~
E
I
X
B
I
X
~
D
I
X
I
5
I
I
I
A:
I
I
I
~
I
I
I
I
B
I
I
~
C
I
I
X
I
I
IE
I
I
I
X7
X
Figure 4. Trace Mode Sequence Timing Diagram
CLOCK
~
I
TCLK
(RAM WRITE)
I
I
PIPELINE REGISTER
INPUT
j t---r------i--------------I~
!
DATA X
I
PIPELINE REGISTER
OUTPUT
RAM DATA
DATA X + 2
I
I
==tJ"""'r-----i---------------Il~--'x
I
DATA X
I
INITIALIZE COUNTER
(RAM ADDRESS)
+1
DATA X
+1
I
I
-Xi«X"---N-+-1____. !. ______
:I
N __
_t--_-+--_ _
:
OLD
!xmw . . . )). . . . . . . )IX'-_ _ _
DA_TA_X_ _ _ _ _ _-'--_ _ _ __
Figure 5. Trace Mode Clock Timing Diagram
513-73
.....................
_-_ _..__._.. •.•. _-_
.....
_
......_..
_--_
...
_. -.--.-...-.-"-.-"._........
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Parity Output
The Parity Output pin is generated from a 16-bit parity tree, as
shown in the Parity Tree Logic Block Diagram (Figure 6). Even parity is used. Parity is generated on the contents of the Pipeline Register. The parity output driver is three-state and is enabled by the
SOE Flip-Flop to allow depth expansion of the parity output.
The Parity Output always reflects the parity of the registered
value. Additional flip-flops and multiplexers are included in the
REGISTER BIT 15
REGISTER BIT 14
REGISTER BIT 13
REGISTER BIT 12
REGISTER BIT 11
REGISTER BIT 10
REGISTER BIT 9
REGISTER BIT 8
REGISTER BIT 7
REGISTER BIT 6
REGISTER BIT 5
REGISTER BIT 4
REGISTER BIT 3
REGISTER BIT 2
REGISTER BIT 1
REGISTER BIT 0
~l~
~l~
parity tree to cover the case of non-registered outputs. If one or
both bytes of the Pipeline Register are set to the Non-Registered
mode, a flip-flop pipeline delay is added to the corresponding byte
parity chain to make the result of that byte parity calculation the
same as if the Pipeline Register was not in the Non-Pipelined
mode.
CLOCK
NON-REGISTER HI BYTE
OUTPUT DRIVER
D-{?--
~l~
PARITY OUTPUT
~ FLIP-FLOP
NON-REGISTER La BYTE
j~
jI)--F
Figure 6. Parity Tree Logic Block. Diagram
S13-74
IDT7M6052 4K x 80 WRITABLE CONTROL
STORE STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
lOT
XXX)(
Device Type
999
Speed
A
A
Package
Process/
Temperature ,
Range
y:~k
L..----------------------i
Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Semiconductor components
compliant to MIL-STD-883,
Class B
CK
Ceramic alP
25
Commercial OnlY)
Speed in Nanoseconds
35
45
55
~------------------------------~ S
L---------------------------------------I
S13-75
7M6052
Standard Power
4K x 80 w/Sequencer
t;)
8K x 36 FIFO MODULE
lOT 7MB2001 S
Integrated Dev1ce1echnology.1nc.
FEATURES:
• First-In/First-Out memory module
• Asynchronous and simultaneous read and write
• Configurable as BK x 36 or 16K x 1B unidirectional or BK x 1B
bidirectional FIFO
• Multiple status flags: Full, Empty
• Ultra-high-speed: 40ns access time
• Fully expandable by both word depth and/or bit width
• Dual-port zero fall-through time architecture
• Available inhigh-clensity 10B-pin quad in-line FR-4 package
DESCRIPTION:
The IDT7MB2001 is a FIFO module that consists of eight
IDT72041s (4K x 9). The IDT72041 is a dual-ported memory that
utilizes a special first-in/first-out algorithm that loads and empties
data on a first-in/first-out basis.
The IDT7MB2001 is user-configurable in three modes:
- An BK x 36 unidirectional FIFO, or
- A 16K x 1B unidirectional FIFO, or
- An BK x 1B bidirectional FIFO.
In all three modes, the module offers two flags, Full and Empty,
to prevent data overflow and underflow. Expansion logic of the
IDT72041s allows wider and/or deeper FIFOs to be created using
multiple devices without external logic.
The module also allows asynchronous and simultaneous read
and write operations. The dual-port RAM array allows zero fallthrough time and a ninth bit is provided for every byte to store
parity.
Access time is as fast as 40ns. The module is offered in a highdensity 10B-pin quad in-line package.
FUNCTIONAL BLOCK DIAGRAM
LOWER
FLAG
LOGIC
FLAGS IN
D (0:8)
.....
_
LOWER CONT &
2x4Kx9
FIFO
"
UPPER
FLAGS IN
0(0:8) ..
D (18:26)
-
EXPANSION OUT
UPPERCONT&
,
EXPANSION IN
D(9:17)
LOWER:
FLAGS OUT
2x4Kx9
FIFO
UPPER
FLAG
LOGIC
FLAGS OUT
2x 4Kx 9
FIFO
'i'
0(18:26) --"'"
.
EXPANSION OUT
EXPANSION IN
'If
0(9:17) ....
D(27:35) ..
~
LOWER OE*
2 x 4Kx9
FIFO
0(27:35)
UPPER OE*
CEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
©
OSC-7036/-
1989 Integrated DevIce Technology. Inc.
813-76
---------
- - -....
...
IDT7MB2001 S 8K x 36 FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM (Continued)
16Kx 18
8Kx36
0(0:17)
0(0:17)
0(0:17)
LOWER
8Kx 18
BLOCK
LOWER
FLAGS
CaNT
0(18:35)
UPPER
0(18:35)
8Kx 18
BLOCK
CaNT
-
UPPER
CaNT
FLAGS
8K x 18 BIFIFO
LEFT_0/0():17)
j~
8Kx 18
BLOCK
8Kx 18
BLOCK
LEFT_CONT&FLAGS
.
~
~
8Kx 18
BLOCK
-
~If
RIGHT_D/0(0:17)
RIGHT_CONT&FLAGS
S13-77
0(0:17).,
,.
8Kx 18
BLOCK
FLAGS
IDT7MB2001S 8K x 36 FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GNO
'5U o
0(0)
0(1)
0(2)
0(3)
0(4)
0(5)
0(6)
0(7)
0(8)
~
FtLL
0(9)
0(10)
0(11)
0(12)
0(13)
0(14)
0(15)
0(16)
0(17)
'5Ul
"E"F IL
F'F'IL
Vcc
1
55
GNO
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
56
W(2)
0(18)
0(19)
0(20)
0(21)
0(22)
0(23)
0(24)
0(25)
0(26)
57
58
59
60
61
62
63
64
65
~~
0(18)
0(19)
0(20)
0(21)
0(22)
0(23)
0(24)
0(25)
66 "R'u
22
67 ~u
68 GNO
69 0(27)
70 0(28)
71 0(29)
72 0(30)
73 0(31)
74 0(32)
75 0(33)
76 0(34)
23
24
25
26
27
78 ~)
79 "E"Fu
80 F'F'u
81 Vee
77
M2i 1)
108
107
106
105
104
103
102
101
100
99
~~6) 98
97
]igu
96
Ftu
95
94
0(27)
93
0(28)
0(29)
92
91
0(30)
90
0(31)
89
0(32)
88
0(33)
87
0(34)
~3:) 86
85
"E"FIW 84
F'F'IW 83
GNO 82
NOTE:
1. For module dimensions, please refer to module drawing M27
in the packaging section.
S13-78
~
0(0)
0(1)
0(2)
0(3)
0(4)
0(5)
0(6)
0(7)
0(8)
"R'L
~L
GNO
0(9)
0(10)
0(11)
0(12)
0(13)
0(14)
0(15)
0(16)
0(17)
W1
"E"FL
F'F'L
GNO
COMMERCIAL TEMPERATURE RANGE
IDT7MB2001S 8Kx 36 FIFO MODULE
TRUTH TABLES
TABLE 1- RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INTERNAL STATUS
INPUTS
MODE
RT
RS
Reset
0
X
Read/Write
1
1
OUTPUTS
XI
Read Pointer
Write Pointer
EF
0
0
Location Zero
Location Zero
0
1
Increment (1)
Increment (1)
X
X
FF
NOTE:
Pointer will increment if flag is high.
1.
TABLE II-RESET AND FIRST LOAD TRUTH TABLE
DEPTH EXPANSION/COMPOUND EXPANSION MODE
INTERNAL STATUS
INPUTS
MODE
Reset-First Device
Reset all Other Devices
Read/Write
FL
XI
Read Pointer
Write Pointer
EF
FF
0
0
1
0
1
(1)
Location Zero
Location Zero
1
(1)
Location Zero
Location Zero
0
0
X
(1)
X
X
X
X
NOTE:
is connected to "5(Q of previous device for depth expansion.
liS = Reset Input, 'FI:= First Load, E"F = Empty Flag Output, 'FF
1.
OUTPUTS
RS
m
=
Full Flag Output,
1
m = Expansion Input.
PIN DESCRIPTIONS
SYMBOL
NAME
DESCRIPTION
I/O
DO-D8
Inputs
I
Data inputs for 9-bit wide data.
RS
Reset
I
When RS is set 10wJ!!temai READ and WRITE pOinters are set to the first location of the RA..11 arr~ HF and FF go
high, anJi.AEF and EF go low. A reset is required before an initial WRITE after power-up. R and W must be high
during RS cycle.
W
Write
I
When WRITE~low, data can be written into the RAM arr~ sequentially, independent of READ. In orderforWRITE
to'be active, FF must be high. When the FIFO is full (FF-Iow), the intemal WRITE operation is blocked.
R
READ
I
When RE@ is low, data can be read from the RAM.array sequentially, independent of WRITE. In order for READ to
be active, EF must be high. When FIFO is empty (EF-Iow), the intemal READ operation is blocked and 00-08 are in
a high impedance condition.
.
In the depth expansion configuration, FL-Iow indicates the first activated device.
FL
First Load
I
XI
Expansion In
I
OE
Output Enable
I
When OE is set low, the parallel output buffers receive data from the RAM array. WhenOE is set high, parallel
three-state buffers inhibit data flow.
IT
Full Flag
0
When FF goes low, the device is full and further WRITE operations are inhibited. When FF is high, the device is not
full.
EF
Empty Flag
0
When EF goes low, the device is empty and further READ operations are inhibited. When EF is high, the device is
not empty.
XO
Expansion Out
0
In the depth expansion configuration (XO connected to XI of the next device), a pulse is sent from XO to XI when
the last location in the RAM array is filled.
00- 08
Outputs
0
Data-outputs for 9-bit wide data.
In the single device configuration, XI is grounded. In depth expansion or daisy chain expansion, XI is connected to
.
.'
XO (expansion out) of the previous device.
S13-79
COMMERCIAL TEMPERATURE RANGE
IDT7MB2001S 8K x 36 FIFO MODULE
ABSOLUTE MAXIMUM RATINGS
(1)
UNIT
VALUE
VTERM
RATING
Terminal Voltage with
Respect to GND
TA
Operating Temperature
TalAs
Temperature Under Bias
-55 to +125
°C
Tsm
Storage Temperature
-55 to +125
°C
SYMBOL
-0.5 to +7.0
V
Oto +70
°C
50
mA
DC Output Current
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
SYMBOL
PARAMETER
Vcc
Commercial
Supply Voltage
MIN.
TYP.
MAX.
UNIT
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
"'H(l)
Input High Voltage
Commercial
2.0
-
V
"'L (1)
Input Low Voltage
Commercial
-
-
O.S
V
AMBIENT
TEMPERATURE
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL· CHARACTERISTICS
(Commercial: Vcc= 5.OV ±10%, TA = O°C to + 70°C)
SYMBOL
PARAMETER
MIN.
IlL (1)
Input Leakage Current (Any Input)
-5
IOL (2)
Output Leakage Current
-10
VOH
Output Logic "1" Voltage lOUT = -2mA
2.4
VOL
Output Logic "0· Voltage lOUT = SmA
-
Icc1 (3)
Average Vcc Power Supply Current
IC02 (3)
Average Standby Current (~ =
ICC3 (3)
Power Down Current (All Input = Vcc = -0.2V)
W = R'ST = ~'RT = VI~
NOTES:
1. Measurements with 0.4 S
S "oUT'
2. R ~ '4H, 0.4 S VOUT S Vcc
3. Icc measurements are made with outputs open.
"'N
S13-S0
-
-
COMMERCIAL
TYP.
MAX.
UNIT
-
0.4
V
600
960
mA
64
96
mA
-
64
mA
5
J.IA
10
J.IA
-
V
COMMERCIAL TEMPERATURE RANGE
IDT7MB2001S 8Kx 36 FIFO MODULE
CAPACITANCE
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
VIN = OV
15
pF
VOUT= OV
25
pF
NOTE:
1. This parameter is sampled and not 100% tested.
AC ELECTRICAL CHARACTERISTICS (1)
(Commercial: Vee= 5.0V ±10%, TA = O°C to + 70°C)
SYMBOL
7MB2001S40
MIN.
MAX.
PARAMETER
7MB2001S50
MIN.
MAX.
7MB2001S60
MAX.
MIN.
7MB2001S70
MIN.
MAX.
7MB2001S85
MIN.
MAX.
UNIT
t RC
Read Cycle Time
50
-
65
-
75
-
85
-
105
-
ns
tA
Address Access Time
-
40
-
50
-
60
-
70
-
85
ns
tRR
t RPW (2)
Read Recovery Time
10
15
-
15
-
ns
50
60
-
70
-
20
40
-
15
Read Pulse Width
-
85
-
ns
tOE
t oU (3)
Output Enable to OIP Valid
-
20
-
25
-
30
-
30
-
30
ns
Output Enable to OIP in Low Z
0
-
0
-
0
-
0
-
0
-
ns
t OHZ (3)
Output Disable to OIP in High Z
-
20
-
25
-
30
-
30
-
30
ns
85
-
,105
ns
70
-
85
105
ns
85
ns
85
ns
85
ns
85
ns
Write Cycle Time
twc
t wPW (2) Write Pulse Width
50
-
65
-
75
40
50
-
60
tWR
Write Recovery Time
10
-
-
15
15
-
15
-
20
t DS
Data Set-up Time
20
-
30
30
-
30
-
40
tDH
Data Hold Time
0
5
5
-
10
Reset Cycle Time
50
65
75
85
105
t RS(2)
Reset Pulse Width
40
-
50
70
-
10
t RSC
-
-
t RSR
Reset Recovery Time
10
-
15
-
20
t RSF
Reset to Empty Flag Low,
Full Flag High
85
Read Low to Empty Flag Low
70
tRFF
Read High to Full Flag High
-
50
tREF
tWEF
Write High to Empty Flag High
tWFF
Write Low to Full Flag Low
-
60
15
-
15
-
-
65
-
75
40
50
-
60
40
-
50
-
60
-
-
40
-
50
-
60
-
70
-
40
-
50
-
60
-
70
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by deSign, not currently tested.
:q :q
+5V
5V
UK
DoUT
6800.,
AC TEST CONDITIONS
Input Pulse Levels
Input RiselFail Times
Input Timing Reference Levels
Output Reference Levels
Output Load
70
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1, 2, and 3 '
85
30pF*
Figure 1. Output Load
2550
5pF*
Figure 2. Output Load
(for tou , t OHZ )
*Includes jig and scope capacitances.
S13-81
4800
DoUT
ns
ns
ns
ns
ns
ns
ns
IDT7MB2001 S SK x 36 FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
~------------------------tR~ ------------------------~
w
FF
NOTES:
1. E"F' and FF may change status during Reset. but flags will be valid at t ROO
2. Wand 'R = VH around the rising edge of'RS.
Figure 3. Reset
~-------
0 0 -017
t RC
------~OO<
--------t~---
DATA OUT VALID
tRPW
)@(DATAOUTVALlD)OO----
~-------------twc------------~
14-------- twPw ------+1---W
C=t
Do -D17
--------c(
DS
tDH
=j
DATA IN VALID
)00-----4:(
Figure 4. Asynchronous Write and Read Operation
S13-S2
DATA IN VALID
»0---
IDT7MB2001S 8K x 36 FIFO MODULE
LAST WRITE
COMMERCIAL TEMPERATURE RANGE
FIRST READ
IGNORED
WRITE
ADDITIONAL
READS
FIRST WRITE
w
Figure 5. Full Flag From last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
w
DATAO~----1-i--€~~~~---+------------~------~--~~QID~
Figure 6. Empty Flag From last Read to First Write
tOHZ
00-17 ----.j---.....w~'\fY'l.
tOLZ
Figure 7. Output Enable Timings
S13-83
IDT7MB2001 S SK x 36 FIFO MODULE
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
lOT
XXXX
Device Type
A
Power
999
Speed
A
A
Package
Process/
Temperature
Y~Mk
~----~--------~
K
'---------------------1
50
60
QIP (Quad in-line package)
40
70
85
~------------------------------~
S
'------------------------~ 7MB2001
S13-S4
Standard Power
8K x 36 FIFO Module
- - - - - - - ..•...----....- .. _-----_._....-
--------------------
f;)
_.
__ .... _._.__ _.__ __
.
..
... _•...•..
_-----------
lOT 7MB2002
36 TO 9 BIFIFO
IntegratedDevlce~Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
This module is a FIFO that has up to 8 I0172041 s (4K x 9) on
board. The module is bidirectional with 4K x 36 transforming to 16K
x 9 on one side and back to 4K x 36 on the other side. All logic necessary to control the conversion between 36 and 9 bits is included
on the module.
On the 9-bit side, there is a DIRN pin which determines whether
the 36 bits of data is presented to the 9-bit side's most significant
byte first or least significant byte first and, conversely, whether the
9-bit side data is being entered MSB or LSB first.
Included on-board is an 8-bit transceiver with separate latch
enables for each side to allow the passing of status between the
buses.
The module is packaged on a 92 pin FR-4 substrate occupying
less than 4 square inches of board space.
•
•
•
•
•
First-in/First-out memory module
Asynchronous and simultaneous read and write
36-bit data bus on one side; 9-bit data bus on other side
All logic required for conversion between 36 and 9-bit buses
included on board
4K x 36-bit to 16K x 9-bit deep
Selectable LSB or MSB first on 9-bit side
Bidirectional
Latching transceiver for LS 8 bits between the two buses
Total cycle time 45ns
FUNCTIONAL BLOCK DIAGRAM
y
R
WRITE
W
OE
D
y
R
W
OE
D
Y
R
I/O 36
W
OE
D
y
R
W
OE
Y
D
~I/O
LE
R
OE
y
R
OE
y
R
OE
READ
y
R
OE
W
D
W
D
W
D
.-RESET
W
FULL
CEMOS is a trademark of Integrated Device Technology. Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology, Inc.
OSC-7037/-
513-85
IDT7MB2002 4K x 36 TO 9 BIFIFO
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
1
I/0L o
2
37 GND
38 CJE[R
I/0Ll
3
39
I/OL2
Vcc
'OER[
72
36
Vcc
71
35
IIOR 6 .
I:Ern
Ern[
70
34
IIOR7
4
40 1I0L3
1I0R5
69
33
1I0Re
I/OL 4
5
68
32
I/OR 4
6
41 1I0L 5
42 I!OL7
1I0R 3
I/0Le
GND
67
31
1I0R o
1I0L35
66
30
1I0R2
1I0R l ·
65
29
RESET
1I0L 33
64
28
1I0L34
1I0L 3l
63
27
IIOL 32
1I0L 30
62
26
I/OL 8
7
43 1I0Le
I/OL10
8
44 1I0Lll
'FUIIL
E'tVWT?L
WI1ITE'L
9
45
10
46 E"MJ5T?R
47 DIRN
'FUII R
M25(1)
m:Al5 L
12
48 GND
GND
61
25
WI1ITE'R
m:Al5R
(jEL
13
49 1I0L12
1I0L 29
60
24
(jER
I/OL13
14.
50 1I0L14
1I0L 27
59
23
1I0L 26
I/OL15
15
51
1I0L16
IIOL 25
58
22
1I0L26
I/0L17
16
52 1I0L16
1I0L 23
57
21
1I0L24
I/OL 19
17
53 1I0L 2o
1I0L 2l
56
20
Vee
18
54 Vcc
GND
55
19
1I0L 22
GND
11
NOTE:
1. For module dimensions, please refer to module drawing M25 in the
packaging section.
PIN DESCRIPTIONS
SIGNAL NAME
DESCRIPTION
Power
Vee
GND
Ground
I/OL
36 bit 1/0 bus
1I0R
9 bit 1/0 bus
FULL
FIFO Full Flag
EMPTY
FIFO Empty Flag
WRITE
Write Enable
READ
Read Enable
(jE
Output Enable
OELR
Transceiver Output Enable (L - R)
OERL
Transceiver Output Enable (R - L)
LELR
Transceiver Latch Enable (L - R)
LERL
Transceiver Latch Enable (R - L)
DIRN
LSB/MSB Selection on 9 bit side
RESET
System Reset
S13-86
COMMERCIAL TEMPERATURE RANGE
IDT7MB2002 4Kx 36 TO 9 BIFIFO
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage with
Respect to GND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
(1)
VALUE
UNIT
AMBIENT
TEMPERATURE
V
-0.5 to 7.0
TA
Operating Temperature
Oto +70
°C
TSIAS
TSTG
Temperature Under Bias
-55 to +125
°C
Storage Temperature
-55 to + 125
°C
lOUT
DC Output Current
50
mA
Vee
50V ±10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vcc
Commercial Supply
Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
VIH (1)
Input High Voltage
Commercial
2
-
-
0
V
VIL (1)
Input Low Voltage
Commercial
-
-
O.B
V
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5.0V :!:10%, TA = O°C to +70°C)
SYMBOL
PARAMETER
MIN.
MAX.
1L1 LEFT
Leakage Current Left
-10
10
UNIT
~A
1L1 RIGHT
Leakage Current Right
-40
40
~A
ICC1
Ave. Vcc Supply Current
-
680( 1)
mA
ICC2
Ave. Standby Current
-
130
mA
ICC3
Power Down Current
-
90
mA
VOH
Output High Voltage
10H = -2mA
2.4
-
V
Output Low Voltage
VOL
NOTE:
1. Icc 1 = 7BOmA at 45ns.
10L = -BmA
-
0.4
V
CAPACITANCE
SYMBOL
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
C OUT
Output Capacitance
.
CONDITIONS
TYP.
VIN = OV
15
pF
VOUT= OV
25
pF
UNIT
NOTE:
1. This parameter is sampled and not 100% tested.
S13-87
IDT7MB2002 4K x 36 TO 9 BIFIFO
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5.0V -+10%. TA = O°C to + 70°C)
PARAMETER
SYMBOL
7MB2002S45
MIN.
MAX.
7MB2002S60
MIN.
MAX.
7MB2002S75
MIN.
MAX.
7MB2002S90
MIN.
MAX.
7MB2002S130
MIN.
MAX.
UNIT
READ CYCLE
1s
Frequency Shift
-
18
-
13
-
11
-
9
-
7
MHz
t RC
Read Cycle Time
55
-
75
-
90
-
110
-
150
-
ns
tA
Access Time
-
45
-
60
-
75
-
90
-
130
ns
tRR
Read Recovery Time
10
-
15
15
-
20
-
20
-
ns
t RPW
Read Pulse Width
45
-
60
-
75
-
90
-
130
-
ns
tov
Data Valid from Read Pulse High
5
-
5
-
5
-
5
-
5
-
ns
tREF
Read Low to Empty Flag Low
-
45
-
60
75
-
75
ns
Read High to Full Flag High
-
45
-
60
75
-
75
tRFF
-
75
-
75
ns
tRLZ
Read Low to Data Low Z
5
-
10
-
10
-
10
-
10
-
ns
tRHZ
Read High to Data High Z
-
30
-
40
-
40
-
40
-
40
ns
WRITE TIMING
twc
Write Cycle Time
55
-
75
60
75
90
130
-
tWR
Write Recovery Time
10
-
-
150
45
-
110
Write Pulse Width
-
90
t wpw
15
-
15
-
20
-
20
-
ns
tos
Data Set-up Time
20
-
42
-
ns
5
10
-
10
-
42
0
-
32
Data Hold Time
-
32
tOH
10
-
ns
tWEF
Write High to Empty Flag High
45
-
60
-
75
-
75
ns
Write Low to Fall Flag Low
45
-
60
-
75
-
75
tWFF
-
75
-
75
ns
70
-
85
-
105
-
145
55
-
70
85
-
125
-
ns
55
-
70
15
-
-
40
50
-
90
-
ns
ns
RESET TIMING
t RSC
Reset Cycle Time
50
t RS
Reset Pulse Width
40
tRSS
Reset Set-up Time
40
t RSR
Reset Recovery Time
10
-
-
23
-
31
-
23
-
26
t RSF
Reset Empty/Full Flag
-
55
-
31
tOE
m: High to Data High Z
m: Low to Data Low Z
m: Low to Valid Data
tOHZ
toLZ
S13-88
36
75
15
40
85
20
ns
-
125
-
ns
20
-
ns
40
40
ns
40
-
40
ns
50
-
50
ns
110
-
150
ns
IDT7MB2002 4K x 36 TO 9 BIFIFO
COMMERCIAL TEMPERATURE RANGE
t Rsc -----------I.~I
w
NOTES:
1. U and ~ may change status during Reset, but flags will be valid at t RSC '
2. W and R = VH around the rising edge of liS.
Figure 1. Reset
t RC
- - - - -.......1 - -
~
Qo - Q s
--00
'I:l"'lA
DATA OUT VALID
~
t RHZ - . /
DATA OUT VALID
'm----
w
1'Do - Os
--------«
t
Ds
+
tDH
DATA INVALID
~
)>-----~(
Figure 2. Asynchronous Write and Read Operation
S13-89
DATA IN VALID
)'r---
COMMERCIAL TEMPERATURE RANGE
IDT7MB2002 '4K x 36 TO 9 BIFIFO
IGNORED
WRITE
LAST WRITE
ADDITIONAL
READS
FIRST READ
FIRST WRITE
Figure 3. Full Flag from Last Write to First Read
LAST READ
IGNORED
READ
FIRST WRITE
W ---+-----------r------~
ADDITIONAL
WRITES
-. .-
FIRST READ
tWEF
1~--+----------4----------------
DATA OUT
---I'---+--<~------------------~><~---+
---, ~
..
1 tAPS!')
......
.:::~
•
•
--~tCB
tCB
RJ3S?
_ _V_A_L1_D_ _
X
NOTE:
1. tAPS is only necessary to guarantee left side access. Within this set-up time, one side or the other will gain access, but neither will have priority.
TIMING WAVEFORM OF CONTENTION WRITE
LAND R
ADDR
==x~
________~x~__
--: I'-
-'r
tAPS
...
......
.....
~
"
--~-~
tCB
I.
1-"--,
RJ5S
_________________l:_4_t'oo~-
TIMING WAVEFORM OF SLAVE
~ t--
u~ OUT
---+
+---
tLA
~
(FROM MASTER)
SEL OUT
(FROM MASTER)
tCB
.....
......
"
tSEL
....
~ I1\
S13-103
COMMERCIAL TEMPERATURE RANGE
IDT7MB6036128Kx 16 SHARED PORT RAM
ORDERING INFORMATION
IDT
xxxx
___A__
OeviceType
Power
~
Speed
___A___ _____ ___
~A
Package
Process/
Temperature
RI_~
BLANK
I
1K
70
FR-4 QIP (Quad In Une)
Commercial Only
85
100
I
I
S
7MB6036
513-104
} Speed in Nanosecond'
Standard Power
. 128K x 16
t;)
Integrated Device 'Jechnobgy. Inc.
DUAL(16K X 60)
lOT 7MB6039
DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
FEATURES:
DESCRIPTION:
• High-speed CMOS static RAM module constructed to
support the IDT79R3000 RISC CPU as a complete data and
instruction cache (dual 16K x 60)
• Operating frequencies to support 12 MHz, 16.7MHz, 20MHz
and 25MHz CPUs
• Available in a high-density, low profile 128-pin QIP (quad
in-line package)
• Surface mounted SOIC components on a multilayer epoxy
substrate
• Multiple ground pins for maximum noise immunity
• On-board address latches for direct interface to the
IDT79R3000 CPU
• TIL-compatible I/Os
• Single 5V (±10%) power supply
The IDT7MB6039 is a 240K byte high-speed CMOS static RAM
consructed on a multilayer epoxy substrate (FR-4) , using 30
IDT7198 (16K x 4) RAMs and 8 IDT74FCT373 latches.
The construction and specifications of this module have been
optimized to support its use as a complete 16K deep INSTRUCTION and DATA cache for the IDT79R3000.
The iDT7MB6039 is organized as two seperate banks of 16K X
60, with the IDT74FCT373s being used as ADDRESS latches. The
two banks of RAM with thier associated ADDRESS latches share a
common 14-bit ADDRESS bus and a common 60-bit DATA bus.
The chip select, write enable, RAM output enable and latch enable
controls for the two banks are brought out separately to support interleaving access to the two banks of RAM. Also, each bank has
two sets of ADDRESS latches to reduce the capacitance loading
on the outputs of the latches and thereby enhance performance.
DATA CACHE
INSTRUCTION CACHE
7198
0 0- 15
A7-13
FCT
ABo-e
FCT
373
LATCH
AOo-e
373
LATCH
LE2
LE4
FCT
373
AB 7- 13
LATCH
COMMERCIAL TEMPERATURE RANGE
©
MARCH 1989
DSC-7040/-
1989 Integrated DevIce Technology. Inc.
S13-105
IDT7MB6039 DUAL (16K x 60) DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
Do
D2
D4
De
DB
WE" 1
~l
~5
WE"5
Dll
D13
Ao
A2
A4
4
d'i
CS2~
D 15
D17
D 1S
~
~2
~6
WE"6
D23
D 25
D27
D29
D3l
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65 GND
66 Dl
67 D3
68 D5
69 D7
70
71
72 GND
73
74
75 ~2
76 Vee
77 Al
78 A3
79 As
80 GND
81 LEl
82 LE3
83 ~6
84 Vee
85 D 19
86
87
88 GND
89 D22
90 OE'e
91 D24
92 D26
93 D2S
94 D30
95 D32
96 '6c
~l
~5
M29(l)
~2
Vee
N.C.
N.C.
D5B
D5e
GND
WE"4
D54
D53
WE"s
D5l
GND
A12
Ala
As
Ae
LE2
LE4
GND
D47
D45
D43
WE"7
GND
D42
WE"3
D40
Vee
D37
D35
D33
GND
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
Vee
N.C.
N.C.
D59
D57
~
~4
CSTB
OE's
D52
Dso
A13
All
A9
A
~2
CS24
D49
D 4S
D46
D44
~7
~3
0E'3
D4l
D39
D38
D36
D34
GND
NOTE:
1. For module dimensions, please refer to module drawing M29 in the
packaging section.
PIN NAMES
Do - D59
Data I/Os
Ao - A13
Address Inputs
LEl - LE4
Latch Enables
~l-~S
RAM Selects
CS2l - CS24
RAM Selects
WE"1 - WE"s
Write Enables
0E'1 - OE's
Output Enables
GND
Ground
Vce
Power Supply
N.C.
No Connection
NOTES:
1. All GND pins must be grounded for proper operation.
2. All Vee pins must be connected to + 5V for proper operation.
5V
---r-f
255QYaopF'
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
DATAoor
480Q
Figure 1. Output Load
5V
DATAOl1T
~
2550
5pF*
Figure 2. Output Load
(for tou •t OHZ )
* Including scope and jig.
S13-106
4800
IDT7MB6039 DUAL (16K X 60) DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage with Respect to
GND
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
TA
Operating Temperature
Oto +70
°C
TB1AS
Temperature Under Bias
-10 to +85
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
-
6.0
V
O.S
V
SYMBOL
-0.5 to +7.0
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Input Low Voltage
-0.5(1)
UNIT
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
DC ELECTRICAL CHARACTERISTICS
12 MHz
SYMBOL
16.7 MHz
20 MHz
25 MHz
TEST CONDITIONS
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Ilul
Input Leakage Current
Vcc = Max., "'IN = GND to Vcc
-20
20
-20
20
-20
20
-20
-20
J.lA
IILol
Output Leakage Current
\be = Max.
cg = V1H , VOUT = GND to \be
-10
10
-10
10
-10
10
-10
10
J.lA
ICCl
Operating Current
f = 0, 'CS = V1L , Vcc= Max.,
Output Open
3000
3000
3000
3600
rnA
ICC2
Dynamic Operating Current
Vcc = Max., cg = V1L, f = fMAX
Output Open
3750
3750
4050
4500
rnA
ISBl
Full Standby Supply Current
cg ~ \be
450
450
450
600
rnA
ISB
Standby Power Supply
Current
CS
= "'IH
1500
1650
1SOD
rnA
VOH
Output High Voltage
VOL
Output Low Voltage
\be
\be
= Min., IOL = SmA
-0.2V, "'IN >
\be
-0.2V
or < 0.2V
1500
= Min., IOH = -4mA
2.4
S13-107
2.4
2.4
0.4
0.4
V
2.4
0.4
0.4
V
IDT7MB6039 DUAL (16K x 60) DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
16.6 MHz
MIN.
MAX.
12 MHz
MIN.
MAX.
PARAMETER
SYMBOL
20 MHz
MIN.
MAX.
25 MHz
MIN.
MAX.
UNIT
READ CYCLE
-
tLE
Latch Enable Width
8
t AS
Address Setup lime to LE
4
tAH
t AA(2)
Address Hold lime from LE
3
Address Access lime
45
tAcS
Chip Select lime
-
6
2
1.5
1.5
-
1.5
-
35
-
30
-
25
ns
30
-
25
-
20
ns
-
6
2
-
6
2
ns
ns
ns
tOE
Output Enable lime
-
22
-
17
-
13
-
10
ns
t OHZ (l)
Output Diasable to Output in High Z
2
16
2
14
2
10
2
8
ns
t OLZ (l)
Output DiaSable to Output in Low Z
5
-
5
-
5
-
5
-
ns
40
NOTES:
1. Guaranteed but not tested.
2. LE tested.
TIMING WAVEFORM OF READ CYCLE
ADDRVALID
ADDR
t(AS)
LE
tAA
OE·
t(OHZ)
t(OLZ)
DATA VALID
DATA
CST.~
*
tACS
S13-108
/
IDT7MB6039 DUAL (16K x 60) DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
12 MHz
MIN.
MAX.
PARAMETER
SYMBOL
16.6 MHz
MIN.
MAX.
20 MHz
MIN.
MAX.
25 MHz
MIN.
MAX.
UNIT
WRITE CYCLE
6
-
6
-
ns
2
2
-
ns
ns
17
-
11
-
ns
0
7
ns
tcw
Chip Select to End of Write
35
-
25
twp
Write Pulse Width
30
25
tow
Data Valid to End of Write
20
-
-
13
-
13
-
tOH
Data Hold Time
0
7
0
7
0
7
tLE
Latch Enable Width
8
-
6
tAS
Address Setup Time to LE
4
2
tAH
Address Hold Time from LE
3
1.5
tAW (2)
Address Valid to End of Write
40
-
30
1.5
25
20
20
1.5
23
18
NOTES:
1. Guaranteed but not tested.
2. LE asserted.
TIMING WAVEFORM OF WRITE CYCLE
ADDRVALID
ADDR
t(AS)
----+4----- t(AH)
-----.j
LE
14------------- t(AW) ---------------t
~--------t~P)-------~~
WE·
14------ t(oW) ------I~
DATA
DATA VALID
ADDRVALID
14------- t(cW)-------~f_-----
S13-109
ns
ns
ns
IDT7MB6039 DUAL (16K x 60) DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
TRUTH TABLE
MODE
CST CS2 DE WE
OUTPUT
POWER
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
Standby
H
X
X
X
HighZ
Standby
C IN
Input Capacitance
Standby
X
H
X
X
HighZ
Standby
C OUT
Output Capacitance
Read
L
L
L
H
DOUT
Active
Read
L
L
H
H
High Z
Active
Write
L
L
X
L
DIN
Active
CONDITIONS
TYP.
UNIT
VIN = OV
30
pF
VOUT= OV
18
pF
NOTE:
1. This parameter is sampled and not 100% tested.
FULLY ASSEMBLED MODULE SCREENING FLOW(1)
TEST METHOD
LEVEL
a) @ 25°C and Power
Supply Extremes
100%
b) @ Temperature and Power
Supply Extremes
100%
a) @ 25°C and Power
Supply Extremes
100%
b) @ Temperature and Power
Supply Extremes
(IDT imposed)
100%
a) @ 25°C and Power
Supply Extremes
100%
SCREEN
Final Electrical Tests
Static (DC)
Functional
Switching (AC) or
Dynamic
External Visual
b) @ Temperature and Power
Supply Extremes
(IDT imposed)
100%
IDT Specification
100%
NOTE:
1. Screening of the fully assembled module is performed per the table to
assure package integrity and mechanical reliability. Finally, 100% electrical tests are performed.
ORDERING INFORMATION
IDT
xxxx
Device Type
A
Power
999
Speed
A
Package
A
Process!
Temperature
RM~
~--------------~
~
______________________
~
~------------------------------~
'-----------------------i
S13-110
Blank
Commercial (O°C to
K
QIP (Quad In-Une)
12
16
20
25
12MHz
16.7MHz
20MHz
25MHz
S
Standard Power
7MB6039
Dual (16K x 60)
+ 70°C)
(;)
Integrated Devlcehhnolosy.lnc.
DUAL(16K X 64) DATAl
INSTRUCTION CACHE
MODULE FOR GENERAL CPUs
lOT 7MB6040
FEATURES:
DESCRIPTION:
• High-speed CMOS static RAM module constructed to
support general purpose CPUs as a complete data and
instruction cache (dual 16K x 64)
The IDT7MB6040 is a 256K-byte high-speed CMOS static RAM
constructed on a multilayer epoxy substrate (FR-4) , using 30
IDT7189 (16K x 4) RAMs and 8 IDT74FCT373 latches.
The IDT7MB6040 Is organized as two separate banks of 16K x
64 with the IDT74FCT373s being used as address latches. The two
banks of RAM with their associated address latches share a
common 14-bit ADDRESS bus and common 64-bit DATA bus. The
chip select, write enable, RAM output enable and latch enable
controls for the two banks are brought out separately to support
interleaving access to the banks of RAM. Also, each bank has two
sets of address latches to reduce the capacitance loading on the
outputs of the latches and, thereby, enhance performance.
• Operating frequencies to support 12MHz,16.7MHz, 20MHz
and 25MHz
• Available in a high-density, low profile 128-pin alP (quad
in-line package)
• Surface mounted SOIC components on a multilayer epoxy
substrate
• Multiple ground pins for maximum noise immunity
• TTL-compatible I/Os
• Single 5V (±10%) power supply
PIN CONFIGURATION
GNO
00
02
04
06
Os
Wl:l
CS1 1
CS15
M5
011
013
Ao
A2
A4
~4
CS 1
CS23
0 15
0 17
°IS
020
wt:.2
CS12
CS16
M6
0 23
0 25
0 27
0 29
0 31
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
72
73
74
75
76
n
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
GNO
01
03
05
07
09
~1
GNO
010
0E'5
0 12
Vee
Al
A3
A5
GNO
LEI
LE3
~6
Vee
0 19
021
0E'2
GNO
022
0E'6
0 24
026
°2S
0 30
0 32
Vee
PIN NAMES
Do - 0 63
M291)
Vee
062
060
05S
056
GNO
Wl: 4
054
053
WE"s
051
GNO
A12
Al0
As
A6
LE2
LE4
GNO
0 47
0 45
043
wt:.7
GNO
042
wt:.3
040
Vee
037
035
033
GND
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
Vee
0 63
061
0 59
0 57
055
~4
CS14
CS1s
OE's
0 52
050
A13
All
A9
Data I/Os
Ao - A13
Address Inputs
LEI - LE4
Latch Enables
CS'f1 - CSTs
CS2 1 - CS24
RAM Selects
WEI -WEs
Write Enables
OE 1 - OEs
GND
Ground
Vee
Power Supply
RAM Selects
Output Enables
~
CS2:
0 49
04S
0 46
044
0E'7
CS'f7
CS'f3
0E'3
041
039
03S
036
034
GND
alP
TOP VIEW
NOTE:
1. For module dimensions, please refer to module drawing M29 in the
packaging section.
CEMOS is a trademark of Integrated Device Technology,lnc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated DevIce Technology. Inc.
DSC-7041/-
S13-111
IDT7MB6040 256K (16K x 64) DATA/INSTRUCTION
CACHE MODULE
DATA CACHE
INSTRUCTION CACHE
7198
A7-13
FCT
373
LATCH
COMMERCIAL TEMPERATURE RANGE
0 0 - 15
AA 7- 13
5V
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
10ns
OATA oUT
1.5V
1.5V
~
2550
See Figures 1 and 2
5V
48oa
OATA oUT
3OpF*
Figure 1. Output Load
~
'2550
5pF*
Figure 2, Output Load
(for tou ,tOHZ )
* Including scope and jig.
S13.,.112
4800
IDT7MB6040 256K (16K x 64) DATA/INSTRUCTION
CACHE MODULE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA
RECOMMENDED DC OPERATING CONDITIONS
VALUE
RATING
Terminal Voltage with Respect to
GND
UNIT
SYMBOL
MIN.
TYP.
MAX.
Vcc
Supply Voltage
4.5
5.0
5.5
°C
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
-
6.0
V
0.8
V
-0.5 to +7.0
Operating Temperature
Oto +70
TBIAS
Temperature Under Bias
-10to +85
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
.conditions above those indicated in the operational .sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PARAMETER
-0.5(1)
V 1L
Input Low Voltage
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 2Ons.
UNIT
V
RECOMMENDED OPERATING
·TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
S.OV ± 10%
DC ELECTRICAL CHARACTERISTICS
12 MHz
SYMBOL
16.7 MHz
20 MHz
25 MHz
TEST CONDITIONS
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
= GND to Vcc
-20
20
-20
20
-20
20
-20
-20
~A
Max.
~ = V1H , VOUT = GND to \be
-10
10
-10
10
-10
10
-10
10
~A
'-"N
MAX. MIN.
MAX.
Input Leakage Current
Vcc = Max.,
IILol
Output Leakage Current
\be =
Icc1
Operating Current
f = 0, ~ = V1L ' Vcc = Max.,
Output Open
3000
3000
3000
3600
mA
ICC2
Dynamic Operating Current
Vcc = Max., ~ = V1L , f = fMAX
Output Open
3750
3750
4050
4500
mA
ISBI
Full Standby Supply Current ~ ~ \be -O.2V, '-"N >
or < O.2V
450
450
450
600
mA
ISB
Standby Power Supply
Current
1500
1650
1800
mA
VOH
Output High Voltage
Vcc = Min., 10H = -4mA
VOL
Output Low Voltage
Vee
0.4
V
Ilul
\be
-0.2V
1500
~='-"H
2.4
= Min., 10L = 8mA
2.4
0.4
2.4
0.4
2.4
V
0.4
S13-113
...............
_--_._........._- ..._--_ _._"" _.__.... _._----..
..
IDT7MB6040 256K (16K x 64) DATA/INSTRUCTION
CACHE MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
12 MHz
MIN.
MAX.
PARAMETER
16.6 MHz
MIN.
MAX.
20 MHz
MAX.
MIN.
25 MHz
MIN.
MAX.
UNIT
READ CYCLE
tLE
Latch Enable Width
8
t As
Address Setup Time to Le
4
tAH
t AA(2)
Address Hold Time from Le
3
Address Access Time
6
-
6
-
6
-
ns
2
-
2
2
-
ns
1.5
-
1.5
-
1.5
-
ns
45
-
35
30
ns
40
-
30
20
ns
17
13
-
24
22
-.
-
10
ns
-
t ACS
Chip Select Time
tOE
Output Enable Time
-
t OHZ (l)
Output Diasable to Output In High Z
2
16
2
14
2
10
2
8
ns
t OLZ (l)
Output Diasable to Output In Low Z
5
-
5
-
5
-
5
-
ns
25
NOTES:
1. Guaranteed but not tested.
2. LE tested.
TIMING WAVEFORM OF READ CYCLE
ADDRVALID
ADDR
teAS)
LE
tAA
OE·
t(OHZ)
t(OLZ)
DATA VALID
DATA (OUT)
~,~
i
t ACS
S13-114
/
IDT7MB6040 256K (16K x 64) DATA/INSTRUCTION
CACHE MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
SYMBOL
12 MHz
MIN.
MAX.
PARAMETER
16.6 MHz
MIN.
MAX.
20 MHz
MIN.
MAX.
25 MHz
MIN.
MAX.
UNIT
WRITE CYCLE
tLE
t AS
Latch Enable Width
8
Address Setup Time to LE
4
tAH
Address Hold Time from LE
3
tAw (2)
Address Valid to End of Write
40
tcw
Chip Select to End of Write
35
twp
Write Pulse Width
30
tow
Data Valid to End of Write
20
tOH
Data Hold Time
0
-
-
6
2
-
30
-
25
25
20
-
25
-
-
1.5
-
1.5
20
-
17
13
-
10
0
-
0
6
13
0
2
6
2
1.5
22
17
-
-
NOTES:
1. Guaranteed but not tested.
2. LE asserted.
TIMING WAVEFORM OF WRITE CYCLE
ADDRVALID
ADDR
t(AS) - - - _....- - - - t(AH) - - - - - . . j
LE
~------------ t(AW) ---------------~
~-----------t~~-------~~
OE*
\+---------- t(ow) -----~
DATA (OUT)
ADDRVALID
DATA VALID
14------- t ( c W ) - - - - - - - : l ._ _ _ __
S13-115
ns
ns
ns
ns
ns
ns
ns
ns
IDT7MB6040 256K (16K x 64) DATA/INSTRUCTION
CACHE MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
TRUTH TABLE
DE WE
MODE
'C'ST
~
Standby
H
X
X
Standby
X
H
X
Read
L
L
L
H
DOUT
Active
Read
L
L
H
H
HighZ
Active
Write
L
L
X
L
DIN
Active
(TA= +25°C, f = 1.0MHz)
PARAMETER(t)
SYMBOL
OUTPUT
POWER
X
HlghZ
Standby
C 1N
Input Capacitance
X
HighZ
Standby
C OUT
Output Capacitance
CONDITIONS
TYP.
VIN = OV
30
pF
VOUT= OV
18
pF
NOTE:
1. This parameter is sampled and not 100% tested.
FULLY ASSEMBLED MODULE SCREENING FLOW(t)
SCREEN
TEST METHOD
LEVEL
a) @ 25°C and Power
Supply Extremes
100%
b) @ Temperature and Power
Supply Extremes
100%
a) @ 25°C and Power
Supply Extremes
100%
b) @ Temperature and Power
Supply Extremes
(lOT Imposed)
100%
a) @ 25°C and Power
Supply Extremes
100%
Final Electrical Tests
Static (DC)
Functional
Switching (AC) or
Dynamic
External Visual
b) @ Temperature and Power
Supply Extremes
(lOT Imposed)
100%
lOT Specification
100%
NOTE:
1. Screening of the fully assembled module Is performed per the table to
assure package Integrity and mechanical reliability. Finally, 100% electrical tests are performed.
'
ORDERING INFORMATION
lOT
xxxx
Device Type
A
Package
A
Process/
Temperature
Range
~Blank
~----~--~----~
1
1
+ 70°C)
K
FR-4 QIP (Quad In-Une)
12
16
20
12MHz
16.7MHz
20MHz
25MHz
25
~--------------------------~II S
~------------------------------------~: 7MB6~0
S13-116
Commercial (O°C to
Standard Ppwer
Dual (16K x 64)
UNIT
~
IntesJated Devlcekhnology.lnc.
8Kx 112 WRITABLE
CONTROL STORE
STATIC RAM MODULE
FEATURES:
• 8K x 112 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC TM ) - reading, writing and
interrogation
• High fanout pipeline register
• Width expandable
• DeSigned for high-speed writable control store applications
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Compact quad in-line module
• Single 5V (±10%) power supply
• Inputs and outputs directly lTL-compatible
DESCRIPTION:
The IDT7MB6042 is an 8K x 112-bit Writable Control Store
(WCS) RAM and pipeline register. It features fourteen 8K x 8
IDT7164 high-performance static RAMs and fourteen
IDT49FCT818 Serial Protocol Channel (SPC) registers. These devices are arranged to form the 8K x 112 Writable Control Store RAM
with Serial Protocol Channel for loading of the memory. Each eight
lOT 7MB6042
outputs of the RAM are connected to the D inputs of an
IDT49FCT818 in the normal fashion. The device has the serial
data-in and serial data-output bits connected to form a 112-bit Serial Protocol Channel register. The command/data (C/O) and Serial Shift Clock (SCLK) are all bus organized across the fourteen
IDT49FCT818 registers. The 112 register output bits, 8 from each
device, are separately brought out to form a 112-bit wide pipeline
register on the Writable Control Store.
In normal operation, data from the 112-bit wide memory is
loaded into the IDT49FCT818 registers on the low-to-high transition of PCLK. Reading and writing of the memory by means of the
Serial Protocol Channel are performed using the protocol of the
IDT49FCT818. (For details of this operation, please refer to the
IDT49FCT818 data sheet.) The data to be loaded can be shifted in
the serial data input by using the SCLK and a load command executed by shifting the proper command word in the serial data input
when the C/O line is in the command mode. This command will
then be executed by manipulating the C/O line and SCLK line in
the desired fashion. Data is then written into the RAM by bringing
the write enable line on the RAM memory from the high state to the
low state and back to the high state.
The IDT7MB6042 is offered as a compact, cost-effective FR-4
quad in-line module and occupies less than 9 square inches of
board space.
FUNCTIONAL BLOCK DIAGRAM
~
WE
"FK5E'
3
2
cs
A
WE
8Kx 112 RAM
14 - I0T7164s
~
I/O
I/O
I/O
I/O
501
500
Cfrj
SCLK
PCLK
o
IOT49FCT818
Y
~
Y111- Y104
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1969 Integrated Device Technology, Inc.
DSC-702111
513-117
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GNO
Ao
A2
A4
SCLK
SOl
Y105
Y107
Y109
Y111
~1
PClK3
Yoo
Y9a
Y100
Y102
Y88
Yeo
Y92
Y94
<:>E11
Y80
Y82
Y84
Y86
Y72
Y74
Y76
Y78
c:5E"9
PClK 2
Y84
Yee
YS8
Y70
Y56
Y58
Yeo
Y62
c:5E"7
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
83 GNO
84 A1
85 A3
86 A
87 C~
88 Y104
89 Y106
90 Y108
91 Y110
92 <:>E13
93 WE1
94 <:>E12
95 Y97
96 Ygg
97 Y101
98 Y103
99 Y89
100 Y91
101 Y93
102 Y95
103 <:>E10
104 Y81
105 Y83
106 Ya5
107 Y87
108 Y73
109 Y75
110 Yn
111 Y79
112 GNO
113 c:5E"a
114 Y65
115 Y87
116 Y69
117 Y71
118 Y57
119 Y59
120 Y61
121 Ye3
122 ~2
123 Vee
Vee
A6
Aa
A 10
A12
Y7
Y5
Y3
Y1
<:>Eo
GNO
Y15
Y13
Y10
Y9
Y23
Y21
Y 19
~~
Y
M3d 1)
31
Y29
Y 27
Y25
c:5E"3
Y39
Y37
Y35
Y33
~o
PClK 1
Y47
Y45
Y 43
Y41
Y55
Y53
Y51
Y49
c:5E"6
GNO
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
Vee
A7
A9
A11
SOO 111
Y6
Y4
Y2
Yo
PClKo
<:>E1
Y14
Y12
Y10
Y8
Y22
Y2Q
Y1a
Y16
S0087
Y3Q
Y28
Y26
Y24
c:5E"4
Y38
Y36
Y34
Y32
WEo
c:5E"5
Y46
Y44
Y42
Y40
Y54
Y52
Yso
Y48
~
GNO
NOTE:
1. For module dimensions, please refer to module drawing M30 in the
packaging section.
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
RATING
Terminal Voltage with
Respect to GNO
RECOMMENDED DC OPERATING CONDITIONS
COMM.
UNIT
-0.5 to +7.0
V
TBrAs
Temperature Under Bias
-55 to +125
TSTG
Storage Temperature
-55 to +125
°c
°c
°c
lOUT
OC Output Current
50
mA
TA
Operating Temperature
Oto +70
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
MIN.
TYP•
.MAX.
UNIT
Vcc
Supply Voltage
4.5
5.0
5.5
V
GNO
Supply Voltage
0
0
0
V
VrH
Input High Voltage
2.2
6.0
V
VrL
Input Low Voltage
-
0.8
V
SYMBOL
PARAMETER
-0.5(1)
NOTE:
1. VrL (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
Vee
5.0V
S13-118
±
10%
~----------------------...-.---.,,-
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
TRUTH TABLE
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
MODE
CS
OE
WE
OUTPUT
POWER
SYMBOL
CONDITIONS
TYP.
UNIT
Standby
H
H
X
HighZ
Standby
C1N(D)
V1N = OV
10
pF
Standby
H
L
X
DOUT
Standby
Input Capacitance
Data
C1N(A)
Input Capacitance
Address and Control
V1N = OV
120
pF
COUT
Output Capacitance
Vour= OV
10
pF
Read
L
L
H
DOUT
Active
Read
L
H
H
HighZ
Active
Write
L
L
SPCll)
Active
SPCll)
NOTE:
1. This parameter is sampled and not 100% tested.
PIN DESCRIPTION
PIN NAME
PCLK
DESCRIPTION
I/O
I
Parallel Data Register Clock
Address Bus Pins (Ao = LSB, A12 = MSB)
Ao-12
I
Yo-11l
I/O
OEy
I
SDI
I
SDO
0
...
Parallel Data Register Output Pins (Yo = LSB, Yl1l = MSB)
Output Enable for Y Bus (Overidden by SPC Inst. 8 & 14)
Serial Data In for SPC Operation. Data and command shifts in the Least Significant Bit first
Serial Data Out for SPC Operation. Data and command shifts out the Least Significant Bit first
c/l5
I
Mode Control for SPC
SCLK
I
Serial Shift Clock for SPC Operations
CS
I
Intemal RAM Chip Select
WE
I
Internal RAM Write Enable
ROE
I
Internal RAM Output Enable
NOTE:
1. See SPC commands for proper execution of write cycle.
S13-119
-._-_._-----._._-------_._---_..... _....
_._-
_--
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
Vee = 5V +10%
TEST CONDITIONS
PARAMETER
SYMBOL
Ilu l
Input Leakage (Address & Control)
Vee = Max., V1N = GND to Vcc
Ilu l
Input Leakage (Data)
Vee = Max., V1N = GND to Vee
IILol
Output Leakage
Vee= Max.
~ = ~H' VOLrr = GND to Vee
VOL
Output Low Voltage
Vee = Min., 10L = 32mA
VOH
Output High Voltage
Vee = Min., 10H = -15mA
MIN.
MAX.
UNIT
-
100
J.lA
15
J.LA
15
J.LA
-
0.4
V
2.4
-
V
Operating Current
f = O,"CS = V1L , Vee = Max.,
Output Open
-
1500
mA
lee2
Dynamic Operating Current
Vcc = Max., ~ = \t; f = fMAX
Output Open
-
2380
mA
IS8
Standby Supply Current
~=VIL
mA
Full Standby Supply Current
~ ~ Vee - O.2V, V1N
-
560
IS81
280
mA
ICCl
> Vee - 0.2V or < 0.2V
AC ELECTRICAL CHARACTERISTICS
Vce = 5V+10%
SYMBOL
30ns
PARAMETER
MIN.
35ns
MAX.
MIN.
MAX.
40ns
MIN.
MAX.
SOns
MIN.
MAX.
60ns
MAX.
MIN.
UNIT
READ CYCLE
t Ae
Address Valid to PCLK Set Up
30
-
35
tcs
~ Valid to PCLK Set Up
30
35
t OESU
ROE" Valid to PCLK Set Up
17
-
tpcy
PCLK to Output Valid
10
tOE
~ Asserted to Output Valid
-
10
-
tOHZ
~ Negated to Output In High
10
-
-
30
Z
-
20
12
12
12
40
-
50
40
-
50
15
-
25
-
15
15
30
-
60
-
ns
15
15
ns
15
-
15
ns
15
-
15
ns
-
ns
60
35
ns
ns
WRITE CYCLE
28
23
-
28
-
0
-
0
-
tAW
Address Valid to End of Write
25
tew
Address Valid to End of Write
25
twp
Write Enable Pulse Width
23
t WeD
Cont/Dat to End of Write
tAS
Address Setup Time
30
S13-120
35
-
45
-
55
35
45
-
55
33
-
53
30
-
35
-
2
-
2
-
2
43
40
ns
ns
ns
ns
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vee = 5V+l0%
-
SPCTIMING
PARAMETER
SYMBOL
t pLH
t pHL
tsu
tH
T2
SCLI< High to SOO
T3
SOl to SOO (Stub Mode)
MIN.
-
T6
C/r5 Low to SOO
-
S2
C/f5 to SCLK High
15
S3
SOl to SCLK High
8
S4
Y or 0 to C/r5 Low
5
S5
C/f5 to PCLI< High
12
S6
Y to PCLK High
5
H2
C/r5 from SCLK Low
12
H3
SOl from SCLK High
T4
C/r5 Low toY
T5
SCLK High to Y
35ns
MAX.
MIN.
15
-
210
15
15
15
H4
Y or 0 to C/f5 Low
2
H5
SCLK High to PCLK High
2·
-
2
15
8
5
15
210
15
15
15
-
40ns
MIN.
MAX.
SOns
MAX.
MIN.
60ns
MIN.
MAX.
-
-
20
ns
ns
25
ns
5
12
-
5
-
12
2
-
2
2
-
2
-
2
-
2
-
-
2
H7
Y from PCLK High
3
-
3
-
3
-
15
12
-
12
5
-
5
-
12
-
5
2
2
2
2
3
C/r5 Low to 0 or Y Valid
-
15
-
15
-
20
-
WI
PCLK (High & Low)
10
-
10
-
15
-
15
W2
SCLK (High & Low)
30
-
30
35
C/f5 High
30
-
30
-
35
W3
-
S13-121
20
25
8
12
= ~H
-
-
-
NOTES:
20
25
8
8
12
1. Guaranteed but not tested.
ns
15
-
15
ns
310
-
2
15
22
-
25
15
-
15
25
2
-
22
-
15
25
-
20
20
35
-
-
20
20
35
UNIT
310
-
5
12
22
310
C/r5 from PCLK High
t (1,2) Z2,Z3
ZHL
2."OE
MAX.
H6
t Hz!I,2) 2z.4z SCLK High to 0 or Y High Z
LZ<1,2) 3z,5z c/f5 High to 0 or Y High Z
tw
30ns
20
-
5
ns
ns
ns
ns
ns
ns
2
-
2
-
ns
3
-
ns
-
20
ns
20
ns
-
20
ns
2
2
15
35
35
-
ns
ns
ns
ns
ns
ns
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.1 (1)
ADDRESS
_ _ _ _-----JX___
~
-
~"'~I---------
t Ac
.. '
1 4 - - - - - t OESU ----~
~O.1.2
\4------- tos ------~
y
PCLK
NOTES:
1. WE Is High for Read Cycle.
2. Transition Is measured ±200mV from steady state.
S13-122
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
1 + - - - - - - - - - - tAw - - - - - - - - - . .
~O.1.2
---+--
--+~------twp~)-----~
Ciri
-----------~~------twCD------~
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)(1,2,3,4,5)
ADDRESS
=:)K
tAW
~V
'~
~O.1.2
~tAS
tcw
L
Ciri
l'
t WCD
NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (wp) of a low ~ and a low WE.
3. tWR is measured from the eariier of ~ or WE going high to the end of the write cycle.
4. If the ~ low transition occurs simultaneously with or after the WE low transition, the outputs remain In the high Impedance state.
5. m:>E =
"'H
S13-123
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
GENERAL AC WAVEFORMS FOR PARALLEL INPUTS AND OUTPUTS
PCLK
y
D<__
~
tpcy
~y
GENERAL AC WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS
SCLK
SOl
SDO
(DECODE)
1
@)+-I-I---t-PLH-(stu-b-m-od-e-)--'
.\
(EXECUTE)
----------------------------~~I·~---t-w---~·~I~~W-3------
S13-124
_.
__._--_._.__
....
_--_. __....
_
_-_..... _---
....
....
-----------------------
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DETAILED WAVEFORMS OF SERIAL PROTOCOL OPERATIONS
Y -
SPC Data (Inst 0)
D -
SPC Data (Inst. 2)
PARALLEL DATA REGISTER -
SET STUB MODE (Inst. 12)
Status - - - - SPC Data (Inst. 4)
SCLK
SCLK
C/I5
c/I5
\
1":1'-·--ts-u-~·I~®-S2--
®
D. Y. (')E.
PCLK
--<
I)
--~--
SDO
®I-' -I- -I@
tsu
tH
~-
SDO
,
t pHL
tpHL
SPC Data CONNECT Y TO D (Inst. 5)
SPC Data -
SPC Data -
SCLK
c/I5
c/I5
D
Y
I.
SPC Data
PARALLEL DATA REGISTER (Inst. 10)
Y (Inst. 8)
CONNECT D TO Y (Inst. 14)
D (Inst. 9)
SCLK
Y -
SPC Data (Inst. 1)
SET SERIAL MODE (Inst. 11)
SYNCHRONOUS W/PCLK (Inst. 3)
SPC Data -
SCLK
SCLK
C/I5
C/I5
PCLK
PCLK
~----~----~
1HZ
:I~
PARALLEL DATA REGISTER SYNCHRONOUS
W/PCLK (Inst. 13)
Y
S13-125
._._--------- ..__ .- ._._.. _ - - -
I0T7MB6042 SKx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
DETAILED FUNCTIONAL BLOCK DIAGRAM
SOl
r---
D
-----------------------------,
SERIAL PROTOCOL COMMAND & DATA REGISTERS
C/[5
PCLK
SCLK -I---
PCLK
&
COMMAND
,<>-----
REGISTERS
SDO
S13-127
Y
'O"E"y
IOT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
Opcode 3 transfers data on the Y pins to the SPC data register
on the next PCLK, thus achieving a synchronous observation of the
SPC data register in real time. This operation can be forced to repeat without shifting In a new command by pulsing C/Dlow-hlghlow after each PCLK. As soon as data Is shifted out using SCLK, the
command is terminated and must be loaded In again.
Opcode 5 connects Y to D. Opcodes 6 and 7 are reserved,
hence designated NO-OP.
Connect Y to 0 (Inst 5)
SERIAL
PROTOCOL
y -+ SPC Data Synchronous w/PCLK (Inst 3)
SCLK
o
SOl
0
SOl
c/r5
SERIAL
PROTOCOL
DATA
&
COMMAND
PCLK
REGISTERS
ITE'y
SCLK
DATA
&
COMMAND
C/r5
y
SOO
A>-----
ITE'y
SPC Data -+ Y (Inst. 8)
SOl
0
y
SOO
SERIAL
PROTOCOL
SCLK
C/r5
Opcode 4 is used for loading status into the SPC data register.
The format of bits is shown below.
7
6
5
PCLK
DATA
&
COMMAND
.0----- ITE'y
REGISTERS
0
SOO
y
Opcode 8 is used for transferring SPC data directly to the Ypins.
When executing opcode 8, the state of OEy·ls a "do not care"; that
is, data will be output even if OE y = HIGH. Opcode 9 is used for
transferring SPC data to the D pins. Qperands 8 and 9 can be temporarily suspended by raising the C/D Input and resumed by lowering the Ctr5. As soon as SCLK completes transition, the command is terminated.
Status -+ SPC Data (Inst 4)
SOl
o
SOl
SERIAL
PROTOCOL
SERIAL
PROTOCOL
SCLK
C/r5
SCLK
PCLK
DATA
&
COMMAND
C/!5
ITE'y
REGISTERS
SOO
Y
DATA
&
COMMAND
PCLK
REGISTERS
ITE'y
SOO
S13-128
y
IDT1MB6042 8K x 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
Opcode 10 is used for transferring data from the SPC data register into the parallel data register, irrespective of the state of PCLK.
However, PCLK must be static between ci5 going high-te-Iow and
SCLK going low-te-hlgh.
STUB MODE
DEVICE #2
DEVICE #3
DEVICE #4
SDI--~--,---~---.---+;---,---~~SDO
SPC Data -+ Parallel Data Register (lnsl10)
SDI
D
SDI--~---r---rr---r---~.
SERIAL
PROTOCOL
SCLK
DATA
COM~AND r-v'----...,..--......
C/C5
PCLK
Opcode 13 transfers data from the SPC data register to the parallel data register on the next PCLK. Opcode 14 connects the D bus
to the Y. Operation 14 can be temporarily suspended by raiSing the
C/O input and resumed by lowering the C/O input again. The operation is terminated by SCLK.
REGISTERS
SPC Data -+ Parallel Data Register Synchronous w/PCLK (Insl13)
y
SDO
SDI
Opcodes 11 and 12 are used to set Serial and Stub Mode, respectively. After executing one of these opcodes, the device remains in this mode until programmed otherwise. The Serial mode
is the default mode that the IDT49FCT818 powers up in. In Serial
mode, commands are shifted through the SPC command register
and then to the SDO pin. This is the typical mode used when several varieties of devices that utilize the SPC access method are employed on one serial ring.
SERIAL
PROTOCOL
SCLK
CiD
SERIAL MODE
DEVICE #1
501
DEVICE #2
DEVICE #3
DEVICE #4
D
PCLK
DATA
&
COMMAND
REGISTERS
DEVICE #5
500
In Stub mode, SDI is connected directly to SDO. In this way, the
same diagnostic command can be loaded into multiple devices of
like type. For example, in four clock cycles the same command
could be loaded into 8 IDT49FCT818s (64-bit pipeline register).
Dissimilar devices must be segregated into serial scan loops of
similar type, as shown below. During the command phase, the serial shift clock must be slowed down to accommodate the delay
from SDI to SDO through all of the devices. The slower clock is typically a small tradeoff compared to the reduced number of clock
cycles.
SDO
y
Connect D to Y (Insl14)
SDI
D
SERIAL
PROTOCOL
SCLK
C!F5
DATA
&
COMMAND
REGISTERS
SDO
S13-129
PCLK
.0-------- O""i:y
IDT7MB6042 8Kx 112 WRITABLE
CONTROL STORE STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
Opcodes 3 and 13 transfer data synchronous to the PCLK which
means that the high-te-Iow on the ci5 input is an arm signal. The
data and command can be shifted in while the PCLK is running.
The C/O line is dropped prior to the desired PCLK edge and raised
before the next edge. Instruction 13 can be repeated over many
times by leaving the C/O line low during multiple transitions of the
PCLK while not clocking SCLK. PCLK cycles can even be skipped
by raising the C/O input during the desired clock periods. Instruction 3 can be repeated by pulsing the C/O high after each PCLK.
The ability to continuously execute a synchronous command
can provide major benefits. For example, the synchronous read
(Instruction 3, Y to SPC data) instruction could be clocked into the
SPC data register. Then, it could be continuously executed by
pulsing the C/O line high. When the whole system is stopped
(PCLK quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted out
and the current state of the parallel register can then be observed,
allowing for the observation of two states of the parallel register (the
current and the previous).
CJ[5
SCLK
EXECUTE
(SPCCMD)
PCLK
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DATAoUT
:Q
2550
5V
480n
DATA OUT
30pF*
:Q
2550 .
Figure 1. Output Load
ORDERING INFORMATION
xxxx
Device Type
999
Speed
A
A
Package
Process/
Temperature
Range
~BI"'k
~------------~I K
I
30
35
~----------------------~ 40
50
60
~--------------------------~l S
~----------------_--_ _~I 7MB6042
S13-130
Commercial (O°C to
+ 70°C)
QIP (Quad In-Line)
}
5pF*
Figure 2. Output Load
(for t OLZ ' t cHZ ' t OHZ'
tWHZ and tow)
* Including scope and jig.
IDT
4800
Speed" N"",,,,,,,,,,d,
Standard Power
8K x 112 WCS Module
Only
._..•. -....
~-----------------
t;)
IntesratedDevIce~ Inc.
DUAL (8K x 64)
DATA/INSTRUCTION
CACHE MODULE FOR
IDT79R3000 CPU
------------ -----
..... ~-.~.•
ADVANCE
INFORMATION
IDT 7MB6043
FEATURES:
DESCRIPTION:
• High-speed CMOS static RAM module constructed to support
the IDT79R3000 RISC CPU as a complete data and instruction
cache (dual BK x 64)
• Operating frequencies to support 12MHz, 16.7MHz and 20MHz
IDT79R3000
• Available in a high-density,low profile 12B-pin QIP (quad in-line
package)
• Surface mounted SOIC components on a multilayer epoxy
substrate
• Multiple ground pins for maximum noise immunity
• On-board address latches for direct interface to the IDT79R3000
CPU
• TIL compatible I/Os
• Single 5V (±10%) power supply
The IDT7MB6043 is a 12BK-byte high-speed CMOS static RAM
constructed on a multilayer epoxy substrate (FR-4), using 16
IDT7164 (BK x B) RAMs and B IDT74FCT373 latches.
The construction and specifications of this module have been
optimized to support its use as a complete BK deep Instruction and
Data cache for the IDT79R3000.
The IDT7MB6043 is organized as two separate banks of BK x 64
with the IDT74FCT373s being used as address latches. The two
banks of RAM with their associated address latches share a common 13-bit ADDRESS bus and a common 64-bit DATA bus. The
chip select, write enable, RAM output enable and latch enable
controls for the two banks are brought out separately to support
interleaving access to the two banks of RAM. Also, each bank has
two sets of address latches to reduce the capacitance loading on
the outputs of the latches and, thereby, enhance performance.
PIN CONFIGURATION
PIN NAMES
GNO
Do
02
04
06
08
WE, (3)
CST 1(3)
CS1 5(3)
WE5(3)
0 11
0,3
Ao
A2
A4
0 ,4
N.C.
N.C.
0 ,5
017
0 ,8
020
WE2(3)
CS12(3)
CS16(3)
WE6(3)
023
0 25
0 27
029
0 31
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
66
67
68
69
70
71
72
73
74
75
76
GNO
0,
03
05
07
09
DE, (3)
GNO
010
DE5 (3)
0 ,2
Vee
IT A,
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
A3
As
GNO
LE1
LE3
0,6
Vee
0,9
021
0E2(3)
GNO
022
0E"6(3)
024
026
0 28
0 30
0 32
Vee
M2g )
'
Vee
062(4)
060(4)
058
056
GNO
WE4(3)
0 54
0 53
WE8(3)
051
GNO
A12
A '0
A8
A6
LE2
LE4
GNO
047
045
0 43
WE7(3)
GNO
042
WE3(3)
040
Vee
037
035
033
GNO
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
Vee
063(4)
061(4)
059
057
055
0i:4(3)
CS14(3)
CS18(3)
DE8 (3)
052
050
N.C.
All
A9
A7
N.C.
N.C.
0 49
0 48
0 46
044
01:7(3)
CS17(3)
CS13(3)
0E"3(3)
041
039
038
036
034
GNO
Do - 059
Data I/Os
Ao - All
Address Inputs
LE1 - LE4
Latch Enables
CS1,(3) - CS18(3)
RAM Selects
WE ,(3) - WE 8(3)
Write Enables
oEP) - DE8(3)
Output Enables
GNO
Ground
Vee
Power Supply
N.C.
No Connection
NOTES:
1. All GNO pins must be grounded for proper operation.
2. All Vee pins must be connected to + 5V for proper operation.
3. Active Low Signal.
4. These pins must be connected to GN 0 or Vee through a resistor
for proper operation in the 10T79R3000 application.
QIP
TOP VIEW
NOTE:
1. For module dimensions, please refer to module drawing M29 in the
packaging section.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
DSC-7031/-
© 1989 MIPS Computer Systems. Inc. All Rights Reserved.
513-131
I DT7M B6043 12SK (SK x 64) CMOS STATIC RAM
FR-4 alP MODULE
COMMERCIAL TEMPERATURE RANGE
INSTRUCTION CACHE
7164
A(O-6) - - - - - - - - -..........,
2 (8K x8)
....- - 0(0-15)
---1---+---+----LE3 ----t---.......
WE'(5). 0E(5). CS1(5)
. A(7-12)
--------.--t--t
. . . . . - - - 0(16-31)
7164
2 (8Kx 8)
WE'(7).
0(32-47)
~). CST(7) .:........:+-..:....----I---+---~
LE4
- - + - - - -......
7164
2 (8Kx S)
0(48-63)
WE'(8). "C5E"(8). CST(8) - - - - - - - - - - - - - - _ _ "
DATA CACHE
-t
A(O-6) - - - - - - - - -......
WE'(1). 0E(1).
~1) ---J--~-+--+-----..
LE1
A(7-12)
0(0-15)
----+-----.
--------..-t--t
---~ 0(16-31)
7164
2 (8Kx 8)
0(32-47)
-+------11---/------..
- - + - - - -......
WE'(3). 0E(3). CST(3)
LE2
0(48-63)
WE'(4). 0E(4). CST(4) - - - - - - - - - - - - - - - - "
S13-132
DUAL (4K X 64) DATAl
INSTRUCTION CACHE
MODULE FOR IDT79R3000
CPU
ADVANCE
INFORMATION
lOT 7MB6044
FEATURES:
DESCRIPTION:
• High-speed CMOS static RAM module constructed to
support the IDT79R3000 RISC CPU as a complete data and
instruction cache (dual 4K x 64)
• Operating frequencies to support 12MHz, 16.7MHz and
20MHz IDT79R3000
• Available in a high-density, low profile 128-pin QIP (quad
in-line package)
• Surface mounted SOIC components on a multilayer epoxy
substrate
• Multiple ground pins for maximum noise immunity
• On-board address latches for direct interface to the·
IDT79R3000 CPU
The IDT7MB6044 is a 64K-byte high-speed CMOS static RAM
constructed on a multilayer epoxy substrate (FR-4) , using 8
IDT71586 (4K x 16) Latched RAMs.
The construction and specifications of this module have been
optimized to support its use as a complete 4K deep Instruction and
Data cache for the IDT79R3000.
The IDT7MB6044 is organized as two separate banks of 4K x 64
with the IDT71586s being used as address latched RAMs. The two
banks of RAM with their associated address latches share a
common 12-bit ADDRESS bus and a common 64-bit DATA bus.
The chip select, write enable, RAM output enable and latch enable
controls for the two banks are brought out separately to support
interleaving access to the two banks of RAM.
• TTL compatible I/Os
• Single 5V (±10%) power supply
PIN CONFIGURATION
GND
D(o)
D(2)
D(4)
D(6)
D(8)
WE(l)
CS1(1)
CS1(S)
WE(s)
~11)
D(13)
A(o)
A(2)
A(4)
D(14)
N.C.
N.C.
O(lS)
0(17)
0(18)
vJg20)
(2)
CS1(2)
CS1(6)
WE (6)
0(23)
D(2S)
D(27)
Dc29)
D(31)
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65 GND
66 D(l)
67 D(3)
68 D(s)
69 D(7)
70
71
(1)
72 GND
73 ~O)
74
(S)
75 D(12)
76 Vcc
77 A(l)
78 A (3)
79 A(s)
80 GND
81 LE1
82 LE3
83 D(16)
84 Vee
85 D(19)
86 ~1)
87
(2)
88 GND
89 ~2)
90
(6)
91 D(24)
92 D(26)
93 D(28)
94 D(3O)
95 D(32)
96 Vee
PIN NAMES
Do - DS9
~
M2g 1)
Vcc
D(62)
0(60)
D(S8)
D(S6)
GND
WE (4)
D(54)
~S3)
(8)
D(Sl)
GND
N.C.
A(10)
A(8)
A(6)
LE2
LE4
GND
D(47)
0(4S)
~43)
(7)
GND
~42)
(3)
D(40)
Vee
0(37)
D(3S)
0(33)
GND
128
127<4)
12&4)
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
Datal/Os
Address Inputs
Vcc
D(63£4)
Ao -All
4
D(61i )
LE1 - LE4
Latch Enables
D(S9)
D(S7)
CS11 - CS18
RAM Selects
WEl - WE8
Write Enables
~S)
m)
1 (4)
CS1(8)
0E"(8)
D(S2)
D(5O)
N.C.
A(ll)
A (9)
~~B.
N.C.
D(49)
D(48)
D(46)
(1)
67 Vee
68 D(9)
69 D(ll)
70 P1A(1)
71 P1A(3)
72 P1A(s)
73 P1LE2
74 P1A (7)
75 P1A (9)
76 P1A(11)
n
78 ~1~~3)
(2)
79
80
81
82
83
0(13)
0(15)
0(17)
GND
0(58)
0(56)
D(54)
~52)
(4)
GND
D(50)
D(48)
P2A(o)
P2A(2)
P2A(4)
P2LE1
P2A(6)
P2A(8)
P2A(10)
pf~12)
(1)
D(46)
D(44)
D(42)
~O)
SE-9)
(2)
(3)
Vee
0(38)
D(36)
0(34)
0(32)
D(3O)
GND
84 GNO
85
86
87
88
89
D(21)
0(23)
0(25)
D(27)
D(29)
90 GNO
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
Vee
(S9)
D(S7)
D(55)
o
~3)
(4)
GNO
D(Sl)
D(49)
P2A(l)
P2A(3)
P2A(5)
P2LE
P2A(7)
P2A(9)
P2A(11)
~§~~3)(2)
0(47)
D(4S)
0(43)
~1)
(3)
CS(2)
0(39)
D(37)
0(35)
0(33)
0(31)
GND
Do - OS9
Oata liDs
P1A(0) - P1A(13)
Address Inputs
--"-
P2A o - P2A 13
Invalidate Address
P1LE1
Oata Address Latch Enable
P1LE2
Instruction Address Latch Enable
'P"f"C5E" 1
'I5lOE 2
Instruction Address Enable
'I52OE" 1
Invalidate Data Address Enable
Data Address Enable
~2
InValidate Instruction Address Enable
P2LE 1
InValidate Data Address Latch Enable
P2LE2
Invalidate Instruction Address Latch Enable
CS 1 -CS 2
RAM Selects
~P) -~J3)
Write Enables
or: p) - or: J3)
Output Enables
GND
Ground
Vee
Power Supply
NOTES:
1. All GND pins must be grounded for proper operation.
2. All Vcc pins must be connected to + 5V for proper operation.
3. Active Low Signal.
OIP
TOP VIEW
CEMOS is a trademark of Integrated Device Technology,lnc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated DevIce Technology. Inc.
DSC-7044/-
S13-135
----_._-_.__.. _.-....---_._-
IDT7MB6049 DUAL (16K x 60) DATA/INSTRUCTION
CACHE MODULE FOR IDT79R3000 CPU (MULTIPROCESSOR)
COMMERCIAL TEMPERATURE RANGE
INSTRUCTION CACHE
DATA CACHE
I
I
P2A (0-6)
I
r::::::L.--
P2A (0-6)
-...-----!;;.~
FCT
~
7198
I
I
AC(0-6)
-
Ji~H
-, r;:-
P1A O- 6
16Kx4
~
r::::::L.--
P2LE(1)
WI:(3)
P2LE(2)
~
7198
16Kx 4
TI.._ _..I
01:(3)
'F5R5E(2)
I I
esT(2)
~
I
0(16-31)
7198
P2A(7-13)
FCT
373
LATCH
P1A(7-13
I"'"
--- -
"'~
P2A(7-13
~.
16Kx 4
P1A.l7-13
I-AA (7-13)
7198
- - r-
AC(7-13)
WI: 2)
L-_.j.-.+~
16Kx 4
I
L...-----;;:::=-_-.
0(32-35)
1-1-;:-'
16Kx4
I
WI: 4LJ
01:(4)
I 0(36-39)
1/2 FCT
AO(10-13)
FCT
373
AO(0-6
'-~ LATCH
244~'
I
I
--r-
t--
P1LE1(1) .
I
1/2 FCT 10(36-39)
244
~'
I
--I"'"
~
7198
~)
7198
~.
1r-01:~(2)==_ _~
FCT
AB(10-13)
373 IAB(Q-6
LATCH
~.
~
16Kx4
~~~
0(16-31)
7198
FCT
373
LATCH I - -
r-
I----l I
L...-----;;:::::::..._-,
.....
~)
7198
P1LE1(2)
16Kx4
16Kx4
JSlOE'(2)
~~I,..;
L...-_~~~
-4
"'-;:::::L ...
I
L...-_~~~
FCT
373
LATCH
7198
.
~)
--- -AB(7-13)
f-:-:--
---
---'
I
; 373
LATCH
-i:::!
16Kx4
1'--_--'
S13-136
I
FCT
-
7198
~
A°(7-13)
16Kx4
~)
IDT7MB6049 DUAL (16K x 60) DATA/INSTRUCTION
CACHE MODULE FOR IDT79R3000 CPU (MULTIPROCESSOR)
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
120-PIN QIP
··............................
............................ ..
08000080
0 80000 80
D idO
idO
O~OOOO~O
··............................
........................... ...
S13-137
t;)
JntegJated Devk:e~Inc.
DUAL(8K x 64) DATAl
INSTRUCTION CACHE
MODULE FOR IDT79R3000
CPU (MULTIPROCESSOR)
ADVANCE
INFORMATION
lOT 7MB6051
FEATURES:'
DESCRIPTION: .
• High-speed CMOS static RAM module constructed to
support the IDT79R3000 RISC CPU in a multi-processor
system as a complete data and instruction cache (Dual SK x
64)
IDT7MB6051 is a 12SK-byte high-speed CMOS static RAM constructed on a multilayer epoxy substrate (FR-4), using 161DT7164
(SK x S) RAMs and S IDT4FCT373 latches.
The IDT7MB6051 supports use in a multi-processor system by
providing data address invalidation latches on-board. The
IDT7MB6051 is organized as two separate banks of 16K x 64 with
the IDT74FCT373s being used as address latches. The two banks
of RAM with their associated address latches share a common
14-bit ADDRESS bus and a common 64-bit DATA bus. The chip
select, write enable, RAM output enable and latch enable controls
for the two banks are brought out separately to support interleaving
access to the two banks of RAM. Also, each bank has two sets of
address latches to reduce the capacitance loading on the outputs
of the latches and, thereby, enhance performance.
• Additional data address Invalidation latches on-board to
facilitate use in a multi-processor system
•
Operating frequencies to support 12 MHz; 16.7 MHz and
20 MHz IDT79R3000
• Available in a high-density, low profile 144-pin QIP (quad
In-line package)
• Surface mounted SOIC components on a multilayer epoxy
substrate
•
Multiple ground pins for maximum noise immunity
• TTL-compatible I/Os
• Single 5V (±10%) power supply
PIN CONFIGURATION
GND
Do
D2
D4
De
Da
Wl:l
~1
~s
Wl:s
Dll
D13
P2Ao
P2A2
P2A4
l5TC5'E'
Ao
A2
A4
D14
N.C.
N.C.
DIS
D17
D18
~
CST 2
CST e
Wl: e
D23
D2S
D27
D29
D31
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
GND
Dl
D3
Ds
D7
D9
0'E'1
GND
Dl0
O'E's
~2
Vcc
P2Al
P2A3
P2As
PIN NAMES
Vcc
D62
Doo
Dsa
DS6
GND
Wl:4
D54
DS3
Wl: a
DSI
GND
P2A12
P2Al0
P2A8
P2Ae
A12
AlO
A8
A6
N.C.
P2LE
GND
D47
D4S
D43
Wl:7
GND
D42
~3
D40
Vee
D37
D3S
D33
GND
l520E
AI
A3
As
GND
P1LE 1
P1LE2
~6
Vee
D19
D21
~2
GND
D22
0'E'6
D24
D26
D28
D30
D32
Vee
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
alP
TOP VIEW
Vcc
D63
D61
DS9
DS7
Dss
~
~4
8
O'E' a
DS2
Dso
N.C.
P2All
P2A9
P2A 7
N.C.
All
A9
A7
N.C.
N.C.
D49
D48
D4e
D44
Do - DS9
Data I/Os
Ao - A13
Address Inputs
P2Ao - P2A 13
P1LE1
Data Address Latch Enable
Invalidate Address
P1LE2
Instruction Address Latch Enable
l5TC5'E'
Data Address Enable
~
Invalidate Address Enable
P2LE
Invalidate Address Latch Enable
~l -CST8
RAM Selects
CS2 l - CS24
RAM Selects
WE l - WE8
Write Enables
DEl - OE 8
Output Enables
GND
Ground
Vcc
NC
Power Supply
No Connection
~7
CST 7
CST3
0'E'3
D41
D39
D38
D3e
D34
GND
NOTES:
1. All GND pins must be grounded for proper operation.
2. All Vee pins must be connected to + 5V for proper operation.
CEMOS is a trademark of Integrated Device TechnologY,lnc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
OSC-704S/-
© 1989 Integrated Device Technology. Inc.
S13-138
JDT7MB6051 12SK (SK x 64) CMOS STATIC RAM
FR·4 QIP MODULE
DATA CACHE
COMMERCIAL TEMPERATURE RANGE
INSTRUCTION CACHE
S13-139
G
Integrated Devlce1echnology. Inc.
256K (256K x 1-BIT)
CMOS STATIC RAM
SIP MODULE
lOT 7MC156
FEATURES:
DESCRIPTION:
• High-density 256K (256K x 1) CMOS static RAM module
• Single 5V (±10%) power supply
• Inputs and outputs directly TIL-compatible
The ID17MC156 is a 256K (256K x 1-blt) high-speed static RAM
module constructed on a co-fired ceramic substrate using four
IDT7187 64K x 1 static RAMs In surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The ID17MC156 is offered in a 28-pin
ceramic SIP (single in-line package). At only 350 mils high, this low
profile package is ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing greater than three IDT7MC156 modules to be
stacked per Inch of board space.
The ID17MC156 is available with maximum access times as fast
as 25ns and maximum power consumption of 1.8 watts. The module also offers a full standby mode of 440mW (max.).
All Inputs and outputs of the ID17MC156 are TIL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
Is used, requiring no clocks or refreshing for operation, and providIng equal access times for ease of use.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
.
• Available in low profile 28-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 600mW (typ.)
- Full standby: less than 30mW (typ.)
• Utilizes ID17187s high-performance 64K static RAMs produced with advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
Vee
A4
Al
As
A13
WEo·
. ()
CEl
A2
A12
As
A10
WEl
~1
Ao
A7
A9
A6
~2
WE2
DATA our
DATA IN
A3
All
CE3
WE3
GND
A14
A15
64Kx 1
RAM
10
11
12
13
14
15
16
17
18
19
ADDRESS
(")
()
64Kx 1
RAM
c")
64Kx 1
RAM
c")
c")
64Kx 1
RAM
16/
/
M19(1)
DATAour
20
21
22
23
24
25
PIN NAMES
26
27
28
SIP
SIDE VIEW
NOTE:
1. For module dimensions, please refer to module drawing M19
in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.
Ao-A15
Address Unes
DIN
Data Input
Dour
Data Output
~o-3
Chip Enable
WEo-3
Write Enable
Vee
Power
GND
Ground
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
© 1989 Integrated Devfce Technology. Inc.
OSC-7oo2/1
S13-140
IDT7MC156 256K (256K x 1-Bm
CMOS STATIC RAM SIP MODULE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage with Respect
toGND
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS'
(1)
VALUE
UNIT
MIN.
TYP.
MAX.
-0.5 to +7.0
V
Vcc
Supply Voltage
4.5
5.0
5.5
V
0
0
0
V
-
6.0
V
-
0.8
V
PARAMETER
SYMBOL
TA
Operating Temperature
Oto +70
°C
GND
Supply Voltage
TBlAs
Temperature Under Bias
-55 to +125
°C
V1H
V1L
Input High Voltage
TSTG
Storage Temperature
lOUT
DC Output Current
-55 to +125
°C
50
mA
Input Low Voltage
2.2
-0.5(1)
UNIT'
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratIng only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AMBIENT
TEMPERATURE
Vee
5.0V ± 10%
DC ELECTRICAL CHARACTERISTICS
\bc = 5.0V ±10%. Vee (Min.) = 4.5V. Vcc (Max.) = 5.5V. VLC = 0.2V. VHC = Vcc - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
IDT7MC156
(2)
(1)
TYP.
MAX.
MAX.
(3)
UNIT
lIu l
Input Leakage Current
Vcc = Max.; VIN = GNDtoVcc
15
.:..15
J.lA
IILol
Output Leakage Current
Vcc = Max.• ~ = "'IH.
15
;::;1§.::;
J.lA
ICCl
Operating Power Supply
Current
CS
110
225
00«(
mA
120
245
~:
mA
ICC2
Dynamic Operating Current
\loUT
"'L.
=
Vcc= Max.•
Output Open. f = 0
CS
= "'IL. Vcc = Max.•
Output Open. f = fMAX
ISB
Standby Power Supply
Current
~::::: "'H or (TTL Level)
Vcc = Max.• Output Open
ISB1
Full Standby Power Supply
Current
CS ::::: VHC. "'IN ::::: \4ic or VLC
Vcs = Max.• Output Open
Output Low Voltage
10L = SmA. Vcc = Min.
Output High Voltage
10H = -4mA.
VOL
VOH
= GND to Vcc
\Icc. =
Min.
NOTES:
1. Vcc = 5V. TA = +25°C
2. tM = 35. 45. 45. 55ns
3. tM = 25. 30ns
S13-141
,,'
90
180
:;?jtg
mA
::.::;::::::.::;:
6
60
0.4
2.4
t.oo::
./:9:4
-
mA
V
V
IDT7MC156 256K (256K x l-Bm
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
GNDto3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
DATAoUT
DATAOUT
4800
~3OpF
. - - - . - - ! .
255Q
5V
~
48OO
2550
Figure 1. Output Load
5pF*
Figure 2. Output Load
(for t CLZ1 ,2' toLZ' t CHZ1 ,2' t oHZ'
tOW.tWHZ )
*Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
(Vcc
= 5V ±10%, TA = O°C to + 70°C)
SYMBOL
PARAMETER
IDT7MC156S25 IDT7MC156S30 IDT7MC156S35 IDT7MC156S45 I DT7MC156S55
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
UNIT
READ CYCLE
30
-
35
-
45
-
55
ns
30
-
35
-
-
-
45
55
ns
::.:.:;:;::~
-
30
-
35
-
45
-
55
ns
Chip Select to Output in Low Z
5 .:::::::::::::::::::-
5
-
5
-
5
-
5
-
ns
tCHZ (1)
Chip Select to Output in High Z
- . ::::::tt::·
20
-
25
-
25
-
30
-
30
ns
tOH
t pU (l)
Output Hold from Address Change
fr::::'::':::/
5
-
5
-
ns
0
0
-
5
.:Qt::::}·
-
5
Chip Select to Power Up Time
-
0
-
0
-
ns
t PO (l)
Chip Deselect to Power Down Time
25
-
30
-
35
-
45
-
55
ns
t Rc
Read Cycle Time
25
tAA
Address Access Time
-
tAOS
t CLZ1 . 2 (1)
Chip Select Access Time
-
;.)!:!:~.::::.
':::'::2£)"
.:::
2 ....
NOTE:
1. This parameter guaranteed but not tested.
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = O°C to + 70°C)
SYMBOL
PARAMETER
IDT7MC156S25 IDT7MC156S30 IDT7MC156S35 IDT7MC156S45IDT7MC156S55
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
UNIT
WRITE CYCLE
twc
Write Cycle Time
25
.:;}:i:;:::
30
35
45
55
ns
tcw
Chip Selection to End of Write
25
t/t;
25
30
40
50
ns
Address Valid to End of Write
25
·:::::\I:·:....
25
30
40
50
ns
Address Set-up Time
5
5
5
5
5
ns
20
25
35
45
ns
a
a
a
0
::::::iI::::::'
Write Pulse Width
20 .::;;:;;:;~~~::~::'
Write Recovery Time
o;:~:iI/::
t WHZ (l)
Write Enable to Output in High Z
;::::':'..
tow
Data to Write Time Overlap
twp
Data Hold from Write Time
Output Active from End of Write
-
ns
"':';':;::.:.,'
.:::'
.4~::::;?
.::I~:/::
'::::::::0;
20
25
25
20
20
5
5
a
0
NOTE:
1. This parameter guaranteed but not tested.
S13-142
30
25
30
ns
25
ns
5
5
ns
0
0
ns
IDT7MC156 256K (256Kx 1-81T)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
1...-----tACS-----~
1 _ - - - - tCLZ (5) _ _ _~
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
=l
..
DATAoUT
2(1,2,4)
t Ac
.1
tM
.1
tOH
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
3(1,3,4)
DATAoUT
NOTES:
1. ~ is High for Read Cycle.
2. Device is continuously selected, CS = V1L•
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.
S13-143
-------------_. __._-------------_.._ - - - -
_._-----------------------------.
__
.
IDT7MC156 256K (256Kx 1-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS
~
----./
~
<
)K:
tAW
)r
~
t
: - t - t AS
tWR
(7)
WP
...... ~
f4tOHZ
I-
~,
t
(6)--.
WHZ
(6)
-tow--t
(4) ....
(4)
DATA OUT
tow_
•.. '> .• ', ..........
------~E---*~---tOH
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)
twc
ADDRESS
~
)(
- /(
tAW
'~
_ t AS
/V
tWR
tcw
tow
/
I'
f4-
tOH
,
"I
NOTES:
1. M or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low ~ and a low M.
3. tWR is measured from the earlier of ~ or M going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the M low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
513-144
- - - - _ .._..
__
.__. .-
IDT7MC156 256K (256K xl-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
TRUTH TABLE
B
MODE
~
WE
OUTPUT
POWER
Standby
H
X
X
HlghZ
Standby
Read
L
L
H
DoUT
Active
Read
L
H
H
HighZ
Active
Write
L
X
L
DIN
Active
SYMBOL
~N
(TA= +25°C, f = 1.0MHz)
TEST
Input Capacitance
CONDITIONS
TYP.
UNIT
VIN = OV
35
pF
ov
40
pF
COUT
Output Capacitance
VOUT=
NOTE:
1. This parameter Is sampled and not 100% tested.
ORDERING INFORMATION
lOT
xxxx
A
A
Device Type
Package
Process/
Temperature
Range
I
I Blank
+ 70°C)
CS
Ceramic SIP
25
30
35
}_nN~
45
55
S13-145
Commercial (O°C to
S
Standard Power
7MC156
256Kx 1-Bit
~
IntegJated Devlcekhnology. Inc.
1 MEGABIT (1 024K x 1-BIT)
CMOS STATIC RAM
SIP MODULE
PRELIMINARY
lOT 7MC4001
FEATURES:
DESCRIPTION:
• High-density 1 megabit (1024K x 1) CMOS static RAM
module
The IDT7MC4001 is a 1 megabit (1024K x 1-bit) high-speed
static RAM module with separate I/O. The module is constructed
on a co-fired ceramic substrate using four IDT71257 256K x 1 static
RAMs in surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The IDT7MC4001 is offered in a 30-pin
ceramic SIP (single in-line package). At only 420 mils high, this low
profile package is Ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing five IDT7MC4001 modules to be stacked per inch of
board space.
The IDT7MC4001 Is available with maximum access times as
fast as 35ns, with maximum power consumption of 1.35 watts. The
module also offers a full standby mode of 330mW (max.).
A" inputs and outputs of the IDT7MC4001 are lTL-compatible
and operate from a single 5V supply. Fu"y asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access times for ease of use.
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profile 30-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 35ns (max.)
• Separate I/O lines
• Low power consumption
- Dynamic: 1.35W (max.)
- Fu" standby: 330mW (max.)
• Single 5V(±10%) power supply
• Inputs and outputs directly lTL-compatible
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Vee
A4
AI
A5
A'3
WEo
CEo
A2
A'2
A8
A,o
WE,
CE,
Ao
A7
A9
As
CE2
WEl
DATAoUT
DATA IN
A3
All
CEl
WE3
GND
A14
A'5
A'6
A17
()
()
256Kx 1
RAM
10
11
12
13
14
15
16
17
18
19
ADDRESS
() 1
256Kx 1
RAM
I I
()
6 6
256Kx 1
RAM
256Kx 1
RAM
()
18L
/
M20(1)
I
20
21
DATA
IN
22
23
24
25
I
DATA
OUT
PIN NAMES
26
27
28
29
30
SIP
SIDE VIEW
NOTE:
1. For module dimensions, please refer to module drawing M20 in the
packaging section.
AO-17
Address
DATA IN
Data Input
DATA OUT
Data Output
CSO- 3
Chip Select
WE"0-3
Write Enable
Vee
Power
GND
Ground
CEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology. Inc.
DSC-7003/1
S13-146
-------------. -
- - - - - - - - - - - - - - - - - - . - - - . -••- - - - . _ - - - - - - -
.•
IDT7MC4001 1 MEGABIT (1024K xl-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM
RATING
Terminal Voltage with Respect
toGND
VALUE
UNIT
-0.5 to +7.0
V
TA
Operating Temperature
Oto +70
°C
TslAS
Temperature Under Bias
-55 to +125
°C
TSTG
Storage Temperature
-55 to +125
°C
lOUT
DC Output Current
50
MIN.
TYP.
MAX.
Vcc
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
V1L
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.51)
-
O.S
V
PARAMETER
SYMBOL
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
UNITS
NOTE:
1. V1L = -3.0V for pulse width less than 2Ons.
AMBIENT
TEMPERATURE
Vee
5.0V ±10%
DC ELECTRICAL CHARACTERISTICS
Vec = 5.0V ±10%, Vcc (Min.) = 4.5V, Vcc (Max.) = 5.5V, VLC = O.2V, VHC = Vcc SYMBOL
PARAMETER
Ilul
Input Leakage Current
IILol
Output Leakage Current
ICCl
Operating Power Supply
Current
TEST CONDITIONS
IDT7MC4001
MIN.
= Max.; VIN = GNDtoVcc
Vcc = Max.• ~ = \'IH' VOUT = GND to 'be
~ = "'IL' Vcc = Max.,
Output Open, f = 0
CS = "'IL' Vcc = Max.•
Output Open, f = fMAX
Dynamic Operating Current
Iss
Standby Power Supply
Current
~;:: "iH or (TTL Level)
Vcc = Max.• Output Open
ISSl
Full Standby Power Supply
Current
CS ;::VHC • \'IN ;:: VHC or :5 V LC
Vcs = Max.• Output Open
= SmA, Vcc = Min_
Vee = Min.
Output Low Voltage
10L
Output High Voltage
'OH = -4mA.
S13-147
MAX.
1.P..
Vcc
'CC2
VOL
VOH
0.2V
UNIT
jJA
....;:.:.;.;.
tOO::::
2.4
rnA
IDT7MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
q
5V
5V
AC TEST CONDITIONS,
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
Input Pulse Levels
Input Rise/Fall Times
Input TIming Reference Levels
Output Reference Levels
Output Load
DATAoUT
2550
..
, q4SOO
480Cl
DATAoUT
2550
:lOpF'
5pF*
Figure 2. Output Load
Figure 1. Output Load
(for t cLZ1 , 2. t oLZ • t CHZ1 , 2. t OHZ '
tow and tWHV
* Including scope and jig.
, AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±100/0, TA = DOC to +7DOC)
SYMBOL
PARAMETER
IDT7MC4001 S35
MAX.
MIN.
IDT7MC4001 S45
MIN.
MAX.
IDT7MC4001 S55
MIN.
MAX.
UNIT
READ CYCLE
tRO
Read Cycle Time
35
-
45
-
55
-
ns
tM
Address Access Time
-
35
45
-
55
ns
tAOS
t oLZ1 ,2(1)
Chip Select Access Time
-
35
-
45
-
55
ns
Z
Chip Select to Output in High Z
10
-
10
-
10
-
ns
-
25
-
35
-
45
ns
Output Hold from Address Change
5
-
5
-
ns
0
-
5
Chip Select to Power Up Time
0
-
0
-
ns
-
35
-
45
-
55
ns
tCHZ (1)
tOH
t pU (1)
Chip Select to Output In Low
t
(1)
Chip Deselect to Power Down Time
PO
NOTE:
1. This parameter guaranteed but not tested.
AC ELECTRICAL CHARACTERISTIC'S
(Vcc = 5V ±10%, TA = O°C to + 70°C)
SYMBOL
PARAMETER
IDT7MC4001 S35
MIN.
MAX.
IDT7MC4001S45
MIN.
MAX.
IDT7MC4001 S55
MIN.
MAX.
UNIT
WRITE CYCLE
-
55
50
5
-
5
-
25
-
30
-
40
ns
-
25
-
35
-
ns
two
Write Cycle Time
35
tow
Chip Selection to End of Write
30
tAW
Address Valid to End of Write
30
tAS
Address Set-up Time
5
twp
Write Pulse Width
25
tWR
t WHZ (1)
Write Recovery Time
5
-
Write Enable to Output In High Z
-
tow
Data Valid to End of Write
20
tOH
Data Hold from Write Time
5
tow (1)
Output Active from End of Write
5
NOTE:
1. This parameter guaranteed but not tested.
S13-148
45
40
40
5
35
5
5
50
5
45
5
5
ns
ns
ns
ns
ns
ns
ns
ns
IDT7MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
1....-----tACS----+--~
1....- - - - t C L Z (5) _ _ _~
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
~
•
DATAoUT
2(1,2,4)
t AC
.1
tAA
• I
tOH
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
3(1,3,4)
DATAoUT
NOTES:
1. ~ is High for Read Cycle.
2. Device is continuously selected, CS = V1L.
3. Address valid prior to or coincident with CS transition low.
4. 'O!: = V1L
5. Transition Is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
S13-149
IDT1MC4001 1 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS
~
---./
~
)(
K
,
tAW
~'"
t
- tAS
tWA
(7)
WP
f-
~,
"'~
I'-- t WHZ( 6 ) -
tOHZ
(6)
_tOW--j
(4)
DATA OUT
(4)
tow_
tOH
------~E---~~---TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)
twc
ADDRESS
=:)K
)K
tAW
f4--
t AS
"
/V'
tWA
tcw
~
WE
,
I'
tow
tOH
,
'1
NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlaP (tw of a low ~ and a low WE.
3. tWR is measured from the earlier of ~ or ~ going high to the end of write cycle.
4. During this period, 110 pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the ~ low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and ~ot 100% tested.
S13-150
IDT7MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE
TRUTH TABLE
~
MODE
WE
OUTPUT
SYMBOL
POWER
(TA= +25°C. f = 1.0MHz)
TEST
Standby
H
X
HighZ
Standby
CIN
Input Capacitance
Read
L
H
DOUT
Active
COUT
Output. Capacitance
Write
L
L
HighZ
Active
CONDITIONS
TYP.
UNIT
VIN = OV
35
pF
Vour= OV
20
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
xxxx
999
A
A
Device Type
Speed
Package
Process/
Temperature
Range
I
I Blank
S13-151
Commercial (OOC to
+ 70°C)
CS
Ceramic SIP
35
45
55
} Speed" Nanosecond,
S
Standard Power
7MC4001
1024K x 1-Bit
t;)
Integrated DevIce~Inc.
256K (16K x 16) 'CMOS
STATIC RAM DUAL SIP
MODULE
lOT 7MC4005
.'
The IDT7MC4005 is a 16-bit wide 256K (16K x 16) static RAM
module constructed on a co-fired ceramic substrate using four
IDT7198 16K x 4 static RAMs In lead less chip carriers. Extremely
fast speeds can be achieved due to the use of 64K static RAMs
fabricated in IDT's high-performance, high-reliability CEMOS
technology. The IDT7MC4ooS is available with access times as
fast as 20ns, with minimal power consumption.
The IDT7MC family of ceramic DSIPs offers the optimum In
packing density and profile height. The IDT7MC4oo5 is packaged
in a 36-pin ceramic DSIP (dual single-in-line package). The dual
row configuration allows 36 pins to be placed on a package
1.8 Inches long and .27 Inches wide. At only .500 inches high, this
low profile package Is Ideal for systems with minimum board
spacing. Extremely high packing density can also be achieved,
allowing four IDT7MC4oo5 modules to be stacked per 1.2 inches of
board space.
All inputs and outputs of the IDT7MC4oo5 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
Is used, requiring no clocks or refreshing for operation, and providIng equal access and cycle times for ease of use.
AIiIDT military module semiconductor components are manufactured in compliance to the latest revision of MIL-STD-883,
Class B, making them Ideally suited to applications demanding
the highest level of performance and reliability.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
• High-density 16-bit word 256K (16K x 16) static RAM module
• Low profile 36-pin sldebraze ceramic DSIP (dual slngle-inline package)
• Fast access time: 20ns (max.)
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• CEMOS 1M process virtually eliminates alpha particle soft
error rates (with no organic die coating)
• Single 5V (±10%)
• Inputs/outputs directly TTL-compatible
• Multiple GND pins for maximum noise Immunity
DESCRIPTION:
1/00
1/01
1/°2
1/°3
Ao
Al
A2
A3
A4
As
As
A7
1/04
1/°5
I/Oe
I/Dr
Vcc
ADDRESS
1/°15
1/°14
1/°13
1/°12
GND
A 13
~
16Kx 16
RAM
~
A12
A11
A 10
A9
Aa
we
I/O
16
1/°11
1/°10
1/°9
I/Oa
~
we
GND
~
DATA
PIN NAMES
OE'
Data Inputs/Outputs
Addresses
Chip Select
Write Enable
Output Enable
Vee
GND
Power
Ground
1/°0-15
Ao- 13
NOTE:
1. For module dimensions, please refer to module
drawing M22 in the packaging section.
~
we
CEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-7032/-
1989 Integrated DevIce Technology. Inc.
S13-152
IDT7MC4005 256K (16K x 16) CMOS STATIC
RAM DUAL SIP MODULE
ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
Oto +70
TBIAS
Temperature
Under Bias
-10 to +S5
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
mA
-0.5 to +7.0
-0.5 to +7.0
-55 to +125
SYMBOL
V
°C
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
6.0
V
V1L
Input Low Voltage
0.5(1)
-
O.S
V
NOTE:
1. V1L = -3.0V for pulse width less than 2Ons.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLVVOLTAGE
GRADE
Military
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Commercial
,Vee
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL
MILITARY
MIN.
MAX.
TEST CONDITIONS
PARAMETER
COMMERCIAL
MIN.
MAX.
UNIT
lIu l
Input Leakage Current
(Address & Control)
Vee = Max.
ViN = GND to Vee
-
40
-
20
)JA
Ilu l
Input Leakage
(Data)
Vee = Max.
ViN = GND to Vee
-
10
-
5
)JA
IILol
Output Leakage
Vee = Max.
= ViH, \loUT = GND to Vee
-
10
-
5
)JA
VOL
Output Low Voltage
Vee = Min., 10L = SmA
-
0.4
-
0.4
V
VOH
Output High Voltage
Vee = Min., IOH= -4mA
2.4
-
V
CS'
-
2.4
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ±10%, TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL
PARAMETER
TEST CONDITIONS
IDT7MC4005
20n.
COM'L
MIL
IDT7MC4005
25n.
MIL
COM'L
IDT7MC4005
30,35,45,55n.
COM'L
MIL
UNIT
leel
Operating Current
F = 0, CS' = ViL
Vee = Max.; Output Open
480
-
480
500
400
440
IC02
Dynamic Operating
Current
Vee = Max.; CS' = ViL; f = fMAX
Output Open
600
-
600
620
500
560
mA
ISB
Standby Supply Current
-
240
240
200
220
mA
ISBl
Full Standby
Supply Current
CS = ViL
CS' ~ Vee
240
80
-
80
80
60
80
mA
V1N
-0.2V
> Vee -0.2V or < 0.2V
S13-153
mA
I DT7MC4005 256K (16K x 16) CMOS STATIC
RAM DUAL SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%. TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL
7MC4005S20 7MC4005S25 7MC4005S30 7MC4005S35 7MC4005S45 7MC4005S55
UNIT
(COM'L)
MAX. MIN.
MAX. MIN.
MAX.
MIN.
MAX. MIN. . MAX. MIN. MAX. MIN.
PARAMETER
READ CYCLE
30
-
35
-
45
-
-
30
35
-
45
30
-
35
-
5
-
5
-
5
-
20
-
20
,-
5
-
5
'10
-
13
8 ..... 1::::':}i{@H'
15
-
15
--=::;:;:::: ,:,~,tst~~~t
-
5
-
t RC
Read Cycle Time
20
-
tAA
Address Access Time
20
t AcS
Chip Select Access Time
-
t cLZ1 . 2 (1)
Chip Select to Output in Low Z
5
-
tOE
t OLZ (1)
Output Enable to Output Valid
-
15
Output Enable to Output In Low Z
5
-
t CHZ (1)
Chip Deselect to Output in High Z
8.,..
tOHZ(1)
Output Disable to Output In High Z
-
tOH
Output Hold from Address Change
5
t pU (1)
Chip Select to Power Up Time
0
t pO (1)
Chip Deselect to Power Down Time
-
-
~:':"
::""".,.
20
:':':':',',':':
.:::::~:::::.
....,.:.25
I,I:::,§",::::::::::':::::::::: -
-
""""":',' 15
" [:~~'~~::§':'::::tt':"
,,:=:::=::,
-
I",:"",...,;,.,.,..
""""~:"""
-
ns
55
ns
45
-
55
ns
-
5
-
ns
-
25
.-
35
ns
-
5
-
5
-
ns
-
15
-
15
-
20
ns
15
-
20
ns
5
-
ns
0
-
5
0
-
5
0
-
0
-
ns
-
30
-
35
-
45
-
55
ns
25
-
30
-
40
-
50
-
ns
35
50
37
-
50
-
ns
25
48
0
-
~
25
twc
Write Cycle Time
17
-h@Q
-
tcw
Chip Selection to End of Write
17
t~:~* : ~ ,:,,)~O
25
tAW
Address Valid to End of Write
17
-
25
0
-
WRITE ~YCLE
-
",,:?O
25
0
t AS
Address Set-up Time
0
twp
Write Pulse Width
17
,:IW,tt
"t'20
tWR
Write Recovery Time
0
""",{,'~tt~:t
Ii'
0
-
t WHZ (1)
Write Enable to Output In High Z
- J::/"':::::tti? -
7
-
to.:v
Data to Write Time Overlap
10 ·,:,::,:~~~,~~~:'~:n;tt
13
tOH
t oW (1)
Data Hold from Write Time
o ,t(':::'tii
0
-
Output Active from End of Write
......;....
5':::: ......
:.:.::::::::~
::
;
5
15
25
27
55
2
2
2
ns
ns
35
0
-
0
-
10
-
10
-
15
-
25
ns
15
-
15
20
-
ns
-
0
0
-
ns
5
-
5
-
25
0
-
5
-
ns
0
5
ns
ns
NOTE:
1. This parameter guaranteed but not tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
~
DATAOU,T
2550
+5V
4800
DATA OUT
,
3OpF*
Figure 1. Output Load
~
2550
4800
5pF*
Figure 2. Output Load
(for tCU1, 2, tou, t CHZ1 , 2, t OHZ '
tow and t WHZ )
* Including scope and jig.
S13-154
IDT7MC4005 256K (16Kx 16) CMOS STATIC
RAM DUAL SIP MODULE
I
TIMING WAVEFORM OF READ CYCLE NO.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1(1)
~-----------------tRC~------------~
ADDRESS
1 4 - - - - - - tACS----:--t--~
14-------- tcLZ (5) ------~
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
DATA OUT
=1
2(1,2,4)
t Rc
.1
tM
~I
tOH
DATA VALID
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
DATA OUT
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, ~ = VIL.
3. Address valid prior to or coincident with ~ transition low.
4. C5E = ~L.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
S13-155
I DT7MC4005 256K (16K x 16) CMOS STATIC
RAM DUAL SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (1)
~------------------twc----------------~~
ADDRESS
14-------------~- tAW
----------------..!
\4------twp (2) - - - - - + I
DATAoUT
----~
TIMING WAVEFORM OF WRITE CYCLE NO.2
~
(1,8)
~-----------twc-------------~
ADDRESS
~-:.....-----
tow
-------t~
~------=------tAW --------~
--------~~~~~~~~
1+-----tWP (2) _ _ _---t~
I~--~~----------
DATA OUT
NOTES:
1.
or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low ~.
3. twp is measured from the earlier of CS or
going high to the end of the write cycle.
4. During this period. I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CS low transition occurs simultaneously with the
low transitions or after the
transition, outputs remain in a high impedance state.
6. C5E' is continuously low (C5E' = \'IL)'
7. DOUT is the same phase of write data of this write cycle.
S. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be
applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
wr:.
wr:.
wr::
wr:.
S13-156
IDT7MC4005 256K (16K x 16) CMOS STATIC
RAM DUAL SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CS
OE
WE
OUTPUT
POWER
SYMBOL
CONDITIONS
TYP.
Standby
H
X
X
HighZ
Standby
CIN(D)
Input Capacitance (Data)
~N = OV
20
pF
Read
L
L
H
DOUT
Active
CIN(A)
"'IN = OV
50
pF
Write
L
X
L
Read
L
H
H
DIN
HlghZ
Input Capacitance
Address and Control
Active
20
pF
MODE
Active
Output Capacitance
VOUT = OV
CoUT
NOTE.
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
XXXX
A
A
A
Device Type
Power
Package
Process!
Temperature
y~k
L..-._ _ _ _ _ _ _....,:
'---------------11
CV
Dual Ceramic SIP.
20
25
30
35
45
55
Commercial Only
~--------------------------~IS
-I.:
I
L..-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
S13-157
Commercial (O°C to +70°C) .
Military (-55°C to + 125°C)
Semiconductor Components
Compliant to MIL-STD-883, Class B
7MC4005
} Speed In Nano""","",
Standard Power
16K x 16 Static RAM Module
UNIT
lOT 7MC4018
64K X 6 CMOS STATIC RAM
CERAMIC SIP MODULE
WITH SEPARATE DATA I/O
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT7MC4018 is a 64K x 6-bit high-speed static RAM module
constructed on a co-fired ceramic substrate using six I0T7187
64K x 1 static RAMs in surface mount packages.
The 7MC famify of ceramic SIPs offers the optimum in packing
density and profife height. The I0T7MC4018 is offered in a 40-pin
ceramic SIP (single in-line package). At only 360 mifs high, this low
profife package is ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing five I0T7MC4018 modules to be stacked per inch of
board space.
The I0T7MC4018 is avaifable with maximum access times as
fast as 20ns. Separate data inputs and outputs are supplied for
high-performance systems. Three modules can be configured to
yield 64K x 18, which is ideal for 16-bit systems with 2 parity bits.
All inputs and outputs of the I0T7MC4018 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal chip select and access times for ease of use.
All lOT military module components are compliant with the
latest revision of MIL-STO-883, Class B, making them ideally
suited to applications demanding the highest level of performance
and reliabifity.
High-density 64K x 6 CMOS static RAM module
Separate data inputs and outputs
Configurable as 64K x 18 using 3 modules
Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profife 40-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 20ns (max.) over commercial temperature
• Low power consumption
• Utilizes I0T7187s, high-performance 64K static RAMs,
produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL compatible
• Modules avaifable with semiconductor components compliant
to MIL-STO-883, Class B
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
10
11
12
13
14
15
16
64Kx3
RAM
PIN NAMES
16
17
18
M21 (1)
Ao - A15
Address Inputs
Dlo - Dis
Data Inputs
DOo - DOs
Data Outputs
WF:.o
Write Enable
for D10-2
CSo
Chip Select
for D10-2 • DOo-2
WI:1
Write Enable
for DI3-S
CS1
Chip Select
for DI3-s. D03-s
Vee
Supply Voltage
GND
Ground
64Kx3
RAM
3
3
DATA IN
DATAoUT
DATA IN
DATA OUT
NOTE:
1. For module dimensions, please refer to module drawing M21 in the
packaging section.
CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JANUARY 1989
DSC-7034/-
1989 Integrated Device Technology, Inc.
S13-158
IDT7MC4018 64Kx 6 CMOS
STATIC RAM CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to
GND
RECOMMENDED DC OPERATING CONDITIONS
(1)
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
Oto +70
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
lOUT
DC Output Current
50
50
mA
TA
-55 to +125
MIN.
TYP.
MAX.
Vcc
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
-
6
V
0.8
V
SYMBOL
°C
PARAMETER
Input Low Voltage
-0.5(1)
UNIT
NOTE:
1. VIL = -3.0V for pulse width less than 20ns.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may eause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational seetions of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
-55°C to + 125°C
GND
OV
5.0V ± 10%
O°Cto +70°C
OV
5.0V ± 10%
Vee
DC ELECTRICAL CHARACTERISTICS
Vee = 5V -+10%
SYMBOL
PARAMETERS
TEST CONDITIONS
MIN.
MAX.
UNIT
lIul
Input Leakage
(Address & Control)
Vcc = Max.
VIN = GND to \be
-
30
J-IA
lIul
Input Leakage
(Data)
Vcc = Max.
VIN = GND to Vee
-
30
J-IA
-
5
J-IA
IlLOI
= Max.
CS = VIH, Vour = GND to Vcc
Vcc = Min., IOL = 8mA
Vee = Min., IOH = -4mA
Vcc
Output Leakage
VoL
Output Low Voltage
VOH
Output High Voltage
0.4
V
-
V
2.4
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±10%
IDT7MC4018
SYMBOL
PARAMETERS
MAX. (1)
TEST CONDITIONS
MAX. (2)
UNIT
COM'L
MIL
COM'L
MIL
ICCl
Operating Current
F = 0, CS = \'JL
Vcc = Max.; Output Open
720
-
540
630
mA
ICC2
Dynamic Operating
Current
Vcc = Max.; CS
Output Open
900
-
660
720
mA
ISB
Standby Supply Current
360
-
270
300
mA
ISBl
Full Standby Supply
Current
CS = '-"L
CS ~ Vcc - 0.2V
VIN > Vee - 0.2V or < 0.2V
120
-
90
120
mA
= VII.; F = FMAX
NOTES:
1. 20, 25ns
2. 30, 35, 45, 55ns
S13-159
IDT7MC4018 64K x 6 CMOS
STATIC RAM CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V ±10%, All Temperature Ranges
SYMBOL
7MC4018S20 7MC4018S25 7MC4018S30 7MC4018S35 7MC4018S45 7MC4018S55
UNIT
COM'L ONLY COM'L ONLY
MiN • . MAX. MIN.
MAX. MIN. MAX. MIN;
MAX. MIN.
MAX. MIN.
MAX.
PARAMETER
t RC
Read Cycle Time
20
-
25
-
30
-
35
-
45
-
55
-
ns
t,tiA
Address Access Time
-
20
25
ns
25
30
35
45
-
55
20
-
45
-
-
35
Chip Select Access Time
-
30
t ACS
-
55
ns
t CLZ1 .2(1)
Chip Select to Output In Low Z
5
-
5
-
5
-
35
-
45
-
55
-
ns
t CHZ (1)
Chip Deselect to Output In High Z .
-
20
-
25
-
30
-
35
-
45
-
55
ns
5
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
ns
0
-
0
-
0
-
0
0
-
-
Chip Select to Power Up Time
-
5
t pU (1)
0
-
ns
t p ol1)
Chip Deselect to Power Down Time
-
20
-
25
-
30
-
35
-
45
-
55
ns
twc
Write Cycle Time
20
-
25
-
30
-
55
-
25
-
25
40
-
50
tAW
Address Valid to End of Write
20
25
30
40
-
50
Address Set-up Time
0
0
-
0
-
0
-
ns
Write Pulse Width
15
20
-
25
30
35
Write Recovery Time
0
0
0
-
0
0
0
-
ns
tWR
-
-
0
twp
-
25
t AS
-
-
ns
20
-
45
Chip Selection to End of Write
-
35
tcw
t WHZ (1)
Write Enable to Output in High Z
-
20
-
20
-
25
-
25
-
30
-
30
ns
tow
Data to Write Time Overlap
15
-
20
5
5
-
ns
-
tow (1)
Output Active from End of Write
0
0
-
0
-
25
5
-
25
5
-
20
Data Hold from Write Time
-
15
tOH
0
-
ns
0
20
5
0
30
5
0
ns
ns
ns
ns
NOTE:
1. This parameter guaranteed but not tested.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
. Output Load
+5V
. GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
DATA6UT.·.~.·....
2550y3OpF
4800
Figure 1; Output Load
+5V
DATAoUT
.
~
2550
.
4800
5pF*
Figure 2. Output Load
(fort cLZ1 ,2, t oLZ, t CHZ1 ,2. t OHZ '
tOW.tWHZ )
*Including scope and jig.
S13-160
IDT7MC4018 64Kx 6 CMOS
STATIC RAM.CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE (1)
~
~----------------tRC--------------~
ADDRESS
.
___________________________________
~-~---------tAA----------~·!
~----------tA~----------~
14--------- tCLZ(2)-----~
NOTES:
1. ~ is High for Read Cycle.
2. Transition is measured ± 200mV from steady state. This parameter is sampled and not 100% tested.
S13-161
- - - - - - - - - - - _ ... _-_.-
IDT7MC4018 64K x 6 CMOS
STATIC RAM CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,:S,7) .
~-----------------------twc----------------------~
ADDRESS
~--------------------tAW------------------~
--~~-------------tw?~)----------~~
tWA
~------ tOHZ (6) - - - - - - . j
DATA OUT
DATA IN
____________________________________
K~-t-ow------------ ~-------------------
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)(1, 2,:S, 5)
twc
ADDRESS
:=) <
)(
tAW
/'
'r\.
~tAS
tWR
tew
tow
/
I"
I--
tOH
"
/1
NOTES:
1.
2.
3.
4.
5.
6.
7.
wr:. or CS must be high during all address transitions.
wr:..
A write occurs during the overlap (twp) of a low CS and a low
t WR is measured from the earlier of CS or WE going high to the end of the write cycle.
During this period, the 1/0 pins are in the output state, and input signals must not be applied.
If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
During a VIr=. controlled write cycle, write pulse (t wp ) > tWHZ + tow to allow the 1/0 drivers to tum off and data to be placed on the bus for the
required tow. If ~ is high during a VIr=. controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
twP.
S13-162
IDT7MC4018 64K x 6 CMOS
STATIC RAM CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA= +25°C, f
TRUTH TABLE
MODE
CS
rn::
WE
OUTPUT
POWER
Standby
H
X
X
HighZ
Standby
Read
L
L
H
DOUT
Active
Read
L
H
H
HighZ
Active
Write
L
X
L
DIN
Active
PARAMETER(1)
= 1.0MHz)
CONDITIONS
TYP.
UNIT
CIN(D)
Input CapaCitance
(Data)
VIN = OV
20
pF
CIN(A)
Input Capacitance
Address and Control
VIN = OV
60
pF
20
pF
SYMBOL
COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
xxxx
A
999
A
A
Device Type
Power
Speed
Package
Process/
Temperature
-y~IMk
~------------~II CS
L....-___________
~
20
25
30
35
45
55
~---------------~: S
L....----------------------f
S13-163
7MC4018
Commercial (O°Cto + 70°C)
Military (-55°C to + 125°C)
Semiconductor Components Compliant
to MIL-SID-883, Class B
Ceramic SIP
Commercial onlY}
Commercial Only
Speed in Nanoseconds
Standard Power
64K x 6 Ceramic SIP Module
t;)
Integrated Devk:e"Jechnology.Inc.
512K(16Kx32)
CMOS STATIC RAM DUAL
CERAMIC SIP MODULE
lOT 7MC4032
FEATURES:
DESCRIPTION:
• High-density 32-bit word 512K (16K x 32) static RAM module.
The IDT7MC4032 is a 32-bit wide 512K (16K x 32) static RAM
module with separate 1/0 constructed on a co-fired ceramic substrate using eight IDT71982 16K x 4 static RAMs in leadless chip
carriers. Extremely fast speeds can be achieved due to the use of
64K static RAMs fabricated in lOT's high-performance, high-reliability CEMOS TM technology. The IDT7MC4032 is available with
access time as fast as 20ns, with minimal power consumption.
The 7MC family of ceramic SIPs offers the optimum is packing
density and profile height. The IDT7MC4032 is packaged in a
88-pin dual ceramic SI P. The dual row configuration allows 88 pins
to be placed on a package less than 4.5 Inches long and .27 Inches
wide. At only 520 mils high, this low profile package is Ideal for systems with minimum board spacing. Extremely high packing density can also be achieved allowing four IDT7MC4032 modules to
be stacked per inch of board space.
All inputs and outputs of the IDT7MC4032 are lTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
Is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
All lOT military module semiconductor components are manufactured In compliance to the latest revision of MIL-STD-883, Class
B, making them Ideally suited to applications demanding the highest level of performance and reliability.
• Available in low profile 88-pin sidebraze dual ceramic SIP
(dual single in-line package)
• Separate 1/0
• Fast access time: 20ns (max.)
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• High impedance outputs during write mode
• CEMOS TM process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs/outputs directly lTL-compatible
• Multiple GND pins for maximum noise immunity
FUNCTIONAL BLOCK DIAGRAM
DATA IN
"~32
ADDRESS
INPUT
14/
m
'OE'
~U.L
f'""I
'-"'
,....,
16Kx32 RAM
'""
f'""I
'-"'
OUTPUT
;'~32
DATA OUT
CEMOS Is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1989 Integrated DevIce Technology. Inc.
JANUARY 1989
050-700411
S13-164
IDT7MC4032 512K(16Kx32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
PIN CONFIGURATION (1)
GNO
01 0
Dll
01 2
01 3
01 4
015
Ole
01 7
AO
A2
A4
DI8
DI9
Dho
Dhl
Dh2
DIl3
DI14
DI15
WE
\Co
'O'E'
Dhe
DI17
DI,8
D I19
0120
DI21
DI22
D~~
A8
A10
A12
0124
0125
DI26
DI27
DI28
DI29
DI30
D~l
G D
1
Vee
2
DOo
DOl
D02
D03
D04
DOs
DOe
DCr
Al
A3
As
D08
DOg
DOlO
DOll
D012
D013
D014
D015
~L
GND
3
4
5
6
7
8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
~U
D018
D017
D018
D019
O~
D021
D022
0~3
A7
A9
An
A13
0024
D025 ·
D026
D027
D028
D029
D030
D031
Vee
NOTE:
1. For module dimensions, please refer to module drawing M23 in the
packaging section.
S13-165.
A~13
Addresses
010-31
Data Input
DOG-31
Data Output
~
Write Enable
(jE
Output Enable
~L
Chip Select (Lower)
~u
Chip Select (Upper)
V~
Power
GND
Ground
IDT7MC4032 512K (16K x 32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect to '
GND
COMMERCIAL
-0.5 to +7.0
MILITARY' UNIT
-0.5 to +7.0
Operating
Temperature
Oto +70
TSIAS
Temperature
Under Bias
-10to +85
-65 to +135
TSTG
Storage
Temperature
-55 to +125
-65 to + 150
°C
lOUT
DC Output Current
50
50
mA
TA
-55 to +125
SYMBOL
V
°C
°C
MIN.
TYP.
MAX.
Vcc
Supply Voltage
PARAMETER
4.5
5.0
5.5
UNIT
V
GND
Supply Voltage
0
0
0
V
VIH
VIL
Input High Voltage
2.2
V
-0.5(1)
-
6.0
Input Low Voltage
0.8
V
NOTE:
1. VIL = -3.0V for pulse width less than 2Ons.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to + 125°C
DoC to +70 oC
OV
5.OV
OV
5.OV
Vee
±
±
10%
10%
DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10% TA = -55°C to + 125°C and DoC to + 70°C)
SYMBOL
PARAMETERS
MIN.
MAX.
UNIT
Vcc = Max.
VIN = GND to \to
TEST CONDITIONS
-
40
pA
5
pA
pA
lIu
I
Input Leakage
(Address & Control)
lIu
I
Input Leakage
(Data)
Vcc = Max.
VIN = GND to VCC
-
IILO I
Output Leakage
Vcc = Max.
~ = VIH, VOUT
-
5
VOL
Output Low Voltage
Vcc
-
0.4
V
VOH
Output High Voltage
Vcc
2.4
-
V
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to + 125°C and DoC to
SYMBOL
PARAMETER
= GND to Vcc
= Min., 10L = 8mA
= Min., 10H = -4mA
+ 70°C)
TEST CONDITIONS
ICCl
Operating Current
F = 0, ~ = \1L
Vcc = MAX: Output Open
Icc2
Dynamic Operating
Current
Vcc = MAX: CS = ~L:
F = FlMx Output Open
Iss
Standby Supply Current
ISBl
Full Standby Supply
Current
CS = ~L
CS ~ Vee - 0.2V
~N> Vcc - 0.2V or <0.2V
IDT7MC4032
20na
MAX.
COM'L.
MIL.
IDT7MC4032
25n.
MAX.
COM'L.
MIL.
IDT7MC4032
30, 40, SO, 70n.
MAX.
COM'L.
MIL.
UNIT
960
-
960
1000
800
800
mA
1200
-
1200
1200
1000
1120
mA
480
480
480
400
440
mA
160
-
160
160
120
160
mA
S13-166
IDT1MC4032 512K (16Kx32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Ycc = 5V
± 10%)
SYMBOL
7MC4032S20 7MC4032S25
COM'L ONLY
MIN. MAX.
MIN. MAX.
PARAMETER
7MC4032S30 7MC4032S40 7MC4032S50 7MC4032S70
MIL ONLY
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX UNIT
READ CYCLE
Read Cycle Time
t Acs
30
20
Chip Select Access Time
-
20
25
k:;:::::'C
J[:;;)§:?::::::::::' -
70
50
40
20
Address Access Time
ns
30
40
50
70
ns
30
40
50
70
ns
45
ns
t CLZ1 . 2 (1) Chip Select to Output in Low Z
5
-
tOE
Output Enable to Output Valid
-
15:':':::::::;::::::::::::::
t OLZ (I)
Output Enable to Output in Low Z
5
- {:::::l'::::::::~:::r::::
-
5
-
5
-
5
-
5
-
ns
tCHZ (1)
Chip Select to Output in High Z
-
8"':':::=W:::::::
10
-
13
-
17
-
18
-
25
ns
15
5
5
-
5
5
-
20
22
-
ns
-
30
r-______17__+-_____1_8__+-______2_5-r_n_s~
~t~o~H~Z_(I)~~O_u~tP_ut
__
D_is_ab_le
__
to_O_ut~pu_t_in__
H~ig_h_
Z~______O~i~:m%~:::,___
15__;-______1_7__
tOH
Output Hold from Address Change
5
J/:tt It:::t§t
t pU(I)
Chip Select to Power Up Time
0
4.t::::; i:tt:H
t pO(I)
Chip Deselect to Power Down Time
-:20.:.
twc
Write Cycle Time
17
tcw
Chip Selection to End of Write
17
tAW
-
-
5
-
5
-
5
-
5
-
ns
0
-
0
-
0
-
0
-
ns
25
-
30
-
40
-
50
-
70
ns
25
35
45
65
-
ns
25
28
38
62
-
ns
Address Valid to End of Write
25
30
40
65
-
ns
t AS
Address Set-up Time
o
2
2
3
-
ns
twp
Write Pulse Width
25
28
38
62
-
ns
tWR
Write Recovery Time
o
o
o
o
t WHZ (I)
Write Enable to Output in High Z
tow
Data to Write Time Overlap
13
15
17
23
30
ns
tOH
Data Hold from Write Time
o
o
o
o
o
ns
tow (1)
Output Active from End of Write
5
5
5
5
5
ns
:.:...::::'7::::::::......:.:.20
17 .@I: .::::7 :::;::::
20
7
10
ns
17
12
30
ns
NOTE:
1. This parameter guaranteed but not tested.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
~
.
DATAoUT
2550;
+5V
4800
DATAoUT
.3OpF
Figure 1. Output Load
~
2550
5pF*
Figure 2. Output Load
(for t CLZ1 .2,t OLZ ' tCHZ1.2. t OHZ '
tOW.tWHz)
*Including scope and jig.
S13-167
4800
IDT7MC4032 512K (16K x 32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
~----------------tRC--------------~
ADDRESS
TIMING WAVEFORM OF READ CYCLE NO.
ADDRESS
DATAoUT
=i
2(1,2,4)
t RC
.1
tAA
.'
tOH
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
3(1,3,4)
. DATA OUT
NOTES:
1. WE is High for Read Cycle.
_
2. Device is continuously selected. CS = VII,.
3. Address valid prior to or coincident with ~ transition low.
4. DE = VIL•
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
S13-168
IDT7MC4032 512K(16Kx32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OFWRITE CYCLE NO.1 (1)
~------------------twc----------------~~
--------~
1,------------
ADDRESS
---------------.1
~--------------- tAW
I+-----twp (2)
-------+I
DATAoUT
---~~
TIMING WAVEFORM OF WRITE CYCLE NO.2
~
(1,6)
~-------------------twc--------------------~
ADDRESS
'-"--------- few
~------------:..-...--- tAW
--------~~
---------------.1
14-------- twp (2) ______~~
--------~~~~~~~,
I~~~~----------
DATA OUT
NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, 110 pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. DE is continuously low (DE = \'Id.
7. DATA OUT is the same phase of write data of this write cycle.
8. If CS is low during this period, 110 pins are in the output state. Then the data input signals of opposite phase to the outputs must not be
applied to them.
9. Transition is measured ±500mVfrom steady state. This parameter is sampled and not 100% tested.
S13-169 :
IDT7MC4032 512K (16K x 32) CMOS STATIC
RAM DUAL CERAMIC SIP MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE
TRUTH TABLE
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CS
OE
WE
OUTPUT
POWER
SYMBOL
Standby
H
X
X
HighZ
Standby
C1N(D)
Input Capacitance
Read
L
L
H
Active
C1N(A)
Write
L
X
L
CblJT
HighZ
Output Capacitance
Address and Control
C OlJT
Output Capacitance
MODE
Read
L
H
H
HighZ
Active
Active
CONDITIONS
TYP.
UNIT
V1N = OV
15
pF
~N
= OV
80
pF
VOlJT= OV
15
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
lOT
XXX)(
Device Type
A
Power
999
Speed
A
Process/
Temperature
Range
Y:LANK
Commercial (O°C to
L . . - - - - - - - - - - l CV
Dual ceramic SIP
20
25
Commercial Only
L..-_____________
+ 70°C)
Military (-55°C to + 125°C)
Semiconductor components
Compliant to MIL-STO-883, Class B
~30
40
50
70
L..-------------------~S
~---------------------__47MC4032
S13-170
}
Speed In Nanoseconds
Mil only
Standard Power
16K X 32 Static Ram Module
~
Integrated Device~ Inc.
lOT 7MP156
256K (256K X 1-BIT)
CMOS STATIC RAM
PLASTIC SIP MODULE
FEATURES:
DESCRIPTION
• High-density 256K (256K x 1) CMOS static RAM module
The IDT7MP156 is a 256K (256K x 1-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four
IDT7187 64K x 1 static RAMs in surface mount packages. Extremely fast speeds can be achieved with this technique due to use
of 64K static RAMs fabricated in I DT's high-performance, high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
IDT7MP156 is offered in a 28-pin SIP (single in-line package). The
IDT7MP156 can be mounted on 200 mil centers, yielding 1.25
megabits of memory in less than 3 square inches of board space.
The IDT7MP156 is available with maximum access times as fast
as 25ns with maximum power consumption of 1.8 watts. The module also offers a full standby mode of 440mW (max.).
All inputs and outputs of the IDT7MP156 are ITL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single In-line package) for maximum
space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 600mW (typ.)
. - Full standby: less than 30mW (typ.)
• Utilizes IDT7187 high-performance 64K static RAMs produced with advanced CEMOS TN technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly ITL-compatible
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Vee
A4
Al
A5
A13
w-t=.o
I
()
C5:J
A2
A12
A8
A10
wr=.,
Ul
Ao
A7
A9
A6
crz
w-t=.2
DATA OUT
DATA IN
A3
All
U 3
w-t=.3
A14
A15
GND
(')
64Kx 1
RAM
10
11
12
13
14
15
16
ADDRESS
1
()
64Kx 1
RAM
I
. (')
1
(')
64Kx 1
RAM
(')
64Kx 1
RAM
16/
/
M14(1)
17
18
19
I
20
DATA
IN
21
I
DATA
OUT
22
23
24
25
PIN NAMES
26
Ao-A15
27
28
~N
0,1 IT
U0-3
W!:o-3
SIP
TOP VIEW
NOTE:
1. For module dimensions, plese refer to module drawing M14 in the
packaging section.
Vee
GND
Address Unes
Data Input
Data Output
Chip Enable
Write Enable
Power
Ground
CEMOS is a trademark of Integrated Device Technology, Inc.
JANUARY 1989
COMMERCIAL TEMPERATURE RANGE
DSC-7005/1
© 1989 Integrated DevIce Technology. Inc.
S13-171
_._-----------------
· IDT7MP156 256K (256Kx 1-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
RATING
Tenninal Voltage with Respect
to GND
COMMERCIAL TEMPERATURE RANGE
R'ECOMMENDED DC OPERATING CONDITIONS
(1)
VALUE
UNIT
-0.5 to +7.0
V
TA
Operating Temperature
Oto +70
°C
TBIAS
Temperature Under Bias
-10 to +85
°C
TSTa
Storage Temperature
-55 to +125
°C
lOUT '
DC Output Current
50
mA
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause pennanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V1H
Input High Voltage
2.2
-
6.0
V
0.8
V
-0.5(1)
Input Low Voltage
V1L
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
Vee
5.OV ± 10%
DC ELECTRICAL CHARACTERISTICS
\be = 5.0V ±10%. Vee (Min.) = 4.5V. Vee (Max.) = 5.5V. VLe = 0.2V. VHc = Vee SYMBOL
PARAMETER
lIu l
IlLOI
Output Leakage Current
leel
Operating Power Supply
Current
Input Leakage Current
TEST CONDITIONS
= Max.; VIN = GND to \be
Vee = Max.• ~ = \'IH. \bUT = GND to Vee
~ = \'IL. Vee = Max.•
Vee
Output Open. f
=0
~ = \'Il. Vee = Max.•
Output Open. f = fMAX
lee2
Dynamic Operating Current
ISB
Standby Power Supply
Current
Vee
ISBl
Full Standby Power Supply
Current
CS ~VHe. \'IN' ~ ~e orVLe
Ves = Max.• Output Open
VOL
VOH
O.2V
~ ~ \'IH or (TTL Level)
Output Low Voltage
10L
Output High Voltage
IOH
= Max.• Output Open
= 8mA. Vee = Min.
= -4mA. Vee = Min.
NOTES:
1. Vee = 5V. TA = +25°C
2. tM = 35. 45. 45. 55ns
3. :tM = 25. 30ns :
S13-172
MIN.
-
IDT7MP156
TYP.(l) MAX. (2)
MAX. (3)
UNIT
-
15
.15
JlA
-
15
:::,15::
JlA
mA
mA
........
-
110
225
300:
-
120
245
330:
-
90
180
:?4P
mA
-
6
60
/~O
mA
-
-
0.4
:\0.4
V
2.4
-
-
-
V
IDT7MP156 256K (256K x 1-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2
5V
5V
DATAoUT
~
2550
4800
DATA OUT
30pF
~
2550
4800
5pF*
Figure 1. Output Load
Figure 2. Output Load
(for tCLZ1,2' toLZ' t CHZ1,2' tOHZ'
toW.twHZ)
*Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = -55°C to + 125°C and O°C to 70°C)
SYMBOL
PARAMETER
IDT7MP156S25 IDT7MP156S30 IDT7MP156S35 IDT7MP156S45 IDT7MP156S55
MAX. MIN.
MAX.
MAX. MIN.
MAX. MIN.
MIN.
MAX. MIN.
UNIT
READ CYCLE
t Ac
Read Cycle Time
25
-
30
-
35
-
45
-
55
-
ns
tAA
t ACS
Address Access Time
25
-
30
ns
30
35
45
-
55
-
-
45
25
-
35
Chip Select Access Time
-
55
ns
t CLZ1 . 2 (1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHZ (1)
Chip Select to Output in High Z
-
20
-
25
-
25
-
30
-
30
ns
tOH
t pU (l)
t po (l)
Output Hold from Address Change
5
-
5
0
-
0
-
ns
0
-
5
0
-
5
0
-
5
Chip Select to Power Up Time
Chip Deselect to Power Down Time
-
25
-
30
-
35
-
45
-
55
ns
30
-
35
45
-
55
50
25
0
-
0
-
ns
WRITE CYCLE
tAW
Address Valid to End of Write
25
t AS
Address Set-up Time
5
twp
Write Pulse Width
20
tWA
t WHZ (l)
Write Recovery Time
0
-
Write Enable to Output in High Z
-
20
-
25
-
tDW
Data to Write Time Overlap
15
20
-
20
tDH
Data Hold from Write Time
5
5
-
tow (1)
Output Active from End of Write
0
-
0
-
twe
Write Cycle Time
25
tew
Chip Selection to End of Write
25
25
25
5
20
NOTE:
1. This parameter guaranteed but not tested.
S13-173
5
35
-
-
45
-
ns
0
-
0
-
ns
25
-
30
-
30
ns
25
-
25
-
ns
5
-
5
-
5
-
ns
0
-
0
-
0
-
ns
30
30
5
40
40
5
50
ns
ns
ns
ns
IDT7MP156 256K (256K x 1-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO.
1(1)
11------ tAcs - - - - - - - . )
1....
1___- - - - tCLZ (5) _ _ _--..)
1------t
cHz
(5)
DATAoUT
TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
ADDRESS
DATAoUT
~=======t-OH=_tAA=~=--=-.-t~ -=-=~-.,~~:E-tOH-PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
3(1,3,4)
DATA OUT
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V'L and 00,
= V'L for 16 output active.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested .
rn
.813-174
IDT7MP156 256K (256K xl-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
ADDRESS
--~------ tw~7)
------..j
----~--------~I
~-------------------------
DATA OUT
__________________________________-K~tDW
tDH
i
);)1--------
DATA IN
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)
two
ADDRESS
~K
)(
tAW
~tAS
'~
~V
tWR
tow
tDW
"
I'
f-
tDH
"
II
NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low ~ and a low WE.
3. tWR is measured from the earlier of ~ or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the
low transition, the outputs remain in a high Impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
wr:.
S13-175
IDT7MP156 256K (256K x 1-BIT)
CMOSST.ATIC RAM PLASTIC.SIP MODULE
CAPACITANCE
SYMBOL
COMMERCIAL TEMPERATURE RANGE
(TA= +25°C. f = 1.0MHz)
CONDITIONS
TEST
C1N
Input Capacitance
COUT
Output Capacitance
TYP.
UNIT
V1N = OV
35
pF
VOUT= OV
40
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
xxxx
A
999
A
A
Device Type
Power
Speed
Package
Processl
Temperature
Range
1
....- - - - i \
Blank
'-----------1: S
Plastic SIP
25
30
~-----------__i 35
} Speed
In NanoSecond,
45
55
L..-------------------------------------------------------------------i'S
I
......_ _ _---'-_ _ _ _ _ _ _ _ _ _ _ _ _ _---11 7MP156
S13-176
Standard Power
. 256Kx 1-Bit
lOT 7MP456
256K (64K X 4-BIT)
CMOS STATIC RAM
PLASTIC SIP MODULE
FEATURES:
DESCRIPTION:
• High-density 256K (64K x 4) CMOS static RAM module
The IDT7MP456 is a 256K (64K x 4-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four
IDT7187 64K x 1 static RAMs in plastic surface mount packages.
Extremely fast speeds can be achieved with this technique due to
the use of 64K static RAMs fabricated in lOT's high-performance,
high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
IDT7MP456 is offered in a 28-pin SIP. The IDT7MP456 can be
mounted on 200 mil centers, yielding 1.25 megabits of memory in
less than 3 square inches of board space.
The IDT7MP456 is available with maximum access times as fast
as 25ns, with maximum power consumption of 3.3 watts. The module also offers a full standby mode of 440mW(max.).
All inputs and outputs ofthe IDTMP456 are TTL-compatible and
operate from a single 5V supply. Fully asynchronous Circuitry is
used, requiring no clocks or refreshing for operation and providing
equal access and cycle times for ease of use.
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single in-line package) for maximum
space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
-Dynamic: less than 1.2W (typ.)
- Full standby: less than 30 mW(typ.)
• Utilizes IDT7187 high-performance 64K static RAMs produced
with advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) powersupply
• Inputs and outputs directly TTL-compatible
PIN CONFIGURATION
Vcc
A4
AI
A7
DATAoUTO
DATA INO
A5
A2
AI2
A8
A10
DATAoUTl
DATAINl
Ao
A13
A9
DATA INPUT
4
ADDRESS _ _ _1.;.,;;6r---i
64Kx4 CMOS
STATIC RAM
10
11
12
13
14
15
16
As
17
DATAOUT2
DATAIN2
18
19
WE
'CE"
20
A3
All
DATAOUT3
DATA IN3
GND
A14
A15
FUNCTIONAL BLOCK DIAGRAM
M1g(1)
4
DATA OUTPUT
21
22
23
24
25
PIN NAMES
26
27
28
Ao-A15
Address Inputs
'CE"
WE
Chip Enable
Write Enable
~NO - DIN3
DoUTO - DOUT3
SIP
SIDE VIEW
NOTE:
1. For module dimensions, please refer to module drawing M19
in the packaging section.
Data Input
Vee
Data Output
Power
GND
Ground
CEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology. Inc.
OSC-7oo7/1
S13-177
IDT7MP456 256K(64K x 4-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA
TSTG
Storage Temperature
VALUE
UNIT
-0.5 to +7.0
V
o to
Operating Temperature
Temperature Under Bias
RECOMMENDED DC OPERATING CONDITIONS
(1)
RATING
Terminal Voltage with Respect
toGND
T81AS
lOUT
COMMERCIAL TEMPERATURE RANGE
°C
+70
°C
-10to +S5
-55 to +125
DC Output Current
50
°C
SYMBOL
Ilul
mA
IILol
Output Leakage Current
MAX.
UNIT
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
\1H
Input High Voltage
2.2
6.0
V
\1L
Input Low Voltage
-0.5(1)
-
O.S
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
TEST CONDITIONS
Vee = Max.; V1N = GND to Vee
V.
= Max.
ifg = V1H • VOUT = GND to Vee
CS
lecl
Operating Power Supply Current
lee2
Dynamic Operating Current
IS8
Standby Power Supply Current
1581
Full Standby Power Supply Current
VOL
Output Low Voltage
VOH
Output High Voltage
PARAMETER
Vee= 50V +10% Vce (Min) = 45V Vee (Max) = 55V
PARAMETER
Input Leakage Current
TYP.
Supply Voltage
NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
MIN.
Vcc
SYMBOL
= V1L
Vee = Max.• Output Open
F=O
"CS = \1L
Vce = Max., Output Open
f = fMAX
CS ~
\1H or (TTL Level)
Vec=Max.
Output Open
cs ~ VHe , V1N
~VHe or S VLe
Vee = Max., Output Open
MIN.
IDT7MP456
TYP, t CHZ1,2' tOHZ'
toW.tWHZ)
*Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±10%, TA = O°C to + 70°C)
SYMBOL
PARAMETER
IDT7MP456S25 IDT7MP456S30 IDT7MP456S35 IDT7MP456S45 IDT7MP456S55
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
UNIT
READ CYCLE
21>:::::::.:....
.....:.::::::::::::;::::::::-
35
45
t RC
Read Cycle Time
tAA
Address Access Time
+~::~::::::::':"""""'25
30
35
45
55
tACS
Chip Select Access Time
-f:~r:~::::~::~::~J}25
30
35
45
55
t cLZ1 . 2 (1)
Chip Select to Output in LowZ
5:~::::;::::~:::~:~:~:~:~::t-
t CHZ (l)
Chip Select to Output in High Z
::::::t~::::::~::t}20
tOH
Output Hold from Address Change
5
t pU (l)
Chip Select to Power Up Time
t po (l)
Chip Deselect to Power Down Time
d"::::::::::::tf:~::L
2!"':::::::::::::::::::::::25
WRITE CYCLE
······:-:·:::::::::;:t...
30
5
5
5
5
5
a
35
40
ns
ns
ns
a
ns
55
45
ns
ns
5
a
0
30
ns
5
35
30
25
5
55
ns
:::::::::::::::::::::::::::::::
twc
Write Cycle Time
2&:::::j::;:;:::::::::::::-
30
35
45
55
ns
tcw
Chip Selection to End of Write
2$.:~::::::::::::::::::;::;;:-
25
30
40
50
ns
tAW
Address Valid to End of Write
~~:::::::,:::::::::::::::{-
25
30
40
50
ns
t AS
Address Set-up Time
5
5
5
5
ns
twp
Write Pulse Width
:::::::2tf::::~::ttII~
20
25
35
45
ns
tWR
t WHZ (l)
Write Recovery Time
dl.Bw. }:r-
0
0
a
0
Write Enable to Output in High Z
':<':':':':':':':':':':':::::20
5
25
25
ns
30
30
ns
tow
Data to Write Time Overlap
1&:::;:::::::::::;::::;;;;:-
20
20
25
25
ns
tOH
Data Hold from Write Time
§'::f(}:
5
5
5
5
ns
tow (1)
Output Active from End of Write
ot:::::t:::::::::::::::-
a
a
a
0
ns
NOTE:
1. This parameter guaranteed but not tested.
IE
S13-179
.
__ _-_.._---_.
--_.. _._._. __ •... - ..... ..
IDT7MP456 256K(64K x 4-BIT)
CMOS STATIC RAM PLASTIC SIP MOQULE
TIMING WAVEFORM OF READ CYCLE NO.
COMMERCIAL TEMPERATURE RANGE
1(1)
~
.
ADDRESS
JooIf----'-------tRc
::::::::::~----------
________________
~I
...
-_-----tAA
14-,-~----
tAcs-------.j
DATAoUT
.
I
TIMING WAVEFORM OF READ CYCLE NO. 2 (1~3)
...
ADDRESS
DATA oUT ·
PREVIOUS DATA VALID
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. ,3(1,3)
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, ~ = VIL .
3. Address valid prior to or coincident with
transition low.
4. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
cs
S13-180
IDT7MP456 256K(64K x 4-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
~----------------------twc----------------------~
~-----------------
ADDRESS
~-------------------tAW------------------~
---'~------------twf)----------~
----~--------~I
tWR
~-------------------------
DATA OUT
___________________________________
~~-t-ow---------t-OH-~
TIMING WAVEFORM OF WRITE CYCLE NO. 2 ~ CONTROLLED TIMING) (1,2,3,5)
twc
ADDRESS
~
---./
)K
K
tAW
/~
'I\.
~tAS
tWR
tcw
,
1'-
tow
tOH
"-
-'I
NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low ~ and a low WE.
3. tWR Is measured from the earlier of ~ or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition Is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter Is sampled and not 100% tested.
S13-181
IDT7MP456 256K(64K x 4-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
CAPACITANCE
SYMBOL
COMMERCIAL TEMPERATURE RANGE
(TA= +25°C, f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
VIN = OV
35
pF
VOUT= OV
40
pF
NOTE:
1. This parameter is sampled and not 100% tested.
ORDERING INFORMATION
IDT
xxxxx
A
Device Type
Po er
999
Speed
A
Package
A
Process!
Temperature
Range
----II
1
....
'--------------------------------------~II
Blank
Commercial (O°C to
S
Plastic SIP
25
30
35
45
55
'--------------------------------------------------------------------~II S
'----------------------1:
S13-182
8MP456
}
Sp",d In N"""eond,
Standard Power
64Kx 4-bit .
+ 70°C)
4 MEGABIT (512K x a-BIT)
CMOS STATIC RAM
PLASTIC SIP MODULE
lOT 7MP4008L
FEATURES:
DESCRIPTION:
• High-density 4096K (S12K x 8) CMOS static RAM module
The IDT7MP4008L is a 4096K (S12K x 8-bit) high-speed static
RAM module constructed on an epoxy laminate surface using sixteen 32K x 8 static RAMs in plastic surface mount packages.
The IDT7MP4008L is available with maximum access times as
fast as 70ns, with maximum operating power consumption of
910mW. The module also offers a full standby mode of 430mW
(max.).
The IDT7MP4008L is offered in a 36-pin SIP (single in-line package). Surface mount SIP technology is a cost-effective solution allowing for very high packing density. The IDT7MP4008L can be
stacked on 300 mil centers, yielding greater than 12 Megabits of
memory per inch of board space.
All inputs and outputs of the IDT7MP4008L are lTL-compatible
and operate from a single SV supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
• Accesstime
- 70ns (max.)
• Low power consumption
- Dynamic: less than 910mW (max.)
- Full standby: less than 430mW (max.)
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in a 36-pin SIP (single in-line package) for maximum
space-saving
• Single SV (±10%) power supply
• Inputs and outputs directly lTL-compatible
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
NC
Vee
WE
1/02
1/03
1/00
Al
A2
A3
A4
GND
~05
10
All
A5
A 13
A14
NC
9
10
11
12
13
14
15
le
M161) 17
18
19
512Kx 8
RAM
1/0
8
~
DATA
A15
Ale
A12
A18
Ae
20
21
22
23
24
1/01
25
26
PIN NAMES
GND
Ao
A7
A8
A9
27
28
29
30
31
32
33
A O- 18
1/00-7
OE
WE
:~gr
35
I/O:
A17
Vee
36
'O'E'
34
CS
Vee
GND
NC
m
Addresses
Data Input/Output
Output Enable
Write Enable
Chip Select
Power
Ground
No Connect
SIP
SIDE VIEW
NOTE:
1. For module dimensions, please refer to moudle drawing M16 in the
packaging section.
COMMERCIAL TEMPERATURE RANGE
©
JANUARY 1989
DSC-7031/-
1989 MIPS Computer Systems. Inc. All Rights Reserved.
S13-183
-- _
.... .. _._--
..
_._--_ ..........-._ .. - . _ - - - -
._----_................._...... __..
IDT7MP4008L4 MEGABIT (512K x 8-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
....
TA
RATING
Terminal Voltage with Respect
toGND
UNIT
-0.5ta +7.0
V
Temperature Under Bias
TSTa
:Storage Temperature
SYMBOL
PARAMETER
TYP.
MAX.
5.0
5.5
0
0
0
V
Input High Voltage
2.2
6.0
V
Input Low Voltage
0.3V
-
0.8
V
Vee
Supply Voltage
GND
Supply Voltage
°C
V1H
-55 to +125
°C
V1L
50
mA
, Operating Temperature
TBIAS
lOUT
VALUE
°C
Oto +70
-10 to +85
DC,Output Current
,NOTE: ,
1; ,Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This Is a stress rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for eXtended periods may affect reliability.
MIN.
' 4.5
UNIT
VO
NOTE:
1. V1L (min.) = -2.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE
Vee
5.0V ±10%
DC ELECTR'ICAL CHARACTERISTICS'
Vce = 5.0V ±10%, Vee (Min.) = 4.5V, Vee (Max.) = 5.5V
, SYMBOL
PARAMETER
. TEST CONDITIONS
IDT7MP4008L
MIN.
MAX.
UNIT
Input Leakage Current(l)
Vee = Max.; "'IN = GND to Vec
-
40
~A
Output Leakage Current
Vee = Max.
~ = "'IH. VOUT = GND to Vee
-
40
~A
leel
Operating Power Supply Current
CS ="'IL
Vee = Max.• Output Open
f = 0
-
90
mA
lee2
Dynamic Operating Current
CS = "'IL
Vee = Max.• Output Open
f = fMAX
-
165
mA
ISB
Standby Power Supply Current
-
78
mA
rnA
lIu l
IILol
ISBl
Full Standby Power Supply Current
Vol.
Output Low Voltage
VOH
Output High Voltage
NOTE:
1. Ilu I for A15 - A18 and ~ is 400 ~A max.
CS ~ V1H
~ > Vee-O.2V
"'IN > Vee -0.2Vor < 0.2V
-
78
10L = 2.1 mAo Vee = Min.
-
0.4
V
10H = -1mA. Vee = Min.
2.4
-
V
'S13-184
IDT7MP4008L 4 MEGABIT (512K x B-Bm
CMOS STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.SV
DATAour
1.5V
- - - . - - ! .
4800
DATAour
25f Vee - 0.2V
or < 0.2V
(TA= +25°C f = 10MHz)
PARAMETER(l)
S13-191
UNIT
IDT7MPS025 512K (S4K x 8) SYNCHRONOUS
STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V +10%
7MP6025S45
7MP6025S35
SYMBOL
7MPS025S55
PARAMETER
MIN.
MAX.
MIN.
MAX.
. MIN.
UNIT
MAX•
READ CYCLE
tcp
Read Cycle Time
35
-
45
-
55
-
ns
tCH
Clock High Time
10
-
10
10
-
ns
-
15
ns
11
ns
15
ns
55
5
-
6
-
10
-
10
4
4
-
5
tH
WE, CS,
Set Up Time
Address, WE, CS, cr Hold Time
6
-
t OlZ (1)
Output Low Z Time
-
10
-
15
t OHZ (1)
Output High Z Time
-
8
11
Prop Delay to Valid Data Out
-
10
45
-
tCl
Clock Low Time
ts
Address,
. tpVD
cr
.
15
10
-
ns
5
-
ns
6
ns
WRITE CYCLE
tcp
Write Cycle Time
35
tCH
Clock High Time
10
tCl
Clock Low Time
23
ts
Data, Addr,
WE, es, cr Set Up Time
4
-
tH
Data, Addr,
WE, es, cr Hold Time
4
-
10
30
5
6
10
37
NOTE:
1. This parameter is guaranteed but not tested.
TIMING WAVEFORM OF READ CYCLE
(1)
tcp --------~
\ 4 - - - - tCH ---~----
tCl---~
CLK
ADDRESS,
es
. DATA VALID
ADDRESSZ
1 4 - - - - - - tcH
--r---~
tpvo
DATAoLrr
DATA FROM
ADDRESS X
tOLZ
DATA FROM
ADDRESSY
NOTE:
1.
The device must be selected by a CS level for the conditions above to take place.
S13-192
DATA FROM
ADDRESSZ
ns
ns
ns
ns
ns
IDT7MP6025 512K (64K x 8) SYNCHRONOUS
STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE
tcp
\ 0 4 - - - - tCH
---------;~
----;~----
tCl - - - - - . j
CLK
ADDRESS,
DATA IN
'CS" or
~(1)
NOTES:
1. Either CS or ~ can be used to trigger a write cycle, provided that the other signal is low at the same time.
2. When a write is terminated, either'O'S or ~ must become high at least one ts before the next rising edge of CLK.
TRUTH TABLE
MODE
~
~
CK
Standby
H
H
Read
L
L
Read
L
H
Write
L
H
t
t
t
t
150-cCREf\l
I5I-cCREf\l
WE
OUTPUT
POWER
H
H
H
X
HighZ
Standby
L
X
L
H
LowZ
Active
L
X
L
H
HighZ
Active
H
L
L
L
HighZ
Active
S13-193
A-cCREf\l
IDT7MP6025 512K (64K x 8) SYNCHRONOUS
STATIC RAM PLASTIC SIP MODULE
COMMERCIAL TEMPERATURE RANGE
:q
5V
AC TEST CONDITIONS
GNDto 3.0V
5ns
Input Pulse Levels
Input Rise/Fall Times
Input TIming Reference Levels
Output Reference Levels
Output Load
DATA OUT
1.5V
1.5V
See Figures 1 and 2
. 2550.
:q
5V
4800
DATA OUT
2550
. 3OpF*
Figure 1. Output Load
ORDERING INFORMATION
XXX)(
999
A
A
Device Type
Speed
Package
Process/
Temperature
~~
~------------~
L.---------------i
L . -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Blank
Commercial (O°C to
S
Plastic SIP
35
45
55
}
+ 70°C)
Speed In N"""""""d,
S
Standard Power
L...---------------------r
S13-194
7MP6025
5pF*
Figure 2. Output Load
(for t OLZ • tCHZ. tOHz.
tWHZ and tow)
* Including scope and jig.
IDT
4800
512K (64K x 8) Synchronous Ram Module
~
IntegJated Device1echnology.1nc.
256K (16K x 16-BIT) &
128K (8K x 16-BIT)
CMOS STATIC RAM
PLASTIC SIP MODULES
lOT 8MP656S
lOT 8MP628S
FEATURES:
DESCRIPTION:
• High-density 256K/128K CMOS static RAM modules
The IDT8MP656S/IDT8MP628S are 256K/128K-bit high-speed
CMOS static RAMs constructed on an epoxy laminate substrate
using four IDT7164 8K x 8 static RAMs (IDT8MP656S) or two
IDT7164 static RAMs (IDT8MP628S) in plastic surface mount
packages.
Functional equivalence to proposed monolithic static RAMs is
achieved by utilization of an on-board decoder that interprets the
higher order address A13 to select one of the two 8K x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (1/01-8) and upper byte (1/09-16) control,
respectively. (On the IDT8MP628S 8K x 16 option, A 13 needs to be
externally grounded for proper operation.) Extremely high speeds
are achievable by the use of IDT7164s, fabricated in IDT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides the fastest 256K/128K static RAMs available.
The IDT8MP656S/IDT8MP628S are available with maximum
operating power consumption of only 1.BW (IDT8MP656S 16Kx 16
option). The modules also offer a full standby mode of 330mW
(max.).
The IDT8MP656S/IDT8MP628S are offered in a 40-pin plastic
SIP. For the JEDEC standard 40-pin DIP, refer to the IDT8M656S1
IDT8M628S.
All inputs and outputs of the IDTBMP656S/IDT8MP628S are
TTL-compatible and operate from a single 5V supply. (NOTE: Both
GND pins need to be grounded for proper operation.) Fullyasynchronous circuitry is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of
use.
• 16K x 16 organization (IDT8MP656S) with 8K x 16 option
(IDT8MP628)
• Upper byte (1/09-16) and lower byte (1/01-8) separated control
- Flexibility in application
• Fast access times
- 40ns (max.)
• Low power consumption
- Active: less than 825mW (typ. in 16K x 16 organization)
- Standby: less than 20mW (typ.)
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR-4) substrate
• Offered in an SIP (single in-line) package for maximum
space-savings
• Utilizes IDT7164s-high-performance 64K static RAMs
produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
FUNCTIONAL BLOCK DIAGRAM
A0-12
1/0 _
18
IDT7164
1/09-16
IDT7164
8Kx8
8Kx8
CMOS
STATIC
RAM
WE
-
OE
I
CS
I
1/2 FCT139
DECODER
L
IDT7164
8Kx8
(
CMOS
STATIC
RAM
-
IDT7164
8Kx8
CMOS
STATIC
RAM
CMOS
STATIC
RAM
<;>
;>
\
~
Y
Y
l.....
1/2 FCT139
DECODER
L
~
Y
CEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 1989
© 1989 Integrated Device Technology. Inc.
DSC-7016/1
S13-195
IDTSMP656S/IDTSMP62SS CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16Kx 16-BIT) & 12SK (SKx 16-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN NAMES
PIN CONFIGURATION
123456 7 8 910111213141516171819202122232425262728293031323334353637383940
A5
As
A3
A.;
Al
A2
[B Vcc 1/01 1/03 1/05 1/07 OS
Ao WE GNoI 1) I/,,:!
1/04
1/06 1/08
1/09
rn::
1/011 1/'131/015 OND UB
As AlO A12 NC
1/010 1/012 1/0141/016 Vec Ar
A9
A11 A13
NOTE:
1. For module dimensions, please refer to module drawing M 17 in the packaging section.
SYMBOL
VTERM
RATING
Terminal Voltage with Respect
toGND
Addresses
1/01-16
Data Input/Output
CS
Chip Select
Vee
Power
WE
Write Enable
OE
Output Enable
GND
Ground
UB
Upper Byte Control
LB
Lower Byte Control
NOTES:
1. Both Vee pins need to be connected to the 5V
supply and both GND pins need to be
grounded for proper operation.
2. On IDTSMP62SS, 12SK (SK x 1B-Bit) option,
A 13 (Pin 39) is required extemal grounding for
proper operation.
SIP
FRONT VIEW
ABSOLUTE MAXIMUM RATINGS
AO-13
RECOMMENDED DC OPERATING CONDITIONS
(1)
VALUE
UNIT
-0.5 to +7.0
V
TA
Operating Temperature
Oto +70
°C
TBIAS
Temperature Under Bias
-10to +S5
°C
TSTG
Storage Temperature
lOUT
DC Output Current
-55 to +125
°C
50
mA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
UNIT
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
O.S
V
NOTE.
1. VIL (min.) = -3.0V for pulse width less than 20ns.,
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Vee
5.0V ±10%
DC ELECTRICAL CHARACTERISTICS
Vec = 5.0V ± 10%, Vee (Min.) = 4.5V. Vcc (Max.) = 5.5V, VLC = 0.2V, VHC = Vee = - 0.2V
SYMBOL
PARAMETER
TEST CONDITIONS
IIu l
Input Leakage Current
Vee = Max.; \'IN
IILol
Output Leakage Current
Vee = Max.
CS= \'IH' VOUT
CS, UB & LB
= GND to Vec
= GND to Vec
= \'IL
Vee = Max., Output Open
f = fMAX
IDTSMP656S
MIN. TYP. MAX.
IDTSMP62SS
MIN.' TYP. MAX.
-
-
15
-
-
15
-
-
-
165
330
-
UNIT
15
J.LA
15
J.LA
150
300
mA
170
mA
rnA
leex16
Operating Current In X16 Mode
leexa
Operating Current In XS Mode
CS = \'IL, UB or LB = \'IL
Vee = Max., Output Open
f = fMAX
-
100
200
-
SO
ISB&
ISBl
Standby Power SupplY.Current
CS ~ \'IH or _
UB ~ \'IH and LB ~ "'H
Vee = Max.
.
Output Open
-
4
60
-
2
30
VOL
Output Low Voltage
10L
-
0.4
V
VOH
Output High Voltage
10H = -4mA, Vee = Min.
-
-
V
= SmA, Vee = Min.
S13-196
2.4
-
0.4
-
-
2.4
IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16Kx 16-BIT) & 128K(8Kx 16-BIT)
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
~
~
5V48on
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DATA OUT
255!1
5V48on
DATA OUT
30pF
255!1
Figure 1. Output Load
5pF*
Figure 2. Output Load
(for tCU1 ,2' tou. t CHZ1 ,2' t OHZ '
tOW.tWHZ)
*Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETERS
(Vcc= 5V ±10%, TA = O°C to +70°C)
I DT8M P656S40
IDT8MP628S40
MIN.
MAX.
IDT8MP656S50
I DT8M P628S50
MIN.
MAX.
IDT8MP656S70
IDT8MP628S70
MIN.
MAX.
IDT8MP656S85
IDT8MP628S85
MIN.
MAX.
UNIT
READ CYCLE
t AC
Read Cycle Time
40
-
50
-
70
-
85
-
ns
tAA
Address Access Time
40
ns
50
70
-
85
40
-
70
Chip Select Access Time
-
50
tACS
-
85
ns
t cLZ1 .2 (1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
ns
tOE
(l)
t
oLZ
t
(l)
CHZ
t oHZ (l)
Output Enable to Output Valid
-
25
-
30
-
40
-
50
ns
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
ns
Chip Select to Output in High Z
-
15
20
ns
15
30
-
35
-
-
30
Output Disable to Output in High Z
-
35
ns
t
Output Hold from Address Change
5
-
5
5
-
5
Chip Select to Power Up Time
0
-
0
0
-
0
-
ns
t pu (l)
-
t po (l)
Chip Deselect to Power Down Time
-
40
-
50
-
70
-
85
ns
50
70
-
85
ns
45
-
20
ns
WRITE CYCLE
twc
Write Cycle Time
40
tcw
Chip Selection to End of Write
5
tAW
Address Valid to End of Write
35
-
t AS
Address Set-up Time
5
-
5
-
10
twp
Write Pulse Width
30
-
40
-
55
Write Recovery Time
5
-
5
-
5
-
10
-
Write Enable to Output in High Z
-
15
-
20
-
25
-
30
ns
tow
Data to Write Time Overlap
15
20
-
30
-
35
-
ns
tOH
Data Hold from Write Time
5
-
5
5
-
5
t oW (l)
Output Active from End of Write
5
-
5
-
5
-
5
-
ns
tWA
t
WHZ
(l)
NOTE:
1. This parameter guaranteed but not tested.
S13-197
45
65
65
75
75
10
65
ns
ns
ns
ns
ns
ns
IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 128K (SK x 16-BIT)
TIMING WAVEFORM OF READ CYCLE NO.
COMMERCIAL TEMPERATURE RANGE
1(1)
~-----------------tRC--------------~~
ADDRESS
US. LB &Cs
1_----------- t
ACS
-------+---..-j
1..__- - - - - - - tcLZ (5) _ _ _ _~
TIMING WAVEFORM OF READ CYCLE NO.
2(1,2,4)
ADDRESS
DATAoUT
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO.
DATA VALID
3(1,3,4)
Us. LB &Cs
DATAoUT
NOTES:
1.
2.
3.
4.
5.
WE is High for Read Cycle.
Device is continuously selected. CS = "'IL and DB. La = V1L for 16 output active.
Address valid prior to or coincident with CS transition low.
OE = V1L
Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
S13-198
IDTSMP656S/IDTSMP62SS CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16Kx 16-811) & 12SK (SKx 16-811)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS
~
----./
)K:
K
/'
tAW
~~
/V'
~tAS-
t
(7)
tWR
WP
f-
~,
..... :0-...
__ t
(6)
tOHZ
-tOW-l.
(4)
DATA OUT
(6)_
OHZ
-t
(6)WHZ
~«(4»;:_
J'
tow_
tOH
----------~E---->~~-----TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)
twc
ADDRESS
~(
)(
tAW
)~
'~
I - - - tAS
tWR
tcw
tow
1/
I'
tOH
,
/1
NOTES:
1.
or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low ~.
3. tWR is measured from the earlier of CS or
going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the
low transition. the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If
"Ol: is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp .
wr=.
wr=.
wr=.
S13-199
IDTSMP656S/IDTSMP62SS CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA= +25°C
TRUTH TABLE
MODE
CS UB LB
OE WE
OUTPUT
POWER
Standby
H
X
X
X
X
HighZ
Standby
Standby
L
H
H
X
X
HighZ
Standby
Read
L
L
L
L
H
DOUTl-16
Active
Lower Byte Read
L
H
L
L
H
DOUT 1-8
Active (X8)
Upper Byte Read
L
L
H
L
H
DoUT9_16
Active (X8)
Read
L
L
L
H
H
HighZ
Active
Lower Byte Read
L
H
L
H
H
HighZ
Active (X8)
Upper Byte Read
L
L
H
H
H
HighZ
Active (X8)
Write
L
L
L
X
L
DINl_16
Active
Lower Byte Write
L
H
L
X
L
DINl_8
Active (X8)
Upper Byte Write
L
L
H
X
L
DIN9-16
Active (X8)
PARAMETER(l)
SYMBOL
CIN
Input Capacitance
f = 10MHz)
CONDITIONS
VIN = OV
COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.
TYP.
UNIT
35
pF
40
pF
Address Access Time vs.
Capacitive Load
1.2
I
(TA= +25°C)
"0
~
1.1
~'-
o
Z
V~
1-=
V
o
~
./
50
Capacitive Load (pF)
ORDERING INFORMATION
IDT
XXXX
A
Device Type Power
999
Speed
A
Package
A
Process/
Temperature
RI__1
BLANK
~--------------~S
~
______________________
Commercial (O°C to
Plastic SIP
40
} Spa'" In Nano'econd,
85
L...---------------IS
L...-___________________-I
g~~~~~
Standard Power
16Kx 16-Bit
8K x 16-Bit
S13-200
+ 70°C)
~50
70
./
100
Application and Technical Notes
- - - . _ - - - _.... __.. _-_._._------_._._--
---------_.. _._----_ ...._--
....._..
_
..
_-" .. __ ._-".---------
.---.---.....-.-.. - ..-.---------. - - - - - - - - - - - - - - - - - - - - - - -
TABLE OF CONTENTS
CONTENTS
Application and Technical Notes
Technical Notes
Build a 20 MIP Data Processing Unit ............................................. .
TN-02
Using the IDT49C402A ALU ....•.................................................
TN-03
Using High-Speed 8K x 8 RAMs ................................................. .
TN-04
FCT-Fast, CMOS TTL-Compatible Logie .......................................... .
TN-05
Designing with FIFOs .......................................................... .
TN-06
Fast RAMs Give Lowest Power .................................................. .
TN-07
Operating FIFOs on Full and Empty Boundary Conditions .......................... .
TN-08
Cascading FIFOs or FIFO Modules .............................................. .
TN-09
Dual-Port RAM Address Arbitration Metastability Testing .........................•..
TN-10
TN-11
Cache Timing for the 68020 .................................................... .
Using lOT's Video DACs in 5V Only Systems ...................................... .
TN-12
Cache Timing for the 80386 .................................................... .
TN-13
TN-14
Expand Your IDT49C403 ........................................................ .
Programmable Length Shift Registers Using RAMs and Counters ....................... .
TN-16
Using the IDT7MB6049 Cache Module ............................................. .
TN-18
Application Notes
AN-01
Understanding the 1OT7201/7202 FIFO. ... . .. . . . . .... . ...... .. .. . . . .. .. . . . .. . .. . ..
AN-02
Dual-Port RAMs Simplify Communications In Computer Systems (Rev. 1) . '" ..........
AN-03
Trust Your Data with a High-Speed CMOS 16-, 32-, or 64-Blt EDC ........ '" . .. . . . ....
AN-04
High-Speed CMOS TTL-Compatible Number-Crunching Elements for Flxed- and
Floating-Point Arithmetic ....................................................
AN-05
Separate I/O RAMs Increase Speed and Reduce Part Count ..... " . . . .. .. . . . . . . . . ...
AN-06
16-Blt CMOS Slices - New Building Blocks Maintain Microcode Compatibility Yet
Increase Performance ......................................................
AN-07
Cache Tag RAM Chips Simplify Cache Memory Design..............................
AN-08
CMOS Breathes New Ufe Into Bit-Slice............................................
AN-09
Dual-Port RAMs Yield Bit-Slice Designs Without Microcode ..........................
AN-10
Low-Power and Battery Back-Up Operation of CMOS Static RAMs. . . . . . . . . . . . . . . . . . ..
AN-11
A Powerful New Architecture for 32-Blt Bit-Slice Microprocessor .....................
AN-12
Using the IDT721264/65 Floating-Point Chip Set. . . . . .. . ...... .. .. .. . . . .. . . . . . . .. . ..
AN-13
The IDT49C04 32-Blt Microprogram Microprocessor................................
AN-14
Dual-Port RAMs with Semaphore Arbitration ........... " ...................... " ..
AN-15
Using the 1OT721 03/04 Serial-Parallel FIFO ........................................
AN-16
SPC™ Provides Board and System Level Testing Through a Serial Scan Technique. . ...
AN-17
FIR Filter Implementation Using FIFOs and MACs ..................................
AN-18
High-Performance Controllers Need Microprogramming. ...... .. .. . . . ... . .. .. . . . . . ..
AN-19
RISC and the Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-20
Static RAM Timing..............................................................
AN-22
Performance Advantages with IDT's Flagged FIFOs ...................................
AN-23
High-Performance Fixed-Point Fast Fourier Transform Processor. . . . . . . . . . . • . . . . . . . . . . . ..
AN-24
Designing with the IDT49C460 and IDT39C60 Error Detection and Correction Units. . . . . . . ..
AN-25
The Key Advantages of Multi-Port Static RAMs .......................................
AN-26
Interrupt Latency and Handling in the IDT79R3000 ....................................
AN-27
Cache Design Considerations Using the IDT79R3000 ... . . .. . . .. . .. . . ... . ... . . . . . . . . . ..
AN-28
USing the IDT79R3000 in a Multiprocessor Organization. . .. . . . . . ... . . .. . . .. . . . . . . . . . . ..
AN-30
The Complete High Performance Cache System for the 80386 Microprocessor. " . .. . . . . ...
PAGE
14-200
14-203
14-207
14-209
14-251
14-253
14-254
14-257
14-260
14-264
14-266
14-268
S14-1
S14-4
S14-6
14-1
14-9
14-22
14-30
14-36
14-41
14-47
14-56
14-68
14-74
14-86
14-95
14-111
14-139
14-146
14-154
14-193
14-197
S14-9
S14-12
S14-26
S14-31
S14-49
S14-63
S14-67
S14-72
S14-78
S14-83
- - - - - - - - - - - - - - - - - - - - - - - - - " .•__.__..,--, ..• ,.
t;)
Integrated Devk:eTechnology. Inc.
"-,,,
.•_------
TECHNICAL
NOTE
TN-14
EXPAND YOUR
IDT49C403
By Michael J. Miller
INTRODUCTION
One of the key features of the IDT49C403 that distinguishes it
from other registered ALUs, such as the IDT49C402, is its 3-bus
architecture which allows for flexibility expanding its function. This
technote shows how the ALU can be expanded in an example
employing a very high speed fixed point multiplier. The technote
goes on to further demonstrate the flexibility ofthe IDT49C403 in an
example expanding the register file using a 2K by 16 Dual Port
RAM.
EXPANDING THE ALU
The IDT49C403 (Figure 1) is comprised of a 3-Port register file
tightly coupled with an ALU. There are 3 data buses which go on
and off this device - DA, DB, and Y. These are 16 bit buses and are
bidirectional, each with its own output enable control, OEA, OEB,
and OEY respectively. The onboard 64 location by 16 register file
is capable of outputting two 16-bit words simultaneously, the
contents of which are selected by the address buses A and B. Data
is written back into the register file via the Y bus to the location
identified by the B address bus. The Y bus is also connected to the
output of the ALU.
DA
DB
The data from the latches travels through output buffers and
onto the DA and DB buses as well as into the ALU. When OEA or
OEB are LOW, data is supplied from the register file to the DA or
DB bus and to the ALU. When either of these control lines are HIGH
the respective data bus becomes an input and data can be fed from
an external source into the ALU. The Y bus is the output bus of the
ALU. When OEY is low the data present on the Y bus comes from
the ALU. When OEY is high data can be brought onto the chip
through the Y bus and written into the RAM.
The ID17217 (Figure 2) is a fixed point multiplier capable of
providing a 16 x 16-bit multiply In 20ns. It too is organized with
3 data buses going on and off the chip. The X and Y buses are the
input into the multiplier chip. Data coming in on these buses is
captured in the X register and Y r~er on every riSing edge of CPo
The two enable signals ENX and ENY are used as clock enables for
the X and Y register respectively and control which given cycle new
data will be loaded. On every cycle the output of the X and Y
registers are multiplied together, the result being a 32-bit binary
number which is clocked into the MSP and LSP register on the
rising edge of CPo Again, the enable signal ENP is used to control
which cycle will load these two registers. Two paths are provided
for bringing data off the chip. The LS P register contents m~
read back out onto the Y bus through a buffer controlled by OEL.
When OEL is low the Y pins become output pins. The other path is
through a multiplexer which selects the contents of the MSP or LSP
registers. The multiplexer is controlled by MSPSEL. OEP is the
control line which controls when the P Port will be driven with the
data selected by the multiplexer at the output of MSP and LSP.
B
y
X
M
.----...---'---- 1m
r------r------~~
CP
" ) - - - - + - - <:5E"a"
y
Figure 1. The IDT49C403 16·Blt Registered ALU
The flow of data in and out of the register file is controlled
primarily by the system clock (CP). The output ofthe register file is
put into two latches which hold the data constant through the write
cycle. When the clock CP is HIGH, the register file is in the Read
mode and the latches are transparent. When the clock is LOW the
register file enters into a Write mode and the latches are closed,
thus holding the data previously fetched during the Read portion of
the cycle. Data is written when CP is LOW, the instruction enable
lEN is LOW and the write enable WE is LOW.
©
1988 Integrated Device Technology, Inc.
p
Figure 2. Block Diagram of IDT121716 x 16 Multiplier
The functionality of the IDT49C403 can be expanded by
connecting an ID17217 in parallel with the ALU on the IDT49C403.
This is accomplished by connecting the X bus to the DA bus and
the Y bus to the DB bus, thus providing a path to take data out ofthe
514-1
Printed In the U.S.A.
01/89
EXPAND YOUR IDT49C403
TECHNICAL NOTE TN·14
register file on the IDT49C403 and place it into the X and Y registers
on the IDT7217 (Figure 3a). On the following clock edge the results
are put into the MSP and LSP registers of the IDT7217 at which
point the data can be read out on the P bus which is connected to
the Y bus. The Y bus then is used to write data back into the register
file as shown In Figure 3b. Therefore operands go out on the DA
and DB bus and results come back on the Y bus.
IDT49C403
The FT control input on the IDT7217 can be used to make the
MSP and LSP registers transparent. In this way the multiplier would
have only one pipeline delay thus allowing the actual multiply and
register file update to happen in one cycle.
IDT49C403
IDT7217
IDT7217
Figure 3b.
Figure 3a.
Figure 3. Data Flow Between the IDT49C403 and IDT7217
An alternate path for bringing results into the IDT49C403 is
using the Y bus of the IDT7217 as shown In Figure 4. By low~
OEl the Y bus becomes an output. Correspondingly the OEB
signal on the IDT49C403mustbe brought HIGH. The data then can
IDT49C403
be brought back on the DB bus, passed through the ALU, possibly
added with an accumulation value In the register file, and written
back into the accumulation register In the register file.
IDT7217
Figure 4. Alternate Data Flow From the IDT7217 to the IDT49C403
EXPANDING THE REGISTER FILE
half of the cycle (CP HIGH) two operands may be read out of the
Dual Port RAM and passed through transparent latches. When the
clock goes LOW, the latches are then closed providing continuous
data to the ALU. The result may be brought out on the Y bus which
is then enabled back onto the B port data bus. At this point the Dual
Port RAM could be put into the write mode on the B side, thus
turning the B data bus around and writing the results back in. Also,
the A side at this point could be turned around and new data could
be brought in from the outside host system and written into the Dual
Port RAM. The advantage ofthis configuration is that two operands
can be fetched simultaneously from the Dual Port RAM at the
beginning of the cycle and on the last part of the cycle two values
can be written back into the Dual Port RAM, one being the result
from the ALU and one being from the host system.
Three buses on the IDT49C403 also make it convenient for
expanding the register file. In the previous discussion we explored
how data has been taken out of the register file via the DA and DB
buses. In this section we explore how data can be brought from
external memory on the DA and DB buses, pass through the ALU
and the result brought out on the Y bus is written back into the
external memory or register file.
The IDT7133, (2K x 16 Dual Port RAM) isan ideal selection with
respect to register file expansion. It is comprised of two address
buses and two data buses which can be operated at the same time
in both the read or the write modes. In the first example shown in
Figure 5, the Dual Port RAM is configured in such a way that in one
S14-2
TECHNICAL NOTE TN-14
EXPAND YOUR IDT49C403
DUAL
A
A
SOURCE
ADDR
PORT RAM
2Kx 16
DUAL
B
B
ADDR
SOURCE AND
DESTINATION
IDT7133
A DATA
PORT RAM
2K x 16
B
ADDR
B
DESTINATION
IDT7133
BDATA
IDT49C403
HOST
SYSTEM
INTERFACE
Figure 5. Expanding the IDT49C403 Register File with Dual Port RAM
In the second design example shown in Figure 5, the Dual Port
RAM provides one operand while the host system might be .
providing the other operand. The host system may be buffered
through some memory device like another Dual Port RAM or a
FIFO. The result of the IDT49C403 could be written back into the
Dual Port RAM on the B port. Thus the A port would be dedicated to
only reading operands and the B port would be dedicated only to
writing the results. This architecture can run much faster because
the data buses are not constantly being switched from input to
output.
CONCLUSION
Because of the 3-bus architecture, the IDT49C403 allows for
easy expansion of the chip register file as well as expanding the
ALU. These three buses not only add flexibility, but they also
increase the bandwidth going on and off the ALU. While the
IDT49C402 may operate at a slightly faster cycle time, the
IDT49C403 has fifty percent more bandwidth capability in its third
data bus, thus making it an ideal choice in certain applications.
S14-3
- - - - - - - - _..
_. __..... _-----.............. -
PROGRAMMABLE LENGTH
~
Integrated Deviceh:hnology. Inc.
SHIFT REGISTERS USING
RAMs AND COUNTERS
TECHNICAL
NOTE
, TN-16
By David C. Wyland
Programmable length shift registers can be made using
counters and RAMs. These shift registers can be quite long and
reprogrammed during use if desired.
A block diagram of a programmable length shift register made
from a RAM and counter is shown in Figure 1. This shift register can
be from one to 16,384 words long by four bits per word. It can shift
at clock cycle times down to 38ns for 15ns RAMs and FCT161A
counters.
The RAM and counter configuration provide a circular buffer.
The counter size (in total counts) sets the size of the circular buffer.
The counter points to the next location for storing data in this buffer.
SHIFT REGISTER LENGTH
VALUE = LENGTH-1
DATA IN
Before storing new data at this location, the old data is read out and
latched. As the counter walks around the ring, the old data is
continuously read out and new data written in.
The programmable length is provided by the counter. In the
case shown, the counter counts from zero and increments up to the
compare value which is the shift register effective length minus 1.
The 521 comparator output is active at this maximum count and
causes the counter to be parallel loaded with zero, effectively
resetting the counter.
ZERO
(RESET VALUE)
ADDRESS
DATA OUT
. 16Kx4
SRAM
4x6167SA15
CLOCK --------~----------------------------~
Figure 1. Variable Length RAM Based Shift Register Block Diagram
Timing for this shift register is shown in Figure 2. Data is read out
from the RAM during the first half of the clock cycle and latched in
the 373 during the second half. Data is written into the RAM in the
© 1989 Integrated Device TechnolOgy, Inc.
second half, and the counter is incremented at the end of the cycle.
Clock cycle time calculations are shown in Table 1.
S14-4
Prfnted In the U.S.A.
01/19
PROGRAMMABLE LENGTH SHIFT REGISTERS
USING RAMs AND COUNTERS
CLOCK
COUNTER
O~
RAM READ DATA
J
TECHNICAL NOTE TN·16
WRITE
READ
r
~--41
x=
==x .
~:.:i!{}::.·?:.~
GOOD
~··I.}.·))::::··:····
:·· ·:::··::::.::·.:.·:• :.::::.»>H::})n·K
I
I
WRITE DATA IN'
X=
I
I
==X..:!:U:?i/· ·:}··(·>:·:.:::::·::::~",_____G_O_O_D_ _ _ _.....
Figure 2. Variable Length RAM Based Shift Register Timing Diagram
Table 1. Clock Cycle Time Calculations
Counter settling time: FCT161 A
RAM access time: IDT6167SA15
Latch setup time:· FCT373A
Clock high time, minimum
7.2ns
15,0
~
24,2ns
Clock low time = RAM write time: IDT6167SA15
13.0
Total
37.2ns
S14-5
~
Integrated Device1echnology.1nc.
TECHNICAL
NOTE
TN-18
USING THE
IDT7MB6049
CACHE MODULE
By Kelly Maas
The IDT7MB6049 is a complete cache module for the R3000
RISC processor and is designed for both single- and
multi-processor systems. It has two banks of SRAM, each
configured as 16K x 60, and each with address latches. One bank
is used to cache data, and the other is used to cache instructions.
They share a data bus, allowing one bank to be accessed at a time.
Use in multi-processor systems is facilitated by a second
address bus and an additional set of latches for that bus. This bus is
used in multi-processor applications to latch an address from a
source other than the R3000. This allows the system to invalidate
entries in the data cache in conjunction with the R3000. This is
done in order to maintain cache coherency. The second address
latch for the instruction cache is included in the module for
symmetry, although normally no invalidations are done to the
instruction cache. Only data cache invalidation is described
below. Instruction cache invalidation would require cache
swapping.
When the system wants to invalidate an entry in the data cache,
itforces the R3000 into an MP Stall by asserting CpCond(3). During
the one clock cycle that it takes for the processor to enter the MP
Stall, it is the responsibility ofthe system to disable the output of the
latch which supplies the processor's address to the data cache,
and enable the output of the latch which supplies the invalidate
address. The module pins P10E*(1) and P20E*(1) are used for
this purpose. It is important that they should never be activated
simultaneously since the outputs of the latches are tied together.
The same applies to P10E*(2) and P20E*(2) for the instruction
cache. Both address latches of the data cache are normally
clocked by the same OClk signal from the R3000 through the
P1LE(1) and P2LE(1) pins of the 7MB6049.
Once the processor is in MP Stall, it strobes ORd* while
CpCond(2) is unasserted, allowing the system to read the contents
of the cache. The actual invalidation of data cache entries begins
when the system asserts CpCond(2) and provides the appropriate
invalidate address. CpCond(2) causes the R3000 to output an
invalid bit and strobe OWr*. Multiple invalidations are performed
by keeping CpCond(2) and (3) asserted, and changing the
invalidate address. Note that the invalidate address timing must be
consistent the processor timing. One suggestion is that the
invalidate address input of the module be driven by a register that is
clocked by SysOut.
The 10T7MB6049 has two chip select (CS*) signals. Both of
these should be grounded if the cache is not depth expanded. The
four output enable (OE*) and four write enable (WE*) signals are
© 1989 Int.grated Device Technology, Inc.
S14-6
split evenly between the data and instruction caches: (1-2) control
the data cache, and (3-4) control the instruction cache.
OE*(1-2) of the 7MB6049 connect to ORd1* and ORd2* on the
R3000. ORd1 * and ORd2* are identical, and the load should be
distributed evenly between them. Likewise, OE*(3-4) connect to
IRd1* and IRd2*. WE*(1-2) connect to OWr1* and OWr2*, and
WE*(3-4) connect to OWr1* and OWr2*.
The convention of the pin naming of the 7MB6049 is that P1
refers to the address from the R3000, and that P2 refers to the
(invalidate) address from the system. Likewise, (1) refers to the
data cache and (2) refers to the instruction cache. As shown in
Figure 2, P1 LE* (1) and P2LE* (1) are typically connected together
to OClk since they latch addresses into the two data cache latches.
P1 LE* (2) and P2LE* (2) likewise connect together to IClk, although
P2LE*(2) is not used if instruction cache invalidation is not
performed.
Similarly, P10E*(1) and P10E*(2) are typically connected
together so that the outputs of the two R3000 address latches are
enabled and d)sabled together, while P20E* (1) and P20E* (2) can
together control the output of the invalidate address latches.
P20E*(2) may be pulled continuously high if the instruction
invalidate address latch is unused.
The 60 data I/O pins of the module are labeled 0(0) to 0(59).
Although the ordering of the data and address pins of a RAM is
normally arbitrary and can be ignored, that is not the case with the
7MB6049. Because of steps taken to reduce the chip count and
power consumption of the module, Tag(12)-Tag(15) of the R3000
must connect to 0(36)-0(39) on the 7MB6049, and
AdrLo(12)-AdrLo(15) of the R3000 must connect to
P1A(10)-P1A(13) on the 7MB6049. The order in which the other I/O
pins are connected is not critical. Table 1 shows recommended I/O
pin connections between the R3000 and the 7MB6049.
R3000 Signals
IDT7MB6049 Signals
data
Oata(O) - Oata(31)
0(0) - 0(31)
data parity
OataP(O) - OataP(3)
0(32) - 0(35)
tag
Tag(12) - Tag(31)
0(36) - 0(55)
tag parity
TagP(O) - TagP(2)
0(56) - 0(58)
tag valid
TagV
0(59)
Table 1. Connection of Data and Tag Buses
Printed In the U.S.A.
01/1'
TECHNICAL NOTE TN-18
USING THE IDT7MB6049 CACHE MODULE
TO SYSTEM
------------~~~-----------,-INVALID
PROCESSOR
~
INVALIDATE
ADDRESS
ADDRESS
ENABLE
ADDRESS
ENABLE
R3000
DClK
IClK
AdrLo (2-15)
~!£!L@W~~~~lnl:.i ~:::*::::i*m::;:;:i::::i:i::W~:::i:i:*:::i:::~::::~::~:i::;:;m::ii:::~~:::::,***:mi:2~
...
12 MHZ
48 MBYTES/SEC
......
"
II
MAIN MEMORY
~:;:;~:;:;::w.~m~:~}:~:;::;;:m~m;';::;~~
LOWEST BANDWIDTH
(WHERE THE PROGRAM RESIDES)
Figure 2. The Memory Hierarchy
The first level of the hierarchy is the register file that keeps the
ALU fed with. data. The management of the register file is
performed at compile time. Without optimizing compilers, the total
power of RISC cannot be realized.
The second level of the hierarchy is the instruction and data
caches. Because RISC CPUs require a new instruction every clock
cycle, the access time of the cache SRAM is the pacing delay in a
RISC CPU's cycle time. To further increase the bandwidth into the
RISC CPU, a separate cache for data is used.
The third level hierarchy is the main memory consisting of
cache hard disks. Today's RISC CPUs employ on-chip a memory
management unit (MMU) to manage the swapping of program
segments between main memory and the disk. The Translation
Lookaside Buffer (TLB) is a key element in the MMU that translates
the logical addresses to the physical address of the programs
stored in main memory. The TLB is a look-up table of addresses.
Since circuitry to implement TLBs is costly in silicon area, TLBs are
kept small and function as another cache for a large master look-up
table kept in main memory.
S14-10
----------
..._..•....... _.....
APPLICATION NOTE AN·19
RISC AND THE MEMORY HIERARCHY
HIERARCHY
MANAGEMENT CONTROL
MANAGEMENT
TABLES
0, 0--------
OPTIMIZING COMPILER
REGISTER ''---_ _.....1
CACHE
~~H~- -~~;~~;.~.I~~~~:;~~
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9 INSTRUCTIONS, ONE LOAD. MORE
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Figure 3. Managing the Memory Hierarchy
More than a Data Path
Therefore, RISC CPUs need not only a datapath, but also a
memory hierarchy that must be managed by the CPU and software
in order to operate efficiently. All levels ofthe hierarchy are used to
feed the insatiable appetite of the instruction and data path of
S14-11
teday's RISC CPUs. Since the reduced instruction set is only one
aspect of the RISC CPU technique, perhaps a more appropriate
name would be Bandwidth Increased Streamlined Computer
(BISC). This new term could be used at the 'risc'of adding more
letters to todays' already full bowl of alphabet soupl
4LJ
STATIC RAM TIMING
Integrated DevIce1echnoIc:::>sy. Inc.
APPLICATION
NOTE
AN-20
By Mammad A. Safal
The timing parameters are divided Into two groups: those that
are involved with common 1/0 parts and those that are involved
with the separate 1/0 parts.
In order to show the different aspects of the timing problem in
static RAMs, two lOT 16K static RAMs will be used as examples.
INTRODUCTION
This application note Is about timing parameters Involved in the
use of static RAMs. The application note describes these
parameters, their Individual meanings and their uses.
Optimum performance can be accomplished by understanding
the timing of the memory element. A system which is designed
using this knowledge will be fast and will not consume a lot of
power.
The timing parameters are actually the reflection of the internals
of the static RAMs. These Internals will be discussed and the
relationship between the timing at the cell level and the timing at
the component level will become ciear.
The RAM Cell
In order to better represent the different timing parameters
involved in read or write operations in static RAMs, we will start with
the basic memory cell. The basic memory cell of Integrated Device
Technology Is the four transistor cell (4T Cell shown in Figure 1).
SUPPLY VOLTAGE
PULL-UP RESISTOR
PULL-UP RESISTOR
ROW SELECT
BIT-LINE
Figure 1. Four Transistor Cell
In the four transistor cell of Figure 1, transistors 02 and 03
constitute a latch. When 02 is on, it keeps 03 off, and when 03 is
on, it keeps 02 off. A zero (0) bit is accomplished by 02 on and 03
. off. A one (1) bit is accomplished by 03 on and 02 off.
READING FROM THE CELL
To read the contents of the cell, Row Select becomes active.
Transistors 01 and 04 tum on. The state of the drains of transistors
02 and 03 becomes available on Bit-Line and Bit-Une. One of the
two Bit-Lines will be pulled down through 0102 or 0304. If
Bit-Line is high and Bit-Line Is low, the contents of the latch Is a "1-.
WRITING INTO THE CELL
To write a one (1) into the cell, Row Select becomes active.
Transistors 01 and 04 tum on. Bit-Line is forced high and Bit-Line
is forced low. Transistor 02 will tum off and transistor 03 will tum
on. Therefore, the contents of the latch becomes a "1".
© 1881 Integrated DevIce Technology. Inc.
RAM
A RAM is a RAM cell together with some logic Interface for read
or write operations. Figure 2 shows a one-bit RAM with some logic
interface in order to operate it.
S14-12
PrInted In the U.S.A.
01/81
APPLICATION NOTE AN-2D
STATIC RAM TIMING
SUPPLY VOLTAGE
PULL-UP RESISTOR
PULL-UP RESISTOR
.......----,Q4
As shown in Figure 2, in order to write, the control logic has to
enable the differential write amplifier that is placed in the path of
DIN. When a data bit has to be written into the latch, DIN is put
through that differential amplifier which will charge up one of the bit
lines and will charge down the other. The Row Select line has
already selected the appropriate latch, and finally, the data is
written into the cell.
,.--
READING FROM THE ONE-BIT RAM
The reading operations of the one-bit RAM are performed in the
following order:
• Row Select becomes active
• 01 and 04 tum on
• Bit-Line will charge to the value of the drain of 02
• Bit-Line will charge to the value of the drain of 03
• Read amplifier will evaluate the two Bit-Lines and will output the
logic value corresponding to the content of the latch.
While reading from the latch, Row Select selects the appropriate
latch. The control logic will enable the appropriate sense amplifier.
The sense amplifier will sense the bit lines and output a value that
will represent the content of the latch in question.
In Figure 2, the read amplifier is a differential amplifier that
senses which bit line is being pulled low. Both bit lines start high
and are pulled low by 01 02 or by 0304. By senSing the movement
of the bit line being pulled low, the time spent to determine the
content of the latch is reduced.
ROW SELECT
~-----~
~-----~
BIT-LINE
WRITE AMPLIFIER
DOUT
A 2 X 2 RAM ARRAY
CS
WE
OE
Figure 2. One-Bit RAM
WRITING TO THE ONE-BIT RAM
The writing operations of the one-bit RAM are performed in the
following order:
• Force Bit-Line high and Bit-Line low (to write a "1")
• Row Select goes high to select the cell to be written
•
•
•
•
•
01 and 04 tum on
02's drain is pulled high towards the supply
03's drain is pulled down to ground level
02's gate will be low, therefore 02 is OFF
03's gate will be high, therefore 03 is ON
514-13
Before showing the general picture, let us examine the inner
connections of four cells arranged as a 2-word-by-2-bit RAM.
Figure 3 shows the configuration of this memory array. This array
could be extended in both directions.
AD selects the particular row that interest the user. If AD is low,
RSO becomes active, and if it is high, RS1 becomes active. A1
selects the particular column that interest the user. If A 1 is low, eso
becomes active, and if it is high, eS1 becomes active.
In the manner described above, if the user would like to access
the latch placed on the top left part of the Figure 3A, A 1AO = 00.
Latch (0,0) -- > A 1AO = 00
Latch (1,0) --> A1AO = 10
Latch (0,1) --> A1AO = 01
Latch (1,1) --> A1AO = 11
STATIC RAM TIMING
APPLICATION NOTE AN-20
Vee
RSO
Vee
AD
ROW
SELECT
RS1
CSO
A1
COLUMN
SELECT
CS1
WE
Figure 3. A 2 x 2 Array
514-14
APPLICATION NOTE AN-20
STATIC RAM TIMING
A REAL PART
Before going into detail about the different aspects and
trade-offs of the various approaches of reading or writing, let us
take a look at Figure 4 which represents an actual part. This part
has 16K of memory and is arranged in a 16K x 1-bit manner
(IDT6167). It is similar to the array shown in Figure 3 but has been
expanded from 2 x 2 to 128 x 128.
GND
128 x 128
MEMORY ARRAY
COLUMN I/O
DIN
----1-----1
DOUT
COLUMN SELECT
~-*"----I
Figure 4. Functional Block Diagram of IDT6167 16K x-Bit
The selection of a particular row is done using address lines
AO---A4, A12 and A13. The selection of a particular column is
done using address lines AS---A11. The chip select line (CS),
enables the row select logic and the write/read signal. Data In and
Data Out paths are controlled by CS and the WE signal. If CS and
WE are active, the path for Data In becomes valid. If CS is active
and WE high, the path for Data Out becomes active. If CS is not
active, both paths are turned off.
WRITING METHODS: WE vs. CS CONTROLLED
WRITE
There are also two different ways for executing a write, i.e.
the WE-controlled . or the CS-controlled write. For the
WE-controlled write, the basic steps that one should consider are:
• Bring the address bits to the address pins
• Wait for the address pins to settle
• Select the chip
• Strobe the Write Enable pin: This will tum on the write amplifier
switches
• Terminate the strobe
• Keep the data bits stable for a while
During a read operation, the WE signal is high, disabling the
write amplifiers and enabling the output drivers. In Figure 4, since
the part is a by one (x1) part, there is only one output driver and one
write amplifier.
Once the sense amplifier is active, the address lines (using the
row and column select logic) enable a particular memory cell. The
state of the cell is sensed by the sense amplifier (read amplifier)
which in tum will output the corresponding logic level.
The user has to wait a certain amount of time for the read
amplifier to sense the value of the latch. This amount of time will
correspond to the access time of the device.
Here are some steps representing a read operation:
• Select the device (CS low)
• Enable the read amplifier or sense amplifier (WE high): This will
actually tum on the driver at the output of the sense amplifier
(see Figure 2)
COMMON I/O AND SEPARATE 1/0
Chip Select controlled write uses a slightly different set of steps:
• Bring the Write Enable low (enabled)
• Bring the address bits to the address pins of the IC
• Wait for the address pins to settle
• Strobe the Chip Select: This will tum on the bit and row select
switches
• Terminate the strobe
READING FROM THE RAM ARRAY
• Wait for the access time
• Read the data bit out of the data bus
• Bring the data bits to the data pins
• Bring the data bits to the IC data pins
• Keep the data bits stable for a while
What we have discussed is called a Separate I/O part. Separate
I/O means that you have separate input and output paths. As far as
the user is concerned, it means that, at the device level, the part has
different pins for the Data In and Data Out bits.
A 2x 2 COMMON I/O RAM ARRAY
There are also other memory parts that are called Common I/O
RAMs. A common I/O part has only one path for the data bits and
S14-15
._--------_._
..
APPLICATION NOTE AN-20
STATIC RAM TIMING
this path is'bidirectional. At the cell level in a common I/O part, the
DIN line is connected directly to the DoUT line. Figure 5 illustrates
the idea of a common I/O part at the cell level. It represents a 2 x 2
common I/O array of RAM.
RSD
AD
ROW
SELECT
RS1
A1
COLUMN
SELECT
CSD
~--+-C-S-1---------------+--------~
DOUT
DATA
Figure 5. A 2 x 2 Common I/O ARRAY
If the user decides to execute a write on a common I/O part,
there will be one extra step to take compared to our previous set of
steps illustrated for a separate I/O part. This extra step is just
tuming off the output driver, enabling the Input differential amplifier
and finally executing a write Into the array.
S14-16
APPLICATION NOTE AN-20
STATIC RAM TIMING
A REAL COMMON I/O PART
Let us now take a look at another actual part from Integrated
Device Technology. Figure 6 shows the functional block diagram
of a 4K x 4-bit memory device, the IDT6168.
128 x 128
ROW
SELECT
MEMORY ARRAY
COLUMN I/O
COLUMN SELECT
INPUT
DATA
CONTROL
Figure 6. Functional Block Diagram of 4K x 4-Bit Common I/O Memory
In order to understand the different timing parameters involved
in the read/write operation of the memory elements in general, let
us examine Figure 6 in more detail.
WRITING METHODS: WE
WRITE
VS.
• Wait for the address pins to settle
• Keep the Write Enable pin low: This will keep the output drivers
off and allows the input differential amplifier to get enabled as
soon as the CS goes low
CS CONTROLLED
• Bring the data bits to the IC data pins
Writing is achieved using two different techniques. Similar to the
previous section, a write can be achieved by either strobing the
chip select or strobing the write pulse. Here is the sequence to
follow if the WE (Write Pulse) controlled write is used:
• Bring the address bits to the IC address pins
• Select the IC by enabling Chip Select
• Wait for the address pins to settle
• Start the Write Pulse: This will turn off the output drivers and
enable the input differential amplifier
• Bring the data bits to the IC data pins
• Turn off the write pulse
• Keep the data bits stable for a while after the Write pulse: This is
required hold time for the cells to settle
The other way of writing is the Chip Select controlled write. The
steps that follow are very similar to the steps taken for the separate
I/O part. Here is the sequence:
• Bring the address bits to the IC address pins
• Strobe the Chip Select: This will enable the input differential
amplifier for writing
• Bring the Chip signal high again: This will disable the input
differential amplifier
• Keep the data bus stable for a while after the Chip Select pulse
goes high: This is the required hold time for the cells to settle
READING FROM THE COMMON I/O ARRAY
Again, reading the common I/O part is not very different from
reading the separate I/O part. If the user decides to continuously
read an entire block sequentially, the Chip Select signal should be
kept low and the Write Enable signal high. In this way, the output
drivers are enabled and the concerned memory cells are selected.
The steps to follow are described below:
• Bring the address bits to the pins of the IC
m
• Select the IC by bringing the CS signal low
• Turn the outputs on by bringing the WE Signal high: This step
and the two above can be executed together
S14-17
.....
__._-_._------ - - - - - - - -
~
APPLICATION NOTE AN·20
STATIC RAM TIMING
• Wait for a while for:
The concemed cells to be selected
two different sorts of array. We have shown that the difference is not
a big one (Separate I/O vs. Common I/O) and that the parts are not
only similar in their base structure, but also similar in the way they
work.
Then the description of the necessary steps to take for a write or
a read operation was given. In order to finalize the idea about
memory parts, and before going into further detail about the timing
parameters and what they mean, Figure 7 shows a general block
diagram representing a memory part.
The output drivers to be enabled (tLZ)
The data bits to be valid (tACS)
• Read the Data Out of the IC after the above wait
Data will be available after TAA (address access time) from the
last time the address changed or after tAcs (chip select access
time) from the time CS became active, whichever is longer.
WHAT DID WE TALK ABOUT SO FAR?
We have talked about latches and how they work. We have
described the structure of an array and then shown that there are
BIT LINE PULLUPS
ADDRESS
R/W
cs
SENSE AMPLIFIERS AND WRITE
CIRCUITRY
CONTROL
DE"
DATA IN-DATA OUT
COMMON OR SEPARATE I/O
Figure 7. Block Diagram for a Static RAM Memory Device
TIMING
WRITING TO SEPARATE I/O SRAM
At this point let us divide the timing parameters into two different
categories: those involved with common I/O and those involved
with separate I/O. To have a better understanding of these
parameters, let us take a look at various timing diagrams taken
from actual devices that Integrated Device Technology produces.
To start, let us take a look at the 16K x 1-bit part (separate 110),
the IDT6167. As the reader remembers, there are two ways of
accomplishing a write. Figure 8 illustrates the Write Enabled
controlled write for the mentioned memory IC.
S14-18
APPLICATION NOTE AN-20
STATIC RAM TIMING
WRITE ENABLED CONTROLLED WRITE
~-----------------------------twe----------------------------~
ADDRESS
tew
-----------------*1 ,..,.._,...,,...,...,....,...7I-J,...,...,
------~---------.-p~ ~------------- twp -----------~~
-----------------------------~---~
~--------- tDW
-----------..t_--DATAIN VALID
I
\=-= twz~
DATAoUT
r-----------------
~ tow~
Jo-------------------------------iC-
DATA UNDEFINED
HIG. H IMPEDANCE.
(
\0._ _ _ _ __
Figure 8. Timing Diagram for WE Controlled Write, IDT6167
Figure 8 shows the timing for Write Enabled controlled write and
the steps described below relate to that Figure:
• Bring the address bits at the IC address pins. (At this point the
user should keep the address bits stable throughout the write
operation.) The Write Cycle time is twe during which the address
must remain constant.
• Select the chip. At this point the chip is selected and tew is the
chip select to end of write (WE signal) time. This is the minimum
amount of time that the IC has to remain in a selected mode.
• Wait a while for the address pins to settle. The address set-up
time is tAS. During that particular time the user is giving the
memory some time for the concerned cells to be selected with
the row and column select logic.
• Strobe the Write Enable pin. This will enable the write differential
amplifiers (since CS is active already). The write pulse width
is twP. This isthe minimum amount oftime necessary for the WE
signal to be active in order to give enough time for the cells to
change state.
• Bring the data bits to the IC data pins. The data bits should be
stable by the cells for at least tDW, which is the data valid to end
of write time. The set-up time is tDw for the latches of the IC.
• Terminate the strobe. At this point, the WE signal is deactivated
and the strobing is done.
• Keep the data bits stable for a while. This corresponds to the
hold time for the latches of the IC, tDH. By holding the data bits
stable during this time, the user is giving the cells a chance to
settle at the correct logic state while the write switches tum off.
• This is the end of the cycle. At this point, the user can make an
address transition for the next operation but rememb~ CS or
WE must be high during address transition. If the CS or the
WE signals are not held high during an address transition, the
address decoders can glitch when addresses change, and
therefore, cause random cells to be written:
Figure 9 shows the timing for chip select controlled write and the
steps described below relate to this Figure:
• Keep the Write Enable low (enabled). During a Chip Select
controlled write, the Write Enable signal is low during the the
Chip Select pulse. It should be active for at least the minimum.
The write pulse width is twP.
• Bring the Address bits at the IC address pins.The user must
keep the address bits stable throughout the write operation. The
Write Cycle time is twe during which the address must remain
constant.
• Wait for the address pins to settle. The address set-up time
is lAs. Duringthattime, the user is giving the memorytimeforthe
cells to be selected by the row and column select logic.
• Strobe the Chip Select. This will tum on the bit and row select
switches and will bring the cells to a situation where they are
ready to be written into. tew is the chip select to end of write time.
This is the minimum width of the CS strobe.
• Bring the data bits at the IC data pins. The Data bits should be
stable at the cells for at least tDw, which is the data valid to end of
write time. The set-up time tDW is for the latches of the IC.
• Terminate the strobe. At this point the CS signal is deactivated
and the strobing is done.
• Keep the data bits stable for a while. This corresponds to the
Hold time for the latches of the IC. tDH is the data hold time. By
holding the data bits stable during this time, the user is giving
the cells a chance to settle at the correct logic state while the
select lines turn off.
• This the end of the cycle. At this point the user can make an
address transition for the next operation but rememb~ CS or
WE must be high during address transition. If the CS or the
WE signals are not held high during an address transition, the
address decoders can glitch when addresses change and,
therefore, cause random cells to be written.
S14-19
APPLICATION NOTE AN-20
STATIC RAM TIMING
CHIP SELECT CONTROLLED WRITE
®
~-----------twc------------~
ADDRESS
---.+0_----
tcw
----*I
~--------tAw-------~~-
~---- twp-----~
14-+---- tOw _ _ _ _...._ - - . j
DATAIN VALID
I
to- twz~
DATAoUT
DATA UNDEFINED
- ' 1 J - - - - - - - - H..
IG....H--IM...P~E~D-A-NC~E.....--------
Figure 9. Timing Diagram for CE Controlled Write, IDT6167
TIMING FOR CONTINUOUS READ
signal is high and the CS signal is low, continuously. The timing
that will apply is shown in Figure 10.
Let us now take a look at the timing for a read cycle. Let us
assume that the user wants to constantly read the IC. The WE
TIMING WAVEFORM OF READ CYCLE NO.1
o
@
~------------------- t RC -------------------~
ADDRESS
I+-:::®::::---------
tAA
@
!04-=--- tCH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 10. Timing Waveform for Read Cycle No.1
During this read cycle, the Write Enable..LWE) is high (therefore
disabled) and the Chip Select line is low (CS, therefore enabled).
The output drivers are turned on while the chip is selected, putting
the IC in a constant read mode. The amount of time that the
previous data will still be valid after an address transition has
occurred is tOH. Finally, after TAA has passed since the address
transition, the valid data bits are available. Since TAA-toH is
changing, data from the IC is not valid during this time.
Let us go through Figure 10 step by step:
• Bring the address bits to the IC address pins. The read cycle
time parameter during which the address must remain constant
Is t RC •
• At this point the previous,data is still valid on the bus. This data is
going to stay valid for tOH, which is the output hold from address
change time.
• At this point the valid data will appear at the pins. TAA is the IC
access time and is the amount of time that has to pass since the
address transition for the valid data to appear at the pins.
S14-20
APPLICATION NOTE AN-20
STATIC RAM TIMING
• At this point the IC is ready for a new address.
TIMING FOR CS CONTROLLED READ
Figure 11 shows the timing of a chip select continuous read
operation.
TIMING WAVEFORM OF READ CYCLE NO.2
~----------------------- t Rc ------------------------~
@ -----
t~----~~
________~
DATA VALID
DATAoUT
Figure 11. Timing Waveform for Read Cycle No.2
In Figure 11, it is assumed that the WE signal is high and that the
address transition has occurred and the address is val id prior to the
CS transition to a low state:
• The CS signal makes a high-to-Iow transition, therefore
becoming active. tRC is the read cycle time and represents the
amount of time that this signal has to stay active.
• Terminate the strobe. This will start turning off the output drivers.
At this point the CS signal will become inactive.
• From this point on, the output drivers are turning off and the valid
data will be present for only tHZ time after this point. tHZ is the
Chip Deselect to output in high impedance time parameter.
The Chip Select to Outputl!llow Impedance state is t~. This
shows thatt~ time after the CS high-te-Iow transition the output
drivers will be on.
• The Chip Select access time is tACS . This shows the amount of
wait necessary after the high-te-Iow transition of the CS signal
before the valid data will appear at the output pins.
WRITING TO COMMON I/O SRAM
•
514-21
Let us take a look at the 4K x 4-bit part (Common I/O), the
IDT6168. Figure 12 illustrates the Write Enabled controlled write for
the common I/O RAM.
STATIC RAM TIMING
APPLICATION NOTE AN-20
WRITE CYCLE NO.1
~-----------------------------twe----------------------------~
®
ADDRESS
~
___-h-....__...
rl-----------
tew
------------------~
,..,...,...,....,,....,._ _......_ ..
~---------------------tAw ----------------------~I----
14------------
®
twp
----------------.1
tow
r--------
.:CP
DATAIN VALID
tOH
d _
-L
I
DATA OUT
DATA
I=- twz~
~ tow~
M-------------------W(
UNDEFINE~
_
HIGH IMPEDANCE
'-_ __
Figure 12. Timing Diagram for WE Controlled Write, IDT6168
TIMING FOR WE CONTROLLED WRITE
The steps described below relate to Figure 12:
• Bring the address bits to the IC address pins. At this point, the
user must keep the address bits stable throughout the write
operation. The Write Cycle time during which the address must
remain constant is twe.
• Wait for the address pins to settle. The address set-up time
is tAS. During that time, the user is giving the memory time for
the cells to be selected with the row and column select logic.
• Select the chip by enabling Chip Select. At this point the chip is
selected and Tew is the chip select to end of write (WE signal)
time. This is the minimum amount of time the IC has to remain
selected.
• Strobe the Write Enable pin. This will enable the write differential
amplifiers (Since CS is active already). The minimum write pulse
width is twP. This is part of the amount of time necessary for the
WE signal to be active in order to give enough time to the cells to
change state. On the data out graph in Figure 12 (bottom), the
814-22
user should notice that at this time, the output drivers start to turn
off and, in twz time, they will be completely in the high
impedance state.
• Bring the data bits to the IC data pins. The data bits should be
"seen" by the cells for at least tow, which is the data valid to end
of write time. The Set-up time is tow for the latches of the IC.
• Terminate the strobe. A\ this point the WE signal is deactivated
and the strobing is done.
• Keep the data bits stable for a while. This corresponds to the
Hold time for the latches of the IC. The data hold time is tOH. By
holding the data bits stable during this time, the user is giving
the cells a chance to settle at the correct logic state.
• This is the end of the cycle. At this paint, the user can make an
address transition for the next operation. Remember, CS or
WE must be high during address transition. By keeping them
inactive, the user is preventing the row and column select logic
to expose the cells to the address bus while it is in transition.
APPLICATION NOTE AN-20
STATIC RAM TIMING
WRITE CYCLE NO.2
®
®
~-------------------------- twe------------------------------------------------~
ADDRESS
-1101+------------------
tew -----------------------------....
----------------~----__
r-4------------
~------------- tAw ---------------------------~~
twp
-----------------~
®
1 4 - - - - - tDW ---------------.j
DATA VALID
DATAoUT
-----------------------------~~----------------H-IG-H--IM-P-E-D-A-N-C-E--------
___
Figure 13. Timing Diagram for CS Controlled Write, IDT6168
TIMING FOR CS CONTROLLED WRITE
The steps described below refer to Figure 13.
• Keep the Write Enable low (enabled). During a Chip Select
controlled write, the Write Enable signal is supposed to be
active for at least the write pulse width amount of time. The time
that the WE signal is enabled should correspond to the time
where the IC is selected for at least the width of the write pulse.
From the moment that WE becomes active, twz is the amount of
time after which the output drivers are turned off and reach high
impedance state.
• Bring the address bits to the IC address pins. The user should
keep the address bits stable throughout the write operation. The
Write Cycle time is twe during which the address must remain
constant.
• Wait for the address pins to settle. The address set-up time is
tAS. During that time, the user is giving the memory time for the
cells to be selected with the row and column select logic.
• Strobe the Chip Select. This will turn on the bit and row select
switches and bring the cells to a situation where they are ready
to be written into. The chip select to end of write time is tew. This
is the minimum width of the CS strobe.
• Bring the data bits to the IC data pins. The Data bits should be
"seen" by the cells for at least tDW, which is the data valid to end
of write time. The Set-up time is tow for the latches of the IC.
• Terminate the strobe. At this pOint, the CS signal is deactivated
and the strobing is done.
• Keep the data bits stable for a while. This corresponds to the
Hold time for the latches of the IC. The data hold time is tOH. By
holding the data bits stable during this time, the user is giving
the cells a chance to settle at the correct logic state.
• This the end of the cycle. At this point the user can make an
address transition for the next operation. Remember, CS or
WE must be high during address transition. By keeping them
inactive, the user is preventing the row and column select logic
to expose the cells to the address bus while it is in transition.
SOME POINTS TO NOTICE IN COMMON 1/0
SRAMs
1. WE vs. CS Controlled Write on Common 1/0
SRAMs
One more detail about common I/O is that it is possible to
improve the speed of operation of the system by intelligently
chOOSing what signal will be strobed during a write:
if the user decides to strobe the WE signal, he would have to wait
for at least:
- Twz + Tow (Write Enable to output in high Z + data valid to
end of write)
if the user decides to strobe the CS signal, he would have to wait
only for:
- TWP (Write Pulse width)
- And generally ------->Twz + Tow ~ Twp
2. WE Controlled Write
An additional timing requirement is to wait for the drivers to turn
off at the beginning of the write.
3. CS Controlled Write
S14-23
In a Chip Select controlled write, the designer does not have to
wait for the drivers to turn off.
STATIC RAM TIMING
APPLICATION NOTE AN-20
TIMING FOR CONTINUOUS READ
Let us now take a look at the read cycles of a common I/O
device. Again, they are not really different from the separate I/O
case. Figure 14 shows the read cycle for continuous enabled write.
In this cycle, it is assumed that the IC is continuously selected and
that the addresses are changing at a certain rate. The data is being
read after an appropriate wait after each address transition.
TIMING WAVEFORM OF READ CYCLE NO.1
o
1+--------------
@
t AC
ADDRESS
~=------------- tAA
®
1+"":;.------ tCH
DATAoUT
---------.j
@
PREVIOUS DATA VALID
DATA VALID
Figure 14. Timing Waveform for Read Cycle No.1
In a continuously enabled read cycle, CS is active, therefore the
IC is selected and WE Signal is high-putting the IC in the read
"mode" by turning off the output drivers. Let us examine Figure 14
step by step:
• Bring the address bits to the IC address pins. The read cycle
time is tAC parameter during which the address remains
constant.
• At this point the previous data is still valid on the bus. This data is
going to stay valid for tOH, which is the output hold from address
change time.
• At this point the valid data will appear at the pins. TAA is the Ie
access time and is the amount of time that has to pass since the
address transition for the valid data to appear at the pins.
• At this point the IC is ready for a new address.
TIMING FOR CS CONTROLLED READ
Let us now take a look at Figure 15, which shows the timing of a
Single read operation.
TIMING WAVEFORM OF READ CYCLE NO. 2
------,
®
14-----------tAC
-------------.,.-1
1------------
1 4 - - - - - - - t ACS - - - - - - - l . - l
tLZ
HIGH IMPEDANCE
DATAOUT
DATA VALID
~ASI----------------------------~------~10
t:t~H~
. Figure 15. Timing Waveform of Read Cycle No.2
• WE goes high, putting the IC in a read "mode". The read
command set-up time is tACS . At this point the IC is ready to tum
on the output drivers as soon as the CS (Chip Select) signal
becomes active.
.
• The CS signal makes· a high-to-Iow transition, therefore
becoming active. The read cycle time is tAc and represents the
amount of time that this signal has to stay active.
S14-24
• The Chip Select to Output l!J-'ow impedance state is tLZ . This
. shows that tLZtime after the CS high-to-Iowtransition, the output
drivers will be on.
• The Chip Select access time is tACS. This shows the amount of
wait necessary after the high-to-Iow transition of the CS signal
before the valid data will appear at the output pins.
STATIC RAM TIMING
APPUCATION NOTE AN·20
• Terminate the strobe. This will start tuming off the output drivers.
At this point the ~ signal will become inactive. The valid data
will be present for only tHZ time, the Chip Deselect to Output in
High Impedance time is !Hz parameter.
• From this point on, the output drivers are turned off.
CONCLUSION
To get a better understanding of the timing for read or write
operations, this application note went through an overview
covering a range of subjects.
To start, a RAM cell and its operation was presented. Then, the
way of achieving an array of RAM by interconnecting the different
RAM cells was shown.
S14-25
There are two different sorts of RAMs: Separate I/O and
Common I/O. The application note went through a complete
explanation of read and write operations for these different types
with concrete examples.
There are two different ways of writing into the memory: Chip
Select controlled Write and Write Enabled controlled write.
While writing to a common I/O device, it is generally faster to use
the Chip Select controlled write.
The use of all RAMs is very similar and generally, if the
guidelines of this paper are followed, the operations will be
accomplished successfully.
PERFORMANCE
ADVANTAGES WITH lOT's
FLAGGED FIFOS
APPLICATION
NOTE
AN-22
By Oanh Le Ngoc
INTRODUCTION
the basic features of lOT's Industry standard FIFOs
while
providing
two
new
flags:
(IDT7201/02l03/04)
ALMOST-EMPTY and ALMOST-FULL. These flags can be used as
early warning flags In critical real-time applications such as data
acquisition, high-speed data link and pipeline Digital Signal
ProceSSing applications. In the multi-tasking environment, the
ALMOST-EMPTY and ALMOST-FULL can also be used to set the
Interrupt request In advance, so that the CPU has sufficient time to
perform the task switch without loss of data due to the task switch
latency. Other advantages of these Flagged FIFOs are an increase
in memory utilization and the Three-State Control, OE, for the
outputs (00-8). The use of independent Three-State Control
simplifies the interface with bus and I/O channels and Improves
timing in read and write cycles. Figure 1 Is a block diagram of the
new Flagged FIFOs: IDT72021/31/41.
The most common application for the FIFO Is an elastic data
buffer between two synchronous or asynchronous systems for the
purpose of passing data.
Because data Is produced and accepted at different rates, It Is
Important to monitor the boundary conditions (FULL or EMPTY) of
the data buffer. Failure to act on the boundary conditions will result
in data overflow or underflow. The current FIFO generation, such
as IDT7201/02l03/04, signals the empty, half-full and full condition
by asserting the EF, HF and FF , respectively. The empty and full
flags are also fed back internally and inhibit further Read and Write
operations until the FIFO Is no longer empty or full.
The Increasing use of high-speed CMOS, coupled with the
Introduction of the 32-blt CPU, has created the demand for a
faster and smarter generation of FIFOs. New Flagged FIFOs offer
DO-8
w
B
FLAG
lOGIC
RS
]![ /RT
~
RF
~
----I RESET
-..J..._l_O_G_IC_....
00-8
Figure 1. Simplified Block Diagram for Flagged FIFOs
© 1989 Integrated Device Technology, Inc.
S14-26
Printed In the U.S.A.
01119
PERFORMANCE ADVANTAGES WITH
lOT'S FLAGGED FIFOS
APPLICATION NOTE AN·22
AE'F
1/8 FULL
AE'F
7/8 FULL
ALMOST-EMPTY FLAG
ALMOST-FULL FLAG
Figure 2. Almost-Empty and Almost-Full Flags on the 10T72021/31/41
APPLICATIONS USING THE FLAGGED FIFOS
Typical applications using the new features of the Flagged
FIFOs are demonstrated below.
• ALMOST·EMPTY AND ALMOST·FULL FLAG AS EARLY
WARNING FLAGS IN REAL·TIME DIGITAL SIGNAL
PROCESSING APPLICATIONS
Figure 3 is a simplified block diagram of a real-time spectrum
analyzer featuring AID channels, input buffer, FFT processor,
display processor, output buffer and CRT. In operation, the DSP
engine processes on the previous frame of data at the 50 MHz
rate,. while the AID channel samples the analog signal at the
comparatively slow rate of 20 MSPS. This data rate mismatch
requires the use of a FIFO toact as an elastic data buffer. To
prevent data overflow, the ALMOST-FULL flag is used as an
early waming to the DSP controller. With this signal, the DSP
engine has sufficient time to empty the Input buffer (FIFO) into
the buffer at Its own high-speed data rate. Meanwhile, the AID
channel continues to refill the input buffer from other side at its
much slow rate. At the other end of the system, a second FIFO
acts as an output buffer between the high-speed display
processor and slow CRT. In this case the ALMOST-EMPTY
FLAG is used as an early waming so that the display processor
can begin filling the buffer with the next image.
IDTm
Figure 3. Simplified Block Diagram for a Real-Time Spectrum Analyzer
S14':27
. _ - - _..._._........._--.•....._ - _ . _ - - - -... _ - - - - - - ...
PERFORMANCE ADVANTAGES WITH
lOT'S FLAGGED FIFOS
APPLICATION NOTE AN-22
• MAXIMUM UTILIZATION OF MEMORY WITH THE
ALMOST-FULL AND ALMOST-EMPTY FLAGS IN HARD
DISK DRIVE APPLICATIONS
Because of the high data rates used in the hard disk drive
protocols, SMD, SCSI and IPI or the· standard data
communication protocols (Ethernet, Supernet and Fiber-optlcs
which can go up to 100 Mbits per second), even the newer and
faster microprocessors will struggle to keep up with the speed of
I/O channels. For this reason, data buffering is always
considered in any high-speed I/O transfer. The design in Figure
4 shows the data buffer for a high-speed hard disk application.
In such CPU-te-I/O controller applications, FIFOs are often
used to construct the data buffer. Normally two sets of FIFOs are
arranged In the back-to-back manner, where one set acts as a
transmit buffer and the other as the receiver buffer. In this
arrangement, the CPU dumps data In the transmit FIFO until the
FIFO is 7/8 full. At this point, the FIFO sets the Almost-Full Flag,
Initiating the data transfer to the I/O channel at its higher speed
rate. In similar fashion, the high-speed I/O channel dumps data
Into the receiver FIFO until It Is almost full. In this case, the
Almost-Full· Flag triggers an Interrupt request to the host
processor or DMA request to the DMA controller. If the request
goes to the DMA controller, the DMA channel can transfer the
entire block of data Into the system memory in one burst. Figure
4 Illustrates a host Interface between a 32-bit microcomputer
system based on an Intel 80386 and a Disk Drive.
DISK
CONTROLLER
HARD DISK CONTROLLER
Figure 4. Block Diagram of a Disk Drive Controller
• ASYNCHRONOUS THREE-STATE CONTROL
Another common use for FIFOs Is as a data buffer between a
microcomputer and high-speed I/O bus for the purpose of
passing data back and forth. The figures on the next page
Illustrate two examples of the Interface between a 32-blt
processor and the I/O channel of the IBM PC AT, one using
S14-28·
FIFOS without three-state control and the other using FIFOs
with their three-state control. As Table 1 Indicates, using the new
Flagged FIFOs with their three-state control pin produces faster
read and write cycles. An additional advantage is the ability to
repeat a reading from the same FIFO location without
advancing the read pointer.
PERFORMANCE ADVANTAGES WITH
lOT'S FLAGGED FIFOS
APPLICATION NOTE AN-22
DATA ADDRESS
BUS CONTROL
r---~-.t
VO
A0-23
CHANNEL
FOR
IBM PCAT
D0-31
Figure 5. 10T7202 FIFOs Without Three-State Control as a Data Buffer Between IBM AT and an Accelerator Board
DATA ADDRESS
BUS CON,.;.;TR.,;.;;O.;;,.L~--..
I/O
CHANNEL
A0-23
FOR
IBM PC AT
Figure 6. 10T72021 FIFOs withThree-State Control as a Data Buffer Between IBM AT and an Accelerator Board
S14-29
PERFORMANCE ADVANTAGES WITH
IDT'S FLAGGED FIFOS
APPLICATION NOTE AN·22
Table 1. Read and Write Cycle with IDT7202/021
WITHOUT THREE-STATE
CONTROL
WITHOUT THREE-STATE
CONTROL
10174FCT521 A: TPLH
7.2ns
O.Ons·
10174FCT138A:TPLH
9.0ns
9.0ns
1017402/021: TRC
35.0ns
35.0ns
TOTAL
50.2ns
44.0ns
DELAYS PATHS
• Although this propagation delay Is specified at 7.2ns, it occurs In parallel with the slower 9.0ns propagation delay of
the 10174FCT138A and is not additive as is the case In the ·without three-state control· application.
CONCLUSION
As the need for high-speed data computation increases, the
FIFO must also become faster and smarter. The next generation of
FIFO, as exemplified by the 10T72021/31/41, meets that challenge.
S14-30
t;)
Intesrated Device1echnoJogy.Jnc.
APPLICATION
NOTE
AN-23
HIGH-PERFORMANCE
FIXED-POINT FAST
FOURIER TRANSFORM
PROCESSOR
By Julie Un and Danh Le Ngoc
Some digital signal processing applications involve large
amounts of data requiring very fast, real-time processing. In these
cases, convolution in the time domain is too time consuming and is
usually replaced by the frequency domain multiplication. The use
of an FFT processor in a pipelined architecture meets the
high-speed computation requirements for this class of
applications. Typical application areas include:
• Digital Image Processing-Image compression, used for
communication and storage, can be done in the Fourier
transform domain. FFT processing has been successfully
applied to image deblurring for motion blur and optical
aberrations. Reconstruction from projections requires
two-dimensional FFT processing.
• Radar Signal Processing - Dopplerfrequency determination for
ambiguities is done in the frequency domain. Implementation of
the critical digital match filter requires a high-speed FFT
processor. When the detection processor encounters a large
number of targets or clutter, a special kind of postprocessor is
required, which is implemented with a small, fast FFT system.
The moving target indication in air traffic control uses a bank of
FFT-implemented bandpass filters. The sophisticated
computation of signal compression used for synthetic aperture
radar also needs the power of FFT processing.
• Sonar Signal Processing -In active sonar systems, the user
transmits the acoustic energy. The energy is observed after it
has propagated through the water and is reflected by a target.
Uses include target detection, communications, navigation,
mapping and charting. The signal processing methods used in
active sonar signal processing have much in common with
radar. As such, the detector processors are also implemented
with FFT-based algorithms for building match filters and
detecting ambiguities. With passive sonar systems, one listens
to signals that are radiated by various sources of acoustic
energy in the ocean. Some of these sources are natural, arising
from wind, earthquakes, and marine life. The signals of most
interest are man-made by shipping and military vessels. The
most important use of passive sonar is in surveillance systems.
Spectral analysis and array processing are the main signal
processing elements of a passive sonar system and both are
prime candidates for FFT processing.
The fixed point implementation of an FFT processor can be
used to meet the very high performance requirements of some
special-purpose systems, where the dynamic range has been
carefully studied to prevent overflow problems. The IDT7317
(multiplier) and IDT7384 (ALU) are new building blocks with
architectures optimized for fast pipeline digital signal processing
(DSP) applications. With lOT's high-performance submicron
CEMOS technology, both chips have low power consumption and
very fast (20ns) clock cycle time.These two powerfullCs make it
very easy to implement a high-speed FFT processor. This
application note gives a brief introduction to the IDT7317 and the
IDT7384, after which the general architecture ofthe FFT processor
is described. Within the processor are several basic function
blocks: control unit, butterfly unit, address generator, input and
output buffers, and the coefficient look-up tables. Further
explorations detail the design of the control and butterfly units. We
© 18111 Integrated Device Technology, Inc.
814-31
also consider the data addreSSing problem. The performance for
1024-point complex FFT is discussed. Appendix A contains the
description of OFT and FFT algorithm.
FEATURES OF THE IDT7317 AND IDT7384
The IDT7317 is a fixed point 16-bit x 16-bit parallel multiplier with
a 32-bit output. Multiplier operations include unSigned, two's
complement and mixed-mode multiplications for both integer and
fractional numbers. A functional block.diagram for the IDT7317 is
shown in Figure 1. It features a flexible output scaling shifter and
pipeline or flow-through operational modes. Figure 2 is the
functional block diagram of the IDT7384 16-bit ALU, which can be
cascaded to form a 32-bit ALU. In addition to 32 basic ALU
functions, an on-chip funnel shifter performs flexible scaling
functions. On-chip merge capability is also provided. Input data on
AO-15 and 80-15 can be fetched directly by the ALU or shifter inthe
flow-through mode or stored in the pipeline registers. Data path B
has a single register, but Data path A can be optimized to match
pipelined DSP systems with depths to 4 levels. The ALU or shifter
result is fed into one of three output registers and can then go into
either the internal feedback path for accumulation or through final
stage manipulations. Available manipulations include shifting,
rounding, bit-reversing, and flow-through. The output shifter is
used for scaling. Rounding can be dona on either bit 14 or bit 15 of
the Least Significant Slice. The bit-reversing scheme is particularly
suited for FFT processing on data lengths of 1K, 4K, 16K, and 64K.
Both the IDT7317 and the IDT7384 are housed in 84-pin packages.
XO-15
YO-15
PO-31
Figure 1. Functional Block Diagram of the IDT7317
Printed In the U.S.A.
01/811
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
AO-15
APPLICATION NOTE AN-23
HOST DATA BUS
80-15
BUTTERFLY
UNIT
Figure 3. The Basic Block Diagram of an FFT Processor
FREG2
CONTROL UNIT
YD-15
Figure 2. Functional Block Diagram ofthe 1DT7384
GENERAL ARCHITECTURE
As shown In the block diagram of Figure 3, the FFT processor is
composed of six basic blocks. The control unit contains the
horizontally micro-coded program, which controls all the other
blocks in parallel. Initially, a macro-instruction is fetched from the
host processor. The opcode is then decoded and used as the
jump-address to the microprogram. By executing a sequence of
micro-instructions, the microprogram emulates this macroinstruction. All internal tasks, such as address generation,
input-buffer access, table look-up, butterfly execution, and writing
the result to the output-buffer, are controlled by these
micro-instructions. All of these tasks are executed in a pipelined
manner.
The control unit coordinates the entire FFT engine. It consists of
a high-speed 12-bit sequencer, 10T71502 Registered RAMs for
microcode storage, and a multiplexer for condition code selection
(Figure 4). The 10T71502 is a registered RAM with a high-speed
pipeline register at the output and serial load and read capability
using the lOT Serial Protocol Channel (SPC). FFT microprograms
can be loaded through the SPC and executed in real time. An octal
register (IDT49FCTS1SA) is inserted between the sequencer and
the writable control store (WCS) to provide pipelining. Table 1
summarizes the control unit's worst case propagation delay time if
the multiplexer is Implemented with a 74F151 and the sequencer
with an IDT39C10. It is clear that the propagation delay from
register to WCS dominates the timing consideration of the whole
control unit. 45ns Is the clock cycle requirement of the control unit.
S14-32
Table 1. The Worst Case Propagation Delay Time Within
the Control Unit
•
•
•
•
•
•
•
Condition Multiplexer 74F151
SequencerlDT39C10
Input set up time of IDT49FCT818A
Total
Propagation delay of IDT49FCT818A
WCS IDT71502
Total
9ns
16ns
2.5ns
27.5ns
10ns
35ns
45ns
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN-23
BUTTERFLY STAlUS
EX. SIGNALS
EXECUTION UNIT
Figure 4. Block Diagram of the Control Unit
BUlTERFLY UNIT
As discussed in Appendix A, the butterfly units execute the heart
of the FFT computation, consisting of four multiplications, three
additions and three subtractions. The signal flow graph of the
butterfly computation is shown in Figure Sa, where the input
variables are denoted as C and D and the output variables as
GandH.
With the twiddle factor represented as Wk= ele = cose +jsin e,
the relationship between butterfly input and output is redrawn in
Figure Sb to separate the real and imaginary parts of complex
numbers.
Because the butterfly computation is highly repetitive,
implementation of the FFT algorithm lends itself to a pipelined
structure. This section presents four different implementations of
the butterfly unit, using the lDT7317 multiplier and IDT7384 ALU.
Their designation-six-cycle, four-cycle, three-cycle, and single-
S14-33
cycle-reflect the clocked cycle time that each needs to complete
an entire butterfly computation.
c
G
D
H
Figure Sa. The Signal Flow Graph of a Butterfly With One
Complex Multiplication and Two Complex Additions
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
ReC
APPLICATION NOTE AN-23
+
--------------~----~~--~D---~~ReG
sine
+
ImC ----+-----------+--_~--~D---~~ ImG
fmD
The six-cycle butterfly unit needs only one 1017317 and two
cascaded 1017384s, which form a 32-bit ALU (Figure 6). The
addition of two consecutive results from the 1017317 is
accomplished by using the B register of the 1017384's input path
B. In addition, the three output registers can be used to hold
temporary data which Is fed back to the ALU as input for the next
two addition cycles. Thus, the ALU performs the six additions in six
continuous cycles. The pipeline Is kept full as each succeeding
butterfly computation Is performed. Figure 7 shows the timing
diagram of a complete slx-cycle butterfly, where ReG and ReH
outputs are at clock 5 and clock 6, ImG and ImH outputs are at
. clock 8 and clock 9.
----~--~~--~~--~~--~~--~~fmH
case
G = C + ale. D
H = C- ale. D
ReG = ReC + (ReD. case - ImD • sine)
ReH = ReC - (ReD. case - ImD • sine)
ImG = fmC + (ImD • case + ReD. sine)
ImH = fmC - (ImD • case + ReD. sine)
Figure 5b. The Signal Flow Graph of a Butterfly With Four
Real Multiplications and Six Real Additions
ReD OR/mD
ReCOR/mC
cas e OR sin e
... ~ 16
...... 16
>
> AO
...... 16
U
·1
II
'>
X
Y
16 BY 16 MULTIPLIER
:>
> A1
f
>
r>
A2
I
MUX
B
MUX
32-BIT ALU
~
F1
>
FO
16
....
r
TO OUTPUT BUFFER
Figure 6. Six-Cycle Butterfly
S14-34
1, ...••
P
32
--------..
__ _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ .
..
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
MUL
X,Y
P
ALU
B
FO
AO
A1
A2
F1
I.
r---
r
NTH BUTIERFLY OUTPUT _ _- :
PIPELINE LATENCY
N + 1ST BUTIERFLY OUTPUT
-----------i-~.
Figure 7. The Timing Diagram of Slx·Cycle Butterfly
The four-cycle butterfly has one multiplier and two 32-bit ALUs
(Figure 8). One of the ALUs handles the operations for ReG and
ReH. The other one takes care of ImG and ImH. The timing diagram
in Figure 9 shows that four clock cycles are required at the
beginning to fill the pipeline. Starting from clock 5, we get the
results of ReG and ReH from one ALU output. The results of ImG
and ImH from the other ALU are at clock 7 and clock 8. At clock 9
we will expect the result of ReG from the next butterfly computation.
S14-35
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
fmC
case OR sine
ReD OR fmD
ReC
.... 1-' 16
.... 1-' 16
.. I-- 16
.. I-- 16
I>
AO
J
.>
AO
[>
A1
16 BY 16 MULTIPLIER
I>
>
A1
P
::::::::
:
:::::
.. I-- 32
[>
A2
t>
A3
[>
t>
B
B
....-:.. .:...J;;
MUX
>
A2.
~
A3
MUX
MUX
MUX
.:::
./
'">FO
F1
~ FO
::> F1
.....
[>
16
..... 16
"
TO OUTPUT BUFFER
"
TO OUTPUT BUFFER
Figure 8. Four·Cycle Butterfly
S14-36
I
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN-23
MUL
X,Y
P
ALU1
B
FO
A3
F1
ALU2
B
FO
A3
F1
NTH BUTTERFLY
OUTPUT
~
PIPELINE LATENCY--------i>!
N+1ST BUTTERFLY
OUTPUT
-
I
~
Figure 9. The Timing Diagram of Four-Cycle Butterfly
The three-cycle butterfly requires the addition of one more
multiplier (Figure 10). One multiplier and one ALU form one
independent data path, one for ReG and ReH, the other for ImG and
ImH. These two data paths proceed in parallel (Figure 11).
Therefore, the results of ReG and ReH from different ALUs come
out at the same time-at clock 5. At clock 6 we get the results of
814-37
ReH and ImH. However, ReG and ImG from next butterfly should
wait for one more cycle because the ALUs are dedicated to the
ImD sin and ReD sin
previous stage operations, I.e. ReD cos
+ ImD cos It is clear that the three-cycle is formed because of
this waiting cycle.
e.
e-
e
e
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN-23
ReD ORlmD
R1
case OR sine
16
> ,AO
x
:::::
> A2
~I
AO
>-.XJl)y
J~ Y
I
I> P
A1
{16
1
JIDT:7
I
MULTIPLIER
MULTIPLIER
:
ImC
J16
16
::::1>..
:;:;
I
P
A1
:
.-y.:.
:;::;
--+--32
-+-32
B
A2
>
B
A3
:.'Y
,
/.
>F1
t>F0
t>
FO
[>F1
2." DT71 :2"
.. 16
, 16
TO OUTPUT BUFFER
I.·
TO OUTPUT BUFFER
Figure 10. Three-Cycle Butterfly
MUL1
X,Y
P
ALU1
B
FO
A3
F1
MUL2
X,Y
P
ALU2
B
FO
A3
F1
I+-
~~ERFLY ~
~.
PIPELINE LATENCY
N + 1ST
BUTTERFLY
Figure 11. The Timing Diagram of Three-Cycle Butterfly
S14-38
-+I
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
The high-speed single-cycle butterfly is achieved by assigning
a hardware element to each operation, i.e. four multipliers and six
ALUs for one butterfly unit (Figure 12). The pipeline is now filled in
just two cycles and generates outputs ReG, ReH, ImG, and ImH In
ReC
ReD
,/16
/
case
sine
fmD
> A1
t>
MUL2
I>
I
P1
1.
32
P2
MUL4
MUL3
I
~
:::1>
t>
-1
F01
I'
.>
"
ReH
> A1
F02
I
.~.. A2
t>
F04
,
I
32
ALU5
....... ::.
,/
P4
ALU2
ALU4
"v 16
ReG
t>
P3
32
ALU1
~
16
~XlpY
4
: I" F03
/
~------~"+---------,~.
I
MUL1
ALU3
fmC
... v16
I- 16
16 ), 16
1
> A1
every clock cycle thereafter (Figure 13). Since two IDT7384s are
cascaded to perform 32-bit operations, 40ns is required to finish
one addition or subtraction.
16
F05
S14-39
~F06
, / 16
,~ 16
"
ImH
ImG
Figure 12. Single-Cycle Butterfly
ALU6
,
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
2
4
3
5
MUL1
X.Y
-Z
ReD
case
I
ReD
case
I
ReD
ReD
case
I
ReD
case
I
I
case
P1
MUL2
X.Y
K
fmD
I
sine
"'
ReD • case
ReD • case
fmD
I
sine
ImD
I
sine
I
P2
"-
ALU1
F01
"-
ALU3
"-
I
ReD • case
-lmD • Sine
ReC
ReC
ReC
sine
::
'
.
X
ReG
ReC
,
I
\
;r:'1t1r
I
ReH
sine
ReD, sine
ReD, sine
ReD , sine
ReD • sine
ReD • sine
ReD • sine
ReD • sine
case
fmD , case
ImD , case
ImD , case
ImD • case
ImD • case
ImD • case
ImD • case
ReD • sine
+lmD • case
ReD • sine
+lmD • case
ImC
fmC
ReD
P3
ReC
ReC
/
I
sine
ReD • case
-lmD • sine
F04
ReD
I
ReD • case
-lmD • sine
"
K
ImD
ImD • Sine
/ .,.".,: ...:Hal:i
A2
I
"-
MUL4
X.Y
sine
ImD • sine
ALU4
X.Y
I
ImD • sine
F03
MUL3
fmD
ReD • case
J
ImD • sine
A2
ReD • case
K
fmD
I
case
fmD
P4
"-
ALU2
I
ReD • sine
"- +lmD • case
F02
ALUS
fmC
A2
)
"-
.,,:\j
F05
ALU6
A2
"'
F06
..
ImC
fmC
ImC
fmH
\ . - NTH
BUTTERFLV---.
PIPELINE LATENCY
Figure 13. The Timing Diagram of Slngle·Cycle Butterfly
S14-40
ImG
.....
+
N + 1ST
BUTTERFLY
-1
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
this requirement feasible. The pipeline for butterfly computation
from one stage to another stage will not be interrupted.
ADDRESSING AND MEMORY DESIGN
Since the butterfly output rate can be as fast as 40ns, the
memory access time should match this speed. The two IDT71502
registered RAMs were selected to implement the SINE and
COSINE look-up tables based on their speed (35ns). Furthermore,
the on-chip Serial Protocol Channel (SPC) allows user to load WCS
and look-up tables simultaneously with the same serial input
set-up. Both in-place and not-in-place computations require
"bit-reversed" addressing in the input sequence for correctly
ordered output results. This is easily accomplished with the special
"bit-reversing" feature of the I0T7384 , for data lengths of
1K,4K,16K, or 64K. Hence, the 10T7384 is used as the address
generator.
In the in-place computation, the butterfly outputs are stored
back into the same storage locations (Figure 20). The drawback of
this method is the complicated addressing scheme, because the
addresses of the memory locations for each butterfly computation
vary from stage to stage. Figure 14 shows the memory organization
for the in-place computation.
l
...
DATA
BUS
DATA
BUS
ReD
_t_
ReG
;-
5
0
fmG
>-
-fmH
:E
w
:E
BUTTERFLY
~f-r+ DATA
BUS
ReH a:
If we use the dual-port RAM 10T7132 and 10T7142 as the
input/output buffers, the memory delay time for one butterfly
computation is calculated in Table 2.
~
fmG
~r-+
ReD
t - - :E
w
fmD :E
I
Figure 15. Memory Allocation For the Not-In-Place
Computation
ADDRESS .1
GENERATOR
ReG
ReG ~
t - - >fmG a:
ADDRESS
GENERATOR
I
>-
a:
0
:E ~
w
:E
BUTTERFLY f-r--+ DATA
BUS
Table 2. Memory Delay Time For One Butterfly
Computation
Output delay to the clock on IDT7384
fmD
Twc or TRC of the IDT7132/42
Input setup time for IDT731717384
Total
18ns
35ns
5ns
58ns
Figure 14. Memory Allocation For the In-Place Computation
CONCLUSION AND PERFORMANCE
This application note has introduced a high-speed CMOS FFT
solution for a class of OSP applications that require very
high-speed processing, such as imaging processing, radar and
sonar signal processing. Fast (20ns) 10T7317 multipliers and
10T7384 ALUs are used to build the butterfly unit. The 10T7384 is
also used for address generation. The SINE and COSINE look-up
tables use the 10T71502 registered RAM. Input and output buffers
are made up of 10T7132/42 dual-port RAMs. The control unit
consists of an IOT39C10 sequencer and an 10T71502-based WCS.
Figure 16 illustrates the complete hardware implementation for the
high-speed fixed-point FFT processor.
Three factors affect the pipelined system performance: the
signal delay time of the control unit (45ns), the memory delay time
of the input register (58ns), and the butterfly computation time,
which is 40ns for a single-cycle butterfly implementation. Since the
memory access delay path is the longest, the 58ns delay time
determines the pipeline clock for 'the whole system.
As the not-in-place computation of Figure 22 (in Appendix A)
shows, the outputs of the butterfly are not put back where they
came from. Since the butterfly span for input and output is kept
constant from stage to stage, a simple and constant addressing
method can be used to select data for each butterfly in all stages.
The block diagram in Figure 15 illustrates the memory
implementation for the not-in-place algorithm. However, the
butterfly outputs stored in ReG, fmG, ReH, and fmH are not in
one-ta-one correspondence with the next stage input storage ReC,
fmC, ReD, and fmD. Eight dual-port RAMs are used for input and
output buffers-four for input and four for output. So, the output
results can be put back to the proper input buffers once they are
generated. This kind of data shuffling operation has to be done
before the next-stage butterfly computation starts. The memory
implementation with dual-port RAMs and pipeline structure make
814-41
------_.. _._._-._----------------------
iII
•
HIGH-PERFORMANCE FIXED-POINT
FAST FOURIER TRANSFORM PROCESSOR
-
.....
......
DATA
~~
-"
~r
I
APPLICATION NOTE AN-23
~
I
IDT49C818
lOT 39C10
r--
SEQUENCER
)
IDT49FCT81
IDT71502
.....
.....
WCS
•
I
+
•
+
I ADDRESS
lOT 7384
I0T7384 II'OT7384
ADDRESS
ADDRESS
... I GENERATOR
GENERATOR
GENERATOR
L--
L...--.....J
~
+
1/0L
1/0L
1/0L
1/0L
AL 7132 AR
AL 7132 AR
AL 7132 AR
AL 7132 AR
IIOR
IIOR
IIOR
IIOR
ReD
IReC
lImO
ImC
I
I
-"I'
"I'
IDT7317
IDT7317
IDT7317
IDT7384
1
IDT7317
+
71502
71502
sine
case
I
I
J
IDT7384
••••••••
IDT7384
•
ReH
IDT7384
IDT7384
,.
•
ReG
ImH
IDT7384
..
ImG
Figure 16. A Fixed-point FFT Processor With Single-Cycle Butterfly and In-Place Design Where Control Unes Are Not Shown
However, for a single-cycle butterfly, this critical memory delay
can be reduced by replacing the 35ns I0T7132/42 dual-port RAMs
with a pair of fast IDT71682 static RAMs (20ns) arranged in the
ping-pong structure shown in Figure 17. In this approach, the
butterfly unit reads data from the first RAM, and writes output data
to the second RAM. Once a single stage FFT operation is done,
then, by changing the state of the WE· input, the butterfly unit
reads data from the second RAM and writes output data to the first
RAM. In this fashion, one RAM is always in the read mode and the
other is in the write mode.
The memory delay time now becomes 43ns, which moves the
bottleneck to the control unit (45ns delay). Thus, the system clock
cycle time for a single-cycle butterfly becomes 45ns. The system
processing time for a 1024-point complex FFT, where 5120
butterfly computations must be made, will be 5120 X 45ns =
230ps.
S14-42
_.__. _ - _ . _ - - - - - - _ . _ - _ .._ . _ - - - - - - - -
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
DATA IN
16
ADDR
71682
71682
. . .;j--_ _ _
LEFT
cs
~~--~--~
~
CS
~
16
DATA OUT
Figure 17. The Ping·Pong RAM Used to Replace Dual-Port RAM of Figure 16
814-43
------_._----_ ....... __ . .
ADDR
RIGHT
HIGH·PERFORMANCE FIXED·POINT
FAST FOURIER TRANSFORM PROCESSOR
APPLICATION NOTE AN·23
APPENDIX A
FOURIER TRANSFORM AND DFT
In general, transforms are used to simplify certain types of
problems by moving them into a different domain in which analysis
is much easier. Specifically, the Fourier transform is used to
determine the frequency components. of a time series by
transferring the time domain signal into the frequency domain. In
essence, the Fourier transform decomposes the signal into the
sum of sinusoids of different frequencies. The result can be plotted
as amplitude or phase angle versus frequency. An inverse
transform converts the frequency analysis back to the time
domain. Mathematically, the relationship is based on the pair of
equations:
00
J
=J
X(f) =
x(t)e -j2'TTt! dt
-00
00
x(t)
FFT ALGORITHM
X(f)e -j21Tt! df
For convenience in notation, the DFT equations are generally
written in terms of WN, defined as:
-00
where x(t) is the signal to be decomposed into a sum of
sinusoids and X(fJ is the Fourier transform of x(t). Inherent
properties of the Fourier transform help solve problems easily in
the frequency domain. For example, time domain convolution is
equivalent to frequency domain multiplication.
If the signal x(t) is sampled at equally spaced intervals of I:J. t to
produce a discrete sequencexn =x(nl:J.t) for -oo >
NE
C4
C5
T
C6
T
T
0
16
32
48
64
80
96
112
T
T
14
T
M
M
T
1
0
0
0
1
CO
1
17
33
49
65
81
97
113
2
0
0
1
0
C1
T
T
M
T
2
24
T
2
18
34
50
66
82
98
114
3
0
0
1
1
T
18
8
T
M
T
T
M
3
19
35
51
67
83
99
115
C2
T
T
15
T
3
25
T
4
20
36
52
68
84
100
116
T
19
9
T
M
T
T
31
5
21
37
53
69
85
101
117
T
20
10
T
M
T
T
M
6
22
38
54
70
86
102
118
T
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0,
0
0
9
1
0
0
1
A
B
C
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
M
T
T
M
T
4
26
7
23
39
55
71
87
103
119
C3
T
T
M
T
5
27
T
8
24
40
56
72
88
104
120
T
21
11
T
M
T
T
M
9
25
41
57
73
89
105
121
T
22
12
T
1
T
T
M
10
26
42
58
74
90
106
122
17
T
T
M
T
6
28
T
11
27
43
59
75
91
107
123
T
23
13
T
M
T
T
M
12
28
44
60
76
92
108
124
T
M
T
T
M
T
7
29
13
29
45
61
77
93
10
125
M
T
M
M
T
E
1
1
1
0
16
T
T
14
30
46
62
78
94
110
126
F
1
1
1
1
T
M
M
T
0
T
T
M
15
31
47
63
79
95
111
127
NE=NO ERROR
Cn = check-bit error bit n
n = data-bit error bit n
n = decimal equivalent of the syndrome
T = Two errors
M = Multiple errors
Table 1. 32-bit Syndrome Tables with Hex, Binary and Decimal Equivalents.
S14-59
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
HEX
ERROR
S7
S6
o
o
S5
S4
HEX
o
S3
S2
S1
SO
0
0
0
0
o
2
3
4
o
o
o
6
o
7
o
9
A
BI
CI
DI
EI
FI
o
o
0
0
o
5
8
0
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
APPLICATION NOTE AN·24
1
2
3
4
5
6
7
0
0
0
o
o
o
o
o
o
o
o
o
o
o
o
o
8
9
A
B
o
o
o
o
o
o
o
o
C
D
o
o
o
E
F
o
NE
C4
C5
T
C6
T
T
62
C7
T
T
46
T
M
M
T
o
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
CO
T
T
14
T
M
M
T
T
M
M
T
17
33
49
65
81
97
113
129
145
161
C1
T
T
M
T
34
56
T
T
50
40
2
18
34
50
66
82
98
114
130
146
162
M
T
T
30
193
209
225
241
T
M
T
T
M
178
194
210
226
242
T
18
8
T
M
T
T
M
M
T
T
M
T
2
24
T
3
19
35
51
67
83
99
115
131
147
163
179
195
211
227
243
C2
T
T
15
T
35
57
T
T
51
41
T
M
T
T
31
4
20
36
52
68
84
100
116
132
148
164
180
196
212
228
244
T
19
9
T
M
T
T
63
M
T
T
47
T
3
25
T
5
21
37
53
69
85
101
117
133
149
165
181
197
213
229
245
T
20
10
T
M
T
T
M
M
T
T
M
T
4
26
T
246
6
22
38
54
70
86
102
118
134
150
166
182
198
214
230
M
T
T
M
T
36
58
T
T
52
42
T
M
T
T
M
7
23
39
55
71
87
103
119
135
151
167
183
199
215
231
247
C3
T
T
M
T
37
59
T
T
53
43
T
M
T
T
M
8
24
40
56
72
88
104
120
136
152
168
184
200
216
232
248
T
21
11
T
M
T
T
M
M
T
T
M
T
5
27
T
9
25
41
57
73
89
105
121
137
153
169
185
201
217
233
249
T
22
12
T
33
T
T
M
49
T
T
M
T
6
28
T
10
26
42
58
74
90
106
122
138
154
170
186
202
218
234
250
17
T
T
M
T
38
60
T
T
54
44
T
1
T
T
M
11
27
43
59
75
91
107
123
139
155
171
187
203
219
235
251
T
23
13
T
M
T
T
M
M
T
T
M
T
7
29
T
12
28
44
60
76
92
108
124
140
156
172
188
204
220
236
252
M
T
T
M
T
39
61
T
T
55
45
T
M
T
T
M
13
29
45
61
n
93
109
125
141
157
173
189
205
221
237
253
16
T
T
M
T
M
M
T
T
M
M
TOT
T
M
14
30
46
62
78
94
110
126
142
158
174
190
238
254
206
222
T
M
M
T
32
T
T
M
48
T
T
M
T
M
M
T
15
31
47
63
79
95
111
127
143
159
175
191
207
223
239
255
NE=NO ERROR
Cn = check-bit error bit n
n = data-bit error bit n
n = decimal equivalent of the syndrome
T = Two errors
M = Multiple errors
Table 2. 64-blt Syndrome Tables with Hex, Binary and Decimal Equivalents.
S14-60
DESIGNING. WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
APPLICATION NOTE AN-24
CB
DATA
CB
DATA
CB
DATA
CB
DATA
0
28
20
127
40
E
60
101
1000F
21
10100
41
10029
61
10126
2
10000
22
1010F
42
10026
62
10129
3
27
23
128
43
1
63
10E
4
1000C
24
10103
44
1oo2A
64
10125
5
2B
25
124
45
D
65
102
6
24
26
12B
46
2
66
10D
7
10003
27
1010C
47
10025
67
1012A
8
10024
28
1012B
48
10002
68
1010D
9
3
29
10C
49
25
69
12A
A
C
2A
103
4A
2A
6A
125
B
1oo2B
2B
10124
4B
1000D
6B
10102
C
0
2C
10F
4C
26
6C
129
D
10027
2D
10128
4D
10001
6D
1010E
E
10028
2E
10127
4E
1000E
6E
10101
F
F
2F
100
4F
29
6F
126
10
10022
30
1012D
50
10004
70
1010B
11
5
31
10A
51
23
71
12C
12
A
32
105
52
2C
72
123
13
1oo2D
33
10122
53
1000B
73
10104
14
6
34
109
54
20
74
12F
15
10021
35
1012E
55
10007
75
10108
16
1oo2E
36
10121
56
10008
76
10107
17
9
37
106
57
2F
77
120
18
2E
38
121
58
8
78
107
19
10009
39
10106
59
1002F
79
10120
1A
10006
3A
10109
5A
10020
7A
1012F
1B
21
3B
12E
5B
7
7B
108
10123
1C
1oo0A
3C
10105
5C
1oo2C
7C
10
2D
3D
122
5D
B
7D
104
1E
22
3E
12D
5E
4
7E
10B
1F
10005
3F
1010A
5F
10023
7F
1012C
Table 3. Minimal 32-blt check-bit to data tables for diagnostic use. One data value Is listed to generate every possible check-bit pattern.
S14-61
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
APPLICATION NOTE AN-24
DATA
CB
DATA
CB·
DATA
CB
DATA
0
C
100
2F
10000
2
10100
CB
21
1
43
101
60
10001
40
10101
6E
2
46
102
65
10002
48
10102
68
3
9
103
2A
10003
7
10103
24
4
5E
104
7D
10004
50
10104
73
5
11
105
32
10005
1F
10105
3C
6
14
106
37
10006
1A
10106
39
7
58
107
78
10007
10107
76
8
58
108
78
10008
55
56
10108
75
9
17
109
34
10009
19
10109
3A
A
12
10A
31
1000A
1C
1010A
3F
8
50
108
7E
10008
53
10108
70
C
A
10C
29
1000C
4
1010C
27
0
45
100
66
10000
48
10100
68
E
40
10E
63
1000E
4E
1010E
60
F
F
10F
2C
1000F
1
1010F
1F
20
54
120
77
10020
5A
10120
79
21
18
121
38
10021
15
10121
36
22
1E
122
3D
10022
10
10122
33
23
51
123
72
10023
5F
10123
7C
24
6
124
25
10024
8
10124
28
25
49
125
6A
10025 . 47
10125
64
26
4C
126
6F
10026
42
10126
61
27
3
127
20
10027
0
10127
2E
28
0
128
23
10028
E
10128
20
29
4F
129
6C
10029
41
10129
62
2A
4A
12A
69
1oo2A
44
1012A
67
28
5
128
26
10028
8
10128
28
2C
52
12C
71
1oo2C
5C
1012C
7F
20
10
120
3E
10020
13
10120
30
2E
18
12E
38
1002E
16
1012E
35
2F
57
12F
74
1oo2F
59
1012F
7A
Table 4. Minimal 32-blt data to check-bit tables for diagnostic use. At least one data value Is listed for every possible check-bit pattern. This
table Is Identical to Table 3 except In sequence of presentation.
S14-62
~
PRELIMINARY
APPLICATION
NOTE
AN-25
THE KEY ADVANTAGES OF
MULTI-PORT STATIC RAM
Integrated DevIce'Jec:hnolosy. Inc.
By Robert Stodleck
LOCAL
MEMORY
CPU OR
PERIPHERAL
CPU OR
PERIPHERAL
I
J
III L
ADDRESS
DUAL-PORT
MEMORY
I I
~ ~
I
LOCAL
MEMORY
J
I I
DATA
Figure 1. Dual-Port, Memory With Separate Busses.
MULTI-PORT STATIC RAM MEMORY
implementing multi-processor schemes where, ideally, all the
processors use a memory bus all the time.
Another approach to memory basad communication Is that of
sharing a RAM in a time multiplexed fashion (fig 2). Time-sliced or
ping-pong shared RAM can be more efficient than conventional
DMA since it provides for independent busses and local memory.
Even so, data transfer through a shared RAM interface, as we shall
see, is inherently slower and less flexible than a multi-port RAM
interface. The additional hardware associated with implementing a
real-world shared RAM detracts significantly from the operating
speed as well as being more complex and difficult to design.
The popularity of multi-port RAM has increased as designers
have become more sophisticated about the inherent advantages of
multi-ports as a communications devices. Multi-port memory can
be far faster than alternate approaches to memory based
communication, as well as being simpler to implement. Of the
available RAM based communications links, dual-port RAM is the
least likely to limit the data processing algorithms that the link is
intended to facilitate.
THE HIERARCHY OF MEMORY BASED
COMMUNICATIONS TECHNIQUES
Direct memory access (DMA) generally refers to a method of
sharing common memory on a single common bus (fig 2). This
requires that only one device at a time use the bus. This is a more
efficient approach than having the CPU be responsible for all data
transfers on a bus, since that usually requires multiple transfers on
the bus for any data item moved (Le. peripheral to CPU then CPU to
memory). If the fraction of time spent in accessing peripherals is
not large then this conventional DMA approach may be
economical. The conventional DMA approach becomes limiting,
as the fraction of time that each device needs to spend on a bus
increases. This approach to DMA is completely inappropriate for
© 1989 Integrated Device Technology, Inc.
DUAL-PORT TRANSFER SPEED ADVANTAGE
OVER TIME-SHARED RAM
We will use a hypothetical, but realistic, case to examine the
advantages of dual-ported memory over time shared RAM. Radar
digital signal processing systems frequently use mUlti-port RAMs
to act as a "rate-buffer". The multi-port is located between the
analog-ta-digital convertors, which must sample the incoming
signals at a constant high rate, and the signal processing
elements. The signal processors, in general, must access data
from the incoming stream in a non-sequential way and this makes
a hardware FIFO inappropriate for this task of rate buffering.
S14-63
Printed In the U.S.A.
01/89
APPLICATION NOTE AN-25
THE KEY ADVANTAGES OF MULTI-PORT STATIC RAM
CPU OR
PERIPHERAL
COMMON
MEMORY
1
p
r
CPU OR
PERIPHERAL
LJ
L
ADDRESS
DATA
LOCAL
MEMORY
[
~
CPU OR
PERIPHERAL
1[
I-
ADDRESS
I-
TIME SLICED
MEMORY
lO [
CPU OR
PERIPHERAL
'1U L
~
r-~
II:
II:
0
I--
::>
~
DATA
I
01---CI)
CI)
::>
....
LOCAL
MEMORY
~
r--cn
II:
rei)
~
W
>
w
U
x
CI)
II:
w
>
w
U
x
r--
CI)
::>
::>
~
~
Figure 2. Two Members of a Hierarchy of Memory Based Communications. Common Memory With a Common
Bus, Shared RAM with Separate Busses.
Assume that the minimum write access time on the side of the
NO convertor is 35ns and the read access time Is 35ns on the
signal processor side. The signal processor works on one data set
of N words then switches to another. The signal processors
accesses are random within a data set. The NO convertor outputs
data continuously In a word-serial stream that wraps around when
it reaches the end of the RAM. The two sides never need to
simultaneously access the same location.
A dual-port memory handles this communications task
painlessly. To better see what the dual-port advantages are we will
look at two possible alternatives. A time-sliced single RAM, and a
ping-pong multiple RAM arrangement. Both approaches Involve
more hardware, more design-in time, and create more severe
timing constraints than a multi-port memory. Both, we will see, limit
the generality of the algorithms that may executed.
In order to begin to meet the basic timing requirements of our
radar OSP system, the RAM in a time-sliced RAM system must
have an access time at least half that of the equivalent dual-port.
This Is due to the fact that the RAM must do two accesses in the
same time as the dual-port. The buffers required for address and
data bus Isolation In a real deSign, will have basic prop-delays of
about 6.5ns. For the read path this would add 6.5 + 6.5 ns to the
read cycle time. Thus before considering signal skews the basic
RAM access times required would be less than 35/2-6.5ns-6.5ns or
4.5ns versus 35ns for a dual-port RAM.
SYNCHRONIZATION AND ALGORITHMIC
CONSTRAINTS OF THE TIME-SLICED RAM
The time-sliced example shows us that the dual-port has more
than twice the effective data communications bandwidth of a
real-world time sliced RAM arrangement for any given RAM speed
grade. The time-sliced arrangement also places serious constraints on the algorithms that can be run. To match the transfer rate
of the dual-port, the reads and writes In the time-sliced RAM must
now be Interlaced one to one and thus must occur at the same rate.
If reads cannot be cleanly interlaced with writes then the transfer
rate may become grossly slower.
S14-64
APPLICATION NOTE AN-25
THE KEY ADVANTAGES OF MULTI-PORT STATIC RAM
CI)
CI)
A~
w
«
«
0
a:
o
o
•
PING-PONG
RAM #2
Ci)
I-
a:
w
>
«
i
-a:
0
CI)
-
:>
~
,
w
~
()
CI)
I
CI)
-
:>
III
(i)
a:
w
>
w
()
X
III
III
-----
..
PING-PONG
RAM #2
r0CI)
a:
w
->
a:
0
"
-
CI)
:>
~
'""(i)
a:
w
>
~ ~
\
'Ci)
-a:
0
CI)
:>
~
'(i)
a:
a:
w
w
>
w
~ '~
()
x
,
0
:>
:>
\
a:
CI)
'----
!
>
~~
a:
x
a:
w
Ci)
>
w
~~
'U)
CI)
>
w
.'
()
x
CI)
:>
:>
~
~
~~ ~ ~
~ ~~
Figure 3. A RAM Ping-Pong RAM. This Arrangement Can be Expanded Indefinitely to Provide Any Number of Independent Sets~
DUAL-PORT RAM TRANSFER SPEED
ADVANTAGES OVER THE PING-PONG
RAM APPROACH
In order to begin to meet the basic timing requirements of our
radar DSP system, the RAM in a ping-pong system (figure 3) must
also have an access time that is less than that of the equivalent
dual-port. Again in a real-world design, the buffers required for
address and data bus isolation will have basic prop-delays of
about 6.5ns best case. For the read path this would add
6.5ns + 6.5ns to the read access time. The basic RAM access times
required would be less than 35 -6.5 ns-6.5 ns or 22ns.
SYNCHRONIZATION AND ALGORITHMIC
CONSTRAINTS OF THE PING-PONG APPROACH
The same kinds of algorithmic constraints are introduced by a
ping-pong schemes, but they are less severe than the time-sliced
single RAM. In a ping-pong scheme, two or more RAMs are used.
In the signal processing scheme, blocks of data are written
altemately to one RAM and then the other. Simultaneous accesses
are now allowed if they are to different physical RAMs. A two RAM
ping-pong scheme could serve the RADAR signal processing
example relatively well, if it can operate on only two data sets
altemately. One RAM can be accessed at rates appropriate for the
A to D convertor, and the other RAM can be accessed at rates
appropriate for the signal processor.
If there are more than two datasets involved in the algorithm, we
again have a potential scheduling conflict. One way to conquer this
problem is to add yet more independent RAMs, One allocated to
each dataset or block required by the overall machine algorithm.
Each time we add an additional RAM, the algorithmic flexibility of
the ping-pong communications link improves, until it approaches
that of dual port RAM.
At this point it becomes apparent that we have created a
spectrum of memory based communications devices. We can
identify the members of this spectrum by the number of fully
independent RAM blocks we can access. For example, a two RAM
ping-pong arrangement, a three RAM ping-pong arrangement. By
this numbering scheme a 1K dual-port is an order one-thousand
device. It has one-thousand one word data sets 999 of which can
be freely accessed at any time from one side. The order three
pin-pong device has three multi-word data sets two of which can
be freely accessed at any time from one side. The order two
ping-pong device has two multi-word data sets one of which can
be freely accessed at any time from One side. The time sliced RAM
is an order 1 device and cannot allow any simultaneous accesses.
S14-65
m
j
APPLICATION NOTE AN-25
THE KEY ADVANTAGES OF MULTI-PORT STATIC RAM
In this discussion we have Ignored the size of the Individual
RAMs, and In fact there are no advantages to using large Individual
RAMs In a ping-pong arrangement as long as the total number of
words available remains the same. In a ping-pong arrangement the
physical RAM sizes determine the maximum data block size. This,
again, reduces the number of algorithms that can be run without
conflicts. In a dual-port, the data block size is a software variable. It
is possible to define any number of arbitrarily sized data blocks for
transfer in either direction. In general, hardware synchronization
per se Is not required, only data block synchronization.
DATA BLOCK SYNCHRONIZATION AND
DATA COHERENCY IN TIME OR CONTEXT
A dual-port video Interface Is an example of a system where
strict data-coherency in time Is not required. It Is usually not critical
that a pixel be updated at a precise instant In time. An update can
be made on one scan or the next If there Is a timing conflict.
However, data corruption In the RAM must be avoided.
The video example Is a special case. In most data processing
environments, however, all data written to memory has to be read
again with perfect fidelity both In data content and In coherency in
time or context. A reading device must know not only what data
was written but it must also know its exact context or meaning. In
any common memory system it is possible for data to be changed
in a location with out 'informing' all of the devices using the data.
So a mechanism must exist for updating the context of data for all
devices using data from shared locations.
The passing of context or time information is usually done by
semaphores or Interrupts. This information synchronizes datablock transfers and, consequently, prevents simultaneous
accesses to any location. Data writes and reads may be
asynchronous from each other in timing of Individual accesses, but
the reading of a block of data does not begin until a block of data
has been written and Its context is known.
The importance of observing that data-coherencyin-time has to
be guaranteed In software, in a particular system, is that it often
eases the hardware design. For example, "busy" arbitration logic
can be used to prevent simultaneous accesses to a Single location.
Busy logic might appear to be an essential feature of dual-port
RAM systems. However, an active busy signal coming on a
S14-66
dual-port usually indicates that something has gone wrong in
software or hardware. In any system where strict data
coherency-In-time or context is required, i.e. the transfer is
block-synchronous, simultaneous accesses to one physical
location cannot be allowed because the outcome Is not
deterministic. (Simultaneous write-read access to one address can
be allowed in synchronous systems if timing Is done correctly).
TRANSFER ALGORITHMS
Having established that In general purpose computing
environments data is normally passed In a block synchronous
fashion it Is useful to classify some common block transfer
algorithms.
1. First-In-first-out (FIFO) buffer Word serial entry, word serial
output in the same sequence.
2. Last-in-first-out (LIFO) buffer or stack Word serial entry, word
serial output In reverse sequence.
3. Random input, random output buffers
4. Word Serial input/output, random outpuVinput
Any of these algorithms can be run with any of the common
memory schemes discussed. The dual-port solution will generally
be faster, easier to Implement, and much 13SS confining in
utilization.
As a simple illustration of dual-port flexibility, consider the fact
that a FIFO algorithm could be executed with a hardware FIFO.
Using a dual-port RAM, instead, would allow any number of FIFO
algorithms to run simultaneously in both directions, along with
other types of transfers.
SUMMARY
Single-chip dual-port memory offers greater data transfer rates,
easier hardware design, and greater flexibility of application than
any competing approach. It facilitates rate-buffering between
hardware devices and allows bidirectional transfer. It's intrinsically
separate address and data busses make it far faster than
conventional approaches to DMA for peripheral-ta-CPU data
transfer. The application of dual-ported static RAM has seen rapid
growth as multiple sources have become available, assuring that
multi-ported static RAM will become a mainstream product.
APPLICATION
NOTE
AN-26
INTERRUPT LATENCY
AND HANDLING
IN THE IDT79R3000
By Satyanarayana Slmha
the instruction causing the exception and also aborts all those
following in the exception pipeline which have already begun
execution. The R3000 then performs a direct jump into a
designated exception handler routine.
When an exception occurs, the R3000 loads the EPC (Exception
Program Counter) with an. appropriate restart location where
execution may resume after the exception has been serviced. The
restart location In the EPC is the address of the Instruction causing
the exception. If the exception occurred in a branch delay slot, the
EPC contains the address of the branch instruction immediately
preceding the delay slot.
.
INTRODUCTION
The exception processing capability of the ID179R3000 is
provided to assure an orderly transfer of control from an executing
program to the supervisor program. Exceptions may be broadly
~ivided into two categories: those caused by an Instruction,
Including an unusual condition arising during Its execution, and
those caused by external events such as interrupts. When an
ID179R3000 detects an exception, the normal sequence of
instruction is suspended; the processor exits User mode and is
forced to the Kernel mode where it can respond to the abnormal or
asynchronous event. This paper presents an overall view of the
ty~ of exceptions in the R3000 and the exception handling
registers. It then describes one specific exception, namely
Interrupts, the latency associated with it and gives an example of
code on how to handle an interrupt event.
EXCEPTION HANDLING REGISTERS
The system coprocessor (CPO) registe'rs contain information .
pertinent to exception processing. Software can· examine these
registers during exception processing to determine such things as
the cause of an exception, and the state of the CPU at the time of an
excepti~n. ~ere are six registers handling exception processing
(shown In Figure 1). These are the cause register, the EPC register,
the Status register, the BadVAddr register, the Context register,
and the Prld register. A brief description of each follows. ..... .
EXCEPTION PROCESSING
The R3000's exception handling system efficiently handles
machine exceptions, Including Translation Lookaside Buffer (TLB)
misses, arithmetic overflOWS, I/O interrupts, system calls,
breakpoints, reset, and coprocessor unusable conditions. All of
these events interrupt the normal execution flow. The R3000 aborts
I
STATUS
I
ENTRYHI
I
CAUSE
ENTRYLO
II
'I
i;:::::Z:X:;i;::~~:::~::~:;:;:";;::::::;;:X;;;::::;S::~~
EPC
INDEX
RANDOM
CONTEXT
63
BADVA
I
I
~
I
PRLO
Figure 1. The Exception Handling Registers
The Cause Register:
The contents' of this register describe the last exception. A 4-bit
exception code indicates the cause. The remaining fields contain
detailed information specific to certain exceptions. All bits in this
© 19811 Integrated Device Technology, Inc.
S14-67
register with the exception of the Sw bits are read-only. The SWbits
can be written into in order to set or reset software interrupts. See
Figure 2 . '
.
Printed In the U.S.A.
01/89
INTERRUPT LATENCY AND HANDLING IN THE IDT79R3000
'APPLICATION NOTE AN-26
o
31
2
12
2
6
BD : Branch delay.
2
4
2
ExcCode : Exception Code Field
CE : Coprocessor Error
: Reserved
IP : Interrupts Pending
Sw : Software Interrupts*
*: Read and Write. The rest are Read-only
Figure 2. The Cause Register
The EPC (Exception Program Counter) Register:
Context Register:
The 32-bit register contains the address where processing can
resume after an exception has been serviced. This register
contains the virtual address of the Instruction that caused the
exception. When the virtual address of the Instruction resides In a
branch delay slot, the EPC contains the virtual address of the
instruction immediately preceding - which is the Branch or Jump
Instructions.
The Context register duplicates some of the Information in the
BadVAddr register, but provides the information In a form that may
be more useful for a software TLB exception handler.
The Status Register:
This register contains all the major status bits. Any exception
puts the system in Kemel mode. All bltsln the status register, with
the exception of the TS (TLB shutdown) bit are readable and
writeable; the TS bit is read-only. Figure 3 shows the functionality
of the various bits in the status register.
Bad VAddr Register:
The Bad VAddr register saves the entire bad virtual address for
any addressing exception.
4
5
8
CU : Coprocessor Usability
2
IntMask : Interrupt Mask
BEV : Bootstrap Exception vector
KUo : Kemel/User mode, old
TS : TLB shutdown
lEo: Interrupt enable, old
PE : Parity Error
KUp : Kemel/User mode, previous
CM : Cache Miss
IEp : Interrupt enable, previous
PZ : Parity Zero
KUc : Kemel/User mode, current
SwC : Swap Caches
IEc : Interrupt enable, current
IsC : Isolate Cache
0: Reserved
Figure 3. The Status Register
Processor Revision Identifier Register:
LATENCY FOR EXCEPTION PROCESSING
This 32-blt register contains Information that identifies the
Implementation and revision level of the Processor and System
Control Co-Processor.
Different types of exceptions can occur in different stages of the
pipeline. The exception handling routine itself occurs after a one
cycle latency. The R3000 has a five stage pipeline that consists of
instruct/on fetch, instruction decode, ALU operation, cache fetch,
and the write-back staga-; Table 1 shows in the last column the
number of instructions in the pipeline that need to be flushed on an
exception. Address error, for example, can have a maximum
latency of four if it occurs on a memory operation cycle. This is
because four instructions in the pipeline stage have to be fiushed.
EXCEPTION VECTOR LOCATIONS
The R3000 uses three different addresses for exception vectors:
• The RESET exception vector is at address OxbfcOOOOO,
• The UTLB Miss exception vector at address OxBOOOOOO
• The General exception vector for all other exceptions at address
OxBOOOOOBO
514-68
INTERRUPT LATENCY AND HANDLING IN THE IDT79R3000
Error
APPLICATION NOTE AN-26
Figure 4 shows the pipeline stages in the R3000. The different
stages are 1:lnstructlon fetch; R:Read Decode; A:ALU operation;
M:Memory operation; and W:Write-Sack. When there is an
exception on an instruction fetch cycle, the exception routine starts
executing one clock cycle later as shown.
Pipeline stages
to be flushed
Pipeline stage
Illegal Instruction
Instruction Decode
2
Address Error
Memory Operation
4
Interrupts
Instruction Fetch
3
Overllow
ALU Operation
3
TLB Miss
Instruction Decode
2
Table 1. Latency in the R3000 on an exception
I
I
R
I
ICACHE
I
\
~
IDEC I
RF
I
IA
I
\ICACHE
I
A
I
OP
DA
I
I
r
\
~
M
I
DCACHE
I
IDEC
I
OP
RF
I
DA
IA
W
RW
I
.1
1
1 DCACHE I
RW\
1
ICACHE
IDEC
1
OP
1
DA
RF
IA
1
1
1
Figure 4. Pipeline Stages in the R3000
useful for selecting the proper static RAM parts for interface
considerations. The interrupts are level-sensitive. They continue to
be sampled during phase 2 of the clock cycle after an interrupt
exception has occurred. The interrupts are not latched within the
processor when an interrupt exception occurs. Since the interrupts
are not sampled during stall cycles, BusErr* can be asserted and
used for exception processing. This is useful in cases where there
is a need to abort from a stall mode.
INTERRUPTS IN THE IDT79R3000
The R3000 processor has six general purpose hardware
interrupts and two software generated interrupts. The hardware
interrupts are sampled during phase 2 of all run and fixup clock
cycles. This is shown in Figure 5. tDS is the data setup time, tHLD is
the data hold time and tSMP is the phase delay between the
Clk2xSmp input and the Clk2xPhi input. These two clock inputs are
part of the four phase clock inputs given to the processor and are
RUN
FIXUP
PHASE 1
I
Int*_ _ _ _ _
PHASE 2
PHASE 1
I
PHASE 2
~~'--------~=
~ tDS~
-1
~DH
-l tSMPr
Figure 5. Interrupt Timing Diagram
S14-69
INTERRUPT LATENCY AND HANDLING IN THE IDT79R3000
APPLICATION NOTE AN-26
shows which of the six hardware interrupts are pending and the SW
field in the Cause register shows which of the two software
interrupts are pending. Multiple interrupts can be pending at one
time.
When the interrupt occurs, the KUp, IEp, KUc and IEc bits of the
Status register are saved in the KUo, lEo, KUp, IEp bit field in the
Status register. The current kemel status bit KUc and the interrupt
bit IEc are cleared. See Figure 6. This masks all the interrupts.
Each of the eight interrupts can be individually masked by
clearing the corresponding bit in the IntMask field of the Status
Register. All eight of the interrupts can be masked at once by
clearing the IEc bit in the Status Register.
INTERRUPT HANDLING
The R3000 branches to the general exception vector at address
OxBOOOOOBO for the exception. The R3000 sets the Int code in the
Cause Register's ExcCode field. The IP field in the Cause register
Figure 6. Kernel Status and Interrupt Status Are Saved on Interrupts
cleared by setting the corresponding bits (SW1 :0) in the Cause
register to zero. A flow chart of a general exception routine handler
is shown in Figure 7.
INTERRUPT SERVICING
In case of an hardware interrupt, the interrupt must be cleared by
deasserting the interrupt line. This has to be done by alleviating the
conditions that caused the interrupt. Software interrupts have to be
Figure 7. Flow Chart for exception Handling
An example piece of code is given below in Figure B. It illustrates
a simple service routine that the processor branches to on
detecting an interrupt. The actual interrupt handling code itself will
depend on the user's application and, therefore, is not given. (an
and sn are registers in the R3000.)
As soon as the branch to the address is taken on an interrupt, the
exception program counter is saved. Line 2 indicates the reading
of the cause register to determine the exception (in this case an
interrupt). The status register is saved to be restored after
processing the exception. A lookup table contains the addresses
of all the different exception processing routines. A jump is taken to
the appropriate exception routine.
1.
mfcO
aO,EPC
;save exception PC
2.
mfcO
a3,CO_CAUSE
;get CAUSE register
3.
mfcO
;save status register
sO,CO_STATUS
S14-70
APPLICATION NOTE AN-26
INTERRUPT LATENCY AND HANDLING IN THE IDT79R3000
4.
5.
and
Iw
8.
a2,causevec(a1)
;get entry to
;register a2 with address
in look up table
;jump to service routine
(line 7)
a2
6.
7. intr:
a1,a3,CAUSE_EXC_MASK
index into look up table
and
a4,aO,INT_CAUSE ;Ioad interrupt level in
register
Iw
t1,int_level(a4)
9.
mtcO
12.
rfe
mtcO
aO,EPC
sO, CO_STATUS
;restore status register to
previous value
;restore status and
interrupts prior to
exception exit
Figure 8: Interrupt Service Routine Example
Figure 9 illustrates a simplistic block diagram of an R3000 board
with the interrupt lines connected to a PAL device. The PALIogic is
designed to affect the R3000 run-time behavior and it defines the
state of the interrupt lines during Reset. Accordingly, the R3000
can be initialized to work as a big-end ian or a little-endian
processor, its block refill rate can be varied, etc.
; index into interrupt level
'n' routine.
;go to interrupt routine for
level 'n'
;return from interrupt
routine
t1
10.
11.
R3000
EXTERNAL
RESET
Rst* 1+------'---------.---1
IntO-lnt5*
a:
MUX
w
I-
sa
faa:
SysOut*
INT~RRUPT
Figure 9: Block Diagram of Interrupt Controller on Reset
CONCLUSION
The IDT79R3000 provides both flexible and fast exception
handling capability. Once an exception occurs, the first instruction
of the exception handler routine is fetched on the very next clock
cycle, providing minimal latency. Management of the processor
and system state is left to the exception handling software, allowing
the system designer to determine what must be done to respond to
a given exception and thus minimizing the amount of processor
overhead required to handle exceptions. Even the prioritization of
the external interrupts is under software control, providing the
system designer with maximum flexibility in the target system*.
*Note: Chapter 5 of the "MIPS RISC Architecture" Book, available
from lOT, contains further detail on exception proceSSing of the
79R3000.
S14-71
.t;)
Integrated Dev1ce1echnology.1nc.
CACHE DESIGN
CONSIDERATIONS
USING THE lOT 79R3000
APPLICATION
NOTE
AN-27
By Satyanarayana Slmha
INTRODUCTION
however, to know the critical timing parameters goveming the
design of a cache subsystem. This article is divided into three
parts. The first part shows a general cache system with a
description of the clock inputs. The second section details the
equations used to calculate the critical parameters. It is followed by
an example of an ID17198 static RAM used as a cache RAM for the
R3000.
The reduced instruction set computer (RISC), the ID179R3000,
has allowed for simplicity in hardware and synergy between
architecture and compliers. To further Increase the throughput of a
computer system, direct-mapped cache memory is Implemented
on systems using the R3000. The availability of a wide variety of
high-speed static RAMs from IDT gives the designer the flexibility
of selecting the proper part for his application. It is necessary,
CACHE DESIGN
Figure 1. 64KB Instruction/Data Cache Configuration
. A Si~plistiC block diagram implementation of a 64KB separate
Instruction cache and data cache is shown in Figure 1. The design
of a cache subsystem such as the one above depends on the four
input clocks to the R3000 processor. These clock inputs are twice
t~e. frequency of the output clock Le., SysOut. By adjusting the
. timings of these clocks, the designer can accommodate a wide
variety of static RAMs by properly considering specific parameters
such as set-up and hold times. The clocks themselves can be
adjusted using tap settings on a delay line or by using delay logic.
The clock inputs are described below.
1) Clk2xSyS: Determines the position of SysOut with respect to the
data, tag, and address buses. It is positioned so that devices in
© 1989 Integrated Device Technology. Inc.
the cache/bus interface clocked by SysOut meet the set-up and
hold time requirements.
2) Clk2xSmp: Is used by the R3000 to capture external data onto
data bus and control inputs.
3) Clk2xRd: Is used to delay the enable of data bus drivers .
4) Clk2xPhi: Is used to determine all R3000 outputs Le., data,
address, and tag buses.
Figure 2 shows the timing relationships between the four clocks.
All t~e ti~ing equations for cache design depend on the phase
relationship between these clocks. Tsmp is the Clk2xSmp to
Clk2xPhi delay, Trd is the Clk2xRd to Clk2xPhi delay, and Tsys is
the Clk2xSys to Clk2xPhi delay.
S14-72
Printed In the U.S.A.
01/89
APPLICATION NOTE AN·27
CACHE DESIGN CONSIDERATIONS USING THE IDT79R3000
CLK2xAD
I
I
I
I
-ilrTRdl~
~_~S--+ll
'I::=_tCYcl2_--1_tCYC _ _
Figure 2. Timing Relationships Between the Four 2x Clock Inputs
In the cache implementation scheme, instruction references
begin their reference during phase 2 and transfer data during the
following phase 1. Data references begin during phase 1 and
transfer data during phase 2. Thus, data and instruction references
can take place In different phases of the same clock cycle. See
Figures 3a and 3b. This is an Importantfactorto consider in order to
prevent contention between instruction and data caches.
Figure 3a. Data and Instruction Caches During Phase 1
S14-73
APPLICATION NOTE AN-27
CACHE DESIGN CONSIDERATIONS USING THE 1DT79R3000
Figure 3b. Data and Instruction Caches During Phase 2
Specific factors such as access time, set-up time, hold time,
enable and disable times, and the deration factor are key In
choosing the proper static RAM and in setting the phase delays in
the clocks. The next section discusses the timing equations
needed for selecting a static RAM for cache design.
Read Write I-Cache Data Bus Contention: This timing parameter
requirement guarantees that no contention will occur between the
instruction cache and the processor on a store.
RAMHZ $; tsys - Rdd
Equations Governing the Critical Parameters in
RAM Selection:
Figure 4 shows the timing of the relevant signals for a 25MHz
(40ns) R3000. The numbers represent the equations that are
critical in determining the selection of the static RAMs. The timing
is given for the worst case condition I.e., a STORE followed by a
LOAD. An explanation of the equations is given below.
Internal Sample to Phi: This timing parameter requirement
guarantees that the processor internal sample to Phi is met.
tsmp ~ 5ns
..; ~E::'--':-:-;---------------(1)
Address Access to Data Sample: This timing parameter
requirement guarantees that the cache RAMs have sufficient
access time. This calculation assumes that the address delay
through the FCT373 is limited by its propagation delay.
RAM~ $; teye - tsmp - AdrLod*- 373PD - tos --- (2)
Cache Enable to Sample: This timing parameter requirement
guarantees that the cache RAMs are enabled soon enough to meet
the processor's input set-up specification.
RAMOEd~ Tcye/2 - tsmp-rd - Rdd - tos -------
(3)
Minimum Read Pulse Width: This timing parameter requirement
guarantees that the read pulse generated by the processor is at
least as long as the cache RAM output enable time.
RAMdOE $; teye/2 - tsys-rd
---------------
+ Den
-----
(5)
Processor Data Set-up to End of Write: This timing parameter
requirement guarantees that the cache RAMs have adequate data
set-up time when being written into by the processor.
RAMSD :S teye/2 - tsmp - DVal d + Wr d ----(6)
Data Hold from End of Write: This timing parameter requirement
guarantees that the data hold from end of write specification of the
cache RAMs is met when either the processor or the read buffer is
writing to the RAMs.
RA~-RA~
m
s~~
Data Set-Up to SysClk: This timing parameter requirement
guarantees that the set-up time into an external register is met on a
processor store.
SetUpsys $; teye/2 - tsys - (DVal d + - Sysd - 240PD)-- (8)
Data Hold from SysClk: This guarantees that the hold time
specification of an external register is met on a processor store.
The data holds on the bus until a subsequent read drives new data.
Holdsys
~ t~ys-rd -
Sysd - 240PD
+ RAMLZ+
Rdd - (9)
Equations 1 to 9 are sufficient for the purpose of selecting the
proper RAMs for use as cache memory. To illustrate the point
further, an lOT RAM device, the I0T7198 (16K x 4), is chosen as an
example.
(4)
*d: Deration due to additional load. 1ns per 25pF.
S14-74
APPLICATION NOTE AN-27
CACHE DESIGN CONSIDERATIONS USING THE IDT79R3000
phi
phi
phi
FETCH (phase 1)
STORE (phase 2)
AdrLo
"Y
IAdr
Y
'"
DAdr
"/
V
/~~--------~/~~--------~
~
samp
RAMout
..
.----)
(READ:
.....
~"""""""""""""""""""""""""","'~
rd
'"""'"
I in
[1J
.....
-""'-
.
"
"",""""""""':~
/"""""".""""'"",,",7
""" """ """ "'" "'" """.""'" "." """ """ "'" "";;:-"""
.....
.....
.....
•
U1
QJ
IRd*__-;~______________________~:~~t-----ir---------------~~~~~:t::::::::::~:t_
~RITE:
)
samp
~
____' - ____________J
/V
CPUout
A"'"""."'","'","',,,'~
~",""""","","'","~
3
Dout
r.vrDly
........
u:J..
• c::z::J
--i ,.---:-:+_ _- I -_ _ _ _~I---....+_----..
DWr_*~r------------J/
..... [::II ........
.....
. ......
".
\~~_~\,~~--
SysClk*
Figure 4.IDTR3000 40"5 (2SMHz) Cycle Timing
Deration Calculations:
CALCULATION OF TIMING PARAMETERS
An example of a cache subsystem design using an IDT7198 i.e.,
a 16 K x 4 static RAM follows. All the numbers used in the
calculations have been taken from the IDT Data Book 1 and the
R3000 Interface Manual. The numbers are presented in Figure 6.
The deration factor has been taken Into account for DIPs. Surface
mount would decrease the deration factor.
The following factors have been taken into account for
calculating the deration factor 2 •
1) The SSllogic and cache RAM propagation delays are derated
by 1ns per 25pF of additional load.
2) Cache RAM input capacitance is 5pF.
3) Cache RAM output capacitance is 7pF.
4) Trace capacitance is estimated at 2pF per inch.
5) Data and trace tag buses are 6 inches.
6) Address buses are 2 x 5 inches.
7) SysOut loading is 50pF.
8) Test value of 30pF to be subtracted.
Address Capacitance: 12 x 2pF = 24pF; (factors 4,5, and 6) 5
Devices = 5 x 10pF = 50pF; Test value = -3OpF; Total
capacitance = 45pF; At 1ns per 25pF, total deration of address
bus = 2ns.
Data Bus Deration: Is approximately the same I.e., 2ns. Read
control capacitance for IDT7198 will be about 10 inches of trace
and 8 devices at 7pF each. Therefore, Read control deration =
(76-30)pF/25pF/ns = 2ns.
In Figure 5, the circled numbers are the equations previously
described. The number in parentheses is the allowable worst case
timing. The adjacent number is the total time taken using the
IDT7198. The numbers for the IDT7198 with the R3000 running at
different frequencies and the FCT373A are shown in Table 1 and
Table 2 respectively.
The first value for each parameter in Table 1 shows the
maximum allowable worst case rating and the second value shows
the timing using the IDT7198 RAM.
S14-75
iII
~
o):o
:J:
m
c
phi
en
phi
STORE (phase 2)
tJ
m
FETCH (phase 1)
.•'--J
o Adr
IAdr
AdrLo
2
5.2
AdrLo
19+2
d
+373 po+ RAM
d
AA
6
(READ:)
m»
~rr'f~'~rL'~
'---'-"'-'---'---~'-'---'---~'-""--" '-
2
rd
10+1
Ref
d
m
::0
!t
5 (6)
')).')')')~
1m
.I~~~
6
d
en
c:
en
...:J:
C')
19 (20)
10+1
5z
Z
+RAM OE + os CD
2
18
-1.5
Ref + RAM HZ - Den G::>
RAMOE CD
o
z
en
C
5
samp CD
J
34.2 (34)
RAMout
o
tJ
samp
CD
+ os
is
z
phi
11 (14)
m
C
:j
11.5 (12)
CD
::0
~
~
IRd"
(WRITE:)
"'"
.!.,
samp
I
(I)
CPUout
o out
LL
'-''''''''''''''''2+2
OVal
10
d
~
~
1
o:
+ RAM so - Wr d CD
""-
o
o
o
-.
13(14)
RAM
2
HO •
3
RAM
LZ
WrDly
a:::::>
!+-:no>
,
DWr"
~
(6)
(6)
2+2
d
OVai +
(6)
I
Setup
1
1.5
sys - Sysd_ 240
..
7.5(8)
PO
1
C!:)
I
4.8
'(3)
2
2d
Sysd+ 240 PO + Hold sys - RAM LZ - R"cr::J
•
4.8(6)
-,
):"tJ
"tJ
(6)
SysClk"
r
sys
sys
(0)
(0)
(12)
Figure 5: IDT79R3000 40 ns cycle timing using an IDT 7198 SRAM.
o
~
5
z
z
...
o
.m
I~
APPLICATION NOTE AN-27
CACHE DESIGN CONSIDERATIONS USING THE IDT79R3000
R3000 Clock Frequencies
Load
(pF)
Symbol
Address to Data Valid
30
tM
Output enable to Data Valid
30
tOOE
Parameter
Output Disable time
tHZ
Output Enable Time
ttz
Address SetUp to End of Write
tAW
Data SetUp to End of Write
tos
Min.
(ns)
tPWE
Write Pulse Width
Data Hold from End of Write
tHO
Address Hold from End of Write
16MHz
Max.
(ns)
Min.
(ns)
20MHz
Max.
(ns)
Min.
(ns)
25MHz
Max.
(ns)
31
25
19
29
25
19
17
13
10
15
13
10
14
12
12
10
2
8
7
2
2
2
5
5
5
43
36
27
20
20
13
14
13
11
13
13
8
55
47
37
20
20
13
0
0
0
0
0
0
0
0
0
0
0
0
tHA
Table 1. Cache RAM Parameters. RAM Specifications vs.IDT7198 Specifications.
Load
(Units)
Parameter
Symbol
Min.
(ns)
Max.
(ns)
8.5
FCT373A Propagation Delay
50
t373 PO
FCT373A Latch Enable Delay
50
t:373LE
2
FCT373A Latch Enable Hold
50
t373 Hid
1.8
FCT240A Prop Delay
50
t240PO
1.5
5.2
4.8
Table 2. Parameters for Latches and Buffers
Figure 6 shows a block diagram oftap settings on a delay line for
the four clock input signals. By varying the phase delay between
these signals, the designer can select the proper static RAMs for
cache memories and the operating frequency of the R3000. Table
3 shows suggested tap settings on the delay line for the R3000
running at different frequencies.
Clk2xsys
CIk2xSmp,
CIk2xRd
Clk2xPhi
' 16.67MHz
20MHz
Clk2xSys
0
0
0
6
6
6
Clk2xSmp
6
6
6
CIk2xPhi
16
14
12
The lOT R3000 RiSe processor allows an ,efficient cache system
to be implemented with standard architecture static RAMs. To
design a cache subsystem, it is essential to know only the critical
equations mentioned above and their relation to the four input
clocks. The tap settings provide further Control of the cache
subsystem design for different operating frequencies of the R3000.
1. lOT Data B60k, pp 4-74 -- 4-83, pp 10-72 -- 10-75.
2. MIPS R3000 Processor Interface Manual, pp 105.
*d: deration due to additional load. 1 ns per 25 pF.
25M Hz
Clk2xAd
CONCLUSION
REFERENCES
Figure 6. Tap Settings for the Clock Inputs
Parameter
The designer can use a DDU-7F-20* chip for the delay line. The
clock is the input to the device and the outputs at various points can
be chosen with the appropriate phase delays.
*Avallable from Data Delay Devices (201) n2-1106
Table 3. Delay Une Setting Summarization
S14-n
..
__ ._---_ ....
_--_.... .. _----_.._--"-_ ..- - - - - - - - - - - - _""
..,,
APPLICATION
NOTE
AN-28
, USING THE IDT79R3000
IN A MULTIPROCESSOR
ORGANIZATION
By Roy M. Johnson
,applications note discusses the features of shared memory
multiprocessor architectures with local caches, examines the
critical Issue of cache coherency, and demonstrates' how the
features of the IDT79R3000 facilitate its use in a shared memory
multiprocessor system.
INTRODUCTION
High performance systems, such as shared memory
multiprocessor architectures, can be built using IDT79R3000 RISC
processors. The IDT79R3000 Incorporates special features that
provide support for multiprocessor environments. This
PROCESSOR 1
PROCESSOR N
PROCESSOR 2
LOCAL
CACHE
LOCAL
CACHE
LO CAL
CACHE
:I
INTERCONNECTION NElWORK
:11:1:11::I~illI11:imll:
mmmIT
MEMORY
MODULE 2
MEMORY
MODULE 1
::,',::::i:::::,:,I:::I::II:
MEMORY
MODULE M
1/02
h:
Figure 1. Block Diagram of a Shared Memory Multiprocessor System
SHARED MEMORY MULTIPROCESSOR
SYSTEMS
CACHE COHERENCY
A simplified block diagram of a shared memory multiprocessor
with local caches. is shown in Figure 1. This model of a
multiprocessor system is defined to be tightly coupled and the N
processors are connected to M memory modules and P I/O
devices via an Interconnection network. All the processors have a
local cache memory, share the same global address space and
communicate via shared memory. The interconnection network
ensures complete connectivity between the processors and
memory modules and can be implemented as a simple shared
bus, multi-stage delta network or a more complex cross-bar
switch. The global shared address space is assumed to be
interleaved amongst the memory modules in order to minimize
memory access conflicts. Note that the need for a interconnection
network can be obviated by using a multi-port memory [1].
Examples of commercial machines employing a shared memory
multiprocessor configuration using the R2000/3000 RISC
processor Include the Titan Graphics Supercomputer from Ardent
Computers [2] and the 4D-MP Graphics Superworkstation from
Silicon Graphics [3].
© 1988 Integrated Device Technology. Inc.
The presence of local caches in a shared memory
multiprocessor system introduces the Issue of cache coherency
that may result in data inconsistencies. This problem arises
because several copies of the same data may exist In local caches
of different processors at the same time. If one of the processors
modifies (writes) the value of its copy of the data, then the other
processors will have the stale or incorrect copy of the modified data
in their local caches. This Is a potential problem created by
asynchronous parallel algorithms that do not have explicit
synchronization. Data inconsistencies may also arise in
multiprogrammed multiprocessor systems whereby a suspended
process may migrate to another processor and the most recently
updated data of the process might still be in the original
processor's local cache. When the process is run on the new
processor, there is a possibility that stale data is used if the local
cache was not previously flushed. This assumes that the process
did run previously on this processor. It is clear that if data
consistency is to be ensured in a multiprocessor system, cache
coherency must be maintained.
S14-78
Printed In the U.S.A.
01/Ba
USING THE IDT79R3000 IN A
MULTIPROCESSOR ORGANIZATION
IDT79R3000
PROCESSOR 1
APPLICATION NOTE AN·28
IDT79R3000
PROCESSOR 2 .
::::;MPREQUESt:
:;MP;REQUEST
c
I
I CACHE
D CACHE
I CACHE
D CACHE
rr
MEMORY INTERFACE
READ & WRITE BUFFERS
SNOOP
CACHE &
CONTROL.
LOGIC
BUS CONTROL
LOGIC
MEMORY INTERFACE
READ & WRITE BUFFERS
SNOOP
CACHE &
CONTROL'
LOGIC
L
MAIN MEMORY
Figure 2. Block Diagram of a Dua11DT79R3000 Shared Memory Multiprocessor
A static approach to maintain cache coherency is to make all
writeable data that is shared,' non-cacheable. This method ensures
data consistency, but at the price of decreased performance and
with increased main memory conflicts. A dynamic approach to
maintain cache coherency is to allow multiple copies of shared
writeable data to exist and rely on a cache coherence protocol
between the processors to ensure cache consistency. Several
cache coherence protocols have been proposed and
implemented using both hardware [4] and software support [5].
The type of protocol used depends primarily on interconnection
network and the number of processors in the system.
A DUAL IDT79R3000 SHARED MEMORY
MULTIPROCESSOR
A simplified block diagram of a dual IDT79R3000 shared
memory multiprocessor is shown in Figure 2. A simple shared bus
configuration was chosen Jor clarity. The two processors are
connected to the main memory and an I/O device via a common
bus. Access to the shared bus is arbitrated by the bus control logic.
Each processor has an instruction and data cache and
write-through cache update policy is assumed, i.e. all writes to the
cache are also immediately transmitted directly to main memory.
Note that a write-back cache update policy, (writes done only to the
cache and main memory is updated when the cache line is
replaced) would generate less memory traffic [10]. This is usually
implemented when there are more than two processors in the
system. Read and write buffers are. included to provide a
convenient asynchronous interface to the' main memory. The
snoop cache and control logic is used to implement a dynamic
cache coherency check mechanism. For clarity, a very simple
cache coherence protocol is chosen for the dual IDT79R3000
multiprocessor system and is described in detail below (more
sophisticated and efficient schemes are described in [4], [5], [6],
[7] & ~8)).
S14-79
----_._------
------.------- ...
USING THE IDT79R3000 IN A
MULTIPROCESSOR ORGANIZATION
APPLICATION NOTE AN-28
o CACHE
I CACHE
OE*
WE*
DATA TAG
DRD* ::::: .:.:.:.'
DWR*
IRD*
IWR*
:. .
ADDR lO
'
OE*
WE*
TAG DATA
ADDR lO
::::,
.. :::0;::'::.
.... ::::::
.
IDT79R3000
I
1
:.:.:.: .. ::," .:: ':J::.:.::::-"
INVALIDATE
DClK :. I:.... .J TRANSPAREN ..... TRANSPARENT
I,",..
LATCH
:.
LATCH
.
IClK
SYSOUT*hl'Tli: l i:[: il .·:I·']'· r ~ ·: il ·:~: :n·:·m:· m'~!;·'~N~ C~ '~ ID~:~·~TE~· : i·:·
CPCOND(2)
DATA
TAG
.... :T::
CPCOND(3)
ADDR lO
1'1"
1'::111:11:'
,liilillli:::i!':j:I:!il"
ADDRESS
REGISTER
.:> :.
!:'/ : : :
Figure 3. Processor Interface to the Snoop Control logic
CACHE COHERENCE PROTOCOL
Each snoop cache maintains a directory of the current entries in
the local data cache, (I. e. it contains the tags of all the current
entries in the local data Cache). Its primary function is to monitor
the external memory bus for an address match. In addition, the
snoop cache maintains state Information for each data cache line.
A cache (tag) line can be in one of three states: private, shared or
Invalid. Data that is exclusive to the processor Is marked private
data that is common to the processors is marked shared and da~
that Is Inconsistent is marked invalid. The snoop cache Is updated
concurrently with the data cache. Whenever processor 1 modifies
or writes a lin~ that Is marked shared In its local cache, its snoop
control logic signals processor 2 that a write to a shared line has
occurred. The snoop control logic of processor 2 then interrogates
its snoop cache to determine whether a copy of the modified data
is pr~sent in the local data cache. If a copy is present, it is
Invalidated using the MP request and MP invalidate signals as
shown in the Figure 2 and the tag line In the snoop cache of
processor 2 is marked invalid. The snoop control logic of
processor 2 sends an acknowledge Signal to processor 1 which
then proceeds to complete its write operation to the shared
location, I.e. writes into the data cache as well as into the write
buffer. It must be noted that the data value in the write buffer must
be retirec:l to the main memory before the write operation can be
c~mpleted. This prevents possible data inconsistencies that may
anse by processor 2 trying to read that particular main memory
location before it is updated. This cache coherence protocol is also
known as cross-interrogation. Note that this protocol Is applicable
only to cache lines that are marked shared, while writes to cache
lines marked private are performed at the processor speed. In the
event of simultaneous writes to the same shared cache line by both
the processors, only one of the processors will successfully
acquire the external bus (determined by the bus arbitration logic)
to issue a cross-interrogation signal to the other processor. The
write operation of the processor that did not acquire the extemal
bus will result in a write miss. Figure 3 shows a typical processor
interface to the snoop cache and control logic in more detail, and is
also described below.
S14-80
USING THE 1DT79R3000 IN A
MULTIPROCESSOR ORGANIZATION
APPLICATION NOTE AN·28
.,i,:'.
Figure 4. Cache Invalidation Timing Diagram
DYNAMIC CACHE COHERENCY CHECK
MECHANISM
The signals at the snoop logic - processor interface include the
MP request, MP invalidate, processor latch enable, invalidate
latch enable and the invalidate address (address of the cache
location to be invalidated). The snoop logic receives a crossinterrogation signal from the other processor when a write is
performed to a shared cache line. It then searches its tags for an
address match. If a match occurs, the address is captured in the
invalidate address register which is clocked by SysOut*, as shown
in the Figure 3. The CpCond(3) input (MP request signal) of the
ID179R3000 is then asserted, causing the 79R3000 to enter into a
MP stall. As there is no cache activity on the first cycle of an MP
stall, the processor latch enable signal is deasserted and the
invalidate latch enable is asserted in order to presentthe invalidate
address to the data cache. After the first stall cycle, the CPU will
issue DRd* pulses during every phase 2 arid DClk '(COnnected to
the transparent latches) during every phase 1, this lasts until the
end of the stall or until one cycle after the assertion of CpCond(2).
This permits the snoop logic to read the data cache (Data and Tag
values can be sampled by the falling edge of SysOut*) in order to
determine whether an invalidation is to be performed. If the cache
location Is to be invalidated, the MP invalidate signal (connected to
the CpCond(2) input of the 79R3000) is asserted. Invalidation
occurs by the assertion of Dwr* during phase 2 of the stall cycle
with an arbitrary invalid tag and arbitrary data value driven onto the
Tag and Data buses. If CpCond(2) is deasserted while CpCond(3)
is still asserted, the processor will retum to issuing DRd* pulses to
enable data cache reads. The cycle afterCpCond(3) is deasserted
contains no cache activity. This cycle is used to re-enable the
processor's transparent latch and disable the invalidate
transparent latch. A detailed timing diagram of a snapshot of the
S14-81
_. ----_. --_.
-----------_._..._--_ ..... _------_ - - - - - - - - ••
USING THE IDT79R3000 IN A
MULTIPROCESSOR ORGANIZATION
APPLICATION NOTE AN-28
cache invalidation process is shown in Figure 4. This is a modified
version of the timing diagram shown in [11]. Note that Figure 4
shows the minimal timing required. CpCond(2) Is asserted two
cycles after CpCond(3) is asserted and before the first Drd*. This
Implies thatthe data location is Invalidated Irrespective ofthe value
being read. The symbol "cD" denotes that the cache drives the
data and tag buses when CpCond(3) Is asserted. The symbol "pO"
denotes that the processor drives the data and tag buses when
CpCond(2) is asserted. The snoop control logic, at this stage, must
mark the tag line In Its snoop cache as Invalid and send an
acknowledge signal to the other processor. This Indicates that the
cache invalidation is complete. If desired, more sophisticated and
efficient invalidation schemes, such as techniques for block
invalidation, could be implemented.
.
REFERENCES
[1] K. Hwang & F. A. Briggs, Computer Architecture and Parallel
Processing, McGraw-Hili, 1984, pp 459 - 525.
[2] T. Diede et ai, "The Titan Graphics Supercomputer
Architecture", IEEE Computer, Sept. 1988, pp 13 - 30.
[3] F. Baskett, T. Jermoluk & D. Solomon, "The 4D-MP Graphics
Superworkstatlon: Computing + Graphics = 40 MIPS + 40
MFLOPS and 100,000 Lighted Polygons per second", Digest
of Papers, COMPCON, Spring
1988, 33'rd IEEE Computer Society Int. Conference, pp468
- 471.
[4] J. Archibald & J. Baer, "cache Coherence Protocols:
Evaluation Using a Multiprocessor Simulation Model", ACM
Transactions on Computer Systems, Vol. 4, No.4, Nov. 1986,
273 - 298.
pp
SECONDARY CACHE SCHEME
The cache-main memory Interface described above could be
made more efficient by using a system of multi-level caches [9],
[12], to provide additional memory bandwidth. For instance, a
secondary cache that Is four times the size of the first leve~ or
primary cache could be implemented. !he seconda~ cache I~ a
superset of the primary cache and also Includes state Information
to maintain cache coherency. The cache update policy is typically
write-through, from the primary to the secondary ca~he and
write-back from the secondary cache to main memory. Since the
primary cache is always a subset of the secondary cache,
consistent data Is guaranteed. This type of multi-level cache
organization Is implemented in the 4D-MP Graphics
Superworkstation [3] made by Silicon Graphics.
CONCLUSION
Maintaining cache coherency is vital in shared memory
multiprocessors. The Implementation of the cache- main memory
interface and the cache coherency protocol are critical issues. The
IDT79R3000 RISC processor provides features that facilitate the
Implementation of cache coherence check mechanisms with
minimum hardware and is well suited to be used in a shared
memory multiprocessor environment.
S14-82
[5] A. J. Smith, " CPU cache Consistency with Software Support
and Using "One Time Identifiers" ", Technical Report 86/290,
EECS Department, University of California, Berkeley,
California 94720.
"'!'
[6] M. Papamarcos & J. Patel,
Lo~-Overhead Coher~nc.?
Solution for Multiprocessors With Pnvate Cache Memones ,
Proc. 11'th Annuallnt. Symp. on Comp. Arch., June 1984, pp
348 - 354.
[7] L. Rudolph & Z. Segall, "Dynamic Decentralized cache
Schemes for MIMD Parallel Architectures", Proc. 11 'th Annual
Int. Symp. on Comp. Arch., June 1984, pp 340 - 347.
[8] P. Sweazey & A. J. Smith, "A Class of Compatible Cache
Consistency Protocols and their Support by the IEEE
Futurebus", Proc. 13'th Annuallnt. Symp. on Comp. Arch.,
June 1986, pp 414 - 423.
[9] A. J. Smith, "Design of CPU Cache Memories", Proceedings,
IEEE TENCON, Korea, Aug. 1987, pp 1 -10.
[10] A. J. Smith, "cache Memories", ACM Computing Surveys,
Vol. 14, No.3, Sept 1982, pp 474 - 530.
[11] Multi-processor Interface, MIPS R3000 Processor Interface,
MIPS Computer Systems, May 231988, pp 59-61.
[12] S. Przybylski, M. Horowitz & J. Hennessey, "Performance
Tradeoffs in Cache Design", Proc., 15th Annual In1. Symp. on
Compo Arch., June 1988, pp 1 - 18.
t;)
Integrated Device'Jechnology. Inc.
APPLICATION
NOTE
AN-30
THE COMPLETE HIGH
PERFORMANCE CACHE
SYSTEM FOR THE 80386
MICROPROCESSOR
By Mammad A. Safal
stores the main memory page addresses of the data that is stored
in the cache memory. Besides the cache tag and cache memory, a
complete cache system for a microprocessor incorporates; a
cache controller to instigate and respond to local and system bus
states; system and local bus control logic to interface to extemal
system bus masters and the local microprocessor; coherency
logic to assure system coherency in multi-master based systems.
Faster caches include a write buffer to allow for zero wait state
posted writes.
INTRODUCTION
The design of microprocessor systems, teday, requires an
extensive knowledge of the principles of cache controller and
cache memory design-for it is the cache that enables the
microprocessor to achieve its maximum throughput. For example,
the Intel 25MHz 80386 (using main memory DRAMs with a cycle
time of 250ns), without a cache, is rated at 2 MIPs (peak). However,
with a well designed cache, the system performance can reach
12.5 MIPs (peak). Similarly, for the Motorola 68030, the
performance can be increased from 2 MIPs to 10 MIPs (again with
250ns DRAMs as the main memory element).
Besides increasing the throughput of a microprocessor system,
the inclusion of a cache decreases the system bus traffic, making it
an ideal element for use in the design of multiprocessing and
multi-master based systems. A well designed cache for coherent
multiprocessing and multi-master systems.
Central to a cache design, is the coherency architecture
employed. This application note discusses the design of a unique
cache controller which uses two cache tags to achieve coherency.
This dual cache tag design for the 80386 microprocessor offers
greater speed than the more common time multiplexed cache tag
design in addition to simplifying the system bus interface and
timing requirements.
CACHE TIMING PARAMETERS
When designing a cache system using cache tag and data
cache SRAMs, you have to consider the cycle time of the
microprocessor used, the match time of the cache tag and the
access time of the data cache SRAM. For the Intel 80386 (25MHz
verSion), the cycle time is 40n8. This allows nearly 80ns for the
cache tag address to be compared against the microprocessor
address and the data cache SRAM to be accessed (a minimum of
two cycles are required for the read instruction). IDT's cache tag
SRAMs and data cache SRAMs can be used to meet the timing
requirements of most microprocessors. The IDT7174 8K x 8 cache
Tag SRAM features a match time of 20ns (maximum) while IDT's
7164 8K x 8 has a cycle time of 20ns (maximum). When both the
cache memory and cache tag are accessed simultaneously, valid
data can be placed onto the microprocessor address bus in nearly
20ns (address to match time of the cache tag (20ns) is equal to the
access time of the cache memory (20ns) in the above). Here, the
controller will start the cycle as if the data is in the cache memory, if
later during the cycle it was determined that the data is missing
from the cache, the controller will float the I/Os of the cache
memory and accesses the main memory.
CACHE DEFINITION AND OPERATION
A cache may be defined as a high speed memory element that
serves as a high speed memory buffer between slower main
memory and the microprocessor. The design of the cache is such
that it has an effective cycle time that is less than the cycle time of
main memory. This, of course, is because the design of the cache
dictates that the data or code needed most often is usually in the
cache memory.
The cache memory can not be too large in size because of cost
and board space considerations. The main memory will therefore
be divided into pages equal in size to the cache memory size. The
size of a page will depend on the total size of the cache and the
degree of associativity of the cache implementation.
The general operation of a cache based system can be
understood by examining its interaction with the microprocessor
and main memory during program execution. When a
microprocessor issues a 'read instruction, the microprocessor's
address's page field is compared against the page address stored
in the cache tag. If the cache tag page address matches the
microprocessor address's page field, a hit occurs, and the
microprocessor reads the associated data from the data cache
SRAM. On the other hand, if the microprocessor page address is
not in the cache tag a cache miss occurs. In the latter case, the
microprocessor will retrieve the data from main memory and
update the cache memory and cache tag with the required main
memory address and data i.e. a cache read miss cycle.
CACHE ARCHITECTURE OVERVIEW
A cache system consists of a cache memory which may be
divided into two parts; the dictionary or cache tag (a cache tag
SRAM) and the cache memory (a data SRAM). The cache tag
© 1989 Integrated Device Technology. Inc.
EFFECTIVE CYCLE TIME
The effective cycle time of a microprocessor based system is
the average amount of time that is required to access memory. For
a system without a cache, the effective cycle time is equal to the
cycle time of main memory (teday's 1Mbit DRAMs feature cycle
times between 100 and 400ns). However, for a microprocessor
system based on a cache, the effective cycle time is a function of
the cycle time of main memory, the cycle time of the cache and the
hit ratio of the cache, i.e. :
tert = htcache + (1-h)
where
!ert
h
1-h
!maln
tcache
=
!maln
Effective Cycle Time
Hi! Ratio
Miss Ratio
Main Memory Cycle TIme
Cache Cycle Time
A normalized graph showing the effective cycle time for a
varying hit rate with a constant main memory cycle time of 200ns
on a cache that allows zero wait states operation, is given in Figure
1. From the graph, it can be seen how dramatically the hit rate
affects the effective cycle time of the system e.g. for a decrease in
the hit rate from 99% to 89%, the effective cycle time of the cache
will almost double.
S14-83
Printed In the U.S.A.
01/89
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
200
190
180
170
160
150
Effective Cycle Time
ofthe system In ns
140
130
120
110
100
90
80
70
60
50
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Hit Ratio of the System
Figure 1. Effective Cycle Time vs. Hit Rate
CACHE ASSOCIATIVITY
Associativity, the number of unique cache memory banks of a
cache design, is fundamental to the design of a cache system. The
associativity determines the cache architecture, affects, to a
degree, the overall performance of the system, plays a role in the
selection of the replacement algorithm (pertains to the method
used to update the cache memory), and indirectly sets the page
size.
matches the tag 1763X, X refers to an octal digit from 0 to 7. The
data associated with the tag 1763X have addresses from 17630 to
17637. Therefore the address 17635 refers to the sixth element in
that line. The corresponding data is 72.
CACHE MEMORY
TAG
r--t'
Associativity and Cache Architecture
After the designer decides on a cache memory size, he or she
must then decide on the associativity so as to obtain the optimized
cosVperformance ratio. The architecture of the cache memory is
dictated by its associativity. For example, ifthe designer selected a
cache memory size of 32Kbytes, the direct mapped cache
memory will be one 8K bank of 32 bit words. A 32Kbytes two-way
set cache will have two 4K banks of 32 bit words. Finally a 32Kbytes
four way set design will have four 2K banks of 32 bit words.
I
DATA
1763X
4736X
9876X
OOOOX
I - 12,78,90,65,37.72,44.10
4563X
H44.10.20........
Associativity and Mapping Cache To Main Memory
The 80386's 32-bit address field to be viewed as two fields, a
page field (given by the tag) and a line offset field (See Figure 5).
Since the page size of main memory is dictated by the size of the
cache a direct mapped cache with a cache memory size of
32Kbytes will have a main memory page size of 32Kbytes (or 8K
32-Bit words). Since the page size of main memory is the same size
as the cache memory, every address in cache memory directly
maps to the associated line in a page of memory i.e. line 5 of the
cache maps to line 5 of the main memory page (Figure 2). In this
example we will use a line length of 8 bytes. The address 17635
-
~
68.99.56 ........
89.76.35........
~E
I
~
,
Associativity and Page Size
Because of the different architectures for caches of different
associativity, the page size for a given sized cache will vary with the
degree of associativity. For the direct mapped 32Kbytes cache,
given above, the page size will be 8K doublewords. Similarly, the
two-way set associative design will have a page size of 4K
doublewords and the four-way set associative will have a page size
of 2K doublewords. Since the size of the page is smaller for caches
of higher degrees of associativity, the number of main memory
pages will also vary with associativity (See Figure 3).
I - 22.34.35 ........
17635
ADDRESS
72
DATA
Figure 2. Mapping to Main Memory
Since the page size is affected by the associativity of the cache,
the addressing scheme for fixed sizeJcaches of different
associativity will also be affected. As shown in Figure 3, the page
field for a direct mapped cache is 17 bits while the line offset field is
13 bits. This contrasts to a four way set which has a page field of
19 bits and a line offset field of 11 bits.
The addressing scheme for a cache based on the Intel 80386 is
also determined by the size of the cache. If the cache size is
32Kbytes (8K x 32) the 13 LSBs of the 80386 microprocessor
address bus will be needed to address each four byte line in the
cache. This leaves 17bits to define the number of pages in main
memory i.e. 217 = 128K pages. In summary, an 8K doubleword
cache divides main memory into 128K pages of 8K doublewords
each.
S14-84
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
ADDRESS BUS OF THE 80386 MICROPROCESSOR
I
I
3 12
1 311 30 1 291 • 1 • 1 ·1 • 1 .11411 1
1 ·1 • 1 • 1 • 1 21
17 BITS
13 BITS
18 BITS
12 BITS
---------------------------............. ............................
........................................
TWO WAY SET ASSOCIATIVE
11 BITS
19 BITS
Solid Unes :
DIRECT MAPPED
FOUR WAY SET ASSOCIATIVE
Address bits that are used to Address the Tag Memory
Dashed Unes: Address bits that are stored in the Tag Memory
Direct Mapped
Two way set
Four way set
To address the Tag memory
A(2:14) ->13 bits
A(2:13) ->12 bits
A(2:12) ->11 bits
To store In the Tag memory
A(15:31) ->17 bits
A(14:31) ->18 bits
A(13:31) ->19 bits
Page Size
8K
4K
2K
Number of pages
128K
256K
512K
Number of cache memory banks
1 Bank
2 Banks
4 Banks
Absolute size of the cache memory
1 x 8K
2x4K
4x2K
Figure 3. Associativity, Architecture, Addressing, and Page Size for a fixed size cache. In the Implementation that follows the cache alze la 32
KBytes. Figure 3 shows how the address bus of the 80386 should be divided for different associativity of the same size cache (32 KBytea).
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- - - - - ----_._-._----..
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-3~
MAIN MEMORY
DWord 8191
PAGE 131071
•
•
•
8K
DWord2
DWord 1
DWordO
DWord 8191
PAGE 131070
•
•
•
8K
DWord2
DWord 1
DWordO
PAGE 0
TAG
•
•
•
•
•
•
•
•
•
•
•
DWord 8191
•
•
•
•
•
DATA
•
•
•
DWord 2
DWord 1
DWord 0
CACHE TAG
+ MEMORY
DWord 2
DWord 1
DWord 0
TOTAL MEMORY = Number of Pages
x Page Size x DWord
= 128K x 8K x 4Bytes
= 4 GigaBytes
Figure 4A. Direct Memory Mapped representation of a 32 KBytes Cache
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8K
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
MAIN MEMORY
DWord 4095
•
•
•
PAGE 262143
4K
DWord2
DWord 1
DWordO
DWord4095
•
•
•
•
•
•
•
PAGE 262142
4K
DWord2
DWord 1
DWordO
•
•
•
•
•
•
•
•
•
•
•
Page 0
Page 2
Page 212
TAG
Page 32
t-'age 01
t-'age 24
•
•
•
•
DWord 4095
•
•
}K
•
PAGE 0
TAG
t-'ageti
Page 10001
Page 104_
DWord2
DWord 1
DWord 0
Page 123
Page 338
Page 653
DATA
DWord 4095
DWord 4094
DWord 4093
•
•
•
•
DWord 2
DWord 1
DWordO
BANKA
DATA
DWord 4095
DWord 4094
DWord 4093
•
•
•
•
DWord 2
DWord 1
DWord 0
BANKB
TOTAL MEMORY = Number of Pages x Page Size x DWord
= 256K x 4K x 4Bytes
= 4 GigaBytes
Figure 4B. Two-Way Set Associative Memory Map for a cache with a total size of 32 KBytes
The operation of comparison for the cache tag, for the latter
example, uses the 13 LSBs of the microprocessor address bus to
address the cache tag and compares this accessed address to the
17 MSBs of the microprocessor address bus (Figure 5).
Additionally, the valid bit(s) is(are) also examined. If a match
occurs the cache memory is· enabled and the microprocessor
reads the data from cache memory.
Byte Enable Bits
AD 0-1
17-Bit Page Field Addresses
217 Pages i.e.128K Pages
I I I I I "
I. ~I---.
13-Bit Une Field
2 13 Doublewords
\
I I I I I I I I I I I I I I I I I I I I I I I
AD 31-15
--~~~I~
AD 2-14 - . \
Figure 5. Local Address Bus For 80386 Direct Mapped Design
Performance as a Function of Associativity
The differences in the architectural structure of caches of
different associativity results in different performance levels for
equivalent program. If one examines the direct mapped
architecture, one will notice that it will not permit more than one
page/line offset conflict in its cache I.e. page 1/Iine 2 and page
21line 2 can .D.Q! coexist in cache memory. For a two-way set, one
will notice that the design will not permit more than two page/offset
line conflicts I.e. page 1/Iine 2 and page 2Iline 2 can exist in the
cache concurrently, but page 1/Iine 2, page 21line 2 and page
3/line 2 can .D.Q!. Similarly, a four way set will not permit more than
4 page/line offset conflicts.
Thrashing
Because of the existence of page/line offset conflicts, certain
programs may result in a situation coined as thrashing-which
results in a significant increase in the miss rate. As an example of a
program which results in thrashing, consider a direct mapped
cache design where the microprocessor must process two lines of
code in a repetitive loop e.g. the microprocessor must first read the
code on page 2Iline 1, then read the code on page 3/line 1 and then
go back and read the code on page 21line 1. For a direct mapped
design, such a code structure (or trace) will result in consecutive
misses.
Although thrashing occurs most often in direct mapped
systems, it can also occur in two-way set or four way set designs.
This, of course, is due to the fact that the number of page/line offset
conflicts supported by these designs is also limited.
In this example a smaller line size in a direct mapped cache
reduces thrashing more than the more common approach of a
bigger line size in a two way set associative cache.
S14-87
(9
~
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
REPLACEMENT ALGORITHMS
Replacement algorithms for caches pertain to the method used
to update the cache memory. The replacement algorithm is
Important in that it will affect the hit rate of the system which in turn
alters the effective cycle time of the system (and hence the MIPs
rating) Replacement algorithms, are designed such that the cache
is updated with data or code that will be most frequently used by
the microprocessor. Conversely, replacement algorithms are also
designed to delete data or code that is least frequently used.
There are several types of replacement algorithms used for
caches. Three of these are the least recently used (LRU) algorithm,
the First In First Out (FIFO) algorithm and the random replacement
algorithm. The least recently used algorithm, on a cache read miss,
replaces the data/code in the cache that in relation to the other
code/data was not used last. The random replacement algorithm
replaces data/code in the cache by random selection. Finally, the
FIFO algorithm replaces data that entered the cache first i.e. the
oldest data In the cache.
The associativity of the cache, i.e. direct mapped, two-way set,
or four way set, often dictates the replacement algorithm chosen.
For direct mapped caches, for example, there is no need to
consider a replacement algorithm. This is because the direct
mapped hardware design requires that the cache be updated, on a
miss, with the corresponding page/line address from main
memory.
For the two-way set cache, because of its deSign, one has the
option, on a cache miss, to update either of two cache addresses
(in one of the two ways). The LRU algorithm is often used here
because it only requires one memory bit in the cache tag to
determine which way of the cache was accessed last. On a cache
miss, the LRU bit Is checked, and, for example, if it is set, the data in
way 1 is replaced. On the other hand, if it is reset, the data in way
2 is updated.
For caches with associativity greater than or equal to 4, a
random replacement algorithm is often used. This is because it
offers a hit rate comparable to that of other algorithms and requires
a pseudorandom number generator to implement.
LINE SIZE SELECTION
Line size is a term used in cache design that refers to the unit of
transfer (in Bytes) between the cache and main memory. Forthe
majority of 32-bit systems, the line size is often chosen to be 4 bytes
A line size of 4 bytes simplifies controller logic and problems
associated with byte boundaries. The line size, however, has an
affect on the overall performance of a system. As one increases the
line size, the effective hit rate of the system goes up (for a fixed size
cache) which increases the overall MIPs performance of the
system. On the other hand, a larger line size will result in an
increase in the amount of system bus traffic. Which is, of course,
due to the greater number of bytes transferred on a cache miss.
Depending on the type of system design, the size of the line
chosen will affect the overall system performance. For
multiprocessing systems, where it is desirable to keep system bus
traffic to a minimum, a small line size is often opted for.
Table 1 illustrates the affect of line size for different size caches
on the overall system throughput, where "an Is the marginal transfer
time per byte and "bn is the overhead per miss.
Cache Size
(bytes)
32
64
128
256
512
1024
2048
4096
8192
16384
32768
a
b
= 15 ns/byte
= 360ns
4 -16
8 -16
8 -16
8 - 32
8 - 32
8 - 32
16 - 32
16 - 64
16 - 64
16 - 128
16 - 128
a
b
= 15 ns/byte
= 160ns
4-8
4 -16
4 -16
8 - 16
8 - 16
8 - 16
8 - 32
8 - 32
8 - 64
8 -128
8 - 128
b
= 600ns
8 -16
8 - 32
8 - 32
16 - 32
16 - 64
16 - 64
16 - 128
32 - 128
> = 64
>= 64
> = 64
Table 1. Optimized Line Size vs. Cache Size and Delays. This table
was taken from A. Smith's paper on cache memories.
COHERENCYDEFINITION AND COMPONENTS OF
Coherency is defined as the capability of cache memory to
replicate in real time the current contents of main memory. Cache
coherency is necessary in all cache bused microprocessor
designs where an external device can control the bus and write to
main memory. If a system has a DMA device, more than one
microprocessor, or memory mapped I/O devices, coherency logic
must be considered.
WRITE COHERENCY HARDWARE
Write operations require special considerations in cache
design. For a microprocessor write operation to main memory, in
order to maintain local cache and main memory coherency, the
local cache memory must be updated along with main memory.
In order to ensure write coherency, there are a number of
hardware techniques. The three most popular design techniques
are the copy-back, write-through, and buffered write through
schemes. Each of these techniques offers different advantages.
The copy-back and buffered write through schemes feature
increased system throughput. On the other hand, the write-through
scheme offers minimized support logic.
For a write-through based cache design, every time the
microprocessor write occurs the code/data is written
simultaneously to the cache and main memory. Because of the fact
that main memory is slower than cache memory, the time to
implement a write is governed by the cycle time of main memory.
This, of course, puts a limitation on the effective cycle time of a
cache system based on a write through scheme.
A hardware modification to the write-through design that allows
for a reduction in the effective cycle time is a high speed buffer.
This design, often referred to as a buffered write-through or posted
write, improves the performance by allowing the microprocessor to
operate out of the cache, at cache speeds, after a microprocessor
write operation. This is in direct contrast to the write-through which
requires that the microprocessor wait for the completion of the
main memory write cycle. In a buffered write-through cache
system, when a write occurs, the cache and buffer are updated with
the write data, allowing the microprocessor to read from the cache
again. During this time, the buffered write-through logic takes
control of the system bus and updates main memory by
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _..
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
............_... _.--
APPLICATION NOTE AN-30
a SNOOP hit is issued and the controller could either invalidate that
particular entry or flush the content of the entire cache.
As can be seen from the above, the time-multiplexed scheme
requires two sequential cache tag comparisons, i.e. the CPU
address bus is compared against the contents of the cache tag and
then the system bus is compared against the contents of the cache
tag. This, of course, results in a delay time equal to the time it takes
to perform two accesses to cache tag memory plus the time it takes
to multiplex between the system bus and the CPU bus.
The dual cache tag scheme when compared to the
time-multiplexed scheme permits a significant reduction in the
microprocessor cycle time. This is because, as opposed to the
time-multiplexed scheme, the dual cache tag scheme allows for
the system bus address tags (SNOOP tag) and the CPU address
bus tag (cache tag) to function at the same time. On the instigation
of a system bus transfer, the system address bus page field (or tag)
is compared against the page field stored in the SNOOP tag. At the
same time, the CPU bus page field is compared against the page
field stored in the CPU bus cache tag. If the SNOOP tag page
address does not match the system bus page address, the
controller continues onto its next cycle. If, on the other hand, the
SNOOP tag did match the system address page field, the
associated valid bit of both cache tags are cleared or both cache
tags will be reset.
This means, of course, that the microprocessor cycle time
required for the dual cache scheme (equal to the time it takes to
perform one cache tag access and comparison) is less than
one-half of that required by the time multiplexed scheme (equal to
th~ time it takes to perform two cache tag accesses and
comparisons) .
downloading the file buffer. Adding a buffer, of course, increases
the number of components for the cache module.
A copy back system operates on the use of a dirty bit that is
stored along with the cache tag address. For a copy-back scheme,
when a cache write hit occurs, the associated dirty bit is set which
indicates that the data in the cache is no longer coherent with main
memory. When another bus master requests control of the bus,
before releasing the bus, the cache controller will update all the
locations in the main memory that are not coherent with the content
of the cache memory as a result of cache write hits. A cache write
miss will occur when the microprocessor attempts to write to a
location that was not cached earlier.
The disadvantage of a copy-back system becomes apparent in
the design of multiprocessor and multi-master based systems. In
these systems, any extemal read from main memory requires that
all caches in the system be checked to see if the dirty bit has been
set for each address written. If the dirty bit has been set, the
associated data entry in the cache must be downloaded to main
memory before an extemal device accesses that address.
Although, the buffered write through has a somewhat lower
performance than a copy-back (because of main memory traffic
during write misses), write-through and buffered write through are
often preferred to use in multiprocessing systems. This is because,
as mentioned above, there are a number of coherency issues that
must be dealt with for a copy-back scheme.
COHERENCY LOGICFOR DMA AND MULTIPROCESSOR SYSTEMS
In order to maintain coherency for multiprocessing and OMA
applications, a cache design needs to be able to monitor the
system bus for extemal device writes to main memory. If a write to
main memory occurs from an external device, it is necessary to
inform the cache memory of the address written to so that the
cache controller can decide whether or not to invalidate the cache
memory contents (either by flushing the entire cache or by clearing
the associated valid bit of the entry).
Implementing a Dual Cache Coherency
Architecture
For implementing a dual cache coherency system, 10T7174's
cache tag SRAMs can be used to form both the microprocessor
cache tag block and the system bus cache tag block (SNOOP
tag) -as shown in Figure 7. For a dual cache based system, the
SNOOP memory is always identical to the microprocessor cache
memory. This is accomplished by writing the same information at
the same time to both system (SNOOP) and CPU cache tag
memories. The operation of the dual cache is such that when
another bus master has control of the system bus and writes data to
a previously cached address in main memory, a SNOOP hit
occurs. A SNOOP hit will result in the controller either invalidating a
particular entry in both cache tags or flushing all the entries in both
cache tags.
Architectures for Cache Coherency
There are two common architectures used to achieve
coherency in microprocessor based systems; a time-multiplexed
cache tag architecture and a dUlll cache tag architecture. For the
multiplexed cache tag architecture, the cache is time multiplexed
between the system address bus and the local address bus. This
permits the controller to check if the system address location
written to is in the cache memory. For the dual cache tag system,
one cache tag is used to monitor the local address bus and another
cache tag (the SNOOP tag) is dedicated solely to monitoring the
system address bus.
DESIGNING A CACHE TAG UNIT
In order to optimize cache design, the 10T7174 may be used
(Figure 6). This cache Tag SRAM (8K x 8) has built-in features that
help and simplify cache tag design. These include a match output,
a reset input, CEMOS TIl technology, and three state I/O. The
match output is high whenever the address stored in the 10T7174,
accessed by the address pins, matches the address at the I/O pins.
The tag is addressed by pins AO-A 12 and the tag is compared to
the. stored tag on the I/O pins via an internal comparator-if they
match, the match output goes high. For cache design
applications, the match output drives the cache controller which in
case of a match (hit) places the data contents of the cache memory
on the microprocessor data bus. The reset input (active low) allows
the entire contents of the cache tag memory to be cleared which
permits reset on system power up and the cache to be flushed (for
coherency applications).
.
Dual Cache Tag vs. Time-Multiplexed Cache Tag
Architecture
The advantages of a dual cache tag system over a
time-multiplexed cache system are seen when one examines the
timing requirements of the two, i.e. the dual cache tag design can
work with a much shorter microprocessor cycle time. The
time-multiplexed scheme uses the same physical tag memory to
tag the addresses present in the cache memory (tag) and checks
the main memory's address bus activity (SNOOP). When the
processor requests data of any address, the page field of its
address bus is compared against the one stored in the tag
memory, if they match a hit occurs else a miss is issued. The
remaining part of the cycle, the tag memory acts as a SNOOP
memory i.e. it monitors the main memory's address bus activity for
any write to an address with a matching page field. In the latter case
S14-89
- - - - - - - - _ . _ - _..
_
__ __..._._._--_
..
..
(9
•
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
AO
1/°1
1/0 2
1/0 3
1/0 4
1/0 5
A1
f.2.
A3
A4
A5
A6
IDT7174
1/°6
1/0 7
I/O e
A7
MATCH
AS
RESET#
CHIP SELECT#
A9
A10
A11
WRITE ENABLE#
O~PUT
ENABLE#
A12
Figure 6. The IDT7174 8K x 8 Cache Tag SRAM
The 1017174 features an address to match time of 20ns, making
it suitable for applications up to 40MHz along with fast SRAMs to
build the cache memory for two-cycle machines such as the Intel
80386). It is also cascadable in depth and width which allows
caches to be easily designed for a variety of different
microprocessor address bus widths.
Figure 7 illustrates a cache tag SRAM comprised of three
1017174's organized as IOT8192 23-bit words. If used in a
microprocessor based system, main memory would be divided
into 8 Million pages. The lower address bits specify the line offset in
the cache where the lower page address tag is stored. The 23 bit
page address (within the cache tag SRAM) accessed by the 13
lower microprocessor address bus bits is compared against the
23-8it microprocessor page address. If there is a match from all
three, the wired AND match output will go high indicating that the
needed data is in the cache memory.
I/O 8 of the last 1017174 is the cache data valid bit. This bit is
used to indicate thatthe data in the cache Is valid. On power up or a
cache. flush the valid bit is very useful.
LOWER ADDRESS BITS
UPPER ADDRESS BITS
AO
f.2.
A3
A4
A5
A6
AO
AO
A1
IDT7174
1/0 1
1/0 2
1/0 3
1/0 4
1/0 5
1/0 6
1/0 7
I/Oe
A1
f.2.
A3
A4
A5
A6
IDT7174
1/0 1
1/0 2
1/0 3
1/0 4
1/°5
1/0 6
1/0 7
I/O e
A1
f.2.
A3
A4
A5
A6
IDT7174
1/0 1
1/0 2
1/0 3
1/0 4
1/0 5
1/0 6
1/°7
I/Oe
A7
MATCH
A7
MATCH
A7
MATCH
AS
RESET#
AS
RESET#
AS
RESET#
CHIP SELECT#
A9
CHIP SELECT#
A9
A9
A10
WRITE ENABLE#
A10
WRITE ENABLE#
A10
CHIP SELECT#
WRITE ENABLE#
A11 OUTPUT ENABLE#
A11 OUTPUT ENABLE#
A11 OUTPUT ENABLE#
A12
A12
A12
MATCH OUTPUT ~----~__--------~------------~~----------------------~
2000
PULL-UP
RESISTOR
+5 VOLTS
WRITE INVALID - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Figure 7. A Cache Tag Unit
S14-90
- - - - - - - - - - - - - - - - - - - - - - - - -..
•..
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
A CACHE CONTROLLER AND MEMORY MODULE
FOR THE 80386
For the design of a cache controller, one must become familiar
with the microprocessor that is being used,' its interface and
signaling requirements. As well, one must decide on the cache's
associativity, depth, configuration and ensure that all critical
microprocessor and system timing requirements are met. The
design of the cache controller must then be considered to allow for
functions such as coherency, bus arbitration, and state machine
sequencing (to control the interface to the system bus and the
microprocessor) .
For the design that follows, an 80386 microprocessor is used
(25M Hz Version) which incorporates a dual cache tag coherency
architecture.
80386 Microprocessor Cache Considerations
In the following processor description and cache system
Implementation, when a M#" sign follows the name of a signal It
indicates that this signal is active low, if there is no M#" sign at the
end of a signal name, it means that it is an active high signal.
The 80386 microprocessor from Intel is the current mainstay of
both the PC market and low end workstation market. The 80386 is
currently used In the leading edge IBM PCs, Compaq's
microcomputer and in Sun's new multitasking workstation.
The 80386 (Figure 8) is based on low power CMOS technology
and comes in 16MHz, 20M Hz, and 25MHz versions.
As Illustrated in Figure 8, the 80386 has an effective 32 bit
address bus giving an address space of 4 Gigabytes. The address
bus consists of address lines A2-A3,1 and four byte enable lines
BEO#-BE3#. The byte enable signals allow the 80386 to address
one or an adjacent combination of the 4 bytes contained in the
80386's 32-bit word.
"'-
.....
CLK2
2XCLOCK
ADDRESS BUS
/
BE3#
"'-
/
32BIT
DATA
(
DATA BUS
DO-D31
"'-
~~kOL[
..,.
7
"/
BE1#
.....
NM ...
-'"
..
..
80386
PROCESSOR
INTERRUPTS
(
.........
(
...
......
NMI
....
RESET
........
W/R#
....
LOCK#
HLDA
INTR
...
,....
MilO#'
..
......
BED#:
DIG#'
BSl6# ...
READY# ...
BUS
ARBITRATION
..
..
-..
32-BIT
ADDRESS
"""111"'"
BE2#
ADS#
HOLD
A2-A31
.......
....
PEREO#
....
.....
BUSY#
....
.....
ERROR#
..
.
.
--,...
--,...
......
BYTE
ENABLES
J
BUS CYCLE
DEFINITION
J
J
COPROCESSOR
SIGNALLING
Figure 8. The 80386 Microprocessor
80386 Microprocessor Signals
80386 Bus Cycle Definition Signals,
The 80386 microprocessor signals can be divided into bus
cycle definition signals, bus control Signals, bus arbitration
signals, and interrupt signals. The bus cycle definition signals
define attributes and conditions of the current bus cycle in
progress, e.g. memory read or I/O write. The bus control signals,
on the other hand, control the operation of either the bus or
microprocessor, e.g. inform the microprocessor of the completion
of a cycle or the transfer of a 16 bit word. Bus arbitration signals are
used to arbitrate the control of the bus by competing bus masters,
e.g. HOLD and HOLD Acknowledge. Finally, interrupt Signals are
used to interrupt the current process of the microprocessor so that
another process may be executed, e.g. NMI#.
Lock# (Lock) indicates that the current microprocessor cycle
under execution can not be interrupted i.e. by an interrupt signal.
S14-91
W/R# (Write or Read) signals whether or not the microprocessor is
in a read cycle or write cycle.
M/IO# (Memory or I/O Cycle) indicates whether or not the cycle is
a memory access or I/O access.
D/C# (Data or Control Cycle) signals whether or notthe current bus
cycle is a data or control cycle.
[9
•
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
80386 Bus Control·Signals
Bus Arbitration Signals
ADS# (Address Status) Is an address status signal which Indicates
that the address Issued by the microprocessor is valid and ready
for sampling.
HOLD Is an Input signal to the 80386 that requests that the 80386
relinquish control of either the local bus or system bus so that an
extemal master can take control of the bus.
HLDA (Hold Acknowledge) Is an output from the microprocessor
that signals to an external bus master that It has received and
acknowledged a HOLD signal and has released the bus.
READY# Is an Input to the microprocessor that Indicates the end of
the current bus cycle.
NAN (Next Address) Is an Input to the microprocessor that Is used
to Instigate the hlgh·speed pipeline mode.
BS#16 (Bus Size 16) Is an Input to the microprocessor that Informs
the microprocessor that 16·8it data Is to be transferred
Interrupt and Interface Signals
CLK2 Is the microprocessor clock Input provided by a crystal
(twice the microprocessor clock frequency). This signal Is divided
by two Inside the microprocessor.
RESET Is an Input to the microprocessor that forces the 80386 to a
known state.
T1
T2
Microprocessor Cycles
Figure 9 Illustrates the basic timing for a microprocessor cycle.
ClK2 serves as the timing reference for the microprocessor bus
cycles. This signal Is divided by two to form the Internal ClK signal
(for a 25MHz 80386, ClK2 would be 50MHz and ClK would be
25M Hz). The bus cycle of the microprocessor consists of two bus
states, T1 and T2, which are further subdivided Into two phases
each, 01 and 02.
T1
T2
CLK2
CLK
ADS#
READY#
Figure 9. Basic Timing Waveform for 80386 2 State Cycle
The Intel 80386 requires a minimum of two 25MHz cycles to
complete any Instruction. The start of a microprocessor cycle Is
characterized by ADS# going low which Indicates that there Is a
valid address on the microprocessor bus. At the end of bus state
T2, the microprocessor checks the READY# Input to see If the
cycle Is finished. If READY# Is 10w,It means that the current cycle Is
completed which allows the microprocessor to start a new bus
cycle. On the other hand, if READY# Is high at the end of T2, the
processor will stay In the T2 bus state until It sees a low level on the
READY Input. For this condition, all added T2 bus states are called
walt states (Figure 10). In cache design, for a miss, the READY
Input remains high until data Is retumed from main memory.lfthere
Is no pending action required by the microprocessor after T2, the
microprocessor will enter In an Idle state, Ti (ADS# will remain
high - Figure 11).
S14-92
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
WAIT STATES
T1
~
/
T2
T1
T2
..4.. '
'1-'1
..4.. 1..4..
'1-'2' '1-'1
'
ClK2
ClK
READY#"
jLf
y
t
~
WAlJW
Figure 10. An 80386 Bus Cycle With 2 Walt States
IDLE STATES
T1
T2
/
~
T1
T2
..4.. '..4.. I ..4..
'1-'1
'1-'2' '1-'1
' ..4.. 1..4..
'1-'2' '1-'1
'
ClK2
ClK
Lf
READY#
Figure 11. An 80386 Cycle Followed By Two Idle States
When designing a cache system with the 80386
microprocessor, it is important to remember that the only time
when the microprocessor probes the READY# input is at the end of
T2. The rest of the time, the processor ignores the logic state of the
READY# input.
Another bus cycle that is important in the design of a controller
for cache memory operation is the hold-hold acknowledge cycle
(Figure 12). When another bus master (e.g. DMA Device) wants to
take control over the bus, it asserts the HOLD signal that feeds the
microprocessor. When the microprocessor sees the HOLD signal
go high, it will finish the current bus cycle it is executing, float its
data, control and address buses, and then issue a HLDA (hold
acknowledge) signal to the extemal bus master. However, if the
LOCK# pin is active on the microprocessor, a HOLD will not be
acknowledged by the microprocessor. The lock signal effectively
prevents any device from interrupting the microprocessor process
in progress.
S14-93
III
i
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-3~
HOLD STATES
T1
12
IDLE STATE
~
/Th
Th
ClK2
ClK
ADS#U
READY#
7I//////////1U!!!!!!!11////////II
H O L D _ I IL...--_
HLDA
Figure 12. A Two Hold 80386 Cycle Followed By An Idle State
State Diagram
Figure 13 shows the state diagram for the 80386 operating in
non-plpelined mode. After the microprocessor Is first tumed on, a
RESET pulse will put the 80386 into a known state. When the 80386
receives a RESET pulse, it will automatically fetch its first
instruction from address OFFFFFFFOH. Usually, at this address,
there Is an unconditional jump to the location where the bootstrap
routine Is located(the BIOS).
For plpellned mode the NA# pin must be asserted. For a
discussion of pipelined mode for the 80386 refer to the Intel 386
Microprocessor Reference Manual.
ALWAYS
NO HOLD
NO REQUEST
READY, NO REQUEST, NO HOLD
Figure 13. State Diagram For The 80386
S14-94
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
always map to line 0 of a main memory page (given by tag). This, of
course, means that it is impossible to have more than one unique
line address in a direct mapped cache e.g .. line O/page 1 and line
O/page 3 can never coexist in the cache.
CACHE CONTROLLER DESIGN
Cache Associativity, Depth, Page Size, and Line
Size Selection
Cache Controller Hardware Overview
One of the first considerations for the design of a cache
controller Is the selection of the cache memory. For this design, a
direct mapped cache is selected with a cache size of 8K x 32. The
8K data cache divides main memory into 128K pages of 8K
doublewords (a doubleword is 32 bits or 4 bytes). The line size
selected for this cache design is 4 bytes.
It should be recalled that for a direct mapped cache (Figure 2)
every line in the cache will map to a corresponding line In a page
(given by the tag) In main memory e.g .. line 0 of the cache will
Figure 14 Illustrates the block diagram of the dual cache
. controller to be designed for the 25MHz version of the 80386. The
design consists of; two cache tag SRAM blocks, one for the system
bus and one for the CPU bus; three PALS used for the design of the
cache controller state machine; a data cache SRAM block for the
microprocessor; and a number of 74F logic blocks thatserve as
data/address/control logic and system bus drivers.
SYSTEM
BUS
80386
BUS
~
: A (2:31)
0(0:31)
A (2:14)
BA (2:31)
80386 CACHE MODULE
NCI#~
AOS#
M/lO#
RESET
...
....
."
TAG
DATA
SNOOP
3x7174
4x 7164
3x7174
MAT1
W/R#
O/C#
l'
La{>o-
ClK
li
."
IBM
FLUSH
lROY#
A·WE1#
ClR#
WINW
•
A~
MAT2
OE2#
WE2#
CE1~
"
,
,
A.
WE1#
CLR#
WINW
-..
,
......
BAOS#
BHLDA
: CONTROL LOGIC
,
REAOY#
BROY#
g~?~
~
FBE# '
BEO# - BE3#
..
Em
SBEO# - SBE3#
I..ot
.....
J SBEO# -
SBE3#
OEN#. OIR. WlE. SEl. BHLDA
OElMt ...... G#
OIR
~
WlE _. OIR
CAB
SEl
..JIo
SAB
o (0:31)
J
___
DATA
BUS
BUFFERS
(4-FCT646)
B ....
A
BO (0:311
......
'32
SBEO# - SBE3#
BHLOA
G#
;: CAB
WlE
SEL
_
SAB
LA
~ A
, 33
... A
f
..
...
M/IO#. O/C# W/R#
A (2:31)
ADDR
BUS
BUFFERS
(5-FCT646)
B
BBEO# - BBE3#
BM/lO#. BO/C#. BW/R#
BA (2:31)
..
Figure 14. Block Diagram of the Complete Cache System
S14-95
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
For the CPU cache tag, a 8K x 24 cache tag Is used (Figure 28
and 30) which Is constructed from three IDT7174 cache tag
SRAMs. The system bus cache tag (SNOOP tag) Is constructed
exactly the same i.e. with three IDT7174's.
For proper termination of a bus cycle, a 74F64 And Or Invert
gate is used (Figure 31) to drive the READY input of the 80386. The
74F64 is used in order to meet the critical timing requirements of
the READY signal.
The buffer network is built from nine IDT74FCT646's to form the
address, data and control bus buffers. The IDT74FCT646 is a Fast
CMOS Octal Transceiver Register with an 8-Blt A register and an
8-blt B Register. The 646 block allows for the bidirectional transfer
and temporary storage of 32 bits of data. The DIR (direction) pin is
used to control the direction of data flow between the processor's
data bus and the system's data bus (Figure 14).
The system bus tag (SNOOP tag) monitors the addresses on the
system's address bus when an extemally controlled data transfer
takes place (e.g. DMA) .If the SNOOP tag detects an address that is
contained in the CPU cache tag (when BHLDA is active and when a
write occurs), the entire content of both cache tags is flushed via
the reset input of the IDT7174.
The Microprocessor Interface
The microprocessor Interface consists of four byte enable pins.
The bus cycle status pins i.e. 0/0#, MI/O#, W/R#, clock and reset
signals, the address status pin ADS#, and the four local control
signals FLUSH#, LRDY#, READY#, RESET, LBM and NCM (see
Figure 15 for a complete description of the microprocessor and
system interface pins).
The NCM Input is for decoding non-cacheable addresses such
as I/O memory space. The deSigner needs to design a decoder
that recognizes non-cacheable addresses. The decoder output
ties directly to the NCM Input. LBM is used to Indicate that the
80386 is working with a local device (such as a coprocessor).
System Bus Interface
The system bus Interface consists of the buffered data bus
(BDO:31), the buffered address bus, (BA2:31), the bus byte enable
Signals (BBEO#-BBE3#), the system bus control signals (BM/IO#,
BDO#, and BW/R#), and the system control signals of BRDY#,
BHOLD, BADS# and BHLDA. It should be noted that the 80386
equivalent front end signals of the controller module are prefixed
by the letter B (For a complete listing of system bus interface
signals, see Figure 15).
SIGNAL DESCRIPTION
• BA (2) - BA (31) are the 30 address pins that connect the system
address bus to the cache module. These 30 pins form the BA
bus or the board address bus.
• BHOlD Is an input to the cache module. BHOLD (bus hold) is
asserted by system when another bus master wants to take
control of the bus. BHOLD is active high.
• BHlOA is an output from the cache module to the system. When
Bhold is asserted by another bus master, the cache module
responds by activating BHLDA (bus hold acknowledge), the
other bus master is then granted control of the bus.
• BROY# Is an Input to the cache module. When the system
asserts this pin, it indicates that the current memory cycle is
complete. BRDY# is active low.
• SBEO# - SBE3# are four output signals from the cache module.
They are the individual byte enables for the memory. These four
signals are active low.
• BAOS# is an output from the cache module to the system. When
BADS# (board address status) is asserted, it indicates that the
BA bus is stable. BADS# is active low.
• BW/RII is an input to the cache module from the system. BW/R#
(board write read) is used in the SNOOP function of the module
and helps the device to detect when a write has occured to an
active cache address.
• RESET is an input to both the cache module and the 80386. The
RESET Signal comes from the system and is asserted for 8 or
more CLK periods so that the processor and the cache module
will be placed in a known reset state. The tags of the cache will
be cleared. RESET is active high.
• FLUSH is an input to the cache module. While FLUSH Is
asserted, It will cause the tags to clear. This pin Is a
"programmable reset". This signal is active high.
.• lROY# Is an input to the cache module. LRDY# is an indication
to the module that a local bus cycle is complete. This Signal is
active low.
• W/Ri1 Is an input to the cache module. When W/R# Is high it
indicates that the 80386 is executing a write cycle and when it Is
low it shows that the processor is executing a read cycle.
• AOS# Is an Input to the cache module. This signal shows the
status of the A bus. When ADS# is low it indicates that the
address bits A (2) - A (31) are stable. This signal is active low.
• ClK is an Input to the cache module. It Is identical to the 80386
clock.
• A (2) - A (31) are the 30 address pins that connect the 80386
address bus to the cache module. These 30 signals are the A
bus.
• BEO# - BE3# These four byte enable signals are outputs from
the 80386 and are tied directly to the byte enable inputs of the
cache module.
• NCM Is an input to the cache module, while active it indicates to
the device that the current address present on the address bus,
A (2) - A (31), Is a non cache-address. This signal is active low.
• O/C# is an input to the cache module. 0/0#, data-control, is
used by the 80386 to Indicate a data cycle or a control cycle.
While low the processor Is In a control cycle and while high in a
data cycle. No cache operations are permitted in control cycles.
• M/IO# is an Input to the cache module, while low it indicates that
the 80386 Is addressing an I/O device and while high it Indicates
the processor Is addreSSing memory. No cache operations are
permitted for I/O devices.
• IBM Is an input to the cache module, while active It indicates
that the processor is acceSSing another device on the local bus,
for example the 80387 coprocessor. Local bus addresses are
not cache addresses.
• OIR, OEN# are outputs from the cache module. These signals
control the data bus buffers and the address bus buffers
(external to the module). DIR determines the direction of the flow
of the data bus buffers. DEN# is the enable signal and is used to
tum on the bus drivers.
• WlE is an output from the cache module to the data bus buffers
and to the address bus buffers. WLE Is used to latch write data
Into the write buffers.
• SEl is an output from the cache module. It Is used to select the
latches in the data bus buffers and the address bus buffers.
• 0 (0) - 0 (31) These 32 signals are the data bus connecting
directly to the data bus of the 80386. They are also connected to
the data bus buffers.
• REAOY# Is an output from the cache module. When asserted It
indicates to the 80386 that the current cycle is finished. This
signal is active low.
Figure 15. Functional Cache Controller and 80386 Signal DescrlpUons
S14-96
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
Timing Diagrams for the Cache Design
controller enabling the cache memory for a write operation (via the
WE2# line). At this time the CPU data bus is written into the cache
memory.
For either a cache hit or miss cycle, the cache controller also
drives the WLE line of the posted write latch such that the address
and data bus contents are captured for the system bus. For a write
miss, the controller exhibits similar timing as it does for the write hit.
However, for a write miss, the cache controller will start writing to
both cache and main memory as if it was handling a write hit cycle.
If later during T2 it was determined that a miss had occured (via
MAT1) then the new content of that cache location does not
correspond to the tag address. The WINV# signal will be driven low
to invalidate the corresponding tag in the cache tag and the
SNOOP tag (see Figures 28 and 30).
Figures 16 through 26 illustrate the cache controller and
memory module timing diagrams for a number of different bus
cycles, namely cache read miss, cache read hit, write cache hit,
write cache miss, read LBA, write LBA, read NCA, write NCA,
BHOLD, and BHLDA. Figures 25 and 26 illustrate the cache tag
and cache memory timing for both the cache and SNOOP tag.
Cache Read Miss and Hit Cycles
The cache read hit cycle, illustrated in Figure 16, begins by
ADS# going low followed by the W/R# signal going low (to indicate
a read). The controller responds by driving WE1# high. The WE#1
signal which drives both the local bus cache tag and the SNOOP
tag sets the two cache tags up for a read and compare operation.
After the read and compare operation is complete, the MAT1 signal
will be valid. At this point in time (at the beginning of bus state T2)
the cache controller samples MAT1. If MAT1 is high, it indicates
that the cache memory has valid data. The controller responds to
this condition by sending its OE# signal low which in tum enables
the output of the cache memory to drive the microprocessor data
bus with its associated 32-bit data word.
On the other hand, if MAT1 was low,· the controller would
respond by entering into a cache read miss cycle (as shown in
Figure 17). This condition indicates that the address is not cached.
For the cache read miss cycle, the cache controller drives the
DEN# signal low which connects the local data bus to the system
data bus. The control signals ADS# and W/R# are duplicated by
BADS# and BW/R# which are placed on the system bus to allow
main memory access. The system bus responds with the required
data and then drives BRDY# low when done. During the main
memory access, the controller updates the cache memory with the
new data, the local bus cache tag and the SNOOP tag with the
associated tag. After the controller receives the BRDY#signal from
the system bus, it then drives READY# low which terminates the
bus cycle. It should be noted here, that for the cache read miss, the
READY# signal is held high an amount of time equal to the main
memory cycle time.
Cache Write Hit and Miss Cycles
When the microprocessor writes data to memory it may enter
into a write hit cycle or a write miss cycle (Figures 18 and 19). As
with the cache read hit cyc!e, the beginning of the cycle is
instigated by ADS# going low, but with W/R# going high. This state
results in the controller enabling the local and SNOOP cache tags
for a read and compare operation. If MAT1 is retumed high to the
controller from this tag, a write hit has occurred which results in the
LBA and NCA Read and Miss Timings
LBA and NCA both deal with special conditions. The LBA (local
bus access) cycle occurs when another device is to be accessed
on the local bus for a read or write operation. For the Intel 80386 this
is most often a numerics coprocessor. In order to read data from a
coprocessor on the local bus, (Figure 20), the LBA input to the
cache controller is activated. The cache controller then disables
the cache memory (via WE2# and 0E2#) the tag and the SNOOP
memory (via WE1#). The local ready signal (LRDY) is sent from the
coprocessor to the controller indicating the end of the LBA cycle.
NCA (non-cacheable address) cycles are entered into
whenever the NCA input to the cache controller is active. The NCA
is usually employed to keep I/O data from entering the cache. An
active NCM input results in the controller disabling the cache
memory, cache tag and the SNOOP tag. This, of course, keeps
the undesired addresses from entering the cache. As noted in
Figure 22, the NCA cycle has added wait states due to the fact that
the speed of the I/O device is limited. The designer has also the
option of mapping the address space in several sections and
choosing what section of the address space will be cacheable.
This is accomplished by connecting the NCM input to the output
of an appropriate decoder. During NCM cycles the cache
ensemble is totally transparent.
Cache Memory and Cache Tag Timing
Figures 25 and 26 illustrate the timing specifications for the
cache memory, the cache tag and the SNOOP tag. The associated
tables give the necessary memory timing delays for the 16MHz,
20MHz and 25MHz versions of the 80386 microprocessor. As seen
in the table, the READY# signal AC timing specification is met by
use of an 74F64 AOI with a delay that is less than 6ns.
814-97
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
READ HIT TIMING
I. READ HIT __I
'T1:
/
T2:
T1'
T2'
T1'
T2'
n'
T2'
n'
CLK2
CLK
ADDR
W/R#
DB
ADS#
READY#
READY
WE1#
TAG
RAM
(~IGH L~EL)
CLR#
[
MAn
"
HI"
'L . . . . _
! ....
,
~
I
~---~:~~r----p-----~----~----~----~----~----~---
(HIGH LEVEL)
CACHE[W::
RAM
----=
DB
T2#
T3#
T4#
CONTROL
SIGNALS
- :- - - - ~ - - - ~ - - _ -: - • _ -: _ JIt:l~9"IY~ _ : ___
I
•
I
_: _ _ _ _ ~ _ _ _
~
I
I
I
,
_ _ _ _: _ _ _ _: _ JI ~~~Iy~) _
WLE
(INACTIVE)
SEL
(INACTIVE)
~
~
I
____ : ____ :__ _
I
•
_ _ _ _: _ _ _ _: _ _ _ _ :_ _ _
,
MAIN#
DEN#
SYSTEM
BUS
G~D~
(INACTIVE)
-, ....... ,. ...... , ...... -," .... -,- ......
SYSDB
...... , ...... -." .... -,- ...... c .. ..
. :.. . . . :........ ~ ...... ~ ...... ~ . (~I:~.B_L:D2 . :........ :........ :........ ~ . .
(INAo/IVE)
READY
BRDY#
SYSADDR
~
: VALID: .
~\\\\\\\\\\\\\\\\\\\\\\\\\\\~\\\\\\\\\\\\\\\
,
,
Figure 16. Read Hit Timing
S14-98
: (HI-Z):
'
,
0
---.-.--.---------------~
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
READ MISS TIMING
,-:ARTlAl OR FUll WORD READ MISS~
,
T1
'
12
:
13
:
T4
:
NOT READY
,
T4
,
T1
12
T1
'
12
CLK2
ClK
ADDR
80386
BUS
~
INTERFACE
W/PrII
DB
,
ADS#
READY#
~~ [::~
MAT1
,
,
I -- ~ --- ~ ----: ~~~~:- . -- ~ --
1\\\\\\\\\\\\\\\\\\\\\\\\\\
READTAG
(HIGH LEVEL)
~~~~~==~~~~--~~--~
: I WRi~E DATA~I
__--~'~~~--~--~'~~~~~----'~H~I-~Z~'--------
CONTROL
SIGNALS
WlE
_
L.
___
~
,
SEL
___
.. _ _ _ _ I .
,
_ _ _ L.
,
:
___
.I.
---: --. -:- ---
-
-, -
-
-
___
.. _ _ _
.1.
_ _ _ L.
___
.&.
__
(INA~VE)
-,- -
-
~I
• : ,- -
-
T -
-
-
.... -
-
-,- "
"
"," -
"
SYSTEM
BUS
SYSDB
BBEO#-BBE3#
'
~~~~~~--~----~-
~\\\ \ \ \ \ \\\~ - ~ -: -ALLAciTlVE - : - ~\\\\\\\\\\\\\\\\\\\\\\W
I
I
I
I
I
Note: FBE causes all FB lines to be activated.
Figure 17. Read Miss Timing
514-99
........
_-_.__.._-------
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
WRITE HIT TIMING
I. WRITE HIT ~
:
T1
:
T2
:
T1
'
T2
'
T1
'
T2
'
T1
'
T2
'
T1
'
CLK2
CLK~"""""
ADDR
Sgrf§6
-<
W/R#
INTERFACE
~
' VALID,
,
: WRITE:
t\\\\\\\\\\\\\\~\\\\\\\\\\\\\\\\\\\\\\\\\\\\
)~:--~--~--~--~--~--~
DB
ADS#
READY#
READY
/
TAG
RAM
CACHE
INTERFACE
MAT1
i
I
C~r~E[ W::
\..
DB
HIT
I
1 ..
_
_
, ,
.., . . . . .J
I
(DISABLED)
:,~
I ~~!!~I
-----;"""'<
IN
T2#
T3#
...-
T4#
CONTROL
SIGNALS
WLE
SEL
:
:
-;- ---: :I
(INAcTIVE)
.. .. .. "," .. .. .. ,- .. .. ..
:
:
:
~ ~;,CFA~~~. ~~T~:-
:
"
r .. .. .. , .. .. .. -," .. .. .. ,- .. .. .. c .. ..
---
(INAcTIVE):
I
,
I
i - - - ~ - - - -, - - - -,- - - - i - -
I
:~I:::=:;:====;====::::;::=::=::::::::!::==
: I" - - : - - - : - - - -: I
MAIN#
DEN#
SYSTEM
BUS
,
.. .. .. T .. .. .. ,
[~D~
SEL LATCHES
:I '
:
:U
BRDY#
.
\~
SYSADDR \ \ \
SYSDB
:
VALID (LATCHED)
:
f\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
-'-----'--I( . IN (LA~CHED) ; ) '
,.
Figure 18. Write Hit Timing
814-100
,
,
,
,
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
WRITE MISS TIMING
I"
:
.1
WRITE MISS
T1
:
T2
:
T3
:
T1
I
T2
I
T2
T1
I
T1
I
T2
CLK2
c~~""""",
I
ADDR
8~~r <
W/R#
INTERFACE
I
I
I
VALID
I
~
I
I
•
I
'
I
•
I
WRITE
DB
ADS#
)=:=====::READY#
SEL
~
READY
~ 'd~HE SEL....LE-CT-:i,Ir===::;::,==::::;:=~==:::::;:::==;====;::.:==
I
WE1#:
TAG
RAM
,
I
[
C~X~E[
CLR#:
:
MAT1:
:
W::
I VJi=\I!~1
I~
"
:
1---:-
:
MISs- ~
~
;
; LMI8.J
:
--IIrr IIrrl
rT"lf
(H~GH LEV~L)
---r---r------r---r------r--
(DISABLED)
WRITE I
,.----'---..&.,.
DB
, (HI-Z)·
IN
I
T2#
T3#
T4#
I
-
WLE
CONTROL
SIGNALS
SEL
•
•
(INACTIVE)
I
•
•
•
I
I
•
,. - - - i - - - - - - - -.- - - -.- - - - i - - - i - - - -. - - - - ,. - - - i - -
~
,
'LATCH ADDR,DATA
•
I
.,
:1
•
I
t
I
I
,
•
,
•
,
,
,
•
SEL LATCHES
MAIN#
DEN#
'--_ _ RDY2#
BADS#
BRDY#
SYSTEM
BUS
[
:U
:I
: VALID ~LATCH~D)
SYSADDR
SYSDB
i
NOT READY
--~:(
iN
(LAT~HED)
Figure 19. Write Miss Timing
814-101
READY
:111
:f\\\\\\\\\\\\\\\\\\\\\
:)
I
I
,
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPUCATION NOTE AN-30
READ LBA TIMING
READ LBA
I" T1
T1
X
X
X
1'2 :
n'
1'2'
'
1'2'
CLK2
C~~
ADDR
80386
BUS
<
INTERFACE
Wffi#
~
:~\\\\\\\\\\\\\\\\\\\\\\\\\\\
'READ,
DB
ADS#
,
, NOT READY ,
READY#
>===
READY
'(HIGH LEvEL)
,
-, - - - - ,. - - - r - - - ., - - - -, - - - - ,- - - - r - - - , - - - -, - - - -,. - -
TAG [ : : _ :. ___ ~ ___ ~ ___ .: ____ .~H~G_H _L~E~) _ ~ ___ .: ___ .'. ___ '. __
RAM
MAT1
,
-
,
1- -
-
-
-
,
.. -
,
-, -
DB
,
to -
-
,
CACHE[W::
RAM
----
(HIGH LEVEL)'
,
: (DISABLED)
,
_ , ____ L ___ oJ _ _ _ _ , ____ , _ _ _ _ ... ___ .I ____, ____ , ____ '- __
-
-
-I -
,
-
-
- 1- -
,
- - -,- - - - (' - - -
-
-
.. -
-
,
-
..
-
-
-
(HIGH LEvEL):
T -
- - -, - -
- - - - -
... -
,
-
-
,
- ,- - - -
-
-
-
,
r - - -
i
""
I
I
•
I
'~""
.\....::!...I
I
I
I
I
I
I
,
-1-
... -
-
,
- - - -,- - -
I
I
I
•
I
I
I
I
T2#
,
T3#
-,. - - - c - - - T - - - , - - -
T4#'
CONTROL
SIGNALS
,
, (INACTIVE)
-e -
_ ,____ ! ___
2, ____,,____ ,,_
-
.. -
1- -
-
-
..
-
-
_
-
_
-I -
-
-
-
-
-
RGT -, - - - -
C
OCAL::::
-
,
-
-
...
-
-
-
r - - - ] - - - , - - - -, - - -
_ .!,
____ , ____ ,____
~
__
-
-
...
_
..
,
-
-
... -
,
-
-
-1- _
-
-
,
-
: (INACTIVE)
-, -
BUS
- ,. -
: (INACTIVE)
RDY1#
80386
-
JI~~C!ly~)
- 1- -
WLE,SEL
DEN#
-
,-
:-1
-
-
-
..
-
-
-
.. -
.' ____ , ____ 'M ___
-
-
-, -
-
-
- 1- -
-
-
r - - - .. - - - -, - - - -.- - -
:1 - - - .- - - - ~ - - - -, - - - -, - - -
, (DISABLED)
!. ___ oJ ___ .' ____ '. ___ !. ___ .! ___ .' __ _
~~~c'~_-~-:~~_~_~_~2~_A_~_~_-~~~-~-=-~~~-~~'~R~E~A~D~Y~~'~~~~
ADDR \\\\\)
,
VAliD
-=--____~_
LOCAL DB ......:._ _
_!.._ _
:
~\\\\\\\\\\\\\\\\\\\\\\\\\~
~'~
Figure 20. Read Local Bus Access Timing
814-102
,
,
,
,
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
WRITE LBA TIMING
WRITE LBA
T1
T2:
X
X
X
T1
T1
T2
T2
CLK2
CLK~"""""
ADDR
80386
BUS
<
INTERFACE
W/PJI
~
'
'LBA '
i
i
WRliE
DB
[
:~\\\\\\\\\~\\\\\\\\\\\\\\\
i
,
,
READY#
TAG
,
OUT
ADS#
RAM
"
NOT READY ,
READY
WE1#
(HIGH LEVEL)
CLPJI
.. :........ ! ....... .! ........' ......... ~H~~H_ ':.~E:)
MAT1
(HIGH LEVEL)
,
-,'" ........ ,- ......... r ........ ., ....... -.'" ....... ,....... r ...... , ...... -, ...... -,- .. -
.. ' ........ L ....... .J ......... ' . . . . . . . . ' . . . . . . . .
,
i i i
~
.. ~ ...... _' ........ '_ ...... '_ ....
,
. . . . . . J ...... -' ......... '_ ...... __ .. _
(DISABLED)
:
i i i
i
.. 1- . . . . . . . . . . . . . . . . . . . . . . . . . . - I " . . . . . . 1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . - .............
CACHE[ W::
RAM
DB
'-----
,
,
,
,
'('
I
I
I ,
I
I
I
I
I
I
I
I
I
,
I
.,'" ......... , ........ r ......
,
·(HIGH LEVEL):
T ....... ,
. . . . . . " , " . . . . . . . .-
OUT
,
.......
,
T ....... i
')'
,
"
I
I
I
..
,
..
~
.. -.'" .....
,
,
I
I
I
r
I
I
I
I
T2#
T3#
T4#
CONTROL
SIGNALS
_: ____ :____
:
~
___ ; ____: _
:
:
:
,
,
,
:
I
JI~~?!ly~
(INACrIVE):
:.: : : : ; : :": ; : : : :. : : : :.: : : : .: : : : ; : :. :
WLE,SEL
RDY1#
DEN#
BUS
c:
OCAL
::::
ADDR
LOCAL DB
., - - - -:
-I
"
I
~
:
___ ; ____ : __ _
:
:
~
: :. : :,:' : : :. ..:. :. :.
:I -. . ,- -. . i
................ - , - .. ..
(INACTIVE)
:
(INACTIVE)
:
-,- ..... -,- ...... ro ................ .., .......
RGT
80386
I
_ :____
-1- ......
,(DISABLED)
r- ........
~
- - - i - - - -,. . -
,
..' ........ ' ......... '.. .. ..... ! .. ... .. ..' ........ ' ......... '.......... !. ........I
........ ' .......
~~~~_-~-:_·N_~_~_~~:~_~D_~_-~:~i~li=·~~~·~~'~~RE~A~DY~~'~~~~
-+\ '\:u. .Jo~\). 1. . .f-'------r-;::VA::::L::LID=:::::i:===~:~l. l. l~ ~'\~ . l. .l. ~'\~ . l. .l. '~\l. l. l~t;-u;'~!. l. .l.&.l.f'\u.l.~
~
....!...--!....----!..~('_......;..--IN..,...._-~:)
Figure 21. Write Local Bus Access Timing
S14-103
,
,
,
,
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
READ NCA TIMING
READ NCA
I~
T2 '
T1
X
T2'
T1
X
X
T2'
T1
CLK2
CLK~""""'"
•
I
I
I
•
I
I
I
I
I
,
,
~r: ~
INTERFACE
ADS#
READY#
, NOT READY
WE1#"
READY
, (HIGH 'LEVEL)
-," .... -.- ...... r ......
TAG [
RAM
,
,
T . . . . . . . . . . . . . . - . - . . . . . . ,- . . . . . . ,
CLR# _' ____ ~ ___ ! ____' ____ : _(~I~~ .~:V:L! :. ___ .! ____ ' ____ ' __ _
MAT1
OE#
(HIGH ,____
LEVEL) L ___ J ____ ," ____ , __ _
_, ____ ,to ___ 1 ___ oJ" ____ , ____
,
,
i
i
:
(DISABLED):
-1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1- . . . . . . 1- . . . . . . to
CACHE [
RAM
. . . . . . -. . . . . . . - , - .. ..
WE2#
~
DB
I
:
.
:
:
:
(HIGH .LEVEL) •
i i i
......
~
. . . . . . - I " . . . . -1- .. -
I
I
I
- - - -: - - - -:- - - - ~ - - - ~ - -~ - -:- - -(HI-i> - - ~ - - - -: - - -
""
•
I
•
'~""
I
I
I
I
I'
,
I
I
•
I
I
I
I
I
,
I
T2#
T3#
T4#
-:- - - - ~ - - - ; - - - ; - - - -:- JI~~9!ly~) - ~ - - - ; - - - ; - - - _:_ - :
:
,
I
I
I
: ,: : : : ; : : : ; : : : :
CONTROL
SIGNALS
WLE,SEL
..:
,(INACTIVE):
: : :.: : : : ...-
I
(INACTIVE) :
-I -
-
. . . . ,-
0:: :::::
BADS#'
BRDY#
[
SYS ADDR
SYSDB
I::::: :: :: :
(INACTIVE) :
RDY1#
SYSTEM
BUS
.- .- .- ..- .- : .- .;, .- .- .- .-,.-, .- .- .-.--, .- .-
-
.... p
. . . . . . ., . . . . . .
- I " . . . . . . 1- -
J:U (ENA~lEOI'
....
r - ..... - ....
-I ..
-
-
- , - ..
-
\=i'~'n:;:::::::!:=-I_....!·N_O_T_RE...!.Ao_Y_.t:I~"=:r::mm:;~';:;:R;::;EA:;:;D'v~::;::;=;!~~::;::;::-
~~~~\Ju--:----:-_VA-:-Llb_-:----::~~~~\~~~.l..l..~:u..l~~&"\~~~~~"\.l..l..~"\:u..l&~~\"\~~
~:____~__~____~__~~~~~-__~--~-~--
Figure 22. Read Non-Cached Addreaae TIming
S14-104
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
WRITE NCA TIMING
WRITE NCA
T1
T2:
X
X
T2
T1
X
'
T1
T2
CLK2
CLK~""".'.'···"
-
~
ADDR
80386
BUS
INTERFACE
<
W/R#
~
i
WRITE
i
DB
ADS#
[
i
t\\\\\\\\\\\\\\\\\\\\\\\\\\\
,
, NOT READY ,
READY#
TAG
RAM
i
OUT
READY
(HIGH LEVEL)
WE1#
,
-." ...... ,- ...... r ....... , ......... -." ....... ,- ......... r ....... , ......... - ......... "'.- .. -
CLR#
... :_ .......
~
.......
~
....... _: ........... ~H~~H_ L~E~) ...
"
MAT1
.. t_ ........ L ....... .J .......
i i i
.. t-
CACHE[ W::
RAM
DB
--'----
........
~
.................... -I . . . . . . . . . . -
,
,
(:
•
•
........ _' .......... : .......... :_ ......
.......................................... -1- ..............
. (HIGH ~EVEL)
-, .. .. ... ".- .. ... .. c ... ... ...
~
(HIGH LEVEL)'
,
,
,
_' . . . . . . . . ' ........... L ....... .a ....... _, .......... '_ ........ '.... _
,
, (DISABLED)'
,
i
,
T
... ... ...
1 .. .. ...
..!.. . . .. .. .- .. .. ..
'IN
..
:
r .. .. .. -. .. .. .. -," ... -
)'"
T2#
T3#
T4#
. :. - . -
............
CONTROL
SIGNALS
I
I
~
[~
SYSDB
. . . . . . . -, ............ 1- . . . . . . .
~: ~ ~ ~ J ~NABLED)
,
:U
BRDY#
SYSADDR
I
I
(I~~~~~) ~
(INACTIVE)
-, .......... ,- . . . . . . . . . . . . . . 1
SYSTEM
BUS
,
(INACTIVE)
RDY1#
DEN#
,
- - . ! . - - .' - .........
- - -'1-. .
• - • - ! - . . .' . . - .' - - .
......................................... _1_ ........ to- .. ..
to .................... -I'"
WLE,SEL
RGT
I
.: •••• ~ __ • ; ___ ~ ____ :. JI~~o/lyE) _ ~ _ • _ ; __ • ~ • __ .: __ •
VALID
~
...... -, .......... ,- .. ...
1~ ~:~ ~ ~ ~ :~ ~ ~ :~ ~ ~ ~:~ ~ ~
,
, NOT READY ,
\%\l '
:
r ......
,
,READY,
:
&\\\\\\\\\\\\\\\\\\\\\\\\\\\
:.
-~------~~(~'
_: ______~______
IN~: ______~"-J)
.•
'
Figure 23. Write Non-Cached Addresse Timing
S14-105
_.....
_--_.._----_...._----
,
,
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
BHOLD/BHLDA TIMING
, ,
,
N,
,...-.;
"
......""T""""'----'-----'--4---'----'----'----'-.............
BHOLD
--,---"",!"'"T~: :
::: : : : : : : - :
~
L
=: :,; ==: ::: : : ::: -~.~.~.-;:L:-;::=:::t:==;::::::t=::::i::=
INTERNAL~::: --'-:--""':-+--....L..., ... '.. _. : ... ~ ....:.... :.... : : : : ; ...
J.
~ ••• .!
'..I.--.:...._-+-_ _ _ _ _ _ _ _-...:.._ _....:..+_.....;..!...J,
--'-_ _........._--1"--_........... L • • • J • • • • ' • • • • ' • • • • L • • • J
SIGNALS
•
BHLDA#:
BHLDA
N REPRESENTS
lWO 80386 CYCLES
FROM BHOLD ACTIVE
TO BHX# ACTIVE
,
• • • oJ • • • • ' • • • • ' • •
:
: i : : : 1
.
-r--i"---'--
.:.:::.::.:.: 1_:+=±==t::=:±==i::==±+==~I==t:..J
'.,
CERTAIN CACHE
OPERATIONS DISABLED
DURING BHX# ACTIVE
Figure 24. Hold and Hold Acknowledge Timing
S14-106
CERTAIN CACHE
OPERATIONS NOT
RE-ENABLED UNTIL
BHY# DE-ACTIVE
: =:= =
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
ClK2
---
---
---
---
~I
.---
ClK
ADDRESS
BUS
, ADDR
ADS#
• J _______ 1 _
-J'-----'-.....J _____
,
!. _ _ _ _ _ _ _ ,__ • __
,
tAA
... - - . - - - -
~
- - .. - - -
~
. - - l - -...------4~_
DATA BUS .........- - - - - - - - - -........-~J
-
,
of
-
-
-
-
-
-
-
+ - - - - - - -
to
,
tOS
-
-
-
, DATAIN
f---_------4:o::\-...J.
SPEC ANALYSIS
80386 Clock Rate
Parameters
Units
16MHz
20M Hz
25M Hz
tClK
62
ns
50
40
- - -- - - . -- - - - - . - - - . - - - - - - - - - - - . . -- ns
tAD
40
35
30
--. ---- -------------. ------- -- ---tOS
10
ns
10
5
- - . - - - - - - . - -- - . -- - - - - - - - - - - - - - - - - .
tAA
72
55
45
ns
Figure 25. Cache Memory Timing
S14-107 .
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
ClK2
--.
---
.
.-.
-.tCLK.
tcLK
----
ClK
ADDRESS
, ADDR
BUS
ADS#
,
,
- , - - - - - - - T - -I'----.,.--J - - - - -
r - - - - - - - ,- - - - -
- - : - - - - - - - : - - - - - - - - : - - - " \ t - - - ~ - - - - - - - :- - - - -
MAT1
: CACHE MIsS :
- ~ - - - - - - - ; - - - - - - - ~ - - - t ....-~~----___:_--t19
_ J _______ 1 _______ L ___ l~t:-:!~~'t!:::j~---
80386
READY#
NOT READY
---' _ _ _ _ _-"'" _ _ _ _ _....... _ _ _ _ _........_...J _
_ _ _ _ ... _ _ _
SPEC ANALYSIS
80386 Clock Rate
Parameters
tClK
tAD
Units
16MHz
20MHz
25MHz
62
50
40
40
35
- - - - - - - r - - - - - - - - - - -. - - tADM
tF64
58
6
48
6
-------~--------------
t19
20
11
30
------34
6
ns
-----ns
ns
-----------10
ns
Figure 26. Cache Tag and SNOOP Timing
S14-108
ns
_
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
Top Level Diagram Description and Operation
Figure 27 illustrates the top level diagram of the cache controller
and memory module. The block CRAM is the cache memory,
TRAM is the cache tag for the local bus, SNOOP is the cache tag for
the system bus (SNOOP tag), and CTRL is a PAL based state
machine which controls the. timing and state sequences for
interfacing to; the cache memory; the SNOOP and local cache
tags; and the system and microprocessor buses.
l...oL
....
...
A (2:14)
D (0'311
-
.::
CRAM
SBEO#
SBE1#
SBE2#
SBE3#
WE2#
OE2#
A (2:14)
D (0:31)
MAIN SYSTEM
BUS PINS
MEMORY CONTROL
PINS
SBEO#
SBE1#
SBE2#
SBE3#
WE2#
80386 BUS PINS
m:~
SNOOP
BA (2:31) ......
MAT2 "'"
WE1# ......
WINV# ~
ClR# ~
....
A (2:31)
-'"
...
R!=O#
BE1#
RF?#
J::
z:
f"
~F~
'"
...
l...oL
BEO#
BE1#
BE2#
BE3#
..
)Y#
JET
LBM
FIII~~
LRDY#
Nr.A#
CONTROL
INPUTS
TRAM
A (2:31)
J:: D/C#
z: M/IO#
W/R#
~
ADS#
READY#
J::: ClK
-'" RESET
ff:
...'!
LBM
J::: FLUSH#
z: LRDY#
NCM
.
BA 12:311
MAT? to.
WE1# ,..
WINV#
CLR#
MAn
WE1#
WINV#
CLR#
CE1#
CTRL
SBEO#
SBE1#
SBE2#
SBE3#
BADS#
WE1#
WINV#
WE2#
OE2#
BHLDA
WLE
SEL
CLR#
BRDY#
MAT1
MAT2
BHOLD
BW/R#
DIR
DEN#
CE1#
""""
~
~
~
MAT1 ..
WE1# ,..
WINV#
CLR#
C!=1#
"'"
BUS BUFFERS
CONTROLS PINS
..
~J::\I::(){'!
S8E1# t:
~~r::~ t:
';:~I
~
,..1:
...
BADS# ..
WI:1#
WIN\I# t
WI?iI<
,..
n~-r
~I~
BHLDA ...
WIF :.
SEl J:::
-'"
..
-~
RRnVft
MAT1
MAT?BHOLD
RW/~
[jl~-
IFN#
~F1#
...
,...
Figure 17. Top Level Diagram of the Cache Controller Module
S14-109
RHlnA
...
..
z:
...
to.
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-30
TRAM Block
Figure 28 represents the connections of the local address bus
(80386 address bus) to the cache tag SRAM (CRAM). A(2:31) are
the address lines which come directly from the 80386 address bus.
The cache tag is addressed using address bus bits A(2) through
A(14). A(15) through A(31) are the address bits that are recorded In
the memory of the cache tag. MAT1 is an input to the cache
controller Indicating a hit or a miss.
CE#1, WE#1, CLR# and WINV# are control signals which come
from the CTRL block (the Intemal PAls) to the cache tag . WINV# Is
used to Invalidate a write entry In the cache. For instance, for an
80386 write cycle, the controller will start to write data to the cache
and main memory at the same time. However, if it is determined
later on in the cycle that a write miss occurred, the WINV# signal
will write a logic low in the 24th bit of the tag which invalidates the
tag address at the cache's page offset location. CE#1 Is used to
keep non-cacheable addresses from entering the tag. If a
non-cacheable address Is detected (via the NCM Input), CE#1 will
be disabled which In tum floats the 1017174 cache tag's 1/05. The
CLR# signal Is an Input signal to the tag and the SNOOP and Is
used to flush the cache on SNOOP hits.
CRAM Block
Figure 28 illustrates the cache memory which is used to store
the associated data of the tag addresses. The cache memory
consists of four 1017164 8K x 8 SRAMs. A(2:14) are the same
address lines that address the cache tag memory of Figure 27 i.e.
the microprocessor address bus. 0(0:31) is the 32 bit data bus of
the 80386. The data bus is divided Into 4 bytes with each byte being
stored in a unique 1017164 SRAM.
A (2:31)
1DT7174
1/01
1102
1/03
1104
1/05
1106
1/07
1/08
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
+5V
c~
200 OHM
MATCH
RESET#
CS#
OE#
WE#
IDT7174
1/01
1/02
1/03
1/04
1/05
1/06
1/07
1/08
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
MATCH
RESET#I'"
CS#
OE#I'"
WE#I'"
IDT7174
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A (311
1/01
1/02f1/03 H~
1/04
1/05
1/06 H~
1/07 HI- +5V
1/08
~~
MAT1
MATCH
RESET#
g~1'"
WE#I'"
+5V
CE1#
WE1#
CLR#
WINV#
Figure 28. Cache Tag Block (TRAM)
S14-110
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
D (0:31)
A(2 :14)
IDT7164
AO
A1
1/01
1/02
1/03
1/04
A2
A3
A4
I/OS
1/06
1/07
1/08
AS
A6
A7
A8
A9
A10
A11
A12
SBEOII
CS1#
CS2 t-+SV
OE#
WE#
1DT7164
1/01
1/02
1/03
AO
A1
A2
A3
1/04
I/OS
A4
1/06
1/07
1/08
AS
A6
A7
A8
A9
A10
A11
A12
CS1#
CS2 i - + SV
OE#
WE#
l
SBE1#
IDT7164
1/01
1/02
1/03
1/04
AO
A1
A2
A3
A4
I/OS
1/06
1/07
1/08
AS
A6
A7
A8
A9
A10
A11
A12
CS1#
CS2 ~+SV
OE#
WE# .....
SBE2#
IDT7164
AD
A1
1/01
1/02
A2
1/03
1/04
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
I/OS
1/06
1/07
1/08
CS1#
CS2 -+SV
OE#
WE#
SBE3#
WE2#
OE2#
Figure 29. Cache Memory Block (CRAM)
SBE(O#:3#), WE2#, and OE2# are signals generated by the
CTRL block (Figure 34) which control the operation of the cache
memory. SBE (0#:3#) are used to select a specific byte of the 32-bit
doubleword via their direct connection to the IDT7164s. In the case
of a read miss, if the microprocessor wants to read just one byte
instead of the full 32-bit doubleword, the, controller will update the
entire 32-bit double word in the data cache (so as to ensure valid
data in the cache). In orderto update the full 32-bit doubleword, the
force byte enable signal, FBE#, is gated with the byte enable
signals, BE(O#:3#), of the 80386 to. form SBE(O#:3#) as shown in
Figure 34. WE2# and OE2#, from the CTRL block, are used to
control the read and write operation of the cache memory.
S14-111
m
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
SNOOP Block
BA(15:30) is the address recorded in the SNOOP. As mentioned
previously, the design of the controller module Is such that the
SNOOP and the tag always contain the same information.
The SNOOP (Figure 30) is very similar to the tag. BA(2:31), the
system address bus, Is the main memory address bus that the
SNOOP monitors. BA(2:14) is used to address the SNOOP and
BA (2:31 )
IDT7174
AD
A1
+5V
1/01
1/02
1/03
1/04
1/05
A2
A3
A4
A5
A6
A7
A8
A9
A1D
A11
A12
> 2000 HM
- +5V
1/01
RA
IDT7174
AD
A1
(~1\
1/02 1/03 -:""1.
1/04 -:""1.
1/05 -:""1.
1/06 ~.
1/07 ~"'+5V
1/08
A2
A3
A4
A5
A6
A7
AS
A9
A1D
A11
A12
MAT2
MATCH
RESET#
CS#
OE# ;}- +5V
WE#
-l.-
WE1#
-
e
CLR#
WINW
Flgur. 30. SNOOP Block (SNOOP)
The WI NV#, CLR# and WE1# signals are used In the exact same
way as the tag memory of Figure 28. Functionally the only
difference between the tag memory and the SNOOP memory Is the
fact that the SNOOP memory Is always monitoring the main
memory address bus.
'
The only output of the SNOOP block Is MAT2 which ties directly
to the control block to indicate a SNOOP hit or miss. On a SNOOP
hit, the cache controller will flush the entire contents of the tag
(TRAM) and the SNOOP ta~ via the clear line (CLR#).
S14-112
I
ITHE COMPLETE HIGH PERFORMANCE CACHE
,SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
a PAL based state machine. For this design, three 22V10 PAls
were used (Figure 32) to form the PAls block of the controller In
Figure 31.
As shown In Figure 31, the READY# Input Is generated by the
use of the 74F64. For Figure 31, It should also be noted that all
inputs to the PAls block are on the left side, all outputs are on the
right side and buses are represented as dark vertical lines. For
Figure 32 it should be noted that the pin out are shown for 28·Lead
PLCC packages.
The designer should use caution If he plans to Implement the
PAL design given In this application note. In particular, the pin
assignment should not be changed. This is because the internal
structure of the PAls may not accommodate a term swap between
pins. For example, if the Signals WINV# and DIR of PAL1 (Figure
32) were Interchanged CNINV# to pin 19 and DIR to pin 17), the
JEDEC fuse map will not run because pin 17 does not have enough
inputs (internally) to handle the equations for DIR.
Posted Write Logic Design and Operation
The posted write logic comes into action when a write occurs.
For the posted write operation, the IDT74FCT646 octal transceiver
registers are controlled by the WLE (write latch enable), signal. The
WLE line, on a microprocessor to memory write, latches the data
and its address into the 646s and continue on without wait states
while the cache control logic downloads the posted write buffer to
main memory (the posted write operation can not be interrupted by
an external system bus request i.e. it is locked). In a case where two
write miss cycles occur back to back, the 80386 will have a number
of wait states depending on the main memory access time.
For a write hit, the timing (Figure 18) is the same as that of the
read hit (Figure 16). For a write miss however, the bus cycle is
extended by an extra clock period (Figure 19).
Design of the Cache Controller Block (CTRL)
The design of the cache controller requires determining the
state machine cycles of the 80386 and replicating them through
TAG &
SNOOP
INPUT PINS
CRAM
80386
F10
"\....
BEO#
INPUTS
...--
BE1#
r-~F08
SBE1#
BE2#
It-k'
SBE2#
BE3#
It-F<
SBE3#
.... L..-J'
F11
NCA#
TAG &
SNOOP
MAIN
BUS
CE1#
SBEO#
D/C#~'
MIIO#
lBA#
W/R#
ADS#
MAT1
BRDY#
BHOlD
PALS
f-
1-1-.
r-
FlUSH#
BW/R#
MAT2
F04
ClK
~
"'"
RESET
NC#
LBA#
W/RIF
ADS#
MAT1
BRDY#
BHOLD
RESET#
lRDY#
FlUSH#
BW/RIF
MAT2
ClKB
BHLDA
FBE#
BADS#
WE1#
WINV#
WE2#
OE2#
WLE
SEl
DIR
DEN#
RDY1#fRDY2#
RGT H T4# f-tClRIF
~
lRDY#
1 -74F04
1 -74F08
1 -74F10
1 - 74F11
1 -74F64
MAIN
BUS
BHLDA
BADS#
WE1#
WINV#
WE2#
OE2#
WlE
SEl
DIR
DEN#
DATA &ADDR.
BUFFERS
ClRIF
lF04
~O
r
'--
~h
80386
~U-~
~
74~
9"
Figure 31. The Controller Block (CTRL)
S14-113
OUTPUT PINS
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
INTERNAL BUS
PAL1
PAL2
22V10
NC# 3
4
5
~
ADS# 6
7
9
~
BHX# 10
BHY# 11
12
~
BH~ 13
i-- 16
~
~
;r
2
PAL3
22V10
27 ~~
26 MAIN#
25 T2#
24 ntL
~
23 T4#
21 ~
WE2# .~
20 ~~
19 ~~
18 ~~.
17 ~~:
NC#
IBM
W/R#
ADS#
MAT1
BRDY#
BHOlD
lRDY#
RESET#
T2#
MAIN#
3
4
5
6
7
9
10
11
12
13
16
22V10
27
26
25
24
23
21
WlE
SEl
RDY1#
RDY2#
0E 2#
RGT
20~~
BHY#
198Ht[5'A~
17 DEN#
18
-2
••
RESET#
BHLDA
BW/R#
BADS#
MAT2
FLUSH#
3
4
5
6
~
10
~ 11
~ 12
13
.~ 16
r---
....--
27.QJ..B.1#
26~2#
25~~
242321-
20191718-
-'-
r-2
IN PUT
PINS
OUTPUT PINS
ClK B
PINS ARE FOR 28-lEAD PlCC PACKAGES.
Figure 32. The PALs of the CTRL Block
S14-114
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN-3~
PAL Equations
The equations for the three PALS are presented in Tables 2
through 6. The PALASM source code for the PAls is also given for
generating the corresponding JEDEC fuse map.
INPUTS
I
I
I
•
I
I
INTERNALS
I
I
I
N,L,W,A,M,B,B, B,B,
C,B' /'O'A'R'H'H'H'
#'A'R'S'T'O'X'Y'L'
'#'#'#'1'Y'#'#'O'
SIGNAL
NAME
: : : : :*: : :A:
1-._....F
....B....E_#_4-
H, H' L'
,L,
i~ i.~
H:- Ii: -L~ - :
,
I-._ _
M_A_IN#_--+
,
,
,
~:_ ~: _H_: _ !
H'
H' L'
.. 1 _ _ I .. _,
..
,H,
,I'
, H,
,
,H L'
.. ,L,
,
i
,
- T -
,H
_!. _ ,__ :_ ~: _ .! _
'L'
J ... L ..
,1_ _ 'H'
,
, _ _ ' ..
~
H'
H' L' 'L' L' H'
... 1_ _ ' . . . . . . . . . . . L . . . . . . . 1 _ _ I ...
"
~
, H'
H, H, L,
,
,
".- -.- -, .. , .. r .. ,- -.- -."
H, H, H,
,
,
,
,
,
i
,
, L,
L:
I
:
H:
,
-. ..
I
I
I
.. "
....... , _ _ I . . . . . . .
.. T
.. .. .. ,- -,.. -. ..
"
,
,H
,
... ,- .. I" - , " ,
,H
L,
,H
I
, L'
T ..
... T ..
I
-,..
, ,
r -.- -.- -,-
~:~ ~:~ ~:~H~ ~ ~ ~ ~ ~:~ ~:~~: ~
..
H
.. ,. .. ,-
-.- -.- -,- 1 " T"
, 'L'
, H L'
... 1_ _ 1 _ _ ,... .J
.L ..
"
,
, H' H,
., .. T
, L, H,
-,..
J ..
r ..... -,- -." ., ..
,L, H,
'H
.. I "
..
, L,
+ -.- -,- -. .. , ..
L...._ _ _ _
~ ~
OESCRIPTION
#: '
H:- -: - ~ - : H
- ,- -, - -, - , - r - ,- - ,- -, -
T2#
:R T:T:T:M:F:O:
,E 2'3,4'A'B,I,
'S #'#'#'I'E'R'
'E
' , 'N' #' ,
: T
:
...-
L.
•
-,'"
,
..
_1_
L .. ,__ , __ I
..' ...
H' H' H'
..
~
..
, L'
T .. .- ".- -." - ...
• L. • •
-:-L:":":~
L,
,L,
, H,
I
, H
,H
_S~~ ~ ~~e.: ~~n.
_____ ____
~~~ i!~C!':.~a~n _________
_
_S~~ ~ ~e~d_ ~i~s._ B_H9~ ____ _
Stay if Write. BHOLD
.. 1- .. 1-
H, H, H,
I
L'
L'
T4#
I
1 ..
, H
Read Miss. no Main
-----------------Read Miss. Main
------------.. ----Stay until Ready
_S~~ ~ ~d _Mjs~. _n~t _R~y______ _
-:- -:- -: .
~:~~:~~: ~ ~ ~.~ ~:~ ~:~ ~:~~: ~ ~ ~ i:- -:H' H' L' 'L' , 'L' , 'H
J ..
~:~ ~: ~ ~: ~ ~ ~ ~ ~ ~ ~:~ ~: ~ ~: ~
.. ' ..
Write
AOS
,L",
.. I "
Read Miss. no Main
------------------Read Miss. Main
------------------Stay until Ready
L.
,
H'
I
- I " .....
+ ..
~
..
,L,
, H,
1-
- , ..
"
, L,
T2.Rd Miss. no Main
-II -
------------.. ----T2.Rd Miss. Main
-----------------..
T2.Wr Miss. no Main
T3. Read
H
Stay until Ready
Table 2. First Part of PAL1's Equations
Tables 2 and 3 show the equations for PAL1. A horizontal line in
these tables means an AND function between the present terms.
FBEI
=
NCI. LBAI •
+
WiR# •
The lines grouped together for a signal are ORed vertically. As an
example, the logic equation defining the signal FBE# is as follows:
MAT1 • BHY' • RESET# • T2# • MAIN# • FBEI
NCI. LBAI • W/R# • MAn. BROY# • BHX# • RESET# • T2# • 'MAi'N# • FBEI
+
BROY# • RESET# • FBEI
Bared signal
Unbared signal
logic low level
logic high level
Each line is accompanied on the right hand side by a short
comment describing the situation to which it relates.
S14-115
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
INTERNALS
INPUTS
:R
'E
'S
'E
SIGNAL
NAME
T:T:T:M: F:D:
2'3'4'A'B'I'
#'#'#'I'E'R'
' , 'N' #' ,
:T
:
,#
H, H, H,
WE1#
,L,
,
,H,
, H
' - - - - - - t -.- -.- -.- i .. i -,- -.- -.- -." i"
H, H, L,
,L, , , , , ,H
~
i . { ., . ., . ., . i
I
:!i
.,.:!i
I
H, H, H,
,H,
,
,
,
,
,
I
•
I
I
I
I
I
I
I
I
I
I
.. 1-
, H,
,L,
,H
-I"
-I"
Ij:..:.
'H'
.. 1-
..........
,
,
".- -." -. .. i
,
..
.. '..
'H
_I . . . . . . . . . . . .
~:.t-!: ••, . , . ~ !-~Ij: .., .
L, H,
•
~
..
Y
..
,H, L,
.,. ~!i
,
r ...- .. ,- -." -. ..
,H
i"
r
.. ,- - I " -t ..
Miss, no Main
._Write.. --.------------Read Miss
Stay until Rd Miss, Ready
Write Miss, no Main
"
.. I..
..'..
_1 _ _ 1 _ _
.. , -
-,-
:_H~
, L'
-I"
.,
'- .'•• ' ••'.
, , , ,
~ .. '..
...........
..'.. ..' ..
_1 _ _ I _ - t _
Read Miss, no Main
------------------Read Miss, Main
.. ---- .. ---------- .. -NCA, no Main
------------- .. ----NCA,wait for Main
..
"
..
r
.. ,- -, .. -. ..
, H,
".-"." -." i
Read Miss
Stay until Rd Miss, Ready
, H,
L,
,
~
I
, L' L'
~:. H.:. L.: • ~ .L~ • ,.Ij:.~: ..' . ~ !i ~'•• ' ••,.H.!.!.
L' , 'L' ,
~:.t-!:.L.:. ~ .L~ ~~
~. ~ tl
oJ .. .I. ..
L'H'
'L'
.. 1- _I .. · ... ..
I
Write,ADS
, L'
,H
WINV#
,
L.
-- .. --------------
L.o.. ., • • , . . . .
~:.H.:.L~. ~ .L~.o- ., •• , •
,-__B_A_D_S#_~
#: '
H -,- -I-L't- L:";" ,- -.- -,- -,-
H:. H·: ·l' . .
,-__W_E_2#_-I-~:.H.:.H~.L~.
L,
DESCRIPTION
---------------- .. -NCA, after BHOLD
.. i
...- ".- "," - ...
------------------Write, no Main
~".H.".H.".L." ••,'.,'.Ij,'.~,' ..,' ..,'!i
' , ,H, , , , , ,
~,.t-!,.H.,. l . ~ !-,.Ij,..'. oJ.!!i •• ',.. ..',.. ..', ·.L·.,' .• . ', .• ',. •. ".. ..".. .." •.
-------------------
H' H' H'
Write, after BHOLD
, L' H' L'
, H
' H'
.~ri~e,.",,:a~f9r.M.ai!l • • • • • • • • •
DIR
' H' H' L'
, H'
, H
' H'
Write, no Main
L-~~__~~~~~____~______~------~______- - + - - - 4 · · · · · · · · · · · · · · · · · · ·
, H' H'"
, L' H'
, H
' L'
Write, wait for Main
I-"T"""'"-r--'-T--,r-.....-':;;'-..,.--,.--...--.-+--.-r--"T"""'":;;'-....,.--,r-.....-'-r-..,.-+ • • • • • • • • • • • • • • • • • • •
1--,---:-,_':""",---::--:-'_H;..;..,...'---,,--::-=L.,..'_',.....;..H+--:-,_,--.,...---:-_:-'..:.H.:..;:--:---:----:--+
H, H, , , , ,L, , ,H L, , , , ,H, , "
. ,., H'·
H' . ~ . ; L. ,. ;{ c:· ., . ~ H . ,.. ,..,.H·' • i L. ;- . ,.. ,..,.
Table 3. Second Part of PAL1's Equations
S14-116
~~~ l!~1 !I~a?~ (~~ ~H) • • • • • •
.S~~ l!n~1 ,!3~c?L?
Write, after BHOLD
........ .
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
INTERNALS
INPUTS
SIGNAL
NAME
,R
,E
'S
'E
'T
N' L'W'A'M' B' B' L'T'M'
C:B: /:D:A:R:H:R:2:A:
#,A,R.S. T.D.O.D.#. I.
.#·#,#.1'Y.L.Y. ·N.
'#'
D'I #'I '#'
I
I
I
I
::#
WLE
H, H, H, L,
,
,
,
,
,H,
'H
SEL
H. H. H, •
H' H' H' L'
,L.
• ,
•
,
•
•
• L.
'H'
,H
H
' - - - - - - - t -.- -,- -... i ... r ...- -,- -." -... i ...
' - - - - - - - t .. ' ... -' ....' ..
J ...
,
.. 1_
-I"
,
......
..
.1 ...
P
I
,
.....
~
",'"
-."
•
'
•
,
I
I
I
I
,
,
,
• -:-
,
•
,
•
,
•
,
•
,
•
,
i ... i .. ,- .. ,- -,- -, -
•
,
~ .. .... ' ...... ' ... J ... 1 ........ ' .. _' ......'_
. •~ H'~~ . . :,.....:, . ~, . L:, . 'H
~ ~_ . :....:. ~ . : . . ~ . . :..... :. . ~_
' , , 'L' H' , ,
4
...
L
... t-
.. 1_ - I " . . . . + .. L
H, H, H'
• L,
..... -1- - I " ..... + ....... 1- - I " ... -
• H
,L,
DESCRIPTION
I
,
~:_~:_H~_ ~
,
!.. .. '.. _' ...... 1 ... ~
B'B'R'R'B'S'D'R'
H:H:D:G:H:E:E: D:
X,Y,Y,T,L,L,N,Y,
#,#,1, ,D, ,#,2,
'#"
A'
, #'
Write, no Main
-- ..
----------------
Write, wait for Main
Write, no Main
------------------Write, wait for Main
------------------
.S~~ ~n~I.R~.?~ ~n~ ~H) • • • • _ •
, H,
Stay until BHOLD
Write while Main
-.. ---------------_S~~ ~n~I_R~a.?~ • ________ _
Write while BHOLD
~~~ ~n~1 !e!e~~
________ •
NCA, Main
------------------NCA while BHOLD
------------------NCA while BHOLD
RDY2#
H, H, H.
,L'
'------+ - ,- -.- -: -H:
,
•
,L, H,
-: -.- -.- -, - -, -
• H H, H,
i - ~
H- -.- -. - i
,
,
,
,
,
- i - .- -.- -.-
,
C: -
T2,WrMiss, no Main
------------------Stay until next ADS#
:H
OE2#
Read Hit
Table 4, First Part of PAL2's EquaUons
INPUTS
SIGNAL
NAME
INTERNALS
N: L:W:A:M:B:B: L:T:M:
C, B, /.D.A,R,H, R,2.A,
#'A'R'S'T'D·O'D'#' I'
'#'#'#'1'Y'L'Y' 'N'
I
•
•
I
:
DESCRIPTION
*: 0: *: :*:
, ,
,
, H•
L:H: . L,
L:
'--_RGT
_ _ _+~-~~~-~~~-~~~-~,-H+-H~:-~-,~L~·-~~~~~4~~~~~----L:H:
L' H'
,
,
H H: L:
, H H'
• L:
, L'
NCA after BHOLD
- - - - - - - - _NCA,
_ _ _wait
_ _ for
_ _Main
_ _
t--'--:"'--'--:""":""-:"'--'--:"-":""":"''''':''--1-':''''-''':--:'''--'--:'''''':''''''':'''--=--+ -
L'
L' L'
I--'-.....L.--I._.L...--'-....L.--L_L..-...L-..:..L........L-I_"--'-.....L.--I._.L...--'-....L.--L~
'L'
'L'
_I.. ... ... 4
.. 1_
...
..
-
r -
'H'
-1-
-1-
,L,
.. ...
......
_I..
.. ..
•
-1-
-I -
... -
....
..
, H'
... -
,
.,
"
~
,H"
,.. H
... _
, H
.. , H
~
' _L'..
_ 1_
_I..
..
-1-
-I -
..
' H'
- ..
, H,
_
..
_ 1_
_. _
.. _
-
...
-
-1-
... -
1-
BHX#
-
- -
_____ _
-
-
-
-
-
-
_ _ _ _ _ _ _ _ _
LBA
~~ ~~A_u~ti~ ~~~y _______ _
Stay LBA until Ready
BHOLD, no Main
------------------BHOLD, Main
stay until ;'0 BHOio - - - - - - - BHY#
BHLDA
.. 1-
-I"
... -
.,
..
..
-
...
.. 1- -I -
.. -
..
..
• H.
DEN#
H, H, L,
,L,
,
i:
,
, L, H,
• H L'
'H
'L'
... .. - - I - -I • H
,H
One cycle after BHX
.. ..
to
.. ..
- 1- - I -
.....
• H.
,H,
,
,
,
,H,
,
'-------/'" H:- H:- C: - : L:- -:- . -: -L: - : H.. -: - -:. : - : .. :- -:- -: - -: ~:~ ~:~H~: ~L~ ~ ~ ~:~ ~:~ ~ ~: ~H ~ ~ ~ 8~ 8: ~ ~: ~ ~ ~ ~ ~ :~ ~:~ ~: ~ ~: ~
, H' H'
.. I. _I _
.. _
,
-.-
-I -
... ..
L, H. L·
'L'
,
,
,
,
...
.. 1-
.. .. L .. ... .. 1_
L' H' L' L'
..
-
~
-
• L,
•
'L'
'H H'
,
,
,
,
,
,
,
.J _ .L _ L .. . . . 1_ .1 _ .J _ .L _ L. _ 1_ _ I .. .J _
'H'
.... -
•
• L.
'H
-
...
-
'H'
•
-1-
-I.
~
-
... ~
1-
-I"
Read Miss, no Main
------------------------------------Write, no Main
------------------Write, wait for Main
------------------Read Miss, wait for Main
Read NCA, no Main
, H'
-
~~Y_~!n_~e~dy _________ _
Stay until no BHOLD
.. -
-------------------
Read NCA, wait for Main
• H
-------------------
~~y_u!'~ ~e~y
__ '________ _
Write, after BHOLD
-------------------
NCA, after BHOLD
Table 5. Second Part of PAL2's EquaUons
514-117
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
APPLICATION NOTE AN·30
INTERNALS
INPUTS
SIGNAL
NAME
C:L, C:L,
R:B:B:M:B: F:
E,H,W,A,A,L,
SILI/ITIDIUI
E I OIRI2ISIS'
T'A'#' '#'H'
#: I I I : #:
RI RI
l' 2
DESCRIPTION
I
#:#:
Snoop Write while BHLDA
CLR1#
LI
CLR2#
CLR#
H,
'------t- .
I
I H,
I · . , • •, •
HI
I
I
,
I
•
•
r •
I
I
I
I
I· . , • •, .
I
I
I
'I
"'I •
I
I
T •
I
H:- -: - -: - : - : L.:- -: - -:.. -: - : ..
L:" .. :- -... i .. - ,- ..
~
I" - , "
-, .. ;
-
Write Hit while BHLDA
L.
I
I
I
.. ,- "," -, .. , - T - i
',L.
I
I
•
I
I
I
Write Hit while BHLDA
I
.. ,- -," -, ..
I
I
I
-I- .I - -I - -I - .I - -I - - I- -II
.. I.
_' . . .' _
I
I
~
I
,
..
! _ '. _ '... ' ...' ..
I
•
I
I
•
.S!S~ ~n.? !ll?~ ~y:l~ ••••••••
.~~I1]a!~L'd~H. '• • • • • • • • • •
System RESET
Table 6. PAL3's Equations
These equations were developed by closely analyzing the
logical timing diagrams for the 80386 under all the possible states.
A combination of several of these states following each other were
also looked at. The timing waveforms for the controller were then
developed In order to meet Its specifications and handle the 80386
operations. Once the timing waveforms were done then the
equations were derived and the PAls programed.
The software PALASM was used to compile the equations for
the PAls Into their corresponding JEDEC fuse map. The source
code for each PAL's program Is presented below. The
nomenclature In PALASM Is somewhat deceptive In that an
apparently logical "high" term might mean a logical "low". In the
pin declaration part of the source code an active low Signal Is
represented by a .. preceding Its name. In the description of the
equations, however, if a term Is written as It was declared (in the pin
declaration) It will be perceived as a logic high, yet if the signal Is
written in the opposite sense than In the declaration then PALASM
understands it as a logic low.
Keeping the above In mind, It will become clear to the reader
how Tables 2 through 6 match their respective PAL code.
S14-118
r
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE
APPLICATION NOTE AN-30
+
Controller1
N.A.
XNC * ILBA * IRESET * T2 * MAIN
+
/XNC * ILBA * W R *./MAT1 * BHY * IRESET * T2
+
-
1.1
Mammad safai
Integrated Device Technology Inc.
09-21-1988
/XNC * ILBA * /W_R * BHY * IRESET * T2
CHIP CONTROL_PAL1 PAL22V10
T3
IMAIN
;PINS
;1
2
3
4
5
6
7
8
9· 10
CLKB IXNC ILBA /W R lADS MAT1 IBROY IBHX IBHY IRESET
;11
12
13 14
15
16
17
18
19 20
BHLOA GNO NC /WINV IBAOS OIR /WE2 /WE1
;21 22
23
24 25
IMAIN IFBE VCC GLOBAL
+
GLOBAL.RSTF
OIR
WE1
: = IBHX * ILBA * /W R * ADS * IRESET * IMAIN
-
IBROY * IBHLOA * IRESET * OIR
ILBA * /W_R * BHY * IRESET * T2 * OIR
WE2
+
ILBA * /W R * BROY * IBHX * BHY * IRESET * IMAIN *
IOIR
-
: = IXNC * ILBA * W R * IMAT1 * IBHY * IRESET * T2 *
IMAIN */FBE
-
+
/XNC * ILBA * W R * IMAT1 * BROY * IBHX * IRESET *
T2 * MAIN * IFBE
+
:= IXNC*/LBA*/W R*/MAT1 */BHY*/RESET*T2*
IMAIN
-
: = IXNC * ILBA * /W R * ADS * IRESET * IMAIN
+
-
/XNC * ILBA * W_R * IMAT1 * IRESET * T3
+
/XNC * ILBA * W_R * IBROY * IRESET * T4 * MAIN
WINV
: = /XNC * ILBA * /W R * IMAT1 * IBHY * IRESET * T2 *
IMAIN
-
BAOS : = IXNC * ILBA * W R * IMAT1 * IBHX * IBHY * IRESET *
T2 * IMAIN
-
IBROY * IRESET * FBE
+
: = /XNC * ILBA * /W R * IBHY * IRESET * T2 * IMAIN
-
/XNC * ILBA * W R * IMAT1 * BROY * IBHX * IRESET *
T2 * MAIN
-
+
/XNC * ILBA * W R * IMAT1 * IBHY * IRESET * T2 *
IMAIN
-
XNC * ILBA * ADS * IBHX * IRESET * IMAIN
+
+
/XNC * ILBA * W R * IMAn * BROY * IBHX * IRESET *
T2 * MAIN.
+
XNC * ILBA * BROY * IBHX * IRESET * MAIN
+
.
XNC * ILBA * IBHX * BHY * IRESET * IMAIN
+
IBROY * IRESET * MAIN
T2
-
/XNC * ILBA * W_R * IBROY * /RESET * T4 * MAIN
+
+
+
+
IXNC * ILBA * W R * IMAT1 * IRESET * T3
+
-
IBHX * ILBA * /W_R * BROY * IRESET * MAIN
MAIN
:= /XNC * ILBA * W R * IRESET * T3
BROY * IRESET * T4
+
FBE
* BROY * IBHX * IRESET *
/XNC * ILBA * /W R * IMAn * IBHY * IRESET *T2 *
IMAIN
-
= RESET
+
* IBHY * IRESET * T2 *
+
T4
EQUATIONS
-
/XNC * ILBA * W R * IMAT1
T2 * MAIN
-
rr4 rr3
rr2
: = /XNC * ILBA * W R * IMAT1
/XNC * ILBA * /W R * ADS * /BHX * IBHY * IRESET *
IMAIN
-
: = ADS * IRESET
+
+
/XNC * ILBA * /W R * BROY * IBHX * IRESET * MAIN
+
-
+
/XNC * ILBA * /W R * BROY * IBHX * BHY * IRESET *
IMAIN
-
/XNC * ILBA * W R * IMAT1 * IBROY * IRESET * T2 *
MAIN
/XNC * ILBA * /W_R * IRESET * T2 * MAIN
S14-119
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE
APPLICATION NOTE AN·30
+
Controller2
N.A.
1.1
Mammad Safal
Integrated Device Technology Inc.
09-01-1988
lADS * IRESET * RDY2
OE2
:= IXNC * ILBA * W_R * ADS * MAT1 * IRESET
RGT
: = XNC * ILBA * ADS * BRDY * IMAIN * IRESET * IBHX *
IRGT
'
+
CHIP CONTROL_PAL2 PAL22V10
XNC
+
;PINS
;1
2
3
4
5
6
7
8
9
10
CLKB /XNC ILBA IW R lADS MAT1 IBRDY BHOLD ILRDY
/RESET
;11 12
13
14
15
16
17
18
19
20
rr2 GND IMAIN BHLDA IDEN IBHY IBHX RGT IOE2 IRDY2
;21
22 23
24
25
IRDY1 SEL WLE VCC GLOBAL
EQUATIONS
LBA
+
ILBA
+
,
, IXNC
RDY1
BHY
+
IXNC
+
* MAIN * IRESET * RDY1
* ILBA * IW R * ADS * IRESET * BHX
* BHY * RDY1
XNC
+
XNC
+
* ILBA * ADS * IRESET * BHX
* ILBA * T2 * IRESET * BHY
: = IXNC * ILBA * IW R * IMAT1 * T2 * IMAIN * IRESET *
/BHX
* IBHY
* BHY * IBHLDA
* T2 * IMAIN * IRESET *
+
/XNC * ILBA * W R • IMAT1 • BRDY· MAIN • IRESET
+
ILBA * IW R • ADS * IMAIN • IRESET • IBHX
+
ILBA * IW_R • BRDY * MAIN • IRESET • IBHX
+
*W
-
R * ADS
* IMAIN
• IRESET * IBHY •
+
XNC * ILBA * W R * BRDY· MAIN * IRESET
+
IBRDY· IRESET * DEN
+
* ILBA * IBRDY * MAIN * IRESET * IBHX
XNC
RDY2
• IRESET
: = /XNC • ILBA * W 'R * IMAT1
IBHY· IDEN
-
XNC * ILBA
IDEN
IRESET
+
* BHOLD
BHOLD • IRESET • BHLDA
DEN
* ILBA * IW_R * T2 * IRESET * BHY * SEL
IBRDY
+
* MAIN • IRESET • IBHX
: = IRESET • BHX
BHLDA : = BRDY
: = /XNC * ILBA * IW R * ADS * IBRDY * MAIN * IRESET
* IBHX
-
+
RGT
* IMAIN • IRESET * IBHX
BHOLD • IRESET • BHX
* ILBA * IW_R * BRDY * MAIN * IRESET
: = /XNC * ILBA * IW R * ADS * IMAIN * IRESET
+
IXNC * ILBA * IW_R * BRDY * MAIN * IRESET
+
IBRDY * IRESET * IBHLDA * SEL
+
* RGT
* IRESET •
: = BHOLD • T2
+
IRESET
BRDY • BHOLD • T2
/XNC
SEL
* IBRDY •
+
:= /XNC * ILBA * IW R * ADS * IMAIN * IRESET
-
* IRGT
* ADS * IRESET * IRGT
LBA • ILRDY
BHX
+
BHY
XNC * ILBA * BRDY • T2 • MAIN * IRESET· IBHX • IRGT
+
GLOBAL.RSTF = RESET
WLE
* ILBA • IRESET * IBHX •
-
S14-120
IW R • ILBA * BRDY • IMAIN • IRESET • IBHX • BHY •
10 EN
+
XNC • ILBA * BRDY * IMAIN • IRESET • IBHX
IDEN
* BHY •
THE COMPLETE HIGH PERFORMANCE CACHE
SYSTEM FOR THE 80386 MICROPROCESSOR
TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE
APPLICATION NOTE AN-30
Controller3
NA
1.0
Mammad Safai
Integrated Device Technology Inc.
09-28-1988
CLR
/RESET
/RESET
+
/RESET
* CLR2
* FLUSH
+
RESET
CHIP CONTROL_PAL3 PAL22V10
CONCLUSION
;PINS
;1
* MAT2 * CLR1
+
2
3
4
5
6
7
8
9
10
ClKB /RESET BHLDA /BW R /BADS MAT2/FLUSH NC NC
NC
;11 12
13
14
15
16
17
18
19
20
NC GND NC
NC
NC
NC
NC
NC
NC
NC
;21
22
23
24
25
/CLR /CLR2 /CLR1 VCC
GLOBAL
EQUATIONS
GlOBAL.RSTF
= RESET
CLR1
.-
/RESET
CLR2
:=
/RESET
* BHLDA * /BW_R * BADS
* MAT2 * CLR 1
The design of cache based microprocessor systems is
optimized by the use of a cache controller based on a dual cache
tag scheme. Such an architecture is adaptable to present day
25MHz systems as well is easily adapted to future higher speed
microprocessors. Posted writes further improves the effective
cycle time (with the IDT74FCT646s).
At the heart ofthis design is the IDT7174 cache tag SRAM. This
device with an address to match time of 20ns gives a wide margin
for the two cycle 80386 operating at 25M Hz. Faster microprocessor
can be easily accommodated without changes to this design.
S14-121
-----------,._-,------------
Package Diagram Outlines
THERMAL PERFORMANCE CALCULATIONS FOR lOT'S PACKAGES
Since most of the electrical energy consumed by microelectronic devices eventually appears as heat, poor thermal performance of the device or lack of management of this thermal energy
can cause a variety of deleterious effects. This device temperature
increase can exhibit Itself as one of the key variables In establishing device performance and long term reliability; on the other
hand, effective dissipation of Intemally generated thermal energy
can, if properly managed, reduce the deleterious effects and Improve component reliability.
A few key benefits of lOT's enhanced CEMOS TM process are:
low power dissipation, high speed, Increased levels of Integration,
wider operating temperature ranges and lower quiescent power
dissipation. Because the reliability of an integrated circuit is largely
dependent on the maximum temperature the device attains during
operation, and as the junction stability declines with increases in
junction temperature (TJ), it becomes increasingly important to
maintain a low (TJ).
CMOS devices stabilize more quickly and at greatly lowertemperature than bipolar devices under normal operation. The accelerated aging of an integrated circuit can be expressed as an exponential function of the junction temperature as:
~ = to exp
[E (-1.. --1..)\l
k
To
TJ
~
where
4.
Tightly controlled the assembly procedures to meet or
exceed the stringent criteria of MIL-STO-883C to ensure
maximum heat transfer between die and packaging
materials.
'
The following figures graphically illustrate the thermal values of
lOT's current package families. Each envelope (shaded area) depicts a typical spread of values due to the Influence of a number of
factors which Include: circuit size, package cavity size and die attach Integrity. The following range of values are to be used as a
comprehensive characterization of the major variables rather than
single point of reference.
When calculating junction temperature (TJ), it is necessary to
know the thermal reSistance of the package (eJA) as measured in
"degrees celsius per watt". With the accompanying data, the following equation can be used to establish thermal performance, enhance device reliability and ultimately provide you, the user, with a
continuing series of high-speed, low-power CMOS solutions to
your system design needs.
eJA = [TJ - TAI/P
TJ = TA+ P [eJAI = TA + p[eJA+ ecAi
where
eJC = lj - Tc
P
Thermal resistance, junction to reference point
Junction
Operational power of device (dissipated)
Ambient temperature in degrees celsius (normally
+70°0)
Junction temperature of integrated device
Temperature of case/package
Case to Ambient, thermal resistance-usually a
measure of the heat diSSipation due to natural
or forced convection, radiation and mounting
techniques.
Junction to Case, thermal resistance-usually
measured with reference to the temperature at a
specific point on the package (case) surface. (Dependent on package material properties and package geometry.)
Junction to Ambient, thermal resistance-usually
measured with respect to the temperature of a specified volume of Still Air. (Dependent on eJC + eJA
which includes the influence of area and environmental condition.)
tA
lifetime at elevated junction (TJ) temperature
to
normal lifetime at normal junction (To) temperature
Ea
activation energy (ev)
k
Boltzmann's constant (8.617 x 10-5 ev/k)
I.e. the lifetime of a device could be decreased by a factor of 2 for
every 10°C increase temperature.
To minimize the deleterious effects associated with this potential increase, lOT has:
1. Optimized our proprietary low-power CEMOS fabrication process to ensure the active junction temperature
rise is minimal.
2. Selected only packaging materials that optimize heat
diSSipation, which encourages a cooler running device.
3. Physically designed all package components to enhance the inherent material properties and to take full
advantage of heat transfer and radiation due to case
geometries.
Ref. MIL-STO-883C, Method 1012.1
JEOEC ENG. Bulletin No. 20, January 1975
1986 SemI. Std., Vol. 4, Test Methods G30-86, G32-86.
S15-1
100
90
~
80
~
- 70
(/)1- I- 60
~ ~ 50
0: ......
~.
...J U 40
~ !.. 30
~"'"
w
ffi
U
~
80
~t=' 70
-
I-
~~
0: ......
10
0:
20
10
W
:c
I-
O~L-~~~~~~~~~~~~~
o L-16L......12L-0--'2L-4...J28L---J32L---J36-4-:.10:---:l44:--:l48~52----'56---L60-64...1-...J..J68
1620242832364044485256 60 64 68
LEAD COUNT
Thermal Resistance of Ceraml~DIP Packages
LEAD COUNT
Thermal Resistance of PLCC/SOIC Packages
100
,100
~
~
~
w
90
80
z
«
t='
70
60
~ ~ 50
...J U 40
~ !.. 30
~
t='
-
I-
~~
0: ......
~~
0:
0:
~
90
80
U
en ~
I-
60
50
...J U 40
~ !.. 30
~
20
~
100
90
w
w
20
10
:c
I-
OL...-",--'--""'--",",--'--'---'---'-~~~--'---''-'-'
e
70
60
50
40
30
20
10
OL--~~~~~~:---:l----,~----,~----,~
1620242832364044 48 5256606468
LEAD COUNT
Thermal Resistance of Plastic DIP Packages
LEAD COUNT
Thermal Resistance of Ceramic Sidebraze Packages
JA
°CNlATT
100
90
80
70
60
56
40
30
20
10
0~~~~~~1~~~14~0~-1~60~~1~80~~~
LEAD COUNT
PPGA Packages
Package Laminate Material: Hi Temp. Epoxy or Triazine (81)
100
w
U
«
1--
90
80
70
~~
60
50
z
(/)1-I-
0: ......
...JU 40
~!.. 30
0:
w
~
I-
10
:c
0
Thermal Resistance of Ceramic Leadless
Chip Carrier (LCC) Packages
S15-2
~
PACKAGE DIAGRAM OUTLINE INDEX
IntegratedDevIce~Inc.
PAGE
PKG.
DESCRIPTION
P16-1
P18-1
P20-1
P22-1
P24-1
P24-2
P28-1
P28-2
P32-1
P40-1
P48-1
P64-1
16-Pin
18-Pin
20-Pin
22-Pin
24-Pin
24-Pin
28-Pin
28-Pin
32-Pin
4Q-Pin
48-Pin
64-Pin
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
D16-1
D18-1
D20-1
D22-1
D24-1
D24-2
D28-1
D28-2
D28-3
D32-1
D40-1
D40-2
16-Pin
18-Pin
20-Pin
22-Pin
24-Pin
24-Pin
28-Pin
28-Pin
28-Pin
32-Pin
4Q-Pin
40-Pin
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP
C20":1
C22-1
C24-1
C24-2
C28-1
C28-2
C28-3
C32-1
C32-2
C40-1
C48-1
C48-2
C64-1
C64-2
C68-1
20-Pin 8idebraze DIP (300 mil)
22-Pin 8idebraze DIP (300 mil)
24-Pin 8idebraze DIP (300 mil)
24-Pin 8idebraze DIP (600 mil)
28-Pin 8idebraze DIP (300 mil)
28-Pin 8idebraze DIP (400 mil)
28-Pin 8idebraze DIP (600 mil)
32-Pin 8idebraze DIP (600 mil)
32-Pin 8idebraze DIP (400 mil)
40-Pin 8idebraze DIP (600 mil)
48-Pin 8idebraze DIP (400 mil)
48-Pin 8idebraze DIP (600 mil)
64-Pin 8idebraze DIP (900 mil)
64-Pin Topbraze DIP (900 mil)
68-Pin 8idebraze DIP (600 mil)
..................................................•......
..........................••..•....•...••........•.......
........................................................ .
..•....................................................•.
........................................................ .
...........................................•..•••........
..........................•.•........•...................
..........•............................•.................
........................................................ .
........................................................ .
........................................................ .
................................. ~ .••.........•..........
...................................................•.....
.....................................•...•...............
...................................•......•..•...•.......
815-10
815-10
815-10
815-12
815-10
815-11
815-12
815-12
815-11
815-12
815-11
815-12
815-13
815-14
815-12
PG68-2
PG84-2
PG208-2
68-Lead Plastic Pin Grid Array (Cavity Up) ......................................••.......
84-Lead Plastic Pin Grid Array (Cavity Up) ........................................•......
208-Lead Plastic Pin Grid Array (Cavity Up) ..................................••..........
815-15
815-15
815-15
G68-1
G68-2
G84-1
G84-2
G108-1
G144-1
G144-2
G208-1
68-Lead Pin Grid Array (Cavity Up) .................................................... .
68-Lead Pin Grid Array (Cavity Down) .................................................. .
84-Lead Pin Grid Array (Cavity Up) .........•.................•...•...•.........••......
84-Lead Pin Grid Array (Cavity Down) .................................................•.
108-Lead Pin Grid Array (Cavity Up) ..................................................•.
144-Lead Pin Grid Array (Cavity Down) ........................••...•..................•.
144-Lead Pin Grid Array (Cavity Up) ................................................... .
208-Lead Pin Grid Array (Cavity Up) ................................................... .
815-16
815-21
815-17
815-22
815-18
815-23
815-19
815-20
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
(300
(300
(300
(300
(300
(600
(600
(300
(600
(600
(600
(900
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
mil)
.......................•••........••..•....•....•...........
............................•......•..•••...•...............
........••.•........•...............................•.......
........ ~ .....•..............••.............................
..............••.....•.......••..••.•.•.....................
.•...........................................•..............
.........................................••.....•...••......
....................••...........•..•••.•••.........••...•..
....................•.........•..•...•.•.•.•........••......
............•..•....•...................................••..
........••.................................•... ; ........••..
........................................................... .
815-6
815-6
815-6
815-6
815-6
815-7
815-7
815-6
815-7
815-7
815-7
815-7
(300 mil) .....•..................................... ; .............••..•
(300 mil) ............................................................. .
(300 mil) ....................................•....................•....
(300 mil) ....................................•...••...•..•...•.........
(300 mil) ....................................•...•.........•.•.........
(600 mil) .........................................•..••........•.......
(600 mil) ...........•••................................. '.' ............ .
(Wide Body) ......................................•............•..••...
(300 mil) ................................•....•...•.•..................
(Wide Body) •..........................................................
(600 mil) ............................................................. .
(Wide Body) .•............•............................................
815-8
815-8
815-8
815-8
815-8
815-9
815-9
815-9
815-8
815-9
815-9
815-9
515-3
iEI
PACKAGE DIAGRAM OUTLINE INDEX
PAGE
PKG.
DESCRIPTION
S016-1
S018-1
S020-1
S020-2
S024-2
S024-3
S024-4
S028-2
S028-3
S028-4
16-Pin Small
18...Pin Small
2Q-Pin Small
2Q-Pin Small
24... Pin Small
24... Pin Small
24... Pin Small
28... Pin Small
28... Pin Small
28... Pin Small
J20-1
J28-1
J32-1
J44-1
J52-1
J68-1
J84-1
2Q-Pin
28... Pin
32... Pin
44...Pin
52-Pin
68-Pin
84-Pin
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
L20-1
L20-2
L22-1
L24-1
L28-1
L28-2
L32-1
L44-1
L48-1
L52 ...,1
L68-1
L68-2
20... Pin
20-Pin
22-Pin
24-Pin
28-Pin
28-Pin
32-Pin
44-Pin
48-Pin
52-Pin
68... Pin
68-Pin
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
Leadless
E16-1
E20-1
E24-1
E28-1
E28-2
16... Lead CERPACK
20-Lead CERPACK
24-Lead CERPACK
28... Lead CERPACK
28-Lead CERPACK
Outline
Outline
Outline
Outline
Outline
Outline
Outline
Outline
Outline
Outline
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Leaded
Leaded
Leaded
Leaded
Leaded
Leaded
Leaded
(Gull Wing) .................................................... .
(Gull Wing) .................................................... .
(J ... Bend) ....................................... , .............. .
(Gull Wing) .................................................... .
(Gull Wing) .................................................... .
(Gull Wing) .................................................... .
(J ... Bend) ...................................................... .
(Gull Wing) ..................................................... .
(Gull Wing) ............................ ~ ....................... .
(J ... Bend) ...................................................... .
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
(Sq.) ................................................ .
(Sq.) ................................................ .
(Rect.) ............................................... .
S15-24
S15-24
S15-25
S15-24
S15-24
S15-24
S15-25
S15-24
S15-24
S15-25
(Sq.) ....................... ; ........................ .
S15-26
S15-26
S15-27
S15-26
S15-26
S15-26
S15-26
(Rect.) ................................................... .
(Sq.) ..................................................... .
(Rect.) ................................................... .
(Rect.) ................................................... .
(Sq.) ..................................................... .
(Rect.) ................................................... .
(Rect.) ......................................, ............. .
(Sq.) ..................................................... .
(Sq.) ..................................................... .
(Sq.) ..................................................... .
(Sq.) ..................................................... .
(Sq.) ..................................................... .
S15-30
S15-28
S15-30
S15-30
S15-28
S15-31
S15-31
S15-28
S15-29
S15-29
S15-29
S15-29
................................................................. .
................................................................. .
................................................................. .
................................................................. .
................................................................. .
S15-32
S15-32
S15-32
S15-32
S25-32
CQ68-1
CQ84-1
68 ... Lead CERQUAD (Straight Leads) ................................................... .
84-Lead CERQUAD (J ... Bend) ......................................................... .
S15-33
S15-34
F20-1
F20-2.
F24-1
F28-1
F28-2
F48-1
F64-1
F172-1
20-Lead Flatpack ................................................................... .
20... Lead Flatpack (.295 Body) ......................................................... .
24-Lead Flatpack ................................. : ................................. .
28... Lead Flatpack ................................................................... .
28... Lead Flatpack ................................................................... .
48-Lead Flatpack ................................................................... .
64-Lead Flatpack ................................................................... .
172-Lead Flatpack .................................................................. .
S15-35
S15-35
S15-35
S15-35
S15-35
S15-36
S15-36
S15-37
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
Carrier
(Sq.) .•.....•.•...•......•••••••.•....•...........•..•
(Sq.) ................................................ .
(Sq.) ........................•.......••.............•.
515-4
PACKAGE DIAGRAM OUTLINE INDEX
MODULE PACKAGING
PKG.
DESCRIPTION
PAGE
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
28-Pln Sidebraze DIP •.•.••........••...........•••..••.•....•.........••. " .....•....
32-Pin Sidebraze DIP ................•......•............•..............•....•..••...•
32-Pin Sidebraze DIP ..••.......••....•..••.......•....••...••........•..........••..•
40-Pin Sidebraze DIP ......••........•........•...•....••..•••...•...•••..••...••••...
40-Pin Sidebraze DIP ..•.........•...••........•........•....••....•..............•••.
40-Pin Sidebraze DIP ...........•..............•........•....•........•••....•......•.
40-Pin Sidebraze DIP ......•.•..•....•..............•...•....•.•....•...•....•.....•..
44-Pin FR-4 DIP •..•....•••...................................•••....•...••... '" .•..
48-Pin Ceramic DIP .•....•....••...•............•••...•.....•..•.....•...........••.•
58-Pin Sidebraze DIP ....................•.............••..•••...•....••........ ; ••.•.
60-Pin Ceramic DIP .......••........•..•..................•........••..•.......••....
64-Pin Sidebraze DIP ..•.............••.............•......•....•........•......•....•
64-Pin Ceramic DIP •..............••.................•••...••.....•...•..........••..
28-Pin FR-4 SIP •..........•......•.............•....•••..•.•...•.•..••.........••.•.
30-Pin FR-4 SIP ...•....•....•.........•.....•...•...........•....•....•...••.....•..
36-Pin FR-4 SIP •....•...•.....•.........••...•....•....•....•••..•.....•.....••....•
40-Pin FR-4 SIP •.........••....•....•.........••...••.....•...•.....•.........•••...
43-Pin FR-4 SIP .•...••....... " ......•....••....•........••.•..••...••...•••.....••.
28-Pin Ceramic SIP ...............••.......•.....••....••......•..•••..•..•••.....••.
30-Pin Ceramic SIP ......•.....•....•...••.....••........•••...•.....•..•.....•••...•
40-Pin Ceramic SIP •....•..........•....•.................... ~ ......•........•.......
36-Pin Ceramic Dual SIP ........................ ; ..................................... .
88-Pin Ceramic Dual SIP .....•.....•....••.......••...•......••....•.•...•...••..••...
40-Pin FR-4 ZIP .....••..........•.........•.•.........•..........•.•.......••....••.
92-Pin FR-4 alP ............•......•...•••....•...•.. ~ .•.....••••....•....••...•...••
1oa-Pin FR-4 alP ••...•......•...........••........•......•••...•••...•.....••....••.
108-Pin FR-4 alP ...................................•..•......••.•...•....•••..•.•...
120-Pin FR-4 alP .•.....•..•.........••....••....••...••....••......•...•............
128-Pin FR-4 alP ....•.........•......•••.•..•••....•••....••..••••....•....••...•.•
164-Pin FR-4 alP .•.••.....•.....••.....•..........•.•...••.•..•••...•.....••...••••
92-Pin Ceramic alP .............•.......•.....•..........••.•..•.....•.•..•.....••••.
128-Pin Ceramic alP ••••...........••....••.•...••.....•.....•....••••..•..........•.
S15-38
S15-38
S15-38
S15-38
S15-38
S15-39
S15-39
S15-39
S15-40
S15-40
S15-40
S15-41
S15-41
S15-41
S15-42
S15-42
S15-42
S15-43
S15-43
S15-44
S15-44
S15-44
S15-45
S15-45
S15-45
S15-46
S15-46
S15-47
S15-47
S15-48
S15-49
S15-49
S15-5
---------
..•. _..
_
__ ._-_
..._.....
...
_._._.
__
_---
..
~
PACKAGE DIAGRAM OUTLINES
Intesrated DevIce~Inc.
PLASTIC DUAL IN-LINE PACKAGES
NOTES.
m
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHER'JISE STATED.
[2] BSC - BASIC PIN SPACING BET'JEEN CENTERS.
[3] D Be E1 DO NOT INCLUDE HOLD FLASH DR PROTRUSIONS.
16-28 PIN PLASTIC DIP (300 MIL)
I,
o~~?NI (N)
A
1l)~O'J
IN
C
0
15
15
5C
.008
D
1-5
A'
b
b'
E
.3
.1
.1-
7
E'
e
e,lt
16
0
.012
6
5
2
1
.J7
3
9
1l}:~o2
ilL)
MAX
IL)
IX
MIN
.140
.C15
015
05C
.008
.!'l85
7
.012
0
01
1
05
45
15
15
5
.008
22
3
7
.1
0
0
.012
MIN
.145
15
15
.050
.008
04(;
6
.Q
51
0
.1
6
025
055
9
.J
.1
2lfsO'ciMAX
MIL)
MIL)
~A
320
,280
11
05C
MIL)
6
.008
)2
6
.012
1
0
1
5
.(]
.(]
9
.O~
.0'
7C
:3C
.0
~.
0
MA
.008
,5
4
~f~tIL)
2
I
4
1
0
40
O·
815-6
165
35
02C
065
.012
061
l~t0i1
I
0
3"
0(
S
2Crt:~oJ
~IN
.0
02C
06fi
.012
PACKAGE DIAGRAM OUTLINES
PLASTIC DUAL IN-LINE PACKAGES (Continued)
24-48 PIN PLASTIC DIP (600 MIL)
1#
DWG ~
OF PIN (N)
A
A1
b
b1
C
D
E
E1
e
eA
L
0(
S
01
P24-2
24 (600 MIL)
MIN
MAX
.160
.185
.035
.015
.020
.015
.050
.065
.012
.008
1.240
1.260
.600
.620
.550
.530
.090
.110
.670
.610
.150
.120
o·
15'
.060
.080
.060
.080
P28-1
28 (600 MIL)
MIN
MAX
.160
.185
.015
.035
.015
.020
.050
.065
.008
.012
1.420
1.460
.600
.620
.530
.550
.090
.110
.610
.670
.120
.150
O'
15'
.055
.080
.060
.080
P32-1
32 . (600 MIL)
MIN
MAX
.170
.190
.015
.050
.016
.020
.045
.055
.008
.012
1.645
1.655
.600
.625
.530
.550
.090
.110
.610
.670
.125
.135
0'
15'
.065
.075
.070
.080
64 PIN PLASTIC DIP (900 MIL)
DWG #
/I OF PINS (N)
A
A1
b
b1
C
D
E
E1
e
eA
L
0(
S
01
P64-1
64 (900 MIL)
MIN
MAX
.180
.230
.015
.040
.015
.020
.050
.065
.008
.012
3.200
3.220
.900
.925
.790
.810
.090
.110
.910
1.000
.120
.150
0'
15'
.045
.065
.080
.090
S15-7
P40-1
40 '(600 MIL)
MAX
MIN
.160
.185
.015
.035
.015
.020
.050
.065
.008
.012
2.050
2.070
.600
.620
.530
.550
.110
.090
.610
.670
.120
.150
0'
15'
.070
.085
.080
.060
P48-1
48(600 MIL)
MIN
MAX
.170
.200
.015
.035
.015
.020
.050
.065
.008
.012
2.420
2.450
.600
.620
.530
.560
.090
.110
.610
.670
.120
.150
O·
15'
.060
.075
.060
.080
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES
A
L1
SEATING PLANE
NOTES.
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
[2] BSC - BASIC PIN SPACING BET'w'EEN CENTERS.
[3] THE MINIMUM LIMIT FOR DIMENSION bl MAY BE .023 FOR CORNER LEADS.
[1]
16-28 PIN CERDIP (300 MIL)
OWG 1f,
016-1
018-1
020-1
022-1
024-1
028-3
II OF LEA S (N) 16 (300 MIL' 18 (300 MIL) 20 (300 MIL) 22 (300 MIL) 24 -(300 MIL) 28 (300 MIL)
A
b
b1
e
0
E
E1
e
L
L1
a
S
S1
ANGLE lDEG)
MIN
.090
.016
.045
.009
.750
.240
.290
.100
.125
.150
.015
.020
.005
o·
MAX
.200
.020
.065
.013
.B30
.310
.320
sse
.175
.060
.080
15'
MIN
.090
.014
.038
.009
.BBO
.220
.290
.100
.125
.150
.015
.020
.005
o·
MAX
.200
.023
.065
.014
.940
.310
.320
sse
.175
.060
.080
15'
MIN
.140
.014
.038
.009
.935
.220
.290
.100
.125
.150
.015
.020
.005
o·
MAX
.200
.023
.065
.014
1.060
.310
.320
sse
.175
.060
.080
15'
815-8
MIN
.140
.014
.038
.009
1.050
.220
.290
.100
.125
.150
.015
.020
.005
O'
MAX
.200
.023
.065
.014
1.1BO
.310
.320
sse
.175
.060
.080
15'
MIN
.140
.014
.038
.009
1.240
.220
.290
.100
.125
.150
.015
.030
.005
o·
MAX
.200
.023
.065
.014
1.2BO
.310
.320
sse
.175
.060
.080
15'
MIN
MAX
.140
.200
.014
.023
.038
.065
.009
.014
1.440 1.490
.220
.310
.290
.320
.100 sse
.125
.175
.150
.015
.060
.030
.080
.005
o·
15'
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24-40 PIN CERDIP (600 MIL)
DWG
/I
JI OF LEADS (N)
A
b
bl
C
D
E
El
e
L
L1
a
S
Sl
0<
D24-2
24 (600 MIL)
MIN
MAX
.200
.090
.023
.014
.038
.065
.OOB
.015
1.290
1.230
.500
.560
.590
.620
.100 esc
.125
.200
.150
.015
.060
.030
.080
.005
O·
15·
D2B-l
28 (600 MIL)
MIN
MAX
.200
.090
.015
.020
.060
.045
.OOB
.013
1.440
1.490
.510
.545
.590
.620
.100 esc
.200
.125
.150
.020
.060
.030
.080
.005
O·
15·
D40-1
40 (600 MIL)
MIN
MAX
.160
.220
.015
.020
.045
.060
.OOB
.012
2.070
2.020
.510
.545
.590
.620
.100 BSC
.125
.200
.150
.020
.060
.030
.080
.005
O·
15·
28-40 PIN CERDIP (WIDE BODy)
DWG II
JI OF LEADS lNl
A
b
bl
C
D
E
El
e
L
L1
a
S
Sl
0<
D28-2
28 (WIDE BOD'l'l
MAX
MIN
.090
.200
.015
.020
.045
.060
.008
.013
1.490
1.440
.570
.600
.590
.620
.100 BSC
.125
.200
.150
.020
.060
.030
.080
.005
O·
15·
D32-1
32 LWiDE BODY)
MIN
MAX
120
.210
.015
.020
.038
.065
.015
.008
1.625
1.675
.570
.600
590
.620
.100 BSC
.200
.125
.150
.020
.060
.030
.080
.005
O·
15·
D4O-2
40 (WIDE BOD--'!'l
MIN
MAX
160
.220
.015
.020
.045
.060
.008
.012
2.020
2.070
.570
.600
.620
.590
.100 BSC
.125
.200
.150
.020
.060
.030
.080
.005
O·
15·
lEI
I
515-9
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
20-26 PIN SIDEBRAZE (300 MIL)
j
t-~~
SEATING
PLANE
S2
~Ll
-,
b~1-
I~I~
-leI- -II-Sl '
NOTES:
[1] ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE STATED•.
[2] BSC - BASIC PIN SPACING BETWEEN CENTERS.
D'JG I/:
# OF LEADS (N)
A
10
101
C
D
E
El
e
L
L1
Q
S
Sl
S2
C20-1
20 (300 MIl)
MAX
MIN
100
.200
014
Q23
.038
.060
.008
liS
.970
1.060
.220
.310
.290
.320
.100 BSC
.125
.200
.150
015
060
065
.030
005
.005
C22-1
22 (301 MIL>
MIN
MAX·
.100
.200
02a
.014
.030
.060
008
015
1.040
1.120
.260
.310
.290
.320
.100 BSC
.125
.200
.150
015
060
030
.065
.005
.005
S15-10
C24-1
24 (3)0 MIL>
MIN
MAX
.200
0
-,014
.023
038
.060
.008
.015
1.180
1.230
.220
.310
.290
.320
.100 BSC
125
.200
.150
015
060
.030
.065
.005
.005
~~~Ol
28
MID
MIN
MAX
lOa
.20
.014
023
.030
.060
.008
015
1.380
1.420
.220
.310
.290
.320
.100 BSC
.125
.200
.150
015
.060
.030
065
.005
.005
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
28-48 PIN SIDEBRAZE (400 MIL)
I
I
D
48 PIN OPTION
jJu=:r
SEATING
~JNE
tU-
~
Io-ll- -leI-
I-Sl
T
~C
l-El-J
NOTES:
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE STATED.
[2] BSC - BASIC PIN SPACING BETWEEN CENTERS.
[1]
D'WG #
# OF LEADS (N)
A
10
101
C
D
E
El
e
L
L1
Q
S
Sl
S2
C28-2
28 (400 MID
MIN
MAX
.090
.200
.014
.023
.030
.060
.014
.008
1.380
1.420
.380
.420
.390
.420
.•100 BSC
.100
.175
.150
.030
.060
.030
.065
.005
.005
C32-2
32 (400 MID
MIN
MAX
.090
.200
.014
.023
.030
.060
.008
.014
1.580
1.640
.380
.410
.390
.420
.100 BSC
.100
.175
.150
.030
.060
.030
.065
.005
.005
515-11
C48-1
48 (400 MID
MIN
MAX
.085
.190
.014
.023
.030
.060
.008
.014
1.690
1.730
.380
.410
.390
.420
.070 BSC
.125
.175
.150
.030
.060
.030
.065
.005
.005
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
24-68 PIN SIDEBRAZE (600 lrlIL)
m
I
ID
.j
68 PIN OPTION
SEATING
~~JNE
~Ir:r==!.
fLl
f"
r~
b-ll- -leI- -ll-Sl T
rr~
1
2
.
ALL DIMENSIONS ARE IN INCHESI.'yNLESS OTHERWISE STArrD.
BSC - BASIC PIN SPACING' BETvvt.EN CENTERS.
C48-2 .
C40-1
C68-1
C24-2
C28-3
C32-1
DW'G #
I OF" LEADS (N) 24 (600 MIL> 28 (600 MIl) 32 (600 MIl) 40 (600 MIl) 48 (600 MIl) 6B (600 MIl)
MIN
MAX
MIN
MAX
A
0[
10
10:
C
.015
041
.008
IBU
191
.022
06U
.012
.231
E
El
.51~
361<1
.590
.620
.100
.015
041
.OOB
,3BU
.SSC
.590
190
.022
.060
.012
.42(
.6\0
.620
_e
l
_Ll
Q
S
SI
S2
.100 BS(
.125
.151l
030
.030
005
.010
.175
.100
.125
:as(
.175
~15Q
.060
.065
.030
.030
005
.010
.060
.065
MIN
MAX
191
10C
.015
.022
06(
04U
.OOB
.012
.. SBU
1.640
.SSC
.6\0
.590
.620
00 IS[
.125
.175
ISO
.030
.060
.030
.065
.005
.010
MIN
MAX
MIN
MAX
IOU
19U
.100
.190
.015
.022
.015
.022
04U
06e
04U
06U
.008
.012
.OOB
.012
1.9BO
2.030 2.370 2.430
.611
.SSC
.SSC
.6lC
.620
.590
.620
.590
00 IS[
.10U BSI
.125
.175
.125
.175
15(
15C
.030
.060
.030
.060
.030
.065
.030
.065
.005
.005
010
.005
S15-12
MIN
MAX
DC
.015
04U
.OOB
2.3BC
.5BU
.590
7U
.125
151
.030
.030
.005
.005
19U
.022·
06U
.012
2.440
.61
.620
~S(
.175
060
.065
--_.
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
64 PIN SIDEBRAZE (900 MIL)
NOTES
[1] All. DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE STAlED.
[2] BSC - BASIC PIN SPACING BElWEEN CENlERS.
# OF
D~E~D~
(N)
64 f;ct-1MIL>
MIN
MAX
A
lU
b
bl
,014
,030
D
E
3,160
,023
,060
.015
3,230
,884
.915
E1
,890
e
190
.OOB
,920
,100 BSC
L
125
L1
J7~
,150
,030
,030
,060
,065
Q
S
S'
S2
OS
05
S15-13
__. _ - - - - - -
PACKAGE DIAGRAM OUTLINES
DUAL IN-LINE PACKAGES (Continued)
64 PIN TOPBRAZE (900 MIL)
NOTESr
ALL DIMENSIONS ARE IN INCHES, UNLESS DTHER'w'ISE STATED.
[2] BSC - BASIC PIN SPACING BET'w'EEN CENTERS.
m
'*
D'w'G
It OF' LEADS (N)
A
b
bl
D
E
E1
e
L
L1
Q
S
SI
S2
C64-2
64 (900 MIL>
MIN
MAX
.120
.180
.•
021
.015
.040
.060
-,009
.012
3.165
3.235
.785
.815
.885
.915
.100 BSC
.125
.175
.150
030
.060
.030
.065
.005
.005
S15-14
PACKAGE DIAGRAM OUTLINES
PLASTIC PIN GRID ARRAY
-11
68-208 PIN PGA (CAVITY UP)
1-----------11
L
I
I
I
I
I
I
I
I
I
I
A
+++++++++
+++++++++++
...
gogEl E
!!
++
!!lJ
++
+++++++++t
+++++++++ f-
A
NOlES:
1. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
2. SYMBOL "Nil REPRESENTS THE NUMBER OF PINS.
3. DIM "A" INCLUDES BOTH THE PKG BODY &: lHE UD. IT DOES NOT
INCLUDE HEATSINK OR OlHERATTACHED FEATURES.
4. PIN DIAMETER "C" EXCLUDES SOLDER DIP OR OlHER LEAD FINISH.
5. PIN TIPS MAY HAVE RADIUS OR CHAMFER •.
DWG No.
II OF PINS (N)
SYMBOLS
A
C
D
D1
E
E1
e
L
M
Q
PG 68-2
68 PIN
MAX
MIN
.115
.160
.016
.020
1.140
1.180
1.000 BSC
1.140
1.180
1.000 BSC
.100 BSC
.100
.160
11
.040
.070
PG 84-2
84 PIN
MAX
MIN
.115
.160
.016
.020
1.140
1.180
1.000 esc
1.140
1.180
1.000 BSC
.100 BSC
.100
.160
11
.040
.070
515-15
PG 208-2
208 PIN
MAX
MIN
.115
.160
.016
.020
1.740 1.780
1.600 esc
1.740 1.780
1.600 esc
.100 BSC
.100
.160
17
.040
.070
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS
68 PIN PGA (CAVITY up)
sonOM VIEW
TOP VIEW
1--------
NOTES:
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE SPECIFIED.
2
BSC - BASIC PIN SPACING BETWEEN CENTERS.
3 SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4 SYMBOL "N" REPRESENTS THE NUMBER OF PINS.
11
1
DING #
NO. OF" LEADS
G68-1
68-LEADS
MIN
.010
.016
II
j~
.0_'4
l.l~
J
• IJlJ
lj
.IBO
1.
E1
• UU J:I
e
lj;
h
.U~:
J
L
N
.01
.Li:!1
Q
.040
• B5
• 25
.H
66_
M
.060
11
815-16
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY up)
TOP VIEW
sonOM VIEW
El
E
PIN 1 ID
",.
r ..
SEATING PLANE
-rt_.!--tI
y
I
~ tt ~ m~ ~ ~ ~I-l-
~e~~B~~ ~~~B2
f
NOTES:
11 ALL DIMENSIONS ARE IN INCHES, UNLESS OlHERWlSE SPECIFIED.
2
BSC - BASIC PIN SPACING BETWEEN CENTERS.
3
SYMBOL "M" REPRESENTS lHE PGA MATRIX SIZE.
4
SYMBOL DN" REPRESENTS lHE NUMBER OF PINS.
~
D\JG tf:
NO, OF LEADS
G84-1
84-LEADS
III
\II
\1112
:~
, UU
.Il~1
},It:
El
e
1,230
, UU
.lI~l
, DC .lI:S1
1"1
J
L
R
Q
.1§!L
,1~1
tl4
,060
.040
12
M
I]J
I
S15-17
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
108 PIN PGA ( CAVITY UP)
TOP VIEW
BOTTOM VIEW
C6Bl
PIN 1 ID
~
A
t
NOlES:
1~ ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWI. SE SPECIFIED.
2
8SC - BASIC PIN SPACING BETWEEN CENlERS.
3
SYMBOL "M" REPRESENTS THE PGA MAlRlX SIZE.
4
SYMBOL "N" REPRESENTS TI-fE NUMBER OF PINS.
1
DW'G #
NO. OF LEADS
Gl08-l
l08-LEADS
MIN
.070
III
III
III
.lb
~~
.04
l.1E
• IU H:S
l.lt
E
• ~1c
I
.IUU !:I:S
• UU .tI:S1
e
h
J
.1cL
N
Q
.L4L
lll~
.040
.060
12
H
S15-18
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
144 PIN PGA (CAVITY UP)
11
BonOM VIEW
.B1
1---- -------15
Q
000 0000000000
I 000000000000000
000000000000000
000
000
000
000
000
000
000
I 000 EXTRA PIN COO
I 000
coo
I
I
I
I
I
000
1
000
II 000
I
TOP VIEW
11
E1 E
ceo
ceo
gggoooooooooggg
000000000000000
A 0000000000000
I.
~1==:U
NOTE 5-
SEAllNG -PLANE
NOTES:
11 ALL DIMENSIONS ARE IN INCHES, UNLESS OlHER_ WISE STATED.
2 BSC - BASIC PIN SPACING BETWEEN CENTERS.
3 SYMBOL -M- REPRESENTS lHE PGA MATRIX SIZE.
4
SYMBOL -N- REPRESENTS lHE NUMBER OF PINS.
5 INDEX MARK INDICATES APPROX LOCAllON.
6
EXTRA PIN (D-4) ELECTRICALLY CONNECTED TO 0-3.
NO~~~
lEADS
14't-ili~s
t-
ID
¢ 11
I:.!
ID
9
[
tj
• '!1
..
E
e
(
'I::l~
L
.
.120
(NOTE 6) N
Q
1• ~
B
---
,.0
.040
~u
-
.060
15
M
S15-19
-----------------------------------------
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
208 PIN PGA (CAVITY UP)
BOTTOM VIEW
TOP VIEW
1--------·--L..--,
PINl~
SEATING PLANE
t
f
NOlES:
1j ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
~
2
esc -
3
4
SYMBOL -M- REPRESENTS THE PGA MATRIX SIZE.
SYMBOL -N- REPRESENTS THE NUMBER OF PINS.
BASIC PIN SPACING BElWEEN CENTERS.
DIJG It
NO. OF LEADS
G208-1
208-LEADS
MIN
~
.UI
III
III
III 12
lb
.U4'
.1·
IQ.
• )UL
.Ij;
.I:
J:
.I tiL
• )00 B::l
e
• .UI
h
.8:
.J
.LC!:J
N
Q
M
.M..l!
cUtl
.060
.040
17
815-20
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
68 PIN PGA (CAVITY DOWN)
BOTTOM VIEW
TOP VIEW
IIIBl
INDEX MARK
~
NOTES:
1j ALL DIMENSIONS ARE IN INCHES. UNLESS OlHERWISE SPECIFIED.
2 BSC - BASIC PIN SPACING BETWEEN CENTERS.
:5 SYMBOL -M- REPRESENTS lHE PGA MAlRlX SIZE.
4 SYMBOL -N- REPRESENTS lHE NUMBER OF PINS.
!
D"G #
NO. OF LEADS
G68-2
68-LEADS
1.000
~__~~____~_~t..~09:B~
~--~e~----~~l~20-·1
HS
.14~
68
N
(;11
BSC
~BSC~l2a
025
M
061l
11
I])
I
S15-21
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
84 PIN PGA (CAVITY DOWN)
BOTTOM VIEW
TOP VIEW
I/SBI
INDEX MARK
~
NOTES:
ALL DIMENSIONS ARE IN INCHES. UNLESS OTHERWISE SPECIFIED.
2 BSC - BASIC PIN SPACING BETWEEN CENTERS.
3 SYMBOL -M- REPRESENTS THE PGA MATRIX SIZE.
4 SYMBOL -N- REPRESENTS THE NUMBER OF PINS.
11
1
D'JG #
NO. OF LEADS
G84-2
84-LEADS
III
~
12
i5
)0 BS
.?~5
1
e
l
.lOC
M
.140
14
N
JIll
10 BS
BS
.025
.060
2
815-22
PACKAGE DIAGRAM OUTLINES
PIN GRID ARRAYS (Continued)
144 PIN PGA (CAVITY DOWN)
BOTTOM VIEW
TOP VIEW
~Bl
1--------·........--'5
Q
I
I
I
I
I
I
I
I
I
I
INDEX MARK
A
NOTES:
1! ALL DIMENSIONS ARE IN INCHES, UNLESS OTI-lERWISE SPECIFIED.
2 BSC - BASIC PIN SPACING BETWEEN CENTERS.
3 SYMBOL -M- REPRESENTS TI-lE PGA MAlRlX SIZE.
4 SYMBOL -N- REPRESENTS TI-lE NUMBER OF PINS.
~
DWG #
NO. OF LEADS
.>
G144-1
144-LEADS
[N
~AK
182
GB
ttl
16
III 12
40
.100
022
080
,060
.591
0
DC BS
1.5
.590
DC RS(
e
L
00 BS1
.120
.140
N
(,I:
M
H4
.025
S15-23
1~
~060
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE Ie
16-28 PIN SMALL OUTIJNE (Guu. WING)
PIN
~=t
A1-.--r
-ll-B
SEATING
PLANE' J
NOTES.
m
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHER'WISE STATED.
[2J BSC - BASIC PIN SPACING BET'WEEN CENTERS.
[3J D 8. E DO NOT INCLUDE MOLD FLASH DR PROTRUSIONS.
[4] FORMED LEADS SHALL BE PLANAR 'WITH RESPECT
TO ONE ANOTHER 'WITHIN .004' AT THE SEATING PLANE.
D'WG
I(:
I(:
OF LDS (N
SD16-1
SD18-1
S020-2
S024-2
S024-3
S028-2
S028-3
16 LD
18 LD
20.LD
24 LD
24 LD
28 (.300')
28 (.330')
SYMBOL
MIN
MIN
MAX MIN
MAX
A
A1
.095
.1043 .095
MAX
.1043 .095
.1043
.005
.0118 .005
.0118 .005
B
.014
.020
.020
C
.0091
.0125 .0091
.0125 .0091
D
.403
.413 .447
.462 .497
.014
.014
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
.120
.095
.1043
.110
.120
.0118
.095 .1043 .110
.005 .0118 .005
.0118
.005
.0118
.005
.014
.020
.014
.018
.014
.020
.014
.019
.0125
.0091
.0125
.006
.010
.630
.700
.712
.718
.728
.020
.014
.0125 .0091 .0125 .0091
.511
.600 .614
.620
e
.050 BSC
E
h
.292
.010
H
.400
.419
.400
.419
.400
.419
.400 .419
.406
.419
.400
.419
.462
.478
L
.018
.045
.018
.045
.018
.045
.018
.045
.028
.045
.018
.045
.028
.045
0(
O·
8·
O·
8·
O·
8·
O·
8·
O·
8·
O·
8·
o·
8·
.050 BSC
•050 BSC
.2992 .292 .2992 .292
.020 .010
.020 .010
.050 BSC .
.050 BSC
.2992 .292 .2992 .292
.020 .010 .020 .012
S15-24
.050 BSC
.2992 .292
.020
.010
.050 BSC
.2992 .340
.020 .012
.350
.020
PACKAGE DIAGRAM OUTLINES
SMALL OUTLINE IC (Continued)
20-28 PIN SMALL OUTLINE (J-BEND)
~------Dl------~
I
.
I
t--E2---j
NOTES.
1. D1 8. El DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
2. FORMED LEADS SHALL BE PLANAR VITH RESPECT TO
ONE ANOTHER WITHIN .004' AT THE SEATING PLANE.
3. Dl a. El INCLUDE MOLD MISMATCH a. ARE DETERMINED
AT THE PARTING LINE.
OWG #
/I OF LOS eN)
SYMBOLS
A
A1
B
B1
e
01
E
E1
E2
e
h
S020-1
20 LO .300")
MAX
MIN
.120
.140
.090
.094
.026
.030
.014
.020
.007
.011
.500
.512
.336
.347
.292
.299
.262
.272
.050 Bse
.010 R
S024-4
24 LO .300')
MAX
MIN
.130
.148
.082
.095
.026
.032
.015
.020
.007
.011
.620
.630
.345
.335
.295
.305
.260
.280
.050 Bse
.012 I .020
S15-25
S028-4
28 LO (.350·)
MIN
MAX
~148
.130
.082
.095
.026
.032
.016
.020
.007
.011
.720
.730
.380
.390
.345
.355
.310 .. 330
.050 8se
.012
.020
PACKAGE DIAGRAM OUTLINES
PLASTIC LEADED CHIP CARRIERS
20-84 PIN PLCC
1----- D----I
~---Dl----~
0,045 X 45·
ElE
D2/E2
~JJl
e
NOTES.
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE STATED,
[2] BSC - BASIC PIN SPACING BETWEEN CENTERS,
[3] D 8. E DO NOT INCLUDE MOLD FLASH DR PROTRUSIONS,
[4] FDRMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN ,004' AT
THE SEATING PLAN~
[5) ND 8. NE
** LEADS IN D 8. E DIRECTIONS
[1]
=
nWG #
** OF LDS
SYMBOL
A
Al
B
bl
C
Cl
D
D1
DUE2
D3/E3
E
El
e
ND/NE
J~O-l
J28-1
J44-1
J52-1
J68"1
JB4"1
20
28
44
68
52
84
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
,165 ,180 ,165 ,180 ,165 ,180 ,165 ,180 ,165 ,180 ,165 ,180
,095 ,115 ,095 ,115 ,095 ,115 ,095 ,115 ,095 ,115 ,095 ,115
,026 ,032 ,026 ,032 ,026 ,032 ,026 ,032 ,026 ,032 ,026 ,032
,013 .021 ,013 .021 ,013 .021 ,013 .021 ,013 .021 ,013 .021
,020 ,040 ,020 ,040 ,020 .040 ,020 ,040 .020 ,040 .020 .040
,008 ,012 ,008 ,012 ,008 ,012 ,008 ,012 ,008 ,012 ,008 ,012
.385 ,395 .485 .495 .685 .695 ,785 ,795 ,985 ,995 1.185 1.195
,350 .356 .450 .456 ,650 ,656 ,750 .756 ,950 ,956 1.150 1,156
,290 .330 .390 .430 ,590 .630 ,690 ,730 ,890 ,930 1.090 1.130
.200 REF ,300 REF .500 REF ,600 REF ,800 REF 1,000 REF
,385 .395 .485 .495 ,685 .695 ,785 ,795 .985 .995 1.18511.195
,350 ,356 .450 .456 ,650 ,656 ,750 .756 ,950 .956 1.1501.156
.050 BSC ,050 BSC ,050 BSC ,050 BSC .050 BSC ,050· BSC
5
7
11
13
17
21
S15-26
PACKAGE DIAGRAM OUTLINES
PLASTIC LEADED CHIP CARRIERS (Continued)
32 PIN PLCC
D
D1
0.045 X 45·
I
E3
(ND
L
z
~
El
E
U
NOTES.
ALL DIMENSIONS ARE IN INCHES, UNLESS OTHER'w'ISE STATED.
[2j BSC - BASIC PIN SPACING BET'w'EEN CENTERS.
[3] D ~ E DO NOT INCLUDE MOLD FLASH DR PROTRUSIONS.
[4] FDRMED LEADS SHALL BE PLANAR 'w'ITH RESPECT TO ONE ANOTHER 'WITHIN .004' AT
THE SEATING PLANE.
.
.
[5] ND ~ NE = # LEADS· IN D ~ E DIRECTIONS RESPECTIVELY.
[1]
D'w'G #
# OF LDS
J32-1
32 LD
SYMBOL
MIN
A
.120
.140
Al
.075
.095
.032
MAX
B
.026
bl
.013
.021
C
.015
.040
Cl
.008
.012
D
.485
.495
D1
.449
.453
D2
.390
.430
D3
.300
REF
E
.585
.595
E1
.549
.553
E2
.490
.530
E3
.400 REF
e
.050 BSC
7 I 9
ND/NE
IE)
i
S15-27
PACKAGE DIAGRAM OUTLINES
LEADLESS CHIP CARRIERS
20-44 PIN Lee (SQUARE)
NOTES.
mALL DIMENSIDNS ARE IN INCHES, UNLESS OTHERIJISE STATED.
[2] BSC - BASIC PIN SPACING BETIJEEN CENTERS.
[3] ND=NE - NUMBER OF LEADS PER SIDE.
OWG
II
L20-2
# DF PINS (N)
L28-1
~O
A1
Bl
MAX
.100
.066
.028
82
.022
.o~,
0
.342
.075
.200
A
01
02
04
05
E
E1
E2
E4
E5
e
h
L
:.t.
N
NO
.358
REF
BSC
.358
I
.250 REF
.358
.342
I
175 REF
.200 BSC
I .358
.250 REF
.050 BSC
.040 REF
.020 REF
.045
I .055
.LJ~')
• ILl
20
5
L4+-1
~8
MIN
.064
.054
.022
H·
MIN
.064
.054
022
.022
MAX
.100
.077
028
.041
.442
.458
.075 REF
300 BSC
I .458
.350 REF
.442
I
.458
175 REF
.300 BSC
I
458
.350
REF
.050 BSC
.040 REF
.020 REF
.045
I .055
.LJ~')
. III
28
J
S15-28
MIN
.064
.054
.022
.022
.64C
.075
.500
MAX
.120
.088
028
.041
.660
REF
BSC
.560
I
.550
REF
.640
I
.660
,015 REF
.500 BSC
I .560
.550
REF
.050 BSC
.040 REF
.020 REF
.045
I .055
,I
.09,)
44
"
PACKAGE DIAGRAM OUTLINES
LEAD LESS CHIP CARRIERS (Continued)
46-66 PIN LCe (SQUARE)
DWG #
I OF LEADS (N)
A
A1
B1
82
0
01
2
04
05
E
E1
E2
E4
E5
II
h
J
L
.
........................................
........................................
PINll
=
=
=
fj
=
=
= 0
= = 0 = fj
0
fI
fii
!\mo~
co
co
co
co
co
co
co
E)jiiiiii'F ~DoiF ~iF
[OJ [OJ [I:J] [OJ
c:P.OO!!!!6
[OJ [OJ [OJ [OJ
~ .J!!!!D!l[b
9iioooDrF 9miioiF 9iioDooiF
[OJ [OJ
C
[OJ [OJ [OJ [OJ
.""gJDDDD[b
ijJlD WI 10
10 V
··........................................
........................................
<=
<=
=
<=
0=0
<=
co
co
<=
<=
co
§
=
co
is
=
:3
~
0=0
S15-48
<=
1.990
2.010
1
1.890
T.92O
~~~ I
~
t
0.016
0.026
- - - -..--...
-.--------------,
PACKAGE DIAGRAM OUTLINES
(M31) 92-PIN CERAMIC QIP
:~~+r
DDDDD
DDDD
DDD D D
1.490
.
1.520
¥.OOTYP
~i.5~r.
.050
.100 TYP
.035
.060
.
.175
.015
.022
00000001
00000 ~:::~~
--:--------------------
I•
2.765
2.835
..
I
(M32) 128-PIN CERAMIC QIP
M -+-
.100TYP11=~
.910
I:O::CJ~:O:]f
I.
3.165
3.235
.
.1
515-49
--t
:~~
..
--~ ..
---.,--
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Integrated Device Technology, Inc.
Printed in U.S.A
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