1989_Intel_Microcomputer_Programmable_Logic_Handbook 1989 Intel Microcomputer Programmable Logic Handbook

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inter
Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology. In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
modules, and systems to give its customers the best possible competitive advantages.

PROGRAMMABLE LOGIC
HANDBOOK

1989

Intel Corporation makes no, warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
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Contact your local sales office to obtain the latest specifications before placing your order.
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Table of Contents
Alphanumeric Index .... ,. . . . . . . . . . • . • . • . . . • . . . . . • . . . . . • . . . . . . . . . . . . . . . . . • . •

ix

CHAPTER 1
Overview
Overview. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . . • . .

1-1

CHAPTER 2
,
EPLDs-Erasable Programmable Logic Devices
DATA SHEETS
SC031 , 300-Gate CHMOS H-Series Erasable Programmable Logic Device
(H-EPLD) ...........................•...................•..............
SC032, 300-Gate CHMOS H-Series Erasable Programmable Logic Device
(H-EPLD) ....'..........................................................
SC060, 600-Gate CHMOS H-Series Erasable Programmable Logic Device
(H-EPLD) ..............................................................
SC090, 900-Gate CHMOS H-Series Erasable Programmable Logic Device
(H-EPLD) ...................•.•.........•................•.•...........
SC121, 1200-Gate CHMOS H-Series Erasable Programmable Logic Device ......
SC180, 1800-Gate CHMOS Erasable Programmable Logic Device. • . . . . . . • . . . . . .
APPLICATION BRIEFS
AB-8 Implementing Cascaded Logic in the SC121 ...........•.....•...........
AB-9 SC121 As Ii Three and One-Half Digit Display Driver .....•................
AB-l0 Square Pegs in Round Holes-A Fitting Tutorial for the SC121 ............
AB-ll 16-Bit Binary Counter Implementation Using the SC060 EPLD . . • . . . . . . . . ..
AB-12 Designing a Mailbox Memory for Two SC031 s . . . . . . . . . . . . . . . . . . . . . . . . . ..
AB-16 Atypical Latch/Register Construction in EPLDs .....................•...
AB-22 SC032-2S vs. 16V8-2S: A Device Comparison. . . . . . . . . . . . . . . • . . . . . . . . . ..
APPLICATION NOTES
AP-271 Applying the SC121 Architecture. . .. .. .. . .. . .. . . . . ... . .. .•. ... . .. .. ..
AP-272 The SC060 Unification of a CHMOS System ............•..............
AP-276 Implementing a CMOS Bus Arbiter/Controller in the SC060 EPLD •.......
AP-307 EPLDs, PLAs, and TTL-Comparing the "Hidden Costs" in Production....
AP-321 Fitting the SC180 . • . • . . . . . • . . . . . . . • . . . . . . . . . . . . . . . • . . • • . • . . . . . • . . . ..
ENGINEERING REPORTS
ER-22 SC180 vs. EP1800: A Comparison of Device Specifications. . . . . . . . . . . . . ..
TECHNICAL PAPERS
Techniques for Modular EPLD Designs ..........' .........•............. '. . . . ..
ARTICLE REPRINTS
AR-4S0 Crosspoint Switch: A PLD Approach. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-4S1 A Programmable Logic Mailbox for 80C31 Microcontrollers . . . . • . . . . . . . ..
AR-454 Regain Lost I/O Ports with Erasable PLDs .....•......•...............

2-1
2-13
2-26
2-42
2-S9
2-74
2-106
2-111
2-116
2-128
2-138
2-1S2
2-1S9
2-16S
2-177
2-188
2-198
2-220
2-233
2-241
2-2S1
2-2SS
2-2S8

CHAPTER 3
Advanced Architecture EPLDs
DATA SHEETS
SAC312, l-Micron CHMOS Erasable Programmable Logic Device...............
SAC324,l-Micron CHMOS EPLD ...•...••..........•...•.........•.........
8SCS08, Fast l-Micron CHMOS EPLD .... . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
SCBIC, Programmable BUS Interface Controller. . . . • . . . . . . . . . . . . . . . . . . . . . • . . . •
APPLICATION NOTES
AP-317 Implementing a PS/2 POS Using the SAC312 EPLD ...•..........•.....
AP-319 Designing with the SAC312/SAC324 EPLDs ............•..............
TECHNICAL PAPERS
Programmable and/ Allocatable Based EPLD Addresses the Needs of Complex
Combinational and Sequential Designs. . . . • . . . . • . . • . . . . . . • . . . . . . . . . . . . . . . . .
Advanced Architecture PLDs Solve Common State Machine Problems. . . . . • . . . . .
vii

3-1
3-19
3-38
3-4S
3-62
3-74
3-83
3-91

Table of Contents (Continued)
CHAPTER 4

Development Support Tools
DATA SHEETS
iPLDS II, The Intel Programmable Logic Development System Version II . . . . . . . . . .
iUP-PC, Intel Universal Programmer for the Personal Computer .................
iUP-200AliUP-201 A Universal PROM Programmers . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRODUCT BRIEFS
SCHEMA II-PLD ................................................. .'........
iPLSIl Macro Librarian .....................................................
PLDUTIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTILITIES
PAL2ADF Utility...........................................................
JED2HEX Conversion Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATION BRIEFS
AB-18 TTL Macro Library Listing for EPLD Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-21 EPLD Custom Macro Library Listing for EPLD Designs . . . . . . . . . . . . . . . . . . .
APPLICATION NOTES
AP-311 Using Macros in EPLD Designs ........................... . . . . . . . . . . .
AP-312 Creating Macros for EPLD Designs...................................
TECHNICAL PAPERS
Tools for Optimizing PLD Designs '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1
4-11
4-18
4-25
4-26
4-27
4-29
4-32
4-33
4-37
4-41
4-52
4-62

CHAPTER 5

Appendix
EPLD Third Party Programming Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLA to EPLD Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information ......................................................
Device Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPLD Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compatible Computers for iPLDS II .•. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

5-1
5-2
5-3
5-4
5-5
5-6

Alphanumeric Index'
SAC312, l-Micron CHMOS Erasable Programmable Logic Device......................
3-1
SAC324, l-Micron CHMOS EPLD ................ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
SC031 , 3bO-Gate CHMOS H-Series Erasable Programmable Logic Device (i-t-EPLD) ..... " 2-1
SC032, 300-Gate CHMOS H-Series Erasable Programmab,e Logic Device (H-EPLD) ..... 2-13
SC060, 600-Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD) ..... 2-26
~C090, 900-GateCHMOS H-Series Erasable Programmable Logic Device (H 7EPLD) ... :.
2-42
SC121, 1200-Gate CHMOS H-Series Erasable Programmable Logic Device ..... :....... 2-S9
SC180, 1800-Gate CHMOS Erasable Programmable Logic Device..................... 2-74
SCBIC, Programmable BUS Interface Controller .........•......•..................... 3-4S
8SCS08, Fast l-Micron CHMOS EPLD ............ " ...•...........•....... ~ . . . . . . . . . 3-38
iPLDS II, The Intel Programmable Logic Development System Version II ......... :......
4-1
iUP-200AliUP-201A Universal PROM Programmers.................................. 4-18
iUP-PC, Intel Universal Programmer for the Personal Computer . . . . . . . . • . . . . . . . . . . . . . . . 4-11

'ix

Any of the following products may appear in this publication. If so, it must be noted that
such products have counterparts manufactured by Intel Puerto Rico, Inc., Intel Puerto
Rico II, Inc., and/or Intel Singapore, Ltd. The product codes/part numbers of these
counterpart products are listed below next to the corresponding Intel Corporation product
codes/part numbers.
Intel Corporation
Product Code./
Part Numbers

376SKIT
903
904
913
914
923
924
952
953
954
ADAICE
B386MI
B386M2
B386M4
B386M8
C044KIT
C252KIT
C28
C32
C452KIT
D86ASM
D86C86
D8~EDI

DCM911 I
DOSNET
FI
GUPILOGICIID
H4
1044
1252KIT
I452KIT
I86ASM
ICE386
111010
111086
111086
111111 1II186
1II186
1II198
111212
111286
1II286
111515
I1I520
1II520
1II531
1II532
1II533
1II621
111707
1II707
111815
INA96 I
IPAT86
KAS
KC
KH
KMI

Intel Puerto Rico, Ioc.
Intel Puerto Rico II, Inc.
Product Codes/
Part Numbers
p376SKIT
p903
p904
p913
p914
p923
p924
p952
p953
p954
pADAICE
pB386MI
pB386M2
pB386M4
pB386M8
pC044KIT
pC252KIT
pC28
pC32
pC452KIT
pD86ASM
pD86C86
pD86EDI
pDCM911I
pDOSNET
pFI
pGUPILOGICIID
pH4
plO44
pI252KIT
pI452KIT
pI86ASM
pICE386
plllOIO
plll086
TIII086
pIlI111
pIlI 186
TIII186
plll198
plII212
plII286
TIII286
plll515
TIII520
plII520
plII53 I
plII532
plII533
plII621
plll707
TIII707
pIII815
pINA961
pIPAT86
pKAS
pKC
pKH
pKMI

Intel Siogapore, Ltd.
Product Code./
Part Number.

Intel Corporation
Product Code./
Part Numbers

KM2
KM4
KM8
KNLAN
KT60
KWI40
KW40
KW80
MI
M2
M4
M8
MDS610
MDX3015
MDX3015
MDX3016
MDX3016
MDX457
MDX457
MDX458
MDX458
MSA96
NLAN
PCLINK
PCX344A
R286ASM
R286EDI
R286PLM
R286SSC
R86FOR
RCB44 10
RCX920
RMX286
RMXNET
S301
S386
SBCOIO
SBCOl2
SBC020
SBC028
SBC040
SBC056
SBCI08
SBCI16
SBCI8603
SBCI86410
SBC18651
SBCI86530
SBC18678
SBCI8848
SBCI8856
SBC208
SBC214
SBC215
SBC220
SBC221
SBC28610
SBC28612
SBC28614

Intel Puerto Rico, Inc.
Intel Puerto R,co II, Inc.
Product Code./
Part Numbers

Intel Singapore, Ltd.
Product Codes /
Part Number.

pKM2
pKM4
pKM8
pKNLAN
pKT60
pKWI40
pKW40
pKW80
pMI
pM2
pM4
pM8
pMDS610
pMDX3015
pMDX3015
pMDX3016
pMDX3016
pMDX457
pMDX457
pMDX458
pMDX458
pMSA96
pNLAN
sPCLINK
pPCX344A
pR286ASM
pR286EDI
pR286PLM
pR286SSC
pR86FOR
sRCB4410
pRCX920
pRMX286
pRMXNET
pS301
pS386
pSBCOIO
pSBCOI2
pSBC020
pSBC028
pSBC040
pSBC056
pSBClO8
pSBCI16
pSBCI8603
pSBC186410
pSBC18651
pSBC186530
pSBCI8678
pSBC18848
pSBCI8856
pSBC208
pSBC214
pSBC215
pSBC220
pSBC221
pSBC28610
pSBC28612
pSBC28614

sSBCOl2

sSBC18603
sSBCI8651

sSBCI8848
sSBCI8856
sSBC208
sSBC220
sSBC28610

Intel Corporation
Product Codes/
Part Numbers

SBC28616
SBC300
SBC301
SBC302
SBC3P4
SBC307
SBC314
SBC322
SBC324
SBC337
SBC341
SBC386
SBC386116
SBC386120
SBC38621
SBC38622
SBC38624
SBC38628
SBC38631
SBC38632
SBC38634
SBC38638
SBC428
SBC464
SBC517
SBC519
SBC534
SBC548
SBC550
SBC550
SBC550
SBC552
SBC556
SBC569
SBC589
SBC604
SBC608
SBC614
SBC618
SBC655
SBC66 II
SBC8010
SBC80204
SBC8024
SBC8030
SBC8605
SBC8612
SBC8614
SBC8630
SBC8635
SBC86C38
SBC8825
SBC8840
SBC8845
SBC905
SBCLNKOO1.

Int~ Puerto Rico, Inc.
Intel Puerto Rico II, Inc.
Product Codes/

Part Numbers

pSBC28616
pSBC300
pSBC301
pSBC302
pSBC304
pSBC307
pSBC314
pSBC322
pSBC324
pSBC337
pSBC341
pSBC386
pSBC386116
pSBC386120
pSBC38621
pSBC38622
pSBC38624
pSBC38628
pSBC38631
pSBC38632
pSBC38634
pSBC38638
pSBC428
pSBC464
pSBC517
pSBC519
pSBC534
pSBC548
TSBC550
pSBC550
pSBC550
pSBC552
pSBC556
pSBC569
pSBC589
pSBC604
pSBC608
pSBC614
pSBC618
pSBC655
pSBC6611
pSBC8010
pSBC80204
pSBC8024
pSBC8030
pSBC8605
pSBC8612
pSBC8614
pSBC8630
pSBC8635
pSBC8825
pSBC8840
pSBC8845
pSBC905
pSBCLNKOOI

Intel Singapore, Ltd.
Product Codes/
Part Numbers

sSBC386

sSBC428
sSBC519
sSBC534

sSBC556

sSBC8024
sSBC8605
sSBC8630
sSBC8635
sSBC86C38
sSBC8825
sSBC8845

Intel Corporation
Product Codes/
Part Nulnbers

SBCMEM310
SBCMEM312
SBCMEM320
SBCMEM340
SBE96
SBX217
SBX218
SBX270
SBX311
SBX328
SBX331
SBX344
SBX350
SBX351
SBX354
SBX488
SBX586
SCHEMAIIPLD
SCOM
SDK51
SDK85
SDK86
SXM217
SXM28612
SXM386
SXM544
SXM552
SXM951
SXM955
SYP120
SYP301
SYP302
SYP31090
SYP311
SYP3847
SYR286
SYR86
SYS120
SYS310
SYS311
T60
TA096
TA252
TA452
W140
W280
W40
W80
XNX286DOC
XNX286DOCB
XNXIBASE
XNXIDB
XNXIDESK
XNXIPLAN
XNXIWORD

Intel Puerto Rico, Inc.
Intel Puerto Rico II, Inc.
Product Codes/
Part Numbers

Intel Singapore, Ltd.
Product Codes/
Part' Numbers

pSBCMEM310
pSBCMEM312
pSBCMEM320
pSBCMEM340
pSBE96
pSBX217
pSBX218
pSBX270
pSBX311
pSBX328
pSBX331
pSBX344
pSBX350
pSBX351
pSBX354
pSBX488
sSBX586
pSCHEMAIIPLD
pSCOM
pSDK51
pSDK85
pSDK86
pSXM217
pSXM28612
pSXM386
pSXM544
pSXM552
pSXM951
pSXM955
pSYP120
pSYP301
pSYP302
pSYP31090
pSYP311
pSYP3847
pSYR286
pSYR86
pSYS120
pSYS310
pSYS311
pT60
pTA096
pTA252
pTA452
pW140
pW280
pW40
pW80
pXNX286DOC
pXNX286DOCB
pXNXIBASE
pXNXIDB
pXNXIDESK
pXNXIPLAN
pXNXIWORD

CG/PCPN/1024BB

Overview

1

•

I

I

OVERVIEW

a. SMALLER SYSTEM SIZES: Customized compo-

INTRODUCTION

nents allow for reducing chip count and saving board
space, resulting in smaller system physical dimensions.

In today's increasingly competitive marketplace, system designers need to squeeze out every little edge they
can get from their designs. This has led to a trend
towards better performance, smaller system sizes, lower
power requirements and greater system reliability with
a strong emphasis on preventing easy duplication of the
system design. This trend provided the impetus to the
system designers to move away from standard SSI and
MSI logic components (54/74 & 4000 series Bipolar
and CMOS families) towards a growing class of IC devices variously called 'ASIC' (application specific IC),
'USIC' (user specific IC) or, as referred to in this document, user defined logic.

b. LOWER SYSTEM COSTS: When custom LSI or
VLSI components are used instead of standard SSI and
MSI logic elements, there is a considerable saving in
component cost per system, assembly and manufacturing cost, printed circuit board area and board costs and
inventory costs.
c. HIGHER PERFORMANCE: Reduced number of
ICs contributes to faster system speeds as well as lower
power consumption.
d. HIGHER RELIABILITY: Since probability of failure is directly related to the number of ICs in -the system, a system composed of customized LSI & VLSI
chips is statistically much more reliable than the identical system made up of SSI/MSI devices.

User defined logic circuits allow system designers, for
the first time, to tailor the actual silicon building blocks
used in their systems to their individual system needs
and requirements. Such customization provides the
needed performance, reliability and compactness as
well as design security. Cost per gate of logic implemented is also greatly reduced when user defined logic
solutions are chosen over standard components.

e. DESIGN SECURITY: Systems designed with standard components can be replicated relatively easily
whereas systems that contain user customized ICs cannot be copied because "reverse engineering" of the customized components is extremely difficult. Thus, use of
customized ICs allows for the protection of proprietary
designs.

User defined logic has therefore emerged as the fastest
growing segment of the semiconductor industry and
has presented its users, the system designers, with a
wide range of implementation alternatives namely, programmable logic, gate arrays, standard cell and full
custom design. The tradeoffs between these alternatives
involves time-to-market, one-time engineering charges,
expected unit volume, ease of use of design tools and
familiarity with the design methodology.

f. INCREASED FLEXIBILITY: Customized components allow for the tailoring of systems to the end user's
specific needs relatively easily. This also allows for upgradability and obsolescence protection.

USER DEFINED ICIMPLEMENTATION ALTERNATIVES

This document discusses the reasons for the trend to
user defined logic devices, briefly describes some of the
user defined logic implementation alternatives and covers details on programmable logic devices, the only alternative that is completely user implementable. Tools
used to design with programmable logic are also discussed here.

Currently, the choices available to the system designer
for customization of ICs (see Figure 1) are as follows:
(1) user programmable ICs-programmable logic devices
(2) mask programmable ICs--gate arrays
(3) standard cell based ICs
(4) full custom I Cs

Details on Intel's programmable logic product line, including device terminology and nomenclature, architectural features and development tool features are also
described in this document.

Alternatives (1) & (2) are usually called 'Semicustom'
because in these methods only a few (less than three) of
the mask layers involved in the manufacture of the IC,
are customized to the users' specifications. The later
two alternatives (3) & (4), involve customization of all
mask layers required to manufacture the ICs to the users' specifications and are therefore called 'Custom'.

WHY USER DEFINED LOGIC?
System designers prefer user customized ICs for the
following reasons:

1-1

OVERVIEW
his logic requirements, determines which of th~e connections he would like to remain open and which he
would like to close, through the programming of the
PW. Programmability of these connections is achieved
using various memory technologies such as fuses,
EPROM cclls, EEPROM cells or Static RAM cells (see
Figure 3).

USER DEF"INED LOGIC

1

I

,I

.. SE..ICUSTO..

I

I

PROGRA....ABLE
LOGIC

CUSTO..

I

GATE
ARRAYS

I

STANDARD
CELL

I

F"ULL
CUSTO..
296032-1

User programmability allows for instant customization,
very similar: to user programmable memories such as
PROMs or EPROMs. The user can purchase a PLD
off-the-shelf, use a development system running on a
personal computer and, in a matter of a few hours, have
customized silicon in his hands. Figure 4 compares
user-defmed logic alternatives.

Figure 1. User Defined Logic
Implementation Choices.

PROGRAMMABLE .LOGIC
Most user Programmable Logic Devices (PLD) are internally structured as variations of the PLA (programmable logic array) architecture, that is composed of an
array of 'AND' gates connected to an array of 'OR'
gates (see Figure 2). Programmable logic devices make
use of the fact that any logic equation can be converted
to an equivalent 'Sum-of-Products' form and can thus
be implemented in the 'AND' and 'OR' architecture.
This basic PLA structure has been augmented in most
PLDs with input and output blocks containing registers, latches and feedback options; that let the user implement sequential logic functions in addition to combinational logic.

memory cell
used a. logic control element

The number and locations of the programmable connections between the 'AND' and 'OR' matrices as well
as the input and output blocks are predetermined by
the architecture of the PLD. The user, depending on

296032-3

Figure 3. Programmable Connections

F"EEDBACK (pl'Qllrammable)

~~
INPUT
PIN [

I

.J\.

.J\.

-v

-v

.J\.

PROGRA....ABLE
'AND' Be 'OR' ARRAY

INPUT BLOCK
(contain. latche. and other
programmable Input options)

-v

F=;.

OUTPUT
PIN

OUTPUT BLOCK
(containing output
controls, registers. etc.)
296032-2

Figure 2. General Architecture of a PLD

1-2

OVERVIEW

tional testing elements incorporated in the chips, which
can be blown to examine electrical characteristics.
However, such testing methods never allow for 100%
testability of all parts shipped. Thus, most users of bipolar programmable logic devices resort to extensive
post-programming testing, specific to their applications.

USER DEFINED LOGIC

,I

I

I

SEMICUSTOM

I

1

PROGRAMMABLE
LOGIC

CUSTOM

I

GATE
ARRAYS

I

I

I

STANDARD
CELL

FULL
CUSTOM

ERASABLE PROGRAMMABLE LOGIC
DEVICES

DESIGN COMPLEXITY
DESIGN TIME &: COST
LOWEST SYSTEM COST

4

Erasable programmable logic devices (EPLD) result
from the matching of CHMOS EPROM technology
with the architectures of programmable logic devices.
EPLDs use EPROM cells as logic control elements and
therefore, when housed in windowed ceramic packages,
can be erased with UV light and reprogrammed. Figure
5 shows the architecture of Intel EPLDs.

FASTEST TIME TO MARKET
EASIEST DESIGN CHANGE IMPLEMENTATION

296032-5

Figure 4. User Defined Logic
Alternatives Compared

Other than the obvious benefit of reprogrammability,
EPLDs offer several very significant benefits over bipolar PLDs. These are:

LIMITATIONS OF BIPOLAR FUSE
TECHNOLOGY FOR PROGRAMMABLE
LOGIC DEVICES

1. LOW POWER CONSUMPTION: Due to the
CMOS technology, these products consume an order of
magnitude less power than the equivalent bipolar devices. This allows for the design of complete CMOS systems, that can operate at lower voltages (less than 5V).
Also, this makes for cooler systems that do not require
cooling systems like fans.

I

Until 1985, all PLDs were built using Bipolar fuse technology. The bipolar fuse based devices, although offering the users the benefits of quick time to market and
low development costs, had several inherent limitations.

2. GREATER LOGIC DENSITY: EPROM cells are
an order of magnitUde smaller than the smallest fuses.
This means that the same function can be accommodated in significantly smaller die area, or that greater
amounts of logic can now be incorporated on a single
chip. Thus higher integration programmable logic devices result with the use of EPROM elements.

a. HIGH POWER CONSUMPTION: Bipolar processes by nature are power hungry and as a consequence also make for very hot systems, often requiring
cooling aids such as heat sinks and fans. They also cannot operate at lower voltages (2-3V) and have a lower
level of noise immunity than MOS devices.
b. WWER INTEGRATION: A fuse takes up a large
amount of silicon area; this fact in conjunction with the
large power requirements makes for smaller levels of
integration.

3. TESTABILITY: Since the EPROM cells are erasable, the entire EPROM array of the EPLD can be
100% factory tested. Thus, before the part is shipped to
the customers, it can be completely tested by the programming and erasure of all the EPROM logic control
bits. This testing is therefore independent of any application, in contrast to the bipolar PLDs that need application specific testing.

c. ONE-TIME PROGRAMMABILITY: Bipolar fuses
can only be blown once and cannot be reprogrammed.
This does not allow for easy prototyping and could result in significant losses when preprogrammed parts are
inventoried and design changes occur.

4. ARCHITECTURAL ENHANCEMENTS: The inherent testability of the EPROM elements allows for

d. TESTABILITY: Since fuses can only be blown once,
bipolar PLDs can only be destructively tested. Thus,
testing is usually done by sampling or through addi-

1-3

OVERVIEW

5. DESIGN SECURITY: EPLDs are provided with a
'security bit,' which when programmed does not allow
anyone to read the programmed pattern. The logic programmed in an EPLD cannot be seen even if the die is
examined ,(unlike bipolar PtDs-a blown fuse is clearly
visible) as the stored charges are captured on a buried
layer of polysilicon.

significant architectural improvements over bipolar
PLDs. New features, such as buried registers, programmable registers, programmable clock control, etc;, can
now be incorporated because of this testability. These
new features allow for greatly· increased utilization of
the EPLDs and use of these devices in newer applications.
.'

FEEDBACK (programmable)

~~
INPUT
PIN

~

I
.1..

.J\.
-y"

-V

PROGRAMMABLE
'AND' ARRAY

FIXED
'OR'
ARRAY

.J\.

---,I

~

OUTPUT
PIN

OUTPUT BLOCK
(containing output
controls, registers. etc.)

INPUT BLOCK
(contains latches and other
programmable Input options)

296032-4

Figure 5. Architecture of Intei EPLDs
'DEVELOPMENT
SOFTWARE

USER

Data
Entry

User
Specific
Resource or

Device Request

Device
Utilization
Report

...
...

,
.,
,

~

CONVERSION TO
BOOLEAN
EQUATIONS

~

LOGIC
MINIMIZATION TO
SUM-Or-PRODUCTS
FORMAT

RESOURCE
MATCHING OPTIMAL
RESOURCE
ALLOCATION

PROGRAMMING
PATTERN
GENERATION

PROGRAMMING
HARDWARE

[l]

[II

,

lID

[Z)
JEDEC
Data
Flle

to..
r

296032-6

Figure 6. The PLD Design Process

1-4

OVERVIEW

The steps in a generalized design process of programmable logic is shown in Figure 6 and described in the
following paragraphs.

"JEDEC" format interface and allows the output of the
design software to be compatible with any piece of
PROM programming hardware.

STEP 1: The user decides on the logic he wants implemented in the PLD and enters the design into the PC or
workstation. This Design Entry may be done by the
following methods: (i)SCHEMATIC CAPTURE-A
'Mouse' or some other graphics input device is used to
input schematics of the logic, (ii)NET LIST ENTRYIf the user has a hand drawn schematic he can enter the
design into the computer by describing the symbols and
interconnections in words using a standardized format
called a net list (without using a graphics input device),
(iii)STATE EQUATION/DIAGRAM ENTRY-Entry of a sequential design involving states and transitions between states. In the state diagram method circles represent states and the arrows interconnecting
them represent the transitions. Equations or a state table can also be used to define a state machine, and
(iv)BOOLEAN EQUATIONS-this is the most common design entry method. The logic is described in
boolean algebraic equations.

STEP 8: PROM programmer is used to program the
pattern stored in the JEDEC file onto the PLD. Also,
at this stage fuse programmed PLDs (bipolar) are functionally tested using test vectors included in the JEDEC file information.

CHMOS TECHNOLOGY IN EPLDs
EPLDs are manufactured with Intel's proprietary
CHMOS (Complementary High Performance MOS)
technology. The backbone of the process is the integration of both a P and an N channel MOS transistor on
the same substrate. In addition, EPLD's programmable
architecture makes use of Intel's proven EPROM cell
for programmable array interconnections as well as
macrocell configuration bits. These cells are programmed electrically and erased with ultraviolet light.
For details on Intel's CHMOS technology and
EPROM cells technology, refer to the Components
Quality/Reliability Handbook, Order Number 210997.

STEP 2: The software converts all design entry data
into boolean equations.

CHMOS DESIGN GUIDELINES

STEP 3: The boolean equations entered are converted
to the sum of products format after logic reduction
(minimization of the logic through heuristic algorithms).

Designing with Intel EPLDs is relatively straightforward if the following guidelines are observed:
• Minimize the occurrence of ESD (electro-static discharge) when storing or handling EPLDs.
• Observe good design rules in printed circuit board
layout.
• Provide adequate decoupling capacitance at both
the device and the board level.

STEP 4: The user has the ability to choose the PLD he
would like the design implemented on. He can enter
device choice and/or he can also enter in specific
choices on the device as regards pinout he would like
etc ...
STEP 5: The software optimizes the logic equations to
fit into the device using the minimum amount of resources (resources are input pins, output pins, registers
and product terms and macrocells). This step is where
the user requirements as regards required pins are taken into account. The user requests are viewed as constraints during the optimization process.

• Connect all unused inputs to Vee or GND
(CHMOS inputs should not be left floating).

Electrostatic Discharge
The two most common sources of electrostatic discharge are the human body and a charged environment.

STEP 6: The software, at the end of the resource optimization/allocation, produces a report detailing the resources used up in fitting the design on the PLD. This
report allows the user to incrementally stuff in logic by
going back to Step I from this stage. Also, if the design
overflowed the PLD, i.e., did not fit in the user chosen
device, the software lists out the resources needed to
complete the fit. The requirements such as four more
inputs, one register more and one more output (are
needed to complete the design) gives the user data in
choosing a bigger PLD or in partitioning the intial design to fit into two devices.

A charged human body that touches a device lead
discharges electricity into the device. Electrostatic discharge from people handling devices has long been recognized by manufacturers and users of all MOS products. Human body static electricity can be controlled by
using ground straps and anti-static spray on carpeted
floors. CHMOS devices should also be stored and carried in conductive tubes or anti-static foam to minimize
exposure to ESD from people.
Discharge also occurs when an integrated circuit is
charged to one potential and then contacts a conductor
at another potential. This type of ESD can be reduced

STEP 7: The next step is to generate the appropriate
programming pattern for the PLD. This is a standard
1-5

intJ

OVERVI~W

by grounding all work surfaces, grounding all handling
equipment, removing static generators such as paper
from the work area, and erasing EPLDs in metal tubes,
metal trays, or conductive foam.

Tabular methods like Karnaugh maps are efficient up
to a certain point. Past that point, however, computerassisted minimization plays a crucial part in efficient
design. Even at the computer-assisted stage, the choice
of minimizer software has an impact on time and the
confidence level of the reduced equation (i.e., is it in the
smallest possible form).

PCB Layout
The best PCB performance is obtained when close attention is payed to Vee, GND, and signal traces. Vee
and GND should be gridded to minimize inductive
reactance and to approximate a trace layer. Clocks
should be layed out to minimize crosstalk. Ensure adequate power supply and ground pins on the board connector.

iPLS II software includes a minimizer that uses the
ESPRESSO algorithms. ESPRESSO was developed by
U.C. Berkeley during the summers of 1981 and 1982 in
an effort to study the various strategies used by the
MINI logic minimizer developed by IBM , [HaN 74]
and PRESTO developed by D. Brown [BRa 8il.
ESPRESSO uses many of the core principles in MINI
and PRESTO while improving on the speed and efficiency of their algorithms.

Oecoupling

The primary advantage of the ESPRESSO minimizer
becomes apparent when designing large finite state machines or complex, product-term intensive logic designs. In these cases, ESPRESSO arrives at the' minimize solution sooner, and frequently reduces the logic
to a smaller number of product terms. In certain cases
where other CAD packages such as ABELTM (PRESTO) or CUPLTM minimize equations to greater than 8
product terms, iPLS II further reduces these equations
to allow the design to fit into devices supporting up to 8
product terms.

Decouple each EPLD with a ceramic capacitor in the
range of 0.01 to 0.2 /kF, depending on board frequency
and current consumption. For most applications, a
0.1 /kF capacitor will suffice. The following equation
produces the exact value:
C=

alee

aV/ar
where

C

=

capacitor value

alee = maximum switched current

av

=

switching level

For more information on ESPRESSO, refer to Logic
Minimization Algorithms for VLSI Synthesis, Brayton,
Hachtel, McMullen, and Sangiovanni-Vincentelli, Kluwer Academic Publishers.

aT = switching time

For boards that contain mixed logic (EPLDs and
TTL), observe both EPLD and TTL decoupling practices.

References
[BRa 81]

D.W. Brown, "A State-Machine Synthesizer-SMS", Proc. 18th Design Automation
Conference, pp. 301-304. Nashville, June
1981.
[HaN 74] S. J. Hong, R. G. Cain and D. L. Ostapko,
"MINI: A heuristic approach to logic minimization." IBM Journal of Research and
Development, Vol. 18, pp. 443-458, September 1974.

Unused Inputs
To minimize noise receptivity and power consumption,
all unused inputs to EPLDs should be connected to
Vee or GND. By default, iPLS II software assigns unused inputs to GND. These pins, shown on the pinout
representation of the iPLS II report file, should be connected to ground on the PCB. Pins listed as RESERVED on the report file must be left floating. Pins
marked N.C. have no internal device connections and
can also be left floating.

ABELTM is a trademark of Data 1/0 Corporation
CUPLTM is a trademark of Personal CAD Systems, Inc.

BOOLEAN MINIMIZATION
TECHNIQUES FOR PLA
ARCHITECTURES'

LOGIC REFRESHER COURSE
Minimization of EPLD logic equations is normally performed by sophisticated algorithms that eliminate the
need for tedious manual reductions. The sections provided here contain logic reference tables for cases where
manual reduction techniques may be desirable.

Minimization plays an important role in logic design.
Methods for minimization can be grouped into two
classes. Class 1 includes manual methods for minimization, such as Boolean reduction or Karnaugh mapping.
Class 2 is computer-assisted minimization.
1-6

intJ

OVERVIEW

Boolean Algebra

Karnaugh Maps

The Sum-of-Product architecture used in EPLDs
makes Boolean algebra ideal for design analysis. The
following tables summarize standard Boolean functions.

Graphical representation of data is usually easier to analyze than strings of ones and zeros. The Karnaugh
Map techniques take advantage of this capability and
provide an important tool to the logic designer.

Properties
S* A
=S+A

A'S
A+S
A • (S

Commutative Property

=

* C)

= (A

* S) • C

Two Variables

Associative Property

A+(S+C)=(A+8)+C
A • (8 + C) = A * S + A * C
Distributive Property
A + 8 * C = (A + 8) * (A + C)

296032-7

Postulates
0*0 = 0
0"1 = 0
1•1 = 1

0+0=0
0+1 = 0
1+ 1= 1

Three Variables
0=1

1=0

Theorems
A"O =
A'1 =
A"A =
A'A =

0
A
A
0

A+O=A
A+1=1
A+A=A
A+A=1

296032-8

A=A

Four Variables
AS

DeMorgan's Theorems
(A + S + C + D)
(A' S' C· D)

CD

A*S'C'O
A+S+C+O

Logic Functions

A
A

e

S

=

A EXCLUSIVE OR B

0

4 12 8

01

1

5 13 9

11

3

7 15 11

10 2

6 14 10

296032-9

AANDA
AORA
A NOT

A'A
A+A

0001 11 10
00

AS+AB

1-7

intJ

OVERVIEW

Five Variables
BC
DE

BC
A=1
DE
00 01 11 10
16 20 28 24 00
17 21 29 25 01
19 23 31 27 11
1822 30 26 10

A=O
0001 11 10
00 0 4 12 8
01 1 5 13 9
11 3 7 15 11
10 2 6 14 10

296032-10

Six Variables
CD
EF"
00
01
11
10

A=O

00
01
11
10

A= 1

EF"

B=O
0001 11
0 4 12
1 5 13
3 7 15
2 6 14

10
8
9
11
10

CD
B=1
EF
0001 11 10
16 20 28 24 00
17 21 29 25 01
19 23 3127 11
18 22 30 26 10

32 36 44 40
33 37 45 41
35 39 47 43

48 52 60 56 00
49 53 61 57 01
51 55 63 59 11

34 38 46 42
0001 11 10

50 54 62 58 10
0001 11 10

EF
CD

i

CD

296032-11

T Truth Table

Flip-Flop Tables
This subsection includes truth tables and excitation tables for the flip-flops supported by EPLDs.

o Truth Table
0

QN

0
0
1
1

0
1
0
1

QN+1
0

0
0
1
1

QN+1
0
1
0
1

QN

0
0
1
1

0
1
0
1

QN+1
0
1
1
0

T Excitation Table

0
1
1

o Excitation Table
QN

T

0
0
1
0
1

1-8

QN

QN+1

T

0
0
1
1

0
1
0
1

0
1
1
0

inter

OVERVIEW

when input transitions are not detected over a short
period of time. The following paragraphs describe how
the Turbo Bit affects power and speed in EPLDs.

JK Truth Table

J

K

QN

QN+1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
0
1
1
1
0

Turbo Off (Low Power)
Intel EPLDs contain circuitry that monitors all inputs
for transitions. When a transition is detected while the
device is in standby mode, the circuit generates an active pulse. The leading edge of this pulse wakes the
device up and the device responds according to its programming, changing outputs as necessary. If no new
transitions occur during the active pulse, the device enters standby mode again. Outputs are always held valid
in standby mode. Input transitions that occur during
the active mode interval retrigger the active pulse. The
active pulse is different depending on the device
(5C060, 5AC312, etc), but is typically 2-4 times the
propagation delay for a particular device.

JK Excitation Table
QN

QN+1

J

K

0

0
1
0
1

0
1
X
X

X
X
1
0

0
1
1

In applications with infrequent input transitions, standby mode can result in significant power savings (see the
appropriate data sheet for standby power vs. active
power). The slight speed loss associated with waking up
a device is in the range of o-to ns, which is small
enough to allow standby mode to be used with most
applications (see the appropriate data sheet for effect of
Turbo Bit on performance).

SR Truth Table

S

R

QN

QN+1

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

0
1
0
0
1
1

1

1

Turbo On (Faster Speed)

Illegal

In cases where the slight speed loss associated with
waking a device from standby mode cannot be traded
off to save power, the Turbo bit can be enabled for
maximum speed operation. With the Turbo Bit enabled, the device is always in active mode, thus avoiding the wakeup delay. Note that data sheet performance is specified with the Turbo Bit enabled.

JK Excitation Table
QN

QN+1

S

R

0
0
1
1

0
1
0
1

0
1
0

X

X

0
1
0

The Turbo Bit is enabled/disabled via a TURBO
ON or TURBO = OFF statement in an iPLS II ADF
OPTIONS: statement. It can also be enabled/disabled
by editing the JEDEC file using device programmable
software. With TURBO = ON the device will be programmed for high speed; with TURBO = OFF the
device will be programmed for automatic standby
(power savings). The default state is OFF.

NOTES:
ON = Present State
ON + 1 = Next State
X = Don't Care

AUTOMATIC STANDBY MODE
(TURBO BIT)

PACKAGING

INTEL EPLDs contain a programmable bit, the Turbo
Bit, that optimizes devices for speed or power savings.
When TURBO = ON, EPLDs are optimized for
speed. When TURBO = OFF, they are optimized for
power savings by automatically entering standby mode

Intel EPLDs are available in several packages to meet
the wide requirements of customer applications. Current information on available packages is available from
your local Intel field sales engineer. Detailed informatiqn on package dimensions, etc. for a particular package is provided in Packaging Outlines and Dimensions,
Order Number 321369, which covers all Intel packages.
1-9

OVERVIEW

ORDERING INFORMATION
Intel EPLDs are identified as follows:

o
'-vJ

5

c

x

'X

I

Device

s

X

'-vJ \.~------~------------/

S
/

\.

Speed

Technology
C -CHMOS
AC- Advanced CHMOS
Package Type
A - Hermetic, Pin Grid Array

AJ -

L *M Q T -

D - Hermetic, Type D (Cerdip) Dip
N - Plastic, Leaded Chip Carrier
CJ - Ceramic, J Leaded Chip Carrier
P - Plastic Dip and Plastic Flatpack
R - Hermetic, Leadless Chip Carrier
X - Unpackaged Device
Indicates automotive operating temperature range (-40°C to + 12S°C)
Indicates a JAN qualified device, but is for internal identification purposes only. All JAN devices must be
ordered by M38SlO part number. (Example: M38S10/42001 BQB), and will be marked in accordance
with MIL-M-38SlO specifications.
Indicates extended operating temperature range ( - 4O"C to + 8S°C) express product with
160 + 8 hrs. dynamic burn-in.
Indicates military operating temperature range (- SsoC to + 125°C)
Indicates commercial temperature range (O°C to 70°C) express product with 160 + 8 hrs. dynamic burnin.
Indicates extended temperature range (-40~C to + 8S°C) express product without burn-in.
No letter indicateS commercial temperature range (OOC to 700C) without burn-in.

Examples:
QDSC060-45 Commercial with burn-in, ceramic Dip, 060 (600 gate) device, 45 nanosecond.
'On military temperature devices, B suffix indicates MIL-STD-883C level B processing.

1-10

EPLDs Erasable Programmable
Logic Devices

2

5C031 ,
,
300 GATE CHMOS H-SERIES ERASABLE
PROGRAMMABLE LOGIC DEVICE (H-EPLD)
•

High Performance, Low Power
Replacement for SSI & MSI Devices
and Bipolar PLDs.

• Up to 18 Inputs (10 Dedicated & 8 1/0)
and 8 Outputs.
• Eight Macrocells with Programmable
1/0 Architecture.
•

•

CHMOS EPROM Technology Based UV
Erasable.

•

Programmable "Security Bit" Allows
Total Protection of Proprietary Designs

•

Icc (standby) 35 mA (max)
Icc (10 MHz) 40 mA (max)

• tpD = 40 ns (max)
• 20-pin 0.3" Windowed CERDIP Package

100% Generically Testable EPROM
Logic Control Array.

(See Packaging Spec., Order # 231369)

• High Performance Upgrade for All
Commonly Used 20-pin PLDs.

•

100% Compatible with EP310'

Vee
I/o
I/o
I/O
I/O
I/O
I/O
I/O
I/o
I/Vpp

INPUT/eLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT

8

INPUT
GND

290154-1

Pin Configuration

2-1

October 1988
Order Number: 290154-002

inter

5C031

The Intel 5C031 H-EPLD (H-series Erasable Programmable Logic Device) is capable of irnplemElnting over 300 equivalent gates of user~customi,zed
logic functions through programming. This device
can be used to replace bipolar programmable logic
arrays and LS TTL and 74HC (CMOS) SSI and MSI
logic devices. The 5C031 can also be used as a
direct, low-power. replacement for almost all common 20-pin fus.e-based programmable logic devices.
With its flexible programmable 1/0 architecture, this
device has advanced functional capabilities beyond
that of typical programmable logic.

ARCHITECTURE DESCRI.PTION
The architecture of the 5C031 is based on the "Sum
of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a
fixed OR array: This device can acco·mmodate both
combiAational and sequential logic functions. A proprietary programmable 1/0 architecture provides individual selection of either combinational or registered output and feedback signals, all with selectable polarity.
The 5C031 contains 10 dedicated inputs as well as 8
input/output pins. These 1/0 pins can be individually
configured to be inputs, outputs or bi-directional 1/0
pins. Each of these 1/0 pins is connected to a macrocell. The 5C031 contains 8 identical macrocells organized as shown in Figure 1.

The 5C031 H-EPLD uses CHMOS EPROM (floating
gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power
consumption of H-EPLOs to less than 20% of a
comparable bipolar device without sacrificing speed
performance. In addition, the use of Intel's advanced
CHMOS II-E EPROM process technology enables
greater logic densities to be achieved with superior
speed and low-power performance over other comparable devices. EPROM technology allows these
devices to be 100% factory tested by programming
and erasing all the EPROM logic control elements.

Each macrocell (see Figure 2) consists of a PLA
(programmable logic array) block and an 1/0 architecture block, which contains a "0" type register.
The PLA block consists of eight 36-input AND gates
(TRUE & COMPLEMENT of 10 dedicated inputs
plus the 8 feedback inputs from the eight macrocells), feeding into an OR gate. The output of this
PLA block is fed into the I/O architecture block. The
different 1/0 and feedback options that are achievable from the 5C031 1/0 block are shown in
Figure 3.

The 5C031 is housed in a windowed 0.3" 20-pin DIP
and has the benefits of being an ideal prototyping
tool with its highly flexible 1/0 architecture.

2-2

5C031

CLOCK

.Q.

3

5
4

7
6

9 11 13 15 17 19 21 23 25 27 29 31 33 35
8 10 12 14 16 18 20 22 24 26 28 30 32 34

290154-2

Figure 1. SC031 Architecture

2·3

l
CLOCK

3

o

~~I

2

T

7

5
4

6

9

s

11
10

13
12

14

12

17
16

21
23
25
27
29
31
33
35
19
1sT 20- 22T 24T 26T 2sT 30- 32T 34--

TI TI TI TITI TITI TI TI TI TI TI TI TI TI TI Til

o~~~~~~-+~-+~-+~-+~-+-+-+-+-;-+-;-+-;-+~~~~~~--r;--r;~r;H

~

~I

PRESET CLOCK

c

Vl

:::;:

Cil

eJ3
l-

~

ARCHITECTURE ~
CONTROL
~

f) ti
'9.
::>4
n Cl

~ .,»

~

~
Q

~

0
Q::
Cl..5

...

Co)

ifl
n
.,

0

n

l!:

7

FEEDBACK

11
NOTE 0

= I/O

2

19

3

18

4

17

5

16

PIN IN WHICH LOGIC ARRAY INPUT IS FROM FEEDBACK PATH

6

15

7

14

8

13

9

-----------J

__- - - - - - - - - - - - - - - - - - - - - - - - - -________________________~I\~ ______________

PLA BLOCK

1/0 ARCHITECTURE
BLOCK
290154-3

inter

5C031

OE

PRODUCT
TERMS

--------------------------.
OUTPUT
SELECT

RESET

FEEDBACK
SELECT
FEEDBACK

-------------------------290154-4

Figure 3. 5C031 1/0 Architecture Control

20 PIN CMOS COMPATIBILITY
The 5C031 is architected to be a logical superset of most 20 pin bipolar programmable array logic (PAL *)
devices. The I/O and logic sections of the 5C031 device can be configured to emulate any of the devices
listed below. Designers can make use of this feature by reducing the power of PAL based systems (EPLDs are
much lower power), replacing multiple PAL inventory items with a single EPLD. Designers can also create new
20 pin PLD configurations by utilizing the individual logic and output controls of each macrocell.
List of PAL devices logically compatible with the 5C031.
10H8
16L2
12H6
16L8
14H4
16R8
16H2
16R6
16H8
16R4
16C1
16P8A
10LB
16RP8A
12L6
16RP6A
14L4
16RP4A
'PAL is a registered trademark of Monolithic Memories, Inc.

2-5

5C031

The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each bit is continually monitored to determine when the bit has
been successfully programmed.

Erased-State Configuration
Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output
with input (pin) feedback.

ERASURE CHARACTERISTICS
FUNCTIONAL TESTING

Erasure characteristics of the 5C031 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 30004oooA. Data shows that constant exposure to room
level flourescent lighting could erase the typical
5C031 in approximately three years, while it would
take approximately one week to cause erasure when
exposed to direct sunlight. If the 5C031 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels
should be placed over the device window to prevent
unintentional erasure.

Since the logical operation of the 5C031 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of the EPROM array are
required.
The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming. These tests must be done at
the device level because of the cummulative error
effect. For example, a board containing ten devices
each possessing a 2% device fallout translates into
an 18% fallout at the board level (it should be noted
that programming fallout of fuse-based programmable logic devices is typically 2% or higher).

The recommended erasure procedure for the 5C031
is exposure to shortwave ultraviolet light with a
wavelength of 2537A. The integrated dose (i.e., UV
intensity X exposure time) for erasure should be a
minimum of fifteen (15) Wsec/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm2
power rating. The 5C031 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the 5C031 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week at
12,000 p.W/cm2). Exposure to high intensity UV light
for longer periods may cause permanent damage to
the device.

DESIGN RECOMMENDATIONS
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN pr VOUT) < Vee. Unused inputs
should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the iPLDS
REPORT file) should be left floating (no connect) so
that the pin can attain the appropriate logic level. A
power supply decoupling capacitor of at least 0.2 p.F
must be connected directly between Vee and GND
pins of the device.

PROGRAMMING CHARACTERISTICS
Initially, and after erasure, all the EPROM control
bits of the 5C031 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cells into
their "0" state. Programming voltage and waveform
specifications are available by request from Intel to
support programming of the 5C031.

As with all CMOS devices, ESD handling procedures
should be used with the 5C031 to prevent damage
to the device during programming, assembly, and
test.

inteligent Programming™ Algorithm
The 5C031 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method.

2-6

inter

5C031

code output files which can be downloaded to other
programmers as well.

DESIGN SECURITY
A single EPROM bit provides a programmable design security feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMA II-PLD, a low-cost
schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entry
and State Machine design entry.

LATCH-UP IMMUNITY

The iPLDS operates on the IBMt PC/XT, PC/AT, or
other compatible machine with the following configuration:
1. At least one floppy disk drive and hard disk drive.
2. MS-DOStt Operating System Version 3.0 or
greater.
3. 512K Memory (640K recommended).
4. Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS).
5. A color monitor is suggested.

All of the input, I/O, and clock pins of the 5C031
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C031 is designed with Intel's proprietary CHMOS II-E EPROM
process. Thus, each of the 5C031 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore,
the programming pin is designed to resist latch-up to
the 13.5V maximum device limit.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)

Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet. (Order Number: 280168)
tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
i"tMS-DOS is a registered trademark of Microsoft
Corporation.

iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will
optimize a design to benefit from architectual features). It contains comprehensive third generation
software that supports four different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
RONF
INP
CONF
ROCF
COCF
RORF
ROlF
CORF
NORF
COIF
NOCF

In addition, the iPLDS II contai[ls programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object

ORDERING INFORMATION
tpD
(ns)

(ns)

fMAX
(MHz)

Order
Code

Package

Operating
Range

40

24

29.5

D5C031-40

CERDIP

Commercial

D5C031-50

CERDIP

Commercial

50

teo

28

22.5

2-7

5C031

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at t,7ese or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Parameter

Min

Max

Units

Vee

Supply Voltage(1)

-2.0

7.0

V

Vpp

Programming
Supply Voltage(1)

-2.0

13.5

V

V,

De Input Voltage(1)(2)

-0.5 Vee+ 0.5

V

t8t9

Storage Temperature

-65

+150

'e

tamb

Ambient Temperature(3)

-10

+85

'e

NOTES:
1. Voltages with respect to ground.
2. Minimum De input is -0.5V. During transitions, the inputs may undershoot to - 2.0V or overshoot to 7.0V for
periods less than 20 ns under no load conditions.
3. Under bias. Extended temperature versions are also
available.

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

Vee

Supply Voltage

4.75

5.25

-V

V,N

Input Voltage

0

Vee

V

\

Vo

Output Voltage

0

Vee

V

TA

Operating Temperature

0

+70

°C

tR

Input Rise Time

500

ns

tF

Input Fall Time

500

ns

D.C. CHARACTERISTICS
Symbol

TA = 0° to + 70°C, Vee = 5V ± 5%

Parameter/Test Conditions

Min

Typ

Max

Unit

V'H(4)

High Level Input Voltage

2.0

Vee + 0.3

V

V'L~4)

Low Level Input Voltage

-0.3

0.8

V

VOH(5)

High Level Output Voltage
10 = -4.0 mA D.C., Vee = min.

VOL

Low Level Output Voltage
10 = 4.0 mA D.C., Vee = min.

0.45

V

I,

Input Leakage Current
Vee = max., GND < V,N

±10

IJ-A

2.4

< Vee

2-8

V

intJ

5C031

D.C. CHARACTERISTICS
Symbol

TA = o·to +70·C, vcc = 5V ±5% (Continued)

Parameter/Test Conditions
Output Leakage Current
Vee = max., GND < VOUT

loz

Min

Typ

Max

Unit

±10

,...A

10

mA

40

mA

< Vcc

Isc!6)

Output Short Circuit Current
Vee = max., VOUT = 0.5V

Icc

Power Supply Current
Vee = max., VIN = Vee or GND
No Load, Input Freq. = 1 MHz
Active mode (Turbo = Off)
Device prog. as 8-bit Ctr.

15

NOTES:
4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included.
5. 10 at CMOS levels (3.84V) = -2 rnA.
6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

.-----5V
INPUT

DEVICE [ > - t -.....-i:> TO TEST
OUTPUT
SYSTE~

OUTPUT

3.0](2.0

0 0 . 8 >TEST POINTS<

V2E
~

1~-TEST POINTS-~
290154-7

341.0.

A.C. Tesung: Inputs are Dnven a13.0V for a logic "'I" and OV tor
a Logic "'0"'. Timing Measurements are made at 2.0V for a Logic
"'1" and O.BV for a Logic "'0" on inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times < 6 ns.

290154-6
CL=50pF

CAPACITANCE
Symbol

Parameter

Conditions

=

Min

Typ

Max

Unit

OV, f = 1.0 MHz

20

pF

=

20

pF

20

pF

50

pF

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT = OV, f

CCLK

Clock Pin Capacitance

VIN = OV, f

CvPp

VppPin

Pin 11

=

2-9

1.0 MHz

1.0 MHz

5C031

A.C. CHARACTERISTICS TA = O·C to + 70·C, vee = 5V ± 5%, Turbo Bit Programmed(7)
Symbol

From

5C031-40
EP310-3

To
Min

Typ

6C031-50
EP310
Min

Max

Typ

Unit
Max

tpD

1/0

Comb. Output

40

50

ns

tpzx(S)

lor 110

Output Enable

40

50

ns,

tpxz(S)

10ril0

Output Disable

40

50

ns

telR

Asynch Reset

QReset

40

50

ns

NOTES:

7. Typical Values are at TA = 25·C, Vee = SV, Active Mode
S. tpzx and tpxz are measured at ±O.SV from steady state voltage as driven by spec. output load. tpxz is measured with
CL = S pF.

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
TA = O·C to +70·C, Vcc = 5.0V ±5%, Turbo Bit On(7)
Symbol

5C031-50
EP310

5C031-40
EP310-3

- Parameter
Min

Typ

Max

Min

Typ

Unit
Max

tMAX

Max. Frequency (Pipelined)
1I (tel + teH)- No Feedback

29.4

22.7

MHz

tCNT

Max. Count Frequency
1ItCNT - With Feedback

22.2

18.1

MHz

tsu

1/0 Setup Time to CLK

32

30

0

ns

tH

I or 1/0 Hold after CLK High

teo

CLK High to Output Valid

tCNT

Register Output Feedback to
Register Input - Internal
Path

45

55

ns

teH

CLK High Time

17

22

ns

tCl

CLKLowTime

17

22

tSET

ns

0
28

24

40

Synch. Set to Q Set

2-10

ns

ns
50

ns

5C031

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

f~=l
! - - - tpxz -

COMBINATORIAL OR
REGISTERED OUTPUT

I

r

HIGH IMPEDANCE

tpzx

\,

HIGH IMPEDANCE

/

3- STATE

~

3- STATE

VALID OUTPUT

tCLR

\

i\

ASYNCHRONOUSLY
CLEAR OUTPUT
290154-8

SYNCHRONOUS CLOCK MODE

CLK1

INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290154-9

2-11

5C031

5C031 Current In Relation to Frequency
100
90

~

~
,~

80
70
60
50
40
l,.....oo" I-"'"
30
20
10

o
o

5

---- - -

10

15

20

25

30 35

fo (MHz)
290154-10

Conditions: TA .. O"C, Vcr; = 5.25V

2-12

inter

5C032
300 GATE CHMOS H-SERIES ERASABLE
PROGRAMMABLE LOGIC DEVICE (H-EPLD)

Performance, Low Power
• High
Replacement for SSI & MSI Devices

•
•
•
•
•
•

and Bipolar PLDs
Up to 18 Inputs (10 Dedicated & 8
• and
8 Outputs

•
•
•

1/0)

Eight Macrocells with Programmable
1/0 Architecture
100% Generically Testable EPROM
Logic Control Array
High Performance Upgrade for All
Commonly Used 20-pin PLDs

CHMOS EPROM Technology Based UV
Erasable
Programmable "Security Bit" Allows
Total Protection of Proprietary Designs
Icc (standby) 100 /LA (max)
Icc (10 MHz) 25 rnA (max)
tpD

=

25 ns (max)

20-pin 0.3" Ceramic and Plastic DIP
Package
(See Packaging Spec., Order #231369)

100% Compatible with EP320

Vee
I/o
I/o
I/o
I/O
I/o
I/o
I/o
I/O
I/Vpp

INPUT/elK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GND

290155-1

Pin Configuration

2-13

October 1988
Order Number: 290155-003

5C032

The Intel 5C032. H-EPLO (H-series Erasable Programmable Logic Device) is capable of implementing over 300 equivalent gates of user-customized
logic functions through programming. This device
can be used to replace bipolar programmable logic
arrays and LS TTL and 74HC (CMOS) SSI and MSI
logic devices. The 5C032 can also be used as a
direct, low-power replacement for almost all common 20-pin fuse-based programmable logic devices.
With its flexible programmable I/O architecture, this
device has advanced functional capabilities beyond
that of typical programmable logic.

ARCHITECTURE DESCRIPTION
The architecture oOhe 5C032 is based on the "Sum
of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a
fixed OR array: This device can accommodate both
combinational and sequential logiC functions. A proprietary programmable liD architecture provides individual selection of either combinational. or registered output and feedback signals, all with selectable polarity.
. .
The 5C032 contains 10 dedicated inputs as well as 8
input/output pins. Th~se I/Opins can be individually
configured to be inputs, outputs or bi-directional liD
pins. Each of these liD pins is connected to a macrocell. The 5C032 contains 8 identical macrocells organized as shown in Figure 1.

The 5C032 H-EPLO uses CHMOS EPROM (floating
gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power
consumption of H-EPLOs to less than 20% of a
comparable bipolar device without sacrificing speed
performance. In addition, the use of Intel's advanced
CHMOS II-E EPROM process technology enables
greater logic densities to be achieved with superior
speed and low-power performance over other comparable devices. Intel's 5C032 has the benefit of
"zero" stand-by power not available on other programmable logiC devices. EPROM technology allows these devices to be 100% factory tested by
programming and erasing all the EPROM logiC control elements.

Each macrocell (see Figure 2) consists of a PLA
(programmable logic array) block and an I/O architecture block, which contains a "0" type register.
The PLA block consists of eight 36-input AND gates
(TRUE & COMPLEMENT of 10 dedicated inputs
plus the 8 feedback inputs from the eight macrocells), feeding into an OR gate. The output of this
PLA block is fed into the liD architecture block. The
different liD and feedback options that are available
in the 5C032 liD block are shown in Figure 3.

The 5C032 with its superior speed and power performance and its plastic package is an ideal production vehicle for high-volume manufacturing. Most
commonly used 20-pin bipolar PLOs can be easily
replaced with this device allowing for tremendous
power consumption savings without sacrificing
speed of operation.

2-14

intJ

5C032

CLOCK

a

~
;E

3

5

7

9 11 1 3 1 5 17 1 9 21 23 25 27 29 31 33 35

.1 It it tIf If

rIfif rIf rII IIf r
II

PLA BLOCK

I/O

I-- ARCHITECTURE

I

2

IIII

rI r I I I I I I I I I I f I I I I

I I I I I I I I I I I IFEEDBACK

PLA BLOCK

3

-

19

CONTROL CK

7

IIIIIIII

r-

r Ir I I I I I I I I I I I I I I I

I/O
ARCHITECTURE
CONTROL CK

j....J

I II I I I I

H

PLA BLOCK

I
I

I/O
ARCHITECTURE
CONTROL CK

t--I

-

I II I I I I I I I I I I I I I

6

r-

~

I/O
ARCHITECTURE
CONTROL CK

15

I

I
PLA BLOCK
I""-

I I I I I I II II LUll U Ul

16

'I

I II I LUll tlH1Ll U

PLA BLOCK

7 r>

17

I

I
PLA BLOCK

5

18

~

ARCHITECTURE
I/O
CONTROL CK

4 D-I'

~

1-1

I

PLA BLOCK

r-

8

'10
ARCHITECTURE
CONTROL CK

}!ba

I

I/o
ARCHITECTURE
CONTROL CK

I

J

PLA BLOCK

I/O
I-- ARCHITECTURE
CONTROL CK

~

9 C>

14

~

13

~

12

1
1
290155-2

Figure 1. 5C032 Architecture

2-15

(
CLOCK

3
.0

2

5

r

4

7
.6'

9
81'"

r

11
10

1~

13

1~

15

r

17

16 ~

1~

19

21
20

23
22

2~

25

27
26 :

2~

29

31
30

33
32

35
34

OE

8J

o

'TI

is
c:

;

~.

2

::::e

eJ3

lI-

"" g4
b

ca
I\)

.!..
0)

n

o

j

(L5

~

CONTROL

oQ:

i:

CLOCK

Db- .., """'""' ..:J
D

til

-j) -va

~

6

Co)

N

I ." " ~ ." ." .~ ." ~ ." ~ ~ ." ~ ~ ." ~ .~ ."I'.oJ
7

~

J..

~

l

~

J.

l

~ ~

i.

J.

l

~

J., J. ~ ~

:I.

,i.

J.

~ ~

,J. ,~

~

-11
~

2

19

3

18

4

17

5

16

6

15

7

14

8

13

.

9

NOTED = I/O PIN IN WHICH LOGIC ARRAY INPUT 15 FROM FEEDBACK PATH
___________________________________________________________________________________________________________

J\~ _ _ _ _ _ _ _ _ _ _ _ _~ _ _ _ _ _ _ _ _ _ _~

PLA BLOCK

~
C)

I/o

ARCHITECTURE
BLOCK
290155-3

intJ

5C032

OE

r-------------------PROOUCT

I/o

TER~S

FEEDBACK

290155-10

Figure 3. 5C032 1/0 Architecture Control

20 PIN CMOS COMPATIBILITY
The 5C032 is architected to be a logical superset of most 20 pin bipolar programmable array logic (PAL *)
devices. The I/O and logic sections of the 5C032 device can be configured to emulate any of the devices
listed below. Designers can make use of this feature by reducing the power of PAL based systems (EPLDs are
much lower power), replacing multiple PAL inventory items with a single EPLD. Designers can also create new
20 pin PLD configurations by utilizing the individual logic and output controls of each macrocell.
List of PAL devices logically compatible with the 5C032.
16V8
. 16L2
10H8
16L8
12H6
16R8
14H4
16R6
16H2
16R4
16H8
16P8A
16C1
16RP8A
10LB
16RP6A
12L6
16RP4A
14L4
'PAL is a registered trademark of Monolithic Memories, Inc.

2-17

inter

5C032

Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output
with input (pin) feedback.

This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each tiit is continually monitored to determine when the bit has
been successfully programmed.

ERASURE CHARACTERISTICS

FUNCTIONAL TESTING

Erased-State Configuration

Erasure characteristics of the 5C032 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room
level flourescent lighting could erase the typical
5C032 in approximately three years, while it would
take approximately one week to cause erasure when
exposed to direct sunlight. If the 5C032 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels
should be placed over the device window to prevent
unintentional erasure.

Since the logical operation of the5C032 is con. trolled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of tile EPROM array are
required.
The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar deviCes based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming. These tests must be done at
the device level because of the cummulative error
effect. For example, a board containing ten devices
each possessing a 2% device fallout translates into
an 18% fallout at the board level (it should be noted
that programming fallout of fuse-base~ programmable logic devices is typically 2% or higher).

The recommended erasure procedure for the 5C032
is exposure to shortwave ultraviolet light with a
wavelength of 2537A. The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (15) Wsec/cm 2 . The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 IJ-W/cm 2
power rating. The 5C032 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the 5C032 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week at
12,000 IJ-W/cm 2 ). Exposure to high intensity UV light
for longer periods may cause permanent damage to
the device.

DESIGN RECOMMENDATIONS
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or VOUT) < Vee. Unused inputs
should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the iPLDS
REPORT file) should be left floating (no connect) so
that the pin can attain the appropriate logic level. A
power supply decoupling capacitor of at least 0.2 IJ-F
must be connected directly between Vee and GND
pins of the device.

PROGRAMMING CHARACTERISTICS
Initially, and after erasure, all the EPROM control
bits of the 5C032 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cells into
their "0" state. Programming voltage and waveform
specifications are available by request from Intel to
support programming of the device.

As with all CMOS devices, ESD handling procedures
should be used with the 5C032 to prevent damage
to the device during programming, assembly, and
test.

inteligent Programming™ Algorithm
DESIGN SECURITY

The 5C032 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programming environment.

A single EPROM bit provides a programmable design security feature that controls the access to"the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisi2-18

5C032

process. Thus, each of the 5C032 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore,
the programming pin is designed to resist latch-up to
the 13.5V maximum device limit.

ble even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

AUTOMATIC STAND-BY MODE
The 5C032 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed
(TURBO = ON), the device is optimized for maximum speed. When the Turbo bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)
iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will
optimize a design to benefit from architectual features). It contains comprehensive third generation
software that supports four different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.

Figure 4 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 15 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
code output files which can be downloaded to other
programmers as well.

After erasure, the Turbo Bit is unprogrammed (OFF):
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

LATCH-UP IMMUNITY

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMAII-PLD.a low-

All of the input, 1/0, and clock pins of the 5C032
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C032 is designed with Intel's proprietary CHMOS II-E EPROM

FIRST
INPUT

---

t

....--~------;lr"""

LAST
INPUT

OUTPUT

CURRENT
OmA

VALID OUTPUT

VALID OUTPUT

ACTIVE MODE

ACTIVE MODE

Icc

Icc

----------------------~~======~--------------290155-14
Figure 4. 5C032 Standby and Active Mode Transitions
2-19

inter

5C032

cost schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entry
and State Machine design entry.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
RONF
RORF
NORF

INP
CONF
COIF

The iPLDS operates onthe IBMt PC/XT, PCI AT, or
other compatible machine with the following configuration:
1. At least one floppy disk drive and hard disk drive.

ORDERING INFORMATION
tpD teo fMAX
(ns) (ns) (MHz)

2. MS-DOStt Operating System Version 3.0 or
greater.
3. 512K Memory (640K recommended).
4. Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS II).

25

15

50

30

17

43.5

20

40

Order
Code

Package

D5C032-25 CERDIP

Operating
Range
Commercial

P5C032-25 PDIP
D5C032-30 CERDIP

Commercial

P5C032-30 POIP

5. A color monitor is suggested.
35
Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet. (Order Number: 280168)

D5C032-35 CERDIP
P5C032-35 PDIP

tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

2-20

Commercial

inter

5C032

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Min

Max

Unit

Vee

Supply Voltage(l)

Parameter

-2.0

7.0

V

Vpp

Programming
Supply Voltage(l)

-2.0

13.5

V

VI

DC Input Voltage(1)(2)

-0.5 Vee+ 0.5

V

tSlg

Storage Temperature

-65

+ 150

·C

tamb

Ambient Temperature(4)

-10

+85

·C

NOTES:
1. Voltages with respect to ground.
2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to - 2.0V or overshoot to 7.0V for
periods less than 20 ns under no load conditions.
3. Under bias, Extended temperature versions are also
available.
4. Extended temperature versions also available.

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

4.75

5.25

V
V

Vcc

Supply Voltage

VIN

Input Voltage

0

Vcc

Vo

Output Voltage

0

VCC

V

TA

Operating Temperature

0

+70

'C

tR

Input Rise Time

500

ns

tF

Input Fall Time

500

ns

D.C. CHARACTERISTICS
Symbol

T A = O'C to 70'C, Vcc = 5V ± 5%

Max

Unit

High Level Input Voltage

2.0

VCC + 0.3

V

VIL(5)

Low Level Input Voltage

-0.3

O.B

VOH(6)

High Level Output Voltage
10 = -4.0 mA D.C., Vce = min.

VOL

Low Level Output Voltage
10 = 4.0 mA D.C., Vce = min.

0.45

V

II

Input Leakage Current
Vee = max., GND < VIN

±10

p,A

±10

p,A

VIH(5)

loz

Parameter/Test Conditions

Min

Typ

V
V

2.4

< Vec

Output Leakage Current
Vee = max., GND < VOUT

< Vee

2-21

50032

D.C. CHARACTERISTICS
,Symbol

TA = O°C to 70°C, Vee = 5V ± 5% (Continued)

'ParametertTest .Conditions

Ise(7)

Output Short Circuit Current
Vee = max., VOUT = 0.5V

ISB(S)

Standby Current
Vee = max., VIN
Standby Mode

=

Min

Max'

Unit

10

mA

10

100

p,A

15

25

mA

Vee or GND,

Power Supply Current
Vee = max., VIN = Vee or GND,
No Load, Input Freq. = 10 MHz
Active Mode (Turbo = Off),
Device Prog. as 8-bit Ctr.

led9 )

Typ

NOTES:
5. Absolute values with respect to device GND; all over· and undershoots due to system or tester noise are included.
6.10 at eMOS levels (3.S4V) = -2 mA.
7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.
S. With Turbo Bit = Off, device automatically enters standby mode approximately 100 ns after last input transition.
9. Maximum Active eurrent at operational frequency is less than 40 mAo

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

.-----sv

3'°--Y20
INPUT

o-Ao~

>TEST POINTS

< vr.o
~

8SSA
DEVICE
OUTPUT C

TO TEST

....- t -...-I:::> SYSTEM

OUTPUT

l~-TEST P01NTS-~
290155-7

341A

A.C. Testing: Inputs are Driven at 3.0V for a Logic "I" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.5V pOint Device input rise and fall times < 6 ns.

290155-6

CAPACITANCE
Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CIN

Input Capacitance

VIN = OV, f = 1.0 MHz

10

pF

COUT

Output Capacitance

VOUT = OV, f = 1.0 MHz

10

pF

CeLK

Clock Pin Capacitance

VIN

10

pF

Gvpp

Vpp Pin

Pin 11

20

pF

=

OV, f

=

2-22

1.0 MHz

intJ

5C032

A.C. CHARACTERISTICS
Symbol

From

=

TA

To

O·C to + 70·C, Vcc

=

5C032-25

5C032-30

Min

Typ

Max

Min

5V ± 5%, Turbo Bit On(10)

Typ

5C032-35

Max

Min

Typ

Max

Non-(8)
Turbo
Mode

Unit

tpD

lor 1/0

Comb. Output

25

30

35

+15

ns

tpZX(11)

lor 1/0

Output Enable

25

30

35

+15

ns

tpXZ(11)

lor 1/0

Output Disable

25

30

35

+15

ns

NOTES:
,
10, Typ, values are at TA = 25°C, Vee = 5V, Active Mode.
11. tpzx and tpxz are measured at ± 0,5V from steady state voltage as driven by spec. output load. tpxz is measured with

Cl

=

5 pF.

A.C. CHARACTERISTICS

T A = O·C to 70·C, VCC = 5V

± 5%, Turbo Bit On (10)

SYNCHRONOUS CLOCK MODE
Symbol

5C032-30
EP320-1

5C032-25

Parameter

5C032-35
EP320-2

Min Typ Max Min Typ Max Min Typ Max

Non-(8)
Turbo Unit
Mode

fMAX

Max. Frequency (Pipelined)
1Itsu - No Feedback

50

43.5

40

MHz

fCNT

Max. Count Frequency
1ItCNT - with Feedback

33.3

28.5

25

MHz

tsu

Input Setup Time to ClK

20

tH

lor liD Hold after ClK High

0

tco

ClK High to Output Valid

tCNT

Register Output Feedback
to Register Input - Internal
Path

30

35

40

tCH

ClK High Time

10

11

12

ns

tCl

ClKlowTime

10

11

12

ns

23

25

0
15

2-23

+15

0
17

ns
ns
ns '

20
+ 15

ns

5C032

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

~~,~
!--tpxz - -

COMBINATORIAL OR
REGISTERED OUTPUT

,

I

HIGH IMPEDANCE
3- STATE

I

!--tpzx ./';1'

HIGH IMPEDANCE
3-STATE

VALID OUTPUT

I'-..
290155-8

SYNCHRONOUS CLOCK MODE

ClK!

INPUT MAY CHANGE

INPUT MAY CHANGE

(fROM REGISTER
TO OUTPUT)

VALID OUTPUT
290155-9

2-24

5C032

Current in Relation to Frequency

Current in Relation to Temperature

50

50r---~--~r---'---~,

40

.."

30
20
10

~

40r----+----+----+----~

"..,.

(TURB
VV V

~

,....

~NON-TURBO

o
o

5

20

10 15 20 25 30 35 40

=

o°C, Vee

=

60

80 85
290155-12

290155-11
Condl1tons: TA

40

TEMP(C)

fCNiMHz)
Condilions: Vee

5.25V

=

5.25V

Output Drive Current in Relation to Voltage
100
50
40
30

-

/

20

IIOL

........ IOH

........

10

~

5
4
3
2

1

o

2

3

4

5

Vo Output Voltage (V)
290155-13
Conditions. T A

=

+ 25°C, Vee

=

5V

2-25

intJ

5C060
600-GATE CHMOS
H-SERIES ERASABLE PROGRAMMABLE
LOGIC DEVICE (H-EPLD)

Performance LSI Semi-Custom
• High
Logic Alternative to Low-End Gate
Arrays, TTL, and 74HC SSI and MSI
Logic

•
Programmable Clock System with Two
• Synchronous
Clocks as Well as

CHMOS EPROM Technology Based. UV
Erasable

Asynchronous Clocking Option on all
Registers

16 Macrocells with Programmable I/O
• Architecture;
up to 20 Inputs (4
Dedicated, 16 I/O) or 16 Outputs
High Speed tpo (max) 45 ns, 16.67 MHz
• Performance
Low Power; 50 J.lA Typical Standby
• Current
Erasable Array for 100% Generic
• Testability
Footprint 24-Pin 0.3" DIP and 28
• Small
Pin J-Leaded Chip Carrier Package

Output Registers. Can
• Programmable
be Configured as 0, T, SR, or JK Types
Security Bit Allows Total
• Programmable
• 100% Compatible with EP600
Protection of Proprietary Designs
(See Packaging Spec. Order #231369)

CLK1

Vee

INPun

INPUT4

1/0.1

1/0.16

1/0.2

1/0.15

1/0.3

1/0.14

1/0.4

1/0.13

1/0.5

1/0.12

1/0.6

1/0.11

1/0.7

1/0.10

1/0.8

1/0.9

INPUT2

GND

1/0.15
1/0.14
1/0.13
1/0.12
1/0.11
1/0.7

1/0.10

NC

NC

INPUT3
CLK2

'"

0

(!>

(!)

Z

290194-1

Z

N

'"
d

290194-2

Figure 1. 5C060 Pin Configurations

2-26

November 1988
Order Number: 290194-001

intJ

5C060

The Intel 5C060 H-EPLD (H-series Programmable
Logic Device) is capable of implementing over 600
equivalent gates of user-customized logic functions
through programming. The device can be used to
replace low-end gate arrays, multiple programmable
logic arrays and LS TTL and 74HC (CMOS) SSI and
MSI logic devices. The 5C060 can also be used as a
direct, low-power replacement for most, common
24-pin fuse-based programmable logic devices. With
its revolutionary programmable 1/0 architecture, the
device has advanced functional capabilities beyond
that of typical programmable logic.
The 5C060 H-EPLD uses CHMOS EPROM (floating
gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power
consumption of H-EPLDs to less than 20% of a
comparable bipolar device without sacrificing speed
performance. In addition, Intel's advanced CHMOS
II-E EPROM process technology enables greater

AND ARRAY

logic densities to be achieved with superior speed
and low-power performance over other comparable
devices. Intel's H-ELPDs add the benefits of "zero"
stand-by power not available on other programmable logic devices. EPROM technology allows these
devices to be 100% factory tested by programming
and erasing all the EPROM logic control elements.
The erasability of EPLDs introduces the designer to
a new concept in hardware design called Modular
EPLD Logic Design (MELD). Just as modular software design speeds development time and reduces
errors by isolating them to a specific module, the
MELD philosophy aids in hardware design. A designer can develop his modular design on the Intel Programmable Logic Development System II (iPLDS II)
and test individual modules for functionality. If one of
the modules has a design flaw, the designer merely
erases the part and starts anew (since the 5C060 is

SYNCHRONOUS

CLOCK
OE/ClK

vcc

l~ElECT
OE

{3- -{
-

I-I--

r-

EPROM
CONTROL
BIT

II

@

8=
8=

\

ClK

OUTPUT

8=

REGISTER

H?-6
OUTPUT

8=

BUFFER

~
~

~

~

~

~

c~

INPUTS AND I/O

~

~

~

A

~REGISTER

I

FEEDBACK

290194-3

Figure 2. Basic Macrocell Architecture of the 5e060
.
2-27

intJ

5C060

EPROM-based, there is no waste associated with
modular design as there would be in fuse-based
PLDs).

ARCHITECTURE DESCRIPTION
Externally, the 5C060 has 4 dedicated data input
pins, 16 I/O pins which may be configured for input,
output, or bidirectional operations, and 2 synchronous clock inputs. The 5C060 is contained in a
24-pin windowed package (0.3 inch wide) or 28-lead
J-Ieaded chip carrier package, and contains 16 programmable registers.

The architecture of the 5C060 is based on the "Sum
of Products" PLA (Programmable logic Array) structure with a programmable AND array feeding into a
fixed OR array. The device accommodates combinational and sequential logic functions. A proprietary
programmable I/O architecture provides individual
selection of either combinatorial or registered output
and feedback signals all with selectable polarity.

The basic Macrocell architecture for the 5C060 is
-shown in Figure 2. The 5C060 has' 16 of these Macrocells (one for each I/O pin). The Macrocell is organized in the familiar sum-of-products structure with a
programmable AND array attached to a fixed OR
term. The inputs to the programmable AND array
originate from the true and complement signals from
each of the dedicated input pins and each of the I/O
control blocks. The 40-input AND array of the 5C060
feeds 160 AND gates (product terms) which are distributed among the 16 available Macrocells within
that device. The global device architecture is shown
in Figure 3.
-

A feature unique to the 5C060 is the ability to individually program the output registers as a D-, T-, SR-, or
JK-type Flip-Flop without sacrificing the utilization of
programmable AND logic. Additionally, each output
register can be individually clocked from any of the
input or feedback paths available within the AND array. With these features, a wide variety of logic functions can be simultaneously implemented-all on the
same device.

DEDICATED
INPUTS

DEDICATED
INPUTS

IAACROCELLS

IAACROCELLS

I/O

I/O

8 IAACROCELLS •

• 8 IAACROCELLS

••

•
•

AND RRAY

I/O ....... "'---'

GND

VCC

290194-4

Figure 3. 5C060 Global Architecture

2-28

inter

5C060

The Macrocells contain ten product terms total.
Eight of the ten product terms (AND gates) are dedicated for logic implementation. One product term on
each Macrocell is used for RESET control to the
output register associated with the Macrocell. The
final product term is used for OUTPUT ENABlEI
Asynchronous Clock implementation.

Output Enable (OE)/Clock Selection
Two modes of operation are provided by the
OE/ClK Select Multiplexer as a part of each Macrocell. One mode provides for three-state buffering of
outputs while in the other mode, the outputs are always enabled. The operation of the OE/ClK Select
Multiplexer sets the mode within a given Macrocell.
Therefore, the output mode can be selected individually on every output. Figure 4 illustrates the two
modes of OE/ClK operation.

Within the AND array, there is an EPROM connection at every intersection of an input signal (true and
complement) and a product term to a given Macrocell. Before programming an erased device, every
EPROM connection is made at every intersection.
But during the programming process, these connections are opened so that only the desired connections remain. Therefore, the true or complement of
any input signal can be connected to any product
term. If both the true and complement connections
of any signal are left intact, a logical false results on
the output of the AND gate. However, if both the true
and complement connections are open, then a logic
"don't care" results on the AND gate. lastly, if all
the inputs of a product term are programmed open,
then a logical true results on the output of the AND
gate.

MODE 0: THREE-STATE BUFFERING

In Mode 0, the three-state output buffer is controlled
by a single product term originating from the AND
array. The output is enabled when the product term
is a logical true. Conversely, the output appears as
high impedance when the product term is a logical
false as shown in Table 1. In Mode 0, the Macrocell
Flip-Flop is connected to its associated synchronous
clock (either ClK1 or ClK2 depending upon the
Macrocell's location within the device). Thus, the
Macrocell Flip-Flop may be clocked by its respective
synchronous clock but its output will not become
valid until the output is enabled.

The 5C060 has two dedicated clock inputs to provide synchronous clock signals to the internal registers. Each of the clock signals controls half the total
registers within the given device. For example, ClK1
provides synchronous clocking to the registers in
Macrocells' in the left half of the array while ClK2
controls the registers associated with Macrocells in
the right half of the array. The advanced 1/0 architecture allows for any number of the registers to be
synchronously clocked (from none to all). Both of
the dedicated clock inputs latch the data into a given
register when triggered on a positive edge.

Table 1. Mode 0 Output Selection
Product Term

Output Buffer

FALSE

Three-State

TRUE

Enabled

MODE 1: OUTPUT BUFFER ENABLED

In Mode 1, the Output Buffer is always enabled. In
addition, the Macrocell Flip-Flop is connected to the
AND array. The Macrocell Flip-Flop may now be triggered from an asynchronous clock signal generated
by the AND array logic to the OE/ClK multiplexable
term. Mode 1 allows the Macrocell Flip-Flops to be
individually clocked from any of the available signals
in the AND array. Since both true and complement
values appear in the AND array, the Flip-Flop may
be configured to trigger on positive or negative clock
edges. Gated clock structures can be created since
the Flip-Flop clock is created by a product term.

MACROCELL ARCHITECTURE
SELECTION
The 5C060 architecture provides each Macrocell
with over 50 different possible 1/0 register configurations. Each 1/0 pin can be configured for combinatorial or registered output (true or complement) with
feedback. In addition, four different types of output
registers can be implemented into every 1/0 pin
without any additional logic requirements. The feedback mechanism for each register back into the
AND array can be programmed to provide for either
registered feedback from the Macrocell or input
feedback (treating the pin as an input). Another advantage of the advanced 1/0 capability of the 5C060
is the ability to individually clock each internal register from asynchronous clock signals.

Invert Select EPROM Bit
The Invert Select EPROM bit is used to invert the
product term input into the register. This applies to
all inputs including double inputs on the JK and SR
registers.

2-29

seaGO
MODE 0
SYNCHRONOUS
CLOCK
VCC

OE/ClK
SELECT

OE
OE/ClK

ClK - SYNCHRONOUS
ClK

OE - P-TERM CONTROllED

OUTPUT
REGISTER
OUTPUT
BUFFER

290194-5

MODE 1
SYNCHRONOUS
CLOCK
VCC

OE/ClK
SELECT

OE

ClK - ASYNCHRONOUS
ClK

OE- ENABLED

OUTPUT
REGISTER
OUTPUT
BUFFER

290194-6

Figure 4. Output Enable/Clock Configuration

2-30

intJ

5C060

When either a JK or SR register is configured, the
eight product terms are shared among two OR
gates (one for the J or S input and the other for
the K or R input). The allocation for these product
terms for each of the register inputs is optimized
by the iPLDS II development software.

REGISTER SELECTION
The advanced I/O architecture of the 5C060 allows
four different register types along with combinatorial
output as illustrated in Figure 5a. The register types
include a T, D, JK, or SR Flip-Flop and each Macrocell I/O structure may be independently configured.
In addition, all registers have an individual asynchronous RESET control from a dedicated product term
derived in the AND array. When this dedicated product terf!! is a logical one, the Macrocell register is
immediately cleared to a logical zero independent of
the register clock. The RESET function occurs automatically on power-up.

OUTPUT IFEEDBACK
The Output Select Multiplexer allows for either registered, combinatorial or no output.
The Feedback Select Multiplexer EPROM bit enables registered, I/O (using the pin for bidirectional
input or just input), or no feedback to the AND array.

Output Register Configuration

The Feedback Select is also important for building
product terms with more than 8 products. The 8product product term of a Macrocell can be fed back
into the AND array and combined with still more signals to create a much larger product term (of more
than 8-inputs). In addition, if the feedback product
term is not to be output, then the iPLDS II will reserve the associated Macrocell pin and indicate it in
the REPORT file. A reserved pin should be left floating (no connect) when assembled onto a circuit
board.

The four different register types shown in Figure 5b5e are described below.
D- or T-type Flip-Flops
When either a D- or T-type Flip-Flop is configured
as part of the I/O structure, all eight of the product
terms into the Macrocell are ORed together and
fed into the register input.
JK or SR Registers

Any I/O pin may be configured as a dedicated input
by selecting no output and pin feedback through the
appropriate multiplexers.

I/O SELECTION

OUTPUTIPOLARITY

FEEDBACK

Combinatorial/High
Combinatorial/Low
None

Pin, None
Pin, None
Pin

290194-7

Figure,5a. Combinatorial I/O Configuration
2-31

intJ

5C060

SYNCHRONOUS

CLOCK

I/O SELECTION

vee

0'

OUTPUTI
POLARITY

FEEDBACK

D-RegisterIHigh
D-Register/Low
None
None

D-Register, Pin, None
D-Register, Pin, Nore
D-Registered
Pin

FUNCTION TABLE
D

On

0
0

0

1
1

0

On+ 1
0
0
1

1

1

1

290194-8

Figure 5b. D-Type Flip-Flop Register Configuration
SYNCHRONOUS
CLOCK

vee

I/O SELECTION

~~~~~

0'

OUTPUTIPOLARITY

FEEDBACK

T-Register/High
T-Register/Low
None
None

T-Register, Pin, None
T-Register, Pin, None
T-Register
Pin

FUNCTION TABLE
T

On

On + 1

0
0

0

0

1

1
1

0

1
1

1

0

290194-9

Figure 5c. Toggle Flip-Flop Register Configuration
2-32

inter

5C060

SYNCHRONOUS

CLOCK

vee

1/0 SELECTION

DE/elK
SELECT

OE

OUTPUT IPOLARITY

FEEDBACK

JK Register/High
JK Register/Low
None

JK Register, None
JK Register, None
JK Register

FUNCTION TABLE

eLK

J

K

On

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

On + 1
0
1
0
0
1
1
1
0

Figure 5d. JK Flip-Flop Register Configuration
SYNCHRONOUS
CLOCK

vee

1/0 SELECTION

OE/elK
SELECT

OE

OUTPUTIPOLARITY

FEEDBACK

SR Register/High
SR Register/Low
None

SR Register, None
SR Register, None
SR Register

FUNCTION TABLE
CLK

S

R

0
0
0
0
1
1

0
0
1
1
0
0

1

1

290194-11

Figure 5e. SR Flip-Flop Register Configuration
2-33

On
0
1
0
1
0
1

On+ 1
0
1
0
0
1
1
Illegal

intJ
Erased-State

5C060

ming time while programming reliability is ensured as
the incremental program margin of each bit is continually monitored tQ determine when the bit has
been successfully programmed.

Co~figuration

Prior to programming or -after erasing, the 1/0 structure is configured for combinatorial active low output
with input (pin) feedback.

FUNCTIONAL TESTING
ERASURE CHARACTERISTICS

Since the logical operation of the 5C060 is
controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit
controlling the internal logic is tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM
array are required.

Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 3000A4000A. Data shows that constant exposure to room
level flourescent lighting could erase the typical device in approximately three years, while it would take
approximately one week to cause erasure when exposed to direct sunlight. If the 5C060 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels
should be placed over the device window to prevent
unintentional erasure.

The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming. These tests must be done at
the device level because of tne cummulative error
effect. For example, a board containing ten devices
each possessing a 2% device fallout translates into
an 18% fallout at the board level (it should be noted
that programming fallout of fuse-based programmable logic devices is typically 2% or higher).

The recommended erasure procedure for the 5C060
is exposure to sho.rtwave ultraviolet light with a
wavelength of 2537A. The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (15) Wsec/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm 2
power rating. The 5C060 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the ·5C060 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week at
12,000 p.W/cm 2). Exposure to high intensity UV light
for longer periods may cause permanent damage to
the device.

DESIGN RECOMMENDATIONS
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or VOUT) < Vee. Unused inputs
should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the logic
compiler REPORT file) should be left floating (no
connect) so that the pin can attain the appropriate
logic level. A power supply decoupling capacitor of
at least 0.2 p.F must be connected directly between
Vee and GND pins of the device.

PROGRAMMING CHARACTERISTICS
Initially, and after erasure, all the EPROM control
bits of the 5C060 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cells into
their "0" state. Programming voltage and waveform
specifications are available by request from Intel to
support programming of the 5C060.

As with all CMOS devices, ESD handling procedures
should be used with the 5C060 to prevent damage
to the device during programming, assembly, and
test.

inteligent Programming™ Algorithm

DESIGN SECURITY

The 5C060 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall program-

A single EPROM bit provides a programmable design security feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices

2-34

inter

5C060

since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

LATCH-UP IMMUNITY
All of the input, 1/0, and clock pins of the 5C060
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C060 is designed with Intel's proprietary CHMOS II-E EPROM
process. Thus, each of the pins will not experience
latch-up with currents up to 100 mA and voltages
ranging from -1V to Vee + 1V. Furthermore, the
programming pin is designed to resist latch-up to the
13.5V maximum device limit.

AUTOMATIC STAND-BY MODE
The 5C060 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed
(TURBO = ON), the device is optimized for maximum speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)
iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will
optimize a design to benefit from architectual features). It contains comprehensive third generation
software that supports four different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.

Figure 6 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 25 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.
After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

FIRST
INPUT

t

""---------\
,-------------------------------\

LAST
INPUT

VALID OUTPUT

OUTPUT

CURRENT

VALID OUTPUT

ACTIVE MODE

ACTIVE MODE

Icc

Icc

OmA
290194-12

Figure S. 5COSO Standby and Active Mode Transitions

2-35

5e060

In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer
Pers~lnal Computer to enable the user to program
EPLDs, read and verify programmed devices and
also to graphically edit programming files. The software generates industry standard JEDEC object
code output files which can be downloaded to other
programmers as well.

Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet. (Order Number: 280168)
tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMA II-PLD, a low-cost
schematic capture package that supports EPLD
primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager,
which provides a single user interface to both SCHEMA II-PLD and iPLS II software.The other design formats supported are Boolean equation entry and
State Machine design entry.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
'
device:
JOJF
JONF
SONF
SOSF
TOIF
TONF
TOTF
CLKB

INP
CONF
COIF
RONF
RORF
ROlF
NORF
NOJF
NOSF
NOTF

The iPLDS II operates on the IBMt PC/XT, PC/AT,
or other compatible machine with the following configuration:
1. At least one floppy disk drive and hard disk drive.
2. MS-DOStt Operating System Version 3.0 or
greater.
3. 512K Memory (640K recommended).

ORDERING INFORMATION
tpD teo fMAX
(ns) (ns) (MHz)

4. Intel iUP-PC Universal Programmer Personal
Computer and GUPI Adaptor (supplied with iPLDS
II).

45

22

26

5. A color monitor is suggested.

Order
Code

Package

D5C060-45 CERDIP

Operating
Range

Commercial

P5C060-45 PDIP
N5C060-45 PLCC
55

25

23

D5C060-55 CERDIP
P5C060-55 PDIP
N5C090-55 PLCC

2-36

Commercial

intJ

5C060

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Max

Units

Vee

Supply Voltage(1)

Parameter

-2.0

7.0

V

Vpp

Programming
Supply Voltage(1)

-2.0

13.5

V

VI

DC Input Voltage(1)(2)

-0.5 Vee+ 0.5

V

tSlg

Storage Temperature

-65

+150

tamb

Ambient Temperature(3)

-10

+S5

'c
'c

Symbol

Min

NOTES:
1. Voltages with respect to ground.
2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to - 2.0V or overshoot to 7.0V for periods less
than 20 ns under no load conditions.
3. Under bias. Extended temperature versIons are also available.

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

Vee

Supply Voltage

4.75

5.25

V

VIN

Input Voltage

0

Vee

V

Vo

Output Voltage

0

Vec

V

TA

Operating Temperature

0

+70

'C

tR(4)

Input Rise Time

500

ns

tF(4)

Input Fall Time

500

ns

NOTE:
4. tR, tF for elK is 250 ns max.

D.C. CHARACTERISTICS
Symbol

T A = O°C to 70°C, Vee = 5.0V ± 5%

Parameter

Conditions

Min Typ

Max

Unit
V

VIH(5)

HIGH Level Input Voltage

2.0

Vee + 0.3

Vll(5)

LOW Level Input Voltage

-0.3

0.8

VOH(6)

2.4
= -4.0 mA DC, Vee = Min.
LOW Level Output Voltage 10 = 4.0 mA DC, Vee = Min.
Input Leakage Current
Vee = Max., GND < VIN < Vee
Output Leakage Current
Vee = Max., GND < VOUT < Vee
Output Short Circuit Current Vee = Max., VOUT = 0.5V
Standby Current
Vee = Max.,
(Standby)
VIN = Vee or GND
Power Supply Current
No Load,
Vee = Max.,
(Active) (Turbo Bit Off)
VIN = Vee or GND Input Freq. = 1 MHz

VOL
II
loz
Ise(7)
ISB(S)
5COSO
lec
5COSO

HIGH Level Output Voltage 10

0.45

V

±10.0

/LA

±10.0

/LA

20

30

mA

50

100

/LA

10

15

mA

Device Prog. as 1S-Bit Ctr.
NOTES:
5. Absolute values with respect to device GND; all over and undershoots due to system or tester nOIse are Included.
6.10 at CMOS levels (3.S4V) = -2 mA.
7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.
S. With Turbo Bit Off, device automatically enters standby mode approximately 100 ns after last input transition.

2-37

V
V

inter

5C060

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT
DEVICE
OUTPUT

3.0](20 >

D-+-....-C> TO
TEST
SYSTEM
341.(1

OUTPUT

°

.

TEST POINTS

_0.8

< )(;0.
.

0.8

l~-TEST POINTS---~

290194-14
A.C. Testing: Inputs are Driven at 3.0V for a LogiC "I" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times < 6 ns.

290194-13

CAPACITANCE
Parameter

Symbol

Conditions

CIN

VIN

COUT

Output Capacitance

VOUT

CCLK

Clock Pin Capacitance

VIN

Cvpp

Vpp Pin

CLK2 on 5C060

A.C. CHARACTERISTICS

Min

Typ

= OV, f = 1.0 MHz

Input Capacitance

=

= OV, f = 1.0 MHz
OV, f = 1.0 MHz

Max

Unit

20

pF

20

pF

20

pF

50

pF

TA = O°C to 70°C, VCC = 5V ± 5%, Turbo Bit On(9)

Device
Symbol

From

5C060-45
EP600-3

To
Min

Typ

5C060-55
EP600
Max

Min

Typ

Non-{ll)
Turbo
Mode

Unit

Max

tpDl

Input

Comb. Output

43

53

+25

ns

tpD2

1/0

Comb. Output

45

55

+25

ns

tpzx(10)

lor 1/0

Output Enable

45

55

+25

ns

tpXZ(10)

lor 1/0

Output Disable

45

55

+25

ns

tClR

Asynch. Reset

Q Reset

45

55

+25

ns

NOTES:
9. Typical Values are at TA = 25'C, Vcc = 5V, Active Mode.
10. tpzx and tpxz are measured at ±0.5V from steady state voltage as driven by spec. output load. tpxz is measured with

CL = 5 pF.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode). increase time by amount shown.

2-38

intJ

5e060

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC
TA = O·C to 70·C, Vcc = 5.0V

± 5%,

Turbo Bit On(9)

Device
Symbol

Parameter
Min

Typ

Non·(ll)
Turbo
Mode

5C060-55
EP600

5C060·45
EP600·3
Max

Min

Typ

Unit

Max

fMAX

Max. Frequency (Pipelined)
(1 Itsu-No Feedback)

26.3

23.3

MHz

fCNT

Max. Count Frequency
(1 ItCNT-With Feedback)

22.2

18.2

MHz

tSUl

Input Setup Time to ClK

36

41

+25

ns

tSU2

1/0 Setup Time to ClK

38

43

+25

ns

tH

lor 1/0 Hold after ClK High

0

0

tco

ClK High to Output Valid

tCNT

Register Output Feedback
to Register Input-Internal
Path

teH
tel

ns
25

22

ns
+25

ns

45

55

ClK High Time

17.5

21.5

ns

ClK low Time

17.5

21.5

ns

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
T A = O·C to 70·C, Vcc

=

5.0V ± 5%, Turbo Bit On(8)

Device
Symbol

5C060·45
EP600·3

Parameter
Min

Typ

Non·(ll)
Turbo
Mode

5C060·55
EP600
Max

Min

Typ

Max
18.2

22.2

Unit

MHz

fACNT

Max. Count Frequency
(1 ItACNr-With Feedback)

tASUl

Input Setup Time to
Asynch. Clock

10

10

+25

ns

tASU2

1/0 Setup Time to
Asynch. Clock

12

12

+25

ns

tAH

Input or 1/0 Hold After
Asynch. Clock

15

15

tACO

Asynch. ClK to Output Valid

tACNT

Register Output Feedback
to Register Input-Internal
Path

tACH
tACl

ns
+25

ns

45

55

58

+25

ns

Asynch. ClK High Time

17.5

21.5

+25

ns

Asynch. ClK low Time

17.5

21.5

+25

ns

50

2-39

inter

5C060

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

~'''j
!---tpxz -

(FROM REGISTER
TO OUTPUT)

"-

I

r

HIGH IMPEDANCE
3- STATE

HIGH IMPEDANCE
3-STATE

I
tpzx -

~.~

~V'

VALID OUTPUT

1'0..

ASYNCHRONOUSLY
CLEAR OUTPUT
290194-15

SYNCHRONOUS CLOCK MODE

CLK1,CLK2

J

ir=tCH:=j

1\. . . __. . . .

INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290194-16

2-40

inter

5C060

SWITCHING WAVEFORMS (Continued)
ASYNCHRONOUS CLOCK MODE

ASYN. - - - - ' \ ,
CLOCK
INPUT _ _ _oJ

OTHER
INPUT

(FROIoi REGISTER
TO OUTPUT)

VALID OUTPUT

290194-17

5C060
Current In Relation to Frequency
120

<5
oJ?
"

110
100
90
80
70
60
50

5C060
Current In Relation to Temperature

/
/
/'
./

r;,,

TO TEST

°

TEST POINTS

~~

<: ~20.

.

O~

0-+-....-1:> SYSTEM

CL (INCLUDES JIG
CAPACITANCE)

......,

341.n

'--

OUTPUT

1""i!J.,.-

TEST POINTS

-~

290195-14
A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a L09ic
"1" and O.BV for a LogiC "0" on Inputs. Outputs are measured at
a 1 .5V point. Device Input rise and fall times < 6 ns.

290195-13
CL = 50pF

CAPACITANCE
Symbol

Parameter

Conditions

Min

COUT

Output Capacitance

CCLK

Clock Pin Capacitance

= OV, f = 1.0 MHz
VOUT = OV, f = 1.0 MHz
VIN = OV, f = 1.0 MHz

CvPp

Vpp Pin

CLK2 on 5C090

CIN

Input Capacitance

A.C. CHARACTERISTICS

Typ

VIN

TA = O·C to 70·C, Vcc = 5V

Max

Unit

20

pF

20

pF

20

pF

80

pF

± 5%, Turbo Bit On(9)
Device

Symbol

From

5C090-50
EP900-2

To
Min

Typ

5C090-60
EP900
Max

Min

Typ

Non-(ll)
Turbo
Mode

Unit

Max

tpDt

Input

Comb. Output

45

55

+25

ns

tpD2

1/0

Comb. Output

50

60

+25

ns

tpzx(10)

lor I/O

Output Enable

50

60

+25

ns

tpXZ(10)

lorllO

Output Disable

50

60

+25

ns

tCLR

Asynch. Reset

Q Reset

50

60

+25

ns

NOTES:
9. Typical Values are at TA = 2SoC, VCC = SV, Active Mode.
10. tpzx and tpxz are measured at ± O.SV from steady state voltage as driven by spec. output load. tpxz is measured with

CL

= S pF.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown.

2-54

inter

seogo

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC
= O°C to 70°C, VCC = 5.0V ± 5%, Turbo Bit On(9)

TA

Device
Symbol

Se090·S0
EP900·2

Parameter
Min

Typ

Non·(11)
Turbo
Mode

Se090·60
EP900
Max

Min

Typ

Unit

Max

fMAX

Max. Frequency (Pipelined)
(1 Itsu-No Feedback)

fCNT

Max. Count Frequency
(1 ItcNr-With Feedback)

tSU1

Input Setup Time to ClK

36

43

+25

ns

tSU2

1/0 Setup Time to elK

38

46

+25

ns

tH

lor 1/0 Hold after ClK High

0

0

tco

ClK High to Output Valid

tCNT

Register Output Feedback
to Register Input-Internal
Path

tcH
tCl

26.3

21.7

MHz

20

16.7

MHz

ns

23

ns

25

50

60

+25

ns

ClK High Time

17.5

23

ns

ClKlowTime

17.5

23

ns

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
T A = O°C to 70°C, VCC = 5.0V ± 5%, Turbo Bit On(8)
Device
Symbol

Se090·S0
EP900·2

Parameter,
Min

Typ

Non·(11)
Turbo
Mode

Se09O-60
EP900
Max

Min

Typ

Unit

Max

fACNT

Max. Count Frequency
(1 ItACNT-With Feedback)

tASU1

Input Setup Time to
Asynch. Clock

10

10

+25

ns

tASU2

1/0 Setup Time to
Asynch. Clock

13

15

+25

ns

tAH

Input or 1/0 Hold After
Asynch. Clock

15

15

tACO

Asynch. ClK to Output Valid

tACNT

Register Output Feedback to
Register Input-Internal Path

tACH
tACl

,

20

16.7

48

MHz

ns
59

+25

ns

50

60

+25

ns

Asynch. ClK High Time

17.5

23

+25

ns

Asynch. ClK low Time

17.5

23

+25

ns

2·55

intJ

5eOgO

SWITCHING WAVEFORMS
COMBINATORIAL MODE

~~O~

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

,

\ . - - tpxz - (FROM REGISTER
TO OUTPUT)

I

r

HIGH IMPEDANCE
3 - STATE

I
tpzx

HIGH IMPEDANCE
3- STATE

VALID OUTPUT

'w~

ASYNCHRONOUSLY
CLEAR OUTPUT
290195-15

SYNCHRONOUS CLOCK MODE

.
CLK1,CLK2

Ir=tCH~

--.A'

. . .___

~

INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290195-16

2-56

seogo
SWITCHING WAVEFORMS (Continued)
ASYNCHRONOUS CLOCK MODE

1___,~4___. f'~ 1. . .__

~Wf~ ___~f'~
OTHER
INPUT

------------~
INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT

290195-17

SC090

SC090

Current in Relation to Frequency

Output Drive Current in Relation to Voltage
100

200

v

180
160
140

<~
u

.2

/'

120

V

"/

60

20
10

:;
:;

5

IOL

:::9

o

5

10

15

20

25

30

35

\
2

3

4

290195-19
Conditions: TA

290t95-18
~

IOH " \

Vo Output Voltage (v)

fo (MHz)
Conditions. T A

.....

1

o

o

- '"

--

I

20

I

0

I

40

c

u

Q.

/7

80

50

~

./

100

::;-

.5

O'C, Vee

~

5.25V

2-57

~

25'C

5C121
1200 GATE CHMOS
H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE
•

High Performance LSI Semi-Custom
Logic Replacement for Gate Arrays and
Conventional Fixed Logic

•

EPROM Technology Based. UV
Erasable

•

Programmable Macrocell and I/O
Architecture; up to 36 Inputs or 24
Outputs, 28 Macrocells Including 4
Buried Registers

•

Advanced Architecture Features
Including Programmable Output
Polarity (Active High/Low), Register
By-Pass and Reset Controls

•

Programmable Clock System for Input
Latches and Output Registers

•

Product-Term Sharing and Local Bus
Architecture for Optimized Array
Performance

•

All Inputs are Latchable with a
Programmable Latch Feature

•

Compatible with LS TTL and 74HC
CMOS Logic

•

High Speed tpD (Max) 50 ns Operating
Frequency (Max) 20 MHz

•

Register Pre-Load and Erasable Array
for 100% Generic Testability

•

Low Power; 15 mW Typical Standby
Dissipation

•

Programmable "Security Bit" allows
total protection of proprietary designs

•

Typical Usable Gate Count of 1200
2-lnput NAND Gates

•

Available in a 40-Lead Window Cerdip
Package (See Packaging Spec, Order #231369)

•

Fully Compatible with EP1210

The Intel 5C121 H-EP~D (H-series Erasable Programmable Logic Device) is an LSI logic circuit that is user
customizable through programming. This device can be used to replace gate arrays, multiple programmable
logic arrays and LS TTL and 74HC CMOS SSI and MSI logic devices. The logic capacity of the 5C121 is
typically equal to 1200 two-input NAND gates.
Pin Configuration
elKl

Vee/Vpp
Vee

17
18

Is/ClK2

19

15

110

14

111

13

112

12

1/°1

11

1/°2

1/°24

1/°3

1/°23

1/°4

1/°22

1/°5

1/°21

1/°6

1/°20

1/°7

1/°19

1/°8

1/°18

1/°9

1/°17

1/°10

1/°16

1/°11

1/°15

1/°12

1/°14

Vss

1/°13
290098-1

ILLUSTRATIONS COURTESY OF ALTERA CORPORATION.
2-59

October 1988
Order Number: 290098-005

infef

5C121

The 5C121 H-EPLD uses CHMOS' EPROM (floating
gate) cells as logic control elements instead of fuses. Use of Intel's advanced CHMOS II-E EPROM
process technology enables greater logic densities
to be achieved with superior speed and power performance. The EPROM technology also enables
these devices to be 100% factory tested by the programming and tlie erasure of all the EPROM logic
control elements in the device.

product terms (AND gates) each containing 64 input
signals.
The, macrocells share a common programmable
clock system (described in a later section) that controls clocking of all registers and input latches. The
device contains 8 modes of clock operation that allow logic transition to take place on either rising or
falling edges of the clock signals.

The architecture of the 5C121 is based on the' 'Sum
of Products' PLA (Programmable Logic Array) structure with a programmable AND array feeding into a .
fixed OR array. Flexibility in accommodating logical .
functions without the overhead of unnecessary product terms or speed penalties of programmable OR
structures is achieved through the provision of a
range of OR gate widths as well as through product
term sharing. The use of a segmented PLA structure
with local and global connectivity allows for further
improvements in performance. The 5C121 also contains innovative architectural features that provide
extensive Input/Output flexibility.

ARCHITECTURE DESCRIPTION
The 5C121 H-EPLD has 12 dedicated inputs as well
as 24 Input/Output pins. All inputs to the circuit
(both dedicated and I/O inputs) may be latched using transparent 7475 type latches. In addition to
these 36 input latches, 28 D type registers are also
provided.

The device also contains four macrocells whose outputs are not tied to any 110 pin but feed back into
the array to create buried state-functions. The feedback path may be either the registered or combinational result of the PLA output. The use of the buried
state macrocells provides maximum equivalent logic
density without demanding higher pin-count packages that consume valuable board space.

MACROCELL I/O ARCHITECTURE
The Input/Output architecture of the 5C121 macrocell (see Figure 1) can be programmed using both
static and dynamic controls. The static controls remain fixed after the device is programmed whereas
the dynamic controls may change state as a result
of the signals applied to the device.
The static controls set the inversion logic (i), register
by-pass (ii) and input feedback multiplexers (iii). In
the latter two cases these controls operate on four
macrocells as a bank.

The internal architecture of the 5C121 H-EPLD is
based on 28 macrocells. Each macrocell (see Figure
1) contains a PLA structure (programmable AND array product terms connected to an OR gate) and an
I/O architecture control block (with a D Flip-Flop)
that can be programmed to create many different
output logic structures. This powerful I/O architecture can be configured to support both active-high,
active-low, 3-state, open drain and bi-directional
data ports all on a 4-bit wide basis. They can also
act as inputs on a nibble wide basis with optional
input latching.

The buried-state registers have simpler controls that
determine if the feedback is to be registered or combinational.
The inversion control logic, marked (i) in Figure 1, is
achieved by programming the EPROM control bit
connected to the same XOR gate as the output from
the PLA structure. Programming or erasure of this
EPROM element toggles the OR gate output of the
PLA between active-high and active-low. The inversion control operates on an individual macrocell basis.

Macrocells in each half of the circuit are grouped
together for 1/0 architecture programming. Each
bank of four macrocelis can be further programmed
on an individual macrocell basis to generate active
high or active low outputs of the logic function from
the PLA.

The register by-pass control, marked (ii) in Figure 1
allows the PLA output to either flow through the D
Flip-Flop as a registered output or by-pass the FlipFlop and be a combinational output.
The dynamic controls consist of a programmable input latch-enable as well as reset and output enable
product terms. The latch-enable function is common
throughout the 5C121 and once chosen, will latch all
the inputs. This function is programmed by the clock
control block but may also be driven by input signals
applied to pin 1 (see clock modes-Table 1).

The primary logic array of the 5C121 is segmented
into two symmetrical halves that communicate via
global bus signals. The main array contains some
15104 programmable elements representing 236

*CHMOS is a patented process of Intel Corporation.

2-60

inter

5C121

PLA BLOCK

I/O ARCHITECTURE BLOCK

EPROIA
CONTROL
BIT
290098-2

Figure 1. 5C121 Macrocelil/O Architecture

The reset and output·enable controls are logically
controlled by single product terms (the logic AND of
programmed variables in the array). These terms
have control over banks of four macrocells.

for communication within each half of the chip con·
tains 16 conductors that carry the TRUE and COM·
PLEMENT of 8 local macrocells. In the block dia·
gram (Figure 2) of the 5C121 the local macrocells
are B·1 and B·2 on one half and A·1 and A·2 on the
other half.

The output·enable control may be used to generate
architecture types that include bi·directional, 3·state,
open drain, or input only structures.

The global busses (Input bus & Global feedback
from A·3 & B·3 macrocells & buried registers) are
made up of 48 conductors that span the entire chip.
These 48 conductors carry the TRUE and COMPLE·
MENT of the twelve primary inputs (pins 2 through 7
and 33 through 38), signals from 4 Buried Registers
as well as the global outputs of 8 macrocells in
groups A·3 and B·3.

INTERNAL BUS STRUCTURE
The two identical halves of the 5C121 communicate
via a series of busses. The local bus structure used

2·61

intJ

50121

A-I MACROCELLS

20

v..

,

o---

290098-3

Figure 2. 5C121 Block Diagram

2-62

5C121

B-2 MACROCELLS

B-3 MACROCELLS
290098-4

Figure 2. 5C121 Block Diagram (Continued)

2·63

5C121

LOCAL
BUS

GLOBAL
BUS

INPUT
BUS

In this illustration a small group of 4 product·terms is
shared by groups containing 8 product·terms each.
This feature is most useful in counier applications
where common terms exist in the functions.

DETAILED CIRCUIT
REPRESENTATION

-0-

= 64 INPUT AND GATE
(ONE PRODUCT TERM)
290098-5

Figure 3. Shared Product-Term Circuits

2-64

inter

5C121

is adjacent to their macrocell (see Figure 4) so that
they may produce a logical AND of any of the variables (or their complements) that are present on the
busses.

SHARED PRODUCT TERMS
Macrocells 9 & 10,11 & 12, 17 & 18 and 19 & 20 (in
groups A-3 and B-3-the macrocelis with global
feedback) have the facility to share a total of 16 additional product terms. This sharing takes place between pairs of adjacent macrocells. This capability
enables, for example, macrocelis 9 and 10 to expand to 16 and 8 effective product terms respectively, and for macrocells 11 and 12 both to expand to
12 effective product terms. Figure 3 shows this sharing technique in detail. This facility is primarily of use
in state machine and counter applications where
common product terms are frequently required
among output functions.

All macrocells have the ability to return data to the
local or the global bus. Feedback data may originate
from the output of the macrocell or from the 1/0 pin.
Feedback to the global bus communicates throughout the part. Macrocells that feedback to the local
bus communicate only to their half of the 5C121.
Connections to and from the signal busses are
made with EPROM switches that provide the reprogrammable logic capability of the circuit.
Macrocells in groups A-3 and B-3 and the buried
registers ali have global bus connections while macrocells in groups A-1, A-2 and B-1, B-2 have only
local bus connections (see Block Diagram, Figure 2).
Advanced features of the Intel Programmable Logic
Development System II will, if desired, automatically
select an appropriate macroceli to meet both the
logic requirements and the connection to an appropriate signal bus to achieve the interconnection to
other macrocells.

MACROCELL-BUS INTERFACE
As discussed earlier, the macrocells within the
5C121 are interconnected to other macrocells and
inputs to the device via three internal data busses.
The product terms span the entire bus structure (local feedback, global feedback and input buses) that

At each intersectmg point in the logic array there eXists an
EPROM-type programmable connection. Initially, all connections
are complete. This means that both the true and complement of all
inputs are connected to each product-term. Connections are
opened during the programming process. Therefore any product
term can be connected to the true or complement of any input.
When both the true and complement connections of any input are
left mtact, a logical false results on the output of the AND gate. If
both the true and complement connections of any input ate programmed open. then a logical "don't care" results for that input. If
all inputs for a product term are programmed open. then a logical
true results on the output of the AND gate.

EPROM
CELL
CONNECTION

®
II

64 INPUT AND GATE

~

EPROM CELL
ARCHITECTURE
SWITCH

FEEDBACK
SIGNALS

LOCAL
BUS

GLOBAL
BUS

INPUT
BUS

290098-6

Figure 4. Macrocell-Bus Interface
2-65

inter

5C121

CLOCK MODE CONTROL

PROGRAMMING CHARACTERISTICS

The 5C121 contains two internal clock data paths
that drive the input latches (transparent 7475 type)
and the output registers. These clocks may be programmed into one of 8 operating modes (see clock
mode Table 1). Figure 1 shows a typical macrocell
which is driven by the master clock Signal ClK and
the input latch-enable signal IlE.

Initially, and after erasure, all the EPROM control
bits of the 5C121 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cell into
their "0" state. Programming voltage and waveform
specifications are available by request from Intel to
support programming of the 5C121.

The master clock signal is input via pin 1. If programmed modes 4, 5, 6 & 7 are chosen, a second
clock signal is required which is input via pin 38 (see
Figure 5). Table 1 shows the operation of each clock
programming mode.

inteligent Programming™ Algorithm
The 5C121 supports the inteligent Programming Algorithm which rapidly programs Intel H-ElPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each bit is continually monitored to determine when the bit has
been successfully programmed.

If modes 0, 1, 4, 5, 6 or 7 are chosen (i.e. latching of
the inputs is required), all inputs, both dedicated and
110, are latched with the same IlE signal. Data applied to the inputs when ClK1 is low (high) is latched
when ClK1 goes high (low) and will stay latched as
long as ClK1 stays high (low). levels shown in parenthesis are for modes 1, 5 & 7 and levels shown
outside parenthesis are for modes 0, 4 & 6.

FUNCTIONAL TESTING

Care is required when using any of the clock modes
4, 5, 6 or 7, that require two input clock signals to
ensure that timing hazards are not created.

Since the logical oPeration of the 5C121 is controlled by EPROM elements, the device is completely factory tested. Each programmable EPROM bit
controlling the internal logic including the buried
state registers are tested uSing application-independent test program patterns. After testing, the devices are erased before shipment to customers. No
post-programming tests of the EPROM array are
necessary.

ERASURE CHARACTERISTICS
Erasure characteristics of the 5C121 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room
level fluorescent lighting could erase the typical
5C121 in approximately three years, while it would
take approximately one week to cause erasure when
exposed to direct sunlight. If the 5C121 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels
should be placed over the window to prevent unintentional erasure.

DESIGN RECOMMENDATIONS
For proper operation it is recommended that input
and output pins be constrained to the range GND <
(VIN or VOUT) < Vee. Unused inputs should be tied
to an appropriate logic level (e.g. either Vee or GND)
to minimize device power consumption.
When utilizing a macrocell with an 1/0 pin connectiqn as a buried macrocell (i.e. just using the macrocell for feedback purposes to other macrocells), its
110 pin is a 'reserved pin'. (The Intel Programmable
logic Development System" will label the pin 'RESERVED' in the utilization report that it generates.)
Such an 110 pin will actually be an output pin and
should not be grounded. It should be left unconnected such that it can go high or low depending on the
state of the macroc.el/'s output.

The recommended erasure procedure for the 5C121
is exposure to shortwave ultraviolet light which has
the wavelength of 2537 A. The integrated dose (I.e.,
UV intensity X exposure time) for erasure should be
a minimum of fifteen (15) Wsec/cm 2 . The erasure
time with this dosage is approximately 15 to 20 min"
utes using an ultraviolet lamp with a 12,000 JLW/cm 2
power rating. The 5C121 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the 5C121 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week @
12,000 JLW/cm 2 ). Exposure to high intensity UV light
for longer periods may cause permanent damage.

In normal operation VeelVpp (pin 40) should be
connected directly to Vee (pin 39).

2-66

5C121

Table 1. Clock Programming (Key: L = Latched; T = Transparent)
Programmed
Mode

Input Signals
Are Latched When:

Output Registers
Change State When:

0

CLK1
(Pin 1)

~

L
T

CLK1
(Pin 1)

1

CLK1
(Pin 1)

~

T
L

CLK1
(Pin 1)

2

Inputs Not Latched

CLK1
(Pin 1)

3

Inputs Not Latched

CLK1
(Pin 1)

4

CLK1
(Pin 1)

~

L
T

CLK2
(Pin 38)

5

CLK1
(Pin 1)

~

T
L

CLK2
(Pin 38)

6

CLK1
(Pin 1)

~

L
T

CLK2
(Pin 38)

7

CLK1
(Pin 1)

~

T
L

CLK2
(Pin 38)

~

.f
~

.f
~
~

.f
.f

Clock
Configuration

1 Clock
1 Clock
1 Clock
1 Clock
2 Clocks
2 Clock
2 Clocks
2 Clocks

Figure 6 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 10 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

As with all CMOS devices, ESO handling procedures
should be used with the 5C121 to prevent damage
to the device during programming, assembly, and
test.

DESIGN SECURITY
A single EPROM bit provides a programmable design secruity feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be cop·
ied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

LATCH-UP IMMUNITY
All of the input, 1/0, and clock pins of the 5C121
have been designed to resist latch·up which is inherent in inferior CMOS structures. The 5C121 is designed with Intel's proprietary CHMOS II-E EPROM
process. Thus, each of the 5C121 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore,
the programming pin is designed to resist latch-up to
the 13.5V maximum device limit.

AUTOMATIC STAND-BY MODE
The 5C121 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed (TURBO = ON), the device is optimized for maximum
speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

2-67

5C121

CLOCK SIGNALS TO
'A' HALF OF CIRCUIT

=
=

ClK REGISTER CLOCK
IlE INPUT lATCH ENABLE

IlE
ClK

t-------.

ClK
IlE
"CLOCK CONTROL
lOGIC"

ClK
(PIN 1)

13

14
15
OPTIONAL SECOND /
CLOCK INPUT

r;;
'(~IN

ClK2
38)

290098-7

Figure 5. Programmable Clock Control System

FIRST
INPUT

lAST
INPUT

)j(

'.1 '-----------\
r---------~

OUTPUT

CURRENT

VALID OUTPUT

VALID OUTPUT

ACTIVE MODE

ACTIVE MODE

Icc

Icc

OmA
290098-21

Figure 6. 5C121 Standby Mode and Active Mode Transitions

2-68

inter

5C121

(3) 512K Memory (640K recommended)

Intel Programmable Logic
Development System II (iPLDS II)

(4) Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS II).

iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. It contains comprehensive third generation software that
supports four different design entry methods, minimizes logic, does automatic pin assignments and
produces the best design fit for the selected EPLD.
It is user friendly with guided menus, on-line Help
messages and soft key inputs.

Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet (Order Number: 280168).
·IIBM Personal Computer is a registered trademark of International Business Machine Corporation
HMS-DOS is a registered trademark of Microsoft Corporation.

In addition, the iPLDS II contains programmer hardware in the form of an expansion card for the PC
with programming software to enable the user to
program EPLDs, read and verify programmed devices and also to graphically edit programming files.
The software generates industry standard JEDEC
object code output files which can be downloaded to
other programmers as well.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
INP
LlNP
CONF
CORF
COIF
COLF

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMA II-PLD, a low-cost
schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design entry formats supported are Boolean equation
entry and State Machine design entry.

RONF
RORF
ROlF
ROLF
NOCF
NORF

ORDERING INFORMATION
tpD teo fMAX
(ns) (ns) (MHz)

The iPLDS II runs on the IBMt PC, PC/XT or PC/AT
and other compatible machines with the following
configuration:
(1) At least one floppy disk drive and hard disk drive
(2) MS-DOStt Operating System Version 2.0 or later release

2-69

Order
Code

Package

Operating
Range

55

32

25

D5C121-55 CERDIP

Commercial

65

33

20

D5C121-65 CERDIP

Commercial

90

38

16

D5C121-90 CERDIP

Commercial

5C121

*Notice: Stresses above those listed under ':.4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Min

Max

Unit

Vee

Supply Voltage(1)

Parameter

-2.0

7.0

V

Vpp

Programming
Supply Voltage(1)

-2.0

13.5

V

VI

DC Input Voltage(1)(2)

-0.5 Vee+ 0.5

lec

DC Vee Current(4)

Tstg

Storage Temperature

Tamb

Ambient Temperature(3)

V

100

mA

-65

+150

·C

-10

+85

·C

NOTES:

1. Voltages with respect to ground.
2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to -2.0V or overshoot to 7.0V for
periods less than 20 ns under no load conditions.
3. Under bias.
I
4. With outputs tristated.

RECOMMENDED OPERATING
CONDITIONS
Symbol

Parameter

Min

Max

Units

4.75

5.25

V

Input Voltage

0

Vee

V

Va

Output Voltage

0

Vee

V

0

70

·C

Vee

Supply Voltage

VI

TA

Operating Temperature

tR

Input Rise Time

500

ns

tF

Input Fall Time

500

ns

D.C. CHARACTERISTICS TA =
Symbol
VIH

0° to 70°C, VCC

=

5.0V

HIGH Level Input Voltage

VIL

LOW Level Input Voltage

VOH

HIGH Level
Output Voltage

10 = -4.0 mA DC

VOL

LOW Level
Output Voltage

10 = 4.0 mA DC

II

Input Leakage Current

VI = Vee or GND

loz

3-State Output
Off-State Current

Vo

lOS

Output Short Circuit Current

ISB

Vee Supply Current (Standby)
(Note 6)

VI

Vee Supply Current (Active)

No Load
f=10MHz

lec

± 5%

Conditions

Parameter

=

Vec or GND

Vec or GND
10 = 0

Unit

2.0

Vce+ 0.3

V

-0.3

0.8

V

Typ

2.4

V
0.45

V

±10.0

,..,A

±10.0

,..,A

130

mA

CMOS Inputs

3

mA

TTL Inputs

30

CMOS Inputs

50

TTL Inputs

100

(Note 5)

=

Max

Min

mA

NOTES:

5. Output shorted for no more than 1 sec. and no more than one output shorted at a time.' los is sampled but not 100%
tested.
6. Chip automatically goes into standby mode if logic transitions do not occur. (Approximately 100 ns after last transition.)
2-70

intJ

5C121

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

3'°-V20

o--A=o~

INPUT

290098-9
A.C. Testing. Inputs are Driven at 3.OV for a Logic "I" and OV for
a Logic "0" Timing Measurements are made at 2.0V for a Logic
"I" and 0.8V for a Logic "0" on Inputs Outputs are measured at
a I.SV pOint. Device Input rise and fall times < 6 ns

290098-8

A.C. CHARACTERISTICS TA = O· to 70·C, VCC =
Parameter

vro
~

1~--TESTPOINTS-~

OUTPUT

Symbol

>TEST POINTS<

5.0V

Device
Conditions

± 5%
SC121-SS
EP1210-1

SC121-6S
EP1210-2

Min

Min

Max

Max

SC121-90
EP1210
Min

Unit

Max

55

65

90

ns

50

65

90

ns

50

65

90

ns

tpD

Non-Registered Input or 1/0
Input to Non-Registered Output

tpzx(7)

Non-Registered Input or 1/0
Input to Output Enable

tpxz(7)

Non-Registered Input or 1/0
Input to Output Disable

tsu

Non-Registered Input or 1/0
Input to Output Register Setup

40

47

62

ns

tH

Non-Registered Input or 1/0
Input to Output Register Hold

0

0

0

ns

20

25

30

ns

20

25

30

tCH

Clock High Time

teL

Clock Low Time

teo

Clock to Output Delay

teNT

Minimum Clock Period (Register Output Feedback to Register Input-Internal Path)

CL = 30pF

CL = 30pF

33

32
50

55

ns
38

75

ns
ns

tCNT

Maximum Frequency (1/teNT)

20.0

18.0

13.0

MHz

fMAX

Maximum Frequency (1/tsu)-Pipehned

25.0

21.2

16.1

MHz

tRST

Asynchronous Reset Time

50

65

90

ns

tlLS

Set Up Time for Latching Inputs

tlLH
tC1C2
tlLDFS

Input Latch to D-FF Setup Time

40

50

65

ns

tDFILS

D-FF to Input Latch Setup Time

25

30

35

ns

tp3

Minimum Penod for a
2-Clock System (TCl C2

72

83

103

ns

f3

0

0

Hold Time for Latching Inputs

15

20

25

ns

Minimum qlock 1 to Clock 2 Delay

40

50

65

ns

Mode 0, 1

0

ns

+ teo 1)
13.8

Maximum Frequency (1/tp3)

12.0

9.7

MHz

NOTE:
7. tpzx and tpxz are measured at ±0.5V from steady state voltage as dnven by spec. output load. tpxz is measured with
CL = 5 pF.

2-71

inter

5C121

SWITCHING WAVEFORMS
INPUT OR

I/o

INPUT

X

COMBINATIONAL OUTPUT

INPUT MAY CHANGE

-tpxz~

HIGH IMPEDANCE
3-STATE

COMBINATIONAL
OR REGISTERED OUTPUT

-lpzx-J
HIGH IMPEDANCE
3-STATE

ASYNCHRONOUSLY
RESET OUTPUT

VALID OUTPUT

290098-11

290098-10

NOTE:
Above waveforms shown for clock modes 2 or 3 (tsu & tH are as in modes 2 & 3; no ILE Signal is used).

CLOCK MODES
SWITCHING WAVEFORMS
1·CLOCK SYSTEM: MODES 0 AND 1

ClKl (PIN 1)
t'LS
INPUTS OR
r'l--"""'\. , - - - I/O INPUTS _fl"+_..J11'-_ _ _f-..J ,-+-_ _" ,,_ _ __

-,I •.-+---..Ir---.-+-""

--.-+--------,,1.,-+------.-+________.11''"+_ _ _ _ _ __

REGISTERED
OUTPUT _ _

COMBINATIONAL _ _

_+---------"1""-+-------

--....!::'':::==:..:~

COMBINATIONAL
OR REGISTERED _ _ _ _ _ _ _ _ _ _ _.Jr-------~
OUTPUT

290098-12

INVERT eLKl FOR MODE 0

1·CLOCK SYSTEM: MODES 2 AND 3

ClKl (PIN!) \

r tcLl~
v--\I..._____

_I:-tsu
---->K t~f. .-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_
teo,/:
REG~J~~5~ -------....;.;.,x
. .-_-_-_-_-_-_-_-_-_-_-_:I~ty~u~

t
~_+-t:-:D~~f '".1:
~

I/O INPUTS _ _ _ _ _--'
INPUTS OR

COM8IN~~~~~~

______

.....

COMBINATIONAL - - - - - - -......
OR REGISTERED
OUTPUT

INVERT eLKl FOR MODE 2

2·72

290098-13

5C121

CLOCK MODES
SWITCHING WAVEFORMS (Continued)
2-CLOCK SYSTEMS: MODES 4 THROUGH 7
ClKl PIN 1 CONTROLS THE INPUT LATCH CLOCK
ClK2 PIN 38 CONTROLS THE D-FF CLOCK.

I+--tC1C2 --+
ClK2 (PIN 38)
tco --.
REGISTERED
OUTPUT
t PD

COMBINATIONAL
OUTPUT

f

..=:1.
X
~tpzx

~

-tpxz
COMBINATIONAL
OR REGISTERED
OUTPUT - - - - - - - - ....

290098-14

INVERT ClKl FOR MODES 5 & 7
INVERT CLK2 FOR MODES 4 & 5

100

200
180
160

./

140

<-

5

u
..9

/"

~

-a
c

/

120

t

/

100
./;
~/

80
60

"
.eo"
~

I

40

I

20

o

o

10

15

20

25

30

f

10

IIOl

-- -

r-.....

5

IOH

~

2

o

35

O'C, Vee

~

2

3

4

5

Vo Output Voltage (V)

290098-20

290098-22
~

20

1
5

fo (MHz)

Conditions: T A

50

-5.

5.25V

5C121 Current in Relation to Frequency

Output Drive Current in Relation to Voltage

2-73

5C180
1800-GATE CHMOS
ERASABLE PROGRAMMABLE LOGIC DEVICE

•

High Performance LSI Semicustom
Logic.Replacement for TTL and 74HC
SSI and MSI Logic

EPROM Technology-Based UV
• CHMOS
Erasable
48 Macrocells with Programmable I/O
• Architecture;
up to 64 Inputs (16
Dedicated, 48 I/O) or 48 Outputs

•

•
•

High Speed tpD (max) 70 ns, Operating
Frequency (max) 20.8 MHz (Pipelined),
16.1 MHz (w/Feedback)
Low Power; 100 p,W Typical Standby
Dissipation
Programmable "Security Bit" Allows
Total Protection of Proprietary Designs

•

Dual Feedback Signals Allowing I/O
Pins to Be Used for Buried Logic and
Dedicated Input

•

Programmable Clock System with Four
Synchronous Clocks as well as
Asynchronous Clocking Option on All
Registers

•

Programmable Registers. Can Be
Configured as D, T, SR or JK Types
with Individual, Reset Controls

•
•
•

Register Pre-Load and Erasable Array
for 100% Generic Testability
100% Compatible with EP1800
68-Pin J-Lead Chip Carrier and Pin Grid
Array Packages
(See packaging spec., Order # 231369)

The Intel 5C180 EPLD (Erasable Programmable Logic Device) is a CHMOS LSI Logic Device capable of
integrating 1800 to over 2000 equivalent gates of SSI/MSI logic. This user customizable Logic Device is
available in a 68-pin J-Leaded chip carrier or Pin Grid Array package and has the benefits of low power and
increased flexibility.
The 5C180 EPLD uses CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. Use of
Intel's advanced CHMOS II-E EPROM process technology enables greater logic densities to be achieved with
superior speed and power performance. The EPROM technology also enables these devices to be 100%
.factory tested by the programming and the erasure of all the EPROM logic control elements in the device.

000000000
00000000000
J 00
00
H 00
00
G 00
SC1BO
00
F 00
(BOTTOM VIEW)
00
E 00
00
0 00
00
C 00
00
B 00000000000
000000000
L

I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O GNO
I/O I/O
INPUT

I/O I/O

INPUT

I/O I/O
I/o I/O

K

1

2

o

3

000 0 0 0 0 0 a 0 0 0 0 000
~~~~~~~~~~~~~~~~~

5

0

7

8

I/O I/O
I/O I/o
GND I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/o

9 10 11

~ ~

>

~ ~ a

o

~

I-

I-

I-

z

z

z

z

0

~~

~ ~

290111-1

6

I/O I/O

~~~~~~~

~~

8

4

I/O I/O

~ ~ ~

-~~-

Figure 1. Pin Configuration

dd

290111-35

Figure 2. PGA Pin Configuration

2-74

November 1988
Order Number: 290111-005

inter

5C180

within the AND array. All 48 internal registers may be
individually programmed for synchronous or asynchronous clocking. Asynchronous clocking is possible via a Macrocell product term. Clock inputs not
used for synchronous clock signals may be used as
global bus inputs.

The architecture of the 5C180 is based on the "Sum
of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a
fixed OR array. The 48 macrocells of the 5C180 can
be partitioned into 4 identical quandrants each containing 12 macrocells. This device makes use of a
segmented PLA structure with local and global bus
structures to provide for increased performance and
greater device utilization. The 5C180 has unique architectural features that allow programming of all 48
registers to D, T, SR or JK configurations without
sacrificing product terms. These registers can be either clocked asynchronously or in banks with four
synchronous clocks. In addition, the 16 global macrocells have two independent feedback paths to the
array that allow for buried logic implementation together with use of the I/O pin for input functions.

Invert Select EPROM Bit
The Invert Select EPROM bit is used to invert the
product term input into the register. This applies to
all inputs including double inputs on JK and SR registers. The invert option allows the highest possible
logic utilization by use of de Morgan logic inversion.
At each intersecting point in the logic array there
exists an EPROM-type programmable connection.
Initially, all connections are complete. This means
that .both the true and complement of all inputs are
connected to each product term. Connections are
opened during the programming process. Therefore
any product term can be connected to the true or
complement of any input. When both the true and
complement connections of any input are left intact,
a logical false results on the output of the AND gate.
If both the true and complement connections of any
input are programmed open, then a logical "don't
care" results for that input. If all inputs for a product
term are programmed open, then a logical true results on the output of the AND gate.

ARCHITECTURE DESCRIPTION
Externally, the 5C180 provides 12 dedicated data inputs, 4 synchronous clock inputs, and 48 I/O pins
which may be individually programmed for input, output, or bi-directional operation.
The Block Diagram is shown in Figure 2 with pin
numbers for the JLCC package. Figure 3 shows the
device block diagram with pin numbers for the PGA
package. The internal architecture is organized in familiar sum-of-products (AND-OR) structure. The
5C180 houses a total of 480 product terms distributed among 48 Macrocells. The basic Macrocell structure is shown in Figure 4. Input and feedback signals
are selectively connected to product terms via
EPROM cells. The output of the AND array feeds a
fixed OR gate to produce sum-of-products logic. The
final output may be combinatorial or registered, programmed active high or low. Combinatorial, registered, or pin feedback is also user-defined.

BUS STRUCTURE
Input and feedback signals are connected to each
5C180 Macrocell via a Local and Global Bus. Figure
5 shows the Macrocell-Bus interface for Quadrant D.
The Global Bus contains 64 input signals while the
Local Bus has 24.
Within the 5C180 Macrocell, the product-terms
share the entire bus structure. Therefore, a logical
AND of any of the variables (or their complements)
that is present on the buses may be produced by
each product term.

The 5C180 is partitioned into 4 identical quadrants.
Each quadrant contains 12 Macrocells. Input signals
to the Macrocells come from the 5C180 Local and
Global bus structures. These two buses comprise an
88-input AND array for each quadrant. The output of
each Macrocell feeds an I/O Architecture Control
Block which contains output and feedback selection.

All quadrants share the same Global Bus. Inputs to
the bus come from the true and complement signals
of the 12 dedicated data inputs, 4 clock inputs, and
the 16 Global Macrocell pin feedback signals.

Four dedicated clock inputs provide synchronous
clock signals to the 5C180 internal registers. There
is one synchronous clock per quadrant. Therefore
each clock signal controls a bank of 12 registers.
CLK1 may be connected to registers in Macrocells
1-12, CLK2 with Macrocells 13-24, CLK3 with Macrocells 25-36, and CLK4 with Macrocells 37-48.
With synchronous clocks, the flip-flops are positive
edge triggered. Both true and complement signals
for each dedicated clock input may also be used

Each quadrant has its own Local Bus. Inputs to this
bus come from the 12 quadrant Macrocells. For the
eight Local Macrocells, the signals can be either
from the Macrocell internal logic or from the pin. For
the four Global Macrocells, the signals come from
the Macrocell internal logic only.

2-75

5C180

QUADRANT A

QUADRANT D

QUADRANT B

QUADRANT C
GENERAL MACFlOCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS

Figure 2. 5C180 Block Diagram-JLCC Package

2-76

290111-2

intJ

5C180

QUADRANT D

QUADRANT C

QUADRANT B

290111-36

GENERAL MACROCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS
~--------------------------~~------

Figure 3. 5C180 Block Diagram-PGA Package

2-77

inter

5C180

Table 1 summarizes the Macrocell interconnect.

Table 1. Macrocell Interconnect
Pin
#
2-9

Quad
A

10~13

Quad 23-26
8

Macro- Feedback Feedback
Structure Interconnect
1-8
Local
Quad A
9-12
Quad A
Local

··~ell#

13-16

27-34 17-24

Global

All

Local .
Global
Local '

Quad 8
All
Quad 8

Quad 36-43 25-32
44-47 33-36
C

Local
Local
, Global

QuadC
QuadC
All

Quad 57-60 37-40
0

Local
Global
Local

Quad 0
All
Quad 0

61-68 41-48

AND ARRAY

SYNCHRONOUS

CLOCK

vcc

OE/ClK

l~ElECT

OE
OE/ClK

0

f--

K

t--

ClK

' - - f--

EPROM
CEU

PRODUCT
TERW

coNNECTION

II

j

D-

®

&lib

\

s:~~

~

lOGIC

INVERT

=

{YrF1D,=~
~,
~~
~

I/O

SELECTION

RESET

~

~

~

~

~

,~

~

~

L.z1.

FEEDBACK SIGNALS

INPUTS AND I/o

290111-3

Figure 4. Basic Macrocell Architecture of the 5C180

2-78

intJ

5C180

GLOBAL BUS
(64 INPUT)

LOCAL BUS
(24 INPUT)

QUADRANT D

MACROCELL 48

MACROCELL 47

MACROCELL 46

MACROCELL 45

MACROCELL 44

MACROCELL 43

MACRO CELL 42

MACROCELL 41

MACROCELL 40

MACROCELL 39

MACROCELL 38

MACROCELL 37

GLOBAL BUS TO
OTHER QUADRANTS
290111-4

Figure 5. Quadrant "0" Bus Interface

2·79

5C180

rocells within the same quadrant. There are a total of
32, Local Macro~!ls within the 5C180, with eight pe~
quadrant.

5C180 MACROCELLS
Within each 5C180 quadrant there are two different
types of Macrocells; Local Macrocells, Figure 6, and·
Global Macrocells, Figure 7. Both types share an 88input AND array and contain a total of ten product
terms. Eight product terms are dedicated for logic
implementation. One product term is reserved for
Asynchronous Clear to the Macrocell register. The
remaining product term is used for Output Enable!
Asynchronous Clock implementation. Each 5C180
product term represents an 88-input AND gate. The
110 Architecture Control Block provides each Macrocell with both combinatorial and registered 110
configurations.

Local macrocells are divided into two groups: General Macrocells and Enchanced Macrocells. The Enhanced Macrocells are architecturally identical to
the General Macrocells but operate at higher
speeds. These speed differences are reflected in
the specification tables.
Global Macrocells contain two independent feedback paths to the AND array. Combinatorial or registered feedback is supplied to the local bus and pin
feedback is supplied to the global bus. The "dual
feedl?ack" capability allows the Macrocell to be
used for internal logic functions as well as a dedicated input pin. To obtain this configuration, the output
buffer must be disabled. If the Global Macrocell 110
pin is not being used as a dedicated input, the Macrocell logic may be fed back along the global bus
allowing routing to any of the 5C180's 48 Macrocells. There are 16 Global Macrocells contained in
the 5C180, four per quadrant.

Local Macrocells provide one feedback path into the
AND array. Combinatorial, registered or pin feedback may be selected from the Feedback Select
Multiplexer. The selected feedback signal is then
routed to the quadrant local bus. Therefore, the Local Macrocell feedback communicates only to Mac-

QUADRANT
SYNCHRONOUS
CLOCK
-GLOBAL BUS--LOCAL BUSOE

OE/CLOCK~F--R=--FF----R=---R=--.....j.:F-1-I

L!::~ij--,
CLK

~ 2~+-~-~--~-~~-++-~

IIIu

3~r-H-~----+r~~~+-~~~

5

4~+-~-~--~-~-~+-~

~ 5~+-~-~--~-~-~~~

I/O
ARCHITECTURE
CONTROL

6~~~~+---~~~~~~
7~+-~-~--~-~~~~~

FEEDBACK
SELECT
LOCAL BUS

~ ~'--------

GLOBAL
DEDICATED
INPUTS
(16 INPUTS)

QUADRANT
QUADRANT
A,B,C,D
LOCAL
GLOBAL
FEEDBACK
FEEDBACK
(12 MACROCELLS)
(16 MACROCELLS)

290111-5

Figure 6. Local Macrocell Logic Array

2-80

inter

5C180

QUADRANT
SYNCHRONOUS
CLOCK
--GLOBAL BUS----LOCAL BUS ___

CLOCK
SELECT

OE
SELECT
OE

OE/ CLOCKI-+r-.....,F--FF;.....-~FF---FF--FF-I-I

'"~

21-+t--H~~--~H--~--H~-i

'"~

31-+t--H~~---iH--~--H~-i

~ 41-+t--H~~---iH--~--H~-i
~ 51-+t--H~~---iH--~--H~-i

I/O
ARCHITECTURE
CONTROL

61-+~-H~4+---iH--~-~~-i
71-+t--H~~---iH--~--H~-i

RESET H+--+I--H--~H--++--+I--I

LOCAL BUS
GLOBAL BUS
~

GLOBAL
DEDICATED
INPUTS
(16 INPUTS)

~------~

QUADRANT
QUADRANT
A,B,C,D
LOCAL
GLOBAL
FEEDBACK
FEEDBACK
(12 MACROCELLS)
(1 6 MACROCELLS)

290111-6
Figure 7. Global Macrocell Logic Array

product term derived in the AND array. When this
dedicated product term is a logical one, the Macrocell register is immediately cleared to a logical zero
independent of the register clock. The RESET function occurs automatically on power-up.

MACROCELL LOGIC
CONFIGURATIONS
Combinatorial Selection

The four different register types shown in Figures
8b-8e are described below:

In the Combinatorial configuration, eight product
terms are ORed together to generate the output signal. The Invert Select EPROM bit controls output
polarity and the Output Enable buffer is product-term
controlled. The Feedback Select allows the user to
choose combinatorial, 1/0 (pin) or no feedback to
the respective local and global buses.

D- or T-type Flip-Flops
When either a -D- or T-type Flip-Flop is configured
as part of the 1/0 structure, all eight of the product terms into the Macrocell are ORed together
and fed into the register input.

REGISTER SELECTION

JK or SR Registers

The advanced 1/0 architecture of the 5C180 allows
four different register types along with combinatorial
output as illustrated in Figures 8a-8e. The register
types include a T, D, JK, or SR Flip-Flop and each
Macrocell 1/0 structure may be independently configured. In addition, all registers have an individual
asynchronous RESET control from a dedicated

When either a JK or SR register is configured,
the eight product terms are shared among two
OR gates (one for the J or S input and the other
for the K or R input). The allocation for these
product terms for each of the register inputs is
optimized by the iPLDS II development software.
2-81

inter

5C180

Buried Logic Selection
For Global Macrocells, if no output is selected, the
logic may be "buried" and the 110 pin can be used
as an additional dedicated input. The use of "dual
feedback" is accomplished by tri-stating the Output
Enable Buffer. Thus, up to 16 additional dedicated
inputs may be added without sacrificing the Macrocell internal logic.
In the erased state, the 1/0 architecture is configured for combinatorial active low output with 1/0
(pin) feedback.

Q

RESET

RESET
290111-9

Figure 8e. Toggle Flip-Flop Register
Configuration

D-

ClK
N

290111-7
Q

Figure 8a. Combinatorial 1/0 Configuration
8-N
K RESET

INVERT
SELECT

290111-10

Figure 8d. JK Flip-Flop Register Configuration

Q

RESET

RESET
290111-8

Figure 8b. 0-Type Flip-Flop Register
Configuration

2-82

intJ

5C180

The operation of each multiplexer is controlled by
EPROM bits and may be individually configured for
each 5C180 Macrocell.

ClK
N

In Mode 0, the three-state output buffer is controlled
by a single product term. If the output of the AND
gate is a logical true then the output buffer is enabled. If a logical false resides on the output of the
AND gate then the output buffer is seen as high impedance. In this mode the Macrocell flip-flop may be
clocked by its quadrant synchronous clock input. In
the erased state, the 5C180 is configured as Mode

S

Q

8-N
R RESET

o.

In Mode 1, the Output Buffer is always enabled. The
Macrocell flip-flop now may be triggered from an
asynchronous clock Signal generated by the Macrocell product term. This mode allows individual clocking of flip-flops from any available signal in the quadrant AND array. Because both true and complement
signals reside in the AND array, the flip-flops may be
configured for positive or negative edge triggered
operation. With the clock now controlled by a product term, gate clock structures are also possible.

INVERT
SELECT

290111-11

Figure 8e. SR Flip-Flop Register Configuration

MACROCELL OE/CLK SELECT

In Modes 2 and 3, the Output Buffer is always disabled. The Macrocell flip-flop may still be triggered
from clock signals generated from the Macrocell
product term or asynchronous clocks. This mode is
only possible for Global Macrocells.

Each 5C180 register may be clocked synchronously
or asynchronously. Figure 9a and 9b shows the
modes of operation provided by the OE/ClK Select
Multiplexers for both local and Global Macrocells.

2-83

intJ

5C180

SYNCHRONOUS
CLOCK
VCC

OE
OE/CLK

CLK - SYNCHRONOUS
CLK

OE - P-TERM CONTROLLED

MACROCELL
REGISTER
OUTPUT
BUffER

290111-12
The register IS clocked by the quadrant synchronous clock Signal which IS common to 11 other Macrocells The output IS enabled by the
logiC from the product term.
.
,

SYNCHRONOUS
CLOCK
VCC

OE
OE/CLK

CLK - ASYNCHRONOUS
CLK

OE- ENABLED

IotACROCELL
REGISTER
OUTPUT
BUFFER

•

290111-13

The output IS permanently enabled and the register IS clocked via the product term. ThiS allows for gated cloCks that may be generated
from elsewhere In the 5C180

Figure 9a. Local Macrocell OE/CLK Selection

2-84

intJ

5C180

SYNCHRONOUS
CLOCK

OE
OE/ClK

ClK - SYNCHRONOUS
ClK

OE- DISABLED

NACROCEll
REGISTER

290111-14
The output IS permanently disabled and the register clocked by the quadrant synchronous clock signal. The pin can be used as an Input
while the register or combinational output can be fed back.

SYNCHRONOUS
CLOCK

OE
OE/ClK

ClK - ASYNCHRONOUS
ClK

OE - DISABLED

NACROCEll
REGISTER

290111-15
The output IS permanently disabled and the register is clocked via the product term. This allows gated clocks that may be generated
elsewhere In the 5e180. The pin can be used as In Input while the register or combinational oulput can be fed back.

Figure 9b. Global Macrocell Additional OE/CLK Selection

2-85

inter

5C180

MACROCELL LOGIC
CONFIGURATIONS

+

Figures 10 and 11 show the 5C180 basic I/O configurations for both the Local and Global Macrocells.
Along with combinatorial, four register types are
available. Each' Macrocell may be independently
programmed.

1/0

The 5C180 Input/Output Architecture provides each
Macrocell with over 50 possible I/O configurations.

FEEDBACK
. SELECT
290111-16

COMBINATORIAL

I/O Selection

Output/Polarity

Feedback

Bus

Combinatorial/High
Combinatorial/Low
None
None

Comb, Pin, None
Comb, Pin, None
Comb
Pin

Local
Local
Local
Local

Figure 10_ Local Macrocelii/O Configurations

2-86

intJ

5C180

SYNCHRONOUS
CLOCK

OE/CLOCK
SELECT
OE

CLK

0

0
(f)

(f)

:::>
m

:::>
m

~

~

«
m

(.)

~

0

«

0

C

~

(!)

290111-17

0-TYPE FLIP-FLOP
I/O Selection
Output/Polarity

Feedback

Bus

D-Reglster/High
D-Register/Low
None
None

D-Register, Pin, None
D-Register, Pin, None
D-Register
Pin

Local
Local
Local
Local

Function Table

0
0
0
1
1

Qn

Qn +1

0
1
0
1

0
0
1
1
Figure 10. Local Macrocelii/O Configurations (Continued)

2-87

inter

5C180

SYNCHRONOUS
CLOCK

OE/CLOCK
SELECT
OE

Q

'"::>

'"::>

ID

ID

..J

«
ID

..J

..J

..J

~

0

C

0

C)

FEEDBACK
SELECT
290111-18

TOGGLE FLIP-FLOP
I/O Selection
Output/Polarity
T-Register/High
T-Register/Low
None
None

Feedback
T-Register, Pin, None
T-Register, Pin, None
T -Register ;
Pin

Bus
Local
Local
Local
Local

Function Table

T
0
0
1
1

Qn

Qn +1

0

0

1

0

1
1

1

0
Figure 10. Local Macrocelii/O Configurations (Continued)

2-88

5C180

SYNCHRONOUS
CLOCK

OE/CLOCK
SELECT
OE

CLK
N

VI

Vl

m

m

...I

...I

=>

=>

~
o

8-N
K

j
o
...I

...I

"

C

INVERT
SELECT

FEEDBACK
SELECT
290111-19

JK FLIP-FLOP
110 Selection
Output/Polarity

Feedback

Bus

JK Register/High
JK Register/Low
None

JK Register, None
JK Register, None
JK Register

Local
Local
Local

Function Table
J

K

Qn

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Qn +1
0
1
0
0
1
1
1
0
Figure 10. Local Macrocelil/O Configurations (Continued)

2-89

inter

5C180

SYNCHRONOUS
CLOCK

OE/ClOCK
SELECT
OE

ClK

en

en

::>

::>

CD
...J

CD
...J

«

C

~

CD

0

0

...J

...J

co

INVERT
SELECT

290111-20

SR FLIP-FLOP
I/O Selection
Output/Polarity

Feedback

Bus

SR Register/High
SR Register/Low
None

SR Register, None
SR Register, None
SR Register

Local
Local
Local

Function Table

S
0
0
0
0
1
1

R
0
0
1
1
0
0

Qn

Qn + 1

0
1
0
1
0
1

0
1
0
0
1
1
Figure 10. Local Macrocelii/O Configurations (Continued)

2-90

inter

5C180

OE

Vl

::>
m
--'
..:
m

o

--'



m

--'
..:
u

9

290111-21

COMBINATORIAL
I/O Selection
Output/Polarity

Feedback

Combinatorial/High Comb, Pin, None
Combinatorial/Low Comb, Pin, None
None
Comb
None
Pin
None
Comb/Pin

Bus
Local, Global
Local, Global
Local, Global
Global
Local/Global

Figure 11. Global Macrocelil/O Configurations

2-91

infef

5C180

SYNCHRONOUS
CLOCK

CLOCK
SELECT

OE
SELECT
OE

VI

VI

III

III

::>

::>

--'

--'

;:;\
o...J

tl

o

--'

<.!)

290111-22

D-TYPE FLIP-FLOP
1/0 Selection

Output/Polarity

Feedback

Bus

D-Register/High
D-Register/Low
None
None
None

D-Register. Pin. None
D-Register. Pin. None
D-Register
Pin
D-Register/Pin

Local; Global
Local. Global
Local. Global
Global
Local/Global

Function Table

0
0
0
1
1

Qn
0
1
0
1

Qn +1
0
0
1
1

Figure 11. Global Macrocelil/O Configurations (Continued)

2-92

intJ

5C180

SYNCHRONOUS
CLOCK

CLOCK
SELECT

OE
SELECT
OE

V>

::>

V>

CD

::>

-'

~
o

-'

-'

"

-'

CD

~
o

290111-23

TOGGLE FLIP-FLOP
I/O Selection
Output/Polarity

Feedback

Bus

T-Register/High
T -Register flow
None
None
None

T-Register, Pin, None
T-Register, Pin, None
T-Register
Pin
T-Register/Pin

local, Global
local, Global
local, Global
Global
local/Global

Function Table

T
0
0
1
1

Qn
0
1
0
1

Qn+1

0
1
1
0
Figure 11. Global MacrocelillO Configurations (Continued)

2-93

infef

5C180

SYNCHRONOUS
CLOCK

CLOCK
SELECT

OE
SELECT

N

Vl

Vl

:;)

m

:;)

...J

...J

m

~

8-N

13o

o

...J

...J

'"

INVERT
SELECT

290111-24

JK FLIP-FLOP
I/O Selection
Feedback
Output/Polarity
Bus
JK Register/High JK Register, None Local, Global
JK Register/Low JK Register, None Local, Global
JK Register
None
Local
None
JK Register/Pin Local/Global
Function Table
J

K

On

0

0
0
1
1
0
0
1
1

0
1
0
1
0

0
0
0
1
1
1
1

1

0
1

On+1
0
1
0
0
1
1
1
0
Figure 11. Global MacrocelillO Configurations (Continued)

2-94

inter

5C180

SYNCHRONOUS
CLOCK

CLOCK
SELECT

OE
SELECT

N

III

III

::>
m

::>
m
-'

~

o

g

C>

-'

-'

8-N

INVERT
SELECT

290111-25

SR FLlp·FLOP
I/O Selection
Feedback

Output/Polarity

Bus

SR Register/High SR Register, None Local, Global
SR Register/Low SR Register, None Local, Global
Local
None
SR Register
None
SR Register/Pin Local/Global
Function Table

S
0
0
0
0
1
1

R
0
0

Qn

Qn +1

0

0

1

1

1
1

0

0
0

0
0

0

1
1

1
1
Figure 11. Global Macrocelii/O Configurations (Continued)

2-95

5C180

wavelengths shorter than approximately 4000A. It
should be noted that sunlight and, certain types of
fluorescent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
room level fluorescent lighting could erase the typical SC180 in approximately three years, while it
would take approximately one week to cause erasure when exposed to direct sunlight. If the SC180 is
to be exposed to these types of lighting conditions
for extended periods of time, conductive opaque labels should be placed over the device window to
prevent unintentional erasure.

AUTOMATIC STAND-BY MODE
The SC180 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed
(TURBO = ON), the device is optimized for maximum speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.
Figure 12 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 30 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than


3'°-V- 20

INPUT

°

DEVICE C:_+-1H::> TO TEST
OUTPUT
SYSTEM
341.ll

OUTPUT

·
TEST POINTS

-< vr:o
Ai!

~~.-------------

l~-TEST F:OINTS-~
290111-27

A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a LogIc
"1" and 0.8V for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. DevIce rise and fall times <6 ns.

290111-28

2-100

5C180

CAPACITANCE
Symbol

Parameter

Min

CIN

Input Capacitance

Typ

Max

Unit

Conditions

15

pF

= OV, f = 1.0 MHz
VOUT = OV, f = 1.0 MHz
VOUT = OV, f = 1.0 MHz
CLK2, VOUT = OV, f = 1.0 MHz

COUT

Output Capacitance

15

pF

CClK

Clock Pin Capacitance

25

pF

Cvpp

Vpp Pin Capacitance

160

pF

A.C. CHARACTERISTICS
Symbol

From

TA

VIN

= O'Cto +70'C, Vcc = 5V ±5%, Turbo BitOn(S)

To

5C180-70
EPi800-2

5Ci80-90
EPi800

5C180-75

Non-Turbo
Mode(11)

Unit

85

+30

ns

Min Typ Max Min Typ Max Min Typ Max
tpD1

Input(12)

Comb. Output

tpD2

1/0(12)

Comb. Output

70

75

90

+30

ns

tPD2e

1/0(13)

Comb. Output

65

70

85

+30

ns

tpZX(10) lor I/O

Output Enable

70

75

90

+30

ns

tpXZ(10) lor I/O

Output Disable

70

75

90

+30

ns

70

75

90

+30

ns

telR

65

Asynch. Reset Q Reset

70

NOTES:
S. Typ. Values are at T A = 2S'C, Vee = SV, Active Mode.
10. tpzx and tpxz are measured at ± O.SV from steady state voltage as driven by spec. output load. tpxz IS measured with

CL = S pF.
.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode), Increase time by amount shown.

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
= O'C to + 70'C, VCC = 5V ± 5%, Turbo Bit On(S)

TA

Symbol

5Ci80-70
EPi800-2

Symbol

5Ci80-90
EPi800

5Ci80-75

Non-Turbo
Mode(11) Unit

Min Typ Max Min Typ Max Min Typ Max
fMAX

Max Frequency
1/(teH + tcu-No Feedback

20.8

19.6

16.1

MHz

fCNT

Max. Count Frequency
1/tCNT-With Feedback

16.1

15.1

12.2

MHz

tSU1

Input Setup Time to Clk(12)

48

51

62

+30

ns

tSU2

I/O Setup Time to Clk(12)

53

56

67

+30

ns

tSU2e

I/O Setup Time to Clk(13)

48

51

62

+30

ns

tH

I or I/O Hold after Clk High

0

teo

Clk High to Output Valid

tCNT

Register Output Feedback
to Register InputInternal Path

62

66

82

tCH

Clk High Time

24

25

30

ns

tel

ClkLowTime

24

25

30

ns

0
29

2-101

0
30

ns
35

ns
+30

ns

5C180

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
TA =

ooe to +70oe, vcc

Symbol

=

5V ±5%, Turbo Bit On(9)
5C180·70
EP1800-2

Parameter

5C180·75

5C180·90
EP1800

Non·Turbo
Mode(11)

Unit

Min Typ Max Min Typ Max Min Typ Max

fAMAX

Max. Frequency
1I (tACH + tAcd-No Feedback

20.8

20

16.6

MHz

fACNT

Max. Frequency
1ItACNT-With Feedback

16.1

15.1

12.2

MHz

tASU1

Input Setup Time to Asynch. Clock(12)

17

19

23

+30

ns

tASU2

I/O Setup Time to Asynch. Clock(12)

22

25

28

+30

ns

tAH

Input or 1/0 Hold to Asynch. Clock

30

tACO

Asynch. Clk to Output Valid

tACNT

Register Output Feedback
to Register InputInternal Path

62

66

82

tAGH

Asynch. Clk High Time

24

25

30

ns

tACL

Asynch. Clk Low Time

24

25

30

ns

30
70

30
75

ns

90

ns

+30

ns

NOTES:
12. For General and Global Macrocells.
13. For Enhanced Macrocells.

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

~.,,~
I--- tpxz - -

COMBINATORIAL OR
REGISTERED OUTPUT

HIGH IMPEDANCE
3-STATE

,

I

r

I
tpzx

.

-

HIGH IMPEDANCE
3- STATE

/';'"

VALID OUTPUT

~.~

..... i'o...

ASYNCHRONOUSLY
CLEAR OUTPUT
290111-29

2-102

inter

5C180

SWITCHING WAVEFORMS (Continued)
SYNCHRONOUS CLOCK MODE

CLK1.CLK2.
CLK3.CLK4

INPUT MAY CHANGE

INPUT MAY CHANGE

1-

teo

(fROM REGISTER
TO OUTPUT)

VALID OUTPUT

290111-30

ASYNCHRONOUS CLOCK MODE

ASYN. - - - - " " \
CLOCK
INPUT

-----'

OTHER
INPUT

INPUT MAY CHANGE

INPUT MAY CHANGE

1(fROM REGISTER
TO OUTPUT)

VALID OUTPUT

290111-31

2-103

inter

5C180

240

./

220

./

200

./

180

A~

160
'00/

140

<-

!

u
..Y

-·. .'~yz
120

7

V V Non-Turbo

100

J

80

I
I

60
40

II

20

o

o

TA

=

O°C, Vee

=

5

10

20

teNT (MHz)

5.25V

290111-32

Current in Relation to Frequency

240

r- -t-J..l

220

feNT= 20MHz

200
180
140

'U

~

-

f- r-- feNT= 10MHz

160

!

r- -l-

I I

I

120

r--

100 80

'j

I I

I

J

I

feNT =1 MHz,Turbo I" 1 1 1

I I I

60

I I I
-c- leNT = 1MHz,Non-Turbo

40
20

r

o

o

20

I I I I I
40

60

8085

TEMP (e)

290111-33

Vee = 5.25V

Current in Relation to Temperature

100

-:;(

50

.5.
1:.,

20

I

l;

:>
0

10

10L

:>

Q.

"5

-

'"1'\
IOH

5

0

:J?

.......

j

2

1

o

2

3

4

5

Vo Output Voltage (V)
290111-34

Output Drive Current in Relation to Voltage

2-104

intJ

5C180

5C180 INTERNAL TIMING
The following internal timing model and specifications are provided to aid in determining the different
timing parameters for all permutations of timing paths through the device. The mnemonics in the table
represent internal parameters only and should not be confused with external timing parameters shown
in previous tables, even though some mnemonics are the same.

-

---

SYSTEM CLOCK DELAY tiCS

INPUT
DELAY

~

CLOCK DELAY tIC(a)

~

REGISTER
tsu
tH

tiN

~

LOGIC ARRAY DELAY
t LAO(.)

OUTPUT
DELAY
teo
txz
tzx

----.

f--a

T

--

I/o

FEEDBACK
DELAY
tro

INPUT
DELAY
t lO

~
290111-38

Symbol

Parameter

tiN

Input Pad and Buffer Delay

tlO

1/0 Input'pad and Buffer Delay

tLADe
tLAD

5C180-70
5C180-90
5C180-75
EP1800-2
EP1800

Non-Turbo
Mode(11)

Min Max Min Max Min Max

Min

10
5

Enhanced Logic Array Delay
. Logic Array Delay

Unit

Max

11

14

0

ns

5

5

0

ns

35

37

43

30

ns

40

42

48

30

ns

tOD

Output Buffer and Pad Delay

15

17

23

0

ns

tzx

Output Buffer Enable

15

17

23

0

ns

txz

Output Buffer Disable

15

17

23

0

ns

tsu

Register Setup Time

12

13

18

0

ns

tHS

Register Hold Time (System Clock)

0

0

0

0

ns

tH

Register Hold Time

30

30

30

0

ns

tlCa

Enhanced Clock Delay

35

37

43

30

ns

tiC

Clock Delay

40

42

48

30

ns

tiCS

System Clock Delay

4

4

4

0

ns

tFD

Feedback Delay

10

11

16

-30

ns

telRe

Enhanced Register Clear Time

35

37

43

30

ns

telR

Register Clear Time

40

42

48

30

ns

2-105

inter

APPLICATION
BRIEF

AB-8

May 1986

Implementing Cascaded
Logic in the 5C121

J. R. DONNELL
APPLICATIONS ENGINEER
PROGRAMMABLE LOGIC'

Order Number: 292003-001
2-106

intJ

AB-8

PROBLEM
Designs that utilize numerous levels of cascaded logic
often result in excessive product terms when expressed
in the sum-of-products form. Although this poses no
problem when designing with discrete logic, EPLDs are
generally optimized for the sum-of-product form. This
stems from the architecture of the basic Macrocell.
Macrocells typically consist of a programmable AND
array feeding a fixed width OR gate. In the 5C121, OR
gate widths range from four to sixteen inputs. For
many applications, sixteen available product terms are
sufficient. However, one example where product terms
become an issue is cascaded exclusive-OR circuits.
Here the number of product terms increase as 2"n
where n equals the number of exclusive-OR gates. If
the number of product terms exceeds sixteen, the equation will not fit directly in the 5C 121.

SOLUTION
There is a simple solution to reduce the product term
requirements when using cascading XOR (or other)
logic. Figure 1 shows a circuit cascading five exclusive
ORs. As designed, this circuit expands to 32 product
terms when expressed in the minimized sum-of-products form. (This is assuming that signals A thru F are

single product terms themselves.) Figure 2 shows the
minimized logic equation file produced by Intel's Logic
Optimizing Compiler (iLOC).
An easy solution to fitting this logic into the 5C121 is
to cascade three exclusive ORs together and then send
the result through a No Output Combinational Feedback primitive (NOCF). This signal can now be cascaded through two more XOR's to get the five total. This
circuit is shown in Figure 3. Figure 4 shows the logic
equation file for this implementation. Note the reduction in product terms from Figure 2. If the buried registers are available, Intel's iPLDs software will automatically assign the combinational feedback to a buried register thereby saving a pin. This technique can be used
for any circuit that generates excessive product terms.
The only penalty in this method is the added delay
needed for the feedback path. The worst case 1pd (input
to output delay) for the circuit in Figure 3 would be
twice the specified Tpd in the 5C121-XX data sheet.
Basically the signal must go through the device twice.
For the 5C121-90 the Tpd would be 180 ns worst case
as implemented in Figure 3.
Figure 5 shows the report file generated by the compiler. In this case the NOCF path was automatically assigned to the buried registers.

:=lD-:=l~~
~I-----~
L-./ E-.J~
L-./

r--J

I

lOUT

I

I

._----_ ..

292003-1

Figure 1. Cascaded Excluslve..QRs

E

.-------~
D-;=)~
I
lOUT

.. _---_ ..

r

I

I

Figure 3. Cascaded Exclusive-ORs using Combinational Feedback

2-107

292003-2

AB-8

5C12l
cascading exclusive or's
LB Version 3.0. Baseline l7x, 9/26/85

5C12l
CASCADING 5XORS WITH COMBINATIONAL
FEEDBACK

PART:

LB Version 3.0, Baseline l7x, 9/26/85
5C12l
PART:

INPUTS:
Ap, Bp, Cp, Dp, Ep, Fp

5C12l
INPUTS:
Ap, Bp, Cp, Dp, Ep, Fp

OUTPUTS:

o

OUTPUTS:

o

NETWORK:
A
B
C
D
E
F
0
EQUATIONS:
NO

INP(Ap)
INP(Bp)
INP(Cp)
INP(Dp)
INP(Ep)
INP(Fp)
CONF (NO, Vee)

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

NETWORK:
A
B
C
D
E
F

F • E' • D' • C' • A' • B'
F' • E • D' * C' • A' • B'
F' • E' • D • C' • A' • B'
F' • E' • D' • C • A' • B'
F' • E' • D' • C' • A' • B
F' • E' • D' • C' • A • B'
F • E • D • C' • A' • B'
F • E • D' • C • A' • B'
F • E • D' • C' • A' • B
F • E * D' • C' * A • B'
F • E' • D • C • A' • B'
F • E' * D • C', • A' • B
F • E' * D • C', • A • B'
F • E' • D' • C • A' • B
F • E' • D' • C • A • B'
F • E' • D' • C' * A • B'
F' • E • D • C * A' • B'
F' • E • D • C' • A' • B
F' • E * D • C' • A • B'
F' • E • D' • C • A' • B
F' • E • D' • C • A • B'
F' • E • D' • C' • A • B
F' • E' • D • C • A' • B
F' • E' • D * C • A • B'
F" E' • D • C' * A • B
F' • E' * D' • C • A * B
F • E • D • C • A' • B
F • E • D • C • A • B'
F • E • D • C' • A • B
F • E • D" • C • A • B
F • E' • D • C • A • B
F' • E • D • C • A • B;

Figure 2. Minimized Logic Equations for Figure 1

2-108

o

N2
EQUATIONS:
N3

=

INP(Ap)
INP(Bp)
INP(Cp)
INP(Dp)
INP(Ep)
INP(Fp)
CONF (NO, Vee)
NOCF (N3)

D * C' * A' • B'
D' • C • A' • B'
D' • C' • A' • B
D'
C' • A • B'
D • C • A' • B
D * C • A • B'
D • C' • A • B
D' • C * A • B;
NO
F • N2' • E'
+ F' • N2' • E
+ F' • N2 • E'
+ F • N2 * E;

+
+
+
+
+
+
+

·

Figure 4. Minimized Logic Equations for Figure 3

inter

AB-8

I.. oqi (' IJpt imiz.i ng CompilE'r' Uti li7dti on Report
.*:+.~

.... Design implemen ted SUCCE'ssfu 1 J y

JRD

INTEL
october 8,

198t>

1

t>C121
CASCADING 5XoRS WITH COMB] NAT J UNAL H::I:.DBACK
LB Version 3.0, Baseline 1/x, 9/20/85
t>C121

GN))
GND
GND
GND
biN))
GND
GNU
GND
GND
GND
GND
GNfJ
GNU
GND
GNU
GNfJ
GND
GND
GND
GND

-I 1
-I ~
-I 3
-I 4
-I t>
.- f 6
_M: 7

-I 8

-- :

9

-: .10

-Ill
--112
-113

-- I 14
-- 11 t>
-: If:,
-Ill'

-118
-: 19

-120

401- Vce
Vcc
Ap
371 Bp
.. 161- Cp
.351· Dp
.341- E'p
::>.3: -- Fp
3'.,1: '::;8: -

.:,2:- 0
RE:-SI:.RVFD
.501- RFSERVED
RESERVI-Il
2'''''
- GND
21=-::
~~l: -- GND
~:-!bl - GNU
2.5: ._- GND
24: - (iND
231·- GNn
22:- GND
211- GND
31:-

.:+.INPU1S:+.:+.
f-epds:

Namp

Pin

fh?SClUt"C €I

f-p

~~s

INP

Ep

34

fNP

Dp

3!'i

INP

13

Up

.Sf;.

INP

l.S

Bp

:37

INP

I::;

Ap

.18

INP

13

Name

Pin

Resource

n

:;~')

CONI'

MCpl1 II

PTetms

MCells

01:.

CI ,~ar

Clock

4',rllllT PIITS~''''
MCel! II

PTpt-m __
4/

Fper.ls:
MCells

1)1:

Cleat

t~

292003-3

2-109

inter

AB·8

H·BlIRIEll REG!::; r~.H~H-+F~eds:

Name

Pin

Resourc~

MCell II

F'I

NOr:~

Namf>

Pirl

Rt?sout'"cp

MCells

!.IE

Cl .. ",y

FJ

MCE'l]

P1E'FmS

28
'?7

10

1

2
4
!j

b

7

8

'.lD
II
12
lJ
14
15

Ib
17

4

,?"

1::

<'5

h

~)4

h

:.) ~.;
2~'

21

20

,~

IU
4
12
4

1'~

Iq
lFl
1/

21

1-2

8

22
23
24

II
10

8
4
1;.-

18

~~5

2b
27
2>.1

29

"8

"H
4

/

lU

h

H

::;
4

6
b

.3U
31

-,

I;

2

10

NA
NA
NA

14
15
1"

8

~l

I-J

**PART lJTILIZA1ION-+--+18%

Pins

7%

MacroC~I]s

5%

Pt.e,-ms
292003-4

Figure 5. The Utilization Report

2-110

AB-9

APPLICATION
BRIEF

May 1986

5C121 As A Three
And One Half Digit
Display Driver

THOM BOWNS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292006-001
2-111

AB-9

INTRODUCTION
Described is a method of constructing a multi-digit,
seven segment decoder driver with latching capability
in a single EPLD. The design is a simple, easily understood method of using the 5Cl21 as a seven-segment
display driver.
This design has many advantages: (1) the ability to update a single digit without disturbing the others, (2)
Outputs are latched and retain their data without update from the controlling device(s), (3) Input interfacing is simple and straightforward, using four data inputs, two digit select lines, and a data strobe line.
The display driver interface is therefore not limited to
microprocessor applications only (although it can be
used with them). Possible applications include a Multimeter display, a clock or timer display, or a simple
controller system display.

PROBLEM
The display driver needs to latch the incoming data at
the correct time, route it to the correct digit, and then
decode the four bit data into seven-segment output format.

SOLUTION IN EPLD,
A simple solution to the display driver imagined above
can be realized in the 5C121 EPLD ..
,The 5C121 EPLD is organized in groups of Macrocells.
Each Macrocell contains a number of multiple input
AND gates which are feeding an OR gate. The OR gate
feeds a selectable registered output. This output may
also be routed back into the array for feedback purposes.
Figure 1 shows a basic block diagqun of the three and
one half digit display driver. The data is input to a
distribution block, which sends the data to one of four
seven-segment decoders depending upon the digit selected by the Digit Select inputs. The outputs are updated by strobing the WR input. The data input is in a
HEX format and may be in the range of 0 to F HEX (0
to 15 Decimal). Digit select is placed upon the two
select lines in a binary format; 0, 1, 2, 3. When data is
present on the input lines and a digit is selected, the
strobe line may be pulsed high and that output digit is
then updated to the numeral suggested by the input
data.

Figure '2 illustrates the Boolean equivalents of the design in Figure 1. In the NETWORK section of Figure
2, the inputs and outputs of the design are described.
For instance, the NETWORK equation
SSA1, SA1F = RORF (ISA1, WRN, GND, GND, VCC)

represents that the output pin for segment "A" of the
1st Seven Segment display (SSAl) results from a Registered Output Registered Feedback (RORF) structure in
the EPLD. The feedback signal (SAIF) is the same as
the signal output (SSAl). The RORF's D input is driven by the signal ISAl, the clock input is driven by
WRN, and reset, preset and output enable signals are
tied to their default voltage levels (either GND or
VCC).
The EQUATION section of Figure 2 shows how the
data distribution and decoding logic works. Equations
starting with A-G are generic seven segment display
equations. Segment decoding results from the combination of the true or false of the four data inputs (e.g., DO
or !DO).
Equations such as
SE1 = (E· WE1)

+

(SE1F • !WE1)

show how the data, is distributed. Segment E of display
1 (SEl) is valid (ON) if~e "E" decode exists and display 1 is chosen by the address inputs (WEI = !AO •
!Al). It is also valid if it was previously turned on
(SElF) AND seven segment display 1 is not selected
(!WEt).
These equations may be entered using LB in the form
of It Netlist, or may be entered directly into the ADF by
means of a text editor. The ADF is then compiled and
programmed into a 5C121 using iPLS.

SUMMARY
This method of using the 5C121 as a three and one half
digit display driver is advantageous in respect to its
simple interface, and its ability to hold all other digits
stable while one is being updated. Displays with more
than three and one half digits may be produced in the
5C121 by using the input latches as data storage and by
multiplexing the outputs in a scanning fashion.

AB·9

WRO~--------------------------------,

~

DECODE
4

LATCHES

7

000----1
010----1

020----1

DATA
DISTRIBUTION

030----1

AOo---~

Al 0----1

SELECTION
292006-1

Figure 1. Block Diagram

2·113

AB-9

Thorn Bowns
Intel
Oc tobt? r- 29, 1 9:3"~.
1.14
1
5C121

3.5 digit output dr-iverLB Yer-sion 3.0, Baseline 17x, 9/26/85
PART: SC1~H
INPUTS: AOp,Alp,DOp,Dlp,D2p,D3P,WRp
OUTPUTS: SSAl,SSBl,SSCl,SSDl,SSEl,SSFl,SSGl,SSA?,

SSB 2 'I SSC~~ , SSD2 'I SSE2 , SSF2 ., SSG~2 'I SSA'::; , !:'iSB:.5 , sse::') , SSD~) , SSE::~ , SSF ;:,; ., SSG::') ., SSA4

NETWORK:
SSA1,SAIF
SSB1,SBIF
SSCl,SClF
SSD1,SDIF
SSE1,SEIF
SSFl,SFIF
SSGl,SGl F
SSA:'- , SA~~F

RORF
. . RORF
= RORF
- RORF
- RORF
- RORF
"" RORF.,'
, " HORF

SSB~!,SB2F = RORF

(ISA1,WRN,GND,GNO,YCC)
(ISBl,WRN,GND,GND,YCC)
(ISCl,WRN.,GND,GND,VCC)
(ISDl,WRN,GND,GND,VCC)
(SE1,WRN,GND,GND,vec)
(SFl,WRN,GND,GND,YCC)
(SGl, WRN, GND, GND, VCC)
(SA2, WRN, GND, GND, vee)
(SB2,WRN,G'ND,(3ND,VCC)

SSC:'- , SC2F "" RORF (SC2, WRN , GND, GND , Yee:)
SSD~~., SD2F = RORF (SD~~., WRN., GND., GND., vcr:)
SSE2, SE2F "" RORF (SE2, WRN , GND , GND, YCI:)
SSF2,SF2F

=

RORF (S~2,WRN,GND.,l:.iND,VCC)

SSG2 ., SE,2F :: RORF

(SG~., WRN., GND ., GND., vee)

SSA3,SA3F = RORF (SA3,WRN,GND,GND,VCC)
SSB~:),SB3F

.. RORF
SSC3,SCJF - RORF
SSD3 , SD3F . RO RF
SSE3,SE3F ~ RORF
SSF3,SF3F " RORF

(SB3,WRN,GND,GND,YCC)
(SC3,WRN,GNO,GND,VCC)
(SD::; , WRN , CiNO , GND , YCr:)
(SE3,WRN,GND,GND,YCC)
(SF3,WRN,GND,GND,Yec)

SSG3,SG3F :: RORF (SG3,WRN,GND,GND,VCC)

SSA4, SA4F "" RORF (SA4, WRN ,GND, GND , Yec)
ISAI - NOCF (SAl)
ISBI " NOCF (SI:31.)
ISCI :: NoeF (5el.)
ISD! - NOCF (BDl)
WRN ::: NOT (WR)
WR "" INP (WRp)
DO "" INp ([lOp)
D1 "" INP (DIp)
D2 ;; INP (D2p)

D3 .. INP (D:")p)
AO :: INP (AOp)
Al ::: rNP (Alp)
EGlUA T! ONS :
A _ !D3*!D2*!Dl*OO + !DJ*D~*!01*!DO + 0~*!D21~1*DO + D3*D2*!Dl*DO;
Ii ." ! D3*D::~*! Dl*DO + 1l~*Dl *! DO + D3*D2*! D11'! DO + D::'~":Dl'+:DO;
e ::: !D3*!02*Dl*!DO + OJ*D2*!01*!DO + D31'D2*Dl;
D - !D3*!D2.+:!Dl*OO + !D3*D2*!D1*!DO + D2*DltDO + D3*!D2*Dl*!DO;
E:
! 031' ! 02:tDO f ! 1l~.;*D~~*! D'j .... 1D3*D:?*Dl *Dll ... D:5,1! D2*! Lll>l:1l0;
F - !D31'!D2*!Dl'+:DO + !03*!D2*Dl + !D3*D2*01'ml + 03*D2*!Dl*DO;
G _. ! D31'! O:?*! Dl -+ ! D...I*1)2*0.1 *00 .... D3*D~?*! D.l1 !DO;
292006-2

Figure 2. ADF Listing

2·114

inter

AB-9

-+: WEI)
(SI-:1F >I- ! WFI ) ;
SFI :: (F .+. WE!)
of (SnF ... !WEI);
SGI :: (G ... WEl)
+ (SGIF .... !WEl);
SA2 -- (A :+: WE::~)
+ (SA2F .01. ! WE~~) ;
SB2 :: (B :+: WE2)
+ (SB:~F :+ !WE?) ;
SC2 -- (C :+: WI'_2)
+ (SC2F :+: ! W~:2) ;
SD2 -- (D >I- WE2)
+ (SD2F i: !W(2) ;
(E :+: W1:"2)
SE2
+ (SE2F- .+: !WE:?) ;
(F :+. WE2)
SF2
+ (SF2F :+ !WE2) ;
WE2)
(G
SG2
t (SG2F -+: !WE2) ;
SA3 :: (A :+ WFJ)
+ (SMF + ! WE~;) ;
SB3 :: (B -+: WE3)
+ (SB3F i. !WE5) ;
(C :+: WE':;)
SC3
f (SC3~- :+: ! W~::;) ;
(II -+: WE3)
SD3
+ (SD~'lF :+: !WF3);
SE3 :: (E :+' WE:3 )
+ (SE3F .., ! WE~;) ;
(F >I- WE3)
SF::';
+ (SF3F :+: !WE:n;
SG3 -- (G + WE~')
+ (SG3F .+. !WE5) ;
SAl :: (A -+: WEI)
of (SA1F- :+: !WE!) ;
(B >I- WEI)
SBl
!WEl);
+ (SBIF
(C .., WEI)
SCI
+ ( SClF- -+: ! WE 1);
(D .+: WE!)
SIll
of ( SDlF: >I- ! WEI);
«!Il3-+:!Il2:+:!Dl:+:!DO) :+. WE4) + (SMF :+: !WE4) ;
SM
!AO >I- !AI;
WE'!
AD t: !AI;
WE2
!AO :+ AI;
Wl.3
WE4
AO t: Al;
SF.!

(I"

-I

.

..

E::ND$

292006-3

Figure 2. ADF Listing (Continued)

2-115

inter

APPLICATION
BRIEF

AB-10

June 1986

Square Pegs in Round Holes-A
Fitting Tutorial for the 5C121

J. R. DONNELL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292014-001
2-116

inter

AB-10

Once the basic 5C121 architecture is understood, intelligent pin assignments can be made. After assigning the
pins recompile the design using iPLS.

INTRODUCTION
This application brief explores the various techniques
for getting the most out of Intel's line of Erasable Programmable Logic Devices (EPLDs). In many cases,
techniques discussed here will not be needed due to the
intelligent fitting algorithms built into Intel's Programmable Logic Software (iPLS). As a matter of fact, most
designs can be implemented in EPLDs without any
knowledge of the device architectures. For complex designs, the designer will still need an in-depth understanding of the target EPLD in order to maximize the
EPLD's utility.
This application brief explores fitting techniques for the
5C121, a 1200 gate equivalent CHMOS EPLD. The
techniques described here will also apply to any EPLD
that supports a similar architecture.

FITTING
When fitting logic designs into the 5C121 there are two
typical scenarios: 1) The 5C121 design has been completed without pin assignments and the compiler warns
the user that fitting may be time consuming, and 2) pin
assignments have been made and the "'**ERR-FIT
. . . " message comes up.

Compiling the design with pin assignments is a new ball
game. This time it is fit or not fit. If the design does not
fit, an error like: ""'ERR-FIT-It is not possible to
fit the specific pin requests you made" will occur. In
most cases, the compiler will also ask if it can remove
pin assignments and try its own. If the design has already been attempted without pin assignments, or if
specific pin assignments are needed, answer no and isolate the problem.

ISOLATE THE PROBLEM
The first step towards isolating the problem is to print
out a copy of the utilization report « Filename> .RPT), logic equation file «Filename> .LEF),
and the Advanced Design File «Filename> .ADF).
Next, fill out the 5C121 architecture worksheet included in this application brief. Include the signal name for
each pin, the type of output, and the number of product
terms needed for each output. All this information is
available in the files that were printed earlier. The next
step is to identify the conflict .

Let's look at the first situation.

CONFLICTS

In general, if the designer does not care what signals get
assigned to what pins, the choice can be left to the
compiler and the compiler will make pin assignments.
For simple designs pin assignments are very easy. However, designs that include a variety of different register
types, feedback paths, and product term widths may
take a long time for the compiler to fit. When the designer is faced with the message, "Fitting may be time
consuming", the compilation should be aborted, and
intelligent pin assignments made. NOTE: Control C
(hC) may be used to abort a design. The software will
not stop immediately because the software does not poll
the keyboard until it updates the display. Rebooting the
system will also work.

There are three potential conflicts with pin assignments
in the 5C121; incompatible output structures, excessive
product terms, and local/global feedback conflicts. Incompatible output structures and excessive product
term errors are the easiest to spot.

To make intelligent pin assignments, the designer needs
a basic understanding of the architecture of the part.
For the 5C121 this understanding should include the
number of product terms supported in each Macrocell,
what Macrocells support local feedback, and what
Macrocells support global feedback. This information is
easily found in the data sheet. One other point, the
Macrocells in the 5CI21 are grouped into groups of
four. All Macrocells in a group must have the same
output type. Therefore, if one output is registered, the
other three must also be registered. This means that a
combinatorial output could not be put into the same
group as a registered output. Output enable (OE) terms
are also based on Macrocell grouping. All four Macrocells are driven from the same OE term.

INCOMPATIBLE OUTPUT
STRUCTURES
As shown in the 5C121 Design Worksheet, the 5C121
is divided into six Macrocell groupings. The data sheet
refers to these as the A-I, B-1, A-2, B-2, A-3, and B-3
Macrocells. One requirement of the 5C121 architecture
is that Macrpcells within the same grouping have the
same output structure. This was discussed earlier, but it
is worth revisiting. The file titled example 1 in the appendix shows an ADF for a design that contains such
an 1/0 conflict. Following the ADF is a completed
5C121 architecture worksheet with a number of problems. Concentrating on the incompatible output problem on the 5C121 worksheet, notice that pins 31 and 32
belong to the same Macrocell group, and that they are
assigned conflicting 1/0 structures.
The solution to an incompatible output structure conflict may be as simple as reassigning pins. Another option may be to use a different output type for that sig-

2-117

intJ

AB-10

nal. This is very dependent on the design. Another option is possible when a Macrocell grouping has been
assigned combinatorial output structure, and a registered output needs to be assigned to that same group. A
possible solution is to use one of the buried registers
configured as a NORF (No Output Registered Feedback) cell to hold the signal, and then send the signal
out through a CONF (Combinatorial Output No Feedback) primitive. This output primitive is compatible
with the other output primitives in that grouping, and
the register output requirement has also been satisfied.
The penalty is loss of speed due to the additional feedback path.

EXCESSIVE PRODUCT TERMS
Excessive product term conflicts are also easy to spot.
(A product term consists of a set of signals ANDed
together which are separated from other ANDed
groups by an OR gate.) Written next to the I/O slot on
the 5CI21 architecture worksheet is the number of
product terms that each Macrocell supports. Match
that number with the number of product terms for each
output indicated in the logic equation file (LEF). If
more product terms are required of a output than are
provided, there is a product term conflict. The utilization report also shows the number of product terms
used for each signal.
The solution, again, may be as simple as reassigning
pins since the 5CI21 supports varying product term
widths. In fact, the 5Cl21 supports up to 16 product
terms on pins 16 and 24. Note that four of those product terms are shared with the adjacent Macrocell. Sharing means that those signals are common. It is not
product term allocation. If the number of product
terms exceeds the capability of the device, the design
may still fit by splitting up long equations and inserting
NOCF (No Output Combinatorial Feedback) primitives. Again the price for using this solution is reduced
speed. This technique is covered more thoroughly in
AB-8 titled: Implementing Cascaded Logic in the
5Cl21.

LOCAL/GLOBAL FEEDBACK
It is possible to encounter one other type of fitting conflict in the 5C121. This occurs when a feedback signal
from the A-lor A-2 Macrocells feeds the B-1 or B-2
Macrocells. The issue is that these Macrocells feed busses that are local to one half of the chip. Therefore, the
signal is not physically available to the other side of the
device.

The best way to understand the local and global bussing in the 5C121 is to divide the chip in half1engthwise.
One side contains the A Macrocells, and the other side

contains the B Macrocells. The two sides are mirror
images. Speaking generically now, the -I and -2 Macrocells feed only local busses; local to their respective side
of the device. The -3 Macrocells and the buried registers feed global busses which route signals to both sides
of the device. Therefore a feedback signal coming from
the A-lor A-2 group can only feed the A Macrocells,
however, a feedback signal from the A-3 group could
feed the B-1, B-2, B-3, or the B buried Macrocells. This
local!global bussing applies to both feedback and input
signals on the I/O pins. All of the dedicated inputs feed
the global bus.
Example I also shows a simple two bit counter with
seven segment driver outputs. The worksheet shows
that the counter registers were assigned to pins 27 and
28, while the seven segment outputs were assigned to
pins 8 thru 14. The seven segment outputs decode the
feedback signals from the counter registers to generate
the appropriate digit output, and therefore must have
access to those signals. This presents a local!global
feedback conflict. If the designer is locked into those
specific pin assignments a design workaround is needed.
One solution might be to take the outputs of the counter and externally tie them to dedicated input pins
thereby making those signals global. This would work
but that solution ends up wasting input pins. A better
solution would be to internally route the counter feedback signals through one of the buried registers configured as a NOCF primitive. After passing through the
buried register the signals become global. Both the incompatible output solution and this solution are shown
in the worksheet, ADF, and utilization report shown as
example 2. If we did not need the counter signals externally, it would of been wise to &imply use the buried
registers to perform the counting fun,ction.
One final comment regarding the utilization report.
The utilization report shown in example 1 indicates
that signals CLK and CNT feed Macrocell 1001 and
1002. These are fictitious Macrocell numbers that the
software assigns to requests that cannot be met. In example I, three requests were unfulfilled: REGOUT,
LED I and LEDO. REGOUT was unfulfilled because of
incompatible output structures. LEDO and LED I were
unfulfilled because their feedback signals needed to
drive the seven segment display outputs. This was impossible because the LED outputs were assigned to a
local bus on the opposite side of the device.
The files shown in example 2 fix the LED fitting problems by sending the feedback signals through the buried
registers, thereby making them global. In the case of
REGOUT, the buried register primitive NORF (No
Output Registered Feedback) is used, allowing the output primitive to be combinatorial.

2-118

AB-10

EXAMPLE 1

ADF
JR Donnell
Intel
April 3, 1986

o
5C121
Fitting exe.ple
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C121
INPUTS: CNT82,CLK81
OUTPUTS: LED0828,LED1827,REGOUT832,CONFOUT831,SEGA88,
SEGB89,SEGC810,SEGD81l,SEGE8l2,SBGF8l3,SBGG8l4
NETWORK:
LEDO,A = RORF (NLSDOD,CLK,GND,GND,YCC)
LSDl,B
RORF (NLSDlD,CLK,GND,GND,YCC)
RSGOUT
RONF (NRSGOUTD,CLK,GND,GND,YCC)
CONFOUT
CONF (NCONFOUTIN,YCC)
SSGA
CONF (NSSGAIN,YCC)
SSGB
CONF (NSSGBIN,YCC)
SSGC
CONF (NSSGCIN,YCC)
SSGD
CONF (NSSGDIN,YCC)
CONF (NSSGSIN,YCC)
SSGS
SHGF
CONF (NSHGrIN,YCC)
SHGG
CONF (NSHGGIN,YeC)
CLK = INP (CLK)
CNT
INP (CNT)
EQUATIONS:
NSHGGIN = 2
+ 3;
2
B*/A;
3
A*B:
NLHDlD
IA*/B*CNT
+ IUU/CNT
+ A*/B*CNT
+ A*B*/CNT:
NLHDOD = IA*B*CNT
+ A*/B*/CNT
+ A*/B*CNT
+ AU*/CNT:
NSHGrIN = 0:
o = IB*/A:
NSIIGHIN
0
+ 2;
NSHGDIN
0
+ 2
+ 3;
NSEGCIN
0
+ 1
+ 3;
1 = IUA:
NS8GBIN
0
+ 1
+ 2

=
=
=

=

=
=

=

+ 3;

0
+ 2
+ 3;
NCONrOUTIN
A*B:
NREGOUTD = IA*/B:
BNDS
NSBGAIN

292014-2

2-119

AB-10

SUMMARY
As programmable logic devices become more dense, signal routing and resource partitioning becomes necessary. In
general, these choices are made by the semiconductor manufacture to most efficiently utilize the available logic. In
some cases though, these choices make certain designs more difficult to implement in a given device. Intelligent
software, a basic knowledge of the device architecture, and a little experience in fitting techniques will always make
the job easier.

EXAMPLE 1 (Continued)
5C121 Design Worksheet

-.£!L..
PIN-NAME

~
~

~

~

~

~
~
~

~

~

....ill!....

292014-1

2-j20

intJ

AB-10

EXAMPLE 1 (Continued)
Logic Optimizing Compiler Utilization Report

*****

Unable to implement design

JR Donnell
Intel
April 3, 1986

o
5C121
Fitting exa.ple
LB Version 3.0, Baseline 17x, 9/26/85
5C121
CLK
CNT
GND
GND
GND
GND
GND
SEGA
511GB
SEGC
SEGD
SEGII
SEGF
SBGG
RESERVED
GND
GND
GND
GND
GND

-

1
- 2
3
- 4
-: 5
- 6
- 7
- 8
- 9
-:10
-: 11

-

-: 12
-: 13

-: 14
-:15
-:16
-: 17
-:18
-: 19
-:20

40:39:38:37:36:35:34:33:32:31:30:29:28:27:26:25:24:23:22:21 :-

Vee
Vee
GND
GND
GND
GND
GND
GND
RBSERVED
CONFOUT
RIISERVED
RESERVIID
GND
GND
GND
GND
GND
GND
GND
GND

**INPUTSU

Na.e

Pin

CLK
CNT

Resource

MCell #

PTerm.

MCell.

Feeds:
011

Clear

Clock
Reg

INP
2

INP

Naae

Pin

Resource

MCell /I

PTer ••

SIIGA

8

CONF

28

2/ 4

Sl!GB

9

CONF

27

2/10

Sl!GC

10

CONF

26

2/ 8

Sl!GD

11

CONF

25

2/ 6

1001
1002

UOUTPUTS . .
MCell.

Feed.:
OE

Clear

292014-3

2-121

intJ

AB-10

EXAMPLE 1 (Continued)
SHGB

12

CONF

24

SIIGF

13

CONF

23

1/ 8

SIIGG

14

CONF

22

1/10

CONFOUT

31

CONF

2

1/10

RONF

NCell ,
1000

PTerm.
1

NCells

LIDI

RORF

1001

2

2
22
23
25
26
28
1000
1001
1002

LIDO

RORF

1002

3

2
23
24
25
26
27
28
1000
1002

Resource

NCell

PTerms

21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
1

4
12
4
8
8
8
8
4
12
4
10
8
6
6
8
4

13
14
15
16

8
8
8
8

1/ 6

**UNFULFILLBD RBQUBSTS**
**OUTPUTS*,
Name
RBGOUT

Pin

Resource

Feeds:
011

'Clear

**UNUSBD RBSOURCBS**
Nalle

Pin
3
4
5
6
7
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
32
33
34
35
36
37
38
NA
NA
NA
NA

2-122

292014-4

292014-5

inter

AB-10

EXAMPLE 2

ADF
JR Donnell
Intel
April 3, 1986

o
5C121
Fi tt ing exa.ple
LB Version 3.0, Baseline 17x, 9/Z6/85
PART: 5C1Z1
INPUTS: CNT8Z,CLK81
OUTPUTS: LBD08Z8,LBD1827,RBGOUT83Z,CONFOUT831,SEGA88,
SEGB89,SBGC810,SBGD811,SBGB812,SEGF813,SBGG814
NBTWORK:
LBDO,NATONOCF = RORF (NLBDOD,CLK,GND,GND,VCC)
LBD1,NBTONOCF = RORF (NLBD1D,CLK,GND,GND,VCC)
RBGOUT = CONF (NRBGOUTIN,VCC)
CONFOUT = CONF (NCONFOUTIN,VCC)
SBGA
CONF (NSBGAIN,VCC)
SBGB
CONF (NSBGBIN,VCC)
SBGC
CONF (NSBGCIN,YCC)
SBGD
CONF (NSBGDIN,VCC)
SBGB
CONF (NSBGBIN,VCC)
SBGF
CONF (NSBGFIN,VCC)
SBGG
CONF (NSBGGIN,VCC)
NOCF (NATONOCF)
A
eLK = INP (CLK)
B
NOCF (NBTONOCF)
NRBGOUTIN
NORF (NRBGOUTD,CLK,GND,GND)
CNT
INP (CNT)
BQUATIONS:
NLBDOD = /A*B*CNT
+ A*/B*/CNT
+ A*/B*CNT
+ A*B*/CNT;
NLBD1D
/A*/B*CNT
+ /A*B*/CNT
+ A*/B*CNT
+ A*B*/CNT;
NCONFOUTIN = A*B;
NSBGAIN
0
+ 2
+ 3j
NSBGBIN
0
+ 1
+ Z
+ 3;
NSBGCIN
0
+ 1
+ 3;
NSBGDIN
0
+ 2
+ 3;
NSBGBIN
0
+ 2;
NSI!GFIN
0;
NSI!GGIN
Z
+ 3;
NRI!GOUTD
/A*/B;
2
B*/A;
3 = A*B;
o = IB"'/A;
1 = /B*A;
BND$

=
=

=

=

=

=

2-123

292014-7

inter

AB-10

EXAMPLE 2

(Continued)
5C121 Design Worksheet

~
~

~

SEGC

~

~
SEGE

~

.JlQ2...

SEGG

LED1

292014-6

2-124

intJ

AB-10

EXAMPLE 2

(Continued)

Logic Optiaizing Coapilar Utilization Report
***** De.ign iaple.ented succe.sfully
JR Donnell
Intel
April 3, 1986

o

5C121
Fitting exaaple
LB Version 3.0, Baseline 17x, 9/26/85
5C121
CLK
CNT
OND
OND
OND
OND
OND
SIIOA
SlOB
SHOC
SlOD
SIIOI
SlOI'
SlOO
RISIIRVIID
OND
OND
OND
OND
OND

-: 1

-:
-

2
3
4
-: 5
-: 6
-: 7
-: 8
-: 9
-:10
-: II

-:12
-il3
-: 14
-: 15
-: 16
-: 17
-: 18
-: 19
-:20

40:39:38:37:36:35:34:33:32:31:30:29:28:27:26:25:24:23:22:21:-

Vcc
Vee
OND
OND
OND
OND
OND
OND
RHOOUT
CONFOUT
RIISIIRnD
RIISIIRVHD
LIDO
LlDl
RIISIIRVIID
RIISIIRVIID
OND
OND
OND
OND

.. INPUTS**
Na••

Pin

Resource

CLK

1

INP

CNT

2

INP

Pin

Resource

MCell #

PTera.

MCell #

PTera.

MCells

Feed.!
OB

Clear

Clock
Reg

5
6

..OUTPUTS**
Naa.

SIIOA

8

CONI'

28

2/ 4

SlOB

9

CONI'

27

2/10

SHOC

10

CONI'

26

2/ 8

SHOD

II

CONI'

25

2/ 6

MCells

Feeds!
OB

Clear

292014-8

2-125

inter

AB-10

EXAMPLE 2 (Continued)
SBGB

12

CONI'

24

SIlGF

13

CONI'

23

1/ 8

SIlGG

14

CONI'

22

1/10

1/ 6

LBD1

27

RORF

6

2/ 8

13

LBDO

28

RORF

5

3/ 6

14

CONFOUT

31

CONI'

2

RIlGOUT

32

CONI'

1/10
1/ 4

**BURIED REGISTERS**
Naae

Pin

Resource

MCell ,

PTer.s

MCella

NOCF

13

1/ 8

2
5
6
15
22
23
25
26
28

NOCF

14

1/ 8

2
5
15
23
24
25
26
27
28

NORI'

15

1/ 8

Resource

MCell

PTera.

21
20
19
18
17
12

4
12
4
8
8
8
8
4
12
4
10
6

Feeds:
OB

Clear

**UNUSED RESOURCES**
Nalle

Pin
3
4
5
6
7
15
16
17
18
19
21
22
23
24
25
26
29

11

10
9
8
7
4

292014-9

2-126

inter

AB-10

EXAMPLE 2 (Continued)
30
33
34
35
36
37
38
NA

3

8

16

8

**PART UTILIZATION**
35~

Pins

50~

MacroCella
pter.s

10~

292014-10

2-127

AB-11

APPLICATION
BRIEF

February 1987

16-Bit Binary Counter
Implementation
Using the SC060 EPLD

KARL-HEINZ WEIGL
INTEL CORPORATION
MUNICH, GERMANY

Order Number: 292015-002
2-128

intJ

AB-11

INTRODUCTION

TOGGLE FLIP-FLOPS

System designers often use programmable logic devices
to implement counters. Use of PLA devices lets the
user build customized counters to suit individual applications. In most cases such counters are not available,
'off-the-shelf SSI/MSI devices. In other applications,
the PLA implementation allows the designer to squeeze
the counter function along with other 'glue' tasks into a
single PLA, with the attendant higher integration benefits.

Counters can be most effectively implemented in PLA
architectures using toggle flip-flops. This is because
counters constructed with 'D' type flip-flops require an
additional product term for every successive significant
bit, whereas toggle flip-flop implementation requires
only one product term per significant bit. Thus, the
toggle flip-flop counter design is more miserly in product term consumption than the 'D' register design.
Since product term minimization is the key element to
maximizing PLA utilization, the T-FF counter design
is more efficient. The truth table for the toggle flip-flop
is shown in Fig. 2.

Use of traditional 20-pin and 24-pin PLAs, however,
does not allow for the construction of large counters
having greater than 10 significant bits. This is because
these traditional PLAs have register and product term
restrictions (even the larger bipolar PLAs have only 8
to 10 registers and less than 8 product terms per register). In contrast, the 5C060 24-pin erasable programmable logic device (EPLD) contains 16 registers that
are programmable as 'D', 'T', 'RS' or 'JK' types. These
16 programmable registers enable the construction of
Up/Down counters with up to 16 significant bits.
This application brief details the implementation of a
16-bit binary counter in the 5C060 EPLD. The design
also demonstrates efficient counter construction utilizing toggle flip-flops (T-FF) that allows for minimum
product term utilization.

DESIGN OBJECTIVE
The objective of the design is to implement a counter
with the following features: (i) 16-bit binary count, (ii)
toggle flip-flops, (iii) asynchronous clear, (iv) RUN/
STOP function and (v) UP/DOWN function. The
function table is shown in Figure 1.
RESET UP/DOWN RUN/STOP

X
0

X

0

1
X

1

0

0
1
1
X

Function

T

Q(N)

0
0
1
1

0
1
0
1

Q (N

+ 1)

0
1
1
0

Figure 2

SOLUTION
The 16-bit binary counter function was implemented in
the 5C060 EPLD using the Intel Programmable Logic
Development System (iPLDS). The equations for the
16-bit binary counter with the RESET, UP/DOWN
and RUN/STOP functions are shown in the 'EQUATIONS' section of the LEF (Fig. 4). The pinout of the
5C060 with the implemented counter is shown in the
RPT file (Utilization Report) Fig. 5. This RPT file also
shows, under the 'OUTPUTS' section, that in each
macrocell only one out of 8 product terms is used. In
contrast the same 16-bit counter designed using 'D'
type flip-flops would have required more than 16 product terms for the last significant bit.

Inhibit Counting
Count Down
Count Up
Reset All Outputs
to 'LOW'

Figure 1

2-129

AB-11

INTEL CORPORATION
JAN. 15. 1987

1
1.0
5C060
BINARY 16-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF

LB Version 4.01. Baseline 27.1 4/9/86
OPTIONS: TURBO=ON
PART: 5C060
INPUTS: RS.CLOCK.RESET.OO
OOTPUTS: '10. '11-.'12.'13.'14.'15.'16.'17 .Q8.Q9.QA.QB.QC.QD.QE.QF

NETWORK:

QO.QOF = TOTF (QOT.CLK.CLR.GND.VCC)
TOTF (Q1T.CLK.CLR.GND. VCC)
'11.'111'
'12.'12' = TOT' (Q2T.CLK.CLR.GND.VCC)
'13,'13' = TOT' (Q3T ,CLK,CLR,GND, VCC)
'14','14' = TOn (Q4T,CLK,CLR,GND,VCC)
'15,'16' = TOTF (Q6T,CLK,CLR,GND,VCC)
'16,'18' = Ton (Q6T,CLK.CLR,GND,VCC)
'17,'17' = Ton (Q7T,CLK,CLR,GND, VCC)
'18.'18'
TOTF (Q8T,CLK,CLR,GND,VCC)
'19,'19' = Ton (Q9T,CLK,CLR,GND,VCC)
QA,QAJ' = TOTF (QAT, CLK,CLR,GND, VCC)
QB,QBF = TOTF (QBT,CLK,CLR,GND,VCC)
TOTF (QeT,CLK,CLR,GND.VCC)
Qe,QCF
TOT' (QDT,CLK,CLR,GND,VCC)
QD,QD'
QE,QEF = TOTF (QET,CLK,CLR,GND,VCC)
QF
TONF (QFT,CLK,CLR,GND,VCC)
QOT
OR (QOO,QOD)
CLK = INP (CLOCK)
CLR
INP (RESET)
Q1T = OR (Q1U,QID)
Q2TOR (Q2U,Q2D)
Q3T = OR (Q3U,Q3D)
Q4T
OR (Q4U,Q4D)
Q6T = OR (Q5U,Q6D)
Q6T
OR (Q6U,Q6D)
Q7T = OR (Q7U,Q7D)
'leT = OR (QeO,QeD)
'leT = OR (QeU,QeD)
QAT = OR (QAU,QAD)
QBT = OR (QBU,QBD)
QeT = OR (QeO,QeD)
QDT = OR (QDO,QDD)
QET
OR (QEO, QED)
QFT = OR (QFU.QFD)
RS = INP (RS)
DO
INP (UD)
MUD
HOT (00)
QOU
AND (OD,RS)

=

=

=
=

=
=

=

=
=
=

=

=
=
=

292015-1

Figure 3. Example .ADF

2-130

AB-11

QIO
QlO
QSO
Q40
1160
QeD
QTO
QeD

= AIID

(OD,IIOI',IIOO)
(OD,Qll',Q10)
(OD,Q21',Q20)
= AIID (OD,Q3I',Q3U)
= AIID (OD,Q4I' ,Q40)
= AIID (OD,Q5I',Q50)
AIID (OD,IIBI',Q80)
= AIID (OD,QTI',Q70)
Q8U = AIID (OD,IIBI' ,Q8U)
CIAO = AIID (OD,Q8I',Q80)
QBU = AIID (OD, QAI' ,ClAU)
QCU = AIID (OD, QIII' ,QBU)
lIDO = AIID (OD, QCJ' ,QeU)
QKU = AIID (OD, QDI' ,lIDO)
QI'D = AIID (OD, QII' ,QED)
HQOI' = \lOT (1101')
RQlr
\lOT (QlI')
_ I ' = \lOT (Q2I')
MQSI' = \lOT (Q31')
MQ41' = \lOT (1141')
MQIiI' = \lOT (1161')
IIQ8I' = NOT (1161')
MQTI' = \lOT (QTI')
RQlr = \lOT (Q8r)
MQ8r = \lOT (Q8r)
IIQAJ' = \lOT (QAI')
lIQBI' = \lOT (QIII')
IIQCr = \lOT (QCJ')
RQDI' = \lOT (QDI')
IIQIr = \lOT (QII')
IIOD = AIID (IIDD, RS)
QID = AIID (IIDD, HQOr ,IIOD)
Q2D = AIID (IIDD,MQlI',Q1D)
QaD = AIID (HOD, MQ2r, Q2D)
Q4D = AIID (HOD, RQ3r ,Q3D)
QIiD = AIID (1IDD,MQ4r,Q4D)
QeD = AIID (HUD, RQ5r, Q5D)
QTD
AIID (IIDD,RQar,Q6D)
Q8D = AIID (IIDD,MQTr,Q1D)
Q8D = AIID (IIDD, MQer, Q8D)
ClAD = AIID (IIDD, RQer , QBD)
QBD = AIID (HUD, HQAI', ClAD)
QCD = AIID (HOD, HQIII' , QBD)
QDD = AIID (IIDD ,IIQCI' ,QeD)
lID = AIID (HOD, HQDI'. QDD)
QI'D = AIID (IIDD ,11QBr ,QED)

= AIID
= AIID
=

=

=

IHDI

292015-2

Figure 3. Example .ADF (Continued)

2-131

infef

AB-11

INTEL CORPORATION
JAN. 15, 1987
1

1.0
5C060
BINARY 16-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF
LB Version 4.01, Baseline 27.1 4/9/86
LEF Version 4.01 Baseline 22.2 2/4/86
OPTIONS: TURBO=ON
PART:
5COSO
RS, CLOCK, RESET, UD
OUTPUTS:
NETWORK:

oo,m,~,~,~,~,~,~,~,~,~,~,OC,~,~,~

CLK = INP(CLOCK)
RS = INP(RS)
CLR = INP(RESET)
UD = INP(UD)
QO, QOF = TOTF(QOT,
Q1, Q1F = TOTF(Q1T,
Q2, Q2F = TOTF(Q2T,
Q3, Q3F = TOTF(Q3T,
Q4, Q4F = TOTF(Q4T,
Q5, Q5F = TOTF(Q5T,
Q6, Q6F = TOTF(Q6T,
Q7, Q7F = TOTF(Q7T,
Q8, Q8F
TOTF(Q8T,
Q9, Q9F
TOTF(Q9T,

CLK, CLR, GND, VCC)
CLK, CLR, GND, Vce)
CLK, CLR, GND, VCC)
CLK, CLR, GND, Vce)
CLK, CLR, GND, VCC)
CLK, CLR, GND, Vee)
CLK, CLR, GND, VCC)
CLK, CLR, GND, VCC)
CLK, CLR, GND, VCC)
CLK, eLR, GND, VCC)
~,QAF
TOTF(~T, CLK, CLR, GND, VCC)
~,QBF
TOTF(~T, CLK, CLR, GND, vee)
QC, QCF
TOTF(QCT, CLK, CLR, GND, VCC)
QD, QDF
TOTF(QDT, CLK, CLR, GND, Vce)
~, ~F = TOTF(~T, CLK, CLR, GND, VCC)
QF = TONF(QFT, CLK, CLR, GND, vec)
EQUATIONS:
~T = DD' * ~F' * ~F' * OCF' * ~F' * QAF' * Q9F' * Q8F' * Q7F'
Q6F'
Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * RS
+~*~*~*~*~*QAF*~*~*~*~*~*
Q4F
Q3F
Q2F
Q1F
QOF
RS;

*

*

QET = UD' * QDF'
Q4F'
Q3F'

*

*

* QCF' *

*

*

* Q5F'

*

*

QBF' * QAF' * Q9F'
Q1F'
QOF'
RS

*
* Q2F' *
*
* Q2F * Q1F * QOF * RS;

*

* Q8F' * Q7F' * Q6F'

+~*~*~*~*QAF*~*~*~*~*~*~*

Q3F

QDT = UD' * QCF' * ~F' *
Q3F'
Q2F'
Q1F'

*

*

QAF' * Q9F' * Q8F' * Q7F' * Q6F' * Q5F' * QU'

* QOF' * RS

*

+~*~*~.*QAF*~*~*~*~*~*~*~*

Q2F

*

Q1F

* QOF * RS;

292015-3

Figure 4. Example .LEF

2-132

AB-11

QCT

* QBF' * QAF' * Q9F' * Q8F' * Q1F' * Q6F' * Q5F' * Q4F' * Q3F' *
* Q1F' * QOF' * as
QBF * QAF * Q9F * Q8F • Q1F * Q6F * Q5F * Q4F * Q3F * Q2F *
Q1F * QOF * as;
= UO' * QAF' * Q9F' * Q8F' * Q1F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' *
Q1F' • QOF' * RS
+~*QAF*~*~*~*~*~*~*~*~*~*
QOF * RS;
UO' * Q9F' * QBF' * Q1F' • Q6F' * QSF' * Q4F' * Q3F' * Q2F' * Q1F' *
QOF' * RS
+ UO * Q9F * Q8F * Q1F * Q6F * Q5F * Q4F * Q3F * Q2F * Q1F * QOF *
RS;
=

UO'
Q2F'

+ UO *
QBT

QAT

Q9T

Q8T
Q1T
Q6T
Q5T
Q4T
Q3T

= UO' * QBF' • Q1F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' *
RS
+ UO * QBF * Q1F * Q6F * Q5F *' Q4F * Q3F * Q2F * Q1F * QOF * RS;
=

* Q1F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F'

UO'

+ UO * Q7F * Q6F * Q5F * Q4F * Q3F * Q2F
= UO' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F'
+ UD * Q6F * Q5F * Q4F * Q3F * Q2F * Q1F
= UO' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F'
+ UO * Q5F * Q4F * Q3F * Q2F * Q1F * QOF
= UO' * Q4F' * Q3F' * Q2F' * Q1F' * QOF'
+ UO * Q4F * Q3F * Q2F * Q1F * QOF * as;
= UO' * Q3F' * Q2F' * Q1F' * QOF' * RS
+ UO * Q3F * Q2F * Q1F • QOF * RS;
= UO' * Q2F' * Q1F' * QOF' * RS

• Q1F'

* QOF' * RS

* Q1F * QOF * as;
* Q1F' * QOF' * RS
* QOF * RS;

* QOF' * RS

* RS;
* RS

* Q2F * Q1F * QOF * as;
* Q1F' * QOF' * RS
* Q1F * QOF • as;
= UO' * QOF' * RS
+ UO

Q2T
Q1T

=

UO'
+ UO

+ UO
QOT

*

QOF

* as;

= RS;

ENOS

292015-4

Figure 4. Example .LEF (Continued)

2-133

AB-11

Logic Optimizing Compller,Utllization Report
FIT Version 4.01 Baseline 27.1 4/9/86

*****

Design implemented successfully

**** NOTE:

Connect signal CLOCK to

pin 1 AND pin 13.

INTEL CORPORATION
JAN. 15. 1987
1
1.0

5C060
BINARY 16-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF
LB Version 4.01. Baseline 27. '1 4/9/86
OPTIONS: TURBQ=ON
5C060
CLOCK -: 1
GND ... : 2
Q7 - : 3
Q6 -: 4
Q5 -: 5
Q4 -: 6
Q3 : 7
Q2 -: 8
Ql -: 9
QO -1l0

-

un -: 11

GND -:12

24123: 22: 21: 20119118: 17116:-

Vec
RS
QF

QE
QD

QC
QB

QA

Q9

151- Q8

14: - RESET
131- CLOCK

**INPUTS**
Name

Pin

CLOCK
UD

Resource

MCell #

PTerms

MCells

Feeds:
OE

Clear

INP
11

Clock
CLKI
CLK2

INP

1
2
3
4
5
6

7
8
9
10
11
12
13
14
15
GND

12

GND

CLOCK

13

INP

RESET

14

INP

CLKI
CLK2
1
2

3
4
5
6

7
8
9
10
11
12
13
14
15
16

292015-5

Figure 5. Example .RPT File

2-134

AB-11

RS

23

1
2
3
4
5
6

INP

7

8
9
10
11
12
13
14
15
16

Vee

24

Vee

Pin

Resource

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

**OUTPUTS**
Name

Q7

TOTF

HCell

•
9

PTerms

HCells

2/ 8

1
2
3
4
5
6

Feeds:
OE

Clear

Clock

7

8
Q6

4

TOTF

10

2/ 8

1
2
3
4
5
6
7

8
9
Q5

TOTF

11

2/ 8

1
2
3
4
5
6
7

8
9
10
Q4

6

TOTF

12

2/ 8

1

2
3
4
5
6
7

8
9
10
11

292015-6

Figure 5. Example .RPT File (Continued)

2-135

intJ

AB·11

Q3

7

TOrr

13

2/ 8

1
2
3
4
5
6
7
8
9
10
11
12

Q2

8

TOTF

14

2/8

1
2
3
4
5
6
7
8
9
10

11

12
13
Q1

9

TOTF

15

2/8

QO

10

TOTF

16

1/ 8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
Q8

15

TOTr

8

2/ 8

1
2
3
4
5
8
7

Q9

16

TOTr

7

2/ 8

1
2
3
4
5
8

QA

17

TOTF

8

2/ 8

1
2
3
4
5
292015-7

Figure 5. Examl?le .RPT File (Continued)

2-136

intJ

AB·11

QB

18

TOTF

2/ 8

1

2
3
4
QC

19

TOTF

QD

20

TOTF

QE

21

TOTF

QF

22

TONF

4

2/ 8

1
2
3

2/ 8
2

2/8
2/8

**UNUSED RESOURCES**
Name

Pin

Resource

HCell

PTerms

**PART UTILIZATION**
95%
100%
24%

Pins
HacroCells
Pterms

292015-8

Figure 5. Example .RPT File (Continued)

2-137

inter

APPLICATION
BRIEF

AB-12

October 1988

Designing a Mailbox Memory for
Two 80C31 Microcontrollers Using
EPLDs

K. WEIGL & J. STAHL
INTEL CORPORATION
MUNICH, GERMANY

Order Number: 292016-003
2-138

inter

AB-12

INTRODUCTION
Very often, complex systems involve two or more microcontrollers to fulfill the requirements defined by a
given objective. Since the nature of microcontrollers
does not allow for easy dual-port memory design (no
"READY" input; no "HOLD/HLDA" interface; portoriented I/O etc.), design engineers are faced with the
problem of interchanging information (data and status)
between those microcontrollers. This application brief
describes the design of a mailbox for exchanging information between two 80C31s, using a SC060 H-EPLD
as a "back-to-back" register, and a SC03l H-EPLD as
an arbitration vehicle to control the actions of the
CPUs.

THE SC060 MAILBOX

The SC060 allows for independent clocking of 8 macrocells on each side of the chip, the two clock inputs are
used to clock data from the microcontroller bus into
the chip. To read the data written into the mailbox by
one of the controllers, the RDA- (controller A is reading) or RDB- (controller B is reading) line must be
pulled low by activating the read command (lRD). In
order to avoid spurious read-cycles, the /RD commands from both microcontrollers are logically
"ORed" together with an active high CS-signal (Chip
Select) inside the SC060. The CS-signal for both ports is
derived from address line A1S. Therefore, whenever
A1S becomes a logic "I" (true), the mailbox is activated and ready to take or submit data.
Address range for the mailbox: FOOO Hex to FFFF
Hex
(Upper 12 kbyte)

In this application, the 16 macrocells of the SC060 are
grouped into two sets of 8 so called "ROlF" (register
output with input feedback) primitives to implement
the two 8 bit bus interfaces needed. The grouping is
done according to the following picture.
5C060
WRB

VCC

CSA

RDB

I/OAO

GROUP A
(MICROCONTROLLER A)

I/OBO

1/0AI

I/OBI

I/OA2

I/OB2

I/OA3

I/OB3

1/0A4

I/OB4

I/OA5

I/OB5

I/OA6

I/OB6

GROUP B
(MICROCONTROLLER B)

I/OB7

I/OA7
RDA

CSB

GND

WRA
292016-15

2-139

AB-12

THE 5C031 "MAILBOX CONTROLLER"
To keep the two microcontrollers informed about the
status of their mailbox, the SC031 is programmed to
supply the following signals to both controllers:

/OBFA: ·OUTPUT BUFFER FULL" FOR Me A
/OBFB: ·OUTPUT BUFFER FULL" FOR Me B
/IBEA: "INPUT BUFFER EMPTY" FOR Me A
/IBEB: ·,INPUT BUFFER EMPTY· FOR Me B
/INTA: INTERRUPT TO Me A
/INTB: INTERRUPT TO Me B
The next section will discuss the meanings of these signals in more detail.
Output Buffer Full: This flag is set whenever the controller writes into its own output
buffeL The flag remains valid, until
the second controller has read the
data, The flag is automatically reset to its inactive state when this
read cycle is accomplished.

NOTE:
Both controllers can access (read or write) the mailbox simultaneously.
Input Buffer Empty: This flag indicates that there is no
message in the mailbox. The flag
will become inactive as soon as
one microcontroller places a message for the other one (or vice versa).

Example:
IIBEA
remains
"LOW" until microcontroller B
places a message for controller A
into the mailbox for A. IIBEA
will go "HIGH" as soon as controller B has accomplished its
write cycle, and will not go
"LOW" again until microcontrol~
ler A has read the message.
Interrupt: The SC031 is programmed to supply interrupts to both microcontrollers involved, on
one of the following events.
1. The /OBF flag of the opposite microcontroller becomes active; e.g. if controller A is
placing a message for controller B, controller
B receives an interrupt the same time as
IOBFA becomes valid or vice versa.
2. The IIBE flag of the opposite microcontroller goes active, indicating that this controller has received the message; e.g. if controller B reads the message stored by controller A, its IIBEB flag goes active and controller receives an interrupt indicating that
the buffer is empty.
The signals described above are necessary to accomplish a secure handshake without overwriting messages
accidentally. In addition to that, the SC031 is issuing
the actual write commands for the two register sets inside the SC060. The /WRA and IWRB signals are results oflogical "AND" functions between the appropriate CS- and /WR signals from the microcontrollers.
Therefore, spurious write cycles are unlikely to happen.
NOTE:
This design can also be efficiently implemented in a
single SCBIC EPLD.

2-140

intJ

AB-12

A
AOO-A07
PO

B
Ii!

]I

Ii!

~ ~ 74HCT373 ---..J

~-~~ l r.~

00-07

00-07

AD-A7

AO-A7

f1--

CE OE

ALE
A8-A15
P2

I-

PSEN

I---

027C64

027C64

A

A8-12

OEES

ES OE "

*L--

00-07

00-07

AO-A7

AD-A7

RAM

RAM

~

A15

~

A8-12

- ----'*
~

P80C31BH

]I

74HCT373:J

I -"'~

rv

AOO-A07
PO

OE CE

~

-

I---

I-

-

~

ALE
A8-A15
P2

PSEN

P80C31BH

A

A8-12

RD

WR

A8-12

ES

ES

WR

RD

I Il

RDP3.7
WRP3.6 -

"

A15

II-

RDP3.7
WRP3.6

5C060

~
~

I--

lOA
0-7

lOB A
0-7

ROA
CSA
WA

ROB
CSB
WB

"

-

I-

5C031
WA
' - - WRA
"""--- ROA

RST

--

P3.4
P3.5
P3.2INTO
RESET

r

CSA
OBFA
IBEA
INTA
RST

WB
WRB
ROB
CSB
OBFB
IBEB
INTB

OE

Block Diagram

2-141

f-

I--P3.4
P3.5
INTO P3.2

l

RESET

292016-1

AB-12

5C060 "BACK TO BACK REGISTER"
WB

10AO

lOA 1

I

A

1:....

1

.A

~I"'"

r- ~L

~

.......
-r-

1:....

.....
r- ~

L

-~

_....

_i-

IOA2

1

.A

L

-r-

L

.... -

_i-

IOA3

I

A

L....

-

L .-.... -

_I-

IOA4

IOA5

1

.A

1:....

1 ...

-r-

...

L

L

1""'-

... -

-r-

I""'~

I ...
1:....

-

--

~l -

I

.A

r--I"'"

L

..

lOBI·

...

IOB2

...

IOEl3

...

IOB4

~

~

~

~.

-

~

IOB5

...

IOB6

...

IOB7

....1

--

_I-

IOA7

lOBO

...1

L -- ...

_I-

IOA6

..

L

1""'''''-

J
I-i--

1....-1-

WA

RDA
CSA

~

:<{)-

2-142

RDB
CSB
292016-2

inter

AB-12

5C031 "MAIL BOX CONTROLLER"

WRA
CSA

---oQ"-'"~-~~--------------------c>--- WA
X).----.------~~--IBEB

ROB

OBFA
INTA

RST
INTB
OBFB

ROA

IBEA
CSB
WRB

WB

DE
292016-3

2-143

AB-12

5C060 REGISTER ADF
JURRG
INTEL
March
80C31

STAHL
ZUERICH
27, 1986
MAILBOX MRMORY USING 5C060 / 5C031

1

********************
** RXAMPLI! .ADF **
********************

5C060
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C060
INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813
OUTPUTS: 1087815, IOA7810, IOB6816, IOA689,
rOB5817, IOA588, r084818, rOA487,
rOB3819, IOA386, IOB2820, rOA285,
IOB1821, IOA184, 10B0822, IOA083
NETWORK:
rOB7,DB7
ROlF (DA7,WAC,GND,GND,RDBC)
IOA7,DA7
ROlF (DB7,WBC,GND,GND,RDAC)
ROlF (DA6,WAC,GND,GND,RDBC)
rOB6,DB6
IOA6,DA6
ROlF (DB6,WBC,GND,GND,RDAC)
IOB5,DB5
ROlF (DA5,WAC,GND,GND,RDBC)
rOA5,DA5
ROlF (DB5,WBC,GND,GND,RDAC)
ROlF (DA4,WAC,GND,GND,RDBC)
rOB4,DB4
rOA4,DA4
ROlF (DB4,WBC,GND,GND,RDAC)
rOB3,DB3
ROlF (DA3,WAC,GND,GND,RDBC)
IOA3,DA3
ROrF (DB3,WBC,GND,GND,RDAC)
IOB2,DB2
ROlF (DA2,WAC,GND,GND,RDBC)
IOA2,DA2
ROlF (DB2,WBC,GND,GND,RDAC)
10Bl,DBI
ROrF (DAl,WAC,GND,GND,RDBC)
IOAl,DA1
ROlF (DBl,WBC,GND,GND,RDAC)
10BO,DBO
ROlF (DAO,WAC,GND,GND,RDBC)
rOAO,DAO
ROlF (DBO,WBC,GND,GND,RDAC)
WAC = INP (WA)
RDBC
AND(CSBI,RDBI)
WBC
INP (WB)
RDAC
AND(CSAI,RDAI)
CBBI = INP (CSB)
nRDBI = INP(nRDB)
nRDAI
INP(nRDA)
CSAI
INP(CSA)
RDAI
NOT(nRDAI)
RDBI
NOT(nRDBI)

=
=
=

=

=

RND$

292016-4

2-144

intJ

AB-12

5C060 REGISTER LEF
JUIRG
INTBL
March
80031

STAHL
ZUIRIOH
27, 1986
MAILBOX MIMORY USING 50060 / 50031

1

********************
** IXAMPLI .Llr **
********************

50060
LB Vereion 3.0, Baeeline 17x, 9/26/86
LIF Vera ion 1.0 Baeeline 1.5i 02 Feb '1987
PART:
5C060
INPUTS:
WBel, CSA.2, CSB.14, nRDAell, nRDB.23, WA.13
OUTPUTS:
IOB7e15, IOA7el0, IOB6.16, IOA6e9, IOB5e17, IOA5e8, IOB4.18, IOA4e7,
IOB3119, IOA3e6, IOB2e20, IOA2.5, IOBl.21, IOAl.4, IOBO.22, IOAO.3
NITWORK:
WBC = INP(WB)
WAC = INP(WA)
CUI = INP(CSA)
CSBI = INP(CSB)
nRDAI = INP(nRDA)
nRDBI = INP(nRDB)
ROlr(DA7, WAC, GND, GND, RDBC)
IOB7, DB7
IOA7, DA7
ROlr(DB7, WBC, GND, GND, RDAC)
IOB6, DB6
ROlr(DA6, WAC, GND, GND, RDBC)
IOA6, DA6
ROlr(DB6, WBC, GND, GND, RDAC)
IOB6, DB6
ROlr(DA6, WAC, GND, GND, RDBC)
IOA6, DA6
ROlr(DB6, WBC, GND, GND, RDAC)
IOB4, DB4
ROlr(DA4, WAC, GND, GND, RDBC)
IOA4, DA4
ROIF(DB4, WBC, GND, GND, RDAC)
IOB3, DB3
ROlr(DA3, WAC, GND, GND, RDBC)
IOA3, DA3
ROlr(DB3, WBC, GND, GND, RDAC)
IOB2, DB2
ROlr(DA2, WAC, GND, GND, RDBC)
IOA2, DA2
ROlr(DB2, WBC, GND, GND, RDAC)
lOBI, OBI
ROlr(DAl, WAC, GND, GND, RDBC)
10Al, DAI
ROlr(DBl, WBC, GND, GND, RDAC)
lOBO, DBO
ROlr(DAO, WAC, GND, GND, RDBC)
10AO, DAO
ROIF(DBO, WBC, GND, GND, RDAC)
IQUATIONS:
RDAC
CSAI
nRDAI';

*

RDBC

CSBI

* nRDBI';

IND$
292016-5

2-145

AB-12

5C060 REGISTER UTILIZATION REPORT
Lo,ie Opti.izin, Co.piler UtIlization Report
FIT Version 1.0 Baseline 1.0i 2/6/87
••••• De.i,n i.ple.ented Bueee •• fully
JUBRG
INTIL
March
80C31

STARL
ZUBRICH
27, 1986
MAILBOX MBMORY USING 5C060 / 5C031

••••••••••• *•• *•• *•• *****
*. IXAMPLB .RPT FILB **
**.** •• *****.**********.*

1

5C060
LB Version 3.0, BaBeline 17x, 9/26/85
5C060
WB
CSA
10AO
10Al
10A2
10A3
10A4
IOA5
IOA6
lOA?
nRDA
GND

-

1
- 2
-: 3
-: 4
- 5
- 6
- 7
- 8
-: 9
-: 10
-: 11

-:12

24:- Vee
23:- nRDB
22:- lOBO
21:- lOBI
20:- IOB2
19:- 10B3
18:- IOB4
17 :- IOB5
16:- IOB6
15:- IOB7
14:- CSB
13:- WA

ttINPUTS ..
Na.e

Pin

WB
CSA

Reaouree

MCell ,

PTer.s

MCells

Feeda:
01

Clear

INP
2

Clock
CLKI

INP

9
10
II

12
13

14
15
16
nRDA

II

9
10

INP

II

12
13
14
15
16
GND

12

GND

1
2
3
4

5
6

7
8
9

292016-6

2-146

inter

AB-12

5eoso REGISTER UTILIZATION REPORT (Continued)
10
II

12
13
14
15
16

WA

13

INP

CSB

14

INP

CLK2
I
2
3
4
5
6
7
8

nRDB

23

INP

I
2
3
4
5
6
7
8

24

Vee

Pin

Resource

Vee

**OUTPUTSU
Name

10AO

ROlF

10Al

4

IOA2
IOA3

6

IOU

MCell

•
9

Feeds:

PTerms

MCells

ROlf

10

1/ 8

ROlF

II

1/ B

ROlF

12

1/ B

4

ROlF

13

1/ 8

5
6

IOA5

8

ROlf

14

1/ 8

9

ROlF

15

1/ 8

7

IOA7

10

ROlF

16

1/ B

8

IOB7

15

ROlF

8

1/ 8

16

IOB6

16

ROlF

7

1/ 8

15

IOB5

17

ROlF

6

1/ 8

14

IOB4

18

ROlF

5

1/ 8

13

IOB3

19

ROlF

4

1/ 8

12

IOB2

20

ROlF

1/ 8

II

lOBI

21

ROlf

1/ 8

10

1/ B

9

22

ROIr

Clear

Clock

2

IOA6

lOBO

08

1/ 8

292016-7

All Resources used

UPART UTILIZATIONU
100""
100""
12,,"

Pins
MacroCella
Pter ••

292016-8

2-147

inter

AB-12

5C031 ARBITER ADF
JUI!RG
INTEL
March
BOC31

STAHL
ZUBRICH
28, 1986
MAILBOX MBMORY USING 5C060 / 5C031

********************
** BXAMPLE .ADF **
********************

2
5C031

LB Version 3.0, Baseline 17x, 9/26/B5
PART: 5C031
INPUTS: RST,nWRA,nRDB,CSA,nRDA,nWRB,CSB,nOB
OUTPUTS: WA,nOBFA,nIBEB,nINTA,nINTB,nOBFB,nIBEA,WB
NETWORK:
nWRA = INP(nWRA}
nRDB = INP(nRDB}
RST = INP(RST}
CSA = INP(CSA}
nRDA = INP(nRDA}
nWRB = INP(nWRB}
CSB
INP(CSB}
nOE
INP(nOE}
WRA
NOT(nWRA}
WRB
NOT(nWRB}
RDA
NOT(nRDA}
RDB
NOT(nRDB}
OE = NOT(nOB}
nRST = NOT(RST}
WA = CONF(WAd,YCC}
WAd = AND(CSA,WRA}
WB = CONF(WBd,YCC}
WBd = AND(CSB,WRB}
nRB = NAND(RDB,CSB}
nRA = NAND(RDA,CSA}
nWAd = NOT(WAd}
nWBd = NOT(WBd}
nOBFA,nOBFA
COCF(nOBFAd,OB}
nOBFB,nOBFB = COCF(nOBFBd,OB}
nIBBA,nIBIlA = COCF(nIBBAd,OB}
nIBEB,nIBBB = COCF(nIBBBd,OB}
nINTA = CONF(nINTAd,OE}
nINTB = CONF(nINTBd,OE}
nINTAd
AND(nOBFA,nIBBA}
nINTBd
AND(nOBFB,nIBBB}
nOBFBd
NAND(nRA,nIBBA,nRST}
nOB FAd
NAND(nRB,nIBEB,nRST}
nIBBBd
NAND(nWAd,nOBFA}
nIBBAd
NAND(nWBd,nOBFB}
BND$

292016-9

2-148

inter

AB-12

5C031 ARBITER LEF
JUERG
INTEL
March
80C3l

STAHL
ZUERICH
28, 1986
MAILBOX MEMORY USING 5C060 / 5C03l

********************
** EXAMPLE .LEF **
********************

2

5C03l
LB Version 3.0, Baseline l7x, 9/26/85
LEF Version 1.0 Baseline 1.5i 02 Feb 1987
PART:
5C03l
INPUTS:
RST, nWRA, nRDB, CSA, nRDA, nWRB, CSB, nOE
OUTPUTS:
WA, nOBFA, nIBEB, nINTA, nINTB, nOBFB, nIBEA, WB
NI!TWORK:
RST = INP(RST)
nWRA = INP(nWRA)
nRDB = INP(nRDB)
CSA = INP(CSA)
nRDA = INP(nRDA)
nWRB = INP(nWRB)
CSB = INP(CSB)
nOE = INP(nOE)
WA = CONF(WAd, VCC)
nOBFA, nOBFA = COCF(nOBFAd, OE)
nIBEB, nIBEB = COCF(nIBEBd, OE)
nINTA = CONF(nINTAd, OE)
nINTB = CONF(nINTBd, OE)
nOBFB, nOBFB = COCF(nOBFBd, OE)
nIBEA, nIBEA = COCF(nIBEAd, OE)
WB = CONF(WBd, VCC)
EQUATIONS:
WBd = eSB
nWRB';

*

nIBI!Ad

eSB

*

nWRB'

+ nOBFB';

nOBFBd
+

* eSA'
* RST'
* RST' * nRDA) , ;

(nIBEA
nIBEA

nINTBd

nOBFB

* nIBEB;

nINTAd

nOBFA

* nIBEA;

nIBEBd

eSA

* nWRA'

+ nOBFA';

OE

= nOB'

nOB FAd
WAd

j

(nIBEB
+ nIBEB
eSA

*

RST'

* eSB'

* RST' * nRDB)' ;

* nWRA';

END$
292016-10

2-149

5C031 ARBITER LEF (Continued)
LogIc Optiaizlng Coapiler UtilIzation Report

FIT VerSl0n 1.0 Baseiine 1.01 2/6/87

*****
.JUIRG
INTJ!L
March
80C31

Design iaple.ented successfully
STAHL
ZUBRICH
28, 1986
MAILBOX MBMORY USING 5C060 / 5C031

*************************
** EXAMPLB .RPT FILl! **
*************************

2

5C031
LB Version 3.0, Baseline 17x, 9/26/85
5C031

-

GND
I
GND - 2
nOI! - 3
CSB - 4
nWRB
5
nRDA
6
7
CSA
nRDB - 8
DWRA - 9
GND -: 10

-

20:- Vee
19:- NB
18:- NA
17: - nOBFB
16:- nINTB
15:- nINU
14:- nIBBS
13:- nOBFA
12:- nIBEA
11: - RST

,*INPUTS,*
Feeds:
Naae

Pin

Resource

nOB

3

INP

MCe11

II

PTer ••

MCells

01

Clear Preset

3
4
5
6
7
8

CSB

4

INP

1
7
8

nWRB

5

INP

I

8
niDA

6

INP

3

CSA

7

INP

2
3
6

DRDB

8

INP

7

nWRA

9

INP

2
6

GND

10

GND

RST

11

INP

Vee

20

Vee

3
7
I

2
292016-11

2-150

AB-12

5C031 ARBITER UTILIZATION REPORT
UOUTPUTS**
Na.e

Pin

Resource

nIBEA

12

COCF

MCell

,

PTera.

a

2/ a

MCell.

Feed.:
01

Clear Preset

3

5

nOB FA

cocr

13

7

2/ a

5
6

nIBBB

cocr

14

6

2/ a

nINTA

15

CONI'

5

1/ a

nINTB

16

CONI'

4

1/ a

nOBFB

17

cocr

3

2/ a

WA

la

CONI'

2

WB

19

CONI'

4
7

4

a

1/ a
1/ a

**UNUSBD RESOURCES**
Na.e

Pin

Resource

MCell

PTer ••

1
2
UPART UTILIZATION**
aa_
100_
la_

Pin.

MacroCell.
pter••
292016-12

2-151

intJ

AB-16

APPLICATION
BRIEF

October 1988

Atypical Latch/Register
Construction in EPLDs

THOM BOWNS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292031-003
2-152

intJ

AB-16

in this Ap brief, the "!" operator is used to signify inversion). The schematic of the RS latch is shown in
Figure lao

ATYPICAL LATCH/REGISTER
CONSTRUCTION IN EPLDs
Though Intel's EPLDs include many of the typical
latch and register types, some logic designs require register or latch configurations not directly supported in
the current EPLDs. In many cases these register and
latch configurations can be generated using the logic
array and combinational feedback. A "latch" is defined
as a level-triggered, flow-through type such as the
74373, and a "register" is defined as an edge-triggered
flip-flop such as the 7474.

Since cross coupled logic is not supported in EPLDs,
we must convert the equation to a single term with
feedback.
aD, OF = COCF (a, VCC)

0= S + !R * OF;

where QF is the feedback from Q output.
This circuit can be implemented in an EPLD I)lacrocelL Where combinational feedback is not supported,
I/O feedback will suffice. The schematic of this implementation is shown in Figure lb.

This application brief will detail the construction of a
D-type latch, an RS latch and a D flip-flop using combinational logic and feedback. Also discussed is the
construction of an RS flip-flop, a JK flip-flop and a T
flip-flop using registered logic and feedback.

With the RS latch, the inputs are normally low. A logical one on S sets Q to I, and a one on R resets Q to a O.
Logical ones on both inputs simultaneously cause the
output to remain at a high level since S takes precedence over R in this implementation.

The RS latch is the simplest latch configuration. The
equations for it are as follows: QB = !(Q + S), Q =
!(QB + R) where Q is the output of one NOR gate, and
QB is the output of the other (Note: as a convention

~
NOR2

R

0

OS
S

NOR2

292031-1

(a)

INP

s--~~------------,
INP

-COCF~

>-£:>;..1- 00

292031-2

(b)

Figure 1. RS Latch Implementation In a) Discrete Gates and b) EPLD Logic

2-153

inter

AB-16

QD, QF = COCF (Q,VCC)

Another latch is the 74373 type, or D latch. This latch
works by either enabling input data to appear at the
output, or by holding the output to the last input data
state. Its equation is this: QB = !(!(!D*E)*Q), Q =
!(!(D*E)*QB). Again, Q is the output of one NAND
gate, and QB is the output of the other. Figure 2a
shows this version of the design.

Q

= D ' E + !E ' QF;

QF is the feedback from the COCF. In this circuit,
when E is high, data flows through transparently.
When E is brought low, data is latched. When using
input feedback, care must be taken when tri-stating the
output as data will no longer be latched. The EPLD
implementation is given in Figure 2b.

Again, we must convert to an EPLD-type equation and
schematic:

O_I-of--I

Q

E-'-'--I
NAN02

292031-3

(a)

O'-O---i,

----.

E-'L.._-

COCFI
I

~-C>r--Qo

292031-4

(b)
Figure 2. Implementation of a D Type Latch Using a) Discrete Gates and b) EPLD Logic

2-154

intJ

AB-16

This latch can be cascaded with a second latch to produce an edge triggered, master/slave D flip-flop, using
combinational logic. The flip-flop is a solution to using
asynchronous clocking, preset and clear functions when
they aren't supported. Also, if an I/O conflict exists
within a macrocell group when using registered logic,
this design will fit since it uses combinational logic.
Figure 3 shows the schematic for this design.
This design does consume two macrocells, but in many
cases, that isn't a problem.

The boolean equation of the D flip-flop is this:
= COCF (Q,VCC)
= NOCF (Y)

QD,QF
YF

Y = D
Q

* !CLOCK +

YF

* CLOCK;

= YF * CLOCK + QF • !CLOCK;

Q is the flip-flop output and Y is the first latch output.
Data is latched in to the second latch on the low-going
edge of clock, and is clocked out to Q on the high-going
edge of clock.

INP

0--0---1

INP

CLOCK

-.c>-....~
YF

----.
COCF'

~~~ ~~~'--QO

292031-5

Figure 3. Combinational Logic Implementation of a D Flip-Flop

2-155

AB~16

Preset and clear can be added into the equations as
well:
QD,QF = COCF (Q,VCC)
YF = NOCF (Y)
Y = D • !CLOCK

+

, When the CLEAR TERM is logically true, Q is asynchronously cleared to O.
The PRESET TERM, takes priority over the CLEAR
TERM.
This schematic is shown in Figure 4.

YF • CLOCK;

Q = YF • CLOCK * ! (CLEAR TERM) +
(PRESET TERM) +
QF • !CLOCK • ! (CLEAR TERM);

When the PRESET TERM is logically true, Q is asynchronously set to 1.

Due to the nature of the design, input delays plus array
delays plus feedback delays must be added and used to
determine a maximum operating frequency. In this example, tIN + tAD + tCF + tAD = 113 ns for a
-65 5C121, leaving a maximum frequency of 8.8
MHz.

INP

D--~~------------~.

.

INP
CLOCK--~>---------~~--~.

YF'

____ .
COCF'.

r-'-~ ~-f[~'--OD
INP
CLEAR TERM -C>--I ~~""---II--IA
INP
PRESET TERM --~>-----------'

----_ ..

OF'

Figure 4. D Flip-Flop with Added Preset and Clear Terms

2-156

292031-6

AB-16

Other useful workarounds involve D registers and logic
in constructing RS, JK and T flip-flops, for use in
EPLDs not supporting these configurations. The RS
flip-flop is simply the RS latch discussed earlier coupled to registered feedback.

The JK flip-flop is another useful and easily implemented register:
.

QD,QF = RORF (Q,CLOCK,GND,GND,VCC)

When J = K = I, QD toggles to opposite state on next
clock trigger. When J = K = 0, QD remains the same.
When J does not equal K, QD will follow J on next
clock trigger. The schematic is shown in Figure 6.

Q = 5

+ QF'

!R;

Normally, Sand R will remain low. When S is brought
high, QD will become I on the next clock trigger edge.
When R is brought high, QD will become 0 on the next
clock trigger edge. The schematic is given in Figure 5.

QD,QF = RORF (Q,CLOCK,GND,GND,VCC)
Q = J • !QF

INP
eLoeK-C~-----------,

INP

s-~~------------,
INP

R---ID-t '>()--I.

GND

+

!K • QF

Vee

____ .
RORF',
>--G>I--OD
292031-7

Figure 5. EPLD Implementation of an RS Flip-Flop

INP

CLOCK--<:>----------------------,
INP

___ e.

J-~~-------I.

RORF'
>-t:>r'-OD
INP

K---ID-t XH..-r
292031-8

Figure 6. EPLD Implementation of a JK Flip-Flop

2-157

intJ

AEJ.16

The T flip-flop is also easily constructed:

register clock), as lbng as the minimized logic equations
resulting do not exceed the macrocells p-term count.

OD,OF = RORF (O,CLOCK,GND,GND,VCC)
T • I OF + IT· OF;

o=

When T is high, QD will toggle to opposite state on
next trigger. When T is low, ,QD will remain the same.
Figure 7 shows the T flip-flop design schematic.
Each of these designs uses a minimum number of pterms; adding p-tenns is possible to the limit of the
macrocell being used. It is possible to substitute an entire logical expression for each input listed (except

For example, consider using the J-K register. Setting
J=A*B"C+DandsettingK=E"IF*IO+
H + I then the minimized p-tenn count will expand
from two p-terms to five p-terms, which would still be
okay within a macrocell with more than five p-tenns.
Using logic ga1;es and combinational or, registered feedback, one can easily implement many types of latches
and registers. Regardless 'of the EPLD'type, there exists
the resources to implement any of the discussed circuitry.

GND

INP

CLOCK:-OC>----.....,
INP
T'-D-~

___ e.
RORn

~-r'":h'-QD

292031-9

Figure 7. Implementation of a T Flip-Flop

2-158

inter

AB-22

APPLICATION
BRIEF

October 1988

5C032-25 vs. 16V8-25:
A Device Comparison

DANIEL E. SMITH
LILIYAS KOUMIS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292051-001
2-159

AB-22

INTRODUCTION

ARCHITECTURE

This application brief compares the Intel 5C032-25
EPLD with the Lattice 16V8-25 GAL', showing how
the 5C032 is superior to the 16V8 for low-power CMOS
PLD applications. The compatibility between the two
devices is high enough that the 5C032-25 can be
dropped directly into the 16V8-25 socket for the majority of applications. Areas where the 5C032 is not compatible are also noted. Information in the brief is based
on the Intel 5C032 Data Sheet (order number: 290155002 or later) and the Lattice 16V8 Data Sheet (undat, ed).

Architecturally, the 5C032 is a superset of the 16V8.
Any architectural configuration supported by the 16V8
can be implemented in the 5C032. There are a number
of configurations, however, supported by the 5C032
that cannot be implemented in the 16V8 architecture.
As shown in Figure 1, both the 5C032 and 16V8 are 20pin devices with 8 I/O macrocells. The two devices are
pin compatible. All inputs and VOs are on the same
pins. Macrocells in the devices support registered and
combinatorial modes. (Refer to the discussions on "Inputs" and "Macrocells" later in this brief.)

The comparison is divided into the following areas:
• Technology
• Architecture
• Specifications
• Deveiopment Support

TECHNOLOGY
The 5C032 is produced on Intel's CHMOS EPROM
process and is, therefore, UV erasable. The 16V8 is produCed on a CMOS EEPROM process and is electrically
erasable. Because neither device will typically be erased
and reprogrammed in-circuit, this difference is negligible. The fuse patterns for the two devices are different.
Therefore, the JEDEC files are not compatible.

The major architectural difference between the 16V8
and the 5C032 lies in flexibility. During programming,
the 16V8 uses 10 bits to internally configure all 8 macroce11s. 1 bit (SYN) is a global "register/combinatorial"
mode bit. A second bit (AO) is also a global bit that
controls an OE mux. These two bits provide global selection of modes but limit the independent control of
macrocells. Each macrocell has an individual configuration bit (ACn) to give macrocells some independent
control. In contrast, the 5C032 provides 2 bits per macroce11 to independently configure each macrocell (16
bits total). This gives the 5C032 greater flexibility than
the 16V8. Another difference concerns the state of macrocell registers on power-up. 5C032 registers are low on
power-up, while the 16V8 registers are high. This difference may be important in some applications.

5,C032

16V8

INPUT/ClK

VCC

10/CK

INPUT

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/o

11

INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GND

12

F6

13

F5

14

F4

15

F3

16

F2

17

Fl

18

FO

GND

I/VPP

VCC
F7

292051-1

I/OE
292051-2

Figure 1. 5C032 and 16V8 Pinouts

"GAL is a r!39istered trademark of Lattice Semiconductor Corporation.

2-160

inter

AB-22

Inputs

1/0 Configurations

The 5C032 has 9 dedicated inputs and one CLK/INP
pin. The 16V8 has 8 dedicated inputs, one global CLK/
INP pin, and one global OE/INP pin. The CLK inputs
are both on pin 1. The global OE on the 16V8 (pin 11)
corresponds to an input on the 5C032. This pin can be
used on the 5C032 as a global OE. On the 5C032, however, any input can function as the global OE. The
16V8 does not provide this flexibility.

Table I shows the configurations supported for both
devices. Note that most 16V8 macrocell configurations
have some restriction on use.

On both devices, the CLK pin can function as an input
to the logic array when implementing combinatorial
logic only (no registers). Pin II (OE/INP on the 16V8)
can also be used as a dedicated input in combinatorial
mode. Pin lion the 5C032 can be used as an input in
both registered and combinatorial mode.

Macrocells
Each 16V8 macrocell is fed by 8 p-terms. One of the
eight p-terms can be used to control the OE signal for
combinatorial macrocells. When this is done, only 7 pterms remain as inputs to the macrocell. Depending on
the configuration, the OE can also be tied to VCC or
GND, or can be globally driven by pin II.
5C032 macrocells are fed by 8 p-terms. A ninth p-term
is provided for independent OE control. Thus the
5C032 macrocell can implement equations with more
p-terms than the 16V8. All options are available independently for all macrocells, which makes the device
more flexible than the 16V8.
The 16V8 is placed in registered or combinatorial mode
by a global architecture bit. Registered mode means pin
I is global CLOCK and pin II is global OE. Registered
macrocells cannot use product terms to independently
enable outPllts; only the global OE can be used. Macrocells can be configured as combinatorial outputs when
the device is in registered mode, but only 7 p-terms are
available as macrocell inputs. Buried registers can be
emulated on a global basis by disabling the global OE
and using the feedbacks only, but buried registers cannot be mixed with output registers in the same design.
In the 5C032, registers are selected on a macrocell-bymacrocell basis. Any supported configuration can be
implemented on any other macrocell. Independent OE
p-terms are available with registers (see Figure 2). A
global OE can be implemented by programming all OE
p-terms the same. Buried registers can also be selected
on a macrocell basis. These differences make the 5C032
much more flexible than the 16V8.

2-161

Table 1. 5C032/16V8 Configurations
5C032

16V8 (Comb.)

16V8 (Reg.)

Input

Input

Input

Input on unused
Macrocell

Input on unused
Macrocell

Input on unused
Macrocell

Comb. Out
(no feedback)

Comb. Out
(no feedbackOE = VCC)

Comb. Out
(no feedback7 p-terms)

Comb. Out
(input feedback)

Comb. Out
Comb. Out
(input feedback- (input feedback7 p-terms)
7 p-terms)

Register (with
feedback-p-term
controlled OE)

nla

Register (with
feedback-global
OEonly)

Register (no
feedback-p-term
controlled OE)

nla

Register (no
feedback-global
OEonly)

Buried Register
nla
(any register)
p-terms = Product terms
nla = not available

Buried Register
(global only)

Table 2 summarizes the architecture comparison:
Table 2. 5C032/16V8 Architecture Comparison
Device Feature

of Pins

5C032

16V8

20

20

9

8/9

Total Inputs

16

16

Macrocells

8

8

Synch. Clocks

1

Logic P-terms/Macrocell

8

8/7(1)

1

0/1(2)

#

Dedicated Inputs

OE P-Terms/Macrocell

1

GlobalOE

1 (3)

1

Device Erase

UV

Electrical

Register Output State
low
high
On Power-Up
1. When using a p-term to drive the OE signal for a macrocell, the 16V8 can only use 7 p-terms as macrocell inputs.
2. 16V8 registers must use the global OE signal. Macrocells programmed for combinatorial mode can use a pterm. In contrast, the 5C032 provides a p-term for all macrocells in all configurations.
3. Global OE is implemented on 5C032 by driving all OE pterms by pin 11.

AB-22

SC032 Registered Macrocell
GLOBAL

ClK
REGISTERED
OUTPUT

IN

FBK

292051-3

16V8 Registered Macrocell
(Device in Registered Mode)
GLOBAL

GLOBAL

ClK

OE
REGISTERED
OUTPUT

IN

D

Q

FBK

292051-4

Figure 2. SC032 and 16V8 Registers

SPECIFICATIONS
The following tables describe differences between the
SC032 and the half-power 16V8 in three different tables: (I) Absolute Maximum Ratings, (2) D.C. Characteristics, and (3) A.C. Characteristics.

standby power than the half-power 16V8. For low power applications where the output drive current requirements are 4mA or less, the Intel SC032 is an ideal replacement for the l6V8. The l6V8, with outputs capable of sinking up to 16mA, is better suited to applications that require higher current sink.

D.C. Characteristic Differences

A.C. Characteristics Differences

The Intel SC032-2S meets or exceeds all but two 16V8
D.C. specifications (short circuit current and lod. Due
to the advanced CMOS technology, the Intel SC032
consumes one-third the power of the half-power l6V8.
It also consumes almost three orders of magnitude less

The Intel SC032-2S meets all but one 16V8 A.C. specification (Output EnablelDisable). Thus. the Intel
SC032 is an ideal replacement for the 16V8 in most
applications.

2-162

inter

AB-22

Absolute Maximum Rating Differences
5C032-25

Parameter

16V8·25

Units

Symbol

Min

Max

Symbol

Min

Max

Supply Voltage

Vee

-2.0

7.0

Vcc

-0.5

7.0

V

Storage Temp.

T stg

-65

+150

Tstg

-65

+125

C

Ambient Temp.

Tamb

-10

+85

TA

0

+75

C

D.C. Characteristics(1)
5C032-25

Parameter
Symbol

Min

16V8·25
Max

Symbol

Min

Units
Max

Supply Current

Icc

30

Icc

90

rnA

Short Circuit Current

Isc

-10

los

-130

rnA

Standby Current

ISB

0.1

ISB

70

rnA

Output Low Voltage

VOL

0.45
IOL=4

VOL

0.5
IOL =16

V
rnA

Output High Voltage

VOH

2.4
IOH=-4

VOH

2.4
10H= -3.2

V
rnA

Input High Voltage
V
2.0
2.0
V,H
Vcc+ 0.3
V,H
Vcc+ 1
..
1. All D.C. Characteristics are compared to the Half-Power GAL 16V8. A Comparison to the Full-Power GAL 16V8 would
show that power consumption is twice that of the Half-Power GAL 16V8.

2-163

AB-22

A.C. Characteristics
16V8-25

5C032-25

Parameter
Symbol

Min

Max

Symbol

Min

. Units
Max

Input to Active Out

tpo

25

tOVOV1

25

ns

P-term Enable to Out Enable \

tpzx

25

tOVOV2

25

ns

P-term Disable to Out Disable

tpxz

25

tOVOZ2

25

ns

OE-pin Enable to Out Enable

tpzx

25

tGHOZ2

20

ns

OE-pin Disable to Out Disable

tpxz

25

tGHOV

20

ns

Clock High to Output Valid

tco

15

tCHOV

15

ns

Input Setup Time

tsu

20

tovCH

20

ns

Input Hold Time

tH

0

tCHDX

0

ns

Clock Low

tCl

10

tCHCl

15

ns

Clock High

tCH

10

tClCH

15

ns

tCNT

30

(1 )

Register Output Fdbk
to Register Input (Internal)

ns

Max Count Frequency
33.3
33.3
MHz
(2)
fCNT
..
1. lattice does not specify this parameter. Intel specifies this parameter strictly for calculation of fCNT. fCNT IS the count
frequency associated with designs that use feedback signals, e.g., counters.
2. lattice does not specify an equivalent. However, this value can be determined using either "register output feedback to
register input" delay, or the "clock period", whichever is the larger. Since "register output feedback to register input" delay
is unknown, the indicated frequency value assumes the clock period (tCHCl + tClCH = 30 ns) is the larger of the two
parameters.

DEVELOPMENT SUPPORT

SUMMARY

Both the 5C032 and the 16V8 are supported by ABEL
and can be programmed on the Data I/O LOGICPAK
and UNISITE programmers. The 5C032 is also supported by iPLDS II (Intel Programmable Logic Development System) using the PCCP PC-based programmer and by iPLS II (Intel Programmable Logic Software) using either the PC-based programmer or the
iUP-200A/20IA Programmer. The 16V8 is also supported on the Data I/O Model 60 programmer.

The 5C032-25 provides a low-power upgrade to the
16V8-25 for most applications. If your application requires higher density devices, or fast programmable devices for specific applications, contact your local Intel
sales office.

2-164

inter

APPLICATION
NOTE

AP-271

April 1986

Applying The 5C121 Architecture

JIM DONNELL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292008-001
2-165

AP-271

INTRODUCTION
Intel's 5Cl21 Erasable Programmable Logic Device
represents a new breed in the world of programmable
logic. With gate densities approaching those of gate arrays and a reconfigurable architecture, the logic designer is freed from choosing between scores of generic programmable logic to perhaps find an acceptable match
for his or her design needs. Adding to the list of benefits
is the fact that the 5CI21' is erasable. Now sections of
the design can actually be programmed and tested in
the device - without sacrificing a part to the circular
file. In addition, there is no longer a need to generate
test vectors to qualify the programming of the parts.
EPLDs are erasable and therefore 100% testable at the
factory.

OBJECTIVE
The purpose of this application note is to demonstrate
the architectural options of the 5C121 by designing a
digital crosspoint switch. Conceptually, a digital crosspoint switch switches data from any input to any output. Figure 1 shows a block diagram of a bytewide
crosspoint switch.

include registered or combinational output. In' addition,
each output may be fed back into the array in both the
true and complement version. For a more complete description of the 5Cl21 architecture the reader is referred to the 5Cl21 data sheet.

COMBINATIONAL FEEDBACK
Feedback in logic designs is used for a variety of reasons. Combinational feedback in the 5C121 is often
used to reduce the number of product terms feeding one
Macrocell. Though the 5Cl21 has Macrocells that can
accept up to 16 product terms, all Macrocells are not
that wide.
Let's look at an example. Equation 1 represents one of
the eight Boolean expressions necessary to implement a
digital crosspoint switch. Logically, this expression selects one of eight input signals (10-17), and routes that
signal to QO. Data bits DO, Dl, and D2 select one of the
eight input lines. In this case, data bits !D3, !D4, and
!D5 select output QO. (The exclamation point is used to
indicate a logical complement of the signal.) Equations
for Q 1 through Q7 are very similar and will be discussed later.

ao =
10-17

QO-Q7
DIGITAL
CROSSPOINT
SWITCH

( 10
11
+ 12
+ 13
+ 14
+ 15
+ 16
+ 17

+

x

x
X

x
x
x
x

x

!02
102
ID2
102
D2
02
02
02

X !01
101
X D1
x 01
x !01
x !01
x 01
x D1

x

x

x
x
x
x
x
x

x

SELECTEa =10 x !D2 x
+ 11 x !02 x
+ 12 x 102 x
+ 13 x !02 x
+ 14 x 02 x
+ 15 x D2 x
+ 16 x D2 x
+ 17 x D2 x

030405
OUTPUT SELECT
292008-1

Figure 1. Functional Diagram of a Digital
Crosspoint Switch

This design will employ features such as: registered output with registered feedback, combinational feedback,
input latches, buried registers, and dual clock options.
The digital crosspoint switch in this design can route
data from one of eight inputs to one of eight outputs in
a single clock cycle. Options for holding the deselected
outputs at previous levels, latching inputs, and fitting
cousiderations are explored.

THE BASIC ARCHITECTURE
The 5C121 contains -28 Macrocells, 12 dedicated inputs, 24 programmable I/O lines, and two clocks input
pins. Inputs may be flow through, or latched on the
rising or falling edge of either clock. Output options

!OO
DO
!DO
DO
!DO
DO
100
DO)

x

105

!D1 x !DO
!D1 x DO
01 x !OO
D1 x DO
101 x !OO
!D1 x DO
D1 x !DO
D1 x DO;

x

!04

x

!03; (1)

(2)

Equation 2 contains the terms that 'Will be common to
all eight output equations. Both equations in this case
contain eight product terms. By treating equation 2 as
one common signal and routing that signal through
combinational feedback, we can reduce the number of.
product terms in equations QO thru Q7 to one p-term
each. The advantage is that the outputs can now be
. placed in any of the 24 I/O Macrocells available in the
5Cl21. In additi,on, the 5Cl21 contains four buried registers. (Buried registers have no output and are used
solely for feedback.) If a 1;uried register is available,
iPLDs (Intel's Programmable Logic Development System) will automatically assign the No Output - Combinational Feedback function to a buried register. This
increases the flexibility for pin assignments and makes

2-166

inter

AP-271

COMBINATIONAL FEEDBACK
(Continued)

p-terms available in case a design change is needed.
Equations 3 thru 10 reflect this improvement.
00 = SELECTEO

x

!D5

x

!D4

x

!D3;

(3)

01 = SELECTEO

x

!D5

x

!D4

x

D3;

(4)

02 = SELECTEO X !D5

x

D4

x

!D3;

(5)

03 = SELECTEO

x

!D5

x

D4

x

D3;

(6)

04 = SELECTEO

x

D5

x

!D4

x

!D3;

(7)

05 = SELECTEO

x

D5

x

!D4

x

D3;

(8)

06 = SELECTEO

x

D5

x

D4

x

!D3;

(9)

07 = SELECTEO

x

D5

x

D4

x

D3;

(10)

REGISTERED FEEDBACK
Registered feedback is also employed in a variety of
applications such as counters and state machines. In
this particular example, the registered feedback signal
can be used to hold the deselected outputs of the switch
at their previous level until that output is selected
again. This is accomplished by simply "ANDing" the
feedback signal with the inversion of the output select
signal. The result is then "ORed" with the equation for
the given output. Holding the previous output might be
useful in control applications or when interfacing to
slow peripherals. Equations II thru 18 are the result.
00

=

SELECTEO x !D5 x !D4
x !D3) x OO-fdbk;

x

!D3

+

!(D5

x

!D4
(11)

01 = SELECTEO x !D5 x !D4
x D3) x 01-fdbk;

x

D3

+

!(!D5

x

!D4
(12)

02 = SELECTEO x !D5 x D4
x !D3) x 02-fdbk;

x

!D3

+

!(!D5

x

D4
(13)

03

=

SELECTEO x !D5 x D4
x D3) x 03-fdbk;

x

D3

+

!(!D5

x

D4
(14)

04

=

SELECTEO x D5 x !D4
x !D3) x 04-fdbk;

x

D3

+

!(D5

x

!D4
(15)

05

=

SELECTEO x D5 x !D4
x D3) x 05-fdbk;

x

D3

+

!(D5

x

!D4
(16)

06

=

SELECTEO x D5 x D4
x !D3) x 06--fdbk;

x

!D3

+

!(D5

x

D4
(17)

07

=

SELECTEO x D5 x DR
x DE) x 07-fdbk;

x

D3

+

!(D5

x

D4
(18)

Equations II thru 18 are all that are necessary to implement a digital crosspoint switch with the output
hold feature. Each equation contains only four product
terms when written in the expanded form and could
therefore fit into any Macrocell in the 5C121. The appendix contains the report and ADF files generated by
the iPLDs software.

TIMING ANALYSIS
Figure 2 shows the internal delay paths associated with
this design in the 5CI21. The frequency at which the
5C121 may be clocked can be determined by examining
the internal delay elements of the 5C121. These include
the input delay (Tin), two array delays (Tad), and the
combinational feedback delay (Tct). Table 1 gives the
simulation data for each of these paths in a 5CI21-50.

--o+-----Tad----~I

ARRAY

-Tad

Trd-i--Tod--I

ARRAY

REG OUTPUT

~--------Trl

Figure 2. Crosspoint Delay Path

2-167

.1

292008-2

inter

AP-271

TIMING ANALYSIS

bits could be switched per cycle. Figure 3 shows the
timing diagram for this configuration of the 5C121 digital crosspoint switch. Included in the appendix is the
Advanced Design File (AD F),. Logic Equation File
(LEF), and Utilization report generated by Intel's Programmable Logic Software (iPLS) for this design.

(Continued)

Table 1. 5C121-50 Simulation Data
Model
Parameter

Delay (ns)

Tad

38

Trd

7

INPUT LATCHES

Tod

8

Tin

10

Tie

8

Trf

5

Tef

5

One point must be raised about Figure 3. Notice that
the time allowed for external data set-up is only 17 ns.
Therefore, 17 ns after the rising edge of the clock, data
must be stable and remain stable at the input pins until
the next clock pulse. In most systems this would be a
very stringent requirement. Fortunately the 5C121 has
the ability to latch the data at the input pins with 7475
type transparent latches. Employing this feature eases
the data set-up requirement as shown in Figure 4.

The sum of the delays before the register input equal
the set-up time Tsu with reference to the internal clock.
By substracting the input clock delay Tic we shift the
reference to the external clock pin. The set-up time
with reference to external signals is shown in equation
19. Inverting this signal yields the maximum clock frequency, fmax. The maximum clock frequency is shown
in equation 20.
Tsu = Tin

+

2Tad

+

Tcf

Tic;

(19)

fmax = 1 Tsu

(20)

Therefore, this configuration of the 5C121-50 could be
clocked at 10 MHz, allowing a data transfer rate of 10
Mbits/second. By paralleling six 5C121s together, eight

I'

SUMMARY
The flexible architecture of the 5C 121 gives the designer a variety of options for input and output configurations. Inputs may be latched to ease system timing requirements. Outputs may be clocked for synchronous
systems or fed directly out as asynchronous signals.
Feedback can be used to reduce product term requirements, to save present state information for state machines and counters, or simply to hold deselected outputs as shown in this example. Imagine the possibilities.
J. R. Donnell
PLDO Applications

'I

lOOn.

elK
INPUTS~''-

T.u (83NS)
__________________________
INPUT STABLE

17n.

J

'I'"-X
__-J·''-____________________--'

-

DATAOUT:::::::::::::::::::::::::::::::~~~:-~K::::JD~A~T!A~O~U~T~V~A~l~ID~::::
-Tcol
(Tcol = Tic + Trd + Tod)
292008-3

Figure 3. Crosspoint Timing Diagram

2-168

inter

AP-271

I'
\.

ClK

.I

lATCHED INPUTS

x:

X

.1
X

Tou (83NS)

17no

INPUT STABLE

r---\

lATCH ENABLE

DATA TO PINS

'I

lOOns

EXTERNAL DATA SET-UP

DATA STABLE

X

l",,:j

DATA OUT

X,

DATA OUT VALID

(Teol = Tie + Trd + Tod)
292008-4

Figure 4. Crosspoint Timing Diagram with Input Latches

2-169

inter

AP-271

APPENDIX
ADF File
o
5C121
Oigital C~osspoint Switch
LB Ye~sion 3.0, Baseline 17x, 9/26/85
PART: 5C121
INPUTS: 100@37,IOl@36,102@35,103@34,104@8,105@9,106@10,107@11,IIO@33,ll1@32
,112@31,113@30,114@29,115@28,116@27,117@26,CLK@38,OO@2,Ol@3,02@4,03@5
,D4@6,05@7,ILE@1
OUTPUTS: QOO@12,QOl@13,Q02@14,Q03@15,Q04@16,Q05@17,Q06@18,Q07@19,QIO@24,Qll@23
,Q12@22,Q13@21
NETWORK:
QOO,QOOFBK
RORF (QOOO,CLK,GNO,GND,YCC) % BIT 0 OUTPUTS %
QOl,QOlFBK
RORF (QOIO,CLK,GNO,GNO,YCC)
Q02,Q02FBK
RORF (Q020,CLK,GNO,GND,YCC)
Q03,Q03FBK
RORF (Q030,CLK,GNO,GNO,YCC)
Q04,Q04FBK
RORF (Q040,CLK,GNO,GNO,YCC)
Q05,Q05FBK
RORF (Q050,CLK,GNO,GND,YCC)
Q06,Q06FBK
RORF (Q060,CLK,GND,GND,YCC)
Q07,Q07FBK
RORF (Q070,CLK,GNO,GND,YCC)
QI0,QI0FBK
RORF (QIOD,CLK,GND,GND,YCC) % 4 OF THE 8, BIT 0 OUTPUTS%
Qll,QllFBK
RORF (QIID,CLK,GND,GND,YCC)
Q12,Q12FBK
RORF (Q12D,CLK,GND,GNO,YCC)
Q13,Q13FBK
RORF (Q130,CLK,GND,GND,YCC)
CLK = INP (CLK)
05 = LINP (05,ILE) % OUTPUT SELECT CONTROL BITS %
ILE = INP (ILE)
D4
LINP (04,ILE)
03
LINP (03,ILE)
D2
LINP (02,ILE) % INPUT SELECT CONTROL BITS %
01
LINP (Ol,ILE)
DO
LINP (OO,ILE)
100
LINP (IOO,ILE)
101
LINP (IOl,ILE)
102
LINP (102,ILE)
103
LINP (103,ILE)
104
LINP (104,ILE)
105
LINP (105,ILE)
106
LINP (106,ILE)
107
LINP (107,ILE)
110
LINP (II0,ILE) % INPUTS FOR BIT 1 SWITCH %
III
LINP (ll1,ILE)
112
LINP (112,ILE)
113
LINP (113,ILE)
114
LINP (114,ILE)
115
LINP (115,ILE)
116
LINP (116,ILE)
117
LINP (117,ILE)
SELECTEQOF = NOCF (SELECTEQO)
SELECTEQIF = NOCF (SELECTEQl)
EQUATIONS:
QOOO
SELECTEQOF*!05*!04*!03
+ !(!05*!04*!03)*QOOFBK;
QOID
SELECTEQOF*!05*!04* 03
+ !(!05*!04* 03)*QOIFBK;
Q02D
SELECTEQOF*!05* D4*!03
+ !(!05* 04*!03)*Q02FBK;
Q03D
SELECTEQOF*!05* 04* 03
+ !(!05* 04* 03)*Q03FBK;
Q040
SELECTEQOF* 05*!04*!03
+ !( 05*!04*!03)*Q04FBK;
Q050
SELECTEQOF* 05*!04* 03
292008-5

2-170

inter

AP-271

ADF File (Continued)
+ !( D5*!D4* D3)*005FBK;
SBLBCTBOOF* D5* D4*!D3
+ !( D5* D4*!D3)*006FBK;
007D
SBLBCTBOOF* D5* D4* D3
+ !( D5* D4* D3)*007FBK;
010D
SBLBCTB01F*!D5*!D4*!D3
+ !(!D5*!D4*!D3)*010FBK;
011D
SBLBCTB01F*!D5*!D4* D3
+ !(!D5*!D4* D3)*011FBK;
012D
SBLBCTB01F*!D5* D4*!D3
+ !(!D5* D4*!D3)*012FBK;
013D
SBLBCTB01F*!D5* D4* D3
+ !(!D5* D4* D3)*013FBK;
SBLBCTBOO = 100*!D2*!Dl*!DO
~ COMMON BOUATION FOR BIT 0
+ 101*!D2*!Dl*DO
+ 102*!D2*Dl*!DO
+ 103*! D2*D1*DO
+ 104*D2*!D1*!DO
+ 105*D2*!D1*DO
+ 106*D2*D1*! DO
+ 107*D2*D1*DO;
SBLBCTBOI = 110*!D2*!D1*!DO
~ COMMON BOUATION FOR BIT 1
+ Ill*!D2*!Dl*DO
+ 112*!D2*D1*!DO
+ 113*! D2*D1*DO
+ 114*D2*!Dl*!DO
+ 115*D2*! D1*DO
+ 116*D2*D1*!DO
+ 117*02*D1*DO;
BND$

006D

2-171

~

~

292008-6

AP-271

LEF File
JR Donnell
Intel
January 24, 1986

o

5C121
Digital Crosspoint Switch
LB Yersion 3.0, Baseline 17x, 9/26/85
PART:
5C121
INPUTS:
100@37, 101@36, 102@35, 103@34, 104@8, 105@9, 106@10, 107@l1, 110@33,
111@32, 112@31, 113@30, 114@29, 115@28, 116@27, 117@26, CLK@38, DO@2,
Dl@3, D2@4, D3@5, D4@6, D5@7, ILE@l
OUTPUTS:
QOO@12, QOl@13, Q02@14, Q03@15, Q04@16, Q05@17, Q06@18, Q07@19, QI0@24,
Qll@23, Q12@22, Q13@21
NETWORK:
CLK
INP(CLK)
ILE
INP ( ILE)
100
LINP(IOO, ILE)
101
LINP(IOl, ILE)
102
LINP(102, ILE)
103
LINP(I03, ILE)
104
LINP(104, ILE)
105
LIN'P(105, ILE)
106
LINP(106, ILE)
107
LINP(I07, ILE)
110
LINP(110, ILE)
III
LINP(ll1, ILE)
112
LINP(Il2, ILE)
113
LINp(113, ILE)
114
LINP(114, ILE)
115
LINP(I15, ILE)
116
LINP(116, ILE)
117
LINP(117, ILE)
DO
LINP(DO, ILE)
Dl
LINP(Dl, ILE)
D2
LINP(D2, ILE)
D3
LINP(D3, ILE)
D4
LINP(D4, ILE)
D5
LINP(D5, ILE)
QOO, QOOFBK
RORF(QOOD, CLK, GND, GND, YCC)
QOl, QOIFBK
RORF(QOID, CLK, GND, GND, YCC)
Q02, Q02FBK
RORF(Q02D, CLK, GND, GND, YCC)
Q03, Q03FBK
RORF(Q03D, CLK, GND, GND, YCC)
Q04, Q04FBK
RORF(Q04D, CLK, GND, GND, YCC)
Q05, Q05FBK
RORF(Q05D, CLK, GND, GND, YCC)
Q06, Q06FBK
RORF(Q06D, CLK, GND, GND, YCC)
Q07, 007FBK
RORF(007D, CLK, GND, GND, YCC)
QI0, QI0FBK
RORF(QI0D, CLK, GND, GND, YCC)
011, 011FBK
RORF(QI1D, CLK, GND, GND, YCC)
Q12, 012FBK
RORF(Q12D, CLK, GND, GND, YCC)
Q13, Q13FBK
RORF(Q13D, CLK, GND, GND, YCC)
SELECTEOOF = NOCF(SELECTEQO)
SELECTEOIF = NOCF(SELECTEQl)
EQUATIONS:
SELECTEQI
110
D2'
Dl'
DO'
+ D2 * Dl' * DO' * 114
+ D2' * Dl * DO' * 112
+ D2' * Dl' * DO * III
+ D2 * Dl * DO' * 116
+ D2 * Dl' * DO * 115
+ D2' * Dl * DO * 113
292008-12

*

*

*

2-172

intJ

AP-271

LEF File (Continued)

*

+ 02 * 01 * DO

SELECTEQO
+
+
+
+
+
+

Q120

*

*

+

Q130

117;

100 * 02' * 01' * 00'
02 * 01' * 00'
104
02' * 01
00' * 102
02' * 01' * 00 * 101
02 * 01 * 00' * 106
02 * 01' * 00 * 105
02' * 01 * 00
103
02 * 01 * 00 * 107;

*

*

03'
Q13FBK
+ 04'
Q13FBK
+ 05 * Q13FBK
+ SELECTEQIF * 05'

*

04'

*

*

04

*

*

04

* 03';

03;

Q12FBK

+ 03 * Q12FBK

+ 05 * Q12FBK
+ SELECTEQIF * 05'

QII0

QI00

03' * QIIFBK
+ 04 * QllFBK
+ 05 * QllFBK
+ SELECTEQIF * 05' * 04' * 03;
03 * QI0FBK

+ 04 * QI0FBK
+ 05 * QI0FBK
+ SELECTEQIF * 05'

Q070

*

* 04'

03'

j

03' * Q07FBK

*

+ 04'
Q07FBK
+ 05' * Q07FBK
+ SELECTEQOF * 05 * 04 * 03;

Q060

04' * Q06FBK
+ 05' * Q06FBK
+ 03 * Q06FBK
+ SELECTEQOF * 05 * 04

Q05D

03'

* Q05FBK

03'

*

D3';

* Q03FBK

+ 04' * Q03FBK
+ 05 * Q03FBK
+ SELECTEQOF * 05'

Q020

* 03;

05' * Q04FBK
+ 03 * Q04FBK
+ 04 * Q04FBK
+ SELECTEQOF * 05 * 04'

Q030

D3';

*

+ 05'
Q05FBK
+ 04 * Q05FBK
+ SELECTEQOF * 05 * 04'

Q040

*

*04*03;

04' * Q02FBK
+ 03 * Q02FBK

+ 05 * Q02FBK
+ SELECTEQOF * 05'

QOI0

QOOO

* 04 * 03';

03' * QOIFBK
+ 04 * QOlFBK
+ 05 * QOIFBK
+ SELECTEQOF * 05'

*

04' * 03;

03 * QOOFBK
+ D4 * QOOFBK
+ 05 * QOOFBK
+ SELECTEQOF

*

04' * 03';

*

05'

END$

292008-13

292008-14

2-173

AP-271

RPT File
Logic Optimizing Compiler Utilization Report

*****

Design implemented successfully

JR Donnell
Intel
January 24, 1986

o
5C121
Digital Crosspoint Switch
LB Version 3.0, Baseline 17x, 9/26/85
5C121
ILl!
DO
Dl
D2
D3
D4
D5
104
105
lOS
107
QOO
QOl
Q02
Q03
Q04
Q05
Q06
Q07
GND

-

1
2
3
-: 4
-: 5
-: 6
-: 7
-: 8
-: 9
-: 10
-: 11
- :12
-: 13
-: 14
-:15
-: 16
-:17
-:18
-:19
-:20

40:39:38:37:3S:35:34:33:32:31:30:29:28:27:2S:25:24:23:22:21: -

Vcc
Vcc
CLK
100
101
102
103
110
III
112
Il3
114
115
116
117
GND
QI0
Qll
Q12
Q13

**INPUTS**
Name

Pin

ILl!

Resource

MCell

,

PTerms

MCells

INP

Feeds:
Ol!

Clear

Clock
Latch

DO

2

LINP

13
15

Dl

3

LINP

13
15

D2

4

LINf

13
15

D3

5

LINf

9
10
11
12
17
18
19
20
21
292008-9

2-174

inter

AP-271

RPT File

(Continued)

22
23
24
D4

6

LINP

9
10
11
12
17
18
19
20
21
22
23
24

D5

7

LINP

9
10
11
12
17
18
19
20
21
22
23
24

104

8

LINP

28

0/ 4

15

105

9

LINP

27

0/10

15

106

10

LINP

26

0/ 8

15

107

11

LINP

25

0/ 6

15

117

26

LINP

7

0/10

13

116

27

LINP

6

0/ 8

13

115

28

LINP

5

0/ 6

13

114

29

LINP

4

0/ 6

13

113

30

LINP

3

0/ 8

13

112

31

LINP

2

0/10

13

III

32

LINP

1

0/ 4

13

IlO

33

LINP

13

103

34

LINP

15

102

35

LINP

15

101

36

LINP

15

100

37

LINP

15

eLK

38

INP

Reg
292008-10

2-175

inter

AP-271

RPT File (Continued)
**OUTPUTS**
Name

Pin

Resource

MCell ,

PTerms

MCells

QOO

12

RORF

24

4/ 6

24

Q01

13

RORF

23

4/ 8

23

Q02

14

RORF

22

4/10

22

Q03

15

RORF

21

4/ 4

21

Q04

16

RORF

20

4/12

20

Q05

17

RORF

19

4/ 4

19

Q06

18

RORF

18

4/ 8

18

Q07

19

RORF

17

4/ 8

17

Q13

21

RORF

12

4/ 8

12

Q12

22

RORF

11

4/ 8

11

Qll

23

RORF

10

4/ 4

10

QI0

24

RORF

9

4/12

9

Resource

MCell ,

PTerms

MCells

NOCF

13

8/ 8

9
10
11
12

NOCF

15

8/ 8

17
18
19
20
21
22
23
24

Resource

MCell

PTerms

8
14
16

4
8
8

Feeds:
OR

Clear

Feeds:
OE

Clear

**BURIED REGISTERS**
Name

Pin

**UNUSED RESOURCES**
Name

Pin
25
NA
NA

**PART UTILIZATION**
97~
89~

30~

Pins
MacroCells
Pterlls
292008-11

2-176

inter

APPLICATION
NOTE

AP-272

June 1986

The SC060
Unification of a CHMOS System

J. R. DONNELL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292009-003
2-177

inter
INTRODUCTION

OBJECTIVE

From an outside glance, the world of computers and
microprocessors seems filled with dedicated ICs that
fulfill a variety of system needs. Upon closer inspection
we find that designers must still reach into their bag of
random logic to link together all of the parts of the
system. It seems a shame to stuff a board full of high
powered peripherals and still have portions of that
board wasted on decoders, latches, and other miscellaneous random logic.

This application note covers the design of three separate _circuits for Intel's CHMOS Design Kit. The functions performed by the 5C060 are: Memory decoding,
wait state generation, and the power down circuitry for
the 8OC88 system clock.

True, programmable logic has been around a long time.
But that logic is somewhat rigid in form, one time programmable, and can also double as space heaters. These
devices are totally unacceptable for a CMOS system.
What is needed is a flexible PLA architecture, erasability for prototyping, and CMOS for low power. In addition, for this particular application the device must perform from static operation to 10 MHz.

MEMORY DECODING
The system in question supports one 32K bank of
EPROM memory, and four banks of 4K static RAM.
Figure 1 shows the memory map of this system. Address lines A19, A13, and A12 will be used to decode
the address space. PWR_DWN and S2_MIO serve as
enables. In addition, to avoid data bus contention signals memory read (MRDC) and advanced memory
write (AMWC) are decoded along with the address
lines for RAM chip selects. This is necessary for devices without output enables (OE) on multiplexed address/data busses.

FFFFF

EPROM

aoaoo

•

•
•
•

•

•
03FFF
AAM18K

03000

02000

O1FFF

01000

..-.---------1 ,-....

00000

292009-1

Figure 1. aocaa Memory Map

2-178

intJ

AP·272

Figure 2 shows a discrete implementation of the chip select decoding logic.

MRDC-r---+-+-L~
WR

--1-++-1

=P---tJD

Q

OEN

AEN

BCLK -------------~
BPRO
AEN
RO

--1-++-1
AEN (GRANT)

BPRN

4-t+-i-.J

BUSY

--1-++-1

AEN
BPRO

G:

BREO

AEN

~_o

AEN~

Lo-t>o--

CBREQ - - - - - I

BUSY

292012-3

BCLK ---------------------......
292012-2

B) Grant! Access Logic

C) Bus Transfer Control

Figure 1. PLA Approach to a Bus Arbiter

2-191

AP-276

.-----------------,

PlA
l6l8

IN~-----------------r------~

M/IO----------------+---~«

BUS CONTROL
LOGIC

OEN

Rii
WR

-------------AEN

PLA
l6R4

SREQ

BREQ

BPRN

CBREQ

RESET

BUSY

BUS ARBITER

BPRO
BCLK

292012-4

Figure 2. Bus Controller with Arbiter Connected

PLA16R4
ARBOOI
MULTIBUS I ARBITBR
SOMB SYSTBM COMPANY
BCLK IWR
IRD
ISREQ IRBSET IBPRN
IE
ICBREQ IBUSY ISYNC IBPRO IAEN
SYNC

: = /RESET*SREQ*WR
IRESET*SREQ*RD

BPRO

:

ABN

: = IRBSBT* ABN*BPRO*WR
+
IRBSBT* AEN*BPRO*RD
+
IRESBT*BPRO*BPRN*/BUSY +
IRBSBT* AEN*BPRN*ICBRBQ

OEN

:=

::;::

PLA DBSIGN FILB
D. B. BNOR. 1/1/85
NC
NC
NC
IOEN IBREQ NC

OND
VCC

+

IRESBUSYNC

IRBSBT*SRBQ~BN

IF(BPRO*/ABN) CBRBQ

= BPRO*/ABN

IF(AB,N) BUSY = UN
BRBQ

BPRO +
ABN

292012-5

Figure 3. List File for PLA Arbiter

2-192

AP-276

RESET~~----~-i

XREO

D-----L....-I
) - - - - C ] BPRO

BeLK~~----------------~~--------------~

BPRN~_-~ ~o-----------------------------~
292012-6

A) Request

RESET --------.....-1
SREO ------.....+-1""""""'\
BPRN - - -......++-I._~
eSI

---+++-1

AEN
AEN -

eBI

+--+--1

....

---------1

eeLK----------------------------~

292012-7

B) Grant

RESET

X:~:
BCLK

~

---t:=W

eMDEN

RE:~: ------~~>--B-S-I-J-- -a
....

BUSY

292012-8

292012-9

D) Busy

C) Command Enable

SREO
AEN

~--..-_

292012-10

E)CBRQ
Figure 4. Logic Diagram of Bus Arbiter Functions
2-193

intJ

Ap·276

INTAIN

C > - - - - - - - - - I ;>---<:::J INTA

MIlO 0 - - - - 1 H

>--1-.......0

IORC

>-+--<:::1 IOWC

o..-r.....t--iH

>-t-.......OMRDC

WRO~-t---t

>-t-.......OMRWC

RD

CMDEN

AEN

Figure 5. Logic Diagram of Bus Controller Functions

2-194

292012-11

inter

AP-276

DANIEL B. SMITH
INTEL CORPORATION
MARCH 27, 1986
VBRSION 1.1
RBV. A
5C060
CMOS BUS ARBITBR/CONTROLLBR

PART:
INPUTS:
OUTPUTS:

5C060
BCLK, XRBQ, RBSRT, BPRN, MIO, RD,
WR,
INTAIN
BPRO, ARN, BRBQ, CBRQ, BUSY, INTA, MRDC, MWTC, 10RC, 10WC

NBTWORK:
BCLK
INTUN
XRRQ
RESET
BPRN
MIO
RD
WR
BPRO
AlN,AlN
BRBQ
CBRQ,CBI
BUSY,BSI
INTA
MRDC
MWTC
10RC
10WC
SRRQ
SYNC
CMDRN

INP (BCLK)
INP (INTAIN)
INP (XREQ)
INP (RESIIT)
INP (BPRN)
INP (MIO)
INP (RD)
INP (WR)
CONr (BPROe,VCC)
RORr (AENd,BCLK,GND,GND,VCC)
CORr (BRBQe,VCC)
cOlr (CBRQel,CBRQe2)
COIF (BUSYe, AlN)
CORr (INTAIR,ABN)
CONr (MRDCe,AlN)
con (MWTCe,AlR)
CONr (IORCe,ARN)
con (IOWCe,AEN)
RORr (SREQd,BCLK,GRD,GND)
NORr (SYRCd,BCLK,GRD,GRD)
NORr (CMDERd,BCLK,GND,GND)

.BUS CLOCK INPUT.
.INT. ACK. INPUT.
.SYSTEM RRQUBST INPUT.
.RBSET INPUT.
.BUS PRIORITY INPUT.
.MEMORY/IO INPUT.
.READ INPUT.
.WRITR INPUn
.BUS PRIORITY OUTPUT.
.ADDRESS BNABLB (GRANT).
.BUS RBQUBST.
.CBRQI -- SIMULATBD O.C .•
.BUSYI -- SIMULATBD O.C .•
.INT. ACK. OUTPUT.
.MEMORY RBAD COMMAND.
.MBMORY WRITB COMMAND.
.1/0 READ COMMAND.
.1/0 WRITB COMMAND.
.VALID BUS RBqUBST.
.SYNCHRONIZBD REQUEST.
.COMMAND ENABLE.
292012-12

BQUATIONS:
BPROe
ABNd
BRBQe
BUSYe
CBRQel
CBRQeZ
MRDCe
MWTCe
10RCe
10WCe
SREQd
SYNCd
CMDBNd

*
*

(SREQ
IBPRN);
RBSBT
SREQ
IBPRN
BSI +
RESET
SREQ
AEN +
RESRT
IBPRN
ABR
CBI;
I(SREQ + ARN);
IRESIIT;
I(SREQ
lAIN);
SREQ
IABIi;
IMIO + RD + CMDEN;
IMIO + WR + CMDBN;
MIO + RD + CMDEN;
MIO + WR + CMDBN;
RESBT
SYNC;
RRSBT
XREQ;
I(RESET
XRRQ
ABN);

*

*

*

*

*

*

*
*

*

*
*

*

*

END$

292012-13

Figure 6. iPLDS Network List File

2-195

inter

AP-276

Logic Optimizing Compiler Utilization Report

*****

Design i.ple.ented successfullY

DANIEL E. SMITR
INTEL CORPORATION
MARCH 27, 1985
VERSION 1.1
REV. A
5e060
CMOS BUS ARBITER/CONTROLLER

5COSO
BCLI
MIO
RESERVBD
RBSERVED
RESERVED
ARN
BPRO
INTAIN
WR
liD
BPRN
GND

-:
-

1
2
3

4

-: 5

-: S

-

7

-: 8

9
-:10
-: 11
-: 12

24:23:22:21 :20: 19:18:17:IS:15:14:13:-

Vec
XREQ
INTA
IOWC
10RC
MWTC
MRDC
BUSY
CBRQ
BREQ
RBSBT
GND

nINPUTS**
Na.e

Pin

BCLI
MIO

Resource

MCe11 It

PTer ••

MCells

INP
2

Feeds:
OE

Clear

Clock
CLKI

INP

2
3
4
5

INTAIN

8

INP

14

0/ 8

WR

9

INP

15

0/ 8

2
4

RD

10

INP

16

0/ 8

3
5

BPRN

11

INP

12
13

RBSBT

14

INP

S
9
10
11
12

XRBQ

23

INP

9
10
292012-14

Figure 7. iPLDS Report File

2-196

infef

AP-276

nOUTPUTS**
Na.e

Pin

Resource

MCell It

PTer ••

MCell.

Feeda:
OB

ABN

6

RORF

12

3/ 8

7
8
9
12

-7
1
2
3

Clear

Clock

Clear

Clock

4

6
6

BPRO

7

CONF

13

1/ 8

BRBO

15

CONF

8

1/ 8

CBRQ

16

COIF

7

1/ 8

12

BUSY

17

COIF

6

1/ 8

12

MRDC

18

CONF

6

1/ 8

MWTC

19

CONF

4

1/ 8

IORC

20

CONF

3

1/ 8

IOWC

21

CONF

2

1/ 8

UTA

22

CONF

1/ 8

**BURIED REGISTBRS**
Haae

Pin

Resource

MCell It

PTer ••

MCells

3

NORF

9

1/ 8

2
3

Feed. :
OE

4
5
4

NORF

10

1/ 8

11

6

NORF

11

1/ 8

7
8
12
13

Resource

MCell

PTera.

7

**UNUSED RESOURCBS**
Haae

Pin
13

nPART UTILIZATION**
96_
100_
11_

PiDe
MacroCells
Pter ••
292012-15

Figure 7. iPLDS Report File (Continued)

2-197

intJ

APPLICATION
NOTE

AP-307

January 1987

EPLDs, PLAs and TTL
Comparing the "Hidden Costs"
in Production

PEDRO VARGAS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292030-001
2-198

inter

AP-307

INTRODUCTION

• Prototype costs - first implementation of the product idea

When comparing logic alternatives, too often the outcome is dominated by the piece price of the components. A side by side comparison based on component
costs only, may give the appearance that EPLDs are
cost prohibitive. However, when the overall cost of
manufacturing a system is considered, the higher integration of EPLDs proves to be a cost-effective solution.

• Production costs - volume manufacturing of the
product

OBJECTIVE
This application note examines the total costs associated with designing, prototyping, and manufacturing a
system. Once these costs have been examined, a comparison is made between EPLDs and other logic alternatives. By being aware of these additional costs, the
engineer can make a more accurate cost comparison as
a design is begun.

COSTS DEFINED
Costs can be difficult to pinpoint, let alone measure.
However, with a bit of examination, we can break down
costs into the following categories;
• Design costs
- the cost of conceiving a product

Usually, the brunt of the cost for the first two categories is dismissed as NRE (non recurring expense). The
effect of these costs on the overall project is examined
later, let's look at the third category. Production costs,
can be further broken down into;
• Component costs- the cost of the parts per board
• Inspection costs - labor costs for receiving the
parts
• Inventory costs - the cost for storing, handling
and dispensing the parts
• PCB fabrication - the cost for labor and equipment
used in building a board
• Integration costs - the cost of harnesses, enclosures,
nuts and bolts etc.
It's important to understand how the cost of a product
is affected not only by the cost of the ICs used, but also
by the other costs listed above. Figure 1 is a graph
which shows this relationship.

TOTAL
SYSTEM COST
COST OF
CIRCUITS

...
Iii
o
u

SYSTEM
HARDWARE
COSTS

OPTIMUM
COMPLEXITY

M S I - - - . . , . - - - - - - - - - - - - - - , VLSI
CIRCUIT COMPLEXITY

Figure 1. Optimizing Circuit Complexity

2-199

292030-1

AP-307

RESET~

RESET

XREQ ~ Q

SREQ
U3

AEN

BPRN

BCLK

BSi

CMDEN

LS10
LS74

292030-4
Ull

1/4Ul0

~S126

.= ~~"""

AEN
AEN

AEN

LS74

AEN

BSi
292030-5
U3

Cai

LS21

BCLK

292030-2
SREQ

->........r-.......

AEN .....- 1 - . . /
LSOB
BREQ

REsET
XREQ

BPRO

BCLK
BPRN

INTAIN

O>---------i

M/iO D----1>-i_

RD

0>+....1-+-1

WRD.....-t---i

Figure 2. MULTIBUS Arbiter/Controller-TTL Implementation

2-200

CBI

292030-6

AP-307

The graph shows that as the density of the components
used in a system progresses from SSI to VLSI, the cost
for these devices increases. This isn't surprising, denser
chips cost more to make. At the same time, by using
denser devices, system hardware cost decreases. This is
shown by the center line, which encompasses all the
costs listed above. The bathtub curve above these shows
the effect that denser ICs has on a system. That is, by
using higher integration ICs, more functions are removed from the board. This in tum reduces the cost of
the system in labor and parts costs.
A cost-effective product is one that uses the most efficient logic for the application. It's important to note
that use of the least expensive component may not
translate into system cost savings.
PAL' is a registered trademark of Monolithic Memories Inc.

INTA

---------+----01

ARBITER CIRCUIT
Let's explore costs in more detail with an example. The
example used here is the circuit of Figure 2, a
MULTIBUS® I arbiter/controller. The circuit is used
by bus masters arbitrating for control of the bus. Our
implementation comparison contrasts TTL, PAL', and
EPLD solutions.

Implementation Requirements
The TTL implementation is typical of many board level
designs in the sense that it relies on inexpensive
LSTTL. Figure 2 shows that the implementation is
composed of standard logic gates and D-latches. The
component list in Table I shows the circuit breakdown
in more detail. [20]

>-IH

M/IO-----------~--~~

BUS CONTROL
LOGIC

RD-II-I~-I

I--....--+CMDEN

wR-II-4.....-I

-------1
BPRN -------1
RESET -------1
SREQ

1------..... AEN
PLA
16R4

I-----BREQ

1 - - - - - CBREQ

BUS ARBITER

1-----BUSy

[~::::::~=======BPRO
BCLK
292030-8

Figure 3. MULTIBUS Arbiter/Controller-PAL Implementation

2-201

AP-307

- The total chip count
- The total number Of IC pins
- The traces required to connect logic gates together
• Area (inches-square)- The.sum of the area of all ICs

Table 1. Arbiter/Controller TTL Component List
IC

Type

DIP

U1
U2
U3
U4
U5
U6
U7
US
U9
Uta
U11

LS08
LS74
LS21
LS10
LS11
LS02
LS27
LS27
LS366
LS126
LS04

14 PIN
14PIN
14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
16 PIN
14 PIN
14 PIN

• ICCount
• Pin Count
• Interconnections

ICC (mA) Area (in2) Cost $
8.8
8
4.4
3.3
6.6
5.4
6.S
6.8
21
22
6.6

0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.24
0.21
0.21

0.18
0.24
0.22
0.16
0.22
0.17
0.23
0.23
0.39
0.39
0.16

• Icc (rnA)
• Pwr(mW)

Production Costs

The PAL version of the circuit is shown in Figure 3.
Two PALs are used due to the requirement of registered outputs on several of the signals. [20]
The complete circuit can also be designed in one 5C060
EPLD (Figure 4).1 18] Looking at the three figures
quickly points out the amount of circuit board space
required by each version. The three implementations
are compared side by side in Table 2.

SC060
BCLK
MIO
RESERVED
RESERVED
RESERVED
AEN
BPRO
INTAIN
WR
RD
BPRN
GND

2
3
4
5
6

24
23
22

7
8
9

10
11
12

15
14
13

Vee
XREQ
INTA
IOWC
IORC
MWTC
MRDC
BUSY
CBRQ
BREQ
RESET
GND

- The current consumed while
active
- Total power consumption at
5VDC.

Earlier, we noted that production costs consist of many
variables. Usually, these variables are lumped together
under the term "hidden cost". Although hidden costs
are kept in mind by engineers, lack of tangible figures
usually precludes their use in detailed cost breakdowns,
For this reason, several manufacturers and consulting
firms have come up with typical costs per IC and per
pin.
For example, SOURCE III (San Jose, CA) reports in
one of their studies that the manufacturing cost of a
system translates to about 0.35 cents per IC pin. ICE
Corporation (Scottsdale, AZ) and EDN magazine concur that the inserted cost of an IC is about $2 dollars.
DATAQUEST also published a cost of about $2 to $4
per IC. While the data seems to be consistent, most
engineers want to see for themselves how figures like
. these might be arrived at. The next sections provide
insight into this process.
COMPONENTS

The cost of the component is the easiest value to obtain.
A quick call to a distributer or (at worst) a scan
through the back of BYTE magazine (for TTL) gives us
this cost. Table 3 shows the breakdown of component
costs for each version of our MULTIBUS I circuit.
Table 3. Average Component Costs
Package

292030-9

DIP14
DIP16
DIP20
DIP24

Figure 4. MULTIBUS Arbiter/Controller-EPLD
Implementation
Table 2. Implementation Results
for Arbiter/Controller
Item

TTL

PLA

EPLD

IC Count
Pin Count
Interconn
Area
ICC (rnA)
Pwr (rnW)

11
156
36
2.34
100
500

2
40
7
0.6
240
1,200

1
24
0
0.36
15
75

TTL
$0.25
$0.35
$0.55

PLA

EPLD

$1.50
$2.90

$6.00

The price of TTL has changed very little for the last
few years[24] while EPLDs are dropping in price tremendously. PALs have also leveled off in pricing.
Why? Figure 5 shows the life cycle curve of IC products used by the semicc;mductor industry. From the
curve we see that TTL is in the stable range and prices
are not likely to drop much more. PALs are also maturing and approaching a stable pricing range. EPLDs
however, are in a growth area and historically this is
2-202

Ap·307

-20%

INTRODUCTION
EPLD

GROWTH

MATURITY

SATURATION

PAL
LSTTL

STTL

1987 {

DECLINE (OBSOLETE)

TTL

EPLD
PAL
LSTTL

1988{

STTL TTL

EPLD

1989{

I

PAL
LSTTL

ISTTL TTL

292030-10

Figure 5. Typical Price Changes Through Semiconductor Product Life Cycle

where the heaviest pricing pressure is. This means that
while EPLDs might be expensive (per part) right now,
it's not out of the question to expect a 30% per year
price reduction as the process is honed and perfected.
In other words, it's also important to consider the price
of a component at the projected production date, not
just at design time.
Life cycle position is also important in understanding
the gate cost that is associated with programmable logic
devices like PALs and EPLDs. This relationship is
shown in Figure 6. The curves translate our observation
that newer devices have steeper price cuts during their
introduction phase. The PAL curve shows that the cost
per gate is leveling off due to the maturity of the device.
In contrast, the EPLD is in the growth region, and
based on the traditional price reductions, shows a cost
per gate that intersects and bypasses the PAL curve.

INCOMING INSPECTION

For most companies, incoming inspection is more than
taking the parts and putting them on the shelf. Most
have visual checking as well as some form of IC testing.
The variables here are, what amount of human intervention is needed, are automatic handlers needed, are
"go/no go" tests or "binning" done automatically? The
typical scenario means that components are graded and
tested individually, and then placed into one of several
bins or kitted. Because the operators handle a large va·
riety of pinned devices (resistors, capacitors, ICs), the
cost can be distributed on a per pin basis. Many compa·
nies use a penny per pin for this cost.(16)

2·203

Inspection cost

=

$0.01 per pin

AP-307

$ COST/GATE
0.03

PALs

_____ EPLDs

0.0025

04 '85

04' 86

04 '87

04' 88

04' 89

04 '90

292030-11

Figure 6. Projected Cost Per Gate
INVENTORY

While most engineers agree that reducing parts count
on their board makes the cost of inventory less, they
usually attribute this to the reduction in component
costs alone. In reality, the overhead of carrying inventory is made up of the following factors; [21]

Maintenance refers to the cost of handling, counting,
marking, and auditing each IC. Each production manager has their own way of keeping tabs on this. One
way is to charge on a per part basis. A review from
several production oriented journals cites $0.3 cents as
the typical handling charge for 16 pin devices.l 23 ]
Maintenance = $0.03 per 16 pin part.

• Cost of the component
• Cost of storage
• Maintenance costs
• Data processing

Processing[21] usually entails a parts log that tracks
each part by manufacturer, cost, second source etc.
Also, monthly shortage reports are quite common as
are quarterly orders and audits. Limiting this cost to
paper only, at one sheet of paper per week, per year, at
a cost of a penny per part type;

• Usage
• Taxes insurance and interest
• Turnover rate

Processing = $0.52 per part type per year

The American Production and Inventory Control Society (APICS) reports that since 1973 the median cost of
carrying inventory has been about 25% of total production costs. They also note that the largest contributing
factors are the cost of materials handling storage, and
data processing. For simplicity, let's limit our inventory
cost to these items.
Inventory cost = storage

+

maintenance

+

PCB FABRICATION

The cost of manufacturing (cutting, etching, drilling) a
circuit board seems to vary around two pricing methods. Some fab houses charge on a square inch basis.
Others base their price on a gut feeling based on previous jobs. The square inch method is the most common.

processing

Depending on the locale of a company, the cost of storage can vary greatly. However, this cost is charged on a
square foot per year basis. Lets assume a conservative
figure of $20 dollars and distribute this amoung the ICs
in our example circuit.
storage = [TotallC area (sq. ft.) x $20]/IC count

Items of interest in evaluating PCB costs are, number
of ICs, number of traces and vias, and in general, the
complexity of the. board. Traces that are smaller than
10 mils require extra care in etching. Depending on
complexity, and additional charge might be added to
the area cost. This charge covers material loss in case of
low etch yields. Yield is directly dependent on the number of ICs on a board. In other words, more ICs mean
more holes, tighter traces, and a greater chance of losing some boards in their processing. The average going

2-204

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rate is $0.20 cents per inch for double-sided boards.
The price increases by about 40% for every two layers.
This extra charge, however is too subjective to consider
in our comparison.
PCB Fab = [$0.20 x total IC area (sq. inch)]/IC count

Traces

There is a real cost involved with traces, which doesn't
surface until later in the production cycle or on a later
board revision. A technical paper presented at the 1984
international Test Conference[l] estimates that the cost
of a trace on a board is ten to thirty times that of one
made in silicon. The cost of traces is taken up by:
• Increased drilling (more traces = more vias =
more holes)
• Lower PCB yield (smaller mill lines drop the board
yield)
• Increased risk oftrace to trace shorts (lower reliability)
• More expensive artwork mods (it costs more to
move traces around on a board)
• More expensive PCB mods (cost of cuts, jumpers,
and rework)
In our circuit example, an extra trace is that which is
unnecessary in contrasting implementations. For example, referring to Figure 2, of all the traces required to
connect/RESET in the TTL implementation, only one
will be required for the EPLD and PAL circuit (the
input); the others won't be needed.

ASSEMBLY

The cost of assembling a board is largely dependent on
labor charges and capital. Assembly consists of lead
forming, component insertion, and soldering. The labor
charge is hourly and varies between domestic and offshore assembly houses. While machines can certainly
do lead cutting, crimping, and insertion, human intervention is still an expensive presence. Assembly costs
can be charged on a per board or per chip basis. The
latter is more appropriate for our comparison. The average charge (domestically) is about $0.10 per Ie.
Assembly = $0.10 per 16 pin part

One important result of using high integration parts
like EPLDs is that the assembly procedures (manual or
automatic) go smoother. This is due to fewer parts being handled, and less overheating of the equipment.
Overall, the industry reports less insertion faults (parts
stuffed wrong) as denser ICs are used and as insertion
equipment matures with them.
TEST

Test strategies can vary, but the typical test flow for a
board[3] is shown in Figure 7. The process is basically
taking a board through increasing complexity levels of
testing. For example, ATE might be a bed of nails fixture that catches 60 percent of the faults. Test bed is
usually a backplane with all boards known good except
for the one under test. System test is the final integration of all the boards that were tested individually.

For our comparison, let's take the median value of
twenty as our multiplying factor. Since a silicon trace
costs an order of magnitude less than an EPLD gate
($0.01), the resulting cost of a PCB trace is;
($0.01/10) x 20 = $0.02 cents per trace

Trace cost = [total trace count x $0.02]/IC count

292030-12

Figure 7. Typical Test Flow

2-205

AP-307

TO NEXT LEVEL
OF TEST OR
SHIPPING

BOARDS IN--r--l~

292030-13

Figure 8. Typical Test and Repair Loop
Errors can occur at any step of the test flow; each time
this happens, a test loop is initiated. This loop is depicted in Figure 8. The cost for testing a device depends on
the cost of the equipment, depreciation, the labor rate,
and other factors that are company dependent. There
are several ways to reduce test costs, but the best way is
to reduce the probability of errors occuring. There is no
question that as the number of ICs increases, so does
the probability of error.
With all things considered, the industry reports a nominal test cost of about $0.15 per IC,[27](28]
Test cost

=

insert, resolder, and clean a component pin[91, one can
see that more ICs on a board directly affect cost. Repair
times also increase dramatically on multi-layer boards
that might have been doubled sided if denser logic was
used.
For our comparison, let's assume that our test equipment is 95% efficient in finding solder faults on the
first pass (no loop). This leaves 5% of the faults that go
undetected and eventually must be found and repaired.
The estimated cost per pin based on a $6.00 hourly
wage and the two minute repair time is approximately
$0.02 cents.

$0.15 per 16 pin 10
Rework = [$0.02 X total pin countl/lC count

REWORK

It is important to note that the probability of errors is

The cost of rework is best understood by considering
the cause of errors in more detail. Errors are typically
caused by poor board quality, inadequate solder process, tolerance of insertion, and of course, bad chips.
Table 4 shows the average board fault spectrum. The
figures are a conclusion reached by EVALUATION
ENGINEERING magazine[101 as to what the industry
is currently seeing. The table shows that the majority of
board errors is due to solder shorts. These errors are
the result of traces or IC holes being too close, which is
what happens on densely populated boards.

Table 4. Average Board Fault Spectrum
Tolerance
Shorts
Insertion
Bad Parts

20%
40%
30%
10%

based on a Poisson distribution[81 that increases exponentially with the number of pins and components.
This distribution is used in wave solder processing to
correct for solder errors. Mathematically this is expressed as:
p = e-nP(np)X
X!

where; P
n
p
x

= The probability that a defect will occur

= The number of components
= The fraction defective
= The actual number of defects

This means that the TTL and PAL version of the arbiter have a higher probability of error than the EPLD
version. However, to make our comparison easier, let's
simplify this to more of a linear relation. For each implementation, the rework cost per IC is calculated by;

Of all the material costs associated with rework, the
main cost is the time spent on a repair. Considering
that it takes approximately two minutes to desolder,

Rework cost = [(total pin count) x (5%) x ($0.02 cents)]IIC count

2-206

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PRETEST

AFTER
PRETEST
OPERATION

292030-14

Figure 9. Example of a Production Line
QUALITY CONTROL

POWER SUPPLV

In most production operations, boards go through several steps of quality inspection. The bare board might
be inspected after preliminary tests and after system
tests. Although 100% inspection should theoretically
eliminate all errors, in real life this rarely happens. The
main reason for this is the complexity of the production
and rework loops as shown in Figure 9.

Price for 5V, single output, switching power supplies as
advertised by several vendors is $1.00 per watt. The
calculation for determining power supply costs in our
comparison is:

Quality control's purpose is to remove defective products and either junk them or rework them, neither of
which is cost effective. The best approach is to design
the quality in, not fix it in. One way to design in quality
is by reducing the possibility of errors and increasing
the reliability of a product. This is one of the primary
advantages of dense logic (like EPLDs and PALs) over
TTL.

Additional Costs

A survey conducted by CIRCUITS MANUFACTURING magazinel 8] yielded the cost of $10 to $50 dollars
to inspect, find, and repair a defect on a board. They
summarized that the actual cost of inspection is about
$0.004 for each hole on a board. With this in mind, let
us assume a 100% inspection of our arbiter circuit for
each implementation. This means that each pin (and
every trace via) will have to be looked at. The calculation for this is;

ac cost

Power cost = [(5VDC x Icc (rnA)) x $1.00 per walt]/IC count

In addition to the more obvious costs, there are several
other items that contribute to the "hidden cost" of a
system.
PROGRAMMING LOSS

Because PALs are a one time programmable type of
device, full testing can't be done on them without destroying the user's fuses. For this reason PALs have a
published programming loss of 2%[20]. The cost for
this is:

= (total pin count x $0.004)/IC count

2-207

Programming loss = (PAL IC count
per IC

x

0.02)

x

PAL cost

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Ap·307

EPLDs, because they are based on EPROM cells, can
be programmed for different patterns, fully tested before customer delivery, and then erased. The result is ~
near 100% percent programming yield(22).
'
PROGRAMMING FEE

Programming fee is the cost of programming a device.
While many companies have in-house programmers, it
is quite common for programming to be done by the
distributor. In some cases, and at low volumes, the programming may be done free of c4arge. However, at
larger volumes a 'programming charge is not uncommon. The charge varies with volume, programmer
availability and in general, your state of affairs with the
distributor. The cost for programming EPLDs and
PALs is the same IJer device and averages about $0.25
cents.
Programming fee

=

Let us assume that the production manager reduces
safety stock py a moderate amount, let's say 3%. In a
case like this, usually, the larger more expensive parts
are curtailed first. Since EPLDs provide good coverage
for work in progress and ,because they are more expensive by eomparison, we can reduce the total safety stock
to 2% and not compromise our safety margin. Because
TTL is inexpensive.it tends to suffer more of the "gunshot" approach in testing(7). This means that the useage rate is greater because production technicians tend
to replace TTL parts with more liberty. For this reason
let's leave the TTL ,safety stock as it stands. PALs
could be reduced, but faced with the fact that the programming yield is 2% and that internal modifications
can't be made, the production manager might decide
not to change the safety stock for PALs. These results
are shown in Table 5.
Table 5. Safety Stock

$0.25 cents

Unexpected
Events

SAFETY STOCK

Although this particular item was not mentioned in the
inventory section, it plays a very important role in the
production world. Safety stock(21) is extra ICs ordered
to cover for unexpected events. Unexpected here might
be a large unforeseen customer order or simply a bad
batch of pails.
While industry seems to strive for the' optimum JIT
Gust in time) production(14)[J6), which stresses mini-'
mal inventory until needed, it's not unusual for production managers to carry a five to ten percent inventory
buffer depending on the cost of the part. In most cases,
the larger expensive parts like microprocessors, peripheral controllers, and other LSI devices are safety
stocked in smaller quantities.
Let's assume that the safety stock is to be a maximum
of 10%. Five percent might be used to cover for the
unexpected occurrences, and five for WIP (work in process) modifications. Since all parts have the same probability of unexpected events we can assign that percentage equally. Justifying the second 5% depends on the
IC technology itself. For instance, WIP modifications
usually require cuts and jumpers on TTL, therefore it's
unnecessary to order'the additional 5%. In process
modifications to an EPLD are done simply by reprogramming it, here again there is no need for the additional 5%. PALs however cannot be cut andjumpered
(internally) nor can they be reprogrammed. Also/there
is the possbility that "on the shelf' PALs will be programmed in advance, therefore a WIP mod that impacts their function means that those parts must be
obsoleted Gunked). In this case, an additional 5% is
justifiable.

WIP
MODS

Total

TTL

PAL

EPLD

5%

5%

2%

0

5%

0

5%

10%

2%

The safety stock calculation for each implementation is:
Safety stock ~ (% of stock x IC type x IC type cost)/IC count

DE-COUPLING CAPACITORS

While adding caps solves many problems due to system
noise, it also increases the cost of PCB layout, PCB fab,
and adds an additional burden on,all of our other costs:
For a TTL system,a good de-coupling rule of thumb is
to use one 0.01 /-I-f per each synchronous driven gate
and at least 0.1 /-I-f per 20 gates regardless of synchronicity. Engineers recognize the need for decoupling and
usually take it a step further by using one capacitor per
IC. Most boards reflect this practice, which, in itself is
very good. However, the addition of all these caps is
definitely measurable, in both component and systems
cost.
The ;iverage cost of a ceramic capacitor in moderate
quantities is about half ,a cent. For our comparison we,
will follow the accepted practice and de~couple each
TTL, PAL, and EPLD' device. Our capacitor cost is
then:

2-208

De-coupling cost = $0.005 x Ie count

inter

AP-307

---;-"ESCAPE"

$50

~~~U~~~L~E~E~~?RNE~STICS

:
• DIAGNOSTICS TIME
(SECONDS TO MINUTES)

:

• UNSTRUCTURED DIAGNOSTICS • SAME AS SYSTEM TEST
• HIGH SKILL REQUIRED
+
• DIAGNOSTICS TIME
• TRAVEL OVERHEAD
(MINUTES TO HOURS)
• "LOST" CUSTOMER GOODWILL

292030-15

Figure 10. Escape Costs

Other Costs To Consider

ENCLOSURE

Eventually, some place toward the end of a production
line, a board becomes part of a system. At this point it
is housed in an enclosure and all the necessary cabling
is done. Even here, however, the impact of using a particular IC technology can still be felt.

Certain applications require reduced packaging or enclosure size. In industrial control for example, each line
might require a complete system to monitor it's operation. In a case like this, a large bulky box full of boards
might not be appropriate. A good example of the benefits that high integration logic provide enclosures, is the
third market versions of the popular PC. Many of these
companies have fully compatible versions that fit on a
single board. EPLDs and PALs are capable of providing a cost savings in this respect. However, while PALs
approach the density requirements, their large power
needs render them counterproductive to the low power
specs of small systems. TTL is just not as effective as
either PALs or EPLDs.

DEFECT ESCAPES

One very significant item that the test community acknowledges is the cost of "escap~s"[41. "Escape" is defined as a fault that goes through the early stages of
board test undetected. Figure 10 shows the escape relationship. An industry rule of thumb states that the cost
to detect a fault increases by an order of magnitude at
each stage. This means that if it costs $5 to find a fault
at the board test level, that same fault might cost $50 at
the system level and $500 at the field level. An important relationship to remember, is that the number of
faults per board increases logarithmically, as the number of components on the board increases[61. The cost
of an "escape" is difficult to quantify, but generally, a
board with a higher component count has a greater
costf2)[8].
CABLES/WIRING HARNESS

For our comparison let us assume the cost of enclosure
per chip is $0.75. The calculation is:
Enclosure cost

=

$0.75 x IC count

Table 6 shows the cable and enclosure costs for the
MULTIBUS I circuit. Although the results are based
on assumed values, we can see that a larger IC count
influences the burdened cost of the system. Our final
comparison will not use these figures, but they should
be considered.

When the number of components or the power requirements of a system are reduced, a reduction in cables
and wiring is usually expected. The cost savings here is
either in the elimination of cables (because more functions are condensed into an IC) or the reduction of
cable gauge or length (because less power is required, in
the case of EPLDs). Also, fewer cables means fewer
cable ties, connector pins, and mounting hardware.
While this is a subjective figure, lets assume that the
distributed cost of system cables is $0.25 per IC.
Cable cost

=

$0.25 x IC count

2-209

Table 6. Other Production Costs for
Multibus I Circuit
TTL

Wiring/harness
Enclosure

$2.750
$8.250

PLA

$0.500
$1.500 '

EPLD

$0.250
$0.750

inter

AP-307

were done on a Lotus 1-2-3 worksheet that the individual engineer can modify with their specific values. The
worksheet is available, and can be downloaded from the
Intel EPLD bulletin board. Table 8 shows our calculation results for tpree years of production.

Arbiter Circuit Conclusion
A compilation of the cost variables for our comparison
is shown in Table 7a and 7b. Because the cost may
differ for each company, the comparison calculations
Inventory: .

Costs
Incoming insp. ($/pin)
Storage ($/sq.ft./yr)
Maintenance ($/part)
Processing ($/part type/yr)
Safety stock (%)

Manufacturing:

$0.010
$20.000
$0.030
$0.520
2%
Costs

PCB fab. ($/sq.in.)
Assembly ($/part)
Test ($/part)
Rework ($/pin)
QC ($/pin)
Power ($/watt)
Interconn
Program ($/part)
Caps. (each)

$0.200
$0.100
$0:150
$0.020
$0.004
$1.000
$0.020
$0.250
$0.005
(a)

Integrated Circuits
Component Count:
Package
DIP14
DIP16
DIP20
DIP24

TTL

PLA

10
1
0

EPlD

2

ICs

Types

TTL
PLA
EPLD

10
2
1

1

Circuit Requirements:

ICC (max)

TTL circuit (total rnA).
PLA circuit (total rnA).
EPLD circuit (total rnA).

100
240
15

Interconnects
36
7
0

(b)
Tables 7a and b. Multibus Arbiter/ControllerCost Variables

2-210

AP·307

Table 8. MULTIBUS I Arbiter/Controller Production Costs

AVERAGE COMPONENT COST
Year 1
Package

DIP14
DIP16
DIP20
DIP24

TTL

$0.25
$0.35
$0.55

PLA

Year 3

Year 2
EPLD

TTL

$0.20
$0.30
$0.38

$2.00

PLA

EPLD

$1.70

$6.00

TTL

PLA

$0.19
$0.27
$0.35

$1.56

EPLD

$2.90

$4.20

PRODUCTION COSTS

Year 2

Year 1
Item
(costs per part)

TTL

PLA

EPLD

TTL

PLA

Year 3
EPLD

TTL

PLA

EPLD

Components

$0.259

$2.000 $6.000

$0.209

$1.700 $4.200

$0.197

$1.560 $2.900

Incoming Insp.

$0.142

$0.200 $0.240

$0.142

$0.200 $0.240

$0.142

$0.200 $0.240

Inventory
Maintenance
Storage
Processing

$0.027
$0.030
$0.473

$0.038 $0.045
$0.042 $0.050
$0.520 $0.520

$0.027
$0.030
$0.473

$0.038 $0.045
$0.042 $0.050
$0.520 $0.520

$0.027 $0.038 $0.045
$0.030 $0.042 $0.050
$0.473 $0.520 $0.520

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

$0.060
$0.070
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

$0.060
$0.070
$0.125
$0.150
$0.020
$0.080

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

Power Supply

$0.045

$0.600 $0.075

$0.045

$0.600 $0.075

$0.045 $0.600 $0.075

Total Cost/Part

$1.393

$3.904 $7.422

$1.343

$3.604 $5.622

$1.331

Total Cost/System

$15.321 $7.808 $7.422 $14.771

Additional Costs/System
Programming loss
Safety stock
Programming fee
De-coupling caps

$0.000
$0.143
$0.000
$0.055

True mfg. cost/system

$15.518 $8.798 $7.797 $14.941

Printed Circuit Board
Fabrication
Trace costs
Assembly
Board test
Rework
QC

$0.080
$0.400
$0.500
$0.010

$0.000
$0.120
$0.250
$0.005

$0.000
$0.115
$0.000
$0.055

2-211

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.060
$0.070
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$3.464 $4.322

$7.208 $5.622 $14.641 $6.928 $4.322

$0.068
$0.340
$0.500
$0.010

$0.000
$0.084
$0.250
$0.005

$0.000
$0.109
$0.000
$0.055

$0.062
$0.312
$0.500
$0.010

$0.000
$0.058
$0.250
$0.005

$8.126 $5.961 $14.804 $7.813 $4.635

intJ

AP-307

The comparison in component costs shows that the
EPLD costs more than either a TTL or PAL IC. As '
costs are added, the figures for TTL and PALs begin to ,
approach the cost of an EPLD. These are shown on the '
line labeled "Total cost/part".
The "Total cost/system" line shows the actual cost
when all the ICs are considered. For the first year, the
TTL version is the more expensive implementation, and
the EPLD numbers look very favorable.
The "True mfg. cost/system" line results after additional costs are figured in. Here we see that the ,first
year, the EPLD version already provides a $1 savings
'over the PAL version, and that the cost of the TTL
implementation is very high: Also, the inserted cost per
IC at this point is, $l.lS for TTL, $2.40 for PAL and
$1.80 for the EPLD. This is in line with the inserted
costs that we mentioned earlier.
The production costs for two additional, years shows
that the decreasing price of EPLDs (based on the curve
of Figure 5) will continue to prl)vide costs savings as
production ramps up in quantities.
, In terms of functional benefits, the EPLD implementation is the most beneficial because;
• The chip count has gone down, one EPLD has replaced II TTL ICs in one implementation, and 2
PALS in the other, reducing the cost and time of:
-board layout
-board fab
-assembly
-rework
• The reliability of the board has increased. Fewer
components translates into less probability of error.
• Modifications are easier to make. Instead of cuts
and jumpers (for TTL), or throwing away a PAL, a
change is re-programmed.
• The need for de-coupling caps is reduced. All those
individual ICs are eliminated and in some cases the
distributed capacitance of the board may be enough
de-coupling.
• Power supply requirements are small. The active
current requirements are much smaller with
EPLDs. This in turn reduces the need for large power supplies and fans.
• Cable requirements and enclosure benefits have been
improved. Since EPLDs provide better integration
over TTL and PALs, the size of the system will be
smaller. This translates into fewer boards and cables.
'
• Inventory is reduced. One EPLD replaces many
TTL devices. Also, "on the shelf' programmed
,EPLDs can be reused in a pinch, PALs can't.
Less expense and probability of "escapes". The time
and cost of finding and fixing escape problems is re-

duced to one reprogrammable IC. In the field,' this
translates into,less "down time" for the customer and a
higher level of customer "goodwill" for the OEM.
Allows capability for customized hardware. Specific
customer requirements'can be implemented. Also, DIP
switches and configuration jumpers' may not be necessary in many cases, since configurations can be programmed into the EPLD.

Development Costs
As mentioned earlier, the costs of development are usually dismissed as NRE. One reason for this is the difficulty in pegging down these costs. However, while
money might be expendable at this stage, time is usually critical. Time saved at the front end can make a
difference in beitrlng the competition to market. The
following topics are presented for consideration. No
costs are assigned to them.
RESEARCH

The amount of time spent researching components,
component sources, and technical data can be very
large. Designs done with a large IC count require more
research and analysis time. Higher integration devices
require learning curv:e time, but, in the long run this
tends to reduce research time, especially in future designs.
PROTOTYPING

For most companies, prototypes are three to five level
wire wrap boards built by inhouse technicians or outside contractors. During prototype fab, a certain
amount of work has to be done to each IC. Part of this
work is, adding bypass caps, labeling chips, and lead
forming. In smaller companies, the board might be
hand wrapped. Larger companies might use an automatic wrapper. Once the board is wrapped, a continuity
check is done on each wire net to insure connections
and minimize shorts.
The tum around time for a protoboard is one to two
weeks and can be shoitened by payiRg a premium price.
An alternate way of shortening this time is to simplify
the board by using denser ICs.
DEBUGGING

Fixing bugs on a protoboard involves unwrapping and
wrapping connections, as well as replacing ICs. Making
mods on a TTL board is very time consuming and error
prone due to the large numbers of wires. Making mods
with PALs is expensive since the part usually has to be
junked. EPLDs in contrast, are re-programmable and
lend themselves to all the revisions that are common in
the early design stages.

2-212

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AP-307

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292030-16

TIME -DIVISION
MULTIPLEXED
SIGNAL

-'L

SYNC PULSE

n

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292030-17

Figure 11. Time Window Generator, TTL Circuit
2-213

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WINDOW CIRCUIT

PCB LAYOUT

Artwork quotes are based on several factors. These are,
board size, number of 16-pin chip equivalents, pad
count, and the chip to board packing ratio. The chip
equivalents are calculated by taking the total lead count
(ICs and discretes) and dividing by 16. Pad count is the
number of holes in the board. The packing ratio determines how much room an IC has around it. This is
critical because space is needed to place sockets, vias,
and trace bends. Currently, most service bureaus consider 0.75 square inches per IC to be the minimum
packing density. This figure applies to DIPs only, other
packages like SMT (Surface Mount Technology) will
improve on this. However, for standard DIPs anything
less than this might push the board into a multi-layer.

Background Information
In applications that involve time-division mUltiplexing,
it is useful to have a circuit that windows a specific area
ofthe bit stream [271. The circuit of Figure 11 is a TTL
implementation of such a circuit. The idea is to count
time slots from a known reference and at a certain decode, set and clear a latch. The output of the latch is
the time window, which might be used for further gating in other parts of the circuit. The TTL parts list is
detailed in Table 9.
The PAL alternative of Figure 12 is comprised of two
16L8s and one 16R4. While the component count has
been reduced from nine to three, there are still fourteen
extra interconnections.

During schematic evaluation, the bureau doesn't usually charge for traces directly. Because they can't foresee
the exact count, and they don't have time to count
them on the sheets, they make a judgment based on
previous jobs. If the board appears to be tight, their
autorouter (CAD based) won't be as efficient, and more
hand layout will have to be done. However, as more
CAD based service bureaus integrate schematic capture
front ends, the cost of traces and vias will be more
visible.

One 5C06O is needed to integrate the complete circuit.
Fourteen out of the sixteen EPLD macrocells are used,
and exernal traces are only the three I/O pins as shown
in Figure 13.

Because the evaluation is SUbjective, the final cost varies, and is a combination of charges. However, because
pad count can be determined easily, the overall price is
usually gauged against a pad price.

The production variables for the window circuit are
shown in Table lOa and lOb, and the production costs
in Table 11. The comparison shows three years of system costs for each implementation.

Production Costs

2-214

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AP-307

Table 9. TTL Component List for Window Generator
IC

Type

DIP

Icc(mA)

Area(ln 2)

$

U1
U2
U3
U4
U5
U6
U7
U8
U9

LS162
LS162
LS162
LS42
LS42
LS42
LS32
LS32
LS112

16
16
16
16
16
14
14
14
14

32
32
32
13
13
13
9.8
9.8
6

.24
.24
.24
.24
.24
.24
.21
.21
.21

.49
.49
.49
.39
.39
.39
.18
.18
.29

,

-

_vco

-

0

U2 0
l6R8 0
0
0
0

r- ,

---

-

Cll
Cl0
C9
C8
C7

RCO

oj

,
Ul
l6R8

0
0
0
0
0
0
0

C6
C5
C4
C3
C2
Cl

..... ,

,
,
,
,

,

, rU3
l6R4

,
,

co

,' r-,
,~

Wl
W2

0
0

--

;::=:::,

Figure 12. Time Window Generator, PAL Circuit

VCO

,

ClKl

Vee

I/o
W1

W2
GND

ClK2
292030-19

Figure 13. Time Window Generator, EPLD Circuit

2-215

292030-18

inter

AP-307

Inventory:

Costs
Incoming insp. ($/pin)
Storage ($/sq.ft./yr)
Maintenance ($/part)
Processing ($/part type/yr)
Safety stock (%)

Manufacturing:

$0.010
$20.000,
$0.030
$0.520
2%

Costs
PCB fab. ($/sq.in.)_
Assembly ($/part)
Test ($/part)
Rework ($/pin)
QC ($/pin)
Power ($/watt)
Interconn
Program ($/part)
Caps. (each)

$0.200
$0.100
$0.150
$0.020
$0.004
$1.000
$0.020
$0.250
$0.005

(a)

Integrated Circuits
Component Count:
Package
DIP14
DIP16
DIP20
DIP24

TTL

PLA

EPLD

3
6
3

ICs

Types

TTL
PLA
EPLD

4
2
1

1

Circuit Requirements:

Icc (max)

TTL circuit (total rnA).
PLA circuit (total rnA).
EPLD circuit (total rnA).

Interconnects

160
360
15
(b)

Tables 10a and b. Window Circuit Cost Variables

2-216

52
14
0

inter

AP-307

Table 11. Window Circuit Production Costs
AVERAGE COMPONENT COST

Package

DIP14
DIP16
DIP20
DIP24

TTL

PLA

Year 3

Year 2

Year 1
EPLD

$0.22
$0.44

TTL

PLA

EPLD

$0.19
$0.37
$2.00

TTL

PLA

$0.17
$0.26
$1.70

.

$1.56
$4.20

$6.00

EPLD

$2.90

PRODUCTION COSTS

Components

Year 3

Year 2

Year 1
Item
(costs per part)

EPLD

. TTL

PLA

EPLD

TTL

PLA

EPLD

TTL

PLA

$0.367

$2.000

$6.000

$0.310

$1.700

$4.200

$0.230

$1.560

$2.900

$0.153

$0.200

$0.240

Incoming Insp.

$0.153

$0.200

$0.240

$0.153

$0.200

$0.240

Inventory
Maintenance
Storage
Processing

$0.029
$0.032
$0.231

$0.038
$0.042
$0.347

$0.045
$0.050
$0.520

$0.029
$0.032
$0.231

$0.038
$0.042
$0.347

$0.045
$0.050
$0.520

$0.029
$0.032
$0.231

$0.038
$0.042
$0.347

$0.045
$0.050
$0.520

Printed Circuit Board
Fabrication
Trace costs
Assembly
Board test
Rework
QC

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.060
$0.093
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.060
$0.093
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.060
$0.093
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

Power Supply

$0.089

$0.600

$0.075

$0.089

$0.600

$0.075

$0.089

$0.600

$0.075

Total Cost/Part

$1.385

$3.754

$7.422

$1.328

$3.454

$5.622

$1.248

$3.314

$4.322

$9.943

$4.322

$0.094
$0.468
$0.750
$0.015

$0.000
$0.058
$0.250
$0.005

Total Cost/System

$12.463 $11.263 $7.422 $11.953 $10.363 $5.622 $11.233

Additional Costs/System
Programming loss
Safety stock
Programming fee
De-coupling caps

$0.000
$0.165
$0.000
$0.045

True mfg. cost/system

$12.673 $12.748 $7.797 $12.137 $11.740 $5.961 $11.381 $11.269 $4.635

$0.120
$0.600
$0.750
$0.015

$0.000
$0.120
$0.250
$0.005

$0.000
$0.140
$0.000
$0.045

2-217

$0.102
$0.510
$0.750
$0.015

$0.000
$0.084
$0.250
$0.005

$0.000
$0.104
$0.000
$0.045

intJ

AP-307

The production costs again show that the system cost
for the first year is better with EPLDs. The two consecutive years show that the declining ptice of EPLDs
make them an excellent candidate for systems that will
ramp up production at that time.

Window Circuit Conclusion
The TTL version of the circuit was implemented with
MSI counters and decoders. As a result, the PAL implementation was bound by the number of count bits
and had to be programmed into two PALs. In circuits
like this, it is useful to rewire the decode for different
counts depending on the application. The PAL implementation allows this by incorporating the decode arid
output latches into one IC.
The EPLD implementation tackles the MSI integration
quite easily and also provides the capability to reprogram the decoder. Since the counter and output latches
consist of fourteen registered outputs, the sixteen macrocells of the 5C060 easily accommodate the needed
functions.

SUMMARY
We have examined the hidden costs of production and
how they differ for several logic alternatives. By examining these costs, we have shown that while an EPLD is
presently a more expensive part; it's level of integration
reduces system costs and improves reliability. The following items should be conSidered when evaluating logic alternatives:
• system cost is determined by more than component
cost
• system cost and reliability is influenced by the type
and amount of components used
• semiconductors have a life cycle that determines
their present price at design, and at production time
In summary, when all system costs. are considered,
EPLDs can provide cost savings to the design and production of most board designs.

REFERENCES
1. The Future Is Now: Extending CAE into test of custom VLSI.
Robert S. Broughton, Tektronix.
Michael G. Brashier, Tektronix.
IEEE International' Test Conference Proceedings,
1984

2. Reducing The Cost of Quality Through Test Data
Managment.
Paul N. Manikas, GenRad Inc.
Stephen G. Eichenlaub, Harvard University.
IEEE International Test Conference Proceedings,
1983 .
3. A Quantitative Analysis Of The Trade-offs Between
Higher Capital Investment and Higher Yield In PCB
Testing.
Mark A. Myers, Teradyne Inc.
IEEE International Test Conference Proceedings,
1984
4. An Analysis Of The Cost And Quality Impact Of
LSI/VLSI TechnOlogy On PCB Test Strategies.
Mark A. Myers, Teradyne Inc.
.
IEEE International Test Conference Proceedings,
1983
5. IC Quality Control By The User.
Roger Dunn, Xerox Corp.
IEEE International Test Conference Proceedings,
1983
6. An Analysis Of The Economics of Self Test.
P. Varma, University of Manchester.
A. P. Ambler, University of Manchester.
K. Baker, GEC Research Labs.
IEEE International Test Conference Proceedings,
1984
7. In Circuit Testability Factors: Shoot With A Rifle.
Douglas W. Raymond, Zehntel Production Services.
IEEE International Test Conference Proceedings,
1984
8. Seven Steps To Zero Defects.
D. W. Rudd,AT&T Technologies.
Circuits Manufacturing, June 1986
9. Rework Forum
Donald Ford, Senior Editor.
Circuits Manufacturing, September 1986
10. Manufacturing Defect Analyzers: Annual Roundup.
Evaluation Engineering magazine, August 1986
11. Assembly: Automation Makes It Better.
Roland W. Roy and Gordon Weeks, Andover Controls.
Circuits Manufacturing, February 1986
12. Shrinking Lines Squeeze Processes.
Jerry Murray, West Coast Editor.
Circuits Manufacturing, September 1986
13. Ribbon Cable for Reliable Interconnections.
Bennett W. Brachman, Xport Trading Inc.
Electronic Packaging and Production magazine,
July 1986

2-218

inter

AP-307

14. TQC and JIT: Partners In Production.
Rick Walleigh, Hewlett Packard.
Circuits Manufacturing, February 1986
15. Automated Handling/Sorting: Multisite Development Moves to Back Burner.
Evaluation Engineering magazine, May 1986
16. Software Charts The Course of Component Testing.
Ronald Pound, Editor.
Electronic Packaging and Production magazine,
June 1986
17. Complexity, PLDs Drive The Market.
Evaluation Engineering magazine, July 1986
18. Intel User Defined Logic Handbook.
Intel Corp. 1986
19. VLSI Semicustom Design Guide.
CMP Publications, Summer 1986
20. AMD Programmable Array Logic Handbook.
Advanced Micro Devices, 1984

21. Handbook Of Industrial Engineering.
Gavriel Salvendy, Editor, Purdue University
John Wiley & Sons Publications
22. Components QualityIReliability Handbook.
Intel Corporation.
23. The Cost Edge.
DM DATA Corp.
Scottsdale, AZ
24. Semiconductor Purchasing Strategies Integrated
Circuits Engineering Corp.
Scottsdale, AZ
25. Status 1986 Integrated Circuits Engineering Corp.
Scottsdale, AZ
26. EDN Semicustom Design Series
EDN Magazine, 1985
27. EDN Design Ideas
EDN Magazine, 1985

2-219

inter

APPLICATION
, NOTE

AP~321

November 1988

Fitting the 5C180

TODD KOELLING
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292053-001
2-220

inter

AP-321

INTRODUCTION
In many ways, fitting the SC180 is like climbing a
mountain. Just when what appears to be the summit is
reached, another summit is revealed behind it. This
may occur several times before the actual summit is
surmounted.
Likewise, fitting a SC180 may have several false summits. Just when one has conquered what appears to be
the "problem", another problem often appears behind
it. This may occur several times before the design fitting is complete.
This application note addresses the problems that can
be encountered when trying to fit a SC180 and offers
suggestions on how to get past them. The key to the
climb is examining what resources are still available
after the software' complains that a particular resource
is not available.

QUAD A REGISTERS

SUMMIT NUMBER ONE: PIN
ESTIMATE
Before keying in the design, it is best to estimate the
I/O pin requirements. This is done by counting the total number of inputs to the device and outputs from the
device.
PROBLEM: Not enough Input Pins
HELP: Run all synchronous clocks through Clock
Buffers (CLKBs). Shared clocks may use the same
CLKB output which may result in reduction from 4
CLK input pins to 1 CLK input pin (see Figures la &
',PLS II ver. 1.1 or later is ESSENTIAL for 5C180 designs as the fitting
algorithm was significantly Improved with thiS release.
'IPLS II ver. 1.5 or later is HIGHLY RECOMMENDED as the error
messages and Utlllzalion Report Files were significantly enhanced
with thiS release.

QUAD D REGISTERS
00

OA
RON,

RON,

CLK1PIN
INP
CLK,1
CLK4PIN
INP
CLK4

CLK3PIN
INP
CLK3
CLK2PIN
INP
CLK2
OC
RON,

QUAD B REGISTERS

QUAD C REGISTERS
292053-1

Figure 1a. Summit One-Input Clocks Before

2-221

inter

AP-321

QUAD X REGISTERS

QUAD X REGISTERS

ClK4PIN
INP

ClKS

0

ClK4

ClK3PIN
INP
ClK3

ClKS

0

QC
RONF

QUAD X REGISTERS

QUAD X REGISTERS
292053-2

Case:

ClK 1 = ClK4 frequency
ClK2 = ClK3 frequency

Figure 1b. Summit Two-Input Clocks After
Ib). This also frees the registers that the clock feeds
from the synchronous clock pin quadrant, increasing
the chance of fitting later on. THIS PRACTICE IS
RECOMMENDED FOR ALL DESIGNS.
PENALTY: Input setup time is shortened. (See Synchronous vs. Asynchronous A.C. Characteristics in
Data Sheet).
If clock buffering cannot solve the problem, the design
must be repartitioned to reduce the number of input
pins. Repartitioning is explained in the next section.

SUMMIT NUMBER TWO: MACROCELL
ESTIMATE
If the I/O pin requirements can be met, the next step is
to consider the macrocell requirements. The total macroce11 count can be estimated by counting the number
of outputs plus the number of internal registers.
PROBLEM: Not enough macrocells
REPARTITIONING: Unless the fundamentals of the
design can be changed, this error means that the design

2-222

inter

AP-321

must be repartitioned. This is done by removing part of
the circuitry and placing it in a second device such as a
5C060 or 5C090. The 5C06O and 5C090 are recommended since their architectures (and therefore their
ADFs) are nearly identical to those of the 5C180 (the
NOCF and COCF primitives are the only exceptions).

FIX: In order to tell the LOC software that the clock
for a flip-flop will be driven by an equation or gate
logic, a Clock Buffer (CLKB) must be placed between
the equation or logic and the register clock input for
each register that is asynchronously clocked.

Portions of the 5Cl80 ADF can b~ easily transferred
into one of the smaller devices or the smaller device
ADFs can be transferred back to the 5C180 if sufficient
room is freed up later on. IT IS RECOMMENDED
THAT FOUR OR FIVE UNUSED MACROCELLS
BE LEFT IN THE 5C180 FOR USE BY LATER
STAGES.

SUMMIT NUMBER FIVE:
ASYNCHRONOUS CLOCKS AND
OUTPUT ENABLES

SUMMIT NUMBER THREE:
SUCCESSFUL TRANSLATION
With the design entered, the next summit is successful
translation.
ERROR: '''ERR-MAC-No macrofunction for: ...
EXPLANATION: The Macro Expander Module cannot find a macro for a network element.
FIX: Make sure correct search path is available for
macro libraries. Check for typo or syntax error. Ifusing
schematic capture, make certain that only valid EPLD
library symbols were entered.
ERROR: Any"·**ERROR-XLT-... "
EXPLANATION: The Translator found a problem
with the way the design was entered. These errors are
basically syntax errors which violate ADF format. It
may be a simple typo, missing parenthesis or missing
semicolon. Remember that the iPLS II LOC does differentiate between upper and lower case letters. If using
schematic capture, make sure that all device inputs and
outputs have pin symbols and that all the pins and
wires are properJ,y labeled.
FIX: Refer to your iPLS II manual or call the EPLD
Hotline, 1-800-323-EPLD, for help on the tough ones.

ERROR: "'ERROR-XLT-OE with asynchronous
clock not allowed
EXPLANATION: Asynchronous clock and output
enable can't be used at the same time in the same macrocel!. The 5Cl80 basic macrocell architecture, Figure
2, sho\Vs why. A single p-term is shared between the
asynchronous clock and the output enable. This means
that both switches in the diagram can be up or both
switches can be down. By trying to use a p-term output
enable with an asynchronous clock, the top switch
would have to be down while the bottom switch is up.
This cannot be done as then the register would be
clocked and enabled with the same signal.
WORKAROUND: To get around this problem, one of
the signals must be routed through another macrocell
(see Figures 3a-b). The clock could be generated in another macrocell, sent out to a pin, then sent back in on
the synchronous clock pin. Alternately, in a first macrocell the register is placed as an asynchronously
clocked NORF. In a second macrocell, the register
feedback is sent out to a pin using a CONF enabled by
the desired enable signal.
PENALTIES: Routing the clock through a separate
macrocell and back in offers slightly better performance-since the synchronous clock to ouput time is
faster than a second macrocell delay, but this implementation uses a lot of resources-three pins and two
macrocells. The second method, routing the feedback
from the register back and controlling the ·output enable in a second macrocell is more straightforward and
uses less resources.

SUMMIT NUMBER FOUR: REGISTER

CLOCK INPUTS

SUMMIT NUMBER SIX: GREATER
THAN ONE PRODUCT-TERM
REGISTER CONTROLS

ERROR: "'ERROR-XLT-Clock input must be driven by INP or CLKB

ERRORS: "'INFO-FlT- Eqn.
PTerm(s), on OE signal OE3

EXPLANATION: The clock for a flip-flop must be
driven synchronously by a direct quadrant clock pin
input (INP) or asynchronously through a Clock Buffer
(CLKB). This problem occurs when an equation or
gate logic is connected directly to the register clock
input.

"'INFO-FITCLEAR input (CLRl)

Illegal

too

big,

inversion

4/-1
of

EXPLANATION: As shown in the basic 5C180 macrocell architecture, Figure 2, only one product term
(multiple input AND gate) is available for the register

2-223

inter

,AP·321

clock, clear, and output enable. This means that any
control resource containing an OR gate following Boolean minimization will not fit. Likewise, any Control
resource requiring an invert will not fit either. To find
the offending signal, LOOK AT THE EQUATIONS
SECTION OF THE LOGIC EQU;).TION FILE
(.LEF).

elr Fitting Trick
PROBLEM: Register clear input breaks 1 p-term resource limit
TRICK: If register has D input of either
GND, substitute SR Flip-Flop.

WORKAROUND: Once the offending signal has been
'located, it must be routed through another macrocell
using an NOCF primitive (see Figure 4a-b).1fthe control signal is a clock, then a clock buffer (CLKB) must
also be added.

or

EXPLANATION: D-type EPLD register has only 1
AND gate feeding CLR; SR Flip-Flop utilizes logic ar, ray for CLR input allowing a max of 8 AND gates
(p-terms) for the CLR resource.
PENALTIES: SR Flip-Flop is synchronously clocked.
D register has asynchronous clear.
'

PENALTY: Unless a trick explained below can be
used, this routing results in the use of an additional
macrocell and a doubling of the signal propagation delay.
AND ARRAY

vce

SYNCHRONOUS
CLOCK

vee

OE/ClK

l~ElECT

OE

D- -{

t-t--

ClK

' - - t--'
EPROM
CEll
ONNECTION

II

, PRODUCT

@

TEr

~ s-w~
~D=J
~1~£,c
D-

\

J

lOGIC

r-;=

D-r-'\

~

~

~

~

~

'~

~

~

T1 1 T 1

I/O

SELECTION

FEEDBACK
SELECTION

RESET

L...J

~

FEEDBACK SIGNALS

INPUts AND I/O

292053-3

Figure 2. Basic Macrocell Architecture of the 5C180

2-224

Ap·321

OE--------------------------------------~

FFI
RONF

Dl--------------------------------~
AND2

ClKB

a

EN----:,.i
ClK ____--=2'L_~

292053-4

Figure 3a. Summit Five-Asynchronous Clock and OE Before

OE----------------------------,
FFI
NORF

Dl-----------------------------~
AND2

ClKB

F

2

a

EN----.....:~

ClK ___.....:2'·L

CONF
292053-5
(Recommended Method)

Figure 3b. Summit Five-Asynchronous Clock and OE After

1 AND3

4

2
3

7474X
Q

3

5

Q 6

C
Cl

AND3

TOO MANY P - TERMS
FOR CLEAR RESOURCE

292053-6

Figure 4a. Summit Six-Too Many p.Terms on Control· Clear

2-225

inter

AP-321

1

2
3
0

4

1

2
3
1 S

Q

5
NOSF

2
3 R
AND3

C

2

4

F

3

292053-7

Figure 4b. Summit Six-SR Flip-Flop Equivalent Implementation

OE Fitting Trick
PROBLEM: Output enable on an equation or combinational equation exceeds 1 p-term resource limit.
TRICK: If a low output rather than a tri-state output
can be tolerated, the signal can be gated rather than tristated.
EXPLANATION: Run the OE and the equation
through an AND gate before going to a pin. The output
of the pin will only follow the equation when the enable
is active, otherwise it will be zero.
PENALTY: Forced low rather than tri-state output.

SUMMIT NUMBER SEVEN: NOT
ENOUGH P-TERMS FOR AN
EQUATION
ERROR: ***INFO-FIT- Too many PTerms to fit in
any MCell: 10/8 for EQN.
EXPLANATION: Since the 5C180 has a maximum of
eight product terms per macrocell, there's a chance that
this number may be exceeded by the requirements of an
equation.' If so, the equation is cited by the LOC and
can be examined by looking at the EQUATIONS section of the .LEF.

WORKAROUND: The workaround for this situation
may already be in place! If any portion of the logic (or
equation) is routed into an NOCF or CONF elsewhere
in the design, that feedback can be taken and, routed
into the equation (see Figure 5a-b). This means a single
feedback node-rather than several nodes will now feed
the equation and thereby reduce the p-term count. (If
the feedback is to be taken from a CONF primitive, the
CONF must be changed to a COCF or COIF to make
the feedback available.)
If part of the logic or equation is not routed into a
NOCFor CONF elsewhere in the design, then part of
the equation must be routed through a NOCF, COCF,
or COIF primitive. A NOCF is recommended as it does
not use a pin if placed in a global macrocell. If several
equations are in vio,lation of the eight p-term maximum, try to choose a group of logic that is common to
all of the equations. In this manner, the p-term count
for several equations can be brought down with the use
of single extra macrocell, rather than the use of a macrocell for each equation.
PENALTY: Any time a portion of an output signal
must be routed through another macro~ell a speed penalty is incurred (roughly one propagation delay). If an
already existing macrocell can be found, then there is
no architectural penalty. If a new one must be created,
then another macrocell is added to the total macrocell
count.

2-226

intJ

AP-321

-------~
-------~:.:.:
_ _ _ _ _ _ _ _3'fi
_ _ _ _ _ _-.::4.,.,
~--.......:..t
_ _ _ _ _ _ _.;:.51
PTERt.A1------..:6i/.1

PTERt.A6
PTERt.AS
PTERt.A4
PTERt.A3
PTERt.A2

PTERt.A9 - - - - - - - e ; ' "
PTERt.A8 ------~4.,.,
PTERt.A7 - - - - - - . . . . ; ; : ; . . - -

'>--"'C> EONA

6 P-TERMS

CONf

r----.:.t >--c> EONB

9 P - TERMS

CONf
292053-6

Figure Sa. Summit Seven-Too Many P-Term Equation Before

1

PTERt.A6 -------~
2
PTERt.A5 -------~:.:.:
3
PTERt.A4 ------~4..
~-PTERt.A3 - - - - - - - . : : . , .5 ,
PTERt.A2
6
PTERt.A1-------~

....~ >--c> EONA

-------.;:.r-

6 P - TERMS

COCf

f

fBK

1

2
PITRt.A9-------e'"
3
PTERt.A8 ------~.,.,
4
PTERt.A7 -------~-

~---~

>--c> EONB

4 P-TERMS

CONf
292053-9

Figure 5b. Summit Seven-Too Many P-Term Equation After

SUMMIT EIGHT: MACROCELL
RESOURCES EXCEEDED

THE FINAL ASCENT: NOT ENOUGH
GLOBAL FEEDBACK!

ERROR: "'INFO-FIT- Design requires too many
macrocells

Congratulations! If you have made it this far, you have
demonstrated courage, intelligence and tenacity beyond
that of the average climber. You will soon be rewarded,
but first there is one more obstacle to be overcome.
Welcome to the North Face of local/global feedback!

EXPLANATION: If this error didn't occur at the beginning, there's a good chance summits five, six or seven will push the rnacrocell count over the limit. (Remember that the macrocell count includes not only the
outputs, but also the buried resources such as NOCFs,
NORFs and NOTFs). To find out exactly how many
macrocells the design requires, LOOK AT THE NETWORK: SECTION OF THE LOGIC EQUATION
FILE (.LEF). The inputs list in the LEF wi11list both
the outputs and all the buried resources required by the
design. If the count exceeds 48, then too many macrocells are required.
FIX: Repartition. The same applies if the number of
input pins is exceeded.

A Word About Local/Global Feedback
First of all, why does local/global feedback exist? The
answer can be found in the graph shown in Figure 6.
The propagation delay versus array size is shown for
the 5C060/090/180 family. As the number of inputs
into the array increases, the propagation delay increases ...exponentially. If all the inputs and feedback were
made global, the 5Cl80 would have 136 inputs feeding
each array (remember that both true and complement
polarities must be fed into the array of a PLD architec-

2-227

AP~321

ture). This would have put the 5Cl80 Tpd in the 250 300 ns range! By making eight macrocells local for four
quadrants, the number of array inputs was dropped to
88 and the Tpd subsequently decreased to 75 ns.
The tradeoff to the local/global routing scheme is more
difficult design routing. With the help of the iPLS II
and a couple of tricks, however, most designs can still
be fit.

"il:
-=."

60
50
40

where GLOBAL means that the signal feeds all macrocells and LOCAL means that the signal only feeds the
macrocells in its quadrant.

Clock Input Pins '
The clock input pins feed the global bus like the regular
inputs, except the synchronous register input connection is dedicated to a particular quadrant. Thus, each
clock input can be used as a logic input in all quadrants
or a clock input in its own quadrant. To be used as a
register clock input in a quadrant outside its own, however, it must be tapped from the global bus via an asynchronous clock buffer (CLKB).

Total
90
Propagation 80
Delay
70
~

4. Local macrocell pin/feedback paths are LOCAL.

I-------~

Global Macrocell Feedback

~ 30
20
10

OL-__~T_+_+_+_+-+-+-~~I

o

10 20 30 40 50 60 70 80 90

# OF

ARRAY INPUTS
Q920S3-10

Array Size
Device

5e060
5e090
5elBO

Array
Inputs

40
72
88

TpD

The feedback path is local for GLOBAL macrocells
while the I/O input is global for all GLOBAL macrocells. Thus, changing the feedback of a register or combinational equation from a standard feedback to I/O
pin feedback path will change the routing from local to
global. The iPLS II LOC automatically recognizes and
performs this through a process called "promoting".
With the promotion process, global routing can be obtained on signals that would otherwise remain local.
"'INFO-FIT- Promoted "TEQNf" from NOCF to
COIF

45 ns
50ns
75 ns

Array size increases Capacitance
Capacitance Increases Propagation Delays

Burying a Register in a Global Cell

Figure 6. Propagation Delay vs. Array Size for
the S'C060/090/180 Family

Because the global macrocells have separate register
and I/O pin feedback paths; it is possible to "bury" a
register or equation by disabling the output buffer and
still use the pin as an input. The iPLS II LOC automatically assigns an input to the pin of a buried register
macrocell if it is necessary and possible. Such assignments are documented in the Utilization Report File
(.RPT). If manual assignment is desired, it may be performed by placing the input pin assignment in the ADF
INPUTS: list and assigning the buried register feedback
to the same pin in the OUTPUTS: list (Figure 8). Registers or equations can only be buried on global macrocells, since local macrocells only have one feedback
path that is used for either the register or the pin feed.
back.

A Few Notes
The globaillocal macrocell assignments are shown in
Figure 7. Please note that:
1. Dedicated input pins are GLOBAL.
2. Global macrocell I/O pin are GLOBAL.
3. Global macrocell internal feedback paths are LOCAL.

2-228

intJ

AP-321

QUADRANT A

QUADRANT D

,',~:i!'

,:'~-

,.:'~t-'~

~,,~if

I/O

~,~,,\

I/O

~.

I/O

~3: "
,,:"~r
IIACRQeW. S

c

<>

i

i

!,

~
0

"''''CROC£U. Ii

I

IIIlcaoa:LL 7

i
~,

IjACROCD.LI

MACROCDl Ii

i...
...~,

~10

68

I/O

«

I/O

IU

IIACROCILL l'

I

IIACRQeW. 17

'I

I

I

'"i

iI

~

I/O
I/o

~

t.lACROCD.L 29

I/O
I/O
I/O

QUADRANT B
292053-11

~"

_

-'

GENERAL MACROCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS

Figure 7. 5C180 Block Diagram

2-229

AP-321

r - - - NOTF
INP
INP010D_--

QI-

1 T

2

c
3

F

FBK010
292053-12

Buried Register Pin' Assignment in ADF

Intel
PLDO Apps
July 27, 1988
5C180 Buried Reg Pin Assignments
PART: 5C180
INPUTS: A@15, B@lO, CLK@17
OUTPUTS: FBK@lO

% Assign input B to pin 10 %
% Assign buried reg feedback FBK %
% to pin 10 (GLOBAL macrocell 9) %

NETWORK:
A = INP(A)
B = INP(B)
CLK
INP(CLK)

% Inputs %

=
FBK =NORF(IN,CLK,GND,GND)

% Buried Register %

EQUATIONS:
IN

=A * B * FBK;

% Register Input Equation %

END$
Figure 8. Assigning Buried Reg in Schematic

Two Global Fitting Tricks
If the LOC is unable to fit the design, there are a couple
of manual tricks that may help:
PROBLEM: NOT ENOUGH GLOBAL FEEDBACK

PENALTIES: There may be a slight timing discrepency between the two macrocells for combinational logic,
but any discrepency will be small « 2 ns).
PROBLEM: NOT ENOUGH GLOBAL FEEDBACK
RESOURCES AVAILABLE: EXTRA INPUT PINS

RESOURCES
CELLS

AVAILABLE: EXTRA

MACROTRICK: Send out the signal that needs to be global and
externally connect it to one of the input pins.

TRICK: Duplicate the macrocelliogic that needs to be
global in two (or more) regions with appropriate re-'
naming (see Figure 9).

EXPLANATION: Inputs feed the global bus, making
the signal available in all quadrants.

EXPLANATION: This makes the signal available in
two regions via two local macrocells rather than one
which can't be global.

PENALTIES: An output buffer plus input buffer minus feedback delay is added (approximately 25 ns). An
external connection must be made on the board.

2-230

infef

AP-321

NOTE:
For the previous tricks, look at the Utilization Report
(.RPT) file. The "Interconnect Cross Reference" is
particularly useful for examining the routing requirements of the design.
If the previous tricks cannot be done (see Figure II)
and scrutinization of the Interconnect Cross Reference
reveals no other way to achieve the desired routing,
repartitioning is necessary. That is, place a chunk of
interconnected logic into a 5C060 or 5C090 and go
back to the start.

CONCLUSION
Fitting the 5CI80 is a process with many stages. One
difficulty may hide the next and fixing one problem will
sometimes uncover another. Equipped with the iPLS II
LOC and a few tricks, however, fitting can be accomplished.

A1
AND2

2
4

o

7474X

PR

2 0

0

5

QUAD B
2

3

Q

C

6

CL

01

QUAD B
OR

'--________-:;11
___________________________________
29

0
1
~
2

CON,
292053-13

AND2

4

0

7474X

PR

2 0

0

5

QUAD C
2

3

Q 6

C

CL

02

QUAD C
OR2

2

o
CONF
292053-14

Figure 9. Not Enough Global Feedback Extra Macrocells-Fit

2-231

inter

AP-321

2
4

0

2 D

QUAD 8

7474X

PR

0

5

OOUT

QUAD B

1
2

3

Q

C

CONF

6

CL

QUAD B

-----------------------~------------------~~~~

CONF
EXTERNALLY CONNECT
Ip----------------------------------------------------- -----------------~

:
I

:_·OIN

QUAD C

J
D>-O------..:..t>-e>

INP

D _ _G_L_O_B_A_L_______-;,-~

OR2

1

2

CONF

292053-15

Figure 10. Not Enough Global Feedback Extra Inputs-Fit

1
2
4
0

7474X

PR

2 D

0

5

0

QUAD B
2

3

Q

C

6

CL

QUAD.B
OR

____________________

t-________~1~ ~
0
1
2

~r-------~2

CONF

CAN'T REACH

QUAD C
OR2

2

o
CONF

Figure 11. Not Enough Global Feedback-N.o Fit
2-232

292053-16

inter

ER-22

ENGINEERING
REPORT

September 1988

5C180 vs. EP1800:
A Comparison of
Device Specifications

,

LILIYAS KOUMIS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 294006-001
2-233

ER·22

INTRODUCTION
This engineering report compares the Intel 5C180

EPLD with the Altera EPI800 EPLD showing how the
specifications for the two devices relate to one another.
Because Intel and Altera use a different methodology
for specifying parameters for this device, the most signifiCant hurdle to overcome when performing a comparison is to correlate the different specs. That correlation is performed here in table format.

In summary, the Intel parts meet or exceed the specifzcations for the equivalent Altera parts. The equivalent InteVAltera devices are shown below. All numbers are
based on the most current data sheet specs. (Intel
5C180 Data Sheet, order number 290111-005. Altera
1988 Data Book.)
Intel
5C180-70
5C180-75
5C180-90

Altera
EP1800-2
EP1800-3
EP1800

The tables that follow compare each spec. listed in the
Intel 5C180 data sheet for each of the three versions of
the device. A description of the parameter is listed, followed by the Intel mnemonic and the Intel spec. The

equivalent Altera value is then listed. The formula used
to determine the Altera value is provided on a second
line to aid in correlating Altera's internal timing numbers to Intel's external numbers. Intel specifies device
parameters (i.e., input pin to output pin).' while Altera
specifies internal timing paths (i.e., input pad delay,
logic array delay, etc.). Intel's specifications reflect
numbers that can be measured, rather than internal
numbers that must be estimated from external measurements. Altera's internal timing specifications appear at
the top of each page.
Note that a new spec. has been added to many of the
parameters. This new spec. is "enhanced output". Enhanced outputs are macrocells 1 through 4,21 through
24, 25 through 28, and 45 through 48. Enhanced macrocells are 5 ns faster than the standard macrocells.
Intel guarantees the specifications of the 5C 180 devices
listed in the 5C180 Data Sheet. Our Manufacturing
group conducts extensive testing of the devices with
appropriate guardbands to guarantee all published values under worst case conditions. This testing ensures
proper operation across widely divergent applications.
Also, every Intel product must pass an extensive qualification program before it is released to the marketplace. Strict quality controls and monitors are applied
during the qualification and manufacturing processes.

2-234

inter

ER-22

Inte15C180-70 vs. Altera EP1800-2
COMBINATORIAL MODE (5C180-70 VS. EP1800-2)
ALTERA

INTEL
Parameter

Symbol

Min

Max

Symbol

Min

Max

Units

tlO
tiN
tLAO
tLAOe
too
tzx
txz
tiC
tlCe

5
10
40
35
15
15
15
40
35

ns
ns
ns
ns
ns
ns
ns
ns
ns

65

tp01

65

ns

tPD1e

60

tP01e

60

ns

I/O pin to comb. output
(tiO + tiN + tLAO + taD)

tpD2

70

tp02

70

ns

I/O pin to enhanced comb. output
(tiO + tiN + tLAOe + too)

tPD2e

65

tP02e

65

ns

INPUT to output enable
(tiN + tlAO + tzx)

tPZX1

65

(2)

65

ns

INPUT pin to enhanced output enable
(tiN + tLAOe + tzx)

tPZX1e

60

(2)

60

ns

I/O to output enable
(tiO + tiN + tLAO + tzx)

tPZX2

70

(2)

70

ns

I/O pin to enhanced output enable
(tiO + tiN + tLADe + tzx)

tPZX2e

65

(2)

65

ns

INPUT to output disable
(tiN + tlAD + txz)

tPXZ1

65

(2)

65

ns

INPUT pin to enhanced output disable
(tiN + tLADe + txz)

tPXZ1e

60

(2)

60

ns

tPXZ2

70

(2)

70

ns

I/O pin to enhanced output disable
(tiO + tiN + tlADe + txz)

tPXZ2e

65

(2)

65

ns

Asynchronous Clear
(tiO + tiN + tiC + too)

tClR

70

(2)

70

ns

I/O pin pad & buffer delay
INPUT pin pad & buffer delay
Logic array delay
Enhanced logic array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

(1 )
(1 )
(1 )
(1)
(1)
(1 )
(1 )
(1 )
(1)

INPUT pin to comb. output
(TIN + tlAO + too)

tpD1

INPUT pin to enhanced comb. output
(tiN + tLADe + too)

110 to output disable
(tiO

+ tiN + tLAO + txz)

NOTES:

1. Intel does not spec internal timings of the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.

2-235

ER-22

SYNCHRONOUS MODE (5C180-70 VS. EP1800-2)
ALTERA

INTEL
Parameter

Symbol

Min

Max

Symbol

Min

tsu
tlO
tiN
too
tlAO
tlAOe
tiCS
tFO

12

Max

Units

Internal register setup time

(1 )

1/0 pin pad & buffer delay
INPUT pin pad & buffer delay
OUTPUT buffer and pad delay
Logic array delay
Enhanced logic array delay
System clock delay
Feedback delay

(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )

ns

Max. Frequency (no fdbk)
(1 I [INPUT pin setup to CLKx))

fMAX

20.8

Max. Count Frequency (with fdbk)
(1/tCNT)

fCNT

16.1

INPUT pin setup to CLKx(3)
(tiN +tLAO + tsu - tiN - tiCS)

tSU1

48

(2)

48

ns

tSU2

53

(2)

53

ns

tSU1e

43

(2)

43

ns

tSU2e

48

(2)

48

ns

5
10
15
40
35
4
10

ns
ns
ns
ns
ns
ns

fMAX

20.8

MHz

fCNT

16.1

MHz

n~

1/0 pin setup to CLKx(3)
(tiO

+ tiN + tLAO + tsu

- tiN - tiCS)

INPUT pin setup to CLKx(4)
(tiN + tLAOe + tsu - tiN - tiCS)

1/0 pin setup to CLKx(4)
tlO

+ tiN + tLAOe + tsu

- tiN - tiCS)

Clock High to Output Valid
(tiN + tiCS + too)

28

tco

(2)

29

ns

Register output feedback to
register input-internal path
(tFO + tLAO + tsu)

teNT

62

tCNT

62

ns

Clock High Time

tCH

24

tCH

24

ns

Clock Low Time

tCl

24

tCl

24

ns

NOTES:
1. Intel does not spec internal timings on the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.
3. For global and standard macrocells.
4. For enhanced macrocells.

2-236

inter

ER-22

Intel 5C180-75 vs. Altera EP1800-3
COMBINATORIAL MODE (5C180-75 VS. EP1800-3)
INTEL
Parameter

Symbol

Min

ALTERA
Max

1/0 pin pad & buffer delay

(1)

INPUT pin pad & buffer delay
Logic array delay
Enhanced logic array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

(1)
(1 )
(1 )

(1)

INPUT pin to comb. output
(tiN + tlAD + tOD)

tpD1

70

tPD1e

Symbol

Min

Max

5
12

Units

39

ns
ns
ns
ns
ns
ns
ns
ns
ns

tpD1

75

ns

65

tPD1e

70

ns

tpD2

75

tpD2

80

ns

tPD2e

70

tPD2e

75

ns

INPUT to output enable
(tiN + tLAD + tzx)

tPZX1

70

(2)

75

ns

INPUT pin to enhanced output enable
(tiN + tLADe + tzx)

tPZX1e

65

(2)

70

ns

tpZX2

75

(2)

80

ns

I/O pin to enhanced output enable
(tiO + tiN + tlADe + tzx)

tPZX2e

70

(2)

75

ns

INPUT to output disable
(tiN + tLAD + txz)

tpXZ1

70

(2)

75

ns

INPUT pin to enhanced output disable
(tiN + tLADe + txz)

tPXZ1e

65

(2)

70

ns

tPXZ2

75

(2)

80

ns

tPXZ2e

70

(2)

75

ns

tClR

75

(2)

80

ns

tlO
tiN
tlAD
tLADe
tOD
tzx
txz
tiC
tlCe

(1)
(1 )

(1 )
(1)

44

39
19
19
19
44

INPUT pin to enhanced comb. output
(tiN

+ tLADe + toD)

1/0 pin to comb. output
(tiO

+ tiN + tLAD + tOD)

1/0 pin to enhanced comb. output
(tiO

+ tiN + tlADe + tOD)

1/0 to output enable
(tiO

+ tiN + tLAD + tzx)

1/0 to output disable
(tiO

+ tiN + tLAD + txz)

1/0 pin to enhanced output disable
(tiO

+ tiN + tlADe + txz)

Asynchronous Clear
(tiO + tiN + tiC + tOD)
NOTES:

1. Intel does not spec internal timings of the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.

2-237

inter

ER-22

SYNCHRONOUS MODE (5C180-75 VS. EP1800-3)
INTEL
Parameter
Internal register setup time

Symbol

Min

ALTERA
Max

Symbol

Min

tsu
tlO
tiN
too
tLAD
tLADe
tiCS
tFO

14

Max

Units

OUTPUT buffer and pad delay
Logic array delay
Enhanced logic array delay
System clock delay
Feedback delay

(1 )
(1 )
(1 )
(1)
(1)
(1 )
(1)
(1 )

Max. Frequency (no fdbk)
(1/[1NPUT pin setup to CLKx))

fMAX

19.6

fMAX

18.5

MHz

Max. Count Frequency (with fdbk)
(1/tCNT)

fCNT

15.1

fCNT

13.8

MHz

INPUT pin setup to CLKx(3)
(tiN + tLAD + tsu - tiN - tiCS)

tSU1

51

(2)

54

ns

1/0 pin setup to CLKx(3)
(tiO + tiN + tLAD + tsu - tiN - tiCS)

tSU2

56

(2)

59

ns

INPUT pin setup to CLKx(4)
(tiN + tLADe + tsu - tiN - tiCS)

tSU1e

46

(2)

49

ns

1/0 pin setup to CLKx(4)
(tiO + tiN + tLADe + tsu - tiN - tiCS)

tSU2e

51

(2)

54

ns

ClOCK High to Output Valid
(tiN + tiCS + too)

tco

110 pin pad & buffer delay
INPUT pin pad & buffer delay

Register output feedback to
register input-internal path
(tFO + tLAD + tsu)

tCNT

Clock High Time
Clock Low Time

30

(2)

66

tCNT

tcH

25

tCL

25

ns
ns
ns
ns
ns
ns
ns
ns

35

ns

72

ns

tCH

27

ns

tCL

27

ns

NOTES:
1. Intel does not spec internal timings on the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.
3. For global and standard macrocells.
4. For enhanced macrocells.

2-238

5
12
19
44
39
4
14

ER-22

Inte1SC180-90 VS. Altera EP1800
COMBINATORIAL MODE (5C180·90 VS. EP1800)
INTEL
Parameter

liD pin pad & buffer delay
INPUT pin pad & buffer delay
Logic array delay
Enhanced logic array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

Symbol

Min

ALTERA
Max

(1 )
(1 )
(1 )
(1 )
(1)

(1 )
(1 )
(1 )
(1 )

Symbol

Min

Max

Units

tlO
tiN
tLAO
tLAOe
too
tzx
txz
tiC
tlCe

5
14
48
43
23
23
23
48
43

ns
ns
ns
ns
ns
ns
ns
ns
ns

INPUT pin to comb. output
(tiN + tlAO + too)

tp01

85

tp01

85

ns

INPUT pin to enhanced comb. output
(tiN + tLAOe + too)

tP01e

80

tP01e

80

ns

tp02

90

tp02

90

ns

tP02e

85

tP02e

85

ns

INPUT to output enable
(tiN + tlAO + tzx)

tPZX1

85

(2)

85

ns

INPUT pin to enhanced output enable
(tiN + tLAOe + tzx)

tPZX1e

80

(2)

80

ns

tpZX2

90

(2)

90

ns

tPZX2e

85

(2)

85

ns

tPXZ1

85

(2)

85

ns

tPXZ1e

80

(2)

80

ns

tpXZ2

90

(2)

90

ns

tPXZ2e

85

(2)

85

ns

tClR

90

(2)

90

ns

liD pin to comb. output
(tiO

+ tiN + tlAO + too)

liD pin to enhanced comb. output
(tiO

+ tiN + tlAOe + too)

liD to output enable
(tiO

+ tiN + tLAO + tzx)

110 pin to enhanced output enable
(tiO

+ tiN + tLAOe + tzx)

INPUT to output disable
(tiN + tLAO + txz)
INPUT pin to enhanced output disable
(tiN

+ tlAOe + txz)

liD to output disable
(tiO

+ tiN + tlAO + txz)

liD pin to enhanced output disable
(tiO

+ tiN + tLAOe + txz)

Asynchronous Clear
(tiO + tiN + tiC + too)
NOTES:

1. Intel does not spec internal timings of the device.
2. Altera does not spec. in 1988 handboqk, these are calculated values based on formula given.

2-239

intJ

ER-22

SYNCHRONOUS MODE (5C180-90 VS. EP1800)
INTEL
Parameter

Symbol

Min

ALTERA
Max

Internal register setup tim'e
I/O pin pad & buffer delay
INPUT pin pad & buffer delay
OUTPUT buffer and pad delay
Logic array delay
Enhanced logic array delay
System clock delay
Feedback delay

(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )

Max. Frequency (no fdbk)
(1/ [INPUT pin setup to CLKxj)

fMAX

16.1

Max. Count Frequency (with fdbk)
(1/tCNT)

fCNT

12.2

Symbol

Min

tsu
tlO
tiN
toD
tLAD
tLADe
tiCS
tFD

18

Max

Units

5
14
23
48
43
4
16

ns
ns
ns
ns
ns
ns
ns
ns

fMAX

16.1

MHz

fCNT

12.2

MHz

INPUT pin setup to CLKx(3)

+ tlAD + tsu

tSU1

62

(2)

62

ns

I/O pin setup to CLKx(3)
(tiO + tiN + tlAD + tsu - tiN - tiCS)

tSU2

67

(2)

67

ns

INPUT pin setup to CLKx(4)
(tiN + tlADe + tsu - tiN - tiCS)

tSU1e

57

(2)

57

ns

I/O pin setup to CLKx(4)
(tiO + tiN + tlADe + tsu - tiN - tiCS)

tSU2e

62

(2)

62

ns

Clock High to Output Valid
(tiN + tiCS + tOD)

tco

(tiN

- tiN - tiCS)

35

(2)

41

ns

Register output feedback to
register input-internal path
(tFD + tlAD + tsu)

tCNT

82

tCNT

82

ns

Clock High Time

tcH

30

tCH

30

ns

Clock Low Time

tCl

30

tCl

30

ns

NOTES:
1. Intel does not spec internal timings on the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.
3. For global and standard macrocells.
4. For enhanced macrocells.

, 2-240

Techniques for Modular EPLD Logic Design

Lawrence Pal ley
PLDO Product Marketing Manager
Intel Corporation
151 Blue Ravine Road
Folsom, CA 95630
iNTRODUCTION
Advances in both programmable logic
devices and the tools used to configure them
now enable new design techniques for custom
logic applications. New high capacity flexible
architectured EPLDs (erasable and electrically
programmable logic devices) allow for complete
single chip integration of one or more logic
configurations. Additionally. development
tools make use of these capabIlitIes by
providing alternatives for design Input, high
speed logic compilation and minimization,
heuristic logic fitting into EPLD devices, and
superior reporting documentation. Designers
can take advantage of these advances with a new
Modular EPLD logic design (MELD)technique, to
accelerate their product development.
ADVANCES IN EPLDs
Traditional PLDs relied on Boolean
equation entry and compilation methods for
combinatorial function implementation. The
primary applications were as SSI/MSI replacements for implementing decode "glue" in
microprocessor based systems. PLDs came in
oipolar versions with total logic content under
400 gates of equivalent logic. Tools to
develop the programmable logic implementation
of a function didn't require a high degree of
sophistication - the devices for which they
were optimizing designs had relatively little
logic and little logic flexibility.
Newer EPLDs incorporate several features
which broaden their application base. Besides
their low power CMOS technology, they incorporate individually configurable register and
I/O logic for each macrocell. Devices such as
the 5C060 incorporate 16 macrocells with
registers programmable into D, or JK configurations. Each register is also
programmably configured to be clo~ked by
synchronous or asynchronous clocks.
Additionally, outputs and feedback paths for
each pin can be combinatorial or registered.
The combination of this level of flexibility
and gate counts of some devices exceeding 1200,
EPLDs have moved programmable logic well past
simple combinatorial functions.

logic optimization for maximum device utilization, and improved reporting documentation.
Intel's programmable logic development system
provides these improvements. Input methods
include the choice of (and combination of)
schematic, netlist, state machine, or Boolean
entry. Besides Boolean equation minimlzation,the optimizer program optimally matches
I/O and register resources required by the
design with what's available in EPLD devices.
it then reports on how the logic entry was
reduced, which resources were re- quired, and
how the design was placed in a given device.
Resources still available in the devices or not
able to fit in to the device are also
documented.

Making use of both the advances in EPLD
devices and.their development tools, engineers
can now desIgn hardware (logic) in much the
same way as software is developed. This new
design technique called MELD (Modular EPLD
Logic Design) is shown in Figure 1. Design
Entry, in any of the typical engineering
formats, is entered on a development station
(in this case a personal computer). Using EPLD
development system software, the design is then
compiled for EPLD implementation. Object code
or (in the case of an EPLD) a JEDEC l's and O's
file are the result. The unique capability of
EPLDs is to test a part of a partitioned design
in silicon, erase the EPLD, test the next
design, and finally to merge the designs
together. Th i s powerful 1ogi c des i gn methodolog~ allows for the partitioning of a complex
logIc function into smaller sub-functions that
can be ~ndividually designed and debugged using
the desIgn tools and the erasability feature of
EPLDs. After the individual modules are proved
to be functional as desired, they can be combined on the same EPLD, allowing for higher
integration and its attendant benefits.

To make optimum use of the new EPLD device
technology, design tools needed to improve to
allow more freedom of design input, better
2-241

26/1

EPLD
DESIGN

(}
OTH ER
DESIGN
SECTIONS

OTHER
DESIGN
SECTIONS

rm:"01';~rrr17V--,ir1

ESIGN
REPORT
ITH
DEVICE
UTILIZATION

DESIGN
REPORT
WITH
ERRORS

V>

W

o

w

'"

Figure.1.

NOTE:

EPLD design process compared with software
des i gn process

The MELD technique would involve this design process
shown above to be lmplemented for different sub-modules
and combining of the sub-functions into the completed
high-integration EPLD design.

A MELD Example:
The two design files, BCD-Counter and
SEGEQS, are now compiled together in the LOC
(Logic Optimizing Compiler) of the Intel
Programmable Logic Development System (Figure
6) to yield the combined file; BCD-Counter, of
Figure 7.

This Modular EPLD logic design (MELD)
methodology is now illustrated with an example.
The example shown here is a design which
lmplements a BCD-counter which is encoded into
a seven-segment display.
Figure 2 shows the design of a BCD:counter
designed using state machine entry. ThlS
design was compiled (Figure 3) and individually
tested in-circuit.

When implemented in the 5C121 EPLD, the
utilization report of Figure 8 results. It
shows a pinout designated by the compiler. the
routing of inputs, the source of outputs,
unused device resources, and some figure of
merit about how the design used 5C121
resources. This data can be used to test the
device to as feedback for new design inputs.
An example of such an input would be to assign
signals to 5C121 pins so that PCB layout is
simple.

Figure 4 shows a design for implementing
the seven-segment display shown in Figure 5.
It uses ,Boolean design methods, although not
yet optimized. This design has been tested out
in several previous designs. An additional
section called "LINK EQUATIONS" is now used to
connect the BCD-counter with the seven-segment
display.
26/1

2-242

FIGURE'2

LSP
INTEL
February 7, 1986
0
0
5C121
BCD COUNTER
LB Version 3.0, Baseline 17><, 9/26/85
PART: 5C121
INPUTS: CLK,ENABLE,RESET
OUTPUTS: BCDO,BCDl,BCD2,BCD3
MACHINE: BCD_COUNTER
CLOCK: CLK
STATES: [BCD3 BCD2 BCDI BCDO]
SO
[
0
0
SI
[
0
0
S2
[
0
0
S3
[
0
0
S4
[
0
1
S5
[
0
I
S6
[
0
I
S7
[
0
1
[
S8
1
0
[
I
S9
0

0
0
I

0
1
0

I
0
0

0
I

I

I

0

I
0

0

0

1

1

%TRANS ITIONS%
SO:
IF RESET THEN SO
IF ENABLE THEN Sl
S I:
IF RESET THEN SO
IF ENABLE THEN S2

S2:
IF RESET THEN SO

IF ENABLE THEN S3
S3:
IF RESET THEN SO
IF ENABLE THEN S4
S4:
IF RESET THEN SO
IF ENABLE THEN S5

S5:
IF RESET THEN SO

IF ENABLE THEN S6
S6:
IF RESET THEN SO
IF ENABLE THEN S7
S7 :
IF RESET THEN SO
IF ENABLE THEN S8
S8 :
IF RESET THEN SO
IF ENABLE THEN S9
S9:
IF RESET THEN SO
IF ENABLE THEN SO
END$

2-243

26/1

FIGUKE "3

LSP
INTEL
February 7, 1986

o
o

5C12l
BCD COUNTER
LB Version 3.0, Baseline 17x, 9/26/85SMV Version 1.0 Baseline 1.3 85/12/13 00:12:5
PART: 5C12l
INPUTS:
CLK, ENABLE, RESET
OUTPUTS:
BCDO, BCD1, BCD2, BCD3
NETWORK:
CLK = INP(CLK)
ENABLE = INP(ENABLE)
RESET = INP(RESET)
%

I/O's for State Machine "BCD - COUNTER"

%

BCD3,
BCD2,
BCDl,
BCDO,

BCD3
BCD2
BCDl
BCDO

RORF(BCD3.d,
RORF(BCD2.d,
RORF(BCDl. d,
RORF(BCDO.d,

CLK,
CLK,
CLK,
CLK,

GND,
GND,
GND,
GND,

GND,
GND,
GND,
GND,

VCC)
VCC)
VCC)
VCC)

EQUATIONS:
%

Boolean Equations for State Machine "BCD_COUNTER"
%
%

Current State Equations for "BCD_COUNTER"
%

SO
Sl
S2
S3
S4
S5
S6
S7
S8
S9

BCD3'*BCD2'*BCD1'*BCDO';
BCD3'*BCD2'*BCDl'*BCDO;
BCD3'*BCD2'*BCD1*BCDO';
BCD3'*BCD2'*BCD1*BCDO;
BCD3'*BCD2*BCDl'*BCDO';
BCD3'*BCD2*BCD1'*BCDO;
BCD3'*BCD2*BCD1*BCDO';
BCD3'*BCD2*BCDl*BCDO;
BCD3*BCD2'*BCDl'*BCDO';
BCD3*BCD2'*BCD1'*BCDO;

%

SV Defining Equations for State Machine "BCD_COUNTER"
%

BCD3.d

S8.n
+ S9.n;

BCD2.d

S4.n
+ S5.n

+ S6.n

+ S7.n;
S2.n
+ S3.n
+ S6.n
+ S7.n;
BCDO.d
Sl.n
+ S3.n
+ S5.n
+ S7.n
+ S9.n;

BCDl. d

%

26/1

2-244

FIGURE 3 (CONTINUED)
Next state Equations for State Machine "BCD_COUNTER"
%

Sl.n

S1
+ SO

S2.n

S2
+ S1

S3.n

S3
+ S2

S4.n

S4
+ S3

S5.n

S5
+ S4

S6.n

S6
+ S5

S7.n
S8.n

S7
+ S6

S8

+ S7

S9.n

S9
+ S8

(ENABLE)'
* (RESET); ,
* ENABLE
* (ENABLE)*, (RESET)'
* (RESET)'
* ENABLE (RESET)'
* (ENABLE)* , (RESET); ,
*
** ENABLE (RESET)'
;
* (RESET)'
(ENABLE)'
* ENABLE (RESET)';
*
* (ENABLE)*, (RESET) ,
* ENABLE (RESET)';
*
* (ENABLE)*, (RESET)'
* ENABLE (RESET)';
*
* (ENABLE)*, (RESET)'
*
(RESET)'
;
** ENABLE
(ENABLE)*,
* ENABLE (RESET)';
* (RESET)'
* (ENABLE)*, (RESET) ,
* ENABLE (RESET)'
*
;
*
*

END$

2-245

26/1

FIGURE 4

LSP
INTEL
February 7, 1986

o
o

5C121
SEYEN SEGMENT DECODERS FOR BCD COUNTER
LB Version 3.0, Baseline 17K, 9/26/85
PART: 5C121
INPUTS:
OUTPUTS: SEGA,SEGB,SEGC,SEGD,SEGE,SEGF,SEGG
NETWORK:
SEGA
CONF (SEGA,YCC)
SEGB
CONF (SEGB,YCC)
SEGC
CONF (SEGC,YCC)
SEGD
CONF (SEGD,YCC)
SEGE
CONF (SEGE,YCC)
SEGF
CONF (SEGF,YCC)
SEGG
CONF (SEGG,YCC)
EQUATIONS:
SEGA
0 + 2 + 3 + 5 + 7 + 8 + 9:
SEGB

o

+ 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9:

SEGC

o

+ 1 + 3 + 4 + 5 + 6 + 7 + 8 + 9:

SEGD
SEGE
SEGF
SEGG

0
0
0
2

+
+
+
+

2
2
4
3

+
+
+
+

3
6
5
4

+
+
+
+

5 + 6 + 8;
8:
6 + 8 + 9',
5 + 6 + 8 + 9:

o

/D3*/D2*/Dl*/DO:
1
/D3*/D2*/Dl*DO:
2
/D3*/D2* Dl*/DO:
3
/D3*/D2* Dl*DO:
4
/D3* D2*/Dl*/DO;
5
/D3* D2*/Dl*DOj
6
/D3* D2* Dl*/DO;
7
/D3* D2* Dl*DO;
8
D3~/D2*/Dl*/DO;
9
D3*/D2*/Dl*DOj
%LINK EQUATIONS %
DO
Dl
D2
D3

BCDO:
BCD1:
BCD2:
BCD3:

END$

FIGURE 6
Intel Programmable Logic Software
LOC Menu
Fl Help
F2 iPLS Menu
F3 Input Format
F4 File Name
F5 Minimization
F6 Inversion Control
F7 LEF Analysis
26/1

ADF
A:BCD A:SEGEQS
Yes
No
Yes

2-246

FIGURE 7

LSP
INTEL
February 7, 1986

o
o

5C121
BCD COUNTER
LB Version 3.0, Baseline 17x, 9/26/85SMV Version 1.0 Baseline 1.3 85/12/13 OD:12:5
PART:
5C121
INPUTS:
CLK, ENABLE, RESET
OUTPUTS:
BCDD, BCDl, BCD2, BCD3, SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG
NETWORK:
CLK = INP(CLK)
ENABLE = INP(ENABLE)
RESET = INP(RESET)
BCDD, BCDO
RORF(BCDD.d, CLK,
BCDl, BCDI = RORF(BCDl.d, CLK,
BCD2, BCD2 = RORF(BCD2.d, CLK,
BCD3, BCD3 = RORF(BCD3.d, CLK,
SEGA
CONF(SEGA, VCC)
SEGB
CONF(SEGB, VCC)
SEGC
CONF(SEGC, VCC)
SEGD
CONF(SEGD, VCC)
SEGE
CONF(SEGE, VCC)
SEGF
CONF(SEGF, VCC)
SEGG
CONF(SEGG, VCC)
EQUATIONS:
SEGG
BCDI
BCD3'
BCD2'
+ BCDl'
BCD3'
BCD2
+ BCDl'
BCD3
BCD2'
+ BCDl
BCD3'
BCDD':

GND,
GND,
GND,
GND,

GND, VCC)
GND, VCC)
GND, VCC)
GND, VCC)

*
*
*
*

SEGF
+
+
+

*
*
*
*
BCD3' * BCDl' * BCDD'
BCD3' * BCD2 * BCDl'
BCD3 * BCD2'
* BCDl'
BCD3' * BCD2 *
BCDD' :

SEGE

BCD2'
+ BCD3'

BCDl' * BCDD'
** BCDl * BCDD';

SEGD

BCD2'
+ BCD3'
+ BCD3'
-+ BCD3'

* BCDl
** BCD2'
* BCDD'
** BCDl
BCD2 * BCDl' * BCDD;

SEGC

BCD2'
+ BCD3'
+ BCD3'

SEGB

BCD2'
+ BCD3'
+ BCD3'

** BCD2
* BCDD;
BCDl'
* BCDD'

SEGA

BCD3 '
+ BCD3
+ BCD3'
+ BCD3'

BCD3.d
+

BCDl'

* BCDD'

BCDl'

** BCDl;

* BCD2' * BCDD'
* BCD2' * BCD l'
* BCD2' * BCDl

* BCD2 * BCDO;
BCD3 * BCD2' * BCDl' * BCDD' * RESET'
BCD3 * BCD2' * BCDl' * ENABLE' * RESET'

+ BCD3'

*

BCD2

* BCDl * BCDO * ENABLE *
2-247

RESET';
26/1

FIGURE 7 (CONTINUED)
BCD2.d

BCD3'
+ BCD3'
+ BCD3'
+ BCD3'

BCDI. d

BCD3'
+ BCD3'
+ BCD3'

BCDO.d

BCD3'
+ BCD3'
+ BCD2'
+ BCD2'

* BCDO' * RESET'
* BCD2
* BCDl' * RESET'
* BCD2
BCD2 * ENABLE' * RESET'
* BCD2'
* BCDI * BCDO * ENABLE * RESET';
*
BCDI * BCDO' * RESET'
* Boia
* RESET'
* BCDl' **ENABLE'
BCDO * ENABLE * RESET';
*
* ENABLE * RESET'
* BCDO'
* ENABLE' * RESET'
* BCDO
* BCDO * ENABLE' * RESET'
* BCDl'
* BCDl' * BCDO' * ENABLE * RESET' ;

END$

'FIGURE 8
Logic Optimizing Compiler Utilization Report

*****

Design implemented successfully

LSP
INTEL
February 7, 1986

o
o

5C121
BCD COUNTER
LB Version 3.0, Baseline 17x, 9/26/85SMV Version 1.0 Baseline 1.3 85/12/13 00:12:5
5C121
CLK
GND
GND
GND
GND
GND
GND
SEGD
RESERVED
RESERVED
RESERVED
SEGA
RESERVED
RESERVED
SEGE
RESERVED
BCD2
RESERVED
RESERVED
GND

26[1

-

1

-: 2

-

3

-

5-

-

7

-: 4

-: 6
-: 8
-: 9

-: 10
-: 11
-: 12
-:13
-: 14
-: 15
-:16
-:17
-:18
-: 19
-:20

40:39:38:37:36:35:34:33:32:31:30:29:28:27:26:25:24:23:22:21:-

Vcc
Vcc
ENABLE
RESET
GND
GND
GND
GND
SEGG
RESERVED
RESERVED
SEGC
SEGB
RESERVED
RESERVED
SEGF
RESERVED
BeD3
BCDI
BCDO

2-248

FIGURE 8 (CONTINUED)

**INPUTS**

MCe11 #

PTenns

MCe11s

Name

Pin

Resource

CLK

1

INP

RESET

37

INP

10
11
12
19

ENABLE

38

INP

10
11
12
19

Feeds:
OE

Clear

Clock
Reg

**OUTPUTS**
Name

Pin

Resource

MCe11 #

PTerms

SEGD

8

CONF

28

4/ 4

SEGA

12

CONF

24

4/ 6

SEGE

15

CONF

21

2/ 4

BCD2

17

RORF

19

4/ 4

1
4
5
8
10
12
19
21
24
28

BCDO

21

RORF

12

4/ 8

1
4
5
8
10

MCells

Feeds:
OE

Clear

11

12
19
21
24
28
BCD1

22

RORF

11

3/ 8

1
4
5
8
10
11
12
19
21
24
28

2-249
26/1

FIGURE,S (CONTINUED)
BCD3

23

RORF

10

3/ 4

SEGF

25

CONF

8

4/ 4

SEGB

2B

OONF

5

3/ 6

SEGO

29

OONF

4

3/ 6

SEGG

32

OONF

1

4/ 4

1
4
5
B
10
11
12
19
21
24
28

**UNUSED RESOURCES**
Name

Pin

Resource

2
3
4
5
6
7
9
10
11
13
14
16
IB
19
24
26
27
30
31
33
34
35
36
NA
NA
NA
NA

-;-

MCe11

PTerms

27
26
25
23
22
20
18
17

10
8

9
7
6

12
10

6
8

10
12
8

B
8

3
2

10

B

13
14
15
16

8
8
8
B

**PART UTILIZATION**
37%
39%
18%

Pins
MacroCells
Pterms

CONCLUSIONS
The complete design
to enter, compile, and 1
ability to partition des
implement those designs
26/1

took less than an hour
nk with EPLDs. The
gns, then individually
n the logic design

entry of choice, and finally to link designs
together is a new design method only available
with advances in programmable logic and their
design tools. By taking advantage of these
capabilities, designers can bring logic
implementations to market faster and with a
high degree of integration.
2-250

AR-450
VLSI DESIGN TECHNOLOGY

Crosspoint Switch:
A PLD Approach
by Jim Donnell, Intel Corp.

E

deVIce dIctates the number of sWItches that can be deSIgned mto
rasable programmable logic devIces (EPLDs) combme
a single device.
the gate densities oflow·end gate arrays with the short
Configuration 1
development time and low cost of EPROMs. ThIS
The first cIrcuit (Figure 1) considered is a dIgItal crosspomt
mergmg of technologies produces a device with features suited
switch with eight mputs and a 3-blt word WIdth. ThIS switch
to a wide range of digital applications. In contrast to the long
transfers a 3-bit word coming from one of eight sources to a pardevelopment times (and hIgher costs) for gate arrays, EPLDs
require mimmal frontend design time. In just a few hours,
tcuar output. The number of deVIces "OR-tied" to each outEPLD designs can be developed, modified and venfied. Also.
put pin determines the number of outputs. Selectmg one of eight
data mputs from each of the three channels (AO to A7. BO to B7
core elements from one EPLD design can be incorporated inand CO to C7), the sWItch routes that data to a smgle output (QA.
to new designs as quickly as standard software subroutines from
QB and QC). Each output can be OR-tied to more than one
one program can be modified and used in other programs.
The design of a digital crosspoint
sWItch using an Intel 5CI21 EPLD illustrates these features. Digital Design
implemented a crosspoint switch in a gate
array last year (see Digital Design,
January through March, 1985). ApplicatIOns that require a data transfer from one
of several inputs to one of several outputs
frequently use a dIgital crosspoint switch.
Usmg the 5Cl21 EPLD, Intel Corp. (Santa Clara, CAl designed three different
configurations of a crosspoint switch.
Offered in a 40-pin package that provides up to 36 inputs or 24 outputs, the
5CI21 supports up to 28 macrocells (including four buried registers) and 236
product tenns (p-tenns). Logic density in
the 5CI21 is the equivalent of 1,200
usable NAND gates. Maximum power
requirements are 100 rnA active and 30
rnA standby with TTL input levels. With
CMOS input levels. a 5CI21 requires 50
rnA active and 3. rnA standby.
Two major parameters determine the
complexity and configuration of a ~hgital
crosspoint switch: the number of possible switching locatlons for each bit (inputs and outputs), and the number of bits
Figure 1: Configuration 1 uses a three-channel elght-to-one multiplexer CirCUit with latching Intransferred in one clock pulse (word
puts Each output can dnve multiple. individually selected Inputs to complete the digital crosswidth). The avaIlability of I/O pins,
pOint SWitch By connecting mputs to the EPLD outputs In an "OR-tied" configuration, with only
macrocells and p-tenns for a given EPLD
one Input enabled at any time, the multiplexer Circuit becomes a crosspomt sWitch

© Intel Corporation, 1986
Reprinted with permission from Digital Design
2-251

VLSI DESIGN TECHNOLOGY

three-state lOput to complete the switch (only one input can be
enabled at a time). Three additional control bits (DO to D2)
select one of the eight different inputs. All three channels
operate in parallel. Separate mput and output clocks allow a
high data rate and relax input set-up and hold times. Input data
for all three channels, along with the three select bits, are
latched by ILE. Data at the mputs can change state after bemg
latched and data is clocked out of the switch by CLK.
Equation 1 shows the Boolean expression for a single channel in the sum-of-products form. (See Table 1 for all equations.)
. The Boolean expression for the remaining two channels is
SImilar: the designer need only change the A m the equatIOns
toaBorC.

Timing Analysis
The internal delay paths determme the CIrCUIt'S maximum
operating frequency (fmax).ln thiS configuration there is an input delay (Tm), an array delay (Tad), a register delay (Trd) and
an output delay (Tad). The fmax is a function ofthe signals that
must settle at the input of the output register before the rismg
edge of the clock. In thiS case, signals propagate only through
the input latches and the array. Therefore, the data must be valid
at the inputs Tin + Tad Just nanoseconds before the rising edge
of the internal clock signal (CLK). However, because ofthe inherent delay of the CLK signal, thiS reference must be shifted
to the rismg edge of the external clock signal by subtractmg the
mternal clock delay (Tic). The external data set-up time (Tsu)
is shown in Equation 2. Inverting thiS time reqUIrement yields
the maximum operating frequency.
As the output flip-flops are clocked, data propagates through
the register to the output pin. With reference to the external
clock pin, data becomes valId at the outputs Tic + Trd + Tad
nanoseconds after the Tlsmg edge of the clock. Figure 2 shows
the timing reqUIrements for this circuit, including the input latch
signal.
Using a 5C121-50 (50-nsec propagation delay), data can be
sent through this switch configuration at 25 Mblts/sec. ThiS
transfer rate remains independent ofthe word width. Smce one
5CI2I EPLD in this configuration can simultaneously transfer
three bits of informatIOn, three 5C12],s are reqUIred to transfer
a byte of data during each clock cycle. This configuration of a
digital crosspomt switch uses 86 % of the.40 pins, 71 % of the
macrocells and 11 % ofthe available p-terms in the 5C121 EPLD.

Figure 3 Configuration 2 uses a slngle~blt elght-lnpuUelght-output
digital crosspoint switch DeSigners can Implement thiS for either optimal package count (see Figure 4) or for optimal speed (see Figure 5)

outputs (QO to '(Jl). SIX control bits are required for each
transfer: three to selectthe input path (DO to D2); three to select
the output path (D3 to D5). By selecting a single output path and
clocking all output registers simultaneously, deselected outputs
are automatically cleared. This is useful for designs where only
the most current data is needed. Equation 4 IS the common
equatIon to select one of eight input paths. Equations 5 to 12
complete the Boolean equations for thiS example.
The previous equations would contain eight product terms If
they were written in expanded form. However, by treating
SELECTEQ as one signal, each equation contains only one
productterm. Both options are available in the 5C121. But, there

In contrast to the long
development times for
gate arrays, EPLDs
require minimal frontend
design time.

are advantages and disadvantages to the two methods. If
SELECTEQ is implemented as one signal through a combinational feedback option, one and one-half crosspoint switches
can be implemented in one 5CI21 (Figure 4). The trade-off is
faster speed forlow chip count. By design, only 18 macrocells
in the 5CI2I can support eight product terms. On the other
hand, selecting the combinational option reduces the p-terms
but introduces an additional input mux delay.
Figure 4 shows that an input Signal must pass through four
delays before.reaching the input to the flip-flop. Again, subtracting the input clock delay to shift the reference point yields
Configuration 2
Equation 13 for the set-up time. Inverting Tsu gives the maxThe second cirCUIt (Figure 3) also selects one of eight inputs
imum operating frequency. In thiS configuration, data can be
(10 to 17), but thiS tIme data is routed to one of eight different
clocked through at 12 Mbits/sec. This layout utilizes 97 % of the
available pins, 89 % of the available
macrocells and 13 % of the product terms.
Six 5CI2ls would be required to implement a byte-wide switch With this layout.
If the combinational feedback option is
not used, there are eight output equations, each contaimng eight product
terms. ASSigning these equations to the
macrocells that support eight p-terms
shows that only a single, one-of-eight
select line digital crosspoint switch fits
Figure 2 A 40-nsec mternal set-uptime (pnortoclocklng data through the Dutputfhp-flop) marks
into one 5C12l. Thus, the design requires
Configuration 1 Data clocked Into aU eight mput latches at the rising edge of one ILE/CLK cycle
IS selected and clocked out of the output flip-flop on the next rising edge of ILEfCLK
eight 5CI21s to complete a byte-Wide

DIGITAL DESIGN. JULY 1986

2-252

VLSI DESIGN TECHNOLOGY

parallel transfer. Since the signal paths are Identical to Configuration I, the same timing analysis applies here.
This layout (Figure 5) utilizes 65 % of the pins, 39 % of the
macrocells and 30% of the p-terms. Though the utilization
numbers are lower for this example, the actual available pins
and macrocells in the 5Cl21 are higher than initially visible.
Since macrocells in the 5C12l are organized into groups of four,
when one output structure in a macrocell group is defined the
other three must be of the same structure. Many times, this
results in unused pins being labeled "RESERVED" in the utilization report.

Configuration 3
The final circuit (Figure 6) again uses eight mputs (10 to 17) and
eight outputs (QO to (JI), though thIS time the deselected outputs "remember" their previously selected state. With the
5Cl2I's register feedback option, deselected outputs can hold
the last data bit sent to that output. New data appears when the
output is selected agam.
Equations 14 to 22 express the Boolean terms necessary to
implement this hold feature In the digital crosspOint SWitch.
Note that each output is now a functton of both the present mputs
and the previous output (Qnfuk), which Implements the regIStered feedback. Data bits D3, D4 and D5 determine which data
bit will pass to the output. Agam, the number of p-terms dictates the use of combinational feedback, as m ConfiguratIOn 2.

Timing Analysis
ThiS configuration's timmg analysis IS Similar to Configuratton

2', combinational feedback analysis, With the exception of a

Figure 4: Configuration 2 features a low package count layout Note that
one and one-half SWitches fit Into each 5C121 EPLD Thlsconflguratlon
uses comblnatonal feedbacks to simplify the logiC equations, thus
eliminating the reqUirement for eight product terms per output

register feedback delay (Trl). Trf IS the time that the data IS pre·
sent at the output of the t1ip-t1op to the ttme that data IS available
to the array.
The total delay assOCiated with the regIStered feedback consists ofthe Trd, the Trf and the Tad. Data from the t1lp-t10p output reaches the mput in about 50 nsec The delay associated With
data coming from the mput pms IS the same as that of ConfiguratlOn 2 with combmattonal feedback - approximately 83 nsec
Using this as the clock penod. there IS ample time to Implement
the register feedback Without affecting the cycle time. In thIS
configuratIOn, data could be clocked through at 12 Mblts/sec.
CombmatlOnal feedback reduces the p-term reqUIrement to
two p-terms per equation. ThIS allows one and one-half crosspomt SWitches to fit into one 5C12!. The design utilizes 64 % of
the available pins, 42 % of the macrocells and 11 % of the product terms. SIX deVices would be required to implement a byteWide SWitch.
All of the configurations function differently, and no one configuration is optimum for all applications. A deSigner can
customize a deVice to meet the needs of an application. whether
those needs include higher speed or lower chip count A second
device can be qUIckly developed for a different application.
Designers are no longer restncted to a single device type that
must be adapted to an apphcatton With additIOnal logic deVices.

.JULY 1986. DIGITAL DESIGN

2-253

inter
VLSI DESIGN TECHNOLOGY

An original design can be developed in an afternoon. Additional
devices derived from an original design can be developed in a
few hours. Also, the ability to erase an EPLD and reprogram
it allows design errors to be corrected immediately. Instead of
several weeks delay with gate arrays, a designer using EPLDs
can have working silicon devices in one day.
Both the flexibility and short design times associated with
EPLDs make them a good choice for applications that benefit
Figure 6: Configuration 3 shows the use of registered feedback to allow
deselected outputs to retain the" previously selected data. The logic
for a representattve channel IS shown As with Configuration 2, thiS configuration can be optimized for package count or speed.

from custom silicon devices. Today, EPLDs offer designers the
densities and configuration flexibility of gate arrays, along with
the short development time and cost associated with EPROMs.
DC

Figure 5: ThiS circuit (Configuration 2 optimized for speed) combines
the multiplexer and demultiplexer functions for each channel in asingle
array. Since each output equation uses eight product terms, only one
sWitching channel can fit into each 5C121 package.

.JULY 1998 • DIGITAL DESIGN

2-254

inter

AR-451

Designer's Corner

A Programmable Logic Mailbox for
80C31 Microcontrollers
Karlheinz Weigl anc1 Jim Donnell, Intel Corp., Frankfurl, West Germany, and Folsom, CA

T

his article describes the implementation of a semi-intelligent interface between two 80C31 microcontrollers, using a mailbox
protocol. Applications for an interface
such as the the one described here are
often found in industrial control areas
where multiple mlcrocontrollers are
used to accomplish a given task. Due to
the architecture of the microcontroller
(i,e" no READY input; no HOLD/HLDA
interface; port-oriented 110; etc,), exchanging data and status between these
devices becomes a cumbersome task,
Given this directive, it becomes the designer's task to develop a mUlti-port
memory interface that allows for zero
wait-state operation (i.e" no READY signal required), that electrically isolates
the microcontroller buses, and that permits asynchronous access, Synchronization would result in the generatIOn of
wait states.
We realize the logic necessary to implement the desired functions in two
erasable programmable logic devices
(EPLDS), One device, the 5C03l, contains roughly the equivalent of 300 2input NAND gates, while the other EPLD,
the 5C060, can implement designs with
up to approximately 600 gates,

ADoA° /

ADt;-AD,

Pc

P,

A ..

e:

ALE
A8A,~

I\&A 15

P,

P,

~

P"StR

.... &lC31[1H

P80C31BH

7

m:iP37

Wffi:>3t

~6

flVpJ

The Mailbox Principle
And its Implementation
In a mailbox memory system, the microcontrollers exchange information as
bytes of data written to or read from a
mailbox register. Control logic permits
simultaneous access to the mailbox, thus
eliminating the need for arbitration between the microcontrollers. Implementing the data exchange in this form
achieves most of the design criteria given above,
Avoiding bus arbitratIOn together
with the short propagation delays of the

FIGURE 1, Schematic of mailbox memory system,
EPLDs provides zero wait-state operation
of the data exchange. Electncal isolation
of the address and data buses IS achieved
by using the high-impedance output capability of the 5C060, Simultaneous,
asynchronous access is achieved by separatIng the RD and WR strobes Issued by
each microcontroller.
With a mailbox memory system, there

CopYrlght© 1987 by CMP Publications, Inc, 600 Community Drive, Manhasset, NY 11030.
Reprinted With permission from VLSI Systems DeSign.

2-255

is an obvIOUS need for some type of
communicatIOn protocol to confirm the
reception of a message, or the presence
of data in the mailbox, In addItIOn, the
read and wnte logic must be defined
such that Simultaneous access to the
mailbox is permitted. In order to segment the task, the deSign will be approached In terms of two separate mod-

ules: the mailbox/memory section), and
the the control logic (protocol),
To begin the design of the membry
section, it is first helpful to identify the
lesources required for the design. The
mailbox requires a total of 16 memory
storage registers (two bytes of data), tristate output control, and two separate
clock lInes used to wnte the memory
regIsters.
The SC060 EPLD was chosen to implement the memory section. ThIs device
contains 16 programmable regIster
groups that may be configured to operate
as JK-, RS··, D., and T-type flIp-flops.
Each regIster group feeds a bl-dlrectional input/output pin, whIch may be tnstated VIa an output-enable product
term. These lIO pins may also serve as
data inputs when the register output is
tri-stated. ThIS feature forms the basis of
the read-signal logic required in the design. Write logic can be accomplished
through the two synchronous clock inputs provided in the SC060. Each synchronous clock dnves a set of eight
registers In the device. The operatIOn of
the memory section of the maIlbox
memory may now be solidified.
As shown in Figure I, the two microcontrollers are separated into controller
A and controller B. Register group A
(signals lOAD to lOA 7) serves as an input
buffer to microcontroller A. This buffer
receives Information from mlcrocontroller B's data bus. The write control for
register group A comes from microcontroller B.
Again, referrIng to Figure I, it can be
seen that register group B serves as an
output buffer to microcontroller B. ThIS
buffer gets information from mlcrocontroller A and is therefore write-controlled by microcontroller A.

W6 _ _ _ _ _--.

10AO

,lOBO

10AI

IOS1

10112

1082

IOA3

1063

10M

1084

10AS

100&

IOA6

IOB6

IOA7

1007

+ __ WA

L....._ _

RDA

RDS

CSA

GSS

FIGURE 2. Schematic of register interface.

WRB 1
CSA· 2

Data Transfer
In order to read 'data from the mailbox, the microcontroller must initiate a
read cycle addreSSIng the mailbox. The
read signal (RDA for microcontroller A,
ROB for mlcrocontroller B) enables the
tri-state outputs of the SC060, reveahng
the appropriate data. Spurious read cycles are avoided by logically combining
the read signal with a chip select signal
(CSA or CSB) within the chip. The example shown utilizes address bit A15 as the

Group A
(mlcrocontrolier Ai

l.

:g~~:

24 -vCC
23 -ROB

"

3

22

4
5
6
7
II,

21 -lOBI
·IOBO
20 -IOB2
19 -IOB3
18 -IOB4
17 ·IOB5

IOA2IOA310A4·
IOA510Ae· 9
IOA7· 10

5C060

I

Group B
, (microcontroller B)

16 ·IOB6
15 ·IOB7
14 ·CSB
13 ·WRA.

RDA· 11
GND- 12
"

FIGURE 3. Pin-out for register interface.

VLSI SYSTEMS DESIGN

2-256

January 1987

Designer's Comer

WRA
GSA
RST

=~==:gr-~-----1~------------------- WA

-r..--<......./

H---+';:'ROB
GSB

--\4-..{

'SEA

"

- T T T '........- /

,NTB

WRS

r----.----+~+_---~----_+--- WH
r'"'U_/

INTA

IBFI - - - - - - - - - - - - - - - '
OBEI : : : : : : : : : : : : : : : : : : : : : : : : : : : : :___________
OE

J

FIGURJ:: 4. Schematic of control logic.
chip-select signal. thereby reserving the
upper 32K bytes of memory space for the
mailbox.

Protocol Control Logic
Having defined the memory section of
the mailbox, we next must orchestrate
the control logic. To guarantee reliable
data transfers, both microcontrollers
need feedback about the status of their
respective input and output buffers.
In order to achieve a maximum data
transfer rate, an interrupt-driven protocol may be used. The signals necessary
to achieve the transfer protocol are:
OBFA (A'S output buffer full)
OBFB (B's output buffer full)
IBEA (A'S input buffer empty)
IBEB (B's input buffer empty)
INTA (A'S data ready interrupt)
INTB (B's data ready interrupt)
Further definitions of the control signals
can be made as follows.
Output Buffer Full. This flag is set
whenever a controller writes to the mailbox. The flag remains valid until the
second controller has read the data. The

flag is reset when the recipient controller
reads the data from the mailbox.
Input Buffer Empty. This flag mdicates that there IS no message in the
mailbox and that the mailbox can be
written without corrupting the data. This
flag is set whenever a controller reads
data from the mailbox. The flag remams
set until data is placed in the mailbox.
Interrupt. The SC031 IS programmed
to supply interrupts to both microcontrollers involved, when either one of two
events occurs. First, the recipient micro-

controller receives an interrupt when ItS
OBF flag goes active. This Signals the
recipient that data is available in the
mailbox. Secondly, the originator microcontroller receives an interrupt when
data placed by that microcontroller in
the mailbox has' been received by the
recipient microcontroller. ThiS IOterrupt
indicates that data has been received and
that it is safe to write data to the
mailbox.
The signals described above form the
basis for clean and efficient data transfer
between the two microcontrollers. The
transfer time is limited only to the over-

head of the interrupt service routlOes.
The SC060 can accept data at clock rates
. in excess of 20 MHz.

Programming the EPLDs
Figures 2 and 3 show the schematiCs
and pin-out for the memory sectIOn, and
Figure 4 IS a schematic of the protocol
sections in the mailbox memory Usmg
Intel's Programmable Logic Development System, these schematics can be
transformed With ease mto the logiC
equations that represent the deSired
function. The development system accepts a variety of entry methods, mclud109 schematiC, netlist. state machme.
and text file entry.
Once the deSign has been entered, the
file IS submitted to the LogiC Optlmizmg
Compiler (LOC), which performs an optIOnal Boolean mlOimlzatlon, mcludmg
De Morgan's inverSIOn, and logically
fits the deSign mto the target EPLD
The development system generates
three output files. The Logic EquatIOn
File (LEF) con tams the result of the mlmmlzatlon process, the UtilIzation Report
File (RPT) contains the final device pinout, mformation about the mternal logic
routmg, and a percent utilizatIOn for
pms, macrocells, and product terms. Finally, the JEDEC file (JED) contains the
deVice programming mformation reqUired to program the EPLDs. These files
are available from the authors.
Programming of the EPLDs is accomplished through Intel's LogiC ProgrammlOg Software (LPS) and the IUP,PC programmlOg hardware. DeSigns also may
be logically Simulated through the use of
Intel's FSIM software.

Summary
Applications such as IOdustnal automation often reqUire commumcation between multiple microcontrollers. Unfortunately this communicatIOn is
hampered 'by the port orientation and
lack of bus control Signals WlthlO the
mlcrocontroller environment. One solution-as presented here-IS the mailbox
memory. The mailbox memory serves as
an effective method for transferrmg data
between microcontrollers, while the
fleXibility of the EPLDs serves as an
effective way to implement the mailbox
D
itself.

VLSI SYSTEMS DESIGN

2.. 257

January 1987

inter

AR-454
~I------D-ES-IG-N-A-P-P-U-CA-J-IO-NS------~I
aECTRONIC DESIGN EXCLUSIVE

Regain lost 1/0 ports
with erasable PLDs
Daniel E. Smith and Thomas B. Bowns

ntel corp.. 1900 Praiie City Rd .• Folsom. CA 95630; (916) 351·2747.

As a means for reconstructing or regaining microcontroller I/O ports lost to memory expansion.
erasable programmable logic devices, or EPLDs,
contain all the necessary functions. In fact, EPLDs
perform more functions than most programmable
logic arrays, and offer the additional benefits of
EPROM-like erasability, the low power consumption of CMOS technology, and gate densities near
those of low-end gate arrays.
Lost I/O ports can be externally reconstructed
with standard SSI
packages. EPLDs, howeVer, supply an alternaErasable PLDs cut the
tive that reduces the exspace and power
ternal approach's
usually needed to
impact on power and
reconstruct 110 ports.
space consumption.
They can even build
The computing
new ports, adding to
power of one-chip microcontrollers plays a
a chip's capabilities.
role in many applications. But the growing
complexity of these devices, as designers shift from
8- to 16-bit controllers, has strained their I/O capacity.
A typical 8-bit microcontroller in a 4O-pin package contains a 4- to 8-kbyte program memory and
32 I/O pins, usually grouped into 8-bit ports. The
16-bit devices contain 8-kbyte memories and up to
40 I/O pins in packages that range from 48 to 68
pins; The possible number of ports falls short for
some complex tasks in switching circuits, robotics,
, and automotive systems.
The I/O shortage is aggravated when the chip's
internal program memory is too small for a given
task. While tacking on external memory is easy
enough, the addition consumes I/O pins.
Although some details vary, the basic techniques
for reconstructing these lost I/O ports with EPLDs
are the same for most microcontrollers. An example
describes a 5CI21 EPLD and an 8096 16-bit microcontroller, noting details specific to the micro-

controller.
These techniques not only reconstruct ports on
any available microcontroller, but they also are
suited to adding new ports. For the 8096, the designer can add two new ports, 5 and 6, by changing
to I FFC-I FFF the hexadecimal address range in
which the external memory is deselected. The new
ports create a system with 561/0 signals. The
tradeoffs of this addition are the board space
needed for two more EPLDs and two more bytes of
reserved memory space at I FFC and I FFD.
The first consideration in reconstructing a port is
the microcontroller's fixed-memory and I/O address map. In the 8096, memory-address ranges 0
to FF and 2000-3FFF contain on-chip registers, interrupt vectors, factory test code, and program
memory. Expansion memory can go into the 100 to
I FFD range, a capacity of 8k bytes minus the first
256 and the last 2 bytes, and into the 4000 to FFFF
range, another 8 kbytes.
The miCrocontroller has five 8-bit ports, three of
which (0 to 2) are dedicated to I/O functions. Ports
3 and 4, however, are memory-mapped to IFFE
and IFFF, respectively. These two ports reside
right above the lower section of expansion memory
space. (Other microcontrollers have the same functions, but their address ranges may vary.)
External memory, therefore, connects to the pins
reserved for ports 3 and 4, eliminating them as general I/O ports. Reclamation of these ports calls for
external latches and decode logic that disables the
external memory and enables the latches at I FFE
and I FFF. This logic decodes signals Ao and Byte
High Enable, BHE, to select ports 3 and 4. The
ports are selected either separately for 8-bit data
transfers or together for Hi-bit transfers.
The microcontroller multiplexes address and
data on signal lines ADo to AD,s. As a result, Address Latch Enable, ALE, must latch the address as
each bus cycle starts and keep it there for the cycle
duration. Then the lines can transfer data throughout the cycle. Because BHE has the same timing as

"Repnnted with permiSSion from ElectroniC DeSign (Vol. 35, No 7) March 19, 1987. Copynght 1987 Hayden Publishing Co., Inc.,
a subSidiary of VNU:'
2-258

DESIGN APPUCAnONS • Erasable PLOs restore ports

the address, ALE must also latch BHE.
Reconstruction of both ports without EPLDs requires
14 SSI packages if the high-current sink capability of
open-collector drivers is needed. If not, nine packages
will do.
Besides the address-decoding logic, the input ports
need octal latches. The outputs contain octal latches, but
inverting buffers are a!so needed. If the output does include open-collector drivers, the designer must add another set of inverting buffers to compensate for the
drivers' inversion of the signal. In addition, a discrete flipflop latches BHE, and discrete gates decode the port selection and RD and WR signals.
On the other hand, reconstructing ports with EPLDs
requires no logic outside of the EPLDs themselves (Fig.
I). Each device decodes its respective memory-mapped
address, and one device disables the external memory at
both lFFEand IFFF.
The EPLDs can sink 4 rnA, which puts them in the
same range as an SSI version without open-collector
drivers. The designer can add open-collector drivers if a
higher-current sink is needed.
The design process leading to port reconstruction be-

gins with defining the functions required of the EPLD
and then creating a design file that can be translated into
a Jedec file. Next, the designer programs the EPLD and
tests the final circuit. Software can automate much of this
procedure.
The first step is to list the functions the EPLD must
perform. Then the designer identifies which EPLD feature best satisfies that need, because as with SSI logic, the
device can accomplish its task in different ways.
In general, a device reconstructing a port must latch
and decode address information from a multiplexed bus.
The chip then produces an internal port-selection signal
and an external memory-selection signal; the latter in address range I FFE-I FFF. Moreover, the device acts' as a
bidirectional data path and decodes the RD and WR
signals, routing the data with the port-selection signal
(Fig. 2).
Drawing a schematic diagram of the EPLD helps isolate the circuit into functional blocks. In the example,
combinatorial logic and three latches do the decoding at
port 3.
Address lines AD, throu.gh AD" pass through an
AND gate and are latched as LAD A • Address lines A12

+SV<>-tI
ADo-AD"

iii

0"
0.

. . 0.-0.,

.'

~.'

27C64-15
£I>Rt1M

latch

0.-0,

*. .*
OS

"

.

.' ..!+'5V
0,-0"
74HCT373

.. Jill 0.-0,
..'

:. * . . ¥"

'"

latch

OlE

..

',,:,':

CE

Of

"

O£ CE
AQ,,-AD,

LE

.'.

.

A7 -A'2

LE

0.

~L.

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~ A.,-A.,

14HCT373

21C64-15

1-

.*

'

AD SHE

Vee

..J:r

PaM

v""

;~
II,..

EPIIOM
AO,-A,.

Port 4

MCS
ALE WR

-P4, P47

5C121
Ao,,-AO, EPLD

+yv

...

0.-0,

I!IIII

;

ALE WR

AD

~h

l1li Ao"-AD,,
5C121
EPLD

~.
AD.-Ao,

P3,,-P3,

Port 3

~.

Il-

1. Two erasable programmable logic devices contain all the logic required to reconstruct ports 3 and 4 of
an 8096 mlcrocontroller. The two latches and two EPROMs comprise the external memory.

Electronic Design' March 19, 1987

2-259

and inverted signals AD 13
through AD15 pass through an
AND gate and are latched as
LAD B. These two latched signals pass through another
AND gate to create the Memory Disable Signal, MDS,
which deactivates the
EPROMs. Combined with
LA Do (address signal ADo
inverted and latched), LADA
and LADB generate the portselection signal.
PARALLEL FORMAT

SAVE~

AD,

TIME

The EPLD decodes and
latches signals AD, through
AD" and ADI2 through AD,s
in parallel to minimize the time
between address setup and
ALE going low. An inverted
ALE clocks the latches, which
also store decoded addresses
while the microcontroller transfers data over the bus.
Two combinatorial-output,
internal feedback (COIF)
primitives create a doublefeedback loop with all output
enables to the microcontroller
bus controlled by OE" which is
active during read operations.
Output enables on the I/O side
of the EPLD are controlled by
OE 2 , which is active during
write operations. Thus data is
valid at the inputs or outputs
only while the appropriate command, RD or WR, is active.
If the application calls for
latched outputs, the designer
can create them from logic on
the EPLD. One configuration is
a D-type latch activated by the.
trailing edge of WR (Fig. 3). In
this circuit, the outputs are always enabled, except during
reads, when they are placed in a
high-impedance state. The Re-,
set signal clears the outputs to a
logic 0 during initialization.
The fourth port's schematic
varies little from that of the
third. Because port 4 handles
data transfers on the micro-

AD,

. AOtn
AD~1

AD,. 0--------,
A~13

AD ••

AO..o-----;
~

0--,----'----'

Al5o--------'
WRo-~------------'

aHE~

2. The schematic for fhe port 3 EPLD contains a bidireCtional path that Includes parallel address decoding that speec:is circuit operation. In the port 3
device. Ao Is inverted and latched. then used to qualify reads and writes; the
port 4 EPLD relies on BHE for qualification.

Electronic Design· March 19, 1987

2-260

DESIGN APPLICAnONS • Erasable PlDs restore ports

controller's high byte, the data path connects to ADs
through AD,s. The BHE signal replaces ADD and becomes LAD, which combines with LADA and LADs to
select the correct port.
A microcontroller with a different address map or bus
interface may require some variations in address decode
logic. The basic techniques for regaining I/O ports with
EPLDs, however, remain the same.
DESIGN FILE CREATED

The next step in the port-reconstruction process is to
create from the schematic diagram a design file that can
be automatically converted to a Jedec file by Intel's Programmable Logic Software II (iPLSII) program. Four
types of inputs are acceptable: a net list file, Boolean
equations, state variables, and files from any of several
schematic-entry packages that run on personal comput-

ers. The designer can write a net list file with a wordprocessing program in a nondocument mode, but an easier way is to work with iPLS II's Logic Builder.
The Logic Builder prompts the user for the information
it needs. After establishing the file with some background
information, the program asks for lists of all the input and
output pin names (the user can assign a name to a specific
pin number). Next come the internal assignments and
connections, and finally, the logic equatIOns needed.
The designer must list all the COIFs that form the bidirectional data path. For example, the entries that create
the data line between ADD and P3 0 (see Fig. 2 again) are
as follows:
ADD, ADD = COIF (P3 o, OE,)
P3 o, P3 0 = COIF (ADo, OE 2 )
The iPLS II program contains a logic-optimizing compiler that translates the schematic's net list, or other suitable input, into a Jedec programming file. The compiler,
which is selected from the program's main menu, optimizes the logiC equations and assigns I/O pins and other
EPLD resources.
£RROR MESSAGES POINT OUT PROBLEM

3. If a designer needs latched outputs, they can be
built without additional logic. This D-type flip-flop is
made of logic elements contained in the EPLO.

ALE

The program's outputs are the programming file and a
device report file that shows the pinout of the programmed device and describes the use of the device's resources. If the compiler cannot translate the file, error
messages indicate the design-file entry that caused the
problem.
Programming the EPLD is very similar to programming EPROMs. The designer connects an EPLD programming module to the workstation, inserts an unprogrammed device into the socket, and calls up the

ClocI<

t---Tm---l

=

T..
T!n= 12 os

=

7ns

T.- 5ns

T.,,-48ns

T",= 5ns

T. -- 11 ns

Too = 11 ns

4. A block diogram of an ELPO's intemal delays shows how users can determine the maximum delay for
each signal path and, as a result, the port's maximum operating frequency.

Electronic Design· March 19. 1987

2-261

DESIGN APPUCATIONS • Erasable PLDs restore ports

programming menu. The menu asks for the device's type
and the Jedec file name, and the system then programs
and verifies the chip.
Considering how straightforward the port-reconstruction functions are, the best test of the programmed
EPLD is to plug it into a circuit and see if it works. An
EPROM-based microcontroller with some simple read
and write routines to exercize the device works well.. The
designer can also use an in-circuit emulator for the microcontroller, if one is available.
Any bugs can be fixed quickly. To correct a bug the
user erases the EPLD file and changes the design file,
which then can be recompiled and the device reprogrammed.
A timing analysis confirms the EPLD's compatibility
with different microcontroller clock speeds. The analysis
amounts to adding the internal delays for paths through
the EPLD and comparing these path delays to the microcontroller's timing requirements.
The three paths of interest are Address Setup to ALE,
which must take no longer than 116 ns for an 8096 operating at 6 MHz; and no longer than 50 ns at 10 MHz. Other
maximum values are: Data Valid From RD, 358 ns and
230 ns; and Data Valid Before Write, 272 ns and 130 ns.
A block diagram of the specific device with each internal delay is needed for the timing analysis. For the example circuit, the Address Setup to ALE delay for the port 3
EPLD is 49 ns (Fig. 4). This value, achieved by decoding
and latching AD) to AD)) in parallel with ADI2 to AD)5,
just meets the maximum delay at 10 MHz.
The delay for Data Valid From RD is the sum of delays
in the enable path and the data path, or 136 ns. The delay
path for the ,write operations is shorter: It is that for the
enable path added to 41 ns for the data path (after eliminating a 30-ns overlap in enable and data timing), or
106 ns. Both are well within limits. 0
'

Daniel E. Smith, a senior technical writer at Intel, has
also worked in microcomputer-systems testing and
written manuals for microprocessors, development
software, and bubble memories. He has a BA in history
from San Jose University and an MA in biblical studies
from the Graduate Theological UnionfJesuit School of
Theology in Berkeley, Calif.
Thomas B. Bowns is an application engineer for Intel's EPLD operation. He also has worked as a technician on the company's EPROM line. Bowns studied
digital and microwave electronics at American River
College in Carmichael, Calif

Electronic Design· March 19, 1987

2-262

Advanced Architecture

EPLDs

3

5AC312
1-MICRON CHMOS

ERASABLE PROGRAMMABLE
LOGIC DEVICE
Performance LSI Semi-Custom
• High
Logic Alternative for Low-End Gate

Feedback on All Macrocells for
• Dual
Buried Registers with Bidirectional 1/0
2 Product Terms on All Macrocell
• Control
Signals
CHMOS III-E EPRO!\t1 Technology
• based; UV-Erasable
UV Erasable Array for 100% Generic
• Testability
Security Bit Allows
• Programmable
100% Protection of Proprietary Designs
Programmable Low-Power Option for
• Standby
Operation; 100 JLA Typical
Standby Current
in 24-Pin 0.3" DIP and 28-Pin
• Available
PLCC Packages

Arrays, TTL, and 74HC- or 74HCT SSI
and MSI Logic
Speed tpd (max) 25 ns, 50 MHz
• High
Performance Pipelined, 33 MHz with
Feedback
12 Macrocells with Programmable 1/0
• Architecture;
Up To 22 Inputs (10
Dedicated, 12 IIO) or 12 Outputs

•

8 Programmable Inputs Individually
Configurable as Latches, Registers or
Flow-Through

Product Term
• Software-Supported
Allocation between Adjacent
Macrocells

•

(See Packaging Spec, Order Number # 231369)

Programmable Output Registers
Configurable as D, T, JK, or SR Types

- ;;::

~

Q:-:~

CLK/INP1
1/0.11

~~d

Vee

~

>

'"-

en

~~~

1/0.12

LlNP1

1/0.9

LlNP2

1/0.10

LlNP2

1/0.10

LlNP3

1/0.7

LlNP3

1/0.7

LlNP4

1/0.8

LlNP4

1/0.8

LlNPS

1/0.6

LlNPS

1/0.6

LlNP6

1/0.5

LlNP6

1/0.5

LlNP7

1/0.4

LlNP7

1/0.4

N.C.

LlNP8

1/0.3

1/0.1
GND

N.C.

co -

1/0.2

a..

d

c

z

~':::::-.C,!)

ILE/ICLK/INP2

...J

CI

Z

'" '" '"
'"
!.2
D..

••

~~~~
...J

~

290156-1

,:

290156-2

Figure 1. Pin Configurations

3-1

November 1988
Order Number: 290156-002

inter

5AC312

a highly flexible macrocell and I/O structure. The
5AC312 has been designed to effectively implement
both combinationa:l-register and register-combinational-register forms of logic to easily accommodate
state machine designs.

INTRODUCTION
The Intel 5AC312 CHMOS EPlD (Erasable Programmable logic Device) represents an innovative
approach to overcoming the primary limitations of
standard PlDs. Due to a proprietary I/O architecture
and macrocell str~cture, the 5AC312 is capable of
implementing high performance logic functions more
effectively than previously possible. It can be used
as an alternative to low-end gate arrays, multiple
programmable logic devices or lS-, HC- or HCT SSI
and MSI logic devices. Input and macrocell features
for the 5AC312 are a superset of features offered by
other PlD-type products.

Figure 2 shows a global view of the 5AC312 architecture. The 5AC312 contains a total of 121/0 macrocells, 8 user-programmable input structures, .and 2
additional inputs that can be programmed to serve
as either combinatorial inputs or clock inputs. Each
of the eight inputs can be individually configured as
a latch, register, or flow-through input. Input latches/
registers can be synchronously or asynchronously
clocked.

The 5AC312 uses advanced CHMOS EPROM cells
as logic control elements instead of poly-silioon fuses. This technology allows the 5AC312 to operate at
levels necessary in high performance systems while
significantly reducing the power consumption. Its
programmable stand-by function reduces power
oonsumption to almost "zero" in applications where
a slight speed loss is traded for power savings.

Each macrocell is further sub-divided into 16 Product Terms with 8 Product Terms dedicated to the
control signals OE, PRESET, ASYNCH. ClK and
CLEAR, and 8 Product Terms available for the general data array (see Figure 3).
The basic macrocell architecture of the 5AC312 includes a user-programmable AND array and a userconfigurable OR array. The inputs to the programmable AND array originate from the true and complement signals from the programmable input structure, the dedicated inputs, and the 24 feedback
paths from the 12 I/O macrocells.

ARCHITECTURE DESCRIPTION
The architecture of the 5AC312 is based on the familiar "Sum-Of-Products" programmable AND, fixed
OR structure, though the 5AC312 macrocell contains a number of significant functional enhancements. This device can implement both combinational and sequential logic functions through

Programmable Input Structure
Figure 4 shows a block diagram of the 5AC312 input
architecture. This device contains 8 user-pro·gram-

3-2

inter

5AC312

RING 1
r------

I
I

GLOBAL
CLOCK

CLK/INPI

I

I
I
I

r------

LOGIC

A~RAY

LINPI

1/0.1

1/0.2

I
I
I
IL______
I
I
I
I

1/0.3

-,
I
I

,------

LINP2

I/O ••

I
I
I
I
I

L ______

LlNP3

I
I
I
I
I
I

1/0.5

LINP.

._-----

1/0.6

LINP5

,,------

1/0.7

r------

1/0.8

I
I
I
I
I
I

LlNP6

I
I
I
I
IL ______

LlNP7

I
I
I

1/0.9

-,
I
I

,------

LINP8

1/0.10

I
I
I
I
L
I ______

ILE/ICLK/INP2

I
I
I
I
I
I

._----RING 2

1/0.11

1/0.12

290156-3

Figure 2. 5AC312 Architecture

3-3

l
TO NEXT
IotACROCELL

LOGIC ARRAY

tT

FROIot NEXT
IotACROCELL
OUTPUT

~

I

I

I

I

I

I

I

PRESET

I

."

C·

...CD

C

~
U1

l>
0

...

II II II II

LOWER HALF

I

~

OUTPUT
IotUX

I

Co)

N

m
c.J

./..

~'I

W'''r;,J

~
DI
C"I

r-:VERT

cRL./j

~

D/T
IotACROCELL
REGISTER

o

....
Co)

I\)

...0

C"I

~

.....en

.....
C
C"I
C
CD

CLEAR

T~A~:~~~~LS

•

1FR~~C~~~~LUS

"@
290156-4

2&
Iiiiil

If'"

~
~

~

2:ID
~

inter

5AC312

INP
PIN

CI----..... IN

LOGIC

OUT~------------~

ARRAY

P-TERIA

ILEjlCLK
PIN

0-----------------.....1
290156-5

NOTE:
Flow-through input selected by connecting ILE P-Term to Vee.

Figure 4. 5AC312 Input Structure
to derive an input clock signal for the input structure.
Because the clock signal for each input structure
can be individually selected, a mix between synchronously and asynchronously clocked input structures
is also possible.

mabie input structures that can be individually configured to work in one of five modes:
-

Input register (D-register), synchronous operation
Input register (D-register), asynchronous operation
Input latch (D-Iatch), synchronous operation
Input latch (D-Iatch), asynchronous operation
Flow-through input

Table 1 shows the input latch/register function table
with respect to the synchronous ILE/ICLK input.
Table 1. 5AC312 Input Latch/Register Functions

The configuration is accomplished through the programming of EPROM architecture control bits by
the logic compiler and programmer software. If synchronous operation is chosen, the ILE/ICLK/INP
becomes an ILE/ICLK (Input Latch Enable) input
global to all input latch/register structures. For asynchronous operation, ILE/ICLK/INP can be used as a
normal input (flow-through input) to the device while
a separate Product Term in the control array is used

H

3-5

Input Type

ILE/ICLK

0

Q

Latch
Latch
Latch
D-FF
D-FF
Flow-Through
Flow-Through

H
H
L

H
L
X
H
L
H
L

H
L
an
H
L
H
L

=

HIGH Level

J,
J,
X
X
L

=

LOW Level

X

=

Don't Care

intJ

5AC312

Macrocell Array

Example:

Each of 12 macrocells in the 5AC312 contains 8
p-terms (Product Terms) to support logic functions.
These 8 p-terms are subdivided into 2 groups each
containing 4 p-terms. This grouping of p-terms supports the proprietary p-term allocation scheme.

The logic function in macrocell 4 requires 16
p-terms. In this case, the iPlS II software allocates 4
p-terms from the previous macrocell in Ring 1 (macrocell 3) and 4 p-terms from the next macrocell in
Ring 1 (macrocell 5) to accumulate a total of 16
p-terms (8 + 4 + 4). This implementation leaves
macrocells 3 and 5 with a remainder of 4 p-terms
each. These remaining p-terms in macrocells 3 and
5 can also be allocated away to or can be supplemented with p-terms from their respective previous/
next macrocells in Ring 1.

Each macrocell can be configured as a 0, T, RS, or
JK register. The 8 p-terms for control functions are
organized so that 2 p-terms support each of the four
control signals. Control signals in the 5AC312 are:
Output Enable (OE), asynchronous I/O register preset (PRESET), asynchronous clock for I/O registers
(ASYNCH. ClK), and asynchronous I/O register reset (CLEAR).

Applying this scheme to the 5AC312 it becomes
clear that any macrocell inside the device can support logic functions requiring between 0 and 16
Product Terms. Product Terms allocated away from
a macrocell do not affect that macrocell's output
structure. If all Product Terms are allocated "away"
from a macrocell, the input to that macrocell's I/O
control block is tied to GND. This polarity can be
changed by programming the invert select EPROM
bit. The I/O register as well as all secondary controls
to this I/O control block are still available and can be
used if needed.

ClK is a global clock signal that can be used to
synchronously clock any or all macrocell registers. It
can be used as an input to the logic array at the
same time as a macrocell clock. When ClK is not
used as a synchronous clock, it functions only as a
dedicated input to the logic array.

Combinatorial Configuration
The macrocell register can be bypassed to implement combinatorial logic functions. When configured
to provide combinatorial logic, only the OE control
signal is used.

The Product Term allocation scheme described
above is automatically supported by iPlDS II V2.0
and is transparent to the user. Users can still use
explicit pin assignments, but should assign pins in a
way that does not conflict with p-term allocation.

Invert Select Bit

Table 2. Product Term Allocation Rings
Ring 1
Ring 2
Current Next Previous Current Next Previous
Macro- Macro- Mlicro- Macro- Macro- Macrocell
cell
cell
cell
cell
cell
12
1
2
6
7
8
2
3
1
8
9
7
4
2
9
10
8
3
11
4
5
3
10
9
5
6
4
11
12
10
6
1
5
12
7
11

An invert select EPROM bit is used to invert the
product term input into each macrocell register, including double inputs on JK and SR registers. This
invert option allows the highest possible logic utilization by use of DeMorgan's logic inversion.

Product Term Allocation
Product Term allocation is defined as taking logic
resources (p-terms) away from macrocells where
they are not used to support demand for more than
8 Product Terms in other areas of the chip. In the
5AC312, this allocation can occur in increments of 4
p-terms between adjacent macrocells.
The 12 macrocells available in the 5AC312 are
grouped into two "rings" with 6 macrocells per ring.
Product Terms can be allocated in a "shift register"
mode inside a ring; allocation of Product Terms between the rings is not supported. The two rings are
shown in Figure 2 and listed in Table 2.

3-6

intJ

5AC312

LOGIC ARRAY
LOWER HALF
P-TERMS 1-4
MACROCELL

*3

P-TERMS ALLOCATED TO
NACROCELL #4
(NEXT MACROCELL IN RING)

UPPER HALF
P-TERMS 5-8

MACROCELL

#'

UPPER HALF
P-TERMS 5-8

P-TERMS ALLOCATED TO
MACROCELL #'
(PREVIOUS MACROCELL IN RING)

MACROCELL

i5

290156-6

Figure 5. Product Term Allocation (8 + 4 + 4)

3-7

5AC312

savings. When the Turbo Bit is programmed
(TURBO = ON), the device is optimized for maximum speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

Macrocelll/O Control Block
Each macrocell in the 5AC312 has the ability to implement 0, T, SR, and JK registered outputs as well
as combinatorial outputs. The asynchronous set and
reset inputs to each macrocell register allows implementation of true SR Flip-Flops. Registered outputs
may be clocked from the synchronous ClK/INP1
pin or asynchronously clocked t;>y the 2 Product
Terms available for ASYNCH. ClK. The 5AC312
also features separate input and feedback paths
(dual feedback) on all macrocell 1/0 control blocks.
This enables the designer to utilize input pins when
the associated macrocells have been assigned a no
output with buried feedback attribute. Multiplexed
liD is accomplished by controlling the output buffer
associated with each macrocell using the 2 Product
Terms set aside for implementing an OE function.

Figure 6 shows the device entering standby mode
approximately 100 n~ after the last input transition.
When the next input transition is detected, the device returns to active mode: Wakeup time adds an
additional 20 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.
After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

Power-On Characteristics
The Macrocell registers of the 5AC312 will experience a reset to their inactive state (logic low) upon
Vee power-up. Using the PRESET function available
to each macrocell, any particular register preset can
be achieved after power-up. 5AC312 inputs and outputs begin responding within 10 ,...s (6 ,...s typical)
after Vee power-up or after a power-Ioss/power-up
sequence. Input registers are not reset on power-up
and are indetermh'late. Input latches reflect the state
of the input pins on power-up.

inteligent Programmlng™ Algorithm
The 5AC312 supports the inteligent Programming algorithm which rapidly programs Intel H-EPlDs,
EPROMs and Microcontrollers while maintaining a
high degree of reliability. It is particularly suited for
production programming environments. This method
,greatly decreases the overall programming time
while programming reliability is ensured as the incremental program margin of each bit has been verified
in the programming process. (Programming information for the 5AC312 is available from Intel by request.)

Automatic Standby Mode
The 5AC312 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power

t

INPUT
FIRST - - -...

LAST
INPUT

---------~
,------------~

OUTPUT

CURRENT
OmA

VALID OUTPUT

VALID OUTPUT

ACTIVE MODE
Icc

ACTIVE MODE

Icc

------------------~--~==~====~~------~~----290156-19
Figure 6. 5AC312 Standby and Active Mode Transitions

3-8

inter

5AC312

ERASED STATE CONFIGURATION

LATCH-UP IMMUNITY

After erasure and prior to programming, all macrocells are configured as combinatorial, inverted outputs with output buffers three-stated. Inputs are configured as synchronous registers.

All of the input, 110, and clock pins of the device
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5AC312 is designed with Intel's proprietary 1-micron CHMOS
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -0.5V to Vee + 0.5V. The
programming pin is designed to resist latch-up to the
13.5 maximum device limit.

ERASURE CHARACTERISTICS
Erasure time for the 5AC312 is 1 hour at
.12,000 p.W/cm 2 with a 2537A UV lamp.

DESIGN RECOMMENDATIONS
Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
fluore!,cent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
room level fluorescent lighting could erase the typical 5AC312 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device window to prevent unintentional erasure.

For proper operation, it is recommended that all input and output pins be constrained to the voltage
range (GND < (VIN or VOUT) < Vee. All unused
inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capacitor of at
least Q.2 p.F must be connected directly between
each Vee and GND pin.
As with all CMOS devices, ESD handling procedures
should be used with the 5AC312 to prevent damage
to the device during programming, assembly, and
test.

The recommended erasure procedure for the
5~C312 is exposure to shqrtwave ultraviolet light
With a wavelength of 2537 A. The integrated dose
(Le., UV intensity X exposure time) for erasure
should be a minimum of forty (40) Wsec/cm 2 .

FUNCTIONAL TESTING
Since the logical operation of the 5AC312 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application-independent test
patterns. EPROM cells in the 5AC312 are 100%
tested for programming and erase. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.

The erasure time with this dosage is approximately 1
hour
using
an
ultraviolet
lamp
with
a
12,000 p.W/cm2 power rating. The device should be
placed within 1 inch of the lamp tubes during exposure. The maximum integrated dose the 5AC312
can be exposed to without damage is
7258 Wsec/cm 2 (1 week at 12,000 /LW/cm2). Exposure to high intensity UV light for longer periods may
cause permanent damage to the device.

The testability and reliability of EPROM-based programmable logic devices are important features over
similar devices based on fuse technology. Fusebased programmable logic devices require a user to
perform post-programming tests to insure device
functionality. During the manufacturing process,
tests on these parts can only be performed in very
restricted manners to prevent pre-programming of
the array.

DESIGN SECURITY·
A Security Bit provides a programmable security option to protect the data programmed in the device.
Once this bit is set during programming, subsequent
attempts to read the device architecture information
are prevented. This method provides a higher degree of design security than fuse-based devices,
since programmed EPROM cells are invisible even
to microscopic examination. The Security Bit (also
called the Verify Protect Bit), along with all the other
EPROM cells, is reset by erasing the device.

3-9

inter

5AC312

Detailed information on the Intel Programmable Logic Development Sy~tem II is contained in a separate
Intel data sheet. (Order Number: 280168)

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)
Release 2.0 of iPLDS II provides all the tools needed
to design with the 5AC312 EPLO. In addition to providing development assistance, iPLDS II insulates
the user from knowing the intricate details of EPLD
architecture (the machine will optimize a design to
benefit from architectural features). It contains comprehensive third generation software that supports
four different design entry methods, minimizes logic,
does automatic pin assignments and produces the
best design fit for the selected EPLD. It is user
friendly with guided menus, on-line Help messages
and soft key inputs.

tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
INP
LlNP

In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
code output files which can be downloaded to other
programmers as well.

NOTF
JOJF
JONF

RINP

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. A more integrated schematic entry method is provided by SCHEMAII-PLD.a lowcost schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entry
and State Machine design entry.

CONF

SONF

COCF
COIF

SOSF
TOIF

RONF
ROlF

TONF
TOTF

RORF

CLKB

NOCF
NORF

LlNB

NOJF
NOSF

ORDERING INFORMATION
tpD teo fMAX
(ns) (ns) (MHz)

The iPLDS operates on the IBMt PC/XT, PC/AT, or
other compatible machine with the following configuration:

25

15

50

Order
Code

Package

05AC312-25 CEROIP Commercial

1. At least one floppy disk drive and hard disk drive.

P5AC312-25 POIP

2. MS-DOStt Operating System Version 3.0 or
greater.
3. 512K Memory (640K recommended).

N5AC312-25 PLCC
30

18

40

Operating
Rilnge

05AC312-30 CEROIP Commercial
P5AC312-30 POIP

4. Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS II)
.

N5AC312-30 PLCC
35

5. A color monitor is suggested.

20

40

05AC312-35 CEROIP Commercial
P5AC312-35 POIP
N5AC312-35 PLCC

3-10

infef

5AC312

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vecl (1) .......... -2.0V to +7.0V
Programming Supply
Voltage (Vpp) (1) ............. -2.0V to + 13.5V
D.C. Input Voltage (VI)(l, 2) ... -0.5V to Vee + 0.5V
Storage Temperature (Tstg) ..... - 65·C to + 150·C

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other condition$ above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Ambient Temperature (Tamb) (3) .. -1 O·C to + 85·C

NOTICE- Specifications contained within the
fol/owing tables are subject to change.
NOTES:--

1. Voltages with respect to GND.
2. Minimum D.C. input is -O.SV. During transitions, the inputs may undershoot to -2.0V or overshoot to
less than 20 ns under no load conditions.
3. Under bias. Extended temperature range versions are available.

+ 7V for periods of

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

4.75

5.25

V

Input Voltage

0

Vee

V

Vo

Output Voltage

0

Vee

V

TA

Operating Temperature

0

+70

·C

tR

Input Rise Time

500

ns

tF

Input Fall Time

500

ns

Vee

Supply Voltage

VIN

D.C. CHARACTERISTICS
Symbol

TA = O·Cto +70·C, Vee = 5.0V ±5%

Parameter

Max

Unit

High Level Input Voltage

2.0

Vee + 0.3

V

VIL(4)

Low Level Input Voltage

-0.3

0.8

V

VOH(S)

High Level Output Voltage

VIH(4)

Min

Typ

2.4

V

Test Conditions

10 = -4.0 mA D.C.,
Vee

=

min.

VOL

Low Level Output Voltage

0.45

V

10 = 8.0 mA D.C.,

II

Input Leakage Current

±10

p,A

Vee = max.,
GND < VIN < Vee

loz

Output Leakage Current

±10

p,A

Vee = max.,
GND < VOUT

Isd6)

Output Short Circuit Current . -30

-90

mA

Vee = max.,
VOUT = 0.5V

Iss(7)

Standby Current

100

150

p,A

Vee = max.,
VIN = Vee or GND,
Standby Mode

led8)

Power Supply Current

10

mA

Vee = max.,
VIN = Vee or GND,
No Load, Input Freq. = 1 MHz
Active Mode (Turbo = Off),
Device Prog. as 12-Bit Ctr.

Vee

=

min.

< Vee

NOTES:

4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. Do not
attempt to test these values without suitable equipment.
S. 10 at CMOS levels (3.84V) = -2 mA.
6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.
7. With Turbo Sit Off, device automatically enters standby mode approximately 100 ns after last input transition.
8. See graph at end of data sheet for IcC vs. frequency.
3-11

inter

5AC312

CAPACITANCE
Symbol

Parameter

Min

Typ

Unit

Max

Conditions

= OV, f = 1.0 MHz
= 1.0 MHz

CIN

Input Capacitance

8

pF

VIN

COUT

110 Capacitance

15

pF

Vour'" OV, f

CClK

ILE/ICLK/INP2 Capacitance

12

pF

VIN == OV, f == 1.0 MHz

Cvpp

Vpp Pin (CLK/INP1)

25

pF

VIN

A.C. TESTING LOAD CIRCUIT

INPUT
855.!l

O~~~~C)~~-1~~>~~S~i~T
OUTPUT
(INCLUDES JIG
CAPACITANCE)

A.C. CHARACTERISTICS
From

T A = O·C to

To

3'°-Y20
o-AO:8>

TEST POINTS

V2E

<~

1~-TEST POINTS-~
290156-8

A.C. Testing: Inputs are driven at 3.0V for a Logic "I" and OV for
a logic "0". Timing Measurements are made at 2.0V for a Logic
"I" and O.SV for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. Device input rise, and fall ijmes < 6 ns.

290156-7

Symbol

== 1.0 MHz

A.C. TESTING INPUT, OUTPUT WAVEFORM

....----5V

34Ul

== OV, f

+ 70·C, Vee

5AC312-25
Min

Typ

Max

= 5.0V

± 5%, Turbo Bit "On"(9)

5AC312-30
Min

Typ

Max

5AC312-35
Min

Typ

Max

Non-(l1)
Turbo
Mode

Unit

tpDI

Input

Comb. Output

20

25

25

30

30

35

+20

ns

tpD2

1/0

Comb. Output

20

25

25

30

30

35

+20

ns

tpZX(IO)

lor 1/0

Output Enable

20

25

25

30

30

35

+20

ns

tpXZ(10)

10ril0

Output Disable

20

25

25

30

30

35

+20

ns

tClR

Asynch. Reset

25

25

30

30

35

+20

ns

Asynch. Set

a Reset
a Set

20

tSET

20

25

25

30

30

35

+20

ns

NOTES:
9. Typical values are at TA = 25'C, VCC = 5V, Active Mode.
10. tpzx and tpxz are measured at ± 0.5V from steady-state voltage as driven by spec. output load. tpxz is measured with
Cl = 5 pF.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown.

3-12

5AC312

SYNCHRONOUS CLOCK MOCE (MACROCELLS) A.C. CHARACTERISTICS
TA = OOG to + 70o G, VCC = 5.0V ± 5%, Turbo Bit On(8)
Symbol

5AC312-25

Parameter

Min
fMAX

fCNT

Typ

Max

Max. Frequency (Pipelined)
1/tsu-No Feedback

66

Max. Count Frequency

40

5AC312-30
Min

Typ

Max

50

50

33

35

5AC312-35
Min

Non·(11)
Turbo
Mode

Unit

Typ

Max

40

50

40

MHz

30

28.5

25

MHz

1/tCNr-with Feedback
tsUl

Input Setup Time to ClK

20

15

25

20

25

20

+20

ns

tSU2

I/O Setup Time to ClK

20

15

25

20

25

20

+20

ns

tH

I or I/O Hold after ClK High

0

teo

ClK High to Output Valid

tCNT

Macrocell Output Feedback
to Macrocellinput-internal Path

30

tCH

ClK High Time

10

12.5

12.5

ns

, tCL

ClKlowTime

10

12.5

12.5

ns

0
10

0

15

25

12
35

ns

18

30

15
40

20

35

ns
+20

ns

SYNCHRONOUS CLOCK MOCE (INPUT STRUCTURE) A.C. CHARACTERISTICS
= OOG to +70o G, VCC = 5.0V ±5%, Turbo Bit On(8)

TA

Symbol

5AC312-25

Parameter

Min
fMAXI

Max. Frequency

tSUIR

Input Register/latch Setup Time
before IlEI/ClK

Typ

Max

50

40

5

5AC312-30
Min

Typ

Max

40

33

5

5AC312-35
Min

Typ

Max

33

28.5

Non..(11)
Turbo
Mode

Unit

MHz

5

ns

tpU(12)

Minimum Input Clock Period

tHI

I Hold after IClKl/lE

teol

IClK

tEOI

IlE t to Comb. Output

tCHI

IlEl/elK High Time

10

12.5

12.5

ns

tcu

IlEI/ClK low Time

10

12.5

12.5

ns

.J,

.J,

20

25

7

to Comb. Output

25

30

10

25

30

+20

12

ns
ns

30

35

35

40

35

40

+20

ns

30

35

35

40

35

40

+20

ns

NOTE:
12. tpu = Input signal through registersl/atch to macrocell register input.

3-13

inter

5AC312

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
TA = O°C to

+ 70°C, VCC

Symbol

= 5.0V ±5%, Turbo Bit On(8)
5AC312-25

Parameter

Min

Typ

Max

5AC312-30
Min

Typ

Max

5AC312-35
Min

Typ

Max

Non-(10)
Turbo
Mode

Unit

INPUT STRUCTURE
fAMAXI

Max. Frequency Input Register

50

,40·

40

MHz

l/(tACLI + tACHI)
tASUI

Input Register/latch Setup
Time to Asynch. IlE/IClK

0

0

tAHI

Input Register/latch Hold
after Asynch. IlE/IClK

20

tACOI

Asynch. IClK to Comb. Output

40

48

45

55

50

60

+20

ns

tAEOI

Asynch, IlE t to Comb. Output

40

48

45

55

50

60

+20

ns

0

14

25

20

30

+20

ns

ns

25

tACHI

Asynch. IClK High Time

10

12,5

12.5

ns

tACLI

Asynch. IClK low Time

10

12,5

12.5

ns

MACROCELLS
fAMAX

Max. Frequency (Pipelined)

50

40

40

MHz

25

MHz

l/(tACL + tACH)-No Feedback
fACNT

Max. Frequency

40

33

35

28.5

30

l/tACNT-with Feedback
tASU1

Input Setup Time to
Asynch. Clock

10

12

15

+20

ns

tASU2

110 Setup Time to
Asynch. Clock

10

12

15

+20

ns

tAH

Input or I/O Hold after
Asynch. Clock

5

tACO

Asynch. ClK to Output Valid

tACNT

Register Output Feedback
to Register InputInternal Path

30

tACH

Asynch. ClK High Time.

10

12.5

12.5

ns

tACL

Asynch. ClK low Time

10

12.5

12.5

ns

0

20

5

0

35

30

25

25

3-14

25

5

30

0

30
40

35

ns

35

+20

ns

+20

ns

inter

5AC312

INPUT-CLOCK-TO-MACROCELL-CLOCK A.C. CHARACTERISTICS
vcc = 5.0V ±5%, Turbo Bit On(8)

TA = O·C to +70·C,
Symbol

5AC312-25

Parameter

Min
tC1C2

Typ

5AC312-35

5AC312-30

Max

Min

Typ

Max

Min

Typ

Max

Non-(10)
Turbo
Mode

Unit

Synchronous IlEIIClK to
Synchronous Macrocell ClK

25

30

35

+20

ns

Synchronous IlE/lClK to
Asynchronous Macrocell ClK

15

18

20

+20

ns

Asynchronous IlE/lClK to
Synchronous Macrocell ClK

35

40

45

+20

ns

Asynchronous IlE/lClK to
Asynchronous Macrocell ClK

25

35

40

+20

ns

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR

I/o

\ /

---------------------'j'~---------------------------------_tpD---I

COMBINATORIAL OUTPUT
______________
____
~

~

________

\ /

_Jj'~

_______________________

I------tpxz - - - - I
HIGH IMPEDANCE

COMBINATORIAL OR
REGISTERED OUTPUT

3-STATE

I---- tpzx - - - I
HIGH IMPEDANCE

VALID OUTPUT

3-STATE
_t"'CLR _
_

t"'SET_

VALID OUTPUT
.\/
ASYNCHRONOUSLY
_______________________________________
J1'-_______________
S_ET
__
OR_R_E_SET
__
OU_TP_U_T____- -

290156-9

3-15

5AC312

SWITCHING WAVEFORMS (Continued)
SYNCHRONOUS CLOCK MODE (MACROCELLS)

ClK

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT

290156-10

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

IlE,lClK

INPUT MAY CHANGE

INPUT MAY
CHANGE

INPUT MAY CHANGE

DATA VALID
BEFORE IlE
(SEE NOTE)

1-----

tEOI

INPUT MAY CHANGE

----I

INPUT LATCH/REGISTER TO
COMBINATORIAL OUTPUT

VALID OUTPUT

NOTE: WHEN IlE GOES HIGH BEFORE DATA IS VALID, USE tpD
INSTEAD OF tEOI.

3-16

290156-11

inter

5AC312

SWITCHING WAVEFORMS

(Continued)

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

ASYNCH.
ILE/CLK
INPUT

INPUT MAY CHANGE

INPUT MAY CHANGE

INPUT MAY
CHANGE

INPUT MAY CHANGE

INPUT LATCH/REGISTER TO
COMBINATIONAL OUTPUT

VALID OUTPUT

NOTE: WHEN ILE GOES HIGH BEFORE DATA IS VALID, USE tpD
INSTEAD OF tAEOI.

290156-13

ASYNCHRONOUS CLOCK MODE (MACROCELLS)

ASYNCH.
CLOCK
INPUT

FLOW
THROUGH
INPUT

INPUT MAY CHANGE

INPUT MAY CHANGE

FLOW THROUGH INPUT
TO REGISTERED OUTPUT

VALID OUTPUT
290156-12

3-17

intJ

5AC312

SWITCHING WAVEFORMS

(Continued)

INPUT CLOCK-TO-MACROCELL CLOCK TIMING (CLOCKED PIPELINED DATA)

IlE,lClK

INPUTS

ClK

VALID

OUTPUTS

OUTPUT
290156-18

CLOCK, SETUP, HOLD, and OUTPUT VALID times are dependent on synchronous/asynchronous clocking and are
listed in the specification tables.

Current in Relation to Frequency
120
110
100
90
80
~ 70
,5. 60
()
..Y 50
40
30
20
10

I
II

Output Drive Current in Relation to Voltage

-

I

1

50

~

20

o

10

c

::J

--

/

..........

~

::J

.e-

J

::J

o
~

I

I
I

5
2
1

5

o

10 15 20 25 30 35 40
ICNT (MHz)

Conditions: TA

=

O'C, Vee

=

5.25V

2

3

4

5

Vo Output Voltage (V)
290156-20

ConditIons: T A =

3-18

+ 25'C

290156-16

intJ

5AC324
1-MICRON CHMOS EPLD

• High-Performance LSI Semi-Custom
Logic Alternative to Low-end Gate
Arrays, TTL, and 74HC SSI and MSI
Logic

• 2 Product Terms on All Macrocell
Control Signals

• High Speed tpD (max) 35 ns, 40 MHz
Performance Pipelined, 25 MHz wI .
Feedback

• Programmable Low-Power Option for
"Stand-by" Operation; 150 JLA Typical
Standby Current

• 24 Macrocells with Programmable I/O
Architecture; 10 Programmable Inputs;
1 Dedicated Input or Global CLK Pin; 1
Dedicated Input or Global ILE/ICLK Pin

• UV Eraseable EPROM Technology.
100% G,merically Testable EPROM
Logic Control Array

• Programmable Output Registers
Configurable as D, T, JK, or SR Types

• Programmable Security Bit Allows
100% Protection of Proprietary Designs

• Programmable Inputs Conflgurable as
Latches, Registers, or Flow-Through

• (Proposed) JEDEC Pinout
• Available in 40-pin DIP and 44-pin JLeaded Chip Carrier Package (Ceramic
and Plastic)

• Software-Supported Product Term
Allocation Between Adjacent
Macrocells
• Dual Feedback on All Macrocells for
Implementing Buried Registers with
Bidirectional 1/0

(See PackagIng Spec., Order Number .. 231369)

CLK/INPI
LlNPl
LlNP2

LINP8

1/0.1

1/0.24

1/0.2

1/0.23

1/0.3

1/0.22

GND

1/0.4

1/0.21

1/0.5

GND

1/0.3

7

1/0.22
1/0.21

1/0.4

Vee

Vee

5AC324

1/0.20
1/0.19

1/0.5

1/0.20

NC

1/0.6

1/0.19

1/0.7

1/0.7

1/0.18

1/0.8

1/0.17

GND

GND

1/0.16
1/0.15

1/0.16

NC

1/0.18
1/0.17

1/0.15
1/0.14
1/0.13
LlNP7
LlNP6
ILE/ICLK/INP2

290160-2

290160-1

Figure 1. 5AC324 Pinout Diagrams

3-19

August 1988
Order Number: 2901fiO.OOl

5AC324

INTRODUCTION

ARCHITECTURE DESCRIPTION

The Intel 5AC324 CHMOS EPLD (Erasable Programmable Logic Device) is a high integration device that overcomes the primary limitations of standard PLDs. Due to a proprietary I/O .architecture and
macrocell structure, the 5AC324 is capable of implementing high performance logic functions more effectively than previously possible. The 5AC324 can
be used as an alternative to low-end gate arrays,
multiple programmable logic devices, or LS-, HC-, or
HCT 551 and MSI logic devices. Input and macrocell
features for the 5AC324 are a superset of features
offered on other PLD-type products.

The architecture of the 5AC324 is based on the familiar ~'Sum-Of-Products" programmable AND, fixed
OR structure. This structure is then surrounded by
powerful, programmable macrocells and inputs. The
5AC324 can implement both combinatorial and sequential logic functions through a highly flexible
macroceil and I/O structure. The architecture of the
device supports both combinatorial-register and register-combinatorial-register forms. of logic to easily
acc0modate state machine designs.

The 5AC324 uses advanced CHMOS EPROM cells
as logic control elements instead of poly-silicon fuses. This technology. allows the device to operate at
levels necessary in h,gh performance systems while
significantly reducing power consumption. Its programmable standby mode reduces power to near
zero in applications where a slight speed loss is traded for power savings.

Figure 2 shows a global view of the 5AC324 architecture. The 5AC324 contains a total of 24 I/O programmable macrocells, 10 programmable input
structures, and two clock inputs that can be programmE;ld to function either as combinatorial inputs
or clock inputs for the input structures and macrocells.
Each of the ten programmable inputs can be individually configured as a latch, register or flow-through

CLK/INPI D-------_---==~:::::;

LlNPI

. LOGIC ARRAY
(GLOBAL BUS)

1/0.1

1/0.2
LINP2
MACROCELLS
1 THRU 12
(RING 1)

•
•
•

LlNP3

LlNP4

1/0.12

LINP5

LlNP6

1/0.13

LlNP7

1/0.14
MACRO.CELLS
13 THRU 24
(RING 2)

•
•
•

LINP8

LINP9

1/0.24
LlNP10

ILE/ICL~/INP2

D - - -.....- - - - '
290160-3

Figure 2. 5AC324 Global Architecture
3-20

l
LOGIC ARRAY

TO NEXT
MACROCELL

tT

rROM NEXT
MACROCELL
OUTPUT

~

1
11

II

II

II II n.....

;1

II

II

II II

.

--

-. I I

PRESET

a
c

01

>0

LOWER HALr

I

~I

OUTPUT
MUX

Co)

N

V

~

(oJ

•

N
.....

iI:

..
!:
..>-

en

><

~

III

0

0

N

n

w

""

n
n

II II II II II ~

'-I'

~
l§!

ASYNCH. CLK (CLKB)

~

Cil

~

CLEAR
TO PREVIOUS '"
MACROCELL

©

1rROM
PREVIOUS
MACROCELL

1I

!iiiiI
c:::::>

~

'liil

290160-4

@
aeJ
~
~
~

c:::::>

@
~

intJ

5AC324

input. Input latches/registers can be synchronously
or asynchronously clocked.

structures. For asynchronous operation, a separate
product term in the array is used to derive the ILE/
ICLK signal for each input structure. Because the
clock signal for each programmable input can be individually selected, a mix between synchronously
and asynchronously clocked inputs is possible. Software can configure each input structure as a flowthrough input by selecting a latch and tying the ILE
p-term to VCC. When ILE/ICLK is not used as a
latch/clock, it functions as a dedicated input to the
logic array. Data is latched/clocked on the falling
edge of ILE/ICLK (synchronous mode).

Figure 3 shows the basic architecture of each of the
24 macrocells in the 5AC324. Each macrocell contains 16 p-terms (product terms), with 8 p-terms
available for the global array and 8 p-terms dedicated to the four control signals: OE, PRESET, CLEAR,
and ASYNCH. CLK. The 8 p-terms from the logic
array are organized as a user-programmable AND
array and a user-configurable OR array. The inputs
to the AND array originate from the true and complement signals from the programmable input structure,
the dedicated inputs, and the 48 feedback paths
from the 24 I/O macrocells to the global bus. This
global bus simplifies designing with the device by
eliminating the need to partition a circuit to fit into a
local/global internal bus structure.

MACROCELLS
Each of the 24 macrocells in the device contains 8
p-terms to support logic functions and 8 p-terms for
control signals. The 8 p-terms for logic functions are
subdivided into 2 groups;each with 4 p-terms. This
grouping of p-terms supports the proprietary p-term
allocation scheme in the 5AC324. Each macrocell
also provides dual feedbacks to the logic array,
which results in more efficient macrocell/pin usage
than possible with single feEldbacks.

INPUTS
Figure 4 shows a block diagram of the 5AC324 input
structure. The device contains 10 user-programmable inputs that can be individually configured to operate in one of five modes:
• input register (D-register), synchronously clocked

Register Configuration

• input register (D-register), asynchronously
clocked
• input latch, (D-Iatch), synchronously clocked

Each macrocell can be configured as a 0, T, RS, or
JK register. The 8 p-terms for control functions are
organized so that 2 p-terms support each of the 4
c()ntrol signals: Output Enable (OE), asynchronous
I/O preset (PRESET), asynchronous I/O reset
(CLEAR), and asynchronous I/O 'register clock (AS_YNCH. eLK). Availability of 2 p-terms per control signal is another feature that increases the efficiency of
the device by reducing the need to use intermediate
macrocells sometimes needed to implement controlfunctions.

• input latch, (D-Iatch), asynchronously clocked
• Flow-through input

<

Configuration is accomplished through the programming of EPROM architecture control bits via the logic compiler and programmer software. If synchronous operation is selected, the ILE/ICLK pin is used
as a global latch/clock to all input latch/register

INPUT

0--+1 D

Q

LATCH/
REGISTER

1-------...

TO LOGIC
ARRAY

CLOCK/ENABLE
SELECT
P-TERM
FROM LOGIC
ARRAY

LATCH/REG.
SELECT'

ILE/ICLK

D------------.. .

290160-5

NOTE:
Software implements a direct (flow-through) input by selecting an asynchronous latch and tying its control P-term to Vee.

Figure 4_ 5AC324 Programmable Input Structure
3-22

5AC324

ClK is a global clock signal that can be used to
synchronously clock any or a" macroce" registers.
When ClK is not used as a synchronous clock, it
functions as ~ dedicated input to the logic array.

EXAMPLE:

Figure 5 shows a p-term allocation example. In this
example, the logic function in macroce" 4 requires
16 p-terms. In this case, software allocates 4 pterms from the previous macroce" in Ring 1 (macrocell 5) and 4 p-terms from the next macroce" (macroce" 3) to accumulate a total of 16 p-terms (8 + 4
+ 4). This implementation leaves macroce"s 3 and
5 with a remainder of 4 p-terms. These remaining pterms can also be allocated away to, or supplemented with p-terms from, their adjacent macroce"s in
Ring 1 (macroce"s 2 and 6).

Combinatorial Configuration
The macroce" register can be bypassed to implement combinatorial logic functions. When configured
to provide combinatorial logic, only the OE control
signal is used.

Invert Select Bit

With this scheme, any macroce" inside the device
can support logic functions requiring between 0 and
16 p-terms. P-terms allocated away do not affect
that macrocell's output structure. The input to the
macroce" can be tied to VCC or GND, even when a"
p-terms have been allocated away. Thus the register
and a" control signals are still available for use if
needed.

An invert select EPROM bit is used to invert the
product term input into each macroce" register, including double inputs on JK and SR registers. This
invert option allows the highest possible logic utilization by use of DeMorgan's logic inversion.

LOGIC ARRAY

Figure 6 shows adjacent macroce"s in the 5AC324.
Table 1 shows the previous and next macroce"s for
each macroce" in the device, along with the corresponding allocation ring. P-term allocation is implemented automatically in the develpment software
and is transparent to the user. Users can still use
explicit pin assignment, but should assign pins in a
way that does not conflict with p-term allocation.

Each intersecting point in the logic array contains a
programmable EPROM connection. Initia"y (erased
state), a" connections are complete, i.e., both true
and complement states of a" signals are connected
to each p-term.
Connections are opened during programming. When
both the true and complement connections exist, a
logical false results on the output of the AND gate. If
both the true and complement connections of a signal are programmed "open", then a logic "don't
care" results for that signal. If a" connections for a
p-term are programmed open, then a logical true results on the output of the AND gate.

Software support allows the control signals on macroce"s to be used to implement simple logic functions even when a" the input p-terms have been allocated to adjacent macroce"s.

DUAL-FEEDBACK/BURIED LOGIC
Macroce" output can be fed back to the logic array
on either one of the two feedback paths. If the pin
feedback is used (connected after the output buffer),
bidirectional 1/0 can be implemented. If the internal
feedback path is used to implement a buried register
or buried logic function, the pin feedback is still available for use as an input. The availability of dual feedbacks on the 5AC324 enhances resource efficiency
over single feedback devices.

PRODUCT TERM ALLOCATION
Product Term (p-term) allocation is defined as taking
logic resources (p-terms) from macroce"s where
they are not used to support demand for additional
p-terms in other macroce"s. In the 5AC324, p-term
allocation can occur in increments of 4 p-terms between adjacent macroce"s. The 5AC324 includes 2
rings of 12 macroce"s each. P-term groups from one
macroce" can be allocated to the adjacent macrocell in the ring. P-term allocation between the two
rings is not supported.

AUTOMATIC STAND-BY MODE
The 5AC324 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed (TURBO = ON), the device is optimized for maximum

3-23

l

LOGIC ARRAY

LOWER HALF
P-TERMS 1-4
MACROCELL

#5

P., TERMS ALLOCATED TO
MACROCELL #4
(NEXT MACROCELL IN RING)

.,..

cO"
e

iil

UPPER HALF
P-TERMS 5-8

!"
"tI

..

.!oj

CD

3

~

0c.J
!!l.
N
0"
.j>.
n

~

MACROCELL
#4

o

Co)
I\)
~

::J

rn

)C

I»

3
iD
Cii
""0

~
l§l

..,.+

~

+
~

UPPER HALF
P-TERMS 5-8

::2

©

P-TERMS ALLOCATED TO
MACROCELL #4
(PREVIOUS MACROCELL IN RING)

Iiiiil

~

'1ij)

©

MACROCELL

2eJ

#3

~

~
~

c:::::>

290160-6

@

::2

inter

5AC324

ADJACENT MACRO CELLS
FOR RING 1

ADJACENT MACROCELLS
FOR RING 2

MACRO CELL
1

MACROCELL
24

MACRO CELL
2

MACROCELL
23

MACROCELL
3

MACROCELL
22

MACROCELL
4

MACROCELL
21

MACROCELL
5

MACROCELL
20

MACROCELL
6

MACROCELL
19

MACRO CELL
7

MACROCELL
18

MACROCELL
8

MACROCELL
17

MACROCELL
9

MACROCELL
16

MACROCELL
10

MACROCELL
15

MACRO CELL
11

MACROCELL
14

MACRO CELL
12

MACROCELL
13
290160-7

Figure 6. 5AC324 Adjacent Macrocell
Table 1. Product Term Allocation Rings
RING 1

RING 2

Current
Macrocell

Next
Macrocell

Previous
Macrocell

Current
Macrocell

Next
Macrocell

Previous
Macrocell

1
2
3
4
5
6
7
8
9
10

7
1
2
3
4
5
8
9
10

2
3
4
5
6
12

11

12
6

13
14
15
16
17
18
19
20
21
22
23
24

19
13
14
15
16
17
20
21
22
23
24
18

14
15
16
17
18
24
13
19
20
21
22
23

12

11

1

7
8
9
10
11

3-25

infef

5AC324

speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during-periods of
inactivity.

POWER-ON CHARACTERISTICS
On Vee power-up, the 5AC324 registers are reset to
a logic low. Input latch/register output (to the logic
array) are also set to a logic low. 5AC324 inputs and
outputs begin responding approximately 20 ,...8 after
Vee power-up or after a power-Ioss/power-up sequence. After power-up, macrocells can be preset to
a logic high via the PRESET control signal for each
macrocell.

Figure 7 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 15 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

ERASED STATE CONFIGURATION
After erasure and prior to programming, all macrocells are configured as combinatorial outputs with
output buffers three-stated. Inputs are configured as
synchronous registers.

After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

FIRST
INPUT

LAST
INPUT

t

-----

~----------------~
r---------------~

OUTPUT

CURRENT
OmA

VALID OUTPUT

VALID OUTPUT

ACTIVE MODE

ACTIVE MODE

Icc

Icc

----------------------~==~====~~--------------290160-6
Figure 7. 5AC324 Standby and Active Mode Transitions

3-26

5AC324

attempts to read the device architecture information
are prevented. This method provides a higher degree of design security than fused-based devices,
since programmed EPROM cells are invisible even
to microscopic examination. The Security Bit (also
called the Verify Protect Bit), along with all the other
EPROM cells, is reset by erasing the device.

ERASURE CHARACTERISTICS
Erasure time for the 5AC324 is 1 hour at 12,000
mW/cm 2 with a 2537A UV lamp.
Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 30ooA4000A range. Data shows that constant exposure to
room level flourescent lighting could erase the typical 5AC324 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device window to prevent unintentional erasure.

LATCH-UP IMMUNITY
All of the input, 110, and clock pins of the device
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5AC324 is designed with Intel's proprietary 1-micron CHMOS
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -0.5V to Vee + 0.5V. The
programming pin is designed to resist latch-up to the
13.5V maximum device limit.

The recommended erasure procedure for the
5AC324 is exposure to shortwave ultraviolet light
with a wavelength of 2537A. The integrated dose
(Le., UV intensity x exposure time) for erasure
should be a minimum of fifteen (15) Wsec/cm 2. The
erasure time with this dosage is approximately 1
hour using an ultraviolet lamp with a 12,000 mWI
cm2 power rating. The device should be placed Within 1 inch of the lamp tubes during exposure. The
maximum integrated dose the 5AC324 can be exposed to without damage is 7258 Wsec/cm 2 (1
week at 12,000 ,...W I cm 2). Exposure to high intensity
UV light for longer periods may cause permanent
damage to the device.

DESIGN RECOMMENDATIONS
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or Your) < Vee. All unused inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capaCitor of at
least 0.2,...F must be connected directly between
each Vee and GND pin.
As with all CMOS devices, ESD handling procedures
should be used with the 5AC324 to prevent damage
to the device during programming, assembly, and
test.

inteligent ProgrammingTM Algorithm
FUNCTIONAL TESTING

The 5AC324 supports the inteligent Programming Algorithm, which rapidly programs Intel EPLDs, and
many of Intel's microcontrollers and EPROMs while
maintaining a high degree of reliability. It is particularly suited for production programming environments. This method decreases the overall programming time while programming reliability is ensured as
the incremental programming margin of each bit has
been verified during programming. Programming
voltage and waveform specifications are available
by request from Intel to support programming the
device.

Since the logical operation of the 5AC324 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application independent test
patterns. EPROM cells in the device are 100% tested for programming and erasure. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.

DESIGN SECURITY

The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure

A Security Bit provides a programmable security option to protect the data programmed in the device.
Once this bit is set during programming, subsequent

3-27

intJ

5AC324

device functionality. During the manufacturing process, tests on fuse-based parts can only b~ performed in very restricted ways in order· to avoid preprogramming the array.

will compile 5AC324 designs and product a Logic
Equation File (LEF) and a Report File. No JEDEC file
is produced..
Full iPLS II. support (including JEDEC generation capability) is provided by Version 2.0 of iPLS II, which
will be available during the second half of 1988. iPLS
II includes the LOC .(Logic Optimizing Compiler), and
LPS (Logic Programming Software).

DESIGN SOFTWARE
Contact your local Intel sales office for evaluation
software to get you started with 5AC324 designs.
The evaluation software is a proprietary version of
iPLS II (Intel Programmable Logic Software II) that

ORDERING INFORMATION
tpo
(ns)

tco
(ns)

fMAX.
(MHz)

35

20

40

40

25

33

Package

Order Code
N5AC324-35

PLCC

P5AC324-35

PDIP

CJ5AC324-35

J LEAD CHIP CARRIER

D5AC324-35

CERDIP

N5AC324-40

PLCC

P5AC324-40

PDIP

CJ5AC324-40

J LEAD CHIP CARRIER

D5AC324-40

CERDIP

3-28

Operating Range
Commercial

Commercial

5AC324

* Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vec>(1) .......... - 2.0V to + 7.0V
Programming Supply
Voltage (Vpp)(1) .............. - 2.0V to + 13.5V
D.C. Input Voltage (VI)(1.2) .... -0.5V to Vee +0.5V
Storage Temperature (T stg) ..... - 65°C to + 150°C
Ambient Temperature (T amb)(3) ...... -1 ooe to + 85°e

NOTICE Specifications contained within the
fol/owing tables are subject to change.

NOTES:
1. Voltage with respect to GND.
2. Minimum D.C. input is - 0.5V. During transitions.
the inputs may undershoot to - 2.0V for periods of
less than 20 ns under no load conditions.
3. Under bias. Extended Temperature versions are
also available.

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee
VIN
Vo
TA
tR
tF

Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise Time
Input Fall Time

D.C. CHARACTERISTICS

Min
4.75

Max
5.25

0
0
0

Vee
Vee
+70
500
500

Unit
V
V
V
°C
ns
ns

(TA = 'G°eto + 70°C, Vee = 5.0V ±5%)

Symbol

Parameter

Min

Max

Unit

VIH(4)

High Level Input Voltage

2.0

Vee +0.3

V

VIL(4)

Low Level Input Voltage

-0.3

0.8

VOH(5)

High Level Output yoltage

VOL

Low Level Output Voltage

II

Typ

Test Conditions

V

10 = -4.0 mA D.C .•
Vee = min.

0.45

V

10 = 4.0 mA D.C.,
Vee = min.

Input Leakage Current

±10

iJ-A

Vee = max.,
GND < VIN < Vee

loz

Output Leakage Current

±10

iJ-A

Vee = max.,
GND < VOUT

Ise(6)

Output Short Circuit Current

ISB(7)

Standby Current

lee

Power Supply Current

2.4

-30

-90

< Vee

mA

Vee = max., VOUT = 0.5V

150

iJ-A

Vee = max., VIN = Vee or
GND, Standby Mode

50

mA

Vee = max., VIN = Vee or
GND. No Load, fiN = 1 MHz,
Active Mode (Turbo Off),
Device Prog. as Two
12-Bit Counters

NOTES:

4.
5.
6.
7.

Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included.
10 at CMOS levels (3.84V) = - 2 mA.
Not more than 1 output should be tested at a time. Duration of that test should not exceed 1 second.
With Turbo Bit Off. device automatically enters standby mode approximately 100 ns after last input transition.
3-29

intJ

5AC324

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

,..----5V
INPUT

855.0.

DEVICE D--I-.....--C> TO TEST
OUTPUT
SYSTEM
OUTPUT
341.0.

(INCLUDES JIG
CAPACITANCE)

3.0~20•

°

_0.8

>

TEST POINTS

< ~20.
.

0.8

l~-TEST POINTS-~

290160-10
A.C. Testing: Inputs are driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V far a Logic
"1" and O.SV for a Logic "0" on Inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times are less than 6 ns.

290160-9

CAPACITANCE
Typ

Max,

Unit

5

20

pF

Output Capacitance

10

20

pF

Your = OV, f = 1.0 MHz

Clock Pin Capacitance

10

20

pF

Your = OV, f = 1.0 MHz

Vpp Pin Capacitance

20

40

pF

Vpp on LlN3

Symbol

Parameter

CIN

Input Capacitance

Cour
CCLK
CvPp

Min

3-30

Conditions
VIN = OV, f = 1.0 MHz

inter

5AC324

COMBINATORIAL MODE A.C. CHARACTERISTICS
(TA = O·C to +70·C,
Symbol

vcc

= 5.0V ±5%, Turbo Bit On)(8)

5AC324-40

5AC324-35

Parameter

Min

Typ

Max

Min

Typ

Max

Non-Turbo(9)
Mode

Unit

tpD

Input or 1/0 to Output

30

35

35

40

+15

ns

tpZX(10)

Input or 1/0 to Output Enable

30

35

35

40

+15

ns

tpXZ(10)

Input or 1/0 to Output Disable

30

35

35

40

+15

ns

tClR

Asynch. Reset to Q Clear

30

35

35

40

+15

ns

tSET

Asynch. Set to Q Set

30

35

35

40

+15

ns

NOTES:
8. Typical values are at TA = + 25°C, Vee = 5V, Active Mode.
9. If device is operated with Turbo bit Off (Non-Turbo Mode), increase time by amount shown.
10. tpzx and tpxz measured at ±0.5V from steady-state voltage as driven by spec. output load. tpxz measured with CL = 5
pF.

SYNCHRONOUS CLOCK MODE (MACROCELLS) A.C. CHARACTERISTICS
(TA = O·C to +70·C, VCC = 5.0V ±5%, Turbo Bit On)(8)
5AC324-35

Symbol Parameter

Min

Typ

5AC324-40

Max Min Typ Max

Non·Turbo(9)
Mode

Unit

fMAX

Maxim\,lm Frequency (1 Itsu)
No Feedback

50

40

40

33.3

(11)

MHz

fCNT

Maximum Frequency (1 ItCNT)
With Feedback

28.5

25

25

22.2

(11 )

MHz

tSU1

Input Setup Time to ClK

tSU2

1/0 Setup Time to ClK

tH

Input or 1/0 Hold Time from ClK

teo

ClK

teNT

Register Output Feedback to Register
Input-Internal Path

teH

Clock High Time

12.5

tel

Clock low Time

lew

Minimum Clock Width

i

i

i
i

25

20

30

25

+15

ns

25

20

30

25

+15

ns

0

ns

0
+15

ns

+15

ns

15

+15

ns

12.5

15

+15

ns

25

30

+15

ns

to Output Valid

15
40

35

NOTE:
11. Recalculate frequency according to expression at left of table.

3-31

20

20
45

40

25

5AC324

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) A.C. CHARACTERISTICS
(TA = O·C to +70·C. vcc = 5.0V ±5%. Turbo Bit On)(8)
Symbol

,

5AC324-35,

Parameter ,

Min

Typ

Max

50

40

5AC324-40
Min

fMAXI

Maximum' Frequency (1/tcwl)

tSUIR

Input Register Setup Time
Before ICLK J,

5

5

tESUI

Input Latch Setup Time
Before ILE t

5

5

tCOI

IClK

J,

to Comb. Output

J,

30

35

35

40

Typ

Max

40

33.3

Non-Turbo(9)
Mode

Unit

(11)

MHz

,

ns
ns
ns

40

45

+15

45

50

+15

ns

ns

5

tHI

Input Hold after IClK/llE

tEOI

IlE

tCHI

IlE/lClK High Time

12.5

15

+15

ns

tCLI

IlE/lClK low Time

12.5

15

+15

ns

tcWI

Minimum Input Clock Width

25

30

+15

ns

t

5

to Comb. Output

ASYNCHRONOUS CLOCK MODE (MACROCELLS) A.C. CHARACTERISTICS
(TA

=

O·C to +70·C. Vcc

=

f/.OV ±5%. Turbo Bit On)(8)
5AC324-35

Symbol Parameter

5AC324-40

Min Typ Max Min Typ Max

t

fAMAX

Max. Frequency (1/tACL
No Feedback

fACNT

Max. Frequency (1/tACNT)
With Feedback

16.6

16.5 14.2

(11 )

MHz

15.3 14.2

14.2 13.3

+15

MHz

20

tACH)

Non-Turbo(9)
Unit
Mode

tASU1

Input Setup Time to Asynch. ClK

10

12.5

+15

ns

tASU2

1/0 Setup Time to Asynch. ClK

10

12.5

+15

ns

tAH

Input or 1/0 Hold Time from Asynch. ClK

30

+15

ns

tACO

Asynch. ClK to Output Valid

+15

ns

tACNT

Asynch. Output Feedback to Register
Input -Internal Path

70

+15

ns

tACH

Asynch. ClK High Time

30

35

+15

ns

tACL

Asynch. ClK low Time

30

35

+15

ns

tACW

Asynch. ClK Width

60

70

+15

ns

25
45

3-32

65

35
50

40
50

75

70

55

inter

5AC324

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) A.C. CHARACTERISTICS
(TA = O°C to + 70°C, Vec = 5.0V
Symbol

± 5%, Turbo

Bit On)(8)
5AC324-40

5AC324-35

Parameter

Min

Typ

Max

25

22.2

Min

Typ

Max

23

20

Non-Turbo(9)
Mode

Unit

(11 )

MHz

fAMAXI

Maximum Frequency Input Register
(1/tACWI)

tASUIR

Input Register Setup Time
Before Asynch. IClK

0

0

ns

tAESUI

Input latch Setup Time
Before Asynch. IlE

0

0

ns

tACOI

Asynch. IClK to Comb. Output

50

55

35

40

55

60

+15

45

50

+15

ns

25

ns

tAHI

Input Hold after Asynch. IClK/llE

tAEOI

Asynch. IlE to Comb. Output

tACHI

Asynch. IlEIIClK High Time

22.5

25

+15

ns

tACLI

Asynch. IlEIIClK low Time

22.5

25

+15

ns

tACWI

Minimum Input Clock Width

45

50

+15

ns

20

ns

INPUT-CLOCK-TO-MACROCELL-CLOCK A.C. CHARACTERISTICS
(T A = O°C to + 70°C, VCC = 5.0V ± 5%, Turbo Bit On)(8)
Symbol

Min

tC1C2(12)

5AC324-40

5AC324-35

Parameter

Typ

Max

Min

Typ

Max

Non-Turbo(9)
Mode

Unit

Synchronous IlEIIClK
Synchronous Macrocell ClK

30

35

+15

ns

Synchronous IlE/IClK
Asynchronous Macrocell ClK

10

20

+15

ns

Asynchronous IlE/IClK
Synchronous Macrocell ClK

45

55

+15

ns

Asynchronous IlE/ClK
Asynchronous Macrocell ClK

30

40

+15

ns

NOTE:
12. Times for SETUP, HOLD, and OUTPUT VALID are shown in previous tables.

3-33

5AC324

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR

I/o

' !/

---------------------'I~~--~-----------------------------I - - - t PD----i

COMBINATORIAL OUTPUT

\

------------------~--------~I~--------------------I----tpxz - - - _
HIGH IMPEDANCE

COMBINATORIAL OR
REGISTERED OUTPUT

3-STATE

I - - - tpzx - - HIGH IMPEDANCE
VALID OUTPUT

3-STATE
f---tACLRf---tASET-

VALID OUTPUT

\V

, Ir-,.

ASYNCHRONOUSLY
SET OR RESET OUTPUT

~-----------------------290160-11

3-34

inter

5AC324

SYNCHRONOUS CLOCK MODE (MACROCELLS)

I----tcw----J

CLK

INPUT

INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER CLOCK
TO OUTPUT)

OUTPUT

VALID OUTPUT
290160-12

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

ILE.ICLK

INPUT

INPUT MAY
CHANGE

INPUT MAY CHANGE

f - - - - tEOI - - -../
INPUT LATCH/REGISTER TO
COMBINATORIAL OUTPUT

VALID OUTPUT
290160-13

NOTE:
When ILE goes high before data is valid. use tpD instead of tEOI-

3-35

inter

5AC324

ASYNCHRONOUS CLOCK MODE (MACROCELLS)

ASYNCH.
CLOCK
INPUT

FLOW
THROUGH
INPUT

INPUT MAY CHANGE

INPUT MAY CHANGE

FLOW THROUGH INPUT
TO REGISTERED OUTPUT

VALID OUTPUT

290160-14

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)
1_--IACWI---o-l

ASYNCH.
ILE/CLK
INPUT

INPUT MAY CHANGE

J----IAEOI----1
INPUT LATCH/REGISTER TO
COMBINATIONAL OUTPUT

VALID OUTPUT

290160-15

NOTE:
When ILE goes high before data is valid, use tpD instead of tAEOf'

3-36

5AC324

INPUT-CLOCK-TO-MACROCELL CLOCK TIMING (CLOCKED PIPELINED DATA)

IlE,lClK

INPUTS
t C1C2

ClK

OUTPUTS

J

\
X

\

I
VALID
OUTPUTS
290160-16

CLOCK, SETUP, HOLD, and OUTPUT VALID times are dependent on synchronous/asynchronous clocking and are
listed in the specification tables.

3-37

85C508
FAST 1-MICRON CHMOS
DECODER/LATCH EPLD
Performance Programmable Logic
16 Dedicated Inputs for Address/Data
• High
• Bus
Device for High-Speed MlcroprocessorDecoding; 8 Latched Outputs; 1
Global Latch Enable
to-Memory Decode
1QO% Generically Testable Logic Array
Upgrade Alternative to Fast Bipolar
• PLAs
• Available
and Fast MSI Logic
In 28-pln30o-mll CERDIP and
•
PDIP Packages and in PLCC Package
Extremely High Speed-tPD 7.5 ns
• (max), 133.3 MHz (max), tEO 5 ns (max)
(See Packaging Spec., Order Number

;I' 231369)

F100111
F100112
vpp

Vee

..,

INPl

INP16

;i;

INP2

INP15

INP3

I>.

I>.

CD

t

>

g

>

on

a:: ;i;a::

;i;

01
INP4

02

04

INP7

05

INP8

06

INP9

07

S

01

INPS

03
INP6

02

INP6

03

85C508

INP10

08

INPll

INP14

INP12

INP13

GND

'" ;i;a::

;i;

04

INP9

06

INP10

07

a:-Z ....N

ALE

-

t:L

;i;

Q

Z

ell

....,

-'

-c

tt)

......

....

..-

;i;

;i;

Ill..

0..

lID

0

290175-2
290175-1

Figure 1. 85C508 Pinout Diagrams

3·38

October 1988
Order Number: 290175-001

inter

85C508

INTRODUCTION

ERASURE CHARACTERISTICS

The Intel8SCS08 1-micron CHMOs EPLD (Erasable
Programmable Logic Device) is designed to support
the speeds required in fast microprocessor to memory paths. The sixteen inputs, p-term array, and eight
output latches in the 8SCS08 provide address and
data bus decoding and latching. The 8SCS08 takes
full advantage of the lightning speed of Intel's 1-micron CHMOs technology. The 8SCS08 can be used
as an upgrade to fast bipolar PLDs, and to fast AL,
ALs, HC, or HCT 551 and Msi logic devices.

Erasure time for the 8SCS08 is 1 hour at 12,000
,...Wsec/cm2 with a 2S37A UV lamp.
Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 400A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
room level flourescent lighting could erase the typical 8SCS08 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device window to prevent unintentional erasure.

The 8SCS08 uses advanced EPROM cells as architecture and logic array storage elements instead of
poly-silicon fuses. Coupled with Intel's proprietary
CHMOs technology, the result is a device that offers
a fast 7.S ns tpD in flow-through mode and a tEO of
S ns in latch mode. The inherent speed of the device
makes the 8SCS08 ideally suited for bus decoding
applications with Intel's 80386 microprocessor and
80960 embedded controller families.

The recommended erasure procedure for the
8SCS08 is exposure to shqrtwave ultraviolet light
with a wavelength of 2S37A. The integrated dose
(Le., UV intensity x exposure time) for erasure
should be a minimum of fifteen (1S) Wsec/cm 2. The
erasure time with this dosage is approximately 1
hour using an ultraviolet lamp with a 12,000
,...W/cm2 power rating. The device should be placed
within 1 inch of the lamp tubes during exposure. The
maximum integrated dose the 8SCS08 can be exposed to without damage is 72S8 Wsec/cm 2 (1
week at 12,000 ,...W/cm2). Exposure to high intensity
UV light for longer periods may cause permanent
damage to the device.

ARCHITECTURE DESCRIPTION
The architecture of the 8SCS08 is designed for highspeed performance, with dedicated inputs feeding a
logic array. Outputs from the logic array feed the fast
output latches. All output latches are controlled by
the global ALE (Address Latch Enable) signal. Figure 2 shows the global architecture of the 8SCS08.
The input to each latch is a single NAND p-term that
can be connected to the true or complement state of
the dedicated inputs. All input signals are available
to all eight macrocells.

LATCH-UP IMMUNITY

Each intersecting point in the logic array is connected or not connected based on the value programmed in the EPROM array. Initially (EPROM
erased state), no connections exist between any pterm and any input. Connections can be made by
programming the appropriate EPROM cells. True
and complement connections cannot exist at the
same time. Since p-terms are implemented as
NANDs, a true condition on a p-term drives the output low.

All of the input, output, and clock pins of the device
have been designed to resist latch-up which is inherent in inferior CMOS structures. The 8SCS08 is designed with Intel's proprietary 1-micron CHMOs
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -O.SV to Vee + O.SV. The
programming pin is deSigned to resist latch-up to the
13.SV maximum device limit.

POWER-ON CHARACTERISTICS

DESIGN RECOMMENDATIONS

On Vee power-up~ the 8SCS08 latches respond to
the values on the input signals. No logic high/low
state is guaranteed at power up. 8SCS08 inputs and
outputs begin responding approximately S ,...s after
Vee power-up or after a power-Ioss/power-up sequence.

For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (YIN or VOUT) < Vee. All unused inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capacitor of at
least 0.2 ,...F must be connected directly' between
each Vee and GND pin.
3-39

85C508

•••
INP1

---"""01

O-~tjt:=jl
""""----....-.02

INP2

0--1t::!t:=jjjj
">--003

INP3

O-~tjt:=:tttt:U

•
•

.
-

INP16

0---1~t:=::t:t=tttt=jj

ALE 0-------------------1
Figure 2. 85C508 Global Architecture

3-40

290175-3

inter

85C508

As with all CMOS devices, ESD handling procedures
should be used with the 8SCS08 to prevent damage
to the device during programming, assembly, and
test.

The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
device functionality. During the manufacturing process, tests on fuse-based parts can only be performed in very restricted ways in order to avoid preprogramming the array.

FUNCTIONAL TESTING
Since the logical operation of the 8SCS08 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application independent test
patterns. EPROM cells in the device are 100% tested for programming and erasure. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.

DESIGN SOFTWARE
Full software support is provided by version 2.0 of
iPLS II (Intel Programmable Logic Software II). That
version includes the LOC (Logic Optimizing Compiler), LPS (Logic Programming Software), and Macro
Librarian.
For detailed information on iPLS II, refer to the
iPLDS II Data Sheet, order number: 290134.

ORDERING INFORMATION
tpD
(ns)

tEO
(ns)

f max
(MHz)

*7.S

S

133.3

10

1S

6

10

100

66.S

Order Code

Package

Operating Range
Commercial

N8SCS08-7

PLCC

D8SCS08-7

CERDIP

P8SCS08-7

PDIP

N8SCS08-10

PLCC

D8SCS08-10

CERDIP

P8SCS08-10

PDIP

N8SCS08-1S

PLCC

D8SCS08-1S

CERDIP

P8SCS08-1S

PDIP

'NOTE:
Under development.

3-41

Commercial

Commercial

inter

85C508

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vec)(1) .......... -2.0V to + 7.0V
Programming Supply
.
Voltage (Vpp)(1) .............. - 2.0V to + 13.5V
D.C. Input Voltage (VI)(1, 2) ... -0.5V to Vee + 0.5V
Storage Temperature (Tstg) ..... - 65"C to + 150·C

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Ambient Temperature (Tam!})(3) ... -1 O·C to + 85·C

NOTES:
1. Voltages with respect to GND.
2. Minimum D.C. input is -0.5V. During transitions,
the inputs may undershoot to - 2.0V or overshoot
to 7.0V for periods of less than 20 ns under no load
conditions.
3. Under bias. Extended Temperature versions are
also available.

NOTICE Specifications contained within the
following tables are subject to change.

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee

Min

Max

Units

4.75

5.25

V
V

Parameter
Supply Voltage

VIN

Input Voltage

0

Vee

Vo

Output Voltage

0

Vee

V

+70

·C

TA

Operating Temperature

tR

Input Rise Time

500

tF

Input Fall Time

SOO

D.C. CHARACTERISTICS
Symbol

0

ns

,

ns

(TA = O·Cto +70·C, Vee = 5.0V ±5%)

Parameter

Conditions

Min

Typ

Max

Units

VIH(4)

High Level Input Voltage

2.0

Vee + 0.3

V

VIL(4)

Low Level Input Voltage

-0.3

0.8

V

VOH

High Level Output Voltage

10

VOL

Low Level Output Voltage

10

II

Input Leakage Current

Vee
Vee

loz

Output Leakage Current

ISC<5)

Output Short Circuit Current

lee

Power Supply Current

=
=

-4.0 mA D.C., Vee

=

=

min

V

max., GND

±10

JJ-A

max., GND

±10

JJ-A

-90

mA

min

< VIN < Vee
< VOUT < Vee
Vee
max., VOUT = 0.5V
Vee
max., VIN = Vee or GND,
No Load, fiN = 50 MHz, Device

=
=
=
=

V

2.4
0.45

4.0 mA D.C., Vee

-30

mA
30

Prog. as 16-Bit Address Decoder
NOTES:
4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. Do not
attempt to test these values without suitable equipment.
5. Not more than 1 output should be tested at a time. Duration of that test 'should not exceed 1 second.

3-42

intJ

85C508

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

3.0~20.

....----5V

°

INPUT

DEVICE
OUTPUT

[>--+--1>----[::> SYSTEM
TO TEST

.

TA

=

O°Cto +70°C;Vcc

A.C. Testing: Inputs are driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times are less than 3 ns.

=

5.0V ± 5%
Min

Typ

Max

Units

1.0 MHz

6

10

pF

=
=

6

10

pF

6

10

pF

20

40

pF

Conditions

=

CIN

'Input Capacitance

VIN

COUT

Output Capacitance

VOUT

OV, f

=
=

=

OV, f

CClK

ALE Capacitance

VOUT

CvPp

Vpp Pin Capacitance

Vpp on Pin 1

A.C. CHARACTERISTICS

0.8

290175-5

Parameter

Symbol

< ~20.

TEST POINTS

1~-TEST POINTS-~

OUTPUT

290175-4

Symbol

>

(INCLUDES JIG
CAPACITANCE)

341.11

CAPACITANCE

_0.8

OV, f

1.0 MHz
1.0 MHz

TA = O°C to + 70c C, Vcc = 5.0V ± 5%
*S5C50S-7

Parameter
Min

Typ

S5C50S-10

Max

Min

S5C50S-15

Typ

Max

Min

Typ

Max

Units

tpD

Propagation Delay
(Flow-Through Mode)

7.5

8

10

13

15

ns

f max

Maximum Frequency
(1/tcw)

133.3

112

100

90

82.5

MHz

tEO

Output Valid from ALE

5

6

8

10

tsu

Input Setup Time to ALE

i

5

.J..

7

.J..

5

10

8

ns
ns

-3

-3

ns

5

7.5

ns

ALE Low Time

5

7.5

ns

ALE Clock Width

10

15

ns

tH

Input Hold from ALE

tCH

ALE High Time

tCl
tcw

"NOTE:
Under development.

3-43

85C508

FLOW-THROUGH MODE
H~~~~~~~~~~~~

ALE L

LATCHES ARE IN rLOW-THROUGH MODE
WHEN ALE IS HELD HIGH

INPUT

OUTPUT

290175-6

LATCH MODE

ALE _ _ _"I

VALID

INPUT

INPUT

OUTPUT _ _ _ _ _",,,..;;;;;.;;.;;.;,.,, '-_ _ _ _ _ _"

290175-7

3-44

5CBIC
PROGRAMMABLE BUS
INTERFACE CONTROLLER
•

Higher Integration Alternative to
Transceivers, Latches, Multiplexers and
PAL * Functions

•

Applications Include Dual Port Control,
Multiplexed Bus Interface, DRAM
Control and Similar Functions

•

Port-Oriented Bus Management Unit
Supports:
- 3-Way Asynchronous Data Transfer
on Byte-Wide Buses
- Programmable Option of Latched or
Real Time Data
- True or Complement Data Path

•

- On-Chip Controls for the Bus
Management Unit
- Up to Eight Buried Registers
- Programmable Registers can be
Configured as Positive EdgeTriggered D-, J-K, R-S or T- Types
- Asynchronous Preset and Clear on
All Registers
- Option of Latched Inputs

Macrocell-Based Programmable Logic
Unit Provides:
- Variable Input and Output
Architecture

•

Low Power: 75 !-LA Typical Standby

•

CHMOS EPROM Technology Based:
- Max Bus Port Drive Capability: 16 mA
- Typical Data Transfer Delay Between
Ports = 45 ns

•

Available in 44-Lead Package
(See Packaging Spec., Order # 231369)

The Intel 5CBIC is useful in implementing bus interfacing logic functions that have traditionally been done
using SSIIMSI TTL components. Core bus functions are provided that can be customized using EPROM bits
for specific applications. Control logic can also be implemented through a sum of products architecture that is
included in this 44-lead package. Such levels of integration are realized utilizing the benefits of Intel's advanced CHMOSII-E process.
This general purpose architecture is supported by iPLDS II, Intel's Programmable Logic Development System,
to develop the design and program the devices. Several methods of entry facilitate the design resulting in
shorter completion times.
'PAL is a trademark of Monolithic Memories, Inc.

87
PORT A

JL--l\
\r---oI

A7
BUS MANAGEMENT
UNIT

A6
AS
IN4

vee
IN3

A4

44 PAD
0.650" x 0.650"
TOP VIEW

Vee
A3
A2

103

INPUTS

c==:=I

102

LOGIC

JL--l\ INPUTS/
\r---oI OUTPUTS

IN2

AO

INt

B6

290126-1

Figure 1. Block Diagram
290126-2

Figure 2. Lead Configuration

3-45

Augusl1988
Order Number: 290126·004

inter

SCBIC
trol is illustrated in Figure 5. The Bus Management
Unit (BMU) and the Programmable Logic Unit (PLU)
interface to the feedback and the control busses.
The macrocells in the PLU feed the input bus.

FUNCTIONAL DESCRIPTION
As the name suggests, this programmable bus interface controller offers a high integration solution to
design problems involving data transfer on bus lines
and the logic needed to control these transfers. This
integration directly translates into savings in board
space and lower system cost for equivalent functions implemented using conventional SSIIMSI
components.

Bus Management Unit (BMU)
The Bus Management Unit (BMU) comprises three.
ports: PA, PB and PC (Figure 4a). Each of these
ports is bidirectional and 8 bits wide. Data can be
routed from any port to any other port.

Present in the port-oriented 5CBIC are two functional blocks that enable complex bus functions to be
realized: the Bus Management Unit (BMU) and the
Programmable Logic Unit (PLU). These two units
communicate with each other through the input and
the feedback buses. A control section showl) in Figure 3 steers signals from the PLU to the two units
through the control bus.

Data into any port can be user-selected to be
latched by a port Latch Enable signal, (LE). Routing'
of latChed or unlatched data between ports is
achieved using a combination of EPROM architecture and dynamic control signals defined by the user.
Data out of any port can be programmed to have an
inverted sense through EPROM architecture control
(INV).

ARCHITECTURE DESCRIPTION

Each bidirectional port can be dynamically configured as an input or an output depending on the control signals OEA, OEB and OEC. Latched data from

The innovative architecture of the 5CBIC incorporating a port-oriented approach for bus interface con-

f2

P

1

.+-

PORT A

1+--+ PORTC

H+

INPUT
PORT

I

PORT
CONTROL

FEEDBACK

I

OUTPUT
PORT

~

BUS MANAGEMENT
UNIT

,

,~ f---+ PORT B

....

....

'f

/
00

CONTROL

1 'f

or

~
0
0
0

fl
0

~

4

PROGRAMMABLE LOGIC UNIT

't...l..
INO ~
INPUT
MACROCELL

r.

r.
ARRAY

1/07

0

1/01
1/00

INPUT/OUTPUT
LOGIC
MACROCELL

~
0

....

0

290126-3
In the tridirectional BMU, any port can be steered to any other port. In this diagram. Port A can be directed to Port B or Port C or both. The PLU
provides a 600-gate equivalent PAL function.
,
'

Figure 3. Functional Blocks in the SCBle
3-46

inter

SCBIC

FROM PORT C

H.o04HI-+-7-'-----

PORT B
(OUTPUT PORT)

TFB2

FROM
CONTROL
BUS

TO
FEEDBACK
BUS

SELC
ELA
SELB

OEA

Each bidirectional port can be dynamically configured as an input or an output dependIng on the control signals OEA, OEB and DEC. The feedback to the array IS controlled
by TFB1, TFB2 and port routing occurs through SELA, SELB and SELC. In the diagram, Port A IS the input port with possible outputs at Port B and Port C.
290126-5

Figure 4a. Bus Management Unit Block Diagram

PORT A

PORT B

PORT C

290126-23

TO FEEDBACK BUS

LEGEND:
OEA, OEB. OEC, SELA, SELB, SELC, LEA, LEB, LEC. TFB1 and TFB2 are the control outputs for the BMU derived from
the control bus.
MPCA, MPCB and MPCC are dynamic multiplexers controlled by SELA, SELB and SELC for port selection.
MUXA, MUXB. INVA, INVB and INVC are static multiplexers controlled by architecture bits (EPROM bits).
All latches are the "transparent" type.

Figure 4b. BMU Logic Diagram

any incoming port can be fed internally to the array
through TFS1 and TFS2. The three ports can be
time-multiplexed, if needed. Port routing is controlled
by signals SELA, SELS and SELC (Figure 4b)_

Programmable Logic Unit (PLU)
An on-chip 600-gate-equivalent EPLD supplies the
control signals to the bus unit and related applica3-47

SCBIC

80 81 92 83 84 95 86 B7

BIAU

CONTROL
BUS

lOGIC
(PORT B)

SElB
LE

0
AD
Al
A2
BUS

A3

lOGIC
(PORT A)

A.
A5
A6
A7

SELC
LEe
DEC
BUS
LOGIC
(PORT C)

CO C1 C2 C3 C4 C5 C6 C7

290126-4
INMC
IOMC
p-term

~

Input Macro Cell
Input/Output Macro Cell
~ Product Terms through the logic array
~

Figure 5. The 5CBIC Architecture

3-48

intJ
100

SCBIC

101

102

103

104

105

106

107

Vee
GNO

INO

INI

IN2

lN3

lN4

lN5

IN6

lN7

290126-21

3-49

intJ

5CBIC

EPROM
CONTROL
BIT

II

PROGRAMMABLE AND ARRAY

\

PRODUCT
TERMS

,

~

I.

I>

I.

~

4~

l ~

4~

l ~

4~

c~

l ~l ~

c~
I>

J.

I>

~ I>

INPUT AND FEEDBACK BUSES
290126-6

Figure 6. The Array Structure

tion functions in the system. A dedicated input port
and a bidirectional 1/0 port, each 8 bits wide, allows
control logic implementation in the 5CBIC. The macrocell based architecture enables the designer to
use up to 24 inputs and 8 outputs.
.

be implemented by selecting the architecture bit
MARB1 and the edge-triggered flip-flop (Figure 7).
The Macrocells support D, T, S-R or J-K type registers for optimal design. Truth tables for these are
listed in Figure 8 for easy reference. Whereas all
eight of the product terms are OR-ed together at the
register input for the D- and the T- registers, the J-K
and the S-R configurations employ sharing of the
product terms among two OR-gates.

The inputs, array and 1/0 marcrocells generate a
sum-of-products (AND-OR) representation of any
given logic. Within the AND array, there is an
EPROM connection at every intersection of an incoming signal (true and complement) and a product
term to a given macrocell (Figure 6). Before programming an erased device an EPROM connection
exists at every intersection. It is during the programming process that these connections are opened to
generate the required connections.

The registers receive inputs at its data, clock, set
and reset lines. Eight product terms are available for
the data input and one each for the set and the clear
inp.uts.
The clock, output enable and the latching signals
can be selected by architecture bits MARB2, 6 and 3
respectively to be outputs from the control bus or
one product term from the array. Designers thus
have more options available for asynchronous
clocking and output controls.

The bidirectional 1/0 port, when configured as an
input, is identical to the input port in that inputs may
be latched by a signal from the control bus as shown
in Figure 7. An additional flow-through option for the
data inputs is available in the input macrocell.

The macrocell output can be fed back to the array
through the feedback bus or to the control bus. Figure 9 summarizes the bus structure and its relationship to the relevant units in the 5CBIC.

The variable output architecture in the PLU allows
the designer to select the combinatorial or registered output types on a macrocell basis. This may

3-50

intJ

SCBIC

II>

:>
OJ

LATCH
INPUT PIN

>-....<:>1/0 PIN

TO ALL I/o WAC ROC ELLS

290126-7

Figure 7. The Programmable Logic Unit

Input and Input/Output Logic Macrocell

LATCH
INPUT PIN

>-.....-<:::>1/0 PIN
z

!..
en

~====~----~~~
TO ALL I/O WACROCELLS
290126-8

Figure 8a. Combinational

3-51

inter

5CBle

Input and Input/Output Logic Macrocell

LATCH
INPUT PIN

~
~
~

~
~'"

~

i

I/O PIN

TO ALL I/O MACROCELLS

290126-9

Function Table
OnH

o
o
1
1

o

o

1

o

1

1
1

o

Figure 8b. D-Type Flip-Flop

Input and Input/Output Logic Macrocell

LATCH

.-..,-.-~~I/O PIN

TO ALL I/O MACROCELLS

290126-10

Function Table
T

o
o
1
1

Onl1

o
1
o
1

o
1
1

o
Figure 8c. Toggle Flip-Flop

3·52

intJ

SCBIC

Input and Input/Output Logic Macrocell

INPUT PIN

>-1-4-<::>1/0 PIN

290126-11

Function Table
J

K

Qn

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

+1

Qn

0
1
0
0
1
1
1
0

Figure 8d. J-K Flip-Flop
Input and Input/Output Logic Macrocell

INPUT PIN

>-1-4-<::>1/0 PIN

TO ALL

va lAACROCELLS

Function Table

s

R

o
o
o

o
o

1
1

o
o

o

1
1

Qn

o

+1

o
1
o
o

1

o
1
o

1
1

1
Illegal

Figure 8e. S-R Flip-Flop
3-53

290126-12

SCBIC

INPUT BUS

FEEDBACK BUS

FROM INPUT
MACROCELL~

FROMI/O~
MACRO CELL

r----.-1.!L... ~~~T~~LS
t7-..--.1
TO I/o
MACROCELlS CONTROL

Vee

'--_.....J---'--"

CONTROL BUS

~~~~6~~LL CONTROL
290126-13

Figure 9. The 5CBIC Bus Organization
Table 2. BMU Primitive

Configuring the SCBIC
The Device Configuration Manager (DCM) in
iPLS II provides a high-level graphic design entry alternative that allows bus configurations to be implemented in minutes. A more detailed explanation is
given in the iPLS II manual. An ADF (Advanced Design File) is then automatically generated that defines the logic network using primitives.
The primitive necessary for configuring inter-port
communication is the "BMU", while the one required
for internal feedback from the BMU to the PLU is the
feedback primitive "BFMUX". Tables 1 through 4
define these primitives and their fields/bits.

Latched or Flow-Through
Port Data

INVA, INVB, INVC

True or Inverted Data Output

Ports

PA
PB
PC

BMU (Bus Management (Unit)
Name:
ADF Syntax: PortA, PortB, PortC = BMU (Type,
OeA, SeIA, LeA, OeB, SeIB, LeB,
OeC, SeIC, LeC)
Description: Port A = connection to 8 parallel I/O
pins labeled AO-A7
Port B = connection to 8 parallel I/O
pins labeled BO-B7
Port C = connection to 8 parallel I/O
pins labeled CO-C7
OeA = output enable for Port A
SeIA= select B or C internal connection to Port A (0 = C,
1 = 8)

Selects

MUXA, MUXB

I/O

BMU

Table 1. BMU Architecture Bits
Architecture
Bit

8 bit

OeA
SelA
LeA
OeB
SelB
LeB
OeC
SelC
Lec

LeA = input latch enable for Port A
OeB = output enable for Port B
SeIB= select A or C internal connection to Port B (0 = C,
1 = A)

LeB = input latch enable for Port B
OeC = output enable for Port C
SeIC= select A or B internal connection to Port C (0 = A,
1 = B)

LeC = input latch enable for Port C

3-54

inter

5CBIC

Inversion Control

A

Port:

Input Latch

B

C

B

A

C

Bit:

5

4

3

2

1

0

0

Invert Output

Invert Output

Invert Output

Latched A

Latched B

Latched C

No Invert

No Invert

Direct A

Direct B

Latched C'

1
'If LeC

No Invert
IS

continually high, the C latch

IS

transparent.

Table 3. Bus Feedback Multipler Primitive

Table 4. PLU Architecture Bits

BFMX

TFB1
TFB2

0
0

0
1

1
0

C

B

A

Architecture
Bit

Fbk
[0:7]

MARBO
MARB1
MARB2
MARB3
MARB4

Name:
BFMX (Bus Feedback Multiplexer
ADF Syntax: Fbk[0:7] = BFMX (TFB1, TFB2)
Description:

Outputs,
Fbk

=

MARB5
MARB6

8 parallel lines of feedback to
logic array,

Inputs:
TFB 1, TFB2 = By appling 0 or 1 as
shown on the chart above, select
feedback from Port A, B, or C, TFB1
and TFB2 can be set to VCC or GND,
or they can be connected to any internal feedback or input node, The ports
are defined in the BMU primitive section,

3-55

Selects

Output Polarity
Combinatorial or Registered Outputs
Clock Source
Latching Signal Source
Combinatorial or Registered
Feedback to the Logic Array
Input Source to the Control Bus
tri-state Control Signal

5CBIC

ABSOLUTE MAXIMUM RATINGS*
Min

Max

Units

Vee

Supply Voltage(1)

-2.0

7.0

V

Vpp

Programming
Supply Voltage(1)

-2.0

13.5

V

VI

DC Input Voltage(1)(2)

-0.5 Vee+ O.5

V

t~tg

Storage Temperature

-65

+150

·C

tamb

Ambient Temperature(3) -10

+85

·C

Symbol

Parameter

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTES:

1. Voltages with respect to ground.
2. Minimum DC input is -0.511. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns
under no load conditions.
3. Under bias. Extended temperature versions are also
available.

D.C. CHARACTERISTICS
Parameter

T A= O·C to + 70·C, Vce = 5.0V

Description

Min

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

Max

± 5%

Unit

Test Conditions

V

TIL:IOH

PortA
-1 mA

I, I/O
Port S, C
-1 mA
-5mA
VCC = Min

0.45

V

10L

PortA
5mA

Port S, C
16mA
Vec = Min

VIH

Input High Level

2.0

Vec +0.3

V

VIL

Input Low Level

-0.3

0.8

V
p.A

< Vce, Vee

I, I/O
5mA

II

Input Leakage Current

10
10

p.A

Vss ::;; VOUT s Vee, Vee = Max

80
16

mA
mA

VCC = Max, VOUT = 0.5

VSS ::;; VIN

= Max

loz

Output Leakage Current

IOS(4)

Output Short Circuit Current

Iss(5)

Operating Current
(standby, low power mode)

75

p.A

VIN = Vee or Gnd,
10 = 0

lec2

Operating Current
(active, low power mode)

20

mA

VIN = Vce or Gnd,
f = 1 MHz, No Load

lec3

Operating Current
(active, turbo mode)

108

mA

VIN = Vcc or Gnd,
f = 1 MHz, No Load

CIN

Input Pin Capacitance

30

pF

COUT

Output Pin Capacitance

40

pF

SMU
PLU

NOTES:

4. Output shorted for no more than 1 sec. and only one output shorted at a time.
5. Chip automatically goes into standby mode if logic transitions do not occur at input pins. (Approximately 100 ns after last
transition).

3-56

inter

SCBIC

92n

325n

PORT A,I/O ~ 2.075V
OUTPUT _ ..L __ ~ ..
Cl.I. 50pF

PORTB,C~1.93V
OUTPUT . ..L ... ~ ..
C l I . 50pF

290126-14

NOTES:
CL includes jig capacitance
Device input rise and fall times

290126-15

< 6 ns
Figure 10. A.C. Testing Load Circuit

INPUT

1~- T E S T POINTS---)E

OUTPUT

290126-16
A.C. Testing' Inputs are driven at 3.0V for a Logic "1" and OV for a Logic "0". Timing
measurements are made at 2.0V for a Logic "1" and O.BV for a Logic "0" on inputs.
Outputs are measured at a 1.5V point.

Figure 11. A.C. Testing Input, Output Waveform

SWitching Characteristics
Timing
Suffix

Notation:

Referenced to
Control From:

direct Input pin

1
2
3

product term

control bus

PORT
INPUTS

VALID

I--:

LlSU, _ ~:LlHO'_
TUH03

TUSU3

LATCH
ENABLE

--'
i---TlEH

OUTPUT
ENABLE

-

'l

TauSPD

)-

;PXZ;~
PXZ3

I---

TpZX1

TpZX3

PORT
OUTPUTS

_ T lEPD' _
TlEPD3

290126-17

A) Latched Port Inputs

,----------

PORT -------",----""'''\.
INPUTS _ _ _ _ _ _ _ _JI,--V-A-Ll-D--J ' -_ _ _ _ _ _ _ _ __

OUTPUT
ENABLE

---------+----"1
TpZX1

TpZX3

"1
----------~I(==)~--{=======

OUTPUTS
PORT _ _ _ _ _ _ _ _ _ _ _

B) Direct Port Inputs
Figure 12. Bus Management Unit

3-57

290126-22

inter

SCBIC

Switching Characteristics
INPUTS OR
I/O INPUTS

(Continued)

If

VALID

I-- :LISU2 _____ 1+-:LIH02_
TUSU3

TUH03

LATCH
ENABLE

1\

)

I---TCISU2
TCISU3

TCLEH. -

CLOCK

OUTPUT
ENABLE

If
_ :PXZ2-..
TpXZ3

- TCPO -

I---

TpZX2
TpZX3

COMBINATORIAL
OUTPUT

~:RP02 .....
TRP03

r--

REGISTERED
OUTPUT

110290126-18

A) Latched Inputs

.,-------------

INPUTS OR ------~.I.,-------'"'
VALID
I/O INPUTS OR
REGISTERED FEEDBACK - - - - - - - " , , - - - - - - - - ' - - - - - - - - - - - - - -

CLOCK

-----i-t---TcwH ----4==r:;:;-:::::r

OUTPUT
ENABLE
PXZ2_
TpXZ3

I--Tcpo COMBINATORIAL
OUTPUT

PZX2_
TpZX3

.~

TRPO~-L--

TRP03
REGISTERED
OUTPUT
TSpW
SET, RESET
INPUT
TSPO

-----------~-PO-3·

ASYNCHRONOUSLY
SET, RESET
OUTPUT - - - - - - - - - - -

.-------------------------------290126-19

8) Direct Inputs.
Figure 13. Programmable Logic Unit

3-58

inter

SCBIC

AC CHARACTERISTICS
BUS MANAGEMENT UNIT
Symbol

-45

Parameter

Typ

Min

Max

Units
Max

TUSU1

Port Input Setup Time to
Latch Enable (Fast Option)

0

ns

TUSU3

Port Input Setup Time to
Latch Enable (Control Bus)

0

ns

TUH01

Port Input Hold Time to
Latch Enable (Fast Option)

55

ns

TUH03

Port Input Hold Time to
Latch Enable (Control Bus)

95

ns

hEH

Latch Enable High Time

45

ns

TSUSPD

Port to Port Propagation Delay

45

ns

TpXZ1

Valid Output to High Impedance
(OE From Fast Option)

45

ns

TpXZ3

Valid Output to High Impedance
(OE From Control Bus)

95

ns

TpZX1

High Impedance to Valid Output
(OE From Fast Option)

45

ns

TpZX3

High Impedance to Valid Output
(OE From Control Bus)

95

ns

TLEPD1

Latch Enable (From Fast Option)
To Port Output Delay

65

ns

TLEPD3

Latch Enable (From Control Bus)
To Port Output Delay

95

ns

PROGRAMMABLE LOGIC UNIT
Symbol

-45

Parameter
Min

Typ

Units
Max

TUSU2

Input Setup Time to Latch Enable
(P-Term)

0

ns

T LlSU3

Input Setup Time to Latch Enable
(Control Bus)

0,

ns

TUH02

Input Hold Time to Latch Enable
(P-Term)

80

ns

TUH03

Input Hold Time to Latch Enable
(Control Bus)

90

ns

TCISU2

Input Setup Time to Clock (P-Term)

20

ns

TCISU3

Input Setup Time to Clock (Control Bus)

60

ns

TCLEH

Clock to Latch Enable Hold Time

5

ns

TCPD

Combinatorial Output Delay

135

3-59

ns

intJ

SCBIC

PROGRAMMABLE LOGIC UNIT (Continued)
Symbol

-45

Parameter
Min

TRP02(6)

Typ

Registered Output from Clock (P-Term)

Units
Max

115
70

ns

TRP03(7)

Registered Output from Clock (Control Bus)

TIH02

Input Hold Time to Clock (P-Term)

25

ns

ns

TIH03

Input Hold Time to Clock
(Control Bus)

90

ns

TCWH

Minimum Clock Width High

43

ns

TCWL

Minimum Clock Width Low

43

ns

Tspo

Set Output Delay

100

ns

TRPO

Reset Output Delay

100

ns

Tspw

SETIRESET Pulse Width

TpXZ2

Valid Output to High-Impedance
(OE from P-Term)

85

ns

TpXZ3

Valid Output to High Impedance
(OE from Control Bus)

95

ns

TpZX2

High Impedance to Valid Output
(OE from P-Term)

95

ns

TpZX3

High Impedance to Valid Output
(OE from Control Bus)

95

ns

TCP1

Minimum Clock Period (Register Output
to Register Input Through Feedback Path)

110

ns

F1

Maximum Internal Frequency

TCP2

Minimum Clock Period Between
Logic Transitions (Inputs to Outputs)

F2

Maximum External Frequency

43

ns

9.0

MHz
135

7.0

ns
MHz

NOTES:
6. Data out on rising edge of clock.
7. Data out on falling edge of clock.

inteligent Programming AlgorithmTM

FUNCTIONAL TESTING

The 5CBIC supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each bit is continually monitored to determine when the bit has
been successfully programmed.

Since the logical operation of the 5CBIC is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal. logic is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of the EPROM array are
required.
The testability and reliability of EPROM-based programmable logic devices is an important feature

3-60

inter

5CBIC

optimize a design to benefit from architectual features). It contains comprehensive third generation
software that supports several different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.

over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming.

DESIGN SECURITY
A single EPROM bit provides a programmable design security feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
code output files which can be downloaded to other
programmers as well.
The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. One low-cost schematic entry
method is provided by SCHEMA II-PLD, which supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD DeSign
Manager, which provides a single user interface to
both SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation
entry and State Machine design entry.

TURBO-BIT
The device will consume quiescent current (75 /LA,
typically) if no transitions are detected in the array
for 100 ns or more. This mode, the power-down
mode, can be enabled by selecting the Turbo Bit
OFF. If this bit is enabled, however, the device consumes active current. The power-down mode will revert to its active state if a transition is detected in the
array, at an extra delay of 25 ns in speed paths.

The iPLDS II operates on the IBMt PC.XT, PC/AT,
or other compatible machine with the following configuration:
1. At least one floppy disk drive and hard disk drive.
2. MS-DOStt Operation System Version 3.0 or
greater.
3. 512K Memory. -

LATCH-UP IMMUNITY
All pins of the 5CBIC have been designed to resist
latch-up which is inherent in inferior CMOS structures. The 5CBIC designed with Intel's proprietary
CHMOS II-E EPROM process. Thus, pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -1V to Vee +1V. Furthermore, the programming pin is designed to resist
latch-up to the 13.5V maximum device limit.

4. Intel iUP-PC Universal Programmer-Personal
Computer
5. A GUPI LOGIC Adaptor
6. A color monitor is suggested.
Detailed information on the Intel Programmable Logic Developement System is contained in a separate
Intel data sheet.
tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM (iPLDS II)
iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will

3-61

intJ

APPLICATION
NOTE

June 1988

Implementing a PS/2 P~S
Using the 5AC312 EPLD

PEDRO VARGAS
PROGRAMMABLE LOGIC APPLICATIONS

Order Number: 292047-001
3-62

intJ

AP-317

INTRODUCTION

POS REQUIREMENTS

The introduction of the IBM· PS/2 (personal
System/2·) models and the innovative Micro Channel"
has provided numerous opportunities to develop creative interface solutions. Although the interface requirements are new, the designer is faced with making a
familiar choice: Use discrete chips (SSIIMSI), incorporate a PLD, or go for the custom IC solution.

Each adapter must implement POS with eight registers.
Depending on the adapter function, not all of them
need to be used. The first three (pOS registers 0,1,2) are
required because they provide the adapter 10 and the
adapter enable/disable function necessary during setup
and error checking. In brief, the way that the system
uses POS is as follows:
1. The system selects the adapter to be placed in setup
mode by driving its -CD SETUP signal active.
2. The adapter is identified by reading two 10 bytes
from POS 0 and POS I (HEX 100 and 101).
3. The adapter is disabled by writing "0" to POS 2
(HEX 102).
4. If implemented, Option Select Data is written to
POS 3, 4,5.
5. The adapter is enabled by writing "I" to POS 2.
6. The adapter is out of setup mode when the system
drives the -CD SETUP signal inactive.

In the past, using .TTL on the PC/XT/ AT bus was
often a good choice, but the reduced size of the PS/2
adapters ("plug in boards") increases the cost of board
space dramatically. The custom chip solution is probably the best for companies that have a well-defined
product, large volumes, and can afford the cost of the
chip development. The third choice, using a PLD, is
one that has not been popular in PC bus interfacing due
to the limited function and performance of most PLDs.
The Intel 5AC312 is a third-generation EPLD that
gives designers the resources needed to interface to buses like the Micro Channel. In addition, it provides two
benefits not completely provided by either of the other
two choices; high integration, and re-programmability.
The rest of this application note contains a detailed presentation of a basic POS (programmable Option Select)
implementation for the PS/2 Micro Channel that is
done with the 5AC312 EPLD.

PS/2 MICRO CHANNEL
One of the best features in the PS/2 models is the capability to do system and adapter configuration with software instead of hardware. This feature, called POS
(Programmable Option Select), eliminates the need for
switches on the motherboard and adapters by replacing
them with programmable registers. The idea is, rather
than removing boards and manually setting switches,
all configuration information is located in files and can
be read or written to the motherboard or to the adapters through the Micro Channel. The motherboard and
each connector on the Micro Channel has a unique signal called -CD SETUP that initiates a setup mode when
it is active. Only one connector at a time can be in the
setup mode, which provides an organized way to perform initialization.

The actual hardware implementation of POS is summarized in IBM technical documents, but the details are
left up to each designer.

ADAPTER REQUIREMENTS
The adapter used for this design is an Intel single-function card that incorporates two modems controlled by a
8OC186. Since it performs only one function, there was
no need to implement the POS Option Select bytes.
(These POS bytes are used with multi- function adapters that do more than one task and reside in the system
with similar adapters.) In this case, the only requirements were to provide the 10 bytes and the enable/dis. able features, which are done with POS registers 0,1,
and 2. Figure I shows the POS register layout and the
typical POS hardware implementation as suggested by
IBM. Table 1 defines the POS registers.

'IBM, Personal System/2 and Micro Channel are trademarks of International Business Machines Corporation.

3-63

intJ

AP·317

LOCAL
ADAPTER
CONTROL

I
~

lOR
A02
-CDSETUP

t::
't::
'-

~

I
I

ADO

Data

Registers

Gate

---.
---.
---.
---.
---.
---.
~

'--

I

3
2
10-

AD1

pos

'-

~

Data

POS
Registers

Gate

""-

~

~

Decode

~

---.
---.

""-

~

""-

000-007

-

2

10
Drivers

~

3

I-'"

Decode
-COSEllJP
AD2

lOW

I
I

~

f---'

MSBYTE

~

~

I
10
Drivers

~

I-'"

~

I-'"
LSBYTE

~

292047-1

Figure 1. Typical Adaptor Implementation of POS
Table 1. POS 1/0 Address Decode
Address
(hex)

Register

0100

POS Register 0

0101

POS Register 1

0102
0103

-CD
SETUP

Address Bit

Function

A2

A1

AO

0

0

0

0

Adapter Identification Byte (Least Significant By1e)

0

0

0

1

Adapter Identification By1e (Most Significant By1e)

POS Register 2

0

0

1

0

Option Select Data (By1e 1)'

POS Register 3

0

0

1

1

Option Select Data (By1e 2)

0104

POS Register 4

0

1

0

0

Option Select Data (By1e 3)

0105

POS Register 5

0

1

0

1

Option Select Data (By1e 4)'

0106

POS Register 6

0

1

1

0

Subaddress Extension (Least Significant By1e)

0107

POS Register 7

0

1

1

1

Subaddress Extension (Most Significant By1e)

..

'These bytes contain one or more bits with specific value assignments

3·64

inter

AP-317

RING 1
I

LOGIC ARRAY

1/0.1

I
I
I

I
I

r------

CLK/INP1 C>------~

1/0.2

I
I
I

I
IL _____ _

LlNP1

I
I

1/0.3

-,
I

I

I

r------

LlNP2

1/0.4

I

•I
I
Il

LlNP3

_____ _

1/0.5

I
I
I
I
I
I

1/0.6

LlNP4

LlNP5

1/0.7

I
I
I
I
I

r-----I

LlNP6

1/0.8

I
I

I
I
IL _____ _

LlNP7

I
I
I

1/0.9

-,
I
I

,------

LlNP8

1/0.10

I

I
I
I

ILE/ICLK/INP2

Il

C>--------I

_____ _

I

1/0.11

I
I
I

I
I

1/0.12
RING 2

Figure 2. 5AC312 Architecture

5AC312 EPLD

DEVICE DESCRIPTION

With 12 macrocells and a host of other features, the
5AC312 is Intel's newest EPLD. The device is based on
the same CHMOS process used in other Intel devices.
This EPLD provides an abundant feature set, but its
strength lies in being able to efficiently implement one
very important function missing from most PLDs: register-logic-register functions.

The 5AC3l2 (Figure 2) contains 12 macrocells with
programmable outputs and inputs. A macrocell is the
basic block associated with each output register within
the EPLD. The 5AC3l2 has the following features:
• 12 I/O macrocells with dual feedback for implementing buried registers.

3-65

AP-317

terms per macrocell (Figure 4). Product Term Allocation takes place in two rings of six macrocells.
Within each ring (Figure 2), individual macrocells
can allocate p-terms to/from adjacent macrocells.
This is a real benefit in bus decoding where intermediate signals can have few or many p-terms all within
the same logic function. Most designers that use
PLDs have at least one horror story of a design that
required 10 or more p-terms and a device that could
only provide 8.
3. A flexible output structure is a must for efficient bus
interfacing, which quite commonly requires lots of 1/
and complex control signals. The 5AC312 meets
these demands head-on with dual-feedback paths
and two p-terms per control signal on all I/O macrocells. This means that certain functions, like state
machines, can be buried and a pin won't be wasted
because it can be used as an additional input. Also,
output enables and register operations are frequently
generated by a combination of memory, I/O, read,
and write strobes. Many times these control signals
require two p-terms or the equivalent of an external
read/write multiplexer. Prior to the 5AC312, the
only way to implement this in PLDs was to waste a
macrocell to inefficiently provide this function. Figure 5 shows the macrocell structure and details this
third benefit.

• 8 programmable inputs that can be configured as
latches, registers, or flow through inputs. These can
be clocked synchronously or asynchronously.
• Product term allocation on each macrocell.
• 2 product terms on all macrocell control signals.
• 2 multi-function pins; a CLK/INPUT and a ILE/
ICLK/INPUT.
• 40 MHz operation.
The 5AC312 provides three major benefits that are especially important to designers working on bus interfaces:
1. The availability of input latches (Figure 3) makes it
easy to synchronize bus control signals synchronously or asynchronously. The latches can be clocked as a
group of 8 or individually, as is quite common on
most buses. Input latches also make state machine
designs more reliable. Since buses are prone to glitches and other transients, the ability to hold the inputs
stable while transitioning through states makes the
difference between a clean and a jittery state machine.
2. Product Term Allocation (Patent Pending) brings a
new concept to the Intel EPLD family and makes
the 5AC312 unique among PLDs. This feature
means that the designer can implement large designs
that contain as few as zero or as many as 16 product

INP
PIN

C>-----.. IN

°

OUT~------""

lOGIC
ARRAY

P-TERM

IlE/IClK
PIN
292047-3

NOTE:
Flow-through input selected by connecting ILE P·Term to Vee.

Figure 3. 5AC312 Input Structure

3-66

(

LOGIC ARRAY

LOWER HALF
P-TERMS 1-4

MACROCELL

#3

P-TERMS ALLOCATED TO

MACROCELL #4
(NEXT MACROCELL IN RING)

!!

cc
c

iil

UPPER HALF
P-TERMS 5-8

..

~
'V
0
Co

..
C

(')

..

-I

»

CD

t.)

-..J

"tI
I

MACROCELL
#4

a, 3

~

...
Co)

......

0'
(')
~

0

~

ex;

+
~

+
~
UPPER HALF
P-TERMS 5-8

P-TERMS ALLOCATED TO

MACROCELL #4
(PREVIOUS MACROCELL IN RING)

MACROCELL

#5

292047-4

(
LOGIC ARRAY

TO NEXT
MACROCELL

FROM NEXT
MACROCELL
OUTPUT
ENABLE

PRESET

::!!

CO
C

;

OUTPUT
MUX

!JI
(II

~

....
Co)

r.)

»
....
......

ID
(,J

III



"tI

....CO•
Co)

inter

AP-319

LOGIC ARRAY

LOWER HALF'
P-TERMS 1-4

MACROCELL

#3

p- TERMS ALLOCATED TO
MACROCELL #4
(NEXT MACROCELL IN RING)

UPPER HALF'
P-TERMS 5-8

MACROCELL

#4

UPPER HALF'

p- TERMS 5-8

P-TERMS ALLOCATED TO

MACROCELl #4
(PREVIOUS MACROCELL IN RING)

MACROCELL

#5

292049-3

Figure 3. Product Term Allocation (8

3-78

+ 4 + 4)

AP·319

NOT
CLOCK
DATA

_-+___-+_--J

REG 1 OUTPUT

r

PRESET

------+-+-------1

REG 2 OUTPUT

r

CLEAR

OUTPUT ENABLE

.....- - - - - - - - - -......, >-1::>

OUTPUT

CONr
292049-4

Figure 4. Implementation of 0 Flip-Flop with Added Preset Function Using Combinational Logic

of logic resources (p-tenns) from areas they are not
being utilized to other areas within the chip where they
are needed. As shown in Figure 3, each macrocell has
the potential to borrow 4 more p-tenns to add to the 8
it already has from each of its adjacent macrocells. This
increases the maximum number of p-terms per macrocell to 16. Thus, any macrocell within the 5AC312 has
the potential to satisfy logic functions requiring between 0 and 16 p-terms.

OEN1

> .....-t:-:;>

P-terms can be allocated in a "shift register" mode
within each of the two rings of the macrocell; however,
allocation of p-tenns between rings is not possible. See
Table 1 for a listing of adjacent macrocells within pterm allocation rings.

DATA

----I

CLOCK

----I

OUTPUT

CLEAR - - - - - '
FEEDBACK - - - - - - - - - - - '
292049-5

Figure 5. Implementation of
2 P-Term OE Control Signal

Table 1. 5AC312 Product Term Allocation Rings
Ring 1

Ring 2

Previous Current
Previous
Current
Next
Next
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell

1
2
3
4
5
6

2

8

3
4
5
6

1
2

7
8
9

3
4
5

10
11
12

1

OUTPUT ENABLE

OEN2

3-79

8
9

10
11
12
7

12
7
8
9

10
11

intJ

AP-319

A given macrocell's output structure is still available
for use when some or all of its p-terms are allocated
away, If all of the p-terms of one macrocell are allocated away to its respective adjacent macrocells, the data
input to that macrocell defaults to GND. This polarity
can be changed through programming of the invert select EPROM bit. The I/O register as well as all secondary controls to this I/O control block are still available
and can be used as needed for design purposes.

POWER ON CHARACTERISTICS
Another feature of the 5AC312 is its power-on characteristics. The lio registers of the 5AC312 experience a
reset to their inactive state upon Vcc power-up. Using
the PRESET' function available for each macrocell allows any particular register preset to be achieved after
power-up. The inputs and outputs of the 5AC312 begin
responding approximately 10 JLs (6 JLs typical) after
Vcc power-up or after a power-Ioss/power-up sequence.

DUAL FEEDBACK
The 5AC312 contains separate input and feedback
paths (dual feedback) on each of the macrocell I/O
control blocks. This allows designs to utilize input pins
when the associated macrocells have been assigned a no
output with buried feedback primitive. Multiplexed
I/O is accomplished by controlling the output buffer
associated with each macrocell using the 2 p-terms that
implement the OE function. Registered outputs may be
clocked from the synchronous CLK/INPI pin or asynchronously clocked by the 2 p-terms available for
ASYNCH_CLK.

POWER DOWN MODE
A trade-off between power consumption and speed is
possible'when using the 5AC312 by programming the
"Turbo Bit". Left unprogrammed and with no transition occurring at the device inputs for a period of
approximately 100 ns, the device powers-down the internal array while holding the outputs at their previous
levels. At the next input transition occurrence, the
5AC312 powers-up the array and reacts to the change
in input conditions. If the "Turbo Bit" is programmed,
the power-down circuitry is disabled and the device will
not power-down even if there are no more transitions.
The array power-up sequence requires an additional 20
ns of propagation delay. Power supply current during
power-down is no more than 120 JLA. See Figure 6.

FIRST
INPUT

LAST
INPUT

OUTPUT

VALID OUTPUT

VALID OUTPUT

ACTIVE MODE

CURRENT

Icc

OmA
292049-6

Figure 6. 5AC312 Standby and Active Mode Transitions

3-80

AP-319

EXAMPLE

SUMMARY

An example application for the 5AC3l2 can be shown
by replacing a PAL' 20R6 and a 374 D type flip-flop in
a design due to a power constraint. The same implementation can be achieved consuming less power using
one 5AC312 EPLD. Compare Figures 7 and 8. Straight
jumpers can be substituted in the PC board where the
374 sits, and since the clock signal is already available
on the PAL socket, it can be internally routed to clock
the input registers of the 5AC312. The 5AC312 can
then be programmed to match the existing pin assignments and therefore require no PC board re-layout. The
internal circuitry of the 5AC312 allows the EPLD to
act as both a D type flip-flop and a PAL.

The 5AC3l2 EPLD, which uses advanced CHMOS
EPROM cells as logic control elements instead of polysilicon fuses, represents an innovative device to help
overcome the primary limitations of standard PLDs.
With its advanced features, proprietary architecture
and macrocell structure, the 5AC312 is capable of implementing high performance logic functions more effectively than was previously possible. The p-term allocation scheme is a unique feature, increasing the efficiency of the device immensely. The PRESET signal
and 2 p-term control lines are also features giving the
5AC312 added efficiency in many designs.
These same architectural features have been included in
the 5AC324 EPLD, making that device ideal for even
higher integration applications. Refer to the 5AC324
Data Sheet for details on that device.

(

DATA
374 0 FLIP-FLOP
18
80
17
70
14
60
13
50
8
40
7
3D
4
20
3
10
CK
Rl

~(
(

80
70
60
50
40
30
20
10

19
16
15
12
9
6
5
2

OE

1111

20R8
23
14
11
10
9
8
7
6
5
4

~

,...2-

112
111
110
19
18
17
16
15
14
13
12
11

oun
rtk-+
~

06
05
04 19
18
03
02
16
01
22
102
15
101

~

CK

OE

1'..

11

CLOCK
SELECT

WRITE

(

RESET

13

R2

( ADDRESS

(

OUT2
. . OUT3
OUT4
OUTS
OUT6
OUT7
OUT8

-==
292049-7

Figure 7. Original Implementation Using a 374 D Flip-Flop and A PAL20R6

'PAL is a registered trademark of Monolithic Memories. Inc.

3-81

inter

AP-319

(

DATA
5AC312
23
14
11
10
9
8
7
6
5
4

-.....~

Rl

~(
(

T

--4~

112
111
110
19
18
17
16
15
14
13
12
11
CK

Q6
Q5
Q4
Q3
Q2
Ql
IQ2
IQl

11

SELECT

WRITE

(

RESET

OUT5
OUT6
OUT7
OUT8

13

R2

( ADDRESS

(

17
16
22
15

OE

"'-

CLOCK

~ oun
~ OUT2
OUT3
~
18
OUT4

-==
292049-8

Figure 8. Example Implementation Using the 5AC312

3·82

PROGRAMMABLE AND/ALLOCATABLE OR BASED EPLD
ADDRESSES THE NEEDS OF
COMPLEX COMBINATIONAL AND SEQUENTIAL DESIGNS
Todd K. Koelling
Applications Engineer
Intel Corporation
1900 Prairie City Road
Folsom, CA 95630
INTRODUCTION
Matching programmable logic applications
with programmable logic devices has become a
difficult task. Increasing demands for
higher integration, higher performance and
lower cost continue to drive system design
engineers on to new technologies. The
programmable logic industry has adeptly
responded by supplying a wide variety of
devices. At times, however, it is hard to
differentiate these devices and to determine
which makes the best solution for a
particular application.

GATE
AXIS

(GATES)

(FLlP·FLOPS)

In a small way, this paper will attempt to
differentiate devices and to determine
which devices make the best solutions for
groups of applications. This task will be
accomplished by taking a general look at
applications, the history of PLD arrays and
a new device which solves several design
problems.

Figure 1:

REGISTER
AXIS

Gate/Register Coordinates

Common TTL functions are easily graphed.
Figure 2 displays a comparator, storage
register, shift register and counter. The
comparator is a combinational circuit
(purely gates) and hence lies along the gate
axis. The storage register, on the other
hand, is purely flip-flops and hence lies
along the register axis. The shift
register is primarily flip-flops -- placing
it close to the storage register -- but it
includes some gate logic, thus moving it up
the gate axis. The counter is a good
example of a function that lies somewhere
in-between the two axes. The counter must
store its current state. and thus leans
heavily upon the registers, but it also uses
a significant amount of gate logic to
generate the next count state. The
inclination toward the gate or register
axis depends on the features the counter
incorporates. Up and down count operation,
clear and preload functions, and count
enable/disable circuitry, all move the
counter increasingly toward the gate axis.
The magnitude of the counter (as with the
other functions) depends on the number of
bits and features it includes. That is, a
16-bit counter is twice as large as an a-bit
counter which is twice as large as a 4-bit
counter. provided the feature set remains
the same.

APPLICATIONS
College textbooks 1 on digital design teach
that fundamentally there are only two types
of applications: combinational and
sequential. A combinational circuit
generates outputs based on the immediate
status of a group of inputs. A sequential
circuit uses some mechanism to store data
before generating the next set of outputs.
Inside combinational and sequential
circuits are two fundamental elements:
gates and registers. Gates are the prime
component of combinational circuits where
the output is an immediate function of the
input. Registers are the static storage
element added in sequential circuits to
latch and hold data until the next cycle.
Figure 1 displays gates and registers
graphically. The coordinates measure
registers along the x-axis and gates along
the y-axis. In this space, any
combinational or sequential application
can be displayed.
3-83

system represents a healthy mix of both
gates and registers. This means it is
probably a state machine or some sort of
sequential application. Hence, the middle
third region will be called the "state
machine" region, though some state machines
may land in the other two regions. The
coordinate system with the three regions
segmented and labelled is shown in Figure 4.

GATE
AXIS

GATE
AXIS
(FLIP· FLOPS)

Figure 2:

HOII.Y

COMBINATIONAL
REGION

REGISTER
AXIS

STATE
MACHINE
FE----,

L
SElECT

BAUD

DATA

RATE

Itf'UTS

SELECT

CIRCUITRY

'>-'---<::l BAUDOUT
: ••.1:QIf:

Figure 10:, Programmable Baud Rate Generator
Ci rcuitry
By using the input latches available on the
5Ac312, the select data inputs can be stored
immediately at the input pin rather than
inside a macrocell. This saves a macrocell,
saves a pin, and decreases the delay time.
Second, since the SAC312 has separate
register and pin feedbacks on each
macrocell, the baud rate divider can be
buried by using the register feedback paths
while the input feedback paths remain
available for use as standard inputs.
Inside the 5AC312, the circuit consumes 8 of
12 macrocells, and 7 of 24 pins, a
siginificant I/O pin savings.

Though not a state machine, the programmable
baud rate generator circuitry for the Intel
8251 Universal Synchronous/Asynchronous
Receiver/Transmitter does have a good
mixture of gates and register functions,
Qualifying it for the state machine
application region. The input baud rate
(BAUDIN) is divided down to lower baud
rates through a series of toggle flip-flops.
Then, based on the select data stored in the
02, 01, DO flip-flops, one of the
divided-down baud rates is selected and sent
.out on the baud rate out pin (BAUDOUT).
Implementing the design in a standard
24-pin PlD (exemplified here by the Intel
5C060) is very costly. The data inputs must
be latched inside a macrocell, using not
only the macrocell but also the pin. The
divide down toggle flip-flops cannot be
buried, resulting in the loss of a pin for
each flip-flop. The net utilizatioh for the
5C060 implementation is 12 of 16 macrocells
and 16 of 24 pins, virtually all of the
device.

In fact, the 1/0 pin savings is so
significant that the accompanying address
decode circuitry -- which would be
implemented typically in a 2018 or second
PlD -- can be added to the SAC312 (Figure
11). The 14 address inputs (A13 - AO),
along with the memory or 1/0 status signal
(MilO) are fed into the PlD to generate the
baud rate select data clock signal (BAUDSEl)
and the 8251 Command/Data (C/O) and Chip
Select (/CS) signals. The net result is a,
10 of 12 macrocell, 24 of 24 pin,
single-chip solution.

Implementing the same design in the Intel
5AC312 uses a much smaller amount of space.
3-89

flAW RATE DIVIDeR

SElECT

D2

BAllI

DATA

RATE
SElECT

IIfIU1S

Dl

CIRCUITRY

DO

L~,.::·=·c:.l__---,

Figure 11:

Programmable Baud Rate Generator

5AC312 Implementation

CONCLUSION

Acknowledgements

GATE
AXIS
PLA

Special thanks to David Poisner of the
Datacomm Focus Group in Folsom. CA and
J. Michael Dunlap and Robert A. Miller
Willamette University in Salem, OR for
use of their designs in this paper.

PLS
,22Y10

SAC111

Intel
Prof.
of
the

References
(GATES)

(fLIP-flOPS)

Figure 12:

1.

An Engineering Approach to Digital
Design, William 1. Fletcher, PrenticeHall Inc., 1980, pp. 276, 280, 281.
(Provided as an example).

2.

PAL is a registered trademark of
Monolithic Memories In.c.

3.

Product Term Allocation is an Intel
Patent Pending.

4.

Personal System/2 and Micro Channel
are trademarks of International
Business Machines Corp.

5.

Ethernet is a trademark of Xerox
Corp.

6.

ESPRESSO is a copyright of the
University of California at Ber.keley.

7.

IBM PC/AT is a registered trademark of
Intern.ational Business Machines Corp.

REGISTER
AXIS

5AC312 Application Areas

Based around a novel programmable
AND/allocatable OR array structure, the
Intel 5AC312 is uniquely suited to cover
both highly combinational and complex
seauential designs (Figure 12). The 5AC312
is made combinationally powerful through a 0
- 16 product term allocation arrangement and
sequentially powerful through separate
register and pin feedback and other
features. The 5AC312's latched input
capability is an asset in both
combinational and sequential applications.
The net result is a combinationally
powerful. sequentially powerful 24-pin
device.
3-90

ADVANCED ARCHITECTURE PLDs SOLVE COMMON
STATE MACHINE PROBLEMS
Liliyas S. Koumis
Technical Marketing Engineer
Intel
1900 Prairie City Road
"olsom. CA 95630

INTRODUCTION
The introduction of programmable logic
devices (PLD) was a true revolution in the
hardware design

XCiJN I RfJL

F-::'

r4
I-::J

"6
F7
1-8
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cJ~fll .... rlcl tJr:tof fI!l f,jO·t:!
fl.tt Lnq compl~=tt::!

i llt! l)Ut!=-'Ut.

SllLc:~~sS'-fuljy

c.umpletE-?d

290134-9

Logic Optimizing Compiler Main Menu

4-4

inter

IPLDS II

Device Programming

A. TTL SCHEMATIC ENTRY

The programming hardware is controlled by the
LOGIC PROGRAMMER SOFTWARE. LPS takes the
JEDEC file produced by the LOC and programs it
into the device. LPS can also read a programmed
device or verify that a device has been programmed
correctly.

SCHEMA II-PLD is an optional software package
that allows EPLD design to be implemented with
standard TIL functions. SCHEMA II-PLD contains a
symbol library that includes common SSI/MSI TIL
symbols. SCHEMA JI-PLD also outputs directly in
ADF format. The TIL symbols appear in the ADF in
the form of macro calls. During compilation, iPLS II
automatically expands these calls from its TIL macro library. Thus, with SCHEMA II-PLD, conversion to
EPLD logiC primitives is performed automatically in a
manner completely transparent to the user.

The Intel Universal Programmer for the Personal
Computer (iUP-PC) is a versatile programming solution in a PC-based system. Installed in an IBM
PC/XT, PCI AT or compatible host, the iUP-PC emulates the performance of the standalone INTEL
iUP-200A Universal Programmers. As such, it supports the iUP Generic Universal Programmer Interface (iUP-GUPI). With the appropriate socket adapters for the iUP-GUPI, the iUP-PC supports all Intel
EPLDs. Future EPLDs will be supported by new
GUPI adapters or adapter upgrades. Many other Intel devices-EPROMs, EEPROMs, and microcontrollers-are also supported by the GUPI. The iUPPC is controlled by the LPS or the iPPS (Intel PROM
Programmer Software). iPLDS II includes the iUPPC, which contains the iPPS, PCPP programming
card, interconnect cable, and the GUPI base. GUPI
adapters are available separately.

Only parts supported by the SGHEMA II-PLD TIL
symbol library and the iPLS II TIL macro definition
library may be used for TIL schematic entry. In most
cases, this won't be a limitation as the most common parts are included in both libraries. Parts not in
the macro libraries may be created by the user and
stored in proprietary user libraries. SCHEMA II-PLD
also supports creating of user-defined macro symbols. The iPLS II Macro Librarian supports creation
of iPLS II macro libraries.
B. SCHEMATIC ENTRY WITH
INTEL SYMBOL LIBRARY
If the user prefers designing with EPLD logiC primitives but still wants to use schematic entry,
SCHEMA II-PLD, in addition to supporting TIL schematic capture, also supports design using EPLD
primitive symbols. Users can enter their design and
have both a schematic drawing and an ADF version
of the design. The logic symbols are loaded from the
Intel library and connected in the usual manner. For
quicker use of EPLD primitives, a second library,
EPLDMAC.LlB is available for use. Optional symbol
libraries are also available for PC-CAPS' by P-CAD
Corporation and DASH-2, -3, -4" by FutureNet
(iSLlBPCAD, iSLlBFNET). The iSIMLIB optional library is available for simulating logic designs with PCAD's PC-LOGS logic simulator.

iPLS II SOFTWARE
The Intel Programmable Logic Software II (iPLS II)
has many options and enhancements for implementing a logic design. iPLS II accommodates a wide variety of design input methods. Schematics, state machines or Boolean equations may all be used provided the proper formats and convertors are implemented as needed. No matter what method is chosen, the Logic Optimizing Compiler will minimize and
fit the design during compilation. Finally,iPLS II contains the Logic Programmer Software which controls
the iUP-PC programming hardware for all Intel
EPLDs.

'PC-CAPS and PC-LOGS are registered trademarks of
P-CAD Corporation.

I. Design Input

"DASH-2, -3, -4 are registered trademarks of FutureNet
Corporation.

The entire spectrum of design input methods is
available to the logic designer in iPLS II. Everything
from TIL schematics to Boolean equations are accepted and processed by the LOC.

4-5

intJ

iPLDS II

C. TEXT EDITOR ENTRY

,II. Logic File Compilation

Designers who are familiar with the logic primitives
and the Advanced Design File format can directly
enter ADFs with a standard text editor. The bulk of
the design entry can be accomplished using Boolean
Equations obtained from a Karnaugh map or truth
table. Hence, the need for conversion to gates is
eliminated. This method of entry is useful for sub-circuits that will be incorporated into larger designs.

Before programming the part, the designer must
compile the input design file into a JEDEC standard
file. This f\Jnction is performed by the Logic Optimizing Compiler.
LOGIC OPTIMIZING COMPILER (LOC)
Once the input file is in Advanced Design File (ADF)
format, the LOC will compile it into a device-specific
JEDEC Design File. The first phase of this compilation is performed by the MACRO EXPANDER. The
Macro Expander expands Intel or TIL macros into
equivalent EPLD equations. The second phase is
performed by the ii=SPRESSO MINIMIZE;R. The minimizer reduces all the logic equations to their simplest form using the ESPRESSO II-MV algorithm.
The final phase of compilation is performed by the
FITIER. The Fitter creates a cell map of the minimized equations according to the resources available within the specified device.

D. STATE MACHINE ENTRY
In the past, state diagrams or flowcharts (ASM
charts) were merely abstractions used to obtain the
logic equations necessary to implement TIL designs. With the advent of the iPLS II state machine
convertor (iSTATE), this is no longer the case. Using
an IF THEN I ELSE format, the designer may enter
the state machine description without having to extract the logic and convert the equations into TIL
components. The state machine to Boolean logic
conversion is handled by the state machine convertor, provided the input file adheres to the specified
State Machine File (SMF) format.

MACRO EXPANDER
The input design file is initially passed thfough the
MACRO EXPANDER. The Macro Expander
searches the file for any non-EPLD network elements. If found, the Expander then searches the
User Libraries and TIL Library for the unidentified
element. Once the element is located, the design file
element is replaced by the equivalent EPLD primitive
implemeritation found in the library. Having the Expander search the User Libraries allows the user to
create his own ,macros. User macrp files are created
with a standard ASCII text editor and are stored in
libraries by the iPLS II, Macro Librarian.

Summary of Optional Entry Requirements:
TTL Schematic Capture
1. TTL Macro Library
2. EPLD Custom Macro Library
3. SCHEMA II-PLD
PC-CAPS
1. Intel Library used to design logic circuit
2. Component List Output

ESPRESSO MINIMIZER

3. PCAD convertor used in LOC
(Library and convertor contained in iSLlBPCAD)

The minimization in the LOC is performed by the
ESPRESSO II-M,V MINIMIZER. Developed by the
University of California at Berkeley, the ESPRESSO
II-MV algorithm is regarded by many as being the
best minimization method available. ESPRESSO 11MV uses DeMorgan's and other logic theorems to
reduce the equations to the least number of product
terms possible. Since product terms are the key variable in the EPLD architecture, the ESPRESSO II-MV
Minimizer provides the simplest equations possible.
As a result, the success rate for fitting large designs
is dramatically increased.

DASH-2, -3,-4
1. Intel Library used to design logic circuit
2. Pin List Output
3. FutureNet convertor used in LQC
(Library and convertor contained in iSLlBFNET)
State Machines
1. State Machine File (SMF) format used
2. Optional state machine convertor used in LOC
(Convertor contained in iSTATE)

FITTER
The FITIER examines the architecture of the specified device, then tries to map the minimized equations into the resources available. The Fitter automatically assigns pins unless pin assignments are

4-6

inter

iPLDS II

already specified in the design input file. The fitting
sequence continues until a successful fit is accomplished or all possible implementations are exhausted. Release 2.0 of iPLS II includes a new, faster
Fitter that supports PGA packages and the 5AC312,
5AC324, and 85C508. Also included in this new Fitter is the capability to allocate p-terms to adjacent
macrocells for devices such as the 5AC312 and
5AC324 that support p-term allocation.

LOGIC PROGRAMMER SOFTWARE

To program a device with the LPS, the user enters
the file name and device to be programmed. The
LPS checks if the device is blank, programs the device, then verifies that the device was programmed
correctly. As a part of the Intel EPLD Programming
Algorithm, each programmed cell is checked. Adding the complete device check after programming
gives double verification that the part has been successfully programmed.

OUTPUT FILES

-

-

-

-

It is also possible to read a pre-programmed device
and program other devices with the program read.
The JEDEC Editor in LPS provides a hierarchical
view of the device from the pin level, to the macrocell level, to the product term level. At the product
term level, individual EPROM cells may be set or
reset to connect or disconnect the logic equation
inputs.

JEDEC Design File
A properly designed circuit results in the desired
file from the LOC-the JEDEC Design File. The
JEDEC Design File is a device-tailored EPROM
cell programming map expressed in JEDEC standard format.
Resource Utilization Report
The Resource Utilization Report gives an indepth view of what was used inside the EPLD.
Items such as device pinout, macrocell usage,
and feedback arrangements are all listed. Unused resources are also listed to aid the user in
adding logic or merging EPLD designs.

If the user does not want an EPLD to be read, the
Security bit may be set when running the LPS. The
Security Bit prevents a device from being examined
after it has been programmed. This function is useful
for protecting confidential designs.

Logic Equation File
The LEF file lists the logic equations after they
have passed through the minimizer. It is these
equations that are actually implemented in the
final design.
Compiler Error File
If a logic circuit is incorrectly designed" messages are produced by the LOC denoting the errors. To assist the redesign, these errors are
placed into the Compiler Error File for later reference.

iUP-PC HARDWARE

The Intel Universal Programmer for the Personal
Computer consists of the PCPP programming card,
50-lead interconnect cable, GUPI base and GUPI
adapter. Together they form a system for programming most PROM-type Intel devices directly from
the PC host.
PCPP

The Personal Computer Personal Programmer
(PCPP) is the programmer interface card that fits
into the IBM AT/XT or true compatible. It is capable
of driving both the iUP-GUPI base and the iUPFAST27K personality module. The PCPP emulates
the performance of the Intel iUP-200A. The LPS or
iPPS (Intel PROM Programmer Software) controls
the PCPP, causing the programming card to generate the control signals for the GUPI base.

FILE MERGING

Once a design is successfully implemented, the LOC
can merge it with other designs by simultaneously
running the two ADF's. In this manner, LSI circuits
can be broken into manageable chunks that can be
implemented and tested individually. After each portion is completed, the subcircuits can be merged into
one ADF to implement the total design.

GUPIBASE

III. Device Programming

The Generic Universal Programmer Interface (GUPI)
is used for all programmable logic support. As all

After the design has been successfully entered: minimized and fitted, the designer programs his part using the JEDEC file produced by the LOC. Programming is accomplished by running th~ Logic Programmer Software.

4-7

inter

IPLDS II

,------,

~- ..........

.
I
I

- ......
...

......

I
I
I
I
I

-.
,
,
,
,

I

"

I
I

IUP - GUPI ADAPTER

,,

,-----------------,
.----------------------.
I
I

PCPP
~
••
PROGRA ....ING CARD ~
•
.-,
c .______
--- ,I• ______________________ •

.
I

INTERCONNECT CABLE
(SIDE VIEW OF P.C. HOST)

IUP - GUPI BASE .. ODUlE
290134-7

The Intel Universal Programmer for the Personal Computer (iUP·PC)
signal generation to devices is done by the GUPI,
the programming waveforms are extremely reliable.
Using the GUPI also allows upgrading for future devices with the simple addition of a plug-in adaptor.
Future Intel EPLDs will be supported by the GUPI
system.

vice description data for a family of similar devices.
New devices will be supported by new adapters or
by upgrades to existing adapters.

GUPIADAPTERS

Host System

Table 1 details the GUPI adapters required for the
logic devices. The adapters available for programming EPROM's, E2PROM's and microcontrollers
can be found in the data sheet for the iUP-PC (Intel
order number 290130). The adapters contain the de-

The iPLDS II software requires an IBM PC/XT,
PC/AT or other true compatible computer capable
of running MS-DOS* version 3.0 or later. The computer must have a 360KB double-sided, double-density diskdrive, a hard disk, and 512KB of RAM. Addi-

SPECIFICATIONS

Table 1_ Intel Programmable Logic Development System II Programming Support
iUp·GUPI
Adapter

Package Type
Supported

Device

Number of
Macrocells

5C031,EP310

8

GUPI LOGIC-12

20 Pin DIP

5C032, EP320

8

GUPI LOGIC-12

20 Pin DIP

5C060, EP600

16

GUPI LOGIC-liD

24 Pin DIP

5C090, EP900

24

GUPI LOGIC-liD

5C121, EP1200

28

GUPI LOGIC-12

5C180, EP1800

48

GUPI LOGIC-18

,

40 Pin DIP
40 Pin DIP
. 68 Pin PLCC and JLCC

GUPI LOGIC-18PGA

68 Pin PGA

(inPLU):8
(" of Ports):5

GUPI LOGIC-BIC

44 Pin PLCC

5AC312

12

GUPI LOGIC-liD

24 Pin DIP

5AC324

24

GUPI40D44J

85C508

8

5C180PGA
5CBIC

48

GUPI85EPLD28

(EPXXX Devices from Altera Corp_)
4-8

40-PinDIP
28-Pin DIP and PLCC

intJ

iPLDS II

tional memory is recommended (640K) and is reo
quired for the optional schematic capture programs.
A color monitor is recommended, as the color graph·
ics available provide a better representation of the
data than a monochrome display. The PCPP pro·
gramming card requires one full-size card slot in the
host computer. iPLSIl (Intel Programmable Logic
Software) can run on the IBM PS/2.

GUPI:
Length: 7.0 inches (17.8 cm)
Width: 5.5 inches (1.4 cm)
Height: 1.6 inches (4.1 cm)

Environmental Characteristics

*MS-DOS is a trademark of Microsoft Corporation

10·C to 40·C
Operating Temperature:
Operating Relative Humidity: 85% Maximum

Operating Environment

Equipment Supplied

Electrical Characteristics
PCPP: Worst Case Power Consumption at IBM
PC 1/0 Channel
Supply
Voltage
+5V
-12V
+12V

Voltage
Variance

HARDWARE
-

Personality Max. Current
Drain
Module

+5%, -4% FAST27K
+10%, -9% FAST27K
+5%, -4% GUPI

-

1.898A
102.9 mA
530mA

PCPP programming card
Interconnect cable
GUPI base
(GUPI-LOGIC adaptors purchased separately)

SOFTWARE
-

Physical Characteristics
PCPP:
Length: 1'3.3 inches (33.9 cm)
Height: 3.9 inches (10.0 cm)

iPLSil
iPPS
PLDUTIL

DOCUMENTATION
-

INTERCONNECT CABLE:
50 lead ribbon cable
Length: 3.0 feet (91.4 cm)
Width: 2.43 inches (5.5 cm)

4-9

iPLS II User's Guide·V2.0 (order number 450196)
PCPP User's Guide (order number 168161)

inter

iPLDS II

PLD Utilities:
Functional Simulatory
TTL Macro Library
EPLD Custom Macro Library
iUP-GUPI
Intel Universal ProgrammerGeneric Universal Programmer
Interface: Generic programmer
base which holds GUPI adaptors
GUPI LOGIC-liD GUPI Adaptor for the 5AC312,
5C060 and 5C090.
GUPI LOGIC-12 GUPI Adaptor for the 5C031 ,
5C032, 5C121 and future 20 DIP
EPLDs
GUPI-LOGIC-18 GUPI Adaptor for the 5C180 and
future 68 pin PLCC and JLCC
EPLDs
GUPI LOGICGUPI Adaptor for the 5C180 de18PGA
vice in a 68 pin PGA package.
GUPI-LOGIC-BIC GUPI Adaptor for the 5CBIC and
follow-on products
GUPI Adaptor for the 5AC324;
GUPI40D44J
includes 40-pin DIP and 44-pin
JLCC sockets.
GUPI85EPLD28 GUPI Adaptor for the 85C508; includes 28-pin DIP and JLCC
sockets.
ADAPT24T028
Adapts 24 pin DIP socket to 28
pin PLCC socket; for use with
GUPI LOGIC-09 and GUPI
LOGIC-liD.
ADAPT40T044
Adapts 40 pin DIP socket to 44
pin PLCC socket; for use with
GUPI LOGIC-09 and GUPI
LOGIC-liD.
PLDUTIL

ORDERING INFORMATION
Order Code
iPLDSIl

iPLSIl

iUP-PC

MLiB

iSTATE

iSLlBFNET

iSLlBPCAD

iSIMLIB

Product Description

Intel Programmable Logic Development System II: iPLS
softWare, iUP-PC, iPLS II User's Guide
Intel Programmable Logic
Software II: Logic Builder design entry, Logic Optimizing
Compiler, Logic Programmer
Software, iPLS II User's Guide
Intel Universal Programmer
for the Personal Computer:
PCPP programming card, interconnect cable, iUP-GUPI
base, Intel PROM Programming Software PCPP User's
Guide
iPLS II Macro Librarian: Macro
Librarian Software and User's
Guide Supplement for creating user-defined macro libraries.
Intel State Machine Software:
Entry format documentation,
state machine convertor for
LaC
Intel Symbol Library-FutureNet: EPLD symbol library for
FutureNet DASH-2 schematic
capture package, Futurenet
Pinlist convertor for LaC
Intel Symbol Library-PCAD:
EPLD symbol library for PCAD
PC-CAPS schematic capture
package, PCAD Component
List convertor for LaC
Intel Simulation Library (PCLOGS): EPLD simulation library for PC-LOGS simulator
by PCAD

4-10

intJ

iUP-PC
INTEL UNIVERSAL PROGRAMMER

FOR THE PERSONAL COMPUTER

• Easily Upgradable for new Devices
Through Low-Cost Plug-In Adapters
• Extremely Versatlle-Programs Intel or
Intel-Compatible EPROM, E2PROMs,
EPLDs, Peripherals and MlcroControllers, Including the Latest Intel
EPLDs

• Personal Computer Version of the iUP200A/201A Universal Programmers
• Runs on an IBM PC/AT*, PC/XT* or
True Compatible
• GUPI and FAST27K Personality
Modules Provide Support for Numerous
Device Families
• Utilizes the inteligentTM and QuickPulse Programming™ Algorithms

The Intel Universal Programmer for the Personal Computer, iUP-PC, provides a high performance programming solution from a PC host. Through plug-in adapters for the Generic Universal Programmer Interface (iUPGUPI), the iUP-PC supports all Intel EPLDs and most other Intel programmable devices. Upgrades for new
devices are made by the simple addition of a GUPI adapter or the upgrade of an existing adapter.

290130-1

NOTE:
GUPI Adapter NOT included.
'IBM PC/AT and PC/XT are registered trademarks of International Business Machines Corporation.

4-11

October 1988
Order Number: 290130-003

intJ

iUP·PC

the programming base which holds the device
adapters.

FUNCTIONAL DESCRIPTION
The iUP-PC provides a fast,' versatile and reliable
programming solution from a Personal Computer
host. Downloading to a stand-alone programmer or
moving from one workstation to another i$ no longer
required. With the iUP-PC, the designer may do his
development and -programming on one workstation.
Through the Generic Universal Programmer Interface (iUP-GUPI), the iUP-PC is made extremely versatile. With the iUP-GUPI the designer may program
across EPROM, E2PROM, Microcontrolier, Peripheral and EPLD device categories with the mere
change of a plug in adapter. No other hardware or
software addition is needed. As all of the programming signals are generated at the GUPI base, extremely reliable waveforms reach the device.

GUPI Adapters*-The GUPI Adapters plug-in to the
iUP-GUPI base. They carry the sockets and hardware for a particular device family.
iPPS-The Intel PROM Programmer Software (iPPS)
runs on a personal computer under DOS and controls the PCPP/host communication.
~NOTE:

Though the iUP-GUPI base is included in the iUPPC package, the GUPI Adapters are NOT included.
The desired adapters must be .ordered separately.

PCPP CARD
COMPONENTS
The iUP-PC programming system consists of five
components:
PCPP-The Personal' Computer Personal Programmer (PCPP} is an IBM PC/XT form factor expansion
card which fits into an IBM PC/XT, PCI AT or true
compatible.
Interconnect Cable-A 50 le'ad ribbon cable connects the PCPP to the iUP-GUPI.

The PCPP is an BOBS-based co-processor board.
Communication between the host and the PCPP
may be controlled by the iPPS or LPS (Logic Programmer Software). Version 2.3 or greater of iPPS is
required for running the iUP-PC on a personal computer. LPS is the programming software included in
Intel's Programmable Logic Software II (iPLS II).
The PCPP is capable of driving the iUP-GUPI and
FAST27/K modules. Future Intel EPLDs will be supported by an iUP-GUPI adapter or adapter upgrade.

iUP-GUPI-The Intel Universal Programmer-Generic Universal Programmer Interface (iUP-GUPI) is

'

______ '
~I
........ _
I

:

...
-_

"'~ .........

I

I

iUP - GUPI ADAPTER

I
I

I
I

,

-----------------,
•.----------------------.•

•
·
r:~~~~~~~~..~
1:.-:.-.-.-::. t______'_____________ .. __ .
•
:

PCPP
PROGRAMMIJI!G CARD

(SIDE VIEW

oF' P.C. HOST)

INTERCONNECT ~BLE,

iUP - GUPI BASE MODULE
290130-2

Figure 1. The Intel Universal Programmer for the Personal Computer (iUP-PC)

4-12 '

inter

iUP-PC

iUP-GUPI MODULE

GUPIADAPTERS

The iUP-GUPI is a generic base module that enables
the iUP-PC system to accept low-cost plug-in adapters. These adapters configure the system to support
a wide variety of programmable devices-EPROMs,
microcontrollers, and EPLDs-as well as device
package types.

The iUP-GUPI adapters provide the final link of the
iUP-PC programming system. The adapters provide
the proper sockets and characteristic information for
families of Intel devices.
The iUP-GUPI LOGIC adapters complete the programming solution of the Intel Programmable Logic
Development System II (iPLDS II). The GUPI LOGIC
adapters provide support for the entire range of
Erasable Programmable Logic Devices (EPLDs). .
The adapters support families EPLDs with similar architecture, such as the 5C060 and 5C090. All future
EPLDs will be supported by the GUPI LOGIC adapter system.

The iUP-GUPI module connects to the PCPP card
via a ribbon cable. An opening in the top of the iUPGUPI provides easy plug-in installation of the GUPI
adapters (refer to Figure 2).
The iUP-GUPI offers the programming performance
of earlier Intel personality modules, with the fastest
Intel programming algOrithms for each device type.
For example, the iUP-GUPI uses the new QuickPulse Programming algorithm to program the 1-Meg
EPROM in seconds.

Intel's one megabit EPROMs are also supported
with GUPI adapters. Adapters are available for the
27010, 27011, and 27210. The page mode of the
27011 is supported by the GUPI 27011 adapter. Other Intel EPROM support is provided with the
FAST271K personality module.
Intel's first flash memory products are supported by
the GUPI FLASH Adapter.
The MCS-51 and MCS-96 microcontroller families
are supported by the GUPI MSC-51 and GUPI 8796
adapters. Supplemental adapters provide support
for the variety of microcontroller package types. The
8741 and 8742 peripheral components are supported by the GUPI 8742 adapter.
Table 1 displays a cross-reference of the EPLD
GUPI adapters and the devices they support. Table
2 displays a cross-reference of the EPROM/Microcontroller adapters and the devices they support.
Note that these tables are current at the time of
printing. Contact your Intel sales representative for
information on current support.

iUP-GUPI
GENERIC BASE MODULE
290130-3

Figure 2. GUPI Adapter Installation

Table 1. EPLD GUPI Module Adapters
Device
Type

GUPI
Logic-liD

EPLD

GUPI
Loglc-12

GUPI
40D44J

GUPI
Loglc-18

GUPI
Loglc-18PGA

GUPI
85EPLD28

GUPI
Logic-BIC

5C031
5C032
5C060
5C090
5C121
5C180
5C180G
5CBIC
5AC312
5AC324
85C508

Package
Types

DIp·

DIP

DIP
PLCC

PLCC

CJ

"ADAPT Units aV81lable to adapt DIP socket for PLCC package.

4-13

PGA

DIP
PLCC

PLCC

Device
Type
EPROM

GUPI
27010

GUPI
27011

GUPI
27210

27011

27210

GUPI
FLASH

GUPI
8742

GUPI
MCS-51

GUPI
8796

GUPI
8796LCC

GUPI
87C51GB

27010
27F64
27F256
28F256

Flash

~

8741AH
8742AH

Peripheral

17

CD

8751H
87C51
8752BH
87C51FA
87C51FB

Microcontrolier

~

m

"

XI

o
8794BH
8795BH
8796BH
8797BH

!

s:::
......
s:::

n"

§

8796BH
8797BH

3-

87C51GB

"""

8797BH
87C196KB

Package Types

l

GUPI
MCS-96LCC

DIP

DIP

DIP

DIP

DIP

PLCC
DIP
~---

PGA
DIP
.

------

PLCC

LCC
--

PLCC

2..,CD
C)

c:
:!!

s:::

8.
c
CD

~

"9CD
iil

2:

"P
'tI

n

iUP-PC

The hexadecimal display shows the PROM device
type selected.

The iPPS software supports data manipulation in the
following Intel formats: 8080 hexadecimal ASCII,
8080 absolute object, 8086 hexadecimal ASCII,
8086 absolute object, 80286 absolute object, and
80386 bootloadable object. Addresses and data can
be displayed in binary, octal, decimal, or hexadecimal. The user can easily change default dat"" formats as well as number bases.

Table ,3. FAST27/K Module Device Support
Prom
Type

Fast
27/K
Module

Fast
27/K U2
Kit

Fast
27/K-CON*
Kit

2764
2764A

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
2751,3

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513

2817A

2817A

EPROM

27128
27256

E2PROM

iUP-PC SPECIFICATIONS
HOST SYSTEM
The iPPS will run on an IBM PC/XT, PCI AT or othe~ ,
true compatible with a DOS operating system. The
PCPP requires one full-sized card slot inside the PC.

OPERATING ENVIRONMENT

'Uses QUick-Pulse Programming Algorithm.

Electrical Characteristics

'iPPS SOFTWARE

PCPP:

The iPPS software, included with the iUP-PC brings
increased flexibility to PROM programming. The
iPPS software provides user control through an
easy-to-use interactive interfaoe and performs the
following functions to make programming quick and
easy:

Supply
Voltage

•
•
•
•

Worst Case Power Consumption at
IBM PC I/O Channel

Reads PROMs, ROMs and EPLDs.
Programs PROMs directly or from a file.
Verifies PROM data with buffer data.
Prints PROM buffer, or device file contents on the
system printer.

Voltage
Variance

Personality Max_ Current
Drain
Module

+5V

+5%;-4%

FAST27K

1.898 A

-12V

-1:"10%, -9%

FAST27K

102.9 mA

+12V

+5%, -4%

GUPI

530mA

Physical Characteristics

• Performs interactive formatting operations such
as interleaving, nibble swapping, hit reversal, and
block moves.
.

PCPP:
Length: ,13.3 inches (33.9 cm)
Height: 3.9 inches (10.0 cm)

• Programs multiple PROMs from the source file,
prompting the user to insert new PROMs.

Interconnect Cable:

• Uses a buffer to change P~OM contents.

50 lead ribbon cable
Length: 3.0 feet (91.4 cm)
Width: 2.43 inches (5.5 cm)

With the iPPS software the user can load programs
from system memory or directly from a disk file. Access to the disk lets the user create and manipulate
data in a virtual buffer. This block of data can be
formatted into different PROM word sizes for program storage into several different PROM types. In
addition, a program stored in the target PROM, the
system memory, or a system disk file can be interleaved with a second program and entered into a
specific target PROM or PROMs.

iUP-GUPI:
Length: 7.0 inches (17.8 cm)
Width: 5.5 inches (1.4 cm)
Height: 1.6 inches (4.1 cm)

4-16

inter

iUP-PC

Environmental Characteristics
Environmental Class:

B

Temperature:
Operating
10 to 40 degrees C
Non-Operating -40 to 70 degrees C
Relative Humidity:
Operating
Non-Operating

85% Maximum
95% Maximum

ADAPT24T028

28-Pin PLCC Socket Adapter
for GUPI LOGIC-liD

ADAPT40T044

44-Pin PLCC Socket Adapter
for GUPI LOGIC-liD

piUPGUPI

Generic Universal Programmer
Interface (Base)

GUPI LOGICIID

GUPI Logic Adapter

GUPI40D44J

GUPI Logic Adapter

GUPI85EPLD28

GUPI Logic Adapter

GUPI LOGIC12

GUPI Logic Adapter

GUPI LOGIC18

GUPI Logic Adapter

DOCUMENTATION

GUPI LOGIC18PGA GUPI Logic Adapter for 5C180
PGA

168161-PCPP User's Guide

GUPI LOGICBIC

GUPI Logic Adapter

GUPI27010

iUP-GUPI EPROM Adapter

GUPI27011

iUP-GUPI EPROM Adapter

GUPI27210

iUP-GUPI EPROM Adapter

GUPI8742
GUPIMCS51

iUP-GUPI Peripheral Adapter

166428-iUP-GUPI Module User's Guide
User's Guides for Adaptors, FAST 27/K Modules,
and upgrades included with respective units.

ORDERING INFORMATION
Order Code

Product Description

iUPPC

Universal Programmer for the
Personal Computer: PCPP Programming Card, 50-Lead Interconnect Cable,
iUP-GUPI,
iPPS, PCPP User's Guide

4-17

iUP-GUPI Microcontroller
Adapter

GUPI87C51GB

iUP-GUPI Microcontroller
Adapter

GUPI8796

iUP-GUPI Microcontroller
Adapter

GUPI8796LCC

iUP-GUPI Microcontroller
Adapter

piUPFAST 27K

EPROM Personality Module

iUPFAST 27KU2

FAST 27/K Upgrade Kit

iUPFAST 27KCON

Adds Quick-Pulse
and device support

iUPFAST 27KIT

Combines piUPFAST 27K and
iUPFAST 27KU2

algorithm

iUP-200A/iUP-201A UNIVERSAL
PROM PROGRAMMERS
MAJOR iUP-200A/iUP-201A FEATURES:

•

Personality Module Plug-Ins Provide
Programming Support for Intel and
Intel-Compatible EPROMs, EPLDs,
Microcontrollers, Flash Memories, and
other Programmable Devices

•

PROM Programming Software (iPPS)
Makes Programming Easy with IBM PC,
XT, AT, and PC Compatibles

•

Supports Personality Modules and
GUPI Base WI Adaptors

•

iUP-200A Provides On-Line Operation
with a Built-In Serial RS232 Interface
and Software for a PC Environment

•

iUP-201A Provides Same On-Line
Performance and Adds Keyboard and
Display for Stand-Alone Use

•

iUP-201A Stand-Alone Capability
Includes Device Previewing, Editing,
Duplication, and Download from any
Source Over RS232C Port

•

Updates and Add-Ons Have Maintained
Even the Earliest iUP-200 and iUP-201
Users at the State-of-Art

The iUP-200A and iUP-201A universal programmers program and verify data in Intel and Intel compatible,
programmable devices. The iUP-200A and iUP-201A universal programmers provide on-line programming and
verification in a growing variety of development environments using the Intel PROM programming software
(iPPS). In addition, the iUP-201 A universal programmer supports off-line, stand-alone program editing, duplication, and memory locking. The iUP-200A universal programmer is expandable to an iUP-201A model.

210319-1

4-18

October 1988
Order Number: 210319-005

inter

iUP-200A/iUP-201A

• Verifies device data with buffer data
• Locks device memory from unauthorized access
(on devices which support this feature)

FUNCTIONAL DESCRIPTION
The iUP-200A universal programmer operates in online mode. The iUP-201 A universal programmer operates in both on-line and off-line mode.

• Prints device contents on the network or development system printer
• Performs interactive formatting operations such
as interleaving, nibble swapping, bit reversal, and
block moves

On-Line System Hardware
The iUP-200A and iUP-201 A universal programmers
are free-standing units that, when connected to a
host. compu.ter with at least 64K bytes of memory,
provide on-line programming and verification of Intel
programmable devices. In addition, the universal
programmer can read the contents of the ROM versions of supported devices.

• Programs multiple devices from the source file,
prompting the user to insert new devices
• Uses a buffer to change device contents
All iPPS commands, as well as program address and
data information, are entered through the host system ASCII keyboard and displayed on the system
CRT.

The universal programmer communicates with the
host through a standard RS232C serial data link. Different versions of the iUP-200A and iUP-201A are
equipped with different cables, including the cable
most commonly used for interfacing to that host.
Care should be taken that the version with the correct cable for your particular system is selected, as
cable requirements can vary with your host configuration. A serial converter is needed when using the
MDS 800 as a host system. (Serial converters are
available from other manufacturers.)

The iPPS software supports data manipulation in the
following Intel formats: 8080 hexadecimal ASCII,
8080 absolute object, 8086 hexadecimal ASCII,
8086 absolute object, and 80286 absolute object.
Addresses and data can be displayed in binary, octal, decimal, or hexadecimal. The user can easily
change default data formats as well as number bases. iPPS can also access disk files.
For programming Intel EPLDs, the iUP-200Al201A
can be controlled by Intel's Logic Programming Software (LPS). LPS programs EPLDs from JEDEC files
produced by Intel's logic compiler. (iPPS can also
p~ogram EPLDs, but only from pre-programmed device masters.)

Each universal programmer contains the CPU, seI~ctabl.e power supply, static RAM, programmable
timer, Interface for personality modules, RS232C interface for the host system, and control firmware in
EPROM. The iUP-201A also has a keyboard and display.
A personality module or GUPI Adaptor adapts the
u~lversal programmer to a family of devices; it contains all the hardware and software necessary to
program either a family of Intel devices or a single
Intel device. The user inserts the personality module '
into the universal programmer front panel.

On-Line System Software

System Expansion
The iUP-200A universal programmer can be easily
upgraded (by the user) to an iUP-201A universal programmer for off-line operation. The upgrade kit (iUPPAK-A) is available from Intel or your local Intel distributor.

Off-Line System

The iUP-200A and iUP201 A includes your choice of
one copy of Intel's PROM Programming software
IPPS, selected from a list of versions for different
operating systems and hosts. Each version includes
the software implementation designed for that host
and O.S. and the RS232C cable most commonly
used. Additional versions may be purchased separately if you decide to change hosts at a later date.
The iPPS software provides user control through an
easy-to-use interactive interface. The iPPS software
performs the following functions to make EPROM
programming quick and easy:

The iUP-201A universal programmer has all the online features of the iUP-200A universal programmer
plus off-line editing, device duplication, program verification, and locking of device memory independent
of the host system. The iUP-201A universal programmer also accepts Intel hexadecimal programs
developed on non-Intel development systems. Just
a few keystrokes download the program into the iUP
RAM for editing and loading into a device.
Off-line commands are entered via a 16-character
keypad. A 24-character display shows programmer
status.

• Reads devices
• Programs devices directly or from a file
4-19

intJ

iUP·200A/iUP·201A

Adaptors. GUPI Adaptors tailor the GUPI module
base Signals to a family of devices or an individual
device. The GUPI module and GUPI Adaptors provide a lower-cost method of device support than if
unique Personality Modules were offered for each
device/family. Tables 2 and 3 show which Adaptors
support which devices.

SYSTEM DIAGNOSTICS
Both the iUP-200A'and iUP-201A universal programmers include self"contained system diagnostics that
verify system operation and aid the user iri fault isolation.

PERSONALITY MODULES
For some 'devices, a personality module is the interface between the iUP-200AliUP-201A universal programmer (or an iPDS system) and a selected device.
Personality modules contain all the hardware and
firmware for reading and programming a family of
Intel devices. Table 1 lists the devices supported by
the different modules.
For most devices, the GUPI module and interchangeable GUPI Adaptors provide the interface between the programmer and the device being programmed (see Figure 1). the GUPI (Generic Universal Programmer Interface) module is a base module
that intefaces to the iUP-200Al201 A and GUPI

i\IP·6UP1
6ENERIC BASE MOIIUI.E
210319-12

Figure 1. GUPI Adaptor

4-20

intJ

IUP-200A/IUP-201A

Table 1. IUP Personality Programming Modules

Device Type

Fast 27/K
Module

Fast27/KU2
Kit

Fast 27/K-CON*
Kit

EPROM

2764
2764A
27128
27256

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513

F27/128
Module

F87/44A
Module

F87151A
Module

8041A
8042
8044AH
8741H
8742
8744H

8748
8748H

2716
2732
2732A
2764

27128

2815
2816

E2PROM

2817A

2817A

MicrocontroUer

8755A
'Qulck·Pulse Programmlng™ algorithm

4·21

8749H
8751
8751H
8048
8048H
8049
8049H
8050H
8051

intJ

iUP-200A/iUP-201A

Table 2. iUP-GUPI Adaptors for Programming Memories
GUPI GUPI GUPI GUPI
27010 27011 27210 Flash

Device
Type
EPROM

GUPI
8742

GUPI
MC5-S1

GUPI
8796

GUPI
GUPI
GUPI
8796LCC 87CS1GB MCS-96LCC

27010
27011 27210

Flash

27F64
27F256
28F256

Peripheral

8741AH
8742AH
8751H
87C51
8752BH
87C51FA 8794BH
87C51FB 8795BH
8796BH 8796BH
8797BH 8797BH

Microcontroller

87C51GB
8797BH
87C196KB

Package
Types

DIP

DIP

DIP

DIP

DIP

PLCC
DIP

PGA
DIP

LCC

PLCC

PLCC

Table 3. Programming Adaptors for EPLDs
Device
Type

GUPI
Logic-liD

EPLD

GUPI
Logic-12

GUPI
40D44J

GUPI
Logic-18

GUPI
Logic-18PGA

GUPI
8SEPLD28

GUPI
Logic-BIC

5C031
5C032
5C060
5C090
5C121
5C180
5C180G
.5CBIC
5AC312
5AC324
85C508

Package
Types

DIp·

DIP

DIP
PLCC

PLCC

CJ

"ADAPT Units available to adapt DIP socket for PLCC package.

4-22

PGA

DIP
PLCC

PLCC

inter

iUP-200A/iUP-201A

166043-001- Getting Started with the iUP-200AI
201A (For DOS Users).
- iUP-200A1201A Universal Program164853
mer Pocket Reference.

iUP-200AliUP201A SPECIFICATIONS
Control Processor
Intel 8085A microprocessor
6.144 MHz clock rate

ORDERING INFORMATION
Product
Order Code
iUP-200A 211 A

Description
On-Line PROM programmer with
iPPS rei 1.4 on Single density ISIS
II floppy
iUP-200A 212B On-Line PROM programmer with
iPPS rei 1.4 on Double density
ISIS II floppy
iUP-200A 213C On-Line PROM programmer with
iPPS rei 2.0 for Series IV, on minifloppy
iUP-200A 2160 On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for PC or XT
iUP-200A 2170 On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for AT
iUP-201A 211A Off-Line and on-line PROM programmer with iPPS rei 1.4 on Single density ISIS II floppy
iUP-201A 212B Off-Line and on-line PROM programmer with iPPS rei 1.4 on Double density ISIS II floppy
iUP-201A 213C Off-Line and on-line PROM programmer with iPPS rei 2.0 for Series IV on mini-floppy
iUP-201A 2160 Off-Line and on-line PROM programmer with iPPS rei 2.0 for PCI
DOS, and cable for PC or XT
iUP-201A 2170 Off-Line and on-line PROM programmer with iPPS rei 2.0 for PC/
DOS, and cable for AT
iUP-200/201 U1' Upgrades an iUP-200/201 universal programmer to an iUP-200Al
Upgrade Kit
201 A universal programmer
iUP-DL
Download Support Kit for iUP200Al201A upgrades programmer to support adaptors that use
software programming (.DSS)
files.
iUP-PAK-A
Upgrades an iUP-200/ A universal
programmer to an iUP-201 A uniUpgrade Kit
versal programmer
'Most personality modules can be used only with
an iUP-200Al201 A universal programmer or an
iUP-200/iUP201 universal programmer upgraded to
an A witD the iUP-200/iUP-201 U1 upgrade kit.

Memory
RAM-4.3 bytes static
ROM-12K bytes EPROM

Interfaces
Keyboard: 16-character hexadecimal and 12-function keypad (iUP-201 A model only)
Display: 24-character alphanumeric (iUP-201 A
model only)

Software
Monitor- system controller in pre-programmed
EPROM
iPPS - Intel PROM programming software on
supplied diskette

Physical Characteristics
Depth:
Width:
Height:
Weight:

15 inches (38.1 cm)
15 inches (38.1 cm)
6 inches (15.2 cm)
15 pounds (6.9 kg)

Electrical Characteristics
Selectable 100,120,200, or 240 Vac ± 10%; 50-60
Hz
Maximum power consumption-80 watts

Environmental Characteristics
Reading Temperature:
10°C to 40°C
Programming Temperature: 25°C ± 5°
Operating Humidity:
10% to 85% relative
humidity

Reference Material
166041-001- iUP-200A1201A Universal Programmer User's Guide.
166042-001- Getting Started with the iUP-200AI
201A (For ISISliNDX Users).
4-23

inter

iUp-200A/iUp-201A

Product
Order Code
piUP-GUPI

Description

Generic Universal Programmer Interface (Base)

Software Sold Separately
Product
Order
Code
Description
211A
PROM programming software rei 1.4 on
Single density ISIS II floppy

212B

Product
'Order
Code
Description
PROM programming software rei 2.0 for
213C
Series IV on mini-floppy
2160
PROM programming software rei 2.0 for
PC/DOS with cable for PC or PC XT
PROM programming software rei 2.0 for
2170
PC/DOS with cable for PC AT

PROM programming software rei 1.4 on
Double density ISIS II floppy

4-24

SCHEMA II-PLD
SCHEMA II-PLD is a low-cost schematic capture software for designing with Intel EPLDs and with
standard MSI, SSI, and discrete components. For EPLD designs, SCHEMA II-PLD outputs Advanced
Design Files (ADFs) that can subsequently be compiled by iPLS II software. Figure 1 shows the flow
to generate a drawing file and convert it to an ADF for processing by iPLS II. SCHEMA II-PLD supports
EPLD design primitive symbols as well as MSI and SSI macro symbols, allowing designers to combine
TTL and EPLD symbols as needed. An EPLD Custom library supports groups of EPLD symbols and
"generic" function symbols such as counter, multiplexers, etc. The ability to create user-defined
symbols that can be translated into ADF macro calls adds to SCHEMA II-PLD's power and versatility.
SCHEMA II-PLD provides fast, smooth panning, combined mouse/keyboard support, instant command execution, and automatic "step and repeat" to make schematic capture as quick and easy as
possible. In addition to the symbol libraries targeted for EPLD design, SCHEMA II-PLD provides over
10 symbol libraries for standard PCB design. Its sophisticated library management routines, reentrant
object editor, and true "hierarchical" design capability makes SCHEMA II-PLD a powerful tool for
professional designers.
The EPLD Manager software included with SCHEM II-PLD provides a single user interface to both
SCHEMA II-PLD and iPLS II software modules. EPLD Manager software is also available separately
to users who already own SCHEMA II.
Order Codes:

SCHEMA II-PLD

(SCHEMA II and EPLD Manager)

EPLDMGR

(EPLD Manager)

.------,
1

EPLDMGR
MENU
L.

______

1
1
....

1

r - - - - - - - - - - - - -

.

1

CAPTURE SCHEMATIC

-

-

SCHADF

,

,_/

ADF

o

../

1--+

SYMBOL
LIBRARIES

r-

-

I"--

_/

DRAWING
FILE

SCHDRAW

T

...

,r-"
I"--

_1- - - - - - - - - - - - - - - - - - ...
1 NETLIST TO ADF
INTERFACE
T iPLS II

+---

..
.
.

device.LBR
TTL.LBR
EPLDMAC.LBR
user.LBR
PCB LIBRARIES (10)

Figure 1. SCHEMA II-PLD Schematic Capture Flow for EPLD Designs

4-25

F100139

iPLS II MACRO LIBRARIAN
The iPLS II Macro Librarian (MUB) is a software package that allows designers to build user-defined
macro definition libraries for EPLD designs. Macro libraries can include TTL macros available from
Intel, or proprietary macros developed by a user. User-defined macros are developed as individual
macro files using a text editor, and then are combined into macro libraries by MUB, where they can
be accessed by the LOC. Figure 1 shows the flow to build a macro library. Use of macros in ADFs
(Advanced Design Files) allows EPLD design to proceed at a higher level than with EPLD primitives
alone.
Macro files are standard ASCII files that describe the function of the macro. The Network and Equations seotions of macro files follow ADF format. The header section, which differs from ADF format,
defines the macro name, calling sequence, and defaults. MUB combines these files into a library that
can be accessed by the macro expander in the LOC (Logic Optimizing Compiler). MUB can be invoked
from the command line, from command files, or from a combination of both. The macro expander
identifies and expands each macro call in an ADF with the corresponding macro definition from macro
libraries. The first occurrence of a macro is used.
Two preconfigured libraries are available from Intel: (1) TTL macro library, and (2) an EPLD Custom
macro Library. These libraries are described in the "PLDUTIL" Product Brief.

Order Code: MUB

,r

'-

-

"

./

COMMAND
FILE

TEXT
EDITOR

'-

./

,r

-......,

,r

-......,

'-

./

'-

./

TEXT
EDITOR

MACRO
FILES

'-.

MLiB

MACRO
LIBRARY

'-.

./

MACRO
LIBRARIES ARE
ACCESSED BY
LOGIC COMPILER

./

LIBRARY
LISTING
F100138

Figure 1. FIQw to Build a Macro Library

4-26

PLDUTIL
PLDUTIL V1.0 contains the following utilities for designing with Intel EPLDs:
• SIM, version 2.1 of a basic Functional Simulator for EPLD designs
• TTL.LlB, version 3.6 of Intel's TTL macro definition library
• EPLDMAC.LlB, version 1.0 of Intel's EPLD custom macro definition library.

Functional Simulator
The Functional Simulator allows designers to perform basic function simulation of EPLD designs. By
verifying proper operation of a design with the Simulator, designers can catch logic errors before
devices are programmed and installed in products.
Design information is provided by the minimized LEF (Logic Equation File) generated by the iPLS II
logic compiler. Input stimulus for the Simulator is in the form of a user-generated ASCII vector file
containing strings of 1s and Os (see Figure 1). Vector files can also contain expected output values
to serve as a reference for the simulated outputs. The simulator produces state machine or waveform
output and supports bidirectional signals. Output registers can be preloaded to speed the process of
simulating counter and state machine transitions.
The Functional Simulator operates on any IBM PC/XT, PC/AT, or compatible computer. A.C. timing
simulation is not supported.

STATE TABLE OUTPUT
SCREEN
PRINTER
DISK FILE

-.....,

r-----

.-/
iPLSII
LEF

SIM
OUTPUT

SIM

-001-002-003-004-005-006-007-008-

00
01
01
00
00
01
11
01

0010100000101111-

WAVEFORM OUTPUT

~

'-TEXT
EDITOR

./
VECTOR
FILE

Figure 1. Functional Simulator Flow

4-27

-001-002-003-004-005-006-007-008-

I

-

1

-

I

-

I

1

I

TTL Macro Library
The TTL Macro Library contains macro definitions for most common 74~series TTL devices. The
Ii~rary is accessed by the iPLS II macro expander module when compiling an ADF (Advanced Design
File). When the macro expander identifies a macro call in an ADF, it searches available libraries for
the respective ADF macro definition, and replaces the macro call by the ADF implementation.
I

Macro definitions implement the TTL functions via EPLD design primitives and Boolean equations.
In some cases, precise TTL emulation is not possible. In addtion to the built TTL macro library, the
TTL.LlB disk contains the individual device files (.DEV) used for each macro, and document files
(.DOC) describing the implementation details for each macro. The device files can be used to build
user-defined macro libraries using the iPLS II Macro Librarian.
TTL.LlB provides the ADF macro definitions for compilation. Macro symbols for use with supported
schematic capture packages are provided with the schematic capture software. A complete listing of
the contents of the TTL macros in the library is provided in Applications Brief AB-18, TTL Macro
Library Listing for EPLD Designs.

EPLD Custom Macro Library
The EPLD Custom Macro Library contains macro definitions for a set of common EPLD primitive
groups and "generic" logic functions. Included in the library are groups of INPs, CONFs, RORFs, etc.
Also included are frequehtly used counters, multiplexers, decoders, etc. The library is accessed by
the iPLS II macro expander module when compiling an ADF (Advanced Design File). When the macro
expander identifies a macro call in an ADF, it searches available libraries for the respective ADF macro
definition, and replaces the macro call by the ADF implementation.
In 'addition to the built library, the EPLDMAC.LlB disk contains the individual device files (.DEV) used
for each macro, and document files (.DOC) describing the implementation details for each macro.
The device files can be used to build user-defined macro libraries using the iPLS II Macro Librarian.
EPLDMAC.LlB provides the ADF macro definitions for compilation. Macro symbols for use with
supported schematic capture packages are provided with the schematic capture software. A complete
listing of the contents of EPLD Custom Macro Library is provided in Applications Brief AB-21 , EPLD
Custom Macro Library Listing for EPLD Designs.

Order Code:

PLDUTIL

(Functional Simulator, TTL.LlB, EPLDMAC.LlB and User
Documentation)

4-28

UTILITIES
PAL2ADF UTILITY
Description
This document is a brief note on the use of the PAL2ADF program in translating PALASM 1 files
into Intel's Advanced Design File (ADF) format. Descriptions for actual use can be found on the
accompanying Manual page in the file PAL2ADF.MAN.
The PALASM file serves as a template for mapping the PALASM equations into ADF. The
translation is performed as follows:
1) Read PAL description, and set the PAL pins to their appropriate EPLD primitive
counterparts
2) Parse file and produce network description
3) Translate equations to ADF

PAL Configuration Database
When it is translating a PALASM file, PAL2ADF reads a database (default:PAL2ADF.DAT) that
tells it:
• How many pins the PAL has
• Which default EPLD to translate to
• What pins are special inputs (Clock and Output Enable defaults)
• What EPLD I/O primitives to use for each PAL pin
The EPLD I/O primitives specify the network architecture that the EPLD must take on in order
to mimic the functionality of the PAL. See the PAL2ADF.DAT file for more information.

Reconfiguring Outputs
In step (2) above, several checks are done in order to make sure that the network is configured
appropriately. These primarily involve output pins, although input pins can be specified as well.
The first reconfiguration is for active low outputs in their equations. Le.,
PALASM: /SIGNAL = A· /8 + C
becomes
ADF: SIGNAL = /(A • /8 + C);
The other reconfigurations are slightly more complex. Consider a PAL pin X which is an output
with a D-Iatch. The output value is fed back into the P-term array after the Output Enable. This
is described as a Registered Output Registered Feedback (RORF) in the Intel EPLDs. The default
network description for this pin then is:
NETWORK:
X,X = RORF (Xp,CLK,GND,GND,OE)
where CLK and OE are the default Clock and Output Enable signals.
Normally, there would be an equation that would describe Xp. (The 'p' is used to name the
P-term value.) If, however, the X feedback is never used in an equation, then the I/O macrocell
is reconfigured to a Registered Output No Feedback (RONF).

4-29

NETWORK:

x=

RONF (Xp,CLK,GND,GND,OE)

For those 1/0 pins on the PAL which are used strictly as inputs, these use the Combinatorial
Output 1/0 Feedback (COIF) primitive, with the Output Enable shut off (GND). The P-term is tied
to the feedback, in order to satisfy the semantics of ADF.
NETWORK:

...

,

YY,YY = COIF (YYp,GND)
EQUATIONS:
YYp

=

YY;

If the PAL pin is being used strictly as an output and is never used in an equation, then the
primitive is reconfigured to a Combinatorial Output No Feedback (CON F).
NETWORK:
YY,YY

= COIF (YYp,GND)

This is the same as above where a RORF is reconfigured to a RONF.

Multiple PAL Designs into 1 EPLD
It is possible to incorporate multiple PALASM descriptions into one EPLD. If each PALASM
description is disjoint, (Le., they have different pin names for each pin) then you can simply
translate each file (with the pin list information OFF) and compile them together with the iPLS
Logic Optimizing Compiler (LOC).
The compiler allows you to specify multiple ADF files, allowing different subnetworks within one
EPLD. You will probably want to use a larger EPLD to fit all the designs in.
If the PAL designs are not disjoint, then there are some steps that can be done by hand to
integrate the designs. A simple example would be where one PAL feeds another a signal, and
the second uses that to generate another signal.

~Clc--.c~

~LJ

L:J

4-30

X

In this case, C is an output of PAL 1, and an input to PAl2. In PAl2, C,Z, and W generate the
signal X. Suppose we have the equations:
PAL1
IC=A*/B
PAl2
X = IC*Z*W
+ C*/Z*W
In the resulting ADFs, the following NETWORKS are produced:
ADF for PAL 1:
NETWORK:
A = INP(A)
B = INP(B)
C = CONF(Cp,VCC)
EQUATIONS:
C = I(A * IB);
ADF for PAl2:
NETWORK:
Z = INP(Z)
W =INP(W)
C = INP(C)
X,X = RORF(Xp, ClK, GND, GND, OE)
EQUATIONS:
Xp = IC*Z*W
+ C*/Z*W;
These can be joined together into a single ADF:
NETWORK:
A = INP(A)
B = INP(B)
Z = INP(Z)
W = INP(W)
X,X = RORF (Xp, ClK, GND, GND, OE)
EQUATIONS:
C = I(A * IB);
xp = IC*Z*W
+ C*/Z*W;
Notice how C is now an intermediate variable rather than an actual signal. This is obviously a
simple example, yet similar techniques can be applied to more complex cases. As much more
logic can be placed into larger EPlDs, the job of splitting functions across multiple devices is
reduced.

Availability
The PAL2ADF utility is available at no cost to Intel EPlD customers. Contact your local Intel
sales office.

4-31

JED2HEX CONVERSION UTILITY
Description
JED2HEX is a utility to convert JEDEC files created by iPLS (.JED) into Intellec HEX files which
can then be read by Intel's iPPS software. This allows programming of EPI,.Ds via Intel's iUP~OAl
201A using a GUP I base and the appropriate adaptor (e.g. LOGIC-12). The following diagram
represents a typical development cycle.
iPLS

JED2HEX

.JED '

·1

t

1

.HEX

·8

.TTF
INSTALLATION: To install the utility and its device specific files, place the master disk in drive
A: and invoke the JINSTALL.BAT batch file with the destination path for the utility and device
files. Example:
A: JINSTALL C: MYPATH
When using JED2HEX, attach the package description letter when enterin~ the device type.
That is, enter 5C121D for a 5C121 ceramic DIP when prompted for the device type. Entering
5C121 will result in:
***ERROR: Device File Missing
To determine the packages supported in your JED2HEX software, examine all the .ttl extension
files; it is the .ttl files which the device type command attempts to match.
When using iPPS, a file format of 8080 or 8086 must be specified when copying the JED2HEX
generated HEX file to the buffer or directly into a device. If 8080 or 8086 is not specified, the
default file format type of 80386 will be chosen and a "GENERAL ERROR ""':ILLEGAL FILE
TYPE SPECIFIED" will result. An example of the proper COPY format:
PPS> COpy a: filename. HEX TO PROM 86

Availability
The JED2HEX Conversion Utility is available at no cost to Intel EPLD Customers. Contact your
local Intel sales office.

4-32

inter

AB-18

APPLICATION
BRIEF

October 1988

TTL Macro Library Listing
for EPLD Designs

PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292037-003
4-33

AB-18

TTL Macros

MSI FUNCTIONS

The following is a list of TTL macros that are in
TTL.LIB version.J.6. This library is available through
the Intel EPLD customer hot line.

Decoders/Demultiplexers
7442

These macros are calIed from an Advanced Design File
(ADF). Schematic capture packages such as Schema 11PLD create ADFs with the correct macro invocation
for each TTL device listed here.

7444

7447X
7449

Macros listed here 8re grouped by general function.
74138
74139
74145
74154
74155
74156

SSI GATES
7400
7402
7404
7408
7410
7411
7420
7421
7427
7430
7432
7486

2 Input NAND
2 Input NOR
1 Input INVERTER
2 Input AND
3 Input NAND
3 Input AND
4 Input NAND
4 Input AND
3 Input NOR
8 Input NAND
2 Input OR
2 Input XOR

(10) BCD to Decimal
(10) Excess-3-Gray to Decimal
(7) BCD to 7-Segment-Active Low Output
(7) BCD to 7-Segment-Active High
Output
(8) l-of-8 Decoder
(4) Single l-of-4 Decoder
(10) BCD to Decimal
(16) l-of-16 Decoder
(8) Dual l-of-4
(8) Dual l-of-4

Multiplexers

4-34

74151
74153
74157
74158
74253
74257X

(2)
(2)
(4)
(4)
(2)
(4)

74258X

(4)

74298XA

(4)

74298XB

(4)

74352

(2)

8-to-1
Dual 4-to-l-Active High Output
Quad 2-to-I-Active High Output
Quad 2-to-I-Active Low Output
DuaI4-to-I-Three-State Output
Quad 2-to-I-Active High, ThreeState Output
Quad 2-to-l-Active Low, ThreeState Output
Quad 2-to-I-Active High with Storage
Quad 2-to-I-Active High with Storage
DuaI4-to-I-Active Low Output

inter

AB-18

Counters
7490XD
7490XQ
74160
74161
74162
74163
74168
74169
74176XD
74176XQ
74177X
74190XA
74190XB
74191XA
74290XD
74290XQ
74390X
74393XA
74393XB
S
A
9

=
=
=

U/D
RCO
MM

(4)
(4)
(5)
(5)
(5)
(5)
(5)
(5)

(4)
(4)
(4)
(6)
(6)
(7)
(4)
(4)
(4)
(4)
(4)

Type
BCD Decade
Bi-Quinary
BCD Decade
4-Bit Binary
BCD Decade
4-Bit Binary
BCD Decade
4-Bit Binary
BCD Decade
Bi-Quinary
4-Bit Binary
BCD Decade
BCD Decade
4-Bit Binary
BCD Decade
Bi-Quinary
Bi-Quinary/BCD
4-Bit Binary
4-Bit Binary

Synchronous
Asynchronous
Synchronous Set-to-9

=
=
=

Load
9
9

Clear

S
S

S
S
S
S
S
S
S
S
S
S
S
S

A
A

S
S

A
A
A

S
S

9
9

R
F

=
=

7472XB
7473X
7474X
74112XA
74112XB

74378

UfO, RCO,MM
U/D,RCO,MM
U/D,RCO,MM

Rising-Edge Triggered
Falling-Edge Triggered

(2)
(2)
(2)
(2)
(3)
(2)

Latches

AND-Gated JK Master/Slave
AND-Gated JK Master/Slave
JK with Clear
D with Preset and Clear
JK with Preset and Clear
JK with Clear

7475X
7477X
74259XA
74259XB
74373X

Multiple Flip-Flops (Registers)

74377

RCa
RCa
RCa
RCa
U/D, RCO
U/D, RCa

Up/Down
Ripple Carry Output
Max/Min Output

7472XA

74273X

Extras

F
F
F

A
A
A

Single Flip-Flops

74174X
74175X

Clk
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

(6)
(8)
(8)
(8)
(6)

Hex D
Quad D with Q and /Q
Octal D
Octal D with Common Enable
Hex D

4-35

(8)
(4)
(8)
(8)
(8)

4-Bit Bistable
Quad D-Type
Octal Addressable D-Type
Octal Addressable D-Type
Octal D-Type

inter

AB-18

Shift Registers
7491
7495XA
7495XB
7495XC
7496X
74164
74165X
74194
74395XA
74395XB

DEMORGAN EQUIVALENTS
(BUBBLE GATES)

(8) 8-Bit-Serial-In, Serial-Out
(4) 4-Bit-Serial-In/Parallel-In,
Parallel-Out
(4) 4-Bit-Serial-In/Parallel-In,
Parallel-Out
(4) 4-Bit-Serial-In/Parallel-In,
Parallel-Out
(5) 5-Bit-Serial-In/Parallel-In,
Parallel-Out
(8) 8-Bit-Serial-In,
Parallel-Out
(9) 8-Bit-Serial-In/Parallel-In,
Serial-Out
(4) 4-Bit Bi-Directio.nalSerial-In/Parallel-In, Parallel-Out
(5) 4-Bit CascadableSerial-In/Parallel-In, Parallel-Out
(5) 4-Bit CascadableSerial-In/Parallel-In, Parallel-Out

2 Input
3 Input
4 Input
6 Input
8 Input
12 Input

(4)
(8)
(7)
(4)
(17)

74180X
74180XA
74182
74183

(4)
(4)
(5)
(2)

74280X

(5)

Bubble
NAND
(OR)
BNAND2
BNAND3
BNAND4
BNAND6
BNAND8
BNAND12

Bubble
NOR
(AND)
BNOR2
BNOR3
BNOR4
BNOR6
BNOR8
BNOR12

Bubble
OR
(NAND)
BOR2
BOR3
BOR4
BOR6
BOR8
BOR12

INPUTIOUTPUT MACROS
INPUT

N/A Generates Input Pin and No.de in
ADF
OUTPUT (1) Generates Enabled Output Buffer in
ADF
OUTP
(1) Output Pin (Used in SCHEMA IIPLD)
74125
(1) Single Three-State Output, Active
Lo.w Enable
(1) Single Three-State Output, Active
74126
High Enable

Miscellaneous
7482X
7483X
7485X
7487
74143X

Bubble
AND
(NOR)
BAND2
BAND3
BAND4
BAND6
BAND8
BAND12

2-Bit Adder
4-Bit Adder
4-Bit Magnitude Co.mparato.r
4-Bit True/Co.mplement Element
4-Bit Co.unter; 4-Bit Latch; 7 Segment
Deco.der
8-Bit Parity Generato.r/Checker
8-Bit Parity Generato.r/Checker
Lo.o.k-Ahead Carry Generato.r
Single-Bit Full Adder
with Carry/Save
9-Bit Odd/Even Parity Generato.r/
Checker

NOTES:
1. All TTL macro.s duplicate TTL functio.n o.nly. They
DO NOT DUPLICATE perfo.rmance characteristics
such as o.pen-co.llecto.r, to.tem-po.le, Dr high-drive o.utput.
2. Any TTL macro.s which deviate in so.me way fro.m
standard TTL functio.n are deno.ted with an appended
"X" (see device .DOC file fo.r details). Appended
"D"s and "Q"s indicate co.unters co.nfigured to. Decimal Dr bi-Quinary mo.de; appended "A"s and "B"s indicate a macro co.nfigured fo.r a family o.f EPLD devices (e.g. 5C060, 5C090, 5CI80).
3. The (#) indicates the maximum number o.f EPLD
macrocells consumed if all o.utputs are used. If an o.utput is no.t used, the macro. co.mpressio.n phase o.f the
Macro. Expander will remo.ve the signal unless it is
used as feedback inside the macro. definitio.n.
4. /Q's sho.u1d be avo.ided as pin o.utputs if po.ssible.
The EPLD is structured such that the Q is readily
available as a pin o.utput and both the Q and /Q are
readily available as feedbacks. Using /Q as a pin o.utput, however, requires an extra macro.cell and adds to.
the propagatio.n delay.

4-36

inter

APPLICATION
BRIEF

AB-21

October 1988

EPLD Custom Macro Library
Listing for EPLD Designs

PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292050-001
4-37

AB-21

EPLD CUSTOM MACROS
The following is a list of the macros contained in version 1.0 of Intel's EPLD Custom Macro Library
(EPLDMAC.LIB). This library is available through the Intel EPLD customer hot line.
These macros are called from an Advanced Design File (ADF). Schematic capture packages such as SCHEMA 11PLD create an ADF with the correct macro invocation syntax for each macro listed here.
The macros are grouped by function. The macro name is followed by the least number of macrocells used and a
description of the macro's function.

INPUTS
21NP
4INP
61NP
81NP

(0)
(0)
(0)
(0)

2 Input
4 Input
6 Input
8 Input

Pins
Pins
Pins
Pins

BURIED FEEDBACK
4NOCF
6NOCF
8NOCF

(4)
(6)
(8)

4 "No Output Combinational Feedback" I/O Primitives
6 "No Output Combinational Feedback" I/O Primitives
8 "No Output Combinational Feedback" I/O Primitives

COMBINATIONAL 1/0
4CONF
6CONF
8CONF
4COIF
6COIF
8COIF

(4)
(6)
(8)
(4)
(6)
(8)

4 "Combinational Output
6 "Combinational Output
8 "CombinatioJ?al Output
4 "Combinational Output
6 "Combinational Output
8 "Combinational Output

No Feedback" I/O Primitives
No Feedback" I/O Primitives
No Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives

REGISTERED 1/0
4RONF
6RONF
8RONF
4ROIF
6ROIF
8ROIF
4RORF
6RORF
8RORF

(4)
(6)
(8)
(4)
(6)
(8)
(4)
(6)
(8)

4 "Registered Output
6 "Registered Output
8 "Registered Output
4 "Registered Output
6 "Registered Output
8 "Registered Output
4 "Registered Output
6 "Registered Output
8 "Registered Output

No Feedback" I/O Primitives
No Feedback" I/O Primitives
No Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives
Registered Feedback" I/O Primitives
Registered Feedback" I/O Primitives
Registered Feedb!lck" I/O Primitives

4-38

AB-21

LATCHES/REGISTERS
4REG .
6REG
8REG
4LATCH
6LATCH
8LATCH
8TRANS
RSLATCH
DLATCH
DFFPRE

(4) 4 Registers with Common Clock and Clear
(6) 6 Registers with Common Clock and Clear
(8) 8 Registers with Common Clock and Clear
(4) 4 Transparent Data Latches with Common Enable
(6) 6 Transparent Data Latches with Common Enable
(8) 8 Transparent Data Latches with Common Enable
(8) 8-Bit Bi-Directional Data Transceiver
(I) Set-Reset Latch
(I) Standard D-Type, Transparent Latch
(2) D Flip-Flop with Preset and Clear

MULTIPLEXERS/ENCODERS
2MUX
D2MUX
Q2MUX
4MUX
8MUX
16MUX
10MUXBCD

(0) 2-to-1 Multiplexer
(0) Two 2-to-1 Multiplexers with Common Select
(0) Four 2-to-1 Multiplexers with Common Select
(0) 4-to-1 Multiplexer
(0) 8-to-1 Multiplexer
(0) 16-to-1 Multiplexer
(0) 1O-to4 BCD Encoder

CONVERTERS/DECODERS
BINGRY
GRYBIN
lOEC
2DEC
4DEC
3DEC
7SEG

(0)
(0)
(0)
(0)
(0)
(0)
(0)

4-Bit Binary to Gray Code Converter
4-Bit Gray Code to Binary Converter
l-to-2 Decod~
2-to-4 Decoder
4-to-16 Decoder
3-to-8 Decoder
4-Bits to Seven Segment Display Decoder

COUNTERS/DIVIDERS
2CNT
4CNT
8CNT
16CNT
BCDCNT
FDIV2
FDIV5

(2)
. (4)
(8)
(16)
(4)
(4)
(4)

2-Bit Counter with Preload and Clear
4-Bit Counter with Preload and Clear
8-Bit Counter with Preload and Clear
16-Bit Counter with Preload and Clear
4-Bit BCD Counter with Preload and Clear
Divides Input Frequency By 2, 4, 8, and 16
Divides Input Frequency By 5, 10, 15, and 20

4-39

inter

AB·21

SHIFT REGISTERS
2SHIFT
4SHIFT
8SHIFT
16SHIFT

(2)
(4)

2-Bit Serial or Parallel In Shift Register with Enable
4-Bit Serial or Parallel In Shift Register with Enable

(8)

8-Bit Serial or Parallel In Shift Register with Enable

(16) 16-Bit Serial or Parallel In Shift Register with Enable

ARITHMETIC OPERATIONS
lADD

(0)

I-Bit Full Adder

2MULT
4COMP

(0)
(0)

2-Bit Multiplier
4-Bit Magnitude Comparator... Equality Only

(2)
8COMP
8PAREVN (2)

8-Bit Magnitude Comparator... Equality Only
8-Bit Even Parity Generator

8PARODD (2)

8-Bit Odd Parity Generator

4-40

inter

APPLICATION
NOTE

AP-311

October 1988

Using Macros in EPLD Designs

DANIEL E. SMITH
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292039-002

4-41

inter

Ap·311

• A Macro Expander in the LOC that expands macro
calls in ADFs with the contents of the corresponding macros from libraries.

INTRODUCTION
The iPLS II (Intel Programmable Logic Software) Logic Optimizing Compiler includes a Macro Expander
that supports the use of macros in EPLD designs. This
application note shows how to use the TTL and EPLD
Custom macros available from Intel with ADFs created
by a text editor. Included are descriptions of macro file
support, guidelines for using macros, and two design
examples.

Figure 1 shows text editor/ADF macro support for
iPLS II. Note that the ADF can be created by any
standard ASCII text editor (text edi.tor supplied by
user). Creation of user-defined macros is covered in application note, AP-3l2 "Creating Macros for EPLD
Designs", order number 292040. Use of macros with
schematic capture software is covered in the documentation for the respective software package.

OVERVIEW

This note discusses use of macros under the following
headings:
• Macro Libraries, briefly describes the two libraries
available from Intel.
• Using Macros, describes macro files, how to call
macros, the process of macro expansion, calling
multiple macro calls, and some basic guidelines to
follow and pitfalls to avoid.
• Two examples showing use of TTL macros, and
mixing macros and EPLD primitives.

iPLS II allows designers to include macro calls in design files to implement common circuit functions. Macro calls are subsequently expanded by the LOC (Logic
Optimizing Compiler) into ADF network and/or equation entries required to perform the desired functions.
Use of macros allows designs to proceed at a high level,
which simplifies and shortens the design process. Macros can be connected together or used in conjunction
with standard iPLS II EPLD primitives. Designing
with macros is analogous in many ways to using subroutines in software.

MACRO LIBRARIES

Macros can be used in ADFs (Advanced Design Files)
created by a text editor, or by several schematic capture
software products. This application note covers use of
macros in ADFs created by a text editor. Macro support at this level includes the following:
• A TTL macro library (TTL.LIB) for designing with
common TTL circuit equivalents
• An EPLD custom macro library (EPLDMAC.LIB)
for designing with "generic" macros.

Intel offers two macro libraries: a TTL Library and an
EPLD Custom Library.

TTL Macro Library
A TTL macro library (TTL.LIB) is available from Intel
to support design entry using familiar 74-series logic
IPLS II LOC

TEXT
EDITOR

--+

-

--+

ADF

-

MACRO
EXPANDER

ESPRESSO
MINIMIZER

FITTER

H

-

f
.•

•••

~

-

JEDEC

MACRO
LIBRARIES

~TTL
I..r..

: - - - -- --- !~

EPLD CUSTOM
USER

Figure 1. Text Editor/ADF Macro Support for IPLS II

4-42

292039-1

inter

AP-311

Some of the macros in the TTL library have an "X"
suffix appended to the filename, for example 74138X.
This suffix indicates that the macro is device-specific
(not supported on all EPLDs) or that there is some
difference from the TTL device. This information is
described in the .DOe file for each macro.

devices. The library contains macros that implement
the most widely used 74-series device functions as well
as macros for some members of other logic families.
Each device in the library is supported by a .DOe file.
The .Doe file describes the macro syntax and lists any
notable differences between the macro implementation
and the TTL part.

The second line of the macro file contains defaults for
each input and place holders (blanks) for each output.
The default for an input sets the input to an intelligent
level (i.e., enables are enabled, clears, preset, loads are
disabled, etc.).

EPLD Custom Macro Library
An EPLD custom macro library (EPLDMAe.LIB) is
available from Intel to support design entry using
groups of EPLD primitives or "generic" functions such
as latches, registers, counters, decoders, etc.

Macro files can contain a Network section, an Equation
section, or both. A Network section is not needed when
the macro functions can all be implemented in Boolean
equations. When used, the Network section contains
EPLD design primitives. An Equations section is not
needed when the macro functions can all be implemented in the Network section. Macro files end with the
keyword "ENDEF".

USING MACROS
The iPLS II Macro Expander is automatically invoked
by the LOe when an ADF is submitted to the compiler. When invoked, the Macro Expander identifies macro calls in ADFs, searches macro libraries for a corresponding macro, and expands the call with ADF network and equation entries from the macro file. The
expanded file is then compiled normally.

Macro Calls
All macro calls appear in the Network section of an
ADF. Macro calls use the same part/function name
and signal sequence used on the first line of the macro
file. The signal names in the macro and the macro call
do not need to match, but the order of signals in the
call is crucial to proper implementation of the macro
function. For example, the macro call for the 74138
device could be anyone of the following examples:

Macro Files
Figure 2 shows the macro file for a 7413.8 TTL device,
a commonly used one-of-eight decoder. Note that the
first line contains the name and I/O signals for the
device. Signals are listed in the order in which they
appear on the actual TTL device, including vee and
GND (i.e., A = pin 1, B = pin 2, ... , vee = pin 16).
The sequence of signals in this line determines how the
macro is "called" from an ADF.

74138(A,B,C,G2A,G2B.Gl,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Yl,YO,VCC)
74138(Dl,D2,D3,EN1,EN2,EN3,07,GND,06,
05,04,03,02,Ol,OO,VCC)

74138(A.B.C.nG2A.nG2B.Gl.nY7.GND.nY6.nY5.nY4.nY3.nY2.nYl.nYO.VCC}
DEFAULT:(GND.GND.GND.GND.GND.VCC •• GND •••••••• VCC}
NETWORK:
EQUATIONS:
nYO
nYl
nY2

nY3
nY4
nY5
nV6
nY7

= !(!A •

IB • !C • !nG2A * !nG2B • Gl);
I(A * !B * !C * !nG2A * !nG2B * Gl);
* B * Ie * !nG2A * InG2B * G1);
!(A*B* !C· !nG2A* !nG2B*G1);
• 1(IA * IB * C * !nG2A * !nG2B * G1);
!(A * !B * C * !nG2A * !nG2B * G1);
= 1(IA * B * C * !nG2A * !nG2B * G1);
_ I(A * B * C * !nG2A * !nG2B * Gl);
-

=!(!A

ENDEF
$

292039-2

Figure 2. Sample TTL Macro File (74138.DEV)

4-43

intJ

AP-311

74138(A,B,C,ENA,ENB,ENC,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Yl,YO,VCC)

appropriate gate array input or output macro calls.
When using gate array macros with EPLDs, the I/O
macros are implemented in terms of EPLD primitives.
Note that when designs targeted for gate arrays are
partitioned for multiple EPLDs, many internal gate array signals are transformed into EPLD input and output signals. These signals must be supported by INPUT
and OUTPUT macro calls.
'

In each case, the part name corresponds to the macro
part name. The names of the signals differ, but the or.
der of signals match the macro. During processing, the
Macro expander assigns node connections between the
macro call and the macro file based on the positions of
signals, not the names of the signals. For example, note
the following macro call to macro file signal assignments:
ADf MACRO CALL

MACRO fiLE SYNTAX

Macro Expansion
The Macro Expander identifies and expands each macro call in an ADF with the corresponding macro definition from macro libraries (the TTL library in the case
of the 74138). The Macro Expander searches libraries
in the following order and in the directories listed:
• MACRO. LIB-first in the current directory, then
in other directories specified by the DOS "PATH"
variable.
• user libraries (filename.LIB)-names for user libraries are specified in the "IPLS" environment variable. If a pathname and filename are both specified
(SET IPLS= C:\MACLIB\USRl.LIB;), the path is
treated as an absolute path. If a filename alone is
specified (set IPLS = USR 1. LIB;), the Macro Expander searches for that library in the directories
specified by the "PATH" variable. (IPLS can be set
in an AUTOEXEC.BAT file.)
• TTL macro library (TTL.LIB)--first in the current
directory, then in other directories specified by the
DOS "PATH" variable.

74138 ( A, B, C, EN 1. EN2. EN3. YCS •...

ttt t t t t

74138 (A, B, C. nG2A, nG2B, G1. nY7, ...
292039-3

TTL macro signals originating outside the target EPLD
require a prior INPUT macro call in the Network section. All signals used as outputs require a prior OUTPUT macro call in the Network section. Figure 3 shows
a sample ADF that uses the 74138 macro. Each input is
listed in the INPUTS: declaration and has an INPUT
macro call. Outputs are listed in the OUTPUTS: declaration and have OUTPUT macro calls. (EPLD INP
and CONF primitive statements may also be used in
place oflNPUT and OUTPUT macro calls, if desired.)
Gate arrays support a much richer selection of input
and output types than EPLDs. Gate array signals originating outside the target gate array device require the
YOUR NAME
YOUR COMPANY
DATE
1
A

5C060
One-af-Elght Decoder
OPTIONS, TURBO=OFF
PART, 5C060
INPUTS, A.B,C,G2A.G2B.Gl
OUTPUTS, Y7.Y6.Y5.Y4,Y3.Y2.Yl.YO
NETWORK,
INPUT{A.A)
INPUT{B,B)
INPUT{C.C)
INPUT{G2A,G2A)
INPUT{G2B,G2B)
INPUT{Gl ,Gl)
OUTPUT{Y7,Y7)
OUTPUT{Y6.Y6)
OUTPUT{Y5.Y5)
OUTPUT{Y4.Y4)
OUTPUT{Y3.Y3)
OUTPUT{Y2.Y2)
OUTPUT{Yl, Yl)
OUTPUT{YO.YO)
74138{A.B.C,G2A.G2B,Gl.Y7.GND.Y6,Y5.Y4.Y3.Y2,Y1,YO,VCC)
END$

292039-4

Figure 3. ADF File Calling the 74138 Macro

4-44

AP-311
• EPLD Custom macro library (EPLDMAC.LIB)first in the current directory, then in other directories specified by the DOS "PATH" variable.
• reserved iibrary (INTEL.LIB)-first in the current
directory, then in other directories specified by the
DOS "PATH" variable.

The Macro Expander uses the ADF Network and
Equation entries from the macro libraries and assigns
the appropriate primitives for INPUT and OUTPUT
calls. INP primitives are assigned to replace the INPUT macro calls. The OUTPUT calls are assigned
primitives with output pins and output enables are supplied where needed.

Only the first occurrence of a macro is used. The names
TTL. LIB, EPLDMAC.LIB, and INTEL.LIB are reserved by Intel. They may not be used for user libraries
and may not be specified in the "IPLS" variable. The
"IPLS" variable can contain more than one library
name. Each library can have an absolute path or can
rely on the "PATH" variable to determine the search
path.

Combination of primitives is automatically performed
when needed. For example, when a feedback primitive
such as a NORF feeds an output primitive such as a
RONF, the Macro Expander combines the two primitives into a RORF. Combination of primitives conserves resources and results in the shortest possible delay path through the device.
During macro expansion, unused nodes are eliminated.
For example, the VCC and GND nodes that correspond to TTL power and ground pins are eliminated. If
an input node is not connected to a node in the ADF,
the default value for that node is assigned from the

NETWORK:
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%
%'%
%

INPUT(A,A)
%
A=INP(A)
INPUT(B,B)
%
B=INP(B)
INPUT(C,C)
%
C=INP(C)
INPUT(G2A,G2A)
%
G2A=INP(G2A)
INPUT(G2B,G2B)
%
G2B=INP(G2B)
INPUT(Gl,Gl)
%
Gl=INP(Gl)
OUTPUT(Y7,Y7)
%
Y7=CONF(Y7,VCC)
OUTPUT(Y6,Y6)
%
Y6=CONF(Y6,VCC)
OUTPUT(Y5,Y5)
%
Y5-CONF(Y5,VCC)
OUTPUT(Y4,Y4)
%
Y4=CONF(Y4,VCC)
OUTPUT(Y3,Y3)
%
Y3-CONF(Y3,VCC)
OUTPUT(Y2,Y2)
%
Y2-CONF(Y2,VCC)
OUTPUT(Yl,Yl)
%
Yl-CONF(Yl,VCC)
OUTPUT(YO,YO)
%
YO*CONF(YO,VCC)
74138(A,B,C,G2A,G2B,Gl,Y7,GND,Y6,Y5,Y4,Y3,Y2,Yl,YO,VCC)

%

EQUATIONS:
%'%
%'%
%'%
%'%
%'%
%'%
%'%
%'%

YO=!(!A*!B*!C*!G2A*IG2B*Gl);
Yl-!(A*!B*!C*IG2A*IG2B*Gl);
Y2=1(!A*B*!C*!G2A*!G2B*Gl);
Y3=!(A*B*!C*!G2A*!G2B*Gl);
Y4=!(!A*IB*C*!G2A*!G2B*Gl);
Y5=!(A*!B*C*!G2A*!G2B*Gl);
Y6=!(!A*B*C*!G2A*!G2B*Gl);
Y7-!(A*B*C*!G2A*!G2B*Gl);
292039-5

Figure 4. Network and Equations for 74138.SDF
4-45

intJ

AP-311

DEFAULT: section of the macro file. Note, however,
that the default value for each input in the macro file
may be the value that disables the input or, for data
inputs, is usually a logic O. To be certain of the level
used, specify a "VCC" or "GND" in the macro call for
unused inputs.

The Macro Expander uses the first three ASCII characters after the first percent sign (%), except for white
space, to create instance !lumbers. For example, internal nodes for the first three signals of each macro call
will be:
.

..SFAN1, •• SFAN2, •• SFAN3,
The INPUT and OUTPUT calls and the original macro call are "commented out" by surrounding them with
percent (%) signs. The %A% string is placed at the
start of lines where primitives are created. by the Macro
Expander. The fully expanded file is written to the disk
using the original filename and a .SDF extension. Figure 4 shows the Network and Equation sections for the
74138 SDF.

•• SFBN1, •• SFBN2, •• SFBN3
where SFA/SFB are the user-defined instance names
and NI, N2, N3 are the node numbers associated with
each instance. For cases where no internal nodes numbers are generated, the Macro Expander simply ignores
the instance name.
Outputs from one macro call can be used as inputs for
other calls, as follows:

One final note with regard to compiling ADFs that use
macros. Warning messages are typically encountered
while compiling files that use macros. The most common message is .. ···WARN-XLT-Node Missing Destination". This message is displayed as unused nodes
from a macro are deleted. For example, if a macro using a NOCF primitive is combined with a CONF and
the original feedback is not needed, the warning is displayed as the feedback is deleted.

74138(A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Y1,YO,VCC)
74138(A,B,C,Y7,G3B,G1,YF,GND,YE,YD,YC,
YB,YA,Y9,Y8,VCC)
Here the Y7 output from the first decoder feeds an
enable input of the second decoder.

Multiple Macro Calls
The Macro Expander allows use of more than one macro in ADFs. Each macro must have its own call, even
when the same macro is used more than once.

Different macros are connected in the same manner.
For example, the following macro calls connect the outputs from a 74138 decoder to the inputs of 74175 latches:

For example, to implement two 74138s, each case or
"instance" must have its own call:

74138(A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Y1,YO,VCC)

74138(A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Y1,YO,VCC)

74175 (CLR,OQ,nOQ,YO,Y1,n1Q,lQ,GND,CLK,
2Q, n2Q,Y2,Y3,n3Q,3Q,VCC)

74138(A,B,C,G3A,G3B,G1,YF,GND,YE,YD,
YC,YB,YA,Y9,Y8,VCC)

74175 (CLR,4Q,n4Q,Y4,Y5,n5Q,5Q,GND,CLK,
6Q, n6Q,Y6,Y7,n7Q,7Q,VCC)

In this example, many of the inputs are routed to both
devices. The Macro Expander automatically generates
internal nodes for each instance of the macro. Each
node is assigned a unique number based on the position
of the macro in the Network section (i.e., .. 0140,
.. 0141, etc. for nodes connecting to the 14th primitive
in the Network section).

Each decoder output is routed to a 74175 input. The
74175 macro produces both true and complement
latched outputs.

Guidelines/Pitfalls
The following paragraphs discuss some general guidelines for using macros:
• Because the Macro Expander supports only one level of hierarchy, there is a tende!lcy for p-terms to
multiply quickly when several macros are connected
together. In many cases, the total number of p-terms
exceeds the capacity of the target EPLD. One method of avoiding problems with excessive p-terms is to
route the outputs from a macro function through
EPLD macrocells and use the feedbacks from the
macrocells as inputs to the subsequent macro functions. This partitioning of functions trades off device
resources for a lower p-term count.

For traceability, you can define your own instance
names for nodes of different macros by including the
instance name in a comment immediately following the
macro call. For example, to call two 74161 macros, one
as Shift Register A and the other as Shift Register B,
enter the calls as follows:

74161(CLR,CK,A,B,C,D,ENP"LD,ENT,QD,
QC,QB,QA,RD1,) % SFA %
74161(CLR,CK,E,F,G,H,ENP"LD,ENT,QH,
QG,QF,QE,RC2,.) % SFB %
4-46

AP-311

• Implementation of some TTL macros requires primitives that are not supported on all devices. The
.DOC file for a device notes any device dependency.
In many cases, a modification to the basic TTL
functions results in device independence. For example, a NOCF, which is not supported on all EPLDs,
can be changed to a COIF, which is supported on
all devices.
• Some macros use primitives that specify an output
pin (COIF, CONF, RORF, etc.). These primitives
must be supported with a signal name in the OUTPUTS: declaration and by an OUTPUT call in the
Network Section of the ADF. Failure to provide
this support causes the following error message during compilation:

Circuit
The design is a two-stage decoder using a 74138 macro
and two 74139 macros. Figure 5 shows the schematic
for the circuit. Each 74139 macro represents one half of
a TTL 74139 device. Note that two of the outputs from
the 74138 are routed back to enable the two 74139 decoders.
A
B
C

YO
Yl
Y2
Y3
Y4

74138
ENl
EN2
EN3

***ERR-XLT-undeclared output name

YCS
YCE

If you encounter this error, check the macro file for
output primitives that require ADF support.

Y5

~

CEO

D

CEl

74139

CE2

L......c

Macro Usage Summary

CE3

r--

ADF macro calls must observe the following guidelines:
• Macros are called from the Network Section of an
ADF.
• The name in the call must match the name in the
macro file (e.g., 74138 = 74138).

CSO
CSl

74139

CS2

'--<

CS3

292039-6

Figure 5. Schematic Diagram
for Two-Stage Decoder

• All input and output pins on the target device must
have both: (I) a corresponding signal name in the
INPUTS: or OUTPUTS: declaration, and (2) a corresponding INPUT or OUTPUT macro call in the
Network section. It is recommended that the same
node name be used on both sides of each INPUT
and OUTPUT macro call. This is required when
macros containing CONFs are used. (EPLD INP
and CONF primitives may also be used) ..

Figure 6 shows the ADF file containing the macro calls
that implement the circuit. The two internal feedback
signals (YCS and YCE) do not show up in the INPUTS: or OUTPUTS: declarations and are not represented by INPUT or OUTPUT calls in the Network
section. The sequence of signals in the INPUTS: and
OUTPUTS: declarations of the ADF is not important.
In the NETWORK: section, however, order is important. INPUT and OUTPUT calls must be listed before
any other macro calls. This is a requirement of the
Macro Expander. The sequence of signals within the
ADF macro call is critical, as the Macro Expander automatically assigns macro call signals to macro file signals based on position.

• All INPUT and OUTPUT calls in the Network section must precede any other macro call.
• Node connections within an ADF are made based
on the names of the nodes.
• Connections between the macro call and macro files
are based on the position of signal names in the call.
Therefore, the sequence of inputs and outputs in a
macro call must match the sequence of inputs and
outputs in the corresponding macro file.

Internal connections between macros are established by
assigning the same name to the respective signals. For
example, YCS in the 74138 macro call in Figure 7 represents the nY6 output from the 74138, while YCS in
the 74139 macro call represents the IG input to one
74139 decoder. Use of the same name establishes the
connection. In the same manner, use of the signal name
YCE connects the nY7 output from the 74138 to the
IG input of the second 74139.

EXAMPLE 1: TTL MACROS
This section provides an example design using TTL
macros.

4-47

inter

AP-311

DANIEL E. SMITH
INTEL CORPORATION
2/27/87
1
A

5C090
TWO-STAGE DECODER
OPTIONS: TURBO=OFF
PART: 5C090
INPUTS:
A,B,C,D,E,EN1,EN2.EN3
OUTPUTS: YO,Yl,Y2,Y3,Y4,Y5,CSO,CS1,CS2,CS3.CEO,CE1,CE2,CE3
NETWORK:
INPUT (A,A)
INPUT (B,B)
INPUT (C,C)
INPUT (0,0)
INPUT (E,E)
INPUT (EN 1 , EN 1 )
INPUT (EN2,EN2)
INPUT (EN3,EN3)
OUTPUT (YO,YO)
OUTPUT (Yl, Yl)
PUTPUT (Y2,Y2)
OUTPUT (Y3,Y3)
OUTPUT (Y4,Y4)
OUTPUT (Y5,Y5)
OUTPUT (CSO,CSO)
OUTPUT (CSl ,CS1)
OUTPUT (CS2,CS2)
OUTPUT (CS3,CS3)
OUTPUT (CEO,CEO)
OUTPUT (CE1,CE1)
OUTPUT (CE2,CE2)
OUTPUT (CE3,CE3)
74138(A,B,C,EN1,EN2,EN3,YCS,GND,YCE,Y5,Y4,Y3,Y2,Yl,YO,VCC)
74139(YCS,D,E,CSO,CS1,CS2,CS3,GND,VCC)
74139(YCE,D,E,CEO,CE1,CE2,CE3,GND,VCC)
END$

292039-7

Figure 6. ADF File for Two-Stage Decoder Using TTL Macros

Sample Session

3. Invoke the LOC from the Main Menu by pressing

This session assumes familiarity with the iPLS II Logic
Optimizing Compiler (LOC). For detailed information
on the LOC, refer to Chapter 4 of the iPLS II User's
Guide. order number: 450196. Proceed as follows to
implement the TTL macro design shown here:
1. Use a standard ASCII text editor to create the ADF
shown in Figure 7 under the name DECODE.ADF.
2. Invoke the iPLS II Menu by entering:

4. Answer the LOC promts as follows:

.
Input Format?
File Name?
Minimization?
Inversion Control?
LEF Analysis?
Error Message File

IPLS 

4-48


DECODE 
y
N

Y



AP-311

The LOC then asks:

circuit. CS2 and CS3 are qualified by two additional
inputs (RD" and WR") to set or clear two latches. This
is a configuration commonly used in microcomputer
systems, where control signals are set and reset based
on the address and command signals but not on a data
value. A read to the port decoded by CS2 sets output
LCS2 (Latched CS2) high. A write to that same port
clears LCS2 low.

Do you wish to run under the above
conditions [YIN]?
Enter: Y
The LOC expands the macros and compiles
the expanded file to produce a JEDEC programming file (DECODE.JED), a utilization report file (DECODE. RPT), a minimized equation file (DECODE. LEF), and an error message file (DECODE. ERR). For tracability, a
file called DECODE.SDF is created to show
the expanded form of the ADF output by the
Macro Expander.
S. The LOC terminates execution with the following
message:

Figure 8 shows the ADF that implements the example
circuit. This is the same ADF used in Figure 6, with
the addition of several primitives and equations. The
data inputs to both latches are tied to VCC. When RDand the chip enable are both low, the respective clock
signal goes low. As RD- or chip enable go high, the
rising edge ofthe clock signal triggers the register, driving the output high.

LOC cycle successfully completed

Note that many Intel EPLDs do not support multiple
product terms for register clocks. Therefore, the clock
buffer primitive is driven by a macrocell configured as a
COIF (Combinatorial Output-Input Feedback). Control signals (Clear and Preset) for many EPLDs also
support only one product term. In this case, however,
the NOR gate driving the clear input to the RONFs
can be minimized to a single p-term. Thus a low on
WR' and chip enable clears the respective latch to logic
O. (The intermediate macrocell for the Read function
can be omitted for EPLDs that support two p-terms on
register clocks.)

You can examine the LEF file to see the minimized
form of the design. The LEF shows the EPLD primitives used to implement the design. Macro calls are not
shown. If you wish, ydu can also use LPS (Logic Programmer Software) to program a part.

EXAMPLE 2: MIXING MACROS AND
EPLD PRIMITIVES
This final example uses TTL macros together with
standard EPLD primitives.

The connections between the TTL macros and the
EPLD primitive are made by assigning the appropriate
names to the input and output nodes. The CS2 and CS3
signals from the first example are no longer outputs,
but are simply inputs to equations that feed the LCS2
and LCS3 RONF primitives.

Circuit
The example circuit here is the 74138 macro used in
example 1 with two of the outputs routed through additional combinatorial logic and RONF (Registered Output - No Feedback) primitives. Figure 7 shows the

4-49

AP·311

A
B

C
74138
ENl
EN2
EN3

YO
Yl
Y2
Y3
Y4
Y5

YCS
YCE
CEO
CEl
CE2
CE3

0

E

CSO
CSl

RO·-----r;--------.-i

>---.-SET2 C

>-......-SET3C

>-----LCS2

WR' -

.....-+--1-1

>---LCS3

292039-11

Figure 7. Schematic of Decoder Circuit with Latched Outputs

4-50

inter

AP-311

DANIEL E. SMITH
INTEL CORPORATION
2/27/87
1

A

5C090
DECODER WITH TWO LATCHED OUTPUTS
OPTIONS:
TURBO-OFF
PART:
5C090
INPUTS:
A,B,C,D,E,EN1,EN2,EN3,RD*,WR*
OUTPUTS,
SET2c,SET3c,VO,Vl,V2,V3,V4,V5,CSO,CS1,LCS2,LCS3,CEO,CEl,CE2,CE3
NETWORK,
INPUT (A,A)
INPUT (B,B)
INPUT (C,C)
INPUT (0,0)
INPUT (E, E)
INPUT (EN1,EN1)
INPUT (EN2,EN2)
INPUT (EN3,EN3)
OUTPUT (VO,VO)
OUTPUT (Vl, Vl)
OUTPUT (V2,V2)
OUTPUT (V3,V3)
OUTPUT (V4,V4)
OUTPUT (V5,V5)
OUTPUT (CSO,CSO)
OUTPUT (CS1,CS1)
OUTPUT (CEO,CEO)
OUTPUT (CE1,CE1)
OUTPUT (CE2,CE2)
OUTPUT (CE3,CE3)
74l38(A,B,C,EN1,EN2,EN3,VCS,GND,VCE,V5,V4,V3,V2,Vl ,VO,YCC)
74l39(VCS,D,E,CSO,CS1,CS2,CS3,GND,YCC)
74l39(VCE,D,E,CEO,CE1,CE2,CE3,GND,YCC)
RD _ INP(RD*)
WR _ INP(WR*)
LCS2 - RONF(VCC,SET2,CLR2,GND,VCC)
LCS3 - RONF(VCC,SET3,CLR3,GND,VCC)
SET2 - CLKB(SET2c)
SET3 - CLKB(SET3C)
SET2c,SET2c _ COIF(ST2,YCC)
SET3c,SET3c - COIF(ST3,VCC)
EQUATIONS,
ST2 _ RD + CS2;
CLR2 = I(WR + CS2);
ST3 - RD + CS3;
CLR3 - I(WR + CS3);
ENDS
292039-12

Figure 8, ADF file for Decoder with Latched Outputs

Sample Session
To implement this ADF in an actual session. follow the
steps described for Example 1. sUbstituting the name
LDECODE for DECODE. iPLS II produces a JEDEC
programming file (LDECODE.JED). a utilization re-

port file (LDECODE.RPT). a minimized equation file
(LDECODE.LEF). and an error message file
(LDECODE.ERR). For traceability. a file called
LDECODE.SDF is created to show the expanded form
of the ADF output by the Macro Expander.

intJ

APPLICATION
NOTE

AP-312

October 1988

Creating Macros
for EPLD Designs

DANIEL E. SMITH
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292040-002
4-52

inter

AP-312

By following the macro file format described in this
note, users can also create their own proprietary macros with an ASCII text editor. These macro files can
then be stored in user-defined libraries by using Intel's
Macro Librarian software. User-defined macros can be
called from ADFs created by a text editor or by schematic capture software that supports user-defined symbols and that outputs in ADF format. User-defined
macros can optimize development of EPLD designs by
modularizing the design process and by allowing the
design process to proceed at a higher level than with
EPLD primitives alone. iPLS II support for user-defined macros (see in Figure I) includes the following:
• MLIB, the optional iPLS II Macro Librarian for
creating macro libraries from individual user-defined 'macro files.
• a Macro Expander in the LOC that expands macro
calls in ADFs with the contents of the corresponding macros from libraries.

INTRODUCTION
The iPLS II (Intel Programmable Logic Software II)
Logic Optimizing Compiler includes a Macro Expander that supports the use of macros in EPLD designs.
These macros can include TTL and EPLD custom
macros available from Intel, or proprietary macros developed by a user. This application note shows how to
create user-defined macros and how to build macro libraries with Intel's Macro Librarian, an optional software package for use with iPLS II. A design example
also shows creation of a user-defined macro and its use
in an ADF (Advanced Design File). Detailed information on using the TTL Macros in iPLS II ADFs are
described in a companion application note: AP-311
"Using Macros in EPLD Designs", Order Number:
292039. This application note concentrates on creating
macros; it assumes that you have read and understood
the discussion on using macros in AP-311.

This application note describes how to create macro
files, store them in libraries with MLIB, and shows how
to call them from ADFs created by a text editor. For
information on creating user-defined macro symbols
with schematic capture packages, refer to the appropriate
manual for the schematic capture package you are using. SCHEMA II-PLD available from Intel supports
user-defined symbols and outputs in ADF format.

OVERVIEW
iPLS II allows designers to include macro cans in design files to implement common circuit functions. Macros calls are subsequently expanded by the LOC (Logic
Optimizing Compiler) into the ADF network and/or
equation entries required to perform the desired functions. Macros can be connected together or used in conjunction with standard iPLS II EPLD primitives.

SCHEMATIC
CAPTURE

I-----

i
SYMBOL
LIBRARY
iPLS II LOC

TEXT
EDITOR

ADF

r----

I"'"

~

MACRO
FILES

I"'"

1--+

MLiB

ESPRESSO
MINIMIZER

FITIER

r----

JEDEC
FILE

f

MACRO
LIBRARIAN
TEXT
EDITOR

MACRO
EXPANDER

-

~

MACRO
LIBRARIES
-T

-

t...

I+- TIL.LlB
EPLDMAC.LlB
USER - DErIN~D (·.LlB)
292040-1

Figure 1. Macro Support for iPLS II
4-53

AP-312

(SCHEMA II-PLD is based on SCHEMA II from
Omation, Inc. The Intel EPLD Design Manager, also
available from Intel, allows existing SCHEMA II users
to design with EPLDs and macros.)

16207 (A,B,C,D,E,F,U,Y,W,X,Y,Z)
16207 (B,D,A,R,Z,U,W,C,F,X,E,Y)
16207 (Z,Y,X,W,Y,U,F,E,D,C,B,A)

MACRO FILES

Note that this first line of the header forms the template used to call the Macro from the ADF. The Macro
Expander connects ADF nodes in the macro call to
1/0 signals in the macro file on the basis of positioll,
not on the basis of node name.

This section describes iPLS II macro files. User-defined
macro mes must follow'the guidelines presented here to
be successfully processed by the Macro Librarian
(MLIB) and expanded by the iPLS II LOC Macro Expander.

The second line in the header specifies defaults for inputs (VCC or GND) in cases where those signals are
left unconnected. The DEFAULT: line must be included in the macro definition file, even when no defaults
are used in the ADF. The keyword DEFAULT: is the
first entry in this line. The default values for all signals
follow immediately and are enclosed in parentheses. Input defaults may be YCC or GND. The position of the
default value corresponds to the signal listed in the previous line.

Macro filenames follow DOS conventions. It is recommended that macro filenames end with the extension
.DEY, which is the default for MLIB. Only one macro
can be contained in a macro file. Macro files are comprised of three sections:
• Header
• Network Section
• Equation Section

Defaults for outputs are blank, but a comma (,) must be
present (place holder) for each output signal except the
last. For example, the 16207 black box contains six inputs (A through F) and six outputs (U through Z). The
first two lines for this macro might be:

All macro files must end with the literal "ENDEF".
Figure 2 shows a sample macro file for a proprietary
part (16207), a "black box" containing random logic.

16207 (A,B,C,D,E,F,U,Y,W,X,Y,Z)
DEFAULT: (GND,GND,GND,YCC,YCC,YCC"",,)

16207(A.B.C.D.E.F.U.V.W.X.Y.Z)
DEFAULT,(GND.GND.GND.VCC.Vcc.Vcc ..•••• )
EQUATIONS,

U _ I(A • B);
I(/E • A * 6);
W _ 1(0 • C * A • IE);
x'- I ( l D ' E);

Defaults for inputs A through Care GND; defaults for
inputs D through F are YCC. Defaults for the outputs
are not specified, but the comma denotes the positions
for those signals.

v.

Y _ I(F • 0 • A);

Z _ F •

/E;

ENDEF

Defaults should be chosen with care. Clears, Presets,
Loads, etc. should be disabled in most cases. Enables
should be enabled. Input defaults can also be left blank
as long as those inputs are connected to nodes in the
ADF that calls the macro, but it is recommended that
they be specified in the macro file.

292040-2

Figure 2_ Sample Macro File for
"Black Box" (16207.DEV)

Header
Headers for macro files contain two lines. The first line
includes the name of the macro function and a list of
inputs and outputs for the macro. The second line contains defaults for the device.

Network Section

The name of the macro can be a device number (16207,
83546, etc.), function name (ADDRCNT, CMDLO,
etc.), or any name up to eight characters long. No
spaces or comments precede the name.
Inputs and Outputs follow immediately after the macro
name and are enclosed in parentheses. 1/0 signal'
names may be up to eight characters long, but may not
contain pin numbers, For user-defined macros, signals
may be listed in any order desired. For example, any of
the following entries are legal:
4-54

The NETWORK: section lists the EPLD primitives
used to implement the desired functions. The Network
Section follows ADF syntax rules, As far as possible,
the macros should be implemented in equations to eliminate concern about feedbacks and output enables. In
the case of a circuit that requires macrocell registers,
the feeback-only form of the primitive should be used
so that the Macro Expander can make the correct pin
connections. The following example shows this:
OUT! = NORF (INd,CLK,GND,GND)

inter

AP-312

During processing, the Macro Expander connects the
feedback to an output (if necessary) and supplies the
required output enable node name. The Macro Expander also eliminates unneeded Network and Equations
entries if they are not used by an ADF.

MACRO LIBRARIAN
The Macro Librarian (MLIB) is an optional software
package that combines individual macro files into macro libraries. These libraries are in tum used by the LOC
Macro Expander. MLIB can be invoked from the command line, from command files, or from a combination
of both. Figure 3 shows a block diagram of the Macro
Librarian.

If no network entries are required (i.e., a macro implemented entirely in equations), the entire Network section may be omitted, including the keyword NETWORK:. In many cases, equations alone can implement the desired functions.

Syntax for MLIB command lines is as follows:
MLID

Equations Section

[-options

1

[@cmdfile 1 [filel file2 •••

1


-d

directory. Displays directory information for
the library being created.
-v
verbose. Print status during processing. When
not specified, status messages are suppressed.
-I lib
list. Lists the contents of existing macro library to console. This option may not be used
while building a library.
-0 lib
name of the target macro library.
MACRO. LIB is the default when no name is
specified. TTL.LIB, EPLDMAC.LIB, and
INTEL. LIB are reserved for Intel libraries
and may not be used.
-s string include version stamp in macro library. The
version string can be up to 7 characters long.
"Vl.OO" is the default stamp.

The EQUATIONS: section lists the Boolean equations
for the desired functions and follows ADF syntax rules,
with one exception; intermediate equations are not permitted in macro files. If no equation entries are required (i.e., a macro implemented entirely in the Network Section), the entire Equation section may be omitted, including the keyword EQUATIONS:.

Comments and White Space
Comments can be placed anywhere in a macro file except before the name and signals on the first line. Comments must be enclosed in percent signs, as follows:
% THIS IS A SAMPLE COMMENT %

White space can appear on any line except the first two
lines.

TEXT
EDITOR

r-+ COt.lt.lAND
FILE

TEXT
EDITOR

-+

t.lACRO
FILES

T
-+

-

t.lLlB

.L.

....

t.lACRO
LIBRARY

-

LIBRARY
LISTING
292040-3

Figure 3. Macro LIbrarian Block Diagram

4-55

Ap·312

-c string

include copyright string in' macro library.
The copyright string can be up to 61 characters long and, if blanks are used, must be
contained in quotation marks, for example,
"texta textb".
@cmdfile name of command file. The command file
can iIiclude options and macro filenames.
The @ symbol must precede the filename.

"macro r I brary name "
-v
-s Vl.50 " version number"
-c "Copyright (e) Date. Your Company .. Your Name"

-0 PROJA. LIB

S copyright Information"
-d "

"

display directory"

Include the following macros"

INPUT.DEV
7487.DEV
14151.DEV

filel .. " name of device files to be included in the
macro, library. Separate files by spaces.

OUTPUT.DEV
7408.DEV
74138.DEV
74139.DEV
74157.DEV
74251.DEV

292040-4

Figure 4. Sample Command File for MLIB

For example, the following command line:

The command line to process the file shown in Figure 4
is as follows:

MLIB -v -s 2.00 -0 USER.LIB @USERLIST 
creates a library called USER.LIB that includes all the
individual macro files contained in the command file
USERLIST. MLIB displays status messages as it processes the macro files in USERLIST (-v). The library is
created as version 2.00 (-s).

MLIB @SAMPLE 
where SAMPLE is the name of the command file.
To list the contents of PROJA.LIB after creation, invoke MLIB as follows:
'

Macro library filenames follows DOS conventions and
should end with the extension .LIB to be recognized by
the Macro Expander. TTL. LIB, EPLDMAC.LIB, and
INTEL.LIB are reserved and may not be used.

MLIB -1 PROJA.LIB
This command line lists the macros in PROJA.LIB to
the screen. The DOS file redirection capability can also
be used to create a disk file listing the contents of macro
libraries. For example:

USERLIST is the name of the command file and must
be preceded by the @ symbol. The command file is
simply an ASCII,text file that can be modified to con-

tain any number of macros desired. MLIB processes
the entire list of macros on each invocation. To add a
new macro to an existing library, add the name of the
macro to USERLIST, and create the new library by
entering the command line shown above. Command file
names follow DOS conventions. MLIB supplies a .DEV
extension if no extension is specified. MLIB searches
first in the current directory, then along the DEV envi-'
ronment,variable, and finally along the PATH environment variable for the files.
In order to connect inut and output primitives, the files
INPUT.DEV and OUTPUT.DEV must be included in
at least one of the libraries. These files are contained in
the TTL macro library.

MLIB -1 PROJA.LIB > PROJA.DOC

SAMPLE SESSION: COMMAND
DECODER USING MACROS
Decoding logic is one common function implemented
by programmable logic devices. The target circuit fot
this example is a device that decodes microprocessor
command signals in selected address ranges. The target
application and decoder requirements are as follows:
• The target application is a 16-bit microcomputer
system with I-Megabyte of memory and about two
dozen I/O ports.
• The memory is divided into shared memory Qower
512K bytes) and Ipcal memory (upper 512K bytes).
Shared memory resides off the processor board and
requires active low memory command signals. Local
memory resides on-board and requires active high
memory command signals.

Figure 4 shows a sample MLIB command file that includes options, the library name, and the names of seven macro files to be included in the library in addition
to the INPUT and OUTPUT macros. The format of
the command file is free form. Note that comments can
be included in the command file and must be contained
within percent (%) signs.

• I/O ports are also split between on-board devices
requiring active high signals and off-board devices
requiring active low signals. I/O devices between
the address range FOOO-FFFFH are on-board; devices below that range (OOOO-EFFFH) are off-board.

Note that the -1 option cannot be included in an MLIB
command file; it can only appear on the command line.
The -1 option lists the contents of existing libraries; it
does not list library contents while building a library.

4-56

intJ

AP-312

• AU interrupt requests are resolved by an on-board
interrupt controUer. Therefore, only an active high
on-board interrupt acknowledge signal is needed.
• On-board control signals are always high or low,
never three-stated. Off-board control signals are
three-stated when not being used to execute a bus
cycle. An external bus arbiter accepts a request signal from the command decoder and, after gaining

control of the bus, sends address enable and command enable signal~ back to the command decoder.
Figure 5 shows a block diagram of the application, including the target EPLD design. The three functional
blocks to be included in the EPLD are highlighted (not
shaded).

OFF- BOARD
SYSTEM BUS
ADDRESS AND
DATA BUS

CPU

292040-5

Figure 5. Block Diagram of Target Circuit and Application

4-57

AP-312

Creating the Macro

Building the Library

Figure 6 shows a schematic diagram for the active low
command decoder implemented with OR gates (low inputs enable the outputs; high inputs disable the outputs). Figure 7 shows the macro file that implements
the circuit (CMDLO.DEV). This file was created with
an ASCII text editor. Used as is, it provides the active
low outputs for the design. With inputs RD, WR, and
INTAIN inverted, it also provides the active high outputs for the design. This design uses CONF primitives
to implement the three-state outputs in the macro. As
an alternative, equations alone could have been used
with the CONFs included in the ADF.

Use your text editor to create an MLIB command file
that includes CMDLO.DEV, INPUT.DEV, and OUl'PUT.DEV. The following example shows a sample
command file named MACLIST.
-v % show status %
-c "1987, AP-312 Sample Macro Library"
-0 AP312.LIB
-d % show the list %
% include the following macros %
CMDLO.DEV INPUT.DEV OUTPUT.DEV

;::=:+:::f". . . .

RD __

Invoke the Macro Librarian with the following command line:

MRD

MLIB

The Macro Librarian processes the three macro files
and stores them in a user library named AP312.LIB.
The library contains the copyright statement "1987,
AP-312 Sample Macro Library". When processing is
complete, MLIB returns control to DOS.

MWT

lOR

MIO:=~=~~_;
eMDEN

lOW

INTAIN - - - - - - - - H

INTA

@MACLIST

Creating the ADF
Figure 8 shows a schematic diagram for the target
circuit. Figure 9 shows the ADF for the circuit (COMCODE.ADF), which invokes both instances of the
CMDLO macro and contains equations used to enable
the decoders under the proper conditions. The ADF
signal named ONBEN (On-Board Enable) enables the
active high decoder). The AEN (Address Enable) input
to the on-board decoder is left unconnected. The default (always enabled) will be used.

AEN-------~

292040-6

Figure 6. Schematic Diagram of
Command Decoder

CMOLO(MIO.RO.WR.INTAIN.CMOEN.AEN.MRO.MWT.IOR.IOW.INTA)
OEFAULT,(GNO.VCC.vCC.VCC.GNO.GNO ••••• )
NETWORK,
MRO = CONF(MROc.AEN)
MWT ~ CONF(MWTc.AEN)
lOR = CONF(IORc.AEN)
lOW = CONF( IOWc.AEN)
INTA = CONF(INTAIN.AEN)
EQUATIONS,
MRDe m /MIQ + RD + eMDEN;
MWTc - IMIO + WR + eMDEN;
lORe - MIO + RD + eMDEN;
lOWe ... MIO + WR

+ CMDEN;

ENOEF

292040-7

Figure 7. Macro File for Command Decoder (CMDLO.DEV)

4-58

inter

AP·312

NINT

INTAIN-

MID

MilO-

OFF- BOARD
DECODER

INTA
MRD

NRD

RD-

MWT

NWR

WR·

lOR
lOW
Vee

MIO
RD
WR

t---+--l::> MRDC·
t---+--l::> MWTC·
t---+--l::> IORC·
t--,......+--l::> IOWC·

CMDEN·r:>--------+--rr+---~
AEN1~~------~~~~~------~

AF
AE~L-r-~~~~~-+_-~Hr~
ADL....o~'--_

AC
NMIO

NA13
OFFBDEN·

NUPPER
292040-8

Figure 8. Schematic Diagram for COMCODE.ADF

4-59

AP-312·

DANIEL E. SMITH
INTEL CORPORAT ION
417187
1

A

16209-001
COMMAND DECODER
OPTIONS,
TURBO-ON
SCD90
PART,
INPUTS,
MID, RD, WR, INTAIN, CMDEN, AEN1, A13, AF, AE, AD, AC
OUTPUTS, MRD, MWT, lOR, lOW, INTA, MRDC, MWTC, 10RC, 10WC, OFFBDEN
NETWORK,
INPUT(MIO,MIO)
I NPUT(RD, RD)
I NPUT(WR, WR)
INPUT(INTAIN,INTAIN)
INPUT(CMDEN,CMDEN)
INPUT(AEN1,AENl )
I NPUT(A 13 ,A13)
INPUT(AF,AF)
INPUT(AE,AE)
INPUT(AD,AD)
INPUT(AC,AC)
OUTPUT(MRD,MRD)
OUTPUT(MWT ,MWT)
OUTPUT( 10R,IOR)
OUTPUT( 10W,IOW)
OUTPUT(INTA,INTA)
OUTPUT(MRDC,MRDC)
OUTPUT(MWTC,MWTC)
OUTPUT( 10RC, 10RC)
OUTPUT( 10WC, 10WC)
CMDLO(MIO,RD,WR, ,CMDEN,AEN1,MRDC,MWTC, 10RC,IOWC,) % OFB %
CMDLO(M 10,NRD ,NWR ,N I NT ,ONBEN, VCC ,MRD,MWT, lOR, lOW, INTA) % ONB %
OFFBDEN
OFBEN
ONBEN
NRD
NWR
NINT
NMIO
NUPPER
NA13

_ CONF(OFBEN,VCC)
_ NOR(OF1,OF2,OF3,OF4)
- NOR(ON1,ON2,ON3,ON4)
a
NOT(RD)
_ NOT(WR)
_ NOT ( INTAIN)
_ NOT(MIO)
_ NOT(UPPER)
_ NOT(A13)

EQUATIONS,
UPPER
ONI
ON2
ON3
ON4
OFI
OF2
OF3
OF4

_
_
_
_
_
_
_
_

(AF • AE • AO • AC);
(MID' A13 • NRD):
(MIO • A13 • NWR);
(NMIO • UPPER' NRD),
(NMIO • UPPER' NWR):
(MID' NA13 • NRC):
(MID' NA13 • NWR):
(NMIO • NUPPER • NRD):
(NMIO • NUPPER • NWR),

ENDS

292040-9

Figure 9. ADF for COMCODE.ADF
OFFBEN (Off-Board Enable) requests permission to
access the off-board bus from the external bus arbiter.
The bus arbiter enables the off-board decoder via
AENI (Address Enable 1) and CMDEN (Command
Enable). CMDEN allows the appropriate signal to go
high or low, and AENI causes the outputs to independently enter or exit a high impedance state (three-state).

Note the same name is used for both nodes of each
INPUT and OUTPUT macro call. Use of the same
name ensures proper connection when the Macro Expander eliminates redundant primitives (for example, a
CONF feeding another CONF).

4-60

intJ

AP-312

Compiling the Design

The LOC then asks:

Proceed as follows to compile the ADF.
1. Include AP312.LIB in the IPLS environment variable. From the DOS command prompt, type:
SET IPLS=C:\IPLSII\AP312.LIB; ... 
For user-defined macro libraries that are regularly
accessed, the IPLS variable can be set in an
AUTO EXEC. BAT file.
2. Invoke the iPLS II Menu by entering:
IPLS 
3. Invoke the LOC from the Main Menu by pressing
.
4. Answer the LOC prompts as follows:
Input Format?

File Name?
COMCODE 
Minimization?
Y
Inversion Control? N
LEF Analysis?
Y
Error Message File COMCODE.ERR 

Do you wish to run under the above conditions
[YIN]?

Enter: Y
The LOC expands the macros and compiles the
expanded file to produce a JEDEC programming file
(COMCODE.JED), a utilization report file
(COMCODE.RPT), a minimized logic equation file
(COMCODE.LEF) and an error message file (COMCODE. ERR). For traceability, a file called COMCODE.SDF is created to show the expanded form of
the ADF output by the Macro Expander.
S. The LOC terminates execution with the following
message:
LOC cycle successfully completed
You can examine the LEF file to see the minimized
form of the design. The LEF shows the EPLD primitives used to implement the design. Macro calls are not
shown in the LEF. If you wish, you can also use LPS
(Logic Programmer Software) to program a part.

4-61

Tools for Optimizing PLD Designs
AJanJ. Coppola
Tool Architect
Intel Corporation
MIS EY2-11
5200 HE EJam YOUllg Pkwy.
Hillsboro, OR 97123
(503)681-2177

In the modeling area, extensive simulations must occur before
and after the device is built, as each device is custom crafted.
FInally, in the CAD tools area, a highly functional, but hard to use
set of tools gtude and control the whole process. The too15 are
the best In terms of functionallty, but the worst in terms of cost
and ease of use.

Introduction:

The purpose of this paper is to describe a design methodology for
Programmable LogIc Devices(PLD's) and to survey current PLD
optimIzation techniques.
1. Penpectille: Where do PLO'5 fit in?

The job of ASIC vendors in the next ten years is to make the
Custom/Serm·Custom problems disappear or become acceptable
to the logIC deSIgner of the next generation. The facts are clear.
Without advanced tools which automate much of the logic
.
deSIgner's work, the Custom/Serm-Custom approach only works
for large scale,large volume or special purpose devices. Silicon
compIlers and other Custom/Semi'Custom design methodologies
are working hard to overcome the Inherent problems of this type
of deSIgn.

The. use of Programmable LogIc Devices(PLD's) represents a

mIddle ground In logIc desIgn. The two common approaches to
logic Implementation in today's market are Board Design
methods(bwldmg a solution from a selection of pre-fabricated
standard parts - 'ITLJSSl/MSI) and Custom/Semi-Custom design
methods(fabricating a custom logIc chIp to solve the problem at
hand, arldlll&n buildini a much simpler boardl.
With the Board Design approach, PCB's carry the
fruIt of a desIgner's labor to the customer. Many Ilttle black boxes
and other elecmcal CIrcuit components make up the brunt of a
PCB's load. Many times there are large Islands of functionallty to
be connected together VIa encodmgjdecodIng and timIng cirCUItS.
The Islands of funCtIonalIty (I.e. rmcroprocessor, mIcro controller,
RAM, EPROM, trans Clever, etc.) all have different protocols, and
all speak dIfferent languages at different speeds.

The use of PLD's in a deSIgn is a compromise between the
fleXIbility of a Custom/Semi-Custom design, and the standard
Board deSIgn methodolgy.
The defInition of PLD whIch I am USIng for the purposes of thIs
paper IS very ieneraL A Programmable Logic Device IS any
device, whIch can be programmed by the user, to realize a chunk
of combinatorial or sequentIal logIC. A subset of the most
popular, or newest types of PLD's are: PAL's, PLE's(Monolithic
Memories), EPLD's(lnte~ Altera), EEPLD's(Lattlce), FPLA's,
FPLS's(SIgnetics), LCA's(XIlInx), and ERASIC's(Exel). All
except the last two are based on some form of twolevel(AND/OR} regIstered array logIC. I WIll mainly be concerned
Wlth two·level array logic deVlce5.

lntegraung the ITJaJor devices of a board together Involves much
"glue" logIC. The typlcforgan's mverslOn, In AND/OP type PLD aIchIteClures. With
InverSIOn controlm the I/O mao ocells. reier; to loglcallv In"ertmg
an output signal phase m such a ""ay that the number of p-terms
IeallZlng the complement iunctIon IS less thar, t.he ongmal
funcoon. ThiS can save the user from an un-solvable p-term fItung
problem due to too many p-terms when usmg one sense of an
equation. F'or deVices \"Ith Single output macfocell:.lIl.e PALs.
and EPLDs, thecomplement oi the smgle output equatIOn 15
computed and then mlfJlffilZed. The sense of the equation With
the least nurc.ber oj p-terms 15 then the one that IS unplemented
In the deVice lmder programmmg.
Fitting and Pin Assignment
The fltung and pin assignment problem refers to compiling a
deSign fIle. and haVIng the compiler automatically choose those
delilce resources and pms that the user did not assign In the
deSign fIle. In the past. del'lce architectures have been Simple
er,ough and small enough 50 that flttmg and pm assignment were
not a problem for the user. NOlli. With mcreasIng Size, complexitY',
and non-homogeneity of the deVice al cllltecture. a heuristic GAD
tool, "Ihlch 15 lIke an automatic place and route tool, 15 a necesslt"
If a deVice architecture IS homogeneous 'Mth respect to ltructure
and lesources. fIttmg 15 not a problem. a5 there 15 no contentl>Jn
feeT resources or placeme-flt of tho3e reSOlJfCE'5 Flttmg 15 a
problem when tllere are multiple clocks and tvpe S of cloCY.5 ..
muluple deVice sectJons(lIte quadraIltsl, "dr'lIng numbers 01 pterms per quadrant, produCl term sharIng and 5teermg. mput pms,
I/O maclocells 01 var:llng t'ipe5, or buned registers. The greatel
the nurnber and size of the features, the greater the fIttmg
problem. '.!,lahout a tool to help, the deSigner must do the fIttmg
by hand,leadJng '0 err»!·s and r.ot fmdmg an ,llo'-,'able fit.
Some of the large scale de"lces tlB.! eXhibit these problems are
Intel'51 Altera" 5I 5,::'1211 EP1210 I and 5C'180, EP18001 The IIttmg
and alttomatlt pm a5:1gnmfnt tools ot IPLDS reheue the user
from havmg to IjeallMth thIS pI oblem

Future PLD tools 'A/ill depend more arJd more on logiC
ITlIfUmlZatlOn. Just as a Iugh-Ie'lellanguage prograrnmer looks

4·64

3. Future PLD OptilDiziltion ',fools

Conclusion:

TIlls seCtIon descnbes new dlreCtlons lor PLD dellelopment
systems opttrruzatlon tools. Opttrruzatlon tools must be near
transparent to the user to get umversal acceptance. 01 the four
opttrruzatlon tools mentloned above, all but the FSM compiler tool
satlsfy that cntenon.

We have surveyed the reasons for, and components of PLD
development systems, With emphaSl5 on the Hardware
Descnption Languages, and optunizatlon methods 10 such
systems. The conclUSions of the survey are that the HDL's are
the essential cornerstone of any PLD system, and WIll control the
future dlreCtlons of any new PLD development tools. The second
conclUSion IS that two-level logiC rrururruzatlon, FSM compiler,
and automatlc fitting tools are the most unportant In the PLD
optlmlZlltlon area. Also, recent breakthroughs and public
aval1ablbty of heunstlc llllIlllIllZers pomt to mcreased use of such
tools. FiIW\y, future direCtIons, and an expanding market mdlcate
a Wide range of new tools will appear. The key emphasis W1Il be
on makmg them transparent to 'the user, who, when alliS said and'
done, knows how to deSign logiC best I

There are baslca\ly two types of opttrruzatlon tools which W1Il
appear 10 the PLD arena. The first type are tools which are
ported from, or mterfaced to the Custom/Serm-Custom
enVIronment The current logiC descriptlon and synthesIs tools of
silicon compilers and Custom/Serm-Custom CAD tools fit mto
this classificatIOn. The second type are new tools which W1Il
address the architecture-specifiC opttrruzatlOn Issues. The tools 10
this group W1Il use methods based on logiC opttrruzatlon and
expert·system techruques. These two methodologies W1Il be
applied to taking abstact speclflcatlons and reahzmg them
automatlca\ly mto multiple deVices, or 10 talang multlple abstract
specificatIOns and realizmg them 10 one deVice.

References
[1] R. Rudell and 'A. Sanglovanm-V'mcentelll, "ESPRESSO-MV:
Algonthms for Multlple Valued LogiC MlTllIlllZlltion", 10 Proc.
Cust Int Crrc. Conf.,IEEE, Portland, OR. May, 1985.

Portation of Custom/Semi-Custom Tools:
Available Ideas ready for porting to the PLD enVIronment down
the HDL path mclude lrnplementlng a subset of VHDL(VHSIC
Hardware Descnptlon Language)[S], and haVIng ttie complier
produce an EDlF(EleCtlomc DeSign Interchange Format) [6]
mtermediate format In this way, mterfacmg With other toolboxes
of any type W1l\ be easier. New deVice support W1Il also be easier,
given the genenc nature of VHDL. Usmg VHDL would also
standardize an HDL, and allow deSigners to learn one HDL
which W1Illast for a long lime. Also, PLD.tools which mterface
With the CU5tom/Serm-Custom toolset mvolV1ng board deSign,
testlng and manufactunng IS needed now, and IS bemg addressed
by the malor CAD vendors. Standardization, like VHDL and
EDIF will. eventually,lower the cost of the3e mterfaces ..

[2] M.R. Dagenais, V.K Agarwal and N.C. Rumm, "McBoole: A
New Procedure for Exact LogiC MlnlfIllZatlon", IEEE Trans. on
CAD, Jan. 1986, 229-238.
[3]1.1. Bartholomeus and H.D. Man, "Presto-lI: Yet Another
LogiC Mmrrl'llzer for Programmed LogiC Arrays", Proc. Int Symp.
Crrc, Syst, June 1985,58.
[4] R. Rudell, "Multlpl~Valued LogiC MlnlfIllZatlon far PLA

SyntheSIS", M.S. TheSl5, Umverslty of Cabfarma, Berkeley, 1986.
[5] V. D. Agrawal, ed.. "VHDL: The VHSIC Hardware
Descnptlon Language", IEEE DeSign and Test of Computers,
Apn~ 1986.

The new logiC rmmrmzatlOn algonthms, like Espresso, and new
state assignment tool3,IiI'e KISS[7] and STASH [81can be used 10
the PLD enVIronment The algonthms and methods of tools
InlloIVIng placement and routlng can be applied to the flttlng/pm
assignment problem. On the logiC syntheSIS Side, new tools
which combme expert·systems With multl-Ie'/elloglc opttrruzatlOn
can be applied to PLD deVIces which allow multi-level logiC to be
easllv unplementecl

[6] lP. Eunch. "A Tutonal IntroductIOn to the Electromc DeSign
Interchange Format", In Proc. of 23rd DeSign Automation
Conference, JuIv, 1986,321-333.
[7] G DeMlcheb, R.K. Brayton. and A. Sanglollanm·Vmcentelli,

"Optlmal State ASSignment for Fimte-State Machines", IEEE
Trans. on CAD, July, 1985, 269-285.

The key pOlnt,lITegardles5 of the actuallools from the
Custom/Berm-Custom arena winch are produCtlZed IS that the
U3er halle an essentlall" transparent '!lew of anI' new opturnzatlon
tool;

[B1 A. 1. Coppola. "An Implementatlon of a State ASSignment
Heunstlc", In Proc. of 23rd DeSign AutomatIOn Conference, July
1986, 64H49
'

Once a PLD IS manufactured, the funCtlonabl'J cannot be
changed. TIlls fact leads to the belief that tools can be created
which map logiC, which 15 too big or too slow, mto multIple
de'!lces by domg automatic logiC partJUomng. The converse
problem of flttlng multlple churu.s of commumcatlng logiC Irlto one
de,~ce mal' also be addJes3ed Tools to Ilt multiple state
machmes rota one de'~ce, or to partltlOn a schematic or FSM mto
tu'o or more de'IlCe3 IS a Ilrst step For example, the [lice
Exarnplel Flgw 831·31 has three small state machines, which are
Integrated 1010 one de'~ce and deSign flle. Expert-system3 can
capture the rules for partttlDmng, and the database of all allowable
deVices, "'hlie optmuzatJon techmques canmaJ..e the experts"stems "Jorl' as ','ell as, or better than a logiC deSigner

4-65

Dice Example Description

Th. Die. Example ShDWS th. useful"ess of logic minimizatiDn.
Figure 2 shows th. FSM Language(State MachinoFilel
.
repr.senlation of the Oico Example und., the iPlDS sy51om.
Figuro 3 shows the AOF cod. which resulted. as .. inlorm.diate
SloP. in the compilatiDn ProcfSS.

Probl.m: O.. ign a.circuit thaI will rO.II two dice. Push a switch 10
start th. dic. rDmng. Wh." the switch is released. a (ps.udol
random sel Df numbers will be displayed.
'
The .x....pl. is wrilll!n using th' FSM cDmpiler module of iPlDS.
This oxample is a mDdification of an .>lisling Application NOIo[AP219] design. which is written in AOF language.
Th. Oic. Example pseudo-randomly rolls iwo dice. The Dice
Example is cDn\pos.d of th .. e FSMs·. Th. firsltwD are essentially
up-counlers. which cDunl from on. II' six. using th. notatiDn grDuPs
Df Dn. Dr twD LEO·s. for .ach Df lour Dutputs. 10 reproseRlthe six
faces !,f a die. A PI.clure which indicales the LEO groupings by
listing .the !Output signal nam. nexllD th. LEO cDntrDlied by is
gIven on DIagram I. Th. groupings for bDth die aro id.ntical. and
:'
honce. li51ed nex110 each Dther

Th. target device. th. 5C060. has 18 '1/0 macrocells. but each
macroc.1I has Dnly .nough rDDm for 8 p-torms. Ther. ar. 11
.qUaliDnS thaI r.suh from th. Dice Example design. Four for .ach
die. to cDmrDI1ho LEO·s. and three frDm th. 51ate variabl.s of th.
Un.ar Feedback Shift Regi51er.
We pros.nl a b.lo.. and aft., minimizatiDn table. showing th. efIoCI
Df the mini,!,izalion and the automatic O.Morgan·s Inversion Slop.

it:

The third machine generales a shDn pseudD-randDm bil sequnce by
implem.nting a Unear Feedback Shift Regislor(LFSRI • with three
roglsters. The ps.udo-random bit sequ.nc.s from the LFSR are
used to add prDbabilistic transitions tD the up-counlor mod.1 of
each die. Th. implementation of th. LFSR is by s.tr&igh!
,
memorization of the sequence, by means of ttle state variables of an
up-counter.

Dice LED Encoding

Ib,2b
Id,2d
le,2c

•••••
.la,2a

•

Ie, 2e

p-torms lH.rms
before aItor
min

Equation

Inputs

min

Sv3.d
Sv2.d
Svl.d
2d.d

3
3
3
6

3
3
3
3

2o.d

G

2b.d
2a.d
Id.d
IC.d
Ib.d
la.d

6
6
6
6
6
6

,•
10
3
9
5
10

,2
2

2
3
4

4
6
3
4

4
1

A nec.ssary cDnditiDn 10 fit inlO th. 5C060 is thaI all of th. numbers
in th. la51 cDlumn be no more than 8. as there are nD more than 8
p-1erms cDnnecl.d 10 "II' macroe,II. This particular prob"m took 2
monut•• 1'1 CPU Ume Dn an 8MIlz PC/AT. Reducing these .qualions
by hand. evon fDr this simple .xampl•• would b. difficuh. The ne.d
for th. autDmatic minimizor is clear in this .xample. Without it. a
designer would either hav. 10 reduct the eqations resulting frDm th.
FSM languag. by hand, Dr nI'l us. an FSM languag. at all. and do
the whole d.sign using hanlkraft.d m.thods.

Id,2d
Ib,2b

Die I Signals: I a, I b, Ie, I d
Die 2 Signals: 2a, 2b, 2e, 2d
Figure I.

4-66

Dice Example
FSM language(SMF) Description

"

Slat. variables are used as oUIPuts to die.
Each state encodes the set of LEO's 10 light
10 realize that die value

"

Alan Coppola
Intel

Jul, 21, 1986

Pill No.: lasVegas

VIt.3.0
5C060
Roll a pair of die
LB Version 4.01, Baseline 21.1 4/9/86
PART: 5C060

STATES [la lb lc ld]
Reset
[0 0 0 0]
One
[1000]
Two
[0 1 0 0]
Three
[1100]
Four
[0 1 1 0]
Five
[1110]
Six
[0 1 1 1]

"
"

" No pins assigned:
.
Automme Pin Assignment and FlI1mg "

Com2 15 a pseudo-random coin which controls the
up-<:ounler transitions, so thaI the dice roll is
ps.udo-random

INPUTS: clkl, elk2, Go
OUTPUTS: 1a. 1 b, 1c, 1d, 2a, 2b, 2., 2d

l

Reset
II Go Then One
One
II Go.Coin2 Then Two
Two:
II Go.Coin2 Then Three
Three:
II Go.Com2 Then Four
Four:
II Go.Coin2 Then Five
Five:
II Go.Coin2 Then SIX
SIX.
II Go.Coin2 Then One

NENORK:
cUd = INP(elkl)
elk2 = INP(clk2)
Go = INP(Ga)
;ree term LFSR. implemented b, storing sequence
in S!ale vanables, which act as nipping coins

"

MACHINE: lFSR
CLOCK. clk2
STATES: [Cainl Coin2 Coin3]
se [000]
SI
[108]
S2
[110]
S3
[011]
S4
[1 01]
S5
[010]
S6
[0 0 1]

MACHINE Oie-./\olU

"
"

Duplicate of Dle_RoIU machine, except for
a dihrem die, using a differenl pseudo-random _om.

"

S!aIe equmons are:
Coin2 := Coinl
Coin3 := Coin2
Coinl := /(Coin2 lOr Coin3)

"so:
SI
SI'
S2
S2:
S3
S3:
S4
S4'
S5
S5:
S6
S6:

CLOCK _1k2
STATES:
Res.1D1I2
OneOie2
TwoDie2
ThreeDie2
FourDie2
FiueDie2
SixD.. 2
ReselDi.2·
II Go.Coin3
Dn.Dle2:
II Go.Coin3
TwoDie2'
II Go.Coin3
ThreeDie2.
II Go.Coin]
FourDie2.
II Go.Coin]
FiueDII2
II Go.Coin]
SixDII2'
II Go.Coin]

so

MACHINE: Oie_RoIU
CLOCK: elkl

ENDS

Figure 2.

4-67

[20 2b 2_ 2d]
[0000]
[1 000]
[0 1 0 0]
[1 1 0 0]
[0 1 1 0]
[1 1 1 0]
[0 1 1 1]
Then DneDie2
Then TwoDle2
Then ThreeDle2
Then FourD .. 2
Then Fi.eDle2
Then SixDi.2
Then DneDie2

inter
Dice Example'
Hardware Description Language(ADF)
AI.. Coppola
Intel
July 21. 1986
Pan No.: lilSVegilS
Ver.3.0
5COBO
Roll a pair of die
LB Version 4.01. BilSeline 27.1 4/9/86
SMV Version 1.01 BETA2 Baseline 26.1 4/3/86
PART: 5C060
INPUTS:
elkl. elk2. Go

X

Reset = la"lb"lc'ald';
One = 1a'lb'alc'ald';
Two = "'olb'lc"ld"
Three = hOlb'lc"ld';
Four = 1a'ol b'l c'l d"
Five = h'lbOlc"ld';'
Six = la'olbolc'ld'

.

X

elkl = INP(elkll
elk2 = INP(clk2)
Go = INP(Go)
X

Three term LFSR. implemented by storing sequence
in state variables. which act ilS flipping coins.
X

X
I/O's for State Machine "LFSR"
X
Coinl = NORF(Coinl.d. clk2, SNO, SNO)
Coin2 = NORFICoin2.d. clk2. GNO. GNO)
Coin3 = NORFICoin3.d, elk2. SNO. GNO)
X
I/O's for Stale Machine "Oie_RolI_l"
X
la. la = RORF(1a.d. clkl. GNO. GND. VCC)
lb, Ib RORF(lb.d, clkl. SND, GND. VCC)
Ic. lc = RORF(1c.d, elkl. GND. GND. VCC)
ld. Id = RORF(1d.d. clk1. SNO. SND. VCC)
X
I/O's for State Machine "Die_RoIU"
X
2a. 2a = RORF(2a.d. clk2. GND. GND. VCC)
2b. 2b = RORF(2b.d'. clk2. GND. SND. VCC)
2c. 2c = RORF(2c.d. clk2, GND. GND. VCC)
2d. 2d = RORF!2d.d. clk2. SND. GND. VCC)

=

EQUATIONS:
X
Boolean Equations for State Machin. "LFSR"

.

X

Current State Equations for "LFSR"
X
SO = Coinl"Coin2"Coin3';
SI = Coinl'Coin2"Coin3';
S2 = Coinl'Coin2'Coin3';
S3 = Coinl"Coin2'Coin3;
S4 = Co,," I'Coin2"Coin3.
S5 = Coinl"Coin20Coin3';
S6 Coinl"Coin2"Coin3;
X
SV Defining Equations for Stat. Machine "lFSR"

=

Coinl.d = SI.n + S2.n + S4.n;
Coin2.d = S2.n + S3.n + S5.n;
Coin3.d = S3.n + S4.n + S6.n;
X
Next State Equations lor Stat. MachIne "lFSR"
X
SI.n = SO;
S2.n = SI;
S3.n S2;
S4.n = S3;

=

X

X
Current Stato Equations lor "Die_RolLI"

X

NETWORK:

X

X

Boolean Equations lor State Machine "Die_Roll_I"

SV Dolining Equations lor Stale Machine "Die_Roll_I"

OUTPUTS:
h. lb. lc. ld. 2a. 2b. 2e. 2d

X

S5.n = S4;
S6.n = S5;

h.d = Dne.n + Three.n + Five n;
lb.d' = One n + Reset.n;
lc.d = Four.n + FiYe.n + Six.n;
Id.d = Six.n;
X
Next Siale Equations lor Slate Machme "Dio_RoILl"
X
One.n = Six a Go a Coin2 + One" (Go a Com2)'
+ Rosel' So;
Res.l.n = Res.1 • (Gor.
Throe.n = Thr., • (So' Coin2r + Two" Go " Coin2,
+ Three" Go • Coin2;
Four.n = Four' (Go' Coin2r
Five.n = Fivo • (Go' Coin2r
+ Four' Go • COln2,
Six.n = Six " IGo a Coin2r
+ Fi •• a Go " Com2;
X

Bool.an Equations lor Slat' Machin. "DI._Rol'-2"
X
X

Currenl Siale Equabons for "Oie_Rol'-2"
X
Re.etOie2 = 2a"2b"2c"2d"
OnoDie2 = 2aa2b'"2c"2d'; ,
TwoDie2 = 2a'a2b a 2c"2d',
Thre,Oie2 = 2aa2ba 2c'a2d',
FourOie2 = 2a'.2b"2c a 2d',
Fi.eDie2 = 2.'2b a 2ca 2d';
SixOie2 = 2.'a2b a 2c'2d·
X
'
SV Defining Equations lor Siale Machino "Oio_RolI_2"
X

2a d = OneDie2 n + ThrooDi.2.n + FivoDi.2 n,
2b.d' = OnoOi02.n + RosotOi.2 n,
2c d = FourOl02.n + Fi.eDie2.n + Si.o102.n;
2d.d = SixOie2.n;
X
~oxt

Sialo Equations lor Sial. MachIn. "Oio_RDI'-2"

On.Oi02.n = SixD,02 a Go " Coin3
+ OnoOi.2 a (Go a COln3),
+ Res.tOi.2 a Go a Coin3,
R.s.tO,.2.n = R.sotO,.2 • (Go" CDin3),;
Thr.eOi.2 n = Thre.0,.2 " (Go a Coin3"
+ TwoOi02 • Go " Coin3;
FourOie2 n FourOi.2 a (Go a CDin3"

=

... ThreoDio2 • Go • Coin3;

F,.eOi.2 n = FiveOi.2 a (Go a CDin3)'
+ FourDie2 a Go a COin3;
SixQl.2.n = SixOi02 " (Go a CDin3),
+ F1v.DI02 • Go " Com3,
ENO$

Figure 3,

4"68

Appendix

5

EPLD THIRD PARTY PROGRAMMING SUPPORT*
Company

Model

Type

Adams/Macdonald P11
Universal
Enterprises
(Promac)
Sprint Plus Universal
Data 110

Oigelec

Kontron

Module

Adaptor

Devices Supported

-

PA-1

5C031 , 032, 060

-

-

5C031 , 032, 060

29B

Universal LogicPack 303A-010 V.2
5C090,121
303A-011AV.7
5C031,032,060,5AC312
V.4
303A-011 B (PLCC) 5C060

40

Universal

-

-

Chipsite (PLCC)

5C031,032,060, 090, 121
5C060, 090,180

60A/H

Logic

-

-

5C031 , 032, 060

Unisite

Universal

-

Site 40
Chipsite (PLCC)

5C031 , 5C032, 5C060, 5C090,
5C121,5AC312
5C090, 180

PLO

-

-

5C031 , 060, 121

803-0P5

Logic

-

-

5C031 , 060, 121

EPP-80

Universal UPM/B
UPM/C

-

5C031 , 032, 060
5C031,032,060, 090, 121

803-LOC

Oliver Advanced
Engineering

Omni64

Universal

-

OM-S-20 LCC
OM-S-24 LCC

5C031
5C060, 090, 121

Stag

ZL30

Logic

-

5C031 , 032, 060

ZL30A

Logic

-

30A640

5C031 , 032, 060
5C031,032,060, 090, 121,180

-

-

5C031 , 060

-

5C031,032,060,090, 121

ZL33

Gang

PPZ

Universal ZM2200

·Claimed by the manufacturer to support the listed devices. Not qualified by Intel.

5-1

PLA TO EPLD REPLACEMENT
Already in wide use throughout the electronics industry are numerous different Programmable Logic
Devices. Many of these are PALs from MMI. Currently, two of Our EPLD products, the 5C060 and
5C031 can functionally replace most 24-pin and 20pin PALs, respectively. A third product, the 5AC312,
with its architecturally advanced features, can replace most designs using more complex PALs such
as the 20RA10, 22Y10, and 32V10.

SC031/SC032 As a 20-Pin PAL Replacement

- 100%
Compatible
10H8, -2
12H6,72
14H4, -2
16H2, -2
10L8, -2
12L6, -2
16L8, A-2, A-4
16R4, A-2, A-4
14L4, -2
16L2, -2
16R8, A-2, A-4
16R6, A-2, A-4
16P8, -2
16RP8, -2
16RP6, -2
16RP4, -2
16V8
These are
25 ns-45 ns PALS.

The 5C031
The 5C031 is a direct, drop-in replacement for most
20-pin PALs, although some PALs have an incompatible architecture.

The 5C060
The 5C060 is NOT a drop-in replacement for any 24pin PAL, though it cari functionally replace most. The
reason for this is that pin 1 is used as the main clock
on registered PALs and as an input on non-registered. Also, pin 13 is used as an OE line on some
PALs, and as an input on others. The 5C060, however, uses pin 1 as the left-half synchronous clock input and pin 13 as the right-half synchronous clock
input.

Functionally
Compatible

16R6A
16R4A
16L8A
16RP6A
16RP4A
16P8A
16R8A
16RP8A

These are
15 ns PALs.

SCOSO As a 24-Pin PAL Replacement

While that may not be a problem in some PAL designs, those designs that require clocking or inputs
on pins 1 or 13 will necessitate hardware modifications. In the case of the registered PALs; the connection to pin 1 must be rerouted to pin 13 and the
OE connected to one of the available inputs (if
used). hi this manner, the 5C060 can functionally
replace the PAL.

The 5AC312
The 5AC312 is a direct, drop-in replacement for the
20RA 10 as well as many of the other simple 24-pin
logic devices. The 5AC312 can also serve as a dropin replacement for most designs using the 22V10 or
32V10 devices.

Modified
Replacement

Functionally
Compatible

12L10
14L8
16L6
18L4
20L2
20L10
20L8
20RB
20R6
20R4
20RAlO

20L8A
20R8A
20R6A
20R4A

With hardware
modifications

These are
15 ns PALs.

5AC312 As a 24-Pin PAL Replacement
100%
Compatible

20L8
20R8
20R6
20R4
20RA10

5-2

100%
Compatible
(Qualified)

22V10
32V10
Dependent on the
number of product
terms used.

I

ORDERING INFORMATION
Intel EPLDs are identified as follows:
M

5

D

.'-.-1 '-.-I

C

'-.-I

X

X

I..

I

S

X

T

S

I..

)

)
Speed

Device

Technology
C -CHMOS
AC - Advanced CHMOS
Package Type
A

-

D

-

Hermetic, Type D (Cerdip) Dip

N

-

Plastic, Leaded Chip Carrier

CJ -

Hermetic, Pin Grid Array

Ceramic, J Leaded Chip Carrier

P

-

Plastic Dip and Plastic Flatpack

R

-

Hermetic, Leadless Chip Carrier

X

-

Unpackaged Device

+ 125°C)

A-

Indicates automotive operating temperature range (-40°C to

J -

Indicates a JAN qualified device, but is for internal identification purposes only. All JAN devices must
be ordered by M38510 part number. (Example: M3851 0/42001 BQB), and will be marked in accordance with MIL-M-38510 specifications.

L -

Indicates extended operating temperature range (- 40°C to
± 8 hrs. dynamic burn-in.

+ 85°C)

express product with 160

+ 125°C)

M-

Indicates military operating temperature range (- 55°C to

Q-

Indicates commercial temperature range (O°C to 70°C) express product with 160 ± 8 hrs. dynamic
burn-in.

T -

Indicates extended temperature range (- 40°C to

-

+ 85°C) express product without burn-in.

No letter indicates commercial temperature range (O°C to 70°C) without burn-in.

Examples:
QD5C060-45 Commercial with burn-in, ceramic Dip, 060 (600 gate) device, 45 nanosecond.
'On military temperature devices, B suffix indicates MIL-STD-883C level B processing.

5-3

Device feature Comparison

INPUTS
Dedicated
Maximum
Input Latches

5C031

5C032

5C060

5C09O

5C121

5C180

5CBIC

5AC312

5AC324.

10
18

10
18

4
20

12
36

12
36

12
60

8
16

10
22

12
36

Y

Y

Y

24

Y

1/0
Number
Tri-State
Programmable
Polarity

B

8

16

24

24

48

32

12

Y
Y

Y
Y

Y
Y

Y
Y

Y

Y

Y

Y

Y

y

y

y

y

y

MACROCELLS

8

8

16

24

28

48

8

12

24

REGISTERS
Number
Types

8

8

16

24

28

48

8

12

24

0

0

OfTf

OfTf

0

OfTf

OfTf

OfTf

OfTf

RSfJK

RSfJK

RSfJK

RSfJK

RSfJK

RSfJK

Y

Y

Y

Y

y
y
Y

y
y
y

y
y
, y

112

200

2

2

Y

Y

Y

Y

Buried Reg. S
Preload
By-Pass
Reset
Preset
PRODUCT TERMS
Number
Sharing
Variable Prod.
Term Distribution

4
Y
Y
Y
Y

Y
Y
Y

74

72

Y
Y
Y

160

Y
Y

y

240

Y

CLOCKS
Asynchronous
Clocking
Programmable
Clock Edges

TURBO BIT
(LOW POWER)

236

y.
y

480

394

y
Y

LOCALfGLOBAL BUSSES

SECURITY BIT

Y

y
y

2

2

Y

Y

2

Y

4

Y

Y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

y

5-4

ELPD CUSTOMER SUPPORT
Transmit/receive protocols supported are:

Hotline

ASCII
XMODEM
KERMIT
TELINK
Cyclic Redundancy on XMODEM

The Intel EPLD Technical Hotline is manned byapplication personnel from 8:00 a.m. to 5:00 p.m.
(PST) every business day. The number for the United States and Canada is 1-800-323-EPLD (1-800323-3753). Outside of the U.S. and Canada, contact
your local Intel Sales Office. The Hotline is provided
to assist with technical questions concerning Intel
EPLDs.

EPLD Customer Design
Support Center
Intel has a Customer Design Support Center to help
customers who are implementing EPLD designs.
Service includes answering questions, device selection assistance, and design partitioning as well as
limited prototyping, and product/design evaluation
and implementation. For more information on the
Design Support Center, contact your local Intel field
sales office.

BBS
Intel has a Bulletin Board System for registered iPLS
and iPLS II customers to electronically transfer information. Any registered person with a modem can log
onto the system. The current number is (916) 9852308. If your communication software supports file
transfers, you can receive utilities, software updates,
and the latest information on EPLDs via the Bulletin
Board.
Data format for the BBS is as follows:
Start Bits: 1
Stop Bits: 1
Data Bits: 8
300 or 1200 BAUD
Speed:

5-5

COMPATIBLE COMPUTERS FOR iPLDS II
A partial list of computers that have been verified to be software compatible with the Intel Programmable Logic
Development System (iPLDS II) is given below:
AT&T 6300 and 6300+
Compaq family of PCs (88, 86, 286, 386)
IBM AT
IBMXT
IBM XT-286
IBM Personal System II Model 30
.
HP Vectra
Sperry IT
Tandy 3000 HD
The IBM Personal System II Models 50, 60, 70, filnd 80 can run iPLS II (Intel Programmable Logic Software)

5-6

inter

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¢:u;e~~~

ILUNOIS

NEW YORK

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Intel Corp
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HuntsVIlle 35805

Su/te200

30092

Suite B 295

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Lane
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Tel (602) 869-4980

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Tel (602) 299-6815

ri(~~~!t~
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~:'x(~I~!~~~~
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~=51~~~1~~

0

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~~~b?:i~~

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inter
DENMARK

EUROPEAN SALES OFFICES
WEST GERMANY

ISRAEL

SPAIN

Intel"
Dornacher Strasse 1
8016 Feldklrchen bel Muenchen

Intel'
Abdim Industrial Park-Neve Sharet
PO Box43202
Tel-AvIv 61430

Intel
Zurbaran,28
28010 Madrid

+~ (~bOW~90992-O
FAX 9()4..3948

~ (Wr~2~98080

FINLAND

+~(~~04004
SWEDEN

Intel
HOhenzoilern Strasse 5
3000 Hannover 1

'"~

Ruosllantle2

00390 Helsinki

+~~~644

FRANCE
303
-en-Vvellnes Cedex

7000

+~ (~~1~/344081

ITALY
Intel'
Intel'
Mllanoflori Palazzo E

20090 Assago
Milano

Intel
Abraham Lincoln Strasse 16-18
6200 Wl8sbac\en
Tel· (49) 06121/1605-0
TLX 4-186183

+~~~1~ 824' 40 71
NETHERLANDS
Intel'

Intel

Intel
4, Quai des Etrorts
69321 Lyon Ceclex 05
+~ (3;:kN~ 784240 89

=AV~~=~:a

~:frso~!

+~ (~~~J34 01 00
SWITZERLAND
Intel
ZU9flchstrasse
8185 Wlnkel-Ryah bel Zuench

i~~~5~V?60 62 62

+~(~~2~4071111

UNITED KINGDOM

NORWAY

Intel'

Intel
Hvamvel8n 4-PQ Box 92
2013 Skletten

m!fJo~A 842420

~=O,,:::a~IHShlre SN3 1RJ
H'''i~i1J 696000

EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA

we:ST GERMANY

Bacher ElectronICS G m b H.
Rotenmuehlgasse 26
1120Wien
Tel. (43) (0222) 83 56 46-0
TLX 131532

NETHERLANDS
Koning en Hartman

~~'r~~~

Tel (31) 15609906
TLX 38250

UNITED KINGDOM
Accent ElectroniC Components Ltd
Jubilee House, Jubilee Road
Letchworth, Herts SG61TL

+~(~~2) 686666

BELGIUM

~~a:~o:'rntGmbH

NORWAY

~~w~nab~::ms

lnelco Belgium S A
Av des CrOIx de Guerre 94
1120 Bruxelles
~skrwsenlaan, 94
1120 russet
+~!~~;) 216 01 60

Bahnhofsttasse 44

Nordls!<. Elektronlkk (Norge) AjS
Postboks 123
Smedsvlngen 4
1364 Hvalstad

Western Road
Bracknell RG121RW

~~1~~~¥~879
Jermyn GmbH
1m Dachsstueck 9

DENMARK

~~~:~.Jf508.0

ITT-Muitlkomponent
Navertand 29
2600 Glostrup

Metrologl8 GmbH

+~(~~2456645

~~I~iI:::~7t9

+~(~~1~G8042.o

+~(W~)846210
PORTUGAL

Dotram
Avenlda Marques de Tomar, 46-A
1000 Lisboa

+~~~VJJ) 73 48 34

+~.(~7~) 55333

Jermyn

~~~=
Sevenoaks
KenfTN145EU

+~.(~1~~32) 450144
MMD
Unit 8 SouthView Park

SPAIN

FINLAND
OV FlntroOicAB
Melkonkatu 24A
00210 HelSinki

~~I~~! 6926022

Proelectron Vertri8bs GmbH
Max Planck Strasse 1-3
6072 Drelelch
Tel (49) 06103/3040
TLX 417903

ATD ElectrOniCS, S A
Plaza Cludad de Vlena, 6
28040 Madrid

IRELAND

ITT..gESA

Micro MarketlO!} Ltd
Glenageary Office Park
Glenageary

+~~:W4t~9 09 57

Tel (21)(353)(01) 85 63 25
TLX 31584

SWEDEN

FRANCE
Genenm
Z A de Courtaboeuf
Av de Is Battlque-BP 88
91943 Les Ulis Cedex

~t.I1&,91lO69 017. 7.

~3.~nrue des Solets

=~ieres

4, BY Laurent~
92606 Asnieres cectex
Tel (33) (1) 47 90 62 40
TLX 611448
Tekelec-Alrtronlc
Rue Carle Vernet - BP 2
92315 Sevres Cedex
+~~~5 34 7535

Co,

+~(~7~4000

~:g~oM~a1r~tngel, 21-3

OAF
481666
Rapid Slhcon
Rapid House
Denmark Street
High WycOmbe

f~?~i~~IZt~~ 2ER

Dub~n

ISRAEL
EastroOics Ltd
11 Rozanis Street
PO S 39300
Tel-AvIV 61392
~(~03-475151
ITALY
Intesl
DIVISlone ITT Industnes GmbH
Vlale Mllanoflori
PaiazzoE/5
20090 Assago
Milano

+~~)1'f'1824701

Lasl Elettronlcs SpA
V Ie Fulvlo Test!, 126
20092 CIOIsel1e Balsamo
MilanO

NordlSk Elektronlk AS
Huvudstagatan 1
Box 1409
17127 Solna
+~~~Ot734 97 70
YUGOSLAVIA
SWITZERLAND
Industrade A G
Hertlstrasse 31
8304 Wallisellen
Tel (41)(801)8305040
TLX· 56788

Rapldo Electronic Components S.p a
VIS. C Beccana, 6
34133 Trieste
ltalla

~(~~/360555

l\I1IKEY
EMPA ElectronIC
Lmdwurmstrllsse 9SA
8000 Muenchen 2
+~ (~~W53 80 570

+~(~=4400'2

'Held Application Location

CG/SALE/111088
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