1989 Linear Data Manual Volume 1 Communications

1989_Linear_Data_Manual_Volume_1_Communications 1989_Linear_Data_Manual_Volume_1_Communications

User Manual: manual pdf -FilePursuit

Open the PDF directly: View PDF PDF.
Page Count: 1178

Download1989 Linear Data Manual Volume 1 Communications
Open PDF In BrowserView PDF
Signetics

Linear
Data Manual
Volume 1
Communications

PHILIPS

Signetics

Linear Products

1989 Linear
Data Manual
Volume 1:
Communications

Signetics reserves the right to make changes, w~hout notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in
order to improve design and/or performance. Signetics assumes no responsibility or
liability for the use of any of these products, conveys no license or title under any
patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein
for any of these products are for illustrative purposes only. Signetics makes no
representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
LIFE SUPPORT APPLICATIONS
Signetics Products are not designed for use in life support appliances, devices, or
systems where malfunction of a Signetics Product can reasonably be expected to
result in a personal injury. Signetics customers using or selling Signetics' Products
for use in such applications do so at their own risk and agree to fully indemnify
Signetics for any damages resulting from such improper use or sale.

Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.

® Copyright 1966 Signetics Company
a division of North American Philips Corporation

All rights reserved.

Signetics

Preface

Linear Products

The Linear Division, one of four
Signetics product divisions, is a major
supplier of a broad line of linear integrated circuits ranging from high performance application specific designs to
many of the more popular industry standard devices.
A fifth Signetics division, the Military
Division, provides military-grade integrated circuits, including Linear. Please consult the Signetics Military data book for
information on such devices.
Employing Signetics' high quality processing and screening standards, the
Linear Division is dedicated to providing
high-quality linear products to our customers worldwide.
The three 1989 Linear Data and Applications Manuals provide extensive technical data and application information for a

December 1988

broad range of products serving the
needs of a wide variety of markets.

Volume 1 - Communications:
Contains data and application information concerning our radio and audio
circuits, compandors, phase-locked
loops, compact disk circuits, and ICs for
RF commUniCation, fiber optic communication, telephony and modem applications.

Volume 2 -Industrial:
Contains data and application information concerning our data conversion
products (analog-to-digital and digital-toanalog), sample-and-hold circuits, comparators, driver/receiver ICs, amplifiers,
position measurement devices, power
conversion and control ICs and music/
speech synthesizers.

Volume 3 - Video:
Contains data and application information concerning our video products. This

iii

includes tuning, video IF and audio IF
cirCUits, sync processors/generators,
color decoders and encoders, video processing ICs, vertical deflection circuits,
and power supply controllers for video
applications.
Each volume contains extensive product-specifiC application information. In
addition there are selector guides and
product-specific symbols and definitions
to facilitate the selection and understanding of Linear products. A functional
Table of Contents for each of the three
volumes and a complete product and
application note listing is also included.
Although every effort has been made to
ensure the accuracy of information in
these manuals, Signetics assumes no
liability for inadvertent errors.
Your suggestions for improvement In
future editions are welcome.

Signetics

Product Status

Linear Products

DEFINITIONS
Data Sheet
Identification

December 1988

Product Status

Definition

OI>JecIIve SpecmCIIIlon

Formative or In Deslg"

This data sheet contams the design target or goal
specifications for product development. Specifications may
change In any manner without notice.

"rellmlfIII'Y Speclflcallon

PreproducUon Product

This data sheet contains preliminary data and supplementary
data will be published at a later date. Signetlcs re88N8S the
right to make changes at any time without notice In order to
Improve design and supply the best pOSSIble product.

Product Speclf/t:allon

Full Production

This data sheet contains Final Spec,f,catlOns. Signetics
reserves the right to make changes at any arne Without
notlcs In order to Improve design and supply the best
possible product.

iv

Signetics

Section 1
General Information

Linear Products

INDEX

Contents of Volume 1, COMMUNICATIONS ..................................................1-3
Alphanumeric Listing of all Linear Products ........................................ .. ............ 1-8
Application Note Listing
- by Product Group ................................................................................ 1-14
- by Part Number ..................................................................................... 1-17
Outline of Contents of Volume 2, INDUSTRIAL ................................................. 1-20
Outline of Contents of Volume 3, ViDEO ......................................................... 1-21
Cross Reference Guide by Manufacturer ......................................................... 1-22
Cross Reference GUide by Numeric List ......................................................... 1-25
SO Availability List ..................................................................................... 1-31
Ordering Information ................................................................................... 1-33

•

Volume 1:
Communications
Contents

Signetics

Linear Products

Preface
Product Status
Outline of Contents

'"

IV

V

Section 1 - General Information
Contents of Volume 1, COMMUNICATIONS.
Alphanumeric listing of all linear Products.
Application Note Listing
- by Product Group
- by Part Number .
Outline of Contents of Volume 2, INDUSTRIAL.
....... ... .
Outline of Contents of Volume 3, VIDEO
..... . ...... . ............... .
Cross Reference GUide by Manufacturer ... . . .... ..... .. . ..
Cross Reference GUide by Numeric list
.. ... .. ..... . ....
SO Availability list
Ordering Information

1-3
1-8
1-14
1-17
1-20
1-21
1-22
1-25
1-31
1-33

Section 2 - Quality and Reliability
Quality and Reliability...

. ........ .

2-3

Section 3 - Small Area Networks
SMALL AREA NETWORKS
Introduction to 12C.. . ....
12C Bus S p e c i f i c a t i o n .
..
.
..
AN168
The Inter-Integrated Circuit (12C) Serial Bus. Theory and Practical Considerations.
PCF2100
4-Segment LCD Duplex Driver ..
PCF2111
64-Segment LCD Duplex Driver ..
PCF2112
32-Segment LCD Static Driver
PCF8200
Single-Chip CMOS Male/Female Speech SyntheSizer
PCF8570
256 X 8 Static RAM .
PCF8571
lk Serial RAM ...
.
PCF8573
Clock/Timer With 12C Interface. .
PCF8574
8-Blt Remote I/O Expandor
PCF8576
Universal LCD Driver for Low Multiplex Rates .
PCF8577
32-/64-Segment LCD Driver for Automotive ..
PCF8583
256 X 8-Blt Static RAM With Alarm Clock/Calendar .
PCF8591
8-Blt A/D and D/A Converter
SAA 1057
PLL RadiO TUning CircUit.
SAA3028
IR Receiver .
SAB3035
FLL TV TUning CirCUit (Eight 0/ A Converters) ..
SAB3036
FLL TV Tuning Circuit .
SAB3037
FLL TV TUning CirCUit (Four 0/ A Converters)
TDA8440
Audlo/Vldeo SWitch . .. .
TDA8442
I/O Expandor
RGB/YUV MatriX SWitch.
TDA8443

December 1988

1-3

3-3
3-4
3-16
(Vol 2)
. ... (VoI2)
. (Vol 2)
8-6
.. (Vol 2)
. (Vol 2)
.. (Vol 2)
(Vol 2)
. ... (Vol 2)
. ..... (VoI2)
.. . (Vol 2)
.. (VoI2)
4-193
..(VoI3)
(Vol 3)
. ... (Vol 3)
... (Vol 3)
.. 7-210
......... (Vol 3)
. . (Vol 3)

Signetics Linear Products

Contents

Volume 1: Communications

Section 4 - RF Communications
RF SIGNAL PROCESSING
Amplifiers
NE/SA5204
NE/SA/SE5205
NE/SE5539
AN140
NE5592
NE/SE592
AN141

Wide-band High Frequency Amplifier................... ........................... .......................................
Wide-band High Frequency Amplifier....... ... ............................................................................
Ultra-High Frequency Operational Amplifier... .. .... ..................................................................
Compensation Techniques for Use With the NE/SE5539.......... ........... .................. .......................
Video Amplifier................. ...................... .................... ................................................
Video Amplifier.............. .......... ...... ... .... . .... ................................................................
USing the NE/SE592 Video Amplifier..... ........... .................. ..... .... . ..... ... ...............................

4-3
4-13
4-24
4-32
4-38
4-44
4-53

Mixer/Modulators/Demodulators
MC1496/1596
Balanced Modulator/Demodulator .......... ...... ...................... .......................................................
AN189
Balanced Modulator/Demodulator Applications USing the MC1496/MC1596 . ................................•.....•.
NE602
Double-Balanced Mixer and Oscillator............ ....... ..... .. ...... ...... ... ....... ...................................
AN19S1
New Low Power Single Sideband Circuits (NE602) ......... .. ... .... ..... . ............... ... ............. .•.....
AN1982
ApplYing the Oscillator of the NE602 In low Power Mixer Applications .. ......... ....... .......... .......... ....
NE612
low Power VHF Mixer/Oscillator ........ ............... ...... ............ .... ..... ..... .................................
TDA1574
FM Front-End IC (VHF Mixer and Oscillator) ...... ... ....................... .................................•.........
TDA5030A
VHF Mixer-Oscillator (VHF Tuner IC)..... .................. .......... ........................................................

4-57
4-61
4-66
4-72
4-80
4-83
4-89
4-95

IF Systems
CA3089
MC3361
AN1992
NE/SA604A
AN1991
AN1993
NE605
NE614A
NE/SA615
TDA1576

FM IF System. ............................... ...........................................................................
Low Power FM IF ..........................................................................................................
Using the Signetics MC3361 Demonstration Board....... ... ......... ................................ .... ..............
Low Power FM IF System ......................................................................................................
Audio Decibel Level Detector With Meter Driver .................................................................•.•.•......
High SenSItivity Applications of low-Power RF/IF Integrated Circuits ...........................................•...•..
Low Power FM IF System .......................................................................................................
low Power FM IF System .....................................................................................................
High-Performance Low Power Mixer FM IF System .......................................................................
FM-IF (Quadrature Detector) ..........................................................................................•...

4-99
4-105
4-108
4-114
4-124
4-126
4-137
4-141
4-151
4-156

Single-Chip Receivers
NE605
low Power FM IF System ...................................................................................................... 4-137
NE/SA615
High-Performance low Power Mixer FM IF System ..................................................................... 4-151
TDA7000
Single-Chip FM Radio Clrcult...... .......... .................................................................................. 7-41
TDA7010
Single-Chip FM Radio Circuit (SO Package) . ..... .. ........ .. .........................• ........... ..... .... ...... 7-77
FREQUENCY SYNTHESIS
Synthesizers
HEF4750V
HEF4751V
SAA1057
AN196
AN197
TDD1742

Frequency Synthesizer ..... .................................. ......................... ... . .......................•..........•.
Universal Divider. .............. . ..... ......... ............. .... ....................... ................. ...•..................
PLL Radio Tuning Circuit.... ................................. ............................. ......................................
Single-Chip Synthesizer for Radio Tumng ............................... . ..........................................•.....
AnalysIs and BaSIC Application of the SAA 1057 (Pll Radio Tumng)........ ............................•.............
CMOS Frequency Synthesizer................ .............. ...... .. ...... .......................•...............•.........

4-163
4-173
4-182
4-190
4-197
4-209

PHASE-LOCKED LOOPS
An Overview of the Phase-Locked loop (Pll).... ............... ..... ....................................................
AN177
Modeling the Pll .................... ........... .... ...........................................................................
AN178
Phase-locked loop..................... ............... ... .......................................•...............•..........
NE/SE564
CirCUit Description of the NE564...................... .............. ................... ..... .. .. .. .•... .. . .. .. ... .... .. .•....
AN179
Frequency Synthesis With the NE564 ..... . ................................................................................
AN180
10.8MHz FSK Decoder With the NE564 .....................•.............................................................
AN1801
A 6MHz FSK Converter Design Example for the NE564 .................. ...................................•..........
AN181
Clock Regenerator With Crystal-Controlled Phase-locked VCO (NE564).......... ......•.............................
AN182
Phase-locked loop.. .............................. .... ...... .......... ..... • .. ..............................................
NE/SE565
CircUit DeSCription of the NE565 PlL.. ... ...... ................................... ..... ...................................
AN183
..............................................................•............•
Typical Applications With NE565...... .....
AN184
Function Generator........ ........................ .... .......... ............ .... ... ..........................................
NE/SE566
Circuit Descnption of the NE566...... ........... .. ...........................................................................
AN185
Waveform Generators With the NE566.. ..... .... . ........ .. . ....... .................................................
AN186
Tone Decoder/Phase-locked loop ............ ... ... ... . ..........................................................
NE/SE567
CirCUit DeSCription of the NE567 Tone Decoder.... .... .. .. . ..........................................................
AN187
AN188
Selected CIrCUIts USing the NE567 ....... ............ ..... .... .. . ................................................•......
150MHz Phase-Locked Loop..... ... ............. ......... .. .. . ..............................................
NE568

4-222
4-227
4-243
4-252
4-259
4-263
4-266
4-268
4-277
4-283
4-287
4-290
4-295
4-296
4-299
4-311
4-316
4-319

December 1988

1-4

Signetics Linear Products

Contents

Volume 1: Communications

COMPANDORS
AN 174
AN 176
NE570/SA571
NE/SA572
AN175
NE575

Applications for Compandors: NE570/571/SA571
Compandor Cookbook.. ... .... . ........... .
Compandor. .... .... . .. .
Programmable Analog Compand or
Automatic Level Control USing the NE572 .
Low Voltage Compandor

4-325
4-334
4-341
4-348
4-356
4-357

Section 5 - Data Communications
LINE DRIVERS/RECEIVERS
Symbols and Definitions for Line Dnvers .
Dual Differential RS-422 Party Line/Quad Single-Ended RS-423 Line Dnver .
AM26LS30
AM26LS31
Quad High-Speed Differential Line Dnver
AM26LS32/33
Quad High Speed Differential Line Receivers
MC1488
Quad Line Dnver ...
MC1489/A
Quad Line Receivers ........ .
AN113
USing the MC1488/1489 Line Dnvers and Receivers
NE5170
Octal line Dnver ..
Octal Line Recelver. ....
NE5180/81

5-3
5-4
5-12
5-18
5-22
5-26
5-29
5-32
5-39

MODEMS
NE5050
AN1951
NE5080
NE5081
AN195
AN1950

Power Line Modem ....
NE5050· Power Line Modem Application Board Cookbook ...... ... .......................... . ........... .
High-Speed FSK Modem Transmitter (IEEE 802.4). ... ....... ..... ...... . ....... ... .... . ....................... .
High-Speed FSK Modem Receiver (IEEE 802.4) . ......
. ......................................................... .
Applications USing the NE5080/5081
. . ...... ...... . ..... .
Application of NE5080 and NE5081 With Frequency Deviation Reduction. .... ..... . ..... ... ...... ..... . .. .

5-44
5-50
5-78
5-82
5-86
5-94

FIBER OPTICS
NE5210
NE/SA5211
NE/SA/SE5212
NE/SA5214
NE/SA5217
NE568

Translmpedance Amplifier .... .
Translmpedance Amplifier ... .
Translmpedance Amplifier
Postampllfler With Link Status Indicator
Postamplifler With Link Status Indicator
150MHz Phase-Locked Loop

5-97
5-111
5-125
5-139
5-146
4-333

Section 6 - Telecommunications
COMPANDORS
AN 174
AN 176
NE570/571/SA571
NE/SA572
AN 175
NE575

Applications for Compandors· NE570/571/SA571
Compandor Cookbook... .
Compandor ..
Programmable Analog Compandor ..
Automatic Level Control USing the NE572
Low Voltage Compandor ...

PHASE-LOCKED LOOPS
ANl77
An Overview of the Phase-Locked Loop (PLL)
AN 178
Modeling the PLL
NE/SE564
Phase-Locked Loop
AN179
CirCUit Descnptlon of the NE564 ..
AN180
Frequency SyntheSIS With the NE564 .. .
AN1801
10.8MHz FSK Decoder With the NE564 ... .
AN181
A 6MHz FSK Converter Design Example for the NE564 .
AN182
Clock Regenerator With Crystal-Controlled Phase-Locked VCO (NE564) ... .
NE/SE565
Phase-Locked Loop . ..... .
. ............. .
AN183
CirCUit Description of the NE565 PLL.
AN184
TYPical Applications With NE565 ..
NE/SE566
Funclion Generator .....
AN185
CirCUit Description of the NE566 .....
AN186
Waveform Generators With the NE566 ....
NE/SE567
Tone Decoder/Phase-Locked Loop ....
AN187
CirCUit Description of the NE56? Tone Decoder ..... .
AN188
Selected CircUits USing the NE567
NE568
150MHz Phase-Locked Loop.
TELEPHONY
NE5900
PCD3310/A
December 1988

Call Progress Decoder
Pulse and DTMF Dialer With Redial. . ..

4-325
4-334
4-341
4-348
4-356
4-357
4-222
4-227
4-243
4-252
4-259
4-263
4-266
4-268
4-277
4-283
4-287
4-290
4-295
4-296
4-299
4-311
4-3-16
4-333
6-3
6-10

1-5

Signetics Linear Products

Contents

Volume 1: Communications

PCD3311/3312
PCD3315
PCD3341
PCD3343
PCD3360
PCD4415
TEA1060/61
TEA1067
AN1942
AN1943
TEA1068

DTMF/Modem/Muslcal Tone Generator .... . ..... ". .. ............... ..
CMOS Redial and Repertory Dialer ..................................................................... ..
CMOS Repertory Telephone Set Controller ............................................................................ ..
CMOS Mlcrocontroller for Telephone Sets .............. " ..... .." ........................................... .
.. .. " ........ , .................. .
Programmable Multi-Tone Telephone Ringer .......... . ..... .........
... . ..... ..... ....... . ..... .... .. .................... ,
Pulse and DTMF Dialer with Redial... ..... .......
Versatile Telephone Transmission CirCUitS With Dialer Interface. .... .............. .. ...................... ..
Low Voltage Transmission IC With Dialer Interface .. " ............ . .......... .. .......................... .
Application of the Low Voltage Versatile Transmission CirCUit.
................ ..... .. .. " .............. ..
Supply of Peripheral CirCUitS With the TEAl 067 Speech CirCUit... .................. .. ..................... .
Versatile Telephone Transmission CirCUlI.. ............ ....... ..... ..... ....... ........ . ..................... .

6-25
6-37
6-45
6-55
6-82
6-90
6-102
6-113
6-125
6-145
6-151

Section 7 - RadiolAudio
RADIO CIRCUITS
AM Radio
TDA1072A
AN1961
TEA5570

AM Receiver CirCUit ... . .... ...
Integrated AM TDA 1072A Receiver
AM/FM Radio Receiver CirCUit... .

FM Radio
CA3089
NE602
AN1981
AN1982
NE/SA604A
AN1991
NE612
NE614A
TDA1001B
TDA1574
TDA1576
TDA7000
AN192
AN193
TDA7010
TDA7021
TEA5560
TEA5570

FM IF System..... ... . .... ......... ....... ........... ..........
.. ......................................... .
Double-Balanced Mixer and Oscillator..... ............... ..... ...... .........
.. ........................... .
New Low-Power Single Sideband CirCUitS (NE602) ........... , ...... ..
ApplYing the Oscillator of the NE602 In Low-Power Mixer Applications.. .... .... ... ............. .. ...... ..
.. ........................................................ ..
High-Performance Low-Power FM IF System.
Audio Decibel Level Detector With Meter Driver (NE604) ......... " .......................................... ..
Double-Balanced Mixer and Oscillator ............................................................................ ..
Low Power FM IF System..... ..... ........ ..... ..... ... . ..... ...
.. ........................... .
Interference Suppressor ..... " ......... " ... " .. " ...................................................... ..
FM Front-End IC (VHF Mixer and Oscillator)..
..." .. " ....... .......
... .. .................. ..
FM-IF System (Quadrature Detector) ...... ....
... . ............. .....
'''''''' ......... " .... .
Single-Chip FM Radio CirCUit....
....... .... .... ....
....... ..... ....... .. ............ ..
.. ......................... .
A Complete FM Radio on a Chip .............. " ....... ".. . ...... ... .. ...
TDA7000 for Narrow Band FM RecepllOn ........ ....... ,,,,,,,,,,,,,,,,, .................................. .
FM Radio Circuit (SO Package) ... ....... ...... ......... ...... ......
.. ...... " ........................... ..
Single-Chip FM Radio CIrCUIi.. ..................................................................................... .
FMIIF System .................................................................................................... .
AM/FM Radio Receiver Circuit. .. .................................. , ........... , ................................... ..

4-99
4-66
4-72
4-80
4-114
4-124
4-83
4-141
7-35
4-89
4-156
7-41
7-46
7-61
7-77
7-82
7-88
7-26

Stereo Decoders
TDA1578A
TDA7040
TEA5581
p.A758
AN191

PLL Stereo Decoder............... ..... ....... ... . .............. ...... ....... .....
.. ............................... ..
PLL Stereo Decoder (Low Voltage)
.... ....... ...........
.... ..... .. .......................... .
PLL Stereo Decoder... ...... ............... ... . ....... ............... . ............... " .......... " .... .
FM Stereo Multiplex Decoder Phase-Locked Loop.. ........... .. ........................................... ..
Stereo Decoder Applications USing the JJ.A758 ...................... ,
.................................... ..

7-96
7-105
7-111
7-118
7-t23

7-3
7-15
7-26

Digital Tuning Circuits
SAA1057
PLL Radio TUning CIrCUlt.. .................................................................................................. 4-182
AN196
Single-Chip Synthesizer for RadiO TUning ............................................................................ 4-190
AN197
AnalysIs and BasIc Application of the SAA1057 (PLL RadiO TUning) ........................................ 4-197
AUDIO CIRCUITS
Preamplifiers
NE542
AN190

Dual Low-Noise Preamplifier ......................................... """ ....................................... 7-131
Applications of Low-NOise Stereo Amplifiers' NE542 ......................... , ..................................... 7-135

Tone/Volume/Switching
Stereo AudiO Switch .......................................................................................................
TDA1029
TDA1074A
DC-Controlled Dual Potentiometers ........................................................................................
TDA1524A
Stereo AudiO Control.. .... ................... . ... ....... .............. ............. .. ...................................
TDA8440
Video/Audio SWitch IC ...... .. ................................................ " .............. " ...................
TEA6300
Digitally-Controlled Tone, Volume, and Fader Control CirCUlI.. ..................................................

7-138
7-147
7-154
7-162
7-168

Dolby
NE5240
NE645/646
NE648/649
NE650

7-178
7-182
7-187
7-192

December 1988

Dolby Digital AudiO Decoder. ...... ..... .... ....... ..... .. ................................................
Dolby NOise ReducllOn Circuit... ... ..... ...... ...... .............. .......... ............... .. ...............
Low Voltage Dolby NOise ReducllOn CirCUit ...... ............. . .....
.. ...................................
. ... .. ... ' ..
. .. .... . . .. "" .......... ".
Dolby B-Type NOise ReducllOn CirCUit...

1-6

Signetics Linear Products

Volume 1: Communications

Contents

Power Amplifiers
Symbols and Deflmtlons for Audio Power Amplifiers .....
TDA10l0A
6W AudiO Amplifier With Preamplifier
... .... . .... .. ... ..... ..... ..... . .... ... ..... ..... ....... . .......
TDA10llA
2 to 6W AudiO Power Amplifier With Preamplifier............ ............................ ..... ........... .....
TDA1013A
4W AudiO Amplifier With DC Volume Control.. . ... ................... .... ..... .... . .... . .... ....... . .....
AN148
AudiO Amplifier With TDA 1013A .. .... ................... ..................... ................. ...........
TDA1015
1 to 4W AudiO Amplifier With Preamplifier .... ...
.. .......... ....... . ..... .............. ... ... . ....
TDA1020
12W AudiO Amplifier With Preamplifier ... '"
............................................................... "
TDA1510
2 X 12W AudiO Amplifier ......... '" ... ........
. ............................................................
AN1491
Car RadiO AudiO Power Amplifier up to 24W With the TDAI510.. .. ... .... ..... ........... ..........
TDA1512
12 to 20W AudiO Amplifier .... . ...... ... . .... .... .............. ........................ ... ... ....
40W High-Performance HI-FI Amplifier. .....
.. . ..... ... .............. ... ..... ..... ...
"
TDA1514A
24W BTL AudiO Amplifier .... ...... ...... ....... ... .... ............. '"
.... ...... ...
... . ... .. ...
TDA1515A
Car RadiO AudiO Power Amplifiers up to 20W With the TDA1515 ..........................................
AN1481
TDA1520B
20W HI-FI AudiO Amplifier.. .. .... . ........ ..... . ... .... ....... . .......................................... "
AN149
20W HI-FI Power Amplifier With the TDA1520A ............. , ................................................
.... .... ....
...... ....... ..... .... ....... . .......... ....
2 X 12 HI-FI AudiO Power Amplifier ... ...
TDA1521
5W AudiO Amplifier ...... ..... ...
.... . ..... . .. ..... . .... ... .... . .... ....... ....
... . ...........
TDA2611A
TDA7050
Low Voltage Mono/Stereo Power Amplifier ....................................................................
1 Watt Low Voltage AudiO Power Amplifier.. .. ..... ... .... ..... . ........... .... .... ..... ..... . ....
TDA7052
COMPACT DISK
SAA7210
SAA7220
TDA1541

7-197
7-198
7-203
7-207
7-210
7-219
7-224
7-228
7-232
7-240
7-245
7-248
7-252
7-259
7-264
7-269
7-274
7-278
7-281

Decoder for Compact Disk Digital Audio System ..................................................................... . 7-284
Digital Filter for Compact Disk Digital Audio System .................................................................... .. 7-298
Dual 16-Blt Dlgltal-to-Analog Converter .................................................................. .
7-310

Section 8 - Speech I Audio Synthesis
OM8210
PCD3311/3312
PCF8200
SAA1099

Speech Encoding and Editing System ...... ...... .........
.... ........................... ....... . ....... .
DTMF/Modem/Muslcal Tone Generator ............................................................... .
Single-Chip CMOS Male/Female Speech Synthesizer......................... ......... . ......................... .
Stereo Sound Generator for Sound Effects and MusIc SynthesIs. .... . ......................................... .

8-3
6-25
8-6
8-16

Section 9 - Packaging Information
Substrate Design GUidelines for Surface Mounted Devices.. ........ ......... ...... . .............................. " ..... . .. .
........ ....... . ............................ .
Test and Repair...... .... .......... ..... . "
Fluxing and Cleamng ..... ..... ....... "
............... ........ .............. . .................................... .
.................... .. .
Thermal Considerations for Surface-Mounted Devices ... ......... .............. ......... ....
Package Outlines for Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM, MC, NE, SA, SE, SG, IJA, and UC.............. . .. .
Package Outlines for Prefixes HEF, OM, PCD, PCF, PNA, SAA, SAB, TDA, TDD and TEA......... .... . ....................... .

9-3
9-14
9-17
9-22
9-35
9-51

Section 10 - Sales Office Listings
Sales Office listings... .. ..

December 1988

. . ....... . ....

..

.. . . .

.

. . .

1-7

10-3

Signetics

Alphanumeric
Product List

Linear Products

Vol 1
ADC0803/4/5
ADC0820
AM26LS30
AM26LS31
AM26LS32/33
AM6012
AU2901
AU2902
AU2903
AU2904
CA3089
DAC-08 Series
HEF4750V
HEF4751V
ICM7555
LF198
LF298
LF398
LM111
LM119
LM124
LM139/A
LM158
LM193/A
LM211
LM219
LM224
LM239/A
LM258
LM293/A
LM311
LM319
LM324
LM339/A
LM358
LM393/A
LM2901
LM2902
LM2903
LM2904
MC1408-7
MC1408-8
MC1458
MC1488
MC1489/A
MC1496
MC1508-8
MC1558
MC3302
MC3303
MC3361
MC3403
MC341 0
MC3410C
December 1988

8-Blt CMOS AID Converter
8-Blt CMOS AID Converter
Dual Differential RS-422 Party Line Quad Single-Ended RS-423
line Driver
Quad High-Speed Differential Line Driver
Quad High-Speed Differential line Receivers
12-Blt MultiplYing DI A Converter
Quad Voltage Comparator
Low Power Quad Operational Amplifier
Low Power Dual Voltage Comparator
Low Power Dual Operational Amplifier
FM IF System
8-Blt High-Speed MultiplYing DI A Converter
Frequency Synthesizer
Universal Divider
CMOS Timer
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Quad Voltage Comparator
Low Power Quad Operational Amplifier
Low Power Dual Voltage Comparator
Low Power Dual Operational Amplifiers
8-Blt MultiplYing DI A Converter
8-Blt MultiplYing DI A Converter
General Purpose Operational Amplifier
Quad Line Driver
Quad Line Receivers
Balanced Modulator/Demodulator
8-Blt MultiplYing DI A Converter
General Purpose Operational Amplifier
Quad Voltage Comparator
Quad Low Power Operational Amplifier
Low Power FM IF
Quad Low Power Operational Amplifier
10-Blt High-Speed MultiplYing DI A Converter
10-Blt High-Speed MultiplYing DI A Converter

1-8

Vol 2
5-11
5-24

5-4
5-12
5-18
5-99
5-229
4-29
5-234
4-35
4-99
5-90
4-163
4-173

5-22
5-26
4-57

7-3
5-306
5-306
5-306
5-239
5-242
4-40
5-248
4-141
5-255
5-239
5-242
4-40
5-248
4-141
5-255
5-239
5-242
4-40
5-248
4-141
5-255
5-248
4-40
5-255
4-141
5-123
5-123
4-47
6-4
6-8
5-123
4-47
5-248
4-53

4-105
4-53
5-129
5-129

Vol 3

Signetics linear Products

Alphanumeric Product list

Vol 1
MC3503
MC3510
NE/SE521
NE/SE522
NE/SE527
NE/SE529
NE/SE530
NE/SE531
NE/SA532
NE/SE538
NE542
NE544
NE/SE555
NE/SA/SE556/1
NE/SA/SE558
NE/SE564
NE/SE565
NE/SE566
NE/SE567
NE568
NE570
NE/SA571
NE/SA572
NE575
NE587
NE589
NE590
NE591
NE/SE592
NE/SA594
NE602
NE/SA604A
NE605
NE612
NE/SA614A
NE/SA615
NE645
NE646
NE648
NE649
NE650
NE/SE4558
NE/SE5018
NE/SE5019
NE5020
NE5034
NE5036
NE5037
NE5044
NE5045
NE5050
NE5060
NE5080
NE5081
NE5090
NE/SA/SE51 051 A
NE/SE5118
NE/SE5119
NE5150
NE5151
NE5152
NE5170
NE5180
December 1988

Quad Low Power Operational Amplifier
10-Bit High-Speed MultiplYing DI A Converter
High-Speed Dual Differential ComparatorlSense Amp
High-Speed Dual Differential ComparatorlSense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Dual Low-Noise Preamplifier
Servo Amplifier
Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
150MHz Phase-Locked Loop
Compand or
Compand or
Programmable Analog Compandor
Low Voltage Compandor
LED Decoder/Driver
LED Decoder/Driver
Addressable Peripheral Drivers
Addressable Peripheral Drivers
Video Amplifier
Vacuum Fluorescent Display Driver
Low Power VHF Mlxer/Osclliator
High-Performance Low-Power FM IF System
Low Power FM IF System
Low Power VHF Mlxer/Osclliator
Low Power FM IF System
High-Performance Low Power Mixer FM IF System
Dolby NOise Reduction CirCUit
Dolby NOise Reduction CirCUit
Low Voltage Dolby NOise Reduction CirCUit
Low Voltage Dolby NOise Reduction CirCUit
Dolby B-Type NOise Reduction CirCUit
Dual General Purpose Operational Amplifier
8-Blt Microprocessor-Compatible DI A Converter
8-Blt Microprocessor-Compatible DI A Converter
10-Blt Microprocessor-Compatible DI A Converter
8-Blt High-Speed AID Converter
6-Blt AID Converter (Serial Output)
6-Blt AID Converter (Parallel Outputs)
Programmable Seven-Channel RC Encoder
Seven-Channel RC Decoder
Power Line Modem
Sample-and-Hold CirCUit
High-Speed FSK Modem Transmitter
High-Speed FSK Modem Receiver
Addressable Relay Driver
12-Blt High-Speed Comparator
8-Blt Microprocessor-Compatible DI A Converter
8-Bit Microprocessor-Compatible DI A Converter
RGB Video DI A Converter
RGB Video DI A Converter
RGB Video DI A Converter
Octal Line Driver
Octal Line Receiver

1-9

Vol 2

Vol 3

4-53
5-129
5-274
5-279
5-285
5-290
4-66
4-73
4-141
4-81
7-131
8-33
7-48
7-33
7-39
4-243
4-277
4-290
4-299
4-319
4-341
4-341
4-348
4-357

4-44
4-66
4-114
4-137
4-83
4-141
4-151
7-182
7-182
7-187
7-187
7-192

11-3

6-53
6-63
6-34
6-34
4-244
6-78

11-93

4-214

4-61
5-137
5-143
5-149
5-37
5-44
5-51
8-4
8-15
5-44
5-311
5-78
5-82

5-32
5-39

6-28
5-261
5-157
5-157
5-169
5-169
5-169
6-14
6-21

11-19
11-19
11-19

•

Signetics Linear Products

Alphanumeric Product List

NE5181
NE5204
NE/SA/SE5205
NE5210
NE/SA5211
NE/SA5212
NE/SA5214
NE/SA5217
NE/SA5230
NE5240
NE/SE5410
NE/SE5512
NE/SE5514
NE5517/A
NE5520
NE/SE5521
NE/SE55321 A
NE5533/A
NE5534A
NE/SE5535
NE/SE5537
NE/SE5539
NE/SE5560
NE/SE5561
NE/SAlSE5562
NE5568
NE/SA/SE5570
NE5592
NE5900
OM8210
PCD3310
PCD3311
PCD3312
PCD3315
PCD3341
PCD3343
PCD3360
PCD4415
PCF2100
PCF2111
PCF2112
PCF8200
PCF8566
PCF8570
PCF8571
PCF8573
PCF8574
PCF8576
PCF8577
PCF8582A
PCF8583
PCF8591
PNA7509
SA532
SA534
SA556/1
SA558
SA571
SA572
SA594
SA604A
SA614A
SA615
December 1988

Octal line Receiver
Wldeband High Frequency Amplifier
Wide band High Frequency Amplifier
Translmpedance Amplifier (280M Hz)
Translmpedance Amplifier (180MHz)
Translmpedance Amplifier (140MHz)
Postampllfler with Link Status Indicator
Fiber OptiC Postampllfler with Link Status Indicator
Low Voltage Operational Amplifier
Dolby Digital Audio Decoder
10-Blt High-Speed MultiplYing DI A Converter
Dual High Performance Operational Amplifier
Quad High Performance Operational Amplifier
Dual Operational Transconductance Amplifier
LVDT Signal Conditioner
LVDT Signal Conditioner
Internally-Compensated Dual Low-NOise Operational Amp
Single and Dual Low-Noise Operational Amp
Single and Dual Low-NOise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra High Frequency Operational Amplifier
SWitched-Mode Power Supply Control CirCUit
SWitched-Mode Power Supply Control CirCUit
SMPS Control CirCUit, Single Output
SWitched-Mode Power Supply Controller
Three-Phase Brushless DC Motor Driver
Video Amplifier
Call Progress Decoder
Speech Encoding and Editing System
Pulse and DTMF Dialer With Redial
DTMF/Modem/Muslcal Tone Generator
DTMF/Modem/Muslcal Tone Generator
CMOS Redial and Repertory Dialer
CMOS Repertory Telephone Set Controller
CMOS Mlcrocontroller for Telephone Sets
Programmable Multi-Tone Telephone Ringer
Pulse and DTMF Dialer with Redial
LCD Duplex Driver
LCD Duplex Driver
LCD Driver
Single-Chip CMOS Male/Female Speech Synthesizer
Universal LCD Driver for Low Multiplex Rates
256 X 8 Static RAM
1K Serial RAM
Clock/Calendar With Serial 1/0
8-Blt Remote 1/0 Expandor
Universal LCD Driver for Low Multiplex Rates
32/64 Segment LCD Driver for Automotive
12 C CMOS EPROM (256 X 8)
256 X 8-Blt Static RAM with Alarm Clock/Calendar
8-Bit AID and D/A Converter
7-Blt AID Converter
Low Power Dual Operational Amplifier
Low Power Quad Operational Amplifier
Dual Timer
Quad Timer
Compandor
Programmable Analog Compandor
Vacuum Fluorescent Display Driver
4-114
4-141
High-Performance Low Power Mixer FM IF System

1-10

Vol 1

Vol 2

5-39
4-3
4-13
5-97
5-111
5-125
5-139
5-146

6-21
4-170
4-180
4-279
4-293
4-307
4-321
4-328
4-122

Vol 3
11-52
11-62

7-178

4-24

4-40
6-3
8-3
6-10
6-25
6-25
6-37
6-45
6-55
6-82
6-90

5-196
4-88
4-94
4-263
5-324
5-354
4-100
4-106
4-106
4-148
5-316
4-224
8-73
8-102
8-113
8-145
8-44
4-238

11-73

11-87

9-3

6-83
6-90
6-95
8-6
6-100
9-30
9-38
9-46
9-57
6-120
6-141
9-65

4-3
4-11
4-19
4-30

4-38

7-23
5-59
5-72
4-100
4-40
7-33
7-39
4-341
4-348
6-78
4-191
4-214
4-151

11-9

II

III

Signetics Linear Products

Alphanumeric Product List

SA723C
SA741C
SA747C
SA1458
SA5205
SA5211
SA5212
SA5214
SA5217
SA5230
SA5534A
SA5562
SA5570
SAA1057
SAA1064
SAA1099
SAA3004
SAA3006
SAA3027
SAA3028
SAA7210
SAA7220
SAB3035
SAB3036
SAB3037
SE521
SE522
SE527
SE529
SE530
SE531
SE532
SE538
SE555
SE555C
SE556-1C
SE556/-1
SE558
SE564
SE565
SE566
SE567
SE592
SE4558
SE5018
SE5019
SE5118
SE5119
SE5205
SE5212
SE5410
SE5512
SE5514
SE5521
SE5532/A
SE5534A
SE5535
SE5537
SE5539
SE5560
SE5561
SE5562
SE5570
December 1988

PrecIsion Voltage Regulator
General Purpose Operational Amplifier
Dual Operational Amplifier
General Purpose Operational Amplifier
Wide-band High Frequency Amplifier
Translmpedance Amplifier
Translmpedance Amplifier
Translmpedance Amplifier
Translmpedance Amplifier
Low Voltage Operational Amplifier
Single and Dual Low-Noise Operational Amp
SMPS Control CirCUit, Single Output
Three-Phase Brushless DC Motor Dnver
PLL Radio Tuning CirCUit
4-Dlglt LED Dnver with 12 C Bus Interface
Stereo Sound Generator for Sound Effects and MusIc
IR Transmitter (448 Commands)
IR Transmitter (2K Commands, Low Voltage)
IR Transmitter
IR Remote Control Transcoder With 12C
Compact Disk Decoder
Digital Filter and Interpolator for Compact Disk
FLL Tuning and Control CirCUit (Eight 0/ A Converters)
FLL Tuning and Control CirCUit
FLL Tuning and Control CirCUit (Four 0/ A Converters)
High-Speed Dual Differential Comparator/Sense Amp
High-Speed Dual Differential Comparator/Sense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Timer
Timer
Dual Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
Video Amplifier
Dual General Purpose Operational Amplifier
8-Blt Microprocessor-Compatible 0/ A Converter
8-Blt Microprocessor-Compatible 0/ A Converter
8-Blt Microprocessor-Compatible 0/ A Converter
8-Blt Microprocessor-Compatible 0/ A Converter
Wide-band High Frequency Amplifier
Translmpedance Amplifier
10-Blt High-Speed MultiplYing 0/ A Converter
Dual High Performance Operational Amplifier
Quad High Performance Operational Amplifier
LVDT Signal Conditioner
Internally-Compensated Dual Low-NOise Operational Amp
Single and Dual Low-NOise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra High-Frequency Operational Amplifier
SWitched-Mode Power Supply Control CirCUit
SWitched-Mode Power Supply Control CirCUit
SMPS Control CirCUit, Single Output
Three-Phase Brushless DC Motor Dnver

1-11

Vol 1

Vol 2

4-13
5-111
5-125
5-139
5-146

8-235
4-157
4-163
4-47
4-180
4-293
4-307
4-321
4-328
4-122
4-106
8-113
8-44

Vol 3

11-62

4-182
6-153
8-16
5-3
5-19
5-28
5-37
7-284
7-298
4-50
4-65
4-75
5-274
5-279
5-285
5-190
4-66
4-73
4-141
4-81
7-48
7-48
7-33
7-33
7-39
4-243
4-277
4-290
4-299
4-44

4-13
5-125

4-24

4-244
4-61
5-137
5-143
5-157
5-157
4-180
4-267
5-208
4-88
4-94
5-354
4-100
4-106
4-148
5-316
4-224
8-73
8-102
8-113
8-44

11-93

11-62

11-73

Signetics Linear Products

Alphanumeric Product List

Vol 1
SG1524C
SG2524C
SG3524
SG3524C
SG3526
TDA1001B
TDA1010A
TDA1011A
TDA1013A
TDA1015
TDA1020
TDA1023
TDA1029
TDA1072A
TDA1074A
TDA1510
TDA1512
TDA1514A
TDA1515A
TDA1520B
TDA1521
TDA1524A
TDA1534
TDA1541
TDA1574
TDA1576
TDA1578A
TDA2545A
TDA2546A
TDA2577A
TDA2578A
TDA2579
TDA2582
TDA2593
TDA2594
TDA2595
TDA2611A
TDA2653A
TDA3047
TDA3048
TDA3505
TDA3566
TDA3567
TDA3654
TDA4501
TDA4502
TDA4503
TDA4505
TDA4555
TDA4565
TDA4570
TDA4580
TDA5030A
TDA5040
TDA7000
TDA7010
TDA7021
TDA7040
TDA7050
TDA7052
TDA8340/41
TDA8440
TDA8442
December 1988

Improved SMPS Push-Pull Controller
Improved SMPS Push-Pull Controller
SMPS Control Circuit
Improved SMPS Push-Pull Controller
SWitched-Mode Power Supply Control Circuits
Interference Suppressor
6W Audio Amplifier With Preamplifier
2 to 6W Audio Power Amplifier With Preamplifier
4W Audio Amplifier With DC Volume Control
1 to 4W Audio Amplifier With Preamplifier
12W Audio Amplifier With Preamplifier
Time-Proportional Triac Trigger
Stereo Audio SWitch
AM Receiver Circuit
DC-Controlled Dual Potentiometers
2 X 12W Audio Amplifier
12 to 20W Audio Amplifier
40W High-Performance HI-FI Amplifier
24W BTL Audio Amplifier
20W HI-FI Audio Amplifier
2 X 12W Hi-FI Audio Power Amplifier
Stereo-TonelVolume Control Circuit
14-Blt A/D Converter, Serial Output
16-Blt Dual D/ A Converter, Serial Output
FM Front End IC (VHF Mixer and Oscillator)
FM IF System
PLL Stereo Decoder
QuasI-Split Sound IF System
QuasI-Split Sound IF and Sound Demodulator
Sync CircUit With Vertical Oscillator and Driver
Sync Circuit With Vertical Oscillator and Dnver
Synchronlzalion Circuit
Control Circuit for Power Supplies
HOrizontal Combination
HOrizontal Combination
HOrizontal Combination
5W AudiO Output Amplifier
Vertical Deflection Circuit With Oscillator
IR Preamplifier
IR Preamplifier
Chroma Control CirCUit
PAL/NTSC Decoder With RGB Inputs
NTSC Color Decoder
Vertical Defleclion
Small Signal Subsystem IC for Color TV
Complete Video IF IC With Vertical and HOrizontal Sync
Small Signal Subsystem for Monochrome TV
Small Signal Subsystem IC for Color TV
Mullistandard Color Decoder
Color Transient Improvement CircUit (CTI)
NTSC Color Difference Decoder
Video Control Combination Circuit With Automatic Cut-Off Control
VHF Mixer-OSCIllator (VHF Tuner IC)
Brushless DC Motor Driver
Single-Chip FM RadiO Circuit
Single-Chip FM RadiO Circuit (SO Package)
Single Chip FM RadiO Circuit
PLL Stereo Decoder (Low Voltage)
Low Voltage Mono/Stereo Power Amplifier
1 Watt Low Voltage AudiO Power Amplifier
TeleVISion IF Amplifier and Demodulator
Vldeo/ AudiO SWitch
Quad DAC With 12 C Interface

1-12

Vol 2

Vol 3

8-147
8-147
8-200
8-147
8-216
7-35
7-198
7-203
7-207
7-219
7-224
8-268
7-138
7-3
7-147
7-228
7-240
7-245
7-248
7-259
7-269
7-154
7-310
4-89
4-156
7-96

5-82
5-217

8-3
8-6
9-3
9-14
9-31
13-3
9-41
9-46
9-51
7-274
12-3
5-42
5-46
10-11
10-18
10-60
12-9
6-3
6-13
6-15
6-24
10-38
10-53
10-57
10-62
4-80

4-95
8-63
7-41
7-77
7-82
7-105
7-278
7-281
7-210

7-3
11-46
10-101

Signetics linear Products

Alphanumeric Product List

Vol 1

TDA8443/A
TDA8444
TDD1742
TEAl 039
TEA1060
TEA1061
TEA1067
TEA1068
TEA5560
TEA5570
TEA5581
TEA6300
UC1842
UC2842
UC3842
pA723
pA723C
"A733
p.A733/C
"A741
p.A741C
"A747
"A747C
"A758

December 1988

RGBIYUV SWitch Inputs
Octuple 6·Blt DI A Converter With 12 C Bus
CMOS Frequency Synthesizer
Control CirCUit for SWltched·Mode Power Supply
Telephone Transmission CirCUit With Dialer Interface
Telephone Transmission CirCUit With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
FM IF System
AM/FM RadiO Receiver CircUit
PLL Stereo Decoder
Dlgitally·Controlied Tone, Volume, and Fader Control CirCUit
Current Mode PWM Controller
Current Mode PWM Controller
Current Mode PWM Controller
PrecIsion Voltage Regulator
PrecIsion Voltage Regulator
Differential Video Amplifier
Dlfferenllal Video Amplifier
General Purpose Operallonal Amplifier
General Purpose Operational Amplifier
Dual Operallonal Amplifier
Dual Operational Amplifier
FM Stereo Multiplex Decoder Phase-Locked Loop

1·13

Vol 2

Vol 3
10·107

5·222
4·209
8·227

13·12

6·102
6·102
6·113
6·151
7·88
7·26
7·111
7·168
8·241
8·241
8·241
8·235
8·235
4·257
4·257
4·157
4·157
4-163
4·163
7·118

11-106
11·106

Signetics

Application Notes
by Product Group

Linear Products

Vol 1

Vol 2

Vol 3

4-32
4-53
4-72
4-80
4-124

4-232
4-253

11-81
11-102

Signal Processing
AN140
AN141
AN1981
AN1982
AN1991

Compensation Techniques for Use With the NE/SE5539
USing the NE592/5592 Video Amplifier
New Low Power Single Sideband CirCUitS (NE602)
ApplYing the OSCillator of the NE602 In Low Power Mixer Applications
Audio DeCibel Level Detector With Meter Driver

4-201

Frequency Synthesis
AN196
AN197

Single-Chip SyntheSizer For Radio TUning
AnalysIs and BasIc Applicallon of the SAA1057 (VBA8101)

4-190
4-197

Phase-Locked Loops
AN177
AN178
AN179
AN180
AN1801
AN181
AN182
AN183
AN184
AN185
AN186
AN187
AN188

An Overview of Phase-Locked Loops (PLL)
Modeling the PLL
CirCUit Description of the NE564
The NE564 Frequency SyntheSIS
108MHz FSK Decoder With the NE564
A 6MHz FSK Converter Design Example for the NE564
Clock Regenerator With Crystal Controlled Phase-Locked VCO
CirCUit Description of the NE565
TYPical Applications With NE565
CirCUit Description of the NE566
Waveform Generators With the NE566
CirCUit Description of the NE567 Tone Decoder
Selected CirCUitS USing the NE567

4-222
4-227
4-252
4-259
4-263
4-266
4-268
4-283
4-287
4-295
4-296
4-311
4-316

Applications for Compandors, NE570/571/SA571
Automatic Level Control NE572
Compandor Cookbook

4-325
4-356
4-334

Compandors
AN 174
AN175
AN176

Line Drivers/Receivers
AN113
AN195
AN1950
AN1951

Applications USing the MC1488/1489 Line Drivers and Receivers
Appllcallons USing the NE5080/5081
Application of NE5080 and NE5081 with Frequency Deviation Reduction
NE5050 Power Line Modem Application Board Cookbook

5-29
5-86
5-94
5-50

TEA 1067 Application of the Low Voltage Versatile Transmission CirCUit
TEA 1067' Supply of Peripheral CirCUits With the TEA 1067 Speech CirCUit

6-125
6-145

TDA 1072A. Integrated AM Receiver
New Low Power Single Sideband CirCUitS (NE602)
ApplYing the OSCillator of the NE602 In Low Power Mixer Appllcallons
Stereo Decoder Appllcallons USing the pA758
A Complete FM Radio on a Chip
TDA7000 for Narrow-Band FM-Receptlon
AudiO DeCibel Level Detector With Meter Driver (NE604A)
USing the Signetics MC3361 Demonstration Board
High Sensitivity Applicallons of Low-Power RFIIF Integrated CirCUitS

7-15
4-72
4-80
7-123
7-46
7-61
4-124
4-108
4-126

6-11

Telephony
AN1942
AN1943
Radio Circuits
AN1961
AN1981
AN1982
AN191
AN192
AN193
AN1991
AN1992
AN1993

December 1988

1-14

4-201
4-203

Signetics Linear Products

Application Notes by Product Group

Vol 1

Vol 2

Vol 3

Audio Circuits
AN148
AN1481
AN149
AN1491
AN190

Audio Amplifier With TDA1013
Car Radio Audio Power Amplifiers up to 20W With the TDA1515
20W Hi-FI Power Amplifier With the TDA1520A
Car Radio Audio Power Amplifiers up to 24W With the TDA1510
Applications of Low Noise Stereo Amplifiers: NE542

7-210
7-252
7-264
7-232
7-171

Operational Amplifiers
AN142
ANI44
AN1441
AN1511
AN1512
ANI60
ANI64
AN165
AN166

Audio Circuits USing the NE5532/33/34
Applications for the NE5512 and NE5514
Applications for the NE5514
Low Voltage Gated Generator: NE5230
All In One. NE5230
Applications for the MC3403
Explanation of NOise
Integrated Operational Amplifier Theory
BasIc Feedback Theory

4-114
4-91
4-97
4-134
4-136
4-58
4-8
4-18
4-25

High Frequency Amps
AN1991

Audio Decibel Level Detector With Meter Driver

4-124

4-210

4-32
4-53

4-232
4-253

Video Amps
AN140
AN141

Compensation Techniques for Use With the NE/SE5539
Using the NE592/5592 Video Amplifier

11-81
11-102

Transconductance
AN145

NE5517: General Description and Applications for Use With the NE5517/A
Transconductance Amplifier

4-276

Data Conversion
AN100
AN10l
AN105
ANI 06
AN108
AN1081
AN109

An Overview of Data Converters
Basic DACs
Digital Attenuator
USing the DAC08 Without a Negative Supply
An Ampliflying, Level Shifting Interface for the PNA7509 Video DI A Converter
NE5150/51152: Family of Video D/A Converters
Microprocessor-Companble DACs

5-3
5-90
5-97
5-122
5-81
5-176
5-162

Applications for the NE5211522/527/529
12-Bit AID Converter USing the NE5105 Comparator

5-295
5-269

Comparators
AN116
AN1161

Position Measurement
AN118
AN1180
AN1181
AN1182

LVDT Signal Conditioner: Applications Using the NE5520
A Microprocessor-Based Servo-Loop for linear Position Control
NE5521 In a Modulated Light Source Design Application
NE5521 In Muill-faceted Applications

5-329
5-344
5-359
5-363

Line Drivers/Receivers
AN113

Applications Using the MC148811489 line Drivers and Receivers

5-29

6-11

Display Drivers
AN112

LED Decoder Drivers: USing the NE587 and NE589

6-72

NE555 and NE556 Applications
NE558 Applications

7-54
7-43

TImers
AN170
AN171

December 1988

1-15

11-18
11-26

Signetics Linear Products

Application Notes by Product Group

Vol 1

Vol 2

Vol 3

Motor Control and Sensor Circuits
ANt28t
AN131
AN1311
AN132
AN133
AN1341

8-49
8-11
8-13
8-21
8-39
8-22

NE5570: A Theory of Operation and Applications
Applications Using the NE5044 Encoder
Low Cost AID Conversion USing the NE5044
ApplicallOns Using the NE5045 Decoder
Applications USing the NE544 Servo Amplifier
Control System for Home Computer Robotics

Switched-Mode Power Supply
AN120
AN1211
AN122
AN1221
AN123
AN124
AN125
AN126
AN1261
AN1262
AN128
AN1291

An Overview of SMPS
A Microprocessor Controlled SWitched-Mode Power Supply
NE5560 Push-Pull Regulator ApplicallOn
SWitched-Mode Drives for DC Motors
NE5561 ApplicallOns
External SynchronlzallOn for the NE5561
Progress In SMPS Magnetic Component Optimization
ApplicallOns USing the SG3524
High Frequency Ferrite Power Transformer and Choke
Theory of Operation and ApplicallOns for SG1524C/2524C/3524C
Introduction to the Senes-Resonant Power Supply
TDA 1023: Design of Time-Proportional Temperature Controls

8-68
8-88
8-94
8-97
8-t07
8-112
8-250
8-214
8-t54
8-200
8-260
8-276

Tuning Circuits
AN157

Microcomputer Peripheral IC Tunes and Controls a TV Set SAB3035

4-55

Remote Control System
AN172
AN173
AN1731

Circuit DeSCription of the Infrared Receiver TDA3047/TDA3048
Low Power Preamplifiers for IR Remote Control Systems
SAA3004: Low Power Remote Control IR Transmitter and Receiver
Preamplifiers

5-50
5-52
5-10

Synch Processing and Generator
AN158
AN162
AN1621

Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and Graphics
Directives for a Print Layout DeSign on Behalf of the
IC Combination TDA2578A and TDA3651
Color Decoding and Encoding
AN155/A
AN1551

December 1988

Multi-Standard Color Decoder With Picture Improvement
Single-Chip Multi-Standard Color Decoder TDA4555/4556

1-16

9-57
9-25
9-30
to-3
to-44

Application Notes
by Part Numbers

Signetics

Linear Products

DAC08
MC1488
MC1489/A
MC1496/1596
MC3361
MC3403
NE5044

NE5045
NE5050
NE5080/5081
NE/SA/SE51 051 A

AN10l:
AN106:
AN113:
AN113:
AN189:
AN1992
AN160:
AN131:
AN1311:
AN1341:
AN132:
AN1951:

NE5517

AN195:
AN1161
AN1950:
AN1081:
AN116:
AN116:
AN1511:
AN1512:
AN116:
AN116:
AN1511:
AN190:
AN133:
AN144:
AN144l:
AN145:

NE5520

AN118:

NE5150/51 152
NE521
NE522
NE5230
NE527
NE529
NE531
NE542
NE544
NE5512/5514

AN1180
NE5521

AN1181:

NE5532/33/34
NE5539

AN1182:
AN142:
AN140:

NE555
NE556
NE/SE5560

AN170:
AN 170:
AN1211
AN122:
AN1221
AN125:

NE/SE5561

AN123:
AN124:
AN125:

NE/SE5562

AN125:

NE/SE5568

AN125:

December 1988

Applying the DAC08
USIng the DAC08 Without a Negative Supply
Using the MC1488/89 Line Drivers and Receivers
USIng the MC1488/89 Line Drivers and Receivers
Balanced ModulatorIDemodulator Applications Using
the MC1496/1596
Using the Signetics MC3361 Demonstration Board
Applications for the MC3403
ApplicatIons USIng the NE5044 Encoder
Low Cost AID Conversion Using the NE5044
Control System for Home Computer and Robotics
Applications Using the NE5045 Decoder
NE5050: Power Line Modem Application Board
Cookbook
ApplicatIons Using the NE5080, NE5081
12-Bit AID Converter Using the NE5105 Comparator
Exploring the Possibilities in Data Communications
NE5150/51/52 Family of Video 01 A Converters
Applications for the NE521/522/527/529
Applications for the NE521/522/527/529
Low Voltage Gated Generator: NE5230
All in One: NE5230
Applications for the NE521/522/527/529
Applications for the NE521/522/527/529
Low Voltage Gated Generator: NE5230
Applications of Low NOIse Stereo Amplifiers: NE542
Applications Using the NE544 Servo Amplifier
Applications for the NE5512
Applications for the NE5514
NE5517: General Description and Applications for
Use With the NE5517/A Transconductance Amplifier
LVDT Signal Conditioner: Applications Using the
NE5520
A MIcroprocessor-Based Servo-Loop for Linear
Position Control
NE5521 in a Modulated Light Source Design
Application
NE5521 in Multi-faceted Applications
Audio CIrcUIts USIng the NE5532/33/34
Compensation Techmques for Use WIth the
SE/NE5539
NE555 and NE556 Applications
NE555 and NE556 Applications
A Microprocessor Controlled Switched-Mode Power
Supply
NE5560 Push-Pull Regulator Application
Switched-Mode Drives for DC Motors
Progress in SMPS Magnetic Component
OptimIzation
NE5561 Applications
External Synchronization for the NE5561
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization

1-17

Vol 1

Vol 2

5-29
5-29

5-90
5-122
6-11
6-11

Vol 3

4-61
4-108
4-58
8-11
8-13
8-22
8-21
5-50
5-86
5-269
5-94
5-176
5-295
5-295
4-134
4-136
5-295
5-295
4-134

11-26

7-135
8-39
4-91
4-97
4-276
5-329
5-344
5-359
5-363
4-114
4-32

4-232
7-54
7-54
8-88
8-94
8-97
8-250
8-107
8-112
8-250
8-250
8-250

11-81

Signetics Linear Products
"

Application Notes by Part Numbers

Vol 1
NE/SAlSE5570
NE558
NE564

AN1281
AN171:
AN179
AN180.
AN1801:
AN181:

NE564

AN182.

NE565

AN183.
AN184:
AN185:
AN186
AN187'
AN188.
AN174
AN175
ANl12:
AN141.
AN1981:
AN1982:

NE566
NE567
NE570/571/SA571
NE572
NE587/589
NE592/5592
NE/SA602

NE/SA604A
NE/SA604A

AN1991:
AN1993

PNA7509

AN108:

SAA1057
SAA3004

AN196'
AN197.
AN1731:

SAB3035

AN157:

SG1524C

AN1261:

SG3524C

AN125:
AN126:
AN1261:
AN1262.

TDA1013A
TDA1023
TDA1072A
TDA1510

AN148:
AN1291:
AN1961:
AN1491:

TDA1515

AN1481:

TDA1520A
TDA2578

AN149:
AN1621:

TDA2595

AN158:
AN162:

TDA2653

AN162

TDA3047

AN172:
AN173:

TDA3048

AN172:
AN173:

December 1988

NE5570' A Theory of Operation and Applications
NE558 Applications
Circuit Descnptlon of the NE564
The NE564: Frequency SynthesIs
108MHz FSK Decoder With the NE564
A 6MHz FSK Converter Design Example for the
NE564
Clock Regenerator With Crystal Controlled
Phase-Locked VCO
CirCUit Description of the NE565
FSK Demodulator With NE565
CirCUit Description of the NE566
Waveform Generators With the NE566
Circuit Description of the NE567 Tone Decoder
Selected CirCUits USing the NES67
Applications for Compandors: NE570/571/SA571
Automatic Level Control: NE572
LED Decoder Drivers: USing the NE587 and NE589
USing the NE592/5592 Video Amplifier
New Low Power Single Sideband CirCUits (NE602)
ApplYing the OSCillator of the NE602 In Low Power
Mixer Applications
Audio DeCibel Level Detector With Meter Driver
High Sensitivity Applications of Low-Power RF /IF
Integrated CirCUits
An Amplifying, Level Shifting Interface for the,
PNA7509 Video D/A Converter
Single-Chip SyntheSizer for Radio TUning
AnalysIs and BasIc Application of the SAA 1057
SAA3004: Low Power Remote Control IR
Transmitter and Receiver Preamplifiers
Microcomputer Peripheral IC Tunes and Controls a
TV Set
High Frequency Femte Power Transformer and
Choke Design
Progress In SMPS Magnetic Component
Optimization
Applications USing the SG3524
High Frequency Femte Power Transformer and
Choke Design
Theory of Operation and Applications for SG 1524CI
2524C/3524C
Audio Amplifier With TDA1013A
Design of Time-Proportional Temperature Controls'
TDA1072A: Integrated AM Receiver
Car Radio Audio Power Amplifiers Up to 24W With
the TDA1510
Car Radio Audio Power Amplifiers Up to 20W With
the TDA1515
20W Hi-FI Power Amplifier With the TDA1520A
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651
Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and
Graphics Display Unit
A Versatile High-Resolution Monochrome Data and
GraphiCS Display Unit
Circuit DeSCription of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems
Circuit Description of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems

1-18

Vol 2

Vol 3

8-49
7-43
4-252
4-259
4-263
4-266
4-268
4-283
4-287
4-295
4-296
4-311
4-316
4-325
4-356
4-53
4-72

6-72
4-253

4-80
4-124

4-201

4-126

4-203
5-81

11-102

11-18

4-190
4-197
5-10
4-55
8-154
8-250
8-214
8-154
8-200
7-120
8-276
7-15
7-232
7-252
7-264
9-30
9-57
9-25
9-25
5-50
5-52
5-50
5-52

Signetics Unear Products

Application Notes by Part Numbers

Vol 1
TDA3505

ANI55/A;

TDA3651

AN1621;

TDA4555

ANI55/A;
AN1551;

TDA7000
TEAl 067

AN192;
AN193;
AN1942;
AN1943;

1lA758

December 1988

AN191;

Multi-Standard Color Decoder With Picture
Improvement
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651
Multi-Standard Color Decoder With Picture
Improvement
Single-Chip Multi-Standard Color Decoder TDA45551
4556
A Complete FM Radio on a Chip
TDA7000 for Narrowband FM Reception
TEAl 067; Application of the Low Voltage Versatile
Transmission Circuit
TEAl 067; Supply of Peripheral Circuits With the
TEA 1067 Speech Circuit
Stereo Decoder Applications Using the jJ.A 758

1-19

Vol 2

Vol 3
10-3
9-30
10-3
10-44

7-46
7-61
6-125
6-145
7-123

Signetics

Volume 2
Industrial

Linear Products

Preface
Product Status
Section 1:

GENERAL INFORMATION

Section 2:

QUALITY AND RELIABILITY

Section 3:

12 C SMALL AREA NETWORKS

Section 4:

AMPLIFIERS
Operational
High Frequency
Transconductance
Fiber Optics

Section 5:

DATA CONVERSION
Analog-to-Digital
Digital-to-Analog
Comparators
Sample-and-Hold
Position Measurement

Section 6:

INTERFACE
Line Drivers/Receivers
Peripheral Drivers
Display Drivers
Serlal-to-Parallel Converters

Section 7:

TIMERS AND CLOCKS

Section 8:

POWER CONVERSION/CONTROL

Section 9:

SYSTEM CONTROL

Section 10: PACKAGE INFORMATION
Section 11: SALES OFFICES

December 1988

1-20

Signetics

Volume 3
Video

Linear Products

Preface
Product Status
Section 1:

GENERAL INFORMATION

Section 2:

QUALITY AND RELIABILITY

Section 3:

12 C SMALL AREA NETWORKS

Section 4:

TUNING SYSTEMS
Tuner Control Peripherals
Tuning Circuits
Prescalers
Tuner IC

Section 5:

REMOTE-CONTROL SYSTEMS

Section 6:

TELEVISION SUBSYSTEMS

Section 7:

VIDEO IF

Section 8:

SOUND IF AND SPECIAL AUDIO PROCESSING

Section 9:

SYNCH PROCESSING AND GENERATION

Section 10: COLOR DECODING AND ENCODING
Section 11: SPECIAL-PURPOSE VIDEO PROCESSING
Video Modulator/Demodulator
AID Converters
0/ A Converters
SWitching
High Frequency Amplifiers
CCD Memory
Section 12: VERTICAL DEFLECTION
Section 13: SWITCHED-MODE POWER SUPPLIES FOR TV/MONITOR
Section 14: PACKAGE INFORMATION
Section 15: SALES OFFICES

December 1988

1-21

Cross Reference Guide by
Manufacturer

Signetics

Pin-for-Pin Functionally-Compatible *
Cross Reference by Manufacturer

Linear Products

Manufacturer Signetics
Manufacturer Part Number Part Number
AMD

Datel

Exar

Harris

AM26LS30PC
AM26LS31PC
AM26LS32PC
AM25LS33PC
AM6012DC
DAC-OBAQ
DAC-OBCN
DAC-OBCQ
DAC-OBEN
DAC-OBEQ
DAC-OBHN
DAC-OBHQ
DAC-08Q
LF198H
LF19BH
LF398H
LF39BH
LF398L
LF398L
LF398N
LF39BN
AM-453-2
AM-453-2C
AM-453-2M
DAC-UP10BC
DAC-UP8BC
DAC-UP8BM
DAC-UPBBQ

AM26LS30CN
AM26LS31CN
AM26LS32CN
AM26LS33CN
AM6012F
DAC-OBAF
DAC-OBCN
DAC-OBCF
DAC-OBEN
DAC-OBEF
DAC-OBHN
DAC-OBHF
DAC-OBF
LF198H
SE5537H
LF39BH
NE5537H
LF398D
NE5537D
LF39BN
NE5537N
NE5534/AF
NE5534/AF
SE5534/AF
NE5020N
NE5018N
SE5019F
SE5018F

XR-558CN
NE55BF
XR-558CP
NES58N
XR-558M
SE558F
XR-L567CN
NE567F
XR-L567CP
NE567N
XR-14BBCP
MC148BN
XR-1489/ACP MC1489/AN
XR-1524N
SG3524F
XR-1524P
SG3524N
XR-2524P
SG3524N
XR-3524N
SG3524F
XR-3524P
SG3524N
XR-455BCP
NE4558N
XR-5532/A N NE5532/AF
XR-5532/A P NE5532/AN
XR-5534/ A CN NE55341 AF
XR-55341 A CP NE55341AN
XR-55341 A M SE55341 AF
XR-6118CP
NE594N
XR-13600CP NE5517N
HA-2539N
HA-2420-2/8B
HA-2425N
HA-2425B
HA-5320B

NE5539N
SE5060F
NE5060N
NE5060F
NE5060F

Temperature
Range (OC) Package

o to
o to
o to
o to
o to
- 55

o to
o to
o to
o to
o to
o to
-55
- 55
- 55
o to
o to
o to
o to
o to
o to
o to
o to
- 55
o to
o to
- 55
-55

o to
o to
- 55
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
- 55
o to
o to

o to
- 55
o to
o to
o to

+70
+70
+70
+70
+70
to + 125
+70
+70
+70
+70
+70
+70
to + 125
to + 125
to + 125
+70
+70
+70
+70
+70
+70
+70
+70
to + 125
+70
+70
to + 125
to 125

Plastic
Plastic
Plasllc
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Metal Can
Metal Can
Metal Can
Metal Can
Plastic
Plastic
Plastic
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic

+70
+70
to + 125
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
to + 125
+70
+70

Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic

+70
to + 125
+70
+70
+70

Plastic
Ceramic
Plastic
Ceramic
Ceramic

Manufacturer Signetics
Manufacturer Part Number Part Number

Temperature
Range (OC) Package

HAI-5102-2
HAI-5135-2
HAI-5135-5
HAI-5202-5
HA3-51 02-5

SE5532/AF
SE5534/AF
NE5534/AF
NE5532/AF
NE5532/AN

Intersil

ADC0803LCD
ADCOa04
ADC0805
ICM7555CBA
ICM75551PA
ACM7555CP

ADC0803-1 LCF -40
ADCOa04-1 CN 0 to
ADCOa05-1 LCN-40
ICM7555CD
o to
ICM75551N
-40
ICM7555CN
o to

Motorola

AM26LS31 PCD AM26LS31CD
AM26LS31PC AM26LS31CN
AM26LS32PC AM26LS32CN
AM26LS32PCD AM26LS32CD
DAC-OBCD
DAC-OBCN
DAC-OBCQ
DAC-OBCF
DAC-OBED
DAC-08EN
DAC-OBEF
DAC-OBEF
DAC-OBHQ
DAC-OBHF
DAC-OBQ
DAC-08F

o to
o to
o to
o to
o to
o to
o to
o to
o to

+70
+70
+70
+70
+70
+70
+70
+70
+70
- 55 to + 125

Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic

LM2901N
LM311J-8
LM311N
LM324J
LM324N
LM339/A J
LM339/A N
LM35BN
LM393A1J
LM393A1N
MC1408L
MC140BP
MC14BBL
MC14B8P
MC1489/A L
MC14B9/A P
MC1496L
MC1496P
MC3302L
MC3302P
MC3361D
MC3361P
MC3403L
MC3403P
MC3410CL
MC3410L

-40 to +B5
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-40 to +B5
-40 to +B5
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
- 55 to + 125
o to +70
o to +70
o to +70
o to +70

Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic

MC3510L
NE565N
NE592F
NE592F
NE592N

1-22

LM2901N
LM311F
LM311N
LM324F
LM324N
LM339/AF
LM339/AN
LM358N
LM393/AF
LM393/AN
MC1408F
MC1408N
MC14B8F
MC148BN
MC14B9/AF
MC14B9/AN
MC1496F
MC1496N
MC3302F
MC3302N
MC3361D
MC3361N
MC3403F
MC3403N
MC3410CF
MC341OF
NE5410F
MC5410F
NE565N
NE592F-B
NE592F-14
NE592N-14

- 55
- 55
o to
o to
o to

to + 125
to + 125
+70
+70
+70

Ceramic
Ceramic
Ceramic
Ceramic
Plastic

to + 85
+ 70
to + 85
+70
to +85
+70

Ceramic
Plastic
Plastic
Plastic
Plastic
Plastic

Signetics Linear Products

Cross Reference Guide

Manufacturer Slgnetlcs
Manufacturer Part Number Part Number

National

Temperature
Range (OC) Package

SE592F
SE592F
SE592H

SE592F·8
SE592F·14
SE592H

ADC0803F
ADC0803N
ADC0805
ADC0820CCN
ADC0820CCD
ADC0820CD
DAC0800LCJ
DAC0800W
DAC0800LCN
DAC0801LCJ
DAC0801LCN
DAC0802W
DAC0802LCJ
DAC0802LCN
DAC0806LCJ
DAC0806LCN
DAC0807LCJ
DAC0807LCN
DAC0808LCJ

ADC0803·1 LCF-40 to +85
ADC0803·1 LCN-40 to + 85
ADC0805·1 LCN-40 to + 85
ADC0820CNEN 0 to + 70
ADC0820CSAN -40 to + 85
ADC0820CSEF - 55 to + 125
DAC·08EF
o to +70
DAC·08F
-55 to +125
DAC-08EN
o to +70
DAC·08CF
o to +70
DAC·08CN
o to +70
-55 to + 125
DAC·08AF
DAC·08HF
o to +70
DAC-08HN
o to +70
MC1408-6F
o to +70
MCI408·6N
o to +70
MC1408·7F
o to +70
MC1408·7N
o to +70
MC1408F
o to +70

DAC0808LCN
DAC0808LD
DS3691N
DS3691M
LF198H
,LF398H
LF398N
LM13600AN
LMI3600N
LM1458N
LM161H
LM161J
LM2524J
LM2524N
LM2901N
LM2903N
LM3089
LM319J
LM319N
LM324J
LM324N
LM324AD
LM324AN
LM339/AJ
LM339/AN
LM3524J
LM3524N
LM358H
LM358N
LM361H
LM361J
LM361N
LM393/AN
LM555J
LM555N
LM556J
LM556N
LM556CJ
LM556CN

MC1408N
MC1408F
AM26LS30CN
AM26LS30CD
SE5537H
NE5537H
NE5537N
NE5517N
NE5517N
MC1458N
SE529H
SE529F
SG3524F
SG3524N
LM2901N
LM2903N
CA3089N
LM319F
LM319N
LM324F
LM324N
LM324AD
LM324AN
LM339/AF
LM339/AN
SG3524F
SG3524N
LM358H
LM358N
NE529H
NE529D
NE529N
LM393/AN
NE555F
NE555N
SE556·1F
SE556·1N
NE556·1F
NE556·1N

Manufacturer Signetics
Manufacturer Part Number Part Number

- 55 to + 125 Ceramic
- 55 to + 125 Ceramic
- 55 to + 125 Metal Can

o to
o to
o to
o to

+70
+70
+70
+70
- 55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to + 125
o to +70
o to +70
-40 to +85
-40 to +85
- 55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70

NE565N
SE566N
NE566N
NE567N
1lA733CN
1lA741CF
IlA741CN
1lA741F
IlA74tN
1lA747CF
IlA747CN
1l747F
IlA747N
ICM7555CN
ICM7555CD
1lA080/DA
DAC·08F
1lA0801CDC MC1408F
1lA0801CPC MC1408N
1lA0801EDC DAC·08EF
DAC·08AF
1lA0801EPC
2M124F
1lA124J
1lA1458TC
MC1458N
MC1488F
1lA1488DC
MC1488N
1lA1488PC
1lA1489/A PC MC1489/AF
IlA14891 A PC MCI4891 AN
NE5537H
1lA198HM
1lA198RM
NE5537N

o to

+70
- 55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
- 55 to + 125
-55 to + 125
o to +70
o to +70
- 55 to + 125
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70

Plastic
Plastic
Plastic
Plastic
Plasuc
Ceramic
Plasuc
Ceramic
Plastic
Ceramic
Plasuc
Ceramic
Plastic
Plastic
Plasuc
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Plasuc
Ceramic
Plasuc
Ceramic
Plasnc
Metal Can
Plastic

,.,A2901DC
,.,A2901PC
1lA311RC
1lA324DC
1lA324PC
1lA3302DC
1lA3302PC
1lA339/ADC
1lA339/APC
1lA3403DC
1lA3403PC
1lA398HC
1lA398RC
1lA555TC
1lA556PC

-40 to +85
-40 to +85
o to +70
o to +70
o to +70
-40 to +85
-40 to +85
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70

Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
Plastic
Plastic

o to +70
-55 to + 125
o to +70
o to +70
- 55 to + 125
o to +70
- 55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70

Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic

LM565CN
LM566N
LM566CN
LM567CN
LM733CN
LM741CJ
LM741CN
LM741J
LM741N
LM747CJ
LM747CN
LM747J
LM747N
LMC555CN
LMC555CM

Ceramic
Plasuc
Plastic
Plasuc
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plasuc
Ceramic
Plasuc
Ceramic
Plasuc
Ceramic
Plastic
Ceramic
Plastic
Plasnc
Metal Can
Metal Can
Plastic
Plasnc
Plastic
Plastic
Metal Can
Ceramic
Ceramic
Plasuc
Plastic
Plastic
PlastiC
Ceramic
PlastiC
Ceramic
Plastic
Plastic
PlastiC
Ceramic
PlastiC
Ceramic
Plastic
Metal Can
Plastic
Metal Can

1lA723DC
1lA723DM
1lA723PC
1lA733DC
1lA733DM
1lA733PC
1lA741NM
1lA741RC
1lA741TC
1lA747DC
1lA747PC
UC3842D
UC3842J
UC3842N
UC2842D
UC2842J
UC2842N

Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic

1-23

Temperature
Range (OC) Package

LM2901F
LM2901N
LM311F
LM324F
LM324N
MC3302F
MC3302N
LM339/AF
LM339/AN
MC3403F
MC3403N
SE5537H
SE5537N
NE555N
NE556·1N,
NE556N
1lA723CF
1lA723F
1lA723CN
1lA733F
1lA733F
1lA733N
1lA741N
1lA741CF
1lA741CN
1lA747CF
1lA747CN
UC3842D
UC3842FE
UC3842N
UC2842D
UC2842FE
UC2842N

•

Signetics Unear Products

Cross Reference Guide

Manufacturer Signetics
Manufacturer Part Number Part Number

Temperature
Range (OC) Package

Manufacturer Signetics
Manufacturer Part Number Part Number
LM311D
LM311J
LM311JG
LM324D
LM324J
LM339!AJ
LM339/AN
LM358P
LM393/A P
MC1458P
NE55321A JG
NE5532/A P
NE55341 A JG
NE5534/A P
NE555JG
NE555P
NE556P
NE556J
NE55SN
NE592
NE592A
NE592J
NE592N
SA556P
SE55341 A JG
SE555JG
SE55SJ
SE55SN
SE592
SE592J
SE592N
SN55107AJ
SN55108AJ
SN75107AJ
SN75107AN
SN75108AJ
SN75108AN
SN75186J
SN75188N
SN75189AJ
SN75189AN
SN75189J
SN75189N
TL592A
TL592P
1lA723CJ
1lA723CN
1lA723MJ

LM311D
LM311F
LM311FE
LM324N
LM324F
LM339/AF
LM339/AN
LM358N
LM393/AN
MC1458N
NE55321 AF
NE5532/AN
NE55341AF
NE5534/AN
NE555N
NE555N
NE556N
NE556·1F
NE55S·1N
NE592N14
NE592F14
NE592F
NE592N·14
SA556N
SE5534! AF
SE555N
SE55S·1F
SE556·1N
SE592N14
SE592F·14
SE592N·14
NE521F
SE522F
NE521F
NE521N
NE522F
NE522N
MCI488F
MCI468N
MC1489AF
MCI489AN
MC1489F
MCI489A
NE592F14
NE592NB
1lA723CF
1lA723CN
1lA723F

o to
o to
o to
o to
o to

+70
+70
+70
+70
+70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-40 to +85
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
o to +70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
- 55 to + 125

Plastic
Ceramic
Ceramic
Plastic
Ceramic
CeramIC
Plastic
Plastic
Plastic
PlastiC
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
PlastiC
Ceramic
PlastiC
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic

UC3524J
UC3524N

SG3524F
SG3524N

o to +70
o to +70

Ceramic
Plastic

UC1842J
UCI842N
IIPC1571C

UC1842FE
UC1842N
NE571N

-55 to + 125 Ceramic
-55 to + 125 Plastic
o to +70 Plastic

PMI

CMp·05GP
CMP-05CZ
CMp·05BZ
CMp·05GZ
CMP·05FZ
DACI408A-6P
DACI408A·SQ
DACI408A·7N
DACI408A·7Q
DACI408A·8N
DACI408A-8Q
DACI508A-8Q
DAC312FR
OP27BZ
OP27CZ
PM747Y
SMp·l0AY
SMp·l0EY
SMP·llAY
SMP·llEY

NE5105N
SE5105F
SE5105F
SA5105N
SA5105N
MC1408-6N
MC1408-6F
MC1408·7N
MC1408·7F
MC1408·8N
MC1408-8F
MC1408-8F
AMS012F
SE5534AFE
SE5534FE
1lA747N
SE50S0F
NE50S0N
SE5060F
NE50S0N

o to +70
-55 to +125
- 55 to + 125
-40 to +85
-40 to +85
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
o to +70
- 55 to + 125
-55 to + 125
-55 to + 125
- 55 to + 125
o to +70
-55 to + 125
o to +70

Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
PlastiC
Ceramic
PlastiC
Ceramic
PlastiC

Raytheon

RC4805DE
RC4805EDE
RM4805DE
RM4805ADE
RC5532! A DE
RC5532! A NB
RC5534! A DE
RC5534! A NB
RM5532! A DE
RM5534! A DE

NE5105N
NE5105AN
SE5105F
SE5105AF
NE5532!AF
NE5532! AN
NE5534!AF
NE5534!AN
SE5532!AF
SE5534!AF

o to
o to

+70
+70
-55 to +125
-55 to + 125
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to +125

Plastic
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic

Silicon
General

SG3524J
SG352SN

SG3524F
SG3526N

o to
o to

+70
+70

Ceramic
Plastic

Sprague

UDNS118A
UDNS118R
ULN3524A
ULN8142M
ULN8160A
ULN8160R
ULN8161M
ULN8168M
ULN8564A
ULN8564R
ULS8564R

SA594N
SA594F
SG3524
UC3842N
NE5560N
NE55S0F
NE5561N
NE5568N
NE564N
NE564F
SE564F

-40 to +85
-40 to +85
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125

Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Ceramic

TI

ADC0803N
ADC0804CN
ADC0805N
LMlllJ

ADC0803·1 LCN-40 to +85 Plastic
ADC0804·1 CN 0 to + 70
Plastic
ADC0805·1 LCN-40 to +85 Plastic
LMlllF
-55 to + 125 Ceramic

NEC

Unltrcde

Temperature
Range (OC) Package

"THERE MAY BE PARAMETRIC DIFFERENCES BETWEEN SIGNETICS'
PARTS AND THOSE OF THE COMPETITION.

1-24

Cross Reference Guide by Numeric Usting
NUMERIC
DAC-OII

08031
08041
0805

DESCRIPTION
B-BiI DIA
Co..-

8-811 AID

Converter

SlGNETlCS

IJAC.08F
DAC-08AF
DAC-08CF. CN
NE5007F. N
DAC-08ED. EN
NE5008D. F. N
SE5OO8F
DAC-OIIHF. HN
NE5009F. N
SE5009F

ANALOG
DEVICES
ADDAC-08

DAC-08

DAC-0800
DAC-0801
DAC-0802

NEe

PM!

pl'C624

DAC-08

RAY·
THEON

RCA

SGS/
THOMSON

SILICON
GENERAL

SPRAGUE

TI

O1lIEAS

DATEL IJAC.08
AMD IJAC.08
Hams-HI5618

III

VoI1age
ComparalOf

LM111FE

ADttt

Dual
ComparalOr

LM119F

Quad OP Amp

LM124F, N

ADC0803
ADC0804
ADC0805

ADCOB20
....111

L.Ml11

LM111

LTI19

[ntarSll
ADC0803
0840
OB05

M",m
Maxl50

LMl11

PMIII

LMI19

PMI19

LMIII

LM124

LT1014

LMI24

XRI3600

NE5517AN

LMI24

CAI24

~

SGI24

LM124

c:

LMI39

...
cr

Z

3

LMI3800IA

CD

NE5517D. N

'"

LMI39AF
LMI39F. N

14081

8-811D/A

1508

Convertor

MCI408-Ie-and.
-Amp

LFI98FE, H
SE5537FE, H

211

Voltage
Compafator

LM211D. FE. N

219

IJualCo_

LM2190, F, N

Co_

LII224D. F. N
SA534D. F. N

jlA224

LM239AN
LM239F. N

jlA239

224
239

Quad Op Amp

Quad Voltage

()
HITACHI

".,98

UNEAR
TECH

MOTOROLA

LM211

HA17224

NEC

PIli

~YTHEO

RCA

SGSI
THOMSON

SlUCON
GENERAL

SPRAGUE

n

OTHERS
AMO
LF198
Hams
HA2430

lF100

LFI98

AD211

NATIONAL

LM211

PM211

SG211

LM219

TOE0119

LM224

LM224

LM224

LM239

LM23l1

PM239
CMP-04

LM239

Improved SMPS

ConIroIIC

::J

n

CD

(j)

LM239

CS2524

SG2524

Unrtrode
UC2524

258

DuaIOp Amp

25n

Sync W11h Vert Osc

2593
28lS31

~

2901
2902

and Onver
Honzontal

Combmabon
Quad Hr-Speed

!me Dnvar

LM258N
SA532O. N

jlA258

HA17258

LM258

LM258

,.PC258

0058

LM258

TDA2577A

TDA2577

TDA2593

TDA2593

AM28LS31
CD. CN. IN. MN

AM28LS31

AM28lS31

Z

P~

TA2593
AM28lS31

Quad Voltage
Comparator

LM2901D. F. N

jIA2901

LM2901

LM2901

LM2901

Quad Op Amp

LM2902D, N
SA534D. F. N

jIA2902

LM2902

LM2902

LM2902

2903

Dual Voltage
Comparator

LM29/l3D. FE. N

pA2903

LM2903

LM2903

LM2903

2904

Dual Op Amp

LM2904D. N

jIA2904

LM2904

LM2904

LM2904

293

Dual Comparator

LM293AFE. AN
LM293FE. N

LM293/A

LM293/A

3089

FM IF System

CA3089N

Co_

jlA311

0011

311

Voltage Comparator

00110. FE. N

319

High-Speed
Dual

LM319D. F. N

324

Quad Op Amp

LM324AD. AN
00240. F. N

3302

Quad Voltage
Comparator

MC3302D. F. N

jIA3303

MC3302

3303

Quad Op Amp

MC33OOF. N

jIA3303

MC3303

3381

Low Power FM IF

MC3381D. N

339

Quad Voltage
Comparator

LM339AF. AN
LM339D. F. N

34031
3503

Quad

Op Amp
_.

MC3403D. F. N
MC3505. F. N

jlA324

HA17324

LM324/A

_03

LM339/A
MC3403
MC3503

iii"

(Q

0019

LM324/A

lM324

LM324

MC3303

M3303

Samsung
LM324

Sam"""
MC3361
LM339/A

,.PC339

PM339

LM339
RM4137

CA339

LM339

LM339

MC3403
MC3503

MC3403
MC3503

3

....
0"
,....
CD

S"

LM311

,.Pe319

c

-

LM293/A

MC3381
jlA339

AMO
AM25lS31

00069

0011
LM319

c

a:CD
~

LM258

DS28LS31

LM3089

CD

(j)

LM224

CA239

SG2524CN

;:0

CD'

LM211

Chony
2524

aenen

:5
:;J

~

g
c

:;J

a>

Q
"U

8.c
a-

Cross Reference Guide by Numeric Listing (Continued)
NUMERIC

DESCRIPTION

34101
3510

10-81\ D/A
Converter

SMPS Control

3524

ClfCUlt

ANALOG
DEVICES

SIGNETICS

EXAR

FAIRCHILD

HITACHI

LINEAR
TECH

MC3410F
MC3410CF
MC3510F

MOTOROLA

NATIONAL

NEC

PMI

RAYTHEO

RCA

SGSI
THOMSON

~

SILICON
GENERAL

SPRAGUE

TI

XR3524

LT3524

OTHERS

Hams
HI-S6ID

MC3410/C
Me3S10

8G35240, F, N

CA3524

LM3524

8G3524

8G3524

ULN3524

8G3524

Cherry
C83524

Umlrode
UC3524

Improved SMPS
Control Circuli

3524C

SMPS

SG3526F, N

358

Dual up Amp

LM358AD, AN
LM358D, N
NE5320, N

361

See 529
SMPS

3842

Ie

387

See 542

393

Dual Comparator

8G3526

LM358/A

HA17358

8G3526

LM358/A

/lPC358

CA358/A

OP-221

398

4558

LM358

UC3526

LM35B/A

Sanyo
LA6358

;:c

-

CD
CD
CD
~

:::J

(')

CD

(j)

c

0.:
CD

UC3842AN

UC3842N, D

Umtrode
UC3842N/D
Cherry
CS3842AN

SG3842M

0-

-<
Z

c
LM393AFE, AN
LM3930, N
LM393FE-Sole
Source

LM393/A

HA17393

Sample-and-Hold
Amp

LF398D, FE, H, N
NE5537D, FE, H, N

Dual General
Purpose Op Amp

NE45580, FE, N
SA4558FE, N
SE4558FE, N

5007

See OAC-08C

5008

See DAC-08E

5009

See OAC-08H

5018

8-Brt Converter
Voltage Out

NE5018D, F, N
SE5018F

5019

8-Bit D/A
Converter
Voltage Out

NE5019F, N
SE5019F

5020

10-Blt D/A
Converter
Voltage Out

NE5020F, N

5060

High-Speed
PreCISion
Sampleand-Hold Amp

NE5060F

5105

High-Speed
PrecISion
Comparator

NE51050, N
SA5105AN
(NE510SAO,
AN-soie source)

I

Umtrode

ULN8126

LM393/A

LM393

LM393/A

r\:,
--J

Unllrode
UC3524A

8G35248

8G3524C, D, N

3526

()
0
en
en

LF398

pA398

XR4588

LF398

Sanyo
LA6393

AMD
LF398
Hams
HA2425

SMP-l0

MC4558

RC4558

3

CD
~

0"
c::
en
-+

:r
(Q

AMD
A.M6081
Datel
DAC pP8B

,

Dalel
DAC
pP8BM

I
AD583

Hams
HA2420
HA2425
HA5320

SMP-l0
SMP-l1

CMP-05

I

Datel
OAC pPl0

RCA805

•

en
«5"
=>

~

g

c:
=>

-..



::J

0

(j)

c

a:

LM387

NE542N

5532

Hams

AC4531

NES31 FE, H, N

See 13600

low NOise Op Amp

FAIRCHILD

SE5118F

Dual low NOIse Op
Amp

5534

EXAR

NE5118F, N

5517

CD

ANALOG
DEVICES

()

Hams
HA35102-5

OP-27

RC5534IA

NE5534/A

SE5534AFE, AN
SE5534FE, N

Z

c

NE5533/A

XR5534

~

Analog
Systems
MA332
Datel
AM453·2C
Hams
HA5101/11

3

:r


0"
r-

Cij"

(Q

5537

See 398

5539

Fast Op Amp

NE5539D, F, N
SE5539, F, H

555

Timer

NE555D, FE, N
SA555D, N
SE555CN, FE, N

556

Dual Timer

NE556D, F, N
SA556N
SE556CN, F, N

5580

SMPS Control
CirCUIt

NE5560D, F, N
SE5560F, N

UlN8160
'diSC

5561

SMPS Control
CirCUIt

NE5561D, FE, N
SE5561 FE, N

ULN8161
*dlsc

5568

SMPS Control
Clfct.ut

NE5568D, N

ULN8168
'dlsc

Hams
HA2539

AD5539

XR555

pA555

pA556

HA17555

NE555
MC1455

LM555

NE556
MC1456

LM556

pPC555

RC555

CA555

NE555

NE555

InterSl1
NE555

NE556

NE556

Samsung
NE556
Cherry
CS5560C
IPS 'disc
IP5560C

Ch<>ny
CS5561
IPS 'diSC
IP5561C
Cherry
CS5588
IPS 'dlsc
IP5568C

en
cO"
:J

~

£l

c:

:J


Q
-U

a

(\)

c
0
it

Q.

(j)

c
0:
(\)

NE571D, F, N
(SA571D, F, N-sole

IlPC1571C

0"

-<
Z

NE592 014, DB,

'"


o

I!?

()

n

r-

in·

s·

CO

::J

~

c

(I)

~
"U

c
0

Signetics

SO Availability List

Linear Products

PART
NUMBER

SMD
PACKAGE

ADC0820D
'DAC08ED
'LF398D
LM1870D
LM2901D
LM2903D
LM311D
LM319D

SOL-20
SO-16
SO-14
SOL-20
SO-14
SO-8
SO-8
SO-14

LM324AD
LM324D
LM339D
LM358AD
LM358D
LM393D
'MC1408-8D
MC1458D
MC1488D
MC1489D
MC1489AD
MC3302D
MC3361D
MC3403D

SO-14
SO-14
SO-14
SO-8
SO-8
SO-8
SO-16
SO-8
SO-14
SO-14
SO-14
SO-14
SOL-16
SO-14

NE4558D
'NE5018D
'NE5019D
'NE5036D
NE5037D
NE5044D

SO-8
SOL-24
SOL-24
SO-14
SO-16
SO-16

NE5045D
NE5090D
NE5105/AD

SO-16
SOL-16
SO-8

NE5170A
NE5180A
NE5204D
NE5205D
NE521D

PLCC-28
PLCC-28
SO-8
SO-8
SO-14

NE5212D8

SO-8

NE522D

SO-14

NE5230D
NE527D

SO-8
SO-14

NE529D

SO-14

February 1987

PART
NUMBER

DESCRIPTION

8-Bit CMOS AID
8-Bit DI A Converter
Sample-and-Hold Amp
Stereo Demodulator
Quad Volt Comparator
Dual Volt Comparator
Voltage Comparator
High-Speed Dual
Comparator
Quad Op Amp
Quad Op Amp
Quad Volt Comparator
Dual Op Amp
Dual Op Amp
Dual Comparator
8-Bit DI A Converter
Dual Op Amp
Quad Line Driver
Quad line Receiver
Quad Line Receiver
Quad Volt Comparator
Low Power FM IF
Quad Low Power Op
Amp
Dual Op Amp
8-Bit DI A Converter
8-Bit DI A Converter
6-Bit AID Converter
6-Bil AID Converter
Prog 7-Channel
Encoder
7-Channel Decoder
Address Relay Driver
High-Speed
Comparator
Octal Line Driver
Oclal Line Receiver
High-Frequency Amp
High-Frequency Amp
High-Speed Dual
Comparator
Transimedance
Amplifier
High-Speed Dual
Comparator
Low Voltage Op Amp
High-Speed
Comparator
High-Speed
Comparator

1-31

SMD
PACKAGE

NE532D
'NE544D
'NE5512D
'NE5514D
NE5517D
NE5520D
'NE5532D

SO-8
SOL-16
SO-8
SOL-16
SO-16
SOL-16
SOL-16

'NE5533D
NE5534AD
NE5534D
NE5537D
NE5539D

SOL-16
SO-8
SO-8
SO-14
SO-14

NE555D
NE556D
NE5560D
NE5561D
NE5562D
NE5568D
NE558D
NE5592D
NE564D
'NE565D
NE566D
NE567D
NE568D
NE571D
NE572D
'NE587D

SO-8
SO-14
SO-16
SO-8
SOL-20
SO-8
SOL-16
SO-14
SO-16
SO-14
SO-8
SO-8
SOL-20
SOL-16
SOL-16
SOL-20

'NE589D

SOL-20

NE5900D
NE592D14
NE592D8
NE592HD14
NE592HD8
'NE594D
NE602D

SOL-16
SO-14
SO-8
SO-14
SO-8
SOL-20
SO-8

NE604D

SO-16

NE605
NE612D

SOL-20
SO-8

NE614D

SO-16

'PCD3311TD

SO-16

DESCRIPTION

Dual Op Amp
Servo Amp
Dual HI-Perf Op Amp
Quad Hi-Perf Op Amp
Dual HI-Perf Amp
LVDT Signal Cond Ckt
Dual Low-Noise Op
Amp
Low-Noise Op Amp
Low-NOise Op Amp
Low-Noise Op Amp
Sample-and-Hold Amp
HI-Freq Amp
Wldeband
Single Timer
Dual Timer
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
Quad Timer
Dual Video Amp
Hi-Frequency PLL
Phase Locked Loop
Function Generator
Tone Decoder PLL
PLL
Compandor
Prog Compandor
7 Seq LED Driver
(Anode)
7 Seq LED Driver
(Cath)
Call Progress Decoder
Video Amp
Video Amp
HI-Gain Video Amp
Hi-Gain Video Amp
Vac Fluor Disp Driver
Double Bal Mlxerl
OSCillator
Low Power FM IF
System
FM IF System
Double Balanced
Mixer/Osclliator
Low Power FM IF
System
DTMF/Melody
Generator

Signetics Linear Products

SO Availability List

PART
NUMBER

SMD
PACKAGE

PCD3312TD

SO-8

PCD3315TD
PCD3360TD
PCF2100TD

SOL-28
SO-16
SOL-28

PCF2111TD

VSO-40

PCF2112TD

VSO-40

PCF8570TD
PCF8571TD
PCF8573TD
PCF8574TD
PCF8576TD
PCF8577TD

SO-8
SO-8
SO-16
SO-16
VSO-56
VSO-40

SA5105/AD

SO-8

SA5230D
SA5212D8
SA532D
SA534D
SA555D
SA571D
SA572D
'SA594D
SA602D

SO-8
SO-8
SO-8
SO-14
SO-8
SOL-16
SOL-16
SOL-20
SO-8

SA604D

SO-16

PART
NUMBER

DESCRIPTION
DTMF/Melody
Generator With ICC
Repertory Pulse Dial
Progress Tone Ringer
LCD Duplex Driver
(40)
LCD Duplex Driver
(64)
LCD Duplex Driver
(32)
Static RAM (256 x 8)
1K Serial RAM
Clock/Timer
Remote I/O Expander
MUX/Static Driver
32-/64-Segment LCD
Driver
High-Speed
Comparator
Low Voltage Op Amp
Transimpedance Amp
Dual Op Amp
Dual Op Amp
Single Timer
Compandor
Compandor
Vac Fluor Disp Driver
Double Bal Mixer/
Oscillator
Lower Power FM IF
System

SMD
PACKAGE

SAA3004TD
SG3524D
TDA1001BTD
TDA1005ATD
TDA3047TD
TDA3048TD
TDA5040TD

SOL-20
SO-16
SO-16
SO-16
SO-16
SO-16
SO-8

TDA7010TD
TDA7050TD
TDD1742TD
ULN2003D
ULN2004D
IlA723CD
IlA741CD
IlA747CD

SO-16
SO-8
SOL-28
SO-16
SO-16
SO-14
SO-8
SO-14

DESCRIPTION
R/C Transmitter
SMPS Control Circuit
Noise Suppressor
Stereo Decoder
IR Preamp
IR Preamp
Brushless DC Motor
Driver
FM Radio Circuit
Mono/Stereo Amp
Frequency Synthesizer
Transistor Array
Transistor Array
Voltage Regulator
Single Op Amp
Dual Op Amp

NOTE:
* Non~standard pinout.

NOTE:
For Information regarding additional SO products released since the publication of this document, contact your local Signetics Sales Office.

February 1987

1-32

Signetics

Ordering Information
for Prefixes ADC, AM, AU, CA,
DAC, ICM, LF, LM, MC, NE, SA,
SE, SG, I1A, UC

Linear Products

Signetics' Linear integrated circuit products may be ordered by contacting either
the local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors. A complete listing is
located in the back of this manual.

Table 1_ Part Number Description
PART NUMBER

CROSS REF
PART NO.

!':!,E..§...5~1.!':!

PRODUCT
DESCRIPTION

PRODUCT
FAMILY

LF398

LIN

Minimum Factory Order:

C"·'' " "''

Descnption of
Product Function

Commercial Product:
$1000 per order
$250 per line item per order
Military Product:
$250 per line item per order

_

Linear Product Family

Table 1 provides part number information concerning Signetics originated
products.
Table 2 is a cross reference of both the
old and new package suffixes for all
presently existing types, while Tables 3
and 4 provide appropriate explanations
on the various prefixes employed in the
part number descriptions.

~ Package Descriptions -

Device Number
Device Family and Temperature Range Prefix Tables 3 & 4

As noted in Table 3, Signetics defines
device operating temperature range by
the appropriate prefix. It should be noted, however, that an SE prefix (-55°C to
+ 125°C) indicates only the operating
temperature range of a device and not
its military qualification status. The military qualification status of any Linear
product can be determined by either
looking in the Military Data Manual and/
or contacting your local sales office.

December 1988

See Table 2

1-33

See

Signetics Linear Products

Ordering Information

Table 2. Package Descriptions
OLD

NEW

A, AA
A

N
N·14

B, BA

N
D

F

F

I,IK

I

K
L

H
H

NA, NX

N

Q, R

Q

T, TA
U
V
XA
XC
XC
XL, XF

H
U
N
N
N
N
N
A
EC
FE

December 1988

PACKAGE
DESCRIPTION
14·lead plastic DIP
14·lead plastic DIP
(selected analog
products only)
16·lead plastic DIP
Microminiature
package (SO)
14·, 16·, 18·, 22·,
and 24·lead
ceramic DIP
(Cerdip)
14·, 16·, 18·, 22·,
28·, and 4·lead
ceramic DIP
10·lead T0-100
10·lead high· profile
TO·100 can
24·lead plastic DI P
10·, 14·, 16·, and
24·lead ceramic
flat
8·lead TO·99
SIP plastic power
8·lead plastic DIP
18·lead plastic DI P
20·lead plastic DIP
22·lead plastic DI P
28·lead plastic DIP
PLCC
TO·46 header
8·lead ceramic DIP

Table 3. Signetics Prefix and
Device Temperature
PREFIX

DEVICE TEMPERATURE
RANGE

NE
SE
SA

o to +70·C
-55·C to +125·C
-40·C to + 85·C

Table 4. Industry Standard Prefix
PREFIX
ADC
AM
CA
DAC
ICM
LF
LM
MC
NE
SA
SE
SG
p.A
UC

DEVICE FAMILY
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
linear
Linear
Linear
linear
Linear

Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry

1-34

Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard

Signetics

Ordering Information
for Prefixes HE, OM, PC, PN,
SA, TO, TE

Linear Products

Signetics' integrated circuit products
may be ordered by contacting either the
locai Signetics sales office, Signetics
representatives and/or Signetics authorized distributors.

Minimum Factory Order:
Commercial Product:

$ 1000 per order

$ 250 per line item per order
Table 1 provides part number information concerning Signetics/Philips integrated circuits.
Table 2 provides package suffixes and
descriptions for all presently existing
types. Letters following the device number !lQ! used in Table 2 are considered
to be part of the device number.
Table 3 provides explanations on the
various prefixes employed in the part
number descriptions. As noted in Table
3, Signetics/Philips device operating
temperature is defined by the appropriate prefix.

OPERATING TEMPERATURE:
The third letter of the prefix, in a threeletter prefix, is the temperature designator.
The letters A to F give information about
the operating temperature:
A: Temperature range not speCified.
See data sheet.
e.g. TDA2541N
B: 0 to +70°C
e.g. PCB8573PN
C: -55°C to + 125°C
e.g. PCC2111 PN
D: -25°C to + 70°C
e.g. PCD8571 PN
E: -25°C to +85°C
e.g. PCE2111 PN
F: -40°C to + 85°C
e.g. PCF2111 PN

December 19B8

Table 1_ Part Number Description
PART
NUMBER

PRODUCT
FAMILY

1

l

T 0 A 2 54 1 N

PRODUCT
DESCRIPTION

LIN

Video IF Amplifier
LDescnption of
Product Function
Product Family Linear

Package Description - See Table 2A
'---_.- Device Number
'-------Device Family and Temperature Range Prefix-See Table 3A

Table 2_ Package Description
SUFFIX

PN

PACKAGE DESCRIPTION

B-, 14-, 16-, 18-. 20-, 24-, 2B-, 40-lead plastiC DIP
Microminiature Package (SO)
14-, 16-, lB-, 22-, 24-lead ceramic DIP
Single in-line plastic (SIP) and SIP power packages

TO

OF
U

Table 3_ Device Prefix
PREFIX

DEVICE FAMILY

HEx
OM

CMOS circuit
Linear circuit

PCX
PNx

CMOS circuit
NMOS circuit

SAx
TDx
TEx

Digital circuit
Linear circuit
Linear circuit

1-35

I

Signetics

Section 2
Quality and Reliability

I

•

Linear Products

INDEX
Zero Defects program ..................... :::::::::::::::::::::::::::::::::.:::::::....
Signetics
Linear DIvIsion Lmear Process Flow .............. .

2-3
2-7

Signetics

Quality and Reliability

Linear Products

SIGNETICS' ZERO DEFECTS
PROGRAM
In recent years, American industry has demanded increased product quality of its IC
suppliers in order to meet growing International competitive pressures. As a result of this
quality focus, it IS becoming clear that what
was once thought to be unattainable - zero
defects - is, in fact, achievable.
The IC supplier committed to a standard of
zero defects provides a competitive advantage to today's electronics OEM. That advantage can be summed up In four words:
reduced cost of ownership. As IC customers
look beyond purchase price to the total cost
of doing business with a vendor, It is apparent
that the quality-conscious supplier represents
a viable cost reduction resource. Consistently
high quality circuits reduce reqUirements for
expensive test equipment and personnel, and
allow for smaller inventories, less rework, and
fewer field failures.

REDUCING THE COST OF
OWNERSHIP THROUGH TOTAL
QUALITY PERFORMANCE
Quality involves more than just IC's that work.
It also includes cost-saving advantages that
come with error-free service - on-time delivery of the right quantity of the right product at
the agreed-upon price. Beyond the product,
you want to know you can place an order and
feel confident that no administrative problems
will arise to tie up your time and personnel.
Today, as a result of Signetics' growing
appreciation of the concern with cost of
ownership, our quality improvement efforts
extend out from the tradlllOnal areas of product conformance into every administrative
function, including order entry, scheduling,
delivery, shipping, and invoicing. Driving this
process is a Corporate Quality Improvement
Team, comprised of the president and hiS
staff, which oversees the activities of 30 other
Quality Improvement Teams throughout the
company.

LINEAR PRODUCT QUALITY
Signetics has put together a winning process
for the manufacturing of Linear Integrated
Circuits. The circuits produced by our Linear
Division must meet rigid criteria as defined In
our design rules and as evaluated through
product characterization over the device operating temperature range.
December 1988

Product conformance to specification IS measured throughout the manufacturing cycle.
Signetics calls the first submittal to a Product
or Quality Assurance gate our Estimated
Process Quality or EPQ. It IS an internal
measure used to drive our Quality Improvement Programs toward our goal of Zero
Defects. All product acceptance sampling
plans have zero as their acceptance criteria.
Only shipments that demonstrate zero defects dunng these acceptance tests may be
shipped to our customers. This IS in accordance With our commitment to our Zero
Defect policy.
Our standard is Zero Defects and our customers' statistiCS and awards for outstanding
product quality demonstrate our advance toward thiS goal. Nowhere IS this more eVident
than at our Electrical and Visual-Mechanical
Outgoing Product Assurance inspection
gates. Over the past eight years, the measured defect level at the first submiSSion to
Electrical Product Assurance for Linear products has dropped from over 4000PPM (0.4%)
to under 50PPM (0.005%) (See Figure la).
Similarly our Visual-Mechanical (body defects, lead bend, etc.) defect level has improved remarkably (see Figure 1b). The results from our Quality Improvement Program
have allowed Signetics to take the industry
leadership position with its Zero Defects limIted Warranty policy. No longer is it necessary
to negotiate a mutually acceptable AQL between buyer and Signetics. Signetlcs will
replace any lot in which a customer finds one
verified defective part.

QUALITY DATABASE
REPORTING SYSTEM - QA05
The capabilities of our manufactunng process
are measured and the results are recorded
through our corporate-wide QA05 database
system. The QA05 system collects the results
on all finished lots and feeds this data back to
concerned organizations where appropriate
corrective actions can be taken. The QA05
reports Estimated Process Quality (EPQ) data
which are the sample inspection results for
first submittal lots to Quality Assurance inspection for electrical, visual/mechanical,
hermelicity, and documentation. Data from
this system is available upon request and IS
dlstnbuted routinely to our customers who
have formally adopted our Ship-to-Stock program.

2-3

CUSTOMER/VENDOR
COOPERATION IS AT THE
HEART OF ZERO DEFECTS
AND REDUCED COSTS
Working to a zero defects standard requires
that emphasis be conSistently placed, not on
"catching" defects, but on preventing them
from ever occurring. This strong preventive
focus, which demands that quality be "built-in"
rather than "inspected in," includes a much
greater attention to ongoing communication on
quality-related issues. At Signetics, a focus on
this cooperative approach has resulted In better service to all customers and the development of two innovative customer/vendor programs: Shlp-to-Stock and Self-Qual.

Signetics' Shlp-to-StoCk
Program
Shlp-to-Stock is a jOint program between
Signetics and a customer which formally
certifies specific parts to go directly into
inventory or to the assembly line from the
customer's receiving dock without incoming
inspection. This program was developed at
the request of several major customers after
they had worked with us and had a chance to
experience the data exchange and joint corrective action that occurs as part of our
quality improvement program.
The key elements of the Ship-to-Stock program are:
• Signetlcs and customer agree on a list
of products to be certified, complete
device correlation, and sign a
specification.
• The product Estimated Product Quality
(EPQ) must be 300ppm or less for the
past 3 months.
• Signetics will share Quality (QA05) and
Reliability data on a regular basis.
• Signetics will alert Ship-to-Stock
customers of any changes in quality or
reliability which could adversely impact
their product.
Any customer interested in the benefits of the
Ship-to-Stock program should contact his
local Signetics sales office for a brochure and
further details.
As a result of their participation In the Ship-toStock Program, many of our customers have
eliminated costly incoming testing on selected ICs. We will work together with any customer interested to establish a Ship-to-Stock
Program, and identify the products to be
included in the program and finalize all neces-

Signetics Linear Products

Quality and Reliability

ting continuous-flow manufactunng and eliminating the need for expensive Inventories.
PPM (Parts per Million)

Signetics Self-Qual Program

500

like Ship-to-Stock, our Self-Qual Program
employs a cooperative approach based on
ongoing information exchange. At Signetics,
formal qualification procedures are required
for all new or changed matenals, processes,
products, and facilities. Prior to 1983, we
created our qualification programs independently. Our major customers would then test
samples to confirm our findings. Now, under
the new Self-Qual Program, customers can
be dlfectly Involved In the prequaliflcation
stage. When we feel we have a promising
enhancement to offer, customers Will be Invited to participate In the development of the
qualification plan. This eliminates the need to
duplicate expensive qualification testing and
also adds another dimension to our ongoing
efforts to build in quality.

400

o

1985

1986

1987

1988

1989

Year

WE WANT TO WORK WITH
YOU
At Signetics, we know that our success depends on our ability to support all our customers with the defect-free, higher density, higher
performance products needed to compete
effectively in today's demanding bUSiness
environment. To achieve thiS goal, quality in
another arena - that of communicationsis vital. Here are some specific ways we can
maintain an ongoing dialogue and information
exchange between your company and ours
on the quality issue:
• Periodical face-to-face exchanges of
data and quality improvement ideas
between the customer and Signetics
can help prevent problems before they
occur.

Figure la. Product Electrical Quality

PPM (Parts per Million)

600

500

400

300

• Test correlation data is very useful. Line
pull information and field failure reports
also help us Improve product
performance.
• When a problem occurs, provide us as
soon as possible with whatever specific
data you have. This will assist us in
taking prompt corrective action.
1985

1986

1987

1988

1989

Year
Figure 1b. Visual-Mechanical Quality
sary terms and conditions. From that pOint,
the specified products can go dlfectly from
the receiving dock to the assembly line or Into
Inventory. Signetics then provides, free of
charge, monthly reports on those products.

December 1988

In our efforts to continually reduce cost of
ownership, we are now using the expenence
we have gained with ShiP' to-Stock to begin
developing a Just-In-Time Program. With JustIn-Time, products Will be delivered to the
receiving dock lust as they are needed, permlt-

2-4

Quality products are, in large measure, the
result of quality communication. By working
together, by opening up channels through
which we can talk openly to each other, we
Will insure the creation of the Innovative,
reliable, cost effective products that help
Insure a competitive edge.

QUALITY AND RELIABILITY
ASSURANCE
Signetlcs' Linear Division Quality and Reliability Assurance Department is involved in all
stages of the production of our Linear IGs:

Signetics Linear Products

Quality and Reliability

• Product Design and Process
Development

device specifications not only the first time,
but also every time thereafter.

changes, intermittently generating and healing the problem.

PRODUCT CHARACTERIZATION

HTSL - High Temperature Storage Life:
ThiS stress exposes the parts to elevated
temperatures (150'C - 175'C) with no applied bias.

• Wafer Fabrication
•
•
•
•

Assembly
Inspection and Test
Product Reliability Monitoring
Customer liaison

The result of this continual involvement at all
stages of production enables us to provide
feedback to refme present and future designs, manufacturing processes, and test
methodology to enhance both the quality and
reliability of the products delivered to our
customers.

RELIABILITY BEGINS WITH THE
DESIGN
Quality and reliability must begin with design.
No amount of extra testing or inspection Will
produce reliable ICs from a design that is
inherently unreliable. Signetics follows very
strict design and layout practices with its
circuits. To eliminate the possibility of metal
migration, current density in any path cannot
exceed 5 X 105 ampsl cm 2. Layout rules are
followed to minimize the possibility of shorts,
circuit anomalies, and SCR type latch-up
effects. All circuit designs are computerchecked using the latest CAD software for
adherence to design rules. Simulations are
performed for functionality and parametric
performance over the full operating ranges of
voltage and temperature before gomg to
production. These steps allow us to meet

Before a new design is released, the characterization phase is completed to insure that
the distribution of parameters resulting from
lot-to-Iot variations is well within specified
limits. Such extensive characterization data
also provides a basis for identifymg unique
applicallOn-related problems which are not
part of normal data sheet guarantees.

RELIABILITY MEASUREMENT
PROGRAMS
Signetics has developed comprehensive
product and process qualification programs to
assure that its customers are receiving highly
reliable products for their critical applications.
AddillOnally, ongoing reliability monitoring
programs, SURE III and Product Monitor,
sample standard production product on a
regularly established basis (see Table I below).

DESCRIPTION OF STRESSES
SHTL - Static High Temperature Life:
SHTL stressmg applies static DC bias to the
device. ThiS has specific merit in detecllng
Ionic contamination problems which require
continuous uninterrupted bias to drive contaminants to the Silicon surface. DHTL stressIng is not as effective in detecting such
problems because the bias continuously

THBS - Biased Temperature-Humidity,
Static: ThiS accelerated temperature and humidity bias stress is performed at 85'C and
85% relative humidity (85'C/85% RH).
TMCL - Temperature Cycling, Air-to-Air:
The deVice is cycled between the specified
upper and lower temperature without power
in an air or nitrogen environment. Normal
temperature extremes are -65'C and
+ 150'C with a minimum 10 mmute dwell and
5 minute transition per Mil-STD-883C, Method 1010.5, CondillOn C. This IS a good test to
measure the overall package to die mechanical compatibility, because the thermal expansion coefficients of the plastic are normally
very much higher than those of the die and
leadframe.
PPOT - Pressure Pot: ThiS stress exposes
the deVices to saturated steam at elevated
temperature and pressure. The standard condition IS 20 PSIG which occurs at a temperature of 127'C and 100% RH. The stress is
used to test the moisture resistance of plastic
encapsulated deVices. Because the steam
environment has an unlimited supply of moisture and ample temperature to catalyze thermally activated events, it is effective at detectmg corrosion problems, contammation in-

Table I. RELIABILITY ASSURANCE PROGRAMS
TYPICAL STRESS

RELIABILITY FUNCTION

FREQUENCY

New Process Qualification

High Temperature Operatmg Life
Biased Temperature-Humidity, Static
High Temperature Storage Life
Pressure Pot
Temperature Cycle

Each new wafer fab process

New Product Qualification

High Temperature Operatmg Life
Biased Temperature-Humidity, Static
High Temperature Storage Life
Pressure Pot
Temperature Cycle
Electrostatic Discharge Charactenzatlon

Each new product

SURE III

High Temperature Operatmg Life
Biased Temperature-Humidity, Static
High Temperature Storage Life
Pressure Pot
Temperature Cycle
Thermal Shock

Each fab process family,
every four weeks

Product Monitor

Pressure Pot
Thermal Shock

Each package type and
technology family at each
assembly plant, every week

December 1988

2-5

Signetics Linear Products

Quality and Reliability

duced leakage problems, and general glasslvation stability and integrity

ONGOING RELIABILITY
ASSESSMENT PROGRAMS

TMSK - Thermal Shock, Liquid-Io-Liquid:
Similar to TMCL, however, heating and coolIng are done by Immersing the Units In hot
and cold inert liquid. Temperature extremes
are -65°C to + 150°C with a minimum 5
minute dwell and less than 10 second transItion per MII-STD-883C, Method 1011.4, Condition C. Since heat transfer by conduction IS
generally much faster than by conveclion, the
liqUid-based thermal shock causes more rapId temperature changes In the part.

The SURE Program
The SURE (Systematic and Uniform Reliability Evaluation) program audits products from
each of Signetlcs linear D,v,s,on's process
families: Bipolar Junclion, SlngJe Layer Metal,
Dual Layer Metal, Gdld-Doped and Schottky,
OXide Isolated and ACMOS, under a variety
of accelerated stress condllions. This program, first Introduced In 1964, has evolved to
SUit changing product complexities and performance reqUIrements

The Audit Program
PRODUCT QUALIFICATION
Linear products are subjected to rigorous
qualification procedures for all new products
or redesigns to current products. Qualification
testing consists of:
• High Temperature Operating Life:
TJ = 150°C, 1000 hours, static bias
• High Temperature Storage Life:
T J = 175°C, 1000 hours, unbiased
• Temperature Humidity Biased Life.
85°C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker:
20 pSlg, 127"C, 168 hours, unbiased
• Temperature Cycle:
-65°C to + 150°C, 500 cycles, 10
minute dwell, air to air, unbiased
Formal qualification procedures are reqUIred
for all new or changed products, processes,
and faCilities. These procedures ensure the
high level of product reliability our customers
expect. New faCilities are qualified by corporate groups as well as by the quality organlzalions of specific Units that Will operate In the
facility. After qualification, products manufactured by the new facility are subjected to
highly accelerated environmental stresses to
ensure that they can meet rigorous failure
rate requirements. New or changed processes are Similarly qualified.

December 1988

Samples are selected from each process
family every four weeks and are subjected to
each of the follOWing stresses.
• High Temperature Operating Life:
TJ = 150°C, 1000 hours, static bias
• Temperature Humidity Biased Life:
85°C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker'
20 pSlg, 127"C, 72 hours, unbiased
• Thermal Shock.
-65°C to + 150°C, 300 cycles, 5 minute
dwell, liquld-to-liquid, unbiased
• Temperature Cycling'
-65°C to + 150°C, 1000 cycles, 10
minute dwell, air-to-air, unbiased

The Product Monitor Program
In addition, each Signetics assembly plant
performs Pressure Cooker and Thermal
Shock SURE Product Monllor stresses on a
weekly baSIS on each molded package by pin
count per the same conditions as the SURE
Program

Product Reliability Reports
The data from these test matrices provides a
basic understanding of product capability, an
Ind,calion of major failure mechanisms, and
an estimated failure rate resulting from each
stress. This data IS complJed periodically and
IS available to customers upon request.

2-6

Many customers use this Information In lieu of
running their own qualification tests, thereby
eliminating time-consuming and costly additional testing

Reliability Engineering
In addition to the product performance monitors encompassed in the linear SURE program, Signetics' Corporate and Division Reliability Engineering departments sustain a
broad range of evaluation and qualification
activities.
Included In the engineering process are:
• Evaluation and qualification of new or
changed materials, assembly/wafer-fab
processes and eqUipment, product
deSigns, faCilities, and subcontractors.
• DeVice or generic group failure rate
studies
• Advanced environmental stress
development.
• Failure mechanism characterization and
corrective aclion/prevenlion reporting.
The enVIronmental stresses utilized in the
engineering programs are Similar to those
utilized for the SURE monitor; however, more
highly-accelerated conditions and extended
durations tYPify these engineering projects.
Additional stress systems such as biased
pressure pot, power-temperature cycling, and
cycle-biased temperature-humidity, are also
Included In some evaluation programs.

Failure Analysis
The SURE Program and the Reliability Engineering Program both Include failure analysis
activities and are complemented by corporate, divIsional, and plant failure analYSIS
departments. These engineering Units proVide a service to our customers who desire
detailed failure analYSIS support, who In turn
provide Signetics with the technical understanding of the failure modes and mechanisms actually experienced In service. This
,nformalion IS essential in our ongoing effort
to accelerate and Improve our understanding
of product failure mechanisms and their prevention.

Signetics Linear Products

Quality and Reliability

LINEAR DIVISION LINEAR PROCESS FLOW

0------------

I

0------------

SCANNING ELECTRON MICROSCOPE CONTROL
Wafers afe sampled dally by the Quality Control laboratory from each fabncatlon area and subtected
to SEM analysIs This process control reveals manufacturing defects such as contact and OXide step
coverage In the metahzahon process which may result 111 early failures
DIE SORT VISUAL ACCEPTANCE
Product IS Inspected for dejects caused dunng fabncatlon, wafer teslmg. or the mechanical scnbe
and break operallon Detects such as scratches, smears and glasslvated bOnding pads are mcluded
In the lot acceptance crltena

DIE AnACH AND WIRE BONDING
The latest automated equipment IS used under statistical process control program

o _ __ __ _ _ _ ____

PRE·SEAL VISUAL ACCEPTANCE
Product IS Inspected to detect any damage Incurred at the die attach and wife bonding stations
Defects such as scratches, contamination and smeared ball bOf)(jS are Included In the 101 acceptance
cntena

_ _ _ _ _ _ _ _ _ _ SEAL TESTS
HermetiC pacKage seal Integrity IS ensured by 100% and fine gross leaK testing
SYMBOL
DeVices are marKed With !he SlgnetlCS logo, devICe number and penod date code of assembly or
custom symbol per IndiVidual specllicatlon requirements

_ _ _ _ _ _ _ _

100% PRODUCTION ELECTRICAL TESTING
Every deVice IS tested to all data sheet parameters guaranteeing temperature speclhcatlons
BURN~IN

(SUPR II LEVEL B OPTION)

Devices are burned In for 21 hours at 155'C maximum Junction Temperature

100% PRODUCTION ELECTRICAL TESTING
Every deVice IS tested to all data sheet parameters guaranteemg temperature speCificatIOns

_ _ _ _ _ _ _ _ VISUAL
AU products are Visually Inspected per the reqUIrements speCified In Signetics' or customer
documents
_ _ _ _ _ _ _ _ FINAL QUALITY ASSURANCE GATE
The final QA Inspecllon step guarantees the speCllied mechamcal and electrical AOL s Every shipment IS sealed and Identified by QA personnel

December 1988

2-7

Signetics linear Products

Quality and Reliability

SIGNETICS' MANUFACTURING
FACILITIES
Signetlcs, as part of a multinational corporation, utilizes manufactUring facilities for wafer
fabrication, package assembly, and test In
three states and three overseas countries as
shown In Table II. All wafer fabrication IS
performed In Signetics operated fabs which
report to the Vice President of Die Manufac-

turing Operations (DMO) In Sunnyvale Similarly, Signetlcs Assembly operations In Utah,
Korea, and Thailand, report to the Vice PresIdent of Assembly ManufactUring Operations
(AMO). Assembly subcontractors, Pebel and
Anam, are scheduled and controlled through
the AMO organization. Assembly subcontractors process all product to Signetics' specifications and materials. Signetics has on-site

Table II. Signetics' Linear Product Manufacturing Facilities
WAFER FABRICATION FACILITIES
Designation

Fab
Fab
Fab
Fab
Fab

01
09
16
21
22

Location

Sunnyvale, California
Orem, Utah
Sunnyvale, California
Orem, Utah
Albuquerque, New MeXICO

Process Families

Bipolar Junction Isolated
Bipolar Gold Doped
OXide Isolated
Bipolar Schottky
ACMOS

ASSEMBLY FACILITIES
Designation

SlgKor
SlgThai
Orem
Pebel
Anam

Location

Seoul, Korea
Bangkok, Thailand
Orem, Utah
Kaohslung, Taiwan
Seoul, Korea

Package

DIP, SO, and PLCC
DIP and CERDIP
Military "Jan" Hermetic
SO
SO and Metal Can

TEST FACILITIES
Designation

Location

TA03

Sunnyvale, California

SlgKor

Seoul, Korea

Package

Wafer Sort, Final Test
and Quality Assurance
Final Test and Quality
Assurance

SlgThal

Bangkok, Thailand

Final Test and Quality
Assurance

Sacto

Sacramento, California

MIlitary Final Test and
Quality Assurance

December 1988

2-8

quality assurance personnel at each subcontractor to audit assembly processes and procedures.
All Signetics Linear products are electrically
tested In Signetics operated faCIlities These
faCilities report to the manufactUring organization (DMO or AMO) operating the faCility at
which they are located.

Signetics Linear Products

Quality and Reliability

SYMBOLIZATION INFORMATION
Signetics' Linear D,v,s,on products are symboled with the
fOllowing information on each package:
• Signetics' Logo
• Product Identification and Package Designator
• Traceability Code'
• Assembly Date and Plant Codes'
• Product Revision Level'
• SUPR II B Processing Code (If applicable)
, May appear on the backside of SO 8, 14 & 16 lead
packages due to space limitations on topside symbol.
Example:
S NE5534N
FBW5491
8901 VCB

line 1
line 2
line 3

Line 1:
S = Signetlcs' Logo
NE5534 = Product type designation
N = Package type:
N = Dual-in-Line Plastic
F = Dual-in-Line CerDlp
D = Small Outline (SO) Surface Mount
A = Plastic Leaded Chip Carrier (PLCC)
E or H = Metal Header
Line 2:
FBW5491 = 7 character Traceability Code assigned to each
Assembly Lot which maintains product
traceability back to the Wafer FabricallOn.
(May be truncated on SO-8 and metal headers.)
Line 3:
8901 = Assembly Date Code (YYWW) specifies the year (YY)
(YYWW) and week number (WW) that begins the 4 week
assembly period dUring which the product was
manufactured. Thus, 8901 indicates that the
product was packaged dUring the first four weeks
of 1989. The first digit of the year may be
omitted on some packages: 901.

v=

Assembly Plant Code which indicates the assembly
facility in which the finished product was packaged.
Assembly Plants Codes are:
V = Signetics Bangkok, Thailand
K = Signetics Seoul, Korea
B = Philips Kaohsiung, Taiwan
L = Anam Seoul, Korea
C = Product Revision Level
B = SUPR II B Burn-In Processing Code (if present)
indicates that the product was processed through 100% SUPR II B Burn-In for 21 hours
under biased operallOn at a juncllOn temperature (Tj) of 155°C

December 1988

2-9

Signetics

Section 3
Small Area Networks

Linear Products

INDEX
Introduction to 12 C ..................... . .. .. ......... ............................................
... ... .. .. ........ ......... ........................................
12 C Bus Specification....
AN168
The Inter-Integrated Circuit (12C) Serial Bus. Theory and
Practical Considerations............ ................................ .........

3-3
3-4
3-16

Signetics

Introduction to 12C

Linear Products

THE 12C CONCEPT
The Inter-IC bus (12C) is a 2-wire serial bus
designed to provide the facilities of a small
area network, not only between the circuits of
one system, but also between different systems; e.g., teletext and tuning.
Philips/Signetics manufactures many devices
with built-in 12C interface capability, any of
which can be connected in a system by
simply "clipping" it to the 12C bus. Hence, any
collection of these devices around the 12C
bus is known as "clips."
The 12C bus consists of two bidirectional
lines: the Serial Data (SDA) line and the Serial
Clock (SCl) line. The output stages of devices connected to the bus (these devices
could be NMOS, CMOS, 12C, TTL, ...) must
have an open-drain or open-collector in order
to perform the wired-AND function. Data on

December 1988

the 12C bus can be transferred at a rate up to
1OOkbits/ sec. The physical bus length IS
limited to 13 feet and the number of devices
connected to the bus is solely dependent on
the limiting bus capacitance of 400pF.
The inherent synchronization process, built
into the 12 C bus structure using the wiredAND technique, not only allows fast devices
to communicate with slower ones, but also
eliminates the "Carrier Sense Multiple Access/Collision Detect" (CSMA/CD) effect
found in some local area networks, such as
Ethernet.
Master-slave relationships exist on the 12C
bus; however, there is no central master.
Therefore, a device addressed as a slave
during one data transfer could possibly be the
master for the next data transfer. DevIces are

also free to transmIt or receIve data dunng a
transfer.
To summarize, the 12C bus eliminates interfacing problems. Since any peripheral device
can be added or taken away wIthout affecting
any other devices connected to the bus, the
12C bus enables the system desIgner to bUIld
various configurations using the same basic
architecture.
Application areas for the 12 C bus include:
Video Equipment
Audio Equipment
Computer TermInals
Home Appliances
Telephony
Automotive
Instrumentation
Industrial Control

3-3

•

Signetics'

12C Bus
Specification

Linear Products

INTRODUCTION
For 8-bit applications, such as those requiring
single-chip microcomputers, certain design
criteria can be established:
• A complete system usually consists
of at least one microcomputer and
other peripheral devices, such as
memories and 1/0 expanders.
• The cost of connecting the various
devices within the system must be
kept to a minimum.
• Such a system usually performs a
control function and does not require
hlgh·speed data transfer.
• Overall efficiency depends on the
devices chosen and the
Interconnecting bus structure.
In order to produce a system to satisfy these
cnteria, a senal bus structure is needed.
Although serial buses don't have the throughput capability of parallel buses, they do require less wiring and fewer connecting pins.
However, a bus is not merely an interconnecting wire, it embodies all the formats and
procedures for communication within the system.
Devices communicating with each other on a
serial bus must have some form of protocol
which avoids all possibilities of confusion,
data loss and blockage of information. Fast
devices must be able to communicate with
slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be
impossible. A procedure has also to be resolved to decide which device will be in
control of the bus and when. And if different
devices with different clock speeds are connected to the bus, the bus clock source must
be defined.

a receiver, while a memory can both receive
and transmit data. In addition to transmitters
and receivers, devices can also be considered as masters or slaves when performing
data transfers (see Table 1). A master is the
device which initiates a data transfer on the
bus and generates the clock signals to permit
that transfer. At that time, any device addressed is considered a slave.
The 12C bus is a multi-master bus. This means
that more than one device capable of controlling the bus can be connected to it. As
masters are usually microcomputers, let's
consider the case of a data transfer between
two microcomputers connected to the 12C
bus (Figure 1). This highlights the masterslave and receiver-transmitter relationships to
be found on the 12C bus. It should be noted
that these relationships are not permanent,
but only depend on the direction of data
transfer at that time. The transfer of data
would follow in this way:
1) Suppose microcomputer A wants to send
information to microcomputer B
- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master transmitter)
sends data to microcomputer B (slave
receiver)
- microcomputer A terminates the
transfer.
2) If microcomputer A wants to receive information from microcomputer B

- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master receiver)
receives data from microcomputer B
(slave transmitter)
- microcomputer A terminates the
transfer.
Even in this case, the master (microcomputer
A) generates the timing and terminates the
transfer.
The possibility of more than one microcomputer being connected to the 12C bus means
that more than one master could try to initiate
a data transfer at the same time. To avoid the
chaos that might ensue from such an event,
an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all devices to the 12C bus.
If two or more masters try to put information
on to the bus, the first to produce a one when
the other produces a zero will lose the
arbitration. The clock signals during arbitration are a synchronized combination of the
clocks generated by the masters using the
wired-AND connection to the SCl line (for
more detailed information concerning arbitration see Arbitration and Clock Generation).
Generation of clock signals on the 12C bus is
always the responsibility of master devices;
each master generates its own clock signals
when transferring data on the bus. Bus clock
signals from a master can only be altered
when they are stretched by a slow slave

All these criteria are involved in the specification of the 12C bus.

THE 12C BUS CONCEPT
Any manufacturing process (NMOS, CMOS,
12l) can be supported by the 12C bus. Two
wires (SDA - serial data, SCl - serial clock)
carry information between the devices connected to the bus. Each device is recognized
by a unique address - whether it is a microcomputer, LCD driver, memory or keyboard
interface - and can operate as either a transmitter or receiver, depending on the function
of the device. Obviously an LCD driver is only
December 1988

Figure 1. Typical 12C Bus Configuration

3·4

Signetics Linear Products

12C Bus Specification

Table 1. Definition of 12C Bus Terminology
TERM

device holding down the clock line or by
another master when arbitration takes place.

DESCRIPTION

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock
signals and terminates a transfer

Slave

The device addressed by a master

Multl·master

More than one master can attempt to control the
bus at the same time without corrupting the message

Arbitration

Procedure to ensure that if more than one master
simultaneously tries to control the bus, only one IS
allowed to do so and the message is not corrupted

Synchronization

Procedure to synchronize the clock signals of two or
more devices

GENERAL CHARACTERISTICS
Both SDA and SCL are bidirectional lines,
connected to a pOSitive supply voltage via a
pull-up resistor (see Figure 2). When the bus
is free, both lines are High. The output stages
of devices connected to the bus must have
an open-drain or open·collector in order to
perform the wired-AND function. Data on the
12C bus can be transferred at a rate up to
100kblt/s. The number of deVices connected
to the bus IS solely dependent on the limiting
bus capacitance of 400pF.

BIT TRANSFER

- ....-r---SDA

+VDD

(SERIAL DATA LINE)

+-__~___~______+-__

SCL_~~_'AL_C_~_K~LI_N_E)~_ _ _

r------

-I

I

iI

o~

SCLK

I

I
I

I
I
I

iI iI

SCLK1..J

I
I

iI

j------

I

DATA

-,
I

iI

SCLK2..J
o~

i i IN
IN
L _______________
...Ji
SCLK

DATA

IN
IN
l _______________
...JI
DEVICE 1

DEVICE 2

Figure 2. Connection of Devices to the 12C Bus

SDA

I

I

I

I

!~.......j--..,!>e+:~
I

SCL~~
I

I

C:~

DATA VALID

I
I
I

I ~~':.~: I
I ALLOWED I

Due to the variety of different technology
devices (CMOS, NMOS, 12L) which can be
connected to the 12C bus, the levels of the
logical 0 (Low) and 1 (High) are not fixed and
depend on the appropriate level of VD D (see
Electrical SpeCifications). One clock pulse is
generated for each data bit transferred.

Data Validity
The data on the SDA line must be stable
during the High period of the clock. The High
or Low state of the data line can only change
when the clock signal on the SCL line is Low
(Figure 3).

Start and Stop Conditions
Within the procedure of the 12C bus, unique
situations arise which are defined as start and
stop conditions (see Figure 4).
A High-to-Low tranSItion of the SDA line while
SCL is High is one such unique case. ThiS
situation indicates a start condition.
A Low-to-High transition of the SDA line while
SCL IS High defines a stop condition.
Start and stop conditions are always generated by the master. The bus IS considered to be
busy after the start condition. The bus is
conSidered to be free again a certain time
after the stop condition. ThiS bus free situation will be described later in detail.
Detection of start and stop conditions by
devices connected to the bus IS easy if they
possess the necessary interfacing hardware.
However, microcomputers with no such Interface have to sample the SDA line at least
twice per clock period in order to sense the
transition.

Figure 3. Bit Transfer on the 12C Bus

TRANSFERRING DATA

Byte Format
Every by1e put on the SDA line must be 8 bits
long. The number of bytes that can be
transmitted per transfer is unrestricted. Each
by1e must be followed by an acknowledge bit.

Figure 4. Start and Stop Conditions

December 1988

3-5

Signetics Linear Products

12C Bus Specification

BYTE COMPLETE,
INTERRUPT WITHIN RECEIVER
CIDCK UNE HELD IJ:N/ WHILE
INTERRUPTS ARE SERVICED

Figure 5. Data Transfer on the 12C Bus

DATAOUTPUT
BYTRANSMrrTER

DATA OUTPUT
BY RECEIVER

I I
~
I
I
I
I
I

..._ _......

I
I
I
I

I
sc~:;..c: I
I

>e::x

X

/ ___- J

~I_.L

_ _ _oJ

I

I
I
L..::J
S

START
CONDmON

CIDCK PULSE FOR
ACKNOWLEDGEMENT

Figure 6. Acknowledge on the 12C Bus

Data is transferred with the most significant
bit (MSB) first (Figure 5). If a receiving device
cannot receive another complete byte of data
until it has performed some other function, for
example, to service an internal interrupt, it
can hold the clock line SCl low to force the
transmitter into a wait state. Data transfer
then continues when the receiver is ready for
another byte of data and releases the clock
line SCl.
In some cases, it is permitted to use a
different format from the 12 C bus format, such
as CBUS compatible devices. A message
which starts with such an address can be
terminated by the generation of a stop condition, even during the transmission of a byte.
In this case, no acknowledge is generated.

Acknowledge
Data transfer with acknowledge is obligatory.
The acknowledge-related clock pulse is generated by the master. The transmitting device
releases the SDA line (High) during the acknowledge clock pulse.

December 1988

The receiving device has to pull down the
SDA line during the acknowledge clock pulse
so that the SDA line is stable low during the
high period of this clock pulse (Figure 6). Of
course, setup and hold times must also be
taken into account and these will be described in the Timing section.
Usually, a receiver which has been addressed
is obliged to generate an acknowledge after
each byte has been received (except when
the message starts With a CBUS address.
When a slave receiver does not acknowledge
on the slave address, for example, because it
is unable to receive while it is performing
some real-time function, the data line must be
left High by the slave. The master can then
generate a STOP condition to abort the
transfer.
If a slave receiver does acknowledge the
slave address, but some time later in the
transfer cannot receive any more data bytes,
the master must again abort the transfer. This
is indicated by the slave not generating the
acknowledge on the first byte following. The

3-6

slave leaves the data line High and the
master generates the STOP condition.
In the case of a master receiver involved in a
transfer, it must signal an end of data to the
slave transmitter by not generating an acknowledge on the last byte that was clocked
out of the slave. The slave transmitter must
release the data line to allow the master to
generate the STOP condition.

ARBITRATION AND CLOCK
GENERATION
Synchronization
All masters generate their own clock on the
SClline to transfer messages on the 12C bus.
Data is only valid during the clock High period
on the SCl line; therefore, a defined clock is
needed if the bit-by-bit arbitration procedure
is to take place.
Clock synchronization is performed using the
wired-AND connection of devices to the SCl
LINE. This means that a High-to-low transi-

Signetics Linear Products

12C Bus Specification

START COUNTING
WAIT -+~~HPERIOD

II
STATE
CLK
1

I
--'"'\

----~.~----~'------------~------

ClK
2 ____

~---7~'-~------__--------J-~~-----~--~---

SCl

Figure 7. Clock Synchronization During the Arbitration Procedure

TRANSMITTER 1LDSES ARBITRATION
DATA1+SDA
DATA
1

DATA

2,L·'-J1~--~-'-------~---r-------~'----~
SDA

Arbitration can carry on through many bits.
The first stage of arbitration is the comparison
of the address bits. If the masters are each
trying to address the same device, arbitration
continues into a comparison of the data.
Because address and data Information IS
used on the 12C bus for the arbitration, no
information is lost dunng this process.
A master which loses the arbitration can
generate clock pulses until the end of the
byte in which it loses the arbitration.
If a master does lose arbitration during the
addreSSing stage, it IS possible that the winning master is trying to address it. Therefore,
the losing master must switch over immediately to its slave receiver mode.
Figure 8 shows the arbitration procedure for
two masters. Of course more may be Involved, depending on how many masters are
connected to the bus. The moment there IS a
difference between the Internal data level of
the master generating DATA 1 and the actual
level on the SDA line, Its data output is
switched off, which means that a High output
level IS then connected to the bus. This Will
not affect the data transfer Initiated by the
winning master. As control of the 12C bus IS
decided solely on the address and data sent
by competing masters, there is no central
master, nor any order of pnority on the bus.

Use of the Clock Synchronizing
Mechanism as a Handshake
Figure 8. Arbitration Procedure of Two Masters
lion on the SCl line Will affect the deVices
concerned, causing them to start counting off
their low penod. Once a deVice clock has
gone low It will hold the SCl line In that state
until the clock High state is reached (Figure
7). However, the low-to-Hlgh change in this
device clock may not change the state of the
SCl line if another device
clock is still within its low penod. Therefore,
SCl will be held low by the device with the
longest low period. Devices with shorter low
periods enter a High walt state during thiS
time.
When all deVices concerned have counted off
their low penod, the clock line will be released and go High. There will then be no
difference between the deVice clocks and the

December 1988 .

state of the SCl line and all of them Will start
counting their High penods. The first deVice
to complete ItS High penod Will again pull the
SCl line low.
In this way, a synchronized SCl clock is
generated for which the low penod IS determined by the device with the longest clock
low period while the High period on SCl IS
determined by the deVice With the shortest
clock High penod.

Arbitration
Arbitration takes place on the SDA line in
such a way that the master which transmits a
High level, while another master transmits a
low level, will switch off its DATA output
stage since the level on the bus does not
correspond to ItS own level.

3-7

In addition to being used during the arbitrallOn
procedure, the clock synchronization mechanism can be used to enable receiving devices
to cope with fast data transfers, either on a
byte or bit level.
On the byte level, a device may be able to
receive bytes of data at a fast rate, but needs
more time to store a received byte or prepare
another byte to be transmitted. Slave devices
can then hold the SCl line low, after reception and acknowledge of a byte, to force the
master Into a wait state until the slave is
ready for the next byte transfer In a type of
handshake procedure.
On the bit level, a device such as a microcomputer without a hardware 12 C interface
on-chip can slow down the bus clock by
extending each clock low period. In this way,
the speed of any master is adapted to the
Internal operating rate of this device.

Signetics Linear Products

j 2C

Bus Specification

FORMATS
Data transfers follow the format shown in
Figure 9. After the start condition, a slave
address is sent. This address is 7 bits long;
the eighth bit is a data direction bit (R/iN). A
zero indicates a transmission (WRITE); a one
indicates a request for data (READ). A data
transfer is always terminated by a stop condition generated by the master. However, if a

master still wishes to communicate on the
bus, It can generate another start condition,
and address another slave without first generating a stop condition. Various combinations
of read/write formats are then possible within
such a transfer.

er and the slave receiver becomes a slave
transmitter. This acknowledge is still generated by the slave.
The stop condition is generated by the master.
During a change of direction within a transfer,
the start condition and the slave address are
both repeated, but with the R/W bit reversed.

At the moment of the first acknowledge, the
master transmitter becomes a master receiv-

Figure 9. A Complete Data Transfer

Possible Data Transfer Formats are:
a) Master transmitter transmits to slave
receiver. Direction is not changed.

s

8LAVEADDRESS

A - ACKNOWLEDGE

R/W

DATA

A

11

'O'(WIIIl'E)

S-START

IIo1U'A TRANSFERRED
+ ACKNOWLEDGE)

(n BYTES

P=STOP

b) Master reads slave immediately after
first byte.

p

A

A

s

SLAVEADDRESS

R/W

IIo1U'A

A

A

p

A

11
IIo1U'A TRANSFERRED
+ ACKNOWLEDGE)

(n BYTES

t:.:J

c) Combined formats.

Is I SLAVEADDRESS I JRlW I A

s I SLAVEADORESS I RJ'W I All:;~r I

(n BYTES

(n BYTES

+ ACKNOWLEDGfj
READ OR

WRrrE

+ ACKNOWLEDGE)
READ OR
WRrrE

DIRECTION OF
TRANSFER MAY

CHANGER
THIS POINT
AF(l351OS

NOTES.
1 Combined formats can be used, for example. to control a serial memory Dunng the first data byte, the Internal memory locabon has to be wntten After the start condlbon IS repeated,
data can then be transferred
All deciSions on auto-Jncrement or decrement of prevIOusly accessed memory locations. etc. are taken by the designer of the deVIce
Each byte IS followed by an acknowledge as Indicated by the A blocks In the sequence
12(; devices have to reset their bus logiC on receipt of a start condition so that they all antiCipate the sending of a slave address

December 1988

3·8

Signetics Linear Products

12C Bus Specification

ADDRESSING
The first byte after the start condItion determines whIch slave WIll be selected by the
master. Usually, this first byte follows that
start procedure. The exception is the general
call address whIch can address all devices.
When this address is used, all devices
should, in theory, respond with an acknowledge, although deVIces can be made to
ignore this address. The second byte of the
general call address then defines the action
to be taken.

Definition of Bits in the First
Byte
The first seven bIts of this byte make up the
slave address (Figure 10). The eighth bit
(lSB - least SIgnificant bIt) determines the
dIrection of the message. A zero on the least
SIgnificant posItion of the fIrst byte means that
the master WIll write Information to a selected
slave; a one In this posItIon means that the
master will read information from the slave.
Msa
-SLAVEADDRESS-

LSB

I

a

AXXXXX
F1RSrBYTE

Figure 12. Sequence of a Programming Master
bllities in group 1111 WIll also only be used for
extensIon purposes but are not yet allocated.
The combinallOn OOOOXXX has been defined
as a speCIal group. The following addresses
have been allocated;
FIRST BYTE
Slave
Address

0000
0000

001
010

X
X

0000
0000
0000
0000
0000

all

X
X
X
X
X

100
101
110
111

1

edge this address and behave as a slave
receIver. The second and follOWing bytes will
be acknowledged by every slave receiver
capable of handling thIS data. A slave which
cannot process one of these bytes must
ignore It by not acknowledging.
The meaning of the general call address is
always specified In the second byte (FIgure
11).

R/W

When an address IS sent, each device in a
system compares the first 7 bits after the start
condition with its own address. If there IS a
match, the deVIce will consider itself addressed by the master as a slave receIver or
slave transmItter, depending on the R/W bit.

December 1988

SECOND BYTE

H'06'

a

The address 1111111 is reserved as the
extension address. This means that the addreSSing procedure will be continued in the
next byte(s). Devices that do not use the
extended addressing do not react at the
reception of this byte. The seven other possi-

A

I s I H'OO' I A I H'II2' I A I ABCDOOO I X I A I ABCDOQ1 I X I A I ABCD010 I X I A I p I

Figure 10. The First Byte After the
Start Procedure

The bit combinallOn 1111 XXX of the slave
address is reserved for future extension purposes.

I

B

Figure 11. General Cal! Address Format

000
000

The 12C bus committee is available to coordinate allocation of 12C addresses.

x

(GENERAL CALL ADDRESS)

0000
0000

The slave address can be made up of a fIxed
and a programmable part. Since it IS expected
that Identical ICs will be used more than once
in a system, the programmable part of the
slave address enables the maxImum possIble
number of such devices to be connected to
the 12C bus. The number of programmable
address bits of a deVIce depends on the
number of pins available. For example, if a
device has 4 fixed and 3 programmable
address bits, a total of eIght identical devices
can be connected to the same bus.

x

General call address
Start byte

There are two cases to conSIder;
1. When the least signifIcant bIt B IS a zero.
2. When the least SIgnificant bIt B IS a one

CBUS address
Address reserved for
different bus format

When B is a zero, the second byte has the
following definitIon;

]" "" '"""

No device is allowed to acknowledge at the
reception of the start byte.
The CBUS address has been reserved to
enable the intermixing of CBLlS and 12C
deVIces in one system. 12 C bus deVIces are
not allowed to respond at the reception of this
address.
The address reserved for a different bus
format IS included to enable the miXIng of 12C
and other protocols. Only 12 C deVIces that are
able to work with such formats and protocols
are allowed to respond to this address.
General Cal! Address
The general call address should be used to
address every deVIce connected to the 12 C
bus. However, If a device does not need any
of the data supplied within the general call
structure, it can ignore this address by not
acknowledging. If a device does reqUIre data
from a general call address, it will acknowl-

3-9

00000110 (H'06') Reset and write the programmable part of slave
address by software and
hardware. On receIving this
two-byte sequence, all devIces (designed to respond
to the general call address)
WIll reset and take in the
programmable part of their
address.
Precautions must be taken
to ensure that a deVIce is
not pulling down the SDA
or SCl line after applYIng
the supply voltage, sInce
these low levels would
block the bus.
00000010 (H'02') Write slave address by
software only. All deVIces
which obtain the programmable part of their address
by software (and which
have been deSIgned to respond to the general call
address) WIll enter a mode
in which they can be programmed. The deVIce will
not reset.

Signetics Linear Products

j 2C

Bus Specification

An example of a data transfer of a programming master is shown in Figure 12 (ABCD
represents the fixed part of the address).

(8)

I

s

00000100 (H'04') Write slave address by
hardware only. All devices
which define the programmable part of their address
by hardware (and which respond to the general call
address) will latch this programmable part at the reception of this two-byte sequence. The device will not
reset.

oooooooo

AI

MASTER ADDRESS

IsI

SLAVEADDRH/WMASTER

R/W

(n BYTES

I

DATA

IP

A

11

+ ACKNOWLEDGE)

IA I

DUMPADDRFORH/WMASTER

IXI A

P

a. Configuring master sends dump address to hardware master

s

DUMP ADDR FROM H/W MASTER

I R/W I A I
I
WRITE

When B is a one, the two-byte sequence is a
hardware general call. This means that the
sequence is transmitted by a hardware master device, such as a keyboard scanner,
which cannot be programmed to transmit a
desired slave address. Since a hardware
master does not know in advance to which
device the message must be transferred, it
can only generate this hardware general call
and its own address, thereby Identifying itself
to the system (Figure 13).

December 1988

A

WRITE

The remaining codes have not been fixed and
devices must ignore these codes.

Start Byte
Microcomputers can be connected to the 12C
bus In two ways. If an on-chip hardware 12 C
bus interface IS present, the microcomputer
can be programmed to be interrupted only by
requests from the bus. When the device
possesses no such interface, it must constantly monitor the bus via software. Obvious-

I DATA

Figure 13. Data Transfer From Hardware Master Transmitter

Sequences of programming procedure are
published in the appropriate device data
sheets.

In some systems an alternative could be that
the hardware master transmitter is brought In
the slave receiver mode after the system
reset. In this way, a system configuring master can tell the hardware master transmitter
(which is now In slave receiver mode) to
which address data must be sent (Figure 14).
After this programming procedure, the hardware master remains in the master transmitter mode.

A

SECOND
BYTE

GENERAL
CALL ADDRESS

00000000 (H'OO') This code IS not allowed to
be used as the second
byte.

The seven bits remaining in the second byte
contain the device address of the hardware
master. This address IS recognized by an
Intelligent device, such as a microcomputer,
connected to the bus which will then direct
the information coming from the hardware
master. If the hardware master can also act
as a slave, the slave address IS identical to
the master address.

1

DATA

IAI

DATA I

P

A

12

In BYTES + ACKNOWLEDGE)

b. Hardware master dumps data to selected slave device
Figure 14. Data Transfer of Hardware Master Transmitter Capable of Dumping
Data Directly to Slave Devices

II

~I
SDA
I \
I
I

SCL

II

~UMMY
I I
ACKNOWLEDGE

I
I
I

2

(HIGH)

I
I

I

--t-j'\
~
r:;\ I';\. I';\. Jt-i
i _i \.J/0.
' \.J . ~~ . \.J. \.JiCK\.J i _ i
LS.J

LSr.J

!----START BYTEOClOOOOO1-\

Figure 15. Start Byte Procedure
Iy, the more times the microcomputer monitors, or polls, the bus, the less time it can
spend carrying out its intended function.
Therefore, there is a difference in speed
between fast hardware devices and the relatively slow microcomputer which relies on
software polling.
In this case, data transfer can be preceded by
a start procedure which is much longer than
normal (Figure 15). The start procedure consists of:
a)
b)
c)
d)

A start condition, (S)
A start byte 00000001
An acknowledge clock pulse
A repeated start condition, (Sr)

After the start condition (S) has been transmitted by a master requiring bus access, the

3-10

start byte (00000001) is transmitted. Another
microcomputer can therefore sample the
SDA line on a low sampling rate until one of
the seven zeros in the start byte is detected.
After detection of this Low level on the SDA
line, the microcomputer is then able to switch
to a higher sampling rate In order to find the
second start condition (Sr) which is then used
for synchronization.
A hardware receiver will reset at the reception
of the second start condition (Sr) and will
therefore ignore the start byte.
After the start byte, an acknowledge-related
clock pulse is generated. This is present only
to conform with the byte handling format used
on the bus. No device is allowed to acknowledge the start byte.

Signetics Linear Products

12C Bus Specification

S~

.... ..,
I____________________-,
~I

'"

""

I'"
~
I II
I I

~

SCL

OLEN

I I
I I

(2

I

~~---------------------I~L-J--~L-J--JL-__________________________~I L--J
STARr

CONDITION

~:ss

r:::

I

II

~J

LOA~~:LSE CO~~ON

n DATA BITS

""K

RELATED
ClOCK PULSE

Figure 16. Data Format of Transmissions With CBUS Receiver/Transmitter
CBUS Compatibility
Existing CBUS receivers can be connected to
the 12C bus. In this case, a third line called
DlEN has to be connected and the acknowledge bit omitted. Normally, 12 C transmissions
are multiples of 8-bit bytes; however, CBUS
devices have different formats.

V DD1 -4=5V::t:1O%

In a mixed bus structure, 12C devices are not
allowed to respond on the CBUS message.
For this reason, a special CBUS address
(OOOOOOtX) has been reserved. No 12C device will respond to this address. After the
transmission of the CBUS address, the DlEN
line can be made active and transmission,
according to the CBUS format, can be performed (Figure 16).

S~~~~--~~----~~--~~--~~-­
~L-----+----~~----~------+-----~-

Figure 17. Fixed Input level Devices Connected to the 12C Bus

VDD = e.g. 3V

After the stop condition, all devices are again
ready to accept data.
Master transmitters are allowed to generate
CBUS formats after having sent the CBUS
address. Such a transmission IS terminated
by a stop condition, recognized by all devices.
In the low speed mode, full 8-bit bytes must
always be transmitted and the timing of the
DlEN signal adapted.
If the CBUS configuration is known and no
expansion with CBUS devices is foreseen,
the user is allowed to adapt the hold time to
the specific requirements of device(s) used.

ELECTRICAL SPECIFICATIONS
OF INPUTS AND OUTPUTS OF
12C DEVICES
The 12C bus allows communication between
devices made in different technologies which
might also use different supply voltages.
For devices with fixed input levels, operating
on a supply voltage of +SV ± 10%, the following levels have been defined:
Vilmax = 1.SV (maximum input low
voltage)

December 1988

R.

R.

S~--+-~----+-+-----~~--~~~--~~­

~L----~----~~----~------+-----~Figure 18. Devices With a Wide Range of Supply Voltages Connected
to the 12 C Bus
VIHm,n

= SV (minimum Input High
voltage)

Devices operating on a fixed supply voltage
different from + SV (e.g. 12 l), must also have
these input levels of 1.SV and SV for Vil and
VIH. respectively.
For deVices operating over a wide range of
supply voltages (e.g. CMOS), the following
levels have been defined:
Vilmax

= O.SVoo (maximum input low

VIHmin

= 0.7Voo (minimum input High

voltage)
voltage)
For both groups of devices, the maximum
output low value has been defined:
VOlmax = OAV (max. output voltage low)
at SmA sink current

3-11

The maximum low-level Input current at
VOlmax of both the SDA pin and the SCl pin
of an 12C device is -10/lA, including the
leakage current of a possible output stage.
The maximum high-level input current at
o 9Voo of both the SDA pin and SCl pin of an
12C device is 10/lA, including the leakage
current of a possible output stage.
The maximum capacitance of both the SDA
pin and the SCl pin of an 12C device is 10pF.
Devices with fixed input levels can each have
their own power supply of + 5V ± 10%. Pullup resistors can be connected to any supply
(see Figure 17).
However, the devices with input levels related
to Voo must have one common supply line to
which the pull-up resistor is also connected
(see Figure 18).

•

Signetics Linear Products

12C Bus Specification

When devices with fixed input levels are
mixed with devices with Voo-related levels,
the latter devices have to be connected to
one common supply line of + 5V ± 10% along
with the pull-up resistors (Figure 19).

V DDI -SV::t:'IO%

lip

V0D2 =5V:t:10%

Rp

Input levels are defined In such a way that:
1. The noise margin on the low level is 0.1
Voo·
2 The noise margin on the High level IS 0.2
Voo·
3. Series resistors (Rs) up to 300n can be
used for flash-over protection against high
voltage spikes on the SDA and Sel line
(due to flash-over of a TV picture tube, for
example) (Figure 20).

s~--~~--~~----~~--~~

S~

The clock on the 12e bus has a minimum low
penod of 4.7/1s and a minimum High period of
4/1s. Masters in this mode can generate a bus
clock with a frequency from 0 to 100kHz.

~L

__

l
I D~CE I

I D~CE I

R.

R.

R.

VDD

I
I

R.

Rp

Rp

LD05650S

Figure 20. Serial Resistors (Rsl for Protection Against High Voltage

LOW-SPEED MODE

Data Format and Timing

As explained previously, there is a difference
In speed on the 12e bus between fast hardware devices and the relatively slow microcomputer which relies on software pOlling.
For this reason a low speed mode is available
on the 12 e bus to allow these microcomputers
to poll the bus less often.

The bus clock in thiS mode has a low period
of 130/1s ± 25/1s and a High period of
390/1s ± 25/1s, resulting in a clock frequency
of approx. 2kHz. The duty cycle of the clock
has this low-to-High ratio to allow for more
efficient use of microcomputers without an
on-chip hardware 12 e bus interface. In this
mode also, data transfer with acknowledge is
obligatory. The maximum number of bytes
transferred is not limited (Figure 22).

Start and Stop Conditions
In the low-speed mode, data transfer is preceded by the start procedure.

Figure 21. Timing Requirements for the 12 C Bus

December 1988

~~

Figure 19. Devices With Voo Related Levels Mixed With Fixed Input Level
Devices on the I C Bus

TIMING

Figure 21 shows the timing requirements in
detail. A descnptlon of the abbreviations used
IS shown in Table 2. All timing references are
at V,Lmax and V,LmlO'

__

~L-----+----~------~------+------+-

The maximum bus capacitance per wire IS
400pF. This Includes the capacitance of the
wire Itself and the capacitance of the pinS
connected to it.

All devices connected to the bus must be
able to follow transfers with frequencies up to
100kHz, either by being able to transmit or
receive at that speed or by applying the clock
synchronization procedure which will force
the master Into a wait state and stretch the
low penods. In the latter case the frequency
IS reduced.

VDD3 =6V:t:1O%

3-12

Signetics Linear Products

12C Bus Specification

Table 2. Timing Requirement for the 12C Bus
LIMITS
PARAMETER

SYMBOL

UNIT

fSCl

SCL clock frequency

tBuF

Time the bus must be free before a new transmission can start

tHO; STA

Hold time start condition. After this penod the first clock pulse is generated

tLOW

Min

Max

0

100

kHz

4.7

p.s

4

p.s

The Low period of the clock

4.7

p.s

tHIGH

The High period of the clock

4

p.s

tsu. STA

Setup time for start condition (Only relevant for a repeated start condition)

4.7

p.s

tHO. OAT

Hold time DATA
for CBUS compatible masters
for 12C devices

5
O·

p.s
p.s
ns

250

tsu. OAT

Setup time DATA

tR

Rise time of both SDA and SCL hnes

tF

Fall time of both SDA and SCL lines

tsu; STO

Setup time for stop condition

1
300

NOTES:

Figure 22. Data Transfer Low-Speed Mode

SOA

8Cl

I
I

I

I
I

I

I
I
I

IttD: srA -+r---I

~

i----'HlGH-----i

L S"']

Figure 23. Timing Low-Speed Mode

December 1988

3-13

ns
p.s

4.7

All values referenced to VIH and Vil levels.
* Note that a transmitter must Internally provide a hold time to bridge the undefined region (300ns max) of the falhng edge of

p.s

sel.

Signetics Linear Products

12C Bus Specification

In this mode, a transfer cannot be terminated
dUring the transmission of a byte.

LOW SPEED MODE
CLOCK
DUTY CYCLE

START BYTE
MAX. NO. OF BYTES
PREMATURE TERMINATION OF TRANSFER
ACKNOWLEDGE CLOCK BIT
ACKNOWLEDGEMENT OF SLAVES

: tLOW = 130l1S ± 2511S
tHIGH = 390l1s ± 2511S
1:3 Low-to-Hlgh (Duty cycle of
clock generator)
0000 0001
UNRESTRICTED
NOT ALLOWED
ALWAYS PROVIDED
: OBLIGATORY

The bus is considered busy after the first start
condition It is considered free again one
minimum clock Low period, 10511S, after the
detection of the stop condition. Figure 23
shows the timing requirements in detail, Table
3 explains the abbreviations.

Table 3. Timing Low Speed Mode
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Max

tSUF

Time the bus must be free before a new transmission can start

105

I1S

tHO; STA

Hold time start condition. After this period the first clock pulse is generated

365

!.IS

tHO; STA

Hold time (repeated start condition only)

210

tLOw

The Low penod of the clock

105

155

tHIGH

The High period of the clock

365

415

I1S

tsu. STA

Setup time for start condition (Only relevant for a repeated start condition)

105

155

I1S

tHO; tOAT

Hold time DATA
for CBUS compatible masters
for 12C devices

5
O'

tsu. OAT

Setup time DATA

tR

Rise time of both SDA and SCL lines

tF

Fall time of both SDA and SCL lines

tsu; STO

Setup time for stop condition

I1S

I1S
I1S

ns

250
1

105

ns

155

I1S

NOTES:

3-14

I1S

300

All values referenced to VIH and VIL levels
* Note that a transmitter must Internally provide a hold time to bridge the undefined region (300ns max) of the falhng edge of SCL.

December 1988

I.IS

Signetics Linear Products

12C Bus Specification

APPENDIX A
Maximum and minimum values of the pull-up
resistors Rp and senes resistors Rs (See
Figure 20).
In a 12C bus system these values depend on
the following parameters:
- Supply voltage
- Bus capacitance
- Number of devices (input current + leakage current)
1) The supply voltage limits the minimum value of the Rp resistor due
to the specified 3mA as minimum
sink current of the output stages,
at OAV as maximum low voltage.
In Graph 1, Voo against Rpm," IS
shown.

In Graph 2, RSmax against Rp IS shown.
2) The bus capacitance IS the total capacitance of Wire, connections, and
pins. This capacitance limits the maxImum value of Rp because of the
specified rise time of 111S.

In Graph 3, the bus capacitance - RPmax
relationship is shown.
3) The maximum high-level Input current
of each Input/output connection has a
specified value of 101lA max. Due to
the desired noise margin of 0.2 Voo
for the high level, this Input current
limits the maximum value of Rp. This
limit IS dependent on Voo.
In Graph 4 the total high-level input current - RPmax relationship is shown.
20

~

rl"
w
3

18

12

§

8

/

MAXIMUM VAWE R.(Q)

/: ~
/
9'

Graph 2

VMAX.Rs

~

\
12

18

12C LICENSE

./R.=O

MAX.~~~

Graph 1
The desired nOise margin of 0.1 Voo for the
low level limits the maximum value of Rs.

Graph 4

\\

o

o

@Voo-Si
o
o

--=

100
200
300
BUS CAPACITANCE (PF)

Graph 3

December 1988

~

lOTAL HIGH LEVEL INPUT CURRENT (j.A)

,

20

:IE
:::>
:IE

3-15

Purchase of Signetics or Philips 12C components conveys a license under the Philips 12C
patent nghts to use these components in an
12C system, provided that the system conforms to the 12C standard specification as
defined by Philips.

•

Signetics

AN168
The Inter-Integrated Circuit (PC)
Serial Bus: Theory and
Practical Consideration

Linear Products

Author: Carl Fenger

INTRODUCTION
The 12C (Inter-Ie) bus is becoming a popular
concept which implements an innovative serial bus protocol that needs to be understood
On the hardware level 12 C is a collection of
microcomputers (MAB8400, PCD3343,
83C351, 84CXX) and peripherals (lCD/lED
drivers, RAM, ROM, clock/timer, A/D, D/A,
IR transcoder, I/O, DTMF generator, and
various tuning circUits) that communicate serially over a two-wire bus, serial data (SDA)
and serial clock (SCl). The 12C structure is
optimized for hardware Simplicity. Parallel
address and data buses inherent in conventional systems are replaced by a senal protocol that transmits both address and bidirectional data over a 2-line bus. ThiS means that
interconnecting wires are reduced to a minimum; only Vee, ground and the two-wire bus
are required to link the controller(s) with the
peripherals or other controllers. This results in
reduced chip Size, pin count, and interconnections. An 12 C system IS therefore smaller,
Simpler, and cheaper to implement than ItS
parallel counterpart.
The data rate of the 12 C bus makes it SUited
for systems that do not reqUire high speed.
An 12C controller is well SUited for use in
systems such as television controllers, telephone sets, appliances, displays or applications involving human interface. TYPically an
12C system might be used In a control function where digitally-controllable elements are
adjusted and monitored via a central processor.
The 12C bus is an innovative hardware Interface which provides the software designer
the flexibility to create a truly multi-master
environment. Built Into the serial Interface of
the controllers are status registers which
monitor all possible bus conditions: bus freel
busy, bus contention, slave acknowledgement, and bus interference. Thus an 12C
system might include several controllers on
the same bus each with the ability to asynchronously communicate with peripherals or
each other. This provIsion also provides expandability for future add-on controllers. (The
12C system is also ideal for use In environments where the bus is subject to noise.
Distorted transmissions are Immediately detected by the hardware and the information
presented to the software.) A slave acknowl-

December 1988

Application Note
edgement on every byte also faCilitates data
integrity.
An 12C system can be as Simple or sophisticated as the operating enVIronment demands. Whether In a single master or multimaster system, nOIsy or 'safe', correct system operation can be insured under software
control.

CONTROLLERS
Currently the family of 12 C controllers Include
the MAB8400, and the PCD 3343 (the
PCD3343 IS basically a CMOS verSion of the
MAB8400). The MAB8400 is based on the
8048 architecture with the 12 C Interface bUiltIn. The instruction set for the MAB8400 is
Similar to the 8048, With a few instructions
added and a few deleted. Tables 1 and 2
summarize the differences.
Programs for the MAB8400 and PCD 3343
may be assembled on an 8048-assembler
using the macros listed In AppendiX A. The
senal I/O instructions involve moving data to
and from the SO, S1, and S2 serial I/O control
registers. The block diagram of the 12 C interface is shown in Figure 1.

SERIAL 1/0 INTERFACE
A block diagram of the Senal Input/Output
(SIO) is shown In Figure 1. The clock line of
the serial bus (SCl) has exclusive use of Pin
3, while the Senal Data (SDA) line shares Pin

2 With parallel I/O Signal P23 of port 2.
Consequently, only three I/O lines are available for port 2 when the 12 C interface is
enabled.
Communication between the microcomputer
and Interface takes place via the Internal bus
of the microcomputer and the Serial Interrupt
Request line Four registers are used to store
data and Information controlling the operation
of the Interface'
• data shift register SO
• address register SO'
• status register S1
• clock control register S2.

THE 12C BUS INTERFACE:
SERIAL CONTROL REGISTERS

SO, S1
All serial 12 C transfers occur between the
accumulator and register SO. The 12C hardware takes care of clocking out/In the data,
and recelvlng/generaling an acknowledge. In
addition, the state of the 12C bus IS controlled
and mOnitored via the bus control register S1
A definition of the registers IS as follows:
Data Shift Register SO - SO IS the data shift
register used to perform the conversion between senal and parallel data format. All
transmissions or receptions take place
through register SO MSB firSt. All 12 C bus
receptions or transmissions Involve moving
data to/from the accumulator fromlto SO.

Table 1_ MAB8400 Family Instructions not in the MAB8048 Instruction Set
SERIAL 1/0
MOV A,Sn
MOV Sn,A
MOV Sn,#data
EN SI
DIS SI

REGISTER

CONTROL

DEC @Rr
DJNZ @Rr,addr

SEl MB2
SEl MB3

CONDITIONAL
BRANCH
JNTF addr

Table 2_ MAB8048 Instructions not in the MAB8400 Family Instruction Set
DATA MOVES
MOVX A,@R
MOVX @R,A
MOVP3 A,@A
MOVD A,P
MPVD P,A
ANlD P,A
ORlD P,A

FLAGS
ClR
CPl
ClR
CPl

FO
FO
F1
F1

BRANCH
'JNI addr
JFO addr
JF1 addr

'replaced by
JTO, JNTO

3-16

CONTROL
ENTOClK

Signetlcs Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

INTREO

8400

T

INTERRIJPT
LOGIC
ENSI
DISSI

WRSO
RDSO

INmALIZE
(PIn 17)
o

•

LRB

RESET

PIN

INTERNAL MICROCOMPUTER BUS

BIT 7
WRS1
MST TRX BB
RDS1

S1
CLOCK

SERIAL CLOCK PULSE GENERATOR

PAODR. COUNTER

1••- - - INTERNAL CLOCK

Figure 1. Block Diagram of the MAB8400 510 Interface
Address Register SO' - In multi-master
systems, this register is loaded with a controller's slave address. When activated,
(ALS = 0), the hardware will recognize when
it is being addressed by setting the AAS
(Addressed As Slave) flag. This provision
allows a master to be treated as a slave by
other masters on the bus.
Status Register 51 - S1 is the bus status
register. To control the SIO interface, information is written to the register. The lower 4
bits in S1 serve dual purposes; when written
to, the control bits ESO, BC2, BC1, BCO are
programmed (Enable Serial Output and a 3bit counter which indicates the current number of bits left in a serial transfer). When
reading the lower four bits, we obtain the

December 1988

status information AL, AAS, ADO, LRB (Arbitration Lost, Addressed As Slave, Address
Zero (the general call has been received), the
Last Received Bit (usually the acknowledge
bit)). The upper 4 bits are the MST, TRX, BB,
and PIN control bits (Master, Transmitter, Bus
Busy, and Pending Interrupt Not). These bits
define what role the controller has at any
particular time. The values of the master and
transmitter bits define the controller as either
a master or slave (a master initiates a transfer
and generates the serial clock; a slave does
not), and as a transmitter or receiver. Bus
Busy keeps track of whether the bus is free or
not, and is set and reset by the 'Start' and
'Stop' conditions which will be defined. Pending Interrupt Not is reset after the completion

3-17

of a byte transfer + acknowledge, and can be
polled to indicate when a serial transfer has
been completed. An alternative to polling the
PIN bit is to enable the serial interrupt; upon
completion of a byte transfer, an interrupt will
vector program control to location 07H.

SERIAL CLOCKI ACKNOWLEDGE
CONTROL REGISTER S2
Register S2 contains the clock-control register and acknowledge mode bit. Bits
S20 - S24 program the bus clock speed. Bit
826 programs the acknowledge or not-acknowledge mode (1/0). The various 12C bus
clock speed possibilities are shown in
Table 3.

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
Table 3. Clock Pulse
Frequency Control
When Using a 4.43MHz Crystal
HEX
S20-S24
CODE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18'
19'
lA'
lB'
lC

10
IE
IF

DIVISOR

APPROX.
fCLOCK
(kHz)

Not Allowed
114
39
45
98
51
87
63
70
75
59
51
87
99
45
123
36
147
30
171
26
195
23
243
18
291
15
339
13
387
11
483
9.2
579
7.7
675
6.6
5.8
771
963
4.6
1155
3.8
1347
3.3
1539
2.9
1923
2.3
2307
1.9
2691
1.7
3075
1.4
3843
1.2
4611
1.0
5379
0.8
6147
0.7

AN168

The losing Master is now configured as a
slave which could be addressed during this
very same cycle. These provisions allow for a
number of microcomputers to exist on the
same bus. With properly written subroutines,
software for anyone of the controllers may
regard other masters as transparent.

12C PROTOCOL AND
ASSEMBLY LANGUAGE
EXAMPLES
12 C data transfers follow a well-defined protocol. A transfer always takes place between a
master and a slave. Currently a microcomputer can be master or slave, while the 'CLIPS'
peripherals are always slaves. In a 'bus-Iree'
condition, both SCl and SDA lines are kept
logical high by external pull-up resistors. All
bus transfers are bounded by a 'Start' and a
'Stop' condition. A 'Start' condition is defined
as the SDA line making a high-to.IOw transition while the Sel line Is high. At this pOint,
the internal hardware on all slaves are activated and are prepared to clock-in the next 8
bits and interpret it as a 7-bit address and a
R/W control bit (MSB first). All slaves have an
internal address (most have 2 - 3 programmable address bits) which is then compared
with the received address. The slave that
recognized its address will respond by pulling
the data line low during a ninth clock generated by the master (all 12C byte transfers
require the master to generate 8 clock pulses
plus a ninth acknowledge-related clock
pulse). The slave-acknowledge will be registered by the master as a '0' appearing in the
lRB (Last Received Bit) position of the 51
serial I/O status register. If this bit is high

after a transfer attempt, this indicates that a
slave did not acknowledge, and that the
transfer should be repeated.
After the desired slave has acknowledged its
address, it is ready to either send or receive
data in response to the master's driving
clock. All other slaves have withdrawn from
the bus. In addition, for multi-master systems,
the start condition has set the 'Bus Busy' bit
of the serial I/O register 51 on all masters on
the bus. This gives a software indication to
other masters that the bus is in use and to
wait until the bus is free before attempting an
access.
There are two types of 12C peripherals that
now must be defined: there are those with
only a chip address such as the I/O expander, PCF8574, and those with a chip address
plus an internal address such as the static
RAM, PCF8570. Thus after sending a start
condition, address, and R/W bit, we must
take into account what type of slave is being
addressed. In the case of a slave with only a
chip address, we have already indicated its
address and data direction (R/W) and are
therefore ready to send or receive data. This
is performed by the master generating bursts
of 9 clock pulses for each byte that is sent or
received. The transaction for writing one byte
to a slave with a chip address only is shown in
Figure 3.
In this transfer, all bus activity is invoked by
writing the appropriate control byte to the
serial I/O control register SI, and by moving
data to/from the serial bus buffer register SO.
Coming from a known state (MOV SI,#18HSlave, Receiver, Bus not Busy) we first load
the serial I/O buffer SO with the desired

·only values that may be used In the low speed mode
(ASC~1)

vce
These speeds represent the frequency of the
serial clock bursts and do not reflect the
speed of the processor's main clock (I.e. it
controls the bus speed and has no effect on
the CPU's execution speed).

SCL

SOA

BUS ARBITRATION
Due to the wire·AND configuration of the 12C
bus, and the self-synchronizing clock circuitry
of 12C masters, controllers with varying clock
speeds can access the bus without clock
contention. During arbitration, the resultant
clock on the bus will have a low period equal
to the longest of the low periods; the high
period will equal the shortest of the high
periods. Similarly, when two masters attempt
to drive the data line simultaneously, the data
is 'ANDed', the master generating a low while
the other is driving a high will win arbitration.
The resultant bus level will be low, and the
loser will withdraw from the bus and set its
'Arbitration lost' flag (51 bit 3).
December 1988

MAB
8400

Ao
PCF

PCB

8574

8570

I/O EXPANDOR
ADDR = '40'H

Figure 2. SchematiC for Assembly Examples

3-18

RAM (l28-BYTE)
ADDR = 'AO'H

Signetics Uneor Products

Application Note

The Inter-Integrated Circuit (12C) Serial Bus:
Theory and Practical Consideration

AN168

+
MOV Sl,#18H
MOV SO.#40H
~

MOV Sl,#OF8H

CALL ACKWT:
MOV A,#2AH
MOV SO.A - - - - - - '
CALL ACKWT:
MOV S1.#OD8H _ _ _ _...J

;Initialize Sl-Slave, Receiver, Bus not
; Busy, Enable Serial 1/0.
;Preload SO with Siave's address &
;R/W bit.
;Invoke start condition & slave address
; (Master, Transmitter, Bus Busy, Enable
;Serial 1/0, Bit Counter = 000).
;Check for transmission complete, ack.
;received, no arbitration, etc.
;Get a data byte.
;Transmit data byte.
;Wait for transmission complete again.
;Generate Stop condition
;(Master, Transmitter, Bus not Busy).

Figure 3
sieve's address (MOV SO.#40H). To transmit
this preceded by a start condition. _ must
first examine the control register S1. which.
after initialization. looks like this:
lIASTER

_

m_...,

PIN

E80

IC2

Bet

8CO

1 0 / 0 1 0 1 1 1 1 1010101
To transmit to a slave. the Master. Transmlttar. Bus Busy. PIN (Pending Interrupt Not).
and ESO (Enable Serial Output) must be set
to a 1. This results in an 'F6H' being written to
S1. This word defines the controller as a
Master Transmitter, Invokes the transfer by
setting the' Bus Busy' bit, clears the Pending
Interrupt Not (an inverted flag Indicating the
completion of a complete byte transfer), and
actIvatas the serlel output logic by setting the
Enable Serial Output (ESO) bit.

BIT COUNTER S12, S11, S10
BC2. BC1, and BCO comprise a bit-counter
which Indicatas to the logic how long the
word Is to be clocked out over the serial data
line. By setting this to a OOOH, _ are teillng It
December 1988

to produce 9 clocks (8 bits plus an acknowledge clock) for this transfer. The bit counter
will then count off each bit as it is transmitted.
The bit counter possibilities are shown in
Table 4.
Thus the bit counter keeps treck of the
number of clock pulsas remaining in a serial
transfer. Additionally. there is a not-acknowledge mode (controlled through bit 6 of clock
control register 52) which inhibits the acknowledge clock pulse. allowing the possibility of straight serial transfer. We may thus
define the word size for a serial transfer (by

preloading BC2. BC1, BCO with the appropriate control number). wfth or without an acknowtedge-related clock pulse being generated. This makes the controller able to transmit
serial data to most any serial device regardless of its protocol (e.g.• C-bus devices).

CHECKING FOR SLAVE
ACKNOWLEDGE
After a 'Star!' condlticn and address heve
been Issued. the selected sieve will heve
racognized and acknowledged its address by

Table 4. Binary Numbers In Bit-Count Locatlona BC2, BC1 and BCO
Be2

Be1

BCO

0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

0
0
1
1
1
1
0

3-19

BITS/BYTE
WITHOUT ACK

BITS/BYTE
WITH ACK

1
2

3

3
4
5
6

2
4
5
6

7

7

8

6

9

Signetics Unear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
pulling the data line low during the ninth clock
pulse. During this period, the software (which
runs on the processor's 4MHz clock) will
have been either waiting for the transfer to be
completed by polling the PIN bit in 51 which
goes low on completion of a transfer/reception (whose length is defined by the preloaded Bit-counter value), or by the hardware
in Serial Interrupt mode. The serial interrupt
(vectored to 07H) is enabled via the EN 51
(enable serial interrupt) instruction.
At the point when PIN goes low (or the senal
interrupt is received) the 9-blt transfer has
been completed. The acknowledgement bit
will now be in the lRB position of register 51,
and may be checked in the routine 'ACKWT'
(Wait for Acknowledge) as shown In Figure 4.
This routing must go one step further In multimaster systems; the possibility of an Arbitration lost situation may occur if other masters
are present on the bus. This condition may be
detected by checking the 'Al' bit (bit 3). If
arbltrallOn has been lost, provIsions for reattempting the transmiSSion should be taken.
If arbitration is lost, there is the possibility that
the controller is being addressed as a Slave.
If this cond~ion is to be recognized, we must
test on the 'AAS' bit (bit 2). A 'General Call'
address (OOH) has also been defined as an
'all-call' address for all slaves; bit I, ADO,
must be tested if thiS feature is to be recognized by a Master.
After a successful address transfer/ acknowledge, the slave is ready to be sent its data.
The instruction MOV SO,A will now automatically send the contents of the accumulator
out on the bus. After calling the ACKWT
routine once more, we are ready to terminate
the transfer. The Stop condition IS created by
the instruction 'MOV 51, #OD8H'. This resets the bus-busy bit, which tells the hardware to generate a Stop - the data line
makes a low-to-high tranSition while the clock
remains high. All bus-busy flags on other
masters on the bus are reset by this signal.
The transfer IS now complete - PCF8574
I/O Expandor will transfer the senal data
stream to its 8 output pins and latch them
until further update.

December 1988

ACKWT:

AN168

MOV A,SI

;Get bus status word
;from 51.
;Poll the PIN bit
;until it goes low
;indicating transfer
;completed
;Jump to BUSERR
;routine if acknowledge
;not received.
;transfer complete,
;acknowledge received - return.

JB4 ACKWT

JBO BUSERR

RET

Figure 4

MASTER READS ONE BYTE
FROM SLAVE
A read operation IS a similar process; the
address, however, Will be 41H, the lSB
Indicating to the I/O deVice that a read is to
be performed. Dunng the data portion of a
read, the I/O port 8574 will transmit the
contents of ItS latches In response to the
clock generated by the master. The Master/
Receiver in thiS case generates a low-level
acknowledge on reception of each byte (a
'pOSitive' acknowledge). Upon completion of
a read, the master must generate a 'negative'
acknowledge dunng the ninth clock to indicate to the slaves that the read operation IS
finished. This IS necessary because an arbitrary number of bytes may be read Within the
same transfer. A negative acknowledge consists of a high Signal on the data line during
the ninth clock of the last byte to be read. To
accomplish thiS, the master 8400 must leave
the acknowledge mode just before the final
byte, read the final byte (producing only 8
clock pulses), program the bit-counter with
001 (prepanng for a one-bit negative acknowledge pulse), and simply move the contents of SO to the accumulator. This final
Instruction accomplishes two things simultaneously: It transfers the final byte to the
accumulator and produces one clock pulse
on the SCl line. The structure of the serial
I/O register SO is such that a read from it
causes a double-buffered transfer from the
12C bus to SO, while the Original contents of
SO are transferred to the accumulator. Because the number of clocks produced on the
bus is determined by the control number in
the Bit Counter, by presetting it to 001, only

3-20

one clock is generated. At this point in time
the slave is still waiting for an acknowledge;
the bus is high due to the pull-up, as single
clock pulse in this condition is interpreted as
a 'negative' acknowledge. The slave has now
been informed that reading is completed; a
Stop condition is now generated as before.
The read process (one byte from a slave with
only a chip address) is shown in Figure 5.

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

AD
ACKNOWLEDGE

SCL

I STAIII'
I CONDmON

I STOP
I CONDITION
I

I

J
MOV S1,#18H
MOV SO,#41H

MOV S1,#OF8H
CALL ACKWT

WAIT:

S2'#0~~

I

MOVSO,A~

MOV

MOV A,S1
JB4 Wait
MOV S1,#OA9H

MOV A,SO - - _.....
MOV S1,#OD8H - - -....

;Initialize serial 1/0 control
;register.
;Preload serial register SO
;with slave address and RD
;control bit.
;Send address to bus along with
;start condition.
:Wait for acknowledge (as
;before).
;Leave aCknowledge mode.
;Read data from slave to SO.
;Test for byte received by
;testing S1 PIN bit.
;Wait until PIN received.
;Set Bit Counter to 1 and
;become a receiver (A9 =
;Mst,Rec,Bus Busy,Bit Coutner =
;001).
;Move data to accumulator and
;clock out a negative
;acknowledge.
;Generate Stop Condition.

Figure 5

December 1988

3-21

I

Signetics Unear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

CO-"NlCATION WITH PERIPHERAL REQUIRED

MOVS1,#18H

MOV SO, #OAOH
MOV SI, #OF8H
CALL ACKWT
MOVA,#OOH
MOVSO,A
CALL ACKWT
MOVS1,#18H
MOVA,#OA1H
MOVSO,A
MOV S1,#OF8H
CALL ACKWT
MOVA,SO
CALL ACKWT
MOVA,SO
CALL ACKWT
MOVRO,A
MOVA,SO
CALL ACKWT
MOVR1,A
MOV S2,#01H
MOVA,SO

WAIT1:

MOVR2,A
MOVA,St
JB4WAITt
MOV SI,#OD8H
MOVS2,#41H

Figure 8. Flowchart for Reading/Writing One Byte to an 12(:
Peripheral; Slngle-Ma8ter, Slng....Addreas Slave
These examples apply to a slave with a chip
address - more than one byte can be writ·
ten/read within the same transfer; however,
this option is more applicable to 12C devices
with sub·addresses such as the static RAMs
or Clock/Calendar. In the case of these types
of devices, a slightly different protocol is
used. The RAM, for example, requires a chip
address and an internal memory location
before It can deliver or accept a byte of
information. During a write operation, this is
December 1988

done by simply writing the secondary address
right after the chip address - the peripheral
is designed to interpret the second byte as an
internal address. In the case of a Read
operation, the slave peripheral must send
data back to the Master after it has been
addressed and sub-addressed. To accomplish this, first the Start, Address, and Subaddress is transmitted. Then we have a
repeated start condition to reverse the direction of the data transfer, followed by the chip

3-22

;Initialize bus-status register
;Master, Transmitter,
;Bus-not-Busy, Enable SIO.
;Load SO with RAM's chip
;address.
;Start condo and transmit
;address.
;Wait until address received.
;Set up for transmitting RAM
;Iocation address.
;Transmit first RAM address.
;Wait.
;Set up for a repeated Start
;condition.
;Get RAM chip address & RD bit.
;Send out to bus
;preceded by repeated Start.
;Wait.
;First data byte to SO.
;Wait
;Second data byte to SO.
;And First data byte to Acc.
;Wait.
;Save first byte," RO.
;Third data byte to SO
;and second data byte to Acc.
;Wait.
;Save second data byte
;inRI.
;Leave ack. mode.
;Blt Counter=OOl for neg ack.
;Third data byte to acc
;negative ack. generated.
;Save third data byte in R2.
;Get bus status.
;Wait until transfer complete.
;Stop condition.
.Restore acknowledge mode.

Figure 7

address and RD, then a data string (w/
acknowledges). This repeated Start does not
affect other peripherals - they have been
deactivated and will not reactivate until a
Stop condition is detected. 12c peripherals
are equipped with auto-incrementing logic
which will automatically transmit or receive
data in consecutive (increasing) Iccations.
For example, to read 3 consecutive bytes to
PCB8571 RAM locations 00, 01 and 02, we
use the following format as shown in Figure 7.

Application Note

Signetlcs Linear Products

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
This routine reads the contents of location 00,
01 and 02 of the PCB8571 128-byte RAM and
puts them in registers RO, R1, and R2. The
auto-incrementing feature allows the programmer to indicate only a starting location,
then read an arbitrary block of consecutive
memory addresses. The WAIT 1 loop is
required to poll for the completion of the final
byte because the ACKWT routine will not
recognize the negative acknowledge as a
valid condition.

BUS ERROR CONDITIONS:
ACKNOWLEDGE NOT RECEIVED
In the above routines, should a slave fall to
acknowledge, the condition is detected during the 'ACKWT routine. The occurrence
may indicate one of two conditions: the slave
has failed to operate, or a bus disturbance
has occurred. The software response to either event is dependent on the system application. In either case, the 'BusErr' routine
should reinitialize the bus by issuing a 'Stop'
condition. Provision may then be taken to

AN168

repeat the transfer an arbitrary number of
times. Should the symptom perSist, either an
error condition will be entered, or a backup
device can be activated.
These sample routines represent single-master systems. A more detailed analysis of multimaster/noisy environment systems will be
treated in further application notes. Examples
of more complex systems can be found in the
'Software Examples' manual; publication
9398 615 70011.

~

I

December 1988

3-23

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
APPENDIX A
Only the 8048 assembler is capable of assembling MAB8400 source code when it has
at least a "DATA" or "Define Byte" assembler directive, possibly in combination with a
MACRO facility.

AN168

The new instructions can be simply defined
by MACROs. The instructions which are not
In the MAB8400 should not be In the
MAB8400 source program.
An example of a macro definitions list is given
here for the Intel Macro Assembler.

This list can be copied in front of a MAB8400
source program; the new instructions are
added to the MAB8400 source program by
calling the MACRO via its name in the opcode field and (if required) followed by an
operand in the operand field.

MACRO DEFINITIONS
LINE

SOURCE STATEMENT

1 $MACROFILE
2 ;MACROS FOR 8048 ASSEMBLER RECOGNITION
3 ;OF 8400 COMMANDS
4
MOVSOA
5
DB 3CH
ENOM
6
7
MOVASO
DB OCH
8
9
ENDM
10
MOVS1A
11
DB 3DH
12
ENDM
13
MOVASI
14
DB OOH
15
ENDM
16
MOVS2A
17
DB 3EH
18
ENDM
19
MOVSO
DB 9CH,L
20
ENDM
21
22
MOVSl
23
DB 9DH,L
24
ENDM
25
MOVS2
26
DB 9EH,L
ENDM
27
ENSI
28
29
DB 85H
30
ENDM
31
DISSI
32
33
34;
35; PORT 0 INSTRUCTIONS;
36;
37
38
39;
40
41
42
43;
44
45
46
47;
48
49
50
51;

December 1988

MACRO

;MOV SO,A

MACRO

;MOV A,SO

MACRO

;MOV SI,A

MACRO

;MOV A,SI

MACRO

;MOV S2,A

MACRO L

;MOV SO,#DATA

MACRO L

;MOV SI,#DATA

MACRO L

;MOV S2,#DATA

MACRO

;EN SI

MACRO

;DIS SI (Disable serial
interrupt)

DB
ENDM

95H

INAPO
DB
ENDM

MACRO
08H

;IN A,PO

OUTPOA
DB
ENDM

MACRO
38H

;OUTL PO,A

ORLPO
DB
ENDM

MACRO L
88H,L

;ORL PO,#DATA

ANLPO
DB
ENDM

MACRO L
98H,L

;ANL PO,#DATA

3-24

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

MACRO DEFINITIONS (Continued)
LINE

SOURCE STATEMENT

52; DATA MEMORY INSTRUCTIONS:
53

DECARO
DB
ENDM

MACRO
OCOH

;DEC @RO

DECAR1
DB
ENDM

MACRO
OC1H

;DEC @R1

SELMB2
DB
ENDM

MACRO
OA5H

;SEL MB2

SELMB3
DB
ENDM

MACRO
OB5H

;SEL MB3

DJNZAO
DB
ENDM

MACRO L
;DJNZ @RO,ADDR
OEOH,L AND OFFH

MACRO L
;DJNZ @R1,ADDR
OE1H,L AND OFFH

77

DJNZA1
DB
ENDM

78;
79

JNTF

MACRO L

DB
ENDM

06H,L AND OFFH

54
55
56;
57
58
59
60;
61; SELECT MEMORY BANK INSTRUCTIONS:
62
63
64
65;
66
67
68
69;
70; CONDITIONAL JUMP INSTRUCTIONS:
71
72
73
74;
75
76

80
81
82
83; END OF MACRO DEFINITIONS

December 1988

3-25

;JUMP IF TIMERFLAG IS
NON ZERO

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (12C) Serial Bus:
Theory and Practical Consideration

AN168

THE 8400 INSTRUCTIONS BUILT FROM THE MACRO LIST
LOC/OBJ

0000
OOOOOC
0001 OD
00023C
0003 3D
0004 3E

0005 9C
0006 56

00079D
00089F

0009 9E
OOOA E8
OOOB 85
OOOC 95
OOOD 08
OOOE 38
OOOF 88
0010 5A
0011 98
0012 2F
0013 CO
0014 Cl
0015 A5
0016 B5

0017 EO

LINE

SOURCE STATEMENT

1
2
3+
4
5+
6
7+
8
9+
10
11 +
12

ORG 0
MOVASO
DB
MOVASl
DB
MOVSOA
DB
MOVS1A
DB
MOVS2A
DB
MOVSO

13 +

DB

9CH,56H

14

MOVSl

9FH

15+

DB

9DH,9FH

16

MOVS2

OE8H

17 +

DB

9EH,OE8H

18
19 +
20
21 +
22
23 +
24
25 +
26
27 +

ENSl
DB
DiSSI
DB
INAPO
DB
OUTPOA
DB
ORLPO
DB

28
29+

ANLPO
DB

30
31 +
32
33 +
34
35 +
36
37+
38

DECARO
DB
DECARl
DB
SELMB2
DB
SELMB3
DB
DJNZAO

39 +

DB

OEOH,567H AND
OFFH

40

DJNZAl

OEFEH

41 +

DB

OEl H,OEFEH AND
OFFH

42
43 +

JNTF
DB

789H
06H, 789H AND
OFFH

44

END

;MACRO for MOV A,SO
OCH
;MACRO for MOV A,Sl
ODH
;MACRO for MOV SO,A
3CH
;MACRO For MOV Sl,A
3DH
;MACRO For MOV S2,A
3EH
56H

;MACRO For MOV SO,
#56H

;MACRO for MOV Sl,
#9FH

;MACRO for MOV S2,
#OE8H

;MACRO for EN Sl
85H
;MACRO for DIS SI
95H
;MACRO for iN A,PO
08H
;MACRO for OUTL PO,A
38H
5AH
88H,5AH
2FH
98H,2FH

;MACRO for ORL PO,A

;MACRO for ANL PO,A

;MACRO for DEC @RO
OCOH
;MACRO for DEC @Rl
OC1H
;MACRO for SEL MB2
OA5H
;MACRO for SEL MB3
OB5H
567H

;MACRO for DJNZ @RO,
567H

0019 67

0019 El

;MACRO for DJNZ @Rl,
OEFEH

001A FE
001B 06
001C 89

December 1988

3-26

;MACRO for JNTF 789H

Signetics

Section 4
RF Communications

Linear Products

INDEX
RF SIGNAL PROCESSING
Amplifiers
NE/SA5204
NE/SAI
SE5205
NE/SE5539
AN140
NE5592
NE/SE592
AN141

Wide-band High Frequency Amplifier. ....
Wide-band High Frequency Amplifier.. ... ..
.... . ..... .
Ultra-High Frequency Operational Amplifier.. .... ...... . ...... .
Compensation Techniques for Use with the NE/SE5539 ........ .
Video Amplifier ........ .......... ..... . ...... .. .... . .... .. .. .
Video Amplifier.... .................... .. .. .
USing the NE/SE592 Video Amplifier .. .

4-3
4-13
4-24
4-32
4-38
4-44
4-53

Mlxer/Modulators/Demodulators
MC14961
1596

AN189
NE602
AN1981
AN1982
NE612
TDA1574
TDA5030A

Balanced Modulator/Demodulator ...
Balanced ModulatorIDemodulator Applications USing the
MC1496/MC1596 ............................................ ..
Double-Balanced Mixer and Oscillator...... .. ........ .. ........ .
New Low Power Single Sideband Circuits (NE602) ..... .. ....... .
Applying the OSCillator of the NE602 In Low Power
Mixer Applications .....
Low Power VHF Mixer10sciliator ...
FM Front-End IC (VHF Mixer and OSCillatOr). . ...... .. ........ ..
VHF Mixer-OSCillator (VHF Tuner IC)
.............. .

4-57
4-61
4-66
4-72
4-80
4-83
4-89
4-95

IF Systems
CA3089
MC3361
AN1992
NE/SA604A
AN1991
AN1993
NE/SA605
NE614A
NE/SA615
TDA1576

FM IF System.
Low Power FM IF .
USing the Signetics MC3361 Demonstration Board
Low Power FM IF System ....
........ ..
Audio DeCibel Level Detector with Meter Driver
High Sensitivity Applications of Low-Power
RF/IF Integrated Circuits ......
Low Power FM IF System... ....... .. .......
Low Power FM IF System ...
High-Performance Low Power Mixer FM IF System ..
FM-IF (Quadrature Detector) .... ......... .

Single-Chip Receivers
NE/SA605
Low Power FM IF System .. ..... .. .... .. ... . ... . ....
NE/SA615
High-Performance Low Power Mixer FM IF System .............
TDA7000
Single-Chip FM Radio Circuit... .. ..... . .. ..
TDA7010
Single-Chip FM Radio CirCUit (SO Package). .. .. ... ..........

4-99
4-105
4-108
4-114
4-124
4-126
4-137
4-141
4-151
4-156

4-137
4-151
7-41
7-77

II

FREQUENCY SYNTHESIS
Synthesizers

Frequency Synthesizer.........................................................
Universal Divider................................................................
SAA1057
PLL Radio TUning Circuit.....................................................
Single-Chip Synthesizer for Radio Tuning.................................
AN196
Analysis and BasIc Application of the SAA 1057
(PLL Radio Tuning).............................................................
AN197
TDD1742
CMOS Frequency Synthesizer ...............................................
PHASE-LOCKED LOOPS

4-163
4-173
4-182
4-190

4-222
4-227
4-243
4-252
4-259
4-263
4-266

NE568

An Overview of the Phase-Locked Loop (PLL) .........................
Modeling the PLl...............................................................
Phase-Locked Loop............................................................
Circuit Description of the NE564 ...........................................
Frequen'cy Synthesis with the NE564......................................
10.8MHz FSK Decoder with the NE564 ..................................
A 6MHz FSK Converter Design Example for the NE564.............
Clock Regenerator with Crystal-Controlled Phase-Locked
VCO (NE564) ....................................................................
Phase-Locked Loop............................................................
Circuit Description of the NE565 PLL .....................................
Typical Applications with NE565 ............................................
Function Generator.............................................................
Circuit Description of the NE566 ...........................................
Waveform Generators with the NE566....................................
Tone Decoder/Phase-Locked Loop ........................................
Circuit Description of the NE567 Tone Decoder ........................
Selected CircUits Using the NE567 .........................................
150MHz Phase-Locked Loop ................................................

COMPANDORS
AN174
AN176
NE570/SA571
NE/SA572
AN175
NE575

Applications for Compandors: NE570/571/SA571 ..................... .
Compandor Cookbook ........................................................ .
Compandor ...................................................................... .
Programmable Analog Compandor ......................................... .
Automallc Level Control Using the NE572 .............................. .
Low Voltage Compandor ..................................................... .

4-325
4-334
4-341
4-348
4-356
4-357

HEF4750V
HEF4751V

ANl77

AN 178
NE/SE564
AN179
AN180
AN1801
AN181
AN182
NE/SE565
AN183
AN184
NE/SE566
AN185
AN186
NE/SE567
AN187
AN188

4-197
4-209

4-268
4-277
4-283
4-287
4-290
4-295
4-296
4-299
4-311
4-316
4-319

Signefics

NE/SA5204
Wide-band High-Frequency
Amplifier
Product Specification

Linear Products
DESCRIPTION
The NE/SA5204 is a high-frequency
amplifier with a fixed insertion gain of
20dB. The gain is flat to ± 0.5dB from DC
to 200M Hz. The -3dB bandwidth is
greater than 350M Hz. This performance
makes the amplifier ideal for cable TV
applications. The NE/SA5204 operates
with a single supply of 6V, and only
draws 25mA of supply current, which IS
much less than comparable hybrid parts.
The noise figure is 4.8dB in a 75.12
system and 6dB in a 50.12 system.
The NE/SA5204 is a relaxed version of
the NE5205. Minimum guaranteed bandwidth is relaxed to 350M Hz and the "s"
parameter MiniMax limits are specified
as typicals only.
Until now, most RF or high-frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high-frequency
gain stages. These include high power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NEI
SA5204 solves these problems by incorporating a wideband amplifier on a single
monolithic chip.
The part is well matched to 50 or 75.12
input and output impedances. The
standing wave ratios in 50 and 75.12
systems do not exceed 1.5 on either the
input or output over the entire DC to
350M Hz operating range.

No external components are needed
other than AC-coupling capacitors because the NE/SA5204 is internally compensated and matched to 50 and 75.12.
The amplifier has very good distortion
specifications, with second and thlrdorder intermodulation Intercepts of
+24dBm and +17dBm, respectively, at
100MHz.
The part is well matched for 50.12 test
eqUipment such as signal generators,
oscilloscopes, frequency counters, and
all kinds of signal analyzers. Other applications at 50.12 Include mobile radio, CB
radio, and data/video transmission in
fiber optics, as well as broadband LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SA5204s in series as
required, without any degradation In amplifier stability.

FEATURES
• Bandwidth (min_)
200 MHz, ± 0.5dB
350 MHz, - 3dB
• 20dB insertion gain
• 4.8dB (6dB) noise figure
Zo 75.12 (Zo 50.12)
• No external components required
• Input and output impedances
matched to 50175.12 systems
• Surface-mount package available
• Cascadable

=

PIN CONFIGURATION
N, D Packages

I.

I
!

~

TOP VIEW

APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•

Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
Oscilloscopes
Signal analyzers
Broadband LANs
Networks
Modems
Mobile radio
Security systems
Telecommunications

=

Since the part is a small, monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit Into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects.

ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic DIP

8-PIn Plastic SO package

November 3, 1987

TEMPERATURE RANGE

ORDER CODE

o to +70°C

NE5204N

-40 to +85°C

SA5204N

o to +70°C

NE5204D

-40 to +85°C

SA5204D

4-3

853-1191 91260

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Supply voltage

9

V

VIN

AC input voltage

5

Vp_p

TA

Operating ambient temperature range
NE grade
SA grade

o to +70
-40 to +85

'C
'C

1160
780

mW
mW

PDMAX

Maximum power dissipation "
= 25'C (still-air)
N package
D package

2

TA

TJ

Junction temperature

TSTG

Storage temperature range

TSOLD

Lead temperature
(soldering 60s)

150

'C

-55 to + 150

'C

300

'C

NOTES:
1. Derate above 25°C, at the following rates

N package at 9.3mWrC
D package at 6.2mWrc.
2. See "Power Dissipation ConSiderations" sectIon.

EQUIVALENT SCHEMATIC
vee

R,

Ro

: r - - - -......--~~~M----O vour

Q,

November 3, 1987

4-4

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

DC ELECTRICAL CHARACTERISTICS at Vee = 6V, Zs = ZL = Zo = 50Q and TA = 25'C, In all packages, unless otherwise
specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Vee

Operating supply voltage range

Over temperature

5

lee

Supply current

Over temperature

19

S21

Insertion gain

f = 100MHz, over temperature

16

S11

8

V

24

31

mA

19

22

dB

25

dB

DC -550MHz

12

dB

f = 100MHz

27

dB

DC -550MHz

12

dB

f = 100MHz

-25

dB

DC -550MHz

-18

dB

Output return loss

S12

Max

f = 100MHz
Input return loss

S22

Typ

Isolation

BW

Bandwidth

BW

Bandwidth

tR

±0.5dB

200

350

MHz

-3dB

350

550

MHz

NOise figure (75Q)

f = 100MHz

4.8

dB

Noise figure (50Q)

f = 100MHz

6.0

dB

Saturated output power

f = 100MHz

+7.0

dBm

1dB gain compression

f = 100MHz

+4.0

dBm

Third-order Intermodulation
intercept (output)

f = 100MHz

+17

dBm

Second-order Intermodulatlon
intercept (output)

f = 100MHz

+24

dBm

Rise time

5

ps

Propagation delay

5

ps

34
""

T

32


-2
-3 r-Zo=500

VCC=8V

t--

.6 ~ r--

~

t;;;---

Vcc=6V

Vcc=5V

-5
8

6

10'

40

30
E

...

;;e

30

./

25

w

0
II:
0

,

20

I

0

z

0

(J

15

""

/

20

i,...-'

'"

;;e

II:

w

0
II:

C!0

9;

8

15

/

10

V

TA= 25·C
Zo = 500

-

-

'(

...:z:
5

10

4

POWER SUPPLY VOLTAGE-V

10
POWER SUPPLY VOLTAGE-V

Figure 7. Second-Order Output Intercept vs Supply Voltage

November 3, 19B7

......
II:

I
I
7

25

w

10
4

.
(J

TA=25°C
Zo = 500

w

en

...
...I

III

35

w

II:

8 102

Figure 6. ldB Gain Compression vs Frequency

at

..

'",
.....

FREQUENCY -MHz

Figure 5. Saturated Output Power vs Frequency

liw

~

-8

• 102

FREOUENCY -MHz

E

-

--

r---

-4 r-T..,=25°C

-5
-8

...I
...

......

Vcc=7V

0-2 f--Zo=500
-3
TA=25·C
-4

l~

10'

8 103

Figure 4. Insertion Gain vs Frequency (S211

-- ""

VCC=7V
Vcc=6V

6

FREQUENCY -MHz

Figure 3. Insertion Gain vs Frequency (S21)

10
9
8

8 1()2

6

10'

FREQUENCY-MHz

Figure 8. Third-Order Intercept vs Supply Voltage

4-6

Signetics Linear Products

Product Specification

:I
I
I
I

Wide-band High-Frequency Amplifier

NEjSA5204

i
I

I

~
5a.

2.0

2.0

1.9

1.9

1.8

1.8

1.7

a: 1.7
il 1.6
>
1.5
:>

1.6

TA=25°C

VCC=6V

'"...

1.5
1.4

....

1.'

0

1.3

::>

1.2

-Zo=750

1.2

1.1 -

Zo = 500

1.0
10'

1.1 -Zo=500
1.0
'0'

8 102

6

Figure 9. Input VSWR

VB

Frequency

35

"''''

30

"
I
I",

"'0
0-,
-'z

Za:
a::>
:> ...
Wa:
a: ...
... :>
:> ..
~g

-15

III
I

Zo = 500
TA=25°C

z

25

2-20

VCC=6V

~

~ -25

20

~

-30
10'
FREQUENCY-MHz

W

III

.

\
.......

C

"z
~

VCc=~v J

ii!:

",

I-,0

TA= 8S"C

0

fiW

<11

r---

:!!!

Zo=7S0
T,,=25°C

6

10'

8 102

...,.,

I.

6

8 102

6

8 103

FREOUENCY -MHz

FREQUENCY-MHz

Figure 14. Insertion Gain vs Frequency (52,)

Figure 13. Insertion Gain vs Frequency (52')

November 3, 1987

/'

-

•

15 -Zo=7S0
-VCC=6V

10

'0'

8,03

TA 40-:;;; -

= T,,= 25°C
20

"'z"

t\..

VCC=5V

,5

:!!!

6

25

VCC=7V"""\.\

I

8 102

Figure 12. Isolation vs Frequency (5,2)

VCC=~V

20

6

FREQUENCY-MHz

Figure 11. Input (5 11 ) and Output (522) Return Loss vs
Frequency

25

V

----

15
10
10'

"'z"I

8 103

-10

"'w

.....

•

8 102

Figure 10. Output VSWR vs Frequency

40

",Ill

•

FREOUENCY-MHz

FREQUENCY -MHz

4-7

Signetlcs Linear Products

Product Specification

NE/SA5204

Wide-band High-Frequency Amplifier

THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic in Figure 1S, the gain is set primarily by the equation:

The DC input voltage level VIN can be determined by the equation:
(3)

where RE' = 12n, VSE = 0.8V, Ic, = SmA
and IC3 = 7mA (currents rated at Vcc = 6V).

(1)

Under the above conditions, VIN is approximately equal to 1V.

which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wide-band terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, RE1 and the base resistance of 0,
are kept as low as possible, while RF2 is
maximized.

Level shifting is achieved by emitter-follower
03 and diode 0 4 , which provide shunt feedback to the emitter of a, via RF" The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shuntfeedback loading on the output. The value of
RF1 = 140n is chosen to give the desired
nominal gain. The DC output voltage Your
can be determined by:

The noise figure is given by the following
equation:

NF

[rb+RE1+~]J dB

= 10Log { 1 + _ _ _ _.::2~ql~C1
Ro

(2)

where Ic, = S.SmA, RE1 = 12n, rb = 130n,
KT/q = 26mV at 2SoC and Ro = SO for a Son
system and 7S for a 7Sn system.

Your = Vcc - (IC2+ Ica)R2,
where Vcc
Ica = SmA.

= 6V,

R2

= 22Sn,

(4)

IC2

= 7mA and

From here, it can be seen that the output
voltage is approximately 3.3V to give relatively equal positive and negative output swings.
Diode 0 5 is included for bias purposes to
allow direct coupling of RF2 to the base of 0"
The dual feedback loops stabilize the DC
operating point of the amplifier.

The output stage is a Darlington pair (Oa and
O2 ) which increases the DC bias voltage on
the input stage (a,) to a more desirable
value, and also increases the feedback loop
gain. Resistor Ro optimizes the output VSWR
(Voltage Standing Wave Ratio). Inductors L,
and L2 are bondwire and lead inductances
which are roughly 3nH. These improve the
high-frequency impedance matches at input
and output by partially resonating with O.SpF
of pad and package capacitance.

POWER DISSIPATION
CONSIDERATIONS
When using the part at elevated temperature,
the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 2SmA (30mA max).
For operation at supply voltages other than
6V, see Figure 1 for Icc versus Vcc curves.
The supply current is inversely proportional to
temperature and varies no more than 1mA
between 2SoC and either temperature extreme. The change is 0.1 % per °C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat-sinking benefits can be realized by
mounting the SO and N package bodies
against the PC board plane.

Vee

R,
225

R,
650

Ro

l,

'0

3nH

VOUT

0,

V,N

3nH

R,

0,

140

RE'
12

140

200

Figure 15. Schematic Diagram

November 3, 1987

4-8

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5204 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (I.e., all
GND and Vce pins on the package). The
power supply should be deeoupled with a
capacitor as close to the Vcc pins as possible, and an RF choke should be inserted
between the supply and the device. Caution
should be exercised in the connection of
input and output pins. Standard microstrip
should be observed wherever possible. There
should be no solder bumps or burrs or any
obstructions in the signal path to cause
launching problems. The path should be as
straight as possible and lead lengths as short
as possible from the part to the cable connection. Another Important consideration is that
the input and output should be AC-coupled.

This is because at Vcc = 6V, the input is
approximately at 1V while the output is at
3.3V. The output must be decoupled Into a
low-impedance system, or the DC bias on the
output of the amplifier will be loaded down,
causing loss of output power. The easiest
way to decouple the entire amplifier is by
soldering a high-frequency chip capacitor dIrectly to the input and output pins of the
device. This circuit is shown in Figure 16.
Follow these recommendations to get the
best frequency response and noise Immunity.
The board design is as important as the
integrated circuit design itself.

vec

!---oVaUT
AC
COUPLING
CAPACITOR

SCATTERING PARAMETERS

Figure 16. Circuit Schematic for
Coupling and Power Supply Decoupllng

The primary specifications for the NE5204
are listed as S-parameters. S-parameters are
measurements of incident and reflected currents and voltages between the source, am-

plifier, and load as well as transmission
losses. The parameters for a two-port network are defined in Figure 17.

S" - INPUT RETURN LOSS
5"

S" -

POWER REFLECTED
FROM INPUT PORT

•

S" "VTRANSDUCER POWER GAIN

POWER AVAILABLE FROM
GENERATOR AT INPUT PORT

5"

I··

S" -

POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT

b.

4-9

OUTPUT RETURN LOSS
POWER REFLECTED
FROM OUTPUT PORT

REVERSE TRANSDUCER
POWER GAIN

Figure 17

November 3, 1987

S22 -

REVERSE TRANSMISSION LOSS
OR ISOLATION

a_ Two-Port Network Defined

FORWARD TRANSMISSION LOSS
OR INSERTION GAIN

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

son

5ystem

VCC=6V

VCC=8V

Vcc- 7V

......

~

~z

.~

Vcc=~V

~"

vcc=.voL ~~

-TA,=2S·C

Vee= 5V...J

i!:

I. I.'

r----

I-6

I.

8 102

FREQUENCY-MHz

!

Zo

~

Vee'" BY

TA

2-20

- -25

-3.

W

6

'8

=25°C

-15

~

f--

-2.

g

'f-I

- 2. f - -

-3.

8 102

/
6

8,()2

6

FREQUENCY -

.,03

MHz

d. 5'2 Isolation vs Frequency
40

.... 3.
'11 3.
....

r--....

"0
0",

I."

,.1

INPU~

C

6

0",

OUTPUT

~

Vcc:z 6V

f - - Zc=5on

T'=T

..'8 3.
"I
~:'.l
3.
"0

~

2.
20

/V

VCC=6V
Zo=7SQ

TA=2rC

I.'

c. Isolation vs Frequency (5,2)

4.

~5

a 103

1

FREQUENCY-MHz

....."'''"

,

• 10'

b. Insertion Gain vs Frequency (521 )

=1 501)

- ---

g

0: ..

,

-I.

.. -I'

z"'z
..

T..,=25°C

I.'

a. Insertion Gain vs Frequency (521 )

0:",

111.

Zo=75D

FREQUENCY-MHz

-10

.. w
"'''
Wo:

5ystem

.. 2.

vc~r:.c.,~~

-'o=SOO

7sn

2.

2.

• 102

"'z
zo: 25

"'"
"'''
.........
"'''
~o:

2'.. I
...... X
~g~;:~ -

-

"""~
a

20
1NPrT

",

iSs "
I.

'103

FREQUENCY_MHz

TA=2S o C

I.'

6

-""
6 8,03

8102

FREQUENCY -

e. Input (511) and Output (522) Return Loss vs
Frequency

MHz

f. Input (5,,) and Output (522) Return Loss vs
Frequency

Figure 18

November 3, 1987

r--- -OUTPUT

~w

4-10

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

Actual 5-parameter measurements, using an
HP network analyzer (model 8505A) and an
HP 5-parameter tester (models 8503A1B),
are shown in Figure 18.

Relationships exist between the input and
output return losses and the voltage standing
wave ratios. These relationships are as follows:

Values for Figure 20 are measured and specified in the data sheet to ease adaptation and
comparison of the NE5204 to other highfrequency amplifiers. The most important parameter is 521. It is defined as the square root
of the power gain, and, in decibels, is equal to
voltage gain as shown below:

INPUT RETURN L055 = S11dB
511dB = 20Log 15" I

Zo = Z'N = ZoUT for the NE5204

0-1
0-

V,N 2

P'N = - Zo

NE5204

2
~OpOUT-_ VOUT
--

Zo

Zo

0

VOUT 2

--2-

P'N

--2-

Y,N

V,N'

P, =V, 2
P, = Insertion Power Gain
V, = Insertion Voltage Gain
Measured value for the
NE5204 = 1521 12 = 100

1- 5 "

OUTPUT V5WR =

11 + 5221

-I--I";; 1.5
1 - 522

The saturated output power is a measure of
the amplifier's ability to deliver power into an
external load. It is the value of the amplifier's
output power when the input is heavily overdriven. This includes the sum of the power in
all harmonics.

POUT

= - - = 1521 12 = 100

and V,

= -I- - I ,.;; 1.5

The 1dB gain compression is a measurement
of the output power level where the smallsignal insertion gain magnitude decreases
1dB from ItS low power value. The decrease
is due to non-linearities In the amplifier, an
Indication of the point of transition between
small-signal operation and the large-signal
mode.

Zo

:. P,

INPUT V5WR

The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.

11 + 5,,1

1dB GAIN COMPRESSION AND
SATURATED OUTPUT POWER

z;;- = VOUT2 = P,
:. - - =
POUT

OUTPUT RETURN LOSS = S22dB
522dB = 20Log I 5221

P'N
VOUT

= - - = v'PI = 521 = 10
Y,N

In decibels:
P'(dB)

= 10Log

1521 12 = 20dB

INTERMODULATION INTERCEPT
TESTS

V, (dB) = 20Log 521 = 20dB
:. P'(dB)

= V'(dB) = 521 (dB) = 20dB

Also measured on the same system are the
respective voltage standing-wave ratios.
These are shown in Figure 19. The VSWR
can be seen to be below 1.5 across the entire
operational frequency range.

The intermodulation intercept is an expression of the low level linearity of the amplifier.
The Intermodulation ratio is the difference in
dB between the fundamental output Signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure

2.0
1.•
1.8
1.7
a:
jI: 1.6
'"....> 1.5
iI!

The intercept point IS determined by measuring the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept pOint is
known, the intermodulallOn ratio can be determined by the reverse process. The second-order IMR is equal to the difference
between the second-order intercept and the
fundamental output level. The third-order IMR
is equal to twice the difference between the
third-order intercept and the fundamental output level. These are expressed as:
IP2 = POUT + IMR2
IP3 = POUT + IMR3/2
where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second- and thlrdorder output intercepts in dBm, and IMR2 and
IMR3 are the second- and third- order intermodulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small-signal operating range of the amplifier. Above some output
level which is below the 1dB compression
point, the active device moves Into largesignal operation. At this point, the intermodulation products no longer follow the straightline output slopes, and the intercept descnption is no longer valid. It is therefore important
to measure IP2 and IP3 at output levels well
below 1dB compression. One must be care-

20
19
18
17
'"jI: 16
>
....::> 1.5
1,

'"

...

:::>

a. I.'

20, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the fundamental output plotted against itself with a 1dB
to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.

f=

Zo=750
1.3
1.2
1.1 I-- Zo=500
1.0
10'

::>
0

6

13
12

:-'-'Zo=7SH

11 -Zo=50n
10
10'

8 102

FREQUENCY -MHz

6

8 102

FREQUENCY -MHz

a. Input VSWR vs Frequency
b. Output VSWR vs Frequency
Figure 19. Input/Output VSWR vs Frequency
November 3, 1987

4·11

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

ful, however, not to select levels which are
too low, because the test equipment may not
be able to recover the signal from the nOise.
For the NE5204, an output level of -1 O.5dBm
was chosen with fundamental frequencies of
100.000 and 100.01MHz, respectively.

ADDITIONAL READING ON
SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers; by Ralph S. Carson of the University of
Missouri, Rolla, Copyright 1985, published by
John Wiley & Sons, Inc.

+30r--T~H-'~RD~0~R~D~ER~r--,--cr~r-~2N-D~OCR~D~ER~

+20

INTERCEPT POINT
1 dB --r
T
T

+10

COMPRESSION
POINT
-

+

I

I

-60

1 RESPONSE ______L-__
-50

-40 -30

I __

L-~

-20

-10

!

Figure 20

4-12

i __

~~

o

INPUT LEVEL
d8m

S-Parameter Design, HP App Note 154, 1972.

---i--

RfSP9NSE
3RD ORDER

-30
_40~

1

I

:--2~D O~D~Rr
-20

S-Parameter Techmques for Faster, More
Accurate Network Design, HP App Note 95-1,
Richard W. Anderson, 1967, HP Journal.

November 3, 1987

INTERCEPT
-rpOINT

-..10

~

-r-20

____

~

T30 ,..40

NE/SA/SE5205

Signetics

Wide-band High-Frequency
Amplifier
Product Specification

Linear Products
DESCRIPTION
The NE/SA/SES20S is a high-frequency
amplifier with a fixed insertion gain of
20dB. The gain is flat to ± O.SdB from DC
to 4S0MHz, and the -3dB bandwidth is
greater than 600MHz in the EC package.
This performance makes the amplifier
ideal for cable TV applications. For lower
frequency applications, the part is also
available in industrial standard dual inline and small outline packages. The
NE/SA/SES20S operates with a single
supply of 6V, and only draws 24mA of
supply current, which is much less than
comparable hybrid parts. The noise figure is 4.8dB in a 7Sn system and 6dB in
a son system.
Until now, most RF or high-frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high-frequency
gain stages. These include high-power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NE/SAI
SES20S solves these problems by incorporating a wide-band amplifier on a single monolithic chip.
The part is well matched to SO or 7Sn
input and output impedances. The
Standing Wave Ratios in SO and 7Sn
systems do not exceed 1.S on either the
input or output from DC to the -3dB
bandwidth limit.
Since the part is a small monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects. A TO-46 metal
can is also available that has a case
connection for RF grounding which increases the -3dB frequency to 600MHz.
The Cerdip package is hermetically
sealed, and can operate over the full
-SsoC to + 12SoC range.
No external components are needed
other than AC coupling capacitors because the NE/SAlSES20S is internally
compensated and matched to SO and
November 3, 1987

7sn. The amplifier has very good distortion specifications, with second and
third-order intermodulation intercepts of
+24dBm and +17dBm respectively at
100MHz.

PIN CONFIGURATIONS
N, FE, D Packages

The device is ideally suited for 7Sn
cable television applications such as
decoder boxes, satellite receiver / decoders, and front-end amplifiers for TV receivers. It is also useful for amplified
splitters and antenna amplifiers.
The part is matched well for son test
equipment such as signal generators,
oscilloscopes, frequency counters and
all kinds of signal analyzers. Other applications at son include mobile radio, CB
radio and data/video transmission in
fiber optics, as well as broad-band LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SAlSES20Ss in series
as required, without any degradation in
amplifier stability.

TOP VIEW

EC Package

NOTE:

Tab denotes Pin 1

FEATURES
• 600MHz bandwidth
• 20dB insertion gain
• 4.8dB (6dB) noise figure
Zo 75n (Zo 50n)
• No external components required
• Input and output impedances
matched to 50175n systems
• Surface mount package available
• MIL-STD processing available

=

=

APPLICATIONS
•
•
•
•
•
•
•
•
•

75n cable TV decoder boxes
Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
OSCilloscopes
Signal analyzers
Broad-band LANs
Fiber-optics

•
•
•
•

Modems
Mobile radio
Security systems
Telecommunications

4-13

853-0058 91249

•

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to
o to

8-PIn Plastic SO
4-Pln Metal can
8-Pln Cerdip
8-PIn Plastic DIP

ORDER CODE

+70°C

NE5205D

+70°C

NE5205EC

+ 70°C

NE5205FE

+70°C

NE5205N

8-Pln Plastic SO

-40°C to + 85°C

8-Pln Plastic DIP

-40°C to + 85°C

SA5205N

8-Pln Cerdlp

-40°C to + 85°C

SA5205FE

8-Pin Cerdlp

-55°C to + 125°C

SE5205FE

8-Pln Plastic DIP

-55°C to + 125°C

SE5205N

SA5205D

EQUIVALENT SCHEMATIC
Vee

Ro
::J-----_---<~_w_---o YOUT

Q,

v'oo---_-.["

November 3, 1987

4-14

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNIT

Vee

Supply voltage

9

V

VAC

AC input voltage

5

Vp_p

TA

Operating ambient temperature range
NE grade
SA grade
SE grade

o to +70
-40 to +85
-55 to + 125

·C
·C
·C

780
1160
780
1250

mW
mW
mW
mW

PDMAX

Maximum power dissipation,
T A = 25·C (still-air) 1. 2
FE package
N package
D package
EC package

NOTES:
1. Derate above 2SoC, at the following rates:
FE package at 6.2mW I"C
N package at 9.3mWI"C
D package at 6.2mW I"C
EC package at 10.0mWI"C
2. See "Power Dissipation Considerations" section.

DC ELECTRICAL CHARACTERISTICS at Vcc = 6V, Zs = ZL = Zo = 50n and TA = 25·C, in all packages, unless otherwise
specified.
SE5205
PARAMETER

SYMBOL

NE/SA5205
UNIT

TEST CONDITIONS
Min

Typ

Max

Min

6.5
6.5

5
5

Operating supply voltage range

Over temperature

5
5

Icc

Supply current

Over temperature

20
19

24

30
31

20
19

S21

Insertion gain

f = 100MHz
Over temperature

17
16.5

19

21
21.5

17
16.5

SII

Input return loss

f

= 100MHz

D, N, FE

DC - fMAX D, N, FE
SII

Input return loss

25
12

Output return loss

f

= 100MHz

S22

Output return loss

f

= 100MHz

Isolation

f

27

IR

mA
mA

19

21
21.5

dB

12

12

-25

dB
dB

26

dB
dB

-25
-18

-18

dB
dB

10

= 100MHz

dB
dB

27

EC package

DC-fMAX

30
31

24

DC-FMAX
S12

24

10

D, N, FE

DC-fMAX

V
V

25

f = 100MHz EC package

Max

8
8

12

DC-fMAX EC
S22

Typ

dB
dB

Rise time

5

5

ps

Propagation delay

5

5

ps

November 3, 1987

4-15

I'

!ij"
!
!
I

Signetlcs Linear Products

Product Specification

NE/SA/SE5205

Wide-band High-Frequency Amplifier

DC ELECTRICAL CHARACTERISTICS

at Vee = 6V, Zs = ZL = Zo = 500 and TA = 25°C, in all packages, unless otherwise
specified.
SE5205

SYMBOL

PARAMETER

NE/SA5205

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

BW

Bandwidth

±0.5dB 0, N

450

MHz

fMAX

Bandwidth

±0.5dB EC

500

MHz

fMAX

Bandwidth

±0.5dB FE

300

MHz

fMAX

Bandwidth

-3dB 0, N

550

MHz

fMAX

Bandwidth

-3dB EC

600

MHz

fMAX

Bandwidth

-3dB FE

c

i

:>

u

~

..

!;

2.

400

400

MHz

NOise figure (750)

f= 100MHz

4.8

4.8

Noise figure (500)

f= 100MHz

6.0

6.0

dB

Saturated output power

f= 100MHz

+7.0

+7.0

dBm

dB

1dB gain compression

f= 100MHz

+4.0

+4.0

dBm

Third-order Intermodulation
Intercept (output)

f= 100MHz

+17

+17

dBm

Second-order Intermodulatlon
intercept (output)

f= 100MHz

+24

+24

dBm

35
3'
32

E 3.

...I

300

ID •

I-

~

T... = 25·C

VCC=8V

vpc"rv

~1

28

2.

I
Ii

Zo='"
TA=2S-C

"'-

~

VCC=8V
VCC=5Y

......::

22

~

20

,.

5
5

55

65

75

I I
'0'

SUPPLY VOLTAGE-V

I

•

102

• ',03

t

FR£OUENCY-_

0P048SOS

Figure 1. Supply Current va Supply Voltage

Figure 2_ Noise Figure VB Frequency

25

ZS
~

I

-s5J~1ff-

VC:~.,;~~
VCC=6V
Vce=5V

-Zo= _
_

,0

TA22S'C

T!=
T.=ZS"C

""
'"""

T'.85'~tt.
T..,=12S·C

-Vcc*8V

-Zo=5OO

~

10

'0'

• ',02

•

10'

• 103

Figure 3. Insertion Gain vs Frequency (S2,)

November 3, 1987

• • 102

FREQUENCY-MHz

FREQUENCY-MHz

Figure 4. Insertion Gain vs Frequency (S2,)

4-16

Product Specification

Signetics Linear Products

Wide-band High-Frequency Amplifier

11
10
9

.

i

..

....I

>

....
....

~
5

Vcc:z7V

•
7

,."....--

....

~

•

•

I 102

~
z
8

.'"

"""

........

.......

YS

6

10'

• 102

• • 103

FREQUENCY -MHz

Figure 6. 1dB Gain Compression vs Frequency

Frequency

.
......
.

30

E

~
....
I>.

35

/

30

~

/'
/

25

f

20

Q

TA=2SOC
Zo = 500

20

15

""

/

II:

0

I
Q

I

15

25

;!;
II:

Q

II:

Vee=5V

1
0

• 103

40

....

;!;

II:

.....
"""" .....

Vee=6V

-4
-5
-6

I>.

II:

Vee=7V

-Zo-soo
-3 T.=25'C

Figure 5. Saturated Output Power

~

-- """

Vee-IV

~ :~

FREQUENCY-MHz

u

-

U

Vcc=5V

6
5
4
3
2
1
0
-1
-2
-3 -Zo-500
-4 r-T.=25'C
-5

10'

E

10
9
I
7

Vee=IV

VCc z6V

-I

.
.....
.
.

NE/SA/SE5205

II:

1/
TA=25°C
zo=soo

r--

..,/

10

:;:

....

'04~~-:--~~~--~-L--IL-~~--!-.J'0
POWER SUPPLY VOLTAGE-V

POWER SUPPLY VOLTAGE-V

Figure 8. Third-Order Intercept vs
Supply Voltage

Figure 7. Second-Order Output Intercept vs
Supply Voltage

1.9

1.9

1.1

1.1

!5

1.7

1.7

~

1.4
1.3

1.6

;

1.6

1.5

5

1.5

=

~ 1.4

O

Zo=750

1.3

;---Zo=750

1.2

1.2

1.1 -

1.1 c-- Zo=soo

Zo=soo

1.0
10'

6

1.0
10'

8 102

• 102

Figure 10. Output VSWR

Figure 9. Input VSWR vs Frequency

November 3, 1987

6

FREQUENCY-MHz

FREQUENCY -MHz

4-17

VB

Frequency

~

Signetlcs Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

40r----r----r--r-r-r----r----r--r-~

'II

35

r--+---,-+-++----f----+---i--+--I

H

30

r--I----":;-....b-f--'f----i----i--+--t-l

III

~g

-10

-15

Zo =500
TA_2S·C

~i

j: 25 j---+-----I--+-+"Ioii"""':-..----i--i-+-l
.. w
WI!:
~

......"''''
~ ...

20

liE 5

15

",

VCcz6V

-30
10'

1010':'----:-----:---:-.-:!-.-10'-:2:----:------:---:-,~
• ...Jl03

Figure 11. Input (511) and Output (522) Return Loss va
Frequency

25

VCC=~V

-

Vcc=SV-

15

TAD -S5-:;;;eTA= 25·C
e-

'"
"

TA- asoc
TA=12S·C -'

-Zo-751l
r - Vcc· 6V

liE

f--

r--

Zo-7SIl
TA=2S·C
10

10
101

• • 103

25

VCC=]"""", '\
20

Z

:ll

• 102

",I

Figure 12. Isolation vs Frequency (512)

VCC=~V .......

III

~

8

FREQUENCY-MHz

FREQUENCY -MHz

"T
~
C!I

-

t---+---t--+-+-i----i---~J.:;-"':!j-j

-"

•

8

10'

103

• • 103

..
•

• 103

FREQUENCY-MHz

Figure 14. Insertion Gain vs Frequency (521)

Figure 13. Insertion Gain vs Frequency (521)

November 3, 1987

4-18

Ii

Signetlcs Linear Products

Wide-band High-Frequency Amplifier

THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic in Figure 15, the gain is set primarily by the equation:
VOUT

V;; = (RFl

NEjSAjSE5205

The DC input voltage level VIN can be determined by the equation:

where REl = 12n, VBE = O.BV, ICl = 5mA
and IC3 = 7mA (currents rated at Vcc = 6V).

(1)

Under the above conditions, VIN IS approxi·
mately equal to 1V.

which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wideband terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, REl and the base resistance of 0 ,
are kept as low as possible while RF2 is
maximized.

Level shifting is achieved by emitter-follower
03 and diode 0 4 which provide shunt feedback to the emitter of 0, via RF1. The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shunt
feedback loading on the output. The value of
RFl = 140n is chosen to give the desired
nominal gain. The DC output voltage VOUT
can be determined by:

+ RE1)/REl

The noise figure is given by the following
equation:
NF=

VOUT = Vcc - (1c2+ IC6)R2,

(4)

where Vcc = 6V, R2 = 225n, IC2 = 7mA and
IC6= 5mA.
dB (2)

10 Log {

where ICl = 5.5mA, REl = 12n, rb = 130n,
KT /q = 26mV at 25°C and Ro = 50 for a 50n
system and 75 for a 75n system.

From here it can be seen that the output
voltage is approximately 3.3V to give relatively equal positive and negative output swi ngs.
Diode as is included for bias purposes to
allow direct coupling of RF2 to the base of 0 , .
The dual feedback loops stabilize the DC
operating point of the amplifier.

The output stage is a Darlington pair (06 and
02) which increases the DC bias voltage on
the Input stage (0,) to a more desirable
value, and also Increases the feedback loop
gain. Resistor Ro optimizes the output VSWR
(Voltage Standing Wave Ratio). Inductors L,
and L2 are bondwire and lead Inductances
which are roughly 3nH. These improve the
high-frequency Impedance matches at input
and output by partially resonating with 0.5pF
of pad and package capacitance.

POWER DISSIPATION
CONSIDERATIONS
When uSing the part at elevated temperature,
the engineer should consider the power dissl·
pation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 25mA (30mA Max).
For operation at supply voltages other than
6V, see Figure 1 for Icc versus VCC curves.
The supply current IS inversely proportional to
temperature and vanes no more than 1mA
between 25°C and either temperature extreme. The change is 0.1 % per °C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat sinking benefits can be realized by
mounting the D and EC package body against
the PC board plane.

vee

R,
225

R,
650

Ao

L,

10

lnH

VOUT

L,
VIN

0,

RE'
12
RE'
12

Figure 15. Schematic Diagram
November 3, 1987

I:

Product Specification

4-19

•

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-bond High-Frequency Amplifier

PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5205 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (I.e., all
GND and Vee pinS on the SO package). In
addition, if the EC package is used, the case
should be soldered to the ground plane. The
power supply should be decoupled with a
capacitor as close to the Vee pins as possible
and an RF choke should be Inserted between
the supply and the device. Caution should be
exercised In the connection of input and
output pins. Standard microstrip should be
observed wherever possible. There should be
no solder bumps or burrs or any obstructions
in the signal path to cause launching problems. The path should be as straight as
possible and lead lengths as short as possible from the part to the cable connection.
Another important consideration is that the

input and output should be AC coupled. This
is because at Vee = 6V, the input is approximately at 1V while the output is at 3.3V. The
output must be decoupled into a low impedance system or the DC bias on the output of
the amplifier will be loaded down causing loss
of output power. The easiest way to decouple
the entire amplifier is by soldering a high
frequency chip capacitor directly to the Input
and output pins of the device. This circuit is
shown in Figure 16. Follow these recommendations to get the best frequency response
and noise immunity. The board design is as
important as the integrated circuit design
itself.

source, amplifier and load as well as transmission losses. The parameters for a two-port
network are defined in Figure 17.

VCC

1----0 Vour
AC
COUPLING
CAPACITOR

SCATTERING PARAMETERS
The primary specifications for the NE/SAI
SE5205 are listed as S-parameters. S-parameters are measurements of Incident and reflected currents and voltages between the

Figure 16. Circuit Schematic
for Coupling and Power Supply
Decoupling

S21

•

I~

S'2

Figure 17a. Two·Port Network Defined

S" -

INPUT RETURN LOSS

S21 -

POWER REFLECTED
FROM INPUT PORT

S21 ",jTRANSDUCER POWER GAIN

POWER AVAILABLE FROM
GENERATOR AT INPUT PORT
S" -

FORWARD TRANSMISSION LOSS
OR INSERTION GAIN

S22 -

REVERSE TRANSMISSION LOSS
OR ISOLATION
REVERSE TRANSDUCER
POWER GAIN

OUTPUT RETURN LOSS
POWER REFLECTED
FROM OUTPUT PORT
POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT

Figure 17b

November 3, 1987

4·20

Actual S-parameter measurements using an
HP network analyzer (model 8505A) and an
HP S-parameter tester (models 8503A1B) are
shown in Figure 18.
Values for the figures below are measured
and specified in the data sheet to ease
adaptation and comparison of the NE/SAI
SE5205 to other high-frequency amplifiers.

Signetics Linear Products

Product Specification

Wide-band High-Frequency Amplifier

son

NEjSAjSE5205

7Sn

System

System

2S

2S

VCC",8V

r:-

I

ID

vc~c.cw"!,.r-

i20
z

..ffi

."\:

VCC=8V
5V

vee.:.

r - T,,=2SoC

10'

~

lS

.•

2

• 10'

FREQUENCY-MHz

......

~

vcc=~v

~

..

,

10

20

...

15 r-Zo=SCHl

~

i

~z

c

"~

Vee· 7V """> \

ID

10=750

I--

T.a. = 25°C

f----

10

.•

2

10'

'10>

"

YCC=5V

8102

.•

2

FREQUENCY-MHz

a. Insertion Gain vs Frequency (52,)

b. Insertion Gain vs Frequency (52')

-10

-10

I

I

-lS

¥!

Zo=l sDu

¥!

I

: II

J---t':I

~

~ -2S

II I...--tl,

~

I

Z

TA = 2S·C
VCC=6V

~

I

~

. . I~l . .I I
8 102

2

-20

,/1,1

VCC=6V

-

-2S

Zo = 750
TA=25°C

/'

I

I .

2

-lS

I

2-20

-30
'0'

-30

8103

2

'0'

FREQUENCY -MHz

4

•

2

•

4

'10'
FREQUENCY - MHz

Of'(J4800s

c. Isolation vs Frequency (5,2)

ID¥!

3S

~~

30

d. 5'2 Isolation vs Frequency
40

,,¥!

........

"I
I ..

~

-'z

I'" 2,
~t

"'...w'""...

.....
""
l:8

Zo-SOIl

2

.

z",

"'''
~tu

INPJ~

TA=2r C
lS

:g ..
09
-'z

OUTPUT

~

VCC=8Y

20-

10
10'

,

'10'

2

.....
... "
.....
""
3:8
w'"

~""

.•

3S
30

'10>

--

2S r - - f- OUTPUT
20

~

IN:rT

'S
10
'0'

FREQUENCY-MHz

2

4

.

VCC=6V

....... p<;

1/

20=750
TA=2SoC
8102

4

5

•

'10>

FREQUENCY - MHz
01'048205

OP046305

e. Input (5 11 ) and Output (522) Return Loss vs
Frequency

f. Input (511) and Output (522) Return Loss vs
Frequency

Figure 18

November 3, 1987

',0>

OP049108

40

"I

e 103

OP0479OS

OP047805

4-21

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

INPUT RETURN LOSS = Sl1dB
S,ldB = 20 Log Isl, 1

The most important parameter is S21' It is
defined as the square root of the power gain,
and, in decibels, is equal to voltage gain as
shown below:

OUTPUT RETURN LOSS = S22dB
S22dB = 20 Log I S221

VIN2

0-

Zo

NE/SAI f-o
SE5205
Zo

0-

The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.

11 +S,11
INPUT VSWR=-I--1';;1.5
1-S"

Zo = ZIN = ZOUT for the NE/SA/SE5205

PIN = - -

to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.

V
2
OUT
POUT=-f-o
Zo

11 + S221
OUTPUT VSWR = -I- - I .;; 1.5
1-S22

VOUT 2
POUT ~ VOUT 2
' - - = - - = - - = PI
VIN2
.. PIN
VIN 2

1dB GAIN COMPRESSION AND
SATURATED OUTPUT POWER
The 1dB gain compression is a measurement
of the output power level where the small·
signal insertion gain magnitude decreases
1dB from its low power value. The decrease
is due to nonlinearities in the amplifier, an
indication of the pOint of transition between
small·signal operation and the large signal
mode.

Zo
PI =V12
PI = Insertion Power Gain
VI = Insertion Voltage Gain
Measured value for the
NE/SA/SE5205 = I S21 12 = 100

The saturated output power is a measure of
the amplifier's ability to deliver power into an
external load. It is the value of the amplifier's
output power when the input is heavily over·
driven. This includes the sum of the power in
all harmonics.

:. PI =POUT
- - = I S21 12 = 100
PIN
VOUT
_
and VI = - - = V PI = S21 = 10
VIN
In decibels:
PI(dB) = 10 Log I S21 12 = 20dB

INTERMODULATION INTERCEPT
TESTS

VI(dB) = 20 Log S21 = 20dB

The intermodulation intercept is an expres·
sion of the low level linearity of the amplifier.
The intermodulation ratio is the difference in
dB between the fundamental output signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure
20, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the funda·
mental output plotted against itself with a 1dB

:. PI(dB) = VI(dB) = S21 (dB) = 20dB
Also measured on the same system are the
respective voltage standing wave ratios.
These are shown in Figure 19. The VSWR
can be seen to be below 1.5 across the entire
operational frequency range.
Relationships exist between the input and
output return losses and the voltage standing
wave ratios. These relationships are as fol·
lows:

The intercept point is determined by measur·
ing the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept point is
known, the intermodulation ratio can be de·
termined by the reverse process. The second
order IMR is equal to the difference between
the second order intercept and the funda·
mental output level. The third order IMR is
equal to twice the difference between the
third order intercept and the fundamental
output level. These are expressed as:
IP2 = POUT + IMR2
IP3 = POUT + IMR3/2
where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second and third
order output intercepts in dBm, and IMR2 and
IMR3 are the second and third order inter·
modulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small signal operat·
ing range of the amplifier. Above some output
level which is below the 1dB compression
point, the active device moves into large·
signal operation. At this point the intermodu·
lation products no longer follow the straight
line output slopes, and the intercept descrip'
tion is no longer valid. It is therefore important
to measure IP2 and IP3 at output levels well
below 1dB compression. One must be care·
lui, however, not to select too low levels
because the test equipment may not be able
to recover the signal from the noise. For the
NE/SA/SE5205 we have chosen an output
level of -1 0.5dBm with fundamental frequen·
cieso! 100.000 and 100.01 MHz, respectively.

,.

2.
I .•

, 9

I .•

T..,-25·C
Vee- 6V

1.7

~

i

0:

;0

.

1.6
1.5



:>

e::>
0

I.'

15
14
1.3

"1.1

1.1 -20=SOO
II

'--- 20= 7511

r--- 20 -

I.
I.'

I .•

I.'

17

I.

8102

FREQUENCY-MHz

son
6

a. Input VSWR vs Frequency

b. Output VSWR vs Frequency

Figure 19. Input/Output VSWR vs Frequency
November 3, 1987

8 102

FREQUENCY -MHz

4-22

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

ADDITIONAL READING ON
SCATTERING PARAMETERS

+30 r--;T~H:::'R=O':O=R:;'O=:ER::---'-~---';.--:l"'--===:=1

For more information regarding S-parameters, please refer to HIgh-Frequency AmplifIers by Ralph S. Carson of the University of
Missouri, Rolla, COPYright 1985; published by
John Wiley & Sons, Inc.
"S-Parameter Techniques for Faster, More
Accurate Network Design", HP App Note 951, Richard W. Anderson, 1967, HP Journal.

+20
+10

i

INTERCEPT POINT

1 dB ---r-

r

T

COMPRESSION

POINT

-

-10

-20

"S-Parameter Design", HP App Note 154,

-30

1972.

-40 IL-_---'-L_-L_C-..--'---'-_'--_---'
-60 -so -40 -30 -20 -10 0 .,..10 +20 .,.30 .,..40
INPUT LEVEL
d8m
OP04860S

Figure 20

November 3, 1987

4-23

NEjSE5539

Sighetics

High Frequency Operational
Amplifier
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The NE/SE5539 is a very wide bandwidth, high slew rate, monolithic operational amplifier for use in video amplifiers, RF amplifiers, and extremely high
slew rate amplifiers.

• Bandwidth
- Unity gain - 350M Hz
- Full power - 48MHz
- GBW - 1.2 GHz at 17dB
• Slew rate: 600/V JJS
• AVOL: 52dB typical
• Low noise - 4nV1v'Hi typical
• MIL-STD processing available

Emitter-follower inputs provide a true
differential high input impedance device.
Proper external compensation will allow
design operation over a wide range of
closed-loop gains, both inverting and
non-inverting, to meet specific design
requirements.

D, F. N Packages
+ INPUT

1

-VSUPPLY

3

12 FFiEQUENCY

COMPENSA11ON

VOSAdjlAVAdj 5

APPLICATIONS
•
•
•
•
•
•
•

High speed datacomm
Video monitors & TV
Satellite communications
Image processing
RF instrumentation & OSCillators
Magnetic storage
Military communications

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

14-Pin Plastic DIP

o to

+70'C

NE5539N

14-Pin Plastic SO

o to +70'C

NE5539D

14-Pin Cerdip

o to +70'C

NE5539F

14-Pin Plastic DIP

-55'C to + 125'C

SE5539N

14-Pin Cerdip

-55'C to + 125'C

SE5539F

ABSOLUTE MAXIMUM RATINGS 1
RATING

UNIT

Vee

Supply voltage

±12

V

POMAX

Maximum power disSipation,
TA = 25'C (still-air)2
F package
N package
D package

1.17
1.45
0.99

W
W
W

TSTG
TJ

Storage temperature range

-65 to + 150

'C

Max junction temperature

150

'C

TA

Operating temperature range
NE
SE

o to 70
-55 to + 125

'C
'C

300

'C

SYMBOL

TSOLO

PARAMETER

Lead temperature (10sec max)

NOTES;

1. Differential input voltage should not exceed O.25V to prevent excessive Input bias current and
common-mode voltage 2.SV. These voltage limits may be exceeded if current is limited to less

than lOrnA.
2. Derate above 25'C, at the following rates:
F package at 9.3 mW/'C
N package at 11.6 mW rc
D package at 7.9 mWrC

November 3, 1987

4-24

853-0814 91253

Product Specification

Signetics Unear Products

NEjSE5539

High Frequency Operational Amplifier

EQUIVALENT CIRCUIT
('2) FREOUfNCY

coW'
(to)

..

+Vcc

(-) 14

VERTING INPUT

I
V

.......

tTl'
NO N-INVERTIHG
INPUT

K

~J

),-

,

V

?- I . . . .

t-

•

&.

......
~

(8) OUTPUT

2.2K
(7)GND

J.......

H::

~
(3)

-vee

DC ELECTRICAL CHARACTERISTICS Vcc = ± av, T A = 25°C, unless otherwise specified.
SE5539
SYMBOL

PARAMETER

UNIT
Min

Vos

Input offset voltage

Vo = OV, Rs = lOOn

2

5

TA = 25°C

2

3

Over temp

0.1

3

TA = 25°C

0.1

1

CMRR

Common-mode rejection ratio

Min

Typ

Max

2.5

5

mV



o·
~

-

----~--.--...- - - -

+

OUTPUT

i'--.

.........
OdS

..........

-

r-.

....'"
w

(/)

...........
1SO·
RF

"

270 350

---lCof-----vvvRc

I (MHz)

R1

ALTERNATE
LOWERS OFFSET

a_ Open-Loop Gain - No
Compensation (Computer
Simulation)
a_ Pin 12 Compensation Showing Internal Connections - Inverting

OUTPUT

I\. 1\ 11
\I

\

II

\.

.J\
"

II

INPUT

5nslDIV

OUTPUT

b_ Closed-Loop Non-Inverting
Response - No Compensation
(Computer SimulationOscillation is Evident)
Figure 11
To indicate the accuracy of this system, the
actual open-loop gain IS compared to the
computer plots In Figures 14 and 15. The real
payoff for this system IS that once a credible
simulation is achieved, any outside CirCUit can
be modeled around the op amp. This would
be used to check for feasibility before breadboarding in the lab. The internal circuit can be
treated like a black box and the outside CirCUit
program altered to whatever application the
user would like to examine.

December 1988

RF

---lCof-----vvvRc

R1

ALTERNATE
LOWERS OFFSET

b_ Pin 12 Compensation Showing Internal Connections - Non-Inverting
Figure 12

4-36

Signetics linear Products

Application Note

Compensation Techniques for Use with the NE/SE5539

AN140

I
46

a;
E

..

..........

-

......

>

''''
II
..........

..........

OdB

140 0

44

..........

INPUT

r-.. "

'"

OUTPUT

.............

OdB

"

'"

I

"-

92"-'

f---.

"

I
I

I I

250350

I

b. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 1pF,
Av = 3 (Computer
Simulation - Underdamped)

=

43

!

IL
,
1

I

I

.........

.........

1\ '
!\ I
\!

c-------

............. OdB

",

'---,

~

73°

r---"'-

--\;
-rr

-t---

I
I

75

5ns/DIV

350

=

=

=

O~TPGT
>

IA

J

J

I

:

I

I

INPut

;;
:;
E

g

I !
I
, ,
j

I

I

\

I

"f\.
l.
I

I

I

I I

I

Sns/OIV

t (MHz)

d. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 2pF, Av 3
(Computer Simulation - Critically-Damped)

=

c. Open-Loop Pin 12 CompensationRc = 200n, Cc 2pF (Computer
Simulation)

-- ~

I
INPUT

=

I

I
I

OUTPUT

I

350

f(MHz)

a. Open-Loop Pin 12 CompensationRc = 200n, Cc = 1pF,
(Computer Simulation)

I ,
i

150

5nsJDIV

f(MHz)

e. Open-Loop Pin 12 CompensationRc 200n, Cc = 3pF,
(Computer Simulation)

=

f. Closed-Loop Non-Inverting Pulse
Response - Rc 200n, Cc 3pF, Av 3
(Computer Simulation - Overdamped)

=

=

=

Figure 13

1. J. Millman and C. C, Halkias: Integrated
Electronics: Analog and DigItal CIrcuits and
Systems, McGraw-Hili Book Company, New
York, 1972.

120

100
80
60

40

-

a;

ss

..
E
>

2. A. Vladlmlrescu, Kalhe Zhang, A. R. Newton, D. 0, Peterson, A. SanqUiovannl-Vmcentelll: "Spice Version 2G," University of California, Berkeley, California, August 10, 1981,

........

"

20

.........
350

f(MHz)

-20
1MHz

10MHz

100MHz 350 1GHz

Figure 14. Actual Open-Loop Gain
Measured in Lab

December 1988

Figure 15. Computer-Generated
Open-Loop Gain

4-37

3. Signetics: Analog Data Manual 1983,
Signetics Corporation, Sunnyvale, California
1983.

NE5592

Signetics

Video Amplifier
Product Specification

Linear Products
DESCRIPTION

FEATURES

The NE5592 is a dual monolithic, twostage, differential output, wideband video amplifier. It offers a fixed gain of 400
without external components and an
adjustable gain from 400 to 0 with one
external resistor. The input stage has
been designed so that with the addition
of a few external reactive elements between the gain select terminals, the
circuit can function as a high-pass, lowpass, or band-pass filter. This feature
makes the circuit ideal for use as a video
or pulse amplifier in communications,
magnetic memories, display, video recorder systems, and floppy disk head
amplifiers.

•
•
•
•

PIN CONFIGURATION

110MHz unity gain bandwidth
Adjustable gain from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components

D, N Packages

APPLICATIONS
• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications
TOP VIEW

• Magnetic memory
• Video recorder systems

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

14-Pin PlastiC DIP

o to

70°C

NE5592N

14-PIn SO package

o to

70°C

NE5592D

EQUIVALENT CIRCUIT
r----.-----4~----~----1-------~----~---O+v

R.

R.

o.

+---___1-..,==+-+-------t---~HMo-+T--___1--o OUTPUT 1
INPUT 1
OUTPUT 2
G

a"

~--_+----_+--------~----------~--_4--~-v

October 20, 1987

4-38

853-0888 91020

Product Specification

Signetics Linear Products

NE5592

Video Amplifier

ABSOLUTE MAXIMUM RATINGS

T A = 25°C, unless otherwise specified,

PARAMETER

RATING

UNIT

VCC

Supply voltage

±8

V

VIN

Differential input voltage

±5

V

VCM

Common mode Input voltage

±6

V

lOUT

Output current

10

mA

TA

Operating temperature range
NE5592

TSTG

Storage temperature range

-65 to + 150

°C

PD MAX

Maximum power dissipation,
TA = 25°C (still air) 1
D package
N package

1.03
1.48

W
W

SYMBOL

o to

+70

°C

NOTE:
1. Derate above 25°C at the follOWing rates:
D package 8 3mW I"C
N package 11.9mWI"C

DC ELECTRICAL CHARACTERISTICS

T A = + 25°C, Vss = ± SV, VCM = 0, unless otherwise specified. Recommended
operating supply voltage is Vs = ± S.OV, and gain select pins are connected together.
LIMITS

SYMBOL

PARAMETER

UNITS

TEST CONDITIONS

RL = 2kn, VOUT

= 3Vp_p

Min

Typ

Max

400

480

SOO

3

14

AVOL

Differential voltage gain

RIN

Input resistance

CIN

Input capacitance

2.5

los

Input offset current

0.3

3

vA

ISlAS

Input bias current

5

20

p.A

Input noise voltage
VIN

BW 1kHz to 10MHz

CMRR

Common-mode rejection ratio

PSRR

Supply voltage rejection ratio
Channel separation

Vos

Output offset voltage
gain select pins open

VCM

Output common-mode voltage

VOUT

Output differential voltage swing

ROUT

Output resistance

Icc

Power supply current
(total lor both sides)

October 20, 1987

kn
pF

4

nV/YHz

± 1.0

Input voltage range

VIV

V

VCM ± 1V, I < 100kHz
VCM ± 1V, f = 5MHz

SO

93
87

dB
dB

tNs= ± 0.5V

50

85

dB

VOUT = 1Vp.p; f = 100kHz
(output referenced) RL = 1kn

S5

70

dB

RL = 00
RL = 00

0.5
0.25

1.5
0.75

V
V

3.4

V

RL = 00

2.4

3.1

RL=2kn

3.0

4.0

V

20

n

RL

4-39

=

00

35

44

mA

Product Specification

Signetics Linear Products

NE5592

Video Amplifier

DC ELECTRICAL CHARACTERISTICS

VSS - ± av, VCM = 0, O·C';; TA';; 70·C, unless othelWise specified. Recommended
operating supply voltage Is Vs - ± a.ov, and gain select pins are connected together.

LIMITS
SYMBOL

PARAMETER

AVOL

Differential voltage gain

R'N

Input resistance

los

I nput offset current

ISlAS

Input bias current

Y,N

Input voltage range

CMRR

Common-mode rejection ratio

PSRR

Supply voltage rejection ratio
Channel separation

Vos

Output offset voltage
gain select pins connected
together
gain select pins open

Your

Output differential voltage swing

Icc

Power supply current
(total for both sides)

AC ELECTRICAL CHARACTERISTICS

UNITS

TEST CONDITIONS
RL - 2kSl, VOUT - 3Vp.p

VCM ± W, f < 100kHz
Rs-tP
AVs~

± 0.5V

Min

Typ

Max

350

430

aOO

1

11

VIV
kSl

5

p.A

30

p.A

±1.0

V

55

dB

50

dB

Your - Wp.p; f = 100kHz
(output referenced) RL = lkSl

70

dB

RL == 00

1.5

V

RL -

1.0

V

00

RL-2kSl
RL

2.8

V
47

_00

mA

TA - + 25·C, Vss = ± av, VCM - 0, unless otherwise specified. Recommended
operating supply voltage Vs = ± a.ov. Gain select pins connected together.

LIMITS
SYMBOL

PARAMETER

UNITS

TEST CONDITIONS
Min

BW
tR
tpD

Bandwidth

Vour- 1Vp.P

Typ

Max

25

MHz

Rise time

15

20

ns

Propagation delay

7.5

12

ns

October 20, 1987

VOUT -lVp.p

4·40

Signetics Unear Products

Product Specification

Video Amplifier

NE5592

TYPICAL PERFORMANCE CHARACTERISTICS
I

=

Common-Mode ReJection Ratio
a Function of Frequency

Output Voltage Swing as a
Function of Frequency

Vs ±IV
=

i:

lit. =

lidl
TA, • 250C

iI::
I~
ts

Channel Separation as a
Function of Frequency
,

~-30

,

II:

~.-4O

= 2Sec
As·O

TA

I,

I

I

..

1=:

I

-90
10.

105

107

101

...!

I

iL80

o
104

10'

I

iii-so I

1

YIN = 2V"

105

!!!!

..

"

I IT~,= 2~"C
I!

II II i I

!-20

V. -= i:8V

I lilt. = lidl

1111 II

0
• -10

107

10'

10'

10'

fREOUENCY • Hz

FREOUENCY • Hz

00' . . . .

DIfferential Overdrive
Recovery Time

Pulse Response as a
Function of Supply Voltage

so

~45

~:: is6~-

!I!

40

:

35

~30

8 25

1/

lI!2O

~ 15

1,0I~

5

00

40

'"

V

Pulse Response as a
Function of Temperature

> 1.4I-T"

= 25DC

Vs = ±8V
..... V. =

.;. 1.2

:::-

±IV

! ,--------- 7
~
l'
r:=t=t=~~~~~~.~~=itI3:V~
~ 0.410.8

.. 0.1

V-

5 0.2f-_+-+-IIFI!_+_-1_f-__+_-_l-_-+_-__+_-l
O~~~-r~~+-t-~

80

120

160

-15-10-5 0 5 10 15 20 25 30 35
nUE· na

200

1.6
1.4

I
HL J,~ +-H-+-+-H

1.8

1.2
1

V. =

±lvi

At. =

lldll

I

~ :::

!;
..

§

O. 4
0.2

TA

1.:

oec
~

TA = 25~_
I I I
TA = 7O"C-

1

--

.++-

-0.2

-D.'

-15-10-5 0

I

5 10 15 20 25 30 35

nuE-na

DIffERENTIAL INPUT VOLTAGE· mV
OP18130S

Voltage Gain as a
Function of Temperature

Gain vs Frequency as a
Function of Temperature
10

1.'
•

I

!

At. =

0

~A==':~

I

~

~4O

0.'
-0.4

lkQ

,so

0 .•

~

4

Vs = i:6V

1.2

!:;

Voltage Gain as a
Function of Supply Voltage

TA = O"C

~3O

f-TA. 2S-C

>20

f- ~AI ilr'~

10

IIII! I

g

11111
-1 .•

010203040501070
TEMPalATURE:'C

10S

10'

107

, .,'"

1

"

1

~

!

-4

10'

fREOUENCV • Hz

101

~

-5
-1 3
SUPPLV VOLTAGE· V
OP1tuD8

October 20. 1987

4-41

Product Specification

Signetics Linear Products

NE5592

Video Amplifier

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Phase vs Frequency as a
Function of Supply Voltage

Gain vs Frequency as a
Function of Supply Voltage
60

III

IIII
Vs

50

~

~

.

T. = 25"C
RL = lkO

= ±av

I

Vs = ±6V
40

."'"

"

Vs = ±3V

Q

~
~

~ 30
0-

l\

-'

II
10'

10&

10'

10'

10'

= 25"C
= lid)

TA,

30

so

Vs

10'

i!

(J

90

~

Vs = tay
Vs
t6V
Vs = t3Y

>

=

~ 180
210
240
10'

,. IIII
10'

10'

I

10'

""

1
10- 1

10'

1

10

6

= 25"C

TA

= t6V

ffi

'"

::>
U

'"'"u

:>

~ 20 ......

..

~ 33

:>

w'"

",.

..

>-

~5
0-,.

'/

~!

....
0-0-

0

10 20

30 40 50 60
TEMPERATURE - "C

70

1

~

±6V

V-

~

.
'"
~

.

J

0-

"
~
w

100

102

10'

10"

LOAD RESISTANCE· OHMS

0

10

..

= 25"C
= t6V

R = 1000
1\

10

::>

20 30 40 50 80
TEMPERATURE - "C

OP18730S

October 20, t 987

8

0-

i!

10

Vs

1000

S
z

V

i!

::>
0

TA

~

0<

'/

15

::>

0-

0
10'

=

.;.

u 20

~

0-

7
4
5
6
SUPPLY VOLTAG~ - ±V

Input Noise Voltage as a
Function of Frequency

.;.
Z

.
::>

Vs

I

3

OPl'720S

Input Resistance as a
Function of Temperature
25

Ii

3

2

8

GAIN 1

Vs = tay
}4 TA = 2S-C
~

~

0

4
6
7
5
SUPPLY VOLTAGE - ±V

OP18710S

Output Voltage Swing as a
Function of Load Resistance

"

,---

~~ 1

0
3

OP18700S

i

~

2

~d-. I/>~:i::>

~ 10

'"

I#-

. '" .
Zo-

",.
30

TA=,25"CJ

5

'i~
"

",.

0-

"

::"1

",.

.. 40
E

.'"

OP18690S

Output Voltage Swing and Sink
Current as a Function of Supply
Voltage

Supply Current as a
Function of Supply Voltage
50

:'34

10' 10"

RADJ - OHMS
OPl86BOS

Supply Current as a
Function of Temperature

"E

"

10' 10' 10'

FREQUENCY· Hz

OP18670S

Vs

25'C

0-

FREQUENCY - Hz

35

=

= fay

"

10

"-'0

120

~ 150

20

10
10'

TA
RL

0

..

0

>

...'"

Voltage Gain as a
Function of RADJ

70

10'

10'

10'

10·

10"

FREQUENCY· Hz
OP1874OS

4-42

1
1

OP1l7SOS

Signetics linear Products

Product Specification

NE5592

Video Amplifier

TEST CIRCUITS TA = 25'C, unless otherwise specified.

51

October 20, 1987

4-43

51

1K

1K

NEjSAjSE592

Signetics

Video Amplifier
Product Specification

Unear Products
DESCRIPTION

FEATURES

The NE/SAlSE592 is a monolithic, twostage, differential output, wideband video amplifier. It offers fixed gains of 100
and 400 without external components
and adjustable gains from 400 to 0 with
one external resistor. The input stage
has been designed so that with the
addition of a few external reactive elements between the gain select terminals, the circuit can function as a highpass, low-pass, or band-pass filter. This
feature makes the circuit ideal for use as
a video or pulse amplifier in communications, magnetic memories, display, video
recorder systems, and floppy disk head
amplifiers. Now available in an a-pin
version with fixed gain of 400 without
external components and adjustable
gain from 400 to 0 with one external
resistor.

•
•
•
•

PIN CONFIGURATIONS

120MHz unity gain bandwidth
Adjustable gains from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components
• MIL-STD processing available

D, F, N Packages
INPUT2

INPUT 1

1

HC

G2A GAIN
SELECT

11

:~~~~'N
y+

APPUCATIONS
• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications

OUTPUT 2

7

TOP VIEW

H Package-

• Magnetic memory
• Video recorder systems
INPUT 2

G~Et'J

OUTPUT 1

EQUIVALENT CIRCUIT
.---~----~------.---~------

__

V-

~----.--o.v

NOTES:
Pm 5 connected to case
*Metal cans (H) not recommended for

2008

new

deSIgns

D, F, N, Packages

INPUT

INPUT 1
OUTPUT 2

G...

G1\Et~~

2

7

V-

3

8

OUTPUT 2 4

INPUT 1

~~t~N
v.

5 OUTPUT 1
TOP VIEW

"""',os

~--~----~----------~------------~--+--o-v

"""'''

November 3, 1987

4-44

853-0911 91255

Product Specification

Signetics Linear Products

NEjSAjSE592

Video Amplifier

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

14-Pin Plastic 01 P

o to +70·C

NE592N14

14-Pln Cerdip

o to +70·C

NE592F14

14-Pin Cerdip

- 55·C to + 125·C

SE592F14

o to +70·C

NE592D14

o to +70·C

NE592N8

DESCRIPTION

14-Pin SO
8-PIn Plastic DIP
8-Pin Cerdlp

-55·C to + 125·C

SE592F8

8-Pin Plastic DIP

-40·C to +85·C

SA592N8

8-Pin SO

o to +70·C

NE592D8

8-PIn SO

-40·C to +85·C

SA592D8

10-Lead Metal Can

o to +70·C

NE592H

10-Lead Metal Can

-55·C to + 125·C

SE592H

NOTE:
N8, N14, 08 and 014 package parts also available In "High" gaon version by addIng "H" before package
deslgnabon, Ie, NE592HD8

ABSOLUTE MAXIMUM RATINGS TA= + 25·C, unless otherwise specified.
SYMBOL

PARAMETER

RATING

UNIT

Vee

Supply voltage

±8

V

V,N

Differential input voltage

±5

V

VCM

Common-mode Input voltage

±6

V

lOUT

Output current

10

rnA

TA

Operating ambient temperature range
SE592
NE592

-40 to +85
o to +70

·C
·C

TSTG

Storage temperature range

-65 to +150

·C

Po MAX

Maximum power dissipation,
TA = 25·C (still air)1
F-14 package
F-8 package
0-14 package
0-8 package
H package
N-14 package
N-8 package

1.17
0.79
0.98
0.79
0.83
1.44
1.17

W
W
W
W
W
W
W

NOTE:
1. Derate above 25·C at the follOWIng rates
F-14 package at 9.3mW
F-8 package at 6.3mW
0-14 package at 7 BmW
O-B package at 6.3mW I·C
H package at 6. 7mW I·C
N-14 package at 11.5mWrC
N-8 package at 9.3mW/·C

rc
rc
rc

November 3, 1987

4-45

Signetics Linear Products

Product Specification

Video Amplifier

NE/SA/SE592

DC ELECTRICAL CHARACTERISTICS TA = + 25°G, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltages Vs = ± B.OV. All specifications apply to both standard and
high gain parts unless noted differently.
NE/SA592
PARAMETER

SYMBOL

AVOL

Differenllal voltage gain,
standard part
Gain 11
Gain 22. 4

RL

= 2kn,

VOUT

= 3Vp_p

High gain part
R'N

Input resistance
Gain 11
Gain 22 .4

G,N

Input capacltance 2

los

Input offset current

IBIAS

Input bias current

VNOISE

Input nOise voltage

Y,N

Input voltage range

GMRR

Common-mode rejection ratio
Gain 24
Gain 24

PSRR

Supply voltage rejection ratio
Gain 24

Vos

Output
Gain
Gain
Gain

offset voltage
1
24
33

VCM

Output common-mode voltage

VOUT

Output voltage swing
differential

ROUT

Output resistance

Icc

Power supply current

UNIT
Min

Typ

Max

Min

Typ

Max

250
80

400
100

600
120

300
90

400
100

500
110

400

500

600

10

4.0
30

Gain 24

20

VCM±IV, f< 100kHz
VCM± IV, f = 5MHz
t.Vs

= ±0.5V

RL

= 2kn

2.0

= 00

4-46

pF

0.4

3.0

9.0

30

9.0

20

12

IJ.A
IJ.A
IJ.VRMS

± 1.0

V

60

86
60

60

86
60

dB
dB

50

70

50

70

dB

0.35

1.5
1.5
0.75

2.4

2.9

3.4

3.0

4.0
20

RL

kn
kn

5.0

12

RL = 00
RL = 00
RL = 00
RL = 00

4.0
30

0.4

± 1.0

VIV
VIV
VIV

2.0

BW 1kHz to 10MHz

NOTES:
1. Gain select Pins G 1A and G 18 connected together.
2. Gain select Pins G2A and G28 connected together.
3. All gam select pins open
4. Applies to 10~ and 14·pln verSions only.

November 3, 1987

SE592

TEST CONDITIONS

18

0.35

1.5
1.0
0.75

2.4

2.9

3.4

3.0

4.0

18

V
V

20
24

V
V
V

n
24

mA

Product Specification

Signetics Linear Products

NEjSAjSE592

Video Amplifier

DC ELECTRICAL CHARACTERISTICS

Vss = ± 6V, VCM = 0, O°C';;; T A';;; 70°C for NE592; -40°C';;; T A';;; 85°C for SA592,
- 55°C';;; T A .;;; 125°C for SE592, unless otherwise specified. Recommended operating
supply voltages Vs = ± 6 OV. All specifications apply to both standard and high gain
parts unless noted differently.
NE/SA592

PARAMETER

SYMBOL

UNIT
Min

AVOL

R'N

Differential voltage gain,
standard part
Gain l'
Gain 22. 4

SE592

TEST CONDITIONS
Typ

Max

Min

Typ

Max

I

RL = 2kQ, VOUT = 3Vp.p

250
80
400

Input resistance
Gain 22,4

8.0

600
120
500

200
80

600
120

600

VIV
VIV
VIV
kQ

8.0

los

Input offset current

6.0

5.0

f,IA

IBIAS

Input bias current

40

40

IlA

Y'N

Input voltage range

CMRR

Common-mode rejection ratio
Gain 24

PSRR

Supply voltage rejection ratio
Gain 24

VOS

Output
Gain
Gain
Gain

VOUT

Output voltage swing
differential

Icc

Power supply current

VCM± 1V, f

< 100kHz

!!Ns = ± 0.5V
RL =
RL =
RL =

± 1.0

V

50

50

dB

50

50

dB

1.5
1.5
1.0

00
00
00

RL = 2kQ
RL =

± 1.0

1.5
1.2
1.0

V

2.5

2.8
27

00

V
V
V

27

mA

NOTES:
1. Gam select Pins G 1A and G 1B connected together.

2. Gain select Pins G2A and G28 connected together
3. All gain select pins open.
4. Applies to to- and 14-pln verSions only.

AC ELECTRICAL CHARACTERISTICS

TA = + 25°C, VSS = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltages Vs = ± 6.0V. All specifications apply to both standard and
high gain parts unless noted differently.

NE/SA592
SYMBOL

PARAMETER

tR

tpD

Bandwidth
Gain 11
Gain 22,4

UNIT

Rise time
Gain 11
Gain 22,4

VOUT= 1Vp_p

Propagation delay
Gain 11
Gain 22,4

VOUT = 1Vp_p

Gain select Pins G" and G, 8 connected together.
Gain select Pins G2A and G28 connected together.
All gain select pins open.
Applies to 10- and 14-pln versions only.

November 3, 1987

Typ

Max

40
90

NOTES:

1.
2.
3.
4.

SE592

TEST CONDITIONS
Min

BW

Ii
I

I

High gain part

offset voltage
1
24
33

i

4-47

Min

Typ

Max

40
90

MHz
MHz

10.5
4.5

12

10.5
4.5

10

ns
ns

7.5
6.0

10

7.5
6.0

10

ns
ns

I

I
I

III

Product Specification

Signetics Linear Products

Video Amplifier

NE/SA/SE592

TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Swing as
a Function of Frequency

Common-Mode Rejection Ratio
as a Function of Frequency

.
~ ,.
.

100

!-I

IO

"iii
z

~

50
40

g

30

~

20

8

1.

...
••

>

..

100.

1M

10M

~ ...

30

,.

'I!
II

~ ..,
0
~

\

.,.

•

100M

......
:.t _

08

0

•,

Vs;: ±.v

TA:: 2S"c
AL::: 1K

1.'
1.'

I ,.

~

l!:0

U

GAIN 2
VS:: tlY
TA;: 25"C

I

!

Pulse Response

.-.-n-r-r-r-n-r-r-rTnr-T......,..,.....,

1

FREQUENCY-Hz

.//

..

-.,

50 100

-

500 1000

-15

10

5

0

5

10

15

20

25

30

35

TIME-n.

FAEQUENCY-MH~

0P04440S

Differential Overdrive
Recovery Time
70

..
.

"

Vs =- f6Y
TA = 25°C

V

12

/

40

/

30

o0

......

10

~

08

VS:: flY

V

,.

Vs '"

06

,

1I

.
~ ..
10

~

~

0

TA=Ofll

.,.,

..,

-02

TA=25°C

Ifl 1

-r-

VTA'C700C

/

-02

-04- ,S

20 40 80 80 100 120 140 160 180 200
DIFFERENTIAL INPUT VOLTAGE-mY

GAIN 2
Vs::: ±6Y
Al:: 1kn

12

0

1

I

"

14

! ,

VS:: f3Y

i ..

,;'

~~

~

e

20

,.

I I ~:'~ :soC
I I "L"nU

14

GAIN 2

Pulse Response as a
Function of Temperature

Pulse Response as a
Function of Supply Voltage

- 10

5

0

5

10

15

20

25

30 35

15

10

5

0

TIME-n.

5

10

15

~

~

30

TIII£-ni

OP0447OS

Voltage Gain as a
Function of Temperature

".

14

"

Vs:: ±8V

1."

Voltage Gain as a
Function of Supply Voltage

Gain vs Frequency as a
Function of Temperature

I,
f",.

....
....
.... •

l~

'-4

,.

. ".."'-

20
30
40
TEMPERATUAE- 0 C

\
70

~ .,•• r- po. ,

1

5

10

sa

100

A"

ss"c

'"

A = 25"c
TA :::
125"C
500 1000

FREQUENCY-MHz

4-48

I .,

~

'.7

••

I)'

V

•• 3

-"
.

"

...oiI:- f0",

,

SUPPlY VOL TAGE- ty

........

November 3, 1987

1.1

~

\\

,.

.........

1.,..0

12

1.'

30

;:-.... r-...

13

~

40

!"'--.; ~

T.= 25"c

Vs= ilY

RL:: lkfl
GAIN 2

35

Product Specification

Signetics Linear Products

Video Amplifier

NE/SA/SE592

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain vs Frequency
as a Function of
Supply Voltage

.
i ,..
~
.
m

GAIN 2
TA = 2S"C

50

AL= 1kA

"\\

~

~

~ 10

R..,

~: s=

i

;;

-,. ,

5 - t8Y
t6Y

:t",..'000
t3Y

5

10

50 tOO

FAEQUENCY-MHz

Vs = ±6V

Supply Current as a
Function of Temperature
21

.

v~=

=25°C

Output Voltage and Current
Swing as a Function of
Supply Voltage

Supply Current as a
Function of Supply Voltage

.

±IV

TA

~.

r--. ......

1/

B

......

>

I

15

"-eo

..
10

=25°C

20

20

60

100

/

16

/

~:: 2t5~~

I ..

5

7'

10

Vs

.
V,

500 1k
00
LOAD AESI$TANCE_

November 3, 1987

u

.

5

10k

=

P"
50

60

10

80

GAIN 2

.. H-ttlH-+-Hi-++Hl-i: ~ ~~~

:t6Y

"H-ttlH-+-Hi-++HI-~·W~~~'~'~MF~~

/

10

'

.

"
/'"
V

II"

50

/c~

Input Noise Voltage
as a Function of
Source Resistance

/

2.0

~ ,..

~

~V

SUPPLY VOlTAGE_:r.y

GAIN 2

U

30

~

40

•

SUPPLY VOLTAGE- ty

Input Resistance
as a Function of
Temperature

70

~

~~
~~

V
f"'"

10

• 3

••
>t

20

12

=25°C

k'

30

V

140

TEUPEAATUHE_oC

TA

40

/
/

Output Voltage Swing
as a Function of
Load Resistance

$

TA

24

7

~

Voltage Gain as a
Function of RADJ (Figure 3)

Voltage Gain
Adjust Circuit

.

- 20

0

20

60

TEMPEAATUAE-oC

4-49

100

..

,

'~'~~~IO~~~,±OO~~~'~'-UUL~,~
SOUACE RESISTANCE-U

Signetics Linear Products

Product Specification

Video Amplifier

NE/SA/SE592

TEST CIRCUITS TA ~ 25°C, unless

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

otherwise specified.

Phase Shift as a
Function of Frequency

!'

e

Phase Shift as a
Function of Frequency

~

GAIN 2

~: ~ :s~~

-,

-50

~

'\\
\\

~

~

-10

"

f"'.,

:

en -15

i

\\

-300

0

,

2

• , •

3

5HI

•

7

FREQUENCY-MHz

-,50
10

100

1

02",F

\\

1000

FREQUENCY-MHz

-""

.
so

Voltage Gain as a
Function of Frequency
(All Gain Select Pins Open)

Voltage Gain as a
Function of Frequency
~: ~ ;s~~

Vs" :t6V

40

"l:: lKH

GAil

TA"'25°C
GAIN 3

30

"""

40
GAIN 2

20

10

100

FREQUENCY-MHz

November 3, 1987

........

1\\

20

510

\

-20

-as

~: ~ ;5~~

\\
\\
'\

-10

-30
-40
1000

-so

I'

,.....,
01

,

/

\
\

/

I'
1

1
10
FREQUENCY-MHz

4·50

'00

10

Signetics Linear Products

Product Specification

Video Amplifier

NE/SA/SE592

TYPICAL APPLICATIONS
r-----------------------~"---------------------__,

.,

v,

-,
NOTE:
Vo(s)

V,(s)

14 X 104

"'--Z(s) + 2re
14 X 104

"'--Z(s) + 32

Basic Configuration

.,

.,
o 2"F

TVo

AMPLITUDE'
FREQUENCY:

47 pFd

ReAD HEAD

-,

DIFFI!FU!NTIATOR/AMPlIFIEA

-,
ZEAO CROSSING DET£CTOA

T

NOTE:
For frequency F j «~21r(32)C
dV,
Vo~14 x 104V;r

Disc/Tape Phase-Modulated Readback Systems

November 3, 1987

4-51

Differentiation with High
Common-Mode Noise Rejection

Signetics Linear Products

Product Specification

NEjSAjSE592

Video Amplifier

FILTER NETWORKS
FILTER
TYPE

ZNElWORK

•

•

LOW PASS

c

~~

•

14 x 10

L

~

HIGH PASS

c

L

~f----<>

BAND PASS

L

~

Vo (s) TRANSFER
V, (s) FUNCTION

BAND REJECT

4

--L

[~

4[_0_]
0
0 J

1.4 x 10

+ l/RC

R

14 x 10'[
L
s2 + R/L s + lILC

4[

1.4Xl0
R

02

s2+lILC
]
+ l/LC + slRC

NOTES:
In the networks above, the A value used IS assumed to Include 2r e. or approxImately 32n
S""I(.)
w=2JTf

November 3, 1987

+lR/LJ

4-52

Signetics

AN141
Using the NEjSAjSE592
Video Amplifier
Application Note

Linear Products

VIDEO AMPLIFIER PRODUCTS
NE/SA/SE592 Video Amplifier
The 592 IS a two-stage differential output,
wide-band video amplifier with voltage gains
as high as 400 and bandwidths up to
120MHz.
Three basIc gain opllOns are provided. Fixed
gains of 400 and 100 result from shorting
together gain select pins G1A - G1B and
G2 A - G28, respectively. As shown by Figure
I, the emitter CirCUitS of the differenllal pair
return through independent current sources.
This topology allows no gain in the Input
stage if all gain select pins are left open.
Thus, the third gain option of tYing an external
resistance across the gain select pinS allows
the user to select any desired gain from 0 to
400V IV. The advantages of this configuration
will be covered In greater detail under the
filter application section.
Three factors should be pOinted out at this
time:

3. DIVide by the CIrcuit gain (assume 100).
ThiS refers the output offset to the input.
4. The maximum input resistor size IS:
Input Offset Voltage
Max Input Offset Current

(1)

vats) = 1.4 X 104
V,N(S)
Z(8) + 32

0.005V
5/lA
= 1.00kr!

Of paramount Importance dUring the design
of the NE592 device was bandWidth. In a
monolithic device, thiS precludes the use of
PNP transistors and standard level-shifting
techniques used In lower frequency devices.
Thus, Without the aid of level shifting, the
output common-mode voltage present on the
NE592 IS tYPically 2.9V. Most applications,
therefore, require capacitive coupling to the
load.
As mentioned earlier, the emitter CIrCUIt of the
NE592 Includes two current sources.

2. The CIrcuit 3dS bandwidths are a function
of and are Inversely proportional to the gain
settings.

Since the stage gain IS calculated by diViding
the collector load Impedance by the emitter
impedance, the high Impedance contributed
by the current sources causes the stage gain
to be zero with all gain select pins open. As
shown by the gain vs. frequency graph of
Figure 2, the overall gain at low frequencies is
a negative 48dS.

In applicallOns where the signal source is a
transformer or magnetic transducer, the input
bias current required by the 592 may be
passed directly through the source to ground.
Where capacitive coupling is to be used, the
base inputs must be returned to ground
through a resistor to provide a DC path for the
bias current.
Due to offset currents, the selection of the
Input bias resistors IS a compromise. To
reduce the loading on the source, the resIstors should be large, but to minimize the
output DC offset, they should be
small - Ideally Or!. Their maximum value IS
set by the maximum allowable output offset
and may be determined as follows:
1. Define the allowable output offset (assume
1.5V).
2. Subtract the maximum 592 output offset
(from the data sheet). ThiS gives the output
offset allowed as a function of Input offset
currents (1.5V - 1.0V = 0.5V).

December 1988

(2)

where Z(8) can be resistance or a reactive
Impedance. Table 2 summarizes the possible
conflgurallOns to produce low, high, and
bandpass filters. The emitter Impedance IS
made to vary as a function of frequency by
using capacitors or inductors to alter the
frequency response. Included also in Table 2
IS the gain calculation to determine the voltage gain as a function of frequency.

Filters

1. The gains specified are differential. Singleended gains are one-half the stated value.

3. The differential Input Impedance IS an Inverse function of the gain setting.

Any calculations of Impedance networks
across the emitters then must include thiS
quantity. The collector current level IS approxImately 2mA, causing the quantity of 2 re to
be approximately 32r!. Overall device gain is
thus given by

Higher frequencies cause higher gain due to
distributed paraSitic capacitive reactance.
ThiS reactance In the first stage emitter CIrCUIt
causes Increasing stage gain until at 10MHz
the gain IS OdS, or unity.
Referring to Figure 3, the Impedance seen
looking across the emitter structure Includes
small re of each transistor.

NOTE:
All resIstor values are

In

ohms

Figure 1. 592 Input Structure

Table 1_ Video Amplifier Comparison File
PARAMETER

NE/SA/SE592

Bandwidth (MHz)

120

120

Gain

0,100,400

10,100,400

R'N (k)

4-30

4-250

Vp_p (Vs)

4.0

40

4-53

733

Signetics Linear Products

Application Note

Using the NEjSA/SE592 Video Amplifier

AN141

Table 2. Filter Networks
VS' IV
TA.:/5 C

/

/

V

FILTER
TYPE

L

LOW
PASS

R

v\
/

Z NETWORK

~

Vo(s) TRANSFER
VI(S) FUNCTION

1.4 X 104

----

[s+lR/L]

L

AF03770S

\

\

R

C

~I

l,....---'"

0

HIGH
PASS

1.4X104

---R

[s+

AF037BOS

c
~~
AF03790S
R

Figure 2. Voltage Gain as a Function
of Frequency (All Gain Select
Pins Open)

.,
2"

L

~

BAND
PASS

~/RC]

4

1.4 X 10
---L

BAND
REJECT

[S2 + R/L: + 1/LC ]

1.4 X 104 [
s2+1!LC
]
R
s2 + 1/LC + s/RC

----

AF03750S

NOTES:

v,

In the networks above, the A value used IS assumed to mclude 2 re, or approximately 32n

s=,n
n=2nf

NOTE:
Vo(s) "'" 1 4 X 104
V 1 (s}

2(s)

+ 2re

14 X 104
Z(s)

+ 32

Figure 3. Basic Gain Configuration
for NE592. N14

Differentiation
With the addition of a capacitor across the
gain select terminals, the NE592 becomes a
differentiator. The primary advantage of using
the emitter circuit to accomplish dIfferentiation
is the retention of the high common mode
nOIse rejection. Disc file playback systems rely
heavoly upon this common-mode rejection for
proper operatIon. FIgure 4 shows a differential
amplifier confoguration with transfer function.

Disc File Decoding
In recovering data from dIsc or drum files,
several steps must be taken to precondition
the linear data. The NE592 video amplifier,
coupled wIth the BT20 bIdIrectIonal one-shot,
provides all the signal conditioning necessary
for phase-encoded data.
When data IS recorded on a disc, drum or tape
system, the readback will be a Gaussian
shaped pulse with the peak of the pulse
correspondIng to the actual recorded transiDecember 19BB

tlon point. This readback sIgnal is usually
5001lVp_P to 3mVp_p for oxide coated disc files
and 1 to 20mVp_p for nIckel-cobalt disc files. In
order to accurately reproduce the data stream
originally written on the dIsc memory, the time
of peak point of the Gaussian readback signal
must be determined.
The classical approach to peak tIme determl'
nation is to differentiate the input signal.
DifferentiatIon results In a voltage proportional
to the slope of the input signal. The zerocrossing point of the differentlator, therefore,
will occur when the input Signal IS at a peak.
Using a zero-crossing detector and one-shot,
therefore, results in pulses occurring at the
input peak points.
A circuit which prOVIdes the preconditioning
described above is shown in Figure 5. Readback data is applied directly to the input of the
first NE592. This amplifier functIons as a wldeband AC-coupled amplifier with a gain of 100.
The NE592 is excellent for this use because of
its high phase linearity, high gain and ability to
directly couple the unit wIth the readback
head. By direct coupling of readback head to
amplifier, no matched terminating resistors are
required and the excellent common-mode rejection ratio of the amplifier is preserved. DC
components are also rejected because the
NE592 has no gain at DC due to the capacItance across the gain select terminals.
The output of the first stage amplifier is routed
to a linear phase shift low-pass filter. The filter

4-54

is a sIngle-stage constant K folter, wIth a
characteristic impedance of 200n. Calculations for the filter are as follows:

L = 2'Y"",
where
R = characteristic Impedance (n)
C= 1,1"",
where

we = cut-off

frequency (radIans/sec)

.,
OZ .. F

T

v,

vo

0211F

-,

T

NOTES:

For frequency F1

Vo::1 4 X

< < 1/21T(S2)C

104C~

dT

AU resistor values are In ohms

Figure 4. Differential with High
Common-Mode Noise Rejection

Application Note

Signetics Linear Products

AN141

Using the NE/SA/SE592 Video Amplifier

The second NE592 is utilized as a low noise
differentlator I amplifier stage. The NE592 is
excellent in this application because it allows
differentiation with excellent common-mode
noise rejection.
The output of the differentiator/amplifler is
connected to the 8T20 bidirectional monostable unit to provide the proper pulses at the
zero-crossing points of the dlfferentiator.

The signal is fed to the signal Input of the
MC1496 and RC-coupled to the NE592. Unbalancing the carner Input of the MC1496
causes the signal to pass through unattenuated. Rectifying and filtering one of the NE592
outputs produces a DC signal which is proportional to the AC signal amplitude. After
filtering; this control signal is applied to the
MC1496 causing its gain to change.

The circuit in Figure 5 was tested with an
Input signal approximating that of a readback
signal. The results are shown In Figure 7.

Automatic Gain Control
The NE592 can also be connected in conjunction with a MC1496 balanced modulator
to form an excellent automatic gain control
system.
4mH

r---~-------------------------------1~------rn~-----1~------------o.5V
4mH

r---~---------------------------1-t------JYrr~----4---~----------o-5V

~O'~F

IOl~F

DIGITAL

8r20

OUTPUTS
CLR

200

43

Xl00AC
PRE AMPLIfiER

LINEAR PHASE

DIFFERENTIA TOR

BIDIRECTIONAL

LOW PASS FILTER

ONE-SHOT

NOTE:
AU resIstor values are In ohms

Figure 5. 5MHz Phase-Encoded Data Read Circuitry

.----.--------.--------.----------O+6V

lK

27K
10pF

2.7K

0.1 J.lF

~~~--------~

6r-.....--+~ 1--.-----'-1

51

MC1496

51

12t-------....
14

3.3K

10

lK

.1K

4.7K

56K

0.1

lK

L-----~----~-JV1~K~-e--------------_e________________________~--------~-6V
NOTE:
All reSIstor values are In ohms

Figure 6. Wide-band AGC Amplifier
December 1988

4-55

Signetics linear Products

Application Note

Using the NE/SA/SE592 Video Amplifier

I

IV \I V \. 'I
/I,

1 J"i1

V II

v

rv 'V \.

..,

...

,.,

~

~

I I I

v~

I

I

....

PRE-AMPUFIER OUTPUT
lOOmV/DIV.

DIFFERENTIATOR
2OOmV/DIV.

TIME BASE 2OOft./DlY.

~

J), jI

I

~ ~

[f [J ~
,~

[J

r"I

r

f

J~
I

PRE·AMP AND DlFFERENTIATOR
SUPER IMPOSED
BOTH 2OOmV/DIV.

-

TIME BASE 2OOnsfDIV.

f,

r f1

.1 J U ~
'It

I

,

I

I I I

II\..

f

,...

r f1

.
I JI
• I .I

I II U

DIFFERENTIATOR
2OOmV/DIV.
~

8T20 Q OUTPUT
2V/DIV.

TIME BASE 2OOna/DlV.

Figure 7. Test Results of Disc File Decoder Circuit

December 1988

4-56

AN141

MC1496/MC1596

Signetics

Balanced Modulator/
Demodulator
Product Specification
Linear Products

DESCRIPTION

FEATURES

The MC1496 is a monolithic doublebalanced modulator/demodulator designed for use where the output voltage
is a product of an input voltage (signal)
and a switched function (carrier). The
MC1596 will operate over the full military
temperature range of -55°C to + 125°C.
The MC1496 is intended for applications
within the range of O°C to + 70°C.

• Excellent carrier suppression
65dB typ @ O.5MHz
50dB typ @ 10MHz
• Adjustable gain and signal
handling
• Balanced inputs and outputs
• High common-mode rejectlon85dB typ

PIN CONFIGURATION
F. N Packages

SIQN:~~~T~~~

1

OAINADJUST 2
GAIN ADJUST 3

SIG::~~~~;

4

APPLICATIONS
• Suppressed carrier and amplitude
modulation
• Synchronous detection
• FM detection
• Phase detection
• Sampling
• Single sideband
• Frequency doubling

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

14-Pin Cerdip
14-Pin Plastic

ORDER CODE

+ 70°C

MC1496F

+ 70°C

MC1496N

14-Pin Cerdip

-55°C to + 125°C

MC1596F

14-Pin Plastic

-55°C to + 125°C

MC1596N

EQUIVALENT SCHEMATIC
VO(+)

CARRIER (-)

Vo(-)

o-.:.:'o'--__---l_---l_--'

INPUT( ... )
SIGNAL(-)
INPUT(+)

GAIN
ADJUST

BIAS

March 18, 1987

4-57

853-1201 88138

Product Specification

Signetics Linear Products

Balanced Modulator/Demodulator

MC1496/MC1596

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

Applied voltage

RATING

UNIT

30

V

Vs - VlO

Differential input signal

±5.0

V

V4-V,

Differential input signal

(5± Is Re)

V

V2- V "
V3- V4

Input signal

5.0

V

Is

Bias current

10

mA

1190
1420

mW
mW

Operating temperature range
MC1496
MC1596

o to +70
-55 to +125

°c
°c

Storage temperature range

-65 to + 150

°c

Maximum power dissipation, TA = 25°C
(still-air)'
F package
N package

Po

TA

TSTG
NOTE:

1. Derate above 25°C, at the following rates:

F package at 9.SmW re
N package at II.4mWre

DC ELECTRICAL CHARACTERISTICS Vcc = + 12Voc; Vee = -8.0Voc; 15 = 1.0mAoc; RL = 3.9kst; RE = 1.0kst; TA = 25°C,
unless otherwise specified.
MC1596
PARAMETER

SYMBOL

UNIT
Min

RIP
CIP

Single-ended input impedance
Parallel input resistance
Parallel input capacitance

Rop
COP

Single-ended output impedance
Parallel output resistance
Parallel output capacitance

MC1496

TEST CONDITIONS
Typ

Max

Min

Typ

Max

Signal port, f = 5.0MHz
200
2.0

200
2.0

kst
pF

40
5.0

40
5.0

kst
pF

f= 10MHz

Input bias current

ji.A

Iss

I, + 14
IsS =-2-

12

25

12

30

Isc

Is + 110
Isc=-2-

12

25

12

30

1105
Iloc

Input offset current
1105 = 1,-14
Iloc = Is -1'0

0.7
0.7

5.0
5.0

0.7
0.7

7.0
7.0

Tcllo
100

ji.A

Average temperature coefficient
of input offset current
Output offset current
16- 1'2

14

50

15

90

90

8.0

8.0

Vo
10+
10-

Power supply current
16 + 112
1,4

2.0
3.0

Po

DC power dissipation

33

March 18, 1987

2.0

2.0

Average temperature coefficient
of output offset current
Common-mode quiescent
output voltage (Pin 6 or Pin 12)

Tcloo

p.A

ji.A
nArC

80

p.A

nA/oC

Voc
mAoc

4-58

3.0
4.0

2.0
3.0
33

4.0
5.0
mW

Product Specification

Signetics Unear Products

Balanced Modulator/Demodulator

MC1496/MC1596

AC ELECTRICAL CHARACTERISTICS vcc = + 12oc; Vee =-9.0Voc; 15 = 1.0mAoc; RL = 3.9kn; RE = 1.0kn; TA = + 25°C,
unless otherwise specified.
MC1596
PARAMETER

SYMBOL

UNIT
Min

VeFT

Ves

BW3dB

Carrier feedthrough

Carrier suppressions

Transadmittance bandwidth
(Magnitude) (RL = 50n)

Avs

Signal gain

CMV
AcM

Common·mode input swing
Common·mode gain

DVOUT

Differential output voltage
swing capability

March 18, 1987

MC1496

TEST CONDITIONS

Ve = 60mVRM s sinewave and
offset adjusted to zero
fe = 1.0kHz
Ie = 10MHz
Ve = 300mVp.p squarewave:
Offset adjusted to zero
Ie = 1.0kHz
Offset not adjusted fc = 1.0kHz
Is = 10kHz, 300mVRMS sinewave
Ie = 500kHz, 60mVRMS sinewave
fe = 10MHz, 60mVRMS sinewave

Signal port, Is = 1.0kHz
Signal port, Is = 1.0kHz
IVel = 0.5Voe

4-59

Max

Min

40
140

50

Carrier input port,
Ve=60mVRMS
sinewave Is = 1.0kHz,
300mV RMS sinewave
Signal input port,
Vs = 300mVRMS
sinewave I Vc I = 0.5Voc
Vs = 100mVRMS; f = 1.0kHz
IVel = 0.5Voe

Typ

2.5

Typ

Max

40
140

I'VRMS

0.04

0.2

0.04

0.4

20

100

20

200

65
50

65
50

dB

300

300

MHz

80

80

MHz

3.5

VIV

5.0
-85

5.0
-85

Vp.p
dB

8.0

8.0

Vp.p

3.5

40

mVRMS

2.5

Signetics Linear Prod ucts

Product Specification

Balanced Modulator/Demodulator

MC1496/MC1596

TEST CIRCUITS
10}--.-_-.-_£,=____-I::

8IASC5

V_C'0~--~

__~____~
NOTE,
All reSistor values are In ohms

NOTE,

Figure 2_ Single-Supply Biasing

All reSistor values are In ohms

Figure 1_ Balanced Modulator Schematic

December 1988

4-61

853-1201 88138

I

~

Signetlcs Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596
an example. Thus, the Imtlal assumptions and
criteria are set forth:
1.

Output sWing greater than 4Vp.p

2

Positive and negative supplies of 6V are
available.

3.

Collector current IS 2mA It should be
noted here that the collector output current IS equal to the current set In the

AN189

-~-------------'------~-----------------,

I.5K

15K

current sources.

As a matter of convenience, the carner signal
ports are referenced to ground. If desired, the
modulation signal ports could be ground referenced With slight changes In the bias arrangement. With the carner Inputs at DC
ground, the qUiescent operating pOint of tne
outputs should be at one-half the total POSItive voltage or 3V for thiS case. Thus, a
collector load resistor IS selected which drops
3V at 2mA or 1 5k~1 A qUick check at thiS
pOint reveals that With these loads and current levels the peak-to-peak output sWing Will
be greater than 4V It remains to set the
current source level and proper biasing of the
signal ports.

...v

The voltage at Pin 5 IS expressed by
VSIAS

= VSE = 500 x

N01E.
All reSistor values are In ohms

Is

where Is IS the current set In the current
sources
For the example VSE IS lOOm V at room
temperature and the bias voltage at Pin 5
becomes 1 lV. Because of the cascade configuration, both the collectors of the current
sources and the collectors of the signal
transistors must have some voltage to operate properly. Hence, the remaining voltage of
the negative supply (-6V + 1 lV = -4.3V) IS
split between these transistors by biaSing the
signal transistor bases at -2 15V.

'JZ>

.ft

Countless other bias arrangements can be
usea With other power supply voltages. The
Important thing to remember IS that suffiCient
DC voltage IS applied to each bias pOint to
aVOid collector saturallOn over the expected
signal wings.

BALANCED MODULATOR
In the primary applicallOn of balanced modulation, generation of double Sideband sup-

+

.ft

f:+
k!

~

'JZ>

'JZ>

5

5

+
u

--- - - - - - - - - - - - ,

'JZ>

£

.ft
FREQUENCY ~--_

NOTES;
fc Carner Fundemental

fs Modulatmg Signal
fe± fs Fundemental Carner Sidebands
fe::! nfs Fundemental Carner Sideband HarmOniCs
ofe Carner Harmonics
nfe± nfs Carner HarmOniC Sidebands

Figure 4. Modulator Frequency Spectrum

December 1988

pressed carner modulation IS accomplished.
Due to the balance of both modulation and
carner Inpuls, the output, as menllOned, contains the sum and difference frequencies
while attenuating the fundamentals. Upper
and lower Sideband signals are the strongest
signals present With harmOniC Sidebands beIng of diminishing amplitudes as characterIzed by Figure 4.

'JZ>

I

.ft

~
I

Figure 3. Dual Supply Biasing

4-62

I

2>

;:

Application Note

Signetics Linear Products

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596
Gain of the 1496 is set by including emitter
degeneration resistance located as RE in
Figure 5. Degeneration also allows the maximum Signal level of the modulation to be
increased. In general, linear response defines
the maximum input signal as

AN189

,.

"

r.y.,'I.-~-1r----~Iv-------1'--o.12 \Ide

R,
39.
51

Vs " 15 • RE(Peak)

Ve
CARRIER
INPUT

and the gain is given by

01 .. F

o----jPO----------I

MC1496

V,

MODULATING
SIGNAL
INPUT

•

10
10'

(2)

t

This approximation is good for high levels of
carrier signals. Table 1 summarizes the gain
for different carrier signals.
As seen from Table I, the output spectrum
suffers an amplitude increase of undesired
sideband signals when either the modulation
or carrier signals are high. Indeed, the modulation level can be increased if RE is increased without significant consequence.
However, large carrier signals cause odd
harmonic sidebands (Figure 4) to Increase. At
the same time, due to imperfections of the
carrier waveforms and small imbalances of
the device, the second harmonic rejection will
be seriously degraded. Output filtering is often used with high carrier levels to remove all
but the desired sideband. The filter removes
unwanted signals while the high carrier level
guards against amplitude variations and maximizes gain. Broadband modulators, without
benefit of filters, are implemented using low
carrier and modulation Signals to maximize
linearity and minimize spurious sidebands.

AM MODULATOR
The basic current of Figure 5 allows no carrier
to be present in the output. By adding offset
to the carrier differential pairs, controlled
amounts of carrier appear at the output
whose amplitude becomes a function of the
modulation Signal or AM modulation. As
shown, the carrier null circuit is changed from
Figure 5 to have a wider range so that wider
control is achieved. All connections are
shown in Figure 6.

9

I---+--o-Vo

51

"

68'

v-8Vdc

NOTE:
All resistor values are In ohms

Figure 5. Double Sideband Suppressed Carrier Modulator

Table 1. Voltage Gain and Output Spectrum vs Input Signal
CARRIER INPUT
SIGNAL (Vel

OUTPUT SIGNAL
FREQUENCY(S)

APPROXIMATE
VOLTAGE GAIN
RLVe

Low-level DC

fM
2(RE +2rE) (KqT)

- RL
--

High-level DC

fM

R + 2re

RLVc(rms)
Low-level AC

fe± fM
2V2 ( :T )(RE + 2re)
0.637RL

fe ± fM' 3fe ± fM·
5fe ± fM···

---

High-level AC

RE + 2re

+12VOC

,.

"

...

3.'K

Vc

CARRIER INPUT
MODULATING

O.l,.F

o-----J

--L

r-'W"o--+---j

•

Me

1

Me

1596K
14961(

+v.

StGNAL INPUT Ys

,-,--,.-,4 ,0

AM DEMODULATION
As pointed out in Equation I, the output of the
balanced mixer is a cosine function of the
angle between signal and carrier inputs. Further, if the carrier input is driven hard enough
to provide a switching action, the output
becomes a function of the input amplitude.
Thus the output amplitude is maximum when
there is O· phase difference as shown in
Figure 7.

'.aK

v+
avDC
NOTE:
All resistor values are In ohms

Figure 6. AM Modulator

Amplifying and limiting of the AM carrier is
accomplished by IF gain block providing 55dB
December 1988

5•

4-63

- Yo

Application Note

Signetics Linear Products

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596

AN189

... ,2 V

,.

39K

19K

,.

,.

Me,.

~IL\

51

~90·

0

90·

PHASE ANGLE
-BV

NOTE,
All reSistor values are In ohms

Figure 7, AM Demodulator
of gain or higher with limiting of 400I'V. The
limited carner IS then applied to the detector
at the carner ports to provide the desired
switching function. The signal IS then demodulated by the synchronous AM demodulator
(1496) where the carrier frequency IS attenuated due to the balanced nature of the
device. Care must be taken not to overdrive
the signal Input so that distortion does not
appear In the recovered audio. MaXimum
converSion gain IS reached when the carrier

signals are In phase as indicated by the
phase-gain relationship drawn In Figure 7.
Output filtering will also be necessary to
remove high frequency sum components of
the carner from the audiO signal.

NOTE,
All resistor values are In ohms

Figure 8. Phase Comparator

PHASE DETECTOR
The versatility of the balanced modulator or
multiplier also allows the device to be used as
a phase detector. As mentioned, the output of
the detector contains a term related to the
cosine of the phase angle. Two signals of
equal frequency are applied to the Inputs as
per Figure 8. The frequencies are multiplied
together producing the sum and difference
frequencies. Equal frequencies cause the
difference component to become DC while
the undeSired sum component is filtered out.

December 1988

The DC component is related to the phase
angle by the graph of Figure 9. At 90· the
cosine becomes zero, while being at maxImum positive or maximum negative at O· and
180·, respectively.
The advantage of using the balanced modulator over other types of phase comparators is
the excellent linearity of converSion. This
configuration also provides a converSion gain
rather than a loss for greater resolution. Used
in conjunction with a phase-locked loop, for

4-64

instance, the balanced modulator provides a
very low distortion FM demodulator.

FREQUENCY DOUBLER
Very Similar to the phase detector of Figure 8,
a frequency doubler schematic is shown in
Figure 10. Departure from Figure 8 is primarily
the removal of the low-pass filter. The output
then contains the sum component which is
twice the frequency of the input, since both
Input signals are the same frequency.

I:
Signetics Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596

-P .. so'
fjI-o'
t;·'80'

HfJ ffff

=
=

AN189

OVDCAV£RAG£

"~&~Ft-=-----;
"VOCAVEFlAG£
1

-VDCAVERAGE

...Me'.,'"

....."

11SmV/....'

i"

Figure 9. Phase Detector ± Voltages

..

voc

NOTE:
All resistor values are In ohms

Figure 10. Low Frequency Doubler

December 1988

4-65

I

Signetics

NEjSA602
Double-Balanced Mixer and
Oscillator
Product Specification

Linear Products
DESCRIPTION

FEATURES

The SAlNE602 is a low-power VHF
monolithic double-balanced mixer with
input amplifier, on-board oscillator, and
voltage regulator. It is intended for high
performance, low power communication
systems. The guaranteed parameters of
the SA602 make this device particularly
well suited for cellular radio applications.
The mixer is a "Gilbert cell" multiplier
configuration which typically provides
l8dS of gain at 45MHz. The oscillator
will operate to 200M Hz. It can be configured as a crystal oscillator, a tuned tank
oscillator, or a buffer for an external L.O.
The noise figure at 45MHz is typically
less than 5dS. The gain, intercept performance, low-power and noise characteristics make the SAlNE602 a superior
choice for high-performance battery operated equipment. It is available in an 8lead dual in-line plastic package and an
8-lead SO (surface-mount miniature
package).

• Low current consumption: 2.4mA
typical
• Excellent noise figure: < 5.0dB
typical at 45MHz
• High operating frequency
• Excellent gain, intercept and
sensitivity
• Low external parts count;
suitable for crystal/ ceramic filters
• SA602 meets cellular radio
specifications

AD.

PIN CONFIGURATION

D, FE, N Packages

INPUT

INPUT B

Vee

2

7

OSCILLATOR

GROUND

J

6

OSCILLATOR

OUTPUT A

4

5

OUTPUT 8

TOP VIEW

APPLICATIONS
•
•
•
•
•
•

Cellular radio mixer/oscillator
Portable radio
VHF transceivers
RF data links
HF/VHF frequency conversion
Instrumentation frequency
conversion

• Broadband LANs

BLOCK DIAGRAM

November 9, 1987

4-66

853-0390 91374

Product Specification

Signetlcs Unear Products

NE/SA602

Double-Balanced Mixer and Oscillator

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic DIP

o to +70·C

NE602N

8-Pin Plasbc SO

o to +70·C

NE602D

8-Pin Cerdip

o to +70·C

NE602FE
SA602N

DESCRIPTION

8-Pin Plastic DIP

-40·C to + 85·C

B-Pin Plastic SO

-40·C to + B5·C

SA602D

8-Pin Cerdip

-40·C to + 85·C

SA602FE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

PARAMETER

UNIT

9

V

Storage temperature

-65 to +150

·C

Operating ambient temperature range
NE602
SA602

o to +70
-40 to +85

·C
·C

Vee

Maximum operating voltage

TSTG
TA

AC/DC ELECTRICAL CHARACTERISTICS

TA = 25·C, Vee = 6V, Figure 1
LIMITS

SYMBOL

TEST CONDITIONS

PARAMETER

Min
Vee

Typ

4.5

Power supply voltage range

2.4

DC current drain

UNIT
Max
8.0

V

2.8

rnA

fiN

Input signal frequency

500

MHz

fose

Oscillator frequency

200

MHz

Noise figured at 45MHz
Third-order intercept point

RFIN

= -45dBm:

f, = 45.0
f2 = 45.06

Conversion gain at 45MHz

14

RIN

RF input resistance

1.5

CIN

RF input capacitance

5.0

6.0

dB

-15

-17

dBm

18
3

(Pin 4 or 5)

MIXer output resistance

dB
kO

1.5

3.5

pF
kO

DESCRIPTION OF OPERATION
0.5 to 1.3,,"

Vee

q
150pF

NE602

1.5
to
44.2~

t

120pF

TC02701S

Figure 1. Test Configuration
November 9, 1987

4-67

The NE/SA602 is a Gilbert cell, an oscillatorl
buffer, and a temperature compensated bias
network as shown In the equivalent circuit.
The Gilbert cell is a differential amplifier (Pins
1 and 2) which drives a balanced switching
cell. The differential input stage provides gain
and determines the nOise figure and signal
handling performance of the system.
The NE/SA602 is deSigned for optimum low
power performance. When used With the
SA604 as a 45MHz cellular radio 2nd IF and
demodulator, the SA602 IS capable of receiving -119dBm signals With a 12dB SIN ratio.
Third-order intercept is typically -15dBm
(that's approXImately + 5dBm output intercept
because of the RF gain). The system designer must be cognizant of thiS large signal
limitation. When designing LANs or other
closed systems where transmiSSion levels are
high, and small-signal or signal-to-noise
issues not critical, the input to the NE602
should be appropriately scaled.

Signetics Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

Besides excellent low power performance
well into VHF, the NE/SA602 is deSigned to
be fleXible. The input, output, and oscillator
ports can support a variety of configurations
provided the designer understands certain
constraints, which will be explained here.
The RF inputs (Pins 1 and 2) are biased
internally. They are symmetrical. The equivalent AC input Impedence is approximately
1.5k II 3pF through 50MHz. Pins 1 and 2 can
be used interchangeably, but they should not
be DC biased externally. Figure 3 shows
three typical input configurations.

NE/SA602

The mixer outpu1s (Pins 4 and 5) are also
Internally biased. Each outpu1 is connected to
the internal positive supply by a 1.5kn resIstor. ThiS permits direct output termination yet
allows for balanced output as well. Figure 4
shows three single ended output configurations and a balanced output.
The OSCillator is capable of sustaining oscillation beyond 200MHz in crystal or tuned tank
configurations. The upper limit of operation is
determined by tank "0" and required drive
levels. The higher the "0" of the tank or the
smaller the required drive, the higher the

permissible OSCillation frequency. If the required L.O. is beyond oscillation limits, or the
system calls for an external L.O., the external
signal can be injected at Pin 6 through a DC
blocking capacitor. External L.O. should be at
least 200mVp_p.
Figure 5 shows several proven oscillator
circuits. Figure 5a is appropriate for cellular
radiO. As shown, an overtone mode of operation is utilized. Capacitor C3 and inductor L 1
suppress oscillation at the crystal fundamental frequency. In the fundamental mode, the
suppression network is omitted.
Figure 6 shows a Colpitts varacter tuned tank
oscillator suitable for syntheSizer-controlled
applications. It IS Important to buffer the
output of this cirCUit to assure that SWitching
spikes from the first counter or prescaler do
not end up in the oscillator spectrum. The
dual-gate MOSFET provides optimum isolation wrth low current. The FET offers good
Isolation, simplicity, and low current, while the
bipolar transistors provide the simple solution
for non-crrtlcal applications. The resistive diVider in the emitter-follower CirCUit should be
chosen to provide the minimum input signal
which Will assure correct system operation.
When operated above 100MHz, the oscillator
may not start if the 0 of the tank is too low. A
22kn resistor from Pin 7 to ground Will
increase the DC bias current of the OSCillator
transistor. This improves the AC operating
characteristic of the transistor and should
help the oscillator to start. 22kn will not upset
the other DC biasing internal to the device,
but smaller resistance values should be
avoided.

TC02030S

Figure 2. Equivalent Circuit

a. Single-Ended Tuned Input

b. Balanced Input (For Attenuation
of Second-Order Products)
Figure 3. Input Configuration

November 9, 1987

4-68

c. Single-Ended Untuned Input

-----~~~~-

Signetics Unear Products

Product Specification

NE/SA602

Double-Balanced Mixer and Oscillator

........

-

OR I!QUIVALENT
NellI

a. Single-Ended Ceramic Filter

FILTER UL38780 OR eQUIVALENT

*er MATCHES 3.5M TO NEXT STAGE

b. Single-Ended Crystal Riter

-

•

NEIIII

4

c. Single-Ended 1FT

d. Balanced Output
Figure 4. Output Configuration

NEII02

a. Colpitts Crystal Oscillator
(Overtone Mode)

-

NEII02

b. Colpitts LIC Tank Oscillator

c. Hartley LIC Tank Oscillator

Figure 5. OSCillator Circuits

November 9. 1987

4-69

-----~~-----

-~~~~-

Signetlcs Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

NEjSA602

5.5.uH

t--~--P---·~~FFER

5

~------...

1 ..

l000pF}?t:--r--o DC CONTROL VOLTAGE
l000pF
FROM SYNTHESIZER

-:- *

O.06.H

t

..z:s.. MV2105
OR EOUIVALENT
TCOZ1SOS

lO.OlpF
lOOK

2K

3SKI26

2pF

~~--4---~~~~~
o.OlpF

lOOK
lOOK

Figure 6. Colpitts Oscillator Suitable for Synthesizer Applications and Typical Buffers

"l,

0.510 1.30"

44.545 MHz
THIRO OVERTONE CAYST AL

Vee

SA602

07pF
INPUT

r--'---==-

~

~t 0.20110 0.213,,"

~100nf
Figure 7. Typical Application for Cellular Radio

November 9, 1987

4-70

Product Specification

Signetics Linear Products

Double-Balanced Mixer and Oscillator

NE/SA602

-14.5

-10

+10

-11

I

-12

...
:>

E

-10

!

S -20
i

Ii:w

0

U

II:

...w~

-30

-40

-so

-1'
-1'

e

-12

12.5

12.5 -

- ~13.S

r--

~

5u -16.5

~

-15

-15.5

..

-17.5

I

!;

-1.

~

-11

-18.5

-18

-19.0

•

5

•

7
Vcc(VOLTS}

8

•

-19.5

10

I

/

v

V

I
40

40

80

120

TEMPERATURE (OC)

OPO,S,os

Figure 8. NE/SA602 Third-Order
Intermod and ldB Compression
Point Performance

Figure 9. Input Third-Order
Intercept Point vs Vee

Figure 10. Third-Order Intercept
Point vs Temperature

22,..---.....,..---,..-----,

+80
TEMPERATURE (Oc)

Figure 11

November 9, 1987

~4O~------~------~+~4O~----~+~80

~4O~~-----70-------+~4O~-----+~80'

TEMPERATURE (0C)

TEMPERATURE COC)

Figure 12

Figure 13

4-71

Signetics

AN1981
New Low Power Single
Sideband Circuits
Application Note

Linear Products

by Robert J. Zavrel Jr.

INTRODUCTION
Several new integrated circuits now permit
RF designers to resurrect old techniques of
single-sideband generation and detection.
The high cost of multi-pole crystal filters limits
the use of the SSB mode to the most
demanding applications, yet the advantages
of SSB over full-carrier AM and FM are welldocumented (Ref 1 & 2). The use of multipole filters can now be circumvented by
reviving some older techniques without sacrificing performance. This has been made
possible by the availability of some new RF
and digital integrated circuits.

CARRIER

LOWER
SIDEBAND

9.999MHz

UPPER
SIDEBAND

10.000MHz

tD.OO1MHz

Figure 1. Frequency Domain Display of
a 10MHz Carrier AM Modulated by a
1kHz Tone (Spectrum Analyzer Display)

DESCRIPTION
Figure 1 shows the frequency spectrum of a
1OM Hz full-carrier double-sideband AM signal
using a 1kHz modulating tone. This wellknown type of signal is used by standard AM
broadcast radio stations. FUll-carner AM's
advantage is that envelope detection can be
used in the receiver. Envelope detection is a
simple and economical technique because it
simplifies receiver circuitry. Figure 2 shows
the time domain "envelope" of the same AM
signal.
The 1kHz tone example of Figures 1 and 2
serves as a simple illustration of an AM
signal. Typically, the sidebands contain complex waveforms for vOice or data communications. In the full-carrier double Sideband mode
(AM), all the modulation information is contained in both sidebands, while the carrier
"rides along" without contributing to the
transfer of intelligence. Only one sideband
without the carrier is needed to effectively
transmit the modulation information. This
mode is called "Single-sideband suppressed
carrier". Because of its reduced bandwidth, it
has the advantages of improved spectrum
utilization, better signal-to-nolse ratios at low
signal levels, and improved transmitter efficiency when compared with either FM or fullcarrier AM. A finite frequency allocation using
SSB can support three times the number of
channels when compared with comparable
FM or AM full-carner systems.
There are three basic methods of slnglesideband generation. All three use a balanced
modulator to produce a double-sideband suppressed carrier Signal. The undesired sideband is then removed by phase and amplitude nulling (the phasing method), high Q
multi-pole filters (the filter method), or a
December 1988

10MHz CARRIER

Figure 2. Time Domain Display of the
Same Signal Shown in Figure 1.
(Oscilloscope Display)
"third" method which is a derivation of the
phasing technique called here the "Weaver"
method for the apparent inventor. The reciprocal of the generator functions is employed
to produce sideband detectors. Generators
start with audio and produce the SSB signal;
detectors receive the SSB signal and reproduce the audio. Since the sideband Signal is
typically produced at radio frequencies, it can
be amplified and applied to an antenna or
used as a subcarner.
Reproduction of the audio signal in a fullcarrier AM receiver is simplified because the
carrier is present. The signal envelope, which
contains the carrier and the sidebands, is
applied to a non-linear device (typically a
diode). The effect of envelope detection is to
multiply the sideband signal by the carrier;
this results in the recovery of the audio
waveform. The mathematical baSIS for this
process can be understood by studying trigonometric identities.
Since the carner is not present In the received
SSB signal, the receiver must provide it for
proper audiO detection. This Signal from the
local oscillator (LO) is applied to a mixer
(multiplier) together with the SSB signal and
detection occurs. This technique is called

4-72

product detection and IS necessary in all SSB
methods. A major problem in SSB receivers is
the ability to maintain accurate LO frequencies to prevent spectral shifting of the audio
signal. Errors in this frequency will result in a
"Donald Duck" sound which can render the
signal unintelligible for large frequency errors.

Theory of Single-Sideband
Detection
Figures 3 through 8 illustrate the three methods of SSB generation and detection. Since
they are reciprocal operations, the circuitry for
generation and detection is similar with all
three methods. Duplication of critical circuitry
is easy to accomplish in transceiver applications by using appropriate switching circuits.
Figures 3 and 4 show the generation and
detection techniques employed in the filter
method. In the generator a double sideband
signal is produced while the carrier is eliminated with the balanced modulator. Then the
undesired sideband is removed with a high Q
crystal bandpass filter. A transmit mixer is
usually employed to convert the SSB signal to
the desired output frequency. The detection
scheme is the reciprocal. A receive mixer is
used to convert the selected input frequency
to the IF frequency, where the filter removes
the undesired SSB response. Then the Signal
is demodulated in the product detector. A
major drawback to the filter method is the fact
that the filter is fixed-tuned to one frequency.
This necessitates the receive and transmit
mixers for multi-frequency operation.
Figures 5 and 6 show block diagrams of a
generator and demodulator which use the
phase method. Figure 6 also includes a
mathematical model. The input signal
(Cos(Xt» is fed in-phase to two RF mixers
where "X" is the frequency of the input
signal. The other inputs to the mixers are fed
from a local oscillator (LO) in quadrature
(Cos(Yt) and Sin(Yt», where "Y" is the frequency of the LO signal. By differentiating the
output of one of the mixers and then summing
with the other, a Single sideband response is
obtained. Switching the mixer output that is
differentiated will change the selected sideband, upper (USB) or lower (LSB). In most
cases the mixer outputs will be the audio
passband (300 to 3000Hz). Differentiating the
passband involves a 90 degree phase shift
over more than three octaves. This is the
most difficult aspect of using the phasing
method for voice band SSB.

Application Note

Signetics Linear Products

New Low Power Single Sideband Circuits

AN1981

DOUBLE SIDEBAND
SUPPRESSED CARRIERSINGLE SIDEBAND

1

SUPPRESSED CARRIER

+

AUDfO

INPUT

BALANCED
MODULATOR

MOOULATOR

TRANSMIT

LO

LO

Figure 3. Filter Method SSB Generator

PRODUCT

1ST MIXER

DETECTOR

AUDIO
OUTPUT

RFSSB
INPUT

For vOice systems, difficulty of maintaining
accurate broadband phase shift IS eliminated
by the technique used In Figures 7 and 8. The
"Weaver" method IS Similar to the phaSing
method because both reqUire two quadrature
steps in the signal chain. The difference
between the two methods IS that the Weaver
method uses a low frequency (1.8kHz) sub·
carner in quadrature rather than the broad·
band 90 degree audio phase shift. The desired sideband IS thus "folded over" the
1.8kHz subcarrier and ItS energy appears
between 0 and 15kHz. The undesired sideband appears 600Hz farther away between
2.1 and 4.8kHz. Consequently, sideband rejection is determined by a low-pass filter
rather than by phase and amplitude balance .
A very steep low-pass response In the Weaver method is eaSier to achieve than the very
accurate phase and amplitude balance needed In the phasing method. Therefore, better
sideband rejecllOn is pOSSible With the Weaver method than with the phaSing method.

Quadrature Dual Mixer Circuits
RECEIVE

PRODUCT

LO

DETECTOR
LO

Figure 4. Filter Method SSB Detector

CLOCK
SIN("Y')

RF

SSB
OUTPUT

Figure 5. Phasing Method Generator

SIN(yI)

UPPER SiDEBAND
AUDIO OUTPUT

-2 COS{x+y)t

RFSSB
INPUT

2SIN(xt)

-COS(x+Y)I- CDS(x-y)'

90" PHASE SHIFTER

(DIFFERENTIAlOR)
COS (")

Figure 6. Phasing Method Detector with Simplified Mathematical Model

December 1988

4-73

One of the two cntical stages In the phasing
method and both cntical stages In the Weaver
method reqUire quadrature dual mixer CirCUitS.
Figures 9 and 10 show two methods of
obtaining quadrature LO signals for dual mixer applications. Other methods ex.st for producing quadrature LO Signals, particularly use
of passive LC Circuits. LC Circuits will not
maintain a quadrature phase relationship
when the operating frequency is changed.
The two Illustrated Circuits are Inherently
broad-banded; therefore, they are far more
flexible and do not require adjustment. These
cirCUits are very useful for SSB CirCUitS, but
also can be applied to FSK, PSK, and QPSK
digital communications systems.
The NE602 is a low power, senSItive, active,
double-balanced mixer which shows excellent phase characteristics up to 200M Hz. ThiS
makes it an Ideal candidate for thiS and many
other applications.
The cirCUit In Figure 9 uses a dlvide-by-four
dual flip-flop that generates all four quadratures. Most of the popular dual fhp-flops can
be used in different situallOns. The HEF4013
CMOS deVice uses very little power and can
maintain excellent phase integnty at clock
rates up to several megahertz. Consequently,
the HEF4013 can be used With the ubiqUitous
455kHz intermediate frequency With excellent
power economy. For higher clock rates (up to
120MHz for up to 30MHz operation), the fast
TTL 74F7 4 is a good chOice. It has been
tested to 30MHz operating frequencies With
good results (> 30 dB SSB rejection). At
lower frequencies (5MHz) Sideband rejecllon
increases to nearly 40dB With the CirCUitS
shown. The ultimate low frequency rejection
IS mainly a function of the audio phase shifter.

•

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

_B.

AN1981

Better performance is possible by empioying
higher lolerance resistors and capacitors.

RFLO

7.2kHz

7.2kHzFROM

LO

RECEIveD SIGNAL

1.8kHz
L.R FlLTER
lD016ol0S

Figure 7. Weaver Method Generator

Figure 11 shows a circuit that is effective for
driving the 74F74, or other TTL gates, with a
signal generator or analog LO. The NE5205
provides about 20dB gain with 50n input and
output impedances from DC to 450MHz. Minimum external components are required. The
1kn resistor is about optimum for "pulling"
the input voltage down near the logic threshold. A 50n output level of OdBm can be
used to drive the NE5205 and 74F74 to
100MHz. Two NE5205s can be cascaded for
even more sensitivity while maintaining extremely wide bandwidth. An advantage of
using digital sources for the LO is that lowfrequency power supply ripple will not cause
hum in the receiver front end. This is a
common problem in direct conversion designs.

RFLO

OFFSET 12kHz
FROM RECEIVED SIGNAL

7.2kHz LO

1._
L.P-FILTER

Figure 8. Weaver Method Detector

Figure 12 shows the interface circuitry between the 74F74 and the NE602 LO ports.
The total resistance reflects conservative current drain from the 74F74 outputs, while the
tap on the voltage divider is optimized for
proper NE602 operation. The low signal
source impedance further helps maintain
phase accuracy, and the isolation capacitor is
miniature ceramic for DC isolation.

~=o

.. OUTPUT

FREQUENCY

Audio Amplifiers and Switching

Figure 9. Dual Flip-Flop Quadrature Synthesis

r-----------------Niiii21
I
I

iI ......

..... - _______ -,

I

I

I

I

1

I

I
I
I
I

D£T&CTOR.J

I

~

C08...

Figure 10. PLL Quadrature Synthesis

December 1988

The circuit in Figure 10 shows another technique for producing a broadband quadrature
phase shift for the LO. The advantage of this
circuit over the flip-flops is that the clock
frequency is identical to the operating frequency; however, phase accuracy is more
difficult to achieve. A PLL will maintain a
quadrature phase relationship when the loop
is closed and the VCO voltage is zero. The
DC amplifier will help the accuracy of the
quadrature condition by presenting gain to
the VCO control circuit. The other problem
that can arise is that PLL circuits tend to be
noisy. Sideband noise is troublesome in both
SSB and FM systems, but SSB is less sensitive to phase noise problems in the LO.

4-74

USing active mixers (NE602) in these types of
circuits gives conversion gain, typically 1adS.
More traditional applications use passive diode ring mixers which yield conversion loss,
typically 7dB. Consequently, the detected
audio level will be about 25dB higher when
using the NE602. This fact can greatly reduce
the first audio stage noise and gain requirements and virtually eliminate the "microphonic" effect common to direct conversion receivers. Traditional direct conversion receivers use passive audio LC filters at the mixer
output and low noise, discrete JFETs or
bipolars in the first stages. The very high
audio sensitivity required by these amplifiers
makes them respond to mechanical vibration-thus the "microphonics" result. The

Signetics Linear Products

Application Note

AN1981

New Low Power Single Sideband Circuits

.-----------------------------------------------------------,

soo

:O~~
..8m
0-120MHz

1

1

O'1,11~O'j.lF

CKl

I---r-+-~ CK2

-=

,.

NES205

-

74F74

Figure 11. FAST TTL Driver from Analog Signal Source Using NE5205

,...
74F74

0'
510n

D.'

~
5100

f--------l
3O 70dB sideband rejecllon.

Conclusions
Single Sideband offers many advantages over
FM and full-carrier double-sideband modulalion These advantages Include: more efficient spectrum use, better signal-to-noise
rallos at low signal levels, and better transmitter effiCiency. Many of the disadvantages can
now be overcome by using old techniques
and new state-of-the-art integrated circuits.
Effective and inexpensive circuits can use
direct conversion techniques with good results. 35dB sideband rejection with less than
1JlV senSitIVIty IS obtained with the NE602
CirCUitS. 70dB sideband rejection and superior
senSitiVity are obtained by using phaSing-filter
techniques. Either the phasing or Weaver
methods can be used in either the direct
converSion or IF section applications. The
filter and phase-filter methods can be used in
only the IF application.

Application Note

Signetics Linear Products

New low Power Single Sideband Circuits

HEF4053

2XNE5S14

AN1981

BROADBAND PHASE SHIFT NETWORK
FIGURE 15 CIRCUIT

NE5534

DETECTOR

NE5534

DETECTOR
AMPLITUDE

BAlANCE POTS
LSB

10K
9.5K

SSB
AUDIO

THE THREE

SWITCH CONTROL

OUTPUT

PINS ARE TIED
TOGETHER FOR

ONE BIT
SIDEBAND SELECT
FUNCTION

Figure 14. Sideband Select SWitching Function

10k!!

101<0

10k!)

1OkO

10k!)

10k!)

ANALOG . - - - - . . . ,
SWITCH
BUFFERS
INPUT
A

INPUT
B

Figure 15

December 1988

4-77

•

Signetics Linear Products

Application Note

New low Power Single Sideband Circuits

Ci.OCK

VOICE
INPUT

I

TAPPED
DELAY LINE
NSAMPLES

I

R,

AN1981

RETICONTA 0 ....

......

R2

RN-2
:: R3

R3

RN-1
:: R2

RN=R1

T

VOIC E9O'

WEIGHTED SUM

FIXED DELAY
N/2SAMPLES

VOIC

REFERENCE
CHANNEL

RETICON TA0-32

Figure 16. Broadband 90 0 Audio Phase Shift Technique Using Tapped Delay Line (Reference 4)

DIRECT
CONVERSION
PHASINGSSB
RECEIVER

AUDIO FILTERS,
S-METERAND

AGC

SYNTHESIZED
LO

Receivers built usrng this technique can exhibit excellent charactenstrcs without resorting to expensive multi-pole
filters or an IF Amplifier cham

Figure 17. Complete Phasing-Filter Receiver

December 1988

4-78

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

AN1981

s_
LO

CLOCK

NE602

ssa
RFINPUT

DUAL
FLlP·FLOP
74F74

r-----------------~~

'--t__________________.!!18O'!!!:..j

450pF

HEF 4013

DUAL

:::.;:~c:

CIRCUIT

72kHz CLOCK
OSCILLATOR

ANO- 512
CIRCUIT

Figure 18. Weaver Method Receiver Concept Example For .;; 30MHz Operation

REFERENCES
1.

Spectrum ScarcIty Drrves Land-mobIle
Technology, G. Stone, M,crowaves and
RF, May, 1983.

2.

SSB Technology Fights its Way into the
Land-mobile Market, B. Manz, MIcrowaves and RF, Aug., 1983.

3.

4.

A ThIrd Method of GeneratIon and Detection of Single-SIdeband SIgnals, D. Weaver, Proceedmgs of the IRE, 1956.
Delay Lmes Help Generate Quadrature
VOIce for SSB, Joseph A. Webb and M.
W. Kelly, Electronics, Apnl 13, 1978.

December 1988

5.

6.

7.
8.

9.

A Low Power Dlfect Conversion SIdeband Receiver, Robert J. Zavrel Jr., ICCE
DIgest of Techmcal Papers, June, 1985.
Electromc FIlter DesIgn Handbook, Arthur
B. Williams, McGraw· HIli, 1981.
SolId State RadIO Engmeerrng, Herbert L
Krauss, et aI, Wiley, 1980
ACSB·An OvervIew of Amplttude Com·
pandored SIdeband Technology, James
Eagleson. Proceedmgs of RF Technology Expo 1985.
The ARRL Handbook for the RadIO Ama·
teur, Amencan RadiO Relay League,
1985.

4-79

10. Desigmng WIth the SAlNE602 (AN198),
Signetics Corp, Robert J. Zavrel Jr.,
1985.

11 RF IC's Thrrve on Meager Battery·Supply
DIet, Donald Anderson, Robert J. Zavrel
Jr., EON, May 16, 1985.
12 AudIO IC Op Amp Appltcatlons, Walter
Jung, Sams Publications, 1981
13 2 Meter Transmitter Uses Weaver ModulatIon, Norm Bernstein, Ham RadIO, July,
1985.

Signetics

AN1982
Applying the Oscillator of the
NE602 in Low Power Mixer
Applications

Linear Products

Application Note

by Donald Anderson

most commonly used configurations In their
most basIc form

rent, 200MHz oscillation can be achieved with
high Q and appropriate feedback.

INTRODUCTION

In each case the Q of the tank will affect the
upper frequency limits of oscillation: the
higher the Q the higher the frequency. The
NE602 IS fabricated w~h a 6GHz process, but
the emitter resistor from Pin 7 to ground IS
nominally 20k. With O.2SmA typical bias cur-

The feedback, of course, depends on the Q
of the tank. It is generally accepted that a
minimum amount of feedback should be
used, so even If the choice is entirely empirical, a good trade-off between starting charactenstlcs, distortion, and frequency stability
can be quickly determined.

For the designer of low power RF systems,
the Signetics NE602 mixer/oscillator provides mixer operation beyond SOOMHz, a
versatile oscillator capable of operation to
200MHz, and conversion gain, with only
2 SmA total current consumption With a
proper understanding of the oscillator design
considerations, the NE602 can be put to work
qUickly In many applications.

DESCRIPTION
Figure 1 shows the equivalent CirCUit of the
device. The chip IS actually three subsystems:
A Gilbert cell mixer (which provides differential Input gain), a buffered emitter follower
OSCillator, and RF current and voltage regulation Complete Integration of the DC bias
permits Simple and compact application. The
SimpliCity of the OSCillator permits many configurations
While the OSCillator IS Simple, OSCillator design
Isn't This article will not address the ngors of
OSCillator design, but some practical gUidelines will permit the designer to accomplish
good performance with minimum difficulty.

III

Either crystal or LC tank CirCUitry can be
employed effectively. Figure 2 shows the four

GND

Figure 1

':'

':'

a. Fundamental
Crystal

[

c. Colpitis
L/C Tank

b. Overtone
Crystal
Figure 2

December 1988

I

4-80

':'

IT
d. Hartley
L/C Tank

':'

Signetics linear Products

Application Note

Applying the Oscillator of the NE602
in Low Power Mixer Applications

AN1982

Crystal Circuit Considerations
Crystal oscillators are relatively easy to Implement since crystals exhibit higher Q' s than LC
tanks. Figure 3 shows a complete Implementation of the SA602 (extended temperature
version) for cellular radiO With a 45MHz first IF
and 455kHz second IF.

0.5 to 1.3~H

THIRD OVERTONE CRYSTAL

vee

The crystal IS a third overtone parallel mode
with 5pF of shunt capacitance and a trap to
suppress the fundamental.
NE602

LC Tank Circuits
LC tanks present a little greater challenge for
the deSigner. If the Q IS too low, the oscillator
won't start. A trick which will help If all else
fails is to shunt Pin 7 to ground With a 22k
resistor. In actual applications thiS has been
effective to 200MHz with high Q ceramic
capacitors and a tank inductor of 0.08"H and
a Q of 90. Smaller resistor value will upset DC
bias because of Inadequate base bias at the
input of the oscillator. An external bias resIstor could be added from Vec to Pin 6, but thiS
Will Introduce power supply nOise to the
frequency spectrum.
The Hartley configuration (Figure 20) offers
simplicity. With a variable capacitor tuning the
tank, the Hartley will tune a very large range
since all of the capacitance IS van able.
Please note that the Inductor must be coupled to Pin 7 With a low Impedance capacitor.
The Colpitts oscillator Will exhibit a smaller
tuning range since the fixed feedback capacItors limit variable capacitance range; however, the Colpitts has good frequency stability
with proper components.

Synthesized Frequency Control
The NE602 can be very effective With a
synthesizer If proper precautions are taken to
minimize loading of the tank and the introduction of digital SWitching transients Into the
spectrum. Figure 4 shows a CIrCUIt suitable for
aircraft navigation frequencies (108 -118MHz)
with 10.7MHz IF.
The dual gate MOSFET prOVides a high
degree of isolation from prescaler SWitching
spikes. As shown In Figure 4, the total current

December 1988

Figure 3. Cellular Radio Application
consumption of the NE602 and 3SK126 IS
typically 3mA. The MOSFET Input IS from the
emitter of the OSCillator transistor to aVOid
loading the tank. The Gate 1 capacitance of
the MOSFET in senes With the 2pF coupling
capacitor adds slightly to the feedback capacitance ratio. Use of the 22k resistor at Pm
7 helps assure OSCillation Without upsetting
DC bias.
For applications where optimum buffenng of
the tank, or minimum current are not mandatory, or where cirCUit compleXity must be
minimized, the buffers shown In Figure 5 can
be conSidered.
The effectiveness of the MRF931 (or other
VHF bipolar transistors) Will depend on frequency and reqUired Input level to the prescaler. A bipolar transistor Will generally provide the least isolation. At low frequencies the
transistor can be used as an emitter follower,
but by VHF the base emitter Junction Will start

4-81

to become a bidirectional capacitor and the
buffer IS Jost.
The 2N5484 has an lOSS of 5mA max. and
the 2SK126 has lOSS of 6mA max. making
them SUitable for low parts count, modest
current buffers. The Isolation IS good

Injected LO
If the application calls for a separate local
OSCillator, It IS acceptable to capacltlvelycouple 200 to 300mV at Pin 6

Summary
The NE602 can be an effective low power
mixer at frequencies to 500MHz With OSCillator operation to 200MHz. All DC bias IS
provided Internal to the deVice so very compact deSigns are pOSSible. The Internal bias
sets the OSCillator DC current at a relatively
low level so the deSigner must choose frequency selective components which Will not
load the transistor. If the gUidelines mentioned are followed, excellent results Will be
achieved.

Signetics Linear Products

Application Note

Applying the Oscillator of the NE602
in low Power Mixer Applications

AN1982

Vee
0.8
1001<

2K

0.001

II

Vee

1001<

0.01

10nF

NE602

10.7 MHz

K & L 38780

12pF"

IF

OR EQUIV

.~

2-10pF
18K

FROM

SYNTHLOOP
FILTER
MV2105
OR EOUIV

NOTES:
* Permits Impedance match of NE602 output, Ie 1

*.

5KI/3pF to 35K filter Impedance

Choose for Impedance match to next stage

Figure 4

1001<

2K'

2K'
0.01

2pF

0.01

~
~~~-r-4~~
PRESCALER

~~~~~~

PRESCALER

471<

MRF931

2N5484

NOTE:
• 2K or as necessary for current limits or prescaler Impedance match

Figure 5

December 1988

4-82

3SK126

NE612

Signetics

Double-Balanced Mixer and
Oscillator
Product Specification
Linear Products
DESCRIPTION

FEATURES

The NE612 is a low-power VHF monolithic double-balanced mixer with onboard oscillator and voltage regulator. It
is intended for low cost, low power
communication systems with signal frequencies to 500MHz and local oscillator
frequencies as high as 200M Hz. The
mixer is a "Gilbert cell" multiplier configuration which provides gain of 14dB or
more at 49MHz.

• Low current consumption

The oscillator can be configured for a
crystal, a tuned tank operation, or as a
buffer for an external L.O. Noise figure at
49MHz is typically below 6dB and makes
the device well suited for high performance cordless telephone. The low
power consumption makes the NE612
excellent for battery operated equipment. Networking and other communications products can benefit from very low
radiated energy levels within systems.
The NE612 is available in an 8-lead dual
in-line plastic package and an 8-lead SO
(surface mounted miniature package).

PIN CONFIGURATION

•
•
•
•

Low cost
Operation to 500MHz
Low radiated energy
Low external parts count;
suitable for crystal! ceramic filter
• Excellent sensitivity, gain, and
nOise figure

APPLICATIONS
•
•
•
•
•
•
•
•

D, N Packages

INPUTAO.
INPUT B

Vee

2

1

OSCILLATOR

GROUNO

3

6

OSCILLATOR

OUTPUT A

4

5

OUTPUT 8

TOP VIEW

Cordless telephone
Portable radio
VHF transceivers
RF data links
Sonabuoys
Communications receivers
Broadband LANs
HF and VHF frequency
conversion

BLOCK DIAGRAM

November 3, 1987

4-83

853-0391 91251

•

Signetics Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

NE612

ORDERING INFORMATION
TEMPERATURE RANGE

DESCRIPTION

o to
o to

B-Pin Plastic DIP
B-Pin Plastic SO

ORDER CODE

+70°C

NE612N

+70°C

NE612D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

Vee

Maximum operating voltage

TSTG

Storage temperature

TA

Operating ambient temperature range

UNIT

9

V

-65 to + 150

°C

o to

+70

°C

AC/DC ELECTRICAL CHARACTERISTICS TA = 25°C, Vee = 6V, Figure 1
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITION
Min

Typ

Max
8.0

V

DC current drain

24

3.0

mA

fiN

Input signal frequency

500

MHz

fose

Oscillator frequency

200

MHz

Noise figured at 49MHz

5.0

dB

-15

dBm

Power supply voltage range

Vee

45

Third-order Intercept point at 49MHz

RIN

RFIN

= -45dBm

Conversion gain at 49MHz

14

RF Input resistance

15

RF input capacitance

CIN

Mixer output resistance

(Pin 4 or 5)

18

dB
krl

3

pF

1.5

krl

DESCRIPTION OF OPERATION

"1THIRO OVERTONE CRYSTAL

0.5 to 1.3,uH

Yeo

150pF

NE612

1.5 to
44.2,11

~
120pF

47pF

r--r--=-~

INPUT~O'209 to O.2831'H
220pF
100nF

Figure 1. Test Configuration

November 3, t 987

4-84

The NE612 IS a Gilbert cell, an oscillator/
buffer, and a temperature compensated bias
network as shown In the eqUivalent circuit.
The Gilbert cell is a differential amplifier (Pins
1 and 2) which drives a balanced switching
cell. The dlfferenlJal input stage provides gain
and determines the nOise figure and signal
handling performance of the system.
The NE612 IS designed for optimum low
power performance. When used with the
NE614 as a 49MHz cordless telephone system, the NE612 IS capable of receiving
-119dBm signals With a 12dB SIN ratio.
Third-order Intercept IS typically -15dBm
(that's approximately + 5dBm output intercept
because of the RF gain). The system designer must be cognizant of this large signal
limltaMn. When designing LANs or other
closed systems where transmission levels
are high, and smail-Signal or signal-to-nolse
Issues not cntical, the input to the NE612
should be appropnately scaled.

Product Specification

Signetics Linear Products

Double-Balanced Mixer and Oscillator

Besides excellent low power performance
well into VHF, the NE612 is designed to be
flexible. The input, output, and OSCillator ports
can support a variety of configurations provided the designer understands certain constraints, which will be explained here.
The RF inputs (Pins 1 and 2) are biased
Internally. They are symmetrical The eqUivalent AC input impedance IS approximately
I.Sk II 3pF through SOMHz. PinS 1 and 2 can
be used Interchangeably, but they should not
be DC biased externally. Figure 3 shows
three typical input configurations.

The mixer outputs (Pins 4 and S) are also
Internally biased. Each output IS connected to
the Internal positive supply by a I.Skn reSIStor. This permits direct output termination yet
allows for balanced output as well. Figure 4
shows three Single-ended output configurations and a balanced output.
The OSCillator IS capable of sustaining OSCillation beyond 200M Hz In crystal or tuned tank
configurations. The upper limit of operation IS
determined by tank "a" and required drive
levels. The higher the
of the tank or the
smaller the required drive, the higher the

a

NE612

permissible OSCillation frequency. If the reqUIred L.O. is beyond oscillation limits, or the
system calls for an external L.O., the external
Signal can be inlected at Pin 6 through a DC
blocking capacitor. External L.O. should be
200mVp_p minimum to 300mVp_p maximum.
Figure S shows several proven oscillator
circuits Figure Sa IS appropriate for cordless
telephones. In this circuit a third overtone
parallel-mode crystal With approximately SpF
load capacitance should be speCified. CapacItor C3 and inductor L 1 act as a fundamental
trap. In fundamental mode oscillation the trap
is omitted.
Figure 6 shows a Colpitts varacter tuned tank
OSCillator SUitable for syntheSizer-controlled
applications. It IS Important to buffer the
output of thiS circuit to assure that SWitching
spikes from the first counter or prescaler do
not end up In the OSCillator spectrum. The
dual-gate MOSFET prOVides optimum Isolation With low current. The FET offers good
Isolation, simplicity, and low current, while the
bipolar Circuits provide the Simple solution for
non-critical applications. The resistive divider
in the emitter-follower circuit should be
chosen to provide the minimum input signal
which Will assume correct system operation.

ill

GND

Figure 2_ Equivalent Circuit

NE612

NE612

a. Single-Ended Tuned Input

b. Balanced Input (for Attenuation
of Second Order Products)
Figure 3. Input Configuration

November 3, 19B7

4-85

c. Single-Ended Untuned Input

i

..

Signetlcs Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

NE612

CFU45.

OR EQUIVALENT
NES12

FILTER K&L38780 OR EQUIVALENT

NES12

·CT MATCHES 3 5Kn TO NEXT STAGE.

a. Single-Ended Ceramic Filter

b. Single-Ended Crystal Filter

NE612

NE612

c. Single-Ended 1FT

d. Balanced Output
Figure 4. Output Configuration

NE612

a. Colpitts Crystal Oscillator
(Overtone Mode)

NE612

NE612

b. Colpitts LlC Tank Oscillator

c. Hartley LIC Tank Oscillator

Figure 5. Oscillator Circuits

November 3, 1987

4-86

Signetics Uneor Products

Product Specification

Double-Balanced Mixer and Oscillator

NE612

I--..------:FA!R

'C02290S

l

f.G1pF
lOOK

2K
38Kl.
o.olpF

(-------I

,_

-

l

E---o
TO_

G.01pF

,_
":"

":"
":"

":"

":"

":"

Figure 6. Colpitts Oscillator Suitable for Synthaslzer Applications and Typical Buffers

TEST CONFIGURATION

NE812

TC0217QS

Figure 7. Typical Application for 46/49MHz Cordle.. Telephone
November 3. 1987

4-87

Signetics Linear Products

Product Specification

NE612

Double-Balanced Mixer and Oscillator

-14.5

-~

I
-1~.5

-n
-12

-~r--t---r~~~~

Ii ~r-~~~~+-~~
~r-~~-H~~~

I

i
i

-,2

-,2.5 -

-13

{.,3.5
-'4 -

i

f.-

~ -11.5

Ii

-15
-18

i!

-'7

./'

4

5

•

7

Ycc(VOLTSI

• •

-17.5

-18.5

to

-18.50

+40
TEMPERATURE ("c1

OPOI:J7(IS

OPOI380S

Figure 9. Input Thlrd-order
Intercept Point VB Vee

18

___ av

~

18

too--

-

~

4Y

5Y

av

-

~

12 ~.v

10

o

+40
TEMPERATURE ("c1

Figure 11

November 3, 1987

4Y

+70

,o

+40
TEMPERATURE ("c1

Figure 12

4-88

"""'_

.....,...,..

~

~

+70

Figure 10. ThlrdoOrder Intercept
Point VB Temperature

iii

zl!. ,.

----

-18.0

-tl

Figure 8. NE612 ThlrdoOrder
Intermod and 1dB Compression
Point Per10rmance

-,5.5

+70

""",

....

av
BY

---

+40
TEMPERATURE ("c1

Figure 13

TDA1574

Signetics

FM Front-End

Ie

Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA1574 is a monolithic integrated
FM tuner circuit designed for use in the
RFIIF section of car radios and home
receivers. The circuit comprises a mixer,
oscillator and a linear IF amplifier for
signal processing, plus the following additional features.

• Keyed automatic gain control
(AGe)
• Regulated reference voltage
• Buffered oscillator output
• Electronic standby switch
• Internal buffered mixer driving

IIr~l~

1

INM~~

2

WIDEB~g

3

AGCOUT
MIXER
OUT VOLT
MIXER
OUT VOLT

4

vcc

5

IF AMP IN
IN BIAS
VOLT-IF AMP
AGC
NARROWBAND INFO
STANDBY
SWITCH
UNEAR
IF AMP OUT

INFO
GND

v~If

APPLICATIONS
•
•
•
•

N Package

OSCJ1l1.~ 6

FM radio
Radio communication
Auto radio
High-performance stereo FM

O~l~
O~l~

7

11

8

OSCi~J 9

1..-_---'
TOP VIEW

ORDERING INFORMATION
DESCRIPTION

ORDER CODE

TEMPERATURE RANGE

1B-Pin Plastic DIP (SOn 02HE)

o to

+70·C

TDA1574N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNITS

Vcc = V15-4

Supply voltage (Pin 15)

1B

V

V16. 17-4

Mixer output voltage (Pins 16 and 17)

35

V

V11_4

Standby switch input voltage (Pin 11)

23

V

V5-4

Reference voltage (Pin 5)

7

V

PTOT

Total power dissipation

BOO

mW

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-40 to +B5

·C

°JA

Thermal resistance from junction to
ambient (in free air)

80

·C/W

NOTE:
1. All Pins are short-circuit protected to ground.

FUNCTIONAL DESCRIPTION
Mixer
The mixer circuit is a double balanced
multiplier with a preamplifier (common
base input) to obtain a large signal
handling range and a low oscillator radiation.

OSCillator
The oscillator circuit is an amplifier with
a differential input. Voltage regulation is
achieved by utilizing the symmetrical
tank-transfer function to obtain low-order 2nd harmonics.

Linear IF amplifier
The IF amplifier is a one-stage, differential input, wideband amplifier with an
output buffer.

Keyed AGC
The AGC processor combines narrowand wideband information via an RF
level detector, a comparator and an
ANDing stage, The level-dependent,
current sinking output has an active load
which sets the AGC threshold.

November 14, 19B6

4-89

B53-0970 B6554

Product Specification

Signetics Linear Products

FM Front-End

Ie

TDA1574

BLOCK DIAGRAM AND TEST CIRCUIT
AGCOUTPUT

10

r---------~--._~~~--------------------------------_Ov~
RM<.3OO

N2 N,,.I:.r...._ _.....,

220FtFl

100

~

220Fl

88

18

16

15

n

14

AGC
NARROWBAND

~FORMA:~N
13

12

Ir.ANDBY SWITCH
THRESHOLD
SUPPLY VOLTAGE

11

lnF

BUFFERED

>---M.....-t----t':::g-iFOSCILLATOR
RL OUTPUT
r.=~~~---U~

n

•

EMF

1

f=98MHz

NOTES:

CoIlDaIa
L1 TOKO MC-l0S. 514HNE-150023S14, L=007SpH
L2 TOKO MC-lll, E516HNS-200057, l-OOSpH
L3 TOKO cOil set 7P, N1 =0 5 5 + 5 5 turns. N2" 4 turns

November 14, 1986

4-90

8

Signetics Linear Products

FM Front-End

Product Specification

Ie

TDA1574

DC AND AC ELECTRICAL CHARACTERISTICS Vee = V15 - 4 = B.5V; TA = 25°C; measured in test circuit (Block Diagram),
unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Supply (Pin 15)
Vee = V15 - 4

Supply voltage

7

16

V

Icc = 115

Supply current (except mixer)

16

23

30

mA

V5-4

Reference voltage (Pin 5)

4.0

4.2

4.4

V

35
4.5

V
V
mA

9
11
115

dB
dB
dBIN

14

dB

12
13

n
pF

Mixer
V1. 2- 4
V16,17-4
116+ 117
NF
NF
EMF11P3

DC characteristics
Input bias voltage (Pins 1 and 2)
Output voltage (Pins 16 and 17)
Output current (Pin 16 + Pin 17)

1
4

AC characteristics (fl = 9BMHz)
Noise figure
Noise figure including transforming network
3rd order intercept point
Conversion power gain
4(VM(Out) 10.7 MHz)2

RSI

x-

Gp

10 log

Rl,2-4
C16,17

Input resistance (Pins 1 and 2)
Output capacitance (Pins 16 and 17)

(EMFl 9B MHz)2

RML

Oscillator
V7, 6-4
V6_4

DC characteristics
Input voltage (Pins 7 and B)
Output voltage (Pin 6)

1.3
2

V
V

tof

AC characteristics (fose = 10B.7MHz)
Residual FM (Bandwidth 300Hz to 15kHz);
de-emphasis = 50llS

2.2

Hz

1.2
3.5

V
V

Linear IF amplifier
V13-4
VIO-4

DC characteristics
Input bias voltage (Pin 13)
Output voltage (Pin 10)
AC characteristics (fl = 10. 7MHz)
Input impedance

R14 - 13
C14-13

240

300
13

360

n
pF

240

300
3

360

n
pF

27

30

dB

Output impedance
R1o- 4
C1O- 4
Voltage gain
GVIF

20 log V1O - 4
V14 - 13

TA = -40 to +B5°C

0

dB

Vl0-4RMS
V1O- 4RMS

1 dB compression point (RMS value)
at Vee = B.5V
at Vee = 7.5V

900
500

mV
mV

NF

Noise figure
at Rs= 300n

6.5

dB

t..GVIF

November 14, 19B6

4-91

•

Signetics Linear Products

FM Front-End

Product Specification

Ie

TDA1574

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) VCC=V 15_4=8.5V; TA=25°C; measured in test c;:ircuit
(Block Diagram), unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Keyed AGe

118

DC characteristics
Output voltage range (Pin 18)
AGC output current
at 13 = q,or
V12 - 4 = 450mV; V18-4 = Vcc/2
at V3 - 4 = 2V and
V12-4 = lV; V18-4 = V15-4

V18-4
V18 - 4

Narrow-band threshold
at V3 - 4 = 2V; V12-4 = 550mV
at V3 - 4 = 2V; V12 - 4 = 450mV

V18-4

-1 18

0.5

25

50

2

Vcc- 0.3

V

100

p.A

5

mA

1

V
V

Vcc- 0.3

AC characteristics (fl = 98MHz)
Input impedance
4
3

R3-4
C3-4

EMF2RMS

Wide-band threshold (RMS value)
(see Figures 1, 2, 3 and 4)
at V12 - 4 =0.7V; V18_4=Vcc/2; 118 =0

-

kQ
pF

19

mV

6.0

V

110

mV
mV

Oscillator output buffer (Pin 9)
V9-4

DC output voltage

V9-4RMS
V9- 4RMS

Oscillator output voltage (RMS value)
at RL = 00
at RL = 75Q

R9- 15

DC ouput impedance

2.5

kQ

THD

Signal purity
total harmonic distortion

-15

dBC

fs

Spurious frequencies
at EMFl = 1V; RSl = 50Q

-35

dBC

25

Electronic standby switch (Pin 11)
OSCillator; linear IF amplifier; AGC at TA = -40 to +85°C

Vl1 - 4

Input switching voltage
for threshold ON; V18_4;;'Vcc-3V
for threshold OFF; V18 - 4 ';; 0.5V

-111
111
Vll - 4

Vl1 _ 4

November 14, 1986

0
3.3

2.3
23

V
V

Input current
at ON condition; V11 _ 4 = OV
at OFF condition; V11 _4 = 23V

150
10

p.A
p.A

Input voltage
at 111 = q,

4.4

V

4-92

Signetics Linear Products

FM Front-End

Product Specification

Ie

TDA1574

'O.---.---r---~--'---'---,

'0r---r---r---r---r---r-~

v'8_"

V'8_4
(VI

(VI

8~--+---+---~--~---r--~

~00~--L-~5~00~"-=~8~00~"--~700
V12_4(mV.
OP19600S

Figure 1. Keyed AGC Output Voltage V'8-4 as a Function
of RMS Input Voltage V3-4. Measured in Test Circuit
(Block Diagram) at V'2_4 = O.7V; 1'8 = 

Figure 2. Keyed AGC Output Voltage V'8_4 as a Function
of Input Voltage V'2-4. Measured In Test Circuit
(Block Diagram) et V3_4=2V; 1'8 = 

',S

"8
(mAl

5

(mAl

4

I
I
I

I
I

,

,

II

o
400

0

'0

20

30

Figure 3. Keyed AGC Output Current I,e as a Function
of RMS Input Voltage V3- 4• Measured in Test Circuit
(Block Diagram) at V'2-4 = O.7V; V'8-4 = B.5V

November 14, 1986

500

V3_4(mVI

Figure 4. Keyed AGe Output Current 1'8 as a Function
of Input Voltage V 12 _.. Measured In Test Circuit
(Block Diagram) at V3-4 = 2V; V'8-4 = B.5V

4·93

Product Specification

Signetics Unear Products

FM Front-End

Ie

TDA1574

10

r--------1~--------~~----------------~--~~------------------------~S~TAN~D~B~V~S~W=IT=C~H~---Ovcc
THRESHOLD
SUPPl.V VOLTAGE
LOW FOR FM ON

QHQI-o
SFE

10

18

LINEAR
IF AMPl.IFIER

~

OUTPUT

1nF

BUFFERED

TDA1S74

9

>--""-+---f~~ g~~'ti:TOR
~ RL

(losC>

I

~

ANTENNA

Vee

GAIN CONTROLLED
RFPRESTAGE

L-______~~---------------_4--------_o~~~E
NOTES:
1 Field strength Indication of main IF amplifier

COil Data:
L1 TOKO Me-lOS. N1 ;; 5 5 turns, N2"" 1 turn

~ } see Block DIagram

Figure 5. TDA1574 Application Diagram

November 14, 1986

4-94

TDA5030A

Signetics

VHF MixerjOsciliator Circuit
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA5030A performs the VHF mixer,
VHF oscillator, SAW filter IF amplifier,
and UHF IF amplifier functions in television tuners.

• A balanced VHF mixer
• An amplitude-controlled VHF
local oscillator
• A surface acoustic wave filter IF
amplifier
• A UHF IF preamplifier
• A buffer stage for driving an
external prescaler with the local
OSCillator signal
• A voltage stabilizer
• A UHF/VHF switching circuit

PIN CONFIGURATIONS

N Package
DECOUP

1

VHF INPUT 2

DECOUP

4

MIX/IF PREAMP
(UtF) OUTPUT

MIX/IF PREAMP
(UHF) OUTFUT

IrN~~~

'rN~~

1

OSCOUTPUT

1

SWitcH INPUT

11 :;.:::;,.

-,___....'_0 :r~&r
TOP VIEW

• Mixer/oscillator
• TV tuners

D Package

• CATV

• LAN
• Demodulator

VHF DECOUP

1

VHF INPUT

2

OSC INPUT

IFAMP

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

18-Pin Plastic DIP (SOT-l02A)

- 25'C to + 85'C

TDA5030AN

20-Pin Plastic SO DIP (SOT-163A)

-25'C to +85'C

TDA5030ATD

DECOUP
IF PREAMP
INPUT
Ne 6
MIXIIF PREAMP
(UHF) OUTPUT

~~.w; ~u~~~

'fN~
'fN~~

3 SWITCH INPUT

12

~u~~

_'. ,0'-___r-" ~.m~
TOP VIEW

BLOCK DIAGRAM

18

Vee

IF •

APPLICATIONS

DESCRIPTION

DECOUP

16

15

13

TDA5030A

12

NOTE:
Pinout

IS

for 18-pln N package

January 14, 1987

4-95

853-115087202

Signetics Linear Products

Product Specification

VHF MixerjOsciliator Circuit

TDA5030A

VT

UHF/VHF
SWITCH

Vee

Bill

BB909B

B,

::t.

1.5pF

~lnF

lnF

IDCAL OSCILLATOR OUTPUT

-=

f

rr e
82pF

nF

N7W

-=

18

17

-=
lnF
16

15

14

13

12

TDAW30

lnF

270

VHF INPUT

o------.J

IF INPUT 0 - - - - - - - -_ _ _ _---1

Figure 1. Test Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

14

V

Vce

Supply voltage (Pin 15)

V,

Input voltage (Pin 1, 2, 4, and 5)

V12

Switching voltage (Pin 12)

-1 10, 11, 13

Output currents

10

mA

tss

Storage·circuit time on outputs
(Pin 10 and 11)

10

s

·C

o to
o to

5

V

Vee+0.3

V

TSTG

Storage temperature range

-65 to + 150

TA

Operating ambient temperature range

-25 to +85

·C

TJ

Junction temperature

+125

·C

flJA

Thermal resistance from junction to
ambient

+55

·C/W

January 14, 1987

4-96

270

Product Specification

Signetics Unear Products

TDA5030A

VHF Mixer/Oscillator Circuit

DC AND AC ELECTRICAL CHARACTERISTICS

Measured in circuit of Figure 1; Vce = 12V; TA = 25°C, unless otherwise
specifIed
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

Supply
Vcc

Supply voltage

Icc

Supply current

10
42

13.2

V

55

mA

V12

SWItching voltage VHF

0

2.5

V

V12

Switching voltage UHF

9.5

Vcc+ 0.3

V

112

Switching current UHF

0.7

mA

470

MHz

9
10
12

dB
dB
dB

VHF mixer (including IF amplifier)
fR

Frequency range

NF

Noise figure (Pin 2)
50MHz
225MHz
300MHz

75
9
10

Optimum source admittance (Pin 2)
50MHz
225MHz
300MHz

0.5
1.1
1.2

ms
ms
ms

Input conductance (Pin 2)
50MHz
225M Hz
300MHz

0.23
0.5
0.67

ms
ms
ms

G

GI

CI

Input capacItance (Pin 2)
50MHz

V2_3

Input voltage for 1% cross-modulation
(in channel); Rp > 1kn; tuned circuit
wIth Cp = 22pF; fRES = 36MHz

50

97

V2-14

Input voltage for 10kHz pulling (in channel) at

Av

Voltage gain

< 300MHz

2.5

pF

99

dBj.lV

dBj.lV

100
22.5

24.5

26.5

dB

UHF preamplifier (including IF amplifier)
GI

Input conductance (Pin 5)

0.3

C,

Input capacItance (Pin 5)

30

NF

Noise figure

5

VS-14

Input voltage for 1% cross-modulation (in channel)

Av

Voltage gaIn

Gs

Optimum source admittance

January 14, 19B7

BB

90

31.5

33.5
3.3

4-97

ms
pF
6

dB
dBj.lV

35.5

dB
ms

Signetlcs Linear Products

Product Specification

VHF MixerjOscillator Circuit

TDA5030A

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Measured in circuit of Figure 1; Vee = 12V; TA = 25°C.
unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

VHF mixer
YC2-6,7

Conversion transadmittance

5.7

ms

Zo

Output impedance

1.6

kn

VHF oscillator

fR

Frequency range

520

MHz

Af

Frequency shift
AVec = 10%; 70 to 330M Hz

200

kHz

AI

Frequency drift
AT = 15k; 70 to 330M Hz

250

kHz

AI

Frequency drift Irom 5sec to 15min after switching on

200

kHz

70

SAW filter IF amplifier
Ze.9

Input impedance
Z10, 11 = 2kn. 1= 36MHz

Ze, 9-10, 11

Transimpedance

Z10.11

Output impedance
Ze, 9 = 1.6kn; I = 36MHz

340+il00

n

2.2

kn

50+j40

n

20
20

mV
mV

90

n

VHF local oscillator buffer stage

V13
V13
Z13

RF
(RF+LO)

January 14. 19B7

Output voltage
RL = 75n; 1< 100MHz
RL = 75n; I> 100MHz

14
10

Output impedance
f= 100MHz
RF signal on LO output; RL = son; VI = 1V; I';;; 225M Hz

4-98

10

dB

Signetics

CA3089
FM IF System
Product Specification

Linear Products

DESCRIPTION
CA3089 is a monolithic integrated circuit
that provides all the functions of a comprehensive FM IF system. The block
diagram shows the CA3089 features,
which include a three-stage FM IF amplifier/limiter configuration with level detectors for each stage, a doubly-balanced quadrature FM detector and an
audio amplifier that features the optional
use of a muting (squelch) circuit.
The circuit design of the IF system
includes desirable features such as delayed AGC for the RF tuner, an AFC
drive circuit, and an output signal to drive
a tuning meter and/or provide stereo
switching logiC. In addition, internal power supply regulators maintain a nearly
constant current drain over the voltage
supply range of + 8V to + 18V.
The CA3089 is ideal for high-fidelity
operation. Distortion in a CA3089 FM IF
system is primarily a function of the
phase linearity characteristic of the outboard detector coil.

The CA3089 utilizes a 16-lead dual-inline plastic package and can operate
over the ambient temperature range of
-40'C to +85'C.

PIN CONFIGURATION
N Package

FEATURES

IF INPUT
BYPASSING

• Exceptional limiting sensitivity:
10llV typo at -3dB point
• Low distortion: 0.1% typo (with
double-tuned coil)
• Single-coil tuning capability
• High recovered audio: 400mV
typo
• Provides specific signal for
control of interchannel muting
(squelch)
• Provides specific signal for direct
drive of a tuning meter
• Provides delayed AGC voltage
for RF amplifier
• Provides a specific circuit for
flexible AFC
• Internal supply/voltage regulators

If INPUT
BYPASSING

aUAORATURf'
INPUT

TOP VIEW

APPLICATIONS
• High-fidelity FM receivers
• Automotive FM receivers
• Communications FM receivers

BLOCK DIAGRAM

,---------------------------------------------------------------------

.Fe
OUTPUT

AUDIO
OUTPUT

"K
12

470

TO STEREO
THRESHOLD
LOGIC CIRCUITS

NOTES:
1 All reSIstor values are typical and In ohms 00 ~ 75 (G I EX27825 or eqUIvalent)

L tunes With 100pF (C) at 107MHz
L2-______________________________________________
. _________________ . ________

November 14, 1986

4-99

~

853-0044 86551

Signetics linear Products

Product Specification

FM IF System

CA3089

EQUIVALENT SCHEMATIC

NOTES:
1 All resistance values are tYPical and In ohms
2 All capacitance values are In picofarads

November 14, 1986

4-100

Signetics Linear Products

Product Specification

FM IF System

CA3089

ORDERING INFORMATION
DESCRIPTION

16-Pin Plastic DIP

TEMPERATURE RANGE

ORDER CODE

-40'C to + 85'C

CA3089N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vce

Po

RATING

UNIT

DC supply voltage:
between terminals 11 and 4
between terminals 11 and 14

PARAMETER

18
18

V
V

DC current (out of Terminal 15)

2

mA

Device dissipation:
up to TA = 60'C
above T A = 60'C

600
derate linearly
6.7

mW
mW/'C

TA

Operating ambient temperature range

-40 to +85

'C

TSTG

Storage temperature range

-65 to + 150

'C

TSOLO

Lead soldering temperature
(10sec max)

+300

'C

November 14, 1986

f

I

4-101

•

I

Product Specification

Signetics Linear Products

CA3089

FM IF System

DC ELECTRICAL CHARACTERISTICS TA = 25°C, V+ = 12V, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Typ

Max

No signal input, non-muted

16

23

30

Static (DC) Characteristics
111

Quiescent Circuit current

mA

DC Voltages4
V1

Terminal 1 (IF input)

No signal input, non-muted

1.2

1.9

2.4

V

V2
V3

Terminal 2 (AC return to input)
Terminal 3 (DC bias to input)

No signal input, non-muted
No signal input, non-muted

1.2
1.2

1.9
1.9

2.4
2.4

V
V

V6
V7
V10

Terminal 6 (audio output)
Terminal 7 (AFC)
Terminal 10 (DC reference)

No signal input, non-muted
No signal input, non-muted
No signal input, non-muted

5.0
5.0
5.0

5.6
5.6
5.6

6.0
6.0
6.0

V
V
V

10

25

IlV

Dynamic Characteristics
V'(LlM)

Input limiting voltage (-3dB point)3
AMR AM rejection (Terminal 6)4

Vo

Recovered audio voltage (Terminal 6)3

THO
THO

Total harmonic distortion: 1
Single tuned (Terminal 6)3
Double tuned (Terminal 6)4

S+N/N
MU,N

Signal plus noise-to-noise ratio (Terminal 6)3
Mute input (Terminal 5)

MUOUT

Mute oulput (Terminal 12)

Y'N = O.lV, fo = 10.7MHz,
fMOD = 400Hz, AM Mod = 30%

400

500

600

mV

0.5
0.1

1.0

%
%

Deviation = ± 75kHz, Y'N = 0.1 V
V5 = 2.5V

60
50

Y'N = 50llV
Y'N =OV

4.0

Meter output (Terminal 13)

Y'N = O.lV
Y'N = 500llV
V'N=OV

AGC

Delay AGC (Terminal 15)

Y,N = O.OlV
Y,N = 10llV

Double tuned (Terminal 6)4

55

fMOD = 400Hz, Y'N = 0.1

MTR

THO

45

fMOD = 400Hz
Y'N = 0.1

dB

70
70

dB
dB
0.5

2.5
1.0

3.5
1.5
0.7
0.5

4.0

V
V
V
V
V

5.0

V
V

0.1

%

NOTES
1. THO characteristics and audio level are essentialty a function of the phase and Q characteristics of the network connected between Terminals 8, 9,

and 10.
2. Test Circuit Figure 1.
3. Test Circuit Figure 2.

4. Test circuit Figures 1 and 2.

November 14, 1986

4-102

Product Specification

Signetics Linear Products

CA3089

FM IF System

TEST CIRCUITS
V

12\1

ita:;

l'OOp'1
I
I

s:~~~~rO"

VOLTAGE

,

v-

12\1

AFe OUTPUT

I c, I
I__ h·
I
I

I
AUDIO
OUTPUT

I

SIGNAL
INPUT
VOLTAGE

1I
00"

002"I

NOTES:
1 L tunes with l00pF (C) at 107MHz.
2 All resistor values are typical and In ohms
3. Co (unloaded) ~ 75 (G I automabe mig dIV EX27825 or equ,valent)

Figure 1. Test Circuit Using a Single-Tuned Detector Coil
NOTES:
All resastor values are typtcal and In ohms
T. Pn-Co (unloadod) ~ 75 (tunos WIth 100pF (Cl) 20 t of 340 on 7132' ilia
form) Sec -0 (unloaded) ~ 75 (tunes With 100pF (C2) 20 t of 34e on 7/32'
dla form)
kQ (percent of cnbcal coupling) > 70%
(Adjusted for COil voHage Vc - 150mV)
Above values permit proper operation of mute (squelch) arcurt 'E' type slugs,

spacing 4mm

Figure 2. Test Circuit Using a Double-Tuned Detector Coli

November 14, 1986

4-103

Signetics Linear Products

Product Specification

FM IF System

CA3089

TEST CIRCUITS
y'" ",12Y

NOTES:
All reSistor values are typical and In ohms.
1 Waller 4SN3FIC or equNalent
2 Murate SFG 10. 7mA or eqUivalent
3. As will affect stability dependmg on ClrCUlt layout To Increase stablhty Rs IS decreased
Range of Rs IS 330 to 50n, R, + As ~ 330n
4 L tunes with 100pF (C) at 107MHz 00 unloaded ~ 75 {G I EX27825 or eqUIvalent}
Performance data at fo - 98MHz, fMOD = 400Hz, deviatIOn = ± 74kHz
±74kHz
- 3dB limiting sensltlvrty
2p.V (antenna level)
20dB qUieting sensitivity
1JlV (antenna level)
30da qUieting sensitIVIty
1 SpV (antenna level)

Figure 3. Typical FM Tuner With a Single·Tuned Detector Coli

SYSTEM DESIGN
CONSIDERATIONS
The CA3089 is a very high gain device and
therefore careful consideration must be given
to the layout of external components to
minimize feedback. The input bypass capaci.
tors should be located close to the input
terminals and the values should not be large

nor should the capacitors be of the type
which might introduce inductive reactance to
the circuit. An example of good bypass ca·
pacitors would be ceramic disc with values in
the range of 0.01 to 0.05/lF.
The input impedance of the CA3089 is ap·
proximately 10,000n. It is not recommended

to match this impedance. The value of the
input termination resistor should be as low as
possible without degrading system operation.
The lower the value of this resistor the
greater the system stability. An input terminat·
ing resistor between 50n and 1oon is recom·
mended.

TYPICAL PERFORMANCE CHARACTERISTICS
Muting Action, Tuner AGC
(Tuning meter output as a
function of input signal voltage.)

AFC Characteristics
(Current at Terminal 7 as a
function of change in frequency.)
'25

DC VOLTAGE SUPPLY V 1"::: 12V
AMBIENT TEMPERATURE(T A) =... 2SoC
TEST CIRCUIT - SEe FIGURE 3

..

I;;i

..

;

+-....:~-,~-t 4 ~

'00
75
50

...;!;
...z
w
"'"'::>

g

0

-25

'K

'OK

/'

/

V

.J

-75

/
-'00

'OOK

-50

o

50

CHANGE IN FREQUENCY (Af)- kHz

INPUT SIGNAL - J.JV

November 14, 1986

/

-50

-125

'00

"A

25

" -'00

l- I--

~

~

g

'0

~;:'~:i~E:::;:T~;J (T:~v= 2~OC
SEE TEST CIRCUIT FIGURE 3

4·104

'00

MC3361

Signetics

Low Power FM IF
Product Specification

Linear Products
DESCRIPTION
The MC3361 is a monolithic low-power
FM IF signal processing system consisting of an oscillator, mixer, limiting amplifier, quadrature detector, filter amplifier,
squelch, scan control and mute switch. It
is intended for use in narrow band FM
dual conversion communications equipment. The MC3361 is available in a 16lead, dual-in-line plastic package and
16-lead SOL (surface-mounted miniature package).

FEATURES
• 2.0V to B.OV operation
• Low current: 4.2mA typ at
Vcc= 4.0Voc
• Excellent sensitivity: 2.0J.lV for
-3dB limiting typ
• Low external parts count
• Operation to 60MHz

PIN CONFIGURATION
0 1 and N Package

oac.

RF
INPUT
GNO

MIXER

AUDIO
MUTE

CIIYS'tIIL {
O\ITI'UT

3~L

Vee
U..-rER
INPUT

_LCH

DECOUPUNQ

APPLICATIONS
• Cordless telephone
• Narrow band receivers
• Remote control

~~

:::lot::

11

1

7

8

1 0 - 0 _....

~Il-r
FILTER INPUT
DEMOO.
OUTPUT

NOTE:
1 Available In 16-pln SOL package

BLOCK DIAGRAM
IDER
INPUT

March 28, 1988

SCAN

GND

MUTE

CONTRDL

SQUELCH
IN

FILTER
O\ITI'UT

FILTER
INPUT

4-105

RECOVERED
AUDIO

853-1190 92745

•

Signetics Linear Products

Product Specification

Low Power FM IF

MC3361

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic DIP

-40 to +85°C

MC3361N

16-Pin Plastic; SOL

-40 to +85°C

MC3361 0

ABSOLUTE MAXIMUM RATINGS
SYMBOL

(TA = 25°C, unless otherwise noted)

PARAMETER

PIN

RATING

UNIT

Vee (Max)

Power Supply voltage

4

10

Voc

Vee

Generating supply voltage range

4

2.0 to 8.0

Voc

Detector input voltage

8

1.0

Vp.p

V16

Input voltage (Vee:::4.OV)

16

1.0

VRMS

V14

Mute function

14

-0.5 to 5.0

VPK

TJ

Junction temperature

150

°C

TA

Operating ambient temperature range

-40 to +85

°C

TSTG

Storage temperature range

-65 to +150

°C

AC AND DC ELECTRICAL CHARACTERISTICS (Vcc = 4.0Voc, fo = 10.7MHz, af - ±3.0kHz, fMOO = 1.0kHz, TA - 25°C
unless otherwise noted.)

LIMITS
PARAMETER

PIN

TEST CONDITIONS

UNIT
Min

Drain current (no signal)
squelch off
squelch on
Input limiting voltage
Detector output voltage

4
16

-3.0dB limiting

9

4.2
5.4

7.0
9.0

2.0

6.0

VIN - 10niVAMS

100

VIN - 1.0mVRMS

40

11

Trigger hysteresis

150

rnA
IJ-V
Voc
n

450
9

Filter gain (10kHz)
Filter output voltage

Max

2.0

Detector output impedance
Recovered audio output voltage

Typ

270

mVAMS

46

dB

1.7

Voc

50

mV

Mute function low

14

10

n

Mute function high

14

10

Mn

Scan function low (mute off)

13

V12=1.0Voc

Scan function high (mute on)

13

V12=GND

0.5
3.5

Voc
Voc

Mixer conversion gain

3

27

dB

Mixer input resistance

16

3.6

kn

Mixer input capacitance

16

2.2

pF

March 28, 1988

4-106

Signetics Linear Products

Product Specification

low Power FM IF

MC3361

TEST CIRCUIT

O.OI"F

MIXER INPUT
10.7MHz
51

muRata
CFU455D2

AUDIO MUTE

I

SCAN CONTROL

I

10k
SQ SW INPUT
O.1p.F

O.1J.LF

1.0"F

+
20k

f-o RLTER AMP IN

8.2k
AF OUTPUT
lO.OI"F

QUADCDlL
TOKOTYPE
RMC-2A6597HM

March 28, 1988

4-107

•

AN1992

Signetics

Using the Signetics MC3361
Demonstration Board
Application Note

Linear Products

Author: Michael M. Sera

INTRODUCTION
Circuit Description
This demo is set up to show the functions of
the Signetics MC3361. The MC3361 is a Low
Power Narrow-Band FM IF. It IS designed for
use as the second IF of FM dual conversion

communications eqUipment. The MC3361 includes the following:
• Oscillator

• Active filter
• Squelch
• Scan control
• Mute switch

• Mixer
• limiting amplifier
• Quadrature discrlmmator

115VAC

O.1~F +12V
CERAMIC

~~+---------~

10

10k

6

2

NE555

5

I-::-

Cc
3

CT
100

"!:4.7,.F

1---"'-1-: 2N3906 ill

Fl:

13

LINE NEIIT

7

--+-10k

510

[ TRIGGER
OIlT

<,-CONTROL
O·5V oc

-aJn1---....n

n

L_____

T=8.33msec

=~i <' =_"'_'X_T_'8_0_0

NOTE:
This IS the schematiC of the Signetics MC3361 demonstration board The mput and output connectIOns are AC-coupled to protect the deVice from
any DC that may be Introduced at the Inputs The supply IS capacltlvely decoupled to ground to help eliminate any AC on the supply hne

Figure 1. Schematic of the Signetics MC3361 Demonstration Board
December 1988

4-108

Signetics linear Products

Application Note

Using the Signetics MC3361 Demonstration Board

The appllcallon outlined here does not demonstrate the absolute maximum performance
of the Signetics MC3361. It IS merely an
example given to show the flexibility of the
part.

In general, the external components used for
each applicalion tend to be the IImlling factors In each application. In order to make the
demo board sUItable for general usage, the
Local Oscillator (LO) IS supplied externally.

COIIPONENT SIDE

AN1992

ThiS allows the Input frequency to operate
anywhere within the limltallOns of the part.
The Inputs have not been matched for any
one partIcular frequency.

•

3012 Sl30J02
Figure 2. Layout of the Signetics MC3361 Demonstration Board

PARTS LIST

Signetics

Capacitors
Cl
C2
C3
C4
C5
C6
C7
C8
C9
C10
Cll
C12
C13
C14
C15

G
BNC

Rl1

R4;g:: Q

~

MC3361

O.lfJF
O.1fJF
O.1fJF
10fJF Elect
o lfJF
o 1fJF
O.lfJF
O.lfJF
o 47fJF
O.OlfJF
000lfJF
O.001fJF
O.OlfJF
o 1fJF
o 1fJF

LEO'~2 ~
~
u~
l8J
~

_Q ~~ +~

R6

~

a::

RF

@ill @ill

JUMPER1
IN

)

MC3361

Al0

c:JAUOIO

0:

)

Q'~~":II'~B
":.
LJ
~)
Figure 3. Part Layout for Demonstration Board

Resistors l
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rll

51
51
330
68k
120k
390k
750
18k
20k
7.5k
51k

NOTE:
1. All resistors are 5%

December 1988

1'4
1'4
1'4
1'4
1'4
1'4
1'4
1'4
1'4
1'4
1'4

W
W
W
W
W
W
W
W
W
W
W

Miscellaneous
MC3361
LEDl
D1
P1
01
F1
BNC

SIGNETICS MC3361
Red LED
DIode (1N4148)
50k PotentIometer (BOURNS 3299 144C 50K)
Ouad Tank (TOKO RMC 2A6597HK 1)
455kHz FIlter (MURUTA CFU455D22 )
BNC Connector (KINGS KC-79-232-M06)

NOTES:
1 TOKO AMERICA INC
West Touhy Ave
SkokIe, IL 60077
Tel' (213) 677-3640
CA (408) 996-7575

4-109

BNC

130

-c:::l-

MURUTA ERIE
1453 Lmcoln Street
Caritsle, PA 17013
Tel (717) 249-2232

GND +Vcc

Signetics Linear Products

Application Note

Using the Signetics MC3361 Demonstration Board

Matching the Input will Increase the sensitivity
of the part. See Appendix II for matching
network.

LAYOUT
The board layout uses basIc RF techniques,
I.e , GND on both top and bottom layers, very
short Input and output lead lengths and wide
traces, with decoupllng capacitors on the
supply lines.

Operation of the MC3361
Demonstration Board
In this application the MC3361 IS set up as an
FM receiver. The Inpulls mixed with the La to
convert the Input signal down to 455kHz. The
signal then goes through an external
(455kHz) ceramic bandpass filter. Next, the
455kHz signal goes through a limiting amplifier. The audio is finally recovered uSing an FM
demodulator and then amplified by an audiO
amp.
The absence of an Input signal IS indicated by
the presence of nOise above the deSired
audiO frequencies. This' nOise band' IS monitored by an active filter and a detector. A
squelch control CirCUit mutes the audiO output
signal when the 'noise band' IS above a
certain level set by P1 The squelch control
CirCUit also provides a scan control output
(Pin 13) which can be used to drive an LED,
as we have done on the application board.

AN1992

3. Connect # 1 Signal Generator to RF,N;
note the frequency on the display. Set the
signal generator to FM With a peak devialion of 3kHz and a modulation frequency
of 1kHz. The amplitude should be adJusted to around - 20dBm (22mVRMS).

and up to 8 OV. The demo board Will function
With a supply voltage as low as 3.5V. The
demo board consumes 4.7mA (Mute off) and
8.2mA (Mute on, LED current Included) at
5.0V. A regulated supply With at least
+ 3.5VDe should be connected to the + Vee
terminal of the board. The same supply's
ground should be connected to the GND
terminal.

4. Connect # 2 Signal Generator to LO,N,
noting the frequency of the # 1 Signal
Generator connected to RF,N; add or
subtract 455kHz from that number and
adjust the # 2 Signal Generator to this
frequency. The amplitude should be set at
OdBm (220mVRMS). Make sure no modulation IS applied at this input.

QT1 (Quad Tank) - ThiS IS the 'Silver can'
located near the supply Inputs. It has been
adjusted at the factory. If It needs to be
adjusted, see Testing.
P1 (Potentiometer) - ThiS adjusts the senSitIVIty of the mute function. ThiS Will cause
the AUDIO to be muted at varying levels of
RF Input amplitudes.

5. Connect an OSCilloscope to AUDIO. The
OSCilloscope should trigger off of a signal
near 1kHz. The Red LED should not be lit.
If the Red LED is lit, adjust P1 until the
Red LED turns off.

The Red LED (Mute ON Indicator) - When
lit, the audiO signal IS muted. P1 (potenllometer located near AudiO Out connection) adjusts the mute senSitIVIty. The SenSITIVity can
be checked by varying the RF Input amplitude.

6. Once all the connections have been
made, you should see a clean sine wave
on the OSCilloscope.
7. Peak the amplitude of the sine wave seen
at the AUDIO output by adjusting QT1.
ThiS Will tune the Quadrature Detector.

TESTING AND ADJUSTING THE
DEMONSTRATION BOARD

8. To test the sensitivity of the CirCUit, vary
the input amplitude of the RF'N signal.
The sine wave Will start to get noisy
around - 100dBm. As you decrease the
amplitude even more, the' noise band' will
Increase, causing the Squelch Control
CirCUit to trigger. When the Squelch Control CirCUit does trigger, the audiO output
Will go to OV and the Red LED Will be on.

Equipment Required
Power Supply: HP 6216A or equivalent
Signal Generator: HP 8640B or equivalent
Signal Generator: HP 8640B or eqUivalent

DEMONSTRATION BOARD
CONNECTIONS AND
ADJUSTMENTS
RF'N (RF Input) - An RF signal source With
FM content should be connected here. The
MaXimum frequency IS shown on the graph
(Figure 2). Set the signal generator to FM and
adjust the peak deViation to 3kHz. Set the
modulallon frequency to 1kHz. The RF amplitude can be varied from as low as 2/N to as
high as 1V.
LO'N (Local Oscillator Input) - Should be
455kHz above or below the RF Input at
approximately OdBm With no deViation. ThiS
Input IS normally configured With a Colpitts
crystal OSCillator (see Appendix I), but for
ease of fleXibility we chose to feed the La
externally.
AUDIO (Audio Output) - The audiO recovered from the RF signal can be seen at thiS
pOint. Use an OSCilloscope adjusted to trigger
at the audiO frequency (1 kHz). Remember
that the RF Input must have some FM content
In order to see a signal here

OSCilloscope: Philips PM3243 or eqUivalent
To test the MC3361 demonstration board,
you should carefully follow the Instructions
listed below.
1. Connect a + 5V regulated power supply to
+ Vee·

10. The RF'N frequency can also be varied,
just as long as the LO'N is 455kHz above
or below the RF'N frequency. Figure 4
shows the senSitivity vs. frequency of the
demonstration board.

2. Connect the supply ground to GND.

100

I

75

./~

~

~
z

50

'"w
'"

~

25

--0-

25

50

..0--0"'"'

75

/

V

100

125

150

FREQUENCY (MHz)

Power Supply - The Signetics MC3361 Will
operate With a supply voltage as low as 2.0V

December 1988

9. The Squelch Control CirCUit'S sensitiVity
can be controlled by P1. Adjust P1 to
trigger at the deSired RF input level.

Figure 4_ Sensitivity vs Frequency

4-110

175

200

Il
Signetics Linear Products

Application Note

Using the Signetics MC3361 Demonstration Board

SENSITIVITY VS FREQUENCY
Figure 4 shows the sensitivity of the demonstration board over frequency (Vcc = 5.0V).
The inputs are 50n termInated to suit most
inputs. Note that the inputs are not matched
for anyone frequency; matching the input to

one desired frequency will increase the sensitivity.

APPENDIX I

cy. Figure 5 shows a Colpitts crystal oscillator
tuned to 10.245MHz, which would accommodate an input of 10.7MHz.

The LO can be supplied using a Colpitts
crystal oscillator tuned to the desired frequen-

Figure 5_ Schematic of a Colpitts Crystal Oscillator

December 1966

4-111

AN1992

I'

Signetics Linear Products

Application Note

Using the Signetics MC3361 Demonstration Board

the frequency response of the input as it is on
the demonstration board.

APPENDIX II
The Input has a 50Q termination resistor for
matching the input to most (50Q) signal
sources. This way the device IS not limited to
anyone particular frequency. Figure 6 shows

Figure 7 uses a matching network tuned to
10MHz. The network IS called a capacitor
divider. It basically transforms the input impedance to ma1ch the device input Imped-

ance of 3.3kQ and 2.2pF at 10MHz. The
matched input has an increase gain of 16dBV
over the 50Q termination network.
REF: Ferromagnetic Core DeSign Application &
Handbook, Doug DeMaw.

rOl=""""------

rlh··-----~­
.-f"""'"''

),~,

a. Broadband Termination
-6.0

40

30

,.

-6.2

III

:!?

C 20

w
II)

.." '0
<

-'0

~

-6.4

"~w

-6.6

<

!:;
0
>

/

-7.0

VOLTAGE GAIN

J
~\

-6.8

0.01

"

"
0.1

-

PHASE

1.0

"r-,
10

100

1000

FREQUENCY (MHz)

b. Voltage Transfer Ratio With Broadband Termination
Figure 6. Voltage Transfer Ratio of the Demonstration Board

December 1988

4-112

AN1992

Signetics Linear Products

Application Note

Using the Signetics MC3361 Demonstration Board

AN1992

I

DIAL

I
o

I

Q

I

CONVERSATION
MOOE

STANDBY
MODE

-

PULSE OR
TONE OUT

a. Typical Input Matching Network
20

....... PHASE

............,

100

:;:
m
:!?
z

C

J

0

/ 1\
/ ,
'.
/

~

w

..

!II:z:

w

c
"~-20
0

>

'"
"

-100

/vOLTAGE GAIN

-40
1.0

~
-----

10
FREQUENCY (MHz)

100

b. Typical NetwQrk Voltage Transfer Ratio
Input Matching (at 10.7MHz)
Figure 7

December 1988

4-113

•

Signetics

NE/SA604A
High-Performance Low-Power
FM IF System
Preliminary Specification

Linear Products
DESCRIPTION
The NE/SA604A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal strength
indicator, and voltage regulator. The
NE/SA604A features higher IF bandwidth (25M Hz) and temperature compensated RSSI and limiters permitting
higher performance application compared with the NE/SA604. The NEI
SA604A is available in a 16-lead dual-inline plastic and 16-lead SO (surfacemounted miniature package).

FEATURES
• Low-power consumption 3.3mA
typical
• Temperature compensated
logarithmic Received Signal
Strength Indicator (RSSI) with a
dynamic range in excess of gOdS

• Two audio outputs - muted and
unmuted
• Low external component count;
suitable for crystal/ceramic filters
• Excellent sensitivity: 1.5t.N across
input pins (0.22IN into 50.12
matching network) for 12dS
SINAD (Signal to Noise and
Distortion ratio) at 455kHz
• SA604A meets cellular radio
specifications

APPLICATIONS
• Cellular Radio FM IF
• High performance
communications receivers
• Intermediate freqency
amplification and detection up to
21MHz
•
•
•
•

RF level meter
Spectrum analyzer
Instrumentation
FSK and ASK data receivers

BLOCK DIAGRAM

December 1988

4-114

PIN CONFIGURATION

o and N Packages
IF AMP

IF AMP INPUT

DECOUPLING

IF AMP
DECOUPUNG

IF AMP

MurE INPUT

3

OUTPUT

RSSI OUTPUT

5

LIMITER

MUTE AUDIO
OUTPUT

6

UNMUT~~~~~~

INPUT

LIMITER
OECOUPUNG
10

7

LIMITER
OECOUPLING

QUADRATURE

INPUT
TOP VIEW

Preliminary Specification

Signetics Linear Products

High-Performance Low-Power FM IF System

NE/SA604A

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic DIP

DESCRIPTION

o to +70°C

NE604AN

16-Pin Plastic SO (Surfacemounted miniature package)

o to

NE604AD

+70°C

16-Pin Plastic DIP

-40 to +85°C

SA604AN

16-Pln Plastic SO (Surfacemounted miniature package)

-40 to +85°C

SA604AD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

I

..

UNIT

Vcc

Maximum operating voltage

9

V

TSTG

Storage temperature

-65 to + 150

°C

TA

Operating temperature
NE604A
SA604A

o to 70
-40 to +85

°C
°C

DC ELECTRICAL CHARACTERISTICS TA ~ 25°C; Vcc ~ + 6V unless otherwise stated
PARAMETER

SYMBOL

TEST
CONDITIONS

NE604A

UNIT
Min

Power supply voltage range

4.5

DC current drain

2.5

Mute sWitch input threshold (on)
(off)

1.7

December 1988

SA604A

Typ

3.3

Max

8.0

4.5

4.0

2.5

Typ

3.3

Max

8.0

V

4.0

rnA

1.0

V
V

1.7
1.0

4-115

Min

Signetics Linear Products

Preliminary Specification

High-Performance low-Power FM IF System

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

NEjSA604A

Typical reading at TA = 25°C; Vcc = + 6V unless otherwise stated. IF frequency
= 455kHz; IF level = -47dBm; FM modulation = 1kHz with ± 8kHz peak devlallon.
Audio output with C-message weighted filter and de-emphasis capacitor. Test circUit
Figure 1. The parameters listed below are tested using automatic test equipment to
assure consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the device. Use of an optimized RF layout will improve many
of the listed parameters.
TEST
CONDITIONS

NE604A

SA604A
UNIT

Min

Typ

Max

Min

Max

Input limiting-3dB

Test at Pin 16

AM rejection

80% AM 1kHz

30

34

Recovered audio level

15nF de-emphasis

110

175

Recovered audio level

150pF de-emphasis

530

530

mV rms

RF level -97dBm

16

16

dB

-42

dB

SINAD sensitivity
THD
Signal-to-noise ratio

RSSI output 1

-92

Typ

-35
No modulation for nOise

dBm/50n

-92

250

-42

30

34

80

175

-34

73

dB
260

73

mV rms

dB

RF level = -118dBm

0

160

550

0

160

650

mV

RF level = -68dBm

2.0

2.65

3.0

1.09

2.65

3.1

V

RF level = -18dBm

4.1

4.85

5.5

4.0

4.85

5.6

RSSI range

R4 = 100k Pin 5

RSSI accuracy

R4 = 100k Pin 5

IF input impedance

90
± 1.5
1.4

IF output impedance
Limiter input impedance

90

V
dB

± 1.5

dB

1.6

kn

0.85

1.0

kn

1.4

1.6

kn

1.6

1.4

0.85

1.0

1.4

1.6

Unmuted audio output resistance

58

58

kn

Muted audio output resistance

58

58

n

NOTE:
NE604 data sheets refer to power at 50n Input termination; about 21dB less power actually enters the Internal 1.5k Input.
NE604(SO)
NE604A (1 Sk)/NE60S (l.Sk)
-97dBm
-118dBm
-47dBm
-68dBm
+ 3 dBm
-18dBm
2 The NE60S and NE604A are both derived from the same baSIC die. The NE60S performance plot NE604A.

December 1988

4-116

Signetics Unear Products

Preliminary SpeCification

High-Performance Low-Power FM IF System

NE/SA604A

NEII04A TUT CIRCUIT

r---~--' Q

r
I
I
I

= 20 LOADED

--,
I
I F2
I

L.*~-1

•

OATA
OUTPUT

MUTE
INPUT
NOTES:
C1 10nF +80-20% 63V
C2 100nF ± 10% SOV
C3 100nF ± 10% SOV
C4 100nF ± 10% SOV

K10000~Z5V

RSSI
OUTPUT

Vee

C10 150pF±2% 10DV N1500 Ceramic

Ceramic

Cll lnF±10% l00Y K2000-Y5P Cerarrnc
C12 6 auF ± 20% 25V Tantalum
F1 455kHz Ceramic Fitter Murata SFG455A3
F2 455kHz IF Filter A2549
R1 51fU 1% ~4W Metal Film
R2 1500n±1% 1t4W Metal Film
R3 1500n ± 5% 'taW Carbon CompoSloon
R4 l00ka± 1% 1t4W Metal Film

C5 100nF ± 10% 50Y
C6 10pF±2% 1QOV NPO CeramIC
C7 100nF ± 10% SOV

CB 100nF ± 10% 50Y
C9 15nF ± 10% SOV

SIGNETICS
NESS'! TEST CKT

<:K-)

I

.

0

o~
0-

iOI ~ .,,, etlE> 0 o~
"'-" e",,~
IlO ~~GtIE>:
Ie
1Ri'.' :

31

::: .
'"
.
.
. ~

!J\." sor\
!::\J (1

o
Gel
IV.' ir.
!J\..I
~ ~ o~
. . (Ii(Ii

.

~

00

..

SIGNETICS

NES/II,! TEST CKT (.) ()

0

0(.)
. 'IIi!

""'tI,.,0 00 ()

"'-tC" e""0 000

. i:)

1Ri"

.i!I\."

'1Ri'.'

-'
.. :::

.Q

c:::>

O~

-

~

0 ...

·h

"""

13.::::: 0

0

..

(-)O~ 0

01:) (.x.)

~~.)

c:::;) ~S·)

".

·n~

6 ~oo

.
§()
(·x·\·

'!J\." ~ (.)

'.i'~(·)(·)
..,.
. ..
. . ..
.

~~.~.

~(.:
.. .• 0:')
••
•
e
· ·.. 1;500
0'

<:)

(.) : 1')

1:)(.)

(.)

()

()

00
C0153906

Figure 1. NE604A Test Circuit

December 1988

4-117

Signetics Linear Products

Preliminary Specification

High-Performance low-Power FM IF System

NE/SA604A

Figure 2. Equivalent Circuit

CIRCUIT DESCRIPTION

IF AMPLIFIERS

The NE/SA604A is a very high gain, high
frequency device. Correct operation is not
possible if good AF layout and gain stage
practices are not used. The NE/SA604A can
not be evaluated independent of circuit, components, and board layout. A physiciallayout
which correlates to the electrical limits is
shown in Figure 1. The configurallon can be
used as the basiS for production layout.

The IF amplifier section consists of two loglimiting stages. The first consists of two
differential amplifiers with 39dB of gain and a
small signal bandwidth of 41 MHz (when driven from a 50n source). The output of the first
limiter is a low impedance emitter follower
With 1kn of equivalent series resistance. The
second limiting stage consists of three differential amplifiers with a gain of 62dB and a
small signal AC bandwidth of 28MHz. The
outputs of the final differential stage are
buffered to the Intemal quadrature detector.
One of the outputs is available at Pin 9 to
drive an external quadrature capacitor and LI
C quadrature tank.

The NE/SA604A is an IF signal processing
system suitable for IF frequencies as high as
21.4MHz. The device consists of two limiting
amplifiers, quadrature detector, direct audio
output, muted audio output, and signal
strength indicator (with log output characteristic). The sub-systems are shown in Figure 2.
A typical application with 45MHz Input and
455kHz IF is shown in Figure 3.

December 1988

Both of the limiting amplifier stages are DC
biased using feedback. The buffered output
of the final differential amplifier is fed back to
the Input through 42kn resistors. As shown In
Figure 2 the input Impedance is established

4-118

for each stage by tapping one of the feedback resistors 1.6kn from the input. This
requires one additional decoupling capacitor
from the tap point to ground.
Because of the very high gain, bankwldth and
input impedance of the limiters, there is a very
real potential for instability at IF frequencies
above 455kHz. The basic phenomenon is
shown in Figure 6. Distributed feedback (capacitance, inductance and radiated fields)
forms a divider from the output of the limiters
back to the inputs (including the AF input). If
this feedback divider does not cause attenuation greater than the gain of the forward path,
then oscillation or low level regeneration is
likely. If regeneration occurs, two symptoms
may be present: (I)The ASSI output will be
high with no signal Input (should nominally be
250mV or lower), and (2) the demodulated
output will demonstrate a threshold. Above a
certain input level, the limited signal will begin

Signetlcs Linear Products

Preliminary Specification

High-Performance low-Power FM IF System

NE/SA604A

BFQ455A3

F
7 PF

2ZpF

':'

0.:

1

O.28f.iH

•

:r. '00""
"::'

NE604

'0

,.

IF INPUT (~V) (15OOl1)

'00

'01(

'00.
4'
3.

2.

.

,

NE602 RF INPUT (dam) (SOil)

Figure 3. Typical Application Cellular Radio (45MHz to 455kHz)

42K

v+
15~--~~f'~----------~~1

16o--+--.............,c;...-----I'"

700

t---""''¥-014

Figure 4. First Limiter Bias
to dominate the regeneration, and the de·
modulator will begin to operate in a "normal"
manner.
December 1988

attenuation factor, and (3) reduce the gain.
Gain reduction can effectively be accom·
pllshed by adding attenuation between sta·
ges. This can also lower the input impedance
If well planned Examples of impedancel gain
adjustment are shown In Figure 7 Reduce
gain Will result In reduced limiting sensitIVity.

There are three primary ways to deal with
regeneration: (1) Minimize the feedback by
gain stage isolation, (2) lower the stage input
Impedances, thus Increasing the feedback

4-119

A feature of the NE604A IF amplifiers, which
IS not specified, IS low phase shift. The
NE604A IS fabricated with a 10GHz process
with very small collector capacitance. It is
advantageous in some applications that the
phase shift changes only a few degrees over
a Wide range of signal Input amplitudes.
Additional Information Will be provided in the
upcoming product speclficabon (thiS is a pre·
limlnary specification) when characterization
IS complete.

Signetics Linear Products

Preliminary Specification

NEjSA604A

High-Performance low-Power FM IF System

42K

12

40K

Figure 5. Second Limiter and Quadrature Detector

r---------i...._z,.;......Jr----------l
I
I

r,-

i __z,----'I- - -~-::.-::.-::'-:1-1 '
~

Z,

I

I-,-J- -z, - ~

~L...-~
I
I

I
I

I
I
I

Figure 6. Feedback Paths

Stability Considerations
The high gain and bandwidth of the NE604A
in combination with its very low currents
permit circuit implementation with superior
performance. However, stability must be
maintained and, to do that, every possible
feedback mechanism must be addressed.
These mechanisms are: 1) Supply lines and
grounds, 2) stray layout inductances and
capacitances, 3) radiated fields, and 4) phase
shift. As the system IF increases, so must the
attention to fields and strays. However,
ground and supply loops cannot be overlooked, especially at lower frequencies. Even
at 455kHz, using the test layout in Figure 1,
instability will occur if the supply line is not
decoupled with two high quality RF capacitors, a 0.1!iF monolithic right at the Vee pin,
and a 6.8!iF tantalum on the supply line. An
electroly1ic is not an adequate substitute. At
10.7MHz, a 1IlF tantalum has proven acceptible with this layout. Every layout must be
evaluated on its own merit, don't underestimate the importance of good supply bypass.
At 455kHz, if the layout of Figure 1 or one
substantially similar is used, it is possible to
December 1988

r

directly connect ceramic filters to the input
and between limiter stages with no special
consideration. At frequencies above 2M Hz,
some input impedance reduction is usually
necessary. Figure 7 demonstrates a practical
means.
As illustrated in Figure 8, 430n external
resistors are applied in parallel to the internal
1.6kn load resistors, thus presenting approximately 330n to the filters. The input filter is a
crystal type for narrow-band selectivity. The
filter is terminated with a tank which transforms to 330n. The interstage filter is a
ceramic type which doesn't contribute to
system selectivity, but does suppress wideband noise and stray signal pickup. In wideband 10. 7MHz IFs the input filter can also be
ceramic, directly connected to Pin 16.
In some products it may be impractical to
utilize shielding, but this mechanism may be
appropriate to 10.7MHz and 21.4MHz IF. One
of the benefits of low current is lower radiated
field strength, but lower does not mean nonexistent. A spectrum analyzer with an active
probe will clearly show IF energy with the
probe held in the proximity of the second

4-120

limiter output or quadrature coil. No specific
recommendations are provided, but mechanical shielding should be considered if layout,
bypass, and input impedance reduction do
not solve a stubborn instability.
The final stability consideration is phase shift.
The phase shift of the limiters is very low, but
there is phase shift contribution from the
quadrature tank and the filters. Most filters
demonstrate a large phase shift across their
passband (especially at the edges). If the
quadrature detector is tuned to the edge of
the filter passband, the combined filter and
quadrature phase shift can aggravate stability. This is not usually a problem, but should
be kept in mind.

Quadrature Detector
Figure 5 shows an equivalent circuit of the
NE604A quadrature detector. It is a multiplier
cell similar to a mixer stage. Instead of mixing
two different frequencies, it mixes two signals
of common frequency but different phase.
Internal to the device, a constant amplitude
(limited) signal is differentially applied to the
lower port of the multiplier. The same signal is
applied single ended to an external capacitor
at Pin 9. There is a 90' phase shift across the
phase shift across the plates of this capacitor,
with the phase shifted signal applied to the
upper port of the multipler at Pin 8. A quadrature tank (parallel L/C network) permits frequency selective phase shifting at the IF
frequency. This quadrature tank must be
returned to ground through a DC blocking
capacitor.

Signetics Linear Products

Preliminary Specification

NE/SA604A

High-Performance low-Power FM IF System

fll>

HIGH IMPEDANCE

1-----l

L____
I
I

I
I
I

I
_
L ___ ;_

_~

I
I
I
I
I
:

I

I
I
I ________________
":"
JI

7a. Terminating High Impedance Filters with Transformation to Low Impedance

7b. Low Impedance Termination and Gain Reduction
Figure 7. Practical Termination

430

430

604A

Figure 8. Crystal Input Filter with Ceramic Interstage Filter

December 1988

4-121

Signetics linear Products

Preliminary Specification

NE/SA604A

High-Performance Low-Power FM IF System

From the above equation, the phase shift
between nodes 1 and 2, or the phase across
C3 will be:

NOTE:.:lw is the deviation frequency from
the carrier W1.
Ref. Krauss, Raab, Bastian; Solid State Radio

£ng.; Wiley, 1980, p.311. Example: At 455kHz
IF, with ± 5kHz FM deviation. The maxImin
normalized frequency will be
455 ± 5kHz

--.,.--= 1.010 or 0.990
455

Go to the  vs. normalized frequency curves
(Figure 10) and draw a vertical

TC2:l150S

Figure 9.
The loaded Q of the quadrature tank impacts
three fundamental aspects of the detector:
Distortion, maximum modulated peak devia·
tlon, and audio output amplitude. Typical
quadrature curves are illustrated In Figure 10.
The phase angle translates to a shift in the
multiplier output voltage.
Thus a small devIation gives a large output
with a high Q tank. However, as the deviation
from resonance increases, the nonlinearity of
the curve increases (distortion), and, with too
much deviation, the signal will be outside the
quadrature region (limiting the peak deviation
which can be demodulated). If the same peak
deviation IS applied to a lower Q tank, the
deviation will remain in a region of the curve
which is more linear (less distortion), but
creates a smaller phase angle (smaller output
amplitude). Thus the Q of the quadrature tank
must be tailored to the design. Basic equa·
tions and an example for determining Q are
shown below. This explanation includes first
order effects only.

Frequency Discriminator Design
Equations for NE604A
Cs

vo=---o

(1 a)

cp+cs

_____ 0

S

1

Q1

'1r2 and the

shift is

= W1,

The curves with Q = 100, Q = 40 are not
linear, but Q = 20 and less shows better
linearity for this application. Too small Q
decreases the amplitude of the discrimination
FM signal. (Eq.6)

the phase

response is close to

a straight line with a slope of

-Choose a Q = 20.
The internal R of the 604A is 40k. From Eq.
1c, and then 1b, it results that

The signal Vo would have a phase shift
of

[~-( :1 )w ] with respect to the VIN.

IfVIN = A Sin wt

(3)

-Vo=A

Multiplying the two signals in the mixer, and
low pass filtering yields:
VIN

° Vo = A2 Sin wt

(4)

after low pass filtering

-Your
(lb)

= R (Cp + Cs) w1

(lC)

COS

For

=!2 A2

(5)

[~ _( : 1 ) w ] = ~ A2 Sin ( :1 ) w

2Q1w

1r

w1

2

--«-

Which is the discriminated FM output.
December 1988

= 1.01.

Cp + Cs = 174pF and L = 0.7mH.
A more exact analysis including the source
resistance of the previous stage shows that
there is a series and a parallel resonance in
the phase detector tank. To make the parallel
and series resonances close, and to get
maximum attenuation of higher harmonics at
455kHz IF, we have found that a Cs = 10pF
and Cp = 164pF (commercial values of
150pF or 180pF may be practical), will give
the best results. A variable inductor which
can be adjusted around 0.7mH, should be
chosen and optimized for minimum distortion.
(For 10.7MHz, a value of Cs = 1pF is recommended.)

Audio Outputs

v' L(Cp + Cs)

where w1 =

It is notable that at w

VN

1+~+(W1)2
Q1S

straight line at ( : )

Figure 10. Is the plot of  vs ( : )

4-122

Two audio outputs are provided. Both are
PNP current-to-voltage converters with 55kn
nominal internal loads. The unmuted output is
always actIve to permit the use of signaling
tones in systems such as cellular radio. The
other output can be muted with 70dB typical
attenuation. The two outputs have an internal
180· phase difference.
The nominal frequency response of the audio
outputs is 300kHz. This response can be
increased with the addition of external resistors from the output pins to ground in parallel
with the internal 55k resistors, thus lowering
the output time constant. Since the output
structure is a current-to-voltage converter
(current is driven into the resistance, creating
a voltage drop), adding external parallel resis-

Preliminary Specification

Signetlcs Linear Products

NEjSA604A

High-Performance Low-Power FM IF System

tance also has the effect of lowering the
output audio amplitude and DC level.
This technique of audio bandWidth expansion
can be effective In many applications such as
SCA receivers and data transceivers Because the two outputs have a 180 0 phase
relallonshlp, FSK demodulation can be accomplished by applYing the two outputs differentially across the Inputs of an op amp or
comparator. Once the threshold of the reference frequency (or "no-Signal" condition)
has been established, the two outputs will
shift In opposite dlrecllons (higher or lower
output voltage) as the Input frequency shifts
The output of the comparator will be the
logical output. The choice of op amp or
comparator will depend on the data rate, With
high IF frequency (10 MHz and above), and
wide IF bandWidth (L/C filters) data rates In
excess of 4Mbaud are pOSSible.

RSSI
The "received Signal strength Indicator", or
RSSI, of the NES04A demonstrates monotonIC loganthmlc output over a range of 90dB.
The Signal strength output IS denved from the
summed stage currents In the limiting amplifiers It IS essentially Independent of the IF
frequency Thus, unfiltered Signals at the

limiter Inputs, SpUriOUS products, or regenerated Signals will mamfest themselves as RSSI
outputs An RSSI output of greater than
250mV With no Signal (or a very small Signal)
applied, IS an Indlcallon of pOSSible regeneration or OSCillation.

clally true With high IF frequencies which
require insertion loss or Impedance reduction

for stabl lity.
At low frequencies the RSSI makes an excellent logarithmic AC voltmeter.
For data applicallOns the RSSI IS effective as
an amplitude shift keyed (ASK) data slicer. If
a comparator IS applied to the RSSI and the
threshold set slightly above the no Signal
level, when an In band Signal IS received the
comparator Will be sliced. Unlike FSK demodulallOn, the maximum data rate IS somewhat
limited. An Internal capacitor limits the RSSI
frequency response to about 100kHz At high
data rates the rise and fall times Will not be
symmetrical.

In order to achieve optimum RSSI linearity,
there must be a 12dB Insertion loss between
the first and second limiling amplifiers With a
typical 455kHz ceramic filter, there IS a nominal 4dB Insertion loss In the filter An addillonal SdB IS lost In the Interface between the
filter and the Input of the second limiter. A
small amount of additional loss must be
Introduced With a tYPical ceramic filter. In the
test CIrCUIt used for cellular radiO applications
(Figure 3) the optimum linearity was achieved
With a 5.1 Q resistor from the output of the
first limiter (Pin 14) to the Input of the Interstage filter With thiS resistor from Pin 14 to
the fliter, sensitivity of 0.25JlV for 12dB SINAD was achieved. With the 3.SkQ reSistor,
sensitivity was optimized at 0.22JlV for 12dB
SINAD With minor change In the RSSI linearity.

The RSSI output IS a current-to-voltage converter Similar to the audio outputs. However,
an external resistor IS reqUIred With a 91 kQ
reSistor, the output characteristic IS 0.5V for a
10dB change In the Input amplitude.

Additional Circuitry
Internal to the NES04A are voltage and current regulators which have been temperature
compensated to maintain the performance of
the deVice over a Wide temperature range.
These regulators are not acceSSible to the

Any application which reqUires optimized
RSSI linearity, such as spectrum analyzers,
cellular radiO, and certain types of telemetry,
Will reqUIre careful attention to limiter Interstage component selecllOn. This Will be espe-

user.

~r------------------r-----------------.r-----------------'------------------'
Q =

100

175~_~_~_~_~_~_~_~_~_~_~.~:;.-;:.t=~----~~-=~~~-----------------1------------------1

150F===~--~~~-------f~~~~~~~,~~--~------------------~------------------~
~-"-

125r------.----.---.~-~·--~~--~----~~~--~~~T\--+_--------------------_4----------------------~
Q= 10"-¢ 100r-------------------r---------~~~~~------------------_+------------------_1

25r--------------------t--------------------r-------~~~~~~~~~~-----------==4

~.~95~-------------------:oj.9l75~--------------------,1.0----------------~=:::,.J02:~~.~::~~~-=-:.=~=-:.-=-:.:~::~:~~.~-~.~-~,~:~
Figure 10. Phase vs. Normalized IF Frequency

w

-0.)1

December 1988

4·123

~

Dow

1 + -0.)1

I
i

I

II

AN1991

Signetics

Audio Decibel Level Detector
With Meter Driver
Application Note

Linear Products

Author: Robert J. Zavrel Jr.

DESCRIPTION
Although the NE604 was designed as an RF
device intended for the cellular radio market.
it has features which permit other design
configurations. One of these features IS the
Received Signal Strength Indicator (RSSI). In
a cellular radio. this function is necessary for
continuous monitoring of the received signal
strength by the radio's microcomputer. This
circuit provides a logarithmic response proportional to the input signal level. The NE604
can provide this logarithmic response over an
BOdS range up to a 15MHz operating frequency. This paper describes a technique which
optimizes this useful function within the audio
band.
A sensitive audio level indicator circuit can be
constructed using two integrated circuits: the
NE604 and NE532. This circuit draws very
little power (less than 5mA with a single 6V
power supply) making it ideal for portable
battery operated equipment. The small size
and low-power consumption belie the BOdS
dynamic range and 10.51LV sensitivity.

The RSSI function reqUIres a DC output
voltage which IS proportional to the 10glO of
the input signal level. Thus a standard 0 - 5
voltmeter can be linearly calibrated In decibels over a single BOdS range. The entire
circuit IS composed of 9 capacitors and two
resistors along with the two ICs. No tuning or
calibration is required in a manufacturing
setting.
The Audio Input vs Output Graph shows that
the circuit is within 1.5dS tolerance over the
BOdS range for audio frequencies from 100Hz
to 10kHz. Higher audio levels can be measured by placing an attenuator ahead of the
input capacitor. The input impedance is high
(about 50k). so lower impedance terminations
(50 or 600n) will not be affected by the Input
impedance. If very accurate tracking is required « 0.5dS accuracy). a 40 or 50dS
segment can be "selected". A range switch
can then be added with appropriate attenuators If more than 40 or 50dS dynamic range is
reqUIred.

OdB=300mVp.T.p._L ,I
SOLID LINE INfCATES
IDEAL SLOPE

)
,,)

1J

DOTTED LINE.
INDICATES
MEASURED SLOPE
Vcc=6V

.I

~

~

~~

-o 11
-100

"/

-80

"

-60

-40

-20

AUDIO INPUT (dB)

.---------------------~----__o+6V

18

NE804

+
330FI-::+6V

Figure 1

December 19BB

4-124

Signetics Linear Products

Application Note

Audio Decibel Level Detector With Meter Driver

There are two amplifier sections in the 604
with 2 and 3 stages in the first and second
sections respectively. Each stage outputs a
sample current to a summing cirCUIt. The
summing Circuit has a current mirror which
appears at Pin 5. This current IS proportional
to the 10glo of the Input audiO signal. A
voltage IS dropped across the 100k resistor
by the current, and a 0.1 /IF capacitor IS used
to bypass and filter the output signal. The 532
op amp is used as a buffer and meter driver,
although a digital voltmeter could replace
both the op amp and the meter shown The
rest of the capacitors are used for power
supply and amplifier Input bypaSSing.
The RC cirCUit between Pins 14 and 12 forms
a low-pass filter which can be adjusted by
changing the value of Cl RaiSing the capacl-

December 1988

tance will lower the cut-off frequency and also
lower the zero signal output restong voltage
(about 0.6V). Lowering the capacitance value
Will have the opposite effect with some reduction in dynamiC range, but Will raise the
frequency response. The 2kn resistor value
provides the near-Ideal inter-stage loss for
maximum RSSI linearity. C2 can also be
changed. The trade-off here IS between output damping and ripple. Most analog and
digital metering methods will tend to cancel
the effects of small or moderate ripple voltages through Integration, but high ripple voltages should be avoided.
A second op amp IS used with an optoonal
second filter. ThiS filter has the advantage of
a low Impedance signal source by virtue of
the first op amp. Again, a trade-off eXists

4-125

AN1991

between meter damping and ripple attenuation. If very low ripple and low damping are
both required, a more complex active lowpass filter should be constructed.
Some applications of this circuit might include:
1. Portable acoustic analyzer
2. Microphone tester
3. AudiO spectrum analyzer
4. VU meters
5. S-meter for direct conversion radiO
receiver
6. AudiO dynamic range testers
7. AudiO analyzers (THO, noise, separation,
response, etc.)

•

AN1993

Signetics

High Sensitivity Applications of
low-Power RFjlF Integrated
Circuits
Linear Products

Application Note

ABSTRACT
This paper discusses four high sensitivity
receivers and IF (Intermediate Frequency)
strips which utilize intermediate frequencies
of 10.7MHz or greater. Each circuit utilizes a
low-power VHF mixer and high-performance
low-power IF strip. The circuit configurations
are
1. 45 or 49MHz to 10.7MHz narrowband,
2. 90MHz to 21.4MHz narrowband,
3. 100MHz to 10.7MHz wideband, and
4. 152.2MHz to 10.7MHz narrowband.
Each circuit is presented with an explanation
of component selection criteria, (to permit
adaptation to other frequencies and bandwidths). Optional configurations for local oscillators and data demodulators are summarized.

quired extensive gain stage Isolation to avoid
instability and very high current consumption
to get adequate amplifier gain bandwidth. By
enlightened application of two relatively new
low power ICs, Signetics NE602 and
NE604A, it is possible to build highly producible IF strips and receivers with input frequencies to several hundred megahertz, IF frequencies of 10.7 or 21.4MHz, and sensitivity
less than 2p.V (in many cases less than 1p.V).
The Signetics new NE605 combines the function of the NE602 and the NE604A. All of the
circuits described in this paper can also be
implemented with the NE605. The NE602 and

NE604A were utilized for this paper to permit
optimum gain stage isolation and filter location.

THE BASICS
First let's look at why it is relevant to use a
10.7 or 21.4MHz intermediate frequency.
455kHz ceramic filters offer good selectivity
and small size at a low price. Why use a
higher IF? The fundamental premise for the
answer to this question is that the receiver
architecture is a hetrodyne type as shown in
Figure 1.

AlIOtO

ANDiOR
DATA

INTRODUCTION
Traditionally, the use of 10.7MHz as an intermediate frequency has been an attractive
means to accomplish reasonable image rejection in VHF/UHF receivers. However, applying significant gain at a high IF has re-

TCZI'' '
Figure I, Basic Hetrodyne Receiver

IMAGE

10.7 MHz IF

0

0

iii'
:!!.
~ -10

!

z~
~-ao

z~

455kHz IF

~ -10

~-2O

iC
II:

e

~

!

!
...

~-30

~-30

II:

IE

-20

-10
0
+10
11 PRESELECTOR FREQ (MHz)

+20

-20

-10
0
+10
11 PRESELECTOR FREQ (MHz)

Figure 2. Effecte of Preaelectlon on Images
December 1988

4-126

+20

Application Note

Signetics Linear Products

High Sensitivity Applications of
low-Power RF jlF Integrated Circuits

AN1993

local oscillator (LO) frequency and the preselector frequency.
AUDIO

ANDIOR
DATA

Figure 3. Dual Conversion

I-------~----------l

I

I

r-~-~~~~~---~
I
I

~
I
I

~

I

I
I

I

I
I
I

The reality is that there are always two
frequencies which can combine with the LO:
The pre-selector frequency and the "Image"
frequency. Figure 2 shows two hypothetical
pre-selection curves. Both have 3dB bandwidths of 2MHz. This type of pre-selection IS
typical of consumer products such as cordless telephone and FM radiO. Figure 2A
shows the attenuation of a low side Image
with 10.7MHz. Figure 2B shows the very
limited attenuation of the low Side 455kHz
Image.
If the Single conversion architecture of Figure
1 were implemented with a 455kHz IF, any •
Interfering Image would be received almost a s ,
well as the desired frequency. For thiS rea•
son, dual conversion, as shown In Figure 3,
has been popular.
In the application of Figure 3, the first IF must
be high enough to permit the pre-selector to
reject the Images of the forst mixer and must
have a narrow enough bandwidth that the
second mixer images and the ontermod products due to the forst mixer can be attenuated
There's more to It than that, but those are the
basics. The multiple converSion hetrodyne
works well, but, as Figure 3 suggests, compared to Figure 2 it IS more complicated. Why,
then, don't we use the approach of Figure 2?

Figure 4. Feedback Paths

THE PROBLEM
Historically there has been a problem: Stabllity' CommerCially available Integrated IF amplifiers have been limited to about 60dB of
gain. Higher discrete gain was possible If
each stage was carefully shielded and bypassed, but this can become a nightmare on
a production line. With so little IF gain available, in order to receive signals of less than
10jlV It was necessary to add RF gaon and
this, in turn, meant that the mixer must have
good large signal handling capability. The RF
gain added expense, the high level mixer
added expense, both added to the potential
for Instabllitoes, so the multiple converSion
started looking good again.
But why is Instability such a problem In a high
gain high IF strip? There are three baSIC
mechanisms. First, ground and the supply line
are potentially feedback mechanisms from
stage-to-stage in any amplifier. Second, output pins and external components create
fields which radiate back to inputs. Third,
layout capacitances become feedback mechanisms. Figure 4 shows the fields and capacItances symbolically.

ill

GND

Figure 5. NE602 Equivalent Circuit
A pre·selector (bandpass in this case) precedes a mixer and local oscillator. An IF fdter
December 1988

follows the mixer. The IF filter is only supposed to pass the difference (or sum) of the

4-127

If ZF represents the impedance assOCiated
with the circuit feedback mechanisms (stray
capacitances, inductances and radiated
fields), and Z'N IS the equivalent input imped-

Signetics Linear Products

Application Note

High Sensitivity Applications of
low-Power RF jlF Integrated Circuits

AN1993

Figure 6. NE604A Equivalent Circuit

h,.........--o~~'o

TC23&20S

Figure 7. Symbolic Circuit
ance, a divider is created. This divider must
have an attenuation factor greater than the
gain of the amplifier if the amplifier is to
remain stable.
• If gain is increased, the input-to-output
isolation factor must be increased.
• As the frequency of the signal or amplifier
bandwidth increases, the impedance of the
layout capacitance decreases thereby reducing the attenuation factor.

bandwidth, the amount of current in the
amplifiers needed to be quite high. The
CA3089 operates with 25mA of typical quiescent current. Any currents which are not
perfectly differential must be carefully bypassed to ground. The higher the current, the
more difficult the challenge. And limiter outputs and quadrature components make excellent field generators which add to the
feedback scenario. The higher the current,
the larger the field.

The layout capacitance is only part of the
issue. In order for traditional 10. 7MHz IF
amplifiers to operate with reasonable gain
December 1988

4-128

THE SOLUTION
The NE602 is a double balanced mixer suitable for input frequencies in excess of
500MHz. It draws 2.5mA of current. The
NE604A is an IF strip with over 1OOdB of gain
and a 25MHz small signal bandwidth. It draws
3.SmA of current. The circuits in this paper
will demonstrate ways to take advantage of
this low current and 7SdB or more of the
NE604A gain in receivers and IF strips that
would not be possible with traditional integrated circuits. No special tricks are used, only
good layout, impedance planning and gain
distribution.

----~----------

Application Note

Signetics Linear Products

High Sensitivity Applications of
Low-Power RF jlF Integrated Circuits

LO
,...
...,

-

THE IF STRIP

u,...

...,

AN 1993

SIGNETICS
NE6~2/6~~

DEMO BOARD

The baSIC functions of the NE604A are ordinary at first glance: limiting IF, quadrature
detector, signal strength meter, and mute
switch. However, the performance of each
of these blocks Is superb. The IF has
100dB of gain and 25MHz bandwidth. This
feature will be exploited in the examples. The
signal strength indicator has a 90dB log
output characteristic with very good lineanty.
There are two audio outputs with greater than
300kHz bandwidth (one can be muted greater
than 70dB). The total supply current is typically 3.5mA. This is the other factor which
permrts high gain and high IF.
Figure 6 shows an equivalent circuit of the
NE604A. Each of the IF ampl~iers has a
1.6kn input Impedance. The input impedance
IS achieved by splitting a DC feedback bias
resistor. The input impedance will be mampulated in each of the examples to aid stability.

BASIC CONSIDERATIONS
In each of the Circuits presented, a common
layout and system methodology is used. The
basic circuit is shown symbolically In Figure 7.

Figure 8. Circuit Board Layout

THE MIXER
The NE602 is a low power VHF mixer with
built-in oscillatbr. The equivalent circuit is
shown in Figure 5. The basic attributes of this
mixer include conversion gain to frequencies
greater than 500MHz, a noise figure of 4.6

~~

z 20f-+_ _,

~

.. W

:lill;
w

>

2.0

Ii -

iii
oil

1.5

-70

a: 40

1.0

-80

10.5

10.7
FREQUENCY (MHz)

10.9

0.5 (VOLTS)

-120 -110

-100

-90

-80

-70
-60
-so -40
RF INPUT (dBm) (500)

0

-30

-20

-10

0

Figure 10. Passband Relationship
+ 45MHz RF input
+55.7MHz LO
(OdBm)

+10.7MHz iF
+ 15kHz iF BW
+ 7kHz deviation

Figure 11. VHF or UHF 2nd Conversion (Narrow Band)

December 1988

4-130

Signetlcs Linear Products

Application Note

High Sensitivity Applications of
low-Power RF jlF Integrated Circuits

AN1993

LO INPUT

220pF

430

@-Tt

Ll"n

•
ASSI
MUTE

<6V

AUDIO

DATA

Figure 12. NE602/604A Demonstration Circuit with RF Input of 90MHz and IF of 21.4MHz ± 7.5kHz
As mentioned. a single layout was used for
each of the examples. The board artwork is
shown in Figure B. Special attention was
given to: (1) Creating a maximum amount of
ground plane with connection of the component side and solder side ground at locations
all over the board; (2) careful attention was
given to keeping a ground ring around each of
the gain stages. The objective was to provide
a shunt path to ground for any stray signal
which might feed back to an input; (3) leads
were kept short and relatively wide to mini·
mize the potential for them to radiate or pick
up stray signals; finally (and very important).
(4) RF bypass was done as close as possible
to supply pins and inputs. with a good (10"F)
tantalum capacitor completing the system
bypass.

AUDIO

~--------------------------;Y
4.0
3.5
3.0

G.5 (IIIOLTS)

EXAMPLE: 45MHz to 10.7MHz
NARROWBAND

-120 -110 -100

As a first example. consider conversion from
45MHz to 10.7MHz. There are commercially
available filters for both frequencies so this is
a realistic combination for a second IF in a
UHF receiver. This circuit can also be applied
to cordless telephone or short range commu·
nications at 46 or 49MHz. The circuit is shown
in Figure 9.
The 10.7MHz filter chosen is a type commonly available for 25kHz channel spacing. It has
a 3dB bandwidth of 15kHz and a termination
requirement of 3k{U2pF. To present 3kn to
Decamber 19BB

-90

-811

-70 -60 -60 ~
RF INPUT (dBm) (son)

.90MHz RF Input
.6B.6MHz LO
(OdBm)

-3CI

-20

-10

.21.4MHz IF
• 15kHz IF BW
.7kHz deviation

Figure 13. UHF Second Conversion (Narrow Band) or VHF
Single Conversion (Narrow Band)
the input side of the filter. a 1.5kn resistor
was used between the NE602 output (which

4-131

has a 1.5kn impedance) and the filter. Layout
capacitance was close enough to 2pF that no

Application Note

Signetics Linear Products

High Sensitivity Applications of
low-Power RFjlF Integrated Circuits

AN1993

10.7 MHz



3 . 42

PIN '4

i3.38

13.34 ~
3.3~ 10

-

j......-

~

j...-

I--"

+--""

I---""V

I-""
~~ f-

0

'0 20 30 40 50 60 70
AMBIENT TEMPERATURE ee)

• 152.2MHz RF Input
• 141.5MHz LO
(OdBm)

80

.10.7kHz IF
• 15kHz IF BW
• 7kHz deviation

Figure 17. VHF Single Conversion (Narrow Band)
The performance of this circuit is presented in
Figure 11. The -12dB SI NAD (ratio of Signal
to Noise And Distortion) was achieved with a
0.6/J-V input.

4-133

EXAMPLE: 90MHz to 21.4MHz
NARROWBAND
This second example, like the first, used two
frequencies which could represent the inter·
mediate frequencies of a UHF receiver. This
circuit can also be applied to VHF single
conversion receivers if the sensitivity is ap·
propriate. The circuit is shown in Figure 12.

Signetics Uneer Products

Application Note

High Sensitivity Applications of
Low-Power RF/IF Integrated Circuits
Most of the fundamentals are the same as
explained In the first example. The 21 4MHz
crystal filter has a 1.5kn/2pF terminatIon
requirement so direct connection to the output of the NE602 is possible. With strays
there is probably more than 2pF In thIs cIrcuit,
but the performance IS good nonetheless.
The output of the crystal fIlter IS terminated
with a tuned Impedance-step-down transformer as in the prevIous example. Interstage
fIltering IS accomplIshed wIth a 1kn 330 stepdown ratio. (Remember, the output of the first
limIter is 1kn and a 430n resIstor has been
added to make the second lImiter Input
330n). A DC blockIng capacItor IS needed
from the output of the fIrst limIter The board
was not laId out for an interstage transformer,
so an "XACTO" knife was used to make
some minor mods. FIgure 13 shows the
performance. The +12dB SINAD was wIth
1.61lV Input.

a. Fundamental
Colpitts Crystal

if

EXAMPLE: 100MHz to 10.7MHz
WIDEBAND
This example represents three possIble applicatIons: (1) low cost, sensItIve FM broadcast
receIvers, (2) SCA (SubsidIary Communications AuthorizatIon) receivers and (3) data
receivers. The cIrcUIt schematIc IS shown In
Figure 14. WhIle thIs example has the greatest diversIty of application, It is also the
sImplest. Two 10.7MHz ceramic filters were
used. The fIrst was directly connected to the
output of the NE602. The second was dIrectly
connected to the output of the first IF limIter.
The secondary SIdes of both fIlters were
termInated wIth 330n as In the two prevIous
examples. While the filter bandpass skew of
thIs sImple single conversion receiver mIght
not be tolerable in some applicatIons, to a
first order the results are excellent. (Please
note that sensitIvity is measured at + 20dB In
this wideband example.) Performance IS illustrated in Figure 15. +20dB SINAD was measured with 1.81lV input.

EXAMPLE: 1S2.2MHz to 10.7MHz
NARROWBAND
In this example (see FIgure 16) a sImple,
effective, and relatively sensitIve sIngle conversion VHF receIVer has been implemented.
All of the circuit philosophy has been descnbed in prevIous examples. In this CIrcuit,
tuned-transformed termination was used on
the input and output sides of the crystal fIlter.
Performance is shown in Figure 17. The
+12dB SINAD sensItivity was 0.9IlV.

OSCILLATORS
The NE602 contains an oscIllator transistor
which can be used to frequencies greater
December 1988

AN 1993

b. Overtone
Colpitts Crystal

-=

TC23670S

d. Hartley
LIC Tank

c. Overtone
Butler Crystal

ill

3

'::"
TC23550S

e. Colpitts
LIC Tank

Figure 18. Oscillator Configurations
than 200M Hz Some of the pOSSIble confIguratIons are shown In Figures 18 and 19.

20kn are acceptable values. Too small a
resIstance can upset DC bIas (see references).

LIC
When using a synthesIzer, the LO must be
externally buffered Perhaps the sImplest approach IS an emitter follower wIth the base
connected to PIn 7 of the NE602. The use of
a dual-gate MOSFET will improve performance because It presents a faIrly constant
capacitance at Its gate and because It has
very high reverse Isolanon.

CRYSTAL
With both of the ColpItts crystal confIguratIons, the load capacItance must be speCIfIed.
In the overtone mode, thIs can become a
sensitive Issue sInce the capacitance from
the emItter to ground IS actually the equivalent capaCItive reactance of the harmonic
selection network. The Butler oscillator uses
an overtone crystal speCIfied for senes mode
operation (no parallel capacItance). It may
reqUIre an extra Inductor (La) to null out Co of
the crystal, but otherwIse IS fairly easy to
Implement (see references).
The OSCIllator transistor is bIased wIth only
220jLA. In order to assure oscillation in some
configuratIons, It may be necessary to increase transconductance wIth an external
resIstor from the emitter to ground. 10kn to

4-134

DATA DEMODULATION
It is possible to change any of the examples
from an audIO receiver to an amplitude shllt
keyed (ASK) or frequency shift keyed (FSK)
receIver or both WIth the addItIon of an
external op amp(s) or comparator(s). A SImple example IS shown In FIgure 20. ASK
decoding IS accomplished by applying a comparator across the receIved SIgnal strength
indIcator (RSSI) The RSSI will track IF level
down to below the limIts of the demodulator
(-120dBm RF input in most of the examples).
When an in-band signal IS above the comparator threshold, the output logic level will
change.
FSK demodulatIon takes advantage of the
two audIO outputs of the NE604A. Each IS a
PNP current source type output with 180·
phase relationshIp. With no SIgnal present,
the quad tank tuned for the center of the IF
passband, and both outputs loaded with the
same value of capacitance, if a signal IS
receIved whIch IS frequency shIfted from the
IF center, one output voltage WIll Increase
and the other will decrease by a correspondIng absolute value. Thus, if a comparator IS
dIfferentially connected across the two out-

Application Note

Signetics Linear Products

High Sensitivity Applications of
Low-Power RF jlF Integrated Circuits
puts, a frequency shift in one direction will
drive the comparator output to one supply
rail, and a frequency shift in the opposite

AN1993

direction will cause the comparator output to
swing to the opposite rail. Using this technique, and LIC filtering for a wide IF band-

width, NRZ data at rates greater than 4Mb
have been processed with the new NE605.

vee
0.8

-

2K

NE802

t1E
I

0.01

0.001

2-_

l

0.01

18K

FROM
SYNTH LOOP
FILTER

MV2105
OREQUIV

* Permits Impedance match of NE602 output of 1.8k/BpF to 3 Ok filter Impedance
• • Choose for Impedance match to

Figure 19. Typical Varactor Tuned Application

December 1988

JJ

II

'lin'

oo,.H

0.001

4-135

Signetics linear Products

Application Note

High Sensitivi1y Applications of
Low-Power RF jlF Integrated Circuits

AN 1993

10.7 MHz
CERAMIC
FILTER

LO INPUT

 500MHz

• Mixer conversion power gain of
13dB at 45MHz
• Mixer noise figure of 4.6dB at
45MHz
• XTAL oscillator effective to
150MHz (L.C. OSCillator to 1GHz
local oscillator can be injected)
• 102dB of limiter gain
• 25MHz limiter small signal
bandwidth
• Temperature compensated
logarithmic Received Signal
Strength Indicator (RSSI) with a
dynamic range in excess of 90dB
• Two audio outputs - muted and
unmuted
• Low external component count;
suitable for crystallceramic/LC
filters

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

20-P,n Plastic DIP

DESCRIPTION

O'G to +70'G

NE605N

20-Pin Plastic SOL (Surface·
mounted)

O'G to +70'G

NE605D

20-Pin Plastic DIP

-40 to +85'G

SA605N

20-Pin Plastic SOL (Surfacemounted)

-40 to +85'G

SA605D

BLOCK DIAGRAM

PIN CONFIGURATION
0 1 and N Packages
RFIN

1

RF BYPASS

2

CRYSTAL OSC

CRYSTAL OSC

4

17

RSSIOUT

LIMITER IN

MUTED
AUDIO OUT

A~~~cl'6ij~
QUAORATUR,NE

LIMITER
DECOUPLING

~rc'b'[JI.LING

9
0 _ _ _ _r--.

NOTE,
1 Large SO (SOL) package only

• Excellent sensitivity: O.22J1V into
50n matching network for 12dB
SINAD (Signal to Noise and
Distortion ratio) for 1kHz tone
with RF at 45MHz and IF at
455kHz
• SA605 meets cellular radio
specifications
• ESD hardened

APPLICATIONS
• High performance
communications receivers
• Cellular Radio FM IF
• Single conversion VHF/UHF
receivers
SCA receivers
RF level meter
Spectrum analyzer
Instrumentation
FSK and ASK data receivers

• Log amps
• Wideband low current
amplification

4-137

LIMITER
OUT

TOP VIEW

•
•
•
•
•

December 1988

:rE~~~LlNG

18 IFAMPOUT

Preliminary Specification

Signetics Unear Products

NE/SA605

High-Performance Low Power Mixer FM IF System

ABSOLUTE MAXIMUM RATINGS
PARAMETER

RATING

Vee

Maximum operating voltage

9

V

TSTG

Storage temperature

-65 to +150

°C

TA

Operating temperature

SYMBOL

NE605
SA605

UNIT

°C
°C

o to + 70
-40 to + 85

DC ELECTRICAL CHARACTERISTICS

TA = 25°C; Vee = + 6V, unless otherwise stated
LIMITS
TEST
CONDITIONS

PARAMETER

SYMBOL

Min
Vee

Power supply voltage range

4.5

DC current drain

5.1

Mute swrtch Input threshold (on)
(off)

1.7

AC ELECTRICAL CHARACTERISTICS

SA60S

NE60S
Typ

Max

Min

8.0

4.5

5.7

6.5

4.55

UNIT

Typ

Max
8.0

V

5.7

6.55

mA

1.0

V
V

1.7
1.0

TYPical reading at TA = 25°C; Vee = + 6V unless otherwise stated. AF frequency
= 45MHz + 14.5dBV AF Input step-up; AF frequency = 455kHz, A17 = 5.1k; AF
level = 45dBm; FM modulation = 1kHz with ± 8kHz peak deviation. Audio output with
C-message weighted filter and de-emphasIs capaCItor. Test circuit Figure 1. The
parameters listed below are tested uSing automatic test equipment to assure
consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the deVice. Use of an optimized AF layout will Improve many
of the listed parameters.
LIMITS

SYMBOL

TEST
CONDITIONS

PARAMETER

SA605

NE60S
Min

Typ

Max

Min

Typ

UNIT
Max

Mlxer/Osc section (ext LO = 300mV)
fiN

Input signal frequency

500

500

MHZ

fose

Crystal oscillator frequency

150

150

MHz

NOise figure at 45MHz

5.0

5.0

dB

-10

-10

dBm

= 45.0;

fl

Conversion power gain

Matched 14.5dBV step-up
son source

10.5

Single-ended input

3.5

AF Input resistance

f2

= 45.06MHz

Third-order intercept pOint

13
-1.7
4.7
3.5

AF input capacitance
(Pin 20)

Mixer output resistance

1.3

14.5

10
3.0

4.0

15

dB
dB
kn

4.7
3.5

1.25

1.5

13
-1.7

4.0

pF

1.5

kn
dB

IF section
IF amp gain

SOn source

39.7

39.7

limiter gain

son source

62.5

62.5

dB

Test at Pin 18

-113

-113

dBm

Input limiting -3dB, A17 = 5.1k
AM rejection
Audio level, A l o = lOOk
Unmuted audio level, All
SINAD sensitivity
THD

Total harmOniC distortion

SIN

Signal-to-noise ratio

December 1988

= lOOk

80% AM 1kHz

30

34

42

29

34

43

dB

15nF de-emphasIs

110

175

250

80

175

260

mVRMS

150pF de-emphasis

530

530

mVRMS

AF level -118dBm

16

16

dB

-42

dB

73

dB

-35
No modulation for noise

4-138

-42
73

-34

Signetlcs Linear Products

Preliminary Specification

High-Performance Low Power Mixer FM IF System

NE/SA60S

AC ELECTRICAL CHARACTERISTICS (Continued) Typical reading at TA = 25'C; Vce = + 6V unless otherwise stated.
RF frequency = 45MHz + 14.5dBV RF Input step-up; RF frequency
= 455kHz, R17 = 5.1 k; RF level = 45dBm; FM modulation = 1kHz with
± 8kHz peak deviation. Audio output with C-message weighted filter
and de-emphasis capacitor. Test circuit Figure 1. The parameters
listed below are tested uSing automatic test equipment to assure
consistent electrical characteristics. The limits do not represent the
ultimate performance limits of the device. Use of an optimized RF
layout will Improve many of the listed parameters.
LIMITS
SYMBOL

TEST
CONDITIONS

PARAMETER

IF RSSI output, Rg =100k 1
1.5k input

NE605

SA605

Min

Typ

Max

IF level = -118dBm

0

160

IF level = -68dBm

2.0

2.5

IF level = -18dBm

4.1

4.8

RSSI range

Rg = 100kU Pin 16

RSSI accuracy

Rg = 100kU Pin 16

UNIT

Min

Typ

Max

550

0

160

650

mV

3.0

1.9

2.5

3.1

V

5.5

4.0

4.8

5.6

90

90

± 1.5

V
dB

± 1.5

dB

IF input impedance

1.40

1.6

1.40

1.6

kU

IF output impedance

0.85

1.0

0.85

1.0

kU

Limiter Input Impedance

1.40

1.6

1.40

1.6

kU

58

58

kU

Test at Pin 18

58

58

kU

Unmuted audio level

4.5V = Vec, RF level = -27dBm

480

480

mVRMS

System RSSI output

RF level = -27dBm, 4.5V = Vec

4.3

4.3

V

Unmuted audio output impedance
Muted audio output impedance
RF/IF section (int LO)

NOTE:
1. NE604 data sheets refer to power at

son

Input termination; about 21dB less power actually enters the Internal 1.5k Input.
NE604 (50)
NE604A (1 5k)/NE605 (15k)
-97dBm
-11adBm
-47dBm
-6adBm
+3dBm
-1adBm
The NE605 and NE604A are both derived from the same baSIC die. The NE605 performance plots are directly apphcable to the NE604A

CIRCUIT DESCRIPTION
The NE/SA605 IS an RF/IF Signal processing
system suitable for second IF or single conversion systems with Input frequency as high
as 1GHz. The bandwidth of the IF amplifier is
about 40MHz With 39.7dBV of gain from a
50U source. The bandwidth of the limiter IS
about 28MHz With about 62.5dBV of gain
from a soU source. However, the gain!
bandWidth distribution is optimized for
455kHz, 1.5kU source applications. The
overall system IS well-suited to battery operation as well as high performance and high
quality products of all types.
The Input stage IS a Gilbert cell mixer With
oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain
of 13dB, and input third order intercept of
-10dBm. The oscillator will operate In excess
of 1GHz in LlC tank configurations, either

December 1988

Hartley or Colpitts. For crystal oscillators, the
Colpitts configuration IS used up to 150MHz.
The output of the mixer IS Internally loaded
with a 1.5kU resistor permitting direct connection to a 455kHz ceramic filter. The input
resistance of the limiting IF amplifiers is also
1.5kU. With most 455kHz ceramic filters and
many crystal filters, no Impedance matching
network is necessary. To achieve optimum
linearity of the log signal strength indicator,
there must be a 12dBV Insertion loss between the first and second IF stages. If the IF
filter or interstage network does not cause
12dBV Insertion loss, a fixed or variable
resistor can be added between the first IF
output (Pin 16) and the interstage network.
The Signal from the second limiting amplifier
goes to a Gilbert cell quadrature detector.
One port of the Gilbert cell IS Internally driven
by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This

4-139

signal, which now has a 90' phase relallonship to the Internal signal, drives the other
port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For
operation at intermediate frequencies greater
than 455kHz, special care must be given to
layout, termination, and interstage loss to
avoid instability.
The demodulated output of the quadrature
detector IS available at two pins, one continuous and one with a mute switch. Signal
attenuation with the mute activated IS greater
than 60dS. The mute Input is very high
impedance and is compatible with CMOS or
TTL levels.
A log signal strength indicator completes the
circuitry. The output range is greater than
90dB and is temperature compensated. ThiS
log signal strength indicator exceeds the
criteria for AMPs or TACs cellular telephone.

•

Signetlcs Linear Products

PreliminalY Specification

High-Performance low Power Mixer FM IF System

m
n

-25dB, 1500/500 PAD

~

...

'" ""

"" "'"

~

T""

-10d8,50SOIlPAO

-3 6d8, 92915011 PAD

~
."

".

-10dB,SO/50flPAO

~
:~

'"

."
'"

n.
""

'=

T

NEjSA605

n

-36d8, 1 SSk/5tlll PAD

'"

-;-

C20

....

."'"

Te1s

UNMtITED
AUOIO

0<"""

12=85uHT015uH
RS REQUIRED FOR AUTO TEST EQUIP ONLY

See NOTES in back of this book for additional drawings.

Figure 1. NE/SA605 45MHz Test Circuit and Application Circuit (Relays as shown)
Application Component List
C1
C2
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C17
C18

100pF NPO Ceramic
390pF NPO Ceramic
100nF ± 10% Monohthic Ceramic
22pF NPO Ceramic
1nF Ceramic
5.6pF NPO Ceramic (minimum)
100nF ± 10% Monolithic Ceramic
151lF Tantalum (minimum)
100nF ± 10% Monohthlc Ceramic
15nF ± 10% Ceramic
150pF ±2% N1500 Ceramic
100nF ± 10% Monolithic Ceramic
10pF NPO Ceramic
100nF ± 10% Monolithic Ceramic
100nF ± 10% Monolithic Ceramic

C21
C23
Flt1
Flt2
IFT1

L1
L2

X1
R9
R17
R5
R10
R11

December 1988

4-140

100nF ± 10% Monolithic Ceramic
100nF ± 10% Monohthic Ceramic
Ceramic Filter Murata SFG455A3 or equiv
Ceramic Filter Murata SFG455A3 or equiv
455kHz (Ce = 180pF) RMC·2A6597H
147·160nH Coilcraft UNI·10/142·04J08S
0.5·1.3IlH, 800nH nominal
Coil craft UNI·10/143·16J12S
Coilcraft SLOTTEN·04·01
Toko 113KN·2K353HM
44.545MHz Crystal ICM4712701
100k ±1% 1/4W Metal Film
5.1k ±5% 1/4W Carbon Composition
Not used in application; required for auto
test equipment only
100k ±1% 1/4W Metal Film (optional)
100k ± 1% 1/4W Metal Film (optional)

Signetics

NE/SA614A

Low Power FM IF System
Linear Products

PrelimInary Specification

DESCRIPTION

dynamic range In excass of
90dB
• Two audio outputs - muted
and unmuted
• Low external component
count; suhable for
crystal/ceram Ic filters

The NEISA614A is an improved monolithic low-power FM IF system incorporating two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received signal
strength indicator, and voltage regulator. The NEISA614A features higher IF
bandwidth (25M Hz) and temperature
compensated RSSI and limiters permitting higher performance application
compared with the NE/SA604. The
NEtSA614A is available in a 16-lead
dual-in-line plastic and 16-lead SO
(surface-mounted miniature package).

• Excellent _nshIvHy: 1.511V
across Input pins (0.22I1V Into
50n matching network) for 12dB
SINAD (Signal to Noise and
Distortion ratio) at 455kHz
• SA614A meets consumer cellular
radio specifications

• Low-power consumption
3_3mA typical
• Temperature compensated
logarithmic Recalved Signal
Strength Indicator (RSSI) with a

D,N PACKAGE
IFAMP 1

1

Doupllng

GND2
Mute~ut

15

3

• Consumer cellular radio FM IF
• Consumer communications
receivers
• Intermediate frequency
amplification and detection up to
25MHz
• RF level meter

14 IF An1> output

RSSloutput 5

Mutad.::~ 6
Unmutad 7
audio output
Quadrature 8
Input

• Spectrum analyzer
• Instrumentation
• FSK and ASK data receivers

ORDERING INFORMATION
DESCRIPTioN

TEMPERATURE RANGE ORDER CODE

16-Pin Plastic DIP
16-Pin Plastic SO (Surface-mounted miniature package);
16-Pin Plastic DIP
16-Pin Plastic SO (Surface-mounted miniature package);

BLoCK DIAGRAM

SllUrrbor 13. 1988

4-141

IFAn1> Input

~;11ng

TOP VIEW

APPLICATIONS
FEATURES

PIN CONFIGURATION

oto +70·C
Oto +70·C
-40 to +85·C
-40 to +85·C

NE614AN
NE614AD
SA614AN
SA614AD

•

Preliminary Specification

Signetics linear Products

Low Power FM IF System
ABSOLUTE MAXIMUM RATINGS
SYMBOL AND PARAMETER
Maximum operating voltage
Storage temperature
Operating temperature
NE614A
SA614A

NE/SA614A

RATING

UNIT

9
-65 to +150

V
DC

Oto 70
-40 to +S5

°C
°C

= +6V unless otherwise stated

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee
PARAMETER

TEST

SA614A

NE614A

CONDITIONS

MIN
4.5
2.5
1.7

Power supply voltage range
DC current drain
Mute switch input threshold (on)
(off)

TYP
3.3

MAX
S.O
4.0

MIN TYP
4.5
2.5 3.3
1.7

MAX
S.O
4.0
1.0

1.0

UNIT
V
mA
V
V

AC ELECTRICAL CHARACTERISTICS Typical reading at TA = 25°C; Vee = +6V unless otherwise stated. IF
frequency =455kHz; IF level = -47dBm; FM modulation = 1kHz with ±SkHz peak deviation. Audio output with C-message
weighted filter and de-emphasis capacitor. Test circuit Figure 1. The parameters listed below are tested using automatic
test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits
of the device. Use of an optimized RF layout will improve many of the listed parameters.
PARAMETER
Input limitina - 3dB
AM rejection
Recovered audio level
Recovered audio level
SINAD sensitivity
THD
Signal-to-noise ratio
RSSloutput

RSSI range
ASSI accuracy
IF inout imoedance
IF output impedance
Limiter input impedance
Unmuted audio output resistance
Muted audio output resistance

TEST
CONDITIONS
Test at Pin 16
SO%AM 1kHz
15nF de-emphasis
150pF de-emphasis
RF level -97dBm

MIN
25
60

-30
No modulation for noise
RF level = -11SdBm
RF level = -6SdBm
RF level = -1SdBm
R = 100k Pin 5
100k~in 5

0
1.7
3.6

13.=

1.4
0.S5
1.4

NElSA614A
TYP
-92
33
175
530
12
-42
6S
160
2.50
4.S0
SO
±2.0
1.6
1.0
1.6
58
58

MAX

260

SOO
3.3
5.S

NOTE:
1. NE6l4A data sheets refer to power at son input termination; about 2ldB less power actually enters the intemall.5k input.
NE6l4A (SO)
NE6l4A (1.5k)lNE615 (1.5k)
-97dBm
-ll6dBm
-47dBm
-66dBm
+3dBm
-16dBm
The NE6l5 and NE6l4A are both derived from the same basic die. The NE615 performance plots are directly applicable to the NE6l4A.

4-142

UNIT
dBm/50Q
dB
mV"""
mVrms
dB
dB
dB
mV
V
V
dB
dB
kQ
kQ
kQ
kQ
kg

Signetlcs Linear Products

Preliminary Specification

Low Power FM IF System

NE/SA614A

DATA.
OUTPUT

MUTE

RSSI

Vee

OUTPUT

INPUT

SISNtTICS

Cl 10nF +80-20' 63V K10000·ZSV CeramIC
C2 100nF! 10 .... SOV

NES1'1 TEST CKT! ()

C3
C4
CS
C6
C7

100nF! 10-" SOY
l00nF! 10'" SOY
l00nF! 10-.. SOli
lOpF! 2-" l00V NPO Cera""uc
100nF! 10"" soy
ce l00nF! 10," sav
C9 1SnF! 10·,. SOY
etC lSOpF! 2'" 100V Nl500 CeramIC
'"F! 'O~ 100V K2000·VSP CeramiC
C12 6 auF! 20 .... 251/ Tlnt.lum

~)

iOI
~I!'.'GI~
..... c::z

0

()

e"~~

gO ~

e"

F 1 .. 55kHz CeramiC Fill.. Murata SFG45SA,3
F2 455kHz If Filter
Fll
1/4IN Metal Film
R2 1S000:,'" ,floW Melal Film
R3 ,soon! 5'" 1/8W Cirbon Composition
Fl4 l00kn:1 __ 1/4W Mellol Film

s,n!, ...

~.)

31

~

.~.~

SO

00

4-143

-

()~

Gt

~G ~ 'blol~~·
~
..

FI ure 1. NE614A Test CIrcuIt

O~

•

Signetfcs Linear Products

Prellmlngry Specification

Low Power FM IF System

NE/SA614A

Figure 2. Equivalent Circuit

Circuit Description
The NElSA614A Is a very high gain,
high frequency device. Correct
operation Is not possible If good RF
layout and gain stage practices are
not used. The NElSA614A can not
be evaluated Independent of circuit,
components, and board layout. A
physical layout which correlates to
the electrical limits Is shown in Figure 1. This configuration can be
used as the basis for production
layout.
The NE/SA614A is an IF signal processing system suitable for IF frequencies as high as 21.4MHz. The device
consists of two limiting amplifiers,
quadrature detector, direct audio output, muted audio output, and signal
strength indicator (with log output char-

acteristic).
The sub-systems are
shown in Figure 2. A typical application
with 45MHz input and 455kHz IF is
shown in Figure 3.

IF Amplifiers
The IF amplifier section consists of two
log-limiting stages. The first consists of
two differential amplifiers with 39dB of
gain and a small signal bandwid,h of
41 MHz (when driven from a 500
source). the output ofthe first limiter is
a low impedance emitter follower with
1kO of equivalent series resistance.
The second limiting stage consists of
three differential amplifiers with a gain
of 62dB and a small signal AC bandwidth of 28MHz. The outputs of the
final differential stage are buffered to
the internal quadrature detector. One
of the outputs is available at Pin 9 to

4-144

drive an external quadrature capacitor
and UC quadrature tank.
Both of the limiting amplifier stages are
DC biased using feedback. The buffered output of the final differential
amplifier is fed back to the input
through 42kO resistors. As shown in
Figure 2 the input impedance is established for each stage by tapping one of
the feedback resistors 1.6kO from the
input. This requires one additional
decoupling capacitor from the tap point
to ground.
Because of the very high gain, bandwidth and input impedance of the limiters, there is a very real potential for
instability at IF frequencies above
455kHz. The basic phenomenon is
shown in Figure 6. Distributed feed-

Slgnetics Linear Products

Preliminary Specification

Low Power FM IF System

NE/SA614A

... _ _..19Ii'II..,_...

_ F tlPUTII&YlC11G11D!

-,.

..

-

... ...

....

--

Figure 3. Typical Application Cellular Redlo (45MHz to 455kHz)

4.2K
V+

-1.,,-----.. . . .

700

1.0--+-....

back (capacitance, inductance and
radiated fields) forms a divider from the
output of the limiters back to the inputs
(including the RF input). If this feedback divider does not cause attenuation greater than the gain of the forward path, then oscillation or low level
regeneration is likely. If regeneration
occurs, two symptoms may be present:
(1 )The RSSI output will be high with no
signal input (should nominally be
250mVor lower), and (2) the demodulated output will demonstrate a threshold. AboVe a certain input level, the
limited signal will begin to dominate the
regeneration, and the demodulator will
begin to operate in a "normal" manner.
There are three primary ways to deal
with regeneration: (1) Minimize the

FI ure 4. First Limiter Blaa

4-145

Preliminary Speclftcation

Signetics linear Products

Low Power FM IF System

NE/SA614A

12

O-~~--~~~------~~---------L~~

8

10K

Figure 5. Second Umlter and Quadrature Detector

r--------I...._z,........t-----------,
~--t It t---;...-=--=--=-"".1-1 z, t- - - - J

I

'------I

"'----

~,~~""",~,~
I

I

I

I
I

Figure 6. Feedback Paths

feedback by gain stage isolation, (2)
lower the stage input impedances, thus
increasing the feedback attenuation
factor, and (3) reduce the gain. Gain
reduction can effectively be accomplished by adding attenuation between
stages. This can also lower the input
impedance if well planned. Examples
of impedance/gain adjustment are
shown in Figure 7. Reduced gain will
resu~ in reduced lim~ing sens~ivity.
A feature of the NE614A IF amplifiers,
which is not specified, is low phase
shift. The NE614A is fabricated w~h a
1OGHz process with very small collec-

tor capac~ance. It is advantageous in
some applications that the phase shift
changes only a few degrees over a
wide range of signal input ampl~udes.
Additional information will be provided
in the upcoming product specification
(this is a preliminary specification)
when characterization is complete.

Stability Considerations
The high gain and bandwidth of the
NE614A in combination w~h its very
low currents permit circu~ implementation with superior performance. However, stability must be maintained and,
to do that, every possible feedback

4-146

mechanism must be addressed.
These mechanisms are: 1) Supply
lines and ground, 2) stray layout inductances and capac~ances, 3) radiated
fields, and 4) phase shift. As the system IF increases, so must the attention
to fields and strays. However, ground
and supply loops cannot be overlooked, especially at lower frequencies. Even at 455kHz, using the test
layout in Figure 1, instabil~y will occur
if the supply line is not decoupled w~h
two high quality RF capacoors, a 0.1 uF
monolithic right at the Voc pin, and a
6.8jLF tantalum on the supply line. An
electrolytic is not an adequate substitute. At 10. 7MHz, a 1jLF tantalum has
proven acceptible with this layout.
Every layout must be evaluated on ~s
own merit, but don't underestimate the
importance of good supply bypass.
At 455kHz, if the layout of Figure 1 or
one substantially similar is used, it is
possible to directly connect ceramic
filters to the input and between lim~er
stages with no special consideration.
At frequencies above 2MHz, some
input impedance reduction is usually
necessary. Figure 7 demonstrates a
practical means.

As illustrated In Figure 8,

4300

external resistors are applied in parallel to the internal1.6kn load resistors,
thus presenting approximately 3300 to

Preliminary Speclficalion

Signetics Linear Products

NE/SA614A

Low Power FM IF System

0-o1

BP F

ffiPedance

1.:----,

4
...=

I~ BPF

I
I

I

I
II

L_~~I
I~~ I
I

T ~
=

ha~, - - - - ,
I

L\-______
Low Impedance

L- L ___ "':" T

I
~

I
_____ ..JI

I

i
i

7a. Terminating High Impedance Filters with Transformation to Low Impedance

1-----,
I
I

I
I
I
I

Resistive Loss Into BPF

TL------------- _____ ..J

-

T

7b. Low Impedance Termination and Gain Reduction
Figure 7. Practical Termination

the filters. The input filter is a crystal
type for narrow-band selectivity. The
filter is terminated with a tank which
transforms to 330(:1. The interstage
filter is a ceramic type which doesn't
contribute to system selectivity, but
does suppress wideband noise and
stray signal pickup.
In wideband
10.7MHz IFs the input filter can also be
ceramic, directly connected to Pin 16.
In some products it may be impractical
to utilize shielding, butthis mechanism
may be appropriate to 10.7MHz and

21.4MHz IF. One of the benefits of low
current is lower radiated field strength,
but lower does not mean non-existent.
A spectrum analyzer with an active
probe will clearly show IF energy with
the probe held in the proximity of the
second limiter output or quadrature
coil. No specnic recommendations are
provided, but mechanical shielding
should be considered if layout, bypass,
and input impedance reduction do not
solve a stubborn instability.

phase shift. The phase shift of the
limiters is very low, but there is phase
shift contribution from the quadrature
tank and the filters. Most filters demonstrate a large phase shift across their
passband (especially at the edges). If
the quadrature detector is tuned to the
edge of the filter passband, the combined filter and quadrature phase shift
can aggravate stability. This is not
usually a problem, but should be kept in
mind"

The final stability consideration is

430

430

614A

ut Filter with Ceramic Intersta e Filter

4-147

•

I

Signetics Linear Products

Preliminary Specification

Low Power FM IF System

NE/SA614A

Quadrature Detector
Figure 5 shows an equivalent circuit of
the NE614A quadrature detector. It is
a multiplier cell similar to a mixer stage.
Instead of mixing tw,o different frequencies, it mixes two signals of common
frequency but different phase. Internal
to the device, a constant amplitude
(limited) signal is differentially applied
to the lower port of the multiplier. The
same signal is applied single ended to
an external capacitor at Pin 9. There is
a 90· phase shift across the plates of
this capacitor, with the phase shifted
signal applied to the upper port of the
multiplier at Pin 8. A quadrature tank
(parallel UC network) permits frequency selective phase shifting at the
IF frequency. This quadrature tank
must be returned to ground through a
DC blocking capacitor.
The loaded 0 of the quadrature tank
impacts three fundamental aspects of
the detector: Distortion, maximum
modulated peak deviation, and audio
output amplitude. Typical quadrature
curves are illustrated in Figure 10. The
phase angle translates to a shift in the
multiplier output voltage.
Thus a small deviation gives a large
output with a high 0 tank. However, as
the deviation from resonance increases, the nonlinearity of the curve
increases (distortion), and, with too
much deviation, the signal will be outside the quadrature region (limiting the
peak deviation which can be demodulated). If the same peak deviation is
applied to a lower 0 tank, the deviation
will remain in a region of the curve
which is more linear (less distortion),
but creates a smaller phase angle
(smaller output amplitude). Thus the 0
of the quadrature tank must be tailored
to the design. Basic equations and an
example for determining 0 are shown
below. This explanation includes first
order effects only.

Frequency discriminator design
equations for NE614A
Cs
Vo= - - Cp + Cs

(Ia)

Multiplying the two signals in the mixer,
and low pass fine ring yields:
2 .

VNo Vo= A Sin oj

Fl ure 9.

co, =

where

(4)

after low pass filtering
(Ib)

1

::} Vour

0,,, R ( Cp + C.) co,

=~ A2

(5)

2

tl\C p + CsJ
(Ic)

From the above equation, the phase
shift between nodes 1 and 2, or the
phase across C. will be:

11>= LVo- LVN=

(2)

'if ai~rl
For
Figure 10. Is the plot of ell vs. (:)
Which is the discriminated FM output.

It is notable that at co = co" the phase
shift is

1t

2"

(Note that ACO is the deviation frequency from the carrier co,.)

and the response is close

to a straight line with a slope of

20,

~ =

co,

~co

:::r~i:H::h~':.a
to the V'N.

Ref. Krauss, Raab, Bastian; Solid
State Radio Eng.; Wiley,1980, p.311.
Example: At 455kHz IF, with ±5kHz
FM deviation. The maxImin normalized frequency will be
455 :!:5kHz
455
.. 1.0100rO.990
Go to the ell vs. normalized frequency
curves (Figure 10) and draw a vertical
straight line at

If V'N = A Sin 01
(3)

::}Vo=A

0

.

[

1t

Sm CIt + 2-

4-148

(20,\
]
~I co

J

(:)

.. 1.01. The

curves with 0 .. 100, 0 = 40 are not
linear, but 0 = 20 and less shows better
linearity for this application. Too small
o decreases the amplitude of the discriminated FM signal. (Eq.6)
~ Choose a 0 .. 20.

Signetics Linear Products

Preliminary Specification

Low Power FM IF System
TheinternalRofthe614Ais40k. From
Eq. 1c, and then 1b, it results that
C, + G. = 174pF and L = 0.7mH.
A more exact analysis including the
source resistance of the previous
stage shows that there is a series and
a parallel resonance in the phase detector tank. To make the parallel and
series resonances close, and to get
maximum attenuation of higher harmonics at 455kHz IF, we have found
that a Cs = 10pF and Cp =164pF (commercial values of 150pF or 180pF may
be practical), will give the best results.
A variable inductor which can be adjusted around 0.7mH should be chosen and optimized for minimum distortion. (For 10. 7MHz, a value of Cs = 1pF
is recommended.)

Audio Outputs
Two audio outputs are provided. Both
are PNP current-to-voltage converters
with 55kn nominal internal loads. The
unmuted output is always active to
permit the use of signaling tones in
systems such as cellular radio. The
other output can be muted with 70dB
typical attenuation. The two outputs
have an internal 180" phase difference.
The nominal frequency response of the
audio outputs is 300kHz. This response can be increased with the
addition of external resistors from the
output pins to ground in parallel with
the internal55k resistors, thus lowering
the output time constant. Since the
output structure is a current-to-vo~age
converter (current is driven into the
resistance, creating a voltage drop),
adding external parallel resistance
also has the effect of lowering the output audio amplitude and DC level.
This technique of audio bandwidth
expansion can be effective in many
applications such as SCA receivers
and data transceivers. Because the
two outputs have a 1800 phase relationship, FSK demodulation can be
accomplished by applying the two outputs differentially across the inputs of
an op amp or comparator. Once the
threshold of the reference frequency
(or "no-signal" condition) has been
established, the two outputs will shift in

NE/SA614A
opposite directions (higher or lower
output voltage) as the input frequency
shifts. The output of the comparator
will be the logic output. The choice of
op amp or comparator will depend on
the data rate. With high IF frequency
(1 OM Hz and above), and wide IF bandwidth (UG filters) data rates in excess
of 4Mbaud are possible.

RSSI
The "received signal strength indicator", or RSSI, of the NE614A demonstrates monotonic logarithmic output
over a range of 9OdB. The signal
strength output is derived from the
summed stage currents in the limiting
amplifiers. It is essentially independent of the IF frequency. Thus, unfiltered signals at the limiter inputs, spurious products, or regenerated signals
will manifest themselves as RSSI outputs. An RSSI output of greater than
250mV with no signal (or a very small
signal) applied, is an indication of possible regeneration or oscillation.
In order to achieve optimum RSSllinearity, there must be a 12dB insertion
loss between the first and second limiting amplifiers. With a typical 455kHz
ceramic fi~er, there is a nominal 4dB
insertion loss in the fi~er. An additional
6dB is lost in the interface between the
fi~er and the input of the second limiter.
A small amount of additional loss must
be introduced with a typical ceramic
filter. In the test circuit used for cellular
radio applications (Figure 3) the optimum linearity was achieved with a
5.1 kn resistor from the output of the
first limiter (Pin 14) to the input of the
interstage filter. With this resistor from
Pin 14 to the filter, sensitivity of 0.25j.lV
for 12dB SINAD was achieved. With
the 3.6kn resistor, sensitivity was optimized at 0.22j.lV for 12dB SINAD with
minor change in the RSSllinearity.
Any application which requires optimized RSSI linearity, such as spectrum analyzers, cellular radio, and
certain types of telemetry, will require
ccreful attention to limiter interstage
cvmponent selection. This will be
especially true with high IF frequencies
which require insertion loss or impedance reduction for stability.

4-149

At low frequencies the RSSI makes an
excellent logarithmic AG voltmeter.
For data applications the RSSI is effective as an amplitude shift keyed (ASK)
data slicer. If a comparator is applied to
the RSSI and the threshold set slightly
above the no signal level, when an inband signal is received the comparator
will be sliced. Unlike FSK demodulation, the maximum data rate is somewhat limited. An internal capacitor
limits the RSSI frequency response to
about 100kHz. At high data rates the
rise and fall times will not be symmetrical.
The RSSI output is acurrent-to-voltage
converter similar to the audio outputs.
However, an external resistor is required. With a 91 kn resistor, the output characteristic is 0.5V for a 10dB
change in the input amplitude.

Additional Circuitry
Internal to the NE6 14A are voltage and
current regulators which have been
temperature compensated to maintain
the performance of the device over a
wide temperature range. These regulators are not accessible to the user.

•

Preliminary Specification

Signetlcs Linear Products

NE/SA614A

Low Power FM IF System

~r----------------r--------------~~--------------~---------------'

"~==--

__-=~-----F~~~~~~--~----------------+---------------~

.....-......-

.~
U5~------~~~~-r--~~~~~~~----------------+---------------~

_..

r---------------~~------~~~~a+----------------~----------------~

~r---------------~~--------------_+~~~~~~----~----------------~
.r---------------~~--------------_+--~~~----~~~------~~~~~~

Figure 10. Phase

VB.

Normalized IF Frequency

4-150

Signetics

NEjSA615
High-Performance Low Power
Mixer FM IF System
Pre/imlnary Specification

Linear Products

DESCRIPTION
The NE/SA615 is a consumer monolithic low power FM IF system incorporating
a mixer/osc, two limiting intermediate
frequency amplifiers, quadrature detector, muting, logarithmic received signal
strength indicator (RSSI), and voltage
regulator. The NE/SA615 is available in
a 20-lead dual-in-line plastic and 20-lead
SOL (surface-mounted miniature package).

FEATURES
• Low-power consumption 5.7mA
typical at 6V
• Mixer input to > 500MHz
• Mixer conversion power gain of
13dB at 45MHz
• Mixer noise figure of 4.6dB at
45MHz

• XTAL oscillator effective to
150MHz (L.C. oscillator to lGHz
local oscillator can be Injected)
• 102dB of limiter gain
• 25MHz limiter small signal
bandwidth
• Temperature compensated
logarithmic Received Signal
Strength Indicator (RSSI) with a
dynamic range in excess of 90dB
• Two audio outputs - muted and
unmuted
• Low external component count;
suitable for crystal/ceramlc/LC
filters

Dl and N Packages
RFIN
RF II'IPASS 2
CRYSTAL OBC

3

CRYSTAL OSC

4

TEMPERATURE RANGE

ORDER CODE

O·C to +70·C

NE61SN

20-Pln PlastiC SOL (Surfacemounted)

O·C to +70°C

NE61SD

20-Pin PlastiC DIP

-40·C to + 8SoC

SA61SN

20-Pin PlastiC SOL (Surfacemounted)

-40·C to + 8S·C

SA61SD

RSSIOUT 7

1

UMrrER IN

8

13

~Jre:.LING

~~~~

9

12

~UNG

QUADRATUFlE
IN ---.. _ _ _

-s-

UMrrER
OUT

TOP VIEW

so (SOL)

package only

• Excellent sensitivity: O.22/lV Into
50n matching network for 12dB
SINAD (Signal to Noise and
Distortion ratio) for 1kHz tone
with RF at 45MHz and IF at
455kHz
• SA615 meets cellular radio
specifications
• ESD hardened
• Will handle IF frequencies up to
25MHz

APPLICATIONS

BLOCK DIAGRAM

• Consumer cellular radio FM IF
• Single conversion VHF/UHF
receivers
• SCA receivers
• RF level meter
• Spectrum analyzer
• Instrumentation
• FSK and ASK data receivers
• Log amps
• Wldeband low current
amplification

December 1988

IrE~r..uNG
IF AMP OUT

AU:O~~

1 Large

20-Pin Plastic DIP

1

MUTEIN 5

NOTE:

ORDERING INFORMATION
DESCRIPTION

PIN CONFIGURATION

4-151

•

Preliminary Specification

Signetics Linear Products

High-Performance Low Power Mixer FM IF System

NE/SA615

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

9

V

Storage temperature

-65 to +150

'C

Operating temperature
NE605
SA605

o to + 70
-40 to + 85

'C
'C

Vce

Maximum operating voltage

TSTG
TA

DC ELECTRICAL CHARACTERISTICS TA = 25'C;

Vee = + 6V, unless otherwise stated.

LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA615
Min

Power supply voltage range

Typ

4.5

DC current drain

5.7

8.0

V

7.4

rnA

1.0

V
V

1.7

Mute switch input threshold (on)
(off)

AC ELECTRICAL CHARACTERISTICS

UNIT
Max

Typical reading at TA = 25'C; Vee = + 6V unless otherwise stated. RF frequency
= 45MHz, + 14.5dBV RF input step-up; IF frequency = 455kHz, R'7 = 5.1k; RF
level = -45dBm; FM modulation = 1kHz with ± 8kHz peak deviation. Audio output
with C-message weighted filter and de-emphasis capacitor. Test circuit Figure 1.
The parameters listed below are tested using automatic test equipment to assure
consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the device. Use of an optimized RF layout will improve many
of the listed parameters.
LIMITS

SYMBOL

TEST
CONDITIONS

PARAMETER

NE/SA615
Min

Mixer/Osc section (ext LO

Typ

UNIT
Max

=300mV)

fiN

Input signal frequency

500

MHz

fose

Crystal OSCIllator frequency

150

MHz

Noise figure at 45MHz

5.0

dB

-12

dBm

13
-1.7

dB
dB

fl

Third-order intercept point
Conversion power gain
RIN

RF Input resistance

CIN

RF input capacitance

= 45.0; f2 = 45.06MHz

Matched 14.5dBV step-up
50n source

8.0

Single-ended input

3.0

4.7
3.5

(Pin 20)

Mixer output resistance

1.25

kn
4.0

pF

1.50

kn
dB

IF section
IF amp gain

SOn source

39.7

Limiter gain

SOn source

62.5

dB

Test at Pin 18

-109

dBm

Input limiting -3dB, R17

= 5.1 k

AM rejection
Audio level, R,o

= lOOk

Unmuted audio level, R"
SINAD sensitivity
THO

Total harmonic distortion

SIN

Signal-to-noise ratio

December 1988

= 1OOk

80% AM 1kHz

25

33

43

dB

15nF de-emphasis

60

175

260

mVRMS

150pF de-emphasis

530

mVRMS

RF level -118dBm

12

dB

-42

dB

68

dB

-30
No modulation for noise

4-152

Preliminary Specification

Signetics Linear Products

High-Performance low Power Mixer FM IF System

NE/SA615

AC ELECTRICAL CHARACTERISTICS (Continued) Typical reading at TA = 25'C; Vce = + SV unless otherwise stated.
RF frequency = 45MHz, + 14.5dBV RF input step-up; IF
frequency = 455kHz, R17 = 5.lk; RF level = -45dBm; FM
modulation = I kHz with ± 8kHz peak deviation. Audio output with Cmessage weighted filter and de-emphasis capacitor. Test circuit
Figure I. The parameters listed below are tested uSing automatic test
equipment to assure consistent electrical characteristics. The limits do
not represent the ultimate performance limits of the device. Use of
an optimized RF layout will improve many of the listed parameters.
LIMITS
SYMBOL

TEST
CONDITIONS

PARAMETER

IF RSSI output, Rg

= lOOk1

Min

Typ

Max

IF level

0

ISO

800

mV

IF level

1.7

2.5

3.3

V

3.S

4.8

5.8

= -118dBm
= -S8dBm
IF level = -18dBm
Rg = 100kn Pin 7
Rg = 100kn Pin 7

RSSI range

UNIT

NE/SA615

80

V
dB

±2

dB

IF input impedance

1.40

I.S

kn

IF output impedance

0.85

1.0

kn

Limiter input impedance

1.40

I.S

kn

58

kn

58

kn

480

mVRMS

4.3

V

RSSI accuracy

Unmuted audio output impedance
Test at Pin 18

Muted audio output impedance
RF/IF section (int LO)

= Vee, RF level = -27dBm
= -27dBm, 4.5V = Vee

Unmuted audio level

4.5V

System RSSI output

RF level

NOTE:
1. NE614 data sheets refer 10 power at 50n Input termlnabon; about 21 dB less power actually enters the Internal 1.5k Input
NE614 (50)
NE614A (1.5k)/NE615 (1.5k)
-97dBm
-118dBm
-47dBm
-68dBm
+ 3dBm
-18dBm
The NE615 and NE614 are both derived from the same basic die. The NE615 performance plots are dorectly applicable to the NE614A.

CIRCUIT DESCRIPTION
The NE/SASI5 is an RF/IF signal processing
system suitable for second IF or single conversion systems with input frequency as high
as I GHz. The bandwidth of the IF amplifier is
about 40MHz with 39.7dBV of gain from a
50,11 source. The bandwidth of the limiter is
about 28MHz with about S2.5dBV of gain
from a 50,11 source. However, the gainl
bandwidth distribution is optimized for
455kHz, 1.5kn source applications. The
overall system is well-suited to battery operation as well as high performance and high
quality products of all types.
The input stage is a Gilbert Cell mixer with
oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain
of 13dB, and input third order intercept of
-IOdBm. The oscillator will operate in excess
of I GHz in LIC tank configurations, either

December 1988

Hartley or Colpitts. For crystal oscillators, the
Colpitts configuration is used up to 150MHz.
The output of the mixer is internally loaded
with a 1.5kn resistor permitting dorect connection to a 455kHz ceramic filter. The input
resistance of the limiting IF amplifiers is also
1.5kn. With most 455kHz ceramic filters and
many crystal filters, no impedance matching
network is necessary. To achieve optimum
linearity of the log signal strength indicator,
there must be a 12dBV insertion loss between the first and second IF stages. If the IF
filter or interstage network does not cause
12dBV insertion loss, a fixed or variable
resistor can be added between the first IF
output (Pin IS) and the interstage network.
The signal from the second limiting amplifier
goes to a Gilbert cell quadrature detector.
One port of the Gilbert cell is Internally driven
by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This

4-153

signal, which now has a 90' phase relationship to the internal signal, drives the other
port of the multiplier cell.
Overall, the IF section has a gain of 90dB. For
operation at Intermediate frequencies greater
than 455kHz, special care must be given to
layout, termination, and interstage loss to
avoid instability.
The demodulated output of the quadrature
detector is available at two pins, one continuous and one with a mute switch. Signal
attenuation with the mute activated IS greater
than SOdB. The mute input is very high
Impedance and IS compatible with CMOS or
TTL levels.
A log signal strength indicator completes the
circuitry. The output range is greater than
90dB and is temperature compensated. This
log signal strength indicator exceeds the
criteria for AMPs or TACs cellular telephone.

•

Signetics Linear Products

Preliminary Specification

NEjSA615

High-Performance Low Power Mixer FM IF System

7:-"'
R
m

-1I5d8,181101fiOf.lPIlD

~

~

...
......
..........
T""

'15

CU

~
...
."
'"

517

...

'"
T

-10dB,!O/SOOPAD

~

TC20

::~

n

-38d8,1&1k/SOOPAD

":'"

R13

.n

."

13k

~

TC>'

. ....
'"~

v'"
U-81iuHT011iUH

A5 REClUAEO FOR AU'tQ. TEST EQIJII ONLY

Figure 1. NE/SA615 45MHz Test Circuit and Application Circuit (Relays as shown)
Application Component Ust
Cl
C2
C5
C6
C7
CB
C9
Cl0
Cll
C12
C13
C14
C15
C17
C18

December 1988

100pF NPO Ceramic
390pF NPO Ceramic
100nF ± 10% Monolithic Ceramic
22pF NPO Ceramic
1nF Ceramic
5.6pF NPO Ceramic (minimum)
100nF ± 10% Monolithic Ceramic
151lF Tantalum (minimum)
100nF ± 10% Monolithic Ceramic
15nF ± 10% Ceramic
150pF ± 2O/~ N1500 Ceramic
100nF ± 10% Monolithic Ceramic
10pF NPO Ceramic
100nF ± 10% Monolithic Ceramic
100nF ± 10% Monolithic Ceramic

C21
C23
Fltl
Flt2
IFTl
L1
L2

Xl
A9
A17
A5
Al0
All

4-154

100nF ± 10% Monolithic Ceramic
100nF ± 10% Monolithic Ceramic
Ceramic Filter Murata SFG455A3 or equiv
Ceramic Filter Murata SFG455A3 or equiv
455kHz (Ce = 180pF) AMC-2A6597H
147-160nH Collcraft UNI-l0/142-04J08S
0.5-1.3IlH. 800nH nominal
COllcraft UNI-l0/143-16J12S
Coilcraft SLOTIEN-04-01
Toko 113KN-2K353HM
44.545MHz Crystal ICM4712701
lOOk ±1% 1/4W Metal Film
5.1k ±5% 1/4W Carbon Composition
Not Used in ApplicatJon
lOOk ± 1% 1/4W Metal Film (optional)
lOOk ± 1% 1/4W Metal Film (optional)

Preliminary Specification

Signetics Linear Products

High-Performance Low Power Mixer FM IF System

5 L9nET i

NEjSA615

1:5

5 !"BnEt i 1:5

o

fUi

000 fLn

CI7

o Otiu-"
n.. O..J']O
l:1"""'
••
CeCCICI ClalZl~·.
.. '"
.IFTI.

•

C2

Cl

Rc::J
l:f ~ (;] ~~e~~el:l CIS
c:::;o
c:::::::J
0X1
.'[] I e "
(5

f£60S

.. C6

0
0

m

en

ell

L2

•

Cl •

Irn SWI

Figure 2. Layout for NE/SA615 Test and Application Board

' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ ..

December 1988

4-155

-:~...

--------'

TDA1576

Signetics

FM-IF (Quadrature Detector)
Product Specification

Linear Products

DESCRIPTION

FEATURES

APPLICATIONS

TDA157f IS an IC which provides all the
functions of a comprehensive FM-IF system. The block diagram of the TDA 1576
includes a 4-stage FM-IF Amplifier/limiter with level detector, quadrature FM
detector, FM detector, internal regulator,
AFC output, and audio meeting circuit.
The TDA 1576 is Ideal for application
areas that require low distortion characteristics (THD).

• Symmetrical limiting IF amplifier
• Symmetrical quadrature
demodulator
• Internal muting circuit
• Symmetrical AFC output
• Field-strength indication output
• Detune-detector
• Reference voltage output
• Electronic smoothing of the
supply voltage
• Standby on/off switching circuit

• High-fidelity receiver
• Communication receiver
• Automotive receiver
• TVRO

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

- 30°C to + 80°C

TDA1576N

18-PIn PlastIC DIP (SOT-l02C)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vee=Vl-18

PARAMETER

Supply voltage (Pin 1)

RATING

UNIT

23

V

Vee
0
23
0
7
0
6
23
0

V
V
V
V
V
V
V
V
V

Voltages
V2- 18
-V2- 18
VS-18
-VS-18
V12-18
-V12-18
V13-18
V14 - 18
-V14 - 18

January 14, 1987

at Pin 2
at Pin 5
at Pin 12
at Pin 13
at Pin 14

PTOT

Total power dissipation

800

mW

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-30 to +80

°C

OeRA

Thermal resistance from crystal to ambient

80

°C/W

4-156

853-1134 87196

Signetics linear Products

Product Specification

TDA1576

FM-IF (Quadrature Detector)

BLOCK DIAGRAM AND TEST CIRCUIT
+

Q

750

+

2

1

L

25k

15k

AFC
VOLTAGE

t

25k

..

15k

1

8.3k

~-+~~r----~~--~~~~----;~'
t4-STAGE
LIMITER!
AMPLIFIER

~~

MUTING

t

250

~-

t

QUADRATURE
DEMODULATOR

- ,.

-

+

~

r-5.5
k
~

r

~-H-

TDA1576

LEVEL
DETECTOR

II

1
INDICATOR
DRIVER

DETUNE~
1.7V
DETECTOR
1---+-+---,
G

INTERNAL
POWER
SUPPLY

STANDBY
SWllt:H

I
I

z,,-10

I
I
I
I

j 111=
O.SmA

(185Vy)

20k

1--+';;...0-<1>-.-

14

12
220k

f-- - --,
I

r-"NYI

1Ok~~

+

(AM)
RELD-STRENGTH
INDICATOR

VFo

+

ZER().ADJUSTMENT
OF RELD-STRENGTH
INDICATOR

«23V)

NOTES,
1 For d~mphasls 'T = 50ps Ca _9 = 6 8nF For stereo operatIOn Ca _ 9 = 56pF
2 l = 0 38pH, 00 = 70, Ol = 20, adjusted to minimum 2nd harmonic dlstortton (d2), at VI

January 14, 1987

=

4-157

~ 20-10

(240k) ~ (180k)

>--

5.3V

13

•

3.7k

DETUNE·
VOLTAGE

1mV, cOil 6 turns Cul (025mm) on cOil former KAN (C)

-.J

Signetics linear Products

Product Specification

FM·IF (Quadrature Detector)

TDA1576

DC AND AC ELECTRICAL CHARACTERISTICS

Vee ~ 8 5V fa ~ 10 7MHz, Ll.f ~ t 22.5kHz, fM ~ 400Hz; Rs ~ 60Q; de-emphasIs 7 ~ 50"s (C a _ 9 ~ 6.8nF), T A ~ 25"C; measured In the Block Diagram, unless otherwise specified The demodulator CIrCUIt IS adjusted at
minimum 2nd harmonic (d2) distortion. V 1 ~ lmV; Ll.f ~ ± 75kHz.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

Vce

Sup ply voltage range (Pin 1)

Ice

Sup ply current, without load (112

Typ

Max
20

V

16

23

mA

22

30

"V

7.5
~

~~~-'--

113 ~ 0)
-

10

JF ampJifier/detector
--_.
V,
Sen SltlVlty at - 3dB before limiting
-------"------------~--------------~.

IF sensitivity for
S + N/N = 26dB
S + N/N = 46dB

V,
V,

IF output voltage (peak-to-peak value)
1=lmV, Z3-1a~Z7-1a
--IF output resistance

V3.7(P_P)

8
35

"V
"V

680

mV

v

250

Q

Det ector Input Impedance

30
1

kQ
pF
kQ

--

Ra, R9

Out put resistance

3.7

Va-1a~V9-1a

DC output voltage

5.5

Va

AF output voltage, QL = 20

60

67

V
75

mV

--~---~~

Total dlstorlion
sIngle tuned CIrCUit, QL
tw o tuned CirCUits

~

20

Sig nal pulse nOlse-to-nolse ralio
B ~ 250Hz to 15kHz, V, > 1mV

S + N/N

_.

IF Input voltage range,

 40dB

.-

Hu m suppression at f = 100Hz
Vec = V1-1a = 100mVRMS
C2-1a=47"F
_.-------------AF C tUning slope at QL

~

76

dB

54

dB 1

0.5

500

mV

~--

43

20

J

AF C offset voltages, QL = 20
at V, = lmV
at V, = 30"V to 500mV (reference at 1mV and muting)
- - -- - - - - - - - - - - - - - - .
Field-strength indic alion
-Ind Icator sensitivity, 114 = 0

±Ll.Va _ 9
±Ll.Va-9

%
%

-

AM reJection, V, = 10mV
FM. 1M = 70Hz, Ll.1 = ± 22.5kHz
A M' 1M = 1kHz, m ~ 0 3

V,

0.1
0.02

48

dB

8.5

mY/kHz

100
50

mV
mV

600

mV

0

200

mV

36

41

25

-.-~-

20

Fie Id-strength indicator voltage
R 13-1a~36kQ, 114~0, V,=O
V,= 250mV

V13 - 1a

3.2
2

mA

Re verse voltage at the output for FM 'olf' , V5_1a>35V

5

V

----~~--

January 14, 1987

V

Avaliable output current

4-158

Signetics Linear Products

Product Specification

FM-IF (Quadrature Detector)

TDA1576

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Vee = 8.5V fo = 10.7MHz; af = ± 22.5kHz; fM = 400Hz;
Rs - 60n; de-emphasis .,. = 50j.lS (Cs _ 9 = 6.8nF);
TA = 25°C; measured In the Block Diagram, unless otherWise specified. The demodulator circuit IS adjusted at
minimum 2nd harmonic (d2l distortion: V, = ImV;
af = ±75kHz.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

20

100

Detune-detector
1'0

Quiescent input current; V'0_9 = 0

V"_'8

Output voltage range

1.8

I"

Available output current

Av

Vo~age

V'0-9

Input offset voltage (Pin 10) at Vll_'8 - 2.5V

0.5

0.35

gain; aV"/a(± V'0-9) at I" = 0.25mA

nA

5.0

V

0.65

mA

•

3.3
20

mV

Reference voltage

= ImA

VREF - V'2-'8

Output voltage; -1'2

-1'2

Available output current

5.1

V

2.5

mA

Standby switch

Vs ON
Vs OFF

Required control voltage within
the rated ambient temperature and supply voltage ranges
for FM 'on'
for FM 'off'

-15

Input switching current for FM 'on'

2

V
V

100

p.A

3.5

NOTE:
1. Simultaneously measured.

30

150

20
TYP

t-"

I-"'"

1.5

QL=30

-

/

v

100

./

0L =30

/

I

Jo./

J

/I
10

50

"..

./

~

0.5

v

o
o

10

20

o
o

Vee(¥)

IL

./
./

./

'"

./
10

20

o
o

../

~

,,50

./
,,100

Af(kHz!

Vee(¥)
OP181111OS

NOTE:

NOTE:
vee "" 1mV(lF). .af'" + 15kHz. fM'" 400Hz, typical

values

Figure 1. Supply Current Consumption;
Without Load

January 14, 1987

Figure 2, AF Output Voltage

4-159

VI ... 1mV (IF), fM ... 400Hz, adjusted at minimum 2nd
harmOniC dlstortlon, typical values

Figure 3_ Total Distortion for Single
Tuned Circuit

Signetics Linear Products

Product Specification

FM-IF (Quadrature Detector)

TDA1576

.-

±75kHz

+20

S+N

,'7

,,~

+,,'1~-"::
\+

..,

.-

?,.,.~

.-

'l-..::4>

.-

+",'l,,"
'l<>l-':4>

o

1

10

NOTE:

R13 _ 18 = 3 6kn

Figure 5. Voltage at Field·Strength Indicator Output (Proportional to V12 - 181

/1

/1

v
- 1GHz
• Typical 15MHz Input at 10V
• Flexible programming:
- frequency offsets
- ROM compatible
- fractional channel capability
• Program range 6 b decades,
Including up to 3 decades of
prescaler control
• Division range extension by
cascading
• Built-In phase modulator
• Fast lock feature
• Out-of-Iock indication
• Low power dissipation and high
noise immunity
APPLICATIONS
Some examples of applications for the
HEF4750V in combination with the
HEF4751V are:
• VHF/UHF mobile radios
• HF SSB transceivers
• Airborne and marine
communications and navaids
• Broadcast transmitters
• High quality radio and television
receivers
• High-performance citizens band
equipment
• Signal generators

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

28-Pln Cerdip

-40·C to +85·C

HEF4750VDF

28-Pin Cerdip

-55·C to + 125·C

HEC4750VDF

DESCRIPTION

November 6, 1986

4-163

PIN CONFIGURATION
F Package

Ao
A,

Ao

Aa
v..
TOP VIEW
CD11210S

PIN
NO.

SYMBOL
V

8
9
10

STB
TCB
OL
TCA
TRA
TCC
PC,
PC,

Ao

11

A,

12

A,

13

A,

14
15

vs.

DESCRIPTION
Phase comparator Input
Strobe Input
Timing capaCItor CB Pin
Out~of·lock IndICation
Timing capacitor CA pm
BIasing pm (resistor RAJ

Timing capacitor Cc pin
Analog phase comparator output
DIgital phase comparator output
Programming Inputs/programmable
dIVIder
Programming Inputs/programmable

dIVIder
Programming Inputs/programmable
diVider
Programming Inputs/programmable

dlvtder
A,

16

As

17

As

18

A,

19

As

20

As

21
22
23
24
25
26

XTAL
OSC
NSo
NS,
R
OUT

27

MOD

Programming Inputs/programmable
diVIder
Programming Inputs/programmable
diVider
Programming Inputs/programmable
dlYtder
Programming Inputs/programmable
diVider
Programming Inputs/programmable
dIVIder
Programming Inputs/programmable
dIVIder
Reference OSCillator/buffer output
Reference oscillator/buffer Input
Programming Inputs, prescaler
Programming inPuts, prescaler
Phase comparator Input. reference
Reference dMder output
Phase modulabon Input

853-0905 86381

Product Specification

Signetics Linear Products

HEF4750V

Frequency Synthesizer

BLOCK DIAGRAM

14

OSC

22

Ag

XTAL NSo

21

23

10111213151617181920

24

28

OUT R

28

25

V

1

TCB MOD STB

TRA

TCA

TCC

27

u

PROGRAMMING INPUTS
REFERENCE DIVIDER

EXTERNAL CIRCUITRY
CRYSTAL STANDARD

NOTES:
1 PC1 = analog output
2 PC2 "" 3-state output

Block Diagram Comprising Five Basic Functions: Phase Comparator 1 (PC 1), Phase Comparator 2 (PC2),
Phase Modulator, Reference Oscillator and Reference Divider (These Functions are Described Separately)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VOD

Supply voltage

VI

Voltage on any Input

±I

DC current Into any Input or output

Po

TA = 0 to +85°C

PD

TA = 0 to +85°C

TSTG
TA

RATING

UNIT

-0.5 to + 15

V

-0.5 to Voo + 0.5

V

10

mA

500

mW

100

mW

Storage temperature range

-65 to +150

°C

Operating ambient temperature
HEF4750V
HEC4750V

-40 to +85
-55 to + 125

°C
°C

Power dissipation per package for
Power dissipation per output for

November 6, 1986

4-164

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

DC ELECTRICAL CHARACTERISTICS

HEF4750V. HEC4750V Voo = 1OV± 5%; voltages are referenced to Vss = OV. unless otherwise specified. For definitions see Note 1.
LIMITS

SYMBOL

PARAMETER

TA=-40°c
Min

Typ

TA

=+25°c

Min

Max

Typ

TA = + 85°C
Max

Min

Typ

UNIT
Max

100

QUiescent device current2

100

100

750

IlA

±IIN

Input current; logic
Inputs. MOD3

300

300

1000

nA

±Iz

Output leakage current at
1J2 Voo3. 4
TCA. hold-state
TCC. analog
sWitch OFF
PC2. high impedance
OFF-state

VIL
VIH

Logic input voltage
LOW
HIGH

VOL
VOH

Logic output voltage3
LOW; at 1101 < 1/lA
HIGH

±Iz
±Iz

20

0.05

20

60

nA

20

0.05

20

60

nA

50

500

nA

0.3Voo

V
V

50

50
0.3Voo

0.3Voo

0.7Voo

0.7Voo

0.7Voo

50
Voo-50mV

Voo-50mV

50
Voo-50mV

mV
mV

10L
10L

Logic output current LOW;
at VOL = 0.5V3
outputs OL. PC2. OUT
output XTAL

5.5
2.8

4.6
2.4

3.6
1.9

mA
mA

-IOH
-IOH

LogiC output current HIGH;
at VOH = Voo - 0.5V3
outputs OL. PC2• OUT
output XTAL

1.5
1.4

1.3
1.2

1.0
0.9

mA
mA

10

Output TCC sink
current3. 4. 5

2.1

mA

-10

Output TCC source
current3. 4. 6

1.9

mA

RI

Internal resistance
of TCC
loutput swing I.;; 200mV
specified output range: 0.3
Voo to 0.7 VOO3• 4

0.7

kU

f)"V

Output TCC voltage
With respect to
TCA Input voltage3• 4. 7

10

Output PC l sink
current3. 4. 9

1.1

mA

-10

Output PCl source
current3. 4. 9

1.0

mA

RI

Internal resistance
of PCl
loutput sWing I.;; 200mV
specified output ran~e:
0.3 Voo to 0.7 Voo . 4

1.4

kU

November 6. 1986

a

a

4-165

a

V

•

Product Specification

Signetics Linear Products

Frequency Synthesizer

HEF4750V

DC ELECTRICAL CHARACTERISTICS (Continued)

HEF4750V, HEC4750V voo = 10V± 5%; voltages are referenced to
Vss = OV, unless otherwise specified. For definitions see Note 1.
LIMITS

TA = -40°C

PARAMETER

SYMBOL

Min

tJ,V

Output PC 1 voltage
with respect to
TCC Input voltage 3 , 4, 10

VEOR

EOR generation
YEOR = Yoo - YTCA 3, 4, 8, 11

10
10

Source current; HIGH
at VOUT = h Voo;
output In ramp mode3, 4
TCA
TCB

Typ

TA
Max

= +25°C

Min

Typ

TA
Max

= +85°C

Min

Typ

UNIT
Max

0

0

0

V

0,9

0.7

0,6

V

13
2,5

mA
mA

AC ELECTRICAL CHARACTERISTICS
General Note
The dynamic specifications are given for the circuit built-up with external components as given in Figure 6, under the following conditions; for
definitions see Note 1; for definitions of times see Figure 17; Voo = 10V± 5%; TA = 25°C; inputtransitlon times ",; 20ns; RA = 68kn ± 30% (see
also Note 4); CA = 270pF; CB = 150pF; Cc = 1nF; Co = 10nF; unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
Min

STCA
STCA
STCB
STCB

Slew rate 11
TCA
TCA
TCB
TCB

ITCA
ITCB

Ramp linearity 13
TCA
TCB

tCBCA

Start of TCA ramp delay

tRCA

Delay of TCA hold

RA = minimum
RA = maximum
RA = minimum
RA = maximum

Typ

Max

52
28
20
10

V//ls
V//ls
V//ls
V//ls

2
2

%
%

200

ns

40

ns

tVCA

Delay of TCA discharge

60

ns

tveB

Start of TCB ramp delay

60

ns

trCB

TCB ramp duration

250
350
450

ns
ns
ns

treB

Required TCB min. ramp duration 14

150

ns

tPWVL
tPWVH

Pulse width
V: LOW
V: HIGH

20
20

ns
ns

VMOO = 4V
VMOO = 6V
VMOO = 8V

tPWRL
tPWRH

R: LOW
R: HIGH

20
20

ns
ns

tPWSL
tPWSH

STB: LOW
STB: HIGH

20
20

ns
ns

50
50

ns
ns

tlCA
tlCB

Fall time
TCA
TCB

November 6, 1986

4-166

Signetics Unear Products

Product Specification

Frequency Synthesizer

HEF4750V

AC ELECTRICAL CHARACTERISTICS (Contined)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

fpR

Prescaler Input frequency

All divIsion ratios

30

fDIV

Binary divider frequency

All diVISion ralios

30

MHz

fose

Crystal oscillator frequency

10

MHz

Icc
Icc

Average power supply current
with speed-up 1.1 0 '5
without speed-up 16

3.6

mA
mA

MHz

Locked state

3.2

NOTES:
1. Definitions.
AA = external biaSing resistor between pins TRA and Vss , 68 kSl± 30%
CA = external timing capacitor for time/voltage converter, between pins TeA and Vss
CB = external timing capacitor for phase modulator, between pins TCB and Vss
Cc = external hold capacitor between pins TCe and VS8
CO = decouphng capacitor between pins TRA and VDD

•

LogiC Inputs. V, R, STB, Ao to Ag, NSo, NS" OSC
LogiC outputs' OL, PC 2 , XTAL, OUT
Analog signals: TCA, TCB, TCC and MOD
2. TRA at Voo, TCA, TCB, TCC and MOD at Vss, logiC Inputs at Vss or Voo
3. All logiC Inputs at Vss or Voo
4. RA connected; Its value chosen such that

ITRA

= 100,UA

5 The analog SWitch IS 10 the ON position

(see Figure t)

vss
Figure 1. Equivalent Cicuit for Note 5
6. The analog sWitch

IS

In

the ON position

(see FIgure 2)

Figure 2_ Equivalent Circuit for Note 6
7. This guarantees the DC voltage gain,
combined with DC offset Input condition

o 3VOD ::; VTCA ::; 0 7VOD

jj,V

= VTCC -

VTCA
10k

TCC
ANALOG

SWITCH

10k

Figure 3, Circuit for Note 7
8. See Figure 4.

pc,
~
~

VDD

1x

TCC

vss
Figure 4. Equivalent Circuit for PC l Sink Current
November 6, 1986

4-167

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

9. See Figure 5.
DD

~
~pc'

TCC

Ix

vss
Figure 5, Equivalent Circuit for PC 1 Source Circuit
10. This guarantees the DC voltage gam, combined with DC offset.
Input condition. 0.3 Voo

flV

= VPC' -

< VTCC .:::0;;; 0 7VDD.

VTCC·

20k

20k

Figure 6, Circuit for Note 10
t 1. SWitching level at TCA, generaling an Ex-OR
signal, dunng Increasing Input voltage
12. See Figure 7.

Figure 7, Waveform at the Output
13. Definition of the ramp linearity at full sWing See
Figure 8.

70%VDD ----~~

30% VDD _ _--.~

NOTE:

IJ,V
Linearity = "'2 Voo X 100%

Figure 8.

t:. V

is the Maximum Deviation of the Ramp Waveform to the Straight
Line, Which Joins the 30% VDD and 70% VDD Points

14. The external components and modulation Input
voltage must be chosen such that this requirement will be fulfilled, to ensure that CA IS
sufficiently discharged dUring that time.

November 6, 1986

4-168

Product Specification

Signetics Linear Products

HEF4750V

Frequency Synthesizer

15. Circuit connections for power supply current
specification, with speed-up 1:10. V and R are

In

the range 01 PC" such that the output voltage at
PC, IS equal to 5V
lose = 5MHz (external clock)
ISTB = 12.5kHz
Iv = 125kHz

r--------1~----_1----+~V

DIVISION RATIO = 40
+5V

'------IR

..n..
..n..

HEF4750V

V

SfB
OL

Vss
iRA

•

'=

Figure 9. Circuit for Note 15
16. CirCUit connections for power supply current
specification, without speed-up. V and R are In
the range 01 PC" such that the output voltage at
PC, IS equal to 5V.
lose = 5MHz (external clock)
ISTB = 12.5kHz
Iv = 12.5kHz

. - - - -....-

NSo
Von
+5V

..n..
..n..

....- - -....--+10V

NS,
DIVISION RATIO = 400

MOD

pc,

R

HEF4750V

V

SfB

OL

Vss

'=

TRA

TCA

teB

'=

Figure 10. Circuit for Note 16

November 6, 1986

4-169

Pc.

Product Specification

Signetics Linear Products

HEF4750V

Frequency Synthesizer

10 Vss OR VDD

Ns" NS,
VDD
MOD

Ao -------------- As

OUT

~

R
HEF4750Y

V

STB
Vss
TRA

Figure 11. Test Circuit for Measuring AC Characteristics

FUNCTIONAL DESCRIPTION
Phase Comparator 1
Phase comparator 1 (PC 1) is built around a
SAMPLE and HOLD circuil. A negative-going
transition at the V input causes the hold
capacitor (CA) to be discharged and, after a

specified delay, caused by the Phase Modulator by means of an internal V' pulse, it
produces a positive-going ramp. A negativegoing transition at the R input terminates the
ramp. Capacitor CA holds the voltage that the
ramp has attained. Via an internal sampling
switch this voltage is transferred to Cc and in

turn buffered and made available at output
PC1'
If the ramp terminates before an R input is
present, an internal end of ramp (EaR) signal
is produced. These actions are illustrated in
Figure 12.

I

v

---------,

I

I

f- ~~':~:~~~E_
v

...... ....
.J .....

TeA
(ANALOG)

VDD

!

/'

I\.
-HOLD

-

RESET

RAMP-

VOLTAGE
TRANSFERRED 10 TCC
HOLD

Vss

!

!r-----------------------------------

EOR

ANALOG
SAMPLING --ON
ON
OFF
SWITCH'S' - - O N - I - - - - - - - - - O F F - - - - - - - - ! - - - O N - - - - - - - - - - -

(AN~~

_.... ...... .......

.... ;F

_____________________________________________c<~...
~_______________________________________

Figure 12. Waveforms Associated With PC1

November 6, 1986

4-170

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

The result phase characteristic IS shown In
Figure 13 PC, IS designed to have a high
gain, typically 3200 V/cycle (at 125kHz) This
enables a low nOise performance.

Phase Comparator 2
Phase comparator 2 (PC2) has a Wide range,
which enables faster lock times to be
achieved than otherWise would be pOSSible It
has a linear ± 360°C phase range, which
corresponds to a gain of tYPically 5V / cycle.
This digital phase comparator has three stable states
• Reset state

Figure 13_ Phase Characteristic of PC,

• V' leads R state
• R leads V' state
Conversion from one state to another takes
place according to the state diagram of Figure 14
Output produces positive or negative-going
pulses with vanable Width; they depend on
the phase relationship of R and V'. The
average output voltage IS a linear function of
the phase difference Output PC 2 remains In
the high-Impedance OFF state In the region In
which PC, operates. The resultant phase
charactenstlc IS shown In Figure 15.

ACTIVE R·EDGE
(NEGATIVE GOING)

ACTIVE R-EDGE
(NEGATIVE GOING)

ACTIVE V-EDGE
(NEGATIVE GOING)

ACTIVE V-EDGE
(NEGATIVE GOING)

•

Figure 14. State Diagram of PC 2

Strobe Function
The strobe function IS Intended for applications reqUlnng extremely fast lock times. In
normal operation the additional strobe Input
(STB) can be connected to the V Input and
the CIrCUIt Will function as descnbed In the
prevIous sections.
In single, phase-locked loop type frequency
syntheSizers, the companson frequency generally used IS either the nominal channel
spacing or a sub-multiple, PC2 runs at the
higher frequency (a higher reference frequency must also be used), while strobing takes
place on the lower frequency, thereby obtainIng a decrease In lock time In a system uSing
the Universal D,v,der HEF4751V, the output
OFS cycles on the lower frequency, the
output OFF cycles on the higher frequency

Out-of-Lock Function
There are a number of situations In which the
system goes from the locked to the out-oflock state (OL goes HIGH)
1. When V' leads R, however out of the range
of PC,.
2 When R leads V'.
3 When an R pulse IS missing.
4 When a V pulse IS missing
5 When two successive STB commands
occur, the first without corresponding V signal.

Phase Modulator
The phase modulator only uses one external
capaCitor, Cs at pin TCB A negative-going
November 6, 1986

./

Figure 15. Phase Characteristics of PC2
transition at the V Input causes Cs to produce
a positive-gOing linear ramp. When the ramp
has reached a value almost equal to the
modulation Input voltage (at MOD), the ramp
terminates, Cs discharges and a start Signal
to the CA ramp at TCA IS produced. A linear
phase modulation IS reached In thiS way. If no
modulation IS reqUIred, the MOD Input must
be connected to a fixed voltage of a certain
positive value up to Vaa. Care must be taken
that the V' pulse IS never smaller than the
minimum value to ensure that the external
capacitor of PC,(CA) can be discharged durIng that time Since the V' pulse Width IS
directly related to the TCB ramp duration,
there IS a requirement for the minimum value
of thiS ramp duration.

Reference Oscillator
The reference OSCillator normally operates
with an external crystal as shown In the block
diagram. The Internal CIrCUitry can be used as
a buffer amplifier In case an external reference should be reqUIred

4-171

Reference Divider
The reference diVider consists of a binary
diVider With a programmable diVISion ratio of
1-to-1024 and a prescaler With selectable
diVISion ratios of 1, 2, 10 and 100, according
to the follOWing tables:

Binary divider
N (Ao TO Ag)

DIVISION RATIO

0
0";; N";; 1023

1024
N

Prescaler
PROGRAMMING
WORD
(NSo, NSd

DIVISION RATIO

0
1
2
3

1
2
10
100

Signetics Linear Products

Product Specification

Frequency Synthesizer

In this way, suitable comparison frequencies
can be obtained from a range of crystal
frequencies. The diVider can also be used as
a 'stand-alone' programmable divider by connecting input TRA to Voo, which causes all
Internal analog currents to be sWitched off.

HEF4750V

TRA

>---

HEF4750V

Biasing Circuitry
The biasing cirCUitry uses an external current
source or resistor, which has to be connected
between the TRA and Vss pins. ThiS CirCUitry
supplies all analog parts of the CIrCUIt. Consequently the analog properties of the device,
such as gain, charge currents, speed, power
dissipation, Impedance levels, etc., are mainly
determined by the value of the Input current
at TRA. The TRA Input must be decoupled to
Voo, as shown In Figure 16. The value of Co
has to be chosen such that the TRA Input IS
'clean', e.g., 10nF at RA = 68kn.

Figure 16. Oecoupling of Input TRA

v
-----t-~---------tpWVL---------_I

R

----.J-----------tpWRl-----------..J
STB
---+~-----------tpWSL------------l

FORBI~g~~ --------------l-~

"""'""""1"""""'"""1
-------------~-~--~--~------------------------VDD

(ANA~ --------------l-~~'I11%

____________________~--~~~~~__---------------------------------V~
-------------~r_~--t-~--------------------------VDD

lCB
(ANAlOG)

l'~-----------------------------------------v~
NOTE:
1 Forbidden zone

In

the locked state for the POSitive edge of V and A and both edges of STB

Figure 17. Waveforms Showing Times in the Locked State

November 6, 1986

4-172

Signetics

HEF4751V
Universal Divider
Product Specification

Linear Products

DESCRIPTION

FEATURES

The HEF4751V is a universal divider
(UD) intended for use in high-performance phase-locked loop frequency
synthesizer systems. It consists of a
chain of counters operating in a programmable feedback mode. Programmable feedback signals are generated
for up to three external (fast) .;- 10/11
prescalers.

(in combination with HEF4750V) are:
• Wide choice of reference
frequency using a single crystal

The system comprising one HEF4751V
UD together with prescalers is a fullyprogrammable divider with a maximum
configuration of 5 decimal stages, a
programmable mode M stage
(1 .;;;; M .;;;; 16, non-decimal fraction channel selection), and a mode H stage
(H = 1 or 2, stage for half-channel offset). Programming is performed in BCD
code in a bit-parallel, digit-serial format.
To accommodate fixed or variable frequency offset, two numbers are applied
in parallel, one being subtracted from
the other to produce the internal program. The decade selection address is
generated by an internal program counter which may run continuously or on
demand. Two or more universal dividers
can be cascaded. Each extra UD (in
slave mode) adds two decades to the
system. The combination retains the full
programmability and features of a single
UD. The UD provides a fast output signal
flip-flop at output OFF, which can have a
phase jitter of ± 1 system input period, to
allow fast frequency locking. The slow
output signal FS at output OFS, which IS
jitter-free, is used for fine phase control
at a lower speed.

PIN CONFIGURATION

• High-performance phase
comparator -low phase noiselow spurii
• System operation to > 1GHz
• Typical 15MHz input at 10V
• Flexible programming:
frequency offsets
ROM compatible
fractional channel capability
• Program range 6.5 decades,
including up to 3 decades of
prescaler control
• Division range extension by
cascading
• Built-in phase modulator
• Fast lock feature
• Out-of-Iock indication
• Low power dissipation and high
noise immunity

F,N Packages

•
10PVIEW
CD112OO$

PIN
NO.

A3
A2

~1

~
00.
~s

APPLICATIONS
• VHF/UHF mobile radios
• HF SSB transceivers
• Airborne and marine
communications and navigations
• Broadcast transmitters
• High quality radio and television
receivers
• Signal generators

SYMBOL

QQ4

B

9
10
11
12
13

l'

15
16
17
18
19
20
21
22
23

2'
25
26
27
28

003
llll2

00,

000
PE
PC

DESCRIPTION

} Data Input,

)--Program enable
Program clock

V,s
51

~o
B,

} BOITOW onput
Data Inputs

62
83
IN

Input

5SY

Sync output

OFB,
C5Fll2
OFBs
OF5

AT
OFF

} Proscaler control outputa
Output signal (slow)
Rate inPut
Output signal (FAST]

Voo

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pln Plastic DIP (SOT-l17)

-40·C to + 85·C

HEF4751VPN

28-Pin Cerdlp (SOT-135A)

-55·C to + 125·C

HEC4751VDBF

November 14, 1986

4-173

853-0107 86553

Signetics Linear Products

Product Specification

Universal Divider

HEF4751V

BLOCK DIAGRAM
SI

4

3

2

1

15

000

11 10 9

8

7

PC

00.

------

6

PE
12

13

5

I

SUBTRACTO~

PROGRAM DECODER
PROGRAM
COUNTER

C

D

0

CARRYFF

RS
Swm:HES

OFB.

OFB2

OFB,

24

23

I
I
I
I

22

RS3

I

LATCH

RS2

I

LATCH

..

"2

I
I

RS1

----LATCH

n,

November 14, 1986

i

RSO

I+_-+_.......~~---LATCH
~d,

4-174

do_

"0

r--I-

RSH

f----....
LATCH
ii,

""_

""

.-

f!!.o Ri

Signetics Linear Products

Product Specification

:1
I

Universal Divider

HEF4751V
I

I
ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VDD

Supply voltage

RATING

UNIT

-0.5 to + 15

V

V,

Voltage on any Input

-05 to VDD +0.5

V

±I

DC current into any Input or output

10

mA

PTOT

Total power dissipation per package
for TA = 0 to +85°C

500

mW

PD

Power dissipation per output for
TA = 0 to +85°C

100

mW

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operaling ambient temperature range

-40 to +85

°C

DC ELECTRICAL CHARACTERISTICS

Vss

!1

= OV
LIMITS

SYMBOL

PARAMETER

Voo
(V)

VOH
(V)

VOL
(V)

TA

=-40°C

Min
IOL

-IOH

Output (sink)
current LOW
Output (source)
current HIGH

4.75
5
10
5
5
10

AC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL
tpHL

Propagation delay
IN ~ OSy
HIGH-to-LOW

0.4
0.4
05
4.6
2.5
9.5
Vss

= OV;

TA

Max

=+25°C

TA
Min

TA

Max

=+85°C

Min

UNIT

Max

1.6
1.7
2.9

1.4
1.5
2.7

1.1
1.2
2.2

mA
mA
mA

1.0
30
30

085
2.5
2.5

055
1.7
1.7

mA
mA
mA

= 25°C;

Input transition times

TEST CONDITIONS

CL = 10pF

<: 20ns.

Voo
(V)

LIMITS
UNIT
Min

Typ

Max

5
10

135
45

270
90

ns
ns

5
10
5
10

30
12
45
20

60
25
90
40

ns
ns
ns
ns

Output transllion times
tTHL

HIGH-to-LOW

C L = 50pF

tTLH

LOW-to-HIGH

CL = 50pF

fMAX

Maximum Input frequency; IN

fMAX

Maximum Input frequency, IN

fMAX

Maximum Input frequency; PC

8= 50%

i Cab ratio> 1
8= 50%
i Cab ratio = 1

5
10

4
12

8
24

MHz
MHz

5
10

2
6

4
12

MHz
MHz

5
10

0.15
0.5

0.3
1.0

MHz
MHz

Typical Formula for P ("W)
PD

Dynamic power dissipation per
package (P) 1

5V
10V

NOTE:
f, = Input frequency (MHz)
fo = output frequency (MHz)
GL = load capacitance (pF)
~ (foGd = sum of outputs
Voo = supply voltage (V)

November 14, 1986

4-175

1 200 f, + L (foCLl X VDD2
5 400 f, + L (foCLl X VDD 2

Signetics Linear Products

Product Specification

HEF4751V

Universal Divider

.----------~~

C2

C3

-10

+M

C4

INPUT

OFS

(f~

RS4

".
RS3

",
RS2

",
RSO

RS1

: OFB,
EXTERNAL PRESCALER

NOTES:
1';;;;M~16; 1";;;;:H,2, "5>0, fllfOFS'''j(n50104

UNIVERSAL DIVIDER

n,

+ n40103+n3"102+n2"10+nl) M+no! H+nh

Figure 1. The HEF4751V UD Used in a System With 3 (Fast) Prescalers

November 14, 1986

OFF

4-176

RSH

Product Specification

Signetics Linear Products

HEF4751V

Universal Divider

PC

PE

n-

51 IlIL IL IL IIn-n-IL IIn-lllli1JL
II

----1

---

I--

---

I--

•

I--

I--

-

--DATA VALID
(SHADED)

FETCH PERIOD

I--

~
6

I

~ ~ ~ ~ ~ ~ ~
10

11

12

13

14

Is

16

I

~ ~ ~
10

11

Figure 2. Timing Diagram Showing Program Data Inputs

November 14, 1986

4-177

161 6

I

6

I

6

Product Specification

Signetics Linear Products

HEF4751V

Universal Divider

Allocation of Data Input
INPUTS

FETCH
PERIOD

A3

A2

A1

0
1
2
3
4
5

nOA
n1A
n2A
n3A
n4A
nSA

6

M

AD

83

82

81

Sl

Bo

n08
n18
n28
nS8
n48
nS8
COb
control

I

bin
X
X
X
X
X
)12 channel
control

X

Allocation of Data Input 83 to 80 During Fetch Period 6
B3

B2

COb DIVISION RATIO

Bl

Bo

L
L
H
H

L
H
L
H

1
2
5
10/11

L
L
H
H

L
H
H
L

1'2

CHANNEL CONFIGURATION
H= 1
H = 2, nh = 0
H=2;nh=1
test state

H - HIGH state (the more positive voltage)
L - LOW state (the less positive voltage)
X = state IS Immatenal

PROGRAM DATA INPUT (see
also Figures 1 and 2)

P = A - B - bin or If thiS result IS negative;
P=A-B-b ln +M·10 s.

The programming process IS timed and controlled by Input PC and PE When the program enable (PE) Input IS HIGH, the poSItive
edges of the program clock (PC) signal step
through the Internal program counter In a
sequence of 8 states. Seven states define
fetch penods, each Indicated by a LOW signal
at one of the corresponding data address
outputs (000 to 006) These data address
signals may be used to address the external
program source The data fetched from the
program source IS applied to Inputs Ao to As
and 60 to 6s When PC IS LOW In a fetch
penod, an Internal load pulse IS generated.
The data IS valid dunng thiS time and has to
be stable When PE IS LOW, the programming
cycle IS Interrupted on the first positive edge
of PC. On the next negative edge at Input PC,
fetch penod 6 IS entered. Data may enter
asynchronously In fetch penod 6.

The numbers A and B, each consisting of SIX
four bit digits nA to nSA and n08 to nS8, are
applied In fetch penod 0 to 5 to the Inputs Au
to As (data A) and 6 0 to 6s (data B) In binary
coded negative logiC.

Ten blocks In the UD need program Input
signals (see Block Diagram). Four of these
(COb, C3, C4 and RSH) are concerned with
the configuration of the U0 and are programmed In fetch penod 6. The remaining
blocks (RSO to RS4 and Cl) are programmed
with number P, consisting of SIX Internal digits
no to ns.
P=(nS ' 104+n4 ' 10S +ns ' 102+n2 '
10 + nl) , M + no
These digits are formed by a substractor from
two external numbers A and B and a borrowIn (bin)
November 14, 1986

A= (nSA • 104 + n4A • lOS + nSA
102 +n2A' 10+n1l0' M+nOA
B = (nS8' 104 + n48' lOS + nS8' 102 + n28 •
10+n18)' M+n08
BorrOW-in (bin) IS applied via Input SI in fetch
penod 0 (SI = HIGH borrow; SL = LOW· no
borrow).
Counter Cl IS automatically programmed with
the most significant non-zero digit (n ms) from
the Internal digits ns to n2 of number P The
counter chain C - 2 to Cl (Figure 1) IS fully
programmable by the use of pulse rate feedback.
Rate feedback IS generated by the rate selectors RS4 to RSO and RSH, which are programmed with digits n4 to no and nh, respectively In fetch penod 6 the fractional counter
C3, half-channel counter C4 and COb are
programmed and configured via data B inputs. Counter C3 IS programmed In fetch
penod 6 via data A Inputs in negative logiC
(except all HIGH IS understood as: M = 16).
The counter CO IS a Side steppable 10/11
counter composed of an Internal part COb and
an external part CO a. COb IS configured via 6 s
and 62 to a diVISion ratio of lor 2 or 10/11;
CO. must have the complementary ratio 101

4-178

11 or 5/6 or 2/3 or 1, respectively. In the
latter case, COb compnses the whole CO
counter with Internal feedback. COa IS then
not reqUired.
The half channel counter C4 is enabled with
6 0 = HIGH and disabled With 6 0 = LOW With
C4 enabled, a half channel offset can be
programmed With Input 6 1 = HIGH, and no
offset With 6 1 = LOW.

FEEDBACK TO PRESCALERS
(see also Figures 3 and 4)
The counters Cl, CO, C - 1 and C - 2 are
slde-steppable counters, I.e., their diVision
ratio may be Increased by one, by applying a
pulse to a control terminal for the duration of
one diVISion cycle. Counter C2 has 10 states,
which are accessible as timing signals for the
rate selectors RSl and RS4. A rate selector,
programmed With n (nl to n4 In the UD)
generates n of 10 baSIC timing penods an
active signal. Since n .;; 9, 1 of 10 periods IS
always non-active. In thiS penod RSl transfers the output of rate selector RSO, which IS
timed by counter C3 and programmed With
no. Similarly, RSO transfers RSH output durIng one penod of C3. Rate selector RSH IS
timed by C4 and programmed with nh. In one
of the two states of C4, If enabled, or always,
If C4 IS disabled, RSH transfers the LOW
active signal at Input
to RSO. If
IS not
used it must be connected to HIGH. The
feedback output signals of RS 1, RS2 and
RS3 are externally available as active LOW
signals at outputs OFB1, OFB2 and OFBs.

m

m

Output OFB1 IS Intended for the prescaler at
the highest frequency (If present), OFB2 for

Signetics Linear Products

Product Specification

Universal Divider

HEF4751V

the next (01 present) and lJFB3 for the lowest
frequency prescaler (If present) A prescaler
needs a feedback signal, which IS timed on
one of Its own division cycles In a basIc timing
period. The timing signal at OSY IS LOW
dunng the last UD Input period of a basIc
timing period and IS suitable for timing of the
feedback for the last external prescaler. The
synchronization signal for a preceding prescaler is the OR-funcllon of the sync. Input and
sync. output of the follOWing prescaler (all
sync. signals active LOW).

CASCADING OF UDs (see
Figure 6)
A UD is programmed Into the 'slave' mode by
the program Input data. n2A = 11, n28 = 10,
n3A = n4A = n38 = n48 = nS8 = O. A UD operating in the slave mode performs the function

of two extra programmable stages C2' and
C3' to a 'master' (not slave) mode operating
UD More slave UDs may be used, every
slave adding two lower significant digits to the
system.
Output DFB3 IS converted to the borrow
output of the program data subtraclor, which
is vahd after fetch penod 5. Input SI is the
borrow Input (both In master and In slave
mode), which has to be valid In fetch penod O.
Input SI has to be connected to output OFB3
of a following slave, If not present to LOW.
For proper transfer of the borrow from a lower
to a higher significant UD subtractor, the UDs
have to be programmed sequentially In order
of significance or synchronously 01 the program IS repeated at least the number of UDs
In the system.
Rate Input AT and output OFS must be
connected to rate output DFBl and the Input

IN of the next slave UD. The combination
thus formed retains the full programmablhty
and features of one UD.

OUTPUT (see Figure 5)
The normal output of the UD IS the slow
output OFS, which consists of evenly spaced
LOW pulses.
This output IS intended for accurate phase
comparison. If a better frequency acquisition
time is reqUired, the fast output OFF can be
used. The output frequency on OFF IS a
factor M - H higher than the frequency on
OFS. However, phase jitter of maximum ± 1
system Input penod occurs at OFF, since the
diVISion ratio of the counters preceding OFF
are vaned by slow feedback pulse trains from
rate selectors follOWing OFF.

~T6

OUT' 1--+-1

UNIVERSAL DIVIDER

Figure 3. Block Diagram Showing Feedback to Prescalers

November 14, 1986

4-179

4

Signetics Linear Products

Product Specification

HEF4751V

Universal Divider

BASlClIMING PERIOD

BASIC liMING PERIOD

BASIC liMING PERIOD

(11-1)

(n)

(0+1)

IN'

-----------------------------------~----------------------------------r_;.--~~--WF17990S

NOTE:
1 Scaling factor

Figure 4. Timing Diagram Showing Signals Occurring In Figure 3

OFS

OFF

~
1--------------------- (M'H) PULSES -----------------------l
Figure 5. Timing Diagram Showing Output Pulses

November 14, 1986

4-180

L

Product Specification

Signetics Linear Products

Universal Divider

HEF4751V

., lOa.

I--

PC

"o'lOAo'
PC'

PE

I
I

PE'

110'10 a.'

DATA
SUB11lAC1OR

DATA
SUBTRACTOR

51'

OFS'
L-_ _ _ _ _ _ _ _

~

O~9---~----+-----~

L--------------------MASI'ER UNIVERSAL DIVIDER
«"u"9; n2B<9)

~

SLAVE UNIVERSAL DIVIDER

--------------(n2A- 11;rtm=1O)

Figure 6. Block Diagram Showing Cascading of UDs

November 14, 1986

4-181

-

-

~------

J

OF!"

iii'

Signetics

SAA1057
PLL Radio Tuning Circuit
Product Specification

Linear Products

DESCRIPTION
The SAA 1057 performs the entire PLL
synthesizer function (from frequency inputs to tuning voltage output) for all
types of radios with the AM and FM
frequency ranges.
The circuit comprises the following:
• Separate Input amplifiers for the
AM and FM VeO-signals.
• A divlder-by-10 for the FM channel.
• A multiplexer which selects the AM
or FM input.
• A 15-blt-programmable divider for
selecting the required frequency.
• A sample-and-hold phase detector
for the in-lock condition, to achieve
the high spectral purity of the veo
signal.
• A digital memory frequency/phase
detector, which operates at a 32
times higher frequency than the
sample-and-hold phase detector, so
fast tuning can be achieved.
• An in-lock counter detects when
the system is In-lock. The digital
phase detector is switched-off
automatically when an In-lock
condition is detected.
• A reference frequency oscillator
followed by a reference divider. The
frequency is generated by a 4MHz
quartz crystal. The reference
frequency can be chosen either
32kHz or 40kHz for the digital
phase detector (that means 1kHz
and 1.25kHz for the sample-andhold phase detector), which results
in tuning steps of 1kHz and
1.25kHz for AM, and 10kHz and
12.5kHz for FM.
• A programmable current amplifier
(charge pump), which controls the
output current of both the digital
and the sample/hold phase
detector in a range of 40dB. It also
allows the loop gain of the tuning
system to be adjusted by the
microcomputer.
• A tuning voltage amplifier, which
can deliver a tuning voltage of up
to 30V.
November 14, 1986

• BUS: this circUitry consists of a
format control part, a 16-bit shift
register and two 15-bit latches.
Latch A contains the to be tuned
frequency Information In a binary
code. This binary-coded number,
multiplied by the tumng spacing, IS
equal to the synthesized frequency.
The programmable divider (without
the fixed dlvlde-by-l0 prescaler for
FM) can be programmed In a
range between 512 and 32,767.
Latch B contains the control
information.

FEATURES

PIN CONFIGURATION
N Package

TOP VIEW

• On-chip prescaler with up to
120MHz input frequency
• On-chip AM and FM input
amplifiers with high sensitivity
(30mV and 10mV, respectively)
• Low current drain (typically 16mA
for AM and 20mA for FM) over a
wide supply voltage range (3.6V
to 12V)
• On-chip amplifier for loop filter
for both AM and FM (up to 30V
tuning voltage)
• On-chip programmable current
amplifier (charge pump) to adjust
the loop gain
• Only one reference frequency for
both AM and FM
• High signal purity due to a
sample and hold phase detector
for the in-lock condition
• High tuning speed due to a
powerful digital memory phase
detector during the out-lock
condition
• Tuning steps for AM are: 1kHz
or 1.25kHz for a VCO frequency
range of 512kHz to 32MHz
• Tuning steps for FM are: 10kHz
or 12.5kHz for a VCO frequency
range 70MHz to 120MHz
• Serial 3-line bus interface to a
microcomputer

APPLICATIONS
• Hi-Fi radios
• Auto radios
• Communication receivers

• Test/features

4-182

853-0956 86556

Product Specification

Signetics Linear Products

SAA1057

PLL Radio Tuning Circuit

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-Pin Plastic DIP (SOT-102HE)

-25·e to + 80·e

SAA1057N

BLOCK DIAGRAM
TR

IN

TCA TC8

FFM

•

OCA

FAM

VCC1

c>"i--------

vcco

016,._ _ _p--_ __

CURRENT
DCS

•

STABIUZER

v.., o-:::
'5i -_ _......_ ___
t---i;;;:.160TEST

OLEN

13

CLB

1.

DATA

12

8USII.DAD

•

SAA1057

CONTROl.

LOGIC

November 14, 1986

4-183

Product Specification

Signetics linear Products

SAA1057

PLl Radio Tuning Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

VCC1: VCC2

Supply voltage; logic and analog part

-0.3 to 13.2

V

VCC3

Supply voltage; output amplifier

VCC2 to +32

V

PTOT

Total power dissipation

TA

Operallng ambient temperature range

TSTG

Storage temperature range

DC AND AC CHARACTERISTICS

800

mW

-30 to +85

'C

-65 to + 150

'C

VEE = OV; VCCl = VCC2 = 5V; VCC3 = 30V; TA = 25'C, unless otherwise specified.
LIMITS

SYMBOL

VCCl
VCC2
VCC3
ITOT

PARAMETER

TEST CONDITIONS

Supply voltages

UNIT
Min

Typ

Max

3.6
3.6
VCC2

5
5

12
12
31

Supply currents 1
AM mode

V
V
V

16

mA

20

mA

ITOT = ICCl + ICC2 in-lock:
BRM = '1';
FM mode

ITOT

PDM = '0' lOUT = 0
0.3

Icc3

0.8

1.2

mA

RF inputs (FAM, FFM)
fFAM

AM input frequency

512kHz

32

MHz

fFFM

FM input frequency

70

120

MHz

VI(RMS)

Input voltage at FAM

30

500

mV

VI(RMS)

Input voltage at FFM

10

500

mV

RI

Input resistance at FAM

2

RI

Input resistance at FFM

135

kn
n

CI

Input capacitance at FAM

3.5

pF

CI

Input capacitance at FFM

3

pF

VSIVNS

Voltage ratio allowed between selected and
non-selected input

-30

dB

Crystal oscillator (XTAL)2
fXTAL

Maximum input frequency

Rs

Crystal senes resistance

MHz

4
150

n

BUS inputs (OLEN, CLB, DATA)
VIL

Input voltage LOW

0

0.8

V

2.4

VCCl

V

VIH

Input voltage HIGH

-IlL

Input current LOW

VIL =0.8V

10

IlA

IIH

Input current HIGH

VIH = 2.4V

10

IlA

November 14, 1986

4-184

Product Specification

Signetics Linear Products

SAA1057

Pll Radio Tuning Circuit
DC AND AC CHARACTERISTICS (Continued)

VEE = OV; VCCl = VCC2 = 5V; VCC3 = 30V; T A = 25'C, unless otherwise
specified.
LIMITS
TEST CONDITIONS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

BUS inputs timing 3 (OLEN, CLB, DATA)
tCLBlead

Lead time for CLB to OLEN

tTlead

Lead time for OATA to the first CLB pulse

1

I1s

0.5

I1S

tcLBlagl

Setup time for OLEN to CLB

5

I1S

tcLBH

CLB pulse width HIGH

5

I1s

tCLBL

CLB pulse width LOW

5

I1s

tOATAlead

Setup time for DATA to CLB

2

I1S

tOATAhoid

Hold time for OATA to CLB

0

I1s

tOLENhoid

Hold time for OLEN to CLB

2

I1s

tcLBlag2

Setup time for OLEN to CLB load pulse

2

I1s

tOIST

Busy time from load pulse to next start of
transmission

5

I1S

tOIST
tOIST

Busy time
Asynchronous mode
Synchronous mode6

0.3
1.3

ms
ms

After word 'B' to other
device

Sample-and-hold circuit 4, 5 (TR, TCA, TCB)
VTCA, VTCB

Minimum output voltage

VTCA, VTCB

Maximum output voltage

~CA
~CA

Capacitance at TCA
(external)

tOIS
tOIS

Discharge time at TCA

1.3

V
VCC2- 0.7

V

REFH = 'I'
REFH ='0'

2.2
2.7

nF
nF

REFH = 'I'
REFH = '0'

5
6.25

I1S
I1 s

n

RTR

Resistance at TR (external)

VTR

Voltage at TR during discharge

100

CTCB

Capacitance at TCB (external)

10

nF

IBIAS

Bias current into TCA, TCB in·lock

10

nA

0.7

V

Programmable current amplifier (PCA)
± IOIG

Output current of the digital phase detector

0.4

rnA

0.023
0.07
0.23
0.7
2.3

dB
dB
dB
dB
dB

1.0

I1AN

Current gain of PCA
VCC2;;' 5V (only for PI)

PI
P2
P3
P4
P5

Gpl
Gp2
Gp3
Gp4
Gp5

CP3

CP2

CPl

CPO

0
0
0
0
1

0
0
0
1
1

0
0
1
1
1

0
1
0
0
0

I

STCB

Ratio between the output current of StH Into
PCA and the voltage on CTCB

~VTCB

Offset voltage on TCB
12 In·lock

November 14, 1986

1

4-185

V

•

Product Specification

Signetics Linear Products

SAA1057

PLL Radio Tuning Circuit

DC AND AC CHARACTERISTICS (Continued)

VEE = OV; VCCl = VCC2 = 5V; VCC3 = 30V; T A = 25'C. unless otherwise
specrfred.
LIMITS

SYMBOL

UNIT

TEST CONDITIONS

PARAMETER

Min

Typ

Max

Output amplifier (IN, OUT)
VIN

VOUT
VOUT
VOUT
±IOUT

Input voltage
in-lock; equal to internal reference voltage

1.3

Output voltages
minimum
-lOUT = 1mA
maximum
lOUT = 1mA
maximum
IOUT=O 1mA
Maximum output current. VOUT =

V

V

0.5

1t2

VCC3

VCC3- 2

V

VCC3 -1

V

5

mA

Test output (TEST) 7
VTL

Output voltage LOW

0.5

V

VTH

Output voltage HIGH

12

V

ITOFF

Output current OFF. VTH

10

p.A

ITON

Output current ON. VTL

p.A

150

Ripple rejection (see Frgure 4)
At fRIPPLE = 100Hz
tJ.VCC1/ tJ.VOUT
tJ. VCC2/ tJ. VOUT
tJ.VCC3/ tJ.VOUT
VOUT 17) must be the same as the
next transmission to the SAA 1057 When the other device has a separate OLEN or has less clock pulses than the SAA 1057 It IS
keep to this busy-time, 511S Will be sufflclsnt
Open-collector output

November 14. 1986

4-186

detector. The

1;2 VCC2 + O.3V.
busy-time for a
not necessary to

Signetics Linear Products

Product Specification

SAA1057

PLL Radio Tuning Circuit

OPERATION DESCRIPTION
Control Information
The following functIons can be controlled wIth
the data word bits in latch B. For data word
format and bit position see FIgure 2.
FM
FM/AM selection; '1' = FM, '0' = AM
REFH
Reference frequency selecMn; '1' = 1.25kHz, '0' = 1kHz (sample-and-hold phase detector)
CP3 }
CP2
CPl
CPO

Control bIts for the programmable current amplifier
(see section CharacteristIcs)

SB2

enables last 8 bits (SLA to TO) of data word B; '1'
word B wIll be set to '0' automat,cally

SLA

Load mode of latch A; '1' = synchronous, '0'

PDMI
PDMO

Phase detector mode
PDMI PDMO

0
1
1
BRM

= enables,

'0'

= dIsables;

when programmed '0', the last 8 bits of data

= asynchronous

DIGITAL PHASE DETECTOR

Automatic on/off
on
off

X
0
1

Bus receiver mode bit; in thIS mode the supply current of the BUS receiver will be sWItched-off automatically aiter a data
transmissIon (current-draw is reduced); '1' = current switched; '0' = current always on

T3

Test bit; must be programmed always '0'

T2

Test bit; selects the reference frequency (32 or 40kHz) to the TEST pIn

Tl

Test bIt; must be programmed always '0'

TO

Test bIt; selects the output of the programmable counter to the TEST pIn
TEST (PIN 18)

T3

T2

Tl

TO

0

0

0

0

0

1

0

0

Reference frequency

0

0

0

1

Output programmable counter

0

1

0

1

Output In-lock counter
'0' = out-lock
'1' = In-lock

November 14, 1986

1

4-187

•

Signetics Linear Products

Product Specification

PLL Radio Tuning Circuit

SAA1057

For the complete initialization (defining all
control bits) a transmission of word B should
follow. This means that the IC is ready to
accept word A.

achieved when bit' SLA' of word B is set to
'1'. This mode should be used for small
frequency steps where low tUning nOise is
important (e.g., search and manual tUning).
ThiS mode should not be used for frequency
changes of more than 31 tuning steps. In this
case asynchronous loading is necessary.
This IS achieved by setting bit 'SLA' to '0'.
The in-lock condition will then be reached
more quickly, because the frequency information is loaded immediately Into the divider.

Synchronous/Asynchronous
Operation

Restrictions to the Use of the
Programmable Current Amplifier

APPLICATION INFORMATION
Initialize Procedure
Either a train of at least 10 clock pulses
should be applied to the clock input (CLB) or
word B should be transmitted, to achieve
proper initialization of the device.

Synchronous loading of the frequency word
into the programmable counter can be

voltage VCC2 is below 5V (CP3, CP2, CPl and
CPO are all set to '0'). This IS to avoid
possible instability of the loop due to a too
small range of the sample and hold phase
detector in this condition.

Transient Times of the Bus
Signals
When the SAA 1057 is operating In a system
with continuous activity on the bus lines, the
transient times at the bus inputs should not
be less than 1DOns. Otherwise the signal-tonoise ratio of the tuning voltage is reduced.

The lowest current gain (0.023) must not be
used In the In-lock condition when the supply

OLEN

CLB

DATA

BITHo.

IS

NOTE:
1 Durmg the zero setup time (tL2su) CLB can be LOW or HIGH, but no tranSient of the signal IS permitted ThiS can be
of use when an 12C bus IS used for other devices on the same data and clock lines

Figure 1. BUS Format

DATA WORD A

Figure 2. Bit Organization of Data Words A and B

November 14, 1986

4-188

,.

Signetics Linear Products

Product Specification

Pll Radio Tuning Circuit

+5V-

10nF 22k

o V Jlf o-t
4MHz

C

SAA1057

17

~5

XTAL

XTALIpF

Figure 3. Circuit Configuration Showing
External 4MHz Clock

TUNER

OUT~______r-~10~k~('~)__+-__r-~~~~~~E

DCS

I

.L 100nF(,)

DCA

T
I

IN

-=k-

SAA1057

TEST

17

22nF

A». OSCILLATORo----j

18

11 FA».

XTAL

(Z, = 2 kO)

1

OLEN

13

CLB

14

DATA

1
12

VEE

4 MHz

27 pF

DH~

15

V

~

BUS

NOTE:
Values depend on the tuner diode charactensttcs

Figure 4. Application Example of the SAA 1057 PLL Frequency Synthesizer Module

November 14, 1986

4-189

•

Signetics

AN196
Single-Chip Synthesizer for
Radio Tuning
Application Note

Linear Products

Authors' J. Matull and J. Van Straaten
To remain competitive, manufacturers of domestic radios must not only produce a comprehensive range of reliable equipment with
the required performance at the right pnce,
but must also meet the needs of the market
with regard to styling, ease of operation and
available functions. Although the widespread
use of Integrated CirCUitS has allowed vast
Improvements of performance and reliability
and has increased the range of available
facilities, the integrated circuits are not always optimally matched, resulting In partial
redundancy and a large number of peripheral
components. We foresaw this problem and
were able to avoid It by uSing a total systems
approach to manufacture our comprehensive
range of Ideally-matched Integrated circuits
lor signal processing and digital control of
tUning, displays and analog functions In all
classes of radio. We can now, therefore,
devote our design resources and considerable knowledge of integration technologies
and techniques to reducing radio manufacturers' development and assembly costs by
minimizing the number of Integrated CirCUitS
needed to implement the wide range of
features and facIlities required In today's
radios.
If a radio must Incorporate facIlities such as
search tUning and/or tuning by direct entry of

December 1988

frequency at a keyboard, vanable-capacltance diode tuning must be used and a stable
local oscillator signal can be generated by
indirect frequency synthesIs with a phaselocked loop (PLL) controlled by a microcomputer. We have now used bipolar technology
to combine analog CirCUitS with several types
of logic (l2L, ECL and mlnlwatt) so that all the
functions previously performed by three integrated circuits can be performed by a single
18-pin LSI integrated circuit called synthesIzer module SAA 1057. The component economy afforded by the SAA 1057 IS amply Illustrated by Figure 1 which shows that tUning
synthesizer functions which previously required the use of three integrated CirCUitS and
a large number of penpheral components can
now be performed by the SAA 1057 and only
16 penpheral components.
The SAA 1057 IS not only economical with
regard to the reqUired number of components. It also consumes very little current
( < 20mA) and IS able to meet the vaned
performance requirements of all classes of
radio from battery-powered portables to
mains-powered hi-fi tuners. For example, a
novel tWin-phase detector system In the PLL
achieves the fast tuning often reqUired for car
radios and also ensures that, when the PLL IS
locked, the VCO signal has high spectral

4-190

pUrity to ensure low distortion In hi-fi tuners.
The wide frequency range (AM 512kHz to
32M Hz, FM 70MHz to 120MHz) and high
maximum tUning voltage (30V) make the
SAA 1057 suitable for multi-waveband mains
sets. The low current consumption combined
with the wide supply voltage range (3.6V to
12V) due to Internal stabilization allow It to be
used in battery-powered portables.
In addition to the basic function of tUning by
direct entry of frequency, the SAA 1057 can
also provide the following software-controlled
facilities:
• Search tuning with muted interstatlon
noise
• Continuous up/down step tuning
(manual tUning)
• Accurate storage and automatic tuning
to preset frequencies
• Loading of frequency data in
synchronism with the sampling
frequency to prevent disturbance of the
tuning lock
• Feed out of a number of Internal
signals for alignment purposes
• Adjustment of PLL current gain over
40dB range (0.023 to 2.3) to eliminate
switching of external loop filter
components dunng waveband selection.

Application Note

Signetics Linear Products

Single-Chip Synthesizer for Radio Tuning

AN196

•
a. Three Integrated Circuits and 36 Peripheral Components

SAA1057

18

36V to 12V

b. Synthesizer Module SAA 1057 and 16 Peripheral Components
Figure 1. Basic Radio Tuning Synthesizers

December 1988

4-191

TEST

Signetics Linear Products

Application Note

AN196

Single-Chip Synthesizer for Radio Tuning

simply and economically accommodated are
analog signal control, extra display functions,
and remote control via an infrared data link.

OPERATING PRINCIPLES OF
FREQUENCY SYNTHESIS

Figure 2. Integrated Circuits for Tuning Systems Using SAA 1057

BIPOLAR CIRCUITS

A basic digitally-controlled PLL for radio tuning is shown in Figure 3. The output from the
voltage-controlled local oscillator in the radio
is converted into a pulse train, and frequency
divided by a programmable divider, before
being applied to one of the inputs of the
phase detector. The output from the crystalcontrolled reference oscillator is converted
Into a pulse train, and frequency divided by
one of two ratiOS, before being applied to the
other input of the phase detector. The phase
detector output, which is proportional to the
relative phase (and therefore the frequency)
of the two input signals, IS passed through the
low-pass loop filter to remove the high-frequency components and fed back to the VCO
as the tuning control voltage. The loop is
locked, and the radio correctly tuned, when
fose = NfREF where N is the programmable
division ratio determined by selecting the
frequency of the required broadcast.

Remote control

TDB2033

Galn·controlled remote IR receiver amplifier

Frequency synthesizer

SAA1057

Radio tuning PLL frequency synthesizer

Local Oscillator Inputs

Display drivers

SAA1060

32·segment LED

SAA1062/T

20 static outputs for LCD

SAA1063

32·segment FTD

Tuner switching

SAA1300

5-IIne switching circuit

As the word 'module' In the name of the
SAA1057 indicates, this new IC is part of a
modular, data bus-compatible, digitally-controlled tuning system In accordance with the
system's design philosophy followed for other
CirCUitS in our range of ICs for digital systems
in radios. The modular approach minimizes
radiation and reduces wiring and screening
costs because:
• all the sensitive signal processing
circuits for the tuning systems are now
in the SAA 1057 which can be mounted
in the ideal position close to the tuner
• internal HF dividers eliminate the need
for an external prescaler
• two sensitive, internally-switched VCO
inputs to the SAA 1057 allow direct
connection of the FM and AM local
oscillator signals Without additional
impedance matching, amplification or
switching
December 1988

BRIEF DESCRIPTION OF THE
FUNCTIONS OF THE SAA 1057
(Figure 4)

• the crystal-controlled reference OSCillator
for the PLL operates at the same
frequency for the AM and FM
waveband and causes little radiation
because It generates a low level
sinewave
• the separate microcomputer and
memory can be mounted close to the
keyboard and their capacity can be
tailored to meet the demands of
specific radios
• the frequency display dnver can be
mounted close to its display
As shown in Figure 2, the data bus compatibility of tuning systems uSing the SAA 1057
also allows the Simple addition of cirCUits as
required for waveband switching and for driv·
ing LED, LCD or fluorescent displays of
preset station number, waveband and channel number. Other facilities which can be

4-192

The local oscillator signals from the radio are
applied to Inputs FFM for FM and FAM for
AM. Since these Inputs have a sensitivity of
30mV to 500mV (AM) and 10mV to 500mV
(FM), the local oscillator Signals can be directly applied without preamplification or buffenng. A separate pin (DCA) allows the bias
cirCUitry of the internal Input amplifiers to be
decoupled by an external capacitor. The input
frequency range IS 512kHz to 32MHz for AM
and 70MHz to 120MHz for FM, the FM
signals being passed through an internal
dlvlde-by-ten HF prescaler which IS switched
off by software to minimize current consumption while tUning the AM band. Since the AM
and FM local oscillator signals are automatically selected by software, they need not be
externally SWitched during waveband selection.

Programmable Divider
ThiS 15-bit frequency divider, which is designed In a special manner to minimize current consumption, is programmed with a binary-coded diVisor (N) to synthesize the required frequency for the voltage-controlled
local oscillator in the radio. The local oscillator frequency (foscl is usually the IF above
the tuned frequency. The dividing number is
(32foscl/fREF for AM and (3.2foscl/fREF for

Signetics Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

diVided local OSCillator signal IS applied as
one of the inputs to a dual-phase detector
system

MOS CIRCUITS
Display drivers
PCE2100
PCE2110
PCE2111

40-segment LCD
60-segment LCD + 2 LEDs
64-segment LCD

PCE2112

32-segment LCD static

1 In duplex mode

SAA1061

16 static outputs for LED dnve and sWitching functions

SAB3044

2-diglt LED

Single-chip B-bit microcomputers
MAB8021

With 1k byte ROM and 28-pin package

MAB8048

With 1k byte ROM and 40-pln package

MAB84XX

NMOS family with 1 to 4k byte ROM and 12C bus

MAB85XX

CMOS family with 0.5 to 4k byte ROM and 12C bus

Memories
PCD8571

128 X 8-bit CMOS memory with senal I/O

PCB1400

100 X 16-blt EEPROM with senal I/O

Infrared remote-control receivers
SAB3023

Receiver and analog memory

SAB3033

Receiver and analog memory

SAB3042

Receiver and decoder with C-bus

SAB3028

Receiver and decoder with 12C bus

7 X 64 commands

SAB3021

2 X 64 commands

SAB3027

32 X 64 commands

~ ~~,';-

I

-- -- -I- -- -- -- -- -,

(Ov~~~~;lGlEF0

-~.
"

LOCAL

______ 1

Figure 3_ A Basic Digitally-Controlled PLL for Radio Tuning
FM, where fREF is the output frequency from
the reference frequency divider (40kHz or
December 1988

Reference Frequency Oscillator
ThiS stable, temperature-compensated OSCillator IS controlled by an inexpensive 4MHz
crystal (senes resistance < 150n) connected In senes With a capacitor between Pin 17
of the SAA 1057 and the common return line.
The reference frequency may alternatively be
denved from a stable external source. In thiS
case, a 4MHz squarewave of 5Vp_p may be
connected to Pin 17 via a senes-connected
10nF capacitor and 22kn resistors.

Reference Frequency Divider
ThiS circuit diVides the frequency of the signal
from the reference OSCillator by 125 or 100 to
obtain a reference frequency of 32kHz or
40kHz for the dual-phase detector system
under the control of software. If the selected
reference frequency IS 32kHz, the minimum
tuning step is 1kHz on AM and, due to the
dlvlde-by-ten HF diVider, 10kHz on FM. If the
selected reference frequency IS 40kHz, the
minimum tuning steps for AM and FM are
1.25kHz and 12.5kHz, respectively. If larger
tUning steps are reqUIred, Integer multiples of
these tuning steps can be selected by software.

Phase Detector System

Infrared remote-control transmitters
SAB3004

AN196

32kHz). The minimum divisor IS 512 and the
maximum divisor IS 32,767. The frequency-

4-193

To simplify the design of the PLL loop filter,
the SAA 1057 Incorporates a novel dualphase detector system that uses the same
reference frequency for AM and FM. One of
the phase detectors IS a high-speed digital
memory (flip-flop) type, the other IS a high
gain and analog memory (sample and hold)
type. The digital phase detector operates at
the reference frequency, generates about
100 times as much tUning current as the
analog phase detector and prOVides highspeed tUning over a Wide frequency range.
The analog phase detector operates at 1,132 of
the reference frequency, has no region of
uncertainty In ItS transfer charactenstlc and
prOVides Increased spectral punty of the local
OSCillator signal when the PLL IS locked. The
'hold' voltage from the analog phase detector
IS converted Into a DC current and summed
with the output pulses from the digital phase
detector to proVide a current proportional to
tuning error. This current dnves a gain-programmable amplifier to generate the tUning
voltage output.
The analog phase detector IS always operating, but the digital phase detector can be
switched on/off by setting/resetting the Inlock det~ctor With features/test bits In the
software (e.g., to minimize nOise during step
tuning). If the software does not Include any
features/test bitS, the digital phase detector
IS automatically SWitched on If the tuning error
exceeds the phase range of the analog phase

~

~

I
!

Signetics Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

9 Vee1

TR

AN196

TeA Tee

SAA1057

GAIN
PROGRAMMABLE
CURRENT
AMPLIFIER

LOOP
AMPL

"

5

Figure 4. Block Diagram of the SAA 1057

detector. This could occur, for example, as
the result of executing a large frequency
change. When the in-lock detector determines that the tuning error has been reduced
to within the operating range of the analog
phase detector for three consecutive sampling periods, the digital phase detector is
automatically switched off again.

Gain-Programmable Current
Amplifier
The sum of the output currents from the two
phase detectors drives a gain-programmable
bidirectional current source which replaces
the normally-used resistor between the
charge pump and loop amplifier of a PlL. This
allows the loop gain of the Pll to be software
programmed over a 40dB range within the
limits 0.023 to 2.3, thereby eliminating the
need to switch loop filter components during
waveband selecliOn.

Loop Amplifier
The loop amplifier is capable of providing a
tuning voltage output of up to 30V and only
reqUires a series-connected RC network between its input and output to form an active
low-pass loop filter. The supply voltage for
the loop amplifier (Vec3) need not be stabilized but it should be adequately filtered.
December 1988

Reception of Frequency and
Control Data
Data for the SAA 1057 consists of seriallytransmitted 17-bit frequency setting and control words from a microcomputer. Both types
of word incorporate a zero start bit which is
tested to identify a correct transmiSSion. Each
word also contains a latch selection bit which
IS 0 for a frequency setting word and 1 for a
control word. The Incoming data is transmitted via an asychronous data highway with
separate data (DATA), clock (ClB) and enable (DlEN) lines. The logic levels on the
lines are TTL-compatible and are independent of supply voltage.

A control word includes fifteen bits for the
following purposes:
• one bit (FM) to control the SWitch to
select the required input from the AM
or FM local oscillator. If the AM input is
selected, the divide-by-ten prescaler is
switched off to conserve power
• one bit (REFH) to program the divisor
for the reference frequency divider

Six1een bits of each incoming data word are
loaded Into a shift register. The bus, load and
control logic then checks that the transmission is valid by checking that the first bit IS
zero and that the word length is correct
dUring the HIGH period of the DlEN line. If
valid, the data word is then transferred to the
appropriate latch by the next pulse on the
clock line.

• four bits (CPO to CP3) to set the gain
of the gain-programmable current
amplifier
• one bit (SB2) to determine whether the
remaining eight features/test bits should
be used or not
• one feature bit (SlA) which determines
whether frequency setting data is
loaded into the programmable divider
immediately after reception
(asynchronous loading) or synchronized
With the sampling frequency
(synchronous loading). Synchronous
loading is for minimizing noise during
manual tuning without muting

A frequency-setting word includes fifteen bits
which define the required frequency expressed as a IS-bit binary-coded divisor (512
to 32767) for the programmable divider.

• two features bits (PDMO and PDM1)
which set the operating mode of the
digital phase detector as previously
deSCribed

4-194

ii,'
Signelics Linear Products

I

Application Note

I

Single-Chip Synthesizer for Radio Tuning

AN196
I

,--------------------------------- ---------------,
VCC3
30V~_4~--------------------

.le6

r

R1

SAA1057

I

i

AMOS

8

~
r
~C1

~t--'-f"'-'t-1

FTr~

FFM

,,) 1

I~"'

I

)

="
~
1l's

1----'- ; ".

13

c~~s 14 ClB
12 CBUS 12 DATA

r=J 4MH,
FM

Iell

Z'" 75n

1

t----~-.------------------------------

_----.-l

4Vto28V

Figure 5. An AM/FM Frequency Synthesizer Using the SAA 1057

• one feature bit (BRM) which sets the
bus receiver Into an automatic mode so
that It IS sWItched off to conserve
power after a data transmIssIon
• four test bIts (TO to T3) whIch can
route the reference sIgnal, the output
from the programmable dIvider or the
output level from the In·lock detector to
the TEST pIn for alignment purposes

mance, application fleXIbility and low power
consumption A deSCriptIon of the techniques
listed here IS beyond the scope of thIS artIcle
but further information can be found In the
references
• travelling-wave dIVIders In the dlvlde·byten prescaler ensure low current
consumption and hIgh senSitIVity for the
RF Inputs
• a tall·end diVider IS used to Increase
the speed of the digital phase detector

TECHNIQUES USED TO OBTAIN
THE HIGH PERFORMANCE OF
THE SAA1057
Many new CIrCUIt techniques have been used
in the SAA 1057 to achIeve the high perlor·

December 1988

• a rate-select technique In the
programmable diVider

minimiZeS

phase

Jump IrI the digital phase detector
• current consumption IS minimized by
uSing stacked logiC for the three

4-195

different types of digital CirCUitS (1 2l,
Eel and mlnlwatt) In thiS way, many of
the logiC CIrCUIts aci as current sources
for other logiC CirCUitS
• use of a bandgap current reference
ensures that the current consumption
remains constant over a Wide range of
supply voltage and operating
temperature
• the op amps at the RF Inputs have an
Input bias current of less than 10nA
and also have a very high slew rate
• the tunIOg VOltage IS derived from a
30V op amp with a low bias current
and a high slew rate

Signetics Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

AN196

BASIC APPLICATION OF THE
SAA1057

ACKNOWLEDGEMENT
The authors Wish to thank H. PrUlm of the IC
development department, Nllmegen, J. L.
Baurdoux of the car radiO development department, Eindhoven, and U. Schilihof of the
applicallOn laboratory, Hamburg, for their
contributions to thiS prolect.

Figure 5 IS the CirCUit diagram of a complete
frequency synthesizer uSing the SAA1057.
The functions and values for each component In the diagram are as follows
REF

FUNCTION

VALUE

R1

Defines the current In the analog phase detector

180f!

REFERENCES

R2

Loop filter resistor (value depends on Veo)

18kf!

1.

R3

Low-pass filter resistor (value depends on Veo)

R4
C,

Matching resistor for 75f! FM Input

180f!

Sample capaCitor (low leakage type)

2.2nF typ

UNDERHILL, M. J. 'Phase lock frequency
syntheSIS for communications', sympoSium on phase-locked loops and their
applications, January 18th 1980, Department of Electrical Engineering, University
of Technology, Delft.

C2

Hold capacitor (low leakage type)

10nF typ

2.

C3
C4

Decoupllng of Internal reference voltage
Loop filter capacitor (value depends on Veo)

330nF typ

Cs

Low-pass filter capaCitor, normally located In the tuner
(value depends on loop frequency)

100nF typ

C6

Power supply filtering

C7

DC blocking

Ca
Cg

Power supply filtering

UNDERHILL, JORDAN, CLARK and
SCOTT, 'A general purpose LSI frequency syntheSizer system' 32nd annual symposium on frequency control, 1978, Department of Electrical Engineering, University of Technology, Delft.
UNDERHILL, M. J. 'Universal frequency
syntheSizer IC system' lEE communications '78, 4th to 7th April 1978.
KASPERKOVITZ, W. D. 'Ultra high frequency divider', Philips Technical ReView, Vol 38, No.2, 1978179, pp. 50 to
65.
KASPERKOVITZ, W. D. and VERBEEK,
R. 'Low power CIrCUIt block for digital
telephone exchanges', Microelectronics
and Reliability, Vol. 15, 1976, pp. 163 to
170.

100f! min
10kf! typ

47flF

100nF
lOOflF

Decoupllng of RF Input stages

10nF

C1Q

DC blocking

llnF

C'l

Series capacitor for crystal
(value depends on crystal)

33pF

PERFORMANCE OF THE CIRCUIT FOR FM
TUning range

87.5 (88) to 108 MHz

TUning steps

10 kHz or 12.5 kHz

Intermediate frequency

10 7 MHz (variable In steps of 10kHz
or 12.5 kHz)

TUning voltage of the VCO

4 to 28 V

VCO gain

0.3 to 3 MHzIV

Ref. frequency

32 kHz

Prog. diVider ratios

9820 (9870) to 11870

Time to tune across band

< 400

Gain of current amplifier

0.3

Loop filter time constant

1 ms

ms

RMS ripple on tuning voltage nOise
(20 Hz to 20 kHz)
1 kHz

December 1988

3.

lnF

<1

flV (03 flV)

4-196

4.

5

Signefics

AN197
Analysis and Basic Application
of the SAA1057
Application Note

Linear Products

Author. J Matull

INTRODUCTION
Early digital tuning systems for AM/FM radio
receivers were constructed from ICs out of
standard logic families (ECL, TTL etc.)
Later, first dedicated ICs for PLL frequency
synthesizers have appeared on the market,
but there were stili several packages required
for the complete tUning system. The partitionIng of functions depends on the semiconductor technologies used. The tUning part of a
digital tuning system typically reqUires three
packages' a prescaler In ECL or Schottky TTL
(speed), a programmable divider and other
digital functions In either LOCMOS, NMOS or
j2L (packing density, current consumption)
and a loop amplifier with FET Inputs (low bias
current) and a bipolar output stage (current,
slew rate).
Now, more sophisticated ICs for digital tUning
of radio receivers are shOWing The SAA 1057,
being descnbed In thiS report, belongs to thiS
new generallon of radio PLL frequency syntheSizers It compnses all of the functions of a
digital PLL frequency synthesizer and all active components from the Inputs for the local
oscillators to the output for the yaractor
tUning voltage on one monolithic ChiP, reqUirIng only a minimum of external passive components.

SYSTEM DESCRIPTION
A functional block diagram of the SAA 1057 IS
shown In Figure 1. ThiS system IS designed to
handle both AM and FM local oscillator frequencies In a microcomputer-controlled radio
receiver. Attention has been paid to the
power consumption of the IC In order to
permit ItS use In portable as well as In mains
operated radios
An Important property of the SAA 1057 IS ItS
very low radiation. ThiS IS due to the compact
one-chip design which does not require an
external prescaler and ItS control line and due
to the crystal controlled reference oscillator
which operates with a low sine-wave voltage
sWing.

RF Inputs
Separate Inputs are provided for the AM and
FM local oscillators. Amplifiers at the Inputs
offer high sensitivity for easy interfacing to the

May 1981

radio's VCOs. No external buffers are reqUired. A bUilt-in dlvlde-by-l0 prescaler for
FM permits a maximum Input frequency of
120MHz while the AM Input can directly
handle up to 32M Hz.
An Input multiplexer permits both OSCillators
to be operating at the same time, thus saving
cost for sWitching the OSCillators In the radio
On AM, the prescaler IS sWitched off In order
to reduce the current drain of the chip
There IS one pin, DCA, for the decoupling
of the Input amplifiers' bias CirCUitry

Programmable Divider
ThiS 15 bit diVider IS programmed with a
binary coded diViding number, N, In order to
syntheSize a desired frequency fvco In view
of the current consumpllon, thiS diVider was
designed according to the rate select technique. ThiS Implies a minimum permiSSible
diViding number, N m1n , which IS equal to 512
In the SAA 1057. The maximum diViding
number, N max , IS given by the 15 bit length as
32767

Phase Detectors
A novel phase detector concept IS used in the
SAA 1057, permitting the use of the same
reference frequency on AM and FM, thereby
faCilitating the design of the loop filter.
Two phase and frequency sensitive detectors
are used In thiS concept, a high-speed digital
flip-flop type detector and a high-gain analog
sample and hold type detector. The digital
phase detector (PD) operates at the reference frequency and provides for high tuning
speed. The analog PD operates at 1/32 of
the reference frequency and proVides for
Improved spectral punty of the radio's VCO
after lock has been achieved There IS no
region of uncertainty In the analog PD's
transfer charactenstlc.

ThiS OSCillator IS designed to operate with a
low-cost 4MHz crystal Only one Pin IS reqUired for thiS stable, temperature-compensated OSCillator

The analog PD IS always operating. The
digital PD can be sWitched onloff either under
software control (see also 2.9) or automatically If no featuresltest bits are selected, the
digital PD IS automatically sWitched on If the
operating range of the analog PD IS exceeded, e.g. when a lump In frequency IS
executed. It IS automatically sWitched off
again If the operallng range of the analog PD
has not been exceeded during three consecutive sampling pen ods. That IS accomplished by the In-lock detector. ThiS detector
can be set and reset under software control
to establish the different modes of PD operation.

In case of an externally available 4MHz signal
of sufficient stability, the pin XTAL can be
supplied with a resistor from that source.

The "hold" voltage of the analog PD IS
converted to a DC current and summed with
the output pulses of the digital PD.

Reference Divider

Gain-Programmable Current
Amplifier

Two outputs of the programmable diVider are
fed to the phase detectors. They differ In
frequency by a factor of 32.

Reference Oscillator

ThiS diVider generates the reference frequency for the digital phase detector from the
4MHz crystal frequency. ThiS reference frequency IS either 32kHz or 40kHz. It can be
changed under software control and outputted at the pin TEST In case that IS desired,
e g for aligning the frequency of the reference OSCillator
With these two reference frequencies, the
minimum step size for changing the VCO's
frequency IS 1kHz and 125kHz on AM On
FM, the step size IS 10kHz and 125kHz due
to the dlvlde-by-l0 prescaler. Larger steps In
VCO frequency (Integer multiples of the values given above) can be achieved under
software control.

4-197

The output current of the phase detector
configuration IS passed through a gain-programmable amplifier. ThiS IS an eqUivalent for
the normally used senes resistor from the
charge pump to the loop amplifier. The advantage of thiS solution IS that the loop gain
can be programmed under software control
without any changes In hardware.

Loop Amplifier
The on-chip loop amplifier requires only a CR
senes connection between ItS Input and output pins to bUild a basIc loop filter. TUning
voltages of up to 30 volts can be generated.
The supply voltage for thiS amplifier, VCC3,
need not be stabilized; however, It should be
sufficiently filtered.

August 1988
Rev. 1

•
~

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

AN197

TR TCA Tea

1---1- XTAL
DCA

FAM
FFM

Yc",

OUT

IN

-4-----"----l

i-----t-TEST

OLEN CLCK DATA

Figure 1. Functional Block Diagram

Data Reception
The SAA 1057 reqUIres both frequency and
control Information from an external mIcro·
computer. ThIs informatton IS received vIa an
asynchronous senal data link with separate
data (DATA), shift clock (CLCK) and enable
(DLEN) lines. This structure with the assocIated tIming requirements used to be called
CBUS. The logIc levels on these CBUS lines
are TTL compatIble, mdependent of the supply voltage.

May 1981

IncomIng data IS receIved in a shift regIster. A
bus, load and control logic performs a format
check on received data and a decisIon on
whether the transmIssIon was valid or not.
Only correctly received data are transferred
to one of the two latches. Frequency Information IS stored in latch A and control information in latch B.

Features/Test
In additIon to the baSIC PLL operation of the
SAA 1057 there are a few features and test

4-198

functions whIch can be enabled by certain
bits In the control informatIon.
Examples are synchronous loading of frequency data to prevent an out-of-Iock condition due to that transmIssion, disabling of the
dIgItal phase detector to aVOId tuning noise in
case of step tuning, and outputtIng of the
reference frequency, e.g., for the alignment of
the crystal OSCIllator frequency. Details are
descnbed in the application sectIon of this
report.

Signetics linear Products

Application Note

Analysis and Basic Application of the SAA1057

AN197

Table 1. Description of Components
R1
R2
R3
R4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Y1

Defines current In S/H detector
Loop filter reSistor, depends on VCO
Low·pass filter resistor
Matching resistor for FM Input
Sample capaCitor, low leakage type
Hold capaCitor, low leakage type
Decoupllng of Internal reference voltage
Loop filter capaCitor, depends on VCO
LOW·pass filter capacitor, mostly located In tuner, depends on loop frequency
Power supply filter capacitor
DC blocking capacitor
Power supply filter capacitor
Decoupling of RF Input stages
DC blocking capacitor
Senes capacitor for crystal
Crystal for reference oscillator, f = 4.000MHz

ego
e.g.
min.
e.g.
typo
typo
typo
e.g.
e.g.
e.g.
typo
e.g.
typo
typo
e.g.

R1 =390
R2 = 18
R3 = 100
R4 = 180
C1 = 2.2
C2=10
C3 = 10
C4 = 330
C5 = 100
C6 = 100
C7 = 1
C8 = 100
C9 = 10
C10 = 22
C11 = 33

n
kn
n
n
nF
nF
nF
nF
nF
nF
nF
nF
nF
nF
pF

R1
18

TEST
Y1

Cl1

DH~

SAA 1057

GND
CLCK

VTUN

OLEN
DATA

VCC3

C10
AMOS

C9

VCC1J2

Figure 2. Basic Application

Power Supply
Vce>
TEST

VCC1I2

CLCK~~
DLEN~

DATA
GND

VTUN
GND

~~

FMOS
GND

Besides the already menllOned supply volt·
age for the loop amplifier there are two pinS
for the supply of the whole circuit: VCC1 and
VCC2. The supply voltage may be chosen In
the range from 3.6 to 12 volts without signifi·
cant influence on the supply current due to
the internal stabilizer, which IS decoupled at
pin DCS. The supply voltage should be well
filtered.

AMOS

APPLICATION
The cirCUit diagram for the baSIC application
of the SAA1057 In an AM/FM radio receiver
IS shown In Figure 2; a short descnpllOn of the
components IS given In Table 1.

SAA 1057 RADIO PLL SYNTHESIZER

Figure 3. Bottom View of PC Board

May 1981

4-199

•

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

As there are many ways In which radio
receivers can be different from each other,
e.g. number of wave bands, supply voltages,
tuning voltage range, VIF characteristic of
the VCO, the synthesizer circuitry has to be
designed for a specific application.

AN197

C4

>---~--o

In this chapter information is given on all of
the components in the cirCUit diagram and on
the software requrrements of the SAA 1OS7
for a number of receiver tuning procedures.
A typical lay-out of a printed circuit board for
the application of the SAA 1OS7 is given in
Figure 3. There are two connectors; one for
the supply voltages and the connection of the
radio receiver and one for the CBUS from the
microcomputer or a synthesizer controller,
like the SYCO II.

(1)
Let Zo = 7Sn, then
13S '7S
R4=---= 169n
13S-75
The closest standard resistor is R4 = 180
ohms.
The DC blocking capacitors, C7 and C10,
should be chosen so that their senes reactance at the lowest VCO frequency IS small
compared to the Input Impedance. Thus,
C7> > - - - - - 2 • '!r • fFM.m,n • R,FM

(2)

and
C10> > - - - - - 2 • '!r • fAM.m,n • R,AM

VOUT

Figure 4. Loop Filter Principle

t--,-- 90(0)

9~0)

InterfaCing of the Tuner's
Oscillators
The oscillator frequency lines are either realized on a PC board or as a screened cable,
depending on their length, among others. The
output at the AM VCO IS not cntlcal; it can be
an Inductive or capacitive tap at the resonant
cirCUit, provided the output voltage IS at least
30 millivolts rms Into a load of 2 kn. The
minimum required FM oscillator voltage is 10
millivolts rms, the Input resistance of the SAA
10S7 IS 13Sn. In order to minimize the
voltage standing wave ratiO, VSWR, a resistor, R4, is used to match the input resistance,
R,FM, to that of the connecting cable, Zoo
Ignoring the capacitances, R4 can be calculated according to

.2

Figure 5. PLL Block Diagram
fs = 1kHz or 1.2SkHz

Interfacing of the Tuning
Voltage

Designing the Loop Filter

The output of the loop amplifier is connected
to the vancap tuning diodes via a CR lowpass filter, R3 and CS.
Although there IS no lower limit of R3, a
minrmum of about 100n should be used to
avoid capacitive loading of the loop amplifier
output. For CS, there is normally a lower limit
given by the deSign of the varactor tuned
resonant circuits in the radio.
The cut-off frequency of the low-pass filter,
f 1p, should be less than the sampling frequency, fs, of the phase detector in order to
attenuate potential ripple at this frequency.
On the other hand, the cut-off frequency
should be high compared to the loop's natural frequency, fn' to keep the decrease of the
phase margin as small as pOSSible. fn depends on the FIV characteristic of the VCO,
the dividing number, N, and the loop filter
deSign.

Due to the on-chip loop amplifier and galnprogrammable current amplifier, the loop filter
consists of only two external components, R2
and C4. The loop filter prinCiple is shown in
Figure 4.
As outlined earlier, the commonly used series
resistor between charge pump and loop amplifier input IS replaced by a gain-programmable current amplifier in the SAA 1OS7. Therefore, the loop filter transfer function evaluates
to
VOUT (s) 1 + sT
KF = - - - = - liN (s)
sC4

(6)

with T = R2 • C4.
The baSIC block diagram of a PLL in terms of
gain is shown In Figure 5.
The output to input ratio reflects a second
order system:

Thus, the choice of the low-pass filter's cutoff frequency IS a compromise between ripple
rejecllon at the sampling frequency and loss
of phase margin.

(7)

e,(s)

(4)

(3)

or

with KIP

= gain of digital phase detector including current amplifier

1
1
->R3'CS>-wn
2'!r'fs

with
May 1981

Wn

= 2 ''!r'fn

(S)

KF

= gain of loop filter as given

Kv

in Equation (6)
= gain of VCO
= integer divisor

N

4-200

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

Table 2. Loop Filter Input Current VS. Gain Programming
CP3

CP2

CP1

CPO

Idlg

0
0
0
0
1

0
0
0
1
1

0
0
1
1
1

0
1
0
0
0

0.01mA
0.03mA
0.1mA
0.3mA
1.0mA

AN197

with Id,g = current programmed according to
Table 2
and
dfveo
Sveo=-dVtune

(13)

being the slope of the VCO's FIV characteristic.
Since neither Svco nor N remain constant
over a larger frequency band, Wn and 1
should be calculated for several POints in the
wave band considered, in order to find the
appropriate constants for best loop performance. See the Appendix for a design example.
The lock-up time not only depends on the
loop filter components but also on the current
gain setting. The longest time which can
occur IS that for a jump from one end of a
wave band to the other. It consists of two
parts:
tband ~ tslew

+ tsettle

(14)

The output pulses of the digital phase detector can be assumed to have an average duty
cycle of 50 0/0 dUring most of the slew time.
Therefore, tsl ew can be approximated as
C4' .:lVtune
tslew "" 2' -----'=
Id,g

(15)

The settling time, tsettle, depends on Wn and
can be estimated from
(16)
with wnt taken from Figure 6 for a certain
overshoot and Wn as given by Equation (12).

-

wn l

Figure 6. Type 2. Second Order Step Response
Substituting KF Yields

with wn
(8)

Oo(s)
O,(s)

1

K",'Kv
--C--· (1 + sT)

The gain of the phase detector, KIl, IS the
output current of the p.o. times the gain of
the programmable current amplifier. In order
to simplify the calculation, we re-write Equation (10) as follows:

S2 + s. K",' Kv - R2 + K",' Kv
N

= loop bandwidth or natural
frequency
= damping factor

C4'N

clearly showing the Characteristic Equation of
a second order polynomial:
(9)

W = '\IId'9 'Svco
n
C4'N

By comparison of coefficients one obtains

W ='\IK.p'Kv
n
C4'N

(10)

R2'C4
I=Wn '--2-

(11 )

May 1981

4-201

(12)

The output phase response of a type 2
second order system (Figure 5) to a phase
step Input is shown in Figure 6. The curves
can also be used for frequency inputs and
outputs. The required damping factor, I, for a
given overshoot can be taken from the plot.
Also, the natural frequency, w n, can be calculated If 1 and the lock-up time, tsettle, are
known.

The Analog Phase Detector
In the analog PD a comparison of the relative
phase of two digital signals IS performed. In
principle, a voltage ramp is started by the
crystal controlled reference frequency and
stopped by the high-speed output of the
programmable divider. As only every 32nd
output pulse is sampled, the phase jitter of
that rate-multiplier type divider is eliminated.
The ramp voltage IS transferred to the hold
capacitor, C2. Any deviation from the ramp's
center voltage is converted to a current,
amplified In the gain-programmable current
amplifier, and fed into the loop amplifier.

•

Signetics Linear Products

Application Note

AN197

Analysis and Basic Application of the SAA1057

The voltage ramp IS generated by first chargIng the capacitor, Cl, with Internal circuitry
and then discharging it with a constant current, which IS defined by an external resistor,
R1. Thus, the slope of the ramp, I.e. the gain
of the analog PO, can be changed by changIng the component values of Cl and R 1.
There are two limitations. For Rl, there eXists
a minimum value of 100 ohms In order to limit
the discharge current to a safe value and for
C2, there IS a maximum value given for both
reference frequencies to permit complete
pre-charging of that capacitor.

1500

1200
1000
820
680
560

ri

The maximum ramp amplitude depends on
the supply voltage, VCC2, and IS typically

470

a: 390

(17)

330

The time reqUIred for a discharge of Cl from
VTCA.max to VTCA.mm depends on the value of
Cl and the discharge current, which IS defined by Rl. The maximum time IS

270
220

Cl 'Vramp

180

tramp

= --I-dl-S-

(18)

150

With
120
100

RIMIN

(19)

-

0

Vcc, (VOLTS)

and the maximum permitted time, tdlS' we can
calculate the maximum value of resistor R 1 to
be

Figure 7. Maximum R1 as a Function of VCC2

Rl max

•

,~.~n

4.0 Hz

22K
8AA 1057

The center voltage is typically
VCC2
Vr,o = -2- + 0.3V

PEAK-TO-PEAK

(20)

(21)

giving an operating range of the analog PO of
VSH

-=TC01470S

Figure 8. Connection of an External 4MHz Source

Table 3. Loop Filter Input Current Per Volt Change of the
Hold Capacitor Voltage
CP3

CP2

CP1

CPO

lanalog PER VOLT

0
0
0
0
1

0
0
0
1
1

0
0
1
1
1

0
1
0
0
0

0.03=JlA
0.1 =1lA
0.3=JlA
1.0=JlA
3.5=JlA

May 1981

Cl • (VCC2 - 2)

VTR IS the voltage at pin 1 of the SAA 1057
during the discharging of capacitor, Cl. The
dependency of the upper limit of Rl on VCC2
IS shown In Figure 7 for two different values of
Cl.

17

10nF

tdls,vm

= -...::.:'-...:.:..:-

4-202

= Vr.o-+

Vramp
2

(22)

As the maximum output current of the analog
PO depends on VCC2, only a "gain" constant
of 1.51lA1V IS specified, I.e. a deviation of 1
volt from the center voltage, Vr.O' produces an
output current of 1.5JlA. ThiS current is amplified In the gain-programmable amplifier and
then fed into the loop amplifier. In Table 3
there are given some loop filter Input current
values for different gain settings of the galnprogrammable amplifier.
To obtain the maximum currents obtainable
from the analog PO, the values in Table 3
have to be multiplied by 1/2' Vramp '

Signetics Linear Products

Application Note

Analysis and Basic Application of the SM1057

DLEN

AN197

U

CLCK

DATA

TEST FOR START BIT
Figure 9. CBUS Timing

DATA

Figure 10. Data Word for Frequency

DATA

Figure 11. Data Word for Control Information

Generating the Reference
Frequency
The simplest way of completing the reference
frequency oscillator IS to connect a 4MHz
quartz crystal from Pin 17 (XTALl to ground.
Any crystal with a series resistance of not
more than 150n will do. As crystal frequen·
cies are normally specified for a certain
extemal capacHance, a series capacitor, Cll,
should be connected in series with the crys·
tal, Yl. If the crystal spec IS properly chosen,
a fixed capacitor will normally do. If we
assume a mis·alignment of 50ppm the result·
ing veo frequency of e.g. 100MHz would be
offset by 5kHz, I.e., half the step size. That IS
normally unimportant. In special appilcations,
however, it might be necessary to tune the
crystal. There is room for a series trimmer
capacHor on the PC board.

May 1981

Table 4. Frequency Programming Range
INPUT
AM
FM

=

fREF
32

=1kHz

fREF
32

=1.25kHz

f max =

512kHz
32767kHz

640kHz
40958.75kHz

f mm =
f max =

5.12MHz
327.67MHz

6.40MHz
40S.5875MHz

f m,n

Another way of generating the reference
frequency is the use of an external 4MHz
source of satisfactory stability. In Figure 8 It is
shown how to connect such an external
source.

There are two checks performed on data
receIVed In the SAA 1057:
- a test for the start bit
- a test for correct word length.

Please note that the stray capacitance at pin
17 should not exceed 8pF.

The start bit is tested dUring the high time of
the first clock pulse. It has to be '0' to Indicate
the beginning of a proper transmission.

Transmitting Data to the
SAA1057
All Information is entered serially into the SAA
1057. The timing of the CBUS data transmission is shown In Figure S.

4-203

Signetics linear Products

Application Note

Analysis and Basic Application of the SAA1057

(FM = '0') or one tenth of the frequency at
the FM Input (FM = '1') is sWitched to the
Input of the programmable diVider. In AM
mode (FM = '0') a part of the FM signal path
IS sWitched off In order to reduce the current
drain of the chip

Table 5. Phase Detector Mode
PDM1

PDMO

0
0
1
1

0
1
0
1

DIGITAL PO
Automatic onloff
Automatic onloff
On
Off

Table 6. TEST Signals
T3

T2

Tl

TO

0
0
0
0

0
1
0
1

0
0
0
0

0
0
1
1

OUTPUT AT TEST (PIN 18)
Reference frequency
Output of prog divider
Output of In-lock detector
low = out-of-Iock
high = In-lock

Table 7. Control Information

x

TRANSMISSION

SB2

SLA

PDM1

PDMO

Control 1
Control 2
Control 3

1
1
1

0
1
1

0
0
1

X
X
1

= don't

care

The word length IS defined as the number of
clock pulses dUring the time Interval
DLEN = '1', I e., the number of data bits plus
1 (start bit). The word length for the SAA 1057
IS 17.
Correctly received data are transferred to
their latch by another pulse on the CLCK hne,
the so-called load pulse Clock pulses need
not be symmetric; however, minimum high
and low times should be observed.
Due to internal data shifting there IS a time
after the reception of the load pulse dUring
which the SAA 1057 does not react to information on the CBUS hnes. This time IS called
busy time. Under worst case conditions this
busy time IS as long as 1.3 mllhseconds, I.e. a
following data transmission to the SAA 1057
must not start before 1.3 milliseconds have
passed since the tralhng edge of the load
pulse. If the following transmission IS, however, Intended for a different deVice, e.g. a
display driver, It may start as early as 5fJs
after the load pulse for the SAA1057.
Frequency Information
The organlzatoon of the data word for the
setting of frequency IS shown in Figure 10.
Frequency IS expressed as a diViding number,
N, for the programmable diVider according to
the following formulae
(23)
(24)

with fosc being the VCO frequency (normally the sum of tuning frequency and IF) and
fREF being the reference frequency
at the digital PD of either
32kHz or 40kHz.
The diViding number has then to be converted to binary notation in a 15-blt format as
shown In Figure 10 and a '0' added for the
register select bit, thereby defining latch A as
the destination of the data word.
Due to the apphed diVider principle, the minimum diViding number IS Nmln = 512. In case a
smaller value IS transmitted, N = 512 will be
programmed The maximum dividing number
of Nmax = 32767 results from the 15-blt
length. The total programming range of the
SAA 1057 IS given In Table 4.
Concerning the usablhty of the given programming range the frequency hmlts of the
SAA1057 (AM. 0.512 to 32M Hz, FM: 60 to
120M Hz) as well as any relevant hcenslng
regulations (e.g., FCC, GPO etc.) have to be
observed.
Control Information
The organization of the data word for the
transmission of control Information IS shown
In Figure 11.
By setting the control bits either low or high
the mode of operation of the SAA 1057 IS
programmed The register select bit IS always
'1' to define latch B as the destination of
control Information.
Control bit FM - With the control bit FM
either the frequency at the AM Input

May 1981

4-204

AN197

Control bit REFH - With the control bit
REFH the reference diVider can be programmed for two different diViding numbers,
Nro = 125 and Nrl = 100. In connection with
the 4MHz reference OSCillator this results In
the reference frequencies frO = 32kHz and
frl = 40kHz and the sampling frequencies
fso = 1kHz (REFH = '0') and fSl = 1.25kHz
(REFH = '1 '), respectively.
Control bits CP3 to CPO - With the control
bits CP3 through CPO the gain of the galnprogrammable current amplifier IS Influenced.
In addition to a minimum gain there are 4
steps available which may be combined at
will. In Table 2 there are given some programming examples and the resulting loop filter
Input currents under control of the digital PD.
With a given loop filter the PLL gain can be
changed under software control in a range of
1 to 100 with intermediate values resulting
from programming of bit combinations. The
current from the analog PD depends on the
amount of phase error and the supply voltage, VCC2, as outhned In section 3 4. See also
Table 3 for some current values.
Control bit SB2 - With the control bit SB2 It
can be chosen whether the featuresltest bits
(Io\"(er half of control word) shall be used
(SB2 = '1') or not (SB2 = '0') In case of
SB2 = '0' the lower 8 bits of the control word
are Interpreted as all "zeros" independent of
the actual transmitted bit pattern. Please
note, that the length of the control word must
not be shortened In view of the format reqUirements of the SAA 1057. In case of
SB2 = '1' the actual value of the lower 8 bits
IS used
Control bit SLA - With thiS control bit it can
be chosen whether transmitted frequency
Information IS loaded Into the programmable
diVider Immediately after reception
(SLA = '0') or synchronized to the sampling
frequency (SLA = '1').
Asynchronous loading is mandatory for frequency changes of more than 31 tuning
steps, e.g., when recalling a pre-programmed
station from memory Synchronous loading
(SLA = '1 ') IS recommended for manual tunIng without muting In order to minimize tUning
nOise.
Control bits PDM1, PDMO - With these
control bits the operating mode of the phase
detectors IS selected according to Table 5.
The meaning of automatic onloff IS that In
case of a phase error exceeding the operatIng range of the analog PD the digital PD IS

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

SEND CONTROL 1

OUTPUT SILT
DELAY 1

OUTPUT SILT
DELAY 1

SEND CONTROL 1

SEND CONTROL 2

SEND FREQUENCY

SEND FREQUENCY
DELAY 2

AN197

•
SEND FREQUENCV

NO

CELAY3
SEND CONTROL 3
OUTPUT SILT

SILT

Figure 12. Data Sequences for the Synthesizer

May 1981

4-205

= ~Lent !unlng (Switching Signal)

Application Note

Signetics Linear Products

AN197

Analysis and Basic Application of the SAA1057

Please note, that between consecutive transmisSions to the SAA 1057 there has to be a
minimum time delay of 1.3 milliseconds
(SLA = '1 '). ThiS need not necessarily be a
restriction, as processing of data In the microcomputer, e.g. BCD to binary conversion or
operating a display driver, also takes time.

Power Supply Requirements
As shown In Figure 2, two different supply
voltages are reqUired for the SAA10S7.
VCC1/2 IS between 3.6 and 12 volts and VCC3
between VCC2 and 31 volts, depending on the
varactor diodes used In the tuner If the full
programming range of the gain-programma·
ble current amplifier IS to be used, VCC'/2
should, however, not be less than S volts.

Figure 13. Power Supply Filtering
automatically sWitched on. It IS sWitched off
again as descnbed In secllOn 2 5, I e. If the
analog PO's operating range has not been
exceeded dunng three consecutive sampling
penods. For the In·lock condition It IS recom·
mended to sWitch the digital PO permanently
off In order to Improve the digital PO perma·
nently off In order to Improve the VCO's
spectral punty. O1herwlse, Induced disturbances could cause a temporary out-of-Iock
condlllOn and, thus, an audible nOise.
Control bit BRM - With this control bit the
bus receiver mode IS selected, I e whether
the bus receiver IS permanently sWitched on
(BRM = '0') or automatically sWitched off after each data transmission (BRM = '1 ') In
order to reduce the current drain
Control bits T3 to TO - These bits are test
bits. T3 and Tl must always be programmed
low With T2 and TO a few Internal signals can
be put out at Pin 18 (TEST) as shown In
Table 6.

Software Considerations
After power has been applied to the SAA
1OS7, an Initialization must be performed
before any meaningful data transmission
takes place ThiS Initialization can either conSiSt of a train of at least 10 clock pulses on
the CLCK line and afterwards a transmission
of control Information (word B) or by transmltling that control InformallOn twice, as It contains a suffiCient number of clock pulses.
A number of radiO tUning operations IS executed With the audiO part being mute In order
to suppress any tUning nOise ThiS applies to
recalling of stored stallOns, executing numencal frequency Inputs, changing of wave bands
and to automatic search tUning. Dunng manual tUning undlstorted listening should be posSible. From the above there result a few
different sequences of data transmissions
from a MC to the SAA1057, as shown In
Figure 12.

May 1981

It IS assumed that at power-up the receiver IS
Silent Therefore, no SILT signal need be
output to operate sWitching or squelch
circuitry
In Table 7 a proposal IS made for a few
control bits which are not dictated by tuner
charactenstlcs or test signals
FM and REFH depend on the current wave·
band and the deSired VCO step size. CP3 to
CPO depend on the tuner charactenstlcs and
tUning time specification, their programming
need not be the same for each control word
The word "control 3" sets the synthesizer to
synchronous loading of frequency data, I e
no extra control Information IS reqUired In
case of manual tUning, and sWitches the
digital phase detector off for best spectral
punty of the tuner's VCO
The different delays shown In Figure 12 serve
for the follOWing purposes 'Delay l' IS Intend·
ed to permit the audiO squelch CirCUitry to
reach a certain mullng depth before tUning
changes The time IS typically In the range
between 0 and 50 milliseconds. 'Delay 2' IS to
adjust search tUning sweep speed to a speci'
fled value The time depends largely on the
frequency step size and on receiver time
constants In case of the minimum step Size
there might be no delay allowed at all. Time IS
tYPically between 0 and SO milliseconds DurIng 'delay 3' the actual tUning process takes
place In order to permit any frequency to be
tuned to, thiS time IS normally between 200
and 500 milliseconds
The path for manual tUning In Figure 12
depends on the type of actuator, e g. tUning
knob or pius/minus buttons In case of a
tUning knob the tuning speed depends on the
user's action In case of plus/ minus buttons
and one step per operation It IS nearly the
same But In case of an auto-repeat function
some time delay IS reqUired to adjust the
speed, as shown for the path of automatic
search tUning.

4·206

Power supply ripple cannot be neglected
because of the limited ripple rejection of the
SAA10S7. For the calculation of permissible
power supply ripple let us assume the follow·
Ing
- we use an FM tuner
- the maximum slope IS Svco = 3MHzIV
- the deSired slgnal-to-nolse rallO IS
SNR = 7SdB
- SNR IS based on a deViation of
Ll.f = ± 40kHz
- SNR depends on supply npple only
From the data sheet It can be seen that the
reJecllOn of VCC2 and VCC3 ripple is dominatIng. If we assume both voltages to be of equal
Influence each of them has to give an SNR
which IS 3dB better than specified. The per·
mlsslble supply ripple voltage (peak-to·peak)
can be calculated from
(rvcc, - SNR - 3dB)
2 - Ll.f
V VCC = - - -10-'--'-'-"-------'"
'Svco
20
(2S)

With 1=2 or 3, Indicating VCC2, VCC3
rvCQ = ripple rejection of Vcc, In dB
For the data assumed above we Will get
V,VCC2 = 0.6mV peak·to-peak
V,:VCC3 = 6mV peak-ta-peak
In other words, If the power supply ripple in
the baSIC appllcallon of Figure 2 is not greater
than Indicated above, an overall slgnal·tonOise ratio of 7SdB can be achieved With a
VCO slope of 3MHzIV and no other nOise
sources being present.
If, however, the actual power supply ripple is
larger than the limit calculated for a deSired
SNR, additional filtenng has to be used. The
deSign of a filter circuit depends on the
permitted voltage drop. If a drop of several
volts IS acceptable, a CirCUit as given In Figure
13a can be used. If the drop should be less
than 1V, Figure 13b could be used.

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

Let us assume that a stabilized supply voltage
of 8V with a maximum ripple of SmV peak-topeak is available. We choose the filter circuit
of Figure 13a to generate the supply voltage
VCC1/2. The attenuation is given by
a = 20 "logY1 + (wRC)2

(26)

The required attenuation is 20" log (SI
0.6) = 18.SdB. In order not to operate the
SAA10S7 below SV, the drop across R should
be less than 3V. Thus,
3V
Rmax - - - = 167n
18mA

For the basic application to AM/FM radios
there is Information given on hardware, software, power supply and a deSign example for
the calculation of the loop filter.

BIBLIOGRAPHY
1.

and obtain an attenuation of
a-21dB @ f,=120Hz

2.

Now let us calculate component values for
Figure 13b as a filter for VCC3. Let us assume
a supply voltage of 30V with a ripple of 1 Vp.p
and a maximum tuning voltage of 27V. The
allowed voltage drop should be less than lV.
The required filter attenuation is 20 log
(1/0.006) = 44.4dB. Again the attenuation is
given by Equation (26). The voltage drop is
le"R

s

(27)

with
Ie - load current = ICC3

3.
4.

S.
6.

Phase-Locked Loop Systems Data Book;
Motorola Inc., 1973.
P. Atkinson et.ai.: "DeSign of Type 2
Digital Phase-Locked Loops," The Radio
and Electronic Engmeer; November
1975.

R. Best: Theone und Anwendungen des
Phase-Locked Loops; AT-Verlag, 1976.
A.B. Przedpelskl: "Analyze, don't estimate, phase-locked-loop," Electronic
Design, May 10, 1978.
H. Geschwinde: Emfiihrung in die PLLTechnik; Vleweg, 1978.
M.J. Underhill: "Phase Lock Frequency
Synthesis for Communications," Symposium on Phase Lock Loops and Applications, Delft University of Technology,
January 1980.

B = DC gain of transistor
We select
R = 10kn
C=22j.lF
and obtain
a = 44.4dB @ fr - 120Hz
AV = 0.7V @VBe-0.6V
B = 100
le= lmA
In case of higher attenuation, i.e. a larger time
constant R "C, a speed-up path for a quick
charging of C at power-on should be provided. Otherwise, Vcca could reach its nominal
value too late and tuning to the desired
frequency can be delayed.

SUMMARY
This report has described a new microcomputer-controlled AM/FM radio PLL frequency
synthesizer IC, the SAA1OS7, and its baSIC
application.
There are several unique design ideas realized in the IC. The most important is the
combination of a digital and an analog phase

May 1981

The tuning time from one end of the band to
the other is assumed to be not longer than
0.4 seconds. If we split this time into equal
parts for the slew and settle times, we can
calculate capacitor C4 by rewriting equation
(lS) as
C4 "" Islew" Idlg
2" AVtune

(15a)

For the first trial a medium value is taken for
the loop filter current, e.g.
Idlg = O.lmA (CP = 0010)
We then get from Equation (lSa)

We select
R = 1son
C = 100j.lF

AV=VBe+

detector, giVing improvements In tuning
speed as well as In spectral purity of the veo.
The use of the same reference frequency for
both AM and FM tUning Simplifies the design
of the loop filter. The PLL gain can be
programmed in a range of 1 to 100 under
software control, thereby eliminating the need
for switching of external loop filter components.

AN197

APPENDIX

Design Example
Based on the Circuit Diagram of Figure 2 a
PLL frequency synthesizer for an FM radio
shall be designed. The following tuner data
are given:
tuning range
fRF = 88 to 108MHz
tUning steps
AfRF = 10kHz
flF = 10.70MHz
intermediate frequency
Vtune = 4 to 28V
tuning voltage
VCOgain
Svco = 3.0 to 0.3MHzlV
Svco is assumed to decrease linearly from
the low end of the tuning range to the high
end.
From the tuning step size It is obVIOUS to use
REFH = 0, i.e., 32kHz reference frequency.
Using Equation (24) we can calculate the min
and max values of the dividing number, N, for
the programmable divider:
Nmln - 9870
Nmax = 11870

C4 ""O.4j.lF
We choose the closest standard capacitor
value of
C4 = 0.33j.lF
and calculate an approximate slew time of
Islew "" 0.16 seconds
Now we have to determine the lower limit of
the loop's natural frequency and see if the
actual frequency is larger. From Figure 6 we
read Wnt = 7 for a maximum overshoot of 1
010 at an optimum damping factor of 0.7. We
re-write Equation (16) as
Wn"t

Wn=--

(16a)

tsettle

and calculate
Wn,mln ~ 35s- 1
with Isettle = 0.2 seconds being our initial
assumption. Using Equation (12) we calculate
the loop's natural frequency for the low and
high ends of the tuning range.

wn low = 304 s-1
Wn:hl9h = 88 S-1
As both values are well above the minimum,
the settling time will not be larger than assumed and we will not have to change the
assumptions made so far.
Now, we have to solve for resistor, R2.
Looking at Equation (11) we quickly realize
that the damping factor, ~, will change with
Wn, thereby influenCing the overshoot. Let us
try to solve thiS dilemma by calculating R2 for
the mid of the tuning range. We take
N = 10870
Svco = 1. 7MHzIV
Idlg = O.lmA
~= 0.7
C4 = 0.33j.lF
and get
Wn = 218 s-1
R2= 19S00n

4-207

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

We choose a standard resistor value of
R2 ~ 18krl
and check the damping factor With the aid of
Equation (11) at the ends of the tUning range
end get
t,ow ~ 0.87
thigh ~ 0.25
The low
end the
resulting
shoot of
time of

end value IS stili good. At the high
response IS highly under-damped,
In wnt ~ 18 for a maximum over1 010. That would mean a settling
tsettle

~

0.2 seconds

which IS equal to our assumption. In reality,
the digital phase detector will be switched off
earlier due to the action of the analog PD.
Thus, tUning from one end of the band to the
other IS achieved In less than 0.4 seconds. If
the calculated damping factor thigh IS regarded too small, a new calculation can be started

May 1981

with a higher current gain, e.g. Idlg ~ 0.3mA
(CP ~ 0110). This would result In thigh ~ 0.45
and t,ow = 1.56 which IS now too large.
For normal applications it seems to be satisfactory to use only one value for the galnprogrammable amplifier. USing more than one
value Within one wave-band requires additional software in the MC because the tUning
frequency has to be checked against some
cross-over frequency.
For the low-pass filter, R3 and C5, we get
from Equation (5) by uSing Wn ~ Wn.low
4.6ms

> R3 - C5 > 0.32ms

We choose the fliter time constant to be
millisecond, resulting In component values of
e.g.
R3 ~ 10krl
C5 ~ 0.1MF

4-208

AN197

As the filter capacitor might be designed in
view of RF reasons, a modification may be
necessary which, however, should Include R3
to maintain the time-constant of the low-pass
filter.

ADDENDUM
The currently available samples of the
SAA 1057 are stamped as N 1653. These
samples require an extra current of approximately 10J1A at room temperature Into Pin 4.
This extra current can most easily be realized
by connecting a resistor between Pins 4 and
16. In this case, the supply voltage VCCl/2
shall not be changed, once a resistor value
has been fixed. For a nominal supply voltage
of VCCl/2 ~ 5V, a resistor value of 270krl is
an adequate solution at room temperature. At
ambient temperatures above approximately
40 to 45'C It may be necessary to increase
the resistor value.

T001742

Signetics

CMOS Frequency Synthesizer
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDD1742 is a CMOS low-current
frequency synthesizer IC designed for
VHF/UHF portable or mobile transceivers. This IC combines in a single chip
many features of the HEF4751 (divider
circuit), and HEF4750 (synthesizer), including a high-gain phase comparator,
using a sample-and-hold technique. A
multiplexed or bus-structured programming sequence has been adopted to
allow interfacing to an external ROM or
a microcontroller. Operation down to a
7V supply rail is possible with a maximum input frequency of 8.5MHz.

• Single-chip with on-board
sample-and-hold capacitor
• Low power requirements
• High-performance phase
comparator with low phase noise
and spurious response
• Auxiliary digital phase
comparator for fast locking
• On-board phase modulator
• Simple interface to memory
• Microprocessor controllable
• Power-on reset circuitry

Figure 1 shows the functional block
diagram of the TDD1742 with the principal features of a reference oscillator,
programmable reference and main dividers, the two phase comparators, phase
modulator, and the programming input
interfaces.

• Cellular radio
• Digital frequency synthesizers
• Communications equipment
(HF-UHF)
• Portable transceivers

D Package

APPLICATIONS

TOP VIEW
PIN NO. SYMBOL
VOD3

PCl

ORDERING INFORMATION

PC2

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP (SOT-136A)

Test 2
ClK

TDD1742TD

vss

RF IN
VOO2

ABSOLUTE MAXIMUM RATINGS
SYMBOL
Voo1.
VOO2.
VDD3

PARAMETER
Supply voltage
Voltage on any input

RATING

UNIT

-0.5 to +15

V

-0.5 to VOOl +0.5

V

0.5

V

Vooz- V oo1

Relative supply voltage

VOO3-VOO1

Relative supply voltage

0.5

V

Direct current Into any Input

±10

mA

Direct current Into any output

±10

mA

Po

Power diSSipation
TA = 0 to +85°C

500

mW

TSTG

Storage temperature

-65 to + 150

°C

TA

Operating ambient temperature

-40 to +85

°C

July 15, 1988

4-209

10
11
12
13

,.

15
16
17
18
19
20
21
22
23
2'
25
26
27
28

FB
Ol
RES
XTAl
OSC
VOD1

DB3
DB2
DBl
DBO
ABO
ABl
AB2
PE2
PEl
MOD
MEMEN
TRB
TRC
TRA

DESCRIPTION
Main power supply, + 7 to + 10V
High-gain phase comparator
(analog)
Low-gain phase comparator
(dIgItal)
Test pm
Clock output
Ground
RF Input
Power supply tor TIL-compatible
stages, + 5V ± 10 %
Feedback to prescaler
Out-af-Iock Indication
Power-on reset
Reference OSCillator/buffer output
Reference OSCIllator/buffer Input
MaIn power supply; + 7 to + 10V
Data bus Inputs
Data bus Inputs
Data bus Inputs
Data bus mputs
Address bus
Address bus
Address bus
Program enable 2
Program enable 1
Phase modulatIon Input
Memory enable
Bias resistor Rs
Bias resistor Rc
BIas reSistor RA

853-113693870

Signetics Linear Products

Product Specification

1001742

CMOS Frequency Synthesizer

BLOCK DIAGRAM
TRS

11100

r---------------+O mA
I-----------to PC.

IN

1-----+0 TAe
Fa

_-+-----------\

pe2~_+~------------~PC2

PROGRAM DATA
DECODER AND
PROM COHmOL

CIRCUITRY

1-......---+-0 TEST PIN

AESo--4----------~:::::::J------~

eLKON.-=~~J_---------------------'

osc

v..

XTAL

eooaeo1s

July 15, 1988

4-210

Signetics linear Products

Product Specification

TDD1742

CMOS Frequency Synthesizer

PIN DESCRIPTIONS AND FUNCTIONS
SYMBOL

DESCRIPTION

Inputs

DBO to DB3

TTL-compatible data bus inputs.

PE1, PE2

TIL-compatible program enable Inputs which Imllate the programming cycle or strobe the Internal data
latches.

IN

Input to the main programmable divider, usually from a prescaler (85MHz max.).

OSC

Input to reference OSCillator which, together with the XTAL output and an external crystal, IS used to
generate the reference frequency Alternatively, the OSC Input may be used as a buffer amplifier for an
external reference OSCillator.

RES

Power-on reset; follOWing power-up, an Initial pulse is applied to this pin to set the Internal counters.

MOD

High-Impedance linear phase modulator Input, which applies a voltage-controlled delay to the output of
the programmable divider before being applied to the phase comparator input.

Outputs

PC1

High gain phase comparator output IS used when the system IS In lock to give low levels of nOise and
spurious outputs. This comparator uses a sample-and-hold technique Similar to that used In the
HEF4750, but In the TDD1742 the sample-and-hold capacitor IS on-chip

PC2

Low gain digital phase comparator which enables fast lock times to be achieved when the system
imtlally IS out-of-Iock. This comparator IS Inhibited when the phase IS within the locking range of PC1,
i.e., 3-state output.

OL

Out-of-Iock flag which IS HIGH when the digital phase comparator PC2 is In operation, i.e., when the
system is out-of-Iock.

FB

Feedback output to control the modulus of the external prescaler

XTAL

Output to form crystal oscillator CIrCUIt In combination With the OSC input.

Bidirectional pins

ABO-AB2

TTL-compatible bidirectional address bus. Provides address output to an external memory or receives
output from a microcomputer. The outputs are all 3-State with Internal pulldowns.

MEMEN

Mode control and memory enable pin At general reset, the mode of operation can be set to
microcomputer mode, MEMEN LOW, or memory mode, MEMEN HIGH. For further information, see
PROGRAMMING section.

TRA

Current mirror pin for control of the gain 01 PC1.

TRB

Current mirror pin for control of the phase modulator gain.

TRC

Current mirror pin for analog biasing.

T2

Test pin should be left unconnected.

July 15, 1988

4-211

•

I

Signetics Linear Products

Product Specification

1001742

CMOS Frequency Synthesizer

DC ELECTRICAL CHARACTERISTICS

at VOO, = 7AV, V002 = 5.0V, V0 03 = 7AV; TA = 25°C; voltages are referenced to Vss,
unless otherwise noted.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

Supply

Supply voltage
Pin 14
Pin 8
Pin 1

10
5
10

V
V
V

Quiescent device current 2, 3

1.5
100
1.5

mA
IlA
mA

± liN

Input current logic inputs, MOD 2. 3

300

nA

± Iz
± Iz

Output leakage current at Y2 V00 2. 3
PC2, high-Impedance OFF-state
MEMENB, high-Impedance state

50
1.6

nA
p.A

Iz

I/O current, high-Impedance state ABO to AB2

30

p.A

1

0.3V 00 1

V

1

0.8

V

VOOl
V002
V003
1001
1002
1003

VIL
VIL

VIH
VIH

VOL
VOH

July 15, 1988

7
4.5
7

5

Logic input voltage
LOW
CMOS inputs
CMOS I/O
TTL inputs
TTL 1I0's
HIGH
CMOS Inputs
CMOS 1/0
TTL inputs
TTL I/O's
1

1

Logic output voltage2
1101< 11lA
LOW
HIGH 2

0.7VOOl

V

2

V

50
Vool -50

4-212

mV
mV

Signetlcs Linear Products

Product Specification

1001742

CMOS Frequency Synthesizer

DC ELECTRICAL CHARACTERISTICS (Continued) at VOOl = 7.4V, VOD:! = S.OV, VOOa = 7.4V; TA = 2S"C; voltages are
referenced to Vss , unless otherwise noted.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

logic output voltage
lOW2
Output~

VOL
VOL
VOL
VOL
VOL
VOL

IOL=4mA
Output PC2
10L= I.SmA
Outputs ClK, Ol
10L = lmA
Output XTAl at:
10L =3mA
Output FB
10L= lmA
Outputs ABO, AB1, AB2
10L =0.2mA

1

V

O.S

V

O.S

V

O.S

V

O.S

V

0.4

V

VOH

logic output voltage
HIGH 2• 3
Output PC2
10H =-I.SmA
Outputs ClK, Ol
10H=-lmA
Output XT Al at:
IOH=-3mA
Output FB
10H=-lmA
Outputs ABO, ABI at:
IOH=0.2mA
Output AB2 at:
IOH=0.8mA

2.4

V

10

Output PCl sink current 2, 3, 4

1

mA

-10

Output PCl source current 2. 3, 5

1

mA

RIN

Internal resistance of PC1, locked state
I output sWIng I ..;; 200mV, specified output range: 2, 3
o 5VOO - O.SV to O.SVoo + O.SV

VOH
VOH
VOH
VOH
VOH

July IS, 1988

4-213

VOO1- 0.5

V

Voo l -O.S

V

Voo1-1

V

VOO2- 1

V

2.4

V

2.0

n

Slgnetlcs Linear Products

Product Specification

1001742

CMOS Frequency Synthesizer

AC ELECTRICAL CHARACTERISTICS

The dynamic speCification is given for the circuit, built up with the external
components as given in FIgure 4, unless otherwise specified.
LIMITS

SYMBOL

DESCRIPTION

TEST CONDITIONS

UNIT
Min

f,N

Programmable divider input frequency, all division ratios

Square wave input

6.5

fOlv

Reference divider input frequency, all diviSIon ratios

Square wave input

9

fosc

Crystal oscillator frequency

C'N

Inpu1 capacity IN,

C'N

Input capacity DBO to DB3, PEl, PE2, ABO to AB2

tpOHl
tpOlH

FB feedback outpu1 to externalS prescaler delays IN ..... FB

100

Average power supply current 3. 7

9

MHz

Cl = 10pF

MHz

12

35
35

3

pF

5

pF

70
70

ns
ns

Locked state

1001

2

mA

1002

0.15

mA

1003

0.45

mA

2. All logic Inputs
3. RA connected,
Rs connected.
Rc connected.

at
its
lis
lis

CMOS logiC Inputs
CMOS logIC outputs
CMOS logIC 110
TTL logIC Inputs
TTL logIC output
TTL logIC 110
Analog Inpuls
Analog output
Analog bIaSIng p,ns

. OSC, RES
. Ol, PC2, XTAL, ClK
MEMENB
DBO to DB3. PEl. PE2
FB
ABO to AB2
MOD, IN
PCl
TRA. TRB. TRC

Vss or Voo
value chosen such that ITRA - 20JJA,
value chosen such that ITRS = 20JJA,
value chosen such that ITRC = 2OJJA,

EQUlVAI.ENT CIRCUIT:

INPUT FORCED LOW
BY 2 PRECEDING R PULSES

Internal Voltage-Follower VF2
5.

MHz

asc

NOTES:
1. Defintltons:
RA = External btaSlng reSIstor between pins TRA and Vss
Rs - External bIasIng resIstor between p,ns TRB and Vss
Rc = External btaslng reSIstor between p'ns TRC and Vss
CA - Decoupltng capaCitor between pins TRA and Voo
Cs = Decoupltng capacitor between pIns TRB and Voo
Co - Decoupltng capacItor between p,ns TRC and Voo

4.

Typ Max

=-

EmlYALENT CIRCUIT"

INPUT FORCED HIGH
BY 2 PRECEDING V PULSES

Intarnal Voltage VF2

6.

~=~-+-t-1~:

--+b:-

_I

Waveforms IN ..... FB

7. lose - 5MHz, external clock. diVISIon ratio 420
l,N = 2MHz, diVISIon rabo 168

July 15, 1966

4-214

Signetics Linear Products

Product Specification

T001742

CMOS Frequency Synthesizer

REFERENCE OSCILLATOR AND
DIVIDER CHAIN
The reference oscillator chain comprises a
crystal oscillator and diViders to give the
required reference frequency drive to the
phase comparators.
A single inverter is used as an oscillator stage
and oscillates satisfactorily With crystals up to
9MHz. Alternatively, an external reference
source may be applied to the Input of thiS
Inverter (OSC Pin) at logic level drive or at a
lower level (300mV min) if a biasing resistor IS
connected from OSC to XTAL. The reference
divider chain comprises a fixed 74 stage
followed by three cascaded programmable
dividers with ratios of 712/13/14/15, 75/6/
7/9 and 71/2/4/8. The output of thiS last
stage is applied as one Input to the two phase
comparators. Hence, a number of diVISion
ratios are possible between 240 and 4320,
enabling all the usual VHF and UHF channel
spacings to be accommodated with reference
crystals in the range 1 - 9MHz.

MAIN PROGRAMMABLE
DIVIDER
The main programmable divider is a rate
feedback binary diVider. Referring to the
Block Diagram, the programmable diVider
uses a fixed 7-bit binary divider (7128) and
two rate selectors (n1 and no). One rate
selector controls a 7-bit fully programmable
dual modulus diVider (7n2/n2 + 1) and the
other rate selector controls an external dual
modulus prescaler (7A/A + 1).
The overall diVision ratio (N) is given by:
N

= (128

n2 + n1)A + no

where 0 < no < 127
0< n1 < 127
1  > 2WL

(2S)

Equations 23 and 24 show that the capture
range increases as the low-pass filter lime
constant is decreased, whereas the lock
range is unaffected by the filter and is determined solely by the loop gain.
Figure 7 shows the typical frequency-to-voltage transfer characteristics of the PLL. The
input is assumed to be a sine wave whose
frequency is swept slowly over a broad frequency range. The vertical scale IS the corresponding loop error voltage. In Figure 7a, the
input frequency is being gradually increased.
The loop does not respond to the Signal until
it reaches a frequency W1, corresponding to
the lower edge of the capture range. Then,
the loop suddenly locks on the input and
causes a negative jump of the loop error
voltage. Next, Vd varies with frequency with a
slope equal to the reciprocal of VCO conversion gain (1/Ko) and goes through zero as
WI = wo'. The loop tracks the input until the
input frequency reaches w2, corresponding to
the upper edge of the lock range. The PLL
then loses lock and the error voltage drops to
zero. If the input frequency is swept slowly
back, the cycle repeats itself, but IS Inverted,
as shown in Figure 7b. The loop recaptures
the signal at Wa and tracks it down to W4. The
total capture and lock ranges of the system
are:
2wc= w3- w 1

In terms of the basic gain expression in the
system, the lock range of the PLL wL can be
shown to be numerically equal to the DC loop
gain (2-sided lock range).
2WL = 41TfL = KvF(O)

lock range. For the simple first-order lag filter
of Figure Sb, the capture range can be
approximated as

(27)

and
(28)
Note that, as indicated by the transfer characteristics of Figure 7, the PLL system has an
Inherent selectivity about the free-running
frequency, wo'. It will respond only to the
Input signal frequencies that are separated
from wo' by less than we or wL, depending
on whether the loop starts with or without an
initial lock condition. The linearity of the
frequency-to-voltage conversion characteristics for the PLL is determined solely by the
VCO conversion gain. Therefore, in most PLL
applications, the VCO is reqUired to have a
highly linear voltage-to-frequency transfer
characteristic.

II

Signetics Linear Products

Application Note

Modeling the Pll

AN178

0----0
F(o)

0----0

-0 - - - - -......-lir--

••

-I~

ROOrLOCUS

FREOUENCY RESPONSE

a. Zero-Order Filter

,
F(~"=R'C
R,

+jw

I

"

I

..

-.
"

\

\

~.

\

ROOT LOCUS

FREQUENCY RESPONSE

-1<0>

b. First-Order Simple Lag Filter
R,

·Iw

~

F('~

"

ROOrLOCUS

FREQUENCY RESPONSE

c. First-Order Lag-Lead Filter
Figure 6. Root Locus and Frequency Response Plots

December 1988

4-232

Signetics Linear Products

Application Note

AN17S

Modeling the PLL

DETERMINING LOOP
RESPONSE
The transient response of a PLL can be
calculated using the model of Figure 4 and
Equations 18 and 19 as starting points. Combining these equations gives
lIo(s)
KvF(s)
H(s)=- = - - 1I;(s)
s + KvF(s)

~

v.

:

(29)

INCREASING
FREQUENCY

".om;.';,
SWEEP

I ..

The phase error which keeps the system in
lock is
1I.(s) = 8,(s) -lIo(s)

I

..

a. Input Frequency Increasing

(30)

Define a phase error transfer function
CAPTURe RANGE

E(s)

= 8.(s) = 1 _ 80 (s)
11,(s)

=1-

8,(s)

Vd

(31)

H(s)

+

J4-

~

2wc

-+l

I

INCREASING
FREQUENCY

o O'RECi-T-'O"'N....
OF"T-·-----?t"---'------ - SWEEP

As an example of the utilization of these
equations, consider the most common case
of a loop employing a simple first-order lag
filter where
1
F(s)=-1 + STl

b. Decreasing Input Frequency

(32)

Figure 7. Typical PLL Frequency-to-Voltage Transfer Characteristics

For this filter, Equations 29 and 31 become
(33)

"'PUT
VOLTAGE

f

'I(t)

(34)

Both equations are second-order and have
the same denominator which can be expressed as
D(s) = S2 + S/Tl + KVITl
= S2 + 2~Wns + wn 2

(35)

Where Wn and ~ are, respectively, the system's undamped natural frequency and
damping factor defined as
(36)

1

Wn

2v'1 1.0, and critically damped ~ = 1.0. Now
examine this PLL system's response to vanous types of inputs.

December 1988

Figure 8. Input Signal Representing a Unit Step of Phase at Constant
Frequency

H(s)

110 (s)

=-

=

Wn 2

S
S(S2 + 2~Wns + Wn 2)
E(s)
s + 2~wn

l1e(s) = - =
S
S2 + 2~wnS + Wn 2

(39)

When

(40)

(depending upon the working units) while
maintaining the same input frequency. Mathematically this input has the form

~

= I, these phase responses are
(44)

and
(45)

4-233

Signetics Linear Products

Application Note

Modeling the Pll

AN178

Figure 9 is a plot of the veo phase response
and the phase error transient for various
damping factors. Note from this figure that an
underdamped system has overshoot which
can cause the loop to break lock If this
overshoot IS too large. The critical condition
for maintaining lock is to keep the phase error
within the dynamic range for the phase comparator of -1112 to 112 radians. For the underdamped case, the peak phase-error overshoot IS

e.(max) = e -\111> ~

for \*1.
The time expression for the veo frequency
change for a unit step-of-frequency Input is
the same as the time response veo phase
change due to a step-of-phase Input (Equation 41), or
walt) for frequency step Input = eo(t) for
phase step Input Thus
wo(t) = 1 +

e-\Wnt
v'
2 sin (wnt ~ + '1')

1-\

tion, it IS Important that the veo voltage-tofrequency charactenstic be linear so that the
output IS not distorted. Over the linear range
of the veo, the conversion gain is given by
Ko (In radian IV-sec)
Ll.wo
Ko=-Ll.Vd

(56)

Since the loop output voltage IS the veo
voltage, we can get the loop output voltage
as

(52)

(46)

(57)

which must be less than 1112 to maintain lock.
Lock can also be broken for the overdamped
and cntically-damped loops If the Input phase
shift is too large where the phase error
exceeds ± 1112 radians.
The analysis and equations given are based
upon the smail-signal model of Figure 4. If the
signal amplitudes become too large, one or
more functional blocks In the system can
saturate, causing a slew rate type limiting
action that may break lock.
The transient change In the veo frequency
due to the unrt step-of-phase Input can be
found by taking the time derivative of Equation 41 or alternatively by finding the Inverse
Laplace transform of

Unit Ramp-ot-Frequency Input
ThiS form of input signal represents sweeping
the Input frequency at a constant rate and
direction as shown In Figure 11. The amplitude and phase of the input remain constant;
the Input frequency changes linearly with
time Since the input signal to the PLL model
IS a phase, a unit ramp-of-frequency appears
as a phase acceleration type Input that can
be mathematically described as
1
e,(s)=~

(53)

The veo output phase change is

The gain Ko can be found from the data
sheet. When the veo voltage IS changed, the
frequency change IS virtually instantaneous.

Phase Comparator
All of Signetics' analog phase-locked loops
use the same form of phase comparatoroften called the doubly-balanced multiplier or
mixer. Such a circuit IS shown In Figure 12.
The Input stage formed by transistors 01 and
02 may be viewed as a differential amplifier
which has an equivalent collector resistance
Rc and whose differential gain at balance IS
the ratio of Rc to the dynamic emitter resIstance, re , of 01 and 02.
Rc
0.026

RCIE
0.052

which is

(48)

The time expression for the veo phase
change IS

where IE is the total DC bias current for the
differential amplifier pair.

t2 2\t
2\ [
eo(t) = - - - + - 2 2\(1 - Wn 2) +
2
wn
wn
( 1 _ 4\2Wn 2 + 4\2Wn 't2

The switching stage formed by 03 - 06 IS
switched on and off by the veo square wave.
Since the collector current swing of 02 is the
negative of the collector current swing of 01,
the switching action has the effect of multiplying the differential stage output first by + 1
and then by -1. That is, when the base of 04
is positive, RC2 receives 11 and when the base
of 06 IS positive, RC2 receives i2 = i1 . Since
the circuit is called a multiplier, performing the
multiplication will gain further inSight into the
action of the phase comparator.

4)

1 _\2

Unit Step-ot-Frequency Input
This type of input occurs when the Input
frequency is instantaneously changed from
one frequency to another as IS done In FSK
and modem applications. For this Input, as
shown in Figure 10,

1

e,(S)=~

(49)

The veo output phase is

X

e-~wnt

Sln(wnt

v'1=-f2 + '1")]
(55)

where '1' = arc tan

~

W _ 2wn 2) +

'1'

and '1' is given In Equation 42.

PLL BUILDING BLOCKS
VCO

The transient time expression for the veo
phase change IS

sin (Wnt~ + 2'1')
December 1988

(51)

(58)

Since three different forms of veo have been
used In the Signetics PLL senes, the veo
details will not be discussed until the indlvldualloops are described. However, a few general comments about veos are In order.
When the PLL is locked to a Signal, the veo
voltage IS a function of the frequency of the
input signal. Since the veo control voltage is
the demodulated output during FM demodula-

4-234

Consider an input signal which consists of
two added components: a component at
frequency w, which is close to the freerunning frequency and a component at frequency wk which may be at any frequency.
The Input signal IS
v,(t) + Vk(t)

= V,sin(w,t + e,) +
(59)

Signetics Linear Products

Application Note

Modeling the PLL

80(1)

AN178

t

1

1.8
1.6

II

1.4

rl

1.2

0.8

1
lw-'=0.10

Y

0.6
0.4

,=0.7: \
,='1

1

1

1

..,;

8.(t)

0.4

~j-=G.25

'L . / "\'

0.8

t

0.6

~=0.50

1.0

0.2

"'\

frequency difference frequency component.
This IS the beat frequency component that
feeds around the loop and causes lock-up by
modulating the VCO. As Wo is driven closer
to wI> this difference component becomes
lower and lower in frequency until Wa = Wi
and lock IS achieved. The first term then
becomes

!-

"'"

0.2
0

-0.2

2AdVi
ve(t) = VE = --cos II,
1f

-0.4

(62)

-0.6

-0.8
1
-u
01234567891.L-

oV

"n(l)

Figure 9. VCO Phase and Loop Phase Error Transient Responses for Various
Damping Factors

which is the usual phase comparator formula
shOWing the DC component of the phase
comparator during lock. ThiS component
must equal the voltage necessary to keep the
VCO at wo0 It is possible for Wa to equal w,
momentarily dUring the lock·up process and,
yet, for the phase to be incorrect so that Wa
passes through Wi Without lock being
achieved. ThiS explains why lock IS usually
not achieved Instantaneously, even when
WI = Wa at t = O.

*

If n 0 in the first term, the loop can lock
when Wi = (2n + 1)Wa, giving the DC phase
comparator component
2AdV,
Ve(t) = VE =---cosll,
1f(2n + 1)

I

;-V\NW{ ---.
Figure 11. Input Signal for a Unit Ramp-of-Frequency Input
where 8, and Ilk are the phase in relation to
the VCO signal. The unity square wave devel·
oped in the multiplier by the VCO signal is

V
__'-cos [(2n + 1) Wat-wit-llil
n=O (2n+1)
00

~

[

4
- - - sin [(2n + l)Watl
n=O 1f(2n+ 1)
~

(60)

where Wa IS the VCO frequency. Multiplying
the two terms. using the appropriate trigono·
metric relationships. and inserting the differ·
ential stage gain Ad gives:

00

-

V,

~ - - - cos [(2n + 1) wat + wit + lI,l
n=O (2n+1)

00
Vk
+ ~ ---cos [(2n + 1) wot-wkt-1I1<1
n=O (2n+1)

-

00
Vk_ cos [(2n + 1) wat + W\(t + 81<1 ]
~ __
n=O (2n+1)

(61)

Assuming that temporarily Vk is zero. if w, is
close to wo, the first term (n = 0) has a low
December 1988

4-235

(63)

shOWing that the loop can lock to odd harmonics of the free-running frequency. The
(2n + 1) term in the denominator shows that
the phase comparator's output IS lower for
harmonic lock, which explains why the lock
range decreases as higher and higher odd
harmonics are used to achieve lock.

Figure 10. Input Signal for a Unit Step-of-Frequency at Constant Phase

INPUT

I

i

Note also that the phase comparator's output
dUring lock IS (assuming ~ is constant) also
a function of the input amplitude Vi. Thus, for
a given DC phase comparator output VE, an
input amplitude decrease must be accompanied by a phase change. Since the loop can
remain locked only for 8, between 0 and 180·,
the lower V, becomes, the more the lock
range is reduced.
Note from the second term that during lock
the lowest possible frequency is
Wa + w, = 2wl· A sum frequency component
is always present at the phase comparator
output. This component is usually greatly
attenuated by the low-pass filter capacitor
connected to the phase comparator output.
However, when rapid tracking is required (as
with high-speed FM detection or FSK), the
requirement for a relatively high frequency
cutoff in the low-pass filter may leave this
component unattenuated to the extent that it
interferes with detection. At the very least,
additional filtering may be required to remove
this component. Components caused by
n 0 in the second term are both attenuated
and of much higher frequency, so they may
be neglected.

*

I
I

.-

Signetics Linear Products

Application Note

Modeling the Pll

AN178

amplitude detector. The output of the quadrature-phase detector is given by

+Vcc

(64)

t - - - - ov•

where V, is the constant or modulated AM
signal and 0,""90· in most cases so that sine
0,= 1 and

veo

INPUT.

(65)

This IS the demodulation principle of the
autodyne receiver and the baSIS for the 567
tone decoder operation.

INITIAL PLL SETUP CHOICES

Figure 12. Integrated Phase Comparator Circuit

Suppose that other frequencies represented
by Vk are present. What is their effect for
Vk*O?
The third term shows that Vk introduces
another difference frequency component. Ob·
viously. if wk is close to w,. it can interfere
with the locking process since it may form a
beat frequency of the same magnitude as the
desired locking beat frequency. However.
suppose lock has been achieved so that
we = WI· In order for lock to be maintained.
the average phase comparator output must
be constant. If wa = Wk IS relatively low in
frequency. the phase 0, must change to
compensate for this beat frequency. Broadly
speaking. any Signal in addition to the signal
to which the loop is locked causes a phase
variation. Usually thiS IS negligible since wk is
often far removed from w,. However. It has
been stated that the phase 0, can move only
between 0 and 180·. Suppose the phase limit
has been reached and Vk appears. Since it
cannot be compensated for. it will drive the
loop out of lock. This explains why extraneous signals can result in a decrease in the
lock range. If Vk is assumed to be an instantaneous noise component. the same effect
occurs. When the full sWing of the loop is
being utilized. noise will decrease the lock or
tracking range. This effect can be reduced by
decreasing the cutoff frequency of the lowpass filter so that the we - "'" is attenuated
to a greater extent. which illustrates that
noise immunity and out-band frequency rejection is improved (at the expense of capture
range since Wo - w, is likewise attenuated)
when the low-pass filter capacitor is large.

December 1988

The third term can have a DC component
when Wk is an odd harmonic of the locked
frequency so that (2n + 1) (we - WI) is zero
and Ok makes its appearance. ThiS will have
an effect on 01 which will change the 01
versus frequency w1' This is most noticeable
when the waveform of the incoming signal is.
for example. a square wave. The Ok term will
combine With the 0, term so that the phase is
a linear function of input frequency. Other
waveforms will give different phase versus
frequency functions. When the input amplitude V, is large and the loop gain is large. the
phase Will be close to 90· throughout the
range of veo sWing. so this effect IS often
unnoticed.
The fourth term is of little consequence
except that if "'" approaches zero. the phase
comparator output will have a component at
the locked frequency we at the output. For
example. a DC offset at the input differential
stage Will appear as a square wave of fundamental we at the phase comparator output.
This is usually small and well attenuated by
the low-pass filter. Since many out-band signals or noise components may be present.
many Vk terms may be combining to influence
locking and phase during lock. Fortunately.
only those close to the locked frequency
need be considered.

Quadrature-Phase Detector
(QPD)
The quadrature-phase detector action is exactly the same except that its output is
proportional to the sine of the phase angle.
When the phase 0, is 90·. the quadraturephase detector output IS then at its maximum.
which explains why it makes a useful lock or

4-236

In a given application. maximum PLL effectiveness can be achieved if the designer
understands the tradeoffs which can be
made. Generally speaking. the deSigner is
free to select the frequency. lock range.
capture range. and input amplitude.

FREE-RUNNING FREQUENCY
SELECTION
Setting the center or free-running frequency
is accomplished by selecting one or two
external components. The center frequency
is usually set in the center of the expected
input frequency range. Since the loop's ability
to capture is a function of the difference
between the incoming and free-running frequencies. the band edges of the capture
range are a/ways an equal distance (In Hz)
from the center frequency. TYPically. the lock
range is also centered about the free-running
frequency. Occasionally. the center frequency is chosen to be offset from the incoming
frequency so that the tracking range is limited
on one side. ThiS permits rejection of an
adjacent higher or lower frequency signal
without paying the penalty for narrow-band
operation (reduced tracking speed).
All of Signetics' loops use a phase comparator in which the Input Signal is multiplied by a
unity square wave at the veo frequency. The
odd harmonics present in the square wave
permit the loop to lock to Input Signals at
these odd harmonics. Thus. the center frequency may be set to. say. Y3 or Y5 of the
input signal. The tracking range. however. will
be considerably reduced as the higher harmonics are utilized.
The foregoing phase comparator diSCUSSion
would suggest that the PLL cannot lock to
subharmonics because the phase comparator cannot produce a DC component IT w, is
less than woo

Signetlcs Linear Products

Application Note

Modeling the PLL

The loop can lock to both odd harmonic and
sub harmonic signals In practice because
such signals often contain harmonic components at Wo For example, a square wave of
fundamental wo/3 will have a substantial
component at Wo to which the loop can lock.
Even a pure sine wave Input signal can be
used for harmonic locking If the PLL Input
stage IS overdrlven. (The resultant internal
limiting generates harmonic frequencies.)
Locking to even harmonics or sub harmonics
IS the least satisfactory, Since the Input or
VCO signal must contain second harmOniC
distortion. If locking to even harmonics IS
deSired, the duty cycle of the Input and VCO
Signals must be shifted away from the symmetrical to generate substanllal, even harmOniC, content.
In evaluating the loop for a potenllal application, It is best to actually compute the magnitude of the expected Signal component nearest wo. ThiS magnitude can be used to
estimate the capture and lock ranges
All of Signetlcs' loops are stabilized against
center frequency drift due to power supply
variations. Both the 565 and the 567 are
temperature-compensated over the entire
military temperature range (- 55 to + 125°C)
To benefit from thiS Inherent stability, however, the deSigner must proVide equally stable
(or better) external components. For maxImum cost effectiveness In some noncritical
applications, the deSigner may Wish to trade
some stability for lower cost external components.

GUIDELINES FOR LOCK RANGE
CONTROL
Two things limit the lock range. First, any
VCO can sWing only so far; It the input Signal
frequency goes beyond this limit, lock Will be
lost. Second, the voltage developed by the
phase comparator IS proportional to the product of both the phase and the amplitude of
the in-band component to which the loop IS
locked. If the signal amplitude decreases, the
phase difference between the signal and the
VCO must increase In order to maintain the
same output voltage and, hence, the same
frequency deViation. The 564 contains an
internal limiter CirCUit between the signal Input
and one input to the phase comparator. ThiS
cirCUit limits the amplitude of large input
Signals such as those from TTL outputs to
approximately 100mV before they are applied
to the phase comparator. The limiter Significantly Improves the AM rejection of the PLL
for input Signal amplitudes greater than
100mV.
This happens so often with low input amplitudes that even the full ± 90° phase range of
the phase comparator cannot generate
December 1988

AN178

enough voltage to allow tracking Wide deViations When thiS occurs, the effective lock
range IS reduced Weak Input Signals cause a
reduction of tracking capability and greater
phase errors Conversely, a strong Input signal Will allow the use of the entire VCO sWing
capability and keeps the VCO phase (referred
to the Input Signal) very close to 90· throughout the range Note that the lock range does
not depend on the low-pass filter. However, If
a low-pass filter is In the loop, It Will have the
effect of limiting the maXimum rate at which
tracking can occur. ObViously, the LPF capacitor voltage cannot change Instantly, so
lock may be lost when large enough step
changes occur Between the constant frequency Input and the step-change frequency
Input IS some limiting frequency slew rate at
which lock IS just barely maintained When
tracking at thiS rate, the phase difference IS at
ItS limit of O· or 180· It can be seen that If the
LPF cutoff frequency IS low, the loop Will be
unable to track as fast as If the LPF cutoff
frequency IS higher. Thus, when maximum
tracking rate IS needed, the LPF should have
a high cutoff frequency. However, a high
cutoff frequency LPF Will attenuate the sum
frequencies to a lesser extent so that the
output contains a Significant and often bothersome Signal at tWice the Input frequency.
The phase comparator's output contains both
sum and difference frequencies DUring lock,
the difference frequency IS zero, but the sum
frequency of tWice the locked frequency IS
stili present. ThiS sum frequency component
can then be filtered out With an external lowpass filter.

INPUT LEVEL AMPLITUDE
SELECTION
Whenever amplitude limiting of the In-band
Signal occurs, whether In the loop Input stages or prior to the Input, the lock and capture
ranges become Independent of Signal amplitude.
Better noise and out-band signal immUnity IS
achieved when the Input levels are below the
limiting threshold, since the input stage is In
ItS linear region and the creation of crossmodulation components IS reduced. Higher
Input levels will allow somewhat faster operation due to greater phase comparator gain
and will result In a lock range which becomes
constant with amplitude as the phase comparator gain becomes constant. Also, high
input levels will result in a linear phase versus
frequency characteristic.

CAPTURE RANGE CONTROL
There are two main reasons for making the
low-pass filter time constant large. First, a
large time constant prOVides an Increased

4-237

memory effect In the loop so that it remains at
or near the operating frequency dUring momentary fading or loss of signal. Second, the
large time constant Integrates the phase
comparator's output so that Increased immunity to nOise and out-band signals is obtained.
BeSides the lower tracking rates attendant to
large loop filters, other penalties must be paid
for the benefits gained The capture range IS
reduced and the capture transient becomes
longer. Reduction of capture range occurs
because the loop must utilize the magnitude
of the difference frequency component at the
phase comparator to drive the VCO towards
the Input frequency
If the LPF cutoff frequency IS low, the difference component amplitude IS reduced and
the loop cannot sWing as far. Thus, the
capture range IS reduced.

LOCK-UP TIME AND TRACKING
SPEED CONTROL
In tracking applicallOns, lock-up time IS normally of little consequence, but occasions do
arise when It IS deSirable to keep lock-up time
short to minimize data loss when nOise or
extraneous Signals drive the loop out of lock.
Lock-up time IS of great Importance In tone
decoder type applications. Tracking speed is
Important If the loop IS used to demodulate an
FM signal. Although the following diSCUSSion
dwells largely on lock-up time, the same
comments apply to tracking speeds
No Simple expression IS available which adequately deSCribes the acqulslllOn or lock-up
time. ThiS may be appreCiated when we
review the following factors which influence
lock-up time.
a. Input phase
b. Low-pass filter characteristic
c. Loop damping
d. Deviation of input frequency from center
frequency
e. In-band Input amplitude
f. Out-band signals and noise
g. Center frequency
Fortunately, it IS usually sufficient to know
how to improve the lock-up time and what
must be sacrificed to get faster lock-up.
Consider an operational loop or tone decoder
where occasionally the lock-up transient is
too long. What can be done to Improve the
situation - keeping in mind the factors that
Influence lock?
a. Initial phase relationship between Incoming signal and VCO - This IS the greatest
Single factor Influencing the lock time. If
the initial phase IS wrong, it first drives the

•

Application Note

Signetics Linear Products

AN178

Modeling the PLL

I

100%

V

80%

I

60%

40%

f. Out-band signals and noise - Low levels
of extraneous Signals and nOise have little
effect on the lock-up time, neither improving or degrading It. However, large levels
may overdrive the loop input stage so that
limiting occurs, at which pOint the in-band
signal starts to be suppressed. The lower
effective Input level can cause the lock-up
time to Increase, as discussed In e above.

r-

NOTE
THE ABSCISSA WILL, IN GENERAL,
BE DIFFERENT FOR EACH lOOP

/

g. Center frequency - Since lock-up time
can be deSCribed in terms of the number of
cycles to lock, fastest lock-up is achieved
at higher frequencies. Thus, whenever a
system can be operated at a higher frequency, lock will typically take place faster.
Also, in systems where different frequencies are being detected, the higher frequencies, on the average, Will be detected
before the lower frequencies.

OPERATING CONDITION

;/

20%

0%
10

15

20

25

35

30

However, because of the Wide varlallan due
to initial phase, the reverse may be true for
any single trial.

INPUT CYCLES

Figure 13. Probability of Lock vs Input Cycles
VCO frequency away from the Input frequency so that the veo frequency must
walk back on the beat notes. Figure 13
gives a typical distribution of lock-up times
with the input pulse Initiated at random
phase. The only way to overcome this
variation is to send phase information all
the time so that a favorable phase relationship IS guaranteed at t = O. For example, a
number of PLLs or tone decoders may be
weakly locked to low amplitude harmOniCs
of a pulse train and the transmitted tone
phase related to the same pulse train.
Usually, however, the incoming phase cannot be controlled.
b. Low-pass filter - The larger the low-pass
filter time constant, the longer will be the
lock-up time. The lock-up time can be
reduced by decreasing the filter time constant, but In dOing so, some of the nOise
immUnity and out-band signal rejection will
be sacrificed. This IS unfortunate, Since
this IS what necessitated the use of a large
filter In the first place. Also present will be
a sum frequency (twice the VCO frequency) component at the low pass filter and
greater phase jitter resulting from out-band
signals and nOise. In the case of the tone
decoder (where control of the capture
range is required Since it specifies the
deVice bandWidth) a lower value of lowpass capacitor automallcally Increases the
bandwidth. Speed IS gained only at the
expense of added bandWidth.
c. Loop damping - A simple first-order lowpass filter of the form
1
F(s)=-1 + ST
December 1988

PLL MEASUREMENT
TECHNIQUES

produces a loop damping of
(67)

Damping can be Increased not only by
redUCing n, as discussed above, but also
by redUCing the loop gain Kv. USing the
loop gain reducllan to control bandWidth or
capture and lock ranges achieves better
damping for narrow bandWidth operation.
The penalty for thiS damping IS that more
phase comparator output IS required for a
given deViation so that phase errors are
greater and nOise immUnity IS reduced.
Also, more input drive may be reqUired for
a given devlallan.
d. Input frequency deViation from free-running frequency - Naturally, the further an
applied Input Signal IS from the free-running frequency of the loop, the longer it Will
take the loop to reach that frequency due
to the charging time of the low-pass filter
capacitor. Usually, however, the effect of
thiS frequency deviation IS small compared
to the variation resuiling from the Inillal
phase uncertainty. Where loop damping is
very low, however, it may be predominant.
e. In-band Input amplitude - Since input amplitude is one factor In the phase comparator's gain Kd, and since Kd IS a factor In the
loop gain Kv damping is also a function of
input amplitude. When the input amplitude
IS low, the lock-up time may be limited by
the rate at which the low-pass capacitor
can charge with the reduced phase comparator output (see d above).

(66)

4-238

ThiS section deals with measurements of PLL
operation. The techniques suggested are
meant to help the deSigner in evaluating the
performance of the PLL dUring the initial
setup period as well as to pOint out some
pitfalls that may obscure loop evaluation.
Recognizing that the test equipment may be
limited, techniques are deSCribed which require a minimum of standard test items.
The majority of the PLL tests deSCribed can
be done with a Signal generator, a scope and
a frequency counter. Most laboratories have
these. A low cost digital voltmeter will faCilitate accurate measurement of the veo conversion gain. Where the need for a FM
generator arises, It may be met In most cases
by the VCO of a Signetics PLL. Any of the
loops may be set up to operate as a veo by
simply applying the modulating voltage to the
low-pass filter terminal(s). The resulting generator may be checked for linearity by using
the counter to check frequency as a function
of modulating voltage. Since the VCOs may
be modulated right down to DC, the calibration may be done In steps. Moreover, loop
measurements may be made by applying a
constant frequency to the loop input and the
modulating signal to the low-pass filter terminal to simulate the effect of a FM input so that
an FM generator may be omitted for many
measurements.

FREE-RUNNING FREQUENCY
Free-running frequency measurements are
easily made by connecting a frequency counter or oscilloscope to the VCO output of the

Signetics Linear Products

Application Note

Modeling the PLL

AN178

loop. The loop should be connected in its
final configuratton with the chosen values of
input, bypass, and low-pass filter capacitors.
No input signal should be present. As the
free-running frequency IS read out, It can be
adjusted to the desired value by the adjustment means selected for the particular loop.
It is important not to make the frequency
measurement directly at the timing capacitor,
unless the capacity added by the measurement probe IS much less than the timing
capacitor value, since the probe capacity will
then cause a frequency error.

,--------------,

CAPACITOR

L-------IPHASE-LOCKED 1
L2~
J

__

L.. _ _ _ _ _ _ _ _ _ _

When the frequency measurement IS to be
converted to a DC voltage for production
readout or automated testing, a calibrated
phase-locked loop can be used as a frequency meter.

TC07S8DS

a. Measurement Setup

CAPTURE AND LOCK RANGES
Figure 14a shows a typical measurement
setup for capture and lock range measurements. The signal Input from a variable frequency oscillator is swept linearly through the
frequency range of Interest and the loop FM
output is displayed on a scope or (at low
frequencies) X-V recorder. The sweep voltage is applied to the X OO CeAIT, AEXT

INPUT MODULATION

I

,

~:I

!

a. Underdamped With

I

I

I

1\

ERROR VOLTAGE

I

i

~
:

!

.,

I
I

I

::
i
~'tiH++-r--

I\..

it

INPUT MODULATION

I

t

:;:

=0)

(CEXT

Damped With

t = 1.0

I

,,
,

i

=eeRll, REXy =O)

b. Critically

+~f

I

I
.

~~

V- r - -

I

'-..

/

ERROR VOLTAGE
(C < CeAIT, REXT > 0)

c. Overdamped With

(C< 

10

•

Application Note

Signetics Linear Products

Modeling the Pll

AN17S

~. 0.7

~

0.0
OS
0.'

is

"

0.3

'"~

02

!!:

'"0

~

~

01

if:

/

~

031\

g...

\

"';'

i\.\\

OS,\

2"
s
!

DAMPING

0.1

FACTOR

~

--......::

,

~
\'\ r--.....

~

~

\

\

2

S

1

r-

w-3dB

LOW FREQUENCY

Wn

AMPLITUDE
0.3
0.5
0.7
1.0
5.0

~ if'
OJ /

-0.2
-03

PEAK AMPLITUDE

'-1"3

6.0dB
3.2dB
2.2dB
1.3dB
0.5dB

1.8
2.1
2.5
4.3
10

_nt

a. Transient Phase Error as an Indication of Damping

b. Ratio of Peak Amplitude to Low Frequency Amplitude of
Error Voltage From Modulating Frequency Response

Figure 19. Estimating the Damping In a Second-Order PLL

December 1988

4-242

NEjSE564

Signetics

Phase-Locked Loop
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The NE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As
shown in the Block Diagram, the NE564
consists of a veo, limiter, phase comparator, and post detection processor.

• Operation with single 5V supply
• TTL-compatible inputs and
outputs
• Guaranteed operation to 50MHz
• External loop gain control
• Reduced carrier feedthrough
• No elaborate filtering needed in
FSK applications
• Can be used as a modulator
• Variable loop gain (externally
controlled)

D, F, N Packages

.+

1

l.OOPGAIN

CONT11OI.
INPUT TO PHASE
COWAAATOf'
FROM yeo

15 H't'STIERU.S SET

2
3

14

LOOPFILT£ft

..

13 FRtEQ Sl!:T CAP

lOOP FLT£fI

5

FM/IIIF...-.sr

6

atAS FILTER

7

ANALOG OUTPUT

"

vee OUTPUT

9

veo OUTPUT TTL

.2

TOP VIEW

APPLICATIONS
•
•
•
•
•

High-speed modems
FSK receivers and transmitters
Frequency synthesizers
Signal generators
Various satcom/TV systems

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

16-Pin Plastic SO
16-Pln Plastic DIP

ORDER CODE

+70°C

NE564D

+70°C

NE564N

16-Pin PlastIC DIP

-55°C to + 125°C

16-Pin Cerdlp

-55°C to + 125°C

-

SE~
SE564F

BLOCK DIAGRAM

.

,-----------------------~-------------------,

,-------

--------

V'
~-----

14 - - - - - - - - - ,
I

I

I
I
I
I
I
I

'0

!!-------

July 8, 1988

t----------______

4-243

-.J

853-0908 93801

•

Signetics Unear Products

Product Specification

NE/SE564

Phase-locked loop

ABSOLUTE MAXIMUM RATINGS
SYMBOL
V+

PARAMETER

RATING

Supply voltage
Pin 1
Pin 10

UNIT
V

14
6

lOUT

(Sink) Max (Pin 9)

10

mA

Po

Power dissipation

600

mW

TA

Operating ambient temperature
NE
SE

to +70
-55 to +125

·C

Storage temperature

-65 to +150

·C

TSTG

o

NOTE:
Operation above 5V Will require healstnking of the case.

DC AND AC ELECTRICAL CHARACTERISTICS Vee - 5V, TA - 25·C, 10 - 5MHz, 12 = 400llA, unless otherwise specilied.
SE564
SYMBOL

PARAMETER
Maximum VCO frequency

Lock range

Capture range

VCO frequency drift with
temperature
VCO free-running frequency
VCO frequency change with
supply voltage

Demodulated output voltage

Distortion

SIN

Signal-to-noise ratio
AM rejection
Demodulated output at
operating voltage

lee

Supply current
Output
"1" output leakage current
"0" output voltege

July 8, 1988

NE564

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

C, - 0 (slray)

50

65

45

60

MHz

Input ~ 200mVRMS TA = 25·C
TA 125·C
TA =-55·C
TA - O·C
TA = 70·C

40
20
50

70
30
80

40

70

% 0110

Input ~ 200mVRMS, A2 = 270.

20

=

70
40

10=5MHz, TA=-55·C to +125·C
TA - 0 to +70·C
- 0 to +70·C
10 = 500kHz, TA = -55·C to + 125·C
TA = 0 to +70·C
C, = 91pF
Ac - 1000. "Internal"

20

30

% 0110
PPM/·C

600
300

800
500

4

Vee = 4.5V to 5.5V
Modulation frequency: 1kHz
10 = 5MHz, input deviallOn:
2%T-25·C
1%T=25·C
1%T=0·C
1%T - -55·C
1%T-70·C
1%T-125·C

30

500 1500

5

6

3

8

16
8

28
14

6

10

12

16

3.5

16
8

5

6.5

MHz

3

8

% 0110

28
14
13

mVRMs
mVRMS
mVRMS
mVRMS
mVRMS
mVRMS

15

Deviation: 1% to 8%

1

1

%

Sid. cortdition, 1% to 10% deY.

40

40

dB

SId. condition, 30% AM

35

35

dB

12
14

mVRMS
mVRMS

ModulallOn frequency: 1kHz
10 - 5MHz, input deviation: 1%
Vee- 4•5V
Vee- 5•5V

7
8

12
14

7
8

Vee - 5V I" ',0

45

60

45

60

rnA

VOUT = 5V, Pins 16, 9
lOUT - 2mA, Pins 16, 9
lour - 6mA, Pins 16, 9

1
0.3
0.4

20
0.6
0.8

1
0.3
0.4

20
0.6
0.8

IlA

4-244

V
V

Signetics Linear Products

Product Specification

Phase-Locked Loop

NE/SE564

TYPICAL PERFORMANCE CHARACTERISTICS
Lock Range vs Signal Input

VCO Capacitor vs Frequency

1000
10'

8

I

I

I

I

I
>

10'

I

~
~

,'P'N, O"A"

E

U
Z

I

~

:!

10'

~

.

10'

u

;!

100

;;;
...'"

8

Z

~

10'

w

0

~

~

I

I

I PIN~ = 400tlA

~

.

i\

::>

;!;

'\

!

07

08

\\ if {

09

10

/

11

\.

10

J

I

\

10

",

U

10

I

'Y

5M

12

1()1

10J

•

10~

10·

FREQUENCY kHz

Vee = 5V

r

13

NORMALIZED LOCK RANGE

Typical Normalized VCO
Frequency as a Function of
Pin 2 Bias Current

Typical Normalized VCO
Frequency as a Function of
Pin 2 Bias Current

110

I
I

Normalized veo Frequency
as a Function of Temperature

I
I

veo FREOUENCY 5MHz

>

;
u

, o.

,

FREQUENCY 50MHz

.....

.......

,/

"

096
600IJ.A

400

200

BIAS CURRENT (uA), PIN 2

July 8, 1988

+200

~;
i

..... 1--,

090

'00
09.
090

-6oo1'A -400

-200

BIAS CURRENT ("A), PIN 2

4-245

,

EliAS CURRENT - 2oo"A

~ , 05 FREO~

!-....

09.

7

, '0

0

'00

+200

+400

FRE~UEHCY

--

======

BlAl CURrNT 12ool-{

-50

-25

500 KHz

25

50

TEMPERATURE UN "el

""""" .......

75

100

125

Product Specification

Signetics Uneor Products

NEjSE564

Phase-Locked Loop

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Y.· PHASE COMPARATOR'S
OUTPUT VOLTAGE IN mY

8001
600

tI

t
I

'.=',OMHz

r

-t
200

yeo FREQUENCY
INMH.
6

!

1.4

'0= 1.0MHz

ri
I

40

-400

16l)

200

400

6l)0

800

o ~ PHASE
ERROR IN
DEGREES

-200

.8

--

.6

-600

-800
VCO Output Frequency as a Function of
Input Voltage and Bias Current (Ko)

Variation of the Phase Comparator's Output Voltage
vs Phase Error and Bias Current (Ko)

TEST CIRCUIT
+5Yo---'---~-1~-'--'

R3

"!:'

lK

yeo
OUTPUT

Rl

390

INPUT C3

o--i r--t---i6 1
O.II1 F

2

10

16

9

3

lK

"!:'

...c---1~--I
R2

DEMODULATEO

14

O.II1F ~ OUTPUT

564

13

Cl
12
8

"!:'
TCl3801$

July 8, 1988

4-246

Y.,INmY

Signetics Linear Products

Product Specification

NEjSE564

Phase-Locked Loop

logiC compatible signals. For high data rates,
a considerable amount of carner will be
present at the output of the PLL due to the
wideband nature of the loop filter. To avoid
the use of complicated filters, a comparator
with hysteresis or Schmitt tngger IS reqUired.
With the conversion gain of the VCO fixed,
the output voltage as given by Equation 1
varies according to the frequency deViation of
fiN from fo. Since this differs from system to
system, it IS necessary that the hysteresis of
the Schmitt tngger be capable of being
changed, so that it can be optimized for a
particular system. This IS accomplished In the
564 by varying the voltage at Pin 15 which
results In a change of the hysteresis of the
Schmitt tngger.

FUNCTIONAL DESCRIPTION
(Figure 1)
The NE564 is a monolithic phase-locked loop
with a post detection processor. The use of
Schottky clamped transistors and optimized
device geometnes extends the frequency of
operation to greater than 50MHz.
In addition to the classical PLL applications,
the NE564 can be used as a modulator with a
controllable frequency devlallOn.
The output voltage of the PLL can be written
as shown in the following equallOn:
(fIN-fO)
Vo=--Kvco

(1)

Kvco = conversion gain of the VCO

For FSK signals, an important factor to be
considered IS the dnft In the free-running
frequency of the VCO Itself. If this changes
due to temperature, according to Equation 1 it
Will lead to a change In the DC levels of the
PLL output, and consequently to errors in the

fiN = frequency of the Input signal
fo - free-running frequency of the VCO
The process of recovering FSK signals involves the conversion of the PLL output Into

digital output signal. This is especially true for
narrow-band signals where the deviation in fiN
Itself may be less than the change in fo due
to temperature. This effect can be eliminated
if the DC or average value of the signal is
retrieved and used as the reference to the
comparator. In this manner, variations In the
DC levels of the PLL output do not affect the
FSK output.

VCO Section
Due to Its Inherent high-frequency performance, an emitter-coupled oscillator is used
In the VCO. In the circuit, shown In the
equivalent schematic, transistors 021 and
023 with current sources 025 - 026 form the
basic oscillator. The approximate free-running
frequency of the oscillator IS shown In the
follOWing equation:

1

fo=------

(2)

22 Rc (C1 + Cs)

EQUIVALENT SCHEMATIC

r-----------------'r-------------------,
,
,
I
II
I

±.

"

I

I
I
I
I
I
I
I
I
I
I

Of E!
c

0,
I

I

I
I
I
I
I
I

I
I
I

: 0,

hi

0,

o.

('

,..

I

___________
~ _____

L
.
n

"

a"

~

r""

"I

a.

~

,

i ::

J!
a

J ~

r: 'I

a.

.. va •

r

0" --'1'1
~I
0,.

.,

...!.

)

~

D.~

.
,

D.

I
vco
IL _________________________
~
I

" "

.,

~

...... ~ '''I ~

On

0"

~

rd· ~'W"

·i:

I:
,II
II
II
II
II
II
II

0 ..

•

r--

.;~

I
II
II

1'1,.

0 ••

Q.

1Otr.

vt I>

I
I
I
I
I

;::~

0"

D.

°

~
r
Q..

t~

":~
~ D.

L......o-- I

0"

*0. II

~

a.

10k

10k

1'1"

Q,'I ..."J'"
II
II
II
II ______
__

A

0..

:;

;11

I::~

0"

----

- - --:=\1

~~*

J"

______________

:: .. ··-·,·:i _ .......

I

; ~

:

I
I
I
I
I ; ______ "

0,

,GO

~

0"

i: ~

J.

.tv ~'.II:'!l- ...!!'·Il

~
a;t

h-

~ L ____________

.,

J~

~

:ri ,

I',
I"
II
II
I

~~D.

~

1

II

I

. :• $11l"

.

Va,

~ ~IIII
a;oJ

I

I

II
II

lk

I
I
I

.

~ .~. ~iII:
II -:-:
I!
~

0,

I"
I

PHASE
C'OMPAAATOR

II

it: ti itI

I

I
I
I
I
I
I
I

r

LIMITER

I
I

0.,

V-

'J
~.

2;

"I '1(11/ J "),0" 0"
___________
~L

.,

~

.J

I
I
I
I
I
I
I
I

L_~M~'~~_..J

TC13812S

Figure 1
July 8, 1988

4-247

•

Signetics Linear Products

Product Specification

NE/SE564

Phase-Locked Loop

Rc - R19 = R20 - lOOn (INTERNAL)
Cl = external frequency setting capacitor
Cs

m

LOCK RANGE ADJUSTMENT

stray capacitance
LOOP FILTeR
00'",

Vanation of Vo (phase detector output voltage) changes the frequency of the oscillator.
As indicated by Equation 2, the frequency of
the oscillator has a negative temperature
coefficient due to the positive temperature
coefficient of the monolithiC resistor. To compensate for thiS, a current IR with negative
temperature coeffiCient IS Introduced to
achieve a low frequency drift with temperature.

~
":"
ANALOG OUT
POST DETECtiON FILTER

,.

Phase Comparator Section

IV

The phase comparator consists of a doublebalanced modulator with a limiter amplifier to
improve AM rejecllon. Schottky-clamped vertical PNPs are used to obtain TTL level
inputs. The loop gain can be varied by changing the current in 0 4 and 015 which effectively changes the gain of the differential amplifiers. ThiS can be accomplished by introdUCing
a current at Pin 2.

IV

"',
plifier 042 - ~ together with an external
capacitor which IS connected at the amplifier
output (Pin 14). This forms an integrator
whose output voltage is shown in the following equation:
(3)

Post Detection Processor
Section

.....

Figure 2. FM Demodulator at 5V
The comparator with hysteresis is made up of
049 - 050 with positive feedback being provided by 047 - 0 48• The hysteresis is varied
by changing the current in 052 with a resulting
variation in the loop gain of the comparator.
This method of hysteresis control, which is a
DC control, provides symmetric variation
around the nominal value.

gM = transconductance of the amplifier

The post detection processor consIsts of a
unity gain transconductance amplifier and
comparator. The amplifier can be used as a
DC retriever for demodulation of FSK signals,
and as a post detection filter for linear FM
demodulation. The comparator has adjustable hysteresis so that phase jitter in the
output signal can be eliminated.
As shown In the equivalent schematic, the DC
retriever is formed by the transductance am-

Design Formula

C2 ~ capacitor at the output (Pin 14)

The free-running frequency of the VCO is
shown by the following equation:

VIN = Signal voltage at amplifier Input
With proper selection of C2, the integrator
time constant can be varied so that the output
voltage is the DC or average value of the
input signal for use in FSK, or as a post
detection filter in linear demodulation.

(4)

fO - 22 Rc (Cl + CS)
Rc= 100n
Cl = external cap in farads
Cs - stray capacitance

5Y

1'1 LOCK RANGE ADJUSTMENT

+

001~
~ LOOP FILTER

ADJUSTMENT

MODULATING

,....

":" 001pF

INPUT

:~:=s::: 04
lIAS FILTER

1K

..ci
":"

01pF

INPUT

~

OA7uF

,...,

ANALOG OUT

7

~o.t.u.F
200

,.

IV

,.
IV

,zy

FREQUENCY SET CAP

MODut.ATED OUTPUT

ITTL>

"'"..,.
Figure 3. FM Demodutator at 12V
July 8, 1988

FINE FREQUENCY

Figure 4. Modulator

4-248

Product Specification

Slgnetlcs Linear Products

NE/SE564

Phase-Locked Loop

The loop filter diagram shown is explained by
the following equation:

.
1
Fs - - - - (First Order)
1 +SRC3

Modulation Techniques
(5)

R = R12 = R13 = 1.3kn (Internal)"
By adding capacitors to Pins 4 and 5, a pole is
added to the loop transfer function at

w=-

RC3

Figure 5 shows a high-frequency FSK decoder designed for input frequency deviations of
± 1.0MHz centered around a free-running frequency of 10.BMHz. The value of the timing
capacitance required was estimated from Figure B to be approximately 40pF. A trimmer
capacitor was added to fine tune fo' to
10.BMHz.

the frequency deviation In the input signal
should be 1 % or higher.
The NE564 phase-locked loop can be modulated at either the loop filter ports (Pins 4 and
5) or the input port (Pin 6) as shown in Figure
4. The approximate modulation frequency
can be determined from the frequency conversion gain curve shown in Figure 5. This
curve will be appropriate for signals injected
into Pins 4 and 5 as shown in Figure 4.

The lock range graph indicates that the
± 1.0MHz frequency deviations will be within
the lock range for input signal levels greater
than apprOlamately 50mV with zero Pin 2 bias
current. (While smctly this figure IS appropriate only for 5MHz, it can be used as a guide
for lock range estimates at other fo' frequencies).

FSK Demodulation

The 564 PLL is particularly attractive for FSK
NOTE:
demodulabon since it contains an internal
"Refer to Figure 1.
voltage comparator and VCO which have TTL
compatible inputs and outputs, and it can
operate from a single 5V power supply. DeAPPLICATIONS
modulated DC voltages associated with the
FM Demodulator
mark and space frequencies are recovered
The NE564 can be used as an FM demodula- with a single external capacitor in a DC
tor. The connections for operation at 5V and
retriever without utilizing extensive filtering
12V are shown in Figures 2 and 3, respectivenetworks. An internal comparator, acting as a
ly. The input signal is AC coupled with the . Schmitt trigger with an adjustable hystereSIs,
output signal being extrscted at Pin 14. Loop
shapes the demodulated voltages into comfiltering is provided by the capacitors at Pins 4
patible TTL output levels. The high-frequency
and 5 with additional filtering being provided
design of the 564 enables it to demodulate
by the capacitor at Pin 14. Since the converFSK at high data rates in excess of 1.0M
sion gain of the VCO is not very high, to
baud.
obtain sufficient demodulated output signal

The hysteresis was adjusted experimentally
via the 10kn potentiometer and 2kn bias
arrangement to give the waveshape shown in
Figure 7 for 20k, 500k, 2M baud rates with
square wave FSK modulation. Note the magnitude and phase relationships of the phase
comparators' output voltages with respect to
each other and to the FSK output. The highfrequency sum components of the input and
VCO frequency also are visible as noise on
the phase comparator's outputs.

,,.
OUTPUT

,*,'O.FIfiY

.....
p:=j
- ..... ~------------------~
figure 5. 10.8MHz FSK Decoder Using the 564

July B, 198B

4-249

•

Product Specification

Signetics Linear Products

NEjSE564

Phase-Locked Loop

...,:.lmv

=

-

50,oi5

- ,..- ,..- ,..."..

-

lo..-

'"--

'"--

...-

t--

~

'"--

- - a. Data Rate

= 20k

I---

-

.......

"

-

~

f-

-

~

I'--

,.........

b. Data Rate

Baud

100mV

= 500k

Baud

5OOn$

lODmV

2V

c. Data Rate

=2.0m Baud

NOTES:

1 Top trace"" Pin 4
2. Center trace = Pin 5
3 Bottom trace = Pin 16

Figure 6. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs

OUTLINE OF SETUP
PROCEDURE
1.

2.

3.

Determine operating frequency of the
VCO:
If .;. N In feedback loop, then
fo = N X fiN.
Calculate value of the VCO frequency set
capacitor:
Co

1

~--­

-

2200 fo

July 8, 1988

4.

5.

Set 12 (current sinking into Pin 2) for ~
1001lA. After operation is obtained, this
value may be adjusted for best dynamic
behavior.
Check VCO output frequency with digital
counter at Pin 9 of device (loop open,
VCO to q, de!.). Adjust Co trim or frequen·
cy adj. Pins 4 - 5 for exact center fre·
quency, if needed.
Close loop and Inject input signal to Pin
6. Monitor Pins 3 and 6 with two·channel

4-250

6.

7.

scope. Lock should occur with A---'
Figure 7. NE564 Phase-Locked Frequency Multiplier with VCXO

July 8, 1988

4-251

Signetics

AN179
Circuit Description of the
NE564
Application Note

Linear Products

CIRCUIT DESCRIPTION Of The
NE564

functional With vanable supply voltages between 5 and 12V'

The 564 contains the functional blocks shown
In Figure 1. In addition to the normal PLL
functions of phase comparator, VCO, amplifier and low-pass filter, the 564 has Internal
CirCUitry for an Input signal limiter, a DC
retriever, and a Schmitt tngger. The complete
circuit for the 564 IS shown in Figure 1.

Signal limiting IS accomplished In the 564 With
a differenlial amplifier whose output voltage IS
clipped by diodes D, and D2 (see Figure 2)
Schottky diodes are used because their limitIng occurs between 0 3 to OAV Instead of the
0.6 to 0.7V for regular IC diodes. ThiS lower
limiting level IS helpful In biasing, especially
for 5V operation. When limiting, the DC voltage across R2 R3 remains at the Schottky
diode voltage. Good high-frequency performance for 02 and 0 3 IS achieved With current
levels In the low rnA range. Current-source
biasing IS established via the current mirror of
D5 and 04 (See Figure 1).

Limiter
The input limiter functions to produce a near
constant amplitude output that serves as the
Input for the phase comparator. Eliminating
amplitude variations In the FM Input Glgnal
Improves the AM rejection of the PLL. Additional features of the 564's limiter are that It IS
capable of accepting TTL Signals, operates at
high frequencies up to 50MHz, and remains

Base biaSing for 03 IS of concern because of
the nature of the Input Signal which can be
either a TTL digital signal of 0 to 5V amplitude

I
I

I
I
I _________________________
veo
12
13
':'
I
L
~

Figure 1. Schematic Diagram of NE564

December 1988

4-252

or a low-level, AC coupled analog signal.
Compatibility for either type is achieved by
modifying the limiter of Figure 2 wilh the
addition of the vertical Schottky PNP transIstors 0, and 05 as shown In Figure 3. The
Input Signal voltage appears as a collectorbase voltage for 0" which presents no problems for either high TTL level Inputs or lowlevel analog inputs. 05 is In turn diode-biased
by D3 and D4 (see Figure 1) which places the
base voltages of 0, and 05 at approximately
1.0V. This same biasing network establishes
a 1.3V bias at the base of 0,3 for biasing the
phase comparator section. A differential output Signal from the Input limiter IS applied to
one Input of the phase comparator (Og
through 0,2) after buffering the level shifting
through the 0 7 - Os emitter-followers.
*When operating above 5Voc, a limiting reSistor must be
used from Vee to Pin 10 of the 564

Application Note

Signetics Unear Products

Circuit Description of the NE564

AN179

.Vee

.Vee

...••

.....
..••

...
at

...

....

...

v..

TC074tOS

Figure 2. Basic Limitar Stage

Figure 3. Umlter Stage With Input Buffering

Phase Comparator
The phase comparator section of the 564 Is
shown in Figure 4. It is basically the conven·
tional, double·balanced mixer commonly
used in PLL circuits, with a few exceptions.
The transconductance, gM, for the 0'3 - 0'4
differential amplifier is directly proportional to
the mirror current in 0'5. Thus, by externally
sinking or sourcing current at Pin 2, gM can be
changed to alter the phase comparator's
conversion gain, K.t. The nominal current
injected into this node by the internal current
source is O.75mA for 5V operation. If the
current is externally removed by gating. the
phase comparator can be dIsabled and the
VCO will operate at its free-running frequen·

.Vee

•

...

,

·.2'.311

.•••.
FIIOII
¥CO

cy.

Figure 4. Phase Comparator SectIon

December 1988

4-253

•

Signetlcs Linear Products

Application Note

Circuit Description of the NE564

AN179

Vo • PHASE COMPARATOR S
OUTP'..JT vOt. T AGE IIH mV

10

~

10MHz

Figure 5. Variation of the Phase Comparator's Output Voltage vs Phase Error and Bias Current
--------------~

December 1988

4-254

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

The variation of Kd with bias current at Pin 2
is shown In the experimental results of Figure
5. Note that the inherent 90° phase error in
the loop produces an approximate zerophase comparator output voltage. For any
particular bias current, the slope of the line is
the Kd conversion gain for the phase comparator. Numerically the data of Figure 5 can be
expressed as

"co

...

,,.
'"

~~----~-------------4

0"

...

."

......

VoltS)
Kd",,0,46 ( rad

..,

'"

'"

+ 7.3

I" "I

~

'"

0"

'"

,,!

.

De

Figure 6. yeO Section of NE564

~)
X IBIAS (IlA)
rad X !lA
(1)

.

.,

X 10- 4 (

Equation 1 is valid for bias current less than
800llA where saturation occurs within the
phase comparator.
The current level established in 015 of Figure
3 determines all other quiescent currents in
the phase comparator (09 through 014)' Currents through R12 and R 13 set the commonmode output voltage from the phase comparator (Pins 4 and 5). Since this common-mode
voltage is applied to the veo to establish its
quiescent currents, the veo conversion gain
(Ko) also depends upon the bias current at
Pin 2.

veo

The veo is of the basic emitter-coupled
astable type with several modifications included to achieve the high frequency, TTL compatible operation while maintaining low frequency drift with temperature changes. The
basic oscillator in Figure 6 consists of 019,
020, 021, and 023 with current sinks of 025
and 026. The master current sink of 028
keeps the total current constant by altering
the ratio of currents in 025 - 0 26 and the
dummy current sink of 0 27 ,
The input drive voltage for the veo is made
up of common-mode and difference-mode
components from the phase comparator. After buffering the level shifting through
017-018 and R15-R16, the veo control
voltage is applied differentially to the base of
027 and to the common bases of 025 and
026·

The veo control voltages from the phase
comparator are the Pin 4 and Pin 5 voltages
or

0'
Figure 7. yeO Waveshapes

(2)

V5 = VC12 = V B17 = VCM - Y2VOM

(3)

where VCM and VOM are the respective common-mode and difference-mode voltages.
December 1988

4-255

•

Application Note

Signetics Linear Products

Circuit Description of the NE564

Emitter-followers 017 and 01B convert these
control voltages Into control currents through
0 6 and 07 of the form
16 =

~
[VCM - Y2VOM - 3
A15

17 =

~
[VCM + hVOM - 3V8E ]
A16

VSE]

(10)
where 0';;; x .;;; 1. Thus x is defined to be

(4)

(S)

These Individual currents are summed in Os
and become with A 15 = A 16 = R.
IB = I = 16 + 17 = ~(VCM - 3 VSE)

AN179

(11)
Currents 16 and 17 establish proportional currents in 025, 026, and 027 in a manner similar
to the analysis above Since the current in 02B
is a constant, or
10 = IC2B = IE25 + IE26 + E27A + IE278

(6)

Writing 16 and 17 as functions of the total I
current gives
(7)

(8)

Now consider variations in 16 and 17 while I
remains constant.
Let 'x' Indicate the current imbalance such
that

It can be shown that the 07 - 0 8 diode pair
will cause Identical differential currents to be
reflected in both the 025 - 026 and the
027A - 0278 differential amplifier pairs. Consequently, the constant-current of 10, jointly
shared by the differential amplifier pairs, will
divide In each pair with the same x factor
Imbalance as In Equation 11.
IE25 + IE26 = x 10

(12)

X

IE25 = IE26 =

(13)

210

IE27A + IE27B = (1 - x) 10
1-x
IE27A = IE27B = {-2-)lo

(14)

(1S)

Now consider placing a capacitor between
the collectors of 025 and 026 (Pins 12 and
13). Oscillation will occur with the capacitor
alternately being charged by 021 and 023 and
constantly discharged by 025 and 026. When
the 021 and 022 pair conducts, 023 and 024
will be off, causing a negative ramp voltage to
appear at Pin 13 and a constant voltage at
Pin 12 as shown in Figure 7. During the next
half-cycle, the transistor roles and voltages
are reversed. Capacitor discharge is via 025
and 026, which act as constant-current sinks
with current amplitudes as in Equation 13.
During each half-cycle, the capacitor voltage
changes linearly by UN volts in Ll.T seconds
where
(16)

and
C2Ll.V
Ll.T=--.
IE25

Combining these two equations with Equation
13 gives a half period of
4C A20
Ll.T=--

(18)

x

(9)

..

(17)

Utilizing Equation 11 with the Ll.T expression
gives the desired veo frequency expression
of

-

veo FREOUENCY

VOM
VOM
]
fa = fo'(1 + ) = fa' [
AI
2(VCM-3 VSE)
(19)
where fa' is the VCO's free-running frequency
given by
f ,-

a -

-400

800
VOIN mV

1

22 A20 C

(20)

Equation 19 shows that the oscillator frequency is a linear function of the differential
voltage from the phase comparator. Aesistors
A35 and A36 function to insure that an initial
current imbalance exists between the
025 - 026 transistor pair and the dummy 027.
This imbalance insures that the oscillator is
self-starting when power is first applied to the
circuit.
The VCO conversion gain is determined as

010

fa'

aVOM

AI

Ko=-_=_H~

Figure 8. VCO Output as a Function of Input Voltage and Bias Current
December 1988

4-256

(21)

which is valid as long as the transistor's VBE
changes are small with respect to the common-mode voltage. Both fa and Ko are in-

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

16

>---0

FSK OUT

I
I
I
I

I
I
I
I
DC RETRIEVER
'-___________
.JI

HYSTERESIS

ADJUST

Figure 9. Post Detection Processor for FSK
versely proportional to R, which has a strong
positive temperature coefficient. An internal
current IR having an equal and opposite
negative temperature coefficient is inserted
into the VCO as shown in Figure 6.
Experimental determination of Ko can be
found from the data of Figure a where Ko is
the slope of either line. Numerically these
results are for ISlAS = O.
MHz
rad
Ko = 0.95-- = 5.9 X 106- - V
volt-sec
and for ISlAS = aOOMA
MHz
rad
Ko = 1.7-- = 10.45 X 106- - V
volt-sec
(23)

It must be noted that the specific values
obtained for Ko in the manner above are valid
only for the 1.0MHz free-running frequency
where the data was taken. However, good
estimates for Ko at other free-running frequencies can be obtained by linearly scaling
Ko to the desired fo'. Thus, it is sometimes
convenient to define a normalized Ko as
Ko(norm)

= fd

rad
= 5.9 -y(ISIAS

rad

= 0)

= 1 0.45-y (ISlAS = aOOMA)

December 19aa

Ko(any fo')

= Ko(norm)fO"

(25)

The additional VCO circuitry of 029 through
036 functions to produce the TTL and ECl
compatible outputs at PinS 9 and 11.

Amplifier
(22)

Ko

The Ko estimate for any bias then can be
obtained by multiplYing the normalized conversion gain by the desired free-running frequency, or

(24)

The difference-mode voltage from the phase
comparator is extracted and amplified by the
amplifier In Figure 1. The single-ended output
from this amplifier serves as Input signals for
both the Schmitt Trigger and a second differential amplifier. low-pass filtering with a large
capacitance at Pin 14 produces a stable DC
reference level as the second input to the
Schmitt Trigger. When the Pll is locked, the
voltage at Pin 14 IS directly proportional to the
difference between the input frequency and
fo'. Thus Pin 14 provides the demodulated
output for an FM Input signal.

Schmitt Trigger
In FSK applications, the Pin 14 voltage will
assume two different voltage levels corresponding to the mark and space input frequencies. A voltage comparator could be
used to sense and convert these two voltage
levels to logic compatible levels. However, at
high data rates, VDM Will contain a consider-

4-257

able amount of carrier signal which can be
removed by extensive filtering. Normally this
complex filtering requires qUite a few components, most all of which are external to the
monolithic PlL. Also, since the control voltage for the comparator depends upon Ko and
the deviations of the mark and space frequencies from fo', the filtering has to be
optimized for each different system utilized.
However the necessary DC reference level
for the comparator is present In the Pll but
buried In carner-frequency feedthrough which
appears as nOise in the system. A Schmitt
trigger with variable hysteresIs can be used
successfully to decode the FSK data without
the need for extensive filtering.
Consider the system shown in Figure 9 where
the input signal is the single-ended output
derived from the amplifier section of the 564.
The DC retriever functions to establish a DC
reference voltage for the Schmitt trigger. The
upper and lower trigger pOints are adjustable
externally around the reference voltage giving
the variable hysteresis. For very low data
rates, carrier feedthrough will be negligible
and the ideal situation depicted in Figure 10
results. Increased data rate produces the
carrier feedthrough shown In Figure 10b,
where false FSK outputs result because the
feedthrough amplitude exceeds the hysteresis voltage. Having the capability to increase
the hysteresis, as in Figure 10c, produces the
desired FSK output in the presence of carrier
feedthrough.
Another important factor to be considered is
the temperature drift of the fo' in the VCO.
Small changes in fo' will change the DC level
of the input voltage to the Schmitt trigger.
This DC voltage shift would produce errors in
the FSK output in narrow-band systems
where the mark and space deviations In fiN
are less than the fo' change with temperature. However, thiS effect can be eliminated if
the DC or average value of the amplifier
signal IS retrieved and used as the reference
voltage for the Schmitt trigger. In this manner,
variations In the fo' with temperature do not
affect the FSK output.

•

~

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

IN

~

__~r--l~___ __
TIME

a. Low Data Rates With Negligible Carrier Feedthrough

'51<

OUT

1

-

TIME

b. False FSK Outputs Due to Feedthrough and Low Hysteresis

IN

'SK
OUT

T. .,

c. Increased Hysteresis Restores Proper FSK Output
in the Presence of Feedthrough
Figure 10. Waveshapes for FSK Decoding in the Post Detection Processor

December 1988

4-258

Signetics

AN180
Frequency Synthesis with the

NE564
Application Note

Linear Products

FREQUENCY SYNTHESIS WITH
THE NE564
Frequency multiplication can be achieved
with the PLL In two ways:
a. Locking to a harmonic of the input signal.
b. Insertion of a counter (digital frequency
divider) in the loop.
Harmonic locking is simpler and usually can
be achieved by setting the veo free-running
frequency to a multiple of the Input frequency
and allowing the PLL to lock. However, a
limitation of thiS scheme IS that the lock range
decreases as successively higher and weaker
harmonics are used for locking. This limits the
practical harmonic locking range to multiples
of approximately less than ten. For larger
multiples, the second scheme is more desirable.
A block diagram of the second scheme IS
shown in Figure 1a. Here, the loop IS broken
between the veo and the phase comparator
and a counter is Inserted. In thiS case, the
fundamental of the divided VCO frequency is
locked to the input reference frequency so
that the VCO is actually running at a multiple
of the reference frequency. The amount of
multiplication is determined by the counter.
An obvious practical application of this multiplication property is the use of the PLL in wide
range frequency syntheSizers.
In frequency multiplication applications, it is
important to take into account that the phase
comparator is actually a mixer and that its
output contains sum and difference frequency
components. The difference frequency IS DC
and is the error voltage which dnves the VCO

to keep the PLL in lock. The sum frequency
components (of which the fundamental IS
twice the frequency of the input signal), If not
well filtered, will induce Incidental FM on the
VCO output. ThiS occurs because the VCO IS
runOing at many times the frequency of the
input signal and the sum frequency component which appears on the control voltage to
the veo causes a periodic variation of ItS
frequency about the desired muillple. For
frequency multiplication, It is generally necessary to filter qUite heavily to remove thiS sum
frequency component. The tradeoff, of
course, is a reduced capture range and a
more under-damped loop transient response.
Producing a large number of frequencies With
close spacing reqUires a counter with a large
N for the system of Figure 1a. Large N values,
In turn, require reference frequencies too low
to be practical for commerCially available
crystals. To overcome this difficulty, a second
counter (+M) is Inserted as a prescaler as In
Figure 1b to divide down the reference frequency input This also gives more programming flexibility, since the synthesized output
frequencies are functions of both M and N
Integers, each of which can be changed
separately. As an example of fractional frequency synthesis, the two counters can be
set to generate an output frequency exactly
16/3 of the Input reference frequency. In thiS
case N = 16, M = 3, and the Initial fo' is set to
approximately 16/3 times the reference frequency Input. The output always Will be exactly 16/3 of the Input frequency as long as the
PLL remains In lock.
PLL frequency syntheSizers based upon Figure 1b find wide applications in many types of

communications systems that require precisely spaced channels having narrow bandwidths which are centered around relatively
high frequencies. For example, Citizens Band
(CB) transceiver applications require forty
channels corresponding to forty different reference frequencies, each separated by
10kHz bandwidths and centered in the
26 - 27MHz range. Channel 4 uses
27.005MHz; Channel 5 uses 27.015MHz;
Channel 6 uses 27.025MHz; and so on.
These frequencies could be produced by
uSing forty different crystals - one for each
channel. However, this becomes expensive
and adds unnecessary compleXity to the
system. Frequency-mixing techniques have
been employed to reduce the number of
crystals needed to less than one crystal per
channel. For example, one common mixer
design uses 14 crystals for 23 channels. As a
general rule, most practical approaches that
use numerous crystals and mixers to produce
discrete frequencies require more than one
crystal for every two channel frequencies
produced. As the number of channels grows
large, frequency synthesis using PLLs becomes more attractive, espeCially since usually only one or two crystals are needed.
Frequency stability of all channels will be
essentially the same as that of the crystal
reference frequency. Reduced system compleXity, size, weight, and power consumption
are key advantages of PLL synthesizers.
Since the function of frequency synthesizers
is to generate frequencies and not to linearly
decode or demodulate input signals, digital
PLLs are more commonly used than analog
loops.

IN LOCK

It! = Ie
' . = tolN

to = "II

a. Frequency Multiplication

b. Fractional-Frequency SyntheSis
Figure 1. Frequency Synthesis Using PLLs

December 1988

4-259

Signetics Linear Products

Application Note

Frequency Synthesis with the NE564

...

ANiS0

2.
I~

RE'

'In =

ose

3GMHz

I

Nt,"

I 'In .. 54MH.1:

2

SOn.

I

J

\.

I~

n~

l - I--

--.....- "" --..: 2.

a. Block Diagram Organization

""""

~

b. Waveshapes

Figure 2. Fractional Frequency Synthesis With the 564

4-260

,

1

1. n n
I I I!I I II I I I... II... I...

r r

o

December 1988

I,

~

-

{
WF15120S

Signetics Linear Products

Application Note

Frequency Synthesis with the NE564

AN180

4 .. !-1.

,

-

.....
rl-r- ,. ·

°r
-=-

N......

3

.5.

.WTl

H -'

1K

u_

".
0

...

" .5
T

rC~~'
o!t;'

3

...

'I-

..

• I-'1-

COUNmI

'in",36 MHz

~

"

,.sL

~i.! ]

.....

,.

rl":"

f=21 'MHz

300

•

.

.$V

i

.5.

5

,

•

,

.,

"r-

>-,

'--

"'"

11(

NE...
3

o.cn,.F

r-CI--:
."..!J;-

"
"at.13

3-."

I

'.U_

.

Tl
c. Circuit Implementation

Figure 2. Fractional Frequency Synthesis With the 564 (Continued)

4-261

..

"""'lOR

1

December 1988

I--

• r--

"'

'"""""1,

$

,.

2

+:.'

..

-"

":"

7

.. -

.".

•

Signetics Linear Products

Application Note

Frequency Synthesis with the NE564

Analog PLLs also can be used for frequency
synthesis applications. The 564 IS particularly
well suited for these applications because the
loop is open between the veo output and the
phase comparator input. Also, the phase
comparator input and veo output are compatible with TTL counters.

NE564 FREQUENCY SYNTHESIS
WITH CRYSTAL CONTROL
The system shown In Figure 2 has been used
to generate frequencies of 5.4MHz and
21.6MHz from a 3.6MHz crystal-controlled
source. This reference signal input IS produced by using the crystal as the frequencydetermining element in the veo of a second
PLL. The thermal stability of all three frequen-

December 1988

cles will be the same as the stability afforded
by the crystal. It may be necessary to place a
small detunlng capacitor In parallel with the
crystal to preCisely tune the PLL to the
crystal's resonant frequency and to prevent
oscillations at harmonics of the resonant
frequency. The value of this tUning capacItance must always be kept conSiderably less
than the value reqUIred to produce an fo'
without the crystal present. Otherwise the
crystal will lose control and the Input reference frequency will be set by the capacitor
alone.
A recommendation for Improved 564 operalIOn IS to utilize a divlde-by-N counter in the
loop which produces "square" waves for the
phase comparator that have as close to a

4-262

ANi80

50% duty cycle as possible. Normally, counters with even N values produce square wave
outputs perfectly compatible for the phase
comparator. Counters for odd N values more
commonly produce unsymmetrical outputs
that can be less desirable inputs to the phase
comparator. An easy modification to "square
up" odd divide-by-N counter outputs is to
insert a single toggling flip-flop stage between
the counter output and the phase comparator's input. This produces an effective 2N
multiplication of the input frequency within the
PLL. The extra factor of two IS removed by a
second toggle flip-flop whose input is the
output from the first flip-flop. This is the same
system as was previously shown In Figure 2a
where the + N counter becomes a + 2N and
M = 2 for the second counter.

AN1801

Signetics

10.8MHz FSK Decoder With
NE564
Application Note
Linear Products

FSK DEMODULATION WITH
THE 564
The 564 PLL is particularly attractive for FSK
demodulation since It contains an Internal
voltage comparator and VCO which have TTL
compatible Inputs and outputs, and It can
operate from a single 5V power supply. Demodulated DC voltages associated with the
mark and space frequencies are recovered
with a single external capacitor In a DC
retriever without utilizing extensive filtering
networks. An Internal comparator, acllng as a
Schmitt trigger with an adjustable hysteresIs,
shapes the demodulated voltages Into compatible TTL output levels. The high frequency
design of the 564 enables It to demodulate
FSK at high data rates In excess of 1.0M
baud.
Figure 1 shows a high-frequency FSK decoder designed for Input frequency deviations of
± 1.0MHz centered around a free-running frequency of 10.8MHz. The value of the timing
capacitance reqUIred was estimated from Figure 4a to be approximately 40pF. A trimmer
capacitor was added to fine tune fa' to
10.8MHz.
Figure 2b indicates that the ± 1.0MHz frequency devlallons will be within the lock
range for Input signal levels greater than
approximately 50mV with zero Pin 2 bias
current. While strictly this figure IS appropriate
only for 5MHz, It can be used as a gUide for
lock range estimates at other fa' frequencies
A more thorough analysIs confirms these lock
range conclusIons and serves as a gUide for

designing other systems. The closed-loop
gain of the PLL IS equal to the system's lock
range and IS found as the product of Kd and
Ko adjusted to 10.8MHz
(1)

Thus Pin 2 could be left as an open CirCUit
and the Internally set closed-loop gain would
be adequate for tracking the mark and space
Input frequencies. However, to be safe, a bias
adjustment as shown In Figure 1 IS recommended to allow for Kd and Ko variations from
device to device.
Designing for a capture range of approxImately 700kHz gives a low-pass filter time
constant of
Wc'O'yWL

2WL = Kv = 2 73 X 107

(2" X 700 X 103 )

=Y

T

= 1.lBms

Therefore, choose the low-pass filter capacItor as
T
1.41)1s
C=-=--""lnF
R
1.3k

February 1987

(3)

Two 1nF capacitors were selected for the
deSign
Capacitive coupling was used for the FSK
Input and IS recommended to avoid DC feedthrough. ThiS DC voltage would act as a DC
offset to shift fa' from 10.BMHz Balanced
biaSing with the 1.0kn resistors from Pin 7 to
Pins 3 and 6 also IS recommended to establish symmetrical, qUiescent current conditions
In the limiter and phase comparator secllons
of the 564 The 470n pull-up resistor for the
VCO output was found to give a rise time less
than 10ns. ThiS rise time was further reduced
by adding the lOOn resistor between PinS 9
and 11. Figure 3 shows an unmodulated
10 BMHz Input Signal and the VCO output.
Note the approximate 90° phase lag of the
VCO output

(2" X 10.8 X 106 radian)
sec

2wL = 2.73 X 107 radian
sec

273 X 107
T

volt
MHz
2WL = (0.46 - - ) (0.875-)
radian
volt

x

(2)

T

(Lock range total)

4-263

A O.l)1F DC retriever capacitor (Pin 14) has
less than 1.12 Impedance at fa, and represents a good compromise between high baud
rates (-100k baud) at fa' and higher-order
filtering If very high baud rates are used, thiS
capacitor could be made smaller with an
accompanying Increase In the Schmitt trigger
hysteresis voltage. The hysteresIs was adJusted experimentally via the 10kn potentiometer and 2kn bias arrangement to give the
waveshape shown In Figure 5 for 20k, 500k,
and 2M baud rates with square wave FSK
modulation Note the magnitude and phase
relationships of the phase comparator's output voltages with respect to each other and to
the FSK output. The high frequency sum
components of the Input and VCO frequency
also are vIsible as nOise on the phase comparator's outputs.
The phase comparator's outputs exhibit the
waveshapes shown In Figure 4 when the FM
Input IS changed from a square wave FSK
modulation to a triangular sweep at a 100Hz
modulation rate. The amplitude of the triangular sweep was Increased from that used with
square wave modulation, causing the loop to
be driven In and out of lock The loop is
locked during the smooth, linear portions of
the phase comparator's waveshapes and
locked dUring the remaining portions. Lock
and capture frequencies were measured for a
Pin 2 bias current of 375)1A and
fa' = 10.BMHz as:
Lock. fL1 = 6.2MHz fL2=16.4MHz
Capture: tCl = 9.3MH z fC2=122MHz 'P
When the loop IS locked, the phase detector's outputs represent the demodulated FM
output. When unlocked, high frequency harmonics are present, increasing in amplitude
until lock IS achieved.

•

Signetics Linear Products

Application Note

AN1801

10.8MHz FSK Decoder With NE564

.,.

~

,....

""
,

.

..

-

OK

OUII'UT

11

,.
I-

B

T

~'------.....
Figure 1. 10.8MHz FSK Decoder Using the NE564

1000
8

10'

"

n-

!
I
I

I

!

~

rt- H- ~.... ~~

I

'\.

I

j

10

10'

III'

FREQUENCY kHz

-

I
I
' ..... o,.A."

I

J

~

10'

It
\\ II loti

\\

,

\.

10

10'

0.7

0.8 0.. 1.0

v... sv

1.1

1.2

- . z E D LOCK RANCIE

0.......

a. YCP Timing Capacitor vs Frequency

1.3

........

b. Lock Range vs Input Signal Level and Bias Current

Figure 2. NE564 Characteristics

February 1987

I

f-

I

!\.
10

V-

4-264

Application Note

Signetlcs Linear Products

AN1801

10.8MHz FSK Decoder With NE564

.

~

.,:;r~

........,

~

~

"--I

PIN 4

INPUT

-v

---.I

'--'

'-

1""'\

1""'\

1'"'""\

VCO

---.J

>---J

~

---.I

'"'""
PINS

--.I

;\

Figure 3. PLL Input and veo Output for Phase and
Frequency Lock at 10.8MHz

(ai_BAUD

=

:...;;..Lv

....

I-

- - - - -

/

~ .J

-

I.S

r\ .1 ~ .I ~

..... IF

I--

-

.Jy

100.!

~

l-

IV

1111 500K IIAUO

-

I-

;: ;; ;; ;;

Figure 4. Phase Comparator Outputs Showing Lock and
capture Ranges

IV

.I ~ ./r\

.. ".

""-

.,~ .,~ ~ ~

--- --I--

I--

I--

~

1-

-

,-

(el 2.OM BAUD

.....
/ "- .;"1 "- /' "- ",., ...

...!",

~~

-

..

'1-

,....

,
--~

'- ~ "-

.
NOTE:
Top trace-Pm 4

Center trace - Pin 5
Bottom trace - Pin 16

Figure 5. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs for Various Data Rates

February 1987

4-265

•

AN181

Signetics

A 6MHz FSK Converter Design
Example for the NE564
Application Note
Linear Products

Design Example
It is desired to design an FSK converter
operating at 6MHz with deviation of ± 1%.
Supply voltage is 5V. Input to the 564 is from
a radio receiver with an amplitude of
0.5VRMS. Worst case SIN IS 10dS. An overall
loop damping factor of 0.5 is specified (!"J.

..

-

*01. .

oomur

Using the circuit in Figure 1
First the frequency determining capacitor
must be estabhshed. USing the equation

"

1

fo=--22RcCo

••• o-...,.,.,.-+--I

where Rc is the internal resistance in the
VCO OSCillator equal to 1DOn. Given two
parameters the third IS calculated fo = 6MHz;
therefore

1
Co = 22 X 100 X 6 X 106 = 75pF.
A parallel 2 - 20pF trimmer and a 68pF ± 5%
fixed mica capacitor IS chosen.
Next, signal level versus bias current and lock
range IS examined.

Figure 1. FSK Decoder Using the 564
problem with adequate lock range as it pertains to bias current. We are free to use any
loop gain necessary. The bias current sinking
into Pin 2 is set to an initial value of 200pA.
It's now possible to determine the damping
factor of the closed-loop. First, the natural
frequency of the loop is calculated from the
relationship

1000
8

.1

I

I PIN,

17',

I

~

= 4oo"A

I

JKoK;

Wn=V~-­

,

(1)

T

Iot'PlN,·-~

J

10

07

08

KO = Phase detector conversion gain

/ / 'Y0Mj'
\\ /I

\\
08

volts
in-radian

Ycc"IV

10

11

12

T

= loop filter time constant in seconds.

13

NORMALiZED LOCK RANGE

Figure 2. Lock Range vs Signal Input
The signal input to the 564 is specified to be
0.5VRMS; In the lock range graph, the input
level IS well Within the limiting region of the
564. Thus, no external AM hmiter Circuit is
required and a 10dS SIN (3.1:1) min. should
provide rehable communication with a narrow
deViation of ± 1% (± 60kHz) and there IS no
December 1988

Ko=

1.45 X 106rad/sec
0.2V

= 7.2

X 106 radians
sec'volt

Next, uSing the Ko graph (Figure 3b), ± 1
radian (_90' ± 57°); i.e., .1.8 = 1 radian, results
in an output of 0.6V /rad.
0.6
Therefore, Ko = rad = 0.6 Vlrad at

where
radians
Ko = VCO conversion gain in - - .
sec'volt

~

Multiplying .1.fo by 2" results in

For fo K 6MHz and Ie = 200pA, Ko may be
denved from Figure 3a by first constructing an
extrapolated transfer line with slope onequarter of the angle between the existing
Ie = 0 and Ie - 800 plots.

Ie = 200tJA·
The value obtained for Ko is for data taken at
1MHz and must be multiplied by 6 in order to
find the correct value.
radians
Therefore, Ko = 6 X 7.2 X 10 6 - - sec'volt
radians
(6MH z) =4.34 X 107 - - sec'volt
KoKo-Kv = (4.34 X 10 7)(0.6) = 2.6 X 10 7
The damping factor specified (0.5) is now
used to determine the necessary filter time
constant (Pins 4, 5).
1

r - 2T ~ -

Interpolation gives

T

(1.48 - 1.25MHz)
Ko a. -'-------'(0.4-0.2V)

4-266

1

1

Wn

2v'KvT = 2Kv

(2)

Signetlcs linear Products

Application Note

A 6MHz FSK Converter Design Example for the NE564

AN181

Note that the filters on Pins 4 and 5 operate
differentially with the net effect that break
frequency IS
1
wp = RC (single pole filter - 3dB freg.)

Now solVing for Wn uSing (1)
wn~

VoINmV

[

(2.6

X107) ]\12 =26X106 radians I

(3.8 X 10- 8 )

sec

fn = 4.16MHz (natural frequency of the loop
and approximate one-sided capture
BW)
The value of the loop filter capacitor may be
determined by dividing the time constant by
the value of the Internal resistance, 1 3kU.
T
3.8 X 10- 8
CL = 1.3kQ = 13 X 103

a. VCO Output Frequency as a Function of Input Voltage and Bias
Current (Ko)
Vo

PHASE COWAIUoTOJIS

OUTPUT vOt. TAGE ..... '1

'81.1.5. 200.",

29pF

ThiS value filter time constant will give a lessthan-Critically-damped response allOWing the
fast excursion In Vea frequency necessary to
good FSK reception. The tradeoff between
response speed and carner frequency harmOnic rejection Will have to be considered. A
longer time constant gives more carner releclion but slower resporlse and less damping
(Refer to equallon 2)
The next step IS to test the CirCUit under
actual operating conditions with the specified
FSK signal. The level on Pin 15 (hysteresIs
adjust) must be set In the viCinity of + 1AV In
order to attain proper FSK demodulation.
Final signal tests may be carned out with
nOise Injected through a resistive summing
network at the Input (Pin 6) to simulate the
10dB SIN
Note that the loop filter response actually
operates on the frequency spectrum above
(+) and below (-) the carner center frequency, or center of devlallon, for a symmetric FM
or FSK signal. ThiS may be seen In Figure 4

"<')
"!-_-+_-I;;:--

/:
- 2fo

(fo

I"'\.

(to + 'p)

fp)

10

-3d8

210

Figure 4. Bandpass Effect of Loop
Filter
'---------------------------~

b. Variation of the Phase Comparator's Output Voltage vs Phase
Error and Bias Current (Ke)
Figure 3.
---------------------------------------------------~

December 1988

4-267

4

AN182

Signetics

Clock Regenerator
With Crystal-Controlled
Phase-Locked VCO (NE564)
Linear Products

Application Note

60mVp.p for the NE564). The signal limiter
output IS fed to the phase detector, where the
"unknown" Input IS compared to the
"known" VCO frequency of the NE564. The
differenlial error signal that IS generated IS fed
through a DC amplifier and a vOltage-tocurrent converter. The change in the current
generated forces the VCO frequency to vary
In its frequency and/or phase relationship,
such that a 8 of 90° lagging IS obtained (the
actual phase relationship may be somewhat
less than 90° depending upon the KdKo (gain)
product of the NE564 at the operating frequency and bias current). The external filterIng Incorporated at PinS 4 and 5 control the
dynamic frequency response and loop stability critena.

Author: Les Hadley

INTRODUCTION
In order to obtain a local clock signal In
Multiplexed Data Transmission systems, a
phase and frequency coherent method of
signal extraction is reqUIred. A Master-Slave
system using the quartz crystal as the primary
frequency determining element In a phaselock loop VCO IS used to reproduce a phase
coherent clock from an asynchronous Data
Stream.
The NE564, a versatile phase-locked loop
(PLL) operating at frequencies to 50MHz, has
inputs and outputs designed to be TTL compatible. The Signetlcs NE564 is used to
generate the phase-locked, crystal-stabilized
clock reference signal.

typical curves for each of the parameters are
shown for the NE564 in Figures 2 and 3.

THE CLOCK REGENERATOR
CIRCUIT
The basic bUilding blocks of the clock regenerator cirCUit are shown In Figure 4. The PLL
is shown as a frequency multiplier incorporatIng a diVide by "N" In the VCO phase
detector feedback loop. The functions of the
ringing CirCUit and the NE527 high-speed
comparator will be discussed later.
The waveforms of Figure 5 Indicate the waveforms transmitted over a Tl line. The bipolar
signal transmitted has "no" DC components
induced In the transmission line (reference
should be made to the effect of normal mode
and common effects on signal information).
When transmitted over telephone wire pairs,
the resultant signal (at the receive end) will
have been degraded In both waveshape and
slgnal-to-nolse ratios. TYPical attenuation factors for a Tl line are -30d8 per 6000 feet.

The NE564 IS a first order system; therefore,
the use of Single capacitors (at PinS 4 and 5)
Will automatically create a "second-order"
system. An RC senes filter combination Will
cause a lead-lag condition that Will permit
dynamiC selectiVity, along With closed-loop
stability.

Its particular adaptation, for use with a crystal-controlled VCO Instead of the usual RC
control elements, requires a brief review of
the principles of the Phase-Lock Loop design.
The NE564 Phase-Locked Loop IS a fully
contained system, including limiter, phase
detector, VCO, DC amplifiers, DC retriever
and output comparator (reference Figure 1).
For the clock regeneration system to be
discussed, the portions of the NE564 Implemented are the Input limiter, phase detector
and VCO.

In addition, palr-to-pair crosstalk can degrade
slgnal-to-noise ratios. The energy transmitted
In the bipolar system of signal transfer is
centered at 772kHz (generated by the bit
format).

LOOP GAIN FUNCTIONS
The phase detector conversion gain (Kd) and
the VCO conversion gain (Ko) determine, in
large part, the lock range, capture range and
lineanty charactenstlcs of the NE564. These
deVice parameters are both dependent upon
bias current and operating frequency. Some

The signal limiter amplifies low level Inputs
(until saturation is reached, which IS tYPically

........,..

LOW . . . .

FLTEII

+Vcc

At the receiving end the bipolar signal information IS converted to a unipolar pulse train
after being amplified, filtered and fed through
an automatic level control circuit. Some types

--------------------"""'"----------,
,.

I

I

I
I
I
I

I
I

...-

,

OUT

I

I
II

L

JI
---------0-=::;-----------1-------------------12

13

•

......

SET

-

CANCmlR

-

Figure

December 1988

4-268
Rev. 1

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

AN182

VD - PHASE COMPARATOR'S

OUTPUT VOLTAGE IN raY

...
...

...-.
..

....,.
........

-200

-400

.....

-Figure 2. Variation of the Phase Comparator's Output Voltage vs Phase Error and Bias Current

December 1988

4-269

Application Note

Signetics Linear Products

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

AN182

veo FREQUENCY

Of_

-400

800
Vo IN MY

Figure 3. VCO Output Frequency as a Function of Input Voltage and Bias Current

of PCM systems use the rectified and filtered
DC (average) to control the phase of the
regenerator clock; however, In newer sys·
tems, bipolar signals are preprocessed (or
preconditioned) by terminal common eqUip,
ment resulting in unipolar information.

CRT

DATA

T1 Data Transmission
The bipolar signal, as transmitted on a T1
line, appears below with the original binary,
converted Unipolar and clock waveform (reference Figure 5).
The bipolar signal, when transmitted over
standard wire pairs, will be degraded both in
wave shape and signal-to-noise by the time it
reaches the signal repeater. This is due to the
attenuation factor of the cable which is nearly
-30dB for 6000 ft. In addition, pair to pair
crosstalk degrades signal·to·noise. The ener·
gy in the transmitted bipolar signal is centered
at 772kHz due to the particular bit format.
Bipolar signals have no DC offset.
At each receiving station the bipolar signal is
amplified, filtered and fed through an automatic level control circuit. A full wave rectified
signal is then sent to the clock regeneration
circuit. This is essentially the format followed
by some of the original T1 repeater equipment. The clock regeneration circuit described here could be adapted to this system.
December 1988

..............,
"Ul""

Figure 4

THE T1 SPECTRUM
The bipolar signal IS similar to NRZ data in
that it does not contain carrier information. In
order to give the PLL coherent frequency
Information sufficient to obtain" capture" and
lock, carner components must be obtained
from the data stream. The time duration of
the frequency Information fed to the PLL IS
also Important In order to obtain accurate and
stable information to update the PLL. In order
to begin the extraction of frequency information, the positive-going portions of the bipolar
data signals are used to drive a class "C"

4-270

transistor tank circuit (reference Figure 4)
which is sharply tuned to the basic clock
frequency (1.544MHz). Each positive half cycle of data then starts a wave train of
coherent information which IS phase synchronous with each succeeding positive data bit.
When the LC tank is optimally tuned, relatively extended periods without data bits can be
tolerated with minimal loss of frequency and
phase information. The combination of good
short-term frequency stability of the high "0"
LC tank, coupled with the long-term stability
of the crystal-controlled VCO, is the founda-

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

AN182

particular worst case condition IS shown In
Figure 7 below
BINARY CODe

Solving equation 1 for the relative amplitude
of the 1.544MHz spectral component with the
pulse spacing shown,

.... DUTy
CYCLE

161Tb

Sln(...-- )

('6,nb)

.-aLAR

where T

~

2nb, n

, .........

CLOCI(

Ab

~((2)(16)b)

Figure 5

~

16

sln( '3S:bb )
('6rrb)

A 2
32 IT

32b
~
~

I

~,
•
3238na

Figure 6
tlon of the NE564 clock regeneration system
accuracy.
It must be emphasized that data pulse synchronization of the preproceSSing CirCUit must
be frequency coherent with the fundamental
penod of the time base to be extracted. That
IS, If the time penod of the clock IS '1fc ~ T,
where fe IS the clock frequency, then the
spacing between any positive code bit sequence must be n x T (reference Figure 6).
Looking at the spectral analysIs of the relative
energy available to the clock extraction CirCUitry (With a worst-case duty cycle of 1 of 16)
will demonstrate the need for enchanclng the
particular deSired frequency component before applYing the signal to the Phase-Lock
Loop. For fa ~ 1.544MHz, the penod IS
T ~ 647.67ns. The pulse or bit Width IS
323.8ns.
Here the bit duration 323.8ns ~ b. The Founer expansion of the discrete spectrum IS
related by the follOWing equation:

In

~

0,1,2.

(2)

where f  'Vee

...... , .:t:L
..

....

DVM

TC07550$

NOTE:
Check

veo

free-runnmg frequency and output waveshape

Figure 13. Check VCO Free-Running Frequency
and Output Waveshape

S0213

Figure 14

•

SCOPE

Figure 15

Figure 16

5DQnS

l00mV
l00mV

5DDnS

III" I II 'I

I

I
I

,.

,U \
J J\

,., I"

n

f"'I

II/ 1\ I
\

lJ \J \

,,..

!

lJ

Figure 17. Ringing Circuit Response (1 Data Pulse in 16)

I
I

,

"

J

r

"\

I

J U

in r

l J

Figure 18. Ringing Circuit Response (4 Data Pulses in 16)

2DOnS

200mV

5DDnS

n

,...... 's

DATA NttIT

!r

1

Il

COMPARATOR OUTPUT

-U

'v

'v
Figure 19. Ringing Circuit to Square Wave Conversion

J

-I
'-

r .........
... e

~

L

,

1 r rn 1 r r 1 Cl
L ll.J .JL L J
L

December 1988

, ,

h 'n

I I
Jl I
, I

2V

2V

l00mV

DATA (4 .. US)

l II J !L I

QlTA PULSE
(11ft 1e)

NESM

"'3

L

Figure 20. Phase Comparator Signals (in Lock)

4-275

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

,V

:..I

-

200nS

AN182

IV

.. ,.

,

I

r n
J IL

1

DATASfT

200nS

II

J

It

,

r

, ...-.our

Ct.OCK

l

MULTlPl..£ DATA

r
I

,

I

'v

2V

Figure 22. Regenerated Clock Signals

Figure 21. Regenerated Clock Signals

,V

'DOnS

200nS

2V

I

I

I
J

I11....00•.,

L....

L

CLOCK OUT

DATA ..

I

li-

,

I

[I fll[1
I I111

,

1 /I n

I I /I

'r

"I "'"1/

"

[ nIHI

A ..,.FEAEO
vco OUT
6176Wtz)

I I III Il

r

-

..

1

L. ~

!I
J

r

J

DATA .. (AAHDOM)

ClOCK OUT (8l.IFF£RfD)

'v
Figure 25. Regenerated Clock Signal
Relative to Random NRZ Data Signal
NOTES:
1. Recent versions of thiS CircUit no longer reqUIre senes capacitors Cc and
CT See Figure 12

Input levels to the NE564 have been reduced for thiS application to ~
800mVp-p. See Figure 12
Improved operation regarding clock Jitter IS obtained by carefully decoupIIng the divider counter IGs and the PLL's Vee hne ThiS IS accomplished by adding a small senes "A" Into the Vee hne with the bypass
capacitor to ground

References
1. "Founer Analysis" by Hwei P. Hsu. Simon & Schuster Tech
Outlines
2. "Pulse and Digital CirCUits" by Millman and Taub McGraw HIli
3. "Phase lock Techniques" by Floyd M. Gardner Wiley, 1966
December 1988

fI nIII ~lJ e
I I III !t III

VCOOUT
17811H

z

Figure 24. Regenerated Clock Signal
Relative to NE564 VCO Signal

'OOnS

I
I
J

,....-.

'v

Figure 23. Regenerated Clock Signals
Relative to NE564 VCO Signal

'v

I
L

4-276

t'.

NE/SE565

Signetics

Phase-Locked Loop
Product Specification

Linear Products
DESCRIPTION

FEATURES

The NE/SE565 Phase-Locked Loop
(PLL) is a self-contained, adaptable filter
and demodulator for the frequency
range from 0.001 Hz to 500kHz. The
circuit comprises a vOltage-controlled
oscillator of exceptional stability and linearity, a phase comparator, an amplifier
and a low pass filter as shown In the
Block Diagram. The center frequency of
the PLL is determined by the free-running frequency of the veo; this frequency can be adjusted externally With a
resistor or a capaCitor. The low pass
filter, which determines the capture
characteristics of the loop, IS formed by
an internal reSistor and an external capaCitor.

• Highly stable center frequency
(200ppmrC typ.)
• Wide operating voltage range
(± 6V to ± 12V)
• Highly linear demodulated output
(0.2% typ.)
• Center frequency programming
by means of a resistor or
capaCitor, voltage or current
• TTL and DTL compatible square
wave output; loop can be
opened to insert digital
frequency divider
• Highly linear triangle wave output
• Reference output for connection
of comparator in frequency
discriminator
• Bandwidth adjustable from
<±1% to >±60%
• Frequency adjustable over 10 to
1 range with same capaCitor

PIN CONFIGURATIONS
F, N Packages

INPUT

2

INPut

3

VCOOUTPUT 4
PHASE

COMPARATOR s

R~~~~

10 V+

6

EXTERNAL C

DEMODULATED 7

8 EXTERNAL R

OUTPUT

OUTPUT

FOR yeo

'--_ _.......

FOR yeo

10PYIEW

D Package'
INPUT

1

VCOOUTPUT
PHASE
COMPARATOR
VCOINPUT

4

11

v+
~~1E:~~l c

5

10

~E:~tLR

Ne

•

12

REFERENce
OUTPUT

DEMODULATED

OUTPUT

TOPYIEW
NOTE:

1 SO and non-standard pin out

APPLICATIONS
• Frequency shift keying

BLOCK DIAGRAM

C2

INPUT

r--~~:;"~~:...jk-.L<> DEMOD

L __J-'---j;ti-O REF

July 8, 1988

4-277

OUTPUT

OUTPUT

•
•
•
•
•
•
•
•
•

Modems
Telemetry receivers
Tone decoders
SCA receivers
Wide-band FM discriminators
Data synchronizers
Tracking filters
Signal restoration
Frequency multiplication &
division

853-0909 93798

•

Signetics Linear Products

Product Specification

Phase-locked loop

NEjSE565

EQUIVALENT SCHEMATIC
,-----------------------------------------------------------------

1oT

FREQUENCY SETTING RESISTOR
V+
u----n-------------- n -----

r-----"+--...,R1

f[

1____ tf.- __--=~
Cl FREQUENCY SETTING veo
PHASE
CAPACITOR
OUTPUT COMPARATOR

v-

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to

14-Pln Plastic SO
14-Pln Cerdlp
14-Pln Plastic DIP

ORDER CODE
NE565D

+ 70'C
+ 70'C

NE565F

+ 70'C

NE565N

14-Pln Cerdlp

-55'C to + 125'C

SE565F

14-Pln Plastic DIP

-55'C to + 125'C

SE565N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

TA

= 25'C,

PARAMETER

unless otherwise specified
RATING

UNIT

V+

Maximum operating voltage

26

V

VIN

Input voltage

3

Vp_p

TSTG

Storage temperature range

-65 to + 150

'C

Operating ambient temperature
range
NE565
SE565

o to +70
-55 to + 125

'C
'C

300

mW

TA

Po

July 8, 1988

Power dissipation

4-278

Signetics Linear Products

Product Specification

NEjSE565

Phase-Locked Loop

DC AND AC ELECTRICAL CHARACTERISTICS

T A = 25'C, Vcc = ± 6V, unless otherwise specified.

NE565

SE565
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

Min

±12

±6

Typ

Max

±12

V

8

12.5

mA

Supply requirements
Vcc

Supply voltage

Icc

Supply current

±6
8

12.5

Input characteristics
Input impedance 1
Input level required for
tracking

7
fa = 50kHz, ± 10%
frequency deviation

5

10

10

10

kn

10

mVRMS

VCO characteristics
fc

Center frequency
Maximum value
distribution 2

Dnft with temperature
Drift with supply voltage

Distribution taken about
fa = 50kHz, Rl = 5.0kn,
C 1 = 1200pF

Duty cycle
tR

500

-10

0

fa = 50kHz
fa = 50kHz, Vcc = ± 6 to ± 7V

Tnangle wave
output voltage level
linearity
Square wave
logical "1" output voltage
logical "0" output voltage

300

= 50kHz
= 50kHz
fa = 50kHz

fo
fa

500
0.1
1.9

2.4
0.2

+4.9

+5.2
-0.2

45

Rise time

tF

Fall time

ISINK

Output current (sink)

ISOURCE

Output current (source)

500
+10

-30

600
0.2

1.0
3

50

55
100

50

200

+30

1.5

%N

3

Vp_p
%

2.4
0.5

+4.9

+5.2
-0.2

+0.2

50

60

40

%
ppml'C

1.9

+0.2

20

0

kHz

V
V
%
ns

20
50

ns

0.6

1

0.6

1

mA

5

10

5

10

mA

4.25

4.5

4.0

4.5

Demodulated output characteristics
VOUT

Output voltage level

Measured at Pin 7

Maximum voltage sWlng3
Output voltage swing
THO

Vas

4.75

± 10% frequency deviation

250

300

200

300

mVp.p

0.2

Output impedance 4

3.6

Offset voltage (V6 - V7)

30

Offset voltage vs temperature
(drift)

50

100

jJ.V/'C

40

40

dB

AM rejection

30

0.75

4-279

0.4

1.5

100

50

%
kn

3.6

Both input terminals (PinS 2 and 3) must receive Identical DC bias. This bias may range from OV to -4V
The external resistance for frequency adjustment (R1) must have a value between 2kil and 20kn.
Output voltage SWings negative as Input frequency increases
Output not buffered.

July 8, 1988

V
Vp.p

Total harmonic distortion

NOTES:
1.
2.
3.
4.

50

2

2

200

mV

•

Product Specification

Signetics Linear Products

NE/SE565

Phase-locked loop

TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current
as a Function of
Supply Voltage

Lock Range
as a Function of
Input Voltage

Veo Conversion Gain
()

20r-----r----~--~----~

R,

= FREQUENCY SETTING

ffi

2.0

::0

V+

Sl0:

RESISTOR

"-

~

1.5

z
Z
z

/v

~

w

0:

"Q

0.5

~

,/

0:

10

14

18

22

26

TOTAL SUPPLY VOLTAGE -

Lock
as a
Gain
(Pins

~

0.5

fit t'l'~

i

....
::>

eo
::>

-1

I t II

II ;';~~c15o
0: "'_

2.0

()

>

~

I"'

~

1.5

1.0

2.0

2.5

..

Z I
z>
::>()

~llJ

r- ~~ ~:~

1.0
0.5

~~
w
z

".

-2

%

()

0.20.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
I.

DESIGN FORMULAS
(See Figure 1)
Free-running frequency of VCO:
12
fo""-- In Hz
4R , C,

V
/

W::O
0:0

0

-1.5

"

L

V

-2.0
-2.5
-75-50-25

./

V

./

z
0:
....
::0

....
::0

0

25

50

75 100 125

TEMPERATURE _ °C

shift its frequency to match that of the input.
Consequently, the linearity of the phase comparator output with frequency is determined
by the voltage-to-frequency transfer function
of the VCO.

TYPICAL APPLICATIONS

FM Demodulation
The 565 Phase-Locked Loop is a general
purpose circuit designed for highly linear FM
demodulation. During lock, the average DC
level of the phase comparator output signal is
directly proportional to the frequency of the
Input signal. As the input frequency shifts, it is
this output signal which causes the VCO to
July 8, 1988

-2

::0

V'

'\

1\ I

1\ II

\ I

r-

r-

....,

I

A typical connection diagram is shown in
Figure 1. The VCO free-running frequency is
given approximately by
1.2
f O ""4R 1C1

V -::-=-

....

-1

0

Because of its unique and highly linear VCO,
the 565 PLL can lock to and track an input
signal over a very wide bandwidth (typically
± 60%) with very high linearity (typically, within 0.5%).

8fO

=±-

.
.
.
..
z
0:
....
::0
>

in Hz
Vee
1 _ /2irtl
Capture range: fe""± 21T
T

Lock range: fL

0.6 0.8 1.0 1.2 1.4 1.6 1.8
NORMALIZED LOCK RANGE

veo Output
Waveform
>
I

1.5

"-w -0.5
zO:
-"- -1.0

RELATIVE FREE·RUNNING FREQUENCY -

10

3.0

2.5
0

=6V

>

8

....
::0

Change in Free-Running
VCO Frequency as a
Function of Temperature
v+ =6V

~

.
v,o-v,
OP'''''''

2

I

/

V

I

/

VOLTAGE BETWEEN PIN 7 AND PIN 10 -

V

Range
Function of
Setting Resistance
6 -7)

v-

100

E

1.0

~

...-...-"""M"-'--"--'-"""-"""""

>

::>

~

1000

= +6V

v- = -6V
...!

and should be adjusted to be at the center of
the input signal frequency range. C, can be
any value, but R, should be within the range
of 2000 to 20,000n with an optimum value on
the order of 4000n. The source can be direct
coupled if the DC resistances seen from Pins
2 and 3 are equal and there is no DC voltage
difference between the pins. A short between

4-280

0

.....
-2
V+=V-=6V

r-

-

. ,.....

Pins 4 and 5 connects the VCO to the phase
comparator. Pin 6 provides a DC reference
voltage that is close to the DC potential of the
demodulated output (Pin 7). Thus, ij a resistance is connected between Pins 6 and 7, the
gain of the output stage can be reduced with
little change in the DC voltage level at the
output. This allows the lock range to be
decreased with little change in the freerunning frequency. In this manner the lock
range can be decreased from ± 60% of fa to
approximately ± 20% of fa (at ± 6V)_
A small capacitor (typically 0.001I'F) should
be connected between Pins 7 and 8 to
eliminate possible oscillation in the control
current source.
A single-pole loop filter is formed by the
capacitor C2, connected between Pin 7 and
the positive supply, and an internal resistance
of approximately 3600!2.

Product Specification

Signetics Linear Products

NEjSE565

Phase-locked loop

, - -......-

,--~--~

......- - - 0 - 6V

__--......----~--~------~·+6V

c,

J'lJ

DEMODULATED
OUTPUT
REFERENCE
OUTPUT

FSK

0.1

IHPuro--!
30K

'--......----<> -6V

L-__

Figure 1

Frequency Shift Keying (FSK)
FSK refers to data transmission by means of
a carrier which is shifted between two preset
frequencies. This frequency shift is usually
accomplished by driving a VCO with the
binary data signal so that the two resulting
frequencies correspond to the "0" to "1"
states (commonly called space and mark) of
the binary data signal.
A simple scheme using the 565 to receive
FSK signals of 1070Hz and 1270Hz is shown
in Figure 2. As the signal appears at the input,
the loop locks to the input frequency and
tracks it between the two frequencies with a
corresponding DC shift at the output.
The loop filter capacitor C2 is chosen smaller
than usual to eliminate overshoot on the
output pulse, and a three-stage RC ladder
filter is used to remove the carrier component
from the output. The band edge of the ladder
filter is chosen to be approximately hal! way
between the maximum keying rate (In this
case 300 baud or 150Hz) and twice the input
frequency (approximately 2200Hz). The output signal can now be made logic compatible
by connecting a voltage comparator between
the output and Pin 6 of the loop. The freerunning frequency is adjusted with R1 so as to
result in a slightly-positive voltage at the
output with fiN = 1070Hz.

~

______________________

__

~_6V

Figure 2
The input connection is typical for cases
where a DC voltage is present at the source
and therefore a direct connection is not
desirable. Both input terminals are returned to
ground with identical resistors (in this case,
the values are chosen to effect at 600n input
impedance).

Frequency Multiplication
There are two methods by which frequency
multiplication can be achieved using the 565:
1. Locking to a harmonic of the input signal.
2. Inclusion of a digital frequency divider or
counter in the loop between the VCO and
phase comparator.
The first method is the simplest, and can be
achieved by setting the free-running frequency of the VCO to a multiple of the input
frequency. A limitation of this scheme is that
the lock range decreases as successively
higher and weaker harmonics are used for
locking. I! the input frequency is to be constant with little tracking required, the loop can
generally be locked to anyone of the first 5
harmonics. For higher orders of multiplication,
or for cases where a large lock range IS
desired, the second scheme is more desirable. An example of this might be a case
where the input signal varies over a wide
frequency range and a large multiple of the
input frequency is required.
A block diagram of the second scheme is
shown in Figure 3. Here the loop is broken
between the VCO and the phase comparator,
and a frequency divider is inserted. The

Figure 3
Figure 4

July 8, 1988

~

4-281

fundamental of the divided VCO frequency is
locked to the input frequency in this case, so
that the VCO is actually running at a multiple
of the input frequency. The amount of multiplication is determined by the frequency divider. A typical connection scheme is shown in
Figure 4. To set up the circuit, the frequency
limits of the input signal must be determined.
The free-running frequency of the VCO is
then adjusted by means of R1 and C1 (as
discussed under FM demodulation) so that
the output frequency of the divider is midway
between the input frequency limits. The filter
capacitor, C2, should be large enough to
eliminate variations in the demodulated output voltage (at Pin 7), in order to stabilize the
VCO frequency. The output can now be taken
as the VCO squarewave output, and its fundamental will be the desired multiple of the
input frequency (fiN) as long as the loop is in
lock.

SeA (Background Music)
Decoder
Some FM stations are authorized by the FCC
to broadcast uninterrupted background music
for commercial use. To do this, a frequency
modulated subcarner of 67kHz is used. The
frequency is chosen so as not to interfere
with the normal stereo or monaural program;
In addition, the level of the subcarrier is only
10% of the amplitude of the combined signal.
The SCA signal can be filtered out and
demodulated with the NE565 Phase-Locked
Loop Without the use of any resonant circuits.
A connection diagram is shown in Figure 5.
This circuit also serves as an example of
operation from a single power supply.
A resistive voltage divider is used to establish
a bias voltage for the input (Pins 2 and 3). The
demodulated (multiplex) FM signal is fed to
the input through a two-stage high-pass filter,
both to effect capacitive coupling and to
attenuate the strong signal of the regular
channel. A total Signal amplitude, between
80mV and 300mV, IS required at the input. Its
source should have an impedance of less
than 10,000n.

•
~

Product Specification

Signetics Linear Products

NE/SE565

Phase-Locked Loop

The Phase-Locked Loop is tuned to 67kHz
with a 5000.ll potentiometer; only approxImate tUning is required, since the loop will
seek the signal.
The demodulated output (Pm 7) passes
through a three-stage low pass filter to proVide de-emphasis and attenuate the hlghfrequency nOise which often accompanies
SeA transmission. Note that no capacitor IS
provided directly at Pm 7, thus, the cirCUit IS
operating as a first-order loop. The demodulated output signal is In the order of 50mV and
the frequency response extends to 7kHz

. 12V

r-------~;-----~~-------1-----T-----r-o-24V

10.

.047

18.

DEM SIOpF SIOpF

1.

FM<>-I

47.

Figure 5

July 8, 1988

4-282

1.

1k

018

BACKGROUND
MUSIC (SCA)

Signetics

AN183
Circuit Description of the
NE565 Pll
Application Note

Linear Products

CIRCUIT DESCRIPTION OF THE
NE565 PLL
The 565 is a general purpose PLL designed
to operate at frequencies below 1MHz. The
loop IS broken between the VCO and phase
comparator to allow the insertion of a counter
for frequency multiplication applications. With
the 565. it IS also possible to break the loop
between the output of the phase comparator
and the control terminal of the VCO to allow
additional stages of gain or filtering. ThiS IS
described later in this section.
The VCO IS made up of a precIsion current
source and a non-saturating Schmitt trigger.
In operation. the current source alternately
charges and discharges an external timing
capacitor between two SWitching levels of the
Schmitt trigger. which in turn controls the
direction of current generated by the current
source.

A Simplified diagram of the VCO is shown

In

Figure 1. 11 is the charging current created by
the application of the control voltage Ve. In
the Inllial state. 03 IS off and the current 11
charges capacitor C1 through the diode D2.
When the voltage on C1 reaches the upper
triggering threshold. the Schmitt trigger
changes state and activates the transistor 03.
This prOVides a current Sink and essentially
grounds the emitters of 0 1 and 02. The
charging current 11 now flows through D1. 01
and 0 3 to ground. Since the base-emitter
voltage of 02 IS the same as that of 01. an
equal current flows through 02. ThiS discharges the capacitor C1 until the lower
triggering threshold IS reached. at which pOint
the cycle repeats itself. Because the capacitor C1 is charged and discharged With the
constant current 11. the VCO produces a
triangle waveform as well as the square wave
output of the Schmitt trigger.
The complete circuit for the 565 IS shown in
Figure 2. Transistors 01 - 07 and diodes
D1 - D3 form the precision current source.
The base of 01 IS the control voltage input to
the VCO. This voltage is transferred to Pin 8
where it IS applied across the ex1ernal resistor
R1. ThiS develops a current through R1 which
enters Pin 8 and becomes the charging
current for the VCO. With the exception of the
negligible 01 base current. all the current that
enters Pin 8 appears at the anodes of diodes
D2 and D3. When 08 (controlled by the
Schmitt trigger) is on. D3 is reverse-biased
and all the current flows through D2 to the
duplicating current source 05 - 0 7 • R2 - R3
December 1988

and appears as the capacitor discharge current at the collector of 0 5 . When 0 8 is off. the
duplicating current source 0 5 - 07. R2 - R3
floats and the charging current passes
through D3 to charge C1.

The SWitching stage 018. 019. 022 and 023 is
driven from the Schmitt trigger via Pin 5 and
D11 . Diodes D12 and D13 limit the phase
comparator output. and differential amplifier
026 and 027 provides Increased loop gain.

The Schmitt trigger (0 11 . 0 12 ) IS driven from
the capacitor triangle waveform by the emitter-follower Og. Diodes D6 - Dg prevent saturation of 0 11 and 012. enhanCing the switchIng speed. The Schmitt trigger output is
buffered by emitter-follower 013 and is
brought out to Pin 4. and IS also connected
back to the current source by the differential
amplifier (0 14 - 016).

The loop low pass filter IS formed with an
external capacitor (connected to Pin 7) and
the collector resistance R24 (typically 3.6kn).
The voltage on Pin 7 becomes the error
voltage which IS then connected back to the
control voltage terminal of the VCO (base of
0 1 ). Pin 6 is connected to a tap on the bias
resistor string and provides a reference voltage which IS nominally equal to the output
voltage on Pin 7. ThiS allows differential
stages to be both biased and driven by
connecting them to Pins 6 and 7.

When operated from dual symmetrical
supplies. the square wave on Pin 4 Will sWing
between a low level of slightly (0.2V) below
ground to a high level of one diode voltage
drop (0.7V) below the positive supply. The
triangle waveform on Pin 9 IS approximately
centered between the positive and negative
supplies and has an amplitude of 2V With
supply voltages of ± 5V. The amplitude of the
triangle waveform IS directly proportional to
the supply voltages.
The phase comparator is again of the doublybalanced modulator type. Transistors 020
and 024 form the signal Input stage. and must
be biased externally. If dual symmetrical
supplies are used. It is Simplest to bias 0 20
and 024 through ex1ernal resistors to ground.

The free-running center frequency of the 565
is adjusted by means of R1 and C1 and is
given approximately by
(1 )

When the phase comparator is In the limiting
mode (V,N;;' 200mV p_p). the lock range can
be calculated from the expression:
(2)

r-----------.------o.v

Figure 1. Simplified Diagram of NE565

4-283

veo

II

Signetics Linear Products

Application Note

Circuit Description of the NE565 PLL

AN183

R20r23tR25
2~Q20

I-"-,-+-+--t-JI -~---'
5

R21

I

~-----t------+----1----~~t----t'----~a~2~12f----~~~a~25~a28
~ R15

Rg
CURRENT SOURCE

vco

SCHMITT TRIGGER

tR26

~ R22

PHASE COMPARATOR

~ R27
,

01

AMPLIFIER FILTER

Figure 2. Circuit Diagram af 565
where Ko is the veo conversion gain, Kd is
the phase comparator's conversion gain, A is
the amplifier gam, and Od is the maximum
phase error over which the loop can remain In
lock. Specific values for the terms of Equation
2 for the 565 are
1.4

Kd =-Vlrad

(3)

"
A

= 1.4

"
ed = 2'rad
50fo' rad
Ko=----Vee Volt-sec

to each side of the free-running frequency, or
a total lock range of:
(8)

(12)

The capture range, over which the loop can
acquire lock with the Input signal, is given
approximately by:

(4)

(5)

(9)

where

WL

is the one-sided tracking range

(6)

where Vee IS the total supply voltage applied
to the circuil.

(10)

and r is the time constant of the loop filter

The tracking range for the 565 then becomes:

(11)

(7)

December 1988

The lock-in range can be written as:

4-284

to each side of the free-running frequency or
a total capture range of:

fe""~

y3211iO'

"

rVee

(13)

This approxlmabon works well for narrow
capture ranges (fe = Y3fLl but becomes too
large as the limiting case IS approached
(fe = fd.
When It IS desired to operate the 565 out of
ItS limiting mode (VIN < 200mVp.p or
32mVRMS), Kd can be estimated from the
graph In Figure 3 for the specific mput voltage
anticipated. The previous calculations tor the
lock and capture ranges remam valid with the
new value of Kd from the graph being used to
replace the KdA product m Equation 2. In
Figure 3, the DC amplifier gain A has been
included In the Kd value.

Signetics Linear Products

Application Note

AN·183

Circuit Description of the NE565 PLL

--7

11(

lK

"'221

50K

Figure 5. Expanded Lock Range Configuration for the 565

,---.......---..--.---------0."

Av=

!!!'
R,

Figure 6. Increased Loop Gain and Lock Range for the 565

December 1988

4-286

Signetics

AN184
Typical Applications with NE565
Application Note

Linear Products

FSK DEMODULATION
FSK refers to data transmission by means of
a carner which is shifted between two preset
frequencies. This frequency shift is usually
accomplished by driving a VCO with the
binary data signal so that the two resuiling
frequencies correspond to the "0" and" 1"
states (commonly called space and mark) of
the binary data signal

FSK Demodulation with the 565

r----t----~--~~--~~--~~)+5V

C2
O.2p.F
10K

The Input connecllOn IS typical for cases
where a DC voltage IS present at the source
and, therefore, a direct connection IS not
desirable. Both Input terminals are returned to
ground with identical resistors (In this case,
the values are chosen to achieve a 600Q
Input Impedance).
A more sophisticated approach primarily useful for narrow frequency deViations IS shown
In Figure 2. Here, a constant current IS
Injected Into Pin 8 by means of transistor Ql.
This has the effect of decreaSing the lock
range and Increasing the output voltage sensitivity to the Input frequency shift The baSIS
for this scheme IS the fact that the output
voltage (control voltage for the VCO) controls

December 1988

10K

O.02p.F

O.02I'F

10K

FSK
INPUT

A simple scheme uSing the 565 to receive
FSK signals of 1070Hz and 1270Hz IS shown
In Figure 1. As the signal appears at the Input,
the loop locks to the Input frequency and
tracks It between the two frequencies with a
corresponding DC shift at the output (Pin 7).
The loop filter capacitor C2 is chosen to set
the proper overshoot on the output and a
three-stage RC ladder filter IS used to remove
the sum frequency components. The band
edge of the ladder filter IS chosen to be
approximately half-way between the maxImum keYing rate (300 baud or bits per second, or 150Hz). The free-running frequency
should be adjusted (with R1) so that the DC
voltage level at the output IS the same as that
at Pin 6 of the loop. The output signal can
now be made logic compatible by connecting
a voltage comparator between the output and
Pin 6.

O.02I'F

+14V

~--~------------------------~---o-sv

Figure 1. FSK Decoder Using the 565

Rb

Ra

3.9KO 8.2KO
D4.

FSK

._~~--~;;r------1~l-1-~10~K~0-J~I~OK~O~+-~

INPUT~f-

OUTPUT

6000

-sv
Figure 2_ FSK Decoder With Expanded 565
Output Voltage Range
only the current through Rl, while the current
through Ql remains constant. Thus, if most of
the capacitor charging current IS due to Ql,
the current variation due to Rl Will be a small
percentage of the total charging current and,
consequently, the total frequency deviation of
the VCO Will be limited to a small percentage

4-287

of the center frequency. A 0.25fJF loop filter
capacitor gives approximately 30% overshoot
on the output pulse, as seen In the accompanying photographs. Figure 3 shows the output
of the fJA710 comparator and the output of
the 565 phas'1-locked loop.

•

Application Note

Signetics Linear Products

AN184

Typical Applications with NE565

LOGIC bUTPU) 15V/CM! _

l

I

I ~ "\

~~

J

I

I
(' h

I

~

V .J

"\
\

roo

PLL rTPur MHR IlL TER

mVr M)

a. 100 Baud

LOGI

I

oUTPl15v/cL -

I

II

)r"1'\
/
y
"
~

~~

'\. f.....- /
PLL OUTPUT AFTER FiL TER
120OmtCM)

I

0P06500S

b. 200 Baud

rl

l
J
/

rl

V""\

)

'\..V

r,

r-

LOGL OUT.'uT 'SVlIM)

J

,"\
J

"-V "-VI
PLL OUTPUT TTER F)L TER
1200mltM)

c. 300 Baud
Figure 3

December 1988

4-288

Application Note

Signetics Linear Products

AN184

Typical Applications with NE565

seA
+10 VOLTS
... 24 VOLTS

18K

10K

5K

001

1K

1K

1K

10 7

47K

BACKGROUND
MUSIC (SCA)

NE565

47K

47K

47K

Figure 4. SeA Decoder

December 1988

4-289

Demodulator Using the

565
This application Involves demodulation of a
frequency·modulated subcarner of the main
channel. A popular example here IS the use of
the PLL to recover the SCA (SubSidiary Cam·
er AuthOrization or storecast musIc) Signal
from the combined Signal of many commer·
clal FM broadcast stations. The SCA Signal IS
a 67kHz frequency·modulated subcarner
which puts It above the frequency spectrum
of the normal stereo or monaural FM program
material. By connecting the CIrCUit of Figure 4
to a pOint between the FM discriminator and
the de·emphasls filter of a commerCial band
(home) FM receiver and tuning the receiver to
a station which broadcasts an SCA Signal,
one can obtain hours of commercial· free
background musIc.

•

NEjSE566

Signetics

Function Generator
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE/SE566 Function Generator is a
voltage-controlled oscillator of exceptional linearity with buffered square wave
and triangle wave outputs. The frequency of oscillation is determined by an
external resistor and capacitor and the
voltage applied to the control terminal.
The oscillator can be programmed over
a ten-to-one frequency range by proper
selection of an external resistance and
modulated over a ten-to-one range by
the control voltage, with exceptional linearity.

• Wide range of operating voltage
(up to 24V; single or dual)
• High linearity of modulation
• Highly stable center frequency
(200ppmrC typical)
• Highly linear triangle wave output
• Frequency programming by
means of a resistor or capacitor,
voltage or current
• Frequency adjustable over 10-to1 range with same capacitor

PIN CONFIGURATIONS

APPLICATIONS
•
•
•
•
•
•

D, N Packages

GROUNOO'VO
Ne

TRIANGLE WAVE
OUTPUT

7

C,

6 R
1

4

5

MODULATION
INPUT

TOP VIEW

F Package
Ne ,
GROUND

Tone generators
Frequency shift keying
FM modulators
Clock generators
Signal generators
Function generators

2

SQUARE WAVE
OUTPUT

3

SQUARE WAVE

4

TRIANGLE
WAVE

5

NC'

8

MODULATION
INPUT

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

6-Pin Plastic SO
14-Pin Cerdip
6-Pin Plastic DIP

TEMPERATURE RANGE

o to
o to
o to

ORDER CODE

+ 70·C

NE566D

+ 70·C

NE566F

+ 70·C

NE566N

14-Pln Cerdip

-55·C to + 125·C

SE566F

6-Pin Plastic DIP

-55·C to + 125·C

SE566N

BLOCK DIAGRAM

November 6, 1966

4-290

653-091 0 66366

Product Specification

Signetics Linear Products

NE/SE566

Function Generator

EQUIVALENT SCHEMATIC

,-------------------------

-~

- -----

-- - - -------~

~.~- -~ -~--

--~~----T_----T_~---T_--T_-~-

V'

OK!)
GROUND
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

V+

Maximum operating voltage

26

V

VIN

Input voltage

3

Vp. p

Storage temperature range

-65 to +150

·C

Operating ambient temperature
range
NE566
SE566

o to +70
-55 to +125

·C
·C

300

mW

-~

TSTG

TA

Po

Power dissipation

November 6, 1986

4-291

-----I

Signetics Unear Products

Product Specification

NEjSE566

Function Generator

DC ELECTRICAL CHARACTERISTICS TA=25°C; Vcc=±6V, unless otherwise specified.
SE566
SYMBOL

NE566

PARAMETER

UNIT
Min

Typ

Max

Min

Typ

Max

General
TA

Operating ambient temperature range

-55

125

0

70

Vcc

Operating supply voltage

±6

±12

±6

±12

V

Icc

Operating supply current

12.5

mA

7

12.5

7

°C

veo'
fMAX

1

1

MHz

Frequency dnft With temperature

500

600

ppmfOC

Frequency dIift With supply voltage

0.1

Control terminal input impedance2

1

Maximum operating frequency

FM distortion (± 10% deviation)

0.2

Maximum sweep rate
Sweep range

1

0.2

2

1
0.75

0.4

1

1

10:1

10:1

%IV
Mn

1.5

%

MHz

Output

IR
tF

Triangle wave output
impedance
voltage
linearity
Square wave input
impedance
voltage
duty Cycle
Rise time
Fall Time

1.9

5
45

50
2.4
0.2
50
5.4
50
20
50

1.9

55

NOTES:
1. The external resostance for frequency adjustment (R,) must have a value between 2k!l and 20kU
2. The bIBS voltage (Vel applied to the control tennlnal (Pon 5) should be ,n the range lJ<4V+ '" Vc '" V+.

November 6, 1986

4-292

5
40

50
2.4
0.5

n
Vp.p
%

50
5.4
50
20
50

n
Vp.p
%
ns
ns

60

Product Specification

Signetics linear Products

Function Generator

NE/SE566

TYPICAL PERFORMANCE CHARACTERISTICS

25

>u
z

UJ

0

UJ

15

§
:::;

«

::;
cr:
0

z

~

V

:0

I:

100

V+ ",,12 VOLTS

20

10

V
10

iiicr:
20

25

CONTROL VOLTAGE
(BETWEEN PIN 8 AND PIN 5) -

..e
...zI

w

17.5
15.0

l-l~~
~~

..

~

0:
0:

::> 12.5

..... V
u
>-

::>

en

10.0

7.5

/

o1

30
VOLTS

..." 1/

~
w
u

':";7

1.0

05

V

\

0.1

[\,

SUPPLY VOLTAGE -

22

0.01

25

OPERATING INSTRUCTIONS

14V+ 

12

,

I

10

t-j-

t-t-

Z

ii:

........

'\

::>

I
103

!/1\

1

1\

102

'"'- k

0 +25+50+75+100+125

0

!

/TVPICAL

.[)Y
V

...ii:::>
...::>

\

10

V

The NE/SE566 Function Generator IS a general purpose voltage-controlled oscillator designed for highly linear freauency modulation.
The circUit provides simultaneous square
wave and tnangle wave outputs at frequenCies up to 1MHz. A typical connecllOn diagram IS shown In Figure 1. The control
terminal (Pin 5) must be biased externally with
a voltage (Vel In the range

-05
-10

1,/

'/

VCO Output Waveforms

!

"-

~ 0001

19

'': t\\\ r:--

~

~

16

1

1/

TEMPERATURE _ (OC)

V+=12VOLTS:
Vc = 10.5 VOLTS
R1=4K

0.0001
13

Vc= 10 VOLTS

w

10

[\,

Z

o~

1

v + = 12 VOL T5

~

'!:

,

+05

Frequency as a Function
of Capacitance (C1)

~

1/

+20
+ 15

NORMALIZED FREQUENCY

...

V
10

02

10

Rr 4kO

:0

,

Power Supply Current as a
Function of Supply Voltage
20.0

~

""I""

-

;0

,//

+25

= 12 VOLTS
10 VOLTS

u + 10

10

U
Z

05

05

v+
vc

50

20

iw

1/

Change in Frequency as a
Function of Temperature

Normalized Frequency as a
Function of Resistance (R 1)

Normalized Frequency as a
Function of Control Voltage

104

105

"

i
1

0

106

FREQUENCY - hz

modulating signal IS then AC coupled with the
capacitor C2. The modulating signal can be
direct coupled as well, If the appropriate DC
bias voltage IS applied to the control terminal
The frequency IS given approximately by
fo

=

2[(V + ) - (Vell

R, C,V+

and R, should be In the range 2kn
R, < 20kn

<

A small capacitor (typically 0 001 /IF) should
be connected between Pins 5 and 6 to
eliminate possible oscillation In the control
current source

4-293

If the VCO IS to be used to dnve standard
logiC circUitry, It may be deSirable to use a
dual supply as shown In Figure 2 In this case
the square wave output has the proper DC
levels for logiC circuitry. RTL can be dnven
directly from Pin 3. For DTL or TTL gates,
which require a current sink of more than
1mA, It IS usually necessary to connect a 5kn
resistor between Pin 3 and negative supply.
This Increases the current sinking capability
to 2mA. The third type of Interface shown
uses a saturated transistor between the 566
and the logiC circUitry. This scheme IS used
pnmanly for TTL circuitry which reqUires a
fast fall time « 50ns) and a large current
Sinking capability

•

Signetics Unear Products

Product Specification

NE/SE566

Function Generator

~--~--r----oV·

+8 VOLTS
15K

10K

figure 1

November 6, 1986

Figure 2

4-294

Signetics

AN185
Circuit Description of the
NE566
Application Note

Linear Products

CIRCUIT DESCRIPTION OF THE
566 PLL
The 566 IS the voltage-controlled oscillator
portion of the 565. The basIc die IS the same
as that of the 565; modified metallzation IS
used to bring out only the veo. The 566

circuit diagram is shown In Figure 1. TranSIStor 0,8 provides a buffered tnangle waveform
output. (The tnangle waveform IS available at
capacitor e, also, but any current drawn from
Pin 7 will alter the duty cycle and frequency.)
The square wave output IS available from 0,9

by Pin 4 The cirCUit will operate at frequencies up to 1 MHz and may be programmed by
the voltage applied on the control terminal
(Pin 5), by Injecting current Into Pin 6, or by
changing the value of the external resistor
and capacitor (R, and e,).

•
+-..I----+-.t'

0"

R"

JlJ

R.

CURRENT SOURCE

veo

SCHMITT TRIGGER

Figure 1. Circuit Diagram of the NE566

December 1988

4-295

R"

R'6

Signetics

AN186
Waveform Generators With the
NE566
Application Note

Linear Products

WAVEFORM GENERATORS

Ramp Generators

The oscillator portion of many of the PLLs
can be used as a precision, voltage-ccntrollable waveform generator. Specifically, the 566
Function Generator contains the oscillator of
the 565 PLL. Most of the applications which
follow are designs using the 566. Many of
these designs can be modified slightly to
utilize the oscillator section of the 564 if
higher frequency performance IS desired.

Figure t shows how the 566 can be wired as
a positive or negative ramp generator. In the
positive ramp generator, the external transistor driven by the Pin 3 output rapidly discharges C1 at the end of the charging period
so that charging can resume instantaneously.
The PNP transistor of the negative ramp
generator likewise rapidly charges the timing
capacitor C1 at the end of the discharge
period. Because the circuits are reset so

quickly, the temperature stability of the ramp
generator is excellent. The period
t
Tis2fo
where fo is the 566 free-running frequency in
normal operation. Therefore,
T =

~ = _R.,..T<::.......;1_VCC""210

(1)

5(Vcc - Vel

'Vee

,.K

~

.....-!---hl-+--+-<>~
101<

,.K

/\/'v

4-~---r-oll1f1Jlf""

SAWTOOTH

101<

a. Negative Ramp

a. Positive sawtooth

.Vee

..K

~SAWTOOTH

101<

b. Positive Ramp
Figure t. Ramp Generators
December t 988

b. Negative sawtooth
Figure 2. sawtooth and Pulss Generators

4-296

Signetics Unear Products

Application Note

Waveform Generators With the NE566

AN186

where Vc is the bias voltage at Pin 5 and RT
IS the total resistance between Pin 6 and Vce.
Note that a short pulse is available at Pin 3.
(Placing collector resistance in series with the
external transistor collector will lengthen the
pulse.)

stability. The charge and discharge times may
be estimated by using the formula

Sawtooth and Pulse Generator

where RT is the combined resistance between Pin 6 and Vce for the interval conSidered.

Figure 2 shows how the Pin 3 output of the
566 can be used to provide different charge
and discharge currents for C, so that a
sawtooth output is available at Pin 4 and a
pulse at Pin 3. The PNP transistor should be
well saturated to preserve good temperature

T = _R_rC:.....;.'V-,c:..:c,5(Vce- Vc)

(2)

Triangle-to-Slne Converters
Conversion of triangle wave shapes to sinusoids is usually accomplished by diode-resistor shaping networks, which accurately reconstruct the sine wave segment by segment.
Two simpler and less costly methods may be

used to shape the triangle waveform of the
566 into a sinusoid with less than 2% distortion.
In Figure 3, the non-linear losoVos transfer
characteristic of a P-channel junction FET is
used to shape the triangle waveform.
The amplitude of the triangle waveform is
critical and must be carefully adjusted to
achieve a low distortion sinUSOidal output.
Naturally, where additional waveform accuracy is needed, the diode-reSistor shaping
scheme can be apphed to the 566 With
excellent results since it has very good output
amplitude stability when operated from a
regulated supply.

+12V

R,

,.51(

5K

IIIIUAlU!

Wolve:
0UlI'UT

JL

TRIMGU
WAVE
OUll'UT

A.N' -::

-'2V

Figure 3. Trlangle-to·Slne Converters

"2V

Ii"

R,

Vc
101<

"2V

"2V

I

GiRC TONE
BURST FOLLOWING

seR
12V

••

82K

OPTIONAL ":"
-::
REGULATED
CAPACITOR
CHARGING CIRCUIT

1"' ,

..

TONE FREO

l1li

1
APPLICATION OF POWER
3 R,e,

~c,

":,,50":,,

Figure 4. Single-Burat Tone Generator
December 1988

4-297

•

Signetics Linear Products

Application Note

Waveform Generators With the NE566

AN186

.Vee
CENTER . - - -....- - 4

+Vcc

FREQ

ADJUST

CENTER
fREQ

MODULATION

ADJUST

FREQUENCY

ADJUST

15K
10K

I ~~Krl

10K

R

LOW-PASS FILTER OR

c,

_

_

DEVIATION

-

-

ADJUST

~

LOW-PASS FIL TeR OR SINE CONVERTER
MAY BE INSERTED HERE IF SINUSOIDAL
MODULATION IS REQUIRED

SINE CONVERTER MAY
BE INSERTED HERE

IF SINUSOIDAL MODULATION
IS ReQUIRED

a. Small Frequency Deviations to ± 20%

b. Large Frequency Deviations to ± 100%

Figure 5. Frequency-Modulated Generators

Single-Tone Burst Generator
Figure 4 is a tone burst generator which
supplies a tone for one-half second after the
power supply is activated; Its Intended use is
a communications network alert signal. Cessation of the tone is accomplished at the
SCR, which shunts the timing capacitor C j
charge current when activated. The SCR IS
gated on when C2 charges up to the gate
voltage which occurs in 0.5 seconds. Since
only 70tJA are available for triggering, the SC
must be sensitive enough to trigger at this
level. The triggering current can be increased,

December 1988

of course, by reducing R2 (and Increasing C2
to keep the same time constant). If the tone
duration must be constant under widely varyIng supply voltage condlllOns, the optional
Zener diode regulator circuit can be added,
along with the new value for R2, R2' = 82ki1.
If the SCR is replaced by an NPN transistor,
the tone can be switched on and off at will at
the transistor base terminal.

Low Frequency FM Generators
Figure 5 shows FM generators for low frequency (less than 0.5MHz center frequency)
applications. Each uses a 566 function gener-

4-298

ator as a modulation generator and a second
566 as the carrier generator.
Capacitor Cj selects the modulation frequency adjustment range and C j ' selects the
center frequency. Capacitor C2 is a coupling
capacitor which only needs to be large
enough to avoid distorting the modulating
waveform.
If a frequency sweep In only one direction IS
required, the 566 ramp generators given in
thiS section may be used to drive the carrier
generator.

Signetics

NE/SE567
Tone DecoderjPhase-Locked
Loop
Product Specification

Linear Products

DESCRIPTION
The NE/SE567 tone and frequency decoder is a highly stable phase-locked
loop with synchronous AM lock detection and power output circuitry. Its primary function is to drive a load whenever a
sustained frequency within its detection
band is present at the self-biased input.
The bandwidth center frequency and
output delay are independently determined by means of four external components.

FEATURES
• Wide frequency range (.01Hz to
500kHz)
• High stability of center frequency

• Frequency adjustment over a
20-to-1 range with an external
resistor
• Military processing available

PIN CONFIGURATIONS
FE, D, N Packages

~'!~~~:~~T~~08
2.

7

GROUND

INPUT

3

6

TIMING
ELEMENTS R 1

SUPPLY
VOLTAGE +Y

4

5

CAPACITOR C2

APPLICATIONS
• Touch-Tone@ decoding
• Carrier current remote controls
• Ultrasonic controls (remote TV,
etc.)
• Communications paging
• Frequency monitoring and
control
• Wireless intercom

OUTPUT

lOW·PASS FILTER

AND C1
TIMING
ELEMENT A,

TOP VIEW

F Package

• Precision oscillator

• Independently controllable
bandwidth (up to 14%)
• High out-band signal and noise
rejection
• Logic-compatible output with
100mA current sinking capability
• Inherent immunity to false
signals

TOP VIEW

BLOCK DIAGRAM

'''v'\'To---''t-.......

39.

LOOP
LOW

PASS

FILTER

*C2

+v

@Touch-Tone

IS

a registered trademark of AT & T.

October 7. 1987

4-299

853-0124 90824

m
0

0

&

'V

,

c:

CT

!!l

R5

:-'

R.

R'

RIC

R11

R21

<:
:I>

R3.
5k

R'
"k

r
m

cO

....
'"

r

C3~

Z
-I

UJ
0
:I:

m
ii!:

~

(;

.....

0

:J

(J)

0

(J)
()

I!l

<0

::l

~

0

'"c

::l

CD

Q

0

"aa.

(J)

or

Q.

c
0

'""C
';j'

0

en

arB

f
"'1
....

W
a
a

(J)

'V

.J

e'll
I I

1 1

I

R20

11

f ".~
V

R'.

*C2

R36

"::"

I

r-r't'

i

R40

-:-

v

f~ .. ~J

'V

()

",I

R43

":'"

r-

0

":'

I.)

'"

(J)

Q.

5"
0

"0

'1
R26~

R27

zm

...........
CJ)

m

01

-=-

"8.
c

n.
(J)

-0
CD

30

..... g

0-

::l

Signetics Linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-Locked Loop

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to
o to

8-Pin Plastic SO
14-Pln Cerdip
8-Pin Cerdip
8-Pin PlastIc DIP

ORDER CODE

+ 70·C

NE567D

+ 70·C

NE567F

+ 70·C

NE567FE

+70·C

NE567N

8-Pin Plastic SO

-55·C to + 125·C

14-Pin Cerdip

-55·C to + 125·C

SE567F

8-Pin Cerdip

-55·C to + 125·C

SE567FE

8-Pln Plastic DIP

-55·C to + 125·C

SE567N

SE567D

ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA

PARAMETER

Operating temperature
NE567
SE567

RATING

UNIT

o to +70
-55 to +125

·C
·C

10

V

Vee

Operating voltage

V+

Positive voltage at input

0.5 + Vs

V

V-

Negative voltage at input

-10

Voe

VOUT

Output voltage (collector of output
transistor)

15

Voe

TSTG

Storage temperature range

Po

Power dissipation

October 7, 1987

-65 to + 150

·C

300

mW

4-301

Signetics Linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-Locked Loop

--j-----

DC ELECTRICAL CHARACTERISTICS
~~~L.

~--~

-fa

=

25"C, unless otherwise specified.

___ _ _

SE567

NE567
UNIT

Min

Typ

Max

Min

Typ

Max

--

Highest center frequency

C~nter frequency stabllitl

---_.
-55 to +125"C
o to + 70"C

500

500

kHz

35 ± 140
35 ±60

35 ± 140
35 ±60

ppml"C
ppm/"C

---~-

Center frequency dlstrrbutlon

---- _ .
fa

TA

TEST CONDITIONS
.-l_~
~
~

PARAMETER

.5~~equency 1
fa

v + = 50V;

l~~-----~

1

= 100kHz = - - 11 R1C 1

-10

0

+10

0.5

1

14

16

2

4

-10

0

+10

%

0.7

2

%/V

14

18

% of fa

3

6

% of fa

---.~--.

Center frequency shift With
supply voltage

Detection bandwidth
----

fa

1
fa = 100kHz = - - - 1.1 RIC I

-

,-~-

1
fa = 100kHz = - - - 11 R 1CI

12

BW

Largest detection bandWidth

BW

Largest detection bandWidth
skew

BW

Largest detection bandwidth ~
vanatlon With temperature

VI

= 300mVRMS

± 0.1

±0.1

%;oC

BW

Largest detectionbandwldth ~
variation With supply voltage

VI

= 300mVRMS

±2

±2

%IV

10

Input
RIN

Input resistance

VI

Smallest detectable Input
voltage 4

IL

fl

= fa

Largest no-output Input voltage 4

IL = 100mA, fl

= fa

--

15

= 100mA,

10

Greatest simultaneous out-band
slgnal-to-In-band signal ratio
Minimum Input signal to
wide-band nOise raM

Bn

= 140kHz

20

25

20

25

15

15

10

20

25

kn

20

25

mVRMS

15

mVRMS

+6

+6

dB

-6

-6

dB

Output
Fastest on-off cycling rate
"1" output leakage current
"0" output voltage

r--tF
tR

fo/20

fo/20

Vs = 15V

0.01

25

0.01

25

IlA

IL = 30mA
IL = 100mA

0.2
0.6

0.4
1.0

0.2
0.6

0.4
1.0

V
V

Output fall tlme 3

RL

Output rrse tlme3

RL = 50n

= 50n

30

30

ns

150

150

ns

General
Vcc

Supply current qUiescent
Supply current ~ activated
tpD

9.0

4.75

Operating voltage range

RL

= 20kn

QUiescent power diSSipation

6

8

11

13

30

NOTES:

1 Frequency determining resistor R1 should be between 2 and 20kr2
Applicable over 4 75V to 5 75V See graphs for more detailed Information
Pin 8 to Pm 1 feedback RL network selected to eliminate pulsing dUring turn-on and turn-off
4 With R2 = 130k!1 from Pin 1 to V+ See Figure 1

October 7, 1987

4-302

4.75

9.0

V

7

10

rnA

12

15

35

rnA
mW

Product Specification

Signetics Unear Products

NE/SE567

Tone Decoder/Phase-Locked Loop

TYPICAL PERFORMANCE CHARACTERISTICS

I

Largest Detection
Bandwidth vs
Operating Frequency

Bandwidth vs Input
Signal Amplitude
300

1S

i

~

>

E

.
"
..~
I

>

200

:>

!

50

II

~

~

~

I / /
/ /

150
100

~

~

~

~

'1,

5>

...0

o~

..
%

/ I

4

6

8

I/ :;
10

12

% OF

10'

~~

i
0

....
...
"
z

~
N

;s

10'

:''"S

10'
0.1

1
10
100
CENTER FREQUENCY - kHz

o

1000

I
I:

f"'- i'-- "'i'-- "'- -c,
-c,

.so
_.

14 16

'0

~

0

/ II ~ ~ ~ $
f/; ~ ~~~~~~
BANDWIDTH -

:--.,.

10

I:
I'1

~

~
N
;s

'\

t'

~ .!'

I

10'

..!'
250

I

Detection Bandwidth as
a Function of C2 and C3

2

4
6
8 10 12
BANDWIDTH - % OF

'0

14

OP04300$

OPO.t28OS

Greatest Number of Cycles
Before Output

Typical Supply Current vs
Supply Voltage

..

E

..

25

I

z

a:
a:

'"

<>

.
'"
>....

1000

I~

20

k!.io

15
10

//
..-

tI)

---

I III

SOD

LO~D

300

. / "ON" CURRENT

YI
./

16

~

""-['\,

100
50

QUIESCE~I

CURRENT

30

I I

..
z

BANOWIDTH LIMITED BY

tI)

<>
><>

>
I

w

(MINIMUM C2)

/

'"

~'IMiTEr "IY
10

..'".
'"
>

!L BANDWIDTH

10
10

"!:i0

I III

'\.

SUPPLY VOLTAGE - V

Ii:

EXTERNAL RESISTOR

1'-

50

0

100

Typical Output Voltage vs
Temperature
1.0
0.9

I

O.B

Il=100mA

0.7
0.6

V

V"

t---..

0.5
0.4
0.3
0.2

Il=30mA

V

I

0.1

I

-n

0

-~

BANDWIDTH - 'Yo 01 I.

~

SO

nl00l~

TEMPERATURE - ·C

""''''''
Typical Frequency Drift
With Temperature
(Mean and SO)
1.5

+V=5.75 VOLTS

1.0

..,
-1.0

V;

-7

V-~ -::::::

f-

-25

.,
-0.5

-?

~

~

L.
/

---

~~

0

25

75

·c

125

-1.5
-75

liI -2.5
.l!

(1)

~

+V =7.0 VOLTS (1)
+ V=9.0 VOLTS (2)

~

~

P

I~

.,

t

~
'~ '"

- 5.0

0

\
-7.5

-1.0

TEMPERATURE -

October 7, 1987

0.5

.l!

r~
'f

-1.5
-75

II-

(2)

2.5

1.0

0.5

-0.5

5.0

1.5
+V=4.7SY

liI
.l!

Typical Frequency Drift
With Temperature
(Mean and SO)

Typical Frequency Drift
With Temperature
(Mean and SO)

-25

0

25

75

TEMPERATURE - ·C

4-303

125

-10
-75

I
-25

0

25

TEMPERATURE

75

_·c

125

~

Product Specification

Signetics Linear Products

NE/SE567

Tone Decoder/Phase-Locked Loop

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Center Frequency
Shift With Supply
VoHage Change vs
Operating Frequency

Center Frequency Temperature
Coefficient
(Mean and SO)
100

...z

l-

w
U

ii:
ll;..,

o

~

-200

:Ii
w

...

~

......

8: -100

I

~

f'-

j:!1

:!

.

~

I'

0'.., E
~

1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1

'I .... r-..

I-

.:1t = O°C TO 70G

~IR

e

15.0

/

5.0

5.5

6.0

6.5

I

1/

1
fo""--1.lR1C1
~/VI
BW",,1070V ~ in % of fo.
VI .;; 200mVRMS
Where
VI = Input voltage (VRMS)
C2 = Low-pass filter capacitor (IlF)

PHASE-LOCKED LOOP
TERMINOLOGY CENTER
FREQUENCY (fo)
The free-running frequency of the current
controlled oscillator (CCO) In the absence of
an input signal.

"i
" l00mVrms)

0--1l~~NEL~

5

8-

,

2

tc'*l:f'

C2 " -

Yo

OR RECEIVER

'-;3

8

567

5

•

,

2

~C2.~(

",

C',·c,

c-

mfdl

0

R,-1l2 R,
C

24% Bandwidth Tone Decoder
Dual-Tone Decoder
l00mvlpp}

::~~~~~
SINE INPUT

NOTES
R2"" R1/5
Adjust Al so that

q, = 90° with control midway.

00 to 1800 Phase Shifter
NOTES:
1 ReSistor and capacitor values chosen for deSired frequenCies and bandWidth
2 If Cs IS made large so as to delay turn-on of the top 567, decoding of sequential (f1 '2) tones IS possible

October 7, 1987

4-309

OUTPUT
(lNT01K
OHM MIN
LOAD)

•

Signetics Unear Products

Product Specification

Tone Decoder/Phase-Locked Loop

NE/SE567

TYPICAL APPLICATIONS (Continued)

687
3
":"

687
Z

6

Z

a

5

veo

•

.I1.I1

TERMINAL
1<6'10)

CONNECT PIN 3
TO Z.8V TO
INVERT OUTPUT
RL> lOOO!l

........

Oscillator WHh Quadrature Output

Oscillator With Double Frequency
Output

Preclalon Oscillator With 20na
SwItching

687

+

8

3

6

5

af-

687
5

OUTPUT

1

a

687

10ltn

.n.ru

vco

TERMINAL

I'''''

--

Pulae Generator With 25% Duty Cycle

October 7, 1987

Rl

I
Preclalon Oscillator to Switch 100mA
Loada

4-310

C1

OUTY
CYCLE
ADJUST

........
Pulse Generator

AN187

Signetics

Circuit Description of the
NE567 Tone Decoder
Application Note
Linear Products

CIRCUIT DESCRIPTION OF THE
NE567 TONE DECODER
The NE567 is a PLL designed specifically for
frequency sensing or tone decoding. The
NE567 has a controlled oscillator, a phase
comparator and a second auxiliary or quadrature-phase detector. In addition, however, It
contains a power output stage which IS driven
directly by the quadrature-phase detector output During lock, the quadrature-phase detector drives the output stage on, so the device
functions as a tone decoder or frequency
relay. The tone decoder free-running frequency and bandwidth are specified by the free-

.. .

running frequency and capture range of the
loop portion. Since a tone decoder, by definition, responds to a stable frequency, the lock
or tracking range is relatively unimportant
except as It limits the maximum attainable
capture range. The complete circuit diagram
of the NE567 is shown in Figure 1.
The current-controlled oscillator IS shown In
simplified form in Figure 2. It provides both a
square wave output and a quadrature output
The control current Ie sweeps the oscillator
± 7% of the free-running frequency, which IS
set by external components R1 and C1'

TranSistors Q1 through 06 form a flip-flop
which can sWitch Pin 5 between VBE and + V
-VBE. Thus, the R1C1 network is driven from
a square wave of + V -2VBE peak-to-peak
volts. On the positive portion of the square
wave, C1 is charged through R1 until V1 IS
reached. A comparator circuit driven from C1
at Pin 6 then supplies a pulse which resets
the flip-flop so that Pin 5 switches to VBE and
C1 is discharged until V2 IS reached. A second
comparator then supplies a pulse which sets
the flip-flop, and C1 resumes charging.

4+V

...

RIO

R11

..

R21

+V

Y

:

4.7K ~ C3

+V

...
FIgure 1. CIrcuIt DIagram of NE567

December 1988

4-311

OM

...

---

Signetlcs Linear Products

Application Note

Circuit Description of the NE567 Tone Decoder

The total swing of the capacitor voltage, as
determined by the comparator sensing voltages, is

= K(

+ V - 2VBE)

(1)

Due to the excellent matching of integrated
resistors, the resistor ratio K may be considered constant. Figure 3 shows the Pin 5 and

AN187

Pin 6 voltages during operation. It is obvious
from the proportion that t, + t2 is independent
of the magnitude of + V and dependent only
on the time constant R, C, of the external
components. Moreover, if (V, + V2)/2 = +VI
2, then t, = t2 and the duty cycle is 50%.
Note that the triangular waveform is phaseshifted from the square wave.
A differential stage (022 and 023) amplifies
the triangular wave with respect to (V, + V2)1
2 to provide the quadrature output. (Due to
the exponential distortion of the triangle
wave, the quadrature output is actually
phase-shifted about 80·, but no operating

compromises result from this slight deviation
from true quadrature.)
One source of error in this oscillator scheme
is current drawn by the comparators from the
R,C, mode. An emitter-follower, therefore, is
inserted at X to minimize this drain and 02'
placed in series with 020 to drop the comparator sensing voltage one VBE to compensate
for the VBe drop in the emitter-follower.
In order to insure that the square wave drops
quickly and accurately to VBE, an active
clamp scheme is applied to the collector of
02. The base of 09 is held at 2VBE so that as
02 is turned on its base current, its collector

+Vo-~--t---~-------r-------------------------------r-----,

COMPARATOR

·'3

Q14(n8

V1+ V2

-2-

COMPARATOR
024-028

V2

Figure 2_ Simplified Diagram of NE567 Tone Decoder Current-Controlled Oscillator

1

r---

.'" v,

+V-2VBE

"

,

'.

+V-VBE

" " '"

}

V,-V2"KI+V- 2Vae l

V2

'---

'--Vae

---PIN5
_____ PINe

Figure 3. Current-Controlled Oscillator Waveshapes In the NE567
December 1988

4-312

·'2

Application Note

Signetics Linear Products

AN187

Circuit Description of the NE567 Tone Decoder

Is held at VSE. Because O 2 and 03 have the
same geometry and their base-emitter voltages are the same, the maximum 02 current,
when clamped, Is essentially the same as the
collector current of 03 (as limited by R5)' The
flip-flop was optimized for maximum switching
speed to reduce frequency drift due to switchIng speed variations.
Current control of the frequency Is achieved
by making R21 somewhat less than R24 and
restoring the proper voltage for 50% duty
cycle by drawing Ie of 1001lA for the R21 , 020
junction. When Ie Is then varied between 0
and 200J,lA, the frequency changes by ± 7%.
Because of the slight shift In the voltage
levels V 1 and V 2 With Ie, the square wave duty
cycle changes from about 47% to about 53%
over the control range. To avoid drift of freerunning frequency with temperature and supply voltage changes when Ie "4= 0, Ie Is also
made a function of + V -2VSE.
A doubly balanced multiplier formed by 032
through 037 (Figure 1) functions as the phase
comparator. The Input signal Is applied to the
base of 032. Transistors 0 34 - 0 37 are driven
by a square wave taken from the CCO at the
collector of 02. Phase comparator input bias
Is provided by three diodes, 03S through 040,
connected In series, assuring good bias voltage matching from run to run. Emitter resistors R26 and R27, in addition to providing the
necessary dynamic range at the Input, help
stabilize the gain over the wide temperature
range.
The loop DC amplifier Is formed by 051 and
052. Having a current gain of 8, it permits
even a small phase detector output to drive
the CCO the full ± 7%. Therefore, full detection bandwidth can be obtained for any inband Input Signal greater than about
70mVRMS. However, the main purpose of
high loop gain In the tone decoder is to keep
the locked phase as close to 1T/2 as possible
for all but the smallest Input levels, since this
greatly facilitates operation of the quadrature
lock detector. Emitter-resistors Ra6 and Ra7
help stabilize the gain over the required
temperature range. Another function of the
DC amplifier is to allow a higher impedance
level at the low pass filter terminal (Pin 2) so
that a smaller capacitor can be used for a
given loop cutoff frequency. Once again,
emitter-resistors help stabilize the loop gain
over the temperature range.
The quadrature-phase detector (OPD),
formed by a second doubly-balanced multiplier 0 42 - 0 47 Is driven from the quadrature
output (E, F, In Figure 1) of the CCO. The
signal input comes from the emitters of the
input transistors Oa2 and Oaa.

December 1988

The output stage, 053 through 062, compares
the average OPD current in the low pass
output filter RaCa with a temperature-compensated current In R39 (forming the threshold voltage V,),
Since Ra Is slightly lower In value than Ra9 ,
the output stage Is normally off. When the
lock and the OPD current Iq occurs, Pin 1
voltage drops below the threshold voltage V,
and the output stage Is energized.
The uncommitted collector (Pin 8) of the
power NPN output transistor can drive both
100 - 200mA loads and logic elements, including TTL.
The Ko conversion gam for the N E5S7 tone
decoder Is given by

Ko

radians)
= 0.44wo' ( --

(2)

volt-sec

while the Kd conversion gain depends upon
the input signal level as shown in Figure 4.
These parameters can be used to calculate
the lock and capture range as has been
illustrated previously.
The NE5S7 tone decoder is a specialized
loop which can be setup to respond to a
given tone (constant frequency) within its
bandwidth. The free-running frequency is set
by a resistor R1 and capacitor C1' The bandwidth is controlled by the low-pass filter
capacitor C2. A third capacitor Ca integrates
the output of the quadrature-phase detector
(OPD) so that the DC lock-indicating component can switch the power output stage on
when lock is present. The NE5S7 Is optimized
for stability and predictability of free-running
frequency and bandwidth.

must achieve lock. Second, the output capacItor C3 must charge sufficiently to activate the
output stage. For minimum response tome,
these events must be as brief as pOSSible.
As previously discussed, the lock time of a
loop can be minimized by redUCing the response time of the low-pass filter. Thus, C2
must be as small as possible. However, C2
also controls the bandwidth. Therefore, the
response time is an Inverse function of bandWidth as shown by Figure 5, reprinted from
the NE567 data sheet. The upper curve
denotes the expected worst-case response
time when the bandWidth IS controlled solely
by C2 and the Input amplitude Is 200mVRMS
or greater. The response time IS given In
cycles of free-running frequency. For example, a 2% bandwidth at a free-running frequency of 1000 cycles can require as long as
280 cycles (280ms) to lock when the Initial
phase relationship IS at Its worst. Figure 6
gives a tYPical distribution of response time
versus Input phase. Note that, assuming random Initial input phase, only 39'1 SO = 1,16 of the
time will the lock-up time be longer than half
the worst-case lock-up time. Figure 7 shows
some actual measurements of lock-up time
for a setup haVing a worst-case lock-up time
of 27 cycles and a best-case lock-up time of
four Input cycles.
The lower curve on the graph of Figure 5
shows the worst-case lock-up time when the
loop gain Is reduced as a means of reducing
the bandwidth (see data sheet, Alternate
Method of Bandwidth Reduction). The value
of C2 required for this minimum response time
IS
130 [10k + RA ]

C2(mln)=~ ~

J,lF

(3)

Two events must occur before an output Is
given. First, the loop portion of the NE5S7

..

VOLUIlIAD

.

--V

.1

...
...

-

V

V
&I7-"N2

-

'"liT' ,......

•

10

50

...

....

MV-MIS

Figure 4. Phase Comparator Conversion Gain, K d, for the NES67 Tone Decoder

4-313

•

Signetics Linear Products

Application Note

Circuit Description of the NE567 Tone Decoder

AN187

10
'OGO

...
... "'"... "'-

 6GHz.
The high gain and bandwidth of these transistors make careful attention to layout and
bypass critical for optimum performance. The
performance of the PLL cannot be evaluated
independent of the layout. The use of the
application layout in this data sheet and
surface-mount capacitors are highly recommended as a starting point.
The input to the PLL is through a limiting
amplifier with a gain of 200. The input of this
amplifier is differential (Pins 10 and 11). For
single-ended applications. the input must be
coupled through a DC-blocking capacitor with
low impedance at the frequency of interest.
The single-ended input is normally applied to
Pin 11 with Pin 10 AC-bypassed with a lowimpedance capacitor. The input Impedance IS
characteristically slightly above 500n. Impedance match is not necessary. but loading the
signal source should be avoided. When the
source is 50 or 75n. a DC-blocking capacitor
is usually all that is needed.
Input amplification is low enough to assure
reasonable response time in the case of large
signals. but high enough for good AM rejection. After amplification. the input signal
drives one port of a multiplier-cell phase
detector. The other port is driven by the
current-controlled oscillator (ICO). The output
of the phase comparator is a voltage proportional to the phase difference of the input and
December 1988

ICO signals. The error signal is filtered with a
low-pass filter to provide a DC-correction
voltage. and this voltage is converted to a
current which is applied to the ICO. shifting
the frequency in the direction which causes
the input and ICO to have a 90° phase
relationship.
The oscillator is a current-controlled multlvibrator. The current control affects the chargel
discharge rate of the timing capacitor. It is
common for this type of oscillator to be
referred to as a voltage-controlled oscillator
(VCO). because the output of the phase
comparator and the loop filter IS a voltage. To
control the frequency of an Integrated ICO
multivlbrator. the control signal must be conditioned by a voltage-to-current converter. In
the NE568. special circuitry predistorts the
control signal to make the change in frequency a linear function over a large controlvoltage range.
The free-running frequency of the oscillator
depends on the value of the timing capacitor
connected between Pins 4 and 5. The value
of the timing capacitor depends on internal
resistive components and current sources.
When R2 = 1.2kn and R4 = on. a very close
approximation of the correct capacitor value
is:
0.0014
C'=-- F
fa
where
C'

= C2 + CSTRAY.

The temperature-compensation resistor. R4•
affects the actual value of capacitance. This
equation is normalized to 70MHz. See Figure
6 for correction factors.

4-321

The loop filter determines the dynamic characteristics of the loop. In most PLLs. the
phase detector outputs are internally connected to the ICO inputs. The NE568 was
designed with filter output to input connections from Pins 20 ( DET) to 17 (ICO). and
Pins 19 ( DET) to 18 (ICO) external. This
allows the use of both series and shunt loopfilter elements. The loop constants are:
0.127VIRadian (Phase Detector
Constant)
Radians
Ko = 4.2 X log - - (ICO Constant)
V-sec

KD

=

The loop filter determines the general characteristics of the loop. Capacitors Cg. C10• and
resistor R1. control the transient output of the
phase detector. Capacitor Cg suppresses
70MHz feedthrough by interaction with loon
load resistors internal to the phase detector.
Cg

1

2" (50)(fo)

F

At 70MHz. the calculated value is 45pF.
Empirical results with the test and application
board were improved when a 56pF capacitor
was used.
The natural frequency for the loop filter is set
by C10 and R1. If the center frequency of the
loop is 70MHz and the full demodulated
bandwidth is desired. i.e .• fBW = fo17
= 10MHz. and a value for R1 is chosen. the
value of C10 can be calculated.

Preliminary Specification

Signetics Linear Products

150MHz Phase-Locked Loop

NE568

PARTS LIST AND LAYOUT 70MHz APPLICATION NE568D
C1

100nF

±10%

Ceramic chip

1206

C21

18pF

±2%

Ceramic chip

0805

Ceramic OR chip

cl

34pF

±2%

C3

100nF

±10%

Ceramic chip

1206

C4

100nF

±10%

Ceramic chip

1206

Cs

6.81'F

± 10%

Tantalum

35V

Cs

100nF

±10%

Ceramic chip

1206

C7

100nF

±10%

Ceramic chip

1206

Ca

100nF

±10%

Ceramic chip

1206

Cg

56pF

±2%

Ceramic chip

0805 or 1206

C10

560pF

±2%

Ceramic chip

0805 or 1206

C11

47pF

±2%

Ceramic chip

0805 or 1206

C'2

100nF

±10%

Ceramic chip

1206

C13

100nF

±10%

Ceramic chip

1206

R,

27Q

±10%

Chip

1taW

R2

1.2kQ

Trim pot

1taW

R33

43Q

±10%

Chip

1taW

R44

4.7kQ

± 10%

Chip

1taW

RS3

50Q

± 10%

Chip

1taW

RFC 1S

10l'H

± 10%

Surface mount

RFC2s

10l'H

±10%

Surface mount

NOTES:
1. e2 + eSTRAY ~ 20pF
2. C2 + eSTRAY = 36pF for temperature-compensated confIguration with R4 = 47kn
3. For 50fl setup. A, ~ 62fl, Aa ~ 62fl, A5 ~ 75fl for 75fl application.
4 For test configuration A4 ~ Ofl (GND) and 2 ~ 18pF.
5
chip resistors fjumpers) may be substituted with minor degradation of performance

on

e

For the test circuit, R1 was chosen to be 27Q.
The calculated value of C10 is 590pF; 560pF
was chosen as a production value. (In actual
satellite receiver applications, improved video
with low carrier/noise has been observed
With a wider loop-filter bandwidth.)
A typical application of the NE568 is demodulation of FM signals. In this mode of operation, a second single-pole filter is available at
Pin 15 to minimize high frequency feedthrough to the output. The roll-off frequency is
set by an internal resistor of 350Q ± 20%,
and an external capacitor from Pin 15 to
ground. The value of the capacitor is:
C11 =

The final consideration is bypass capacitors
for the supply lines. The capacitors should be
ceramic ChiPS, preferably surface-mount
types. They must be kept very close to the
device. The capacitors from Pins 8 and 9
return to VCC1 before being bypassed with a
separate capacitor to ground. This assures
that no differential loops are created which
might cause instability. The layouts for the
test circuits are recommended.

b. Back of Board

a. Component Side Top of Board

Figure 2

4·322

F

Two final components complete the active
part of the circuitry. A resistor from Pin 12 to
ground sets the temperature stability of the
cirCUit, and a potentiometer from Pin 16 to
ground permits fine tuning of the free-running
oscillator frequency. The Pin 16 potentiometer is normally 1.2kQ. Adjusting this resistance controls current sources which affect
the charge and discharge rates of the timing
capacitor and, thus, the frequency. The value
of the temperature stability resistor is chosen
from the graph In Figure 6; the respective
timing capacitor needs to be changed.

NOTES:
1 Board IS laid out for King BNC Connector PIN KC-79-243-M06 or eqUIValent Mount on bottom (back) of board Add stand-off
2 Back and top side ground must be connected at 8 pOint minimum

December 1988

1

2". (350)fBW

In

each corner

Signetics Linear Products

Preliminary Specification

NE568

150MHz Phase-Locked Loop

PARTS LIST AND LAYOUT 70MHz APPLICATION NE568N
C,

100nF

± 10%

C2 '

17pF

±2%

Ceramic OR chip

50V

cl

34pF

±2%

Ceramic chip

0805

C3

100nF

±10%

Ceramic chip

50V

C4

100nF

±10%

Ceramic chip

50V

C5

6.8MF

±10%

Tantalum

35V

C6

100nF

±10%

Ceramic OR chip

50V

C7

100nF

±10%

Ceramic chip

50V

Cs

100nF

± 10%

Ceramic chip

50V

C9

58pF

±2%

Ceramic chip

50V

C'0

560pF

±2%

Ceramic chip

50V

Cn

47pF

±2%

Ceramic OR chip

50V
50V

Ceramic chip

50V

C'2

100nF

±10%

Ceramic OR chip

C '3

100nF

±10%

Ceramic OR chip

50V

R,

27Q

±10%

Carbon

Y4W

R2

1.2kQ

R33

43Q

±10%

Carbon

Y4W

R4 4

4.7kQ

±10%

Carbon

Y4W

R5 3

50Q

±10%

Carbon

Y4W

RFC,

10MH

±10%

RFC2

10MH

±10%

Trim pot

NOTES:

1.
2.
3.
4.

C2 + CsTRAY ~ 20pF for lest configurallon with R4 ~ on.
C2 ~ 34pF for temperature·compensated conflgurallon with R4 ~ 4.7kn
For 50n setup R, ~ 62n, R3 ~ 75n for 75n applications
For test configuration R4 ~ on (GND) and C2 ~ 17pF.

• •

.. .
:.:

~It~
om·m··::·o

,

~,

I

•I .-•
..
___ e
,! ••• •~
.::.~­

.

::1V' .

~

"

a. Component Side for Leaded Components

b. Solder Side of Board and Chip Capacitors

NOTES:
1, Board IS laId out for King BNC Connector PIN KC-79·243·M06 or eqUivalent mounted on the component side of the board
2 Component Side and solder Side ground planes must be connected at 8 pomts mlOimum

Figure 3

December 1988

4-323

Signetics Linear Products

Preliminary Specification

NE568

150MHz Phase-Locked Loop

1.25E3

7k

1.25E3 , . . - - - - , - - - , . - - - - ,

1.0E3

! :: : : : : ' ' ' ' -' :-' -' -' -,-;\-,-\S-Zt-"N-I- -~
i~
\----1

"\
ZtN \

1

750.0

!i~ 500.0

"-

0.0
1.0

10.0

~73.17

/

- v'

V
L

/

·v JI f- cylOr

o

y

0102030405080708090100

Ate (pIN 12).8 '.

FREQUENCY (MHz)

Figure 5. NE568 Input Impedance with
CP = 1.49pF 20-Pln Dual In-Line Plastic
Package

Figure 6

c.~17PFI

"

1 70.80
o 70

PIN12=GND-

"

!i68.G9
65

'" "-

3.5

~l/l-I

63.0

1.15

3.0

2.5

1.20 1.25 1.30 1.35 1.40

FREQ. ADJ (kQ)
1'1.64 69.1'1 67.26 64.54 82.08 59.70 57.55 55.53
Icc(mA)
·27.33 ·27.44 ·27.58·27.83 ·28.10 ·28.50 ·28.97 ·29.48
Veo LEVEL (dBm)

Figure 7. Typical VCO Frequency va R2 Adjustment

"J

II

'I
/

r--.....

64.48

80
1.OS 1.10

VI\'
/

'r-..

66.G9

December 1988

-I

lk

~O~--~---~-~~
1.0
10.0
100.0
,.oE3

=

75

4k ' - C.=47pF

~ 3k

~OI_--_+---~.-,~,~:..-.. ,..-...-1
..

Figure 4. NE568 Input Impedance with
CP O.5pF 20-Pln SO Package

76.29

t

2k c.=lJPF

FREQUENCY (MHz)

80
78.72

Ii

500.0 1_--_+----1,,.-'\\!-,

"'

100.0

C.~34~F

5k

RI: ' \

~

250.0

8k

o

10 20 30 40 50 80 70 80 80 100 110 120
TYPICAL DUTPlIT LINEARITY

Figure 8. Typical Output Linearity

4-324

AN174

Signetics

Applications for Compandors:

NE570/571/SA571
Application Note
Linear Products

APPLICATIONS
The following circuits will illustrate some of
the wide variety of applications for the
NE570.

BASIC EXPANDOR
Figure 1 shows how the CirCUit would be
hooked up for use as an expandor. Both the
rectifier and L!.G cell inputs are tied to VIN so
that the gain is proportional to the average
value of (VIN). Thus, when VIN falls 6dB, the
gain drops 6dB and the output drops 12dB.
The exact expression for the gain is

.

Gain expo =

[2

R3 V IN (avg) ]2

share a common capacitor, a small current
will flow between the L!.G cell summing node
and the rectifier summing node due to offset
voltages. ThiS current will produce an error in
the gain control Signal at low levels, degrading tracking accuracy.
The output of the expandor IS biased up to 3V
by the DC gain provided by R3, R4. The
output will bias up to
VOUT DC

R3

= (1+-)
R4

VREF

For supply voltages higher than 6V, R4 can
be shunted With an external resistor to bias
the output up to Y2VCC.

;

Rl R2 18

18 = 140!lA
The maximum input that can be handled by
the circuit in Figure 1 is a peak of 3V. The
rectifier input current can be as large as
1= 3V/Rl = 3V/10k = 300!lA. The L!.G cell
input current should be limited to I = 2.BV I
R2 = 2.BV 120k = 140j.LA. If it is necessary to
handle larger input voltages than 0 ± 2.BV
peak, external resistors should be placed In
series with Rl and R2 to limit the input current
to the above values.
Figure 1 shows a pair of input capacitors CINl
and CIN2. It is now necessary to use both
capacitors if low level tracking accuracy is not
important. If Rl and R2 are tied together and

Note that it is possible to externally increase
R 1, R2, and R3, and to decrease R3 and R4.
ThiS allows a great deal of flexibility in setting
up system levels. If larger input signals are to
be handled, Rl and R2 may be increased; if a
larger output is required, R3 may be increased. To obtain the largest dynamic range
out of this Circuit, the rectifier input should
always be as large as possible (subject to the
± 300j.LA peak current restriction).

BASIC COMPRESSOR
Figure 2 shows how to use the NE570/571 as
a compressor. It functions as an expandor In
the feedback loop of an op amp. If the Input
rises 6dB, the output can rise only 3dB. The
3dB Increase in output level produces a 3dB
Increase In gain In the L!.G cell, yielding a 6dB

Increase In feedback current to the summing
node. Exact expression for gain is

Gain compo

=

[

Rl R2 18

]

2 R3VIN (avg)

The same restrictions for the rectifier and L!.G
cell maximum input current still hold, which
place a limit on the maximum compressor
output. As in the expandor, the rectifier and
L!.G cell Inputs could be made common to
save a capacitor, but low level tracking accuracy would suffer. Since there is no DC
feedback path around the op amp through
the L!.G cell, one must be provided externally.
The pair of resistors Roc and the capaCitor
CDC must be prOVided. The op amp output will
bias up to

For the largest dynamic range, the compressor output should be as large as possible so
that the rectifier input IS as large as possible
(subject to the ± 300!lA peak current restriction). If the input signal is small, a large output
can be produced by reducing R3 With the
attendant decrease In Input Impedance, or by
increasing Rl or R2. It would be best to
increase R2 rather than Rl so that the rectifier
Input current is not reduced.

.,

.,--:-~

VOUT

-{.J-----'IIIo'

...Figure 2_ Basic Compressor

DISTORTION TRIM
Distortion can be produced by voltage offsets
in the L!.G cell. The distortion is mainly even
harmonics, and drops with decreasing input
Signal (input Signal meaning the current into
the L!.G cell). The THD trim terminal provides

Figure 1, Basic Expandor

December 19BB

4-325

I

~2

R,

CIN1

I,
I

I

•

Signetics Linear Products

Application Note

Applications for Compandors: NE570j571jSA571

Vee

-20 r--------.

-'0
36V

o

ToTH~T"m

"'"

~~

.......

... -' ·20

±.,oo~

H.30

a~8 ·40
m
,",z

89
~'"

Figure 3. THO Trim Network

·60
·10

a means for trimming out the offset voltages
and thus trimming out the dIstortion. The
circuit shown in Figure 3 is suitable, as would
be any other capable of delivering ± 30pA
into lOOn resistor tied to 1.8V.

-10
0
.10
EXPANDOR INPUT lEVEL dB OR

COMPRESSOR OUTPUT LEVEL

It is possible to deviate from the 2·to·l
transfer characteristic at low levels as shown
in the circuit of Figure 4. Either RA or Rs, (but
not both), is required. The voltage on CRECT
is 2 X VSE plus Y,N avg. For low level inputs
Y,N avg is negligible, so we can assume 1.3V
as the bias on CRECT. If RA is placed from
CRECT to AND we will bleed off a current

I = 1.3VIRA. If the rectifIer average input
current is less than this value, there will be no
gain control Input to the AG cell so that its
gain will be zero and the expandor output will
be zero. As the Input level is raised, the input
current will exceed 1.3VIRA and the expandor output WIll become active. For large input
signals, RA will have little effect. The result of
this is that we WIll deviate from the 2-to-l
expansion, present at high levels, to an infinite expansion at low levels where the output
shuts off completely. Figure 5 shows some
examples of trackIng curves which can be
obtained. Complementary curves would be
obtained for a compressor, where at low level
signals the result would be infinite compression. The bleed current through RA will be a
function of temperature because of the two
VSE drops, so the low level tracking will drift
with temperature. If a negative supply is

"

"{

-,
VOUT

CIN2

o

-10

EXPANDOA INPUT LEVEL dB OR
COMPRESSOR OUTPUT LEVEL

Figure 6. Mistracking With RB

RECTIFIER BIAS CURRENT
CANCELLATION
The rectifier has an input bias current of
between 50 and 100nA. This limits the dy·
namic range of the rectifier to about 60dB. It
also limits the amount of attenuation of the
AG cell. The rectifier dynamic range may be
increased by about 20dB by the bias current
trim network shown in Figure 7. Figure 8
shows the rectifier performance with and
without bias current cancellatIon.

ATTACK AND DECAY TIME

-,

The attack and decay times of the compan·
dor are determined by the rectifier fIlter time
constant 10k X CRECT. Figure 9 shows how
the gain will change when the input signal
undergoes a 10, 20, or 30dB change in level.

reRleT

....
Figure 4. Expandor With Low Level Mistracking
December 1988

-20,---------"

-'0

Figure 5. Mistracking With RA

LOW LEVEL MISTRACKING
The compandor will follow a 2·to·l tracking
ratio down to very low levels. The rectifier is
responsible for errors in gain, and it is the
rectifier input bias current of < 100nA that
produces errors at low levels. The magnitude
of the error can be estimated. For a full-scale
rectIfIer input signal of ± 200pA, the average
input current will be 127pA. When the input
signal level drops to a I/lA average, the bias
current will produce a 10% or ldB error in
gain. This will occur at 42dB below the
maximum input level.

CIN1

available, if would be desirable to tie RA to
that, rather than ground, and to increase its
value accordingly. The bleed current will then
be less sensitive to the VSE temperature drift.
Rs will supply an extra current to the rectifier
equal to (Vcc - 1.3V)R s. In this case, the
expandor transfer characteristic will devIate
towards l-to-l at low levels. At low levels the
expandor gain will stop dropping and the
expansion will cease. In a compressor, this
would lead to a lack of compressIon at low
levels. Figure 6 shows some typical transfer
curves. An Rs value of approximately 2.5M
would trim the low level tracking so as to
match the Bell system N2 trunk compandor
characteristic.

~! -10

201(

AN174

4-326

The attack time is much faster than the
decay, which is deSirable in most applicatIons. Figure 10 shows the compressor attack
envelope for a + 12dB step in input level. The
initial output level of 1 Unit instantaneously
rises to 4 units, and then starts to fall towards

Application Note

Signetics Linear Products

AN174

Applications for Compandors: NE570/571/SA571

"V

....
3IV
'OMEG

00-_·....v.
..1r-.-

TIME eONSTANTS

. .~ , . . .

Figure 11. Compf8880f Relea.e
Envelope -12dB Step

TORECTlFiEA
INPUT

PlNIOR'S

its final value of 2 units. The cCln recom·
mendation on attack and decay times for
telephone system companders defines the
attack time as when the envelope has fallen
to a level of 3 units, corresponding to t = 0.15
in the figure. The ccln recommends an
attack time of 3 ± 2ms, which suggests an RC
product of 20ms. Figure 11 shows the compressor output envelope when the input level
is suddenly reduced 12dB. The output, initially
at a level of 4 units, drops 12dB to 1 unit and
then rises to its final value of 2 units. The
ccln defines release time as when the
output has risen to 1.5 units, and suggests a
value of 13.5 ± 9ms. This corresponds to
t - 0.675 in the figure, which again suggests a
20ms RC product. Since Rl -10k, the ccln
recommendations will be met if ~ECT = 21lF.

Figure 7. Rectifier Bla. Current
Compen88tlon

.

-

wmtOUT

.

101C.CRECT

~~~-~.-~.~.~~~~~~
IIICTtPJIJI....uTLEYlL....

....

"'. "

Figure 8. Rectifier Performance With
Bias Current Compen88tlon

There is a trade-off between fast response
and low distortion. If a small CRECT is used to
get very fast attack and decay, some ripple
will appear on the gain control line and
produce distortion. As a rule, a 1/-IF CRECT will
produce 0.2% distortion at 1kHz. The distortion is inversely proportional to both frequency and capacitance. Thus, for telephone applications where CRECT - 21lF, the ripple
would cause 0.1 % distortion at 1kHz and
0.33% at 800Hz. The low frequency distortion
generated by a compressor would be cancelled (or undistorted) by an expandor, providing that they have the same value of

~ECT·

FAST ATTACK, SLOW RELEASE
HARD LIMITER

Figure 9. Gain va Time Input Step.
of ± 10, ± 20, ± 30dB

I~bt:~,
,
012'.
7'
"ME CONSTANT. 101lCRECT

...

"""

figure 10. Compre880r Attack Envelope
+12dB Step

December 1988

The NE570/571 can be easily used to make
an excellent limiter. Figure 12 shows a typical
circuit which requires Y2 of an NE570/571, 1t2
of an LM339 quad comparator, and a PNP
transistor. For small signals, the aG cell is
nearly off, and the circuit runs at unity gain as
set by Re, R7. When the output signal tries to
exceed a + or -W peak, a comparator
threshold is exceeded. The PNP is tumed on
and rapidly charges C4 which activates the
aG cell. Negative feedback through the aG
cell reduces the gain and the output Signal
level. The attack time is set by the RC
product of R18 and C4, and the release time Is
determined by C4 and the internal rectifier

4-327

resistor, which is 10k. The Circuit shown
attacks in less than 1ms and has a release
time constant of 100ms. Rg trickles about
0.7 jJA through the rectifier to prevent C4 from
becoming completely discharged. The gain
cell is activated when the voltage on Pin 1 or
16 exceeds two diode drops. If C4 were
allowed to become completely discharged,
there would be a slight delay before rt recharged to > 1.2V and activated limiting
action.
A stereo limiter can be built out of 1 NE5701
571, 1 LM339 and two PNP transistors. The
resistor networks R12, R13 and R14, R15,
which set the limiting thresholds. could be
common between channels. To gang the
stareo channels together (limiting in one
channel will produce a corresponding gain
change in the second channel to maintain the
balance of the stereo image), then Pins 1 and
16 should be jumpered together. The outputs
of all 4 comparators may then be tied together, and only one PNP transistor and one
capacitor C4 need be used. The release time
will then be the product 5k X C4 since two
channels are being supplied current from C4'

USE OF EXTERNAL OP AMP
The operational amplifiers in the NE570/571
are not adequate for some applications. The
slew rate, bandwidth, noise, and output drive
capability can limit performance in many systems. For best performance, an extemal op
amp can be used. The extemal op amp may
be powered by bipolar supplies for a larger
output swing.
Figure 13 shows how an extemal op amp may
be connected. The non-inverting input must
be biased at about 1.aV. This is easily accomplished by tying it to either Pin a or 9, the THO
trim pins, since these pins sit at 1.aV. An
optional RC decoupling network is shown
which will filter out the noise from the NE5701
571 reference (typically about 10llV in 20kHz
BW). The inverting input of the external op
amp is tied to the inverting input of the
intemal op amp. The output of the external op
amp is then used, with the intemal op amp
output left to float. If the external op amp is
used single supply (+ Vee and ground), it
must have an input common-mode range
down to less than 1.aV.

N2 COMPANDOR
There are four primary considerations involved in the application of the NE570/571 in
an N2 compandor. These are matching of
Input and output levels, accurate 6000 input
and output Impedances, conformance to the
Bell system low level tracking curve, and
proper attack and release times.

•
~

Application Note

Signetics linear Products

Applications for Compandors: NE570j571jSA571

AN174

2/4 LM33I

1/2 .570/571

OR LUll3

2.15

10K

-,
2.2MEG

R.

.oon

"oo

...

":r:.
"

.--,

..

5,12

uv

':"

+ 15V Pin 13
GND Pin 4
R1. R2. R4 are mternal to the NE570/571

Figure 12. Fast Attack, Slow Release Hard Limiter

....

R GAIN TAtM

•••

Figure 13. Use of External Op Amp
Figure 14 shows the implementation of an N2
compressor. The input level of O.245VRMS is
stepped up to 1.41 V RMS by the 600n: 20kn
matching transformer. The 20k input resistor
properly terminates the transformer. An internal
20kn resistor (R3) is provided, but for accurate
impedance termination an external resistor
should be used. The output impedance is provided by the 4kn output resistor and the 4kn:
600n output transformer. The O.275VRMS output level requires a 1.4V op amp output level.
This can be provided by increasing the value of
R2 with an external reSistor, which can be
selected to fine trim the gain. A rearrangement
of the compressor gain equation (6) allows us to
determine the value for R2.

12 X 2 X 20k X 1.27
10k X 140j.tA

ROUT

>2_'~_'V_~_M_·~IC-_~ ~_~_·:_·_V
______

Figure 14. N2 Compressor
The external resistance required will thus be
36.3k - 20k = 16.3k.

network around the op amp provides DC
feedback to bias the output at DC.

The Bell-compatible low level tracking characteristic is provided by the low level trim
resistor from CREeT to Vee. As shown in
Figure 6, this will skew the system to a 1: 1
transfer characteristic at low levels. The 2p.F
rectifier capacitor provides attack and release
times of 3ms and 13.5ms, respectively, as
shown in Figures 10 and 11. The R-C-R

An N2 expandor is shown in Figure 15. The
input level of 3.27VRMS is stepped down to
1.33V by the 600n:100n transformer, which
is terminated with a 1oon resistor for accurate impedance matching. The output impedance is accurately set by the 150n output
resistor and the 150n:600n output transformer. With this configuration, the 3.46V
transformer output requires a 3.46V op amp

= 36.3k

December 1988

'_~_F --J~~

________-.____________ __·_Ok___

4-328

Application Note

Signetlcs Linear Products

Applications for Compandors: NE570/571/SA571

AN174

A,20K

R GAIN TRIM

R, 20K

6000 lOOn

10K

327

VRMS
600n

100n
R'N

""'---1

vcc .............

R LOW LEVEL

TRIM DCl MEG

•

Figure 15. N2 Expandor

output. To obtain this output level, it is necessary to increase the value of R3 with an
external trim resistor. The new value of R3
can be found with the expandor gain equation
R, R2 18 Gain
R3 = --'-'=-::-2 VIN avg
10k

x 20k X 140/lA x 2.S
2 X 1.20

= 30.3k
An external addition to R3 of 1Ok is required,
and this value can be selected to accurately
set the high level gain.
A low level trim resistor from CRECT to Vcc of
about 3M provides matching of the Bell lowlevel tracking curve, and the 2j.1F value of
CRECT provides the proper attack and release
times. A ISk resistor from the summing node
te ground biases the output to 7Voc.

VOLTAGE-CONTROLLED
ATTENUATOR
The variable gain cell in the NE570/571 may
be used as the heart of a high quality voltagecontrolled amplifier (VCA). Figure lS shows a
typical circuit which uses an external op amp
for better performance, and an exponential
converter to get a control characteristic of
-SdBIV. Trim networks are shown to null out
distertion and DC shift. and to fine trim gain to
OdB with OV of control voltage.
Op amp A2 and transistors 0, and 02 form
the exponential converter generating an exponential gain control current, which is fed

December 1988

into the rectifier. A reference current of
150/lA, (15V and R20 = lOOk), is attenuated a
factor of two (SdB) for every volt increase in
the control voltage. Capacitor Cs slows down
gain changes to a 20ms time constant
(Cs x R,) so that an abrupt change in the
control voltage will produce a smooth sounding gain change. R, s assures that for large
control voltages the circuit will go to full
attenuation. The rectifier bias current would
normally limit the gain reduction to about
70dB. R, s draws excess current out of the
rectHier. After approximately 50dB of attenuation at a -6dBIV slope, the slope steepens
and attenuation becomes much more rapid
until the circuit totally shuts off at about 9V of
control voltage. A, should be a low noise high
slew rate op amp. R' 3 and R14 establish
approximately a OV bias at A,'s output.
With a OV control voltage, R,S should be
adjusted for OdB gain. At 1V(-6dB gain) Rs
should be adjusted for minimum distortion
with a large (+ 1OdBm) input signal. The
output DC bias (A, output) should be measured at full attenuation (+ 10V control voltage) and then Rs is adjusted to give the same
value at OdB gain. Properly adjusted, the
circuit will give typically less than 0.1 % distortion at any gain with a DC output voltage
variation of only a few millivolts. The clipping
level (140/lA into Pin 3, 14) is ± 10V peak. A
signal-to-noise ratio of 90dB can be obtained.
If several VCAs must track each other, a
common exponential converter can be used.
Transisters can simply be added in parallel
with 02 to control the other channels. The
transistors should be maintained at the same
temperature for best tracking.

4-329

AUTOMATIC LEVEL CONTROL
The NE570 can be used to make a very high
performance ALC as shown in Figure 17. This
circuit hook-up is very similar to the basic
compressor shown in Figure 2 except that the
rectifier input is tied to the input rather than
the output. This makes gain inversely proportional to input level so that a 20dB drop in
input level will produce a 20dB increase in
gain. The output will remain fixed at a constant level. As shown, the circuit will maintain
an output level of ± 1dB for an input range of
+ 14 to - 43dB at 1kHz. Additional external
components will allow the output level to be
adjusted. Some relevant design equations
are:
Output level

R, R218

=- - 2 R3

18 = 140/lA
Gain =

R, R2 18
where
2 R3 VIN (avg)

VIN
VIN (avg)

--- =

"
--=
= 1.11
2\/'2

(for sine wave)

If ALC action at very low input levels is not
desired, the addition of resistor Rx will limit
the maximum gain of the circuit.
R, +Rx

- - - X R2 X 18

Gain max

= _1_._BV_ _:::-_ __
2 R3

The time constant of the circuit is determined
by the rectifier capacitor, CRECT, and an
internal 10k resistor.

Application Note

Signetics Linear Products

Applications for Compandors: NE570j571jSA571

AN174

+15V

150k

Rl0

THD
TRIM

3.8V

DC SHIFT
TRIM

lOOk

lOOk

62k
R14

R8
220k
R7

62k
R13

I

+10pF

loon

Cl

IN11'~

C2

220k
Rll

51k

R16

l"TF
OUT
C5 tOOk
R17

R6

lOOk
R5

1:16- ----- - ~
CONTROL R22
VOLTAGE 5.491<

0-10V

o--"",..,........--+---<~-""',..,..._~

44 MEG

R18
-15V

lOOk
H>-""tv----+15
R20

Figure 16. Voltage-Controlled Attenuator

r = 10k GRECT
Response time can be made faster at the
expense of distortion. Distortion can be approximated by the equation:
THD

1JlF
=( - ) (1kHZ)
- - X 0.2%
GRECT

freq.

proper selection of fixed resistors can be
used instead of the potentiometer. The optional threshold resistor will make the com·
pression or expansion ratio deviate towards
1:1 at low levels. A wide variety of (input)
output characteristics can be created with
this Circuit, some of which are shown in
Figure 16.

HI-FI COMPANDOR
VARIABLE SLOPE
COMPRESSOR-EXPANDOR
Gompression and expansion ratios other than
2: 1 can be achieved by the circuit shown in
Figure 16. Rotation of the dual potentiometer
causes the circuit hook-up to change from a
basic compressor to a basic expandor. In the
center of rotation, the circuit is 1:1, has
neither compression nor expansion. The (input) output transfer characteristic is thus
continuously variable from 2:1 compression,
through 1: 1 up to 1:2 expansion. If a fixed
compression or expansion ratio is desired,
December 1966

The NE570 can be used to construct a high
performance compandor suitable for use with
music. This type of system can be used for
noise reduction in tape recorders, transmission systems, bucket brigade delay lines, and
digital audio systems. The circuits to be
described contain features which improve
performance, but are not required for ali
applications.
A major problem with the Simple NE570
compressor (Figure 2) is the limited op amp
gain at high frequencies. For weak input
signals, the compressor circuit operates at

4-330

high gain and the 570 op amp simply runs out
of loop gain. Another problem with the 570 op
amp is its limited slew rate of about 0.6V 1!I8.
ThiS IS a limitation of the expandor, since the
expandor is more likely to produce large
output signals than a compressor.
Figure 20 is a circuit for a high fidelity
compressor which uses an external op amp
and has a high gain and wide bandwidth. An
input compensation network is required for
stability.
Another feature of the circuit in Figure 20 is
that the rectifier capacitor (Gg) is not
grounded, but is tied to the output of an op
amp circuit. This circuit, built around an
LM324, speeds up the compressor aUack
time at low Signal levels. The response times
of the simple expandor and compressor (Figures 1 and 2) become longer at low signal
levels. The time constant is not simply
10k X GRECT, but is really:
0.026V) )
( 10k + 2 ( X GRECT
IRECT

Signetics Linear Products

Application Note

Applications for Compandors: NE570/571/SA571

AN174

When the rectifier input level drops from
OdBm to -30dBm, the time constant increases from 10. 7k X GRECT to 32.6k
X GRECT. In systems where there is unity
gain between the compressor and expandor,
this will cause no overall error. Gain or loss
between the compressor and expandor will
be a mistracking of low signal dynamics. The
circuit with the LM324 will greatly reduce this
problem for systems which cannot guarantee
the unity gain.
When a compressor is operating at high gain,
(small input signal), and is suddenly hit with a
signal, it will overload until it can reduce its
gain. Overloaded, the output will attempt to
swing rail to rail. This compressor is limited to
approximately a 7Vp.p output swing by the
brute force clamp diodes 03 and 0 4 , The
diodes cannot be placed in the feedback loop
because their capacitance would limit high
frequency gain. The purpose of limiting the
output swing is to avoid overloading any
succeeding circuit such as a tape recorder
input.

...

The time it takes for the compressor to
recover from overload is determined by the
rectifier capacitor Gg. A smaller capacitor will
allow faster response to transients, but will
produce more low frequency third harmonic
distortion due to gain modulation. A value of
1jtF seems to be a good compromise value
and yields good subjective results. Of course,
the expandor should have exactly the same
value rectWier capacitor for proper transient
response. Systems which have good low
frequency amplitude and phase response can
use compandors with smaller rectifier capacitors, since the third harmonic distortion which
is generated by the compressor will be undistorted by the expandor.

10K

C.... I

c..12) ....w .....-~--,\O""'-.

.....

Simple compandor systems are subject to a
problem known as breathing. As the system

fl.'4)
"OUT
(7,10)

-...

R,1.

-

......

(2,11.

1'MIIUHOLD

OUTPUT

1 1110

LOG

TC07230S

Figure 18. Variable Slope Compressor·Expandor

December 1988

4·331

Figure 19, Typical Input-output
Tracking Curves of Variable RatiO
Compressor·Expandor

•

Signetlcs Linear Products

Appl ication Note

Applications for Compandors: NE570j571jSA571

AN174

is changing gain, the change in the background noise level can sometimes be heard.

• ".F c,.

The compressor in Figure 20 contains a high
frequency pre-emphasis circuit (C2, Rs and
Ca, R14), which helps solve this problem.
Matching de-emphasis on the expandor is
required. More complex designs could make
the pre-emphasis variable and further reduce
breathing.
Uy

The expandor to complement the compressor
is shown in Figure 21. Here an external op
amp is used for high slew rate. Both the
compressor and expandor have unity gain
levels of OdB. Trim networks are shown for
distortion (THO) and DC shift. The distortion
trim should be done first, With an input of OdB
at 10kHz. The DC shift should be adjusted for
minimum envelope bounce with tone bursts.
When applied to consumer tape recorders,
the subjective performance of this system is
excellent.

...

,

R..

DC. SHin
TRIM

Ru
22GOC
R..
22GOC

T"O

TRIM

51'F

-.

. . . -"01"""On

I.

...

Rn

0 ..
.,.

C,.,I'."F

c,

c,

...

,

+ 7.SY

.,.

.

,.
0,

D,
D.

Figure 20. Hi-Fi Compressor With Pre-emphasis

December 1988

4-332

COMPRESSOR

'c,}:OUT

Signetics Linear Products

Application Note

Applications for Compandors: NE570/571/SA571

AN174

+3.8V

.I

Figure 21. Hi-Fi Expandor With De-emphasis

December 1988

4-333

Signetics

AN176
Compandor Cookbook
Application Note

Linear Products

Compandors are versatile, low cost, dualchannel gain control devices for audio frequencies. They are used in tape decks, cordless telephones, and wireless microphones
performing noise reduction. Electronic organs, modems and mobile telephone equipment use compandors for signal level control.
So what is companding? Why do it at all?
What happens when we do it? Compandor is
the contraction of the two words compressor
and expandor. There is one basic reason to
compress a signal before sending it through a
telephone line or recording it on a cassette
tape: to process that signal (music, speech,
data) so that all parts of it are above the
inherent noise floor of the transmission medium and yet not running into the max. dynamic
range limits, causing clipping and distortion.
The diagrams below demonstrate the idea;
they are not totally correct because in the real
world of electronics the 3kHz tone is riding on
the 1kHz tone. They are shown separated for
better explanation.
Figure 1 is the signal from the source. Figure
2 shows the noise always in the transmission
medium. Figure 3 shows the max limits of the
transmission medium and what happens
when a signal larger than those limits is sent
through it. Figure 4 is the result of compressing the signal (note that the larger signal
would not be clipped when transmitted).

3V

-3V

Figure 1. Original Signal Input

-2V
-3V

MAX DYNAMIC
RANGE IV pk-pk
0P03490S

Figure 3

Figure 2. Wide-Band Noise Floor
of Transmission Line

3V

The received/playback signal is processed
(expanded) in exactly the same - only inverted - ratio as the input Signal was compressed. The end result is a clean, undistorted signal with a high signal-to-noise ratio.
This document has been designed to give the
reader a basic working knowledge of the
Signetics Compandor family. The analyses of

-3V
OP03SOOS

Figure 4_ Signal After Compression

BLOCK DIAGRAMS
NE570/5711SA571

NE572

CURRENT

CONTROLLED

OUTPUT

GAlNCEU.

BUFfER

RELEASE
TIllE
CAPACItOR

VOLTAGE

10
CURRENT

SEE NOra
AT END
aD02761S

Signetics Linear Products

Application Note

Compandor Cookbook

AN176

CURRENT
CONTROLLED
GAIN CELL

R2

t--'W--1II-...,

i

VOLTAGE TO
CURRENT
CONVERTER

I
I
I

~----------------~--ov~

Figure 5. Basic Compressor
three primary applications will be accompanied by "recipes" describing how to select
external components (for both proper operation and function modification). Schematic
and artwork for an application board are also
provided. For comprehensive technical information consult the Compandor Product Guide
or the Linear Data Manual.
The basic blocks in a compandor are the
current-controlled variable gain cell (t.G), voltage-to-current converter (rectifier), and operational amplifier. Each Signetics compandor
package has two identical, independent
channels with the following block diagrams
(notice that the 570171 is different from the
572).
The operational amplifier is the main Signal
path and output drive.
The full-wave averaging rectifier measures
the AC amplitude of a signal and develops a
control current for the variable gain cell.
The variable gain cell uses the rectifier control current to provide variable gain control for
the operational amplifier gain block.
The compandor can function as a Compressor, Expandor, and Automatic Level Controller or as a complete compressor/ expandor
system as described in the following:
1) The COMPRESSOR function processes
uncontrolled input signals into controlled
output signals. The purpose of this is to
avoid distortion caused by a narrow dynamic range medium, such as telephone
lines, RF and satellite transmissions, and
magnetic tape. The Compressor can also
limit the level of a signal.
2) The EXPANDOR function allows a user to
increase the dynamic range of an incoming
December 1988

compressed signal such as radio broadcasts.
3) The compressor/expandor system allows
a user to retain dynamic range and reduce
the effects of noise introduced by the
transmission medium.
4) The AUTOMATIC LEVEL CONTROL (ALC)
function (like the familiar automatic gain
control) adjusts its gain proportionally with
the input amplitude. This ALC circuit therefore transforms a widely varying input signal into a fixed amplitude output signal
without clipping and distortion.

HOW TO DESIGN COMPANDOR
CIRCUITS
The rest of the cookbook will provide you with
baSIC compressor, expandor, and automatic
level control application information. A
NE570/571 has been used in all of the
circuits. If high-fidelity audio or separately
programmable attack and decay time are
needed, the NE572 with a low noise op amp
should be used.
The compressor (see Figure 5) utilizes all
basic building blocks of the compandor. In
this configuration, the variable gain cell is
placed in the feedback loop of the standard
inverting amplifier circuit. The gain equation is
Av = -RF/RIN. As shown above, the variable
gain cell acts as a variable feedback resistor
(RF) (See Figure 5).
As the input signal increases above the
crossover level of OdB, the variable resistor
decreases in value. This causes the gain to
decrease, thus limiting the output amplitude.
Below the crossover level of OdB, an increase
in input signal causes the variable resistor to

4-335

increase in value, thereby causing the output
signal's amplitude to increase.
In the compressor configuration, the rectifier
is connected to the output.
The complete equation for the compressor
gain is:
Gain compo = [
where: R1
R2
R3
Is

=
=
=
=

R1 R21B
2 R3VIN(avg)

]~2

10k
20k
20k
140l1A

VIN(avg) = O.9(VIN(RMS)

COMPRESSOR RECIPE
1) DC bias the output half way between the
supply and ground to get maximum headroom. The circuit In Figure 6 is designed
around a system supply of 6V, thus the
output DC level should be 3V.
VOUT DC = (1 + (2Roc/R4ll VREF
where:

R4 = 30k
VREF = 1.8V
Roc is external

manipulating the equation, the result is...
Roc=((VOUT)_1
VREF

)~2

Note that the C(OC) should be large enough to
totally short out any AC in this feedback loop.

•

Signetics Linear Products

Application Note

Compandor Cookbook

AN176

2) Analyze the OUTPUT signal's anticipated
amplitude.
a) if larger than 2.BV peak, R2 needs to be
increased. (see INGREDIENTS section)
b) if larger than 3.0V peak, R, will also
need to be increased.
By limiting the peak input currents we avoid
signal distortion.

3) The input and output coupling caps need to
be large enough not to attenuate any
desired frequencies (Xc = 1/(6.2Bxf).
4) The CRECT should be 1j.lF to 2j.lF for initial
setup. This directly affects Attack and Release times.
5) An input buffer may be necessary if the
source's output impedance needs matching.
6) Pre-emphasis may be used to reduce
noise-pumping, breathing, etc., if present.
See the NE570/571 data sheet for specific
details.
7) Distortion (THD) trim pins are available if
the already low distortion needs to be
further reduced. Refer to data sheet for
trimming network. Note that if not used, the
THD trim pins should have 200pF caps to
ground.
B) At very low input signal levels, the rectifier's errors become significant and can be
reduced with the Low Level Mistracking
network. (This technique prevents infinite
compression at low input levels.)
The EXPANDOR utilizes all the basic building
blocks of the compandor (see Figure 7). In
this configuration the variable gain cell is
placed in the inverting input lead of the
operational amplifier and acts as a variable
input reSistance, RIN. The basic gain equation
for operational amplifiers in the standard
inverting feedback loop is Av = -RF/RIN.

Roc

5,12

~------~7~,,~O----OV~

VRE.

NOTES:
Max AC current Into:
• Gameell IS 1401tA peak

• Rectifier IS 3001JA, peak
All components are Internal, except the caps and Roc

Figure 6. Basic Compressor
As the input amplitude increases above the
crossover level of OdBM, this variable resistor
decreases in value, causing the gain to increase, thus forcing the output amplitude to
increase (refer to Figure 10).

The complete equation for the expandor gain
is:

Below the crossover level, an increase in
input amplitude causes the variable resistor
to increase in value, thus forcing the output
amplitude to decrease.
In the expandor configuration the rectifier is
connected to the input.

where: R, = 10k
R2 = 20k
R3 = 20k
19 = 140j.tA
VIN(avg) = 0.9 (VIN(RMS)

,
v~

~1

R.

CURRENT

CONTROLLED
GAIN CELL

R,

>--.....-ov~

VOLTAGE
10 CURRENT
CONVaITER

~
TC07330S

Figure 7. Basic Expandor
December 19B8

4·336

Application Note

Signetics Linear Products

Compandor Cookbook

EXPANDOR RECIPE
1) DC bias the output halfway between the
supply and ground to get maximum headroom. The circuit in Figure 8 is designed
around a system supply of 6V so the output
DC level should be 3V.
VOUT DC = (1 + R3/R4)VREF
where: R3 = 20k
R4 = 30k
VREF = 1.8V
Note that when using a supply voltage higher
than 6V the DC output level should be adjusted. To increase the DC output level, it is
recommended that R4 be decreased by adding parallel resistance to it. (Changing R3
would also affect the expandor's AC gain and
thus cause a mismatch in a companding
system.)

AN176

The complete gain equation for the ALC is:

As the input amplitude increases above the
crossover point, the overall system gain decreases proportionally, holding the output
amplitude constant.

Gain = __R_1_R.;;c2ccls,--_
2 R3 VIN(avg)

As the input amplitude decreases below the
crossover point, the overall system gain increases proportionally, holding the output
amplitude at the same constant level.
VIN
7r
where VIN(avg) = 2V2 = 1.11 (for sine wave)

R3

(6. 11)

20K

vS

3,14

VOUT

20K

7,10

2) Analyze the input signal's anticipated am-

pl~ude:

a) if larger than 2.8V peak, R2 needs to be
increased. (see INGREDIENTS section)

"l..:;N2

A1

2.15 10K

b) if larger than 3.0V peak, R1 will also
need to be increased. (see INGREDIENTS)

By limiting the peak input currents we avoid
signal distortion.
3) The input and output decoupling caps need
to be large enough not to attenuate any
desired frequencies.
4) The CRECT should be I/1F to 2/1F for initial
setup.
5) An input buffer may be necessary if the
source's output impedance needs matching.
6) De-emphasis would be necessary if the
complementary compressor circuit had
been pre-emphasized (as in a tape deck
application). See the Hi-Fi Expandor application in the Linear Data Manual.
7) Distortion (THD) trim pins are available if
the already low distortion needs to be
further reduced. See Linear Data Manual
for trimming network. Note that if not used,
the THD trim pins should have 200pF caps
to ground.
8) At very low input signal levels, the rectifier's errors become significant and can be
reduced with the Low Level Mistracking
network (see Linear Data Manual). (This
technique prevents infinite expansion at
low input levels.)

NOTE:
All components are Internal except caps

Figure 8. Basic Expandor

10K

(5,12)~

____

-I~

30pF

1,F

A3 20K

v~o--~-~~~+-<~-~~-'__-4~--;
(6,11)

In the ALC configuration, (Figure 9), the
variable gain cell is placed in the feedback
loop of the operational amplifier (as in the
Compressor) and the rectifier is connected to
the input.

1.8V

Figure 9. Automatic Level Control
December 1988

4-337

_ _ _ _"

Application Note

Slgnetlcs Unear Products

Compandor Cookbook

Note that for very low Input levels, ALC may
not be desired and to limit the maximum gain,
resistor Rx has been added. The modified
gain equation is:

(
Gain max.

R,

+ Rx )

1.BV
X R2 X Ie
= ______
....:.._-=-_

2 R3

AN176

R3 (20kn) acta in conjunction with R4 as the
feedback resistor (RF) (expandor configuration) in the equation. (R3'S value can be either
reduced or increased externally.) However, it
is recommended that R4 be the one to
change when adjusting the output DC level.
R4 (30kn) aOls as the input resistor (RIN) in
the standard non-inverting op amp circuit. (Ita
value can only be reduced.)
VOUT OC = (1 + (R3/R4))VREF
(for the Expandor)
VOUT OC - (1 + (2Roc/R4llVREF
(for the Compandor, ALC)

Rx;!!! «desired max gain) X 26k) -10k

INGREDIENTS
[Application guidelines for internal and external components (and input/output constraints) needed to tailor (cook) each of the
three entrees (applications) to your taste.]
R, (10kn) limita input current to the rectHier.
This current should not exceed an AC peak
value of ± 300jolA. An external resistor may be
placed in series with R, if the input voltage to
the rectifier will exceed ± 3.0V peak (i.e.,
10k X 30011A - 3.0V).
R2 (20kn) limita input current to the variable
gain cell. This current should not exceed an
AC peak value of ± 1401lA. Again, an external
resistor has to be placed in series with R2 if
the input voltage to the variable gain cell
exceeds ± 2.BV (i.e., 20k X 1401lA).

NOTES;
Th. NE572 doff_ ~orn th. 570/57' In the,:
1. There IS no Internal op amp.
2. The attack and release times are programmed separately.

SYSTEM LEVELS OF A
COMPLETE COMPANDING
SYSTEM
Figure 10 demonstrates the compressing and
expanding functions:

[The purpose of these DC biasing equations
is to allow the designer to set the output
halfway between the supply rails for largest
headroom (usually some positive voltage and
ground).]

Coc aOls as an AC shunt to ground to totally
remove the DC biasing resistors from the AC
gain equation.
CF caps are AC signal coupling caps.
CRECT acta as
directly affecta
circuit. There is
fast attack and

THO;!!! (1 IlF/CRECT)(lkHzlfreq.) X 0.2%

the rectHier's filter cap and
the response time of the
a trade-off, though, between
decay times and distortion.

The time constant is: 10k X CRECT

Point A representa a wide dynamic range
signal with a maximum amplitude of + 16dB
and minimum amplitude of -BOdB.
Point B representa the compressor output
showing a 2: 1 reduction in dynamic range
(-4OdB is increased to -20dB, for example).
Point B can also be seen as the dynamic
range of a transmission medium. Transmission noise is present at the -6OdB level from
Point B to Point C.
Point C represents the input Signal to the
expandor.
Point 0 represents the output of the expandor. The signal transformation from Point C to
o represents a 1:2 expansion.

The total harmonic distortion (THO) is approximated by:

-r
-- -

NEI7UItI71ISA571 SYSTEM LEVEL

[t

[ ]2

AELLEVEL

INPUT 10 40

EXMNDOR

v __ COII~

--- 77_
+1_

4.1Y
3.1V

77ImV

----

7._

r

77SpV

_ _ L- n.spv

A
(COIIPfI!SSOR
_OUT)
B

~

~

'ouT

(EXPANDOR
c IN)

D

~

~

::'f:;.~

+11.0
+12.0

+11
+12

0.0

0

-20

-20

-40

-40

-10

-

-10

-10

-

-10

Figure 10. System Levels of a Complete Companding System

December 19B8

4-338

-

ABSLEVEL

DB

...,.....

Signetlcs Linear Products

Application Note

Compandor Cookbook

AN176

WHAT IS COMPANDING??
Shown here are some scope pictures of what
three functions of the compandor look like In
the kitchen, responding to tone bursts of
varying amplitudes.

COMPRESSION 1kHz

EXPANSION 1kHz

COMPANDOR SYSTEM 15kHz

COMPANDOR SYSTEM 1kHz

AUTOMATIC LEVEL CONTROL
(SMALL SIGNAL INPUT)

AUTOMATIC LEVEL CONTROL
(LARGE SIGNAL INPUT)

INPUT

OUTPUT

Figure 11

December 1988

4-339

•

Signetics Linear Products

Application Note

Compandor Cookbook

AN176

APPLICATION BOARD
Shown below is the schematic (Figure 12) for
Signetics' NE570/571 evaluation/demo
board. This board provides one channel of
Expansion and one channel of Compression
(which can be sWitched to Automatic Level
Control).

"*-

+

I~:r

2.2~

20K
4G

SHOWN AS
COMPRESSOR

33K

Roc

(OPTIONAL DE-EMPHASIS)

+

~'O.F
2.2~

-~r

>-o-........- .....-+~+ ~~..':.ER)
IO.F

2.2.F 14

EXPANDOR
INPUT

6

(OPTIONAL

PRE-EMPHASIS)

Figure 12

December 1988

r---.,

ALe

36K

4-340

16

20K

(OPTIONAL DE-EMPHASIS)

12

10
12K

Signetics

NE570/571/SA571
Compandor
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE570/571 is a versatile low cost
dual gain control circuit in which either
channel may be used as a dynamic
range compressor or expandor. Each
channel has a full-wave rectifier to detect the average value of the signal, a
linerarized temperature-compensated
variable gain cell, and an operational
amplifier.

• Complete compressor and
expandor in one IC
• Temperature compensated
• Greater than 110dB dynamic
range
• Operates down to 6Voc
• System levels adjustable with
external components
• Distortion may be trimmed out

The NE570/571 is well suited for use in
cellular radio and radio communications
systems, modems, telephone, and satellite broadcast/receive audio systems.

CIRCUIT DESCRIPTION
The NE570/571 compandor building
blocks, as shown in the block diagram,
are a full-wave rectifier, a variable gain
cell, an operational amplifier and a bias
system. The arrangement of these
blocks in the IC result in a circuit which
can perform well with few external components, yet can be adapted to many
diverse applications.
The full-wave rectifier rectifies the input
current which flows from the rectifier
input, to an internal summing node
which is biased at VREF. The rectified
current is averaged on an external filter
capacitor tied to the CRECT terminal, and
the average value of the input current
controls the gain of the variable gain
cell. The gain will thus be proportional to
the average value of the input signal for
capacitively-coupled voltage inputs as
shown in the following equation. Note
that for capacitively-coupled inputs there
is no offset voltage capable of producing
a gain error. The only error will come
from the bias current of the rectifier
(supplied internally) which is less than
O.1jJA.

PIN CONFIGURATION
D, F, N Packages 1

APPLICATIONS
• Cellular radio
• Telephone trunk compandor570
• Telephone subscriber
compandor - 571
• High level limiter
• Low level expandor - noise gate
• Dynamic noise reduction systems
• Voltage-controlled amplifier
• Dynamic filters

NOTE:
1 SOL· Released

In

Large SO Package Only

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to
o to
o to

16-Pln Cerdip
16-Pin Plastic DIP
16-Pln PlastiC SOL
16-Pin Cerdip
16-Pin Plastic Cerdip

ORDER CODE

+70·C

NE570F

+70·C

NE570N

+70·C

NE571D

+70·C

NE571F

+70·C

NE571N

16-Pln Cerdip

-40·C to + 85·C

SA571F

16-Pin Plastic DIP

-40·C to + 85·C

SA571N

BLOCK DIAGRAM
R3

R2 20K

'G IN

INVERTER IN
R3
20K

O---.....JM,.._--

-,

'OK

NOTE:
VIN avg
IG-2~

C 1N " R,

o--jHl.......- - !

Figure 6. Sfmpllfied Rectifier Schematic

VOUT

V,N

then mirrored with a gain of 2 to become IG,
the gain control current.
TC11861S

NOTES:

GAIN-(
Ie - 140"A
*external components

Figure 4. Basic Compressor

V.

'G

Figure 5. Rectifier Concept

CIRCUIT DETAILS - RECTIFIER
Figure 5 shows the concept behind the full·
wave averaging rectifier. The input current to
the summing node of the op amp, VINR1, is
supplied by the output of the op amp. If we
can mirror the op amp output current into a
umpolar current, we will have an ideal rectifi·
er. The output current is averaged by Rs, CR,
which BErt the averaging time constant, and
November 14, 1986

Figure 6 shows the rectifier circuit In more
detail. The op amp is a one·stage op amp,
biased so that only one output device Is on at
a time. The non·inverting input, (the base of
01), which is shown grounded, is actually tied
to the internal 1.8V VREF. The inverting input
is tied to the op amp output, (the emitters of
05 and Os), and the input summing resistor
Rl. The single diode between the bases of 05
and 06 assures that only one deVice IS on at
a time. To detect the output current of the op
amp, we simply use the collector currents of
the output devices 05 and 06. Os will conduct
when the Input swings positive and 05 can·
ducts when the input swings negative. The
collector currents will be in error by the a of
05 or 06 on negatIVe or positive signal
sWings, respectIVely. ICs such as this have
typical NPN f3s of 200 and PNP f3s of 40. The
a's of 0.995 and 0.975 will produce errors of
0.5% on negatIVe swings and 2.5% on pOSI·
tive sWings. The 1.5% average of these
errors yields a mere 0.13dB gain error.
At very low input signal levels the biwtcurrent
of 02, (typically 50nA), will become slgmflcant
as it must be supplied by 05. Another low
level error can be caused by DC coupling Into
the rectifier. If an ollset voltage exists be·
tween the VIN input pin and the base of 02,
an error current of VOStRl will be generated.
A mere 1mV of ollset will cause an input
current of 100nA which will produce twice the
error of the input bias current. For highest
accuracy, the rectifier should be coupled into
capacitively. At high Input levels the f3 of the
PNP 06 will begin to suller, and there will be
an increasing error until the circuit saturates.

4-345

Saturation can be avoided by IImillng the
current into the rectifier Input to 250j.tA. If
necessary, an external resistor may be
placed in senes with Rl to limit the current to
this value. Figure 7 shows the rectifier accura·
cy vs Input level at a frequency of 1kHz.

.,...--....,--...,---r--...,

RECTIFIER INPUT dBm

Figure 7. Rectifier Accuracy

At very high frequencies, the response of the
rectifier will fall all. The roll·oll will be more
pronounced at lower Input levels due to the
Increasing amount of gain required to switch
between 05 or 06 conducting. The rectifier
frequency response for Input levels of OdBm,
-20dBm, and -40dBm IS shown in Figure B.
The response at all three levels is flat to well
above the audio range.

Signetics Linear Products

Product Specification

NE570j571jSA571

Compandor

y.

!

i

:i
z
:c

"

INPUT

=Od8m

o~--------~.c~
-3

-,

20K

,01(

Y,N

O--"N'r-.....-C

Figure 8. Rectifier Frequency
Response vs Input Level

VARIABLE GAIN CELL
Figure 9 is a diagram of the variable gain cell.
This is a linerarized two·quadrant transconductance multiplier. 01, 02 and the op amp
provide a predistorted drive signal for the gain
control pair, 03 and 0 4, The gain is controlled
by IG and a current mirror provides the output
current.
The op amp maintains the base and collector
of 01 at ground potential (VREF) by controlling
the base of 02. The input current liN
(= V,N/R2) is thus forced to flow through 01
along with the current 110 so ICl = 11 + liN.
Since 12 has been set at twice the value of 11,
the current through O2 is:
12 - (11 + liN)

Y-

NOTE:

Figure 9. Simplified e.G Cell Schematic

This equation is linear and temperature-insensitive, but It assumes ideal transistors.

= 11 -liN = IC2.

The op amp has thus forced a linear current
swing between 01 and 02 by providing the
proper drive to the base of 02, This drive
signal will be linear for small signals, but very
non-linear for large Signals, since it is compensating for the non-linearity of the differential pair, 0 1 and 02, under large signal conditions.
The key to the circuit is that this same
predistorted drive signal is applied to the gain
control pair, 03 and 0 4, When two differential
pairs of transistors have the same Signal
applied, their collector current ratios will be
identical regardless of the magnitude of the
currents. This gives us:

plus the relationships IG = IC3 + IC4 and
lOUT = 1C4 - IC3 will yield the multiplier transfer
function,

November 14, 1986

2mY
'mY

operating level of OdBm, a 1mV offset will
yield 0.34% of second harmonic distortion.
Most circuits are somewhat better than this,
which means our overall offsets are typically
about Y2mV. The distortion is not affected by
the magnitude of the gain control current, and
it does not increase as the gain is changed.
This second harmonic distortion could be
eliminated by making perfect transistors, but
since that would be difficult, we have had to
resort to other methods. A trim pin has been
provided to allow trimming of the internal
offsets to zero, which effectively eliminated
second harmonic distortion. Figure 11 shows
the simple trim network required.
Vee

INPUT LEVEL (dBm)

Figure 10. e.G Cell Distortion
vs Offset Voltage
If the transistors are not perfectly matched, a
parabolic, non-linearity is generated, which
results in second harmonic distortion. Figure
10 gives an indication of the magnitude of the
distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the magnitude of the offset and
the input level. Saturation of the gain cell
occurs at a + 8dBm level. At a nominal

4-346

....

o>---'\""""'''_~.~~

To THO T1Im

3.V

20K

,

T

'"20OpF

.......
Figure 11. THO Trim Network

Product Specification

Signetics Linear Products

NE570j571jSA571

Compandor

Figure 12 shows the noise performance of
the dG cell. The maximum output level before clipping occurs in the gain cell is plotted
along wIth the output noise in a 20kHz
bandwidth. Note that the noise drops as the
gain is reduced for the first 20dS of gain
reduction. At high gains, the sIgnal to noise
ratio is 90dS, and the total dynamic range
from maximum signal to minimum noise

IS

Vee

R - .ELEeT FOR

J

3OV _ _ _ _ _
_

lOOK

"

..

~ TOPIH 30R,4

11 OdS.
Control signal feedthrough is generated in the
gain cell by imperfect device matching and
mismatches in the current sources, 11 and 12,
When no input sIgnal is present, changing IG
will cause a small output signal. The distortion
trim is effective In nulling out any control
signal feedthrough, but In general, the null for
minimum feedthrough will be different than
the null in distortion. The control sIgnal feedthrough can be trimmed independently of
distortion by tYing a current source to the dG
input pin. This effectively trims 11. FIgure 13
shows such a tnm network.

I5

_40

5
0

"....

Figure 13. Control Signal Feedthrough
Trim

•

OPERATIONAL AMPLIFIER
The main op amp shown in the chip block
dIagram is equivalent to a 741 with a 1MHz
bandwidth. Figure 14 shows the basic circuit.
Split collectors are used in the input pair to
reduce gM, so that a small compensation
capacItor of just 10pF may be used. The
output stage, although capable of output
currents in excess of 20mA, is bIased for a
low quiescent current to conserve power.
When driving heavy loads, this leads to a
small amount of crossover distortion.

Figure 14. Operational Amplifier

RESISTORS

-eo
_00

_'0_40
0

come very SIgnificant. Figure 15 shows the
effects of temperature on the diffused resistors whIch are normally used In Integrated
CirCUItS, and the ion-implanted resistors which
are used in this Circuit. Over the cntical O°C to
+ 70°C temperature range, there is a 10-to-1
improvement In dnft from a 5% change for
the dIffused reSIstors, to a 0.5% change for
the implemented resistors. The implanted
resistors have another advantage in that they
can be made 1t7 the size of the diffused
resistors due to the higher resistivIty. This
saves a significant amount of chip area.

NOISE IN
2Ot--I---OVo
BUFFER

I

CA

"" 1pF

J

(4,12)

L...,...._ _-,-_--'

(1,15)

:2 2/"f
V2

100~f

:'3 3K(3,13)

o---J r'-'VVV---+

---t--~--'lN.,-- T 15V

(16)

---- -_._-----------------_._---- ---------_._.- - - - - - - - - - - - - _ . _ - - _ . _ - - - - - - - - - - - - - - - - '

AUDIO SIGNAL PROCESSING IC
COMBINES VCA AND FAST
ATTACK/SLOW RECOVERY
LEVEL SENSOR
In high-performance audiO gain control appilcations, It IS desirable to Independently control the attack and recovery time of the gain
control signaL This IS true, for example, In
compandor applicatIons for nOise reduction
In high end systems the Input signal IS usually
spilt Into two or more frequency bands to
optimize the dynamic behaVior for each band
This reduces low frequency distortion due to
control signal ripple, phase distortion, high
frequency channel overload and nOise modulation Because of the expense In hardware,
multiple band signal processing up to now
was limited to professional audiO applications.
With the Introduction of the Signetics NE572
this high-performance nOise reduction concept becomes feasible for consumer hi fl
applications The NE572 IS a dual channel
garn control IC Each channel has a linearIzed, temperature-compensated garn cell and
an Improved level sensor In conjunction with
an external low nOise op amp for current-tovoltage converSion, the VCA features low
distortion, low nOise and Wide dynamic range

October 7, 1987

The novel level sensor which provides garn
control current for the VCA gives lower gain
control npple and Independent control of fast
attack, slow recovery dynamiC response. An
attack capacitor CA with an Internal t Ok
resistor RA defines the attack time fA The
recovery time tR of a tone burst IS defined by
a recovery capacitor CR and an Internal 10k
resistor RR TYPical attack time of 4ms for the
high-frequency spectrum and 40ms for the
low frequency band can be obtained with
0.1/lF and 1.0/lF attack capacitors, respectively RecovelY time of 200ms can be obtained With a 4 7/lF external capacitor. With
the recovery capacitor added In ihe level
sensor, tne garn control npple for low frequency signals IS much lower than that of a
simple RC npple filter. As a result, the residual third harmonic distortion of low frequency
signal In a two quad transconductance amplifier IS greatly Improved With the 1 O/lF attack
capacitor and 4 7/lF recovery capacitor for a
1DOHz signal, the third harrnonlc distortion IS
Improved by more than 10dB over the simple
RC npple filter With a single 1 O/lF attack and
recovery capaCitor, while the attack time
remains the same
The NE572 IS assembled rn a standard 16-pin
dual In-line plastic package and In oversized

4-350

SOL package. It operates over a WIde supply
range from 6V to 22V. Supply current is less
than 6mA. The NE572 is designed for consumer application over a temperature range
o - 70°C. The SA572 is intended for applications from -40°C to + 85°C.

NE572 BASIC APPLICATIONS

Description
The NE572 consists of two lineanzed, temperature-compensated gain cells (Ll.G), each
With a tull-wave rectifier and a buffer amplifier
as shown 111 the block diagram. The two
channels share a 2.5V common bias reference denved from the power supply but
otherWise operate Independently. Because of
Inherent low distortion, low nOise and the
capability to IIneanze large Signals, a Wide
dynamiC range can be obtained. The buffer
amplifiers are prOVided to permit control of
attack time and recovery time independent of
each other. Partitioned as shown in the block
diagram, the IC allows flexibility in the design
of system levels that optimize DC shift, npple
distortion, tracking accuracy and nOise floor
for a Wide range of application requirements.

Product Specification

Signetlcs Linem Products

NE/SA572

Programmable Analog Compandor

Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs
0 1 - 02 and 03 - 0 4 are both tied to the
output and inputs of OPA A1' The negative
feedback through 01 holds the VSE of
01 - 02 and the VSE of 03 - 0 4 equal. The
following relationship can be derived from the
transistor model equation in the forward active region.

v+

+

(VSE = Vr In IC/IS)

= Vr In ('1 ;slIN ) - Vr In ('2

-II~-liN )(2)

VIN
whereIIN=A1
A1 = 6.8kn
11 - 140llA
12 - 280/lA
10 is the differential output current of the gain
cell and IG is the gain control current of the
gain cell.
It all transistors 01 through 04 are of the
same size, equation (2) can be simplified to:

The first term of Equation 3 shows the
multiplier relationship of a linearized two
quadrant transconductance amplifier. The
second term is the gain control teedthrough
due to the mismatch of devices. In the design,
this has been minimized by large matched
devices and careful layout. Offset voltage is
caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be trimmed out by feeding a current
source within ± 25/lA into the THO trim pin.

October 7, 1987

V,n

Figure 1. Basic Gain Cell Schematic
The residual distortion is third harmonic distortion and is caused by gain control ripple. In
a compandor system, available control of fast
attack and slow recovery improve ripple distortion significantly. At the unity gain level of
100mV, the gain cell gives THO (total harmonic distortion) of 0.17% typo Output noise
with no input signals is only 61lV in the audio
spectrum (10Hz - 20kHz). The output current
10 must feed the virtual ground input of an
operational amplifier with a resistor from output to inverting input. The non-inverting input
of the operational amplifier has to be biased
at VREF if the output current 10 is DC coupled.

Rectifier
The rectifier is a full-wave design as shown in
Figure 2. The input voltage is converted to
current through the input resistor A2 and
turns on either Os or 06 depending on the

4-351

Signal polarity. Oeadband of the voltage to
current converter is reduced by the loop gain
of the gain block A2. If AC coupling is used,
the rectifier error comes only from input bias
current of gain block A2. The input bias
current is typically about 70nA. Frequency
response of the gain block A2 also causes
second-order error at high frequency. The
collector current of 06 is mirrored and
summed at the collector of Os to form the full
wave rect~ied output current IR. The rectifier
transfer function is
VIN-VREF
IR---A2

(4)

If VIN is AC-coupled, then the equation will be
reduced to:
VIN(AVG)
IRAC----

A2

Signetics Linear Products

Product Specification

Programmable Analog Compandor

NE/SA572

The internal bias scheme limits the maximum
output current IR to be around 300pA. Within
a ± 1dB error band the input range of the
rectifier is about 52dB.

Buffer Amplifier

VREF

In audio systems, it is desirable to have fast
attack time and slow recovery time for a tone
burst input. The fast attack time reduces
transient channel overload but also causes
low-frequency ripple distortion. The low-frequency ripple distortion can be improved with
the slow recovery time. If different attack
times are implemented In corresponding frequency spectrums in a split band audio system, high quality performance can be
achieved. The buffer amplifier is designed to
make this feature available with minimum
external components. Referring to Figure 3,
the rectifier output current is mirrored into the
input and output of the unipolar buffer amplifier As through Oa, 09 and 0 10. Diodes D11
and D12 improve tracking accuracy and provide common-mode bias for As. For a positive-going input signal, the buffer amplifier
acts like a voltage-follower. Therefore, the
output impedance of As makes the contribution of capacitor CR to attack time insignificant. Neglecting diode Impedance, the gain
Ga(t) for LlG can be expressed as follows:

0------1

,--------- -----j
I

I

I

R2

I
I
I
I
I
I

06

I

I
Vm

L______________

I
I
I
I
I

~

Figure 2. Simplified Rectifier Schematic

-t
---1---t"--...,

v+

Ga(t)

= (Ga'NT -

GaFNd eTA + GaFNL

010

Ga'NT = Initial Gain
GaFNL = Final Gain
TA
IR2

= RA

• CA = 10k' CA

where T A is the attack time constant and RA
is a 10k Internal resistor. Diode D15 opens the
feedback loop of As for a negative-going
signal if the value of capacitor CR is larger
than capacitor CA. The recovery time depends only on CR • RR. If the diode impedance is assumed negligible, the dynamic gain
GR (t) for LlG is expressed as follows.

10K

015

-t
10K

X2

IRl

01.

r

INT - GR FNLl e TR + GR FNL

where TR is the recovery time constant and
RR is a 10k internal resistor. The gain control
current is mirrored to the gain cell through
014. The low level gain errors due to input
bias current of A2 and As can be trimmed
through the tracking trim pin into As with a
current source of ± 3p.A.

CR
TRACKING

TRIM

I

Figure 3. Buffer Amplifier Schematic

October 7, 1987

= (GR

TR = RR • CR = 10k' CR

012

CA

GR(t)

4-352

Signetics Linear Products

Product Specification

Programmable Analog Compander

NE/SA572

R3

R4

+VB

4-~Ar~------~~-----,

17 3K

CIN2

CONI
VIN

(7.9)

o---j

2

RI
68K

>--+-----------+------0 YOUT

Roc,. ROC2. and CDC form a DC feedback for
A,. The output DC level of A, IS given by

Vaoc

= VREF

( 1 + Roc, R+.RoC2 )
91
(7.

-VB' (

ROC, + ROC2 )

R.

(8)

1

CIN2
22.u F

CIN3
22j.1F

The zener diodes D, and D2 are used for
channel overload protection.

Basic Compandor System
The above basIc compressor and expandor
can be applied to systems such as tape/disc
nOise reduction. digital audio. bucket brigade
delay lines. Additional system design techniques such as band limiting. band splitting.
pre-emphasis. de-emphasIs and equalization
are easy to incorporate. The IC is a versatile
functional block to achieve a high performance audio system. Figure 6 shows the
system level diagram for reference.

October 7. 1987

33K

"2
(3,13)

Figure 5. Basic Compressor Schematic

4-354

Signetics Uneo r Products

Product Specification

NE/SA572

Programmable Analog Compandor

[
VRMS

COMPRESSION

f

[

30.

5476MY
400MV

100 MY

10MY

1MV

l00,.,V

REL LEVEL
dB

ABSLEVEl

dBM

OUT

~

INPUT TO .o.G
AND REef

/

-----

-----

~

/

~

~

10/JY

Figure 6. NE572 System Level

October 7, 1987

r

EXPANDOA

IN

4-355

+2954

+1176

+1477
+120

-s 78

00

-1778

-20

-3778

-40

-5778

-60

-77 78

-80

-9778

-300

AN175

Signetics

Automatic Level Control Using
the NE572
Application Note
Linear Products

NE572 AUTOMATIC LEVEL CONTROL

2.z,.F

lOOK

9.1K

9.1K

R.

:>~l~~~~~~D~C~~--~+g~vmn

2.2Jd'

TO THD---...,.,.,..----1---=-I

TRIM PIN

2.2,ICF

lK

OF 572
PINS
TC07272S

Roc, + RDC2 )

VOOC=VREF ( 1 + - R- , -

OUTPUT LEVEL _ ( R'R'I.)
2R3

(

V'N

WHERE

R, - lOOk
ROC1 "" R[)C2 "" 91k
VREF - 2 5V

WHERE

R, - 6 8k (Internal)
R2- 33k
R,-173k

)

VIN(avg)

I. = ,.01lA
ATTACK TIME = (10k) C.
RECOVERY TIME - (10k)

c"

TO LIMIT THE GAIN AT VERY LOW INPUT LEVELS. ADD Rx

GAIN MAX _

~x R2 X Ie

1r

(FOR SINE WAVES)

2R,
NOTE:

Pin numbers are for side A of the NE572.

December 1988

VIN

V'NI""Ol - 2'112=111

4-356

Signetics

NEjSA575
Low Voltage Compandor
Product Specification

Linear Products

DESCRIPTION

APPLICATIONS

THE NE/SA575 is a precision dual gaincontrol circuit designed for low voltage
applications. The NE575's channel 1 is
an expandor, while channel 2 can be
configured either for expand or, compressor, or automatic level controller
(ALe) application.

•
•
•
•
•
•
•
•
•

FEATURES
• Operating voltage range from 3V
to 7V
• Reference voltage of
100mVRMS = OdB
• One dedicated summing op amp
per channel and two extra
uncommitted op amps
• 600.11 drive capability
• Single or split supply operation
• Wide input/output swing
capability

PIN CONFIGURATION

Portable communications
Cellular radio
Cordless telephone
Consumer audio
Portable broadcast mixers
Wireless microphones
Modems
Electric organs
Hearing aids

0 1 and N Packages

•
TOP VIEW

NOTE,

ORDERING INFORMATION
DESCRIPTION

1 AvaIlable

TEMPERATURE RANGE

In

large SO package only

ORDER CODE

20-Pin Plastic DIP

O·C to +70·C

NE575N

20-Pin Plastic SOL

O·C to +70·C

NE575D

20-Pln Plastic DIP

-40·C to + 85·C

SA575N

20-Pln Plastic SOL

-40·C to +85·C

SA575D

ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL

PARAMETER

UNIT
NE575

Vce

Supply voltage

TA

Operallng ambient
temperature range

TSTG

Storage temperature range

August 23, 1988

SA575

8

8

V

o to +70

-40 to +85

·C

-65 to + 150 -65 to + 150

4-357

·C

853-1119 94281

Signetics Linear Products

Product Specification

low Voltage Compandor

NE/SA575

BLOCK DIAGRAM

VOUT~R4

h

C3

IO"F

VAEF

~+~~~--~------~
RS

VOUT

RIO

lOOk

200

RECTIFIER
3.9k

-::- GND

17

ClO

R9

10,uF +

100k

-::- GND

C6

IO"F

V,N

14

o--t 1-+,.---......

~

13
R8

30k

12

R7
30k

11
GAIN CELL

See NOTES In back of this book for additional drawings.

August 23, 1988

4-358

Signetlcs Linear Products

Product Specification

Low Voltage Compandor

NE/SA575

ELECTRICAL CHARACTERISTICS TYPical values are at TA ~ 25"C. Minimum and Maximum values are for the full operating
temperature range 0 to 70"C for NE575, -40 to + 85"C for SA575 Vee ~ 5V, unless
otherwise specified Both channels are tested In the Expandor mode (see Figure 1)
LIMITS
PARAMETER

SYMBOL

TEST
CONDITIONS

NE575

SA575
Max

Min

Typ

UNIT

Min

TYP

Max

3

5

7

3

5

7

V

3

4

55

3

4

5.5

mA

24

25

26

24

25

26

V

012

10

0.12

15

%

6

20

6

30

IlV

For compandor, Including summing amplifier
Vee

Supply voltage 1

lee

Supply current

No signal

VREF

Reference voltage 2

Vee

RL

Summing amp output
load

THD

Total harmonic distortion

ENa

Output voltage nOise

OdB

Unity gain level

Vas

Output voltage offset
Output DC shift
Tracking error relative to
OdB
Crosstalk

~

5V

10
1kHz, OdB BW

~

35kHz

BW ~ 20kHz, Rs~on

10

kn

1kHz

-10

10

-1.5

15

dB

No signal

-100

100

-150

150

mV

No signal to OdB

-50

50

-100

100

mV

1kHz, + 6dB to - 30dB

-05

0.5

-10

1.0

dB

-65

dB

1kHz, OdB, CREF

~

-80

220fJF

-65

-80

For operational amplifier
RL

~

Va

Output sWing

RL

Output load

10kn

CMR

Input common-mode
range

0

CMRR

Common-mode rejection
ratio

60

Vee -0.4 Vee- 0.2

1kHz

VIN~O

16

Input bias current

Vas

Input offset voltage

AvaL

Open-loop gain

RL

SR

Slew rate

5V to 45V

V

Vee-O 4 Vee-O 2

600

600
Vee
80

0
60

-03

03

n
Vee
80

-0.5

V
dB

05

IlA
mV

3

3

10kn

80

80

dB

Unity gain

1

1

VIIlS
MHz

~

GBW

Bandwidth

3

3

ENI

Input voltage nOise

BW

Unity gain
20kHz

2.5

2.5

IlV

PSRR

Power supply rejection
ratio

1kHz, 250mV

60

60

dB

~

NOTES:
1 Operation down to Vee = 2V IS pOSSible, but performance IS Significantly reduced See curve In Figure 5
2 Reference voltage, VREF, IS tYPically at 1/2Vcc

DESCRIPTION OF OPERATION
ThiS section desCribes the basIc subsystems
and applications of the NE/SA575 Compandor
More theory of operation on compandors can
be found In AN174 and AN176. The typical
applications of the NE575 low voltage compandar In an Expandor (1'2), Compressor (2.1) and
Automatic Level Control (ALC) funcllon are
explained. These three CirCUit configurations
are shown In Figures 1, 2, 3 respectively
The NE575 has two channels for a complete
companding system. The left channel A can be
configured as a 1'2 Expandor while the right
channel B can be configured as either a 2'1
Compressor, a 1:2 Expandor or an ALC. Each
channel consists of the baSIC companding
August 23, 1988

bUilding blocks of rectifier cell, variable gain
cell, summing amplifier and VREF cell In addllion, the NE575 also has two additional high
performance uncommitted op amps which can
be utilized for applications such as filtering, preemphasIs I de-emphasIs or buffering

C1, C2, RtO, R1t, CtO and C11 so that the
response can be tailored for each Individual
need The components as speCified are SUitable for the complete audiO spectrum from
20Hz to 20kHz A CirCUit schematiC for vOice
(300Hz to 3kHz) IS shown In Figure 6

Figure 4 shows the complete schematiC for the
applications demo board Channel A IS configured as an expandor while channel B IS configured so that It can be used either as a compressor or as an ALC CirCUit The SWitch S t toggles
the CirCUit between compressor and ALC mode
Jumpers J t and J2 can be used to either
Include the addilional op amps for Signal conditioning or exclude them from the Signal path
Bread boarding" space IS proVided for Rt, R2,

The most common configuration IS as a unity
gain non-Inverting buffer where R1, Ct, C2,
RtO, C10 and Ct1 are eliminated and R2 and
Rtt are shorted Capacitors C3, C5, C8 and
C12 are for DC blocking, and R4 and R8
proVide termination (for the capacitors) In systems where the Inputs and outputs are AC
coupled, these capacitors and resistors can be
eliminated. Capacitors C4 and C9 are for setling the attack and release time constant.

4-359

•

Signetics linear Products

Product Specification

NEjSA575

Low Voltage Compandor

CB IS for decoupling and stabilizing the voltage
reference circuit. The value of CB should be
such that It will offer a very low Impedance to
the lowest frequencies of interest. Too small a
capacitor will allow supply ripple to modulate
the audio path. The better filtered the power
supply, the smaller this capacitor can be. R5
and R 12 provide DC reference voltage to the
amplifiers of channel B. RB and R7 provide a
DC feedback path for the summing amp of
channel B while C7 IS a short-circuit to ground
for signals. C14 and C15 are for power supply
decoupling. C14 can also be eliminated If the
power supply is well regulated with very low
nOise and ripple. Figure 5 shows the PC board
layout of the applications demo board.

DEMONSTRATED
PERFORMANCE
The applications demo board was built and
tested for a frequency range of 20Hz to 20kHz
with the component values as shown in Figure
4 and Vce = 5V. In the expandor mode, the
typical input dynamic range was from -34dB to
+12dB where OdB IS equal to 100mVRMS. The
typical unity gain level measured at OdB @
1kHz input was ± 0.5dB and the tYPical tracking
error was ± 0.1 dB for input range of -30 to
+10dB.
In the compressor mode, the tYPical input
dynamic range was from -42dB to + lBdB with
a tracking error of ± 0.1 dB and the typical unity
gain level was ± 0.5dB.
In the ALC mode, the typical input dynamic
range was from -42dB to + BdB with typical
output deviation of ± 0.2dB about the nominal
output of OdS. For inputs greater than + 9dS In
ALC configuration, the summing amplifier
sometimes exhibits high frequency oscillations.
There are several solutions to this problem.
The first is to lower the values of R7 and R8 to
20kn each. The second is to add a current
limiting resistor in series with C13 at Pin 13. The
third is to add a compensation capacitor of
about 22 to 30pF between the input and output
of summing amplifier (Pins 12 and 14). With any
one of the above recommendations, the

August 23, 198B

typical ALC mode input range increased to
+ lBdB Yielding a dynamiC range of over BOdB.

EXPANDOR
The typical expandor configuration is shown in
Figure 1. The variable gain cell and the rectifier
cell are in the signal input path. The VREF is
always 1/2 of Vee which biases the summing
amplifier at 112 Vee to provide the maximum
headroom without clipPing. The OdS ref IS
100mV RM S. The Input is AC coupled through
C5, and the output IS AC coupled through C3. If
In a system the inputs and outputs are AC
coupled, then C3, C5, R3 and R4 can be
eliminated thus requiring only one external
component, C4. The variable gain cell and
rectifier cell are DC coupled so any offset
voltage between Pins 4 and 9 Will cause small
offset error current In the rectifier cell. This will
affect the accuracy of the gain cell. This can be
improved by uSing an extra capacitor from the
input to Pin 4 and eliminating the DC connection between Pins 4 and 9.
The expandor gain expression and the attack
and release time constant is given by Equation
1 and Equation 2 respectively.
Equation 1.
.
Expandor gain
where

4VIN(avg)
= 3.9kX 100"A

VIN(avg)

= O.901VIN(RMS)
Equation 2.

T =

10kX CRECT = 10kX C4

COMPRESSOR
The typical compressor configuration is shown
in Figure 2. In this mode, the rectifier cell and
variable gain cell are In the feedback path. RB
and R7 proVide the DC feedback to the summing amplifier. The input IS AC coupled through
C12 and output is AC coupled through CB. In a
system With inputs and outputs AC coupled, CB,
C12, RB and R9 could be eliminated and only
R5, RB, R7, C7 and C13 would

4-360

be required. If the external components R5, RB,
R7 and C7 are eliminated, then the output of
the summing amplifier will motor-boat in absence of signals or at extremely low Signals.
This is because there is no DC feedback path
from the output to input. In the presence of an
AC signal this phenomenon is not observed
and the circuit Will appear to function properly.
The compressor gain expression and the attack
and release time constant is given by Equation
3 and Equation 4 respectively.
Equation 3.
Compressor Gain

=

[

3.9kX 100"A ]1,12
4VIN(avg)
Equation 4.

TR

= TA = 10kX CRECT = 10kX C4

AUTOMATIC LEVEL CONTROL
The tYPical Automatic Level Control circuit
configuration is shown In Figure 3. It can be
seen that it is quite similar to the compressor
schematic except that the input to the rectifier
cell IS from the input path and not from the
feedback path. The input is AC coupled through
C12 and C13 and the output IS AC coupled
through CB. Once again, as in the previous
cases, if the system input and output Signals
are already AC coupled, then C12, C13, CB, RB
and R9 could be eliminated. Concerning the
compressor, removing R5, RB, R7 and C7 Will
cause motor-boating in absence of signals.
CeoMP IS necessary to stabilize the summing
amplifier at higher input levels. ThiS circuit
provides an Input dynamic range greater than
BOdS with the output within ± O.5dS tYPical. The
necessary deSign expressions are given by
Equation 5 and Equation B respectively.
Equation 5.
ALC gain

3.9kX 1001'A

=- - - 4VIN(avg)

Equation B.
TR

= TA = 10kX CRECT = 10kX C9

Signetics

Section 5
Data Communications

Linear Products

INDEX
LINE DRIVERS/RECEIVERS
Symbols and Definitions for line Dnvers ......... . . .. . ... .......... . .. .
5-3
AM26LS30
Dual DifferentIal RS-422 Party LIne/Quad Single-Ended RS-423 line
5-4
Dnver .......................................................... .
5-12
AM26LS31
Quad HIgh-Speed DifferentIal Line Dnver....... . .... ... . .
AM26LS32/33
Quad HIgh Speed Differential Line Receivers. ........... . ..... .
5-18
5-22
MC1488
Quad Line Dnver....................................... .. . .. .... . . . . .
Quad line ReceIvers.................... ....... ..... ........ ........ . 5-26
MC1489/A
5-29
AN113
USIng the MC1488/1489 Line Dnvers and ReceIvers ..... .
5-32
NE5170
Octal Line Dnver................................. .... .... . ... ..... . .
5-39
NE5180/81
Octal LIne ReceIver......... ............... ............ ... .... . ..
MODEMS
NE5050
AN1951
NE5080
NE5081
AN195
AN1950

FIBER OPTICS
NE5210
NE/SA5211
NE/SA/SE5212
NE/SA5214
NE/SA5217

Power line Modem ....................................... .......... .... ..
NE5050: Power Line Modem Application Board Cookbook.
High-Speed FSK Modem TransmItter (IEEE 802.4) . ........ ... . ..
HIgh-Speed FSK Modem ReceIver (IEEE 802.4).............. .... ..
ApplicatIons Using the NE5080/5081 .............. ..... ..... ... . .. .
Application of NE5080 and NE5081 WIth Frequency DevIatIon
Reduction ............... .......... .................... ....... ... ... . ..

5-44
5-50
5-78
5-82
5-86

Translmpedance AmplifIer.... .......................... ..
Translmpedance Amplifier ................................... .
Translmpedance AmplifIer................... ............ ... . .......... .
Postampllfler wIth LInk Status IndIcator..... .......... ... .... ..
Postampllfler wIth link Status IndIcator ........ ..... ..... . .

5-97
5-111
5-125
5-139
5-146

5-94

•

Signetics

Symbols and Definitions for
Line Drivers

Linear Products

Current Into or Out of Slew
Control Pin (ISLEW)
Differential Output Voltage (Vo
or '10 , VT or 'IT)
For a differential line driver (i.e., an RS-422
driver) this IS the dlfferenllal output voltage for
an Input voltage which IS a logic HIGH (Vo) or
LOW (Vo) Vo IS usually measured with no
applied output load while VT IS the differential
output voltage with a specified output load.

Enable
For line drivers and receivers having an
ENABLE (or ENABLE) Input, the application
of a specified logic voltage to this Input will
force the outputs Into a high resistance (HighZ) state. In this state, the circuit has a minimal
loading effect on the transmission or bus line
being driven by the output.

Failsafe (FS)
For line receivers having a FAILSAFE (FS)
Input, the application of specified voltages to
this Input will force the outputs to correspondIngly specified logic states, VOFS (defined
below), when fault conditions occur on the
transmission line.

Failsafe Output Voltage (VOFS)
For line receIVers' the voltage to which the
outputs are forced when specified fault conditions occur on the transmission line and when
a specified voltage IS applied to the FAILSAFE (FS) Input.

Hysteresis (VH)
For line receivers: the difference between the
high and low threshold voltages, VTH and VTl
(defined below).

Input Current (liN)
For a line receiver' the current flowing Into the
transmission line Input at a specified Input
voltage.

Input Clamp Voltage (VeLl
For a line driver: the Input voltage applied to
an Input below which the driver clamps this
voltage. VCl IS specified for a particular current flowing from the driver Into the voltage
source.

Input High Current (IIH)
The current flowing Into or out of a LogiC Input
when a specified LogiC HIGH voltage IS
applied to that Input (2.7V).

December 1988

Input High Current (II)

Output High Voltage (VOH)

The current Into or out of a Logic input when
Vee IS applied to that Input (S.SV).

The HIGH voltage at an output (for a driver or
receiver) for specified load conditions, I.e., Rl
or lOUT, and Input voltages.

Input High Threshold Voltage
(VTH)
For a line receiver: the differential Input voltage at the transmission line Input above
which the output IS In a defined logiC state.

Input High Voltage (VIH)
The range of Input voltages recognized by a
logiC Input as a logiC HIGH.

Input Low Current (IlL)
The current flOWing Into or out of a logiC Input
when a specified logiC LOW voltage IS applied
to that Input.

Input Low Threshold Voltage
(VTL)
For a line receiver: the differential Input voltage below which the output IS In a defined
logiC state

Input Low Voltage (VIL)

Output Low Voltage (VOL)
The LOW voltage at an output (for a driver or
receiver) for specified load conditions, I.e., Rl
or lOUT, and Input voltages.

Output Leakage Current (Ix)
The current flowing Into or out of an output
when no power is applied to the circuIt. ICEX is
specified at a particular applied output voltage and Input conditions.

Output Resistance (RoUT)
For a line driver: the output resistance over a
specified output voltage range.

Output Short-Circuit Current (Is)
The current flowing Into or out of an output
when the output is connected to the generator circuit ground for a line receiver or dlgijal
ground for a line driver.

The range of input voltages recognized by a
logiC Input as a logiC LOW.

Output Unbalance Voltage
(IvOHI-lvoLI, IvTI-IVT~

Input Resistance (RIN)

For a line driver: the difference between the
absolute values of VOH and VOL or VT and VT.

For a line receiver' the DC resistance of the
transmission line Input over a specified Input
voltage range.

Mode
For line dnvers haVing a MODE Input the
application of specified voltages to this Input
will force the driver outputs to comply With
correspondingly specified EIA transmission
standards, e g., RS-232 or RS-423.

Negative Power Supply Current
(lEE)
Open-Circuit Input Voltage
(Vloe)
For a line receiver the voltage to which the
transmission line Input of the CircUit reverts
when no external connection IS made at this
Input.

Output Current High-Z (10)
The current flOWing Into or out of an output
when that output IS In a Hlgh-Z state (see
ENABLE definition). 10 IS specified at a particular applied output voltage.

5-3

Output Offset Voltage (Vos or
'los)
For a differential line driver, I.e. RS-422, the
difference between the actual voltage at the
center of the output load and the generator
CircUit ground. VOS is measured With VT at the
output and VOS With VT at the output.

Positive Power Supply Current
(Icc)
Propagation Delay (tpxx)
The time delay between specified reference
pOints on the input and output waveforms of a
line driver or receiver. The symbol X can be
H, L or Z specifying HIGH, LOW or HlQh-Z,
respectively; I.e, tplZ IS the propagation delay
for the output of a line dnver to change from
an output LOW to a High-Z state after the
application of a signal to the ENABLE Input.

Rise and Fall Times (tR and tF)
For a line dnver: the time delays between the
10% and 90% pOints on the rising and failing
output waveforms following a change in the
logiC voltage at the Input.

•

AM26LS30

Signetics

Dual Differential RS-422 Party
Line / Quad Single-Ended
RS-423 Line Driver
Linear Products

Preliminary Specification
PIN CONFIGURATION

DESCRIPTION

FEATURES

The AM26LS30 is a line driver designed
for digital data transmission. A mode
control input provides a choice of operation either as two differential line drivers
which meet all the reqUIrements of EIA
Standard RS-422 or as four Independent
single-ended RS-423 line drivers.

• Dual RS-422 line driver or quad
RS-423 line driver

In the differential mode, the outputs
have individual 3-State controls. In the
high impedance state, these outputs Will
not clamp the line over a common mode
transmission line voltage of ± 10V. A
typical full duplex system consists of the
AM26LS30 differential line driver and up
to twelve AM26LS32 line receivers, or
the AM26LS32 line receiver and up to
thirty-two AM26LS30 differential drivers.

• Low Icc and lEE power
consumption
- RS-422 differential mode:
35mW/driver typ
- RS-423 single-ended mode:
26mW/driver typ

A slew control pin allows the use of an
external capacitor to control slew rate
for suppression of near-end cross talk to
receivers In the cable.
The AM26LS30 IS constructed uSing
high speed oXide Isolated bipolar processing.

• Driver outputs do not clamp line
with power off or in high
impedance state
• Individual 3-State controls when
used in differential mode

• Individual slew rate control for
each output
• 50n transmission line drive
capability (RS-422 into virtual
ground)
• Low current PNP inputs
compatible with TTL, MOS and
CMOS
• High capacitive load drive
capability
• Exact replacement for OS16/3691
• High speed oxide isolated bipolar
processing

ORDERING INFORMATION
DESCRIPTION
16-Pln PlastiC DIP
16-Pm PlastiC SO

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70°C

AM26LS30CN

+70°C

AM26LS30CD

16-Pm PlastiC DIP

- 40°C to + 85°C

16-Pm PlastiC SO

-40°C to + 85°C

AM26LS30lD

16-Pm PlastiC DIP

-55°C to + 125°C

AM26LS30MN

16-Pm Ceramic DIP

-55°C to + 125°C

AM26LS30MF

December 1988

D, F and N Packages

AM26LS30lN

5-4

FUNCTION TABLE
INPUTS

OUTPUTS

A (D) B (C)

A (D) B (C)

MODE
0

0

0

0

1

0

0

1

Z

Z

0

1

0

1

0

0

1

1

Z

Z

1

0

0

0

0

1

0

1

0

1

1

1

0

1

0

1

1

1

1

1

Preliminary Specification

Signetics Linear Products

Dual Differential RS-422 Party Line/
Quad Single-Ended RS-423 Line Driver

AM26LS30

BLOCK DIAGRAM
LOGIC FOR AM26LS30 WITH

LOGIC FOR AM2IILS3O WITH

MODE CONTROL HIGH (R5-4231

MODE CONTROL LOW (118-422)

~

_

INPUT A

-V_

INPUTB

SRCONTROLA
OUTPUTA

ENABLEB~
INPUT A

~ SR CONTROL B

-V-

SRCONTROLA
OUTPUT A
OUTPUTS
SRCONTROLB

OUTPUTB

__ ~ SR CONTROL C

INPUTC

-V-

OUTPUTC
INPUTD

~ SR CONTROL D

INPUT 0

-V-

vcc - v.. __

ABSOLUTE MAXIMUM RATINGS

Vce

Supply voltage
V+

VEE

V-

VIN

Input voltage

VOUT

Output voltage (Power Off)

PD

Power dissipation

TA

Ambient temperature range
AM26LS31C

vcc - GND--

v.. __

(Above which the useful hfe may be Impaired)
RATING

UNIT

7

V

-7

V

- 5V to Vee

V

± 13.5

V

600

mW

o to +70

·C

AM26LS31I

-40 to +85

·C

AM26LS32M

-55 to +125

·C

-65 to +150

·C

300

·C

TSTG

Storage temperature range

TSOLD

Lead soldenng temperature (10 seconds)

POWER DISSIPATION TABLE
PACKAGE

POWER DISSIPATION

DERATING
FACTOR

ABOVE
TA

N

1,488mW

11.9mW/"C

25°C

D

1.262mW

10.lmW/"C

25°C

F

1.250mW

10.0mW/oC

25°C

December 1988

SRCONTROLD

ENABLEC

PARAMETER

SYMBOL

OUTPUTD

OUTPUT 0

MODE
CONTROL

GND--

~

SRCONTROLC

OUTPUTC

5-5

_ _ MODE
CONTROL

•

Signetics Linear Products

Preliminary Specification

Dual Differential RS-422 Party line/
Quad Single-Ended RS-423 Line Driver
DC ELECTRICAL CHARACTERISTICS

AM26LS30

over the operating temperature range. The following conditions apply unless
otherwise specified AM26LS30M. TA = -55°C to + 125°C, Vcc = 5.0V± 10%,
VEE = GND, AM26LS30C, T A = 0 to 70°C, Vcc = 5.0V ± 5%, VEE = GND; AM26LS301,
TA = -40 to +85°C, Vcc = 5.0V ± 5%, VEE = GND RS-422 Connection, Mode
Voltage ,,;; 08V
LIMITS

SYMBOL 2

PARAMETER

TEST CONDITIONS 3

UNITS
Min

Va

Differential output

Va

Voltage, VA. 8

Vr

Differential output

VT
Vas, Vas

Voltage, VA. 8
Common mode offset voltage

IVTI - IVTI

Difference In differential
output voltage

Difference In common mode
IVas 1- IVas 1 offset voltage
Vss

IVT-Vrl

VCMR

Output voltage common
mode range

IXA

Output leakage

IX8

current

lax

Off state (high Z)

RL = 00

RL = 100n

Output short CirCUit

V,H

High level Input voltage

V,L

Low level Input voltage

I'H

High level Input current

I,L

Low level Input current

V,

Input clamp voltage

December 1988

36

60

V

V,N = 0 8V

-3.6

-60

V

24

V,N = 0 8V

-20

RL = 100n

-24
2.5

0.4

V
V

RL = 100n

0.005

0.4

V

RL = 100n

0.005

30

V

RL = 100n

4.0

VENA8LE = 2 4V

±10

Vcc = OV

Vcc = Max

V,N = 2 4V

V,N = 0 4V

Supply current

V,N = 20V

2.0

current

Icc

Max

V,N = 20V

output current
ISA, IS8

Typ1

V

48

V
V

VCMR = 10V

20

fJ.A

VCMR = -10V

-20

fJ.A

VCMR";;10V

20

fJ.A

VCMR >-10V

-20

fJ.A

-150

mA

VaA = OV

-80

V08 = 6V

80

150

mA

VaA = 6V

80

150

mA

V08 = OV

-80

-150

mA

18

30

mA

20

V'N=24V

V

10

0.8

V

40

fJ.A

V,N ";;Vcc

10

100

fJ.A

V'N=04V

-30

-200

fJ.A

-15

V

I'N=-12mA

5-6

Signetics linear Products

Preliminary Specification

Dual Differential RS-422 Party Line /
Quad Single-Ended RS-423 Line Driver

AM26LS30

AC ELECTRICAL CHARACTERISTICS EIA RS-422 Connection, Vcc ~ 5 OV, VEE

~ GND, Mode ~

a 4V,

T A ~ 25"C

LIMITS
SYMBOL 2

TEST CONDITIONS 3

PARAMETER

UNIT
Min

~

Typ1

Max

t,

Rise time

RL

100n, CL ~ 500pF, Figure 1

120

200

ns

tf

Fall time

RL ~ 100n, CL ~ 500pF, Figure 1

120

200

ns

tpDH

Output propagation delay

RL ~ 100n, CL ~ 500pF, Figure 1

120

200

ns

tpDL

Output propagation delay

RL ~ 100n, CL ~ 500pF, Figure 1

120

200

ns

tpLZ

Output enable to output

RL

~

450n, CL ~ 500pF, Figure 2

tpHz
Output enable to output

tPZL

RL ~ 450n, CL ~ 500pF, Figure 2

tpZH

180

300

ns

250

350

ns

250

350

ns

180

300

ns

NOTES:
1 TYPical limits are at Vee = 5V, VEE = GND, 25°C ambient and maximum loadtng
2 Symbols and definitions correspond to EIA RS·422 where apphcable
3 RL connected between each output and Its complement

1r------l
Vee~
, - - - - -__, - - - - - 3.0V

:

INPUT

'----OV

•

I

~_r11~5~--,

1

21

INPUT

OUTPUT

'F
-TEK CTR
CURRENT TRANSF.
OR EQUIVALENT

NOTE:
·Current probe

IS

the easiest way to display a differential waveform

Figure 1_ Switching Time Waveforms and AC Test Circuits for EIA RS-422 Connection

, -_ _ _ _""_ _ _ _ _ 3V

Vee
A

OV

(INPUT A HIGH)

~NPUTALOW)

·TEK CTR
CURRENT TRANSF.
OR EQUIVALENT

Figure 2. 3-State Delays

December 1988

5-7

Signetics Linear Products

Preliminary Specification

Dual Differential RS-422 Party Line /
Quad Single-Ended RS-423 Line Driver
DC ELECTRICAL CHARACTERISTICS

AM26LS30

over the operating temperature range. The following conditions apply unless
otherwise specified: AM26LS30 TA ~ -55'C to + 125'C, Vee ~ 5.0V ± 10%,
VEE~-5.0V ±10%, AM26LS30 TA~O to +70'C, Vee~5.0V ±5.0%,
VEE ~ -5.0V± %5, RS-423 Connection, Mode Voltage ;;. 2.0V.

LIMITS
SYMBOl2

PARAMETER

TEST CONDITIONS

UNIT
Min

Vo

Output voltage

Vo
VT

Output voltage

VT
IVTI-IVTI

Output unbalance

Ix+

Output leakage power off

RL

3

Output short CirCUit current

Y,N

~

2AV

4.0

404

6.0

Y,N

~

OAV

-4.0

-404

-6.0

RL ~ 450.12

Y,N

~

2AV

3.6

4.1

IVeel ~ IVEEI ~ 4 75V

Y,N

~

0 4V

-3.6

-4.1

~ ~Note

IVeel = IVEEI, RL~450n
Vee=VEE=OV

Vo~OV

Is_
~

ISLEW

Slew control current

VSLEW

lee

Positive supply current

Y,N

Y,N = 0 4V, RL

lEE

Negative supply current

V,H

High level Input voltage

V,L

Low level Input voltage

I'H

High level Input current

I,L

Low level Input current

V,

Input clamp voltage

Max

IVeel ~ IVEEI ~4.75V

Ix_
Is+

Typ1

~

0.02

~

V

004

V
IlA

Vo = 6V

2.0

20

-2.0

-20

!1A

-80

-150

mA

80

150

mA

18

30

mA

-10

-22

mA

Y,N

~

2AV

Y,N

~

OAV

± 140

~

~ ~

IlA

V

2.0
0.8

V

40

IlA

10

100

!1A

=n130

-200

IlA

-1.5

V

1.0

Y,N = 2AV
Y,N ~~--4-~-_-"'OUTPUT

I ;ci»

'---"-I--OV

pF

~

OUTPUT

Figure 3. Switching Time Waveforms and AC Test Circuits for EIA RS-423 Connection
Slew Rate (Rise or Fall Time)
vs External Capacitor

10k.----,--.,---,---n-,

•

'OL--~--~,O--'~OO~-'~OOO
RISE TIME ("s)

Figure 4

December 1988

5-9

Signetics linear Products

Preliminary Specification

Dual Differential RS-422 Party Line/
Quad Single-Ended RS-423 Line Driver

AM26lS30

High-Level Output Voltage
vs Output Current

4.50

~ '"-

'.05

i'i"-.

~ 3.60

~!j 3.15
g

r·
I-

r·

-r---

---

To

r--- ~~O~' '\.
r--- ~~=.~ \

1\ \

...

'\

Vee - S.SV

'.50

CJ 1.80

:;:

4.05

~ 1.35

3.60

0.90

3.15

=~OV

r--

vee

r---

vee =1.5V

0

2.70

0

-4

-10

-20

-8

-12

-16

-30

-40

-so

\

\

1\
\
1\
\ \

\

To ~25°C

OA5

0

~

70

25

J25 C

-60

\ 1\
-70

-80

90

100

'",,-HIGH-LEVEL OUTPUT CURRENT (mA)

Figure 5

Low-Level Output Voltage
vs Output Current

-'.50
-'.05

E -3.60
w

~ -3.15

g

f'-.-.

To =1 260C

l"- -.... I'-I'-- ...........
~.5V
I'-t---..
............
r--.
I'- I"'- ~=5.0V
I .......

""

1'-

I-

~ -2.70

§
Ld

-2.25

~
;t

-1.80

-'.50

I'--1'--

I"'Vee =15.5V

~

\

-4.05

r--- '"-

Vee

=I s.ov

~ -1.35

-3.60

r'-

vcc

J.:-

-0.90

-315

~

r---

r----..Vcc ='.5V

-

TA = 25°C
-OA5

-2.70

0

0
n

•
~

8

12

16

~

~

80

n

M

~

'Ol-LOW·LEVEL OUTPUT CURRENT (mA)

Figure 6
December 19BB

5-10

~

=

Signetlcs linear Products

Preliminary Specification

Dual Differential RS-422 Party Line/
Quad Single-Ended RS-423 Line Driver

AM26lS30

Supply Current
vs Supply Voltage

I~
ALL INPUTS OPEN OR GROUNDED
rTA = 25'C

0

RS4~ ~

6
2

r.,... t""'" RS423

8
4
0

o

I--

.....

V

0.7 1.4 2.1 2.8 35 4.2 4.9 5.6 6.3 7.0
Vee·SUPPLY VOLTAGE (V)

Figure 7

•

December 1988

5-11

AM26LS31

Signetics

Quad High-Speed
Differential Line Driver
Product Specification
Linear Products
DESCRIPTION

FEATURES

The AM26LS31 is a quad differential line
driver, designed for digital data transmission over balanced lines. The AM26LS31
meets all the requirements of EIA standard RS-422 and Federal standard
1020. It is designed to provide unipolar
differential drive to twisted-pair or parallel-wire transmission lines. The circuit
provides an enable and disable function
common to all four drivers. The
AM26LS31 features 3-state outputs and
logical ORed complementary enable inputs. The inputs are all LS compatible
and are all one unit load.

•
•
•
•
•
•
•
•
•

The AM26LS31 is constructed using advanced Low Power Schottky processing.

PIN CONFIGURATION

Output skew of 2.0ns typical
Input to output delay: 12ns
Operation from single + 5V
16-pin DIP and SO packages
Four line drivers in one package
Output short-cIrcuit protection
Complementary outputs
Meets EIA standard R8-422
High output drive capability for
100n terminated transmission
lines
• Available In military and
commercial temperature range
• Advanced low power Schottky
processing
• Outputs won't load line when
Vcc=OV

16-Pin Plastic DIP
16-Pin SO

OUTPUT

A 3

ENABLEG 4

OUTPUT

II 5
11 OUTPUTC

OUTPUTB
INPUTB

1

7

OUTPUTC

INPUTC
TOP VIEW

FUNCTION TABLE (Each Driver)
ENABLES

OUTPUTS

G

G

A

APPLICATIONS

H

H

X

H

L

•
•
•
•

L

H

X

L

H

H

X

L

H

L

L

X

L

L

H

X

L

H

Z

Z

Data communications equipment
Computer peripherals
Workstations
Automatic test equipment

INPUT

A

NOTES:

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70°C

AM26LS31CN

+70°C

AM26LS31CD

16-Pin Plastic DIP

-40°C to + 85°C

AM26LS31IN

16-Pin SO

-40°C to + 85°C

AM26LS311D

16-Pin Cerdip

-55°C to +125°C

AM26LS31MF

16-Pin Plastic DIP

-55°C to + 125°C

AM26LS31MN

May 5, 1988

INPUT A 1
OUTPUT A 2

A

ORDERING INFORMATION
DESCRIPTION

D, F, and N Packages

5-12

H - High level
L - Low level
X = Irrelevant

Z - High-Impedance (OFF)

853-1272 93196

Signetlcs Linear Products

Product Specification

Quad High-Speed Differential line Driver

AM26LS31

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vcc

Supply voltage

PARAMETER

7

V

VIN

Input voltage

7

V

55

V

Operating temperature range
AM26LS31MF
AM26LS31MN
AM26LS31IN
AM26LS3110
AM26LS31CN
AM26LS31CD

-55 to +125
-55 to +125
-40 to +85
-40 to +85
o to + 70
o to +70

"C
"C
"C
"C
"C
"C

TSTG

Storage temperature range

-55 to + 150

"C

TSOLD

Lead temperature (soldering 10see max.)

300

"C

Output off-state voltage
TA

DISSIPATION DERATING TABLE
PACKAGE

POWER RATING

DERATING FACTOR

F

1250mW

10mW/"C

25°C

N

1488mW

11.9mW/"C

25"C

0

1126mW

9mW/"C

25"C

May 5, 1988

5-13

ABOVE TA

•

Signetics Linear Products

Product Specification

AM26LS31

Quad High-Speed Differential Line Driver

DC AND AC ELECTRICAL CHARACTERISTICS

Vee = SV± 10%, TA=-SS to +12SoC for AM26LS31MF and AM26LS31MN;
Vcc = SV± S%, TA = -40 to + 8SoC for AM26LS31IN and AM26LS31ID;
Vce=SV±S%, TA=O to +70°C for AM26LS31CN and AM26LS31 CD,
unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

VOH

Output High voltage

Vee = Min.,
IOH=-20mA

VOL

Output Low voltage

Vee = Min.,
10L =20rnA

VIH

Input High voltage

Vee = Min

VIL

Input Low voltage

Vee = Max.

IlL

Input Low current

Vec = Max.,
VIN = OAV

IIH

Input High current

Vee = Max.,
VIN = 2.7V

II

Input reverse current

Vec = Max.,
VIN = 7.0V

10

OFF-state (high-Impedance)
output current

Vee = Max,
Vo=55V
Vo=O.SV

VI

Input clamp voltage

Vec = Min.,
IIN=-18mA

Isc

Output short-circUit current

Vee = Max.

Min

Typ1

2S

3.0

0.3

UNIT
Max

V

OS

2.0

V
V

0.8

V

-0.26

-036

mA

0001

20

p.A

0001

01

mA

06
-OOSO

20
-20

I1A
p.A

-0.8
-30

-l.S

V

-150

rnA

lee

Power supply current

Vee = Max; all outputs disabled

40

80

mA

tpLH

Input to output

TA = 25°C, load2

9

20

ns

tpHL

Input to output

TA = 25°C, load2

9

20

ns

SKEW

Output to output

TA = 2SoC, load2

2

6

ns

tLZ

Enable to output

TA = 25°C, CL = 10pF

17

35

ns

tHZ

Enable to output

TA = 2SoC, CL = 10pF

12

30

ns

tZL

Enable to output

TA = 25°C, load2

14

45

ns

tZH

Enable to output

TA=2SoC, load 2

12

40

ns

NOTES:
1. All typical values are TA = + 2S·C, Vee = S OV
2. CL = 30pF, VIN - 1 3V to VOUT = 1 3V, VPULSE = OV to 30V

May 5, 1988

5-14

Signetics Linear Products

Product Specification

Quad High-Speed Differential line Driver

AM26LS31

TIMING DIAGRAMS
PARAMETER MEASUREMENT INFORMATION
3V

~-----3V

ENABLEG

INPUT A

OV

l"-=--OV
(SEE NOTE 2)
WAVEFORM 1
(SEE NOTE 4)

OUTPUT A

OUTPUT

Ii - - - - - -

...Jt=='="-1.5V

WAVEFORM 2
(SEE NOTE 4) _ _...;.~==_'"

-----:t~~~~

1.5V

51 AND
S2CLOSED

Enable and Disable Times

Propagation Delay Times and Skew

NOTES:
1. All pauses are supplied by generators having the follOWing characteristics
PRR <; 1MHz, ZOUT - 50\1, 1R <; 15ns, 1F <; 6ns

2. When measunng propagation delay times and skew, sWitches 81 and 82 are

open.
3. Each enable is tested separately.
4. Waveform 1 IS for an output With internal condition such that the output IS low
except when disabled by the output control Waveform 2 is for an output With
internal conditions such that the output IS high except when disabled by the
output control.
5. CL Includes probe and Jig capacitance

Test Circuit

May 5, 1988

5-15

I

Signetics linear Products

Product Specification

AM26LS31

Quad High-Speed Differential Line Driver

TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs
Data Input Voltage
6.00

Output Voltage vs
Data Input Voltage

5.00

:E

+12!OC

4.00

I

3.00

55'C_

+25°C

I

5

~ 2.00

I

::>

o

~

TA == 25°C
NO LOAD

5.SO

5.00

§>

6.00

6.00

Vee = s.ov
NO LOAD

~

1.00

o

:E
4.SO
w
~

~ 1.50
> 1.00

3.00

~

2.50

§2

200

w

I

I I
I I

-55'C

°>01 .00
0.00

o

;

Sl

4.00

w
" 4.00

> 3.00

3.00

~

~

~ 4.00

2.SO

TA

uj

I

I

";!

_I,

-'

r-

I--

4.00

g

3.50

!5

3.00

~
o

2.00

...J

G 1.00

£!

;:

TA

~

l:

2.50
2.00

1.50

~ OAO

t- ......

g

......

.......

~ee = 5.5V

Vee = 5.0V"",

-- ",r'\. r'\.

:r 0.50

> 0.00

-75 -50 -25 0
25 50 75 100 125
TA AMBIENT TEMPERATURE rC)

:? 0.00

1

0 30
•

iii

I'..

Vee = 4.SV

1.00

1-

-j25 C
C

-55'C

"'- I'\. r'\.
r'\. I'\.. :'\".
~ i\..

o -10-20-3O-4O-SO-60-70-80-90-1oo
10H HIGH LEVEL OUTPUT CURRENT (mAl

o

0.5
1
1.5
2
U
V, ENABLE G INPUT VOLTAGE (V)

Vee = 5V
IOL

~

-

j125'C

Low Level Output Voltage
vs Ambient Temperature

:E 0.50

= 25°C

l:

Ii

0.00

High Level Output Voltage
vs Output Current
5.00

-

I

H

o
> 1.00

\

;; 4.50

10H == -40mA

OO

= 25°C

O.SO LOAD = 470n TO Vee
0.00
o 0.5
1
1.5
2.5
V, ENABLE G INPUT VOLTAGE (VI

:>
5V

lo;:.:.~~

g

...

r';

i

= 5V

5.00

~>
~ ~oo
o

0 1.50

I

Vee

Vee - 4.sV

> 1.00

0.5
1
15
2
2.5
V, ENABLE G INPUT VOLT AGE (V)

5.00

Vee

LOAD = 11c!l TO Vee

:E

5.00
4.50

High Level Output Voltage
vs Ambient Temperature

:E

1.5
2.5
0.5
V, ENABLE G INPUT VOLTAGE (V)

6.00

= 5.0V

§ 2.00

11 III

050

vee

g 3.50

I I
I /I

~ 1.50

= 4.5V

Output Voltage vs
Enable G Input Voltage

Vee - 5.5V

5.SO

>"

+125"C

5

0.00 0

0.5
1
1.5
2
2.5
V, DATA INPUT VOLTAGE (V)

Output Voltage vs
Enable G Input Voltage

+2SOC

5.0V

Vee

0.50

0.00 0

6.00

=

2.SO

Vee

~2.oo

O.SO

Vee - SOV
LOAD
470f!

Vee - 5.5V

~ 4.00
3.50
~ 3.00

~ 1.50

4.00

~

....I

5

0.5
1
1.5
2.5
VI DATA INPUT VOLTAGE (V)

TO?ND!

Vee - 4.5V

5.5V

= 5.0V

T. - 25"C
5.SO LOAD = 4700 TO GND
5.00
4.SO

~ 2.SO
:) 2.00

Output Voltage vs
Enable G Input Voltage
3.50

:E
w

Vee

3.50
3.00

-I

J

Vee

~ 4.00

> 1.00

I

I

0.00

Output Voltage vs
Enable G Input Voltage

0.20

= 40mA

- r-

r-.

~

~

0.10

-'

~

:? 0.00

-75 -so -25 0
25 so 75 100 125
TA AMBIENT TEMPERATURE ("C)
OP200925

May 5, 1988

5-16

Signetics Linear Products

Product Specification

Quad High-Speed Differential Line Driver

AM26LS31

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Low Level Output Voltage
vs Output Current
~ 1.00

IV
c

!:i

T.

Supply Current
vs Supply Voltage

=25"C

Vee

§ 0.50
...... 0.40
.. 0.00

I

I

I

~

~ 0.80

~O.IO

250

I

, _

_~=~EgR GROUNDED _
_NO LOAD

~ 0.70

~ 0.30

- i. =' b I

_ JOLW
I
I
OUTPUT ENABLED
-TA = 25°C

0.90
0.80

~ 0.20

Supply Current
vs Supply Voltage

,..

.#

=4.5V ~
~ Vee =5.5V

/
ALL INPUTS GROUNDED

~y

o

;"

,r. ,l
A~L '~PUf ~PE~-

#

,....!,
20

40

80

80

100

120

....,...

IOL LOW LEVEL OUTPUT CURRENT (mA)

o
o

,/

I

I

.7 IA 2.1 2.8 3.S 4.2 4.9 5.6 8.3 7
Vee SUPPLY VOLTAGE (V)

.........

L

/

L

/
;"

o
o

V
.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 8.3 7
Vee SUPPLY VOLTAGE (V)

......,..

•

May 5, 1988

5-17

AM26lS32/33

Signetics

Quad High Speed Differential
Line Receivers
Objective Specification

Linear Products
DESCRIPTION

FEATURES

The AM26LS32 and AM26LS33 are
quad line receivers with the AM26LS32
designed to meet all of the requirements
of RS-422 and RS-423 and Federal
Standards 1020 and 1030 for balanced
and unbalanced digital data transmission.

• Input voltage range of 1SV
(differential or common mode)
on AM26LS33; 7V (differential or
common mode) on AM26LS32

The AM26LS32 features an Input sensItivity of ± 200mV over the common
mode Input range of ± 7V.
The AM26LS33 features an input sensItivity of ± 500mV over the common
mode Input voltage range of ± 15V.
The AM26LS32 and AM26LS33 provide
an enable and disable function common
to all four receivers. Both parts feature
3-State outputs with 8mA sink capability
and incorporate a fall-safe Input-output
relationship which forces the outputs
high when the Inputs are open.

PIN CONFIGURATION

• ± O.2V sensitivity over the input
voltage range on AM26LS32
• ± O.SV sensitivity on AM26LS33
• 6k minimum input impedance

• 60mV input hysteresis
• The AM26LS32 meets all the
requirements of RS-422 and
RS-423
• Operation from single + SV
supply
• Fall safe input-output
relationship. Output always high
when inputs are open
• 3-State drive, with choice of
complementary output enables,
for receiving directly onto a data
bus
• 3-State outputs disabled during
power up and power down

ORDERING INFORMATION
DESCRIPTION
16-Pm PlastiC DIP
16-Pm SO

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70°C

AM26LS32CN

+70°C

AM26LS32CD

16-Pm Plasllc DIP

-40°C to + 85°C

16-Pln SO

_40°C to +85°C

AM26LS321D

16-Pm Cerdlp

- 55°C to + 125°C

AM26LS32MF

16-Pm PlastiC DIP

-55°C to +125°C

AM26LS32MN

16-Pm PlastiC DIP
16-Pm SO

o to
o to

AM26LS321N

+70°C

AM26LS33CN

+70°C

AM26LS33CD

16-Pln PlastiC DIP

-40°C to + 85°C

16-Pm SO

-40°C to + 85°C

AM26LS331D

16-Pln Cerdlp

-55°C to +125°C

AM26LS33MF

16-Pln PlastiC DIP

-55°C to +125°C

AM26LS33MN

December 1988

AM26LS331N

5-18

F, D and N Packages

3ignetics Linear Products

Objective Specification

Quad High Speed Differential Line Receivers

AM26lS32/33

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vce

Power supply

PARAMETER

7

V

Y'N

Power supply

7

V

50

mA
V

Output sink current
Common mode range

±25

VTH

Differential input voltage

±25

V

TSTG

Storage temperature range

-65 to +150

°C

DERATING
FACTOR

ABOVE
TA

DISSIPATION OPERATING TABLE
PACKAGE

POWER DISSIPATION

F

1,524mW

12.19mWrC

25°C

N

1,275mW

10.2mW/oC

25°C

D

1,262W

10.1mW/oC

25°C

DC AND AC ELECTRICAL CHARACTERISTICS

Vee = 5.0V± 10% for AM26LS32/33MX, Vee = 5.0V± 5% for
AM26LS32/33CX and AM26LS32/331X over operating temperature range
unless otherwise specified.
LIMITS

SYMBOL

VTH

PARAMETER

Differenlial Input voltage

TEST CONDITIONS

AM26LS32133

UNIT

Min

Typl

Max

VOUT = VOL or VOH
AM26LS32, -7V <, VeM <, + 7V

0.2

0.06

0.2

V

AM26LS33, -15V <, VeM <, + 15V

0.5

0.06

0.5

V

6.0

9.8

R'N

Input resistance

-15V <, VeM <, + 15V
(One input AC ground)

liN

Input current
(under test)

Y'N = +15V
Other Input -10V <, Y'N <, + 15V

2.3

mA

liN

Input current
(under test)

V'N=-15V
Other input + 10V <, Y'N <'-15V

-2.8

mA

VOH

Output HIGH voltage

VOL

Output LOW voltage

Vee = min., 10H = -440J.lA
AV'N=+1.0V
VENABLE = 0.8V

Vee = min.,
VENABLE = 0.8V,
AV,N = + 1.0V

Com'l

2.7

Mil

2.5

10L = 8.0mA
V,L

Enable HIGH voltage

V,

Enable clamp voltage

10

December 1988

Off state (high impedance)
output current

V

3.4

V
0.4

V

0.8

V

-1.5

V

Vo = 2.4V

20

J.lA

Vo = O.4V

-20

J.lA

2.0
Vee = min., liN = -18mA
Vee = max.

5-19

V

0.45

Enable LOW voltage

V,H

3.4

0.3

10L = 4.0mA

krl

V

•

Signetics Linear Products

Objective Specification

Quad High Speed Differential line Receivers

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

AM26LS32/33

vce = 5.0V± 10% for AM26LS32/33MX, Vee = 5.0V± 5%
for AM26LS32/33CX and AM26LS32/331X over operating
temperature range unless otherwise specified.

LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

AM26LS32/33
Min

UNIT

Typl

Max

I'l

Enable LOW current

Y'N = O.4V

-0.2

-0.36

mA

I'H

Enable HIGH current

Y'N = 2.7V

0.5

20

pA

I,

Enable input HIGH current

Y'N = 5.5V

1

100

pA

Ise

Output short circuit current

-60

-85

mA

Icc

Power supply current

52

70

mA

Vee = max.
t.V,N = + 1V, VOUT
Vee

Input hysteresis

VHYST

Vee

= max.;

-15

= OV

All Y'N = GND outputs
disabled

TA = 25°C,
= 5.0V, VeM = OV

AM26LS32
AM26LS33

tplH

Input to output

tpHl

Input to output

Enable to output

tHZ

mV

120

mV

TA = 25°C, Vee = 5.0V
Cl = 15pf (see test condition)

TBD

25

ns

T A = 25°C, Vee = 5.0V
= 15pf (see test condition)

TBD

25

ns

Cl

T A = 25 = C, Vee = 5.0V
= 5pF (see test condition)

TBD

30

ns

Cl

TA = 25°C, Vee = 5.0V
= 5pF (see test condition)
TA = 25°C, Vee = 5.0V
Cl = 15pF (see test condition)

TBD

22

ns

TBD

22

ns

TBD

22

ns

Enable to output

tlZ

60

Cl

tZl

Enable to output

tZH

Enable to output

TA

= 25°C, Vee = 5.0V
Cl = 15pF

NOTE:
1. All tYPical values are TA = 25°C, Vec = 5.0V

FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL
INPUT

ENABLES

OUTPUT

E

E

V,D>VTH

H
X

X
L

H
H

VTL .;; V,D .;; VTH

H
X

X
L

?
?

V,D ';;VTl

X

L

L

X

L

H

Z

NOTES:
H = high level, L '" low level, X = Irrelevant
Z = high Impedance (off), ? = Indeterminate
E = enable, E = enable

December 1988

5-20

Signetics Linear Products

Objective Specification

Quad High Speed Differential Line Receivers

ENiii:E

TEST
PONT

3.0Y

INPUT

OUTPUT-t-~~:

ENABLE

INPUT

OV

"''''L
+25V
____
_ _ _ OV

~

OPPOSITE
PH." _ _ _

TRA"::~

Load Test Circuit for 3-State Outputs

AM26LS32/33

- - - -25V

Propagation Delay I, 4

Enable and Disable Tlmes2, 3, 4

NOTES:
1 Dtagram shown for

Eiii6Ie Low
2 Enable IS tested with rniiiiEi High. ~ IS tested With Enable Low
3 51 and 52 of Load CircUit are closed except where shown
4 Pulse Generator for All Pulses Rate"';;;' 1 OMHz. Zo'" 50n, t, < 15ns, If "- 6 Ons

•

December 1988

5-21

MC1488

Signetics

Quad Line Driver
Product Specification

Linear Products

DESCRIPTION
The MG1488 is a quad line driver which
converts standard DTLlDL input logic
levels through one stage of inversion to
output levels which meet EIA Standard
No. RS-232C and GGID Recommendation V.24.

FEATURES
• Current limited output: ± 10mA
Typ
• Power-off source impedance:
300n min
• Simple slew rate control with
external capacitor
• Flexible operating supply range
• Inputs are DTL/TTL compatible
APPLICATIONS
• Computer port driver
• Digital transmission over long
lines
• Slew rate control
• TTL/DTL to MOS translation

PIN CONFIGURATION
D, F, N Packages

VEE

1

INPUT 1

2

OUTPUT 1

3

INPUT'A 4
INPUT'B

OUTPUT • •

GND

11

OUTPUT4

5

1

•

INPUTaA

•

OUTPUT 3

C010aeos

CIRCUIT SCHEMATIC
v+
Rl

R2
62K

B.2K
01

INPUT
INPUT

V

,~

..... 02

"

De

.....

....
02

R3

70!J

.. 03

R8
300!l

OUTPUT

.. 04
06

I-DS

R4
36K

'ii7

~

.

,~

D8

O~
.".

V

,,03

V

04

"OS ....

"..

Rs
10K

R6
7K

R7
70n

V114 CIRCUIT

October 20, 1987

5-22

853-0933 91022

Product Specification

Signetics Linear Products

MC1488

Quad Line Driver

ORDERING INFORMATION
TEMPERATURE RANGE

DESCRIPTION

a to
a to
a to

14-Pin Plastic SO
14-Pin Plastic DIP
14-Pin Ceramic DIP

ORDER CODE

+75°C

MC1488D

+75°C

MC1488N

+75°C

MC1488F

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vce

RATING

UNIT

Supply voltage V +

PARAMETER

+15

V

V-

-15

V

-15 -

--t

'~~,~~91

CArE

- 1 -r-~~~~--~
-~:]:~*
~ ~

INTERNAL DATA
TERMINAL
EQUIPMENT

1_

SIGNAL GROUND

~

.".

-«--::=
_..r1/4 MC1488

MODEM

16

Vo OUTPUT VOLTAGE (V)
0P0974OS

NOTE,
·Optlonal for nOise flltenng

Output Voltage and Current-Limiting
Characteristics

AC LOAD CIRCUIT

APPLICATIONS

VINir.VOUT
3K

.". J

RS-232C Data Transmission

15pf"

By connecting a capacitor to each driver
output the slew rate can be controlled utilizing
the output current-limiting characteristics of
the MC1488 For a set slew rate the appropriate capacitor value may be calculated uSing
the following relallonship

TYPICAL APPLICATIONS
+12V
MOS

DTLI

OUTPUT
-10V TO
-O.4V

TTL
INPUT
10K

C = IsC--

14MC1489
MC1489A

TTL OlL

TTL

on

:r--)o--

)O--+------r---+-;;>O-----L.._
INTERCONNECTING
CABLE
TTL

- --o-l"-r-[), ,.,

I

MOSLOGIC

L __ ~

I

14MCI489
Me 1489A

I

I

b
MODEM

NOTE:
·Opbonal for nOise ftltenng

R5-232C Data Transmission

October 20, 1987

L--[~'

MOS-to-TTL/DTL Translator

5-28

..,

Signetics

AN113
Using the MC1488j1489 line
Drivers and Receivers
Application Note

Linear Products

LINE DRIVERS AND RECEIVERS
Many types of line drivers and receivers are
available today. Each device has been designed to meet specific criteria For Instance,
the deVice may be extremely wide-band or be
Intended for use In party line systems. Some
Include bUilt-in hysteresIs In the receiver while
others do not

The EIA Standard
The Electronic Industries ASSOCiation (EIA)
has produced a number of specifications
dealing with the transmission of data between
data terminal and commUnications eqUipment One of these IS EIA Standard RS-232C,
which delineates much information about slgnallevels and hardware configurations In data
systems

MC1488/1489
As line driver and receiver, the MC1488 and
MC1489 meet or exceed the RS-232C specIfication
Standard RS-232C defines, the voltage level
as being from 5 to 15V with positive voltage
representing a logiC O. The MC1488 meets
these reqUirements when loaded With resIstors from 3k to 7k.l!
Output slew rates are limited by RS-232C to
30V / p.s. To accomplish this speCification, the
MC1488 IS loaded at ItS output by capacItance as shown by the typical hook-up diagram of Figure 1. A graph of slew rate vs
output capacitance IS given In Figure 2. For
the standard 30V / p.s, a capacitance of 400pF
IS selected.

December 1988

The short-circuit current charges the capacItance With the relationship
ISCflT

c~-­

flV
Where C IS the required capaCitor, Isc IS the
ShOrt-CIrCUit current value, and flV/ flT IS the
slew rate.
USing the worst-case output short-CIrcuit current of 12mA In the above equation, calculations result In a required capacitor of 400pF
connected to each output to limit the output
slew rate to 30V / p.s In accordance With the
EIA standard.
The EIA standard also states that output
shorts to any other conductor of the cable
must not damage the driver Thus, the
MC1488 IS deSigned such that the output will
Withstand shorts to other conductors ilideflnIIely even If these conductors are at worstcase voltage levels. In addition to output
protection, the MC1488 Includes a 300.l!,
resistor to ensure that the output Impedance
of the driver will be at least 300.l!, even If the
power supply IS turned off. In cases where
power supply malfunction produces a low
Impedance to ground, the 300.l! resistors are
shorted to ground also. Output shorts then
can cause excessive power diSSipation. To
prevent thiS, series diodes should be Included
in both supply lines as pictured In Figure 3.
The companion receiver, MC1489, IS also
deSigned to meet RS-232C speclflcallons for
receivers It must detect a voltage from ± 3 to
± 25V as logiC Signals but cannot generate an
Input differential voltage of greater than 2V

5-29

should ItS Inputs become open circUited.
NOise and SpUriOUS Signals are rejected by
incorporating positive feedback Internally to
produce hysteresIs. Featured also In the receiver IS an external response node so that
the threshold may be externally varied to fit
the application. Figure 4 shows the shift In
high and low triP POints as a function of the
programming resistance.

APPLICATIONS
The deSign of the MC1488 and MC1489
makes them very versatile With many pOSSible
applications The MC1488 output current limIting enables the user to define the output
voltage levels Independent of supply voltages. Figure 5 shows the MC1488 as a TILto-MaS Translator, while Figures 6 and 7
illustrate TIL-to-HTL and TTL-to-MOS Translators
The MC1489 response control node allows
the user to modify the Input threshold voltage
levels. This IS accomplished by adding a
resistor between the response control pin
and an external power supply. Figure 4 shows
the shift thus prOVided. This feature and the
fact that the Inputs are deSigned to Withstand
± 30V permit the use of the MC1489 for level
translallon as shown In the MOS-to-TTL
Translator of Figure 8. This feature IS also
useful for level shifting, as Illustrated In Figure

9
The response control node can also be used
to filter out high frequency, high energy nOise
pulses. Figures 10 and 11 give typical nOise
pulse relectlon curves for various Sized external capacitors.

•

Application Note

Signetics Linear Products

AN113

Using the MC1488/1489 Line Drivers and Receivers

·
·
·

rJ~!YH

°r·sl.'

I

i

~lK

~,rK

::J

~~

~5T~ t-

··

..=....VTH

!

·

VilOV'H

-,

i
.!

I

o

Figure 1. Typical Line Drlver·Recelver Application

~'r.
"

-

*

I

!
I
!

.10.10.30

Vlft! INPUT VOL TA.GE (Vile,

a. MC1489

10

100

1000

-

-

10.000

CAPACITANCE (pF)
o

Figure 2. Output Slew Rate vs Load Capacitance

''0

_20

_30

-40

VI'" INPl,ltVOLTAGEN- - - - - - , - - -

(;14

'---'-1
I MCl488L I

I

r-

':. T"'c _ )o-t-<)
o-t,~
I
o-p
___ ~~")

g::r:[ ~J<>.l-o
o-l

--=-

I

0-1:;"" _)o-j <)
LT

9'

_,1

?,

~I
vo,o---i. .- ....- - - - -.. - - - - -~ - Figure 3. Protection From Power Supply Malfunction

December 1988

5·30

Figure 4. Hysteresis as a Function of
Programming Resistance

Signetics Linear Products

Application Note

Using the MC1488/1489 line Drivers and Receivers

AN113

+ 12V
MOS
OUTPUT
-10V TO
-0.4V

TTL

INPUT

-12V

R

TTL
INPUT
(V2)

10K

14
VH TO VL
OUTPUT

o-----f

-12V

Figure 5. TTL-to-MOS Translator
Figure 9. Level Shifter 1
+ 12V
NOTE:
1 V2<5V,

3V~VH-VL";;;10V

HTL

TTL

"'-_~_~

INPUT

OUTPUT
-O.7V TO
+10V

in 5

!J

-12V

Figure 6. TTL-to-HTL Translator

~
o~ 4 r-~~--~\-~~---+-----~

::>

....

~

.",

3

W 2

+ 12V

MOS
TTL
OUTPUT

10--1--0

10

~~T~uio

100

1000

10,000

PW. INPUT PULSE WIDTH (ns)

-lOV

Figure 10. Turn-on Threshold vs Capacitance
From Response Control Pin to GND
-12V

Figure 7. TTL-to-MOS Translator

SV

SK
MOS
INPUT
-10VTO

1/4 Me 1489

TTL
OUTPUT

OV

Figure 8. MOS-to-TTL Translator
10

100

1000

10,000

PW, INPUT PULSE WIDTH (ns)

Figure 11. Turn-on Threshold vs Capacitance
From Response Control Pin to GND

December 1988

5-31

•

NE5170

Signetics

Octal line Driver
Preliminary Specification

Linear Products
DESCRIPTION
The NE5170 IS an octal line driver which
is deSigned for digital communications
with data rates up to 1OOkb/ s. This
device meets ali the reqUirements of EIA
standards RS-232C/RS-423A and
CCITT recommendations V.10/X.26.
Three programmable features: (1) output
slew rate, (2) output voltage level, and
(3) 3-State control (high-impedance) are
provided so that output characteristics
may be modified to meet the requirements of specific applications.

FEATURES
• Meets ErA RS-232C/423A and
CCITT V.10/X.26
• Simple slew rate programming
with a single external resistor
• 0.1 to 1OV / JlS slew rate range
• High/Low programmable voltage
output modes
• TTL compatible inputs

PIN CONFIGURATIONS

N Package

APPLICATIONS
• High-speed modems
• High-speed parallel
communications
• Computer I/O ports
• Logic level translation

FUNCTION TABLE
TOP VIEW

OUTPUT VOLTAGE (V)
ENABLE

LOGIC
INPUT

A Package

RS-232C
RS-423A 1
Low Output Mode 1

High Output Mode 2

L

L

5 to 6V

5 to 6V

>9V

L

H

-5 to -6V

-5 to -6V

<-9V

H

X

H,-Z

HI-Z

Hi-Z

NOTES:
1 vcc ~ + 10V and VEE ~ -10V, RL = 3kn
2 Vcc~+12V and VEE~-12V, RL=3kn

ORDERING CODE
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP

o to +70°C

NE5170N

28-PIn PLCC

o to +70°C

NE5170A

24-Pln SO package

o to + 70°C

NE5170D

TOP VIEW

D Package

TOP VIEW

December 1988

5-32

Preliminary Specification

Signetics Linear Products

Octal Line Driver

NE5170

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc

Supply voltage and + MODE

15

V

VEE

Supply voltage and - MODE

-15

V

lOUT

Output current 1

± 150

rnA

Y,N

Input voltage (ENABLE, Data)

-1.5 to +7

V

VOUT

Output voltage 2
M,nimum slew reslstor 3
Power dissipation

PD

DC ELECTRICAL CHARACTERISTICS

±15

V

1

kn

1200

mW

Vcc=10V ±10%; VEE=-10V ±10%, ±MODES=OV; RSL=2kn. 0'C<;;TA <;;70'C.
unless otherwise specified.
LIMITS

PARAMETER

SYMBOL

VOH

VOL

TEST CONDITIONS

UNIT
Min

Max

Y'N = 0.8V
RL = 3kn4

5

6

RL = 450n4

4.5

6

RL = 3kn5 , CL = 2500pF

Vcc- 3

V'N=20V
RL = 3kn4

-6

-5

RL = 450n4

-6

-4.5

Output High voltage

Output Low voltage

RL = 3kn 5 , CL = 2500pF
YOU

Output unbalance voltage

V

VEE+3

Vec = IVEE I. RL = 450n4
-100

004

V

100

I1A

08

V

ICEX

Output leakage current

V,H

Input High voltage

V,L

Input Low voltage

I'L

LogiC "0" input current

Y'N = OAV

-400

0

I1A

I'H

Logic "1" input current

Y,N = 2AV

0

40

I1A

los

Output short circUit current 1

Vo=OV

-150

150

rnA

VCL

Input clamp voltage

liN = -15mA

-1.5
35

rnA

Icc

IVa 1= 6V, ENABLE = 2V or Vcc = VEE = OV

V

20

No Load
Supply current
No Load

lEE

NOTES:
1 Maximum current per driver Do not exceed maximum power diSSipation If more than one output IS on
2 High-Impedance mode
Minimum value of the resistor used to set the slew rate
VOH. VOL at Rl = 450n Will be ~ ~90% of VOH, VOL at RL = 00.

High Output Mode; +MODE pln=Vcc, -MODE pln=VEE, 9V';;;Vcc';;;13V. -9V>VEE>-13V

December 1988

5-33

-45

V

V

rnA

•

Signetics Unear Products

Preliminary Specification

Octal Line Driver

NE5170

AC ELECTRICAL CHARACTERISTICS

Vcc=+10V; VEE=-10V; Mode = GND, 0·C<;;TA<;;70·C
LIMITS

SYMBOL

TEST CONDITIONS

PARAMETER

UNIT
Min

Max

tpHZ

Propagation delay output high to high-Impedance

RL = 4S0, CL = SOpF
or
RL = 3k, CL - 2S00pF

S

iJS

tpLZ

Propagation delay output low to high-Impedance

RL = 4S0, CL = SOpF
or
RL = 3k, CL = 2S00pF

S

iJS

tpZH

Propagation delay high-impedance to high output

RSL = 200k
RL = 4S0, CL = SOpF
or
RL = 3k, CL = 2S00pF

lS0

iJS

tpZL

Propagation delay high-Impedance to low output

RSL = 200k
RL = 4S0, CL = SOpF
or
RL = 3k, CL = 2S00pF

lS0

P.S

SR

Output slew rate 1

RSL = 2k

8

12

RSL = 20k

0.8

1.2

RSL = 200k

006

0.14

V/iJS

NOTE:

SA: Load conditIOn. (A) For ASl < 4kn use Al = 450n; Cl = 50pF; (8) for ASl > 4kn use erther Al = 450n, Cl = 50pF or Al

AC PARAMETER TEST CIRCUIT AND WAVEFORMS
.10V

Vee

ENABLE

EN

VOUT

V,N

1-........-

_ _0

D,N
- MODE GND + MODE VEE

OUTPUT

CL
RSL

RSL

-10Y

3V~

EN

ov --I

I
I

VOH

VOUT

I

VOUT

I

Voz

VOL ___ .L_I'-~_ _"":-'II

: : t

--I

I-

'm

tV

I
I
I

--t
I

I
I

I
1-IpL2

I
-I
WFl6270S

NOTES:
1 See AC electncal charactenstlcs table for values of RSL. At. and CL
2 V,N pulse Frequency'" 1kHz. duty cycle" 50%, .loUT - 50n, tr "" t,.s;;: 10ns

December 1988

--r-

1V

5-34

= 3kn,

Cl = 2500pF.

Signetics Linear Products

Preliminary Specification

Octal line Driver

SLEW RATE PROGRAMMING
Slew rate for the NE5170 IS set uSing a single
external resistor connected between the RSL
Pin and ground. Adlustment IS made accordIng to the formula.
20
RSL (in kn) = Slew Rate
where the slew rate IS In VIllS. The slew
resistor can vary between 2 and 200kn which
gives a slew rate range of 10 to O.W IllS. ThiS
adjustment of the slew rate allows tailOring
output characteristics to recommendations
for cable length and data rate found In EIA

NE5170

standard RS-423A. Approximations for cable
length and data rate are given by:
Max data rate (In kb/s) = 300/t
Cable length (In feet) = 100 X t
where t IS the rise time In microseconds. The
absolute maximum data rate is 100kb/s and
the absolute maximum cable length IS 4000
feet.

OUTPUT MODE PROGRAMMING

levels. The low output mode meets the specIfications of EIA standards RS-423A and RS232C. The high output mode meets the specIfications of RS-232C only, since higher output
voltages result from programming thiS mode.
The high output mode provides the greater
output voltages where higher attenuation levels must be tolerated Programming the high
output mode IS accomplished by connecting
the +MODE pin to Vee and the -MODE pin
to VEE. The low output mode results when
both of these pins are connected to ground.

The NE5170 has two programmable output
modes which provide different output voltage

r-------------,

r------------.,

+v,L.Jr

-v

*
I

I.

TIE TO GROUND FOR

RS232C

_ _ _ _ _ _ _ _ _ _ _ _ _ ...1I

VEE
------------- MODE PINS CONNECTED FOR
PROPER OUTPUT LEVEL

Figure 1. RS-232C/RS-423A Data Transmission

December 1988

I
I

5-35

•

Signetics Linear Products

Preliminary Specification

NE5170

Octal Line Driver

INPUT O-_i4---E:'--~-"":::1-+

Figure 2. Input Stage Schematic

December 1988

5-36

Signetics Linear Products

Preliminary Specification

Octal Line Driver

NE5170

NE5170

...--------+----if-.._--t-oOUTPUT

Figure 3. Output Stage Schematic

December 1988

5-37

•

Signeilcs linear Products

Preliminary Specification

Octal line Driver

NE5170

)+-

------~------~-

45

MODE=GND;RSL -2kQ;
IN = H,EN =L,OUT= NO LOAD

Frt-+tr-+l-t++--1

41

~ lEE

37

I

33

29

Icc

I-~

I

:

11
±9

-10

I

-

T;D'oC

I

col

I

I

~

-600

'

~-50

,;'

RL =450Q- f-

N°rAI-i-

-55

I

-800

-6.0

(Vr ~'ovi ASI =2~Q)

:':13

:'::12

-45

~

I
_I

!

I

V~= ~9V'~SL ~2kh,..6w~oD~_ -

o

-V EE -05V-

70°C

:'.:11

±10

'==

-400

, -_. 1--

:l J

r-- -

r
O

- r--

~

-40

o.-m
:.

III

r DOC

I I

i

1I {

I

,-

-5

I I

I

--r

25

f--

,-

t '-t

!

u

-"

I DOC

I

I I
i I

c

~

we_

v-MODEM
-

70

50

Vee AND VEE (V)

-1000
(W07li1QS

Figure 4. Typical Icc and lEE vs Supply
Voltages
~---

Figure 7. Typical -MODE Current vs
-MODE Voltage

6.0

'OL(mA)

o

20

10

30

----

I

-2

-8
-10

111\1, 1

Vs= ±9V,
LOW MODE

!

J

1

TA =25°C;

-12

800

(V' ~10J
I I i
=

600

A I

=2lQ)~t

,=±1-1 f-I f-r-,
!r-

""g

--- -!

DOC

,

I

D

12

Figure 11. Typical Output High Voltage
vs Temperature

12

Vs = ::t9V, HIGH MODE '
,

f-

--

'.J

r wcT

o

70

I

II
\ I

100

50

I

Vcc~Oi5V

~ 200

4.0

10

11 I I I

-

C( 400

Rll =kkQ,I,NPur=2v

::t13V, HIGH MODE

Vs

..lRL -450Q

MODE r-- -

Figure 8. Typical Output Low Voltage
vs Load Current

--l-

NOLO~

--

Vs - :t13V,
HIGH

i

I

SL

V~= ~9viAsL ~2k~'~W~OD:E+

45

~f;H:t~~'Dl

-2

Figure 5. Typical Input Current vs Input
Voltage

5.5

I

I

-4

50

40

° c--r- 1

-m~~I-~#-+I+I~_~~
H+4'.J~-+I-'--+-T~ 1-r
I
i
--~~r+-"~~I~I~-f-+I~

Figure 10. Typical Output Low Voltage
vs Temperature

--

16

20

V+MODEM

~I

rt- 51 T'
V

I
f-50

I

i
I I I

j"V LOjM'IDE

T, =2S 0 C',A SL =2iQ;

-40

-30

-20

I~PU+=0'8V
-10

0

o

IOH(mA)

RSL (k2)
TYPICAL SLEW RATE vs RSl

OP07631S

Figure 6. Typical + MODE Current vs
+MODE Voltage

Figure 9. Typical Output High Voltage
vs Load Current

---~--

December 1988

5-38

Figure 12. Typical Slew Rate vs RSL

NE5180/NE5181

Signetics

Octal Differential line
Receivers
Preliminary Specification

Linear Products
PIN CONFIGURATIONS

DESCRIPTION

FEATURES

The NE5180 and NE5181 are octal line
receivers designed to interface data terminal equipment with data communications equipment. These devices meet
the requirements of EIA standards RS232C, RS-423A, RS-422A, and CCITT
V.10, V.11, V.28, X.26 and X.27. The
NE5180 is intended for use where the
data transmission rate is up to 200 kb/ s.
The NE5181 covers the entire range of
data rates up to 10 Mb/s. The difference
in data rates for the two devices results
from the input filtering of the NE5180.
These devices also provide a failsafe
feature which protects against certain
input fault conditions.

• Meets EIA RS-232C/423A/422A
and CCITT V.10, V.11, V.28
• Single + 5V supply - TTL
compatible outputs
• Differential inputs withstand
±25V
•
•
•
•

H+
HGo
G+
G-

Fo

APPLICATIONS
Co

• High-speed modems
• High-speed parallel
communications
• Computer I/O ports
• Logic level translation

F+

FD+

Eo

Do

E+

GND

ETOP VIEW

FAILSAFE
INPUT

LOGIC
OUTPUT

X

H

X

L

VID> 200mV 1
VID

vee
Ho

Failsafe feature
Input noise filter (NE5180 only)
Internal hysteresis
Available in SMD PLCC

FUNCTION TABLE
INPUT

N Package

< -200mV 1

OV

L

Vce

H

A Package
B- Ao A+ A- Vee Ho H+

Both Inputs open or grounded

NOTE:
1 VIO IS defmed as the non-mvertlng terminal Input voltage minus the Inverting termmal Input voltage

ORDERING INFORMATION
DESCRIPTION
28-Pln Plastic DIP
28-Pin Plastic DIP
28-Pln PLCC
28-Pin PLCC

December 1988

TEMPERATURE RANGE

o to
o to
o to
o to

ORDER CODE

+70°C

NE5180N

+70°C

NE5181N

+70°C

NE5180A

+70°C

NE5181A

5-39

0+ Do GND E- E+ Eo FTOP VIEW

•

Signetics Linear Products

Preliminary Specification

NE5180/NE5181

Octal Differential Line Receivers

ABSOLUTE MAXIMUM RATINGS

TA=+25'C
YOUT

SYMBOL

PARAMETER

RATING

UNIT

800

mW

Power dissipation

Po
Vce

Supply voltage

7

V

VCM

Common-mode range

±15

V

VIO

Differential Input voltage

±25

V

ISINK

Output sink current

50

mA

VFS

Failsafe voltage

los

Output short-Circuit time

DC ELECTRICAL CHARACTERISTICS

-0.3 to Vee

V

I

sec

FS.Vcc

Vu, Vth,

VOFS

Vtta vlhJ

VIO

Figure 1_ Vlh Vlh. VH Definitions

vcc = + 5V ± 5%, O'C";; TA";; + 70'C, Input common-mode range ± 7V

PARAMETER

NE5181

TEST CONDITIONS

UNIT
Min

RIN

0

WF14330S

NE5180
SYMBOL

FS=GND

DC Input resistance

3V ..;;IVIN 1";;25V

Failsafe output voltage

Inputs open or
shorted to
GND

3

I 0";; lOUT";; 8mA, Vfallsafe = OV
I 0 ;;;>IOUT;;;> -400j.iA, Vfallsaf. = Vee

Max

Min

7

3

0.45

Max
7

kn

0.45
V

2.7

2.7

Differential Input hlgh 4
threshold

VOUT;;;>2.7V,
lOUT = -440j.iA

RS=OI

0.2

0.2

VTH

Rs = 500 1

0.4

0.4

Differential Input low4
threshold

VOUT";; 0.45V,
lOUT = 8mA

RS=OI

-0.2

-0.2

Vtl

Rs = 500 1

-0.4

-0.4

VH

Hysteresls4

FS = OV or Vce (See Figure 1 )

Vloe

Open-circuit Input voltage

2

2

V

CI

Input capacitance

30

30

pF

VOH

High level outpu1 voltage

2.7

140

2.7

lOUT = 8mA2

0.45

0.45

los

Short-Circuit output current

VIO = IV, Note 3

Supply current

4.75V";; Vee";; 5.25V, VIO = -1V; FS = OV

V
20

VIN = +IOV
VIN = -10V

mV

V
0.4

Icc

Other Inputs grounded

50

0.4

Low level output voltage

Input current

140

lOUT = 4mA2

VOL

liN

V
50

VIO = 1V, lOUT = -440j.iA
Vlo=-IV

V

100

mA

100

100

20

100

mA

3.25

3.25
mA

-3.25

-3.25

NOTES

1 Rs

IS

a resistor

In

senes with each input.

2. Measured after lOOms warm-up (at O'C)
3 Only 1 output may be shorted at a time and then only for a maximum of 1 second
4 See Figure 1 for threshold and hysteresIs definitions

AC ELECTRICAL CHARACTERISTICS

Vee = + 5V ± 5%, O'C";; TA ..;; + 70'C
NE5180

SYMBOL

PARAMETER

UNIT
Min

Max

Min

Max

tpLH

Propagatton delay -

low to high

CL = 50pF, VIO = ± IV

500

100

tpHL

Propagation delay -

high to low

CL - 50pF, VIO = ± 1V

500

100

ns

fa

Acceptable Input frequency

Unused Input grounded, VIO = ± 200mV 1

0.1

5.0

MHz

fr

Rejectable Input frequency

Unused Input grounded, VIO = ± 500mV

NOTE:
1

NE5181

TEST CONDITIONS

VIO = ± tV for NES1B1

December 1988

5-40

5.5

NA

ns

MHz

Preliminary Specification

Signetics linear Products

NE5180jNE5181

Octal Differential Line Receivers

FAILSAFE OPERATION
These devices provide a failsafe operating
mode to guard against Input fault conditions
as defined in RS-422A and RS-423A stan-

dards. These fault conditions are (1) driver in
power-off condition, (2) receiver not Interconnected with driver, (3) open-circuited Interconnecting cable, and (4) short-Circuited Interconnecting cable. If one of these four fault

conditions occurs at the Inputs of a receiver,
then the output of that receiver IS dnven to a
known logic level The receiver IS programmed by connecting the failsafe Input to
Vec or ground. A connection to Vee provides

APPLICATIONS

Vee
+VlS

-v

VFAILSAFE

L-_

I-TIE TO GROUND

IFOR AS~232C

":'"

RS-232C/R5-423C Data Transmission

vee

VH

+V

n

VL.J

r-1
L

-v.J

L

+

o------~
R&422A
UNE
DRIVER

+V,

-v

~

L.J

R5-422A Data Transmission

VOLTAGE WAVEFORMS

AC TEST CIRCUIT
Vee

+IV
_ 1V

::!
=l
~

n

.J L

December 1988

5-41

•

Signetics Linear Products

Preliminary Specification

NE5180/NE5181

Octal Differential Line Receivers

a logic "1" output under fault conditions,
while a connection to ground provides a logic
"0" There are two failsafe pins (Fs 1 and FS2)
on the NE5180 or NE5181 where each provides common failsafe control for four receivers.

INPUT

0-----1
OUTPUT

Vcc -WIr--+
R1

R8-232 FAILSAFING
The internal failsafe CirCUitry works by providIng a small input offset voltage which can be
polarity-switched by using the failsafe control
pins This offset IS kept small (approximately
80mV) to avoid degradation of the ± 200mV
input threshold for RS-423 or RS-422 operation. If the positive and negative Inputs to any
receiver are both shorted to ground or open
circUited, the Internal offset dnves that output
to the programmed failsafe state. If only one
Input open CirCUitS (as may be the case for
RS-232 operation), that Input will rise to the
"Input open CirCUit voltage" (approximately
700mV). Since thiS IS much greater than the
200mV threshold, the output Will be driven to
a state that IS Independent of the failsafe
programming. Failsafe programming can be
achieved for non-Inverting single-ended applications by raising or lowering the unused
input bias voltage as shown In Figure 2. For
VBIAS 1 4. an open (or grounded) INPUT
line will be approximately 700mV (OV) and the
output Will failsafe low. If the resistor divider is
not used and VSIAS IS connected to ground,
the output Will failsafe high due to the Internal
failsafe offset for the INPUT grounded and
the 700mV "open CirCUit Input voltage" for
the INPUT open cirCUited. Similar operation
holds for an inverting configuration, with
VSIAS applied to the positive Input and
VFS = ground.

"1AV

R2

NOTE:
Two silICon dIOdes may be used In place of A2

Figure 2. Single-Input Failsafe Programming

=-

Figure 3_ Differential Input Stage

75

INPUT FILTERING (NE5180)
The NE5180 has input filtering for additional
nOise rejection. ThiS filtering IS a function of
both signal level and frequency. For the
specified Input (5.5MHz at ± 500mV) the Input
stage filter attenuates the Signal such that the
output stage threshold levels are not exceeded and no change of state occurs at the
output. As the signal amplitude decreases
(Increases) the rejected frequency decreases
(increases).

L--~-~

__-oV~

GND

OND

Figure 4. Failsafe Input Stage

December 1988

5-42

Figure 5. Output Stage

Preliminary Specification

Signetics linear Products

NE5180/NE5181

Octal Differential Line Receivers

0.6

80
V1D =1V

Vcc~4.75V

FS=OV

V1D =1V

10
2S'C

C

80

.s

I..--:: :::::
~~p
...... ~ ~
O'C

4.0

101'C

-I--:: [;:::::
"- p-

25'C

1O'C

[ - 2S'C

~ ;;::::::

i- ..- C:::::: ~
O'C
~ P'

..llso

_,VCC =4.75V
V,D =1V
05

~

,
"-

:f

I

40

V

1/ Y

0.3

/. V
/ V
0.2

o·c

ao

0.4

/

I

2.5
4.5

4.75

0.1

0-0.2_0.4-0.8_0.& 1 _1.2-U _1.8-1.8_ 2

5.5

024

8

Figure 6. Typical Supply Current
Supply Voltage

VB

~r-r-r-r-r-r-r-r-r-~

8

0.84

~z

:-

:gG.82 :-2

----

0.10

0.88

~o.ao
>

0.58

:-

---

~ r...~
O!c

I

b-rt;

1.0

0.8

10
25'C

0.7

I..

G.6

G.58
0.54

0.2

-8~r-r-r-r-r-r-r-r-~

G.52

0.1

_~L-~~~~~~~~~

o.so

o

~ r"o.c r- f-

0.3

5.25

4.75

Figure 10. Typical V,OC

VB

5.5

VCC

phfler being measured IS grounded

I

V1D =

\
1.5V

\

,,,i-'t:

V

~

l1v
,

-1

0

"

1

2

I

I

r-

I

6

7

8

9

0"TA"1O'C,
c L =SOpF

Joo~v

f-

V 1D =-:t1V

1\ \
1.5 V

800

5

- r- ",soom~- -

[ - fj200iV

400

4
VFS(V)

VCc=5V,
FS=OV,
l=mkHz,

VOL

200

3

Figure 11. Typical FS Input Current vs
FS Applied Voltage

[ - f-

",SOOmV [ -

rt

J.

Vcc =5V,
FS=OV,
l=mkHz,
0< TA<7OOC.
c~ =SOpF

eL"',

•

Jc VA
~~

rI/

0.5

.J1-o.4

Figure 9. Input Current VB Input
Applied Voltage"

~

vicc =~~

0.9

-8

-ThIS graph applieS for all receiver Inputs, provided that the OPPOSite polarity Input of the am-

m

Figure 8. Typical Low Level Output
Voltage VB Output Current

-4

4.5

~

'OL(mA)

Figure 7. Typical High Level Output
Voltage VB Output Current

0.88

n w

~

8

'OIt(mA)

or

Lid·c

~

VOL

\

Y

L

800

'PHL(no)

200

400

800

800

'PLH(no)

Figure 12. NE5180: Propagation Delay
at Various Input Amplitudes

December 1988

5-43

Figure 13. NE5180: Propagation Delay
at Various Input Amplitudes

NE5050

Signetics

Power Line Modem
Product Specification

Linear Products
DESCRIPTION
The NE5050 is a modem for power line,
coaxial cable, and twisted-pair communications. The modem incorporates features to overcome line impulse noise
and line impedance modulation. The
modem's transmitter incorporates a Colpitts oscillator, positive logic, carrieronl -off switch, and a line driver. The
receiver has an amplifier, a limiter, an
amplitude detector, an amplitude modulation cancelling stage, an impulse filter,
and an SR flip-flop. One NE5050 can be
used to transmit and receive with Amplitude Shift Key (ASK) carrier-on I -off
modulation. With two NE5050s, Frequency Shift Key (FSK) modulation can
be implemented. The transmitter input
and the receiver output accept TTL or
CMOS serial data.

FEATURES

PIN CONFIGURATION

• High receiver sensitivity - typo
1.5mVRMS
• Receiver Input overload
protected for signals up to

70Vp.p

Dl and N Packages
+Vcc 1
HIGH·PASS
FlLTaI

AMPOtn(+) 3

• High data rates - 300kbitls ASK
NRZ over twisted-pair
• The modem reaches the Nyquist
limit of 1 bit per carrier cycle
• Has IIsten-whlle-talklng for carrier
sense multiple access/collision
detect (CSMAlCD) networking
capability
• Increased noise immunity with
balance interstage ports for
bandpass filtering
• Flexible oscillator can be made
with LC tank (Colpitts). with
crystal (Pierce). or accept
external clock

DETIN(+) 4

AMPOUTI-) 6
DETOUT(+) 7
DETOUTI-) 6

AM

REJECTION

.....

IM:.u~1

--~
70PVlEW

NOTE:
1 SOl- Released In large SO package only

• Signals are processed in realtime making this modem suitable
for repeater/carrier translation
applications

APPLICATIONS
ORDERING INFORMATION
DESCRIPTION
20-Pln Plastic DIP
20-Pin Plastic SOL

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70·C

NE5050N

+70·C

NE5050D

• Twisted-pair communications
• Coaxial cable communications
• 120/277VRMS. 50 or 60Hz. power
line communications

BLOCK DIAGRAM

October 16, 1987

5-44

853-1281 90944

Signetics Linear Products

Product Specification

Power Line Modem

NE5050

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vee

Supply voltage

PARAMETER

18

V

VLOGIC

Logic supply voltage

18

TA

Ambient temperature range

TJ

Junction temperature range

-55 to +150

·C

TSTG

Storage temperature range

-65 to +150

·C

o to

V

+70

·C

Maximum power disSipation 1
700
mW
PDMAX
NOTE:
1 The power dlsslpallon IS based on Vee = 12V, TJ = + lS0'C, TXOFF Icc = 20mA, TXON Icc = 50mA,
8JA = 61 ·C/W 20-pln plastic package

DC ELECTRICAL CHARACTERISTICS

TA = + 25·C, Vcc = 12V, F carner = 120kHz, data = NRZ, 50% duty cycle unless
otherwise specified.

PARAMETER

SYMBOL
Vee

Supply voltage

Icc

Supply current

LIMITS

TEST CONDITIONS

TXoFF
TXON1

UNIT

Min

Typ

Max

10

12

16

V

5

8

11

rnA

18

24

30

rnA

5

16

V

100
300

220
660

mW
mW

Icc

Supply current

VLOGIC

LogiC voltage

PD

Power diSSipation

V,HM,N

TX TTL Input

TXON, Pin 19

V,LMAX

TX TTL Input

TXoFF, Pin 19

0,8

V

VOLMAX

RX open-collector output

IOL = 5mA, Pin 11

0.4

V

IOLMAX

RX open-collector output
TX data rate 2
RX data rate 2

RXoFF, TXOFF
RXON, TXON, lOOn load
2.4

V

5

rnA

fCXR=120kHz, 500kHz

Pin 11
DC

lk

300k

bitls

fCXR=120kHz, 500kHz

0.1

lk

300k

Carner cycles per bit, TX and RX2

1

bitls
cycle

Broadband I/O ports, carrier
RX Input sensitivity

1:1 Input transformer

RX Input signal level

Vee ± 35V = -25V, +51V

RX Input Impedance

Pin 20

RX line Impedance modulation
rejection

120HzAM 2V/20mV, lkblt/s

RX carner frequencr
RX detector differential Input
Impedance
PSRR

3.5

1.5
70
9

kn

40
0.1

mVRMS
Vp_p

dB
120

500

kHz

Pin 4, Pin 5, each

27

RX power supply releCtlon ratio

60Hz and 120Hz

80

dB

Broadband port Impedance

RXoFF and TXOFF

7.3

kn

TX output signal level

TXoN, lOOn load

8

Vp_p

TXoFF
TXON

40

kn

1.2

n

External oscillator

+140

ppml"C

LC oscillator

+0.23

%I"C

TXON, Pins 15, 17

40

rnA peak

TX dnver output Impedance
TX driver output Impedance
TX amplitude temperature drift
TX amplitude temperature drift
TX output current capability

October 16, 1987

5-45

kn

•

Signetics Unear Products

Product Specification

Power Line Modem

NE5050

DC ELECTRICAL CHARACTERISTICS (Continued) TA = +25°C, vee = 12V, F carrier = 120kHz, data = NRZ, 50% duty
cycle unless otherwise specified.
SYMBOL

PARAMETER

LIMITS

TEST CONDITIONS
Min

TX output THD (total harmonic
distortion)
TX line drive amplifier BW

UNIT

Typ

Max

TXoN, LC oscillator

1

2

At 6dB gain

500

TX carrier frequency"

DC

120

%
kHz

500

kHz
ppm/oC

TX oscillator temperature drift

Temperature range

+60

TX OSCillator initial frequency
accuracy

Same LC tank

±1

%

TXOFF

-90

dBmO

TX carrier feed1hrough (leakage)
ABBREVIATIONS:
TX = transmitter
RX = receiver

NOTES:
1 TX looped back 10 RX, data = 1kblt/s TTL, NRZ, 50% duty cycle ASK.
2. The NE5050 modem reaches the theoretical maxtmum data denstty for a given (fixed) carner frequency. ThiS limrt is set by the maxtmum data
bandwidth required before intersymbol Interference occurs. The minimum specdled limits are not tested in production. They are guaranteed by deSign
and by characterization.

PIN FUNCTION DESCRIPTION
Pin 1: +Vcc
Fordecoupling Vee to ground a O.Ij.tF capacitor must be placed close to Pin 1 and Pin 18.
Pin 2: CHPF
High-pass filter, rejects 60Hz and ns harmonics, rejects low frequencies, directing them to
ground. Capacnor to ground: CHPF = 1OnF for
fCXR = 120kHz and CHPF - 4.7nF for fCXR
300kHz. The input amplifier prOVides a
high-pass function: a + 20dB/ decade frequency response, with a DC attenuation of
-50dB. A frequency of 100kHz is amplified by
+ 24dB. The -3dB point of thiS high-pass filter
is given by the equation:

=

109 /CHPF (F)

= L3dB

(Hz)

Pin 3: OUTI
RX amplifier differential (+) output. Low impedance output. See Pin 6. Pin 3 can be
connected to Pin 4 directly. A differential,
bandpass filter can be connected from Pins 3,
6 to Pins 4, 5. If LC values are used, they are
the same as the oscillator LC values (see
Pins 13 and 14). The BW_3dB is controlled by
the series resistors Rt and R2. An external
active filter providing gain can improve the RX
sensitivity and filter out CW interference.
Pin 4, Pin 5: IN1, INz
AM dertector (±) inputs. High-Impadance inputs - 27kn each. They require DC bias
voltage from Pins 3 and 6 or around 4.5V. Pin
3 can be connected to Pin 4 directly. Pin 6
can be connected to Pin 5 directly. A differential bandpass filter can be connected from
Pins 3, 6 to Pins 4, 5. If LC values are used,
they are the same as the oscillator LC values
(see Pins 13 and 14). The BW_3dB IS controlled by series resistors. An external active
October 16, 1987

filter providing gain can improve the RX
sensitivity and filter out CW interference.
Pin 6: OUTz
RX amplifier differential (-) output. Low impedance output. See Pin 3. Pin 6 can be
connected to Pin 5 directly. A differential
bandpass filter can be connected from Pins 3,
6 to pjns 4, 5. If LC values are used, they are
the same as the oscillator LC values (see
Pins 13 and 14). The BW_3dB is controlled by
the series resistors Rt and R2. An external
active filter providing gain can improve the RX
sensnivity and filter out CW interference.
Pin 7, Pin 8: CDET
Amplitude detector (±) output capacitor between Pins 7 and 8. tDET is the time it takes
for CDET to charge from OmV to 50mV, where
50mV IS the detection threshold. The detector
delay time, tDET, affects the receiver's jitter.
tDET is a term in a sum of delays, the sum
being the total receiver delay, tD' See below
in 'Receiver Delays' the relation between tD
and the maximum M rate. The CDET capacitor value is given by:
CDET (F) = tDET (sec)/105
Pin 9: CAM
Une impedance modulation rejection capacitor. A O.1j.tF capacitor to ground provides
about 4s of delay for the transition from
receive data to standby. The CAM value is
determined in function of the bit rate, or, more
precisely, minimum bit time, to assure proper
capture of leading bns In a bit stnng or In the
preamble. It is a measure of the "readiness"
of the receiver to switch from the "standby"
mode to the "receive data mode" with no
loss of leading bits. A low CAM value will
make the modem react faster (shorter delays)
In both transition directions: from "standby"

5-46

to "receive data" (incoming or departing
messages) and from "receive data" to
"standby" (absence of data traffic). Its value
should be:
CAM (F) = 10- 4/bit rate [bits/s]
Pin 10: CIMP
Impulse noise rejection capacnor. At lkbn/s a
10nF capaCitor to ground provides 350j.tS of
delay and impulse rejection. This capacitor
determines the receiver impulse noise immunity (transmission channel with non-Gaussian
noise). tlMP is the time it takes to ramp up or
down the CIMP voltage (the beginning of the
ramp is delayed by toET)' The shortest M
should last longer than the widest impulse.
tlMP is a term in a sum of delays, the sum
being the total receiver delay, tD' See 'Receiver Delays' for the relation between tD and
the maximum bit rate. The CIMP capacitor
value is determined by the equation:
CIMP (F) = tlMP (s)/85kn
The following equation determines tIMP:
Maximum rejected or expected impulse
noise width (s) < tlMP (s)
Pin 11: RX Data Output
Open-collector RX output. RX data output.
IOLMAX = 5mA - VLOGIC/RpULL-UP
Pin 12: CFO
Oscillator feedback input. CFO - 27 to 51 pF
capacitor between Pins 12 and 13.
CFt = capacitor between Pins 12 and GND. If
the on-chip oscillator is used, CFt may be
omitted. If external OSCillations are injected at
Pin 13, CFO must be removed and CFt must
be connected to GND. Grounding Pin 12
disables the oscillator.

Product Specification

Signetics Linear Products

Power Line Modem

Pin 13: Oscillator 1/0
Colpitts LC oscillator tank, Pierce crystal
OSCillator, or external oscillator input
On-chlp LC oscillator - oscillator output.
External oscillator tank present. Parallel LC
components attached between Pins 13 and
14. CFO attached between Pin 12 and Pin 13.
A resistor between Pins 13 and 14 can
decrease the oscillation amplitude to the
deSired level. Amplitudes above 2V peak may
have THO> 2%. CF1 is not used. The amplitude varies with temperature; thermistor compensation recommended at Pin 16.
On-Chip crystal oscillator - oscillator output. Two external capacitors In series, C13
and C14. C13 is connected to Pin 13 and C14
is connected to Pin 14. The external crystal IS
attached between Pin 13 and the connection
of C13 and C14 An optional inductor L,
attached between Pins 13 and 14, tuned at
the OSCillation frequency by C13 and C14
prevents oscillations at the crystal overtones.
CFO and CF1 are not used.
External oscillator - oscillator Input. Parallel LC components attached between Pins 13
and 14 provide bias to Pin 13 and perform
bandpass filtering. If a square wave is generated from a microprocessor by clock diVision,
a series LC from the divider output to Pin 13
Will perform additional bandpass filtering.
CF1 = 0.1 ,",F is connected to ground. CFO IS
not used. If a sinusoidal wave is available, a
Son resistor may replace the parallel LC
bandpass filter and a O.I,",F capacitor may
replace the senes LC bandpass filter. The
amplitude IS constant over temperature.
Pin 14: +Vcc/2
Oscillator bias at + Vcc/2. A 0 I,",F decoupiing capacitor to GND IS optional. Parallel LC
components attached between Pins 13 and
14.
Pin 15: TX carrier Output (NPN
Transistor Base)
Transmitter broadband output. Can dnve
40mA peak (BOmA peak non-repetitive).
NPN external Darlington transistor Dnves 1n loads.
NPN external transistor drive In-0.SW-RE1 to Pin 16 for Ion loads.
On-Chip driver - Ion RE1 between Pins IS
and 16 for Son loads.
Pin 16: TX Line Driver Feedback
RFEEDBACK adjusts the dnver amplifier gain
Minimum gain (RFEEDBACK = 0) is 2 (6dB). A
thermistor can compensate the LC oscillator
amplitude vanation. RE1 resistor (and NPN
EB junction) to Pin IS. RE2 resistor (and PNP
EB junction) to Pin 17. The CDRIVE coupling
capacitor is in senes With the RDRIVE resistor
from Pin 16 to Pin 20. The RDRIVE value IS the
October 16, 19B7

NE5050

assumed line Impedance. The CDRIVE impedance IS 1/(2 X fcxR CDRIVE).
Pin 17: TX Carrier Output (PNP
Transistor Base)
Transmitter broadband output. Can dnve
40mA peak (BOmA peak non-repetitive).
PNP external Darlington transistor Dnves 1n loads.
PNP external transistor drive In-5.0W-RE2 to Pin 16 for Ion loads.
On-Chip driver - Ion RE2 between Pins 16
and 17 for 50n loads.
Pin 18: Ground
Pin 19: TX Data Input
Transmitter TTL data Input. LogiC 1 Will turn
the transmit dnver on, and sinusoidal carner
Will be sent to the line from a low Impedance
source LogiC 0 Will turn the dnver off, to high
output impedance.
Pin 20: RX Carrier Input
Receiver carrier Input. Withstands an overvoltage of + Vee ± 3SV. DC bias connected
through the line coupling transformer secondary to +Vee (Pin 1). The CDRIVE coupling
capacitor IS in senes with the RDRIVE resistor
from Pin 16 to Pin 20.

DESCRIPTION OF OPERATION
The NE50S0 modem has been deSigned for
transmitting and receiVing control and data
signals over the AC power lines, coaxial
cables and twisted-pair cables. The modem
overcomes line Impulse nOise and line impedance modulation. Two carrier modulation
methods can be used: carner on/off ASK,
NRZ data and non-coherent FSK
The power line IS not an Ideal medium for
communicallOn. The line nOise, Interference,
and losses are oaused by. Impulse noise, CW
Interference, line Impedance modulallOn, and
dlstnbutlon transformer attenuation. N E50S0
was designed to support both ASK and noncoherent FSK communicallOns In thiS enVironment.

Listen-While-Talk
The IC modem IS always In the receive mode,
even when transmitting (it receives Its own
carrier) ThiS capability permits remote RX
and TX functionality testing for each system
node In the receive mode, the modem receives carner signals from other transmitters.
In the transmit mode, the modem transmits
carner to other receivers and receives its own
carner.

On-Chip Collision Detection
The IIsten-whlle-talk capability enables thiS IC
to perform CSMAlCD (carner-sense, multiple-access/colliSion detect) networks. ColIl-

5-47

sian is deteoted when the local TX intends to
transmit and the line is not clear.

In Dense Data Traffic
The RX data output (RXOUT) does not have
time to go into the standby (lower power
consumption, inverted logiC) mode. In this
case the RXOUT is in positive logiC (carrieron = I, carner-off = 0). A collision is detected
at the local node when the local TX IS off and
the local RXOUT = 1. Collision: remote carner
present and detected. Abort local transmission. If, however, standby occurs (bursts of
high-speed data) a proper value of CAN will
Insure capture of all leading bits except for
the first "I 0" transition.

In Rare Data Traffic
The RXOUT is in standby most of the time. In
thiS case the RXOUT logic mode is Inverted
due to a designed-In offset present in the AM
rejection and ImpuJse filter circuits. A Jogic
sequence from the Jocal TX insures proper
RX offset adjustment (preamble, the first
"10" bits). The colliSion detecllOn proceeds
as In the dense data traffic case. The transllIOn time from the last received bit "I" to the
standby mode is proportional to the value of
the AM rejection capacitor at Pin 9. For
CAM = 10nF, the "receive data" to "standby"
transition occurs after 4 seconds from the last
"1". Therefore, long stnngs of "O"s can be
transmitted and receIVed. The standby function may be disabJed with proper bias at Pin 9
(externaJ components).

TX-to-RX and RX-to-TX
Switching Times
With the listen-while-talk capability the TX-toRX and the RX-to-TX switching times have
the meaning of TXON"to-TXOFF and TXoFF-tOTXON switching times, respectIVely. The TXto-RX and RX-to-TX minimum sWitching times
can be calculated from the maximum data
rate. Since one bit can last a minimum of 3j.tS
(NRZ ASK data), this may be conSidered the
minimum switching time.

Data Rate
The maximum data rate is 300kblt/s NRZ
ASK. ThiS data rate was achieved on a
twisted-pair cabJe With a IS0kHz, SO% duty
cycle square wave for data. The data rate
depends on the BPF (between Pins 3 - 4 and
5 - 6), on the AM detector capacitor for delay,
CDET (between Pins 7 and B), on CAM (Pin 9)
for capture of Jeading bits, and on the desired
Impulse nOise immUnity for delay, C'MP (Pin
10).

AC Line Coupling Network
One or two (120V or 240V and 277V AC
RMS) coupling capacitors rated 600V are
connected in senes With the primary of a 1:1
transformer and connected to the AC line.
The transformer secondary may be tuned to
the carner frequency by a capacitor (TOKO

•

Signetics Linear Products

Product Specification

Power line Modem

transformer, low data rates) or no secondary
tuning capacitor for higher data rates (AlE
Magnetics transformer). Two back-to-back
zener diodes must be placed between Pins 1
and 20 for the IC transient protection
(IN4744 or lN627S). The transformer secondary carries DC bias current between Pins
1 and 20 of the IC. This coupling network
itself attenuates to below the RX input sensitivity the SO or 60Hz and their harmonic
frequencies. In a coaxial cable application the
transformer can be replaced with a coupling
capacitor.

Receiver (RX)
The typical RX sensitivity is 1.5mVRMS. For
less sensitivity, adjust the turn ratio of the
coupling transformer or insert loss in the
bandpass filter. The RX-only function can be
implemented by not using the oscillator and
by grounding the TX input. The maximum
data rate is 300kbitl s. The power supply
rejection ratio (PSRR) is 80dB for 60Hz and
120Hz. The RX is composed of the following
blocks:
The Input Amplifier/limiter limits its output
signals to 1.2Vp_p. The maximum input carrier
signal can be 70Vp_p. The gain is 24dB. The
input amplifier bandpass characteristic has the
upper -3dB frequency internally fixed at
300kHz. The lower -3dB frequency is adjustable with the CHPF capacitor from Pin 2 to
GND. For maximum RX sensitivity CHPF
= 10nF at fCXR = 120kHz. A CHPF = O.Ij.lF value attenuates 60Hz by SOdB and 120Hz by
4SdB.
The Bandpass Filter is differential RLC
bandpass filter which can be connected from
Pins 3, 6 to Pins 4, S. The LC values are the
same as the oscillator LC values (see Pins 13
and 14). The formulae relating the BW-3dB to
the RLC values are:
BW_3dB / WCXR
=1/0

= (WCXR * L) / (2 * R)

BW_3dB / wCXR = 1 / (WCXR *2 * C • R)
=1/0
BW-3dB

= (WCXR * WCXR' L) / (2' R)

BW_3dB = 1 / (2 • C • R) and
WCXR = 2 X fCXR.
If no bandpass filter is required, connect Pin 3
to 4 and Pin 5 to 6 (R1 = R2 = On).
The Amplitude Detector is a Gilbert phase
detector with a single differential input. The
compared signals are always in phase and
the demodulated output is a full rectified
wave, function of the bias current, the carrier
amplitude, and the collector load. The detected voltage is developed across a differen-

October 16, 1987

NE5050

tial capacitive load between Pin 7( + ) and Pin
8( -). DC offset is caused by line impedance
modulation.
The AM Rejection Circuit stabilizes the DC
average value of the envelope by adding or
subtracting a series voltage to the voltage of
the detector capacitor. The AM rejection is
40dB at a modulation rate of 120Hz. The
value of the AM rejection capacitor CAM (Pin
9 to GND) determines the transition times to
and from receive data and standby.
The Slicing Comparator has current output
and a fixed threshold of SOmV.
The Impulse Filter consists of a capacitor,
C'MP, at the output of the comparator, from
Pin 10 to GND. This capacitor is charged or
discharged with constant current from the
comparator, causing the voltage variation to
be a constant slope In time. Narrow current
impulses will not last long enough to fully
charge or discharge the capacitor.
2VBE Voltage Hysteresis provides a voltage
interval in which the C'MP voltage ramps and
in which both inputs to the SR flip-flop are
zero.
The Flip-Flop is an SR type, with an opencollector transistor output at Pin 11. The
transistor can switch a maximum load of
SmA.
Receiver Delays and Maximum Data
Rate
The total receiver delay is a sum of delays,
where tDET (sec) is the detector delay, t'MP
(sec) is the impulse filter delay, and 2j.ls is the
approximate receiver delay with no CDET and
no C,MP:
tD (sec) = total receiver delay
= tDET (sec) + t'MP (sec) + 2j.ls
The maximum bit rate, in the no-return-tozero, amplitude shift keying data format is
determined by: Maximum bit rate MRZ ASK
(bitlsec) < lltD (sec- 1)
NOTE:
The COET and C 1MP values so calculated Bre for
guidance and the user shall determine the optimal
performance values In a range between 0.1 times to
10 times the calculated values (power line environment assumed). For twisted-pair or coaxial cables
the calculated values are close to optimal. Based on
power hne applications made at 100 bits/sec and at
50 kbltsl sec, the C1MP I CDer capacitor ratio ranges

from 100:1 to 1:1.

Transmitter, TX
The transmitter includes an oscillator, a line
driver, and a drive sWitch.

5-48

The TTL Switch is a low power TTL gate that
switches on/off the bias current for the line
driver. A logic "I" at Pin 19 (TX,N) enables
the line driver and carrier is being sent on the
line. A logic "0" disables the driver.
The Oscillator is a differential transistor pair.
It can be configured as a Colpitts LC oscillator, as a Pierce crystal oscillator, or used with
external Input (microprocessor clock divided
to the carrier frequency). When the TX drive
is off, the carrier leak is less than -90dBmO.
Pin 18 can be used as input for an external
oscillator. Grounding Pin 12 disables the
oscillation process.
The Line Driver is a class AB push-pull stage
with optional external complementary transistor pair for increased current capability. The
TX output impedance is 40n in the off-state
(receive mode) and less than 2n in the onstate (transmit mode). Note that in the transmit mode one receives its own signal. To
increase the amplitude of the transmitter, add
a feedback resistor in the driver amplifier
feedback path at Pin 16.
By itself the NES050 is capable of driving a
consumer line impedance of SOn (40mA
peak/80mA peak non-repetitive), the THO
being less than 2%. With complementary
transistors, IOn industrial loads can be driven. With complementary Darlington transistors, 1n industrial loads can be driven.
One design objective was to provide the user
with a flexible IC modem for residential as
well as for industrial AC lines, for twisted-pair,
and for coaxial cables. The IC modem can be
used for control functions and data applications. Practical observations of power line
noise point to a data rate upper boundary of
1kbitlsec. The main sources of interference
are the light dimmers. Software for error
correction can be used for improved error
rates. Two system configurations can be
implemented: an ASK system and a noncoherent FSK system. The non-coherent FSK
system can continue to transmit ASK data if
the other channel is made unusable by CW
interference. High-voltage transient protection and filtering are accomplished with userselected external components.
Additional flexibility is provided by the chip
architecture: one-IC real-time repeater, oneIC dual-frequency gateway, external oscillator
input port, the listen-while-talk capability
(CSMAlCD), immediate TX-to-RX switching,
ASK and FSK, and ASK-multinode singlefrequency network.
The modem can be used for control systems
and data applications in homes and other
consumer environments and in industry.

U>

i

f...

!"

~

-

::J

~:.. ~:~ n:,

~

-

!::
~

.,.

~

RI2
1

TIW

J

.:!f~

~
IC~

-I1

Cut..

1"ItIIOV
--f

1

'L

)

L1

EJICII-aII.IIII
_ 'IOIID-l'II7VX-_

GND

PliP
17

111.

-

..

Il

~fo

- II.
15

~

INPUT

.L

Mel(

1 ~==

AMPU_

ZENER1

.

fEED.

:-c;

~

fl

CD

-.,.

3

-

IIIICIIVE

~

.

..

1lIw

110

~

a.
c:

Q.

CAl

~r"

II

IIIk

IIlItoo

3:

11·

..

CD

~

3~

0

~
~
Co.c

RIll
1

+Voc·+1IV

cO

Vee/2
14

LC

0UIIIU1'

CAl

12

: ~R I l FLHIDPJ
L.....-

L:~=-~

DDECrOR -1

.~

ZENER 2

1111_

1
Vee

2

C-

a

OUT,

R1

r~"

1.1k

I~g

4

I

IN,

.."

r-~

•OUT•

7
CDm

AI
1I.1k
IPf

C"

•Com •

CAlI

10

CW

--1L

...¥3

CIPf

I:~

r;:S
~
Z

m
01

•

Figure 1. Typical Application Circuit for 1kbltls on the 120/277V AC Line

o
01
o

u

i

~

o

:>

Signetics

AN1951
NE5050: Power Line Modem
Application Board Cookbook
Application Note

Linear Products

Author: Michael J. Sedayao

INTRODUCTION
Applications Disclaimer
The applications outlined within this cookbook In no way specify the absolute maximum
performance of the NE5050 Power Line Modem. They are merely examples given to
show the flexibility of the part. In general, the
external components used for each application tend to be the limiting factors In each
application. For example, the component drift
for capacitors that provide a load on the
OSCillator would cause a corresponding drift in
the oscillator frequency, although there is
nothing wrong wrth the chip itself. On the
other hand, external drive transistors provide
a larger transmitter voltage than what would
normally be available from direct drive with
the chip.
Only careful characterization of the operating
environment (whether it is the power line,
twisted pair, or coaXial cable) coupled with a
knowledge of the external component limitations, can ensure reliable operation for a
given application. Often, operating problems
originate With an applications fault rather than
with the chip itself.
One reason that the part may not always
work in every situation is the same reason
that It can work in so many situations - the
part is extremely flexible. Operation is dependent on the values of the external components. For instance:
• To change the carner frequency,
change the oscillator capacitor and
Inductor. To receive the same signal,
however, the BPF values must also be
changed to the same values. Active
filters or no filters can be used. The
tuning capacitor must also be changed
so that the transformer secondary locks
onto the carrier. The oscillator can also
be driven with an external source.
• To adjust the limiting of the data rate,
the detection capacitor has to be
changed. If the data rate is increased
without adjusting this capacitor, the bit
rate Will be RC-filtered out.
• Adjusting the Impulse capacitor will
provide protection from transients of a
certain duration, but leaves a
vulnerability to longer ones or a
succession of smaller ones.
Each of these cases should illustrate the fact
that the performance of the board is extremeDecember 1988

Iy application and environment dependent.
The environmental parameters and goals of
data transmission should be determined before speCifying component values. Proper
operation depends on it.

Summary of Operation
The AC power line is, in general, not ideal for
data communication. Impulse nOise, large
magnttude voltage transients ( > 1kV tyPical),
line impedance modulation, and other factors,
have prohibited ItS use as an effective medium for transmitting data and control Signals.
The NE5050 Power Line Modem (PLM) has
been designed to overcome these problems
while affording the user the flexibility of tailoring the deSign to his/her own needs. The
PLM can be used to transmit over power lines
or twisted-pair cables using two forms of
modulation - carrier on/off ASK (Amplitude
Shift-Keying) and non-coherent FSK (Frequency Shift-Keying). To use it in the FSK
mode, ·two devices will be required for each
transceiver in order to bandpass and generate the two different frequencies representing
logical 0 and 1. If one of the two frequencies
used fails, the remaining frequency can be
used in the ASK mode. The applications
referred to In thiS cookbook only refer to the
Single-carner ASK form. Some of the features
of the IC include:

Listen-While-Talk
The modem is always in the receive mode,
even when transmitting (it receives its own
signal). ThiS capability permits RX and TX
remote functionality testing for each system
node since it requires no other transceivers.
In the receive mode, the modem receives
carrier signals from other transmitters. In the
transmit mode, the IC transmits an ASK
carrier to the other receivers, including its
own. It is up to the user to design protocol to
arbitrate ownership of the line. In some protocols, such as in General Electric's HOMENET®, the listen-while-talk feature is not desired and so the receiver is disabled during
transmiSSion mode.
On-Chlp Collision Detection
The listen-while-talk capability enables a controller to perform CSMAlCD (Carrier Sense,
Multiple Access/Collision Detect) functions.
To summarize (for further information, the
reader is referred to IEEE 802.3 and to
general articles describing ETHERNET or
other probabilistic network protocols), any

5-50

node can access the line to transmit signals
at any time provided the line is not being
used. The procedure IS as follows. A receiver
listens to the line to see if there are any
carriers present (Carrier Sense). Every receiver is also listening to the line (hence, Multiple
Access). If a transmitter is on, each node
waits until the line is free before transmitting.
Priorities may be established by the controller. A collision is detected if, while transmitting a message, an incoming transmission
Originating from another node is detected.
The PLM performs a similar operation for
both dense and rare data traffic situations. In
dense data traffic, the RX data output
(RXOUT) does not have time to go into the
standby (lOW power consumption, inverted
logiC mode). In this case, the RXOUT is in
positive logic (carrier on - I, carrier off = 0).
A collision is detected at the local node when
the local TX is off and the local RXouT - 1.
Therefore, a remote carrier is present and
has been detected, so abort local transmission. The line is busy. Wait until the line is
clear.
In rare data traffic, the RXOUT is usually in the
standby mode. In this case, the RXoUT logic
mode is inverted due to a designed-in offset
present in the AM rejection and impulse filter
circuits. A "10" logiC sequence from the local
TX insures proper RX offset adjustment (the
preamble contains the first two "10" bits) and
collision detection can be performed with the
next "10" bits. The collision detection proceeds as in the dense data traffic case. The
transition time from the last received bit "I"
to the standby mode is typically 4 seconds
and this time is independent of the data rate.
This enables long strings of "O's" to be
transmitted and received.
To eliminate the standby mode and to have
the modem in the receive-data mode at all
times, the bias at Pin 9 should be altered. A
10M!2 resistor from Pin 9 to a potential of
2.2Voc will perform this change. The 2.2V
potential may be generated between two
resistors: 1M!2 from Vee = 12V and 220k!2 to
ground.

Power Supply Decoupllng
(C1 and C2)
Capacitor C, = 0.1 p.F at Pin 1 decouples the
supply voltage, Vee. The capaCitor
C2 = 0.1 p.F at Pin 14 is optional and decoupies the supply for the OSCillator section. This

Signetics Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

FEED-

TX,N

GND

PNP

NPN

BACK

VCC /2:LC

LC

CFO

AN1951

RXoUT

Figure 1. Block Diagram

supply, Vcc/2, IS Internally generated. Cl IS
essential for clean operation and should be
placed as close as possible to the IC, between Pins 1 and 18.

AC Line Coupling
The line transformer, a Toko Amenca 707VXTl002N, has a pnmary-to-secondary cOil ratiO, Ll:L2, of 1:1. One end of cOil Ll goes to
the power line via line capacitor CLINE. The
secondary signal IS tapped off between L2
and La and then goes to the receive Input (Pin
20.) The other turn ratio IS Ll :L3 at 1·4. The L2
secondary IS connected between Pins 1 (Vcd
and 20 (RX,N) It carnes about 1mAoc current
Into Pin 20 for biaSing. The L2 + L3 secondary
IS tuned to the carner frequency by a tUning
capacitor CTUNE = 6.8pF. This transformer IS
sUitable only for data rates up to 10kBlts/sec
because of envelope distortion
To tune the transformer for maximum sensItiVity, connect a BNC "T" connector to the
output of the waveform generator One output
should go to an oscilloscope and the other
should be connected to the prongs of the
power cord of the board (make sure ground IS
also connected to one prong). Then send the
100% AM modulated pulse train (ASK) to the
board. The carner envelope IS a square-wave
pattern. Tune the transformer for maximum
carner amplitude. To do this take a jewelhead screwdnver and adlust the transformer
core. MaXimum sensitivity IS reached at maxImum amplitude at the carner frequency
Another manufacturer that provides good
transformers for both power line and twlstedpall communication IS AlE Magnetics (Address and telephone numbers for TOKO and

December 1988

AlE Magnetics are listed In the External
Components Secl1on).

Line and Tuning Capacitors
(CLINE and CTUNE)
CLINE = IIlF AC-couples the transformer

to
the power line and IS rated to Withstand 600V.
Its main funcMn IS to filter out the 60 and
120Hz signals from the line power and to
pass only the higher frequency carrier signals.
CLINE and the primary Inductance of the
transformer act as a voltage diVider that
attenuates 60Hz Signals by 100dB line voltage Signals are less than a millivolt on the
secondary of the coupling transformer. Remember to discharge thiS capacrtor before
removing the Insulating backplane and
changing components.
CTUNE = 6.8nF tunes the transformer secondary Winding to the carner frequency (100kHz)
Make sure to change thiS capaCitor In addition to the LCs of the OSCillator and bandpass filter sections when changing the carner
frequency.

TRANSCEIVER EXTERNAL
COMPONENTS
Figure 1 IS a block diagram of the NE5050. It
comes in a 20-pln DIP (Dual In-Place package) in both plastic and SO (Small Outline).
This section descnbes the external components that must be added and the characterIStiCS to expect at those pins.

Input carner Signal can be 70Vp_p, centered at
Vee. The amplifier gain IS 24dB at the carner
frequency The Input amplifier bandpass charactenstlc has an upper -3dB frequency Internally fixed The lower - 3dB frequency IS set
by CHPF. CHPF actually suppresses the lower
order harmOniCs. With CHPF = 100nF, 60 and
120Hz are rejected more than 40dB (see
Figure 2). For lower values of CHPF, thiS
rejection Increases along the frequency spectrum. For a 1nF capaCitor, amplrtler response
has large peaking near 500kHz. Response for
values of 10, 100, and 1000nF are also
shown over the frequency range
0.01 -100MHz.
CHPF IS connected from Pin 2 to ground For
carner frequencies above 100kHz, typical
values for CHPF are between 2 and 20nF. The
amplifier has d,fferenttal outputs (Pins 3 and
6). The DC voltage at these pins is 4.6V.
Inter-Stage Bandpass Filter R 1, R2,
CBPF, LBPF (Pins 3, 4, 5, 6)
If all necessary bandpass flltenng IS performed in the line-coupling network, then the
BPF between Input amplifier output and AM
detector Input IS not needed It IS also POSSIble to bypass use of the fllter In most twlstedpall applications. Otherwise, for ASK operation, LBPF and CBPF should match the LC tank
components Losc and Case of the OSCillator
in order to have effectIVe carner sense. The
carner frequency IS Simply defined as

1
WCXR

Receiver
Input Filter CHPF (Pin 2)
The Input amplifier limits ItS output Signals to
1.2Vp_p differential. On Pili 20, the maximum

5-51

= v'LBPF

X CBPF

The bandpass charactenstics are governed
by the followlllg equations relating 3dB band-

•

Application Note

Signetics Linear Products

NE5050: Power line Modem Application Board Cookbook

operallOn, but, if an increased data rate is
desired, the value of the capacitor should be
reduced. Similarly, for a longer delay and
reduced data rate, Increase COET (see Figure
4).

60
50

40

iii

os

30
20

g

10

1"F
100"F

;E

iii

§

-10

.'0nF

r---

1nF

~ -20
<-30

"

/

-40

X

K /

X

K

/

Y

/

II COET IS removed altogether, a reduction in
signal delay should be observed (full-wave
rectification). There Will stili be a signal If the
Impulse capacitor IS connected. Removing
both COET and CIMP should eliminate signal
delay enlirely.

\
\

/

\

1111\

\ / '\
\

. / . / .7

L

-50
-60
0.01

y/ / 1
V /
y/ /

~" k' /
X

\

104

1.0

FREQUENCY (Hz)
Figure 2. Receiver Amplifier Gain vs Frequency for Different Values of CHPF
width to carrier frequency WCXR and components R " R2 = R, LBPF, and CBPF·
(WCXR 2 X LBPF)
BW-3dB =
(2 X R)
BW 3dB
-

1

=-----(CBPF X 2 X R)

These equations can easily be manipulated to
express the Quality factor, Q:
BW_ 3dB

= (wCXA

X LSPF)

(2 X R)

WCXA

Q

BW-3dB
WCXA

(WCXR X CBPF X 2 X R)

Q

Since this IS a passive filter, a good deal of
signal attenuation should be expected. If
there is trouble getting signals through, consider shorting out the bandpass by shorting
Pin 3 to Pin 4 and Pin 5 to Pin 6. If this does
not work, trace signal from RXIN (Pin 20) and
follow through.
Depending on the filtering configuration, PinS
4 and 5, the AM detection Input requires DC
biasing. If no DC path IS provided from Pin 3
to 4 and from 6 to 5 (senes capacitors
present for DC open-CirCuit), then the network
in Figure 3 can be used.
Active bandpass filters may be used If gain IS
desired in the signal. This allows more room
for tweaking. Remember, the goal IS to bandpass the broadband signal (WCXR = 100kHz

for the Industnal operation) and not the baseband signal (1 kBlts/s for the same application) as can be seen from the above equalions For more details on alternative BPFs,
see the section on High Performance Industnal OperallOn.
AM Detection COET (Pins 7 and 8)
The capacitor COET IS the load across the
collectors of a Gilbert multiplier cell (PinS 7
and 8) that IS being multiplied by Itsell. So
compared signals are always In phase and
demodulated output IS a function of carner
amplitude (hence, detects AM signals), bias
current, and collector load. (Internally there
are resistors In the collectors of the cell so
the part will run without COET Included.) Since
It IS the load, it has to be charged and
discharged, and thus delays the transition of
the signal. COET Introduces a delay In signal
transmission because of its integraling action.
The combination of COET and the collector
resistors provides an RC low-pass "'tenng
action on the received signal The carrier
(broadband) IS filtered out and only the envelope (baseband) is passed. Consequently,
COET provides the limiting value for the data
rate. The 4.7nF value IS fine for 1kBillsec

>

5.1K

l

PIN 4

T

C BPF

4.TnF

R2

PIN 6
5.1K

AM Rejection CAM (Pin 9)
The AM releclion CirCUit tracks the average
DC value of the envelope by adding or
subtracting a senes voltage to the voltage on
the COET. (It operates as a negative feedback
voltage mechanism for changes on the AM
detector load by the addilional DC components on the line.) AM rejection IS better than
40dB. CAM = O.1/lF typical for 40dB rejecllOn
for 120Hz AM. ThiS value will suffice for most
power line applications. For a different case,
look at the TWisted-Pair Applicalions.
If the received signal remains at the zero
state after a 1-to-0 (on-to-off) transition for
more than 4 seconds, the RXOUT pin will drift
to the logic High level and stay there until the
signal changes state again. ThiS is known as
the standby mode. ThiS feature can be defeated by externally applYing a 2.2Voc signal
(see HOMENET application). Any protocol
should take this feature into account if It does
not externally defeat the feature through the
hardware.

50

w
z

40

S

.

U)

0

.

fll

R1

Probing at this POint (Pins 7 and 8) should
reveal a square wave with riSing edges following a 1 - exp(-tlRCOET) type of curve. Similarly, the falling edge should show an
(exp(-tlRCOET)) type of charactenstic. ProbIng on the complementary pin Will just show
the InverSion of the signal. This should be
expected since just the charging and discharging of the detection capacitor are being
observed.

60

II:

PIN3

AN1951

30

w

Iii
>

20

E

BPF
~ L390~H

ill
PINS

10
0
10- 3

TlMEli

»Z

"Q.

0

a6
Z

S.
(I)

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

Transient Protection
The latest revision of the NE50S0 demo
board incorporates two back-to-back zener
diodes (Motorola lN4744A) which provide
ISV overvoltage protection for the NESOSO.
The NES050 has been designed to endure
± 35V transients, but for additional protecllon
dUring worst-case conditions (such as the
sudden discharge of the line capacitor by
shorting the prongs of the plug), these devices have been added. The diodes are
connected between Pins 1 and 20 of the IC.
Other devices may be used Instead (such as
surge protectors), as long as they are fast
enough to prevent fast-rising high voltage
impulses from reaching plus or minus 3SV.

120/240VAC Compatibility
This incorporates two series line capacitors,
each rated for 680V. This makes the new
demo boards compatible with both 120 and
240VAC power line.

BENCH TUNING AND TESTING
Testing and tuning of the NESOSO demonstration boards can be accomplished safely without plugging the boards Into the power line.
This test procedure is, therefore, done In the
absence of the line voltage. Note that the
boards are configured to a receiver threshold
of 20mV peak-to-peak, with an impulse rejection time of approximately 570flS. The carrier
frequency has been set to 118kHz (± 10%
due to component variations).
Receiver Testing:
1. Make sure to ground the XMIT input to
deactivate the local oscillator.

2. Apply Vce = 12V at the Input pin marked
"Vec" , and OV at "GND".
3. Measure Vce = 12V at Pins 1 and 20.
4. Make sure the voltage at Pin 3 equals the
voltage at Pin 6.
S. With an external frequency source (either
another NE50S0 demonstrallon board or
a generator), create a 100kHz carrier
frequency modulated with a SOOHz envelope (see Figure 6a).
6. Apply this ASK signal to the plug-input of
the demonstration board.
7. View this signal with an oscilloscope at
Pin 3 or 6. It should appear as Illustrated
in Figure 6b.
8. Next, view the signal after the band-pass
filter, at Pin 4 or S. It Will appear as IS
shown in Figure 6c.
9. While viewing the ASK signal at Pin 4,
adjust the frequency of the source until a

December 1988

maximum amplitude IS observed. This
should occur at near 118kHz. (See Figure
6d.)
10. Further maximize the carner amplitude by
tUning the core of the Toko transformer
with a small screwdriver (See Figure 6e )
11 Next, probe PinS 7 and 8, the detector
output. It Will look like Figure 6f.
12. Next, look at how the Impulse filter affects the output signal ThiS IS done by
probing Pin 10. You Will see a trapezoidal
trace With ramps of duration of about
570l1s. ThiS rise time is determined by
C 'MP at Pin 10.

AN1951

guaranteed minimum 3.5mVRMS over 0
to + 70°C, the consumer temperature
range).
• Change the data rate; observe the
theoretical maximum: Data rate ratio to
carner frequency (1 Sit! cycle). Note that
the data rate IS limited directly by the
value of the impulse capaCitor C,MP.
• Sweep Vce from 12 to 18V
• Remove and replace COET (AM detector
cap) and C'MP (Impulse filter cap) and
observe RXOUT (Pin 11)
• Decrease CLPF (changing the Input highpass filter characteristics) to 1nF for
maximum sensitivity at fc = 300kHz

13 The Pin 10 signals are photographed In
Figure 6g.

• Sweep the carrier frequency from 100Hz
to SOOkHz

14. Apply at VLOGle a SVoe supply. View the
recovered TTL level square wave at the
output marked REC (Figure 6h) Note
that any pulse of less than about S70l1S
Will be removed by the impulse filter.

• Increase CLPF to O.II1F; use low carrier
frequencies and low data rates

Transmitter Testing:
• Power the board and test as covered
above (see Figure 61)

• Sweep the carrier down to DC
• Decrease the ASK data rate
• Observe the general limitations of the
IC modem With the given external
components

• Connect a lOn, 2W resistor to Simulate
a load across the plug
• Apply a SOOHz TTL-level square-wave
to the pin marked "XMIT"

TRANSMITTER- Replace the SOn reSistor,
RORIVE, With a lOn, hw resistor. Monitor
prongs of cord on the oscilloscope. Similar
tests to those done in the receiver can now
be done:

• The corresponding ASK Signal Will
appear across the 1On load at the plug

• Inject TTL and CMOS data at TX ,N (Pin
19)

• Disconnect the resistor and the
amplitude should double

• Sweep Vee
• Observe the TX output (4 VPop into a
Ion load, RL, connected between
RORIVE and ground)

• Tune the transformer core to obtain
maximum Signal amplitude at the plug
output
Experiment With the NESOSO board before
plugging It into the power line. Here are some
additional procedures for obserVing each seclion.

Receiver- Turn the transmitter, TX, off by
grounding TX,N (Pin 19) If thiS IS not done,
the Signal coming is the local oscillator.
Remove the line coupling transformer and the
bandpass filter to permit broadband operation
(the filtering acllon of the transformer With
CTUNE is no longer needed). Replace the line
coupling transformer secondary With a son
resistor. Connect Pin 20 of the IC to the line
coupling capaCitor, CTUNE. Inject ASK Input
Signals at the cord prongs from a son generator. Connect the Signal Side to one prong
and the ground Side to the other. Now run the
follOWing checks:
• Sweep the carner frequency
• Change the carner amplitude (sensitivity
speCified to I.SmVRMS tYPical,

5-56

• Open TX,N and observe the THD (total
harmOniC distortion) of the unmodulated
carrier
• Ground TX,N and observe the -90dS
carrier suppression at TXOUT and at the
prongs
• Check the RXOUT Pin to make sure that
It IS always receiving what it is sending
Should you have any recommendations or
questions In the course of your development,
please call Mike Sedayao at (408) 991-4637
or Dan Harlton at (408) 991-4730. We would
be glad to assist you.
The N ESOSO demonstration board kits are
available from your local Signetics distributor
(order # NESOSO EVN MSC). These kits are
for typical power line performance. Each kit
contains 2 samples, 2 demonstration boards
with samples, and thiS applicallon note. Each
kit has an estimated cost of $266.00.

Application Note

Signetics Linear Products

NE5050: Power line Modem Application Board Cookbook

AN1951

EXTERNAL 500Hz

EXTERNAL ASK INTO

PCB PLUG (RX INPUT)
fCXR = 100kHz

a.

PIN 3 OR PIN 6

(RX AMPLIFIER OUTPUn

EXTERNAL ASK AT THE
PCB PLUG (RXIN)
fCXR

=

100kHz

b.

PIN 4 OR PIN 5

(DETECTOR INPUT)

EXTERNAL ASK AT THE
PCB PLUG (RXIN)

fCXR

= 100kHz

c.
Figure 6. Oscilloscope Plots of NESOSO PCB Bench Testing

December 1988

5·57

•

Application Note

Signetlcs Linear Products

NE5050: Power line Modem Application Board Cookbook

PIN 4

(DETECTOR IN)

RX1N
fCXR

=125kHz

d.

PIN 4
(DETECTOR IN)

RX1N
fCXR

= 125kHz

(TRANSFORMER TUNED)

e.

PIN 7 OR PIN 8
(DETECTOR OUTPUT)

f.

Figure 6. Oscilloscope Plots of NE5050 PCB Bench Testing (Continued)

December 1988

5-58

AN1951

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

AN1951

PIN 10
(IMPULSE FILTER)
DELAY -. SOOps

g.

RXOUT "REC"

(PIN 11)

h.

PCB PLUG

(ACROSS 10n LOAD)

'XMIT' (PIN 19)
(TX'N)

Figure 6. Oscilloscope Plots 01 NE5050 PCB Bench Testing (Continued)

December 1988

5-59

•

Signetics Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

GUIDE FOR NE5050
CAPACITOR SELECTION
The NE5050 IS connected to several external
capacitors which must be optimized for different noise environments. Here is how to select
the approximate values:
• CLPF: For rejection of low frequencies
The input amplifier also provides a fixed
high-pass function. The low -3dB pOint of this
filter IS given by the equation:
1Q-3/CLPF [F]

= L3d8

[Hz].

This provides a + 20dB/decade response,
With a DC attenuation of - 50dB. A carrier
around 100kHz IS boosted by + 24dB. See
Figure 2.
• CAM: AM Rejection Capacitor
This capacitor must be adjusted as a function
of the bit rate (or more precisely, minimum-bit
time). Its value should be:
CAM [F] = 1O- 4/bit rate [bits/sec].
This IS to assure proper capture of leading
bits in a bit string or in the preamble. It IS a
measure of the" readiness" of the receiver to
sWitch from the "standby" mode to the "receive data mode" With no loss of leading bits.
A low CAM value will make the modem react
faster (shorter delays) In both tranSItion directions: from "standby" to "receive data" (incoming or departing messages) and from
"receive data" to "standby" (absence of
data traffic).
• COET: AM Detector Capacitor
Its value is given by:
COET [F]

= tOET

[sec]/105; see Figure 4.

tOET IS the time It takes for COET to charge
from 0 to 50mV, where 50mV IS the detection
threshold. The detector delay time, tOET,
affects the receiver's Jitter. This delay is a
term in a sum of delays, the sum being the
total receiver delay, to [sec]. See below In
"Receiver Delays" the relation between to
and the maximum bit rate
• C,MP: Impulse Filter Capacitor
This capacitor determines the receiver
impUlse-noise immunity (transmission channel with non-Gaussian noise) This capacitor
is determined by the equation:
C'MP [F]

= t'MP

[sec]/35k!1 [ohm].

t'MP is the time it takes to ramp up or down
the C'MP voltage (the beginning of the ramp is
delayed by tOET)' The shortest bit should last
longer than the widest Impulse. The following
equation determines t'MP:
Maximum rejected or expected ImpulsenOise width [sec] < t'MP [sec].
This delay IS a term in a sum of delays, the
sum being the total receiver delay, to [sec].
See 'Receiver Delays' the relallOn between
to and the maximum bit rate.
December 1988

• Receiver Delays: Maximum bit rate
The total receiver delay IS a sum of delays,
where tOET [sec] IS the detector delay, t'MP
[sec] IS the Impulse-filter delay, and 211S IS the
receiver delay With no COET and no C,MP:
to [sec] = total receiver delay
tOET [sec] + t'MP [sec] + 211S

=

The maximum bit rate, In the no-return-tozero, amplitude-shift keYing data format is
determined by:
MaXimum bit rate NRZ ASK
[bit/sec] < 1lto [sec- 1]
NOTE:
The GOET and CIMP values so calculated are for
gUidance and the user shall determine the optimal
performance values In a range between 0.1 times to
10 times the calculated values (power hne enVironment assumed) For tWlsted-palf or coaxial cables
the calculated values are close to optimal Based on

power hne applications made at 100BIt/sec and at
50kBJtlsec, the C'MP/COET capacitor ratio ranged
from 1001 to 11

Observing AC line
Transmission
To observe full data transmission, reconnect
the line-coupling transformer, bandpass filter,
and the Initial values for capacitors C'PF ,
C'MP, and CAM'
Take two boards, setting one up as the
transmitter and the other as the receiver
Supply + 12V to + 15V and grou nd to each of
them. On the receiver, short the TX,N to
ground. Attach a pulse generator to the TX,N
of the transmitter, remembering to connect
the ground of the generator to the ground of
the board Review safety precautions before
plugging Into AC line
Receiver sensitivity IS 1mVRMs. It's recommended to start With about 4Vp_p to ensure a
strong square wave for transmission. To center the bandpass of the transformer to the
Incoming carner frequency, adjust the transformer coupling With a jewel head screwdriver.
To monrtor the receiver, connect OSCilloscope
probes to the follOWing CirCUit POints:
• RX,N (Pin 20, AC line signal With nOise)
• OUT1 and OUT2 differentially (Pins 3
and 6, RX amplifier output)
• COET1 and COET2 differentially (Pins 7
and 8, AM detector output, the deVice
can also be operated With thiS capacitor
removed. Observe reduction In delay.)
• CAMREJ (Pin 9, AM rejection)
• C'MPREJ (Pin 10, Impulse filter; as With
the detector capacitor, the deVice can
be operated Without thiS part. There will
also be a reduction In the delay.)
• RXOUT (Pin 11, receive data output)

5-60

AN1951

Loud, high power-consuming electrrcal equipment could be set up nearby to produce Inband disturbances, such as Impulses. Also,
switch fluorescent lights on and off to see the
effect of the transients on the data transmission. To transmit the data, Inject TTL signals
(CMOS signals are fine because they tYPically
sWing from positive to negative ralls. TTL
thresholds are tYPically 0.8V for logiC 0 and
2.0V for logiC 1) Into the TX,N (Pin 19) of the
other modem located nearby. Make sure that
the signals do not go below ground; If they go
more than one diode drop below ground, an
internal diode turns on and redirects any
signal from TX,N Into the substrate of the
deVice. So If just Injecting a pulse train IS
deSired, choose a pulse generator that has
TTL output rather than the symmetrrcal output that sWings both positive and negative.
After observing these signals, gradually separate the distance between the TX modem and
the RX modem, trying different electrical
outlets on the same floor, different floors, and
different bUildings.
Potential Sources of Interference
There are several sources of signal Interference to consider. Among the most Important
and most likely to occur are the follOWing:
Impulse noise - ThiS form of Interference IS
caused by electrical Impulses present on the
line. It IS present In the baseband and In the
frequency Interval (WCARRIER ± 2 x WOATA)
used for data communications. Because the
frequency spectrum of a delta (Dirac) Impulse
!S continuous, It would be present in any
band. (A delta Dirac Impulse IS defined to be
of Infinite amplitude and zero time duration.
Thus, ItS FOUrier transform would give It an
inflnrte bandWidth With value unrty.)
This translates Into a carner of short duration
In the receiver. If data carner bursts are
longer than the Impulse bursts, It is possible
to filter out narrow data by low-pass fllterrng
(Integrating) or by the constant charging and
discharging of a capacitor (time domain filterIng). Observe the waveform at Pin 10 to see
thiS.
Distributor transformer attenuation - The
transformers that separate domestic dwellIngs or different floors In a factory offer safety
features for the people in the bUildings, but
can also attenuate Signals Irylng to pass
through. The maximum attenuation between
any two locations Within the same house IS
around 50dB In the 10 - 550kHz range.
House-to-house attenuation could be from
10dS for the same distrrbutlon transformer 10
30dB for separate transformers.
In reSidential areas, the power line network
should not extend beyond the bUilding. Hlghfrequency blocking may be necessary to
implement thiS separation Consult the EIA
(Electrical Industries ASSOCiation) for up-Io-

Signetics Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

date information on how to Implement the
blocking. The consensus IS that the blocking
should be done at the electnc power meter
CW (Continuous Wave) interference This type of Interference IS usually caused by
tones present on the AC line. They can be
generated by mercury-vapor fluorescent
lamps. If In the frequency band of the receiver, they may affect the received data and can
cause bit errors. The CW Interference has
spectral components at multiples of 60kHz. It
IS amplitude-modulated by a 120Hz envelope.
Line impedance modulation - The Impedance of the AC power line vanes according to
the number and power consumption requirements of the vanous equipment connected to
the line. 120Hz Impedance modulallOn also
occurs as a result of rectification at 60Hz.
Different condilions eXist, of course, for the
resldenllal and the Industnal enVIronments.
The effect of the Impedance modulation IS
best Illustrated by observing the waveforms
on PinS 7 and 8 (AM detection) and on Pin 9
(AM rejection). The data signal vanes In
amplitude because of the varying Impedance
on the line. The AM relectlon CIrCUit forces
the comparator to track the DC average of
the demodulated data and keeps the comparator from changing states ThiS can be envIsioned as a 50mV "window" (comparator
threshold) "surfing" on the Input waveform
A good example of the kinds of nOise on the
power line and how the NE5050 eliminates
them IS shown In Figure 5.
The top trace shows the signal at Pin 20,
RXIN. The signal has already come from the
line, and gone through the line capacitor and
coupling transformer. If the trace IS followed
from left to nght, three squares over show the
effects of Continuous Wave Interference.
These signals start to produce an amplitude
vanauon where the signal should clearly be
cut off. It also starts to distort the logiC 1-10-0
and O-to-l transitions. At about the seventh
block, the effects of Impedance modulation

Figure 7. Oscilloscope Traces of RXIN,
Output of Bandpass Filter,
Impulse ReJection, and RXoUT

December 1988

AN1951

on the signal can be seen. What should
clearly be a square-shaped signal IS now
distorted Into lagged edges of Increasing
magnitude

(Vcel and Pin 15 (feedback) to create a DC
bias at thiS pOint so that the upper dnve
transistor Will not break down. This IS a
process limitation.]

The second trace IS the output of the slnglepole bandpass ftlter and the Input of the AM
detector (Pins 4 and 5) After RXIN, the signal
was amplified and then ftltered before coming
out of Pins 3 and 6 and gOing Into the bandpass filter. At the end of the signal there IS
some nnglng, and In the third block the
effects of the Impedance modulation stili
show slight amplitude vanatlons.

Reducing or shorting output resistor
RORIVE - ThiS 10n resistor drops the transmit voltage by a little RedUCing or bypasSing
thiS resistor Increases the voltage sent over
the AC lines. The overall effect IS slmtlar to
solullon #1.

Trace three shows the output of the sliCing
comparator at the Impulse rejection range.
The slope of the signal IS directly related to
CIMP At thiS pOint the signal has now gone
through the AM detector and the AM rejector
AM relectlon was successful since the Impedance modulation effects do not show up on
the third block.
The bottom trace shows the output, RXOUT,
at Pin 11. ReSistor RpULL connects Pin 11 to
the logiC High voltage. ThiS signal IS a square
wave, Just the output of the flip-flop that was
fed Internally by the comparator. Companng
the top and bottom traces, a delay IS eVident
ThiS IS caused by the charging of the AM
detecllOn and the Impulse rejection capacItors.
Troubleshooting Board Problems
Because all components, discrete or Integrated, are not exactly the same, always expect
to see a difference In performance as different components are used Not every application board IS the same In the sense that the
frequency, ftlter Q, transmitted power, etc.,
vary ± 10%; otherwise, they are all fully functional. To help solve eventual problems, a list
of cures has been accumulated for different
situations. Short of dOing a pln-for-pin, partfor-part test, these are some of the things that
can be done to get the system running pnor
to identifying the specific problem.
Assuming that the setup IS configured in the
send/receIVe mode and connected to the
power line, there are three possible solutions
to use to get the signal through.
Increase power supply - Bringing the power supply of the part to about + 15V may
reduce the total harmOniC distortion (THD) of
the transmitter If the dnver sWings more than
8V Pop. For higher voltage sWing, increase
RFEEDBACK for lower negative feedback. This
also increases the swing of the voltage output
of the transmitter. Sending out a larger signal
over the power lines increases the slgnal-tonOise ratio.
[To operate the board at supply voltages in
excess of + 15V (but not beyond + 18V),
connect an 82kn resistor between Pin 1

5-61

Bypassing the bandpass filter - Although
this IS usually done only In wideband applications, It is possible that the loss of signal
occurs because the signal IS being ftltered
out That may occur because of BPF or
oscillator component skew. The carner may
be filtered out Instead of the noise. In removIng the BPF, more nOise IS Introduced because of the Wider frequency band, but, once
the signal IS Identified, the BPF can be
reconfigured to pass the carner frequency In
the center of ItS bandwidth.

NE5050 DEMONSTRATION
BOARD ADJUSTMENTS
Summary
The demonstrallOn board comes configured
In a particular mode of operation (i.e., carner
frequency, hlter parameters, Impulse filtenng,
etc.) but IS easily modifiable. BE SURE TO
DISCONNECT THE BOARD FROM THE
POWER LINE AND DISCHARGE THE LINE
CAPACITORS BEFORE REMOVING THE
BACKING OR CHANGING COMPONENTS.
Here are some baSIC adjustments that can be
made:
1. Carner Frequency
Both transmitter and receiver are tuned to
approximately 118kHz. This may be altered by changing CePF, LePF, Cose, and
Lose. Center frequency IS determined by
the equation f(Hertz) = 1/[2*pi* (LC) 1/2)].
2. Impulse Filter
The impulse ftlter consists of a capacitor
tied to Pin 10. This capacitor results in a
rejection of impulses (short-duration, highbandwidth noise) that can appear after the
bandpass ftlter. This filter will ignore short
pulses of duration determined by the
equation Impulse Rejection Time (in seconds) = 38k *CIMP. The demonstration
board comes with a 15nF impulse capacitor, resulting in an impulse rejection time of
570"s. This means that any pulse or statechange that is shorter than 570j.lS will be
ignored by the IC. ThiS impulse rejection
time may be changed by altering this
capacitor value. Note that the value of this
capacitor subsequently places a cetling on
the maximum baud rate by placing a minimum allowable time for symbol encoding.

•

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

3. Input High-Pass Filter
The input stage of the NE5050 consists of
a gain/high-pass filter stage. The transfer
function of this filter can be modified by
changing the value of the capacitor at Pin
2. See Figure 3 for this filter's characteristiCS.
4. Receiver Bandpass Filter
The receiver bandpass filter consists of a
differential single-pole LC stage connected to Pins 3, 4, 5, and 6. The center
frequency is given In Part 1 above The
sharpness of this filter IS determined by
the value of the R 1 and R2. By Increasing
the value of these resistors, we may increase the filter 0 (which also Increases
Insertion loss). Figure 8 shows some tyPIcal performance curves of this filter with
different values of resistors.
5. The demonstration board IS designed to
deliver maximum power Into a 10n load.
This may be changed by simply matching
the value of RORIVE to the equivalent
Impedance of the transmission medium.
Be sure to use at least a 2W resistor.
6. Transformer TUning
The Toko transformer provided has an
adjustable core which should be tuned to
provide minimum carner attenuation at the
desired carrier frequency This can be
accomplished by observing the envelope
of a continuous carner (generated by another transmitter and applied through the
power line side of the transformer) and
turning the core to a pOint of maximum
carner amplitude.
The value for CTUNE, 6.8nF, was found to be
the best tuning possible for the secondary of
the TaKa transformer. One could also try to
tune the primary of the transformer.
The TaKa transformer IS not recommended
in networks With a large number of nodes,
and IS not recommended for high bit rates, for
two reasons:
a) In the receive mode the NE5050 IC Input
Impedance is 9kn at the carner frequency
(Pin 20). The TaKa transformer lowers
the receive-mode Input Impedance of the
printed CirCUit board to 200n This IS OK
for few nodes. This TaKa transformer
design does not facilitate the use of many
nodes In a Single network. A possible
substitute transformer IS the AlE
Magnetics transformer which has 2kn at
the carner frequency
b) The TaKa transformer has limited capability for high-speed data transmission
rates (to 10kbitlsec) while the AlE transformer enables data rates In excess of
100kbltlsec. The AlE transformer IS
broadband and does not reqUire tUning.
December 1988

7. Transient Protection
Note that no guaranties are given regarding
the breakdown voltage of either transformer
For transient protection, the user IS directed
to the following standard:
IEEE Standard 587 (ANSI C62.41-1981)
Condition:
Long Branch CirCUits - 0.5/1s - 100kHz oscillatory wave 6kV.
Short Branch CircUits - 1.2 X 50/1s Impulse
wave 6kV.

- 40 L..."---'-_--L_..l----..JI..-...J.._.J

S.OE4 7.SE' 1.0ES 1.2SES 1.SES 1.7SES

FREQUENCY
Figure 8. Typical Response
for One-Pole BPF and Different
Resistor Values

LAYOUT OF BOARD
Shown In Figure 9 IS a copy of the layout
Imagine looking from the top and actually
seeing "through" the board to the metallization layer (solder side) Look on the back and
the pattern Will be reversed. This has been
done so that the engineer may look at the
components on top (component Side) and
see how they are Interconnected on the back
Side (solder Side).

list of External Components
These component values reflect the NE5050
demonstratior, board which has been deSigned for 118kHz operallon Into a line Impedance of 1On.
Component

Value

CapaCitors
CLINE
CTUNE
CPS
CORIVE
C,
CLPF
CBPF
Cosc

0.47f.1F/680V
(2)
6.8nF
10uF
1/1F
o 1/1F
10nF
4.7nF
4.7nF

5-62

AN1951

Component

Value

CapaCitors
COET
CFO
C F1
CAM
C'MP

4.7nF
27pF
.1/1F
1/1F
15nF

Resistors
RORIVE
R,
Rz
RE2
RE1
RFEEOBACK
RAM1
RAM2
RAM3
Roc
RpULL
RLEO
RRCVS

10W2W
5.1kn
5.1kn

m
m
22kn
1Mn
20Mn
220kn
51kn
10kn
2kn
51kn

Inductors
Lose
LBPF

390f.lH
390/1H

Transistors
01
02
03
04

2N6124 (NPN)
2N6121 (PNP)
2N3904
2N3904

Miscellaneous
Transformer Toko America'
# 707VX - T1 002N
Diodes: Motorola 1N4744A
1 LED
'Toko America, Inc
5520 West Touhy Avenue
Skokie, IL 60077
(312) 677-3640
In Callfcrnla (408) 996-7575
AlE Magnetics
A DivIsion of Vernltron Corporation
701 Murfreesboro Road
NashVille, TN 37210
(615) 244-9024
Advance Transformer Company
2950 Northwestern Avenue
Chicago, IL 60618
(312) 267-8100

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

AN1951

•

•
Figure 9. Layout of Application Board

• ~o ~O il\~j

~. ~0{Ej]-0

000

<

L2 -

xoe(OOO)~"';;;- Oi3S0UH~0
~o

""z

<.n~

0 ...\0).;:-0

00000

Q;ll

'C7~ ~

~I.

I lSI UlISI Ul rl z);;
0000000000

ooo"'::!
L3

'" : . 0
Q3

0
0

(,I)

~ : - o~

.0

0

0000000004

0
zf!!~~ ~'"
:7'1:""~
:1

CAUTION'.
120/2'10 VAC

m

ill ~ ~)
~ ~ - 0 - 0 o,)r----=--=-o~
0
0

~!;l",O" 86

M",

0 1T

",0
r 0
n- n ' ;
U'1U1(J1..#(/,)

~~7'OOOonen

<

;:;

ISO",,,,

0 ~(o

'"
::

0

gO{Ej]-O

0

:;J 0

"~

o@o
R8

~

0

'" _

~

01Z§[J-0~
RiB
0
o-IT:!}-o o!;l

~ IgI g I ~

~

0

:;:

~

I~;
l!J

•

•

1.
T
0

0

DO NOT REMOVE
BACK INSULATOR.

*J1 JMPR-Standby suppress
J2. JMPA - Receive suppress

Figure 10. Component Reference on Layout of Board (Top View)

December 1988

5-63

•

Signetics Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

HIGH-PERFORMANCE
INDUSTRIAL APPLICATION
In a hostIle environment, the carrier frequency and filtenng scheme must be Judiciously
chosen. This is usually done over the frequency domaIn and after a thorough charactenzation of the environment it is designed
for. The carner frequency IS then chosen to
be In the range of least Interference. To
ensure the suppressIon of out-of-band signals, whether it IS noise or other carrier
frequencIes (for a multrcarrier system, see the
Multlcarrier OperatIon section), a high Q filter
with large stopband suppressIon IS desirable.
ThIS suggests the use of multlpole passive
filters or actIve filters. The problem in using
multI pole passIve filters IS that the passive
elements tend to overattenuate the sIgnal.
The configuratIon shown In FIgure 7 illustrates one alternatIve to the SIngle-pole filter
gIven In the normal 100kHz Industrial operatIon. The problem presented was that certarn
fluorescent light bulbs added SIgnifIcant interference to lIne transmission and caused biterror-rate problems. The hght bulbs produce
spectral components at 60 and 120kHz that
contnbute to Impedance modulatIon effects in

AN1951

R8. The NE592 is used to amplify the Signal
which has been attenuated by the ceramic
filter and the input resistors. The NE592 has
an adjustable gain, in this case, the gain
(differential) has been set to 200. (This is the
middle of the gain range and should be
adjusted to give the desired signal.) The
output is then sent to the input of the AM
detector, Pins 4 and 5.

that range. With a carrier near 100kHz, the
single-pole passive bandpass filter with its
6dB! octave roll-off did not proVIde sufficient
stopband suppressIon to get around the
spikes at 120kHz. The solution was to move
the carrier to a higher frequency (260kHz)
beyond the effect of the lights and to select a
filter with a much higher Q in order to eliminate as much noise as possible in the spectrum near the carrier.

There are additional changes to be made for
the high-performance application. Case and
Lose have been changed to 1nF and 390/lH
to match the change made in the bandpass
filter. OruNE has been changed to 1nF for the
same reason. CIMP has been raised to 12nF
to provide a suppression of impulses with
duration under 450"s.

The outputs of the input amplifier are Pins 3
and 6 which feed into the high-Q ceramic
filters. The ones used are Toko 262Cs with a
center frequency of 262kHz. These filters
have a BW of greater than 8kHz and an
Insertion loss of 6dB. Given the center frequency and BW, the Q is approximately 32.
The outputs of the ceramic filters then feed
Into the two-pole LC filter on the right part of
the diagram. Cl, L i, C4, and L2' provide the
center frequency.

The filter shown in this example should by no
means be taken as the best possible example. It was only tailored for the application and
environmental conditions in Signetics' laboratory. Any conventional filter with a differential
input and output can be used. In most cases,
the cost of external components to the user
and the amount of available space on the
board will be the limiting factors.

Resistors Rl, R2, R3A, R4A, R5A, R6A, R3,
and R4 provide DC biasing to the middle of
the supply range, 6V. Resistors R3 and R4
buffer the NE592 Differential Amplifier, and
C2 and C3 AC-couple the signal to the
second LC tank which is buffered by R7 and

.------1r----1.----t----O Vee· +12V
R1

R3A

AS

100k

lOOk

lOOk
R7
12k
PIN 4

PIN 3
AI

12k

C4
1nF

L2

3IIO,.H
PINS

PIN6
R2

lOOk

R4A

RIA

lOOk

lOOk

AI

100k

-=
Figure 11_ Ceramic Filter with Two·Pole Filter for Hlgh-Performence Industrial Operation (Fe = 260kHz)

December 1988

5-64

Signetics Linear Products

Application Note

AN1951

NE5050: Power Line Modem Application Board Cookbook

OTHER APPLICATIONS

CONSUMER OPERATION

On the following pages are several applications for the NE5050 that demonstrate its
flexibility. As mentioned in the disclaimer,
these do not denote the maximum performance of the part, they just describe potential
applications.

The consumer application is similar to the
Industrial operatton outlined earlier, except
that it uses a drive resistor of 50n instead of
Ion. Use the same safety precautions, outlined under Electrical Hazards to the User.

A major difference between this application
and that of the Industrial environment is the
lack of extemal drive transistors for the transmitter.

r----------------------------------------------------------------1---O+v~=+~v

TRANSMIT
~Ao---~----------,

INPUT

GNnCF1
GNQ Lose
01jAF 540~~bRDC

cDRlVE

Case

'.F

Rrt/,IVE
RX,.

GND

20

18

RE2

~lrD8AC'

RE,

10

FEEl).

10

V~I

,.

14

PNP
'7

BACK
18

~~LL

CFO
27pF

FANOUT

4.7nF

"we

NPN 2:lC

ADJ

RECEIVE
DATA
OUTPUT

LC

CFO

Rx"ur

13

12

11

•
,
V~

2
C_

3

OUT,

4

5

IN,

IN,

ro.

11lF

':' GND

C,.,
14.7nF

10k

BPF

7
Com

t"PF
540I'H1Roc

<82

10k

BPF

,:,GND
CaPF

4.7nf

Figure 12. 100kHz Consumer Operation

December 1988

8

Corn

9
CAMR..

10
ClMPREJ

R2

AI
C1

6

OUT,

5-65

CoEr
4.7nF

C

I~~ I~:F
':' GND

':' GND

Application Note

Signetics Linear Products

AN1951

NE5050: Power Line Modem Application Board Cookbook

SPLIT-SECONDARY OPERATION
This operation is similar to the industnal
operation except that the transmitted signal IS
sent on a separate secondary winding. Note

received back into the device, so collision
detection IS not used. This is to be expected
since TXoUT and RXIN are transmitted and
received on different secondaries.

that the turns rallOs are 10'40 for the received
signal. The turns ratio for the transmitted
signal back to the line is 1:10. For this
applicallOn, the transmitted Input IS not being

r-----------------------------------1-----------------------------1---o+v~-+uv

ONI!C"""l CFI
-=OpF

--o+VLOQIC= +5V

TRANSMIT

~uo-~~----------_,

INPUT

:r~LL

CFO
27pF

,.

FANOUT

RDAIV!

1

L4

RECEIVE
~TA

,.

..---1-------. ·>

Ccg~~G

."

,

TRANSMIT
OATA
INPUT

Tx,N

RX,.
20

19

GND
18

RFEED8ACK
PNP 75k

FEEDBACK

17

16

I

TTL

~
I
l

GN~CF1
o.111F

-

RE,

'--r-

FANOUT

50

,

Re.

10k

ROSCIN

RECEIVE
OATA
OUTPUT

~

GN~·1$.!F

NPN
15

~UNEDRIVE

SJAMPLIFIER

CORNE

RDRIVE

'.F

10

,.

CFO

II

FLlP.FLDP

INPUT

,

•

C_

Vee

OUT,

-

~

I

•

C1
G.1"F

':'" GND

I

Rt.OAO
10

~

L-

AMPUFIER

..L--

RXour
11

-=GN D

~Ir-OSCILLATOR

CARRIER
OUTPUT

,.

LC

Vcc /2:LC
14

TRANSMIT

DETECTOR

4
IN,

L
5
IN,

-

•

OUT,

AM
REJECTOR

7
CDET1

~

C_
1nFlo.1101F

lOnF

-= GND

~

•

COMPARAlOR

•

9

Com

CAM."
C

10
CIMPREJ

I ~~

':" QND

Figure 14. Wldeband Operation

WIDEBAND OPERATION
For wldeband operation, note in Figure 10
that the bandpass filter IS not utilized and the
output of the Input amplifier IS shorted directly
to the AM detector to permit all frequencies to
pass through. Also note the absence of any
transformer colis. The receive input and the
transmit output are just AC-coupled to their
respective sources and destinations. The external carrier oscillator input is AC-coupled
directly to Pin 13 to the LC tank Input. It goes
through a 50n resistor to Pin 14. Pin 12 has a
capacitor to ground to prevent the Colpitts
oscillator from building up oscillations itself.
This application is ideal for testing the frequency response of the receiver and transmitter. For single frequencies, the 50n resistor between Pin 13 and Pin 14 can be
replaced with a tuned LC tank circuit.

MULTICARRIER OPERATION
This application enables use of multiple
points on the network without interference
from adjacent transceivers using the same
medium. Set up the boards as in the consum-

December 1988

ac,."",
Figure 15. Multiple Carrier Operation
er or industrial apphcauons, but use different
values for the carrier frequency and the bandpass filter. It is suggested that each camer be
separated as much as possible over the
working range of the NE5050. The frequencies should not be multiple integers of each
other. This ensures that any harmonics will be

5-67

suppressed far enough not to interfere with
other carriers in the spectrum of operation.
In this type of application, the stopband
suppression of the bandpass filters plays a
large role in the efficiency of carrier transmission, so active filters should be considered.

Signetics Unear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

AN1951

r-------------------------------------~----------------------------_1--~+v~=+~v

GN~CF1
~

TAANSMIT

DATAo---~~--------~
INPUT

OpF

RE,

AEo
1

1

~O~LL

CFO

FANOUT

27pF

TX,.

GND

PNP

19

18

17

1

2

Vee

C....

3
OUT,

•

RECEIVE

DATA

OUTPUT

Rose

OAXoUT
NPN

NPN
15

Vcc/2:LC
14

LC

6
OUT.

7
CD£T1

8

CFO

AC UNE:120VRMS

PLUG: CARAIER I/O

5
IN.

IN,

CDrn

9
CAM REJ

10
CIMPREJ

LBPF

Io.1

A1
S.1k
BPF

CtiP•

C1

IlF

-:-GND

I4.7nF

A2
5.1k
BPF

CDEr
4.7nF

C BPF

-:- GND

AAM2

10M
RAM1
1M

AtMP

.ok
RAM3
220k

Figure 16, HOMENET Operation at 120kHz

GENERAL ELECTRIC'S
HOMENET OPERATION 1
HOMENET is a software package copyrighted by General Electric Company for the
purposes of power line and tWisted-pair communication in a residential environment. The
software package IS called the HOMENET
Link Layer and IS compatible with the X-10
Home Control System manufactured by BSR
and GE.
A working diagram is shown in Figure 12.
Technical highlights are as follows:
1. The receiver is disabled while In the
transmit mode. This IS done by having the
transm~ input dnve an NPN transistor.
When turned on, it discharges the Impulse capacitor and pulls the comparator
output Low (Pin 10). The flip-flop cannot
change state. When the data is Low, the
oscillator is suppressed and no carrier is
detected.
2. HOMENET wants the Signal inverted and
w~h an open collector so the user can

December 1988

3.

pick the logiC voltage for the receive
output (typically + 5V).
In order to prevent the receive output
from gOing into the standby mode (tYPIcally 4 seconds after a TX'N 1-to-0 transition, the RXOUT pin Will drift High), the AM
rejection pin IS externally biased to 2.2V
DC With the resistors shown to prevent
the comparator from tnggenng.

NOTE:
The HOMENET link Layer IS available as a
software package With the Commodore 64 Per·

sonal Computer. Current version number avail·
able by contacbng. The Industry Standards Staff,
General ElectriC Corporation, Fairfield, CT 0643t

TWISTED-PAIR APPLICATIONS
Data transmiSSion over twisted-pair cable enables much higher data rates because the
media IS usually free of the nOise and impedance modulation problems of the power line.
Transmission over longer distances IS also

5-68

possible. Many of the same reasons can be
applied to coaXial cable. The NE5050 provides an easy Interface for twisted-pair operation.
Figure 13 shows the charactenstlcs of the
cable used Four rolls of cable were used.
Each roll had over a kilometer of cable which
was linked together to create about 15,000
feet of media. The operation IS straightforward and IS shown In the schematic In Figure
14
ThiS version has no external dnve transistors
and has no drive resistor. The receive Input
comes directly from the end of the secondary
(no tUning capacitor); the tap IS left unconnected. The other end of the secondary is
biased to the power supply. The transformer
made by AlE Magnetics connects itself to the
twisted-pair wire. The center tap is grounded
to the shield of the cable. Only a single-pole
filter IS used. The AlE transformer was
chosen because It enabled the high transmission rates.

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

A

A'

B

B'

G

AN1951

G'
CAB =33nFI1000FT
CAG=C BG =60nF/1000 FT
RAA'= RBB '= 25Q/1000 FT
RGG '=18Q/1OOO FT

Figure 17. Parameters of Shielded Twisted-Pair Cable
"------+Vcc = +12V
GND

TRANSMIT

CFO

'<>se

1,F

27pF

390 1-4 H

RE,

RE,
1.

DMA0---r-------------,

INPUT
AI.

,.

GN~
-::.- C2

RpULL

2k
CORIVE

MAGNETICS
1,F
TRANSFORMERr---t____~r_----+_j

TX.N
19

RX.N
2.

RFeEDBACK

Cose
45nF

56k

/FEED·

RECEIVE
OATA

OUTPUT

GND
18

PNP
17

BACK
16

NPN

Vcc /2:LC

15

14

3

4
IN,

6
OUT 2

7

8

9

e OEn

,.

IN,

C OET2

CAM REJ

CIMP REJ

LC

SHIELDED

TWISTE[)'PAIR
CABLE
318-0733

1

Vee

C HPF

OUT,

R2

R1

1

C1

1f./ F

-=-GNO

C HP '

1k
BPF

L BPF

390,H

1k
BPF

I10nF

COEr
180pF

1
14.7nF I
CAM

-= GND

-=- GND

C 1MP

470pF

-=-GND

C BPF

4.5nF

Figure 18. Twisted-Pair Operation: 15,OOOft Unequalized Cable at 20kBits/sec
Faster transmission is possIble if the cable
lengths are shortened. As a rule of thumb,
shortening the cable enables a doubling of
the transmission rates provIded it doesn't
exceed the part's (or the transformer's)
broadband limitations. Remember, when
changing the data rate, CAM has to be adjusted accordingly. Because of the less noisy
environment, hIgh voltage transients are absent and CIMP plays less of a role in maintainIng a lower bit-error-rate. It will, however,
keep the rate-limiting effect outlined earlier.

December 1988

An additional case was performed In the lab
incorporating the following changes:
1. Pin 2 has a 10"F capacItor in series with
a 2.2kn resIstor. The resIstor was added
to reduce the ringing effects on the RXIN,
PIn 20, due to the response of components at hIgher data rates and hIgher
carrier frequencies. The components will
cause the parts to ring. (The transformer
is a potential source. The IC will not ring
unaided.)
2.

R1 = R2 = 1kn, CBPF
LBPF = Lose = 390"H

5-69

= Cosc = 470pF,

3.
4.

CDET = 68pF
CAM = 1 5nF

5.
6.

CIMP = 12pF
Connect a 10n resIstor between the
ends of the primary of the transformer
(AlE MagnetIcs 318-0733). This resistor
shunts the two tWisted wires.

Performance under these changes resulted In
a 100kbits/sec data rate over 3,000 feet of
shielded tWIsted-paIr wire using a carrier frequency of 370kHz.

•

Signetlcs Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

Twisted-Pair Cable Operation at
20kbltlsec
The Belden cable used was 2-conductor, 24
gauge, shielded; trade # IS 9452. Fifteen
spools were connected In series, 1000 feet
each. Longer transmission distance can be
achieved if the cable is not shielded (less
capacitive loss) The cable IS unequalized.
Cable measurements:
Conductor-to-conductor
capacitance = 33nF/1000 ft.
Conductor resistance = 25.11/1000 ft., one
conductor
Conductor-to-shleld
capacitance = 62nF11 000 ft.
Shield resistance = 18.11/1000 ft
The carner frequency is about 125kHz.
The transmitted bit pattern IS 1101 0100 1000
0000.
One bit lasts 501'S; therefore, the NRZ data
rate IS 20kbrtlsec.
In Figure 20A the OSCillator in the receIVer
modem IS turned off; this prevents crosstalk

to the local receiver (possible crosstalk
cause' usage of unshielded inductors). ThiS
crosstalk creates a first type of jitter in the
receiver. In the transmitter there IS synchronization between the data and the carner zerocrossings. The absence of data-to-carrier
synchrOnization creates a second type of
jitter in the receiver. From top to bottom:
Trace 1 IS the transmitter input data, trace 2 IS
the carrier signal at the transmitter, trace 3 is
the carner at the receiver input, and trace 4 IS
the demodulated data at the receiver output.
A D-type edge-triggered flip-flop IS used to
achieve transmitter data-to-carrier synchronization. In the transmitter, the OSCillator carrier
from Pin 13 IS amplified, shaped, and Injected
as clock signal Into the flip-flop. The data IS
applied at the 0 Input of the flip-flop. The flipflop output, 0, IS connected to the transmitter
data Input, Pin 19.
Figure 20b illustrates the effect of the two
types of jitter upon received data. The oscillator In the receiver is on, and in the transmitter
data is applied directly to Pin 19 (data-tocarner not synchrOnized). From top to bot-

tom: Trace 1 IS the transmitter input data,
trace 2 is the carrier signal at the transmitter,
trace 3 is the carrier at the receiver input, and
trace 4 is the demodulated data at the receiver output. Notice the jitter present In trace 4.
Figure 20c shows data transmission at
25kblt/sec. From top to bottom: Trace 1 is
the transmitter Input data, trace 2 is the
carrier signal at the transmitter, trace 3 is the
carrier at the receiver input, and trace 4 is the
demodulated data at the receiver output.
Notice the absence of jitter in trace 4.

LINE IMPEDANCE MODULATION
The NE5050 receiver has 40dB of AM rejection.
To test thiS, the NE5050 transmitter can be
configured to generate 40dB of AM that looks
like line impedance modulation. Therefore, an
NE5050 can be used to test itself (see Figure 4).
The follOWing are oscilloscope plots of receIVer
waveforms which demonstrate the effect of
impedance modulanon on the camero
Notice in photographs Figures 20B and C that
the AM occurs in the middle of the pulse.

DATAINPUTQ-------______________________- ,

ol--.....,I.....~

DATA INPUT(SYNctQ-------------------I 0

ClK
DB

LC
13

18

Figure 19. NE5050 Transmitter Data-to-Carrier Synchronization

December 1988

5-70

AN1951

Application Note

Signetics Linear Products

NE5050: Power Line Modem Application Board Cookbook

AN1951

a.

•
b.

c.
Figure 20. Twisted-Pair

December 1988

5-71

\Q

~
3

Z

m

01
0
01

C"

!!!

&

C ••

m 1kBIT/SECNRZOR500Hz50% DUTY CYCLE SQUARE WAVE

O;:::-il
o.~F

i

GND~

~SCIN

u

~·41~R~ve41~·4

CD

58

RX,N

GND
18

20

RE2
10

I

,---,
1"F
LC C1 ..l...CFO
Rx"UT
13 O.1"F
12 GND 11

T

±

<1>

"U

0

c

(}

r-

S·

CORIVE

=>

":E

EMULAnON OF LINE IMPEDANCE MODULAOON
40dBAM MODULATEDCXR ~k BIT/SEC NRZ DATA)

~--~--~---+---4---------4~

c:

Q

CD
.....
O.1J.!F

:J

~

!=?
0
lOOkHzCXR WITH 4OdB.12OHz AM OR 2Vp.p/20mVp.p

(Q

s::

0

Q.

CD

3

»
"0

NE5050

"0

o·
0

0'1

.!.,.

.....

o·
:::J

TTL BUFFER

I\)

LlNE·DRIVE AMPLIFIER

O:J

0
0.....

DETECTOR

Q.

0
2

C1.LVCC
O.1"F*
GND

i.CHP•
I-=-

I~UT1

1~1

I~N2

CHP
'
O.1"F

10
C 1MP

0
0

;;0;-

rr
0
0

GND

;;0;-

Figure 21. NE5050 Emulation of AC Line Impedance Modulation

»
o·

»
Z

"0

...:0.

0'
=>

-0
01
...:0.

"Q.

9-

z

g.
(1)

Application Note

Signetics Linear Products

NE5050: Power line Modem Application Board Cookbook

AN1951

ASK CARRIER

RXIN

RX OUT

OATA

a.

•
b.

c.
Figure 22. Receiver AM Rejection: General Aspect

December 1988

5-73

Signetics Linear Products

Application Note

NE5050: Power Line Modem Application Board Cookbook

AN1951

OUT-OF-BAND
CW
INTERFERENCE
FROM THE
RADIO SHACK
POWER LINE
TELEPHONE
SET

d.

VISIBLE LINE
IMPEDANCE
MODULATION
CAUSED BY
2 LIGHT
DIMMERS
(IMPULSES PRESENT)

e.
Figure 22. Receiver AM Rejection: General Aspect (Continued)

NE5050 at 50kbit/sec NRZ Data
Over the 277VRMS Power Line
50kbitlsec NRZ data was transmitted in the
laboratory environment over 20 meters, with
277VRMS AC voltage present and the fluores·
cent ceiling lights on. A first reqUIrement was
to reject the 0 to 100kHz frequency band
using a high·pass filter. A 1.5Vp.p 10kHz, CW
interference had to be filtered out. The AlE
Magnetics transformer IS used.
The carrier frequency IS set around 475kHz
using the following components, either In
series or in parallel: L = 390llH/8n and
C = 390pF. In parallel to the LC OSCillator
tank a 20kn potentiometer IS used to adjust
the transmitted amplitude.

December 1988

The bit width IS 20llS and the observed jllter is
< 41ls peak-to-peak. The carner amplitude at
the receiver IS between 0.75 to 2Vp.p

Figure 24a illustrates the transmitted bit pattern (top trace) and the line carner amplitude
(bottom trace).

No external transistors were used. For external transistors the following complementary

Figure 24b illustrates the received ASK carrier (top) and the demodulated data (bottom).

NPN-PNP pairs can be used:

Figure 24c illustrates received ASK carrier
(top) and the jitter increase in the received
data (bottom: jitter < 4Ils). Additional noise
was deliberately added. Notice the drop in
carrier amplitude caused by the low impedance of the noise source.

2N44(l1 - 2N4403 or 2N4400 - 2N4402.
For transient protection two back-to-back
1N4744 zener diodes were used.
A 1010 1110 0000 0000 repetitive bit pattern
was transmitted.
The BPF resistors are 100n, CDET = 390pF,
CAM = 2200pF, CIMP = 270pF.

5-74

Over the 20 meters a 6dB carrier attenuation
was observed.

~

z

:&

(11

Q
c:
OJ

m

3

~

0

(11

-

100

~

0

o:::s·

3

c,.

DATA

0

2

C1

S"

0"

11-___..1

1

~o.1'F I1On",!'

c

~

u

_I "

:=~- II ~

a

0.

»
u

OSCILLATOR

"-J

(J)

Q
"U

eD

'UTPUT
~

.1

20

~

r-

POI'

~__~~~~~~~+-__~
110-:

......

c",

C

2~

OJ

!iBPF *2lU~F
GlND

GINO

()

0
0

7'

0'"

0
0

7'

»
Z

•

Figure 23. SOkBit/sec on the 277VRMS. Neon Lighting. Ceiling Wires

..:..
-0
(11
..:..

J>

"0
'Q.

Ci

8ci"
OJ
z

~

Application Note

Signelics Linear Products

NE5050: Power Line Modem Application Board Cookbook

3.

b.

c.
Figure 24. 50kBits/sec

December 1988

5-76

AN1951

Signetics Linear Products

Application Note

NE5050: Power line Modem Application Board Cookbook

REFERENCES AND
PUBLICATIONS
1. "Low-cost Modem IC Plugs into Power
Lines, Ignores NOise." Dan I. Harlton and
Paul F. Patterson, Electronic Design, October 2, 1986.
2. 1986 Product-of-the-Year Awards:
"Power Line Modem Chip Talks Its Way
to the Top" Electromc Products, January
2, 1987.
3. The Best of 1986 - The Top 100 Product Announcements: "Noise-resistant
Modem IC Plugs Into Power Lines."
Electronic Design, December 29, 1986.
4. "AC Power Line Modem (Technical
Briefs)." Machine Design, November 7,
1985.
5. "AC Power Line Modem for Consumer
and Industrial Environments." Dan I. Hariton and Paul F. Patterson, IEEE International Conference on Consumer Electronics, Conference Proceedings, June 5,
1985.
6. "Carrier Current Digital Data Transceiver" Edward K. Howell, General Electric
Company, U.S. Patent #4,583,232, April
15, 1986
7. "FCC and VDE Impose Tight Conducted
RFI/EMI Specs." Wayne Mitchell, Corcom, Inc., Electronic Design, December
23, 1982.

December 1988

8. "Understanding EMI Test Methods
Eases Product Acceptance." Glen Dash,
Dash, Straus and Goodhue, Inc., EON,
May 26, 1983.
g. "Communication USing Pseudonolse
Modulation on Electric Power Distribution
CirCUitS." Peter K. van der Gracht and
Robert W. Donaldson, IEEE Transactions
on Communications, September 1985.
10. "FM Wireless Intercom, cal.#43-205."
Service Manual, Realistic/Radio Shack,
1983.
11. "A Current-Carner IC for Data Transmission Over the AC Power Lines." Dennis M. Montlcelli and Michael E. Wright,
IEEE Journal of Solid-State Circuits, December 1982.
12 "A New Current-Carner Transceiver IC."
Mitchell Lee, IEEE Transactions In Consumer Electromcs, August 1982.
13. "2-Wlre Bidirectional Data Communication System." National Semiconductor,
1983.
14. "Power Line Carner Transceiver Test
Criteria." Lawrence W. HIli, NONWIRE,
EIA Presentation, January 2, 1985.
15. "PhYSical Layer ReqUirements." H. Bennett T eates and Stanley B Warner, EIA
Consumer Electronic Bus Steering Committee, PLBUS Subcommittee, August
1984.

5-77

AN1951

16. "BSR System X-10." Dave Rye, BSR,
EIA presentation, June 1984.
17. "PLC Communication of ReSidential Digital Control Data." EIA presentation, June
1984.
18. "PLC Transceiver Evaluation Testing
Recommendations." E. Keith Howell,
General Electric Company, EIA presentation, December 1984.
19 "The ReSidential Power CirCUit as a
Communication Medium." J. B. O'Neal,
IEEE Transactions on Consumer Electromcs, August 1986.
20. "Intrabulldlng Data TransmiSSion USing
Power-Line WIring", Robert A. Piety,
Hewlett-Packard Journal, May 1987.
21. "GraphiC Summary of Data Taken on
IndiVidual Homes," (field-test results
comparing the National LM1893 and
Signetics NE5050), Don Pezzolo, Diablo
Research Corporation, EIA Presentation,
April 1987
22. Transient Voltage Suppressors (TransZorb), Product Data Book, General Semiconductor Industries, Inc., 1985.
23. TranSient Voltage Suppression Devices
(GE-MOV Metal OXide Varistors), Fifth
Edition, General Electric, October 1986.

•

Signetics

NE5080
High-Speed FSK Modem
Transmitter
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The NE50BO is the transmitter chip, of a
two-chip set, designed to be the heart of
an FSK modem. (The NE50B1 is the
receiver chip.) The chips are compatible
with the IEEE 802.4 standard for a
"Single-Channel Phase-ContinuousFSK Token Bus." The specifications
shown in this data sheet are those
guaranteed when the transmitter is
tuned for the frequencies given in the
B02 standard. However, both the
NE50BO and the NE50B1 may be used
at other frequencies. The ratio of logic
high to logic low frequencies is normally
at 1.67 to 1.00 at any center frequency;
however, it can be varied externally.
(See AN1950.)

•
•
•
•

PIN CONFIGURATION

Meets IEEE 802.4 standard
Data rates to several Megabaud
Half- or full-duplex operation
Jabber function on-chip

N Package

JABBER FLAG

APPLICATIONS
•
•
•
•
•

Local Area Networks
Point-to-point communications
Factory automation
Process control
Office automation

2

15

:~~~~:TOR

JABBER
CONTROL
Vee,

4

TRANSMIT
GATE

FSK OUTPUT

6

CABLE GNO

7

TOP VIEW

ORDERING CODE
DESCRIPTION

1S-Pin Plastic DIP

TEMPERATURE
RANGE

ORDER CODE

O·G to +70·C

NE5080N

BLOCK DIAGRAM
AI
21K

CI

I~:~~

14'1-_--1
0-..::

r-:;:;;;;--l-__-+L-o

TRANSMIT
GATE

December 1988

JABBER FLAG

o......1t-----==l.....r ....---:=---::=------...L_:::::..J--r---i

5-78

TRANSMITTER
FSK OUTPUT

Signetics Linear Products

Preliminary Specification

NE5080

High-Speed FSK Modem Transmitter

GENERAL DESCRIPTION
The NE5080 IS designed to transmit high
frequency asynchronous data on coaxial cable, at rates from DC to 2M baud (see Note
1). The chip accepts senal data and transmits
it as a periodic signal whose frequency depends on whether the data IS high or low.
The device is meant to operate at a frequency of 6.25MHz for a logic high and 3.75MHz
for a logic low (see Note 2). The frequency is
set up by external trimming components;
however, the ratio of the high and low frequencies IS set Internally and cannot be
altered
The FSK output can be turned off by use of
the transmit gate pin. When turned off, the
transmitter has a high output Impedance and
the oscillator is disabled.
The length of time a transmitter can transmit
can be controlled by the use of the Jabber
control pin (see deSCription of Jabber Control
Pin).

ABSOLUTE MAXIMUM RATINGS
VCCI
VCC2

Supply voltage

VIN

Input voltage range (Data, Gate)

Po

Power dissipation

TA

Operating temperature range

TJ

Max juncllOn temperature

TSTG

Storage temperature range

TSOLO

Lead temperature (soldering, 10sec)

RATING

UNIT

+6

V

-0.3 to +Vcc

V

800

mW

o to

+70

·C

-65 to +150

·C

300

·C

FUNCTION

PIN

r-----~----------------------------------~

OSC 1: One end of the external capacitor used to set the
carrier frequency.

2

Jabber Flag: This pin goes to a logic high if the
transmitter attempts to transmit for a longer time than
allowed by the Jabber control function.

3

Jabber Control: Used to control transmit time. See note on
Jabber function.

4

VCCI:

5

Transmit Gate: A logic flow on this pin Will enable the
transmitter; a logic high will disable it.

Voltage supply.

6

Transmitter FSK Output

7

Cable Ground: The shield of the coax cable should be
connected to this pin and to Pin 11.

8

VCC2:

9

No Connection

Connect to Pin 4 close to device.

10

No Connection

11

Ground 2: Connect to Analog ground close to device.

12

OSC 3: A variable resistor between this point and ground is
used to set the carner frequencies.

13

Ground 1: Connect to Analog close to device.

Jabber Flag Pin

14

Data Input

This pin will go to a logic high when the
Jabber Control pin is used to shut off the
transmitter. It will latch and can be reset by
applying a logic low to the Jabber Control pin.

15

Regulator Bypass: A bypass capacitor between this pin and
VCCI IS required for the internal voltage regulator function.

16

OSC 2: One end of a capacitor that is between Pin 1 and
Pin 16 and is used to set the carrier frequency.

NOTES:
I. The NE5080 IS capable of transmitting up to
I M baud of differential Manchester code at a
center frequency of 5MHz.
2. Although the chip IS designed to meet the reqUirements of IEEE standard 802.4 (TokenPBSSIng Single-Channel Phese-Conbnuous-FSK
Bus), rt can be used at other frequencies.
See "Determining Component Values."

December 1988

·C

+150

NE5080 PIN FUNCTION
r------,-----------------------------,

Jabber Control Pin
Dunng the time the transmitter is transmitting,
this pin sources a current. This current can be
used to set the maximum time that the
transmitter can be on. There are three oplIOns that can be used:
1. Use the current to charge a capacitor.
When the voltage across the cap gets to
approximately 1.4V, the transmitter will
turn off. A logic low applied to Pin 3 Will
reset the Jabber function; an open collector output should be used for this purpose. A logiC high apphed to the pin Will
disable the transmitter.
2. Use to externally sense the current and
have external circuitry to control the
length of time the transmitter is on.
3. The pin can be tied to ground and IS then
not active. Transmission is then controlled solely by the signal at the transmit
gate pin.

PARAMETER

SYMBOL

5-79

•

Preliminary Specitlcation

Signetics Linear Products

NE5080

High-Speed FSK Modem Transmitter

DC ELECTRICAL CHARACTERISTICS

Vcc, 2=4.75-5.25V, TA=O·C to +70·C.
LIMITS
TEST CONDITIONS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max
MHz

f,

Output frequency (Logic high)

Data input ;;;. 2.0V (See Note 1)

6.17

6.25

6.33

fo

Output frequency (Logic low)

Data input <; 0.8V (See Note 1)

3.67

3.75

3.83

MHz

Vo

Output amplitude

Data input ;;;. 2.0V or <; 0.8V
Output Load = 37.5,n

0.5

1.0

VRMS

ROFF

Output impedance (gated off)

Transmit gate ;;;. 2.0V

100

RON

k,n
37.5

,n

TransmH gate ;;;. 2.0V or <; 0.8V

10

pF

Transmit gate ;;;. 2.0V
2.0MHz sq. wave (TTL levels) input

1

mVRMS

Transmit gate <; 0.8V

Output impedance (gated on)

Co

Output capacitance

VF

Feedthrough

IJ

Jabber current

Transmit gate <; 0.8V
Input ;;;. 2.0V or <; 0.8V

1.25

Icc

Supply current

VCCl connected to VCC2

75

VIH
VIL
IIH
IlL

Data Input
Logic high
Logic low
Input current
Input current

Input high voltage
Input low voltage
VIN= 2.4V
VIN = O.4V

2.0

VIH
VIL
IIH
IlL

Transmit gate
Logic high
Logic low
Input current
Input current

Input high voltage
Input low voltage
VG =2.4V
VG =0.4V

2.0

VOH
VOL

Jabber flag
Logic high
Logic low

IOH = -400pA
IOL-4.0mA

2.4

VIH
VIL

Jabber centrol
Logic high
Logic low

Input high voltage
Input low voltage

2.0

pA
100

mA

0.8
40
-1.6

V
V
pA
mA

0.8
40
-1.6

V
V
pA
mA

0.4

V
V

0.8

V
V

Logic levels

NOTE:
1. Tuned per instructions in AN195.

AC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

TO

FROM

TEST CONDITIONS

Setup time

Data in

Gate on

Figure 1

tA

Delay time

Output fraq.
change

Data transition

Figure 2

tB

Delay time

Output
disabled

Gate off

Figure 3

Ie

Delay time

Output
disabled

Jabber centrol

to

Delay time

Jabber flag

Jabber control

ts

Jabber control reset
Pulse width (Logic low)

December 1988

UNIT
Min

Typ

2

0.1

jIS

150

ns

2

jIS

Figure 4

100

ns

Figure 5

100

ns

0.4

100

5-80

Max

ns

Signetlcs Linear Products

Preliminary Specification

NE5080

High-Speed FSK Modem Transmitter

TRANSMITTER
GATE

~ts--':

DATA INPUT

-------':...--.,Ln____
VALID DATA

Figure 4. Delay Time, te
Figure 1. Setup Time, ts

JABBER CONTROL

DATA INPUT

I

I

JABBER FLA.G

--+JtoF
-----i-I..J·
I

OUTPUT

f,

fO

Figure 5. Delay Time, to

Figure 2. Delay Time, tA

TRANSMITTER
l_
I
GATE _ _ _ _-_
01B I

1 - - 1

I

OUTPUT

'V\N.-

Figure 3. Delay Time, tB

December 1988

5·81

•

Signetics

NE5081
High-Speed FSK Modem
Receiver
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The NE5081 is the receiver chip of a
two-chip set designed to operate as an
FSK modem (the NE5080 is the transmitter chip), The chips are compatible
with the IEEE 802.4 standard for a
"Single-Channel Phase-ContinuousFSK Token Bus," The specifications
given in this data sheet are those guaranteed when the receiver is tuned to the
frequencies in the 802 standard, However, the receiver will work at other frequencies,

•
•
•
•

PIN CONFIGURATION

Meets IEEE 802_4 standard
Data rates to several Megabaud
Half- or full-duplex operation
Low bit rate error (10- 12 typical)

N Package

APPLICATIONS
•
•
•
•
•

l' ANALOG GND

Local Area Networks
Point-to-point communications
Factory automation
Process control
Office automation

16

15

14
13 INPUT LEVEL
DETECT

12 DIGITAL GNO
1, DATA OUTPUT

ORDERING INFORMATION
DESCRIPTION

o to

TOP VIEW

ORDER CODE

TEMPERATURE RANGE

20-Pin Plastic DIP

b~~~~TION TIMING
:'N:r~~TlON TIMING
~~~~I DETECTION

+70°C

NE5081N

BLOCK DIAGRAM
Note: Either
L10rC7is
variable,

C6

RS
5K

r

"

R.

13

+-___-L....J\-.....-r---,..-I.!!..--o OUTPUT DATA
L - - - - - - -. . .....:==~--F--O INPUT
LEVEL FLAG
DIGITALGND

12

December 1988

5-82

Signetics Linear Products

Preliminary Specification

High-Speed FSK Modem Receiver

NE5081

ABSOLUTE MAXIMUM RATINGS TA = 25·C
SYMBOL

PARAMETER

VCC1
VCC2

Supply voltage

V,N

Input voltage range

100

Output (Data, Level detect)
Max sink current

Po

Maximum power dissipation, TA = 25·C, (still-air) 1
N package

TA

Operating temperature range

TSTG

Storage temperature range

TsoLO

RATING

UNIT

+6

V

-0.3 to
+Vcc

V

20

mA

1690

mW

o to

+70

·C

-65 to + 150

·C

Lead soldering temperature (10 sec. max)

300

·C

Max differential voltage between
analog and digital grounds

100

mV

NOTE:
1. Derate above 25°C as follows:
N package at 13.5mWrc.

DC ELECTRICAL CHARACTERISTICS VCC1, 2 = 4.75 - 5.25V. External LC Circuit tuned to 5MHz. Input level detect set at
16mVRMS, TA = O·C + 70·C.

LIMITS
SYMBOL

PARAMETER

10

Logic L09v Frequency

11

Logic High Frequency

INOL

Minimum Input Detect Level

VOL
VOH
VOH

Logic Levels:
Data Output
Data Output
Data Output

VOL
VOH

TEST CONDITIONS
Typ

Max

External LC tuned to 5MHz

3.67

3.75

3.83

MHz

External LC tuned to 5MHz

6.17

6.25

6.33

MHz

Minimum input level that is detected as
carrier (See Note 2 in General Description)

5

50

mVRMS

0.4

V
V
V

0.4

V
V

50

mA

10L = 4.0mA V,N> 16mVRMS Freq = 10
10H = -400"A V,N> 16mVRMS Freq = 11
10H = -400/lA V,N < 5mVRMS Freq = 10

2.4
2.4

10L = 4.0mA V,N = OVRMS
10H = -400/lA V,N > 16mV

2.4

Input Detect Flag
Vcc

Icc
BER

December 1988

Supply Current
Bit Error Rate

UNIT

Min

= 5.25V (VCC1 connected to VCC2)
V,N = 1.0VRMS Freq = 11 or 10

Input Signal> 16mVRMS
maximum in-band noise = 1.6mVRMS

5-83

10- 12

10- 9

•

Signetics Linear Products

Preliminary Specification

High-Speed FSK Modem Receiver

NE5081

AC ELECTRICAL CHARACTERISTICS (AN195, Figure 5 with a 100KHz 1Vp_p)
SYMBOL

TO

PARAMETER

FROM

TEST
CONDITIONS

ts

Delay Time

Input Level
Detect Flag

Input On

Figure 1

te

Delay Time

Input Level
Detect Flag

Input Off

Figure 1

tD

Delay Time

Output
Enabled

Input On

Figure 2

tE

Delay Time

Output
Disabled

Input Off

Figure 2

ReqUired Delay

Carner
Turn Off

Valid Data
End

GENERAL DESCRIPTION
The NE5081 Will accept an FSK-encoded
signal and provide the demodulated digital
data at the output. It IS optimized to work at
frequencies speCified In IEEE 802.4 - Token-Passing Single-Channel Phase-Contlnuous-FSK Bus - (I.e., 3.75MHz and 6.25MHz).
However, it Will work at other frequencles. 1
Its normal acceptable Input Signal level range
is from 16mVRMS to 1VRMS. This can be
adjusted. 3
The receiver will yield an undetected .. Bit
Error Rate" of 10- 9 or lower when receiving
Signals with a 20dB signal-to-nolse ratio. It
has a maximum output Jitter of ± 40ns. 3
NOTES:
The receiver can be tuned to accept different
frequencies by adjustment of the LC CirCUit shown
In Figure 7. However, the external components
have been optimized for 3 75MHz and 625MHz
See" Determining Component Values" for use at
other frequencies,
2 Input Level Detect
This IS a method of turning off the output of the
receiver when the Input Signal falls below an
acceptable level This level IS adjustable within
the range given In the electncal speCification
section The purpose of this function IS to minimize the effect of noise on receiver performance
and to mdlcate when there IS an acceptable Signal
present at the input. All speCifications given In this
data sheet are with the Input level detection set at

December 1988

UNIT

0.5

0.5
2

Typ

Max

005

1

IlS

1.5

2.5

IlS

2

IlS

2.5

IlS

1.5

Il s

NE5081 PIN FUNCTION
PIN
1
2
3
4
5
6
7
8
9
10

11
12
13 and
14
15

16

17
18

16mVRMS
3 Jitter (Definition)
This IS a measure of the ability of the receiver to
accurately reproduce the timing of ItS FSK-coded
digital input. The spec mdlcates the error band In
the timing of a logiC level change

LIMITS
Min

19
20

FUNCTION
Vee1: Should be connected to the 5V supply and Pin 9
CT: One end of an external capaCitor that IS used to tune the receiver
LT: One end of an indicator that IS used to tune the receiver
MT: The junction of the capacitor and inductor used for tUning the
receiver

F2]

F1
Pins 5, 6, 7, 8 are used for a low-pass filter to remove carner
F3
harmonics from the data output
F4
Vce2: Connect to Pin 1 (see Pin 1 function) close to the device
Input Level Flag: This pin IS used to indicate when there IS a Signal
at the Input that IS greater than the level set by the Input level
detection CIrCUitry. A logic high indicates an input greater than the
set level
Data Output: Supplies T2L level data that corresponds to the FSK
Input received
Digital Ground: Should be connected to digital ground
Input Level Detect: These pins are used to set the level of Input
Signal that the deVice Will accept as valid
Input Detection Timing: An external capacitor between this pin and
ground IS used to determine the time from carrier turn-off to output
disable
Input Detection Timing: Same as Pin 15, except that a resistor goes
between this pin and ground. The values of the C and R depend
on the carner frequency. The values given in this data sheet are
for a 5MHz carrier center frequency
Analog Ground: Connect to analog ground close to the deVice
Input Bypass: A capacitor between this pin and ground IS used to
bypass the input bias circuitry
Input: The FSK Signal from the cable goes to this pin
No Connection

5-84

Preliminary Specification

Signetics Linear Products

NE5081

High-Speed FSK Modem Receiver

TIMING DIAGRAMS
F(J Fl

INPUT

16mVRMS

-....-oiIIIIIIIIIIIIIIIIIIIIIIII~1'I

II

Tc--....:~

18---"': [ - - -

I

I,,",PUT LEVel

~ETECT OUTPUT _---~

Dela~

Figure 1.

INPI"

-....-oilll11llllllli1fil@rllr--lI·
-1;..---I

I

To----": ~.--

nATA OUTPUT

Time. tB. Ie

11

TE ---..... : ~-4--

VAliD DATA

Figure 2. Delay Time.

December 1988

to.

tE

•

5-85

AN195

Signetics

Applications Using the
NE5080, NE5081
Application Note
Linear Products

APPLICATIONS
Figure 1 shows a block diagram of the
NE5080 and NE5081 In a simple POlnt-topOint communicallOns scheme. Pin 5 of the
NE5080 IS grounded to permanently enable
transmission, grounding Pin 3 disables the
Jabber function
An example of a comrnunlcallOns system
block diagram uSing the NE5080 and the
NE5081 (as In a modern) IS shown In Figure 2

will Interrupt the Transmission Controller,
which will cease transmitting and wnte to the
proper address for the decoder to put out a
signal to discharge the capacitor. The Controller will then pass the token to Ihe next
node

NE5081 receives the FSK signal and converts It to a digital data stream corresponding
to the data sent by the NE5080. Pin lOaf the
NE5081 goes high when the signal at ItS Input
IS above the threshold set by the potentiometer between Pins 13 and 14 of the NE5081.

The transmission medium can be anything
from a tWisted palf to a fiber OptiC link The

The labber funcllOn IS active In this system.
The NE5080 Jabber Flag (Pin 2) goes high
when the capacitor at Pin 3 of the NE5080
charges to about 1 4 V This fault condition

-~--~--------------

DATA IN

--~---~---~--~~~~~~~~~~~

NE5080
TRANSMITTER

3

FSK TRANSMISSION

NE5081

DATA OUT

RECEIVER

5

Figure 1. Point-to-Point Communications

SERIAL
DATA OUl
TRANSMtSS,.QN
CONTROLLER

TRANSMIT

-14

SERIAL

1"c:.'_ _-tDATA IN
NE5080

NE5081

'0

~--~DATA

RECEIVER
CONTROLLER

VAliD

Figure 2. Communications System Block Diagram
__________

December 1988

~

5-86

_ _ _ _ _ _ _ _ _ ~_ _ _ _ ~~~~~~~~~~_l

Signetics Linear Products

Application Note

Applications Using the NE5080, NE5081

AN195

NE5080

C13
00047 J..tF

35 pF

XXE

100

C12
00047 eF

100

NOTE:
In apphcatlons usmg twisted-pair hnes where nOise pick-up may be exceSSive,

It IS

recommended that the tWisted-pair be driven differentially

Figure 3, Modem Using a Twisted-Pair Transmission Line

DC-to-2 Megabaud Modem
Using the NE5080 and NE5081

4.

Either 1 or 2 above operated on two
cables in the full-duplex mode.

modems attached to the cable, and the
carrier frequency.

The NE50BO and NE50B1 are designed to be
used together as an asynchronous modem.
They employ FSK modulation at high carner
frequencies, plus filtering to reject EMI and
RFI noise that is frequently encountered m
industrial and commercial environments. Figures 4 and 5 show full- and half-duplex
modems.

The 30dB dynamic range of modems bUilt
using the NE50BO and NE50B1 makes It
possible to attach them at any pOint on the
cable without any gain adjustment. There is
no problem with proximity to other similar
modems.

Typical operation can be 100 modems randomly spaced on up to 2000 meters of RG-11
(foam) cable with a center frequency of
5MHz.

The distance that can be dnven varies with
the type of cables used, the number of

In pomt-to-pomt operation, one can dnve
further. Table 1 gives obtainable distances
when different carner frequencies and cables
are used.

The carrier frequency IS externally adjustable
and can range from 50kHz to over 20M Hz.
The modem can be used m a number of
ways:
1. Multidrop party line of data transmltllng
and receiving devices (local area networks).
2. Point-to-polnt operation connectmg just
two transmitting/receiving devices.
3. Either of the above operated on one
cable in the half-duplex mode.

December 19BB

Table 1. Transmission Distance for a Single Receiver as a
Function of Center Frequency and Cable Type
CABLE

CARRIER
FREQUENCY

MAXIMUM
DATA RATE

RG-59

RG-11 (Foam)

T4412J

T4750J

1MHz

0.5 Megabaud

6000 Ft

21000 Ft

33000 Ft

50000 Ft

3MHz

1.0 Megabaud

5000 Ft

12000 Ft

20000 Ft

32000 Ft

5MHz

2.0 Megabaud

4200 Ft

9500 Ft

15000 Ft

25000 Ft

5-87

•

Signetics Linear Products

Application Note

Applications Using the NE5080, NE5081

AN195

-"O:::A'"TA='N'--_ _ _~14

GATE IN

NE5080

C5

C2
047pF

O.lpF

r--------+-~~-__o.5V

DATA OUT

INPUT LEVEL FLAG

EXTERNAL COMPONENTS SHOWN HERE ARE FOR 5MHz CARRIER

Figure 4. NES080 and NES081 Connected as a Full-Duplex Modem

~D~A~TA~IN~_ _ __114

FSK
OUTPUT

GATE IN
NE5080

JABBER FLAG

C2

C5
o lJ.'F

0.47,uF

r--------+-~~-__o+5V

FSK
INPUT

DATA OUT

INPUT lEVEL FLAG

7511
C12
100pF

Cl0
240pF

EXTERNAL COMPONENTS SHOWN HERE ARE FOR 5MHz CARRIER

Figure S. NES080 and NES081 Connected as a Half-Duplex Modem

December 1988

5-88

Signetlcs Linear Products

Application Note

Applications Using the NE5080, NE5081

AN195

8.

FSKIN

0JVWt
Figure 6. NE5081 Data Output When
Correctly Tuned to Incoming 5MHz
Carrier

9.
FLAG

Figure 9. Correct Adjustment of Input
Level Detection Timing

Figure 10. 'Eye' Pattern at NE5081
Pin 8
Figure 7. NE5081 Data Output When
Tuned Just Below 5MHz Carrier

FSK MODEM SETUP
PROCEDURES
To set up the modem per IEEE 802.4 specif~
cations, the follOWing sequence should be
followed at 25 ± 2°C ambient.

~JMJU

TRANSMITTER SETUP:
1.

Ground Jabber Control (Pin 3) and the
transmit gate (Pin 5) of the NES080.

2.

Turn on the power and allow the cirCUit to
warm up for 3 minutes.
Hold the Data Input (Pin 14) of the
NES080 at a logic high.

3.
4.

Figure 8. NE5081 Data Output Tuned
Just Above 5MHz Carrier
5.

Measure the frequency at the FSK output
of the transmitter (cable should be prop·
erly terminated) and adjust R2 for a
frequency reading of 6.2S0MHz ± SkHz.
Apply a logic low to the Data Input and
check the output frequency. If the reading IS not 3.750MHz ± 40kHz, readjust Rl
until the high frequency IS 6.2S0MHz
± 25kHz and the low frequency is
3.750MHz ±40kHz.

Transmitter setup IS now complete.
RECEIVER SETUP:
6.

7.

Set Detection Timing pot RS and Input
Level Detect pot R4 at the NES081 to
mid range.
Apply a 5.000MHz 1Vp_p sine wave to the
receiver FSK Input.

5-89

December 1988

----~~.~~-~~

Attach an oscilloscope probe to the Data
Output pin of the NE5081 and adjust L1
or C7 (whichever IS adjustable) until the
output state alternates between high and
low levels. Figure 7 and 8 indicate examples of improper tUning.
Set the generator to 3.7S0MHz, 35mVp_p.

10. Adlust Input Level Detect pot R4 until the
Data Output pin is alternaung between
high and low levels.
11. Increase the generator output to 4SmVp_p
and venfy that the data output is low.
12. Decrease the generator output to
2SmVp_p and venfy that the data output is
high.
13. Apply a 100kHz 1Vpop signal to the FSK
Input and connect a scope probe to the
Input Level Flag and another probe to the
FSK Input. Adjust Detection Timing pot
R5 so that the delay from the time the
FSK Input signal goes through 0 volts on
the PoSItive to negative tranSItion, to the
time when the Input Level Flag goes from
high to low, is between O.S and 2.S/LS .
See Figure 9.
14. For final adjustment to the tuning of L1t
C7 use an adjusted transmitter to transmit pseudo random data and tune the
receiver L1tC7 tank cirCUit for minimum
jitter and symmetrical eye pattern observed on the receiver Pin 8 (see Figure
10).
ThiS concludes the receiver setup procedure.

DETERMINING COMPONENT
VALUES
Power supply pins of both devices should be
bypassed w~h high quality 0.1 p.F capacitors
close to the devices. Additionally, the
NES081 VCC2 (Pin 9) should be well-decoupled from the power supply by a small inductor (about 10p.H) and another O.Ip.F capacitor
as the NES081 exhibits large changes in
power supply current during switching.
The coupling capacitors C4 and C13 are
needed to maintain input bias when a low DC
impedance line is connected to the FSK
Input. Too small a value for these capacitors
could result in excessive signal attenuation. If
these capacitors are too large, the receiver
Input Level Flag may remain high for an
excessive amount of time after the input
signal IS removed. Each transmitter and each
receiver should have its own coupling capacitor. This is necessary to prevent any DC
terminations from altering biases.
The external resistance at the NES080 Pin 12
should always be about 2.4kn, with some
adjustment allowable to compensate for the
tolerance of Cl and slight differences between individual ICs.

•

Application Note

Signetics Linear Products

AN195

Applications Using the NE5080, NE5081

Cll and R5 are the Carner Detect timing
components and determine how long after
the FSK input signal is discontinued before
the Input Level Flag goes low. R5 should not
exceed 5kf2. With Cll set at 56pF, a 5kf2 R5
will allow Carrier Detect Timing adjustment to
2)1s. R5 can be a fixed resistor If thiS timing IS
not critical (perhaps because of the use of an
"end of data" signal). ThiS delay IS required
to allow the signal to propagate through the
receiver. Carner Detect Timing should be
adjusted for different center frequencies by
chOOSing Cl1 according to the relationship:

8
200
Ll=fe

The Input Level Detect function can be disabled and the receiver be made to hold the
Carrier Detect Flag high by removing R5 and
Cll and tYing Pins 15 and 16 together and
pulling them up to Vee with a 10kf2 resistor
If the Jabber function IS not to be used,
Jabber control Pin 3 of NE5080 should be
grounded. If the Jabber function IS to be used,
a capacitor, C2, should be connected between Pin 3 and ground. The value of thiS
capacitor is determined as Indicated below.
C2 = (0.95 X 10~6)t
where t IS the maximum allowable transmit
time in seconds
The resistance Rl, together with capacitor
Cl, set the transmit frequencies The logic
high frequency is fixed at about 1.67 times the
logic low frequency, meaning that the logic
low frequency IS 0.75 times the center frequency fe, and the logic high frequency IS
1.25 times the center frequency. Note that
thiS center frequency IS never transmitted In
normal operation and IS sometimes referred
to as the "carner frequency."
Cl IS chosen by the relationship for fe at or
below 7MHz:
6.5 X 104
Cl=--fc
Above 7MHz center frequency, thiS capacitor
is found by modifYing thiS equation to:
5.5Xl0~4

er character-sties:

9.0 X 10~5
C8=--fe
4.1 X 10~4
C9=--fe
12 X 10~3
Cl0=---fe
5 X 10~4
C12=--fe

December 1988

10. Cable breaks cause no shorts, making
thiS technology useful In hazardous environments, e.g., explosive chemical facilities.
11. No damage to equipment is expected
due to current surges on adjacent lines.

13. Low BER (Bit Error Rate).

2.5 X 10~2
C4 = C13 = - - - fe
In all of the above equations, capacitances
are In Farads, inductances In Henrys, and
frequencies In Hertz

SOME COMMON BAUD RATES
Although Intended to be used With a center
frequency of 5MHz, the NE5080 and NE5081
can be used at other center frequencies.
Table 2 gives minimum center frequency (fe)
for some common baud rates, together With
external component values for those center

The CirCUit of Figure 11 shows a Simplex fiber
link between the NE5080 transmitter and the
NE5081 receiver The components shown
are for a center frequenoy of 5MHz, although
thiS frequency can be increased to 20MHz
With proper selection of external component
values The NE5539 has a 350MHz unity gain
bandWidth which may limit maximum operatIng frequencies in some systems.
Since the NE5081 can adequately accept
signals below 1OmV at 5MHz carrier, the gain
stage (Within the dashed lines of Figure 11)
may be eliminated if the attenuation in the link
IS low If the gain stage is used, be mindful of
the bandwidth trade-off at higher gains. Refer
to the NE5539 data sheet for details.
The transmitter and receiver are set up as
described under FSK Modem Setup Procedure

frequencies Note that It IS not recommended

that these devices be operated at center
frequencies below 50kHz

USING THE NE5080INE5081
WITH A FIBER-OPTIC LINK
The NE5080/NE5081 chip set IS highly SUItable for use In low cost fiber-optic links There
are many advantages to fiber links over openwire or coaxial cable links These advantages
Include:
1. Cost savings In conductor weight and
size.
2 ImmUnity to EMI/RFI
3. Low crosstalk.
4

5.

1
C7=-7885 Ie

Complete electncal isolation between
transmitter and receiver.

12. Fiber cable does not act as an antenna to
pick up high electromagnetic pulses such
as those caused by electrical storms.

Coupling capacitor values also depend upon
center frequency'

Cl=---fe
To get the charactenstics that are needed for
proper operation of the NE5081, It IS Important to keep the proper relationship between
L1 and C7:

9.

Capacitor values of the filter are dependent
upon operating frequencies to maintain prop-

1
Cll=--3572 fc

No ground loops or shifts caused by
common grounds.

High commUnications secunty; cannot be
tapped by electromagnetic Induction or
surface conduction.
Fiber-optic cable does not radiate electromagnetic energy nor disturb other
communications media.

6.

Extremely Wide bandWidth (high channel
per conductor denSity)

7

Low attenuation

5-90

LAYOUT PRECAUTIONS
As IS the case With any components uSing
high frequencies, good layout practice IS
essential; poor layout can adversely affect
performance. All lead lengths should be as
short as IS practical for all lines which carry
RF, Including the tuning capacitor and resistors (Cl, Rl, R2) of the NE5080. Lead length
IS espeCially critical With Cl, which should be
mounted as close to the NE5080 as is
possible. A pnnted CIrCUIt board With a good
ground plane, both top and bottom, IS also
recommended (wire-wrap IS NOT recommended). The ground plane should extend
below tuning capacitor Clan both top and
bottom of the board, With no other trace
coming between the leads of this capacitor.
Because of the high speed switching, Pin 9
(Vee2) of the NE5081 can exhibit a large
current sWing, causing vertical output Jitter
which may be eliminated by decoupllng Pin 9
With a small (10)1H) RF choke and a O.05)1F
capacitor.
See Figure 12 for an example of a working
layou!.

Signetics Linear Products

Application Note

Applications Using the NE5080, NE5081

AN195

Table 2. Recommended Minimum Center Frequency and Component Values for Various Baud Rates
BAUD
RATE
(kBaud)

fc
(kHz)

C1

L1

C4
C13

C7

C8

C9

C10

C11

C12

9.6

50

13nF

4mH

0.501lF

2.4nF

1.8nF

8.2nF

24nF

5.6nF

10nF
10nF

19.2

50

13nF

4mH

0.501lF

2.4nF

1.8nF

8.2nF

24nF

5.6nF

38.4

100

6.8nF

2mH

0.271lF

13nF

0.9nF

3.9nF

12nF

2.7nF

5nF

50.1

125

5.1nF

1.6mH

0.201lF

1.0nF

750nF

3.3nF

10nF

2.2nF

3.9nF

64.0

160

3.9nF

1.3mH

0. 151lF

800pF

560pF

2.5nF

7.5nF

1.8nF

3nF

128

320

2nF

6251lH

0.0751lF

390pF

270pF

1.3nF

39nF

860pF

1.6nF

256

640

1nF

3121lH

0.0391lF

200pF

150pF

640pF

1.8nF

430pF

750pF

512

1250

510pF

160llH

0021lF

100pF

75pF

330pF

1.0nF

220pF

390pF

1500

3750

180pF

531lH

6.8nF

33pF

25pF

110pF

330pF

75pF

130pF

1544

4000

160pF

50llH

6.8nF

33pF

22pF

100pF

300pF

68pF

125pF

2000

5k

130pF

40llH

50nF

25pF

18pF

82pF

240pF

56pF

100pF

8000

20k

33pF

10llH

1.2nF

6pF

5pF

20pF

62pF

15pF

25pF

•

December 1988

5-91

~3

»
"0
"0

fl

en

.s"
:>
9l.
~.

-8'

~

'"

()"
::l

VI

c:::
VI

:r
<0

+5V

;r

CD

~F

DATA IN
TRANSIIn"

GATE

--I
--

FIBEA CABLE ,

=i:

II'.

,

I,.

Z

m

A,

01
0

Q)

PIN
DIODE

s:>

"pF

Z

,DO

m

01
0

U1

cD
I\)

Q)

...:0.

"::"

'1IpF
-5V

Figure 11. SImplex Fiber-Optic System

»

u

»z

12.

...:0.

:J

-0
01

z

~
~

Application Note

Signetics Linear Products

Applications Using the NE5080, NE5081

I.

~

+sv)
C1 ..

J:

AN195

TOAlLVcc's

VCC1 o-------I

C15

47~FyOl~F

NC

C13

10.~:lFSK
INPUT

19

eTA
~1~F,~~~nnnn~~

C12
l00pF

18

-=-

17

N
E
5
0
8
1

JABBER
CONTROL

C5

IS

C2
047~~_ _ _~
N
E
S

VCClo--=
....C::-:3-0-,:-~-::F-I

o

TRAN:~~{~_~_ _ _-i

*'

8

o

FSK~C'
OUTPUT

I

0

0047~F

CABLE

01~

13

DATA
INPUT

Rl
21K

R2
SOD

15

-=-

13
12

GROUNO

GROUND 1
10

12

11

11

10

NC

INPUT LEVEL

GROUN02

FLAG

GROUND

~01~F

16

I.

"

6

-=VCC'o--....C-1-6---I

+5V

NC

...._ _.....

NOTE:

NOTE:

See NE50BO and NE5081 Block Dlagram(s)

Slgnetlcs NE50eO/NE50B1 Evaluabon Board

J. CONTROL JAB.ER
FLAG

.L

•

\

fIJ

.:"11
C4 • •

X GATE

•

•

CI

•

•

..
':11 -•
La

• e--an- •

~"

•

CC..

•

CC1t

•• e-rn:::r..
•

cP

c",e •
"'EYE.

•

.:-

INPUT LEVEL 'LAG

Figure 12. Components and Layout Used for Evaluation Board

5-93

••

C1A. LI •
:
•

c••

I~

NE5080/NE5081
EVALUATION
it 80ARD

c:

•

December 1988

'"

OAT'

I!!IIRJI:II

5

..• ~

•

•
«.:!I:}e.'

C1I • •

... lU:J

GIlD

.Cl •

•

\

DATA OUT

Signetics

AN1950
Application of NE5080 and
NE5081 With Frequency
Deviation Reduction

Linear Products

Application Note

Author: Prasanna M. Shah

INTRODUCTION
Application note AN 195 discusses numerous
applications of NE5080 and NE5081 in pointto-point, half-duplex and full-duplex communi-

12

cations uSing coaxial, twisted-wire pair, and
fiber optic cables. It also discusses several
aspects about tuning the transmitter and
receiver at various center frequencies and
board layout precautions. In this application

note, the transmitter and receiver chips themselves are discussed. Following the brief
circuit description, a few novel application
ideas are discussed.

:J.STATE
OUTPUT
BUFFER

CURRENT AND
VOLTAGE
REFERENCE

FSK
OUTPUT

Res
':'

DATA IN

14

TTL INPUT
BUFFER AND
SWITCH DRIVER

TRIANGLE
TO SINE
CONVERTER

CURRENT·
CONTROLLED
OSCILLATOR

Co

16

Figure 1. NE5080 Block Diagram

TRANSMITTER
The block diagram of the transmitter NE5080
is shown in Figure 1. The transmitter is
composed of the following six major building
blocks: a TTL input buffer and switch driver, a
current controller oscillator, a triangle-to-sine
wave converter, a 3-state output buffer, and
transmission gating and jabber control circUitry. It also has an on-chip voltage regulator
that provides current and voltage references
to the various building blocks of the Circuit.
The transmitter center frequency can be adjusted by selecting the values of the tuning
capacitor, Co. The switch driver circuitry
switches the current sources I in and out of
Pins 1 and 16. This effectively changes the
total average charging and discharging cur-

December 1988

rent into Co from 1.51 to 2.51, which causes
the output to shift from one frequency to
another. This soft switching action keeps the
output phase continuous and eliminates discontinuities. The ratio of the two output frequencies IS equal to the ratio of the total
average current charging and discharging Co.
Since the values of the internal current
sources are fixed, it produces a constant
frequency ratio of 1.66. An external modification for changing this ratio through extra
components is discussed later.
The triangle-to-sine wave converter circuitry
converts the output of the current-controlled
oscillator into a sine wave with about 2%
distortion. The transmission gating and jabber
control circuitry controls the FSK output
through the 3-state output buffer. The trans-

5-94

mit gate, when held high, will inhibit the
transmission by putting the output buffer into
the high impedance state. It also turns off the
current-controlled OSCillator, thus minimizing
any feedthrough to the output.
The jabber control function is similar to the
transmit gate, but the transmission time can
be programmed through an external capacitor. There is a small current sourced to the
jabber control pin, which charges up the
capacitor. When the voltage on the capacitor
reaches a preset threshold level, the transmission is stopped. This is a failsafe feature
provided to restrict an errant transmitter or
the NE5080 itself from tying up the network.
In point-to-point communications, the jabber
control can be disabled by connecting the
jabber control pin to ground.

Application Note

Signetics linear Products

Application of NE5080 and NE5081 With
Frequency Deviation Reduction
RECEIVER
The receiver block diagram shown In Figure 2
IS composed of the follOWing seven major
bUilding blocks· an Input limiter, a phase
shifter, an analog multiplier, a low-pass filter,
a comparator, an Input level detector, and a
TTL output buffer The Input limiter limits the
FSK input Signal eliminating any amplitude
variations.
The Land C tank CirCUit of the phase shifter IS
tuned to resonate With the Incoming carner

The low-pass lilter IS a Simple second-order
Butterworth filter which eliminates the carner
frequency and higher-order Intermodulatlon
frequencies, and gives the baseband data
which IS equivalent to the Signal modulated by

C1

L1

I

'9

r

LIMITER

I

~

I
I

r
L--.

,,-

•

2

IN

the transmitter. The comparator makes the
deCISion based on the output of the low-pass
filter With reference to a threshold Voltage.
The TTL buffers proVide the output data at
TTL levels. The Input detection level can be
adjusted through the external resistor to set
the threshold for minimum Input level. If the
Input level falls below the set threshold, the
output buffers are disabled, preventing the
nOise from being Interpreted as data.

center frequency. A quadrature detection
scheme IS used to demodulate the data The
balanced analog multiplier processes the incoming Signal With ItS phase-shifted carner
frequency and generates Signals With baseband data and other higher order harmOniCs

.-j,

FSK

AN1950

3

5
PHASE SHIFTER

R.

~

FILTER

-:

7T c2

MULTIPLIER

INPUT
LEVEL
DETECTOR

8

I

k--Figure 2

December 1988

l

6

LOW-PASS

5-95

-]

t
COMPARATOR

t

I

C3

11

DATA
OUT

••

INPUT
LEVEL
DETECT

TIL BUFFERS

•

Signetics Linear Products

Application Note

Application of NE5080 and NE5081 With
Frequency Deviation Reduction

AN1950

APPLICATIONS
NE5080 AND NE5081 chip set encompasses
a broad spectrum of data rates and facilitates
economical modem design for various applications. The transmitter can be tuned to
various center frequencies for different data
rates. The wide dynamic range of the receiver
and the excellent drive capability of the transmitter make it possible to drive long distances
without any signal repeaters. The transmitter
is not limited to transmitting on coaxial cable
only; it can also drive a twisted-wore pair and
optical fibers. All these salient features are
discussed in greater detail in AN195.
The major focus of this application note is on
reducing the frequency deviation. The reduction in freque~cy ratio can be achieved by
bringing the two frequencies fo and f1 closer
together. ThiS will reduce the overall bandwidth utilized by the modem because the
main lobe in the spectrum becomes narrower.
This gain in bandwidth reduction is offset by a
sloght increase in the probability of a bit error
due to poor noise margin. As explained in the
transmitter block diagram section of this application note, the frequency of the oscillator
is controlled by the charging and discharging
current into Co. The two oscillating frequencies can be brought close together either by
lowering the higher frequency f 1 or by raising
the lower frequency fo. Figure 3 shows the
technique for raising the lower frequency fo.
When the logic input is a '1', the two diodes
are reversed biased. In this situation, the
capaCitor is charged and discharged by the
current from the internal current sources. As
the logic input changes to a '0', the two
diodes are forward biased. This will increase
the available current from the internal current
sources that are charging and discharging the
capacitor Co, thus resulting in a higher frequency of oscillation than would be obtained
otherwise. The value of resistor R will determine the amount of excess current available,
which will affect the ratio of the higher frequency to the lower frequency (f11f0)'
Figure 4 gives a graph of the deviation ratio
versus the resistor value R for different values of oscillator capacitor Co. It can be seen
from the graph that the deviation ratio remains constant for a fixed value of resistor R

December 1988

14
NE5080

Vee

1

16

~~

DATA
INPUT C>---<

R

R

1N916

, 1N916

Figure 3

1.8

?

1.6

,.~

If'
0

~

~
> 1.4
z

"w

.'

....

-- Co =33pF
........ Co =56pF

::>

S
a:
u.

-.

~.,.

--.Co =l30pF

1.2

- Co =500pF

-~o~4.~n~1

1.0
1.0

10.0

100.0
RESISTOR R(IN kQ)

tOE3

Figure 4
over a wide range of capaCitor values Co. It
should be noted that the effective data rates
will be lower when the frequency deviation is
reduced. A similar scheme can also be applied to increase the frequency ratio and
thereby increase the data rate, but this will be
done at the cost of extra bandwidth. Using

5-96

appropriate filters for the transmitters and
receivers, a frequency division multiplexing
(FDM) can be achieved for more efficient
usage of the most expensive resource, namely the coaxial cable.

NE5210

Si9 netics

Transimpedance Amplifier

(280M Hz)
Preliminary Specification
Linear Products
DESCRIPTION

FEATURES

The NE5210 is a 7kil transimpedance
wide band, low noise amplifier with differential outputs, particularly suitable for
signal recovery in fiber-optic receivers.
The part is ideally suited for many other
RF applications as a general purpose
gain block.

•
•
•
•
•
•
•
•

PIN CONFIGURATION

Low noise: 3.5PA/YHZ
Single 5V supply
Large bandwidth: 280MHz
Differential outputs
Low input/output Impedances
High power supply rejection ratio
High overload threshold current
Wide dynamic range
• 7kil differential transresistance

APPLICATIONS

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

o to +70·C

NE5210D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

6

V

Operating ambient temperature range

o to +70

·C

TJ

Operabng junction temperature range

-55 to +150

·C

TSTG

Storage temperature range

-65 to +150

·C

POMAX

Power dissipation
T A = 25·C (still air) 1

1.0

W

IINMAX

Maximum input current2

5

mA

Vee

Power supply

TA

NOTES:
1. Maximum dlsSlpabon IS determined by the operabng ambient temperature and the thermal resistance.
OJA

= 125°C/W.

2. The use of a pull-up resistor to Vee for the PIN diode,

December 1988

IS

Package

TOP VIEW

• Fiber-optic receivers, analog and
digital
• Current-ta-voltage converters
• Wldeband gain block
• Medical and scientific
instrumentation
• Sensor preamplifiers
• Single-ended to differential
conversion
• Low noise RF amplifiers
• RF signal processing

14-Pin Plastic SO

o

recommended

5-97

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

RECOMMENDED OPERATING CONDITIONS
SYMBOL

PARAMETER

RATING

Vcc

Supply voltage

4.5 to 5.5

V

o to
o to

+70

·C

+90

·C

TA

Ambient temperature range

TJ

Junction temperature range

UNIT

DC ELECTRICAL CHARACTERISTICS Min and Max hmlts apply over operating temperature range at Vcc = SV, unless
otherwise specified. Typical data applies at Vee = SV and TA = 2S·C.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

VIN

Input bias voltage

0.6

0.8

0.95

Vo±

Output bias voltage

2.8

3.3

3.7

V

Vos

Output offset voltage

0

80

mV

32

rnA

V

Icc

Supply current

21

26

lOMAX

Output sinkl source current 1

3

4

rnA

liN

Input current (2% linearity)

Test Circuit 8, Procedure 2

±120

± 160

p.A

IINMAX

Maximum input current
overload threshold

Test Circuit 8, Procedure 4

±160

±240

p.A

NOTE:
1. Test condition: output qUIescent voltage vanatlon IS less than 100mV for 3mA load current

December 1988

5-98

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

AC ELECTRICAL CHARACTERISTICS TYPical data and MiniMax limits apply at Vcc = 5V and TA = 25°C
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Typ

Max

RT

T ransresistance
(differential output)

DC tested, RL = ~
Test CirCUit 8, Procedure 1

49

7

10

kS1

Ra

Output resistance
(differential output)

DC tested

16

30

42

S1

RT

Transreslstance
(Single-ended output)

2.45

3,5

5

kS1

Ro

Output resistance
(Single-ended output)

DC tested

8

15

21

S1

Test Circuit 1, T A = 25°C

200

280

DC tested, RL =

~

f3d8

BandWidth (-3dB)

R'N

Input resistance

60

S1

C 'N

Input capacitance

7.5

pF

AR/AV

Transreslstance power
supply sensitivity

AR/AT

Transreslstance ambient
temperature sensitivity

IN

RMS nOise current spectral
density (referred to Input)

IT

Integrated RMS nOise current
over the bandWidth (referred to
Input) Cs = 0 1

Cs= 1

MHz

Vcc = 5±0.5V

9.6

20

%N

AT A = T A MAX - T A MIN

0.05

0.1

%rC

f = 10MHz, TA = 25°C,
Test CirCUit 2

3.5

6

pA/VHz

TA = 25°C
Test CirCUit 2
Af = 100MHz
Af= 200MHz
Af = 300MHz

37
56
71

nA
nA
nA

Af = 100MHz
Af = 200MHz
Af = 300M Hz

40
66
89

nA
nA
nA

PSRR

Power supply rejection ratl0 2
(VCC1 = VCC2)

Dc tested, AVcc = 0.1V
EqUivalent AC test CirCUit 3

20

36

dB

PSRR

Power supply relectlon ratl0 2
(VCC1)

DC tested, AVcc = 0 1V
Equivalent AC test CirCUit 4

20

36

dB

PSRR

Power supply relectlon ratl0 2
(VCC2)

DC tested, AVcc = 0 1V
Equivalent AC test CirCUit 5

65

dB

PSRR

Power supply relectlon rall0 2
(ECl conflgurallon)

f=0.1MHz, Test CircUit 6

23

dB

VOMAX

Maximum output voltage sWing
differential

RL = 00
Test CirCUit 8, Procedure 3

2.4

32

Vp_p

V,NMAX

Maximum Input amplitude for
output duty cycle of 50± 5% 3

Test CirCUit 7

650

tR

Rise time for 50 mVp.p
output slgnal 4

Test CirCUit 7

mVp_p

NOTES:
1 Package parasitic capacitance amounts to about 0 2pF
2 PSRR IS output referenced and IS CircUit board layout dependent at higher frequencies For best performance use RF filter
3 Guaranteed by hnearlty and overload tests
4 tR defined as 20 - 80% rise time It IS guaranteed by a -3d8 bandWidth test

December 1988

5-99

12

08

In

Vee line

ns

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

TEST CIRCUITS
SINGLE·ENDED
NETWORK ANALYZER
VOUT

RT==--V;;; R=2xS21xR

S-PARAMETER TEST SET

1

R "'Zo 1+S22
o
1-S22

PORT1

Test Circuit

Ne

Test Circuit 2

December 1988

5-100

1-33

DIFFERENTIAL

Vour
Rr=V;;R=4XS2fxR

1

1+522
Ro=2Z0 - 1-66
1-522

Signetics Linear Products

Preliminary Specification

NE5210

Transimpedance Amplifier (280M Hz)

TEST CIRCUITS (Continued)

,,,

NETWORK ANALYZER

•••
5V

S·PARAMETER TEST SET

I'0"F :fO.'"F
I'o"F

T PORT1

*O.'"F I I

CURRENT PROBE
1mV/mA

PORT 2

U

16

VCC1

I

CAl.

VCC2

33

01.uF

33

01f.tF

OUT~I

INo-

OUT

GND1 ~GND2

100
SAl.

TRANSFORMER
NH030DHB

~'?:UN BAL.

•

"
Test Circuit 3

NETWORK ANALYZER

5V

S-PARAMETER TEST SET
PORT 1

~~~~~

PORT 2

_______________________________________
•.

~CAL

5Vo-~------,-------~

100

BAL

Test Circuit 4

December 1988

5-101

TRANSFORMER
NH0300HB

~
UNBAL.

TeST

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280MHz)

NE5210

TEST CIRCUITS (Continued)

NETWORK ANALYZER

SV

S-PARAMETER TEST SET
PORT 2

PORT 1

CURRENT PROBE

1mV/mA

16
SVO-~----~~----~

01#F

100
SAL.

IN

TRANSFORMER

NH0300HB

~

TEST

UNBAL

Test Circuit 5

NETWORK ANALYZER

,,,
•••

S-PARAMETER TEST SET

1

10 F
•

*U.F

I

CURRENT PROBE
1mV/mA

r-

16

CAL

G N D , I GND2 33

IN 0-

O.:~F

,I

OUT
33

01#&F

OUT~I
5.2V

Vee,l

".L

100
BAL

I Vee,

.L.

Test Circuit 6

December 1988

PORT 2

PORT 1

GNDl

5-102

TRANSFORMER
NH0300HB

~~
UNBAl

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

TEST CIRCUITS (Continued)

PULSE GEN

O.1I'F

1k

IN

OUT

O.'"F

OSCILLOSCOPE

1-----iJB[j Zo = 50 n
50
Measurement done using

dIfferential wave forms

Test Circuit 7

•

December 1988

5-103

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

TEST CIRCUITS (Continued)
Typical Differential Output Voltage
vs Current Input

~

'~'~

+

OUT+
OUT
OUT-

IN

.l -

VOUT (V)

GN~N02
TC23460S

2.00
1.60

~

.

w

...."
-'
0

>

..........

::>
::>
0
-'

~

.'"

- - -- - _.

1.20

/

0.80

/V

0.40
0.00

./

I

-0.40

-1.20

./'/

/

-1.80

I

-2.00

-400

V

./

w -0.80 - - - w

~

V

-320

-240

-160

-80

0

CURRENT INPUT

80

160

240

320

400

(pA)
OP20990S

NE5210 TEST CONDITIONS
Procedure 1

RT measured at 60llA
RT = (V01 - V02)/(+ 601lA - ( - 601lA))
Where. V0 1 Measured at lIN
V02 Measured at lIN

Procedure 2

Llnearrty = 1 - ABS((VOA - VOB)/(Vos - V04))
Where: Vos Measured at lIN = + 1201lA
V04 Measured at lIN = -1201lA
VOA = RT • (+ 1201lA) + Vos
VOB = RT • (-120IlA) + Vos

Procedure 3

VOMAX = V07- Vos
Where: V07 Measured at lIN
Vos Measured at lIN

Procedure 4

= + 260llA
= -2601lA

lIN MAX Test Pass Conditions:
V07 - V05 > 20mV and V06 - V05 > 20mV
Where: V05 Measured at lIN = + 160llA
V06 Measured at lIN = -1601lA
V07 Measured at lIN = + 260llA
Vos Measured at lIN = -2601lA
Test Circuit 8

December 1988

= +6OIlA
= -601lA

5-104

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

TYPICAL PERFORMANCE CHARACTERISTICS
NE5210 Supply Current
VB Temperature
32

NE5210 Output Bias Voltage
vs Temperature
3.50

I
5.sJ

I

6

5.0V

-r-

45J

210-

I
0

-r-

r-

I

18
-10

--

10 20 30 40 50 60 70
AMBIENT TEMPERATURE (·C)

"0~ 3•42

-

>

;ID 3.38

3.30
-10

NE5210 Input Bias Voltage
vs Temperature

v .L1.
~
~~:V
5

0

~

-

sol

1-

JI

2.7
-10

80

!.
~

0

~
g-2O
Iii

~ -40

o

}5V

h --..- ,..-

r- I-- I--

I

..~
8- ~
60

-80
-10

4.0

0

i.-'

-.--

10 20 30 40 50 60 70
AMBIENT TEMPERATURE ("C)

December 1988

E38

"i3.6
II>

w

g"~
Ij

I~
4.5V

1

is

10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE ("C)

ffi

~

2.6
24

2.2
-10

50y

-2.0

o

-300.0

IIJ'" f=

w

"~

I--

-

10 20 30 40 50 60 70
AMBIENT TEMPERATURE (·C)

5-105

+300.0

INPUT CURRENT ("A)

20

,
0

~

g

45~

V

~

l

--

~

/

J.ov ~
~k]v
V

Differential Output Voltage
vs Input Current

50V

3.0

w

80

I

1

~ 28

o

2.0

=X

..~ -

"

+125-C

"Y.,...

+85'C-1
+300 0

5-!R

~

55V

34

"-

Differential Output Voltage
vs Input Current

-JCT~STJD
RL

~ 3.2

~

-3000

NE5210 Differential Output
Swing VB Temperature

20

Sos Jvol ,.L voL I.'

0

f'

INPUT CURRENT ("A)

5.5V

~

10 20 30 40 50 60 70
AMBIENT TEMPERATURE ("C)

2.

-55 C

I(
~

80

~

!V

~

0

PIN1~

3.9

NE5210 Output Offset Voltage
VB Temperature

>

V

10 20 30 40 50 60 70
AMBIENT TEMPERATURE (·C)

~

.Jr

~~

5.0V

~
700
-10

-

-== ~ ~

V

VV

I I

+25 C
+125 C

I=::::,.

NE5210 Output Bias Voltage
vs Temperature
4. 1

~~

0

-.--

~

PIN 14

~~ 3.34 r- ~~ .--

80

45

LtJ

~3.46
w

Output Voltage
vs Input Current

80

I
....

I

V
1/
-55 C 1/
f-+25 C

~

-2.0
-3000

V

""

i=+i5 C

o
INPUT CURRENT ("A)

+300.0

•

Preliminary Specification

Signetics linear Products

NE5210

Transimpedance Amplifier (280M Hz)

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain vs Frequency

NE5210 Differential Transresistance
vs Temperature

Gain vs Frequency

g86

tN:j~:r:~

II U
Vee" 55V

RI'II~fll

~

'"

Vee '" 4SV
4

2

Vee = SOY

~

~

!4~+-t+ttHc!tYCC" 45V

~~ Jc~I!~hv_

~3~+-t+~*--+~H+~--~ri+~t-,

°2~+-t+ttHc!t--+~H+~--r1~~t-~

I~

1~+-t+ttHc!t--+~H+~--ri~~t-~

1
0

'!--'--~~~1O~~-U~,~OO~~-'-~'OOO~..J

1

10

100

8.4

z

1000

I

r-l

TjSTEb. RJ =

rf8 &
rxo

sov

a: 76
is 7.4

-'0

Gain vs Frequency

I--

"' i\\

TA=1~o~

3

~

2

1111111

I 11111

1

I ·11111
I 11111

0

1

10

100

T, -

TA = 25"C

111111

000

~

~llllU"C
'11111

1~;[I~c

100

~

"

-350

~

~ 300

Ii!

1111111
10

400

§i

I ~7111;25'C

111111

FREQUENCY (MHz)

"
,,'c

~

11111

WlJJ1

--

V

,/

,/

VV

'0 20 30 40 50 60 70 80
AMBIENT TEMPERATURE eCl

'2J J

1
PlN
SINGLE-ENDED
RL =500--

rfillf{-

= 5V

TA '" -55"C

TA = 85°C

~ ~ b--"

450

PIN'U"

111111

TA - _55°

~4

~

Vee

0

V

/v
V

NE5210 Bandwidth vs Temperature

Gain vs Frequency

PIN1~~~

11111
I
I+~I~ 125"C

1

82

~

FREQUENCY (MHz)

FREQUENCY (MHlIi)

:!
en

1000

~

~
~ :::::-. .......
.5V

250

fREQUENCY (MHz)

200
-10

0

p: ::::::

~ ;::.:.. -.....;:

10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE ('Cl
0P21760S

Gain and Phase Shift
vs Frequency

NE5210 Typical
Bandwidth Distribution
(70 Parts from 4 Wafer Lots)

Gain and Phase Shift
vs Frequency

f--+-f-t1+tHt-+-f-t1+tHt-+-I\t-:~~ !\v

t-+-H-I-ttllt-+-H-I-ttllt--t-IHc,TA '" 25"C

270

~~HHtm~+-HH~r-~rH~~~O!
~~HHtm~+-HH-ttllP.ml\H-m~~-90

_1 ~,--'-----LLLU"'l0!--'-LW-'-";!,OO:!::---'--WJ""",000~..J
FREQUENCY (MHz)

-1 ~,....J....w..J.J.I~lO;--.Ll...LL.w;lOO;,.Ll...LL'"!!lO\;;;OO-'
FREQUENCY (MHz)

FREQUENCY (MHz)

December ,( dB

5-106

Preliminary Specification

Signetics Linear Products

NE5210

Transimpedance Amplifier (280M Hz)

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
NE5210 Output Resistance
vs Temperature

NE5210 Output Resistance
vs Temperature
17

s:16

16

t15.0~

~'N11

I-- DC TESTED
PI~" ROUT~

III

iii
a: "

~

PIN 12 ROUT 5.0V

0,3

12

-10

0

10

~

....-- ....--

~

~

ro

~

12
-10

00

10

I--"

20

30

40

J

/'
, / VV/'

s.ov
5.5V

-----

50

60

13
-10

70 80

P'N
12

~

o
~ 37
w
Ul

lilil V

P'N

11111

0:

"

V

36

~

FREQUENCY (MHz)

35

c:

Q.

3

,,/

V
V

,/

10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE ('C)

I

/

o1

0

10

20

30

40

50

60

70

80

Output Step Response
I
I

I

I

/
/
/

~~C==2;~C -

I

20mVlDIv

\1
\
\

'-

.J

12

20

40

60

80

100

120

140

FREQUENCY (MHz)

33
AMBIENT TEMPERATURE (Oe)

10

V

,/

r-.-..,-1-'---;--'--'-'--'-'--'

V

4----10

(

V

V

en

~

----I--"

V

V

Q.

g;

10

./
,/

l-+-+-I-+-+-+--l~~C= ;:~ t -

:=

1111

J

Group Delay
10

I I•. J
~ o .JVee1 I VCC2
= 50V
0 3 9 r- ..1Vcc
== ::':01V I I
~
a: 38~ g~;~jJ~~FEARED
z

Vee
TA = 25°C

14

16

(ns)

December 1988

0

NE5210 Power Supply Rejection
Ratio vs Temperature

I

o

/'

V
,.I-'" V

AMBIENT TEMPERATURE rC)

~ 5V~m -

I

I

0

~IN ,~

DClj'STED

55V

Output Resistance
vs Frequency

1

J

L
Jov

/'

......

~

/'

AMBIENT TEMPERATURE COC}

01

17

DC TESTED

III

~ 15

i!

NE5210 Output Resistance
vs Temperature

5·107

18

20

160

180

200

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

NE5210

THEORY OF OPERATION
Translmpedance amplifiers have been widely
used as the preamplifier In fiber-optic receivers. The NE521 0 IS a wide bandwidth (typically 280MHz) translmpedance amplifier designed pnmanly for Input currents requiring a
large dynamic range, such as those produced
by a laser diode. The maximum Input current
before output stage clipping occurs at typically 2401/A. The NE521 0 IS a bipolar translmpedance amplifier which IS current dnven at the
input and generates a differential voltage
signal at the outputs. The forward transfer
function IS therefore a ratio of the differential
output voltage to a given Input current with
the dimensions of ohms. The main feature of
thiS amplifier IS a wldeband, low-noise Input
stage which IS desensitized to photodlode
capacitance variations. When connected to a
photodlode of a few picoFarads, the frequency response Will not be degraded Significantly.
Except for the input stage, the entire signal
path IS differential to provide Improved powersupply rejection and ease of Interface to EGl
type CirCUitry. A block diagram of the CirCUit IS
shown In Figure 1. The Input stage (AI)
employs shunt-senes feedback to stabilize
the current gam of the amplifier. The transreslstance of the amplifier from the current
source to the emitter of 03 IS approximately
the value of the feedback reSistor,
RF = 3.Bkn. The gain from the second stage
(A2) and emitter followers (A3 and A4) IS
about two. Therefore, the differential transreslstance of the entire amplifier, RT IS
VOUT(dlff)
RT = - - - = 2RF = 2(3.BK) = 7.2kn
liN
The single-ended transreslstance of the amplifier IS typically 3.6kn.
The Simplified schematiC m Figure 2 shows
how an Input current is converted to a differential output voltage. The amplifier has a
Single Input for current which IS referenced to
Ground 1. An Input current from a laser diode,
for example, will be converted Into a voltage
by the feedback resistor RF The transistor
01 provides most of the open loop gain of the
Circuit, AVOL""70. The emitter follower Q2
minimizes loading on Q1. The transistor Q4,
resistor R7, and VS 1 provide level shifting and
Interface With the Q15-Q16 differential pair of
the second stage which IS biased With an
Internal reference, VS2. The differential outputs are denved from emitter followers
0 11 -0 12 which are biased by constant current sources. The collectors of Q11-012 are
bonded to an external pin, VCC2, In order to
reduce the feedback to the input stage The
output Impedance IS about 17n Single-ended.

December 1988

Figure 1. NES210-Block Diagram
For ease of performance evaluation, a 33n
resistor IS used m senes With each output to
match to a 50n test system

BANDWIDTH CALCULATIONS
The mput stage, shown In Figure 3, employs
shunt-senes feedback to stabilize the current
gain of the amplifier A Simplified analYSIS can
determine the performance of the amplifier
The eqUivalent mput capacitance, GIN, In
parallel With the source, Is, IS approximately
7.5pF, assuming that Gs = 0 where Gs IS the
external source capacitance.
Since the Input IS dnven by a current source
the Input must have a low Input resistance.
The Input reSistance, RIN, IS the ratio of the
Incremental Input voltage, VIN, to the corresponding Input current, liN and can be calculated as:
VIN
RF
36k
R I N = - = - - - = - = 51n
liN
1 + AVOL
71
More exact calculations would Yield a higher
value of BOn.
Thus GIN and RIN Will form the dommant pole
of the entire amplifier,
L3dS

21r RIN GIN

Single pole response Although wider bandWidths have been achieved by uSing a cascode Input stage conflgurallOn, the present
sol ullOn has the advantage of a very Uniform,
highly desensitized frequency response because the Miller effect dominates over the
external photodlode and stray capacitances.
For example, assuming a source capaCitance
of 1pF, mput stage voltage gain of 70,
RIN = BOn then the total Input capacitance,
GIN = (1 + 7 5) pF which will lead to only a
12% bandWidth reduction

NOISE
Most of the currently Installed fiber-optic systems use non-coherent transmission and detect inCident optical power Therefore, receiver nOise performance becomes very Important. The Input stage achieves a low Input
referred nOise current (spectral density) of
3.5pA/YHZ The transreslstance configuration assures that the external high value bias
resistors often reqUired for photodlode biasIng Will not contribute to the total noise
system nOise The eqUivalent Input RMS nOise
current IS strongly determined by the qUiescent current of Q1, the feedback resistor RF,
and the bandWidth; however, It IS not dependent upon the Internal Miller-capacitance.
The measured wldeband nOise was 66nA in a
200M Hz bandWidth

Assuming typical values for RF = 3.Bkn, RIN
= BOn, GIN
7 5pF
1
L3dS = 21r 75pF 60

354M Hz

The operating pOint of Ql, Figure 2, has been
optimized for the lowest current nOise Without
Introducing a second dominant pole In the
pass-band All poles associated With subsequent stages have been kept at suffiCiently
high enough frequencies to Yield an overall

5-108

DYNAMIC RANGE
CALCULATIONS
The electrical dynamic range can be defined
as the ratio of maximum Input current to the
peak nOise current
Electrical dynamic range, DE, m a 200M Hz
bandWidth assuming IINMAX = 240j.lA and a
wldeband nOise of lEa = 6BnARMS for an
external source capacitance of Gs = 1pF

Signetics Linear Products

Preliminary Specification

NE5210

Transimpedance Amplifier (280M Hz)

where Z IS the ratio of RMS nOise output to the
peak response to a single hole-electron pair.
Assuming 100% photodetector quantum efficiency, half mark/half space digital transmisSion, 850nm lightwave and using Gaussian
approximation, the mInimum required optical
power to achieve 10- 9 BER IS:

INPUT

r--------,
I

1"'-+

I
I f
I I
1-=-= I
I
PHOTODIODE

hc
PavMIN= 12-:;:B Z=12 2.3 X 10- 19

OUT-

200 X 106 2063
= 1139nW = - 29.4dBm,

OUT+

I

' - - - - - - - _ . . . 1 < -......>/111,--.

where h IS Planck's Constant, c is the speed
of light, A IS the wavelength. The minimum
Input current to the NE5210, at this input
power IS:

A

Figure 2. Trans-Impedance Amplifier

lavMIN = q PavMINt;;;
1139 X 10- 9 X 1.6 X 10- 19

.----t--.....-ovcc
R1

-j~9-~IF~·

= 792nA.
Choosing the maximum peak overload current of lavMAX = 240/JA, the maximum mean
optical power is:

I.

INPUT

',N

2.3 X 10- 19

R3

R2
hc 'avMAX
PavMAX =--A--q--

= 345mW

2.3

x 10- 19

= 1.6 X

-6

10 19 240 X 10

or -4.6dBm.

R4

1

Thus the optical dynamic range, Do IS:
Do = PavMAX - PavMIN = -4.6- (-29.4) = 24.8dB.

Figure 3. Shunt-Series Input Stage
(Max. Input current)

P

(Peak nOIse current)

No of generated electrons/ sec = 1/ • hc

DE=~--~------~

= 20 log

(240 X 10- 6)
66 X 10-9)

where 1/ = quantum efficiency

(V2

A

APPLICATION INFORMATION

no. of generated electron hole pairs

(240J.lA)
= 20 log (93nA) = 68dB.

no. of Incident photons

P
In order to calculate the optical dynamic
range the incident optical power must be
considered.

I = 1/' hc • e Amps (Coulombs/sec)

A

For a given wavelength A;

where e = electron charge = 1 6 X 10- 19
Coulombs

hc
Energy of one Photon = -:;: watt sec (Joule)

Responslvlty R = hc Amp/watt

1/'e

A
Where h = Planck's Constant = 6.6 X 10- 34
Joule sec.
c = speed of light = 3 X 108 mil sec
c/ A = optical frequency

1= P'R
Assuming a data rate of 400 Mbaud (BandWidth, B = 200MHz), the nOise parameter Z
may be calculated as: 1

P
No. of mCldent photons/sec = hc where
P = optical Incident power
A

December 1988

IEQ
66 X 10- 9
Z= qB = (1.6 X 10 19)(200 X 106)

5-109

This represents the maximum limit attainable
with the NE5210 operating at 200M Hz bandWidth, with a half mark/half space digItal
transmission at 850nm wavelength.

2063

Package parasltlcs, particularly ground lead
Inductances and parasitic capacitances, can
significantly degrade the frequency response.
Since the NE5210 has differential outputs
which can feed back signals to the Input by
parasitic package or board layout capacitances, both peaking and attenuating type
frequency response shaping is possible. Constructing the board layout so that Ground 1
and Ground 2 have very low impedance paths
has produced the best results. This was
accomplished by adding a ground-plane
stripe underneath the device connecting
Ground 1, PinS 8-11, and Ground 2, PinS 1
and 2 on oppoSIte ends of the S014 package. This ground-plane stripe also provIdes
Isolation between the output return currents
flowing to either VCC2 or Ground 2 and the
mput photodlode currents to flowing to
Ground 1. Without this ground-plane stripe
and with large lead Inductances on the board,
the part may be unstable and oscillate near

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (280M Hz)

800MHz The eaSiest way to realize that the
part is not functioning normally IS to measure
the DC voltages at the outputs. If they are not
close to their qUiescent values of 3.3V (for a
5V supply), then the CirCUit may be OSCillating
Input pin layout necessitates that the photo·
diode be phYSically very close to the Input
and Ground 1. ConnectIng PIns 3 and 5 to
Ground 1 Will tend to shIeld the Input but It will
also tend to increase the capacItance on the
Input and slightly reduce the bandWIdth.

NE5210

As WIth any high-frequency device, some
precautIons must be observed In order to
enloy relIable performance. The first of these
IS the use of a well-regulated power supply
The supply must be capable of prOViding
varyIng amounts of current WIthout SIgnificantly changIng the voltage level. Proper
supply bypassIng requires that a good quality
O.1pF hIgh-frequency capacItor be Inserted
between VCC1 and VCC2, preferably a chip
capaCItor, as close to the package p,ns as
pOSSIble. Also, the parallel comblnallon of

O.1I1F capacItors WIth 10pF tantalum capacItors from each supply, VCC1 and VCC2, to the
ground plane should prOVIde adequate decoupling Some applicatIons may require an
RF choke In senes WIth the power supply line
Separate analog and dIgItal ground leads
must be maIntaIned and pnnted CIrCUIt board
ground plane should be employed whenever
pOSSIble.
FIgure 4 depIcts a 50Mb/s TTL fiber-optIc
receIver uSIng the BPF31, 850nm LED, the
NE5210 and the NE5214 post amplifIer.

GND

G"!"~

t------1(£)

51K

VOUT (TTl)

Figure 4. A 50Mb/s TTL Fiber OptiC Receiver Using NE5210/NE5214

December 1988

5-110

NEjSA5211

Signetics

Transimpedance Amplifier
(180MHz)
Preliminary SpeCification

Linear Products
DESCRIPTION

FEATURES

The NE/SA5211 is a 28kn transimpedance, wide-band, low noise amplifier
with differential outputs, particularly suitable for signal recovery in fiber optic
receivers. The part is ideally suited for
many other RF applications as a general
purpose gain block.

•
•
•
•
•
•
•

PIN CONFIGURATION

Extremely low noise: 1.8pA/v'Hi
Single 5V supply
Large bandwidth: 180MHz
Differential outputs
Low input/output impedances
High power supply rejection ratiO
28kSl differential transresistance

D Package

APPLICATIONS
• Fiber optiC receivers, analog and
digital
• Current-to-voltage converters
• Wide-band gain block
• Medical and scientific
Instrumentation
• Sensor preamplifiers
• Single-ended to differential
conversion
• Low noise RF amplifiers
• RF signal processing

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

14-Pin Plastic SO
14-Pin Plastic SO

ORDER CODE

+70'C

NE5211D

-40 to +85'C

SA5211D

ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL

PARAMETER

UNIT
NE5211

SA5211

6

6

V

-40 to +85

'c

Vcc

Power supply

TA

OperatIng ambIent temperature
range

TJ

OperatIng junction temperature
range

-55 to + 150 -55 to +150

'c

T5TG

Storage temperature range

-65 to +150 -65 to +150

'c

Po

Power dissipatIon,
T A = 25'C (stili-aIr) 1

lIN

MAX

MAX

Maximum Input

o to

current 2

+70

1.0

1.0

W

5

5

mA

NOTES:
1. MaXimum diSSipation is determined by the operating ambient temperature and the thermal resistance
OJA

= 125'C/W

2. The use of a pull-up resistor to Vee, for the PIN diode,

December 1988

IS

recommended

5-111

TOP VIEW

I

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

NEjSA5211

RECOMMENDED OPERATING CONDITIONS
SYMBOL

PARAMETER

RATING

UNIT

4.5 to 5.5

V

Ambient temperature range
NE Grade
SA Grade

o to +70
-40 to +85

·C
·C

Junction temperature range
NE Grade
SA Grade

o to +90
-40 to + 105

·C
·C

Vcc

Supply voltage

TA

TJ

DC ELECTRICAL CHARACTERISTICS Min and Max limits apply over operating temperature at Vee = SV, unless otherwise
specified. Typical data apply at Vee = SV and TA = 2S·C.
NE5211
PARAMETER

SYMBOL

SA5211

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

V,N

Input bias voltage

0.6

0.8

0.95

0.55

0.8

1.00

Vo±

Output bias voltage

2.8

3.4

3.7

2.7

3.4

3.7

V

Vas

Output offset voltage

0

120

0

130

mV

30

31

rnA

V

Icc

Supply current

21

24

20

26

lOMAX

Output sink/source current'

3

4

3

4

rnA

liN

Input current
(2% lineanty)

Test Circuit 8,
Procedure 2

±30

±40

±20

±40

pA

liN MAX

Maximum Input current
overload threshold

Test CirCUit 8,
Procedure 4

±40

±60

±30

±60

pA

NOTE:
1 Test condition output qUIescent voltage vanatlon IS less than 100mV for 3mA load current.

December 1988

5-112

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

NEjSA5211

AC ELECTRICAL CHARACTERISTICS Typical data and Min and Max limits apply at Vee = 5V and TA = 25°C.
NE5211
SYMBOL

PARAMETER

SA5211

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

22

28

35

21

28

36

RT

Transresistance
(differential output)

DC tested
RL = 00
Test Circuit 8, Procedure 1

Ro

Output resistance
(differential output)

DC tested

RT

T ransreslstance
(single-ended output)

DC tested
RL = 00

Ro

Output resistance
(single-ended output)

DC tested

15

15

n

f3dS

BandWidth (-3dB)

TA = 25°C
Test circuit 1

180

180

MHz

200

200

n

4

4

pF

3.7

3.7

%N

0.025

0.025

%;oC

1.8

1.8

pAlv'Hz

Af= 50MHz
Af= 100MHz
Af = 200M Hz

13
20
35

13
20
35

nA
nA
nA

Af= 50MHz
Af= 100MHz
Af= 200M Hz
DC tested, AVee = .OW
EqUivalent AC
Test Circuit 3

13
21
41

13
21
41

nA
nA
nA

R'N

Input resistance

C'N

Input capacitance

AR/AV

Transresistance power
supply sensitivity

AR/AT

Transresistance ambient
temperature sensitivity

IN

RMS noise current
spectral density (referred to input)

Test Circuit 2
f= 10MHz
TA = 25°C

IT

Integrated RMS noise current
over the bandwidth
(referred to Input)

TA = 25°C
Test Circuit 2

CS=01

Cs = lpF

PSRR

Power supply rejection rati0 2
(Vee1 = Vec2)

PSRR

Power supply rejection rati0 2
(Vee1)

PSRR

Power supply rejection rati0 2
(Vee2)

PSRR

Power supply rejection ratio (ECl
configuration)2

VOMAX

Maximum differential output voltage
swing

Y'N MAX

tR

11

Vee = 5±0.5V
AT A = TA MAX - T A MIN

14

17.5

14

10.5

18.0

kn

26

32

23

32

dB

DC tested, AV ee = .OW
EqUivalent AC
Test Circuit 4

26

32

23

32

dB

DC tested, AVec = .OW
EqUivalent AC
Test Circuit 5

45

65

45

65

dB

23

dB

3.2

Vp.p

f=O.IMHz
Test Circuit 6

23

RL = 00
Test Circuit 8, Procedure 3

2.4

MaXimum input
amplitude for
output duty cycle
of 50± 5%3

Test CirCUit 7

160

Rise time for 50mV output slgnal 4

Test Circuit 7

3.2

1.7

160

0.8

1.2

NOTES:
1. Package paraSitic capacitance amounts to about 0 2pF.
2. PSRR IS output referenced and IS CirCUit board layout dependent at higher frequencies. For best performance use RF filter
3. Guaranteed by IInea"ty and overload tests.
4. tR defined as 20 - 80% rIse time. It IS guaranteed by - 3dB bandWidth test.

December 1988

n

30

30

kn

5-113

mVp.p

0.8

In

1.8

Vee hnes.

ns

•

Preliminary Specification

Signetics Linear Products

NEjSA5211

Transimpedance Amplifier (180MHz)

TEST CIRCUITS

SINGLE·ENDED

DIFFERENTIAL

Your

Vour

NETWORK ANALYZER
RT==~ R=2xS21xR

S-PARAMETER TEST SET

o "Zo

R

PORTl
5V

33
Zo=50

O.1J.1F

R=1k

O.1J.1F

OUT 1-'\1\1\,-1 t-J Zo:;;50

Test Circuit

NC

Test Circuit 2

December 1988

5-114

11+5221_33

1-S22

Rr=-v.;R=4xS2'lxA

822 -66
Ro=2Z0 11+
-~
1-S22 1

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

NE/SA5211

TEST CIRCUITS (Continued)

NETWORK ANALYZER

, ,
5V

'to.

t

•• •
S-PARAMETER TEST SET

F

1=0.,.F

t'o.F

1=0.,.F

PORT 1

l
VCC1

CURRENT PROBE
1mV/mA

PORT 2

-

16

!

-'>CAL.

VCC2

33

O.1J.1F

OUT~I

INo-

33

O.1J.1F

100
SAL.

TRANSFORMER
NH0300HB

~

TEST

UNBAL.

•

OUT


.

0.40

I-

:>

I-

0.00

..J

-0.40

:>
0

~

...a;z
..."-

15

-0.80

/'
~

V

rr'

L

--

/

--

//

-1.20

--

V

-1.60
-2.00
-400

-320

-240

-160

-80

0

CURRENT INPUT

80

160

240

320

400

(pAl
OP20990S

NE5211 TEST CONDITIONS
Procedure 1

RT measured at 15/lA
RT = (V01 - V02)/(+ 15/lA - (-15/lA»
Where: V0 1 Measured at liN
V0 2 Measured at liN

Procedure 2

Llneanty = 1 - ABS«VOA - VOS)/(V03 - V04»
Where: V03 Measured at liN = +30/lA
V04 Measured at liN = -30/lA
VOA = RT * (+30/lA) + Vos
Vos = RT * (-30/lA) + Vos

Procedure 3

VOMAX = VQ7- Vos
Where: VQ7 Measured at liN
Vos Measured at liN

Procedure 4

= +65/lA
= -65/lA

liN MAX Test Pass Conditions:
Vo 7 -Vos>50mV and Vos-Vos>50mV
Where: Vos Measured at liN = +40/lA
Vos Measured at liN = -40/lA
VQ7 Measured at liN = +65/lA
Vos Measured at liN = -65/lA
Test Circuit 8

December 1988

= + 15/lA
= -15/lA

5-118

Preliminary Specification

Signetics Linear Products

NEjSA5211

Transimpedance Amplifier (180MHz)

TYPICAL PERFORMANCE CHARACTERISTICS
NE5211 Supply Current
vs Temperature
30

~t
f--$..

1

-

r- r-

-r-

--

.........

....... .........

Jtr

.......

~~

3.25
-60

40

>

4S~ ~

5
~

29
-60

If

Iii

-60

0

-80

I-

~

-100

5 -120

VOUT 12 - VOUT 14

I

f..-'- >-- ..-

f- •.slv

..... tr

,......
so;:!...-

-~
~

-

-140
-60

.,-

-

f..- ,...- ~

V

......

,/

//

I

I
40 20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE re)

December 1988

20 0

20 40 60 80 100 120 140

I

/J

4SV

~38

~
1=
:::>
o

34
32

slv

r- i -

o

26

~ 24
22

-60

1

4SV

Differential Output Voltage
vs Input Current

~

>

I-

:::>

II.

:::>
0

40

-- --

I
20 0

100.0

INPUT CURRENT ("A)

I-

sL

"w~ 28 I=- 2
ffi

ssv

12~'e
~
85O~
w
~~
"~ I-~'e ~ 25°C
0

=X

.... 30 f-

"

45

f-dCT~ST~D
Rt
r-r--

/,~

~~

-20
-1000

NE5211 Differential Output
Swing vs Temperature

i" 36

ssv

7:. ::t::
4SV

V

AMBIENT TEMPERATURE

40

,I _I, 1 1 .J 1

f- vos -

o

)

....

I

- 40

J.ov

~

4SV

NE5211 Output Offset Voltage
vs Temperature
40

..

Differential Output Voltage
vs Input Current

§

1

3.1

27

+1000

g

sov

I-

:::>

o

INPUT CURRENT ("A)

"~

I

'"~ 33

650
-60 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE rC)

-20

-20
-1000

w

ssv

~
035

I!:

25 C
85 C

~

1~

~ 37

~~

,

)

20

~

'"

-40

20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE ('C)

NE5211 Output Bias Voltage
vs Temperature
39

,

~

-sS'C, 2S'C

L

125 C

1

ii;;;;;;

g

"

~..v

-55 C

PIN

"~

./'

t; l:::=

~

~,......

I- '-

950

w

~~

.~

:;..--

PIN 12i"""

NE5211 Input Bias Voltage
vs Temperature

20

20

Lls.Jv

sJJ
.........

18
-60 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE rC)

>
§.

Output Voltage
vs Input Current

NE5211 Output Bias Voltage
vs Temperature
350

....

f..- ,...-

20 40 60 80 100 120 140

AMBIENT TEMPERATURE (OC)

5-119

.
~

25°C, r//.

I.t:

r- ~ i"""
2.5

-1000

ss·C

~

J,V

~

11/

"

i=
z
w
a:
w

8s'e

125 c C

~

"

I'-

~;2J;c

-55~

o

INPUT CURRENT ("A)

1000

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

NE/SA5211

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain vs Frequency

,.
17

,.
17

vcc=s~vm

15

14

,
l'
Z12
~,

mt

~\

Ycrc~~~,

~

Vee =4.5V

r-~=~oc

13
2

If-rli

10

.,

II

8

IVee

!HV

III
-!:tIl :\
-!+H ,\\

~

Vcc=5~
Vee "4.5V

PIN 14

TA " 25"C
RL = son

1

,.
FREQUENCY (ftliz)

...

80.1

!33 !cT~ST~D
~

1

10

100

FREQUENCY (MHz)
oP2141OS

/

32 -RL =oc

~3

1

a:

~ 30

1

II

•

I II

15

•

NE5211 Differential Transreslstance
vs Temperature

Gain vs Frequency

~29 ~
w

a: 28

~
0 27

5.0V

./

V~
Y 1/ ~

-:

V ,/ V

......V /

yv

-60 -40 -20 0 20 40 80 80 100 120 140
AMBIENT TEMPERATURE (OC)
OP2142QS

Gain vs Frequency

Gain vs Frequency
17 r-T"TITn
I mr---r-n-mr::.A-:.-=....::::.:::-c,wnJ."1ll1r-1

17

15~~tm~~#m~~~~
PIN 12
TA = 125"C

15

14

Vcc=SV

°11I-+-IH-l++ttI-+-f-H-HJ1I1-1-~H*~W

,.
FREQUENCY (fIWotz)

3

TA = 85°C
I IIII

2

TA" 25°C

•
•

1O~~HH+I!!I--+-HH+JjjIl-+-+-hI-fl+~~

1

Vee" 5V

•

TA =85"C

131-+-IH-l++ttI-+-f-H-HJ1if-·T~ "2s~C

~ 12 ~~HH+I!!I--+-HH+JjjIl-+-+-hI-fl+If"I\v

8.,

'A.~l~ fA ~ 1~!.~

PIN 14

•

M~~rlH~~+-HH+fflf-~rP~~~~

i

NE5211 Typical
Bandwidth Distribution
(70 Parts from 3 Wafer Lots)

.,

8

100

...

I•
FREQUENCY (MHz)

FREQUENCY CMHI)
OP21450S

NE5211 Bandwidth
VB Temperature
220 r-r.--.--.,-...,......,...--r-r--r--,

~Nj21.l

~v-+-+-+--t-S/NGLE-ENDED
'N
~r--....
Rl = SOO
~ 180 ~5V
.......... ........
j5
~ l'-.
o 160 I-+-+-+,-...Ir---::"""""'++--l
200

r-r- .... . . . .

I:l

. . . . i'.i'~

140 I-+-+-+-+---j'-I--P'-t:'~~
........ ~
1201-+-++-+---j-1-+-1-+-4

.

1

17
16

15

1\
\
\

",

.

15

PIN14
Vee = 5V tt+t~-t-I+t-Hfflc-t-+++ttlt\--1
T" = HOC
\

11-- ptN 12

,r-}W~
:01

II

\
10

120

100

FREQUENCY (Mtk)
OP21470S

1~60!:-_-l:4O.,.--J_1:,2O:-0l-2,L0---l40-6L..0-80.L..,.J0-0-12L..0...J,4O
AMBIENT TEMPERATURE (·C)

December 1988

Gain and Phase Shift
vs Frequency

Gain and Phase Shift
vs Frequency

5-120

'01

,.
FREQUENCY (MHz)

100

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

NE/SA5211

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
NE5211 Output Resistance
VB Temperature
18

6

18

~cc ~ s.~v
f-ocTEST D

/
"

5

NE5211 Output Resistance
vs Temperature

PIN 14

~
1'\....... ~N;2
.1

I

I

13
-60 -40 -20 0

,/

....

V

~

V

0: 15

""

0,4

,

Vee " SOY

,

II
ve~ l ~~

..

C 70

;;
U

14
-60

~20

..

~34

53 .... ~
~30
2

,/

/""

70

~

,

Zso

rin:12
111111

F

IIIW

10

0"

Group Delay
vs Frequency

V
~

~

~

~

~

m

~

20 40 60 80 100 120 140

5-121

~

~I~?'"

0'0

FREQUENCY (MHz)

AMBIENT TEMPERATURE rC)

December 1988

11111

11111

~40

I III

FREQUENCY (MHz)

-60 -40 -20 0

II

!vi

0

010

01

veel •

~

V

228

20 40 60 80 100 120 140

80

= ±O.IV

OCTESTED I
I
OUTPUT REFERRED

40 -20 0

!a eo

I III

TA = _55°C

V

5.5V

Output Resistance
vs Frequency

I III

TA = 125°C
TA " 85°C
TA " 25°C

;:;r ....V /

AMBIENT TEMPERATURE (oC)

I III

!40
,

'0

V

VV
V VV
V :/ /

4.SV

~

/'

~CC11 = Jecol= 5.~V

0:

!!;

"

""

~

FREQUENCY (MHz)

038 f-AVcc

~38

"-

Output Resistance
vs Frequency

~30

I
I
I

/

20 40 60 80 100 120 140

80

NE5211 Power Supply Rejection
Ratio vs Temperature

Ii0:

.....

-

~50

,"v

111111
111111

!40

5bv
55V

.......

.l

/

AMBIENT TEMPERATURE (oC)

I

Vcc=55Y

"

""
.... /

4.5V

13
-60 -40 -20 0

20 40 60 60 100 120 140

II

5

/

"'-

~ ~ .......

e

t~

,~

LN
-DC TESTED

16

iii

Output Resistance
VB Frequency

-

19

~

z

AMBIENT TEMPERA1\JRE (0C)

_PIN 12
TA " 25G

.l

§: 17 -OCTESTED

",

,/

~N ,~

NE5211 Output Resistance
vs Temperature

100

~

1

10
FREQUENCY (MHz)

100

•

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

TYPICAL PERFORMANCE CHARACTERISTICS

NE/SA5211

(Continued)

1

LSdB Output Step Response

Assuming typical values for RF a 14.4kn,
R'N = 200n, G'N = 4pF:

I

/

\

\

/

1\

J
0

2

4

6

8

THEORY OF OPERATION
Transimpedance amplifiers have been widely
used as the preamplifier in fiber-optic receivers. The NE521 1 is a wide bandwidth (typically 180MHz) transimpedance amplifier designed primarily for high sensitivity. The maximum input current before output stage clipping occurs at typically 501JA. The NE521 1 is
a bipolar transimpedance amplifier which is
current driven at the input and generates a
differential voltage signal at the outputs. The
forward transfer function is therefore a ratio
of the differenbal output voltage to a given
input current with the dimensions of ohms.
The main feature of this amplifier is a wideband, low-noise input stage which IS desensitized to photodiode capacitance variations.
When connected to a photodlode of a few
picoFarads, the frequency response Will not
be degraded significantly. Except for the Input
stage, the entire signal path is differential to
provide Improved power-supply rejection and
ease of Interface to EGl type circuitry. A
block diagram of the cirCUit is shown In Figure
1. The input stage (A 1) employs shunt-series
feedback to stabilize the current gain of the
amplifier. The transresistance of the amplifier
from the current source to the emitter of Os is
approximately the value of the feedback reSistor, RF = 14.4kn. The gain from the second stage (A2) and emitter followers (A3 and
A4) is about two. Therefore, the differenllal
transresistance of the entire amplifier, RT IS
VOUT (dlft)
RT = - 1 - - = 2RF
IN

= 2(14.4k) = 28.8kn.

The single-ended transresistance of the amplifier is typically 14.4kn.
The simplified schematic In Figure 2 shows
how an input current is converted to a differential output Voltage. The amplifier has a
single input for current which is referenced to
Ground 1. An input current from a laser diode,
December 1988

Vcc=5V_
TA = 25°C
20mVIDIv

"\

/
/
12

0

14

'"

16

18

20

for example, will be converted Into a voltage
by the feedback resistor RF. The transistor
01 provides most of the open loop gain of the
circuit, AVOL "'70. The emitter follower 02
minimizes loading on 01. The transistor 04,
resistor R7, and VBl provide level shifting and
interface With the 015-0 16 differential pair of
the second stage which is biased with an
internal reference, VB2. The differential outputs are derived from emitter followers
0 11 -0 12 which are biased by constant current sources. The collectors of 0 11 -012 are
bonded to an external pin, VCC2, In order to
reduce the feedback to the Input stage. The
output Impedance is about 17n single-ended.
For ease of performance evaluation, a 33n
resistor is used In series with each output to
match to a SOn test system.

BANDWIDTH CALCULATIONS
The input stage, shown In Figure 3, employs
shunt-series feedback to stabilize the current
gain of the amplifier. A Simplified analYSIS can
determine the performance of the amplifier.
The equivalent Input capaCitance, G,N, in
parallel With the source, Is, IS approximately
4pF, assuming that Gs = 0 where Gs is the
external source capacitance.
Since the input is driven by a current source
the Input must have a low input resistance.
The input reSistance, R'N, IS the ratio of the
Incremental Input voltage, Y,N, to the corresponding Input current, liN and can be calculated as:
RIN

= Y'N = ~ = 14.4k = 203n.
liN

.
2". R'N G'N

1 + AVOL

71

More exact calculations would yield a value of
200n
Thus G'N and R'N will form the dominant pole
of the entire amplifier,

5-122

1
LSdB = 2
F
".4p 200

= 200MHz.

The operating point of 01 has been optimized
for the lowest current noise without introducIng a second dominant pole in the pass-band.
All poles associated with subsequent stages
have been kept at sufficiently high enough
frequencies to Yield an overall single pole
response. Although wider bandwidths have
been achieved by using a cascode input
stage configuration, the present solution has
the advantage of a very uniform, highly desensitized frequency response because the
Miller effect dominates over the external
photodiode and stray capacitances. For example, assuming a source capacitance of
1 pF, input stage voltage gain of 70,
R'N = 200n then the total input capaCitance,
G'N = (1 + 4)pF which will lead to only a 20%
bandwidth reduction.

NOISE
Most of the currently Installed fiber-optic systems use non-coherent transmission and detect inCident optical power. Therefore, receiver noise performance becomes very important. The Input stage achieves a low input
referred noise current (spectral density) of
1.8pAlVRZ. The transresistance configuration assures that the external high value bias
resistors often required for photodiode biasIng will not contribute to the total noise
system noise. The equivalent Inpdt RMS noise
current IS strongly determined by the quiescent current of 010 the feedback resistor RF,
and the bandwidth; however, it is not dependent upon the internal Miller-capacitance.
The measured wldeband noise was 41 nA in a
200MHz bandwidth for Gs = 1pF

DYNAMIC RANGE
The electrical dynamic range can be defined
as the radiO of maximum input current to the
peak noise current:
Electrical dynamic range, DE, in a 200MHz
bandwidth assuming I,NMAX = 60IJA and a
wideband noise of lEO = 41 nARMS for an
external source capacitance of Gs - 1pF.
(Max. input current)

DE=~--~--~~~

(Peak noise current)

= 20

(60 X 10- 6 )

log .,...-;=------'--::("\12 41 X 10- 9)

Signetlcs Linear Products

Prellmlnory Spec,f,cot,on

Transimpedance Amplifier (180MHz)

NE/SA5211

(60JlA)
= 20 log (58nA) = 60dB.
In order to calculate the optical dynamic
range the Incident optical power must be
considered.
For a given wavelength A;
Energy of one photon =

hc
>:
watt sec (Joule)

Where h = Planck's Constant = 66 X 10- 34
Joule sec.
c = speed of light = 3 X 108 mt/ sec
ciA = optical frequency

Figure
1. _NESA5211
Block
L -_ _ _ _ _ _ _ _ _ _ _ _
____
______
_ _ _Diagram
_ _ _ _ _ _ _ _ _ _ _ __

P
No. of incident photons/sec = hc where
P = optical incident power

>:

P
No. of generated electrons/sec = 1/' hc

A
Where 1/ = quantum efficiency
no. of generated electron hole pairs

INPUT

r-------.,

I

!~*

OUT~

no. of Incident photons

I

P

'---------~~~vv..._-

_

i PHOTODI;DE

OUT+

I

..

I = 1/' hc • e Amps (Coulombs/sec.)

",

A
where e = electron charge = 1 6 X 10- 19
Coulombs
1/'e

Figure_
2. Trans-Impedance
L - -_
_ Amplifier
_ __

ResponslVIty R = hc Amp/watt
l,vMIN = q PavMIN

Assuming a data rate of 400 Mbaud (BandWidth, B = 200MHz). the nOise parameter Z
may be calculated as: 1
41 X 10- 9

ieq

Z=qB

J

A

1= P'R

hc

APPLICATION INFORMATION

707 X 10- 9 X 1 6 X 10- 19
23Xl0 '9
= 492nA.

(1.6 X 10 19) (200 X 106) = 1281

where Z IS the ratio of AMS nOise output to the
peak response to a single hole-electron pair.
Assuming 100% photodetector quantum efficiency, half mark/half space digital transmisSion, 850nm lightwave and uSing Gaussian
approximation, the minimum reqUired optical
power to achieve 10- 9 BER IS'
P,vMIN = 12

~
A

ChOOSing the maximum peak overload current of l,vMAX = 60JlA, the maximum mean
optical power IS'
hc l,vMAX
P,vMAX =--A-q-

= 86mW

23 X 10- 19

- - - = 60
16 X 10 19

or - 10 6dBm

Thus the optical dynamiC range, Do IS
B Z=12 23X 10- 19

200 X 106 1281 = 707nW =-31.5dBm,
where h IS Planck's Constant, c IS the speed
of light, A IS the wavelength. The minimum
Input current to the NE5210, at thiS Input
power IS:

Do = PavMAX- P,vMIN = -31 5- (-106)
= 20.8dB
ThiS represents the maximum limit attainable

with the NE5211 operating at 200M Hz bandWidth, with a half mark/half space digital
transmission at 820nm wavelength

1 S. 0 Personlck, Optical Fiber TransmissIon
Systems, Plenum Press, NY, 1981, Chapter 3

December 1988

X 10- 6

5-123

•

Package parasltlcs, particularly ground lead
Inductances and parasitic capacitances, can
significantly degrade the frequency response.
Since the NE5211 has differential outputs
which can feed back signals to the Input by
parasitic package or board layout capacItances, both peaking and attenuating type
frequency response shaping IS possible. Constructing the board layout such that Ground 1
and Ground 2 have very low Impedance paths
have produced the best results ThiS was
accomplished by adding a ground-plane
stripe underneath the deVice connecting
Ground 1, PinS 8-11, and Ground 2, Pins 1
and 2 on Opposite ends of the 5014 package ThiS ground-plane stnpe also provides
Isolation between the output return currents
flOWing to either VCC2 or Ground 2 and the
Input photodlode currents 10 flOWing to
Ground 1 Without thiS ground-plane stripe
and with large lead Inductances on the board,
the part may be unstable and OSCillate near
800MHz The easiest way to realize that the
part IS not functioning normally IS to measure

Signetlcs Linear Products

Preliminary Specification

Transimpedance Amplifier (180MHz)

the DC voltages at the outputs. If they are not
close to their quiescent values of 3.3V (for a
5V supply), then the cirCUit may be oscillating.
Input pin layout necessitates that the photodiode be phYSically very close to the Input
and Ground 1. Connecting Pins 3 and 5 to
Ground 1 will tend to shield the Input but It Will
also tend to Increase the capacitance on the
input and slightly reduce the bandwidth.

NE/SA5211

IS the use of a well-regulated power supply.
The supply must be capable of prOViding
varying amounts of current Without slgmflcantly changing the voltage level. Proper
supply bypaSSing requires that a good quality
O.lIlF high-frequency capacitor be Inserted
between VCCl and VCC2, preferably a chip
capecitor, as close to the package pinS as
pOSSible. Also, the parallel combination of
O.lIlF capacitors With lOIlF tantalum capacItors from each supply, VCCl and VCC2, to the
ground plane should prOVide adequate de-

As with any high-frequency deVice, some
precaubons must be observed In order to
enjoy reliable performance. The first of these

Rl

I..

INPUT

j-:-

coupling. Some applications may require an
RF choke In senes With the power supply line.
Separate analog and digital ground leads
must be maintained and pnnted CIrcUIt board
ground plane should be employed whenever
pOSSible.
Figure 4 depICts a 50Mb/s TIL fiber-optic
receiver uSing the BPF31 , 850nm LED, the
NE5211 and the NE5214 post amplifier. For
more Information on thiS CIrCUit, please refer
to Application Bnef AB1432.

R3

I. _
_

1--+
IF_-'VVV-- - 1

!

~~
Figure 3. Shunt-Series Input Stage

GND

G"!-=!Dl

LED

.

5z

~--(!)

R4
51K

VOUT(nL)

Figure 4. A 50Mb/s TIL Fiber-Optic Receiver Using NE5210/NE5214

December 1988

5-124

NEjSAjSE5212

Signetics

Transimpedance Amplifier
(140MHz)
Product Specification
Linear Products
DESCRIPTION

FEATURES

The NE/SA/SE5212 is a 14kS1 transimpedance, wideband, low noise dIfferential output amplifier, particularly sUitable
for signal recovery In fiber optic receivers and in any other applications where
very low signal levels obtained from
high-impedance sources need to be amplified.

•
•
•
•
•
•
•

PIN CONFIGURATION

Extremely low noise: 2.5pA/YHZ
Single 5V supply
Large bandwidth: 140MHz
Differential outputs
Low input/output impedances
High-power supply rejection ratio
14kS1 differential transresistance

IINmS 2
N, FE, D Packages

7

GND
OUT(-)

GND 1 3

6

GND 2

GNO l

5

OUT (+)

vee

2

4

APPLICATIONS
• Fiber-optic receivers, analog and
digital
• Current-to-voltage converters
• Wideband gain block
• Medical and scientific
instrumentation
• Sensor preamplifiers
• Single-ended to differential
conversion
• Low noise RF amplifiers
• RF signal processing

•

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

B-Pln PlastiC DIP

o to +70°C

NE5212N

B-Pln PlastiC SO

o to +70°C

NE5212D

DESCRIPTION

o to +70°C

NE5212FE

B-Pln PlastiC SO

-40°C to + B5°C

SA5212D

B-Pln PlastiC DIP

-40°C to + B5°C

SA5212N

B-Pin Ceramic DIP

-40°C to + B5°C

SA5212FE

B-Pln Ceramic DIP

B-Pln PlastiC DIP

-55°C to +125°C

SE5212N

B-Pln Ceramic DIP

-55°C to + 125°C

SE5212FE

December 7, 19BB

5-125

B53-1266 95294

Signetics Linear Products

Product Specification

NEjSAjSE5212

Transimpedance Amplifier (140MHz)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

PARAMETER

Vee

Power Supply

Po MAX

Power dissipation,
T A = 25'C (still air) 1
8-Pin Plastic DIP
8-Pin Plastic SO
8-Pin Cerdip

liN MAX

Maximum input current'!

UNIT

NE5212

SA5212

SE5212

6

6

6

V

1100
750
750

1100
750
750

1100
750
750

mW
mW
mw

5

5

5

mA

TA

Operating ambient
temperature range

-40 to 85

-55 to 125

TJ

Operating junction

-55 to 150

-55 to 150

-55 to 150

'c
'c

TSTG

Storage temperature
range

-65 to 150

-65 to 150

-65 to 150

'C

o to

70

NOTES:
1. Maximum diSSipation IS determined by the operating ambient temperature and the thermal resistance:
8-Pln Plastic DIP' 110'C/W
8-Pln Plastic SO: 160'C/W
8-Pln Cerdip: 165'C/W
2. The use of a pull-up resistor to Vee. for the PIN diode, IS recommended

RECOMMENDED OPERATING CONDITIONS
PARAMETER

RATING

UNIT

4.5 to 5.5

V

Ambient temperature ranges
NE Grade
SA Grade
SE Grade

o to +70
-40 to +85
-55 to + 125

'C
'C
'C

Junction temperature ranges
NE Grade
SA Grade
SE Grade

o to +90
-40 to + 105
-55 to + 145

'c

SYMBOL
Vce

Supply voltage range

TA

TJ

'C
'C

DC ELECTRICAL CHARACTERISTICS Minimum and Maximum hmits apply over operating temperature range at Vec = 5V,
unless otherwise specified. Typical data applies at Vee = 5V and TA = 25'C.
SAlSE5212

NE5212
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

Min

Typ

Max

V

Y'N

Input bias voltage

0.6

0.8

0.95

0.55

0.8

1.05

Vo±

Output bias voltage

2.8

3.3

3.7

2.5

3.3

3.8

V

VOS

Output offset voltage

120

mV

33

mA

80

Icc

Supply current

21

26

20

26

lOMAX

Output sink/ source current

3

4

3

4

mA

±60

±80

±40

±80

p.A

±80

± 120

±60

± 120

p.A

liN

Input current (2% linearity)

Test Circuit 6, Procedure
2

IN MAX

Maximum Input current overload
threshold

Test Circuit 6, Procedure
4

December 7, 1988

5-126

32

Product Specification

Signetics Unear Products

NE/SA/SE5212

Transimpedance Amplifier (140MHz)

AC ELECTRICAL CHARACTERISTICS

Minimum and Maximum limits apply over operating temperature range at Vee = 5V,
unless otherwise specified. TYPical data applies at Vee = 5V and TA = 25°C.
NE5212

PARAMETER

SYMBOL

SAlSE5212

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

RT

T ransreslstance
(differential output)

DC tested, RL = 00
Test Circuit 6, Procedure
1

9.8

14

18.2

9.0

14

19

kn

Ra

Output resistance
(differential output)

DC tested

14

30

42

14

30

46

n

RT

Transreslstance
(single-ended output)

4.9

7

9.1

4.5

7

9.5

kn

Ra

Output resistance
(Single-ended output)

DC tested

7

15

21

7

15

23

n

f3dB

BandWidth (-3dB)

Test CircUit 1
D package,
TA = 25°C
N, FE packages,
TA = 25°C

100

140

100

140

100

120

70

110

150

n

10

18

pF

R'N

Input resistance

C'N

Input capaCitance

AR/AV

Transreslstance power
supply senSitivity

AR/AT

DC tested, RL =

00

100

120

75

110

143

10

15

MHz
MHz

Vee = 5 ±0.5V

96

9.6

%IV

Transreslstance ambient
temperature sensitivity

D package
AT A = TA MAX - TA MIN

0.05

0.05

%rC

IN

RMS nOise current spectral density
(referred to Input)

Test CIrcUIt 2
f = 10MHz T A = 25°C

2.5

2.5

pA/YHz

IT

Integrated RMS noise
current over the bandwidth
(referred to Input)
CS=01

TA = 25°C
Test CirCUit 2
Af=50MHz
Af= 100MHz
Af = 200M Hz

20
27
40

20
27
40

nA
nA
nA

Cs = 1pF

Af=50MHz
Af= 100MHz
Af = 200M Hz

22
32
52

22
32
52

nA
nA
nA

PSRR

Power supply relectlon ran0 2

Any package
DC tested
AVee= 0.1V
Equivalent AC
Test Circuit 3

33

dB

PSRR

Power supply rejection ratlo 2
(ECl configuration)

Any package
f=01MHz 1
Test CirCUit 4

23

dB

Va MAX

Maximum differential output voltage
sWing

RL = 00
Test CirCUit 6, Procedure
3

3.2

Vp_p

V,N MAX

Maximum input amplitude for output
duty cycle of 50 ± 5%3

Test Circuit 5

325

325

mVp_p

tR

Rise time for 50mV output signal'

Test CirCUit 5

2.0

2.0

ns

26

33

20

23

2.4

3.2

1.7

NOTES:
1 Package parasitiC capacitance amounts to about 0 2pF
2 PSRR IS output referenced and IS Circuit board layout dependent at higher frequencies For best performance use RF filter In Vee hne
Guaranteed by hneanty and over load tests

t., defined as 20 - 80% rise time It

December 7, 1988

IS

guaranteed by -3dB bandWidth test

5-127

•

Signetics Unear Products

Product Specification

NE/SA/SE5212

Transimpedance Amplifier (140MHz)

TEST CIRCUITS
DIFFERENnAL

BINGLE-ENDED

RI - VOUT A=2xS2txA At- VOUT R-4x$2txA
V,N
VIN

11-822 1

1+
Ro'Zo -822
-33

11+8221
1-822

Ao=2Z0 - - · 6 8

NC

Test Circuit 1

Test Circuit 2

NETWORK ANALVZER

8-PARAMETER TEST SET

PORr 1

CURRENT PROBE
1mV/mA

TeBt Circuit 3

December 7, 1988

5-128

PORr 2

Signetlcs Linear Products

Product Specification

Transimpedance Amplifier (140MHz)

NE/SA/SE5212

TEST CIRCUITS (Continued)

NETWORK ANALYZER

S-PARAMETER TEST SET

GND

PORT 1

PORT 2

CURRENT PROBE

1mVlmA

L-~~~

____________________________________

TRANSFORMER
NH0300HB

100
BAL.

~CAL

~TEST
UNBAL.

•

Test Circuit 4

PULSE GEN

l~~~~_l{"~F-4______~~~;;~-'
A
Zo=5On

OUT!-

OSCILLOSCOPE

1-------{JB[j Zo =50 n
Me.aurement done using
differential wave forme

Test Circuit 5

December 7, 1988

5-129

Signetlcs Linear Products

Product Specification

NEjSAjSE5212

Transimpedance Amplifier (140MHz)

TEST CIRCUITS (Continued)

r

+

OUT+-

.l -

IN DUT

'.~cp

OUT-

Yo (VOLTS)

QN~ND2
TC23462S

Typical Vo (Differential) vs liN

2.00
1.60

~

1.20

w
C

0.80

..
c!

....
>

L('

/'
",,/

OAO

::I

!;
0
....
z~
w

.
II:

0.00

,/

-OAO

./

-0.80

/'/

w

is

/

-1.20

V

-1.80
-2.00
-400

-320

-240

-160

-80

0

CURRENT INPUT

80

160

240

320

400

(1'1\)
Of'20990S

NE5212 TEST CONDITIONS
Procedure 1

RT measured at 30p.A
RT = (VOl - V02)/(+30p.A - (-30MA))
Where: Val Measured at liN = + 30MA
V02 Measured at liN = -30MA

Procedure 2

linearity = 1 - ABS«VOA - Vosl (Vas - Vo4))
Where: Vas Measured at liN = + 60MA
V04 Measured at liN = -60MA
VOA = RT • (+60p.A) + Vas
Vas = RT • (-60MA) + Vas

Procedure 3

VOMAX = V07 - Vas
Where: V07 Measured at liN = + 130MA
VAS Measured at liN = -130j.lA

Procedure 4

liN MAX Test Pass Conditions:
V07 - V05 > 50mV and Vee - V05 > 50mV
Where. V05 Measured at liN = +80MA
V06 Measured at liN = -80MA
Va? Measured at liN = + 130MA
VAS Measured at liN =-130j.lA
Test Circuit 6

December 7. 1988

5-130

Signetics linear Products

Product Specification

Transimpedance Amplifier (140MHz)

NEjSAjSE5212

TYPICAL PERFORMANCE CHARACTERISTICS
NE5212 Supply Current
vs Temperature
30

NE5212 Output Bias Voltage
vs Temperature
9SO

vJ)s.oJ
.......

.......

3.SO

vL=ls.oL

i'...

"

r-....

" r--. "-~-~-~o

~

~

~

NE5212 Differential Output
Swing vs Temperature

S

r-

r
~

2.

RL

2

0

./

~

V

g

20

... V

Iii

~

0-40

ij

17
16

aVec = ±O.1V

./'

0:40 r-DCTESTED

35

0:

~

... V

8:

~ 30
0:
W

~

0.

VV
/"

OUTPUT REFERRED

VV

./'

;!

t~s.~v
RL

~ 16.0

V

=oc

m

/

ffi

14. 5

VV

40

20 0

20 40 60 80 100 120 140

C 14.0
-60 -40 -20 0

20 40 60 80 100 120 140

AMBIENT TEMPERATURE ("C)

NE5212 Typical
Bandwidth Distribution
(75 Parts from 3 Wafer Lots)

- vc~ = ~.oJ

DC TESTED

w

o

~ 14

~
w

0:

~

13

1'\
12

0.

11

I'-.

r- PIN-r-7
....... ...... PI~ 5

V

V
~

./

10
25
-60 40 -20 0

FREOUENCY (MHz)

20 40 60 80 100 120 140

AMBIENT TEMPERATURE eC)

December 7. 1988

9

V

...... V

2.15

8

/'

0

~ 16.
z 5 -DC TESTED

it

NE5212 Output Resistance
vs Temperature

tLs.bv J

f7.

~ 15.0

AMBIENT TEMPERATURE ('C)

NE5212 Power Supply Rejection
Ratio vs Temperature

NE5212 Differential Transresistance
vs Temperature

~

V

-60
-80

20 40 60 80 100 120 140

AMBIENT TEMPERATURE eC)

20 40 60 80 100 120 140

~ 15.5

... V

~ -20

2. 4
-60 40 -20 0

-

V OUTS - V OUT7

VV

~

V-

a

~ 2.6

~
ia

Vos

~ 40
;!

t;

AMBIENT TEMPERATURE ("C)

NE5212 Output Offset Voltage
vs Temperature

60

=X

~

;?

3.25
-60 -40 -20 0

20 40 60 80 100 120 140

! f-tJs.olv
=

DC TESTED

~ 3.4

~

3.35

g3.30

80

6t-vic Js.ot

E 3•
~

iii

AMBIENT TEMPERATURE eC)

3.a

~ .-'

!f,!

r'-,

"

600
-60 -40 -20 0

AMBIENT TEMPERATURE eC)

PIN 7

V ~ VI-'""

>

r'\.

"

iINJ~V V

w

i'...

~1001~1~

tLs.!v

~3.45

~
g
3.40

r....,

i'...

25

NE5212 Output Bias Voltage
vs Temperature

-60 -40 -20 0

20 40 60 80 100 120 140

AMBIENT TEMPERATURE ("C)

5-131

•

Signetics Linear Products

Product Specification

NE/SA/SE5212

Transimpedance Amplifier (140MHz)

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain vs Frequency
12

-

11

1111I111

Vee

11

ve~UJIIIII

10

Vee

45V

70

Vee -sov III

V

11111

,

60

N PKG

r- ~~c= =2~~ctt!tt-+--H-Hiijj-----r-H-ttHitI{\-j

o

~\

Vee - 45V

:~

I~

1\

,

M~~I~I~~~rr=~~n=~

- 55V

1..... 1

f//
Vee-SOV

Output Resistance
vs Frequency

Gain vs Frequency

20

"

10

10

PIN 5

'\

"

100

10

100

FREQUENCY (MHz)

FReQUENCY (MHz)

FREQUENCY (MHz)

Output Resistance
vs Frequency
I--

t--

Vee - 5V

I ~sac

10

8 - -rtitittt-H-ttttHt-+++tittiffiri
7 t--t---f+H-H+t-++++t1+tt·-I-t++H+t1\\\-l
~ 6 t--t-;--Ititittt-H-ttttHt--tTA" 125 lC""
iD
"

0

I

~

7

Z

6

;;

I~

I-

..L

I

,,.

10
FReQUENCY (MHz)

"

FREQUENCY (MHz)

Gain and Phase Shift
vs Frequency

.

I IIIIII

I

I III

N PI(G
PIN 5

Vee = sv
TA ~ 25'C

.\

'II

II

-

t-~ PKG

December 7, 1988

"

T,

TA " _55°C

I

I

I
I
,I ,
II
II

1111,

I
10
FREQUENCY (MHz)

5-132

~'II';;;~
i

II LUIIi
I11I1111

10

'00

FREQUENCY (MH/!)

\

I\
\
\

I lilli,
I'ill!

I

TA " -55 C

Gain and Phase Shift
vs Frequency

•

Vee = SV
TA " 2~O~ i

85°C

A - 125'C",' TA " 25"C

PIN 7

Ii
fREOUENCY (MHz)

100

10

Gain and Phase Shift
vs Frequency

I

I I I
I I

I
I

PIN 7

I,
i

~

I

l\

--

I
I

PIN 5

,

"

Gain vs Frequency

,

III

OiPKG

TA

Gain vs Frequency

10
FREQUENCY (MHz)

-270

Signetics Linear Products

Product Specification

Transimpedance Amplifier (140MHz)

NE/SA/SE5212

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain and Phase Shift
vs Frequency

Differential Output Voltage
vs Input Current

Differential Output Voltage
vs Input Current

1

.,9

20

~

0

~

w

o

•

PKG

PINS
Vee = 5V
TA ~ 2S'C

"~o

\
\
1\

6

.
5

"
~

>

g

..

!;
!;

~

..

!;
!;
o

o

..J

"
~
w

3

10

..J

~

ffi

FREQUENCY (MHl)

S.OV

w

a:
w

it

~
S.OV

it

is

is

-20

Output Voltage
vs Input Current
2.000

25 C __

II
II

I;'
0-

r-

/

/

J

0;-

V

S2

1;
.--

ol

-

•

f'V

0

c

i

~

~~25C
:..- 85 C
o

-200
-1500

125

cl

1500
INPUT CURRENT

01

(~(A)

20

40

60

80

100

120

140

160

FREOUENCY (MHz)

Output Step Response
2omJolv_

"-

~

/

/

Vee'" 5V
TA "'25"C_

\

\

il
/

./

I

\

[\.
~

I
10
(ns)

December 7. 1988

150.0

10

8s'e

,,- ~

-

o
INPUT CURRENT (tAA)

Group Delay
vs Frequency

55 C'A

0

I~

/

V

:::p'4.SY

-150.0

INPUT CURRENT (,uA)

~

1/

V

5.5Y

~

12

14

16

5-133

-

18

20

Signetics Linear Products

Product Specification

NE/SA/SE5212

Transimpedance Amplifier (140MHz)

THEORY OF OPERATION
Translmpedance amplifiers have been widely
used as the preamplifier In fiber optiC receivers The NE5212 IS a wide bandwidth (tYPically 130M Hz) tra%lmpedance amplifier designed pnmanly for high sensitivity The maXimum Input current before output stage clipping occurs at tYPically 120l'A The NE5212
IS a bipolar translmpedance amplifier which IS
current dnven at the Input and generates a
differential voltage signal at the outputs. The
forward transfer function IS therefore a ratio
of the differential output voltage to a given
Input current With the dimensions of ohms
The main feature of thiS amplifier IS a wldeb!':md, low~norse Input stage which IS desensItized to photodlode capacitance vanatlons
When connected to a photodlode of a few
picoFarads, the frequency response Will not
be degraded significantly. Except for the Input
stage, the entire signal path IS differential to
provide Improved power-supply rejection and
ease of Interface to EGl type CIrcuitry A
block diagram of the CIrCUIt IS shown In
Figure 1 The Input stage (A 1) employs shuntsenes feedback to stabilize the current gain
of the amplifier The transreslstance of the
amplifier from the current source to the emitter of 0 3 is approximately the value of the
feedback reSistor, RF - 7.2kn The gain from
the second stage (A2) and emitter followers
(A3 and A4) IS about two. Therefore, the
differential transreslstance of the entire amplifier, RT IS
VouT(dlff)
RT - - - - - - 2RF - 2(7 2k) - 14 4kn
liN
The Single-ended transreslstance of the amplifier IS typically 7 2kn
The Simplified schematiC In Figure 2 shows
how an Input current IS converted to a differential output voltage. The amplifier has a
single Input for current which IS referenced to
Ground 1. An Input current from a laser diode,
for example, Will be converted Into a voltage
by the feedback resistor RF The transistor
01 prOVides most of the open loop gain of the
CirCUit, AVOL""70. The emitter follower 02
minimizes loading on 0 , The transistor 0 4 ,
resistor R 7 , and VBl prOVide level shifting and
Interface With the 0 ,5-0,6 differential palf of
the second stage which IS biased With an
Internal reference, VB2 The differential outputs are denved from emitter followers
0,,-0 '2 which are biased by constant current sources. The collectors of 0,,-0'2 are
bonded to an external pin, VCC2 , In order to
reduce the feedback to the Input stage The
output Impedance IS about 17n Single-ended
For ease of performance evaluation, a 33n
resistor IS used In senes With each output to
match to a 50n test system.

December 7, 1988

Figure 1. NE5212 - Block Diagram

INPUT

r-------..,
I

!"*

OUT-

I__
PHOTODIO-DE -

I

&,.., -

-

-- -

OUT+

I

_ _ ...J

'---'WIr---+

Figure 2. Trans-Impedance Amplifier

BANDWIDTH CALCULATIONS:
The Input stage, shown In Figure 3, employs
shunt·senes feedback to stabilize the current
gain of the amplifier. A Simplified analysis can
determine the performance of the amplifier.
The eqUivalent Input capaCitance, G,N, In
parallel With the source, Is, IS approximately
10pF, assuming that Gs - 0 where Gs IS the
external source capacitance.
Since the Input IS dnven by a current source
the Input must have a low Input resistance.
The Input reSistance, R'N, IS the ratio of the
Incremental Input voltage, V,N, to the corresponding Input current, liN and can be calculated as.
V ,N
RF
72k
R,N - - - - - - - - - 1 0 3 n .
liN
1 + AVOL
70

More exact calculations would Yield a value of
110n
Thus G'N and R'N Will form the dominant pole
of the entlfe amplifier;

Assuming Iyplcal values for RF
R'N - 11 on, G,N - 10pF:

7.2kn,

1
f.3dB - 2" 110 10 X 10-12 -145MHz.
The operating pOint of 01 has been optimized
for the lowest current nOise Without introducIng a second dominant pole in the pass-band.
All poles associated With subsequent stages
have been kept at sufficiently high enough
frequencies to Yield an overall Single pole
response. Although Wider bandWidths have
been achieved by uSing a cascade Input
stage configuration, the present solution has
the advantage of a very uniform, highly desensitized frequency response because the
Miller effect dominates over the external
photodlode and stray capacitances. For example, assuming a source capacitance of
1 pF, Input stage voltage gain of 70,
R'N - 11 on then the total Input capacitance,
G'N - (1 + 10) pF which Will lead to only a 9%
bandWidth reduction.

1

NOISE
Most of the currently Installed fiber OptiC
systems use non-coherent transmission and
detect InCident optical power. Therefore, receiver nOise performance becomes very im-

5-134

Signetics Linear Products

Product Specification

NE/SA/SE5212

Transimpedance Amplifier (140MHz)

,--r--,-oYcc

+5V

A3

~ I-A..,=,..560"v-::-.t

VON

TC1I551S

a. Non-Inverting 20dB Amplifier
+5V

Figure 3. Shunt-Series Input Stage
portant. The Input stage achieves a low input
referred nOise current (spectral density) of
2.5pA/YHz. The transreslstance configuration assures that the external high value bias
resistors often required for photodlode biasing will not contribute to the total nOise
system noise. The equivalent input RMS
noise current IS strongly determined by the
quiescent current of 0 1, the feedback resistor
RF, and the bandWidth; however, it IS not
dependent upon the internal Miller-capacitance. The measured wide band noise was
52nA in a 200MHz bandWidth for Cs = 1pF.

Electrical dynamic range, DE, In a 200MHz
bandwidth assuming I,NMAX = 120pA and a
wideband noise of lEa = 52nARMS for an
external source capacitance of Cs = 1pF.
(Max. input current)
DE = (Peak nOise current)
(120 X 10- 6)
52 X 10-9)

(V2

(120j.lA)
20 log - - = 64dB.
(73nA)

In order to calculate the optical dynamic
range the incident optical power must be
considered.
For a given wavelength X;
Energy of one photon =

hc

~

watt sec (Joule)

Where h = Planck's Constant = 6.6 X 10- 34
Joule sec.
c = speed of light = 3 X 108 mtl sec
c/X = optical frequency

P
No. of generated electrons/ sec = 1'/ • hc

b. Inverting 20dB Amplifier

X
Where 1'/ = quantum effiCiency

+5Y

no. of generated electron hole pairs
no. of incident photons

X
where e = electron charge = 1.6 X 10- 19
Coulombs
1'/"9

X

I=P'R

897 X 10- 9 X 1.6 X 10- 19
2.3 X 10- 19
= 624nA.

x 106)

=1625

where Z IS the ratio of RMS noise output to
the peak response to a Single hole-electron
palf. Assuming 100% photodetector quantum
efficiency, half mark/half space digital transmiSSion, B50nm hghtwave and uSing GaussIan approximation, the minimum reqUired optical power to achieve 10- 9 BER is:
hc

PavMIN=12 ~ B Z=12 2.3X10-

19

200 X 106 1625 = 897nW = - 30.5dBm,
where h IS Planck's Constant, c IS the speed
of light, X IS the wavelength. The minimum

5-135

Figure 4

hc

Assuming a data rate of 400 Mbaud (BandWidth, B = 200MHz), the nOise parameter Z
may be calculated as:
leq
52 X 10- 9
Z=-=
qB (1.6 X 10- 19) (200

c. Differential 20dB Amplifier

input current to the NE5212, at thiS Input
power is:
X
lavMIN = qPavMIN

ResponslVlty R = ~ Amp/watt

1 S. O. Personick, Op&cal Fiber TransmIssion Systema, Plenum Press, NY, 1981, Chapter 3
December 7, 1988

~. t-"'VIf\r:::1

I = 1'/' hc' e Amps (Coulombs/sec.)

The electrical dynamic range can be defined
as the radio of maximum input current to the
peak noise current:

~

VON

P

DYNAMIC RANGE:

= 20 log

R =560

P
No. of inCident photons/ sec = hc where
P = opllCal InCident power
};"

Choosing the maximum peak overload current of lavMAX = 120pA, the maximum mean
optical power IS:
hc lavMAX 2.3 X 10- 19
6
PavMAX=---19=120X10Aq
1.6X 10= 86mW or -7.6 dBm.

Thus the optical dynamic range, Do IS:
Do = PavMAX- PavMIN = -30.5-( -7.6) = 22.8dB.
ThiS represents the maximum limit attainable
With the NE5212 operating at 200MHz bandwidth, with a half mark/half space digital
transmission at 820nm wavelength.

•

Signetlcs Linear Products

Product Specification

Transimpedance Amplifier (140MHz)

I-<>

L

__

r---, ~OUT

NEjSAjSE5212
amp. This op amp is configured in a non·
inverting gain of five. The output drives the
gate of the SD210 DMOS FET. The series
resistance of the FET changes with this
output voltage which in turn changes the gain
of the NE5212. ThiS Circuit has a distortion of
less than 1 % and a 25dB range, from
-42.2dBm to -15.9dBm at 50MHz, and a
45dB .range, from -60dBm to -14.9dBm at
10MHz With 0 to IV of control voltage at Vc.

16MHz CRYSTAL OSCILLATOR
Figure 6 shows a 16MHz crystal oscillator
operating In the senes resonant mode uSing
the NE5212 The non'lnverting input IS fed
back to the Input of the NE5212 In series with
a 2pF capacitor. The output is taken from the
inverting output.

101<

2Ak

Figure 5. Variable Gain Circuit

APPLICATION INFORMATION
Package parasltics. particularly ground lead
Inductances and parasitic capacitances, can
significantly degrade the frequency response
Since the NE5212 has differential outputs
whloh can feed back signals to the Input by
psrasltlc package or board layout capaci'
tances, both peaking and attenuating type
frequency response shaping IS possible. Con·
structlng the board layout such that Ground 1
and Ground 2 have very low Impedance paths
have produced the best results. ThiS was
acomplished by adding a ground-plane stripe
underneath the device connecting Ground 1,
PinS 8-11, and Ground 2, PinS 1 and 2 on
opposite ends of the S014 package. ThiS
ground-plane stnpe also provides Isolation
between the output return currents flOWing to
either VCC2 or Ground 2 and the Input photo·
diode currents to flowing to Ground 1. Without thiS ground-plane stnpe and with large
lead Inductances on the board, the part may
be unstable and oscillate near 800M Hz. The
easiest way to realize that the part IS not
functioning normally IS to measure the DC
voltages at the outputs. If they are not close
to their quiescent values of 3.3V (for a 5V
supply), then the OlrcUit may be oscillating.
Input pin layout necessitates that the photodiode be phYSically very close to the Input
and Ground 1. Connecting Pins 3 and 5 to
Ground 1 will tend to shield the Input but It Will
also tend to Increase the capacitance on the
Input and slightly reduce the bandWidth
As With any hlgh·frequency device, some
precautions must be observed In order to
enloy reliable performance The first of these
IS the use of a well-regulated power supply
The supply must be capable of prOViding
December 7, 1988

varying amounts of current Without slgnlfl'
cantly changing the voltage level. Proper
supply bypassing requires that a good quality
O.I/lF hlgh·frequency capacitor be Inserted
between Vee1 and Vcc2, preferably a chip
capaCitor, as close to the package pinS as
pOSSible. Also, the parallel combination of
O.I/lF capacitors With 10/lF tantalum capacItors from each supply, Vcc l and Vcc2, to the
ground plane should prOVide adequate decoupling. Some applications may require an
RF choke In senes With the power supply line.
Separate analog and digital ground leads
must be maintained and pnnted CirCUit board
ground plane should be employed whenever
pOSSible

BASIC CONFIGURATION
A trans resistance amplifier IS a current-tovoltage converter. The forward transfer function then IS defined as voltage out diVided by
current In, and IS stated In ohms. The lower
the source reSistance, the higher the gain
The NE5212 has a differential transreslstance of 14kQ typically and a Single-ended
transreslstance of 7kQ typically The deVice
has two outputs. Inverting and non-inverting.
The output voltage In the differential output
mode IS tWice that of the output voltage In the
Single-ended mode. Although the deVice can
be used Without coupling capaCitors, more
care IS reqwred to aVOid upsetting the Internal
bias nodes of the deVice. Figure 4 shows
some baSIC configurations.

VARIABLE GAIN
Figure 5 shows a variable gain CirCUit uSing
the NE5212 and the NE5230 low voltage op

5-136

Figure 6. 16MHz Crystal Oscillator

DIGITAL FIBER OPTIC
RECEIVER
Figures 7 and 8 show a fiber opbc receiver
uSing off·the·shelf components.
The receiver shown In Figure 7 uses the
NE5212, the Signetics 10116 ECl line receiv·
er, and Philips! Amperex BPF31 PIN diode.
The CirCUit is a capacitor-ooupled receiver
and utilizes positive feedback in the last stage
to prOVide the hysteresIs. The amount of
hysteresIs can be tailored to the individual
application by changing the values of the
feedback resistors to maintain the desired
balance between nOise Immunity and sensi·
tlvlty. At room temperature, the circuit oper·
ates at 50Mbaud with a BER of 10E·l0 and
over the automotive temperature range at
40Mbaud With a BER of 10E·9. Higher speed
experimental diodes have been used to oper·
ate thiS Circuit at 220Mbaud with a BER of
10E-tO.
Figure 8 depicts a TTL receIVer using the
NE52t2 and the NE5214 fast amplifier system along With the Philips! Amperex PIN dl·
ode. The system shown is optimized for 50
Mb!s Non Return to Zero (NRZ) data. A link
status indication IS provided along with a
lamming function when the input level is
below a user-programmable threshold level.

Signetlcs Linear Products

Product Specification

Transimpedance Amplifier (140MHz)

December 7, 1988

5-137

NEjSAjSE5212

Signetics Linear Products

Product Specification

Transimpedance Amplifier (140MHz)

NE/SA/SE5212

GND

G=!"~

11
10,u:H

R1
100

C3
10~F

6 GN02

'--t-ill OUT-

.
~

z

R4
51K

Figure 8. A 50Mb/S TTL Digital Fiber Optic Receiver

December 7, 1988

5-138

:±

rn....:.--.JC4 ":"
01,uF

NEjSA5214

Signetics

Postamplifier with Link Status
Indicator
Preliminary SpeCification

Linear Products
DESCRIPTION

FEATURES

THE NE/SA5214 is a 75MHz postamplifier system designed to accept low level
high-speed signals. These signals are
converted into a TIL level at the output.
The NE5214 can be DC coupled with the
previous transimpedance stage using
NE5210, NE5211 or NE5212 transimpedance amplifiers. This "system on a
chip" features an auto-zeroed first
stage with noise shaping, a symmetrical
limiting second stage, and a matched
rise/fall time TIL output buffer. The
system is user-configurable to provide
noise filtering, adjustable input thresholds and hysteresis. The threshold capability allows the user to maximize signalto-noise ratio, insuring a low Bit Error
Rate (BER). An Auto-Zero loop can be
used to minimize the number of external
coupling capacitors to one. A signal
absent flag indicates when signals are
below threshold. Additionally, the low
Signal condition forces the overall TIL
output to a logical Low level. User interaction with this "jamming" system is
available. The NE/SA5214 is packaged
in a standard 20-pin surface-mount
package and typically consumes 42mA
from a standard 5V supply. The NE/
SA5214 is designed as a companion to
the NE/SA5211/5212 transimpedance
amplifiers. These differential preamplifiers may be directly coupled to the postamplifier inputs. The NE/SA5212/5214
or NE/SA5211 /5214 combinations convert nanoamps of photodetector current
into standard digital TIL levels.

• Postamp for the NE/SA5211/5212
preamplifier family
• Wideband operation: typical
75MHz (100MBaud NRI)
• Interstage filtering/equalization
possible
• Single 5V supply
• Low signal flag
• Low signal output disable
• Link status threshold and
hysteresis programmable
• LED driver (normally ON with
above threshold signal)
• Fully differential for excellent
PSRR
• Auto-zero loop for DC offset
cancellation
• 2kV ElectroStatic Discharge (ESD)
protection

PIN CONFIGURATION
0 1 Package

TOP VIEW
NOTE:
1 SOL - Released In large SO package only

=~

APPLICATIONS
CPKDET

• Fiber optics
• Communication links In Industrial
and/or Telecom environment with
high EMIIRFI
• Local Area Networks (LAN)
• Metropolitan Area Networks
(MAN)
• Synchronous Optical Networks
(SONET)

THRESH

GNDA
FLAG

JAM

• RF limiter

VCCD
VCCA

ORDERING INFORMATION
DESCRIPTION

20-Pin Plastic SOL
20-Pin Plastic SOL

December 1988

SYMBOL
LED

TEMPERATURE RANGE

o to

+70·C

ORDER CODE

NE5214D

-40·C to + 85·C

SA5214D

5-139

9
10

GNDo
Vour

11

RpKDET

DESCRIPTION
Output for the LEO dnver Open
collector output transistor with
12S,Q senes limiting reSistor An
above threshold Signal turns thiS
transistor ON
Capacitor for the peak detector
The value of thiS capacitor de*
termlnes the detector response
time to the Signal, supplementmg
the mternal 10pF capacitor
Peak detector threshold resistor
The value of thiS reSistor determines the threshold level of the
peak detector
Device analog ground pm
Peak detector digital output
When thiS output IS LOW, there
IS data present above the
threshold ThiS pin IS normally
connected to the JAM pin and
has a TIL fanout of two
Input to mhlblt data flow Send109 the pm HIGH forces TIL
DATA OUT ON, Pin 10, LOW
ThiS pm IS normally connected
to the FLAG pm and IS TILcompatible
Power supply pm for the digital
portion of the chip
Power supply pin for the analog
portion of the chip
Device digital ground pm
TIL output pin with a fanout of
five
Peak detector current resistor
The value of thiS resistor determines the amount of discharge
current available to the peak detector capaCitor, CPKOET

•

Signetics Linear Products

Preliminary

NEjSA5214

Postamplifier with link Status Indicator

PIN CONFIGURATION (cont.)
PIN
NO.

12

DESCRIPTION

SYMBOL
RHYST

13

IN2A

14

OUT,A

15
16
17

IN..
OUT,B
CAZN

Peak detector hystereas reSistor
The value of thIS reSistor
determines the amount of
hysteresis In the peak detector
Non-Inverting Input to ampilfler
A2
Non-Inverbng output of amplifier
A1
Inverting Input to amplifier A2
Inverting output of amplifier At
Auto-Zero capaCltaI" pin
(NegatIVe terminal) The value of

18

CAl.

19

IN'A

20

IN,s

thiS capacttor determines the
low-end frequency response of
the preamp A1.
Auta-.Zero capacitor pin (Po8lbve
terminal) The value of thiS
capaCitor determines the low-end
frequency response of the
Pfeamp A1.
Non-Inverttng Input of the
preamp At
Inverting Input of the preamp
A1

BLOCK DIAGRAM

.,..,.

Your

> ____--'Ljo FLAG
LED

GNDA QNDa

December 1988

T....8H

5-140

Spec~ication

Signetics Linear Products

Preliminary Specification

Postamplifier with Link Status Indicator

NE/SA5214

ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL

PARAMETER

UNIT
NE5214

SA5214

VCCA

Power supply

+6

+6

Vcco

Power supply

+6

+6

V

TA

Operating ambient temperature range

o to +70

-40 to +85

°C

TJ

Operating junction temperature range -55 to +150 -55 to +150

TSTG

Storage temperature range

Po

Power diSSipation

300

300

mW

VIJ

Jam Input voltage

-0.5 to 5.5

-0.5 to 5.5

V

V

-65 to +150 -65 to +150

°C
°C

RECOMMENDED OPERATING CONDITIONS
RATING
SYMBOL

PARAMETER

UNIT
NE5214

SA5214

VCCA

Supply voltage

4.75 to 5.25

4.75 to 5.25

V

Vcco

Power supply

475 to 5.25

4.75 to 5.25

V

TA

Ambient temperature range

TJ

Operating junction temperature range

Po

Power diSSipation

o to
o to

+70

-40 to +85

°C

+95

-40 to +110

°C

250

mW

250

•

DC ELECTRICAL CHARACTERISTICS Min and Max limits apply over the operating temperature range at
VCCA = Vcco = + 5.0V unless otherwise specified. TYPical data applies at
VCCA = Vcco = +5.0V and TA = 25°C.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

NE5214
Min

Typ

SA5214
Max

Min

UNIT

Typ

Max

ICCA

Analog supply current

30

36

30

37.2

mA

Icco

DigRal supply current
(TTL. Flag. LED)

10

13.3

10

13.5

mA

VI1

A 1 input bias voltage
(+ /- inputs)

3.16

3.4

3.63

3.13

3.4

3.65

V

V01

A 1 output bias voltage
(+ /- outputs)

3.17

3.8

4.45

3.10

3.8

4.50

V

AY1

A1 DC gain
(without Auto-Zero)

A1psRR

A1 PSRR (VCCA. Vcco)

A1cMRR

A1 CMRR

VI2

A2 input bias voltage
(+ /- inputs)

VOH

High-level TIL output
voltage

IOH = -200jIA

VOL

Low-level TIL output
voltage

IOL=8mA

0.3

0.4

0.3

0.4

V

IOH

High-level TIL output
current

VOUT= 2.4V

-40

-26

-40

-24.4

mA

IOL

Low-level TIL output current

VOUT= O.4V

December 1988

30

30

dB

VCCA = Vcco = 4.75 to 5.25V

60

60

dB

tNCM = 200mV

60

60

dB

5-141

3.59

3.7

2.4

3.4

8.0

30

3.85

3.56

3.7

2.4

3.4

7.0

30

3.86

V
V

mA

Signetics Linear Products

Preliminary Specification

NE/SA5214

Postamplifier with Link Status Indicator

DC ELECTRICAL CHARACTERISTICS (Continued) Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. Typical data applies
at VCCA = VCCD = + 5.0V and TA = 25°C.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

NE5214
Min

los

Short-circuit TTL output
current

VTHRESH
VRPKDET

Typ

UNIT

SA5214
Max

Min

Typ

Max

VOUT= O.OV

-95

-95

mA

Threshold bias voltage

Pin 3 Open

0.75

0.75

V

RPKDET

Pin 11 Open

0.72

0.72

V

VRHYST

RHYST bias voltage

Pin 12 Open

0.72

0.72

V

VIHJ

High-level jam input voltage

VILJ

Low-level jam input voltage

2.0

V

2.0
0.6

0.8

V

30

pA

IIHJ

High-level jam input current

VIJ = 2.7V

IILJ

Low-level jam input current

VIJ = 0.4V

-450

-240

-485

-240

pA

VOHF

High-level flag output
voltage

10H = -60pA

2.4

3.6

2.4

3.8

V

VOlF

Low-level flag output voltage

10l = 3.2mA

0.33

0.4

0.33

0.4

V

10HF

High-level flag output
current

VOUT = 2.4V

-16

-5.3

-16

-5

mA

10lF

Low-level flag output current

VOUT = O.4V

3.6

10

3.25

10

ISCF

Short-circuit flag output
current

VOUT= O.OV

-60

-40

-25

-61

-40

-26

mA

IlEDH

LED ON maximum sink
current

VlED = 3.0V

13

22

60

6

22

60

mA

20

mA

AC ELECTRICAL CHARACTERISTICS Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. Typical data applies at
VCCA = VCCD = +5.0V and TA = 25°C.
LIMITS
SYMBOL

PARAMETER

NE5214

TEST CONDITIONS
Min

Typ

60

75

SA5214
Max

UNIT

Min

Typ

Max

60

75

MHz

fop

Maximum operating
frequency

Test circuit

BWA'

Small signal bandwidth
(differential OUT, liN,)

Test circuit

75

75

MHz

VINH

Maximum Functional A 1
input signal (single ended)

Test Circuit

1.6

1.6

Vp_p

VINl

Minimum Functional AI
input signal (single ended)

Test Circuit'

12

12

mVp_p

RIN'

Input resistance
(differential at IN,)

1200

1200

n

CIN'

Input capacitance
(differential at IN,)

2

2

pF

RIN2

Input resistance
(differential at IN2)

1200

1200

n

CIN2

Input capacitance
(differential at IN2)

2

2

pF

December 1988

5·142

Signetics Linear Products

Preliminary Specification

Postamplifier with Link Status Indicator

AC ELECTRICAL CHARACTERISTICS (Continued)

NEjSA5214

Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. Typical data applies
at VCCA = VCCD = +5.0V and TA ~ 25°C.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE5214
Min

Typ

SA5214
Max

Min

Typ

UNIT
Max

ROUTt

Output resistance
(differential at OUTt)

25

25

n

CoUTt

Output capacitance
(differential at OUT t )

2

2

pF

VHYS

Hysteresis voltage

VTHR

Threshold voltage range
(FLAG ON)

Test circuit

3

3

mVp.p

Test circUlt, @ 50MHz
RRHYST=5k RTHRESH = 47k

12

12

mVp.p

tTLH

TIL Output Rise Time
20% to 80%

Test CircUlt

1.3

1.3

ns

tTHL

TIL Output Fall Time
80% to 20%

Test Circuit

1.2

1.2

ns

tRFD

tTLH/tTHL mismatch

0.1

0.1

ns

tPWD

Pulse wld1h dlstortJon of
output

2.5

%

50mVp.p, 1010... Input
Distortion = 1
TH-h
1

1102

TH+h

2.5

1

NOTE:
t The NE/SA52t4 IS capable of detecllng a mueh lower Input level Operallon under t2mVp.p cannot be guaranteed by present day automate testers

Vce
+5V

NE5214
125

t LE-P-'-'-IN,.'20
2 c,.,.DET

+-_...4,..7K...._+---.::-I34 GTHRESH
5

~A
VeCA

18 10.1""

17

16 0.1"" 25

OUT'A 13

~~.....-:1~: GNPD
VOUT

c';
C

ou~:

o . l " " r V'N

19

IN •• : : " "

6 JAM

~~=+---'-I~ VOCD
O.1~F

IN

RINIA 12 5K
HTST 'I
RPKDET t---V"""'-1

10K

Figure 1. AC Test Circuit

December 1988

5-143

.".

50

•

Signetics Linear Products

Preliminary Specification

NE/SA5214

Postamplifier with Link Status Indicator

TYPICAL PERFORMANCE CHARACTERISTICS
Analog Supply Current vs Temperature
36

34

1/'"

. /~

V
'/
'I'
26

24

1/

~

V
,/

~

4~

~

VV

/'

12.0

,.,....

11.5

ICC I

........ -t::7oov

//'"
/

ICC I

........

~

Digital Supply Current vs Temperature

4~

/'"

/

/'"

-

-

--

r-- -....

-

26

~

•

~

~

11.0. .

~

-40

Y~
Yl~i

-20

20

40

eo

~

eo

120

TEMPERATURE rC)

l'EM'ERATURE rC)

Threshold Voltage vs

Yi=i~r-

-N

........

1/

~

r-.....

Hysteresis Voltage

RTHRESH

VB RHYST

22

21

~

RH'IST = 51(
20

111
!18
~

17

=
~

11
15

IE

"'"

'"

......... 1'-..

"'"

I~

14

.......

'"

13

30

40

"nt_(lcI'I)

December 1988

""

50

Antol.

'"~

'" ~
5
~(kCl)

5-144

"-

4711

"

0"""'"

Preliminary Specification

Signetics Linear Products

NE/SA5214

Postamplifier with Link Status Indicator

THEORY OF OPERATION AND
APPLICATION INFORMATION
The NE 5214 postamplifier system is a highly
integrated chip that provides up to SOdB of
gain at 60MHz, to bring mV level signals up to
TTL levels.
The NE5214 contains eight amplifier blocks
(see Block OIagram). The main signal path is
made up of a cascade of limiting stages: A1,
A2 and AB. The A3-A4-A7 path performs a
wideband full-wave rectification of the input
signal with adjustable hysteresis and decay
times. It outputs a TTL HIGH on the "FLAG"
output (Pin 5) when the input is below a user
adjustable threshold. An on-chip LED driver
turns the external LED to the ON state when

the input signal is above the threshold. In a
typical application the "FLAG" output is tied
back to the "JAM" input; this forces the TTL
data OUT into a LOW state when no signal IS
present at the input.
An auto zero loop allows the NE5214 to be
directly connected to a transimpedance amplHier such as the NE5210, NE5211, or
NE5212 without coupling capacitors. This
auto-zero loop cancels the transimpedance
amplifier's DC offset, the NE5214 A1 offset,
and the data-dependent offset in the PIN
diode/transimpedance amplifier combination.
For more information on the NE5214 Theory
of Operation, please refer to paper titled" A
Low Cost 100 MBaud Fiber-Optic Receiver"
by W. Mack et al.

A typical application of the NE5214 postamplifler is depicted in Figure 2. The system
uses the NE5211 transimpedance amplifier
which has a 2Bk differential translmpedance
gain and a -3dB bandWidth of 140MHz. This
typical application is optimized for a 50 Mb/s
Non Return to Zero (NRZ) bit stream.
As the system's gain bandWidth product is
very high, it IS crucial to employ good RF
design and printed circuit board layout techniques to prevent the system from becoming
unstable.
For more Information on thiS application,
please refer to AB 1432.

GND

G"!*

•

R4
5.1K

TC23504S

NOT£:
The NE5211/NE5214 combinabon can operate at data rates

In excess

of 100Mb/s NRZ

Figure 2. A 5OMb/. Fiber Optic Receiver

December 19BB

5-145

Signetics

NE/SA5217
Fiber OptiC Postamplifier with
Link Status Indicator
Objective Specification

Linear Products
DESCRIPTION
THE NE/SA5217 is a 75MHz postamplifler system designed to accept low level
high-speed signals. These signals are
converted into a TTL level at the output.
The NE5217 can be DC coupled with the
previous transimpedance stage using
NE5210, NE5211 or NE5212 transimpedance amplifiers. The main difference
between the NE5217 and the NE5214 is
that the NE5217 does not make the
output of A1 and input of A2 accessible,
instead, it brings out the output of A2
and the input of AS thus activating the
on-chip Schmidt trigger function by connecting two external capacitors. The
result is that a much longer string of l' s
and O's, in the bit stream, can be tolerated. This" system on a chip" features an
auto-zeroed first stage with noise shaping, a symmetrical limiting second stage,
and a matched rise/fall time TTL output
buffer. The system is user-configurable
to provide adjustable input thresholds
and hysteresis. The threshold capability
allows the user to maximize signal-tonoise ratio, insuring a low Bit Error Rate
(BER). An Auto-Zero loop can be used
to minimize the number of external coupling capacitors to one. A signal absent
flag indicates when signals are below
threshold. Additionally, the low signal
condition forces the overall TTL output
to a logical Low level. User interaction
with this "jamming" system is available.
The NE/SA5217 is packaged in a standard 20-pin surface-mount package and
typically consumes 42mA from a standard 5V supply. The NE/SA5217 is deSigned as a companion to the NEI
SA5211/5212 transimpedance amplifiers. These differential preamplifiers may

be directly coupled to the post-amplifier
inputs. The NE/SA5212/5217 or NEI
SA5211 15217 combinations convert nanoamps of photodetector current into
standard digital TTL levels.

DESCRIPTION

Plastic SOL

20-PIn Plastic SOL

December 1988

D1 Package
IN1B

IN1A

FEATURES

CAZO

• Postamp for the NE/SA5211/5212
preamplifier family
• Wideband operation: typical
75MHz (100MBaud NRZ)
• Interstage filtering/equalization
possible
• Single 5V supply
• Low signal flag
• Low signal output disable
• Link status threshold and
hysteresis programmable
• LED driver (normally ON with
above threshold signal)
• Fully differential for excellent
PSRR
• Auto-zero loop for DC offset
cancellation
• 2kV ElectroStatic Discharge (ESD)
protection

CAZM

OUT28
INes

OUT2A
INaA
R HYST

NOTE:
1 SOL - Released

~~

• RF limiter
• Good for 223.1 pseudo random
number sequence

TEMPERATURE RANGE

ORDER CODE

o to +70·C

NE5217D

-40·C to + 85·C

SA5217D

5-146

SYMBOL
LED

CPKDET

THRESH

GNDA
FLAG

• Fiber optiCS
• Communication links in Industrial
and/or Telecom environment with
high EMIIRFI
• Local Area Networks (LAN)
• Metropolitan Area Networks
(MAN)
• Synchronous Optical Networks
(SONEn

RpKDET

VOUT

APPLICATIONS

ORDERING INFORMATION
~ 20-Pin

PIN CONFIGURATION

JAM

VCCD
VCCA

9

10

GNDo
VOUT

11

RpKDET

In

large SO package only
DESCRIPTION

Output for the LED driver Open
collector output tranSistor with
12Sn senes limiting resistor An
above threshold Signal tums thiS
tranSistor ON
Capacitor for the peak detector
The value of thiS capacitor determines the detector response
time to the Signal, supplementing
the Internal 10pF capacitor
Peak detector threshold reSistor
The value of thiS reSistor determmes the threshold level of the
peak detector.
DeVice analog ground pin
Peak detector digital output
When thiS output IS LOW, there
IS data present above the
threshold ThiS pm IS normally
connected to the JAM pm and
has a fanout of two,
Input to Inhibit data flow Send·
Ing the pin HIGH forces TTL
DATA OUT ON, Pin 10, Low
ThiS pin IS normally connected
to the FLAG pin and IS TTL·
compatible
Power supply pm for the digital
portion of the chip
Power supply pm for the analog
portion of the chip
DeVice digital ground pin
TTL output pm With a fanout of
five
Peak detector current resistor
The value of thiS resistor determines the amount of discharge
current available to the peak detector capaCItor, CPKDET

Signetics linear Products

Objective Specification

Fiber Optic Postamplifier with
Link Status Indicator

NEjSA5217

PIN CONFIGURATION (cont.)
PIN
NO.

12

DESCRIPTION

SYMBOL
RHYST

Peak detector hysteresIs resistor

The value of this resistor
determines the amount of

13

INsA

hysteresIs In the peak detector
Non-Invertmg mput to amplifier

A8
14

OUT2A

15
16

1NaB
OUT2 B

17

CAZN

18

C AZP

19

IN1A

20

IN1B

Non-Inverting output of amphfler

A2
Invertmg mput to amplifier AS
Invertmg output of amplifier A2
Auto-Zero capacitor pin
(NegatIve termmal) The value of
this capacitor determines the
low-end frequency response of
the preamp A 1
Auto-Zero capacitor pin (PosItive
termmal) The value of this
capacitor determines the low-end
frequency response of the
preamp A1
Non-Inverting Input of the
preamp A1
Inverting Input of the preamp A 1

BLOCK DIAGRAM

IN1B

>----"'fO VOUT

IN1A
CUP

Ali

OUTPUT DISABLE

cu.

JAM

PEAK DETECT

>--------.......-10 FLAG

11
RpKDET

>-----'-110 LED

GND.

December 1966

liND.

THRESH

CPKDET

5-147

R HYST

•

Objective Specification

Signetics Linear Products

Fiber Optic Postamplifier with
link Status Indicator

NEjSA5217

ABSOLUTE MAXIMUM RATINGS
RATING
PARAMETER

SYMBOL

UNIT
NE5214

SA5214

VCCA

Power supply

+6

+6

V

VCCD

Power supply

+6

+6

V

TA

Operating ambient temperature range

o to +70

-40 to +85

·C

TJ

Operating junction temperature range -55 to + 150 -55 to + 150

TSTG

Storage temperature range

PD

Power dissipation

300

300

mW

V,J

Jam input voltage

-0.5 to 5.5

-0.5 to 5.5

V

-65 to +150 -65 to +150

·C
·C

RECOMMENDED OPERATING CONDITIONS
RATING
PARAMETER

SYMBOL

UNIT
NE5214

SA5214

VCCA

Supply voltage

4.75 to 5.25

4.75 to 5.25

VCCD

Power supply

4.75 to 5.25

4.75 to 5.25

V

TA

Ambient temperature range

+70

-40 to +85

·C

TJ

Operating junction temperature range

+95

-40 to +110

·C

PD

Power dissipation

250

mW

DC ELECTRICAL CHARACTERISTICS

o to
o to

250

V

Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. Typical data applies at
VCCA = VCCD = + 5.0V and TA = 25·C.
NE5214

PARAMETER

SYMBOL

SA5214

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

ICCA

Analog supply current

30

36

30

37.2

mA

ICCD

Digital supply current
(TTL, Flag, LED)

10

13.3

10

13.5

mA

V,l

A 1 input bias voltage
(+ /- inputs)

3.16

3.4

3.63

3.13

3.4

3.65

V

VOl

A1 output bias voltage (+ /- outputs)

3.17

3.8

4.45

3.10

3.8

4.50

V

AVl

A1 DC gain (without Auto-Zero)

A1pSRR

A1 PSRR (VCCA' VCCD)

A1cMRR

A1 CMRR

V,8

A8 input bias voltage (+ /- Inputs)

VOH
VOL
10H

30

30

dB

VCCA = VCCD = 4.75 to 5.25V

60

60

dB

Ll.VCM =200mV

60

60

dB

3.59

3.7

3.85

High-level TTL output voltage

10H = -2001lA

2.4

3.4

Low-level TTL output voltage

10L =8mA

0.3

0.4

0.3

0.4

V

High-level TTL output current

VOUT = 2.4V

-40

-26

-40

-24.4

IlA

10L

Low-level TTL output current

VOUT = O.4V

30

mA

los

Short-circuit TTL output current

VOUT = O.OV

-95

-95

mA

VTHRESH

Threshold bias voltage

Pin 3 Open

0.75

0.75

V

VRPKDET

RPKDET

Pin 11 Open

0.72

0.72

V

VRHYST

RHYST bias voltage

Pin 12 Open

0.72

0.72

V

V,HJ

High-level jam input voltage

V,W

Low-level jam input voltage

I'HJ

High-level jam input current

December 1988

8.0

3.7

5-148

V

2.4

3.4

7.0

30

2.0

V,J = 2.7V

3.86

V

V

2.0
0.8

0.8

V

20

30

IlA

Signetlcs Linear Products

Objective Specification

Fiber Optic Postamplifier with
Link Status Indicator

NEjSA5217

DC ELECTRICAL CHARACTERISTICS (Continued)

Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. TYPical data applies
at VCCA = VCCD = +5 OV and TA = 25°C
NE5214

SYMBOL

PARAMETER

SA5214

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

I'LJ

Low-level Jam Input current

V,J = O.4V

-450

-240

-485

-240

VOHF

High-level flag output voltage

IOH = -801lA

24

3.8

2.4

3.8

VOLF

Low-level flag output voltage

IOL =3.2mA

0.33

0.4

0.33

0.4

V

IOHF

High-level flag output current

VOUT = 2.4V

-18

-5.3

-18

-5

mA

IOLF

Low-level flag output current

VOUT = 04V

3.6

10

3.25

10

ISCF

Short-circuit flag output current

VOUT = OOV

-60

-40

-25

-61

-40

-26

mA

ILEDH

LED ON maximum sink current

VLED = 3.0V

13

22

80

8

22

80

mA

AC ELECTRICAL CHARACTERISTICS

V

mA

Min and Max limits apply over the operating temperature range at
VCCA = VCCD = + 5.0V unless otherwise specified. Typical data applies at
VCCA = VCCD = +5 OV and TA = 25°C
NE5214

SYMBOL

p.A

PARAMETER

SA5214

TEST CONDITIONS

UNIT
Min

Typ

60

75

Max

Min

Typ

Max

60

75

MHz

fop

Maximum operating frequency

Test CircUit

SWAI

Small signal bandwidth
(differential OUTI/IN,)

Test Circuit

75

75

MHz

V,NH

Maximum Funcllonal A 1
Input signal (single ended)

Test Circuit

1.6

16

Vp_p

V,NL

Maximum Funcllonal A 1
Input signal (single ended)

Test C,rcuit '

12

12

mVp_p

1200

1200

n

2

2

pF

R'NI

Input resistance (differential at IN,)

CINI

Input capacitance (differential at IN, )

R'N2

Input resistance (differential at IN2)

1200

1200

n

C'N2

Input capacitance (differential at IN 2)

2

2

pF

ROUTI

Output resistance (differential at
OUT, )

25

25

n

CoUTl

Output capacitance (differential at
OUT, )

2

2

pF

VHYS

HysteresIs voltage range

Test circuit, T A = 25°C

3

3

mVp_p

12

12

VTHR

Threshold voltage range (FLAG ON)

Test Circuit, @ 50MHz
RRHYST=5k RTHI'IESH = 47k

tTLH

TIL Output Rise Time 20% to 80%

Test circuit

1.3

1.3

ns

tTHL

TIL Output Fall Time 80% to 20%

Test circuit

12

1.2

ns

tRFD

tTLHItTHL mismatch

0.1

0.1

ns

2.5

%

Pulse width dlstorllon of output
tpwD

mVp_p

50mVp_p, 1010... Input
Distortion =

1

TH-TL

1

TH+h

1102
1

2.5

NOTE:

1 The NE/SA5217 IS capable of detecting a much lower Input level Operation under 12mVp_p cannot be guaranteed by present day automatic testers

December 1988

5-149

•

Objective Specification

Signetics Linear Products

Fiber Optic Postamplifier with
Link Status Indicator

NE/SA5217

Vee
+5V

NE52,7

:~;: ~:
C AZP

CAZN
OUT2B

I

~~ O.1pF

INeB~:

:::r":
.
50
25

':'

OUT2A 13
R1N8A 12

0.'#

5K

HYST 11
RpKDET

I-"--'V"O"'K~

400

Figure 1. AC Test Circuit

December 1988

5-150

-=

V,N

Signetics Linear Products

Objective Specification

Fiber Optic Postamplifier with
Link Status Indicator

NEjSA5217

TYPICAL PERFORMANCE CHARACTERISTICS
Analog Supply Current vs Temperature

Digital Supply Current vs Temperature

12.0

-

11.5

11.0

!

/

~ 10.5

;i 10.0

1/

9.5

20

40

60

80

100

9.0-60

120

-40

- t:bl

V

Vl4'T

-20

20

40

60

TEMPERATURE (OC)

TEMPERATURE rC)

December 1988

1/

v~~

/'

V

5-151

525~

1 1 r-

r--

/"

~
-20

t:::"

Vee =

a

-40

r-- r----

,/' V

1
!<

...8ll..

100

I'
120

•

Signetics Linear Products

Objective Specification

Fiber Optic Postamplifier with
Link Status Indicator
THEORY OF OPERATION AND
APPLICATION INFORMATION
The NE 5217 post amplifier system IS a highly
Integrated chip that provides up to 60dB of
gain at 60MHz, to bring mV level signals up to
TTL levels.
The NE5217 contains eight amplifier blocks
(see Block Diagram) The main signal path IS
made up of a cascade of limiting stages: AI,
A2 and A8. The A3-A4-A7 path performs a
wideband full-wave rectification of the Input
signal With adjustable hysteresIs and decay
times It outputs a TIL HIGH on the "FLAG"
output (Pin 5) when the input is below a user
adlustable threshold. An on-chip LED driver
turns the external LED to the ON state when

NEjSA5217

the input signal IS above the threshold. In a
tYPical application the" FLAG" output IS tied
back to the "JAM" Input, this forces the TTL
data OUT into a LOW state when no signal IS
present at the Input.
An auto zero loop allows the NE5217 to be
directly connected to a translmpedance amplifier such as the NE5210, NE5211, or
NE5212 Without coupling capacitors This
auto-zero loop cancels the translmpedance
amplifiers's DC offset, the NE5217 Al offset,
and the data-dependent offset in the PIN
diode/translmpedance amplifier combination.
For more Information on the NE5217 Theory
of Operation, please refer to paper titled "A
Low Cost 100 MBaud Fiber-Optic Receiver"
by W. Mack et al.

GND

G"!"~
R2

220

01
LED

$
z
L.3

C10
10J.LF

T

10,uH

_

C11
01 J.l F r---L.!!.J

-

NOTE:
The NE5210/NE5217 combination can operate at data rates In excess of 100Mb/s NRZ

Figure 2_ A 50Mb/s Fiber OptiC Receiver

December 1988

5-152

A typical application of the NE5217 post
amplifier IS depicted in Figure 2. The system
uses the NE5211 transimpedance amplifier
which has a 28k differential transimpedance
gain and a -3dB bandWidth of 140MHz. This
typical application is optimized for a 50 Mbl s
Non Return to Zero (NRZ) bit stream.
As the system's gain bandwidth product IS
very high, it IS crucial to employ good RF
deSign and printed circuit board layout techniques to prevent the system from becoming
unstable.
For more information on this application,
please refer to Application Brief AB 1432.

Signetics

Section 6
Telecommunications

Linear Products

INDEX
COMPANDORS
AN174
AN176
NE/570/S711
SA571
NE/SA572
AN 175
NES75

Applications for Compandors· NE570/571/SA571 ......
Compandor Cookbook... .. .
... .. . ... .

....

..

.. . ........... .
Compandor. ....... .. .... ......
Programmable Analog Compandor ..... ...................... . .... .
Automatic Level Control USing the NE572.... ............... ... ..
Low Voltage Compandor. .... .......... .... . ................... .

4-325
4-334
4-341
4-348
4-356
4-357

PHASE-LOCKED LOOPS
AN177
AN 178
NE/SE564
AN 179
AN180
AN1801
AN181
AN182
NE/SE565
AN183
AN184
NE/SES66
AN185
AN186
NE/SE567
AN187
AN188
TELEPHONY
NE5900
PCD3310/A
PCD3311112
PCD3315
PCD3341
PCD3343
PCD3360
PCD4415/A
TEA1060/61
TEA1067
AN1942
AN1943
TEA1068

An Overview of the Phase-Locked Loop (PLL) .... .
Modeling the PLL . ..... ....
....... .... .... .. ....... . ... .
... .... .. .
Phase-Locked Loop ... ........
..................... .. .
Circuit DescrlpllOn of the NE564
Frequency SynthesIs with the NE564. ... .. . ..
10.8MHz FSK Decoder With NE564 .....
.......... .
A 6MHz FSK Converter Design Example for the NE564 ..
Clock Regenerator With Crystal-Controlled Phase-Locked
VCO (NE564) .
.......... .
. ....... ...... ....
..
Phase-Locked Loop.. . ...
.. ...... ......... ..... ..
Circuit Description of the NE565 PLL .
.. ..... ............ ..
Typical Applications with NE565
.. .................
FuncllOn Generator .... .. . .
.. ... ..... ...................
Circuit DescrlpllOn of the NE566
. .. .... ........
Waveform Generators With the NE566 .. ....... ............. ....
Tone Decoder/Phase-Locked Loop .... .. .. . ..................
Circuit DescrlpllOn of the NE567 Tone Decoder.... ..... .... . ...
Selected CircUits USing the NE567.. ..... .... . ..................

4-222
4-227
4-243
4-252
4-259
4-263
4-266

Call Progress Decoder .... ..... . ............... ..... ........ ...... ...
Pulse and DTMF Dialer With Redlal......... ...... .......... .........
DTMF/Modem/Muslcal Tone Generator. .... ..... . .... ...... .......
CMOS Redial and Repertory Dialer. ... ......................... ..
CMOS Repertory Telephone Set Controller.. ...... ..... ...........
CMOS Microcontroller for Telephone Sets .............. ........ .......
Programmable Multi-Tone Telephone Ringer .... ..... ....... ......
Pulse and DTMF Dialer with Redial.. ..... .......... .............. ..
Versatile Telephone Transmission Circuits With Dialer Interface ....
Low Voltage Transmission IC with Dialer Interface ................
Application of the Low Voltage Versatile Transmission Circuit ......
Supply of Peripheral CircUits With the TEA 1067 Speech CirCUit ....
Versatile Telephone Transmission Circuit .................................

6-3
6-10
6-25
6-37
6-45
6-55
6-82
6-90
6-102
6-113
6-125
6-145
6-151

4-268
4-277
4-283
4-287
4-290
4-295
4-296
4-299
4-311
4-316

•

Signetics

NE5900
Call Progress Decoder
Product Specification

Linear Products

DESCRIPTION
The NE5900 call progress decoder
(CPO) is a low cost, low power CMOS
integrated circuit designed to interface
with a microprocessor-controlled smart
telephone capable of making preprogrammed telephone calls. The call progress decoder provides information to
permit microprocessor decisions whether to initiate, continue, or terminate calls.
A tri-state, 3-bit output code indicates
the presence of dial tone, audible ringback, busy signal, or reorder tones.
A front-end bandpass filter is accomplished with switched capacitors. The
bandshaped signal is detected and the
cadence is measured prior to output
decoding. In addition to the three data
bits, a buffered bandpass output and
envelope output are available. All logic
inputs and outputs can interface with
LSTIL, CMOS, and NMOS.
Circuit features include low power consumption and easy application. Few and

inexpensive external components are
required. A typical application requires a
3.58MHz crystal or clock, 470kn resistor, and two bypass capacitors. The
NE5900 is effective where traditional call
progress tones, PBX tones, and precision call progress tones must be correctly interpreted with a single circuit.

•
•
•
•
•
•

PBXs
Security equipment
Auto dialers
Answering machines
Remote diagnostics
Pay telephones

PIN CONFIGURATION

FEATURES
• Fully decoded tri-state call
progress status output
• Works with traditional, preCision,
or PBX call progress tones
• Low power consumption
• Low cost 3.58MHz crystal or
clock
• No calibration or adjustment
• Interfaces with LSTTL, CMOS,
NMOS
• Easy application

0 1 and N Packages
INPUT

1

COUNTIN
PROGRESS

TOP VIEW
NOTE:
1 SOL - Released In large SO package only

APPLICATIONS
• Modems

BLOCK DIAGRAM CPD
ANALDGOUT

OV

VREF

5V

TAl-STATE

ENABLE
INPUT
ENVELOPE

EXTCLDCK
IN/XTAL1

BIT 1

TIMING

BIT 2

XTAL2

BIT 3

TEST
IN

May 8, 1986

CLEAR
IN

6-3

COUNT IN
PROGRESS

DATA
VALID

853-0842 83667

•

Signetics linear Products

Product Specification

NE5900

Call Progress Decoder

ORDERING INFORMATION
DESCRIPTION

AMBIENT TEMPERATURE

o to
o to

16-Pin Plastic SOL
16-Pin Plastic DIP

ORDER CODE

+70°C

NE5900D

+70'C

NE5900N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNITS

9

V

VIN

Logic control input voltages

-0.3 to + 16

V

VIN

All other Input voltages 1

-0.3 to Vee
+0.3

V

VOUT

Output voltages

-0.3 to Vee
+0.3

V

TSTG

Storage temperature range

-65 to + 150

'C

TA

Operating temperature range

TSOLD

Lead soldenng temperature (10s)

+300

'C

TJ

Junction temperature

+150

'C

VDD

Power supply voltage

o to

+70

NOTE:
1 Includes Pin 3 - Ext Clock In

May 8, 1986

6-4

'C

Signetics Linear Products

Product Specification

NE5900

Call Progress Decoder

DC ELECTRICAL CHARACTERISTICS Unless otherwise stated, Voo = + 5.0V; Pin 3 fosc = 3.58MHz; Ambient
Temperature = 0 to + 70·C. Pin 5 = OV, Pin 14 = Voo.

LIMITS
SYMBOL

TEST CONDITONS

PARAMETER

UNIT
Min

Typ

Max

4.5

5.0

5.5

V

Power supply voltage

Pin 16
Pin 14 =Voo
Pins 5, 6 =OV

Quiescent current

As above with no output loads.

2.0

4.0

rnA

Input threshold

Pin 1 level, frequency = 460Hz,
Voc = VREF Output Pin 13 = Voo

-39

-35

dB I

Signal rejection

Pin 1 level, 300Hz frequency,
VOC=VREF Output Pin 13 = OV

-50

dBI

Low frequency2 rejection

Pin 1 frequency, OdB max.,
Voc = VREF Output Pin 13 = OV

180

Hz

High frequency2 rejection

Pin 1 frequency OdB max.,
Voc = VREF Output Pin 13 = OV

800

VIH

Logic 1 input voltage

Pins 6, 14

2.0

15

VIL

logic 0 input voltage

Pins 6, 14

0

0.8

V

IHL

Logic 1 input current

Pins 3, 6, 14 = Voo

-1.0

1.0

p.A

Voo

Hz
V

IlL

Logic 0 input current

Pins 3, 6, 14 = OV

-1.0

1.0

p.A

VIH

Logic 1 input voltage

Pin 3 External Clock In/XTAL

Voo-l

Voo

V

VIL

Logic 0 Input voltage

Pin 3 External Clock In/XTAL

0

1.0

V

VOL

Logic 0 output voltage

ISINK = 1.6mA
Pins 7, 9, 10, 11, 12, 13

0

0.4

V

VOH

Logic 1 output voltage

ISOURcE = 0.5mA
Pins 7, 9, 10, 11, 12, 13

Voo

V

loz

Tri-state leakage

VOUT = Voo or OV
Pins 10, 11, 12, 13
Pin 14 = OV

3.0

p.A

Filter output gain

Input Pin 1, 460Hz - 20dB,
Voc = VREF Output Pin 15,
RLOAO= lMn

10.5

dB

Filter frequency response

As above from 300Hz to 630Hz,
referenced to 460Hz

1.0

dBmo

Input impedance2

Pin 1, frequency = 460Hz

VREF

Reference voltage

Pin 2, Voo = 5V

RREF

Reference resistance

Pin 2

Envelope response time

Time from removal or application
of 460Hz - 20dB (Voc = VREF on
Pin 1) to response of Pin 13

NOTES:
1. OdB = O.775VRMS.
2 By d9Slgn; not lested.

May 8, 1986

6-5

Voo-0.4

-3.0

6.5

8.5

-1.0
1
2.4

Mn
2.5

2.6

V

5

n

38

ms

•

Signetics Linear Products

Product Specification

Call Progress Decoder

The NE5900 uses the signal in the call
progress tone passband and the cadence or
interrupt rate of the signal to determine which
call progress tone is present.
Figure 1 shows a detailed block diagram of
the NE5900.
The signal Input from the phone line IS
coupled through a 470k!2 resistor WhiCh,
together with two internal capacitors and an
Internal reSistor, form an anti-aliaSing filter.
ThiS passive low pass filter strongly rejects
AM radiO Interlerence. Insertion loss IS typically 1.SdB at 460Hz. The 470k!2 resistor
also provides protection from line transients
The input (Pin 1) DC voltage can be derived
from VREF (Pin 2) or allowed to self-bias
through a series coupling capacitor (10nF
minimum).
Following thiS is a SWitched capacitor bandpass filter which accepts call progress tones
and inhibits tones not In the call progress
band of 300Hz to 630Hz. The bandpass IlrTuts
are determined by the Input clock frequency
of 3.S8MHz. An on-board inverter between
Pins 3 and 4 can be used erther as a crystal
OSCillator or as a buffer for an external
3.S8MHz clock signal. The SWitched capacitor
filters provide typical rejection of greater than
40dB for frequencies below 120Hz and above
1.6kHz.

NE5900

The decoder responds to Signals between
300Hz and 630Hz With a threshold of -39dB
typical (OdB = O.77SVRMsl. The decoder Will
not respond to any Signals below -SOdB or to
tones up to OdB which are below 180Hz or
above 800Hz. Dropouts of 20ms or bursts of
only 20ms duration are Ignored. A gap of
40ms or a valid tone of 40ms IS detected.
The buffered output of the SWitched capacitor
filter is available at the analog output, Pin 1S
A logic output representing the detected envelope of thiS Signal is available at the envelope output, Pin 13.
At the start of an In-band tone (envelope
output goes high), a 2.3-second Interval IS
timed out. TranSitions of the envelope dUring
thiS interval are counted to determine the
Signal present. At 2.3 seconds, the three bits
of data represenllng thiS deCISion are stored
In the latch and appear at the outputs. A data
valid Signal goes high at thiS time, Signaling
that the data bits, Pins 10- 12, can be read.
The output code IS as follows:
PIN 12 PIN 11 PIN 10
DIAL TONE
RINGING SIGNAL
BUSY SIGNAL
REORDER TONE
OVERFLOW

o
1

o
o

o
o
1

o

o

o

o
1

The overllow condition occurs In the event
that too many transitions occur during the
2.3-second Interval. ThiS can result from
nOise, VOice, or other line disturbances not
normally present dUring the post-dialing interval Note that the end of dial tone IS Interpreted as a valid ringing Signal
The clear Input resets all Internal registers
and the output latch, and IS to be set low after
the completion of dialing. The clear Input
should be pulsed high for proper operation.
Recommended pulse Width IS between 0.2/15
and 20ms. If clear IS held high when envelope
IS high, a false output pulse (Pin 13) can result
when clear IS returned low.
For applications where dialing IS done by a
person rather than by a microprocessor, an
uncertainty eXists about the number of digits
to be dialed (local vs long distance). In such
SItuations It is pOSSible to clear the NES900
by application of the DTMF Signal or dial
pulses to the clear pin (Pin 6) When dialing IS
complete, the deVice IS cleared and ready to
respond to the next call progress Unit
Enable IS held at SV to enable PinS 10, 11, 12,
and 13 When enable IS brought low, data
valid is also set low. Enable must remain high
while the data IS being read. The test pin IS for
production test only and must be kept low In
all user applications

ANALDG
OUT

INPUT

SV
R.

EXT CLOCK
INIXTAL1

10k

XTAL2

VREF

OV

TRI·STATE
ENABLE
ENVELOPE
COUNT IN
PROGRESS .......-"~~--'

2.3-SECOND
TIMER

DECODER
LATCHES

OATA VALID

BIT 1
BIT 2

BIT 3

Figure 1. Detailed Block Diagram CPO

May 8, 1986

6-6

Signetics Linear Products

Product Specification

Call Progress Decoder

Figure 2 shows a typical application of the call
progress decoder.
In this application only one external component is needed and no microprocessor activity other than clear is reqUIred.

NE5900

Figure 3 shows the recommended direct
interface to the telephone line. Bus connection IS possible by utilizing tn-state, and internal timing is accomplished with a 3.58MHz
crystal.

TO EAR·PIECE

I

3.5SMHz IN

-i
~
10nF470k

5V

15

,.

L.><>--------1

__
•

1

~

16 t--""1>-<:><

L.><>-___.1O...:...,K_O_--1

13t----C

ENVELOPE

12t----C

BIT 1

NE5900

5

2

10nF:r

The designer can utilize the input signal,
clock, bus, or microprocessor Interface which
best serves the applicallon. Figure 4 gives a
typical timing diagram for the appllcallon of
Figures 2 and 3.

t----<:t...->

:

11

I

10t----

INTERRUPT

STAAT

'-------------coo-I
10nF

IN2

C2

C>o-I

10nF

R5
R1

16

5V

470kQ

15

WOk

R2

,.

ENABLE

•

13

ENVELOPE

5

'2

NE5900

100k

100k
R3

11

100k

} DECODED
OUTPUTS TO
PROCESSOR

10
INTERRUPT

STAAT
CLEAR

Figure 3. Typical Two·Wire Application

May 8, 1986

6·7

•

Signetics Linear Products

Product Specification

NE5900

Call Progress Decoder

INPUT

CLEAR

ENVELOPE

---------+'1
!---2.27 SECONDS-l

,----.

DATA VALID

BIT 1

BIT 2

BIT 3

Ums TYPICAL

u

COUNTIN~

PROGRESS

Figure 4

May 8, 1986

6·8

u

Signetics Linear Products

Product Specification

Call Progress Decoder

NE5900

TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current vs VDD

5

3.0

Ii

I

i..

ifi
II:

2.5

2.0

./

1.5

II:
:::I

(,)

?:i

A.
A.
:::I

.,

1.0

V-

~

z

V

/

~

V

!i!

..

5A.

4

0

3.S

4.5
SUPPLY VOIrAGE(VDD)(PIN 16)

5.5

 " key IS
activated. Then the circuit changes over to
DTMF dialing and remains there until FL is
activated or, after a static standby condition,
CE IS re-actlvated.
A connection between PD/DTMF pin and
Voo also Initiates DTMF dialing. Chip enable,
FL, or a connection of PD/DTMF pin to Vss
sets the circuit back to pulse dialing.

Keyboard Inputs/Outputs

PO Mode
If PD/DTMF = Vss, the pulse mode is selected. Entries of non-numeric keys are neglected; they are not stored In the redial register
nor transmitted.
DTMF mode
if PD/DTMF = Voo, the dual tone multi-frequency dialing mode is selected. Each nonfunction pushbutton activated corresponds to
a combination of two tones, each one out of
four possible LOW and HIGH group frequencies. The frequencies are transmitted with a
constant amplitude, regardless of power supply variations, and filtered off harmonic content to fulfill the CEPT CS 203 recommendations.

The sense column inputs COL 1 to COL 4
and the scanning row outputs ROW 1 to
ROW 5 of the PCD3310 are directly connected to the keyboard as shown In Figure 2.
All keyboard entries are debounced on both
the leading and trailing edges for approximately time tE as shown in Figure 7. Each
entry IS tested for validity.
When a pushbutton IS pressed, keyboard
scanning starts and only returns to the sense
mode after release of the pushbutton.
Row 5 of the keyboard contains the following
speCial function keys:
• P
memory clear and programming
(notepad)
• FL
flash or register recall

R

FLO
NOTE:

Where tFLRG;:::: RC

a.

b.

Figure 1. Flash Pulse Duration Setting
May 5, 1988

6-15

•

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD3310jA

Table 1. Frequency Tolerance of the Output Tones for DTMF
Signaling
ROWI
COLUMN
Row
Row
Row
Row
Col
Col
Col
Col

FREQUENCY DEVIATION

STANDARD
FREQUENCY Hz

TONE OUTPUT
FREQUENCY Hz 1

697
770
852
941

697.90
770.46
850.45
943.23

+0.13
+0.06
-0.18
+0.24

+0.90
+0.46
-1.55
+2.23

1209
1336
1477
1633

1206.45
1341.66
1482.21
1638.24

-0.21
+0.42
+0.35
+0.32

-2.55
+5.66
+521
+5.25

1
2
3
4

1
2
3
4

%

Hz

redial procedure with the "Flash" Inserted
telephone number). The counter of the reset
delay time is held dUring the penod of tFL'

COWMNS

I I I l
'----

1

2

3

A

4

5

6

B

7

8

9

C

*

0

"

D

FL

R

>

P

KEYBOARD

Figure 2. Keyboard Organization
• R

• >

redial
change of dial mode from PD to
DTMF in mixed dialing mode

In pulse dialing mode, the valid keys are the
10 numeric pushbuttons (0 to 9). The nonnumeric keys (A, B, C, D, " #) have no effect
on the dialing or the redial storage. Valid
function keys are P, FL and R.
In DTMF mode all non-function keys are valid.
They are transmitted as a dual tone combination and at the same time stored in the redial
register. Valid function keys are P, FL and R.
In mixed mode all key entries are valid and
executed accordingly.

Flash Duration Control (FLD)
Flash (or register recall) is activated by the FL
key and can be used in DTMF and pulse
dialing mode. Pressing the FL pushbutton will
produce a timed line-break of 100ms (min.) at
the DP/FLO output. During the conversation
mode this flash pulse entry will act as a chip
enable. This flash pulse duration (tFLl is
calibrated and can be prolonged with an
external resistor and capacitor connected to
the FLD input/output (see Figure 1).
The flash pulse resets the read address
counter (RAC). Later redial is possible (see
May 5, 1988

Inverted output of M1. In the PCD3310P it is
only available as a bonding option of M1.

Strobe Output (M2)
Active HIGH output dUring actual dialing; i.e.,
during break or make time in pulse dialing, or
during tone ON/OFF in DTMF dialing. Available only in 28-pln surface mount device.

Confidence Tone Output (CF)
When any of the keys are activated, a square
wave is generated and appears at thiS output
to serve as an acoustic feedback for the user.

DIALING PROCEDURES
Dialing

NOTE:
1. Tone outpul frequency when uSing a 3 579545MHz cryslal

ROWS

Mute Output (M1)

TONE OUTPUT (DTMF mode)
The Single and dual tones Which are provided
at the TONE output are filtered by an on-chip
switched-capacitor filter, followed by an onchip active RC low-pass filter.
Therefore, the total harmOniC distortion of the
DTMF tones fulfills the CEPT CS 203 recommendations. An on-chip reference voltage
provides output-tone levels independent of
the supply voltage. Table 1 shows the frequency tolerance of the output tones for
DTMF Signaling.
When the DTMF mode is selected, output
tones are timed in manual dialing With a
minimum duration of bursts and pauses, and
in redial With a calibrated timing. Single tones
may be generated for test purposes
(CE = HIGH). Each row and column has one
corresponding frequency. High group frequencies are generated by connecting the
column to Vss. Low group frequencies are
generated by forcing the row to VDD' The
single-tone frequency will be transmitted during activation time, but it is neither calibrated
nor stored.

Dial Pulse and Flash Output
(DP/FLO)
ThiS is a combined output which prOVides
control signals for proper timing in pulse
dialing or for a calibrated break in both dialing
modes (flash or register recall).

Mute Output (M1)
During pulse dialing the mute output becomes
active HIGH for the period of the inter-digit
pause, break time and make time. It remains
at this level until the last digit is pulsed out.
During DTMF dialing the mute output becomes active HIGH for the period of tone
transmission and remains at this level until
the end of hold-over time. It is also active
HIGH during flash and flash hold-over time.

6-16

After CE has risen to VDD, the oscillator starts
running and the Read Address Counter (RAC)
is set to the first address (Figure 3). By
entering the first valid digit, the Temporary
Write Address Counter (TWAC) will be set to
the first address, the decoded digit will be
stored in the register and the TWAC Incremented to the next address. Any subsequent
keyboard entry will be decoded and stored in
the redial register after validation. The first 5
valid entries have no effect on the main
register and its associated write address
counter. After the sixth valid digit IS entered,
TWAC indicates an overflow condition. The
data from the temporary register will be
copied Into the 5 least Significant places of
the main register and TWAC into the WAC. All
following digits (including the Sixth digit) will
be stored in the main register (a total of not
more than 23). If more than 23 digits are
entered, redial will be inhibited. If not more
than 5 digits are entered, only the temporary
register and the assOCiated TWAC are affected. All entries are debounced on both the
leading and trailing edges for at least time tE
as shown in Figure 7. Each entry is tested for
validity before being deposited in the redial
register.
• In DTMF mode all non-function keys
are valid
• In PD mode only numeric keys are valid
Simultaneous to their acceptance and corresponding to the selected mode (PD, DTMF,
or mixed), the entries are transmitted as PD
pulse trains or as DTMF frequencies in acoordance with postal requirements. Non-numeric
entries are neglected during pulse dialing;
they are neither stored nor transmitted.

Redialing
After CE has risen to VDD, the oscillator starts
running and the Read Address Counter (RAC)
is set to the first address to be sent. The
PCD3310 is In the conversation mode.
If "R" is the first keyboard entry, the circuit
starts redialing the contents of the temporary
register. If the overflow flag of the TWAC was

Signetics Unear Products

Product Specification

Pulse and DTMF Dialer with Redial

set in the previous dialing, the rediahng continues in the main register. If the flag was not
set, the number residing in the temporary
register will only be redialed until the temporary read and write registers are equal.
Before pressing "R," a dialing sequence with
up to 4 digits is possible. If the digits are equal
to the corresponding ones in the main register, then redial starts in the main register until
the last digit stored is transmitted.
Timing in the DTMF mode is calibrated for
both tone bursts and pauses.

PCD3310jA

In mixed mode, only the first part entered (the
pulse dialed part of the stored number) can
be redlaled.
During redial, keyboard entnes (function or
non-function) are not accepted until the cirCUit returns to the conversation mode after
completion of redlaling.
No redial activity takes place If one of the
follOWing events occurs:
• Power on reset
• Memory clear ("P" without successive
data entry)
• Memory overflow (more than 23 vahd
data entries)

ADDRESSED THROUGH
POINTERS w OR R

Notepad
The redial register can also be used as a
notepad. In conversauon mode, a number
with up to 23 digits can be entered and stored
for redlahng. By activating the program key
(P) the WAC and TWAC pOinters are reset.
ThiS acts hke a memory clear (redial IS
Inhibited) Afterwards, by entenng and storing
any digits, rediahng will be possible after flash
or hook on and off.
DUring notepad programming, the numbers
entered will neither be transmitted nor IS the
mute active; only the confidence tone is
generated.

6

4

ADDRESSED THROUGH
TEMPORARY POINTERS WOR R

MAIN

WRITE ADDRESS COUNTER (WAC)

READ ADDRESS COUNTER (RAC)

REGISTER

TEMPORARY REGISTER

I

TEMPORARY WRITE ADDRESS

COUNTER (TWAC)

L._ _ _ _ _ _- - '

TEMPORARY ADDRESS COUNTER

:==============:
ADDRESS COUNTER
Figure 3, Program Memory Map

May 5, 1988

I

6·17

•

Product Specification

Signetics Linear Products

Pulse and DTMF Dialer with Redial

PCD3310/A

PUBLIC EXCHANGE

DIAL

•

..

CONVERSATION
MODE

STANDBY
MODE

-

PULSE OR
TONE OUT

Figure 4a, Public Exchange PD/DTMF Mode

May 5, 1988

6-18

Signetics Linear Products

Product Specifrcotion

Pulse and DTMF Dialer with Redial

PCD3310jA

_. -_. -----I

PABX

, - - - - - IF INTERNAL NUMBER" 5 DIGITS - - - - .
DIAL EXTERNAL NUMBER

REDIAL EXTERNAL NUMBER (1)

DIAL INTERNAL NUMBER

REDIAL INTERNAL NUMBER

II
NOTE:
1 If [access dIQlt(S) + external numberJ";;; 23 digits

Figure 4b. PABX PD/DTMF Mode
~-------------------------------------------------------------------------------

May 5, 1988

6-19

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD3310/A

DIAL

. . --'1===~PULSE DlAUNG

SET IN PULSE DlAUNG

PULSE OUT

z---i-----

AUTOMATIC SWITCH TO OTUF OR MANUAL BY ~

DTUFDlAUNG

TONE-OUT

REDIAL

PULSE DlAUNG

462 75 30
FTOTAL

(PO + DTMI')

PULSE OUT

.. 23 DIGITS

Figure 5. PD/DTMF Mixed-Mode Dialing

May 5, 1988

6-20

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD3310jA

NOTE PAD PROGRAM

NO DIALING-NO MUllNG

MEMORY CLEAR

FLASH

•

NO
REDIALING

REDIAL
(SEE PABX PROCEDURE)

Figure 6. Notepad/Memory Clear, Flash; Independent of Dialing Mode

May 5, 1988

6-21

Signetics Unear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD3310/A

~IRD--l
---U--(NO EFFECT)
KEYBOARO
ENTRY

_+__-'

Ml

M2

DPIFLO

~-,--~'---------------mAUNGMOOE-----------------+'-----~.~~--

CONVERSAllON
MOOE

STATIC
STANOBY
MODE

~------------------------------Figure 7a. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing (PD/DTMF = Vss)

KEYBOARD

ENTRV _ _ _

~

Ml

M2

_----;1

M

1;...-._---.

,;...-.-+----1_ _ _ __

WNN

DPIFLO

Figure 7b. TIming Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; DTMF Dialing (PD/DTMF

May 5. 1988

6-22

=VDD)

Signetics linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD3310/A

I

KEYBOARD
ENTRY _ _ _ _ _.....

~

"

DP/FLO

DTMF

M1

M2

PD/DTMF

--1---....

PULSE DIALING ..........

DTMF DIALING

Figure 7c. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing (Mixed Mode)

CE

KEY~::~
M1

~

I

-!fl..__-!f7l

____

',-11- .,-I!- -l~----l~

R

r-"

-------!

DIAL TONE

DTMF

Figure 8. Timing Diagram Showing REDIAL Where PABX Access Digits are the First Keyboard Entries;
DTMF Dialing with PD/DTMF = VDD

50
pF

10k

Figure 9. Tone Output Test Circuit

May 5, 1988

6-23

•

Product Specification

Signetics Linear Products

PCD3310jA

Pulse and DTMF Dialer with Redial

,...{}..,

+. . . . . +
r!)...;' _

aYIMTlICAL LOW-M'EI)ANCE INPUTS FOR
DYNAIIC

AM)

IlAGI£TIC 1llCA00HOt£& (TEA1010)

ABYlMlRICAL tlGl+lFEDANCE IN'UTS FOR

+ '-' +

ELECTRET IKftOPMOIrE8 (lEA,.,)

rlcl4~

L

81:

r-.::=,-f---,

2.2J#"
lOY

~DlAL

10nF
1%

AS
Uk

BAV10

H~>-+--j--=C£=-t18
R14

COl. 4

BAS11

(2)

TONE 3

, . 150ftF
17
AGe

16

15
Vee

14

AlB

UN.

2 3 A

5 6 8

7
1I)O}lF 2.2nF
lOY

c.

P FL R :>
PCD3311

410k

410k

DP
FLO 16
Vss 4

4700

10M

NOTES:
1 Automatic hne compenstlOn obtamed by connecting A6 to Vss
2 The value of reSistor R14 IS determmed by the required level at LN and the OTMF gam of the TEA 1060

Figure 10. Application Diagram of the Full Electronic Basic Telephone Set

6-24

8 9 C

•• 0
100nF

~A-~--+--~

May 5, 1988

1

4

I'DIDTMF
SELECTPW

Signetics

PCD3311/12
DTMF/Modem/Musical Tone
Generators
Product Specification

Linear Products
DESCRIPTION

FEATURES

The PCD3311 and PCD3312 are singlechip silicon gate CMOS integrated circuits. They are intended to provide dualtone multi-frequency (DTMF) combinations required for tone dialing systems in
telephone sets which contain a microcontroller for the control functions.

• Stabilized output voltage level
• Low output distortion with onchip filtering (CEPT CS203
compatible)
• Latched inputs for data bus
applications
• 12C bus compatible
• Mode select input (selection of
parallel or serial data input)
• MODEM and melody tone
generators

The various audio output frequencies
are generated from an on-chip 3.58MHz
quartz crystal-controlled oscillator.
The devices can interface directly to all
standard microcontrollers by accepting a
binary-coded parallel input or serial data
input (l2C bus).
With their on-chip voltage reference the
PCD3311 and PCD3312 provide constant output amplitudes which are independent of the operating supply voltage
and ambient temperature.

PIN CONFIGURATIONS

N Package

TOP VIEW

D. N Packages

APPLICATION
• Microcontrolled telephone sets

An on-chip filtering system assures a
very low total harmonic distortion in
accordance with the CEPT CS203 recommendations.

TOP VIEW

D Package

In addition to the standard DTMF frequencies. the devices provide 12 MODEM frequencies (300 to 1200 bits per
second) used in simplex MODEM applications and two octaves of musical
scale in steps of semitones.

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

14-Pin Plastic DIP (SOT-27k. M. T)

DESCRIPTION

-25'C to + 70'C

PCD3311PN

16-Pin Plastic SO (SO-16L; SOT-162A)

-25'C to + 70'C

PCD3311TD

8-Pin PlastiC DIP (SOT-97A)

-25'C to + 70'C

PCD3312PN

8-Pin Plastic SO (SO-8L; SOT-176)

-25'C to + 70'C

PCD3312TD

July 15. 1988

6-25

853-1033 93869

•

Signetics Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

PCD3311/12

BLOCK DIAGRAM
ascI

osco

1

•

I
MODE
0,
0,

4
(14)

11

(12)

10

(11)

9

(10)

8

(9)

03
0,
°1 /SDA

--t

+

-Xl

I 'HIGH GROUP'

INPUT

,.-

CONTROL
LOGIC

-

5

(6)

t

I

SWITCHED-

-X2

+

VOLTAGE

I

I
I

I

,

ADD~

SWITCHED-

I

CAPACITOR

I

l~~:::S

:

t

TONE GENERATOR
'LOW GROUP'

parentheses refer to the PCD3311TD, Pins 5 and 13 are NC

LIMITS
PARAMETER

UNIT
Min

Max

VDD

Supply voltage range

-0.8

+8.0

V,

Input voltage range (any Input)

-0.8

VDD + 0.8

V

±I,

DC Input current (any input)

10

mA
mA

V

±Io

DC output current (any output)

10

±IDD; ±Iss

Supply current

50

mA

Po

Power diSSipation per output

50

mW

PTOT

Total power diSSipation per package

300

mW

TA

Operating ambient temperature range

-25

+70

°C

TSTG

Storage temperature range

-65

+150

°C

July 15, 1988

RESISTORI

FILTER

PCD3311
PCD3312

ABSOLUTE MAXIMUM RATINGS
SYMBOL

13(15)

~~:~:~:

E]-.l

I

NOTE:
In

I

I

I

7(8)

The pin numbers

f

I

I

I

REFERENCE

!

~C

f...-J

C::~;:J~pR

I
I
I

I

DIVIDER

-I

:

I

SELECTION
(ROM)

Do /SCL

STROBE

I
I TONE GENERATOR I

1

tl :

Vss

114(lS)

-r----T--'

CLOCK
GENERATOR

OSCILLATOR

3

,.

Voo

6-26

1---1f-S.;.(7-o) TONE

Signetics Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

DC AND AC ELECTRICAL CHARACTERISTICS

SYMBOL

PCD3311/12

voo = 2.5 to 6V; Vss - OV; crystal parameters: losc = 3.579 545MHz,
RSMAX = son; TA = -25'C to + 70'C, unless otherwise specified.

LIMITS

PARAMETER

Min

TyP

2.5

Voo

Operating supply voltage

100
100
100

Operating supply current1 OSCillator ON; Voo = 3V
no output tone
single output tone
dual output tone

1000

Static standby current 1
oscillator OFF

50
0.5
0.6

Max

UNIT

6.0

V

100
1.0
1.2

IlA
mA
mA

3

IlA

Inputs/outputs (SOA)
Do to 05; MODE; STROBE
V,l

Input voltage lOW

V,H

Input voltage HIGH

0
0.7

O2 to 05; MODE; STROBE;
Pull-down input current, V,

-I,l

x

0.3 X Voo
Voo

V

Voo

V

300

nA

100

kHz

Ao

= Voo

30

150

SCl (00); SOA (0 1)
IOl

Output current lOW (SOA), VOL = O.4V

ISCl

Clock frequency (see Figure 7)

CI

Input capacitance; VI = Vss

tl

Allowable Input spike pulse width

TONE

3

mA

7

pF

100

ns

205
160

mV
mV

output (See Figure 11)

VHG(RMS)
VlG(RMS)

OTMF output voltage levels (RMS values)
HIGH group
lOW group

158
125

192
150

Voc

DC voltage level

AVG

Pre-emphasIs of group

THO
THO

Total harmOniC distortion, TA = 25'C
dual tone2
modem tone3

-25
-29

IZol

Output Impedance

0.1

V

1,12 Voo
1.85

2.10

2.35

dB
dB
dB

0.5

kn

Voo-Vss

V

OSCllnput
VOSC(P-P)
Timing (Voo

Maximum allowable amplitude at OSCI

= 3V)
3

ms

0.5

ms

IosC(ON)

OSCillator start-up time

tTONE(ON)

TONE start-up time 4

IsrR

STROBE pulse widthS

400

ns

los

Data setup timeS

150

ns

IoH

Data hold timeS

100

ns

NOTES:
1 Crys1al IS connected between ascI and OSCO; Do/SCl and O,/SDA Via a resls1ance of 5.6kn to Voo; all other pins left open.
2. Related to the level of the LOW group frequency component (CEPT CS203).
3. Related to the level of the fundamental frequency.
4. OSCillator must be running
5. Values are referenced to the 10% and 90% levels of the relevant pulse amplitudes, With a total voltage SWIng from Vss to Veo.

July 15, 1988

6-27

•

Signetlcs Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

FUNCTIONAL DESCRIPTION
Clock/Oscillator (OSCI and
OSCO)
The tlmebase for the PCD3311 and PCD3312
IS a crystal-contrOlled oscillator with a
3_58MHz quartz crystal connected between
OSCI and OSCO_ AlternatIvely, the OSCI
Input can be driven from an external clock.

Mode Select (MODE)
This Input selects the data input mode. When
connected to VDD, data can be received In
the parallel mode (only for the PCD3311), or,
when connected to Vss or left open, data can
be receIved vIa the senal 12C bus (for both
PCD3311 and PCD3312).
Parallel mode can only be obtained for the
PCD3311 by setting MODE Input HIGH.

Data Inputs (Do. 01. 02. 03. 04
and 05)
Inputs Do and Dl have no Internal pull-down
or pull-up resIstors and must not be left open
In any application. Inputs D2 to D5 have
internal pull-down. D5 and D4 are used to
select between DTMF dual, DTMF SIngle,
MODEM and melody tones (see Table 1). D3
to Do select the combInatIon of the tones for
DTMF or SIngle-tone itself.

Strobe Input (STROBE. only for
the PC03311)
ThIS Input (WIth Internal pull-down) allows the
loading of parallel data Into Do to D5 when
MODE IS HIGH.
The data Inputs must be stable precedIng the
posItIve-going edge of the strobe pulse (active HIG H). Input data are loaded at the
negatIve-goIng edge of the strobe pulse and
then the correspondIng tone (or standby

July 15, 1988

PCD3311/12

Table 1. 05 and 04 in Accordance With the Selected Application
05

04

0
0
1
1

0
1
0
1

APPLICATION
DTMF songle tones; standby; melody tones
DTMF dual tones (all 16 combInatIons)
MODEM tones; standby; melody tones
Melody tones

NOTES:

1 = H = HIGH voltage level
o = L = LOW voltage level

mode) is provIded at the TONE output. The
output remaIns unchanged untIl the negatlvegOIng edge of the next STROBE pulse (for
new data) IS receIved.
Senal mode can only be obtaIned for the
PCD3311 by settIng MODE Input lOW.

Serial Clock and Data Inputs
(SCL and SOA)
SCl and SDA are combIned WIth Do and Dl,
respectIvely. For the PCD3311, the selectIon
of SCl and SDA IS controlled by the MODE
Input. SCl and SDA are senal clock and data
lines accordIng to the 12C bus specIficatIon
(see CHARACTERISTICS OF THE 12C BUS).
Both Inputs must be pulled-up externally to
VDD·

Address Input (Ao)
Ao IS the slave address Input and It IdentIfIes
the device when up to two PCD3311 or
PCD3312 devices are connected to the same
12C bus. In any case, Ao must be connected
to VDD or Vss.

12C Bus Data Configuration (see
Figure 2)
The PCD3311 and PCD3312 are always slave
receIvers In the 12C bus confIguratIon (R/Vii
blt=O)

6-28

The slave address consIsts of 7 bIts In the
senal mode for the PCD3311 as well as for
the PCD3312, where the least SIgnIficant bIt is
selectable by hardware on Input Ao and the
other more SIgnIfIcant bIts are Internally fIxed.
In the senal mode the same Input codes are
used as In the parallel mode (see Tables 2, 3,
4, and 5). D6 and D7 are don't care (X) bIts.

Tone Output (TONE)
The SIngle and the dual tones whIch are
provided at the TONE output are filtered by
an on-chip SWItched-capacitor folter, followed
by an actIve RC low-pass filter. Therefore, the
total harmonIc dIstortIon of the DTMF tones
fulfils the CEPT CS203 recommendations. An
on-chIp reference voltage proVIdes outputtone levels Independent of the supply voltage. Table 3 shows the frequency tolerance
of the output tones for DTMF SIgnalling;
Tables 4 and 5 for the modem and melody
tones.

Power-On Reset
In order to avoid undefined states of the
deVIces when the power IS switched ON, an
Internal reset cIrcuIt sets them to the standby
mode (OSCIllator OFF)

Signetics Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

PCD3311/12

STROSE-~";';;~

0,

03

0,

r

tTONE

---+-- - ---" - - . .

TONE

OSCILLATOR OFF

OSCILLATOR ON
NO OUTPUT TONE

I

OSCILLATOR ON
OUTPUT TONES

Figure 1. Timing Disgram Showing Control Possibilities of the Oscillator and the TONE Output (e.g., 770Hz
in the Parallel Mode (MODE = HIGH)

ACKNOWLEDGE
F~OMISLAVE
MSS

Is I

R/W

t

0

SLAVE ADDRESS

DATA

INTERNAt STROBE
FOR DATA LATCHING

Figure 2. 12C Bus Data Format

July 15, 1988

6-29

+ 1477Hz)

•

Signetics Linear Products

Product Specification

DTMF /Modem/Musical Tone Generators

PCD3311/12

Table 2. Input Data for Control (No Output Tone; TONE at VDD)

t

Ds

D4

D3

D2

D1

Do

HEX

X
X
X
X

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

00/20
01/21
02/22
03/23

D1

Do

HEX

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C

1

10

B
C
D

0
1

1E
1F

#

._L-_

OSCILLATOR
ON
OFF
OFF
OFF
--

NOTES:
1 = H = HIGH voltage level
o = L = LOW voltage level
X = don't care

Table 3. Input Data for DTMF
--~:l---'Ds

D4

D3

D2

o
o

0
0
0

1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

o
o

o
o
o

o
o
o
o
o

0
0
0
0
0

1

0
0
0
0
0
0
0
0
1
1
1

o
o
o

o
o
o
o
o

1

o

1
1
1
1

o

o
o

I

1

1
0
0
1
1
0
0
1
1
0
0
1

1

SYMBOL

STANDARD
FREQUENCY
(Hz)

TONE
OUTPUT
FREQ. (HZ)1

697
770
852
941
1209
1336
1477
1633
941 + 1336
697+1209
697 + 1336
697 + 1477
770 + 1209
770+1336
770+1477
852 + 1209
852 + 1336
852 + 1477
697 + 1633
770 + 1633
852 + 1633
941 + 1633
941 + 1209
941 + 1477

0
1
2
3
4
5
6
7
8
9
A

.

-1--1----1

697.90
770.46
85045
943.23
120645
134166
1482.21
1638.24

FREQUENCY DEVIATION
0/0

+0.13
+0.06
-0.18
+0.24
-0.21
+0.42
+0.35
+0.32

Hz
+0.90
+0.46
-1.55
+2.23
-2.55
+5.66
+5.21
+5.24

Table 4. Input Data for MODEM Frequencies

Ds

D4

D3

---0
0
0
0
1
o
1
1
o
1
o
1
o
1
o
1
o
1
o

o
o
a
a
o

D2

1
1
1
1
0
0
0
0
1
1
1
1

D1

Do

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0

I

1

LLtJ
1
1

0
1

STANDARD
FREQUENCY (Hz)

HEX

24
25
26
27
28
29
2A
2B
2C
20
2E
2F

I

1300
2100
1200
2200
980
1180
1070
1270
1650
1850
2025
2225

NOTES:
1 Tone output frequency when usmg a 3579 545MHz crystal
1 = H = HIGH voltage level
o = L = LOW voltage level

July 15, 1988

6-30

TONE
OUTPUT
FREQ. (HZ)l
129694
210314
119717
2192.01
97882
117903
1073.33
126530
165566
185277
202120

1 __~223 32

FREQUENCY
DEVIATION
0/0

Hz

-024
+015
-0.24
-036
-0.12
-008
+031
-037
+034
+015
-019
-008

-3.06
+3.14
-2.83
-799
-1.18
-0.97
+3.33
-470
+5.66
+2.77
-380
-1.68

REMARKS

V.23
Bell 202
V.21
Bell 103
V.21
Bell 103

Signetics Unear Products

Product Specification

DTMF/Modem/Musical Tone Generators

PCD3311/12

Table 5. Input Data for Melody Tones
Ds

D4

D3

D2

Dl

Do

HEX

NOTE

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0

1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0

0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
0
0
0
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
1
0
1

30
31
32
33
34
35
36
37
36
39
3A
29
38
3C
3D
OE
3E
2C
3F
04
05
25
2F
06
07

0#5
E5
F5
F#5
G5
G#5
AS
A#5
85
C6
C#6

STANDARD
FREQUENCY (Hz) 1
622.3
659.3
696.5
740.0
764.0
630.6
660.0
932.3
967.6
1046.5
1106.7
1174.7
1244.5
1316.5
1396.9
1460.0
1566.0
1661.2
1760.0
1664.7
1975.5
2093.0
2217.5
2349.3
2469.0

os

0#6
E6
F6
F#6
G6
G#6
A6
A#6
86
C7
C#7
07
0#7

TONE OUTPUT
FREQUENCY (Hz)2
622.5
659.5
697.9
741.1
762.1
632.3
679.3
931.9
965.0
1044.5
1111.7
1179.0
1245.1
1316.9
1402.1
1462.2
1572.0
1655.7
1766.5
1675.1
1970.0
2103.1
2223.3
2356.1
2470.4

NOTES:
1. Standard scale based on A4 = 440Hz.
2. Tone output frequency when uSing a 3.579 545MHz crystal.
1 - H - HIGH voltage level
o - L - LOW voltage level

CHARACTERISTICS OF THE 12C
BUS

The 12c bus is for 2·way. 2·line communica·
tion between different ICs or modules. The
two lines are a serial data hne (SDA) and a
serial clock line (SCl). 80th hnes must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be initiated
only when the bus is not busy.

IDA

!i

IiI

/

v-+----~
A.....L
___ ~
I
_ _ _.a....

I

SCL~---~
I

I

I

DATA LINE

I CHANGE 1

STAIIU.

I ALLOWED :

I OF DATA I

DATA VAUD

Figure 3. Bit Transfer

Bit Transfer
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse, as changes in the data line at this time
will be Interpreted as control signals.

SOA

is defined as the start condition (S). A lOWto-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition
(P).

80th data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-lOW transition of the data line, while the clock is HIGH.

--+-1
r=-_-_~
i \.\..-!I___....L--c...___
___

r-~--1'1..11
i

....Jo..
\. _ _ _ _

I

SCL

Start and Stop Conditions

I
I

I

-

L ___ .J

START CONDmON

I

p
:
IL ___ J1

STOP CONDmON

Figure 4. Definition of Start and Stop Conditions
July 15, 1966

6-31

SDA

i

r---"\'--__.,f:

--~
:
s; \.....-...-I
I

i

SCL

•

Signetics Unear Products

Product Specification

DTMF/Modem/Musical Tone Generators

System Configuration
A device generating a message is a "transmltter"; a device receiving a message IS the
"receiver". The device that controls the message IS the "master" and the devices which
are controlled by the master are the
"slaves".

Acknowledge
The number of data bytes transferred between the start and stop condttions from
transmitter to receiver is not limited. Each

PCD3311/12

byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse. A slave receiver which IS
addressed must generate an acknowledge
after the recepllOn of each byte. Also, a
master must generate an acknowledge after
the reception of each byte that has been
clocked out of the slave transmitter. The
deVice that acknowledges has to pull down

the SDA line during the acknowledge clock
pulse; so that the SDA hne is stable LOW
during the HIGH period of the acknowledge
related clock pulse, setup and hold times
must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event the transmttter must leave
the data line HIGH to enable the master to
generate to stop condttion.

~----~--------~------~~------~--------~~L-~--;-------1---~----~~-+------~--4-------1-~~--

Figure 5. System Configuration

CLOCK PULSE FOR
ACKNOWLEDGEMENT

START

CONDITION

I

--~

I

SCL FROM
MASTER

DATA OUTPUT
BY TRANSMITTER

--~

DATA OUTPUT
BY RECEIVER

Figure 6. Acknowledgment on the 12C Bus

July 15, 1988

6-32

Signetics Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

PCD3311/12

Timing Specifications
Masters generate a bus clock with a maxi·
mum frequency of 100kHz. Detailed timing is
shown in Figure 7.

SOli.

SCl

SOli.

Where
The minimum time the bus must be free before a new transmiSSion can start
Start condition hold bme

tBUF
tHO; tarA

t:>tLOWmln
t>tHIGHmln

tLOWrnm

471's

Clock lOW panod

tHIGHm,"

4~s

Isu, 1sT.

t>tLOWrnn
I"O~

Clock HIGH panod
Start condition setup time, only valid for repeated start code
Data hold bme
Data setup time
Rise bme of both the SOA and SCL hne

tHO. tDAT
tOAT

tau.

t>250n8
t.:o;;;; 1ps
t<3OOn8
t>tLOWmn

Ie

IF
IsU,ISTO

Fall time of both the SOA and SCl Ime
Stop condition setup time

NOTE:
All the tlmmg values refer to VIH and VIL levels With a voltage SWIng of Vss to Voo

Figure 7. Timing

SOli.

'J"" -\J::J\.... _, - x::J:7\.L-rc::v\._,
I

L.....-J

L....-...----.J L--.....J L......--J

START

ADDRESS

RJW

ACK

I

\

~-,

'---=D-::A~::A--.J'

'AcK'

s'rAR'-r

Where

Clock

\tOWlllln

4 71JS

tHIGHmn
4 IJS
The dashed hne IS the acknowledgment of the receiver
Mark-to-space ratiO
1 1 (LOW-to-HIGH)
Maximum number of bytes
unrestncted
Premature termlnatton of transfer
allowed by generabon of STOP condition
Acknowledge clock bit
must be provided by the master

Figure 8. Complete Data Transfer

July 15, 1988

~

CONDITION

CONDInON

6-33

'RiYr' 'AcK'

~

Signetics Linear Products

Product Specification

DTMF/Modem/Musical Tone Generators

PCD3311/12

1A

I

TA =

>1~F

Voo

II
II

TONE

1.2

PCD3311
PCD3312

5OpF:

Vss

=

S 0.8

j

I

r--...

+2S'C/

V

/

C

10k

-25"<: .....

~

~

I

+70'C/

OA

Figure 10. Standby Supply Current as a
Function of Supply Voltage; Oscillator OFF

Figure 9. TONE Output Test Circuit

300

1.5

TAL -~'c,

~~
)W
J. ~

TALJ,c,",
+2S;C,
+70'C,

+25°C

+70 C
G

200

100

A~

P'
~~

0.5

.~ ~
,..
~

~ '?

4

4

Vco(V)

Voo(V)

Figure 11. Operating Supply Current aa a Function of
Supply Voltage; Oscillator ON; No Output at TONE

Figure 12. Operating Supply Current as a Function of
Supply Voltage; Oscillator ON; Dual·Tone at TONE

-11

TA=-;Z

/~
JV~~

+25°C

r-::

~ -13

J

-14

if

r--

~rs:g- ~GRfP

+"c
-15

o

--

HldHGRdup

+700c-:

~

V, (V)

~

0
Voo (VI

Figure 13. Pull·Down Input Current as a Function of Input
Voltage; VDD 3V

Figure 14. DTMF Output Voltage Levels as a Function of
Operating Supply Voltage; RL lM.n

=

July 15, 1988

T~ = -~'c

-12

!JV
If!
o

/

[;( ~

=

6·34

Product Specification

Signetics Linear Products

PCD3311/12

DTMF/Modem/Musical Tone Generators

OA

n

-20

.....

}
-OA

......

.=

-25-C

li-nliiT

-0.8

10"

r--

i:!l. -40

~

10"

I

-60

-100

CS203

--

r-- --

l.

I
i

I lin

1'1

-80

III

--r-

A A A

1/ llA1~
~y

At
1
IIAI\ 11 ILlI I fI _I 1'111 AI
'V \j VI 101 V'~ IW' 'fI 11 V'\ JV

AA A

~I

r

o
FREQUENCY (kHz)

Figure 15_ Dual-Tone Output Voltage
Level as a Function of Output Load
Resistance

Figure 16. Typical Frequency Spectrum of a Dual-Tone Signal After Flat-Band
Amplification of 6dB

MUTE
GENERAL
PURPOSE
MlCROCONTROLLER

(4 - OR 8-BI1)

STROBE

DATA BUS

PCD3311

TONE

II

II
Figure 17_ PCD3311 Driven by a Mlcrocontroller with Parallel Data Bus

July 15, 1988

6-35

•

Product Specification

Signetics Linear Products

PCD3311/12

DTMF/Modem/Musical Tone Generators

MUTE
TELEPHONY

MICRQCONTROLLER
PCD3343

TONE

I I

I I
NOTE:
The PCD3343 15 a smgle-chlp a-bit mfcrocontroller with 3k ROM/224 RAM bytes
The same apphcatlon IS possible with the PCD3311 with MODE = vss

Figure 18. PCD3312 Driven by Telephony Microcontroller PCD3343 with Serial I/O (1 2 C Bus)

July 15, 1988

6-36

PCD3315

Signetics

CMOS Redial and Repertory
Dialer
Product Specification

Linear Products
DESCRIPTION
The PCD3315 is a single-chip CMOS
dialer IC for telephone sets. It has two
dialing modes: pulse dialing (PD), and
dual-tone multi-frequency (DTMF) when
used in conjunction with tone generator
PCD3312. In addition to manual dialing,
it also features several automatic functions, such as redial, extended redial,
note-pad, and repertory dial.

FEATURES
• Pulse dialing
• DTMF dial control of tone
generator PCD3312
•
•
•
•
•

Redial
Extended redial
Electronic notepad
Ten repertory dial numbers
18-digit capacity for each
autodial memory

• 12C compatible
• Maximum of 36 digits per call
• Flash or register recall

• Uses standard 4 x 4 keyboard
(single- or double-contact)
• Four extra function keys:
program/autodial, flash, redial,
access pause
• Access pause generation and
termination
• Automatic PABX-digit recognition
resulting in an access pause
insertion
• Hold input and access pause
output (APO) to adjust the
duration of the access pause
and facilitate use of tone
recognizers
• Four diode or strap functions:
general/German, access pause
time, reset delay time, general:
mark-space ratio/German:
prepulse
• Manual reset of autodial RAM
• On-chip power-on reset
• Programmed for improved noise
immunity

APPLICATION
ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP (SOT-117D)

-25'C to + 70'C

PCD3315PN

28-Pin Plastic SO package
(80-28; 80T-136A)

-25'C to + 70'C

PCD3315TD

May 5, 1988

6-37

N, 0 Packages

TOP VIEW
PIN NO. SYMBOL
DESCRIPTION
Internally connected
IC
Internally connected
IC
IC
Internally connected

'1

10
11
12
13

• Feature phones

DESCRIPTION

PIN CONFIGURATIONS

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

ROW 2
ROW
ROW 3
ROW 4
ROW 5
DIODE
APO
HOLD
CE
j5'i)/DTMF

Vss
XTAL1 }
XTAl2

Scanning row keyboard outputs

Diode option output
Access-pause output
Hold Input
Chip-enable Input
Input to select pulse or DTMF
dialing
NegatIVe supply
Crystal pins

RESET

Reset mput/output

COL 2
COL 3
COL 4
DP/FL
M1
SDA
Sel
IC
IC

Sense column keyboard Inputs

'1

VDD

Dialing pulse and flash output
Muting output
Senal data
Senal clock
Internally connected
Internally connected
Positive supply

853-1146 93195

•

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

PCD3315

BLOCK DIAGRAM OF FEATURE PHONE

-

......

600

KEYBOARD

LN

Vee

Voo

CE

ct-

MUTE

HOOK

~ ~>-

MDPCD3315

r--

TEA1060

UNE

~MF

I--

TP-

~D~
VEE

PO

~L

SOA

OSCI

PCD3312

ABSOLUTE MAXIMUM RATINGS
PARAMETER

VDD

Supply voltage (Pin 28)

VI

All input voltages

±II, ±Ic

RATING

UNIT

-0.8 to +8

V

0.8 to VDD + 0.8

V

DC current into any input or output

10

mA

PTOT

Total power dissipation

500

mW

Po

Power dissipation per output

50

mW

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-25 to +70

·C

TJ

Operating junction temperature

125

·C

OJA

Thermal resistance Gunction-to-ambient)
for SOT-117D
for SOT-136A

120
150

·C/W
·C/W

May 5, 1988

6-38

4

B

7

8

9

C

0

#

0

PL

R

AP

P

IIII
'""<

.." ..'"'"
w

~
a:

DTMF

SYMBOL

A

..

W

SCL

3
6

w

V"

DPIFLASH

2

5

w

3.58 MH;-

~

INTERRUPTER

1

S

w

...c
"~ '"a:
w

w
w

=~

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

DC ELECTRICAL CHARACTERISTICS

PCD3315

VDD ~ 2.5 to 6V, Vss ~ OV, TA ~ -25 to + 70°C; all voltages with respect to Vss;
f ~ 3.58MHz with Rs ~ 50n, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

Voo
VDD

IOD
IDD
IOD
IDD
IDO

Supply voltage
operallng
STOP mode for RAM retention 1
Supply current
dialing mode
at VDD ~ 3V
conversation mode
at Voo ~ 3V
STOP mode2
at VOO ~ 1.8V; TA
at VOO ~ 1.8V; TA
at VDO ~ 1.8V; TA

~
~
~

Typ

2.5
1.0

25°C
55°C
70°C

Max

6
6

V
V

500

!J.A

270

!J.A

1.2

2.5
5
10

1.2

1.5

!J.A
!J.A
!J.A

RESET 1/0

VRESET

SWitching level

10L

Sink current at VOD

> VRESET

7

V
!J.A

Inputs

V,L

Input voltage lOW

0

0.3VDD

VIH

Input voltage HIGH

0.7VDO

VDD

V

±I'L

Input leakage current at Vss

1

!J.A

< V, < VDD

V

Outputs

VOL

Output voltage lOW at V, ~ Vss or VDD, 110 I < 1!1A

10L

Output sink current lOW at VDD

-IOH
-IOH

Pull-up output source current HIGH (except SDA, SCl)
at VO D ~ 3V; Vo ~ 0.9VDD
at VDD ~ 3V; Vo ~ Vss

~

3V; Vo

~

OAV

0.05
0.6

1.5

10

NOTES:
1. Because RAM IS cleared If POR IS activated by software, thiS value must be max VAESET

2. Crystal connected between XTAL1 and XTAL2, SCL and SDA pulled to Voo via 56kn reSistor, CE and PD/DTMF at Vss

May 5, 1988

6-39

V
mA

200

!1A
!1A

•

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

PCD3315

Dialing Pulse and Flash Output
(DP/Fl)

FUNCTIONAL DESCRIPTION
Power Supply (VDD; VSS)

• Dialing

This output drives the line interrupter circuit.
In pulse dialing mode, it controls the timing for
the line interrupter. This output also provides
a "Flash" pulse which generates a 95ms line
break. In the German version, this "Flash"
occurs only in the DTMF dialing mode.

(see Operational Description)

Chip Enable Input (CE)

Oscillator (XTAl1; XTAl2)

The CE input is used for hook-detection.
Hook-off will result in CE = HIGH. This will
change the circuit state from standby to
operational mode and also initialize the circuit.
When the circuit detects a line break longer
than the reset delay time, it will switch the IC
to the standby mode. This essentially
achieves a low standby current during hookon. During access pauses, the reset delay
time is longer because the telephone line
supply is switched over, which may result in
longer line drops.

The minimum supply voltage and supply current depend on the operating modes:
• Standby
• Conversation

The timebase for the PCD3315 is a crystalcontrolled oscillator with a 3.58MHz quartz
crystal connected between XTAL 1 and
XTAL2. The oscillator will run when the
CE = HIGH. The output XTAL2 can drive the
oscillator input of the PCD3312 via a capacitor.

Keyboard Inputs/Outputs (COL
1 to 4; ROW 1 to 5)
The sense column COL 1 to COL 4 and the
scanning row outputs ROW 1 to ROW 4 are
directly connected to a 4 X 4 single-contact
keyboard matrix. An extra row (ROW 5) is
added to address four additional function
keys that are required for autodial functions.
The keyboard organization is shown in Figure
1. Keyboard entries are valid 20ms (debounce time) after the leading edge and until
20ms after the trailing edge of the keyboard
entry.
In pulse dialing mode, the valid keys are the
10 numeric keys (0 to 9). The 6 non-numeric
keys (A, B, C, D, *, #) have no effect on the
dialing and are ignored.
In DTMF dialing mode, the 10 numeric keys
and the 6 non-numeric keys are valid.

Diode Option Output (DIODE)
An extra row is added to the keyboard matrix
to provide several selections:
• Access pause duration
• Reset delay lime
• Mark/space ratio or prepulse yes/no
• General or German version
ROWS

'---

3

A

4

5

6

B

7

8

9

C

0

#

D

FL

R

AP

P

May 5, 1988

Dialing Mode Selection Input
(PD/DTMF)
This input selects the dialing mode:
• PD/DTMF = LOW selects pulse dialing
• PD/DTMF = HIGH selects DTMF dialing

Reset Input/Output (RESET)
When the reset input is active High, it can be
used to initialize the IC. In normal application,
this is achieved by the CE input. Reset is also
an output of the internal power-on reset
circuit, which generates a reset pulse if Voo
drops below 1.3V (typ.).

OPERATIONAL DESCRIPTION

• During access pauses; Mute = HIGH
during the mute hold-over time

Standby Mode

• During flash; Mute

= HIGH

• During programming

Hold Input (HOLD); Access
Pause Output (APO)
The hold input suspends dialing after completion of the current digit, or in pulse dialing
during the inter-digit pause.
The hold function facilitates an extra time
delay during dialing under the control of
external Circuitry, i.e., a dialing tone recognizer.

• Dialing
When the chip enable input (CE) is LOW, the
IC is in the standby mode. The oscillator is
switched off and the IC requires only a
standby current (1.2p.A typ.) for memory retention.
The circuit will leave the standby mode and
enter the conversation mode 0.5ms after CE
becomes High.

Conversation Mode
In this mode, the IC is active in order to scan
the keyboard entries. Mute and dialing pins
are Inactive. The current consumption is
270/JA (typ.) at Voo = 3V.

Dialing Mode
The IC will be switched to the fully-operational mode in the following circumstances:
• A valid keyboard entry
• Dialing mode
• Programming mode
The current consumption is 500/JA (typ.) at
Voo = 3V.

DIAUNG
TONE

KEYBOARD

Figure 1. Keyboard Organization

The serial I/O lines SDA and SCL are used to
control the PCD3312 in the DTMF dialing
mode (see Figure 4). Both outputs require
external pull-up resistors.

The PCD3315 has 3 operating modes:
• Standby
• Conversation

I I I
2

Serial Data (SDA); Serial Clock
(SCl)

• In DTMF dialing mode; Mute = HIGH
during DTMF bursts plus hold-over time

In the hold state (HOLD = LOW), the muting
output is also LOW, thus the IC is in the
conversation mode. The RQ[D input can be

COLUMNS

L~

Mute Output (M1)
This output is active
• In pulse dialing mode; Mute = HIGH
during interdigit pause plus dialing
pulses

controlled by the access pause output (APO) ,
directly, or indirectly via a dialing tone recognizer (see Figure 2). The APO output will go
LOW when an access pause is recognized.

Figure 2. Automatic Variation
of Length of an Access Pause
Under the Control of a Dialing
Tone Recognizer

6-40

The PCD3315 has two dialing modes:
• Pulse dialing direct via DP /FL output
• DTMF dialing via PCD3312 using the serial
I/O lines SDA and SCL

Pulse Dialing
The timing sequence for pulse dialing is
shown in Figure 3a. Output DP/FL starts with

Product Specification

Signetics Unear Products

CMOS Redial and Repertory Dialer

an inter-dig~ pause, followed by a sequence
of pulses corresponding to the digit for transmission. The dialing frequency is fixed at
10Hz; the break and make times are 60ms
and 40ms, respectively.
In the general version w~h diode opl1On, the
user can also seleC1 break and make times of
67ms and 33ms, respectively.
The muting pulse will overlap the total dialing
sequence. After dialing, the muting output
(Ml) goes LOW and the circuit is switched to
the conversation mode.
DTMF Dialing
The timing sequence for DTMF dialing IS
shown in Figure 3b. The PCD3312 generates
the seleC1ed DTMF tones via the serial I/O
lines SDA and SCL. These tones are transmitted with minimum tone burst durations of
70.70ms (for the German version 80.80ms).
The maximum tone burst duration is equal to
the key depression time.
After dialing, the muting output goes LOW
after a hold-over time of 80ms, and the circu~
is switched to the conversation mode.

Normal Dialing
The Ie has a working register with a maximum capac~ of 18 positions. Entries in these
positions may be:
• 10 numertc digits 0 to 9
• Manually-programmed access pauses
• 6 non-numeric special keys (*, II, A, B,
C, D) in DTMF mode
If none of the special keys has been pressed,
the contents of the working register will be
stored automatically in the Redial Buffer.
The number of dig~ can be extended to a
maximum of 36, but this will result in a redial
memory clear after hook-on. This is also valid
for manual dialing after automatic dialing.

Automatic Dialing
In addllton to manual dialing, the IC prOVides
the follOWing automatic funC110ns:
• Redial of the last manually-dialed
number (German version) or
Redial of the last-dialed number
(general version)
• Extended redial
• Electronic notepad
• Maximum of 10 repertory dialing
numbers
The maximum capacity of the registers for
these numbers is also 18 positions. The 6
non-numeric digits (*, II, A, B, C, D) Will not
be stored.
To achieve these automatic dialing funC1ions,
an extra row of the keyboard is required
which contains the following special funC1ion
keys:
• P programming/automatic dialing

Access Pause

• HOLD Input connected to Voo, no
access pause

PABX Digits

Program procedure: P - R - d1, d2 R d3 d4.

During a dialing sequence, it may be necessary to insert a wait time to ensure correct
dialing. A dialing sequence can always be
interrupted by the HOLD Input through an
access pause recogmtion, which results in a
fixed time delay.
There are three ways to enter an access
pause:
• At manual dialing by pressing the AP
key

PROGRAM

Automatic
TN-P
Dial'P'P-TN'P
P'd'TN
P-R-d 1 (d2) R d3 (d4)

Where:
d=DtgrtOto9
2, 5, 8. 0 - Press and keep pressed keys 2. 5, 8. and 0
2, 5, 8. 0 - Aelease keys 2. 5, 8. and 0

TN - Telephone number

May 5, 1988

Pin enables a· dialing tone
recogmzer, which controls the HOLD
Input (see Figure 2)

The PCD3315 Will detect pre-programmed
PABX digits and Insert an access pause In the
dialing sequence. The reserved capacity is for
two different PABX numbers With a maximum
of 2 digits each.

OPERATION

P = Press and release pokey
j5 = Press and keep pokey pressed
A = Press and release A-key

• APO

• FL flash or register recall

Table 1. Keying Procedures for Dial and Program Operation
R
P'R
P'R
P'd
Automatic
Hook-on
2,5,8,0
Hook-off
2, 5, 8, 0

• HOLD, APO pins Interconnected via an
RC network; after a fixed time delay of
3 or 5s In pulse dialing; 1.5 or 2.5s In
DTMF dialing - plus an additional time
delay determined by the RC values

• R redial
• AP manual access pause entry
Besides the operational procedure for automatic dialing, there are also procedures for
programming these numbers into the memory
(see Table 1).

• Recognition of PABX digrts, after which
an automatic access pause Will be
inserted

MODE

There are four ways to terminate an access
pause·
• HOLD, APO pins directly Interconnected;
after a fixed time delay of 3 or 5s In
pulse dialing; 1 5 or 2.5s In DTMF
dialing The fixed time delay IS
determined by a diode strap

During the access pause, the muting output
remains active durtng hold-over time. In order
to handle longer line drops durtng access
pauses, the PCD3315 automatically SWitches
to the maximum reset delay time of 320ms.

• At auto dialing by recognition of the
AP-code in the memory

Redial
Extended redial
Notepad
Repertory dial
PABX digrts
Reset autodial
RAM

PCD3315

6-41

Notepad
In the conversation mode, the notepad procedure will overwrtte the extended redial buffer,
Without dialing-out digitS. After hook-off, thiS
number can be recalled through the extended
redial buffer.
Store procedure: poP-TN P
Dial· P-R

Flash

(see Figure 3b)
Flash or register recall is activated by the
flash key which results In a timed line break at
output pin DP /FL. ThiS line break is of a fixed
95ms duration In both pulse and DTMF dialIng modes. In the German verSion, it is only
applicable to the DTMF mode.

•

Signetlcs Linear Products

Product Specification

CMOS Redial and Repertory Dialer

In the dlahng procedure, a flash entry will
initJalize the Ie and, thus, the working register
which acts hke a chip enable procedure.

Memory Clear
A built-in, manual total-memory clear to facilitate resetting of the autodial RAM after servicing, maintenance, or telephone set delivery
exists.
Procedure: hook-on, press, and keep depressed keys 2, 5, 8, 0; hook-off, release keys

2, 5, 8,

PCD3315

Program Security

Diode Options

Security measures are incorporated In the Ie
to avoid Incorrect dialing operations and
hang-ups.
The program has a built-in RAM check procedure to protect the autodial numbers stored in
the RAM. If one or more bits of this RAM are
changed during standby, or the battery falls
below 1.3V (typ.), this will result In a memory
clear to avoid subsequent incorrect dialing.

There are 4 different diode or strap options
which are an extension of the keyboard
matrix. Addressing Is via the 4 columns and
diode pins.
There are two possibilities:
• Without diode
• With diode (cathode on row-side)
The buiH-in selections are shown in Table 2.

o.

Table 2. Diode Option Selections
COLUMN

DESCRIPTION

4

WITHOUT DIODE

Version
Break, make-time
Prepulse
Access pause
Access pause
Reset delay time

1
1
2
2
3

REMARKS

WITH DIODE

German
60,40ms
No
3s
1.5s
160ms

General
67, 33ms
Ves
5s
2.5s
320ms

General version
German version
Pulse dialing
DTMF dialing

Table 3. Timing Date, General Version
TYP
SVMBOL

PARAMETER

MIN

UNIT
Without Diode

WHh Diode

tROS

Reset delay time

160

320

ms

tRoS

Reset delay time during access pause

320

320

ms

tOB

Keyboard debounce time

20

20

ms

tFL

Flash time

95

95

ms

Pulse dialing
~

fo

Dial frequency

tBIM

Break/make time

10

10

Hz

60/40

67/33

ms

tlOP

Interdigit pause

840

840

ms

tAP

Access pause

3

5

s

tH

Mute hold-over time (only during access pause)

1

1

s

DTMF dialing
tT

Tone transmission time

tp

Tone pause time

tH

Mute hold-over time during dialing

tH

Mute hold-over time during access pause

tAP

Access pause

May 5, 1988

70 or key·down time

ms

70

6-42

ms
150

150

ms

1

1

s

1.5

2.5

s

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

PCD3315

Table 4. Timing Data, German Version
TYP
SYMBOL

PARAMETER

UNIT

MIN
Without Diode

With Diode

tROS

Reset delay time

160

320

tRoS

Reset delay time dUring access pause

320

320

ms

tOB

Keyboard debounce time

20

20

ms

ms

Pulse dialing
fo

Dial frequency

tBIM

Break/make time

10

10

Hz

60/40

60/40

ms
ms

t,OP

Interdlglt pause

840

840

tAP

Access pause

3

5

s

tH

Mute hold-over time (only dUring access pause)

1

3

s

tpp

Prepulse time

20

ms

DTMF dialing
80 or key-down time

tT

Tone transmiSSion time

tp

Tone pause time

tH

Mute hold-over time dUring dialing

tH

Mute hold-over time dUring access pause

tAP
tFL

ms

80

ms
160

160

1

1

ms
s

Access pause

1.5

2.5

s

Flash time

95

95

ms

•

lOB

KEYBOARD
ENTRY

--+--~

!' -~-------,!, I ,!
" -_ _--.L_ >CONTACT BOUNCE TIME +20ms

L----t----

Ml

DP/Fl

f+-.......~*o-----------

DIALING MODE

-----------+++-----11+-CONVERSATION
MODE

CONVERSATION
MODE (AWAIT
DIALING TONE)

MODE

Figure 3a. Timing Diagram for Pulse Dialing Mode, Defined by PD/DTMF

May 5, 1988

STATIC
STANDBY

6-43

= LOW (Vss)

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

PCD3315

Ht

CE

.Jr---------iU

Ros

(NO EFFECT)

,
I
KEV~~~~~ _ _ _ _~

M1

DTMF

DPIFL

----------------------------------------~
Figure 3b. Timing Diagram for DTMF Dialing Mode, Defined by PD/DTMF = HIGH (VDD)

May 5, 1988

6-44

Signetics

PCD3341
CMOS Repertory Telephone
Set Controller
Preliminary Specification

Linear Products

DESCRIPTION
The PCD3341 is a low threshold voltage
IC fabricated in CMOS. It is designed to
control display, redial and repertory dialing in a telephone set. The IC has two
dialing modes: Pulse Dialing (PD) and
Dual Tone Multi-Frequency (DTMF). The
architecture of the PCD3341 IS identical
to that of the PCD3343. It comprises an
8-bit CPU, 224 RAM bytes and 3k ROM
bytes (the ROM is already programmed).
The operating supply voltage is 2.5 to
6.0V with a low current consumption in
all operating modes: Standby, conversation and dialing modes. Up to 18 digits
and 2 manual access pauses can be
stored for redial, extended redial and
direct dial purposes together with onchip storage for 10 repertory numbers.
For expansion of the system, the
PCD3341 provides a two-wire serial input! output port, in accordance with the
12C bus specifications, to control the
DTMF tone generator, LCD drivers and
additional RAMs for additional repertory
numbers.

FEATURES
• Pulse dialing
• DTMF dial control of tone
generator PCD3312
• Redial/Extended Redial

December 1988

• Electronic notepad
• Direct dialing (emergency call)
• On-chip storage for 10 repertory
dial numbers
• 18-digit capacity for each
autodial memory
• Flash or register recall
• Manual reset of autodial RAM
• On-chip power-on reset
• Programmed for improved noise
immunity
• Extension possible with external
RAM for up to 110 repertory dial
numbers
e Four extra function keys:
Program/autodial, flash, redial,
access pause
• Keyboard expansion possible for
10 separate repertory dialed
numbers
• Automatic recognition of PABX
digits resulting in an access
pause insertion
• Hold input and access pause
output (APO) to adjust the
duration of the access pause
and facilitate use of tone
recognizers
• Six diode or strap functions:
Mark-to-space ratio, tone burst
time, inter-digit pause time,
access pause time, normal or
expanded keyboard, normal or
direct dialing

6-45

PIN CONFIGURATION

TOP VIEW

PIN NO. SYMBOL
DESCRIPTION
1
MT
Inverted output of M1
2
SOA
Senal data
3 seL
Serial clock

=g~ ~1

ROW 3
7
8

ROW 4
ROW 5

~

~~6' 6

1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Scanning row keyboard outputs

J Access-pause output
HOLD
Hold Input
CE
Chip-enable mput
PO/DTMF Input to select pulse or DTMF
dlahng
Negative supply
Vss
XTAL1
Input to on-chip OSCillator
XTAL2
Output from on-chip OSCillator
RESET
Reset Input/output

COL
COL
COL
COL

1
2
3
4

Sense column keyboard Inputs

COL 5
COL 6
M3

5P
DP
M1
VOD

Muting output
Inverted pulse dialing output
Pulse dialing output
Muting output
Positive supply

•

Signetics Linear Products

Preliminary Specification

CMOS Repertory Telephone Set Controller

PCD3341

BLOCK DIAGRAM

ROW KEYBOARD OUTPUTS
ROW 1

COLUMN KEYBOARD INPUTS
COLa

COLI

DPM3
11 10 9

8

7

a

5

4

DP Ml

25 24 23 22 21 20 19 18

iii SDA

SCL

262712

? CONTROUER

PCD3341

ACCUMULATOR
&
TEST LOGIC

December 1988

15

16

17

XTALI

XTAL2

RESET

6-46

13

PD/DTIF

12

CE

Signetics Unear Products

Preliminary Specification

CMOS Repertory Telephone Set Controller

PCD3341

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

28-Pln Plastic Dip (SOT-117D)

DESCRIPTION

-2S"C to + 70"C

PCD3341TD

28-Pln Plastic SO (SO-28; SOT-136A)

-2S"C to + 70"C

PCD3341TD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

limiting values In accordance with the
Absolute Maximum System (IEC 134)

PARAMETER

RATING

Voo

Supply voltage range (Pin 28)

±I" ±Io

DC current Into any Input or output

V,

All Input voltages

Po
Po
TSTG

Storage temperature range

TA

Operating ambient temperature range

UNIT

-0.8 to 8

V

10

rnA

Vss-0.8 to
Voo +0.8

V

Total power dissipation

500

mW

Power dissipation per output

50

mW

-65 to +150

"C

-25 to +70

"C

DC AND AC ELECTRICAL CHARACTERISTICS

Voo = 3V; vss = OV; crystal parameters: fose = 3.S79S4MHz; Rs = son
max.; TA = 2S"C; unless otherwise speCified.
LIMITS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

2.5

3

6.0

Supply
Voo

Operating supply voltage
Operating supply current

1000

Conversation mode (CE = 1)
Dialing mode (CE = 1)

Vooo

Standby supply voltage (CE = 0)

1000

Standby supply current (CE = 0)

lODe

270
600
18

3

V
jJ.A
jJ.A

6.0

V

2.5

jJ.A

1.5

V
jJ.A

0.3Voo

V
V

100
1

nA
jJ.A

1

kn
kn

Reset 110
VRESET
IOL

Switching level at Voo < VRESET
Sink current at Voo < VRESET

1.3
7

Inputs
V,L
V,H
-I,L
I,L

Input voltage Low (any Pin)
Input voltage High (any pin)
Input leakage current; CE
at V, = Vss to Voo
at CE=l

0
07Voo

Keyboard contsct resistance
RKON
RKOFF

Keyboard ON
Keyboard OFF

100

Outputs
IOL
-IOH

IOL
-IOH

December 1988

Ml, Ml, M3, DP, DP
Output Sink current
at VOL =0.4V
Output source current
at VOH = 2.6V (push-pull)
SDA, SCL
Output Sink current
at VOL = O.4V
at VOH = 0 to Voo (open drain)

1.5

rnA

1.5

rnA

1.5
1

6-47

rnA
jJ.A

I

Preliminary Specification

Signetics Linear Products

CMOS Repertory Telephone Set Controller

FUNCTIONAL DESCRIPTION
Power supply (VDD; Vss)

(tAP)' The APO output WIll go Low when an
access pause IS recognIzed.

Power supply must be retaIned for data
storage.

Serial Data (SDA); Serial Clock
(see Figure 4)

Clock Oscillator (XTAL 1; XTAL2)

The serial I/O lines, SDA and SCL, are used
to control the PCD3312 in the DTMF dialing
mode, addItional RAMs (PCD8570) for repertory and LCD drivers (PCF8577). Both outputs requIre external pull-up resIstors.

The tIme base for the PCD3341 is a crystal
controlled, on-chIp oscIllator whIch IS completed by connectIng a 3.58MHz crystal between XTAL1 and XTAL2. The oscIllator
starts when VDD reaches the operatIng voltage level and CE = HIgh. The output XTAL2
can be used to drive the oscIllator input of the
PCD3312.

Chip Enable (CE)
ThIS actIve-HIgh Input IS used to InItialize part
of the system, to select the operatIonal or
standby mode, and to handle line power
breaks.

Pulse Dialing Outputs (DP; DP)
DP output drives an external sWItchIng transistor or relay In pulse dialing mode. This
output IS also used to pulse out a calIbrated
FLASH pulse (recall regIster) of 90ms duratIon as soon as the keyboard Input FLASH IS
activated by depressIng the key F. The
FLASH function acts like CE WIth respect to
redIal.

Muting Outputs (M1; M1; M3)
M1 output IS used for mutIng dUring the
dIaling sequence For pulse dIaling, M1 goes
High WIth the first Inter-dIgIt pause and remaIns actIve for 33 or 40ms (mark-to-space
selectIon) followIng the last break pulse after
the last dIgIt held in store has been transmitted. In DTMF dIaling, Input PD/DTMF IS HIgh.
M1 IS HIgh as long as two out of the eIght
frequency sIgnals are sent, then remaIns HIgh
for an additional 80ms (hold-over tIme). M1
output IS the inverted output of M1.
M3 output IS an AND functIon, WIth DP and
M1 as Input, used for dIrect drive of a
switchIng transIstor for dIaling pulses and
muting.

Hold input (HOLD; Access
Pause Output (APO)
The hold input suspends dialing after completion of the current digit, or In pulse dIaling
during an inter-digit pause.
The hold functIon facIlitates an extra tIme
delay during dIaling under control of external
circUIts (dIaling tone recognozed). In the hold
state (HOLD = Low), the mutIng output is also
Low, thus the IC IS In the conversation mode.
The HOLD Input can be controlled by the
access pause output (APO) directly or ind,rectly vIa a dialing tone recognozer (see FIgure
1). The tone recognozer automatIcally termInates access pauses upon receipt of the
access tone, regardless of whether thIs occurs dUring or after the access pause time
December 1988

Keyboard Inputs/Outputs (COL
1 to 6; ROW 1 to 6)
The sense column inputs, COL 1 to COL 6
and the scannong row outputs ROW 1 to
ROW 6, are dIrectly connected to a 4x4 single
contact keyboard matrox. The keyboard
organozatlon IS shown In FIgure 2. In the pulse
dIaling mode the valid keys are the 10 numerIC keys (0 to 9). The 6 non-numeric keys (A, B,
C, D, " #) have no effect on the dIaling. In
the DTMF dIaling mode, the 10 numeric keys
and the 6 non-numeric keys are valid. OnchIp repertory dIaling uses the 10 numeric
numbers (no external RAM).
WIth extended repertory dIaling, 10 extra keys
(M1 to M10) are used (on-chip or external
RAM). Row 5 of the keyboard contains the
followIng special funcllon keys:
• P Memory clear and programming
(notepad)
• FL Flash or register recall
• R RedIal
• AP Manual access pause entry

Diode Options (ROW 6)
ROW 6 IS added to the keyboard matrix to
prOVIde the followIng selectIons:
Mark-to-space ratIo (M/S)
OFF M/S 3:2
ON M/S 2:1
Tone burst tIme (tTS)
OFF tTS = 70ms
ON tTS = 100ms
Inter-dIgIt pause (IDP)
OFF IDP = 900ms
ON IDP = 500ms
Access pause tIme (tAP)
OFF tAP = 1.5s (DTMF; 3s (PD»
ON tAP = 2.5s (DTMF; 5s (PD»
Keyboard expansIon (EKB)
OFF normal keyboard
ON expanded keyboard
Normal/direct call (N/D)
OFF normal call mode
ON direct call (emergency)

6-48

PCD3341

Dialing Mode Selection Input
(PD/DTMF)
ThIS input selects the dialing mode:
• PD/DTMF = Low selects pulse dialing
• PD/DTMF = High selects DTMF dialing

Reset Input/Output (RESEn
When the reset input is actove-High, it can be
used to Initialize the IC. In normal application
this is achieved by the CE Input. Reset is also
an output of the internal power-on reset
CIrcuit, whIch generates a reset pulse if VDD
drops below 1.3V (typ.).

OPERATION
The PCD3341 has 3 operating modes:
• Standby
• Conversation
• DIaling

Standby Mode
When the chIp enable input (CE) IS Low, the
IC is dIsabled. In the standby mode, the only
current drawn is from a back-up supply (battery or line powered) for memory retention,
holdIng up to 13 call numbers for repertory
and redialing.

Conversation Mode
After the handset IS lifted, CE IS activated and
VDD rises to the working voltage. M1 muting is
InactIve and speed or dIal tone can be heard.
With the oscillator operating, the chip is ready
to accept keyboard entries. Current consumption is < 3001IA.

Dialing Mode
The dIaling mode starts with fIrst valid keyboard entry when it initiates:
• a normal call of a newly dialed number
or
• a repertory or redialing cycle of
previously entered and stored numbers
The current consumption IS

< aOOIIA.

=

Pulse Dialing (PD/DTMF Low)
The keyboard entry initiates a recall from a
previously stored number, or is a simultaneous keying-in and pUlsing-out activity, with
storing for possible later recall. If in the
recalled number or at keying-in the keys', #,
A, B, C, D keys are used, these digits will not
be transmitted. Normally, keying-in is followed
by an inter-digit pause of 900 or 500ms
duration (diode option IDP), followed by a
sequence of pulses corresponding to the
present digit in store. Each pulse starts with a
mark (line break) followed by space (line
make).
The pulse period is 100ms with a mark-tospace ratio of 3:2 or 2:1 (diode option). After
transmission of a digit, the next digit will be

Preliminary Specification

Signetics Linear Products

CMOS Repertory Telephone Set Controller

processed again, starting with an Inter-digit
pause. The pulsing IS suspended If HOLD
goes Low. It will be terminated If the current
memory content has been transmitted, or the
handset is replaced (CE = Low < tAD)' The
pulses are available on the DP line. After
completion of the number string, M1 goes
Low and the circUit changes from the dialing
mode to the conversation mode.
Dual Tone Multi Frequency Dialing (POI
DTMF=HIGH)
The PCD3341 converts keyboard Inputs into
serial data via the 12C bus lines SDA and SCL,
suitable for control of the PCD3312 DTMF
tone generator. These tones are transmitted
With minimum tone burst durations of
70.70ms. The maximum tone burst duration IS
equal to the key depression time. With redial
and repertory dialing, tones are automatically
fed at a rate of 70.70ms. After dialing, the
muting output goes Low after a hold-over
time of 80ms, and the circUit IS switched to
the conversation mode.

SYSTEM EXTENSION
The PCD3341 can control the extensions of a
telephone set via its 12C bus. Both in DTMF
dialing and pulse dialing, an extended repertory dialer provides more than 10 stored onchip numbers, and the indication on an LC
display of all keys pressed (programming or
dialing procedure).
The following ICs can be used In combination
with the PCD3341:
• PCD3312
• PCD8570

DTMF generator
256 x 8 static CMOS RAM

• PCF85772

LCD drivers In LCD module

DTMF Dialing
By uSing a PCD3312 DTMF generator With
bus interface, the PCD3341 may be
extended to Dual Tone Multi Frequency dialing applications. This is selected when the
input pin PD/DTMF = High. DTMF dialing is
much faster than pulse dialing. Each keypad
digit corresponds to a umque combination of
two frequencies: One from a group of 4 high
frequencies, and one from a group of 4 low
frequencies. Both frequencies are applied
simultaneously to the line. The PCD3341 IS
capable of directly driving the PCD3312 OSCillator.
12C

Repertory Dialing
If more than 10 stored numbers are reqUired,
repertory dialing can be extended by the 12 C
bus lines and external CMOS RAMs
(PCD8570) with serial interface. With a RAM
capacity of 256 X 8 bits, another 20 stored
numbers can be added. A maximum of 5
external RAMs can be served by the
PCD3341 directly. ThiS provides a telephone
With a total capacity of 110 (100) stored
December 1988

PCD3341

numbers. The number of external RAMs connected on the 12C bus lines IS automatically
checked by the PCD3341 at Initial turn-on.
To identify each RAM, the PCD8570 has 3
hardware address pins (A2, A 1, AO) which
allow a maximum of 8 RAMs to be connected

Display
To display the dialed phone number or programmed number, the PCD3341 provides the
signals to control an LC Display module uSing
two PCD8577 duplex drivers These signals
are fed via the 12C bus lines. In the dialing and
programming modes, the digits are displayed
from right to left in the sequence entered by
the keyboard. The access pause IS indicated
by the bar If the number of digitS exceeds 16,
they drop out on the left Side of the display

OPERATING PROCEDURE
Initialization
At the first application of the standby power
supply, the PCD3341 Will clear the RAM In
order to aVOid a wrong content By lifting the
handset, the buffer capacitor for Voo IS
charged to the operating voltage. CE Will then
be activated. Within start-up time, the OSCillator starts and the initialization program begins.

Automatic Access Pause
Setting
Before the start procedure, the system can
also be Initialized by setllng the access pause
system (e.g., for PABX applications) The
circuit Will automatically Insert an access
pause after recognition of access of a number Within a digit group ThiS (or these) dlglt(S)
must be programmed. Up to a maximum of 3
digits per group can be programmed.
The procedure IS as follows.
• Depress and hold pushbutton P
• Press and release pushbutton R
• Enter 1, 2 or 3 digits as access digit
for first group
• Release pushbutton P (only if no
second group IS reqUired)
• Press and release pushbutton R
• Enter 1, 2 or 3 digitS for second group
• Release pushbutton P

Apart from the procedure that automatically
detects and Inserts access pause(s), a telephone number With up to 2 additional manually Inserted access pauses can be dialed or
programmed by pressing button AP. In DTMF
dialing mode, each access pause has a
duration of 1.5 or 2.5 seconds. In the PD
mode, each access pause has a duration of 3
or 5 seconds.

Data Entry
The debounce keyboard entries are written
Into the on-Chip CMOS RAM In consecutive
order.

Dialing
If the first pushbutton pressed IS 0 to 9 In
pulse dialing, or 0 - 9, A to D, " # in DTMF
dialing, digits are entered Into the redial
register after Initial clearing. DUring the data
entry, the CIrCUit starts With the transmission
of the call, and IS unaffected by the speed of
entry. Transmission conllnues as long as
further data Input has to be processed Up to
18 digits can be stored in the redial register.
After the main store overflows, a 10 digit
Flrst-In/Flrst-Out register (FIFO) takes over
as buffer. After transmitting the first digit of
the FIFO register, thiS position IS automatically cleared to provide space for the storage of
new data. In thiS way, the total number that
can be transmitted IS unlimited, provided the
keY-in rate IS not excessive. However, If the
FIFO register overflows (more than 10 digitS
In store), further input Will be ignored.

Redial
If the first digit entered IS "REDIAL", R, the
stored number In the redial register Will be
recalled and transmitted. If the current content IS less than 18 digits, new digitS entered
are appended automatically to the redial number. After the 18th digit has been entered, the
FIFO register Will take over as preViously
described In the dialing section.

Extended Redial
The dialed number IS saved in the extended
redial buffer If pushbutton P IS the last key
pressed before the handset IS replaced
Pressing and releaSing pushbutton P, followed by pressing and releaSing R, Will cause
the extended redial register to be recalled
and transmitted In the same manner as by

Table 1. Repertory Number Organization
PCD8570 ADDRESS
A2

A1

AD

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

PCD3341

KEYBOARD DIGIT(S)
Without EKB
10
30
50
70
90

to
to
to
to
to

29
49
69
89
99

00 to 09

6-49

With EKB
00
20
40
60
80

to
to
to
to
to

19
39
59
79
99

M1 to M10

II

Preliminary Specification

Signetics Linear Products

CMOS Repertory Telephone Set Controller

redial. If fewer than 18 digits are contained In
the extended redial register, digits can be
added until the total content IS 18. After the
18th digit the FIFO register will take over as
before. The onginal number IS not affected by
the new digits.

Direct Call/Emergency Call

PCD3341

Table 2. Display Indications
PROCEDURE

KEY PROCEDURE

Programming automatic
access pauses after access
digits

PROOR9

DISPLAY INDICATION

Pr-00-9

Dialing

004627530

00-4627530

Redial

R

r - 00-4627530

Extended redial
programming
dialing

004627530
PR

00-4627530P
Pr - 00-4627530

"Programmed" IS achieved by lifting the
handset, depressing the P pushbutton with
the key In the OFF position, then turning the
key sWitch to the ON position (diode option
ON). The reqUIred telephone number IS now
entered. Pushbutton P can now be released
and the handset replaced.

Emergency redial
programming
dialing

N/D OFF, P, N/D ON (+ TN)
N/D ON any key

PH-00-4627530
H - 00-4627530

Repertory
programming
dialing

P12004627530
P12

P12-00-4627530
P12 - 00-4627530

After programming, the key sWitch can remain
in the ON position (activating emergency
call), or be switched off (normal mode). If the
key switch IS In the ON pOSition, emergency
calling IS possible by removing the handset
and pressing any pushbutton.

Repertory with extended
keyboard
programming
dialing

PM1004627530
M1

PM1-00-4627530
M 1 - 00-4627530

Note pad programming

PP0080808P

7530PPOO-808080P

Note pad dialing

PR

00-808080

Error

Incorrect key procedure

-

This IS a diode option usually operated by a
turn key switch. If set, the programmed number will be dialed by pressing any key. In the
normal mode, the turn key sWitch IS positioned OFF, with the diode opliOn OFF.

Repertory Dialing
The PCD3341 has an on-chip CMOS RAM to
store up to ten 18 digit numbers, and can be
extended up to 100 (110) numbers uSing
CMOS RAMs with 2-line senal Interface. The
CirCUit automatically checks the number of
external RAMs If no external RAM IS connected, the on-chip repertory IS limited to 10
numbers. In thiS application the standard
keypad (0 to 9) and one digit address can be
used. With the diode option EKB (expanded
keyboard) ON, the extended keypad matrix
(M1 to M10) can be used to access the onchip repertory. If external RAMs are connected, the capacity of the repertory can be
Increased up to 100 (110) numbers. In this
application, the standard keypad (0 to 9),
and/or the extended keypad (M1 to M10),
can be used to access the repertory (see
Table 1).
Programming IS possible only after the handset IS lifted and no pushbutton IS operated
before P. Programming IS achieved by pushbutton P being continually depressed, enterIng the repertory address of one or two digits,
followed by the number (including access
digits), then releaSing pushbutton P. The
deSignated telephone number, including access digits, IS dialed after pressing pushbut-

December 1988

NOTES:
Where: TN = Telephone number

P = Depress and release pushbutton P

15 = Depress pushbutton P continually dunng programming
R = Depress and release pushbutton R

ton P followed by the address. With the
extended keypad, a Single address pushbutton IS reqUIred. After transmiSSion of the
repertory sequence, it IS pOSSible to manually
enter additional digits (see Redial).

Successive Repertory Dialing
During a Call (Chain Dialing)
It IS possible to dial more than one repertory
number dunng one Single telephone call. The
following procedures are possible:
• Redial, extended redial, or a repertory
number followed by new digits
• Repertory number followed by one or
more repertory numbers
• Normal dial, redial or extended redial,
followed by one or more repertory
numbers

Note Pad
Note pad prOVides the facility to store a
number dunng the conversation mode Without

6-50

dialing and muting. ThiS number Will be stored
In the extended redial register and recalled
With the extended redial procedure. The programming procedure IS as follows:
•
•
•
•

Depress and release pushbutton P
Depress and release pushbutton P
Enter the telephone number
Depress and release pushbutton P

If a wrong number is entered, correction is
achieved by restarting the programming procedure.
A bUilt-in memory clear faCilitates resetting of
the autodlal RAM after servicing, maintenance or telephone set delivery. The procedure IS as follows:
• Hook-on, depress and keep depressed
keys 2, 5, 8, and 0
• Hook-off, release keys 2, 5, 8, and 0

Signetics Linear Products

Preliminary Specification

CMOS Repertory Telephone Set Controller

SET

-

S

L
APO

HOLD

-

RESET

L
SET
DIAUNG TONE
RECOGNIZER
RESET

PCD3341

PCD3341

J

DIAUNG
TONE
8010510$

Figure 1. Automatic Variation of Length of an Access Pause Under Control of a
Dialing Tone Recognizer

Ml M2

P

e

M3 M4

C

M5 M6

0

#

D

M7 M8

FL

R

AP

M9 M10

hSTANDARD KEY

KEYBOARD

DIODE
OPTIONS

k

OFF

~
DIODE OPTION KEY

Figure 2. Keyboard Organization

December 1988

6-51

•

Preliminary Specification

Signetics Linear Products

PCD3341

CMOS Repertory Telephone Set Controller

HANDSET

CE

CLOCK

HANDSET

~~_D_____________________________________________R_~-;~

-

u

FLASH

~

~

KEYBOARD
ENTRY

r-t.q ;;:I¢"1

I
I

1t~
--jtM--jt.r-

DP

I

Mt

M3

I
DTMF

I

f-I

I

PULSE
DlAUNG

~I~I
CONVERSATION MODE

r.I

I
I
tFL

I

TIME

s TANDBY

OUT

[7

r--;--

I

!--

Mt

I

~i

iii

l-II

I
I

DP

I
I
113

~TONE2~tH

tH

TONE 3

CONVERSATION MODE

I

~tH
TONE 1

Figure 3. Pulse Dialing; DTMF Dialing

December 1988

6-52

I t,,~

~

STANDBY

Preliminary Specification

Signetics Linear Products

PCD3341

CMOS Repertory Telephone Set Controller

KEYBOARD

ENTRY

KEY

Lfl~

I

rmJ

---FREE-±--~-IE==~.-I:.=====--KEY-IN-PU-T-ACC-EPTEO------

~---------------~FREE

_-_-_-.....11-.:IE-:.-.:I..

..

Figure 4. Keyboard Entry With Noise Debounced

KEYR

n
I

----------------------~ ~--------

DP-nl}-----l1Il
I

I

I

I

rlllU

~~~~~, .I~.~, .I.~.-~
lAP

Figure 5. Access Pause With Reset BY, Internal 3s Timer, Key R, Tone Recognizer

December 1988

6-53

•

Signetics linear Products

Preliminary Specification

CMOS Repertory Telephone Set Controller

PCD3341

DIFII
BATTERY
SUPPl.Y

+
SUPPLY

voo

CE
GROUND

v..
u.

~
RESET

SOA

iii

=1

PC0334'

r------ -- ------,

U2

U3
DP

6

5

4

3

I

I

I
I
I
I
I

I
I
I
I
I

I

ROWS
2

I

LINE
IIIIEAAUP11!R

I

I

I
I
I
I
IL ________________ I

OAFLASH

OUTPUT

~

Figure 6. PCD3341 in Combination With PCD3312 (DTMF Dialer), PCD8570 (2k RAM) and PCF (Display Drivers)

December 1988

6-54

PCD3343

Signetics

CMOS Microcontroller for
Telephone Sets
Product Specification

Linear Products

DESCRIPTION

PIN CONFIGURATION

The PCD3343 is a single-chip 8-bit microcontroller fabricated in CMOS. It has
special on-chip features for application
in telephone sets. The device is maskprogrammable, designed to provide telephone dialing facilities such as redial,
repertory dial, emergency call, keyboard
scan, and pulse dial and/or DTMF dial
via dedicated peripheral.

FEATURES
• 8-blt CPU, ROM, RAM, I/O In a
single 28-lead DIP or SO package
• 3K ROM bytes
• 224 RAM bytes
• 20 quasi-bidirectional I/O port
lines
• Two test inputs: one of which Is
also the external Interrupt input
(CE/TO)
• Single-level vectored interrupts:
external, timer/event counter,
serial I/O
• Serial I/O which can be used in
bus systems with more than one
master (serial I/O data via an
existing port line and clock via a
dedicated line)
.8-bit programmable timer/event
counter
• Over 80 Instructions (based on
MAB8048, MAB8400 and
PCF8500)
• All Instructions 1 or 2 cycles
• Clock frequency 100kHz to
10MHz
• Single supply voltage from 1.8V
to 6V
• Low standby voltage and current
• STOP and IDLE mode
• On-chlp oscillator with output
drive capability for peripherals
(e.g., PCD3312 DTMF generator)
• Configuration of all I/O port lines
Individually selected by mask:
pull-up, open-drain or push-pull
• Power-on reset circuit and low
supply voltage detection

June 10, 1988

PIN CONFIGURATION

PCF84COOB "Piggy-back" Version
Top Pinning

D, N Package

TOP VIEW
C0114808

PIN NO.

3

4-11
lOP VIEW

12

CD11470S

PIN NO.

SYMBOL

14,22

1.26-28
10-3.25.
24. 21. 23. 2
11-13.15-19
20

Vss
Veo

DESCRIPTION

Ground
Power supply

AO-A12 Address outputs
00-07

i'SEI'I

13

0818
Program store enable

NOTES:
1 RAM capacrty of PCF8500B IS 256 by1es
2. Access time for ROMS/EPAOMS to be below
3

~I~ ~~f"g~ IS on the PCF84COOB,

14
15

Inverted

and labeled iiii'i'/TO

• Reset state of all ports
individually selected by mask
• Operating temperature range: -25
to +70·C

16
17

18-25

APPLICATIONS
• Feature phones
• Pay telephones
• Control application with low
voltage/current requirements

SYMBOL

DESCRIPTION

SCLK

Clock: Bidirectional clock for sana!
1/0
POO - P07 PORT 0: 8-blt quaslMbldlrectlonal
1/0 port
CE/TO
Interrupt/Test 0: External Interrupt

inPut {senSltlve to positive-going
edge)/test Input pin, when used as
a test Input directly tested by
conditional branch Instructions JTO
and JNTO
Tl
Test 1: Test Input pin, directly
tested by conddlonal branch
InstructiOns JT1 and JNT1 T1 also
functIOnS as an Input to the a-bit
bmer/event counter, uSing the
STAT CNT InstructIOn
Ground: Ctrcud ground potential
VS.
Cryatal Input: Connection to bmlng
XTAl1
component (crystal) which
detemllnes the frequency of the
Internal OSCillator, also the Input for
an external clock source
Connection to the other Side of
XTAL2
the tlrmng component
RESET
Reset Input Used to Initlahze the
processor (active High), or output
of power-on-reset clrcud
P10-P17 Port 1: 8-b!t quasi-bidirectIOnal 110

port
26.

27, 1,
2
28

P20 - P23 Port 2: 4-bit quasl-bldlrectlOnal 110
port. P23 IS the senal data Input!
Voo

output In senal 110 mode
Power supply: 1 8V to 6V

NOTE:
CE/TO IS labeled iNT ITO on the PCF84COOB and
has Inverted polanty

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP (SOT-ll7D)

-25°C to + 70·C

PCD3343PN

28-Pin Plastic SO Package
(80·28, SOT·136A)

- 25°C to + 70·C

PCD3343TD

6-55

853·0620 93527

•

Product Specification

Signetics Linear Products

PCD3343

CMOS Microcontroller for Telephone Sets

BLOCK DIAGRAM

...

r- - - -

.----;:O:""i2-------,

AO-A12- - - - - - - ,

I

i

1

00-07

1 ~
1 OXAU;

1
I

1

I DxWii

I
I

I
I
I

iiiiiiii
1
1L

00

___ _

13

_______

fJIIEN

J1

DO-D7

I
:

1L _ _ _
BD01731S

Replacement of Dotted Part In Block Diagram for the
PCF84COOT ROM-less Version

June 10, 1988

Replacement of Dotted Part In Block Diagram for the
PCF84COOB "Piggy-back" Version

6-56

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

Connection of EPROM to 'Piggy-back' Package PCF8500B
A
POO~P07

AO-A12

"

"

A

"-

AO-A12
"

-"-

(ADDRESS BUS)

A

P10-P17

...
00-07

00-01

(DATA BUS)

"

"

-V

A
P20-P23

EPROM

"

MAX.8k
BYTES

CE

"-

"
SCLK

PSEN

Tl

PCF8500 B

BOND OUT CHIP

•

INT/TO

RESET

XTAL1

•

Vss Voo

XTAl2

•

voo
vss

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VDO

Supply voltage (Pin 28)

VI

All input voltages

±II, ±Io

DC current into any input or output

PTOT

RATING

UNIT

-0.8 to +8

V

0.8 to VDO + 0.8

V

10

mA

Total power dissipaliOn 1

500

mW

Po
Po

Power dissipation per output
except P23, SCLK
P23, SCLK

50
180

mW
mW

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range

-25 to +70

·C

TJ

Operating junction temperature

125

·C

NOTES:
1. Thermal reSistance ~unctlon to ambient)
for SOT-117D OJA max. = 120·C/W
for SOT-135A OJA max. = 60·C/W.
for SOT-136A OJA max. = 150·C/W

June 10, 1988

6-57

•

Signetics Unear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

DC ELECTRICAL CHARACTERISTICS Voo = 2 75 to 6V; Vss = OV, TA = -25·C to + 70·C; all voltages with respect to Vss;
f = 3.58MHz with Rs = 50n, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
MIn

Voo
Voo

Supply voltage
operating (see Figure 20)
STOP mode for RAM retention

Typ

1.8
1.0

Max
6
6

V
V

Supply current
operatmg
at Voo = 3V (see Figure 21)
IDLE mode
at Voo = 3V (see Figure 22)
STOP mode (see Figure 23)1
at Voo = 1.BV; TA = 25·C
at Voo =1.8V; TA=55·C
at Voo = 1.8V; TA = 70·C

600

jJ.A

300

jJ.A

VRESET

SWitching level

1.3

V

IOL

Sink current
at Voo> VRESET

7

jJ.A

100
100
100

1.2

2.5
5
10

jJ.A
jJ.A
p.A

Reset 110

Inputs
VIL

Input voltage Low

0

0.3Voo

V

VIH

Input voltage High

0.7Voo

Voo

V

± IlL

Input leakage current
at Vss < V, < Voo

1

jJ.A

0.05

V

Outputs
VOL

Output voltage Low
at VI = Vss or Voo; 1101 < 1jJ.A

IOL
IOL

Output sink current Low
at Voo = 3V; Vo = OAV except P23/SDA, SCLK (see Figure 24)
P23/SDA, SCLK (see Figure 25)

-IOH
-IOH

Pull-up output source current High (see Figure 26)
at Voo = 3V; Vo = 0.9Voo
at Voo = 3V; Vo = Vss

-IOH

Push-pull output source current High
at Voo = 3V; Vo = Voo - 0.4V

075
1.5

1.5

rnA
rnA

25
200
075

1.5

jJ.A
jJ.A

rnA

NOTE:
1 Crystal connected between XTAL 1 and XTAl 2, SCl and SOA pulled to VDD via 56kU resistor, CE and T1 at Vss

AC ELECTRICAL CHARACTERISTICS Rise and fall times between 10 and 90% levels, CL = 50pF
SYMBOL

At 70·e Maximum Value

PARAMETER

UNIT

Voo

Supply voltage

1.8

3.0

6.0

V

tF

Fall time

200

100

70

ns

tR

Rise time

200

100

80

ns

June 10, 1988

6-58

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

FUNCTIONAL DESCRIPTION
Bond-Out Version PCF84COOB
The PCF84COOB IS a microcontroller that
contains no on-board ROM, but has all address and data lines brought out to access an
external ROM or EPROM. This version has
more pins than the PCD3343 With on-board
ROM. The RAM has 256 bytes. It can address 8k bytes of ROM.

'Piggy-Back' Version
PCF84COOB
The PCF84COOB IS a special package that
has standard pinning to the bottom which
facilitates Insertion as a mask-programmed
device. An EPROM can be mounted on top in
an additional socket. The total package
height is greater than the standard DI P package. The RAM has 256 bytes and can also
address 8k bytes of program memory.

PCD3343

register Instructions. Ease of addressing, and
a minimum requirement of instruction bytes to
manipulate their contents, makes these locations suitable for storing frequently addressed
intermediate results. This bank of registers
can be selected by the SEL RBO instruction.

• Location 3: contains the first byte of an
external interrupt service subroutine,
• Location 5: contains the first byte of a
serial 1/0 Interrupt service subroutine,
• Location 7: contains the first byte of a
timerI event counter Interrupt service
subroutine.
Program memory IS arranged in banks of 2k
bytes, which are selected by SEL MB Instructions. The program memory IS further diVided
Into location 'pages', each of 256 bytes. This
latter diviSion applies only for conditional
branches. Memory bank boundanes can be
crossed only by using the unconditional
branch instructions after the appropriate
memory bank has been selected. A CALL
Instruction can transfer control to a subroutine on any 'page'; RET and RETR instructions can transfer control from a subroutine
back to the main program.

Program Memory PCD3343
The program memory consists of 3072 bytes
(8-bit words), in a read-only memory (ROM).
Each 10caUon is directly addressable by the
program counter. The memory is mask-programmed at the factory. Figure 1 shows the
program memory map.
Four program memory locations are of special importance:
• Location 0: contains the first instruction
to be executed after the processor is
initialized (RESET),

'
)
H

Data Memory PCD3343
Data memory consists of 224 bytes (8-bit
words), random-access data memory (RAM).
All locations are indirectly addressable using
RAM pointer registers; up to 16 deSignated
locations are directly addressable. Memory
also includes an 8-level program counter
stack addressed by a 3-bit stack pointer.
Figure 2 shows the data memory map.

Working Registers
Locations 0 to 7 are designated as working
registers, directly addressable by the direct

Executing the select register bank instruction
SEL RB1 designates locations 24 to 31 as
working registers Instead of locations 0 to 7,
and they are then directly addressable. This
second bank of working registers may be
used as an extension of the first or reserved
for use during interrupt service subroutines,
saving the first bank for use in the main
program. If the second bank is not used,
locations 24 to 31 may serve as general
purpose RAM.
The first locations of each bank contain the
RAM pointer registers RO, Rl, RO', and R1',
which indirectly address all RAM locations.
All RAM locations make efficient program
loop counters when used With the decrement
register and test instruction DJNZ.

Program Counter Stack
Locations 8 to 23 may be designated as an 8level program counter stack (2 locations per
level), or as general purpose RAM. The
program counter stack (Figure 3) enables the
processor to keep track of the return addresses and status generated by interrupts or
CALL instructions by storing the contents of
the program counter prior to servicing the
subroutine. A 3-bIt stack pointer determines

] 11

,---------------------------------, r---------------------------------,
PCF8500B
3072

SEL.'

....

PCD3343

t

-+

*7

,

2231_usER-l
RAM
~

~

ADORESSED
_EC1"IY
THROUGH POINT1!RS
RO, R1, RO', R,'

f

&ELM. .

::I---~

=~I---~ (1) THE PROGRAM

BANK 1

WORKING
REGISTERS

MEMORY OF PCf8500
FAOll4 Kio 8K CAN BE
USED VIA SEL MB2 AND
SEL . 3 INSTRUCTIONS

axa

2S
:14
23

R,'
RO'

"'1

DIRECTLY
ADDRESSAIILE
WHEN BANK,

_JCTm

eLEVEL

~f ~K .~1>

I

~~~;

USER RAM

18xe

LOCATION 7: nMERJCOUNTER INTERRUPT VECTOR
LOCATION 5: SERIAL 110 INTERRUPT VECTOR

BANK G
WORKING

LOCATION a: EXTERNAL INTERRUPT VECTOR

REGISTERS

axe

WHEN_KG

E::i:!E:3 _SE,CTEO

LOCATION 0: RESET VECTOR

Figure 1_ Program Memory Map
June 10, 1988

"1

DIRECTLY
ADDRESSAIILE

Figure 2. Data Memory Map

6-59

I
•

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

which of the eight register pairs of the program counter stack will be loaded with the
next generated return address.

STACK
POINTER

I

22

21
110

20

I.
101

18
17
100

The value of the saved contents of the
program counter IS different for an interrupt
CALL compared to a normal CALL to subroutine. With an Interrupt CALL, the program
counter return address IS saved; with a subroutine CALL, the saved program counter
value IS one less than the program counter
return address.

I.

!

15
011

I

14
13

At the end of a subroutine, which is signalled
by a return instruction (RET or RETR), the
stack pOinter decrements by one and the
contents of the register pair on top of the
stack are transferred to the program counter.
The saved PSW bits are transferred to the
PSW only by the RETR instruction.

Nesting of subroutines Within subroutines can
continue up to 8 times without overflOWing the
stack. If overflow does occur, the deepest
address stored (locations 8 and 9) will be
overwritten and lost since the stack pOinter
overflows from 111 to 000. It also underflows
from 000 to 111.

R23

111

The stack pointer, when InJtJahzed to 000 by
RESET, points to RAM locations 8 and 9. On
the first subroutine CALL or interrupt, the
contents of the program counter and bits 4, 6,
and 7 of the program status word (PSW) are
transferred to locations 8 and 9. The stack
pointer Increments by one and pOints to
locations 10 and 11 ready for another CALL.
Because an address may be up to 13 bits
long, two bytes must be used to store each
address.

If not all 8 levels of subroulJne and Interrupt
nesting are used, the unused portion of the
stack may be used as any other Indirectly
addressable RAM 10catJons. Possible locations from 32 to 223 may be used for storage
of program variables or data.

PCD3343

010

12
11
001
10
000

IpC,o I peg I PCs

psw,lpswJ pc 12jPsw. PC"
PC, I pc. I pcsj PC. pe3

I PC2 I PC 1 I pe o

MSB

R8

LSB

Figure 3. Program Counter Stack

IDLE and STOP Modes
IDLE Mode
When the microcontroller enters the IDLE
mode via the IDLE Instruction (H'01 '), the
OSCillator, tlmerlcounter, and serial 1/0 are
kept running. The mlcrocontroller eXits from
the IDLE mode by one of three Interrupts "
they are enabled, or by activalJng a RESET. If
the interrupt is not enabled the processor Will
remain In the IDLE mode. An acllve signal on
the RESET pin restarts the microcontroller
and a normal RESET sequence is executed
(see Figure 4).
An active signal coming from an enabled
interrupt causes the execution of the normal
interrupt routine since normal Interrupt scanning is sllil being carned out A Low-to-High
transition on the external Interrupt pin (CEI
TO) reactivates the microcontroller. A High

level applied to CEITO will reactivate the
microcontroller only in the STOP mode. Thus,
If CElTO was High before the microcontroller
entered the IDLE mode, It must go LOW
before the mlcrocontroller can be reactivated
(see Figure 5).
Wake-up from the IDLE mode IS ensured
when CEITO IS Low for 4CP (clock periods)
followed by a High for 7CP. After the initial
forced CALL H'003' operatJon (60CP) the
program conlJnues With the external interrupt
service routine.

STOP Mode
The microcontroller enters the STOP mode
by the STOP instruction (H'22'). The OSCillator
is sWitched off. The Internal status of the
CPU, RAM contents, and the state of 1/0
ports are not affected. The microcontroller
can be brought out of the STOP mode by an
PROGRAM
COUNTER=.

~

~I

NORMAL MOOE
+1
I ( 10LE MODE
NORMAL MODE
PROGRAMFLOW----____________+.___________·fl--------------------------~·--~~~~::---

OSCILLATOR

RESET

111111111111111111111111111111111111111111111111111111III (fllllllllllllllllllllllllllllll!!!!!I!I!!I!!!!1111111III illlllllllll11111111111111111111111

n

I

-----_--""'1 :;ES r--cL~Kj

--------------------------..((ff-

J.I.8

PERIODS

Figure 4. Exit from IDLE Mode via a RESET
June 10, 1988

6-60

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

~
PROGRAM FLOW

OSCILLATOR

NORMAL MODE

PCD3343

IOLEMOOE------i~ CO~fA"'OO3

tlLI-______

+ _____tl-_;,;N;:,OR;.;;MA;;;;L:;;M;;;O:;;D;;;;E;....._

I

111111111111111111111111111111111111111111111111111111IIIII(~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII111111111111111111111111111111111111111111111

II~~

-rIA

PERIODS PERIODS

PERIODS

Figure 5. Exit from IDLE via an Interrupt

(ST

P)

NORMAL MODE

PROGRAMFLDW

PROGRAM COUNTER =

OOROO3

~I

STOP MODE

NORMAL MODE

-------+-1-----irff-----------4.-------

OSCILLATOR

•

RESET

OR

Figure 6. Entering and Exiting the STOP Mode

active Signal at the external Interrupt Input or
by an external RESET signal. When one of
these two Signals IS applied, an internal delay
of 1866CP IS proVided to ensure that all
Internal clocks are operating correctly before
restart (see Figure 6).
If the microcontroller eXits from the STOP
mode by activating RESET, a normal RESET
sequence IS executed.
If the mlcrocontroller eXits the STOP mode by
pulling the external Interrupt Input pin High, an
Interrupt sequence is executed only if the
external interrupt IS enabled. In thiS event the
mlcrocontroller resumes the normal program
sequence after returning from the Interrupt
routine, as In the normal mode. If the Interrupt
is not enabled, It continues the normal pro·

June 10, 1988

gram sequence, executing the instruction fol·
lOWing the STOP instruction.

• Port 1: Parallel port of 8 lines (Pl0 to
P17).

The microcontroller IS restarted by a High
level applied at the CE/TO pin, and not by a
low·to·Hlgh tranSition as In a normal Interrupt
mechanism

• Port 2: Parallel port of 4 lines (P20 to
P23).

When the CE/TO level is active dUring the
STOP instruction, no STOP IS executed.
A High level on the external Interrupt Input of
at least IllS Will cause the microcontroller to
eXit the STOP mode

I/O Facilities
The PCD3343 family has 23 110 lines ar·
ranged as:
• Port 0: Parallel port of 8 lines (POO to
P07).

6-61

• SClK: Serial 110 consisting of a data
line shared with a parallel port line
(P23) and a separate clock line SClK.

• CE/TO: External Interrupt and test
Input. When used as a test input can
be directly tested by conditional branch
Instructions JTO and JNTO.
• Tl : Test Input which can alter program
sequences when tested by conditional
jump instructions JTl and JNTI. Tl
also functions as an input to the 8·bit
timer I event counter.

Product Specification

Signetics Linear Products

CMOS Microcontroller for Telephone Sets

PCD3343

~1·~---------CYCLE1----------~~~I~·~----------CYCLE2----------~·~I
~~~~I_'~__~~__~~~~__L-~__4-'O~I_'~__~~__~~~~I__L-~__.I_W
__I

I
I

I

-yo;;;:y~

I

I
I
I

k:::

PO,Pl,P2 _ _ _ _ _ _ _ _-JXr-----D-ii.-:rA-O-UT-----""'X

ANL
0RL

----

ALL PORTS FOR IN AND OUTlINSTRUCTIONS

F'9ure 7 TIming Diagram of all pons on IN and OUTL Instructions,
10< ANL and ORl Instruc!oc:ms, the Ports Change On the T.me Slot 7 01 Cycle 2

Parallel Ports
All parallel ports can be used as outputs or
inputs. Their structure IS quasI-bidirectional.
Output data written to a port IS latched and
remains unchanged until reWritten, Input data
IS not latched and so must be present until
read by an Input Instruction.
Input lines are fully CMOS compatible. Output
lines can drive one LSTTL or CMOS load.
Instructions, for ANL and ORL Instructions,
the Ports Change on the Time Slot 7 of Cycle
2.
Figure 8 shows the quasI-bidirectional I/O
interface With push-pull output and sWitched
pull-up current source.
Each line IS pulled up to Voo via a constant
current source (TR4), which IS enabled via
TR3 whenever one of the two output latches
contains a logiC 1 ThiS current proVides
suffiCient source current for a TTL High level,
yet can be pulled Low by an external CMOS
deVice, thus allOWing the same pin to be used
for both Input and output.

June 10, 1988

When a logic 1 is written to the line for the
first time (MO = 1, SO = 0), TR2 IS switched
on for the duration of the internal write pulse
(one OSCillator period), to provide a fast transition from logic 0 to logic 1. Subsequent
writing of a logiC 1 to the port lines will not
switch TR2 on. This prevents unnecessary
current through external components connected to the port lines of the same port
which might be in the Input mode and also
connected to ground.
When a logiC 0 is written to the line, TR3
sWitches off the current source. Current Sinking capability is provided by TR1, which is
now switched on. When used as an input, a
logic 1 must first be written to the line;
otherwise TR1 will remain low impedance.
In telephone applications thiS switched pullup source may not be suffiCient. Therefore,
the PCD3343 offers the possibility to select
Individually 19 of the 20 parallel port pins (not
P23), by the following mask options:
Option 1: STANDARD PORT; quasi-bidirectional I/O with switched pull-up
current source of 100l1A (typ.) and

6-62

P-channel booster transistor TR2
(1.5mA). TR2 is only active during
1 clock cycle (0.28I1S at 3.58MHz).
Option 2: OPEN-DRAIN; quasi-bidirectional
I/O with only an N-channel open
drain output. Application as an output requires connection of an external pull-up resistor (Figure 9).
Option 3: PUSH-PULL OUTPUT; drive capability of the output will be 1.5mA
(typ.) at Voo = 3V in both polarities.
To avoid a large current flowing
through the output transistors during the Input mode, these push-pull
pinS must only be used as outputs
(Figure 10).
Also, individual mask selection of the RESET
state of these port pins can be achieved by
appending the following options Sand R to
options 1, 2, or 3.
Option S-SET:

after RESET this pin will
be initialized to High.

Option R-RESET:

after RESET thiS pin Will
be initialized to Low.

Signetics Unear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

WRnE~o---------~---------,

DATA BUS o--...------i~
100pA
(TYP.)

+----------40_..--<> ~c:.,PORT
RESET

ORLJANL

IN

""""',s

Figure 8. Standard Output with Switched Pull·up Current Source

WRnE~o---------~----------,

SET

DATA BUS O---_----+~D
~-£)OO--~D

MQt-"?""+-I D

sa

•

iml-+--I

DRLJANL

IN

Figure 9. Open·Drain Output

June 10, 1988

6-63

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

WRITE PULSE

Voo
SET

DATA BUS

0

sa
100;.tA
(TYP.)

Mcl

0

0

sa

1/0 PORT
LINE

RESET

ORL/ANt

IN

Figure 10. Push-pull Output
Serial 1/0 (510)
The PCD3343 has an on-chip serial 1/0
interface. This SIO interface is a versatile
feature in an intelligent telephone set. as
shown In application diagram Figure 30.
In this apphcatlon the SIO is used to commu·
nlcate with the different peripherals, such as:
• DTMF generator (PCD3312)
• LCD drivers (PCF8577)
• External RAM (PCD8571)
• Clock calendar (PCB8573)
No extra hardware is required for decoding,
addressing, and data processing.
Whereas a normal microcontroller must regularly monitor the senal data bus for the
presence of data, the serial 110 interface
detects, receives, and converts the serial
data stream into parallel format without interrupting the execution of the current program.
An interrupt is sent to the PCD3343 only
when a complete byte is received. It then
reads the data by1e In one Instruction. Similarly, during transmission the senalllO interface
performs parallel to serial conversion and
subsequent serial output of the data. The
mlcrocontroller is only Interrupted in the execution of its programmed tasks when a complete byte has been transmitted.
The design of the PCD3343 serial 1/0 system
allows any number of devices from PCF8500
family (clips) to be connected via the two-hne
senal bus. The ability of any devices to
communicate, Without Interrupting the operation of any other devices on the bus, IS an
outstanding attnbute of the system. This IS
achieved by allocating a specific 7-bit address to each device and providing a system
whereby a device reacts only to a message
June 10, 1988

prefixed With its own address or the 'general
CALL' address. Address recognition is performed by the interface hardware so that
operation of the microcontroller need only be
interrupted when a valid address has been
received. This saves significant processing
time and memory space compared With a
conventional mlcrocontroller employing a
software serial interface. When the addressing facility IS not reqUIred, for Instance, in a
system With only two mlcrocontrollers, direct
data transfer without addressing can be performed. In multi-master systems, an automatically invoked arbitration procedure prevents
two or more devices from continuing simultaneous transmission.
In NORMAL (running) and IDLE mode, the
serial 1/0 logic remainS active; its Internal
system clock will be sWitched off when there
is no activity on the serial bus.
After execution of the STOP instruction, the
oscillator of the PCD3343 IS sWitched off.
This means that the serial 1/0 logic will
remain in the state It was at the occurrence of
the STOP instructions. To avoid "bus block"
problems and to assure correct start-up of the
bus aiter eXit from the STOP mode, the user
should disable the senal logic (ESO = 0) prior
to the execution of the STOP instruction. ThiS
must be carried out only when the PCD3343
has finished a serial data transfer.
Serial I/O Interface
Figure 11 shows the serial 1/0 Interface. The
clock line of the serial bus has exclusive use
of Pin 3 (SCLK) while the data line shares Pin
2 (serial data) With the 1/0 line P23 of port 2.
When the serial 1/0 IS enabled, P23 is disabled as a parallel port line; (P23 and SCLK
only open drain).

6-64

The microcontroller and interface communicate via the internal microcontroller bus and
the Serial Interrupt Request line. Data and
information controlling the operation of the
interface are stored in four registers:
• Data shift register (SO)
• Senal 1/0 interface status word (S1)
• Senal clock control word (S2)
• Address register
Data Shift Register (SO)
Register SO converts serial data to parallel
format and vice versa. A pending interrupt is
generated only aiter a complete byte has
been transmitted, or after a complete data
by1e, specific address, or 'general CALL'
address has been received. The most significant bit is transmitted first.
Serial 1/0 Interface Status Word (51)
Register 81 provides information concerning
the state of the Interface and stores information from the microcontroller. Bits 0 to 3 are
duplicated: control bits In these positions can
only be written by the mlcrocontroller, while
interface bits can only be read.
MST and TRX (See Table1)
These bits determine the operating mode of
the serial 1/0 interface.

Table 1. Operating Modes of
the Serial 110 Interface
MST

TRX

0
1
0
1

0
0
1
1

OPERATING MODE
Slave receiver
Master receiver
Slave transmitter
Master transmitter

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

BB: Bus Busy.
This is the flag which Indicates the status of
the bus.
PIN: Pending Interrupt Not
PIN = '0' indicates the presence of a pend·
ing interrupt, which will cause a Senal Interrupt Request when the serial Interrupt mechanism is enabled.
ESO: Enable Serial Output
The ESO flag enables/disables the serial 110
interface: ESO = '1' enables, ESO = '0'
disables. ESO can only be written by software.
BCO, BCl, and BC2
Bits BCO, BC1, and BC2 IndIcate the number
of bits receIved or transmitted in a data
stream. These bits can only be written by
software.
AL: Arbitration Lost
The arbitratIon lost flag is set by hardware
when the serial 110 Interface, as master
transmitter, loses a bus arbitration procedure.

Table 2. 510 Clock Pulse Frequency Control When Using a
3.S8MHz Crystal
HEXADECIMAL 520·524
CODE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E

ADO: Address Zero
This flag is set by hardware after detection of
the 'general CALL' address when the interface is operating in the address recognItion

mode.

IF

DIVISOR

FSCLK (kHz) (APPROXIMATE)
Not allowed

39
45
51
63
75
87
99
123
147
171
195
243
291
339
387
483
579
675
771
963
1155
1347
1539
1923
2307
2691
3075
3843
4611
5379
6147

F
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
lE

AAS: Addrelled As Slave
This flag is set by hardware when the interface detects either its own specific address or
the 'general CALL' address as the fIrst by1e
of a transfer and the interface has been
programmed to operate in the address recognition mode.

PCD3343

92
80
70
57
48
41
36
29
24
21
18
15
12
11
9.2
7.4
6.2
5.3
4.6
3.7
3.1
2.7
2.3
1.9
1.6
1.3
1.2
0.93
0.78
0.67
0.58

LRB: Last Received Bit
This contaIns either the last data bit received
or, for a transmItting device In the acknowledgement mode, the acknowledgement signal from the receivIng device.
Bits AL, MS, ADO, and LRB can only be read
by software.
Serial Clock Control Word (52)
Bits 0 to 4 of the clock control register S2 are
used to set the frequency of the serial clock
Signal. When a 3.58MHz crystal IS used, the
frequency of the senal clock can be varied
between 92kHz and 580Hz (see Table 2). An

June 10, 1988

asymmetrical clock WIth a Hlgh-to-Low ratIo
of 3:1 can be generated uSIng BIt 5. The
asymmetncal clock allows a mlcrocontroller
more tIme per clock period for sampling the
data line, makIng the timIng of th,s actIon less
crItical. Bot 6 can be used to actIvate the
acknowledge mode of the serial 110. S2 IS a
wnte only regIster.
Address Register
The address regIster contains the 7-bIt address back-up latches and the bIt (ALS) used
to enable/ dIsable the address recognotoon
mode. The address regIster can be wntten

6-65

uSIng the MOV SO, A and MOV SO, #data
InstructIons, but only when ESO = '0' .
Serial 1/0 Interrupt Logic
An EN SI instructIon enables and a DIS SI
instructIon dIsables the interrupt logic. When
the logic is enabled, a pendIng Interrupt
results In a senal 110 interrupt to the processor, causing a CALL to locauon 5 In the ROM.
When dIsabled, the presence of an Interrupt
is stIli Indicated by PI N In S1, allOWIng the
Interrupt to be servIced. However, vectored
interrupt WIll not occur.

•

<-

c:

()

1il

s:

.0

0

en

CD

'"'"

INTREQ

s:

,5"
...,

PC03343
INTERRUPT

LOGIC
ENSI
015S1

ESO

0
0
0

-

en
cO'
OJ

~
!;l
c

"Q
a
a.
(I)

"U

c

()

or

::J

...,

0

SERIAL

OATAI/O
OR I/O P23
OF PORT 2

(!)

...,
-..

DATA
CONTROL

0...,

(PIN 2)

o

.....

(!)
(!)

PIN

LRB

U

=r

0

::J

Cl'l

m

Cl'l

(!)

-

INTERNAL MICROCOMPUTER BUS

en

INITIALIZE ~ RESET
(PIN 17)

(!)
tn

BITO

BIT 7

BITO
WRS2

MST

SClK
(PIN 3)

S1

CLOCK
SYNC

lOGIC

I

TRX

I

BC2

I

BC1 I BCO

AAS

I

ADO

BS I PIN

I

LRB

STATUS REGISTER

CLOCK

CONTROL

SERIAL CLOCK PULSE GENERATOR

INTERNAL CLOCK

~
o
(.,)
Figure 11. Serial 1/0 Interface

(.,)
~

(.,)

~

c
Q.

~
~
o
OJ

Product Specification

Signetics linear Products

PCD3343

CMOS Microcontroller for Telephone Sets

Table 3. Serial 1/0 Addresses for Telephony Peripherals
DESCRIPTION

ADDRESS

TYPE

7

6

5

4

3

2

1

0

PCF8570
PCD8571
PCD3311
PCD3312
PCF8566
PCF8582
PCF8583

1
1
0
0
0
1
1

0
0
1
1
1
0
0

1
1
0
0
1
1
1

0
0
0
D
1
0
0

A2
A2
1
1
1
A2
0

A1
A1
0
0
1
A1
0

AO
AO
AO
AO
0/1
AO
AO

R/W
R/W
R/W
R/W
0
R/W
R/W

PCF8591
PCF8200
PCD8573
PCF8574
PCF8576
PCF8577

1
0
1
0
0
0

0
0
1
0
1
1

0
1
0
1
1
1

1
0
1
1
1
1

A2
0
D
A2
0
0

A1
0
A1
A1
0
1

AO
0
AD
AO
0/1
0/1

R/W
R/W
R/W
R/W
0
D

Interrupts (see Figure 12)
When the external Interrupt IS enabled, a
Low-to-High transition on the CE/W Input
Initiates an external Interrupt subroutine
which causes a CALL to program memory
location 3 follOWing completion of the current
instruction The Interrupt must remain enabled until the Interrupt instruction IS completed. Otherwise, the next Instruction of the
main program Will be executed Senal I/O
Interrupt, when enabled, causes a CALL to
location 5, and a timer/event counter overflow forces a CALL to location 7 when the
timer Interrupt is enabled.
When an interrupt subroutine starts, the contents of the program counter and bots 4, 6,
and 7 of the PSW have been saved In the
program counter stack. Accumulator contents
have to be saved by software. Interrupt acknowledgement can be carried out by software via port pins. All Interrupt subroutines
must reside In memory bank o.

June 10, 1988

Since the Interrupt system IS single level,
once an Interrupt IS detected all further interrupt requests are latched, but Ignored, pendIng a RETR Instruction to re-enable the interrupt logic After executing RETR, the program
continues In the main part, thiS IS Independent
of the occurrence of a second Interrupt dunng
the running of the first routine. If 2 or 3
Interrupts occur simultaneously, their pnonty
IS:

(1) external
(2) senal I/O
(3) timer/event counter
An external Interrupt can be generated by
uSing the timer/counter In the event counter
mode. The counter IS first preset to (H'FF),
then EN TCNTI instruction IS executed A
Low-to-Hlgh transition of the T1 Input Will then
Initiate an Interrupt subroutine and cause a
CALL to location 7.

6-67

2k RAM
1k RAM
DTMF dialer
DTMF dialer
14 LCD driver
256 X 8 EEPROM
256 X 8 RAM with
clock calendar
A/D plus DAC
Speech synthesizer
Clock calendar
8-bot I/O expander
1 4 LCD driver
1 2 LCD driver

On execution of a DIS I Instruction, the
PCD3343 always clears the digital filter/latch
and the External Interrupt Flag.
The Timer Flag (TF) IS reset only when the
JTF or JNTF instruction IS executed or after
RESET.
The Timer Interrupt Flag IS set when timer
overflow occurs, only If the timer Interrupt IS
enabled
The mlcrocontroller Will eXit the IDLE mode
when anyone of the follOWing three Interrupts
IS enabled
• External
• Senal I/O
• Timer/event counter
There IS no Internal pull-up or pull-down
device connected to the external Interrupt
Input (Pin 12) If reqUired, Pin 12 must be
externally connected to a resistor
(R';; 100kn) When the external Interrupt IS
not used, Pin 12 must be connected to Vss

•

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

EN!

S

PCD3343

.nEHRU"
VEC'I'DR
LOGIC

Q

ENABLE
En IN't

FLAG
DIS!

U"

RESET

PIN

RETR
RESET
ENS!

S

Q

ENABLE
SIO!NT.
DlSS!

FLAG

lI"

RESET

CONDITIONAL
JUllPLOGIC
nMER

OVERFLOW

JNTF,JTF
RESET

-

Tc:.----tSENABLEQ
DIS
TCNT!
RESET

IN't

RFLAGij

NOTES:
1 CE/fOi POSItIVe edge fS always latched In the digital filter/latch
2. Correct Interrupt tlllNng IS ensured when CE/TO IS Low for > 4CP followed by Hrgh for> 7CP
3 When the Interrupt-In-progress flag IS set, further Interrupts are latched but Ignored, until RETR IS executed
4. A DIS I Instrucbon always clears a pending external Interrupt

Figure 12. Interrupt Logic

June 10, 1988

6-68

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

Oscillator (see Figure 13)
PCD3343

The 3.58MHz oscIllator can be InhibIted by
the STOP InstructIon under software control.
It IS also Inhibited when a low voltage condItion is present to prevent dIscharge of a weak
back-up battery.
ProvIded the supply voltage
operating range, the oscIllator
ed after a STOP instructIon by
eIther the CE/TO or RESET

INHIBIT

IS wIthIn the
will be restarta High level at
pin.

C2

The oscillator has the output dnve capabIlity
for the DTMF generator (PCD3311/3312) vIa
Pin 16 (XTAL 2). An external clock can be
applied to PIn 15 (XTAL 1). A machIne cycle
consIsts of ten tIme slots, each tIme slot
beIng three oscIllator penods.

J

A.,• s

Figure 13_ Oscillator with Integrated Elements

In telephony applications the 3.58MHz crystal
provIdes an 8.4l.1s machIne cycle. The range
of the clock frequency IS from 100kHz up to a
maxImum whIch IS a functIon of the supply
voltage (see FIgure 20).

XTAL+30
(INTEANAL CLOCK
FAEQUENCY)

Timer/Event Counter (see
Figure 14)

JUMP IF
TIMEAFLAG

'1

An internal 8-bIt up-counter IS provIded. ThIS
can count external events, modul0-32 machIne cycles, or machIne cycles dIrectly. Table 4 gIves the InstructIons that control the
counter and the prescaler, and the functions
performed.
When used as a tImer, the Input to the
counter IS erther the overflow or input of a 5bit prescaler. When used as an event counter, Low-to-Hlgh transitIons on PIn 13 (T1) are
counted. The maxImum rate at which the
counter may be Incremented IS once every
machine cycle (182.6kHz for an 8.4j.tS machine cycle). When the counter overflows, the
tImer flag is set. The flag can be tested and
reset uSIng the JTF Uump If tImer flag = 1) or
JNTF instructIon. Overflow also generates an
Interrupt to the processor via settIng of the
TImer Interrupt Flag when the tlmer/event
counter Interrupt IS enabled.

A • STAAT TIMEA
B • STAAT COUNTEA
C • STOP TIMEA/COUNTEA

Figure 14. Timer/Event Counter

Table 4. Timer/Event Counter Control
TIMER MODE
MODULO-1, MODULO-32 1

FUNCTION
CLEAR
PRESET
START
STOP
TEST
READ2

MOV T,A (A) = 0 or RESET
MOV T,A
STRT T
STOP TCNT or RESET
JTF/JNTF
MOV A,T

Program Status Word (see
Figure 15)

NOTES:

The program status word (PSW) IS an 8-bIt
word (1 byte) In the CPU which stores Information about the current status of the mlcrocontroller.

2 READ does not dIsturb the counbng process

The PSW bits are:
• BIts 0 to 2 Stack pOInter bIts (SPo, SP1 ,
SP2)
Prescaler select (PS);
• Bit 3
o = moduI0-32; 1 = modulo-l
(no prescallng)
WorkIng register bank select
• Bit 4
(RBS); 0 = regIster bank
1 = register bank 0
Not used (1)
June 10, 1988

•

CLEARED
ONAESET

COUNTER MODE
MOV T,A (A) = 0 or RESET
MOV T,A
STRT CNT
STOP TCNT or RESET
JTF/JNTF
MOV A,T

1 Wrth prescaler select, PS = 0, the tImer counts modulo-32 machIne cycles; WIth PS = I, It counts modulo-1

cycles (prescaler not used), presealer cleared WIth STRT T, prescaler not readable

• BIt 6

Auxiliary carry (AC); halfcarry bIt generated by an
ADD InstructIon and used
by the decimal adjust
InstructIon DA A
• BIt 7
Carry (CY); the carry flag
Indicates that prevIous
operatIon has resulted In an
overflow of the accumulator.
All bIts can be read uSIng the MOV A, PSW
instructIon. BIts 7 and 6 are set and cleared
by CPU operatIon. Bit 4 can be changed by a
SEL RB InstructIon, BIt 3 by the MOV PSW, A

6-69

,....

SAYEe IN

SAVED IN

THE STACK

THE STACK

~

STACK POINTER

I

PS
3
MSB

!

\

I5P21 I I
SP,

2

1

SPo
0

LSB

Figure 15. Program Status Word
InstructIon, and Bits 0, 1, and 2 by the CALL,
RET, or RETR instructIons, and in the event
of an interrupt. BIts 7, 6, and 4 are stored In

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

the program counter stack during subroutine
and interrupt calls. These bits are restored in
the PSW with a RETR (return and restore)
instruction which must be used at the end of
an interrupt and can be used at the end of a
normal subroutine. The RET Instruction has

PCD3343

no restore feature and cannot be used at the
end of an interrupt.

Program Counter (see Figure
16)

arrangement of the bits IS shown in Figure 19.
During an interrupt subroutine PC " and PC '2
are forced to logic O. All 13 bijs are saved in
the stack during CALL and interrupt routines.

A 13-bit program counter is used to facilitate
8k bytes of ROM being addressed. The

Ipc..1pc"lpc..1pc. IPet Ipc. I IPCsl pc. IPet I Ipc. I I

lL

pc.

pc.

\

PC,

I

I
CONVENTIONAL PROGRAM COUNTER
• COUNTS
• OVERFLOWS

OIIOH TO 7FFH
7FFH TO OOOH

JMP OR CALL INSTRUCTIONS TRANSFER THE

~~~:F~ ~

::::-r:

NAL FUp..FlOP MBFFO TO PC"

•

(MBFFO) - 0 BY SEL MBO OR RESET
(Ullf'Fl)-O

•

(UBFFO) - 1 BY SEL UBl
(UBFF1)-O

•

(IIIBFFO) - 0 BY SEL UBI
(MBFF1)-1

•

(UBFFO) _
(Ullf'Fl) -

1 BY SEL MB3
1

Figure 16. Program Counter

Central Processing Unit
The PCD3343 has arithmetiC, logical, and
branching capabilities. The DA A, SWAP A,
and XCH D Instructions Simplify BCD arithmetic and the handling of nibbles. The MOVP
A,@A instruction permits efficient table lookup from the current ROM page.

Conditional Branch Logic
The conditional branch logic within the processor enables several conditions, internal
and external to the processor, to be tested by
the user's program. Table 5 lists the conditional jump Instructions used to change the
program sequence. The DJNZ instruction
decrements a designated register or data
memory location and branches If the contents
are not zero. This instruction is useful for
looping control. The JMPP@A Instruction allows multiway branches to destinations determined by the contents of the accumulator.

Test Input T1 (Pin 13)
The T1 input line can be used as:
• A test input for branch instructions JT1
and JNT1
• An external input to the event counter
When used as a test input:
• JT1 instruction tests for logiC 1 level
• JNT1 instruction tests for logiC 0 level
When used as an input to the event counter,
T1 must be Low for> 4CP, followed by a High
for> 4CP. The transition can be recognized
with a repetition rate of once per 30 oscillator
clock periods (1 machine cycle).

June 10, 1988

Table 5. Conditional Branches
JUMP CONDITION

TEST
Accumulator
Accumulator bit test
Carry flag
Timer overflow flag
Test input TO
Test input T1
Register

All bijs zero
Any bit non-zero
1
1
0
1
0
1
0
1
0
Non-zero

JUMP INSTRUCTION
JZ
JNZ
JBO to JB7
JC
JNC
JTF
JNTF
JNTO
JTO '
JT1
JNT1
DJNZ

NOTE:
1. Because of the Inverted Interrupt Input CE/TO, the conditional Jump JTO IS also Inverted

There is no internal pull-up or pull-down
resistor connected to the T1 input. If requored,
it must be externally connected to a resistor
(R = ..; 100kn). When T1 IS not used, Pin 13
must be connected to Voo or Vss.

Reset (Pin 17)
A positive-going Signal on the RESET input!
output:
• Sets the program counter to zero
• Selects location 0 of memory band 0
and register bank 0
• Sets the stack pOinter to zero (000);
pointing to RAM address 8
• Disables the interrupts (external, timer,
and serial 110)
• Stops the timer/event counter, then
sets it to zero

6-70

• Sets the IImer prescaler to modu10-32
• Resets the timer flag
• Sets all ports according to reset states
• Sets the senal I/O to slave receiver
mode and disables the serial I/O
• Cancels IDLE and STOP mode
After the voltage is applied to RESET, an
Internal delay of 1866CP is introduced before
the microcontroller commences operation.

Power-On Reset and Low
Voltage Detection (see Figure
17)
In telephony applications, correct operation of
the PCD3343 during moments of slowly
changing supply voltages and low-voltage
conditions IS essential. This IS achieved by

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

the addition of an internal power-on reset and
low voltage detection circulI.
To allow an external RESET signal being fed
into the PCD3343, the reset pin (Pin 17) has
been configured as an input! output.
While a reset condition exists In the detection
circuit, Pin 17 is pulled High by TR 1 controlled
by the reset circuil.

PCD3343

Since the level at Pin 17 is recognized by the
mlcrocontroller, the reset time constant can
be stretched by connecting an external capacitor between Voo and Pin 17 (see Figure
19).

delay (to), when the supply voltage rises
above the switching level again. The delay
ensures a complete reset even when the
supply voltage qUickly rises above SWitching
level after initial switch-on.

The signal at Pin 17 can also be used as an
output to reset other devices in the system.

During a low voltage condition, the oscillator
IS Inhibited to prevent complete discharge of
a weak battery. The timing of the power-onreset and low voltage detection Circuit is
shown in Figure 18.

The internal reset circUit monitors the
PCD3343 supply voltage. If the voltage drops
below the switching level (typ. 1.3V), a reset
(High) is applied to Pin 17. This reset IS
removed (Pin 17 goes Low), after a fixed

When the reset condillOn is not present, a
pull-down current source (TR2) Will be activated. TR2 forces Pin 17 Low, thus removing the
RESET signal from the microcontroller.

r---------------------,------------t~a~OVDD

~----~~--_+1.7~ReHrr
CURRENT
SOURCE --~_--...
10,.11

INTERNAL
RESET

PC03343

r-_+1;;..4- 0 v..

Figure 17. Power-on Reset Configuration

3V

LOW VOLTAGE CONDITION

~~E V."~~--~~~----------------------~~~----------------+_---------------

I

RESET

OSCILLATDR

:~f------'---,<>---_--+-~=_~l1-

·

~

ro1t~

Where:
(1) Oscillator inhibited
(2) Osolilator starling
(3) Oscillator running, but may be stopped With a STOP condition

Figure 18. TIming of Power-on Reset and Low Voltage Detection

June 10, 1988

6-71

Product Specification

Signetics linear Products

CMOS Microcontroller for Telephone Sets

PCD3343

28
OICILLATOR
INHIBIT
TAl

V...

POWER

"'U'"

ON

RESET

.".

17 RESET

BATTERY
SUPPlY

CURRENT

SOURCE
(10pA)

PCD3343

INTERNAL
RESET

14

TCI44"S

FlgurB 19. Stretched Power-On Rent with External Capacitor

INSTRUCTION SET
The PCD3343 instruction set consists of over
BO one· and two-byte instructions, and IS
based on the MABB04B instruction set. New
instructions include those for serial 110 operation and memory bank selection. Program
code efficiency is high because all RAM
locations and all ROM locations on a 256
byte page require only a single byte address.
Table B gives the instruction set of the
PCD3343, Table 7 shows the Instruction map,
and Table 6 details the symbols and definition
descriptions that are used.

Table 6. Symbols and Definitions Used in Table 8
SYMBOL

DEFINITION DESCRIPTION

A
Addr
Bb
RBS
C
CNT
D
Data
I
MB
MBFF
P
PC
Pp
PSW
RB
Rr
Sn
SP
T
TF
TO, T1

Accumulator
Program memory address
Bit designation (b - 0 - 7)
Register bank select
carry bit (bit CY)
Event counter
Mnemonic for 4-bit digit (nibble)
B-bit number or expression
Interrupt
Memory bank
Memory bank flip-flop
Mnemonic for 'in-page' operation
Program counter
Port designation (p = 0, 1, or 2)
Program status word
Register bank
Register designation (r = 0 - 7)
Serial 110 register
Stack pointer
Timer
Timer flag
Test 0 and 1 inputs
Immediate data prefix
Indirect address prefix
Contents of X
Contents of location addressed by X
Is replaced by
Is exchanged with

#
@

(X)
«X))
<-

....

June 10, 19B8

6-72

'-

c:

Table 7. PCD3343 Instruction Map

5='

irst hexadecimal character of opcode

Ol
CD

(f)

jI
o

NOP

IDLE

ADD

4

5

6

7

JMP

EN I

JNTF

DEC A

A, # data I page 0
INC @Rr

o
2

XCH A, @Rr

3

XCHD A, @Rr

4

ORL A, @Rr

o
o
o
5

I

7

o

TCNTI

addr

JB1

CALL

DIS

JTO

addr

page 1

TCNTI

addr

JMP
page 2

STRT
CNT

CALL
page 2

MOV

JMP

STOP

T, A

page 3

TCNT

JB3

CALL

JB2

ADDC A, @Rr

o

JNTO

addr

1

ADD A, @Rr

.!..J

EN

A, T

6

(.0)

JMP
page 1

MOV

I

1

I

A, # data
MOV
A, # data

ORL
A, # data
ANL
A, # data

addr

JB4

MOV @Rr, A

B

MOV @Rr, #data

C

DEC @Rr

D

XRL A, @Rr

o
o

o

I
I

1

I
DJNZ @Rr, addr
o I 1

E

F

MOV A, @Rr

o

I

I

JMP

OUTL Pp, A

JNT1

SWAP

ORL A, Rr

addr

A

STRT

JT1

DA A

T

addr

c:

1

2

F

1

3

1

I

4

151

6

1

7

(J)

I

4

151

6

I

7

1

4

151

6

I

7

1

4

1_5_1

6

1

7

5

6

6

I

2

I

2

I

3

~

c::

@-

.....

0'
.....

2

~
(J)

"0

1

1

2

1

3

ADD A, Rr

1

ADDC A, Rr

01

8

-

a

o

4

~

:J

o:J

7

L5 J
-'-1_----'-

3

s::
o·

ao

o

ANL A, Rr

o
JNZ

page 4

SI

addr

MOVP

JMP

SEL

CLR C

1

1
1

2

1

2

3

4

3

CPL C

~

o:J
(J)

(J)

7

~

MB2

CALL

SEL

addr

A, @A

page 5

MB3

JMP

SEL

JZ

MOV

page 6

RBO

addr

A, PSW

2

1

I

1

MOV Sn, #data

I

2

I

2

I

MOV Rr, #data

o

SEL

MOV

RB1

PSW, A

JMP

SEL

JNC

page 7

MBO

addr

JB7

CALL

SEL

JC

addr

page 7

MB1

addr

RL A

DEC Rr

o

•

I

2

1

I

2

I
I

3

I

I

3

3

o

I

5

I

6

4

5

I

6

I

4

I

5

I

6

4

1

I

7

I

7

7

2

I

3

I

4

I

5

I

6

I

7

I

2

I

3

I

4

I

5

I

6

I

7

I

2

I

3

I

4

I

5

I

6

I

7

MOV A, Rr

o

I
I

I

DJNZ Rr, addr

I

2

1

I
I

I
I

XRL A, Rr

o
RLC A

o

MOV Rr, A

o

page 5

I

ANL Pp, #data

o

JMPP

A, # data I page 6

2

E

~

ORL Pp, #data

EN

A, @A

addr

j

D

MOV Sn, A

I

o

o

SI

I CALL

I

2

C

B

MOV A, Sn

I

o

RR A

A

Rr

o

RRC A

I

INC Rr

CPL A

DIS

XRL

9

I
o I
A,
o 1

XCH

JB5

JB6

o

(J)

IN A, Pp

CLR A

CALL

I

o

I

addr

page 4
RETR

addr

A

I

INC A

page 3
RET

8
9

JTF

DIS I

STOP

ANL A, @Rr

o
(l)

1
1

I ADDC I

I

8

o

addr

CALL
page 0

JBO
addr

«s"

s::

SECOND HEXADECIMAL CHARACTER OF OPCODE

CD

~

()

-a

~
o
w

w
~
w

a0.
c::

Q.

-g'
~

ao·
Ol

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

Table 8. Instruction Set
OPCODE
(HEX.)

MNEMONIC

BYTESI
CYCLES

DESCRIPTION

FUNCTION

NOTES

ACCUMULATOR

ADD A, Rr
ADD A, @Rr

XR LA, # data
INC A
DEC A
CLR A
CPL A
RL A

6"
60
61
03
7"
70
71
13
5"
50
51
53
4"
40
41
43
0"
DO
01
03
17
07
27
37
E7

RLC A

F7

1/1

RR A

77

1/1

RRC A

67

1/1

DA A
SWAP A

57
47

1/1
1/1

(A) -- (A) + (Rr)
(A) -- (A) + «RO))
(A) -- (A) + «R1))
Add immediate data to A
(A) -- (A) + data
Add carry and register contents to A
(A) -- (A) + (Rr) + (C)
Add carry and RAM data, addressed
(A) -- (A) + «RO)) + (C)
by Rr, to A
(A) -- (A) + «R1)) + (C)
Add carry and immediate data to A
(A) -- (A) + data + (C)
'AND' Rr with A
(A) -- (A) AND (Rr)
'AND' RAM data, addressed by Rr, with A (A) -- (A) AND «RO))
(A) -- (A) AND «R1»
'AND' immediate data with A
(A) -- (A) AND data
'OR' Rr with A
(A) -- (A) OR (Rr)
'OR' RAM data, addressed by Rr, with A (A) -- (A) OR «RO))
(A) -- (A) OR «R1))
'OR' immediate data with A
(A) -- (A) OR data
'XOR' Rr with A
(A) -- (A) XOR (Rr)
'XOR' RAM, addressed by Rr, with A
(A) -- (A) XOR «RO))
(A) -- (A) XOR «R1))
'XOR' immediate data with A
(A) -- (A) XOR data
Increment A by 1
(A) -- (A) + 1
Decrement A by 1
(A) -- (A)-1
Clear A to zero
(A) -- 0
One's complement A
(A) -- NOT(A)
Rotate A left
(An + 1) -- (An)
(Ao) -- (A7)
Rotate A left through carry
(An + 1) -- An
(Ao) -- (C), (C) -- (A7)
Rotate A right
(An) -- (An + 1)
(A7) -- (Ao)
Rotate A right through carry
(An) -- (An + 1)
(A7) -- (C), (C) -- (Ao)
Decimal adjust A
Swap nibbles of A
(A4 - 7) .... (Ao-a)

F"
FO
F1
23
MOV A, #data
MOV Rr, A
A*
MOV @Rr, A
AO
A1
MOV Rr, #data
B*
MOV @Rr, #data BO
B1
XCH A, Rr
2"
XCH A, @Rr
20
21
XCHD A, @Rr
30
31
C7
MOV A, PSW
MOV PSW, A
07

1/1
1/1

Move register contents to A
Move RAM data, addressed by Rr, to A

2/2
1/1
1/1

Move immediate data to A
Move accumulator contents to register
Move accumulator contents to RAM
Location addressed by Rr
Move immediate data to Rr
Move immediate data to RAM location
addressed by Rr
Exchange accumulator contents with Rr
Exchange accumulator contents with
RAM data addressed by Rr
Exchange lower nibbles of A and RAM
data addressed by Rr
Move PSW contents to accumulator
Move accumulator Bit 3 to PSWa
Move indirectly addressed data in current
page to A

ADD A, #data
ADDC A, Rr
ADDC A, @Rr
ADDC A, #data
ANL A, Rr
ANL A, @Rr
ANL A, #data
ORL A, Rr
ORL A, @Rr
ORL A, #data
XRL A, Rr
XRL A, @Rr

1/1
1/1

data

data

data

data

data

2/2
1/1
1/1
2/2
1/1
1/1
2/2
1/1
1/1
2/2
1/1
1/1
2/2
1/1
1/1
1/1
1/1
1/1

Add register contents to A
Add RAM data, addressed by Rr, to A

r= 0-7

r= 0-7

1
1
1
1
1
1

r=0-7

r= 0-7

r= 0-7

n=0-6
n=0-6

2

n=0-6
n=0-6

2
2

DATA MOVES

MOV A, Rr
MOV A, @Rr

MOVP A, @A

June 10, 1988

A3

data

data
data
data

2/2
2/2
1/1
1/1
1/1
1/1
1/1
1/2

6·74

(A) -- (Rr)
(A) -- «RO))
(A) -- «R1))
(A) -- data
(Rr) -- (A)
«RO)) -- (A)
«R1» -- (A)
(Rr) -- data
«RO)) -- data
«R1)) -- data
(A) .... (Rr)
(A) .... «RO))
(A) .... «R1))
(Ao-a) .... «ROo_a))
(Ao-a) .... «R1o-a)
(A) -- (PSW)
(PSWa) -- (Aa)

r= 0-7

r= 0-7

r= 0-7

(PCO- 7) -- (A), (A) = -- «PC))

3

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

PCD3343

Table 8. Instruction Set (Continued)
OPCODE
(HEX.)

MNEMONIC

BYTESI
CYCLES

DESCRIPTION

FUNCTION

NOTES

FLAGS

CLR C
CPL C

(C) ..... a
(C) ..... NOT(C)

97
A7

1/1
1/1

Clear carry bit
Complement carry bit

l'
10
11
C'
CO
C1

1/1
1/1

(Rr) ..... (Rr) + 1
Increment regIster by 1
Increment RAM data, addressed by Rr, by 1 «RO» ..... ((RO» + 1
«R1» <- «R1» + 1
(Rr) ..... (Rr)-1
Decrement regIster by 1
Decrement RAM data, addressed by Rr, by 1 ((RO)) ..... «RO» - 1
((R1)) ..... «R1»-1

2
2

REGISTER

INC Rr
INC @Rr
DEC Rr
DEC @Rr

1/1
1/1

r = 0-7

r=0-7

BRANCH

JMP addr

• 4 address

2/2

Uncondit,onal jump within a 2k bank

JMPP @A
DJNZ Rr, addr

B3
E' address

1/2
2/2

DJNZ @Rr, addr

EO

2/2

Indirect jump wIthin a page
Decrement Rr by 1 and lump if not
zero to addr
Decrement RAM data, addressed by Rr
by 1 and jump if not zero to addr

E1
JBb addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JTF addr
JNTF addr

... 2 address
F6 address
E6 address
C6 address
96 address
36 address
26 address
56 address
46 address
16 address
06 address

2/2
2/2

2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2

Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump

to
to
to
to
to
to
to
to
to
to
to

addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr

II
II
il
il
il
il
il
II
if
il
if

Acc. bit b = 1
C=1
C= a
A=0
A IS NOT zero
TO = a
TO = 1
T1 = 1
T1 = a
TImer Flag = 1
Timer Flag = a

(PCS - 1o) ..... addrs_l0
(PCo-7) ..... addro_7
(PC 11 -121 ..... MBFF 0 - 1
(PCO- 7) ..... «A»
(Rr) ..... (Rr) - 1
r=0-7
if (Rr) not zero (PCo _ 7) ..... addr
«RO)) <- «RO» - 1
if «RO)) not zero (PCo _ 7) ..... addr
«R1)) ..... «R1»-1
if «R1» not zero (PCO - 7) ..... addr
II b = 1 : (PCO_ 7) ..... addr b = 0 - 7
II C = 1 : (PCO-7) +-- addr
II C = 0 : (PCo -7) ..... addr
II A = a : (PCO_ 7) <- addr
II A a : (PCo-7) <- addr
II TO = 0: (PCo_ 7) ..... addr
II TO = 1: (PCO-7) ..... addr
II T1 =1: (PCO_7) ..... addr
If T1 = 0: (PCo _ 7) +- addr
If TF = 1: (PCO-7) ..... addr
If TF = 0: (PCo_ 7) <- addr

'*

4

TIMER/EVENT COUNTER

MOV A, T

42

1/1

MOV T, A

62

1/1

STRT CNT
STRT T
STOP TCNT
EN TCNTI
DIS TCNTI

45
55
65
25
35

1/1
1/1
1/1
1/1
1/1

Move tImer/event counter contents to
accumulator
Move accumulator contents to timer/event
counter
Start event counter
Start timer
Stop timer/event counter
Enable tImer/event counter interrupt
Disable timer/event counter interrupt

05
15
C5
D5
E5
F5
A5
B5
22
01

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

Enable external interrupt
Disable external interrupt
Select regIster bank 0
Select register bank 1
Select program memory bank
Select program memory bank
Select program memory bank
Select program memory bank
Enter STOP mode
Enter IDLE mode

(A) ..... (T)
(T) ..... (A)

CONTROL

EN I
DIS I
SEL RBO
SEL RB1
SEL MBa
SEL MB1
SEL MB2
SEL MB3
STOP
IDLE

June 10, 1988

6-75

a
1
2
3

(RBS) ..... 0
(RBS) <- 1
(MBFFO) <(MBFFO) .....
(MBFFO) <(MBFFO) <-

5
5
0,
1,
0,
1,

(MBFF1)
(MBFF1)
(MBFF1)
(MBFF1)

..... 0
<- 0
<- 1
<- 1

•

Signetics Linear Products

Product Specification

CMOS Microcontrol/er for Telephone Sets

PCD3343

Table 8. Instruction Set (Continued)
OPCODE
(HEX.)

MNEMONIC

BYTES/
CYCLES

DESCRIPTION

FUNCTION

NOTES

SUBROUTINE
CALL addr

... 4 address

2/2

Jump to subroutine

RET

63

1/2

Return from subroutine

RETR

93

1/2

Return from Interrupt and restore
bits 4, 6, 7 of P5W

1/2

Input port p data to accumulator

1/2

Output accumulator data to port p

2/2

AND port p data with immediate data

2/2

OR port p data with immediate data

((5P» +- (PC), (P5W4, 6, 7)
(SP) +- (5P) + 1
(PCS -10) +- addrs_10
(PCo - 7) +- addro - 7
(PC,, - , 2l +- MBFF 0-1
(5P) +- (5P) - 1
(PC) +- ((5P»
(5P) +- (5P) - 1
(P5W4, 6, 7) + (PC) +- ((5P»

6

6

6
6

PARALLEL INPUT/OUTPUT
IN A, Pp

OUTL Pp, A

ANL Pp, #data

ORL Pp, #data

06
09
OA
36
39
3A
96
99
9A
66
69
6A

(A) +- (PO)
(A) +- (Pl)
(A) +- (P2)
(PO) +- (A)
(Pl) +- (A)
(P2) +- (A)
(PO) +- (PO)
(Pl) +- (Pl)
(P2) +- (P2)
(PO) +- (PO)
(Pl) +- (Pl)
(P2) +- (P2)

SERIAL INPUT/OUTPUT
MaY A, 5 n

EN 51
DI551

OC
OD
3C
3D
3E
9C
9D
9E
65
95

Nap

00

MaY 5 n, A

MaY 5 n, #data

1/2
1/2

Move senal I/O register contents to
accumulator
Move accumulator contents to senal
I/O register

2/2

Move Immediate data to senal
I/O register

1/1
1/1

Enable senal I/O Interrupt
Disable senal I/O interrupt

1/1

No operation

NOTES:
1. PSW CY, AC
affected
2 PSW CY
affected
3 PSW PS
affected
4 ExecutIon of JTF and JNTF InstructIons resets the TImer Flag (TF)
5 PSW RSS
affected
6 PSW SPo, SP" SP2 affected
7 (A) = 1111 P23, P22, P21, P20
8. (81) has a different meaning for read and write operation, see senal 1/0 Interface

9 (S2) IS a wnte only regIster ReadIng S2 WIll gIve value FFH .
• . 8, 9, A, S, C, D, E, F
•. 0, 2, 4, 6, S, A, C, E
... " 3, 5, 7, 9, S, D, F

June 10, 1988

6-76

(A) +- (50)
(A) +- (51)
(50) +- (A)
(51) +- (A)
(52) +- (A)
(50) +- data
(51) +- data
(52) +- data

7

AND data
AND data
AND data
OR data
OR data
OR data

-6

9

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

12

10

10

10

(1)1=

(1)r-

I-' t/ " / r/ r- (~~

,1"/

I

"

1

V

j

4

PCD3343

(2)f--

(1)

l."..- I-'

(3)

f--

l:l~

1,/

'/

1/

~

"'(/

o
o

I,...-

4

NOTES;

0.01

4
8
Voo (V)

10

•
V..,IV)

10

1
2
3
4

4 TA-25"C

Figure 20. Maximum Clock Frequency
(fXTAL) as a Function of the Supply
Voltage (Yoo)

Figure 21. Typical Supply Current (IOf)
In Operating Mode as a Function 0
the Supply Voltage (VDO)

./

.....,...

~
V I,.;'

.(1)

(2)

v..

o

10

Clock frequency "'" 4MHz
Clock frequency ... 2MHz
Clock frequency ". 500kHz
TA""25"C

Figure 22. Typical Supply Current (IDO)
in IDLE Mode as a Function of the
Supply voltage (Voo)

(1)

(2)

.....

~ L."...

17 v

...... (3)

V

V

8

4
8
Vaa (V)

NOTES;

NOTES;
1 Clock frequency "" 4MHz
2. Clock frequency = 2MHz
3. Clock frequency - 500kHz

1 T. =-2S·C
2 TA-25"C
3 T.-70·C

1/V

0.1

1/r/ ~......
V. 7

~

J'

(1)

f--

(2)

i---' (3)

'"

"
o

o

4
8
VDD (V)

10

NOTES;

4

8

10

o

o

VDD (V)
NOTES;

1 T.=-2S·C

1 TA""'-25"C

2 TA""25"C
3 TA~70°C
4 Vo=04V

3 TA=70·C

June 10. 1988

8
VDD(V)

10

NOTES;

1 TA=70°C

2 TA "25"C

Figure 23. Typical Supply Current (100)
In STOP Mode as a Function of the
Supply Voltage (Voo)

4

2 TA-25"C
4 Vo""04V

Figure 24. Output Sink Current Low
(IOL), Except Outputs P23/SDA and
SCLK, as a Function of Supply Voltage
(Voo)

6-77

Figure 25. Output Current LOW(IOL),
Outputs P23/SDA and SCLK, as a
Function of Supply Voltage (Voo

Signetics linear Products

Product Specitication

CMOS Microcontroller for Telephone Sets

Table 9. Input Timing Shown
in Figure 27

200

SYMBOL
160

..- (1)
V

~ 120

is

"i

V

80

-.r
1;-

40

o

PCD3343

V
/

o

..-

V

-

- ----

-

TIMING

> 14tXTAL
> 14tXTAL
> 17tXTAL
> 17tXTAL
> 14tXTAL

ISUF
tHo, tSTA

(2)-

tHIGH
tLOW
tSY, IsTO

(3)-

>0

tHO, tOAT

(4)r-

> 250ns

tsu, tOAT

.;; IllS
.;; IllS
';;1J1S
';;0311S

tRO
tRC

4

tFD

10

tFC

VOD(V)

NOTES.
IXTAL = one period of the XTAL Input frequency (fXTALl
= 2BOns for fXT AL = 3 5BMHz
These figures apply to ali modes

NOTES:

1 TA = 25°C, Vo=Vss
2 TA = 25°C, VO=09VOD

:3 TA "'" 70o e, Vo= Vss

4 TA = lODe, VO=09VOD

Figure 26. Output Source Current
HIGH (-I0H) as a Function of Supply
Voltage (VDD)

SClK

r-it----n;~1Qr 51

tFD. tFC

;;'15txTAL
-< 24tXTAL
;;'15txTAL
-<24tXTAL
;;. 9tXTAL
;;. 9tXTAL
-< 12tXTAL
-< 100ns
at Cb = 400pF

;;. 9txTAL
;;. 9tXTAL
-< 12tXTAL
-< 100ns
at Cb = 400pF

NOTES:
tXT AL
OF
Cb

= one penod of the XTAL Input frequency
=280ns for fXTAL = 3.58MHz.
= divisor (see Table 2 Serial 110 section).

•

(fXT All

= the maximum bus capacitance for each line.

June 10. 1988

tXTAL
tXTAL
tXTAL
tXTAL

;;. 9txTAL
-< 12tXTAL

for OF-<99

for OF> 99
for OF-<51
for OF-<99
tAC

(OF + 9)
(OF)
(OF)
(OF - 3)

6-79

Signetics Linear Products

Product Specification

CMOS Microcontroller for Telephone Sets

APPLICATION INFORMATION

•
•
•
•

A block dIagram of an electric Feature phone
built around the PCD3343 IS shown In FIgure
29. It comprises the followIng dedIcated telephony ICs'

PCD3343

TransmIssIon circuit for telephony
DTMF generator with Serial 1/0
LCD driver
1k RAMs with Serial 1/0; the number of RAMs depends on
the required amount of stored telephone numbers
Programmable multI-tone ringer

TEA1060/1061
PCD3312
PCF8577
PCD8571

• PCD3360

I

I

TRANSMISSION

DIALING

I

SUPPLY

-r,

KEYBOARD
T

TRANSMISSION
CIRCUIT
TEAl060
TEA1061

MUTE

DEDICATED
MtCROCONTROUER

POWER DOWN

PCD3343

I-+-+-H-+ -i

LI'---f-+t-+-t-+-i
N---If-+-+-+-I-t-i
t-++--ll-+- +--i
........'--"-'-..._L.I

AlB

TELEPHONE
LINE
BIA

o---t--'>-----+
DTMF

PC03312

SCL

SDA

2" LCD

DRIVERS
PCE21n or
PCF8S77

l"caus

..
I
I

------,
1II-OtG1T
LCD

I

I

'-______...1I

RAM
PaI8571

CLOCK

"MAlL.

CALENDAR
PC8I573

I I
Figure 29. Block Diagram of Electronic Featurephone with Common Line Interface
A detaIled application dIagram of the
PCD3343 wIth PCD3312 (DTMF), two
PCD85?1 (RAM), and two PCE2111 (LCD
display drivers) IS shown in FIgure 30.
Row 5 of the keyboard contains the followIng
specIal keys.
• P Program and autodial

June 10, 1988

• FL Flash or register recall
• R RedIal or extended redial

Additoonal Information is available on request
for the following:

• AP Access pause

•
•
•
•
•

Row 6 contains the different diode options.
Columns 5 and 6 contaIn the button keys MO
to M9; SIngle name keys for repertory telephone numbers.

6-80

Serial 110
12C bus specification
Interrupt logic
Instruction set deSCriptions
Software routines for an intelligent
telephone set

en

c...

c:

()

::l

'"

s:

p

0

'"

~

s:

(;-

V DD

DTMF

SUPPLY FROM
TEA 106011

......

0

14

()

0

BATTERV
SUPPLY

I

::J
......

~

10k

10 k

12CBUS

GROUND

Vss

P23

Ml

r----

PCD3343
MUTEUNES

M1

LINE INTERRUPTER
OR FLASH OUTPUT

DP

ROWS

I

COLUMNS

16

I
I
I

I

M2 I M3

c

II M4 I M5 I KEYBOARD

......

0
CD
......

0'
......
a;t
CD
"0
"::J"
0
::J
CD

I

M2

~

::l

en

ex>
ex>

Ol

rfi

en
CD
......
U)
I

L __________

I
~

DIIM.IM7
FLI

R IAPIlMSIM9

DIODE OPTIONS

PULSE/DTMF

NORMAL/DIRECT

EXTENSION/KEYBOARD

""C

()

o

(..)
(..)

•

Figure 30. Application Diagram of PCD3343 for Electronic Featurephone with Associated Keyboard

J::o.

(..)

~

c

n.

en

~

a
()"

:;J

PCD3360

Signetics

Programmable Multi-Tone
Telephone Ringer
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The PCD3360 are CMOS integrated circuits, designed to replace the electromechanical bell in telephone sets. They
meet most postal requirements, particularly with tone sequence pOSSibilities and
input frequency selectivity. Output signals for a loudspeaker or for a piezoelectric (PXE) transducer are provided. In the
former application, no audio transformer
is required since the loudspeaker is
driven in class D.

• Output signals for electrodynamic transducer (loudspeaker)
or for piezoelectric transducer

NOTE:
Tone sequences (up to 16 tones long), Impedance
settmgs and automatic swell levels are mask programmable for customized verSions.

D, N Packages

(PXE)

• 7 basic frequencies (tones) and a
pause
• 4 selectable tone sequences
• 4 selectable repetition rates
• 3 selectable impedance settings
• 3-step automatic swell
(loudspeaker only)
• Delta-modulated output signal
that approximates a sinewave
(loudspeaker only)
• Input frequency discriminator
with selectable upper and lower
frequency limits
• Output for optical signal

TOP VIEW
CD127108

PIN NO. SYMBOL

3
4
5
6

7
8
9
10
11
12
13
14
15
16

APPLICATION
• Telephone hand sets

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

IS-Pin Plastic DIP (SOT-36)

-25°C to + 75°C

PCD3360PN

16-Pin Plastic SO
(SO-16l; SOT-162A)

-25°C to + 75°C

PCD3360TD

PDE
RR2
RRI
OSC
Voo
TONE

OPT
DM
152
151
Vss
TS2
TSI
FOI
FL
FH

DESCRIPTION

Frequency dlSCnmlnator enable
Repetition rate setectlon

Oscillator
Posltrve supply
Tone output
Optical signal output
DrIve mode selectlon
Impedance setting and

automatic swell
Negabve supply
Tone sequence selectIOn
Frequency dlscnmlnator Input
Lower frequency limit selectIOn
Upper frequency limit setecbon

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Voo

Supply voltage range

100

±Ih
±Io

RATING

UNIT

-0.8 to +9

V

Supply current

50

mA

DC current mto any Input or output

10

mA

VI

All Input voltages

PTOT

Total power dissipation

-0.8V to Voo +0.8

V

300

mW

Po

Total dissipation per output

50

mW

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-25 to +70

°C

December 2, 1986

6-82

853-1034 66700

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

PCD3360

BLOCK DIAGRAM
fCK

= 32kHz
(TONE PATTERN)

OSC

(32kHz PULSES)

OUTPUT
CIRCUIT

TONE

t - - - - + - o OPT

1---+'-<> FOE

1S1

1$2

RR1

RR2

TS1

TS2

OM

FDI

FL

FH

•

December 2, 1986

6-83

Product Specification

Signetics Linear Products

PCD3360

Programmable Multi-Tone Telephone Ringer

DC ELECTRICAL CHARACTERISTICS VDD = 6V; vss = 0; fose = 64kHz; TA = -25°C to+ 70°C; valid enable conditions at
FDI and FDE, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT

Min

Typ

Max

Supply

VDD

Operating supply voltage

VSB

Standby supply voltage 1

VAS

Supply voltage for automatic swell reset2

IDD

Operating supply current

ISB

Standby supply current3
at VDD < VSB

8.0

V

5.7

V

100

120

p.A

4

8

JlA

VSB + 0.1
TSD

4.8

V

0.5VSB

Inputs

V,L

Input voltage LOW (any pin)

0

0.3VDD

V

V,H

Input voltage HIGH (any pin)

0.7VDD

VDD

V

Pull-down circuits of inputs
R'L
I'H

FDE, RR1, RR2, DM, lSI, IS2, TS1, TS2, FL, FH
PUll-down resistance with input at Vss
PUll-down current with Input at VDD

ISL
ISH
Isx

PUll-down circuit of FDI
PUll-down current with VFDI = 0.3VDD
Pull down current with VFDI = 0.7VDD
Pull-down current with VDD < VSB

± liS

Current into input FDI4

20
0.1'
TSD

20
0.1
0.1

kn

JlA
TSD

p.A
p.A
p.A

0.2

rnA

Outputs (TONE, OPT)

IOL

Output sink current at VOL = 0.5V

1

2

-IOH

Output source current at VOH = VDD - 0.5V

1

2

rnA
rnA

AC ELECTRICAL CHARACTERISTICS VDD = 6V; Vss = 0; fose = 64kHz; TA = -25 to + 70°C; valid enable conditions at FDI
and

FOE,

unless otherwise specified.
LIMITS

SYMBOL

UNIT

PARAMETER
Min

tD(on)

Switch-on delay
(with FDE = LOW and ringing frequency within limits set by FL and
FH)5

tD(off)

Switch-off delay (with FDE= LOW)
at FL = LOW
at FL= HIGH

fose

Oscillator frequency at Rose = 365kn; Case = 56pF6

.:lfose

Frequency variation at VDD = 5.7 to 8.0V

tD(Off)

Typ

1

TSD

64

NOTES:
1. For Voo < VSB the CirCUIt IS in standby.
2. At Voo = VAS the automatic swell register is reset.
3. The standby supply current IS measured with all Inputs and outputs open-Circuit with the exception of ase
4 The current lis is clamped to Voo and to Vss by two Internal diodes. Correct operation IS ensured wrth VFDI > VOD or VFDI
maximum value of lis IS not exceeded. (The Input FDI has an extended HIGH and LOW Input voltage range)
The sWitch-on delay IS measured In cycles of incoming nnglng frequency

6 Lead lengths of Rosc and Cose to be kept to a minimum.

December 2, 1986

6-84

Max

1.5

ms

75

ms

112.5

ms

TSD

kHz

1

%

< Vss,

provided the

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

FUNCTIONAL DESCRIPTION
Supply Pins (VDD and VSS)
If the supply voltage (Voo) drops below the
standby voltage (Vss), the oscillator and most
other functions are sWitched off and the
supply current IS reduced to the standby
current (Iss) The automatic swell register
retains ItS Information until Voo drops further
to a value VAS at which reset occurs

PCD3360

FDE

SELECTION
PINS

RRl
RR2
DM
181
182
T51
T52
Fl
FH

(1)

Oscillator (OSC)
The 64kHz oscillator IS operated via an external resistor and capacitor con nected to pin
OSC. The oscillator signal IS divided by two to
provide the 32kHz Internal system clock

Selection Pins (FOE, RR2, RR1,
OM, IS2, IS1, TS2, TS1, FL and
FH)
These pinS are pulled down Internally by a
pull-down current I'H when they are connected to Voo, and by a pull-down resistance R'L
when they are connected to Vss (see Figure
1). Thus, when the pinS are open-CirCuit, they
are defined LOW Therefore, only a slnglecontact sWitch IS required to connect the pinS
to Voo, yet the supply current IS only marginally Increased as I'H IS very small.

Frequency Discriminator Circuit
(Pins FOE and FDI)
The frequency diSCriminator CIrCUit prevents
the ringer being activated by dial pulses,
speech or other unqualified signals.
The Circuit IS enabled or disabled by Input
FDE
When FDE IS HIGH, FDI acts as a logiC
enable input.
The CirCUit Will produce tone sequences proVided FDI IS HIGH and Voo exceeds Vss.

PCD3360

NOTE.
1 TranSistor resistance = All when sWitched on

Figure 1. Input Circuit of Selection Pins
6) and an Internal Sink current that IS sWitched
from 20)1A (typ.) for FDI ~ LOW to < 0.1)1A
for FDI ~ HIGH. Excess current entering FDI
via R2 IS absorbed to Internal diodes clamped
to Voo and Vss·

Selection of Frequency
Discriminator Limits (FL and
FH)

The tone sequences are repeated continuously provided the enable conditions at Inputs
FDE and FDI are valid and Voo > Vss; the
first sequence always starts With the first tone
shown in Figure 3.

Table 1. Selection of Lower
Frequency Discriminator Limits
(fosc = 64kHz)

Selection of Repetition Rates
(RR1 and RR2)

FL INPUT
STATE

LOWER
DISCRIMINATOR
LIMIT (Hz)

The cirCUit Will produce tone sequences proVided Voo exceeds Vss and the signal at FDI
fulfills the conditions set by FL and FH.

LOW
HIGH

20
13.33

The CIrCUIt Will continue to produce tone
sequences provided the time between subsequent falling edges or between subsequent
rising edges remains Within the limits set by
FL and FH Because two edges are reqUired
for detection, either positive or negative, the
sWitch-on delay Will vary between 1 and 1.5
cycles of the incoming ringing frequency.
FDI has a Schmitt trigger action, the levels
are set by an external resistor R2 (see Figure
December 2, 1986

Four tone sequences are programmed In the
Internal ROM (see Figure 3). Inputs TS1 and
TS2 determine which tone sequence is selected and output at pin TONE. The se·
quences are mask-programmable With any
length up to 16 time Intervals

With the frequency diSCriminator enabled
(Voo > Vss and FDE ~ LOW) the lower and
upper limits of the Input frequency are set by
inputs FL and FH as shown by Tables 1 and
2, respectively.

When FDE IS LOW, FDI acts as the frequency
diSCriminator Input.

When the frequency diSCriminator IS enabled
(Voo > Vss and FDE ~ LOW) the CIrCUit Will
start to produce tone sequences after two
rising or two falling edges have occurred at
FDI. The time between these edges must be
Within the limits set by FL and FH.

their corresponding Internal ROM tone code
In Figure 2.

Table 2_ Selection of Upper
Frequency Discriminator Limits
(fosc = 64kHz)
FH INPUT
STATE

UPPER
DISCRIMINATOR
LIMIT (Hz)

LOW
HIGH

60
30

Selection of Tone Sequences
(TS 1 and TS2)
A tone sequence IS composed of 15 or 16
equal time Intervals Each time Interval may
be filled With one of seven available tones or
With a pause; these are shown together With

6-85

The duration of a time Interval Within a tone
sequence IS determined by the state of inputs
RR1 and RR2 as shown In Table 3. The
resultant vanatlon of repetition rate acts as a
distingUishing feature between adjacent telephones.

Table 3. Duration of Time
Intervals (fosc = 64kHz)
INPUT STATE
RR1

RR2

TIME INTERVAL
(ms)

L
L
H
H

L
H
L
H

15
30
45
60

The repetition rate variation can be extended
by mask-programming (for customer defined
versions) the same tone combination for all 4
tone sequences, but With a different number
of time intervals per tone. Thus the repetition
rate can be selected from 16 values by Inputs
RR1, RR2, TSI and TS2.

•

Product Speclficatlon

Signetlcs Linear Products

Programmable Multi-Tone Telephone Ringer

,

Drive Mode Selection (OM)
The output signal at pin TONE can be selected for application with electro-dynamic or
piezoelectric transducers. An example of both
signals, for a tone frequency of 667Hz, IS
shown in Figure 4.

FREQUENCY RAno

PXE Mode
In the PXE mode (OM = HIGH), pin TONE
outputs a square wave. In thiS mode the
ringer impedance and sound pressure level
are determined by the characteristics (e.g.,
the size) of the PXE transducer; inputs lSI
and IS2 are inactive.

1S2

FREQUENCY (Hz)

C

D

E

co

B

C

E

533

600

867

800

1000

11167

1333

10

12

15

18

20

TONE CODE

Figure 2. Available Tones and Their Corresponding Internal ROM Tone Code

TONE SEQUENCE OUTPUT AT PIN TONE

PIN STATE

Setting of Impedance, Sound
Pressure Level and Automatic
Swell (IS1 and IS2)
With OM = LOW (loudspeaker mode), inputs
lSI and IS2 determine the pulse duration of
the output signal and thereby the DC reSIstance Rxy (seen at points x and y in Figure 6)
and also the Sound Pressure Level (SPL).
The selection of 3 impedance settings and
automatic swell is shown in Table 4.

~

1 r~

TONE KEY

Loudspeaker Mode
In the loudspeaker mode (OM = LOW), pin
TONE outputs a delta-modulated signal that
approximates a sinewave sampled at a rate
of 32kHz. The output pulse duration is determined by pins IS 1 and IS2. The resultant
acoustic spectrum is aurally more acceptable
and has greater penetration than a square
wave spectrum because more power is concentrated at the fundamental frequency.

PCD3360

TSI

TONECOOE

333444222777661

TONE CODE

1313131313131313

TONECOOE

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

TONE CODE

4

4

4

0

4

4

4

0

4

4

4

4

4

4

0

0

H

H

H

H

Figure 3_ Tone Sequences Mask-Programmed In the PCD3360

Table 4. Setting of Pulse Duration and Automatic Swell (OM
INPUT STATE
FUNCTION
IS1

IS2

L

L

L
H
H

H
L
H

Automatic
Swell

Constant
Level

= LOW)

RINGING BURST PULSE DURATION (/lS)
NUMBER (N)
Fund
Harm
1
2
>2

1.8
2.6
3.9
2.6
3.6
5.0

1.6

Rxy
(kn)

(kn)

SPL
(dBr)

40
20
5

TBO
17.5
7

TBO
-4
0

20
10
5

17.5
10.5
7

-4
TBO
0

ZI

Where:
1. Typical pulse duration values of the fundamental and harmonic frequencies are for fose = 64kHz and fCK = 32kHz.
2. SPL IS the relallVe Sound Pressure Level, and OdSr IS defined as the SPL for lSI = IS2 = HIGH
3. Values of the DC resistance Rxy. bell Impedance (Z,) and SPL are valid for a value of Input voRage V, = 40VRMS In Figure 6.

December 2, 1986

6-86

Product Specification

Signetics Linear Products

Programmable Multi-Tone Telephone Ringer

Setting of Impedance, Sound
Pressure Level and Automatic
Swell
When pinS 151 and 152 are both LOW, the
circuit operates In the automatic swell mode.
The 5PL then Increases In three steps so that
the maximum level IS reached for the third
ringing burst.
Each time VDD drops below VAS, the automatic swell register IS reset and the next ringing
burst IS considered as N = 1 (see Table 4).
A buffer capacitor C3 (see Figure 6) must
hold VDD > VAS dUring the time between two
consecutive ringing bursts of a series.
For each of the other three combinations of
PinS 151 and 152, the pulse duration has a
constant value Thus, the ringer can be designed so that the Impedance represented at
the telephone line will comply With postal
requirements that vary In relation to parallel or
series connections of more than one ringer
To sabsfy some applications, a harmOniC
Signal IS added to the fundamental frequency
In the last step of the automatic swell mode.
The pulses representing this harmOniC Signal
are Interleaved with the pulses of the fundamental signal (see Figure 5) The difference In
pulse duration shown In Table 4, IS chosen so
that the harmOniC level IS 10dS below the
fundamental level
The harmOniC frequency range IS from 2kHz to
32kHz. The IndiVidual harmOniC frequencies
for the seven tone codes and the relative
fundamental frequencies are shown In Table
5.

Table 5. Harmonic Frequency In
Relation to Tone Code and
Fundamental Frequency
FREQUENCY (Hz)

TONE
CODE

Fundamental

Harmonic

1
2
3
4
5
6
7

533
600
667
BOO
1000
1067
1333

3200
2400
2667
3200
2000
2133
2667

USing a Single mask It is pOSSible to program
the follOWing.
• Addition of harmOniCs In all the other
Input states of 151 and 152
• All pulse duration values
• Other even harmOniC frequencies.

Optical Output (OPT)
The OPT output IS deSigned to drive an
optical Signal transducer or lamp. It IS LOW
when the ringer circuit IS enabled and HIGH
when the ringer CirCUit IS disabled. ThiS output
can also be used to SWitch the transmitter ON
and OFF In the base of a cordless telephone
set.

APPLICATION INFORMATION
Application of the PCD3360 In a telephone
ringer circuit together With a loudspeaker IS
shown In Figure 6
The threshold levels VH and VL of the frequency diSCriminator CirCUit are determined
by
• The logiC threshold of Input FDI (0.5VDD
typ 34V for VDD = 6 BV)
• The pull-down current of Input FDI
(20j.lA typ for FDI < 34V)
• The value of R2 (6BO kn In Figure 6)
For a positive slope, the voltage at R2 must
exceed the value VH before FDI will become
HIGH, VH IS the sum of the Input threshold
and the voltage drop across R2, thus:

December 2, 19B6

6-87

PCD3360

VH = 3.4 + (6BO X 103) X (20 X 10- 6) = 17V.
For a negative slope, the voltage at R2 must
decrease below the value VL before FDI Will
become LOW. Because the current Into FDI
IS negligible With FDI = HIGH, the voltage
drop across R2 can be discounted, thus
VL = 3.4V.
The minimum operating voltage across C3 is
17.7V which IS determined by'
• The minimum operating voltage of the
PCD3360 (5.7V)
• The supply current of the PCD3360
(120j.lA maximum)
• The value of R3 (100kn In Figure 6)
The total SWitch-on delay equals approxImately the time reqUired to charge the supply
capacitor C3 to the minimum operating value,
plus the speCified SWitch-on delay of the
PCD3360.
The high operating voltage combined With the
class D output stage ensures optimal energy
conversion and thereby a high sound level.
The deSign can eaSily be optimized for parallel or series connection of more than one
ringer. The diode bridge, zener diode (Dl)
and resistor Rl protect the nnger against
transients up to 5kV. DUring these surges the
voltage on the 6BV zener diode (BZW03) can
rise to 100V; the DM05 transistor B5T72
(TR1) has a maximum-drain source voltage of
100V. Up to 220V, 50Hz can be applied to the
AlB terminals Without damaging the ringer
The choke (L 1) In series With the 50n loudspeaker Increases the sound pressure level
by approximately 3dB by suppression of the
32kHz carner frequency and Its Sidebands
The flyback diode BAXl BA (D2) IS a fast type
With low forward voltage to obtain high efficiency
Application of the PCD3360 together With a
PXE transducer IS shown In Figure 7 The only
Significant difference between Figure 6 and
Figure 7 IS the output stage. Two B5T72
transistors prOVide an output voltage sWing
almost equal to the voltage at C3 Pins 151
and 152 are inoperative because DM = HIGH.
Volume control IS pOSSible uSing resistor Rv.

6

Product Specification

Signetics Unear Products

PCD3360

Programmable Multi-Tone Telephone Ringer

DEVELOPMENT SAMPLE OATA

Voo

I

OM- HIGH
(PXE)

v..
I FUND

OM

= LOW
(LSI')

v..

= 48

I
I

)( 3125

= 15OOp.s

---J-~~,!~~~tttt11lr[[llr ttt~l~~~~b-.-.-.-~.~ __ .~~.__d~J-J~H~~ttt
48

30

10

31.25,us

"""70S

NOTE:
For lose = 64kHz, to prOVIde ICK = 32kHz,

OM = LOW
(LSI')

v..

Figure 4. Fundamental Signal (667Hz) at Pin TONE

1.111,11111,111111111'111111111111111,11,111.1.111, .....
LtHARM = 12 )( 31.251:
1

0

___1~~_
o

3751'-$.-J

IFUND

iii

DURATK)N

NOTE:
For lose = 64kHz, to prov,de ICK

="

20

___

30

J

1.1.1.1.1. , ... 1.111.11111.11111
40

= 48 )( 31.25 = 1500p.s

l~~~DURAOON

=

'H

= 32kHz,

Figure 5. Fundamental Signal (667Hz) + Harmonic Signal (2667Hz) at Pin TONE

December 2, 1986

6-88

48
Ii

1

-1t31.251'.

Product Specification

Signetlcs Linear Products

PCD3360

Programmable Multi-Tone Telephone Ringer

DI
R3
lOOk

BZW03

-C68

C2
10nF

D3
BZX79

-ceV8

J

AlB

!!.. tv,

lN5060
(4x)

C3

+

10,uF

C4
56pF

R2
FDI

CI

680k

Rl

osc

PCD3360
BST72

BIA--i
I~F

I.
(SW)

365k

R4

-=

v~IL--_----'L-__----'____

•

Figure 6. Transformerless Electronic Ringer With PCD3360 and a Loudspeaker

Dl
R3

BZW03

-C68

lOOk

C2
10nF

lN5060
(4x)

C3

AlB----<.J

C4
56pF
R2

+-o/II'>/'-f--+--I--If---I FDI
C1

BIA - - i

R1

680.

OPT

PCD3360

OSC

TONE~---'-~"'''---

i--''''''.....f-...J

1.uF

1k
(SW)

365.

R4 ....,.;......,..-r--...,-"T"-~

Figure 7. PCD3360 Ringer With PXE Transducer

December 2, 1986

6-89

CJ

PXE
TRANSDUCER

+

PCD4415/A

Signetics

Pulse and DTMF Dialer with
Redial
Product Specification

Linear Products

DESCRIPTION
The PC04415! A is a single-chip silicon
gate CMOS integrated circuit with an onchip oscillator for a 3.58MHz crystal. It is
a dual-standard dialing circuit for either
pulse dialing (PO) or dual tone multifrequency (OTMF) dialing.

PIN CONFIGURATIONS
0 1 Package

N Package
OSCO

OSCO

Input data is derived from any standard
matrix keyboard for dialing in either PO
or OTMF mode. Numbers of up to 23
digits can be retained in RAM for redial.
In OTMF, mode bursts as well as pauses
are timed to a minimum; in manual
dialing the maximum depends on the key
depression time.

VDD

YDD

CE

CE

M1

M1

M2

lAP

DP/FLO

DP/FLO

DP/FLO

COL 3

COL 3

COL 2

COL 2

COL 1

COL 1

ROW 1

FEATURES
• Pulse and DTMF dialing
• 23-digit capacity for redial
operation
• Three dialing modes: Pulse,
DTMF, and data transmission
(DTMF)
• Redial buffer for PABX and
public calls
• Three function keys: • or >,
or R/AP, and FL (flash)

NOTE:
1 Available In large SO package With different pinout.
PIN
NO.
1
2

• Telecom terminal equipment

July 6, 1988

OSCI
PD/DTMF
TONE

Vss

#

• DTMF timing:
manual dialing - minimum
duration for bursts and pauses
redialing - calibrated timing
• On-chip voltage reference for
supply and temperature
independent tone output
• On-chip filtering for low output
distortion (CEPT CS 203
compatible)
• Uses standard single-contact or
double-contact (common left
open) keybDard
• Keyboard entries fully debounced
• Flash (register recall) output

APPLICATIONS

PIN
NO.
Supply

DESCRIPTION

SYMBOL

Supply

9
10

11
12
13

,.
15
16
17
18
19
20

lAP
ROW 5
ROW'
ROW 3
ROW 2
ROW 1
COL 1
COL 2
COL 3
OP/FLO
DP/FLO
M2
M1
CE

Voo
OSCO

Oscillator Input
Select pm, pulse or DTMF
dialing
Single or dual tone frequency
output
Negative supply
Input access pause
Scanning row keyboard
mput/outputs

Sense column keyboard Inputs
With Internal pull-ups
Dialing pulse and flash output
Dialing pulse and flash output
Strobe, active HIGH dUring
transmission
Muting output
Chip enable Input
PoSItive supply
OSCillator output

SYMBOL

OSCI
PD/DTMF
TONE

Vss

9
10
11
12
13

,.
15
16
17
18

ROW 5
ROW.
ROW 3
ROW 2
ROW 1
COL 1
COL 2
COL 3
DP/FLO
lAP
M1
CE

Voo
OSCO

DESCRIPTION

OSCillator Input
Select pm, pulse or OTMF
dialing
Smgle or dual tone frequency
output
Negative supply

Scanning row keyboard
mput/outputs
Sense column keyboard Inputs
With Internal pull-ups
Dialing pulse and flash output
Input access pause
Muting output
Chip enable Input
PoSItive supply
OSCillator output

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

1B-Pin Plastic DIP
(SOT-102)

DESCRIPTION

-25°C to + 70°C

PCD4415PN

20-Pin Plastic SOL;
(SO-20; SOT-163A)

-25°C to + 70°C

PCD4415TD

18-Pin Plastic DIP
(SOT-102)

-25°C to +70°C

PCD4415APN

20-Pin Plastic SOL;
(SO-20; SOT-163A)

-25°C to +70°C

PCD4415ATD

6-90

853-1117 94028

Product Specification

Signetics linear Products

PCD4415jA

Pulse and DTMF Dialer with Redial

BLOCK DIAGRAM (D Package)

r-----------------1-______-11~4~(1~3~) DP~

PCD441S/A

L.______-,~--~--j-------~1IS~~ DP~
...____.:2.&.(_2).. PD/DTMF

OUTPUT

MGlAlSNTER

-1 RE

........&.....

ADDRESS
DECODING

19 (17) Voo

~~=

CONTROLLER

OUTPUT

4 (4)
TEMPORARY
REGISTER

V..

READ!
WRITE
3 (3)

TONE

•
ROWS ROW4 ROW3 ROW2 ROW1 COLI

COL2 COL3

lAP M2 Ml

osa osco

CE

NOTE:
Pin numbers for N package are In parentheses

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VDD

Supply voltage range

IDD

RATING

UNIT

-0 B to B

V

Supply current

50

rnA

±II.
±VO

DC current Into any Input or output

10

rnA

VI

All Input voltages

-OBV to VDD
+0.8

°C

PTOr

Total power diSSipation

300

mW

Po

Power diSSipation per output

50

mW

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-25 to +70

°C

July 6, 1988

6-91

Signetlcs linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD4415/A

DC ELECTRICAL CHARACTERISTICS voo = 3V; Vss = OV; crystal parameters: fose = 3.579545MHz; Rs = 100n max.;
TA = -25 to + 70·C; unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Typ

Max

Supply
Voo

Operating supply voltage

2.5

6.0

V

VODO

Standby supply voltage

1.8

6.0

V

looc
loop
IOOF
IOOF

Operating supply current2
conversation mode (oscillator ON)
pulse dialing or flash
DTMF dialing (tone ON)
DTMF dialing (tone OFF)

IODO

150
200
0.9
200

Standby supply current 1
(oscillator OFF)

5

Voo= 1.8V
TA = 25·C

IlA
IlA
rnA

IlA
IlA

Inputs
VIL

Input voltage LOW (any pin)

0

0.3Voo

V

VIH

Input voltage HIGH (any pin)

0.7Voo

Voo

V

IIILI

Input leakage current; CE
Keyboard Inputs
Keyboard ON resistance
Keyboard OFF resistance

RKON
RKOFF

1

IlA

2
1

kn
Mn

VOL = Vss +0.5V
Ml, M2, DP/FLO
DP/FLO

0.7

mA

VOH = Voo-0.5V
Ml, M2, DP/FLO

0.6

mA

Outputs
IOL

-IOH

Output sink current

Output source current

Timing and Frequency
toN

Clock start-up time

4

ms

tE

Debounce ume

12

ms

tRO

Reset delay time

152

160

168

ms

158
125

192
150

205
160

mV
mV

+0.6

%

0.1

0.5

kn

2.1

2.35

Tone output (see Figure 1)

VHG(RMS)
VLG(RMS)

DTMF output voltage levels (RMS value)
HIGH group
LOW group

tollf

Frequency deviation

Voc

DC voltage level

1201

Output impedance

RL

Load resistance

toVG

Pre-emphasis of group

THD

Total harmonic distortlon2

July 6, 1988

at Voo = 2.5 to 6V

-0.6

V

0.5Voo

10
1.85
at TA = 25·C

6-92

kn

-25

dB
dB

Signetics Unear Products

Product Specification

Pulse and DTMF Dialer with Redial

DC ELECTRICAL CHARACTERISTICS (Continued)

PCD4415/A

voo = 3V, vss = OV; crystal parameters. fosc = 3 579545MHz,
Rs = lOon max., T A = -25 to + 70°C; unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

Transmission and pause time 3
tT

Manual and data transmission dialing
mode

65

tp

Redlaling

65

tT

Redlaling

65

70

75

tp

Redlaling

65

70

75

ms

tFL

Flash pulse duration

95

100

105

ms

tFLH

Flash hold-over time

32

34

36

ms

ms
ms
ms

Pulse dialing (PD)3
fop

Dialing pulse frequency

98

10

10.4

Hz

tiD

Inter-digit pause

800

840

880

ms

Is

Break tlme4 , 5

64

66/60

68

ms

1M

Make tlme 4 , 5

32

34/40

36

ms

NOTES:
1 Crystal connected between OSCI and OSCO, CE at Vss and all other pins open-Circuit
2. Related to the level of the LOW group frequency component (CEPT CS 203)
3 Other timing IS possible on request
4. Mark-to-space ratio 2 1
6. A version mark-to-space ratio 3 2

HANDLING
Inputs and outputs are protected against
electrostatic charge In normal handling. However, to be totally safe, It IS deSirable to take
normal precautions appropnate to handling
MaS deVices.

Without delay regardless of the state of chip
enable Input (CE).

Clock Oscillator (aSCI, OSCO)
The time base for the PCD44151 A for both
PO and DTMF modes IS a crystal controlled
on-chip OSCillator which IS completed by connecllng a 3 58MHz crystal between the ascI
and OSCO pins.

Chip Enable (CE)
Voo

1,,1'

PC04415 TONEHH~--.

Figure 1. Tone Output Test Circuit

FUNCTIONAL DESCRIPTION
Power Supply (VDD; VSS)
The positive supply of the CirCUit (VOO) must
meet the voltage reqUIrements as Indicated In
the charactenstlcs.
To aVOid undefined states of the deVice when
powered-on, an Internal reset CirCUit clears
the control logiC and counters.
If Voo drops below the minimum standby
supply voltage of 1.8V, the power-on reset
circuit ,nh,bits redlaling after hook-off The
power-on reset signal has the highest pnonty.
It blocks and resets the complete CirCUit
July 6, 1988

The CE Input enables the CirCUit and IS used
to Initialize the IC
CE = LOW provides the StatiC standby condition In thiS state the clock OSCillator IS diSabled, all registers and logiC are reset With the
excepllOn of the Wnte Address Counter
rN AC) which pOints to the last entered digit
(see Figure 3). The keyboard Input IS InhibIted, but data preViously entered IS saved In
the redial register as long as VDO IS higher
than VODO(mln)'
The current drawn IS 1000 (standby current)
and serves to retain data In the redial register
dunng hook-on. CE = HIGH activates the
clock OSCillator and the CirCUit changes from
static standby condition to the conversation
mode. The current consumption is IDDc until
the first digit IS entered from the keyboard.
Then a dialing or redlaling operation starts.
The operallng current IS loop If In the pulse
dialing mode, or 100F If the DTMF dialing
mode IS selected. If the CE Input IS taken to a
LOW level for more than time tRO (see

6-93

Figures 7a, 7b and timing data), the system
changes to the static standby state and the
oscillator stops running. Short CE pulses of
lAD will not affect the operation of the cirCUit
and reset pulses are not produced.

Mode Selection (PD/DTMF)
PO mode
If PDIDTMF = Vss the pulse dialing mode IS
selected.
DTMF mode
If PDIDTMF = Voo the dual tone multi-frequency dialing mode IS selected. Each numenc push-button activated corresponds to a
combination of two tones, each one out of
four possible LOW and HIGH group frequenCies. The frequencies are transmitted With a
constant amplitude, regardless of power supply vanatlons, and filtered off harmonic content to fulfill the CEPT CS 203 recommendations.
The transmission time IS calibrated for redial.
In manual operallOn the duration of bursts
and pauses IS the actual pushbutton depress
time, but not less than the minimum transmission time (tT) or minimum pause time (tp).
Data transmission mode
Data transmission mode IS entered from the
dialing mode (PO or DTMF) on first depression of key" *", or key" > ". The" *" tones
are not transmitted.

6

Product Specification

Signetlcs Unear Products

Pulse and DTMF Dialer with Redial

In the data transmission mode no digits are
stored for later redial; "*" and "#" are
purely DTMF keys, so are no longer special
functions. The digits are temporarily stored In
a special register, which has a maximum
capacity of eight digits.
There are two ways to lease the data transmission mode:
• Reactivate chip enable (CE), HIGH to
LOW then HIGH again
• Pressing the flash (FL) key
Keyboard Inputs/Outputs
The sense column Inputs COL 1 to COL 3
and the scanning row outputs ROW 1 to
ROW 5 of the PCD44151 A are directly connected to the keyboard as shown In Figure 2.
All keyboard entries are debounced on both
the leading and trailing edges for approxImately time tE as shown in Figure 7. Each
entry IS tested for validity.
When a pushbutton is pressed, keyboard
scanning starts and only returns to the sense
mode after release of the push-button.
Keys "." and "#" represent the DTMF
tones and also special dialing functions. In
ROW 5 the keys " >" and R/ AP only are
function keys, whde key FL offers flash or
register recall.
ROWS

---COLUMNS

123

~:

I I

2

3

5

6
9

7

8

•

0

>

FL

#
RI

AP

KEYBOARD

Figure 2_ Keyboard Organization

Flash
Flash (or register recall) is activated by the FL
key and can be used in DTMF, pulse and data
transmission modes. Pressing the FL pushbutton Will produce a timed line-break of
lOOms at the DP/FLO output. During the
conversation mode this flash pulse entry Will
act as a chip enable. ThiS flash pulse duration
(tFU IS calibrated at lOOms.
The flash pulse resets the read address
counter (RAC). Later redial IS possible (see
redial procedure With the "Flash" Inserted
telephone number).

TONE Output (DTMF mode)
The single and dual tones which are provided
at the TONE output are filtered by an on-chip
July 6, 1988

PCD4415/A

Table 1_ Frequency Tolerance of the Output Tones for DTMF
Signaling
ROW/
COLUMN
Row
Row
Row
Row

FREQUENCY
DEVIATION

STANDARD
FREQUENCY HZ

TONE OUTPUT
FREQUENCY HZ(I)

%

Hz

697
770
852
941

697.90
770.46
850.45
943.23

+0.13
+0.06
-0.18
+0.24

+0.90
+0.46
-1.55
+2.23

1209
1336
1477

1206.45
1341.66
1482.21

-0.21
+0.42
+0.35

-2.55
+5.66
+5.21

1
2
3
4

Coil
Col 2
Col 3

NOTE:
1. Tone output frequency when using a 3.579545MHz crystal.
switched-capacitor filter, followed by an
on-chip active RC low-pass fdter.
Therefore, the total harmOniC distortion of the
DTMF tones fulfills the CEPT CS 203 recommendations. An on-chip reference voltage
provides output-tone levels Independent of
the supply voltage. Table 1 shows the frequency tolerance of the output tones for
DTMF signaling.
When the DTMF mode IS selected, output
tones are timed In manual dialing w~h a
minimum duration of bursts and pauses, and
In redial with a calibrated timing. Single tones
may be generated for test purposes
(CE = HIGH). Each row and column has one
corresponding frequency. High group frequencies are generated by connecting the
column to Vss. Low group frequencies are
generated by forCing the row to V DD. The
Single tone frequency Will be transmitted
dunng activation time, but it IS neither calibrated nor stored.

Mute Output (M1)
Inverted output of MI. In the PCD44151 A it is
only avadable as a bonding option of MI.

Strobe Output (M2)
Active-HIGH output during actual dialing, i.e.,
during break and make time In pulse dialing,
or during tone transmission in DTMF dialing.
Only available as a bonding option of lAP.

Input Access Pause (lAP)
ThiS input can be used Instead of the" #"
(RI AP) key for programming access pause(s)
In RAM when dialing and terminating access
pause(s) dunng redial.

Data Transmission Mode
Timing In the data transmiSSion mode IS the
same as the manual dialing mode.

Dialing Procedures (see also
Figures 4, 5 and 6)

Mute Output (M1)

Dialing
After CE has nsen to VDD, the oscillator starts
running and the Read Address Counter (RAC)
IS set to the first address (see Figure 3). By
entering first a numeric digit, the Write Address Counter (WAC) will be set to the first
address, the decoded digit will be stored in
the register and the WAC Incremented to the
next address. Any subsequent keyboard entry
will be decoded and stored in the redial
register after validation. If more than 23 digits
are entered, redial will be inhibited. All entries
are debounced on both the leading and
trailing edges for at least time tE as shown in
Figure 7. Each entry IS tested for validity
before being deposited In the redial register.

During pulse dialing the mute output becomes
active-HIGH for the penod of the Inter-dlg~
pause, break time and make time. It remains
at this level until the last digit IS pulsed out.
Dunng DTMF dialing the mute output becomes active-HIGH for the penod of the tone
transmission and pause times. Dunng Flash
the mute output is active-HIGH and remains
at thiS level for the penod of flash and flash
hold-over time

In manual dialing mode (pulses and DTMF)
only the 0 to 9 keys result in dialing operations. "#" and "." are special function keys:
• If the first key after CE or Flash
means: Redial (see redial procedure)
• If not the first key, then it is used to
program access pause(s) in the RAM
for later redial. If it is the last key it will
be omitted before going "on-hook".

Dial Pulse and Flash Output
(DP/FLO)
ThiS is a combined output which proVides
control signals for proper timing In pulse
dialing or for a calibrated break In both dialing
modes (flash or register recall).

Dial Pulse and Flash Output
(DP/FLO)
Inverted output of DP/FLO. In the PCD4415/A
it IS only available as a bonding option of
DP/FLO.

6-94

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

"." key or "

>"

key

PCD4415/A

RI AP keys are active only dUring access

• Used to switch from dialing mode (pulse
or DTMF) to data transmission mode.
The "." tones will not be transmitted
even If the prevIous mode was DTMF
dialing.
In data transmission mode keys 0 to 9, "."
and" #" result in associated DTMF tones
(see Table 1), keys > and RI AP will be
Ignored.
Redialing
After CE has risen to Voo, the oscillator starts
running and the Read Address Counter (RAG)
IS set to the first address to be sent. The
PCD44151 A is In conversation mode. If "#"
or "R/AP" is the first keyboard entry, the
CirCUit starts redlaling the contents of the
register. Timing In the DTMF mode IS calibrated for both tone bursts and pauses. Only
the first part entered (the pulse or DTMF
dialed part of the stored number) can be
redialed. DUring redial keyboard entries (function or non-function) are not accepted until
the CirCUit returns to the conversation mode
after completion of redlaling. The" #" and

pauses.

No redial activity takes place If one of the
following events occur:
• Power-on reset
• Memory overflow (more than 23 valid
data entries)
If an access pause is detected dUring redial,
the circuit IS switched back to the conversation mode and stays there until the "#" or
RI AP key is depressed. Therefore, when the
" #" or RI AP key is depressed, the access
pause IS ended. After termination of the
access pause, the CirCUit continues dialing
the rest of the telephone number.

In addition to the manual use of the # or RI
AP key for programming and terminating
access pause(s}, the input lAP can be used. If
dUring manual dialing and conversallon mode
lAP becomes HIGH, an access pause will be
stored In the memory.
If, after "on-hook" or "flash", the last stored
digit IS an access pause, then it will be
deleted out of the memory. When dUring

redlallng an access pause occurs and lAP
becomes HIGH, then the access pause will
be automatically terminated and redlallng
continues.
As soon as the conversation mode IS entered,
depreSSing the "." or ">" key will again
sWitch the CirCUit to the data transmission
mode.
Redial takes place in the main register (max.
23 digits). After redial when a numeriC key IS
pressed (first digit of an extension number)
the redial number will be cleared. Thus the
total capacity of the main register is available
for extension number dialing. This extension
number IS stored In the main register (max 23
digits) and IS available later after" on-hook",
"off-hook". The main register will also store
digits that have been keyed-In at a rate faster
than dialed out

Access pause
• The number of access pauses IS
unlimited.
• Consecutive pauses will be stored as a
Single pause.

•

~

ADDRESSED THROUGH
POINTERS W OR R

6

5
4
ADDRESSED THROUGH
TEMPORARY POINTERS
WORR

3
2

1
MAIN REGISTER

WRITE ADDRESS COUNTER (WAC)

DATA REGISTER

~_ _ _ _ _ _ _--1

!

I

TEMPORARY WRITE ADDRESS
COUNTER (TWAC)
L
_ _ _ _ _ _ _ _---J

READ ADDRESS COUNTER (RAe) L__ _ _ _ _ _ _--1
ADDRESS COUNTER

TEMPORARY ADDRESS COUNTER

Figure 3. Memory Organization

July 6, 1988

6-95

Signetics linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD4415/A

DIAL

•..

CONVERSATION

MODE

STANDBY
MODE

-

PULSe OR
TONE OUT

Figure 4. Pulse/DTMF Dialing Mode

July 6, 1988

6-96

Signetics linear Products

Product Specification

Pulse and DTMF Dialer with Redial

PCD4415/A

DIAL

FLASH

OFF.HooK

1-----DlAUNG

SET IN DlAUNG

DlAL-olJT

AUTOMATIC SWITCH
TO DATA
TRANSMISSION MODE

OATA

STORE
ACCESS PAUSE

L..-_...,..._---'

TONE·OUT

REDIAL

REDIAL

DlAUNG
TERMINATE
ACCESS PAUSE
DIAL OUT

Figure 5. Pulse/DTMF Dialing and Data Transmission Mode

July 6, 1988

6·97

Figure 6a. Flash: Independent of
Dialing Mode

•

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

TIMING

CE

~

PCD4415/A

f-tAO-J
--LJ--

KEYBOARD

ENmv

Ml

(M2)

DP/FlO

CONVERSATION
MODE

CONVERSATION
STATIC
MODE
STANDBY
MODE

(AWAIT OIAUNG
TONE)

OTMF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Figure 6b. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing (PD/DTMF = Vssl

r--_ _ _ _ _--;f.tRr-0~!.....__ _ _ _.......,..,..~~-CE-.J

U

(NO EFFECT)
KEYBOARD

~

__ L,
I

ENTRY

Ml

(M2)

DTMF

DP/FLO

Figure 6c. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; DTMF Dialing (PD/DTMF = VDO )

July 6, 1988

6-98

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer with Redial

I

-I

PCD4415/A

I

#(»

'E

-li'E
I

(M2)
PULSE DlAUNG

- - - t - - - DATATRANSMtSSlON MODE

Figure 6d. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing
and Data Transmission Mode

•

July 6, 1988

6-99

Product Specification

Signetics Linear Products

Pulse and DTMF Dialer with Redial

CE

PCD4415/A

J

KEYBOARD
ENTRY

A
I

A
I

-j f-I.
M1

DIAL TONE

-I f-I.
Ip

I

L___

I

DTMF

0

TN

Figure 7a. Timing Diagram Showing REDIAL Where PABX Access Digit(s) are the First Keyboard Entries and Access
Pause is Terminated by the # or R/AP Key; DTMF Dialing with PD/DTMF VDD

=

CE

KEYBOARD
ENTRY
(ALSOR/AP)

J
A
I

--j ~I.
M1

OIALTONE

L___

Ip

I

lAP

DTMF

0

TN

Figure 7b. Timing Diagram Showing REDIAL Where PAB)LAccess Digit(s) Occur and are Terminated by lAP;
DTMF Dialing with PD/DTMF = VOD

July 6, 1988

6-100

I!l

E-

."
C

o<
S1'

rn,
+_ +

SYllMEllllCAL~ ~

,z,'~'50A

~

1z,1,,'50

,.n, ASYllME1AICAL ........1IPEDANCE INPUTS FOR ELEcrAlCAL ..CIIOPHDOIES
+- +(TEA .06.)

tm~
..""

S.I
I

10V

~

C••

L.

2.2~F

•

.%

:~

0
-t

s:

G

~
AlB
UNE

-~
(. U

TEA 1060}61

.%

R.
• 30k

•
.%

.%

2

.8

.6

17

"

f---,
+

4.7 +

: ~:v

"'?r"

R3
3.92k

II

OTMF

fl~
2'i~

14

f;'

'00

rov~ 2.2}Jf

I
I
I

I
I

I
IL

I

Rl1
'30

I

f:ij~'21II
820

220

'Ok

"

1%
R9

R6

20

110k

.

tt- r---• TONE

56k

Q.

@-

:E

=+

••

;;C

COL'

~I2 •

CD

a.

C·

!..-

••
TO_

Vee

~

~ ~
.%

COL'

1SOnF

~

10

nF

(3

c

':J

11

390

r - ------,

CE

COL'

R8

BIA

••

'20k

VDD

Vee

AGC

R7
68k

+ "

•

8



• •
•
"

8
0

FL : ,

PCD441SAN

56k
470k

J2
',(1)

••

OFIFLO

••

M'

• v..

nF

_...1
_____
...J

B~.

T~I\
~

I"·

470k

~-~

PD/DTW

SELECT PIN

~~I
C.O

'10k

'OM

P

~
~
~

...:..

NOTES,
1. AutomatiC line compensatIOn obtained by connectmg R6 to Vss.
2 The value of reSistor R14 IS determined by the required level at LN and the DTMF gain of the TEA1060/61
3. Omit C13 and C14; Insert 81.

•

Figure B. Application Diagram of the Full Electronic Basic Telephone Set

(11

»

..,

8.c

Q.

~
8g

Signe1ics

TEA1060j61
Versatile Telephone
Transmission Circuits with
Dialer Interface

Linear Products

Product Specification

DESCRIPTION
The TEA1060 and TEA1061 are bipolar
integrated circuits performing all speech
and line interface functions required in
fully electronic telephone sets. The circuits internally performs electronic
switching between dialing and speech.

FEATURES
• Voltage regulator with adjustable
static resistance
• Provides supply for external
circuitry
• Symmetrical low-impedance
inputs for dynamic and magnetic
microphones (TEA 1060)
• Symmetrical high-impedance
inputs for piezoelectric
microphone (TEA1061)

• Asymmetrical high-impedance
input for electret microphone
(TEA1061)
• DTMF signal input
• Mute input for pulse or DTMF
dialing
• Power down input for pulse dial
or register recall
• Receiving amplifier for magnetic,
dynamic or piezoelectric
earpieces
• Large amplification setting range
on all amplifiers
• Line loss compensation facility,
line current dependent
• Gain control adaptable to
exchange supply

PIN CONFIGURATION
N Package

Vee
MUTE
DTMF

lOP VIEW
0011540&

PIN NO.

1
2

SYMBOL
LN
GAS1

GAS2
OR-

APPLICATION

OR+

• Electronic telephone sets

GAR

ORDERING INFORMATION
DESCRIPTION

ORDER CODE

-25 to +75°C

TEA1060PN

10

VEE

11

TEA1061PN

12
13

IR
PO
OTMF
MUTE

18-Pln Plastic DIP (SOT-l02A)

-25 to +75°C

PARAMETER

RATING

UNIT

VLN

Positive line voltage

13.2

V

ILlNE(AV)
ILlNE(S)
ILlNE(SM)

Line current
average
non-repetitive (tMAX = 100 hours)
non-repetitive peak (tMAX = 1ms)

140
250
1

mA
mA
A

Vcc + 0.7
0.7

V
V

V
-V

Voltage on all other pins

PTOT

Total power dissipation

TSTG

Storage temperature range

TA

Operabng ambient temperature range

9

"

ABSOLUTE MAXIMUM RATINGS

August 1, 1988

MICMIC+
STAB

TEMPERATURE RANGE

18-Pln Plastic DIP (SOT-l02A)

SYMBOL

7
8

660

mW

-65 to +150

°C

-25 to +75

°C

6-102

15
16
17
18

vee
REG
AGC
SLPE

DESCRIPTION
Positive hne terminal
Gam adjustment,
transmlUlng amplifier
Gain adjustment,
transmitting amplifier
Inverting output,
receiVIng amplifier
Non-Inverting output,
recelvmg amplifier
Gam adjustment,
recelVlng amplifier
Invertmg microphone mput
Non-Inverting mICrophone Input
Current stabilizer
NegatIVe Ime termmal
RecelVfng ampllfler Input
Power·down Input
Dual-tone mutll-frequency Input
Mute Input
POSItive supply decoupllng
Voltage regulator decouplmg
Automatic gain control mput
Slope (DC resistance)
adjustment

853-1049 94026

Signetics Unear Products

Product Specification

Versatile Telephone Transmission Circuits
with Dialer Interface

TEA1060j61

BLOCK DIAGRAM
LN

"
IR~11t-------t--------------1

~

________

~~~GM

~--1--1r-o OR<
~--1HI-'-o OR-

llte<

.....

IIIC-

DTMF

MI/T1!

PO

....

"

,.
,.

18

VEE

REG

sr.a

NOTEs.
The blocks marked "dB" are attenuators

The block marked (1) IS only present In the TEA 1061

August 1, 1988

6·103

aPE

•

Signatlcs Linam Products

Product Specification

Versatile Telephone Transmission Circuits
with Dialer Interface

TEA1060/61

DC ELECTRICAL CHARACTERISTICS ILiNE = 10 to 140mA; VEE = OV; f = 800Hz; TA - 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

4.15
5.4

4.15
4.35
6.1

-4

Max

Supply: LN and Vee (Pins 1 and 15)
VLN
VLN
VLN
VLN

Voltage drop over circuit
at ILiNE= 5mA
at ILiNE = 15mA
at ILiNE = 100mA
at ILiNE = 140mA

~VLN/~T

Variation with temperature at ILiNE = 15mA

Icc
Icc

Supply current
at Vcc = 2.8V; PO = LOW
at Vcc = 2.8V; PO = HIGH

4.55
'6.7
7.5

V
V
V
V

-2

0

mVloC

0.96
50

1.25

mA
pA

Microphone inputs MIC+ and MICIZlsl
IZlsl

Input Impedance
TEAl 060
TEAl 061

4
20

kn
kn

a

Standard deViation on input impedance

12

%

kCMR

Common-mode rejection ratio; TEAl 060

80

dB

Avo
Avo

Voltage amphfication at
ILiNE = 15mA; R7 = 68kn
TEAl 060
TEAl 061

~vo/~f

Vanatlon with frequency
at f = 300 to 3400Hz

±0.2

dB

~vo/~T

Vanation with temperature at
ILiNE = SOmA; TA = -25 to +75°C

±0.5

dB

51
37

52
38

53
39

dB
dB

Dual-tone multi-frequency input DTMF
Izisl

Input impedance

20

kn

a

Standard deViation on input impedance

12

%

Avo

Voltage amphflcatlon
at ILiNE = 15mA; R7 = 68kn

~vo/~f

Variation with frequency
at f = 300 to 3400Hz

±0.2

dB

~vo/~T

Vanatlon with temperature at
ILiNE = SOmA; TA=-25 to +75°C

±0.5

dB

25

26

27

dB

Gain adJustment (Pins GAS1 and GASz)
~vo

Amplification vanation with R7, transmitting amplifier

-8

+8

dB

Transmitting amplifier output LN
VLN(RMS)
VLN(RMS)

Output voltage at ILiNE = 15mA;
dTOT = 2%
dTOT= 10%

VNO(RMS)

NOise output voltage
at ILiNE = 15mA; R7 = 68kn
psophometrically weighted (P53 curve)

1.4

2.3
2.6

V
V

-70

dBmp

Receiving amplifier input IR
IZlsl

August 1, 1988

Input Impedance

17

6-104

21

25

kn

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
with Dialer Interface

TEA1060/61

DC ELECTRICAL CHARACTERISTICS (Continued) ILiNE = 10 to 140mA; VEE = OV; f = 800Hz; TA = 25°C, unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Typ

Min

Max

Receiving amplifier outputs QR+ and QR-

IZosl

Output Impedance; single-ended

Avo
Avo

Voltage amplification
at ILiNE = 15mA; R4 = 100kn;
single-ended; RL = 300n
differential; RL = 600n

4

t:.Avo/  Icc + 0.5mA + Icc The static
behaVior of the Circuit then equ&ls a 4.1 V
voltage regulator diode With an Internal resIStance R9. In the audiO frequency range the
dynamiC impedance equals Rl.
The current Icc available from Vcc for supplyIng peripheral CirCUitS depends on external
components, and on the line current. Figure 2
shows thiS current for Vcc = 3V min., thiS
being the minimum supply voltage for most
CMOS cirCUits including a diode voltage drop
for an enable diode. If MUTE IS LOW, the
available current IS further reduced when the
receiving amplifier IS dnven.

Microphone Inputs MIC + and
MIC - and Gain Adjustment
Pins GAS 1 and GAS 2
The TEAl 060 and TEAl 061 have symmetrical microphone Inputs.
The TEA1060 is Intended for low-sensitivity,
lOW-Impedance dynamiC or magnetic micro-

August 1, 1988

When the DTMF Input IS enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTMF to LN IS tYPically
26dB and vanes with R7 in the same way as
the amplification of the microphone amplifier.
The Signalling tones can be heard In the
earpiece at a low level (confidence tone).

Receiving Amplifier: IR, OR + ,
OR- and GAR
The receiVing amplifier has one Input IR and
two complementary outputs, a non-Inverting
output OR + and an Inverling output OR - .
These outputs may be used for Single-ended
or for differential dnve, depending on the
sensitivity and type of earpiece used (see
Figure 6). Amplification from IR to OR + IS
tYPically 25dB. ThiS Will be sufficient for lowImpedance magnetic or dynamic earpieces;
these are SUited for single-ended drive. By
uSing both outputs (dlfferenlial drive) the
ampllficalion IS Increased by 6dB. ThiS makes
dlfferenlial drive pOSSible, which IS reqUired
for high-Impedance dynamiC, magnetic and
piezoelectriC earpleces with load Impedances
exceeding 450n.
The output voltage of the receiVing amplifier
is specified for continuous-wave drive. The
maximum output voltage will be higher under
speech conditions, where the ratio of peak
and RMS value IS higher.

6-106

TEA1060j61

The amplification of the receiving amplifier
can be adjusted over a range of + 8dB to SUIt
the sensitivity of the transducer used. The
amplification IS proportional to external resIstor R4 connected from GAR to OR + .
Two external capacitors C4 = 100pF and
C7 = lOX C4 = 1n F are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order, low-pass filter. The
"cut-off" frequency corresponds with the
time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor R6 from
AGC to VEE. ThiS automatic gain control
varies the amplification of the microphone
amplifier and the receiVing amplifier In accordance With the DC line current. The control
range IS 6dB. ThiS corresponds With a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable with a DC resistance of
176rl/km and an average attenuation of
1.2dB/km.
Resistor R6 should be chosen In accordance
With the exchange supply voltage and its
feeding bridge resistance (see Figure 5 and
Table 1). Different values of R6 give the same
ratio of line currents for begin and end of the
control range.
If automatic line loss compensation is not
reqUIred AGC may be left open. The amplifiers then all give their maximum amplification
as specified.

Power-Down Input PD
DUring pulse dialing or register recall (timed
loop break) the telephone line IS Interrupted;
as a consequence, It provides no supply for
the transmiSSion circuit. These gaps have to
be bndged by the charge in the smoothing
capacitor C1. The requirements on thiS capacitor are relaxed by applYing a HIGH level
to the PD input, which reduces the supply
current from tYPically 1rnA to typically 501JA.
A HIGH level at PD further disconnects the
capacitor at REG, with the effect that the
Circuit's Impedance equals a 4.1 V voltage
regulator diode with an internal resistance
equal to R9. ThiS results In rectangular current waveforms in pulse dialing and register
recall. When thiS facility IS not required PD
may be left open.

Side-Tone Suppression
Suppression of the transmitted signal in the
earpiece IS obtained by the antl-slde-tone
network consisting of R2, R3, R8. and ZSAl
(see Figure 8). MaXimum compensation is
obtained when ZSAl/k equals the line impedance ZUNE as seen by the set (scale factor
k=Ra /R l)'

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
with Dialer Interface
In practice ZLiNE varies strongly with line
length and cable type; consequently, an average value has to be chosen for ZSAL. The
suppression further depends on the accuracy

TEA1060j61

with which ZSAL/k equals the average line
Impedance.
The anti-side-tone network attenuates the
signal from the line. With R8 = 390n and

R9 = 20n the attenuation is 32dB. The attenuation IS nearly flat over the audio-frequency
range.

-.r

1.5

'---

cc

I

1

+
Cl

'l

b___

S

Jl
0.5

PERIPHERAL

CIRCUITS

i

I
I

_-1

NOTE:

Curve "a" IS valid when the receIVing amplifier IS
not driven or when MUTE = HIGH, curve "b" IS valId when MUTE'" LOW and the receiving amphfler IS
driven, VO(RMS) = 150mV, RL = 1500

Figure 2. Maximum Current Ice
Available from Vee for External
(Peripheral) Circuitry with Vee;;' 3V

Figure 1. Supply Arrangement

I

r--~-""';:.j MIC+

L...-.....--:..jMIC-

NOTE:

The resistor marked (1) may be connected to lower the
terminating Impedance

a. Magnetic or Dynamic
Microphone, TEA1060

b. Electret Microphone, TEA 1061
Figure 3. Alternative Microphone Arrangements

August 1, 1988

6-107

c. Piezoelectric Microphone
TEA1061

Signetics linear Products

Product Specification

Versatile Telephone Transmission Circuits
with Dialer Interface

::~05

QR+[]

TEA1060/61

QR+[)5
(1)

QR+

0
(2)

CJ

V

~

10

~-

4

QRLD07081S

NOTE:
The resistor marked (1) may be
connected to obtain an appropriate
acoustic frequency characteristIc

a. Dynamic Telephone with
Less Than 450>2 Impedance

c. Magnetic Telephone with
More Than 450>2 Impedance

b. Dynamic Telephone with
More Than 450>2 Impedance

Figure 4. Alternative Receiver Arrangements

R6-oo

."'""
"'''

\\
\ \'\
\
r-487kQ\~\ ~O~kQ
\ 1\ \ \
-6
•

kQ

20

60

R9=20Q

100

140

120

160

Figure 5. Variation of Amplification with Line Current, with R6 as a Parameter

Table 1. Values of Resistor R6 for optimum Line Loss
Compensation, for Various Usual Values of
Exchange Supply Voltage VEXCH and Exchange Feeding
Bridge Resistance REXCH
REXCH (>2)
400

600

800

1000

X
68
93.1
120

X
60.4
82
102

R6 (k>2)

VEXCH (V)

August 1, 1988

24
36
48
60

61.9
100
140
X

48.7
78.7
110
X

6-108

QR-

4
LOO7090S

NOTE:
The resIstor marked (2) IS required to
Increase the phase margIn

d. Piezoelectric Telephone

Product Specification

Signetlcs Linear Products

Versatile Telephone Transmission Circuits
with Dialer Interface

TEA1060/61

R1
620

~

IUNE

L

\'5

Vee

IR

LN

QR-

1U'F

~

Vo

8

~V'

MIC+
QR+

7

+et
1IlO,F

-o~
1O,F

0----2!.

100

lOOk TlOOPF

GAR

8

U-

TEA1081

DTMF

lnF

GAS,

10 TO 140mA

2

MUTE
R7
68k

+
;;;

R.

R4 ::bC4

MIC-

TEA1II6O
13

5

GAllo

PD
VEE

10

REG

AGC

16

STAB

17

9

SLPE

lC8
UpF

r!-

18

Ov,

T

+C3

R8

4.7,F

R5
Uk

RS
20

NOTES:
Voltage amplificatIOn IS defined as Avo = 20 log IVoN,1
For measunng the amplification from MtC+ and MIC -. the MUTE mput should be LOW or open, for measunng the DTMF Input, MUTE should be HIGH
Inputs not under test should be open

Figure 6. Test Circuit for Defining Voltage Amplification of MIC+, MIC- and DTMF Inputs

August 1, 1988

6-109

•

Signetics Linear Products

Product. Specification

Versatile Telephone Transmission Circuits
with Dialer Interface

TEA1060/61

R1
620

IS
11

Vee

IR

LN

QR-

z..
MIC+

1Ol

GAR

OR +

1---+--+--<> OR-

MIC+

GAS,
MIC-

13

GAS 2

OTMF

MUTE

PD

I.
12

18
V"

August 1, 1988

REG

AGe

STAB

6-115

SLPE

II

Signetics Linear Products

Product Specification

Low Voltage Transmission Ie with Dialer Interface

TEA1067

DC ELECTRICAL CHARACTERISTICS IUNE ~ 11 to 140mA; VEE ~ OV; f ~ 800Hz; TA ~ 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

1.75
2.25
3.55
3.65
4.9

1.6
2.0
2.8
3.8
3.90
5.6

Max

Supply: LN and Vee (Pins 1 and 15)

VLN
VLN
VLN
VLN
VLN
VLN
VLN

Voltage drop over circUit; between Pin 1
and Pin 10 ~ VLN; microphone inputs open
at IUNE
at IUNE ~ 4mA
at IUNE ~ 7mA
at IUNE = lImA
at IUNE = 15mA
at IUNE = 100mA
at IUNE = 140mA

.::l.VLN/.::l.T

Vanatlon with temperature at IUNE = 15mA

-3

VLN
VLN

Voltage drop over circuit with external resistor RVA
at IUNE = 15mA
RVA (Pin 1 to Pin 16) = 68kn
RVA (Pin 16 to Pin 18) = 39kn

3.1
4.2

Icc
Icc

Supply current Icc; current Into Pin 15
PO = LOW (Pin 12); Vcc = 2.8V
PO = HIGH (Pin 12); Vcc = 2.8V

Icc

Current available from Pin 15 to supply peripheral CirCUits at IUNE = 15mA
Vee;;' 2.2V; Mute = High

2.25
3.35
4.05
4.15
6.5
7.5

V
V
V
V
V
V
V

-1

1

mVfOC

3.4
4.5

3.7
4.8

V
V

1.0
55

1.35
82

rnA

1.4

1.8

51
25.5

64
32

JJ.A
rnA

Microphone inputs MIC+ and MIC- (Pins 7 and 8)

IZ,sl
Iz,sl

Input Impedance
differential (between Pins 7 and 8)
Single-ended (Pin 7 or WRT VEE)

CMRR

Common-mode rejection ratio

Avo

Voltage amplification (from PinS 7 - 8 to Pin 1) at
IUNE = 15mA; R7 = 68kn

.:lAvo/.::l.f

Vanation With frequency at f = 300 to 3400Hz

.:lAvo/.::l.T

Vanation With temperature at IUNE = 50mA; TA ~ -25 to + 75°C

77
38.5

82

kn
kn
dB

51

52

53

dB

-0.5

±0.2

+0.5

dB

TBO

dB

Dual-tone multi-frequency input DTMF (Pin 13)

Iz,sl

Input impedance

TBO

20.7

TBO

kn

Ava

Voltage amplification (from Pin 13 to Pin 1) at
IUNE = 15mA; R7 = 68kn

24.5

25.5

26.5

dB

.:lAvo/.::l.f

Variation With frequency
f = 300 to 3400Hz

-0.5

±0.2

+0.5

dB

.:lAvo/.::l.T

Variation With temperature at
IUNE = 50mA;TA=-25 to +75°C

±0.2

dB

Gain adjustment GAS1 and GAS2 (Pins 2 and 3)
.:lAva

Amplification variation with R7 (connected between PinS 2 and 3)
transmitting amplifier

-8

0

dB

Sending amplifier output LN (Pin 1)
VLN(RMS)
VLN(RMS)
VLN(RMS)
VLN(RMS)

Output voltage at IUNE = 15mA;
dTOT=2%
dTOT= 10%
at IUNE = 4mA; dTOT = 10%
at IUNE = 7mA; dTOT = 10%

VNO(RMS)

Noise output voltage, IUNE = 15mA; R7 = 68kn; 200n between Pins 7 and 8;
psophometrically weighted (P53 curve)

1.9

1.9
2.2
0.8
1.4

V
V
V
V

-72

dBmp

Receiving amplifier input IR (Pin 11)

IZ,sl

August I, 1988

Input impedance

17

6-116

21

25

kn

Signetics Linear Products

Product Specification

low Voltage Transmission Ie with Dialer Interface

DC ELECTRICAL CHARACTERISTICS (Continued)

TEA1067

IUNE = 11 to 140mA; VEE = OV; f = 800Hz; TA = 25°C, unless
otherwise specified.
LIMITS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Receiving amplifier outputs QR+ and QR- (Pins 5 and 4)

IZosl

Output impedance; Single-ended

AVD
AVD

Voltage amplification from Pin 11 to PinS 4 - 5 at IUNE = 15mA; R4 = 1/0kn;
Single-ended; RL = 300n (from Pin 11 to PinS 4 - 5)
differential; RL = 600n (from Pin 11 to Pins 4 - 5)

AVDI t.f

Vanatlon With frequency, f = 300 to 3400Hz

t.AVDI t.T

Variation With temperature
IUNE = 50mA; TA = -25 to + 75'C

VO(RMS)
VO(RMS)
VO(RMS)

Output voltage at Ice = 0; dTOT = 2%; sine wave dnve; R4= 100kn
Single-ended; RL = 150n
Single-ended; RL = 450n
differential; CL = 47nF (100n senes resistors);
f = 3400Hz

VO(RMS)
VO(RMS)

Output voltage at lee = 0; dTOT = 10%; Sine wave drive; R4= 100kn;
RL = 150n
IUNE=4mA
IUNE = 7mA

VNO(RMS)
VNO(RMS)

NOise output voltage IUNE = 15mA, R4 = 100kn; Pin 11 open psophometrically
weighted (P53 curve)
Single-ended; RL = 300n
differential; RL = 600n

n

4
30
36

31
37

32
38

dB
dB

-0.5

±0.3

+0.5

dB

±0.2

dB

0.25
045

0.29
0.55

V
V

0.65

0.80

V

15
130

mV
mV

50
100

p.V
p.V

Gain adjustment GAR (Pin 6)
t.AVD

Amplification vanatlon With R4 (connected between Pins 6 and 5),
receiving amplifier

-11

+8

dB

1.5

Vee
0.3

V
V

15

p.A

-17

dB

Vee
0.3

V
V

5

10

p.A

-5.5

-5.9

-6.3

dB

-1.0

-1.5

-2.0

dB

MUTE input (Pin 14)
V,H
V,L

Input voltage
HIGH
LOW

IMUTE

Input current

t.AVD

Reduction of voltage ampllflcallon from MIC+ (Pin 7) and MIC(Pin 8) to LN at MUTE = HIGH

AVD

8

Voltage amplification from DTMF (Pin 13) to OR+ (Pin 5) or
OR- (Pin 4) at MUTE = HIGH, Single-ended load RL = 300n

70
-21

-19

dB

Power-down input PO (Pin 12)
V,H
V,L

Input voltage
HIGH
LOW

IpD

Input current (Into Pin 12)

1.5

Automatic gain control input AGe (Pin 17)
AVD

AVD

Controlling the gain from Pin 11 to Pins 4 - 5 and the gain from Pins 7 - 8 to
Pin 1; R6 = 100kn (between Pins 17 and 10) amplification control range
Reduction of gain between
IUNE = 15mA
IUNE = 35mA

IUNE

Highest line current for maximum amplification

23

mA

IUNE

Lowest line current for minimum amplification

61

mA

3.2

V
V
V

Peripheral supply across Pins 15 and 10
Veep

August 1, 1988

Ip= OmA
Ip = 0.9mA
Ip = 1.4mA

3.0
2.5
2.2

6-117

2.4

•

Signetics Linear Products

Product Specification

Low Voltage Transmission Ie with Dialer Interface

FUNCTIONAL DESCRIPTION
Supply: Vee, LN, SLPE, REG
and STAB
The circuit and Its peripheral circuits usually
are supplied from the telephone line. The
circuit develops its own supply voltage at Voe
and regulates its voltage drop. The supply
voltage Voe may also be used to supply
external peripheral circuits, e.g., dialing and
control circUits.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and
VEE; the internal voltage regulator has to be
decoupled by a capacitor from REG to VEE.
An internal current stabilizer IS set by a
resistor of 3.6kO between STAB and VEE.
The DC current flowing Into the set is determined by the exchange supply voltage VEXCH,
the feeding bridge resistance REXCH, the DC
resistance of the subscnber line RLINE and
the DC voltage on the subscriber set (see
Figure 1).
If the line current ILiNE exceeds the current
loe + 0.5mA required by the circuit itself
(Icc"" 1mAl, plus the current loe required by
the peripheral circuits connected to Voe, then
the voltage regulator diverts the excess current via LN.
The voltage regulator adjusts the average
voltage on LN to:
VLN = VREF + ISLPE X R9
= VREF + (lLiNE -Ioe - 0.5 X 10- 3 -Ioe)
X R9.
VREF being an internally-generated temperature-compensated reference voltage of 3.6V
and R9 being an external resistor connected
between SLPE and VEE. The preferred value
of R9 is 200. Changing R9 will have influence
on microphone gain, DTMF gain, gain control
Characteristics, side tone, maximum output
swing on LN and on the DC characteristic
(especially in the low voltage part). Under
normal conditions ISLPE :> Icc + 0.5mA
+ loe. The static behavior of the circuit then
equals a 3.6V voltage regulator diode with an
internal resistance R9. In the audio frequency
range the dynamic impedance equals R1.
The internal reference voltage can be adjusted by means of an external resistor RVA. RVA
(1 -16) connected between pins LN and
REG will decrease the internal reference
voltage. RVA (16-18) connected between
REG and SLPE will increase the internal
reference voltage.
At line currents below 9mA the internal reference voltage is automatically adjusted to a
lower value (Typ. 1.6V at 1mAl. This means
that the operation of more telephone sets in
parallel is possible with DC line voltages
(excluding the polarity guard) down to an
August 1, 1988

absolute minimum voltage of 1.6V. At line
currents below 9mA the circuit has limited
sending and receiving levels.
The current loe available from Vcc for supplying peripheral circuits depends on external
components and on the line current. Figure 4
shows thiS current for Voe > 2.2V minimum. If
MUTE is LOW, the available current is further
reduced when the receiving amplifier is driven. To increase the supply possibilities, the
supply IC TEAl 080 can be connected in
parallel with R1 (Figure 9c). An alternative IS
to set the DC line voltage to a higher value by
means of an external resistor RVA (16-18)
connected between REG and SLPE.

Microphone Inputs MIC + and
MIC - and Gain Pins: GAS1 and
GAS2
The TEAl 067 has symmetrical microphone
inputs. Its input impedance is 64kO
(2 x 32kO) and ItS voltage ampllflcallOn IS
typo 52dB. Either dynamiC, magnetic, piezoelectric microphones or an electret microphone With built-In FET source-follower can
be used.
The arrangements with the microphone types
mentioned are shown in Figure 3.
The amplification of the microphone amplifier
can be adjusted between 44dB to 52dB to
suit the sensitivity of the transducer used. The
amplification is proportional to external resistor R7 connected between GAS1 and GAS2.
An amplification more than 52dB IS possible
(up to BOdS); however, in that case, the
spread of the DC voltage (V LN) will increase
and the minimum voltage at 11 mA
(VLN = 3.55V) cannot be guaranteed. An external capacitor CS of 100pF between GAS1
and SLPE is required to ensure stability. A
larger value may be chosen to obtain a firstorder low-pass filter.
The cut-off frequency corresponds with the
time constant R7 X CS.

Mute Input: MUTE
A HIGH level at MUTE enables the DTMF
input and inhibits the microphone inputs and
the receiving amplifier input; a LOW level or
an open circuit does the reverse. Switching
the mute input will cause negligible clicks at
the telephone outputs and on the line. In case
the line current drops below 6mA (parallel
operation of more sets) the circuit is always in
speech condition independent of the DC level
applied to the MUTE input.

Dual-Tone Multi-Frequency Input
DTMF
When the DTMF input is enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTMF to LN is typo 25.5dB
and varies with R7 in the same way as the
amplification of the microphone amplifier. The

6-118

TEA1067

signaling tones can be heard in the earpiece
at a low level (confidence tone).

Receiving Amplifier: IR, QR + ,
QR-and GAR
The receIVing amplifier has one input IR and
two complementary outputs, a non-inverting
output OR + and an inverting output OR - •
These outputs may be used for single-ended
or for differential drive, depending on the
sensitivity and type of earpiece used (see
Figure 4). Amplification from IR to OR + is
typo 31 dB. This Will be sufficient for lowimpedance magnetic or dynamiC earpieces;
these are suited for single-ended drIVe. By
uSing both outputs (differential drive) the
amplification is increased by SdB and differential drive becomes possible. This feature
can be used In case the earpiece impedance
exceeds 4500 (high-Impedance dynamic,
magnetic or piezoelectric earpieces).
The output voltage of the receiving amplifier
is specified for continuous-wave drive. The
maximum output voltage will be higher under
speech conditions, where the ratio of peak
and RMS value IS higher.
The amplification of the receiving amplifier
can be adjusted between 20 and 39dB with
single-ended drive and between 2S and 45dB
in case of differential drive to SUit the sensitivity of the transducer used. The amplification is
proportional to external resistor R4 connected from GAR to OR + .
Two external capacitors C4 = 100pF and
C7 = lOX C4 = 1nF are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order low-pass filter. The
"cut-off" frequency corresponds with the
time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor RS from
AGC to VEE. This automatic gain control
varies the amplification of the microphone
amplifier and the receiving amplifier in accordance with the DC line current. The control
range is SdB. This corresponds with a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable with a DC resistance of
17S0/km and an average attenuation of
1.2dB/km.
Resistor R6 should be chosen in accordance
with the exchange supply voltage and its
feeding bridge resistance (see Figure 5 and
Table 1). Different values of RS give the same
ratio of line currents for begin and end of the
control range. If automatic line loss compensation is not required AGC may be left open.
The amplifiers then all give their maximum
amplification as specified.

Product Specification

Signetics Linear Products

Low Voltage Transmission Ie with Dialer Interface

Power-Down Input PD

Side-Tone Suppression

During pulse dialing or register recall (timed
loop break) the telephone line is interrupted;
as a consequence, it provides no supply for
the transmission circUit and the peripherals
connected to Vce. These gaps have to be
bridged by the charge in the smoothing capacitor Cl. The requirements on this capacitor are relaxed by applYing a HIGH level to
the PD input during the time of the loop break,
which reduces the supply current from typically 1mA to typically 55/lA.

Suppression of the transmitted signal In the
earpiece is obtained by the anti-side-tone
network consisting of Rl ZUNE, R2, R3, RB,
R9 and ZBAl (see Figure B). Maximum compensation is obtained when the following
conditions are fulfilled:
a) R9 X R2 = Rl(R3 + [RB//ZBAl])
b) [ZBAl/(ZBAl + AB)]

A HIGH level at PD further disconnects the
capacitor at REG, with the effect that the
voltage stabilizer will have no sWitch-on delay
after line interruptions. This results in no
contribution of the IC to the current waveform
during pulse dialing or register recall. When
this facility is not required, PD may be left
open.

RLiNE

= [ZUNE/

To obtain optimum side-tone-suppression,
condition b) has to be fulfilled resulting in:
ZBAl = (RB/Rl)ZUNE = k,ZUNE
Where k IS a scale factor; k = (RB/Rl).
Scale factor k (value of RB) must be chosen
to meet the following criteria:

R1

'UNE

'SLPE +O.5mA

IN

TEA1067

I~

i\

SLPE

VEE

18

10

I~

i\

1
C1

\
\
\

PERIPHERAL
CIRCUITS

\i\

i

I
I
_.J

'SLPE

R5

The anti-side-tone network as used In the
standard application (Figure B) attenuates the
signal from the line with 32dB. The attenuation is nearly flat over the audio-frequency
range. Instead of the above described speCial
bridge, the conventional Wheatstone bridge
configuration can be used as an alternative
anti-side-tone circuit. Both bridges can be
used with either a resistive set impedance or
with a complex set impedance.

I

Vee

AC

STAB

In practice ZUNE varies strongly with the line
length and cable type; consequently, an average value has to be chosen for ZBAl. The
suppression further depends on the accuracy
with which ZBAl/k equals the average line
impedance.

cc

lo.smA

REG

• I ZBAl//RB I <{ R3
• IZBAl + RB I <{ R9

r

DC

V EXCH

• compatibility with a standard capacitor
from the E6 or E12 range for ZBAl

--,
Icc
15

RexCH

(ZUNE + AI)]

If fixed values are chosen for Rl, R2, R3 and
R9, then condition a) will always be fulfilled
provided that I RB//Z BAl I <( R3.

TEA1067

R9

\\

2
Vcc(V)
NOTES:
a)=18mA
b) = 1 35mA
'LINE = 15mA at VLN = 3 9V

R1 = 6200 and A9 = 20,0;

Figure 1. Supply Arrangement

Curve (a) IS valid when the recelvmg amplifier IS not
dnven or when MUTE = HIGH.
Curve (b) IS valid when MUTE = LOW and the recelvIn9 amplifier IS dnven, VO(RMS) = 150mV, RL "" 150n
asymmetrical The supply pOSSibilities can be mcreased Simpy by settmg the voltage drop over the
CirCUit VLN to a higher value by means of resistor AVA
(16-18)

Figure 2. Typical Current lec Available
from Vee for Peripheral Circuitry with
Vce> =2.2V

August 1, 19BB

6-119

II

Signetics Uneor Products

Product Specification

Low Voltage Transmission Ie with Dialer Interface

....-

TEA1067

~
~

--~. MlC+

....

-...:..t MIC-

I - . -......

NOTE:
The resIstor marked (1) may be connected to lower the
terminating Impedance In case of sensrtlVe microphone
types a resIstor attenuatar can be used to prevent overloadIng of the mICrOphone Inputs

a. Magnetic or Dynamic
Microphone

b. Electret Microphone

c. Piezoelectric Microphone

Figure 3. Alternative Microphone Arrangements

:~06
..

'u

6
QR+0
QR-

QR+[J
QR-

10

4

LD07070S

lD07081S

NOTE:
The resistor marked (1) may be

connected to prevent dlstortton
(induCtIve load)

a. Dynamic Telephone With
Less Than 4500 Impedance

QR+O.·
QR-

(1)

b. Dynamic Telephone With
More Than 4500 Impedance

lD0708DS

NOTE:
The I"8SIstor marked (2) IS reqund to
Increase the phase margm (capacrttve
load)

c. Magnetic Telephone With
More Than 4500 Impedance

d. Piezoelectric Telephone

Figure 4. Alternative Receiver Arrangements

R8=oo

,\.'\
\ \ '\
\ 1,\ '\.

Iii -2

}
-4 I-----

7a7~\

Mat\k2
\

-6
20

40

\

80

R8=2OQ

80

100

120

140

160

IUNE(mA)

Figure 5. Variation of Amplification with Line Current With R6 a8 a Parameter

August 1. 1988

6-120

Signetics linear Products

Product Specification

Low Voltage Transmission Ie with Dialer Interface

TEA1067

Table 1. Values of Resistor R6 for Optimum Line Loss
Compensation, for Various Usual Values of Exchange
Supply Voltage VEXCH and Exchange Feeding Bridge
Resistance REXCH.
REXCH (n)

400

600

800

1000

R6 (kn)

VEXCH
(V)

36

100

78.7

X

X

48

140

110

93.1

82

60

x

X

120

102

NOTE:
R9 =20n

R1
620

L

11S

~

Vee

IR

LN

QR-

+
;: 1OO.F

~
Vo

8

iv,

MIC+
QR+

7

S

RL
600
R4
+ f100pF
4
lOOk

MICGAR

TEA1067

6

II

H

13
DTMF

+C1

lnF

IQO.F
L......o'~

GAS,

R7
68k

+

=;: 1O.F

10 TO 140mA

2

MUTE

o----E.

PD
VEE
10

REG

AGC

16

17

STAB

9

GAS,
SLPE

l:PF

~

18

Ov,

T
+ C3

R6

4.7.F

RS
3.6k

R9
20

NOTE:
Voltage amplification IS defmed as Avo = 20109 IVoNl1 For measunng the amplification from MIC+ and MIC-, the MUTE mput should be LOW or open, for measuring the DTMF Input,
MUTE should be HIGH Inputs not under test should be open

Figure 6. Test Circuit for Defining Voltage Amplification of MIC+, MIC- and DTMF Inputs

August 1, 1988

6-121

•

Signetics Linear Products

Product Specification

TEA1067

low Voltage Transmission Ie with Dialer Interface

Rl
620

tLiNE

15

11

LN

Vee

IR

100,lolF
QR-

z..
MIC+

10f./F

Vo

600
R'
lOOk

MICGAR

TEA1067
13
+

t

QR+

C7
lnF

DTMF

C1
100 ...F

1OT014OmA

"

GAS,
MUTE
R7

12

PD
V ••
10

AGC

REG

STAB

17

16

+
C3

4.7J.4F

NOTE:
Voltage amplification IS defined as Avo

<=

20109

R6

C6
lOOpF

GAS,
SLPE
18

R5
3.6k

R9
20

1VoN.1

Figure 7. Test Circuit for Defining Voltage Amplification of the Receiving Amplifier

August 1. 1988

6-122

Signetics Linear Products

Product Specification

low Voltage Transmission Ie with Dialer Interface

TEA1067

...
R1

R10
13

R2
C5
130k 100nF

1

LN

11 IR
A3

3.92.

R11

4 QR-

,.
OA+

C4

lOOpF
6

FROM DIAL
AND

TEA1067

CONTROL CIRCUITS

GAR

8 MIC+

MICSLPE

GAS,

GAS,

18

AB

390

z....

AEG
18

co

100pF

A7

AGC

srAB

17

A8

v••

,.

A5

3.8.

.
20

NOTE:

The bridge to the left, the zener diode and R10 limit the current and the voltage mto the CirCUIt dUring hne tranSients Pulse dialing or register recall reqUire a different protection
arrangement By means of reSistor (At6-fa) the DC Ime voltage can be set to a higher value,

Figure 8. Typical Application of the TEA1067, Shown Here with a Piezoelectric Earpiece and DTMF Dialing

August 1, 1988

6-123

•

Product Specification

Signetics Linear Products

Low Voltage Transmission Ie with Dialer Interface

TEA1067

V DD

OTMF 1..------1 OTMF
TEA1067

MUTE 1..------1 M
PO

TELEPHONE
LINE

PCD3310

FL

I

____________ --1I
NOTE:
The dashed lines show an optlonal flash (register recall by timed loop break)

a. DTMF-Pulse Set with CMOS-Bilingual Dialing Clrcuil PCD3310

DTMF

TEA1067

MUTE r - - - - . . . . . : j M

PCD3320
FAMILY

PDr--~-.....:jDP
VEE

TELEPHONE

o

LINE

b. Pulse Dial Set with One of the PCD3320 Family of CMOS Interrupted Current-Loop Dialing Circuits

Voo

DTMF

TEA1067

MUTE

PD
V"

TELEPHONE
UNE

M

PCD3343

DPfFL

V..

1'<:
DTMF
PCD3312

NOTE:
Supply IS provided by the TEA 1080 supply CirCUit

C.

Dual-Standard (Pulse and DTMF) Feature Phone with the PCD3343 CMOS Telephone Controller
and the PCD3312 CMOS DTMF with 12C Bus
Figure 9. Typical Applications of the TEA 1067 (Simplified)

August 1, 1988

6-124

Signetics

AN1942
Application of the Low Voltage
Versatile Transmission Circuit
Application Note

Linear Products

INTRODUCTION
The TEAl 067 is a speech/transmission CIrcuit for analog telephone sets. It has been
developed to fulfill requirements for the North
American Telephony specifications. The circuit enables parallel operation with classical
telephone sets.
Additional features of the TEA 1067 are as
follows:
• High-ohmic microphone inputs and high
gain microphone amplifier which can be
adapted to every type of microphone.
• Improved receiving amplifier (high gain;
low noise).
• Lower DC voltage in the normal
operating range (IUNE > 11 mAl. Meets
USA DC requirement 6V at 20mA
(RS470) with a normal diode bridge
having l.4V voltage drop.
The circuit permits fully electronic telephone
sets to be designed for virtually any kind of
speech transducer and set-impedance. Although the IC has been designed primarily for
the increasingly-used common-line Interface
systems (With internal electronic switching
between dialing and speech condition), It is
also suitable for systems with separated
speech and dialing parts (with a two-wire
connection between the dialing part in the
base and the speech part in the handset). It
can be used with either complex or real setimpedances in either the special antl-sldetone bridge or the Wheatstone bridge configuration. All the interface functions between
microphone and earphone transducers, the
telephone line, and the dialing circuits are
incorporated on-chip.
A supply connection with hmited current (because of the low voltage drop across the
circuit) for peripherals IS prOVided. The supply
possibilities can be extended considerably by
means of a special supply IC TEAl 080, or
more simply by setting the line voltage to a
higher value by means of an external resistor.
Some alternatives to increase the supply
possibilities are given. Also, a straight-forward
design procedure IS given to be able to adjust
all necessary parameters in the most convenient order (Appendix 1).

December 1988

DESCRIPTION OF THE CIRCUIT
Block Diagram

SLPE

The block diagram of the TEAl 067 IS shown
In Figure 2. The Internal functions are as
follows:
• Voltage regulator with low voltage drop and
adjustable static resistance. The voltage
drop can be adjusted externally by approximately plus or minus 0.6V.

AGC
REG

Vee
MUTE
DTMF
PD

• Low DC operating voltage; down to an
absolute mimmum of typlcall.6V excluding
the polarity guard.
• Supply connection for driving peripheral
circuits. The capabilities of the supply depend on the DC voltage setting of the
voltage regulator, on external components,
and on the available line current.
• Microphone amplifier with adjustable gain,
and frequency roll-off with adjustable cutoff frequency.
• High-impedance symmetrical microphone
inputs suitable for dynamic, magnetic, and
piezoelectric microphones. Electret microphones with a source-follower or preamplifier can be connected In asymmetrical
mode.
• DTMF input
• Confidence tone in the earpiece during
DTMF dialing.
• Earpiece amplifier With two complementary
outputs suitable for magnetic, dynamic, or
piezoelectric earpieces. It has a large gain
setting range and adjustable cut-off frequency.
• Line loss compensation facihty dependent
on line current for microphone and earpiece amplifiers. The DTMF amplifier is not
affected by this facility. The control curve
has been optimized for 600n feeding
bridge and is adaptable for various exchange supply voltages.
• Mute input to inhibit the microphone and
earpiece amplifier dUring dialing and to
enable the DTMF Input and confidencetone.

6-125

Mle+

IR

VEE

TOP VIEW

:~

SYMBOL
LN
GAS1
GAS2

OROR+
GAR

7

MIC-

9
10
11
12

MIC+
STAB
VEE
IR
PO

13
14
15

OTMF
MUTE
Vee

16
17
18

REG
AGe
SLPE

a

DESCRIPTION

POSitIVe hne terminal
Gam adjustment, transmitting amplifier
Gam adjustment, transmitting amplifier
Inverting output, recelVlng amplifier
Non-Invertmg output; receIVing amplifier
Gain adjustment, receIVing amplifier
Inverting microphone mput
Non-Invertmg mIcrophone Input
Current stabilizer
NegatIVe hne termmal
Receiving amplifier Input
Power-down mput
Dual-tone multi-frequency mput
Mute Input
Positive supply decouplmg
Voltage regulator decouphng
Automatic gam control Input
Slope (DC resistance) adjustment

Figure 1. Pin Configuration
• Power-down input to minimize the internal
supply current of the IC during line interrupts, for example: during pulse dialing or
register recall (flash). The voltage regulator
capacitor is disconnected to prevent startup delays after line interruptions so as to
minimize the contribution of the IC to the
shape of the current pulses during pulse
dialing.
The anti-sidetone circuit is implemented outside the IC by means of discrete components
and allows maximum flexibility of circuit design.
The pinning is shown in Figure 1 together wijh
a list of the pin functions. These abbreviations
are used throughout the chapters that follow.
Figure 3 shows the basic application diagram.

•

Signetlcs linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

Vee

AN1942

LN

15

11

.------------t-I-o GAR
~--~L-~--~~-_+~~OQR+

IRo-1---------~----------------~

1---+-+-0 QR-

MIC+

GAS,
MIC-

13

GAS:.

DTMF

I.
MUTE

12

PO

18

10

VEE

REG

AGC

STAB

Figure 2. Block Diagram

December 1988

6-126

SLPE

Application Note

Signetlcs Linear Products

Application of the Low Voltage Versatile Transmission Circuit

AN1942

R1
120
C1

R2

100j.lF

130K

R10
13

15

Vee

LN

+-________~C5r_----~11~IR

+

100nF

r-----'M.._--....:..t OR-

BZX79·C12

OTMF

13
FROM

+-------~----~OR+

C4

TEA1067

100pF

MUTE

PO

RYA(16-18)

r--Jo..""II.,r--,

'---------------IMICSLPE

I

I

GAS1

18 I

2

_oJ

RI

0

GAS2 I REG

3

I

1.._

AGe

16

STAB

VEE

17

10

R7

390

RS

C6

ZSAl

R9
20n

3.IK

100pF

NOTE:
The Zener between Pin 1 and Pin 18 IS optional and can be used to obtain symmectncal cliPPing of the sending signal.

Supply Considerations
Supply and Set Impedance
The IC is supplied with current from the
telephone line; the general supply arrange·
ment is shown in Figure 4. The equivalent
impedance of the circuit is shown in Figure 5.
The artificial inductor LEa = Rp' Rg' Ca
With Rg = 20Q

= 4.7J.LF

Rp = 16.2kQ (internal resistor;
tolerance ± 20%)

This results in a typical LEa = 1.52H.
Ca not only influences the value of LEa. but
also determines start-up time of the DC
voltage regulator. The value of Ca has been
chosen to give optimum start up time of the
circuit. This means that the voltage regulator
starts up after the smoothing capacitor at Vcc
has been charged.

December 1988

DIAL
AND

CONTROL

r---r---:-;==....:.:..------~MIC+

Ca

14

Figure 4. Supply Arrangement

6-127

12

CIRCUITS

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

ur-----,------r-----,

LNo--~--~--....,

10 1-----+---+--1

01

0,

LEQ"'R.,.Rp.~

VREF

OEG

Vee

09
20

C1
1OO,F

V"o---+---+----'
Figure 5. Equivalent Impedance
A different value for LEQ can be obtained
either by changing C3 (taking Into account a
different start·up time) or, although not recommended, by changing the value of Rg. The
latter has Influence on several parameters;
this will be discussed later.
In the audio frequency range, the Impedance
of the whole circuit IS determined by R1, or,
more exactly, by the value of R, II Rp.
The network R, C, provides a smoothed voltage Vcc both for the IC Itself (tYPical
Icc = 1mA at Vcc = 2.8V) and also for the
peripheral circuits (Ip). TYPical Icc versus Vcc
is shown In Figure 6; normal operating condition and power down condition are shown.
1.5

C

s-

I-

Z

w

II:
II:

V

1.0

/

::>

()

...~
:i
z

0.5

.....- f.-"A
,/

.......- V

::>

III

V

,Icc......

i-""B

....-jcc x1O -

'"

50

15

100

Figure 7. DC Characteristics
With hne currents in excess of ITH' the voltage
drop across the Integrated CirCUit IS VLN,
where
VLN

=

VREF + (ISLPE'Rg)

In which VREF

= Internal

reference voltage
of 3.6V
ISLPE = IUNE -Icc -O.SmA -Ip
ITH = threshold current low
voltage part (typ. 9mA)

The internal reference voltage IS temperature-compensated, giving a low temperature
coefficient of the hne voltage VLN; typically
about -1 mV Ik at IUNE = 1SmA.
Normally ISLPE~lcc+ O.SmA + Ip, which
means that the equivalent cirCUit for DC
conditions, where IUNE exceeds the threshold
current ITH, equals that of a 3.6V regulator
diode In senes With a resistor Rg (see Figure
S).

W

l-

ii!;

o

AN1942

The typical DC voltage VLN is shown in Figure
7 as a function of line current. The slope of
the graph is determined by Rg.
Changing Rg - Note that Rg also shifts the
low-voltage threshold current ITH. Furthermore, Rg determines microphone gain and
DTMF gain, shifts the gain-control characteristic and, in case its value exceeds 30n, it
decreases the maximum output swing on LN
(especially at high line currents and high
ambient temperature). Also, the sidetone will
be affected because Rg is a branch of the
anti-sidetone bridge; the bridge must be rebalanced if its value IS changed. The preferred value of Rg IS 20n and this value is
used in the basic application circuit as described in this report. However, choosing
another value for Rg can sometimes be
necessary, e.g., to rebalance the anti-sidetone Circuit when a set impedance different
from 600n is chosen.
Increasing DC Slope
Increasing the slope of the DC characteristic
can be done by inserting a resistor between
Pin 1 (LN) and node [R" R2, R ,a] (Figure 3).
This resistor does not have influence on the
set Impedance. However, the maximum output sWing on the line is decreased slightly.
Another alternative IS simply increasing the
protection resistor R10 (Figure 3).
Adjusting the DC Voltage Drop
If necessary, the voltage drop across the
cirCUit (VLN) can be increased by means of an
external resistor (RVAI1S-1SI) connected between Pin 16 (REG) and Pin 18 (SLPE). In
fact, the external resistor RVA sets the internal reference voltage VREF = VLN.SLPE of the
voltage stabilizer. ThiS resistor causes a
slightly increased spread in the voltage drop
and a shghtly different temperature coefficient. With RVAllS-1S1 = 39kn, Figure 8

o
Vee (V)

6r-------,-------,------,-------,-------,
NOTES,

5 \

A Normal operating condition. PO =: Low
B Power down conditIOn, PO = High

4···~r42V

Figure 6. Internal Supply Current
Icc = f(VCC)

••• 3.1SV

~

Supply of the Integrated Circuit
The direct current which flows Into the set IS
determined by the exchange supply voltage
(VEXCH), the resistance of the feeding bridge
(RExCH), the DC resistance of the subscriber
line (RUNE) and the DC voltage across the
subscriber set Including the polanty guard.
If the line current exceeds the value given by
(Icc + O.SmA + Ip), then the voltage regulator
diverts the excess current through LN (see
Figure 4).

OL-~----~------~~~------~--~--~
o 39
100
200 INFINITE 200
100 68
RVA~6-18)(kQ)

RVA~_16)(kQ)

NOTE,
With hne currents between 11 and 140mA
DC Voltage VlN = VLN-SlPE + (I LIN!; 1 5mA)R9

Figure 8. Internal Reference Voltage VLN-SLPE vs Resistor RVA
December 1988

6-128

Signetics Unear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

shows that VREF = 4.2V, resulting in
VLN = 4.5V ± 0.3V at IUNE = 15mA.
A decrease In the voltage drop VLN can be
obtained by means of an external resistor
RYAI1-16J connected between Pin 1 (LN) and
Pin 16 (REG). Figure 8 shows that with
RYAI1-16J = 68k!!, VREF = 3.15V, a voltage
drop VLN = 3.4V ± 0.3V at IUNE = 15mA IS
obtained.
Of course, choosing a modified voltage drop
across the circUit will have Influence on several parameters: maximum output swing of
sending and receiving amplifiers and supply
current available for peripherals. Decreasing
the voltage drop by means of RYAll _ 16J will
lower the set impedance slightly.

Parallel Operation
At line currents below the low-voltage threshold current ITH (typically 9mA), the Internal
reference voltage is automatically adjusted to
a lower value. At 1rnA a typical voltage drop
of 1.6V Is obtained. ThiS means that the
operation of the circuit With more telephone
sets in parallel is possible with line voltages
down to an absolute minimum of typically

vcc >2.9V

swing in the low-voltage range. Furthermore,
the supply point for penpherals is degraded.
2.5

~

1.5

Jl

...... ... t\A)MUTE
··········t\
... ·""'tiV

l'l.

r-rii K\. .Al0.s5mA. uv
H

••• ·B)O.8mA,2.5V

;
;

1.5

2.0

'{~,I
I I
••
O.1mA,2.9~
3.0

2.5

3.5

4.0

VCC{V)
NOTES:
-Speech Condition VLN oro 1 4VRMS (d < 2%)
VOR+ - 150mV across 1500
Single ended load (d < 2%)
-Mute Condition VL.N = 1VRMS

Figure 9. Typical Current lee
Available From Vcc at ILlN~ = 15mA;
VLN
3.9V; TA 25 C

=

=

1.6V. Of course, the sending and receiving
amplifiers have reduced gain and output

v

y V

.LE

- vcc >2.2V

,

o
o

'~cc>2.9V

OL-~-~~-~~-~~

211

40

eo

eo

100

120

140

o

211

eo eo

40

100

120

140

'UNE(mA)

'UNE(mA)

0P16140S

Figure 10. Typical Current lee and Corresponding Vee vs Line Current in
Speech Condition. Signal Conditions as In Figure 9

~rE

V

./

v

."

-Ycc >2.2Y

•

o
o

~cc>2.9Y

oL-~~

211

40

eo eo
'UNE(mA)

100

120

140

o

211

__

40

~-L

__L-~~

eo eo

100

120 140

'UNE(mA)

Figure 11. Typical Current IcC; and Corresponding Vee YS Line Current in Mute
Condition; Signal Conditions as in Figure 9
December 1988

AN1942

6-129

Supply to Peripheral Circuits
The voltage available at Pin 15 (Veel can be
used to supply peripheral Circuits such as
pulse dialer, DTMF dialer, or a microcomputer
With Its own penpherals; an electret microphone With a source·follower or preamplifier
can also be powered from Vcc.
However, the current Icc and the voltage Vee
which are available from the circuit In the
baSIC appllcallOn (Figure 3) are limited and
are dependent on the values of external
components of the IC and on the actually
available line current. Figure 9 shows the
typical available current Icc versus Vcc at a
line current of 15mA. The typical available
current and the corresponding voltage Vee as
a function of line current are shown in Figure
10 for the speech condlllOn and In Figure 11
for the mute condition; parameters are the
same as in Figure 9.
It is shown clearly that the lowest power is
available at minimum line current. At higher
values of line current, the typical values of
available Icc and Vee are both Increased.
The limit on Icc is then imposed by the
requirement to maintain at least the minimum
permitted voltage between Pin 15 (Veel and
Pin 18 (SLPE) (minimum instantaneous voltage: Vee - VSLPE ;;'1.5V). In case this condition is not met, the maximum pOSSible sendIng level on LN will be limited.
If the assumption IS made that 15mA is the
minimum line current under normal operating
conditions, some figures can be given. The
available current Icc is determined by the
minimum supply voltage required for the peripheral circuits. For most CMOS circuits the
minimum supply voltage will be 2.5V. The
typical available current Icc = 1.25mA at
Vee = 2.5V; worst· case Icc > 0.9mA. In
speech condition, the available current depends strongly on the received signal level
because of the class-B receiving amplifier
output stage; With an extremely high and
continuous drive of the receiving amplifier,
the available current Will be typically 0.8mA.
In practice, however, the receiving amplifier
will not be driven continuously and the avail·
able supply current will be higher under normal speech condillOns. ThiS means that the
power available from the supply pOint in the
standard application IS suffiCient for low-power circuits such as pulse dialers and preamplifiers for electret microphones. Most CMOS
DTMF dialers can be powered under typical
conditions; however, under worst-case condi·
lIOns of both TEAl 067 and tone dialer, the
available power may not be sufficient.
In cases where a battery IS used for memory
retaining, an enable diode will become necessary between Vee and the power pin of the

•

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

.-------<~

.------~+

+

---«

AlB

AlB 0 - -......

BIAO------+----~

BIA 0 - -.....

-----+-------'

NOTES:
a 4·Dlode Solution typ 0 5V Less Drop
b 6·Dlode Solution typ 1V Less Drop

Figure 12. Schottky Diode Polarity Guard With Protection Giving Less Voltage
Drop Than a Normal 1.4V Polarity Guard

2.5

1

,

peripheral circuit to prevent discharge of the
battery. Taking Into account a voltage drop
for a Schottky enable diode (BAT85'
VF < 0.32V at 25°C and 1mAl. the minimum
value of Vce we need IS about 2.9V This
results in a tYPical available current of
0.55mA In mute condition (worst case
Ip = 0.2mA). This IS not suffiCient to power a
mlcrocontroller and a DTMF dialer (e.g ..
PCD3315 and PCD3312) simultaneously.
Several possibilities to Improve the supply of
the TEAl 067 are given In the follOWing paragraph. In AN1943 a separate overview IS
given to solve the supply problem of
TEA1067 and stili meet the RS470 requirements at the same time.

II I

....... .....
....... .....

,\:.~~. . LLL1v

B)SPEEC~\
1.5

I I I I

1\ ...

••• B)1.7mA,2.5V

\.~ • A)1.45mA,2.9V

Jl

I I I

~Jlr

o.s

~J

1.5

2.5

3

3.5

VCC(V)
NOTE:
Signal conditions as In Figure 9

Figure 13. Typical Current Icc
Available From Vcc at ILiNE = 15mA
With Increased Line Voltage by
Means of RYA[16.18) = 39kn

Extending the Supply Possibilities
Several methods eXist to extend the supply
possibilities. All of them have advantages and
also disadvantages. These methods are discussed below.
Increasing the Line Voltage - In cases
where this IS allowed, the supply problems
can be overcome simply by setting the volt-

AN1942

age drop across the circuit to a higher value.
Of course, the line voltage IS also increased
then. If a higher line voltage is not allowed
(e.g., reqUirement RS470), this can be cor·
rected In sets with DTMF dialing only (without
flash) by uSing a polarity guard with Schottky
diodes resuiling in a lower voltage drop
across the polarity guard. This is shown in
Figure 12. More Information can be found in
AN1943.
Increasing the voltage drop across the circUit
can be obtained by means of an external
resistor RVA[16-1B]. With RVA[16-1S] = 39kn
the typical available Icc and Vee are shown In
Figure 13 with VLN = 4.45V and
IUNE = 15mA. Taking Into account the spread
on the voltage drop VLN, It can be calculated
that the minimum available power is
Icc = 1.1 mA at Vee = 2.9V and 1.75mA at
Vee = 2.5V in mute condition.
An alternative way to meet the requirements
of RS470 IS to increase the line voltage Into
the conditionally acceptable region at the
moments when this IS allowed. The voltage is
sWitched back into the acceptable region In
those cases where this IS reqUIred; e.g.,
dUring pulse-dialing and during the hook-on to
hook-off transition. This is described extensively In AN 1943.
Compromise Between Set Impedance and
Supply - The TEAl 067 gives a very good
balance return loss (BRL) with respect to a
600n reference impedance. In cases where
the margin with respect to the reqUirements
for BRL IS rather high, It IS possible to reduce
the AC set Impedance to such a value that
the BRL reqUirement sllll IS fulfilled safely. In
this way a considerable Increase of the supply possibilities IS obtained.
Figure 14 shows the typical available supply
current with Vee = 2.9V and Vee = 2.5V as a
function of Rl In mute conditIOn with
IUNE = 15mA and VLN = 3.9V. Furthermore,
Figure 15 shows the measured BRL-figures at
30

I.

~z

\Vcc~2..5V

~cc"2.9Y 1\ \
I\..

"" '"

'UNE=15mA
V LN =3.9V

I'-...

~ r--...

o

o

100

200

300

20

)

m

........

I--

-- -

r--- r-- -

500

600

700

800

:s.
...

.,

o
o

Va;;l;~

)

rr:

10

~

~

/
200

400

600

800

R,(Q)

Figure 14. Typical Supply Current Icc as a Function of the
Supply Resistor R1 (in Mute Condition)
December 1988

6-130

Figure 15. Balance Return Loss as a
Function of R 1

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

300Hz, at 500Hz, and at 3400Hz as a function
of R, .

small correction factor (normally around ldB)
for the total DTMF gaon is introduced.

Note that lowenng of R, will have .influence
also on sending gain (microphone and DTMF),
on the maximum possible sending signal on the
line at low line currents, and on the balancing of
the anti-sldetone bndge. The sending gain normally can be corrected easily. The following
section on Anti-Sldetone CircUits shows how
the anti-sidetone bridge can be rebalanced by
decreasing Rg or R2•

Inductor in Parallel With R, - If the above
descnbed methods cannot be used, a supply
arrangement as shown In Figure 17 IS POSSIble. An inductor In parallel with R, extends
the supply possibilities. The value of this
Inductor must be more than 2.5H In order not
to influence the BRL-figures much. In practice
a BRL;;;' 20dB at f = 500Hz can be realized.
The maximum senes resistance of the onductor depends on the maximum current Ip and
the minimum required voltage Vee. For example, with Vee;;;' 3.5V and Ip;;;' 3mA, the maximum series resistance of the Inductor is
RL = 180n. However, to aVOid the need for
an excessively large and expensive Inductor,
an electronic solution is more favourable for
currents Ip in excess of about 3mA. Also, for
currents less than 3mA an electronic solution
can be used in case a discrete Inductor IS not
desirable.

RC Smoothing Filter Between LN and
SLPE - For relatively small supply currents,
an RC filter between Pin 1 (LN) and Pin 18
(SLPE) can be used to power penpherals. An
advantage of this method IS that the Internally-generated reference voltage is used, which
is rather constant (temperature compensated) and has a relatively low spread. Furthermore, no influence IS to be expected on setimpedance (BRL), sendong gaon, and on the
gain control characteristics.
This configuration IS shown in Figure 16. With
RL1 = 300n, CRL = 220l'F and IRL = 2mA,
the supply voltage across the peripheral load
RL2 measures about 3V ± 0.25V.
A disadvantage is that a higher line current is
necessary for the same output swing of the
transmit output stage on the line, because of
the dissipation of the AC signal In RL"
Furthermore, a problem is that the TEAl 067
and the peripherals do not have a common
reference. The reference used for the penpherals is SLPE; the TEAl 067 reference IS VEE.
This means that level shifters are necessary
between the logical inputs Pin 14 (MUTE) and
Pin 12 (PO) of the TEA1067, and the logical
outputs of the peripheral IC's. Furthermore, a

Ie

Electronic Inductor - The TEA 1080 special
supply cirCUit comprising an artificial inductor
(about 10H) can be used in combination with
the TEAl 067 to extend the supply possibilities to very high values, depending on the
available line current and line voltage. This
combination is very suitable for listen-In and
handsfree applications where a relatively
large power IS needed.
In this report two possible combinations of
TEA 1060 and TEA 1080 are described: the
TEA 1080 IS either connected between LN
and the common reference VEE or between
LN and a different reference SLPE Both
methods have their own ments.
An electronic inductor can also be realized by
means of off-the-shelf components (e.g., op

Icc

'RL

'UNE

-~l

Rp
Rll
VRl

CRl
R7
C3

SLPE

VE

Rl2

I
I
I
I

____ J

R1

Ze'NE

Vee

C1

v exCH

R9
VEE

Figure 16. Equivalent Circuit Diagram of the Transmit/DC Regulator Stage of the
TEA1067 With Supply Part Connected Between LN
December 1988

6-131

AN1942

amp TCA520 + 3 resistors + 2 capacitors + 2
transistors + 1 diode); this IS shown In Figure
18.
Parallel Operation With a Classical Set In case a classical telephone set IS connected In parallel with the TEA1060/61/66T/68
on a loop with low line current, the line
voltage Will drop below the zener voltage of
the voltage stabilizer of the transmiSSion
CirCUit For example, with a 200n classical set
on a 20mA loop the line voltage Will drop to
about 3.8V; this means that the voltage inside
the polanty guard will be about 26V. The
TEA 1067, however, automatically decreases
ItS zener voltage In case the current coming
from the line drops below the threshold
current ITH (typ. 9mA) This means that the
transmit output stage will operate down to
very low voltages. For example, with the
200n classical set connected In parallel to a
TEA 1067 with 20mA available line current,
the line voltage will drop to 3.2V leaVing 4mA
of line current for the TEA 1067 at a voltage Of
2V at the power pin of the TEAl 067 onslde
the polanty guard. We assumed that the
current used for the penpherals can be neglected at such a low voltage (Vee has a
value around 1.6V); this means that on sets
containing a microcontroller and battery, the
controller Will run on the battery; In baSIC tone
dial sets the DTMF dialer Will be in an
unspecified condition and normally this IS a
low-power stand-by condition as long as no
key IS pressed. In case a key IS pressed,
normally distorted dial tones are generated.
In sets where penpherals are connected to
Vee that also consume current under lowvoltage conditions, this Will cause worse performance of the TEAl 067 during parallel
operation under minimum conditions, unless
the penpherals are sWitched Into a low-power
condition on case the line voltage drops below
a predetermined value.

Microphone Amplifier
The TEA 1067 has symmetrical high Impedance microphone Inputs. The onput Impedance IS typically 64kn (2 x 32kn) with tolerances of ± 20%. With this high Input Impedance It is possible to determine the matching
of several microphone types very accurately
by means of external components. The Circuit
IS sUitable for dynamiC, magnetic, or piezoelectric microphones with symmetrical drive;
electret microphones with bUilt-In source follower or preamplifier can be used In asymmetrical mode.
To obtain optimum nOise performance, the
microphone Inputs must be loaded. The
equivalent nOise-voltage (psophometncally
weighted; P53-curve) at the microphone Input
is typically O.65I'V(RMS)P with 8.2kn across
the microphone Inputs. With 200n across the

•

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

R1

R,

= R1 II 16.2kn,

----,

ro

= dynamiC resistance of the Internal circuit·

I
I
I

R5

= 3.65kn, fixed external resistor determln'

6

TEA1067

TELEPHONE
LINE

C1

SfAB

C3

SLPE

R5

PERIPHERAL
CIRCUITS

y

VEE

I
I

R9

I

~----~~~-+--~----~---~
Figure 17. Increased Supply Capability by Means
of an Inductor in Parallel With R1

R81

68k
C62
33pF

R62

68k
R63

15

R1
620

LN
TEA1067

Figure 18. Circuit Diagram of an Electronic Inductor Realized
With Off·the·Shelf Components
inputs, the equivalent nOise at the Input
measures typically 0.45IN(RMS)P'
The Internal microphone preamplifier accepts
signals up to 17mVRMS for a 2% level of total
harmonic distortion (dTOT = 2%) because of
the internal soft limiting. This means that the
minimum possible gain of the microphone
amplifier measured between the inputs and
the line IS 44dB With clipping of the line signal
being determined fully by the transmit output
stage. In case a lower gain is necessary, the
input signal must be attenuated before enter·
ing the preamplifier; otherwise, the input
stage will be overloaded and cause extra
distortion (soft clipping) of the line signal. The
arrangements With several microphone types
are shown in Figure 19.
December 1988

AN1942

In case asymmetrical drive of the microphone
inputs is used, care should be taken that both
inputs MIC+ and MIC- see equal imped·
ances to the common, otherwise, residual line
signals present on the supply point (V cd Will
cause Inaccuracy In gain, and sometimes
(with a large DC·blocking capacitor connect·
ed to MIC-) even low·frequency hlcklng (mo·
torboatlng) may occur.
The gain of the microphone amplifier IS given
by the follOWing equation (see Figure 3):

the dynamiC impedance of
the Circuit RL = load resistance at LN
dUring the measurement; normally
600~1

ry (3.47kn)
Ing the current In an Internal current
stabilizer

If, for a practical CirCUit such as shown In
Figure 3, we Insert In the above equation the
follOWing realistiC values: R7 = 68.1 kn,
R5 = 3 65kn, Rg = 20n, R1 = 620n, and
RL = 600n, then: 2010gA m = 52 ± 1dB.
For various microphone senSitiVities, the gain
can be set between 44dB and 52dB by
means of R7 ; thiS takes values between 25kn
and 68.1 kn . The microphone gain IS shown
as a funcllon of R7 in Figure 20. An ampllflca·
tlon of more than 52dB is possible (up to a
maximum of 60dB); however, In that case the
minimum specified DC voltage of VLN at
11 mA (VLN;;' 3.55V) cannot be guaranteed
any more. Also, the specified DC voltages at
7mA and 4mA will show more spread. ThiS is
caused by the Internal offset voltage of the
microphone Input stage, which causes an
offset onto the low·voltage threshold current
of the DC characteristic. The effect of thiS
offset depends on the microphone gain that
has been set by means of R7. With a micro·
phone gain of 52dB (R7 = 68.1 kn) and a
standard deViation (sigma) of the offset volt·
age of the Input stage of ± 0 5mV, it can be
calculated that the threshold current ITH IS
between about 7 and 11 mA (3'slgma). The
DC voltage at 11 mA IS specified to guarantee
that the DC voltage In the normal operating
range (IUNE > 11 mAl IS not Influenced by this
spread with a microphone gain of 52dB.
It Will be clear that any different choice of Rg
(static resistance of the DC characteristic) Will
directly Influence the gain of the transmitting
channel. The value of Rg also has Influence
on the DC characteristic (slope, ITH), the gain
control characteristic, and on the maximum
output sWing on the output pin LN. Also, the
balanCing of the antl·sidetone CirCUit Will be
affected, necessitating rebalancing of the
bridge.
The value used In the baSIC appllcalion d,a·
gram IS 20n If thiS value IS to be changed,
the consequences should be considered
carefully and the deSign procedure as given In
Appendix 1 must be followed
In case the line current IS suffiCient, clipping
of the output signal at Pin 1 (LN) normally
happens when the Internal output transistor
saturates
(VLN - VSLPE

where,

6·132

= 09V)

Signetics linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

r-"Mr----"-i MIC +

,..---t---4 MIC+

~N\"---,

'----<>--"""'i MIC-

MIC-

NOTE:
The resister marked (1) may be connected to lower
the termmatlng Impedance

a. Magnetic or Dynamic Microphone

b. Electret Microphone

c. Piezoelectric Microphone

Figure 19. Alternative Microphone Arrangements
gives f3dB = 23kHz with R7
G6 = 100pF.

54 r--,.--r-..,.-r-"""''"T"TTrTTTTTm 27.5
52 •••..

TJLER1NcUd~

.....~

/

III

25.5

t---1r-+-+--H-t-ti>ftiT!iH~ttt123.5
48 f---\---t-++I--V1-H*I!.'~'
21.5

.1

..

36

10

20

30

10 .----...,----,---,---...,----,---,----,3.5

13.5

V

38

below the Internal reference voltage and the
CirCUit automatically adlusts this voltage to a
lower value. Of course, thiS will have Influence on the performance of the microphone
amplifier.

iii

46 t--t---t--t-I/-I7'r-l7H;m:39 19.5 ~
44 t--t---t--l'+-YH>f+t+ttl+tH 17.5 I;
42 --15.5
40

68.1 kQ and

Parallel Operation
In case of parallel operation of sets, the
operating voltage of the TEA 1067 can drop

50

;

=

11.5
9.5

40 50 60 : 80 100

R,(kQ)

68.1kQ

I .-'...-::::-.-.---"

2.5

~ .... '" '-'d=2%

..

a

v.

~
..." ..........
....

'z"

>~

........ -"

-

Figure 20. Microphone Gain and DTMF
Gain as Function of R7

oL---~~--~----~----~----~----~~--~

2

Figure 21. Maximum Output Swing Transmit Output Stage as a
Function of DC Voltage VLN (lLINE = 15mA)

At low line currents. the top part of the output
sine wave IS clipped because the output
stage runs out of current.

In Figure 21 the maximum output sWing of the
transmit output stage IS shown as a function
of the DG line voltage VLN at IUNE = 15mA.

Stability and Frequency Roll-off.
The 100pF external capacitor G6 connected
between GAS 1 and SLPE IS necessary for
ensuring the stability of the transmitting amplifier. Larger values can be applied, and
these Will then operate as a first-order lowpass filter, for which the cut-off frequency IS
determined by the time constant R7 G6 . ThiS
December 1988

a

;

- 0.5

This means that the sme wave clips at the
bottom. The top of the sine wave can only be
clipped by the zener diode at Pin 1 (LN) or by
lack of collector current In the output transIstor (low line current).

In case of sufficient line current. symmetncal
clipping at the line output LN can be obtained
by uSing a 6.8V zener diode between LN (Pm
1) and SLPE (Pin 18) of the TEA 1067 (Figure
3).

.
i!!

2

1.5

2.5r---~----_r----,-----r---~----_r----,_--_,

d=10%

.l

v·· ..·· ..······ ..-

/._.........

d=2%

/.-.-.....

1.5

;

...

0······

./.,

./-?-.....
0.5

0

10

0

15

20

IUNE(mA)

Figure 22. Maximum Output Voltage of the Transmitting Output Stage Vs
IUNE in Low Line Current Range

6-133

•

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

In Figure 22 the maximum output voltage at
Pin 1 (LN) is shown with a 300n AC load (the
resistor determining the set impedance
Rl = SOOn is in parallel with the 300n) as a
function of line current that is actually flowing
into the TEAl OS7. This represents one telephone set with a SOOn AC Impedance being
connected in parallel with the TEA 1067
(SOOn load representing the telephone line
being already present). Transmit gain is 52dB
in case of a normal soon load; however, with
a SOOn set in parallel, gain decreases with
about 3.5dB. The maximum output swing is
not determined by the DC voltage at Pin I,
but by the available current in the output
stage of the TEA 1067.

of Figure 3 with a 100llF, 25V capacitor. The
following typical values with respect to 25°C
were found:

+5

I

-0.5dB at -25°C
+ 0.2dB at + 70°C

V-

Receiving Amplifier

I

The input of the receiving amplifier is Pin 11
(IR). Input impedance is approximately 20kn.
The amplifier has two complementary Class B
outputs - the non-inverting output QR+ at
Pin 5, and the inverting output QR- at Pin 4.
The outputs can be used either for singleended drive or for symmetrical drive, dependIng on the impedance, senSitivity, and type of
earpiece used.

/
-20
1

In Figure 23, the transmit gain versus the DC
voltage at Pin 1 (LN) is shown. Gain decrease
starts at VLN = 2.2V. At VLN = 2V, the decrease is about 2-3dB and about 12dB at
VLN = I.SV.

signals up to 170mVRMS for dTOT = 2% with
internal soft limiting of the input stage.

The results given are valid for a typical
sample in the basic application circuit of
Figure 3. Changing component values will
influence the results.

The coupling network between the DTMF
generator PCD3311/12 and the transmission
circuit is very simple. For further information
on this application, contact factory.

DTMF Amplifier

Temperature Dependency
The DTMF amplifier is internally temperature
compensated. However, because of the
asymmetrical input structure (single-ended
drive), some influence can be expected from
the residual AC line voltage being present on
the supply pin Vee. The low-pass filter R1Cl
provides a smoothed supply voltage Vee. The
small residual line voltage being present on
Vee depends on the performance of the
components of the low-pass, especially the
electrolytic capacitor Cl. This means that the
temperature dependency of the capacitor C1
has some influence on the DTMF gain via an
internal feedback mechanism; therefore, an
electrolytic capacitor with low temperature
coefficient should be chosen.

A dual-tone multi-frequency dialing signal can
be applied to the IC through the DTMF input
at Pin 13. Input impedance is typically about
20kn. The voltage gain measured between
the DTM F input and the transmitter output at
LN is 2S.5dB less than that of the microphone
amplifier. Thus:
2010gADTMF = 20 10gAm = 2S.5dB
The DTMF gain depends on the values of R l ,
Rs, R7, R9, and RL in the same way as the
microphone gain (see Figure 20). Thus, the
choice of gain to suit one particular microphone capsule will also predetermine the
DTMF gain. The dialing tones must, therefore,
be adjusted to the appropriate level before
they are applied; the DTMF input accepts

Figure 23. Typical Transmit Gain vs DC
Voltage VLN in Low Voltage Range

It can drive either dynamic, magnetic, or
piezoelectric earpieces as shown in Figure
24. Earpleces with an impedance up to 450n
must be driven in Single-ended mode (Iowimpedance dynamiC or magnetic capsules).
This is shown in Figure 24a. For impedances
above 450n, with a high-impedance dynamic,
magnetic, or piezoelectric capsule, differential
drive is possible, as shown in Figure 24b, c, d.
The additional series resistor (1) shown in
Figure 24c in case of a magnetic capsule can
be used to prevent distortion of the output
signal when the output stage is deficient in
available current (causing a dIldt in an inductive load). To preserve stability with a piezoelectric earpiece, the series resistor (2) is
required as shown In Figure 24d, as this type
of transducer represents a capacitive load.

The temperature dependency of DTMF gain
was measured in the basic application cirCUit

OR- ..4'-_ _ _--'

OR - .-:4:.-_ _ _....J

c.

b.

Figure 24. Alternative Earphone Arrangements

December 1988

Capacitive loading of the receiving output
stage is permitted up to a maximum of 100nF
between QR+ and QR-. However, the decrease of phase margin (could give lead to
instabilities) must be restored by means of
the series resistor R(2) (for example, with
CL = 100nF, R(2) = 50n ).
With an asymmetric load, the gain AT A of the
receiving amplifier, measured between the
input IR and the output QR+, is given by (see
Figure 3):

OR + j-'5::""'...JV(2)V'v-_.,

OR+ ..,5:'-_11--_--,

a.

AN1942

6-134

OR -

.-:4:.-_ _ _....J

d.

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

AcT

Where, 2 T
ro

2010gATA

41

the receiving amplifier (tYPically
4n).

If we Insert the values R, = 100kn,
R5 = 3.65kn, and 2T = 450n, the followmg
results:

= 31dB

± ldB.

This results with the values for R" R5, and 2T
which were used above In:
2010gATS

= 37dB

± ldB.

The gain of the receiving amplifier can be
adjusted by means of R, between 20dB and
39dB with single-ended dnve, and between
26dB and 45dB In case of differential drive
This takes values of R, between 28kn and
250kn . The gains AT A and ATS together with
the confidence tone as a function of R, are
shown In Figure 25.
The maximum output sWing of the recelvmg
output stage(s) versus DC line voltage V LN IS
shown In Figure 26 at ILiNE = 15mA.
The signal received on the line IS attenuated
by the antl-sldetone network before It enters
the Input IR of the receiving amplifier. In the
basIc application CirCUit (Figure 3) thiS attenuation IS about 32dB. Frequency response
between the line and the mput IR IS almost
flat In the audiO frequency range when uSing
the special TEAl 060 family bndge configuration.
The signal at the mput IR of the amplifier IS
Internally limited by symmetncal soft limiting
to 17mVRMS for dTOT = 2% and to 53mVRMS
for dTOT = 10%.
The equivalent noise at the Input IR of the
receivmg amplifier (psophometncally weighted; P53-curve) IS typically 1.25jN(RMS)P' With
the antl-sldetone CirCUit connected to the
input, the nOise generated at the Ime pm LN
will add via the antl-sldetone CirCUit to the
equivalent Input nOise of the receiving amplifier. The total nOise generated at the earpiece
output depends on microphone gain that has
been set and on the actual sldetone suppression; furthermore, extra CirCUitry connected to
pin LN (for example, an artifiCial Inductor to
extend supply possibilities) can give a nOise
contnbutlon.
December 1988

r----y

37
35
33

iO

~

"

31
29
'ZT

25
21

1

~I-

---+-r-----i

/

--I-

--

j-

~L_ TOLERANCE ±1dB-

iO
-15 :g,

-111

±
+
;'

r-----~-I

/

~3

/

I

19

20

-13

I'

./

f----,(,

10

-11

_17

f----.k

f-----2~
'I'

-9

3

ZT=450Q

39

23

With both outputs OR + and OR- being used
In symmetncal mode, the gain ATS is Increased by 6dB and IS given by:

DIFFERENTIAL
DRIVE

Ars

= earpiece Impedance
= output Impedance of

200

30

500

300

700

c

-17 ~

ffi

-19

a

ail

-21

-23 ~

-25

.p

-27

-29
-31

1000

Figure 25. Gain 01 Receiving Amplifiers ATA and ATS and Confidence Tone ACT
Against the Value of R4
--------------------~
Stability and Frequency Roll-off
Stability IS ensured by the use of two discrete
capacitors C4 and C7 In Figure 3. Capacitor
C, IS connected between OR+ and GAR, and
capacitor C7 IS connected between GAR and
VEE The value of C7 IS recommended to be
ten times greater than that of C" and the
values are generally C, = 100pF and
C7 = 1nF A larger value of C4 may be chosen
so as to obtain a flrst·order low· pass frequen·
cy charactenstlc, the cut·off frequency being
determined by the tlme·constant R4C,. In thiS
case, the ratio of 10'1 for C7 .C, must be
preserved. With C4 = 100pF and with
R, = 100kn, the cut-off frequency
fSdS = 16kHz
Parallel Operation
Similar to the microphone amplifier, the POSSIbilities of the receiving amplifier Will be decreased under low voltage conditions occur·
mg dunng parallel operation of sets. Figure 27
shows the maximum output sWing of the
receiving amplifier (dTOT = 10%) versus the
line voltage VLN with different loads In the low
voltage part The maximum output sWing
naturally decreases with the DC voltage at
LN. At VLN = 2V, tYPically an output swmg of
15mVRMS with a 150n load can be obtained
At about 1.6V, the receiving amplifier IS totally
cut off.
Figure 28 shows the receive gam as a func·
tlon of the DC line voltage VLN. Gam de·
crease starts at about VLN = 3V; at VLN = 2V,
the gam has been decreased by about 13dB
The results are valid for a tYPical sample m
the baSIC application CIrCUit of Figure 3.
Changing components Will have Influence on
the results.

Confidence Tone
Dunng DTMF dialing, the dialing tones can be
heard at a low level In the earpiece The level

6-135

1.5

LOAD AT RECEIVER

R=+=0~:"~~~NTI~L

I

l-

47nF (RSERIES = 1OOQ17

1
dror=10%
I UNE =15mA

0.5

Iz

Y

~

t

V

/

1/

DIFF~

450Q

SINGLE·ENDED
150Q-

l-'

./

I:::: ~

~

V
j..-

o
S

Figure 26. Maximum Output Swing
Receiving Amplifier vs
DC Voltage VLN

600

LOAD AT RECEIVER
OUTPUT

500

'"j

400

oS

300

(SINGLE·ENDED):

I

I

dTQT=10%

f=1kHz
Rt.=100kQ

+

f'j

>

200

100

1---+---i7<<'--'h<--+--+--\

Figure 27. Maximum Output Swing
Receiving Amplifier vs
VLN in Low Voltage Range
of the tones at the receiving output depends
on the gam that has been set for the receiving

•

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

~

f

Iii'

-5

I

-10

g

I

GAIN CON11IOL
VEXCH....E+-_-+_-_-_CAB-+_LE_L_EN_QTH+-_-I

',,-

,\

c"z

f-I

-16

-20

i

. . . . . ',

\48yo.;

I~
- I
-3 1-__+_--r-\~0rrT-\~~~+_--r_~---r~-3
\
\ I ~
~~

(-2

o

i

MV

-1

+5

AN1942

,

'\

-

2

-41----+---+---~~~~~.-~--_+--_+--_4

_51--__+-__-r___
i~7k--'~~.-'-'~~~T~k"~~+~I·--~----t_-_i-

1\" '-:..~~
-80~----IO~--~20----~2D----~~~~~~-----~~~·N~--~~~--~~O

I
1

~

~

~

VLNM
OP16280S

Figure 28. Typical Receive Gain vs
VLN In Low Voltage Range

Figure 29. Gain Control Characteristics; 600n Feeding Bridge

amplifier. and on the tone level applied to the
DTMF input.
The gain Acr between the DTMF input and
the receiving output is given by:

"-

-1

MV \ " V ,

..

Iii'

:g, -2

,,~

0

20logAcr - 2010gAT - 50dS
in which AT is a general term for telephone
gain and this can be replaced by either ATA
(single-ended drive) or ATS (symmetrical
drive). This is shown in Figure 24.

Line Current-Dependent Gain
Control
The gain figures of the microphone amplifier
and the receiving amplifier which was derived
in the preceding chapters are applicable only
when the AGC is inoperative: that is, with Pin
17 (AGC) not connected (open circuit).
When the resistor R6 is connected between
AGC and VEE, line current-dependent gain
control of both the microphone amplifier and
the receiving amplHier becomes operative;
the DTMF amplifier is not affected.
Selow a specific value of line current,
IUNE-START, the gain is equal to the values
calculated with the formulas given before. If
the current IUNE-START is exceeded, the gain
of both of the controlled amplifiers decreases
as a function of Increasing DC line current.
Gain control stops when another value of line
current (ILINE-STOP) is exceeded. The gain
control range of both amplifiers is typically
SdS. This corresponds with a line length of
5km of O.Smm diameter copper twisted-pair
cable with a DC resistance of 17Sn/km and
an average AC attenuation of 1.2dS/km. The
slope of the gain control characteristic has
been chosen to give an optimum tracking
between the line attenuation and the required
amplifier gain (typical error <: 0.8dS) for a
system with a 2 x 300n feeding bridge. In
case lines with different parameters are used,
December 1988

II:

Ii

8z
~

~

-3

,~VEXCHANQE

'"

4

:'\..

'~ " " ~

-4

rk'~ , 14Of'~

-5
-8

GAIN CONTROL

- - CABLE LENGTH

o

10

2D

lie

.--

I

I
i

1\ '1'-...... ."'~ ....-

Figure 30. Gain Control Characteristics; 400n Feeding Bridge
a small additional tracking error will be introduced.

the typical tracking error that can be expected
is <: 1.2dS.

Correction for Exchange Supply Voltage
The value of resistor R6 must be chosen in
accordance with the supply voltage in the
exchange. In Figure 29 the control curves are
shown for VEXCH = 3SV and 48V with a feeding bridge resistance of 2 x 300n.

Figure 30 shows the control curves for a
400n feeding bridge with exchange supply
voltages of 3SV and 48V. Figure 31 shows
the characteristics for an 800n bridge of 48V
and SOV. In Figure 32, the results for a 1kn
bridge are shown at the same voltages.

Also, the calculated relationship between line
length and line current is shown in Figure 29.
These ideal curves have been calculated with
the assumption that an increased voltage
drop across the Circuit has been set
(VLN = 4.4SV at 15mA; RVAI16 -lal = 39kn)
and assuming a polarity guard with l.4V
voltage drop. Other parameters will give
slightly different results, giving slightly different optimum values for Rs.

The optimum values of As for the various
values of exchange supply voltage and exchange feeding bridge resistance, with a 1.4V
diode bridge, Ag = 20n, and increased line
voltage VLN ~ 4.45V at 15mA (AVAIIS-16]
- 39kn) are given in Table 1.

Correction for Feeding Bridge
Resistance
If the feeding bridge in the exchange has a
resistance other than BOOn, As must be
adjusted. This will introduce a minor increase
in tracking error because the slope of the gain
control curve has been optimized for a soon
feeding bridge. With a 1000n feeding bridge,

6-136

In case a value for Rs is used different from
20n, the value for As must be adapted.

------ ------

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

AN1942

Table 1
REXCH
-1

..

i

Ii"
S. -2

i3

3

~

~
~
3

-3

z -4

-51----+-+
~

10

20

30

40

50

10

400

800

1000

Rs (kO) with Rg = 200

VEXCH(V)
36

100

78.7

48

140

110

60
NOTES:
1. VLN = 4.45V

0

600

at IUNE = 15mA;

RVAI16-1S] =

93.1

82

120

102

39k

2. In case a value for Rg IS used different from 20n the value for R6 must be adapted

70

IUNE(mA)

Figure 31. Gain Control Characteristics;
8000 Feeding Bridge

IN

R1

R2

MICROPHONE AMPLIFIER
AND
OUTPUT STAGE
Ii"

!

~

-3

~

-4

8
co

I

-2
3

2

I.

SlPE

i

R8

R9

a. Special TEA1060 Family Antl-Sidetone Bridge

Figure 32. Gain Control Characteristics;
10000 Feeding Bridge

IN

R1

MICROPHONEAMPUFIER
AND
OUTPUT STAGE

Antl-5ldetone Circuit
The anti·sidetone circuit takes care that the
microphone signals available on the line out·
put LN are suppressed sufficiently before
they enter the receiving amplifier input IAThis is necessary because otherwise these
signals would be reproduced as sidetone with
an unacceptable high level in the telephone
transducer. The anti-sidetone circuit takes the
signal which IS available at Pin 18 (SLPE) and
uses it to compensate the microphone signal
at the input IR (Pin 11) of the receiving
amplifier.
The design of the anti-sidetone circuit initially
depends on whether the special TEA 1060family bridge or the more conventional
Wheatstone bridge is to be used. Both structures are shown in Figure 33. For the
TEA1060-family bndge In Figure 33a, the
bndge components are Rl II ZlINE, R2, Ra,
Rs, Rg, and ZBAl. For the Wheatstone bridge
in Figure 33b, the comparable bridge components are Rl II ZLlNE, Rs, Rg, RA, and ZBAl.
Both types can be used either with a resistive
set impedance or with a complex set impedDecember 1988

ZeAL

SLPE

VEE
R8

+
R9

R.

b. Wheatstone Bridge
Figure 33. Antl-Sidetone Circuits
ance. A brief comparison of both bndge
structures and the two types of set Impedance IS given in the next paragraphs.

If fixed values are chosen for R t , R2, Ra, and
Rg, condition 'a' Will always be fulfilled prOVided that IRs II ZBAll Rg to

avoid influence on
microphone gain

In practice ZLiNE varies strongly with the line
length and line type. Consequently, a value
for ZBAl has to be chosen that corresponds
to an average line length giving satisfactory
sidetone suppression with short and long
lines. The suppression further depends on
the accuracy with which ZBAl equals this
average line impedance.
In the basic application of Figure 3, ZBAl has
been optimized for a line length of 5km
0.5mm diameter copper twisted pair with an
average attenuation of 1.2dB/km, a DC resistance of 1760/km and a capacitance of
38nF/km. The corresponding impedance can
be approximated by:
Scale factor k has been chosen according to
the cntena menboned before, resulting in
k = 0.636. So ZBAl and Ra can be calculated
resulting in the following practical values:
Rll = 1300, R12 = 8200, C12 = 220nF, and
Ra = 3900.
This results in a roughly equal sidetone level
(acoustically measured) at Okm line and with
a 10km line with the line current-dependent
gain control acllvated. In case no AGC is
1265

210

Figure 35. Equivalent Line Impedance
for Optimum Sldetone Suppression

December 1988

used, the sidetone has to be optimized for a
shorter line length in order to obtain equal
(acoustical) sidetone levels at Okm and at
10km line length. Of course, overall sidetone
suppression is worse in that case compared
to the situation where AGC IS aClivated. In
practice, normally a compromise is chosen
between loudness of the set and sidetone
level; this means that sending and receiving
gain will be reduced somewhat.
The attenuation of the received line signal
between LN and IR can be derived from:
VIR =
VlN

Disadvantages include the need for a relative·
Iy large capacitor (about 200nF) in ZBAl, and
the need for an extra resistor on top of those
required by the Wheatstone bridge. Calculation of new values is also sometimes considered to be more difficult, particularly in case
of complex set impedances.
In some casas, calculating the optimum condition Is not very useful because a compromise must be chosen to meet sidetone requirements In several conditions. In those
cases a more practical and probably faster
method is using an empirical method: doing
acoustical measurements and hustling components ZBAl and Rs until the requirements
are met.
Wheatstone Bridge
The conditions in the Wheatstone bridge
(equivalent circun in Figure 38) for optimum
sidetone suppression are given by:

RTII R3
R2 + (RTII R3)

where RT is the input impedance of the
receiving amplifier (typically 20kO). This attenuation is about 32dB wnh the basic application as shown in Figure 3. Frequency
dependence of the input attenuation is negligible in the audio frequency range. However,
a frequency roll-off can be obtained by means
of a capaCitor connected between IR and VEE
to prevent high frequency components from
entering the receiving amplifier.
Complex Set Impedance
Complex set impedances can be realized by
using a complex network instead of Rl, and
normally the bridge can be rebalanced by
readjusting the values of Ra and ZBAl, and
enher R2 or Rg. Changing Rg also has consequences on other parameters and the range
of possible values is limited. Therefore, the
design procedure as given in Appendix 1
should be considered. Changing R2 has influence on the attenuation of the received signal
between LN and IR; this necessitates a
readjustment of the receiving gain. Note that
changing Rl also has influence on the capabilities of the supply for peripherals.
The TEA 1oeo family bridge configuration has
the advantage of an almost flat transfer
function in the audio frequency range batween LN and the receiving amplifier input IR,

6-138

provided that Rs/Rg

>> 1.

Also, for this bridge type a value for ZBAl has
to be chosen that corresponds with an aver·
age line length.
The attenuation of the received line signal
between LN and IR is given by:
VIR =
VlN

Rsil RTII RA
ZBAl + (Rail RTII RAl

Where RT - input impedance of the receiving
amplifier at IR, typically 20kn
A practical circuit could have the following
values: Rs - 8200. Rl - 6200, and ZBAl
optimized for the line impedance as shown in
Figure 35. With RA = infinite and a 6000 load
at the line, the attenuation varies typically
from about 24dB to 27.5dB over the normal
audio frequency range; the lower attenuation
occurs at the upper frequencies. RA is usad
to adjust the bridge attenuation; its value
does not have influence on the balancing of
the bridge.
Complex Set Impedance
If complex set impedances are used with the
Wheatstone bridge, it can be rebalanced by
adapting the values of ZBAl. However, the
frequency dependence of the transfer function between LN and IR will increase.

Application Note

Signetlcs Linear Products

Application of the low Voltage Versatile Transmission Circuit

Capacitor types SUitable for high frequencies
must be used, such as ceramic types. In
Figure A 1 they have been added to the baSIC
application CIrCUIt. Cs and Cg at the microphone Inputs, C10 at the receiving Input IR,
C 13 at the supply pOint Vcc, and C ll at the
transmitter output LN. All of the capacitors
are connected to the common VEE.

IR

SLPE

Figure 36. Equivalent Circuit of Wheatstone Bridge Anti-Sidestone Circuit
The Wheatstone bndge offers the advantages of needing one less resistor compared
to the special TEA 1OSO-famlly bridge. and
only a small capacitor (about 10nF) IS needed
In ZBAL Furthermore, the values are calculated rather easily with either resistive set Impedances or complex set Impedances
Disadvantages are the dependence of the
attenuation of the bridge on the value chosen
for ZSAL, and also the frequency-dependence
of that attenuation ThiS necessitates a readjustment of the receIve gain

Mute Input
ElectrOnic sWitching between dialing and
speech can be obtained by controlling the
MUTE Input at Pin 14. If a high level (> 1.5V,
<;; 15"A) IS applied to the MUTE Input, then
both the microphone and receiving amplifier
Inputs are inhibited, and the DTMF Input IS
Simultaneously enabled The converse situation, with DTMF Inhibited and the microphone
and earpiece amplifier both enabled, IS obtained by either applying a low-level Input
( <;; O.3V) to MUTE, or by leaVing the MUTE
Input open. The Internal SWitching takes place
with negligible clicking at the earpiece outputs
and on the line
If the supply voltage at Vee drops below
Vce = 2V (In the case of no external load at
Vee. VLN < 2 5V and IUNE < SmA), the mute
function becomes inoperative and the CirCUit
Will be In a condition where Signals applied to
either the microphone Inputs or the DTMF
Input Will be sent onto the line. However,
under these low voltage conditions, only occUffing dUring parallel operation of sets under
worst case conditions, dialing normally Will
not take place.
'

Power-Down Input
The power-down Input PO at Pin 12 IS available for use In pulse dialing and In register
recall applications, In which the telephone
line IS Interrupted DUring these Interrupts, the
telephone set IS without continuous power
and the transmission IC and the peripheral
CirCUitS must be supplied by the charge avallDecember 1988

AN1942

able In the smoothing capacitor C 1 connected
to Vec (Pin 15) In Figure 3. The discharge
time of this capacitor Will be longer In case
the power-down function IS used; thiS results
In less ripple on Vce.
When a high-level Input (> 1.5V, <;; 1o"A) IS
applied to the PO pin, the Internal supply
current IS reduced from about 1mA to typically 55"A at Vce = 2.8V Furthermore, the voltage regulator capacitor C3 at REG (Pin 1S) IS
Internally disconnected to prevent It from
being discharged dUring line interrupts ThiS
means that after each line Interrupt, the
voltage regulator IS able to start without delay
at the same DC line voltage as before the
Interrupt ThiS minimizes the contribution of
the IC to the shape of the current pulses
dUring pulse dialing. Of course, In case of a
highly Induclive character of the exchange
feeding bridge, the Inductors mainly determine current waveform. Under these conditions, the voltage regulator may show some
SWitch-on delay because of the active character of the transmission CIrCUit (the exchange
Inductors determine the current resulting In
voltage overshoot at the line connection (LN)
of the IC).
In case the voltage drop across the CIrCUIt IS
Increased by means of RVAI16-1S), the power-down function Will be affected. ThiS results
In a different shape of the current pulses.

Immunity to RF Signals
In a strong radiO frequency electromagnetic
field, It IS pOSSible for common-mode amplitude modulated RF Signals to be present on
the alb lines. These common-mode Signals
can sometimes become differential-mode signals as a result of asymmetrical parasitic
capacitances to ground; thiS may occur, for
example, through the hand of the subSCriber
holding the handset. Steps have to be taken
to aVOid the pOSSibility of these Signals being
detected and the low-frequency modulation
appearing as unwanted Signal at the earpiece
or on the line. Small discrete capacitors are
necessary to suppress the unwanted RF
signals before they can enter the CIrCUIt.

6-139

Furthermore, the layout of the printed CirCUit
board may have Influence on RF Immunity.
The copper ground area should be kept as
large as pOSSible. Ground loops must be
aVOided and traces must be kept as short as
pOSSible. RFI-capacltors must be mounted as
close as pOSSible to the IC pins.
In practice, It has been shown that two
Inductors (chokes With a value between
200"H and 1mH) In senes With the alb lines
improve RF Immunity conSiderably. It has
been shown also In practice that a so-called
"guard nng" (closed copper nng) around the
CIrCUIt gives a conSiderable Improvement
against radiated magnetic fields.
Because the TEA 1OS7 has a very high microphone Input Impedance, It IS pOSSible to use
low-pass flltenng In senes With both microphone Inputs, Without affecting gain accuracy.
The RC filter should be pOSitioned as close as
pOSSible to Pins 7 (MIC-) and 8 (MIC+). A
low-ohmiC termination across the microphone
inputs Will reduce pick-up of unwanted RF
Signals via the handset cord.

Polarity Guard and Transient
Suppression
There IS a pOSSibility that the transmission IC
IS destroyed by excesSive current surges on
the telephone lines If no proper measures are
taken. The type of protection differs for sets
With only DTMF dialing or sets With either
pulse-dialing or DTMF dialing With "flash"
(register recall by means of a timed line
Interrupt).
With DTMF dialing only, the bndge rectifier,
which normally acts as a polanty guard, can
also Incorporate two voltage reference diodes
(such as BZW14). Under normal operating
conditions, one of the two voltage reference
diodes conducts while the other IS nonconducting. If the voltage across the set
temporarily exceeds the reference voltage of
the previously mentioned non-conducting diode, It Will conduct and limit the voltage
across the set. The maximum permissible
voltage across the transmission CirCUit IS 12V
continuously and IS determined by the collector-emitter breakdown voltage of the IC process used Dunng SWitch-on and line Interrupts, the maximum permissible voltage IS
13.2V allOWing the use of a 12V voltage
reference diode In the polanty guard.

•

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

application of the TEA 1067 with an interrupter circuit.

5.oE+1

4.5E+1

"'- i'-.

3.5E+1

iii" 3.0E+1

.
il.

Hints for Printed Circuit Board
Layout

./'..

4.OE+1

:!!.

,/

2.5E+1
2.OE+1

./"

1.5E+1

"

V-

Care must be taken to avoid having the large
line current flowing into common ground
traces to which sensitive points are connected .

I'

For th,s reason, resistors Rg (connected between STAB and VEE) and R6 (connected
between AGC and VEE) must be situated on
the PCB close to Pin 10 (VEE)'

~

1.oE+1
0.5E+0

o.oE+O
1.oE+2

NOTE:Z_zo
BAL "'" - -

Z+Zo

AN1942

with Zo

1.oE+4

1.0E+3
FREQUENCY (Hz)

=

600n

Figure 37. Balance Return Loss (BRL) as a Function of Frequency

+J

z-

SOOQ

Also, the ground connection of the earpiece
should preferably be realized at a point where
no large line current is flowing.
The copper tracks connecting R7 and R4 to
the corresponding IC pins should be kept as
short as possible.
The ground connection of all RFI capacitors
should be made by means of the largest
possible copper planes. RFI capacitors must
be connected as close as possible to the pins
that have to be decoupled.
The ground plane on the circuit board must
be kept as large as possible.

PERFORMANCE
-Lr-~~--+--+--~~~--+--+--r-~~--+-~~~~+L

Some measurements have been done with
the basic application circuit, including RFI
capacitors as shown in Figure A 1. This gives
an indication of the performance of the
TEAl 067.

Balance Return Loss
The result of the balance return loss measurement (BRL) is shown in Figure 37. The
impedance of the circuit is shown in Figure
38.
Different values chosen for C3 and for Rg will
have influence on the impedance and the
BRL of the circuit. Remember that C3 and Rg
also determine some other parameters.

-J

Figure 38. Polar Plot of Impedance Between AlB Connections
Further protection is offered by the resIstor
RlO in series with the bridge rectIfier, whIch
limits the current that can be drawn by the IC.
The maximum allowed transient voltage on
the circuit, includIng the protectIon resistor
Rl0 being 13n and with Rg = 20n, is 28V
during 1ms with a repetition time of 5sec. ThIS
corresponds with a 50A surge onto the
BZW14 zener dIodes used in the polarity
guard.
For DTMF dialing wIth flash, or for pulse
dialing, a different protection arrangement is
necessary because, during line interruption,
the line current must be zero. This means that
the bridge rectifier must be able to withstand
December 1988

a relatIvely high voltage, on the order of
200V. A polarity guard using four diodes with
type number BAS 11 IS appropriate for this
purpose. Protection against line current
surges can then be obtained by means of a
suitable VDR connected between the alb
lines in front of the polarity guard. The speech
circuit is protected against overvoltages that
may occur, for example, during switching·in,
by means of a 12V regulator diode connected
between LN and VEE, or In case a current
limIter is used (e.g., combined with the interrupter), by a 6.8V voltage regulator diode
connected between LN and SLPE. The latter
method also provIdes symmetrical cliPPing of
the sending sIgnal. FIgure A2 shows an

6-140

Frequency ,Characteristics
Figure 39 shows the frequency characteristic
of the sending channel measured between
microphone Inputs and the transmitter output
LN with a 600n load. The mIcrophone gain is
set by means of R7 to 52dB (R7 = 68.1 kn).
The upper cut-off frequency is about 24kHz
(mainly determined by the time constant
R7C6)·
Note that if a complex set impedance has
been chosen, it will have influence on the
frequency characteristic.
Figure 40 shows the frequency characteristic
of the receiving channel measured between
LN and the QR + output loaded wijh 150n
(single-ended drive; 10llF DC-blocking capacitor). With R4 = 100kn, the transfer ratio

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

;

z

53

~r-~~~nn'--r-rTTrrrn

-65

52.8

t-t~mm=l_

'" -67

53

51~

52.6

~
a:

52.4

w

49

iI 52.2

:f~

52

~

51.8

~ 51.6

...

~ 51.4

o

:E

CD

47

Z

45

OJ

43

:s

:c

~

V

/

h..-l"''t-'IIt+ttH

51.2

37

::: -83

-0.5

m

-1

......

i" -1.5

J

~ -2

...~-2.5

~ -3

:I:

~-3.5

~

-4

/

/

/

jjj

hi -4.5
IX:

-5
-5.5

10"

1Q3
FREQUENCY (Hz)

Figure 40. Frequency Characteristic
of the Receiving Channel

-30

-31

iD

:s
z

~

-32

.......

,

-33

-34
10'
FREQUENCY (Hz)

Figure 41. Frequency Characteristic
of the Anti-Sidetone Circuit
Between LN and IR

December 1988

V

-85
40

Figure 39. Frequency Characteristic
of Microphone Amplifier

/'
V

/

w

6 -81

L200Q

/'
/'

!C( -79

39

,,

/'

-73

-75

10'
FREQUENCY (Hot)

[,

A

3-n

51

10"

iukQ

:: -71

!

~~~71F+4++Ht-~~~~+tH

r-- R~IC +, ~IC-

i'" -69
t:

r-1t1jj:\:~~

AN1942

42

44

FREOUENCY (Hz)

46

46
A., (dB)

50

52

54

Figure 42. Frequency Characteristic
of the Electrical Sidetone at
Okm Line Length

Figure 43. Psophometrically-Weighted
Noise on the Line LN vs
Microphone Gain

is -1 dS at 1kHz. The lower cut-off frequency
IS 120Hz and IS determined In thiS case by the
time constant RLC2 of the load resistor RL
and the DC-blocking capacitor C2 . The upper
cut-off frequency IS about 95kHz and IS
determined partly by R4C4 (15kHz) and partly
by the cut-off frequency of the antl-sldetone
CIrCUit (18kHz).

because both amplifiers (microphone and
receive) are affected by the gain control
function.

The frequency response of the antl-sldetone
circuit (LN to IR) IS given In Figure 41. The
cut-off frequency IS about 18kHz. ThiS is
mainly obtained by the 2.2nF capacitor connected between IR and VEE (necessary for
RF Immunity)
The transfer ratio as a function of frequency
measured from the microphone Inputs to a
150n asymmetrical load at the receive output
QR+ (10IlF DC blocking capacitor) IS shown
In Figure 42. ThiS represents the electrical
sldetone at Okm of telephone line (600n load
at LN) The measured sending Signal at LN IS
shown also The Signal at the receive output
With the same line Signal In receiving condition IS shown also In Figure 42.
The difference between wanted receive signal and prinCipally unwanted sldetone at the
receive output IS In fact the electncal sldetone
suppression. ThiS means that for thiS application the electncal sldetone suppression at
Okm of line length IS about 7.3dS at 1kHz.
The result depends strongly on the balanCing
of the antl-sldetone CirCUIt. In thiS case, the
balance Impedance ZSAL has been optimized
for 5km line length with 0.5mm diameter,
176n/km and 38nF/km
Electncal sldetone suppression IS not dependent on whether gain control IS used or not,

6-141

Noise
TYPical noise psophometrlcally (P53 curve)
measured on the line LN With a 600n load is
given as a functron of microphone gain In
Figure 43. The microphone Input is loaded
With a 200n resistor or 8.2kn.
Psophometrrcal nOise at the receive output
(Single-ended 300n load) as a function of
microphone gain is shown In Figure 44. Parameters are the receive gain and the resistor
across the microphone Inputs.
NOTE:

For mformatlon on discrete semiconductors used In
thiS apphcatlon note, contact Amperex ElectrOnic
Corp, Smithfield, RI, (401) 232-0500

I

I

'" -71 _RM1C+'jIC-

'" -73
>tr.
C

~ -75

t:

-

-17

30

~18.2kQ

.. -78

:s

+ -81

AyA -1dB

IX:

'" -83
~
~

V
>-- r-r200Q

-85

;. -87

AyA= -7dB

-88

40

1 J::
42

44

./
V ./'
V

..... t ..

--

46
46
A., (dB)

,

8.2kQ

~

...

... .-.,;

"
200Q

50

52

54

Figure 44. Psophometrically Weighted
Noise at the Receiver Output
vs Microphone Gain

•

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

AN1942

APPENDIX I

,
,

Component

.---_ _ _ _ _ _ _ Set impedance real or complex?
(Re)-balancing antl-sidetone bridge
(Rg: recommended value 20Q)
DC characteristic
DC slope
Maximum line voltage
type of polarity guard

[

4

,,
,,
,,
,
,
,,
,

sUPPIJ for

R10
RVA
Schottky diodes
Active bridge
Normal diodes

peripherals

I..._------Compromise BRL/ Supply
RC-smoothing filter between LN and SLPE
(level shifters for logical inputs)
..4 1 - - - - - - - - TEAl 080 necessary or (artificial) Inductor?

Gain control start/stop

R6

Microphone gain
Upper cut-off frequency microphone amplifier

R7
Attenuator at microphone inputs
C6

Lower cut-off frequency microphone amplifier

Capacitor(s) at microphone inputs

DTMF input level adjustment

Attenuator at DTMF input

Receive gain:

single-ended or symmetrical

Upper cut-off frequency receiving amplifier
Lower cut-off frequency receiving amplifier

Adjusting Parameters for the TEA 1060 Family

December 1988

6-142

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

AN1942

R1
620

RlO
13

15
LN

+-~e~______~'~'

Vee

IR

,...--------=-1 OR-

BZX79
6V8

13
OR+
R3

c.

3.9k

100pF

DTMF

MUTE

TEA1067

"
12

+

f-o
FROM DIAL
&
CONTROL CIRCUITS

PO

GAR

AlB

C1.

C8
10nF
MIC+

01'
BIA

0-------+--------'

MIC16

REG
GAS1

SLPE

r--I
I
I
I

GAS.

STAB

AGC
17

18

9

VEE

10

R7
C6

ZSAL

68.1k

100pF

C3
4.7/-,F

R9
20

R6

RS
3.6k

NOTE,

RFI capacitors are marked with an astensk

Figure A1. Basic Application Diagram of TEA1067 in Sets With DTMF Dialing

December 1988

6-143

II

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

R1

620

15
LN

Vee

11 IR

BZX79
12.F

'-"'"+-1-0 DTMF
1<

TEA1067

MUTE

fot1f-+--I'-+--t-+-<> MUTE
DIALING
PULSES

TELEPHONE
LINE

(A'B
B'A~--+--""

R1

C6
100pF

R9

20

88.1k

R6

RS
3.6k

R28

R25
<10k
BZx19

IOV

R24
<10k

R23
10M

NOTE,

RFI capacitors are marked with an astensk

Figure A2. Basic Application Diagram of TEA1067 in Sets With Combined Pulse and
Tone Dialing Including Interrupter With Interface

December 1988

6-144

FROM DIAL
&
CONTROL CIRCUITS

Signetics

AN1943
Supply of Peripheral Circuits
With the TEA 1067 Speech
Circuit

Linear Products

INTRODUCTION
The telephony line interface and speech
transmission circuits TEAl 060/1 have been
in use for several years now. They contain all
interface circuitry required to connect transducers and dialers to a telephone line.
A lot of components such as dialers and
computers have been developed which can
be interfaced to the TEA1060/1 easily. These
components are powered by the supply pOint
of the TEA1060/1.
To meet the North American Telephony requirements RS-470, the new speech circuit
TEAl 067 has been developed. TEAl 067 operates at a lower line voltage, which enables
it to operate in parallel with the convenltonal
telephone sets (unlike the TEA1060/1).

Application Note

incoming call. The upper limit of this
region is determined by the ability of
the telephone set to draw adequate
current for proper pull-up of central
office relays.
After this one-second period for incoming
calls, and during DTMF-dlallng, and after
called-party answer on outgoing calls (where
the relays are reqUired only to hold their
energized state), operation may fall within the
conditionally acceptable region of Figure 1.

JNACCEPTABL1E

I

REGION
I
(26,10.4)

(2O,V

I

CONomONALLY ACCEPTA~

However, a lower line voltage and the POSSIbility of connecting conventional telephone
sets in parallel have potentially severe effects
on the supply capabilities of the speech
circuit.
This application report contains some proposals to realize optimal connection of peripherals to the TEAl 067 speech circuit.

NORTH AMERICAN TELEPHONY
REQUIREMENTS R5-470 FOR
TELEPHONE SETS IN USA
Telephone sets used in the USA (and also in
some Far East countries) have to fulfill some
special demands which are described in the
RS-470 requirements. The points of importance for Philips speech circuits are:
• It is allowed to connect more telephone
sets in parallel. RS-470 doesn't specify
details, but it seems to be that
electronic speech circuits must remain
operative (at least at a reduced
performance) if a conventional (carbon
microphone) telephone set is connected
in parallel on a subscriber loop, haVing
the minimum line current of 20mA. For
measurements, a reasonable
replacement for such a conventional
telephone set seems to be a 200n
resistor.
• The off-hook tip-to-ring DC voltage
versus current characteristics must be In
the acceptable region of Figure 1 during
the on-hook to off-hook transition, and
during the make-interval of rotary dial
pulses on outgoing calls, and for at
least one second after answer of an
December 1988

REGION

126,7.8)
(2O,~_

I

ACCEPTABLE

I

REGION

I
I

10
20
LOOP CURRENT (mAl

30

Figure 1, DC Voltage vs Current
Characteristics
It is deSired that the off-hook tip-to-rlng Impedance of the telephone set be 600n
across the 200 - 3200Hz band. More specifically, the balance return loss (measured
against 600n) shall be greater than 3.5dB for
the 200 - 3200Hz band and greater than
7.OdB for the 500 - 2500Hz band.

EFFECTS OF RS-470 ON
PHILIPS SPEECH CIRCUITS
Under normal operation, the minimum line
current which can occur according to the RS470 requirements is 20mA. The minimum
supply capabilities of the supply point of the
TEA 106011 are according to Figure 2a.
Most Philips CMOS peripherals require a
minimum supply voltage of 2.5V. Taking into
account O.4V as the forward voltage drop of a
Schottky enable diode (BAT85: VF < 320mV
at 25°C and 1rnA), the mlntmum allowable
voltage of the supply POint of the TEA 1060/1
IS 2.9V. At thiS voltage the minimum available
supply current IS 1.2mA, according to Figure
2a, which IS enough to power a CMOS
mlcrocontroller (e.g., PCD3315) and a DTMF
generator (PCD3312).

6-145

However, there are two problems with the
TEA1060/1 With respect to the RS-470 reqUirements.
The first problem concerns the parallel connection of conventional telephone sets and
TEA1060/1 sets at low line currents. Taking a
resistance of 200n for the parallel set, the
line voltage at 20mA line current will drop to
about 3.8V (assuming 1rnA remaining current
for the TEA1060/1) or 2.3V after the polarity
guard. The transmitting stage of the
TEA1060/1 doesn't function at such low
voltages. In order to keep the transmitting
amplifier operating at such low line voltages
(with a reduced performance), the TEA 1067
has been designed.
Second, the maximum line voltage of the
TEA 1060/1, excluding the Interrupter CirCUIt,
measures 6.35V at 20mA [maximum line
voltage at 20mA (4.75V), plus temperature
effects (assume 0.1 V), plus polarity guard
voltage drop (assume 1.5V)], which IS O.35V
too much (see Figure 1). Therefore, the line
voltage of the TEA 1067 has been decreased
by 0.55V With respect to the TEA1060/1.
However, both measures have severe implications for the architecture adVised by
Phllips/Signetlcs hitherto.
If a 200n telephone set IS connected In
parallel with a TEAl 067 set on a 20mA loop,
the supply voltage for peripherals Will decrease to less than 2V. In applications With
the TEA1060/1, Phlllps/Slgnetlcs adVises
their customers to use a MOSFET of the type
BST76A as an Interrupter switch. Since the
gate-source threshold voltage of thiS type of
FET can be as high as 2 7V, problems can be
expected when used In a TEAl 067 set with a
200n parallel set - it can't be guaranteed
that the Interrupter SWitch remains conductIng. Therefore, a bipolar Interrupter will be
deSCribed which doesn't have thiS problem.
The problems that occur With the supply of
peripherals In thiS case Will be illustrated later.
Furthermore, due to the reduced line voltage
of the TEA1067, the supply capabilities of ItS
supply point are conSiderably reduced With
respect to the TEA 106011 (see Figure 2b). At
2.9V, a minimum supply current of only
3001lA can be guaranteed. This IS not enough
to power a mlcrocontroller and a DTMF dialer
(e.g., PCD3315 + PCD3312) Simultaneously.
Some suggestions to overcome thiS problem
Will be given later.

II

Signetics linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

AN1943

effect. In the next section it will be shown that
this measure adversely affects the supply
capabilities of the TEA 1067.

INCREASING THE SUPPLY
CAPABILITIES OF THE TEA1067

Use of an Inductor

SUPPLY VOLTAGE (V) ~

Figure 2. Minimum Supply Current Available for Peripherals as a Function of
Supply Voltage of TEA1060/1 (A) and TEA1067 (6) at 20mA Line Current

The bottleneck In the supply problems of the
TEA 1067 is in the 620r! resistor connected
between the pins LN and VCC of the
TEA 1067 (Figure 3). It determines the supply
capabilities of the TEA 1067 as well as the AC
Impedance of the circuit. A reduction of the
resistance therefore results in Improved supply capabilities, but also In poorer BRL figures.
If thiS DC resistance can be reduced while
maintaining the 600r! Impedance for AC, the
supply problem can be solved. This can be
realized by means of an inductor connected
In parallel with the 620r!.

A/B~--------~---------,

There are two POSSibIlities to realize a practical Inductor:

Vee

• Use of a call (Figure 5a)
• Use of an electronic Inductor (e.g.,
TEA 1080 supply IC (Figure 5b),
(discrete) gyrator cirCUit)

+

T1
BC547

Use of a Schottky Diode
Polarity Guard

SLPE

20

In case only DTMF dialing is used (without
FLASH), no interrupter cirCUit IS required and,
therefore, no transients due to line current
Interruplions can occur. This makes it POSSIble to realize protection with rugged lowvoltage zener diodes (e.g., Philips BZW14
with a maximum voltage dunng transients of
28V). At such low voltages, the high voltage
diodes reqUired in the polarity guard (e.g.,
BAS 11 which can stand 300V) normally can
be replaced by lOW-VOltage Schottky diodes
(e.g., BAT86 which can stand 50V) resulting
In a lower voltage drop over the polanty
guard. In Figure 6, two possible configurations are given.

B/A~--~----~------~------------4-----~------~--~---J

Figure 3. Circuit Diagram of Low-Voltage Interrupter

A LOW-VOLTAGE
INTERRUPTER
In Figure 3 the CIrCUIt diagram of an Interrupter IS given which operates at Input voltages

down to 1V
The circuitry around T2 and T3 IS commonly
used already In telephony applications and
needs no further explanation The Interface
function between this Interrupter and the
pulse dialer IS performed by transistor T1 and
resistor R4 USing transistors of the type
2N5401 and 2N5551 allows operation up to
150V In case higher voltages occur, a voltage limiting deVice (e.g., a VDR) has to be
used In front of the CIrCUitry. No current
limiting function IS accomplished In this Circuit.
In Figure 4 the tYPical voltage drop over the
Interrupter (VEC of T3) IS given as a function
of loop current uSing a 2 2kr! resistor for R3
A lower resistance lowers the voltage drop at
high line currents, but also reduces the current which IS left for the TEA1067.
December 1988

~ I-20

30

/
V

/

/

In Figure 6a the voltage gain (due to a lower
voltage drop) is about 0.5V; In Figure 6b it is
about 1.0V.

I---""'

40

50

60

70

80

ILlNE(mA)-

Figure 4. Voltage Drop VEe of T3 as a
Function of Line Current
Since R3 IS connected In parallel with the
600r! Impedance of the TEA 1067 CirCUitry,
the total set Impedance IS now lower than
600r!. USing 2 2kr! for R3, the TEA 1067
Impedance must be Increased to approxImately 850r! In order to compensate for thiS

6-146

It is pOSSible now to Increase the line voltage
of the TEA 1067 by 0.5 or 1.0V, thus increasIng the supply capabilities of the TEA 1067.
(The Increase will measure 0.5V /
620r! = 0.8mA In Figure 6a or 1.6mA In
Figure 6b.
Increase of the line voltage of the TEA 1067
can be achieved by means of an external
resistor between the pinS REG and SLPE. In
Figure 7 the relation between thiS resistance
and the resulting tYPical line voltage for a line
current of 20mA IS given.

Signetics Unear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

4.7JlF

lOOk

I•

1.2

...z

1.0

0:
0:

D.8

.."iii
~

o.s

.,~

0.4

i

02

1,\
,\

W

\

::>

10

:5

-::-

AN1943

'\

'-

!'.

. . . 1'-

o

350 400 450 500 550 500 850 700 750 500

TEA1067

SUPPLY RESIsrANCE (0)-

LSI0931S

a. Coil

b. TEA1080

Figure 8. Calculated Minimum Supply
Current Available at the Supply
Point of the TEA1067, at a Voltage
of 2.9V, Assuming a Subscriber Line
of 20mA, as a Function
of the Supply Resistance

Figure 5. Examples of Increasing the Supply Capabilities of the TEA 1067
500

1/
AlB

AlB

O----4~_<

2. IIZWI4

BIA

/

BIA o--~--+----'

o----t-----'

/

V

/
b. 6-Diode Solution With 1.0V Gain
(Due to a Lower Voltage Drop)

30

t

2Sir

:g.

m~
iI!
~

150:

i

/v
10

300

a. 4-Diode Solution With O.SV Gain
(Due to a Lower Voltage Drop)

/-

350400450500550500650700750500

SUPPLY RESIsrANCE(O)

Figure 6. Schottky Diode Polarity Guard With Protection
the TEA1067. Besides, It has a minor Influence on the power-down function of the
TEA1067.

Two Other Methods

\

\.

"- . . . . r-.
4

o

50

100

~EC>SlPE(kll) -

Figure 7. Typical Line Voltage
(VLN - VEE) as a Function of RREG-SLPE
at a Line Current of 20mA
However, this resistor causes a slightly in·
creased spread In the voltage drop and a
slightly modified temperature coefficient of
December 1988

In prinCiple, the RS-470 requirements give
two alternative ways to come out of the
supply problems of the TEA 1067:
1) The TEA 1067 itself fulfills the balance
return loss figures required With a large
margin. Accepting a smaller margin by
means of decreasing the AC Impedance
Will result In an Increase of the supply
capabilities.
2) The most severe supply problem occurs
when a DTMF dialer must be operative.
But In that case, operation in the conditionally acceptable region of Figure 1 IS
allowed! ThiS lightens the supply problems considerably.
In Figure 8, the minimum supply capabilities
of the TEA 1067 are given as a function of the
supply resistor of the TEA 1067. A subSCriber
line having the minimum line current of 20mA

6-147

Figure 9. Calculated Total Set
Impedance and BRL as a Function
of the Supply Resistor of the
TEA 1067 (Including Influence of
2.2kn Interrupter)
IS assumed here. Assuming the use of a
bipolar interrupter haVing a resistance of
2.2kn (which is connected In parallel to the
TEA1067), the resulting set impedance and
BRL are gIVen In Figure 9.
As can be seen in Figure 8, the supply
capabilities of the TEA 1067 equal those of
the TEA1060/1 if a supply resistor of 380n
(Instead of the 620n used for the TEA 10601
1) IS used. The resulting total set impedance
Will be 320n, resulting in a BRL of about
10dB (see Figure 9). ThiS still fulfills the RS470 reqUirements ( > 7dB between 500 and
2000Hz) With a safe margin.
However, change of the 620n resistor of the
TEA1067 results not only in a change of AC
impedance and an Improvement of the supply
pOint, but also In a change of microphone
gain (which depends linearly on the load

•

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

LN

Vee

LN

+

vee

AN1943

+

1IlO.F
TEA1067

TEA1067

REG

REG

'!i557

VEE

SLPE

lIlOk
VEE

'1

SLPE.t

lOOk
BC547

R

r

+
4.7.F ;:

20

+
4.7.F

20

a. HIGH = Normal Voltage, LOW = Increased Voltage

b. HIGH = Increased Voltage, LOW

=Normal Voltage

Figure 10. Circuit to Increase the Line Voltage Temporarily
impedance) and In a change of the drivIng
range of the transmIttIng stage. BesIdes,
rebalancIng the antl-sldetone bndge wIll become necessary.

AlB
LN

If a better BRL IS requIred, It is possIble to use
one of the cIrcuits given In Figure 10. In these
cIrcuits the supply resIstor IS Increased agaIn,
resultIng In better BRL fIgures, but also In
reduced supply capabIlitIes.

REG

VEE

December 1988

SLPE
R

20

D1
BAW62

.......

~
T1
BC557

+

4.7.F

R2

DP

;:~l00.F

BIA

The sWItching transIstor can be driven dIrectly
by a mute sIgnal generated by a DTMF
generator, resultIng In the nomInal line voltage except for the tIme DTMF tones are
generated. ThIS approach makes It possIble
to dimension the supply resIstor In such a way
that It can power all peripherals excludIng the
DTMF dialer. In case of DTMF dIaling, the line
voltage WIll be increased, resultIng In enough
supply current for the DTMF dIaler, too.

iI a dIal pulse or a flash sIgnal IS applied to
01, Cl IS dIscharged rapIdly vIa Dl, thus
bringIng back the line voltage Into the acceptable region of Figure 1.

C1
1.F

TEA1067

However, If maxImum supply current IS required (I.e., dUring DTMF dIaling), the line
voltage can be increased by actIvatIng the
transistor, thus gIvIng a hIgher maxImum supply current. ResIstor R Increases the line
voltage accordIng to the princIple described
previously and In FIgure 7.

lt IS also possible to drive the transIstor
automatIcally, accordIng to the CirCUIt gIven on
FIgure 11. Immediately after gOIng off-hook,
Tl IS sWItched off untIl Cl IS charged to Vee
(VREG - O.6V) vIa R2. UntIl then, the line
voltage will fall into the acceptable regIon of
FIgure 1. After thIS period, the lone voltage WIll
be increased and WIll fall into the condItIonally
acceptable region of FIgure 1.

Vee

Figure 11. Circuit Which Increases Line Voltage
if This is Allowed According to RS·470

>

>

a. After Initial Switch-On

b. During and After Pulse Dialing

Figure 12. Line Voltage as a Function of Time

6·148

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

AN1943

620

AlB

""

LN

:7-

@FILTER

I

Vee
DTMF

MK5380

M

'\n/

MUTE

TEA1067 MUTE

VEE

Voo

DTMF

Vss

REG
SLPE

KEYBOARD

lOOk
.tk

BIA

BC547 "

20

+

4.7j.lF

+
100IlF

Figure 13. TEA1067 Used in Combination With a 5380 DTMF Dialer
Notice that the power-down function of the
TEA 1067 remains fully operative In thiS case,
since the connection between the pins REG
and SLPE IS now removed.
In Figure 12, the line voltage after Imtlal
sWitch-on and during and after pulse dialing IS
shown.

TWO PRACTICAL EXAMPLES
In Ihe preceding text we have considered
several possibilities to increase the supply
capabilities of the TEAl 067. Now we Will look
at two practical examples.
The use of a TEAI067 With a CMOS DTMF
dialer (5380 in this case) Will be considered.
Later, the use of a TEAl 067 With the
PCD3315 repertory dialer and PCD3312
DTMF dialer Will be discussed.

TEA1067 Plus MK5380 CMOS
DTMF Dialer
The schematiC CirCUit of thiS combination IS
shown in Figure 13.

December 1988

Since an MK5380 In standby mode consumes
only 1501lA maximally at 2.5V, It can be
powered directly from the TEA 1067 supply
pOint uSing the standard supply resistor of
620n when the telephone set IS In ItS speech
mode.
However, in the dial mode, the supply current
of an MK5380 can be as high as 2mA at 2.5V,
while the TEA 1067 can deliver only I mA at
thiS voltage (Figure 2). Therefore, In the dial
mode an increase of the line voltage of
I mA x 620n IS reqUired. ThiS Will result In a
voltage over the telephone set that falls In the
conditionally acceptable region of Figure I
which IS allowed dunng DTMF dialing. ThiS
Increase of voltage can be achieved accordIng to the CirCUit given In Figure lOb uSing a
resistor of 39kn (Figure 7) between pin REG
of the TEA 1067 and the collector of the
BC54 7. The transistor can be controlled directly by the MUTE Signal of the 5380.
As an alternative, the 39kn resistor can be
connected directly between the pins REG

6-149

and SLPE of the TEA 1067 In combination
With the Schottky diode bridge of Figure 6b.
ThiS Will also result in a line voltage which IS
In the acceptable region of Figure I.
II a conventional telephone set is connected
In parallel to the Circuit of Figure 13, the
supply voltage for the 5380 dialer can drop to
below 2V. Since ItS mimmum supply voltage is
2.5V, proper DTMF tones generation can't be
guaranteed under these circumstances.

TEA1067 Plus PCD3315 and
PCD3312
Since It IS not allowed to have a line voltage
which falls Into the conditionally acceptable
region of Figure I dunng pulse dialing, it is not
pOSSible to use the approach descnbed previously here. Therefore, the pnnciple of Figure
II has been chosen for thiS example. In
Figure 14, the schematic diagram of the
cirCUitry used IS shown.

•

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

v!N5401

'$Ok

BATB5

470

AlB

BIA

""'

I

)-

;

LN

2.2k

.-J

VEEOTMFS

K2N555.

~BC547

='=

r

470k

'"F

-

Vee PO

TEA'067

'$Ok

k

+

w
MI--

REG

~

AN1943

BAW62

Voo
CE
3

OP

~~ L.

BC557
39k

20

v

PCD3315

M
Vss

1.12

+

4.7~F

+
lOO"F

SOA

"

I Voo
I

SCL

PCD3312
Vss

I
Figure 14. TEA1067 Used With PCD3315 and PCD3312
The minimum supply voltage of the PCD3315
and the PCD3312 IS 2 5V Since the
PCD3315 has to be powered via a senes
(Schottky) diode. the minimum supply pOint
voltage of the TEAl 067 allowed IS 29V. At
this voltage the TEAl 067 can deliver only
300l1A (Figure 2) Although the maximum
supply current of the PCD3315 dunng pulse
dialing IS not specified yet, 700l1A seems to
be a reasonable value According to Figure 8,
this can be reached by uSing a supply resistor
of 470n Instead of 602n. USing a bipolar
Interrupter with an Impedance of 2.2kn, this
will result In a balance return loss of stili 13dS
according to Figure 9.
In the case of DTMF dialing, the PCD3312
must also be powered. This can be achieved

December 1988

by Increasmg the Ime voltage of the
TEA 1067. The maximum operating current of
the PCD3312 IS specified as 1 2mA at 3.0V
USing a supply resistor of 470n, an extra
1.2mA can be gained by Increasing the line
voltage with 1.2mA X 470n ~ 0.6V. This results In a resistor of 39kn between pins REG
and SLPE of the TEAl 067.
Since the supply resistor In Figure 14 has
been reduced from 620n to 470n, a lot of
components around the TEA 1067 have to be
adapted to the new situation. The sending
gains and the sldetone are especially influenced by this measure.
If a conventional telephone set IS connected
in parallel with the CIrCUIt of Figure 14, the
supply POint voltage might drop to below 2V

6-150

As a result, the PCD3312 receives a too-low
supply voltage, and Improper generation of
DTMF tones might occur. For the PCD3315.
however, there won't be a problem. If the
supply POint voltage drops too far, It Simply
continues to operate on battery power (unless the CE voltage becomes too low) Of
("ourse, the lifetime of the battery will be
decreased considerably In this way
NOTE:
For Information on discrete semiconductors used In
this application note, contact Amperex Electronic

Corp Smithfield. RI (401) 232-0500
ThiS apphcatlon note was originally published as
Laboratory Report ETT8602, In Apnl 1986 The
report was written by J V Tlggelen at CAB -ELCOMA, The Netherlands

TEA1068

Signetics

Versatile Telephone
Transmission Circuit
Product Specification
Linear Products
DESCRIPTION
The TEA1068 is a bipolar integrated
circuit performing all speech and line
interface functions required in fully-electronic telephone sets. The circuit internay performs electronic switching between dialing and speech.

FEATURES

•

•
•

• Voltage regulator with adjustable
static resistance
• Provides supply for external
circuitry
• Symmetrical high-Impedance
Inputs (64kn) for dynamic,

•
•

magnetiC or piezoelectric
microphones
Asymmetrical high-Impedance
Input (32kn) for electret
microphone
DTMF signal input with
confidence tone
Mute input for pulse or DTMF
dialing
Power-down Input for pulse dial
or register recall
Receiving amplifier for magnetic,
dynamic or piezoelectric
earpieces

• Large amplification setting range
on microphone and earpiece
amplifiers
• Line loss compensation facility,
line current dependent for
microphone and receiving
amplifiers
• Gain control adaptable to
exchange supply
• Possibility to adjust the DC line
voltage

APPLICATION
• Electronic telephone sets

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

1B-Pin Plastic DIP (SOT-102HE)

DESCRIPTION

-25·C to +75·C

TEA1068PN

20-Pin SOL (SOT-163)

- 25·C to + 75·C

TEA1068TD

•

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

12

V

VLN

Repetitive line voltage during switch-on
or line interruption

13.2

V

VLNRM

Repetitive peak line voltage
tpfP = 1msf5s;
Rl o = 130; Ra = 200 (see Figure 8)

28

V

ILiNE

Line current

SYMBOL

PARAMETER

VLN

Positive line voltage (DC)

VI
-VI

Voltage on all other pins

P'-OT

Total power dissipation

TSTG

Storage temperature range

TA

Operating ambient temperature range

July 21. 1988

140

rnA

Vee +0.7
0.7

V
V

640

mW

-65 to +150

·C

-25 to +75

·C

6-151

853-1050 93934

Product Specification

Signetlcs Linear Products

TEA1068

Versatile Telephone Transmission Circuit

PIN CONFIGURATION
0'

N Package

Package
LN

SLPE

GAS"

AGC

G~

REG

GAS"

SLPE
AGC
REG
Vee

Vee

NC

MUTE

QR+

MUTE

DTMF

GAR

DTMF

PO

MIC-

PO

NC

MIC+

IR

STAB

IR

STAB

VEE

VEE
TOP VIEW

TOP VIEW

NOTE,

1 Available only In large SO package (SOL) with
different pinout
PIN
NO.

SYMBOL
LN
GAS 1

GAS2
OROR+
GAR

7
8
9
10
11
12
13
14
15
16
17
18
19
20

MICNC
MIC+
STAB
VEE
IR
NC
PO
OTMF
MUTE
Vee
REG
AGC
SLPE

July 21, 1988

DESCRIPTION

PIN
NO.

Positive hne terminal
Gam adjustment, transmitting
amplifier
Gam adjustment, transmrttmg
amplifier
Invertmg output. recelvmg
amplifier
Non-Inverting output, recelvmg
amplifier
Gain adjustment, receiving
amplifier
I nvertlng microphone Input
Not connected
Non-InvertIng microphone Input
Current stabilizer
Negative line terminal
ReceiVing amplifier Input
Not connected
Power-down Input
Dual-tone multi-frequency Input
Mute Input
Posltrve supply decouphng
Voltage regulator decouphng
Automatic gain control Input
Slope (DC resistance)
adjustment

SYMBOL

DESCRIPTION

GAS,

POSitive Ime connectIOn
Gain adjustment connection,

GAS2

Gam adjustment connection,

LN

sending amplifier
OROR+
GAR

7
8
9
10
11
12
13
14
15

MIC+
MICSTAB
VEE
IR
PO
OTMF
MUTE
Vee

16

REG

17

AGC
SLPE

18

sendmg ampllfler
Inverting output, receIVIng
amplifier
Non-Invert,ng output, receiVing

amplifier
Ga.n adjustment connection,
reCBlVtng ampllfler
Non-Inverting mIcrophone Input
Inverting microphone Input
Current stabilIzer connection
Negative hne connecbon
ReceiVing amplifier ,nput
Power-down Input
Dual-tone multi-frequency Input
Mute Input
PositIVe supply decouphng
connection
Voltage regulator decouphng
connectlon
Automallc gain control input
Slope (DC resistance)
adjustment connection

6-152

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

BLOCK DIAGRAM
LN
1

15

IR

11

---MIC-

8

I>
+

r-

7

I-

l-

13
dB

OTMF

0.....
0

L-

TEA1068

MIC+

6

J>~
i--

S

-+

5

+

I> -

4

GAR
QR+
QR-

L-

J>r-

2

GAS,

L
LS
I>
-

0.....
0

+

L-

I-

~~ I>
I

3

GAS"

14

MUTE

PO

12

I
I

SUPPLYANO
REFERENCE

I

II

CONTROL
CURRENT
&.

-

......

+

~

CURRENT
REFERENCE

I
10

b

16

REG

July 21, 1988

17
AGC

b
9

STAB

6-153

18

$LPE

Product Specificotion

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

DC ELECTRICAL CHARACTERISTICS

IUNE = 11 = 10 to 140mA; VEE
otherwise specified

= V10 = OV; f = 800Hz;

R9

= 20n;

TA

= 25°C,

unless

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

3.95
4.20
5.4

4.25
4.45
6.1

4.55
4.70
7
8

V
V
V
V

-4

-2

0

mV/oC

3.45
4.65

3.80
5.0

4.10
5.35

V
V

096
55

1.30
82

mA
p.A

64
32

77
38.5

kn
kn

Supply: LN and Vee (Pins 1 and 15)

VLN
VLN
VLN
VLN
AVLN/AT

Voltage drop over CIrCUIt V1 -10
microphone Inputs open
at IUNE = 5mA
at IUNE = 15mA
at IUNE = 100mA
at IUNE = 140mA
Vanatlon with temperature
IUNE = 15mA

VLN
VLN

Voltage drop over CIrCUIt
at IUNE = 15mA
RVA = Rl - 16 = 68kn
RVA = R16-18 = 39kn

Ice
lee

Supply current
PD (Pin 12) = LOW, Vee = 2.8V
PD (Pin 12) = HIGH; Vee = 2 8V

Microphone inputs MIC+ and MIC- (Pins 8 and 7)

IZ,sl
IZ,sl

Input Impedance
differential (between PinS 7 and 8)
single-ended (Pins 7 - 10 or Pins 8 - 10)

51
25.5

82

CMRR

Common-mode rejection ratio

Avo

Voltage amplification (Pins 7, 8-1) at IUNE

AAvo/Af

Vanatlon With frequency at f

AAvo/AT

Vanatlon With temperature at IUNE

= 300

= 15mA,

R7

= 68kn

to 3400Hz

= 50mA,

dB

51

52

53

dB

-0.5

±0.2

+0.5

dB

TA = -25°C to + 75°C

±0.2

dB

Dual-tone multi-frequency input DTMF (Pin 13)

IZ,sl

Input Impedance

168

20.7

24.6

Avo

Voltage amplification at IUNE

24.5

25.5

26.5

dB

AAVD/Af

Vanatlon With

-0.5

±0.2

+0.5

dB

AAvo/AT

Vanatlon With

= 15mA, R7 = 68kn
frequency at f = 300 to 3400Hz
temperature at IUNE = 50mA, TA = -25°C

±0.2

to + 75°C

kn

dB

Gain adjustment GAS1 and GAS2 (Pins 2 and 3)
AAvo

Amplification vanatlon With R7 transmitting amplifier

-8

+8

dB

Transmitting amplifier output LN (Pin 1)

= 15mA,

VLN(RMS)
VLN(RMS)

Output voltage at IUNE
dTOT = 2%
dTOT = 10%

VNO(RMS)

NOise output voltage
IUNE = 15mA; R7 = 68kn, R7- 8 = 200n
psophometncally weighted (P53 curve)

July 21, 1988

1.9

6-154

2.3
2.6

V
V

-72

dBmp

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

DC ELECTRICAL CHARACTERISTICS (Continued) IUNE = 11 = 10 to 140mA; VEE = V10 = OV; f = 800Hz; R9 = 200;
TA = 25°C, unless otherwise specified.

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

16.5

20.4

24.3

Receiving amplifier input IR (Pin 11)

IZ,sl

Input Impedance

kO

Receiving amplifier outputs QR+ and QR- (Pins 5 and 4)

IZosl

Output impedance; single-ended

Avo
Avo

Voltage amplification from Pin 11 to Pins 4 or 5
IUNE = 15mA; R4 = 100kO;
Single-ended; RL = 3000
differential; RL = 6000

!::.Avo/ L\f

VanallOn With frequency, f

!::.Avo/ L\T

Variation with temperature at IUNE

VO(RMS)
VO(RMS)
VO(RMS)

Output voltage at Icc = 0; dTOT = 2%;
R4 = 100kO; sine-wave drive
Single-ended; RL = 1500
single-ended; RL = 4500
differential; CL = 47nF; (1000 senes resistor); f

VNO(RMS)
VNO(RMS)

NOise output voltage at IUNE = 15mA; R4 = 100kO;
Pin 11 = IR = open
Psophometrically weighted (P53 curve)
single-ended; RL = 3000
differential; RL = 6000

= 300

4

to 3400Hz

= 50mA;

24
30

25
31

26
32

dB
dB

-0.5

±0.2

+0.5

dB

TA = -25 to + 75°C

= 3400Hz

0

±0.2

dB

0.3

0.38

V

0.4
0.8

0.52
1.0

V
V

50
100

/lV
/lV

Gain adjustment GAR (Pin 6)
!::.Avo

Amplification variation
with R4 between Pins 6 and 5 receIVIng amplifier

-8

+8

dB

1.5

Vee
0.3

V
V

15

/lA

MUTE Input (Pin 14)
V,H
V,L

Input voltage
HIGH
LOW

IMUTE

Input current

8

Av~

Reduction of voltage amplification
MIC+ and MIC- to LN at MUTE = HIGH

70

Avo

Voltage amplification from
DTMF to QR+ or QR- to LN at MUTE
R4 = 100kO; RL single-ended = 3000

= HIGH

-21

-19

dB

-17

dB

Vee
0.3

V
V

10

JJA

Power-down Input PO (Pin 12)
V,H
V,L

Input voltage
HIGH
LOW

Ipo

Input current

1.5
5

Automatic gain control AGe (Pin 17)
-!::.Avo

IUNE
IUNE

July 21, 1988

Controlling the gain from Pin 11 to Pins 4 and 5
and the gain from Pins 7 and 8 to Pin 1
R6 = 11 OkO; connected between Pins 17 and 10
Amplification control range
Highest line current for AMAX
Lowest line current for AMIN

6-155

6

dB

22
60

mA
mA

•

Product Specification

Signetics Linear Products

Versatile Telephone Transmission Circuit

FUNCTIONAL DESCRIPTION
Supply: Vee, LN, SLPE, REG
and STAB
The circUit and its peripheral circuits usually
are supplied from the telephone line. The
circuit develops Its own supply voltage at Vee
and regulates its voltage drop. The supply
voltage Vec may also be used to supply
external peripheral circUits, e.g., dialing and
control circuits.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and
VEE; the internal voltage regulator has to be
decoupled by a capacitor from REG to VEE.
An Internal current stabilizer IS set by a
resistor of 3.6k!1 between STAB and VEE.
The DC current flowing Into the set is determined by the exchange supply voltage VEXCH,
the feeding bridge resistance RExeH, the DC
resistance of the subscriber line RUNE and
the DC voltage on the subscriber set (see
Figure 1).
If the line current IUNE exceeds the current
Icc + 0.5mA reqUired by the circuit itself, (Icc
ca. 1mAl, plus the current Ip required by the
peripheral circuits connected to Vee, then the
voltage regulator diverts the excess current
via LN.
The voltage regulator adjusts the average
voltage on LN to:
VLN = VREF + ISLPE X R9
= VREF + (IUNE - Icc - 0.5 X 10- 3 -led
X R9
VREF being an Internally-generated temperature-compensated reference voltage of 4.2V
and R9 being an external resistor connected
between SLPE and VEE. The preferred value
of R9 is 20!1. Changing R9 Will have Influence
on microphone gain, DTMF gain, gain control
characteristics, side tone and maximum output swing on LN.
Under normal conditions ISLPE }> Icc +
0.5mA + Icc. The static behaVior of the circuit
then equals a 4.2V voltage regulator diode
with an internal resistance R9. In the audio
frequency range the dynamic Impedance
equals R1.
The internal reference voltage can be adjusted by means of an external resistor RVA. This
resistor connected between LN (Pin 1) and
REG (Pin 16) will decrease the internal reference voltage. RVA connected between REG
(Pin 16) and SLPE (Pin 18) Will Increase the
internal reference voltage. The current Icc
available from Vee for supplying peripheral
circuits depends on external components and
on the line current. Figure 2 shows this
current for Vee > 2.2V and for Vec > 3V. Of
which 3V being the minimum supply voltage
for most CMOS circUits including a diode
July 21, 1988

voltage drop for an enable diode. If MUTE IS
LOW the available current IS further reduced
when the receiVing amplifier is driven.

Microphone Inputs MIC+ and
MIC- and Gain Adjustment Pins
GAS1 and GAS2
The TEA 1068 has symmetrical microphone
Inputs. Its input impedance IS 64k!1
(2 X 32k!1) and its voltage amplification is
typical 52dB. Either dynamic, magnetiC, piezoelectriC microphones or an electret microphone with built-In FET source-follower can
be used.
The arrangements with the microphone types
mentioned are shown In Figure 3.
The amplification of the microphone amplifier
can be adjusted over a range of + or -8dB to
suit the sensitivity of the transducer used. The
amplification IS proportional to external resIstor R7 connected between GASl and GAS2.
An external capacitor C6 of 1OOpF between
GASl and SLPE IS reqUired to ensure stability. A larger value may be chosen to obtain a
first-order low-pass filter. The cut-oft frequency corresponds with the time constant
R7 X C6.

Mute Input MUTE
A HIGH level at MUTE enables the DTMF
Input and Inhibits the microphone inputs and
the receiVing amplifier input; a LOW level or
an open-circuit does the reverse. SWitching
the mute Input Will cause negligible clicks at
the telephone outputs and on the line.

Dual-Tone Multi-Frequency Input
DTMF
When the DTMF input is enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTMF to LN IS typically.
25.5dB and varies with R7 in the same way as
the amplification of the microphone amplifier.
The Signaling tones can be heard In the
earpiece at a low level (confidence tone).

Receiving Amplifier: IR, QR+,
QR- and GAR
The receiving amplifier has one Input IR and
two complementary outputs, a non-Inverting
output OR+ and an inverting output OR-.
These outputs may be used for Single-ended
or for differential drive, depending on the
sensitivity and type of earpiece used (see
Figure 4). AmpliflcallOn from IR to OR+ IS typo
25dB. This will be suffiCient for lOW-Impedance magnetic or dynamiC eal pieces; these
are suited for single-ended drive. By uSing
both outputs (dlfferenllal drive) the amplification is increased by 6dB and thiS makes
dlfferenllal drive pOSSible. ThiS feature can be
used In case the earpiece Impedance exceeds 450!1 (high-Impedance dynamiC, magnetic or piezoelectriC earpleces).

6-156

TEA1068

The output voltage of the receIVIng amplifier
IS speCified for continuous-wave drive. The
maximum output voltage Will be higher under
speech conditions, where the ratio of peak
and RMS value IS higher.
The ampllficallOn of the receIVIng amplifier
can be adjusted over a range of + and -8dB
to SUIt the sensItivity of the transducer used.
The amplification IS proportional to external
resistor R4 connected from GAR to OR+.
Two external capacitors C4 (100pF) and C7
(10 X C4 = 1nF) are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order low-pass filter. The cutoft frequency corresponds with the time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor R6 from
AGC to VEE. ThiS automatic gain control
varies the amplification of the microphone
amplifier and the receiving amplifier In accordance With the DC line current. The control
range IS 6dB. ThiS corresponds With a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable With a DC resistance of
176S1/km and an average attenuation of
1.2dB/km.
ReSistor R6 should be chosen In accordance
With the exchange supply voltage and ItS
feeding bridge resistance (see Figure 5 and
Table 1). Different values of R6 give the same
ratio of line currents for begin and end of the
control range.
If automatic line loss compensallOn IS not
required, AGC may be left open. The amplifiers then all give their maximum amplification
as specified.

Power-Down Input PO
During pulse dialing or register recall (timed
loop break), the telephone line IS Interrupted;
as a consequence, it prOVides no supply for
the transmission cirCUit and the peripherals
connected to Vee These gaps have to be
bridged by the charge In the smoothing capacitor C1. The reqUirements on this capacItor are relaxed by applYing a HIGH level to
the PO Input during the time of the loop break,
which reduces the supply current from tYPIcally 1mA to tYPically 55/lA.
A HIGH level at PO further disconnects the
capacitor at REG, With the effect that the
voltage stabilizer Will have no SWitch-on delay
after line InterrupllOns. ThiS results In no
contribution of the IC to the current waveform
during pulse dialing or register recall. When
thiS faCIlity is not reqUired PO may be left
open.

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

Side-Tone Suppression
Suppression of the transmitted signal In the
earpiece IS obtained by the antl-slde-tone
network consisting of Rt IIZLlNE, R2, R3, RB,
R9 and ZBAl (see Figure B). Maximum compensation is obtained when the following
conditions are fulfilled.
a) R9.R2 = R1 (R3 + [RBIIZBAU)
b) [ZBAl/(ZBAl + RB)] = [ZLlNE/(ZLINE + R1)].

RUNE

R1

IUNE

--,

I
I

Icc

'SLPE +O.SmA

Icc

15
RexCH

LN

TEA1068

DC

If fixed values are chosen for R 1, R2, R3 and

jo.smA

AC

1
+

R9, then condition a) will always be fulfilled
provided that I RSIIZBAll ~ R3.
To obtain optimum side tone suppression,
condition b) has to be fulfilled resulting in.
ZBAl = (RS/R1 )ZLlNE = k.ZLlNE

REG

V EXCH

STAB
ISLPE

SLPE

VEE

18

10

R5

CI

PERIPHERAL
CIRCUITS

i

I
I
_.J

R8

where k IS a scale factor k = (RS/R1).
Scale factor k (value of RS) must be chosen
to meet the following criteria.

Figure 1. Supply Arrangement
• compatibility With a standard capacitor
from the E6 or E12 range for ZBAl
• IZBAlIIRSI~ R3
• IZBAl + Rsl~ R9

!!..

In practice, ZLiNE varies strongly With line
length and cable type; consequently, an average value has to be chosen for ZBAl. The
suppression further depends on the accuracy
with which ZBAl/k equals the average line
Impedance.

•

The anll-slde-tone network as used In the
standard application (Figure S) attenuates the
signal from the line WIth 32dB. The attenuation IS nearly flat over the audio frequency
range.
Instead of the above described speCial
TEA t 06S bridge, the conventional Wheatstone bridge configuration can be used as an
alternative ann-slde-tone circuit. Both bndge
types can be used With 81ther a resistive set
Impedance or with a complex set Impedance.

July 21, 19S5

NOTES:
Curves (a) and (a') are valid when the receMng amplifier IS not dnven or when MUTE IS HIGH. curves (b)
and (b') are valid when MUTE IS LOW and the tecetYlng ampllfter IS dnven at VOIRMSI 150mV and

Rl ;;; 1500 asymmetrical

=

20n

'UNE - 15mA at VLN ;;; 4 45V, Rt - 6200 and R9 0) - 2 55mA, b) = 2 1mA, 0') = 1 2mA and b') = 0 75mA

Figure 2. Maximum Current Icc Available from Vcc for Peripheral Circuitry with
Vee> 2.2V and Vee> 3V

6-157

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

r--"""1r---'-i MIC +

""w.,.....r---'-I MIC+

'----4--.:-j MIC-

.....w........---'-I MIC-

NOTE:
The resistor marked (1) may be connected to lower
the termlnatmg Impedance In case of senslt:ve miCrophone types, a resistor attenuator can be used to prevent overloadmg of the microphone Inputs

a. Magnetic or Dynamic
Microphone

b. Electret Microphone

c. Piezoelectric Microphone

Figure 3. Alternative Microphone Arrangements

::~Ll

..U

a. Dynamic Telephone with
Less Than 450[2 Impedance

"'~.

OR+O

,-·

"'0.·

~-u~-

LD01070S

LD07081$

b. Dynamic Telephone with
More Than 450[2 Impedance

NOTE:
The resistor marked (2) IS reqUlf'ed to
Increase the phase margin (capacitIve

(mductIVe load)

load)

c. Magnetic Telephone with
More Than 450[2 Impedance

d. Piezoelectric Telephone

Figure 4. Alternative Receiver Arrangements

'"

R6=~

\\ ,'\.
\ 1\ \. 0-.
\ \'\.

-48+V~\ ~k~kQ
.

kQ

\

-6
20

\
40

\

\

R9=2OQ

60

100

120

140

160

Figure 5. Variation of Amplification with Line Current, with RS as a Parameter

July 21, 1988

LD0709QS

NOTE:
The reSistor marked (1) may be
connected to prevent distortion

6-158

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

Table 1. Values of Resistor R6 for Optimum Line Loss
Compensation, for Various Usual Values of Exchange
Supply Voltage VEXCH and Exchange Feeding Bridge
Resistance REXCH.
REXCH (n)
400

600

800

1000

R6 (kn)

VEXCH
(V)

24

61.9

48.7

X

X

36

100

78.7

68

60.4

48

140

110

93.1

82

60

X

X

120

102

NOTE:

R9

~

20n
R1
620

~

IR

1~.F

1,

1'5

Vee

LN

QR-

~

Vo
8

~v,

MIC+
QR+

I

5
R4

MIC-

lOOk
GAR

TEA1068

6

lC4

RL
600

flOOPF

b~

13
OTMF

InF

~~.F

10 TO 140mA

2

L.o~
:

~ 10.F

GAS,
MUTE

RI
68k

~

PO
VEE

10
'V

REG
16

AGC

STAB

17

9

GAS,
SLPE

:=~PF

-

3

18

V,
+C3

T4.7·F

R6

RS
3.6k

R9
20

NOTES,
Voltage amplification IS defmed as Avo = 20 log IVoNl1
For measuring the amphflcatton from MIC+ and MIG-, the MUTE mput should be LOW or open, for measunng the DTMF Input, MUTE should be HIGH
Inputs not under test should be open

Figure 6. Test Circuit for Defining Voltage Amplification of MIC +. MIC- and DTMF Inputs

July 21, 1988

6-159

•

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

R1
620

IUNE

1,

1'5

11

LN

Vee

IR

+
QR-

~I-ZL

1'0"F

~

o----!.

V,

'"

MIC+

t

Vo

5
QR+

600
R4
lOOk

MICGAR

TEA1068

~

100",F

6

;::~PF
II

C7

OTMF

1nF

:+C1
100f.lF

lOTOl40mA

2

~

GAS,
MUTE
R7

~

PO
VEE
10

REG
16

: +;'LF

AGC

STAB

17

R6

9

R5
3.6k

GAS,
SLPE

3

l~PF

r--

,.

R9
20

NOTE:
Voltage amplification IS defined as Avo = 2010g IVoIVIl

Figure 7. Test Circuit for Defining Voltage Amplification of the Receiving Amplifier

July 21, 1988

6-160

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

APPLICATION INFORMATION
R1
620
R10
13

R2
130k

C5
100nF

11

LN

Vee

IR
R3
3.92k

+

Rl1
OR13
DTMF
OR+
14

C4
C7
lnF

MUTE

TEA1068

100pF
GAR

FROM DIAL
AND
CONTROL
CIRCUITS

12
PD
MIC+

MICSLPE

R8

GAS,

GAS,

18

390
R7

C6

REG

AGC

16

17

+C3
4.7"F

R8

STAB

VEE

10
R5
3.6k

100pF

R9

20

NOTES:
The brtdge to the left, the zener diode and R10 limit the current and the voltage Into the CircUIt dUring the tranSients
Pulse dlalmg or register recall require a different protection arangement

Figure 8. Typical Application of the TEA 1068, Shown Here with a Piezoelectric Earpiece and DTMF Dialing

July 21. 1988

6-161

II

Product Specification

Slgnetlcs Linear Products

TEA 1068

Versatile Telephone Transmission Circuit

VDO
DTMF 1-----1 DTMF
DTMF

DIALER
PDI--~--IFL

TaEPHONE
UNE

I

BST78

____________ ..JI
LOO7t41S

NOTE:
The dashed lines show an optional ftash (register recall by times loop back)

a. DTMF Set with a CMOS DTMF Dialing Circuit

v••
DTMF

TEA1D68

MUTE

M

PD

PCD3320
FAMILY

DP
Vss

VEE
TELEPHONE
UNE

b. Pulse Dial Set with One of the PCD3320 Family of CMOS Interupted Current Loop Dialing Clrculta

DTMFI----,
MUTE ...PD

.......-+-i M

PCD3343

1--+-+--1 DP/FL

TaEPHONE
LINE

L-_-HHDTMF
PCD3312

L00716tS

c. Dual-standard (Pulse and DTMF) Feature Phone with the PCD3343 2CMOS Telephone Controller
and the PCD3312 CMOS DTMF Generator with I C Bus

Figure 9. Typlcsl

July 21, 1988

Appll~atlons

of the TEAI068 (Simplified)

6-162

Signetics

Section 7
Radio/Audio

Linear Products

INDEX
RADIO CIRCUITS
AM Radio
TDA1072A
AN1961
TEA5570

AM ReceIver CIrcUIt
Integrated AM TDA1072A ReceIver
AM/FM RadIo ReceIver CirCUIt

7-3
7-15
7-26

FM IF System ..
Double-Balanced Mixer and OscIllator
New Low Power SIngle SIdeband CirCUIts
ApplYing the OscIllator of the NE602 In Low Power M,xer
Applications. . . . .. ... .
HIgh-Performance Low-Power FM IF System
AudIo DecIbel Level Detector WIth Meter Driver
Double-Balanced M,xer and OscIllator
Low Power FM IF System (Independent IF Amp)
Interference Suppressor .
FM Front-End IC.
FM-IF (Quadrature Detector)
Single-ChIp FM RadIo CirCUIt
A Complete FM RadIo on a ChIp
TDA7000 for Narrow-Band FM ReceptIon
FM RadIo CIrcUIt (SO Package)
Single-ChIp FM RadIo CirCUIt
FM/IF System ..... .
AM/FM RadIo ReceIver CirCUIt.

4-99
4-66
4-72

FM Radio
CA3089
NE602
AN1981
AN1982
NE/SA604A
AN1991
NE612
NE614A
TDA1001B
TDA1574
TDA1576
TDA7000
AN192
AN193
TDA7010
TDA7021
TEA5560
TEA5570

4-80
4-114
4-124
4-83
4-141
7-35
4-89
4-156
7-41
7-46
7-61
7-77
7-82
7-88
7-26

Stereo Decoder
TDA 1578A
TDA7040
TEA5581
11A758
AN191

PLL Stereo Decoder
Low Voltage PLL Stereo Decoder
PLL Stereo Decoder ...
FM Stereo MultIplex Decoder, Phase-Locked Loop ..
Stereo Decoder ApplicatIons USing the I1A758

7-96
7-105
7-111
7-118
7-123

Digital Tuning Circuit
SAA1057
AN196
AN197

PLL RadIo TUning CirCUIt ...
SIngle-ChIp SynthesIzer for RadIo TUning.
AnalysIs and BasIc ApplicatIon of the SAA 1057.

4·182
4-190
4-197

AUDIO CIRCUITS
Preamplifiers
NE542
AN190

Dual Low-NoIse PreamplifIer.
ApplicatIons of Low NOIse Stereo AmplifIers: NE542

7-131
7-135

Tone/Volume/Switching
TDA 1029
TDA1074A
TDA 1524A
TDA8440
TEA6300

Stereo Audio SWitch ...........................................................
DC-Controlled Dual Potentiometer CirCUit .................................
Stereo Audio ControL..........................................................
Video and Audio SWitch IC ..................................................
Digitally-Controlled Tone, Volume, and Fader Control Circuit ........

7-138
7-147
7-154
7-162
7-168

Dolby Digital Audio Decoder................................ ................
Dolby NOise Reduction CirCUit ...............................................
Low Voltage Dolby NOise Reduction CirCUit .............................
Dolby B-Type NOise Reduction CirCUIt.. ..................................

7-178
7-182
7-187
7-192

Dolby
NE5240
NE645/646
NE648/649
NE650

Power Amplifiers

Symbols and Definitions for Audio Power Amplifiers ...................................... .. 7-197
TDA 1010A
6W Audio Amplifier With Preamplifier .................................... .. 7-198
TDA 10llA
2 to 6W Audio Power Amplifier With Preamplifier .................... .. 7-203
TDA1013A
4W Audio Amplifier With DC Volume Control .......................... .. 7-207
AN148
Audio Amplifier With TDA1013A .......................................... .. 7-210
TDA1015
1 to 4W Audio Amplifier With Preamplifier ............................... . 7-219
TDA1020
12W Audio Amplifier With Preamplifier ................................... .. 7-224
TDA 1510
2 X 12W Audio Ampllfler. ................................................... .. 7-228
AN1491
Car Radio Audio Power Amplifier up to 24W With the TDA1510 .. . 7-232
TDA 1512
12 to 20W Audio Amplifier ................................................. .. 7-240
TDA 1514
40W High Performance HI-FI Amplifier .................................. .. 7-245
TDA1515A
24W BTL Audio Amplifier ................................................... .. 7-248
AN 1481
Car Radio Audio Power Amplifiers up to 20W With the
TDA1515 ......................................................................... . 7-252
TDA1520B
20W HI-Fi Audio Amplifier ................................................... . 7-259
AN149
20W HI-FI Power Amplifier With the TDA1520A ....................... .. 7-264
2 x 12 HI-FI Audio Power Amplifier ....................................... .. 7-269
TDA1521
TDA2611A
5W Audio Amplifier ............................................................ . 7-274
TDA7050
Low Voltage Mono/Stereo Power Amplifier ............................ .. 7-278
1 Watt Low Voltage Audio Power Amplifier ............................ .. 7-281
TDA7052
COMPACT DISK
SAA7210
Decoder for Compact DIsc Digital Audio System....................... 7-284
Digital Filter for Compact DIsc Digital Audio System.................. 7-298
SAA7220
Dual 16-Blt Dlgltal-to.Analog Converter ....
TDA1541A
. .............. 7-310

TDA1072A

Signetics

AM Receiver Circuit
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA 1072A integrated AM receiver
circuit performs the active function and
part of the filtering function of an AM
radio receiver. It is intended for use In
mains-fed home receivers and car radios. The circuit can be used for oscillator
frequencies up to 50MHz and can handle RF Signals up to 500mV. RF radiation and sensitivity to interference are
minimized by an almost symmetrical design. The voltage-controlled OSCillator
provides signals with extremely low distortion and high spectral purity over the
whole frequency range even when tuning with variable capacitance diodes. If
required, band switching diodes can
easily be applied. SelectiVity IS obtained
using a block filter before the IF amplifier.

• Inputs protected against damage
by static discharge
• Gain-controlled RF stage
• Double-balanced mixer
• Separately buffered, voltagecontrolled and temperaturecompensated oscillator, designed
for simple coils
• Gain-controlled IF stage with
wide AGC range
• Full-wave, balanced envelope
detector
• Internal generation of AGC
voltage with possibility of
second-order filtering
• Buffered field-strength Indicator
driver with short-circuit
protection
• AF preamplifier with possibilities
for simple AF filtering
• Electronic standby switch

PIN CONFIGURATION

N Package
MIXER OUT

GROUND

MUTE

RFBYPASS

lOP VIEW

APPLICATIONS
• AM receiver
• Communications receiver

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-Pln PlastiC DIP

o to +70·C

TDA1072AN

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc = V13 - 16

Supply voltage

20

V

PTOT

Total power diSSipation

875

mW

V14-15

Input voltage

12

V

V14-16, V15-16
11141, 1115 1

Input current

TA

Operating ambient temperature range

TSTG

Storage temperature range

TJ

Junction temperature

OJA

Thermal resistance from junction to ambient

November 14, 1986

7-3

Vcc

V

200

mA

-40 to +80

·C

-65 to +150

·C

+125

·C

80

·C/W

853-0965 86551

•

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

BLOCK DIAGRAM

-=

~~@::es

HI
&0

",,-so

r&---=

D

-=
18

TllA1II72A

: ?

R2

V,

22

-=

+

CI

C2

1110111'

lIIOnF

14

15

~ ~

C3

tr

~
oJ

Vee
13

12

TlO111'

-=

.... (8)

2.7k
VIID

V,

NOTES;
1 Cod Data TOKO sample no 7XNS-A7523DY, L1 NlIN2 - 12/32,
2. Filter Data ZF = 7001l at R3-4 "" 3kn, Z.... 48kn

~r

11

220
25

November 14, 1988

.l.ee

00 -

65,

Oa -

57

7-4

170

Signetics linear Products

Product Specification

AM Receiver Circuit

TDA1072A

1MH~; fM = 400Hz; m = 30%; flF = 460kHz;
measured In Block Diagram and Test CircUit. unless otherwise specilied.

DC ELECTRICAL CHARACTERISTICS Vcc = V13-16 = 8.5V; TA = 25'C; fl =

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Supplies
Vcc = V13- 16

Supply voltage

7.5

8.5

18

V

Icc= 113

Supply current

15

23

30

mA

RF stage and mixer
V14-16.
V15-16

Input voltage (DC value)

R14-16.
R15-16
C14-16.
C15-16

RF input Impedance at VI

< 300l1V

R14-16.
R15-16
C14 - 16.
C15-16

RF Input impedance at VI

> 10mV

V

5.5

kQ

25

pF

8

kQ

22

pF

6

kQ
pF

6.5

mAIV

500

Rl - 16
Cl-16

IF output impedance

111V1

Conversion transconductance before start of AGC

V1 -13(P-P)

Maximum IF output voltage. inductive coupling to Pin 1

11

VI(RMS)

Vce /2

5

V

DC value of output current (Pin 1) at VI =OV

1.2

mA

AGC range of input stage

30

dB

RF signal handling capability:
input voltage for THD = 3% at m = 80%

500

mV

Oscillator
60

MHz
mV

200

kQ

60

Q

Frequency range

Vl1-12

Oscillator amplitude (Pins 11 to 12)

R12-11 (EXT)

External load impedance

R12-11 (EXT)

External load Impedance for no oscillation

RR

Ripple rejection at VCC(RMS) = 100mV; fp = 100Hz
(RR = 20 log [V13-161V11-16])

55

dB

Vl1-16

Source voltage for switching diodes (6 X VBE)

4.2

V

-111

DC output current (lor sWitching diodes)

LlV ll _ 16

Change of output voltage at
Lll11 = 20mA (switch to maximum load)

0.6

150

lose

130
0.5

0

20
0.5

mA
V

Buffered oscillator output
VlO-16

DC output voltage

0.7

V

V1O- 16(P-P)

Output signal amplitude

320

mV

R10

Output Impedance

170

-I 1O(PEAK)

Output current

November 14. 1986

Q
3

7-5

mA

•

Product Specification

Signetlcs Linear Products

TDA1072A

AM Receiver Circuit

DC ELECTRICAL CHARACTERISTICS (Continued) vee - V13_16 = 8.5V; TA = 25·C; II = 1MHz; 1M = 400Hz; m - 30%;
IIF - 460kHz; measured in Block Diagram and Test Circuit,
unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

IF, AGe, and AF stages
V3_16,
V4_16

De input voltage

2.0
2.4

R3_4

3

V
3.9

kO

IF input impedance
7

pF

V3_4

IF input voltage lor THO = 3% at m = 80%

90

mV

V3-41V6-16

Voltage gain belore start 01 AGC

68

dB

tJ.V3_4

AGC range 01 IF stages; change 01
V3-4 lor 1dB change 01 VO(AF);
V3-4 (REF) = 75mV

55

dB

VO(AF)

AF output voltage at V3-4(IF) = 50p.V

130

mV

VO(AF)

AF output voltage at V3 _ 4(1F) = 1mV

310

mV

IZol

AF output impedance (Pin 6)

3.5

kO

Ca-4

Indicator driver
V9-16

Output voltage at VI - OmV; RL(9) - 2.7kO

V9-16

Output voltage at VI - 500mV; RL(9) - 2.7kO

2.5

RL(9)

Load resistance

1.5

20

150

2.8

3.1

mV
V
kO

Standby switch
V2- 16
V2- 16
-12
112 I

Switching threshold at Vee = 7.5 to 18V; TA = -40 to + 80·C
on-voltage
off-voltage
on-current at V2_IS=OV
off-current at V2_16 - 20V

November 14, 1986

7-6

0
3.5

2.0
20
200
10

V
V
p.A
p.A

Product Specification

Signetics Linear Products

TDA1072A

AM Receiver Circuit

OPERATING CHARACTERISTICS Vcc=8.5V; fl=lMHz; m=30%; fM=400Hz; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
MIN

TYP

MAX

RF sensitivity

VI

RF input required for S + NIN = 6dB

1.5

JiV

VI

RF input required for S + NIN = 26dB

15

JiV

VI

RF input required for S + NIN = 46dB

150

JiV

VI

RF input at start of AGC

30

JiV

RF large signal handling

VI

RF input at THO = 3%; m = 80%

500

mV

VI

RF input at THO = 3%; m = 30%

700

mV

VI

RF input at THO = 10%; m = 30%

900

mV

c;'VI

Change of VI for ldB change of VO(AF); VI (REF) = 500mV

86

dB

c;'VI

Change of VI lor 6dB change of VO(AF); VI(REF) = 500mV

91

dB

AGe range

Output signal

VO(AF)
VO(AF)

AF output voltage at VI = 4JiV; m = 80%

mV

130
240

AF output voltage at VI = 1mV

310

390

mV

0.5

%

dTOr

THO at VI = lmV; m = 80%

dror

THO at VI = 500mV; m = 30%

1

%

(S+N)/N

Signal-to-noise ratio at VI = 100mV

58

dB

RR

Ripple rejection at VI = 2mV; VCC(RMS) = 100mV; fp = 100Hz
(RR = 20 log [VCCIVO(AF)))

38

dB

Unwanted signals

a21F
a31F

Suppression of IF whistles at VI = 15JiV; m = 0% related to
AF signal of m = 30%
at fJ "'2 x flF
at fJ "'3 X flF

37
44

dB
dB

alF
alF

IF suppression at RF input
for symmetrical input
for asymmetrical input

40
40

dB
dB

11(OSC)
11(20SC)

Residual oscillator signal at mixer output
at fosc
at 2 x lose

1
1.1

JiA
JiA

November 14, 1986

7-7

Signetics Linear Products

Product Specification

TDA1072A

AM Receiver Circuit

FUNCTIONAL DESCRIPTION
Gain-Controlled RF Stage and
Mixer
The differential amplifier in the RF stage
employs an AGC negative feedback network
to provide a WIde dynamic range. Very good
cross-modulation behavior is achieved by
AGC delays at the various Signal stages.
Large signals are handled with low distortion
and the slgnal-to-noise ratio of small signals
is Improved. Low noise working IS achieved In
the differential amplifier by uSing transistors
With low base resistance.
A double-balanced mixer prOVides the IF
output signal to Pin 1.

OSCillator
The differential amplifier oscillator is temperature-compensated and IS suitable for Simple
coil connection. The oscillator IS voltagecontrolled and has little distortion or spunous
radiation. It is specially SUitable for electronic
tuning using variable capacitance diodes.
Band switching diodes can easily be apphed
using the stabilized voltage V11 _ 16. An extra

..
HD~

buffered OSCillator output (Pin 10) IS available
for driving a synthesizer. If this is not needed.
resistor RL(10) can be omitted.

Gain-Controlled IF Amplifier
ThiS amphfler compnses two cascaded, variable-gain differential amplifier stages coupled
by a band-pass filter. Both stages are gaincontrolled by the AGC negative feedback
network.

Detector
The full-wave, balanced envelope detector
has very low distortion over a wide dynamiC
range. Residual IF carrier IS blocked from the
Signal path by an internal low-pass filter.

AF Preamplifier
This stage preamplifies the audiO frequency
output signal. The amplifier output has an
emitter-follower with a senes resistor which,
together with an external capacitor, yields the
reqUired low-pass for AF filtenng.

AGC Amplifier
The AGC amphfier prOVides a control voltage
which is proportional to the carner amplitude.
Second-order filtenng of the AGC voltage

achieves signals with very little distortion,
even at low audio frequencies. This method
of filtering also gives fast AGC settling time
which is advantageous for electronic search
tuning. The AGC settling time can be further
reduced by using capacitors of smaller value
in the external filter (C16 and C17). The AGC
voltage is fed to the RF and IF stages via
suitable AGC delays. The capacitor at Pin 7
can be omitted for low-cost applications.

Field Strength Indicator Output
A buffered voltage source provides a highlevel field strength output Signal which has
good linearity for logarithmic input signals
over the whole dynamiC range. If the field
strength information is not needed, RL(9) can
be omitted.

Standby Switch
This switch IS pnmarily intended for AM/FM
band switching. During standby mode the
OSCillator, mixer, and AF preamplifier are
switched off.

Short-Circuit Protection
All pins have short-circuit protection to
ground.

~~F

27MHz12pF(t)

I

u,.,H;.-,

-4:-

~~

V

II

S+N
N

~Iz'"

V
V

In

1-1-,....

12

16

-80

1\

V

V

I

V
V

22

~

11

..

S!N

THD

N

o
o

t"'-"""

20

40

eo

10

100

0
120

V, (cIB.Vl

TC12951S

NOTES:
1 Capacrtor values depend on crystal type
2 Cod Data 9 Windings of 0 1mm diS laminated Cu
Wire on TOKO coli set 7K 199CN, 00'" 80

Figure 1. OSCillator Circuit Using
Quartz Crystal; Center
Frequency = 27MHz

November 14, 1986

Figure 2. AF Output as a Function of
RF Input In the Test Circuit;
fl 1MHz; fM 400Hz; m 30%

=

=

7-8

=

Figure 3. Total Harmonic Distortion
and (S + N)/N as Functions of
RF Input in the Test Circuit;
m 30% for (S + N)/N Curve
and m = 80% for THD Curve

=

Product Specification

Signetics linear Products

AM Receiver Circuit

TDA1072A

10

C7_18 = 2.2,..F

............. ~16=O"F

'\.

'-""
0.1

10

20

100

200

1000

2000

Figure 4. Total Harmonic Distortion as a Funcllon of Modulation Frequency at V,
Circuit With C7 _ 16(EXT) = OIlF and 2.21lF

=5mV; m =80%; Measured in the Test

/

I
/

1/

V

1/
o
o

20

40

60

60

100

120

V,(dB"V)

NOTES:
WIth IF fIlter
WIth AF filter
WIth IF and AF filters

Figure 5. Indicator Driver Voltage as a Function of
RF Input in the Test Circuit

November 14, 1986

Figure 6. Typical Frequency Response Curves From Test
Circuits Showing the Effect of Filtering

7-9

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

Figure 7. Car Radio Application With Inductive Tuning

S+N(m=30%)

~

....

i-'

....
80
N

o

20

80

40

120

100

Figure 8. AF Output as a Function of RF Input Using the Circuit of Figure 7 With That of the Test Circuit

40

106

120

v

80

o

10

20

30

40

50

80

68

70

NOTES:
1 Wanted signal CtI'AEW. VRFW} fl=1MHz, fM = 400Hz, m=30%
2 Unwanted Signal (V' AEU. VRFU 11 - 900kHz, 1M - 400Hz, m - 30%
3 Effecttve selectIVity of mput tuned CIrculi == 21dB
4 Curve

IS

for wanted Vo(AF)/unwanted Vo(AF) "" 20dB VRFW, VRFU are Signals at the aenal mput, V'AEW. V'AEU are signals at the unloaded output of the aenal

Figure 9. Suppression of Cross-Modulation as a Function of Input Signal, Measured In the Circuit of Figure 7
With the Input Circuit as Shown in Figure 11

November 14, 1986

7-10

Signetics Linear Products

Product Specification

TDA1072A

AM Receiver Circuit

tv~~

r---,

POWER
SPLITTER

VRFW
VRFU

....

AERIAL

I
I

II

50

Iv~

Iv

AEU
10 RADIO
"----INPUTCIRCUIT
(FIG. 7)

I
I
IL___ .JI

t vu _ .
TC12970S

Figure 10. Input Circuit to Show Cross·Modulation Suppression (see Figure 9)

120 r--

r-

Ll

1110
80

S

\

10

!i
zi+z

S
110
IS

.J

4D

;'

1\

'"

4D

N

8

...

'"

1\
~

20

I

2

THD

o

0
0.1

100 20D

Figure 11. Oscillator Amplitude as a
Function of Pins 11, 12 Impedance
In the Circuit of Figure 7

o

40

10

1110

o

120

Figure 12. Total Harmonic Distortion and (S + N)/N as Functions of RF Input
Using the Circuit of Figure 7 With That of Test Circuit

•
November 14, 1986

7·11

Product Specification

Signetics Linear Products

TDA1072A

AM Receiver Circuit

----------------~--~-----------------------,

~

.....

_~W'U,2~~~~~~~llll~~~~~~~~~~~~u.N~~
-100

-10

-1

±O.1

10

100

!J.'IF(kHz)

Figure 13. Forward Transfer Impedance as a Function of Intermediate Frequency for Filters 1 to 4 Shown in Figure 14,
Center Frequency 455kHz

=

Table 1. Data for IF Filters Shown in Figure 14
FILTER NO.

1

2

Coil data

L1

Ll

Ll

L2

L1

Value of C
Nl: N2
DIameter of Cu
laminated wire

3900
12:32

430
13:(33 + 66)

3900
15.31

4700
29:29

3900
13:31

pF

0.09
65 (typ.)

0.08
50

0.09
75

0.08
60

0.09
75

mm

00
Schematlc 1
of
windings
Toko order no.

•12
•

•

.32

•

•13
•

3

• 66 •15
•

33

7XNS - A7523DY

L7PES - A0060BTG

SFZ455A
4
3
4.2
24

SFZ455A
4
3
4.2
24

4.8
57
0.70
3.6
35
52
63

3.8
40
0.67
3.8
31
49
58

•

•

•
•(Nl)

.31

29

•

7XNS-A7518DY

UNIT

4

• 29 •13
•
•
(N2)
•

7XNS-A7521AIH

•

.31

•

7XNS-A7519DY

Resonators
Murata Type
D (tYPical value)
RG, RL
Bandwidth (- 3d B)
S9kHz

SFT455B
6
3
4.5
38

SFZ455A
4
3
4.2
24

dB
k!2
kHz
dB

Filter data
Z,
Os
ZF
Bandwidth (- 3d B)
S9kHz
S,8kHz
S27kHz

4.2
18(L2)

52(Ll)
0.68
3.6
36
54
66

4.8
55
0.68
4.0
42
64
74

NOTE:
The beginning of an arrow Indicates the beginning of a wmdlng; N1 IS always the Inner Winding, N2 the outer Winding
2 Cntenum for adjustment 15 ZF = maximum (Optimum Selectivity curve at center frequency 10 = 455kHz). See also figure 13

November 14, 1986

7-12

k!2
k!2
kHz
dB
dB
dB

Signetics Unear Products

Product Specification

AM Receiver Circuit

TDA1072A

at
Vee

It

NOTE:
For hi.... dala, refer to Table 1

Figure 14. IF Filter Variants Applied to the Test Circuit

November 14, 1986

7-13

•

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

470pF

lOOk

lOOnFJ;

lOOnF*

Uk

...F

.---....... t-olooc
,----ovIND

lOOk

*. .

12k

100

F

SfANIIIIY swm:H

NOTES:
1 Values of capaCItors depend on the selected group of capacitIVe diodes B8112
2 For IF filter and coli data refer to Block DIagram
3 The circuit Includes pre-stage AGe optimized for good large-signal handling

Figure 15. Car Radio Application With Capacitive Diode Tuning and Electronic MW/LW Switching

Novernbe' 14 191)',

7·14

SigneHcs

AN1961
Integrated AM TDA1072A
Receiver
Application Note

Linear Products

Successor to the well-known TDA 1072, the
TDA 1072A is an inexpensive integrated AM
radio circuH that performs all the active functions between the aerial and the audio power
amplifier. Its ability to handle a wide dynamic
range of inpu1 signals and its low distortion
make the TDA 1072A suHable for use In a
wide range of car radios, domestic radios,
and tuners. The TDA 1072A brings the
TDA 1072 right up-ta-date to meet present
trends in the design of the AM section of a
radio, such as varicap diode tuning, AM
stereo facilHy, and electronic search tuning.
Performance improvements include a SdB
increase in sensitivHy over most of the inpu1
signal operating range, and 55dB ripple rejection between the supply voltage and the
oscillator output.
With the TDA 1072A, designers have complete freedom of choice in tuning method,
gain and selectivity, since none of the aerial
circuit has been integrated. And the
TDA1072A Is ideal for use wHh low-cost
hybrid IF filters.
Semi-professional and professional applications outside the AM broadcast bands using
local oscillator frequencies up to SOMHz and
down to ultrasound frequencies are alse pessible.
The main features of the TDA 1072A are:
• High sensitivity: 15/J.V aerial input for
2SdB signal-to-noise ratiO, m - 0.3
• Large signal handling capability, low
distortion and high signal-to-noise ratio
• Particula~y suitable for use with varicap
diode tuning owing to a constant lowlevel output voltage (typ. 130mVRMS)
from the local oscillator
• Separate buffered local oscillator output
(320mVp_p, Pin 10) for digital frequency
synthesizers
• Internal AGC circuit with fast sellilng
time - essential in electronic search
tuning - and low distortion at low
modulation frequencies
• Logarithmic field strength output for
simple generation of stop pulses and
for dnvlng a signal strength indicator or
meter
• Internal standby switch operated by
logic levels
• Requires very few peripheral
components
• Operates from supply voltages between
7.5 and 18V
December 1988

• Ambient operating temperature: -40·C
to +80·C.

CIRCUIT AND PERFORMANCE
Figure 1 shows the block diagram of the
TDA 1072A. Although basically similar to its
predecesser, the TDA1072A offers:
• SdB Improvement In signal-to-nOise ratio
owing to redeSigned input circuitry
• 55dB improvement In ripple rejection
owing to redeSigned oscillator Circuitry
• New field strength curve optimized for
LED bar indicators and easy stop pulse
generation With selectable level.
The main differences in performance between the two circuits are given in Table 1.

RF Input
A redesigned inpu1 cirCUit gIVes a SdB improvement In signal-to-noise over most of the
operating range (see Figures 2 and 3). To
obtain the full improvement, the source impedance of the RF input circuit should be
reduced from I.Skn (TDA1072) to lkn
(f, = 1MHz), the laller value being a compromise between large signal capability (low
cross modulation) of permeability-tuned circuits and sensitivity.
In addition, thiS value allows low-impedance
electronically-tuned RF input stages with
FETs (especially those used as source-followers) to be used. Moreover, it allows a
home radio frame antenna to be connected
to the TDA1072A Without using a FET. The
antenna forms part of the RF input circuit coil,
which IS a transformer directly connected to
the RF input of the TDA1072A.
The input impedance at lMHz (Pins 14 and
15, both surge-protected) IS 5.5kn II 22pF
for an RF input < 300/J.V; 8kn II 22pF for an
Inpu1 > 10mV.
Tuning behavior of the TDA1072 and
TDA1072A is different oWing to the former's
proportional AGC and the laller's more integrating AGC. With the TDA 1072, the optimal
tuning pesition could be identified by the rapid
increase of noise with detuning. With the
TDA 1072A, the noise only Increases slowly
with detuning. ThiS is advantageous in mechanically-tuned radios since slight detuning
(due to vibration, temperature) produces only
a small increase in noise and distortion.
For optimal tuning and sensitiVity at very low
RF Input signals, a 220nF metal foil capacitor

7-15

should be connected between Pin 5 and
ground. This replaces the 470nF electrolytic
capacitor needed with the TDA 1072.

Local OSCillator
The voltage-controlled oscillator provides signals of low distortion and high spectral purity
even when tuned with varicap diodes. It
delivers an almost constant output of typically
130mV for impedances from 500n to 200kn.
Internal temperature compensation Circuitry
ensures ultra stable Signals even on short
waves. Only a few external components are
required to complete the oscillator.
An additional buffered oscillator output is
provided (Pin 10, 320mVp_p; 200mV
TDA 1072) for use in synthesizer-tuned radios.
The oscillator of the TDA1072A is DC referenced to ground (VII = 4.2V, i.e., SVSE) unlike the TDA 1072 which was DC-referenced
to the supply (VII = V13 - 1.4V). ThiS new
arrangement has improved the ripple rejection between the supply voltage and the DC
oscillator voltage by 55dB. Hence, frequency
modulation of the oscillator signal due to
supply voltage ripple is minimized.
NOTE:

There should always be a DC connectJon between Pins 11 and 12 (usually a coli or resIstor)
owing to Internal bIaSIng. For stablhty, a 100nF
capacItor should be connected between PIn 11
and ground
In order to use band-switching diodes as well
as transistors With the TDA 1072A, Pin 11 can
switch up to 20mA.

Mixer
A double-balanced mixer IS used to generate
the IF signal. The mixer output (Pin 1) is the
collector of a transistor pair which reqUires a
pesitive DC voltage. Since a resistive load
would reduce the maximum IF output signal,
an inductor should be used in the coupling
circuit to the IF amplifier.
High IF gain allows the IF selectivHy to be
prOVided by an external hybrid or ceramic
filter. Hybrid IF filters are recommended for
reasons of cost. These should have a transfer
impedance of
Z21 = V34111 = 700n,
and an input impedance between 3kn and
5kn to prevent overloading the mixer.

Application Note

Signetics Linear Products

Integrated AM IDA 1072A Receiver

AN1961

"~)itI~rIG_·"::-':-1-:~_LOC---1Ar-L_OSC-,,.LLA-m...,R

n
n ._.

Y'
-=-

100nf

IOnF

.-----1r---I1--- 'osc

1~nF

I
I

~OpF
":'" r

1oonF-t-':;,:.......-

2."

--i

....

r----1----~v~o

22

+VBo-~~t--p-~-------~----~--...,

16

27.

15

,....--

I
I
I 3 9nF
1

.

I
I
IL

__

12.

10nF

I I
33nF

~AF)

Figure 1. TDA 1072A and Test Circuit

IF Amplifier and Detector

AGe Amplifier

The IF amplifier comprises two cascaded
dIfferential amplifier stages with Independent
gain control.

This amplifier prOVIdes a control voltage proportional to the carrier amplitude. Secondorder filtenng of the AGe voltage gIves low
dIstortion over the whole range of amplitudes
(even at low modulatIon frequencIes) In addItIon to fast settling time of the AGe - essenllal when this SIgnal IS used to derive stop
pulses In electronic search tuning. The values
of the capacitors (PinS 7 and B) in the external
filter shown in FIgure 1 provide a compromise
between short settling tIme and low dIstortIon.
Both capacItors should be posItIoned close to
the Ie and should be connected to a maIn
ground to avoId coupling ground currents. In
low cost sets, the capacitor at PIn 7 can be
omitted.

The low nOIse full-wave balanced envelope
detector provides a linear low distortion output over a wide dynamIc range Residual IF
carrier is blocked from the signal path by an
internal low-pass filter.

AF Preamplifier
The emitter-follower output with an internal
senes resistor enables external low-pass filtering of the AF signal to be designed as
required.
NOTE:
In applications With fernte rod aenals, the
external capacitors should be close to the
to minimiZe IF Interference

December 1988

Ie

An B6dB AGe control range holds the level of
the AM, IF signal constant (within 1dB) over a
broad range of RF input levels. In AM stereo

7-16

systems, thIs sImplifies the matnxing of the
stereo difference signal.

Field Strength Indicator Output!
Stop Pulse Generation
A buffered De output whIch IS a logarithmic
function of aenal input voltage over the full
dynamIc range IS available for driving a field
strength indicator or for generating stop pulses in search-tuning systems (Figure 4). The
fIeld strength curve of the TDA 1072A (Figure
5) has been optimized for LED Indicator
dnvers, but can stIli be used with meters. Up
to 2mA may be drawn (Pin 9); and with an
Input of 500mV between PinS 14 and 15, the
typical field strength output IS 2.BV.
A dIode IS incorporated in the output stage so
that a common indicator can be used to
display FM and AM field strengths without the
need for a SWitch.

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

Table 1. Perfonnance of the TDA1072A and TDA1072
SYMBOL

TDA1072A

TDA1072

UNIT

VI
VI
VI
VI

Sensitivity (see also Figure 3):
RF input voltagel for
(5 + N)/N = 6dB
(S + N)/N = 26dB
(5 + N)/N = 46dB
start of AGC

1.5
15
150
30

2.2
30
550
14

jJ.V
jJ.V
jJ.V
jJ.V

VI
VI
VI

Large signal handling:
maximum RF input voltage (Pins 14 and 15)
dror = 3%, m = 0.8
dror = 3%, m = 0.3
dTOr = 10%, m = 0.3

500
700
900

600
800
1200

mV
mV
mV

dVI
dVI

AGC control range
for a 6dB change of Vo
1dB change of Vo

91
86

91

dB
dB
mV

VO(AF)
dror
fose
max.
dV11 /dV13

-III

PARAMETER

AF output voltage at VI = 1mV, fl = 1MHz, m = 0.3 and
fM = 400Hz THO of AF output voltage (see Figure 3)
VI = 500mV; m = 0.3
Oscillator frequency range
Oscillator output current
Ripple rejection
Field strength indication range

NOTES:
All values are typical and measured In the CircUit of Figure I unless otherwise speCified.
I. Vee = 8.5V (TDAI072A), 15V (TDAI072); 11-IMHz, 1M - 400Hz; m
< O.6MHz poSSible.

= 0 3.

2. Operabon at

December 1988

7-17

310

300

1% (m = 0.3)

1.8% (m = 0.8)

0.6-602
20
55
114

0.6-60
15
0
114

MHz
mA
dB
dB

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

56

AN1961

15pF

t
~100nF

12

11

TOA1072A

(FIG.')

-,

r---I

SFZ460A

I

I
I

I

430pF

I

I
I

IL___ _

I

I
I
I
I
I

I
I
_________________ JI
IF ALTER

Figure 2. Aerial Local Oscillator Circuits for a Permeability-Tuned Medium-Wave Car Radio Whose Performance is
Shown in Figure 3

December 1988

7-18

Application Note

Signetics Linear Products

AN1961

Integrated AM TDA1072A Receiver

Internal Supply Voltage
An Internal hum filter is completed by connecting a 471lF electrolytic capacitor to Pin
13. The connections from the capacitor to Pin
13 and to the IF filter should be short.

APPLICATIONS

,..,

-30

,;>

-40

:!!.

Existing designs uSing the TDA 1072 can
usually be upgraded using the TDA 1072A.
However, some circuits may have to be
modified owing to different DC levels (Table
2) and the new field strength curve.

-50
-60
-70

Figures 6 to 11 give an indication of the
applications possible with the TDA1072A.

Table 2_ Difference in DC
VOltages Between the TDA 1072A
and TDA 1072, Supply B.5V
PIN

TDA1072A

TDA1072

10

10.7
4.2
4.2

4.5
7.2
2.7

11
14

& 12
& 15

-----

-10
-20

,

\

\

l

Q

~

I

\ TDA1072

3

VI
\

\

NOTE:

All other voltages remain unaltered

NOTE:
fM = 400Hz, Vee = 8 5V

Figure 3. Perlormance of the AM Section of the Car Radio Circuitry
Shown In Figure 2

Vee

R2

R1

STOP-PULSE
OUTPUT

TOA1072A

"---11

FIEUl-STRENGTH

INDICATOR
OUTPUT

Figure 4. Simple Stop Pulse Generation Circuit

December 1988

7-19

•

Signetlcs Linear Products

Application Note

AN1961

Integrated AM TDA1072A Receiver

---

TDA1072

..... ."".,'"

",-

I

/

OPI153OS

NOTE:
f,-1MHz. fM -0, m -0, Vcc'" R.SV.

Figure 5. Field Strength Indication Voltage Characteriatlc for the
Circuit of Figure 3

,\7
3.3pF
II

Q= 70

l ~'TO

(.

640"H

';~39pF
I

~~ , ~

SOpF

l

I'
S1TO
640~H

---

'-_-I-_L

';
90pF

Q=~

Q=/:

_J'[

84"H

,?

I-

l180pF/ ;

390pF

~

I

rt

~3ATO

5SOpF

~ lGOnF

~

"::"

15

SOpF

14

12

100nF

11

TDAI072A
(FIG. I)

NOTE:
Permeabollty tUning COil. Hopi VM 8C2.4.2A.

Figure 6. Aerial and Local OsCillator Circuita for a Permeability·Tuned Car Radio With Input Band·Paas Filter

December 1988

7·20

Signetics Linear Products

Application Note

Integrated AM IDA 1072A Receiver

AN1961

2.4k

I

TOKO 7P-7BR
560 H

"

179p.H

---r-.. . . ..----,

r-..;;0_=..;;8;;..5

22pF

Cl: IOpF TO 510pF
C2: 12pF TO 442pF
15

14

22

12

11

TDA1072A
(AG.l)

Figure 7. Aerial and Local Oscillator Circuits for a Varlable-Capacitor Tuned Medium-Wave Domestic Radio

•
December 1988

7-21

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

VB ________~H~--1_----~~v~~~=-=•.5~V------------------------------_t----1r----r_----------------__,

v~~-------------+------+---------------~----,

o

47J.tF

T

1.2'

3.lnF

'00

16

'00

Tn.
2.2",F

SF24t1OA

'OOk

,.

TOA1072A

O.47p;F

+5V----'lNY.,
iiW =LW ------~......JVI/V-tt:..

*'ODnF

J

'.n

'ose

VINO

STANDBY
SWITCH

NOTE:
The diode-tuned RF preamphfler provides large signal handling capability. For strong aenal signals, TAl loads the antenna, keeping the gate voltage of the BF410D and the
AC voltage across the vancap diodes low (130mV for RF mput signals exceeding 5V). The slope of the AGe IS set by Ra and the onset of gam control by Rb. Because the
AF gam control IS denved from the output of the tuned AF preamplifier, there IS no masking of deSired weak Signals situated close to strong ones.

Figure 8. A Varlcap Diode-Tuned Long-/Medium-Wave Car Radio With AGC for Large Signal Handling Capability

December 1988

7-22

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

TUNING VOLTAGE

O.5VTO BV

10k

lOOk
(SEE INSET)

lnF

L2

L3

751

9t

22
pF

Q= 130

511

l00nF

100nF

+

22

390

22

BF245B

Ll, L2, L3:
TOKO lOSE 161 XN

l00nF
15

14

12

11
TOKO IOEZ·RBR

.--t--..,

TOA1072A

(FIG. 1)

22
TO

TO

PIN 12

PIN 11

INSET
NOTE:
For high Q and aanal decouphng, a BF245B FET IS used

Figure 9. Aerial and Local Oscillator Circuits for a Varicap Diode-Tuned Medium-Wave Domestic Radio

December 1988

7-23

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

BBl12

ULTRASOUND
INPUT

hb

22
12

14

11

TDA1072A
(FIG. 1)

------,

,..---

I
I

I

10nF

I

I
I
I

I

I

I
110nF

I

I

I

I
I

I

_ _ _ _ _ _ _ _ _ _ _ _ ..J

I

'--Vee (PIN 13)

NOTE,
The IF filter IS tuned to 60kHz The Ie oscIllator IS tuned by a varlcap diode to between 25 and 35kHz.

Figure 10. Receiver for 25kHz to 35kHz Transmissions Such as Those Used In Doppler Rangefinders

December 1988

7-24

Signetlcs Linear Products

Application Note

Integrated AM TDA 1072A Receiver

AN1961

26.5MHz

D~'2PF'

470pF

220

TDA1072A
(FIG 1)

--,

r---

I

I
I
I
II 3.9nF
I
I

I
I
IL __ _

I
I
I
I

27k

I
l00nF
IF FILTER

I-

I
I

I
I

-----------------~

Vee (PIN 13)

NOTE:
A crystal OSCillator IS used so that a narrow-band hybnd IF filter can be used

Figure 11. Aerial and Local Oscillator Circuits for a 27M Hz Receiver for Remote lor Remote Control of Garage Doors,
Projectors, Curtains, etc.

REFERENCES
1.

"Integrated AM Radio TDA 1072," Philips
Eleoma Technical Note 148, ordenng
code 9398 014 80011.

2.

JANSEN, W. and KANOW, W., "AM Ste·
reo - A New Dimension for Car Radios,"
Eleetrome Components and Applications,
Vol. 3, No 4, Aug. 1981, also available as
an offpnnt· Philips Elcoma Technical Pub·
licatlon 034, ordenng code 9398 020
40011,

3.

BAHNSEN, B.P. and GARSKAMP, A.,
"Integrated Circuits for Car RadiOS,"

December 1988

Eleetrome Components and Applications,
Vol. 3, No 2, Feb. 1981, also available as
an offprmt. Philips Elcoma Technical Pub·
lication 002, ordenng code 9398 017
00011.

4.

KANOW, W. and SIEWERT, I., "Integrat·
ed CIrcuIts for HI·FI RadIOS and Tuners,"
Electronic Components and Applications,
Vol. 4, No.1, Nov. 1981, also avaIlable as
an offpnnt: PhIlips Elcoma Technical Pub·
licatlon 040, ordenng code 9398 021
10011.

7-25

5.

6.

"Single vanable capacItance dIode for
AM Car RadIOS," Eleetrome Components
and ApplicatIOns, Vol. 4, No.4, Aug.
1982, also avaIlable as an offpnnt: Philips
Elcoma TechnIcal PublicatIon 076, ordermg code 9398 038 20011.
BAHNSEN, B.P., "Voltage-controlled tunIng of AM radIOS," Eleetrome Components and Applications, Vol. 2, No.2,
Feb. 1980.

Previously published as Technical PublicatIon
152, Eleoma, February 5, 1985, The Netherlands

•

TEA5570

Signetics

AMjFM Radio Receiver Circuit
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TEA5570 is a monolithic integrated
radio circuit for use in portable receivers
and clock radios. The IC is also applicable to mains-fed AM and AM/FM receivers and car radio-receivers. Apart from
the AM/FM switch function, the IC incorporates for AM a double-balanced mixer,
'one-pin' oscillator, IF amplifier with AGe
and detector, and a level detector for
tuning indication. The FM circuitry comprises IF stages with a symmetrical limiter for a ratio detector. A level detector
for mono/stereo switch information and/
or indication completes the FM part.

• Simple DC switching for AM to
FM by only one DC contact to
ground (no switch contacts In
the IF channel, AF or level
detector outputs)
• AM and FM gain control
• Low current consumption

PIN CONFIGURATION

(ITOT= 6mA)

• Low voltage operation (Vee = 2.7
to 9V)
• Ability to handle large AM
signals; good IF suppression
• Applicable for inductive,
capacitive and diode tuning
• Double smoothing of AGC line
• Short-wave range up to 30MHz
• Lumped or distributed IF
selectivity with coil and/or
ceramic filters

N Package
INPUTFMIF 1
INPUT AM

AMDETOUT

4~:W":'F

OSCADJ.
MIXEROUT 4

1

OUTFMIF 5
INPUT
AM/FMIF

:t:."ll!..IF
LEVEL DErECIOR

1 AGe
10 ~MITER

• ::UMITER
-..._ _...slllPVlEW

• AM and AGC output voltage
control
• Distribution of PCB wiring
provides good frequency stability
• Economic design for •AM only'
receivers

BLOCK DIAGRAM

14

vl~~.L--_r;:;-l
OSC'L-O.:3t-_ _
LAlOR

INDICA10RI

1-6-_-+=12:.o~R

j--L':::'J

OUTPUT

ADJUST

_o-

S4
--n---I",15;.a DETEClllR

OUTPUTlVoI

16

November 14, 1986

7-26

853-0984 86551

I.'

Product Specification

Signetics Linear Products

TEA5570

AM/FM Radio Receiver Circuit

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

TEA5570N

16-Pin Plastic DIP

ABSOLUTE MAXIMUM RATINGS
RATING

UNITS

Vec= V7-16

SYMBOL

Supply voltage (Pin 7)

PARAMETER

12

V

Vn-16

Voltage at PinS 4, 5, 9, and 10 to Pin
16 (ground)

12

V

VS-16

Voltage range at Pin 8

15

Current into Pin 5

Vec± 0.5

V

3

mA

PTOT

Total power diSSipation

see Figure 1

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range

-30 to +85

°C

DC ELECTRICAL CHARACTERISTICS

Vee = 6V, TA = 25°C, measured

In

Figure 9, unless otherwise specified.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

2.4

5.4

9.0

Supply (Pin 7)
Vee = V7-16

Supply voltage

V

Voltages
V1-16
V1- 16
V2,3 -16
V6-16
V11 - 16
V13-16
V14 - 16

at
at
at
at
at
at
at

1.42
1.28
1.42
0.7
1.4
0.7
4.3

Pin 1 (FM)
Pin 1; -11 = 50IJ.A (FM)
Pins 2 and 3 (AM)
Pin 6
Pin 11
Pin 13
Pin 14

V
V
V
V
V
V
V

Currents
17

Supply current

8.2

mA

-11

Current supplied from Pin 1 (FM)

50

IJ.A

-112

Current supplied from Pin 12

20

IJ.A

-115

Current supplied from Pin 15

30

IJ.A

14

Current Into Pin 4 (AM)

0.6

mA

15

Current into Pin 5 (FM)4

0.35

mA

Is

Current Into Pin 8 (AM)

0.3

mA

19,10

Current into Pins 9, 10 (FM)

0.65

mA

114

Current Into Pin 14

0.4

mA

P

Power consumptton

40

mW

November 14, 1986

4.2

7-27

6.2

•

Product Specification

Signetics Linear Products

TEA5570

AMjFM Radio Receiver Circuit

AC ELECTRICAL CHARACTERISTICS vee = 6V; TA = 25'C; RF condition: f, = 1MHz, m = 0.3, fM = 1kHz; transfer
impedance of the IF filter
otherwise specified.

lzTR 1= vs/14 = 2.7k;

measured in Figure 9, unless

LIMITS
SYMBOL

V,
V,
V,
V,

RF sensitivity (Pin 2)
at Vo=30mV
at S + N/N = 6dB
at S + N/N = 26dB
at S + N/N = 50dB

V,

Signal handling (THO

Va

AF output voltage at V,

THO

UNIT

PARAMETER

« 10%

at m = 0.8)

IF suppression at Va

VB-'S

OSCillator voltage (Pin 8)S
at fosc = 1455kHz

1'2

Indicator current (Pin 12) at V,

Max

3.5

5.0
1.3
16
1

7.0

100

125

mV

0.5
1.0
4.0

2.5
10

%
%
%

80

= 0.3)

= 30mV2

ex

Typ

20

200

= 1mV

Total harmonic distortion
at V, = 100llV to 100mV (m
at V, = 2mV (m = 0.8)
at V, = 200mV (m = 0.8)

Min

26
120

= 1mV

p.V
IlV
IlV
mV
mV

dB

35
160

200

mV

200

230

JJA

AC ELECTRICAL CHARACTERISTICS Vee = 6V; TA = 25'C; IF condition: I, = 10.7MHz, l>.f = ± 22.5kHz, fM = 1kHz; transfer
impedance of the IF filter
otherwise specified.

lzTRI = v6/ls = 275n;

measured in Figure 9, unless

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

90

110
6
1

130

IlV
IlV
mV

80

100

125

mV

IF part

V,
V,
V,

IF sensitivity (adjustable)4
Input voltage
at -3dB before limiting
at S + NIN = 26dB
at S + NIN = 65dB

= 1mV

Va

AF output voltage at V,

THO

Total harmonic distortion at V,

AMS

AM suppressions

= 1mV

0.3

%

50

dB

Indicator/level detector (Pin 12)

1,2

Indicator current

250

V'2-'6
V,2-'6

OC output voltage
at V, = 300llV
at V, =2mV

0.25
1.0

325

JJA
V
V

AM to FM switch

-Is

Switching current at Vs -1S

NOTES:
1. Osclliator operates at V7-16 > 2.25V
2. IF suppression IS defined as the ratio



In

Test Circuit Figure 9

Figure 5. Signal, NOise, and Distortion as a Function of
Input Voltage (V,)

1.5

300

...... .....

~'\
f-

-- "--~

-2

or
~

-

\
"\

-4

\.

-6
20

40

TA(OC)

NOTES,
- - - Sensitivity at -3dB hmltlng
- - - - Output voltage (Vo) at VI = 1mV,
.df = ± 22kHz
Measured at 11 = 10 7MHz In Test Circuit FIgure 9

Figure 6. Sensitivity (V,) Output
Voltage (Vo) as a Function of
Temperature Behavior (TA)

November 14, 1986

/

I

'/

V

o
o
2

/

L

100

-20
60

II

-8

-16

60

j

AM
200

-12

'\
-20

......

-4

1"\

IFM

V

20

60

1.0

0.5

o

60

4
Vcc(V)

NOTES,
- - - SensitIVIty at -3dB limiting Vee =: BV
applicatIOn
•••••••••• Sensitivity at -3dB IImltrng Vee"" 4 5V
application
- - - - Output voltage (Vo) at VI"" 1mV •
.6.f =: ± 225kHz
(Vo) as a function of supply voltage (Vee)
Measured at f,,,,, 10 7MHz In Test Circuit Figure 9

Figure 7. Sensitivity (V,) and
Output Voltage

7-30

NOTES,
AM fl "" 1MHz. (VI) Measured In
Figure 9. Vee = 6V, R12_16=5k

Figure 8. Indicator Output Current
(112) and DC Output Voltage (V12-16)

Signetics Uneer Products

Product Specification

TEA5570

AM/FM Radio Receiver Circuit

~

M

100

88

~------~--~~---'r-------------~=-------------~--~--~~~~~-o~~
56pF

1

M

~

2.7k

1DnF

RS

880

C6

22nF

AM INPUT

14

vp
13

7
R9
18k

R10
18k

TEA5570

R,
Uk
INDlCAlOR

NOTES:
Data
transfer Impedance of the IF filter IS

eoll
The
AM
FM

IZTRIBV./~=27kn (SFZ 455A)

IzTRI =V./'5 = 275n (SFE 107 MS)
See also Figures 10, 11, 12, and 13

Figure 9. Test Circuit

AM IF Coils (Figure 9)

FM IF Coils (Figure 9)

NOTES:
NOTES:

NOTES:

N1 = 73
N2 - 73
N3
9
C16 - 180pF (,nternal)
Wire - 0 07mm daa
TOKO aample no 7 MC-7P

N1 =90

=

Figure 10. IF Bandpa88 Filter (L1)

November 14, 1986

N1

N2- 7
Wire - 0 07mm diS
TOKa sample no 7 BR-7P

Figure 11. Oscillator Coli (L2)

7-31

-

5

N2 = 5
N3 = 4
C19 - 82pF (Internal)

Wire ""0 1mm dla
TOKO sample no 119 AN-7P

Figure 12. Primary Ratio Detector
Coil (LS)

•

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

NOTES:
N1 = 2
N2 ~ 6
N3 ~ 6
C20 "" 68pF (mternal)
Wire = 0 1mm dla
TOKO sample no 119 AN-7P

Figure 13. Secondary Ratio Detector
Coli (L4)

APPLICATION INFORMATION FIgures 14 and 16 show the cIrcuIt diagrams for the apphcanon of 6V AM MW/LW, and 4.5V
AM/FM channels, respectively, uSIng the TEA5570. FIgure 15 shows the circuitry for the
TEA5570.
A2
68

~--~-------------------.----~------~~~~-o~~
C5

rtQr~
-=-

":'"

R7
2.7k

"':'"

15

R3
5k

C10

r.enF
TEA5570

"::"

12
C3

*22nF

C4

I

~ ~~-w• I .

"::"

"::"

I

L_-= __________________________ ...1

I

R4
Uk

16

,_ -"'----------"" 'II
_

I

"::"

Yo

Coil Data
L3

L4

L5

N1

~

N2
N3
C
N1
N2
C

=

N1

-

N2

-

73
73
9

= 180pF

- 146
9
~

180pF

90
6

Figure 14. Typical Application Circuit for 6V AM MW/LW Reception Using the TEA5570

November 14, 1986

7-32

DETEClOR

OUTPUT

Signetics Linear Products

Product Specification

TEA5570

AM/FM Radio Receiver Circuit

-0
';;i'Fii
IF
1

V

"I
......

-

I~ X

?-~

"':

-:"

2

IF

a.

V

~~

~

~

~"

-

-

-

r

5.6k

"::"

FM
LIMITER

'I'.

I

OSCILLATOR

SWITCHING
CIRCUIT

.. I. . .

.
"::"

5.1k

DETECTOR

-53

~~FIER

DETECTOR

~

-54

F"::"

...

~

1111111

I
~

I,

+++ +

DECOUPLING LINE

f

Jr
I

CURRENT
SfABlUZER
ClRCWT

5.1k

~

V cq
AMPLIFIER
AMHF

>-

I,

52{
"::"

IJ

15

53!
54

12

AGCAMPS

v

...

TEA5570

"::"

8

*6

Figure 15, TEA5570 Circuit Diagram

November 14, 1986

f-.t"

1-

,

I

3

r"AiiiFM

AM

~

I

7

I.

1;j'f'

Uk

MIXER

2.2k

:{

~.

11

10

9

13

14

6

4

5

7-33

•

Product Specification

Signetics Linear Products

TEA5570

AMjFM Radio Receiver Circuit

M

~

M

~

~~~-----------t----~~------~--------~~~------------~-t~--~~-----o~5~

R1

10k
N1

R8
10k

R1
410k

AFC
(tOFU
FRONl'END)

14

FMFRONT-END

13

15

TEAS510

12
16

,
I

: ____________________
L

COIl Data
L2 N1
N2
N3

C
L3

N1
N2
N3

C
L4
L5

L6

N1
N2
N1
N2
N3
N1
N2
N3
N4

C

I
~

L-~~~__J

3
8
1
82pF
33
= 113
9
= 180pF
90
6
33
= 113
9
50
50
= 45
= 65
82pF
~

~

~

~

~

~

~

~

Figure 16. Typical Application Circuit for 4.5V AM/FM Reception Using the TEA5570 With Coils and
Single-tuned Ratio Detector (With Silicon Diodes)

November 14, 1986

7-34

TDA1001B

Signetics

Interference Suppressor
Product Specification

Linear Products
DESCRIPTION
The TDA 1001 B is a monolithic integrated circuit for suppressing interference
and noise in FM mono and stereo receivers.

FEATURES
• Active low-pass and high-pass
filters
• Interference pulse detector with
adjustable and controllable
response sensitivity

• Noise detector designed for FM
IF amplifiers with ratio detectors
or quadrature detectors
• Schmitt trigger for generating an
interference suppression pulse
• Active pilot tone generation
(19kHz)
• Internal voltage stabilization

APPLICATIONS
• FM mono and stereo receivers
• Noise suppression

PIN CONFIGURATION
N, D Packages
INPUT

GROUND

1

BUF~5~ 2

HIGH PASS
ALTER IN
HIGH PASS

LOW PASS
AMP IN

FILTER OUT

LOW PASS

THRESHOLD

AMP OUT
SURCOMP

5

AF OUTPUT

6

11 THRESHOLD
10 ~Wf PULSE

PILOT
TONE IN

TONG'Jsm: _8....._ _ _ _ _TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic DIP (SOT-38)

o to

70°C

TDA1001BN

16-Pin Plastic SO
(SO-16; SOT-109A)

o to

70°C

TDA1001BTD

BLOCK DIAGRAM

.,0-1 i-+..-1H-I

AFOUTPUT

April 25. 1988

7-35

853-0962 93043

Signetics Linear Products

Product Specification

TDA1001B

Interference Suppressor

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc

Supply Yoltage (Pin 9)

Y'N

Input yoltage (Pin 1)

Vec

V

lOUT
-lOUT

Output current (Pin 6)

1
15

mA
mA

Po

Total power dissipation

18

V

see derating
curves Figure 3

TSTG

Storage temperature range

TA

Operating ambient temperature range

-65 to +150

°C

-30 to +80

°C

DC ELECTRICAL CHARACTERISTICS Vce = 12V; TA = 25°C, unless otherwise specified
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Input stage
IZ,l1

Input Impedance (Pin 1) f = 40kHz

45

R'l

Input resistance (Pin 1) with pin 2 not connected

600

1'1

Input bias current (Pin 1) Vl_16=4.BV

R02

Output resistance (Pin 2)
unloaded

low-ohmic

R2- 16

Internal emitter resistance

5.6

6

kn
kn
15

pA

kn

Low-pass amplifier
R'3

Input resistance (Pin 3)

1,3

Input bias current (Pin 3)

7

pA

R04

Output resistance (Pin 4)

5

n

Ay

Voltage gain (V41V3)

10

Mn

1.1

V

Suppression pulse stage
loss

Input offset current at Pin 5 during the suppression time ts

50

200

nA

Output stage
R06

Output resistance (Pin 6)

R6-16

Internal emitter resistance

low-ohmic
6

kn

G,S/6

Current gain (15116)

85

dB

Pilot tone generation (19kHz)
IZlsl

Input impedance (Pin 8)

IZ071

Output Impedance (Pin 7) Pin 8 open

150

107

Output bias current (Pin 7)

0.7

G'7IS

Current gain (l7/Is)

1

n
kn

1

1.3

3

mA
mA

High-pass amplifier
R,1S

Input resistance (Pin 15)

ISIAS15

Input bias current (Pin 15)

7

pA

R014

Output resistance (Pin 14)

5

n

AY14/15

Voltage gain (V14I1S)

April 25, 1988

10

Mn

14

7-36

V

Product Specification

Signetics Unear Products

TDA1001B

Interference Suppressor

DC ELECTRICAL CHARACTERISTICS (Continued) Vcc = 12V; TA = 25°C, unless otherwise specified.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

1.5

2.0

2.5

AGe ampll'ler; Interference and noise detectors
kn

R13-14

Internal resistance (Pins 13 and 14)

±VI41n' m
±V14n m

Operational threshold voltage (uncontrolled); peak value (Pin 14)
of the interference pulse detector
of the noise detector

VI I-16M

Output voltage (peak value; Pin 11)

5.2

5.8

6.4

V

112M

Output control current (Pin 12) (peak value)

150

200

250

pA

1012

Output bias current (Pin 12)

2.5

6

pA

V12 -9
or:

Input threshold voltage for onset of control (Pm 12)
(VI(tr)O + 3dB)

360

425
0.86VBE

500

mV
mV

mV
mV

15
6.5

Suppression pulse generation (Schmitt trigger)
VII _ 16
VII _ 16

Switching threshold (Pin 11)
1: gate disabled
2: gate enabled

3.2
2.0
1.2

aVI I_ 16

Switching hysteresIs

10SII

Input offset current (Pin 11)

10lOM

Output current (Pin 10) gate disabled; peak value

IRIO

Reverse output current (Pin 10)

VI O- 16

SenSitIVity (Pin 10)

0.6

1

V
V
V
100

nA

1.4

mA

2

pA

2.5

V

APPLICATION INFORMATION Vcc=12V; TA=25°C; f=1kHz, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Vcc

Supply voltage range (Pin 9)

7.5

12

16

V

Icc

Quiescent supply current (Pin 9)

10

14

18

mA

Signal path
4.5

VI -16

DC input voltage (Pin 1)

IZItI

Input Impedance (Pin 1); f = 40kHz

35

V6- 16

DC output voltage (Pin 6)

2.4

R06

Output resistance (Pin 6)

Ay6/1

Voltage gain

f(_3dB)

- 3dB point of low-pass filter

VI(P.P)

Sensitivity for THD

V6_16(P.P)

Residual Interference pulse after suppression (see Figure 4);
Pin 7 to ground; VI(TR)M = 100mV; (peak-ta-peak value)

"',nt

Interference suppression at R13 = 0;5. 6 VI(RMS) = 30mV;
f = 19kHz (sine wave); VI(TR)M = 60mV; fr = 400Hz

April 25, 1988

2.8

V

low-ohmic

IVeNI)

< 0.5%

V
kn

0

(peak-ta-peak value)

1.2

7-37

0.5

1

kHz

1.8

V
3

20

dB

70

30

mV
dB

•

Signetlcs Linear Products

Product, Specification

Interference Suppressor

APPLICATION INFORMATION (Continued) vee =

TDA1001B

12V; TA - 25°C; f = 1kHz, unless otherwise specified.

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

8
18

11
28.5
1

14
40

Interference processing
Input signal at Pin 1; output signal at Pin 10

V'(TR)M
V'(TR)M

Suppression pulse threshold voltage; control function OFF
(Pin 9 connected to Pin 12); AMS value 1
measured with sinewave input signal
f = 120kHz; -V10-9 > 1V
at AI3=On
at A13 = 2.7kn
voltage difference for safe triggering/non-triggering (AMS
value) measured with Interference pulses
f = 400Hz (see Figure 4); peak value
at AI3=On
at A13 = 2.7kn

ts

Suppression pulse duration2

V'(TR)RMS
V'(fR)RMS
AV'(RMS)

19
45

mV
mV
mV

mV
mV

24

27

30

/.IS

2.3

3.3
8.2

4.3

mV
mV

Noise threshold feedback control 1, 3

VNI(RMS)
VNI(RMS)

NOise inPut voltage (AMS value)
f = 120kHz sinewave
for VI2_9=300mV
at AI3=On
at A13 = 2.7kn
for V12 - 9 = 425mV (V'(fR)O + 3dB)
at AI3=On
at A13 = 2.7kn
for V12 -9 = 560mV (V'(fR)O + 20dB)
at AI3=On
at A13 = 2.7kn

VOS(RMS)
V06(RMS)

Amplification control voltage by interference intensity"
V'(RMS) = 50mV; f = 19kHz;
V'(fR)M = 300mV; AMS value
at repetition frequency fR = 1kHz
at repetition frequency fR = 16kHz

VNI(RMS)
VNI(RMS)
VNI(RMS)
VNI(RMS)

7.3
16.5
33

49
45

45
107

mV
mV
57

mV
mV

56
65

mV
mV

NOTES:
1. The Interference suppression and nOise feedback control thresholds can be determined by R13 or a capscRive voltage divider at the input of the high-pass filter
and they are defined by the following formulae:
V'(TR) = (1 + RI3/Rs X V'(TR)O In which Rs = 2k!2;
VNI - (1 + R13/Rs X VNIO In which Rs = 2k!l.
2. The suppression pulse durallon os determoned by Cll = 2.2nF and Rll - 6.8k!l.
3. The characterosllcs of the noose feedback control os determined by R12 (and Rl0).
4 The feedback control of the onterfence suppreSSIon threshold at higher repetrtion frequencoes is determined by Rl0 (and RI2).
5. The 19kHz generator can be adlusted With R7_16 (and R7_8). Adjustable os not required of components with small tolerances are used, e.g.,.:!oR < 1% and
.:!o<2%.
6

MeasUring conditions.

The peak output noose voltage (VNO. CCITI folter) shall be measured at Ihe oulpul wRh a deemphaSlzing lime 1- 50jlS (R - 5kSl, C -10nF); lhe reference value
of OdS os Vo ONT woth the 19kHz generator short-circuoted (Pin 7 grounded).

April 25, 1988

7-38

Signetics Unear Products

Product Specification

TDA1001B

Interference Suppressor

1.5

1--

- ~"

~

'~ ~

0.5

'\
.~
100

50

150

NOTES:
- - - I n plastIC DIP package (TDA1001B)
- - - In plastic SO package (TDA 1001 BT), mounted on a ceramic substrate of 50 x 15 x a 7mm

Figure 1. Power Derating Curves

"V~tr) M
(mV)

SOUAAE·WAVE
INPUT VOLTAGE

SUPPRESSION
PULSE (TRIGGER)

t. = 27~s

V, Q.9
(V)

OUTPUT

I

.J

-1.5

OUTPUT
VOLTAGE

y:;~
-1
-2

OFFSET VOLTAGE
AND DRIFT

10

20

30

40

liME",")

NOTE:
At the Input (Pin 1) a square wave IS apphed with a duration of tTR = 10llS and with flse and fall times tR ;; tF = 1Dns

Figure 2. Measuring Signal for Interference Suppression

April 25, 1988

7-39

50

•

Signetics Linear Products

Product Specification

Interference Suppressor

TDA10018

HIGH-PASS FILTER

4.7pF

t ·,r

TOVce

91k

V.
(10 TO 18V)

mfl

"::"

6.8k

82

C11

22k

2.2nF

lOnF

220nF

1.Sk

Vce
RIO

13

14

TOVce

10

TDA1001B

1201<

(R~ 0-\1-.....-+----'
4.7~F

.--_ _ _- J

3.9

6.8nF

1.5k

821<

nF

T

3.9

2.2k

2.1k

nFI

Vo

":"-=
19kHz FILTER

LOW-PASS FILTER
TC12782S

Figure 3. Application Circuit Diagram

April 25, 1988

7-40

TDA7000

Signetics

Single-Chip FM Radio Circuit
Product Specification

Linear Products

FEATURES

DESCRIPTION
The TDA7000 is a monolithic integrated
circuit for mono FM portable radios
where a minimum of peripheral components is important (small dimensions
and low costs).
The IC has an FLL (Frequency-Locked
Loop) system with an intermediate frequency of 70kHz. The IF selectivity is
obtained by active RC filters. The only
function which needs tuning is the resonant circuit for the oscillator which selects the reception frequency. Spurious
reception is avoided by means of a mute
circuit, which also eliminates weak, noisy
input signals. Special precautions are
taken to meet the radiation requirements.

PIN CONFIGURATION

• RF input stage

N Package

• Mixer
• Local oscillator
• IF amplifier/limiter

18 g~:RELATOR

MUTING
CAP
AUDIO
FREQOUT
NOISE
SOURCE
lOOP
FILTER CAP

• Phase demodulator
• Mute detector
• Mute switch

APPLICATIONS

17 DEMODCAP

11TINT
CAP (TO PIN 9)
2""INT

• Mono FM Portable Radios

12 l\'A~MITER

11

CAP

• LAN

1"INT
CAP (TO PIN n

• Data Receivers

~

_ _..J 10

~LTERCAP

l\'Jl~~'N11)

TOP VIEW

• SeA Receiver

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

o to +70·C

TDA7000N

18-Pin Plastic DIP (SOT-102HE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vee
VS-5

PARAMETER

Supply voltage (Pin 5)
Oscillator voltage (Pin 6)

RATING

UNIT

12

V

Vce-0.5 to
Vcc + 0.5

V

PTOT

Total power dissipation

See derating curve Figure 1

TSTG

Storage temperature range

-55 to + 150

TA

Operating ambient temperature range

October 10, 1986

o to

+60

7-41

•

·C
·C

853-0893 85938

Product Specification

Signetics Linear Products

TDA7000

Single-Chip FM Radio Circuit

BLOCK DIAGRAM

18

17

10

11

CORRELATOR
2.7K

1.4V

IF FILTER
12K

4.7K

7

Cv

Vee
(+4.SV)
AFOUTPUT

October 10. 1986

7-42

Cs

Signetics Linear Products

Product Specification

TDA7000

Single-Chip FM Radio Circuit

DC ELECTRICAL CHARACTERISTICS

Vcc ~ 4.5V; T A ~ 25'C; measured in Figure 3, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

Vee

Supply voltage

lee

Supply current

TEST CONDITIONS
(Pin 5)
Vee

16

OSCillator current

V14 - 16

Voltage

12
V2-16

UNIT

~

Min

Typ

Max

2.7

4.5

10

4.5V

V

8

mA
I1A

(Pin 6)

280

(Pin 14)

1.35

V

Output current

(Pin 2)

60

I1A

Output voltage

(Pin 2) RL ~ 22k.l!

1.3

V

AC ELECTRICAL CHARACTERISTICS Vee ~ 4.5V; TA ~ 25'C; measured In Figure 3 (mute sWitch open, enabled);
fRF ~ 96MHz (tuned to max. signal at 511V EMF) modulated with III ~ ± 22.5kHz; 1M ~ 1kHz; EMF ~ 0 2mV (EMF voltage at a source
Impedance 01 75.1!); RMS nOise voltage measured unwelghted (I ~ 300Hz to 20kHz), unless otherwise specilled.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

-3dB limiting, muting disabled
EMF

Sensitivity (see Figure 2)
(EMF voltage)

6

~

5.5

EMF

Signal handling (EMF voltage)
Signal-to-noise ratio

THO

< 10%;
III

THO

~

AM suppression 01 output voltage

RR

Ripple relectlon

V6- 5(RMS)

OSCillator voltage (RMS value)

Illose

Vanatlon of OSCillator Irequency

S+300

III

~

± 75kHz

200

mV

60

dB

± 22.5kHz

0.7

± 75kHz

2.3

~

%

(ratio 01 the AM output Signal relerred to
the FM output Signal)
FM Signal: 1M ~ 1kHz; III ~ ± 75kHz
AM Signal: fM ~ 1kHz; m ~ 80%
(IlVee

~

100mV; I

~

1kHz)

(Pin 6)
Supply voltage (IlVee

~

1V)

50

dB

10

dB

250

mV

60

kHzlV

45
SelectiVity

dB

35

S-300
IlIRF

AFC range

BW

AudiO bandwidth

Va RMS

AF output voltage (RMS value)

RL

I1V

Total harmOniC distortion
III

AMS

26dB

Max

15

-3dB muting
SIN

SIN

Typ

IlVa ~ 3dB
measured with pre-emphasis
(t ~ 50ps)
RL

~

22k.l!

±300

kHz

10

kHz

75

mV

Vee

~

4.5V

22

Vce

~

9.0V

47

Load resistance

k.l!

NOTES:
1. The muting system can be disabled by feeding a current of about 20j.J.A Into Pin 1.
2 The Interstation nOise level can be decreased by choosing a low-value capacitor at Pin 3. Silent tunmg can be achieved by omitting this capacitor

October 10, 1986

7-43

•

Product Specification

Signetics Linear Products

TDA7000

Single-Chip FM Radio Circuit

--

1.5

!

..

c:

- 1\
---

1

05

I
I
~

\

+i

\
1\

\
-50

100

150

Figure 1. Power Derating Curve

siN

y
~

'0
>

-20

'2"-.

I
J

1

- L::-

. - -1
-40

THO

.........
-60
10- 6

NOISE

V

o
10- 5

10-- 4

10- 2

10-3
EMF (V) at Rs

10-1

1

= 75 n

NOTES,
1 The mutmg system can be disabled by feeding a current of about 20l1A IOta Pm 1
2 The Interstatton nOise level can be decreased by choosmg a low-value capacitor at Pin 3 Silent tumng can be achieved by omlttmg this capacitor

Conditions OdS'" 75mV, fAF = 96MHz
for S + N curve ilf = ± 225kHz fM = 1kHz
for THO curve df = ± 75kHz fM = 1 kHz

Figure 2. AF Output Voltage (Vo) and Total Harmonic Distortion (THO) as a Function of the EMF Input Voltage (EMF)
With a Source Impedance (Rs) of 75Q: (1) Muting System Enabled; (2) Muting System Disabled

October 10, 1986

7-44

Product Specification

Signetics Unear Products

TDA7000

Single-Chip FM Radio Circuit

220pF

3.3nF

l00nF

330pF

330pF

18

17

15 14

13 12

10

11

";:"

CORRELATOR

UK

1.4V
IF FILTER

12K

UK

UK

UK

7

8

9

3.3nF

80pF

ENABLED

DISABLED

VCCo-~~~S=wrr~CH~-i----------+---~----------~~----------------------~----------~
AFOUTPUT

Figure 3. Test Circuit

October 10, 1986

7-45

•

Signetics

AN192
A Complete FM Radio on a
Chip
Application Note

Linear Products

Authors: W.H.A. Van Dooremolen and
M. Hufschmidt
Until now, the almost total Integration of an
FM radio has been prevented by the need for
LC tuned circuits In the RF, IF, local oscillator
and demodulator stages. An obvIous way to
eliminate the coils In the IF and demodulator
stages is to reduce the normally used Intermediate frequency of 10.7MHz to a frequency
that can be tuned by active RC filters, the op
amps and resistors of which can be integrated. An IF of zero deems to be ideal because it
eliminates spurious signals such as repeat
spots and image response, but it would not
allow the IF signal to be limited prior to
demodulation, resulting In poor slgnal-tonoise ratio and no AM suppression. With an
IF of 70kHz, these problems are overcome
and the image frequency occurs about
halfway between the desired signal and the
center of the adjacent channel. However, the
IF image signal must be suppressed and, In
common with conventional FM radios, there

IS also a need to suppress Interstatlon noise
and nOise when tuned to a weak signal.
Spunous responses above and below the
center frequency of the desired station (side
tumngs), and harmonic distortion in the event
of very inaccurate tuning must also be eliminated.
We have now developed a mono FM reception system which is suitable for almost total
integration. It uses an actIVe 70kHz IF filter
and a unique correlation muting circuit for
suppressing spurious signals such as side
responses caused by the flanks of the demodulator S-curve. With such a low IF, distortion would occur with the ± 75kHz IF swing
due to received signals with maximum modulation. The maximum IF swing IS therefore
compressed to ± 15kHz by controlling the
local oscillator In a frequency-locked loop
(FLL). The combined action of the muting

circuit and the FLL also suppresses image
response.
The new circuit is the TDA7000 which Integrates a mono FM radio all the way from the
aerial input to the audio output. External to
the IC are only one tunable LC circuit for the
local oscillator, a few inexpensive ceramic
plate capacitors and one resistor. The
TDA7000 dramatically reduces assembly and
post-production alignment costs because
only the oscillator circuit needs adjustment
during manufacture to set the limits of the
tuned frequency band. The complete FM
radio can be made small enough to fit inside a
calculator, cigarette lighter, key-ring fob or
even a slim watch. The TDA7000 can also be
used as receiver in equipment such as cordless telephones, CB radios, radio-controlled
models, paging systems, the sound channel
of a TV set or other FM demodulating systems.

DF07680S

A Laboratory Model of the TDA7000 In a Complete FM Radio. Also Shown Is the TDA7010T
in the SO Package Against a CM Scale

December 1988

7-46

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

Using the TDA7000 results in significant improvements for all classes of FM radio. For
simpler portables, the small size, lack of IF
coils, easy assembly and low power consumption are not the only attractive features.
The unique correlation muting system and the
FLL make it very easy to tune, even when
using a tiny tuning knob. For higher-performance portables and clock radios, variablecapacitance diode tuning and station presetting facilities are often required. These are
easily provided with the TDA7000 because
there are no variable tuned circuits in the RF
signal path. Only the local oscillator needs to
be tuned, so tracking and distortion problems
are eliminated.

AN192

BRIEF DATA
DESCRIPTION

SYMBOL

TYP

MAX

UNIT

Typical supply voltage

4.5

V

Icc

Typical supply current

8

mA
110

fRF

RF input frequency range

VRF-3dB

sensItivity for -3dB limiting EMF
with Zs = 7M2, mute disabled

1.5

p.V

VRF

Maximum Signal input for
THD < 10%, .::if = ±75kHz
EMF wIth Zs = 75Q

200

mV

Vo

Audio output (RMS) with
RL = 22kQ, .::if = ±22.5kHz

75

mV

The TDA7000 is available in either an 18-lead
plastic DIP package (TDA7000), or in a 16-pin
SO package (TDA 701 OT). Future developments will include reducing the present supply voltage (4.5V typ.), and the introduction of
FM stereo and AM/FM versions.

December 1988

MIN

Vcc

7-47

1.5

MHz

Application Note

Signetics Unear Products

AN192

A Complete FM Radio on a Chip

Vp

'+4.5VI
C17
330 of

C15
100nF

l2121

39

C12
150pF

pF
130nH

15

r--,
I,

I.

13

12

1.4V

700n

700n

I,

12 kn

I
I

~~R~~R
2.2kO
IF

FILTER

C7
3,3 nF

Cl
1S0nF
C21

C20

56pF

d. ouUlUt

NOTES:
1 These pins are not used In the SO package versson (TDA701 aT) AP - AII·Pass filter
2 L2 IS printed on the expenmental PCB (Figure 12)
L, - Tako MC108 No 514 HNE 150013513
C20'" Toko No 2A-15BT-ROl

Figure 1. The TDA7000 as a Variable Capacitor-Tuned FM Broadcast Receiver

December 1988

7-48

C8

180pF

Application Note

Signetics Uneer Products

A Complete FM Radio on a Chip

AN192

CIRCUIT DESCRIPTION
As shown In Figure 1, the TDA7000 consists
of a local oscillator and a mixer, a two-stage
active IF filter followed by an IF limiter/
amplifier, a quadrature FM demodulator, and
an audio muting circuit controlled by an IF
waveform correlator. The conversion gain of
the mixer, together with the high gain of the IF
limiter/amplifier, provides AVC action and
effecnve suppression of AM signals. The RF
input to the TDA7000 for -3dB limillng IS
1.5I1V. In a conventional portable radio, limitIng at such a low RF Input level would cause
instability because higher harmOnics of the
clipped IF signal would be radiated to the
aerial. With the low IF used with the
TDA7000, the radiation IS negligible
To prevent distortion with the low IF used with
the TDA7000, It IS necessary to restrict the IF
deviation due to heaVily modulated RF signals to ± 15kHz. This IS achieved with a
frequency-locked loop (FLL) In which the
output from the FM demodulator shifts the
local OSCillator frequency In Inverse proporbOn to the IF deviation due to modulation

Active IF Filter
The first section of the IF filter (AF1 A) IS a
second-order low-pass Sallen-Key CirCUit with
its cut-off frequency determined by Internal
2.2k!l resistors and external capacitors C7
and Ca. The second section (AF1 B) consists
of a first-order bandpass filter with the lower
limit of the passband determined by an InternaI4.7k!l resistor and external capacitor Cll.
The upper limit of the passband IS determined
by an internal 4.7k!l resistor and external
capacitor C10. The final section of the IF filter
consists of a first-order low-pass network
comprising an Internal 12k!l resistor and
external capacitor C12. The overall IF filter
therefore consists of a fourth-order low-pass
section and a first-order high-pass section
Design equations for the filter are given In
Figure 2. Figure 3 shows the measured response for the filter.

AF1A

Sallen ~ Key fIlter

Sallen-Key CirCUit

9
ASK = 1 + JW8 _ ifb

With

=

~ ~,~B;t8

v'b_ff,

1
With fo - 211"R , ...1lC7Ca) and Q

=---;-

:=

0 5V

ta

9

ASK""1+(J~Y6)_w2

;;r,

For C7 = 3 3nF, Ca = 1BOpF. Q = 21 and fo = 94kHz

Bandpass CirCUit

1
Asp = 1

IwC,1R2

+ ,wC ,oR 2

X

1

+ ]WC,1 R 2 +

1

JwClOR2
1 + JwCl0R2

1

for 'LP "" - - and fHP = - 2:IIH2C1O
2n'R2C,1
flP

ASP=4;X (1 +1

~)(1-J

¥J+1

For G'0 = 330pF, e'l = 3 3nF, fLP = 103kHz, fHP = 103kHz

Low-Pass CirCUit

1
ALP=----

1 + JwC '2Ra
1
forfLP=--

21J'C,2R3

For

e'l =

150pF, fLP = 884kHz

Figure 2. IF Filler of Ihe TDA7000

FM Demodulator
The quadrature FM demodulator M2 converts
the IF variations due to modulation Into an
audiO frequency voltage. It has a conversion
gain of -3.6V/MHz and requires phase quadrature Inputs from the IF limiter/amplifier. As
shown In Figure 4, the 90° phase shift IS
prOVided by an active all-pass filter which has
about Unity gain at all frequencies but can
provide a variable phase Shift, dependent on
the value of external capacitor C17

December 1988

BP

7-49

LP

Signetlcs linear Products

Application Note

A Complete FM Radio on a Chip

AN192

IF Swing Compression With the
FLL
-'0

-20L-~! --..>o,.--,---.--~--~_
I!
.
I

- r-----T-----r
30'

' .

i

:.

-4°1

-50r--~------~------~---~~~.

i

;

-60~---'------,-------,-------i-----:::::"';

-70 1

o

I

'00

I
200

300

400

f (kHz)

500

Figure 3. Measured Response of the IF Filter

V,I

L-._ _ _..... to correlalOr

'7

TC213.2OS

With A,-O
~ __ 2tan-lwR,C17
for 1/) __ 90°, Cn-

1
wR;

:0

227pF

for flo ... 70kHz
To Improve the performanace of the all-pass Mer
with the amptltude-Ilmlted IF waveform. R2 has been

added.
Since thiS Influences the phase angle, the value of
e17 must be mcreased by 45%, I.e, to 330pF for
'IF -70kHz

Figure 4. FM Demoduletor Phase Shift Circuit (AII-Pa88 Filter)

December 1988

7-50

With a nominal IF as low as 70kHz, severe
harmOniC distortion of the audiO output would
occur wrth an IF deviabon of ± 75kHz due to
full modulation of a receIVed FM broadcast
signal. The FLL of the TDA7000 IS therefore
used to compress the IF swing by using the
audio output from the FM demodulator to shift
the local oscillator frequency in opposition to
the IF deViation. The prinCiple IS illustrated in
Figure 5, which shows how an IF deviation of
75kHz IS compressed to about 15kHz. The
THO is thus limited to 0.7% with ± 22.5kHz
modulation, and to 2.3% With ± 75kHz modulation.

Correlation Muting System With
Open FLL
A well-known difference between FM and AM
IS that, for FM, each stabon IS received In at
least three tuning pOSItions. Figure 6 shows
the frequency spectrum of the output from
the demodulator of a typical portable FM
radio receiving an RF carrier frequency-modulated with a tone of constant frequency and
amplitude. In addition to the audiO response
at the correct tuning point in the center of
Figure 6, there are two side responses due to
the flanks of the demodulator S-curve. Because the flanks of the S-curve are nonlinear, the side responses have Increased
harmonic distortion. In Figure 6, the frequency and intensity of the side responses are
functions of the signal strength, and they are
separated from the correct tuning pOint by
amplitude minima. However, in practice, the
amplitude minima are not well defined because the modulation frequency and index
are not constant and, moreover, the side
response of adjacent channels often overlap.
High performance FM radiOS incorporate
squelch systems such as Signal strengthdependent muting and tUning deviation-dependent mubng to suppress side responses.
They also have a tuning meter to facilitate
correct tuning. Although the TDA7000 is
mainly intended for use in portables and clock
radios, it incorporates a very effective new
correlation muting system which suppresses
interstatlon noise and spurious responses
due to detuning to the flanks of the demodulator S-curve. The muting system is controlled
by a circuit which determines the correlation
between the waveform of the IF signal and an
inverted version of it which is delayed (phaseshifted) by half the period of the nominal IF
(180°). A noise generator works in conjunction with the muting system to give an audible
indication of incorrect tuning.

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

'M

--

MIXER AND
I F AMPLIFIER

f"

DEMODULATOR

f'f

i---+-

2 = -2 tan" wR1C18 - <1>1
for2=-180'C1S=

_1_
wRl

for fil = 70 kHz. CIS = 227 pF

Figure 8. Correlator of the TDA 7000

Figure 9 shows that there are two regions
where the demodulated audio signal IS fed to
the output because the muting is inactive.
One region IS centered on the correct tuning
pOint fL. The other is centered on the Image
frequency - fL. The image response IS therefore not suppressed by the muting system
when the frequency-locked loop IS open.
When the loop IS closed, the time constant of
the muting system, which is determined by
external capacitor C1, prevents the image
response being passed to the audio output.
This is described under the next heading.

December 1988

IF

7-53

•

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

AN192

Correlation Muting System With
Closed FLL

'v
f m demodulator
output voltage - " ' - -__~---t;;--O""~--r--­
Irf-fose

local osc!lIator

control voltage

-1--,"f--- tn--\---r-:---

(a)

(b)

Irf-fose

side
tunmg

i

jv

A
ill

/
~
: ;!! V ;
'

correlator

Output voltage -~- ,

I

i

H-l

j

iii
j

ON

I

!\:L -

(-,-+"0.-'<1\7--','---====

~

iV

i

(e)

frf-fosc

i

mu" fun",on 3J~-lJ-t:---rlj--t~~~~f~"=_f=OSC=
-f,

-f2 0
i

i

audio

OutP~,;~ltage
'soft' mutll'lg

Image

I

i

OFF-----

j

~

'1

'2

I

I
!

I

~

I

correct
tuntng

(e)

fff -fose

side tuning

The closed-loop response of the FLL is
shown in Figure 10, in which the point of
origin is the nominal IF (fRF - fosc = fLl. With
correct tuning, the muting is inactive and the
audio signal is fed to the output. Spurious
responses due to the flanks of the demodulator S-curve which occur outside the IF band
-f2 to f2 are suppressed because the muting
is active. Fast transients of the audio signal
due to locking of the loop (A and B), and to
loss of lock (C and D) are suppressed in two
ways.
Lock and loss of lock transients Band D
occur when the IF IS greater than f2 and are
therefore suppressed because the muting is
active. The situation IS different dunng loss of
lock transient C because the muting is only
active for the last part of the transient. To
completely suppress thiS tranSient, capacitor
C1 in Figure 1 holds the muting control line
positive (muting active) during the short interval while the IF traverses from -f1 to -f2. The
same applies for lock transient A during the
short Interval While the IF traverses from -f2
to -f1. Since the image response occurs
halfway between -f1 and -f2' it is also suppressed.

suppres5ed

Figure 9. Operation of the Correlation Muting System With Open-Loop FLL

Figure 11 shows the audio output from the
TDA7000 radio as a function of tuned frequency with aerial signal level as a parameter. Compared with the similar diagram for a
typical conventional portable radiO (Figure 6),
there are three Important Improvements:
1. There are no side responses due to the
flanks of the demodulator S-curve. This is due
to the action of the correlation muting system
(soft mute) which combines the function of a
detuning-dependent muting system with that
of a signal strength-dependent muting system.
2. The correct tuning frequency band is wide,
even with weak aerial signals. This is due to
the AFC action of the FLL which reduces a
large vanation of aenal input frequency
(equivalent to detuning) to a small variation of
the IF. There is no audio distortion when the
radiO is slightly detuned.

I
capture

range

II
I

--~I

CJ " area of corroc! tuning
NOTE:
The slope of the correct tumng hne IS such that a 75kHz deViation of fAF causes a 15kHz deViation of fRF - fosc

Figure 10. Closed-Loop Response of the FLL

December 1988

7-54

3. Although the soft muting system remains
operative with low level aenal signals, there is
no degradation of the audio signal under
these conditions. This is due to the high gain
of the IF limiter/amplifier which provides
-3dB limiting of the IF signal With an aenal
input level of 1.5I1V. However, the soft muting
action does reduce the audio output level with
low level aerial Signals.

Application Note

Signetics Linear Products

AN192

A Complete FM Radio on a Chip

200kHZ

i-I

'·1
V,f

I
I

(

Vrf" 10mV

)
lmV

c=J
100l'V

V,f

V,f

tuned frequency

.. f OUtput

NOTE:
The modulation frequency and amplitude are both constant.

Figure 11. Audio Signal of the TDA7000 as a Function
of the Tuned Frequency With RF Input as a Parameter

OV

•
Figure 12. Experimental Printed Wiring Board for the
Circuit of Figure 1

RECEIVER CIRCUITS
Circuits With Variable Capacitor
Tuning
The circuit diagram of the complete mono FM
radio is given in Figure 1. An experimental
printed-wiring board layout is given in Figure
12. Special attention has been paid to supply
lines and the positioning of large-signal decoupling capacitors.
The functions of the peripheral components
of Figure 1 not already described are as
follows:

December 1988

C1 - Determines the time constant required
to ensure muting of audio transients due to
the operation of the FLL.
C2 - Together with R2 determines the time
constant for audio de-emphasis (e.g.,
R2C2 = 40I's).
C3 - The output level from the noise generator during muting increases with increasing
value of C3. If silent mute is required, C3 can
be omitted.
C4 - Capacitor for the FLL filter. It eliminates
IF harmonics at the output of the FM demodulator. It also determines the time constant

7-55

for locking the FLL and influences the frequency response.
C5 - Supply decoupling capaCitor which
must be connected as close as possible to
Pin 5 of the TDA7000.
C7 to Cu. C17 and C18 - Filter and demodulator capacitors. The values shown are for an
IF of 70kHz. For other intermediate frequencies, the values of these capacitors must be
changed in inverse proportion to the IF
change.
C14 - Decouples the reverse RF input. It
must be connected to the common return via

Signetics linear Products

Application Note

A Complete FM Radio on a Chip

a good quality short connection to ensure a
low-impedance path. Inductive or capacitive
coupling between C' 4 and the local oscillator
circuit or IF output components must be
avoided.

C'9 and C 21 - Local oscillator tuning capacItors. Their values depend on the reqUired
tUning range and on the value of tuning
capacitor C20.
C22. C23. L, • L2 - The values given are for
an RF bandpass filter with Q = 4 for the
European and U.S.A. domestic FM broadcast
band (87.5MHz to 108MHz). For reception of
the Japanese FM broadcast band (76MHz to

C15 - Decouples the DC feedback for IF
limiter/amplifier LA, .

P

v" ~

AN192

91 MHz), L, must be increased to 78nH and
L2 must be increased to 150nH. If stopband
attenuation for high level AM or TV signals is
not required, L2 and C22 can be omitted and
C23 changed to 220pF.
R2 - The load for the audio output current
source. It determines the audio output level,
but its value must not exceed 22kf2 for
Vce = 4.5V, or 47kf2 for Vee = 9V.

220pF , - - - - 13

750 220p' "

!r.:;
TOA7000

'----

--:"~-:7~~
-40

~~r-~"~rm-'''''r-''-''':"T0---"""'i'.",i"';ii--'-~

-60~·-

10- 6

:~ ::

'-~""'-"1Ii\,OISE~'

___

~====~==~E:~~:J::::==!:~~::==:I:!~~5:::r:lJJilW
1O- s

10 -3

10 -2

10 -1
Vrf temf)

NOTES:
The curves numbered 1 were measured wrth the muting system active The curves numbered 2 were measured With the mutIng system dIsabled by InJectmg about 20pA Into
Pm 1 of the TOA 7000 The mput frequency was 96MHz modulated With 1kHz With a deViation of ± 225kHz for the output level curves, and ± 75kHz for the dlstorbon curve

Figure 13. Audio Output as a Function of Input EMF

December 1988

7-56

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

Performance of the Circuit

SYMBOL

AN192

vee = 4.5V, TA = 25°C, fRF = 96MHz, VRF = 0.2mV EMF from a 750 source, modulated with
Ll.f = ± 22.5kHz, fM = 1kHz. Noise voltage measured unweighted over the bandwidth 300Hz to
20kHz, unless otherwise specified.
PARAMETER

TYP

MAX

UNIT

EMF
EMF
EMF

Sensitivity (EMF voltage) for - 3dB limiting:
muting disabled
for -3dB muting
for (S + N)IN = 26dB

EMF

Signal handling (EMF voltage)
for THO < 10%; Ll.f = ± 75kHz

(S + N)/N

Signal-to-noise ratio (see Figure 13)

THO
THO

Total harmonic distortion (see Figure 13)
at Ll.f = ± 22.5kHz
at Ll.f = ± 75kHz

AMS

AM suppression
(ratio 01 the AM output signal referred to the FM output signal)
FM signal: fm = 1kHz; Ll.f = ± 75kHz
AM signal: fm = 1kHz; m = 80%

50

RR

Ripple rejection (Ll.Vee = 100 mY; I

10

dB

VS-5 RMS

Oscillator voltage (RMS value) at Pin 6

250

mV

1.5
6
5.5

/lV
/lV
/lV

200

mV

60

dB

0.7
2.3

= 1kHz)

%
%

dB

Ll.fosc

Variation of oscillator frequency with supply voltage (Ll.Vee = IV)

60

kHzlV

5+300
S-3oo

Selectivity

45
35

dB
dB

Ll.IRF

AFC range

±300

kHz

B

Audio bandwidth at Ll.Vo = 3dB measured with pre-emphasis (t = 501lS)

10

kHz

VO(RMS)

AF output voltage (RMS value) at RL = 22kn

75

mV

RL
RL

Load resistance lor audio output current source
at Vee = 4.5V
at Vee = 9.0V

22
47

kn
kn

•
December 1988

7-57

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

AN192

vp
14.5V)

pm

5

BZX79-

100kn

820

3VO

5,6kll

10 nF

Vtune

TDA7000
56 nH

lOOkn

BeSSe

300kn

(fig 1)

(log)

pin 6

1,5kn

OV

pin 16

Figure 14. Variable-Capacitance Diode Tuning for the Local Oscillator. Additional
Measures Must be Taken to Ensure Temperature Stability

Circuit With Variable-Capacitance
Diode Tuning
Since It IS only necessary to tune the local
oscillator cOil, it IS very simple to modify the
circUit of Figure 1 for variable-capacitance
diode tuning. The modlficallons are shown in
Figure 14. A circuit board layout for the
modified receiver and a photograph of a
complete laboratory model are shown in Figure 15.

Narrow-Band FM Receiver
The TDA7000 can also be used for reception
of narrowband FM signals. In thiS case, the
local oscillator IS crystal-controlled (as shown
In Figure 16) and there IS therefore hardly any
compression of the IF sWing by the FLL. The
deViation of the transmitted carner frequency
due to modulation must therefore be limited
to prevent severe distortion of the demodulated au<1'o signal.

af Output

ov

L2

NOTE:
ThiS IS the same PC Board as shown In Figure 12

Figure 15. Circuit Board Layout and Complete Model of a TDA7000 Radio With Variable-Capacitance Diode Tuning

December 1988

7-58

Application Note

Signetics linear Products

A Complete FM Radio on a Chip

AN192

+4,5 v --r------1~--...-----..___----_1--~--....,
CIS
el7
3,9 nF
4,7 nF

lOOnF

Cl0
4,1 nF

18

10

17

TOA7QOO
(see FIg 1j

The component values in Figure 16 result in
an IF of 4.5kHz and an IF bandwidth of 5kHz
(Figure 17). If the IF is multiplied by N, the
values of capacitors C17 and C,a in the allpass filters and the values of filter capacitors
C7, Ca, C1Q, Cll, and C'2 must be multiplied
by 1IN. For improved IF selectivity to achieve
greater adjacent channel attenuation, second-order networks can be used in place of
C,o and Cll.
In this circuit the detuning noise generator is
not used. Since the circuit is mainly for
reception of audio signals, the audio output
must be passed through a low-pass Chebyshev filter to suppress IF harmonics.

Cl
150 nF

AUDIO AMPLIFIER AND
DETUNING INDICATOR
CIRCUITS
Audio output stages suitable for use with the
TDA7000 are shown in Figures 18 and 19.
Figure 20 shows how the muting signal can
be used to operate an LED to give an
indication of detuning.

Figure 16. A Narrow-Band FM Receiver With a Crystal-Controlled Local Oscillator

v
20 109 -.!..

+20~

Vo +10
(dB)

I

0fF,==~~:;;e+
-10

,

I

25dB

II

-20~

r

i
- 30

I

~::o~~'----~---~,~-----+.~----~

I
I

10

15

f IkHzJ

20

Figure 17. IF Selectivity for the Narrow-Band FM Receiver

December 1988

7-59

•

Application Note

Signetics Linear Products

A Complete FM Radio on a Chip

.3V----------~--------~

AN192

65n

earpiece

BC550B

Po~0,4mW.d=10%

OV----~--~--------_4

NOTE.
1 These components replace R2 and C2

I

qUIescent current'"' 4 mA

FIgure 1

In

Figure 18. A O.4mW Transistor Audio Output Stage Without Volume Control for
Driving an Earpiece

L

I

. , 5V
to pIn

5

22

n

TDA7000'~

220,uF

TDA10llA
220pF

t..---+-1

PREAMP

4,7!1

from pm 2

TDA7000

------r---,

an

11

~+---------+-~==~(log)

4.7
of

OV ____4-__

~

____

~

________

~

__________.__

O,l,!.1F

~

__

~

__________

~

____

~

I :"';~,e ~~""'.'~ ~ -"". 0'.0 , '.0'_' 0W,"~~, ~,-,~
Figure 19. An Integrated 250mW Audio Output Stage
--------------------------~

----------

j;
l

-------t".
~~; 1=:J70
kn
Be558
.3V

'ro::;

TOA7DQO
(F,~ 1l

I

ACKNOWLEDGEMENTS

REFERENCE

The authors wish to acknowledge the Inlormatlon provided by D Kasperkovltz and H.v
Rumpt lor incorporation In thiS article

KANOW, W. and SIEWERT, I., 'Integrated
CirCUitS lor hi-II radios and tuners', Electromc
Components and Appilcatlons, Vol. 4, No 1,
November 1981, pp 11 to 27.

-7

OV
lD08020S

Figure 20. A Detuning Indicator Driven
by the Mute Signal From the TDA7000

December 1988

7-60

Signetics

AN193
TDA7000 for Narrow-Band
FM Reception
Application Note

Linear Products

Author: W. V. Dooremolen

INTRODUCTION
Today's cordless telephone sets make use of
duplex communication with carrier frequencies of about 1. 7MHz and 49MHz.

1.7MHz

• In the base unit incoming telephone
information IS frequency-modulated on a
1.7MHz carrier.
• This 1.7MHz signal IS radiated via the
AC mains line of the base unit.
• The remote unit receives this signal via
a ferrite bar antenna.
• The remote Unit transmits the call
signals and speech information from the
user at 49MHz via a telescopic
antenna.
• The base unit receives this 49MHz FMmodulated signal via a telescopic aerial.

Today's Remote Unit Receivers
In cordless telephone sets, a normal superheterodyne receiver is used for the 1.7MHz
handset. The suppression of the adjacent
channel at, e.g., 30kHz, must be 50dB, and
the bandwidth of the channel must be
6 - 10kHz for good reception. Therefore, an
IF frequency of 455kHz is chosen. Since at
this frequency there are ceramic filters with a
bandwidth of 9kHz (AM filters), the 1.7MHz is
mixed down to 455kHz with an oscillator
frequency of 2.155MHz. Now there is an
image reception at 2.61 MHz. To suppress
this image sufficiently, there must be at least
two AF filter sections at the input of the
receiver.
The ceramic IF filter with its sub harmonics is
bad for far-off selectivity, so there must be an
extra LC filter added between the mixer
output and the ceramic filter.
After the selectivity there IS a hard limiter for
AGC function and suppression of AM.
Next, there is an FM detector which must be
accurate because it must detect a swing of
± 2.5kHz at 455kHz; therefore, it must be
tuned.

December 1988

2.155MHz

Figure 1. Remote-unit Receiver: 1.7MHz
Figure 1 shows the block diagram which
fulfills this prinCipal. The total number of
alignment points of this receiver is then 5:
2 AF filters
1 Oscillator
1 IF filter
1 FM detector
5 Alignments

A Remote Unit Receiver With
TDA7000
The remote unit receiver (see Figure 2) has
as its main component the IC TDA7000,
which contains mixer, oscillator, IF amplifiers,
a demodulator, and squelch functions.
To avoid expensive filtering (and expensive
filter-adjustments) in AF, IF, and demodulator
stages, the TDA7000 mixes the incoming
signal to such a low IF frequency that filtering
can be realized by active AC filters, in which
the active part and the As are integrated.
To select the incoming frequency, only one
tuned circUit is necessary: the oscillator tank
circuit. The frequency of this circuit can be set
by a crystal.

IMAGE RECEPTION
For today's concept, a number of expensive
components are necessary to suppress the

7-61

image sufficiently. The suppression of the
image is very important because the signal at
the Image can be much larger than the
wanted Signal and there is no correlation
between the Image and the wanted signal.
In a concept with 455kHz IF frequency, the
1.7MHz receiver has Image reception at
2.1 55MHz. In the TDA7000 receiver, the IF
frequency is set at 5kHz. Then the 1.7MHz
receiver (with 1.695MHz oscillator frequency)
has image reception at 1.69MHz, which is at
10kHz from the required frequency (see Figure 3).
An IF frequency of 5kHz has been chosen
because:
• this frequency is so low, there will be
no neighbOring channel reception at the
Image frequency.
• this frequency IS not so low that at
maximum deviation (maximum
modulation) distortion could occur
(folding distortion, caused by the higherorder bessel functions)
• this frequency gives the opportunity to
obtain the required neighbOring channel
suppression with minimum components
in the IF selectivity.

Signetics Unear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

+Yo

+
NEI535

NE5535

C> C>

A.F.FlLTER

A.F.AMPL

TALK

o
STANDBY

pi
Figure 2

CIRCUIT DESCRIPTION
(see Figure 2)
When a remote unit is at "power-on" in the
"standby" position, it IS ready to receive a
"bell signal". A bell signal coming through
the telephone line will set the base unit in the
mode of transmitting a 1.7MHz signal, modulated with, e.g., 0.75kHz with ±3kHz deviation.

,,
,,

The AF output of the demodulator (Pin 4) is
fed to the AF filter and AF amplifier NE5535.

The RF Input Circuit
As the image reception is an In-channel
problem, solved by the choice of IF frequency
and IF selectivity, the RF Input filter is only
required for stopband selectivity (a far-off
December 1988

,

,----

+
I
I
I

I

I
I
I
I

The ferrite antenna of the remote unit receives this signal and feeds it to the mixer,
where it IS converted Into a 5kHz IF signal.
Before the RF Signal enters the mixer (at Pins
13 and 14) it passes RF selectivity, taking
care of good suppression of unwanted signals from, e.g., TV or radio broadcast frequencies. The IF signal from the mixer output
passes IF selectivity (Pins 7 to 12) and the IF
amplifier/limiter (Pin 15), from which the output IS supplied to a quadrature demodulator
(Pin 17). Due to the low IF frequency, cheap
capacitors can be used for both IF selectivity
and the phase shift for the quadrature demodulator.

,, /

~
'"

'IMAGe

-

SkHz/D1V.

'ose
0P01181S

Figure 3
seleqtlVity to suppress unwanted large signals
from, e.g., radio broadcast transmitters).
In a remote unit receiver at 1.7MHz, this filter
is at the ferrite rod. Figure 4 shows the
bandpass behavior of such a filter at 1.7MHz.

The Mixer
The mixer conversion gain depends on the
level of the oscillator voltage as shown in
Figure 5, so the reqUired oscillator voltage at
Pin 6 is 200mVRMs.

7-62

The OSCillator
To obtain the required frequency stability in a
cordless telephone set, where adjacent channels are at 20 or 30kHz, crystal oscillators are
commonly used.
The crystal OSCillator circuits usable for this
kind of application always need an LC-tuned
resonant circuit to suppress the other modes
of the crystal. In this type of oscillator (see
Figure 6 as an example) the crystal is in the
feedback line of the oscillator amplifier. Inte-

Application Note

Signetics Linear Products

TDA7000 for Narrow-Band FM Reception

AN193

gration of such an amplifier should give a 2·
pin oscillator.
0-

The TDA7000 contains a 1'pin oscillator. An
amplifier with current output develops a volt·
age across the load impedance.

I

-.0
-.5

Voltage feedback is internal to the IC.
To obtain a crystal oscillator with the
TDA 7000 1·pin concept, a parallel circuit
configuration as shown in Figure 7 has to be
used.
Explanation of this circuit:
a. Without the parallel resistor RpFigure 8 shows the relevant part of the
equivalent circuit. There are three fre·
quencies where the circuit is in reso·
nance (see Figure 9, and the frequency
• response for "impedance" and "phase",
shown in Figure 10). The real part of the
highest possible oscillation frequency
dominates, and, as there is also a zero·
crossing of the imaginary part, this high·
est frequency will be the oscillator fre·
quency. However, this frequency (fpAR) IS
not crystal-controlled; it is the LC oscillation, in which the parasitic capacitance of
the crystal contributes.
b. With parallel resistor RpThe frequency response (in "amplitude"
and "phase") of the OSCillator circuit of
Figure 7 with Rp is given in Figure 11. As
the resistor value of Rp is large related to
the value of the crystal series resistance
Rl or R3, the influence of Rp at crystal
resonances is negligible. So, at crystal
resonance (see Figure 9b), R3 causes a
circuit damping
R

=~oR3
°C
W2

12

+

R3 (1

'Il

-3S

-40

'.4

1.2

• .0

1.6

17

I

~

"
Z

-1

~
0:

-2

~

-3

w

8
0:
W

~

w

~

0:

I
I

Figure 6

December 1988

I

I

........

/'

"'-..

i'...

-4

-s
.....
-7
-8

-"
-.0
.00

200

300

400

500

600

700

800

900

'000

'100

Vosc(mV)

Figure 5. Relative Mixer Conversion Gain
RO ° ROAMPING
Ro + ROAM PING

RC

Thus a damping resistor parallel to the crystal
(Figure 7) damps the parasillc LC oscillation
at the highest frequency. (Moreover, the
Imaginary part of the Impedance at this frequency shows incorrect zero-crossing.)
+

'.2

2.0

TOA7000 AT lose = 1.7MHz

1
2 oRp ( 1 +C2 }2.
ROAMPING=_oRpoC.
W2
C.

Cs

1.8

Figure 4

where

R.

L-_

L, = 2.3mH

-30

However, at the higher LC-oscillation frequency fpAR (see Figure 9c), Rp reduces the
circuit impedance Ro to

Q

.4

20:1

-20

40

~950

-25

+~)~
C1

JIf----I0 f - - - - - .

{]

-s

'3

Taking care that Rp ~ RSERIES, the resistor is
too large to have influence on the crystal
resonances. Then with the impedance Rc at
the parasitic resonance lower than R at

7-63

crystal resonance, oscillation will only take
place at the required crystal frequency, where
impedance is maximum and phase is correct
(In this example, at third-overtone resonance).
Remarks:
a. It is advised to avoid inductive or capacitive coupling of the oscillator tank circuit
with the RF input circuit by careful positioning of the components for these cirCUitS and by avoiding common supply or
ground connections.

The IF Amplifier
Selectivity
Normal selectivity in the TDA7000 is a fourthorder low-pass and a first-order high-pass

•

Signetics Linear Products

Application Note

AN193

TDA7000 for Narrow-Band FM Reception

filter. This selectivity can be split up In a
Sallen and Key section (Pins 7, 8, 9), a
bandpass filter (Pins 10, 11), and a first-order
low-pass filter (Pin 12).
Some possibilities for obtaining required selectivity are given:
a. In the basic application circuit, Figure
12a, the total filter has a bandwidth of
7kHz and gives a selectIVity at 25kHz IF
frequency of 42dB.
In this filter the lower limit of the passband IS determined by the value of C4 at
Pin 11, where C3 at Pin 10 determines
the upper limit of the bandpass filter
section.
b.

To obtain a higher selectivity, there IS the
possibility of adding a cOil in series with
the capacitor between Pin 11 and
ground. The so-obtalned fifth-order filter
has a selectivity at 25kHz of 57dB (see
Figure 12b).

c.

If this selectivity IS still too small, there IS
a possibility of Increasing the 25kHz selectiVity to 65dB by adding a coil In series
with the capacitor at Pin 11 to ground. In
this application, where at 5kHz IF frequency an adjacent channel at -30kHz
will cause a (30-5) = 25kHz interfering IF
frequency, the pole of the last-mentioned
LC filter (trap function) IS at 25kHz (see
Figure 12c).

For cordless telephone sets with channels at
15kHz distance, the filter characteristics are
optimum as shown in the curves in Figure 13,
in which case the filters are dimensioned for
5kHz IF bandwidth (instead of 7kHz). So for
thiS narrow channel spacing application, the
reqUired selectivity is obtained by redUCing
the IF bandwidth; thiS at the cost of up to 2dB
loss In sensitiVity.
NOTE:
At 5kHz IF frequency adjacent channels at ± 15kHz
give undeSired IF frequenCies of 20kHz and 10kHz,
respectively

LlmlterlAmplifier
The high gain of the limiterI amplifier provides
AVC action and effective suppression of AM
modulation. DC feedback of the limiter IS
decoupled at Pin 15.

The Signal Demodulator
The Signal demodulator IS a quadrature demodulator driven by the IF signal from the
limiter and by a phase-shifted IF Signal derived from an all-pass filter (see Figure 14).
ThiS filter has a capacitor connected at Pin 17
which fixes the IF frequency. The IF frequency is where a 90 degree phase shift takes
care of the center poSItion In the demodulator
output characteristics (see Figure 15, showing the demodulator output (at Pin 4) as a
function of the frequency, at 1mV Input signal).
December 1988

TC01090S

Figure 7

The AF Output Stage

RF Pre-8tage at 46MHz

The signal demodulator output IS available at
Pin 4, where a capaCitor, C, serves for elimination of IF harmonics. ThiS capacitor also
influences the audiO frequency response. The
output from this stage, available at Pin 2, has
an audio frequency response as shown In
Figure 16, curve a. The output at Pin 2 can be
muted.

For better quality receivers at 46MHz, an RF
pre-stage can be added (see Figure 21) to
Improve the nOise figure. Without thiS transistor, a nOise figure F = 11 dB was found. With a
transistor (BFY 90) with RC coupling at SmA,
F = 7dB or at 6mA F = 6dB.
With a transistor stage having an LC-tuned
CirCUit, one can obtain F = 7dB at I = O.SmA.

Output Signal Filtering

NOTE:

Output signal filtering is reqUired to suppress
the IF harmOniCs and Interference products of
these harmOniCs with the higher-order bessel
components of the modulation. Active filterIng with operallOnal amplifiers has been used
(see Figure 17). The frequency response of
such a filter IS given In Figure 16, Curve b, for
an actIVe second-order filter with an additional passive RC filter.

The nOise figure Includes Image-noise

Output Amplification
The dimensiOning of the operational amplifier
of Figure 17a results In no ampllflcallOn of the
AF signal. In case amplification of thiS op amp
is reqUired, a feedback resistor and an RC
filter at the reverse Input can be added (see
Figure 17b, for about SOdB amplification).

MEASUREMENTS
For sensitIVIty, signal handling, and nOise
behaVior information in a standard application
as shown in Figure 1B, the Signal and nOise
output as a function of input Signal has been
measured at 1.7MHz, at 400Hz modulation
where the deviation IS ± 2.5kHz (see Figure
19). As a result the S+ N/N ratio is as given In
Figure 19, Curve 3.

APPENDIX
RF-Tuned Input Circuit at
46MHz
In Figure 20 a filter IS given which matches at
46MHz a 75.11 aerial to the Input of the
TDA 7000. Extra suppression of RF frequencies outside the passband has been obtained
by a trap function.

7-64

An LC Oscillator at 1_7MHz
An LC OSCillator can be designed with or
without AFC. If for better stability external
AFC is reqUired, one can make use of the DC
output of the Signal demodulator, which delivers BOmVlkHz at a DC level of 0.65V to
+ supply. An LC OSCillator as shown in Figure
22a, uSing a capacitor with a temperature
coeffiCient of -150ppm, gives an OSCillator
Signal of 190mV, with a temperature stability
of 1kHz/50o.
With the use of AFC, as shown In Figure 22b,
one can further Improve the stability, as AFC
reduces the Influence of frequency changes
In the transmitter (due to temperature Influence or aging). The given CirCUit gives a
factor 2 reducllOn. Note that the temperature
behaVior of the AFC diode has to be compensated. In Figure 22b, with BB405B haVing a
capacitance of 18pF at the reverse voltage
V4 = 0.7V, the temperature coeffiCient of the
capacitor C has to be -200ppm.

AF Output Possibilities
The AF output from the Signal demodulator,
available at Pin 4, depends on the slope of
the demodulator as shown in Figure 15. The
TDA7000 AF output IS also available at Pin 2
(see Figure 23). The Important difference
between the output at Pin 2 and the output at
Pin 4 IS that the Pin 4 output IS amplified and
limited before It IS led to Pin 2 (see Figure 24).
Moreover, the Pin 2 output IS controlled by
the mute function, a mute which operates in
case the received signal IS bad as far as
nOise and distortion are concerned.

Application Note

Signetics Linear Products

AN193

TDA7000 for Narrow-Band FM Reception

c,

c,
R,

!-I

Rp

b. At f3

•••••[

R,

......._

c. At

fpAR

...........J

TC01060S

Figure 9

The Pin 2 output delivers a higher AF signal;
however, the AF output spectrum shows
more mixing products between IF harmonics
and modulation frequency harmonics. This is
due to the "limited output situation" at Pin 2.
In narrow-band application with relatively
large deviation these products are so high
that extra AF output filtering is required and,
moreover, the IF center frequency has to be
higher compared to the concept, using AF
output at Pin 4.
So for those sets where the mute/squelch
function of the TDA7000 is not used, and the
higher AF output is not required, the use of
the AF output at Pin 4 is advised, giving less
interfering products and simplified AF output
filtering.

December 1988

Squelch and Squelch Indication
The TDA7000 contains a mute function, controlled by a "waveform correlator", based on
the exactness of the IF frequency.
The correlation circuit uses the IF frequency
and an inverted version of it, which IS delayed
(phase-shifted) by half the penod of nominal
IF. The phase shift depends on the value of
the capacitor at Pin 18 (see Figure 23).
This mute also operates at low field strength
levels, where the noise in the IF signal
indicates bad signal definition. (The correlation between IF signal and the inverted
phase-shifted version is small due to fluctuations caused by noise; see Figure 25.) This
field strength-dependent mute behavior IS
shown In Figure 26, Curve 2, measured at full

7-65

mute operation. The AF output IS not "fastswitched" by the mute function, but there is a
"progressive (soft muting) switch". This soft
muting reduces the audiO output signal at low
field strength levels, Without degradation of
the audio output signal under these conditions.
The capacitor, C1, at Pin 1 (see Figure 23)
determines the time constant for the mute
action.
Part operation of the mute IS also a pOSSibility
(as shown by Figure 26, Curve 3) by circUiting
a resistor In parallel With the mute capacitor
at Pin 1.
In Figure 26 the small signal behavior with the
mute disabled has been given also (see
Curve 1).

•

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

One can make use of the mute output signal,
available at Pin 1, to indicate squelch situation by an LED (see Figure 27). Operation of
the mute by means of an external DC voltage
(see Figure 28) IS also possible.

AN193

8ID1V.
80

Bell Signal Operation
To avoid tone decoder filters and tone decoder rectifiers for bell signal transmission, use
can be made of the mute Information in the
TDA 7000 to obtain a bell signal without the
transmission of a bell pilot signal.
With a handset receiver as shown In Figure
23 In the "standby" poslllOn, the high mute
output level turns amplifier 1 off via transistor
Tl until a correct IF frequency is obtained.
ThiS sltuallOn appears at the moment that a
bell signal sWitches the base unit In transmission mode If the transmitted field strength IS
high enough to be received above a certain
nOise level, the mute level output goes down;
Tl will be closed and amplifier 1 starts
operating. However, due to feedback, this
amplifier starts OSCillating at a low frequency
(a frequency dependent on the filter concept).
This lOW-frequency signal serves for bell signal information at the loudspeaker.
SWitching the handset to "talk" position will
stop OSCillation. Then amplifier 1 serves to
amplify normal speech Information.

FREQUENCY

a_ l-Pin Crystal Oscillator

100/DIV.
800

Mute at Dialing
DUring dial operation, the key-pulser IC delIVers a mute voltage. This voltage can be used
to mute the AF amplifier, e.g., via Tl of the
bell signal circUit/amplifier (see Figure 23)

CONCLUSIONS
The application of the TDA7000 in the remote
unit (handset) as narrow-band FM receiver IS
very attractive, as the TDA7000 reduces
assembly and post-production alignment
costs. The only tunable circuit is the OSCillator
Circuit, which can be a Simple crystal-controlled tank circuIt.
A
•
•
•
•

TDA7000 with:
fifth-order IF filter
third-order AF output filter
matched Input circuit
cryslal OSCillator tank circuit

• disabled mute circuit
gives a sensitivity of 2.5p.V for 20dB slgnal-tonOise ratio, at adjacent channel selectIVIty of
40dB (at 15kHz) In cordless telephone application at 1.7MHz.
The TDA7000 circuit IS:
• without an RF pre-stage
• without RF-tuned circuits
• without oscillator transistor (and Its
components)

December 1988

~~

______

10MG

~

I,

__

~~~~~~ww~~

13

__

lpar

~

__

~~~~~~

1G

FREQUENCY

b_ l-Pin Crystal Oscillator

Figure 10
• without LC or ceramiC filters in IF and
demodulator
For Improved performance, the TDA7000 CirCUit can be expanded:
• with an RF pre-slage and RF selectIVIty
• with higher-order IF filtering
• with mute/squelch function.

7-66

For reduced performance the TDA7000 Circuit can be Simplified.
• to LC-tuned OSCillator
• to lower-order IF filter
• to bell Signal operation without pilot
transmission

Signetics Unear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

8/DIV.
80

IOn
Rp-250Il

FREQUENCY

.......

a. 1-Pin Crystal Oscillator
(R = ce, 250, 60)

1001D1V.
800

250n
1 _____4-______-U~::::~~:=~======~IO~n~--of-

FREQUENCY

b. 1-Pln Crystal Oscillator
(R = ce, 250, 60)
Figure 11

December 1988

7-67

•

Signetics linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

10000DIY
40

Rs

12K

Rt

R2=2.2K

A3

A4"'" 4.7K

C1
C2
C3

1.3nf
68nF
3nF

~

47nF

Cs

3.3nF

.....0



FREQUENCY

b.

Figure 12

December 1988

7-68

r
Rs=12K
R,""'R2"'2.2K
R3=R4=4.7K

C,= 1.3nF
C2=68nF
C3=3nF
C4=47nF

Cs=3.3nF
L, = 100mH

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

IF SELECTIVITY

-10

-20

-70

10

15

20

FREQUENCY (kHz)

c.
Figure 12 (Continued)

78'

788101112

10111215

b.

8.

c.

d.
Figure 13

December 1988

16

7-69

•

Application Note

Signetics Unear Products

AN193

TDA7000 for Narrow-Band FM Reception

Val

R.

UK

' - - - - - - _ TO CORRELATOR

17 _ _ _ _ _ _

NOTES:
With R2 =O

.=
for

-2 tan, wA,e'7
1
f/J- -90"C. C ' 7 - - - - - 41nF for'IF-5kHz

WR1~
R.

To Improve the performance of the all-pass flHer with the amplitude Ilrmted IF waveform. R2 has been added. Since this influences the phase angle, the value of e17 must be
Increased by 13%. I.e., to 4.7nF

Figure 14. FM Demodulator Phase-Shlft Circuit (All-Pass Filter)

... H-+-+++-+-+-H--+-+-+++
..
i ..
=
iI ......
..
....
1A

TDAJDIIDItT17MHI,.VJ-1MV

,~

u

°0

,

2

a

4

I

•

7

••

--

,011 1211 M 1& ... 17,. . . .

Figure 15

December 1988

v..

7-70

It.

Signetics Unear Products

Application Note

TDA7000 for Narrow-Band FM Reception

.

AN193

I"'r\.
~.
"\

"-

I
.....

"'0'2

:a

4

s •

7

•

•

,-

..... I'-

,01112 11 1415 ,.,1"

,. 20 21 Z!

Figure 16

+

-=-

":"

a.

1CIK
270

J

1,.,

b.
Figure 17

December 1988

7-71

"""""

•

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

..

AN193

+Y,

--

"
,.

15

17

1

3~

l'

"

~~ ~

!:

I

I

..

I
I

---'

Figure 18

0

10

-10

50

-211

40

I

~-30 !tso

II

I

;,

1/

"f-~fm=4OOHz

,
I-"

'SIN

0

.:

c
-40

20

-&0

10

,,

r\
r\

Nl

100"V
1mV
V, AT PINS 13114 (WITH R. - 500)

Figure 19

December 1988

7-72

TDA7000
f.=1.7MHz
Vs-4.8V

Application Note

Signetics Linear Products

AN193

TDA7000 for Narrow-Band FM Reception

PC COIL a = 20

IINTERNAL

BOPF[llE1
BOpF
II
950
200pF
I

so

10

<10

12pF

2.2oF

I
I

-WOL~~~SO~~~'OO~~~'SO~~-LLL~-LLL~-L~~-L~~~~G
10MGJDIY.

FREQUENCY

Figure 20

+

osc. TANK CIRCUIT

OSCILLATOR

I

"

,.

•

MIXER

IF - AMPLJUMfTER

,.

1
Figure 21

December 1988

7-73

Signetlcs Linear Products

Application Note

AN193

TDA7000 for Narrow-Band FM Reception

TOKOCOIL,np£7IFI:
ft'I-IOTUANS
nz,.7TURHS
Qo·tOO
L"32I1H

a.

.....

b.
Figure 22

+Vo

Figure 23. Remote Unit Receiver: 1.7MHz

December 1988

7-74

Signetlcs Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

OPEN LOOP: IF SIGNj INJECTD AT P'j 7 OF TDA7000
1.2

'"

1.0

5'

g

?

"

II'-...

0.8

..........

'\

0.5

'\.

'-.... ~

0.8

...............

k

OA

0.2

o

o
'I.F(kHZ)

V"'~ (VOLT)IAT R..,.I= 22KO

:--r-- :-=vw

'"'"

'-.....

~
10

11

Figure 24. Demodulator Characteristics

LARGE
COARElAnON
WITH
CORRECT
T....NG

a.

SMALL

I.F·IlSUL

CORRELATION
DUE TO

DETUNING

LF'SLJL..fl

•

b.

VEAYSMALL
CORREl.ATlON

IF.JlJLj"

DUE TO
NOISE

IF.'~
c.

Figure 25. Function of the Correlation Muting System

December 1988

7-75

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

•
·1

Ii

•

')
Vi
,

-20

J VI. -I"i'I IIIII
,IV

'

I

,! II
,I ,

I

1'1:

I

!

-3D

I

(

I

-MUTE DISABLE

---'--l~~~~I~~:UTE

-so

I

I

I

iii:

Ii'ilil I, j:I:11
t__ _

....

I

I

III

Lllwm U: ~!I

1mV

1.V

Figure 26

+

TDA 7000

1---,\47N°-,.K--y-£ BC5sa

'"€9

LED

161------+

Figure 27

/
/
II
I

1/

- e-

I

o

0

--e-

V
o

./
0.1

0.2

0.3

OA

OS

08

0,7

08

0.9

13

14

VHi(YOL.TJ

Figure 28
Previously published as "BAE83135," Eindhoven, The Netherlands, December 20, 1983.

December 1988

7·76

AN193

TDA7010

Signetics

FM Radio Circuit (SO Package)
Product Specification

Linear Products
FEATURES

DESCRIPTION
The TDA7010T is a monolithic integrated circuit for mono FM portable radios,
where a minimum of peripheral components is important (small dimensions
and low costs).
The IC has an FLL (Frequency-Locked
Loop) system with an intermediate frequency of 70kHz. The IF selectivity is
obtained by active RC filters. The only
function which needs alignment is the
resonant circuit for the oscillator, thus
selecting the reception frequency. Spurious reception is avoided by means of a
mute circuit, which also eliminates too
noisy input signals. Special precautions
are taken to meet the radiation requirements.

PIN CONFIGURATION

• RF input stage
•
•
•
•
•
•

D Package

Mixer
Local OSCillator
IF amplifierllimiter
Phase demodulator
Mute detector
Mute switch

APPLICATIONS
• Mono FM Portable Radios
• LAN
• Data Receivers
• SeA Receivers

TOP VIEW

PIN NO.
1

2
3
4

ORDERING INFORMATION

5
6

DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic SO DIP (SOT 109 A)

o to

ORDER CODE

+70·C

TDA7010TD

7
8
9
10
11

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

12

V

Oscillator voltage (Pin 5)

Vce-0.5 to Vee + 0.5

V

Total power diSSipation

See derallng curve Figure 2

Vcc

Supply voltage (Pin 4)

V6-S

TSTG

Storage temperature range

TA

Operating ambient temperature range

October 10, 1986

-55 to +150

·C

o to +60

·C

7-77

DESCRIPTION

Muting capaCitor
AudiO frequency output

Loop filter capaCitor
Supply Voltage

veo

1st Integrator capacitor (to Pin 8)

2nd Integrator capacitor
1st Integrator capacitor (to Pin 6)
IF filter capacitor
IF limiter capacitor
RF mput

Mixer

12
13
14
15

Current source capacitor
Ground

16

Correlator capacitor

Demodulator capacitor

•
853-0894 85939

Signetics Unear Products

Product Specification

TDA7010

FM Radio Circuit (SO Package)

BLOCK DIAGRAM
RFINPUT

15

16

CORRELATOR
2.7K

1.4V

IF FILTER
12K

4.7K

Cp
Cs

v~o-+---t---------------~------------~------------------------4-----------~
AF OUTPUT
EIOO3371S

October 10, 1986

7-78

Product Specification

Signetics Unear Products

TDA7010

FM Radio Circuit (SO Package)

DC ELECTRICAL CHARACTERISTICS vee = 4.5V; T A = 25°C: measured in Figure 3, unless otherwIse specilled.
LIMITS
PARAMETER

SYMBOL

TEST CONDITION

Vee

Supply voltage

(Pin 4)

Ice

Supply current

Vee=4.5V

UNIT
Min

Typ

Max

2.7

4.5

10

V

8

mA
pA

Is

Oscillator current

(Pin 5)

280

V12-14

Voltage

(Pin 12)

1.35

V

12

Output current

(PIn 2)

60

pA

V2-14

Output voltage

(PIn 2) RL = 22kG

1.3

V

AC ELECTRICAL CHARACTERISTICS Vee = 4.5V; T A = 25°C; measured in Figure 3 (mute switch open, enabled);
IRF = 96MHz (tuned to max. signal at 5pV EMF) modulated with ill = ±22.5kHz; 1M = 1kHz; EMF = 0.2mV (EMF voltage at a source
impedance 01 75G); RMS noise voltage measured unwelghted (I = 300Hz to 20kHz), unless otherwIse specllled.
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITION
Min

EMF

SensItIvity (see Figure 2)
(EMF voltage)

-3dB hmlting; mutIng disabled

1.5

-3dB muting

6

SIN = 26dB
EMF

Signal handling (EMF voltage)

SIN

Signal-to-noise ratoo

THO

Total harmonic distortion

AMS

AM suppression 01 output voltage

Typ

THO

< 10%;

ill = ±75kHz

Max
p.V

5.5
200

mV

60

dB

ill = ± 22.5kHz
ill = ± 75kHz

0.7
2.3

%
%

(ratIo 01 the AM output sIgnal relerred to the
FM output signal)
FM sIgnal: 1M = 1kHz; ill = ± 75kHz
AM sIgnal: 1M = 1kHz; m = 80%

50

dB

(ilVee = 100mV; I = 1kHz)

10

dB

(Pin 5)

250

mV

Supply voltage (ilVee = 1V)

60

kHzlV

43

dB

RR

Ripple rejection

VS-4RMS

Oscillator voltage (RMS value)

ilfose

Variation 01 oscillator Irequency

S+3OO

Selectivity

ilfRF

AFC range

±300

kHz

B

Audio bandwidth

ilVa = 3dB Measured wIth pre-emphasis
(t= 50p.s)

10

kHz

Va RMS

AF output voltage (RMS value)

RL=2kG

75

28

S-300

RL

Load resistance

October 10, 1986

mV

Vee = 4.5V

22

Vee = 9.0V

47

7-79

kG

Signetics Linear Products

Product Specification

TDA7010

FM Radio Circuit (SO Package)

04

0.3

\

~j 'O'

\
\

\

0.'

~

\

o

50

-50

'50

100

TA'·C)

Figure 1. Power Derating Curve

R • v,
2

m
:!!.
0
>

-20

r-x

V,r--.

-40

-60

-80
10-6

'I I

sL

!

II I II!

I I
I
I

,,[

! [I I I! I

I

I'N-li

!

I

II

THO!
10- 5

I I! I

I I II

!! I,

!
I!,

i
I

10-4

iI

I!,

i

NOTE:
1. The mutmg system can be disabled by feeding a current of about

I

10-3
EMF tV) at R2 = 75

20~

I

I

NOISE

10-2

I II
, .

I
I

I,

I

I

I

l

I
I

10- 1

40

I

I :I
! !

I

c
:r

: I

t-

,

O

{!

Into Pin 1.

Conditions: 0 dB = 75mVi fRF = 96MHz
for S + N curve: .6.1 = ± 22.5kHz: fll = 1kHz
for THO curve: .6.1 = ± 75kHz: fu = 1kHz

Figure 2. AF Output Voltage (Vo) and Total Harmonic Distortion (THD) as a Function of the EMF Input Voltage (EMF)
With a Source Impedance (Rs) of 75Q: (1) Muting System Enabled; (2) Muting nystem Disabled

October 10, 1986

7-80

Product Specification

Signetics Linear Products

FM Radio Circuit (SO Package)

220pF

TDA7010

33QpF

15

16

CORRELATOR

27K

10K
150
nF
ENABLED

RL
22K

DISABLED

r'·

3.3nF
180pF

8 nF

Vcc~~-----4---4~----------------~-------------+----------------------------~--------------~
MUTE SWITCH

AF OUTPUT

Figure 3. Test Circuit

October 10, 1986

7-81

•

TDA7021

Signetics

Single-Chip FM Radio Circuit
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The TDA7021T integrated radio receiver
circuit is for portable radios, stereo as
well as mono, where a minimum of
periphery is important in terms of small
dimensions and low cost. It is fully compatible for applications using the lowvoltage micro tuning system IC (MTS).
The IC has a frequency-locked loop
(FLL) system with an intermediate frequency of 76kHz. The selectivity is obtained by active RC filters. The only
function to be tuned is the resonant
frequency of the oscillator. Interstation
noise as well as noise from receiving
weak signals is reduced by a correlation
mute system.

•
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Special precautions have been taken to
meet local oscillator radiation requirements. Because of the low intermediate
frequency, low pass filtering of the MUX
signal is required to avoid noise when
receiving stereo. 50kHz roll-off compensation, needed because of the low pass
characteristic of the FLL, is performed
by the integrated LF amplifier. For mono
application this amplifier can be used to
directly drive an earphone. The field
strength detector enables field strengthdependent channel separation control.

APPLICATIONS

RF input stage
Mixer
Local oscillator
IF amplifier/limiter
Frequency detector
Mute circuit
MTS compatible
Loop amplifier
Internal reference circuit
LF amplifier for
- mono earphone amplifier or
-MUX filter
• Field strength-dependent channel
separation control facility

• FM radios
• Stereo
• Mono

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

16-Pin Plastic SO

ORDER CODE

+70·C

TDA7021TD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vee

Supply voltage (Pin 4)

VS-5

Oscillator voltage (Pin 5)

T sig

Storage temperature range

TA

Operating ambient temperature range

8JA

Thermal resistance
From junction to ambient

December 1986

RATING

UNIT

7

V

Vcc-0.5 to Vcc+0.5

V

-55 to +150

·C

-10 to +70

·C

300

·C/W

7-82

SIGNAL
.........._ _....,jt-STRENGTH

TOP VIEW

Signelics Unear Products

Preliminary Specification

TDA7021

Single-Chip FM Radio Circuit

BLOCK DIAGRAM

r
16

17.51<

FIELD
STRENG1H

RFINPUT

MUXOUT

1
14

15

13

12

11

52k

170,.,.

+
O.9V

13k

700

700

v~-J~~----~~~~----~~----------~----------~~~------~------------~
60073108

DC ELECTRICAL CHARACTERISTICS
SYMBOL

vee = 3V, TA = 25°C, unless otherwIse specIfIed.
MIN

PARAMETER

1.8

TYP

MAX

3.0

6

UNIT

Vee

Supply voltage (PIn 4)

lee

Supply current at Vec = 3V

63

mA

V

Is

OSCIllator current (PIn 5)

250

iJA

V13.3

Voltage at PIn 13

0.9

V

V14-3

Output voltage (PIn 14)

1.3

V

December 1988

7-83

•

Signetics linear Products

Preliminary Specification

TDA7021

Single-Chip FM Radio Circuit

AC ELECTRICAL CHARACTERISTICS
(MONO OPERATION)

Vcc = 3V, TA = 25°C; measured In Figure 5; fRF = 96MHz modulated with
t.1 = ± 22.5kHz; 1M = 1kHz; EMF = 300flV (EMF voltage at a source Impedance 01
75Q); RMS noise voltage measured unwelghted (I = 300Hz to 20kHz), unless
otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

EMF

Sensitivity (see Figure 2)
(EMF voltage)
for -3dB IImlllng; muting disabled for -3dB
muting lor SIN = 26dB

EMF

Signal handling (EMF voltage) for THD
t.f = ± 75kHz

< 10%;

Typ

Max

4.0
5.0
7

flV
flV
flV

200
60

mV

SIN

Signal-to-noise ratio

60

dB

THD

Total harmonic distortion
at t.f = ± 22.5kHz
at t.f = ± 75kHz

0.7
2.3

%
%

AMS

AM suppression of output voltage
(ratio of AM signal: 1M = 1kHz;
m = 80% to FM signal: fM = 1kHz;
at t.f = ± 75kHz)

50

dB

RR

Ripple rejection (t.Vcc= 100mV; f= 1kHz)

30

dB

VS-3(RMS)

Oscillator voltage (Pin 5) RMS value
Vanatlon of oscillator frequency

250

mV

t.fosc/ t.Cp
t.losc/ t. T

with supply voltage (t.Vcc = 1V)
with temperature

5
0.2

kHzlV
kHz! °c

S+300
S-300

Selectivity (without modulation;
Test CirCUit, Figure 7)

30
46

dB
dB

± t.fRF

AFC range

160

kHz

± t.fRF

Mute range

120

kHz

BW

Audio bandwidth at t.Vo = 3dB
measured with pre-emphasIs (t = 5OflS)

10

kHz

VO(RMS)

AF output voltage (RMS value) at
RL (Pin 14) = 100Q; Pin 16 open

90

mV

10(DC)
10(AC)

AF output current
MAX. DC load
MAX. AC load for THD = 10%; peak value

AC ELECTRICAL CHARACTERISTICS
(STEREO OPERATION)

-100

+100
3

f.I.A
mA

vcc = 3V,

TA = 25°C; measured In Figure 6, fRF = 96MHz modulated with pilot
t.f = ± 6.75kHz and AF signal t.f = ± 22.5kHz; fM = 1kHz; EMF = 1mV (EMF voltage
at a source impedance of 75Q); RMS nOise voltage measured unweighted
(f = 300Hz to 20kHz), unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

EMF

Sensitivity (Figure 2) (EMF voltage) lor SIN = 46dB

SIN

Signal-to-nOise ratio

(X

Channel separation

VPILOT

Pilot voltage level at Pin 14

VAF(RMS)
S+300
S-300

December 1988

Typ

Max

300

flV

53

dB

20

dB

135

mV

AF level at output

80

mV

Selectivity
without modulation (test cirCUit Figure 6)

22
40

dB
dB

7-84

Preliminary Specification

Signetics Unear Products

TDA7021

Single-Chip FM Radio Circuit

/"

3

o
VCC(V)

Figure 1. Supply Current as a Function of the Supply Voltage

0.20
0.18
0.18

"-

0.14

:E
~
g~

0.12
0.10
0.08

\.

0.08
D.04

0.02

o

-

10-1

10 •

10-3

10-1

EMF (V)

FIgure 2. Field Strength Voltage (V9.3) at Rs = 1k!l ; f

20

-20

~

~ -40

II
~1

t

2

~

7 r--..

a
10
NOISE

-60

nlDI
EMF (V) AT

lis = 751!

NOTES;
Condlbans' 0 dB - 1 OOmV, fRF "" 96MHz,
for S + N curve af"" ± 225kHz. 'M 1kHz
for THO curve .af - ± 75kHz, 1M "" 1kHz
AF output voltage (Vo) and total harmonIC distortion (THO) as a funct1Of1 of the EMF Input v~tage (EMF) With a source
onpedance (Rs) of 7Sn (1) Muting system enabled. (2) MutIng system dlssbled

=

Figure 3. MONO Operation

December 1988

and Supply Voltage Is 3V

S+N

-2

iii

= 96.7SMHz

7-85

~

•

Signetics Linear Products

Preliminary Specification

TDA7021

Single-Chip FM Radio Circuit

10

S+N
-10
-20

~.

,...A

-30

I

-40

>0

-so

......
NOISE

-so
-70

-so
-90
10-6
EMF (V) AT R.

= 750

NOTE:
AF output Voltage (Vo) as a functlon of the EMF Input voltage (EMF) (1) Muting system enabled; (2) mUbng system disabled

Figure 4. STEREO Operation

FlELO STRENGTH

~~o---------------------~

10

TOA7021T

+V~o-~~--

____

~

__

~~

________

~~

__

~~

__-'____-J

NOTE:
1 The AF output can be decreased by 5dB by d,sconnecbon of the l00nF capacrtor Of Pin 16

Figure 5. Test Circuit for MONO Operation

December 1988

7-86

Signetics Linear Products

Preliminary Specification

Single-Chip FM Radio Circuit

TDA7021

FIELD STRENGTH

L
R

270pf

'4

.5

'0

lOA702.T

+v~o-~---------~------~------------~~---~~---~---~

Figure 6. Test Circuit for STEREO Operation

.-

11

IN

lOA702.T

UM

!....--II--

Vee

~~ ~GENERATDR

RtS

r

Setup With Cirellitry' as Fagure 5 or FIgUre 6
(100nF) deleted end replaced by R6 - 'OOk{l. V, - 3OmV: I, - 76kHz.
Output: seIecbve voftmeter; R,;;'.M!l; c," BpF: 10 - I,

Co

Va I (3OOkHz - IJ
Va II,

8..301) - 20Log

Va I(300kHz + IJ

Volf.

Figure 7. Test Circuit

December 1988

(~~:
TCl2651S

NOTES:

S. 300 - 2Oeog

.-

7-87

•

TEA5560

Signetics

FMjlF System
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TEA5560 is a monolithic integrated
FM/IF system circuit. intended for car
radios and home receivers equipped
with a ratio detector.

• A three-stage IF limiting amplifier
• A 15dB field strength-dependent
muting circuit
• A field strength-dependent DC
voltage, for:
- mono/stereo switching
- channel separation control of a
stereo decoder
- an indicator (IMAX 1mA)
• Standby ON/OFF switching circuit
• A voltage stabilizer for the
internal circuit current and an
external current up to 15mA
• Adjustable gain (~G = 15dB)

U Package
1 IF INPUT
2 DC FEEDBACK
3 DC FEEDBACK
4 LEVEL DETECTOR

5 STANDBY INPUT

«

8 VOLTAGE STABILIZER

TOP VIEW

APPLICATIONS
• Home receivers
• Car radios

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-PIn Plastic SIP (SOT-142)

-30'C to + 85'C

TEA5560U

ABSOLUTE MAXIMUM RATINGS
RATING

UNITS

V7-9

Supply voltages
Pin 6
Pin 7

DESCRIPTION

24
24

V
V

V4- 9

Voltage at Pin 4

6

V

VS-9

Voltage at Pin 5

9

V

-18SM

Non-repetitive peak output current (Pin 8)

100

mA

SYMBOL
VCC~V6-9

PTOT

Total power diSSipation

TSTG

Storage temperature range

TA

Operating ambient temperature range

()JA

Thermal resistance from junction to
ambient (in Iree-alr)

November 14. 1986

1000

mW

-65 to + 150

'C

-30 to +85

'C

75

'C/W

7-88

853-0983 86551

Product Specification

Signetics Linear Products

TEA5560

FMjlF System

BLOCK DIAGRAM
+Ycc
8

1st IF
AJlPUFIER

AJlPUFIER
Y,

j
..... v

....

1

IF

~

~r

~

I-

INPUT

~

3nlIF

2nd IF

AJlPUFIER

~rY'

7

~

IF

0U11'UT

(V~

MUTING

Y2

Y2

.".

.".

2

Uk

3

Uk

DC
FEEDBACK

8

2.7k
.".

*

~I

2.7k
.".

==
ID~I

+

Y,

~

t
lEM4IIO

J

--~l~'_-

(~

r~

s;:

10

5

Y,,.J

Sl'ANDBY

INPUT
Uk

Y2

•

u
VOIl'AGE
SI'ABILIZER

.".

4

DCOU11'UT
(LEVEL DETECtOR)

'0'''....

November 14, 1986

7-89

Signetics Linear Products

Product Specification

TEA5560

FMjlF System

DC ELECTRICAL CHARACTERISTICS Vcc = 14.4V; TA = 25°C; measured in Figure 1, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Supply voltage 1

10.2

14.4

18.0

V

at
at
at
at
at
at

7.5

8.0
200

8.5
300
1.0
200
100

V
mV
V
mV
mV
V

30

mA

15

mA

Supply (Pin 6)

Vee = VS_9
Voltages

VS_9

tNS-9
;lVa_9
V4 _9
V1• 2. 3-9

Pin 8;-ls=02
Pin 8 when - 18 increases from 0 to 15mA
Pin 8 when Vee reduces from 14.4V to 10.2V
Pin 8 when Vee increases from 14.4V to 18.0V
Pin 4 (level detector)
Pins 1, 2 and 3

2.4

Currents

ITOT

Total supply current; - la = 0

-Is

Current supplied from Pin 8

IS8

Stand-by current; V5 _ 9 = 0

15

Current into Pin 5

'7

Current into Pin 7

15

20

8

11

14

mA

1.0

1.5

2.0

mA

3.0

mA

300

mW

Power consumption

Pe

-18 =0

NOTES:
1. A stabilized supply voltage of 7 to 9V can also be applied at Pins 5 and 6 (linked); for thiS applicatIOn Pin 8 must not be connected.
2. The temperature coefficient of the stabilized voltage at Pin 8 is typically - 2.3mVre.

November 14, 1986

7-90

Product Specification

Signetics Linear Products

TEA5560

FM/IF System

AC ELECTRICAL CHARACTERISTICS

Vcc=14.4V; TA = 25°C; V,=1mV; fo=10.7MHz; 6.f= ±22.5kHz; fM=1kHz, unless
otherwise specified.
LIMITS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

105

150

210

40

45
65
78
80

dB
dB
dB
dB

IF part and ratio detector
Sensitivity
at - 3dB before limiting (Pin 1);
(Without muting) 1

I1V

SIN
SIN
SIN
SIN

Signal-to-nolse S+ NIS measured
a bandwidth of 60Hz to 15kHz
at V, = 20l1V
at V, = 15Ol1V
at V, = 1mV
at V, = 10mV

Vo
Vo

AF output voltage
6.f = ± 22.5kHz
6.f = ± 75kHz

200
600

mV
mV

THO
THO

Total harmonic distortion
6.1 = ± 22.5kHz
6.f = ± 75kHz

0.3
2.0

%
%

AMS
AMS
AMS

AM suppression
fM = 1kHz; m = 0.3 (for AM)
fM = 70kHz; 6.f = ± 22.5kHz (for FM)
at V, = 15Ol1V
at V, = 1mV
at V, = 10mV

40
50
55

dB
dB
dB

1.9
2.8
3.5
5.0
5.7

V
V
V
V
V

15

dB

In

Level detector circuit
V4-9
V4-9
V4 - 9
V4- 9
V4-9

OC output voltage (Pin 4)
at V, = 2OOl1V
at V, = 500l1V
at V, = 1mV
at V, = 3mV
at V, = 10mV

Muting circuit (see also Figure 4)


SIGNAL

!4.7nF t-1k_.,.=~=:::-.,

Catalog number of detector colis
L1 3122 138 20211 (TOKO 85ACS-4238A)
L2 3122 138 20212 (TOKO 85ACS·4260SEJ)
FM Front-end ALPS MMK11E11

NOTES:
1 Stereo application 220pF

2 Stereo application 390pF

Figure 4. FM Channel for (Car) Radios Using the TEA5560 and a Ratio Detector With AA119 Germanium Diodes

November 14, 1986

7-93

Signetics Linear Products

Product Specification

TEA5560

FMjlF System

o

S+N

_Ill.

'r7

-20 c;;,

..:::

3

lQ

ui!:
-80

N

\

1.5

-80
THD

-100

1

0.5

10

NOTES:

1. Wrthout mubng
2. With muting.
3. Reference level OdB "" 2OOmV. and the total hannonlc distortIOn (THO) as a function of the aenal Input voltage
(V,). Measured In Appilcabon Qrcult
.6.f - ± 225kHz, 1M - 1kHz

FIgUre 6 at

Figure 5. Signal and Noise (S + N) and Noise (N)

./

/

/'

4

2

o

/'

1

10

NOTE:
Measured In Appllcatton Circuit Figure 4

Figure 6. Level Detector DC Output Voltage (Pin 4) as a Function of the Aerial Input Voltage

November 14. 1986

7-94

Signetics Linear Products

Product Specification

FMjlF System

TEA5560

~~~~~4r--~~
I
I
I
I
I

-----------------------------~

"Fe

!unF +--1k_~=~=,...,

Catalog number of detector colis
L1 3122 138 20211 (TOKO 85ACS·4238A)
L2. 3122 138 20212 (TOKO 85ACS-4260SEJ)
F M. Front-end' ALPS MMK11E11

NOTES:
1 Stereo apphcatlon 220pF.
2. Stereo applicatIOn 390pF
3 Further detalled Information on the use of slhcon diodes IS available on request

Figure 7. FM Channel for (Car) Radios Using the TEA5560 and a Ratio Detector With BA281 Silicon Diodes

s:;'N
./

-20

/

~s(m'=H

iit- 4O

N

-:? -80

Ti"i=
~/~ I

-80

WI
-

10 1

Ji

I I

MUTING Nor POSSIBLE

:s

-100

ILIIII
11111111

~

±7SkHz
±22.5kHz

--

10
V,~V)

NOTE:
Reference level OdS - 245mV, AM Suppression (AMS) and Total Harmonic Distortion (THD) as a function of the
aerial Input voltage (VI)' Measured In Apphcatlon Circuit Figure 7
at ~f = ± 22.5kHz, 1M "" 1kHz, for AM suppression m z> 0 3, ,:,\1::: ± 225kHz

Figure 8. Signal and Noise (S + N) and NOise (N)

November 14, 1986

7-95

i

Q

...
%

..,.o

•

TDA1578A

Signetics

PLL Stereo Decoder
Product Specification

Linear Products
DESCRIPTION
The TDA157BA is a PLL stereo decoder
based on the time-division multiplex principle.

FEATURES
• Adjustable input and output
voltage levels
• Automatic mono/stereo switching
with hysteresis, controlled by
both pilot signal and field
strength level
• Analog control of mono/stereo
changeover

•
•
•
•

Pilot indicator driver
Analog muting control
Muting indicator driver
Oscillator with decoupled
frequency measurement output
• Electronic smoothing of the
supply voltage

PIN CONFIGURATION
N Package
LEFT
FEEDBACK
RIGHT
FEEDBACK
RIGHT OUT
VCOINI
MODE SEL

LEFT OUT
MODESEL
PHASE
DETOUT

INPUT

APPLICATION

COMP

• PLL decoder

veo COMP
VCO

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

18-Pin Plastic DIP

+70°C

ORDER CODE
TDA1578AN

Pl.L ALTER

NOTE:
Values given In parentheses are for Vee = 8 5V

Block Diagram With External Components; Used as Test Circuit

November 14, 1986

7-96

853-0971 86551

Product Specification

Signetlcs Linear Products

TDA1578A

Pll Stereo Decoder

ABSOLUTE MAXIMUM RATINGS
~~~"~---

SYMBOL

PARAMETER

Vcc

Supply voltage (Pin 8)

Y,N

Input voltages (Pms 3, 4 and 5)

VOUT

Indicator driver output voltage

RATING

UNITS

20

V

o to

V

12

"-

24

V
mA

lOUT

Indicator dnver output current

30

Po

Total power dissipation at T A = 25°C

12

W

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range

-30 to +80

°C

eCA

Thermal resistance from crystal to
ambient

--

~-"-

-"~

°C/W

80
~-

DC ELECTRICAL CHARACTERISTICS

----~

Input signal m = 100% (Ilf = ± 75kHz), pilot signal m = 9% (Ill = ±6 75kHz)"
Modulation frequency 1kHz, V3~5 = V4~5 = OV,
De-emphasIzing time t = SOilS, oscillator adjusted to fose at a pilot voltage V, = OV,
TA = 25°C, unless otherwise specified
-~-----

SYMBOL

Vee
(V)

PARAMETER

LIMITS
'--"-

Typ

Min

UNIT

Max
I--~---

Vee

75

Supply voltage range (Pin 8)

R5

18
~-

Icc
Icc

Supply current (except
output and Indicator) Pin 8

VMUX(P-P)
VMUX(P"P)

Nominal multiplex Input
voltage (peak-to-peak value)
R, = 47kr!

21
30

8"5
15

40

-.-~

-

V
- ------,mA
mA
---"

05
LO

85
15
~---

Overdrive reserve of Input
at THD= 1%
at THD = 0 3%
VO(RMS)
VO(RMS)
VO(RMS)
VO(RMS)

A> "0,,",

."m,. "M'

'000,

R15~18 = R16~17 = 15kr!

m~ ~"""' .,mJ]

R15~18 = R16~17 = 24kr!

8"5
15

-~----

6
6

3
3

----

dB
dB
- - ---------

075
15
L2
24

85
15
85
15

V
V
~-~ --"-~---

V
V
V
V
""-

Overdrive reserve of output 1
R15~18 = R16~17 = 24kr!

3

dB

"---""

± IlVoNo

Spread In output voltage levels 1

1

dB

± IlV15~ 16NO

Difference of output voltage levels 1

1

dB

----"

-""

Ro

Output resistance 1

±Io

Available output current Pins 15 and 161

V15,16~ 7

Modulation range at output (unloaded) 1

low-ohmiC
I---"-~-

mA
"-

1 to

10

Internal current limiting 1

V15,16~7
V15,16~ 7

DC output voltage
R15~18 = R16~17 = 24kr!

85
15

-117,18
-117,18

DC current
(Pins 17 and 18)

85
15

ex
ex

Channel separation
at V4~5=OV

V9~7-1

V

15
36
7"0

41
7"7

rnA
46
8,4

33
23

--

V
V

IlA
IlA

"--

--

85
15

32
39

dB
dB

50
50

THD
THD

Total harmonic distortion

85
15

0"1
004

SIN
SIN

Signal-to-noise ratio
f = 20Hz to 16kHz

8"5
15

87
90

03
01

%
%
~---

dB
dB
"----~-

November 14, 1986

7-97

•

Signetics Linear Products

Product Specification

PLL Stereo Decoder

TDA1578A

DC ELECTRICAL CHARACTERISTICS (Continued) Input signal: m = 100% (AI = ± 75kHz); pilot signal: m = 9%
(AI = ± 6.75kHz); Modulation Irequency: 1kHz; V3-S = V4-S = OV;
De·emphaslzlng time: t = 50j.ls; OSCillator adjusted to lose at a pilot
voltage VI = OV; TA = 25°C, unless otherwise specified.
SYMBOL

19
38
O:S7
0:76
0:
0:

0:
0:

2
2

3

0:

Vee
(V)

PARAMETER

Carrier and harmonic suppression at the output
pilot signal; I = t 9kHz1
subcarrier; I = 38kHz 1
1= 57kHz 1
1= 76kHz 1
Intermodulatlon 1
1M = 10kHz;
spurious signal Is = 1kHz
PLL·lilter Figure 11
PLL·lilter Figure 21
1M = 13kHz;
SPUriOUS signal Is = 1kHz 1
traffic radio (VWF)2;
1= 57kHz 1

LIMITS
UNIT
Min

40

Typ

Max

32
50
46
60

dB
dB
dB
dB

50
70

dB
dB

75

dB

70

dB

SCA (Subsidiary Communications Authorization);
1= 67kHz4,1

70

dB

a 190

ACI (Adjacent Channel Interference)3
1= 114kHzl
1= 190kHz1

80
52

dB
dB

RRtOO

Ripple rejection at the output; I = 100Hz;
VeC(RMS)= 100mV (Pin 8)1

43

dB

V9_7

Voltage on Iilter capacitor without external load 1

R9_8

Source resistance 1

O:S7(VWF)
67

0:

0:: 114

40

V

Vcc- 0.25
6

8

10

kn

30
61

6
12

21
43
15
30

mV
mV
mV
mV

Mono/stereo control

VI(P_P)
VI(P_P)
VI(P_P)
VI(P_P)

Pilot threshold voltages (peak·to·peak values)
lor stereo 'ON'
lor mono 'ON'

8.5
15
8.5
15

AVI

Switch hysteresIs
VIONIVIOFF 1

3

dB

tSTON
tMON

Switching time at C14 _ 7 = 0.22j.lF
lor stereo 'ON'I
lor mono 'ON'I

15
27

ms
ms

External mono/stereo controlS (see Figure 12)

V14-7
V14-7
or: -V4_S1

Sw~ching

-V4 _ 5

Control voltage lor channel separation:

voltage lor
external mono control

8.5
15
315

-V4- 5
AV4_S1
-V4- 5
-V4- 5
-V4- 5
-V4- 5
-V4-5
-V4- 5
AV 4 _7

November 14, 1986

0.7
1.4

0:

= 6dB

8.5
15

120
130

0:

= 26dB

8.5
15

70
80

mV
mV
mV
mV
mV

8.5
15
8.5
15

240
270
220
250

mV
mV
mV
mV

±20

Control voltage
lor mono 'ON'
lor stereo 'ON'
Control voltage difference lor

0:

V
V
mV

= 6dB; stereo 'ON'

7·98

8.5

80

100

120

mV

Signetics Linear Products

Product Specification

Pll Stereo Decoder

TDA1578A

DC ELECTRICAL CHARACTERISTICS (Continued)

Input signal: m ~ 100% (Af ~ ±75kHz); pilot signal: m ~ 9%
(Af ~ ± 6.75kHz); Modulation frequency' 1kHz; V3-S ~ V4 -S ~ OV;
De-emphasizing time. t ~ 501lS; oscillator adjusted to fosc at a pilot
voltage V, ~ OV; TA ~ 25'C, unless otherwise specified.
Vee
(V)

PARAMETER

SYMBOL

LIMITS
UNIT
Min

Typ

Max

Muting circuitS (see Figure 13)
-V3_S
-V3-S
AV3_s '
-V3-S
-V3-S

Control voltage for an
attenuation: a: ~ 3dB

a:

~

140
145
±20
255
270

8.5
15

26dB

8.5
15

Attenuation
with V3 - S ~ OV'
with -V3-S ~ 450mV'

a:
a:

I,

LED driver output current at an attenuation:

-V3_S
-V3-S

Control voltage
for I, ~ 200J.lA

mV
mV
mV
mV
mV
0.2

dB
dB

2.2

rnA

80
0:

~ 3dB'

1.2
8.5
15

1.7

mV
mV

150
160

Control inputs
V3,4,5-7

Recommended voltage range'

4

V

13,4,S

Input bias current'

0
10

100

nA

Output saturation voltages
at I, ~ 20mA; V3-S ~ OV'
at 12 ~ 20mA'

1.2
0.5

1.8
1

V
V

Indicator driver
V, -7SAT
V2-7SAT

Output leakage current
at V,,2_7 ~ 24V'

20

IIA

fose

OSCillator frequency adjustable with R,o-7'

76

kHz

fose

Spread of free-running frequency at nominal external
circUitry'

TC
Afosel AVec

Free-running frequency6 dependency
with temperature'
with supply voltage'

Aflf

Capture and holding range for a pilot Input voltage
VPIL ~ 0.5 X VPIL NOM'

STaT

PLL control slope (total)'

V lO _ 7

DC voltage at Pin 10'

1,.2
VCO

71

1 X 10- 4

or:

±2

82

kHz

400

'C-,
HzlV
%

4.5

kHz/IIS

2.1
3.2VSE

V
V
V
V

V4-7
or:

Frequency measuring POint; internal SWitching threshold'

6
9VSE

V4_7(P_P)

Output voltage (peak-to-peak value) at Pin 4; R ~4.7kQ'

350

mV

R4_7

Output resistance'

5

kQ

NOTES:

VcC-85 or '5V
Intermodulatlon suppression (BFC Beat-Frequency Components)
"'2 ~

Vo(signal) (at 'kHz)
Vo(spunous) (at 1kHz)

;

fs - (2 x ,OkHz) -19kHz

,

fs - (3 X 13kHz) -38kHz

Vo(slgnal) (at 1kHz)
"'3 -

Vo(spunous) (at 1kHz)

measured With 91 % mono Signal, fM = 10 or 13kHz, 9% pilot Signal

November 14, 1986

7-99

•

Signetlcs Linear Products

Product

Pll Stereo Decoder

Spec~ication

TDA1578A

3. Traffic radio (VWF) suppression
Vo(signal) (at 1kHz)

"'57CVWF) =,-,---'-....':..-:-----,..,.,...,
Vo(spurious) (at 1kHz ± 23kHz)

measured with: 91 % stereo signal; fM
4. ACI (Adjacent Channel Interference)
"'114

Vo(signal) (at 1kHz)
(at 4kHzi fs

= Vo(spurious)

""90 =

Vo(signal) (at 1kHz)
Vo(spurious) (at 4kHz)

= 1kHz;

= 110kHz - (3

9% pilot Signal; 5% traffic subcarrier (f = 57Hz, fM = 23Hz AM, m = 60%).

X 38kHz)

; fs = 186kHz - (5 X 38kHz)

measured w~h: 90% mono signal; fM = 1kHz; 9% pilot signal; 1% spurious signal (fs= 110 or 186kHz, unmodulated).
5. SCA (Subsidiary Communicabon Authorization)
"'67

=

Vo(signal) (at 1kHz)
Vo(sPUrious) (at 9kHz)

; fs = (2

X 38kHz) - 67kHz)

measured with: 81% mono signal; fM= 1kHz; 9% pilot Signal; 10% SCA·subcarrier (fs = 67kHz, unmodulated).
kXT
6. Assuming VT = - - = 28.6mV at TJ = 330·C

q

7. The effects of external components are not taken into account.

APPLICATION NOTES
1. When mono/stereo control and muting control are not used, Pins 3, 4 and 5 have to be grounded,
2. In
a.
b.
c.

a receiver, channel separation adjustment can be obtained by:
A capacitor at Pin 12 (C,2-7): phasing 19/38kHz
RC or LCR filter at the input: frequency response compensation (VG = f(w»
Feeding the output signals of the output amplifier to the inputs of the other channel.

3. PLL·fllter for reduced intermodulation (0:2); see Figure 2.
4. External mono 'ON' switch; see Figure 3.
5. Switching 'OFF' the oscillator; see Figure 4.

4

14

47k

V_ _.....M - .
13

10

681<

1S01e

-

11

100
39k

10k
TC129

1 l J,.
33nF

o.331'F

2nF
-:;-

Figure 1, PLL·filter for 0:2

November 14, 1986

110k

1~~

JuONO
ION

S

. [ 10k

I

J430pF

-:;-

a, At Pin 4; -V4-5 300mV

=70dB at Vee =15V

Figure 2

7·100

b. At Pin 14

Signetics Linear Products

Product Specification

PLL Stereo Decoder

TDA1578A

13

10

1

220k
(470k)
39 (75)k

G~ tiD
Vee

10(22)k

;1

= 15V (8.5V)

{FM
ON
TC129l0S

NOTE:
The oscillator IS sWitched off when
ID100~A (> 50.uA for Vee = 8 5V) and 10 < 1mA

Figure 3

30

40

/

V

/

30

/

/

/
/

/'

20

/
10

o

/

1/
10
Vee (V)

10

o

20

Figure 4. Signal Handling Range at the Input for ISNOM
(± 75kHz); Vg.7 = Vee

20

10
Vee (V)

Figure 5. Supply Current Consumption at V9-7

100

0.3

I/~ON~

50

o
o

/LJ)=O

o. 1
........

I'-.....

L= -R

/

.......

. . .V
10

10

0

20

•

I

0.2

........

= Vee

Vee (V)

,/

-'

20

.V "I

.~'

:.....

30

-+-NOM.

40

50

(±75kotz)
l6(p-p)(j.A)

Figure 7. Total Harmonic Distortion (THO) as a Function of
the Peak-to-Peak Input Current at Pin 6; Vee = 15V;
fM 1kHz; V3-5 V4- 5 OV

Figure 6. DC Current in the Feedback
Loop of the Output Amplifier

November 14, 1986

=

7·101

=

=

Signetics Linear Products

Product Specification

TDA1578A

PLL Stereo Decoder

0.'
0.3

l0

0.2

i!:
0.1

o

0.1

:::-

'-

10
'M(kHz)

fU(kHz)

NOTES,
_ _ Mono
- - - Stereo: L = - A, 91 % + 9% pilot signal
Vee = 15V
Is(p_p) c 21 SpA

Figure 9. Channel Separation (

e

14

I

12

~

w

i:i
~

t0

~

0:

16

./

LAMP ON

I

..'"
I>
..

2

w
0:

10

w

8 '---., ::::::::..LAMP OFF

0:
~

6

0
-2

, .J.
TA= _40°C

.." ~.....

~

u -4

4

'/"

~

~'~

-'

40

80

80

100

10

20

30

40

+ 85°C

~

..:i!

I

I
+8S C

w

In

o

50

~

w

80

.,."""'"

0 .......

7-121

.....
z

+25°C~i~
0

40 60

80 100

0"'''''

80

TA = 25°C

70

V=12V
'=1kHz

I

PILOT LEVEL - mVrms

TEMPERATURE - ·C

November 14, 1966

J..--:::f.--

_~_

-8
20

20

Channel Separation vs
Oscillator Free-Running
Frequency Error

_40°C ....... ~_

-6

2

0

TEMPERATURE - ·C

+25·C;-1~

: I- Vl'2V
4

z

0

-80 -40-20

OP08UOS

.

V

0
-40 -20

0

Capture Ranges VB
Pilot Level

..l--

........

-15

INPUT LEVEL - mVrms

Lamp Turn-on & Turn-Off
Sensitivity vs Ambient
Temperature

I

-

U -2.0
O>

OP0931OS

18 -v'=12J

-0.5

j

./

AUDIO FREQUENCY - Hz

20

0

...

0:
0 -1.0
t-

./

0

r-vL,J

0.5

~

0:

~

t0
t-

1.0

aw

0

10

1.5

0:
0:

w
>
u
zw

:IE

z

20

0:

0

Z

20

..
I

r- TA=2S0C
V=12V
r- L=R
PILOT OFF

C
u O'

Z

u

08

I

C~Jt."
IIIV

I
z 40

Oscillator Free-Running
Frequency Error vs Ambient
Temperature

Harmonic Distortion vs
Input Level

80
60

40

'\.

/

30

z
z
c

20

-

-

u

10

-

-

'"

0
-2.0

INPUT SIGNAL,. 30mVrms
MULTIPLEX SIGNAL
(L-1, R-o, PILOT OFF) =
150mVrml

-1.0

0

1.0

2.0

OSCILLATOR FREE RUNNING
FREQUENCY ERROR - %
0 .......

•

Signetics Unear Products

Product Specification

FM Stereo Multiplex Decoder, Phase-locked loop

#JA758

TEST CIRCUIT AND TYPICAL APPLICATION
v+. +12V

COMPOSITE
MULTIPLEX

UNIT

"'-4---111---1---1

".

21 kn
LED

STEREO
INDICATOR
LAMP

".

SkU

OSCILLATOR
AD'

LEFT
OUTPUT

':"~T --+--------1

(TOPVIEWI

NOTE:
Toterance on reSistors IS ±5% and tolerance on capacitors IS ±20%. unless othel'Wlse sp8Clfled C, tolerance-+100%, -20%,

Os tolerance=±1%

±5% In typical appIlcabons R3 tolerance"'±1%, R4 tolerance-±10%, R, and R2 tolerance=±1% In Test CIrcuit and ±5% In TYPIcal AppltC8tlOn

November 14, 1986

7-122

In

test Circuit and

AN191

Signetics

Stereo Decoder Applications
Using the IlA758
Application Note
Linear Products

INTRODUCTION
The phase-locked loop (PLL) has been used
for many years In consumer equipment Due
to the nature of FM Stereo Multiplex Systems,
where prime Importance IS the channel separation, discrete systems lacked the tracking
ability over wide temperature and voltage
ranges to be done economically.
The development of the monolithic PLL and
Improvements In IC processing have made
the Phase-Locked Loop FM Stereo Multiplexer Decoder a reality

MAJOR ADVANTAGES
The economiC advantages In uSing the PLL
multiplex decoding system are not only cost
reduction, by eliminating peripheral components, but the man-hour cost reduction by
eliminating turning COils, thereby eliminating
tediOUS alignment procedures
The cost advantages are extremely Significant and are In addition to the follOWing.
• 45dB channel separation
• Automatic stereo/mono SWitching
• Stereo indicator lamp driver With current
limiting
• High Impedance Input outputs

low Impedance

• 70dB SCA reJeclion (subSidiary carner
authOrization)
• One adjustment for complete alignment
• 10V to 16V supply voltage range

FM STEREO MULTIPLEX
SUBCARRIER AND PILOT
The two (2) baSIC Signals differentiating an
FM stereo multiplex Signal from an FM mon-

December 1988

aural Signal are the 19kHz pilot and the
38kHz subcarner. The frequency and phase
relationship of these Signals is well defined.

MA 758 IS SUitable for all line-operated and
automotive FM Stereo Receivers.

Earlier systems had to reconstruct the 38kHz
subcarner by uSing the 19kHz pilot. ThiS
system reqUired frequency multipliers and
selective filters (COils). Since maximum channel separation IS directly related to proper
phaSing, alignment procedures were extremely Critical and therefore expensive In addition,
long-term stability and performance were degraded due to component aging, and temperature

REFERENCING THE BLOCK
DIAGRAM

Use of the PLL as the multiplex decoder
eliminated these shortcomings since the
phase accuracy of the 38kHz Signal IS limited
only by the loop gain of the system and the
free-running OSCillator stability. Both of these
parameters are eaSily controlled, proViding
easy, rapid adjustment and excellent longterm stability

GENERAL DESCRIPTION
The MA758 IS a monolithiC Phase-Locked
Loop FM Stereo Multiplex decoder uSing the
16-lead DIP N package ThiS Integrated CirCUit
decodes an FM Stereo Multiplex Signal Into
Right and Left audiO channels while Inherently suppressing SCA Informallon when It IS
contained In the composite Input Signal Internal functions Include automatic mono-stereo
mode SWitching and drive for an external
lamp to Indicate stereo mode operallon.
The )1A 758 operates over a Wide supply
voltage range and uses a low number of
external components. It has only one control
to adjust a potentiometer to set OSCillator
frequency. No external COils are reqUired. The

7-123

The upper row of blocks comprises the PLL
which regenerates the 38kHz subcarrier, necessary for multiplex Signal demodulation. The
baSIC 76kHz generator IS voltage-controlled,
and IS diVided by two to insure a 50% duty
cycle 38kHz Internally-generated signal. ThiS
symmetry IS necessary for maximum left/right
channel separation and SCA rejection (bandcentered at 67kHz). DIViding the 38kHz by
two generates the 19kHz Signal necessary to
lock on to the Incoming pilot signal. A second
19kHz Signal IS generated which IS in quadrature to the first Internally-generated 19kHz
Signal and In phase With the pilot. ThiS second 19kHz is mixed In a quadrature (synchronous) phase detector to operate the stereo
SWitch and lamp driver circUity.
When a stereo Signal is present, the stereo
SWitch enables the stereo demodulator, and
when a stereo Signal IS not present, the
demodulator IS disabled, allOWing the system
to reach optimum nOise performance.

FUNCTIONAL OPERATION
To aid In understanding the system operallOn,
the MA758 eqUivalent CIrCUit has been broken
down Into subsections as follows (see Figure
2):

III
IV
V
VI

Buffer Amplifier and Bias Supplies
Demodulator
Stereo SWitch and Lamp Driver
VOltage-Controlled Oscillator
Frequency D,v,ders
Pilot Phase and Amplitude Detectors

•

li?

en

g

CD

3

~

CD
0

~

'"

0

CD
0

y.

r
DETECTOR
INPUT

__ L

SWITCH FILTER

10

LOOP FILTER

14

0
0.
CD

OSCILLATOR RC NETWORK

y.

~

::J

~

o·

'"r

5·

Q
."

0
a.
c

()

.

I

~~~

II

1

-:

'-'~L

I - - - i - - =~ANNEL

1

I

' - - _.........

1

-1

--- QILEFT CHANNEL

I4

OUTPUT
BUFFER

191

0

50
40
30

165

20

18.
10M

10

"

r:::~~~::=====l====~~
b

90

I

lila

150

'\I
10k

Ay.l000
Vcc ... l2V

20

30

105

\

FREQUENCY -

40
30

15

90

'\

10

~

./

50

10

45

30

\ '--

Voltage Gain vs Supply Voltage

,\GAIN

,

1

/

/

FREQUENCY -

'\.

o
1M

70

Hz

PHASE

60

z
;;:

10

Hz

lOOk

60

'\

70

20

lOOk

"

10.

1k

"'" '\ "'-

90

10k

%

Gain and Phase Response
120

100

lk

V

...B
10

FREQUENCY -

110

FREQUENCY -

~

z
z
c

SOdB""

0.1

,.-r--,--,--,--,--.,

100

.

"'- V/

0.3
0.'

PSRR vs Frequency

~

NAB EQUIVALENT

0.4

.5

l'

~

z

SUPPLY VOLTAGE - V

10

..
i ..

VcC=12V

0.5

Iiia

/

18

Channel Separation

0.•

0

14

90

0.7

",.0

I

12

SUPPLY VOLTAGE -

0.1

-#
I

o

120

10

0.0

/

15

75
·C

% Distortion

L

10

____
50

TEMPERATUAE -

Hz

/

______
25

100M

Peak-to-Peak Output Voltage
Swing vs Vcc

V

...- r--

> 105 ~------~-----~~-----i

\
lOOk

-

10

.1l

o

\

10k

1

~

\

- r--

11

I

14

>

"

115 ~------~----~~-----1

_

.

20

~

~

Vcc vs Icc
13

r-----~-------r-----,

~

"z

Gain vs Temperature
120

Vcc- 24V,AV· 1OOO
< 1" DISTORTION _

~

>
I

10

15

25

20

SUPPLY VOLTAGE -

V

•

Signetics Linear Products

Product Specification

Dual low-Noise Preamplifier

NE542

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Noise Voltage vs Frequency

Noise Current vs Frequency

16
NOTE: Rs

NOTE, Rs=O

,.
12
:J:

~

10

Pulse Response

=SOk

AV=10

0.8

~

I""

~0-

r'--

z

0.6

I
~

>

0.'

"'" rr-..

0.2

100

1k
FREQUENCY -

10k

100

Hz

'1k
FREQUENCY -

1\

\
\
-1
-20 -10.

10k

0

10 20

Hz

TIME
OP100SOS

TYPICAL APPLICATIONS

0.5VRMS

240K

Typical Tape Playback Amplifier

Audio Mixer
Vee = +18V

l2V

!/--r---r-o OUT

+-+--+--...-.-.;

8800pF
elk

Two-Pole Fast Turn-On NAB Tape Preamp

RIAA Magnetic Phono Preamp

NOTE:

All reSistor values are tYPical and In ohms

November 14, 1986

7-134

30

40 50 10 70

-~.

80

Signetics

AN190
Applications of Low Noise
Stereo Amplifiers: NE542
Application Note

Linear Products

Introduction
Stereo preamplifiers have come into greater
and greater demand with the increased usage
of tape recorders. With stereophonic recording systems, the need increased to have
multiple devices In the same package to
insure greater thermal tracking and packing
density. without sacrificing performance.
The NE542 qualifies as a low noise dual
preamplifier. The NE542 is an B-pin dual inline device.
This device has greater than 1OOdB openloop gain and (15 - 20) MHz gain bandwidth
product. In selecting the proper "low noise"
preamplifier, several factors must be considered.
1. Frequency shaping characteristic required.
2. Closed-loop response with respect to a
system reference level.
3. Response of the record/playback head.
4. System distortion requirements.
5. Response of the tape used.

Known as the NAB equalization curve, the
standard deemphasis employs attenuation
from the turnover frequency of 50Hz to the
turnover frequency of 31 BOHz for 7.51ps recording. The slower recording speed of
3.751ps employs turnover frequencies of
50Hz and 1326Hz. These curves are shown
in Figure 1. A reference level of BOOIlV head
sensitivity at 1kHz is also used by the NAB.

STEREO PREAMPLIFICATION
The voltage level appearing at the output of
tape playback heads and some phono cartridges are too small to be useful without a
(72)4 0

(32) 30

~
~

RIAA standards call for a maximum recording
velocity of 21cm/sec for stereo discs. This
worst-case velocity describes a limit for the
preamplifier gain because the input signal at
this velocity is maximum.

NAB TAPE EQUALIZATION
Recording and playback characteristics of
magnetic tape and record/playback heads
are not flat but exhibit a loss at high frequencies and a boost at lower frequencies. To
obtain an overall flat frequency response and
improved signal-to-noise ratio, the audio signals are equalized by boosting the higher
frequencies in amplitude before recording.
Playback amplifiers must exhibit bass boost
to remove the effects of pre-emphasis for an
overall flat response.
December 19BB

50HZ. 3180Hz

\

TIME CONSTANTS

3180,us

, ---\1\

z

($2)

~

so'"
--37SIPS

\

TURN OVEA FREQUENCY

SOHz, 1326Hz
\ ~ IME CONSTANTS
\
3180,us

20

25",

5

5

\

(32) 0

10

_

\\
\1\

(42)10

The following will deal with Items 1, 2, and 4.
When approaching the design criteria of Item
2, the designer should be concerned with the
open-loop device characteristics. These characteristics will aid In determining the maximum boost available, knowing that a specifiC
loop gain (open-loop gain minus closed-loop
gain) will be necessary to keep the system
distortion low and maintain the output impedance of the "low nOise" preamplifier constant
over the required operating frequency range.

7112 IPS
TURN OVER FREOUENCIES

,I--

100

lK

10K

lOOK

FREQUENCY (Hz)
OP03871

Figure 1. Tape Equalization Curves

large amount of low noise preamplification. In
addition to providing low nOise amplification,
the preamplifier should possess enough
open-loop gain so that the RIAA and NAB
equalization curves can be produced in the
feedback networks of the amplifier. The following paragraphs describe the characteristics and applications of the 542. This device
provides a matched pair of amplifiers which
have been specifically designed to minimize
amplifier noise and maximize signal-to-noise
ratio.

NE542 DEVICE DESCRIPTION
The NE542 is a dual low noise amplifier with
104dB open-loop gain produced by two stages of voltage gain followed by one stage of
current gain.
In the design of low noise devices, special
attention must be focused on the input stage.
I! differential topography is used, the stage
should be designed so that one of the differential transistors is turned off. This reduces
the noise contribution by a factor of 1.4 since
only one transistor is producing noise. Current sources and mirrors cannot be used for
biasing loads because active elements will
contribute more nOise.
Implementing these observations, the first
gain stage of the NE542 is pictured with the
complete schematic in Figure 2.

r-----

-----,

I

I
I

I .,
I
I 01
I
I

I
I

I

I

I

I
I
I
I
I
I

I
I

ZI

I

I
L ___ ....L _ _ _
NOTE:
AU resistor values are In

_ _ _ _ _ .l... _ _ _ _ ~

n
Figure 2. Equivalent Schematic NE542

7-135

I
I

•

Signetics Linear Products

Application Note

Applications of low Noise Stereo Amplifiers: NE542

AN190

Although the differential mput configuration
degrades the nOise performance slightly, usmg differential mputs has the advantage of
higher mput Impedance, allowmg smaller capacitors and larger resistors to be used to
achieve the RIAA and NAB curves.

vee

The second stage IS a common-emitter amplifier (05) with a current source load (06)' The
Darlington emitter-follower 03 - 04 provides
level shlftmg and current gam to the commonemitter stage (05) and the output current sink
(0 7 ), The voltage gain of the second stage is
approximately 2000, making the total gain of
the amplifier tYPically 160,000 in the differential mput configuration

el

.,

200K

.4

The preamplifier IS Internally-compensated
With the pole-splitting capacitor, C1. This
compensates to unity gain at 15MHz. The
compensation IS adequate to preserve stability to a closed-loop gam of 10.

Z2

.,

BIASING
The non-mvertlng mput has been internallybiased from a 1 4V Internal voltage source
Followmg the zero differential rule of amplifiers, the output voltage Will be set by the
resistor feedback network (R4 and R5) of
FIgure 3.

NOTE:
All resistor values are In

The base of 02 requires 0.5}1A bIas current.
Hence R5 should pass 5}1A minimum for
Vcc
stabIlIty, for an output DC voltage of the
values of R4 and R5 are:
2
R5

R4

2V SE

= - - = 240kn
10 Is

= (

Vee )
28-1

Max.

(1 )

n
Figure 3. Differential Input Biasing NE542

depIcted by FIgure 4. ResIstors R4 and R5
select the DC gam as defIned by EquatIons 1
and 2. Placing a value of 200k upon R5,
EquatIon 2 Yields a value of 680kn.
The lower corner frequency IS determined
next by the reactance of C4 and R4 such that:

x

R5

(2)

DC amplifIer gam IS defIned by the ratio of R4
and R5. Open-loop AC gam can be regaIned
by addIng a shunt capacItor across R5. The
low frequency 3dB corner IS then defined by
the capaCItor-resistor break pOint.

0.159
f, = C4 R4

(3)

SolVing for C4 Yields a value of 0 0047 }1F.

12V

NAB Tape Preamplifier
DesIgn of a preamplifIer begms by determmmg the gaIn and output Signal amplitudes m
reference to the standard 800}1V input Signal
level. For the followmg desIgn example, we
WIll use the 542 to ach,eve a 100rnV output
level at 1kHz follOWIng the 7.51ps NAB equalIzation curve. The graph of FIgure 1 has been
calibrated both In absolute gam for thIs example and relatIve gaIn for general use.
From the gIven parameters, the closed-loop
gam becomes 32dB at the hIghest frequency
of Interest. The NAB response IS achIeved by
addIng frequency-selectIve AC feedback as

December 1988

.5

4.5

The upper corner frequency, f2' IS similarly
fixed by the reactance of C4 and R7.
0.159
f2 = C4 R7

Then solVing Equation 4 for R7 defines a
value of 11 k.12.
Midband gam IS now fixed by the relationship.
R6 + R7
A=--R6

(5)

SolVing for the 1kHz gain of 42dB uSing 11 k
for R7 yields a value of 88.12 for R6. The final
calculation of the low frequency cut-off of the
preamp determines the sIZe of C2.
0.159
C2=--fCUTOFFR6

II

(4)

(6)

Typical Applications

NOTE:
All reSistor values are

In

n

Figure 4. NAB Response Amplifier

7-136

In addition to the prevIous detailed design
examples, the following general amplifier configurations (see Figures 5 through 8) are
presented. The chOice of design and the
device used IS a functIon of the desired
complexity and overall performance.

Signetics Unear Products

Application Note

Applications of Low Noise Stereo Amplifiers: NE542

AN190

tZv

II

220 •

II

Figure 5. Flat Response Tape Amplifier

...

Figure 6. Two-Pole Fast Turn-On NAB
Type Preamp

>='~"--_-o SVrms
22M

II
NOTE:
All rsStStor values are In

e2K

n

Figure 7. Typical NAB Record
Preamplifier

'SODpf

""",>Os
Figure 8. Typical Tape Playback
Amplifier

•
December 1988

7-137

TDA1029

Signetics

Stereo Audio Switch
Product Specification

Linear Products

DESCRIPTION
The TDA 1029 is a dual operational amplifier (connected as an impedance converter); each amplifier has four mutuallyswitchable inputs which are protected by
clamping diodes. The input currents are
independent of switch position and the
outputs are short-circuit protected.
The device is intended as an electronic
two-channel signal-source switch in AF
amplifiers.

FEATURES
• Four input source/channel
• Clamp diode input protected
• Two channel signal-source switch
APPLICATIONS
• Audio amplifiers
• Preamplifiers
• Graphic equalizers

PIN CONFIGURATION
SIGNAL IN
(Swm:H1)

=~~~
=~~

OUTPUT(n

14

~~~~~

1

=~I~

1

SIGNAL IN
(Swm:H In
SIGNAL IN
(SWITCH In

vee

~N1f.roL

Swm:H
CONTROL
swm:H
CONTROL
BIAS VOLT

SIGNAL IN
9 OUTPUT 01)
(Swm:H In ---.. _ _ _..r-

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-PIn Plastic DIP (SOT-38)

-30·C to +80·C

TDA1029N

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Supply voltage (Pin 14)

23

V

VI
-VI

Input voltage (Pins 1 to 8)

Vee
0.5

V

Vs

SWitch control voltage (Pins 11. 12 and 13)

±II

Input current

SYMBOL
Vee

PARAMETER

o to 23

V

20

mA

-Is

Switch control current

50

mA

PTOT

Total power dlsslpallOn

800

mW

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-30 to +80

·C

December 2. 1986

7-138

853-1046 86702

Product Specification

Signetics Linear Products

TDA1029

Stereo Audio Switch

BLOCK DIAGRAM

10

11

12

13

SIGNAL
OUTPUT

il

14

15

16

SIGNAL
4

3

1

OUTPUT
I

":'

0-

~_uf±::.;.

•
December 2. 1986

7-139

Product Specification

Signetics Linear Products

TDA1029

Stereo Audio Switch

DC AND AC ELECTRICAL CHARACTERISTICS

vee = 20V;

TA = 25°C, unless otherwise specilied.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ
3.5

114

Current consumption without load; 19 = 1,5 = 0

2

Vee

Supply voltage range (Pin 14)

6

Max
5

rnA

23

V

Signal Inputs
VIO

Input offset voltage 01 sWitched-on inputs Rs '" 1kn

2

10

mV

110

Input offset current 01 sWitched-on inputs

20

200

nA

110

Input offset current 01 a sWitched-on input with respect to a
non-swltched-on input 01 a channel

20

200

nA

950

nA

IBIAS

Input bias current Independent 01 sWitch poSItion

250

C

Capacitance between adjacent inputs

0.5

VI

DC input voltage range

SVRR

Supply voltage rejection rallo; Rs '" 1Okn

100

IlVIV

VN(RMS)

EqUivalent input noise voltage
Rs = 0, 1 = 20Hz to 20kHz (RMS value)

3.5

IlV

IN(RMS)

Equivalent Input nOise current
1 = 20Hz to 20kHz (RMS value)

0.05

nA

 33Mn)

December 2, 1986

7-140

V
V

p.A
p.A

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

SWITCH CONTROL
CONTROL VOLTAGES

SWITCHED-ON
INPUTS

INTERCONNECTED PINS

1-1, 11-1
1-2, 11-2
1-3, 11-3
1-4,11-4
1-4,11-4
1-4, 11-4
1-4,11-4
1-3, 11-3

V11-16

V12-16

V13-16

1-15,5-9
2-15,6-9
3-15,7-9
4-15,8-9

H
H
H
L

H
H
L
H

H
L
H
H

4-15,8-9
4-15,8-9
4-15,8-9
3-15,7-9

L
L
L
H

L
H
L
L

H
L
L
L

NOTE:
In the case of offset control, an Internal blocking CircUit of the sWitch control ensures that not more
than one Input will be sWitched on at a time In that case safe switching-through IS obtained at

VSL <1.5V.

APPLICATION INFORMATION Vee = 20V; TA = 25°C; Rs = 47k.Q; CI = 0.1j.lF; RSIAS = 470k.Q; RL = 4.7k.Q; CL = 100pF, unless
otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

LlVS-16;
LlV15-16

I

Output voltage variation when sWitching the Inputs
Total harmonic distortion
over most of signal range (see Figure 4)
V1=5V, f=1kHz
VI = 5V, f = 20Hz to 20kHz

drOT
dTOT
dTOT

Max

-15

Voltage gain

Av

Typ

10

dB
100

0.01
0.02
0.03

mV

%
%
%

VO(RMS)

Output signal handling
dTOT = 0.1 %; 1 = 1kHz (RMS value)

VN(RMS)

NOise output voltage (unwelghted)
1 = 20Hz to 20kHz (RMS value)

5

j.lV

VN

NOise output voltage (weighted)
1 = 20Hz to 20kHz (In accordance with DIN 45405)

12

j.lV

LlVS-16;
LlV15-16

Amplitude response 1
VI = 5V; 1 = 20Hz to 20kHz, CI = 0.22j.lF

I

5.0

5.3

0.1

V

dB

ex

Crosstalk between a sWitched-on Input and a non-swltched-on
Input; measured at the output at 1 = 1kHz2

75

dB

ex

Crosstalk between sWitched-on Inputs and the outputs 01 the
other channels2

90

dB

NOTES:
1. The lower cut-off frequency depends on values of RelAs and Cl
2 Depends on external Circuitry and Rs The value will be fixed mostly by capacitive crosstalk of the external components

December 2, 1986

7-141

•

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

nar--+--~--+-~---+~

z.. =1MQII1OOpF

~ 10' I--Hf.Hf!III'-H+H+lII--H-I-IHlIf-+l+1f!!lI

nar--+--~--=-+---+---l"i1'd

~

I\.

!

J

I:;

I---+---+---+--I---H-i

0.4

;lr: 11)2 1-+1-I+HfI1--HH-HIIII--H+If!!lI-+++If!!lI

r--

-

~~~~~WW~~~~~

10

10'

11)2

11)2

•

o

d

• ':::''::'±:::::::i:=:::'' ........ " ••'

o

2

!(Hz)

• (Hz)

4
VO(AM8l(¥)

NOTES:
--f=1kHz

.......... f=20kHz

Figure 1. Equivalent Input
Nolae Current

30

Figure 3. Total Harmonic Distortion aa
a Function of RMS Output Voltage

Figure 2. Equivalent Input
Noise Voltage

f.1~HZ

-dmr=1%

:JX

RL=ao
20

/
/

--/

o

5

15

/"

~

-1-"1-"

......

V

/'"

...

........ ........

~s
MIN

I"

1

25

1

Vee(¥)

CPU,'"
NOTES:

Figure 4. Output Voltage as a Function
of Supply Voltage

December 2, 1986

Av - 1dB. f - 20Hz to 20kHz
- - VN (output)
- - - - VN (Rsl

Figure 5. Noise Output Voltage as a Function of Input Resistance

7-142

Product Specification

Signetics Linear Products

TDA1029

Stereo Audio Switch

Input Protection Circuit and Indication

Unused Signal Inputs
Any unused Inputs must be connected to a
DC (bias) voltage, which IS within the DC Input
voltage range; e.g., unused Inputs can be
connected directly to Pin 10
TDA1029

V,

Circuits With Standby Operation

C>-JVVI,--t-+--i

« .. V)

The control inputs (Pins 11, 12 and 13) are
high-ohmic at VSH";; 20V(lSH";; 11lA, as well
as when the supply voltage (Pin 14) IS
sWitched off

+

c>-~-oG-O--,

Figure 6. Circuit Diagram Showing Input Protection and Indication

•
December 2, 1986

7-143

Signetics Linear Products

Product Specification

Stereo Audio Switch

TDA1029

+·yooo-----------~~------------------------_,

,.

. .INO

RIGHTINPUT

PIN CONNECTED 10 DV
OR lOW LEVEL:

11

121~3~N~K~

LEFTINPUTC

P----------1f-.. .

12=TAPE1
tI_TAPE2

13

---+-''1

....
.... ...

.
TDA1029

820.

16

•

LEFT
OUTPUT
RIGHT
OUTPUT

R

0.1
,F

0,1"F

"
PREAMPLIREfI
(WITH RiAA EQUALIZATION)

1M

Figure 7. TDA 1029 Connec1ed as a 4-lnput Stereo Source Selector

December 2, 1986

7-144

1M

Signetics Linear Products

Product Specification

Stereo Audio Switch

Uk

lOA 1029

Uk 12Ok(8 xl

~~~~o-~aA~7~"_F______+--4__-t____~__J-________~

TDA1029

O.33"F

A:-tnF

15

~~~r--------i--~------O~~UT

ttk

G.47jAF

RI~~~I~~ o--?-~ ~--------------+----<~-i----------,

)-~~---------+--~------o~~~T
14

J--4--""'--o r~V)
+
27k

27k

Uk

18

10

J.

+ 100jAF
(15V)

11

12

13

ON{ ON{
OFF

MUTE

OFF

RUMBLE

5UaSONIC

FILTER

FILTER

Figure 8. TDA 1029 Connected as a Third-Order Active High-Pass Filter With Butterworth Response and Component Values
Chosen According to the Method Proposed by Fjiillbrant. It is a Four-Function Circuit Which can Select Mute, Rumble
Filter, Subsonic Filter and Linear Response

SWITCH CONTROL
FUNCTION
linear
Subsonic filter 'on'
Rumble filter 'on'
Mute 'on'

December 2, 1986

V11-16

V,2 - ,6

V ,3 - ,6

H
H
H
L

H
H
L
X

H
L
X
X

7-145

•

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

~~tJA

-10

/

-I
/

V
-30
-40

-so

/RUMB~i
Flll'ER

SUBSONIC
FILTER

1

VI

/

I

10
• (Hz)

Figure 9. Frequency Response Curves for the Circuit of Figure 8

December 2, 1986

7-146

TDA1074A

Signetics

DC-Controlled Dual
Potentiometer Circuit
Product Specification
Linear Products

DESCRIPTION
The TDA 1074A is a monolithic integrated circuit designed for use as volume
and tone control circuit in stereo amplifiers. This dual tandem potentiometer IC
consists of two ganged pairs of electronic potentiometers with the eight inputs
connected via Impedance converters,
and the four outputs driving individual
operational amplifiers. The setting of
each electronic potentiometer pair is
controlled by an individual DC control
voltage. The potentiometers operate by
current division between the arms of
cross-coupled long-tailed pairs. The current division factor is determined by the
level and polarity of the DC control
voltage with respect to an externally
available reference level of half the supply voltage. Since the electronic potentiometers are adjusted by a DC control
voltage, each pair can be controlled by
single linear potentiometers which can
be located in any position dictated by the
equipment styling. Since the input and
feedback impedances around the operational amplifier gain blocks are external,
the TDA 1074A can perform bass/treble
and volume/loudness control. It also
can be used as a low-level fader to
control the sound distribution between
the front and rear loudspeakers in car
radio installations.

FEATURES
• High impedance inputs to both
'ends' of each electronic
potentiometer
• Ganged potentiometers track
within O.5dB
• Electronic rejection of supply
ripple
• Internally-generated reference
level available externally so that
the control voltage can be made
to swing positively and
negatively around a well-defined
OV level
• The operational amplifiers have
push-pull outputs for wide
voltage swing and low current
consumption
• The operational amplifier outputs
are current limited to provide
output short-circuit protection
• Although designed to operate
from a 20V supply (giving a
maximum input and output signal
level of 6V), the TDA1074A can
work from a supply as low as
7.5V with reduced input and
output signal levels

PIN CONFIGURATION
N Package

BYPASS 1
OUTPUT (2A1 2
INPUT(2A1 3
INPUT (2AI 4
INPUT~AI

5

INPUTOAI
OUTPUTOAI
REF VOLTAGE
CONTROL
VOLT IN

6

17

OUTPUT (2B)

7

8

TOP VIEW

•

APPLICATIONS
• Volume control
• Tone control
• Low level fader

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-PIn Plastic DIP (SOT·102GS)

-30 0 G to + 80 0 G

TDA1074AN

December 2, 1986

7-147

853-1047 86702

Signetics Linear Products

Product Specification

DC-Controlled Dual Potentiometer Circuit

TDA1074A

BLOCK DIAGRAM

n

lOOnF
1k
1k

V+=20V
Vel

18

10

11

VREF

C,

~~o--t

C,

Zt

ZI

I--;::"~

+

+
Z2

Z2

Co

Co
Vo1Ao--j +
IRc)

+ ~Vo2A
(1\)

Z3

c,

ZI

V,1B o--j +
(RaJ

Z2

Co

Z3

C,
+ I--~B

ZI

15

14

V~o--t +

Z3

Z4

Z4

Z2

12

17

13

18

Co

+ I--~B
Z3

Z4

Z4

TDA1074A

NOTES:
tel (at Pin 9) and IC2 (at Pin 10) are control Input currents, Vel (at Pm 9) and VC2 (at Pin 10) are control mput voltages with respect to VREF III VCC/2 at Pm 8; Zl Z2 ... Z3 - Z4'" 22k!l.
the Input generator resistance RG:;; 60Q, the output load resistance RL = 4.7k.Q, the coupling capacitors at the mputs and outputs are CI .. 2 21lF and Co "" 1QIlF. respectlvety
0;

December 2, 1986

7-148

Signetics Linear Products

Product Specification

TDA1074A

DC-Controlled Dual Potentiometer Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vcc

PARAMETER

RATING

V

1

V

o to Vcc

V

800

mW

Control voltages (Pins 9 and 10)
Input voltage ranges (with respect to Pin
18) at Pins 3, 4, 5, 6, t3, 14, 15, 16

V,

UNIT

23

Supply voltage (Pin 11)

PTOT

Total power dissipation

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range

-30 to +80

°C

OCRA

Thermal resistance from crystal to ambient

80

°C/W

APPLICATION INFORMATION
Treble and Bass Control Circuit

Vcc = 20V; TA = 25°C; measured In Figure 1; RG = 60n; RL
unless otherwise specified.

> 4.7kn; CL < 30pF; f =

1kHz; with a linear frequency response (VCl = VC2 = OV),

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

22

Max

mA

Icc

Supply current (without load)

14

f

Frequency response (-1 dB) VCl = VC2 = OV

10

Av*

Voltage gain at linear Irequency response (VCl = VC2 = OV)

0

dB

AAv'

Gain vanation at I = 1kHz at maximum bassltreble boost or
cut at ±VC1=±VC2=120mV

±1

dB

Bass boost at 40Hz (reI. 1kHz) VC2 = 120mV

17.5

dB

Bass cut at 40Hz (reI. 1kHz) - VC2 = 120mV

17.5

dB

Hz

Treble boost at 16kHz (reI. 1kHz) VCl = 120mV

16

dB

Treble cut at 16kHz (reI. 1kHz) -VCl = 120mV

16

dB

0.002
0.005

%
%

THO
THO

Total harmonic distortion at VO(RMS) = 300mV
I = 1kHz (measured selectively)
I = 20Hz to 20kHz
at VO(RMS) = 5V
I = 1kHz
I = 20Hz to 20kHz

V" VO(RMS)

Signal level at THO = 0.7% (Input and output)

BW

Power bandwidth at relerence level VO(RMS) = 5V (-3dB);
THO=O.l%

THO
THO

30
20,000

0015
0.05
5.5

0.1
0.1

%
%

6.2

V

40

kHz

VNO(RMS)
VNO(M)

Output nOise voltages
(signal plus noise (RMS value); I = 20Hz to 20kHz
nOise (peak value); weighted to DIN 45405; CCITT II Iter

75
160

cxCT
cxCT

Crosstalk attenuation (stereo)
I = 1kHz
I = 20Hz to 20kHz

86
80

dB
dB

-cxCT

Control voltage cross-talk to the outputs at I = 1kHz;
VC1(RMS) = VC2(RMS) = lmV

20

dB

cxl00

Ripple rejeclton at 1= 100Hz; VCC(RMS)

46

dB

Oecember 2, 1986

< 200mV

7-149

230

/lV
/lV

•

Signetics Linear Products

Product Specification

TDA1074A

DC-Controlled Dual Potentiometer Circuit

(+~'VI
-='

88k

88k

lk

lk

lOOnF
y+

4.7flF

..r-J..lOO"F

-='

-='

18

+

(25V)

+
10

11

(OV)

12k

1A: TREBLE (lEFl)

18: TREBLE(RIGH1)
2A: BASS(LEFl)
2B: IIASE(RIGHl)

V,lA

(Rol

UnF

2.2"F

--+-l
L

+
39k

39k

180k

39k

22"F

INPUTS

+

UnF

I-- Yo2A

L
RL)S4.7k

12k
33nF

2.2"F

10

~It'.::~+

39k

15

OUTPUTS 10
POWER AMPUFlER

39k

180k

I.

38k

22"F

17

+
UnF

12k
13

18

t--R Yo2B

Rl >4.7k

33nF

TDAlO74A

4.7pF
(4V)

Figure 1. Application Diagram for Treble and Bass Control

December 2, 1986

7-150

Product Specification

Signetics Linear Products

TDA1074A

DC-Controlled Dual Potentiometer Circuit

APPLICATION INFORMATION (Continued)

-

II

20

BASS

10

~

iii
~

co>

;:;;--

TREBLE

"",

... ~

..... ""

~

-10

..

II

~
-20
20

10'
I (Hz)

Figure 2. Frequency Response Curves; Voltage Gain (Treble and Bass) as a Function of Frequency

20

20

l-

/1-

/
10

10

/

V

iii
~

>

~

,;

/

-10

iJ

-10

/

'--

I_I-f-"
-20
-1SO -100

I

II

iii

II

'"

V

-so

so

100

-20
-1SO -100

150

II

/
-so

so

100

150

VC1 (mV)

Figure 4. Control Curve; Voltage Gain (Treble) as a
Function of the Control Voltage (Vc1l; f = 16kHz

Figure 3. Control Curve; Voltage Gain (Bass) as a
Function of the Control Voltage (VC2); f = 40Hz

TDA1074A

+10

Curve No.

Value of R

iii

10kil
100kil
220kil

~

>

CO

§

470kil

iii

1Mil

-10

(V+=2OV)

+

of; .,
1k

*

lOOnF

Figure 6. Circuit Diagram for
Measuring Curves in Figure 5

=

Figure 5. Voltage Gain (Av vo/v,) Control Curves as a Function of the Angle
of Rotation (
" -40

j

I

-60
-80

I
V

ii

:e.

J

-20

-40

I
I

V

v\
1\

Intemal potentiometer supply from Pin 17 used,

l!.
>

\

~

-10

J

\

NOTES:
Internal potenbome1er supply from PIn 17 used,

Vee e 85V

See Block Diagram

Figure 4. Volume Control Curve;
Voltage Gain (Av) as a Function of
Control Vortage (V, _ 18)

Figure 5. Balance Control Curve;
Voltage Gain (Av) as a Function of
Control Voltage (V 16 -18)

7-159

--

/

"

Vee e 8.5V, f - 1kHz
_
Block DIagram

June 30, 1988

J

ii

1\

-'-

L

10

-20

NOTES:

40

Figure 3. Input Resistance (R,) a8
a Function of Gain of Volume
Control (Av)

20
20

20

Gv(dB)

o

I---'"

NOTES:
With Slngle-pole filter, Internal potentiometer supply
from Pin 17 used, Vee - 8 5V, f .. 40Hz
See Block Diagram.

Figure 6. Bas8 Control Curve;
Voltage Gain (Av) as a Function of
Control Voltage (V, -18)

Product Specification

Signetics Linear Products

TDA1524A

Stereo Audio Control

20

v

to

20

I

iii'

--

l-

:s

co>
-to

-20

-

J

i-

V

,...

-40

-r--.

V

o

I-

-r-.

-80

to'

10

I (Hz)

NOTES:
Internal potentiometer supply from Pin 17 used,
Vee'" 8 5V, f - 16kHz
See Block Dl9.gram

Figure 7. Treble Control Curve;
Voltage Gain (Av) as a Function
of Control Voltage (V,0-IS)

NOTES:
With sing/e-pole filter, Vee "" 8 5V

See Block Diagram

Figure 8. Contour Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency

to'

to

t0 5

I (Hz)
NOTES:
With double-pole filter, Vee = 8 5V
See Block Diagram

Figure 9. Contour Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency

20

l-

i10

:iii'

:s

co>

-

:::::;;:

=-

--~

:ijI

~

-10

II-20

?

::::::

---

::::::

~

to'

10

I (Hz)
NOTES:
Wrth smgle-pole fIlter, Vee'" 8 5V
See Block Diagram

Figure 10. Tone Control Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency
June 3D, 1988

7-160

Signetics Linear Products

Product Specification

Stereo Audio Control

TDA1524A

350

20

-

~

~

......

-

-40
10

,.
""

~

./

-20

300

'~"

i""-....

200

0

~

-I'

:::

250

'7

150
100
50

1Il'

2
3

-60

I (Hz)

1/
VV
V

1

-40

-20

20

40

60

Gv(dB)

NOTES:
With double-pole filler, Vee:: 6 5V
See Block Diagram

NOTES:

Figure 11. Tone Control Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency

1 Vcc=1SV
2 Vcc=12V
3 Vee = 8 5V
f = 20Hz 1020kHz
See Block Diagram

Figure 14. Noise Output Voltage
(VNO(RMS); Unweighled); as a Function
of Voltage Gain (Av)

0.4
VI =
~ O.2V

0.5V
I

P" 2:-=:

f-::

::><

o

10

1.DV
1.4V

10'
I (Hz)

NOTES:
Vee

= 8 5V volume control voltage gam at
Vo
Av=20 log -"'OdB

V,

See Block Diagram

Figure 12. Total Harmonic Distortion (THO); as a Function
of Audio Input Frequency

0.41-----+-----+------+------1
~

;;
~ 02~--~~--~~~--------+~~~~--_+~-------~

OL-________L -_____
o
M

~~

W

______

~~

______

~

w

~

VoM

NOTES:
Vcc=8SV; f, = 1kHz
See Block Diagram

Figure 13. Total Harmonic Distortion (THO) as a Function
of Output Voltage (Vo)

June 30, 1988

7-161

•

TDA8440

Signetics

Video and Audio Switch

Ie

Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA8440 is a versatile video/audio
switch, intended to be used in applications equipped with video/audio inputs.

• Combined analog and digital
circuitry gives maximum flexibility
in channel switching
• 3-State switches for all channels
• Selectable gain for the video
channels
• Sub-addressing facility
• 12C bus or non-1 2C bus mode
(controlled by DC voltages)
• Slave receiver in the 12C bus
mode
• External OFF command
• System expansion possible up to
7 devices (14 sources)
• Static short-circuit proof outputs

It provides two 3-State switches for audio channels and one 3-State switch for
the video channel and a video amplifier
with selectable gain (times 1 or times 2).
The Integrated circuit can be controlled
via a bidirectional 12C bus or it can be
controlled directly by DC switching signals. Sufficient sub-addressing is provided for the 12C bus mode.

N Package
VIDEO II IN

1

OFF
FUNCTION IN
VIDEO IINPUT

3

AUDlOI.IN

5

AUDIO ". IN 7

BYPASS 8
AUDlOI.IN

9

'-----'
lOPYIEW
CD12511S

APPLICATIONS
• TVRO
• Video and audio switching
• Television
• CATV

ORDERING INFORMATION
DESCRIPTION

ORDER CODE

TEMPERATURE RANGE

18-Pln Plastic DIP (SOT-102)

o to

70'C

TDA8440N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vec

Supply voltage Pin 15

VSDA
VSCl
VOFF
Vso
VS1
VS2

Input
Pin
Pin
Pin
Pin
Pin
Pin

voltage
17
18
2
11
13
6

-0.3
-0.3
-0.3
-0.3
-0.3
-0.3

RATING

UNIT

14

V

to
to
to
to
to
to

Vec
Vec
Vee
Vee
Vee
Vee

+0.3
+0.3
+03
+0.3
+0.3
+0.3

V
V
V
V
V
V

-116

Video output current Pin 16

50

mA

TSTG

Storage temperature range

-65 to +150

'C

TA

Operating ambient temperature range

o to +70

'C

TJ

Junction temperature

+150

'C

(JJA

Thermal resistance from Junction to
ambient in free-air

50

'C/W

February 12, 1987

7-162

853-1172 87583

Product Specification

Signetics Linear Products

Video and Audio Switch

Ie

TDA8440

BLOCK DIAGRAM AND TEST CIRCUIT

rl-:-+--I--I
1k

AUDIO I.

-=

AUDIOII.

AUDIOII.

VIDEO I

12 10lAf

+ TAUDIOAOUT

O.47,101f 10

1k
11

1------50

rl-:-+"":'+--I
1k

O.47jAF

14

1k

-=

75

O.47,101F

13

I-----s,

100nF

-..-4----.--16

100nF

VIDEOOUT

1k

~1--+---1
":'"

AUDIOBOUT
1k

~I--t--i
75

lOj.lF

+ T

rl-c-+-+--I
":'"

-=
VIDEO II

TDA8440

9

r~+-+---1
-=-

AUDIOI.

1k

O.47,101F

1,uF

~r----II

s"

+

17

OFF

18

15

SDA
}

I'CBUS

SCL

Vee

NOTE:
SO, 81, 52, and OFF (Pins 11, 13, 6, and 2) connected to Vee or GND If more than 1 device IS used, the outputs and Pin 8 (bias decouphng of the audio Inputs) may be connected In
parallel

February 12, 1987

7-163

•

Product Specification

Signetics Linear Products

Video and Audio Switch

Ie

TDA8440

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee -12V, unless otherwise specified.
LIMITS
SYMaOL

PARAMETER
Min

Typ

Max

I
I

UNIT

Supply
V15-4

Supply voltage

115

Supply current (Without load)

13.2

V

37

50

rnA

10

Video switch
C1 C3

Input coupling capacitor

100

A3-16
A3-16

Voltage gain (times 1; SCl = l)
(times 2; SCl = H)

-1
+5

0
+6

+1
+7

dB
dB

nF

AI-16
AI-16

Voltage gain (times 1; SCl = l)
(times 2; SCl = H)

-1
+5

0
+6

+1
+7

dB
dB

V3-4

Input video signal amplitude (gain times 1)

4.5

V

VI - 4

Input video signal amplitude (gain times 1)

4.5

Z16-4

Output impedance

Z16-4

Output impedance In 'OFF' state

100

kn

Isolation (off-state) (10 = 5MHz)

60

dB

S/S+N

Slgnal-to-noise ratio2

60

V16-4

Output top-sync level

2.4

G

Differential gain

V16-4

Minimum crosstalk attenuation 1

60

dB

RR

Supply voltage rejection3

36

dB

BW

Bandwidth (1 dB)

10

MHz

ex

Crosstalk attenuation lor interference caused by bus signals
(source impedance 75n)

60

db

7

V
n

dB
2.8

3.2

V

3

%

Audio switch "A" and "a"
V9-4 (RMS)
Vl0-4 (RMS)
V5_4 (RMS)
V7-4 (RMS)
Z9-4
Z10-4
ZS_4
Z7_4

Input signal level

50
50

50
50

Input impedance

Z12-4
Z14-4

Output impedance

Z14-4

Output impedance (off-state)

V9-12
Vl0-12
VS-14
V7-14

2
2
2
2

100

Voltage gain
Isolation (off-state) (I - 20kHz)

90

S/S+N

Signal-to-noise ratio4

90

THO

Total harmonic distortion6

February 12, 1987

kn
kn
kn
kn

100
100
100
100
10
10

-1
-1
-1
-1

n
n
kn

0
0
0
0

+1
+1
+1
+ 1

dB
dB
dB
dB
dB
dB

0.1

7-164

V
V
V
V

%

Signetics Linear Products

Product Specification

Video and Audio Switch

Ie

TDA8440

DC ELECTRICAL CHARACTERISTICS (Continued) TA ~ 25°C, Vec ~ 12V, unless otherwise specIfied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Crosstalk attenuation for Interferences
caused by video slgnals 5
Weighted
Unweighted

Typ

Max

80
80

dB
dB

Crosstalk attenuation for Interferences caused by smusoldal
sound slgnals 5

80

dB

Crosstalk attenuallon for interferences caused by the bus
signal (weighted) (source Impedance ~ 1kQ)

80

dB

RR

Supply voltage reiectlon

50

dB

BW

Bandwidth (-1 dB)

50

kHz

C<
C<

C<

12C bus inputs/outputs SOA (Pin 17) and SCl (Pin 18)
V,H

Input voltage HIGH

3

Vce

V

V,L

Input voltage LOW

-0.3

+1.5

V

I'H

Input current HIGH 7

10

/lA

I,L

Input current LOW7

10

/lA

VOL

Output voltage LOW at IOL ~ 3mA

0.4

IOL

Maximum output smk current

C,

Capacitance of SDA and SCL Inputs, Pins 17 and 18

V
mA

5
10

pF

Sub-address inputs So (Pin 11), SI (Pin 13), S2 (Pin 6)
V,H

Input voltage HIGH

3

Vee

V

V,L

Input voltage LOW

-0.3

+0.4

V

I'H

Input current HIGH

10

/lA

I,L

Input current LOW

0

/lA

V

-50

OFF input (Pm 2)
V,H

Input voltage HIGH

+3

Vec

V,L

Input voltage LOW

-0.3

+0.4

V

I'H

Input current HIGH

20

/lA

I,L

Input current LOW

2

IlA

-10

NOTES:

1. Caused by dnve on any other Input at maximum level, measured
crosstalk

= 2010g

B = 5MHz, source Impedance for the used Input 7SD,

VOUT

--VIN max

2. SIN = 2010g Vo video nOise
Vo

(P-P)

(2V)

nOise RMS B = 5MHz

Supply voltage ripple rejection = 2010g
4. SIN = 2010g

In

Vo nominal (0 5V)
Vo nOise B = 20kHz

VR supply

VR on output

at I = max 100kHz

.

5. Caused by dnve of any other Input at maximum level, measured In B = 20kHz, source Impedance of the used Input = 1kn,
VOUT

crosstalk = 2010g - - - according to DIN 45405 (CCIR 468)
VIN max
6. f ~ 20Hz to 20kHz.
7. Also II the supply IS sWitched off.

February 12, 1987

7-165

•

Signetics Linear Products

Product Specification

Ie

Video and Audio Switch

TDA8440

AC ELECTRICAL CHARACTERISTICS 12C bus load conditions are as follows: 4k!1 pull-up resistor to + SV; 200pF to GNO.
All values are referred to V,H

= 3V

and V,L = 1.SV.
LIMITS

SYMBOL

PARAMETER

UNIT

Min

Max

tSUF

Bus free before start

4

{.IS

ts

(STA)

Start condition setup time

4

{.IS

tH

(STA)

Start condition hold time

4

{.IS

tLOw

SCL, SOA LOW period

4

{.Is

tHIGH

SCL, HIGH period

4

tR

SCL, SOA rise time

{.IS

SCL, SOA fall time

tF

1

{.IS

0.3

{.IS
{.IS

ts

(DAT)

Data setup time (write)

1

tH

(DAT)

Data hold time (write)

1

ts

(CAG)

Acknowledge (from TOA8440) setup time

tH

(CAG)

Acknowledge (from TOA8440) hold time

0

{.IS

ts

(STO)

Stop condition setup time

4

{.IS

Table 1_ Sub-Addressing
S2

SI

So

L
L
L
L
H
H
H

L
L
H
H
L
L
H

L
H
L
H
L
H
L

A2

Al

Ao

0
0
0
0
1
1
1

0
0
1
1
0

0
1
0
1

A selection can be made between two input
signals and an OFF-state. The OFF-state is
necessary if more than one TOA8440 device
is used.

H

H

a
1

a
1

a

non 12C
addressable

FUNCTIONAL DESCRIPTION
The TOA8440 is a monolithic system of
switches and can be used in CTV receivers
equipped with an auxiliary video/audio plug.
The IC incorporates 3-State switches which
comprise:
a) An electronic video switch with selectable
gain (times 1 or times 2) for switching
between an Internal video signal (from the
IF amplifier) with an auxiliary input signal.

February 12, 1987

{.IS
2

b) Two electronic audio switches, for two
sound channels (stereo or dual language),
for switching between internal audio
sources and signals from the auxiliary video/audio plug.

SUB-ADDRESS

H

Typ

The SOA and SCL pins can be connected to
the 12C bus or to DC sWitching voltages.
Inputs So (Pin 11), SI (Pin 13), and S2 (Pin 6)
are used for selection of sub-addresses or
switching to the non-1 2C mode. Inputs So, SI,
and S2 can be connected to the supply
voltage (H) or to ground (L). In this way, no
peripheral components are required for selection.

NON-1 2C BUS CONTROL
If the TOA8440 switching device has to be
operated via the auxiliary video/audio plug,
inputs S2, SI, and So must be connected to
the supply line (12V).

7·166

{.Is

The sources (internal and external) and the
gain of the video amplifier can be selected via
the SOA and SCL pins with the switching
voltage from the auxiliary video/audio plug:
• Sources I are selected If SOA = 12V
(external source)
• Sources II are selected if SOA = OV (TV
mode)

• Video amplifier gain is 2 X if SCL
(external source)

= 12V

• Video amplifier gain is 1 X if SCL
(TV mode)

= OV

If more than one TOA8440 device is used in
the non-1 2C bus system, the OFF pin can be
used to switch off the desired devices. This
can be done via the 12V sWitching voltage on
the plug.
• All switches are in the OFF posilion if
OFF = H (12V)
• All switches are in the selected position
via SOA and SCL pins if OFF = L (OV)

12 C BUS CONTROL
Detailed Information on the 12C bus is available on request.

Product Specification

Signettcs Unear Products

Ie

Video and Audio Switch

TDA8440

Table 2. TDA8440 12C Bus Protocol
Do
STA

= start condition

~

:

Aa

=1

A2
AI

= sub-address bit, fixed via S, input

Ao

= sub-address bit, fixed via So input

R/W
AC
D7

- read/write bit (has to be 0, only write mode allowed)
= acknowledge bit (= 0) generated by the TDA8440
- 1 audio I. is selected to audio output a
= 0 audio I. is not selected
= 1 audio II. is selected to audio output a
= 0 audio II. is not selected
= 1 audio Ib is selected to audio output b
- 0 audio Ib output is not selected
= 1 audio lib is selected to audio output b
- 0 audio lib is not selected
= 1 video I is selected to video output
= 0 video I is not selected
= 1 video II is selected to video output
= 0 video II is not selected
- 1 video amplifier gain is times 2
= 0 video amplifier gain is times 1
- 1 OFF-input inactive
= 0 OFF-input active
= stop condition

Dr
D6
06
05
05
04
04

Da
Da

02
02
0,
0,
Do

Do
STO

~

1 Fixed

AC

STO

address bits

= sub·address bit, fixed via S2 input

Do/OFF Gating

Do

OFF Input

o (off input active)
0

H
l

1 (off input inactive)
1

H
l

OFF FUNCTION
With the OFF input all outputs can be
switched off (high-ohmic mode), depending
on the value of Do.

Power-on Reset
The circuit is provided with a power-on reset
function.

Outputs
OFF
In accordance with last defined
07 - 0 , (may be entered while
OFF = HIGH)
In accordance with 07 - 0,
In accordance with 07 - 0,
When the power supply is switched on, an
internal pulse will be generated that will reset
the internal memory So. In the initial state all
the switches will be in the off pOSition and the
OFF input is active (07 - Do = 0), (12c mode).
In the non-12C mode, positions are defined via
SOA and SCl input voltages.

BOA
(WRITE)

SCL

Figure 1. 12C Bua nmlng Diagram
February 12, 1987

7-167

When the power supply decreases below 5V,
a pulse Will be generated and the internal
memory will be reset. The behavior of the
sWitches Will be the same as descnbed
above.

•

TEA6300

Signetics

Digitally-Controlled Tone,
Volume, and Fader Control
Circuit
Linear Products

Preliminary Specification

DESCRIPTION

FEATURES

The TEA6300 is a single-chip 12C buscontrolled tone, volume, loudness, and
fader control circuit ideal for audio signal
processing in an automotive entertainment environment. The TEA6300 provides three stereo source input selector
switching, volume, loudness, tone, and
fader (front! rear) controls. The active
tone control functions are determined by
two capacitors along with on-chip op
amps which keep external component
counts to a minimum.

• Source selector for three stereo
inputs
• Low noise and distortion
• Volume and balance control;
Control range of 86dB in 2dB
steps
• Bass and treble control from
+ 15dB (treble + 12dB) to -12dB
in 3dB steps
• Fader control from OdB to -30dB
in 2dB steps

PIN CONFIGURATION
N Package

BR1
BRO

• Fast muting
• Low noise suitable for DOLBY®

INLB

NR

ELFI

• Signal handling suitable for
compact disc
• Pop-free on/off switching
• 28-pin package

IN LC
QSL
INL
TOP VIEW

APPLICATIONS

CD13340S

PIN NO.

• Auto radio
• Audio systems
• TV
• Remote control audio systems

SYMBOL
SDA
GNDB
DlR
DlF
TL
BL1
BlO

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8
9
10

INLA
Ie

28-Pin Plastic DIP (SOT-117BE)

-40·C to +85·C

TEA6300N

11

ElFI
INLC
DSL
INL
INR
DSR

12
13
14
15
16

ABSOLUTE MAXIMUM RATINGS

SYMBOL

RATING

UNIT

Vcc

Supply voltage (Pins 27 - 18)

PARAMETER

16

V

PTOT

Maximum power disSipation

2

W

TSTG

Storage temperature range

-55 to +150

TA

Operating ambient temperature range

-40 to +85

December 1988

7-168

INLB

17

INRC

18
19
20
21
22

GND
VREF

·C

23

SR1

·C

24

TR

25
26
27
28

DRF
ORR

INAB
INRA
BRO

Vee
Sel

DESCRIPTION
Data Input/output
Ground for BUS terminals
Output left rear
Output left front
Termination for treble control
capacitor left channel
T ermmatlon for bass control
capacitor left channel
TerminatIOn for bass control
capacitor left channel
Input left source A
tnternal connected
Input left source B
Electronic flltenng for supply
Input left source C
Output source selector left
Input left control part
Input fight control part
Output source selector right
Input fight source C
Ground
Input fight source B
Reference voltage (Y2 Vee)
Input right source A
Termination for bass control
capacitor fight channel
Termination for bass control
capacitor fight channel
Termination for treble control
capacitor nght channel
Output fight front
Output nght rear
Supply voltage
Clock mput

Preliminary Specification

Signetics linear Products

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

BLOCK DIAGRAM

-II-

y~

QSL INL
13
14

2.2",F

INLS

o--f

BLa
7

BL1
8

TL
5

TEA8300

(6.1
INLA

r-Iq

rir

"

+
~

o-f~ -0 ,
o-f + 12 9 1I
I
21

....

tL

......

SOURCE
SELEClOR

I
I

.....
....

I
o-f +
o-ft-;--!! -01(
INRC o-f + 17

20

+
122"F

•

tL

t

~ME

BALANCE

27

I

+

11OO"F

•

YI-

1 2

---

SCL GNDB
SOA

4.7

+

3

4.7

+

FADER MUTE

~

~

LO~ESS

TREBLE
LOUDNESS

H~'-

25

4.7

+
28

4.7

+

~VREF

--

18 16
15 28
GN[ QSR INR

4

~VREF

l~CBUSJ
LOGIC

=~~
11
ELFI

to

~

y

....

~r-C'"

8

22
BRG

23
BR1

Yr

24
TR

I

I'CBUS

•
December 1988

7-169

Signetics Linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

FUNCTIONAL DESCRIPTION
The input selector selects three stereo channels, e.g., RF part (AM/FM), recorder and
compact disk. As the outputs of the source
selector as well as the Inputs of the main
control part are available, additional circuits
like compander- and equalizer systems may
be inserted into the signal path. The AC
signal setting is performed by resistor chains
in combination with multi-Input operational
amplifiers. The advantage of this principle IS

the combination of low noise, low distortion,
and a high dynamic range for the cirCUIt.
The separated volume controls of the left and
the right channel make the balance control
possible. The range and the characteristic of
the balance is software-programmable by
setting an extra bass (and optional treble)
control, depending on the actual volume POSItion, the loudness function, performed by
software In a microcomputer controlling both
the sWitching pOints and the ranges. Because
the TEA6300 has four outputs, a low-level

fader is included. The fader control is independent of the volume control and an extra
mute position for the front or the rear or for all
channels is built in. The last function may be
used for muting during preset selection. For
pop-free switching, on and off, an extra pop
suppression circuitry is built in. As all switching and control functions are controllable via
the two-wire 12C bus, no external interface
between the microcomputer and the
TEA6300 is required. The on-chip power-on
reset sets the TEA6300 into the general mute
mode.

DC ELECTRICAL CHARACTERISTICS Vee = 8.5V; Rs = 600Q; RL = 10kQ; f = 1kHz; TA = 25'C (Figure 6), unless otherwise
specified.
LIMITS
SYMBOL

PARAMETER

Vee

Supply voltage

UNIT
Min

Typ

Max

7.0

8.5

13.2

Icc

Supply current

VREF

Internal reference voltage (Pin 20) VREF

Av

Maximum gain bass and treble linear, fader off

VO(RMS)
VO(RMS)

Output level
for PMAX at the output stage
for start of clipping

V'(RMS)

Input sensitivity at Vo

fR

Frequency response
bass and treble linear;
roll-off frequency -1 dB

35

exes

Channel separation
G = OdB; bass and treble linear;
frequency range 250Hz to 10kHz

45

26

= 0.5

Vee

= 500mV

V
mA

4.25

V

20

dB

500
1000

mV
mV

50

mV
20000

70

Hz

dB

THO
THO
THO

Total harmonic distortion frequency range 20Hz to 12.5kHz
Y'N = 50mV; G = 20dB
Y'N = 500mV; G = OdB
VIN = 1.6V; G = -10dB

RR100
RRRANGE

Ripple rejection
VR(RMS) < 200mV; G = OdB;
bass and treble linear;
at f = 100Hz
at f = 40Hz to 12.5kHz

70
tbf

dB
dB

SIN
SIN
SIN
SIN
SIN
SIN

Signal-to-noise ratio bass and treble linear; 1, 2
CCIR 468-2 weighted; quasi-peak
V, = 50mV; Vo = 46mV; Po = 50mW
VI = 500mV; Vo = 45mV; Po = 50mW
VI = 50mV; Vo = 200mV; Po = lW
VI = 500mV; Vo = 200mV; Po = lW
V, = 50mV; Vo = 500mV; Po = 6W
V, = 500mV; Vo = 500mV; Po = 6W

65
67
70
78
70
85

dB
dB
dB
dB
dB
dB

PN

aB

December 1988

0.1
0.05
0.2

Noise power mute position, only contribution of TEA6300,
power amplifier for 25W
Crosstalk (20 log VSUS(P- P)/VO(RMS»
between BUS inputs and signal outputs
G = OOb; bass and treble linear

10

110

7-170

0.3
0.2
0.5

%
%
%

nW

dB

Signetics Linear Products

Preliminary Specification

Digitally-Controlled Tone, Volume, and Fader Control Circuit

TEA6300

DC ELECTRICAL CHARACTERISTICS (Continued) vee = 8.5V; Rs = 600n; RL = 10kn; f = 1kHz; TA = 25°C (Figure 6),
unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

20

30

Max

Source selector

Z,

Input Impedance

Zo

Output Impedance

RL

Admissible output load resistance

10

CL

Admissible output load capacity

0

O:S

Input Isolation not selected source;
frequency range 40Hz to 125kHz

40
100

kn
n
kn

200

pF

80

dB

dB

G

Gain
RL> 10kn

0

VB INTIVREF

Internal bias voltage

1

V'(RMS)
V'(RMS)

Maximum Input level
THD < 0.5%
THD < 0.5%; Vee = 7.5V

THD

Total harmonic distortion
V, = 500mV, RL = 10kn

Nw

NOise voltage weighted CCIR 468-2, quasI peak

Vo

DC offset voltage between any Inputs

1.65
1.5

V
V
0.1

%

20

jJ.V

10

mV

50

65

kn

100

150

9

Control part

(Source selector disconnected, source resistance 600n)
Z,

Input Impedance

Zo

Output Impedance

RL

Admissible output load resistance

10

CL

Admissible output load capacity

0

V'(RMS)

Maximum Input voltage
THD < 0 5%; G = -10dB;
bass and treble linear

2.0

Nw
Nw
Nw
Nw

NOise voltage weighted acc CCIR 468-2, quasI peak,
bass and treble linear, fader off
gaon 20dB
gain OdB
gain -66dB
mute position

110
25
19
11

Continuous control range

86

dB

Step resolution

2

dB

35

n
kn

1000

pF

V

220
50
38
22

jJ.V
jJ.V
jJ.V
jJ.V

Volume control

Gc

.:l.G.

Attenuator set error
(G = +20 to -50dB)

2

dB

.:l.G.

Attenuator set error
(G = + 20 to -66dB)

3

dB

2

dB

.:l.G t

Gaon tracking error balance In mid position,
bass and treble linear

O:M

Mute attenuation

December 1988

80

7-171

dB

•

Signetics Linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

DC ELECTRICAL CHARACTERISTICS (Continued) Vcc=8.5V; Rs=600n; RL=lokn; 1= 1kHz; TA=25'C (Figure 6),
unless otherwise specilied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

14
11

15
12

16
13

dB
dB

0.5

dB

13
13
15

dB
dB
dB

0.5

dB

Bass control

Gb
-Gb

Bass control range
I = 40Hz; maximum boost
I = 40Hz; maximum attenuation
Step resolution

3

Step error

dB

Treble control

Gt
-Gt
Gt

Treble control range
I = 15kHz; maximum boost
I = 15kHz; maximum attenuation
I > 15kHz; maximum boost

11
11

Step resolution

12
12
3

Step error

dB

Fader control

Gf

Continuous attenuation lader control range

30

dB

Step resolution

2

dB

Attenuator set error
CXM

1.5

Mute attenuation

80

dB
dB

Digital part

V,H
V,L

Bus terminals
Input voltage
HIGH
LOW

3
-0.3

12
1.5

V
V

I'H
I,L

Input current
HIGH
LOW

-10
-10

10
10

p.A
jJ.A

VOL

Output voltage LOW
IL =3mA

0.4

V

AC Characteristics according to the 12C Bus specilication

Power-on Reset
When RESET is active the GMU (general mute) bit
the BUS receiver is in RESET position

IS

set and

Vee
Vee

Increasing supply voltage
start 01 reset
end 01 reset

5.2

6.0

2.5
6.8

V
V

Vee

Decreasing supply voltage
start of reset

4.2

5.0

5.8

V

NOTES:
1. The Indicated values for output power assume a 6W power amp, with 20dB gain, connected to the output of the circuit Signal-to-nOlse ratios exclude noise
contribution of the power amplifier.
2. Signal-ta-nolse ratios on a CCIR 468-2 average reading meter are 4.SdB better than on CCIR 468-2 quasI peak

December 1988

7-172

Signetics Linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

12C BUS FORMAT
S

SLAVE ADDRESS

SUB-ADDRESS

A

S
= start condition
SLAVE ADDRESS = 1000 0000
A
= acknowledge, generated by the slave
If more than 1 byte DATA

IS

DATA

A

A

P

SUB-ADDRESS = see Table 1
DATA
= see Table 1
P
= STOP condition

transmitted, then auto-increment of the sub-address is performed

Table 1
FUNCTION

SUB-ADDRESS

Volume left
Volume right
Bass
Treble
Fader
SWitch

00000000
00000001
00000010
00000011
00000100
00000101

DATA
07

D6

05

04

03

02

01

DO

X
X
X
X
X
GMU

X
X
X
X
X
X

VL5
VR5
X
X
MFN
X

VL4
VR4
X
X
FCH
X

VL3
VR3
BA3
TR3
FA3
X

VL2
VR2
BA2
TR2
FA2
SCC

VLl
VRI
BAI
TRI
FAI
SCB

VLO
VRO
BAO
TRO
FAO
SCA

NOTES:

Function of the bits'
VlO to Vl5
VRO to VR5
BAO to BA3
TRO to TR3
FAO to FA3
FCH
MFN
SCA to SCC
GMU
X

Volume control left
Volume control fight
Bess control
Treble control
Fader control
Select fader channel (front or rear)
Mute control of the selected fader channel (front or rear)
Source selector control
Mute control (general mute) for the outputs OlF, OlR, ORF and ORR
Do not care brts (1 dunng tesllng)

Table 2. Bass Setting

Table 3. Treble Setting
DATA

G

(dB)
+15
+15
+15
+15
+12
+ 9
+ 6
+ 3
0
- 3
- 6
- 9
-12
-12
-12
-12

December 1988

DATA

G

BA3

BA2

BAI

BAO

(dB)

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

+12
+12
+12
+12
+12
+ 9
+ 6
+ 3
0
- 3
- 6
- 9
-12
-12
-12
-12

7-173

TR3

TR2

TRI

TRO

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

•

Signetics Linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

Table 4. Volume Setting LEFT
G
(dB)

Table 5. Volume Setting RIGHT
DATA

VL5 VL4 VL3 VL2 VL1

G
(dB)

VLO

DATA
VR5 VR4 VR3 VR2 VR1 VRO

20
18
16
14
12
10
8
6
4
2
0
- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
mute left
mute left

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

20
18
16
14
12
10
8
6
4
2
0
- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
mute right
mute right

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1

mute left

0

0

0

0

0

0

mute right

0

0

December 1988

7-174

1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0

0

0

0

1

1
1
1
1
0
0
0
0

1

Signetlcs Unear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

Table 6. Fader Function
SETTING

DATA

Front/Rear
dB
dB

SETTING

MFN FCH FA3 FA2 FA1

DATA

Front/Rear
dB
dB

FAD

MFN FCH FA3 FA2 FA1

0
0

0
0

1
0

1
1

1
1

- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

-80

0

0

1

1

-80

0

0

1

0

1
1

1
1

1
1

0
0

0
0

1
0

0
0

1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

1

0

0

-80

0

0

1

0

0

0

0

-80

0

0

0

fader front

1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

FAD

fader off

fader off

1
1

1
1

1
1

1
1

1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1

1

0

0

0

0

fader rear

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

mute front

1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

mute rear

Table 7
SELECTED INPUTS
Data
Data
Data
INLC.
Data
INLB.
INLA.
Data

not admissible
not admissible
not admissible
INRC
not admissible
INRB
INRA
not admissible

December 1988

DATA

sec

SCB

SCA

1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0

MUTE
DATA
CONTROL GMU

7-175

Active

1

PassIVe

0

REMARKS
Outputs 0LF. 0LR. ORF and ORR are
muted
No general mute

•

Preliminary Specification

Signetics Linear Products

Digitally-Controlled Tone, Volume, and Fader Control Circuit

15

0

10

~

....... t'~

t;;;"'"

-

-5

-10

~

[.....-"

-15
10

10"
!(Hz)

Figure 1. Bass Control

15

/'"

-

10

..........

./

!!G~':::::

~
-5

-

" "-

-10

...........

-15

10"

10

!(Hz)

Figure 2. Treble Control

160

WITH SOURCE SELECtoR
140

I

I

120

/

/1
I.

LAST STEP

-00

-~

-40

-~

-20

-10

/V

40
o/CON;if20
-iNLi
10

20

GAlN(dB)
OPl3830S

Figure 3. Output Noise Voltage (CCIR 468-2 Weighted; Quasi Peak)

December 1988

7-176

TEA6300

Signetics Linear Products

Preliminary Specification

Digitally-Controlled Tone, Volume, and Fader Control Circuit

90

I IIIIII
V.-SOOmV

80

.....

70

tz

V.=50mV

/

60

iii

....-

50
40

TEA6300

./
NOTE:
VI MIN"" 50mV, Vo'" 500mV for PMAX

30
O.1mW

10mW

lmW

O.lW

lW

lOW

Po

Figure 5. Recommended Level Diagram

Figure 4. Signal-to-Noise Ratio (CCIR 468-2 Weighted; Quasi Peak) With
a 6W Power Amplifier (Gain 20dB) Without Noise Contribution of
the Power Amplifier (See Figure 6)

330nF

IN C RIGHT 02.2.F

I+

-=-2.2.F
INSRIGHT~ +

l.2FJ.FI
-=-2.2 F

IN A RIGHT

o=.!!:-i

+
+

15

14

16

13

17

12

r-I

OUTRIGHTFRONT~4.7·F I +
Vee
(8.5V)

~

+

J--o IN CLEFT

l11OO.~ ~

19

10 2.2.F+

J--o IN S LEFT

8 2.2.F+

I---<> IN A LEFT

20

NC

21
TEA8300

33nF

23

5.6nF

OUT RIGHT REAR

2.2.~

18

22

33nF

330nF

5.6nF

24

~

25

4

4.7 F
•+

J-----o OUT LEFT FRONT

26

3

-=-

4.7.~

I---<> OUTLEFT REAR

27

GNOS

28

SOA
SCL

Figure 6. Test and Application Circuit

December 1988

7-177

I~.oo

•

Signefics

NE5240
Dolby Digital Audio Decoder
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The NE5240 is a two channel decoder
for the Dolby Digital Audio System. 'The
Ie includes input latches to separate two
channels of audio and control data, a
precision internal voltage reference, and
digital/ analog signal processing circuitry
for each channel. The Ie design is Implemented in a bipolar process to achieve
low noise, low distortion, and wide dynamic range.

• Wide dynamic range - 85dB
• Low distortion 0_05% @ 1kHz,
-10dB

NOTE:
'* Available only to licensees of Dolby LaboratOries
licensing Corporation, San FrancIsco, from whom
licensing and applications Information must be obtained Dolby IS a registered trademark of Dolby
Laboratones Llcensmg Corporation, San FrancIsco,
California

PIN CONFIGURATION

• TTL and CMOS compatible logic
inputs
• Audio bandwidth - 30Hz to
15kHz

APPLICATIONS
• High quality digital transmission
of audio data
• Satellite reception
• Cable TV
• Microwave distribution systems

N, D Packages
MULTOUT*

1

ANALOG
SUPPLY VOLT
VARIABLE

IMPEDANCEOUT"

4

SUM NODE*

5

INTERNAL
AMPLIFIER"
SLIDING BAND
BUFFER IN·
SLIDING BAND
BUFFER OUrSTEP SIZE

23

BUFFERIN fI

20

STEP SIZE
LOGIC
SUPPLY
STEP SIZE
DATA IN
AUDIO

DESCRIPTION

28-Pln SO
28-PIn Plastic DIP

December 1988

o to
o to

ORDER CODE

+70°C

NE5240D

+70°C

NE5240N

7-178

rur.~~Ft.""

ru~~~6uP*
EXT RES
REF VOLT

SLIDING BAND
DATA IN

TEMPERATURE RANGE

~~~~~* ~~p.

DIGITALGND

DATA IN

ORDERING INFORMATION

~~~~~~ ~~D

21

19

BUFFEROUT*

~J~rl~~~

22

TOP VIEW

Signetics Linear Products

Preliminary Specification

Dolby Digital Audio Decoder

NE5240

BLOCK DIAGRAM
R1
4.3K

R2
43K

.,.

R3
360K

C1
C2
O.47IlF;;; 47nF;+;

'.1K

C3
4.7nF;:;;

.,3

R4 4.3K RS 43K RS 360K

11

18

5.1K

C4
C5
C6
108 O.47J1.F.J;47nF;J;4.7nF;F,7 9

19

21

•

NOTE:
One channel of the application shown WIth extemal components

December 1988

7-179

Preliminary Specification

Signetics Linear Products

NE5240

Dolby Digital Audio Decoder

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vs

Analog supply voltage

+15

V

Voo

Logic supply voltage

+7

V

TA

Operating ambient temperature range

o to +70

·C

TSTG

Storage temperature range

-65 to +150

·C

TSOLO

Lead temperature (soldering, 60sec)

+300

·C

SYMBOL

PARAMETER

DC ELECTRICAL CHARACTERISTICS All specifications are at TA = 25·C, Vee = 12V, Voo = 5V.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Typ

Max

Vee

Analog voltage supply range

10

12

14

Voo

Logic voltage supply range

4.5

5

5.5

V
V

Icc

Supply current

Vee=12V

10

24

35

rnA

Voo = 5V

5

12

18

rnA

100

Supply current

VIH

Input voltage high

2

5

V

VIL

Input voltage low

0

0.8

V

IlL

Input current low

10

100

IIH

Input current high

1

100

!lA
!lA

ts

Setup time

150

tH

Hold time

150

Ie

Input buffers, Pins 7, 9, 20, 22

RL

Summing amp output load

VOS

Output offset voltage

Vos

Output offset change

VREF

Reference voltage

December 1988

Voo = 4.5V

ns
ns
100

VIN = 2.0V

kn

5

10%-S80-70%
5.5

7-180

nA

0.1

0.6

V

±5

±20

mV

0.5Vee

6.5

V

Signetlcs Linear Products

Preliminary Specification

NE5240

Dolby Digital Audio Decoder

AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS2

UNIT
Min

Typ

118

Full-Scale output, Ode

f -100Hz

Absolute output level

I = 1kHz, SSD - 40%

93

Channel balance

I - 1kHz, 20%-SSD-70%

Step-Size hnearity

I - 1kHz, 20%-SS0-70%

Step-Size linearity
IR
IR

Vo

Max

1.8

VRMS
150

mVRMS

-1.5

1.5

de

-1.5

1.5

de

I = 100Hz, SSD = 90%

-2.5

1.0

dB

Frequency response

I - 2kHz, SeD = 10%

-1.0

1.0

dB

Frequency response

I = 5kHz, SeD - 20%

-1.0

1.0

dB

IR

Frequency response

I - 7kHz, SeD - 30%

-1.0

1.0

dB

IR

Frequency response

I = 8kHz, SeD - 40%

-10

1.0

dB

IR

Frequency response

I = 10kHz, SeD = 50%

-1.0

1.0

de

IR

Frequency response


+10

1%tHD
_RECORD MODE
1kHz

~

....
..
0
0

+10 B

0.1

:::>

Od

0

0.01

/

/

10
100

+20

V

/'"

14

:::>

12

V

/

16

~

:r

0.01

-20

18

!

./

I

ee=1

i
Z

0

a:
c
:r

20

!

g

lIE

~

Maximum Signal Handling
vs Supply Voltage

1K

10K

FREQUENCY (Hz)

OUTPUT (dB)

8

10

12

14

18

18

Vee - SUPPLY VOLTAGE (VOLTS)
OP1012OE1

Supply Current vs
Supply Voltage
20

C

..g

zw

a:
a:
u
~

:::>

15

V f..--

..
.

:::>

I

"

----

10

J!

10

12

14

18

18

Vee - SUPPLY VOLTAGE (VOLTS)

APPLICATION INFORMATION
The NE645/646 IS a direct replacement for
the NE645B/646B. The NE645/646 Incorpo-

November 14, 1986

rates Improved design techniques to insure
excellent performance reqUired In Dolby B
and C Type Audio NOise Reduction Systems.
Critical component values are unchanged

7-184

except for C309 on Pin 1 which is now an
optional component in spec'ific applications
defined by Dolby Laboratones. All circuit
parameters are guaranteed at 12V Vce.

Signetics Linear Products

Product Specification

NE645/646

Dolby Noise Reduction Circuit

DOLBY ENCODER Output for constant level input (single tone frequency response)
Input Level (dB)
Frequency
(kHz)

0
(Dolby
Level)

-5

-10

-15

-20

-25

-30

-35

-40

0.1

0

0.1

0

0.1

0

0

0

0

0

0.14

0

0.2

0.2

0.2

0.2

0.2

0.1

0.2

0.1

0.2

0

0.3

0.4

0.5

0.5

0.6

0.6

0.5

0.5

0.3

0

0.3

0.6

1.1

1.3

1.3

1.3

1.3

1.3

2.0

2.1

2.2

2.3

2.1

2.6

2.9

2.9

3.0

2.9

3.6

3.7

3.8

3.7

0.4
0.5

0

0.3

0.8

1.8

0.6
0.7

0

0.4

0.9

2.1

3.5

0.8

4.3

4.4

4.5

4.4

4.8

5.0

5.3

5.1

5.6

5.8

5.6

6.1

6.3

6.2

6.9

7.1

7.1

6.6

7.5

7.7

7.7
8.9

0.9
1.0

0

0.4

1.0

2.3

4.2

5.7

1.2
1.4

0

0.3

0.9

2.3

4.4

2.0

0.1

0.4

0.9

2.2

4.3

7.0

8.5

8.9

3.0

0.2

0.6

0.9

1.9

3.9

6.6

8.8

9.7

9.7

5.0

0.3

0.6

1.0

1.7

3.2

5.4

8.2

10.0

10.3

7.0

0.3

0.6

1.0

1.7

2.8

4.7

7.3

9.7

10.4

10.0

0.4

0.7

1.1

1.7

2.6

4.2

6.5

9.1

10.4

14.0

0.5

0.8

1.1

1.8

2.7

4.4

6.5

8.7

10.3

20.0

0.7

0.7

1.2

1.9

2.7

4.4

6.5

8.7

10.3

NOTE:
The figures given In this table are the average response of many of Dolby Laboratones' professional encoders, and are not intended to be taken as required
consumer equipment performance charactensbcs. Thus, no Inference should be drawn on the tolerances whICh lICensees must relaln In consumer equipment The
figures can, however, be used to plot typical charactensbcs.

November 14, 1986

7-185

•

Product Specification

Signetics Linear Products

NE645/646

Dolby Noise Reduction Circuit

TEST CIRCUIT

C206
tOpF
1SVDC

~-----4-----t7i: ~
0309

"

14 R304
270K
C208

J

470pF

0 ...

C304

180

rO.047pF

5%

10l'F

' -..H..------+--~
ClOt

C302

~F 002~~I

15VDC

0301
3.3K

1%

NOTE:
All resIstors standard and are measured

November 14, 1986

In

n

"Optional capacitor In specifiC applications defIned by Dolby Laboratones

7 .. 186

C'"

J,0.114F
0305
180K

15

C307
JO.33p F

Signetics

NE649
low Voltage Dolby Noise
Reduction Circuit
Product Specification

Linear Products

DESCRIPTION
The NE649 is an audio noise reduction
circuit designed for use In low voltage
entertainment systems. The circuit is
used to reduce the level of background
noise introduced during the recording
and playback of audio signals on magnetic tape and Improve the noise
Dolby IS a trademark of Dolby Laboratones LicenSing Corporation

level in FM broadcast reception. The
circuit is intended for use in automotive
and portable cassette Dolby™ 8-Type
noise reduction systems. This circuit is
available only to licensees of Dolby Laboratories Licensing Corp., San Fran-

PIN CONFIGURATION
N Package

CISCO.

FEATURE
• Low voltage operation

APPLICATION
• Tape decks

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

16-Pln Plastic DIP

ORDER CODE

+70'C

NE649N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

16

V

Operating temperature range

-40 to +85

'C

TSTG

Storage temperature range

-65 to + 150

'C

TSOLD

Lead soldenng temperature 10sec max

+300

'C

Vcc

Supply voltage

TA

•

BLOCK DIAGRAM
16

October 7, 1987

7-187

853-1193 90826

Signetics Linear Products

Product Specification

Low Voltage Dolby Noise Reduction Circuit

NE649

DC ELECTRICAL CHARACTERISTICS Vcc = 9V, I = 20Hz to 20kHz. All levels relerenced to 580mVRMs (OdB) at Pin 3,
TA = + 25°C, unless otherwise specilled.
NE649
SYMBOL
Vcc

PARAMETER

TEST CONDITIONS

Supply voltage range3
Minimum voltage supply lor
8dB headroom
1Od B headroom

Icc

Supply Current

Icc

Supply Current 1

1= 1.4kHz
THO < 1%

Typ

Max

6

9

14

6.5
7.5

Av

Voltage gain (PinS 5 - 3)

Av

Voltage gain (Pins 3 -7)

I = 1kHz, OdB at Pin 3,
noise reduction out

V
V
V

11

I = 1kHz
(Pins 6 and 2 connected)

Distortion

UNIT
Min

18

mA

20

mA

24.5

26

27.5

dB

-0.5

0

+0.5

dB

0.05
0.2

0.2
0.5

%
%

I = 20kHz to 10kHz, OdB
I = 20Hz to 10kHz, + 10dB

Signal Handling
(See Performance Characteristics)

SIN

Signal-to-noise rati0 2

Record
(PinS 6 and 2 connected)
Playback
(Pins 6 and 2 connected)

Record mode Irequency
response (at Pin 7) relerenced to
encode
monitor pOint (Pin 3)

Back-to-back Irequency response

64

72

dB

74

82

dB

!I = 1.4kHz
OdB
-20dB
-30dB

-1.5
0
-17.1 -15.6
-24.0 -22.5

+1.5
-14.1
-21.0

dB
dB
dB

I = 5kHz
OdB
-20dB
-30dB
-40dB

-1.2
+0.3
-18.3 -16.8
-23.3 -21.8
-30.2 -29.7

+1.8
-15.3
-20.3
-28.2

dB
dB
dB
dB

I = 20kHz
OdB
-20dB
-30dB

-0.8
-18.8
-25.0

+2.2
-15.8
-22.0

dB
dB
dB

USing typical record mode response

R'N

Input resistance

Pin 5
Pin 2

ROUT

Output resistance

Pin 6
Pin 3
Pin 7

+0.7
-17.3
-23.5
± 1.5

db

35
3.1

50
4.2

65
5.3

kn
kn

1.9

2.4
80
80

3.1
120
120

kn
n
n

Record mode Irequency response shift
vs temperature
vs Vee

o to 70°C
-40 to 85°C
6 to 14V

NOTES:
1. With electroniC sWitching
2. All nOise levels are measured CCIR/ARM weighted uSing a 10k source with respect to Dolby level See Do/by LaboratOries Bulletin 19.
3 The Circuit Will function as low as Vee = 4 5V (I,e, output signal present) See graphs of Icc and signal handling vs Vee.

October 7, 1987

7-188

dB
dB
dBIV

Product Specification

Signetics Linear Products

NE649

Low Voltage Dolby Noise Reduction Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
(OdB) THO vs Frequency

(+ IOdB) THO vs Frequency
1. 0

1.0

'i.

9V

cO. 1

1

::<:
....
14Y

6V

0.0 1
100

lK

..-

0.01
100

10K

9Y

:v

~
14Y

lK

10K

FREQUENCY (Hz)

FREQUENCY (Hz)

Current vs Supply Voltage

Maximum Signal Handling
vs Supply Voltage for
10/0THO (Record)
17

15

13
1

:> 15
4O'C
j""Ii"!l'I

:;or

+100'~

4

.

II 11
ID

C

;g

9

~

7

-'
w

>
~

....
::>
l!:

1
::>
0-1

10 12
Vee (V)

October 7, 1987

14

16

-3

18

6

8

10

12

SUPPLY YOLTAGE(V)

7-189

14

16

Signetics Linear Products

Product Specification

Low Voltage Dolby Noise Reduction Circuit

NE649

DOLBY ENCODER Output for constant level input (single tone frequency response)
INPUT LEVEL (dB)
FREQUENCY
(kHz)

0
(DOLBY
LEVEL)

-5

-10

-15

-20

-25

-30

-35

-40

0.1

0

0.1

0

0.1

0

0

0

0

0

0.14

0

0.2

0.2

0.2

0.2

0.2

0.1

0.2

0.1
0.5

0.2

0

0.3

0.4

0.5

0.5

0.6

0.6

0.5

0.3

0

0.3

0.6

1.1

1.3

1.3

1.3

1.3

1.3

2.0

2.1

2.2

2.3

2.1

0.4
0.5

0

0.3

0.8

1.8

2.6

0.6
0.7

0

0.4

0.9

2.1

3.5

0.8

2.9

2.9

3.0

2.9

3.6

3.7

3.8

3.7

4.3

4.4

4.5

4.4

4.8

5.0

5.3

5.1

5.6

5.8

5.6

6.1

6.3

6.2
7.1

0.9
1.0

0

0.4

1.0

2.3

4.2

5.7

6.9

7.1

1.4

0

0.3

0.9

2.3

4.4

6.6

7.5

7.7

7.7

2.0

0.1

0.4

0.9

2.2

4.3

7.0

8.5

8.9

8.9

3.0

0.2

0.6

0.9

1.9

3.9

6.6

8.8

9.7

9.7

5.0

0.3

0.6

1.0

1.7

3.2

5.4

8.2

10.0

10.3

1.2

7.0

0.3

0.6

1.0

1.7

2.8

4.7

7.3

9.7

10.4

10.0

0.4

0.7

1.1

1.7

2.6

4.2

6.5

9.1

10.4

14.0

0.5

0.8

1.1

1.8

2.7

4.4

6.5

8.7

10.3

20.0

0.7

0.7

1.2

1.9

2.7

4.4

6.5

8.7

10.3

NOTE:
The figures given In this table are the average response of many of Dolby Laboratories' professional encoders, and are not Intended to be taken as required
consumer equipment performance charactenstlCS, Thus, no Inference should be drawn on the tolerance which licensees must retain in consumer equipment. The

figures can, however, be used to plot typical characteristics.

October 7, 1987

7-190

Signetics Linear Products

Product Specification

Low Voltage Dolby Noise Reduction Circuit

NE649

TEST CIRCUIT

C...
10/,F

15VDC

~----~~---;~: ~
··R308

"
e202
220pF

+
INPUT AMP

15VDC~

r--+"+-+----;
13

J

C2------~--~~~~~

14 R304
27GK

...

1.

R30I

C307

Jo.33,oF
Rao.
UK

.""

ro,,,,,,,
NOTES:
All reststors standard and are measured In

n

..OptIonal capacitor In SpecdlC appltcattons defined by Dolby laboratones

November 14, 1986

7-196

Signetics

Symbols and Definitions for
Audio Power Amplifiers

Linear Products

Bridge-Tied Load (BTL)

Noise Output Voltage (VN(RMS»

Ripple Rejection (RR)

An application where the outputs of two
amplifiers are tied to opposite ends of a
load (speaker) thereby increasing the
output power level to the load.

The output noise voltage for a given set
of conditions.

The measure of the amplifier's ability to
reject influences of power supply voltage
variations (ripple).

Output Power

Signal-to-Noise Ratio (SIN)

Channel Separation

The power available to the load for a
given set of conditions.

The measure of the electrical isolation
between two or more independent
monolithic circuits.

Peak Output Current

The ratio of recoverable signal level to
the noise level generated by the amplifi-

The maximum instantaneous current
available from the amplifier output.

Standby Current (ISB)

Input Sensitivity
The minimum signal magnitude required
to drive the output to a given output
power level.

Repetitive Peak Output Current
The maximum operating current available from the amplifier output.

er.

The supply current drawn by the device
when operated with no load.

Total Harmonic Distortion (THO)
The measure of the amplifier's ability to
amplify only the input signal without
introducing any harmonic interference.

•
December 1988

7-197

TDA1010A

Signe1ics

6W Audio Amplifier with
Preamplifier
Product Specification

Linear Products
DESCRIPTION
The TDA1010A is a monolithic integrated class-B audio amplifier circuit in a 9lead single in-line (SIP) plastic package.
The device is primarily developed as a
6W car radio amplifier for use with
and
load impedances.

4n

2n

FEATURES
• Single in-line (SIP) construction
for easy mounting
• Separated preamplifier and power
amplifier
• High output power
• Low cost external components
• Good ripple rejection
• Thermal protection

PIN CONFIGURATION
POWER AMP GROUND 1

APPLICATIONS
• Stereo power amplifier
• Television
• Radios
• Intercom
• Alarms
• Modems

POWER AMP OUTPUT 2
POWER AMP vee
COMPENSATION 4
PREAMP vee
POWER AMP INPUT
PREAMP OUTPUT 7
PREAMP INPUT 8
PREAMP GROUND
lOPYiEW
CDl1220S

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-110B)

-2S·C to +150·C

TDA1010AU

TEST CIRCUIT
C2
lIIOnF

AI 330k

~~--~~--~----~~

+

6

November 6, 1986

7-198

853-0912 86388

Signetics Linear Products

Product Specification

6W Audio Amplifier with Preamplifier

TDA1010A

HEATSINK DESIGN
10

Assume Vee = 14.4V; RL = 2>2; TA = 60°C
maximum; thermal shutdown starts at
TJ = 150°C. The maximum sinewave dissipation In a 2>2 load is about 5.2W. The maximum dissipation for music drive will be about
75% of the worst-case sinewave dissipation,
so this will be 3.9W. Consequently, the total
resistance from junction to ambient

\
\

1\

\

8JA = 8JTAS + BrASH + 8HA

\
o

-25 0

150-60

\

= - - - = 23°C/W.
3.9

150

Since 8JTAS = 10°C/W and BrASH = 1'C/W,

Figure 1. Power Derating Curve

8HA = 23- (10 + 1) = 12°C/W.

ABSOLUTE MAXIMUM RATINGS (TA=25'C)
RATING

UNIT

Vee (MAX)

SYMBOL

Supply voltage

PARAMETER

24

V

Icc

Peak output current

5

A

lee (Rep)

Repetitive peak output current

3

A

PTOT

Total power dissipation

see derating curve in Figure 1

TSTG

Storage temperature

-65 to +150

'C

TA

Operating ambient temperature

-25 to +150

'C

tsc

AC short-circuit duration of load during sinewave drive;
without heatsink at Vee = 14.4V

max. 100

hours

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply voltage range

lOAM

Repetitive peak output current

ITOT

Total quiescent current at Vcc = 14.4V

November 6, 1986

Typ

6

Max

24
3
31

7-199

V
A
mA

•

Product Specification

Signetics Linear Products

TDA1010A

6W Audio Amplifier with Preamplifier

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 14.4V; RL = 4n; f = 1kHz, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Po
Po
Po
Po
Po

Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
resistor of

RL = 2n1
RL = 4n1, 2
RL = sn 1
RL = 4n; without bootstrap
RL = 2n; with additional bootstrap
220n between Pins 3 and 4

AVl
AV2
Av TOT

Voltage gain
preamplifier3
power amplifier
total amplifier

5.9

21
27
51

Typ

6.4
6.2
3.4
5.7

W
W
W
W

9

W

24
30
54

dTOT

Total harmonic distortiOn at Po = 1W

0.2

'7

EffiCiency at Po = 6W

75

B

Frequency response (-3dB)

Iz,1
IZII

Input Impedance
preampllfler4
power amplifierS

20
14

IZol

Output impedance of preamplifier; Pin 7s

14

VO(RMS)

Output voltage preamplifier (RMS value)
dTOT < 1% (Pin 7)3

0.7

VN(RMS)
VN(RMS)

Noise output voltage (RMS value)6
Rs=on
Rs = S.2kn

RR
RR

Ripple rejectiOn at f = 1kHz to 10kHz7
at f = 100Hz; C2 = l/lF

V,

Sensitivity for Po

14(RMS)

Bootstrap current at onset of clipping; Pin 4 (RMS value)

SOHz

%

40
26

kn
kn

20

26

kn
V
mV
mV
dB
dB

10

mV

30

mA

3. Measured with a load Impedance of 20kU.
4 Independent of load Impedance of preamplifier.
5 Output Impedance of preamplifier (fZol) IS correlated (Within 10%) With the Input Impedance (I Z, ij of the power amplifier.
6. Unwelghted RMS nOise voltage measured at a bandWidth of 60Hz to 15kHz (12dB/octave)

7-200

%

30
20

NOTES:
1 Measured With an ideal coupling capacitor to the speaker load.
2. Up to Po <3W: dTOT<1%

November 6, 1986

dB
dB
dB

kHz

42
37

7 Ripple rejection measured With a source Impedance between 0 and 2k!2 (maximum ripple amplitude: 2V).
8. The tab must be electrically floating or connected to the substrate (Pin 9)

27
33
57

15

0.3
0.7

= 5.8W

Max

Product Specification

Signetics Linear Products

TDA1010A

6W Audio Amplifier with Preamplifier

30

I

RL =

22
42
82

10 1-+-+-+-+-I--'i1~£""''-+-l

1

20

10

-5

10

I (Hz)

NOTES:
Solid Imes mdlcate the power across the load,
dashed Imes that available at Pin 2 of the
TOA1010 RL "" 2n{l) has been measured with an
additional 220n bootstrap resistor between PinS 3
and 4 Measurements were made at f = 1kHz.
dTOT"" 10%, TA = 25°C

Figure 4. Frequency Characteristics
of the Test Circuit for Three Values
of Load Impedance. Po
Relative to OdB 1W; Vee 14.4V

=

Figure 2. Output Power of the Test
Circuit as a Function of the Supply
Voltage with the Load Impedance as
a Parameter; Typical Values

,

,

,,82

,

r-

,,42

2£

4~

•

o

I

Figure 6. Thermal Resistance from
Heatslnk to Ambient of a 1.5mm
Thick Bright Aluminum Heatslnk
as a Function of the Single-sided
Area of the Heatsink With the Total
Power Dissipation as a Parameter

80

22

~

8Q

42

I- -

40

20

o

I
NOTE:
For Rl ==
an external bootstrap resistor of 2200
has been used; typical values Vee'" 14 4V.
f= 1kHz

2n

~

2
10

NOTES:
Solid Imes mdlcate the power across the load,
dashed Imes that available at Pm 2 of the
TDA1010. RL'" 2(2(1) has been measured wrlh an
additional 220Q bootstrap resistor between Pins 3
and 4 Measurements were made at f = 1kHz,
Vee = 144V

Figure 5. Total Power Dissipation
(Solid Lines) and the Efficiency
(Dashed Lines) of the
Test Circuit; a Function of the
Output Power With the Load
Impedance as a Parameter

Figure 3. Total Harmonic Distortion
in the Test Circuit as a Function
of the Output Power with the Load
Impedance as a Parameter;
Typical Values

November 6, 1986

100

I

2.5

IIII~

25
50
75
HEATSINKAREA(cm2j

~

I

J I

P,.".=

r- ::: ::j~w
5W

100

, ,,""..

~
; ~

I I
7.5

.......
.......

1\.~22

I
I

I

=

VV

10

R)82

o
o

11)3

10

20

vee (V)

"t'... ~

7-201

•

Product Specification

Signetics Linear Products

TDA1010A

6W Audio Amplifier with Preamplifier

C2
100nF

Rl330k

~~--~~--~----~r-~--~+

C7

lOO"F
TDA1010A

C10

VOLUME

27nF

VI

RS

CS

22k

1OOO"F

R4
1.Sk
7 C3
100nF

RL

C1l

C4

180nF

lnF

Figure 7. Complete Mono Audio Amplifier of a Radio

November 6, 1986

7-202

Vee

TDA1011

Signetics

2 to 6W Audio Power Amplifier
with Preamplifier
Product Specification
Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA 1011 is a monolithic integrated
audio amplifier circuit in a 9-lead single
in-line (SIP) plastic package. The device
is especially designed for portable radio
and recorder applications and delivers
up to 4W in a 4Q load impedance. The
device can deliver up to 6W into 4Q at
16V loaded supply in mains-fed applications. The maximum permissible supply
voltage of 24V makes this circuit very
suitable for DC and AC apparatus, while
the low applicable supply voltage of 3.6V
permits 6V applications. The power amplifier has an inverted input! output which
makes the circuit optimal for applications
with active tone control and spatial stereo.

• Single in-line (SIP) construction,
for easy mounting
• Separated preamplifier and power
amplifier
• High output power
• Thermal protection
• High input impedance
• Low current drain
• Limited noise behavior at radio
frequencies

POWER AMP GROUND 1
POWER AMP OUTPUT 2
POWER AMP Vee

3

COMPENSATION

4

PREAMP Vee

5

POWER AMP INPUT 6
PREAMP OUTPUT 7
PREAMP INPUT 8
PREAMP GROUND 9

APPLICATIONS
•
•
•
•
•

lOP VIEW

Radios
Television
Intercom
Modems
Alarms

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-11 OB)

-25·C to +150·C

TDA1011U

TEST CIRCUIT

-rr

100nF

R1
330k

+
TOA1011A

August 1, 1988

7-203

853-0913 94022

Product Specification

Signetics Linear Products

TDA1011

2 to 6W Audio Power Amplifier with Preamplifier

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vcc

Supply voltage

24

V

10M

Peak output current

3

A

PTOT

Total power dissipation

SYMBOL

PARAMETER

see derating curve Figure 1

TSTG

Storage temperature range

-65 to + 150

TA

Operating ambient temperature range

-25 to +150

'C
'C

tse

AC short-circUit durallon of load during sine wave drive;
Vee=12V

100

hours dnve;
Vec = 12V

DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vee

Supply voltage range

IORM

Repetitive peak output current

ITOT

Total qUiescent current at Vee = 12V

August 1. 1988

Typ

20

3.6

14

7-204

Max

V

2

A

22

mA

Signetics Linear Products

Product Specification

TDA1011

2 to 6W Audio Power Amplifier with Preamplifier

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vec = 12V; Rl = 4U; f = 1kHz, unless otherwise specified; see also Test
CircuIt.
LIMITS
PARAMETER

SYMBOL

UNIT

Po
Po
Po
Po
Po

AF output power dTOT = 10% with bootstrap:
Vec = 16V; Rl = 4U
Vec = 12V; Rl = 4U
Vee = 9V; Rl = 4U
Vee = 6V; Rl = 4U without bootstrap:
Vce = 12V; Rl = 4U

AV1
AV2
Av TOT

Voltage gain:
preamplifier2
power amplifier3
total amplifie~

dTOT

Total harmonic distortion at Po = 1.5W

B

Frequency response; -3dB'

Izl1 1
Izo1 1

Output Impedance preamplifier

VO(RMS)

Output voltage preamplifier (RMS value)
dTOT< 1%2

VN(RMS)
VN(RMS)

Noise output voltage (RMS value)6
Rs=OU
Rs= 10kU

VN(RMS)

Noise output voltage at f = 500kHz (RMS value)
B = 5kHz; Rs = OU

RR
RR

Ripple rejection 6
f= 1 to 10kHz
f = 100Hz; C2 = I/lF

I'(RMS)

Bootstrap current at onset of clipping; Pin 4 (RMS value)

Min

Typ

3.6

65
4.2
2.3
1.0
3.0

21
27
50

23
29
52
0.3

60Hz

Input impedance preamplifier5

100

Max

W
W
W
W
W
25
31
54

dB
dB
dB

1

%

15kHz
200

kU

1

kU

0.7

V
0.2
0.6

1.4

mV
mV

8

pV

42

dB
dB

35

rnA

35

NOTES:
1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20kfl.
3. Measured with R2 = 20kfl.
4. Measured at Po = 1W; the frequency response IS mainly determined by C1 and C3 for the low frequencies and by C4 for the high frequencies.
5. Independent of load Impedance of preamphfler.
6. Unweighted RMS nOise voltage measured at a bandwidth of 60Hz to 15kHz (12d8/octave).

August I, 1988

7-205

•

Signetics Linear Products

Product

2 to 6W Audio Power Amplifier with Preamplifier

Spec~ication

TDA1011

HEATSINK DESIGN
7.5

Assume Vee = 12V; RL = 4n; TM = 60·C
maximum; Po = 3.8W.
The maximum sinewave dissipation is 1.8W.

\

\~NFlNITE

WITHOUT
r---- ~HEATSINK

HEATSINK

OJA = OJTAB

25

~
o

-25

0

+50

The derating of 10·C/W of the package
requires the following external heatsink (lor
sinewave drive):

~

+100

+150

+ ~ABH + OHA

150-60
= - - - = 50·C/W.
1.8
Since OJTAB = 10·C/W and ~ABH
OHA = 50 - (10 + 1) = 39·C/W.

+200

= l·C/W,

TA (,C)

J = II

Figure 1. Power Derating Curve

L

..

1

jb

/ II
/1

!o

t-----~~--~r_------~~----~-----o+

4n

2.5

~/

I~

o
o

VCC(V)15

10

20

25

RL VjCC
40

NOTES:
droT = 10%, typical values The available output
power IS 5% higher when measured at Pin 2 (due to
series resistance of C1), *

Figure 5. Output Power Across RL
as a Function of Supply
Voltage with Bootstrap
Figure 2. Circuit Diagram of a 4W Amplifier

lo'MU..

40

F-Ff

!-

~
TYP

//

2.5

10

20

f-H-Hl-Hlf--l-f*1-HJj1t--H-'/IIHttH

30

Vee (V)

Figure 3. Total Quiescent Current as a
Function of Supply Voltage

10

f(MHz)

Po(W)

NOTES:
- with bootstrap, - - - without bootstrap,
f "" 1 kHz, tYPical values The available output
power IS 5% higher when measured at Pm 2
(due to senes reSIstance of C10)

Figure 4. Total Harmonic Distortion as
a Function of Output Power Across RL

August 1, 1988

°llllli

j'

/"

V
o
o

A

B

7-206

NOTES:
Curve A. total amplifier, curve B power amplifIer,
S "" 5kHz. Rs "" 0, typical values

Figure 6. Noise Output Voltage as a
Function of Frequency

TDA1013A

Signetics

4W Audio Amplifier with DC
Volume Control
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA1013A is a monolithic integrated 4W audio amplifier circuit with DC
volume control in a 9-pin single in-line
(SIP) plastic package. The wide supply
voltage range makes this circuit very
suitable for applications such as television receivers and record players.

•
•
•
•

PIN CONFIGURATION

DC volume control
SIP package
I.ow distortion
I.ogarithmic control

U Package

APPLICATIONS
•
•
•
•
•

The DC volume control stage has a
logarithmic control characteristic with a
range of more than aOdS. Control can
be obtained by means of a variable DC
voltage between 3.5 and av.

Computers
Intercom
AM/FM Radio
Television
Modems

The audio amplifier has a well-defined
open-loop gain and a fixed integrated
closed-loop gain. This offers an optimum
in number of external components, performance and stability.

9

DC CONTROL AMP GROUND

8

DC CONTROL AMP INPUT

7

CONTROL VOLTAGE

6

oc CONTROL AMP OUTPUT

5

POWER AMP INPUT

4

BYPASS

2

POWER AMP OUTPUT

,

POWER AMP GROUNO

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-110B)

-25'C to + 150'C

TDA1013AU

BLOCK DIAGRAM

.,f""lc,
- i;i

'.F

~

o.'.FT~-

R4
220K

TDA,013A

C,
O.1",F

0--1 ,
.......
C9

......

~

8

220pFT

.vp
Cl0

~ 470~F

3

AMPLIFIER

/'"

2

IC

7

S

6

,r

:

C6

O.1,u.F

lC7
470""F

C.

TO.'.F

RS
3.3

R3
S.6K

R,
7K
R2
581l

:!:

AU~'
/ ,

UNIT

•

•

C8

~f~.F

UK

:~ ~~

nF
~

+vp

R2
81l

BDOI271S

November 6, 1986

7-207

853-0914 86390

Product Specification

Signetics Linear Products

4W Audio Amplifier with DC Volume Control

TDA1013A

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNITS

Vee

Supply voltage

35

V

IOSM

Non-repetitive peak output current

3

A

IORM

Repetitive peak output current

TSTG

Storage temperature range

TJ

Junction temperature range

PTOT

Total power dissipation

1.5

A

-65 to + 150

°C

-25 to +150

°C

see derating curve, Figure 2

DC AND AC ELECTRICAL CHARACTERISTICS

Vee ~ 18V; RL ~ 8!1; f ~ 1kHz, TA ~ 25°C, unless otherwise specified.

LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vec

Supply voltage

ITOT

Total quiescent current

Typ

15

Max

35
35

Vn

NOise output voltage (see note)

V,

Total sensitivity (DC control at maximum gain)
for Po ~2.5W

f

Frequency response (-3dB)

38

55

35Hz

V

mA
1.4

mV

69

mV

20

kHz

Audio amplifier

IORM

Repetitive peak output current

Po

Output power at dTOT ~ 10%

dTOT

Total harmonic distortion at Po

Av

Voltage gain

V,

Sensitivity for Po

IZII

Input Impedance (Pin 5)

~

1.5
4
~

2.5W

0.5

2.5W
100

A
W

4.5
1

%

30

dB

125

mV

250

k!1

DC volume control unit

I/J

Gain control range (see Figure 1)

80

V,
V,

Signal handling at dTOT < 1%
(DC control at OdB)
sensitivity for Vo ~ 125mV at maximum voltage gain

1.2

Iz,1

Input Impedance (Pin 8)

100

250

Izol

Output Impedance (Pin 6)

100

200

Measured In a bandwidth according to lEG 179 curve 'A', As = 5kn and DC control at minimum gain

7-208

V
mV

55

NOTE:

November 6, 1986

dB

k!1
400

!1

Signetics Linear Products

Product Specification

TDA1013A

4W Audio Amplifier with DC Volume Control

HEATSINK DESIGN

L

I
,
>"5

~ 6

"-

Assume Vee = lav; RL = an; T A = 60'C
(maximum); TJ = 150'C (maxImum); for a 4W
application into an an load, the maxImum
dIssipatIon IS about 2.5W. The thermal reSIstance from junctIon to ambIent can be expressed as:

/

"""'i'.

3
+20

.......

~

/

i'.....

~

//

~

/JJA = /JJTAB

/

.............
~

~

_

~

o(dB)

~

'7 (mA)

u

+ 8rABH + /JHA

_TJ::....:::MAXc::.--_T..:.;Ac..:M:::.A::.:X __
15_0_-_6_0 = 36'C/W.
PMAX
2.5

Since /JJTAB = 9'C/W and 8rABH = 1'C/W,

Figure 1. Typical Values Gain Control

!

g

\

4

IL 3.3

1'-.....

.........

.........
o

o

50

\

... ... ........
,~

100

150
OP11290S

NOTE:
_ _ Inftnrte heabMnk
- - - - Without heatsmk

Figure 2. Power Derating Curve

November 6, 1986

7-209

OHA

= 36 -

(9

+ 1) = 26'C/W.

Signetics

AN148
Audio Amplifier with TDA1013A
Application Note

Linear Products

Author: D. Udo

ABSTRACT
ELECTRONIC
FILTER

The 9-pm SOT -11 OB-encapsulated
TDA 1013A is an audIo power amphfler that
has a DC volume control on-board. The
devIce is designed for audio amphfler applicatIons in TV sound channels.
At a supply voltage of laV, the output power
is about 4.4W Into an an loudspeaker.
The gain control range is > aOdB wIth a DC
control voltage from a to 3.5V.

INPUT

8

.L

9

~

Some basic Information of the TDA1013A is
dealt WIth In this applicatIon note. Detailed
performance properties are gIven for an 1av
Into an application.

CONTROL
I5~N

r-P~
~
TDA1013A

V
7

5

6

"

SUPPLY VOLTAGE

3

4

2

OUTPUT

1
-::-

DC VOLUME
CONTROL
TC01210S

INTRODUCTION

Figure 1

The TDA 1013A has two functions: a DC
volume control and audio power amphfier.
Some performance characteristics are:
• Supply vonage range
15 - 35V
• Max. repetibve peak current
1.5A
• Max. non-repetItive peak current
3A
•
•
•
•
•

OJTAB
9°C
OJA
45°C
Input impedance (Pins 5 and a) 100kn
Output impedance (Pin 6)
2000. (typ.)
Voltage gain DC control part
(Pins a to 6)
7dB

• Voltage gain power amplifier
(Pins 5 to 2)

30dB

APPLICATION CIRCUIT
The complete applIcation circuit is gIven in
Figure 1. WIth hIgh input impedance, Cg is
necessary to fIlter-out RF Input interferences.
Rs in combinatIon with Cs is used to limit the
AF frequency bandwidth. The 470/lF power
supply decoupling capacitor IS C1o.

December 19aa

7-210

a53-0914 a6390

Signetics Linear Products

Application Note

Audio Amplifier with TDA1013A

AN148

R4

220K

C8~

o.1.F

+---.....--~------o+vp
C10

~.70oF

TOA1Q13A

C,
O.1I'F

o-j~,+-----1
C9

......

220pFT

+-+=---1

C4

O.'oF
R.

R2

all

UK

7K

sall

R5
3.3

R3

R,
C3

100.F

UK

C5

1.5 nF

+Yp

Figure 2. Block Diagram and External Components

•
December 1988

7-211

Application Note

Signetics Linear Products

AN148

Audio Amplifier with TDA1013A

MEASUREMENTS
Vanous measurements made In the circUit of
Figure 1 are given. If not otherwise stated, the
measurements are done at Vee = lBV,
RL = Bn, I = 1kHz and TA = 2S0C.

so

40

I

, , , ...

--t-

------

~

Quiescent Current Consumption
The quiescent current as a function of vee is
given in Figure 3. At Vee = lBV the maximum
spraad on 20 samples is indicated by arrows.

Mldtap Voltage
The midtap voltage VA versus Vee at output
Pin 2 is shown in Figure 4.

Output Power and Dissipation
20

.

<>J.
00

'S

'0

20

35

30

Vp SUPPI.Y VOLTAGE (V)

Distortion
The total harmonic distortion as a function of
Po is shown In Figure 7 for signal frequencies
of 1 and 10kHz (DC control voltage at Pin 7 is
constant BV). In Figure B the same curve is
given for f = 1kHz but now the output power
is reduced by the DC control voltage (at
d = 10% Voc Pin 7 = BV). The distortion for
2.SW output power versus frequency is given
in Figure 11. In Figure 9, the distortion of the
DC gain-controlled preamplifier as a function
of the signal excursion at Pin 6 is shown for a
DC control voltage (Voc Pin 7) of BV.

Figure 3. Quiescent Current va Vcc

..
20

•

V~

0

......

>J\
00

"
'0

n

'5

..

30

Vp SUPPLY VOf..TAGE (V)

Figure 4. Mldtap Voltage va Vee

December 1988

/

/
20

The output power lor d = 10% as a function
of Vee at Pin 2 and across the Bn loudspeaker load is given in Figure S. The upper curve
gives the worst-case sinewave dissipation.
The dissipation versus output power for
Vee = 1BV is given in Figure 6.

7-212

35

Application Note

Signetics Linear Products

AN148

Audio Amplifier with TDA1013A

Gain Control
0
f;;:; 1kHz.
RL=80

j=

10%, VCONTRlL PIN 7 "" 8V

. ..- ....

8

.;;~

I

WORST-CASE

DISSIPATION - .

6

,,'"

....
4

..?A
00

/~UTPUT AT
PIN2
~OUTPUT

ACROSSRL

" ';/
,,/}
"'/~

Power Bandwidth

,,-:,." ~I

17.5

Supply Voltage Ripple Rejection
The supply voltage ripple rejectIon versus
frequency IS shown In Figure 14 for Rs = 0
and 10kn. RIpple voltage on Pin 3 IS
500mVRMs·

20

22.5

25

27.5

Vp SUPPLY VOLTAGE (V)

vp ~ ,ai,

VCONTROL

f~'kHz,RL~811

~
o

/"

,If

~

p.J

7

~

8V

CONCLUSION
The TDA1013A IS a sUItable IC as an audIO
amplifIer In TV receivers. It delIvers an output
power of about 4.4W In RL = Sn at
Vcc = 1SV. An SOdB DC gain control IS Incor·
porated.

r---- ........

•

i
I

PO(W)

Figure 6. Dissipation vs Po

December 1985

Noise Behavior
The A,weighted, IEC 179 standard, signal·tonOIse ratio at maximum gain (VDC Pin 7 = SV)
IS 6SdB at Rs = on and related to Po = 2.5W.
Increasing Rs has hardly any Influence on this
noise level. Typical SIN is 74dB.

Figure 5. Output Power and Dissipation vs Vcc

0.

Frequency Characteristic
The frequency characterostlc is presented in
Figure 12. The - 3dB bandwidth IS from 32Hz
to 20kHz.
The power bandwIdth (d = 10%) IS gIven In
Figure 13. The low frequency behaVIor IS
determIned by the value of the output electro·
lytic Cr .

.......::..:::, ~OUTPUT POWER Po

~
'5

The tYPIcal overall voltage gain (VDC PIn
7 ~ SV) IS 3SdB. The gain control curve
versus the DC control voltage on Pin 7 IS
shown In Figure 10.

7-213

Signetics Linear Products

Application Note

Audio Amplifier with IDA 10 13A

AN148

12

10
Vp= lBV
VCONTROL = BV = CONSTANT

l

I

I

Q

10kHz

~lkHz

H

I

---..;:::fj

.- .....

1-.

0
0.1

10

PO(W)

Figure 7. Distortion vs Po

12

10

I

Vp=lBV,f=l_
VCONTROL = 8V at Po

= 4AW

I

,..../

IV

0
0.1

10
PO(W)

Figure 8

December 1988

7·214

Application Note

Signetics Linear Products

AN148

Audio Amplifier with TDA1013A

6

5

Vp = 18V,I = 1kHz
VCONlROL=8V

4

l

Q

3

2

I

o
o

2

------

l/
4

NO R.M.S. (AT PIN 6)

Figure 9. Distortion of Control Amplifier at Pin 6

December 1988

7-215

•

Signetics Linear Products

Application Note

Audio Amplifier with TDA1013A

AN148

5

i
4

/

~~

I

3

Vp
D

V

:;

~

18V; vJONTROL PIN 7

=10%, RL=80
!

1

10Hz

100Hz

1kHz

~

8V

II

I

10kHz

100kHz

FREQUENCY

Figure 10. Typical Control Curve DC Control Voltage at Pin 7

VFLIII
VCONTROl. ~ 8V

1\

/

i'"
o

10Hz

100Hz

1kHz

I

10kHz

FREQUENCY

Figure 11. Distortion at Po = 2.5W vs Frequency (At Pin 2 of IC)

December 1988

7-216

100kHz

Signetics Linear Products

Application Note

Audio Amplifier with TDA1013A

i

I

/

AN148

1\"

I

~ ~~~I~/r+~~+rr11---+-~J.RE-FrER+E+NrJ~ErLE-V-EL-p~O-~r1W~-K+rr---+~-+T+ttH
~CONTROll = ,8V

1!

I'
I
I I
-10~~--~~4+~--+-4--~++~~--~~~H4+rr---+-+-++++H1

100Hz

100kHz

10kHz

1kHz
FREQUENCY

Figure 12. Frequency Characteristic

5

I
i
4

/'
I

!a

I

I

!

3

"

~

I

0.

I

/

1,1

0=10%, Rl =8n

I

Ii
! I

I

I

i

II

! [,

I

If
1

10Hz

100Hz

I II

1kHz

!

i

III

10kHz

FREQUENCY
Figure 13. Power Bandwidth

December 1988

•

I
I i Vp ~ 18V; VeONTROL
PIN 7 ~ 8V

7-217

100kHz

Signetlcs Linear Products

Application Note

Audio Amplifier with TDA1013A

50

AN148

NtLLlIll1
VCONTROL PIN 7 = 8V

II

~~

40

I

I

I'

,,)/
t'.

V
I

I

0

I

!I

!

I
100Hz

1kHz

_I
I

II I '

III

I-~

10kHz

FREQUENCY

Figure 14. Ripple Rejection vs Frequency

December 1988

I

I

IH+
I

>
0
10Hz

10kO

i

I-

I

~,=O!l

7-218

100kHz

TDA1015

Signetics

1 to 4W Audio Amplifier with
Preamplifier
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA 1015 is a monolithic integrated
1 to 4W audio amplifier with preamplifier
circuit in a 9-pin single in-line (SI P)
plastic package. The device is especially
designed for low voltage applications
and delivers up to 4W in a 4[2 load
impedance.

• Single in-line (SIP) construction
for easy mounting
• Separated preamplifier and power
amplifier
• High output power
• Thermal protection
• High input impedance
• Low current drain
• Limited noise behavior at radio
frequencies

PIN CONFIGURATION
U Package
9 PREAMP GROUND

8 PREAMP INPUT

7 PREAMP OUTPUT
6 POWER AMP INPUT
5 PREAMP

POWER AMP

Vcc

2 POWER AMP OUTPUT

APPLICATIONS
•
•
•
•
•
•

vcc

4 COMPENSATION

1 POWER AMP GROUND

Intercoms
Tape recorders and players
AM/FM radio
Alarms
Speech synthesizer output
Telephone amplifier

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

9-Pin Plastic SIP (SOT-110B)

TEMPERATURE RANGE

ORDER CODE

-25°C to + 150°C

TDA1015U

TEST CIRCUIT

•

RIPPLE VOLTAGE
METER

R1

300k

TDA1015

r

C1
100nF

v,

C3

WOnF

1

November 6, 1986

7-219

853-0915 86391

Signetics Linear Products

Product Specification

1 to 4W Audio Amplifier with Preamplifier

TDA1015

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Supply voltage

18

V

10M

Peak output current

2.5

A

PTOT

Total power dissipation

see derating curve, Figure 1

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-25 to + 150

°C

tse

AC short-circuit duration of load during
Sine-wave drive; Vee ~ 12V

100

hours

DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vee

Supply voltage range

lOAM

Repetitive peak output current

ITOT

Total quiescent current at Vee

Typ

3.6

~

12V

Max

18

14

V

2

A

25

mA

AC ELECTRICAL CHARACTERISTICS TA = 25'C; vee = 12V; RL ~ 4n; f ~ 1kHz, unless otherwise specified; see also Figure 2.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Po
Po
Po
Po

AF output power at dTOT ~ 10% ' with bootstrap:
Vee ~ 12V; RL ~ 4n
Vee ~ 9V; RL ~ 4n
Vee ~ 6V; RL = 4n
Vee = 12V; RL = 4n without booststrap

4.2
2.3
1.0
3.0

W
W
W
W

Av,
AV2
Av TOT

Voltage gain:
Preamplifier2
Power amplifier
Total amplifier

23
29
52

55

dB
dB
dB

dTOT

Total harmonic distortion at Po

0.3

1.0

%

B

Frequency response -3dB 3

15

kHz

Iz,,1
Iz,21
Izo,l

Input impedance
Preamplifier4
Power amplifier
Output impedance preamplifier

VO(AMS)

Output voltage preamplifier (RMS value) dTOT

49
~

1.5W
60Hz
100

< 1%2

Vn(RMS)

Noise output voltage (RMS value)s
Rs=On
Rs -10kn
Noise output voltage at f ~ 500kHz (RMS value)
B = 5kHz; Rs = on

RR

Ripple rejecllOn 6 f

Vn(AMS)
Vn(RMS)

= 100Hz

200
20
1

kn
kn
kn

0.8

V

0.2
0.5

mV
mV

8

/.IV

38

dB

NOTES:
1.
2.
3.
4.

Measured with an Ideal coupling capacitor to the speaker load
Measured with a load resistor of 20kn.
Measured at Po = 1W; the frequency response IS mainly determined by C1 and C3 for the low frequencies and by C4 for the high frequencies.
Independent of load impedance of preamphfler
5. Unweighted AMS noise voltage measured at a bandwidth of 60Hz 1015kHz (12dB/oclave)
6. Ripple rejection measured with a source Impedance between a and 2kn (maximum ripple amplitude. 2V)
7. The tab must be electrically floatIng or connected to the substrate (Pm 9)

November 6, 1986

7-220

Signetics Linear Products

Product Specification

1 to 4W Audio Amplifier with Preamplifier

7.5

2.5

TDA1015

HEATSINK DESIGN
= 12V, RL = 4l1,

Assume Vee
maximum.

\~J~~~~
WITHO~ .........
HjTSlr

.........

o

-25 0

= 45°C

The maximum sme·wave dissipation IS 1.8W.
150 - 45
8JA = 8JTAB + 8TABH + 8HA = - - = 580C/W
1.8

\

"- 1"-

TA

Where 8JA of the package is 45°C/W, no
external heatsmk IS required

~

Figure 1. Power Derating Curve

C2

'.F
~~-----V~----~r-------~--~-----------Q+

C10
680jAF

Vee

C5

1.8nF

Figure 2. Circuit Diagram of a 1 to 4W Amplifier

40

lJ

20

./

/- . /

o

o

'0

20

30

Figure 3. Total Quiescent Current as a Function of Supply Voltage

November 6, 1986

7-221

•

Product Specification

Signetics Linear Products

TDA1015

1 to 4W Audio Amplifier with Preamplifier

10

vJJ~'
'11

7.5

911
I
I
2.5

I
I
I

r

I
I
I

10

~

J

I

'=1~Hz

40

II'
I
I 12V
I

~

JH.

i\

-10

~

20

I'

I

lIhv

o

80

I

10- 2

10

-20
10

10"

10'

11)3

o

10

1

FREQUENCY (Hz)
NOTE:

NOTES:
_ _ With Bootstrap.
- - - - Without Bootstrap,
f - 1kHz, typical values
The available output power IS 5% higher when
measured at Pin 2 (due to senes resistance of

Po RelatIVe to OdB

=1W, Vee "" 12V,

R2(kQ)

AL = 40

NOTE:
Rs =0, TYPical Values

Figure 6. Voltage Gain as a
Function of Frequency

Figure 8. Ripple Rejection as a
Function of R2 (see Figure 2)

10

800

Cl0)

Figure 4. Total Harmonic Distortion as
a Function of Output Power AcroBB RL

t-- ~.=8.2fQ

7.5

400

//
I/

200

RL=4Q

2.5

8<:2

2.S

o
o

VV
~

o

10

~

10"

103

20

Po'" 1W, Vee'" 12V, RL = 411

o

1

10
R2(kQ)

NOTE:
Measured accorcllng to A-Curve, capaCitor C5 IS
adapted for obtaining a constant bandwidth

Figure 7. Total Harmonie Distortion as
a Function of Frequency

NOTES:
1 dTOT'" 10%, TYPical Values
2 The available output power 18 5% higher when
measured at Pm 2 (due to series resistance of

Cl0)

Figure 5. Output Power Across RL as a
Function of Supply Voltage with
Bootstrap

November 6, 1986

10'

NOTE:
15

Vee (V)

'I'-.

II
TVP

FREQUENCY (Hz)

10

r'\:
R.=O

7-222

Figure 9. Noise Output Voltage as a
Function of R2 (see Figure 2)

Product Specification

Signetics Linear Products

1 to 4W Audio Amplifier with Preamplifier

TDA1015

60

I=S;
I- B

A

r;:ypr-.

'\

40

20

\

1\
1
10-'

10-1

1

o
10

FREQUENCY (MHz)
NOTE:
Curve a total ampflfJer. curve b, power amplifier,
B "" 5kHz. As "" 0, typical values

1

10
R2(kQ)

Figure 11. Voltsge Gain a8 a Function
of R2 (aee Figure 2)

Figure 10. Noiae Output Voltage as a
Function of Frequency

•
November 6, 1986

7-223

TDA1020

Signetics

12W Audio Amplifier with
Preamplifier
Product Specification
Linear Products
DESCRIPTION
The TDA 1020 is a monolithic Integrated
12W audio amplifier In a 9-lead single inline (SIP) plastic package. The device IS
primarily developed as a car radio amplifier. At a supply voltage of Vee = 14.4V,
an output power of 7W can be delivered
Into a 4,Q load and 12W into 2,Q.
To avoid interferences and car Igmtion
signals coming from the supply lines Into
the IC, frequency limiting is used beyond
the audio spectrum in the preamplifier
and the power amplifier.
The maximum supply voltage of 18V
also makes the IC suitable for mains-fed
radio receivers, tape recorders or record
players. However, if the supply voltage IS
increased above 18V « 45V), the device will not be damaged (load dump
protected). Also, a short-circUiting of the
output to ground (AC) will not destroy
the device. Thermal protection is built in.

As a special feature, the circuit has a low
standby current possibility.

PIN CONFIGURATION
U Package

The TDA 1020 is pin-to-pin compatible
with the TDA1010.

9 PAEAMPGND
8 PREAMP INPUT

FEATURES
•
•
•
•
•

7 PREAMP OUTPUT

APPLICATIONS
•
•
•
•
•
•

6 POWER AMP lNPUT

Load dump protected
Short-circuit protected
Standby mode
High output power
Single in-line (SIP) package

PREAMPVcc
4 COMPENSATION

POWER AMP SUPPLY VOLTAGE fVccl

2 POWER A" OllT'PUT
1 POWER AMP GND

TOP YEW

Auto radio
Modems
Television
Intercom
Telephone amplifier
Alarms

ORDERING INFORMATION
DESCRIPTION
9-Pln PlastiC SIP (SOT-110B)

TEMPERATURE RANGE

ORDER CODE

-25·C to +150·C

TDA1020U

BLOCK DIAGRAM

NOTE:
The heavy Imes Indicate the Signal paths

November 6, 1986

7-224

853-0916 86392

Product Specification

Signetics Linear Products

TDA1020

12W Audio Amplifier with Preamplifier

HEATSINK DESIGN EXAMPLE
10

I'-...

~

The derating of 8°C/W of the encapsulation
reqUires the following external heatsink (for
sine wave drive):

1\
8HA=

~'" \

"'-

o

o

so

10W In 211 at Vee = 14.4V

INFINITE
\HEATSINK

\

~·ClW

100

Maximum sine wave diSSipation: 5.2W
TA = 60°C maximum
OJA

~

= 17.3°C/W

Since OJTAB + OyABH = 8°C/W,
OHA = 17.3 - 8"" 9°C/W.

150

T.(·C)

Figure 1. Power Derating Curves

ABSOLUTE MAXIMUM RATINGS
RATING

UNITS

Vce

Supply voltage; operating (Pin 3)

PARAMETER

18

V

Vee

Supply voltage; non-operating

28

V

Vee

Supply voltage; load dump

45

V

105M

Non-repetitive peak output current

6

A

PTOT

Total power dissipation

SYMBOL

See derating curves, Figure 1

TSTG

Storage temperature range

-65 to +150

°C

Te

Crystal temperature

150

°C

Ise

Short-Circuit duration of load behind
output electrolytic capacitor at 1kHz
sine-wave overdrive (10dS);
Vee = 14.4V

100

hours

November 6, 1986

150-60

= OJTAB + OyABH + OHA = - 5.2
--

7-225

Product Specification

Signetics linear Products

TDA1020

12W Audio Amplifier with Preamplifier

DC ELECTRICAL CHARACTERISTICS
SYMBOL

LIMITS

PARAMETER

Vee

Supply voltage range (Pin 3)

IORM

Repetitive peak output current

ITOT
ITOT

Total qUiescent current
at Vee = 14.4V
at Vee = 18V

Min

Typ

6

Max

UNIT

18

V

4

A

30
40

mA
mA

AC ELECTRICAL CHARACTERISTICS TA = 25'C; Vee = 14.4V; RL = 4n; f = 1kHz, unless otherwise specified;
see also Figure 2.

LIMITS

PARAMETER

SYMBOL

Min

Typ

10
6

12
7
35

Max

UNIT

Po
Po
Po

Output power at dTOT = 10%; with bootstrapl
Vee = 14.4V; RL = 2n
Vee = 14.4V; RL = 4n
Vee = 14.4V; RL = 8n

Po
Po
Po

Output power at dTOT = 1 %; with bootstrap 1
Vee = 14.4V; RL = 2n
Vee = 14.4V; RL = 4n
Vee = 14.4V; RL = 8n

VO(RMS)

Output voltage (RMS value)
RL = 1kn; dTOT = 0.5%

Po

Output power at dTOT = 10%; without bootstrap

Av 1
Ai
Av TOT

Voltage gain
Preamplifler2
Power amplifier
Total amplifier

16.7
28.5
46.2

17.7
29.5
47

18.7
30.5
48.2

dB
dB
dB

Izil
Iz,1

Input impedance
Preamplifier
Power amplifier

28
28

40
40

52
52

kn
kn

IZol
IZol

Output impedance
Preamplifier
Power amplifier

1.4

2.0
50

2.6

kn
mn

VO(RMS)

Output voltage (RMS value) at dTOT = 1%
Preamplifier2

10

1.5

B

Frequency response

25

kHz

VN(RMS)
VN(RMS)

NOise output voltage (RMS value)3
Rs=On
Rs = 8.2k.Q

0.5
1.0

mV
mV

RR
RR

Ripple rejecliOn 4
AI f = 100Hz; C2 = 11lF
At f = 1kHz to 10kHz

14

Bootstrap current at onset of clipPing (Pin 4)
RL =4.Q and 2.Q

Iss

Standby currentS

Te

Crystal temperature for - 3dB gain

W
W
W
5

IS

2V,

50Hz
0.3
0.5

48

V

44
54

dB
dB

40

mA
1

150

Input IS

short-CircUIted

5. Total current when disconnecting Pm 5 or short-Circuited to ground (Pm 9).
6. The tab must be electrically floating or connected to the substrate (Pin 9)

November 6, 1986

V

W

4.5

NOTES:
1. Measured with an Ideal couphng capacitor to the speaker load.
2. Measured With a load resistor of 40kfl
3. Measured accordmg to IEC curve A

4. Maximum ripple amplitude

W
W
W

7-226

mA
'C

Signetics Linear Products

Product Specification

12W Audio Amplifier with Preamplifier

fl

100nF

~NOBV

R1

330.

SWITCH

TDA1020

C5

100nF

P

RIPPLE VOLTAGE

METER

V

+

TDA1020

Vee
V,

j

NOTE:
With RL '" 20., preferred value of CB = 2200j.l.F

Figure 2. Test Circuit

•
November 6, 1986

7-227

TDA1510

Signetics

2 X 12W Audio Amplifier
Product Specification

Linear Products
DESCRIPTION

•
•
•
•
•
•

Large useable gain variation
Very good ripple rejection
Load dump protection
AC short-circuit safe to ground
Thermal protection
Internal limited bandwidth for
high frequencies
• Low standby current possibility,
to simplify required switches
• Low number and small sized
external components
• High reliability

The TDA 1510 is a monolithic integrated
class B output amplifier in a 13-pin single
in-line (SIP) plastic power package. The
device is primarily developed for car
radio applications, and also to drive lowimpedance loads (down to 1.6[2). At a
supply voltage Vee = 14.4V, an output
power of 24W can be delivered into a
4[2 BTL (Bridge-Tied Load), or, when
used as stereo amplifier, it delivers
2 x 12W into 2[2 or 2 X 7W into 4[2.

FEATURES
• Flexibility in use - stereo as well
as mono BTL
• High output power
• Low offset voltage at the output
(important for BTL)

PIN CONFIGURATION
U Package

12 NON-INV INPUT 2
11 ST ANDBV SWITCH

9 OUTPUT 2

B BOOTSTRAP 2
7 GND; SUBSTRATE

APPLICATIONS

6

BOOTSTRAP 1

5

OUTPUT 1

4

INTERNAL CONNECTION

3 RIPPLE REJECTION

• Car radios
• Low-impedance loads
• Stereo amplifiers

2 NON-INV INPUT 1
1 INV INPUT 1

TOP

view

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

13-Pln Plastic SIP (SOT-141B)

ORDER CODE

+70'C

TDA1510U

BLOCK DIAGRAM

+-____

r-____. -______

~------~----------------~----_+------~----~10

--,
t

11

I

12

'---+--1--013

NOTE:
Internal Block Diagram. the heavy Imes Indicate the signal paths Pm 4 IS Internally connected

April 25, 1988

7-228

853-0966 93042

Signetlcs Linear Products

Product Specification

2 X 12W Audio Amplifier

TDA1510

HEATSINK DESIGN EXAMPLE
20

The derating of 3°C/W of the encapsulation
requires the following external heatsink (for
sine wave drive):

IJ IJ
1111

16

INFINITE

24W BTL (411) or 2 X 12W stereo (211)

HEATSINK

!

12

8HA

maximum sine wave dissipation: 12W

=

4"C/W

b

TA = 65°C maximum

~

~ 8
WCIW

150-65

r-.

IIHA

= -1-2-- 3 = 4°C/W.

2 X 7W stereo (411)

o

11\
-20

0

20

40

60

maximum sine wave dissipation: 6 W

80 100 120 140 160

TA = 65°C maximum

T.CC)

150 -65

Figure 1. Power Derating Curves

IIHA

= --6--3 = 11°C/W.

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vee

Supply voltage. operating (Pin 10)

18

V

Vee

Supply voltage. non-operating

28

V

Vee

Supply voltage during 50ms
(load dump protection)

45

V

6

A

SYMBOL

DESCRIPTION

10M

Peak output current

Po

Total power dissipation

TSTG

Storage temperature range

Tc

Crystal temperature

(see derating curve Figure 1)
-65 to +150

°C

150

°C

DC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

Vcc

Supply voltage range (Pin 10)

IORM

Repetitive peak output current

ITOT

Total quiescent current

ISB

Standby current

Iso

Switch-on current (Pin 11) at V11

April 25, 1988

MIN

TYP

6

,,;; V 10

1

7·229

MAX

UNIT

18

V

4

A

75

120

rnA

2

rnA

0.35

0.8

rnA

•

Product Specification

Signetics Linear Products

TDA1510

2 X 12W Audio Amplifier

AC ELECTRICAL CHARACTERISTICS
SYMBOL

TA = 25°C; Vcc=14.4V; f=1kHz, unless otherwise specified.

PARAMETER

MIN

TYP

15.5
20

18.0
24
15
20

39.5

40

20

20,000

MAX

UNIT

Bridge-tied load application (BTL) (see Figure 2)
Po
Po
Po
Po

Output power at RL = 4.11 (with bootstrap)
Vee = 14.4V; dTOT = 0.5%
Vee = 14.4V; dTOT = 10%
Vee = 13.2V; dTOT = 0.5%
Vee = 13.2V; dTOT = 10%

Go

Open-loop voltage gain

Ge

Closed-loop voltage gain2

B

Frequency response at -3dB 3

!z,l

Input impedance 4

Vn(RMS)
Vn(RMS)
Vn

Noise Input voltage (RMS value) at I = 20Hz to 20kHz
Rs=O.n
Rs = 10k.n
Rs = 10k.n; according to IEC179 curve A

RR

Supply voltage ripple rejection 5
I = 100Hz

L,W5-91

DC output offset voltage between the outputs

IAV 5 _ 91

Loudspeaker protection (il one 01 the 2 outputs
is short-circuited to ground)
Maximum DC voltage (across the load)

B

Power bandwidth; -1 dB; dTOT = 0.5%

W
W
W
W

75

dB
40.5

Hz
M.n

1
0.2
0.35
0.25
42

dB

0.8

mV
mV
mV

50

mV

50
2

dB

1

V

30

40,000

Hz

6
6

7
12

W
W
W
W

Stereo application (see Figure 4)
Po
Po
Po
Po

Output power at dTOT = 10%; with bootstrapS
Vee = 14.4V; RL = 4.11
Vee = 14.4V; RL = 2.11
Vee = 13.2V; RL = 4.11
Vee = 13.2V; RL = 2.11

Po
Po
Po
Po

Output power at dTOT = 0.5%; with bootstrapS
Vee = 14.4V; RL = 4.11
Vee = 14.4V; RL = 2.11
Vee = 13.2V; RL = 4.11
Vee = 13.2V; RL = 2.11

Po

Output power at dTOT = 10%; without bootstrap
Vee = 14.4V; RL = 4.116. 8, 9

B

Frequency response; -3dB 3

RR

Supply voltage ripple rejection 5
I = 1kHz

V1Q, then 111 must be 1. so Av = 2 • RS

(S)

Design Criteria
The basic appllcatton CirCUit diagram is given
in Figure 2.
Important design cnteria of the printed circuit
board:
1. The Boucherot filters C4 - R4 and Cs - R6
must be mounted as close as possible to
the output Pins Sand 9 and ground (Pin
7).
2. Filter C9 - Rs must be as close as possible to Pin 13 and the Input ground. The
speCific filter is necessary to improve the
overall stability.
3. The supply decoupling capacitors
Cl0 - Cll must be mounted as close as
possible to Pins 10 and 7.
4. The supply ripple smoothing capacitor C2
and capacitor C8 must be connected to
the input ground.
S. To aVOid ground loops. the input and
output ground must be kept separate.
6. For stability, it is recommended that a
22n resistor with short leads be placed in
series with Pin 11.
7. The inputs are very sensitive to interferences and must be shielded from the rest
of the circuit.

Performance Measurements
In the application circuit of Figure 2. several
measurements are made. Unless otherwise
specified. the measurements are made at
Vee = 14.4V; RL = 4n; f = 1 kHz and
TA = 2SoC. The supply wires to the DC voltage source are a twisted-pair.

(3)

Output voltage - The output voltage. VA.
measured between Pins S-7 and 9-7 as a
function of Vee. IS given In Figure 4.
The offset voltage between Pins Sand 9 is
typically 2mV (maximum limit: SOmV).
Output power - The output power as a
function of Vee for d = O.S% and d - 10% is
given in Figure S.
Harmonic distortion - The distortion as a
function of the output power at f = 1kHz and
f = 20kHz is given in Figure 6. In Figure 7 the
distortion as a function of frequency is given
at Po= 1OW.
Input impedance - The input impedance is
mainly determined by resistor Rl (see Figure
2) In thiS application. Rl = 100kn. To minimize offset voltage. it is necessary that
Rl - R3 and R2 - R7. For resistor values
higher than 100k!2s. the offset voltage can
Increase due to differences in base currents.
Voltage gain - Previously it was derived
that the closed-loop amplification in BTL
equals:

In this application Av "" 100 X = 40dB.
The open-loop gain of the TDA1S10 is 80dB.
It is possible to reduce the voltage gain down
to 32dB (without instability) by increasing RS.
Frequency characteristic - In Figure 8 the
relative voltage gain. Av. is given as a function of the frequency (reference level
Po - 2.4W).
Power bandwidth - The relative output
power as a function of the frequency for
d = O.S% and d = 10% is given in Figure 9.
Power dissipation - The power dissipation
as a function of the output power is given in
Figure 10.
For a worst-case sine wave dissipation of
11.8W, the external heatsink must have a

NOTE:
• Since point 'B' IS a wtual I"put for amplifier 2

December 1988

(4)

Quiescent current consumption - In Figure 3 the total qUiescent current consumption
is given as a function of the supply voltage
Vee. The maximum guaranteed value at
Vee = 14.4V is 1SOmA.

7-233

I

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510
thermal resistance of 4.4°C/W (for derivation
see Appendix I).
Supply voltage ripple rejection (SVRR) The SVRR as a function of the frequency IS
given in Figure 11.
Noise The noise output voltage with
Rs = 10k.n, and measured according to the
IEC 179 A-curve, is 250/1V.
Stability - The TDA1510 is stable for each
kind of load, down to 32dB.

STEREO
The Stereo Application
The basic stereo application CIrCUIt diagram is
given in Figure 12.
Important design criteria for the layout of the
stereo print are the same as those for the
BTL print regarding Boucherot filters, supply
decouphng capacitor and the capacitor for
the supply voltage ripple rejection.

Performance Measurements
In the application circuit of Figure 12 several
measurements are made. If not otherwise
specified, the measurements are made at
Vee = 14.4V; R1 = 4.11; f = 1 kHz and
TA = 25°C.
Quiescent current and output voltage The quiescent current consumption is identical to that given for the BTL CirCUit (see
Figure 3). The same holds for the output
voltages at Pins 5 and 9 (see Figure 4).
Output power - The output power versus
the supply voltage IS given in Figure 13 for
RL = 1.6.11, 2.11, 3.2.11 and 4.11 for a constant
distortion level of 10%.

In Figure 14 the same characteristics are
given for 0.5% distortion.
Using the circuit without bootstrap capacitors
C3 and C7 , the output voltage must be cor-

December 19BB

AN1491

rected to have symmetrical clipping. To do
this a 56k.n resistor has to be connected
between Pin 3 and the input ground; Pins 5
and B must be connected to + Vce.
The output power at the output pins is now
5.7W (4.11 load) and 10.5W (2.11 load).
Distortion - In Figure 15 the distortion as a
function of the output power is given for
RL = 4.11 at 1 and 20kHz.

The same characteristics are given in Figure
16 for RL=2.n.
Input impedance - The input impedances
are mainly determined by resistors R1 and
R5.

In thiS application R1 = 100k.n (see Figure
12).

Noise - The nOise output voltages, measured according to IEC 179 A-curve are 90/1V
and 170/1V at Rs = 0 and 10k.n, respectively.
Channel separation - The channel separation at Po = 1Wand Rs = 10k.n is 60dB.
Stability - The TDA 1510 IS stable for each
kind of complex load down to 26dB of gain.

APPENDIX
Heatsink Design
The TDA1510 has a

OJC 01

3°C/W.

Assume: Vec = 14.4V, RL = 4.11 and
TAMAX = 60°C.
From Figure 10 it can be seen that the
maximum sine wave power diSSipation with a
4.11 load IS '" 11.BW in BTl.

Voltage gain - The closed-loop voltage
gain is determined by the feedback resistors
R2 and R3 and R7 and RB, in this case: 40dB.
It is possible to reduce the voltage gain down
to 26dB (w~hout instabilities) by increaSing
R2 and RB.

The total reqUired thermal resistance becomes:
150-60
OJA = - - = 7.6°C/W
11.B

Frequency characteristics - The voltage
gain Av as a function of the frequency at
Po = 1W is given in Figure 17.

When using a thermal compound, OCH is
approximately 0.2°C/W,

Power bandwidth - In Figure 1B the output
power IS given as a function of the frequency
for d = 0.5% and 10%.
Power diSSipation - The total power diSSIpation of the two channels as a function of
the output power per channel is given in
Figure 19 for RL = 2.11 and 4.11.

The worst-case power dissipation in stereo is
the same as in the BTL circuit.
The external heatslnk must also have a
thermal resistance of 4.4°C/W.
Supply voltage ripple rejection (SVRR) The SVRR of both channels IS 55dB from
100Hz to 20kHz.

7-234

OJA =

OJC

+ OCH + OHA

It follows:
OHA = 7.6 - (3 + 0.2) = 4.4°C/W
From these measurements it appears that the
maximum power dissipation with musIc drive
is about 75% of the worst-case sine wave
power dissipation. Then the maximum practical power dissipation becomes B.BOC/W with
a 4.11 load In BTl.
This gives:
150-60
OJA = - - = 10.2°C/W
B.B
and the heatsink thermal resistance:
OHA = 10.2 - (3 + 0.2)'" 7°C/W

Signetics linear Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510

AN1491

INTERNAL CIRCUIT BLOCK DIAGRAM

r----~r-----~----~------~------------~~--_i------~--~10

11

12
~--+----t--013

, . - - - - - - - - - - - - - - - - - - - - - - - - _ - - - - Vee

v
NOTE:

•

(144)2

IVccV2)2 - 2 POIDEAL =-Rl ---4-=26W measured at f=1kHz, d=10% Po

=

24W

Figure 1. Output Stage BTL

December 1988

7-235

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510

AN1491

R1

R2

C8

C1

v, o---j f-"'-~-I
C9

R8

R7

R3

RS

C6

Figure 2. TDA 1510 Bridge Application

120

I

V

V
40

V

SUPPl.V VOLTAGE (V...,l

Figure 4. Output Voltage vs Supply Voltage

20
0
4681012141618
POWER SUPPLY VOLTAGE (V)

Figure 3. Total Quiescent Current
Consumption vs Supply Voltage

December 1988

7-236

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510

30

fl'kH~RLI=4J

d=10%j

25

!I

/
o

8

024

8

W

V~CI=I,~~UIRLl4hl, 111111

~

z

~~

/

I

/

/

d=0.5%

0.8

iii

~

~

f-H*H-I+t-f-ttttt#t-fli+Htfttl

0.4

f=l:ffil=:ttttttUmttlm

0.2

O~~~±±~~~~

"
w

~

g

~

"w
~...
......
::>

-3

-4

1()2

1D"

1()3

~

~

60

"w~

Ul

50

...ii!

40

~

30

~

20

1()2

~

0.1
0
10

102

-2

1D"

10'
FREQUENCY (Hz)

Figure 7. Total Harmonic Distortion
vs Frequency

.1

J. .I J

Vee = 14.4V, RL =42

12

Y'

r- r- .......

II

Po~kHz)=24W

/

I

'I
102

1()3

Figure 9. Power Bandwidth

i'-

g
::>

10

mo

FREQUENCY (kHz)

Figure 11. Supply Voltage Ripple
Rejection vs Frequency

December 1988

o

2.5

5

7.5 10 12.5 15 17.5 20 22.5
OUTPUT POWER (VI)

Figure 10. Power Dissipation
vs Output Power

•

Vcc=14.4'~'RL =4Q,R~~I~Q

0.1

1D"

FREQUENCY (Hz)

w

.,II:

0.2

-1

10

Figure 8. Frequency Characteristic

z

.."

-3

FREQUENCY (Hz)

iii 70

0.3

d=lO%

::>
0

W

w'

10"

t~~~\W.4J, J~ ~~I~
Po~kHz)=18W IIIIII
d=O.S%

.-e

-2

0

0

:Ii

OUTPUT POWER (VI)

Figure 6. Total Harmonic Distortion
vs Output Power

-1

0.4

l:

10- 1

n u w m

~

~

Z

l:

z

C

z

0

11 0.8 I-H-J-Ijfjjfj-f-ttttf+!t-llt+Htftll

Figure 5. Output Power
vs Supply Voltage

~

~

IlWJ~z fljJ~~

POWER SUPPLY VOLTAGE (V)

.-e

111111

Q

./. ~

"

AN1491

7-237

Signetics Lineer Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510

AN1491

R1

RS

fa

S,

±~2

3
~

'>-

2

V,o--j

1

11

,/

6

5

:::!:C4
R4
:=C2

Rl

C11

12

f---o V,

13

7

r-HC7

CS

R2

8

9

-lt-

R3

±~3

10

~r--....

TDA1510

Vee

C8

~

R7
::!:C9
R8

~

) Rl

R6
~o

Figure 12. TDA1510 Stereo Application

12

20

f=1kHz, d=10%

//

16

~

14

~

12

2

10

a:

V
P' /

Rl =22

Rl =3.22..1-

I>J'

~

~
o

~P'
~ ;::::;....-:~

..-::

2

10
d=D.S%
f=1kHz

RL -42

oP

6 7 8 9 10 U n ~ 14 • 18 V 18
POWER SUPPLY VOLTAGE (V)

Figure 13. Output Power
vs Supply Voltage

Rl-1.6~

~

~ I~ V

V""

~:::;: ~?

December 1988

r1

Rl =1.62/

18

~~

Rl =3.22

L& ~ ~ I

Rl -4Q

~

4681012141818
POWER SUPPLY VOLTAGE (V)

Figure 14. Output Power
vs Supply Voltage

7-238

~erd~rl~.4V. R~;;~~

iz

~

~
~

0.8

20kHz 1kHz

0.6

0
:&

..

a: 0.4

:I:

~

0.2

10-'
100
10'
OUTPUT POWER (W)

Figure 15. Total Harmonic Distortion
vs Output Power

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W with the TDA1510

AN1491

Vee ~'~~ v, RL ~ ~~

Vee

1kHz

20kHz

.s-

:s

/

.,:s

Po=IW

-1

ffi

z

....."~
"

C -2

'"
:i
w

!:j -3

g

.....

~\~~~v, RL ~~~

0

111111111

-1

d=O.S%
Po~kHz)=5.2W

-2

Jij~!.1111

-3

0

J.I

poliliirii
-4

-4

11111111111
10-'

10"

to'

10

10'

1()2

OUTPUT POWER (W)

104

FREOUENCY (Hz)

to

1()2

loS

10'
10'
FREQUENCY (Hz)

OP10920S

Figure 16. Total Harmonic Distortion
vs Output Power

Figure 17. Frequency Characteristic

Figure 18. Power Bandwidth

ve~=1l4V'\=I~HZ

/""

r-- i'. 12Q
Rt

j
,

rr-...
I'R1L =4i

02468t012
OUTPUT POWER (W)

Figure 19. Total Power Dissipation
vs Output Power Per Channel
NOTE:
Originally published as Report No. NBA61 07, N.V. Philips Application Laboratory, December 17, 1961, Nljmegen, The Netherlands.

December 1966

7-239

•

TDA1512

Signetics

12 to 20W Audio Amplifier
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA1512 is a monolithic integrated
hi-fi audio power amplifier designed for
asymmetrical power supplies.

• Thermal protection
• Low intermodulation distortion
• Low transient intermodulation
distortion

PIN CONFIGURATION

au,

9

• Built-in output current limiter
• Low input offset voltage
• Output stage with low cross-over
distortion
• Single in-line (SIP) power
package

APPLICATIONS
• Television
• Radio receivers
• Hi-fi power amp

U Packages
NON-INVERTING INPUT

8

~~~~IT~'l~~rD

7

COMPENSATION

6

GROUND POTENTIAL

5

OUTPUT

4

POSITIVE SUPPLY (Vee>

3

~~~~RrcAfib TO PIN 6

2

RIPPLE REJECTION

1

~~~~Sl~K~NPUT

TOP VIEW

ORDERING INFORMATION
TEMPERATURE
RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-131B)

-25·C to +150·C

TDA1512U

9-Pin Plastic SIP-bent-to-DIP Plastic
Power (SOT-157B)

- 25·C to + 150·C

TDA1512QU

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vee

Supply voltage

PARAMETER

35

V

IORM

Repetitive peak output current

3.2

A

105M

Non-repetitive peak output current

5

A

PTOT

Total power disslpallOn

TSTG

Storage temperature

-55 to + 150

·C

TA

Operating ambient temperature

-25 to +150

·C

tse

AC short-circuit duration of load
dUring full-load sine-wave drive
RL = 0; Vee = 30V with R, = 4.\1

100

hours

OJMB

Thermal resistance
from Junction to mounting base

typo 3
<4

·C/W
·C/W

November 6, 1986

See derating curve Figure 1

7-240

853-0917 86393

Product Specification

Signetics Linear Products

TDA1512

12 to 20W Audio Amplifier

,--------------------------------------------

THERMAL
SHUTDOWN

5
(OUTPUT)

9O---r------------i------------,

(-INPUT)

lo---l-~

(+INPUT)

CURRENT
LIMITER

Simplified Internal Circuit Diagram

November 6, 1986

7-241

•

Signetics Linear Products

Product Specification

12 to 20W Audio Amplifier

TDA1512

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply voltage range

ITOT

Total quiescent current at Vee = 25V

Typ

15

Max

35
65

V
rnA

AC ELECTRICAL CHARACTERISTICS vee = 25V; RL = 4n; f = 1kHz; TA = 25°C;. measured In Test Circuit of Figure 2,
unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Po

Output power
sine-wave power at dTOT = 0.7%
RL=4n
RL=8n
mUSIC power at Vee = 32V
RL = 4n; dTOT = 0.7%
RL = 4n; dTOT = 10%
RL = 8n; dTOT = 0.7%
RL = 8n; dTOT = 10%

B

Power bandwidth; -1.5dB; dTOr = 0.7%

Avo
Ave

Voltage gain
open-loop
closed-loop

RIN

Input resistance (Pin 1)
Input resistance 01 Test Circuit (Figure 2)

VIN

Typ

Max

13
7

W
W

21
25
12
15

W
W
W
W

40Hz

16
74
30

dB
dB

20

kn
kn

16
210

mV
mV

100

Input sensitivity
lor Po=50mW
lor Po = lOW

kHz

Signal-to-nolse ratio
at Po = 50mW; Rs = 2kn;
I = 20Hz to 20kHz; unwelghted

SIN

68

weighted; measured according to IEC 173 (A-curve)

= 100Hz

dB
76

dB

50

dB

RR

Ripple rejection at I

dTOT

Total harmOniC distortion at Po = lOW

0.1

Ro

Output resistance (Pin 5)

0.1

November 6, 1986

7-242

0.3

%
n

Signetics linear Products

Product Specification

12 to 20W Audio Amplifier

TDA1512

20

'" ,

\

,

1\

""" \
,,,~

o

-25

150

NOTES,
- - mounted on Infinite heatsmk
- - - - mounted on heatsmk of 6°C/W

Figure 1. Power Derating Curves

r"""1r------------------...,..-+vcc

TDA1512

20.
THERMAL
PROTECTION
6.8,uF

INPUT
(R s>

o-j ..____.....__-:.I-____

~

+

680

CURRENT
LIMITER

20.

'~~~~'::~-+-t--4-----+

1
330pF

33.

Figure 2. Test Circuit

November 6, 1986

7-243

•

Signetics Linear Products

Product Specification

12 to 20W Audio Amplifier

TDA1512

~r------r------'------'

~

~

20 1-------t------r-I--7--=-c---j

101-------7~~~~------!

o~----~------~----~

10

20

40

Vee (V)

NOTES:
____ dTOr

=

0 7%.

- - - -dTOT= 10%

Figure 3. Ouput Power as a Function of the Supply Voltage; f

= 1kHz

o.751--H-ttlftttr-++1miif-lr.:·
7

jO.5
0.25

1-++++!1I!11--t-++t

10

10-1

·o(W)

Figure 4. Total Harmonic Distortion as a Function of Output Power

November 6, 1986

7-244

TDA1514

Signetics

40W High-Performance Hi-Fi
Amplifier
Product Specification

Linear Products
DESCRIPTION

ambient temperature of 50°C and a
maximum junction temperature of
150°C, the total thermal resistance 8JA is
(150 - 50)/19 = 5.3°C/W. Since the
thermal resistance of the SOT-131 A encapsulation is < 1.5°C/W, the thermal
resistance required of the heatsink is
< 3.8°C/W. Thus the maximum output
power, and therefore the music power
output, is limited only by the supply
voltage and not by the heatsink.

The TDA 1514 integrated circuit is a hi-fi
power amplifier for use as a building
block in radio, TV and audio recorder
applications. The high performance of
the IC meets the requirements of digital
sources (e.g. compact disc equipment).
The circuit is totally protected, the two
output transistors both having thermal
and SOA protection. The circuit also has
a mute function that can be arranged to
operate for a period after power-on with
a delay time fixed by external components.

PIN CONFIGURATION
U Package

MUTE TIME CONSTANT

FEATURES
•
•
•
•
•
•

The device is intended for symmetrical
power supplies, but an asymmetrical
supply may also be used.
The theoretical maximum power dissipation with a stabilized power supply is
(Vee- VN)2/21T2RL = 19W, where Vee =
+27.5V, VN = -27.5V and RL = an.
ConSidering, for example, a maximum

Thermal protection
Low THO
SOA protection
Mute time delay
Short-circuit protected
High power output

TOP VIEW

APPLICATIONS
•
•
•
•

Hi-Fi amplifier
Radio
Television
Motor driver

BLOCK DIAGRAM
+Vee

iOA'.F

100

VBST'

r
8

6

L

THERMAL

J

'50

r---",LC:c I.-=~JPROTECTION

1. '.F

,

...

5

~;~

•

-=

V

.F220

+

I

r-

*220PF

R1

:~

~

± L
":'"

,

4

•

,

THERMAL

,I

I

SOAR
PROTECTION

22.F

~~L=
8Q

r-

5.6

PROTECTION

J

I

2

R.

910.

...
R'

R2

C1

680

22.F

3.3jjF
-Vee

+

November 6, 1986

+

+

T

•

1. 0.4, F
7-245

853-0918 86394

Signetics Linear Products

Product Specification

40W High-Performance Hi-Fi Amplifier

TDA1514

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-131A)

-25'C to + 150'C

TDA1514U

40
\
30

~

\
\

"'-

"'HEATSIN~

_

6Jc =3.S"C/W
10

o

INJINITJ __
HEATSINK

-25

i"-. 1\
\
N

0

'"

150

Figure 1_ Power Derating Curve

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

+Vee to -Vee

Supply voltage (Pin 6 to Pin 4)

PARAMETER

60

V

VeSTR

Bootstrap voltage (Pin 7 to Pin 4)

70

V

4.0

A

10

Output current (repetitive peak)

TA

Operating ambient temperature range

-25 to + 150

'C

TSTG

Storage temperature range

-65 to + 150

'C

PD

Power dissipation

See Figure 1

tpR

Thermal shut-down protection time

1

hour

tse

Short-circuit protecllon time 1

10

min

VM

Mute voltage (Pin 3 to Pin 4)

7

V

NOTE:
1. Driven by a pink-noise voltage
Symmetrical power supply: AC and DC short-ClrCUlt protected
Asymmetrical power supply. AC short-circuit protected

November 6, 1986

7-246

Signetics Linear Products

Product Specification

40W High-Performance Hi-Fi Amplifier

TDA1514

DC ELECTRICAL CHARACTERISTICS +Vcc = + 27.5V; -Vcc = -27.5V; RL = 8n; f = 1kHz; TA = 25°C, unless otherwise
specIfied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

+Vee to -Vee

Supply voltage range (PIn 6 to PIn 4)

15

IOMma><

Maximum output current (peak value)

3.2

ITOT

Total quiescent current

30

60

Po
Pa
Po

Output power with THO
at VCC- VN = 55V
at VCC- VN = 44V
at Vcc- VN S 32V

37

40
25

THO

Total harmonic dIstortion at Po

-90

dIM

Intermodulation distortion at

-80

B

Power bandwidth (- 3dB) at THO = -60dB

dV/dt

Slew rate

Max

60

V
A

90

mA

12.5

W
W
W

-80

dB

= -60dB:

Ayc

Closed-loop voltage gain2

Ayo

Open-loop voltage gaIn

ZI

Input impedance3

(S+N)/N

SIN related to Po = 4mW4

Vas

Input offset voltage

= 32W
Po = 32W1

29.2

dB

20 to 25k

Hz

15

VIps

29.7

30.2

dB

85

dB

1

Mn

80

dB
mV

3

±IIO(B)

Input offset bias current

B+IB

Input bias current

Zo

Output impedance

RR

Supply voltage ripple rejection at
ripple frequency = 100Hz;
ripple voltage (RMS value) = 500mV;
source resIstance = 2kn

tM

Mute tImeS

VM(on)

Mute on voltage (Pin 3 to PIn 4)

0

VM(off)

Mute off voltage (PIn 3 to Pin 4)

6

I2TOT

Quiescent current into PIn 26

0.2

1

p.A

1

5

p.A

0.1

n

70

dB

1.25

s
5
7

20

NOTES:
1.
2.
3.
4
5.

Measured with two superImposed sIgnals of 50Hz and 7kHz with an amplitude relatIonshIp of 4.1.
The closed-loop gain IS detemnlned by extemal resIstors and IS vanable between 20 and 46dB.
The input impedance In the test CorCUlt IS determined by the bIas resIstor Rl
The noise voltage at the output IS measured In the band 20Hz to 20kHz and source reSIstance Rs = 2kn
Determined by R4 and Cl.
6. The qUIescent current Into PIn 2 determInes (WIth the value of R4) the mlnomum power supply voltage at whIch the mute functIon remains In
operation. + Vee - VN = I.TOT x R4 + VM(ON)max

November 6, 1986

7-247

V
V
p.A

TDA1515A

Sighetics

24W BTL Audio Amplifier
Product Specification

Linear Products
DESCRIPTION
The TDA1515 is a monolithic integrated
class-B output amplifier in a l3-pin single in-line (SIP) plastic power package.
The device is primarily developed for car
radio applications, and also to drive lowimpedance loads (down to 1.6n). At a
supply voltage Vee = l4.4V, an output
power of 21W can be delivered Into a
4n BTL (Bridge-Tied Load), or, when
used as stereo amplifier, it delivers
2 X 11W into 2n or 2 X 6.5W into 4n.

FEATURES
• Flexibility in use - mono BTL as
well as stereo
• High output power
• Low offset voltage at the output
(important for BTL)
• Large usable gain variation
• Very good ripple rejection

PIN CONFIGURATION

• Internal limited bandwidth for
high frequencies
• Low standby current possibility
(typ. 1!LA), to simplify required
switches; TTL drive possible
• Low number and small-sized
external components
• High reliability
• Load dump protection
• AC and DC short-circuit safe to
ground up to Vee = 18V
• Thermal protection
• Speaker protection in bridge
configuration

U Package

12

NON~INV

INPUT 2

11 STANDBY SWITCH

10 SUPPLY VOLTAGE (+Vcd
9 OUTPUT 2

8 BOOTSTRAP 2
GNO; SUBSTRATE
BOOTSTRAP 1

5 OUTPUT 1
4

LOUDSPEAKER PROTECTION

3 SUPPLY VOLTAGE RIPPLE REJEcnoN
2 NON-tHY INPUT 1

• SOAR protection
• Outputs short-circuit safe to
ground in BTL
• Reverse-polarity safe

1 tNV INPUT 1
TOP VIEW

APPLICATIONS
• Car radio applications
• Drive low impedance loads
• Stereo amplifier

BLOCK DIAGRAM
8

6

r-----~------~----~--------~--------------~------~------~---o10

11

<
12
'----;-.....- - 0 13

LOUD·
SPEAKER
PROT

9

November 14. 1986

7-248

853-0967 86554

Signetics Linear Products

Product Specification

24W BTL Audio Amplifier

TDA1515A

HEATSINK DESIGN EXAMPLE
20

The derating of 3'C/W of the encapsulation
requires the following external heatsink (for
sine·wave drive):

I II
I II

16

Infinite

21W BTL (4!1) or 2 X 11W stereo (2!1)
maximum sine wave dissipation: 12W

Heat.lnk

!

12

8 C _A

4 K/W

15

~ 8
11 K/W

I'

TA = 65'C maximum

r-.

150-65
OHA = -1-2- - 3 = 4'C/W.

1\
o

-20

0

20

40

2 X 6.5W stereo (4!1) maximum sine wave
dissipation: 6W

"

60 80 100 120 140 160
T.("C)
r

T A = 65'C maximum

OP07771S

150-65

Figure 1. Power Derating Curves

OHA

= --6--3 = 11'C/W.

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

13·Pin Plastic SIP (SOT·141B)

o to +70'C

TDA1515AD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

DESCRIPTION

RATING

UNIT

Vee

Supply voltage; operating (Pin 10)

18

V

Vee

Supply voltage; non-operating

28

V

Vee

Supply voltage; during 50ms (load dump protection)

45

V

10M

Peak output current

6

A

PTOT

Total power dissipation

see derating
curve Fig. 1

TSTG

Storage temperature range

-65 to +150

'C

Te

Crystal temperature

150

'C

AC and DC short-circuit safe voltage

18

V

Reverse polarity

10

V

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Vee

Supply voltage range (Pin 10)

lOAM

Repetitive peak output current

MIN

6

ITOT

Total quiescent current

V11
Vl1

Switching level 11: OFF
ON

~oFFI

Impedance between Pins 10 and 6; 10 and 8
(standby position V11 < 1.8V)

ISB

Standby current at V11

Iso

Switch-on current (Pin 11) at V11  5kn If V 11 > V 10
2, Closed-loop voltage gam can be chosen between 32 and 56dS (BTL), and IS determined by external components.
3. Frequency response externally fixed.
4 The input Impedance In the test Circuit (Figure 3) IS typically 100kn
5. Supply voltage ripple rejection measured with a source Impedance of
(maximum npple amplitude 2V)
6. Output power IS measured directly at the output pins of the Ie

on

7. Closed~loop voltage gain can be chosen between 26 and 50dS (stereo), and IS determined by external components.
8. A resistor of 56kn between Pins 3 and 7 to reach symmetrical clipping
9. Without bootstrap the 100,uF capacitor between Pins 5 and 6 (8 and 9) can be omitted Pins 6, 8 and 10 have to be Interconnected

November 14, 1986

7-250

Signetics linear Products

Product Specification

24W BTL Audio Amplifier

TDA1515A

lOOK

lOOK

o--j
o 22,uF

100 nF

lOOK

lOOK

+
2K

47,uF

Figure 2. Test!Application Circuit Bridge-Tied Load (BTL)

100 K

lOOK

'+

=l=
~

•

lOOK

lK

47

Figure 3. Testl Application Circuit Stereo

November 14, 1986

111

7-251

Signetics

AN1481
Car Radio Audio Power
Amplifiers up to 20W with the
TDA1515

Linear Products

Application Note

Authors F Peiser
J SIPS
The TDA 1515 IS a power amplifier for car
radio applications It contains two Identical
amplifiers which can be utilized for BTL or
stereo applications The TDA 1515 IS available In a 13-lead single in-line plastic power
package with 8JC of ,;;; 3·C/W

thermal shutdown CITCUItS become operative
SpeCial attention has been paid to the layout
of the output transistors to avoid current
crowding

bootstrap, a resistor of 5Skf2 must be connected between Pin 3 and common ground
The supply npple voltage can be smoothed
by decoupllng Pin 3 to ground

Power Supply Over Voltage
Protection

Car radios require protecllOn from hostile
automotive environmental conditions, therefore, several protection CircUits are bUilt Into
the TDA1515
• AC and DC short-circuit to ground
• Power supply over voltage

The power supply over voltage protecllOn
CITCUlt IS activated when the difference between output voltage and Vcc is about 18V
Then, a low Impedance IS SWitched between
the base and emitter of the upper Darlington
output transistor The upper Darlington transistor breakdown voltage IS thereby Increased
to VCER "" 50V

BOOSTER APPLICATION

• Thermal shutdown
• Speaker protection In bndge
configuration
Other features of the TDA 1515 Include
• Low offset voltage
• Large gain selecllOn range
• Good npple protecllOn
• Low standby current
• Standby control with TTL levels

CIRCUIT DESCRIPTION
The TDA 1515 contains two Identical amplifiers with dlfferenllal Input stages It can be
used for stereo or bndge applications

Signal Path
The collectors of the non-Inverting PNP Input
transistors are coupled to the Class A dnver
stages which dnve the Class B output stages
The Class A dnver transistors are frequencylimited by a Miller capacitor This Improves
the stability and overall nOise behavior

Protection Circuits
To Improve the reliability where the overdnve
condition eXists and when short circUiting,
both amplifiers have a Safe Operating Area
Region (SOAR) protection CITCUlt for the upper output stage The base current of the
output transistor IS limited, based on the
voltage and current applied to the output
transistor The SOAR lies between 5A/OV
and OA/20V Due to the SOAR protection
CITCUlt, It IS pOSSible to limit the Signal excursion of these stages to thelT allowable boundanes. Therefore, AC and DC short-clTcUlting
to ground Will not damage the deVice
With continuous short CITCUlt, the chip temperature can nse above 150·C At that pOint, the
December 1988

Thermal Shutdown
To safeguard the IC against high temperatures, thermal shutdown protecllOn CITCUltS
nave been bUilt Into both amplifiers. When the
die temperature exceeds 150·C, a transistor
begins to turn on and thereby decreases the
dnve current to the power transistor. A second thermal shutdown protection CITCUlt protects the output transistors against hot spot
temperatures

Loudspeaker Protection In BTL
The loudspeaker protection In BTL starts
operating when the DC offset voltage between the output PinS 5 and 9 exceeds 1 V
An Internal comparator CITCUlt controls the
devlabng DC output voltage. The maximum
DC current through the loudspeaker IS therefore limited to a safe value for the speaker
(~250mA for a 4f2 speaker)
Due to the RC time (about 1 second With
47 "F) at Pin 4, the DC current-limiting proteclIOn CITCUIt IS inoperative dunng SWitching on
and short-clTculting for one second

Special Features
A speCial feature of the TDA1515 IS a mute
function When Pin 11 IS taken below 1.8V,
mute IS on. When It IS taken above 3V, mute
IS off.
Both amplifiers have bootstrapping capabilities at Pins Sand 8 When these pinS are not
used, the Internal bootstrap resistors must be
short-clTcUited by connecting Pins Sand 8 to
Vce To aVOid poor npple rejection In the
standby mode, the bootstrap resistor IS Internally SWitched off To optimize the output
voltage for maximum output power Without

7-252

Principle of BTL
The pnnclple of the BTL CITCUlt IS shown in
Figure 1. This figure shows only the output
stages Both channels are antiphase driven
Dunng the flTst half-penod of the sine wave
excurSion, T 1 and T4 are conducting, and In
the second half-period T2 and T3 are conducting. The output swing across the load
resistor has a peak-to-peak ampllliJde of two
times Vce
The Ideal average output power at clipping
equals
Vee 2

2

Po Ideal = - RL

(1)

At Vee = 14.4V and RL = 4f2 Po Ideal = 2SW. Because of voltage losses In the
output stage of the TDA 1515 and due to
wlnng of the board, the practical measured
output power on the board IS 20.5W
Measured on the pins of the IC, the output
power becomes 21W.

Amplification
The overall voltage gain In the amplification
CITCUIt becomes.
Vo
IVoll+1vo,,1 RS+R5
Av=- =
=---> +
V,
V,
R5
RS
RS
-=2"-+1
R5
R5
(assuming R3 = RS)

(2)

RS
In practice 2" R5 »1,
RS
therefore Av = 2" R5.

(3)

Design Criteria
The baSIC application CITCUlt diagram IS given
In Figure 2

853-09S7 8S554

II

Application Note

Signetics Linear Products

Car Radio Audio Power Amplifiers
up to 20W with the TDA1515

I

AN1481

I

AMPLIFICATION CIRCUIT

STEREO
The Stereo Application
The basic stereo application Circuit diagram IS
given in Figure 12.
Design criteria for the layout of the stereo
application are the same as those given in the
Design Criteria Section. Component leads are
as short as possible for the power supply
decoupling capacitor, and the capacitor for
the supply voltage ripple rejection.

Important design criteria of the PC board:
1. The Boucherotfilter C4 - R4 must be
mounted as close as possible between the
output Pins 5 and 9.
2. Filter Cg - R7 must be as close as possible
between Pin 13 and the input ground. The
specific filter is necessary to Improve overall stability.
3. The supply decoupling capacitors
ClO - C11 must be mounted as close as
possible between Pins 10 and 7.
4. The supply ripple smoothing capacitor C2
and capacitor Ca must be connected to the
input ground.
5. Separate input and output grounds must be
maintained.
6. With the high input impedance at Pin 11, It
is recommended to decouple Pin 11 with a
100nF capacitor to ground to guarantee a
good standby switching behavior.

Performance Measurements
In the application circuit of Figure 2, several
measurements are done. If not otherwise
stated, the measurements are given at
Vee = 14.4V on the PC board connections;
RL = 4Q; f = 1kHz and TA = 25'C.
The power supply wires are a twisted-pair.
a) Quiescent current consumption
In Figure 3 the total quiescent current
consumption is given as a function of the
supply voltage Vee. The maximum guaranteed value at Vee = 14.4V is 125mA. In
standby position of S the quiescent current
is "'11lA (.;; 0.2mA).
b) Output voltage
The output voltage measured between
Pins 5 -7 and 9 - 7 as a function of Vee IS
given in Figure 4. The offset voltage between Pins 5 and 9 is typically 2mV (maximum limit: 50mV).
c) Output power
The output power as a function of Vee for
d = 0.5% and d = 10% is given in Figure 5
(Power losses across the PC board are

December 1988

"'0.5W at d = 10% and "'0.25W at
d = 0.5% level and Vee = 14.4V).
d) Harmonic distortion
The distortion as a function of the output
power at f = 1kHz and f = 20kHz is given in
Figure 6. In Figure 7, the distortion as a
function of frequency is given at Po = 1W.
e) Input impedance
The input impedance is mainly determined
by resistor R1 (see Figure 2). In our application: 100kQ. To minimize offset voltage,
it is necessary that R1 = Ra and R2 = R6.
For resistor values higher than some
100kfls the offset voltage can increase
due to differences in base currents.
f) Voltage gain
In the Applications section it is derived that
the closed-loop amplification in BTL equals:

In our application Av = 100 x (40dB). The
open-loop gain of the TDA 1515 is 75dB. It
IS possible to reduce the voltage gain down
to 32dB (without instability) by increasing
R5.
g) Frequency characteristics
In Figure 8 the relative voltage gain Av is
given as a function of the frequency (reference level Po 10dB below 20W).
h) Power bandwidth
The relative output power as a function of
the frequency for d = 0.5% and d = 10% IS
given in Figure 9.
i) Power dissipation
The power dissipation as a function of the
output power is given in Figure 10. For a
worst-case sine wave dissipation of
"'11.5W, the external heatsink must have a
thermal resistance of 4.6'C/W.
j) Supply Voltage Ripple Rejection (SVRR)
The SVRR as a function of the frequency is
given In Figure 11.

k) Noise
The noise output voltage with Rs = 10kQ
and measured according to the IEC 179 Acurve is 250IlV.

7-253

Performance Measurements
In the application circuit of Figure 12, several
measurements are done. If not otherwise
stated, the results of the measurements are
given at Vee = 14.4V; R1 = 4Q; f = 1kHz and
TA = 25'C. (Vee measured on the PC board
connections).
a) The quiescent current consumption and
output voltage are identical to those given
for the BTL circuit above.
b) Output power
The output power versus the supply voltage is given In Figure 13 for RL = 1.6, 2,
3.2, and 4Q, respectively, for a constant
distortion level of 10%. (The power losses
due to the output electrolytic are about
0.3W, while the losses across the PC
board traces are'" 0.25W at Vee = 14.4V
and RL = 2Q). In Figure 14, the same
characteristics are given for 0.5% distortion.
Using the circuit without bootstrap capacitors Ca and C7, the output voltage must be
corrected to have symmetrical clipping.
Therefore a 56kQ resistor has to be connected between Pin 3 and the input
ground; Pins 5 and 8 must be interconnected to + Vee.
The output power at the output pinS IS now
5.3W (4Q load) and 6.5W (2Q load).
c) Distortion
In Figure 15 the distortion as a function of
the output power is given for RL = 4Q at 1
and 20kHz, while in Figure 16 it is shown
for RL = 2Q. The total harmonic distortion
versus frequency for RL = 2 and 4Q is
given in Figure 17.
d) Input impedance
The Input impedances are mainly determined by resistor R1 and R5 (100kQ).
e) Voltage gain
The closed-loop voltage gain is determined
by the feedback resistors R2 - Ra and
R7 - Re. in thiS case 40dB. It is possible to
reduce the voltage gain down to 26dB
(Without Instabilities) by increasing R2 and
Ra·
f) Frequency characteristiCS
The relative voltage gain as a function of

•

Application Note

Signetics Linear Products

Car Radio Audio Power Amplifiers
up to 20W with the IDA 1515
the frequency at Po
18.

~

1W is given in Figure

g) Power bandwidth
In Figure 19 the relative output power IS
given as a function of the frequency for
d~1% and 10%.
h) Power dissipation
The total power dissipation of the two
channels as a function of the output power
per channel is given In Figure 20 for RL ~ 2
and 4Q. The worst-case power dissipation
In stereo IS the same as in the BTL circuIt.
The external heatslnk must also have a
thermal resistance of 4.6'C/W.

AN1481

i) Supply Voltage Ripple Rejection (SVRR)
The SVRR as a function of the frequency IS
given In Figure 21.

From Figure 10 it follows that the maximum
sine wave power dissipation with a 4Q load is
""11.5W in BTL.

j) NOise
The noise output voltages, measured according to IEC 179 A-curve are 90 and
170l1V at Rs ~ 0 and 10kQ, respectively.

The total required thermal resistance becomes:

k) Channel separation
The channel separation at Po
f ~ 1kHz and Rs ~ 10kQ is 60dB.

~

OJA

~

150-60
--11.5

~

7.8'C/W

1 W,

When using thermal compound OCH is about
O.2'C/W it follows:

APPENDIX I
Heatsink Design
The TDA1515 has a OJC of 3'C/W

OHA

~

7.8 - (3 + 0.2)

~

4.6'C/W

Assume: Vcc~14.4V, RL~4Q, TA~60'C.

INTERNAL CIRCUIT BLOCK DIAGRAM

r-~~----r-----~-------r-----r--------~r------r------lr--~10

12

'---1--+---013

December 1988

7-254

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W with the TDA1515

AN1481

r-----------------~~---------vp

(144)2
NOTE,
Po Ideal

(VCC/v:!)2
::--~

--2- - - = 26W (measured at f = 1kHz, d = 10%, Po = 20 5W)

RL

4

Figure 1. Output Stage BTL

Rl

R2

5

r[1C12

C1

11

12
TOA1515

./

II

f'...
6

S

RL
~

C3
C4

f-i

8

9

-

z:::::s R4

R3

C6

H-

Figure 2. TDA1515 Bridge Application

7-255

13

7

C7

R6

RS

December 1988

10

2

1

±

-:;.-

3

V,o-l

Cl0

=:= C5

fC2

C8

1lcg
R7

-=-

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W with the TDA1515

AN1481

120

12

30

_,00

10

25

f

"§.

..
..
I-

/'

80

Z

::>

60

0

IZ

/'

0

40


0

L

:/"

o -A

o

8

10

12

14

16

18

o
o

20

8

V1~1\4.4t kI ~ ~

~ 0.8

•

L

~ 0.6

16

18

o

20

6

/

V
[A=o.5%

~/

V

10

12

14

16

18

SUPPLY VOLTAGE (V)

Figure 5. Output Power
vs Supply Voltage

Vee - 14.4V, RL = 40,
Po
2W AT 1kHz

l

111111

ll~~z

~

14

Figure 4. Output Voltage
vs Supply Voltage

Figure 3. Quiescent Current
vs Power Supply Voltage

P

12

~

SUPPLY VOLTAGE (V)

POWER SUPPLY VOLTAGE (V)

~

10

~ 1kHZ,' Re = 4~

=

~ 0.4

H+I#IIIf-t+HttHf-+l-ttt-ttt+ttf-HII

~

~is 0.3 H+I#IIIf-t+HttHf-+l-ttt-ttt+l1ftffill

1kHz

o

o

Z

Z

~ 0.2

~ 0.4

H+lfll1+If-++++lll*-+lc-Hi1llhf+-ttl-tttII

a:

~

"';i 0.1 f-H-Ifll1+If-++tttll*-tirn1Itt11--++tI-tttII
:J:

~ 0.2

g

g

J
o

10-1

100

101

III~~~mII~I
r-

01..102

103

,()2

10

OUTPUT POWER (W)

Figure 6. Total Harmonic Distortion
vs Output Power

1
8

1---11
~ffitlttt--t-ttttttlt-H-IHitttt-++-mtfl

.. -3

l-"t-Ilt+tHttt--t+Hctt!tI-t-Httffit-t+I-fflHl

-4

f-HitttHt-HitttHHHitttHf-Hi+ltlHl

6

102

103
1()4
FREQUENCY (Hz)

10'

i--

I

0

I'--r--..

December 1988

70

~

~

.
..

i:!
"g

60

-I"-

-I

I

15

20

Figure 10. Power Dissipation
vs Output Power

50

2:

::>
-

::>

c-

AL

= 4n_

0

&~!-,:::
o , y, =--o

6

I

~

i '....... kl,V,\

1.6n~

a:

w

..
..
;:

1"-,:1~~

0

V

>-

::>

~~ '<~
~ "-::V

>-

::>
0

--10

12

14

16

18

20

SUPPLY VOLTAGE (Vee>

SUPPLY VOLTAGE (V)

Figure 13. Output Power vs Supply Voltage

December 1988

Figure 14. Output Power vs Supply Voltage

7-257

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W with the TDA1515

Vee ~ '\':i..v. RL'~'~n

2011Hz

lz

1_

V~~ ~1~!.4J. M'~lIkn
1

r&
.b

0.5

~

0.'

RL =20

a

1i 0.3
g

I"

:I:

;i

~o~'\'~

lz

~

I
/

~ 0.2
:I:

r-

Ril

.g

0.1

0.2

10- 1

10'

OUTPUT POWER (W)

10"

10

10

10'

Figure 16. Total Harmonic Distortion
vs Output Power

Vee - 14.4V, RL = 4n,

"'!',
V'i",71"!'!".
~,~i'V' RL = on

1-2
~
5!

Vee ::: 144V, f

JI

i:s. -1 dl~~:tT1

d

= 10%

104

Figure 17. Total HarmQnic Distortion
vs Frequency

HI\~

II

= 1W AT 1kHz

o~~~~~*-~~~+*~

10>
FREQUENCY (Hz)

OUTPUT POWER (W)

Figure 15. Total Harmonic Distortion
vs Output Power

Po

I

a

~ 0.4

10"

II

JkW lJ.

~~ 0.8

,
10- 1

AN1481

=.,!.,Hzr--

~!.n

"-

/
I

/'

.....-

"'L=4H

-3

-.
o

10'

10

10'

10

104

102

103

104

FREQUENCY (Hz)

FREQUENCY (Hz)

lOS

o

10

12

POWER OUTPUT (W)

""'"OS
Figure 18. Frequency Characteristic

Figure 19. Power Bandwidth

ve.}. Ull! It =U. ~~I~lln

"
II

"-

II
1000

10,000

100,000

FREQUENCY (Hz)

Figure 21. Supply Voltage Ripple
Rejection vs Frequency

December 1988

7-258

Figure 20. Total Power Dissipation
vs Output Power per Channel

TDA1520B

Signetics

20W Hi-Fi Audio Amplifier
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA 15208 is a 20W hi-fi audio
power amplifier designed for asymmetricalor symmetrical power supplies.

• Low input offset voltage
• Output stage with low cross-over
distortion
• Single in-line (SIP) power
package
• AC short-circuit protected
• Very low internal thermal
resistance
• Thermal protection
• Very low intermodulation
distortion
• Very low transient
intermodulation distortion
• Complete SOA protection

U Package
1

NON-INVERTING INPUT

2

INPUT GROUND
(SUBSTRATE)

3

COMPENSATION

4

NEGATIVE SUPPLY (GROUND)

5

OUTPUT

6

POSITIVE SUPPLY (Ved

7

NOT CONNECTED

8

RIPPlE REJECTION

9

INVERTING INPUT
(FEEDBACK)

TOP VIEW

APPLICATIONS
• Hi-fi audio power amplifier
• Motor driver
• Power op amp

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

9-Pin Plastic SIP (SOT-131A)

-25°C to +150°C

ORDER CODE

TDA1520BU

9-Pin Plastic SIP (SOT-157A)

-25°C to + 150°C

TDA1520BQU

•

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vee

SYMBOL

Supply voltage

PARAMETER

50

V

IORM

Repetitive peak output current

4

A

IOSM

Non-repetitive peak output current

5

A

PTOT

Total power dissipation

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range

-25 to + 150

°C

August 1, 1988

see derating curve Figure 1

7-259

853-0919 94023

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520B

SIMPLIFIED INTERNAL CIRCUIT DIAGRAM

S1

o
o
o
RA
T4

r--I

8

---~---

..J.,.

"T"
I

RB

I

-~--~I-M-----+----=-4r-~--~--~~-----i

~

I

I
I

1

1

:

~

I

lI

6

T
I

.:~2'-~

August 1. 1988

+

I

I

l

~
:

I

__________

...,...

I

I

-4__~______~~~-4i________~______________________~__.~ __

7-260

I

J

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520B

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply voltage range

ITOT

Total quiescent current at Vcc

laRM

Minimum guaranteed output current (peak value)

Typ

Max

50

V

60

105

mA
mA

3.2

A

15

= 33V

22

AC ELECTRICAL CHARACTERISTICS Vee = 33V; RL = 4n; f = 1kHz, TA = 25°C; measured In Test Circuit of Figure 2,
unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

Output power
sine-wave power at dToT
Po

RL = 4n

UNIT
Typ

20

22

Max

= 0.5%

}

(Figure 4)

B

Power bandwidth at dTOT = 0.5% from Po

Avo
Avc

Voltage gain
open-loop
closed-loop

RIN

Internal resistance of Pin 1 (at R1

RIN

Input resistance of Test Circuit at Pin 1 (Figure 2)

VIN

Input senSitIVity for Po

SIN

Min

= 50mW

to 10W

W

20Hz

kHz
74
30

-8

= 00)

dB
dB

1

Mn
20

kn

= 16W

260

mV

Signal-to-nolse ratio
at Po = 50mW; RSOURCE = 2kn
f = 20Hz to 20kHz, unwelghted;
weighted, measured according to IEC 179 (A-curve)

76
80

dB
dB

= 100Hz;

Rs = on

RR

Ripple rejection at f

60

dB

dTOT

Total harmonic distortion at Po = 16W

0.Q1

%

Ro

Output resistance (Pin 5)

0.01

Vo

Input offset voltage

dTIM

Transient intermodulatlon distortion at Po

diM

IntermodulallOn distortion at Po = 10W

SR

Slew rate

August 1, 1988

45

1

= 10W

0.01

7-261

n
100

mV
%

0.02

%

6

VIIlS

•

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

POWER DISSIPATION AND
HEATSINK INFORMATION
The maximum theoretical power dissipation
with a stabilized power supply is (Vcc = 33V
and RL = 4n):

TDA1520B

Worst case power dissipation with a nonstabilized power supply is (regulation factor of
lS%; over voltage of 10% and RL
min. = 0.8 X RL typ.; Vee is the loaded supply
voltage):
(1.1 X Vec)2

Vce2

--:;;- =

2..- RL

13.8W.

211'2 RL min.

With a maximum ambient temperature of
SO·C and a maximum crystal temperature of
lS0·C, the required thermal resistance is:
lS0 - SO

(JJA = - - - =

23.4

23.4W.

4.3·C/W.

The thermal resistance of the encapsulation
is < 2.S·C/W; therefore, the thermal resistance of the heatsink must be < 1.8·C/W.

50

..--------------------------.......I--r+v.

Ptot

i+

~2200"F

IWI
40

'30

\

1'-,.

'20

i

["

\
c,

f\

,.'

-, \

I
10

I~T~n.+----~4-~~------~

" .\

R,

'-\

o

-25

50

1..
C4

680

NOTES:
_ _ Mounted on infinite heatslok
- - - Mounted on heatsmk of 1.8°C/W

Figure 2. Test and Application Circuit

Figure 1. Power Derating Curves

~r-r--------._--------_r--------~--------__,

~~+-----------+---------~~L-------_+~--------_1

FREQ.= 1kHz
DTOT=O.5%

,or-+-----------t-~~----~~--------_+----------_1

'0

~

30

40

Vs(V)

Figure 3. Output Power vs Supply Voltage VcC 1 MO

The TDA 1520A can be powered with symmetrical and asymmetrical power supplies.
This application note shows applications with
asymmetrical power supplies.

The input amplifier is a Darllngton-coupled
PNP differential stage (T1 - T4) having an
800jlA current source S1. DC biasing for T1
can be derived from the internal voltage
bleeder RA - RB.
In our application with asymmetrical power
supply. the DC biasing is made with an
external resistor between Pin 1 and Pin 8.
The external resistance between Pin 1 and
Pin 8 must be limited to 100 kO for offset
voltage reasons. The current drive to the
class-A driver stage (T7 - T8) is obtained
from the current mirror circuit of T5 - T6.
The DC current source S2 (5mA). for the
class-A stage T7 - T8 flows through the three
series diodes D. to adjust and stabilize the
quiescent current of the output stage.
Each branch of the quasl-complementary output stage consists of two Darlington-coupled
NPN transistors (T9 - T1 0 and T13 - T14).

INTERNAL CIRCUIT
DESCRIPTION
The internal circuit block diagram of the
TDA 1520A is shown in Figure 1.

••

r-----------------~----------------~----------------~--~--

81
D
D
D
RA

r--I

T4
8
1
---~---

I

.....
"T'"
I

I
I
1
1
1

-;--~S-~-----+------_1~_1~~~~~~-----,

I

RS

I

.h
"'/"
I
I

I
I

1

I

1
1

I

12

I
I
I

$
I

1

~
I

I

1

I

!

~------+_--+_--~;-4-[

I

~

~

:

I

1

"'/"

I

~ __ J

I

80012818

Figure 1. Internal Circuit Block Diagram
December 1988

7-264

853-0919 94023

Signetics linear Products

Application Note

20W Hi-Fi Power Amplifier with the IDA1520A

AN149

f--------i---~-------------~---------------------------a--~~~:r++vs

:

2.2K

'*"

~

. . .____

...::.61-1.:...-'N;;:C~_ _ _ _ _ _ _..,

r-i"""~--=+--"-'VI~-1

,

,

,150.F

,

~

cal
I

I-=1

SOAR

0.1#

I_

~ 22OII.F

"*

THERMAL
PROTECTION

R2
20K

I

,,I
INPUT

Cl

I

1.F

:

...,fh-+--+-.....-,...---!t-----I
C3

220pF
SOAR

Rl
680

R3
20K

THERMAL
PROTECTION

TOAl520A

+

C4

1
R4

680pF
270

Figure 2_ Circuit Diagram
The unity gain PNP class-B driver (T11 - T12)
offers the 180· phase-shift for the lower
output stage.
The open-loop frequency cut-off is determined by the Integrated capacitor C1. Openloop gain IS typical 74dB.
The amplifier has a number of ,nternal c,rcurt
blocks to protect the deVice against shortcircuiting of the loudspeaker, misloading conditions (SOAR and thermal protection)
The thermal shut-down Circuit starts operatIng for chip temperatures higher than 150·C.

AMPLIFIER APPLICATION
CIRCUIT
The CirCUit d,agram of the TDA 1520A amplif,er operating from an asymmetrical power
supply IS shown In Figure 2.

nents, a resistor of 2.2k11 and two diodes, are
dashed in Figure 2.
It is recommended to have the power supply
electrolytic as close as possible to the amplifier PC board.
With the asymmetrical power supply of 33V,
the worst-case power diSSipation IS 15.5W
(see also Figure 18).
Calculation of the heatsink:
TJMAX - TAMAX
8JA = ...::::.:.::.........:c::.:::.::.:
PTQT
(150-45)·C =6.7 .C/W
15.5W
The thermal resistance of the heatslnk becomes:
8HA = 8JA - 8JC - 8CH
= (6.7 -2-0.2)·C/W = 4.5·C/W.

The closed-loop gain of 30dB IS fixed by the
resistors R1 and R3 while the Input resistor
R2 has the same value as R3 to keep the
offset voltage as small as possible

In the proposed appliance a 3.5cm extruded
heatslnk is used (type KL-134 of Seifert).

Also to keep the offset voltage low, It IS
advised to limit the value of R2 to about
100k11.

Several measurements are done on the application circuit of Figure 2.

To Improve the turn-off behaVior, some external components are added These compoDecember 1988

MEASUREMENTS
Quiescent Current Consumption.
The qUiescent current consumption versus
supply voltage IS given in Figure 3.

7-265

Midtap Voltage
The midtap voltage versus supply voltage is
given in Figure 4.

Harmonic Distortion
The harmonic distortion versus frequency at
Po = 10W IS given in Figure 5 for Vs = 33V
and RL ~ 411 and ,n Figure 6 for Vs = 42V
and RL = 811.
The harmOniC distortion versus output power
at f = 1kHz is given In Figure 7 for VS = 33V
and RL = 411 and in Figure 8 for Vs = 42V
and RL = 811.

Power Bandwidth
The power bandWidth for dTOT = 0.5% is
given In Figure 9 for Vs = 33V and RL = 411
and ,n Figure 10 for Vs = 42V and RL = 811.

Intermodulation Distortion
1M dlstort,on versus output power is given In
Figure 11 for Vs = 33V and RL = 411 and in
Figure 12 for Vs = 42V and RL = 811.

Frequency Response
In F'gure 13 the frequency response is given
for Vs = 33V and RL = 411 and In Figure 14
for Vs = 42V and RL = 811.
The reference level (OdB) ,s at 10dB below
Po MAX (= 2.2W) at f = 1kHz.

•

Signetics Unear Products

Application Note

20W Hi-Fi Power Amplifier with the TDA1520A

Output Power
The output power versus supply voltage is
given in Rgure 15 lor RL = 4il and Bil,
measured at dTOT - 0.5% and I = 1kHz.

Power Dissipation
The power dissipation 01 the TDA 1520A as a
lunction 01 the output power, measured at
Vs = 33V, 1= 1kHz and RL = 4il is given In
Figure 16 and with Vs = 42V, 1= 1kHz and
RL = ail in Figure 17.
The worst-case power dissipation versus supply voltage is shown in Figure 1B.

Input And Output Impedance
The input impedance 01 the TDA 1520A at Pin
1 is > 1 mil. The input impedance 01 the
application circuit of Figure 2 is 20kil, determined by the external resistor R2.

AN149

The output Impedance at Pin 5 is 10 mil at
I = 1kHz.

Slew Rate

Gain

Supply Voltage Ripple Rejection

The slew rate of the amplilier is 6VI tJS.

The input sensitivity lor Po = 10W IS 210mV.
The closed-loop gain measured at I = 1kHz IS
30dB. The closed-loop gain can be vaned by
resistors R1 and R3.

The supply voltage ripple rejection at
I = 100Hz, is 5BdB (Rs = 0).

Short-Circuit Behavior
AC short-circuiting is possible during 60 sec,
measured with sine wave drive I ~ 40Hz into
clipping at a supply voltage 01 30V and wHh a
supply series resistance 01 4il.

Noise
The weighted signal-to-noise ratio at
Po = 50mW and Rs = 2 kil IS BOdB measured according to IEC 179 (A-curve).

Measuring under the same conditions but
with pink noise drive, according to IEC 26B1C, AC short-circuiting IS allowed up to 15
minutes.

The unweighted noise (I = 20Hz - 20kHz) IS
76dB.
Measured according to CCIR 46B peak value
(also new DIN 45405 standard) this signal-tonOise ratio IS 66dB.

Turn-on and -off Behavior
With the extra network the turn-off behavior

01 the TDA 1520A can be improved.

'50r-r-------~---------r--------,_------_,

30

,~,~~-------+---------r--------i_------~

20

V

~
~

i

~·~,~o--------+--------~~------~~------~~

.

L

/

°0

10

L

20

30

vs(V)

Figure 3. Quiescent Current vs Supply Yoltage

50

40

Vs(Vl

""""',.

Figure 4. Midtap Yoltage vsSupply Voltage

~

•

0
Vs"42V

Vs=33V
RL=4n
Po=10W

...

·
·
·

I
I

4

...

.

10'

I

I

I
!

I

I

II
,oa

I

RL .. 8U

Po=10W

I
I

Ii

2

i

,ao

.

,V

.

0

,

,

i

'"

II

I
,ao

..

,

FREQ (HJ:)

FREQ (Hz)

Figure 5. Distortion vs Frequency

December 1988

Figure 6. Distortion vs Frequency

7-266

.

,

Signetics Unear Products

Application Note

20W Hi-Fi Power Amplifier with the TDA1520A

·

I

•

..
l

t •

I;

·,

V.-33Y
AL-4n
FREQ =11cHz

I
!

,

I

I

I

!

I

!

·"

,

,

-.(WI

Figure 7. Distortion

VB

,

. !I
.

i -,

I

. ,.

·
·

vJv ll1

I
II.
I

DToT=OA

I

•

Ii'

I

11

[

ii

I:

/'

i -,

I

I

Ii
i

I
10'

II

...

10'

10'

Figure 9. Power Bandwidth

•

,

l ..

I

:

I

,

Figure 10. Power Bandwidth

f1-SOHz
fI=71cHz

,

"

I

:i

i

I,

I

I

II

I!

I!
II

I

./

,

'"

Vs=33V
1It..=4t1
Vn YI2=41

!

I
I

4

10'

I

I I
I

10'

FREQ (HI)

FReG (Hz)

·

Po.OdB-.W
DmT=G.I'I!o

:

I
I

10'

01

v•.LIII

, .. en

I

I

·
·

Po(w1

Figure 8. Distortion vs Output Power

,-4t1
Po • • ell-aVo'

I
I;

'"

Output Power

..

l

AN149

I
I

Po (WI

"(WI
OPOOe'"

Figure 12. 1M Distortion

Figure 11. 1M Distortion vs Output Power

December 1988

7-267

VB

Output Power

10'

Application Note

Signetlcs Linear Products

20W Hi-Fi Power Amplifier with the TDA1520A

.
,

v••

l lill

AN149

v••

,

R&.=4n

,

"...

V

! -,
I

I I

'"

! -,

I.

,

i

"

I
i

/

.11

I I,

II
I I I I
,

.

.

,

'"

11111

,=IU
PoATO.-UW

PoATOIII=UW

... ,

.

,

,

"

...

,IP

".

FAEQ(HzJ

FREOIHzJ
0P0101OS

Figure 13. Frequency Response at Po

=2.2W

Figure 14. Frequency Response at Po = 2.2W

~~--------r-------'-------~-------.
VI"'.V

,-4n

FRIQ.-111H1

m'~~------~--------~~-----b~------1

/v-

'If

"H:-------+----;I"---~f__------+------___l

,

,

..

10

~

I

..

,

"

Po(W1

VICVI
OP0103DS

OP01020S

Figure 15. Output Power

V8

Supply Voltage

Figure 16. Power Dissipation vs Output Power

..

~r;---------r--------r--------r--------'

V.=42V

Rc.=an

FRIQ."111Hz

'If

~

"

~

r"Hr------~-+----_7"'--t_--"7""'-_+------__j

I
I

"

15

"

. . !W)

Figure 17. Power Dissipation vs Output Power

December 1988

30

V.M

..

Figure 18. Worst-Case Power Dissipation
VI Supply Voltage

7·268

50

""',....

TDA1521

Signetics

2 X 12 Hi-Fi Audio Power
Amplifier
Product Specification
Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA 1521 is a dual hi-fi audio power
amplifier in a 9-lead single in-line (SIL-9)
plastic power package. The device is
especially designed for mains-fed applications (e.g., stereo TV sound and stereo radio).

• Requires very few external
components
• Input muted during power-on and
-off (no switch-on or switch-off
sounds)
• Low offset voltage between
output and ground
• Excellent gain balance between
channels
• Hi-fi according to lEe 268 and
DIN 45500
• Short-circuit-proof
• Thermally protected

APPLICATIONS

TOP VIEW
PIN NO.
1
2
3

• Stereo
• TV sound
• Radio

OUT1

-Vee

7

DESCRIPTION

9-PIn Plastic SIP (SOT-131B)

TEMPERATURE RANGE

o to

GND

4

5
6
8
9

ORDERING INFORMATION

SYMBOL

-INV1
INV1

OUT2
+Voc
INV2
-INV2

DESCRIPTION
Non-Inverbng Input 1
Inverting Input 1
Ground
Output 1
Negative supply
Output 2
PositIVe supply
Inverting Input 2
Non-inverting mput 2

ORDER CODE

+70·C

TDA1521U

•
November 14, 1986

7-269

853-0968 86554

Signetics Linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

BLOCK DIAGRAM
+Vcc

680
INVI
-INVI
201<

OllTl
+Vcc

10k

GNO
VREF 1

10k
-VREF 2

-Vee
20k

OllT2
-INV2

680
INV2

-Vee

November 14, 1986

7-270

Product Specification

Signetics Linear Products

2 X 12 Hi-Fi Audio Power Amplifier

FUNCTIONAL DESCRIPTION
This hi-fi stereo power amplifier is designed
for mains-fed applications. The circuit IS optimal for symmetrical power supplies but it IS
also well suited to asymmetrical power supply
systems. An output power of 2 X 12W
(THD = 0.5%) can be delivered into an 8n
load with a symmetrical power supply of
±16V.

TDA1521

The gain is fixed internally at 30dB, but can
be changed externally if required. Internal
gain fixing gives low gain spread and very
good balance between the amplifiers (0.2dB).
A special feature is an Input mute circuit
which provides suppression of unwanted signals at the inputs during switching on and off.
This circuit disconnects the non-inverting Inputs when the supply voltage IS below ± 6V,

while allowing the amplifiers to remain In their
DC operating condition.
Two thermal protection circUits are provided,
one mOnitors the average junction temperature and the other the instantaneous temperature of the power transistors. Both protection CIrCU~S activate at 150·C, allowing safe
operation to a maximum junction temperature
of 150·C Without added distortion.

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

+20

V

4

A

Vce= Vs, 7-3

Supply voltage (PinS 5 and 7)

105M

Non-repetitive peak output current (Pins 4 and 6)

PTOT

Total power dissipation

see Figure 1

TSTG

Storage temperature range

-65 to +150

·C

TI

Junction temperature

+150

·C

1

hour

tsc

Short-circuit time:
outputs short-circuited to ground
Symmetrical power supply
Asymmetncal power supply;
Vee < 'V
(unloaded);
RI ;;.'n

8J e

Thermal resistance from junction to case

tse

1

hour

25

·C/W

HEATSINK DESIGN EXAMPLE
20

1n11"Re l

15

~

...~'0

\
8HA, =
3.3°CiW

1\ 1Io._k

,,

i\ \

150-65

~\

BtiA - - - - -

~\

a
-25

-

With derating of 2.5·C/W, the value of heatsink thermal resistance IS calculated as follows: given RL = 8n and Vee = ± 16V, the
measured maximum dissipation is 14.6 W;
then, for a maximum ambient temperature of
65·C, the required thermal resistance of the
heatsink is

14.6

2.5 = 3.3·C/W

"
150

Figure 1. Power Derating Curve

November 14, 1986

7-271

•

Signetics Unear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

Vcc

Supply voltage range

IORM

Repebtlve peak output current

CONDITIONS

MIN

TYP

MAX

UNIT

±16

±20

V

2.2

A

Operating mode: symmetrical power supply; test circUit as per Figure 2; Vcc = ± 16V; RL = an; TA = 2Soc; f -1kHz
Vce

Supply voltage range

ITOT

Total qUiescent current

without RL

Po
Po

Output power

THD=O.S%
THD= 10%

THD

Total harmonic distortion

Po=6W

B

Power bandwidth 1

THD=O.S%

±7.S

Gy

Voltage gain

t.Gy

Gain balance

VNO(RMS)

NOise output voltage (RMS yalue); unweighted
(20Hz to 20kHz)

±16

±20

SO
10

12
1S

.

V

·

mA

0.2

%

W
W

20Hz to 20kHz
29

31

30
0.2

Rs=2kn

dB
dB

70

140

IJV

26

kn

Iz,1

Input Impedance

14

20

RR

Ripple rejection 2

40

60

dB

00

Channel separation

46

70

dB

lis

Input bias current

VOFF

DC output offset yoltage

Rs=On

0.3
WRT GND

JJA

20

200

mV

Input mute mode: symmetrical power supply; test circuit as per Figure 2; Vee = ± 4V; RL = an; TA = 2Soc; f = 1kHz
Vee

Supply voltage

ITOT

Total qUiescent current

without RL

VOUT

Output voltage

V, =600mV

VNO(RMS)

NOise output voltage (RMS value); unweighted
(20Hz to 20kHz)

Rs=2kn

RR

Ripple rejectlon 2

VOFF

DC output offset voltage

±2

±s.a

La

·

mV

70

140

I1V

20

200

mV

·

rnA

3S
WRT GND

dB

Operating mode: asymmetrical power supply; test circuit as per Figure 3; Vee = ± 4V; RL = an; TA = 2Soc; f = 1kHz
ITOT

Total qUiescent current

SO
THD= O.S%
THD = 10%

Po
Po

Output power

THD

Total harmonic distortion

Po=4W

B

Power bandwidth

THD=O.S%l

Gy

Voltage gain

t.Gy

Gain balance

VNO(RMS)

Noise output voltage (RMS value); unweighted
(20Hz to 20kHz)

1z,1

Input Impedance

RR

Ripple rejectlon 2

00

Channel separation

S

6
a.s

.

40Hz
29

30

Rs=On

November 14. 1986

%

20

kHz

31

dB

= 200mV

140

IJ.V

14

20

26

kn

40

SO

40

CRMS value) applied to posillve or negatIVe supply rail.

7-272

dB

70

NOTES:
1 Power bandwidth at Po MAX -3dS
2 Ripple rejection at Rs = of!. f = 100Hz to 20kHz; ripple voltage

W
W

0.2

0.2
Rs=2kn

V
rnA

30

dB
dB

Signetics linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

+Vcc

.g

I
I
I
I
I
I
I

T
..L

20k

680

RL. = 8

..L

T

I
RL = 8

I
I
I
QI
£-=- I
T
I

L - - - - - - - - - - - -.....-..L-o-vcc
Figure 2. Test and Application Circuit; Symmetrical Power Supply

Vccr-----------------.-~~~--oVs

l.c:£

To
680

I

20k

I

..L ..L

220nF

V,

o-----j I---I-+-_~--I
20k
INTERNAL 1f2Vcc

20k

TOA1521

200nF

V,

o-----j r--t-='t----*---I

680

Figure 3. Test and Application Circuit; Asymmetrical Power Supply

November 14, 1986

7-273

•

TDA2611A

Signetics

5W Audio Amplifier
Product Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA2611A is a 5W audio amplifier
in a g-pin single in-line (SIP) plastic
package.

• Possibility for increasing the
input impedance
• Single in-line (SIP) construction
for easy mounting
• Extremely low number of
external components
• Thermal protection
• Well-defined open-loop gain
circuitry with simple quiescent
current setting and fixed
integrated closed-loop gain

U Package

APPLICATIONS
•
•
•
•

lOP VIEW

TV
Radio
Record player
Communication receiver

• Alarms

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-110B)

-25°C to + 150°C

TDA2611AU

TEST CIRCUIT
r---------~-----Q+

+

C4
470,..F
(16V)

Vee

NOTES,
Pin 3 not connected
Input Impedance can be Increased by applYing C and R between Pans 5 and 9 (see also Figures 4 and 5)

November 6, 1986

7-274

853-0921 86397

Product Specification

Signetics Linear Products

TDA2611A

5W Audio Amplifier

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vce

Supply voltage

PARAMETER

35

V

IOSM

Non-repetitive peak output current

3

A

10RM

Repetitive peak output current

1.5

A

SYMBOL

F'TOT

Total power dissipation

see derating
curves
Figure 1

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-25 to + 150

°C

HEATSINK EXAMPLE

8r----,----,----,----,

Assume Vee = 18V; RL = 8n; TA = 60°C
maximum; TJ = 150°C (max. for a 4W application Into an 8n load, the maximum dissipation IS about 2.2W). The thermal resistance
from Junction to ambient can be expressed
as:

8HA =
oL-__-L____
-50

~

__

~

__

100

~

150

150-60
---

2.2

= 41°C/W.

SInce8JTAB = 11°C/W and
iJ.rABH = l°C/W,
8HA = 41 - (11 + 1) = 29°C/W.

Figure 1. Power Derating Curves

DC ELECTRICAL CHARACTERISTICS
LIMITS
UNIT

PARAMETER

SYMBOL

Min
Vee

Supply voltage range

10RM

Repetitive peak output current

ITOT

Total quiescent current at Vce = 18V

November 6, 1986

Typ

35

6

25

7-275

Max
V

1.5

A

25

mA

•

Product Specification

Signetics Linear Products

TDA2611A

5W Audio Amplifier

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 1av;

RL

= an; I = 1kHz,

unless otherwise specified,

see also Figure 2.
LIMITS
PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
Min

Po

AF output power at dTOT = 10%
Vee = 1aV; RL = an
Vee = 12V; RL = an
Vee = a.3V; RL = an
Vee = 20V, RL = an
Vee = 25V; RL = 15n

dTOT

Total harmonic distortion at Po = 2W

Typ

Max

4

W
W
W
W
W
W

4.5
17
0.65
6
5
1

Frequency response

03

%

15

Izil

Input impedance

VN

Noise output voltage at Rs
B = 60Hz to 15kH z

VI

SensitiVity lor Po

kHz
kn 1

45

= 5kn;

= 2.5W

44

0.2

0.5

mV
mV

55

66

mV
mV

NOTE:
1. Input Impedance can be Increased by applYIng C and R between PIns 5 and 9 (see also FIgures 4 and 5).
10
TYPICAL VAWES

15 ----NOT

I
I
I

=:~ ::5~;V~=='::v
7.5

GUARANTEED
IN VIEW OF
IORM s1.5A

I
I
I
I
I

'\

2.5

o

10-1

A

~

~"

B

10

o~-=~--~--------~

o

m

~

VccM

Figure 2. Total Harmonic Distortion
as a Function of Output Power

Figure 3. Output Power as a Function
of Supply Voltage

o
10

1(12

10'

10'

FREQUENCY (Hz)
NOTES!
Curve a for C"" 1pF, R = on,
Curve b for C = l#Ft R '" 1kfl.
C2 = 10pF, typical values

Figure 4. Input Impedance as a
Function of Frequency

November 6, 1986

7-276

Signetics Linear Products

Product Specification

TDA2611A

5W Audio Amplifier

~ ~c~I~~V;R~ ~1~~ii~1k~z
••••• Vcc =18V;RL =8Q;f=1kHz

"

TYP

2.5

v
i

10

01()2

1()2

P

V
......

i-

I

~

}

.... ".

0
100

R(Q)

NOTE:

NOTE:

C"" 1J.lF. f ... 1kHz.

Po = 3.5W; f -1kHz.

Figure 5. Input Impedance as a
Function of R(Q) in Test Circuit

t-H++ttHt--t-H+tHit--ViH+tttH

50

Figure 6. Total Harmonic Distortion as
a Function of Rs(Q) In the Test Circuit

liji
/0/

APPLICATION INFORMATION

R1

..ok

VOWME

+

t-----ovcc

+

TONE

Figure 7. Total Power Dissipation and
Efficiency as a Function of
Output Power

10

C9

22O.F

."lit.

7.5

~

Ji

5

11

2.5

Figure 8. Ceramic Pick-Up Amplifier Circuit

,...

-

10- 1

/

V-

I

10

NOTES:
_ _ with tone control
- - - without tone control. In CircUit of Figure 8,
typical values

Figure 9. Total Harmonic Distortion as
a Function of Output Power

November 6, 1986

7-277

•

TDA7050

Signetics

Low Voltage Mono/Stereo
Power Amplifier
Product Specification
Linear Products

DESCRIPTION
The TDA7050T is a low voltage audio
amplifier for small radios with headphones (such as watch, pen and pocket
radios) in mono (bridge-tied load) or
stereo applications.

FEATURES
• Limited to battery supply
application only (Typ. 3 and 4V)
• Operates with supply voltage
down to 1.6V
• No external components required
• Very low quiescent current
• Fixed integrated gain of 26dB,
floating differential input
• Flexibility in use - mono BTL as
well as stereo
• Small dimension of encapsulation

0

PIN CONFIGURATION
N, D Packages

N?:~.w,

INV INPUT, 2

vee
7 OUTPUT,

INV INPUT2 3

OUTPUT2

N?:P~~ 4

5 GROUND
lOP VIEW
C0137SO$

APPLICATIONS
• Portable radio
• Personal computer
• Speech synthesis
• Telephone
• Modem
ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic SO Package
(SOT-96A; SO-8)

o to

+70·C

TDA7050TD

8-Pin Plastic DIP (SOT-97A)

o to

+70·C

TDA7050TN

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL
Vec

Supply voltage

10M

Peak output current

PTOT

Total power dissipation

TSTG

Storage temperature range

Tc

Crystal temperature

tsc

AC and DC short-circuit duration at
Vec = 3.0V (during mishandling)

October 10, 1986

RATING

UNIT

6

V

150

mA

see derating
curve, Figure 1
-55 to +150

·C

100

·C

5

s

7-278

853-0896 85941

I,
Signetlcs Linear Products

:1

Product Specification

I

1

Low Voltage Mono/Stereo Power Amplifier

TDA7050

DC ELECTRICAL CHARACTERISTICS vee = 3V; f = 1kHz; RL = 32il; TA = 25°C, unless otherwise specified.
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Supply
Vee

Supply voltage

ITOT

Total quiescent current

1.6
3.2

6.0

V

4

mA

Bridge-tied load application (BTL); see Figure 4
Po
Po

Output power1
Vee = 3.0V; c!,ot = 10%
Vee = 4.5V; c!,ot = 10% (RL = 64il)

140
150

mW
mW

Gv

Voltage gain

32

dB

VNO(RMS)

Noise output voltage (RMS value)
Rs = 5kS1; f = 1kHz

140

1t.V\
1Z,1

Input impedance (at Rs = w)

I,

Input bias current

DC output offset voltage (at Rs = 5 kil)

p.V
70

1

mV
Mil

40

nA

Stereo application; see Figure 5
Po
Po

Output power1
Vee = 3.0V; dtot = 10%
Vee = 4.5V; dtot = 10%

35
75

mW
mW

Gv

Voltage gain

26

dB

VNO(RMS)

Noise output voltage (RMS value)
Rs = 5kil; f = 1kHz

100

p.V

ex

Channel separation
Rs=Oil; f=lkHz

Ilil

Input impedance (at Rs =

II

Input bias current

30

'1

40

2

dB
Mil

20

nA

NOTE:

1. Output power is measured directly at the output pins of the IC. It is shown as a function of the supply voltage in Figure 2 (BTL Application) and in
Figure 3 (Stereo Application).

SO PACKAGE DESIGN
EXAMPLE

400

300

To achieve the small dimension of the encap·
sulation the SO package is preferred with
only 8 pins. Because a heatsink is not appli·
cable, the dissipation is limited by the thermal
resistance of the 8·pin SO encapsulation
until:

\

\
100

o

-50

\
\
100

150

Figure 1. Power Derating Curve

October 10, 1986

7-279

•

Signetics Linear Products

Product Specification

Low Voltage Mono/Stereo Power Amplifier

200

I
RL =32Q

I /

100

200

V
/

I
RL =16Q ,/

I

/64Q

1/

100

32Q

,/

50

/

l/
20

10

10

Figure 2. Output Power Across the
Load Impedance (Rd as a Function
of Supply Voltage (Vee) in BTL
Application. Measurements Were
Made at f = 1kHz; d tet = 10%;

TA = 25°C

64Q

:/

!L

o

Figure 3. Output Power Across the
Load Impedance (Rd as a Function
of Supply Voltage (Vee) in Stereo
Application. Measurements Were
Made at f = 1kHz; dtet = 10%;

TA

=25°C

LEFT CHANNEL
INPUT

INPUT~Rs
22k

/

VI

20

o

TDA7050

i
i

Vee

Rs

22k

-.---'-f-l

RIGHT CHANNEL
INPUT

2

1

Rs

22k

Figure 5. Application Diagram (Stereo);
Also Used as Test Circuit

Figure 4. Application Diagram (BTL);
Also Used as Test Circuit

October 10, 1986

7-280

TDA7052

SigneHcs

1 Watt Low Voltage Audio
Power Amplifier
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The TDA7052 is a 1 Watt power amplifier in an a-pin DIP plastic package. The
device is designed for audio applications. It can be used for motor driver
applications. It operates from a supply
voltage of 3 to 15V. It has a proprietary
circuit design making use of the BridgeTied Load (BTL) principle. The TDA7052
makes use of no external passive components.

•
•
•
•
•
•
•
•
•
•
•
•
•

.r~:::;

....

GOOD

MUTE I ..PUT

Vee
_

•• OUT"'.I?

.S

'MO"'
~"~~~""'NU

,.

,.

:;U~'=~T

4

,,.

0000

u

:-':'<::1'.:"

,.

..

MUT~~.r:.:.'? •
...... MUY~~r:.:.'? 7
Q ...... OA~:.::~:

"
,0

•

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

o·e to +70·e

TDA7052PN

BLOCK DIAGRAM
Vee
TDA7052

> .......-r

5 _OUTPUT 1

INPUT

3

> ....-f'8~OUTPUT 2

GROUND (SUBSTRATE)

7-281

PIN NO.

1
2
3

SYMBOL

Vee

t.':'~J.'t.":."'NG
::'~"';;'~':."'''Q

.. L'M,TI!A

TOP

Communications equipment
Speech synthesis output
Portable equipment
Motor drivers
Audio amplifiers
Personal computers
Radio/TV

8-Pin Plastic package (SOT-97)

December 1988

N Package

APPLICATIONS

ORDERING INFORMATION

GROUND
(SIGNAL)

0". .

PIN CONFIGURATION

No external components
No switch-on or switch-off clicks
Good overall stability
Low power consumption
No external heatsink required
Short-circuit proof

v,.w
DESCRIPTION
Supply voltage.

IN

Input

GND1
NC

Ground (signal)
Not connected.

OUT 1
GND2

Output 1
Output 2.

NC

Not connected.

OUT,

Output 2

Signetics Linear Products

Preliminary Specification

1 Watt low Voltage Audio Power Amplifier

TDA7052

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vcc

Supply voltage

18

V

IOSM

Non-repetitive peak output current

1.5

A

PTOT

Operating ambient temperature range

See Figure 1

mW

150

·C

-65 to + 150

·C

Te
TSTG

PARAMETER

Operating junction
Storage temperature range

DC ELECTRICAL CHARACTERISTICS VeeA = 6V; RL = 8n; f = 1kHZ; TA = 25·C; unless otherwise specified.
SYMBOL

PARAMETER

Vee

Supply voltage range

ITOT

Total quiescent current

Gv

Voltage gain

Po

Output power

TEST
CONDITIONS

RL =

00

LIMITS
UNIT
Min

Typ

Max

3

6

15

V

-

4

8

mA

39

40

41

dB

1.0

1.2

-

W

VNO(RMS)

-

150

300

p.V

VNO(RMS)

-

60

-

dB

THD= 10%

Noise output voltage 1.2
(RMS value)

fR

Frequency response

20

SVRR

Supply voltage ripple rejection

40

20k

Hz

50

-

dB
mV

tJ.Vs_a

DC output offset voltage Pin 5 - 8

Rs=5kn

-

-

100

THD

Total harmonic distortion

PO=O.IW

0.2

1.0

%

/Zli

Input impedance

100

-

kn

IBIAS

I nput bias current

-

100

300

nA

NOTES:

1. The unwelghted RMS noise output voltage is measured at a bandwidth of 60kHz with a source impedance (Rs) of 5kn.
2. The RMS output voltage is measured at a bandwidth of 5kHz with a source Impedance of on and a frequency of 500kHz. With a practical load (R = an;
L = 200jlH). the nOise output current is only 100nA.
3. Ripple relectlon IS measured at the output with a source Impedance of on and a frequency between 100Hz and 10kHz The ripple voltage = 200mV (RMS value) IS
applied to the positive supply rail.

December 1988

7-282

Preliminary Specification

Signetics Linear Products

TDA7052

1 Watt low Voltage Audio Power Amplifier

FUNCTIONAL DESCRIPTION
The TDA7052 IS an output amplifier designed
for battery-powered portable audio applications, such as portable and industrial equipment. The TDA7052 uses the Bridge-TiedLoad principle (BTL) which can deliver an
output power of 1.2W (THD = 10%) into an
load with a power supply of 6V. The load
can be short-circuited at each signal output.
The gain is fixed internally at 40dB.

1200

I-- I-\.

\
800

\

an

\

400

o-25

\
0

1\

150

Figure 1. Power Derating Curve.

POWER DISSIPATION
Assume Vcc = 6V;
mum.

RL =

r--------------1------1- Vee = 6V

8$1; T A = 50°C maxi-

The maximum sinewave dlsslpallOn is 0.9W.
8JA

= (150-50)/0.9'"

110°C/W.

Where 8JA of the package is 11 O°C/W, so no
external heatsink is required.

V,-p_---1-1

RS=
5k

--~--~----------~---------------------GND

Figure 2. TDA7052 Application Diagram.

December 1988

7-283

•

SAA7210

Signetics

Decoder for Compact Disc
Digital Audio System
Product Specification
Linear Products
DESCRIPTION
The 8AA7210 incorporates the functions
of demodulator, subcoding processor,
error corrector, and concealment in one
chip. The device accepts data from the
disc and outputs serial data directly to a
dual 16-bit digital-to-analog converter
TDA1541 (DAC) via the Inter-Ie signal
bus (1 2 8). The 12 8 output can also be fed
via the stereo interpolating digital filter
8AA7220 which provides additional concealment plus oversampling digital filtering. For descriptive purposes, the
8AA7210 is referred to as the A-chip
and the 8AA7220 as the 8-chip.

FEATURES
• Adaptive slicer with highfrequency level detector for input
data
• Built-in drop-out detector to
prevent error propagation in
adaptive slicer
• Fully protected timing
synchronization to incoming data

• Eight-to-Fourteen Modulation
(EFM) decoding
• Cross-Interleaved Reed-Solomon
Code (CIRC) used for error
correction system
• Subcodlng microprocessor
handshaking protocol
• Motor speed control logic which
stabilizes the input data rate
• Error flag processing to identify
unreliable data
• Concealment to replace
uncorrectable data
• 12 S bus for data exchange
between A-chip, B-chip, and DAC
• Bidirectional data bus to external
RAM (16k X 4 bits)

PIN CONFIGURATION
N Package

APPLICATION
• Compact disc digital audio
system

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-20°C to + 70°C

SAA721ON

40-P,n Plastic DIP (SOT·129)

TOP VIEW

ABSOLUTE MAXIMUM RATINGS

RATING

UNIT

Voo

Supply voltage range (Pin 40)

-0.5 to +7.0

V

V,

Maximum input voltage range

-0.5 to V DD + 0.5

V

I,

Input current (Pin 23)

5

mA

Vo

Maximum output voltage range
(Pin 17, 33)

-0.5 to +7.0

V

10

Output current (each output)

10

mA

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-20 to +70

°C

YES

Electrostatic handling'

-1000 to +1000

V

SYMBOL

PARAMETER

NOTE:
*Equlvalent to discharging a 100pF capacitor through a 1.Skn senes resistor With a rise time of 15n5.

February 24, 1987

7-284

853-0216 87735

Product Specification

Signetics linear Products

Decoder for Compact Disc Digital Audio System

SAA721 0

PIN DESCRIPTION
PIN NO.

MNEMONIC

1-8

AO-A7

Address: address outputs to external RAM.

DESCRIPTION

9

RAS

Row Address Select: output to external RAM (4416) which uses multiplexed address Inputs

10

R/IN

Read/Write: output signal to external RAM

11

MUTE

Mute: Input from the microprocessor When mute IS LOW, the data output DAAB (Pin 37) IS attenuated to zero In 15
successive dlvlde-by-2 steps. On the riSing edge of mute, the data output IS Incremented to the first "good" value In
2 steps This Input has an Internal pull-up of 50kn (typ)

D1-D3

Data: data Inputs/outputs to external RAM

15

CAS

Column Address Select: output signal to external RAM

16

D4

Data: data Input! output to external RAM

17

MSC

Motor Speed Control: open-dram output which proVides a pulse width modulated signal with a pulse rate of 88kHz
to control the rate of data entry. The duty factor vanes from 1 6% to 98.4% m 62 steps When a motor~start signal IS
detected via Pin 33 (SWAB/SSM) the duty factor IS forced to 98.4% for 02 seconds followed by a normal
calculated signal After a motor~stop signal IS detected, the duty factor IS forced to 1 6% for 0.2 seconds, followed
by a continuous 50% duty factor

12-14

18

XTAl2

Crystal Oscillator Output: dnve output to clock crystal (11 2896MHz typ.)

19

XTAL1

Crystal Oscillator Input: Input from crystal OSCillator or slave clock

20

Vss

Ground: circuit ground potential

21

VBB

Back Bias Supply Voltage: back bias output voltage (-2.5V ± 20%) The Internal back bias generator can be
decoupled at thiS pm

22

PD/OC

Phase Detector Output/Oscillator Control Input: outputs of the frequency detector and phase detector are
summed Internally, then filtered at thiS pin to provide the frequency control signal for the VCO

23

IREF

Current Reference: external reference Input to the phase detector ThiS Input IS required to minimiZe the spread In
the charge pump output of the phase detector An Internal clamp prevents the voltage on thiS pin from nSlng above
35V

24

FB

Feedback: output from the Input data shcer ThiS output IS a current source of 100pA (typ) which changes polanty
when the level detector Input at Pin 25 (HFI) nses above the threshold voltage of 2V (tYPical). When a data run
length vlolallon IS detected (e g , dunng drop-out). or when HFD (Pin 26) IS lOW, thiS output goes to high Impedance
state

25

HFI

High-Frequency Input: level detector Input to the data shcer A differential signal of between 0 25 and 2 5V (peakto-peak value) IS reqUired to dnve the data shcer correctly When aTMAX violation IS detected or when HFO IS LOW,
thiS Input IS biased directly to ItS threshold voltage

26

HFD

High-Frequency Detector: when HIGH, thiS mput Signal enables the frequency and phase detector mputs, also the
feedback output (FB) from the data slicer
An Internal voltage clamp of 3V (typIcal) reqUires the HFO Input to be fed via a high Impedance ThiS Input has an
Internal pull-up of 50kn (typical)

27

CEFM

Clock Eight-to-Fourteen Modulation: demodulator clock output 4 3218MHz (typcal)

28

CRI

Counter Reset Inhibit: when LOW, thiS Input Signal allows the dlvlde-by~588 master counter m the OEMOO timing
to run free ThiS Input has an Internal pull-up of 50kn (typical).

29

ODATA

Q-Channel Data: thiS subcodmg output IS panty checked and changes In response to the Q-channel clock Input
(see subcodlng microprocessor handshaking protocol)

30

ORA

Q-Channel Request Input/Acknowledge Output: the output has an Internal pull-up of nominally 10kn (See
subcodlng microprocessor handshaking protocol)

31

OCl

Q-Channel Clock: clock mput generated by the microprocessor when It detects a ORA LOW signal.

32

DEEM

De-emphasis: Signal denved from one bit of the panty-checked O-channel and fed out via the debounce Circuit.

33

SWAB/SSM

Subcoding Word Clock Output and Start/Stop Motor Input: open-drain output which IS sensed dunng each
HIGH penod, and If externally forced LOW, a motor-stop condition will be decoded and fed to the motor control logic
CirCUit

34

SDAB

Subcoding Data: a 1O~blt burst of data, Including flags and sync bits, IS output senally to the
clocked by burst clock output SCAB (see Figure 2)

8~chlp

once per frame

35

SCAB

Subcoding Clock: a 10-blt burst clock 2 8224MHz (typ) output which IS used to synchronize the subcodlng data.

36

EFAB

Error Flag: output from InterpolatIon and mute CirCUit to

37

DAAB

Data: thiS output which IS fed to the B-chlp or DAC, together With ItS clock (ClAB) and word select (WSAB) outputs.
conforms to the 12 8 bus format (see Figure 3)

38

CLAB

Clock: output to B-chlp or DAC

39

WSAB

Word Select: output to B-chlp or DAC

40

VDD

Power Supply: poSItive supply voltage (+ 5V)

8~chlp

Indicating unreliable data

NOTE:
The pin sequence of the address outputs (AO-A7) and the data outputs (01-D4) has been selected to be compatible With vanous dynamic 16K X
bit RAMs Including the 4416

February 24, 1987

7-285

•
4~

;;l1

UI

I

0

r
0

~

~
~

""

c
5>
I:)

aCL

HFIN~~~
I;~I
I~:

l:J
~

i:

\Q

0

co

a.

:J
 fXTAL

3. Reference levels - O.SV and 2.5V.
4. Output nse and fall times measured with load capacitance (Cd = 50pF.
5. Q-channel access times dependent on cyclic redundancy check (CRG).

7-290

and

fXTAl

< -2- .

ns
ms

10.8

NOTES:

February 24. 1987

ns
500

ms

Signetics Linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

SAA7210

"I

1 FRAME = 588 CHANNEL BITS

31

32

SYNC

I

MAY BE INVERTED

- - - - - - - - + 1..

: . . - - - 14 BIT EFM WORD

----<*.....

NOTE:

(1):r< mergmg and low frequency suppression bits

Figure 1. Data Input Signal

FUNCTIONAL DESCRIPTION
Demodulation
Data read from the disc IS amplified and
filtered externally and then converted Into a
clean digital signal by the data slicer. The
data slicer IS an adaptive level detector which
relies on the nature of the elght-to-fourteen
modulation system (EFM) to determine the
optimum slicing level. When a signal drop-out
is detected (via the HFD input, or Internally
when a data run length violation is detected)
the feedback (FB) to the data slicer is disabled to stop dnft of the slicing level.
Two frequency detectors, a phase detector,
and a vOltage-controlled oscillator (VCO)
form an internal phase-locked loop (PLL)
system. The voltage-controlled oscillator
(VCO) runs at twice the Input data rate
(typically at 8.6436MHz), its frequency being
dependent on the voltage at Pin 22 (PD/OC).
One of the frequency detectors compares the
VCO frequency with that of the crystal clock
to provide coarse frequency-control signals
which pull the VCO to within the capture
range of fine frequency control. Signals for
fine frequency control are provided by the
second frequency detector which uses data
run length violations to pull the VCO within
the capture range of the PLL. When the
system IS phase-locked, the frequency detector output stage IS disabled via a lock indication signal. The VCO output is divided by two
to provide the main demodulator clock signal
which IS compared with the incoming data In
the phase detector. The output of the phase
detector, which is combined Internally with
the frequency detector outputs at Pin 22 (PDI

February 24, 1987

OC), IS a positive and negative current pulse
with a net charge that IS dependent on the
phase error. The current amplitude IS determined by the current source connected to Pin
23 (IREF)'
The demodulator uses a double timing system to protect the EFM decoder from erroneous sync patterns In the data. The protected
divlde-by-588 master counter IS reset only If a
sync pattern occurs exactly one frame after a
prevIous sync pattern (sync cOincidence) or If
the new sync pattern occurs within a safe
window determined by the dlvide-by-588 master counter. If track jumping occurs, the d,vlde-by-588 master counter IS allowed to freerun to minimize Interference to the motor
speed controller; thiS IS achieved by taking
the CRI Input (Pin 28) Low to inhibit the reset
signal.
The sync cOincidence pulse IS also used to
reset the lock Ind,callOn counter and disable
the output from the fine frequency detector. If
the system goes out of lock, the sync pulses
cease and the lock Indication counter counts
frame periods. After 63 frame penods with no
sync coinCidence pulse, the lock Indication
counter enables the frequency detector output.
The EFM decoder converts each symbol (14
bits of disc data + 3 merging bits) Into one of
256 8-blt digital words which are then passed
across the clock Interface to the subcodlng
secllOn. An add,llOnal output from the decoder senses one of two extra symbol patterns
which indicate a subcoding frame sync. This
signal, together with a data strobe and two
error flags, IS also passed across the clock

7-291

Interface. The error flags are denved from the
HFD Input and from detected run length
violations.

Subcoding
The subcodlng section has four main functions
• Q-channel processor
• De-emphasis output
• Pause (P-blt) output
• Serial subcoding output to B-chip
The Q-channel processor accumulates a subcoding word of 96 bits from the Q-bit of
successive subcodlng symbols, performs a
cyclic redundancy check (CRC) using 16 bits
and then outputs the remaining 80 bits to a
microprocessor on an external clock. The deemphasIs signal (DEEM) is derived from one
bit of the CRC-checked Q-channel. The
DEEM output (Pin 32) IS additionally protected by a debounce Circuit.
The P-blt from the subcodlng symbol, also
protected by a debounce CirCUit, IS output via
the senal subcoding signal (SDAB) at Pin 34.
The protected timing used for the EFM decoder makes thiS output unreliable during
track jumping.
The senal output to the B-chip consists of a
burst of 10 bits of data clocked by a burst
clock (SCAB). The 10 bits are made up from
subcodlng signal bits Q to W, the Q-channel
panty check flag, a demodulator error flag
and the subcoding sync signal. At the end of
the clock burst, thiS output delivers the debounced P-bit signal which can be read
externally on the rising edge of SWAB at Pin
33 (see Figure 2).

•

Signetics linear Products

Product Specification

SAA721 0

Decoder for Compact Disc Digital Audio System

CRC ERROR BIT

\
SOAB

SUBCODING ERROR FLAG
(NOT USED SAA7220)

SYNC (ACTIVE LOW)

/

/

P-BIT

SCAB
2.8224 MHz BURST CLOCK
SUBCODE WORD FREQUENCY = 7.35 kHz

Figure 2. Typical Subcoding Waveform Outputs

Pre-FIFO
The 10 bits (8 bits of symbol data + 2 error
flag bits) which are passed from the demodulator across the clock interface to the subcodIng section are also fed to the pre-FIFO with
the addition of two timing signals. These two
timing signals indicate:

therefore, in each access cycle, a row address (RAS Pin 9) is set up first and then
three 4-bit nibbles are accessed using sequential column addresses (CAS Pin 15). As
only 10 bits are used for each symbol (including flags), the fourth nibble is not accessible.

(1) That a new data symbol is valid

There are 4 different modes of RAM access:
• WRITE 1

(2) Whether the new data symbol is the first
symbol of a frame.

• READ 1
• WRITE 2

The pre-FIFO stores up to 4 symbols (including flags) and acts as a time buffer between
data input and data output. Data passes into
the pre-FIFO at the rate of 32 symbols per
demodulator frame and the symbols are
called from the pre-FIFO into RAM storage at
the rate of 32 symbols per error-correction
frame. The timing, organized by the master
controller, allows up to 40 attempts to write
32 symbols into the RAM per error-correction
frame. The 8 extra attempts allow for transient changes in clock frequency (e.g., pitch
control).

• READ 2
During WRITE 1, data IS taken from pre-FIFO
at regular intervals and written into one half of
the RAM. This half of the RAM acts as the
main FIFO and has a capacity of up to 64
frames. During READ 1, the 32 symbols of
the next frame due out are read from the
FIFO. The numerical difference between the
WRITE 1 and READ 1 addresses is used to
control the speed of the diSC drove motor.

This section controls the flow of data between the external RAM and the error corrector. Each symbol of data passes through the
error corrector two times (correction processes C1 and C2) before entering the concealment section.

When a frame of data has been read from the
FIFO it is stored in a buffer RAM until it can
be accepted by the CIRC error correction
system. At this time the error correcting
strategy of the CIRC decoder for the frame is
determined by the flag processor. The frame
for correction IS then loaded Into the decoder
one symbol at a time and the 32 symbols
from the previous correction are returned to
the buffer RAM.

The RAM interface uses the full crystal frequency of 11.2MHz to determine the RAM
access waveforms (the main clock for the
system is 5.6MHz). One RAM access (READ
or WRITE) uses 12 crystal clock cycles which
is approximately 1!Is. The timing (see Figure
4) is based upon the specification for the
dynamic 16k X 4-bit RAM (4416). ThiS RAM
requires multiplexed address signals and

After the first correction (C1), only 28 of the
symbols are required per frame. The symbols
are stored in the buffer RAM together with
new flags generated after the correction cycle
by the flag updating logiC. ThiS partiallycorrected frame is then passed to the externa RAM by a WRITE 2 instruction. The deInterleaving process is carned out during thiS
second passage through the external RAM.

Data Control

February 24, 1987

7-292

The WRITE 2 and READ 2 addresses for
each symbol provide the correct delay of 108
frames for the first symbol and zero delay for
the last symbol.
After execution of the READ 2 Instruction, the
frame of 28 symbols IS again stored in the
buffer RAM pending readiness of the CIRC
decoder and calculation of decoding strategy.
FollOWing the second correction (C2), 24
symbols including unreliable data flags (URD)
are stored In the buffer RAM and then output
to the concealment section at regular intervals.

Flag Processing
Flag processing is carned out in two parts as
follows:
• Flag strategy logic
• Flag updating logic.
While a frame of data from the external
memory IS being wrotten into the buffer RAM,
the error flags associated with that frame are
counted. Two bits are used for the flags, thus
"good" data (flags = 00) and three levels of
error can be Indicated.
The optimum strategy to be used by the CIRC
error corrector is determined by the 2-bit flag
information used by the flag strategy logic
ROM in conjunction with its associated arithmetic unit (ALU). The flags for the C1 correction are generated in the demodulator and
are based on detected signal drop-outs and
data run length violations. Updating of the
flags after C1 IS dependent on the CIRC
decoder correction of that frame. The updated flags are used to determine the C2
strategy. After C2 correction a single flag
(URD) IS generated to accompany the data
into the concealment section.

Signetics Linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

SAA7210

s=x

LEFT SAMPLE

RIGHT SAMPlE

DAAB

I

I

-~

I

~I

¥

EFAB

LEFT ERROR FLAG

I

tI

WSAB

!

RIGHT ERROR FLAG

I
I

I
I

_-LIlSlI

CLAB

I·

·1

11.:w".

2.8224 MHz

Figure 3. Typical Waveform Outputs to B-Chip or DAC

CRYSTAL

CLOCK

I
ADDRESS

RAS

I

I

I

I

I

~~____RO_W____-J)(~____C_O_LU_M_N_1__-J)(~___C_O_L_U_MN__2 __-J)(r----CO-L-U-M-N-3--~~r-----A-O-W------~

~

---J{

\ ' -_ _ _ _ _ _ _ _ _ _ _ _

I

\~---

I

j,-------

RIW

DATA

(WRITE)

_+-____________-' ,,__--;________....1. ,'--__________- '

0

I

J)---------------(

DATA,

(READ)

/"".t------

}------(

-+-______--'

' -_ _ _ _ _ _ _ _ _

0

I

)--------<

~---------

RAM ACCESS CYCLE (6 SYSTEM CLOCK CYCLES" 1 063., NOMINAL) - - - - - _ . \

Figure 4. RAM Timing Waveforms: Timing Based on RAM TMS4416; G Input to RAM Held Low

February 24. 1987

7-293

•

Signetics Linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

CIRC Decoding
Data on the compact disc is encoded according to a cross-interleaved Reed-Solomon
code (CIRC) and this decoder explo~s fully
the error-correction capabilities of the code.
Decoding is performed in two cycles, and in
each cycle the CIRC decoder corrects data In
accordance with the following formula:

symbol memory. From these syndromes errors can be detected and corrected.

'good' value in two steps using the interpolator.

Microcoded Correction Processing
The processor uses an Arithmetic Logic Unit
(ALU) which Includes a multiplier based on
logarithms. The correction algorithm follows
the microcode program stored in a ROM.

All erroneous data supplied to the concealment section continues tG", be flagged when it
is output to the B-chip where ~ receives
additional and more efficient concealment.

Concealment
This section combines 8-bit data symbols into
left and right stereo channels. Each channel
has a 16-bit capacity and holds two symbols
(a stereo sample). The channels operate
independently. A concealment operation is
performed when a URD flag accompanies
either symbol in a stereo sample. If a single
erroneous sample is flagged between two
'good' samples then linear interpolation IS
used to replace the erroneous value. If two or
more successive samples are flagged, a sample-and-hold is applied and the last of the
erroneous samples is interpolated to a value
between that of the hold and that of the
following 'good' sample.

2t+e=4
where:
e = the number of erasures (erroneous
symbols whose position is known).
t - allowed number of additional failures
which the decoder program has to find.
The flag processor points to the erasure
symbols and tells the CIRC decoder how
many additional fat/ures are allowed. If the
error corrector is presented with more than
the maximum it will stop and flag all symbols
as unreliable.
The CIRC decoder is comprised of two sections: Syndrome formation and micro-coded
correction processing.

If MUTE is requested, the data In each
channel is attenuated to zero in 15 successive divlde-by-two steps. At the end of a mute
period, the outpu1 is incremented to the first

Syndrome Formation
Four correction syndromes are calculated
while the frame of data is being written into a

SAA721 0

Motor Speed Control (see
Figure 5)
The motor speed control (MSC) output from
Pin 17 is a pulse width modulated signal. The
duty factor of the pulse width modulation is
calculated from the difference in numerical
value between the WRITE 1 and READ 1
addresses, the difference being nominally
half of the FIFO space. The calculation is
performed at a rate of 88.2kHz.
The duty factor of MSC varies in 62 steps
from 1.6% (FIFO full) to 98.4% (FIFO empty).
When a motor-start signal is detected (via
SWAB/SSM) the duty factor is forced to
98.4% for 0.2 seconds followed by a normal,
calculated signal. After a motor-stop signal is
detected, the duty factor is forced to 1.6% for
0.2 seconds followed by a continuous 50%
duty factor. A change in motor-start/-stop
status occurring Within the 0.2 second periods
overrides the previous condition and resets
the data control timer.

MEAN
PWM

OU'IPUT
SIGNAL

18

0'

,,

2

FlFOF\LL
WINHIIIT

I 24
20

,,

32'40

'I',

48

I

~
I

NOMINAL
WORKING
POINT

5&

FAM:s

J 83
OF
AAMSPACE
FIFO EMPn UNOCCUPIED

'r

R INHI8JT

Figure 5. Motor Speed Control

I,

I.

'.

I,

NOTE:
Reference levels - 0 8V and 2 OV

Figure 6_ Typical Data Output Waveforms to B-Chip or DAC

February 24, 1987

7-294

Signetics Linear Products

Product Specification

SAA721 0

Decoder for Compact Disc Digital Audio System

SCAB

SDAB

SWAB

NOTES:
1. Reference levels for SCAB and SDAB '" 0 BV and 2 OV
2 Reference levels for SWAB = 0 BV and 40V

Figure 7. Typical Subcoding Data Output Waveforms

CODEDNRZ-1

0

1

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

DECODED EOUIVALENT

ORLJ
Figure 8. Non-Return to Zero (NRZ) Representation

Table 1. Codes Used to Define Subcoding Frame Sync
8-BIT NRZ DATA SYMBOL

14-BIT EQUIVALENT CODE WORD

01

02

03

04

05

06

07

08

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

x
x

0

0

1
1

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0

0
0

0
0

0

1

0

1
1

1

1

1
1

1

1

1
1

1

0

P

Q

R

S

T

U

V

W

0

1

C14

NOTE:
Where: X = don't care state.

APPLICATION INFORMATION
EFM Encoding System
The Eight-to-Fourteen Modulation (EFM)
code used in the Compact Disc Digital Audio
system is designed to restrict the bandwidth
of the data on the disc and to present a DC
free signal to the demodulator. In this modulation system, the data run length between
transitions is;;' 3 clock periods and';;; 11
clock periods. The number of bits per symbol
is 17, including three merging and low frequency suppression bits which also assist in
the removal of the DC content.

February 24, 1987

The conversion from 8-bit, non-return-to-zero
(NRZ) symbols to equivalent 14-bit code
words is shown in Table 2. C1 IS the first bit of
a 14-bit code word read from the disc and 01
IS the Most Significant Bit (MSB) of the data
sent to the error corrector. The 14-bit code
words are given in NRZ-I representation in
which a logic 1 means a transition at the
beginning of that bit from HIGH-to-LOW or
LOW-to-HIGH (see Figure 8).
The codes shown in Table 2 cover the normal
256 possibilities for an 8-bit data symbol.
There are other combinations of 14-bit codes

7-295

which, although they obey the EFM rules for
maximum and minimum run length (T MAX,
T MIN)' produce unspecified data output symbols. Two of these extra codes are used in
the subcodlng data to define a subcoding
frame sync and are as shown in Table 1.
When a subcoding frame sync is detected,
the P-bit (Pause-bit) of the data is ignored by
the debounce circuitry. The remaining bits (Q
to W) are not specified in the system but
always appear at the serial output as shown
in Table 1.

•

Product Specification

Signetics Linear Products

SAA721 0

Decoder for Compact Disc Digital Audio System

Table 2. EFM Code Conversion
NO.

DNZ DATA
SYMBOL

D8

D1

o
1
2
3
4

5
6
7
8
9
10
11
to
119
120
121
122
123
124
125
126
127

EQUIVALENT CODE WORD

1 001 000 1 0 0
1 0 0 0 0 1 0 0 0 0 0
100 1 0 0 001 0 0
1 000 1 000 1 0 0
o 1 000 1 0 0 0 0 0
o 0 0 0 0 1 000 1 0
000 1 0 0 0 0 1 0 0
00100 1 0 0 0 0 0
o 1 001 001 000
1 0 0 0 0 0 0 1 0 0 0
100 1 000 1 000

000
0 0 0
0 0 0
0 0 0
000
0 0 0
000
000
000
000
0 0 0

o
o
o
o
o
o
o

o
o

000 000 0 1 0
001 001 000
0 0 0 000 0 1 0
0 0 0 0 0 0 0 1 0
0 0 0 0 000 1 0
0 0 000 0 0 1 0
0 000 0 001 0
0 0 0 0 0 0 0 1 0

o

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1 0 0
100
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1

0
1
0
1
0
1
0
1

1 001
0 001
100 1 0
1 000 1
o1 0 0 0
o 0 001
000 1 0
001 0 0

Subcoding Microprocessor
Handshaking Protocol (see
Figures 9, 10, and 11)

128
129
130
131
132
133
134
135
136
137
138
139
to
247
248
249
250
251
252
253
254
255

1 000 0 0 0 0
1 0 0 0 0 001
1 0 0 0 0 0 1 0
1 0 0 0 0 0 1 1
1 0 0 0 0 1 0 0
10000101
1 0 0 0 0 1 1 0
1 0 0 0 0 1 1 1
1 000 1 000
1 000 1 001
1 0 000 0 1 0

o 1 001 000 1 000 0 1
1 0 000 1 001 0 0 0 0 1
100 1 0 0 0 0 1 0 0 0 0 1
1 000 1 000 1 0 0 0 0 1
o 1 000 1 001 000 0 1
o 0 000 000 1 0 0 0 0 1
000 1 0 0 0 0 1 0 0 0 0 1
00100 1 001 0 0 0 0 1
o 1 001 001 000 001
1 000 0 001 0 0 0 0 0 1
100 1 000 1 0 0 0 001

111
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1

0 1 001 0 0 0 0 1
1 0 0 0 0 0 000 1
100 1 0 0 0 001
1 000 1 000 0 1
0 1 000 0 0 001
0 0 0 0 1 0 0 0 0 1
000 1 000 001
001 0 0 0 0 001

D1

o

1
1
1
1
1
1
1
1

DNZ DATA
SYMBOL

C14

C1

000 0 0 0 0 0
000 0 0 0 0 1
o 000 0 0 1 0
o0 0 0 0 0 1 1
00000 1 0 0
o 000 0 1 0 1
o 000 0 1 1 0
00000 1 1 1
0 001 000
0000100 1
o 0 0 0 1 010

o

NO,

EQUIVALENT CODE WORD
D8

1
1
1
1
1
1
1
1

100 0
100 1
101 0
101 1
1 100
1 101
1 110
1 111

MICROPROCESSOR

C1

C14

001
001
001
001
001
001
001
001

0
0
0
0
0
0
0
0

SAAmo

The ORA line is normally held LOW by the
microprocessor.
When the microprocessor needs data (Request) it releases the ORA line and allows It
to be pulled HIGH by the pull-up resistor in
the SAA7210.
The SM7210 IS continuously collecting 0channel data, and when it deteC1s that ORA is
HIGH, It holds the first frame of O-channel
data for which the Cyclic Redundancy Check
(CRC) is 'good'. Then the SM7210 pulls
ORA LOW to tell the microprocessor that the
data is ready (Acknowledge) and enables the
OOATA output.
When the microprocessor detects a ORA
LOW signal, it generates a clock signal (OCL)
to shift the data out from the SM721 0 to the
microprocessor via the OOATA output. The
first negative edge of OCL also resets the
acknowledge signal and thus releases the
ORA line.
As soon as the microprocessor has received
suffiCient data (not necessarily 80 bits), it
pulls the ORA line LOW again. The SAA7210
now disables the OOATA output and resumes
collecllng new Q-channel data.

February 24, 1987

ENABLE
QCL
31
-----;C>------t-----~----~~--l)~--~CLOCK

Figure 9. Microprocessor Handshaking Protocol
If the microprocessor does not generate a
OCL signal within 10.8ms from the start of the
acknowledge (ORA LOW), the SAA7210 resets the acknowledge signal and allows the
ORA line to go HIGH again. The microprocessor stili has 2.3ms to accept the data, which
allows for a long propagation delay In the
microprocessor. After a further 13.33ms the
SM7210 will have received a new frame of
O-channel data and, provided the CRC is

7-296

'good', will give a fresh acknowledge signal.
ThiS refreshing process is repeated until the
microprocessor accepts the data or stops the
request.
When the microprocessor has a requirement
to hold the data for a long period before
acceptance, it prevents the refreshing process by setting OCL LOW after any acknowledge Signal.

Product Specification

Signetics Linear Products

SAA721 0

Decoder for Compact Disc Digital Audio System

DATA REQUEST
(MICROPROCESSOR
INTERNAL SIGNAL)

L._ _ _ _ _ _ _ _ _ _...:.._ _ _ _ _ _ _ __

I

i
:

-II-IOACK

..IIlLo
I

ORA _ _ _ _

lI

I

ACKNOWLEDGE
(SAA7210 _ _ _ _ _ _ _ _ _..1
INTERNAL SIGNAL)

____

~(

I

~j"I=-~'

IHi=-

------+---~Innnnnni

UUUUUUU

OCL

-11-'00
QDATA _ _~H~IG~H~I~M~P~ED~A~N~C~E_--{

HIGH IMPEDANCE

01

Figure 10. Q·Channel Timing Waveforms (Normal Mode)

r1
.._______________________________.....1

DATA REQUEST - - - - ,
(MICROPROCESSOR
INTERNAL SIGNAL)

L------InL.--____

ACKNOWLEDGE
(SAA7210
INTERNAL SIGNAL)

ORA

OCL

ODA

-------I{..________O_'_ _ _ _ _ _ _J}-----{..__O_'__~

I_

THIS WILL REPEAT
UNTIL OCL GOES LOW

.1

Figure 11. Q·Channel Timing Waveforms (Refresh Mode)

February 24, 1987

7-297

•

SAA7220

Signetics

Digital Filter for Compact Disc
Digital Audio System
Product Specification

Linear Products
DESCRIPTION
The SAA7220 is a stereo interpolating
digital filter designed for the Compact
Disc Digital Audio system. For descriptive purposes, the SAA 7220 is referred
to as the B-chip and the SAA7210 as the
A-chip.

FEATURES
• 16-bit serial data input (two's
complement)
• Interpolated data replaces
erroneous data samples
• -12dB attenuation via the active
Low attenuation input control
(ATSB)

• Smoothed transitions before and
after muting
• Two identical finite impulse
response transversal filters each
with a sampling rate of four
times that of the normal digital
audio data
• Digital audio output of 32-bit
words transmitted in biphasemark code
• 12S data transfer between
SAA7210 and 16-bit dual DAC
(TDA1541)

PIN CONFIGURATION
N Package

APPLICATIONS
• Compact disc digital audio
system

TOPYIEW

PIN NO. SYMBOL
DESCRIPTION
WSAB Word select: Input from A-chip
CLAB
Clock: Input from A-chiP, has an

• Digital filter

Internal pull-up
DAAB
EFAB

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-20·e to + 70·e

SAA7220N

24-Pin Plastic DIP

NC
SCAB

SOAB

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Voo

Supply voltage range (Pin 24)

PARAMETER

-0.5 to +7.0

V

V,

Maximum Input voltage range

-0.5 to Voo + 0.5

V

TSTG

Storage temperature range

-65 to +150

·e

TA

Operating ambient temperature range

-20 to +70

YES

Electrostatic handling 1

-1000 to + 1000

NC

XSYS
10

XOUT

·e

11

XIN

V

12
13

Vss
TEST

14

DOBM

15

DABO

16

ClBD
NC

NOTES:
All outputs are shortMclrcUit protected except the crystal oscillator output
1. EqUivalent to dlschargmg a 100pF capacitor through a 1 5[2 senes resistor with a rise time of 15ns

Data: Input from A-chip
Error flag: Active-High Input from Achip mdlcatlng unreliable data ThiS
Input has an Internal pult-down
Not connected
Subcode clock: a 10-bIt burst clock
282 24MHz (tYPical) Input which
synchrOnizes the subcode data ThiS
mput has an Internal pull-up
Subcode Data: a 10-bIt burst of
data, Including flags and sync bits
senally mput from the A-chip once
per frame clocked by burst clock
Input SCAB (see Figure 6) ThiS
Input has an mternal pull-down
Not connected
System clock output: 11 2896MHz
(tYPical) output to OAC and to A-chip
as slave clock Input
Crystal oscillator output: drive
output to clock crystal (11 2896MHz
typical)
Crystal OSCillator Input: Input from
crystal OSCillator or slave clock
Ground: CirCUit ground potential
Test Input: thiS Input has an Internal
pull-down In normal operation Pin 13
should be open CirCUit or connected
to Vss
Digital audio output: thiS output
contains digital audiO samples which
have received InterpolatIOn,
attenuation, and muting, plus
subcode data Transmission IS by
blphase-mark code
Data: thiS output which IS fed to the
DAC, together with ItS clock (CLBD)

~~~f;~~ t~el;;'~ I~S~~~a~u~~~~s,
17
18
19
20
21
22

December 2, 1986

7-298

WSSO
NC
NC
NC

ATSS

23

MUSB

24

VDD

Figure 5)
Clock: output to OAC
Not connected
Word select: output to DAC
Not connected
Not connected
Not connected
Attenuation: when Active-Low, thiS
control Input provides -12dB
attenuation ThiS Input has an
Internal pull-up
Mute: Active-Low control Input with
Internal pull-up
Power supply: positive supply
voltage (+ 5V)

853-1056 86703

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

BLOCK DIAGRAM
Voo (+5V)

24

CLAB

WSAB
OMB
EFAB

gSE====::~

0-"+-----------1

r ____~~::~F;::~------------~1~8~ WSBO

L____~~::~F;::~------------~1~6~

15

CLBD

L-----------------------~------+_----_+----------------------------------_+~~DABO

12
Vss

December 2, 1986

13
TEST

14
SCAB

SOAB

7-299

DOOM

Signetics Linear Products

Product Specification

SAA7220

Digital Filter for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS

Voo ~ 4.5 to 5.5V; Vss ~ OV; TA ~ -20°C to + 70°C, unless
otherwise specified

,---

LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

50

5.5

Supply
Voo

Supply voltage (Pin 24)

IDD

Supply current (Pin 24)

45

180

V
mA

Inputs
WSAB, DAAB
V,l

Input voltage Low

-0.3

+0.8

V,H

Input voltage High

20

Voo + 0.5

V

III

Input leakage current

-10

+10

I1A

C,

Input capacitance

7

pF

0

V

EFAB, SDAB 1
V,L

Input voltage Low

-0.3

+0.8

V

V,H

Input voltage High

2.0

Voo + 0.5

V

III
III

Input leakage current
at V, ~ OV
at V, ~ Voo

-10
+50

!1A

C,

Input capacitance

7

pF

I1A

CLAB, SCAB, ATSB, MUSB 2
V,L

Input voltage Low

-0.3

+0.8

V

V,H

Input voltage High

2.0

Voo + 0.5

V

III
III

Input leakage current
at V, ~ OV
at V, ~ Voo

-30
+10

!1A
!1A

C,

Input capacitance

7

pF

Crystal oscillator (see Figure 7)
Input XIN
Output XOUT
mAIV

1.5

GM

Mutual conductance at 100kHz

Ay

Small-signal voltage gain (Ay

C,

Input capacitance

10

pF

CFB

Feedback capacitance

5

pF

Co

Output capacitance

10

pF

III

Input leakage current

+10

I1A

~ GM

X Ro)

3.5

-10

VIV

0

Slave clock mode
V'(P.P)

Input voltage3 (peak-to-peak value)

3.0

Voo + 0.5

V

V,L

Input voltage Low3

0

1

V

3.0

Voo + 0.5

V

20

ns

20

ns

65

%

V,H

Input voltage Hlgh 3

tR

Input nse tlme 4

tF

Input fall tlme 4

tHIGH

Input High time at 2V (relative to clock penod)

December 2, 1986

35

7-300

Signetics Linear Products

Product Specification

SAA7220

Digital Filter for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) voo = 4.5 to 5.5V; Vss = OV;

TA = _20°C to

+ 70°C.

unless otherwise specified.

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Outputs
DABD, CLBD, WSBD
VOL

Output voltage Low at IOL - 1.6mA

VOH

Output voltage High at -IOH - 0.2mA

CL

Load capacitance

0

0.4

2.4

Voo

V

50

pF

V

V

XSYS&
VOL

Output voltage Low

0

0.4

VOH

Output voltage High

2.4

Voo

V

CL

Load capacitance

50

pF

0.6

V

DOBM
VL(P-PI

Voltage across a 7511 load via attenuator; see Figure 8
(peak-to-peak value)

0.4

NOTES:
I. Inputs EFAB and SOAB both have Internal pull-downs.
2. Inputs CLAB. SCAB. ATSii. and MlJSlj have internal pull-ups.
3. Ths mInimum peak-to-peak voltage can be reducad to 2V d the output XSYS is not being used. SImilarly V,H can be reduced to 2.4V (mIn.). All other levels remain
ths same.
4. Referenca levels = 10% and 90%.
5. The output current condItIons are dependent on the dnve condrtlOns. When a crystal oscillator IS beIng used. the output current capability IS IOL = + 1.6mA;
IOH = -0.2mA. But if a slave Input is beIng used. the output currents are reduced to IOL = + 0 2mA; IOH = -0.2mA.
6. Reference levels = O.BV and 2.0V.
7. The signal CLAB can run at eIther 2.BMHz (~4 system clock) or 1.4MHz (Ys system clock) under typIcal conditions. It does not have a mInimum or maxImum
frequency. but Is limited to being ~4 or Ys of the syslem clock frequency.
B. Input setup and hold bmes measured with respect to clock input from A-ChIp (CLAB). Referenca levels - O.BV and 2.0V.
9. Input setup and hold bmes measured WIth respect to subcode burst clock Input from A-chlp (SCAB). Referenca levels - O.BV and 2.0V.
10. Output setup and hold times measured WIth respect to system clock output (XSYS).
II. Output setup and hold tImes measured wrth respect to clock output (CLBO).
12. Output rise and fall tImes measured between the 10% and 90% levels; the data brt pulse WIdth measured at the 50% level.

December 2. 1986

7-301

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

FROM TIMING

AND CONTROL
FROM LEFT
ERROR
REGISTER

SCAB

FROM RIGHT
ERROR
REGISTER

+---------,

.::6+-t~-....

DOBM

Where:
SISR
SOSR
IOSR
AOSR

Subcode tnput shift register
Subcode output shift register
Intermediate output shift register
AudiO output shift register
Subcode word error flag

Figure 1. Digital Audio Output Block Diagram

December 2, 1986

7-302

Product Specification

Signetics Linear Products

Digital Filter for Compact Disc Digital Audio System

FUNCTIONAL DESCRIPTION

General
The SAA7220 incorporates the follOWing
functions:
• Interpolation of data in error
• Attenuation
• Muting
• Finite impulse response transversal
filtering with a four times increased
sampling rate
• A digital audio output
Serial data formatted in two's complement
(DAAB; Pin 3) is clocked in by ~s bit clock
(CLAB; Pin 2) together with word select
(WSAB; Pin 1) and error flag (EFAB; Pin 4).
After resynchronization with the internal
clocks, the data is separated into left and
right channels and fed to two identical Input
Shift Registers (IPSR). IOlernai timing and
control loads the data into the interpolation
RAM via the IOlermediate Input Shift Register
(IISR).
After interpolation, attenuation, and muting,
the data is fed serially from the Intermediate
Output Shift Register (IOSR) to the Audio
Output Shift Register (AOSR) and to the IISR.
From the IISR, it is loaded into the filter RAM.
After filtering, the data is passed to the Filter
Data Shift Register (FDSR). From the FDSR it
is transm~ed serially to the data output
(DABD; Pin 15) together with the appropriate
word select (WSBD; Pin 1B) and bit clock
(CLBD; Pin 16), in accordance with the 12 S
bus specHication. Data is again formatted in
two's complement. Outputs DABD, WSBD,

and CLBD are strobed to maintain the correct
timing relationship with the system clock
output (XSYS) at Pin 9 (see Figure 10).

erroneous samples following SIn -1)
SIn - 1) = the preceding sample
SIn + x) = the first following correct sample

I I I
I I

(Each ROM contains only 60 filter coefficients, the same 60 being used a second
time, but in the reverse order, to make a total
of 120.)
Data is stored in a 4BO-bit RAM (30
words X 16 bits). The 30 words are sequentially addressed 4 times to generate the 4
output samples.
When a new word is moved from the interpolation RAM to the filter RAM, the oldest word
is discarded and all other words moved one
position w~h respect to the ROM coefficients.
The data storage effectively forms a 30sample wide moving window on the input
data. The samples move within this window at
5.644BMHz, and the window moves one sample every 22.6118.

I II

I I

I

I I Y
I I
I

Y1
EftRORFLAG

• SAMPLE INTERPOLATEO OR HELD IN A-CHIP

I
Figure 2, Example of an Elght-5ample Unear Interpolation
December 2, 1986

The value of x is detected (1 to B) to
determine the coefficients for the multiplications. Eight coeffiCient pairs are stored in the
ROM. If x = 0 or;;' 9, then SIn) will remain
unchanged.

The subcode data (SDAB; Pin 7) and 10-bit
burst clock (SCAB; Pin 6) are resynchronized
to the internal clocks within the digital audio Attenuation
output block. SCAB clocks the data into the Attenuation is controlled by the ATSB input at
Pin 22. When the input is Active-Low, the
Subcode Input Shift Register (SISR; Figure 2).
Data is transferred to the Subcode Output sample is multiplied by a coefficieOl that
Shift Register (SOSR) on receipt of all of the provides -12dB attenuation. If the input is
10-bit burst clocks. The subcode data is then • High, the multiplication factor is 1.
mixed with the data from the AOSR and the
Mute
error flag to provide the output DOBM at Pin
Mute IS controlled by the MUSB input at Pin
14. SISR is reset when no clocks are de23. When the input is Active-Low, the value of
tected on the SCAB input.
the samples IS decreased smoothly to zero
following a cosine curve. 32 coefficients are
Interpolation
When, for either left or right channel, unrelia- used to step down the value of the data, each
ble samples are flagged between two correct one being used 31 times before stepping onto
samples, linear interpolation is used to re- the next. When MUSB is released (Pin 23
place the erroneous samples (up to a maxi- High), the samples are returned to the full
level again following a cosine curve with the
mum of B consecutive errors).
same coefficients being used in the reverse
When the error flag IS set, the sample is
order.
replaced by a value calculated by the following formula:
Filtering
The SAA7220 incorporates two Identical finite
impulse response transversal filters with the
x
1
equivalent of 120 taps, one filter for each
SIn) = ;;+1'S(n -1) + ;;+1'S(n + x)
stereo channel. The corresponding 120 coefficients are structured as 4 sections of 30
Where: SIn)
= new sample value
coefficients.
x
- number of successive

f Y Y Y '?I Y

'?I

SAA7220

7-303

An output word is fomned by multiplying 30
samples from the filter RAM with 30 coefficients from the ROM, using a 16 X 12 array
multiplier. The result is added in an accumulator. At the end of the 30 multiplications, the
16 MSBs are passed from the accumulator
via the IOSR to the FDSR, and the accumulator is reset. Overflow protection is incorporated so that the output always limits cleanly in
the event of accumulator overflow. Also, to
simplify the design of the digital-to-analog
converter, a DC offset of + 5% is added to
the accumulator.

•

Product Specification

Signetlcs Linear Products

Digital Filter for Compact Disc Digital Audio System

SAA7220

Table 1. Composition of the 32-Bit Digital Audio Output Word
BIT NUMBER

DESCRIPTION

1 to 4
5 to 8
9 to 28

Sync
Auxiliary
Audio sample

29
30
31
32

AudiO valid
User data
Channel status
Panty bit

INFORMATION
Not used (always zero)
Bits 9 to 12 not used (always zero)
Bits 13 (LSB) to 28 (MSB) two's complement
Copy of the error flag
Used for subcode data
Indication of control bits and category code
Even parity for all word bits excluding sync pattern

The filtered data is output in the 12S format at
a 5.6448MHz bit rate and a sample rate of
176kHz.

Digital Audio Output
The digital audio output (DOBM; Pin 14)
consists of 32-blt words transmitted in blphase-mark code. That IS, two transitions for
a logiC 1 and one tranSition for a logic o. The
32-blt words are transmitted In blocks of 384
words. Table 1 shows the Information contained in each word.
The sync word is formed by violation of the
biphase rule and therefore does not contain
any data. Its length IS equivalent to 4 data
bits. The three different sync patterns (B, M,
and W) Indicate the follOWing situations:

Table 2. Channel Status Bit Assignment
BIT
NUMBER

DESCRIPTION

1 to 4
5 to 8
9 to 16

SUBCODE PROVIDED

NO SUBCODE PROVIDED

Control

Copy of Q channel

Reserved
Category
code

Always zero
CD category

Bits 1 and 2 zero
Bit 3 Image of SCAB
Bit 4 Image of SDAB
Always zero
General category

Bit 9 logiC 1
Always zero

All bits zero
Always zero

17 to 192

SYNC
SD

SI

so

SI

• Sync B; start of a block of 384 words,
contains left sample (11101000)
• Sync M; word contains left sample, but
is not a block start (11100010)

CIIC ERROR BIT

• Sync W; word contains nght sample
(11100100)
In the SAA7220, sync words are always
preceded by o. Left and right samples are
transmitted alternately. Audio samples are
available for digital audio output after Interpolation, attenuation, and muting, but before
filtering. Data held in the Subcode Output
Shift Register (SOSR) is transmitted via the
user data bit and is asynchronous with the
block rate.

Channel Status
The channel status bit IS the same for both
left and nght words. Therefore, a block of 384
words contains 192 channel status bits as
shown In Table 2.
When there is no subcode, the channel status
Will switch over to the general format. 'No

December 2, 1986

~------------75~ ------------~

Figure 3. Subcode Data Format for SYNC and CRC BitB
subcode' IS identified by the subcode detector when SCAB is a continuous High or Low.
If a subcode clock is provided, but there is no
subcode data (SDAB IS a continuous High or
Low), the control bits Will be zero and the
category code will be CD.
The SYNC bit and the cyclic redundancy
check bit (CRG) in the subcode data from the
A-Chip to the B-chip have the format shown
by Figure 3. Typical subcode data output
waveforms are shown by Figure 6.

7-304

SYNC is active Low and indicates the start of
a subcode block, which contains 98 words
Including 2 sync words, SO and SI. CRC is
always Low except during SYNC SI when:
• CRC = logic 1; prevIous Q block was
true
• CRC = logic 0; previous Q block was
false
Two 32-bit words are transmitted at the
sample frequency of 44.1 kHz
(2 X 32 X 44.1kHz = 2.8224Mbits/s data
rate). An Internal 5.6448MHz clock (XSYS/2)
is used in the biphase modulator.

Signetics Unear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

TIMING CHARACTERISTICS
LIMITS
SYMBOL
fXTAl

UNIT

PARAMETER
Operating frequency (XTAL)

Min

Typ

Max

10.16

11.2896

12.42

MHz

Inputs (see Figure 9)
SCAB, CLAB6
SCAB clock frequency (burst clock)

2.8224

MHz

fCLAB
fCLAB

CLAB clock frequency7

2.8224
1.4112

MHz
MHz

leKl

Clock Low time

110

leKH

Clock High time

110

IR

Input rise time

20

ns

tF

Input fall time

20

ns

fSCAB

ns
ns

DAAB, WSAB, EFAB8

!SU. tOAT

Data setup time

40

tHO. tOAT

Data hold time

0

tR

Input rise time

20

ns

tF

Input fall time

20

ns

ns
ns

SDAB9
!su. !sOAT

Subcode data setup time

40

tHO. !sOAT

Subcode data hold time

0

tR

Input rise time

20

ns

tF

Input fall time

20

ns

ns
ns

Outputs (see Figure 10)
WSBD6, 10
tsu. tws

Word select setup time

40

ns

tHO. tws

Word select hold time

0

ns

WSBD6
tR

Output rise time

20

ns

tF

Output fall time

20

ns

DABD6• 1O

!SU. tOATD

Data setup time

40

ns

tHO. IoATD

Data hold time

0

ns

DABD6

IR

Output rise time

20

ns

IF

Output fall time

20

ns

197

ns

CLBD6• 1O
leK

Clock period

161

leKl

Clock Low time

65

ns

leKH·

Clock High time

65

ns

!SU. lelO

Clock setup time

40

ns

!Ho.

Clock hold time

0

ns

leLD

December 2. 1986

7-305

177

•

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

TIMING CHARACTERISTICS (Continued)
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

CLB0 6
tR

Output nse time

20

ns

tF

Output fall time

20

ns

OAB0 6,11
tsu, DATBD

Data setup time

40

ns

tHD, DATBD
WSB06,11

Data hold time

60

ns

tsu, DATWSD

Word select setup time

40

ns

tHD, DATWSD

Word select hold time

60

ns

OOBM 12
tR

Output nse time

20

ns

tF

Output fall time

20

ns

tHIGH(O)
tLOW(O)

Data Bit 0
pulse width High
pulse width Low

354
354

ns
ns

tHIGH(I)
tLOW(I)

Data Bit 1
pulse width High
pulse width Low

177
177

ns
ns

XSYS
tR

Output nse time6

20

ns

tF

Output fall tlme6

20

ns

tHIGH

Output High time at 2V
(relative to clock period)

65

%

35

NOTES:
1 Inputs EFAB and SDAB bolh have Internal pull-downs.
2 Inputs CLAB, SCAB, ATSB, and MUSB have Internal pull-ups,
3 The mmlmum peak-ta-peak voltage can be reduced to 2V If the output XSYS IS not being used Similarly, VIH can be reduced to 2.4V (min.). All other levels remain

the same
4. Reference !evels = 10% and 90%.
5. The output current conditions are dependent on the drive condItions When a crystal oscillator is being used, the output current capability IS IOl = + 1.6mA;
IOH = -0 2mA. But If a slave mput IS being used, the output currents are reduced to IOL = +0 2mA, IOH = -O.2mA.
6 Reference levels = C.SV and 2 av.
7 The signal CLAB can run at either 2 SMHz (1,14 system clock) or 1.4MHz (1,18 system clock) under typical conditions It does not have a minimum or maximum
frequency, but IS limited to being 1,14 or 1,18 of the system clock frequency.
B, Input setup and hold times measured with respect to clock Input from A-chip (CLAB) Reference levels ~ O.BV and 2.0V
9 Input setup and hold times measured with respect to subcode burst clock Input from A-chip (SCAB). Reference levels ~ 0 BV and 2.0V.
10 Output setup and hold times measured with respect to system clock output (XSYS).
11. Output setup and hold times measured with respect to clock output (CLBD)
12 Output nse and fall times measured between the 10% and 90% levels; the data bit pulse Width measured at the 50% level

December 2, 1986.

7-306

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

RIGHT SAMPLE

LEFT SAMPLE

E)O(

DAAB

I

¥
'\

EFAB

==¥ II

LEFT ERROR FLAG

RIGHT ERROR FLAG

I

WSAB

)I

I

I

I

_-u--Lru-

I
CLAB

I·

·1

11.34,.0

28224 MHz

a. Typical Sample Data Input Waveforms From A-Chip (2.8MHz)
LEFT SAMPLE
DAAB

I
I

I

I

I

~
EFAB ---A

~
A

LEFT ERROR FLAG

I------------------------------------------JI~_____
I

I

~I-------

I

I
WSAB!
I

I

~

: 1.41MHz

CLAB

I~.~--------------------11~~------------------~
b. Typical Sample Data Input Waveforms From A-Chip (1.4MHz)
Figure 4

LEFT SAMPLE

RIGHT SAMPLE

DABD

I

I

I
I
I

I

WSBD\

I~------------------------------------~

I
I

L
I

56448 MHz

I
I

CLBO

1-1·-----2.830·-----·II_. ------2.83~----__t
Figure 5. Typical Sample Data Output Waveforms to DAC

December 2, 1986

7-307

•

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

8USCODING ERROR FLAG
(NOT USED SAA7220)

SDAB

SYNC (ACTIVE LOW)

NIT

SCAB

2.8224 MHz BURST CLOCK

NOTE:
7.35kHZ

&bcode word frequency -

Figure 6. Typical Subcode Data Input Waveforms

14 DDBM

11.2l18li MHz

0.1"F
10
318

'M
75

9\

'-----.....;'''1't--- X,.

TOLERANCE OF RESISTORS· '1'0
TO......

Figure 7. Crystal OllClllator Circuit

Figure •• Digital Audio Output Load

}___r

-I--_~,

CLAII---I
....

~

~

1

-

-

-

~

-

QU8--------~J~----------------~Lr--------------------~~----------------~lr--------------------~r---------DATA
VALID
DATA_
VALID_-..1
_
_
_ _J
' - _ _ _ _J '- _ _
_ _ _ _J '-_ __

WSAII
_

WFIII230S

NDTES:
1. Reference levels-O.8V and 20V.
2. AppfJcab!e to subcode data Input (tau. TSDAT and tHD. tSOAT)'

December 2, 1986

Figure 9. Data Input Timings

7-308

Product Specification

Signetics Linear Products

Digital Filter for Compact Disc Digital Audio System

SAA7220

XSYS

WS80

CLBO

i----tCKL----J
'SU"DATD

t=

--------------~X~----------

DABD

Figure 10, Data Output Timings; Reference Levels

16k

= O.BV

and 2.0V

x4

DYNAMIC RAM
X SYS (5 6448 MHz)

2S

LEFT
AUDIO
OUTPUT

37 DAAB 3

38 ClAB 2
39 WSAB 1
SAA7220
(B-CHIP)

SAA7210

(A-CHIP)

36 EFAS

4

34 SCAB 7
35 SCAB 6

14

33

RIGHT
AUDIO
OUTPUT

'---~--:--:-T::'::-T::-r.::28::-T~17:-~11 SWAB/SSM

I

MUTE

SUBCODING
PROCESSOR

'-....,...2-3....,...-22--......,3

MUSS

ATSB

TEST

SERVO

Figure 11. System Application Diagram

December 2, 1986

7-309

•

TDA1541A

Signe1ics

Dual 16-Bit Digital-to-Analog
Converter
Product SpecIfication

Linear Products
DESCRIPTION
The TDA1541A is a monolithic integrated dual l6-bit digital-to-analog converter
(DAC) designed for use in hi-fi digital
audio equipment such as compact disc
players, digital tape, or cassette recorders.

FEATURES
• Selectable input format: offset
binary or two'a complement
• Internal timing and control circuit
• TTL-compatlble digital Inputa
• High maximum Input bit rate and
faat settling time
.6Mblta/a data rate
• Low linearity error (l'2 LSB typ.)
• Fast settling (11018 typ.)

PIN CONFIGURATION
N Packllge

v_

_~I

DATA RI8CK 4

MIL

M DECOUP
DECOUP

DECOUP 7

DECOUP
DECOUP

APPLICATIONS
• Compact disc players
• Digital audio tape, and cassette
recorders and players
• Waveform generation
ORDERING INFORMATION
DESCRIPTION

TEMP£RATURE RANGE

ORDER CODE

-20·C to + 70·C

TDA1541AN

28·Pin Plastic DIP

TOPVIIW

co......

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

+7
-7

Voo
VOOI
VDD2

Supply voltage ranges
Pin 28
Pin 26
Pin 15

-17

V
V
V

TJ

Junction temperature range

-55 to +150

·C

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-40 to +85

·C

VES

Electrostatic handling 1

-1000 to +1000

V

NOTE:
1. Discharging a 2S0pF capacdor thrcugh a lkSl selles reSIstor.

August 1, 1988

7-310

853-1171 94031

Product Specification

Signetics Linear Products

TDA1541A

Dual 16-Bit Digital-to-Analog Converter

BLOCK DIAGRAM
• .2 nF

Uk

Your
lett

YOUT
right

,.

*.~

19

2.
21

(7))

22
23

2.

DATAL!

DATA
BCK

100

LEI
WS
CONTROL

•

TOA1541

TIMING
OATAR'
SCK

Oii/

TWC

-5V

~15,+:,~c-o....h,-_=

-

VOD2

-15V

ADDRESS POINTER

~28!.pVO"'D~'-_+5
27

LE
100
nF

August 1, 1988

7-311

•

Signetics Linear Products

Product Specification

Dual 16-Bit Digital-to-Analog Converter

TDA1541A

DC AND AC ELECTRICAL CHARACTERISTICS voo = +5V; vo0 1 =-5V; V002 =-15V; TA = + 25°C; measured in Figure
1, unless otherwise specified.
LIMITS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

4.5
4.5
14

5.0
5.0
15

5.5
5.5
16

V
V
V

27
37
25

40
50
35

rnA
rnA
rnA

Supply
VOO
-VOOl
-V002

Supply voltage ranges
Pin 28
Pin 26
Pin 15

100
-1001
-1002

Supply currents
Pin 28
Pin 26
Pin 15
Resolution

16

Voltage difference between analog and digital ground

bits

-0.3

+0.3

V

rnA

Inputs
III
IIH

Input current (Pins 1, 2, 3 and 4)
digital inputs LOW « 0.8V)
digital inputs HIGH (> 2.0V)

0.4
20

II os/Twcl
II OB/TWcl
II OB/TWcl

Digital input current (Pin 27)
+5V
OV
-5V

1
20
40

IJA
IJA

fecK
fOAT
fws
flE

Input frequency
at clock input (Pin 2)
at data inputs (Pin 3 and Pin 4)
at word select input (Pin 1)
at latch enable Pin 1

0.4
0.4
200
200

MHz
MHz
kHz
kHz

CI

Input capacitance of digital inputs

12

tJA
tJA

pF

Oscillator
fosc

Oscillator frequency Cose = 470pF

150

200

275

kHz

3.4

4.0

4.6

rnA

25

50

rnA

Analog outputs (AOL; AOR)
Voc

Output voltage compliance

IFS

Full-scale current

± Izs

Zero-scale current

TCFS

Full-scale temperature coefficient
TA = -20 to +85°C

mV

±200 x

10- 6

ppm 1°C

El
El

Linearity error integral
at TA = 25°C
at TA = -20 to +85°C

0.5

1.0
1.0

LSB
LSB

EOl
EOl

Linearity error differential
at TA = 25°C
at TA = -20 to +85°C

0.5

1.0
1.0

LSB
LSB

THD

Total harmonic distortion

SIN

Signal-to-noise ratio + THD2

les

Settling time to ± 1 LSB

August 1, 1988

90

7-312

-100

dB

95

dB

0.5

IJ.S

Product Specification

Signetics Linear Products

TDA1541A

Dual 16-Bit Digital-to-Analog Converter

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) voo = + 5V; voo 1 = -5V; V002 = -15V; TA = + 25°C;
measured in Figure 1, unless otherwise specified.

LIMITS
UNIT

PARAMETER

SYMBOL

Min
a:

Channel separation

L1IFS

Unbalance between outputs

to

Time delay between outputs

SVRR
SVRR
SVRR

Supply voltage ripple rejection 3
VDo=+5V
VOOI = -5V
V002 = -15V

SIN

80

Typ

98

dB

98
0.1

Signal-to-noise ratio
at bipolar zero
at full scale

Max

0.3

dB

0.2

IlS

-76
-84
-58

dB
dB
dB

110
104

dB
dB

Timing (see Figures 2, 3, and 4)
tR

Rise time

32

ns

tF

Fall time

32

ns

Icv

Bit clock cycle time

156

ns

tHB

Bit clock High time

46

ns

tLB

Bit clock Low time

46

ns

tFBRL

Bit clock fall time to latch rise time

0

ns

tRBFL

Bit clock rise time to latch fall time

0

ns

tSOB

Data setup time to bit clock

32

ns

tHoB

Data hold time to bit clock

0

ns

!sos

Data setup time to system clock

32

ns

tHWS

Word select hold time to system clock

0

ns

tsws

Word select setup time to system clock

32

ns

NOTES:
1. To ensure no performance losses, permitted output voltage compliance is ± 25rnV maximum.
2. Signal-to-noise ratio + THO with 1kHz lull-scale sine wave generated at a sampling rate 01 176.4kHz.
3. VRIPPLE = 100mV and IRIPPLE = 100Hz.

FUNCTIONAL DESCRIPTION
The TDA 1541 A accepts input sample formats
in time multiplexed mode or simultaneous
mode with any bit length. The most significant
bit (MSB) must always be first. This flexible
input data format allows easy interfacing with
signal processing chips such as interpolation
filters. error correction circuits, pulse code
modulation adaptors and audio signal processors (ASP).
The high maximum input bit rate and fast
settling time facilitates application in 4 X oversampling systems (44.1kHz to 176.4kHz or
48kHz to 192kHz) with the associated simple

August 1, 1988

analog filtering function (low-order, linear
phase filter).

Input Data Selection
(See also Table 1)
With input OB/TWC connected to ground,
data input (offset binary format) must be in
time multiplexed mode. It is accompanied
with a word select (WS) and a bit clock input
(BCK) Signal. A separate system clock input
(SCK) is provided for accurate, jitter-free
timing of the analog outputs AOL and AOA.

With OS/TWC connected to Voo, the mode is
the same, but data format must be in two's
complement.

7-313

When input OB/TWC is connected to (V001 )
the two channels of data (LlR) are input
simultaneously via (DATA L) and (DATA R),
accompanied by BCK and a latch-enable
input (LE). With this mode selected, the data
must be in offset binary.
The format of data input signals is shown in
Figures 2, 3, and 4.
True 16-bit performance is achieved by each
channel using three 2-bit active dividers, operating on the dynamic element matching
principle, in combination with a 10-bit passive
current-divider, based on emitter scaling. All
digital inputs are TTL-compatible.

•

Product Specification

Signetics Linear Products

TDA1541A

Dual 16-Bit Digital-to-Analog Converter

Table 1. Input Data Selection
OB/TWC

Where
LE

WS
BCK

DATA L
DATA R
DATA OB
DATA TWC
MUX OB
MUX TWC

PIN 1

MODE

-5V
OV
+5V

LE
WS
WS

Simultaneous
Time MUX OB
Time MUX TWC

PIN 2
BCK
BCK
BCK

PIN 3
DATA L
DATA OB
DATA TWC

Latch enable

Word select
Bit clock
Data left
Data right
Data offset binary
Data two's complement
Multiplexed offset binary
Multiplexed two's complement

ws
BCK

DATA

Figure 1. Format of Input Signals; Time Multiplexed at fSCK

=f

CK (1 2S Format)

Figure 2. Format of Input Signals; Simultaneous Data

August 1, 1988

7·314

PIN 4
DATA R
NOT USED
NOT USED

Signetics

Section 8
Speech/Audio Synthesis

Linear Products

INDEX
OM8210
PCF8200
SAA1099

Speech Encoding and Editmg System.....................................
CMOS Male/Female Speech Synthesizer.................................
Stereo Sound Generator for Sound Effects and
Music Synthesis.................................................................

8·3
8·6
8·16

OM8210

Signetics

Speech Encoding And Editing
System
Product Specification

Linear Products
DESCRIPTION
The OM8210 is a speech encoding and
editing system and is comprised of a
speech adaptor box and associated
software. The software is available for
use with either the Hewlett-Packard
9816S or IBM AT or XT. The OM8210
and the personal computer function together to produce speech coding for the'
PCF8200 Speech Synthesizer Chip. The
system's human engineering is such that
many of the available commands are
single-key operations.

FEATURES
• Input sampling of analog speech
signal
• Speech analysis using formant
algorithms
• Graphic representation of speech
parameters

• On-screen parameter editing
• Conversion of parameters to
PCF8200 synthesizer
• ROM programming
• Parameter storage on floppy disc
• Speech output via PCF8200 voice
synthesizer

HARDWARE DESCRIPTION
The hardware for the OM8210 is contained in a box allowing access to all
interconnections (IEE488, interface
loudspeaker, headphones, tape input,
and ROM socket) from the front panel.
There are four single Eurocards and a
power supply forming the speed adaptor
box. These cards are:
• Analog card
• Synthesizer card

• ROM card
• Control card
Analog Card
On this card, the level of the recorded
audio input signal is adjusted by an
electronic potentiometer. Before the audio is sampled, frequencies higher than
half the sampling frequency are removed by a switched capacitor filter of
the type normally used for codecs. A 12bit analog-to-digital converter (ADC) produces the digital samples that are sent
to the control card. An 8-bit digital-toanalog converter (DAC) on the analog
card allows the sampled speech to be
output. The audio input Signal, the sampled speech and the synthesized
speech are selected by an analog multiplexer, filtered, and adjusted for volume
before reproduction by a loudspeaker.

BLOCK DIAGRAM

ANALOG CARD

QD
LEVEL

0

ANALOG

MUX

~

VOLUME

CONTROL

t

CARD
IEC625
IEEE488

SYNTHESIZER
CARD

28

PROM
PROGRAMMER

CARD

SPEECH ADAPTER BOX

OM821Q

November 21, 1986

8-3

853-0988 86655

Signetics Linear Products

Product Specification

Speech Encoding And Editing System

The use of Integrated electronic potentIometers and codec filters substantially reduces
the number of components reqUIred while
maintaining high performance.

Synthesizer Card
This card accommodates the PCF8200 vOice
synthesIZer chip and peripheral components
to allow voice output.

PROM Programmer Card
This card allows four different types of PROM
(2716, 2732, 2732A and 2764) to be programmed under software control. All the
hardware to generate the programming voltages and the programming waveforms are on
this card.

Control Card
This card performs three functions:
• IEEE488 Interface
• Control sequencer

quency cut-off and the sample rate of the
ADC and the DAC are automatically linked.
The hardware Includes all the necessary
cabl'es, adapter plug, loudspeaker, headphone and power supply.

SOFTWARE DESCRIPTION
The software for this speech coding system
has been developed and arranged for optimum user convenience. There are eight
modes available
Each mode and each command in the mode
is selected by single-key entries. Commands
that can destroy data have to be confirmed
before they are executed. More than 100
commands are available. The modes are as
follows:

'The IEEE interface IS a simple talker/listener
implementation With an HEF4738 CIrCUIt.

Sample Mode - Samples and digitizes the
recorded speech. The amplitude can be
checked and speech segments selected. The
sampled speech IS stored In a memory and
can be displayed or made audible

An FPLA control sequencer provides the
handshake Signals for IEEE Interface and the
chip enable Signals for the rest of the system
(the ADC, DAC, synthesIZer and control CIrCUitS).

Analysis Mode - Generates speech parameters from samples. The analYSIS selects the
VOIced/unvOIced sections, extracts the formants, amplitude, and the pitch, and quantizes the speech parameters.

The filter sampling frequency is generated
With a software-programmable PLL frequency
synthesizer The speech sampling frequency
IS derived from the lilter sampling frequency
by frequency divISion Hence, the filter fre-

Parameter Edit Mode - Speech parameters
are displayed graphically on the VDU and can
be edited to correct errors In the analYSIS,
Improve speech quality by altering contours
or amplitudes, concatenate sounds and optimize data rate by editing the frame duration

• Clock generator

November 21, 1986

8-4

OM8210

Code Mode - Generates PCF8200 code
and permits the arrangement of utterances In
the optimum order of application. ThiS mode
also generates the address map at the head
of the EPROM.
EPROM Mode - Used to program/read
EPROM With data for the code memory. Also
pOSSible IS a blank check, bit check and
verification commands.
File Mode - Stores speech parameters or
codes on diSC. Can also assemble code
speech segment from an already eXisting
library.
Media Mode - For diskette initialization and
making back-up caples.
Option Mode - Allows the system configuration to be read or changed. The software IS
supplied on two diskettes, one labelled
'BOOT' which wakes up the system and also
contains the system library routines The
other diskette labelled 'SPEECH' contains
the speech program, the diSC inltlallzallon and
the file handler programs. The' BOOT' diSC IS
not reqUIred dUring operallon, giving a free
diSC drive With the system for a diskette to
store speech parameter files.

Computer System
The following eqUipment IS required to make
a complete edlling system'
• HP9816S-630 or IBM AT or XT
• Dual floppy diSC drive
• 512k bytes of memory

Signetics Linear Products

Product Specification

Speech Encoding And Editing System

OM8210

SPEECH CODING PROCESS FLOWCHART

EOlT PARAMETERS

NO

•
November 21, 1986

8-5

PCF8200

Signetics

CMOS Male/Female Speech
Synthesizer
Objective Specification

Linear Products
DESCRIPTION

FEATURES

The PCF8200 is a CMOS integrated
circuit for generating good quality
speech from digital code with a programmable bit rate. The circuit is primarily
intended for applications in microprocessor controlled systems, where the
speech code is stored separately.

• Male and female speech with
good quality
• Speech-band from 0 to 5kHz
• Bit rate between 455 bits/second
and 4545 bits/second
• Programmable frame duration
• Programmable speaking speed
• CMOS technology
• Operating temperature range -40
to +S5°C
• Single 5V supply with low power
consumption and power-down
stand-by mode
• Interfaces easily with most
popular microcomputers and
microprocessors through S-bit
parallel bus or 12C bus
• Software readable status word
(parallel bus or 12C bus)
• BUSY-signal and REQN-signal
hardware readable
• Internal low-pass filter and 11-bit
0/ A converter

PIN CONFIGURATION
N Package

m:I

VSs.D
TOPYIEW
COU511S

PIN
NO.

Telecommunications
Video games
Aids for the handicapped
Industrial control equipment
Automotive
Irrigation systems

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

24-Pin Plastic DIP (SOT-lOlA)

-40·C to +85·C

PCF8200PN

December 1988

8-6

DESCRIPTION

VOO_A

POSitive supply voltage for DAe
output stage
OAe reference voltage input
Speech output
Negative supply voltage for DAe
stage
Not connected
For normal operation this pin must
be grounded (Vss)
Oscillator Input
Oscillator output

VREF
OUT
VSS-A

NC
TEST

APPLICATIONS
•
•
•
•
•
•

SYMBOL

OSCI
OSCO
~/PAR

10

REO

11

BUSY

12

Vss-o

13
14
15
16

CE

17

SCUD6

18
19
20
21
22
23
24

D5
D4
D3
D2
D1
DO

R/W

W
SDAlD7

VOD_D

For parallel data bus operation, this
pin IS hard-wired to Voo, or to Vss.
to enable the 12C bus
Status bit mdlcattng request for data
Status IndIcatIng synthesIzer busy
NegatIve supply voltage for dIgItal
cIrcuIts
ChIp-enable Input
Read/write control Input
Wnte Input
J2C bus serial data Input!output
(senal mode) or parallel data Input!
output D7 (parallel mode)
12C bus sertal clock tnput!output
(senal mode) or parallel data Input!
output D6 (parallel mode)

Parallel data Input! outputs

PosItIve supply voltage for dIgItal
CIrCUIts

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

PCF8200

BLOCK DIAGRAM
os

CE
IiIW

13

--

W

07_

FL1BI
DATAatAIN
3

DC/IICL

MULnPUERS
SOURCE

10

IiiQ

GlENERATOR

n

BUSY

osa~__r:~,
08C0

Oo'.j--1____...:....:..J

•

lEST

NC

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Voo

Supply voltage 1

PARAMETER

-03 to 75

V

V,

Input voltage 1

-0.3 to 7.5

V

Vo

Output voltage 1

-03 to 75

V

TA

Operating ambient temperature range

-40 to +85

°C

TSTG

Storage temperature range

-55 to + 125

°C

NOTE:
1 Any pm with respect to V ss

December 1988

8-7

•

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

PCF8200

DC AND AC ELECTRICAL CHARACTERISTICS TA = -45'C to + 85'C; supply voltage (Voo to Vss) = 4.5V to 5.5V with
respect to V55. unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

4.5

5.0

5.5

Supply
Voo

Supply voltage

100

Supply current

10

mA

IOO(SB)

Standby current

200

J,lA

V

Inputs CE, R/W, W, OSCI
VIH

Input voltage High

2.0

Voo

Vil

Input voltage Low

0

0.8

V

IIR

Input leakage current VIN

-10

10

jJ.A

tRF

Rise and fali times 1

50

ns

CI

Input capacitance

7

pF

=0

to 5.5V

V

PARALLEL MODE
Input Characteristics (DO to 07)
VIH

Input voltage High

2.0

Voo

V

Vil

Input voltage Low

0

0.8

V

IIR

Input leakage current (VIN

-10

10

jJ.A

CI

Input capacitance

7

pF

=0

to 5.5V. output off)

Output Characteristics (05 to 07 only)
VOH

Output voltage High (IOH

VOL

Output voltage Low (IOl

= -1 00J,lA)
= 3.2mA)

3.5

Voo

V

0

0.4

V

Cl

Load capacitance

80

pF

tRF

Rise and fali times2

50

ns

SERIAL MODE
Input Characteristics (SOA and SOL)
VIH

Input voltage High

3.0

Voo

V

Vil

Input voltage Low

0

1.5

V

IIR

Input leakage current
(VIN = 0 to 5.5V. output off)

-10

10

J,lA

CI

Input capacitance

10

pF

0.4

V

6.1

MHz

Output Characteristics (SOA only, open-drain)
VOL

Output voltage Low (IOl

= 3mA)

0

OSCILLATOR
fXTAl

Crystal frequency

6

VREF

VREF

Reference voltage

IIR

Input leakage current

December 1988

Voo-l.5

1.9

1.25
5

8-8

V
jJ.A

Objective Specification

Signetics Linear Products

PCF8200

CMOS Male/Female Speech Synthesizer

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

TA = _45°C to + 85°C, supply voltage (VOD to
Vss) = 4.5V to 5.5V with respect to Vss, unless
otherwise specified.
LIMITS

SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Outputs REQ, BUSY
V

VOH

Output voltage High (IOH = 1OOIlA)

35

Voo

VOL

Output voltage Low (IQL = 3.2mA)

0

04

V

CL

Load capacitance

80

pF

tRF

Rise and fail tlmes2

50

ns

OUT
VOUT

Output voltage

134 X VREF

0.66 X VREF

Minimum external load

V

600

n

Timing characteristics 3
tWR

Write enable

200

ns

tDS

Data setup for write

150

ns

tOH

Data hold for write

30

ns

tRO

Read enable

200

tDD

Data delay for read 1

tOF

Data floating for read 1

tcs

Control setup

0

tCH

Control hold

0

tRN

REO new (new byte of the same speech frame)

tRV

REO Valid

tRH

REQ Hold

ns
150

ns

150

ns
ns
ns

3

IlS

ns

0
250

TSD

ns

NOTES:
Levels greater than 2V for a '1' or less than 0 BV for a '0' are reached With a load of one TTL Input and 50pF
Rise and fall times between 0 6V and 2 2V levels
3 Timing reference level IS 1 5V, supply 5V ± 10%, temperature range of _40°C to 85°C

•
December 1988

8-9

Signetlcs Linear Products

Objective Specification

PCF8200

CMOS Male/Female Speech Synthesizer

FUNCTIONAL DESCRIPTION
The synthesizer has been designed for a
vocal tract modelling technique of voice synthesis. An excitation signal is fed to a series
of resonators. Each resonator simulates one
of the formants in the original speech. It is
controlled by two parameters, one for the
resonant frequency and one for the bandwidth. Five formants are needed for male
speech and four for female speech. The
output of this system is defined by the excitation Signal, the amplitude values and the
resonator settings. By periodic updating of all
parameters very high quality speech can be
produced.

OPERATION
Speech characteristics change quite slowly;
therefore, the control parameters for the

speech synthesizer can be adequately updated every few tens of milliseconds with
interpolation during the interval to ensure a
smooth changeover from one parameter value to the next. In the PCF8200 the standardframe duration can be set to 8.8, 10.4, 12.8 or
17.6 milliseconds with the speed option,
speaking speed, in the command register.
The duration of each individual speech frame
is programmable to be 1, 2, 3 or 5 times the
standard frame duration.
The excitation Signal is a random noise
source for unvoiced sounds and a programmable pulse generator for voiced sounds.
Both sources have an amplitude modulator
which is updated 8 times in one speech-frame
by linear interpolation. The pitch is updated
every 1Ja of a standard frame.

The excitation signal is filtered with a five
formant filter for male speech and a four
formant filter for female speech. The formant
filter is a cascade of all second-order sections. The control parameters, formant-frequency and formant-bandwidth, are updated
eight times per speech frame by linear interpolation. A block diagram of the formant
synthesizer is shown in Figure 1.
The filter output is upsampled to 80kHz and
filtered with a digital low-pass filter. Before
the signal is digital to analog converted
(DAC), with an II-bit switched capacitor DAC,
the signal is multiplied with a DAC-amplitude
factor. The use of a digital filter means that no
external audio filtering is required for lowmedium applications and minimal filtering is
required for those applications requiring very
high quality speech.

Table 1. Frame Duration as a Function of Speed-Option
(FS1, FSO) and Frame-Duration (FD1, FDO).
10

01

00

11

FS1, FSO

00

8.8

10.4

12.8

17.6

ms

01

17.6

20.8

25.6

35.2

ms

10

26.4

31.2

38.4

52.8

ms

11

44.0

52.0

64.0

88.0

ms

FD1, FDO

SPEECH

OUT

Figure 1. Block Diagram of Formant Synthesizer

December 1988

8-10

Signetics Linear Products

Objective Specification

PCF8200

CMOS Male/Female Speech Synthesizer

DATA FORMAT
Three types of format are used for data
transfer to the synthesizer.

DAC Amplitude Factor
The DAC amplitude factor is one byte, which
is used to optimize the digital speech signal to
the 11-bit DAC. It is the first byte after a STOP
or a BADSTOP or VDO on. Table 2 indicates
the amplitude factor.

Start Pitch
The second byte after a STOP or BADSTOP,
or VDD on is the start pitch. It is a one-byte
start value for the on-chip pitch-period generator.
The frame data is a five-byte block which
contains the filter and source information.
The frame data bits are organized as shown
in Figure 2.

Table 2_ DAC Amplitude Factor
BYTE

FACTOR

01110000
10110000
00110000
11010000
01010000
10010000
00010000
11100000
01100000
10100000
00100000
11000000
01000000
10000000
00000000
11110000

dB

3.5
10.88
10.24
3.25
9.54
3.0
2.75
8.97
2.5
7.96
2.25
7.04
2.0
6.02
1.75
4.86
1.5
3.52
1.25
1.94
1.0
0.00
-2.50
0.75
0.5
-6.02
-12.04
0.25
0.0
HEX code FO is not allowed as a DAC amplitude

Frame Data
Pitch Increment/decrement value
Amplitude
Frame duration
Frequency of 1st formant
Frequency of 2nd formant
Frequency of 3rd formant
Frequency of 4th formant
Frequency of 5th formant
Bandwidth of 1st formant
Bandwidth of 2nd formant
Bandwidth of 3rd formant
Bandwidth of 4th formant
Bandwidth of 5th formant

5
4
2
5
5
3
3
1
3
3
2
2
2

bits
bits
bits
bits
bits
bits
bits
bit
bits
bits
bits
bits
bits

40 bits = 5 bytes

DO

07

BYTE 0

I

B1

BYTE11

F5

BYTE21

F01

SYTUI

FOO

8YTE41

F1

+

:
I +

F3

~

I

F2

F4

NOTE:
It IS not allowed to set byte 0 to the hexldeclmel value EO.

Figure 2. Format of Frame-Data

December 1988

8-11

82

Objective Specification

Signetics Linear Products

CMOS Male jFemale Speech Synthesizer

CONTROL FORMAT
Command Write

PCF8200

DO

07

BVTEOI~__~____~____~____

A command write consists of two bytes, and It
may occur before a data block. The four bits
which can be written are shown In Figure 3

-L____

FS1

FSO

SPEECH
SPEED

0
0
1
1

0
1
0
1

100%
123%
145%
73%

128ms
10Ams
8.8ms
176ms

-L____

2.
3.

Repeat last frame with amplitude = 0
BUSY=O

Status Read
Three status bits can be read out at any time
without a preceding byte (EO) This IS shown
In Figure 4
REO = 1 No data required
= 0 Synthesizer requesllng new data
BUS¥: 1 Busy (an utterance IS pronounced)
= 0 Idle, REON will set to 1; (the synthesizer IS In STOP or BADSTOP
mode)
STOP

The STOP bit IS the same as the
stop bit written to the synthesizer
during a command write.
STOP = 1, BUSY = 0 (stopped by
the user).
STOP = 0, BUSY = 0 (BADSTOP
because the data was not sent In
time).
After Inilial power-up the status/command
register IS set to the following status'
FSO, FS1 = 0 Standard-frame duration of
12.8ms

M/F

= 0 Male quantlzallon table

STOP

= 1

December 1988

____

~ ~
__

00

~_F_S_1~__F_SO~

DO

07
REO

BUSY

STOP

M/F, Male/Female Option

STOP = 1 stop, repeat last complete frame
with amplitude = 0 (no excltallon
signal)
= 0 If the frame data IS not sent within
the durallon of a half frame, there
will be a BADSTOP'
1. REO = 1, STOP = 0

~

Figure 3. Control Write: First Byte Fixed, Second Byte Control

Figure 4. Status Read

M/F = 0 male quantization table
= 1 female quantlzallon table

STOP

____

BYTE1~1____~____~_S_TO_P~__M_I_F~____

FSO, FS 1 Speed Option
STANDARD
FRAME
DURATION

~

BUSY

= 0 Idle

POWER-UP

REO

= 1 No data reqUired

The synthesizer will be set to power-up on a
parallel-wnte sequence.

INTERFACE PROTOCOL
Data can be written to the synthesizer when
REO = 0, or when REO = 1 and BUSY = O.
Figure 5 shows the Interface protocol of the
synthesizer.
In parallel mode the synthesizer IS activated
by sending the DAC-amplltude factor In serial
mode the DAC-amplltude factor can be sent
as soon as the synthesizer IS powered-up
The 12C transmitter/receiver will then acknowledge. When the request for the pltchbyte occurs, the byte must be provided Within
the duration of a half standard frame. If the
byte is not provided In time, a BADSTOP will
be generated.
Dunng each data write operation, the status
bit REO will be set to '1' Within a frame data
block, It disappears Within a few microseconds, asking for the next byte of that block. If
the bytes of frame data are not provided
Within the tlme-duralion of a half frame, a
BADSTOP will be generated.

12 C ADDRESS
On chip there IS an 12C slave receiver /
transmitter With the address

PAR mode: The Input latches are active so
they can receive the first byte
SER mode: The 12C transmitter/receiver will
not acknowledge until the synthesizer has powered-up. To power
up the synthesizer, a parallel
write sequence (Figure 7) must
be made to the synthesizer by
uSing external logic for the control lines; at least one line must
be toggled, CE, while W = 0 and
R/W = 1.
The syntheSizer can be set to
permanent power-up by hardwired control pins (CE = 0, R/
W= 1, W=O).

POWER-DOWN MODE
When BUSY = 0 the syntheSizer will be set to
power-down In the power-down mode the
status/ command register will be retained.
In power-down mode the clock-oscillator IS
sWitched off. After initial VDD the syntheSizer
IS In power-down mode.

SER/PAR
SER/PAR is hard-Wired to VDD or Vss.

76543210

o0

1 0 0 0 0 R/W

HANDLING
All inputs and outputs are protected against
electrostatic charge under normal handling
conditions.

8-12

Signetics Linear Products

Objective Specification

PCF8200

CMOS Male/Female Speech Synthesizer

Figure 5. Interface Protocol

Timing Diagrams
The control signals CE, R/W and W have
been specified to enable easy interface to

most microprocessors and microcomputers.
For instance, with connection to an MAB8048

microcomputer, the R/W and W Inputs can
be used as the RD and WR strobe inputs.

TYPICAL CONNECTION OF CONTROL SIGNALS
CE' O - - - - - , O R

111=0

W~eI~
II/W~

r

~

December t 988

R/W - - -____\'-_ __

8·13

•

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

PCF8200

CE
CEUSEO
ASST~BE

{

w=o

AIW

RIW

RIW

USED AS {
READ STROBE

eE"o

W

07

-------------+--~
Figure 6. Read Timing

I
CE

CEUSED
ASSTI!f>BE

w=o

RIW

A~~~l~ {R~ _______" "'
CE"'O

w

J'----JJ
00-07

----------~--~.....::::...I..;.-'------

DATA
WRITE

Figure 7. Write Timing

ADDRESS

t-.

11

VOICE
ROM

l)J

DATA

--"

DATA

CE,RIW,W

MICROPROCESSOR

REO
BUSY

OUT

f---'--

PCF8200
SYNTHESIZER

Figure 8. Typical Application Configuration with Parallel Interface

December 1988

8-14

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

ADDRESS

)I

VOICE
ROM

PCF8200

UJ

DATA

A

MICROPROCESSOR

SDA

1'<:

OUT

SCl

t-

PCf'8200
SYNTHESIZ&A

Figure 9. Typical Application Configuration with Series Interface

100 k

56k

OUT

PCF8200
SYNTHESIZER

RL "25 n
Po" 140 mW
(PEAK)

Figure 10. An Example of an Output Configuration

PCF8200

PCF8200

OSC
IN

OSC
IN

OSC
OUT

L1

~D~

CLOCK

L006960S

L006970S

Figure 11. Oscillator Clock Configurations

December 1988

OSC
OUT

8·15

•

Signetics

SAA1099
Stereo Sound Generator for
Sound Effects and Music
Synthesis

linear Products

Product Specification

DESCRIPTION
The SAA 1099 is a monolithic integrated
circUit designed for generation of stereo
sound effects and musIc synthesis.

FEATURES
• Six frequency generatorseight octaves per generator;
256 tones per octave
•
•
•
•
•

PIN CONFIGURATION
N Package
VDD

Two noise generators
Six noise/frequency mixers
Twelve amplitude controllers
Two envelope controllers
Two 6-channel mixers/current
sink analog output stages

• TTL input compatible
• Readily interfaces to 8-bit
microcontroller
• Minimal peripheral components
• Simple output filtering

07
06
OS

04
03
02
01
DO
TOP VIEW
PIN NO. SYMBOL

APPLICATIONS
• Consumer games systems
• Home computers
• Electronic organs
• Arcade games

ORDERING INFORMATION
DESCRIPTION

Write Enable: Actlve·LOW Input
which operates In conjunction
With CS and AO to allow writing
to the Internal registers

CS

Chip Select: Active-LOW Input
to Identify valid WR Inputs to
the chip ThiS Input also
operates In conjunctIOn With

AO

Control! Address select: Input
used In conjunction With \VA
and CS to load data to the
control register (AO = 0) or the
address buffer (AO = 1)
Right channel output: a 7-level
current sink analog output for
the 'nght' component ThiS pin
requires an external load
reSistor

WR and AO to allow wntlng to
the mternal registers

• Toys
• Chimes/alarm clocks

DUTR

TEMPERATURE RANGE

18-Pln Plastic DIP (SOT-102CS)

o to

ORDER CODE

+70'C

SAA1099PN

OUTl

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Voo

Supply voltage (Pin 18)

-03 to +7.5

V

V,
V,

Maximum Input voltage
at Voo = 4.5 to 5.5V

-0.3 to + 75
-0.5 to 7.5

V
V

10

Maximum output current

10

mA

PTOT

Total power dissipation

450

mW

TSTG

Storage temperature range

-65 to +125

'C

TA

Operating ambient temperature range

VES

Electrostatic handling 1

o to

IREF

10-17

+70

-1000 to + 1000

DESCRIPTION

\VA

'C

18

Left channel output: a 7-level
current Sink analog output for
the 'left' component ThiS pin
reqUires an external load
resistor
Reference current supply:
used to bias the current sink
outputs

DTACK

Data Transfer Acknowledge:
open-drain output, Active-lOW
to acknowledge successful data
transfer On completIOn of the
cycle OT ACK IS set to Inactive

ClK

Clock: Input for an externallygenerated clock at a nominal
frequency of BMHz

vss

Ground: OV

00-07

Data: Data bus Input

VDD

Power supply:

+ 5V

tYPical

V

NOTE:
1 EquIValent to discharging a 2S0pF capacItor through a 1kn senes resIstor

November 21, 1986

8-16

853-0989 86656

Signetics linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

BLOCK DIAGRAM
"00

(+5 V

es

'0

DTACK

TVP)

V55

LEFT
OUTPUT

10
01
02

o:Z~
INPUT

{"

03
04
05

D.

07

11

12
13
I.
15

LINE
DRIVERS

•

16
17

TO FREQUENCY AND
NOISE REGISTERS

RIGHT

INTERNAL

eLK

OUTPUT

CLOCKS
(4 MHz)

•
November 21, 1986

8-17

Product Specification

Signetics Linear Products

Stereo Sound Generator for
Sound Effects and Music SyntheSiS

SAA1099

DC ELECTRICAL CHARACTERISTICS Voo = 5V; TA = 0 to 70'C, unless otherwise specified.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

4.5

5.0

5.5

V

55

90

mA

250

400

p.A

Supply
Voo

Supply voltage

100

Supply current

IREF

Reference current 1

100

Inputs
V,H

Input voltage HIGH

2.0

6.0

V

V,L

Input voltage LOW

-0.5

0.8

V

±ILI

Input leakage current

10

p.A

C,

Input capacitance

10

pF

0
-0.3

0.4
6.0
10
150
10

V
V
pF
pF
p.A

90
85

125
120

%
%

Outputs
VOL
V7 _ 9
Ca
CL
-ILO

DTACK (open-drainf
Output voltage LOW at IOL = 3.2mA
Voltage on Pin 7 (OFF state)
Output capacitance (OFF state)
Load capacitance
Output leakage current (OFF state)

Audio outputs (Pins 4 and 5)
10,IREF
106/6 X IREF

With fixed IREFS
One channel on
Six channels on

101/1REF
106/6 X IREF
101
loe

With IREF=250fJA; RL=I.lkn (±5%)
One channel on
Six channels on
Output current one channel on
Output current six channels on

95
90
238
1.38

115
110
288
1.65

%
%
fJA
mA

101
loe

With resistor supplying IREF 4
Output current one channel on
Output current six channels on

155
0.94

270
1.65

p.A
mA

600
10

p.A

RL

Load resistance

-ILO

DC leakage current all channels off

±IOMAX

Maximum current difference between left and nght
current sinks5

SIN

Signal-to-noise rati06

November 21, 1986

n

15
TBD

8-18

%

dB

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis
AC ELECTRICAL CHARACTERISTICS

SAA1099

VDD = 5V; TA = 0 to 70'C; timing measurements taken at 2.0V for a logic 1 and
0.8V for a logic 0, unless otherwise specified (see waveforms Figures 1 and 2)

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Bus interface timing (see Figure 1)
tASC

AO setup time to CS fall

0

ns

tcsw

CS LOW to WR fall

30

ns

tAsw

AO setup time to WR fall

50

ns

tWl

WR LOW time

100

ns

tBSW

Data bus valid to WR nse

100

tDFW

DTACK fall delay from WR fall 7

0

tAHW

AO hold time from WR HIGH

0

ns

tCHW

CS hold time from WR HIGH

0

ns

tDHW

Data bus hold time from WR HIGH

0

tDRW

DTACK nse delay from WR HIGH

0

tCY

Bus cycle timeS

2CP

tCY

Bus cycle tlme g

8CP

ns
85

ns

ns
100

ns

Clock input timing (see Figure 2)
tClK

Clock penod

120

tHIGH

Clock LOW time

55

125

ns

tLOW

Clock HIGH time

55

ns

255

ns

NOTES:
1 USing an external constant current generator to provide a nominal IREF or external resistor connected to VDO
2 This output IS short-circUIt protected to VOD and Vss
3 Measured with IREF a constant value between 100 and 400J,LA, load reSistance (R L) allowed to match E24 (5%) In all applications via

o 27775± 0 03611

RL~------

IREF

4
5
6
7
8
9

Measured with RREF = 10kn (± 5%) connected between IREF and VOD, Rl = 820n (± 5%), aUTR and OUTL short-circuit protected to Vss
Left and fight outputs must be driven with Identical configuration
Sample tested value only
This timing parameter only applies when no walt states are required, otherwise, parameter IS invalid
The minimum bus cycle time of two clock periods IS for loading all registers except the amplitude registers
The mlmmum bus cycle time of eight clock periods IS for loading the amplitude registers In a system uSing DTACK It IS possible to achieve minimum times of
500ns Without DTACK the parameter given must be used

AO

)

I'AHW~

-'AS~'CSW-

r'WL-

tASW

I.

tCHW

f-------t

'ssw

OHW

OO-D7

~tDFW

'DOW

Figure 1. Bus Interface Waveforms
November 21, 1986

8-19

I

•

Product Specification

Signetics Linear Products

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

The following sections provide a detailed
functional description of the SAA 1099 as
shown in the block diagram.

Each mixer channel has one of the frequency
generator outputs fed to it. Three channels
use noise generator 0 and the other three use
noise generator 1.

Frequency Generators

Amplitude Controllers

FUNCTIONAL DESCRIPTION

Six frequency generators can each select one
of 8 octaves and one of 256 tones within an
octave. A total frequency range of 30Hz to
7.74kHz is available. The outputs may also
control nOise or envelope generators. All
frequency generators have an enable bit
which switches them on and off, making it
possible to preselect a tone and to make it
inaudible when required.
The frequency ranges per octave are:
Octave
Frequency range
o
30Hz to 60Hz
1
60Hz to 122Hz
2
122Hz to 244Hz
3
244Hz to 488Hz
4
489Hz to 976Hz
5
978Hz to 1.95kHz
6
1.95kHz to 3.90kHz
7
3.91kHz to 7.81kHz

Noise Generators

Each of the six channel outputs from the
mixer is split up into a right and left component giving effectively twelve amplitude controllers. An amplitude of 16 possible levels is
assigned to each of the twelve Signals. With
this configuration a stereo effect can be
achieved by varying only the amplitude component. The moving of a sound from one
channel to the other requires, per tone, only
one update of the amplitude register contents.
When an envelope generator is used, the
amplitude levels are restricted. The number
of levels available is then reduced to eight.
This is achieved by disabling the least significant bit (LSB) of the amplitude control.

Envelope Controllers
Two of the six tone generators are under
envelope control. This applies to both the left
and right outputs from the tone generator.

The two noise generators both have a programmable output. This may be a software
controlled noise via one of the frequency
controlled generators or one of three predefined nOises. There is no tone produced by
the frequency generator when it is controlling
the noise generator. The noise produced is
based on double the frequency generator
output, i.e., a range of 61Hz to 15.6kHz.ln the
event of a pre-defined noise being chosen,
the output of noise generator 0 can be mixed
with frequency generator 0, 1 and 2; and the
output of noise generator 1 can be mixed with
frequency generator 3, 4, and 5. In order to
produce an equal level of noise and tone
outputs (when both are mixed) the amplitude
of the tone is increased. The three predefined noises are based on a clock frequency of 7.8kHz, 15.6kHz or 31.25kHz.

The envelope has the following eight possible
modes:
• Amplitude is zero

Noise/Frequency Mixers

There is also the capability of controlling the
'right' component of the channel with inverse
of the 'left' component, which remains as
programmed.

There are six noiselfrequency mixers, each
with four selections:
• Channel off
• Frequency only

•
•
•
•
•
•
•

Single attack
Single decay
Single attack-decay (triangular)
Maximum amplitude
Continuous attack
Continuous decay
Continuous attack-decay

The timing of the envelope controllers is
programmable using one of the frequency
generators (see Block Diagram). When the
envelope mode is selected for a channel its
control resolution is halved for that channel
from 16 levels to 8 levels by rounding down to
the nearest even level.

• Noise only
• Noise and frequency

November 21, 1986

8-20

A direct enable permits the start of an envelope to be defined, and also allows termination of an envelope at any time. The envelope
rate may be controlled by a frequency channel (see Block Diagram), or by the microprocessor writing to the address buffer register. If
the frequency channel controlled is OFF
(NE = FE = 0) the envelope will appear at the
output, which provides an alternative 'nonsquare' tone capability. In this event, the
frequency will be the envelope rate which,
provided the rate is from the frequency channel, will be a maximum of 1kHz. Higher
frequencies of up to 2kHz can be obtained by
the envelope resolution being halved from 16
levels to 8 levels. Rates quoted are based on
the input of an 8M Hz clock.

Six-Channel Mixers/Current Sink
Analog Output Stages
Six channels are mixed together by the two
mixers, allowing each one to control one of
six equally weighted current sinks to provide a
seven level analog output.

Command/Control Select
In order to simplify the microprocessor interface, the command and control information is
multiplexed. To select a register in order to
control frequencies, amplitudes, etc" the
command register has to be loaded. The
contents of this register determine to which
register the data is written in the next control
cycle. If a continuous update of the control
register is necessary, only the control information has to be written (the command
information does not change).
If the command/ control select (AO) is logic 0,
the byte transfer is control; if AO is logic 1, the
byte transfer is command.

Interface to Microprocessor
The SAA1099 is a data bus based I/O
peripheral. Depending on the value of the
command/control signal (AO) the CS and WR
signals control the data transfer from the
microprocessor to the SAA 1099. The data
transfer acknowledge (DTACK) indicates that
the data transfer is completed. When, during
the write cycle, the microprocessor recognizes the DTACK, the bus cycle will be
completed by the processor.

Signetlcs Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

h

ClK

'lOW

SAA1099

!
~

'elK

Figure 2. Clock Input Waveform

APPLICATION INFORMATION
Device Operation
The SAA1099 uses pulse-width modulation to
achieve amplitude and envelope levels. The
twelve signals are mixed In an analog format
(6 'left' and 6 'right') before leaving the chip.
The amplitude and envelope Signals chop the
output at a minimum rate of 62.5kHz, compared with the highest tone output of
7.74kHz. Simple external low-pass filtering is
used to remove the high frequency components.
Rates quoted are based on the input of an
8MHz clock.
A data bus-based write only structure is used
to load the on-board registers. The data bus
is used to load the address for a register, and
subsequently the data to that register. Once
the address IS loaded, multiple data loads to
that register can be performed.

The selection of address or data is made by
the single address bit AO, as shown in register
maps Table 1 and Table 2.
The bus control Signals WR and CS are
designed to be compatible With a wide range
of microprocessors. A DTACK output IS included to optimize the interface with an
S68000 series microprocessor. In most bus
cycles DTACK will be returned Immediately.
ThiS applies to all register address load cycles and all except amplitude data load cycles. With respect to amplitude data, a number of wait cycles may need to be performed,
depending on the time since the previous
amplitude load. DTACK will indicate the number of required waits.

Register Description (See
Tables 2 and 3)
The amplitudes are assigned With 'left' and
'right' components in the same byte, on a
channel-by-channel basis. The spare locations that are left between blocks of registers

IS to allow for future expanSion, and should be
written as zeroes. The tone Within an octave
IS defined by eight bits and the octave by
three bits. Note that octaves are paired (0/1.
2/3, etc). The frequency and nOise enables
are grouped together for ease of programming The controls for nOise 'color' (clock
rate) are grouped in one byte.
The envelope registers are positioned in adJacent locations. There are two types of envelope controls: direct acting controls and buffered controls The direct acting controls always take Immediate effect, and are:
• Envelope enable (reset)
• Envelope resolution (16/8 level)
The buffered controls are acted upon only at
the times shown In Figure 3 and control
selection of:
• Envelope clock source
• Waveform type
• Inverted/non-Inverted 'right' component

Table 1. External Memory Map
OATA BUS INPUTS

SELECT
AD

07

06

05

04

03

02

01

DO

0
1

D7
X

D6

D5
X

D4
A4

D3
A3

D2
A2

D1
A1

DO
AO

OPERATIONS

X

Data for internal registers
Internal register address

NOTE:

Where X = don't care state.

•
November 21, 1986

8-21

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 2. Internal Register Map
REGISTER
ADDRESS

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F

DATA BUS INPUTS
OPERATIONS
D7

D6

D5

D4

D3

D2

D1

DO

AR03
1
2
3
4
5

AR02
1
2
3
4
5

AR01
1
2
3
4
5

AROO
1
2
3
4
5

AL03
1
2
3
4
5

AL02
1
2
3
4
5

AL01
1
2
3
4
5

ALOO
1
2
3
4
5

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

F07
1
2
3
4
F57

F06
1
2
3
4
F56

F05
1
2
3
4
F55

F04
1
2
3
4
F54

F03
1
2
3
4
F53

F02
1
2
3
4
F52

F01
1
2
3
4
F51

FOO
1
2
3
4
F50

X
X
X
X
X
X
X
X
X

X
X

X
X

X
X

X
X

X
X

X
X

012
032
052

011
031
051

010
030
050

002
022
042

001
021
041

000
020
040

X
X
X
X

X

X

X
X
X
X
X
X

FE5
NE5
N11

FE4
NE4
N10

X
E07
E17

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

X

X

X

FE3
NE3

FE2
NE2

X

X

FE1
NE1
N01

FEO
NEO
NOO

X

X

X

X

X

X

E05
E15

E04
E14

E03
E13

E02
E12

E01
E11

EOO
E10

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
SE

Amplitude
Amplitude
Amplitude
Amplitude
Amplitude
Amplitude

0
1
2
3
4
5

right channel; left channel
right/left
right/left
right/left
right/left
right/left

Frequency
Frequency
Frequency
Frequency
Frequency
Frequency

of
of
of
of
of
of

8-22

0
1
2
3
4
5

Oclave 1; octave 0
Octave 3; octave 2
Octave 5; octave 4
Frequency enable
Noise enable
Noise generator 1;
Noise generator 0
Envelope generator 0
Envelope generator 1

Sound enable (all channels)

X
X
X

NOTE:
Where:
All don't cares (X) should be wntten as zeroes.
00 to 1F block 01 regosters repeats eoght times on the block between addresses 00 to FF (lull internal memory map).

November 21, 1986

tone
tone
tone
tone
tone
tone

Signetics linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 3. Register Description
BIT

DESCRIPTION

ARn3; ARn2;
ARn1; ARnO
(n = 0.5)

4 bits for amplitude control
of right channel
o 0 0 0 mInimum amplitude (off)
1 1 1 1 maximum amplitude

ALn3; ALn2;
ALn1, ALnO
(n = 0.5)

4 bIts
of left
o0 0
1 1 1

for amplitude control
channel
0 mInimum amplitude (off)
1 maxImum amplitude

Fn7 to FnO
(n = 0.5)

8 bIts
of the
o0 0
1 1 1

for frequency control
SIX frequency generators
0 0 0 0 0 lowest frequency
1 1 1 1 1 hIghest frequency

On2; On1;
OnO
(n = 0.5)

3 bits for octave control

FEn
(n = 0.5)

Frequency enable bit (one tone per generator)
FEn = 0 indIcates that frequency 'n' IS off

NEn
(n = 0.5)

NOIse enable bit (one tone per generator)
NEn = 0 Indicates that noise 'n' is off

Nn1; NnO
(n = 0.1)

2 bIts for noise generator control.
These bits select the noise generator rate (noIse 'color')
Nn1 NnO Clock frequency (kHz)
0
0
31.3
0
1
15.6
1
0
7.6
61 to 15.6 (frequency generator 0/2)
1
1

000 lowest octave
00 1
o1 0
o1 1
o1 1
1 0 0
10 1
1 1 0
1 1 1 hIghest octave

(30Hz to 60Hz)
(60Hz to 122Hz)
(122Hz to 244Hz)
(244Hz to 488Hz)
(244Hz to 488Hz)
(489Hz to 976Hz)
(978Hz to 1.95kHz)
(1.95kHz to 3.90kHz)
(3.91 kHz to 7.81 kHz)

•
November 21, 1986

8-23

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 3. Register Description (Continued)
BIT

En7;
En5 to EnO
(n=0.1)

SE

DESCRIPTION

7 bits for envelope control
EnO
o Left and right component have the same envelope
1 Right component has inverse of envelope that IS applied to
left component
En3 En2 En2
0
0
0
Zero amplitude
0
0
Maximum amplitude
1
1
Single decay
0
0
0
1
1
Repetitive decay
1
0
0
Single triangular
1
0
1
Repetitive triangular
1
1
Single attack
0
Repetitive attack
1
1
1
En4
0 4 bits for envelope control (maximum frequency = 976Hz)
1 3 bits for envelope control (maximum frequency = 1.95kHz)
En5
0 Internal envelope clock (frequency generator 1 or 4)
1 External envelope clock (address write pulse)
En7
0 Reset (no envelope control)
1 Envelope control enable
SE sound enable for all channels
(reset on power-up to 0)
0 All channels disabled
1 All channels enabled

NOTE:
All rates gIven are based on the Input of an 8MHz clock

November 21, 1986

8-24

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

ENVELOPE
GENeRATOR INACTIVE
(EN? =0)
EN3

EN2

o

0

EN1

SAA1099

ENVELOPE

GENERATOR ACTIVE
(EN7=1)

ENG

A

B

c

D

G

H

•

NOTES:

1 The level at thiS time IS under amplitude control only (En7 "" D, no envelope)
2 When the generator IS acbve (En7 = 1) the rn8X1mum level possible IS 1ft16 of the amplitude level, rounded down to the nearest eight When the generator IS inactIVe (En"" 0) the level
Will be 11716 of the amplitude level

3 After posrtlon (3) the buffered controls Will be acted upon when loaded
4 At pOSItion (4) the buffered controls Will be acted upon If already loaded
5 Waveforms 'a' to 'h' show the left channel (EnD - 0, left and right components have the same envelope)
Waveform ',' shows the right channel (Ena,., 1, nght component lOverse of envelope apphed to left)

Figure 3. Envelope Waveforms

November 21, 1986

8-25

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Voo
CLOCK

GENERATOR

RREF

RL

Rl
OUTPUT

,

FILTERS

elK (8 MHz)

1

18

6

/

50UTl

8

I

WR1

LOS
DTACK

OUTPUT

OUTPUT

r Jh

ADDRESS
DECODER

~

[> r-

40UTR

J

1

t

Figure 4. Typical Application Circuit Diagram

November 21, 1986

LEFT CHANNEL

SAA1099

10~17

ADDRESS

[>

7

00-07
CPU

OUTPUT
AMPLIFIER

8-26

±

I

'---

RIGHT CHANNEL
OUTPUT

Signetics

Section 9
Packaging Information

Linear Products

INDEX
Substrate Design Guidelines for Surface Mounted Devices... ....................... ....
Test and Repair... ... . . .. .. .. . . .. .. .. . . . .. . . . . .. " .. .. . . . .. . . . . . . . . . . . . .. . . . .. . . ... ...........
Fluxing and Cleaning............................. ..................... ........................
Thermal Considerations for Surface-Mounted Devices.. .... ............. ........ .....
Package Outlines for Prefixes ADC. AM, AU, CA, DAC, leM, LF, LM, MC,
NE, SA, SE, SG, pA and UC........................................... ........ ....... ......
Package Outlines for Prefixes HEF, OM, PCF, PNA, SM, TDA,
TDD and TEA........................................................ .... ............

9-3
9-14
9-17
9-22
9-35
9-51

•

Signetics

Substrate DeSign Guidelines for
Surface-Mounted Devices

Linear Products

INTRODUCTION
SMD technology embodies a totally new automated circuit assembly process using a
new generation of electronic components:
surface-mounted devices (SMDs). Smaller
than conventional components, SMDs are
placed onto the surface of the substrate, not
through it like leaded components. And from
this, the fundamental difference between
SMD assembly and conventional throughhole component assembly arises; SMD component positioning is relative, not absolute.
When a through-hole (leaded) component is
inserted into a PCB, either the leads go
through the holes, or they don't. An SMD,
however, is placed onto the substrate surface, its position only relative to the solderlands, and placement accuracy is therefore
influenced by variations in the substrate track
pattern, component size, and placement machine accuracy.
Other factors influence the layout of SMD
substrates. For example, will the board be a
mixed-print (a combination of through-hole
components and SMDs) or an all-SMD design? Will SMDs be on one side of the
substrate or both? And there are process
considerations, such as: what type of machine will place the components and how will
they be soldered?
Using our expertise in the world of SMD
technology, this section draws upon applied
research in the area of substrate design and
manufacture, and presents the basic guidelines to assist the deSigner In making the
transition from conventional through-hole
PCB assembly to SMD substrate manufacture.

Designing With SMD
SMD technology is penetrating rapidly into all
areas of modern electronic equipment manufacture - in professional, industrial, and consumer applications. Boards are made with
conventional print-and-etch PCBs, multilayer
boards with thick film ceramic substrates, and
with a host of new materials specially developed for SMD assembly.
However, before substrate layout can be
attempted, footprints for all components must
be defined. Such a footprint will include the
combination of patterns for the copper solderlands, the solder resist, and, possibly, the
solder paste. So the design of a substrate
breaks down into two distinct areas: the SMD
footprint definition, and the layout and track
routing for SMDs on the substrate.
February 1987

Each of these areas is treated individually;
first, the general aspects of SMD technology,
including substrate configurations, placement
machines, and soldering techniques, are diScussed.

Substrate Configurations
SM D substrate assembly configurations are
classified as:
Type I - Total surface mount (all-SMD);
substrates with no through-hole components
at all. SMDs of all types (SM integrated
circuits, discrete semiconductors, and passive devices) can be mounted either on one
Side, or both sides, of the substrate. See
Figure la.

a. Type I - Total Surface-Mount
(all-SMD) Substrates

Type IIA - Double-sided mixed-print; substrates with both through-hole components
and SMDs of all types on the top, and smaller
SMDs (transistors and passives) on the bottom. See Figure 1b.
Type liB - Underside attachment mlxedprint; the top of the substrate is dedicated
exclusively to through-hole components, with
smaller SMDs (transistor and passives) on
the bottom. See Figure 1c.
Although the all-SMD substrate will ultimately
be the cheapest and smallest variation as
there are no through-hole components, it's
the mixed-print substrate that many manufacturers will be looking to in the immediate
future, for this technique enjoys most of the
advantages of SMD assembly and overcomes the problem of non-availability of
some components in surface-mounted form.
The underside attachment variation of the
mixed-print (type liB - which can be thought
of as a conventional through-hole assembly
with SMDs on the solder side) has the added
advantages of only requiring a single-sided,
print-and-etch PCB and of using the established wave soldering technique. The all-SMD
and mixed-print assembly with SMDs on both
sides require reflow or combination wave!
reflow soldering, and, in most cases, a double-sided or multilayer substrate.
The relatively small size of most SMD assemblies compared with equivalent through-hole
designs means that circuits can often be
repeated several times on a single substrate.
This multiple-circuit substrate technique
(shown in Figure 2) further increases production efficiency.

9-3

b. Type IIA - Mixed-Print
(Double-Sided) Substrate

c. Type liB - Mixed-Print (Underside
Attachment) Substrate
Figure 1

+

lr.=.Y.=.,;u='.=.CU

0··0
··0 ·-0
•• ~"~II~
[?_=_~-=~.=i={]

0·-0
.. i II ·-0
i .. ·-0
i

Q:;;=8=6=~~
DF07100s

Figure 2. Multiple-Circuit Substrate

Mixed Prints
The possibility of using a partitioned design
should be investigated when considering the
mixed·print substrate option. For this, part of
the circuit would be an all-SMD substrate, and
the remainder a conventional through-hole

•

Signetlcs Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

PCB or mlxed-pnnt substrate. This allows the
circuit to be broken down Into, for example,
high and low power sections, or high and low
frequency sections.

Automated SMD Placement
Machines
The selection of automated SMO placement
machines for manufactunng requirements IS
an Issue reaching far beyond the scope of
this section. However, as a gUide, the four
main placement techniques are outlined.
They are'
In-Line Placement - a system with a senes
of dedicated plck-and-place Units, each placIng a single SMO in a preset position on the
substrate. Generally used for small circuits
With few components. See Figure 3a.

OF."'.,
a, In-line Placement

b. Sequential Placement

Sequential Placement - a single plck-andplace unit sequentially places SMOs onto the
substrate. The substrate is posilioned below
the plck-and-place Unit uSing a computercontrolled X-V moving table (a "software
programmable" machine). See Figure 3b.
Simultaneous Placement - places all
SMOs in a Single operation. A placement
module (or station), with a number of pickand-place units, takes an array of SM Os from
the packaging medium and simultaneously
places them on the substrate. The pick and
place Units are guided to their substrate
location by a program plate (a "hardware
programmable" machine), or by softwarecontrolled x-V movement of substrate and/or
plck-and-place Units. See Figure 3c.
Sequential/Simultaneous Placement - a
complete array of SMOs IS transferred in a
single operation, but the plck-and-place units
Within each placement module can place all
devices simultaneously, or indiVidually (sequentially). Posilioning of the SMOs is software-controlled by moving the substrate on
an X-V moving table, by X-V movement of the
plck-and-place Units, or by a combination of
both. See Figure 3d.
All four techniques, although differing in detail, use the same two basIc steps: picking the
SMO from the packaging medium (tape, magazine, or hopper) and plaCing It on the substrate. In all cases, the exact location of each
SMO must be programmed Into the automated placement machine.

Soldering Techniques
The SMO-populated substrate IS soldered by
conventional wave soldenng, reflow solderIng, or a combination of both wave and reflow
soldenng. These techniques are covered at
length in another publication entitled SMD
Soldenng Techniques, but, briefly, they can
be described as follows:
Wave Soldering - the conventional method
of soldering through-hole component assemFebruary 1987

c. Simultaneous Placement

d. Sequential/Simultaneous Placement
Figure 3

blies where the substrate passes over a wave
(or more often, two waves) of molten solder.
This technique is favored for mixed-print assemblies with through-hole components on
the top of the substrate, and SMOs on the
bottom.
Reflow Soldering - a technique onglnally
developed for thick-film hybrid circuits uSing a
solder paste or cream (a suspension of fine
solder particles in a sticky resin-flux base)
applied to the substrate which, after component placement, is heated and causes the
solder to melt and coalesce. This method is
predominantly used for Type I (all-SMO) assemblies.
Combination Wave/Reflow Soldering - a
sequential process uSing both the foregOing
techniques to overcome the problems of
soldering a double-sided mixed-print substrate With SMOs and through-hole components on the top, and SMOs only on the
bottom. (Type liB).

Footprint Definition
An SMO footprint, as shown In Figure 4,
consists of:
• A pattern for the (copper) solderlands
• A pattem for the solder resist

9-4

• If applicable, a pattern for the solder

cream.
The deSign for the footprint can be represented as a set of nominal coordinates and
dimensions. In practice, the actual coordinates of each pattern will be distributed
around these nominal values due to positioning and processing tolerances. Therefore, the
coordinates are stochastic; the actual values
form a probability distribution, with a mean
value (the nominal value) and a standard
deViation.
The coordinates of the SMO are also stochastic. ThiS is due to the tolerances of the
actual component dimensions and the posiIIonal errors of the automated placement
machine.
The relative positions of solderland, solder
resist pattern, and SMO, are not arbitrary. A
number of requirements may be formulated
concerning clearances and overlaps. These
include:
• limiting factors in the production of the
patterns (for example, the spacing
between solderlands or tracks has a
minimum value)

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

• Maximizes the number of tracks
between adjacent solderlands.
The final SMO footprint design also depends
on the soldering process to be used. The
requirements for a wave-soldered substrate
differ from those for a reflow-soldered substrate, so each IS discussed Individually.

Footprints for Wave Soldering
To determine the footprint of an SMO for a
wave-soldered substrate, conSider four main
Interactrve factors:
• The component dimensions plus
tolerances - determined by the
component manufacturer
• The substrate metallization - positional
tolerance of the solderland with respect
to a reference point on the substrate

Figure 4. Component Lead, Solder
Land, Solder Resist, and Solder
Cream "Footprint"
• Requirements concerning the soldering
process (for example, the solderlands
must be free of solder resist)
• Requirements concerning the quality of
the solder joint (for example, the
solderland must protrude from the SMO
metallization to allow an appropriate
solder meniscus)
Mathematical elaboration of these requirements and substitution of values for all tolerances and other parameters lead to a set of
inequalities that have to be solved simultaneously. To do this manually uSing worstcase design is not considered realistic. A
better approach is to use a statistical analysis; although thiS requires a complex computer program, it can be done.
Such an approach may deliver more than one
solution, and, if thiS is so, then the optimal
solution must be determined. Optimization IS
achieved by setting the following objectivefind the solution that:
• Minimizes the area occupied by the
footprint

c:::::::::::{:>

• The solder resist - positional tolerance
of the solder resist pattern with respect
to the same reference point
• The placement tolerance - the ability of
an automated placement machine to
accurately pOSition the SMO on the
substrate.
The coordinates of patterns and SMOs have
to meet a number of requirements. Some of
these have a general validity (the minimum
overlap of SMO metallization and solderland)
and available space for solder meniscus.
Others are specifically reqUired to allow successful wave soldering. One has to take Into
account factors like the "shadow effect"
(missing of joints due to high component
bodies), the nsk of solder bridging, and the
available space for a dot of adheSive.

The "Shadow Effect"
In wave soldenng, the way in which the
substrate addresses the wave is important.
Unlike wave soldering of conventional printed
boards where there are no component bodies
to restrict the wave's freedom to traverse
across the whole surface, wave soldenng of
SMO substrates IS inhibited by the presence
of SMOs on the solder-Side of the board. The
solder is forced around and over the SMOs as
shown In Figure 5a, and the surface tension
EXTENDED

of the molten solder prevents its reaching the
far end of the component, resulting in a dryJOint downstream of the solder flow. This is
known as the "shadow effect."
The shadow effect becomes critical with high
component bodies. However, wetting of the
solderlands during wave soldering can be
Improved by enlarging each land as shown in
Figure 5b. The extended substrate metallization makes contact with the solder and allows
it to flow back and around the component
metallization to form the joint.
The use of the dual-wave soldering technique
also partially alleviates thiS problem because
the first, turbulent wave has sufficient upward
pressure to force solder onto the component
metallization, and the second, smooth wave
"washes" the substrate to form good fillets of
solder. Similarly, 011 on the surface of the
solder wave lowers the surface tension,
(which lessens the shadow effect), but this
technique introduces problems of contaminants in the solder when the oil decomposes.

Footprint Orientation
The orientation of SO (small outline) and VSO
(very small outline) les is critical on wavesoldered substrates for the prevention of
solder bndge formation. Optimum solder penetration is achieved when the central axis of
the Ie is parallel to the flow of solder as
shown in Figure 6a. The SO package may
also be transversely oriented, as shown in
Figure 6b, but this is totally unacceptable for
the VSO package.

Solder Thieves
Even with parallel mounted SO and VSO
packages, solder bridges have a tendency to
form on the leads downstream of the solder
flow. The use of solder thieves (small squares
of substrate metallization), shown in Figure 7
for a 40-pin VSO, further reduces the likelihood of solder-bridge formation.

~

SUBSTRATE

OO"~U'w

SUBSTRATE

?~~~
~

a. Surface Tension Can Prevent the Molten Solder
From Reaching the Downstream End of the SMD,
Known as the "Shadow Effect"

b. Extending the Solder Lands to Overcome the
Shadow Effect
Figure 5

February 1987

SOLDER FLOW

9-5

•

Signetics Unear Products

Substrate Design Guidelines for Surface-Mounted Devices

For bonding small outline (SO) les to the
substrate, two dots of adhesive are sufficient
for SO-8, -14, and -16 packages, but the SOL20, -24, -28, and VS0-40 packages need
three dots. The through-tracks (or dummy
tracks) must be positioned beneath the IC
accordingly to support the adhesive dots.

q
FLOW
t~~:;~~~:;~~;;:;j DIRECTION

FLOW

DIRECTION

.d

"r

~

jM:TALUZATION

~

..\

~~;;;+~LANO
C

a. Parallel Orientation for SO
and VSO Packages

b. Transverse Orientation for
SO Packages Only

----=-+-

DIRECTION

{r:

2ID

l\ .000~~~ND.
SOLDER THIEF

--j'1Figure 7. Example of Solder Thieves
for V50-40 Footprints (Dims In mm)

.",c

Figure 8. Misaligned Placement of SO
Package Increases the Possibility of
Solder Bridging

Placement Inaccuracy
Another major cause of solder bridges on SO
ICs and plastic leaded chip carriers (PLCCs)
is a slight misalignment as shown in Figure 8.
The close spacing of the leads on these
devices means that any inaccuracy in place·
ment drastically reduces the space between

February 1987

SUBSTRATE

NOTES:
A "" Substrate metallization height
B :: SMD metallization height
C = Height of adhesive dot

Figure 6

SUBSTRATE5

>A+ B

adjacent pins and solderlands, thus increas·
Ing the chance of solder bridges forming.

Dummy Tracks for Adhesive
Application
For wave soldertng, an adheSive to affiX
components to the substrate is reqUired. This
is necessary to hold the SMDs in place
between the placement operation and the
soldering process (this techntque IS covered
at length In another publication entitled Adhe·
sive Application and Curing).
The amount of adheSive applied IS crttlcal for
two reasons: first, the adhesive dot must be
high enough to reach the SMD, and, second,
there mustn't be too much adheSive which
could foul the solderland and prevent the
formation of a solder jOint. The three parame·
ters governing the height of the adhesive dot
are shown In Figure 9. Although thiS diagram
illustrates that the mlntmum requirement IS
C > A + B, In practice, C > 2(A + B) is more
realistic for the formation of a good strong
bond.
Taking these parameters in turn, the sub·
strate metallization height (A) can range from
about 35jlm for a normal prtnt·and·etch PCB
to 135jlm for a plated through·hole board.
And the component metallization height (B)
(on 1206-slze passive deVices, for example)
may differ by several tens of microns. Therefore, A + B can vary considerably, but it is
desirable to keep the dot height (C) constant
for anyone substrate.
The solution to this apparent problem is to
route a track under the device as shown in
Figure 10. ThiS Will eliminate the substrate
metallization height (A) from the adhesive
dot-height crtteria. Quite often, the high component density of SMD substrates necessitates the routing of tracks between solderlands, and, where it does not, a short dummy
track should be Introduced.

9-6

Figure 9. Adhesive Dot Height Criteria

Footprints for Reflow Soldering
To determine the footprint of an SMD for a
reflow-soldered substrate, there are now five
Interactive factors to consider: the four that
affect the wave solder footprints (although
the solder resist may be omitted), plus an
additional factor relating to the solder cream
application (the positional tolerance of the
screen-printed solder cream With respect to
the solderlands).

Solder Cream Application
In reflow soldering, the solder cream (or
paste) IS applied by pressure syringe dispensIng or by screen prtnting. For Industrial purposes, screen printing IS the favored technique because It is much faster than dispensing.

Screen Printing
A stainless steel mesh coated with emulsion
(except for the solderland pattern where
cream IS required) is placed over the substrate. A squeegee passes across the screen
and forces solder cream through the uncoated areas of the mesh and onto the solderland. As a result, dots of solder cream of a
given height and denSity (In mg/mm2) are
produced.
There is an optimum amount of solder cream
for each joint. For example, the solder cream
requirements for the C1206 SM capacitor are
around 1.5mg per end; the SO IC reqUires
between 0.5 and 0.75mg per lead.
The solder cream denSity, combined with the
reqUired amount of solder, makes a demand
upon the area of the solderland (in mm2j. The
footprtnt dimensions for the solder cream
pattern are typically identical to those for the
solderJands.

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

\

o

DUMMY·TRACK [
OR

TROUGH·TRACK

1

~

=--"
C>B

-jo~

\

DDDiT

Figure 10. Through-Track or Dummy
Track to Modify Dot Height Criteria

Floating
One phenomenon sometimes observed on
rellow-soldered substrates is that known as
"floating" (or "swimming"). This occurs
when the solder paste rellows, and the force
exerted by the surface tension of the now
molten solder "pulls" the SMD to the center
of the solderland.
When the solder reflows at both ends simultaneously, the swimming phenomenon results
in the SMD self-centering on the footprint as
the forces of surface tension fight for equilibrium. Although this effect can remove minor
positional errors, it's not a dependable feature and cannot be relied upon. Components
must always be positioned as accurately as
possible.

Footprint Dimensions
The following diagrams (Fig. 11 to 19) show
footprint dimensions for SO ICs, the VSO-40
package, PLCC packages, and the range of
surface-mounted transistors, diodes, resistors, and capacitors. All dimensions given are
based on the criteria discussed in these
guidelines.

DO

ODD

I I

INCHES

INCHES
PACKAGE
OUTLINE

SO·B, 14, 16
SOL-16, 20, 24, 28

A

B

C

D

155
310

275
450

aBO
070

024
024

050
050

PACKAGE
OUTLINE

A

B

C

D

VSQ.40
VSO·56

32
46

536
676

108
108

02
02

A

B

C

SO SMALL
SO LARGE

40
78

70
114

15
18

D

PACKAGE
OUTLINE

,~

PACKAGE
OUTLINE

D
127
127

VSO-40
VSO-56

A

B

C

80
115

134
169

27
27

E
762
75

Figure 12. Footprints for VSO ICs

METRIC (mm)

90

030
030

METRIC (mm)

METRIC (mm)
PACKAGE
OUTLINE

SOLoS

Jl~

B

C

D

132

21

.6

127

INCHES
PACKAGE
OUTLINE

A

B

C

D

SOL·8

36

528

084

024

050

Figure 11. Footprints for SO ICs

Please note - these footprints are based on
our experience with both experimental and
actual production substrates and are reproduced for guidance only. Research is constantly going on to cover all SMDs currently
available and those planned for in the future,
and data will be published when in it becomes
available.
PACKAGE
OUTLINE
PLCC·20
PLCC·28
PLCC-44
PLCC·52
PLCC·68
PLCC·84
PLCC·32

A

B

C

INCHES
D
E

260 .440.090 024

050
050

3BO 540090

024

560 .740.090
660 .840090
.8601 040 .090
1 0601.240 090

.024

.050

024

.050
050
.050
.050

.360 540090

.024
024
024

G
.2BO
440
.360 .540
5BO .740
6BO .840
.8BO 1040
1.0BO 1240
.460 .640

Figure 13. Footprints for PLCCs

February 1987

9-7

•

Signetlcs Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

~:~

r- -1

~c-+-:-·I·-c~

A

~-T-r

o+$-0+1 O-+-OI
TF

-IO=ll
~c-1

SOT-23
Reflow

Wave

I

I

DF07280S

F
-

,

A

B

C

0

0048 0104 0028 0044 0104
0032 0136 0052 0052 00480152

Reflow
Wave

I

0096
010

020B
02

0056
005

0056
OOB

METRIC (mm)
C
0

SOO-80

I

Reflow
Wave

1'2
26
0.834

B

A

0.7
13

E

11
13

F

26
1238

Figure 14_ Footprints for SOT-23
Transistors

~c

CODE

COBOS
R/C1206
C1210
C18DB

C1B12
C2220

DF07290$

SOT-143

I

PACKAGE,
OUTLINE

SOT-143

I

CODE
F

G

H

01040028004800360.0«003601160044

A

B

2.6

07

METRIC (mm)
C
0
E
F

1.2 09

11

G

0920

H

50

14

125

+

PACKAG\
OUTLINE
A
SOT-89

I

20

SOT-B9

OF07260$

INCHES
B

0

C

E

I

20

B

46

METRIC (mm)
E
C
0

26

12

08

F

G

07

3B

Figure 16. Footprints for ReflowSoldered SOT-89 Transistors

_lEi

:-+-c~

COBOS
R/C1206
C1210
ClaDB
C1812

C2220

SIZE

INCHES
B
A

C

G

F

0 08 0184 01040048003200280152

PACKAG\
OUTLINE
A

0

14

O-m-Dl
be -I·
:~_c=:J

DF073{)OS

0

008 x 005 0.032 0136 0052 0056
0128X0064 0072 o 1B4 0056 0068
0128 X 01 0072 0184 0056 0104
018XODB 0112
018X0128 0112

0228X02

SIZE
20 X 125
32 X 1 6
32 x 25
45 x 20

45 x 32
57 X 50

016

0248
0.248

METRIC (mm)
B
A

DB
18
18
28
28
40

D068

0084

0068 0132
0296 0068 0204

34
46
46
62
62
74

C

0

13
1.4
14
17
17
17

14
17
26
21
33
51

11

Figure 17. Footprints for ReflowSoldered SOT-143 Transistors

February 1987

25

0_011

OF07270S

~H~

INCHES
0
E

52

i

0-011
C

24

-L

lEG

B

I

METRIC (mm)
B
C

A

0 OI

D_.O+1
-II
A

Reflow
Wave

I

Figure 15_ Footprints for SOD-80
Diodes

~B-+-:-+-B~

I

INCHES

SOO-80

E

B

t:hl:~

OF07250S

INCHES
0
C

B

A

SOT-23

PACKAGE
OUTLINE

r-~

Figure 18. Footprints for ReflowSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors

9-8

I

COa05
R/C1206

CODE

I

SIZE

I

SIZE

A

INCHES
B
C

0

E

008 X 1 05 0048 0144 0048 0048 0016

0128 x 0640 08

C0805
12.0 x 125
R/C1206
32 x 6

0192 0056 0056 0020

METRIC (mm)
A
B
C

12
20

36
48

12
14

0

E

12
14

04
05

Figure 19. Footprints for WaveSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

Layout Considerations
Component orientation plays an important
role in obtaining consistent solder-joint quality. The substrate layout shown in Figure 20
will result in significantly better solder joints
than a substrate with SMO resistors and
capacitors positioned parallel to the solder
flow.

Component Pitch
The minimum component pitch is governed
by the maximum width of the component and
the minimum distance between adjacent
components. When definong the maximum
component width, the rotational accuracy of
the placement machine must also be considered. Figure 21 shows how the effective width
of the SMO is increased when the component
is\{otated with respect to the footprint by
angle 1/>0. (For clarity, the rotation is exaggerated in the illustration.)

SOLDER
FLOW

The minimum permissible distance between
adjacent SMOs is a figure based upon the
gap required to avoid solder-bridging during
the wave soldering process. Figure 22 shows
how this distance and the maximum component width are combined to derive the basic
expression for calculating the minimum pitch
(FMIN).
As a guide, the recommended minimum
pitches for various combinations of two sizes
of SMOs, the A/C1206 and C0805 (A or C
designating resistor or capacitor respectively;
the number referring to the component size),
are given in Table 1. These figures are
statistically derived under certain assumed
boundary conditions as follows:
• Positioning error (Ap)± 0.3mm; (± 0.012")
• Pattern accuracy (Aq)± 0.3mm;
(±0.012")

SUBSTRATE
DIRECTION

~

L--..-.j/'

DF07310S

FlgurB 20. Recommended Component Orientation for Wave-Soldered Substrates

• Aotational accuracy (I/»± 3°
• Component metallizationl solderland
overlap (MMIN) 0.1 mm (0.004") (Note
this figure is only valid for wave
soldering)
• The figure for the minimum permissible
gap between adjacent components
(GMIN) is taken to be 0.5mm (0.020").
As these calculations are not based on worstcase conditions, but on a statistical analysIs
of all boundary conditions, there is a certain
flexibility in the given data.
For example, it is possible to position AI
C1206 SMOs on a 2.5mm pitch, but the
probability of component placements occurring with GMIN smaller than 0.5mm will increase; hence, the likelihood of solder-bridging also increases. Each application must be
assessed on individual merit with regard to
acceptable levels of rework, and so on.

February 1987

"""'".
NOTES:
til "" Component fotatlon with respect to footpnnt

L Sin ¢ "" Effective Increase
W Sin

q, ... Effective

In

width

Increase In length

Figure 21. The Influence of Rotation of the SMD With Respect to the Footprint

Solderland/Vla Hole
Relationship
With reflow-soldered multilayer and doublesided, plated through-hole substrates, there
must be sufficient separation between the via
holes and the solderlands to prevent a solder

9-9

well from forming. If too close to a solder
joint, the via hole may suck the molten solder
away from the component by capillary action;
this results in insufficient wetting of the joint.

•

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

of a leaded component. Minimum distances
between the clinched lead ends and the
SMOs or substrate conductors are 1mm
(0.04") and 0.5 (0.02") respectively.

!

I CENTERLINE Of
~EFERENCE HOLE

T i

J - ~ ______

'11,].,.
.~~lj
P, ±'p

J..

----l:-+-t-...Ji \_

_---'-'L U

'LL....J.-lJ

----T'""'1[lD ,~

NOTES:
WMAX"'" MaXimum Width of component
GMIN = Minimum permissible gap
FMIN = MInimum pitch
P1 = Nominal position of component 1 (tolerance Ap)
P2 = Nominal position of component 2 (tolerance Ap)
FMIN = WMAX + 2Ap + GMIN

Table 1. Recommended Pitch For R/C1206 and COSOS SMDs
Component

A

II
II
II

A

II-t

Uniform placement uses a modular grid system with devices placed on a uniform center·
to·center spacing. (For example, 2.5 (0.1' ') or
Smm (0.2") as shown in Figure 24b.) This
placement has the distinct advantage of es·
tablishing a standard and enables the use of
other automated placement machines for fu·
ture production requirements without having
to redesign boards.

Substrate Population

Figure 22. Criteria for Determining the Minimum Pitch of SMDs

Combination

Placement Machine Restrictions
There are two ways of looking at the distribution of SMOs on the substrate: uniform SMO
placement and non-uniform SMO placement.
With nonuniform placement, center-to-center
dimensions of SMOs are not exact multiples
of a predetermined dimension as shown in
Figure 24a, so the location of each is difficult
to program into the machine.

Component B
R/C1206

COB05

R/C1206
COB05

3.0(0.12")
2.B(0.112")

2.8 (0.112")
2.6 (0.01 04")

R/C1206
COB05

5.B (0.232")
5.3 (0.212")

5.3 (0.212")
4.B (0.192")

R/C1206
COB05

4.1 (0.164")
3.6(0.144")

3.7(0.14B")
3.0(0.12")

Population density of SMOs over the total
area of the substrate must also be carefully
considered, as placement machine limitations
can create a "lane" or "zone" that restricts
the total number of components which can be
placed within that area on the substrate.
For example, on a hardware-programmable
simultaneous placement machine (see Figure
3c), each pick-and-place unit within the placement module can only place a component on
the substrate in a restricted lane (owing to

Fmm

B

A

II~

II II

B

L-fmm-J

II

D

II · II
Lf~n~

Solderland/Component Lead
Relationship
Of specIal consideration for mixed·print substrate layout IS the location of leaded components with respect to the SMO footprints and
February 19B7

the minimum distance between a protruding
clinched lead and a conductor or SMO. Figure
23 shows typical configurations for R/C1206
SMOs mounted on the underside of a sub·
strate with respect to the clinched leads

9-10

Figure 23. Location of RIC 1206
SMDs on the Underside of a MlxedPrint Substrate with Respect to the
Clinched Leads of Through-Hole
Components (Dimensions In mm)

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

Test Points
Siting of test points for in-circuit testing of
SMD substrates presents problems owing to
the fewer via holes, higher component densities, and components on both sides of SMD
substrates. On conventional double-sided
PCBs, the via holes and plated-through component lead-holes mean that most test-points
are accessible from one side of the board.
However, on SMD substrates, extra provision
for test-points may have to be made on both
sides of the substrate.

2Smm

~
I~

Irr:
r.-n
IL...L-

1-

r--u

C:::J

rl--l

+1

[1=1

1 1 IrI-rTl
t:::::J

DF07380S

a. Non-Uniform Component Placement

2Smm

H

FA
FA
b bJ Irr hl Irr n bbd
ILL f.--.lJ ILL f-lJ

n
FA Irr
bbd !LL J....l.l

Irr hl
ILL I-l.I
OF07390S

b. Uniform Component Placement
Figure 24
adjacent pick-and-place units), typically 10 to
12mm (0.4" to 0.48") wide, as shown in
Figure 25.
SUBSTRATE
DIReCTION

S

c:==::>

ee

• •
$

$-

~

--

TYPICAL
100mm

i$

S

DF07400S

Figure 25. Substrate "Lanes"
From Use of a Simultaneous
Placement Machine
Placement of the 10 components in the lane
on the right of the substrate shown will
require a machine with 10 placement modules (or ten passes beneath a single placement module), an inefficient process considering that there are no more than three SMDs
in any other lane.

February 1987

Figure 26a shows the recommended approach for positioning test-points in tracks
close to components, and Figure 26b shows
an acceptable (though not recommended)
alternative where the solderland is extended
to accommodate the test pin. This latter
method avoids sacrificing too much board
space, thus maIntaining a high-density layout,
but can introduce the problem of components
moving ("noating") when reflow-soldered.
The approach shown in Figure 26c is totally
unacceptable since the pressure applied by
the test pin can make an open-circuit
soldered joint appear to be good, and, more
importantly, the test pin can damage the
metallization on the component, particularly
with small SMDs.

a. RECOMMENDED Test Point
Location Close to an SMD

b. Acceptable Test Point Location

CAD Systems for SMD
Substrate Layout
At present, about half of all PCBs are laid out
using computer-aided design (CAD) techniques, and this proportion is expected to rise
to over 90% by 1988. 01 the many current
CAD systems avaIlable for designing PCB
layouts for conventional through-hole components and ICs in DIL packages, few are SMDcompatible, and systems dedicated exclusively to SMD substrate layout are still comparatively rare. There are two main reasons
for this: some CAD suppliers are waiting for
SMD technology to fully mature before updating their systems to cater to SMD-Ioaded
substrates, and others are holding back until
standard package outlines are fully defined.
However, updating CAD systems used for
through-hole printed boards is not simply a
case of substituting SMD footprints for conventional component footprints, since SMDpopulated substrates impose far tougher restraints on PCB layout and require a tolal
rethink of the layout programs. For example,
systems must deal with higher component
densities, finer track widths, devices on both
sides of the substrate (possibly occupying
corresponding positions on opposite sides),
and even SMDs under conventional DILs on
the same side of the substrate.
The amount of reworking that a program
requires depends on whether it's an interactive (manual) system, or one with fully automatic routing and placement capabilities. For

9-11

c. UNACCEPTABLE Test Point
Location
Figure 26
interactive systems, where the user positions
the components and routes the tracks manually on-screen, program modifications will be
minimal. Automatic systems, however, must
contend with the stricter design rules for SMD
substrate layout. For example, many autorouting programs assume that every solderland is a plated through-hole and, therefore,
can be used as a via hole. This is not
applicable for SMD-populated substrates.
CAD programs base the substrate layout on a
regular grid. This method, analogous to drawing the layout on graph paper, must have the
grid ilnes on a pitch that is no larger than the
smallest component or feature (track width,
pitch, and so on). For conventional OIL
boards, this is typically 0.635mm (0.025"), but
with the much smaller SMDs, a grid spacing
of 0.0254mm (0.001") is required. Consequently, for the same area of substrate, a
CAD system based on this finer grid requires

•
I

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

a resolution more than 600 times greater than
that required for conventional-layout CAD
systems.
To handle thiS, extra memory capacity can be
added, or the allowable substrate area can be
limited In fact, the small Size of SMDs, and
the high-density layouts possible, generally
result In a smaller substrate. However, hlghdensity layout gives nse to additional complications not directly related to the SMD substrate design gUidelines. Most CAD systems,
for Instance, cannot always completely route
all Interconnects, and some traces have to be
routed manually. This can be particularly
difficult with the fewer via holes and smaller
component spacing of SMD boards.
Ideally, the CAD program should have a
"tear-up and start again" algonthm that allows It to restart autoroutlng If a prevIous

February 1987

attempt reaches a position where no further
traces can be routed before an acceptable
percentage of interconnects (and this percentage must first be determined) have been
made. This minimizes the manual reworking
reqUired.

CAE/CAD/CAM Interaction
Computer-aided production of pnnted boards
has evolved from what was Initially only a
computer-aided manufactunng process
(CAM - digitizing a manually-generated layout and using a photoplotter to produce the
artwork) to fullY-interactive computer-aided
englneenng, design, and manufacture uSing a
common database. Figure 27 Illustrates how
thiS multi-dimensional interaction IS particularly well-sUited to SMD-populated substrate
manufacture In ItS highly-automated enVIronment of plck-and-place assembly machines
and test equipment.

9-12

USing a fullY-Integrated system, linked by
local area network to a central database, will
make It pOSSible to use the initial computeraided englneenng (CAE - schematiC design,
logic venflcatlon, and fault simulation) In the
generation of the final test patterns at the end
of the development process. These test patterns can then be used With the automatic
test eqUipment (ATE) for functional testing of
the finished substrates.
Such a system IS particularly useful for testing
SMD-populated substrates, as their high component density and fewer Via-holes make incircuit testing ("bed of nails" approach) difficult Consequently, manufacturers are turning
to functional testing as an alternative. These
aspects are covered In another publication
entitled Functional Testing and Repair.

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

CAD
SOFTWARE

J
CAD

B

CAE

'1:.'=

SOFTWARE

DEVELOPMENT

~~

CAM

MANUFACTURE

CAE

rI~~~--~---1~--4----+--~~~~~

SDFTWARE~~'~~--~~F~--==~1~~==~~r-~~~__==~~'~____L-~'~

__ __
~

~~~=-

LOCAL AREA NETWORK

HARDWARE

Figure 27. The Software-Hardware Interaction for the Computer-Aided Engineering, Dealgn,
and Manufacture of SMD Substrates

February 1987

9-13

•

Signetics

Test and Repair

Linear Products

AN INTRODUCTION
The key questions that must be asked of any
electronic circuit are "does it work, and Will It
continue to do so over a specified period of
time?" Until zero-defect soldenng IS
achieved, and all components are guaranteed
serviceable by the vendors, manufacturers
can only answer these questions by carrying
out some form of test on the finished product.
The types of tests, and the depth to which
they are carried out, are determined by the
complexity of the CIrCUIt and the customer's
requirements. The amount of rework to be
performed on the CirCUit Will depend on the
results of these tests and the degree of
reliability demanded. The criteria are true of
all electronic assemblies, and the test engineer must formulate test schedules accordingly.
Substrates loaded With surface mounted devices (SMOs), however, pose additional problems to the test engineer. The devices are
much smaller, and substrate population density is greater, leading to difficulty in accessIng all circuit nodes and test points. Also SMO
substrate layout designs often have fewer via
and component lead holes, so test points
may not all be on one Side of the substrate
and double-sided test fixtures become necessary.
To achieve the high throughput rates made
possible by uSing highly automated SMO
placement machines and volume soldering
techniques, automatic testing becomes a necessity. Visual inspection of the finished substrate by trained Inspectors can normally
detect about 90% of defects. With the correct
combination of automatic test equipment, the
remainder can be eliminated. In this publication, we hope to provide the manufacturer
with information to enable him to evaluate
and select the best combination of test equipment and the most effective test methods for
his product.

BARE-BOARD TESTING
Although SMD substrates will undoubtedly be
smaller than conventional through-hole substrates and have less space between conductors, the prinCiples of bare-board testing
remain the same. Many of the testers already
in use can, with little or no modification, be
used for SMD substrates. As thiS is already a
well-established and well-documented practice, it will not be discussed further in this
publication, but It is recommended that bareFebruary 1987

board testing always be used as the first step
in assuring board Integrity.

POST-ASSEMBLY TESTING
Testing densely populated substrates IS no
easy task, as the components may occupy
both sides of the board and cover many of
the Circuit nodes (see Figure 1 for the three
main types of SMO-populated substrates).
Unlike conventional substrates, on which all
test points are usually accessible from the
bottom, SMO assemblies must be designed
from the start With the siting of test points in
mind. Probing SMO substrates is particularly
difficult owing to the very close spacing of
components and conductors.
Mixed print or all-SMO assemblies With components on both Sides further aggravate the
testing problems, as not all test pOints are
present on the same side of the board.
Although two-sided test fixtures are feasible,
they are expensive and require considerable
time to bUild.
The application of a test probe to the top of
an SMO termination could damage It, and
probe pressure on a poor or open solder joint
can force contact and thus allow a defective
joint to be assessed as good. Figure 2a
Illustrates the recommended siting of test
pOints close to SMO terminations, and Figure
2b shows an alternative, though not recommended, option. Here, problems could arise
from reflow soldering (solder migrating from
the JOint) unless the test pOint area is separated from the solder land area with a stripe of
solder resist. ExceSSive mechanical pressure
caused by too many probes concentrated In a
small area may also result in substrate damage.
It IS good practice for substrates to have test
points on a regular grid so that convenllOnal,
rather than custom, testers may be used. If
the substrate has tall components or heatsinks, the test points must be located far
enough away to allow the probes to make
good contact. All test pOints should be solder
coated to prOVide good electrical contact. Via
holes may also be used as test points, but the
holes must be filled With solder to prevent the
probe from sticking.

AUTOMATIC TEST EQUIPMENT
(ATE)
As manufacturers strive to increase production, the quesllOn becomes not whether to

9-14

4

a. Type I - Total Surface Mount
(AII-SMD) Substrates

b. Type IIA - Mixed Print
(Double-Sided) Substrate

c. Type liB - Mixed Print
(Underside Attachment) Substrate
Figure 1
use automatic test engineering (ATE), but
which ATE system to use and how much to
spend on It. Because of the rapid fall In price
of computers, memories, and peripherals,
today's low-cost ATE equals the performance
of the high-cost eqUipment of just two or
three years ago. For factory automation, manufacturers must consider many factors, such
as producllOn volume, product complexity,
and availability of skilled personnel.
One question is whether the ATE system can
be used not only for production testing but
also for service and repair to reduce the high
cost of keeping a substrate inventory in the
field. Another is whether assembly and process-induced faults represent a significant
percentage of production defects, rather than
out-of-tolerance components. These queslIOns need to be answered before deciding on
the type of ATE system required.

Signetlcs Linear Products

Test and Repair

of an In-CIrcUIt tester alone, improves the
throughput rate.

"~l

FAULT
DETECTION
':

IN· CIRCUIT

~

.0 i

'N·C'RCU'T

lI

40"1

a. Recommended Location
of Test Points Close to SMOs

WEEKS

0

FUNCTIONAL
TESTER

ANA~LVZ~~;RO~~~~~G

SHORT.

~ ~~s;~~
~ 65%
60 "I
70

50

TESTER

98%

PRO'O%

GR~~':NG
9 MONTHS

50%
PROGRAMMING
TIME 4 DAYS

JI PROG~S:;"MING
20
1

30

TIME 6 HOURS

1:JL...____________~

Figure 3. Bar Chart Showing a
Comparison of Percent Fault Detection
and Programming Time for
Various ATE Systems
deSign can, however, often eliminate the
need for double-sided test probe fixtures.

b. Acceptable, Though
Not Recommended, Location of
Test Points Close to SMOs

In-cirCUit testers power the assembly and
check for open or Short-CIrCUitS, cirCUit parameters, and can pinpoint defective components They can provide around 90% fault
coverage, but are more expensive than shortCirCUit testers and programming can take
more than SIX weeks.
In-CIrCUIt analyzers are relatively Simple to
program and can detect manufactUring-induced faults In one third of the time reqUired
by an in-circUit tester Fault coverage is
between 50% and 90%. Because they do not
power the assembly, they cannot detect digital logiC faults, unlike an in-CIrCUit tester or
functional tester.

c_ Unacceptable Location
of Test Points Close to SMOs
Figure 2
Several systems are currently available to the
manufacturer, including short-CIrcUit testers,
in-circuit testers, in-circUit analyzers, and
functional testers. Figure 3 shows a bar-chart
giving a comparison of percent fault detection
and programming time for various ATE systems.
A loaded-board, short-CIrcUit tester takes
from two to six hours to program and ItS
effective fault coverage is between 35% and
65%. It has the advantage of being operationally fast and comparatively inexpensive. On
the negative Side, however, it IS limited to the
detection of short-circuits and may require a
double-sided, bed-of-nalls test fixture (see
Figure 4), which for SMD substrates may be
expensive and take time to produce. Careful

February 1987

Functional testers, on the other hand, check
the assembly's performance and Simply
make a go or no-go decIsion. Either the
assembly performs its reqUired function or It
does not. They are much more expenSive, but
their fault coverage is between 80% and
98%. Their major disadvantages, apart from
cost, are that they cannot locate defective
components, and programming for a hlghcapacity system can take as long as nine
months.

Combining a short-CIrcuit tester with a functional tester produces even more dramatic
results. If most defects are manufacturlngproduced shorts, the use of a short-circuit
tester to relieve the functional tester of this
task can Increase throughput five-fold while
maintaining a fault coverage of up to 98%.
If manufacturing faults and analog component defects are responsible for the maJority
of failures, a relatively low-cost, in-circuit
analyzer can be used in tandem with an InCirCUit tester or functional tester to reduce
testing costs and Improve throughput. The InCircuit analyzer IS three times faster than an
in-circuit tester in detecting manufacturlngInduced faults, offers test and diagnostics
usually within 10 seconds each, and IS relatively simple to program. But because It IS
unpowered, an In-circUit analyzer cannot test
digital logic faults, either an in-CIrcUit tester or
functional tester follOWing the In-circUit analyzer must be used to locate this type of
defect.

POLLUTED POWER SUPPLIES
Today's electronic components and the
equipment used to test them are susceptible
to electrical nOise. Erroneous measurements
on pass-or-fall tests could lower test throughput or, even more seriously, allow defective
products to pass inspection. Semiconductor
chips under test can also be damaged or
destroyed as high-energy pulses or line-voltage surges stress the fine-line geometrics
separaling Individual cells.
NOise pulses can be either In the normal (lineto-line) mode or common (Ilne-to-ground)
mode. Common-mode electrical nOise poses
a speCial threat to modern electronic circuitry
since the safety ground line to which common-mode nOise is referenced IS often used
as the system's logic reference point. Since
paraSitic capacitance eXists between safety
ground and the reference pOint, at high frequencies these points are essentially lied
together, allowing noise to directly enter the
system's logic.

ATE Systems
An analysis of defects on a finished substrate
will determine which combination of ATE will
best meet the test requirements with regard
to fault coverage and throughput rate.
If most defects are short-circuits, a loadedboard short-cirCUit tester, In tandem with an
in-Circuit tester, will pre-screen the substrate
for short-circuits tWice as fast as the in-circuit
tester. This allows more time for the in-circuit
tester to handle the more complex test reqUirements. This combination of ATE, Instead

9-15

MANUAL REPAIR
The repair of SMD-populated substrates will
entail either the resolderlng of individual joints
and the removal of shorts or the replacement
of defective components.
The reworking of defective joints will invariably involve the use of a manual soldering
iron. Bits are commercially available in a
variety of shapes, including special hollow
bits used for desoldering and for the removal
of solder bridges. The criteria for the inspec-

•
•

Signetics Linear Products

Test and Repair

I

I

I

DOUB l{SIDED
TEST

'r

~

I

~

r---1

DOUBlE-SIDED
SM o SUBSTRATE

SPRING.LOAOE~ " ' "
TEST PRODS

~

I
Figure 4. Double-Sided. Bed-of-Nails Test Fixture

Using air pressure, the center pin of the collet
then pushes the PLCC into contact with the
substrate where It IS maintained with the
correct amount of force. Heat is then applied
through the walls of the collet to reflow the
solder paste. The center pin maintains pres·
sure on the PLCC until the solder has solidi·
fied, then the center pin is raised and the
replacement is complete.

VACUUM

PIPEITe

r

HEAD

Mor

SUBSTRATE

Figure 5. Heated Collet for the Removal and Replacement of Multi-Leaded SMDs
(a PLCC is Shown Here)

tlon of reworked soldered JOints are the same
as those for machine soldering.
Special care must be taken when reworking
or replacing electrostatic sensitive devices.
Soldering I(ons should be well grounded via a
safety resistor of minimum 100kU. The
ground connection to the soldering I(on
should be welded rather than clamped. This
IS because oxidation occurs beneath the
clamp, thus isolating the ground connection.
Voltage spikes caused by the sWitching of the
I(on can be avoided by uSing either contlnu,
ously·powered irons, or I(ons that switch only
at zero voltage on the AC Sine curve.
To remove defective leadless SMDs, a variety
of soldering iron bits are available that will
apply the correct amount of heat to both ends
of the component simultaneously and allow it
to be removed from the substrate. If the
substrate has been wave soldered, an adhe·
sive Will have been used, and the bond can

February 1987

be broken by twisting the bit. Any adhesive
residue must then be removed. The same
tool is then used to place and solder the new
component, using either solder cream or
resln·cored solder.
When a multi-leaded component, such as a
plastiC leaded chip carner (PLCC), has to be
removed, a heated collet can be used (see
Figure 5). The collet is pOSitioned over the
PLCC, heat IS applied to the leads and solder
lands automatically until the solder reflows.
The collet, complete with the PLCC, is then
raised by vacuum. Solder cream is then reo
applied to the solder lands by hand. No
adhesive is required in this operation.
The collet is positioned over the replacement
PLCC, which is held in place by the slight
spring pressure of the PLCC leads against the
walls of the collet. The collet, complete with
PLCC, IS then raised pneumatically and posi·
tloned over the solder lands.

9-16

Another method, well·suited to densely popu·
lated SMD substrates, uses a stream of
heated air, directed onto the SMD termina·
tlons. Once the solder has been rellowed, the
component can be removed with the aid of
tweezers. While the hot air is being directed
onto the component, cooler air is played onto
the bottom of the substrate to protect it from
heat damage. DUring removal, the compo·
nent should be twisted Sideways slightly in
order to break the surface tension of the
solder and any adhesive bond between the
component and the substrate. ThiS prevents
damage to the substrate when the compo·
nent is lifted.
To fit a new component, the solder lands are
first retinned and fluxed, the new component
accurately placed, and the solder reflowed
with hot air. Substituting superheated argon,
nitrogen, or a mixture of nitrogen and hydrogen for the hot air stream removes any risk of
contaminating or oxidizing the solder.
Focused infrared light has also been used
successfully to rellow the solder on densely
populated substrates.
In general, the equipment and procedures
used lor the replacement 01 PLCCs can be
used lor lead less ceramic chip carriers
(LCCCs) and small-outline packages (SO
ICs). SO ICs are somewhat easier to replace,
as the leads are more accessible and only on
two sides 01 the component.

Signetics

Fluxing and Cleaning

Linear Products

INTRODUCTION
The adoption of mass soldering techniques
by the electronics Industry was prompted not
only by economics, and a requirement for
high throughput levels, but also by the need
for a consistent standard of quality and reliability in the finished product unattainable by
using manual methods. With surface-mounted device (SMD) assembly, this need is even
greater.
The quality of the end-product depends on
the measures taken dUring the design and
manufacturing stages. The foundations of a
high-quality electronic circuit are laid with
good design, and with correct choice of
components and substrate configuration. It is,
however, at the manufacturing stage where
the greatest number of variables, both with
respect to materials and techniques, have to
be optimized to produce high-quality soldering, a prerequisite for reliability.
Of the two most commonly-used soldering
techniques, wave and reflow, wave soldering
is by far the most widely used and understood. Many factors Influence the outcome of
the soldering operation, some relating to the
soldering process Itself, and others to the
condition of components and substrate to
which they are to be attached. These must be
collectively assessed to ensure high-quality
soldering.
One of the most important, most neglected,
and least understood of these processes IS
the choice and application of flux. This section outlines the fluxing options available, and
discusses the various cleaning techniques
that may be required, for SMD substrate
assembly.

FLUXES
Populating a substrate Involves the soldering
of a variety of terminallons simultaneously. In
one operation, a mixture of IInned copper,
tin/lead-or gold-plated nickel-Iron, palladiumsilver, lin/lead-plated nickel-barrier, and even
materials like Kovar, each possessing varying
degrees of solderability, must be attached to
a common substrate uSing a single solder
alloy.
It is for this reason that the chOice of the flux
IS so Important. The correct flux Will remove
surface oxides, prevent reoxidizallon, help to
transfer heat from source to jOint area, and
leave non-corrosive, or easily removable corrosive residues on the substrate. It Will also
February 1987

Improve wettability of the solder jOint surfaces.
The wettablhty of a metal surface is its ability
to promote the formation of an alloy at ItS
Interface with the solder to ensure a strong,
low-resistance jOint.
However, the use of flux does not eliminate
the need for adequate surface preparation.
This IS very important In the soldering of SMD
substrates, where any temptation to use a
highly-active flux in order to promote rapid
wetting of ill-prepared surfaces should be
aVOided because It can cause serious problems later when the corrosive flux residues
have to be removed. Consequently, optimum
solderability is an essential factor for SMD
substrate assembly.
Flux is applied before the wave soldering
process, and dUring the reflow soldering process (where flux and solder are combined in a
solder cream). By coating both bare metal
and solder, flux retards atmospheric oXidization which would otherwise be intensified at
soldering temperature. In the areas where the
oXide film has been removed, a direct metalto-metal contact IS established with one lowenergy interface. It is from this point of
contact that the solder will flow

Types of Flux
There are two main characteristiCS of flux.
The first IS efficacy-its ability to promote
wetting of surfaces by solder within a specified time. Closely related to this is the activity
of the flux, that is, ItS ability to chemically
clean the surfaces.

ed In varying quantities to increase it. These
take the form of either organic aCids, or
organic salts that are chemically active at
soldenng temperatures. It is therefore convenient to classify the colophony-based fluxes
by their activator content.

Non-Activated Rosin (R) Flux
These fluxes are formed from pure colophony
In a suitable solvent, usually isopropanol or
ethyl alcohol. Efficacy is low and cleaning
action is weak. Their uses in electronic soldering are limited to easily-wettable materials
with a high level of solderability. They are
used mainly on cirCUits where no risk of
corrosion can be tolerated, even after prolonged use (Implanted cardiac pacemakers,
for example). Their flux residues are noncorrOSive and can remain on the substrate,
where they will provide good insulation.

Rosin, Mildly-Activated (RMA)
Flux
These fluxes are also composed of colophony In a solvent, but with the addition of
activators, either In the form of di-basic organic aCids (such as SUCCInC aCid), or organic
salts (such as dlmethylammonium chloride or
dlethylammonium chlOride). It is customary to
express
the amount of added activator as mass percent of the chlorine ion on the colophony
content, as the actlvator-to-colophony ratio
determines the activity, and, hence, the corrosivlty. In the case of RMA activated With
organic salts, this is only some tenths of one
percent.

Organic Soluble Fluxes

When organic aCids are used, a higher percentage of activator must be added to produce the same efficacy as organic salts, so
frequently both salts and acids are added.
The cleaning action of RMA fluxes is stronger
than that of the R type, although the corroslvity of the reSidues IS usually acceptable.
These residues may be left on the substrate
as they form a useful insulating layer on the
metal surfaces. This layer can, however,
impede the penetration of test probes at a
later stage.

Most of the fluxes soluble in organic liquids
are based on colophony or rosin (a natural
product obtained from pine sap that has been
distilled to remove the turpentine content).
Solid colophony is difficult to apply to a
substrate dUring machine soldering, so it is
dissolved in a thinning agent, usually an
alcohol. It has a very low efficacy, and hence
limited cleaning power, so activators are add-

The RA fluxes are Similar to the RMA fluxes,
but contain a higher proportion of activators.
They are used mainly when component or
substrate solderability is poor and corrosionrisk requirements are less stringent. However,
as good solderability is considered essential
for SMD assembly, highly-activated rosin fluxes should not be necessary. The removal of

The second IS the corroslvity of the flux, or
rather the corroslvlty of its reSidues remaining
on the substrate after soldering. This is again
linked to the activity; the more active the flux,
the more corrOSive are its residues.
Although there are many different fluxes
available, and many more being developed,
they fall Into two baSIC categories; those with
reSidues soluble in organic liqUids, and those
with reSidues soluble In water.

9-17

Rosin, Activated (RA) Flux

•

Signetlcs Linear Products

Fluxing and Cleaning

flux residues is optional and usually dependent upon the working environment of the
finished product and the customer's requirements.

Water-Soluble Fluxes
The water-soluble fluxes are generally used
to provide high fluxing activity. Their residues
are more corrosive and more conductive than
the rosin-based fluxes, and, consequently,
must always be removed from the finished
substrate. Although termed water soluble, this
does not necessarily imply that they contain
water; they may also contain alcohols or
glycols. It is the flux residues that are water
soluble. The usual composition of a watersoluble flux is shown below.
1. A chemically-active component for cleaning the surfaces.
2. A wetting agent to promote the spreading
of flux constituents.
3. A solvent to provide even distribution.
4. Substances such as glycols or watersoluble polymers to keep the activator in
close contact with the metal surfaces.
Although these substances can be dissolved
in water, other solvents are generally used, as
water has a tendency to spatter during soldering. Solvents with higher boiling pomts,
such as ethylene glycol or polyethylene glycol
are preferred.

Water-Soluble Fluxes With
InorganiC Salts
These are based on inorganic salts such as
zinc chloride, or ammonium chloride, or inorganic acids such as hydrochloric. Those with
zinc or ammonium chloride must be followed
by very stringent cleaning procedures as any
halide salts remaining on the substrate will
cause severe corrosion. These fluxes are
generally used for non-electrical soldering.
Although the hydrazine halides are among
the best active fluxing agents known, they are
highly suspect from a health point of view and
are therefore no longer used by flux manufacturers.

Water-Soluble Fluxes With
Organic Salts
These fluxes are based on organic hydrohalides such as dimethylammonium chloride,
cyclo hexalamine hydrochloride, and aniline
hydrochloride, and also on the hydrohalides
of organic acids. Fluxes with organic halides
usually contain vehicles such as glycerol or
polyethylene glycol, and non-ionic surfaceactive agents such as nonylphenol polyoxyethylene. Some of the vehicles, such as the
polyethylene glycols, can degrade the insulation resistance of epoxy substrate material
and, by rendering the substrate hydrophilic,
make it susceptible to electrical leakage in
high-humidity environments.
February 1987

Water-Soluble Fluxes With
Organic Acids
Based on acids such as lactic, melonic, or
citric, these fluxes are used when the presence of any halide is prohibited. However,
their fluxing action is weak, and high acid
concentrations have to be used. On the other
hand, they have the advantage that the flux
residues can be left on the substrate for some
time before washing without the risk of severe
corrosion.

Solder Creams
For reflow soldering, both the solder and the
flux are applied to the substrate before soldering and can be In the form of solder
creams (or pastes), preforms, electro-deposit,
or a layer of solder applied to the conductors
by dipping. For SMD reflow soldering, solder
cream is generally used.
Solder cream IS a suspension of solder particles in flux to which special compounds have
been added to improve the rheological properties. The shape of the particles is important
and normally spherical particles are used,
although non-spherical particles are now being added, particularly in very fine-line soldering.
In principle, the s,ame fluxes are used in
solder creams as for wave soldering. However, due to the relatively large surface area of
the solder particles (which can oxidize), more
effective fluxing is required and, in general,
solder creams contain a higher percentage of
activators than the liquid fluxes. The drying of
the solder paste during preheating (after component placement) is an important stage as it
reduces any tendency for components to
become displaced during soldering.

Flux Selection
ChOOSing an appropriate flux is of prime
importance to the soldering system for the
production of high-quality, reliable joints.
When solderability is good, a mildly-activated
flux will be adequate, but when solderability is
poorer, a more effective, more active flux will
be required. The choice of flux, moreover, will
be influenced by the cleaning facilities available, and if, in fact, cleaning is even feasible.

choice will be between an RA or an RMA
rosin-based flux.

Application of Flux
Three basic factors determine the method of
applying flux: the soldering process (wave or
reflow), the type of substrate being processed
(all-SMD or mixed print), and the type of flux.
For wave soldering, the flux must be applied
in liquid form before soldering. While it is
possible to apply the flux at a separate fluxing
station, with the high throughput rates demanded to maximize the benefits of SMD
technology, today's wave-soldering machines
incorporate an integral fluxing station prior to
the preheat stage. This enables the preheat
stage to be used to dry the flux as well as
preheat the substrate to minimize thermal
shock.
The most commonly-used methods of applying flux for wave soldering are by fdam, wave,
or spray.

Foam Fluxing
Foam flux is generated by forcing low-pressure clean air through an aerator immersed in
liquid flux (see Figure 1). The fine bubbles
produced by the aerator are guided to the
surface by a chimney-shaped nozzle. The
substrates are passed across the top of the
nozzle so that thl' solder side comes in
contact with the foam and an even layer of
flux is applied. As the bubbles burst, flux
penetrates any plated-through holes in the
substrate.

Wave Fluxing
A double-sided wave can also be used to
apply flux, where the washing action of the
wave deposits a layer of flux on the solder
side of the substrate (see Figure 2). Waveheight control is essential and a soft, wipe-off
brush should be incorporated on the exit side
of the fluxing station to remove excess flux
from the substrate.

With water-soluble fluxes, aqueous cleaning
of the substrate after soldering is mandatory.
If thorough cleaning is not carried out, severe
problems may arise in the field, due to corrosion or short circuits caused by too low a
surface resistance of the conductive residues.
For rosin-based fluxes, the need for cleaning
will depend on the activity of the flux. Mildlyactivated rosin residues can, in most cases,
remain on the substrate where they will afford
protection and insulation. In practice, for the
great majority of electronic circuits, the

9-18

AERATOR

COMPRESSED AlA

Figure 1. Schematic Diagram
of FoamFluxer

Signetics Unear Products

Fluxing and Cleaning

PREHEATING
Preheating the substrate before soldenng
serves several purposes. It dries the flux to
evaporate most of the solvent, thus Increasing the viscosity. If the Viscosity IS too low, the
flux may be prematurely expelled from the
substrate by the molten solder. This can
result in poor wetting of the surfaces, and
solder spatter.

IMPELLER

Figure 2. Schematic Diagram
of Wave Fluxer

Spray Fluxing
Several methods of spray fluxing exist; the
most common involves a mesh drum rotating
in liquid flux. Air is blown into the drum which,
when passing through the fine mesh, directs
a spray of flux onto the underside of the
substrate (see Figure 3). Four parameters
affect the amount of flux deposited: conveyor
speed, drum rotation, air pressure, and flux
density. The thickness of the flux layer can be
controlled USing these parameters, and can
vary between 1 and 10jlm.
The advantages and disadvantages of these
three flux application techniques are outlined
in Table 1.

Flux Density
One of the main control factors for fluxes
used in machine soldering is the flux density.
This provides an indication of the solids
content of the flux, and is dependent on the
nature of the solvents used. Automatic control systems, which monitor flux density and
inject more solvent as required, are commercially available, and it IS relatively simple to
incorporate them into the fluxing system.

Drying the flux also accelerates the chemical
action of the flux on the surfaces, and so
speeds up the soldering process. During the
preheating stage, substrate and components
are heated to between BOoe and 90°C (solvent-based fluxes) or to between 10Qoe and
11 Qoe (water-based systems). This reduces
the thermal shock when the substrate makes
contact WIth the molten solder, and minimizes
any likelihood of the substrate warping.
The most common methods of preheating
are: convection heating with forced atr, radiation heating using coils, infrared quartz lamps
or heated panels, or a combination of both
convection and radiation. The use of forced
air has the added advantage of being more
effective for the removal of evaporated solvent. Optimum preheat temperature and duration will depend on the nature and deSign of
the substrate and the composition of the flux.
Figure 4 shows a typical method of preheat
temperature control. The deSired temperature
IS set on the control panel, and the microprocessor regulates preheater No. 1 to prOVide
approximately 60% of the required heat. The
IR detector scans the substrate Immediately
follOWing No. 1 heater and reads the surface
temperature. By taking Into account the surface temperature, conveyor speed, and the
thermal characteristics of the substrate, the
microprocessor then calculates the amount
of additional heat reqUired to be prOVided by
heater No. 2 In order to attain the preset
temperature. In thiS way, each substrate Will
have the same surface temperature on reachIng the solder bath.

POSTSOLDERING CLEANING

AOTAnNG DRUM

Figure 3. Schematic Diagram
of Spray Fluxer

February 1987

Now that worldwide efforts In both commerCial and Industrial electrOniCS are converting
old designs from conventJonal assembly to
surface mounting, or a combination of both, It
can also be expected that high-volume cleanIng systems Will convert from In-line aqueous
cleaners to in-line solvent cleaners or In-line
sapOnification systems (a technique that uses
an alkaline material in water to react With the
rosin so that It becomes water soluble).
These systems may, however, become subject to environmental objections, and new
governmental restrictions on the use of halogenated hydrocarbons.

9-19

The major reason for thiS IS that the watersoluble flux reSidues, containing a higher
concentration of activators, or shOWing hygroSCOPIC behaVior, are much more difficult to
remove from SMD-populated substrates than
rOSin-based flux reSidues. ThiS IS primarily
because the higher surface tension of water,
compared to solvents, makes It difficult for
the cleaning agents to penetrate beneath
SMDs, espeCially the larger ones, with their
greatly reduced all-contact distance (the diStance between component and substrate).
Postsolderlng cleaning removes any contamination, such as surface depoSIts, InclUSions,
occlUSions, or absorbed matter which may
degrade to an unacceptable level the chemical, phYSical, or electrical properties of the
assembly. The types of contaminant on substrates that can produce either electrical or
mechanical failure over short or prolonged
periods are shown In Table 2.
All these contaminants, regardless of their
Origin, fall Into one of two groups: polar and
non-polar.

Polar Contaminants
Polar contaminants are compounds that diSsociate into free Ions which are very good
conductors In water, qUite capable of causing
cirCUit failures. They are also very reactive
With metals and produce corrosive reactions.
It IS essential that polar contaminants be
removed from the substrates.

Non-Polar Contaminants
Non-polar contaminants are compounds that
do not dissociate Into free Ions or carry an
electrical current and are generally good
Insulators. ROSin IS a typical example of a
non-polar contaminant. In most cases, nonpolar contamination does not contribute to
corrOSion or electrical failure and may be left
on the substrate. It may, however, Impede
functional testing by probes and prevent good
conformal coat adheSion.

Solvents
The solvents currently used for the postsoldering cleaning of substrates are normally
organic based and are covered by three
classlflcallOns: hydrophobiC, hydrophilllc, and
azeotropes of hydrophobic/hydrophlilic
blends.
Azeotroplc solvents are mixtures of two or
more different solvents which behave like a
Single liqUid insomuch that the vapor produced by evaporation has the same composItion as the liqUid, which has a constant bOIling
point between the bOIling points of the two
solvents that form the azeotrope. The basic
ingredients of the azeotroplc solvents are
combined With alcohols and stabilizers.
These stabilizers, such as nltromethane, are
included to prevent corrosive reaction be-

9

Signetics Linear Products

Fluxing and Cleaning

Table 1. Advantages and Disadvantages of Flux Application Methods
Method

Advantages

Disadvantages

Foam
Fluxing

• Compatible with continuous
soldering process
• Foam crest height not
critical
• Suitable for mixed-print
substrates

• Not all fluxes have good foaming
capabilitIes
• Losses throught evaporation may
be appreciable
• Prolonged preheating because of
high boiling point of solvents

Wave
Fluxing

• Can be used with any
liquid flux

• Wave crest heIght is critical to
ensure good contact with bottom
of substrate without
contaminating the top

• Compatible with continuous
soldering process
• Suitable for denselypopulated mixed print
Spray
fluxing

• Can be used with most
liquid fluxes
• Short preheat time if
appropriate alcohol
solvents are used
• Layer thickness is
controllable

tween the metallization of the substrate and
the basic solvents.
Hydrophobic solvents do not mix with water
at concentrations exceeding 0.2%, and consequently have little effect on ionic contamination. They can be used to remove nonpolar contaminants such as rosin, oils, and
greases.
Hydrophillic solvents do mix with water and
can dissolve both polar and non-polar contamination, but at different rates. To overcome these differences, azeotropes of the
various solvents are formulated to maximize
the dissolving action for all types of contamination.

Solvent Cleaning
Two types of solvent cleaning systems are in
use today: batch and conveyorized systems,
either of which can be used for high-volume
production. In both systems, the contaminated substrates are immersed in the boiling
solvents, and ultrasonic baths or brushes may
also be used to further improve the cleaning
capabilities.
The washing of rosin-based fluxes offers
advantages and disadvantages. Washed substrates can usually be inserted into racks
easier, as there will be no residues on their
edges; test probes can make better contact
without a rosin layer on the test pOints, and
the removal of the residues makes it easier to
visually examine the soldered jOints. On the
other hand, washing equipment is expensive,
and so are the solvents, and some solvents
present a health or environmental hazard if
not correctly dealt with.
February 1987

• HIgh flux losses due to nonrecoverable spray
• System requires frequent
cleaning

Aqueous Cleaning
For high-volume production, special machines have been developed in which the
substrates are conveyor-fed through the various stages of spraying, washing, rinsing, and
drying. The final rinse water is blown from the
substrates to prevent any deposits from the
water being left on the substrate.
Where water-soluble fluxes have been used
in the soldering process, substrate cleaning is
mandatory. For the rosin-based fluxes, it is
optional, and is often at the discretion of the
customer.

Conformal Coatings
A conformal, or protective coating on the
substrate, applied at the end of processing,
prevents or minimizes the effects of humidity
and protects the substrate from contamination by airborne dust particles. Substrates
that are to be provided with a conformal
coating (dependent on the environmental
conditions to which the substrate will be
subjected) must first be washed.

Environmental and Ecological
Aspects of Fluxes and Solvents
Fumes and vapors produced during soldering
processes, or during cleaning, will not, under
normal CIrcumstances, present a health hazard, if relevant health and safety regulations
are observed.
Fumes originating from colophony can cause
respiratory problems, so an efficient fumeextraction system is essential. The extraction
system must cover the fluxing, preheating,
and soldering stations, remain operational for
at least one hour after machine shutdown,

9-20

and conform to local regulations. Today, the
problem of noxious fumes is unlikely to concern the cleaning station, as all commercial
systems are equipped to condense the vapors back into the system. In the future,
however, it can be expected that a much
lower degree of escape of noxious fumes
from any system will be allowed, and all
systems may have to be reviewed.
Certain fluxes, particularly some water-soluble ones, contain highly aggressive substances, and must not be allowed to come
into contact with the skin or eyes. Any contamination should immediately be removed
with plenty of clean, fresh water. Deionized
water should also be readily available as an
eye-wash. Should contamination occur, a
qualified medical practitioner should be consulted. Protective clothing should be worn
during cleaning or maintenance of the fluxing
station.

Conclusion
SMD technology imposes tougher restraints
on fluxing and cleaning of substrate assemblies. Traditionally, rosin-based fluxes have
been used in electronic soldering where residues were considered "safe" and could be
left on the board. However, increased SMD
packing denSity, fine-line tracks, and more
rigid specifications have resulted in changes
to this basic philosophy.
There is now a demand for surfaces free from
residues; test probes are more efficient when
they do not have to penetrate rosin flux
residues. and conformal coating and board
inspection benefit from the absence of such
residues.
Cleaning also poses problems for SMD substrates. The close proximity of component
and substrate means that solvents cannot
effectively clean beneath devices. Components must also be compatible with the cleaning process. They must, for example, be
resistant to the solvents used and to the
temperatures of the cleaning process. They
must also be sealed to prevent cleaning fluids
from entering the devices and degrading
performance.
So, eliminating the need for cleaning is better
than poor or incomplete cleaning. And in a
well-balanced system, mildly-activated rosinbased fluxes, leaving only non-corrosive residues, can be successfully used for SMD
substrate soldering without subsequent
cleaning.
Much research into fluxes and solder creams
is presently being done - for example, the
production of synthetic resin, with qualities
superior to colophony at a lower cost. Another area of research is that of solder creams
with non-melting additives, such as lead or
ceramic spheres, that increase the distance

Signetics Linear Products

Fluxing and Cleaning

CONVEYOR
DRIVE

MOTOR

PRE·HEATER

2

SOLDER BATH

TEMPERATURE SET
CONTROL PANEL

Figure 4. Schematic Diagram of a Typical Controlled Preheat System

Table 2. Substrate Contaminants
Contaminant
Organic compounds
Inorganic Insoluble compounds
Organo-metalilc compounds
Inorganic soluble compounds
Particle matter

Origin
Fluxes, solder mask
Photo-resists, substrate processing
Fluxes, substrate processing
Fluxes
Dust, fingerpnnts

between component and substrate, thus
making it easier for cleaning fluids to pene·
trate beneath the component. It also increases the jOint's ability to withstand thermal
cycling.
Rosin-free and halide-free fluxes are also
being developed With similar actiVities to conventional rosin-based fluxes. These new
types will combine the "safety" of rosin
fluxes With easier removal In conventional
solvents. Using non-polar matenals, IOnizable
or corrosive reSidues are eliminated, and the
need for cleamng immediately after soldering
IS avoided.

•
February 1987

9-21

Signetics

Thermal Considerations for
Surface-Mounted Devices

Linear Products

INTRODUCTION
Thermal characteristics of integrated circuit
(IC) packages have always been a major
consideration to both producers and users of
electronics products. This is because an increase in junclion temperature (TJ) can have
an adverse effect on the long-term operating
life of an IC. As will be shown in this section,
the advantages realized by miniatunzatlon
can often have trade-offs in terms of Increased junction temperatures. Some of the
VARIABLES affecting TJ are controlled by
the PRODUCER of the IC, while others are
controlled by the USER and the ENVIRONMENT in which the device is used.
With the increased use of Surface-Mount
Device (SMD) technology, management of

thermal charactenstics remains a valid concern, not only because the SMD packages
are much smaller, but also because the
thermal energy IS concentrated more densely
on the printed winng board (PWB). For these
reasons, the designer and manufacturer of
surface-mount assemblies (SMAs) must be
more aware of all the vanables affecting TJ.

POWER DISSIPATION
Power diSSipation (PD), varies from one de·
vice to another and can be obtained by
multiplYing Vcc Max by typical Icc· Since Icc
decreases with an Increase in temperature,
maximum Icc values are not used.

THERMAL RESISTANCE
The ability of the package to conduct this
heat from the chip to the environment IS
expressed in terms of thermal resistance. The
term normally used is Theta JA (OJA)· OJA IS
often separated Into two components: thermal resistance from the junction to case, and
the thermal resistance from the case to
ambient. 0JA represents the total resistance
to heat flow from the chip to ambient and IS
expressed as follows:
OJC

+ OCA = OJA

JUNCTION TEMPERATURE (TJ)
Junction temperature (TJ) is the temperature
of a powered IC measured by Signetics at the

so LEADFRAME

DIP LEADFRAME

DIP LEADFRAME

b. PLCC-68 Leadframe Compared
to a 64-Pin DIP Leadframe

a. SO-14 Leadframe Compared
to a 14-Pln DIP Leadframe
Figure 1
February 1987

9-22

Signetics Unear Products

Thermal Considerations for Surface-Mounted Devices

substrate diode. When the chip IS powered,
the heat generated causes the TJ to nse
above the ambient temperature (TA)' T J IS
calculated by multiplying the power dissipation of the device by the thermal resistance of
the package and adding the ambient temperature to the result.
TJ = (Po

x I1JN + TA

FACTORS AFFECTING (}JA
There are several factors which affect the
thermal resistance of any IC package. Effective thermal management demands a sound
understanding of all these variables. Package
van abies include the leadframe design and
materials, the plastic used to encapsulate the
device, and, to a lesser extent, other variables such as the die size and die attach
methods. Other factors that have a slgmflcant
impact on the I1JA include the substrate upon
which the IC IS mounted, the density of the
layout, the air-gap between the package and
the substrate, the number and length of
traces on the board, the use of thermallyconductive epoxies, and external cooling
methods.
PACKAGE CONSIDERATIONS
Studies With dual in-line plastic (DIP) packages over the years have shown the value of
proper leadframe design in achieVing mlmmum thermal resistance. SMD leadframes
are smaller than their DIP counterparts (see
Figures 1a and 1b). Because the same die IS
used In each of the packages, the die-pad, or
flag, must be at least as large in the SO as In
the DIP.
While the size and shape of the leads have a
measurable effect on I1JA, the design factors
that have the most Significant effect are the
die-pad size and the tie-bar size. With design
constraints caused by both miniaturization
and the need to assemble packages In an
automated environment, the Internal design
of an SMD is much different than in a DIP.
However, the design IS one that strikes a
balance between the need to miniaturize, the
need to automate the assembly of the package, and the need to obtain optimum thermal
characteristics.
LEAD FRAME MATERIAL IS one of the more
important factors In thermal management.
For years, the DIP leadframes were constructed out of Alloy-42. These leadframes
met the producers' and users' specifications
in quality and reliability. However, three to five
years ago the leadframe matenal of DIPs was
changed from Alloy-42 to Copper (CLF) in
order to provide reduced IIJA and extend the
reliable temperature-operating range. While
thiS change has already taken place for the
DIP, it is still taking place for the SO package.
February 1987

Signetics began making 14-pin SO packages
With CLF in April 1984 and completed conversion to CLF for all SO packages by 1985. As
IS shown in Figures 10 through 14, the
change to CLF is producing dramatic results
In the I1JA of SO packages. All PLCCs are
assembled with copper leadframes.
The MOLDING COMPOUND is another factor
in thermal management. The compound used
by Signetics and Philips Is the same high
purity epoxy used in DIP packages (at present, HC-10, Type II). This reduces corrosion
caused by impurities and mOisture.
OTHER FACTORS often considered are the
die-size, die-attach methods, and wire bonding. Tests have shown that die size has a
minor effect on I1JA (see Figures 10 through
14).
While there is a difference between the
thermal resistance of the sliver-filled adhesive
used for die attach and a gold silicon eutectic
die attach, the thickness of thiS layer (1 - 2
mils) is so small it makes the difference
insigmficant.
Gold-wire bonding In the range of 1.0 to 1.3
mils does not provide a slgnHlcant thermal
path in any package.
In summary, the SMD leadframe is much
smaller than In a DIP and, out of necessity, IS
deSigned differently; however, the SMD package offers an adequate IIJA for all moderate
power devices. Further, the change to CLF
Will reduce the I1JA even more, lowering the TJ
and prOViding an even greater margin of
reliability.

Test Method
Signetics uses what is commonly called the
TSP (temperature-sensitive parameter) method. This method meets MIL-STD 883C, Method 1012.1. The basic Idea of this method IS to
use the forward voltage drop of a calibrated
diode to measure the change in junction
temperature due to a known power dissipation. The thermal resistance can be calculated using the follOWing equation:
~TJ TJ-TA
I1JA=-=-Po
Po

Test Procedure
TSP Calibration
The TSP diode is calibrated using a constanttemperature oil bath and constant-current
power supply. The calibration temperatures
used are typically 25°C and 75°C and are
measured to an accuracy of ± 0.1 °C. The
calibration current must be kept low to avoid
significant junction heating; data given here
used constant currents of either 1.0mA or
3.0mA. The temperature coeffiCient (K-Factor) is calculated using the following equation:
1
T2-TK- VF2- VF1

Where: K
T2
T1
VF2
VF1
IF

I

IF = Constant

=
=
=
=
=
=

Temperature CoeffiCient (OC/mV)
Higher Test Temperature (0C)
Lower Test Temperature (0C)
Forward Voltage at IF and T 2
Forward Voltage at IF and T1
Constant Forward Measurement Current
(See Figure 2)

SIGNETICS' THERMAL
RESISTANCE
MEASUREMENTS - SMD
PACKAGES
The graphs Illustrated In this application note
show the thermal resistance of Signetics'
SMD devices. These graphs give the relationship between I1JA Ounctlon-to-amblent) or I1JC
Ounction-to-case) and the device die size.
Data is also provided shOWing the difference
between still IlIr (natural convection cooling)
and air flow (forced cooling) ambients. All I1JA
tests were run with the SMD device soldered
to test boards. It IS important to recognize
that the test board IS an essential part of the
test environment and that boards of different
sizes, trace layouts, or composlllOns may give
different results from thiS data. Each SMD
user should compare hiS system to the
Signetics test system and determine if the
data is appropriate or needs adjustment for
hiS application.

9-23

Figure 2. Forward Voltage - Junction
Temperature Characteristics of a
Semiconductor Junction Operating at
a Constant Current. The K Factor Is
the Reciprocal of the Slope

Thermal Resistance
Measurement
The thermal resistance is measured by applying a sequence of constant current and
constant voltage pulses to the device under
test. The constant current pulse (same current at which the TSP was calibrated) is used
to measure the forward voltage of the TSP.
The constant voltage pulse is used to heat
the part. The measurement pulse IS very short

•

Signetics linear Products

Thermal Considerations for Surface-Mounted Devices

(less than 1% of cycle) compared to the
heating pulse (greater than 99% of cycle) to
minimize junction cooling during measurement. This cycle starts at ambient temperature and continues until steady-state conditions are reached. The thermal resistance
can then be calculated using the following
equation:
()JA = D.TJ = K(VFA - VFS)
PD
VH X IH
Where: VFA = Forward Voltage of TSP at Ambient Temperature (mV)
VFS

= Forward

Voltage of TSP at
Steady-State Temperature
(mV)

= Heating
= Heating
Test Ambient
VH

Voltage (V)

IH

Current (A)

()JA Tests
All ()JA test data collected In this application
note was obtained with the SMD deVices
soldered to either Philips SO Thermal Resistance Test Boards or Signetics PLCC Thermal Resistance Test Boards with the following parameters:
Board size

SO Small
1.12" X 0.75" X 0.059"
- SO Large:
1.58" X 0.75" X 0.059"
-PLCC:
2.24" X 2.24" X 0.062"

-

Board Material- Glass epoxy, FR-4 type
with 10z. sq. ft. copper solder coated
Board Trace Configuration - See Figure 3.
SO devices are set at 8 - 9mil stand-oil and
SO boards use one connection pin per device
lead. PLCC boards generally use 2 - 4 connection pins regardless of device lead count.
Figure 5 shows a cross-section of an SO part
soldered to test board, and Figure 4 shows
typical board/device assemblies ready for ()JA
Test.
The still-air tests were run in a box having a
volume of 1 cubic foot of air at room temperature. The air-flow tests were run in a 4" X 4"
cross-section by 26" long wind tunnel with air
at room temperature. All devices were
soldered on test boards and held In a horizontal test position. The test boards were held in
a Textcol ZIF socket with 0.16" stand-oil.
Figure 6 shows the air-flow test setup.
()JC Tests
The ()JC test is run by holding the test device
against an "infinite" heat sink (water-cooled
block approximately 4" X 7" x 0.75") to give

February 1987

a ()CA (case-to-ambient) approaching zero.
The copper heat Sink IS held at a constant
temperature (""20·C) and monitored with a
thermocouple (0.040" diameter sheath,
grounded juncllOn type K) mounted flush with
heat-sink surface and centered below die in
the test device. Figure 7 shows the ()JC test
mounting for a PLCC deVice.
SO devices are mounted with the bottom of
the package held against the heat sink. This
is achieved by bending the device leads
straight out from the package body. Two
small wires are soldered to the appropriate
leads for tester connection. Thermal grease
is used between the test deVice and heat Sink
to assure good thermal coupling.
PLCC devices are mounted with the top of
the package held against the heat sink. A

9-24

~TESI' DEVICE

n

~RTSTAN[)'OFF

TESI'BOARD
PLASTIC PIN
SUPPORT
CONNECTION
PINS

Figure 5. Cross-Section of Test Device
Soldered to Test Board
small spacer is used between the hold-down
mechanism and PLCC bottom pedestal.
Small hook-up wires and thermal grease are
used as with the SO setup. Figure 7 shows
the PLCC mounting.

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

so DEVICES

PL.CC DEVICES

4--AIRFlOW
~AIRFLOW

TESTDEVlCE

~

/ ,..--TESTBOARD
TEST BOARD srANo.oFF

_

TEXTOOLZIF SOCKET
_
SUPPORT

BOARD

SO Devices

Figure 7. OJC Test Setup
With PLCC Device

PLCC Devices
Figure 6. Air-Flow Test Setup

DATA PRESENTATION
The data presented in this application note
was run at constant power dissipation for
each package type. The power dissipation
used is given under Test Conditions for each
graph. Higher or lower power dissipation will
have a slight effect on thermal resistance.
The general trend of thermal resistance de·
creasing with increasing power is common to
all packages. Figure 8 shows the average
effect of power dissipation on SMD 0JA.

Example: Determine approximate junction
temperature of SOL-20 at 0.5W dissipation using 10,000 sq. mil die
and copper leadframe in still air and
200 LFPM air-flow ambients. Given
TA = 30°C,

Answer: 88°C/W

TJ = (OJA X PD) + TA
Where: TJ = Junction Temperature (0C)
OJA = Thermal Resistance Junctionto-Ambient (OC/W)
PD = Power Dissipation at a TJ
(Vee X leel (W)
TA = Temperature of Ambient (0C)

0.7W

From Figure 9: 200 LFPM air flow
gives 14% decrease in OJA
Answer:
91°C/W - (91 X 0.14) = 78°C/W

Percent change in Power

4. Calculate approximate junction
temperature

0.5W-0.7W
----X100
0.7W

Answer:
TJ (still-air)
= (91 °C/W X 0.5W) + 30
= 76°C
TJ (200 LFPM)
= (78°C/W X 0.5W) + 30
= 69°C

=-28.6%

EFFECTIVE RANGE
SO: 0.3 to 1.oW
PLOO o.Sto2.0W

c

The approximate junction temperature can be
calculated using the following equation:

@

3. Determine OJA @ 0.5W in 200
LFPM air flow from Average Effect of Air Flow on SMD OJA,
Figure 9.

2. Determine OJA @ 0.5W using Average Effect of Power Dissipation
on AMD OJA, Figure 8.

SO devices are currently available in both
copper or alloy 42 leadframes; however,
Signetics is converting to copper only. PLCC
devices are only available using copper leadframes.

Thermal Calculations

Answer:
88°C/W + (88 X 0.035)
= 91 °C/W @ 0.5W

1. Find OJA for SOL-20 using 10,000
sq. mil die end copper lead frame
from typical OJA data - SOL-20
graph.

Thermal resistance can also be affected by
slight variations in internal leadframe design
such as pad size. Larger pads give slightly
lower thermal resistance for the same size
die. The data presented represents the typical Signetics leadframe/dle combmations
with large die on large pads and small die on
small pads. The effect of leadframe deSign is
within the ± 15% accuracy of these graphs.

The average lowering effect of air flow on
SMD OJA is shown In Figure 9.

From Figure 8:
28.6% change in power gives
3.5% increase in OJA

07?

\

;!;

...

"z
""
"...z

1\r;;

l:

...
...r£A.

-2

c - 5

07?

i'

-4

~ -15

I'

-6

f--"If"'.......-i-c:.:.r;:.=;.

...;!; -10 I--'l-'tt--"'\;c-l-I-+-+-+-+iii - ~ 1--t-*,-f'~=I-+-"""""'-+­
~-251--t--r~-4~~~~

-8
-~-~-~o

~

~

~

~~1~1~

PERCENT CHANGE IN POWER

...

ffi -30 I--t--t--+~
A.-~j-+--t--t--¥-+~
-~

Figure 8. Average Effect of Power
Dissipation on SMD OJA

_~~~~~~~~~-L-L~

o

100

~

300

~

5DO &DO 700 &DO 9DO ~

AIR FLOW (LFPM)

Figure 9. Average Effect of Air Flow
on SMD OJA

February 1987

9-25

•

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

1}tpicall1JA DataSO-14 1

Typical 11JA Data SO-8 1
300

I-~

Ll4d ,- rrfH:r1
LJDFJAMi

Typicall1JA Data 50-16 1
300

300

250

250

I- ~

COPPER LEADFRAME

Lol42iLJDFJAMi

~'-

I-

r- ~EAriME
CbpP~R L~D~RAME

COPPER LEADFRAME

100

100

100

50

50

50

o

o
012345678910
DIE SIZE (SO MILS

o

012345618910

012345618910

DIE SIZE (SO MILS x 1000)

x 1000)

DIE SIZE (SO MILS x 1000)
01'024005

1}tplcall1JA Data SOL-16 2

1}tpicall1JA Data SOL-243

1}tpical 11JA Data 50L-20 3

300

300

300

250

250

250

-

....... ~LDY 42 LEADFRfME

~

100

100
COPiER LjDFRAiE
50

o

42 ~ADFR~ME

COPPER LEADFRAME

10

15

20

25

30

o

I---

COPPER LEADFRAME

50

50

o

ALLOY 42 LEADFRAME

100

o

o

10

15

20

DIE SIZE (SO MILS

DIE SIZE (SO MILS x 1000)

25

30

o

x 1000)

5

10

15

20

25

30

DIE SIZE (SO MILS x 1000)
0P02431S

NOTES:
1. TEST CONDITIONS,
Test ambient:

Typlcal8JA Data SOL-28 3
300

Stili air

Power dissipatIOn'

250

Accuracy

2. TEST CONDITIONS:

200

~ 150

05W
Philips PCB (1.58" x 0.75" X 0.059")
±15%

Accuracy.

""-

100

ALlOY

42 LEADFRAME,-- -

3. TEST CONDITIONS:
Test ambient.

o

Still alf

Power diSSipation:

COPPER LEADFRAME

50

o

Stili air

Test ambient.
Power dlsslpatton:
Test fixture.

iii

J

O.5W
Philips PCB (1 12" X 075" x 0059")
±15%

Test fixture'

O.7W
Philips PCB (1.58" X 0.75" X 0059")

Test fixture:
Accuracy

±15%

101520253035404550
DIE SIZE (SO MILS x 1000)

Figure 10. Typical 5MD Thermal (OJA) Characteristics

February 1987

9-26

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

Typical8JA Data PLCC·28 1

'IWllcal8JA Data PLCC·20 1
100

90

80

.......

70

!

-

Typical8JA Data PLCC·44 1

100

100

90

90

80
70

~

70

I'--r-

~ 80

80

80

1,,-

!

80

50

~ 50

"'~ 40

J40

J40

30

30

30

20

20

20

10

10

~

50

c

o

100

o
051015202530354045505560
DIE SIZE (SO MILS x 1000)

Typical 8JA Data PLCC-52 1
,-,.-,-,.....,....-r--.-,---.-,---,

901-I-H'"""-iHHH-l-l--1
801-I-HHHHH-l-l--1
701-I-HHHHH-l-l--1

10

Typlcal8JA Data PLCc-ea 2

1-+-+-+-+-+-+-+-++-1

90

801-l-l-<-l-l-HH'"""-i'"""-i-l
7OH'"""-i'"""-iHHH-l-l-l--1

70
80

~

50

TAB BONDED

",'"

40

WIRE BONDED

3O~r-+-+-~-r-r-+-+~~

3O~+-+-+-~-r-r-+-+~~

30

201-I-HHHHH-l-l--1
101-I-HHHHH-l-l-l

2O~+-+-+-~-r-r-+-+~~

20

10 ~+-+-+-~-r-r-+-+~~

10

0L-L-L-~~~~~~-J

o

0'--"--'--'--'--'--1..-'-......1.--'-'
o 10 20 30 40 50 80 70 80 90 100

o

10 20 30 40 50 80 70 80 90 100

NOTES:
1. TEST CONDITIONS:

Accuracy'

075W
Signetics PCB

±1S%

o

I I

10 20 30 40 50 60 70 80 90 100
DIE SIZE (sa MILS x 1000)

3. TEST CONDITIONS:

2. TEST CONDITIONS:
Stili air

(224"

I

DIE SIZE (SO MILS x 1000)

DIE SIZE (SO MILS x 1000)

Test ambientPower diSSipation'
Test fixture'

10 20 30 40 50 60 70 80 90 100
DIE SIZE (SO MILS x 1000)

80

!

~ 50 ~+-~-+-4--+-4--+~--H

o

Typical8JA Data PLCC-84 3
100

!8OH-t-+-++-+-+-t-H
J 4Or-t-t-~~-r~-*~~~

o

051015202530354045505580
DIE SIZE (SO MILS x 1000)

1OOr-r-r-r-r;r;r;-,-,-,
90

--

Test ambient
Power diSSipation
Test fixture

Stili air

Test ambient

lOW
Slgnetlcs PCB

Power diSSipation

15W

Test fixture

Slgnetlcs PCB

Accuracy.

(224" x 2.24" X 0062")
±15%

Accuracy.

x 224" x 0062")

Stili air

(2 24"

x 2 24" x 0 062")

±15%

Figure 11. Typical SMD Thermal (8JA) Characteristics

•
February 19B7

9-27

Signetics Unear Products

Thermal Considerations for Surface-Mounted Devices

1YPJcaI9JC Data SQ.14 1

Typlcal9JC Data SO-8 '
50
4S

I I I I I

40

Ccl....eR LEADFRAME

~

50

4S

4S

40

40

35

35

!"

!"

30

~20

15

15

10

10

10

o

012345678810

o

012345878910

DIE SIZE (SO MILS x 1000)

~ca19JC Data SOL·16 '

~19JCDataSOI.-243

~19JC Data SOL·Z02
50

50

4S

4S

4S

40

40

40

35

35

35

:

~ ""'":,"PER LEADFRAME -

i'
~

-

20

30 ~ ~PER LEADFRAME-

~

r--

2S

"

0;'20

~
",'4

25
20

15

15

10

10

10

o

10

15

20
2S
DlESIZE(SQ MILS x 1000)

30

o

o

o
10

15

20
25
DIE SIZE (SO MILS x 1000)

30

NOTES:
1. TEST CONDITIONS:

4S
40
35

(:

Test ftxture.

05W
"Infinite" heat smk

Accuracy

±15%

2. TEST CONDITIONS:
Power diSSIpatIOn'

07W

Power dlSSlpatlon

lYPlcal9JC Data SOI.-28 3
50

- ' ..... ;;;;;;,~PERLEADFRAME-

Test fIXtUre

"Inflnrte" heat 8tnk

Accuracy

±15%

3. TEST CONDI110NS:

-

Power dl8Slpatton.

lOW
"Irmnlte" heat Sink
±15%

Test fixture

~20

Accuracy

15
10

o

o

5

10 15 20 2S 30 35 40 4S 50

DIE SIZE (SO MILS x 1000)

.....""
Figure 12. Typical SMD Thermal (OJC) Characterlatics

February 1987

9-28

-

COPPER LEADFRAME

30

15

o

012345878910

DIESIZE(SQMILS x 1000)

DIE SIZE (SO MILS x 1000)

50

~

l - I- COPPER LEADFRAME l - f-

~:

30

15

oL-L.-L.-L.-L.-L.-L.-L.-L.-'--I

",'4

35

~

COPPER LEADFRAME

~ 25
(b~ 20

2S

"

"'~ 20

~

1YPIcal9JC Data SQ.16 '

50

o

10

15

20

2S

DIE SIZE (SO MILS x 1000)

30

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

~cal6JC Data PLCC-28 2

~cal 6JC Data PLCC-20 1

50

50

46

46

46

...

40
35

!

~
fD~

40

I'-

30
2S

35
~

..... -t--

~

30
25

40

35

!'\.

!

I'
..........

30

~ 25

20

"'~ 20

~20

15

15

15

10

10

10

o

"

o

051015202530354046505580
DlESlZE(SQMILS x 1000)

Typical6JC Data PLCC-52 2

o

051015202530354046505580
DIE SIZE (SQ MILS x 1000)

50

46~~~~~~~~~-;

46

46

4O~~+-4-4-~-+-+-4~~

40

40

35~~+-4-4-~-+-+-4~~

35

35

20 1-+-4-~-+--f-f-+--4-~--1

!

~
fil:>~

~

30
26

"

15

1O~+-+-4--r~-+-+--f-l-l

10

O~~~~~~~~~~

o

:

"'~ 20

20

15H---f-f""'l'"++*;;j::::;j;;;;;j

0102030405080708090100
DIE SIZE (SQ MILS x 1000)

o

-

10 20 30 40 50 80 70 80 90 100
DIE SIZE (SQ MILS x 1000)

~16JC Data PLCC-84 3

50

~ 25~~~+-+-+-+-4-4-4-~

......

~16JC Data PLCC-611 3

5O~r-~~~~~~-'-'

~30I-I-I-I-I--HH---I---I-I

J

'IWIlcal6JC Data PLCC-442

50

~

15

TAB BONDED

wlRElwN~EDf- ,.-.;;;

10

0102030405080708090100
DIE SIZE (SQ MILS x 1000)

o

0102030405080708090100
DIE SIZE (SQ MILS x 1000)

NOTES:
1. TEST CONDITIONS:
Power dlsslpabon
Test fixture

Accuracy

075W
"lnfIMlte" heat sink
±15%

2. TEST CONDITIONS:
Power dlsslpabon

Test fixture
Accuracy

lOW
"Infinite" heat sink
±15%

3. TEST CONDITIONS:
Power dlsslpabon
Test fixture
Accuracy

20W

"Infinite" heat sink
±15%

Figure 13. Typical SMD Thermal (8Jc) Characteristics

•
February 1987

9-29

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

Effect of Device Stand-Off
on SO OJA 1

sa

Effect of Board Size
on SO OJA 2

Effect of Trace Length on
28-Lead PLCC 0JA 3

220

87

95
90

210

,

86
200

86

~

84

~

83

"'~

82

..

~
~

"'~

81

_-r-

80
79

85

,

1--

160

78

345

6

7 8

9 W

~

~ ~ ~

Ole sIZe
Test Ambient
Power diSSipation
Test forture

SOL-20 elF
11,322sq mils
Sttll-atr

075W
Phillips PCB

\

70

\

r-... r--..

60

55
01234567

9

10

BOARD SIZE (SO IN)
NOTES:
2. TEST CONDITIONS
Package type
Ole size
Test Ambient
Power diSSipation
Test fIxture

SOL-14 eLF
5,040sq mils
StlU-alr

06W
o 062" thIck PCB with
"no traces" 8 - gmtl
stand-off

(1 58" X 075" X 0059")

Figure 14

February 19B7

\

75

65

150
~

DEVICE STAND-OFF (MILS)
NOTES:
1. TEST CONDITIONS
Package type

170

80

9-30

o

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
AVERAGE TRACE LENGTH (INCHES)

NOTES:
3. TEST CONDITIONS
Package type
Ole Size
Test Ambient
Power dlSSlpatron.
Test fixture

PLCC-2B eLF
10,445sq mils
Stili-SIr

10W
Signetics PCB

(224" X 224" X 0062")
trace 27mll-wlde 10z sq It
copper

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

SYSTEM CONSIDERATIONS
With the increases in layout density resulting
from surface mounting with much smaller
packages, other factors become even more
important. THE USER IS IN CONTROL OF
THESE FACTORS.
One of the most obvious factors IS the
substrate material on which the parts are
mounted. Environmental constraints, cost
considerations, and other factors come into
play when choosing a substrate. The chOice
is expanding rapidly, from the standard glass
epoxy PWB materials and ceramic substrates
to flexible circuits, injection-molded plastiCS,
and coated metals. Each of these has its own
thermal characteristics which must be considered when choosing a substrate material.

~

...

200

f-H-+-+-+-++++-1

'50

H-++-H-+-+-+-1H

~

...

'10

STU A
200LFPU

~ -Lf".!'- r400LFPM

~ 100

50

~,A.""~~~
4OOLFPM-:;:'

'riM,"

o~~-L-L~~~-L~

•o

012345878910
DIE SIZE (SO MLS x 1000)

•

•

u u •

~

"

H H

DE SIZE (80 MLb '000)

Figure 15. Results of Air Flow on 8JA
on SO-14 With Copper Leadframe

Studies have shown that the air gap between
the bottom of the package and the substrate
has an effect on 8JA. The larger the gap, the
higher the 8JA• Using thermally conductive
epoxies in this gap can slightly reduce the

3

Figure 16. Results of Air Flow on 8J A
on SOL-16 With Copper Leadframe

250

210

200

200

8JA.

It has long been recognized that external
cooling can reduce the junction temperatures
of devices by carrying heat away from both
the devices and the board itself. Signetics
has done several studies on the effects of
external cooling on boards w~h SO packages. The results are shown in Figures 15
through 18.
The designer should avoid close spacing of
high power devices so that the heat load is
spread over as large an area as possible.
Locate components WIth a higher junction
temperature In the cooler locanons on the
PCBs.
The number and size of traces on a PWB can
affect 8JA since these metal lines can act as
radiators, carrying heat away from the package and radiating it to the ambient. Although
the chips themselves use the same amount
of energy in e~er a DIP or an SO package,
the increased density of a surface-mounted
assembly concentrates the thermal energy
into a smaller area.
It is evident that nothing is free in PWB layout.
More heat concentrated Into a smaller area
makes it incumbent on the system designer
to provide for the removal of thermal energy
from hiS system.
Large conductor traces on the PCB conduct
heat away from the package faster than small
traces. Thermal vias from the mounting surface of the PCB to a large area ground plane
in the PCB reduce the heat bUildup at the
package.
In addition to the package's thermal conSiderations, thermal management requires one to
at least be aware of potential problems
caused by mismatch in thermal expansion.
February 1987

~

...

'50

50

t-

v~TU.-

-

--rSTU AIR
200LFPM
4CJOLFPII
100 LFPM

v:

400LFPU
~ V~LFPU
IOOLFPU
r-r-' t- -.

~,oo

;,..10

~

o

o

01234587.910
DIE SIZE (SO MLS. '000)

o

3

• • U 15 g ~ K H
DE SIZE (8Q . . . . . ,000)

H
OP02711S

Figure 17. Results of Air Flow on 8JA
on SO-16 With Copper Leadframe

Figure 18. Results of Air Flow on 8JA
on SOL-20 With Copper Leadframe

The very nature of the SMD assembly, where
the deVices are soldered directly onto the
surface, not through it, results in a very rigid
structure. If the substrate matenal exhibits a
different thermal coefficient of expansion
(TCE) than the IC package, stresses can be
set up In the solder joints when they are
subjected to temperature cycling (and during
the soldering process itself) that may Ultimately result in failure.

The stress level asSOCiated with thermal expansion and contraction of small SMDs such
as capacitors and resistors, where the actual
change in length is small, is normally rather
low. However, as component sizes increase,
stresses can increase substantially.

Because some of the boards assembled Will
require the use of Leadless Ceramic Chip
Carriers (LCCCs), TCE must be understood.
As will be seen below, TCE is less of a
problem with the commercial SMD packages
w~h leads.
Take the example of a leadless ceramic chip
carrier WIth a TCE of about 6 x 10 - 6 fOC
soldered to a conventional glass-epoxy laminate With a TCE In the region of 16 X 10 ·C. This thermal expansion mismatch has
been shown to fracture the solder jOints
dunng thermal cycling. Substrate materials
with matched TCEs should be evaluated for
these SMD assemblies to aVOid problems
caused by thermal expansion mismatch.

6,

9-31

Thermal expansion mismatch is unlikely to
cause too many problems in systems operating In benign environments; but, in harsher
conditions, such as thermal cycling in mil~
or aVionic applications, the mechanical
stresses set up In solder jOints due to the
different TCEs of the substrate and the.component are likely to cause failure.
The baSIC problem IS outlined In Figure 19.
The leadless SMD is soldered to the substrate as shown, resulting In a very rigid
structure. If the substrate material exhibits a
different TCE from that 01 the SMD material,
the amount of expansion for each will differ
for any given increase in temperature. The
soldered jOint will have to accommodate this
difference, and failure can ultimately result.
The larger the component Size, the higher the
stress levels so that this phenomenon is at its

•
•

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

most critical in applications requiring large
LGGGs with high pin counts.
TCEOFSMD=6 x 10- 4%/K

j

~

2

SMD

~i

SUBSTRATE

TCE OF SUBSTRATE = 16 x 10 4%/K

S

NOTE:
Data provided by N V. Philips

Figure 19. The Basic Problem of
Thermal Expansion Mismatch Is That
the Substrate and Component May
Each Have Different Thermal
Coefficients of Expansion

To address this problem, three basic solu·
tions are emerging. First, the use of leadless
ceramic chip carriers can sometimes be
avoided by using leaded deVices; the leads
can flex and absorb the stress. Second, when
this solution is not feasible, the stresses can
be taken up by inserting a compliant elasto·
meric layer between the ceramic package
and the epoxy glass substrate. Third, TGE
values of component and substrate can be
matched.

USING LEADED DEVICES
(SO, SOL, and PLCC)
The current evolution in commercial electron·
ics includes the adoption of the commercial
SMD packages, i.e., SO with gull,wlng leads
or the PLGG with rolled-under J-Ieads, rely on
the compliance of the leads themselves to
avoid any serious problems of thermal expansion mismatch. At elevated temperatures, the
leads flex slightly and absorb most of the
mechanical stress resulting from the thermal
expansion differentials.
Similarly, leaded holders can be used with
LGGGs to attach them to the substrate and
thus absorb the stress.
Unfortunately, using a lead does not always
ensure sufficient compliancy. The material
from which the lead IS made, and the way it is
formed and soldered can adversely affect it.
For example, improper soldering techniques,
which cause excess solder to over-fill the
bend of the gull-wing lead of an SO, can
significantly reduce the lead's compliancy.

COMPLIANT LAYER
This approach introduces a compliant layer
onto the Interface surface of the substrate to
absorb some of the stresses. A 50llm thick
elastomeric layer is bonded to the laminate.
To make contacts, carbon or metallic powders are introduced to form conductive
February 1987

stripes in the nonconductive elastomer material. Unfortunately, substrates using this technique are substantially more expensive than
standard uncoated boards.
Another solution is to increase the compliancy of the solder joint. This is done by increasing the stand-off height between the underside of the component and the substrate. To
do this, a solder paste containing lead or
ceramic spheres which do not melt when the
surrounding solder reflows, thus keeping the
component above the substrate, can be
used.

MATCHING TCE
There are two ways to approach this solution.
The TGE of the substrate laminate material
can be matched to that of the LGGG either by
replacing the glass fibers with fibers exhibiting
a lower TGE (composites such as epoxyKevlar®or polYlmlde-Kevlar and polyimidequartz), or by using low TGE metals (such as
Invar®, Kovar, or molybdenum).
This latter approach involves bonding a glasspolyimide or a glass-epoxy multilayer to the
low TCE restraining core material. Typical of
such materials are copper-Invar-copper, AIloy-42, copper-molybdenum-copper, and copper·graphite. These restraining-core constructions usually require that the laminate be
bonded to both sides to form a balanced
structure so that they will not warp or twist.
This ineVitably means an increase in weight,
which has always been a negative factor in
this approach. However, the SMD substrate
can be smaller and the components more
densely packed, in many cases overcoming
the weight disadvantages. On the positive
Side, the material's high thermal conductivity
helps to keep the components cool. Moreover, copper-clad Invar lends itself readily to
moisture-proof multilayering for the creation
of ground and power planes and for providing
good inherent EMI/RFI shielding.
Kevlar IS lighter and Widely used for substrates in military applications; but, It suffers
from a serious drawback which, although
overcome to a certain extent by careful attention to detail, can cause problems. The material, when laminated, can absorb moisture
and chemical processing flUids around the
edges. Thermal conductivity, machinability,
and cost are not as attractive as for copperclad Invar.
For the majority of commercial substrates,
however, where the use of ceramic chip
carriers in any quantity is the exception rather
than the rule, and when adequate cooling is
available, the mismatch of TCEs poses little
or no problem. For these substrates, traditional FR-4 glass-epoxy and phenolic-paper will

9-32

no doubt remain the most widely-used materials.
Although FR-4 epoxy-glass has been the
traditional material for plated-through professional substrates, it is phenolic-paper laminate (FR-2) which finds the widest use in
consumer electronics. While It is the cheapest material, it unfortunately has the lowest
dimensional stability, rendering it unsuitable
for the mounting of LCCCs.

SUBSTRATE TYPES
FR-4 glass-epoxy substrates are the most
commonly used for commercial electronic
circuits. They have the advantage of being
cheap, machinable, and lightweight. Substrate size is not limited. On the negative side,
they have poor thermal conductivity and a
high TCE, between 13 and 17 x 1O- 6/,C.
This means they are a poor match to ceramic.
Glass polyimide substrates have a similar
TCE range to glass-epoxy boards, but better
thermal conductivity. They are, however,
three to four times more expensive.
Polyimide Kevlar substrates have the advantage of being lightweight and not restricted in
size. Conventional substrate processing
methOds can be used and ItS TGE (between 4
and 8), matches that of ceramic. Its disadvantages are that it is expensive, difficult to drill,
and is prone to resin microcracking and water
absorption.
Polyimide quartz substrates have a TCE between 6 and 12, making them a good match
for LCCCs. They can be processed using
conventional techniques, although drilling
vias can be difficult. They have good dielectric properties and compare favorably with
FR-4 for substrate size and weight.
Alumina (ceramic) substrates are used extensively for high-reliability military applications
and thick-film hybrids. The weight, cost, limited substrate size and inherent brittleness of
alumina means that its use as a substrate
material is limited to applications where these
disadvantages are outweighed by the advantage of good thermal conductivity and a TCE
that exactly matches that of LCGCs. A further
limitation is that they require thick-film screening processing.
Copper-clad Invar substrates are the leading
contenders for TCE control at present. It can
be tailored to provide a selected TCE by
varying the copper-to-Invar ratio. Figure 20
shows the construction of a typical multilayer
substrate employing two cores providing the
power and ground planes. Plated-through
holes provide an Integral board-to-board interconnection. The low TCE of the core
dominates the TCE of the overall substrate,

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

making it possible to mount LCCCs with
confidence.
Because the TCE of copper is high, and that
of Invar is low, the overall TCE of the substrate can be adjusted by varying the thick-

ness of the copper layers. Figure 21 plots the
TCE range of the copper-clad Invar as a
function of copper thickness and shows the
TCE range of each of several other materials
to which the clad material can be matched.

For example, if the TCE of Alumina is to be
matched, then the core should have about
46% thickness of copper. When this material
is used as a thermal mounting plane, it also
acts as a heatsink.

----------------;;, ,
't;r,i"~~r:fu;~~:r21~~~
-----------------

NOTE:
Data provided by N. V Phlhps

Figure 20. Section Through a Typical Multilayer Substrate Incorporating Copper-Clad Invar Ground and
Power Planes, Interconnected via Plated-Through Holes

12
~

il+
s

10

12

/

I

~
I

12

/V

x

t'"
w

1:1

/

/

ro
o

V
20

40

60

80

100

PERCENT THICKNESS OF COPPER
CLADINVAR

NOTE:

Data provided by N V Phlhps

Figure 21. The TCE Range of Copper-Clad Invar as a Function of Copper Thickness

•
February 1987

9-33

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

Table 1. Substrate Material Properties
TCE (1o- 6 rC)

THERMAL CONDUCTIVITY (W/m 3K)

Glass-epoxy (FR-4)

13-17

0.15

Glass polYlmlde

12-16

0.35

Polyimlde Kevlar

4-6

0.12

PolYlmlde quartz

6-12

TBD

6.4 (typical)

165 (lateral)
16 (transverse)

SUBSTRATE MATERIAL

Copper-clad Invar
Alumina
Compliant layer
Substrate

5-7

21

See Notes

0.15-0.3

NOTES:
Compliant layer conforms to TCE of the LCCC and to base substrate matenal
Data provided by N V Philips
KEVLAR® IS a registered trademark of DU PONT.
INVAR® IS a registered trademark of TEXAS INSTRUMENTS

CONCLUSION
Thermal management remains a malor concern of producers and users of ICs The
advent of SMD technology has made a thorough understanding of the thermal character-

February 1987

Istics of both the devices and the systems
they are used in mandatory. The SMD package, being smaller, does have a higher (JJA
than Its standard DIP counterpart ... even
With copper leadframes. That is the major
trade-off one accepts for package mlnlatur-

9-34

izatlon. However, conSideration of all the
variables affecting IC junction temperatures
will allow the user to take maximum advantage of the benefits derived from use of this
technology.

Package Outlines

Signetics

For Prefixes ADC, AM, AU, CA,
DAC, ICM, LF, LM, MC, NE, SA,
SE, SG, pA, UC
Linear Products

INTRODUCTION

PLASTIC ONLY

The following information applies to all packages unless otherwise specified on individual
package outline drawings.

5.

GENERAL
1.

2.

3.
4.

Dimensions shown are metric units (millimeters), except those in parentheses
which are English units (inches).
Lead spacing shall be measured within
this zone.
a. Shoulder and lead tip dimensions are
to centerline of leads.
Tolerances non-cumulative.
Thermal resistance values are determined by utilizing the linear temperature
dependence of the forward voltage drop
across the substrate diode in a digital
device to monitor the junction temperature rise during known power application
across Vee and ground. The values are
based upon 120mils square die for plastic
packages and a 90mils square die in the
smallest available cavity for hermetic
packages. All units were solder-mounted
to PC boards, with standard stand-off, for
measurement.

6.
7.
8.
9.

Lead material: Alloy 42 (NIckel/Iron Alloy), Olin 194 (Copper Alloy), or equivalents, solder-dipped.
Body material: PlastIc (Epoxy)
Round hole in top corner denotes lead
No.1.
Body dimensions do not include molding
flash.
SO packages/mIcrominiature packages:
a. Lead material: Alloy-42.
b. Body material: Plastic (Epoxy).

HERMETIC ONLY
10. Lead material
a. ASTM alloy F-15 (KOVAR) or equivalent - gold-plated, tin-plated, or solder-dIpped.
b. ASTM alloy F-30 (Alloy 42) or equivalent - tin-plated, gold-plated or solder-dipped.
c. ASTM alloy F-15 (KOVAR) or equivalent - gold-plated.

11. Body Material
a. Eyelet, ASTM alloy F-15 or equivalent - gold- or tin-plated, glass body.
b. Ceramic WIth glass seal at leads.
c. BeO ceramic with glass seal at leads.
d. Ceramic with ASTM alloy F-30 or
equivalent.
12. Lid Material
a. Nickel- or tin-plated nickel, weld seal.
b. Ceramic, glass seal.
c. ASTM alloy F-15 or equivalent,
gold-plated, alloy seal.
d. BeO ceramic with glass seal.
13. Signetics symbol, angle cut, or lead tab
denotes Lead No.1.
14. Recommended minimum offset before
lead bend.
15. Maximum glass climb 0.010 inches.
16. Maximum glass climb or lid skew is 0.010
inches.
17. Typical four places.
18. DImensIon also applies to seating plane.

•
December 1988

9-35

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

PLASTIC PACKAGES
DESCRIPTION

PACKAGE CODE

PACKAGE TYPE

()JA/()JC ("C/W)

Standard Dual-in-Line Packages
8-Pin
14-Pin
16-Pin
18-Pin
20-Pin
22-Pin
24-Pin
28-Pin

N
N
N
N
N
N
N
N

110/49
90/46
90/46
79/36
79/35
56/23
58/30
56/30

E
E
H
H
H

100/20
150/25
150/25
150/25
150/25

TO-46 Header
TO-72 Header
TO-5 Header
TO-5/TO-100 Header, Short Can
TO-5/TO-100 Header, Tall Can

FE
F
F
F
F
F
F
F

162/26
109/26
105/26
88/22
85/22
75/13
65/16
62/16

Dual-m-Line
Dual-In-Llne
Dual-in-Llne
Dual-In-line
Dual-In-Llne
Dual-m-Llne
Dual-in-Llne
Dual-In-Line

I

90/25

DIP Laminate

TO-116/MO-001
MO-001

MO-015
MO-015

Metal Headers
4-Pin
4-PIn
8-Pin
10-Pin
10-Pin
Cerdip Family
8-Pin
14-Pin
16-Pin
18-Pin
20-P,n
22-Pin
24-Pln
28-Pin

Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic

Laminated Ceramic, Side-Brazed Lead
16-Pin

a-PIN PLASTIC SO (0 PACKAGE)
NOTES:
1 Package dimensions conform to JEDEC specification
MS-012-AA for standard small outhne (SO) package, 8
leads, 375mm (150") body width (Issue A, June 1985)
2 Controllmg dimensions are In mm Inch dimensions In
parentheses
3 Dimensions and toleranclng per ANSI Y145M-19B2
4 "T", "D" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (006") on
any Side
5 Pin numbers start with pin # 1 and continue
counterclockwise to pin #8 when viewed from top
6 Signetics ordering code for a product packaged In a
plastic small outline (SO) package IS the suffix Dafter
the product number

D® 10 (004)

1--+---j-1 27
r;;-:,

t:E..:Ji-----+-

[T]

19 .10

(050)

sse

5.00 (197)
4.80 (.189)

L
--l

6HHnH
(.00~1 I
~.49 (019)
.35 (014)

r
(061, 006)
155:1: 20

25 (010)

~.~~

I

25(010)
19 (007)

853·0174 88070

December 1988

50 (020) x45"

9-36

(007,003)
180 ± 07

8'

(025 ± 006)
635 ± 15

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

14-PIN PLASTIC SO (0 PACKAGE)
• D®

NOTES:
1 Package dimenSions conform to JEDEC speCificatIOn
MS-012·AB for standard small outhne (SO) package, 14
leads, 3 75mm (150") body width (Issue A, June 1985)
2 Controlling dimenSions are In mm Inch dimenSions In
parentheses
3 Dimensions and toleranclng per ANSI Y14 SM· 1982
4 "T". "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions. Mold
flash or protrusions shall not exceed 15mm (006") on
any Side
5 Pin numbers start with pin # 1 and continue
counterclockwise to pm # 14 when viewed from top
6 SlgnetICs ordenng code for a product packaged In a
plastic small outline (SO) package IS the suffix Dafter
the product number

10 (.004)

t

(.236:1: 006)

4.00 (.157)

---s;]5

8"

(061dlO8)

m

~

1ClI.'0(.~
.49 (.019)
.35 (.014)

-j.IT IE ID®I

25 (010) @

I

25 (.010)
19 (007)

(.007 ±.O03)
.180:t: 07

853-0175 88068

16-PIN PLASTIC SO (0 PACKAGE)
~flD®I.'0

i

(004)

f---J

NOTES,
1 Package dimenSions conform to JEDEC specification
MS·QI2·AC for standard small outline (SO) package, 16
leads, 375mm (150") body width (Issue A, June 1985)
2 Controlling dimenSions are In mm Inch dimenSions In
parentheses
3 DimenSions and toleranc.ng per ANSI Y14 SM· 1982
4 "T", "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (006") on
any Side
5 Pin numbers start with p.n #1 and continue
counterclockwise to pro # 16 when viewed from top
6 Signetics ordering code for a product packaged In a
plastiC small outline (SO) package IS the suffiX 0 after
the' product number

1----.-

1

(236 ± 006)
~

I.IE®I

25 (010)

®I

lr

.50 (020) x45"
.25 (010)

8"

~~-$

J:~)
19 (007)

853-0005 88069

December 1988

9-37

180:t: .07

J

L(·025

± 006)
635:t: 15

•

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, IF, lM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

16-PIN PLASTIC SOL (0 PACKAGE)

~,

NOTES:

1 Package dimensions conform to JEDEC specification
MS-013-AA for standard small outline (SO) package, 16
leads, 750mm (300") body width (Issue A, June 1985)
2 Controlling dimensions are In mm Inch dimenSions In
parentheses
Dimensions and tolerancmg per ANSI Y14 5M- 1982
"1", "D" and "E" are reference datums on the molded

:

~~~

body and do not Include mold flash or protrusions Mold

flash or protrusions shall not exceed 15mm (006") on
any side
5 Pin numbers start With pin # 1 and continue
counterclockwise to pin # 16 when viewed from top
6 Signetlcs ordenng code for a product packaged In a
plastic small outline (SO) package IS the suffix Dafter
the product number

1065 (419)
1026 (.404)

740 (291)

,.IE®I

I

25 (010)

®I

EEl

I

lr

U , 2 7 (060) SSC

-D-r-----~----- ~~~:;~~

75 (030) X45"
50 (020)

~I~

30 (012)
23 (009)

10 (004)

086 (034)

853·0171 81218

20-PIN PLASTIC SOL (0 PACKAGE)
~~O®I

.10 (.004)

I

NOTES:

11

I

1065 (419)

7.60 (.299)

10,26 (404)

740(291)

I

.!E@I 25 (010) @

m
I

U'27

I

1 Package dimenSions conform to JEDEC specification
MS-013-AC for standard small outline (SO) package, 20
leads, 750mm (300") body width (Issue A, June 1985)
2 Controlling dimenSions are In mm Inch dimenSions m
parentheses
3 DimenSions and toleranclng per ANSI Y145M-1982
4 "T", "D" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (006") on
any side
5 Pm numbers start With pm # 1 and continue
counterclockwise to pin #20 when viewed from top
6 Signetics ordering code for a product packaged In a
plastiC small outline (SO) package IS the suffix Dafter
the product number

(060) BSC
13.00 (.512)
1260 (.496)

-D-r-----+--------'-'T

I~ I

I¢l

10 (.004)

~
ILDJJlJl1DJ][]l

I
----l

I

L

.49 (019)
35 (.014)

>--<=-___-1-1

-i+'T'E:O®1

25 (010)@
===:.:!...C"'-'

'-'.,",'-'-L=.

853-0172 81219

December 1988

8"

265\'04)
235 (093)

9-38

32 (013)

30 (012)

1 07 (042)

23 (009)

10 (004)

86 (034)

~

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

24-PIN PLASTIC SOL (D PACKAGE)
NOTE6:
1 Package dimenSions conform to JEDEC spsClflcabon
M8-013-AD for standard small outline (SO) package, 24
leads, 750mm (300") body Width (Issue A, June 1985)
2 Controllmg dimenSIOns are In mm Inch dimenSions In

II

I

parentheses
3 DimenSIons and tolerancmg per ANSI Y145M-1982

4 "T" "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protruSions shall not exceed 15mm (006") on
any Side
5 Pin numbers start wrth pin # 1 and continue
counterclockwise to pm #24 when Viewed from top
6 SlgnetlCs ordenng code tor a product packaged In a
plastIC small outline (SO) package IS the sufflx Dafter
the product number

1065 (419)

~

1026 (404)

740 (291)

dJ

!fIE ®I 25 (010) ® I

I

-0-+----+-----

l

15.60 (614)
15.20 (.598)

I

191

.10 (.004)

I
---l

1

r

·75 (.030) X45·
50 (020)

~

265 (104)

L

235 (093)

t
.49
«.00 '9))
.35 . 14

-1...1T I E 10 ®I .25 (.010)@

I

32 (013)

.30 (.012)

107 (.042)

23 (.009)

10 (004)

.86 (.034)

853-0173 81220

28-PIN PLASTIC SOL (0 PACKAGE)
NOTE6:
1 Package dimenSIons conform to JEOEC speclilcabon
MS-013-AE for standard small outline (SO) package, 28
leads, 750mm (300") body Width (Issue A, June 1985)
2 Controlling dimenSions are In mm Inch dimenSIons In
parentheses
3 DimenSions and toleranclng per ANSI Y145M-1982
4 "T", "0" and "E" are reference datums on the molded
body and do not Include mold flash or protruSIOns Mold
flash or protrusions shall not exceed 15mm (006") on
any side
5 Pm numbers start with pm #1 and continue
counterclockWise to pm #28 when Viewed from top
6 SlgnetlCs ordenng code for a product packaged In a
plastIC small outline (SO) package IS the suffiX 0 after
the product number

1+10(1)1'0 (004) I

r

18.10 (.713)
1770 (.697)

-0-

75 (030) X45·

50 (020)

t

§

10(004)1

I
---l

L

265 (104)
235 (093)

.:: :.~::: -ttl

32 (013)
23 (009)

TIE 10®1 25 (.010) @ I

853-0006 81217

December 1988

~~'--------' -I"''l--=~

I

9-39

30 (012)
10 (.004)

1 07 (042)
86 (034)

•

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

4-PIN HERMETIC TO-72 HEADER (E PACKAGE)

:~A

~~ ~076'030IMAX
+
533 (210)
432 ( 170)

1422 I

5601m11
00 I

"'i2ToTSOOi

4 LEADS

048(019~

•

584(23~

0ii"'i'0i6i

531 {209}DIA

8-PIN CERDIP (FE PACKAGE)

I l

NOTES:
1 Controlling dimenSion Inches. Millimeters are shown In
parentheses.
2 DimenSions and toleranclng per ANSI Y14.SM - 1982
:3 "T", "D", and "E" are reference datums on the body

055 (140)
030 (.76)

and mclude allowance for glass overrun and meniscus on
the seal hne, and lid to base mIsmatch
4 These dimenSions measured with the leads constrained
to be perpendicular to plane T.
5 Pin numbers start with pm # 1 and contmue
counterclockwise to pin #8 when viewed from the top.

~

JL.oZl

(.56)--ttITIE
.015 (.36)

lo®1

~-I

OlD (254)

ij
30g~62) ~
(NOTE 4)
t395 (1003)

300 (7.62)

853-0580 81594

December 1988

H

9-40

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

14-PIN CERDIP (F PACKAGE)
NOTES:
1 Controlling dimension Inches Millimeters are shown In
parentheses
2 Dimensions and tolerancmg per ANSI Y14 5M - 1982
3 tiT", "D", and "E" are reference datums on the body
and Include allowance for glass overrun and memscus on
the seal hne, and lid to base mismatch
4 These dimensions measured with the leads constrained
to be perpendicular to plane T
5 Pm numbers start with pin #1 and conbnue
counterclockwise to pin # 14 when Viewed from the top

110 (279)

050 (1 27)

320 (813)

rr 290

(7 37)

(NOTE 4)

,:

JL ~:

1
I

:J~
"

!

30&~9 62)
-i (NOTE
4)
t-

~

:::---i!lTI elo®1 010 (254)

395 (1003)
300 (762)

853-0581 81594

16-PIN CERDIP (F PACKAGE)
NOTES:
1 Controllmg dimenSion Inches Millimeters are shown In
parentheses
2 DimenSions and tolerancmg per ANSI Y145M - 1982
3 "T", "0", and "E" are reference datums on the body
and mclude allowance for glass overrun and meniscus on
the seal Ime, and lid to base mismatch
4 These dimenSions measured with the leads constrained
to be perpendicular to plane T
5 Pin numbers start with pm # 1 and continue
counterclockWIse to pm # 16 when viewed from the top

~

JL,~~

!

C

(NOTE 4)

395 (1003)

:.:::-@Tielo®1010(254)

300 (76.2)

853-0582 81594

December 1988

~

300(7 62) BSC:J

9-41

f-

•

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

18-PIN CERDIP (F PACKAGE)
NOTES:
1 Controlling dimenSIon: Inches. Millimeters are shown in
parentheses
2. Dimensions and toleranclng per ANSI Y14.SM - 1982.
3. "T", "0", and "E" are reference datums on the body

098 (2.49)

1

012 (30)

and Include allowance for glass overrun and meniscus on
the seal hne, and lid to base mismatch.
4. These dimenSions measured With the leads constraIned
to be perpendicular to plane T.
5. Pin numbers start with pm #1 and continue
counterclockWIse to pin # 18 when viewed from the top.

rr

JL

320 (813)

290

(737)~

(NOTE 4)
, :

i"

I

C
--t

023 (.58)-ff9\ T 1elo@j.o,o (.254)
.0'5 (.38)

300esc
(7 62)
(NOTE 4)

t-~

395 (10;)
300 (7.

853-0583 81594

20-PIN CERDIP (F PACKAGE)

f--

.078 (' .98)

1

.0'2 (.30)

1

r

078('.98)

NOTES:

1 Controllmg dimenSion: Inches. Millimeters are shown In
parentheses.
2. DimenSions and toleranclng per ANSI Y14.5M - 1982.
3 "T", "0", and "E" are reference datums on the body
and Include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4 These dimenSions measured with the leads constrained
to be perpendicular to plane T.
5 Pin numbers start with pin # 1 and conllnue
counterclockwise to pin #20 when Viewed from the top.

0'2 (30)

~-~~~~~~~~
306 (7.77)

l.---.,oo

(2.54)

esc

.975 (2473)
.940 (23.88)
r.058 ('.47)

.070 ('78)

I

050 ('27)

.030 (.76)

H
035 (.89)

'0:)L0
(.5')'
1

-i

J L ' 0 2 3 (.58)-1$1
.0'5 (.38)

0'5 (.38)
0'0 (25)

T! E !o@j,o,o (.254)

853-0584 81594

December 1988

9-42

:!
!!

H

1-1
I---

esc

300 (7 62)
(NOTE 4)
.395 ('0.03)
300 (7 62)

11

I--

-'=l

Signetics Linear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, pA, UC

Package Outlines

22·PIN CERDIP (F PACKAGE)
NOTES,
1, Controlling dimension Inches Millimeters are shown In

parentheses
Dimensions and toleranclng per ANSI Y145M - 1982
"T", "0", and "E" are reference datums on the body
and Include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch
4 These dimensions measured with the leads constrained
to be perpendIcular to plane T
5 PIn numbers start with pin # 1 and continue
counterclockwise to pm #22 when viewed from the top

:To.,
070 (178)
050 (127)

JL

023

(.58)-1$ITleID®1 010 (254)

015 (.38)

853-0585 81594

24·PIN CERDIP (F PACKAGE)
NOTES,
1 Controlling dImension Inches Mtlhmeters are shown In

parentheses
Dimensions and toleranclng per ANSI Y145M - 1982
"T", "0", and "E" are reference datums on the body
and Include allowance tor glass overrun and meniscus on
the seal Ime, and lid to base mismatch
4 These dimensions measured with the leads constrained
to be perpendicular to plane T
5 Pm numbers start with pin #1 and continue
counterclockwise to pin #24 when viewed from the top

620 (1575)

175 (445)

590 (1499)
(NOTE 4)

145 (368)

1

L853-0588 84221

December 1988

9-43

~
i

60~';i'5241~
(NOTE 4)

695 (1765)

600 (15 25)

•

Signetics Unear Products

For Prefixes ADC, AM, AU, CA, DAC, ICM, LF, LM,
MC, NE, SA, SE, SG, IJA, UC

Package Outlines

28-PIN CERDIP (F PACKAGE)
1101&8:
1. Controlling dlR't8n8lon: IncheS. Millimeters are shown In
parenth......
2. OI_n. and tolerancmg per ANSI Y145M - 1982.
3. "r', "0", and "e" are reference datums on the body
and Include allowance for gtass overrun and menISCUs on
the seal hns, and lid to base mISmatch
4 These dimenSIons measured WIth the leads constrained
to be perpondtcular to plane T.
5. Pm numbers start with pin #1 and continua
counterclockwise to pm #28 when viewed from the top.
6. Denotes window locabon for EPROM Products.

J L.,~~

''.4811(37.72)

853.()589 84000

-.l .
1r·

2o-PIN PGA (G PACKAGE)
I

x "'1-841

015 (.38)

,

022 (51) TYP

OOI (·'S)

-I145.X':~'':

I,

I3"""N_

!lI,

-jI

!:

'

~.,

.... (lAO!

~

1101&8:
1 Package dlinenstOns conform to

r ::::

I

.380 ($.14)

345(i7ij

I

j

i

l-~

.ou (1.80)

~TYP.
I
_(1.15)
-i
,015 (II) MIN

(' CCANEfI8I
853-0063 82276

December 1988

MII.M~10.

outline NO.

e - 2, 20 leads. square ceramec leadless chip camero
2. Controlling dimenSIon. Inches. MIllimeters are shown In
parenthesos.
3. DlmenstOn and toleranclng per ANSI Y145M - 1982.
4. This dimenSIOn represents the mtnImum spacing between
the comer contact pads These corner pads may have a
.020 Inch by 45 degree maxllnum chamfer to accomplish
the 015 mlnmum spacmg
5. Pm numbers start wrth pm #1 and continue
counterclockwise to Pi" #20 when vrewed from the top
8 SlgnotJC8 order coda for product pecl90

(4)

40-PIN CERDIP (SOT-145)
IS9mcx

(Kg
1710;

1530

0(1('1000
I
I
26

20;

24

23

22

IIi" " " " "

21

I

ljljljljljlj I
20

•
December 1988

9-73

Signetlcs Linear Products

For Prefixes HEF, OM, PCO, PCF, PNA,
SM, SAB, TOA, TOO, TEA

Package Outlines

8-PIN PLASTIC SO (D PACKAGE) (SO-8, SOT-96A)

o@

NOTES:

.10 (.004)

1 Package dimensions conform to JEOEC specification
MS-012·AA for standard small outline (SO) package. 8
leads, 3 75mm (.150") body Width (Issue A, June 1985).
2 Controlling dimenSions are In mm. Inch dimensions In
parentheses
3. Dimensions and tolerancmg per ANSI Y145M-1982.

4. "T", "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (.006") on
any Side

5 Pin numbers start with pin #1 and contlnue
counterclockwise to pin #8 when viewed from lOp.
a Signetlcs ordenng code for a product packaged In a
plastiC small outhne (SO) package IS the SuffiX 0 after
the product number

r

I

§

~
.10 (.004)

1

l~

.35 (.014)

B53~0174

-ifl Tie lo@1

8·

~~---'

(.061 •.008)

T

.50 (.020) x45·
.25 (.010)

.25 (.010) @

I

I

.25 (010)
19(.007)

(.025 • .006)
~

(.007, .003)

~

BB070

14-PIN PLASTIC SO (D PACKAGE) (SO-14, SOT-108A)
NOTES:

1. Package dimenSions conform to JEDEC specIfication
MS.012-AB for standard small outline (SO) package, 14
leads, 375mm (150") body width (ISSue A, June 1985)
Controlling dimenSions are In mm Inch dimenSions In
parentheses
3 DimenSions and toleranclng per ANSI Y14.5M- 1982
4 "T", "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protruSions shall not exceed .15mm (.006") on
any Side.
S Pin numbers start with pin # 1 and continue
counterclockwise to pm #14 when viewed from top.
6 SlgnetlCs ordering code for a product packaged In a
plastiC small outhne (SO) package IS the suffiX 0 after
the product number

(.236.006)
~

r

(.061 •.008)
~

m
§.10 (.004)

.49 (.019)
.35 (.014)

-1+1 T 1. E lo@1- .25 (.010) @ 1

1-.E~

I

.25 (010)
.19(.007)

853-0175 88068

December 1988

.50 (.020) x45·
.25 (.010)

(.007 •.003)

(.025 •.008)

~

.635 :t..15
POOO263S

9-74

Signetics Linear Products

For Prefixes HEF, OM, PCO, PCF, PNA,
SAA, SAB, TOA, TOO, TEA

Package Outlines

16-PIN PLASTIC SO (D PACKAGE) (SO-16, SOT-109A)
~D®I.l0

,

(.004)

~

NOTes:
1 Package dimensions conform to JEDEC speCIficatIOn
MS-012-AC for standard small outlme (SO) package, 16
leads, 375mm (150") body Width (Issue A. June 1985)
2 Controllmg dimensions are In mm Inch dimenSions In

~i, ________-r

parentheses

1-tle®I.25

(010)

Dimensions and toleranCing per ANSI Y14 SM- 1982
"T", "DOl and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (006") on
any Side
5 Pin numbers start with pin # 1 and contmue
counterclockwise to pin # 16 when VIewed from top
6. Signetics ordenng code for a product packaged In a
plastic small outline (SO) package IS the suffiX 0 after
the product number.

®I

s·

~$-~~

25

I

(.010)

(.007 •.003)
.180 • •07

19 (007)

(.025 •.008)
.635 ~ .15

853-0005 86069

8-PIN PLASTIC SOL (D Package) (SOL-8, SOT-176)

1-------:::

0,15

•
December 1988

9-75

Signetics Linear Products

For Prefixes HEF, OM, PCO, PCF, PNA,
SM, SAB, TOA, TOO, TEA

Package Outlines

16-PIN PLASTIC SOL (0 PACKAGE) (SOL-16, SOT-162A)
~IO®I

10

(.004)~

NOTES:

1. Package dImensIons conform to JEDEC specification
MS-013-AA for standard small outlme (SO) package, 16
leads, 750mm (300") body width (Issue A, June 1985)
2. Controlhng dimensions are In mm Inch dimenSions In

~i~'~

parentheses.
3, DimenSions and toleranclng per ANSI Y14.SM- 1982

1065 (419)

102£ (.4041
i"tle®! 25 (010) ® !

4 "T". "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions Mold
flash or protrusions shall not exceed 15mm (006") on
any side.
S Pm numbers start with pm # 1 and continue
counterclockwise to pin #16 when viewed from top
6 Signetics ordering code for a product packaged m a
plastiC small outlme (SO) package IS the suffix 0 after
the product number

lr

U , 2 7 (050) SSC

-o~-------+------ ;~~t;~~

.75 (030)
50 (020) X45'
=----;

/---------:=i

§

10(004)!

I
-----l

L

2.35 (093)
t

.32 (013)
23 (.009)

.49(.019) -+"!T!e!o®125 (.010)@
35 (.014)

30 (012)
.10 (004)

086 (034)

853-0171 81218

20-PIN PLASTIC SOL (0 PACKAGE) (SOL-20, SOT-163A)
I---+~o®; .10 (004)!

NOTES:

1 Package dimenSions conform to JEDEC speCifICation
MS·013-AC for standard small outline (SO) package, 20
leads, 7 SOmm (300") body width (Issue A, June 1985).
2 Controlling dimenSions are In mm Inch dimenSIons In
parentheses
3 DimenSions and tolerancmg per ANSI Y14 SM- 1982
4 "T", "0" and "E" are reference datums on the molded
body and do not mclude mold flash or protrusions Mold
flash or protrusions shall not exceed .15mrn (006") on
any Side.
5 Pin numbers start with pm # 1 and continue
counterclockwise to pin #20 when Viewed from top.
S Signetics ordenng code for a product packaged In a
plastiC small outline (SO) package IS the suffiX 0 after
the product number

I

7.60 (.299)
7.40 (.291)

I

m
I

1300 (.512)
1260 (.496)

r·

75 (.030) X45'
50 (020)

,

2.65 (104)

I
-----l

10 .10 (.004) I

L

2.35 (093)

t

.49 (019)
.35 (.014)

+..:

T: e: O®i 25 (.010) @

853·0172 82948

December 1988

9-76

30 (012)

107 (.042)

.10 (004)

86 (034)

Signetics Linear Products

For Prefixes HEF, OM, PCO, PCF, PNA,
SM, SAB, TOA, TOO, TEA

Package Outlines

24-PIN PLASTIC SOL (D PACKAGE) (SOL-24, SOT-137A)
NOTES:
1 Package dlmellSlons conform to JEDEC specification
MS-013-AD for standard small outline (SO) package, 24
leads. 7 SOmm (300") body Width (Issue A. June 1985)
2 Controlling dimensions are In mm Inch dimensions In

II

I

paren1h.....
3 DimensIOns and toleranclng per ANSI Y145M-1982
4 "T", "D" and "E" are reference datums on the molded
body and do not Include mokt flash or protrusions Mokt
flash or protruSions shall not exceed 15mm (006") on
any side
5 Pin numbers start WIth pin #1 and continue
counterclockWIse to pin #24 when Viewed from top
6 SignettCs ordenng code for a product packaged In a

1065 (419)

7.60 (299)

1026 (.404)

740 (.291)

I

plastIC small outline (SO) package IS the suffiX 0 after
the product number

fflE®1 25 (010) ® I

m
I

·O·~--~~---------

r

1560 (614)
1520 (596)

.75 (.030) X45·
SO (020)

I

f9I

.,0 (.004)

L
--l ::

265 (104)
235 (093)
t

I

I

~:~::: -ttl TIE 10 ®I

32 (013)
25 (.010) @ I

23 (.009)

30 (.012)
10 (004)

107 (.042)

.66 (.034)

653-0173 82949

28-PIN PLASTIC SOL (D PACKAGE) (SOL-28, SOT-136A)
1+lo®I·10 (004) I

7.80(290)

1065 (419)

7.40 (.291)

1026 (404)
I"IE®I 25 (010) ® I

U,.27 (OSO)

esc

·O·~---f----------

18.10 (.713)
1770 (697)

r

,

10 (.004)

L
--I ::

I

265 (104)
2.35 (093)

I

::~:::

-ffITiElo@1 25 (.010) @ I

23 (009)

9·77

~X45.
.SO (.020)

t=.~----'
32 (013)

853-0006 81217

December 1988

NOTES:
1 Package dnnenSIOflS conform to JEDEC specdtcabon
MS-013-AE for standard small outline (SO) package, 28
leads, 7 50mm (300") body Width (Issue A, June 1985)
2 Controlling dimenSIons are In mm. Inch dimenSions In
parentheses
DimenSions and toleraoclng per ANSI Y145M-1982
"T", "0" and "E" are reference datums on the molded
body and do not Include mold flash or protruSIons Mold
flash or protrusions shall not exceed 15mm (006") on
any Side
5 Pm numbers start with pm #1 and continue
counterclockwise to pm #28 when Viewed from top
6 Signetics ordering code for a product packaged In a
plasttc small outline (SO) package IS the suffIX 0 after
the product number

30 (012)
.10 (.004)

•

Signetics Linear Products

For Prefixes HEF, OM, PCO, PCF, PNA,
SAA, SAB, TOA, TOO, TEA

Package Outlines

40-PIN PLASTIC SO (VSO-40, SOT-158A)
, - - 9 , 0 max

~c~

-:

m7ixJj4

T

t."1

---I

~- ~

-

t 0,15

171

min

--':5 -1

- - - 12,3max -

top View

t-,-:
4

2,0

I

max I

i___ 16,0 max _ _ _I

40-PIN PLASTIC SO (OPPOSITE BENT LEADS) (VSO-40, SOT-158B)

JIHL.IIdU
..;0

1/

.~""

4 2:o:l~'(I
:

max

I,

(

I:

(

1_ _-

16,0 max -

'

:

~li.!Ht

,_1_1

December 1988

211

I

__I

9-78

tl

1--7,6 max---1

+

I

0,22

I

0, 15

1

~ -

...

1

Signetics

Section 10
Sales Offices

Linear Products

INDEX

Sales Office listing..................................................................................

10-3

II

Signetics Unear Products

Sales Offices

SIGNETICS
HEADQUARTERS

NEW YORK
Hauppauge
Phone: (516) 348-7877

811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA. 94068-3409
Phone: (408) 991-2000

Wappingers Falls
Phone: (914) 297-4074

ALABAMA
Huntaville
Phone: (205) 830-4001

NORTH CAROUNA
Raleigh
Phone: (919) 781-1900

ARIZONA
Phoenix
Phone: (602) 265-4444

OHIO
Columbus
Phone: (614) 888-7143

CAUFORNIA
canoga Park
Phone: (818) 880-6304

OREGON
Beavenon
Phone: (503) 627-0110

Irvine
Phone: (714) 833-8980
(213) 588-3281

PENNSYLVANII.'
Plymouth Meeting
Phone: (215) 825-4404

Los Angeles

TENNESSEE
Greeneville
Phone: (615) 639-0251

Phone: (213) 670-1101

San Diego
Phone: (619) 580-0242
Sunnyvale
Phone: (408) 991-3737
COLORADO
Aurora
Phone: (303) 751-5011
FLORIDA
Ft. Lauderdale
Phone: (305) 486-6300
GEORGIA
Atlanta
Phone: (404) 594-1392
IWNOIS
Itasca
Phone: (312) 250-0050
INDIANA
Kokomo
Phone: (317) 459-5355
KANSAS
Overland Park
Phone: (913) 469-4005
MASSACHUSETTS

UttIeton
Phone: (617) 498-6411
MICHIGAN
FlII'I1Ilngton Hills
Phone: (313) 338-6600

TEXAS
Austin
Phone: (512) 339-9944
Houston
Phone: (713) 666-1989
Rlchardeon
Phone: (214) 644-3500
CANADA
SIGNETICS CANADA, LTO.
Etoblcoke, Ontario
Phone: (416) 626-6676
Nepean, Ontario
Signetics, Canada, Ltd.
Phone: (613) 225-5467

REPRESENTATIVES
ARIZONA
Scottsdale
Thorn Luke Sales, Inc.
Phone: (602) 941-1901
CONNECTICUT
Brookfield
M & M AsSOCiates
Phone: (203) 775-6888
FLORIDA
Cleerwater
Sigma Technical Associates
Phone: (813) 791-0271

MINNESOTA
Edina
Phone: (612) 835-7455

Ft. Lauderdale
Sigma Technical Associates
Phone: (305) 731-5995

NEW JERSEY
Parsippany
Phone: (201) 334-4405

ILUNOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (312) 382-3001

INDIANA
Indianapolis
Mohrfield Marketing, Inc.
Phone: (317) 546-6969
IOWA
Cedar Rapids
J.R. Sales
Phone: (319) 393-2232
MARYLAND
Glen Burnie
Third Waye Solutions, Inc.
Phone: (301) 787-0220
MASSACHUSETTS
N. .dham Helghta
Kanan Associates
Phone: (617) 449-7400

-------

-

OREGON
Beaverton
Western Technical Sales
Phone: (503) 644-8860
PENNSYLVANIA
Pittsburgh
Bear Marketing, Inc.
Phone: (412) 531-2002
Willow Grove
Delta Technical Sales Inc.
Phone: (215) 657-7250

MICHIGAN
Bloomfield Hills
Enco Marketing
Phone: (313) 642-0203

UTAH
Salt Lake City
Electrodyne
Phone: (801) 264-8050

MINNESOTA
Eden Prairie
High Technology Sales
Phone: (612) 944-7274

WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900

MISSOURI
Brfdgeton
Centech, Inc.
Phone: (314) 291-4230
Raytown
Centech, Inc.
Phone: (816) 358-8100

Spokane
Western Technical Sales
Phone: (509) 922-7600

NEW HAMPSHIRE
Hookset
Kanan Associates
Phone: (603) 645-0209
NEW JERSEY
East Hanover
Emtec Sales, Inc.
Phone: (201) 428-0600
NEW MEXICO
Albuquerque
F.P. Sales
Phone: (505) 345-5553
MEXICO
Panamtek
Mexico, D. F.
Phone: (905) 586-6443
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
OHIO
Centerville
Bear Marketing, Inc.
Phone: (513) 436-2061
Richfield
Bear Marketing, Inc.
Phone: (216) 659-3131

10-3

December 1988

OKLAHOMA
Tulsa
Jerry Robinson and
Associates
Phone: (918) 665-3562

WISCONSIN
Waukeeha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
Burnaby, British Columbia
Tech-Trek, Ltd.
Phone: (604) 439-1373
Mlsalsaauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-0366
Nepean, Ontario
Tech-Trek, Ltd.
Phone: (613) 225-5161
Ville 51. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540

DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
AYnet Electronics
Hamiltonl Aynet Electronics
Marshall Industries
Schweber Electronics
Wyle/LEMG
Zentronics, Ltd.

•

Signetics Linear Products

Sales Offices

FOR SIGNETICS
PRODUCTS
WORLDWIDE:

FRANCE
R.T.C. Issy·les-Moulineaux
Cedex
Phone: 33·1·40·93·80·00

ARGENTINA
Philips Argentina S.A.
Buenos Aires
Phone: 54·1·541-7141

GERMANY
Valvo
Hamburg
Phone: 49-40-3·296-0

AUSTRALIA
Philips Electronic
Components and Materials,
Ltd.
Artarmon, N.S.w.
Phone: 61·2-439-3322

GREECE
Philips S.A. Hellenique
Athens
Phone: 30-1-4894-339

AUSTRIA
Osterrichische Philips
Wien
Phone: 43·222-60-101-820
BELGIUM
N.V. Philips & MBLE
Brussels
Phone: 32·2-5-23-00-00
BRAZIL
Philips Do Brasil, Ltda.
Sao Paulo
Phone: 55·11-211-2600
CHILE
Philips Chilena S.A.
Santiago
Phone: 56·02-077-3816
PEOPLES REPUBLIC OF
CHINA
Philips Hong Kong Ltd.
Kwai Chung Kowloon
Phone: 852-0-245-121
COLOMBIA
Iprelenso, Ltda.
Bogota
Phone: 57·1-2497624
DENMARK
Mlnlwatt A/S
Copenhagen S
Phone: 45·1-54-11-22
FINLAND
Oy Philips Ab
HelSinki
Phone: 358-0-172-71

HONG KONG
Philips Hong Kong, Ltd.
Kwal Chung, Kowloon
Phone: 852-0-245-121
INDIA
Pelco Electronics & Elect.
Ltd.
Bombay
Phone: 91-22-493-8721

KOREA
Philips Industries, Ltd.
Seoul
Phone: 82·2·794·5011
112/13/14/15
MALAYSIA
Philips Malaysia SDN Bernhad
Pulau Penang
Phone: 60-4-870055
MEXICO
Panamtek
Guadalajara, Jal
Phone: 52-36-30-30-29
NETHERLANDS
Philips Nederland
Eindhoven
Phone: 31-40-444-755
NEW ZEALAND
Philips New Zealand Ltd.
Auckland
Phone: 64-9-605914

INDONESIA
P.T. Phlllps·Ralin Electronics
Jakarta Selatan
Phone: 62-21-512-572

NORWAY
Norsk AIS Philips
Oslo
Phone: 47-2-68-02-00

IRELAND
Philips Electrical Ltd.
Dublin
Phone' 353-1-69-33-55

PERU
Cadesa
San Isidro
Phone: 51-70-7080

ISRAEL
Rapac Electronics, Ltd.
Tel AVIV
Phone: 972-3-477115

PHILIPPINES
Philips Industrial Dev., Inc.
Makati Metro Manila
Phone: 63-2-868951-9

ITALY
Philips S.p.A.
Milano
Phone: 39-2-67-52-1

PORTUGAL
Philips Portuguesa SARL
Lisbon
Phone: 351-1-68-31-21

JAPAN
Signetics Japan Ltd.
Osaka
Phone: 81-6-304-6071
Signetics Japan Ltd.
Tokyo
Phone: 81-3-230-1521/2

SINGAPORE
Philips Project Dev. Pte., Ltd.
Singapore
Phone: 65-350-2000
SOUTH AFRICA
E.D.A.C. (PTY), Ltd.
Joubert Park
Phone: 27-11-617-9111

EffectIVe OCtober 1988

December 1988

10-4

SPAIN
Mlniwatt S.A.
Barcelona
Phone: 34·3·301·83·12
SWEDEN
Philips Komponenter A.B.
Stockholm
Phone: 46-8-782-10-00
SWITZERLAND
Philips A.G.
Zurich
Phone: 41-1-488-2211
TAIWAN
PhilipS Taiwan, Ltd.
Taipei
Phone: 886-2-712-0500
THAILAND
Philips Electrical Co.
of Thailand Ltd.
Bangkok
Phone: 66-2-233-6330/9
TURKEY
Turk Philips
Ticaret A.S.
Istanbul
Phone: 90-11-43-59-10
UNITED KINGDOM
Philips Componets
London
Phone: 44-1-580-6633
UNITED STATES
Signetics International Corp.
Sunnyvale, California
Phone: (408) 991-2000
URUGUAY
Luzllectron, S.A.
MonteVideo
Phone: 598-91-56-41
142/43/44
VENEZUELA
Magnetlca, S.A.
Caracas
Phone: 58-2-241-7509

Signelics Unear Products

Additional Drawings for the NE/SA605

5 !"gnEt i cs

5 !,BnEt i cs

°[} o-.n'o .,n,.
°c~~cQ'ClQW;pc·'·

"-Tlooo ...",
C2
CI

~

1':"1"
~

'.4

CS

'"

fiiE611S

~c:l Oa:l~CCQCC
c.

CIJ

~

0",

.a~l

...
•

C
'"
'I!I!J

CI5

..-.

~

~

SoWI

0
en

0
elJ

Signetics Linear Products

Additional Drawings for the NE/SA60S

20

iii
:!!.

0

~ -20
S
~

C

AU~ R~F = 1174 Jv RJS

K

-40

\

g
UI -60

~

V

/ \

~

II:

/

~

-80

v

V1

I

I

-olo

AM(j)

NOllE

f-::

I
-130-110 -90 -70 -so -30 -10

-100

=-

Ri

10

RF INPUT LEVEL (dBm)
RF = 45MHz IF = 455kHz Vee = 6V

Figure 3. NE/SA605 Application
Board at 25°C

Signetics Unear Products

Additional Drawings for the NE/SA575

EXP IN

cs

D---iH"""-""""......-t
10K
10jAF

I~OUT
R41100K

UK

Figure 1. Typical Expandor Configuration

RS

R6

20K

301(

R7

C8
COMP IN

C12

13

~~~~~-.~~
lo.,F

R9

CQMP OUT

~~--~~~~R8j[100~v---C>

Figure 2. Typical Expandor Configuration
R8
30K

RS

R7
C7 30K

~1,1
CCQMP

20K

14

ALC IN

C12

1

13

C8

R9

~'----11~~~~]['::

ALCOUT

C>

16

4.7,1

Figure 3. Typical ALC Configuration

Signetics Unear Products

Additional Drawings for the NE/SA575

Vee - 5V

C15

1o,A' COMA'ALC IN
R3

ALC

EXP OUT 200

COMP

EXP IN

C5

~~--------~

C8

R9

COMA'ALC OUT

R71~

1o"F

Hf-......W......... 30K
C7

~1""

fiMlK
_

Figure 4. Signetics NE575 Low Voltage Expandor/Compressor/ALC Demo Board

.9
.8
.7

.6

m
ll.

.5

0:

0

0:
0:

.4

W

~

"
~

.3
.2

Z

"
-.1

-.2
-.3
24

28

3.4

3.8

44

4.8

5.4

5.8

SUPPLY VOLTAGE (V)

Figure 5. Unity Gain Error vs Supply Voltage

6.4

6.8

7A

7.8

Signefics
a division of North American Philips Corporation
Signetics Company
811 E. AfQues Avenue
P. O. Box 3409
Sunnyvale, Ca lifornia 94088-3409
Te lephone 408 /991-2000

98-2000-000

Copy ri ght 1989 NA PC
Printed in USA 8413L!CR/80M/0189
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:22 19:50:11-08:00
Modify Date                     : 2013:08:23 08:06:06-07:00
Metadata Date                   : 2013:08:23 08:06:06-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:b82731c1-2278-1543-8190-5a87824932d9
Instance ID                     : uuid:f24ddaf6-3b5d-4847-962a-314cdd64de27
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 1178
EXIF Metadata provided by EXIF.tools

Navigation menu