1989_Microcomputer_Programmable_Logic_Handbook 1989 Microcomputer Programmable Logic Handbook

User Manual: 1989_Microcomputer_Programmable_Logic_Handbook

Open the PDF directly: View PDF .
Page Count: 464

Download
Open PDF In Browser	View PDF

intJ
Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology. In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
modules, and systems to give its customers the best possible competitive advantages.

PROGRAMMABLE LOGIC
HANDBOOK

1989

inter

IntelCo~poration makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, ETOX,
FASTPATH, Genius, i,
ICE, iCEL, iCS, iDBP, iDIS, 12 1CE, iLBX,
im, iMDDX, iMMX, Inboard, Insite, Intei, intel, Intel376, Intel386, Intel486,
intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPDS, iPSC, iRMK, iRMX, iSBC,
iSBX, iSDM, iSXM, KEPROM, Library Manager, MAPNET, MCS,
Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,
PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse·
Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube,
UP!, and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX,
iSXM, MCS, or UPI and a numerical suffix, 4-SITE, 376, 386, 486.

MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered
trademark of Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130
@INTELCORPORATION 1988

intJ
CUSTOMER SUPPORT
EPLD HOTLINE
'.

The Intel EPLD Technical Hotline is manned by applications personnel from 8:00 a.m. to 5:00 ,p.m.
business day. The number (U,S. and Canada) is 1 ~800-323-EPLD (1-800-323-3753),

(p~:rr)

every

DDS
Intel has a Bulletin Board -System for regis~ered iPLS II customers to electronically transfer infonil!~tiqn; A registered user with a modem can log onto the system. The current number is (916) 985-2308. If your communication
software silpports file transfers, you can receive utilities, software updates, and the latest information on EPLDs
via the Bulletin Board.
. "
. .
,

CUSTOMER SUPPORT
Customer Support is Intel's complete support service that provides Intel customers with hardware support; software
support, customer training, and consulting services. For more information contact 'your local sales offices..

After a customer purchases any system hardware or software product, service and support become major factors in
determining whether that product will continue, to meet a customer's expectations. Such support requires an international support organization and !l breadth of programs to 'meet a variety of customer ,needs. As you might expect,
Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices
providing hardware repair services, software support services, customer training classes;'and consulting services.
. l

HARDWARE SUPPORT SERVICES
Intel is committed to providing an international service support package through a wide variety of service offerings
available from.Intel Hardware Support.

SOFTWARE SUPPORT SERVIC~
Intel's software support consists of two ievels of contra~t~. Staridatd support includ~s TIPS: (Technical I~formation
Phone Service), updates and subscription service (product-specific' troubleshooting guides and COMMENTS
Magazine). Basic support includes updates and the subscription service. Contracts are sold in environments which
.
,
represent product groupings (I.e., iRMXQi) environment).

CONSULTING SERVICES
Intel provides field systems engineering services for any phase of your development or support effort. You can use
our systems engineers in a variety of ways ranging from' assistance iii using it new product" developing an application, personalizing training, and customizing or tailoring an Intel product to providing technical and management
consulting. Systems Engineers are well versed in techniCal areas such as microcommunications, real-time applications, embedded microcontrollers, and network services. You know your application needs;. we know our products.
Working together we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering v!lrious aspects of system design and implementation.
Injust three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.
For optimum convenience, workshops are scheduled regularly at Training Centers worldwi.deor we' can take .our
workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include:
architecture and assembly language, programming and operating systems, BITBUSTM and LAN applications.

CG/CUST/062188

Table of Contents
Alphanumeric Index ............................ : . . . . . • . . . . . • . . . . . . . • . . . . . .

CHAPTER 1
Overview
Overview ...........................•.............••.............•..•...". " 1-1
CHAPTER 2

EPi.D~Erasable Programmable Logic Devices
DATA SHEETS
5C031 , 300-Gate CHMOS H-Series Erasable Programmable Logic Device
(H-EPLD) ............ '.........•..•....•...... : . • • . . . . . • . • . . . . . • . . . • . . . .
2-1
5C032, 300-Gate CHMOS H.;series Erasable Programmable Logic Device
,
',.,', '(H~EPLD)'~ ............. ~ ..... '.•..• '.,'.' .... ~ ... : ...................... .'.'.. 2-13
, 5C060, 600-Gate CHMOS H-Series Erasable Programmable Logic Device "
, (H-EPLD) ............•.•.....••.......•.........•........... :.'. '. '. . . . . . . 2-26
5C090, 900-Gate CHMOS H-Series Erasable Programmable LogicDevice .,' , '
(H-EPLD) ........•.•.•.•.....•........•...............•................ 2-42
5C121, 1200-Gate CHMOS H-Series' Erasable Programmable Logic Device. . . . . . 2-59
5C180,1800-Gate CHMOS Erasable Programmable Logic Device .. : .. :.;...... ..2-74
APPLICATION BRIEFS
AB-8Implementing'Cascaded Logic in the 5C121 .....•.. ; ... ~. '.... ; ;' ... : .. ,:.',2-106
AB-9 5C121 As aThr'ee and One-Half Digit DisplayDriver.' ....•........ : ...•..• ',2-111
, AB~1 0 Squ~r~ ~egs in Ro:und Hole~A F!tting~utorial for the, 5C12i .. ',: .. ~ : . . ... '2~ 116
AB-11,16-Blt Binary Counter Implementation USing the 5C060 EPLD •....... ,..... ,2-128
AB-12 Designing a Mailbox Memory for Two 5C031 s ...... .' .. ~ .......•. : . . . • . .. ' 2-138
AB-16 Atypical Latch/Register Construction in EPLDs ..•... ~ .' .. " : .••.....•..• , '2-152
AB-22 5C032-25 vs. 16V8-25: A Device Comparison ., ...•.........•............. 2-159
APPLICATION NOTES
.
AP-271 Applying the 5C121 Architecture •••.•..•.•.•.•.. : ..... '.. ; .... ; ..... ;.. 2-165
AP-272 The 5C060 Unification of a CHMOS System ........ , ',' ... , .......... ". 2-177
AP-276 Implementing a CMOS Bus Arbiter/Controller in the 5C060 EPLD . ~ ... . .. 2-188
AP-307 EPLDs, PLAs, andTTL~ompari'1g the "Hid~en CO,sts" in Production .. ". 2-198
, ",AP-321 Fitting the,5C180 •....• : .... : ..•..,••.•...•.•. '..• '... :.••..•...... ~ ...... 2-220
ENGINEERING REPORTS,' ' . '
':
." "
, .
"
ER-22 5C180 vs. EP1800: AComparison of Device Specifications ...... '......... ,2-233
TECHNICAL PAPERS
'
Techniques for Modular EPLD Designs ..........•........•.. '...... '... ; ... ; : .. 2-241
ARTICLE REPRINTS ,
AR-450 Crosspoint SwitCh: APLD Approach .... : .. ~ .... ; ••....... ~ ..... ,~'. . . . .2-251
"
, AR':451A Programmable ~ogic Mailboxfor80C31 Microcontrollers ........ : ..... 2-255
, 'AR-454 Regain Lost I/O Ports with Erasable PLDs .;;.: ... : ..•... '. : •.•.. ,":. ~... 2-258
•

, :

" . '

, .

•

; : .

•

I '

• ,

'CHAPTER 3

Advanced Architecture EPLOs
DATA SHEETS
' , '
,
5AC312, 1-Micron CHMOS Erasable Programmable Logic Device: .. : ....... : :'.. ,'3-1
5AC324, 1-Micron CHMOSEPLD ............... '. , ............. ," ......... , .3-19
85C508, Fast 1-Micron CHMOS EPLD '... ~ .. ; .....•.... : ....... ';: ............ ~ 3~38
,5CBIC,Programmabie BUS Interface Controller ... ; .•.•.....• ; .....• ; •..... '; ;.3-45
. APPLICATION NOTES
'AP-317 Implementing a PS/2 POS Using the 5AC312 EPLD ..... ; ......... ,; .. : 3.62
AP-319 Designing with the 5AC312/5AC324 EPLDs . .... .... .. .. . .. . .....•. ... 3-74
, TECHNICAL PAPERS
. Programmable and/AlJocatable Based EPLD Addresses the Needs of Complex
Combinational and Sequential Designs. . . • . . • . • . • . . . • . • . • . . . . . • • . . . . . . .. . . . 3-83
Advanced Architecture PLDs Solve Common State Machine Problems. . . . . . . . . . . 3-91
vii

Table of Contents (Continued)
~HAPTER4

Development Support Tools
DATA SHEETS
, iPLDS II, The Intel Programmable Logic Development System Version II . . . . . . . . . .
iUP-PC,lntel Universal Programmertor the Personal Computei' ................ ~
iUP-200AliUP-201A Universal PROM Programmers...........................
.
PRODUCT BRIEFS
SCHEMA II-PLD .•.................................. ~ .. . . . . . . . . .. . . . . . . . . . . .
iPLSIl Macro Librarian ................... '....... ; .................... " . • . .
PLDUTIL .......... '.' . _............................ ; ...... , . • . . . . . . . . . . . . . .
UTILITIES
pAL2ADF Utility .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JED2HEX Conversion Utility ............................ : . . . . . . . . . . . . . . . . . . .
APPLICATION BRIEFS
AB-18 TIL Macro Library Listing for EPLD Designs............................
AB-21 EPLD Custom Macro Library Listing for EPLD DeSigns ...................
APPLICATION NOTES
AP-311 Using Macros in EPLD DeSigns . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .
AP-312 Creating Macros for EPLD Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
TECHNICAL PAPERS
'
Tools for Optimizing PLD Designs. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .

4-1
4-11
4-18
4-25
4-26
4-27
4-29
4-32
4-33
4-37
4-41
4-52
4-62

CHAPTERS

Appendix
EPLD Third Party Programming Support. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
PLA to EPLD Replacement. . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . .. . . . ...
Ordering Information ................................... ;;..................
Device Feature Comparison .. . . . . . . . . . . . . . . . . . • . . .. . . . . . . . . . . . . . . . . . . . . . . . .
EPLD Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Compatible Computers for iPLDS II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

5-1
5-2
5-3
5-4
5-5
5-6

,Alphanumeri,c Index
SAC312, 1-Micron CHMOS Erasable Programmable Logic Device .•................ ,,.,.,
SAC324, 1-Micron CHMOS EPLD ..................................................
SC031, 300-Gate CHMOS H-Series Erasable Programmable Logip Device (H-EPLD)' .....
SC032, 300-Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD) '. .. . .
SC060, 600-Gate CHMO$ H-Series Erasable Programmable Logic ,Device (H~EPLD). . .. .
SC090, 900-Gate CHMOS H-SeriesErasable Programmable Logic Device (H-EPLD) ... ;.
SC121,,1200-Gate CHMOS H-Series Erasable Programmable Logic Device .•... :.........
SC180, 1800-Gate CHMOS Erasable Programmable Logic Device.....................
SCBIC, Programmable BUS Interface Controller ..•.................... ,.. . . . . . .. . . ..
8SCS08', Fast 1-Micron CHMOS EPLD ............................ ;.' ..•... : ..... ,....
jPLDS II, The Intel Programmable Logic Development System Version II .•.........•... :.
iUp·200AliUP·201 A Universal ,PROM Programmers ........................... ; . ... . . .
iUP·PC, Intel Universal Programmer for the Personal Computer ......•............. ;; ..

3~1

3~19

2-1
2-13
2-26
2-42
2-S9
2-74
3-4S
3-38
4-1
4-18
4·11

".:

Any of the following products may appear in this publication. If so, it must be noted that
such products have counterparts manufactured by Intel Puerto Rico, Inc., Intel Puerto
Rico II, Inc., and/or Intel Singapore; Ltd. The prod1.!ct codes/part numbers of these
counterpart products are listed below next to the corresponding Intel Corporation product
codes/part numbers.
Intel Corporation
Product Codes/
Part Numbers

Intel Puerto Rico, Inc.
Intel Puerto Rico II, Inc.
Product Codes/
Part Numbers

376SKIT
p376SKIT
903
p903
904
p904
p913
913
914
p914
923
p923
924
p924
952
p952
953
p953
954
p954
ADAICE
pADAICE
B386Ml
pB386Ml
B386M2
pB386M2
B386M4
pB386M4
B386M8
pB386M8
C044KIT
pC044KIT
C252KIT
pC252KIT
C28
pC28
C32
pC32
C452KIT
pC452KIT
D86ASM
pD86ASM
D86C86
pD86C86
D86EDI
pD86EDI
DCM911l
pDCM911l
DOSNET
pDOSNET
FI
pFI
GUPILOGICIID pGUPILOGICIID
H4
pH4
1044
pI044
1252KIT
pI252KIT
1452KIT
pI452KIT
186ASM
pI86ASM
ICE386
pICE386
IIIOIO
pIIIOIO
III086
pIII086
III086
TIII086
IIIIIl
pIIIlll
1II186
pIIII86
1II186
TIll I 86
III I 98
pIlI I 98
1II212
pIll212
111286
pIll286
1II286
TIII286
1II515
pIll515
1II520
TIII520
1II520
pIIIS20
I11531
plIIS31
. pIIIS32
I11532
1II533
pIIIS33
III621
pIll62 I
I11707
plII707
I11707
TIII707
III815
plII815
INA961
pINA96I
IPAT86
pIPAT86
KAS
pKAS
KC
pKC
KH
pKH
KMI
pKMl

Intel Singapore, Ltd.
Product Codes/
Part Numbers

Intel Corporation
Product Codes/
Part Numbers

KM2
KM4
KM8
KNLAN
KT60
KW140
KW40
KW80
Ml
M2
M4
M8
MDS610
MDX3015
MDX3015
MDX3016
MDX3016
MDX457
MDX457
MDX458
MDX458
MSA96
NLAN
PCLlNK
PCX344A
R286ASM
R286EDI
R286PLM
R286SSC
R86FOR
RCB4410
RCX920
RMX286
RMXNET
S301
S386
SBCOIO
SBCOl2
SBC020
SBC028
SBC040
SBC056
SBCJ08
SBCIl6
SBC I 8603
SBCI864JO
SBC18651
SBC186530
SBC18678
SBC18848
SBC18856
SBC208
SBC214
SBC21S
SBC220
SBC221
SBC286JO
SBC28612
SBC28614

Intel Puerto Rico, Inc.
Intel Puerto RIco II, Inc.
Product Codes/
Part Numbers

Intel Singapore, Ltd.
Product Codes/
Part Numbers

pKM2
pKM4
pKM8
pKNLAN
pKT60
pKW140
pKW40
pKW80
pMl
pM2
pM4
pM8
pMDS610
pMDX3015
pMDX3015
pMDX3016
pMDX3016
pMDX457
pMDX457
pMDX458
pMDX458
pMSA96
pNLAN
sPCLINK
pPCX344A
pR286ASM
pR286EDI
pR286PLM
pR286SSC
pR86FOR
sRCB4410
pRCX920
pRMX286
pRMXNET
pS301
pS386
pSBCOIO
pSBC012
pSBC020
pSBC028
pSBC040
pSBC056
pSBCJ08
pSBCIl6
pSBC18603
pSBCI864JO
pSBC186S1
pSBC186S30
pSBC18678
pSBC18848
pSBC18856
pSBC208
pSBC214
pSBC21S
pSBC220
pSBC22I
pSBC28610
pSBC286 I 2
pSBC28614

sSBCOl2

sSBCI8603
sSBC18651

sSBC18848
sSBC188S6
sSBC208
sSBC220
sSBC28610

Intel Puerto RiCo, Inc.
Intel Corporation
' Intel Puerto Rico II, Inc.
Product Codes/
Product Codes/
Part Numbers
Part Numbers
SBC28616
SBC300
SBC301
SBC302
SBC304
SBC307
SBC314
SBC322
SBC324
,SBC337
SBC341
SBC386
SBC386116
SBC386120
SBC38621
SBC38622
SBC38624
SBC38628
SBC38631
SBC38632
SBC38634
SBC38638
SBC428
SBC464
SBCS17
SBCS19
SBCS34
SBCS48
SBCSSO,
SBCSSO
SBCSSO
SBCSS2
SBCSS6
SBCS69
SBCS89
SBC604
SBC608
SBC614
SBC618
SBC6SS
SBC6611
SBC80lO
SBC80204
SBC8024
SBC8030
SBC860S
SBC8612
SBC8614
SBC8630
SBC863S
SBC86C38
SBC882S
SBC8840
SBC884S
SBC90S
SBCLNKOOI

pSBC28616
pSBC300
pSBC301
pSBC302
pSBC304
pSBC307
pSBC314
pSBC322
pSBC324
pSBC337
pSBC341
pSBC386
pSBC386116
pSBC386120
pSBC38621
pSBC38622
pSBC38624
pSBC38628
pSBC38631 '
pSBC38632
pSBC38634
pSBC38638
pSBC428
pSBC464
pSBCS17
pSBCS19
pSBCS34
pSBCS48
TSBCSSO
pSBCSSO
pSBCSSO
pSBCSS2
pSBCSS6
pSBCS69
pSBCS89
pSBC604
pSBC608
pSBC614
pSBC618
pSBC6SS
pSBC6611
pSBC80lO
pSBC80204
pSBC8024
pSBC8030
pSBC860S
pSBC8612
pSBC8614
pSBC8630
pSBC863S
pSBC882S
pSBC8840
pSBC884S
pSBC90S
pSBCLNKOOl

Intel Singapore; Ltd.
Product Codes/
Part Numbers

sSBC386

aSBC428

sSBCS19
aSBCS34

aSBCSS6

sSBC8024
sSBC860S

sSBC8630
sSBC863S
sSBC86C38
aSBC882S aSBC884S

Intel Puert9 Rico, Inc.
Intel Corporation,'
Intel Puerto 'Rico II, Inc.'
Product Codes/
Product Cod.../
Part Numbers
Part Numbers
pSBCMEM310
SBCMEM310
pSBCMEM312
SBCMEM312
pSBCMEM320
SBCMEM320
pSBCMEM340 '
SBCMEM340
SBE96 ,
pSBE96 ,
SBX217,
pSBX217
pSBX218
SBX218
SBX270
pSBX270
' SBX311
pSBX311 '
pSBX328,
SBX328
SBX331
pSBX33I
SBX344
pSBX344
SBX3S0
pSBX3S0
pSBX3S1
SBX3S1
pSBX3S4
SBX3S4
pSBX488
SDX488
SBXS86
SCHEMAIIPLD pSCHEMAIIPLD
pSCOM
SCOM
pSDKSl
SDKSI
SDK8S
pSDK8S
SDK86
pSDK86
SXM217
'pSXM217
SXM28612
pSXM28612
SXM386
pSXM386
pSXMS44
SXMS44
pSXMSS2
SXMSS2
pSXM9S1
SXM9S1
SXM9SS
pSXM9SS
SYP120
pSYP120
pS)'P301
SYP301
pSYP302
SYP302
pSYP31090
SYP31090
pSYP311
SYP311
SYP3847
pSYP3847
pSYR286
SYR286
SYR86
pSYR86 ,
SYS120
pSYS120
SYS310
pSYS3lO
SYS311
pSYS311
T60,
pT60
TA096
pTA096
TA2S2
pTA2S2
pTA4S2
TA4S2
W140'
pW140
W280
pW280
pW40
W40
pW80
W80
XNX286DOC
pXNX286DOC
XNX286DOCB
pXNX286DOCB
XNXIBASE
pXNXIBASE
XNXIDB
pXNXIDB
XNXIDESK
pXNXIDESK
XNXIPLAN
pXNXIPLAN
pXNXIWORD
XNXIWORD

Intel Singapore, Ltd.
Product Codes/
Part Numbers

sSBXS86

CG/PCPN/l02488

Overview

OVERVIEW

SMALLER SYSTEM SIZES: Customized components allow for reducing chip count and saving board
space, resulting in smaller system physical dimensions.

INTRODUCTION
In today's increasingly competitive marketplace, system designers need to squeeze out every little edge they
can get from their designs. This has led to a trend
towards better performance, smaller system sizes, lower
power requirements and greater system reliability with
a strong emphasis on preventing easy duplication of the
system design. This trend provided the impetus to· the
system designers to move away from standard SSI and
MSI logic components (54/74 & 4000 series Bipolar
and CMOS families) towards a growing class of IC devices variously called 'ASIC' (application specific IC),
'USIC' (user specific IC) or, as referred to in this docu'
ment, user defined logic.'

b. LOWER SYSTEM COSTS: When, custom LSI or
VLSI components are used instead of standard SSI and
MSI logic elements, there is a considerable saving in
component cost per system, assembly and manufacturing cost, printed circuit board area and board costs and
inventory costs.
c. HIGHER PERFORMANCE: Reduced number of
ICs contributes to faster system speeds as well as lower
power consumption.
d. HIGHER RELIABILITY: Since probability of failure is directly related to the number of ICs in the system, a system composed of customized LSI & VLSI
chips is statistically much more reliable than the identical system made up of SSI/MSI devices.

User defined logic circuits allow system designers, for
the first time, to tailor the actual silicon building blocks
used in their systems to their individual system needs
and requirements. Such customization provides the
needed performance, reliability and compactness as
well as design security. Cost per gate of logic implemented is also greatly reduced when user defined logic
solutions are chosen over standard components.

e., DESIGN SECURITY: Systems designed with standard components can be replicated relati.vely easily
whereas systems that contain user customized ICs cane
not'be copied because "reverse engineering" ofthe customizedcomponents,is extremely difficult. Thus, use of.
customized ICs allows for the protection of proprietary
'
,
designs.

User defined logic has therefore emerged as the fastest
growing segment of the semiconductor industry and
has presented its users, the system designers,. with a
wide range of implementation alternatives ,namely, programmable logic, gate arrays, standard cell and full
custom design. The tradeoffs between these alternatives
involves time-to-market, one-time engineering charges,
expected unit volume, ease. of use of design tools and
familiarity with the design methodology.

f. INCREASED FLEXIBILITY: Customized compo-

nents allow for the tailoring of systems to the end user's
specific needs relatively easily. This also allows for upgradability,and obsolescence protection.

USER DEFINED IC--IMPLEMENTATION ALTERNATIVES

This document discusses the reasons for the trend to
user defined logic devices, briefly describes some of the
user defined logic implementation alternativ:es and covers details on programmable logic devices, the only alternative that is completely user implementable. Tools
used to design with programmable logic are also discussed here.

Currently, the choices available to the system designer
for customization of ICs (see Figure 1) are as follows:
(1) user programmable ICs--programmable logic devices
(2) mask programmable ICs-gate arrays
(3) standard cell based ICs
(4) full custom I Cs

Details on Intel's programmable logic product line, in-.
cluding device terminology and nomenclature, architectural features and development tool features are also
described in this document.

Alternatives (1) & (2) are usually called 'Semicustom'
because in these methods only a few (less than three) of
the mask layers involved in the manufacture of the IC,
are customized to the users' specifications. The later
two alternatives (3) & (4), involve customization of all
mask layers required to manufacture the ICs to the users' specifications and are therefore called 'Custom'.

WHY USER DEFINED LOGIC?
System designers prefer user customized ICs for the
following reasons:

1-1

intJ

OVERVIEW

SEMICUSTOM

I
PROGRAMMABLE
, LOGIC

his logic requirements, determines which of these connections he would like to remain open and which he
would like to close, through the programming of the
PLD. Programmability ofthese connections is achieved
using various memory ,technologies such as fuses,
EPROM cells, EEPROM cells or Static RAM cells (see
Figure 3).

USER DEfINED LOGIC

CUSTOM

GATE
ARRAYS

STANDARD
, CELL

I
FULL
CUSTOM

User programmability allows for instant customization,
very similar to user programmable memories such .as
PROMs or EPROMs. The user can purchase a PLD
off-the~shelf, use a development system running on a
personal computer and, in a matter of a few hours, have
customized silicon in his hands. Figure 4 compares
user-defined logic alternatives.

, 296032-1

Figure 1. User Defined Logic
Implementation Choices,

PROGRAMMABLE'LOGIC
Most user Programmable Logic Devices (PLD) are internally structured as variations of the PLA (program"
mabie logic array) architecture, that is composed of an
array of 'AND' gates connected to an array of 'OR'
gates (see Figure 2). Programmable logic devices make
use of the fa:ct that any logic equation can' be converted
to a1l equivalent 'Sum-of-Products' form arid can thus
be iniplemented in the 'AND' and 'OR'architeCture.
This basic PLA structure has been augmented in most
PLDs with input and output bl()cks 'containing registers, latches and feedback options,that let the userimplement sequential logic functions in addition to combinational logic.

ABC

memory cell
used as logic control element

The number and loca:tions of the programmable connectionsbetween the 'AND' and 'OR' matrices as well
as the input and output blocks are predetermined by
the architecture of the PLD. The user, depending on

296032-3

Figure 3. Programmable Connections '

FEEDBACK (programmable)

PROGRAMMABLE
,'AND'& 'OR'ARRAY

INPUT--"''''
PIN~-~/.

OUTPUT
PIN

OUTPUT BLOCK
(containing output
controls, registers, etc.)

INPUT BLOCK
(contains latches and other
programmable Input options) ,

FigUre 2.G4Nteral Architecture of a PLD

1-2

intJ

OVERVIEW

tional testing elements incorporated in the chips, which
can be blown to examine electrical, characteristics.
However, such testing methods never allow for 100%
testability of all parts shipped. Thus, most users of bipolar programmable logic devices resort to extensive
post-programming testing, specific to their applications.

USER DEFINED LOGIC

SEMICUSTOM

PROGRAMMABLE
LOGIC

CUSTOM

GATE
ARRAYS

STANDARD
CELL

FULL
CUSTOM

ERASABLE PROGRAMMABLE LOGIC
DEVICES

DESIGN COMPLEXITY
DESIGN TIME /1c COST
LOWEST SYSTEM COST

'EraSable programmable logic devices (EPLD) result
from the matching of CHMOS EPROM technology
with the architectures of programmable logic devices.
EPLDs use EPROM cells as logic control elements and
therefore, when housed in windowed ceramic packages,
can'be enised with uV light and reprogrammed. Figure
5 shows the architecture of Intel EPLDs.

FASTEST TIME TO MARKET
EASIEST DESIGN CHANGE IMPLEMENTATION
, 296032-5

Figure 4. User Defined Logic
Alternatives Compared

Other than the obvious, benefit of reprogrammability,
EPLDs offer several very significant benefits over bipolar PLDs. These are:

LIMITATIONS OF BIPOLAR FUSE
TECHNOLOGY FOR PROGRAMMABLE
LOGIC DEVICES
',

1. LOW POWER CONSUMPTION: Due to the
CMOS technology, these products consume an order of
magnitude less power than the equivalent bipolar devices. This allows for the design of complete CMOS systems, that can operate at lower voltages (less than 5V).
Also, this makes for cooler systems that do not require
cooling systems like fans.

Until 1985, all PLDs were built using Bipolar fuse technology. The bipolar fuse based devices, although offering the users the benefits of quick time to market and
low development costs, had several inherent limitations.
a. HIGH POWER CONSUMPTION: Bipolar processes by nature are power hungry and as a consequence also make for very hot systems, often requiring
cooling aids such as heat sinks and fans. They ruso cannot operate at lower voltages (2-3V) and have a lower '
level of noise immunity than MOS devices.
b. LOWER INTEGRATION: A fuse takes up a large
amount of silicon area; this fact in conjunction with the
large power requirements makes for smaller levels of
integration.

2. GREATER LOGIC DENSITY: EPROM cells are
an order of magnitude smaller than' the smallest fuses.
This means that the same function can be accommodated in significantly smaller die area, or that greater
amounts of logic can now be incorporated on a single
chip. Thus higher integration programmable logic de~
vices result with the use of EPROM elements.
3. TESTABILITY: Since the EPROM cells are erasable, the entire EPROM array of the EPLD can be
100% factory tested. Thus, before the part is shipped to
the customers, it can be completely tested' by the programming and erasure of all the EPROM logic control
bits. This testing is therefore independent of any application, in contrast to the bipolar PLDs that need application sPecific testing.
'

c. ONE-TIME PROGRAMMABILITY: Bipolar fuses
can only be blown once and cannot be reprogrammed.
This does not allow for easy prototyping and could result in significant losses when preprogrammed parts are
inv~toried and design changes occur.

4. ARCHITECTURAL ENHANCEMENTS: The inherent testability of the EPROM elements allows for

d. TESTABILITY: Since fuses can only be blown once, '
bipolarPLI)s can only be destructively tested. Thus,
testing is usually ,done by sampling or through addi-

,1-3

intJ

OVERVIEW

significant· architectural . improvements over bipolar
PLDs. New features, such as buried registers, programmable registers, programmable clock control, etc., can
now be incorporated· because of this testability. These
new features allow for. greatly increased utilization of
the EPLDs and use of these devices in newer applications.
.

5. DESIGN SECURITY: EPLDs are provided with a
'security bit,' which when programmed does not allow
anyone to read the programmed pattern. The logic programmed in an EPLD cannot be seen even if the die is
examined (unlike bipolar PLDs-a blown fuse is clearly
visible) as the stored charges are captured on a buried
layer of polysilicon.·,

.,FEEDBACK (programmable)

.. ~
INPUT
PIN

'J\.

J\.
y

J\.

-y

PROGRAMMABLE
'AND' ARRAY

INPUT BLOCK
(contains latches and other
programmable input options)

FIXED,
'OR'
,ARRAY

J\.
-y

OUTPUT
PIN

OUTPUT BLOCK
'.' (containing output '
controls, registers, etc.)

296032-4,

Figure 5. Arcbitecture of Intel EPuis
USER.

PROGRAMMING,
HARDWARE'

DEVELOPMENT
SOFlWARE

,[ID
Data

Entry

CONVERSION TO
BOOLEAN
EQUATIONS

III
Device Request

LOGIC
MINIMIZATION TO
SUM-Of-PRODUCTS
FORMAT

Device
Utilization'
Report

RESOURCE
MATCHING OPTIMAL
RESOURCE
ALLOCATION

, ,'User
Specific
Resource or

lID

m
PROGRAMMING
PATTERN
GENERATION

JEDEC'
Data
file
296032-6

Figure 6. The PLD Design Process

1-4

inter

OVERVIEW

The steps in a generalized design process of programmable logic is shown in Figure 6 and described in the
following paragraphs.

"JEDEC" format interface and allows the output of the
design software to be compatible with any piece of
PROM programming hardware.

STEP 1: The user decides on the logic he wants implemented in the PLD and enters the design into the PC or
workstation. This Design Entry may be done by the
following methods: (i)SCHEMATIC CAPTURE-A
'Mouse' or some other graphics input device is used to
input sc~ematics of the logic, (ii)NET LIST ENTRYIf the user has a hand drawn schematic he can enter the
design into the computer by describing the symbols and
interconnections in words using a standardized format
called a net list (without using a graphics input device),
(iii)STATE EQUATION/DIAGRAM ENTRY-Entry of a sequential design involving states and transitions between states. In the state diagram method circles represent states' and the arrows interconnecting
them represent the transitions. Equations or a state table can also be used to define a state machine, and
(iv)BOOLEAN EQUATIONS-this is the most qommon design entry method. The logic is described in
boolean algebraic equations.

STEP 8: PROM programmer is used to program the
pattern stored in the JEDEC file onto the PLD. Also,
at this stage fuse programmed PLDs (bipolar) are functionally tested using test vectors included in the JEDEC file information.

CHMOS TECHNOLOGY IN EPLDs
EPLDs are manufactured with Intel's proprietary
CHMOS (Complementary High Performance MaS)
technology. The backbone of the process is the integration of both a P and an N channel MaS transistor on
the same substrate. In addition, EPLD's programmable
architecture makes use of Intel's proven EPROM cell
for programmable array interconnections as well as
macrocell configuration bits. These cells are programmed electrically and erased with ultraviolet light.
For details on Intel's CHMOS technology and
EPROM cells technology, refer to the Components
Quality/Reliability Handbook, Order Number 210997.

STEP 2: The software converts all design entry data
into boolean equations.

CHMOS DESIGN GUIDELINES

STEP 3: The boolean equations entered are converted
to the sum of products format after logic reduction
(minimization of the logic through heuristic algorithms).

Designing with Intel EPLDs is relatively straightforward if the following guidelines are observed:
• Minimize the occurrence of ESD (electro-static discharge) when storing or handling EPLDs.
• Observe good design rules in printed circuit board
layout. '

STEP 4: The user has the ability to choose the PLD he
would like the design implemented on. He can enter
device choice and/or he can also enter in specific
choices on the device as regards pinout he would like
etc ...

• Provide adequate decoupling capacitance at both
the device and the board level.

STEP 5: The software optimizes the logic equations to
fit into the device using the minimum amount of resources (resources are input pins, output pins, registers
and product terms and macrocells). This step is where
the user requirements as regards required pins are taken into account. The user requests are viewed as constraints during the optimization process:

• Connect all unused inputs to Vee or GND
(CHMOS inputs should not be left floating).

Electrostatic Discharge
The two, most common sources of electrostatic discharge are the human body and a charged environment.

STEP 6: The software, at the end of the resource optimization/allocation, produces a report detailing the resources used up in fitting the design on the PLD. This
report allows the user to incrementally stuff in logic by
going back to Step 1 from this stage. Also, if the design
overflowed the PLD, i.e., did not fit in the user chosen
device, the software lists out the resources needed to
complete the fit. The requirements such as four more
inputs, one register more and one more output (are
needed to complete the design) gives the user data in
choosing a bigger PLD or in partitioning the intial design to fit into two devices.

A charged human body that touches a, device lead
discharges electricity into the device. Elect~ostatic discharge from people handling devices has long been rec, ognized by manufacturers and users of all MaS products. Human body static electricity can be controlled by
using ground straps and anti-static spray on carpeted
floors. CHMOS devices should also be stored and carried in conductive tubes or anti-static foam to minimize
exposure to ESD from people.
Discharge also occurs when an integrated circuit is
charged to one potential and then contacts a conductor
at another potential. This type of ESD can be reduced

STEP 7: The next step is to generate the appropriate
programming pattern for the PLD. This is a standard

1-5

intJ

OVERVIEW

by grounding all work surfaces, grounding all handling
equipment, removing static generators such as paper
from the work area, and erasing EPLDs in metal tubes,
metal trays, or conductive foam.

Tabular methods like Karnaugh maps are efficient up
to a certain point. Past that point, however, computerassisted minimization plays a crucial part in efficient
design. Even at the computer-assisted stage, the choice
of minimizer software has an impact on time and the
confidence level of the reduced equation (i.e., is itin the
smallest possible form).

PCB Layout
The best PCB performance is obtained when close attention is payed to Vco GND, and signal traces. Vee
and GND should be gridded to minimize inductive
reactance and to approximate a· trace layer. Clocks
should be layed out to minimize crosstalk. Ensure adequate power supply and ground pins on the board connector.

iPLS II software includes a minimizer that uses the
ESPRESSO algorithms. ESP.RESSO was developed by
U.C. Berkeley during the summers of 1981 and 1982 in
an effort to study the various strategies used by the
MINI logic minimizer developed by IBM , [HON 741
and PRESTO developed by D. Brown [BRO 811.
ESPRESSO uses many of the core principles in MINI
and PRESTO while improving on the speed and efficiency .of their algorithms.

Oecoupling
The primary advantage of the ESPRESSO minimizer
becomes apparent when designing large finite state machi~es or complex, product-term intensive logic designs. In these cases, ESPRESSO arrives at the minimize solution sooner, and frequently reduces the logic
to a smaller number of product terms. In certain cases
where other CAD packages such as ABELTM (PRESTO) or CUPLTM minimize equations to greater than 8
product terms, iPLS II further reduces these equations
to allow the design to fit into devices supporting up to 8
product terms.

Decouple each EPLD with a ceramic capacitor in the
range of 0.01 to 0.2 /LF, depending on board frequency
and current consumption. For most applications, a
0.1 /LF capacitor will suffice. The. following equation
produces the exact value:
C = LlICC
LlVILlT

where

C· =
LlIce =
Ll V =
Ll T =

capacitor value
maximum switched current
switching level

For more information on ESPRESSO, refer to Logic
Minimization Algorithms for VLSI Synthesis, Brayton,
Hachtel, McMullen,. and. Sangiovanni-Vincentelli, Kluwer Academic. Publishers.
'

switching time

For boards that contain mixed logic (EPLDs and
TTL), observe both EPLD and TTL decoupling practices.

References
[BRO 811

D.W. Brown, "A State-Machine Synthesizer-SMS", Proc. 18th Design Automation
Conference, pp. 301-304. Nashville, June.
198L
[HON 741 S. J. Hong, R. G. Cain and D. L. Ostapko,
"MINI: A heuristic approach to logic minimization." IBM Journal of Research and
Development, Vol. 18, pp. 443":458, September 1974.

Unused Inputs
To minimize noise receptivity and power consumption,
all unused inputs to EPLDs should be connected to
Vee or GND. By default, iPLS II software assigns unused inputs to GND. These pins, shown on the pinout
representation of the iPLS II report file, should be connected to ground on the PCB. Pins listed as RESERVED on the report file must be left floating. Pins
marked N.C. have no internal device connections and
can also bt; left floating.

ABELTM is a trademark of Data 1/0 Corporation
CUPLTM is a trademark of Personal CAD Systems. Inc.

BOOLEAN MINIMIZATION
TECHNIQUES FOR PLA
ARCHITECTURES

LOGIC REFRESHER COURSE
Minimization of EPLD logic equations is normally performed by sophisticated algorithms that eliminate the
need for tedious manuai reductions. The sections provided here contain logic reference tables for cases where
manual reduction techniques may be desirable.

Minimization plays an important role in logic. design.
Methods for minimization can be grouped into two
classes. Class 1 includes manual methods for minimization, such as Boolean reduction or Karnaugh mapping.
Class f is computer-assisted minimization.
1-6

OVERVIEW

Boolean Algebra

Karnaugh Maps

The Sum-of-Product architecture used in EPLDs
makes Boolean algebra ideal for design analysis. The
following tables summarize standard Boolean functions.

Graphical representation of data is usually easier to analyze than strings of ones and zeros. The Karnaugh
Map techniques take advantage of this capability and
provide an important tool to the logic designer.

Properties

= 8' A

A'8
A+8

Commutative Property

=8+A

A • (8 ' C)

= (A * 8) • C

Two Variables

_Associative Property

A + (8 + C) = (A + 8) + C
A • (8 + C) = A * 8 + A * C
Distributive Property
A + 8 * C = (A + 8) * (A + C)

296032-7

Postulates
Three Variables

O' 0 = 0
0*1 = 0
1• 1 = 1

0+0=0
0+1 = 0
1+ 1= 1

0=1

1=0

Theorems

A' 0 =
A *1 =
A *A =
A*A =

0
A
A
0

A+O=A
A+1=1
A+A=A
A+A=1

296032-8

A=A
Four Variables

DeMorgan's Theorems

(A + B + C + 0)
(A * B • C • 0)

A*S*C"O
A+S+C+O

Logic Functions

A"A
A+A
A Ell B

A NOT
=

A EXCLUSIVE OR B

5 139

7 15 11

6 14 10

4 12 8

296032-9

AANDA
AORA

DO 01 11 10
00

AS+AB

1-7

intJ

OVERVIEW

Five Variables

BC
DE

A=O

A=l

00011110

0001 11 10

BC
OE

4 12 8

16 20 2824 00

5 13 9

17 21 2925 01

7 15 11

19 23 31 27 11

6 14 10

18 22 3026 10
296032-10

Six Variables

CD
EF
00

A=O

B=O

B=l

00 01 11 10

4 12 8

CD
EF

16 20 28 24 00

5 13 9

17 21 29 25 01

7 15 11

19 23 31 27 11

6 14 10

18 22 30 26 10

00 32 36 44 40

48 52 60 56 00

01 33 37 45 41

49 53 61 57 01

11 35 39 47 43

51 55 63 59 11

10 34 38 46 42

, 50 54 62 58 10

00 01 11 10

296032-11

T Truth Table

Flip-Flop Tables
This subsection includes truth tables and excitation tables for the flip-flops silpported by EPLDs.
D Truth Table

QN+1

0
0

1
1

QN+1

0
0

1
1

T Excitation Table

1
1

D Excitation Table

QN+1

0
0

.1
1

1-8

QN+1

0
0

1
1

OVERVIEW

when input transitions are not detected over a short
period of time. The following paragraphs describe how
the Turbo Bit atTects power and speed in EPLDs.

JK Truth Table
J

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ON+1
0
1
0
0
1
1
1
0

Turbo Off (Low Power)
Intel EPLDs contain circuitry that monitors all·inputs
for transitions. When' a transition is detected while the
device is in standby mode, the circuit generates an active pulse. The leading edge of this pulse wakes the
device up and the device responds according to its programming, changing outputs as necessary. If no new
transitions occur during the active pulse, the device enters standby mode again. Outputs are always held valid
in standby mode. Input transitions that occur during
the active mode interval" retrigger the active pulse. The
active pulse is ditTerel).t depending on the device
(5C060, 5AC312, etc), but is typically 2-4 times the
propagation delay for a particular device.

JK Excitation Table

ON
0
0
1
1

ON+1
0
1
0
1

0
1
X
X

X
X
1
0

In applications with infrequent input transitions, standby mode can result in significant power savings (S\!f: the
appropriate data sheet for standby power vs. active
power). The slight speed loss associated with waking up
a device is in the range of 0-10 ns, ,which is small
enough' to allow standby mode to be used with. most
applications (see the appropriate data sheet for etTect of
Turbo Bit on performance).

SR Truth Table

0
0
1
1

0
0
1
1
0
'0

0
1
0
1
0
1

O·

ON+1
0
1
0
0
1
1'
illegal

JK Excitation Table

ON
0
0
1
1

ON+1
0
1
.' 0
1

0
1
0

X
0
1
0

" .x

Turbo On (Faster Speed)
In cases where the slight speed loss associated with
. waking a device from standby .I:Ilode can!lot be traded
otT to save power, the Turbo bit can be enabled for
maximum speed operation. With the Turbo Bit- en'abled, the device is always in active mode, thus avoiding the wakeup delay. Note that data sheet performance is specified with the Turbo Bit enabled.
. The Turbo Bit is enabled/disabled via a TURBO =
ON or TURBO = OFF statement in an iPLS II ADF
OPTIONS: statement. It can also be enabled/disabled
by editing the JEDEC file using device programmable
software. With TURBO = ON the device will be programmed for high speed; with TURBO = OFF the
device will be' programmed for automatic staridby
(power savings). The default state is OFF.

NOTES:
QN = Present State
QN + 1 = Next State
X = Don't Care

AUTOMATIC STANDBY MODE
(TURBO Bin

PACKAGING

INTEL EPLDs contain a programmable bit, the Turbo
Bit, that optimizes devices for speed or power savings.
When TURBO = ON, EPLDs are optimized for
speed. When TURBO = OFF, they are optimized for
power savings by automatically entering standby mode

Intel EPLDs are available in several packages to meet
the wide requirements of customer applications. Current information on available packages is available from
your local.lntel field sales engineer. Detailed information on package dimensions, etc: for a particular package is provided in Packaging Outlines and Dimensions,
Order Number 321369, which covers all Intel packages.
1-9

OVERVIEW

ORDERING INFORMATION
Intel EPLDs are identified as follows:

'---.,-J

X
Device

""....
- ----__-.,-_____1

Speed

Technology
C -CHMOS
AC- Advanced CHMOS

A J -

L *M Q T -

Package Type
A - Hermetic, Pin Grid Array
D - Hermetic, Type D (Cerdip) Dip
N - Plastic, Leaded Chip Carrier
CJ - Ceramic, J Leaded Chip Carrier
P - Plastic Dip and Plastic Flatpack
R - Hermetic, Leadless Chip Carrier
X - Unpackaged Device
Indicates automotive operating temperature range (-4Q'C to + 125'C)
Indicates a JAN qualified device, but is for internal identification purposes only. All JAN devices must be
ordered by M38510 part number. (Example: M38510/42001 BQB), and will be marked in accordance
with MIL-M-3851O specifications.
Indicates extended operating temperature range (- 40'C to + 85'C) express product with
160 + 8 hrs. dynamic bum-in.
Indicates military operating temperature range (- SS'C to + 12S°C)
Indicates commercial temperature range (O°C to 70'C) express product with 160 + 8 hrs. dynamic burn-.
in.
Indicates extended temperature range ( - 4Q°C to + 8S°C) express product without burn-in.
No letter indicates commercial temperature range (O°C to 70°C) without burn-in.

Examples:
QDSC060-45 Commercial with burn-in, ceramic Dip, 060 (600 gate) device, 45 nanosecond.
'On military temperature devices, B suffix indicates MIL-STD-883C level B processing.

1-10

EPLDs Erasable Programmable
Logic Devices

5C031
300 GATE CHMOS H-SERIES ERASABLE
PROGRAMMABLE LOGIC DEVICE (H-EPLD)
• CHMOS EPROM Technology Based UV
Erasable.

•

High Performance, Low Power
Replacementfor SSI & MSI Devices
and Bipolar PLDs.

•

Up to 18 Inputs (10 Dedicated & 8 I/O)
and 8 Outputs.

•

Eight Macrocells with Programmable
I/O Architecture.

•

100% Generically Testable EPROM
Logic Control Array.

•

High Performance Upgrade for All
Commonly Used 20-pin PLDs.

•

Programmable "Security Bit" Allows
Total Protection of Proprietary Designs

•

Icc (standby) 35 rnA (max)
Icc (10 MHz) 40 rnA (max)

• tpb

40 ns (max)
20-pin 0.3" Windowed CERDIP Package

(See Packaging Spec., Order # 231369)

100% Compatible with EP310

Vee
I/O
I/O
I/o
I/O
I/O
I/o
I/o
I/O
I/Vpp

INPUT/elK
INPUT
INPUT

INPUT
INPUT
INPUT
INPUT
INPUT

GND

290154-1

Pin Configuration

2-1

October 1988
Order Number: 290154'()02

5C031

The Intel 5C031 H-EPLD. (H-series Erasable Pro-.
grammable Logic Device) is capable of implementing over 300 ~quivalent gates of 'user-customized
logic functions through programming: This device
can be used to replace bipolar programmable logic
arrays and LS TTL and 74HC (CMOS) ssf and MSI
logic devices. The 5C031 can also be used as a
direct, •low-power replacement for. almost all common 2Q-pin fuse-based program'mable logic devices.
With its' flexible programmable 1/0 architecture, this
device has advanced functional capabilities beyond
that of typical programmable logiC.
'

ARCHITECTURE DESCRIPTION

The architecture of the 5C031 is based on the "Sum
of Products" PLA (Programmable LogiC Array) struc- .
ture with Ii programmable AND array feeding into Ii
fixed OR array: This device can accommodate both
combinational and sequential iogic functions.' A proprietary programmable 1/0 architecture provides individual selection of either combinational or registered output and feedback signals, all with select.
able polarity.
The 5C031 contains 10 dedicated inputs as well as 8
input/output pins. These 1/0 pins can be individually
configured to be inputs, outputs or bi-directionall/O
pins. Each of these 1/0 pins is connected to a macrocell. The 5C031 contains 8 identical macrocells organized as shown in Figure 1.,.

The 5C031 H-EPLD uses CHMOSEPROM (floating
gate) cells as logiC control elemel)ts instead. of fuses. The CHMOS EPROM technology reduces power
consumption of H-EPLDs to less than 20% of a
comparable bipolar device without .sacrificing speed
performance. In addition, the use of Intel's advanced
CHMOS II-E EPROM process technology enables
greater logic densities to be achieved with superior
speed and low-power performance over other comparable devices. EPROM technology allows these
devices to be 100% factory tested by programming
and erasing all the EPROM logic control elements.
The 5C031 is. housed in a windowed 0.3" 20-pin DIP
and has the benefits of being an ideal protoWping .
tool with its highly flexible 1/0 architect~re.
.

2-2

Each macrocell (see Figure 2) consists of a PLA
(programmable logic array) block and an 1/0 architecture block; which contains a "D" type register.
The PLA block consists of eight 36-input AND gates
(TRUE &' COMPLEMENT of 10 dedicated inputs
plus the 8 feedback inputs from the eight macrocells), feeding into an OR gate. The output of this
PLA block is fed into the 1/0 architecture block. The
different 1/0 and feedback options that are achievable. from the 5C031 1/0 block are shown in
Figure 3.

SC031

CLOCK .Q.

PLA BLOCK

290154-2

Flgure1.1CG31 Architecture

2-3

l
CLOCK

5
4

7
6

15 . 17
19
21
23·
25
27
}9
• ~1
. 3~
,~5
14
16
18
20
22
24
26
28
30
32
34

OE I

-D

"1'1

.g:
iil

V')

:::E

I-

(;'

~
....

~
~I

, C)

!:.

D)') T

•. '

i'
I\)

.' .

.
,

.,'

-D
D'
D -.

Db- . ,;"'"'". W
~

)

' .•

:. 4

l~ .~ ~

'i9

~ i.

~ I.

RESET-

~ A

~ I.

15.

____

______________________

__________________________________________________

PLA BLOCK

,
..

l.~

iiO

.'-

Dli

; .

NOTE []=I/O PIN IN WHICH LOGIC ARRAY INPUTISFROM FEEDBACK PATH
~~~

CONTROL'

4~ ~ c~ ~ ~ c~ ~. ~ c~ ~,~ . c~ ~ ~. ~ c~. 4~ ~ c~ D
~.'

.PRESET CLOCK

____

~~"~

________________________

I/O ARCHITECTURE
BLOCK
290154-3

CI1

...w

inter

5C031

p--------------------------.

,,,
,,
,,
,

PRODUCT
TERMS

OUTPUT
SELECT

PRESET

RESET

,,,
,
,
,,

FEEDBACK
SELECT

FEEDBACK

--------~-----------------.
290154-4

Figure 3. 5C031 1/0 Architecture Control

20 PIN CMOS COMPATIBILITY
The 5C031 is architected to be a logical superset of most 20 pin bipolar programmable array logic (PAL *)
devices. The I/O and logic sections of the 5C031 device can be configured to emulate any of the devices
listed below. Designers can make use of this feature by reducing the power of PAL based systems (EPLDs are
much lower power), replacing multiple PAL inventory items with a single EPLD. Designers can also create new
20 pin PLD configurations by utilizing the individual logic and ,output controls of each macrocell.
List of PAL devices logically compatible with the 5C031.
10H8
16L2
12H6
16L8
14H416R8
16H2
16R6
16H8
16R4
16C1
16P8A
10LB
16RP8A
12L6
16RP6A
14L4
16RP4A
'PAL is a registered trademark.of MonolithicMemories, Inc.

2-5

infef

5C031

The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each bit is continually monitored to determine when the bit has
been successfully programmed.

Erased-State Configuration
Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output
with input (pin) feedback.
.

ERASURE CHARACTERISTICS
FUNCTIONAL TESTING

Erasure characteristics of the 5C031 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
flourescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room
level flourescent lighting could erase the typical
5C031 in approximately three years, while it would
take approximately one week to cause erasure when
exposed to direct sunlight. If the 5C031 is to 'be exposed to these. types of lighting conditions for extended periods of time, conductive opaque labels
should be placed over the device window to prevent
unintentional erasure.

Since the logical operation of the 5C031 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of the EPROM array are
required.

The recommended erasure procedure for the 5C031
is exposure to shortwave ultraviolet light with a
wavelength of 2537A. The integrated dose (Le., UV
intensity X exposure time) for erasure should be a
minimum of fifteen (15) Wsecl cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W I cm 2
power rating. The 5C031 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the 5C031 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week at
12,000 p.W/cm 2). Exposure to,high intensity UV light
for longer periods may cause permanent damage to .
the device.

PROGRAMMING CHARACTERISTICS
Initially, and after erasure, all the EPROM control
bits of the 5C031 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cells into
their "0" state. Programming voltage and waveform'
specifications are available by request from Intel to
support programming of the 5C031.

The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming. These tests must be done at
the device level because of thecummulative error
effect. For example, a board containing ten devices
each possessing a 2% device fallout translates into
an 18% fallout at the board level (it should be noted
that programming fallout of fuse-based programmable logic devices is typically 2% or higher).

DESIGN RECOMMENDATIONS.
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND <: (VIN or VOUT) < Vee. Unused inputs
should be tied to an appropriate logic level (e.g. ei. ther Vee or GND) to minimize device power con. ,sumption. Reserved pins (as indicated in the iPLDS
REPORT file) should be left floating (no connect) so
that the pin can attain the appropriate logic level. A
power supply decoupling capacitor of at least 0.2 p.F
must be connected directly between Vee and GND
pins of the device.

inteligent Programming™ Algorithm
The 5C031 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method .

.2-6

As with all CMOS devices, ESD handling procedures
should be used with the 5C031 to prevent damage
to the device during programming, assembly, and
test.

inter

5C031

code output files which can be downloaded to other
.
programmers as well.

DESIGN SECURITY
A single EPROM bit provides a programmable design security feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

The iPLDS /I has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMA II-PLD, a low-cost
schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA I/-PLD and iPLS /I software. The other design formats supported are Boolean equation entry
and State Machine design entry.

LATCH"UP IMMUNITY

The iPLDS operates on the IBMt PC/XT, PC/AT, or
other compatible machine with the following configuration:

All of the input, I/O, and clock pins of the SC031
have been designed to resist latch-up which is inherent in inferior CMOS structures. The SC031 is designed with Intel's proprietary CHMOS II-E EPROM
process. Thus, each of the SC031 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore,
the programming pin is designed to resist latch-up to
the 13.SV maximum device limit.

1. At least one floppy disk drive and hard disk drive.
2. MS-DOStt Operating System Version 3.0 or
greater.
3. S12K Memory (640K recommended).
4. Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS).
S. A color monitor is suggested.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)

Detailed information on the Intel Programmable Logic Development System" is contained in a separate
Intel data sheet. (Order Number: 280168)

iPLDS /I provides all the tools needed to design with
IntelH-Series EPLDs or compatible devices. In addition to providing development ,assistance, iPLDS /I
insulates the user from having to know all the intricate details of EPLD architecture (the machine will
optimize a design to benefit from architectual features). It contains comprehensive thi;d generation
software that supports four different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.

tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
INP
CONF
COCF
CORF
COIF.
NOCF

In addition, the iPLDS /I contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object

RONF
ROCF
RORF
ROlF
NORF

ORDERING INFORMATION
tpD
(ns)

teo
(ns)

(MHz)

Order
Code

Package

Operating
Range

29.S

DSC031-40

CERDIP

Commercial

22.5

D5C031-50

CERDIP

Commercial

fMAX

2-7

inter·

5C031

*Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of. the device at tl1ese or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Parameter

Min

Units

Max

Vee

Supply Voltage(1)

-2.0

7.0

Vpp.

Programming
Supply Voltage(1)

-2.0

13.5

DC Input Voltage(1 )(2)

-0.5 Vee+ 0.5

tstg

Storage Temperature

-65

+150

tamb

Ambient Temperature(3) -10

+85

'c
'c

NOTES:
1. Voltages with respect to ground.
2. Minimum DC input is - 0.5V. During transitions, the inputs may undershoot to - 2.0V or overshoot to 7.0V for
periods less than 20 ns under no load cOrjditions.
3. Under bias. Extended temperature versions are also
available.

RECOMMENDED OPERATING CONDITIONS
Symbol
Vce

Parameter
Supply Voltage

Min

Max

Unit

4.75

5.25·

VIN

Input Voltage

Vee

Output Voltage

Vce

Operating Temperature

+70

Input Rise Time

500

Input Fall Time

500

DC CHARACTERISTICS
Symbol

T A - 0' to + 70°C , Vee - 5V +
- 5%

Parameter/TestConditions

Min

Typ

Max

Unit

VIH(4)

High Level Input Voltage

2.0

Vcc+ 0.3

VIL(4)

LoW Level Input Voltage

-0.3

0.8

VOH(5)

High Level Output Voltage
10 = -4.0 rnA D.C., Vee = min.

VOL

Low Level Output Voltage
10 = 4.0 mA D.C., Vcc= min.

0.45

Input Leakage Current
Vcc = max., GND < VIN

±10

p.A

2.4

< Vec

2-8

inter

5C031

D.C. CHARACTERISTICS
Symbol

0° to

+ 70°C, Vee =

5V ± 5% (Continued)

Parameter/Test Conditions
Output Leakage Current
Vee = max., GND < VOUT

loz

Min

Typ

Max

Unit

±10

p.A

< Vee

Isel6) .

Output Short Circuit Current
Vee = max., VOUT = 0.5V

lee.

Power Supply Current
Vee = max., VIN = Vee or GND
No Load, Input Freq. = 1 MHz
Active mode (Turbo = 011)
Device prog. as a-bit Ctr.

NOTES:
4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included.
5.10 at eMOS levels (3.84V) = -2 mA.
6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

~---5V

INPUT

DEVICE [:>-+-.....--C> TO TEST
OUTPUT
SYSTEM

OUTPUT

l~~TEST POINTS-~
290154-7

341.0.

A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and 0.8V for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times < 6 ns.

290154-6

CAPACITANCE
Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CIN

Input Capacitance

VIN = OV, f = 1.0 MHz

pF'

COUT

Output Capacitance

VOUT = OV, 1= 1.0 MHz

CeLK

Clock Pin Capacitance

VIN = OV,I = 1.0 MHz

Cvpp

Vpp Pin

Pin 11

2-9

inter

5C031

A.C. CHARACTERISTICS
Symbol

From

= O~C to

+ 70·C, Vcc

5V ± 5%, Turbo Bit Programmed(7)

5C031·40
EP310·3

To
Min

Typ

5C031·50
EP310
Max

Min

Typ

Unit
Max

tpD

I/O

Comb. Output

tpZX(B)

lor I/O

Output Enable

tpXZ(B)

lor I/O

Output Disable

tClR

Asynch Reset

Q Reset

NOTES:
7. Typical Values are at TA = 25'C, Vee =5V, Active Mode
B. tpzx and tpxz are mea~ured at ± O.5V from steady state voltage as driven by spec. output load. tpxz is measured with
CL = 5 pF.
.

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
TA = O·C to + 70·C, VCC = 5.0V ± 5%, Turbo Bit On(7)

Symbol

5C031·40
EP310·3

Parameter
Min

Typ

5C031·50
EP310
Max

Min

Typ

Unit
Max

tMAX

Max. Frequency (Pipelined)
1 /(tCl+ tCH)- No Feedback.

29.4

22.7

MHz

tCNT

Max. Count Frequency
1 /tCNT - With Feedback

22.2

18.1

MHz

tsu

I/O Setup Time to ClK

I or I/O Hold after ClK High

tco

ClK High to Output Valid

tCNT

tCH

ClK High Time

tCl

ClKlowTime

tSET

Synch. Setto Q Set

22
40

2-10

ns
50

5C031

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/o INPUT

COMBINATORIAL OUTPUT

~'''~
I.--

COMBINATORIAL OR
REGISTERED OUTPUT

tpxz ---..

HIGH IMPEDANCE
3- STATE

I
tpzx

HIGH IMPEDANCE
3- STATE

VALID OUTPUT

tCLR

i\.

ASYNCHRONOUSLY
CLEAR OUTPUT
290154-6

SYNCHRONOUS CLOCK MODE

CLK1

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290154-9

2-11

5C031

5C031 Current in Relation to Frequency
100
90
80
70

-:c

!.
0

.!:'

.--

40
30

.--I-'"

i"""

20
10

o
o

to (MHz)
290154-10
Conditions: TA '"

PLA BLOCK

J ILlIJ LlLU U Ll1

I/O'
ARCHITECTURE'
CONTROL CK

ULLlIJ LlIIJ U 11JU

PLA BLOCK

I'
I/O'
-1 ARCHITECTURE

CONTROL CK
6

PLA BLOCK

I/O
f- ARCHITECTURE

CONTROL CK
7

lli

PLA BLOCK

I/O·
f- ARCHITECTURE

CONTROL CK

8 D-f

PLA BLOCK

,
9

I/O

f- ARCHITECTURE

~.12

CONTROL CK :

1
·1
290155-2

Figure 1. 5C032 Architecture
2-15

l
, CLOCK

3
2

7
6"

9
8

11
:10

13
'12

17
16

21
20

23
22

25
24

27
26

29
28

31
30

33
32

35
34

~l.

"
l!

IQ
C

;

W 3

n
.!.. :..

o0::

=I
~

-Do.

0..5

i!'

I-

IS.

'0::

or-

I\)

-D~
-D '
D)

2
VI

:::E

'CO" .
AAOHO'Cru"
CONTROL

:.'~

~--t-....-I:::> SYSTEM

OUTPUT

.1:!J,.-

TEST POINTS

-'!iii
290155-7

341.0.

AC. Testing: Inputs are Driven at 3.0V for a LogiC "I" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"I" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.5V point Device input rise and fall limes < 6 ns.

290155-6

CAPACITANCE
Symbol

Parameter

Conditions

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

CCLK

Clock Pin Capacitance

VIN

CvPp

VppPin

Pin 11

OV, f

Max

Unit

1.0 MHz

Min

Typ

intJ

5C032

A.C. CHARACTERISTICS
Symbol

= O°C to + 70°C, VCC = 5V ± 5%, Turbo Bit On(10)

5C032-25

Non-(S)
Turbo
Mode

Unit

+15

5C032-3D

5C032-35

From

tpD

lor I/O

Comb. Output

tpZX(11)

lor I/O

Output Enable

tpxz(11)

lor I/O

Output Disable

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

NOTES:
10. Typ. values are at TA = 25°C, Vcc = 5V, Active Mode.
11. tpzx and tpxz are measured at ± 0.5V from steady state voltage as driven by spec. output load. tpxz is measured with
CL = 5 pF.

A.C. CHARACTERISTICS

TA = O°C to WC, VCC = 5V

± 5%, Turbo Bit On (10)

SYNCHRONOUS CLOCK MODE
Symbol

5C032-30
EP320-1

5C032~25

Parameter

5C032-35
EP320-2

Min Typ Max Min Typ Max Min Typ Max
fMAX

Max. Frequency (Pipelined)
1 /tsu - No Feedback

tCNT

Max. Count Frequency
1 /tCNT - with Feedback

tsu

Input Setup Time to ClK

I or I/O Hold after ClK High

Non-(S)
Turbo Unit
Mode

43.5

MHz

33.3

28.5

MHz

ns
ns

tco

ClK High to Output Valid

tCNT

tCH

ClK High Time

tCl

ClKlowTime

2-23

+15

ns
+15

inter

5C032

SWITCHING WAVEFORMS
COMBINATORIAL MODE
,
INPUT OR

I/o INPUT

COMBINATORIAL OUTPUT

~~I
I---- tpxz

COMBINATORIAL OR
REGISTERED OUTPUT

---'-+

HIGH IMPEDANCE
3- STATE

I---- tpzx - - ,
HIGH IMPEDANCE
3- STATE

VALID OUTPUT
290155-8

SYNCHRONOUS CLOCK MODE

CLK1

INPUT MAY CHANGE

INPUT MAY <;:HANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290155-9

2-24

inter

5C032

Current in Relation to Frequency

Current in Relation to Temperature
50r----r----r---~----"

50
40

. /~

30
20
10

40~--_r----r_---+----~

/'
"<

V
(TURB/ ' /

P,t

~--_r----r_--~-=:~

-5
~ 20!---t-~~~~~::jj

'{NON-TURBO

o
o

10 15 20 25 30 35 40

80 85

TEMP(C)

fCNr
o
.
_0.8

T,EST POINTS

-< )(;20.
•

O.B

c:-........-C> SYSTEM
TO TEST
341,(l

CL (INCLUDES JIG
CAPACITANCE)

OUTPUT

~- - - TEST POINTS --'----~

290194-14
A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for ,
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.SV point. Device input rise and fall times < 6 ns.

290194-13

CAPACITANCE
Symbol

Parameter

Conditions

Min

Typ

= OV, f = 1.0 MHz

Max

Unit

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

CCLK

Clock Pin Capacitance

= OV, f = 1.0 MHz
VIN = OV, f = 1.0 MHz

Cvpp

Vpp Pin

CLK2 on 5C060

A.C. CHARACTERISTICS

O°C to 70°C, VCC

5V ± 5%, Turbo Bit On(9)

Device
Symbol

From

5C060-45
EP600-3

To
Min

Typ

5C060-55
EP600
Max

Min

Typ

Non-(11)
Turbo
Mode

Unit

Max

tpD1

Input

Comb. Output

+25

tpD2

1/0

Comb. Output

+25

tpZX(10)

lor 1/0

Output Enable

+25

tpXZ(10)

lor 1/0

Output Disable

+25

tClR

Asynch. Reset

Q Reset

+25

NOTES:
9. Typical Values are at TA =, 25'C, Vce = 5V, Active Mode.
10. tpzx and tpxz are measured at ± O.5V from steady state voltage as driven by spec. output load. tpxz is measured with
CL = 5 pF.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown.

2-38

5e060

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC
TA = O°C to 70°C, vcc = 5.0V ±5%, Turbo Bit On(9)
Device
Symbol

5C060-45
EP600-3

Parameter
Min

Typ

Non-(11)
Turbo
Mode

5C060-55
EP600
Max

Min

Typ

Unit

Max

fMAX

Max. Frequency (Pipelined)
(1 Itsu-No Feedback)

26.3

23.3

MHz

fCN:r

Max. Count Frequency
(1/tCNT-With Feedback)

22.2

18.2

MHz

tSUl

Input Setup Time to ClK

+25

tSU2

1/0 Setup Time to ClK

+25

I or 1/0 Hold after ClK High

tco

ClK High to Output Valid

tCNT

tCH
tCl

0
25

ns
+25

ClK High Time

17.5

21.5

ClKlowTime

17.5

21.5

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
= O°C to 70°C, vcc = 5.0V ±5%, Turbo Bit On(8)

Device
Symbol

5C060-45
EP600-3

Parameter
Min

Typ

Non-(ll)
Turbo
Mode

5C060-55
EP600
Max

Min

Typ

Max

18.2

22.2

Unit

MHz

fACNT

Max. Count Frequency
(1/tACNT-With Feedback)

tASUl

Input Setup Time to
Asynch. Clock

+25

tASU2

1/0 Setup Time to
Asynch. Clock

+25

tAH

Input or 1/0 Hold After
Asynch. Clock

tACO

Asynch. ClK to Output Valid

tACNT

tACH
tACl

ns
+25

+25

Asynch. ClK High Time

17.5

21.5

+25

Asynch. ClK low Time

17.5

21.5

+25

2-39

inter

se060

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

~~"~
I - tpxz - - -

(FROM REGISTER
TO OUTPUT)

HIGH IMPEDANCE
3 - STATE

rtpzx--oo
HIGH IMPEDANCE
3- STATE

~~~

VALID OUTPUT

ASYNCHRONOUSLY
CLEAR OUTPUT
290194-'15

SYNCHRONOUS CLOCK MODE

I,:tCH:::j

CLK1,CLK2

. ~l . . .___

INPUT MAY CHANGE

INP~T

MAY CHANGE

I-teo
(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290194-16

2-40

inter

se060

SWITCHING WAVEFORMS (Continued)
ASYNCHRONOUS CLOCK MODE

ASYN. - - - - " " " '
CLOCK
INPUT _ _ _ _- '

OTHER
INPUT

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT
290194-17

5C060
Current in Relation to Frequency

5C060
Current in Relation to Temperature

120

110
100
. 90
80

•

290195-2

INPUT?
CLK2
290195-1

Figure 1. 5C090 Pin Configurations

2-42

November 1988
Order Number: 290195-001

seogo
devices. Intel's H-ELPDs add the benefits of "zero"
stand-by power not available on other programmable logic devices. EPROM technology allows these
devices to be 100% factory tested by programming
and erasing all the EPROM logic control elements.

The Intel 5C090 H-EPLD (H-series Programmable
Logic Device) is capable of implementing over 900
equivalent gates of user-customized logic functions
through programming. The device can be used to
replace low-end gate arrays, multiple programmable
logic arrays and LS TTL and 74HC (CMOS) SSI and
MSllogic devices. With its revolutionary programmable I/O architecture, the device has advanced functional capabilities beyond that of typical programmable logic.

The erasability of EPLDs introduces the designer to
a new concept in hardware design called Modular
EPLD Logic Design (MELD). Just as modular software design speeds development time and reduces
errors by isolating them to a specific module, the
MELD philosophy aids in hardware design. A designer can develop his modular design on the Intel Programmable Logic Development System II (iPLDS II)
and test individual modules for functionality. If one of
the modules has a design flaw, the designer merely
erases the part and starts anew (since the 5C090 is
EPROM-based, there is no waste associated with
modular design as there would be in fuse-based
PLDs).

The 5C090 H-EPLD uses CHMOS EPROM (floating
gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power
consumption of H-EPLDs to ,less' than 20% of a
comparable bipolar 'device without sacrificing speed
performance. In addition, Intel's advanced CHMOS
II-E EPROM process technology enables greater
logic densities to be achieved with superior speed
and low-power performance over other comparable

AND ARRAY

SYNCHRONOUS
CLOCK
OE/ClK

vcc

l~ElECT
DE

I--

0-K

t--

' - - I--

ClK

EPROM
CONTROL
BIT

8=
8=
D8=
-D-

OUTPUT
REGISTER

~
OUTPUT
BUFFER

,~ ,~

L.zI-v

INPUTS AND

I/o

I
290195-3

Figure 2. Basic Macrocell Architecture of the SeOgO

2-43

inter

seogo
DEDICATED
INPUTS .

DEDICATED
INPUTS

MACROCELLS

12 MACROCELLS.

• 12 MACRO CELLS

•
•

AND ARRAY

•

I/O

I/o

GND

VCC
290195-4

Figure 3. 5eOgO Global Architecture

The architecture of the 5eOgO is based on the "Sum
of Products" PLA (Programmable Logic Array) structure with a program,mable AND array feeding into a
fixed OR array. The device accommodates combina-.
tional and sequential logic functions. A proprietary
programmable 1/0 architecture provides individual
selection of either combinatorial or registered output
and feedback signals all with selectable polarity.

tional operations, and 2 synchronous clock inputs.
The 5eOgO is packaged in a 40-lead windowed ceramic DIP or 44-lead J-Ieaded chip carrier package
and contains 24 programmable registers~
The basic Macrocell architecture for the 5eOgO is
shown in Figure 2. The 5e090 has 24 of these macrocells (one for each 1/0 pin). The Macrocell is organized in the familiar sum-of-products structure with a
programmable AND array attached to a fixed OR
term. The inputs to the programmable AND array
originate from the true and complement signals from
each of the dedicated input pins and each of the 1/0
control blocks.

A feature unique to the 5eOgO is the ability to individually program the output registers as a D-, T-, SR-, or
JK-type Flip-Flop with but sacrificing the utilization of
programmable AND logic. Additionally, each output
register can be individually clocked from any of the
input or feedback paths available within the AND array. With these features, a wide variety of logic functions can be simultaneously implemented-all on
the same device.

T~e AND array for the 5e090 has 72 inputs derived
from the true and complement signals at the input
and 1/0 pins. The AND array in the 5e090 encompasses 240prciduct terms which are distributed
among the 24 Macrocells. The global device architecture is shown in Figure 3.

ARCHITECTURE DESCRIPTION
The 5e090 has 12 dedicated inputs, 24 1/0 pins
which may be configured for input, output, or bidirec2-44

inter

seogo

The Macrocells contain ten product terms tota\.
Eight of the ten product terms (AND gates) are dedicated for logic implementation. One produCt term on
each Macrocell is used for RESET control to the
output register associated with the Macrocell. The
final product term is used for OUTPUT ENABLE I
Asynchronous Clock implementation.

Output Enable (OE)/Clock Selection
Two modes of operation are provided by the
OE/ClK Select Multiplexer as a part of each Macrocell. One mode provides for three-state buffering of
outputs while in the other mode, the outputs are always enabled. The operation of the OE/ClK Select
Multiplexer sets the mode within a given Macrocell.
Therefore, the output mode can be selected individually on every output. Figure 4 illustrates the two
modes of OE/ClK operation.

Within the AND array, there is an EPROM connection at every intersection of an input signal (true and
complement) and a product term to a given Macrocell. Before programming an erased device, every
EPROM connection is made at every intersection.
But during the programming process, these connections are opened so that only the desired connections remain. Therefore, the true or complement of
any input signal can be connected to any product
term. If both the true and complement connections
of any signal are left intact, a logical false results on
the output of the AND gate. However, if both the true
and complement connections are open, then a logic
"don't care" results on the AND gate. lastly, if all
the inputs of a product term are programmed open,
then a logical true results on the output of the AND
gate.

MODE 0: THREE-STATE BUFFERING
In Mode 0, the three-state output buffer is controlled
by a single product term originating from the AND
array. The output is enabled when the product term
is a logical true. Conversely, the output appears as
high impedance when the product term is a logical
false as shown in Table 1. In Mode 0, the Macrocell
Flip-Flop is connected to its associated synchronous
clock (either ClK1 or ClK2 depending upon the
Macrocell's location within the device). Thus, the
Macrocell Flip-Flop may be clocked by its respective
synchronous clock but its output will not become
valid until the output is enabled.

The 5C090 has two dedicated clock inputs to provide synchronous clock signals to the internal registers. Each of the clock Signals controls half the total
registers within the given device. For example, ClK1
provides synchronous clocking to the registers in
Macrocells in· the left half of the array while ClK2
controls the registers associated with Macrocells in
the right half of the array. The advanced 1/0 architecture allows for any number of the registers to be
synchronously clocked (from none to all). Both of
the dedicated clock inputs latch the data into a given
register when triggered on a positive edge.

Table 1. Mode 0 Output Selection
Product Term

Output Buffer

FALSE

Three-State

TRUE

Enabled

MODE 1: OUTPUT BUFFER ENABLED
In Mode 1, the Output Buffer is always enabled. In
addition, the Macrocell Flip-Flop is connected to the
AND array. The Macrocell Flip-Flop may now be triggered from an asynchronous clock signal generated
by the AND array logic to the OE/ClK multiplexable
term. Mode 1 allows the Macrocell Flip-Flops to be
individually clocked from any of the available signals
in the AND array. Since both true and complement
values appear in the AND array, the Flip-Flop may
be configured to trigger on positive or negative clock
edges. Gated clock structures can be created since
the Flip-Flop clock is created by a product term.

MACROCELL ARCHITECTURE
SELECTION
The 5C090 architecture provides each Macrocell
with over 50 different possible 1/0 register configurations. Each 1/0 pin can be configured for combinatorial or registered output (true or complement) with
feedback. In addition, four different types of output
registers can be implemented into every 1/0 pin
without any additional logic requirements. The feedback mechanism for each register back into the
AND array can be programmed to provide for either
registered feedback from the Macrocell or input
feedback (treating the pin as an input). Another advantage of the advanced 1/0 capability of the 5C090
is the ability to individually clock each internal register from asynchronous clock signals.

Invert Select EPROM Bit
The Invert Select EPROM bit is used to invert the
product term input into the register. This applies to
all inputs including double inputs on the JK and SR
registers.

2-45

intJ

5eOgO

SYNCHRONOUS
CLOCK
VCC

OE/ClK
SELECT

OE
OE/ClK

ClK - SYNCHRONOUS
ClK

OE - P-TERM CONTROllED

OUTPUT
REGISTER
OUTPUT
BUFFER

290195-5

MODE ,0
SYNCHRONOUS
CLOCK
VCC

OE/ClK
SELECT

ClK - ASYNCHRONOUS
ClK

OE- ENABLED

OUTPUT
REGISTER
OUTPUT
BUFFER

290195-6

MODE 1
Figure 4. Output Enable/Clock Configuration

2-46

5eOgO

REGISTER SELECTION
The advanced I/O architecture of the SeagO allows
four different register types along with combinatorial
output as illustrated in Figure Sa through e. The register types include a T, D, JK, or SR Flip-Flop and
each Macrocell I/O structure may be independently
configured. In addition, all registers have an individual asynchronOus RESET control from a dedicated
product term derived in the AND array.· When this
dedicated product term is a logical one, the Macrocell register is immediately cleared to a logical zero
independent of the register clock. The RESET function occurs automatically on power-up.

Output Register Configuration
The four different register types shown in Figure S
are described below.
D- or T-type Flip-Flops
When either a D- or T-type Flip-Flop is configured
as part of the I/O structure, all eight of the product
terms into the Macrocell are ORed together and
fed into the register input.

When either a JK or SR register is configured, the
eight product terms are shared among two OR
gates (one for the J or S input and the other for
the K or R input). The allocation for these product
terms for each of the register inputs is optimized
by the iPLDS II development software.

OUTPUTIFEEDBACK
The Output Select Multiplexer allows for either registered, combinatorial or no output.
The Feedback Select Multiplexer EPROM bit enables registered, I/O (using the pin for bidirectional
input or just input), or no feedback to the AND array.
The Feedback Select is also important for building
product terms with more than B products. The Bproduct product term of a Macrocell can be fed back
into the AND array and combined with still more signals to create a much larger product term (of more
than B-inputs). In addition, if the feedback product
. term is not to be output, then the iPLDS II will reserve the associated Macrocell pin and indicate it in
the REPORT file. A reserved pin should be left floating (no connect) when assembled onto a circuit
board.

JK or SR Registers
Any I/O pin may be configured as a dedicated input
by selecting no output and pin feedback through the
appropriate multiplexers.
1/0 SELECTION
OUTPUTIPOLARITY

FEEDBACK

Combinatorial/High
Combinatorial/Low
None

Pin, None
Pin, None
Pin

290195-7

Figure 5a. Combinatorial 1/0 Configuration

inter

5eOgO

1/0 SELECTION

SYNCHRONOUS
CLOCK

vee

OUTPUTI
POLARITY

FEEDBACK

D-Register/High
D-Register Ilow
Norie
None

D-Register, Pin, None
D-Register, Pin, None
D-Registered
Pin

FUNCTION TABLE
D

0
0
1
1

0
1
0
1

n+ 1
0
0
1
1

290195-8

Figure 5b. D-Type Flip-Flop Register Configuration
SYNCHRONOUS
CLOCK

1/0 SELECTION

vee

OUTPUTIPOlARITY

FEEDBACK

T -Register IHigh
T-Register/low
None
None

T-Register, Pin; None
T-Register, Pin, None
T-Register
Pin

FUNCTION TABLE
T

0
0
1
1

0
1
0
1

290195-9

Figure 5c. Toggle Flip-Flop Register Configuration

2-48

0
1
1
0

inter

seogo
1/0 SELECTION

SYNCHRONOUS
CLOCK

vee
or

OUTPUTIPOLARITY

FEEDBACK

JK Register/High
JK Register/Low,
None

JK Register, None
JK Register, None
JK Register

FUNCTION TABLE
ell(

GIn

an + 1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
,1

0
1
0
1
"
0
1
0
1

0
1
0
,0
1
1
1
0

Figure 5d. JK Flip-Flop Register Configuration
SYNCHRONOUS
ClOCK

vee

1/0 SELECTION,
OUTPUT/POLARITY
FEEDBACK

OE/CLK
S£L[CT

SR Re'gister, None
SR Register, None
SR Register

SR Register/High
SR Register/Low
None
'

FUNCTION TABLE
CLK

an + 1

-C> TO TEST'

DEVICE D...,...........
'OUTPUT

°
,

, ,<::: )(;2.0

TEST ,POINTS,

_0.8.

SYSTEM

341,1).

OUTPUT

1~~TEST POINTS --'--~
290195-14

A,C. Testing: Inputs are Driven at 3.0V for a,Logic '~1".ai1d OV for '
a Logic "0". Timing Measurements are made at 2,OV for a Logic
"1" and O,BV for a Logic "0" on inputs, Outputs are measured at
a 1.5V pOint. Device input rise and fall times < 6,ns.

'290195-13
CL=50pF

:,', .

CAPACITANCE
Symbol

Parameter

CIN

Cvpp

, Clock Pin Capacitance

Unit

: VOUT ;;" OV, f = 1.0 MHz

VIN ='OV, f = 1.0 MHz

CLK2 on 5C09O

VppPin

Min

Typ

Max

'VIN

Output Capacitance

COUT
CCLI(

Conditions

Input CapaCitance

== 'oV, f = 1.0 MHz

A.C. CHARACTERISTICS

TA = 0·Cto70·C, Vcc =5V ±5% , Turbo BitOn(9)
Device

Symbol

From

5C090·50
EP900-2

To
"

Min

Typ

Non·(11) "
Turbo
Unit
Mode

5CQ90-60
EP900
Max

'Min

Typ

Max

Input

Comb. Output

+25

tpD2 '

liD

Comb. Output

+25

tpZX(10)

lorl/O

Output Enable

+25

tpXZ(10)

lorl/O

Output Disable

+25

'tClR

Asynch. Reset

Q Reset

+25

tpD1

NOTES:
9. Typical Values are at T A = 25°C, Vce = 5V, Active Mode.
10. tpzx and tpxz are measured at ±0.5V from steady state voltage' as driven by spec. output load. tpxz is measured with

CL = 5 p F . ' ,
11. If device is operated with Turbo Bit Off (Non-Turbo Mode). increase time by amount showTl.

. . ; ..'

inter

seogo

SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC
TA

Q·C to 70·C, Vcc

5.0V ± 5%, Turbo Bit On(9)
Device

Symbol

5e090-50
EP900-2

Parameter
Min

Typ

Non-(11)
Turbo
Mode

5e090-60
EP900
Max

Min

Typ

Unit

Max

fMAX

Max. Frequency (Pipelined)
(1 Itsu-No Feedback)

26.3

21.7

MHz

fCNT

Max. Count Frequency·
(1/tCNT-With Feedback)

16.7

MHz

tSU1

Input Setup Time to ClK

+25

tSU2

1/0 Setup Time to ClK

·+25

I or 1/0 Hold after ClK High

tco

ClK High to Output Valid

tCNT

tCH
tCl

ns
ns

23
50

+25

ClK High Time

17.5

ClK low Time

17.5

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
= O·C to 70·C, Vcc = 5.0V ± 5%, Turbo Bit On(B)

Device
Symbol

5e090-50
EP900-2

Parameter
Min

Typ

Non-(11)
Turbo
Mode

5e090-60
EP900
Max

Min

Typ

Unit

Max

fACNT

Max. Count Frequency
(1/tACNT-With Feedback)

16.7

tASU1

Input Setup Time to
Asynch. Clock

+25

tASU2

1/0 Setup Time to
Asynch. Clock

+25

tAH

Input or 1/0 Hold After
Asynch. Clock

tACO

Asynch. ClK to Output Valid

tACNT

MHz

ns
59

+25

tACH

Asynch. ClK High Time

17.5

+25

tACl

Asynch. ClK low Time

17.5

+25

2-55

inter

seogo

SWITCHING WAVEFORMS
COMBINATORIAL MODE

~'''j

INPUT OR I/O INPUT

COMBINATORIAL OUTPUT

1---. tpxz - (FROM REGISTER
TO OUTPUT)

HIGH IMPEDANCE
3- STATE

HIGH IMPEDANCE·
3- STATE

I
.,

tpzx

VALID OUTPUT

.~.~
ASYNCHRONOUSLY
CLEAR OUTPUT
290195-15

SYNCHRONOUS CLOCK MODE

.Ir= tCH::j .

CLKl,CLK2

J~ ~ l

~----~

INPU~

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

MAY CHANGE

VALID OUTPUT
290195-16

2-56

inter

5eOgO

SWITCHING WAVEFORMS (Continued)
ASYNCHRONOUS CLOCK MODE

~~~~~ ___...J£'~ ]'--__
OTHER
INPUT

. . __...J£.~ ] . . . .__

·,,"4

-----------------~
INPUT MAY CHANGE

INPUT MAY CHANGE

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT

290195-17

SC090

Current in Relation to Frequency

Output Drive Current in Relation to Voltage
100

200
160
160

140

120

100

./
/7
/

(,)

'5
0.
'5

/I OL

Vo Output Voltage (V)

290195-19
Conditions: TA

290195-18
~

IOH "\.

fo (MHz)
Condi1ions: TA

.......

- ""

o'C, Vee

5.25V

2-57

25'C

5C121
1200 GATE CHMOS
H-SERIES ERASABLE PROGRAMMABLE lOGIC DEVICE
High Performance LSI Semi-Custom
Architecture Features
• Logic
• Advanced
Replacement for Gate Arrays and
Including Programmable Output
Conventional Fixed Logic

Polarity (Active High/Low), Register
By-Pass and Reset Controls

•
Programmable Macrocell and I/O
• Architecture;
up to 36 Inputs or 24
EPROM Technology Based. UV
Erasable

Outputs, 28 Macrocells Including 4
Buried Registers

•
•
•
•

All Inputs are Latchable with a
Programmable Latch Feature
High Speed tpD (Max) 50 ns Operating
Frequency (Max) 20 MHz

Clock System for Input
• Programmable
Latches and Output Registers
Product-Term Sharing and Local Bus
• Architecture
for Optimized Array

'.•

Performance
Compatible with LS TTL and 74HC
CMOS Logic
Register Pre-Load and Erasable Array
for 100% Generic Testability

Programmable "Security Bit" allows
• total
protection of proprietary designs

Low Power; 15 mW Typical Standby
Dissipation

Typical Usable Gate Count of 1200
2-lnput NAND Gates

Available in a 40-Lead Window Cerdip
Package (See Packaging Spec. Order # 231369)

• Fully Compatible with EP1210

The Intel 5C121 H-EPLD (H-series Erasable Programmable Logic Device) is an LSI logic circuit that is user
customizable through programming. This device can be used to replace gate arrays, multiple programmable
logic arrays and LS TTL and 74HC CMOS SSI and MSI logic devices. The logic capacity of the 5C121 is
typically equal to 1200 two-input NAND gates.
Pin Configuration

ClK 1
17
18
19
1,0
1"
1'2
1/°1
1/°2
1/°3
1/°4
1/°5
1/°6
1/°7
1/°8
1/°9
1/°10
1/°11
1/°12

veclvpp
Vee

16/ClK2
15
14
13
12
1,
1/°24
1/°23
1/°22
1/°21
1/°20
1/°19
1/°18
1/°17
1/°16
1/°15
1/°14
1/°13

Vss

290098-1

ILLUSTRATIONS COURTESY OF ALTERA CORPORATION.
2-59

October 1988
Order Number: 290098-005

inter

5C121

The 5C121 H·EPLD uses CHMOS' EPROM (floating
gate) cells as logic control elements instead of fus·
es. Use of Intel's advanced CHMOS II·E EPROM
process technology enables greater logic densities
to be achieved with superior speed and power per·
formance. The EPROM technology also enables
these devices to be 100% factory tested by the pro·
gramming and the erasure of all the EPROM logic
control elements in the device.

product terms (AND gates) each containing 64 input
signals.
The macrocells share a common programmable
clock system (described in a later se.ction) that con· '
trois clocking of all registers and input latches .. The
device contains 8 modes of clock operation that al·
low logic transition to take place on either rising or
falling edges of the clock signals.

The architecture of the 5C121 is based on the 'Sum
of Products' PLA (Programmable Logic Array) struc·
ture with a programmable AND array feeding into a
fixed OR array. Flexibility in accommodating logical
functions without the overhead of unnecessary prod·
uctterms or speed penalties of programmable OR
structures is achieved through the provision of a
range of OR gate widths as well as through product
term sharing. The use of a segmented PLA structure
with local and global connectivity allows for further
improvements in performance. The 5C121 also con·
tains innovative architectural features that provide
extensive Input/Output flexibility.

The device also contains four macrocells whose out·
puts are not tied to any I/O pin but feed back into
the array to create buried state·functions. The feed·
back path may be either the registered or combina·
tional result of the PLA output. The use of the buried
state macrocells provides maximum equivalent logic
density without demanding higher pin·count pack.
ages that consume valuable board space.

MACROCELL 1/0 ARCHITECTURE
The Input/Output architecture of the 5C121 macro·
cell (see Figure 1) can be programmed using both
static and dynamic controls; The static controls re·
main fixed after the device is programmed whereas
the dynamic controls may change state as a result
of the signals applied to the device.

ARCHITECTURE DESCRIPTION
The 5C121 H·EPLD has 12 dedicated inputs as well
as 24 Input/Output pins. All inputs to the circuit
(both dedicated and I/O inputs) may be latched us·
ing transparent 7475 type latches. In addition to
these 36 input latches, 28 D type registers are also
provided.

The static controls set the inversion logic (i), register
by· pass (ii) and input feedback multiplexers (iii). In
the latter two cases these controls operate on four
macrocells as a bank.

The internal architecture of the 5C121 H·EPLDis
based on 28 macrocells. Each macrocell (see Figure
1) contains a PLA structure (programmable AND ar·
ray product terms connected to an OR gate) and an
I/O architecture control block (with a D Flip·Flop)
that can be programmed to create many different
output logic structures. This powerful 110 architec·
ture can be configured to support both active·high,
active· low, 3·state, open drain and bi·directional
data ports all on a 4·bit wide basis. They can also
act as inputs on a nibble wide basis with optional
input latching.

The buried·state registers have simpler controls that
determine if the feedback is to be registered or com·
binational.
The inversion control logic, marked (i) in Figure 1, is
achieved by programming the EPROM control bit
conneCted to the same XOR gate as the output from
the PLA structure. Programming or erasure of this
EPROM element toggles the OR gate output of the
PLA between active·high and active·low. The inver·
sion control operates on an individual macrocell ba·
sis.

Macrocells in each half of the circuit are grouped
together for I/O architecture programming. Each
bank of four macrocelis can be further programmed
on an individual macrocell basis to generate active
high or active low outputs of the logic function from
the PLA.

The register by·pass control, marked (ii) in Figure 1
allows the PLA output to either flow through the D ,
Flip·Flop as a registered output or by·pass the Flip·
Flop and be a combinational output.
The dynamic controls consist of a programmable in·
put latch·enable as well as reset and output enable
product terms. The latch·enable function is common
throughout the 5C121 and once chosen, will latch all
the inputs. This function is programmed by the clock
control block but may also be driven by input signals
applied to pin 1 (see clock modes-Table 1).

The primary logic array of the 5C121 is segmented
into two symmetrical halves that communicate via
global bus signals. The main array contains some
15104 programmable elements representing 236

'CHMOS is a patented process of Intel Corporation.

2·60

intJ

5C121

r - - - - ,-,.,.,- ---,,,-

I
I
I
I,

PLA

I/O ARCHITECTURE BLOCK

EPROM
CONTROL
BIT
290098-2

Figure 1. 5C121 MacrocelillO Architecture

The reset and output-enable controls are logically
controlled by single product terms (the logic AND of
programmed variables in the array). These terms
have control over banks of four macrocells.
The output-enable control may be used to generate
architecture types that include bi-directional, 3-state,
open drain, or input only structures.

for communication within each half of the chip contains 16 conductors that carry the TRUE and COMPLI':MENT of 8 local macro cells. In the block dia, gram (Figure 2) of the 5C121 the local macrocells
are B-1 and B-2 on one half and A-1 and A-2 on the
other half.
The global busses (Input bus & Global feedback
from A-3 & B-3 macrocells & buried registers) are
made up of 48 conductors that span the entire chip.
These 48 conductors carry the TRUE and COMPLE~
MENT of the twelve primary inputs (pins 2 through 7
and 33 through 38), signals from 4 Buried Registers
as well as the global outputs of 8 macrocells in
groups A-3 and B-3.

INTERNAL BUS STRUCTURE
The two identical halves of the 5C121 communicate
via a series of busses. The local bus structure used

2-61

intJ

5C121

. A-l MACROCELLS

290098-3

Figure 2. 5C121 Block Diagram

2-62

5C121

B-2 MACROCELLS

B-3 MACROCELLS
290098-4

Figure 2. 5C121 Block Diagram (Continued)
2-63

intJ

5C121

LOCAL
BUS

GLOBAL
BUS

INPUT,
'BUS

In this illustration a small group of 4 product-terms is
shared by groups containing 8 product-terms each.
This feature, is most useful in counter applications
where common terms exist in 'the functions.

DETAILED, CIRCUIT
REPRESENTATION

-0- =

64 INPUT AND GATE
(ONE PRODUCT TERM)

290098-5

Figure 3. Shared Product-Term Circuits
2-64

5C121

is adjacent to their macrocell (see Figure 4) so that
they may produce a logical AND of any of the variables (or their complements) that are present on the
busses.

SHARED PRODUCT TERMS
Macrocells 9 & 10,11 & 12, 17 & 18 and 19.& 20 (in
groups A-3 and B-3-the macrocells with global
feedback) have.the facility to share a total of 16 additional product terms. This sharing takes place between pairs of adjacent macrocells. This capability
enables, for example, macrocells 9 and 10 to ex"
pand to 16 and 8 effective product terms respectively, and for macrocells 11 and 12 both to expand to
12 effective product terms. Figure 3 shows this sharing technique in detail. This facility is primarily of use
in state machine and counter applications where
common product terms are frequently· required
among output functions.

All macrocells have the ability to return data .to the
local or the global bus. Feedback data. may originate
from. the output of the macrocell or from the 110 pin.
Feedback to the global bus communicates throughout the part. Macrocells that feedback to the local
bus communicate only to their half of the 5C121.
Connections to and from the ·signal busses· are
made with EPROM switches that provide the reprogrammable logic capability of the circuit..
Macrocells in groups A-3 and B-3 and the buried
registers all have global bus connections while macrocells in groups A~ 1, A-2 and B-1, B-2 have only
local bus connections (see Block Diagram, Figure 2).
Advanced features of the Intel Programmable Logic
Development System II will, if desired, automatically
select an appropriate macrocell to meet both the
logic requirements and the connection to an appropriate signal bus to achieve the interconnection to
other macrocells.

MACROCELL-BUS INTERFACE
As discussed earlier, the macrocells within the
5C121 are interconnected to other macrocells and
inputs to the device via three internal data busses.
The product terms span the entire bus structure (local feedback, global feedback and input buses) that

At each intersecting point in the /ogic array there exists an
EPROM-type programmable connection. Initially; a/l connecUons
are complete. This means that both the true and complement of a/l
inputs are connected to each product-term. Connections are
opened during the programming process. Therefore any product
term can be connected to the true or complement of any input.
When both the true and complement connections of any input are
len intact, a logical fa,lse results on the output of the AND gate. If
both the true and complement connections of any input are programmed open, then a logical "don't care" results for that input If
a/l inputs for a product term are programmed open, then a logical
true results on the output of the AND gate.

EPROt.t®
CELL
II
CONNECTION
64 INPUT AND GATE

"-...

EPROt.t CELL
ARCHITEctURE
SWITCH

FEEDBACK
SIGNALS

LOCAL
BUS

GLOBAL
BUS

INPUT
BUS

290098-6

Figure 4. Macrocell-Bus Interface
2-65

inter

5C121

CLOCK MODE CONTROL

PROGRAMMING CHARACTERISTICS' ,

The 5C121' contains two internal clock data paths
that drive the input latches (transparent 7475 type)
and the output registers. These clocks may be programmed into one of 8 operating modes (see clock
mode Table 1).' Figure 1 shows a typical macrocell
which' is driven by the master clock signal CLKand
the input latch-enable signal ILE.
.

Initially, and after erasure, all the EPROM control
bits of the 5C121 are connected (in the "1" state).
Each of the connected control bits are selectively
disconnected by programming the EPROM cell into
their "0" state. Programming voltage and waveform
specifications are available by request from Intel to
support programming of the ,5C121.

The master clock signal is input via pin 1. If programmed modes 4, 5; 6& 7 are c~osen; a second
clock signal is required which is input via pin 38 (see
Figure 5). Table 1 shows the operation of each clock
programming mode.
If modes 0, 1, 4, 5; 6 or 7 are chosen (i.e. latching of
the inputs is required), all inputs, both dedicated and
1/0; are latched with the same ILE Signal. Data applied to the inputs when CLK1 is low (high) is latched
whenCLK1 goes high (low) and will stay latched as
long asCLK1 stays high (low). Levels shown in parenthesis are for modes 1, 5& 7 and levels shown
outside parenthesis are for modes 0, 4 & 6.

inteligent Programming™ Algorithm
The 5C121.!,!upports the inteligent Programming AIgorithm which rapidly programs Intel ,H-ELPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programmirig environment.
This method greatly decreases the overall programming time While programming reliability is ensured as
the incremental program margin of each bit is continually'monitored to determine ,when the bit has
been successfully programmed.

FUNCTIONAL .TESTING

Care is required when using any of the clock modes
4, 5, 6 or 7, that require two input clock signals to
ensure that timing hazards are not created.

Since the logical operation of the 5C121 is c.on"
trolled by EPROM elements, the device is completely factory tested. Each programmable EPROM bit
co!')trolling the internal. logic including the buried
state registers are tested using application-independent test program patterns. After testing; the devices are erased before shipment to customers. No
post-programming tests of the EPROM' array are
.
necessary.

ERASURE CHARACTERISTICS
Erasure characteristics of the 5C121 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlightandcertain types of
fluorescent 'lamps have wavelengths in the 30004000A. Data shows that constant exposure to room
level fluorescent lighting could' erase the typical
5C121 in. approximately three years, while it would
take approximately one week to cause erasure when
exposed to direct, sunlight. If the 5C121 is to be exposed to these types ,of lighting· conditions for ex'tended periods of time, conductive opaque labels
should be placed 'over the window to prevent unintentional erasure.

DESIGN RECOMMENDATIONS
For proper operation it is recommended that input
and output pins be constrained to the range GND <
(VIN or VOUT) < Vee. Unused inputs should be tied
to an appropriate logic level (e.g. either Vee or GND)
to minimize device power consumption.
When utilizing a macrocell with an 1/0 pin connection as a buried macrocell (Le. just using the macrocell for feedback purposes to other macrocells), its
1/0 pin is.a' 'reserved pin'. (The Intel Programmable
Logic Development System II will label the pin 'RESERVED' in the utilization report that it generates.)
Suchan 1/0 pin will actually be an output pin and
should not be grounded.' It should be'left unconnected such that it can go high or low depending on the
state of the macrocell's output.

The recommended 'erasure procedure for the 5C121
is exposure to shortwave ultraviolet light which has
the wavelength of 2537A. The .integrated dose (Le.,
UV intensity x exposure time) for erasure should be
a minimum of fifteen (15), Wsec/cm 2 . The erasure
time with this c;losage is approximately 15 to 20 minutes usirig an ultraviolet lamp with a 12,000 /l-W/cm 2
power rating. The 5C121 should be placed within
one inch of the lamp tubes during erasure. The.maximum integrated dose the 5C121 can be expos/:ld to
without damage is 7258 Wsec/cm 2 (1 week @
.12,000/l-W/cm 2 ). Exposure to high intensity UV light
for longer periods may cause permanent damage.

In normal operation VeelVpp (pin 40) should be
connected directly to Vee (pin 39) .

2-66

infef

5C121

Table 1. Clock Programming (Key: L = Latched; T = Transparent)
Programmed
Mode

Input Signals
Are Latched When:

Output Registers
Change State When:

CLK1
(Pin 1)

L
T

CLK1
(Pin 1)

--v-

T
L

CLK1
(Pin 1)

Inputs Not Latched

CLK1
(Pin 1)

Inputs Not Latched

CLK1
(Pin 1)

--v~

--v-

L
T

CLK2
(Pin 38)

T'
L

CLK2
(Pin 38)

L
T

CLK2
(Pin 38)

T
L

CLK2
(Pin 38)

''f
f

Clock
Configuration

1 Clock
1 Clock
1 Clock
1 Clock
2 Clocks
2 Clock
2 Clocks
2 Clocks

Figure 6 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the de·
vice returns to active mode. Wakeup time adds an
additional 10 ns to the propagation' delay through
the device as measured from the first input. No de·
lay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

As with all CMOS devices, ESD handling procedures
should be used with the 5C121 to prevent damage
to the device during programming, assembly, and
test.

DESIGN SECURITY
A single EPROM bit provides a programmable design secruity feature that controls the access to the
data programmed into the device. If this bit is set, a
proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisibleeven to microscopic evaluation. The EPROM security bit, along with all the other EPROM control
bits, will be reset by erasing the device.

After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

LATCH-UP IMMUNITY
All of the input, 1/0, and clock pins of the 5C121
have been designed to resist latch·up which isinher-'
ent in inferior CMOS structures. The 5C121 is designed with Intel's proprietary CHMOS IJ-E EPROM
process. Thus, each of the 5C121 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -lV to Vee + lV.Furthermore,
the programming pin is designed to resist latch-Up to
the 13.5V maximum device limit.

AUTOMATIC STAND-BY MODE
The 5C121 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed (TURBO = ON), the device is optimized for maximum
speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

2-67

5C121

CLOCK SIGNALS TO
'A' HALF OF CIRCUIT

ClK REGISTER CLOCK
IlE INPUT LATCH ENABLE

iLE
ClK .....- - - - - - ,

ClK

"CLOCK CONTROL
lOGIC"

ClK
(PIN 1)

14
IS
OPTIONAL SECOND
ClQCKINPUT

J;; ClK2

'(~IN 38)

290096-7

Figure S. Programmable Clock Control System

FIRST
INPUT

. lAST
INPUT

OUTPUT

CURRENT
OmA

VALID OUTPUT

ACTIVE MODE

Icc

----------------~----~==~====~~--~----------290096-21
Figure 6. SC121 Standby Mode and Active Mode Transitions

.2-68

infef

5C121

(3) 512K Memory (640K recommended)

Intel Programmable Logic
Development System II (iPLDS II)

(4) Intel iUP-PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS II).
'

iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. It contains comprehensive third generation software that
supports four different design entry methods, minimizes logic, does automatic pin assignments and
produces the best design fit for the selected EPLD.
It is user friendly with guided menus, on-line Help
messages and soft key inputs.

Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet (Order Number: 280168).
tlBM Personal Computer is a registered trademark of International Business Machine Corporation.
HMS-DOS is a registered trademark of Microsoft Corporation.

In addition, the iPLDS II contains programmer hardware in the form of an expansion card for the PC
with programming software to enable the user to
program EPLDs, read and verify programmed devices and also to graphically edit programming files.
The software generates industry standard JEDEC
object code output files which can be downloaded to
other programmers as well.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:
INP
L1NP
CONF
CORF
COIF
COLF

The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. An integrated schematic entry
method is provided by SCHEMA II-PLD, a low-cost
schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design entry formats supported are Boolean equation
entry and State Machine design entry.

RONF
RORF
ROlF
ROLF
NOCF
NORF

ORDERING INFORMATION
tpD teo

fMAX

(ns) (ns) (MHz)

The iPLDS II runs on the IBMt PC, PC/XT or PCI AT
and other compatible machines with, the following
configuration:
(1) At least one floppy disk drive Cj.nd hard disk drive
(2) MS-DOStt Operating System Version 2.0 or later release

2-69

Order
Code

Package

Operating
Range

D5C121-55 CERDIP

Commercial

D5C121-65 CERDIP

Commercial

D5C121-90 CERDIP

Commercial

5C121

* Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Parameter

Min

Max

Unit

Vee

Supply Voltage(1)

-2.0

7.0

Vpp

Programming
Supply Vollage(1)

-2.0

13.5

DC Input Voltage(1)(2)

-0.5 Vee+ 0.5

Icc

DC Vee Current(4)

100

rnA

Tstg

Storage Temperature

-65

+ 150

°C

Tamb

Ambient Temperature(3)

-10

+85

°C

NOTES:
1. Voltages with r~sP.!lct to ground.
2. Minimum DC inpcit is -0.5V. During transitions, the inputs may undershoot to -2.0V or overshoot to 7.0V for
periods less than 20 ns under no load conditions.
3. Under bias.
4. With outputs tristated.

RECOMMENDED OPERATING
CONDITIONS
Symbol

Parameter

Min-

Max

Units
V

Vee

Supply Voltage

4.75

5.25

Input Voltage

Vee

Output Voltage

Vee

Operatih9T emperature

°C

Input Rise Time

500

Input Fall Time

500

D.C. CHARACTERISTICS TA
Symbol
VIH
VIL

= 0° to 70 0

Parameter

e, VCC

= 5.0V ± 5%

Conditions

HIGH Level Input Voltage
LOW Level Input Voltage

VOH

HIGH Level
, Output Voltage

VOL

LOW Level
Output Voltage

10 = -4.0 rnA DC

Min

Max

Unit

2.0

Vee+ 0.3

-0.3

0.8

Typ

2.4

10 = 4.0mADC

V
0.45

Input Leakage Current

VI = Vee or GND

±10.0

p.A

102

3-State Output
Olf-State Current

Vo = Vee or GND

±10.0

p.A

los

Output Short Circuit Current

130

rnA

Iss

Vee Supply Current (Standby)
(Note 6)

VI = Vee or GND
10 = 0

CMOS Inputs

rnA

TTL Inputs

Vee Supply Current (Active)

No Load
1= 10MHz

CMOS Inputs

TTL Inputs

100

Icc

(Note 5)

NOTES:
5. Output shorted for no more than 1 sec. and no more than one output shorted at a time. los is sampled but not 100%
tested.
6. Chip automatically goes into standby mode if logic transitions do not occur. (Approximately 100 ns after last transition.)
2-70

intJ

5C121

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

INPUT

~~~~ D-+-......-C> ~~S~i~T
341.(1

CL (INCLUDES JIG
CAPACITANCE)

< )CI.
0.8

290098-9
A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and 0.8V for a Logic "0" on inputs. Outputs are measured at
a I.SV pOint. Device input rise and fall times < 6 ns.

A.C. CHARACTERISTICS TA = O· to 70·C, VCC
Parameter

TEST POINTS

l~-TEST POINTS---"~

OUTPUT

290098-8

Symbol

3.0~20
a
0.8

5.0V

Device
Conditions

± 5%
5C121-55
EP1210-1
Min

Max

5C121-65
EP1210-2
Min

Max

5C121-90
EP1210
Min

Unit

Max

tpD

Non-Registered Input or 1/0
Input to Non-Registered Output

tpzx(7)

Non-Registered Input or 1/0
Input to Output Enable

tpxz(7)

Non-Registered Input or 1/0
Input to Output Disable

tsu

Non-Registered Input or 1/0
Input to Output Register Setup

Non-Registered Input or 1/0
Input to Output Register Hold

tCH

Clock High Time

tCL

Clock Low Time

tco

Clock to Output Delay

tCNT

Minimum Clock Period (Register Output Feedback to Register Input-Internal Path)

CL = 30 pF

CL = 30pF

33
55

.62

ns
ns

fCNT

Maximum Frequency (1 ItCNT)

20.0

18.0

13.0

MHz

fMAX

Maximum Frequency (1 Itsu)-Pipelined

25.0

21.2

16.1

MHz

tRST

Asynchronous Reset Time

tlLS

Set Up Time for Latching Inputs

tlLH

Hold Time for Latching Inputs

tC1C2

Minimum Clock 1 to Clock 2 Delay

tlLDFS

Input Latch to D-FF Setup Time

tDFILS

D-FFto Input Latch Setup Time

tp3

Minimum Period for a
2-Clock System (TC1C2

103

Mode 0, 1

tCOl)

Maximum Frequency (1 Itp3)

13.8

12.0

9.7

MHz

NOTE:
7. tpzx and tpxz are measured at ±0.5V from steady state voltage as driven by spec. output load. tpxz is measured with
CL = 5 pF.

2-71

inter

5C121

SWITCHING WAVEFORMS
INPUT OR I/o INPUT

COMBINATIONAL OUTPUT

INPUT MAY CHANGE

COMBINATIONAL
OR REGISTERED OUTPUT

)I(
HIGH IMPEDANCE
3-STATE

HIGH IMPEDANCE
3-STATE

ASYNCHRONOUSLY

RESET OUTPUT

VALID OUTPUT

290098-11

290098-,10

NOTE:
Above waveforms shown for clock modes 2 or 3 (tsu & tH are as in modes 2 & 3; no ILE signal is used).

CLOCK MODES
SWITCHING WAVEFORMS
1-CLOCK SYSTEM: MODES 0 AND 1

CLK1 (PIN 1)

INPUTS OR
I/o INPUTS

-"\IJ-+--"Ir-":--+-"'\

rT--~ ~-.....;.-

_.11\-+_-"''-___+_-' '-4-_-' '-_ __

REGISTERED
OUTPUT _ _-+________J,,'-I-_______

-+_______-''1\_-+_______

COMBINATIONAL _ _

COMBINATIONAL
OR REGISTERED
OUTPUT

__ .....!':.===:..:t!::px~z~ _tpzx=1:.
-

290098-12
INVERT CLK1 FOR MODE 0

1-CLOCK SYSTEM: MODES 2 AND 3

'-r\1-____. .;. .
~-;S~~f

CLK1 (PIN 1 ) \

INPUTS OR
I/O INPUTS

tcL-I~
'

-------'--_ _ _ _ _ _ __

t-------

REGISTERED
"
tco _
O'UTPUT _ _ _ _ _ _ _ _..J~

I/o INPUTS _ _ _ _ _- - '
INPUTS OR

COMBIN'1J0~ ~\ -------.+.-:-::..J)fr

COMBINATIONAL
OR REGISTERED
OUTPUT

•

t.eo:c
29009B-13

INVERT CLK1 FOR MODE 2

2-72

5C121

CLOCK MODES
SWITCHING WAVEFORMS (Continued)
2-ClOCK SYSTEMS: MODES 4 THROUGH 7
ClKl PIN 1 CONTROLS THE INPUT LATCH CLOCK
ClK2 PIN 38 CONTROLS THE D-FF CLOCK.

ClKl (PIN l)t

~ tl~Hj

5fs

-------+------+_____

INPUTS OR
I/O INPUTS

.....
'--_ _ _ _ _ _

I - - tC1C2 ClK2 (PIN 38)
tco ...
REGISTERED
OUTPUT

.r.:.

}I{

r--

tpD

.=::j.

COMBINATIONAL
OUTPUT

)K
..-.tpzx

I---tpxz
COMBINATIONAL
OR REGISTERED
OUTPUT

290098-14
INVERT ClKl FOR MODES 5 & 7
INVERT ClK2 FOR MODES 4 & 5

100

200
180
160

140

.e-

f
10l

- -"'-

10H

:::I

1
5

O°C, Vee

Vo Output Voltage (V)
290098-20

. 290098-22

:::I

fa (MHz)

Conditions: TA

o
o

:::I

100
60

120

u
..Y

:;e-

5.25V

5C121 Current in Relation to Frequency

Output Drive Current in Relation to Voltage

2-73

5C180
1800-GATE CHMOS
ERASABLE PROGRAMMABLE LOGIC DEVICE

•
•
•
•

High Performance LSI Semicustom
Logic Replacement for TTL and 74HC
SSI and MSI Logic
CHMOS EPROM
Erasable

Technology~Based

48 Macrocells with Programmable I/O
Architecture; up to 64 Inputs (16
Dedicated, 48 I/O) or 48 Outputs
High Speed tpD (max) 70 ns, Operating
Frequency (max) 20.8 MHz (Pipelined),
16.1 MHz (w/Feedback)

Low Power; 100 J1-W Typical Standby
• Dissipation

•

Programmable "Security Bit" Allows
Total Protection of Proprietary Designs

Feedback Signals Allowing I/O
• Dual
Pins to Be Used for Buried Logic and
Dedicated Input
CI.ock System with Four
• Programmable.
Synchronous Clocks as well as
Asynchronous Clocking Option on All
Registers

•
Pre-Load and
•
• 100% Compatible
•

Programmable· Registers. Can Be
Configured as D, T, SR or JK Types
with Individual Reset Controls

68-Pin J-Lead Chip Carrier and Pin Grid
Array Packages
(See packaging spec., Order # 231369)

The Intel 5C180 EPLD (Erasable Programmable Logic Device) is a CHMOS LSI Logic Device capable of
integrating 1800 to over 2000 equivalent gates of SSI/MSllogic.This user customizable Logic Device is
available in a 68·pin J-Leaded chip carrier or Pin Grid .Array package and has. the benefits of low power and
increased flexibility.
The 5C180 EPLD uses CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. Use of
Intel's advanced CHMOS II-E EPROM process technology enables greater logic densities to be achieved with
superior speed and power performance. The EPROM technology also enables these devices to be 100%
factory tested by the programming and the erasure of all, the EPROM logic control elements inthe device.

I/o I/O
I/O I/O
I/O I/O
I/O I/o
I/O GND
I/O I/O
I/O. I/O
I/O I/o
I/o I/O

0
5C180

000000000
00000000000
J 00
00
H 00
00
G 00
00
5C180
F 00
(BOTTOM VIEW)
00
E 00
00
D 00
00
C 00
00
K

BOOOOOOOOOOO

I/O
I/O
I/O
I/o
GND

I/o
I/o
I/o
I/O

I/O
I/O
I/O
I/o
I/O
I/o
I/O
I/O
I/O

000000000·

8, 9 10 11

~ ~ ~ ~
> Z Z
o

I-

0
0
~~

~ ~ ~ ~ ~

290111-1

~~-

Figure 1. Pin Configuration

290111-35

Figure 2. PGA Pin Configuration

2-74

November 1988
Order Number: 290111-005

intef

5C180

within the AND array. All 48 internal registers may be
individually programmed for synchronous or asynchronous clocking. Asynchronous clocking is possible via a Macrocell product term. Clock inputs not
uS,ed for synchronous clock signals may be used as
global bus inputs.

The architecture of the 5C180 is based on the "Sum
of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding .into a
fixed OR array. The 48 macrocells of the 5C180 can
be partitioned into 4 identicalquandrants each containing 12 macrocells. This device makes use of a
segmented PLA structure with local and global bus
structures to provide for increased performance and
.greater device utilization. The 5C180 has unique architectural features that allow programming of all 48
registers to D, T, SR or JK configurations without
sacrificing product terms. These registers can be either clocked asynchronously or in banks with four
synchronous clocks. In addition, the 16 global macrocells have two independent feedback paths to the
array that allow for buried logic implementation together with use of the I/O pin for input functions.

Invert Select EPROM Bit
The Invert Select EPROM bit is used to invert the
product term input into the register. This applies to
all inputs including double inputs on JK and SR registers. The invert option allows the highest possible
logic utilization by use of deMorganlogic inversion.
At each intersecting point in the logic array there
exists an EPROM-type programmable connection.
Initially, all connections are complete. This means
that both the true .and complement of all inputs are
connected to each product term. Connections are
opened during the programming process. Therefore
any product term can be connected to the true or
complement of any input. When both the true and
complement connections of any input are left intact,
a logical false results on the output ,of the AND gate.
If both the true and complement connections of any
input are programmed open, then a logical "don't
care" results for that input. If all inputs for a product
term are programmed open,then a logical true results on the output of the AND gate.

ARCHITECTURE DESCRIPTION
Externally, the 5C180 provides 12 dedicated data inputs, 4 synchronous clock inputs, and .48 I/O pins
which may be individually programmed for input, output, or bi-directional operation.
The Block Diagram is shown in Figure 2 with pin
numbers for the JLCC package. Figure 3 shows the
<:levice block diagram with pin numbers for'the PGA
package. The internal architecture is organized in familiar sum-of-products (AND-OR). structure. The
5C180 houses a total of 480 product terms distributed among 48 Macrocells. The basic Macrocell structure is shown in Figure 4. Input and feedback signals
are selectively connected to product terms via
EPROM cells. The output of the AND array feeds a
fixed OR gate to produce sum-of:products logic. The
final output may be combinatorial or registered, pro,
grammed active high or low. Combinatorial, registered, or pin feedback is also user-defined.

BUS STRUCTURE
Input and feedback signals are connected to each
5C180. Macrocell via a Local and Global Bus. Figure
5 shows the Macrocell-Bus interface for Quadrant D.
The Global Bus contains 64 input signals while the
Local Bus has 24.
Within the 5C180 Macrocell, the product-terms
share the entire bus structure. Therefore, a logical
AND of any of the variables (or their complements)
that is present on the buses may be produced by
each product term.

The 5C180 is partitioned into 4 identical quadrants.
Each quadrant contains 12 Macrocells. Input signals
to the Macrocells come from the 5C180 Local and
Global bus structures. These two buses comprise an
88-input AND array for each quadrant. The output of
each Macrocell feeds an I/O Architecture Control
, Block which contains output and feedback selection.
Four dedicated clock inputs provide synchronous
clock signals to the 5C180 internal registers. There
is one synchronous clock per quadrant. Therefore
each clock signal controls a bank of 12 registers.
CLK1 may be connected to registers in Macrocells
1-12, CLK2 with Macrocells 13-24, CLK3with Macrocells 25-36, and CLK4 with Macrocells 37-48.
With synchronous clocks, the flip-flops are positive
edge triggered. Both true and complement signals
for each dedicated clock input may also be used

All quadrants share the same Global Bus. Inputs to
the bus come from the true and complement signals
of the 12 dedicated data inputs, 4 clock inputs, and
the 16 Global Macrocell pin feedback signals.
Each quadrant has its own Local Bus. Inputs to this
bus come from the 12 quadrant Macrocells. For the,
eight Local Macrocells, the signals can be either
from the Macrocell internal logic or from the pin. For
, the four Global Macrocells, the signals come from
the Macrocell internal logic only.

2~75

inter

5C180

QUADRANT A

QUADRANT D

QUADRANT B

QUADRANT C
GENERAL MACROCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS·

,Figure 2. 5C180 Block Diagram~LCC Package

2-76

290111-2

inter

5C180

QUADRANT D

QUADRANT B

QUADRANT C
290111-36

GENERAL MACROCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS

Figure 3. 5C180 Block Diagram-PGA Package

inter

5C180

Table 1 summarizes the Macrocell interconnect.
Table 1. Macrocellinterconnect
Pin
#

Macro- Feedback
Feedback
cell # Structure Interconnect

Quad 2-9
A
10-13

1-8
9-12

Local
Local
Global

Quad A
Quad A
All

Quad 23-26
B

13-16

Local
Global
Local

Quad B
All
Quad B

Local
Local
Global

QuadC
QuadC
All

Local
Global
Local

QuadD
All
QuadD

27-34 17-24
25-32
33-36

Quad 36-43
C
44-47
Quad 57-60
D

37-40

61-68 41-48

AND ARRAY

SYNCHRONOUS
CLOCK

OE/ClK

VCC

L~ElECT
OE

I--

-D-K
L....-

EPROM

PRODUCT
TERM

CELL

ONNECTION

I-I--

-D-

ClK

Rllb S"-'-'"~
~1~~~
-. ~~~

lOGIC

.
~

INVERT

I/O

SElE~'

D-RESET
~.

•

~ FEEDBAC~

SIGNALS

INPUTS AND I/O

290111-3

Figure 4. Basic Macrocell Architecture of the 5C180

2-78

5C180

GLOBAL BUS
(64 INPUT)

LOCAL BUS
(24 INPUT)

QUADRANT D
MAC'ROCELL 48

MACROCELL 47

MACROCELL 46

MACROCELL 44

MACROCELL 43

MACROCELL 42

MACROCELL 41

MACROCELL 40

MACROCELL 39

MACROCELL 38

. MACROCELL 37

GLOBAL BUS TO
OTHER QUADRANTS
290111-4

Figure 5. Quadrant "0" Bus Interface

2-.79

inter

5C180

rocells within the same quadrant. There are a total of
32 Local Macrocells within the 5C180, with eight per
quadrant.·
.

.5C180 MACROCELLS
Within each 5C180 quadrant there are two different
types of Macrocells; Local Macrocells, Figure 6, and
Global Macrocells, Figure 7. Both types share an 88input AND array and contain a total of ten product
terms. Eight product terms are dedicated for logic
implementation. One product term is reserved for
Asynchronous Clear to the Macrocellregister. The
remaining product term is used for Output Enablel
Asynchronous Clock implementation. Each 5C180
product term represents an 88-input AND gate. The
lID Architecture Control Block provides each Macrocell with both combinatorial and registered lID
configurations.

Local macrocells are divided into two groups: General Macrocells and Enchanced Macrocells. The Enhanced Macrocells are architecturally identical to
the General Macrocells but operate at higher
speeds. These speed differences are reflected in
. the specification tables.
Global Macrocells contain two independent feedback paths to the AND array. Combinatorial or registered feedback is supplied to the local bus and pin
feedback is supplied to the global bus. The "dual
feedback" capability allows the Macrocell to be
used for internal logic functions as well as a dedicated input pin. To obtain this configuration, the output
buffer must be disabled. If the Global Macrocell lID
pin is not being used as a dedicated input, the Macrocell logic may be fed back along the global bus
allowing routing to any of the 5C180's 48 Macrocells. There are 16 Global Macrocells contained in
the 5C180, four per quadrant.

Local Macrocells provide one feedback path into the
AND array. Combinatorial, registered or pin feedback may be selected from the Feedback Select
Multiplexer. The selected feedback signal is then
routed to the quadrant local bus. Therefore, the Local Macrocell feedback communicates only to Mac-

QUADRANT
SYNCHRONOUS
CLOCK
-GLOBAL BUS--LOCAL BUS .....
OE

OEI CLOCK 1-f~-R:-'f=F----R:-'-R:-'-I=F-1-I

t....=:::........::j:;-t--,
CLK

~
~
~
~

2~r-~-~--~-~-~~~
3~r-~-~--~-~~~~~
4~r-~~~--~-~-~~~
5~r-~-~--~-~-~~~

I/O
ARCHITECTURE
CONTROL

6~r-~-H---~-~-~~~
7~~~-H---~-~-~~~
RESET ~f-++--iH---++-~-~~~
FEEDBACK
SELECT
LOCAL BUS

GLOBAL
DEDICATED
INPUTS
(16 INPUTS)

~'--------

QUADRANT
QUADRANT
A,B,C,D
LOCAL
GLOBAL
FEEDBACK
FEEDBACK
(12 MACROCELLS)
(16 MACROCELLS)

290111-5

Figure 6. Local Macrocell Logic Array

2-80

inter

5C180

QUADRANT
SYNCHRONOUS
CLOCK .'

CLOCK

SELECT

-GLOBAL BUS--LOCAL BUS_

SELECT
OE

OE/CLOCKI-tt-+t-t+---HI'--t-t---tH-+-I

~ 2~t-~-~---H~-H~~H-~

'" 3~r-~~~---H--H~~i-~L-~~
.~
I~ 4rt+--H-tr---H~_+r-~H---i
~ 5rt+--H-tr---H~_+r-~H---i
6r+t-+t-t+---Ht--t-t---tH---i

I/O
ARCHITECTURE
CONTROL

7r++-+t-t+---H~-+t---tH---i

RESET rt+-+l-++----H~_+r-~H---i

. LOCAL BUS

GLOBAL
DEDICATED
INPUTS
(16 INPUTS)

GLOBAL BUS
_ _ _ _ _ _- J

QUADRANT
A,B,C,D
GLOBAL .
FEEDBACK
(16 MACROCELLS)

(12

QUADRANT
LOCAL
FEEDBACK
MACROCELLS)

290111-6
Figure 7. Global Macrocell Logic Array'
product term derived in the AND array. When this
dedicated product term is a logical one, the Macrocell register is immediately cleared to a logical zero
Independent of the register clock. The RESET function occurs automatically on power-up.
.

MACROCELL LOGIC
CONFIGURATIONS

Combinatorial Selection

The four different register types shown in Figures
Sb-Se are described below:

In the Combinatorial configuration, eight product
terms are ORed together to generate the output signal. The Invert Select EPROM bit 'controls output
polarity and the Output Enable buffer is product-term
controlled. The Feedback Select allows the user to
choose combinatorial, .1/0 .(pin) or no feedback to
the respective local and global buses.

D- or T-type Flip-Flops
When either a D- or T-type Flip-Flop is configured
as part of the 1/0 structure, all eight of the product terms into the Macrocell are ORed together
and fed into the register input.

JK or SR Registers

The advanced 1/0 architecture of the 5C1S0 allows
four different register types along with combinatorial
output as illustrated in Figures Sa-Se. The register
types include a T, D, JK, or SR Flip-Flop and each
Macrocell 1/0 structure may be independently configured. In addition, all registers have an individual
asynchronous RESET control from a dedicated

When either a JK or SR register is cOl"!figured,
. the eight product terms are ~hared among two "
OR gates (one for the J or S input and the other
for the. K or R input). The allocation for these
product terms for each of the register inputs is
optimized by theiPLDS II development software.
2-S1

5C180

Buried Logic Selection
For Global Macrocells, if no output is selected, the·
logic may be "buried" and the 1/0 pin can be used
as an additional dedicated input. The use of "dual
feedback" is accomplished by lri-s\ating tl:Je OiJtput
Enable Buffer. Thus, up to 16 ar;jditional dedicated
inputs may be added without sacrificing' the Macrocell internal logic.
'

elK

In the erased state, the 1/0 architecture 'is configured for combinatorial active low output with jlo
(p!n) feedback.
'

RESET

290111-9

Figure 8e. Toggle Flip~Flop Register
Configuration

290111-7

Figure 8a. Combinatorial 1/0 Configu~ation
8-N

, INVERT
SELECT

, : 29011i:"10 '

Figure ad. JK Flip-Flop Register Configuration

RESET

RESET
290111-8

. '' .

Figurf.!8b. D,-Type, Fllp-FI9P Registitr
Configuration

2-82

5C180

The operation of each multiplexer is controlled by
EPROM bits and may be individually configured for
each 5C180 Macrocell.
.

ClK
N

In Mode 0, the three-state output buffer is controlled
by a single product term. If the output of the AND
gate is a logical true then the output buffer is enabled. If a logical false resides on the output of the
AND gate then the output buffer is seen as high impedance. In this mode the Macrocell flip-flop may be
clocked by its quadrant synchronous clock input. In
the erased state, the 5C180 is configured as Mode

8- N

In Mode 1, the Output Buffer is always enabled. The
Macrocell flip-flop now may be triggered from an
asynchronous clock signal generated by the Macrocell product term. This mode allows individual clocking of flip-flops from any available signal in the quadrant AND array. Because both true and complement
signals reside in the AND array, the flip-flops may be
configured for positive or negative edge triggered
operation. With the clock now controlled by a product term, gate clock structures are also possible.

INVERT
SELECT

290111-11

Figure 8e. 'SR Flip-Flop Register Configuration

MACROCELL OE/CLK SELECT

In Modes 2 and 3, the Output Buffer is always disabled. The Macrocell flip-flop may still be triggered
from clock signals generated from the Macrocell
product term or asynchronous clocks. This mode is
only possible for Global Macrocells.

Each 5C180 register may be clocked synchronously
or asynchronously. Figure 9a and 9b shows the
modes of operation provided by the OE/ClK Select
Multiplexers for both local and Global Macrocells.

2-83

5C180

SYNCHRONOUS
CLOCK
VCC

OE
OE/ClK

elK - SYNCHRONOUS

ClK

OE - P-TERM CONTROllED

MACROCEll
REGISTER
OUTPUT
BUFFER

290111-12
The register is clocked by the quadrant synchronous clock signal which is common to 11 other Macrocells. The output is enabled by the
logic from the product t e r m . '

SYNCH RONOUS
CLOCK
VCC

OE
OE/ClK

ClK - ASYNCHRONOUS
ClK '

OE- ENABLED

MACROCEll
REGISTER
OUTPUT
BUFFER

290111-13
The output is permanently enabled and the register is clocked via the product term. This allows for gated clocks that may be generated
from elsewhere in the 5C180.

Figure 9a. Local Macrocell OE/CLK Selection

2-84

inter

5C180

SYNCHRONOUS
CLOCK

OE
OE/ClK

ClK - SYNCHRONOUS
ClK

OE- DISABLED

MACROCEll
REGiSTER

290111-14
The output is permanently disabled and the register clocked by the quadrant synchronous clock signal. The pin can be used as an input
while the register or combinational output can be fed back.

SYNCHRONOUS
CLOCK

OE
OE/ClK

ClK - ASYNCHRONOUS
ClK

OE- DISABLED

MACROCEll
REGISTER
BUFFER

290111-15
The output is permanently disabled and the register is clocked via the product term. This allows gated clocks that may be generated
elsewhere in the 5elBO. The pin can be used as in input while the register or combinational output can be fed back.

Figure 9b. Global Macrocell Additional OE/CLK Selection

inter

5C180

MACROCELL LOGIC
CONFIGURATIONS

1/0

The 5C180 Input/Output Architecture provides each
Macrocell with over 50 possible I/O configurations.

(/)
~

CD
...J

(5
o
...J

Figures 10 and 11 show the 5C180 basic I/O configurations for both the Local and Global Macrocells.
Along with combinatorial, four register types are
available. Each Macrocell may be independently
programmed.

FEEDBACK
SELECT !
290111-16

COMBINATORIAL
I/O Selection
Output/Polarity
Combinatorial/High
Combinatorial/Low
None
None

Feedback
Comb, Pin, None
Comb, Pin, None
Comb
..
Pin •..

Bus
Local
I·. Local
Local
Local

Figure 10. Local Macrocelil/O Configurations

inter

5C180

SYNCHRONOUS
CLOCK
OE/CLOCK
V.
SELECT
CC

CLK .

0
Ul
:::J

Ul
:::J

'"
-<

...J

'"0

...J

290111-17

0-TYPE FLIP-FLOP
I/O Selection
Output/Polarity

Feedback

Bus

D-Register/High
D-RegisterI Low
None
None

D-Register, Pin, None
D-Register, Pin, None
D-Register
Pin

Local
Local
Local
Local

Function Table

D
0
0
1
1

Qn
O·
1
0
1

Qn+1

0
0
1
1
Figure 10. Local Macrocelii/O Configurations (Continued)

5C180

SYNCHRONOUS
CLOCK' .' .

Vee

OE/ClOCK
SELECT
OE

ClK

III
:::l
ID
....I

290111-18

TOGGLE FLIP-FLOP
I/O Selection
Output/Polarity
T-Register/High
T-Register/Low
None
None

Feedback
T-Register; Pin, None
T-Register, Pin, !\lone
T-Register
Pin

Bus
Local
Local
Local
Local

Function Table

T
0
0

Qn +1

1
1

1
'1

0
Figure 10. Local Macrocelii/O Configurations (Co'ntinued)

2-88

intJ

5C180

SYNCHRONOUS
CLOCK .

OE/CLOCK
SELECT
OE

CLK

::>

...J

«
m

...J

<.'l

...J

8-N

INVERT
SELECT

290111-19

JK FLIP-FLOP
I/O Selection
Output/Polarity
JK Register/High
JK Register/Low
None

Feedback

Bus

JK Register, None
JK Register, None
JK Register

Local
Local
Local

Function Table
J

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

On
0
1
0
1
0
1
0
1

°n+1
0
1
0
0
1
1
1
0
Figure 10. Local Macrocelii/O Configurations (Continued)

2-89

intJ

5C180

SYNCHRONOUS
CLOCK

OE/ClOCK
SELECT
OE

ClK
N
Q

(f)

::>
m

..J

8-N

..J

(!)

INVERT
SELECT

290111-20

SR FLIP-FLOP
110 Selection
Output/Polarity

Feedback

Bus

SR Register/High
SR Register/Low
None

SR Register, None
SR Register, None
SR Register

Local
Local
Local

Function Table

0
0
0
0

0
0

0
1
0

1
1

0
0

1
1

1
0

Qn + 1
0

1
0
0

1
1
Figure 10. Local MacrocelillO Configurations (Continued)

2-90

5C180

In
...J

::>

~
o
...J

290111-21

COMBINATORIAL
I/O Selection
Output/Polarity

Feedback

Combinatorial/High Comb, Pin, None
Combinatorial/Low Comb, Pin, None
None
Comb
None
Pin
None
Comb/Pin

Bus
Local, Global
Local, Global
Local, Global
Global
Local/Global

Figure 11. Global MacrocelillO Configurations

2-91

inter

5C180

SYNCHRONOUS
CLOCK

OE
SELECT

CLOCK
SELECT

OE.

(f)
::;)

III

«
u,

,290111-22

0-TYPE FLIP-FLOP
1/0 Selection
Output/Polarity

Feedback

Bus'

D-Register/High
D-Register/Low
None
None
None

D-Register, Pin, None
D-Register, Pin, None
D-Register
Pin
D-Register/ Pin

Local, Global
Local, Global
Local, Global
Global
Local/Global

Function Table

D
0
0
1
1

Qn +1

0
0

0
1

1
1
Figure 11_ Global MacrocelillO Configurations (Continued)

2-92

inter

5C180

SYNCHRONOUS
CLOCK

OE
SELECT

CLOCK
SELECT

ClK

T
III

III

::>

CD
...J

i1i
0

...J

290111-23

TOGGLE FLIP-FLOP
I/O Selection
Output/Polarity

Feedback

Bus

T-Register/High
T-Register/Low
None
None
None

T-Register, Pin, None
T-Register, Pin, None
T-Register
Pin
T -Register/Pin

Local, Global
Local, Global
Local, Global
Global
Local/Global

Function Table

0
0

1
1

On+1
0
1
1
0
Figure 11. Global Macrocelli/O Configurations (Continued)

2-93

inter

5C180

SYNCHRONOUS.
CLOCK

OE
SELECT

CLOCK
SELECT

(/)

III
...J

;;!i

8-N

~
o

...J

INVERT
SELECT

290111-24

JK FLIP-FLOP
I/O Selection
'Output/Polarity

Feedback

Bus

JK Register/High JK Register, None Local, Global
JK Register/Low JK Register, None Local, Global
None
JK Register
Local
JK Register/Pin Local/Global
None
Function Table

J
0
0
0
0
1
1
1
1

Qn
K
0
0
1
0
1
0
1
1
0
0
0
1
1. 0
1
1

Qn +1
0
1
0
0
1
1
1
0

,
Figure 11. Global Macrocelii/O Configurations (Continued)

2-94

inter

5C180

SYNCHRONOUS
CLOCK
.

OE
SELECT

CLOCK
SELECT

N
Q

...J

«
m

«
u

...J

INVERT
SELECT

290111:'25

SR FLIP-FLOP
I/O Selection
Feedback

Output/Polarity

Bus

SR Register/High SR Register, None Local, Global
SR Register/Low SR Register, None Local, Global
Local
SR Register
None
None
SR Register/Pin Local/Global

Function Table

Qn+1

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

0
1
0
0
1
1
F,gure 11. Global Macrocelii/O Configurations (Continued)

2-95

5C180

wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A4000A'range. Data shows that constant exposure to
room level fluorescent lighting could erase the typical 5C180 in approximately three years, while it
would take approximately one week to cause erasure when exposed to direct sunlight. If the 5C180 is
to be exposed to these types of lighting conditions
for extended periods of time, conductive opaque labels should be placed over the device window to
prevent
unintentional erasure. .
,

AUTOMATIC STAND-BY MODE
The 5C180 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit' is programmed
(TURBO = ON), the device is optimized for maximum speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.
Figure 12 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode; Wakeup time adds an
additional 30 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

The'recommended erasure procedure for the 5C180
is exposure to shortWave ultraviolet light with a
wavelength of 2537 A. The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (16) Wsec/cm 2 . The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm 2
power rating. The 5C180 should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose the 5C180 can be exposed to
without damage is 7258 Wsec/cm 2 (1 week at
12,000 p.W/cm 2 ). Exposure to high intensity UV light
for longer periods may cause permanent damage to
the device.

After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

Erased-State Configuration
PROGRAMMING CHARACTERISTICS

Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output
with input (pin) feedback.

Initially, and after erasure, all the EPROM control
bits of the5C180 are connected. Each of the con"
nected control bits are selectively disconnected by
programming the EPROM cells into their "on" state.
Programming voltage and waveform specifications
are available by request from Intel to support programming of the 5C180.

ERASURE CHARACTERISTICS
Erasurecharacterlstics of the 5C180 are such that
erasure begins to occur upon exposure to light with

f-----------!

I~~~i --.......

LAST
INPUT _ _--J

OUTPUT

CURRENT
OmA

VALID OUTPUT

ACTIVE MODE

Icc

----------~----------~~~====~---------------290111-37

Figure 12. 5C180 Standby and Active Mode Transitions
2~96

inter

5C180

inteligent Programming™ Algorithm

DESIGN SECURITY

The 5C180 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and reliable method.
The inteligent Programming Algorithm is particularly
suited to the production programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of· each bit is continLially monitored to determine when the bit has
been successfully programmed.

A single EPROM bit provides,a programmable design security feature that controls the access to the
data programmed into the device. If this bit is set,
proprietary design within ttie device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices
since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with' all the other EPROM control
bits, will be reset by erasing the device.

FUNCTIONAL TESTING

LATCH-UP IMMUNITY

Since the logical' operation of the 5C180 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of the EPROM array are
required.

All of the input, 1/0, and clock pins of the 5C180
have been designed to resist latch-up which is inher- '
ent in inferior CMOS structures. The 5C180 is designed with Intel's proprietary CHMOS II-E EPROM
process. Thus, each of the 5C180 pins will not experience latch-Up with currents up to 100 mA and voltages ranging fronm -1 V to Vee -t' 1V. Furthermore,
the programming pin is'designed to resist latch-up to
the 13.5V maximum device limit. '

The testability and reliability of EPROM-based programmable logic device,s is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic' devices require a
use to perform post-programming tests to insure
proper programming. These tests must be done at
the device level because of the cummulative error
effect. For example, a board containing ten devices
each possessing a 2% device fallout translates into
an 18% fallout at the board level (it shoull:! be noted
that programming fallout of fuse-based programma- .
ble logic devices is typically 2% or higher).

DESIGN RECOMMENDATIONS
For proper operation; it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or VOUT) < Vee. Unused inputs,
should be tied to an appropriate logic level (e.g." either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the logic,
compiler REPORT file) should be left floating (no
connect) so that the pin can attain the appropriate
logic level. A power supply decoupling capacitor of
at least 0.2 ,..,f must be connected directly between
Vee and GND.
As with all CMOS devices, ESD handling procedures
should be used with this device to prevent damage
during programming, assembly, and test.

INTEL PROGRAMMABLE' LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)
iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing deveiopment assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will
optimize a design to benefit from architectural features). It contains' comprehensive third, generation
software that supports several different design entry
methods,minimizes logic, does automatic pin assignments ,and produces the best design .fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.
In· addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Program~
mer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
code output files which'can be downloaded to other
programmers as well.
'
iPLDS II has interfaces to popular schematic capture
packages to enable deSigns to be entered using
schematics. An integrated, schematic entry method
is provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives
and user-defined macro symbols. SCHEMA II-PLD
contains the EPLD DeSign Manager, which provides
a single user interface to both SCHEMA II-PLD and
iPLS II software. TTL symbol and macro libraries are

-n+:..;.r ,',,''"
III-e-

5C180

available for SCHEMA II-PlD to simplify the design
process. The other design formats supported are
Boolean ~quation entry and State Machine design
entry. For additional information,on:iPLDS lI,refer to
the iPlDS II Data Sheet, order number: 290134.

ADF PRIMITIVES SUPPORTED
The following ADF primitiitesare supported by this
device~

iPLDS II operates on the IBMtPC/XT, PC/AT, or
other compatible machine with the following configuration:,
'
1. At least one floppy disk drive and hard disk drive:
2. MS-DOS:j:Op!'lrating System' Version 3.0 or greater.
'"
"
3. 512K Memory (640K recommended).
4. Intel iUP-PC Universal Programmer-Personal
Computer (supplied with iPlDS II).

5~ GUPI

LOGIC Adaptor.

INP
" ,CONF
, COCF
COIF'",
RONF
RORF
ROlF
NOCF
NORF
NOJF
NOSF
NOTF

JOJF
,JQNF'
SONF,
SOSF
TOIF'
TONF
, TOTF
ClKB

6. A color monitor is suggested:
IBM Per~oi1al Computer'is~a registered trademark'of International Business Machines Cor'
poration. "

t
:j:'

MS-DOS is 'a,registered trademark of Micro' "
' ,

soft Corponiti(;m.,

ORDERING INFORMATION
,.

tpo'
, (n5)
70

teo

fMAX

(n5)

, (MHz)

.
:

,'19.6

90,

20.8

·29

Order Code,'

16:1

Package,

CJ5C180-70

'JlCC

N5G180-70

PlCC

A5C180-70

PGA

CJ5C180-75

JlCC

N5C180-75

PlCC

A5C180-75

PGA

CJ5C180-90

JlCC

N5C180-90

PlCC

A5C180-90

PGA

Operatin~

Range "

, Commercial

Commercial

Commercial,

"'\

.. ,

'.,
('

, : >,

,:,

intJ

5C180

*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the opera.tional sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Min

Max

Units

Supply Voltage(1)

-2.0

7.0

Vpp

Programming
Supply Voltage(1)

-2.0

13.5

De Input Voltage(1){2)

-0.5 Vcc+ 0.5

tstg

Storage Temperature

-65

+150

tamb

Ambient Temperature(3)

-10

+85

Vee

Parameter

NOTICE Specifications contained within the
. following tables are subject to change:

NOTES:
1. Voltages with respect to ground.
2. Minimum De input is -0.5V. During transitions. the inputs may undershoot to -2.0V or overshoot to 7.0V for periods less
than 20 ns under no load conditions.
3. Under bias. Extended temperature versions are also available.

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

4.75

5.25

Input Voltage

Vee

Output Voltage

Vee

TA
tR(4)

Operating Temperature

+70

°C

500

tF(4)

Input Fall Time

.500

Parameter

Vee

Supply Voltage

VIN

Input Rise Time

Units

NOTE:
4. tR and tF for clocks is 250 ns.

D.C. CHARACTERISTICS

0' to + 70°C, Vee

5V ±5%
Max

Unit

VIH(5)

High Level Input Voltage

2.0

Vee + 0.3

VIL(5)

Low Level Input Voltage

-0.3

0.8

VOH(6)

High Level Output Voltage
10 = -4.0 mA D.C., Vee = min.

VOL

Low Level Output Voltage
10 = 4.0 mA D.C., Vee = min.

0.45

Input Leakage Current
Vee = max., GND < VIN

±10

/LA

± 10

/LA

Symbol

loz

Parameter/Test Conditions

Min

Typ

2.4

< Vee

Output Leakage Current
Vee = max., GND < VOUT

< Vee

NOTES:
5. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included.
6.10 at eMOS levels (3.84 V) = -2 rnA
7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.
8. With Turbo Bit Off. device automatically enters standby mode approximately 100 ns after last input transition.

2-99

5C180

D.C. CHARACTERISTICS TA = O· to + 70·C, Vee
Symbol

Parameter/Test Conditions

= 5V

± 5% (Continued)

Min

Typ

Max

Unit, ""

rnA

Ise(7)

Output Short Circuit Current
Vee = max., Vour = 0.5V

20'

IsS(8)

Standby Current
Vee = max., VIN
Standby mode

150

fJ-A

rnA

= VeeDr GND,

Power Supply Current
Vee = max., VIN = Vee orGND,
No load, Input Freq. = 1 MHz
Active mode (Turbo = Off),
Device prog. as four 12-bit Ctrs.

.. Iec

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM
3'°-Y20

INPUT
DEVICE
OUTPUT

o-+-....-C> TOSYSTEM
TEST
341.fl.

OUTPUT

°-A-o:a >

TEST POINTS

vrr
-< "Ai!
"

l~-TEST POINTS--~
290111-27

A.G. Testing: Inputs are"Driven at 3.0V fora Logic "1" and OV for
a Logic "0". Timing Measurements are made. at 2.0V for a Logic
" "1" and 0.8V for a Logic "0" on inputs. Outputs are measured at
a 1.5V poinL Device rise and fall times <6ns.

290111..,28

2-100

inter

5C180

CAPACITANCE
Symbol

Parameter

Min

Typ

Max

Unit

Conditions

OV, f

CIN

.Input Capacitance

VIN

COUT

Output Capacitance

VOUT

OV, f

CClK

Clock Pin Capacitance

VOUT

Cvpp

Vpp Pin Capacitance

160

CLK2, VOUT

A.C. CHARACTERISTICS
Symbol

From

O·Cto +70·C, Vcc

SC180-70
EP1800-2

1.0 MHz

=
=

1.0 MHz
1.0 MHz

OV, f

1.0 MHz

5V ±5%, Turbo BitOn(9)
SC180-90
EP1800

SC180-7S

Non-Turbo
Mode(11)

Unit

Min Typ Max Min Typ Max Min Typ Max
tpDl

Input(12)

Comb. Output

tpD2

1/0(12)

tPD2e

1/0(13)

+30

Comb. Output

+30

Comb. Output

+30

tpZX(10) 10rii0

Output Enable

90.

+30

tpXZ(10) 10rii0

Output Disable

+30

Asynch. Reset Q Reset

tClR
NOTES:

9. Typ. Values are at TA = 2S·C, Vee = SV, Active Mode.
10. tpzx and tpxz are measured at ± O.SV from steady state voltage as driven by spec. output load. tpxz is measured with
CL = S pF.
11. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown.

SYNCHRONOUS CLOCK MODE A.C.CHARACTERISTICS
TA =

o·c to

Symbol

+70·C, VCC = 5V ±5%, Turbo Bit On(9)
Symbol

SC180-70
EP1800-2

SC180-90
EP1800

. Non-Turbo
Mode(11)· Unit
Min Typ Max Min Typ Max Min Typ Max
SC180-7S

fMAX

Max Frequency
1/(tcH + tcO-No Feedback

20.8

19.6

16.1

MHz.

fCNT

Max. Count Frequency
1/tCNT-With Feedback

16.1

15.1

12.2

MHz

tSUl

Input Setup Time to Clk(12)

+30

tSU2

1/0 Setup Time to Clk(12)

+30

tSU2e

1/0 Setup Time to Clk(13)

+30

o·

I or 1/0 Hold after Clk High

tco

Clk High to OLitput Valid

tCNT

tCH

elk High Time

tCl

ClkLowTime

2"101

0
30

35
+30

5C180

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
= OOG to +700G , vcc = 5V ±5% , Turbo Bit On(9)

Symbol

Parameter

5Cf80-75

5C180-70
EP1800-2

5C180-90
EP1800

Non-Turb.o
. Mode(ll)

Unit

Min Typ .Max Min Typ Max Min Typ Max
fAMAX

Max. Frequency

20.8

16.6

16.1

15.1

12.2

MHz

11(tACH + tAcLl-No Feedback
fACNT

Max. Frequency

MHz

1/tAcNT-With Feedback

tASUl

Input Setup Time to Asynch. Clock(12)

tASU2

1/0 Setup Til)1e to Asynch. Clock(12)

tAH

Input or 1/0 Hold to Asynch. Clock

tACO

Asynch. Clk to Output Valid

tACNT

+30

'70
62

to Register InputInternal Path
tAcH

ns
ns

75
66

+30 .

Asynch. Clk.High Time

Asynch. Clk Low Time

. ns

,
tACL

NOTES:
12. For General and Global Macrocelis.
13. For Enhanced Macrocelis.

SWITCHING WAVEFORMS
COMBINATORIAL MODE,

, INPUT OR .1/0 INPUT

COMBINATORIAL OUTPUT'

HIGH IMPEDANCE
3.,. STATE

COMBINATORIAL OR '
REGISTERED OUTPUT

HIGH IMPEDANCE
3-STATE

tpzx
VALID OUTPUT

ASYNCHRONOUSLY
CLEAR OUTPUT

290111-29

2-102

5C180

SWITCHING WAVEFORMS (Continued)
SYNCHRONOUS CLOCK MODE

CLK1,CLK2,
CLK3,CLK4

INPUT MAY CHANGE

(fROM REGISTER
TO OUTPUT)

VALID OUTPUT

290111-30

ASYNCHRONOUS CLOCK MODE

ASYN. - - - -.....
CLOCK
INPUT

-----'

OTHER
INPUT

INPUT MAY CHANGE

(fROM REGISTER
TO OUTPUT)

VALID OUTPUT

290111-31

5C180

240

220

200

180

160

~v~/

140

120

100

/Non-Turbo

I
I
20 II
o
60

TA = O'C, Vee

tCNT (MHz)

= S.2SV

290111-32

CUrrent in Relation to Frequency
240

-I"- "-I-J.

220

160

r-- t--

t CNT = 10MHz

r-- r--

tCNT=l MHz,Turbo t-·1· I I 1

I I

140

I I

f--

180

t CNT -20MHz

200

I I I

120
100

I I I

I I

r-- r- tCNT = 1MHz,Non-Turbo

I I I I

8085

TEMP (C)

290111-33

Vee = S.2SV

Current In Relation to Temperature
100
50
20

..........

r---......

IOL

IOH

1'\

Vo Output Voltage (V)
290111-34

Output Drive Current in Relation to Voltage
2-104

5C180

5C180 INTERNAL TIMING
The following internal timing model and specifications are provided to aid in determining the different
timing parameters for all permutations of timing paths through the device. The mnemonics in the table
represent internal parameters only and should not be confused with external timing parameters shown
in previous tables, even though some mnemonics are the same.

SYSTEM CLOCK DELAY tiCS

INPUT
DELAY
tiN

CLOCK DELAY tIC(e)

LOGIC ARRAY DELAY
tLAD(~)

OUTPUT
DELAY
teo
txz
tzx

I/O

FEEDBACK
DELAY

INPUT
DELAY
t lO

lFO

I+290111-38

Symbol

tiN

Parameter

SC180-70
SC180-90
SC180-7S
EP1800-2
EP1800

Non-Turbo
Mode(11)

Min Max Min Max Min Max

Min

Input Pad and Buffer Delay

Unit

Max

ns
ns

tlO

1/0 Input Pad and Buffer Delay

flADe

Enhanced Logic Array Delay

tlAD

Logic Array Delay

too

Output Buffer and Pad Delay

17
17

Output Buffer Enable

15
15

tzx

txz

Output Buffer Disable

tsu

tHS

0
30

tlCe

Enhanced Clock Delay

tiC

Clock Delay

tiCS

System Clock Delay

4
16

0
-30

Feedback Delay

4
10

tFD
tClRe

Enhanced Register Clear Time

tClR

2-105

AB-8

APPLICATION
BRIEF

May 1986

··Implementing Cascaded
Logic in the 5C121

J. R. DONNELL
APPLICATIONS ENGINEER
PROGRAMMABLE LOGIC

Order Number: 292003-001

intJ

AB-8

PROBLEM
Designs that utilize numerous levels of cascaded logic
often result in excessive product terms when expressed
in the sum-of-products form. Although this poses no
problem when designing with discrete logic, EPLDs are
generally optimized for the sum-of-product form. This
stems from the architecture of the basic Macrocell.
Macrocells typically consist of a programmable AND
array feeding a fixed width OR gate: In the 5C121, OR
gate widths range from four to sixteen inputs. For
many applications, sixteen available product terms are
sufficient. However, one example where product terms
become an issue is cascaded exclusive-OR circuits.
Here the number of product terms increase as 2**n
where n equals the number of exclusive-OR gates. If
the number of product terms exceeds sixteen, the equation will not fit directly in the 5C12!.

SOLUTION
There is a simple solution to reduce the product term
requirements when using cascading XOR (or other)
logic. Figure I shows a circuit cascading five exclusive
ORs. As designed, this circuit expands to 32 product
terms when expressed in the minimized sum-of-products form. (This is assuming that signals A thru Fare

single product terms themselves.) Figure 2 shows the
minimized logic equation file produced by Intel's Logic
Optimizing Compiler (iLOC).
An easy solution to fitting this logic into the 5CI21 is
to cascade three exclusive ORs together and then send
the result through a No Output Combinational Feedback primitive (NOCF). This signal can now be cascaded through two more XOR's to get the five total. This
circuit is shown in Figure 3. Figure 4 shows the logic
equation file for this implementation. Note the reduction in product terms from Figure 2. If the buried registers are available, Intel's iPLDs software will automatically assign the combinational feedback to a buried register thereby saving a pin. This technique can be used
for any circuit that generates excessive product terms.
The only penalty in this method is the added delay
needed for the feedback path. The worst case tpd (input
to output delay) for the circuit in Figure 3 would be
twice the specified Tpd in the 5C12I-XX data sheet.
Basically the signal must go through the device twice.
For the 5C121-90 the Tpd would be 180 ns worst case
as implemented in Figure 3.
Figure 5 shows' the report file generated by the compiler. In this case the NOCF path was automatically assigned to the buried 'registers.

._------"

292003-1

Figure 1. Cascaded Exclusive-ORs

r-j-----l

L./F-J~

OUT

292003-2

Figure 3. Cascaded Exclusive-ORs using Combinational Feedback

2-107

inter

AB-8

5Cl2l
cascading exclusive or's
LB Version 3.0. Baseline l7x, 9/26/85

5Cl2l
CASCADING 5XORS WITH COMBINATIONAL
FEEDBACK

PART:

LB Version 3.0, Baseline l7x, 9/26/85·
5Cl2l
PART:

INPUTS:
Ap, Bp, Cp, Dp, Ep, Fp

5Cl2l
INPUTS:
Ap; Bp, Cp, Dp, Ep,Fp

OUTPUTS:

NETWORK:
INP(Ap)
INP(Bp)
INP(Cp)
INP(Dp)
INP(Ep)
INP(Fp)
CONF (NO; Vee)

A
B
C
D
E
F
.0

EQUATIONS:
NO

+
+
+
+
+
+
+
+
+
+
-I:

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

NETWORK:
A
B
C
D
E
F

F • E" • D' ,C' • A' • B'
F' • E • D' • C' • A' • B'
.F' • E' • D • C' • A' • B'
F' • E' • D' ~ C • A' • B'
F' • E' • D' • C' • A' •.B
F' • E' • D' • C' • A * B'
F E • D C' • A'
B'
F • E • D' • C • A' • B'
F • E • D' • C' • A' * B
F • E • D' • C' • A • B'
F • E' • D • C • A' • B'
F • E' • D • C' • A' • B
F • E' • D • C' • A • B'
F • E' • D' • C • A' • B
F • E' • D' • C • A • B'
F • E' • D' • C' • A .• B
F' • E • D • C • A' • B'
F' • E •. D 'C' • A' • B
F' • E • D • C' • A B'
F' • E * D' • C • A' • B
F' • E • D'
C • A • B'
F' • E • D' • C' * A • B
F' * E' • D • C • ·A' • B
F' • E' • D • C • A • B'
F' • E' * D • C' * A *B
F'
E' • D"
C• A• B
F • E • D • C • A' • B
F • E • D • C • A • B'
F • E • D • C' • A • B
F • E • D' • C • A • B
D• C• A• B
F • E'
F'
E • D * C A • B;

· ·

Figure 2. Minimized Logic Equations for Figure 1

N2
EQUATIONS:
N3

INP(Ap)
INP(Bp)
INP (Cp)
INP(Dp)
INP(Ep)
INP(Fp)
CONF (NO, Vee)
NOCF (N3)

D • C' • A' • B'
D' • C • A' • B'
D' • C' • A' • B
D'
C' • A • B'
D • C • A' • B
D * C • A • B'
D * C' • A • B
+ D' • C • A • B;
NO
F • N2' • E'
+ F' • N2' • E
+ F' • N2 • E'
+ F • N2 * E;

+
+
+
+
+
+

Figure 4. Minimized Logic Equations for Figure 3

inter

AB-8

Logic Optimizing Compiler Utilization Report
***** Design ill!plemented successfully
JRD
INTEL
October 8, 1985
1

5C121
CASCADING 5XORS WITH COMBINATIONAL FEEDBACK
LB Version 3.0, Baseline 17x, 9/26/85
5C121
. GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

-I 1
-I 2

-I
-I
-I
-I
-I

4
5
6
7
8
-: 9
-110

40139138:37136135134:331-

321311-

-111

301-

-112
-113
-114
-115
-116
-117
-118
-119
-120

29:28127126125124:231221-

211-

Vce
Vce
Ap
Bp
Cp
Dp
Ep
Fp
0
RESERVED
RESERVED
RESERVED
GND
GND
GND
GND
GND
GND
GND
GND

**INPUTS**
Name

Resource

MCell

PTerms

MCells

INP

Name

P.i.n

Resource

HCell II

PTeloms

CONF

4/ 4

Feeds:
OE

Clear

Feeds:
OE

Clear

Clock

**OUTPUTS**
HCells

292003-3

2-109

inter

AB·8

**SURIED, REGISTERS**
Name

Resource

MCel! II

PTenns

NOCF

8/ 8

MCells

Feeds:
OE

Clear

**UNUSED RESOURCES**
Name

Resource

1
2
3
4
5
6
7
8
9
10
11

12
13

14
15
16
17
18
19
,21
~2

23
24
25
26
27
28
29
30
31

NA
NA

MCell "

28
27
26
25
24
23
22
21
20
19
18
17
12
11
10

9
8
7
6-5
4
3

2
14
15
16

PTerms

4
10
8

6
6

8
10

4
12
4
8
8

8
8
4
12
4
10

8
6
€,

8
10
8

8
8

**PART UTILIZATION**
18%
7%
5%

Pins,
MacroCells
Pterms
292003-4

Figure 5. The Utilization Report

2-110

infef

AB-9

APPLICATION
BRIEF

May 1986

5C121 As A Three
And One Half Digit
Display Driver

THOM BOWNS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292006-001
2-111

Figute 2 illustrates the Boolean equivalents of the design in Figure 1. In the NETWORK section of Figure
2, the inputs and outputs of the design are described.

INTRODUCTION
Described is a method of constructing a multi-digit,
seven segment decoder driver with latching capability
in a single EPLD. The design is a simple, easily understood method of using the Se121 as a seven-segment
display driver.

For instance, the NETWORK equation
SSA1, SA1F = RORF (ISA1, WRN, GND, GND, VCC)

represents that the output pin for segment "A" of the
1st Seven Segment display (SSAl) results from a Registered Output Registered Feedback (RORF) structure in
the EPLD. The feedback signal (SAIF) is the same as
the signal output (SSAl). The RORF's D input is driven by the signal ISAl, the clock input is driven by
WRN, and reset, preset and output enable signals are
tied to their default voltage levels (either GND or

This design has many advantages: (1) the ability to update a single digit without disturbing the others, (2)
Outputs are latched and retain their data without update from the controlling device(s), (3) Input interfacing is simple and straightforward, using four data inputs, two digit select lines, and a data strobe line.
The display driver interface is therefore not limited to
microprocessor applications only (although it can be
used with them). Possible applications include a Mul'timeter display, a clock or timer display, or a simple
controller system display.

vee).
The EQUATION section of Figure 2 shows how the
data distribution and decoding logic works. Equations
starting with A-G are generic seven segment display
equations. Segment decoding results from the combina7
tion of the true or false of the four data inputs (e.g., DO
or !DO).

PROBLEM
The display driver needs to latch the incoming data at
the correct time, route it to the correct digit, and then
decode the four bit data into seven-segment output format.

Equations such as
SE1 = (E

SOLUTION IN EPLD
A simple solution to the display driver imagined above
can be realized in the Se12!. EPl,D.
'The 5e121 EPLD is organized in groups ofM~crocel1s.
Each Macrocell contains a number of multiple input
AND gates which are feeding an OR gate. The OR gate
feeds "a selectable registered output. This output may
also be routed back into the array for feedback purposes.
Figure 1 shows a basic block diagram of the three and
one half digit display driver. The data is input to a
distribution block, which sends the data to one of four
seven-segment decoders depending upon the digit selected by the Digit Select inputs. The outputs are updated by strobing the WR input. The data input is in a
HEX format and may be in the range of 0 to F HEX (0
to 15 Decimal). Digit select' is placed upon the two
select lines in a binary format; 0, 1,2, 3. When data is
present on the input lines and 'a digit is selected, the
strobe line may be pulsed high and that output digit is
'then updated to the numeral s~ggested by the' input
data.

* WE1) +

(SE1F

* !WE1)

show how the data is distributed. Segment E of display
1 (SEl) is valid (ON) if the "E" decode exists and display 1 is chosen by the address inputs (WEI = !AO *
!A 1). It is also valid if it was previously turned on
(SElF) AND seven segment display 1 is not selected
(!WEI).
, These equations may be entered using LB in the form
of a Netlist, or may be entered directly into the ADF by
means of a text editor. The ADF is then compiled and
programmed into a Se121 using iPLS.

SUMMARY
This method of using the se121 as a three and one half
digit display driver is advantageous in respect to its
simple interface, and its ability to hold all other digits
stable while one is being updated. Displays with more
than three and one half digits may be produced in the
Se121 by using the input latches as data storage and by
multiplexing the outputs in a scanning fashion.

2-112

intJ

AB·9

WRO~---------------------------------,

DECODE

~ LATCHES

000------1

010----1
020----t

DATA
DISTRIBUTION

030----t

AO 0------1

A10------I

SELECTION
292006:-'

Figure 1. Block Diagram

2-113

AB-9

Thorn Bowns
Intel
October 29, 1985
1.14
1

5C121
3.5 digit output driver
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5(;121
INPUTS: AOp,A1p,DOp,Dlp,D2p,D3p,WRp
OUTPUTS: SSAI~SSBl,SSC1,SSDl,SSE1,SSFI,SSGI,SSA2,

SSB2,SSC2,SSD2,SSE2,SSF2,SSG2,SSA3,~SB3,SSb3,SSD3,SSE3,SSF3,SSG3,SSA4

NETWORK:
SSA1,SAlF - RORF (ISAI,WRN,GND,GND,VCC)
SSBl,SBlF -- RORF (ISBl,WRN,GND,GND,VCC)
SSCl,SClF = RORF (ISCl,WRN,GND,GND,VCC)

SSD1,SDIF - RORF (ISDI,WRN,GND,GND,VCC)
SBEI,SE1F - RORF (SEI,WRN~GND,GND,VCC)
SSFI,SFlF = RORF (SFI,WRN,GND,GND,VCC)
SSGI,SGIF = RORF (SGI,WRN,GND,GND,VCC)
SSA2,SA2F - RORF (SA2,WRN,GND,GND,VCC)
SSB2,SB2F = RORF (SB2,WRN,GND,GND,VCC)

SSC2,SC2F - RORF (SC2,WRN,GND,GND,V~J)
SSD2,SD2F - RORF (SD2,WRN,GND,GND,VC:C)
SSE2, SE~!F :: RORF (SE2, WRN., GNI)., f3ND, vee)
SSF2,SF2F = RORF (SF2,WRN,GND,GND,VCC)

SSG2,SG2F = RORF (SG2,WRN,GND,GND,VCC)
SSA3,SA3F = RORF (SA3,WRN,GND,GND,VCC)

ssa:1,SB3F
SSC3,SC3F
SSD3,SD3F
SSE3,SE3F
SSF3, SF3F
SSG3,SG3F
SSA4,SA4F

.--

RORF
RORF
RORF
RORF
RORF
= RORF

= RORF

(SB3,WRN,GND,GND,VCC:)
(SC3,WRN,GND,GND,VC:C:)
(SD3,WRN,GND,GND,VCC)
(SE3,WRN,GND,GND,VCC)
(SF3, WRN , GND, GND , vec)
(SG3,WRN,GND,GND,VC:C:)
(SA4,WRN~GND,GND,VCC)

ISAI = NOCF (SAl)
ISBI - ~oeF (S91)
ISC1 = NOCF (SCI)
ISDI - NOCF (SOl)
WRN = NOT (WR)
WR -- INP (WRp)
DO - INP (nOp)
Dl ,,- INP (DIp)
D2 ::: INP (D:~p)
D3 , " INP (D:":;p)
AD ::: INP (AOp)
Al -- INP (Alp)
EI)UATIONS:
A -- ! D3*! D2*! DI*DO + ! D3*D2*! DI*! DO + D3*! D2*D1*DO + D3*D:?*! DI*DO;
B - !D3*D2*!Dl*DO + D2~~1*!DO + D3*D2*!DI*!DO + D3*Dl*DO;
C ::: !D3*!D2*D1*!DO + D3*D2*!DI*!DO + D3*D2*D1;
D _ !D3*!D2*!Dl*DO + !D3*D2*!DI*!DO + D2*DI*DO + D3*!D2*D1*!DO;
E - !D3*!D2*DD + !D3*D2*!Dl + !D3*D2*Dl*DO + D3*!D2*!D1*~O;
F ::: !D3*!D2*!D1*DO + !D3*!D2*Dl + !D3*D2*Dl*rnJ + D3*D2:+:!Dl*DO;
G _. ! D3*! D:2*! DI + ! D:::>*D2*Dl*DO ... D3*D:"~*! DI*! DO;
292006-2

Figure 2. ADF Listing
2-114

AB·9

SA2

= (E * WEI)
+ (SElF *
= (F * WE!)
+ (SFIF *
= (G * WEI)
+ (SGIF *
= (A * WE2)

SB2

= (B *

SEI
SFI
SGI

lWEI);
lWEI);
lWEI);

+ (SA2F
IWE2);
WE2)
+ (SB2F * IWE2);
SC2 = (0 * WE2)
+ (SC2F * IWE2);
SD2 = (D
WE2)
+ (SD2F * I WE2) ;
(E * WE2)
SE2
+ (SE2F
IWE2);
SF2 = (F * WE2)
+. (SF2F * IWE2);
SG2 = (G
WE2)
+ (SG2F
IWE2);
SA3 = (A * WE~n
+ (SA3F * IWE3);
SB3 = (B * WE3)
+ (SB3F * IWE3);
SC3 = (C * WE3)
+ (SC3F * IWE3);
SD3 = (0 * WE3)
+ (SD3F * IWE3);
SE3 = (E * WE3 )
+ (SE3F * IWE3);
SF3 = (F * WE3)
+ (SF3F * IWE3);
SG3 = (G * WE3)
+ (SG3F
IwE3);
SAl = (A * WEI)
+ (SAIF *.IWEI);
SBI = (B * WE!)
+ (SBIF * lWEI);
SCI = (C * WEI)
+ (SCIF * lWEI);
SDI = (0 * WEI)
+ (SDIF * lWEI);
SA4 = «ID3*'D2*!DI*IDO) * WE4) + (SA4F * IWE4);
WEI = !AO * !AI;
WE2
AD * !AI;
WE3 = !AO * AI;
WE4 = AD * AI;
END$

Figure 2. ADF Listing (Continued)

2-11~

292006-3

APPLICATION
. BRIEF

AB-10

June 1986

Square Pegs in Round Holes-A
Fitting Tutorial for the 5C121

J. R. DONNELL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292014-001
2-116

intJ

AB-10

INTRODUCTION
This application brief explores the various techniques
for getting the most out of Intel's line of Erasable Programmable Logic Devices (EPLDs). In many cases,
techniques discussed here will not be needed due to the
intelligent fitting algorithms built into Intel's Programmable Logic Software (iPLS). As a matter of fact, most
designs can be implemented in EPLDs without any
knowledge of the device architectures. For complex designs, the designer will still need an in-depth understanding of the target EPLD in order to maximize the
EPLD's utility.
This application brief explores fitting techniques for the
5Cl21, a 1200 gate equivalent CHMOS EPLD. The
techniques described here will also apply to any EPLD
that supports a similar architecture.

FITTING
When fitting logic designs into the 5CI21 there are two
typical scenarios: I) The 5CI21 design has been completed without pin assignments and the compiler warns
the user that fitting may be time consuming, and 2) pin
assignments have been made and the '''***ERR-FIT
... " message comes up.

Once the basic 5Cl21 architecture is understood, intelligent pin assignments can be made. After assigning the
pins recompile the design using iPLS.
Compiling the design with pin assignments is a new ball
game. This time it is fit or not fit. If the design does not
fit, an error like: "'**ERR-FIT-It is not possible to
fit the specific pin requests you made" will occur. In
most cases, the compiler will also ask if it can remove
pin assignments and try its own. If the design has already been attempted without pin assignments, or if
specific pin assignments are needed, answer no and isolate the problem.

ISOLATE THE PROBLEM
The first step towards isolating the problem is to print
out a copy of the utilization report ( < Filename> .RPT), logic equation file « Filename> .LEF),
al)d the Advanced Design File «Filename> .ADF).
Next, fill out the 5Cl21 architecture worksheet included in this application brief. Include the signal name for
each pin, the type of output, and the number of product
terms needed for each output. All this information is
available in the files that were printed earlier. The next
step is to identify the conflict.

Let's look at the first situation.

CONFLICTS

In general, if the designer does not care what signals get
assigned to what pins, the choice can be left to the
compiler and the compiler will make pin assignments.
For simple designs pin assignments are very easy. However, designs that include a variety ,of different register
types, feedback paths, and product term widths may
take a long time for the compiler to fit. When the designer is faced with the message, "Fitting may be time
consuming", the compilation should be aborted, and
intelligent pin assignments made. NOTE: Control C
(AC) may be used to abort a design. The software will
not stop immediately because the software does not poll
the keyboard until it updates the display. Rebooting the
system will also work.

There are three potential conflicts with pin assignments
in the 5C 121; incompatible output structures, excessive
product terms, and 10caVglobai feedback conflicts: Incompatible output structures and excessive product
term errors are the easiest to spot.

To make intelligent pin assignments, the designer needs
a basic understanding of the architecture of the part.
For the 5CI21 this understanding should include the
number of product terms supported in each Macrocell,
what Macrocells support local feedback, and what
Macrocells support global feedback. This information is
easily found in the data sheet. One other point, the
Macrocells in the 5CI21 are grouped into groups of
four. All Macrocells in a group must have the same
output type. Therefore, if one output is registered, the
other three must also be registered. This means that a
combinatorial output could not be put into the same
group as a registered output. Output enable (OE) terms
are also based on Macrocell grouping. All four Macrocells are driven from the same OE term.

INCOMPATIBLE OUTPUT
STRUCTURES
As shown in ,the 5Cl21 Design Worksheet, the 5CI21
is divided into six Macrocell groupings. The data sheet
refers to these as the A-I, B-1, A-2, B-2, A-3, and B-3
Macrocells. One requirement of the 5Cl21 architecture
is that Macrocells within the same grouping have the
same output structure. This was discussed earlier, but it
is worth revisiting. The file titled example I in the appendix shows an ADF for a design that contains such
an I/O conflict. Following the ADF is a completed
5Cl21 architecture worksheet with a number of problems. Concentrating on the incompatible output problem on the 5CI21 worksheet, notice that pins 31 and 32
belong to the same Macrocell group, and that they are
assigned conflicting I/O structures.
The solution to an incompatible output structure conflict may be as simple as reassigning pins. .Another option may be to use a different output type for that sig-

intJ

AB-10

nal.·This is very dependent on the design. Anotheroption is possible when a Macrocell grouping has been
assigned combinatorial output structure, and a registered output needs to be assigned to that same group. A
possible solution is to use one of the buried registers
configured as a NORF (No Output Registered Feedback) cell to hold the signal, and then send the signal
out through a CONF (Combinatorial Output No Feedback) primitive. This output primitive is compatible
with the other output primitives in that grouping, and
the register output requirement has also been satisfied.
The penalty is loss of speed due to the additional feedback path.

EXCESSIVE PRODUCT TERMS
Excessive product term conflicts are also easy to spot.
(A product term consists of a set of signals ANDed
together which are separated from other ANDed
groups by an OR gate.) Written next to the I/O slot on
the 5C121 architecture worksheet is the number of
product terms that each Macrocell supports. Match
that number with the number of product terms for each
output indicated in the logic equation file (LEF). If
more product terms are required of a output than are
provided, there is a product term. conflict. The utilization report also shows the number of product terms
used for each signal.
The solution, again, may be as simple as reassigning
pins since the 5C121 supports varying product term
widths. In fact, the 5C121 supports up to 16 product
terms on pins 16 and 24. Note that four of those product terms are shared with the adjacent Macrocell. Sharing means that those signals are common. It is not
product term allocation. If the number of product
terms exceeds the capability of the device, the design
may still fit by splitting up long equations and inserting
NOCF (No Output Combinatorial Feedback) primitives. Again the price for using this solution is reduced
speed. This technique is covered more thoroughly in
AB-8 tided: Implementing' Cascaded Logic iiI the
SCl2l.

LOCAL/GLOBAL FEEDBACK
It is possible to encounter one other type of fitting con-

flict in the 5C121. This occurs'when a feedback signal
from the A-I or A-2 Macrocells feeds the.B-l or B-2
Macrocells. The issue is that these Macrocells feed busses that are local to one half of the chip. Therefore, the
signal is not physically ·available to the other side of the
device.
The best way to understand the local and global bussing in the 5C121 is to divide the chip in half1engthwise.
One side contains the A Macrocells, and the other side

contains the B Macrocells. The two sides are mirror
images. Speaking generically now, the -1 'and -2 Macro.cells feed only local busses; local to their respective side
of the device. The -3 Macrocells and the buried registers feed global busses which route signals to both sides
of the device. Therefore a feedback signal coming from
the A-lor A-2 group can only feed the A Macrocells,
however, a feedback signal from the. A-3 group could
feed the B-1, B-2, B-3, or the B buried Macrocells. This
local!global bussing applies to both feedback and input
signals on the I/O pins. All of the dedicated inputs feed
the global bus.
Example 1 also shows a simple two bit counter with
seven segment driver outputs. The worksheet shows
that the counter registers were assigned to pins 27 and
28, while the seven segment outputs were assigned to
pins 8 thru 14. The seven segment outputs decode the
feedback signals from the counter registers to generate
the appropriate digit output, and therefore must have
access to those signals. This presents a local!global
feedback conflict. If the designer is locked into those
specific pin assignments.a design workaround is needed.
One solution might be to take the outputs of the counter and externally tie them to dedicated input pins
thereby making those signals global. This would work
but that solution ends up wasting input pins. A better
solution would be to internally route the counter feedback signals through one of the buried registers configured as a NOCF primitive. After passing through the
buried register the signals become global. Both the incompatible output solution and this solution are shown
in the worksheet, ADF, and utilization report shown as
example 2. If we did not need the counter signals externally, it would of been wise to' simply use the buried
registers to perform the counting function.
One final comment regarding the utilization report.
The utilization report shown in example 1 indicates
that signals CLK and CNT feed Macrocell 1001 and
1002. These are fictitious Macrocell numbers that the
software assigns to requests that cannot be met. In example 1, three requests were unfulfilled: REGOUT,
LEDI and LEDO. REGOUT was unfulfilled because of
incompatible output structures. LEDO and LED 1 were
unfulfilled because their feedback signals needed to
drive the seven segment display outputs. This was impossible because the LED outputs were assigned to a
local bus on the opposite side of the device.
The files shown in example 2 fix the LED fitting problems by sending thefeedback signals through the buried
registers, thereby making them global. In the case of
REGOUT, the buried register primitive NORF (No
Output Registered Feedback) is used, allowing the output primitive to be combinatorial.

2-118

AB-10

EXAMPLE 1

ADF
JR Donnell
Intel
April 3, 1986

o
5C121
Fitting exa.ple
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C121
INPUTS: CNT82,CLK81
OUTPUTS, LED0828,LED1827,REGOUT832,CONFOUT831,SEGA88,
SEGB89,SEGC810,SEGD811,SEGB812,SEGF813,SEGG814
NBTWORK:
LEDO,A
RORF (NLBDOD,CLK,GND,GND,VCC)
LEDl,B
RORF (NLBDID,CLK,GND,GND,YCC)
RBGOUT
RONF (NREGOUTD,CLK,GND,GND,VCC)
CONFOUT
CONF (NCONFOUTIN,YCC)
SEGA
CONF (NSEGAIN,YCC)
SEGB
CONF (NSBGBIN,YCC)
SEGC
CONF (NSEGCIN,YCC)
SEGD
CONF (NSBGDIN,YCC)
SEGE
CONF (NSBGBIN,YCC)
CONF (NSEGFIN,YCC)
SEGF
SEGG
CONF (NSBGGIN,YCC)
CLK
INP (CLK)
CNT
INP (CNT)
EQUATIONS:
NSEGGIN = 2
+ 3;
2
B*/A;
3 = A*B;
NLEDID
/A*/B*CNT
+ /UB*/CNT
+ A*/B*CNT
+ A*B*/CNT;
NLEDOD
/A*B*CNT
+ U/B*/CNT
+ A*/B*CNT
+ A*B*/CNT;
NSBGFIN = 0;,
o = /B*/A;
NSBGEIN
'0
+ 2;
NSEGDIN
0
+ 2
+ 3;
NSBGCIN
0
+ 1
+ 3;
1
/B*A;
NSBGBIN
0
+ 1
+ 2
+ 3;
NSEGAIN
0
+ 2
+ 3;
NCONFOUTIN
A*B;
NRBGOUTD = /A*/B;
END$

=
=
=
=

=
=

292014-2

2-119

inter

AB~10

SUMMARY
As programmable logic devices become more dense, signal routing and resource partitioning becomes necessary. In
general, these choices are made by the semiconductor manufacture to most efficiently utilize the available logic. In
some cases though, these choices make certain designs more difficult to implement in a given device. Intelligent
software, a basic knowledge of the device architecture, and a little experience in fitting techniques will always make
the job easier.

EXAMPLE 1 (Continued)
5C121 Design Worksheet

292014-1

intJ

AB-10

EXAMPLE 1 (Continued)
Logic Optimizing Compiler Utilization Report

*****

Unable to implement design

JR Donnell
Intel
April 3, 1986

o
5C121
Fitting eKample
LB Version 3.0, Baseline 17K, 9/26/85
5C121
CLK
CNT
GND
GND
GND
GND
GND
SEGA
SEGB
SEGC
SEGD
SEGli
SEGF
SEGG
RESERVED
GND
GND
GND
GND
GND

1
2
3
4
5
6
7
8
9
-:10
-: 11
-: 12
-:13
-: 14
-:15
-:16
-:17
-: 18
-: 19
-:20

-:
-:
-

40:39:38:37:36:35:34:33:32:31 :30:29:28:27:26:25:24:2-3 :22:21 :-

Vee
Vcc
GND
GND
GND
GND
GND
GND
RESERVED
CONFOUT
RBSER'yED
RESERVED
GND
GND
GND
GND
GND
GND
GND
GND

UINPUTS**
Nalle

CLK
CNT

Resource

MCell

PTerms

MCells

Feeds:
DE

Clear

Clock
Reg

INP
2

INP

Name

Resource

MCell 1/

PTerms

SEGA

CONF

2/ 4

SEGB

CONF

2/10

SIlGC

CONF

2/ 8

SEGD

CONF

2/ 6

1001
1002

UOUTPUTS**
MCells

Feeds:
OE

Clear

292014-3

2-121

inter

AB-10

EXAMPLE 1 (Continued)
SBGB

CONF

1/ 6

SBGF

CONF

1/ 8

SBGG

CONF

1/10

CONFOUT

CONF

1/10

**UNFULFILLED REQUESTS**
**OUTPUTSn

RONF

MCell It
1000

PTerDls
1

MCells

REGOUT
LRD1

HORF

1001

2
22
23
25
26
28
1000
1001
1002

LI!DO

ROHF

1002

2
23
24
25
26
27
28
1000
1002

Resource,

MCell

PTerms

21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
1

4
12
4
8
8
8
8
4
12
4
10
8
6
6
8
4

13
14
15
16

8
8
8
8

Nalle

Re80urce

Feeds:
OR

Clear

**UNUSRD RI!SOURCI!S**
Name

Pin
3
4
6
6
7
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
32
33
34
36
36
37
38
NA
NA
NA
NA

2-122

292014-4

292014-5

inter

AB-10

EXAMPLE 2

ADF
JR Donnell
Intel
April 3, 1986

o
5C121
Fitting example
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C121
INPUTS: CNT@2,CLK@1
OUTPUTS: LEDO@28,LEDl@27,REGOUT@32,CONFOUT@31,SEGA@8,
SEGB@9,SEGC@10,SEGD@11,SEGE@12,SEGF@13,SEGG@14
NETWORK:
LEDO,NATONOCF
RORF (NLEDOD,CLK,GND,GND,VCC)
RORF (NLEDID,CLK,GND,GND,VCC)
LEDl,NBTONOCF
REGOUT
CONF (NREGOUTIN,VCC)
CONFOUT
CONF (NCONFOUTIN,YCC)
SEGA
CONF (NSEGAIN,YCC)
SEGB
CONF (NSEGBIN,YCC)
SEGC
CONF (NSEGCIN,YCC)
SEGD
CONF (NSEGDIN,YCC)
SEGE
CONF (NSEGEIN,YCC)
CONF (NSEGFIN,VCC)
SEGF
SEGG
CONF (NSEGGIN,YCC)
A
NOCF (NATONOCF)
CLK = INP (CLK)
B
NOCF (NBTONOCF)
NREGOUTIN
NORF (NREGOUTD,CLK,GND,GND)
CNT
INP (CNT)
.
EQUATIONS:
NLEDOD
IA*B*CNT
+ A*/B*/CNT
+ U/B*CNT
+ A*B*/CNT;
NLEDID = IA*/B*CNT
+ IA*B*/CNT
+ U/B*CNT
+ A*B*/CNT;
NCONFOUTIN
A*B;
NSEGAIN
0
+ 2
+ 3;
NSEGBIN
0
+ 1
+ 2
... 3;
NSEGCIN
0
+ 1
+ 3;
NSEGDIN
0
+ 2
+ 3;
NSEGBIN
0
+ 2;
NSEGFIN
0;
NSBGGIN
2
+ 3;
NREGOUTD
IA*/B;
2
U/A;
3
A*B;

=
=

=
=
o = IB*/A;
1 = IB*A;

END$

292014-7

2·123

inter

AB-10

EXAMPLE 2 (Continued)
5C121 Design Worksheet

~
~

....lliL
SEG.

LEDO

2~2014-6

2-124

inter

AB-10

EXAMPLE 2

(Continued)

Logic Optimizing Coapiler Utilization Report

*****

Design i.ple.ented successfully

JR Donnell
Intel
April 3, 1986

o
5Cl21
Fitting exaaple
LB Version 3.0, Baseline 17x, 9/26/85
5C12l
CLK
CNT
GND
GND
GND
GND
GND
SEGA
SEGB
SEGC
SEGD
SHGE
SEGF
SEGG
RESERVED
GND
GND
GND
GND
GND

-: 1

-: 2

3
-: 4
-: 5
- 6
-: 7
-: 8
-: 9
-110
-: 11
-:12
-: 13
-114
~: 15
-116
-:17
-: 18
-: 19
-:20

40:39:38:37:36:35:34:33:32:31:30:29:2S:27:26:25:24:23:22:21:-

Vee
Vee
GND
GND
GND
GND
GND
GND
REGOUT
CONFOUT
RESERVED
RESERVED
LEDO
LBD1
RESERVED
RESERVED
GND
GND
GND
GND

*UNPUTS**
Naae

Resource

CLK

INP

CNT

INP

Name

Resource

MCell #

PTeras

SEGA

CONF

2/ 4

SEGB

CONF

2/10
2/ 8
2/ 6

MCell #

PTe rills

MCells

Feeds:
OE

Clear

Clock
Reg

5
6

UOUTPUTS**

SEGC

CONF

26'

SEGD

CONF

MCells

Feeds:
OJ!

Clear

292014-8

2-125

infef

AB-10

EXAMPLE 2 (Continued)
SI!GI!

CONF

SBGF

CONF

1/ 8

SI!GG

CONF

1/10

LI!D1

RORF

2/ 8

LI!DO

RORF

3/ 6

CONFOUT

CONF

1/10

RI!GOUT

CONF

1/ 6

1/ 4

**BURII!D RI!GISTI!RS**
Na.e

Resource

MCe11 #

PTer.s

MCe11s

NOCF

1/ 8

2
5
6
15
22
23
25
26
28

NOCF

1/ 8

2
5
15
23
24
25
26
27
28

NORF

1/ .8

Resource

MCe11

PTeras

21
20
19
18
17
12
11
10
9
8
7

4
12
4
8
8
8
8
4
12
4
10
6

Feeds:
Ol!

Clear

**UNUSED RI!SOURCI!S**
Name

3
4
5
6
7
15
16
17
18
19
21
22
23
24
25
26
29

292014-9

2-126

inter

AB-10

EXAMPLE 2 (Continued)
30
33
34
35
36
37
38
NA

nPART UTILIZATIONn

35%
50%
10%

Pins
MacroCells
Pterms

292014-10

2-127

inter

AB-11

APPLICATION
BRIEF

February 1987

16-Bit Binary Counter·
.Implementation
Using the 5C060 EPLD

KARL-HEINZ WEIGL
INTEL CORPORATION
MUNICH, GERMANY

Order Number: 292015-002
2-128

AB-11

INTRODUCTION

TOGGLE FLIP-FLOPS

System designers often use programmable logic devices
to implement counters. Use of PLA devices lets the
user build customized counters to suit individual applications. In most cases such counters are not available,
'off-the-sheIr SSI/MSI devices. In other applications,
the PLA implementation allows the designer to squeeze
the counter function along with other 'glue' tasks into a
single PLA, with the attendant higher integration benefits.

Counters can be most effectively implemented in PLA
architectures using toggle flip-flops. This is because
counters constructed with 'D' type flip-flops require an
additional product term for every successive significant
bit, whereas toggle flip-flop implementation requires
only one product term per significant bit. Thus, the
toggle flip-flop counter design is more miserly in product term consumption than the 'D' register design.
Since product term minimization is the key element to
maximizing PLA utilization, the T-FFcounter design
is more efficient. The truth table for the toggle flip-flop
is shown in Fig. 2.

Use of traditional 20-pin and 24-pin PLAs, however,
does not allow for the construction of large counters
having greater than 10 significant bits. This is because
these traditional PLAs have register and product term
restrictions (even the larger bipolar PLAs have only 8
to 10 registers and less than 8 product terms per register). In contrast, the SC060 24-pin erasable programmable logic device (EPLD) contains 16 registers that
are programmable as 'D', 'T', 'RS' or 'JK' types. These
16 programmable registers enable the construction of
Up/Down counters with up to 16 significant bits.
This application brief details the implementation of a
16-bit binary counter in the SC060 EPLD. The design
also demonstrates efficient counter construction utilizing toggle flip-flops (T-FF) that allows for minimum
product term utilization.

DESIGN OBJECTIVE
The objective of the design is to implement a counter
with the following features: (i) 16-bit binary count, (ii)
toggle flip-flops, (iii) asynchronous clear, (iv) RUN/
STOP function and (v) UP/DOWN function. The
function table is shown in Figure 1.
RESET UP/DOWN RUN/STOP

X
0
0
1

X
0
1
X

0
1
1
X

Function

Q(N)

0
0
1
1

0
1
-0
1

Q (N

+ 1)

0
1
1
0

Figure 2

SOLUTION
The 16-bit binary counter function was implemented in
the SC060 EPLD using the Intel Programmable Logic
Development System (iPLDS). The equations for the
16-bit binary counter with the RESET, UP/DOWN
and RUN/STOP functions are shown in the 'EQUATIONS' section of the LEF (Fig. 4). The pinout of the
SC060 with the implemented counter is shown in the
RPT file (Utilization Report) Fig. S. This RPT file also
shows, under the 'OUTPUTS' section, that in each
macrocell only one out of 8 product terms is used. In
contrast the same 16-bit counter designed using 'D'
type flip-flops would have required more than 16 product terms for the last significant bit.

Inhibit Counting
Count Down
Count Up
Reset All Outputs
to 'LOW'

Figure 1

2-129

inter

AB·11

INTEL CORPORATION
JAN. 15, 1987

1
1.0
5C060
, BINARY' 16-BIT UP/DOWN COUNTER WITH 'RUN/STOP AND ASYNCH. RESET USING T-FF
LB Version 4.01, Baseline 27.1 4/9/86
OPT IONS: TURBO=ON
PART: 5C060
INPUTS: RS, CLOCK, RESET, UD
OUTPUTS:QO, Ql, Q2, QS, Q4, Q5, Q6, Q7, Q8, Q9, QA,QB, QC, QD, QE, QF

NETWORK:
QO,QOF = TOTF (QOT,CLK,CLR,GND,VCC)
Ql,QIF = TOTF (QIT,CLK,CLR,GND,VCC)
Q2,Q2F = TOTF (Q2T,CLK,CLR,GND, VCC),
QS,Q3F = TOTF (QST,CLK,CLR,GND,VCC)
Q4,Q4F= TOTF (Q4T,CLK,CLR,GND,YCC)
Q5,Q5P' = TOTF (Q5T,CLK,CLR,GND,VCC)
Q6,Q8P' = TOTF (Q6T,CLK,CLR,GND, YCC)
Q7,Q7F = TOTF (Q7T, CLK,CLR,GND, VCC)
Q8,Q8F = TOTF (Q8T,CLK,CLR,GND,VCC)
Q9,Q9F = TOTF (Q9T, CLK,CLR,GND, VCC)
QA,QAJ' = TOTF (QAT,CLK,CLR,GND, YCC)
QB,QBF = TOTF (QBT,CLK,CLR,GND, YCC)
QC,QCP' = TOTF (QCT, CLK,CLR,GND, YCC)
QD,QDP' = TOTF (QDT,CLK,CLR,GND, YCC)
QE,QKlI' = TOTF (QET, CLK,CLR,GND, YCC)
QF = TONF (QFT,CLK,CLR,GND,VCC)
QOT = OR (QOU,QOD)
CLK= IN!! (CLOCK)
CLR =, IN!! (RESET)
QIT = OR (QIU,QID)
Q2T, = OR (Q2U,Q2D)
Q3T = OR (QSU,Q3D)
Q4T ~ OR (Q40,Q4D)
Q5T = OR (Q50,Q5D)
Q8T = OR (Q60,Q8D)
Q7T = OR (Q70,Q7D)
Q8T = OR (Q8U,Q8D)
Q9T, = OR (QSO,Q9D)
QAT = OR (QAU,QAD)
QBT = OR (QBU,QBD)
\lCT = OR (QCO,QCD)
QDT = OR (QDO,QDD)
\liT = OR (QEU,QED)
QFT = OR (QFU,QFD)
as = INP (RS)
OD = IN!! (UD)
HOD = NOT (OD)
QOO = AND (OD,RS)
292015-1

Figure 3. Example .ADF

2-130

inter
Q1U
Q2U
QSU
Q4U
Q6U
Q6U
Q7U
Q8U
Q9U
QAU

AB·11

= AND
= AND

(UD,QOF,QOU)
(OD,Q1F,Q10)
(UD,Q2F,Q2U)
= AND (UD,Q3F,Q30)
= AND (UD,Q4F,Q4U)
= AND (UD,Q5F,Q5U)
= AND (UD,Q6F,Q6U)
= AND (UD,Q7F,Q7U)
= AND (UD,Q8F,Q8U)
AND (UD,Q9F,Q9U)
QBU = AND (UD,QAF,QAU)
QCU = AND (OD,QBF,QBU)
'100
AND (UD,QCF,QCU)
QlU = AND (OD,QDF,QDU)
QJ'U = AND (UD,QEF ,QEU)
NQOI!' = NOT (QOF)
NQ1F = NOT (Q1F)
NQ21!' = NOT (Q21!')
NQ31!' = NOT (Q3F)
NQ4I' = NOT (Q4I')
NQ61!' = NOT (Q51!')
NQ81!' = NOT (Q6F)
HQ71!' = NOT (Q7F)
NQ81!' = NOT (Q8F)
NQ91!' = NOT (Q9F)
NQAF = NOT (QAF)
HQBI!' = NOT (QBF)
NQCI!' = NOT (QCF)
NQDI!' = NOT (QDF)
HQlI!' = NOT (QEF)
QOD = AND (NUD,RS)
Q1D = AND (NUD,HQOF,QOD)
Q2D = AND (MUD,NQ1F,Q1D)
Q3D = AND (MUD,HQ2F,Q2D)
Q4D = AND (NUD,HQ3F,Q3D)
Q6D = AND (NUD,NQ4F,Q4D)
Q6D = AND (NUD, NQSF ,Q5D)
Q7D = AND (NOD, NQ6F, Q6D)
Q8D = AND (NUD,NQ7F,Q7D)
Q9D
AND (NUD,NQ8F,Q8D)
'lAD = AND (NOD,HQ9F,Q9D)
QBU = AND (NUD, NQAF, 'lAD)
QCD
AND (NOD,NQBF,QBD)
QDD = AND (NUD,NQCF,QCD)
QID = AND (NOD,HQDF,QDD)
QI!'D = AND (NUD, HQEF , QED)

= AND

=
=

IND.

292015-2

Figure 3, Example ,ADF (Continued)

2-131

intJ

AB-11

INTEL CORPORATION
JAN. 15, 1987

1
1.0
5C060
BINARY 16-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF
LB Version 4.01, Baseline 27.1 4/9/66
LEF Version 4.01 Baseline 22.2 2/4/86
OPTIONS: TURBO=ON
PART:
5C060
INPUTS:
RS , CLOCK, RESET, UD
OUTPUTS:
oo,m,~,~,~,~,~,~,~,~,~,~,OC,~,~,~

NETWORK:
CLK = INP(CLOCK)
RS = INP(RS)
CLR = INP(RESET)
UD = INP(UD)
QO, QOF = TOTF(QOT, CLK,
Ql, QlF = TOTF(Q1T, CLK,
Q2, Q2F = TOTF(Q2T, CLK,
Q3, Q3F = TOTF(Q3T, CLK,
Q4, Q4F
TOTF(Q4T, CLK,
Q5, Q5F
TOTF(Q5T, CLK,
Q6, Q6F = TOTF(Q6T, CLK,
Q7, Q7F = TOTF(Q7T, CLK,
Q6, Q8F = TOTF(Q8T, CLK,
Q9, Q9F = TOTF(Q9T, CLK,
QA, ~F = TOTF(~T, CLK,
QB, QBF = TOTF(QBT, CLK,
QC, QCF = TOTF(QCT, CLK,
QD, QDF = TOTF(QDT, CLK,
~, ~F = TOTF(~T, CLK,
QF = TONF(QFT, CLK, CLR,
EQUATIONS:
QFT = UD'
~F'
QDF'
Q5F'
Q4F'
Q3F'

CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLR,
CLK,
GND,

GND,
GND,
GND,
GND,
GND,
GND,
GND,
GND,
GND,
GND,
GND;
GND,
GND,
GND,
GND,
VCC)

VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)

*
* QCF' * QBF' * QAF' * Q9F' * QBF' * Q7F' * Q6F' *
*
*
* Q2F' * Q1F' * OOF' * RS
Q4F * Q3F * Q2F * Q1F * QOF * RS;
= UD' * QDF' * QCF' * QBF' * QAF' * Q9F' * Q6F' * Q7F' * Q6F' * Q5F' *
Q4F' * Q3F' * Q2F' * Q1F' * QOF' * RS
+ UD * ~F * QCF * ~F * QAF * Q9F * Q6F * Q7F * Q6F * Q5F * Q4F *
+~*~*-*~*~*QAF*~*~*~*~*~*

QET

Q3F
QDT = UD'
Q3F'

* Q2F * Q1F * QOF * RS;

QCF'
Q2F'

* QBF' * ~F' * Q9F' * Q6F' * Q7F' *

* Q1F' * QOF' * RS

Q6F'

* Q5F' * QU' *

+~*~*~*QAF*~*~*~*~*~*~*~*

Q2F

* Q1F * OOF * RS;

292015-3

Figure 4. Example .LEF

2-132

infef

AB-t1

QeT

= uO'

* QBF' * QAF' * Q9F' * QeF' * Q7F' * Q6F' * Q5F' * Q4F' * Q3F' *
Q2F' * Q1F' * QOF' * R5

+~*~*QAF*~*~*~*~*~*~*~*~*

Q1F * QOF * RS;

QBT

= uO'

* QAF' * Q9F' * QeF' * Q7F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' *
Q1F' * QOF' * R5

+~*QAF*~*~*~*~*~*~*~*~*~*

QOF * R5;

QAT

= UO'

* Q9F' * Q8F' * Q7F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' *
QOF' * R5
* Q6F* Q5F * Q4F * Q3F * Q2F * Q1F * QOF *
RS;

+ UO * Q9F * Q8F * Q7F

Q9T

= UO'
R5

* QeF'

* Q7F'

* Q6F'

* Q5F' * Q4F'

+ UO * QeF * Q7F * Q6F * Q5F

Q8T
Q7T

= UO'

* Q7F'

* Q7F *
= UO' * Q6F'
+ UO * Q6F *
+ UO

* Q4F

* Q3F' * Q2F'

* Q3F * Q2F

* Q6F' * Q5F' * Q4F' * Q3F'
Q6F * Q5F * Q4F * Q3F * Q2F

* Q1F

Q1F'

* QOF'

* QOF * RS;

* Q2F' * Q1F' * QOF'
* Q1F * QOF * RS;

* RS

* Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * R5
Q5F * Q4F * Q3F * Q2F * Q1F* QOF * RS;

Q6T = UO' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * RS
+ UO * Q5F * Q4F * Q3F * Q2F * Q1F * QOF * RS;
Q5T = UO' * Q4F' * Q3F' * Q2F' * Q1F' * QOF'
+ UO * Q4F * Q3F * Q2F * Q1F * QOF * RS;

* R5

Q4T = UO' * Q3F' * Q2F' * Q1F' * QOF' * RS
+ UO * Q3F * Q2F * Q1F * QOF * RS;
Q3T
Q2T

= UO'

* Q2F' * Q1F' * QOF' * R5
* QOF * RS;

+ UO * Q2F * Q1F

= UO' * Q1F' * QOF' * R5
+ UO * Q1F * QOF * RS;

Q1T = UO' * QOF' * RS
+ UO * QOF * RS;
QOT = R5;
ENOS

292015-4

Figure 4. Example .LEF (Continued)

2-133

AB-11

Logic Optimizing Compiler Utilization Report
FIT Version 4.01 Baseline 27.1 4/9/86

*****

Design implemented :successfully

**** NOTE:

Connect signal CLOCK to

pin 1 AND pin 13.

INTEL CORPORATION
JAN. 15. 1987
1
1.0
5C060
BINARY 16-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF
LB Version 4.01. Baseline 27.1 4/9/86
OPTIONS: TURBO=ON
5C060
CLOCK
GND
Q7
Q6
Q5
Q4
Q3
Q2
Ql
QO
UD
GND

-I
-I
-I
-I
-I
-I
-I
-I
-I

1
2
3
4
5
6
7
8
9

-:to

-Ill
-112

24:- Vee
231- RS
22121 I 201'191181171161151 141 13: -

QF
QE
QD

QC
QB

Q9
Q8
RESET
CLOCK

**INPUTS**
Name

CLOCK

Resource

MCell II

PTerms

MCells

Feeds:
OE

Clear

INP

GND

GNP

CLOCK

INP

RESET

INP

Clock
CLKl
CLK2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

CLK1
CLK2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
292015-5

Figure 5. Example .RPT File

2-134

intJ

AB-11

IMP

Vee

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13

14
15
16

**OUTPUTS**
Name

Resource

HCell II

PTerms

HCells

TOTF

2/ 8

1
2
3
4
5
6
7
8

TOTF

2/ 8

1
2
3
4
5
6
7
8
9

TOTF

2/ 8

1
2
3
4
5
6
7
8
9
10

TOTF

2/ 8

1
2
3
4
5
6
7
8
9
10
11

Feeds:
OE

Clear

Clock

292015-6

Figure 5. Example .RPT File (Continued)

2-135

intJ

AB-11

TOTF

2/ 8

1
2
3
4
5
6
7
8
9
10
11
12

TOTF

2/ 8

1
2
3
4
5
6
7
8
9
10
11
12
13

'TOTF

2/ 8

1
2
3
4

5
6
7
8
9
10
11
12
13
14
QO

TOTF

1/ 8

TOTF

2/ 8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2

3
4
5
6
7
Q9

TOTF

2/8

1
2
3
4
5
6

TOTF

2/ 8

1
2
3
4
5

292015-7

Figure 5:. Example .RPT File (Continued)

2-136

. AB-11

TOTF

' 5

2/ 8

TOTF

2/ 8

1
2
3
4
1

2
3
QD

TOTF

2/ 8

TOTF

2/ 8

TONF

1
2

2/ 8

**UNUSED RESOURCES**
Name

Resource

. MCell

PTerms

**PART UTILIZATION**
95%
100%
24%

Pins
MacroCells
Pterms
292015-8

Figure 5. Example .RPT File (Continued)

2-137

inter

APPLICATION
BRIEF

AB-12

October 1988

Designing a Mailbox Memory for
Two 80C31 Microcontrollers Using
EPLDs

K. WEIGL & J. STAHL
INTEL CORPORATION
MUNICH, GERMANY

Order Number: 292016-003
2-138

inter

AB-12

INTRODUCTION
Very often, complex systems involve two or more microcontrollers to fulfill the requirements· defined by a
given objective. Since the nature of microcontrollers
does not allow for easy dual-port memory design (no
"READY" input; no "HOLD/HLDA" interface; portoriented I/O etc.), design engineers are faced with the
problem of interchanging information (data and status)
between those microcontrollers. This application brief
describes the design of a mailbox for exchanging information between two 80C31s, using a 5C060 H-EPLD
as a "back-to-back" register, and a 5C031 H-EPLD as
an arbitration vehicle to control the actions of the
CPUs.

THE SC060 MAILBOX

The 5C060 allows for independent clocking of 8 macrocells on each side of the chip, the two clock inputs are
used to clock. data from the microcontroller bus into
the chip. To read the data written into the mailbox by
one of the controllers, the RDA- (controller A is reading) or RDB- (controller B is reading) line must be
pulled low by activating the read command (lRD). In
order to avoid spurious read-cycles, the /RD commands from both microcontrollers are logically
"ORed" together with an active high CS-signal (Chip
Select) inside the 5C060. The. CS-signal for both ports is
derived from address line A15. Therefore, whenever
AI5 becomes a logic "I" (true), the mailbox is activated and ready to take or submit data.
Address range for the mailbox: FooO Hex to FFFF
Hex
(Upper 12 kbyte)

In this application, the 16 macrocells of the 5C060 are
grouped into two sets of 8 so calleq "ROlF" (register
output with input feedback) primitives to implement
the two 8 bit bus interfaces needed. The grouping is
done according to the following picture.
5C060
WR8

VCC

CSA

RD8
1/080

I/OAO

GROUP A
(MICROCON. TROLLER A)

1/0Al

1/081

I/OA2

1/082

I/OA3

1/083

I/OM

1/084

I/OA5

1/085

I/OA6

1/086

GROUP 8
(MICROCONTROLLER 8)

1/087

I/OA7
RDA

CS8

GND

WRA
292016-15

2-139

AB~12

THE 5C031 "MAILBOX CONTROLLER"
To keep the two microcontrollers informed about the
status of their mailbox, the SC031 is programmed to
supply the following signals to both controllers:

/OBFA: '"OUTPUT BUFFER FULL" FOR Me A
/OBFB: "OUTPUT BUFFER FULL" FOR Me B
/IBEA: "INPUT BUFFER EMPTY" FOR MeA
/IEEB: "INPUT BUFFER EMPTY" 'FOR Me B
/INTA: INTERRUPT TO Me A
/INTB: INTERRUPT TO Me B
The next section will discuss the meanings of these signals in more detail.
Output Buffer Full: This flag is set whenever the controller writes into its own output
buffer. The flag remains valid, until
the second controller has read the
data. The flag is automatically reset to its inactive state when this
read cycle is accomplished.

NOTE:
Both controllers can access (read or write) the mailbox simultaneously.
Input Buffer Empty: This flag indicates that there is no
message _in the mailbox. _The flag
will become inactive as soon as
one microcontroller places a message for the other one (or vice versa).

remains
Example: - /IBEA
"LOW" until microcontroller B
places a message for controller A
into the mailbox for A. /IBEA
will go "HIGH" as soon as controller B has accomplished its
write cycle, and will not go
"LOW" again until microcontroller A has read the message.
Interrupt: The SC031 is programmed to supply interrupts to both microcontrollers involved, on
one -of the following events.
1. The /OBF flag of the opposite microcontroller becomes active; e.g. if controller A is
placing a message for controller B, controller
B. receives an interrupt the same time as
/OBFA becomes valid or vice versa.
2. The /IBE flag of the opposite microcontroller goes active, indicating that this controller has received the message; e;g. if controller B reads the message stored by controller A, its /IBEB flag goes active and controller receives an interrupt indicating that
the buffer is empty.
The signals described above are necessary to accomplish a secure handshake without overwriting messages
accidentally. In addition to that, the SC031 is issuing
the actual. write commands for the two register sets inside the SC060. The /WRA and /WRB signals are results oflogical "AND" functions between the appropriate CS- and /WR _signals from the microcontrollers.
Therefore, spurious write cycles are unlikely to happen.
NOTE:
This design can also be -efficiently implemented in a
single SCBIC EPLD.

2-140

AB-12

A
AOO-A07
PO

...

74HCT373

00-07

AO-A7

1'~
1

~-~~ ~ r.~.
CE OE

ALE
A8-A15
P2

r--

PSEN

027C64

JI !'~
~

A8-12

DECS

CSDE

f.-J~

~L-

OE CE

027C64

ALE
A8-A15
P2

l- PSEN

A
00-07

P80C31BH

74HCT373

ADO-A07
PO

00-07

AO-A7

RAM

P80C31BH

IA
A15

A8-12

iID
RDP3.7
WRP3.6

A8-12

WR CS

CS WR

I II

A15

iID
RD P3.7
WRP3.6

5C060

'-r-

lOA
0-7

lOB A
0-7

ROA
CSA
WA

ROB
CSB
WB

5C031

---RST

P3.4
P3.5
P3.2INTO
RESET

WA
WRA
ROA

WB
WRB
ROB

CSA
OBFA
IBEA
.INTA
RST

CSB
OBFB
IBEB
INTB

I--

r-P3.4
P3.5
INTO P3.2

RESET

292016-1

Block Diagram

2-141

inter

AB·12

5COGO "BACK TO BACK REGISTER"
WB

lOAD

10Al

IOA2

I
1
1

t...
A

---

L -

~r-

t...

L r--

~_I··

IOA3

IOA5

t...

-L rDo-

-I"'-

-r-

l-_

JO.....- ......----H>--IBEB

ROB

OeFA
INTA

RST
INTB
oeFB

ROA

ISEA
CSB
WRB

DE
292016-3

2-143

inter

AB-12

seoso
JUERG
INTEL
March
BOC3l
1

STAHL
ZUERICH
27, 1986
MAILBOX MEMORY USING 5COSO / 5C031

********************
** EXAMPLE .ADF **
********************

5C060
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5COSO
INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813
OUTPUTS: IOB7815, IOA7810, IOBS816, IOAS89,
IOB5817, IOA588, 1084818, IOA487,
IOB3819, IOA386, 1082820, IOA285,
1081821, IOA184, IOB0822, IOA083
NETWORK:'
1087,DB7
ROlF (DA7,WAC,GND',GND,RDBC)
IOA7,DA7
ROlF (D87,W8C,GND,GND,RDAC)
IOB6,DB6
ROlF (DA6,WAC,GND,GND,RDBC)
IOA6,DA6
ROlF (DB6,WBC,GND,GND"RDAC)
IOB5,DB5
ROlF (DA5,WAC,GND,GND,RDBC)
IOA5,DA5
ROlF (DB5,WBC,GND,GND,RDAC)
IOB4,DB4
ROlF (DA4,WAC,GND,GND,RDBC)
IOA4,DA4
ROlF (DB4,WBC,GND,GND,RDAC)
IOB3,DB3
ROlF (DA3,WAC,GND,GND,RDBC)
IOA3,DA3
ROlF (DB3,WBC,GND,GND,RDAC)
IOB2,DB2
ROlF (DA2,WAC,GND,GND,RDBC)
IOA2,DA2
ROlf (DB2, WBC, GND, GND, RDAC)
IOB1,DBl
ROlF (DA1,WAC,GND,GND,RDBC)
IOA1,DAl
ROlF (DB1,WBC,GND,GND,RDAC)
10BO,DBO
ROlF (DAO,WAC,GND,GND,RDBC)
10AO,DAO
ROlF (DBO,WBC,GND,GND,RDAC)
WAC = INP (WA)
RDBC = AND(CSBI,RDBI)
WBC = INP (WB)
RDAC: 'AND(CSAI,RDAI)
CSBI,= INP (CSB)
nRDBI = INP(nRDB)
nRDAI = INP(nRDA)
CSAI
INP(CSA)
RDAI
NOT(nRDAI)
RDBI = NOT(nRDBI)
BND$

292016-4

2-144

inter

AB-12

5e060 REGISTER LEF
JUBRG
INTBL
March
BOC31
1
5C060

STAHL
ZUBRICH
27, 19B6
MAILBOX MBMORY USING 5C060 / 5C031

********************
** EXAMPLB .LBF **
********************

LB Version 3.0, Baseline" 17x, 9/26/B5
LBF Version 1.0 Baseline 1.5i 02 Feb 19B7
PART:
5C060
INPUTS:
WB81, CSA82, CSB814, nRDA8l1, nRDB823, WA813
OUTPUTS:
IOB7815, IOA7810, IOB6816, IOA689, IOB5817, IOA58B, IOB481B, IOA487,
IOB3819, IOA386, IOB2820, IOA285, IOB1821, IOA184, 10B0822, IOA083
NBTWORK:
WBC = INP(WB)
WAC
INP(WA)
CSA! = INP(CSA)
CSBl = INP(CSB)
nRDAI = INP(nRDA)
nHDBI = INP(nRDB)
IOB7, DB7
ROIF(DA7, WAC, GND, GND, RDBC)
IOA7, DA7
ROIF(DB7, WBC, GND, GND, RDAC)
IOB6, DB6
ROIF(DA6, WAC, GND, GND, RDBC)
IOA6, DA6
ROIF(DB6, WBC, GND, GND, RDAC)
IOB5, DB5
ROIF(DA5, WAC, GND, GND, RDBC)
IOA5, DA5
ROIF(DB5, WBC, GND, GND, RDAC)
IOB4, DB4
ROIF(DA4, WAC, GND, GND, RDBC)
IOA4, DA4
ROIF(DB4, WBC, GND, GND, RDAC)
IOB3, DB3
ROIF(DA3, WAC, GND, GND, RDBC)
IOA3, DA3
ROIF(DB3, WBC, GND, GND, RDAC)
IOB2, DB2
ROIF(DA2, WAC, GND, GND, RDBC)
IOA2, DA2
ROIF(DB2, WBC, GND, GND, RDAC)
lOBI, OBI
ROIF(DAl, WAC, GND, GND, RDBC)
IOAl, DAI
ROIF(DBl, WBC, GND, GND, RDAC)
lOBO, DBO
ROIF(DAO, WAC, GND, GND, RDBC)
IOAO, DAO
ROIF(DBO, WBC, GND, GND, RDAC)
BQUATIONS:
RDAC
CSAI
nRDAI';

RDBC"

CSBI

*
* nRDBI';

BND$
292016-5

2-145

AB-12

5C060 REGISTER UTILIZATION REPORT
Logic Opti.izing Compiler Utilization Report
FITVer8ion 1.0 Baseline 1.0i 2/6/87

•••• * Design
JUBRG
INTBL
March
80C31

i.ple.ented successfully

STAHL
ZUERICH
27. 1986
MAILBOX MBMORY USING 5C060 / 5C031

*************************
** EXAMPLE .RPT FILE **
*************************

5C060
LO Version 3.0, Baseline 17K, 9/26/85
5C060
NB
CSA
10AO
rOAl
10AZ

rOA3
IOA4
IOA5
IOA6
IOA7
nRDA
GND

1
2
3
4
5
6
7
8
9
-:10
-: 11
-:12

24:23:2Z:21:20:19:10:17:16:15:14:13:-

Vcc
nRDO
lOBO
lOBI
10BZ
1003
1004
1005
IOB6
IOB7
CSB
NA

"INPUTS*'
Naae

Reaource

MCe11 •

MCells

Feeds:
OB

Clear

INP

Clock
CLKI

CSA

INP

9
10
.11
lZ
13
14
15
16

nRDA

INP

9
10
11
lZ
13
14
15
16

GND

GND,

1
2
3
4

5
6
7
B

9
292016-6

2-146

AB-12

5C060 REGISTER UTILIZATION REPORT (Continued)
10
II
12
13
14
15
16
WA

INP

CSB

INP

CLK2

1
2

4
5

6
7

nRDB

INP

I
2

3
4
5
6
7

8
24

Vee

Nome

Resource

lOAO

lOA!

Vee

nOUTPUTS

**
Feeds:

IOA2
IOA3

IOA4

MCel1 It

PTerms

ROlF

1/ 8

ROlF

1/ B

ROlF

1/ B

MCell.'

ROlF

1/ 8

ROlF

1/ 8

5
6

IOA5

ROlf

1/ 8

IOA6

ROrr

1/ 8

IOA7

ROlF

1/ 8

1087

ROlF

1/ 8

1086

ROlF

1/ 8

IOB5

ROlF

1/ 8

IOB4

ROlF

1/ 8

13,

IOB3

ROlF

1/ 8

IOB2

ROlF

1/ 8

lOBI

ROlF

1/ 8

lOBO

ROlf

Clear

Clock

292016-7

All Resources used
nPART UTILIZATIONU
10011
10011
1211

Pins
MaeroCella
pter••

292016-8

2-147

AB-12

5C031 ARBITER ADF
JUERG
INTBL
March
BOC31

STAHL
ZUERICR
28, 1986 ,
MAILBOX MBMORY'USING 5C060 / 5C031

********************
** EXAMPLB .ADF **
********************

5C031
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C031
INPUTS: RST,nWRA,nRDB,CSA,nRDA,nWRB,CSB,nOB
OUTPUTS: WA,nOBFA,nIBEB,nINTA,nINTB,nOBFB,nIBEA,WB
NETWORK:
nWRA = INP(nWRA)
nRDB = INP(nRDB)
RST = INP(RST)
CSA = INP(CSA)
nRDA = INP(nRDA)
nWRB = INP(nWRB)
CSB
INP(CSB)
nOE
INP(nOB)
WRA
NOT(nWRA)
WRB
NOT(nWRB)
RDA
NOT(nRDA)
RDB
NOT(nRDB)
OJ! = NOT(nOE)
nRST = NOT(RST)
WA = CONF(WAd,VCC)
WAd = AND(CSA,WRA)
WB = CONF(WBd,VCC)
WBd = AND(CSB,WRB)
nRB = NAND(RDB,CSB)
nRA = NAND(RDA,CSA)
nWAd = NOT(WAd)
nWBd = NOT(WBd)
nOBFA,nOBFA
COCF(nOBFAd,OB)
nOBFB,nOBFB = COCF(nOBFBd,OB)
nIBEA,nIBBA = COCF(nIBBAd,OB)
nIBBB,nIBBB = COCF(nIBBBd,OB)
nINTA = CONF(nINTAd,OB)
nINTB = CONF(nINTBd,OB)
nINTAd
AND(nOBFA,nIBBA)
nINTBd
AND(nOBFB,nIBBB)
nOBFBd
NANDCnRA, nIBBA, nRST)
nOB FAd
NAND(nRB,nIBBB,nRST)
nIBBBd
NAND(nWAd,nOBFA)
nIBBAd
NAND(nWBd,nOBFB)
END$

292016-9

2-148

AB-12

5C031 ARBITER LEF
JUBRG
INTEL
March
80C31

STAHL
ZUBRICH
28, 1986
MAILBOX MEMORY USING 5C060 / 5C031

********************
** EXAMPLE .LEF **
********************

5C031
LB Version 3.0, Baseline 17x, 9/26/85
LEF Version 1.0 Baseline 1.5i 02 Feb 1987
PART:
5C031
INPUTS:
RST, nWRA, nRDB, CSA, nRDA, nWRB, CSB, nOE
OUTPUTS:
WA, nOBFA, nIBBB, nINTA, nINTB, nOBFB, nIBEA, WB
NETWORK:
RST = INP(HST)
nWRA = INP(nWRA)
nRDB = INP(nRDB)
CSA = INP(CSA)
nHDA = INP(nRDA)
nWHB = INP(nWRB)
CSB = INP(CSB)
nOR = INP(nOE)
WA = CONF(WAd, VCC)
nOBFA, nOBFA = COCF(nOBFAd, OR)
nIBBB, nIBBB = COCF(nIBBBd, OB)
nINTA = CONF(nINTAd, OB)
nINTB = CONF(nINTBd, OB)
nOBFB, nOBFB = COCF(nOBFBd, OR)
nIBBA, nIBBA = COCF(nIBBAd, OE)
WB = CONF(WBd, VCC)
BQUATIONS:
WBd = CSB * nWRB';
CSB

nIBRAd

* nWRB'
j

+ nOBFB J

nOBFBd
+

nINTBd

(nIBEA
nIBBA
nOBFB

nINTAd

nOBFA

nIBBBd

CSA

* RST' * CSA'
* RST' * nRDA)' ;
* nIBBB;
* nIBBA;

* nWHA'

+ nOBFA' ;

= nOB' ;
nOB FAd = (nIBBB * HST' * CSB'
+ nIBBB
RST'
nRDB)' ;
OB

WAd = CSA

*
* nWRA' ;

END$
292016-10

2-149

AB-12

5C031 ARBITER LEF (Continued)
Logic Optimizing Compiler Utilization Report

FIT Version 1.0 Baseline 1.0i 2/6/B7

*****

Design implemented successfully

JUI!RG STAHL
. INTEL ZUI!RICH
March 28, 1986
BOC31 ~AILBOX MEMORY USING 5C060 / 5C031

*************************
**
EXAMPLE .RPT FILE **
*************************

5C031
LB Version 3.0; Bsseline 17x, 9/26/85
5C031
GND - 1·
GND - 2
nOB
3
CSB - 4
nWRB - 5
nRDA - 6
CSA
7
nRDB
8
nWRA -: 9
GND -: 10

20:19:18:17:16:15:14:13:12:-

Vee
WB
WA
nOBFB
nINTB
niNTA
nIBEB
nOBFA
nIBBA
I I :- RST

UINPUTSU
Name

Resource

nOB

INP

MCell ,

PTeras

MCella

Feeds:
OE

Clear Preaet

3
4

5
6

7
B
CSB

INP

1
7

8
nltRB

INP

1
8

nRDA

INP

CSA

INP

2
3
6

nRDB

INP

nltRA

INP

2
6

GND

RST

INP

Vee

3
7

1
2
292016-11

2-150

inter

AB-12

5C031 ARBITER UTILIZATION REPORT
UOUTPUTSU

PTeras

MCells

COCF

2/ 8

3
5

COCF

2/ 8

Name

Resource

nIBBA

nOBFA

MCell

Feeds:
OE

Clear Preset

5
6

nIBEB

COCF

2/ 8

nINTA

CONF

1/ 8

nINTB

CONF

1/ 8

nOBFS

COCF

2/ 8

1/ 8

CONF

liB

CONF

4
7

4
8

1/ 8

**UNUSBD RBSOURCBS**
Naae

Resource

MCell

PTeras

1
2

UPART UTILIZATION**
88'
100'
18'

Pins
MecroCells
Pteras
292016-12

2-151

inter

AB-16

APPLICATION
BRIEF

October 1988

Atypical Latch/Register
Construction in EPLDs

THOM BOWNS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292031-003
2-152

inter

AB-16

in this Ap brief, the "!" operator is used to signify inversion). The schematic of the RS latch is shown in
Figure.la.

ATYPICAL LATCH/REGISTER
CONSTRUCTION IN EPLDs
Though Intel's EPLDs include many of the typical
latch and register types, some logic designs require register or latch configurations not directly supported in
the current EPLDs. In many cases these register and
latch configurations can be generated using the logic
array and combinational feedback. A "latch" is defined
as a level-triggered, flow-through type such as the
74373, and a "register" is defined as an edge-triggered
flip-flop such as the 7474.

Since cross coupled logic is not supported in EPLDs,
we must convert the equation to a single term with
feedback.
aD, OF = COCF (a, VCC)

Q = S

!R * OF;

This circuit can be implemented in an EPLD macrocell. Where combinational feedback is not supported,
1/0 feedback will suffice. The schematic of this implementation is shown in Figure lb.

This application brief will detail the construction of a
D-type latch, an RS latch and a D flip-flop using combinational logic and feedback. Also discussed is the
construction of an RS flip-flop, a JK flip-flop and a T
flip-flop using registered logic and feedback.

With the RS latch, the inputs are normally low. A logical one on S sets Q to I, and a one on R resets Q to a O.
Logical ones on both inputs simultaneously cause the
output to remain at a high level since S takes precedence over R in this implementation.

The RS latch is the simplest latch configuration. The
equations for it are as follows: QB = !(Q + S), Q =
!(QB + R) where Q is the output of one NOR gate, and
QB is the output of the other (Note: as a convention

where QF is the feedback from Q output.

NOR2

292031-1

(a)

Vce
INP

----.

COCF'

INP

•

292031-2

(b)
Figure 1. RS Latch Implementation In a) Discrete Gates and b) EPLD Logic

2-153

infef

AB-16

QD, QF

Another latch is the 74373 type, or D latch. This latch
works by either enabling input data to appear at the
output, or by holding the output to the last input data
state. Its equation is this: QB = !(!(!D*E)*Q), Q =
!(!(D*E)*QB). Again, Q is the output of one NAND
gate, and QB is the output of the other. Figure 2a
shows this version of the design.

= COCF (Q,VCC)

Q = D • E

!E • QF;

QF is the feedback from the COCF. In this circuit,
when E is high, data flows through transparently.
When E is brought low, data is latched. When using
input feedback, care must be taken when tri-stating the
output as data will no longer be latched. The EPLD
implementation is given in Figure 2b.

Again, we must convert to an EPLD-type equation and
schematic:

0-1-+--1

E-~--I

NAN02

292031.,.3

(a)
01- 0 - - - - 1 .

----.
COCFI

E:-D'"-'
I'T'

~~~'-QO

292031-4

(b)

Figure 2. Implementation of a D Type Latch Using a) Discrete Gates and b) EPLD Logic

2-154

AB-16

This latch can be cascaded with a second latch to produce an edge triggered, master/slave D flip-flop, using
combinational logic. The flip-flop is a solution to using
asynchronous clocking, preset and clear functions when
they aren't supported. Also, if an I/O conflict exists
within a macrocell group when using registered logic,
this design will fit since it uses combinational logic.
Figure 3. shows the schematic for this design.
This design does consume two macro cells, but in many
cases, that isn't a problem.

The boolean equation of the D flip-flop is this:
QD,QF = COCF (Q,VCC)
YF = NOCF (Y)
Y = D • !CLOCK
Q

YF • CLOCK;

= YF • CLOCK + QF • !CLOCK;

Q is the flip-flop output and Y is the first latch output.
Data is latched in to the second latch on the low-going
edge of clock, and is clocked out to Q on the high-going
edge of clock.

INP

o-D---I

INP

CLOCK

-C>--+--I

----.

cocn
>-C>r'-oo
OF
292031-5

Figure 3. Combinational Logic implementation of a

2-155

o Flip-Flop

intJ

AB·16

Preset and clear can be added into the equations as
well:
QD,QF = COCF (Q,vcC)
YF = NOCF (Y)
Y = D' !CLOCK

+ YF • CLOcK;

Q = YF • CLOCK • I (CLEAR TERM) +
(PRESET TERM) +
QF • !CLOCK • ! (CLEAR TERM);

When the PRESET TERM is logically true, Q is asynchronously set to 1.

When the CLEAR TERM is logically true, Q is asyn.
chronously cleared to O.
The PRESET TERM takes priority over the' CLEAR
TERM.
This schematic is shown in Figure 4.
Due to the nature of the design, input delays plus array .
delays plus feedback delays must be added and used to
determine a maximum operating frequency. In this example, tIN + tAD + tCF + tAD = 113 ns for a
-6S SC121, leaving a maximum frequency of 8.8
MHz.

INP

-0_-------1.
INP

CLOCK--{:>------~--_r.

----"
cocr.

~~~ ~~~'--QD
INP
CLEAR TERM

-C>-of

~>O""'-~I--IA

INP

. PRESET TERM

--C>------....J

292031-6

Figure 4. 0 Flip-Flop with Added Preset and Clear Terms

2-156

intJ

AB-16

Other useful workarounds involve D registers and logic
in constructing RS, JK and T flip-flops, for use in
EPLDs not supporting these configurations. The RS
flip-flop is simply the RS latch discussed earlier coupled to registered feedback.

The JK flip-flop is another useful and easily implemented register:

OD,OF = RORF (O,CLOCK,GND,GND,VCC)

When J = K = 1, QD toggles to opposite state on next
clock trigger. When J = K = 0, QD remains the same.
When J does not equal K, QD 'will follow J on next
clock trigger. The schematic is shown in Figure 6.

0= S

OF· !R;

Normally, Sand R will remain low. When S is brought
high, QD will become 1 on the next clock trigger edge.
When R is brought high, QD will become 0 on the next
clock trigger edge. The schematic is given in Figure 5.

OD,OF = RORF (O,CLOCK,GND,GND,VCC)

= J • !OF

INP

CLOCK--£:)----------------------,
INP

s--~~----------~
INP

GNO

!K • OF

Vee

----.
RORF'
>-C>r'--OO

R--lD-f

292031-7

Figure 5. EPLD Implementation of an RS Flip-Flop

INP

CLOCK--£:)----------------------,
INP

----.
RORF'
>-C>r'-oo
INP

K--lD--I
292031-8

Figure 6. EPLD Implementation of a JK Flip-Flop

2-157

AB-16

The T

flip~flop

is also easily constructed:

OD,OF = RORF (O,CLOCK,GND,GND,VCC)
Q = T • ! OF

! T • OF;

When T is high, QD will toggle to opposite state on
next trigger. When T is low, QD will remain the same.
Figure 7 shows the T flip-flop design schematic.
Each of these designs uses a minimum number of pterms; adding p-terms is possible to the limit of the
macrocell being used. It is possible to substitute an entire logical expression for each input listed (except

INP
CLOCK-C>----__.
INP

For example, consider using the J-K register. Setting
J = A • B • C + D and setting K = E • !F • !G +
H + I then the minimized p-term count will expand
from two p-terms to five p-terms, which would still be
okay within a macrocell with more than five p-terms.
Using logic gates and combinational or registered feedback, one can easily implement many types of latches
and registers. Regardless of the EPLD type, there exists
the resources to implement any of the discussed circuitry.

GND

T-ID--\

Vce

----.
RORF'·
>-C>r'-QD

292031-9

Figure 7. Implementation of a T Flip-Flop

2-158

inter

AB-22

APPLICATION
BRIEF

October 1988

5C032-25 vs. 16V8-25:
A Device Comparison

DANIEL E. SMITH
LlLIYAS KOUMIS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order N!Jmber: 292051-001
2-159

. AB-22

INTRODUCTION

ARCHITECTURE

This application brief compares the Intel 5C032-25
EPLD with the Lattice 16V8-25 GAL', showing how
the 5C032 is superior to the 16V8 for low-power CMOS
PLD applications. The compatibility between the two
devices is high enough that the 5C032-25 can be
dropped directly into the 16V8-25 socket for the majority of applications. Areas where the 5C032 is not compatible are also noted. Information in the brief is based
on the Intel 5C032 Data Sheet (order number: 290155002 or later) and the Lattice 16V8 Data Sheet (undated).

Architecturally, the 5C032 is a superset of the 16V8.
Any architectural configuration supported by the 16V8
can be implemented in the 5C032. There are a number
of configurations, however, supported by the 5C032
that cannot be implemented in the 16V8 architecture.
As shown in Figure I, both the 5C032 and 16V8 are 20pin devices with 8 I/O macrocells. The two devices are
pin compatible. All inputs and I/Os are on the same
pins. Macrocells in the devices support registered and
combinatorial modes. (Refer to the discussions on "Inputs" and "Macrocells" later in this brief.)

The comparison is divided into the following areas:
• Technology
• Architecture
• Specifications
• Development Support

TECHNOLOGY
The 5C032 is produced on Intel's CHMOS EPROM
process and is, therefore, UV erasable. The 16V8 is produced on a CMOS EEPROM process and is electrically
erasable. Because neither device will typically be erased
and reprogrammed in-circuit, this difference is negligible. The fuse patterns for the two devices are different.
Therefore, the JEDEC files are not compatible:

The major architectural difference between the 16V8
and the 5C032 lies in flexibility. During programming,
the 16V8 uses 10 bits to internally configure all 8 macrocells. 1 bit (SYN) is a global "register/combinatorial"
mode bit. A second bit (AO) is also a global bit that
controls an OE mux. These two bits provide global selection of modes but limit the independent control of
macrocells. Each macrocell has an individual configuration bit (ACn) to give macrocells some independent
control. In contrast, the 5C032 provides 2 bits per macrocell to independently configure each macrocell (16
bits total). This gives the 5C032 greater flexibility than
the 16V8. Another difference concerns the state of macrocell registers on power-up. 5C032 registers are low on
power-up, while the 16V8 registers are high. This difference may be important in some applications.

5C032
INPUT/CLK
INPUT

16V8
IOICK

VCC

I/O

INPUT

I/O

INPUT

I/o

INPUT

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/o

GND

18
GND

I/VPP

FO
I/OE
292051-2

292051-1

Figure 1. 5C032 and 16V8 Pinouts

'GAL is a registered trademark of Lattice Semiconductor Corporation.

2-160

inter

AB-22

Inputs

I/O Configurations

The 5C032 has 9 dedicated inputs and one CLK/INP
pin. The 16V8 has 8 dedicated inputs, one global CLK/
INP pin, and one global OE/INP pin. The CLK inputs
are both on pin 1. The global OE on the 16V8 (pin 11)
corresponds to an input on the 5C032. This pin can be
used on the 5C032 as a global OE. On the 5C032, however, any input can function as the global OE. The
16V8 does not provide this flexibility.

Table I shows the configurations supported for both
devices. Note that most 16V8 macrocell configurations
have some restriction on use.

On both devices, the CLK pin can function as an input
to the logic array when implementing combinatorial
logic only (no registers). Pin 11 (OE/INP on the 16V8)
can also be used as a dedicated input in combinatorial
mode. Pin lion the 5C032 can be used as an input in
both registered and combinatorial mode.

Macrocells
Each 16V8 macrocell is fed by 8 p-terms. One of the
eight p-terms can be used to control the OE signal for
combinatorial macrocells. When this is done, only 7 pterms remain as inputs to the macrocell. Depending on
tp.e configuration, the OE can also be tied to vce or
GND, or can be globally driven by pin II.
5C032 macrocells are fed by 8 p-terms. A ninth p-term
is provided for independent OE control. Thus the
5C032 macrocell can implement equations with more
p-terms than the 16V8. All options are available independently for all macrocells, which makes the device
more flexible than the 16V8.
The 16V8 is placed in registered or combinatorial mode
by a global architecture bit. Registered mode means piri
I is global CLOCK and pin II is global OE. Registered
macrocells cannot use product terms to independently
enable outputs; only the global OEean be used. Macro"
cells can be configured as combinatorial outputs when
the device is in registered mode, bilt only 7 p-l'erms are
available as macrocell inputs. Buried registers can be
emulated on a global basis by disabling the global OE
and using the feedbacks only, but buried registers cannot be mixed with output registers in the,same design.
In the SC032, registers are selected on a macroceli-bymacrocell basis.· Any supported configuration can be
implemented on any other macrocell. Independent OE
p-terms are available with registers (see Figure 2). A
global OE can be implemented by programming all OE
p-terms the same. Buried registers can also be selected
on a macrocell basis. These differences make the 5C032
much more flexible than the 16V8.

2-161

Table 1. 5C032116V8 Configurations
5C032
Input
Input on unused
Macrocell
Comb. Out
(no feedback)
Comb. Out
(input feedback)

16V8 (Comb.)

16V8 (Reg.)

Input
Input on unused
Macrocell
Comb. Out
(no feedbackOE = VCC)
Comb. Out
(input feedback'7 p-terms)

Input
Input on unused
Macrocell
Comb. Out
(no feedback7 p-terms)
Comb. Out
(input feedback7 p-terms)
Register (with
feedback-global
OEonly)
Register (no
feedback-global
OEonly)

Register (with
nla
feedback-p-term
controlled OE)
Register (no
nla
feedback-p-term
controlled OE)
Buried Register
nla
(any register)
p-terms = Product terms
nla = not available

Buried Register
(global only)

Table 2 summarizes the architecture comparison:

Table 2. 5C032/16V8 Architecture Comparison
Device Feature
of Pins

5C032
20

16V8
20

Dedicated Inputs
Total Inputs
Macrocells
Synch. Clocks
Logic P-terms/Macrocell

8/9

16
8
1
8

16
8
1

8/7(1)

0/1(2)
OE P-Terms/Macrocell
1
1 (3)
GlobalOE
1
Device Erase
UV
Electrical
Register Output State
high
low
On Power-Up
1. When uSing a p-term to drive the OE signal for a macrocell, the 16V8 can only use 7 p-terms as macro cell inputs.
2. 16V8 registers must use the global OE signal. Macrocells programmed for combinatorial mode can use a pterm. In contrast, the 5C032 provides a p-term for all macrocells in all configurations.
3. Global OE is implemented on 5C032 by driving all OE pterms by pin 11.

intJ

AB-22

5C032 Registered Macrocell
GLOBAL

ClK
REGISTERED
OUTPUT

. FBK

292051-3

16V8 Registered Maci'ocell
(Device in Registered Mode)
GLOBAL

GLOBAL
OE

ClK

REGISTERED
OUTPUT,

FBK

292051-4.

Figure 2. 5C032 and 16V8 Registers

The following tabl~ describe differences between the
5C032 and the half-power 16V8in three different tables: (I) Absolute Maximum Ratings, (2) D.C. Characteristics, and (3) A.C. Characteristics.

s~dby power than the half-pow~ 16V8. For low power applications where the output drive cllrrent requirements are 4mA or less, the Intel 5C032 is an ideal replacement for the 16V8. The 16V8; with outputs capa~
ble of sinking up to .16mA, is better suited to applica.
tions that require higher current sink~

D.C. Characteristic Differences .

A.C. Characteristics Differences

The Intel 5C032-25 meets or excei:ds all but two 16V8
D.C. specifications (short circuit current and Iod. Due
to the advanced CMOS technology, the Intel 5C032
·consumes one-third the power of the half~power 16V8.
It also consumes almost three orders of magnitude less

The Inte15C032-25 meetS all but one 16V8 A.C. specification (Output Enable/Disable). Thus ·the Intel
5C032 is an ideal replacement for the 16V8 in most
applications.

SPECIFICATIONS

2-162

AB-22

Absolute Maximum Rating Differences
5C032-25

Parameter

16V8-25

Units

Symbol·

Min

Max

Symbol

Min

Max

Vcc

-2.0

7.0

Vcc

-0.5

7.0

Storage Temp.

Tstg

-65

+150

Tstg

-65

+125

Ambient Temp.

Tamb

-10

+85

+75

Supply Voltage

D.C. Characteristics(1)
5C032-25

Parameter
Symbol
Supply Current

Icc

Short Circuit Current

Isc

Min

16V8-25

Max

Symbol

Min

Units
Max

Icc

-10

los

-130

ISB

. 0.1

ISB

Output Low Voltage

VOL

0.45
10L =4

VOL·

0.5
10L =16

V
rnA

Output High Voltage

VOH

2.4
10H= -4

Input High Voltage

VIH

2.0

Standby Current

Vcc+ 0.3

VOH

2.4
10H= -3.2

VIH

2.0

V
rnA
Vcc+ 1

1. All D.C. Characteristics are compared to the Half-Power GAL 16V8. A Comparison to the FUll-Power GAL 16V8 would
show that power consumption is twice that of the Half-Power GAL 16V8.

2-163

inter

AB-22

. A C Characteristics
Symbol

Input to Active Out

16V8-25

5C032-25

Parameter

Min

Max

Symbol

Min

Units
Max

tpD

tDVQV1

P-term Enable to Out Enable

tpzx

tDVQV2

P-term Disable to Out Disable

tpxz

tDVQZ2

OE-pin Enable to Out Enable

tpzx

tGHQZ2

OE-pin Disable to Out Disable

tGHQV

tCHQV

tpxz

Clock High to Output Valid

tco

Input Setup Time

tsu

tDVCH

Input Hold Time

tCHDX

Clock Low

tCl

tCHCl

Clock High

tCH

tClCH

tCNT

(1)

20
...

(2)
Max Count Frequency
33.3
33.3
MHz
fCNT
..
1. lattice does not specify thiS parameter. Intel specifies thiS parameter. strictly tor calculation of tCNT. fCNT IS the count
frequency associated with designs that use feedback Signals, e.g., counters.
2. lattice does not specify an equivalent. However, this value can be determined using either "register output feedback to
register input" delay, or the "clock period", whichever, is the larger. Since "register output feedback to register input" delay
is unknown, the indicated frequency value assumes the clock period (tCHCl + .tClCH = 30 ns) is the larger Of the two
parameters.
'

DEVELOPMENT SUPPORT

SUMMARY

Both the 5C032 and the 16V8 are supported by ABEL
and can be programmed on the Data I/O LOGICPAK
and UNISITE programmers. The 5C032 is also supported by iPLDS II (Intel Programmable Logic Development System) using the PCCP PC-based programmer and by iPLS II (Intel Programmable Logic Software) using either the PC-based programmer or the
iUP-200A/201A Programmer. The 16V8 is also supported on the Data I/O Model 60 programmer.

The 5C032-25 provides a low-power upgrade to the
16V8-25 for most applications. If your application requires higher density devices, or fast programmable devices for specific applications, contact your local Intel
sales office.

2-164

intJ

AP-271

APPLICATION
NOTE

April 1986

Applying The 5C121 Architecture

JIM DONNELL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292008-001
2-165

inter

AP-271

INTRODUCTION
Intel's 5C12l Erasable Programmable Logic Device
represents a new breed in the world of programmable
logic. With gate densities approaching those of gate arrays and a reconfigurable architecture, the logic designer is freed from choosing between scores of generic programmable logic to perhaps find an acceptable match
for his or her design needs. Adding to the list of benefits
is the fact that the 5Cl2l is erasable. Now sections of
the design can actually be programmed and tested in
the device - without sacrificing a part to the circular
file. In addition, there is no longer a need to generate
test vectors to qualify the programming of the parts.
EPLDs are erasable and therefore 100% testable at the
factory.

OBJECTIVE
The purpose of this application note is to demonstrate
the architectural options of the 5C 121 by designing a ,
digital crosspoint switch. Conceptually, a digital crosspoint switch switches data from any input to any output. Figure 1 shows a block diagram of a bytewide
crosspoint switch.
0

10-17
DIGITAL
CROSSPOINT
SWITCH

INPUT SELECT 01

-:-t""T"t....l

:02 --+L......:-

COMBINATIONAL FEEDBACK
Feedback in logic designs is used for a variety of reasons. Combinational feedback in the 5C121 is often
used to reduce the number of product terms feeding one
Macrocell. Though the 5C121 has Macrocells that can
accept up to 16 product terms, all Macrocells are not
that wide.
Let's look at an example. Equation 1 represents one of
the eight Boolean expressions necessary to implement a
digital crosspoint switch. Logically, this expression selects one of eight input signals (10-17), and routes that
signal to QO. Data bits DO, 01, and 02 select one of the
eight input lines. In this case, data bits !D3, !D4, and
!D5 select output QO. (The exclamation point is used to
indicate a logical complement of the signal.) Equations
for Q 1 through Q7 are very similar and will be discussed later.
0

00 = ( 10
+ 11
+ 12
+ 13
+ 14
+ 15
+ 16
+ 17

00-07

00--+
--+

include registered or combinational output. In addition,
each output may be fed back into the array in both the
true and complement version. For a more complete description of the 5CI21 architecture the reader is referred to the 5C 121 data sheet.

03 04 05
OUTPUT SELECT
292008-1

Figure 1. Functional Diagram of a Digital
Crosspoint Switch

This design will employ features such as: registered output with registered feedback, combinational feedback,
input latches, buried registers, and dual clock options.
The digital crosspoint switch in this design can route
data from one of eight inputs to one of eight outputs in
a single clock cycle. Options for holding the deselected
outputs at previous levels, latching inputs, and fitting
considerations are explored.

THE BASIC ARCHITECTURE
The 5CI21 contains 28 Macrocells, 12 dedicated inputs, 24 programmable I/O lines, and two clocks input
pins. Inputs may be flow through, or latched on the
rising or falling edge of either clock. Output options

x !D2 x
x tD2 x
X !D2 X
X !D2 X
X D2 x
x D2 X
x D2 X
X D2 X

tD1
tD1
D1
D1
tD1
!D1
D1
D1

x tDO
X DO
X !DO
X DO
X !DO
X DO
X !DO
x DO) x !D5 X !D4 x !D3; (1)

SELECTEO = 10 x
+ 11 X
+ 12 X
+ 13 x
+ 14 x
+ 15x
+ 16 x
+ 17 X

!D2
!D2
!D2
!D2
D2
D2
D2
D2

x
x
x
x
x
X
x
X

!D1
!D1
D1
D1
!D1
!D1
D1
D1

X
x
X
x
x
X
x
X

!DO
DO
!DO
DO
!DO
DO
!DO
DO;

(2)

Equation 2 contains the terms that will be common to
all eight output equations. Both equations in this case
contain eight product terms. By treating equation 2 as
one common signal and routing that signal through
combinational feedback, we can reduce the number of
product terms in equations QO thru Q7 to one p-term
each. The advantage is that the outputs can now be
placed in any of the 24 I/O Macrocells available in the
5Cl2!. In addition, the 5CI21 contains four buried registers. (Buried registers have no output and are used
.solely for feedback.) If a buried register is 'available,
iPLDs (Intel's Programmable Logic Development System) will automatically assign the No Output - Combinational Feedback function to a buried register. This
increases the flexibility for pin assignments and makes

2-166

inter

AP-271

COMBINATIONAL FEEDBACK
(Continued)

p-terms available in case a design change is needed.
Equations 3 thru 10 reflect this improvement.

01 = SELECTEQ X 105 X 104 X 03
X 03) X Q1-fdbk;

1(105 X 104
(12)

Q2 = SELECTEQ X !05 X 04 X 103
X 103) X 02-fdbk;

1(!05 X 04
(13)

Q3 = SELECTEQ X 105 X 04 X 03
X 03) X Q3-fdbk;

+ 1(!05 X 04

Q4 = SELECTEQ X 05 X !04 X 03
x 103) X Q4-fdbk;

!(05 X 104
(15)

Q5 = SELECTEQ X 05 x 104 X 03
x 03) x 05-fdbk;

1(05 x 104
(16)

= SELECTEO X 105 X 104 X 103;

(3)

= SELECTEO X 105 X 104 X 03;

(4)

= SELECTEO X 105 X 04 X 103;

(5)

= SELECTEO X 105 X 04 X 03;

(6)

= SELECTEQ X 05 X 104 X 103;

(7)

= SELECTEQ X 05 X 104 X 03;

(8)

Q6 = SELECTEO x 05 X 04 X 103
x !03) x Q6-fdbk;

1(05 X 04
(17)

= SELECTEQ X 05 X 04 X 103;

(9)

= SELECTEO X 05 X OR X 03

1(05 X 04
(18)

= SELECTEQ X 05 X 04 X 03;

(10)

X OE) X Q7-fdbk;

REGISTERED FEEDBACK
Registered feedback is also employed in a variety of
applications such as counters and state machines. In
this particular example, the registered feedback signal
can be used to hold the deselected outputs of the switch
at their previous level until that output is selected
again. This is accomplished by simply "ANDing" the
feedback signal with the inversion of the output select
signal. The result is then "ORed" with the equation for
the given output. Holding the previous output might be
useful in control applications or when interfacing to
slow peripherals. Equations II thru 18 are the result.
00 = SELECTEQ X 105 X 104 X 103
X 103) X QO-fdbk;

1(05 X 104
(11)

(14)

Equations II thru 18 are all that are necessary to implement a digital crosspoint switch with the output
hold feature. Each equation contains only four product
terms when written in the expanded form and could
therefore fit into any Macrocell in the SCI2!. The appendix contains the report and ADF files generated by
the iPLDs software.

TIMING ANALYSIS
Figure 2 shows the internal deiay paths associated with
this design in the SCI2!. The frequency at which the
SCI21 may be clocked can be determined by examining
the internal delay elements of the SCI2!. These include
the input delay (Tin), two array delays (Tad), and the
combinational feedback delay (Tcl). Table I gives the
simulation data for each of these paths in a SC121-S0.

-~----Tad-----

ARRAY

Tad

'I-Trd-!-Tod_1

ARRAY

REG OUTPUT

1-o1.-------Trf--------.1
Figure 2. Crosspoint Delay Path

2-167

292008-2

AP·271

bits could be switched per cycle. Figure 3 shows the
timing diagram for this configuration of the 5C121 digital crosspoint switch. Included in the appendix is the
Advanced Design File (ADF), Logic Equation File
(LEF), and Utilization report generated by Intel's Programmable Logic Software (iPLS) for this design.

TIMING ANALYSIS (Continued)
Table 1. 5C121·50 Simulation Data
Model
Parameter

Delay (ns)

Tad

Trd

INPUT LATCHES

Tod

Tin

Tie

Trf

Tel'

One point must be raised about Figure 3. Notice that
the time allowed for external data set-up is only 17 ns.
Therefore, 17 ns after the rising edge of the clock, data
must be stable and remain stable at the input pins until
the next clock pulse. In most systems this would be a
very stringent requirement. Fortunately the 5C 121 has
the ability to latch the data at the input pins with 7475
type transparent latches. Employing this feature eases
the data set-up requirement as shown in Figure 4.

The sum of the delays before the register input equal
the set-up time Tsu with reference to the internal clock.
By substracting the .input clock delay Tic we shift the
reference to the external clock pin. The set-up time
with reference to external signals is shown in equation
19. Inverting this signal yields the maximum clock frequency, fmax. The maximum clock frequency is shown
in equation 20.
Tsu = tin
fmax

2Tad

+ Tcf

(19)

- Tic;

1 Tsu

(20)

Therefore, this configuration of the 5C121-50 could be
clocked at 10 MHz, allowing a data transfer rate ono
Mbits/second. By paralleling six 5C121s together, eight

The flexible architecture of the 5C 121 gives the designer a variety of.options for input and output configurations. Inputs maybe latched to ease system timing requirements. Outputs. may be clocked for synchronous
systems or fed directly out as asynchronous· signals.
Feedback can be used to reduce product term requirements, to save present state information for state machines and counters, or simply to hold deselected outputs as shown in this example. Imagine the possibilities,

J. R. Donnell
PLDO Applications

lOOns

I'
elK

SUMMARY

Tsu (83NS)
INPUT STABLE

17ns .1
)I(

DATAOUT::::::::::::::::::::::::::::::Jt:~::~:jC:::~D~A~TA~O~U~T~V!A~LI~D::::::
+-Teol
(Teol = Tic + Trd + Tod)
292008-3

Figure 3. CrosspOint Timing Diagram

2-168

AP-271

ClK

----I'

lOOns

.11----- Tsu (83NS) - - - - - 1
lATCHED INPUTS

lATCH ENABLE

DATA TO PINS

DATA OUT

17n$.1

__
_____
)I( _ _ _ _INPUT
SlABlE

---------1'1
)I( _ _ _ _ _ _ _ _ _- - J

'I~_J"

_ _ _ _ _ _ _ _ _ _-JI~

~--------~

EXTERNAL DATA SET-UP

DATA STABLE

X'--___________

---------------l"o,:J,....--D-A-T-A-O-U-T-V-A-U-D--(Teol= Tic + Trd + Tod)

292008-4

Figure 4. Crosspoint Timing Diagram with Input Latches

2-169

APPENDIX
ADF File

o
5C121
Digital Crosspoint Switch
LB. Version 3.0, Baseline 17K, 9/26/85
PART: 5C121
INPUTS: 100837,101836,102835,103~34,10488,10589,106810,107811,110833,111832
;~12831(113@30,114@29,115@28iI16827,117826,CLK@38,DO@2,Dl@3,D2@4,D3@5

,D4@6,D5@7,ILE@1
OUTPUTS: QOO@12,QOl@13,Q02@14,Q03@15,Q04@16,Q05@17,Q06818,Q07@19,QI0@24,Qll@23
,Q12@22,Q13@21
NETWORK:
QOO,QOOFBK
RORF (QOOD,CLK,GND,GND,YCC) % BIT 0 OUTPUTS %
QOl,QOlFBK.
RORF (QOID,CLK,GND,GND,VCC)
Q02,Q02FBK,
RORf (Q02D,CLK,GND,GND;VCC)
RORF (Q03D,CLK,~ND,GND,yCC)
Q03,Q03FBK
Q04,Q04FBK
RORF (Q04D;CLK,GND,~ND,YCC)
QO&,Q05FBK
RORF (Q05D,CLK,GND,GND,YCC)
Q06,Q06FBK
RORF (Q06D,CLK,GND,GND,YCC)
Q07,Q07FBK
RORF (Q07D,CLK,GND,GND,YCC)
QI0,QI0FBK
RORF (QI0D, C,LK, GND, GND, YCC) % 4 OF THE B, BIT 0 OUTPUTS%
Ql1,QllFBK
RORF (QI1D,CLK,GND,GND,YCC)
Q12,Q12FBK
RORF (Q12D,CLK,GND,GND,YCC)
Q13,Q13FBK
RORF (QI3D,CLK,GND,GND,YCC)
eLK = INP (CLK)
D5 = LINP (D5,ILE) % OUTPUT SELECT CONTROL BITS %
ILE = INP (ILE)
D4
LINP (D4,ILE)
D3
LINP (D3,ILE)
D2 = LINP (D2,ILE) % INPUT SELECT CONTROL BITS %
Dl = LINP (Dl,ILE)
DO = LINP (DO,ILE)
100
LINP (IOO,ILE)
101
LINP (IOl,ILE)
102
LINP (102,ILE)
103
LINP (I03,ILE)
104
LINP (104,ILE)
105
LINP (105,ILE)
106
LINP (106,ILE)
107
LINP (107,ILE)
110
LINP (II0,ILE) % INPUTS FOR BIT 1 SWITCH %
III
LINP (ll1,ILE)
112
LINP (112,ILE)
113
LINP (I13,ILE)
114
LINP (114,ILE)
115
LINP (115,ILE)
116
LINP (116,ILE)
117
LINP (117,ILE)
SELECTEQOF = NOCF (SELECTEQO)
SELECTEQIF = NOCF (SELECTEQl)
EQUATIONS:
QOOD
SELECTEQOF*!D5*!D4*!D3
+ !(!D5*!D4*!D3)*QOOFBK;
QOID
SELECTEQOF*!D5*!D4* D3
+ !(!D5*!D4* D3)*QOIFBK;
Q02D
SELECTEQOF*!D5* D4*!D3
+ !(!D5* D4*!D3)*Q02FBK;
Q03D
SELECTEQOF*!D5* D4* D3
+ !(!D5* D4* D3)*Q03FBK;
Q04D
SELECTEQOF* D5*!D4*!D3
+ !( D5*!D4*!D3)*Q04FBK;
Q05D
SELECTEQOF* D5*!D4* D3
292008-5

2-170

inter

AP-271

ADF File (Continued)
+ !( D5*!D4* D3)*Q05FBK;
SELECTEQOF* D5* D4*!D3
'
+ !( D5* D4*!D3)*QOSFBK;
Q07D
SELECTEQOF* D5* D4* D3
+ !( D5* D4* D3)*Q07FBK;
SELECTEQ1F*!D5*!D4*!D3
Q10D
+ !(!D5*!D4*!D3)*Q10FBK;
011D
SELECTEOIF*!D5*!D4* D3
+ !(!D5*!D4* D3)*01IFBK;
012D
SELECTE01F*!D5* D4*!D3
+ !(!D5* D4*!D3)*012FBK;
013D
SELECTEOIF*!D5* D4* D3
+ !(!D5* D4* D3)*Q13FBK;
SELECTEOO = 100*!D2*!D1*!DO
~ COMMON EOUATION FOR BIT 0
+ 101*!D2*!Dl*DO
+ 102*!D2*D1*!DO
+ 103*! D2*D UDO
+ 104*D2*!Dl*!DO
+ I05*D2*! DUDO
+ IOS*D2*DU! DO
+ 101*D2*D1*DO;
IIO*!D2*!Dl*!DO
~ COMMON EQUATION FOR BIT 1
SELECTEQI
+ 111*!D2*!Dl*DO
+ 112*!D2*Dl*!DO
+ 113*!D2*D1*DO
+ 114*D2*!Dl*!DO
+ 115*D2*! D1*DO
+ I1S*D2*DU! DO
+ 117*D2*D1*DO;
END$

QOSD

2-171

292008-6

AP-271

LEF File
JR Donnell
Intel
January 24, 1986

5C121
Digital Crosspoint Switch
.LB Version 3.0, Baseline 17x, 9/26/85
PART:
5C121
INPUTS:
100@37, IOl@36, I02@35, I03@34, I04@8,
I ll@32, Il2@31, 113@30, Il4@29, 115@28,
Dl@3, D2@4, D3@5, D4@6, D5@7, ILE@l
OUTPUTS:'
QOO@12, QOl@13, Q02@14, Q03@15, Q04@16,
Ql1@23, 012@22, 013@21
NETWORK:
CLK
INP(CLK)
ILE
INP(ILE)
100
LINP(IOO, ILE)
101
LINP(IOl, ILE)
102
LINP(I02, ILE)
103
LINP(I03, ILE)
104
LINP(I04, ILE)
105
LINP(I05, ILE)
106
LINP(I06, ILE)
107
LINP( 107, ILE)
110
LINP(IlO, ILE)
III
LINP(lll, ILE)
112
LINP(I12, ILE)
11.3
LINP(Il3, ILE)
Il4
LINP(Il4, ILE)
115
LINP(Il5, ILE)
Il6
LINP(Il6, ILE)
Il7
LINP(Il7,ILE)
DO
LINP(DO, ILE)
Dl
LINP(Dl, ILE)
D2
LINP(D2, ILE)
D3
LINP(D3, ILE)
D4
LINP(D4, ILE)
D5
LINP(D5, ILE)
000, OOOFBK
RORF(QOOD, CLK, GND, GND,
001, OOlFBK
RORF(OOlD, CLK, GND, GND,
002, 002FBK
RORF(002D, CLK, GND, GND,
003, 003FBK
RORF(003D, CLK, GND, GND,
004, Q04FBK
RORF(004D, CLK, GND, GND,
005, 005FBK
RORF(005D, CLK, GND, GND,
006, 006FBK
RORF(006D, CLK, GND, GND,
007, 007FBK
RORF(007D, CLK, GND, GND,
OlD, OlOFBK
RORF(OlOD, CLK, GND, GNp,
011, ollFBK
RORF(OllD, CLK, GND, GND,
012, 012FBK
RORF(012D, CLK, GND, GND,
013, 013FBK
RORF(013D, CLK, GND, GND,
SELECTEOOF = NOCF(SELECTEOO)
SELECTEQIF = NOCF(SELECTEOl)
EQUATIONS:
SELECTEOI
110
D2'
Dl'* DO'
+ D2 * Dl'
DO'
114
+ D2'
Dl * DO'
112
+ D2'
Dl' * DO
III
+ D2 * Dl * DO' * 116
+ D2 * Dl'
DO * 115
+ D2' * D1 * DO * 113

*
*
*

*
*

I05@9, I06@10, 107@ll, IlO@33,
116@27, 117@26, CLK@38, DO@2,
Q05@17, 006@18, 007@19, 010@24,

VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)
VCC)

*
*
*

2-172

292008 12

inter

AP-271

LEF File (Continued)
+ 02

+
+

+
+
+

QI00

*
*
*

04'
Q12FBK
+ 03
Q12FBK
+ 05
Q12FBK
+ SELECTEQIF
05'

*
*
*

03'
QIIFBK
+ 04
QllFBK
+ 05
QllFBK
+ SELECTEQIF
05'
03

* QI0FBK
*

+ 04
QI0FBK
+ 05
QI0FBK
+ SELECTEQlF

Q070

* 00'
* 104
* 102
* 101
107;

*
*

03'
Q13FBK
+ 04'
Q13FBK
Q13FBK
+ 05
+ SELECTEQIF
05'

QII0

117;

* 106
* 105
* 103

Q120

* DO *

* *
*
*
* *

Q130

100 * 02' * 01'
02 * 01' * 00'
02' * 01 * 00'
02' * 01' * 00
02
01
00'
02
01'
00
02'
01
00
02 * 01
00 *

SELECTEQO

03'

* 04 * 03;
*

* 03';

* 04' * 03;

* 05' * 04' * D3';

* Q07FBK
*

+ 04'
Q07FBK
+ 05' * Q07FBK
+ SELECTEQOF * 05 * 04 * 03;

Q060

04' * Q06FBK
+ 05' * Q06FBK
+ 03 * Q06FBK
+ SELECTEQOF * 05 * 04 * 03';

Q050

* Q05FBK

03'

+ D5' * Q05FBK
+ 04 * 005FBK
+ SELECTEOOF * 05 * 04'

0040

05' * 004FBK
+ 03 * Q04FBK
+ 04
Q04FBK
+ SELECTEQOF

0030

*. 03;

D3'

* D5 * D4'

03' i

* Q03FBK
*
*
*

+ D4'
003FBK
+ D5
Q03FBK
D5' *04*03;
+ SELECTEQOF

Q02D

D4' * Q02FBK

+ D3
002FBK
+ D5 * 002FBK
+ SELECTEOOF

0010

* D5'

*04*03';

03' * 001FBK

*
*

+ D4
001FBK
+ 05
QOIFBK
+ SELECTEOOF * 05' * 04' * 03;

QOOO

D3 * OOOFBK
+ D4 * OOOFBK
+ 05 * OOOFBK
+ SELECTEOOF

292008-13

* D5' * D4' * 03';

ENO$

292008-14

2-173

inter

AP-271

RPT File
Logic Optimizing Compiler Utilization Report

*****

Design implemented successfully

JR Donnell
Intel
January 24, 1986

o
5C121
Digital Crosspoint Switch
LB Version 3.0, Baseline 17x, 9/26/85
5C121
ILE
DO
Dl
D2
D3
D4
D5
104
105
106
107
000
001
002
003
004
005
006
007
GND

-: 1
-: 2
-: 3
-, 4

-:
-:
-:
-:
-:

5
6
7
8
9
-: 10
-: 11
-: 12
-: 13

-: 14
-:15
-:16
-: 17
-: 18
-: 19
-:20

40:39:38:37:36:35:34:33:32:31:30:29:28:27:26:25:24:23:22:21:-

Vec
Vec
CLK
100
101
102
103
IlO
III
Il2
Il3
Il4
Il5
Il6
II7
GND
010
011
012
013

**INPUTS**
Nallle

Resource

MCell I/:

PTerms

MCells

ILE

INP

LINP

13
15

LINP

13
15

LINP

13
15

LINP

9
10
11
12
17
18
19
20
21

Feeds:
OE

Clear

Clock
Latch

292008-9

2-174

inter

AP-271

RPT File

(Continued)

22
23
24
D4

LINP

9
10
11

12
17
18
19
20
21
22
23
24
D5

LINP

9
10
11

12
17
18
19 .
20
21
22
23
24
104

LINP

0/ 4

105

LINP

0110

106

LINP

0/ 8

107

LINP

0/ 6

LINP

0/10

LINP

0/ 8

Il5

LINP

0/ 6

114

LINP

01 6

Il3

LINP

0/ 8

112

LINP

0/10

III

LINP

0/ 4

IlO

LINP

103

LINP

102

LINP

101

LINP

100

LINP

eLK

INP

Reg
292008-10

2-175

inter

AP-272

APPLICATION
NOTE

June 1986

The 5C060
Unification ota CHMOS System

J. R. DON.NELL
PROGRAMMABLE LOGIC ApPLICATIONS
INTEL CORPORATION

Order Number: 292009-003

AP-272

INTRODUCTION

OBJECTIVE

From an outside glance, the world of computers and
microprocessors seems filled with dedicated ICs that
fulfiJl a variety of system needs. Upon closer inspection
we find that designers must still reach into their bag of
random logic to link together all of the parts of the
system. It seems a shame to stuff a board full of high
powered peripherals and still have portions of that
board wasted on decoders, latches, and other miscella-'
neous random logic.

This application note covers the design of three separate circuits for Intel's CHMOS Design Kit. The functions performed by the 5C060 are: Memory decoding,
wait state generation, and the power down circuitry for
the 80C88 system clock.

MEMORY DECODING
The system in question supports one 32K bank of
EPROM memory, and four banks of 4K static RAM.
Figure 1 shows the memory map of this system. Address lines AI9, A13, and A12 will be used to decode
the address space. PWR_DWN and S2_MIO serve as
enables. In addition, to avoid data bus contention signals memory read (MRDC) and advanced memory
write (AMWC) are decoded along with the address
lines for RAM chip selects. This is necessary for devices without output enables (OE) on multiplexed address/data busses.
.

True, programmable logic has been around a long time.
But that logic is somewhat rigid in form, one time programmable, and can also double as space heaters. These
devices are totally unacceptable for a CMOS system.
What is needed is a flexible PLA architecture, erasability for prototyping, and CMOS for low power. In addition, for this particular application the device must perform from static operation to 10 MHz.

FfFFF

EPROM

•
•

•
•
•

•
03FFF
RAM16K

D2FFF

03000

RAM8K
02000

O1FFF

RAM4K
01000

OOFFF

RAMO
00000

292009-1

Figure 1. 80e88 Memory Map

2-178

intJ

AP';272

Figure 2 shows a discrete implementation of the chip select decoding logic.

A12 - - - I A
A13

----I

A19 - - - I C

RAM4KCS

Y4
PWRDWN

---a

1:>------.

Vi 1)----,
G2B

S2MIO - - - I G1

G2A

I:>----~---l--'

74138

292009-2

Figure 2. Discrete Decoding Logic Solution
Several options for entering this design are available
through Intel's Programmable Logic Development System (iPLDS). (For a more complete description of
iPLDS the reader is referred to the iPLDS data sheet.)
The design entry vehicle chosen for this application
note is the Logic Builder. (Logic Builder is an interactive netlist method of design entry especiaIly suited to
Boolean equation entry and entry from existing schematics.) Several reasons are behind this decision. First,
the Logic Builder software is included in iPLDS. In
addition, Logic Builder' entry is very fast, the designer
may choose either netlist entry or Boolean equations,
and finaIIy, the Logic Builder software makes additions
and corrections of design very ..~y.
Using Logic Builder, the first step for this design is to
determine the equations for the 3 to 8 decoder shown in
Fignre 2. These equations are simply the decoding of
the address lines ANDed with the enable signal. Equations 0 thru 8 implement the decoding function of Fig.
ure 2:
/YO = /AI9*/AI3*/AI2*ENABLE;
/YI ';= /AI9* / A13* Al2"ENABLE;
/Y2. = /AI9*A13*/A12"ENABLE;
/Y3 = /AI9*A13*AI2*ENABLE;
/Y4 = AI9*/A13*/A12*ENABLE;
/Y5 = A19*/A13*AI2*ENABLE'
/Y6 = AI9·A13*/AI2·ENABLE~ .
/Y7 = AI9*AI3*AI2*ENABLE;
ENABLE = /PWRDWN*S2MIO;

(0)
(I)
(2)
(3)
(4)
(5)
(6)
(7)
(8)

Armed with this knowledge it becomes trivial to enter
the circuit of Figure 2 into Logic Builder. Included in
the Appendix is the Advanced Design File (ADF) created by Logic BIJi1der for this circuit (ADF-I). Typically the ADF would now be submitted to the Logic Optimizing Compiler (LOC) for Boolean minimization and
design fitting. In this case we have used only a smaIl
portion if the logic available in the 5C060 so let us
continue with the wait state generator and power down '
circuitry.

Power Down
Since this design is based on the 80C88 we can actuaIly
stop the system clock for extended periods of time and
power back up as if nothing had occurred. The circuit
to achieve this power down is shown in Figure 3.
As long as the PWRDWN signal is low the 82C84
clock output is OR'ed with a logical zero from the
PWRDWN flip-flop. As a result the 82C84 drives the
80C88 system clock. If PWRDWN goes HIGH, the
rising edge ofthe.next 82C84 clock will set the output
of the PWRDWN flip-flop HIGH inhibiting the fall of
the next clock cycle. The 80C88 system clock will remain HIGH until PWRDWN goes' LOW and the
PWRDWN flip-flop is clocked from the 82C84 clock.
Using this configuration we avoid partial clock cycles
for the 80C88 system clock.

2-179

inter

AP-272

Vee

BOC88CLK

292009-3

Figure 3. 80C88 Power Down Circuit

Again, entering this circuit into Logic Builder is trivial.
In fact it can be added directly to the decoder circuit
shown above. The ADF file for this addition is shown
in the appendix under ADF-2.

(LEF), arid the Utilization Report. These are also included in the appendix for each step in this design process.

LOC FILES

Wait States
The majority of memory and. peripheral devices which
fail to operate at the maximum CPU frequency typically do not require more than one ,wait state. The circuit
shown in Figure 4 is an example of a simple wait state
generator. The circuit operation is as follows. Given
that a memory location requiring a wait state has been
selected, ALE in conjunction with IWAITCS will clear
the flip-flop-driving the 82C84RDY line high low.
The 82C84 samples the RDY line during T2 of the
80C88 bus cycle, arid in this case detects a wait state.
The rising edge of T2 then clocks the 82C84RDY line
high thereby inserting only one wait state ..
Once again, adding this circuit to the existing decoder
and power down design is simple. The final ADF file is
given in the appendix under ADF-3. Once the final
design has been completed the ADF is submitted to the
Logic Optimizing Compiler. LOC compiles the design,
performs Boolean minimization, and fits the design into
the target EPLD. In addition, LOC produces two files.
The JEDEC programming file, the Logic Equation File

The JEDEC File
The JEPEC file is analogous to the object code file that
is used to program EPROMs. This file is used by the
Logic Programming Software (LPS) to program Intel's
EPLDs.

The LEF File
The LEF file is an optional file produced by the compiler. The LEF file contains the minimized Boolean equations which resulted. from the original ADF. Some interesting points can be raised concerning the LEF file.
Looking at LEF-3, first recall that the EPROM chip
select was a function of A19, A13, A12, and the enable
signals. It turns out that after minimization the
EPROM chip select depends only on A19 and the enable signals (lPWRDWN and S2MIO). This is shown
in the LEF file. One other point, the initial wait state
circuitry employed a JK flip-flop. The compiler automatically minimized this circuitinto a D-type flip-flop
with feedback achieving the same functionality.

2-180

inter

AP-272

GND

Vee

WAITCS __P~I~N~~O~U~T~__~i~~~__~~--~~~-;

INP
ALE --.:P:..:I:.:N~--=O=U.:..T__________---,

>--{:::>i------82C84RDY

INP

292009-4

Figure 4. Single Wait State Generator for the 80C88

The Utilization Report

SUMMARY

Finally, the Utilization Report contains the pin·out for
the design, information about the architectural layout
of the design, and a percent utilization for pins, macrocells, and product terms. Examining the utilization report for this design we find that two of the sixteen macrocells are still available. We could therefore add more
functionality in the same 24 pin package. Possible additions would be more memory decoding, invalid memory detection, additional wait state generators, etc. One
point should be raised: The circuitry designed in this
applications note is relatively simple compared to the
complex logiC functions that could be implemented in
the 5C060.

The designs shown in this applications note are typical
requirements of any miCroprocessor system. The 5C060
provided a single chip solution to bind together the primary elements of that system. Few other types of pro·
grammable logic could implement the same logic in a
single package. None could do it in CMOS erasable
logiC. The 5C060 has room for more.

2-181

AP-272

APPENDIX
ADF·1
III OnnnBl1
Tnt .. 1
,JIlDuary

:n, HIRR

~C060

~CORO

O.. r.ntl"r r"r ROCSS Ayot,"10 - Ifill RAM aDd upper 51211 BPROM
tR VnrRinn 3.0, RnRn1inn 17~, 9/2R/R5
PART: 50060
INPUTS: A19,AI~.Al2.PWROWN.R2MIO.AMWO.MRDO
Oll'PIITS: RAMOC:S.RAM41tC:S.RAMRItCS.RAM1RKCS.RPROMCS
NBTWORII:
RAMOOS = OONF (RAMOes,VC:C)
RAM4KC:S = CONF IRAM4KC:S.VC:C)
RAMBKCS = CONF IRAMBKCS,VCCl
RAM1RItc:S = C:ONF IRAM1RKC:S.VCC:l
RPROMCS = CONF I EPROMCS ;Vce)
A19 = TNP IA19)
Al!! = INP (U3)
A12 = TNP (A121
PWRDWN = INP IPWROWNl
82MTO = TNP 182MTOl
MROC = INP IMHDC)
AMWC = TNP IAMWC:l
RQIIATIONS:
RAMRKCS = II/MROC:*Y2
+ I AMWC*V2l :
RAM1SKC:S = II/MROC:*Y3
+ I AMwe*V3) :
RPROMC:S
II/Y7
+ IVS
+ IY5
+ IY41:

Y7
IIA19*Al~*A12*RNARtRl:
YS
IIA19*A13*/AI2*ENABLB),
V5
IIA19*/A13*A12*RNARtRl,
V4
IIAI9*/AI3*/AI2*BNABLB1,
RNART.R = IPWIIOWNtS2MTO,
Y3 = II/A19*AI3*AI2*BNABLE),
Y2 = II/A19*A13*/A12*RNARtRl,
RAM4KCS = II/MRDC*VI
+ IAMWC*Vl 1,
YI = II/AI9*/AI3*AI2*BNABLE1,
RAMOCS = II/MROC:*VO
+ I AMWCnO) :
YO = /I/A19*/A13*/~12*RNARtRl'
RNDS

2-182

292009-5

inter

AP-272

ADF-2
.JR

nonn~

Intel
J"nun~y

31. 19R6

Iil1060

5C060
Decoder for 80C88 .yftte. - 16K RAM and upper 512KBPROM
PluR powr.r down r:irr.llit

LB Version 3.0, Baseline 17x, 9/26/85
IiC060
INPUTS: A19,A13,A12,PWRDWN,S2MIO,AMWC,MRDC,B2CB4CLK
OUTPUTS: R~MOCS. R~M4KIlS. RAMRKCS. R~M16KIlS. RPROMIlS. STOPC1.K. AOCRRlll,K
NRTWORK:
RAMOCS = eONF (RAMOCS,YCel
R~M4KCS = CONY (R~M4KCS.YIlCl
RAM8KCS = eONF (RAM8KCS,YCCl
R~M16KCS = CONY (R~M16KIlS.YCCl
RPROMeS = CONF (BPROMCS,YCCl
STOPIlLK.STOPCLK~ = RORF (PWRnWN.R2CR4CLKR.GNn.GNn.YCCl
ROCRaCLK = eONF (BOCBBCLK,YCCl
PWRnWN = TMP (PWRnWNl
R2CR4CLKB = CLKB (B2CB4CLKl
ROCRRCLK = OR (STOPCLKY.R2CA4CLKl
R2CB4CLK = INP (R2CR4CLKl
Al11 = TNP (Al111
A13 = INP (Al3l
A12 = TNP (A121
S2MIO = INP (S2MIOl
MRnC = TNP (MRnCl
AMWC = INP (AMWCl
RQU~TTONS:
.
RAMOCS = 1(IMRnC*YO
+ I AMwc*yn 1 :
RAM4KCS
1(IMRDC*Yl
+ I AMWC*Yl1 :
RAMBKCS
1(IMRDC*Y2
+ I ~MWC*Y21 :
RAM16KCS = 1(IMRDC*V3
+ I AMWC*V31 :
RPROMCS
1(IY7
+ IY6
+ IY5
P~RT:

+ IY41:

YO
1(IA19*/A13*/A12*BNABLBl:
Yl
1(IA19*/A13*A12*RNARLR1:
Y2
1(IA19*A13*/A12*ENABLB1:
Y3
1(/~111*A13*~12*RNARLR1:
Y7
I(Alll*A13*A12*BNABLBl:
Y6
!(A19*A13*/A12*RNARLRl
Y5
I(A19*/A13*A12*BNABLBl
Y4
1(~19*/~13*/A12*RNARLR
KNABLB = IPWRDWN*S2MIO;
RNns

292009-6

2-183

AP-272

3R Donnell
Tntel
.January 31, 1986
';C060

ADF-3

5C060
Dftr.o~er
Plu~

for ROCRR 8vetea - 16K RAM and upper 512K EPROM

p~wp.r

dnwn

r.ir~uit

Plus wait state circuit

LR YnrRion 3.0. Rn~~lin~ 17~. 9/26/R5
PART: 5C060
INPUTS: Al9, Al3, Al2. PIIRDIIN, S2MIO;AMIIC. MRDC, 82C84CLK, ALE, IIAITCS
OIlTPIITR: RAMOCR. RAM4KCS. RAMRKCS. RAMI6KCR. RPROMCS. STOPCI.K. ROCRRCI.K. R2CR4RnV
NETIIORK:
RAMOCS = CONF IRAMOCS,YCC)
RAM4KCS = CONF IRAM4KCS.YCC)
RAM8KCS = CONF IRAM8KCS,YCC)
RAMI6KCS = CONF IRAMI6KCS.YCC)
- RPROMCS = CONF I EPROMCS, YCC)
STOPCI.K. STOPCI.KF = RORF IPWRnWN. R2CR4CI;KR. GNn. GNn. YCC)
ROCRRCtK,80C88CLKF = COIF 180C88CLK,YCC)
R2CR4Rnv = RONF I R2CR4Rnvn. ROCRRCI.KR. R2cR4Rnvc. GNn. Vce)
PIIRDIIN = INP IPIIRDIIN)
R2CR4CtKR = CtKR IR2CR4CtK)
ROCRRCLK = OR ISTOPCLKF,R2C84CLK)
R2CR4CI.K = INP I R2CR4CT.K)
A19 = INP IU9)
AI3 = JNP (AI3)
Al2 = INP IAl2)
S2MTO = TNP (S2MTO)
MRDC = INP (MRDC)
AMWC = JNP (AMWC)
ROCRRCLKB = CLKB 180C88CLKF)
WATTCS = TNP IWATTCS)
ALB = INP I ALE)
RQIIATTONS:
RAMOCS = II/MRDC*YO
+- IAMWC*VO):
RAM4KCS
II/MRDC*Yl
+ I AMWC*YIl;
RAM8KCS
/1/MRDC*Y2
+ I AMWC*V2) ;
RAM16KCS = /(/MRDC*Y3
+ IAMIIC*V3):
RPROMCS
/1/V7
... iV6
+ /VS
... IV4):

VO
/(/AI9*/AI3*/AI2*ENA8LI):
YI
II/AI9*/A13*A12*RNARtR):Y2
/(/AI9*AI3*/AI2*£NA8L£);
Y3
1(IAI9*AI3*A12*RNARtR):
Y7
/IAI9*AI3*AI2*ENA8L8);
Y6IIA19*A13*/A12*RNARLR):
Y5
IIAI9*/AI3*AI2*INABL£);
Y4
j(A19*/A13*/A12*RNARLR):
RNABL£ = /PIIRDWN*S2MIO:
R2CR4RDVD
/R2CR4RDVC;
R2CR4RDYC = /IIAITCS*AL£;
RND.
292009-7

2-184

Ap·272

.JR non", .... ' 1
tntel
.Jnnunry ~1.

LEF·3

1RA6

~G060

Se060
Decoder for 80C88 system - 16K RAM and uppp.r 512K BPROM
Plu~ pow~r down r.irr.uit
Plua wait atate circuit
tR V~r9ion ~.O. RAH~lin~ 17~. 9/26/Rfi
PART:
~G060

TNPIJ'I'S:
A19,

A13, A12, PWRDWN, S2MIO, AMWC, MRDC, 82C84CLK, ALE, WAITCS

OIJ'I'PIJ'I'S:
RAMOCS, RAM4KCS, RAM8KCS, RAMI6KCS, EPROMCS, STOPCLK, 80C88CLK,
R2GR4RnV
NR'I'WOR~:

U9
Al~

INPCAl9)
TNPIA1~)

A12 = INPCAl2)
PWRnWN
TNPIPWRnWN)
INPCS2MIO)
S2MIO
AMWG
TNPIAMWG)
MHnG
INPCMRDC)
R2GR4GL~
TNPIR2GR4GLK)
ALE = INPC ALE)
WAT'I'GS
TNPIWAT'I'GS)
HAMDCS
CONFCRAMOCS. YCC)
RAM4KGS
GONFIRAM4KCS. YGC)
RAM8KCS
CONFCRAM8KCS. YCC)
RAM16~CS = CONFIRAM16KCS. YGC)
RPROMCS = CONFCEPROMCS, YCC)
.. SGOOon = CLKRIR2GR4CL~R)
STOPCLK, STOPCLKF = RORFCPWRDWN, .. SGOOOD, GND, GND, YCC)
ROGRACLK. ROGRRCLKF
GOTFIROCRRCLK. YCG)
.. SGOOID
CLKBC80GR8GLKB)
RONFIA2GA4Rnvn . . . SGOOln. R2GR4RnVG. GNn. VGG)
R2GR4RnV
RQIJATIONS:
82C84RDYC
WAITCS'
ALE:

=
=
=
=

.. SGOOln

=
=
=
=
*
= ROGRRGLKF:

R2GR4RDYD = CWAITCS'
ROGRRGT.~

IS'I'OPCT.~F'

.. SGOOon

R2C84CLK:

ALE)':

* R2CR4CT.K')':

= IA19 * PWRnWN'
RAMl6KCS = MRDC * AMWC
RPROMCS

+ Al9'

RAMRKGS

MRne
+ Al9'

MRne
RAM4KeS
+ At!!'
RAMOes

MRne
+ Al9'

* A13

•

* S2MTO)':
A12 • PWRDWN' • S2MIO:

* AMWG
* Al3 • Al2'

PWRDWN'

• S2MIO;

• AMWC
* Al3' • Al2 • PWRDWN' * S2MIO;
• AMWC
* Al3' • H2' * PWRDWN' * S2MIO;

RNnt

292009-8

2-185

Ap·272

RPT·3
T~~;~

Optt~izing

*****

nn~i~n

Co.piler Utilization Report

impln.nnt~rl ~unnnRAful1v

.TR Donnell
Tntel
January 31, 19B6
~C060

nCOI;O
Dp.r.oqp.r for BOCBB sYBtem - 16K RAM and uppp.r 512K EPROM
Plu~

pnw~r

down nirnuit

PluR wRit state circuit
T.R Vp.r!'lion ::t.O.

Rn!llp.linr: 17,<,.

9/26/R5

~COI;O

GND
PWRnWH

1
2

GND
GND

WAITCS

4
5
I;

AT.R

R2C84CLK
MRnc
AMWC
S2MTO
H2

R
9
-: 10

-: 11
GNn -: 12

24:- Vee
Z~:- A19
22:- STOPCLK
21: - R2CR4RnV
20:- BOC88CLK
1~:- RPROMCS
18:- RAM16KCS
17:- RAMRKCS
16:- RAM4KCS
1n:- HAMOCS
14:- U3

n:-

GND

UTHP"TS**
FP.P.OR:

MCr.l1,

PWRDWH

PTf':rm!ll

INP

MCr.l1~

OF.

Clnnr

Clonk

1
4

n
n
7
R

WA TTCS

THP

0/ R

ALE

INP

0/ 8

R2CR4CT.K

TNP

MRDC

INP

0/ 8

-2

0/ R

5
6
7
R

AMWC

TNP

0/ R

n
7
R

S2MTO

TNP

0/ R

4
~

292009-9

2-186

inter

AP-272

6
7

R
A12

TNP

r;
6

7
R

A13

TNP

r;
6

7
R

A19

TNP

4
r;
6

7
A

**OlfTPlfTSU
MCr.11

PTor1R9

NRJIIP.

RC":90urr.r.

RAMOCS

CONF

2/ B

RAM4J(CS

CONF

21 R

2/ 8

RAMBKCS

CONF

RAM16KCS

CONF

21 R

I!PROMCS

CONF

1/ B

ROCARCI.I!

COTF

11 A

A2CB4RDY

RONFA

1/ B

STOPCI.I!

RORH

MCo119

FPop.de:
OR

Clr.nr

Clor.k

1/ A

**lfNlfSRO RBSOURCBS**
Naae

Resource

1
3
4

MC"l1

PTera.

9
10

.. PART lfTTI. TUTTONU
RUI
A711
9_

Pin.
MAcrae.ll.
Ptftr••

292009-10

2-187

inter

APPLICATION
NOTE

AP-276

June 1986

Implementing a CMOS Bus
Arbiter/Controller in the
5C060 EPLD

DANIEL E. SMITH
APPLICATIONS ENGINEERING
INTEL CORPORATION

Order Number: 292012-001

AP-276

INTRODUCTION

SCOGO IMPLEMENTATION

This application note shows how to implement a
CMOS Bus Arbiter/Controller in an Intel 5C060
EPLD (Erasable Programmable Logic Device). The
note includes a brief overview of a similar circuit implemented with typical PLA devices, a more detailed discussion of the 5C060implementation, and a summary.

The equivalent functions for both the MULTIBUS I
arbiter and controller fit inside a single 5C060 EPLD
device. The 5C060 device is available in a 24-pin 0.3"
DIP package. Figures 4 and 5 show logic diagrams for
the arbiter and controller functions. When compared
~ith the PLA implementation, some differences in the
design are immediately apparent. These differences result from the characteristics of the EPLD macrocell or
from corrections to the circuit used in Figures I and 2.

The bus priority resolution and arbitration scheme selected for the circuit is that used by the industry-standard MULTIBUS I interface. Operation and timing for
the MULTIBUS I interface is well understood by most
engineers and is described in readily available Intel
pUblications. Thus, a description of the MULTIBUS I
interface is not included here. The bus arbiter/controller functions shown here support both serial and parallel priority resolution between bus masters. Timing is
equivalent to MULTIBUS I specifications. Electrical
specifications for both the PLA and EPLD approaches
vary from MULTIBUS I standards. Neither of the two
circuits discussed here provide the full current sink capability for all MULTIBUS I signals. Because the
EPLD implementation is designed for CMOS systems,
however, this requirement is not relevant for the 5C060
implementation.

PLA APPROACH
The functional equivalent of a MULTIBUS I arbiter/
controller can be implemented in two 20-pin PLA-type
devices as shown in Figures I and 2. (Figure I shows
the logic for the arbiter device. Figure 2 shows the logic
for the controller and the connections to the arbiter.)
Figure 3 shows the arbiter list file as an example of
PLA-type files. Two different 20-pin PLA devices are
required to implement the arbiter and controller functions, a 16R4-type device and a 16L8-type device.
Implementation of logic devices in PLA-type devices,
such as those shown here, has proven to be quite beneficial. Development time and cost is much less than for
custom silicon device designs. The two PLA-type devices take up less board space than a discrete TTL implementation of the same functions. In addition, the two
raw devices can also be used for different functions in
other products, thereby reducing inventory costs. As a
result of these factors (and others), use of PLA-type
devices has grown substantially in recent years.
With the increased density and flexibility of EPLD devices over typical PLA-type devices, even greater space,
inventory, and cost savings can be obtained by using
EPLDs. The following section shows an implementation of the same arbiter/controller functions in a single
24-pin 5C060 EPLD device.

The major change resulting from the EPLD macrocell
structure concerns the EPLD output buffers. Since output buffers from macrocells are non-inverting (PLAtype devices typically contain inverting buffers), signals
enter the buffers in the same logic orientation from
which they are to appear at the output. The logic for
the EPLD (shown in Figures 4 and 5) incorporates this
change.
Some errors in the PLA-type implementation have also
been corrected in the EPLD design. These changes are
as follows:
• The M/IO input to the MRDC/ and MWTC/ gates
is inverted. M/IO distinguishes between memory
and I/O cycles. The PLA-type implementation does
not use this signal properly; the PLA-type controller
generates read or write commands to both memory
and I/O at the same time, which can result in contention between memory and I/O during bus transfers.
• BPRO/ is gated by BPRN/ in the EPLD design.
When using serial priority resolution, this allows the
highest priority arbiter to prevent all other masters
from controliing the bus. (In the PLA design,
BPRO/ is enabled/disabled only by a local request.
Higher priority arbiters cannot disable all other arbiters. This can result in contention between bus
masters. By gating BPRO/ with BPRN/ in the
EPLD design, this source of bus contention is prevented.)
Figure 6 shows the list file for the arbiter/controller
device. Figure 7 shows the report file produced by the
iPLDS software. This file contains a pinout diagram of
the final programmed device and provides a resource
usage map for the device.
Most of the input and output signals are self-explanatory to those familiar with Intel processors and the
MULTIBUS I interface. The XREQ input is the bus
transfer request signal from the address decode logic.
The BUSY/and CBRQI outputs are bi-directional,
simulated open-collector outputs. These outputs use the
iPLDS 5C060 (Combinational-Output I/O-Feedback)
primitive in the list file. The BUSYI signal serves to
illustrate this use of EPLD outputs.

2-189

intJ

AP-276

A pull-up resistor is used externally (i.e., on the backplane) to hold BUSY/high when no arbiter is in control of the bus. When the arbiter is granted control of
the bus,AEN is clocked high, which enables the output
of the BUSY/driver. Since the input to the BUSY/
driver is low during normal operation (RESET/ inverted), the enabled driver pulls BUSY/low to signal other
arbiters that the bus is in use. When. the arbiter is fmished using the bus, AEN goes low to disable the
BUSY/driver (three-state output). The pull-up resistor
pulls BUSYI. high to signal other arbiters that the bus
is free for use if needed.
Note that BUSY/is also routed into the bus grant logic
as input BSI. BSI prevents the arbiter from taking control of the bus (and driving BUSY/low) when some
other arbiter already has control of the bus. Thus only
one arbiter may pull BUSY/low at anyone time.
The one difference between standard MULTIBUS I
logic levels and the EPLD implementation described
here relates to the BCLK/ signal. MULTIBUS I bus
arbitration uses the negative-going edge of BCLK/ to
synchronize events. All 5C060 flip-flops, however,
clock on the positive-going edge of BCLK/. If all bus
masters in the system use the same arbiter implementation, this poses no problem. Otherwise, an external inverter is required for the BCLK/ input.

COMPARISON/SUMMARY
Both the PLA and EPLD implementations of the bus
arbiter/controller result in a lower device count than a
discrete logic circuit. Lower device count means less
p.c. board space, fewer assembly steps, and fewer device
interconnects. Both PLA and EPLD implementations
are quicker and less expensive to develop than a custom
gate array or dedicated silicon device.
In contrast to the PLA approach, however, the EPLD
implementation requires only a single device, while the
PLA approach requires two different deviceS. Thus the
EPLD approach results in twice the cost savings (inventory and assembly) and half the programming activity to produce the device. Fewer device interconneCts
also means greater reliability. In addition, programmed
EPLD devices can be erased and reprogrammed for a
different application if needed, a feature not available
with PLAs.
Overall, the 'greater flexibility, and the incremental design, manufacturing, and cost'advantages of EPLD devices make them ideal for many applications where
PLA devices would otherwise be used.

2-190

intJ

AP·276

RESET
SREO
RD

BPRO (REO)

WR
BCLK--------------------~~----------~

292012-1

A) Request Synchronizer

RESET ---.+-r,
..
-1

RESET=P--tJ-

AEN--....

BPRO ~-++-I-.J

SREO

OEN

AEN

WR-f-++-I

BCLK ----------------'
BPRO
AEN
RD-f-++-I
AEN (GRANT)

BPRN ~-++-I-.J

AEN
BPRO

BUSY -f-+-+-~

BREO

AEN

~'"''

CBREO----i

BCLK

------------------------1

292012-3
292012-2

B) Grant! Access Logic

C) Bus Transfer Control

Figure 1. PLA Approach to a Bus Arbiter

2-191

inter

AP-276

INTA---------------------r-------~

M/IO--------~------+---~~

BUS CONTROL
LOGIC

RD---Hf-6--1

WR--;.....- - j
SREQ

--~----l

PLA
16R4

BPRN - - - - - - - ;
RESET --------;

t - -.......~AEN
1------ BREQ
1------ CBREQ
1------ BUSY

[=!:===~===

BUS ARBITER

BCLK
BPRO

292012-4

Figure 2. Bus Controller with Arbiter Connected

PLA16R4
ARBOOI
MULTIBUS I ARBITBR
SOME SYSTEM COMPANY
BCLK IWR
IRD
ISRBQ IRBSBT IBPRN
IE
ICBRBQ IBUSY /SYNC IBPRO IABN
SYNC

:= IRBSBT*SREQ*WR

PLA DBSIGN FILB
D. B. BNGR.
1/1;85
NC
NC
NC
IOBN IBREQ NC

GND
VCC

IRESET*SREQ*RD
BPRO

: = IRESET*SYNC

AEN

: = IRESET* AEN*BPRO*WR
+
IRESET* AEN*BPRO*RD
+
IRESET*BPRO*BPRN*/BUSY +
IRESET* AEN*BPRN*/CBREQ

OEN

:= IRESET*SREQ*AEN

IF(BPRO*/AEN) CBREO
IF(AEN) BUSY
BRED

= BPRO*/AEN

= AEN

BPRO +
AEN

292012-5

Figure 3. List File for PLA Arbiter

2-192

inter

AP-276

RES8~~--~--~~

XREQ D~-------L...J

}----CJ BPRO

BCLK~~--------------~~--------------~

BPRND~--~ ~>-----------------------~--~
292012-6

A) Request

RES8 - - - - - - - -.....-1

+-..-"'"

SREQ - - - - - -.....

+-+-......J

BPRN - - - -.....
BSI

----+-+-+--1

AEN
AEN

-+-+----+--I

CBI ----------1
BCLK

----------------------------....1

292012-7

B) Grant

RES8

X:~: _____.-I~
BCLK

R::

CMDEN

------~....I>--B-S-'J-- -<:J
.....

BUSY

292012-8

292012-9

C) Command Enable

.SREQ
AEN ___

D) Busy

"'----~

292012-10

E)CBRQ
Figure 4. Logic Diagram of Bus Arbiter Functions
2-193

AP-276

INTAIN

D--------I

J~--ClINTA

t.f/io D - - -......L
>--+--<:::IIORC

>-+---<:::IIOWC' .

RiiC....+-+--IH

> .....--<:::1 t.fRDC

>-+--<:::1 t.fRWC
AEN

, FigureS. Logic Diagram of Bus Controller Functions

2-1,94

292012-11

AP-276

DANIEL E. SMITH
INTEL CORPORATION
MARCH 27, 1986
VERSION 1.1
REV. A
5C060
CMOS BUS ARBITER/CONTROLLER

PART:
INPUTS:
OUTPUTS:

5C060
BCLK, XREQ, RESET, BPRN, MIO, RD,
WR,
INTAIN
BPRO, AEN, BRBQ, CBRQ, BUSY, INTA, MRDC, MWTC, IORC, 10WC

NBTWORK:
BCLK
INTAIN
XRBQ
RBSET
BPRN
MIO
RD
WR
BPRO
AEN,ABN
BREQ
CBRQ,CBI
BUSY,BSI
INTA
MRDC
MWTC
IORC
IOWC
SREQ
SYNC
CMDEN

INP (BCLK)
INP (INTAIN)
INP (XREQ)
INP (RESET)
HIP (BPRN)
INP (MIO)
INP (RD)
INP (WR)
CONF (BPROe,YCC)
RORF (ABNd,BCLK,GND,GND,YCC)
CONF (BREQe,YCC)
COIF (CBRQel,CBRQe2)
COIF (BUSYe,ABN)
CONr (INTAIN,AEN)
CONF (MRDCe,AEN)
CONr (MWTCe,AEN)
CONF (IORCe, AEN)
CORr (IOWCe, AEN)
NORF (SRBQd,.BCLK,GND,GND)
NORF (SYNCd,BCLK,GND,GND)
NORr (CMDENd,BCLK,GND,GND)

'BUS CLOCK INPUT'
'INT. ACK. INPUT'
'SYSTBM REQUEST INPUT'
UESET INPUn
'BUS PRIORITY INPUT'
'MEMORY/IO INPUT'
'RBAD INPun
'WRITE INPUn
'BUS PRIORITY OUTPUT'
'ADDRESS ENABLB (GRANT)'
UUS REQUESn
'CBRQ/ -- SIMULATBD O.C.'
'BUSY/ -- SIMULATED O.C.'
'INT. ACK. OUTPUT'
'MEMORY READ COMMAND'
'MEMORY WRITB COMMAND'
'I/O READ COMMAND'
'I/O WRITE COMMAND'
'VALID BUS RBQUEST'
'SYNCHRONIZED RBQUEST'
'COMMAND BNABLE'
292012-12

EQUATIONS:
BPROe
ABN"
I

BRBQe
BUSYe
CBRQel
CBRQe2
MRDCe
MWTCe
IORCe
10WCe
SREQd
SYNCd
CMDENd

*
**

(SREQ
/BPRN);
RESET * SREQ * /BPRN * BSI +
RESET
SREQ
AEH +
RESET
/BPRN
AEN
CBI;
/(SREQ + ABN);
/RESET;
/(SRBQ
/AEN);
SREQ
/ARN;
/MIO + RD + CMDBN;
/MIO + WR + CMDEN;
MIO + RD + CMDBN;
MIO + WR + CMDBN;
RBSBT
SYNC;
RESET
XREQ;
/(RBSBT
XRBQ * ABN);

END$

292012-13

Figure 6. iPLDS Network List File

2-195

AP~276

Logic Optiaizing Coapiler Utilization Report

*****

Design iapleaented successfully

DANIBL B. SMITH
INTBL CORPORATION
MARCH 27" 1986
VBRSION 1.1
RBV. A
5C060
CMOS BUS ARBITER/CONTROLLER

5C060
BCLK
MIO
RESBRVED
RBSERVED
RESBRVED
ABN
BPRO
INTAIN
WR
RD
BPRN
GND

-: 1
-: 2

-: 4
-: 5

-: 6

-: 7
-: 8
-: 9
-:10
-: 11

-: 12

24:23:22:21120:19:18:-

l7:-

16:16:14:-

,13:-

Vcc
XRBO
INTA
IOWC
IORC
MWTC
MRDC
BUSY
CBRO
BREO
RESET,
GND

**INPUTS ..
Naae

Resource

BCLK

INP

MIO

MCell

•

PTera.

MCells

INTAIN

INP

01 8

INP

01 8

INP

Clock
CLKl

INP

Clear

2 ,
3
4
6

Feeds':
OE

01 8

3
6

BPRN

INP

RESET

INP

12
13
6
9

10, '
11

12
XREQ

INP

10
292012-14

Figure 7. iPLDS Report File

2-196

intJ

AP-276

UOUTPUTS ..

NB.e

Resource

MCell •

PTerm.

MCell.

Feed.:
OB

ABN

RORF

3/ 8

7
8
9
12

-7
1
2
3

Clear

Clock

5
6

BPRO

CONF

1/ 8

BRBQ

CONF

1/ 8

COIF

1/ 8

12
12

CBRQ

BUSY

COIF

1/ 8

MRDC'

CONr

1/ 8

MWTC

CONr

1/ 8

IORC

CONF

1/ 8

IOWC

CONr

1/ 8

INTA

CONr

1/ ,8

**BURIBD RBGISTBRS**
Name

Resource

NORF

MCell

•
9

PTerm.

MCell.

I/' 8

2
3

Feeds:
OB

Clear

Clock

5
4

'NORF

1/ 8

NORP:

1,1

1/ :8

7
8
12
13

Resource

NCell

PTerm.

**UNUSBD RBSOURCBS**
N...e

PiD

UPART UTILIZATION**
96_
100_

Pin.
MacroCell.
pter ••

292012-15,

Figure 7. iPLDS Report File (Continued)
,

2-197

inter

APPLICATION
NOTE

AP-307

January 1987

EPLDs, PLAs .and TTL
Comparing the "Hidden Costs"
in Production

PEDRO VARGAS
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292030-001
2-198

AP-307

INTRODUCTION

• Prototype costs - first implementation of the product idea

When comparing logic alternatives, too often the outcome is dominated by the piece price of the components. A side by side comparison based on component
costs only, may give the appearance that EPLDs are
cost prohibitive. However, when the overall cost of
manufacturing a system is considered, the higher integration of EPLDs proves to be a cost-effective solution.

• Production costs -

OBJECTIVE
This application note examines the total costs associated with designing, proto typing, and manufacturing a
system. Once these costs have been examined, a comparison is made between EPLDs and other logic alternatives. By being aware of these additional costs, the
engineer can make a more accurate cost comparison as
a design is begun.

COSTS DEFINED
Costs can be difficult to pinpoint, let alone measure.
However, with a bit of examination, we can break down
costs into the following categories;
• Design costs
- the cost of conceiving a product

volume manufacturing of the
product

Usually, the brunt of the cost for the first two categories is dismissed as NRE (non recurring expense). The
effect of these costs on the overall project is examined
later, let's look at the third category. Production costs,
can be further broken down into;
• Component costs- the cost of the parts per board
• Inspection costs - labor costs for receiving the
parts
• Inventory costs - the cost for storing, handling
and dispensing the parts
• PCB fabrication - the cost for labor and equipment
used in building a board
• Integration costs - the cost of harnesses, enclosures,
nuts and bolts etc.
It's important to understand how the cost of a product
is affected not only by the cost of the ICs used, but also
by the other costs listed above. Figure 1 is a graph
which shows this relationship.

COST OF
CIRCUITS

'"....
VJ

OPTIMUM
COMPLEXITY

M S I - - - - - - - - - - - - - - - · VLSI
CIRCUIT COMPLEXITY

Figure 1. Optimizing Circuit Complexity

2-199

292030-1

intJ

AP-307

REsn~
XREO ~ .
AEN
BCLK

eMDEN

LS10
LS74

292030-4
Ull

1/4Ul0

~S126

=~~~
AEN

AEN

.BSi
292030-5

SREQ --'.......or-........
AEN

~-",-...J

LS08

C8i
292030-6

lNTAIN

D---------I

M/iO D----1>-1._

WRD.....- f - - I

Figure 2. MULTIBUS Arbiter/Controller-TTL Implementation

2-200

AP-307

The graph shows that as the density of the components
used in a system progresses from SSI to VLSl, the cost
for these devices increases. This isn't surprising, denser
chips cost more to make. At the same time, by using
denser devices, system hardware cost decreases. This is
shown by the center line, which encompasses all the
costs listed above. The bathtub curve above these shows
the effect that denser lCs has on a system. That is, by
using higher integration lCs, more functions are removed from the board. This in turn reduces the cost of
the system in labor and parts costs.

ARBITER CIRCUIT
Let's explore costs in more detail with an example. The
example used here is the circuit of Figure 2, a
MULTIBUS® I arbiter/controller. The circuit is used
by bus masters arbitrating for control of the bus. Our
implementation comparison contrasts TTL, PAL', and
EPLD solutions.

Implementation Requirements

A cost-effective product is one that uses the most efficient logic for the application. It's important to note
that use of the least expensive component may not
translate into system cost savings.

The TTL implementation is typical of many board level
designs in the sense that it relies on inexpensive
LSTTL. Figure 2 shows that the implementation is
composed of standard logic gates and D-latches. The
component list in Table 1 shows the circuit breakdown
in more detail.[20]

PAL* is a registered trademark of Monolithic Memories Inc.

BUS CONTROL
LOGIC

RD--'HH..........

CMDEN

WR ---11-4....--1
SREO ~""----t

------t
RESET ------t
BPRN

AEN
PLA
16R4

BREO
CBREO

BUS ARBITER

BUSY
BPRO
BCLK

292030-8

Figure 3. MUlTIBUS Arbiter/Controller-PAL Implementation

2-201

intJ

AP-307

• IC Count

- The total chip count
- The total number onc pins
- The traces required to connect logic gates together
• Area (inches-square)- The sum of the area of all ICs

Table 1. Arbiter/Controller TTL Component List
IC

Type

DIP

U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11

LS08
LS74
LS21
LS10
LS11
LS02
LS27
LS27
LS366
LS126
LS04

14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
14 PIN
16 PIN
14 PIN
14 PIN

• Pin Count
• Interconnections

ICC (mA) Area (in2) Cost $
8.8
8
4.4
3.3
6.6
5.4
6.8
6.8
21
22
6.6

0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.24
0.21
0.21

0.18
0.24
0.22
0.16
0.22
0.17
0.23
0.23
0.39
0.39
0.16

• ICC (rnA)

Production Costs

The PAL version of the circuit is shown in Figure 3.
Two PALs are used due to the requirement of registered outputs on several of the signals.l20]
The complete circuit can also be designed in one 5C060
EPLD (Figure 4).1 18] Looking at the three figures
. quickly points out the amount of circuit board space
required by each version. The three implementations
are compared side by side in Table 2.

5C060
BCLK
MIO
RESERVED
RESERVED
RESERVED
AEN
BPRO
INTAIN
WR
RD
BPRN
GND

1
2
3
4
5
6

24
23

10
11
12

15
14
13

Vee
XREQ
INTA
IOWC
IORC
MWTC
MRDC
BUSY
CBRQ
BREQ
RESET
GND

- The current consumed while
active
- Total.power consumption at
5 VDC.

Earlier, we noted that production costs consist of many
variables. Usually, these variables are lumped together
under the term "hidden cost". Although hidden costs
are kept in mind by engineers, lack of tangible figures
usually precludes their use in detailed cost breakdowns.
For this reason, several manufacturers and consulting
firms have come up with typical costs per IC and per
pin.
For example, SOURCE III (San Jose, CA) reports in
one of their studies that the manufacturing cost of a
system translates to about 0.35 cents per IC pin. ICE
Corporation (Scottsdale, AZ) and EDN magazine concur that the inserted cost of an IC is about·$2 dollars.
DATAQUEST also published a cost of about $2 to $4
per Ie. While the data seems to be consistent, most
engineers want to see for themselves how figures like
these might be arrived at. The next sections provide
insight into this process.
COMPONENTS

The cost of the component is the easiest valu~ to obtain.
A quick call to a distributer or (at worst) a sean
through the back of BYTE magazine (for TTL) givesus
this cost. Table 3 shows the breakdown of component
costs for each version of our MULTIBUS I circuit.
Table 3. Average Component Costs

292030-9

Figure 4. MULTIBUS Arbiter/Controller-EPLD
Implementation
Table 2. Implementation Results
for Arbiter/Controller
Item

TTL

PLA

EPLD

IC Count
Pin Count
Intereonn
Area
Icc (rnA)
Pwr (mW)

11
156
36
2.34
100
500

2
40
7
0.6
'240
1,200

1
24
0
0.36
15
75

Package

TTL

DIP14
DIP16
DIP20
DIP24

$0.25
$0.35
$0.55

PLA

EPLD

$1.50
$2.90

$6.00

The price of TTL has changed very little for the last
few years[24] while EPLDs are dropping in price tremendously. PALs have also leveled off in pricing.
Why? Figure 5 shows the life cycle curve of IC products used by the semiconductor industry. From the
curve we see that TTL is in the stable range and prices
are not likely to drop much more. PALs are also maturing and approaching a stable pricing range. EPLDs
however, are in a growth area and historically this is
2-202

AP-307

-20%

INTRODUCTION

1987

[

GROWTH

MATURITY

SATURATION

PAL
LSTIL

STIL

EPLD

DECLINE (OBSOLETE)

TIL

EPLD
PAL
LSTIL

1988[

STIL TIL

EPLD

1989 [
I

PAL
LSTIL

ISTIL TIL

292030":10

Figure 5. Typical Price Changes Through Semiconductor Product Life Cycle

where the heaviest pricing pressure is. This means that
while EPLDs might be expensive (per part) right now,
it's not out of the question to expect a 30% per year
price reduction as the process is honed and perfected.
In other words, it's also important to consider the price
of a component at the projected production date, not
just at design time.
Life cycle position is'also important in understanding
the gate cost that is associated with programmable logic
devices like PALs and EPLQs. This relationship is
shown in Figure 6. The curves translate our observation
that newer devices have steeper price cuts during their
introduction phase. The PAL curve shows that the cost
per gate is leveling off due to the maturity of the device.
In contrast, the EPLD is in the growth region, and
based on the traditional price reductions, shows a cost
per gate that intersects and bypasses the PAL curve.

INCOMING INSPECTION

For most companies, incoming inspection is more than
taking the parts and putting them on the shelf. Most
have visual checking as weII as some form of IC testing.
The variables here are, what amount of human intervention is needed, are automatic handlers needed, are
"go/no go" tests or "binning" done automaticaIIy? The
typical scenario means that components are graded and
tested individuaIIy; and then placed into one of several
bins or kitted. Because the operators handle a large variety of pinned devices (resistors, capacitors, ICs), the
cost can be distributed on a per pin basis. Many companies use a penny per pin for this cost.l161

2-203

Inspection cost = $0.01 per pin

inter

AP-307

$ COST/GATE
0.03

0.0025

04'85

04'86

04'87

04'88

04'89

04'90

292030-11

Figure 6. Projected Cost Per Gate
INVENTORY

While most engineers agree that reducing parts count
on their board makes the cost of inventory less, they'
usually attribute this to the reduction in component
costs alone. In reality, the overhead of carrying inven.
tory is made up of the following factors;[2J]

Maintenance refers to the cost of handling, counting,
marking, and auditing each IC. Each production manager has their own way of keeping tabs on this. One
way is to charge on a per part basis. A review from
several production oriented journals cites $0.3 cents as
the typical handling charge for 16 pin devices.l 23 ]
Maintenance = $0.03 per 16 pin part.

• Cost of the component
• Cost of storage
• Maintenance costs
• Data processing

Processing[21] usually entails a parts log that tracks
each part by manufacturer, cost, second source etc.
Also, monthly shortage reports are quite common as
are quarterly orders and audits. Limiting this cost to
paper only, at one sheet of paper per week, per year, at
a cost of a penny per part type;

• Usage
• Taxes insurance and interest
• Turnover rate

ProceSSing = $0.52 per part type per year

The American Production and Inventory Control Soci"
ety (APICS)reports that since 1973 the median cost of
carrying inventory has been about .25 % of total production costs. They also note that the largest contributing
factors are the cost of materials handling storage, and
data processing. For simplicity, let's limit our inventory
cost to these items.
Inventory cost = storage

maintenance

= [Total IC area (sq. ft.) x

The cost of manufacturing (cutting, etching, drilling) a
circuit board seems to vary around two pricing methods. Some fab houses charge on a square inch basis.
Others base their price on a gut feeling based on previous jobs. The square inch method is the most common.

processing

Depending on the locale of a company, the cost of storage can vary greatly. However, this cost is charged on a
square foot per year basis. Lets assume a conservative
figure of $20 dollars and distribute this amoung the ICs
in our example circuit.
storage

PCB FABRICATION

$20]/IC count

Items of interest in evaluating PCB costs are, number
of ICs, number of traces and vias, and in general, the
complexity of the board. Traces that are smaller than
10 mils require extra care in etching .. Depending on
complexity, and additional charge might be added to
the area cost. This charge covers material loss in case of
low etch yields. Yield is directly dependent on the number of ICs on a board. In other words, more ICs mean
more holes, tighter traces, and a greater chance of losing some boards in their processing. The average going

2-204

AP-307

rate is $0.20 cents per inch for double-sided boards.
The price increases by about 40% for every two layers.
This extra charge, however is too sUbjective to consider
in our comparison.
PCB Fab

[$0.20

totallC area (sq. inch)]IIC count

Traces

There is a real cost involved with traces, which doesn't
surface until later in the production cycle or on a later
board revision. A technical paper presented at the 1984
international Test Conference[!] estimates that the cost
of a trace on a board is ten to thirty times that of one
made in silicon. The cost of traces is taken up by:
- Increased drilling (more traces = more vias =
more holes)
.
-Lower PCB yield (smaller mill lines drop the board
yield)
- Increased risk of trace to trace shorts (lower reliability)
- More expensive artwork mods (it· costs· more to
move traces around on a board)
- More expensive PCB mods (cost of cuts, jumpers,
and rework)
In our circuit example, an extra trace is that which is
unnecessary in contrasting'implementations. For example, referring to Figure 2, of all the traces required to
connect/RESET in the TTL implementation, only one
will be required for the EPLD and PAL circuit (the
input); the others won't be needed;

ASSEMBLY

The cost of assembling a board is largely dependent on
labor charges and capital. Assembly consists of lead
forming, component insertion, and soldering. The labor
charge is hourly and varies between domestic and offshore assembly houses. While machines can certainly
do lead cutting, crimping, and insertion, human intervention is still an expensive presence. Assembly costs
can be charged on a per board or per chip basis. The
latter is more appropriate for our comparison. The average charge (domestically) is about $0.10 per IC.
Assembly

$0.10 per 16 pin part

One important result of using high integration parts
like EPLDs is that the assembly procedures (manual or
automatic) go smoother. This is due to fewer parts being handled, and less overheating of the equipment.
Overall, the industry reports less insertion faults (parts
stuffed wrong) as denser ICs are used and as insertion
equipment Ijlatures with them.
TEST

Test strategies can vary, but the typical test flow for a
board[3] is shown in Figure 7. The process is basically
taking a board through increasing complexity levels of
testing. For example, ATE might be a bed of nails fixture that catches 60 percent of the faults. Test bed is
usually a backplane with all boards known good except
for the one under test. System test is the final integration of all the boards that were tested, hidividually.

For our comparison, let's take the median value of
twenty as our multiplying factor. Since a silicon trace
costs an order of magnitude less than an EPLD gate
($0.01), the resulting cost of a PCB trace is;
($0.01/10)
Trace cost

$0.02 cents per trace

[total trace count x $0.02]IIC count

~.TEST
~

BED

L..I

SYSTEM

J1,-...;T~EST.;....,j'
292030-12

Figure 7_ Typical Test Flow

2-205

intJ

AP-307

TO NEXT LEVEL
OF TEST OR
SHIPPING

BOARDS IN--r-l"

292030-13

Figure 8. Typical Test and Repair Loop

Errors can occur at any step of the test flow; each time
this happens, a test loop is initiated. This loop is depicted in Figure 8. The cost for testing Ii device depends on
the cost of the equipment, depreciation, the labor rate,
and other factors that are company dependent. There
are several ways to reduce test costs, but the best way is
to reduce the probability of errors occuring. There is no
question that as the number of ICs increases, so does
the probability of error.
With all things considered, the industry reports a nominal test cost of about $0.15 per 1c.[27][2S]

insert, resolder, and clean a component pin[9], one can
see that more ICs on a board directly affect cost. Repair
times also increase dramatically on multi-layer boards
that might have been doubled sided if denser logic was
used.
For our comparison, let's assume that our test equipment is 95% efficient in finding solder faults On the
first pass (no loop). This leaves 5% of the faidts that go
undetected and eventually must be found and repaired.
The estimated cost per pin based on a $6.00 hourly
wage and the two minute repair time is approximately
$0.02 cents.

Test cost = $0.15 per 16 pin IC
Rework
REWORK

The cost of rework is best understood by considering
the cause of errors in more detail. Errors are typically
caused by poor board quality, inadequate solder process, tolerance of insertion, and of course, bad chips.
Table 4 shows the average board fault spectrum. The
figures are a conclusion reached by EVALUATION
ENGINEERING magazine[lO] as to what the industry
is currently seeing. The table shows that the majority of
board errors is due to solder shorts. These errors are
the result of traces or IC holes being too close, which is
what happens on densely populated boards.
Table 4. Average Board Fault Spectrum

Tolerance
Shorts
Insertion
Bad Parts

20%
40%
30%
10%

[$0.02

total pin count]/ICcount

It is important to note that the l'robability of errors is
based on a Poisson distribution [8] that increases exponentially with the number of pins and components.
This distribution is used in wave solder processing to
correct for solder errors. Mathematically this is expressed as:

e-nP(np)X
X!

where; P = The probability that a defect will occur
n = The number of components
p = The fraction defective
x = The actual number of defects
This means that the TTL and PAL version of the arbiter have a higher probability of error than the EPLD
version. However, to make our comparison easier, let's
simplify this to more of a linear relation. For each implementation, the rework cost per IC is calculated by;

Of all the material costs associated with rework, the
main cost is the time spent on a repair. Considering
that it takes approximately two minutes to desolder,

Rework cost

2-206

[(total pin count) X (5%) X ($0.02 cents)j/lC count

inter

AP-307

PRETEST

AFTER
PRETEST
OPERATION

292030-14

Figure 9. Example of a Production Line
QUALITY CONTROL

POWER SUPPLY

In most production operations, boards go through sev·
eral steps of quality inspection. The bare board might
be inspected after preliminary tests and after system
tests. Although 100% inspection should theoretically
eliminate all errors, in real life this rarely happens. The
main reason for this is the complexity of the production
and rework loops as shown in Figure 9.

Price for 5V, single output, switching power supplies as
advertised by several vendors is $1.00 per watt. The
calculation for determining power supply costs in our
comparison is:

Quality control's purpose is to remove defective products and either junk them or rework them, neither of
which is cost effective. The best approach is to design
the quality in, not fix it in. One way to design in quality
is by reducing the possibility of errors and increasing
the reliability of a product. This is one of the primary
advantages of dense logic (like EPLDs and PALs) over
TTL.

Additional Costs

A survey conducted by CIRCUITS MANUFACTURING magazine[8] yielded the cost of $10 to $50 dollars
to inspect, find, and repair a defect on a board. They
summarized that the actual cost of inspection is about
$0.004 for each hole on a board. WithJhis in mind, let
us assume a 100% inspection of our arbiter circuit for
each implementation. This means that each pin (and
every trace via) wiII have to be looked at. The calculation for this is;

ac cost

Power cost

1(5VDC x Icc (mA)) x $1.00 per wattl/IC count

In addition to the more obvious costs, there are several
other items that contribute to the "hidden cost" of a
system.
PROGRAMMING LOSS

Because PALs are a one time programmable type of
device, full testing can't be done on them without de·
stroying the user's fuses. For this reason PALs have a
published programming loss of 2%[201. The cost for
this is:

(total pin count x $0.004)/IC count

2-207

Programming loss

(PAL IC count x 0.02) x PAL cost
per IC

AP-307

EPLDs, because they are based on EPROM cells, can
be programmed for different patterns, fully tested before customer delivery, and then erased. The result is a
near 100% percent programming yieId!22].
PROGRAMMING FEE,

Programming fee is the cost of programming a device.
While many companies have in-house programmers, it
is quite common for programming to be done by the
distributor. In some cases, and at low volumes, the programming may be done free of charge. However, at
larger volumes a programming charge is not uncommon. The charge varies with volume, programmer
availability and in general, your state of affairs with the
distributor. The cost for programming EPLDs and
PALs is the same per device and averages about $0.25
cents.

Let us assume that the production manager reduces
safety stock by a moderate amount, let's say 3%. In a
case like this,' usually the larger more expensive parts
are curtailed first. Since EPLDs provide good coverage
for work in progress and because they are more expensive by comparison, we can reduce the total safety stock
'to 2% and not compromise our safety margin. Because
TTL is inexpensive it tends to suffer more of the "gunshot" approach in testing!7]. This means that the useage rate is greater because production technicians tend
to replace TTL paris with more liberty. For this reason
let's leave the TTL safety stock as it stands. PALs
could be reduced, but faced with the fact that the programming yield is 2% and that internal modifications
can't be made, the production manager might decide
not to change the safety stock for PALs. These results
are shown in Table 5.
Table 5. Safety Stock

Programming fee = $0.25 cents

Unexpected
Events

SAFETY STOCK

Although this particular item was not mentioned in the
inventory section, it plays a very important role in the
production world. Safety stock!21] is extraICs ordered
to cover for unexpected events. Unexpected here might
be a large unforeseen customer order or simply a bad
batch of parts.

WIP
MODS
Total

TTL

. PAL

EPLD

10%

The safety stock calculation for each implementation is:

While industry seems to strive for the optimum JIT

Safety stock

(% of stock x IC type x Ie type 'cost)/IC count

Gust in time) production[t4][t6], which stresses minimal inventory until needed, it's not unusual for production managers to carry a five to ten percent inventory
buffer depending on the cosi of the part. In most cases,
the larger expensive parts like microprocessors, peripheral controllers, and other LSI devices are safety
stocked in smaller quantities.
Let's assume that the safety stock is to be a maximum
of 10%. Five percent might be used to cover for the
unexpected occurrences, and five for WIP (work in process) modifications. Since all parts have the same probability of unexpected events we can assign that percentage equally. Justifying the second 5% depends on the
IC technology itself. For instance, WIP modifications
usually require c~ts and jumpers on TTL, therefore it's
unnecessary to order the additional 5%.' In process
modifications to an EPLD are done simply by reprogramming it, here again there is no need for the additional 5%. PALs however cannot be cut and jumpered
(internally) nor can they be reprogrammed. Also, there
is the possbility that "on the shelf' PALs will be programmed in advance, therefore a WIP mod that impacts their function means that those parts must be
obsoleted Gunked). In this case, an additional 5% is
justifiable.

DE-COUPLING CAPACITORS

While adding caps solves many problems due to system
noise, it also increases the cost of PCB layout, PCB fab,
and adds an additional burden on all of our other costs.
For a TTL system, a good deccoupling rule of thumb is
to use one 0.01 /Lf per 'each synchronous driven gate
and at least 0.1 /Lf per 20 gates regardless of synchronicity. Engineers recognize the ne~d for decoupling and
usually take it a step further by using one capacitor per
IC. Most boards reflect this· practice, which, in itself is
very good. However, the addition of all these caps is
definitely measurable, in both component and systems
cost.
The average cost of a ceramic, capacitor in' moderate
quantities is about half a cent. For our comparison we
will .follow the accepted ,practice and de-couple each
TTL; PAL, and EPLD device., Our capacitor cost is
then:

2-208

De-coupling cost

$0.005 x Ie count

AP-307

--;.-- "ESCAPE"
$50

• STRUCTURED DIAGNOSTICS:
• LOW SKILL REQUIRED
• DIAGNOSTICS TIME
(SECONDS TO MINUTES) .:

• UNSTRUCTURED DIAGNOSTICS • SAME AS SYSTEM TEST
• HIGH SKILL REQUIRED
+
• DIAGNOSTICS TIME
• TRAVEL OVERH EAD
(MINUTES TO HOURS)
• "LOST" CUSTOMER GOODWILL

292030-15

Figure 10. Escape Costs

Other Costs To Consider

ENCLOSURE

EventuaJly, some place toward the end of a production
line, a board becomes part of a system. At this point it
is housed in an enclosure and all the necessary cabling
is done. Even here, however, the impact of using a particular IC technology can still be felt.

Certain applications require reduced packaging or enclosure size. In industrial control for example, each line
might require a complete system to monitor it's operation. In a case like this, a large bulky box fuJI of boards
might not be appropriate. A good example of the benefits that high integration logic provide enclosures, is the
third market versions of the popular PC. Many of these
companies have fuJly compatible versions that fit on a
single board. EPLDs and PALs are capable of providing a cost savings in this respect. However, while PALs
approach the density requirements, their large power
needs render them counterproductive to the low power
specs of smaJl systems. TTL is just not as effective as
either PALs or EPLDs. .

DEFECT ESCAPES

One very significant item that the test community acknowledges is the cost of "escapes"[4]. "Escape" is defined as a fault that goes through the early stages of
board test undetected. Figure 10 shows the escape relationship. An industry rule of thumb states that the cost
to detect a fault increases by an order of magnitude at
each stage. This means that if it costs $5 to find a fault
at the board test level, that same fault might cost $50 at
the system level and $500 at the field level. An important relationship to remember, is that the number of
faults per board increases 10garithmicaJly, as the number of components on the board increases[6]. The cost
of an "escape" is difficult to quantify, but generaJly, a
board with a higher component count has a greater
cost[2)[8].
CABLES/WIRING HARNESS

For our comparison let us assume the cost of enclosure
per chip is $0.75. The calculation is:
.
Enclosure cost

$0.75 x IC count

Table 6 shows the cable and enclosure costs for the
MULTIBUS I circuit. Although the results are based
on assumed values,. we can see that· a larger IC count
influences the burdened cost of the system. Our final
comparison will not use these figures, but they should
be considered.

When the number of components or the power requirements of a system are reduced, a reduction in cables
and wiring is usuaJly expected. The cost savings here is
either in the elimination of cables (because more functions are condensed into an IC) or the reduction of
cable gauge or length (because less power is required, in
the case of EPLDs). Also, fewer cables means fewer'
cable ties, connector pins, and mounting hardware.
While this is a subjective figure, lets assume that the
distributed cost of system cables is $0.25 per IC.
Cable cost

$0,25 x IC count

2-209

Table 6. Other Production Costs for
· Multibus I Circuit

Wiring/harness
Enclosure

TTL

PLA

EPLD

$2.750

$0.500
$1.500

$0.250
$0.750

$8~250

inter

AP-307

were done on a Lotus 1-2-3 worksheet that the individual engineer can modify with their specific values. The
worksheet is available, and can be downloaded from the
Intel EPLD bulletin board. Table 8 shows our calculation results for three years of production.

Arbiter Circuit Conclusion
A compilation of the cost variables for our comparison
is shown in Table 7a and 7b. Because the cost may
differ for each company, the comparison calculations

Inventory:

Costs
Incoming insp. ($/pin)
Storage ($/ sq.ft./yr)
Maintenance ($/part)
Processing ($/part type/yr)
Safety stock (%)

Manufacturing:

$0.010
$20.000
$0.030
$0.520
2%

Costs
PCB fab. ($/sq.in.)
Assembly ($/part)
Test ($/part)
Rework ($/pin)
QC ($/pin)
Power ($/watt)
Interconn
Program ($/part)
Caps. (each)

$0.200
$0.100 '
$0.150
$0.020
$0.004
$1.000
$0.020
$0.250
$0.005

(a)

Integrated Circuits
Component Count:
Package

DIP14
DIP16
blP20
PIP24

TTL

PLA
,

10
1
0

EPLD

ICs

Types

TTL

.10
2
1

PLA
EPLD

2
1

Circuit Requiremen~s:

Icc (max)

TTL circuit (total rnA).
PLA circuit (total rnA).
EPLD circuit (total rnA).

100
240
15

Interconnects
36

7
0

(b)
Tables 7a and b. Multibus Arbiter/Controller Cost Variables

2-210

intJ

AP-307

Table 8. MULTIBUS I Arbiter/Controller Production Costs
AVERAGE COMPONENT COST

DIP14
DIP16
DIP20
DIP24

TTL

$0.25
$0.35
$0.55

PLA

Year 3

Year 2

Year 1
Package

EPLD

TTL

$0.20
$0.30
$0.38

$2.00

PLA

EPLD

$1.70

$6.00

TTL

PLA

$0.19
$0.27
$0.35

$1.56

EPLD

$2.90

$4.20

PRODUCTION COSTS

Year 1
Item
(costs per part)

TTL

PLA

Year 3

Year 2
EPLD

TTL

PLA

EPLD

TTL

PLA

EPLD

Components

$0.259

$2.000 $6.000

$0.209

$1.700 $4.200

$0.197

$1.560 $2.900

Incoming Insp.

$0.142

$0.200 $0.240

$0.142

$0.200 $0.240

$0.142

$0.200 $0.240

Inventory
Maintenance
Storage
Processing

$0.027
$0.030
$0.473

$0.038 $0.045
$0.042 $0.050
$0.520 $0.520

$0.027
$0.030
$0.473

$0.038 $0.045
$0.042 $0.050
$0.520 $0.520

$0.027
$0.030
$0.473

$0.038 $0.045
$0.042 $0.050
$0.520 $0.520

Printed Circuit Board
Fabrication
Trace costs
Assembly
Board test
Rework
QC

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

$0.060
$0.Q70
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

$0.060
$0.070
$0.125
$0.150
$0.020
$0.080

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.043
$0.065
$0.089
$0.150
$0.014
$0.057

$0.060
$0.070
$0.125
$0.150
$0.020
$0.080

Power Supply

$0.045

$0.600 $0.075

$0.045

$0.600 $0.075

$0.045

$0.600 $0.075

Total Cost/Part

$1.393

$3.904 $7.422

$1.343

$3.604 $5.622

$1.331

$3.464 $4.322

Total Cost/System

$15.321 $7.808 $7.422 $14.771

Additional Costs/System
Programming loss
Safety stock
Programming fee
De-coupling caps

$0.000
$0.143
$0.000
$0.055

True mfg. cost/system

$15.518 $8.798 $7.797 $14.941

$0.080
$0.400
$0.500
$0.010

$0.000
$0.120
$0.250
$0.005

$0.000
$0.115
$0.000
$0.055

.2-211

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$7.208 $5.622 $14.641 $6.928 $4.322

$0.068
$0.340
$0.500
$0.010

$0.000
$0.084
$0.250
$0.005

$0.000
$0.109
$0.000
$0.055

$0.062
$0.312
$0.500
$0.010

$0.000
$0.058
$0.250
$0.005

$8.126 $5.961 $14.804 $7.813 $4.635

inter

AP-307,

The comparison in component costs shows that the
EPLD costs more than either a TTL or PAL Ie; As
costs are added, the figures for TTL and PALs begin to
approach the cost of an EPLD. These are shown on the
line labeled "Total cost/part".
The "Total cost/system" line shows the actual cost
when all the les are considered. For the first year, the
TTL version is the more expensive implementation, and
the EPLD numbers look'very favorable.
'
The "True mfg. cost/system'; line results after additional costs are figured in. Here we see that the first
year, the EPLD version already provides a $1 savings
,over the PAL' version, and that the cost of the TTL
implementation is very high. Also, the inserted cost per
Ie at this point is, $1.15 for TTL, $2.40 for PAL and
$1.80 for the EPLD. This is in line with the inserted
costs that we mentioned earlier.
The production costs for two additional years shows
that the decreasing price of EPLDs (based on the curve
of Figure 5) will continue to provide costs savings as
production ramps up in quantities.
In' terms of functional benefits, the EPLD implementa- '
tion is the most beneficial because';
• The chip ,count has gone down, one EPLD has replaced 11 TTL les in one implementation, and 2
PALS in the other, reducing the cost ,and time of:
-board layout
'
-board fab
, -assembly
, -rework
• The reliability of the board has increased. Fewer
components translates into less probability of error.
• 'Modifications are easier to make. Instead of cuts'
and jumpers (for TTL); or throwing away a PAL, a
change is re-program~ed.
• The need for de-coupling caps is reduced. All those '
individual les are eliminated and in some cases the
, distributed capacitance of the board may be enough
de-coupling.

'. Power s,upply requirements are small:· The active'
current requirements are much smaller with
EPLDs. This in turn reduces the, need for large power supplies and fans. ' '
• Cable requirements and enclosure benefits have been
improved. Since EPLDs, provide better, integration
over TTL and PALs, the size of the system will be
smaller. This translates into fewer boards and cahies.
• Inventory is reduced. One EPLD replaces many
TTL devices. Also, "on the shelf' programmed
EPLDs can be reused in a pinch, PALs can't.
Less expense and probability of "escapes". The time
and cost of finding and fixing escape problems is re-

duced to one reprogrammable Ie. In the field, this
translates into less "down time" for the customer and a
higher level of customer "goodwill" for the OEM.
Allows capability for customized hardware. Specific
customer requirements can be implemented. Also, DIP
switches and configuration jumpers may not be necessary iri many cases, since configurations can be programmed into the Ei>~D.

Development Costs
As mentioned earlier, the costs of development are usually dismissed as NRE. One reason for this is the difficulty in pegging down these costs. However, while
money might be expendable at this stage, time is usual"
ly critical. Time saved at the front end can make a
difference in beating the competition to market. The
following'topics are presented for consideration. Nq
costs, are assigned to them.

RESEARCH,
The' amount of time spent researching components"
,component sources, and technical data can be very,
large. Designs done with a large Ie count require more
re~earch and analysis time. Higher integration devices
require learning curve time, but, in the, long run this
tends to reduce research time, especiallY'In future de'sigus: '
PROTOTYPlNG

For most companies, protqtypes are three to five level
wire wrap boards built by inhouse technicians or outside contractors. During prototype fab, a certain
amount of work has to be done to each Ie. Part of this
, work is, adding bypass caps, labeling chips, and lead
forming. In smaller companies, the board might be
hand' wrapped. Larger companies might use anautoc
matic wrapper. Once the board is wrapped, a continuity
check is done on each wire net to insure connections
and minimize shorts.
',
The turn around time for a protoboard is one to two
weeks and can be shortened by paying a premium price.
, An alternate way of shortening this timds to simplify
the board by using denser les.
'
DEBUGGING

Fixing bugs on a protoboardinvolves unwrapping and
wrapping connections, as well as replacing les. Making
mods on a TTL boarel is very time consuming and error
prone due to the large numbers of wires. Making mods
with PALs is expensive since the part usually has to be'
junked. EPLDs in contrast, are re-programmable and
lend themselves to all the revisions that are common in
the early design stages.

2-212

intJ

AP-307

t---QClR

'----dl

Cll

ac cIa C
U3
lS162

U6
lS42

ClK
5V

....+-+-c:lClR
aD

U2
lS 162

C7
C6

C
U5
lS42

vco

0-.....-+--1 ClK

t-+--QClR
aD

Ul
lS162

ClK

P T

C3
C2

U4
lS42

aA co

lS112

C
lS32

A
L-__
~~----~

5Vo---.....J
292030-16

,.,-- SYNC PULSE

T~JLr~~~~~~ ~

fl~____~--.Jrl~______~fl~______--.Jrl~________~~

U9-PR

U9-ClR
WI
U9-PR
U9-ClR

--U

W2-1l_______________________________________________________

u---

~-------~
292030-17

Figure 11. Time Window Generator, TTL Circuit
2-213

AP-307

WINDOW CIRCUIT

PCB LAYOUT

Artwork quotes are based on several factors. These are,
board size, number of 16-pin chip equivalents, pad
count, and the chip to board packing ratio. The chip
equivalents are calculated by taking the total lead count·
(lCs and discretes) and dividing by 16. Pad count is the
number of holes in the board. The packing ratio determines how much room an IC has around it. This is
critical because space is needed to place sockets, vias,
and trace bends. Currently, most service bureaus consider 0.75 square inches per IC to be the minimum
packing density. This figure applies to DIPs only, other
packages like SMT (Surface Mount Technology) will
.improve on this. However, for standard DIPs anything
less than this might push the board into a multi-layer.
During schematic evahi:iltion, the bureau doesn't usually charge for traces directly. Because they can't foresee
the exact count, and they don't have time to count
them on the sheets, they make a judgment based on
previous jobs. If the board appears to be tight, their
autorouter (CAD based) won't be as efficient, and more
hand layout will have to be done. However, as more
CAD based service bureaus integrate schematic capture
front ends, the cost of traces and vias will be more
visible.
Because the evaluation is subjective, the final cost varies; and is a combination of charges. However, because
pad count can be determined easily, the overall price is
usually gauged against Ii pad price.

Background Information
In applications that involve time-division multiplexing,
it is useful to have a circuit that windows a specific area
of the bit stream [271. The circuit of Figure 11 is a TTL
implementation of such a circuit. The idea is to count
time slots from a known reference and at a certain decode, set and .clear a latch. The output of the latch is
the time window, which might be used for further gating in other parts of the circuit. The TTL parts list is
detailed in Table 9.
The PAL alternative of Figure 12 is comprised of two
16L8s and one 16R4. While the component count has
been reduced frpm nine to three, there are still fourteen
extra interconnections.
One 5C060 is needed to integrate the complete circuit.
Fourteen out of the sixteen EPLD macrocells are used,
and exernal traces are only the three I/O pins as shown
in Figure 13.

Production Costs
The production variables for the window circuit are
shown in Table lOa and lOb, and the production costs
in Table 11. The comparison shows three years of system costs for each implementation.

2-214

intJ

AP-307

Table 9. TTL Component List for Window Generator
IC

Type

DIP

Icc{mA)

Area{ln 2)

U1
U2
U3
U4
U5
U6
U7
U8
U9

LS162
LS162
LS162
LS42
LS42
LS42
LS32
LS32
LS112

16
16
16
16
16
14
14
14
14

32
32
32
13
13
13
9.8
9.8
6

.24
.24
.24
.24
.24
.24
.21
.21
.21

.49
.49
.49
.39
.39
.39
.18
.18
.29

___ VCO
~

tt-

ot-U2

0
16RB 0

Cl0
C9
CB

0
0

-I

Cll

0
RCO

ooW

-I

0
Ul
16RB

C6
C5

C4
C3

0
0

Cl
CO

0
0

1
1
1
1
1
1

U3
16R4

1
1
1
1-

Wl_

0
0

I
I

::=:::

Figure 12. Time Window Generator, PAL Circuit

VCO

vee

ClKl

I/O
WI
W2
I
GND

ClK2
292030-19

Figure 13. Time Window Generator, EPLD Circuit

2-215

292030-18

inter

AP-307

Inventory:

Costs
Incoming insp. ($/pin)
. Storage ($/ sq. ft.lyr)
Maintenance ($/part)
Processing ($/part type/yr)
Safety stock (%)

Manufacturing: .

.$0.010
$20.000
$0.030
$0.520
2%
.Costs

PCB fab. ($/sq.in.)
Assembly ($/part)
Test ($/part)
Rework ($/pin)
QC ($/pin)
Power ($/watt)
Interconn
Program ($/part)
Caps; (each)

$0.200
$0.100
$0.150
$0.020
$0.004
$1.000
$0.020
$0.250
$0.005

(a)
Integrated Circuits
Component Count:
Package
DIP14
··DIP16
DIP20
DIP24

TTL

PLA

EPLD

3
6
3

ICs

Types

TTL
PLA
EPLD

4
2
1

Circuit Requirements:

ICC (max)

TTL circuit (total rnA).
. PLA circuit (total rnA).
EPLD circuit (total rnA).

!I"!terconnects

160
360
15
(b)

Tables 10a and b. Window Circuit Cost Variables

2·216

52
14
0

inter

AP-307

Table 11. Window Circuit Production Costs
AVERAGE COMPONENT COST

Year 1
Package

DIP14
DIP16
DIP20
DIP24

TTL

PLA

Year 3

Year 2
EPLD

$0.22
$0.44

TTL

PLA

EPLD

$0.19
$0.37
$2.00

TTL

PLA

EPLD

$0.17
$0.26
$1.70

$6.00

$1.56
$4.20

$2.90

PRODUCTION COSTS

Item
(costs per part)

TTL

PLA

Year 3

Year 2

Year 1
EPLD

TTL

PLA

EPLD

TTL

PLA

EPLD

Components

$0.367

$2.000 $6.000 $0.310

$1.700 $4.200 $0.230

$1.560 $2.900

Inco~ing

$0.153

$0.200 $0.240 $0.153· $0.200 $0.240 $0.153

$0.200 $0.2:40

Inventory
Maintenance
Storage
Processing

$0.029
$0.032
$0.231

$0.038 $0.045 $0.029
$0.042 $0.050 $0.032
$0.347 $0.520 $0.231

$0.038 $0.045
$0.042 $0.050
$0.347 $0.520

Printed Circuit Board
Fabrication
Trace costs
Assembly
Board test
Rework
QC

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.060
$0.093
$0.125
$0.150
$0.020
$0.080

Power Supply

$0.089

$0.600 $0.075 $0.089

$0.600 $0.075

Total Cost/Part

$1.385

$3.754 $7.422 $1.328

$3.454 $5.622 $1.248

$3.314 $4.322

Total Cost/System

$12.463 $11.263 $7.422 $11.953 $10.363 $5.622 $11.233 $9.943 $4.322

Additional Costs/System
Programming loss
Safety stock
Programming fee
De-coupling caps

$0.000
$0.165
$0.000
$0.045

True mfg. cost/system

$12.673 $12.748 $7.797 $12.137 $11.740 $5.961 $11.381 $11.269 $4.635

Insp.

$0.120
$0.600
$0.750
$0.015

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.000
$0.120
$0.250
$0.005

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.000
$0.140
$0.000
$0.045

2-217

$0.102
$0.510
$0.750
$0.015

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.000
$0.084
$0.250
$0.005

$0.046
$0.116
$0.096
$0.150
$0.015
$0.061

$0.000
$0.104
$0.000
$0.045

$0.094
$0.468
$0.750
$0.015

$0.072
$0.000
$0.150
$0.150
$0.024
$0.096

$0.000
$0.058
$0.250
$0.005

inter

Ap-307

The production costs again show that the system cost
for the first year is better with EPLDs. The two consecutive years show that the declining price of EPLDs
make them an excellent candidate for systems that will
ramp up production at that time.

Window Circuit Conclusion
The TTL version of the circuit was implemented with
MSI counters and decoders. As a result, the PAL implementation was bound by the number of count bits
and had to be programmed into two PALs. In circuits
like this, it is useful to rewire the decode for different
counts depending on the application. ThePAL implementation allows this by incorporating the decode and
output latches into one IC.
The EPLD implementation tackles the MSI integration
quite easily ,and also provides the capability to reprogram the decoder. Since the counter and output latches
consist of fourteen registered outputs, the sixteen macrocells of .the 5C060 easily accommodate the needed
functions.

SUMMARY
We have examined the hidden costs of production and
how they differ for several logic alternatives. By examining these costs, we have shown that while an EPLD is
presently a niore expensive part, it's level of integration
reduces system costs anq improves reliability. The following items should be considered when evaluating logic alternatives:
• system cost is determined by more than component
cost
• system cost and reliability is influenced by the type
and amount of components used

2. Reducing The Cost of Quality Through Test Data
Managment.
Paul N. Manikas, GenRad Inc.
Stephen G. Eichenlaub, Harvard University.
IEEE International Test Conference Proceedings,
1983
'
3. A Quantitative Analysis Of The Trade-offs Between
Higher Capital Investment and Higher Yield In PCB
Testing.
Mark A. Myers, Teradyne Inc.
IEEE International Test Conference Proceedings,
1984
4. An Analysis Of The Cost And Quality Impact Of
LSI/VLSI Technology On PCB Test Strategies.
Mark A. Myers, Teradyne Inc.
IEEE International Test Conference Proceedings,
1983
5. IC Quality Control By The User.
Roger Dunn, Xerox Corp.
IEEE International Test Conference Proceedings,
1983
6. An Analysis Of The Economics of Self Test.
P. Varma, University of Manchester.
A. P. Ambler, University of Manchester.
K. Baker, GEC Research Labs.
, IEEE International Test Conference Proceedings,
1984
7. In Circuit Testability Factors: Shoot With A Rifle.
Douglas W. Raymond, Zehntel Production Services. '
IEEE International Test Conference Proceedings,
1984
8. Seven Steps To Zero Defects.
D. W. Rudd, AT&T Technologies.
Circuits Manufacturing, June 1986
9. Rework Forum
Donald Ford, Senior Editor.
Circuits Manufacturing, September 1986

• semiconductors have a life cycle that determines
their present price at design, and at production time

10. Manufacturing, Defect Analyzers: Annual Roundup.
Evaluation Engineering magazine, August 1986

In summary, when all' system costs are ,consideted,
EPLDs can provide cost savings to the design anel production of most board designs.

11. Assembly: Automation Makes It Better.
Roland W. Roy and Gordon Weeks, Andover Controls.
Circuits Manufacturing, February 1986

REFERENCES

12. Shrinking Lines Squeeze Processes.
Jerry Murray, West Coast Editor.
Circuits Manufacturing, SePtember 1986'

1. The Future Is Now: Extending CAE into test of custom VLSI.
.
Robert S. Broughton, Tektronix.
Michael G. Brashier, Tektronix.
IEEE International Test Conference Proceedings,
1984

13. Ribbon Cable for Reliable Interconnections.
Bennett W. Brachman, Xport Trading Inc.
Electronic Packaging and Production magazine,
July 1986

2-218

inter

AP-307

14. TQC and JIT: Partners In Production.
Rick Walleigh, Hewlett Packard.
Circuits Manufacturing, February 1986
15. Automated Handling/Sorting: Multisite Development Moves to Back Burner.
Evaluation Engineering magazine, May 1986
16. Software Charts The Course of Component Testing.
Ronald Pound, Editor.
Electronic Packaging and Production magazine,
June 1986
.
17. Complexity, PLDs Drive The Market.
Evaluation Engineering magazine, July 1986
18. Intel User Defined Logic Handbook.
Intel Corp. 1986
19. VLSI Semicustom Design Guide.
CMP Publications, Summer 1986
20. AMD Programmable Array Logic Handbook.
Advanced Micro Devices, 1984

21. Handbook Of Industrial Engineering.
Gavriel Salvendy, Editor, Purdue University
John Wiley & Sons Publications
22. Components Quality/Reliability Handbook.
Intel Corporation.
23. The Cost Edge.
DM DATA Corp.
Scottsdale, AZ
24. Semiconductor Purchasing Strategies Integrated
Circuits Engineering Corp.
Scottsdale, AZ
25. Status 1986 Integrated Circuits Engineering Corp.
Scottsdale, AZ
26. EDN
EDN
27. EDN
EDN

2-219

Semicustom Design Series
Magazine, 1985
Design Ideas
Magazine, 1985

APPLICATION

AP-321

NOTE

November 1988

Fitting the 5C180

TODD KOELLING
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292053-001
2-220

inter

AP-321

INTRODUCTION
In many ways, fitting the SCI80 is like climbing a
mountain .. Just when what appears to be the summit is
reached, another summit is revealed behind it. This
may occur several times before the actual summit is
surmounted.
Likewise, fitting a SCI80 may have several false summits. Just when one has conquered what appears to be
the "problem", another problem often appears behind
it. This may occur several times before the design fitting is complete.
This application note addresses the problems that can
be encountered when trying to fit a SCI80 and offers
suggestions on how to get past them. The key to the
climb is examining what resources are still available
after the software' complains that a particular resource
is not available.

QUAD A REGISTERS
aA

SUMMIT NUMBER ONE: PIN
ESTIMATE
Before keying in the design, it is best to estimate the
1/0 pin requirements. This is done by counting the to-

tal number of inputs to the device and outputs from the
device.
PROBLEM: Not

eno~gh

Input Pins

HELP: Run all synchronous clocks through Clock
Buffers (CLKBs). Shared clocks may use the same
CLKB output which may result in reduction from 4
CLK input pins to I CLK input pin (see Figures la &
'iPLS II ver. 1.1 or later is ESSENTIAL for 5C180 designs as the fitting
algorithm was significantly improved with this release.
'iPlS II ver. 1.5 or later is HIGHLY RECOMMENDED as the error
messages and Utilization Report Files were significantly enhanced
with this release.

QUAD D REGISTERS
aD

RON,

ClK1 PIN
INP
ClK1
ClK4PIN
INP
. ClK4

ClK3PIN
INP
ClK3
ClK2PIN
INP
CLK2

RON,

QUAD B REGISTERS

QUAD C REGISTERS
292053-1

Figure 1a. Summit One-Input Clocks Before
2-221

AP-321

QUAD X REGISTERS

ClK4PIN
INP

ClKS

ClK4

ClK3PIN
INP
ClK3

ClKS

RONF

QUAD X REGISTERS

QUAD X REGISTERS
292053-2

Case:

ClK!
ClK2

ClK4 frequency
ClK3 frequency

Figure 1b. Summit Two-Input Clocks After

1b). This also frees the registers thai the clock feeds
from the synchronous clock pin quadrant, increasing
the chance of fitting later on. THIS PRACTICE IS
RECOMMENDED FOR ALL DESIGNS.
PENALTY: Input setup time is shortened. (See Synchronous vs. Asynchronous A.C. Characteristics in
Data Sheet).
If clock buffering cannot solve the problem, the design
must be repartitioned to reduce the number of input
pins. Repartitioning is explained in the next section.

SUMMIT NUMBER TWO: MACROCELL
ESTIMATE
If the I/O pin requirements can be met, the next step is
to consider the macrocell requirements. The total macroce1l count can be estimated by counting the number
of outputs plus the number of internal registers.

PROBLEM: Not enough macrocells
REPARTITIONING: Unless the fundamentals of th~
. design can be changed, this error means that the design

2-222

Ap·321

must be repartitioned. This is done by removing part of
the circuitry and placing it in a second device such as a
SC060 or SC090. The SC060. and SC090 are recommended since their architectures (and therefore their
ADFs) are nearly identical to those of the SCI80 (the
NOCF and COCF primitives are the only exceptions).

FIX: In order to tell the LOC software that the clock
for a flip-flop will be driven by an equation or gate
logic, a Clock Buffer (CLKB) must be placed between
the equation or logic and the register clock input for
each register that is asynchronously clocked.

Portions of the SCI80 ADF can be easily transferred
into one of the smaller devices or the smaller device
ADFs can be transferred back to the SCI80 if sufficient
room is freed up later on. IT IS RECOMMENDED
THAT FOUR OR FIVE UNUSED MACROCELLS
BE LEFT IN THE SCI80 FOR USE BY LATER
STAGES.

SUMMIT NUMBER FIVE:
ASYNCHRONOUS CLOCKS AND
OUTPUT ENABLES

SUMMIT NUMBER THREE:
SUCCESSFUL TRANSLATION
With the design entered, the. next summit is successful
translation.
ERROR: ***ERR-MAC-No macrofunction for: ...
EXPLANATION: The Macro Expander Module cannot find a macro for a network element.
FIX: Make sure correct search path is available for
macro libraries. Check for typo or syntax error. Ifusing
schematic capture, make certain that only valid EPLD
library symbols were entered.
ERROR: Any "***ERROR-XLT-... "
EXPLANATION: The Translator found a problem
with the way the design was entered. These errors are
basically syntax errors which violate ADF format. It
may be a simple typo, missing parenthesis or missing
semicolon. Remember that the iPLS II LOC does differentiate between upper and lower case letters. If using
schematic capture, make sure that all device inputs and
outputs have pin symbols and that all the pins and
wires are properly labeled.
FIX: Refer to your iPLS II manual or call the EPLD
Hotline, 1-800-323-EPLD, for help on the tough ones.

ERROR: ***ERROR-XLT-OE with asynchronous
clock not allowed
EXPLANATION: . Asynchronous clock and output
enable can't be used at the same time in the same macrocell. The SCI80 basic macrocell architecture, Figure
2, shows why. A single p-term is shared between the
asynchronous clock and the output enable. This means
that both switches in the diagram can be up or both
switches can be down. By trying to use a p-term output
enable with an asynchronous clock, the top switch
would have to be down while the bottom switch is up.
This cannot be done as then the register would be
clocked and enabled with the same signal.
WORKAROUND: To get around this problem, one of
the signals must be routed through another macrocell
(see Figures 3a-b). The clock could be generated in another macrocell, sent out to a pin, then sent back in on
the synchronous clock pin. Alternately, in a first macrocell the register is placed as an asynchronously
clocked NORF. In a second macrocell, the register
feedback is sent out to a pin using a CONF enabled by
the desired enable signal.
PENALTIES: Routing the clock through a separate
macrocell and back in offers slightly better performance-since the synchronous clock to ouput time is
faster than a second macrocell delay, but this implementation uses a lot of resources-three pins and two
macrocells. The second method, routing the feedback
from the register back and controlling the 'output enable in a second macrocell is more straightforward and
uses less resources.

SUMMIT NUMBER FOUR: REGISTER

CLOCK INPUTS

SUMMIT NUMBER SIX: GREATER
THAN ONE PRODUCT·TERM
REGISTER CONTROLS

ERROR: ***ERROR-XLT-Clock input must be driven by INP or CLKB

ERRORS: *"INFO-FIT- Eqn.
PTerm(s), on OE signal OE3

EXPLANATION: The clock for a flip-flop must be
driven synchronously by a direct quadrant clock pin
input (INP) or asynchronously through a Clock Buffer
(CLKB). This problem occurs when an equation or
gate logic is connected directly to the register clock·
input.

***INFO-FITCLEAR input (CLRI)

Illegal

too

big,

inversion

4/-1
of

EXPLANATION: As shown in the basic SCI80 macrocell architecture, Figure 2, only one product term
(multiple input AND gate) is available for the register

2-223

intJ -

AP-321

clock, clear, and output enable. This means that any
control resource containing an.OR gate following Boolean minimization will not fit. Likewise, any control
resource requiring an invert will not fit either. To find
the offending signal, LOOK AT THE EQUATIONS
SECTION OF THE LOGIC EQUATION FILE
(.LEF).

Clr Fitting Trick

WORKAROUND: Once the offending signal has been
located, it must be routed through another macrocell
using an NOCF primitive (see Figure 4a-b). If the control signal is a clock, then a clock buffer (CLKB) must
also be added.

EXPLANATION: D-type EPLD register has only
AND gate feeding CLR; SR Flip-Flop utilizes logic array for CLR input allowing a max of 8 AND gates
(p-terms) for the CLR resource.

PROBLEM: Register clear input breaks 1 p-term resource limit
.
TRICK: If register has D input of either VCC or
GND, substitute SR Flip-Flop.

PENALTIES: SR Flip-Flop is synchronously clocked.
D register has asynchronous clear.

PENALTY: Unless a trick explained below can be
used, this routing results in the. use of an additional
macrocell and a doubling of the signal propagation de-'
lay.

AND ARRAY

SYNCHRONOUS
CLOCK

vcc

OE/ClK
SELECT

-.
-

OE/ClK

D- -{ -

ClK

- -

EPROM

PRODUCT
TERM

CEll
ONNECTION

gjb S·~'-···~
lOGIC

INVERT

~1~£-K]
~" :=~
D-

I/O

SELECTION

RESET

!II

FEEDBACK SIGNALS

INPUTS AND I/O

292053-3

Figure 2. Basic Macrocell Architecture of the 5C180

2-224

AP-321

1 0

2
AN02

ClKS

1
2

EN
ClK

292053-4

Figure 3a. Summit Five-Asynchronous Clock and OE Before

DE
FF1
NORF
01
2
AN02
EN
ClK

ClKS

2
CONF
292053-5
(Recommended Method)

Figure 3b. Summit Five-Asynchronous Clock and OE After

AN03

4
2
3

7474X
Q

Cl
AN03

TOO MANY P - TERMS
FOR CLEAR RESOURCE

292053-6

Figure 4a. Summit Six-Too Many P-Terms on Control- Clear

2-225

inter

AP-321

o
4

1 S

NOSr

2
3 R

AND3

c
4

292053-7

Figure 4b. Summit Six-5R Flip-Flop Equivalent Implementation

OE Fitting Trick
PROBLEM: Output enable on an equation or combinational equation exceeds I p-term resource limit.
TRICK: If a low output rather than a tri-state output
can be tolerated, the signal can be gated .rather than tristated.
EXPLANATION: Run the OE and the equation
through an AND gate before going to a pin. The output·
of the pin will only follow the equation when the enable
is active, otherwise it will be zero.
PENALTY: Forced low rather than tri-state output.

SUMMIT NUMBER SEVEN: NOT
ENOUGH P-TERMS FOR AN
EQUATION
ERROR: "'INFO-FIT- Too many PTerms to fit in
any MCeIl: 10/8 for EQN.
EXPLANATION: Since the 5CI80 has a maximum of
eight product terms per macrocell, there's a chance that
this number may be. exceeded by the requirements of an
equation. Ie's(), the equation is cited by the LOC and
can be examined by looking at the EQUATIONS section of the .LEF.

WORKAROUND: The workaround for this situation
may already be in place! If any portion of the logic (or
equation) is routed into an NOCF or CONF elsewhere
in the design, that feedback can be taken and routed
into the equation (see Figure 5a-b). This means a single
feedback node-rather thai! several nodes will now feed
the equation and thereby reduce the p-term count. (If
the feedback is to be taken from a CONF primitive, the
CONF must be changed to a COCF or COIF to make
the feedback available.)
If part of the . logic or equation is not routed into a
NOCF or CONF elsewhere in the design, then part ()f
the equation must be routed through a NOCF, COCF,
or COIF primitive. A NOCF is recommended as it does
not use a pin if placed in a global macrocell. If several
equations are in violation of the eight p-term maximum, try to choose a group of logic that is common to
all of the equations. In this manner, the p-term count
for several equations can be brought down with the use
of single extra macrocell, rather than the use of a macroceIl for each equation.

PENALTY: Any time a portion of an output signal
must be routed through another macrocell a speed penalty is incurred (roughly one prQpagation delay). If an
already existing macrocell can be found, then there is
no architectural penalty. If a new one must be created,
then another macrocell is added to the total macrocell
count.

2-226

intJ

AP-321

PTERMS _ _ _ _ _ _ _::.1
1
PTERMS -----.....,-~~::
PTERM4 ------"'""""4:H
PTERM3 --"'""""---~S""
PTERM2
PTERM1-------.::..j

r - -......---"'"i

PTERM9 -------~~
PTERM8 -------4>?-1
PTERM7

r----"'"i >--c> EQNB

-------'"'st

~>--I~ EQNA

6 P - TERMS

CONF

------.....;::.r-

9 P-TERMS

CONF
292053-8

Figure 5a. Summit Seven-Too Many P-Term Equation Before

PTERMS ---""';---::.1
PTERMS --------~~.
PTERM4 - - - - - - - : H
PTERM3
PTERM2 -------~
PTERM1-------l4

-------;H

---------H

PTERM9
PTERM8 -------"!:...J
PTERM7 -------~-

r - -......-"'i

~_-(=> EQNA

6 P - TERMS

coeF

).:-----!.I

">--r> EQNB

4 P - TERMS

CONF
292053-9

Figure 5b. Summit Seven-Too Many P-Term Equation After

SUMMIT EIGHT: MACROCELL
RESOURCES EXC~EDED

THE FINAL ASCENT: NOT ENOUGH
GLOBAL FEEDBACK!

ERROR: "*INFO-FIT- Design' requires too many
macrocells

Congratulations! If you have made it this far, you have
demonstrated courage, intelligence and tenacity beyond
that of the average climber. You will soon be rewarded,
but first there is one more obstacle to be overcome.
Welcome to the North Face of local/global feedback!

EXPLANATION: If this error didn't occur at the beginning, there's a good chance summits five, six or sev~
en will push the macrocell count over the limit. (Remember that the macrocell count includes not only the
outputs, but also the buried resources such as NOCFs,
NORFs and NOTFs). To find out exactly how many
macrocells the design requires, LOOK AT THE NETWORK: SECTION OF THE LOGIC EQUATION
FILE (.LEF). The inputs list in the LEF will list both
the outputs and all the buried resources required by the
design. If the count exceeds 48, then too many macrocells are required.
FIX: Repartition. The same applies if the number of
input pins is exceeded.

A Word About Local/Global Feedback
First of all, why does local/global feedback exist? The
answer can be found in, the graph shown in Figure 6.
The propagation delay versus array size is shown for
the 5C060/090/180 family. As the number of inputs'
into the array increases, the propagation delay increases ... exponentially. If all the inputs and feedback were
made global, the 5CI80 would have 136 inputs feeding
each array (remember that both true and complement
polarities must be fed into the array of a PLD architec-

2-227

inter

AP-321

ture). This would have put the 5Cl80 Tpd in the 250 300 ns range! By making eight macrocells local for four
quadrants, the number of array inputs was dropped to
88 and the Tpd subsequently decreased to 75 ns.
The tradeoff to the local!global routing scheme is more
difficult design routing. With the help of the iPLS II
and a couple of tricks, however, most designs' can still
.
be fit.

70
60

.."

...a.

..,

where GLOBAL means that the signal feeds all macrocells and LOCAL means that the signal only feeds the
macrocells in its quadrant.

Clock Input Pins
The clock input pins feed the global bus like the regular
inputs, except the synchronous register input connec"
tion is dedicated to a particular quadrant. Thus, each
clock input can be used as a logicinput in all quadrants
or a clock input in its own quadrant. To be used as a
register clock input in a quadrant outside its own, however, it must be tapped from the global bus via an asynchronous clock buffer (CLKB).

Total
90
Propagation 80
Delay
~

4. Local macrocell pin/feedback paths are LOCAL.

Global Macrocell Feedback

The feedback path is local for GLOBAL macrocells
while the I/O input is global for all GLOBAL macrocells. Thus, changing the feedback of a register or combinational equation from a standard feedback to I/O
pin feedback path will change the routing from local to
global. The iPLS II LOC automatically recognizes and
performs this through a process called "promoting".
With the promotion process, global routing can be obtained on signals that would otherwise remain local.

20
10
0
0 10 20 30 40 50 60 70 80 90

# OF ARRAY INPUTS
'292053-10

Array Size
Device

5C060
5C090
5C180

Array
Inputs

40
72
88

TpD

***INFO-FIT- Promoted "TEQNP' from NOCF to
COIF

45n8
Sans
75 ns

Array size increases Capacitance
Capacitance increases Propagation Delays

Burying a Register in a Global Cell

Figure 6. Propagation Delay vs. Array Size for
the 5C060/090/180 Family

A Few Notes
The global!local macrocell assignments are shown in
Figure 7. Please note that:
1. Dedicated input pins are GLOBAL.
2. Global macrocell I/O pin are GLOBAL.
3. Global macrocell internal feedback paths are LOCAL.

Because the global macrocells have separate register
and I/O pin feedback paths, it is possible to "bury" a
register or equation by disabling the output buffer and
still use the pin as an input. The iPLS II LOC automatically assigns an 'input to the pin of a buried register
macrocell if it is necessary and possible. Such assignments are documented in the Utilization Report File
(.RPT). If manual assignment is desired, it may be performed by placing the input pin assignment in the ADF
INPUTS: list and assigning the buried register feedback
tothe same pin in the, OUTPUTS: Jist (Figure 8). Registers or equations can only be buried on global macrocells, since local mlwrocells only have one feedback
path that is used for either the register or the pin feedback.

2-228

intJ

AP-321

QUADRANT A

QUADRANT D

QUADRANT B

QUADRANT C
292053-11

GENERAL MACROCELLS
GLOBAL MACROCELLS
ENHANCED MACROCELLS
Figure 7. 5C180 Block Diagram

2-229

AP-321

Vee
INP
INP@10D---

F
FBK@10
292053-12

Buried Register Pin Assignment in ADF

Intel
PLDO Apps·
July 27, 1988
5C180 Buried Reg Pin Assignments
PART: 5C180
INPUTS: A@15, B@lO, CLK@17
OUTPUTS: FBK@lO

% Assign input B to pin 10 %
% Assign buried reg feedback FBK %
% to pin 10 (GLOBAL macrocell 9) %

NETWORK:
A = INP(A)
B = INP(B)
CLK = INP(CLK)

% Inputs %

FBK = NORF(IN,CLK,GND,GND)

% Buried Register %

EQUATIONS:
IN = A

% Register Input Equation %

FBK;

END$
Figure 8. Assigning Buried Reg in Schematic

TWo Global Fitting Tricks
If the LOC is unable to fit the design, there are a couple
of manual tricks that may help:
PROBLEM: NOT ENOUGH GLOBAL FEEDBACK

PENALTIES: There may be a slight timing discrepency between the two macrocells for combinational logic,
but any discrepency will be small « 2 ns);
PROBLEM: NOT ENOUGH GLOBAL FEEDBACK
RESOURCES AVAILABLE: EXTRA INPUT PINS

RESOURCES
CELLS

AVAILABLE: EXTRA

MACROTRICK: Send out the signal that needs to be global and
externally connect it to one of the input pins.

TRICK: Duplicate the macrocelliogic that needs to be
global in two (or more) regions with appropriate renaming (see Figure 9).

EXPLANATION: Inputs feed the global bus, making
the signal available in all quadrants.

EXPLANATION: This makes the signal available in
two regions via two local macrocells rather than one
which can't be global.

PENALTIES: An output buffer plus input buffer minus feedback delay is added (approximately 25 ns). An
external coimection must be made on the board.

2-230

inter

AP-321

NOTE:
For the previous tricks, look at the Utilization Report
(.RPT) file. The "Interconnect Cross Reference" is
particularly useful for examining the routing requirements of the design.
If the previous tricks cannot be done (see Figure 11)
and scrutinization of the Interconnect Cross Reference
reveals no other way to achieve the desired routing,
repartitioning is necessary. That is, place a chunk of
interconnected logic into a 5C060 or 5C090 and go
back to the start.

CONCLUSION
Fitting the SCl80 is a process with many stages. One
difficulty may hide the next and fixing one problem will
sometimes uncover another. Equipped with the iPLS II
LOC and a few tricks, however, fitting can be accomplished.

A1
AND2

7474X

2 D

QUAD 8
2

Q 6

C
CL

QUAD 8

~
OR

' -_ _ _ _~1

________________________

~----~2

.2
1

CONF
292053-13

AND2
2

4
1 OR3
2

7474X

2 D

QUAD C
3

QUAD C
OR2

o
CONF
292053-14

Figure 9. Not Enough Global Feedback Extra Macrocells-Fit
2-231

intJ

AP-321

A1
AND2

2
4

2 D

QUAD B

7474X

OOUT·,

QUAD B
3

I
I
I
I
I

CONF

QUAD B
L -_ _ _ _ _ _~1~.
______________________________

~
OR

CONF
EXTERNALLY CONNECT

Ip-------------------------~--------------------------- -----------------

l
I

:'·OIN

QUAD C
G
OR2
1
2
D ___L_O_B_A_L.,..-______-::-iD~O-----,;I>-D

INP

CONF

292053-15

Figure 10. Not Enough Global Feedback Extra Inputs-Fit
A1
AND2

2
4

7474X

2 D

QUAD B

1
2

C
CL

Q 6

QUAD B

----------------~----~~------------------~~~ ~
CONF

CAN'T REACH

QUAD C
OR2

o
CONF

Figure 11. Not Enough Global Feedback-No Fit
2-232

292053-16

inter

ER-22

ENGINEERING
'REPORT

,',

.' . . . September 1988

.....

5C180 vs. EP1800:
. A Comparison of
Device Specifications

LlLIYAS KOUli.lIS
PROGRAMMABLE LOGIC APPLICATIONS
. INTEL CORPORATION

Order Number: 294006-001
2-233

inter
:..

ER-22

",'

INTRODUCTION
This engineering report Compares the Intel SC180
EPLD with the Altera EPI800 EPLD showing how the
specifications for the two devices relate to one another:
Because Intel and Altera use a different methodology
for specifying parameters for this device, the most sig- ,
nifica,nt hurdle to overcome when performing a comparison is to correlate the different specs. That correlation is performed here in table format.

In summary, the Intel parts meet or exceed the specifications for the equivalent Altera parts. The equivalent Intel/Altera devices are shown below. All numbers are
based 9n the most current data sheet specs. (Intel
Sel80 Data Sheet, order number 290111-00S. Altera
1988 Data Book.)
Intel
5C180-70
5C180-75
5C180-90

equivalent Altera value is then listed. The formula used
to determine the Altera value is provided on a second
line to aid in correlating Altera's internal timing numbers to Intel's external numbers. Intel specifies device
parameters (Le., input pin to outpufpin).· while Altera
specifies internal timing paths (i.e., input pad delay,
logic array' delay, etc.). Intel's specifications reflect
numbers that can be measured, rather than internal
numbers that must be estimated from external measurements. Altera's internal timing specifications appear at
the top of each page.
Note that a new spec.' has been added to many of the
parameters. This new spec. is "enhanced output". Enhanced outputs are macrocells 1 through 4, 21 through
24, 2S through 28, and 4S through 48. Enhanced macrocells are S ns faster than the standard macrocells. ,

Altera
EP1800-2
EP1800-3
EP1800

The tables that follow compare each spec. listed in the,
IntelSCI80 data sheet for each of the three versions of
the device. A description of the parameter is listed, followed by the Intel mnemonic and the Intel spec. The

Intel guarantees the specifications of the SC180 devices,
listed in the SCI80 Data Sheet. Our Manufacturing'
group conducts extensive testing of the devices with
appropriate guardbands to guarantee all published values under worst case conditions. This testing ensures,
proper operation across widely divergent applications.
Also, every Intel product must pass an extensive quali-'
fication program before it is released to the market-,
place. Strict quality controls and monitors ru:e applied'
during the qualification and manufacturing processes.

2-234

ER-22

Inte15C180-70 VS. Altera EP1800-2
COMBINATORIAL MODE (5C180-70 VS. EP1800-2)
INTEL
Parameter

Symbol

Min

ALTERA
Max

I/O pin pad & buffer delay
INPUT pin pad & buffer delay
Logic array delay .
Enhanced logic array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

(1)
(1)
(1 )
(1)
(1)
(1 )
(1)
(1)
(1)

INPUT pin to comb. output
(TIN + tLAO + too)

tp01

INPUT pin to enhanced comb. output
(tiN + tLADe + tOD)

tPD1e

I/O pin to comb. output
. (tiD + tiN + tLAD + tOD)

Symbol

Min

Max
5

Units

ns
ns
ns
ns
ns
ns
ns
ns
ns

tpD1

60.

tP01e

60.

tpD2

70.

tpD2

70.

I/O pin to enhanced comb. output
(tiD + tiN + tLADe + toD)

tPD2e

INPUT to output enable
(tiN + tlAD + tzx)

tPZX1

(2)

INPUT pin to enhanced output enable
(tiN + tLADe + tzx)

tPZX1e

60.

(2)

60.

I/O to output enable.
(tiD + tiN + tlAD + tzx)

tpZX2

70.

(2)

70.

I/O pin to enhanced output enable
(tiD + tiN + tLADe + tzx)

tPZX2e

(2)

INPUT to output disable
(tiN + tLAD + txz)

tPXZ1

(2)

INPUT pin to enhanced output disable
(tiN + tlADe + txz)

tPXZ1e

60.

(2)

60.

ns'

I/O to output disable
(tiD + tiN + tLAD + txz)

tPXZ2

70.

(2)

70.

I/O pin to enhanced output disable
(tiD + tiN + tlADe + txz)

tPXZ2e

(2)

Asynchronous Clear
(tiD + tiN + tiC + toD)

tClR

70.

(2)

70.

tiD
tiN
tLAO
tLAOe
too
tzx
txz
tiC
tlCe

NOTES:

1. Intel does not spec internal timings of the device.
2, Altera does not spec. in 1988 handbook, these are calculated values based on formula given.

2-235

10.
40.
35
15
'15
15

40.

intJ

ER-22

SYNCHRONOUS MODE (5C180-70 VS. EP1800-2)
INTEL

Parameter

Symbol

Min

ALTERA

Max

(1 )
(1 )
(1)
(1)
(1)
(1 )
(1)
(1 )

Internal register setup time

1/0 pin pad & buffer delay
INPUT pin pad & buffer delay
OUTPUT buffer and pad.delay
Logic array delay
Enhanced logic array delay
. System clock delay
Feedback delay

Symbol

Min

tsu
tlO
tiN
tOD
tLAD
tLADe
tiCS
tFD

Units

5
10
15
40
35
4
10

ns
ns
ns
ns
ns
ns
ns
ns

Max. Frequency(no fdbk)
(1 I [INPUT pin setup toCLKxj)

fMAX

20.8

fMAX

20.8

MHz

Max. Count Frequency (\\lith fdbk)
(1/tCNT)

fCNT

16.1

fCNT

, 16.1

MHz

INPUT pin setup to CLKx(3)
(tIN+tLAD + tsu - tlN- tiCS)

tSU1

(2)

I/O pin setup to CLKx(3)
(tiO + tiN + tlAD + tsu - tiN - tiCS)

tSU2

(2)

INPUT pin setup to CLKx(4)

+ tsu

II0pin setup to CLKx(4)
tlO + tiN + tLADe + tsu - tiN - tiCS)

tSU2e

Clock High to Output Valid
(tiN + tiCS + tOD)

tco

- tiN - tiCS)

ns
ns
I

tSU1e

(tiN + tLADe

(2)

tCNT

Clock High Time

tCH

.24

tCH

ns·

Clock Low Time.

teL

tCl

NOTES:

1.
2.
3.
4.

Max

Intel does not spec internal timings on the device..
Altera does not spec. in 1988 handbook. these are calculated values based on formula given.
For global and standard macrocells.
For enhanced macrocells.

inter

ER·22

Inte15C180·75 vs. Altera EP1800-3
COMBINATORIAL MODE (5C180-75 VS. EP1800·3)
ALTERA

INTEL
Parameter

Symbol

Min

Max

(1 )

liD pin pad & buffer delay
INPUT pin pad & buffer delay
Logic array delay
Enhanced logic· array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

(1 )
(1 )
(1)
(1 )
(1 )
(1 )
(1 )

INPUT pin to comb. output
(tiN + tLAD + taD)

tpD1

INPUT pin to enhanced comb. output
(tiN + tLADe + tOD)

tPD1e

I/O pinto comb. output
(tiO + tiN + tLAD + taD)

Symbol

Min

Max

5
12

Units

ns
ns
ns
ns
ns
ns
ns
ns
ns

tpD1

tPD1e

tpD2

tlO
tiN
tlAD
tlADe
taD
tzx
txz
tiC
tlCe

(1 )

39
19
19
19
44

liD pin to enhanced comb. output
(tiO + tiN

+ tLADe + taD)

tPD2e

INPUT to output enable
(tiN + tLAD + tzx)

tPZX1

(2)

INPUT pin to enhanced output enable
(tiN + tlADe + tzx)

tPZX1e

(2)

tpZX2

(2)

tPZX2e

(2)

tpXZ1

(2)

. tpXZ1e

(2)

tpXZ2

(2)

tPXZ2e

(2)

tClR

(2)

liD to output enable
(tiO

+ tiN + tlAD + tzx)

liD pinto enhanced output enable
(tiO

+ tiN + tLADe + tzx)

INPUT to output disable
(tiN + tLAD + txz)
INPUT pin to enhanc!3doutput disable
(tiN + tLADe + txz)

liD to output disable
(tiO

+ tiN + tLAD + txz)

liD pin to enhanced output disable
(tiO

+ tiN +

tLADe

+ txz)

Asynchronous Clear
(tiO + tiN + tiC + tOD)
NOTES:

1. Intel does not spec internal timings of the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.

2-237

infef

ER-22

SYNCHRONOUS MODE (5C180-75 VS. EP1800-3)
ALTERA

INTEL
Parameter
Internal register setup time
I/O pin pad & buffer delay
INPUT pin pad & buffer delay
OUTPUT buffer and pad delay
Logic array delay
Enhanced logic array delay
System clock delay
Feedback delay

Symbol

. Min

Max

(1 )
(1 )

(1)
(1)
(1 )

(1 )
(1 )
(1 )

Symbol

Min

tsu
tlO
tiN
taD
tLAD
tLADe
tiCS
tFD

Max

Units

12
19
44
39
4
14

ns
ns
ns
ns
ns
ns
ns
ns

Max. Frequency (no fdbk)
(1 I[lNPUT pin setup to GLKx])

fMAX

19.6

fMAX

18.5

MHz

Max. Count Frequency (with fdbk)
(1/tCNT)

fCNT

15.1

fCNT

13.8

MHz

INPUT pin setup to CLKx(3)
(tiN + tlAD + tsu - tiN - tiCS)

tSUl

(2)

tSU2

(2)

tSUle

(2)

tSU2e

(2)

110 pin setup to CLKx(3)
(tiO + tiN + tLAD + tsu - tiN - tiCS)
INPUT pin setup to CLKx(4)
(tiN + tLADe + tsu - tiN - tiCS)

110 pin setup to CLKx(4)
(tiO + tiN + tLADe + tsu - tiN - tiCS)
Clock High to Output Valid .
(tiN + tiCS + taD)

tco

(2)

tCNT

Clock High Time

tCH

tCl

Clock Low Time

NOTES:
1. Intel does not spec internal timings on the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.
3. For global and standard macrocells.
4. For enhanced macrocells.

2·238

ER-22

Inte15C180-90 VS. Altera EP1800
COMBINATORIAL MODE (5C180-90 VS EP1800)
ALTERA

INTEL
Parameter

Symbol

I/O pin pad & buffer delay
INPUT pin pad & buffer delay
Logic array delay
Enhanced logic array delay
Output buffer and pad delay
Output buffer enable
Output buffer disable
Clock Delay (Asynch.)
Enhanced Clock Delay (Asynch.)

(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )

INPUT pin to comb. output
(tiN + tlAO + tOD)

tpD1

INPUT pin to enhanced comb. output
(tiN + tlAOe
too)
I/O pin to comb. output
(tiO + tiN + tLAO + too)

Min

Max

Symbol

.Min.

Max

Units

tlO
tiN
tLAO
tLAOe
too
tzx
txz
tiC
tlCe

5
14
48
43
23
23
23
48
43

ns
ns
ns
ns
ns
ns
. ns
. ns'
ns

tp01

tPD1e

n!:;

tp02

110 pin to enhanced comb. output

+ tiN + tlAOe + too)

tP02e

INPUT to output enable
(tiN
tLAD + tzx)

tpZX1

(2)

INPUT pin to enhanced output enable
(tiN + tlADe + tzx)

tPZX1e

(2)

I/O to output enable
(tiO + tiN + tLAO + tzx)

tpZX2

(2)

·ns

I/O pin to enhanced output enable
(tiO + tiN + tLAOe + tzx)

tPZX2e

(2)

ns -

INPUT to output disable
(tiN + tLAO + txz)

tpXZ1

(2)

INPUT pin to enhanced output disable
(tiN + tLAOe + txz)

tPXZ1e

(2)

··ns

(tiO

I/O to output disable
(tiO + tiN + tLAO + txz)

tPXZ2

(2)

I/O pin to enhanced output disable
(tiO + tiN + tlAOe + txz)

tPXZ2e

(2)

Asynchronous Clear
(tiO + tiN + tiC + too)

tClR

(2)

NOTES:
1. Intel does not spec internal timings of the device.
2. Altera does not spec. in 1988 handbook, these are calculated values based on formula given.

2-239

ER·22

SYNCHRONOUS MODE (5C180·90 VS EP1800)

INTEL
Parameter

Symbol

INPUT pin pad & buffer delay
OUTPUT buffer and pad delay
Logic array delay
Enhanced logic array delay
System clock delay
Feedback delay .

(1 )
(1)
(1 )
(1)
(1)
(1)
(1)
(1)

Max. Frequency (no fdbk)
(1/ [INPUT pin setup to CLKxl)

fMAX

Internal register setup time

110 pin pad & buffer delay

Max. Count Frequency (with fdbk)'"
(1/tCNT)

ALTERA
Max

·Min

Symbol
tsu
tlO
tiN
too
tLAO
tlAOe
tiCS
tFO

16.1

Units'

18
5
14
23
48
43
4
16

ns
ns
ns
ns.
ns
ns
ns
ns

16.1

MHz

12.2

MHz

fMAX
:

....

12.2

fCNT

Min .... Max

fCNT

INPUT pin setup to CLKx(3)
(tiN + tLAO + tsu - tiN - tiCS)

tS.U1

(2)

I/O pin setup to CLKx(3)
(tiO + tiN + tU\O + tsu - tiN - tiCS)

tSU2

(2)

INPUT pin setup to CLKx(4)
(tiN + tLAOe + tsu - tiN - tiCS)

. 110 pin setup to CLKx(4)
, (tiO + tiN + tlAOe + tsu - tiN - tiCS)
. ClockHigh tei Output Valid
(tiN + tiCS + too)

tSU1e

(2)

tSU2e

(2)

...

tco

.' (2)

ns' ..

.
'

tCNT
tCH
tCl

....

tCNT

tCH

. tCl

30 '

ns
.:

NOTES;'.
1. Intel does not spec internal.timings on the .device.
in 1988 handbook, these are calculated values based on formula given,
3. For global and standard macrocells. .
4.' For enhanced macrocells.

2. Altera does not spec.

2-240

Techniques for Modular EPLD Logic

D~sign

Lawrence Pal ley
PLDO Product Marketing Manager
Intel Corporation
151 Blue Ravine Road
Folsom, CA 95630
I NTRODUCTI ON
Advances in both programmable logic
devices and the tools used to configure them
now enable new design techniques for custom
logic applications. New high capacity flexible
architectured EPLDs (erasable and electrically
programmable logic devices) allow for complete
single chip integration of one or more logic
configurations. Additionally. deVelopment
tools make use of these capabi litles by
providing alternatives for design input, high
, speed logic compilation and minimization,
heuristic'[ogic fitting into EPLD devices, and
superior reporting documentation. Designers
can take ~dvantage of these advances with a new
Modular EPLD logic design (MELD)technique, to
accelerate their product development.
ADVANCES IN EPLDs
Traditional PLDs relied on B~olean
equation entry and compilation methods for
combinatorial function implementation. The
primary applications were as SSI/MSI replacements for implementing decode "gl~e" in
microprocessor based systems. PLDs came in
oipolar versions with total logic content under
400 gates of equivalent logic. Tools, to
develop the programmable logic implementation
of a function didn't require a high degree of
sophistication - the devices for which they'
were optimizing designs had relatively little
logic and little logic flexibility.
Newer EPLDs incor~orateseveral f~atures
which broaden their application base. Besides
their ,low power CMOS technology;th'ey incor~'
por~te, i ndi vi dua fly ,confi gurab le regi stera'nd
I/O logic for each ~acrocell. Devices s~ch as
the 5C060 incorporate 16 macrocells with
registers programmable ,into 0, or JK configurations. Each,re~ister is al~o
,
programmab 1y confi gured to be, clocked by'
'synchronous or, asynchr'onous c i ocks.
Addi tiona lly, outputs and feedb'ack~aths for
each pin can be combinatorial or'registered.
The combination of this levei of fle'xibility'
and gate counts of some devices ~xceeding,1200.
',EPLDs have moved programmable' logic well past
's~mple combinatorial functions.
"

logic optimization for maximum device utilizati on, and improved reporti ng documentati o'n.'
Inte 1 's programmable, logi,c deve 1opment system
provides these improvements. Input methods
include the choice ,of (and combination of)
schematic, netlist, state machine, or Boolean
entry. Besides Boolean equation minimization,the optimizer program optimally matches
I/O and register resources required by the
design with what's available in EPLD devices.
It then reports on how the logic entry was
reduced, which resources were,re- quired, and
how the design was placed in a given device.
Resources still available in the devices or not
ab 1e to fi tin to 'the devi ce a're a Tso
documented.'

Making use of, both the advances, in EPLD
devices and their development tools, engineers
can now design hardware (logic) in much the
same way as software is developed. This new
design technique called MELD (Modular EPLD
Logic 'Design) is shown in Figure 1. Design
Entry, in any of the typical engineering
formats, is entered on a development station
(in this case a personal computer). Using EPLD
development system software, the design is then
c~m~il~d for EPLD' implementation.
Object ,code
or (in,the case of an EPLD) a JEDEC l's and O's
file, are th~ result. The unique capability of
EPLDs is to test a part of a partitioned design
in silicon, erase the EPLD, test the next
design, and finally to merge the d~signi '
together. This powerful logic design methodology allows for 'the partitioning of a complex
logic function into,smaller sub-functions that
,can be i~dividually designed'and debugged using
the design tools and the erasability feature of
EPLDs. After the individual modules are ~roved
to be,functionalas desired, they can be combined,on the same EPLD, allowing for higher
lntegration and its' attendant benefits.

To make optimum use of the new EPLDdevice
technology, design tools needed to improve to
allow more freedom of design input, better
2-241

26/1

o'"
'"
'"

OTHER
DESIGN
, SECTIONS

G'>

:z
n

,-,
,0

'"
'"
'"

'~
'r

figure L

NOTE:

EPLD design process compared with~.<, 9/26/85
PART: 5C121
INPUTS: CLK,ENABLE,RESET
OUTPUTS: BCDO,BCD1,BCD2,BCD3
MACHINE: BCD_COUNTER

CLOCK: CLK
STATES: [BCD3 BCD2 BCDl BCDO]
SO
[
0
0
Sl
[
0
0
S2
[
a
a
[
0
0
S3
S4
[
0
1
S5
0
[
1
S6
[
0
1
S7
[
a
1
S8
[
1
a
S9
[
1
a

0
0
1
1
0
0
1
1

a
a

0
1
0
1
0
1

a
1

%TRANSITIONS%
SO:
IF RESET THEN SO
IF ENAB LE THEN" S 1
S1 :
IF RESET THEN SO
IF ENABLE THEN S2

S2 :
IF RESET THEN SO

IF ENABLE THEN S3
S3:

IF RESET THEN so
IF ENABLE THEN S4

S4:
IF RESET THEN SO
IF ENABLE THEN S5
S5:
IF RESET THEN

IF ENABLE THEN S6
S6:

IF RESET THEN so
IF ENABLE THEN S7

S7:
IF RESET THEN SO

IF ENABLE THEN S8
S8 :

IF RESET THEN so
IF ENABLE THEN S9

S9:
IF RESET THEN SO

IF ENABLE THEN SO
END$

2-243

26/1

FIGUKE 3

LSP
INTEL
February 7, 1986

o
o

5C121
BCD COUNTER
LB Version 3.0, Baseline 17x, 9/26/85SMV Version 1.0 Baseline 1.3 85/12/1~ OO:lt:5
PART: 5C121
INPUTS:
CLK, ENABLE, RESET
OUTPUTS:
BCDO, BCD1, BCD2, BCD3
NETWORK:
CLK = INP(CLK)
ENABLE = INP(ENABLE)
RESET = INP(RESET)
%

I/O's for State Machine "BCD_COUNTER"
%

BCD3,
BCD2,
BCDl,
BCDO,

BCD3
BCD2
BCDl
BCDO

RORF(BCD3.d,
RORF(BCD2.d,
RORF(BCDl. d,
RORF(BCDO.d,

CLK,
CLK,
CLK,
CLK,

GND,
GND,
GND,
GND,

VCC)
VCC)
VCC)
VCC)

EQUATIONS:
%

Boolean Equations for State Machine "BCD_COUNTER"
%
%

Current State Equations for "BCD_COUNTER"
%

SO
Sl
S2
S3
S4
S5
S6
S7
S8
S9

BCD3'*BCD2'*BCDl'*BCDO':
BCD3'*BCD2'*BCD1'*BCDO:
BCD3'*BCD2'*BCDl*BCDO':
BCD3'*BCD2'*BCD1*BCDO:
BCD3'*BCD2*BCD1'*BCDO';
BCD3'*BCD2*BCD1'*BCDO;
BCD3'*BCD2*BCD1*BCDO';
BCD3'*BCD2*BCD1*BCDO;
BCD3*BCD2'*BCD1'~BCDO';

BCD3*BCD2'*BCD1'*BCDO;

SV Definjng Equations for State Machine "BCD_COUNTER"
%

BCD3.d

S8.n
+ S9.n;

BCD2.d

S4.n
+ S5.n
+ S6.n
+ S7.n;

BCDl. d

S2.n
+ S3.n
+ S6.n
+ S7.n;

BCDO.d
+
+
+
+

Sl.n
S3.n
S5.n
S7.n
S9.n;

26/1

2-244

FIGURE 3 (CONTINUED)
Next State Equations for State Machine "BCD_COUNTER"
~

Sl.n

+ SO
S2.n

+ Sl
S3.n

+ S2
S4.n

+ S3
S5.n

+ S4
S6.n

+ S5
S7.n

+ S6
S8.n

+ S7
S9.n

+ SB

(ENABLE)'
* (RESET) ,
* ENABLE
* (ENABLE)*, (RESET)';
* (RESET) ,
** ENABLE * (RESET)';
(ENABLE) ,
** ENABLE
* (RESET) ,
* (RESET)';
(ENABLE) ,
* ENABLE * (RESET)';
* (RESET)'
* (ENABLE)' (RESET)'
*
*
;
* (RESET)'
* ENABLE
(ENABLE) ,
* ENABLE * (RESET)';
* (RESET) ,
* (ENABLE) , (RESET) ,
*
* ENABLE * (RESET)';
* (ENABLE) , (RESET)'
*
*
;
* (RESET)'
** ENABLE
(RESET) ,
(ENABLE) ,
*
* ENABLE * (RESET)';

END$

2-245.

26/1

LSP
INTEL
February 7, 1986

FIGURE 4

o
o

5C121
SEVEN SEGMENT OECOOERS FOR BCO COUNTER
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C121
INPUTS:
OUTPUTS: SEGA,SEGB,SEGC,SEGO,SEGE,SEGF,SEGG
NETWORK:
SEGA
CONF (SEGA,VCC)
SEGB
CONF (SEGB,VCC)
SEGC
CONF (SEGC,VCC)
SEGO
CONF (SEGO,VCC)
SEGE
CONF (SEGE,VCC)
SEGF
CONF (SEGF,VCC)
SEGG
CONF (SEGG,VCC)
EQUATIONS:
SEGA
0 + 2 + 3 + 5 + 7 + 8 + 9;
SEGB

+ 1 + 2 + 3 + 4 + 6 + 7 + 8 + 9;

SEGC

+ 1 + 3 + 4 + 5 + 6 + 7 + 8 + 9;

SEGO
SEGE
SEGF
SEGG

0
0
0
2

+
+
+'
+

2 + 3
2 + 6
4 + 5
3 + 4

+
+
+
+

5 + 6 + 8;
8;
6 + 8 + 9;
5 + 6 + 8 + 9;

103*/02*/01*/00;
103*/02*/01*00;
103*/02* 01*/00;
/03*/02* 01*00;
/03* 02*/01*/00;
5
/03* 02*/01*00;
6
/03* 02* 01*/00;
7
/03* 02* 01*00;
8
03*/02*/01*/00;
9
03*/02*/01*00;
%LINK EQUATIONS %

1
2
3
4

00
01
02
03

BCOO;
BC01;
Be02;
BC03;

ENO$

FIGURE 6
Intel Programmable Logic Software
LOC Menu
Fl Help

F2
F3
F4
F5
F6
F7
26/1

iPLS Menu
Input Format
File Name
Minimization
Inversion Control
LEF Analysis

AOF
A:BCO A:SEGEQS
Yes
No
Yes

2-246

FIGURE 7

LSP
INTEL
February 7, 1986

o
o

5Cl21
BCD COUNTER
LB Version 3.0, Baseline 17x, 9/26/85SMV Versiori 1.0 Baseline 1.3 85/12/13 00:12:5
PART:
5C121
INPUTS:
CLK, ENABLE, RESET
OUTPUTS:
BCDO, BCDl, BCD2, 'BCD3, SEGA, SEGB, SEGC, SEGD, SEGE, SEGF, SEGG
NETWORK:
CLK = INP(CLK)
ENABLE = INP(ENABLE)
RESET = INP(RESET)
BCDD, BCDO
RORF(BCDO.d, CLK,
BCDI, BCDI = RORF(BCDl.d, CLK,
BCD2, BCD2 = RORF(BCD2.d, CLK,
BCD3, BCD3 = RORF(BCD3.d, CLK,
SEGA
CONF(SEGA, VCC)
SEGB
CONF(SEGB, VCC)
SEGC
CONF(SEGC, VCC)
SEGD
CONF(SEGD, VCC)
SEGE
CONF(SEGE, VCC)
SEGF
CONF(SEGF, VCC)
SEGG
CONF(SEGG, VCC)
EQUATIONS:
SEGG
BCDI
BCD3'
BCD2'
+ BCDI'
BCD3'
BCD2
+ BCDl'
BCD3
BCD2'
+ BCDI
BCD3'
BCDO';

*
*
*
*

SEGF

BCD3'
+ BCD3'
+ BCD3
+ BCD3'

BCD2'

SEGE

+ BCD3'

SEGD

BCD2'
+ BCD3'
+ BCD3'
+ BCD3'

GND,
GND,
GND,
GND,

VCC)
VCC)
VCC)
VCC)

*
*
*
*

* BCDl' ~ BCDO'
* BCD2 * BCDl'
BCDl'
BCD2'
* BCD2 *
* BCDO' ;
* BCDO'
* BCDI'
BCDI * BCDO';

* BCDI' ** BCDD'
BCDI
** BCD2'
BCDI * BCDO'

* BCD2 * BCDI ' * BCDO;
* BCDI'
BCD2
* BCDD;
*
BCD2' * BCDI'
BCD3' * BCDO'
BCD3' * BCDI;
BCD3' * BCD2' * BCDO'
BCD3 * BCD2' * BCD l'
BCD3' * BCD2' * BCDI
BCD3' * BCD2 * BCDD;
BCD3 * BCD2' * BCDl' * BCDO' * RESET'
+ BCD3 * BCD2' * BCDl' * ENABLE' * RESET'
+ BCD3' * BCD2 * BCDI * BCDO * ENABLE * RESET';

BCD2'
SEGC
+ BCD3'
+ BCD3'
SEGB
+
+

SEGA
+
+
+

BCD3.d

2-247

26/1

FIGURE 7 (CONTINUED)
BCD2.d

BCD3' * BCD2 * BCDO' * RESET'

+ BCD3' * BCD2 * BCDl' * RESET' ,
+ BCD3' * BCD2 '" ENABLE' * RESET'
+ BCD3' * BCD2' * BCDI * BCDO * ENABLE * RESET';

BCD!. d

BCD3.', * BCDl* BCDO' * RESET',

+ BCD3' * BCDI * ENABLE' * RESET'
+ BCD3' * BCDl' * BCDO * ENABLE * RESET';

BCDO.d- BCD3'
+ BCD3'
+ BCD2'
+ BCD2'

*
*
*
*

BCDO' * ENABLE * RESET'
BCDO * ENABLE' * RESET'
BCDl' * BCDO * ENABLE' * RESET'
BCDl' * BCDO' *~ENABLE *,RESET'j

END$

FIGURf 8'
Logic Optimizing Compiler Utilization Report
***** Design implemented successfully
LSP
INTEL
February 7, 1986

o
o

5C121
BCD COUNTER
LB Version 3.0, Baseline lix, 9/26/85SMV Version 1.0 Baseline :1,3 85/12/13 00:12:5
5C121
CLK
GND
GND
GND
GND
GND
GND
SEGD
RESERVED
RESERVED
RESERVED
SEGA
RESERVED
RESERVED
SEGE
RESERVED
BCD2
RESERVED
RESERVED
GND

211/1

1
2
.-: 3
-I 4
- 5
- 6
7
8
-I 9
-: 10
-I

-Ill

-: 12
-113
-: 14
-: 15
-:16
- 117
- 118
-: 19
-120

40:39:38:37136:35:34:33:32:31:30:29128:27:26:25124:23:22:21: -

Vcc
Vcc
ENABLE
RESET
GND
GND
GND
GND
SEGG
RESERVED
RESERVED
SEGC
SEGB
RESER\IED
RESERVED
SEGF
RESERVED
BOD3
BCDI
BCDO

2-248

FIGURE 8 (CONTINUED)

**INPUTS**

MCe11 #

PTerms

MCe11s

Name

Resource

CLK

INP

RESET

INP

10
11
12
19

ENABLE

INP

10
11
12
19

Feeds:
OE

Clear

Clock
Reg

**OUTPUTS**
Name

Resource

MCell #

PTerms

MCe11s

SEGD

CONF

·28

4/ 4

SEGA

CONF

4/ 6

SEGE

CONF

2/ 4

BCD2

RORF

4/ 4

1
4
5
8
10
12
19
21
24
28

BCDO

RORF

4/ 8

1
4
5
8
10

Feeds:
OE

Clear

12
19
21
24
28
BCDI

RORF

3/ B

1
4
5
8
10
11
12
19
21
24
28

2-249
26/1

'BCD3

RORF

, FIGURE 8'. (CONTINUED)
10
3/ 4

1
4

,'.'

8
10
11

12
19
21
24
28
SEGF

CONF

4/ 4

SEGB

CONF

3/ 6

SEGC

CONF

3/ 6

CONF

4/ 4

SEGG
32
**UNUSED RESOURCES**
Name

Resou'rce

MCe11

.' :

PTerms
':v,"

2
3, '
4
5
6
7
9
10
11
13
14
16
18
19
24
26
27
30
31
33
34
35
36,
NA
NA
NA
NA

'27
26
25
23
22
20
18
17
9,
7
6

10
8
6
8
10
12
8
8
12
10
8
8
10

2
7"

..:.

13
14
15
' 16,:

8
8
8

....

**PART UTILIZA'fION**
37%
39%
18%

Pins
MacroCell~

Pterms
CONCLUS IONS' ,

'The complete design
to enter, compile, and 1
ability to partition des
implement those designs
26/1

took' less than an hour
nk wlth EPLDs. The
gns, then individually
n the logic design

entry of choice, and finally to link designs
together is a new design method only available
with advances in programmable logic and their
design tools. By taking advantage of these
capabilities, designers can bring logic
implementations to market faster and with a
high degree of integration.
2-250

inter

AR-450

VLSI DESIGN TECHNOLOGY

Crosspoint Switch:
A PLD Approach
by Jim Donnell, Intel Corp.

device dictates the nuinber of switches that can be designed into
a single device.
rasable programmable logic devices (EPLDs) combine
the gate densities oflow-end gate arrays with the short
Configuration 1
development time and low cost of EPROMs. This
The first circuit (Figure 1) considered is a digital crosspoint
merging ofte~hnologies produces a device with features suited
switch with eight inputs and a 3-bit word width. This switch
to a wide range of digital applications. In contrast to the long
transfers a 3-bit word coming from one of eight sources to a pardevelopment times (and higher costs) for gate arrays, EPLDs
ticular output. The number of devices "OR-tied" to each outrequire minimal frontend design time. In just a few hours,
put pin determines the number of outputs. Selecting one of eight
EPLD designs can be developed, modified and verified. Also,
core elements from one EPLD design can be incorporated indata inputs from each of the three channels (AO to A7, BO to B7
and CO to 0), the switch routes that data to a single output (QA,
to new designs as quickly as standard software subroutines from
QB and QC). Each output can be OR-tied to more than one
one program can be modified and used in other programs.
The design of a digital crosspoint
.
switch using an Intel 5CI21 EPLD illustrates these features. Digital Design
implemented a crosspoint switch in a gate
array last year (see Digital Design,
January through March, 1985). Application~s that require a data transfer from one
of several inputs to one of several outputs
frequently use a digital crosspoint switch.
Using the 5Cl2l EPLD, Intel Corp. (Santa Clara, CA) designed three different
configurations of a crosspoint switch.
Offered in a 40-pin package that provides up to 36 inputs or 24 outputs, the
5CI21 supports up to 28 macrocells (including four buried registers) and 236
product terms (p-terms). Logic density in
the 5CI21 is the equivalent of 1,200
usable NAND gates. Maximum power
requirements are 100 rnA active and 30
rnA standby with TTL input levels. With
CMOS input levels, a 5Cl2l requires 50
rnA active and 3 rnA standby.
Two major parameters determine the
complexity and configuration of a digital
~ crosspoint switch: the number ofpossible switching locations for each bit (inputs and outputs), and the number of bits
Figure 1: Configuration 1 uses a three-channel eighHo~ne multiplexer circuit with latching intransferred in one clock pulse (word
puts. Each output can drive multiple, individually selected inputs to complete the digital crosswidth). The availability of I/O pins,
point switch. By connecting inputs to the EPLD outputs in an "OR-tied" configuration, with only
macrocells and p-terms for a given EPLD
one input enabled at any time, the multiplexer circuit becomes a crosspoint switch.

2-251

VLSI DESIGN TECHNOLOGY

three-state input to complete the switch (only one input can be
enabled at a time). Three additional control bits (00 to 02)
select one of the eight different inputs. AlIlhree channels
operate in parallel: Separate input and output clocks allow a
high data rate and relax input set-up and hold times. Input data
for all three channels, along with the three select bits, are
latched by ILE. Oata at the inputs can change state after being
latched and data is clocked out of the switch by CLK.
Equation 1 shows the Boolean expression for a single channel in the sum-of-products form. (See Thble 1 for all equations.)
The Boolean expression for the remaining two channels is
similar: the designer need only change the A in the equations
toaBore.

Figure 3: Configuration 2 uses a single-bit eight-inputleight·output
digital crosspoint switch, Designers can implement this for either optimal package count (see Figure 4) or for optimal speed (see Figure 5),

Timing Analysis
The internal delay paths determine the circuit's maximum
operating frequency (fmax). In this configuration there is an input delay (Tin), an array delay (Thd), a register delay (Trd) and
an output delay (Tod). The fmax is a function of the signals that
must senle at the input of the output register before the rising
edge ofth~ clock. In this case, signals propagate only through
the Input latches and the array. Therefore, the data must be valid
at the inputs Tin + Thd just nanoseconds before the rising edge,
ofthe internal clock signal (CLK). However, because of the inherent delay of the CLK signal, this reference must be shifted
to the rising edge ofthe external clock signal by subtracting the
internal clock delay (Tic). The external data set-up time (Thu)
is shown in Equation 2. Inverting this time requirement yields
the maximum operating frequency.
As the output flip-flops are clocked, data propagates through
the register to the output pin. With reference to the external
c10Sk pin, data becomes valid althe outputs Tic + Trd + Tod
nanoseconds after the rising edge ofthe clock. Figure 2 shows
the timing requirements for this circuit, including the input latch
signal.
Using a 5CI2l-50 (50-nsec propagation delay), data can be
sent through this switch configuration at 25 Mbits/sec. This
transfer rate remains independent ofthe word width. Since one
5CI21 EPLO in this configuration can simultaneously transfer
three bits of information, three 5CI21's are required to transfer
a byte of data during each clock cycle. This configuration of a
digital crosspoint switch uses 86% of the 40 pins, 71 % of the
macrocells and II % of the available p-terms in the 5CI2l EPLO.

outputs (QO to '([I). Six control bits' are required for each
transfer: three to selectthe input path (DO to 02); three to select
the output path (03 to 05). By selecting a single output path and'
clocking all output registers simultaneously, deselected outputs
are automatically cleared, This is useful for designs where only
the most current data is needed. Equation 4 is the common
equation to select one of eight input paths, Equations 5to 12
complete the Boolean equations for this example.
The previous equations would contain eight product terms if
they were written in expanded form. However, by treating
SELECTEQ as one signal" each equation ,contains, only one
product term. Both optionsare availabl~ in the 5C12I. But, there

I n contrast to the long
development times for
gate arrays, EPLDs
require minimal frontend
desigr;l time.

are advantages ,and disadvantages to the two methods. If
SELECTEQ is implemented as one signal through a combinational feedback option, one and one-half crosspoint switches
can be implemented in one 5CI21 (Figure 4). The trade-offis
, faster speed for low chip count. By design, only 18 macrocells
in the 5C121 can support eight product terms. On the other
hand, selecting the combinational option reduces the p-terms
but introduces an additional input mux delay.
Figure'4 shows that an input signal must pass through four
delays before,reaching the input to the flip-flop. Again, subtracting the input clock delay to shift the reference point yields
Configuration 2
Equation 13 for the set-up time, Inverting Tsu gives the maxThe second circuit (Figure 3) also selects one of eight inputs
- imum operating frequency. In this configuration, data can be
(10 to 17), but this time data is routed to one of eight different
clocked through at 12 Mbits/sec, This layout utilizes '!I % of the
available pins, 89 % of the available
macrocells and \3 %of the product terms.'
Six 5CI21s would be required to implement abyte-wide switch with this layout.
If the combinational feedback option is
not used, there are eight output equations, each containing eight product
terms. Assigning these equations to the
macrocells that support eight p-terms
shows that only a single, one-of-eight
select line digital crosspoint switch fits
Figure 2: A 4O·nsec internal set-up time (prior to clocking data through the output flip-flop) marks
into one 5C12I. Thus, the design requires
Configuration 1. Data clocked into all eight input latches at the rising edge of one ILE/CLK cycle
eight 5CI21s io complete a byte-wide
is selected and clocked out oftheoutput flip.flop on the next rising edge of ILE/CLK. '
DIGITAL DESIGN • ..JULY 1986

2-252

inter
VLSI DESIGN TECHNOLOGY

parallel transfer. Since the signal paths are identical to Configuration I, the same timing analysis applies here.
This layout (Figure 5) utilizes 65% of the pins, 39% of the
macrocells and 30% of the p-terms. Though the utilization
numbers are lower for this example, the actual available pins
and macrocells in the 5Cl2l are higher than initially visible.
Since macrocells in the 5Cl2l are organized into groups of four,
when one output structure in a macrocell group is defined the
other three must be of the same structure. Many times, this
results in unused pins being labeled "RESERVED" in the utilization report.

Configuration 3
The final circuit (Figure 6) again uses eight inputs (10 to 17) and
eight outputs (QO to ([I), though this time the deselected ouiputs "remember" their previously selected state. With the
5Cl2!'s register feedback option, deselected outputs can hold
the last data bit sent to that output New data appears when the
output Is selected again.
Equations 14 to 22 express the Boolean terms necessary to
implement this hold feature in the digital crosspoint switch.
Note that each output is now a function of both the present inputs
and the previous output (Qnfbk), which implements the registered feedback. Data bits 03, 04 and 05 determine which data
bit will pass to the output. Again, the number of p-terms dictates the use of combinational feedback, as in Configuration 2.

Timing Analysis

Figure4: Configuration 2 features a lowpackagecount layout. Notethat
one and one-half switches fit into each 5C121 EPLD. This configuration
uses combinatorial feedbacks to simplify the logic equations, thus
eliminatIng the requirement for eight product t~rms per output.

This configuration's timing analysis is similar to Configuration
2's combinational feedback analysis, with the exception of a
register feedback delay (Trf). Trf is the time that the data is present at the output of the flip-flop to the time that data is available
to the array.
The total delay associated with the registered feedback consists of the Trd, the Trfand the Tad. Data from the flip-flop output reaches the input in about 50 nsec. The delay associated with
data coming from the input pins is the same as that of Configuration 2 with combinational feedback - approximately 83 nsec.
Using this as the clock period, there is ample time to implement
the register feedback without affecting the cycle time. In this
configuration, data could be clocked through at 12 Mbits/sec.
Combinational feedback reduces the p-term requirement to
two p-terms per equation. This allows one and one-half crosspoint switches to fit into one 5C12!. The design utilizes 64 % of
the available pins, 42 % of the macrocells and II % of the product terms. Six devices would be required to implement a bytewide switch.
All of the configurations function differently, and no one configuration is optimum for all applications. A designer can
customize a device to meet the needs 0;' an application, whether
those needs include higher speed or lower chip count. A second
device can be quickly developed for a different application,
Designers are no longer restrict~d to a single device type that
must be adapted to an application with additional logic devices,

.JULY 1986 • DIGITAL DESIGN

2-253

VLSI DESIGN TECHNOLOGY

An original design can be developed in an afternoon. Additional
devices derived from an original design can be developed in a
few hours. Also, the ability to erase an EPLD and reprogram
it allows design errors to be corrected immediately. Instead of
several weeks delay with gate arrays, a designer using EPLDs
can have working silicon devices in one day.
Both the flexibility and short design times associated with
EPLDs make them a good choice for applications that benefit
Figure 6: Configuration 3 shows the use of registered feedback to allow
deselected outputs to retain their previously selected data. The logic
for a representative channel is shown. As with Configuration 2. this con·

figuration can be optimized for package count or speed.

from custom silicon devices. Today, EPLDs offer designers the
densities and configuration flexibility of gate arrays, along with
the short development time and cost associated with EPROMs.
CD

Figure 5: This circuit (Configuration 2 optimized for speed) combines
the multiplexer and demultiplexer functions for each channel in a single
array. Since each output equation uses eight product terms, only one
switching channel can fit into each 5C121 package.

.:.JULY 19B5 • DIGITAL DEBIGN

2-254

inter

AR-451

Designer's Corner

A Programmable Logic Mailbox for
80C31 Microcontrollers
Karlheinz Weigl and Jim Donnell, Intel Corp" Frankfurt. West Germany, and Folsom, CA

his article describes the implementation of a semi-intelligent interface between two 80C3! microcontrollers, using a mailbox
protocol. Applications for an interface
such as the the one described here are
often found in industrial control areas
where multiple microcontrollers are
used to accomplish a given task. Due to
the architecture of-the microcontroller
(i.e., no READY input; no HOLD/HLDA
interface; port-oriented 110; etc.), exchanging data and status between these
devices becomes a cumbersome tasK.
Given this directive, it becomes the designer's task to develop a mUlti-port
memory interface that allows for· zero
wait-state operation (i.e., no READY signal required), that electrically isolates
the microcontroller buses, and that permits asynchronous access. Synchronization would result in the generation of
wait states.
We'realize the logic necessary to implement the desired functions in two
erasable programmable logic devices
(EPLDs). One device, the 5C031, contains roughly the equivalent of 300 2input NAND gates, while the other EPLD,
the 5C060, can implement designs with
up to approximately 600 gates.

ADoAD ~
Po

AD C-AlJ 1

ALE

'~l..;

Af):Al!>

AS"A1S

·2

p!;tN

rsN

PBOG:HBH

P8UCJ1BH

i'mPJ 7
WRP3S

mJP37
W\1P35

The Mailbox Principle
And its Implementation
In a mailbox memory system, the microcontrollers exchange information as
bytes of data written to or read from a
mailbox register. Control logic permits
simultaneous access to the mailbox, thus
eliminating the need for arbitration between the microcontrollers. Implementing the data exchange in this form
achieves most of the design criteriagiven above.
Avoiding bus arbitration together
with the short propagation delays of the

FIGURE 1. Schematic 01 mailbox memory system.
EPLDs provides zero wait-state operation
of the data exchange. Electrical isolation
of the address and data buses is achieved
by using the high-impedance output capability of the 5C060. Simultaneous,'
asynchronous access is achieved by separating the RD and WR strobes issued by
each microcontroller.
WiJh a mailbox memory system, there

Copyright© 1987 by CMP Publications, Inc., 600 Community Drive, Manhasset,
Reprinted with permission from VLSI Systems Design.
.

2-255

NY 11030.

is an obvious need for some type of
communication protocol to confirm the
reception of a message, or the presence
of data in the mailbox. In addition, the
read and write logic must be defined
such that simultaneous access to the
mailbox is permitted. In order to segment the task, the design will be approached in terms of two separate mod-

ules: the mailbox (memory section), and
the the control logic (protocol).
To begin the design of the memory
section, it is first helpful to identify the
,esources required for the design. The'
mailbox requires a total of 16 memory
storage registers (two bytes of data), tristate output control, and two separate
clock lines used to write the memory
registers.
The 5C06O EPLD was chosen to implement the memory section. This device
contains 16 programmable register
groups that may be configured to operate
as JK·, RS·, D·, and T-type flip-flops.
Each register group feeds a bi-directional input/output pin, which may be tristated via . an output-enable product
term. These lIO pins may also serve as
data inputs when the register output. is
tri-stated. This feature forms the basis of
the read-signal logic required in the design. Write logic can be accomplished
through the two synchronous dock inputs provided in the. 5C060. Each synchronous clock drives a set of eight
registers in the device. The operation. of
the memory section of the mailbox
memory may now be solidified.
As shown in Figure I, the two microcontrollers are separated into controller
A and controller B. Register group A
(signals 10AO to lOA 7) serves as an input
buffer to Illicrocontroller A. This buffer
receives information from microcontroller B's data bus. The write control for
register group A comes from microcon,troller B.
'
Again, referring to Figure I, it can be
. seen that register group B serves as an
output buffer to microcontroller B. This
buffer gets information from microcontroller A and is therefore write-controlled by mic'rocontroller' A.

ws _______-,
lOAD

lOBO

10Al

1081

IOA2

1082

IOA3

1083

10M

1084

lOA5

IOB5

IOA6

1086

IOB7

.L-....,..._-+__ WA

'RDA

eSA

RDS

ess'

FIGURE 2. Schematic of register interface.

Data Transfer
In order to read data from the mailbox, the microcontroller must initiate a
read cycle addressing the mailbox. The
read signal (ROA for microcontroller A,
ROB for microcontroller B) enables the
tri-state outputs of the 5C060, revealing
the appropriate data. Spurious read cycles are avoided by logically combining
the read signal with a chip select signal
(CSA or CSB) within the chip. The.exampie shown.:utilizes address bit /( 15 as the

24 ·vee'
23 ·RDB

WRB 1
eSA· 2
3

~.~.-

Group A
(microcontroll~r

IOA3IOA4
IOA5IOA6·
IOA7·

22
21
20
19
,,18
17
)6
15

:g.
IOA2·
5

SeD60

7
8·
9
10
RDA· 11
GND- 12

' :,

·IOBl
·IOBO
·IOB2 J. '
Group B
·IOB3
(microcontrOlier B),'
·IOB4
·IOB,5
·IOB6
-IOB7 .

14 ·eSB
13' ·WRA·

FIGURE 3. Pin-out for register interface.

VLSI SYSTEMS DESIGN

January 1987

Designer's Comer

WFIA
CSA
AST

:=!;:~==:r------~----~--~---:----~~--- WA

AOB
CSB -TJ"''''---'

WFlB-H--d

INTEl

}------.----~~+-~--r_----~---WB

~t-----ti--~[J~-INTA

OBEI
IBFI
OE

:::::::::~:::;::::::::::::~______~~~

FIGURE 4. Schematic of control logic. ,
chip-select'signal, thereby rese~i,ng the
upper 32K'bytes of memory space for the
mailbox. '
'
"
Protoc,ol, Control LO,g1c,

flag,is reset when the recipient controller
reads the' data from the mailbox.
Input Buffer Empii This flag indicates" thal' 'there is rio message in the
'mailbox and that the mailbox can be
Having defined the,memory'section ofwlitten without corrupting the data. This
the mailbox, we next must orchestrate flag is set whenever a controller reads
the control logic. To guarantee reliable data from the mailbox. The flag remains
data transfers, both microcontrollers set until data is placed' in the mailbox.
need feedback about the staius of their ' Interrupt. The 5C031 is programmed
'to supply interrupts to both 'microconrespective input and output buffers.
'In order to achieve a maximum data trollers involved, wheneither'one of two
transfer rate, an interrupt-driven proto- 'events occurs. First, the recipient microcol may be used. The signals necessary, controller receives an interrupt when its
to achieve the transfer protocol are:
, OBF .flag,goes ac~ive" This ,signals the
recipient that datl! is available in the ,
OBFA (A'S output buffer full), .
mailbox. Secoridly, the originator miOBFB (B'S output ,buffer full)
crocontroller receives an interrUpt when
IBEA (A's input buffer empty)
data placed by' that microcontroller in
IBEB(B's input buffer empty)
INTA (A'S data ready interrupt)
the ' mailbox has been received by the
, ,
,
' recipient microcontroller. This interrupt
, INTB (~'s data ready intern/pt)
indicates that data has been received and
Further definitions of the control signals, that' it is safe to wriie data to the
can be made as follows.
' rnailbox.
Output Buffer FulL Tilis flag' is set '
The signals described above form the
whenever a controller writes to the mail- basis for clean and efficient data transfer
box. The flag remains' valid until the between the two microcontrollers. The
second controller has read the data., The transfer time is limited only to the over- ,

h~ad of the interrupt service routines.
The 5C060 can accept data at clock rates
in excess of 20 MHz.

Programming the EPLDs
Figures 2 and 3 show the schematics
and pin-out for the memory section, and
Figure 4 is a schematic of the protocol
sections in the mailbox memory. Using
Intel's, Programmable Logic Development System, these schematics can be
transformed with ease, into the logic
equations that represent the desired
function, The development system accepts a variety of entry methods, including schematic, net list, state machine,
'and text' file ,entry,
Once'the design has been entered, the
file is submitted to the Logic Optimizing
Compiler (LOC) , which performs an optionalBoolean minimization, including
De" Morgan's inversion, and logically
fits the de~ign into the target EPLD.
The development system generates
, three output files. The Logic Equation
File (LEF) contains the result orthe mini~
mization process, the Utilization Report
File (RPT) contains the final device pinout, information about the internal logic
.fOuting, and a percent utilization for
pins, macrocells, and product terms. Finally, .the JEDEC file (JED) contains the
device programming information required to program'the EPLDs. These files
are available from the authors.
Programming Of the EPLDs is accomplished through Intel's Logic Programming Software (LPS) and the iup-PC programming hardware. Designs also may
'be logically simulated through the use of
Intel's'FSIM software.

Summary
Applications such as industrial automation often require communication beiween lllUltiple microcontrollers. Unfortunaieiy this com'munication is
hampered by the port orientation and
lack of bus control signals within the
microcontroller environment. One solution-,as prese,nted here-is the mailbox
memory. The mailbox memory serves as
an effective method for transferring data
between 'inicrocontrollers, while the'
flexibility of the EPLDs serves as an
effective way, to' implement the mailbox
0
itself.

"LSI SYSTEMS DESIGN

2-257

January 1987

inter

AR-454
I~-----DE-S-IG-N-A-PP-L-.IC-M~IO-N-S--~~I
ELECTRONIC DESIGN EXCLUSIVE

Regain lost 1/0 ports
with erasable PLDs
Daniel·E.

Smith.cinc::i Thomas B. Bowns

ntel cOrp., 1900 Pr<*ie city Rd., Folsom, CA 95630; (916) 351·2747.
I

. .

As a means for reconstru.cting or regaining microc
controller.
controller I/O ports lost to memory expansion,
These techniques not only reconstruct ports on
erasable programmable logic devices, or EPLDs;' any available microcontroller, but they also are'
contain all the necessary functions. In fact, EPLDs
suited to 'adding new ports. For the 8096, the dePerform more functions than most programmable
signer can add two new ports, 5 and 6, by changing
logic arrays, and offer the additional benefits of
to IFFC~IFFF-the,hexadecimal address range in:
EPROM-like erasability, the low power consump- . . which the external memory is deseleCted. The new
tion of CMOS technology, and gate densities near . ports create a system with 56 I/O signals. The
. those oflow-end gate arrays.
tradeoffs of this addition are the board space·
Lost I/Op6rts can be externally reconstructed
needed for two more. EPLDs and two more bytes of.
_ _ _ _ _ _ _ _ _ _.,__
with standard SST reserved memory space at IFFCand IFFD.
packages. EPLDs; howThe first consideration in reconstructing a port is
ever, supply an alternathe microcontroller's' fixed-memory and I/O ad.tive that reduces the exdress map: In the 8096, memory-address rariges 0
t e i nal' a p p ro a c h':s· to FF and '2000-3FFF contain on-chip registers, inimpact on:powi:r and
terrupt vectors, factory 'test code', and program
space cOnsumption."
'. memory. Expansion memory can go into the 100'to
T h,ll com p ut i n g . "lFFDrange, a capacity of8kbytes minus the first
power of one-chip mi256 and the last 2 bytes, and into the'4(lOO to FFI'F
crocontrollers plays a .range, another8kbytes.
role in many applicaThe microccintroller has five 8-bitports, three 'of
.
tions~ But the growing
which (0 to 2)are dedicaled to. i/b functions. Ports
complexity ofthesedevices,'as designers shiftfrom
~ and 4, however, are, memory-mapped to If FE
8- to 16-bit controllers, has strained their lio ca~ .' .and I FFF, respectivi:Iy. These two ports reside
pacity.
. right above the lower section ofexpansion memory
space. (Other microcontrollers have the same funcA typical 8-bit iriicrocontroller in a 40-pin pack. age contains a 4- to 8-kbyte program memory and
tions, buttheir address ranges may vary;)
32 I/O pins, usually grouped into 8-bit' ports;' The .' External memory, therefore, collnects to the pins
16~bit devices contain 8-kbyte memories and up'io . reserved 'for ports 3 and 4, eliminating them·as gen40 I/O pin~ in packages that range from 48 to 68, .' eral I/O ports. Reclamation of these ports calls for
external latches and dC:code logic that disables' the
pins. The.possible number of ports falls short for
, some complex tasks in switching circuits, robotics, 'external memory and enables the latches at 1FFE
and automotive s y s t e m s . a n d I F F F . This logic decodes signais Ao and BYte
, The I/O shortage is aggravated when the chip's
High Enable,'BHE; to select ports '3 and 4. The
internal program memory is too small for a given
ports are selected either ~parateJy for8-bit data
task. While tacking on external memory is easytransfe~ or together for I ~-bit trallsfers.
.
enough, the addition consumes I/O pins.
The microcontroller mUltiplexes address and
data.on signal lines ADolo AD. s• Au result, AdAlthough some details vary, the basic techniqueS
for reconstructing these lost I/O ports with EPLDs
dress Latch Enable, ALE, must latch the address as
are the same for most microcontrollers. An example
each bus cycle starts and keep it there for the cycle
describes a 5C 121 EPLD and an 8096 16-bit miduration. Then the lines can transfer data throughcrocontroller, noting details specific to the microout the cycle. Because BHE has the same timing as

Erasabie PLDs· cut the
space and power
usually needed to
reconstruct 110 ports.
,They can even build
new ports, adding to "
a chip's capabilities.

"Reprinted with permission from Electronic Design (Vol. 35. No.7) March 19. 1987. Copyright 1987 Hayden Publishing Co., Inc.,
a subsidiary of VNU."
2-258 .

DESIGN APPLICATIONS. Erasable PLOs restore ports
the address, ALE must also latch BHE.
Reconstruction of both ports without EPLDs requires
14 SSI packages if the high-current sink capability of
open-collector drivers is needed. If not, nine packages
will do.
Besides the address-decoding logic, the input ports
need octal latches. The outputs contain octal latches, but
inverting buffers are also needed. If the output does include open-collector drivers, the designer must add another set of inverting buffers to compensate for the
drivers' inversion of the signal. In addition, a discrete flipflop latches BHE, and discrete gates decode the port ~e
lection and RD and WR signals.
On the other hand, reconstructing ports with EPLDs
requires no logic outside of the EPLDs themselves (Fig.
I). Each device decodes its respective memory-mapped
address, and one device disables the external memory at
both 1FFE and 1FFF.
The EPLDs can sink 4 rnA, which puts them in the
same range as an SSI version without open-collector
drivers. The designer can add open-collector drivers if a
higher-current sink is needed.
The design process leading to port reconstruction be-

gins with defining the functions required of the EPLD
and then creating a design file that can be translated into
a Jedec file. Next, the designer programs the EPLD and
tests the final circuit. Software can automate much' of this
procedure.
The first step is to list the functions the EPLD must
perform. Then the designer identifies which EPLD feature best satisfies that need, because as with SSI logic, the
device can accomplish its task in different ways.
.
In general, a device reconstructing a port must latch
and decode address information from a multiplexed bus.
The chip then produces an internal port-selection signal
and an external memory-selection signal; the latter in address range IFFE:IFFF. Moreover, the device acts as a
bidirectional data path and decodes the RD and WR
signals, routing the data witli the port-selection signal
.
(Fig. 2).
Drawing a schematic diagram of the EPLD helps isolate the circuit into functional blocks. In the example,
combinatorial logic and three latches do the decoding at
port 3.
Address lines ADI through ADII pass through an
AND gate and are latched as LADA • Address lines AI2
+5V

• • • • • •• •. . . . . . . . . . . . . . . . . . .IIIfAD.-AO,.
5C121

. •III!~ADo~AO, EPuj
ALE WR

Mes
SHE

+5V'.

.JllII!-1111AOQ-AD.·

+5V

27C84-15
EPROM

ALE WR

AOa -AD'5
5C121

EPLD

1..__I11!111. . ._ - - - - - - -. .----.-~AD,~Ao'
1. Two erasable programmable logic devices contain all the logic required to reconstruct ports 3 and 4 of
an 8096 mlcrocontroller. The two latches and two EPROMs comprise the external memory.

Eiectronlc Design· March 19, 1987

2-259

and inverted signals AD,)
through AD,s pass through an
AND gate and a'relatched as
LAD o. These two latched signals pass through another
AND gate to create the' Memory Disable, Signal, MDS,
whichdeactivales the
EPROMs. Combined with
LADo (address signal ADo
inverted and latched), LADA
and LADo generate the portselection signal.

Ao.,

PARALLEL FORMAT SAVES TIME
\

AD..

The EPLD decodes and
latches signals AD', through
AD" and ADI2 through AD is
in parallel to minimize the time
between address setup and
ALE going low. An inverted
ALE clocks the latches; which
also store decoded addresses
while the microcoritroller transfers data over the bus.
Two combinatorial-output,
internal feedback (COIF)
primitives create a doublefeedback loop with all output
enables to the microcontroller
bus controlled by DE" which is
active during read operations.
Output enables on the I/O side
of the EPLD are controlled by
, OE2, which is active during
,AD"o---"
" write operations. Thus data is , AD.. 0-.,--.....:.--......
valid at theinputs or outputs
, only while the~ropriate com,AD ••
mand, RD or WR, is active.
lf the application calls for
AO,.O'-.,--1
latched outputs, the designer
ALE 0---"':---;......1
can create them from logic on
AD o--..,...;..-----'--J
the EPLD. One configuration is
WR 0-----.,.-+--'-----'
a D-typeedge,ofWIt
latch activated
SHE ~
tniiling
(Fig.by
3).the
In '---:-_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..;.....;..._ _ _--.J
2. The schematic lor the port 3 EPLD contains a bidirectional path that In-

this circuit, the outputs are al- cludes parallel address decoding that speeds circuit operation. In the port 3
ways en'abled, except during , device, Ao Is Inverted and 'latched, then used to qualify reads and writes; the,
,'reads, whim they are placed in a ' part 4 EPLD relies on BHE for qualification.
high-impedance state. The Reset signal clears the outputs to a
logic 0 during initialization. '
The fourth port's schematic
varies little from that of the
third. Because port 4 handles
data transfers on the microElectronic Design' March 19.1987

2-260

DESIGN APPLICAnONS • Erasable PLDs reslore ports

controller's high byte, the data path connects to ADs
throu.gh AD'5' The BHE signal replaces ADo and becomes LAD, which combines with LADA and LADB to
select the correct port.
A microcontroller with a different address map or bus
interface may require some variations in address decode
logic. The basic techniques for regaining I/O ports with
EPLDs, however, remain the same.
DESIGN FILE CREATED

The next step in the port-reconstruction process is to
create from the schematic diagram a design file that can
be automatically converted to a Jedec file by Intel's Programmable Logic Software II (iPLSII) program. Four
types of inputs are acceptable: a net list file, Boolean
equations, state variables, and files from any of several
schematic-entry packages that run on personal com put-

ers. The designer can write a net list file with a wordprocessing program in a non document mode, but an easier way is to work with iPLS II's Logic Builder.
The Logic Builder prompts the user for the information
it needs. After establishing the file with some background
information, the program asks for lists of all the input and
output pin names (the user can assign a name to a specific
pin number). Next come the internal assignments and
connections, and finally, the logic equations needed.
The designer must list all the COIFs that form the bidirectional data path. For example, the entries that create
the data line between ADo and P3 0 (see Fig. 2 again) are
as follows:
ADo, ADo = COIF (P3 o, OE.)
P3 o, P3 0 = COIF (ADD, OE 2 )
The iPLS II program contains a logic-optimizing compiler that translates the schematic's net list, or other suitable input, into a Jedec programming file. The compiler,
which is selected from the program's main menu, optimizes the logic equations and assigns I/O pins and other
EPLD resources.
ERROR MESSAGES POINT OUT PROBLEM

RD WR

3. If a designer needs latched outputs, they can be
buill without additional logic. This D-type flip-flop is
made of logic elements contained in the EPLD.

ALE

The program's outputs are the programming file and a
. device report file that shows the pinout of the programmed device and describes the use of the device's resources. If the compiler cannot translate the file, error
messages indicate the design-file entry that caused the
problem.
Programming the EPLD is very similar· to programming EPROMs. The designer connects an EPLD programming module to the workstation, inserts an unprogrammed device into the socket, and calls up the

Clock

f--,-Tm~

'M\
lTd

Tln = 12 ns

Trt =

7 ns
5 ns

T., = 411 ns

Tet =' 5 nS

T. '" 11 ns

T", = 11 ns

4. A block diagram of an ELPD's intemal delays shows how users can determine the maximum delay for
each signal path and, as a result, the port's maximum operating frequency.

Electronic Design' March 19. 1987

2-261

DESIGN APPUCATIONS • Erasable PLOs restore ports

programming menu. The menu asks for the device's type
and the Jedec file name, and the system then programs
and verifies the chip.
Considering how straightforward the port-reconstruction functions are, the best test of the programmed
EPLD is to plug it into a circuit and see if it works. An
EPROM-based microcontroller with some simple read
and write routines to exercize the device works well. The
designer can also use an in-circuit emulator for the microcontroller, if one is available.
Any bugs can be fixed quickly. To correct a bug the
user erases the EPLD file and changes the design file,
which then can be recompiled and the device reprogrammed.
A timing analysis confirms the EPLD's compatibility
with different microcontroller clock speeds. The analysis
amounts to adding the internal delays for paths through
the EPLD and comparing these path delays to the microcontroller's timing requirements.
The three paths of interest are Address Setup to ALE,
which must take no longer than 116 ns for an 8096 operating at 6 MHz; and no longer than 50 ns at 10 MHz. Other
maximum values are: Data Valid From RD, 358 ns and
230 ns; and Data Valid Before Write, 272 ns and 130 ns.
A block diagram of the specific device with each internal delay is needed for the timing analysis. For the example circuit, the Address Setup to ALE delay for the port 3
EPLD is 49 ns (Fig. 4). This value, achieved by decoding
and latching AD! to AD!! in parallel with AD!2 to AD!5,
just meets the maximum delay at 10 MHz.
The delay for Data Valid From RD is the sum of delays
in tile enable path and the data path, or 136 ns. The delay
path for the write operations is shorter:- It is that for the
enable path added to 41 ns for the data path (after eliminating a 30-ns overlap in enable and data timing), or
106 ns. Both are well within limits. 0

Daniel E. Smith, a senior technical writer at Intel, has
also worked in microcomputer-systems testing and
written manuals for microprocessors, development
software, and bubble memories. He has a BA in history
from San Jose University and an MA in biblica! studies
from the Graduate Theological UnionfJesuit School of
Theology in Berkeley, Calif
Thomas B. Bowns is an application engineer for Intel's EPLD operation. He also has worked as a technician on the company's EPROM line. Bowns studied
digital and microwave electronics at American River
College in Carmichael, Calif.

Electronic Design' March 19. 1987

2-262

Advanced Architecture

EPLDs

5AC312
1-MICRON CHMOS

ERASABLE PROGRAMMABLE
LOGIC DEVICE
Performance LSI Semi-Custom
• High
Logic Alternative for Low-End Gate

Feedback on All Macrocells for
• Dual
Buried Registers with Bidirectional 1/0
2 Product Terms on All Macrocell
• Control.
Signals
. CHMOS III-E EPROM Technology,
• based; UV-Erasable
UV Erasable Array for 100% Generic
• Testability
Programmable Security Bit Allows
• .100%
Protection of Proprietary Designs
Programmable Low-Power Option for
• Standby Operation; 100 /LA Typical

Arrays, TTL, and 74HC- or 74HCT SSI
and MSI Logic
Speed tpd (max) 25 ns, 50 MHz
• High
Performance Pipelined, 33 MHz with
Feedback
12 Macrocells with Programmable I/O
• Architecture;
Up To 22 Inputs (10
Dedicated, 12 I/O) or 12 Outputs

•

8 Programmable Inputs Individually
Configurable as Latches, Registers or
Flow-Through

Standby Current

Software-Supported Product Term
• Allocation
between Adjacent

in 24-Pin 0.3" DIP and 28-Pin
• Available
PLCC Packages

Macrocells
Ill!!

(See Packaging Spec., Order Number # 231369)

Programmable Output Registers
Configurable as D, T, JK, or SR Types

CLK/INP1
1/0.11

Vee
1/0.12

LlNP1

1/0.9

LlNP2

1/0.10

LlNP2

1/0.10

LlNP3

1/0.7

LlNP3

1/0.7

LlNP4

1/0.8

LlNP4

1/0.8

LlNP5

1/0.6

LlNP5

1/0.6

LlNP6

1/0.5

LlNP6

1/0.5

LlNP7

1/0.4

LlNP8

1/0.3

1/0.1

1/0.2

GND

ILE/ICLK/INP2
290156-1
290156-2

Figure 1. Pin Configurations

3-1

November 1988
Order Number: 290156·002

5AC312

a highly flexible macrocell and liD structure. The
5AC312 has been designed to effectively implement
both combinational-register and register-combinational-register forms of logic to easily accommodate
state machine designs.

INTRODUCTION
The Intel 5AC312 CHMOS EPlD (Erasable Programmable logic Device) represents an innovative
approach to overcoming the primary limitations of
standard PlDs. Due to a proprietary liD architecture
and macrocell structure, the 5AC312 is capable of
implementing high performance logic functions more
effectively than previously possible. It can be used
as an alternative to low-end gate arrays, multiple
programmable logic devices or lS-, HC- or HCT SSI
and MSI logic devices. Input and macrocell features
for the 5AC312 are a superset of features offered by
other PlD-type products.

Figure 2 shows a global view of the 5AC312 architecture. The 5AC312 contains a total of 12 liD macrocells, 8 user-programmable input structures, and 2
additional inputs that can be programmed to serve
as either combinatorial inputs or clock inputs. Each
of the eight inputs can be individually configured as
a latch, register, or flow-through input. Input latchesl
registers can be synchronously or asynchronously
clocked.

The 5AC312 uses advanced CHMOS EPROM cells
as logic control elements instead of poly-silicon fuses. This technology allows the 5AC312 to operate at
levels necessary in high performance systems while
significantly reducing the power consumption. Its
programmable stand-by function reduces power
consumption to almost "zero" in applications where
a slight speed loss is traded for power savings.

Each macrocell is further sub-divided into 16 Product Terms with 8 Product Terms dedicated to the
control signals DE, PRESET, ASYNCH. ClK and
CLEAR, and 8 Product Terms available for the general data array (see Figure 3).
The basic macrocell architecture of the 5AC312 includes a user-programmable AND array and a userconfigurable OR array. The inputs to the programmable AND array originate from the true and complement signals. from the programmable input structure, the dedicated inputs, and the 24 feedback
paths from the 12 liD macrocells.

ARCHITECTURE DESCRIPTION
The architecture of the 5AC312 is based on the familiar "Sum-Of-Products" programmable AND, fixed
OR structure, though the 5AC312 macrocell contains a number of significant functional enhancements. This device can implement both combinational and sequential logic functions through

Programmable Input Structure
Figure 4 shows a block diagram of the 5AC312 input
architecture. This device contains 8 user-program-

3-2

inter

5AC312

RING 1

GLOBAL
CLOCK

CLK/INP1

I
I
I
I
I
I

r------

1/0.1

1/0.2

I
I

LOGIC ARRAY
LlNP1

I
I
IL ______
I

1/0.3

-,I
I
I

r------

LlNP2

1/0.4

I
I
I
I ______
L

LlNP3

I
I
I
I
I

1/0.5

._-----

1/0.6

r------

1/0.7

LlNP4

LlNP5

I
I
I

r------

LlNP6

1/0.8

I
I
I
I
IL ______

LlNP7

I
I
I

1/0.9

-,
I
I

r------

LINP8

1/0.10

I
I
I

I
I
L
___ "; __

ILE/ICLK/INP2

1/0.11

I
I
I'
I
I

._----RING 2

I/Oj2

290156-3

Figure 2. 5AC312 Architecture

3-3

(
TO NEXT
MACROCELL

LOGIC ARRAX

fROM NEXT
MACROCELL
OUTPUT

PRESET

"TI

IS'
c
(I)

en
»
0

II II II II

LOWER·HALf

OUTPUT
MUX

Co)

.....
I\)

Co)

./:..

m
DI
1/1

(;'

s:
DI

..
!&
en
-....

W~T:~

r-:~ERT c.RL/j

D/T

MACROCELL
REGISTER

....
N

n
0

n
~

(I)

CLEAR
fROM PREVIOUS
MACROCELL

290156-4

2:2J
IiUil
F

~
~
~

2:2J
~

inter

5AC312

INP D-----+tIN
PIN

OUT~------~

LOGIC

ARRAY

P-TERM

ILE/ICLK
PIN

C>------------------....I
290156-5

NOTE:

Flow-through input selected by connecting ILE P-Term to Vee.

Figure 4. 5AC312 Input Structure

mabie input structures that can be individually con·
figured to work in one of five modes: .
-

to derive an input clock signal for the input structure.
Because the clock signal for each input structure
can be individually selected, a mix between synchr()nously and asynchronously clocked input structures
is also possible.

Input register (O-register), synchronous operation
Input register (O-register), asynchronous operation
Input latch (O-Iatch), synchronous operation
Input latch (O-Iatch), asynchronous operation
Flow-through input

Table 1 shows the input latch/register function table
with respect to the synchronous ILE/ICLK input.
Table 1. 5AC312 Input Latch/Register Functions

The configuration is accomplished through the programming of EPROM architecture control bits by
the logic compiler and programmer software. If synchronous operation is chosen, the ILE/ICLK/INP
becomes an ILE/ICLK (Input Latch Enable) input
global to all input latch/register structures. For asynchronous operation, ILE/ICLK/INP can be used as a
normal input (flow-through input) to the device while
a separate Product Term in the control array is used

Input Type

ILE/ICLK

Latch
Latch
Latch
O-FF
O-FF
Flow-Through
Flow-Through

H
H
L

H
L

J.
J.

H
L
H
L

H
L
an
H
L
H
L

H = HIGH Level

3-5

X
X

L = LOW Level

X = Don't Care

inter

5AC312

. Macrocell Array

Example: .
The logic function in macrocell 4 require 16
p-terms. lri this case, the iPlS II software allocates 4
p-terms from the previous macrocell in Ring 1 (macrocell 3) and 4 p-terms from the next macrocell in
Ring 1 (macrocell 5) to accumulate a total of 16
p-terms (8 + 4 + 4). This implementation leaves
macrocells 3 and 5 with a remainder of 4 p-terms
each. These remaining p-terms in macrocells 3 and
5 can also be allocated away to or can be supplemented with p-terms from their respective previousl
next macrocells in Ring 1.

Each of 12 macrocells in the 5AC312 contains 8
p-terms (Product Terms) to support logic functions.
These 8 p-terms are subdivided into 2 groups each
containing 4 p-terms. This grouping of p-terms supports the proprietary p-term allocation scheme.
Each macrocell can be configured as a D, T, RS, or
JK register. The 8 p-terms for control functions are
organized so that 2 p-terms support each of the four
control signals. Control signals in the 5AC312 are:
Output Enable (DE), asynchronous liD register preset (PRESET), asynchronous clock for liD registers
(ASYNCH. ClK), and asynchronous liD register reset (CLEAR).

Applying this scheme to the 5AC312 it becomes
clear that any macrocell inside the device can support logic functions requiring between 0 and 16
Product Terms. Product Terms allocated away from
a macrocell do not affect thatmacrocell's output
structure. If all Product Terms are allocated "away"
from a macrocell, the input to thatmacrocell's liD
control block is tied to GND. This polarity can be
changed by programming the invert select EPROM
bit. The liD register as well as all secondary controls
to this liD control block are still available and can be
used if needed.

ClK is a global clock signal that can be used to
synchronously clock any or all macrocell registers. It
can be used as an input to the logic array at the
same time as a macrocell. clock. When ClK is not
used as a synchronous clock, it functions only as a
dedicated input to the logic array.

Combinatorial Configuration
The macrocell register can be bypassed to implement combinatorial logic functions. When configured
to provide combinatorial logic, only the DE control
signal is used.
.

The Product Term allocation scheme described
above is automatically supported by iPlDS II V2.0
and is transparent to the user. Users can still use
explicit pin assignments, but should assign pins in a
way that does not conflict with p-term allocation.

Invert Select Bit

Table 2. Product Term Allocation Rings
Ring 1
Ring 2
Current Next Previous Current Next Previous
Macro- Macro- Macro- Macro- Macro- Milcrocell
cell
cell
cell
cell
cell
1
2
6
8
12
7
., 1
9
7
2
3
Ii
3
4
2
9
10
8
4
5
3
10
11
9
5
12
6
4
11
10
6
1
5
12
7
11

An invert select EPROM bit is used to invert the
product term input into each macrocell register, including double inputs on JK and SR registers. This
invert option allows the highest possible logic utiliza"
tion by use of DeMorgan's logic inversion.

Product Term Allocation
Product Term allocation is defined as taking logic
resources (p-terms) away from macrocells where
they are not used to support demand for more than
8 Product Terms in other areas of the chip. In the
5AC312, this allocation can occur in increments of 4
p-terms between adjacent macrocells.
The 12 macrocells available in the 5AC312 are
grouped into two "rings" with 6 macrocells per ring.
Product Terms can be allocated in a "shift register"
mode inside a ring; allocation of Product Terms between the rings is not supported. The two rings are
shown in Figure 2 and listed in Table 2.

3-6

5AC312

LOGIC ARRAY
LOWER HALF
P-TERMS 1-4
MACROCELL

P-TERMS ALLOCATED TO
MACROCElL #4

(NEXT MACROCELL IN RING)

UPPER HALF
P-TERMS 5-8

MACROCELL

UPPER HALF'
P-TERMS 5-8

P-TERt.4S ALLOCATED TO
t.tACROCElL #4

(PREVIOUS MACROCELL IN RING)

MACROCELL

290156-6

Figure 5. Product Term Allocation (8 + 4 + 4)

3·7

5AC312

savings. When the Turbo Bit is programmed
(TURBO = ON). the device is optimized for maximum speed. When the Turbo Bit is not programmed
(TURBO. = OFF). the device is optimized for power
savings by entering standby mode during periods of
inactivity.

Macrocelil/O Control Block
Each macrocell in the 5AC312 has the ability to implement D. T. SR. and JK registered outputs as well
as combinatorial ou/puts. The asynchronous set and
reset inputs to each macrocell.register allows implementation of true SR Flip-Flops. Registered outputs
. may be clocked from the synchronous ClKIINP1
pin or asynchronously clocked by the 2 Product
Terms available for ASYNCH. ClK. The 5AC312
also features separate input and. feedback paths
(dual feedback) on all macrocell I/O control blocks.
This enables the designer to utilize input pins when
the associated macrocells have been assigned a no
output with buried feedback attribute. Multiplexed
I/O is accomplished by controlling the output buffer
associated with each macrocell using the 2 Product
Terms set aside for implementing an OE function.

Figure 6 shows the device· entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected. the device returns to active mode. Wakeup time adds an
additional 20 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.
After erasure. the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON). the device never enters
'
standby mod~. .

Power-On Characteristics
The Macrocell registers of the 5AC312 will experience'a reset to their inactive state (logic low) upon
Vee power-up. Using the PRESET function available
to each macrocell. any particular register preset can
be achieved after power-up. 5AC312 inputs and outputs begin responding within 10 p,s (6 p,s typical)
. after Vee power-up or .after a power-Ioss/power-up
sequence. Input registers are not reset on power-up
and are indeterminate. Input latches reflect the state
of the input pins on power-up.

inteligentProgramming™ Algorithm
The 5AC312 supports the inteligent Programming algorithm which rapidly programs Intel H-EPlDs.
.EPROMs and Microcontrollers while maintaining a
high degree of reliability. It is particularly suited for
production programming environments .. This method
greatly decreases t~e overall programming time
while programming reliability is ensured as the incremental program margin of each bit has been verified
in the programming process. (Programming informa-'
tion for. the 5AC312 is available from Intel by request.)

Automatic Standby lIIIode
The 5AC312 contains a programmable bit. the Turbo
Bit. that optimizes operation for speed or for power

INPUT
FIRST

----t

~--------------~

,..--------1

LAST
INPUT _ _.....J

OUTPUT

CURRENT
DmA

VALID OUTPUT

ACTIVE MODE

Icc

~--------------------~==~====~~------~~----290156-19
Figure 6. 5AC312 Standby and Active Mode Transitions

3-8

infef

5AC312

ERASED STATE CONFIGURATION

LATCH-UP IMMUNITY

After erasure and prior to programming, all macrocells are configured as combinatorial, inverted outputs with output buffers three-stated. Inputs are configured as synchronous registers.

All of the input, 1/0, and clock pins of the device
have been designed to resist latch-up which is inherent in inferior CMOS structures. The SAC312 is designed with Intel's proprietary 1-micron CHMOS
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -O.SV to Vee + O.SV. The
programming pin is designed to resist latch-up to the
13.S maximum device limit.

ERASURE CHARACTERISTICS
Erasure time for the SAC312 is 1 hour at
12,000 JJ-W/cm 2 with a 2S37A UV lamp.

DESIGN RECOMMENDATIONS
Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types of
fluorefcent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
. room level fluorescent lighting could erase the typical SAC312 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device window to prevent unintentional erasure.
~

For proper operation, it is recommended that all input and output pins be constrained to the voltage
range (GND < (VIN or VOUT) < Vee. All unused
inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capacitor of at
least Q.2 JJ-F must be connected directly between
each Vee and GND pin.
As with all CMOS devices, ESD handling procedures
should be used with the SAC312 to prevent damage
to the device during programming, assembly, and
test.

The recommended erasure procedure for the
S~C312 is exposure to shs>rtwave ultraviolet light
with a wavelength of 2S37A. The integrated dose
(Le., UV intensity x exposure time) for erasure
should be a minimum of forty (40) Wsec/cm 2.

FUNCTIONAL TESTING
since the logical operation of the SAC312 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application-independent test
patterns. EPROM cells in the SAC312 are 100%'
tested for programming and erase. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.
'

The erasure time with this dosage is approximately 1
hour
using
an
ultraviolet
lamp
with
a
12,000 JJ-W/cm 2 power rating. The device should be
placed within 1 inch of the lamp tubes during exposure. The maximum integrated dose the SAC312
can be exposed to without damage is
72S8 Wsec/cm 2 (1 week at 12,000 JJ-W/cm2). Exposure to high intensity UV light for longer periods may
cause permanent damage to the device.

The testability and reliability of EPROM-based programmable logic devices are important features over
similar devices based on fuse technology. Fusebased programmable logic devices require a user to
perform post-programming tests to insure device
functionality. During the manufacturing process,
tests on these parts can only be performed in very
restricted manners to prevent pre-programming of
the array.

DESIGN SECURITY
A Security Bit provides a programmable security op,
tion to protect the data programmed in the device.
Once this bit is set during programming, subsequent
attempts to read the device architecture information
are prevented. This method provides a higher degree of design security than fuse-based devices,
since programmed EPROM cells are invisible even
to microscopic examination. The Security. Bit (also
called the Verify Protect Bit), along with all the other
EPROM cells, is reset by erasing the device.

3-9

inter

5AC312

Detailed information on the Intel Programmable Logic Development System II is contained in a separate
Intel data sheet. (Order Number: 280168)

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM II (iPLDS II)
Release 2.0 of iPLDS II provides all the tools needed
to design with the 5AC312 EPLD. In addition to providing development assistance, iPLDS II insulates
the user from knowing the intricate details of EPLD
architecture (the machine will optimize a design to
benefit from architectural features). It contains comprehensive third generation software that supports
four different design entry methods, minimizes logic,
does automatic pin assignments and produces the
best design fit for the selected EPLD. It is user
friendly with guided menus, on-line Help messages
and soft key inputs.

tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

ADF PRIMITIVES SUPPORTED
The following ADF primitives are supported by this
device:

In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
. code output files which can be downloaded to other
programmers as well.
The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be· entered
using schematics. A more integrated schematic entry method is provided by SCHEMAII-PLD.a lowcost schematic capture package that supports EPLD
primitives and user-defined macro symbols.
SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both
SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entrY
and State Machine design entry.

INP

NOTF

LlNP

JOJF

RINP

JONF

CONF

SONF

COCF

SOSF

COIF

TOIF

RONF

TONF

ROlF

TOTF

RORF

CLKB

NOCF

LlNB

NORF
NOJF
NOSF

ORDERING INFORMATION
tpD teo 'MAX

The iPLDS operates on the IBMt PC/XT, PCI AT, or
other compatible machine with.the following configuration:

(ns) (ns) (MHz)
25

Order
Code

Package

D5AC312-25 CERDIP Commercial

1. At least one floppy disk drive and hard disk drive.

P5AC312-25 PDIP

2. MS-DOStt Operating System Version 3.0 or
greater.

N5AC312-25 PLCC
30

3. 512K Memory (640K recommended) ..

Operating
Range

D5AC312-30 CERDIP Commercial
P5AC312-30 PDIP

4. Intel iUP7 PC Universal Programmer-Personal
Computer and GUPI Adaptor (supplied with
iPLDS II)

N5AC312-30 PLCC
35

5. A color monitor is suggested.

D5AC312-35 CERDIP Commercial
P5AC312-35 PDIP
N5AC312-35 PLCC

3-10

in~

5AC312
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vee) (1) .......... -2.0Vto + 7.0V
Programming Supply
Voltage (Vpp) (1) ............. -2.0V to + 13.5V
D.C. InputVoltage (VI)(1, 2) ... -0.5V to Vee

+ 0.5V

Storage Temperature (Tstg) ..... -65°C to + 150°C
Ambient Temperature (Tamb) (3) .. -10°C to+ 85°C

NOTICE Specifications contained within the
fol/owing tables are subject to change.
NOTES:

1. Voltages with respect to GND.
2. Minimum D.C. input is -O.SV. During transitions, the inputs may undershoot to -2.0V or overshoot to
less than 20 ns under no load conditions.
3. Under,bias. Extended temperature range versions are available.

+ 7V'for periods of

RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

4.75

5.25

Input Voltage

Vee

Output Voltage

Vee

Operating Temperature

+70

°C

Vee

Supply Voltage

VIN

Input Rise Time

500

Input Fall Time

500

D.C. CHARACTERISTICS
Symbol

TA = O°Cto + 70°C, Vee = 5.0V ±5%

Max

Unit

High Level Input Voltage

2.0

Vee + 0.3

VIL(4)

Low Level Input Voltage

-0.3

0.8

VOH(S)

High Level Output Voltage

VIH(4)

Parameter

Min

Typ

2.4

Test Conditions

10 = -4.0 mA D.C.,
Vee

min.

10 = 8.0 rnA D.C.,

VOL

Low Level Output Voltage

0.45

Input Leakage Current

±10

""A

Vee = max.,
GND < VIN < Vee

Output Leakage Current

±10

""A

Vee = max.,
GND < VOUT

-90

Vee = max.,
VOUT = 0.5V

150

""A

Vee

loz
.

Isd6)

Output Short Circuit Current

IS6(7)

Standby Current

ledB)

Power Supply Current

-30
100

10
I

min.

< Vee

Vee = max.,
VIN = Vee or GND,
Standby Mode
Vee = max.,
VIN = Vee or GND,
No Load, Input Freq. = 1 MHz
Active Mode (Turbo = Off),
Device Prog. as 12-Bit Ctr.

NOTES:

4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. Do not
attempt to test these values without suitable equipment.
S. 10 at CMOS levels (3.B4V) = - 2 rnA.
6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second.
7. With Turbo 6it Off, device automatically enters standby mode approximately 100 ns after last input transition.
S. See graph at end of data sheet for Icc vs. frequency.
3-11

5AC312

CAPACITANCE
Symbol

Parameter

Typ

Min

Max

Unit

CIN

Input Capacitance

COUT

1/0 Capacitance

. pF

Conditions
VIN =OV, f = 1.0 MHz
VOUT = OV, f = 1.0 MHz

CCLK

ILE/ICLK/INP2 Capacitance

VIN = OV, f = 1,0 MHz

Cvpp

Vpp Pin (CLK/INP1)

VIN = OV, f =1.0 MHz

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

.----5V
INPUT

3'°-v"20

0-A0:8>

TEST POINTS

vr:o

855.(1

OUTPUT
(INCLUDES JIG
CAPACITANCE)

.341.(1

290156-8

A.C. Testing: Inputs are driven at 3.0V for a Logic "I" and OV for
a Logic "'0". Timing Meas'urements are made at 2.0V for a Logic
"I" and O.BV for a Logic "0" on inputs. Outputs are measured at
a 1.5V point. Device input rise and fall times < 6 ns.

290156-7

1~-TEST POINTS--~

= 30 pF

A.C. CHARACTERISTICS
Symbol

From

TA ""'O°Cto

+ 70°C, Vee =

5AC312·25
Min

5.0V ±5%,Turbo Bit "On';(9)

5AC312·30

5AC312·35

Typ

Max

Typ

Max

Min

Turbo
Mode

Unit

Typ

Max

tpDl

Input

Comb. Output

+20

tpD2

1/0

Comb. Output

+20

tpZX(lO)

lorllO

Output Enable

+20

tpXZ(lO)

lorllO

Output Disable

+20

tCLR

Asynch. Reset a Reset ,

+20

tSET

Asynch. Set

+20

a Set

Min

Non·(ll)

NOTES:
9. Typical values are at TA = 25°C, VCC = 5V, Active Mode.
10. tpzx and tpxz are measured at .± 0.5V from steady-state voltage as driven by spec. output load. tpxz is measured with
CL = 5 pF.
11. If device is operated with TurboBit Off (Non-Turbo Mode), increase time by amount shown.

3·12

5AC312

SYNCHRONOUS CLOCK MODE (MACROCELLS) A.C. CHARACTERISTICS'
T A = o·e to

+ 7o·e, Vcc

Symbol

5.0V ± 5%, Turbo Bit On(8)
SAC312-30

SAC312-2S

Parameter

Min

Typ

Max

Min

Typ

Max

SAC312-35
Min

Typ

Max

Non-(11)
Turbo
Mode

Unit

fMAX

Max. Frequency (Pipelined)
1/tsu-No Feedback

MHz

fCNT

Max. Count Frequency
1/tCNT-with Feedback

28.5

MHz

tSUl

Input Setup Time to ClK

+20

tSU2

I/O Setup Time to ClK

' 20

+20

I or I/O Hold after ClK High

tco

ClK High to Output Valid

tCNT

Macrocell Output Feedback
to Macrocellinput-internal Path

tCH

ClK High Time

12.5

tCl

ClK low Time

12.5

0
10

15
40

+20

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) A.C. CHARACTERISTICS
T A = o·e to

+ 70·e, VCC

5.0V ± 5%, Turbo Bit On(8)
5AC312-25

Parameter

,Symbol

Min
fMAXI

Max. Frequency

tSUIR

Input Register/latch Setup Time
before IlE/IClK

tpul 12)

Minimum Input Clock Period

tHI

I Hold after IClK/llE

J.,

IClK

tEOI

IlE t to Comb. Output

Max

Min

Typ

Max

.40

5AC312-35
Min

Typ

Max

28.5

Non-(ll)
Turbo
Mode

Unit

MHz
ns

J., to Comb. Output

tCOI

Typ

5AC312-30

+20

ns
ns

+20,

+20

tCHI

IlE/IClK High Time

12.5

tCLI

IlE/IClK low Time

12.5

NOTE:
12. tpLi = Input signal through registers/latch to macrocell register input.

3-13

5AC312

ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS
= O°C to + 70°C, VCC = 5.0V ±5%, Turbo Bit On(8)

Symbol'

5AC312-25

Parameter

Min

Typ

Max

Min

Typ

Max

Non-(10)

5AC312-35

5AC312-30

Min

Typ

Max

Turbo
Mode

Unit

INPUT STRUCTURE
fAMAXI

Max. Frequency Input Register

MHz

1I (tACLI + tACHI)
tASUI

Input Register/latchSetup
Time to Asynch. IlE/IClK

tAHI

Input Register/latch Hold
after Asynch. IlE/IClK

tACOI

Asynch. IClK to Comb. Output

.40

+20

tAEOI'

Asynch. ICE t to Comb. Output

tACHI

Asynch. IClK High Time

12.5

tACLI

Asynch. IClK Low Time

12.5

MACROCELLS
fA MAX

Max. Frequency (Pipelined)

MHz

1/(tACL + tACH)-No Feedback
fACNT

Max. Frequency

28.5

1/tACNi'"with Feedback
tASU1

' Input Setup Time to
Asynch. Clock

+20

tASU2

1/0 Setup Time to
Asynch. Clock

+20

tAH

Input or 1/0 Hold' after
Asynch. Clock

tACO

Asynch. ClK to Output Valid

tACNT

tACH

Asynch. ClK High Time

12.5

tACL

Asynch. ClK low Time

12.5

0
20

3-14

'30

30
40

+20

5AC312

INPUT-CLOCK-TO-MACROCELL-CLOCK A.C. CHARACTERISTICS
o·e to + 7o·e, Vcc = 5.0V ± 5%, Turbo Bit On(8)

TA =

Symbol

5AC312-25

Parameter

Min
tC1C2

Typ

5AC312-35

5AC312-30

Max

Min

Typ

Max

Min

Typ

Max

Non-(10)
Turbo

Unit

Mode

Synchronous IlE/lClK to
Synchronous Macrocell ClK

+20

Synchronous IlE/lClK to
Asynchronous Macrocell ClK

+20

Asynchronous IlE/lClK to
Synchronous Macrocell ClK

+20

Asynchronous IlE/lClK to
Asynchronous Macrocell ClK

+20

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/o

I\,
_tpD

COMBINATORIAL OUTPUT

I\,
t pxz·

HIGH IMPEDANCE

COMBINATORIAL OR
REGISTERED OUTPUT

3-STATE

I-----tpzx
HIGH IMPEDANCE
VALID OUTPUT

3-STATE

r---tACLR~
r---tASET~

VALID OUTPUT

J\.

ASYNCHRONOUSLY
SET OR RESET OUTPUT

290156-9

3-15

5AC312

SWITCHING WAVEFORMS (Continued)
SYNCHRONOUS CLOCK MODE.(MACROCELLS)

ClK

(FROM REGISTER
TO OUTPUT)

VALID OUTPUT

290156-10

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

IlE,lClK

_tCOI

DATA VALID
BEFORE ILE
(SEE NOTE)

INPUT MAY
CHANGE

INPUT MAY CHANGE

1----..,.- tEOI - - - - I
INPUT lATCH/REGISTER TO
COMBINATORIAL OUTPUT

VALID OUTPUT

NOTE: WHEN ILE GOES HIGH BEFORE DATA IS VALID, USE tpD .
INSTEAD OF t EOI•

290156-11

3-16

5AC312

SWITCHING WAVEFORMS

(Continued)

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

ASYNCH.
ILE/CLK
INPUT

INPUT MAY CHANGE

INPUT MAY
CHANGE

INPUT MAY CHANGE

INPUT LATCH/REGISTER TO
COMBINATIONAL OUTPUT

VALID OUTPUT

NOTE: WHEN ILE GOES HIGH BEFORE DATA IS VALID. USE tpD
INSTEAD OF t AEOI •

290156-13

ASYNCHRONOUS CLOCK MODE (MACROCELLS)

ASYNCH.
CLOCK

INPUT

FLOW
THROUGH
INPUT

INPUT MAY CHANGE

FLOW THROUGH INPUT
TO REGISTERED OUTPUT

VALID OUTPUT
290156-12

3-17

5AC312

SWITCHING WAVEFORMS

(Continued)

INPUT CLOCK-TO-MACROCELL CLOCK TIMING (CLOCKED PIPE LINED DATA)

IlE,lelK

INPUTS

elK

VALID

OUTPUTS

OUTPUT
290156-18

CLOCK, SETUP, HOLD, and OUTPUT VALID times are dependent on synchronous/asynchronous clocking and are
listed in the specification tables.
.

Current in Relation to Frequency
120
110
100
90
I
80
I
'< 70
$ 60 II
.9 50
J
40
30 I
20 I
10 1/

Output Drive Current in Relation to Voltage

50
20

J""'-...

5
2
1

10 15 2025 30 35 40
leNT (MHz)

Conditions: T A

DoC, Vcc

5.25V

Vo Output Voltage (v)
290156-20

Conditions: TA

3-18

= + 25°C

290156-16

intJ

5AC324
1-MICRON CHMOS EPLD

• High-Performance LSI Semi-Custom
Logic Alternative to Low-end Gate
Arrays, TTL, and 74HC SSI and MSI
Logic

• 2 Product Terms on All Macrocell
Control Signals
• Programmable Output Registers
Configurable as D, T, JK, or SR Types

• High Speed tpD (max) 35 ns, 40 MHz
Performance Pipelined, 25 MHz w/
Feedback

• Programmable Low-Power Option for
"Stand-by" Operation; 150 p.A Typical
.
Standby Current

• 24 Macrocells with Programmable I/O
Architecture; 10 Programmable Inputs;
1 Dedicated Input or Global CLK Pin; 1
Dedicated Input or Global ILE/ICLK Pin

• UV Eraseable EPROM Technology.
100% Generically Testable EPROM
Logic Control Array
•. Programmable Secur,ty Bit Allows
100% Protection of Proprietary Designs

• Programmable Inputs Configurable'as
Latches, Registers, or Flow-Through

• (Proposed) JEDEC Pinout
• Available in 40-pin DIP and 44-pin JLeaded Chip Carrier Package (Ceramic
and Plastic)

• Software-Supported Product Term
Allocation Between Adjacent
Macrocells
• Dual Feedback on All Macrocells for
Implementing Buried Registers with
Bidirectional I/O

CLK/INPl

(See Packaging Spec., Order Number .. 231369)

LlNP10

LlNPl
LlNP8
1/0.24

1/0.22

1/0.23

1/0.21

1/0.22

Vee

1/0.21

1/0.20
1/0.6

1/0.19

5AC324

1/0.7

1/0.18

1/0.8

1/0.17

Vee

GND
1/0.16

GND

1/0.9

1/0.16

1/0.10

1/0.15

1/0.15
1/0.14

....

I()

Q..

1/0.13

~...I

LlNP7

eN CD .......

a..

........

..J...J

:::-:::

...J

...,

"'1:1'

d ci

- -

.................

LlNP6
ILE/ICLK/INP2

290160-2

290160-1

Figure 1. 5AC324 Pinout Diagrams

3-19

August 1988
Order Number: 290160-001

infef

5AC324

INTRODUCTION

·ARCHITECTURE DESCRIPTION

The Intel 5AC324 CHMOS EPLD (Erasable Programmable Logic Device) is a high integration device that overcomes the primary limitations of standard PLDs. Due to a proprietary 1/0 architecture and
macro cell structure, the 5AC324 is capable of implementing high performance logic functions more effectively than previously possible. The 5AC324 can
be used as an alternative to low-end gate arrays,
multiple programmable logic devices, or LS-, HC-, or
HCT 5S1 and MSI logic devices. Input and macrocell
features for the 5AC324 are a superset of features
offered on other PLD-type products.

The architecture of the 5AC324 is based on the familiar "Sum-Of-Products" programmable AND, fixed
OR structure. This structure is. then surrounded by
powerful, programmable macrocells and inputs. The
5AC324 can implement both combinatorial and sequential logic functions through a highly flexible
macrocell and 1/0 structure. The architecture of the
device supports both combinatorial-register and register-combinatorial-register forms of logic to easily
accomodate state machine designs.

The 5AC324 uses advanced CHMOS EPROM cells
as logic control elements instead of poly-silicon fuses. This technology allows the device to operate at
levels necessary in high performance systems while
significantly reducing power consumption. Its programmable standby mode reduces power· to near
zero in applications where a slight speed loss is traded for power savings.

Figure 2 shows a global view of the 5AC324 architecture. The 5AC324 contains a total of 24 1/0 programmable macrocells, 10 programmable input
structures, and two clock inputs that can be programmed to function either as combinatorial inputs
or clock inputs for the input structures and macrocells.
Each of the ten programmable inputs can be individually configured as a latch, register or flow-through

CLK/INP1 D----------<_--~=:::::..=::::.;

LlNP1

LOGIC ARRAY
(GLOBAL BUS)

1/0.1

1/0.2
LlNP2
MACROCELLS
1 THRU 12
(RING 1)

•
•
•

LlNP3

LlNP4

1/0.12

LlNP5

LlNP6

1/0.13

LlNP7

1/0.14
MACROCELLS
13 THRU 24
(RING 2)

•
•
•

LlNP8

LlNP9

1/0.24
LlNP10

ILE/ICLK/INP2

D - - -.......- - - - - - '
290160-3

Figure 2. 5AC324 Global Architecture
3-20

l
LOGIC ARRAY

TO NEXT
MACROCElL

FROM NEXT
MACROCELL
OUTPUT
ENABLE

PRESET
"II

ifi

...CD

OUTPUT
MUX

l=;
....
Co)

(J1

s::
'fJ III

I\:)

.....

»
o

O/T
MACROCELL
REGISTER

...0

(')

Co)
I\)

....

(')

>
t;
::T

ASYNCH. CLK (CLKB)

l§J

(')

CLEAR
TO PREVIOUS
MACROCELL

Iiiiil

FROM PREVIOUS
MACROCELL·

'iii!

290160-4

~
~

5AC324

input. Input latches/registers can be synchronously
or asynchronously clocked.
Figure 3 shows the basic architecture of each of the .
24 macrocells in the 5AC324. Each macrocell contains 16 p-terms (product terms), with 8 p-terms
available for the global array and 8 p-terr'ns dedicated to the four control signals: OE, PRESET, CLEAR,
and ASYNCH. ClK. The 8 p-terms from the logic
array are organized as a user-programmable AND
array and a user-configurable OR array. The inputs
to the AND array originate from the true and complement signals from the programmable input structure,
the dedicated inputs, and the 48 feedback paths
from the 24 I/O macrocells to the global bus. This
global bus simplifies designing with the device by
eliminating the need to partition a circuit to fit into a
loc'al/ global internal bus structure.

INPUTS
Figure 4 shows a block diagram of the 5AC324 input
structure. The device contains 10 user-programmable inputs that can be individually configured to operate in one of five modes:
.
• input register (D-register), synchronously clocked
• input register
clocked

(D-register),

MACROCELLS
Each of the 24 macrocells in the device contains 8
p-terms to support logic functions and 8 p-terms for
control signals. The 8 p-terms for logic functions are
subdivided into 2 groups, each with 4 p-terms. This
grouping of p-terms supports the proprietary p-term
allocation scheme in the 5AC324. Each macro cell
also provides dual feedbacks to the logic array,·
which results in more efficient macrocell/pin usage
than possible with single feedbacks.

asynchronously

• input latch, (D-Iatch), synchronously clocked
• input latch, (D-Iatch), asynchronously clocked
• Flow-through input
Configuration is accomplished through the programming of EPROM architecture control bits via the logic compiler and programmer software. If synchronous operation is selected, the IlE/IClK pin is used
as a global latch/clock to all input latch/register

INPUTD--..O

structures. For asynchronous operation, a separate
product term in the array is used to derive the IlE/
IClK'signal for each input structure. Because the
clock signal for each programmable input can be individually selected, a mix between synchronously
and asynchronously clocked inputs is possible. Software can configure each input structure as a flow-,
through input by selecting a latch and tying the IlE
p~term to VCC. When IlE/IClK is not used as a
latch/clock, it functions as a dedicated input to the
logic array. Data is latched/clocked on the falling
edge of IlE/IClK (synchronous mode).

Each macrocell can be configured as a D, T, RS, or
JK register. The 8 p-terms for control functions are
,organized so that 2 p-terms support each of the 4
control signals: Output Enable (OE), asynchronous
I/O preset (PRESET), asynchronous I/O reset
(CLEAR), and asynchronous I/O register clock (ASYNCH. ClK). Availability of 2 p-termsper control signai is another feature that increases the efficiency of,
the device by reducing the need to use intermediate'
riiacro.cE;llls sometimes needed to implement control
functions.

t---.,.----'-..' TO LOGIC
ARRAY
I

LATCH/
REGISTER

ILE/ICLK

CLOCK/ENABLE
SELECT
P-TERM
,FROM LOGIC
: ARRAY

D--------------'

290160-5

NOTE:
Software implements a direct (flow-through) input by selecting an asynchronous latch and tying its control P-term to Vee.

Figure 4. 5AC324 Programmable Input Structure
3-22

intJ

5AC324

ClK is a global clock signal that can be used to
synchronously clock any or all macro cell registers.
When ClK is not used as a synchronous clock, it
functions as a dedicated input to the logic array.

EXAMPLE:

Figure 5 shows a p-term allocation example. In, this
example, the logic function in macrocell 4 requires
16 p-terms. In this case, software allocates 4 pterms from the previous macrocell in Ring 1 (macrocell 5) and 4 p-terms from the next macrocell (macrocell 3) to accumulate a total of 16 p-terms (8 + 4
+ 4). This implementation leaves macrocells 3 and
5 with a remainder of 4 p-terms. These remaining pterms can also be allocated away to, or supplemented with p-terms from, their adjacent macrocells in
Ring 1 (macrocells 2 and 6).

Combinatorial Configuration.
The macrocell register can be bypassed to implement combinatorial logic functions. When configured
to provide combinatorial logic, only the OE control
signal is used.

Invert Select Bit,

With this scheme, any macrocell inside the device
can support logic functions requiring between 0 and
16 p-terms. P-terms allocated away do not affect
that macrocell's output structure. The input to the
macrocell can be tied to VCC or GND, even when all
p-terms have been allocated away. Thus the register
and all control signals are still available for use if
needed.

LOGIC ARRAY

Figure 6 shows adjacent macrocells in the 5AC324.
Table 1 shows the previous and next macrocells for
each macrocell in the device, along with the corresponding allocation ring. P-term allocation is implemented automatically in the develpment software
and is transparent to the user, Users can still use
explicit pin assignment, but should assign pins in a
way that does not conflict with p-term allocation.,

Each intersecting point in the logic array contains a
programmable EPROM connection. Initially (erased
state), all connections are complete, i.e., both true
and complement states of all signals are connected
to each p-term.
Connections are opened during programming. When
both the true and complement connections exist, a
logical false results on the output of the AND gate. If
both the true and complement connections of a signal are programmed "open", then a' logic "don't
care" results for that signal. If all connections for a
p-term are programmed open, then a logical true results on the output of the AND gate.

Software support allows the control signals on macrocalls to be used to implement simple logic functions even when all the input p-terms have been allocated to adjacent macrocells.

DUAL-FEEDBACK/BURIED LOGIC
Macrocell output can be fed back to the logic array
on either one of the two feedback paths. If the pin
feedback is used (connected after the output buffer),
bidirectional 1/0 can be implemented. If the internal
feedback path is used to implement a buried register
or buried logic function, the pin feedback is still available for use as an input. The availability of dual feedbacks on the 5AC324 enhances resource efficiency
over single feedback devices.

PRODUCT TERM ALLOCATION
Product Term (p-term) allocation is defined as taking
logic resources (p-terms) from macrocells where
they are not used to support demand for, additional
p-terms in other macrocells. In the 5AC324, p-term
allocation can occur in increments of 4 p-terms between adjacent macrocells. The 5AC324 includes 2
rings of 12 macrocells each. P-term groups from one
macrocell can be allocated to the adjacent macrocell in the ring. P-term allocation between the two
rings is not supported.

AUTOMATIC STAND-BY MODE
The 5AC324 contains a programmable bit, the Turbo
Bit, that optimizes operation for speed or for power
savings. When the Turbo Bit is programmed (TURBO = ON), the device is optimized for maximum

3-23

LOGIC ARRAY

LOWER HALF
P-TERMS 1-4
MACROCELL

P-TERMS ALLOCATED TO
MACROCELL #4
(NEXT MACROCELL IN RING)

"TI

to'
e
CD

UPPER HALF
P-TERMS 5-8

!1'

.."

.!oj
CD

;!::

0'
C'l
(,)
!.
N 0'

"'"

MACROCELL
#4

Co)

::::J

".,

m
>C
III

"coCD

+
~

UPPER HALF
P-TERMS S-8

P-TERMS ALLOCATED TO
MACROCELL #4
(PREVIOUS MACROCELL IN RING)

IiiiiJ

'1iil

MACROCELL

~
~
~

290160-6

inter

5AC324

ADJACENT MACROCELLS
FOR RING 1

ADJACENT MACRO CELLS
FOR RING 2

MACROCELL
1

MACROCELL
24

MACROCELL
2

MACROCELL
23

MACROCELL
3

MACROCELL
22

MACROCELL
4

MACROCELL
21

MACROCELL
5

MACROCELL·
20

MACROCELL
6

MACROCELL
19

MACROCELL
7

MACROCELL
18

MACROCELL
8

MACROCELL
17

MACROCELL
9

MACROCELL
16

MACROCELL
10

MACROCELL
15

MACROCELL
11

MACROCELL
14

MACROCELL
12

MACROCELL
13
290160-7

Figure 6. 5AC324 Adjacent Macrocell
Table 1. Product Term Allocation Rings
RING2

RING 1
Current
Macrocell

Next
Macrocell

Previous
Macrocell

Current
Macrocell

Next
Macrocell

Previous
Macrocell

1
2
3
4
5
6
7
8
9
10
11
12

7
1
2
3
4
5
8
9
10
11
12
6

2
3
4
5
6
12
1
7
8
9
10
11

13
14
15
16
17
18
19
20
21
22
23
24

19
13
14
15
16
17
20
21
22
23
24
18

14
15
16
17
18
24
13
19
20
21
22
23

3-25

intJ

5AC324

speed. When the Turbo Bit is not programmed
(TURBO = OFF), the device is optimized for power
savings by entering standby mode during periods of
inactivity.

POWER-ON CHARACTERISTICS
On Vee power-up, the 5AC324 registers are reset to
a logic low. Input latch/register output (to the logic
array) are also set to a logic low. 5AC324 inputs and
outputs begin responding approximately 20 p.S after
Vee power-up or after a power-Ioss/power-up sequence. After power-up, macrocells can be preset to
a logic high via the PRESET control signal for each
macrocell.
'

Figure 7 shows the device entering standby mode
approximately 100 ns after the last input transition.
When the next input transition is detected, the device returns to active mode. Wakeup time adds an
additional 15 ns to the propagation delay through
the device as measured from the first input. No delay will occur if an output is dependent on more than
one input and the last of the inputs changes after the
device has returned to active mode.

ERASED STATE CONFIGURATION
After erasure ,and prior to programming, all macrocells are configured as combinatorial outputs with
output buffers three-stated. Inputs are configured as
'
synchronous registers.

After erasure, the Turbo Bit is unprogrammed (OFF);
automatic standby mode is enabled. When the Turbo Bit is programmed (ON), the device never enters
standby mode.

FIRST
INPUT

LAST
INPUT

)K'I'.....,_________

~\'.J

r-----~--------------------~!~~

OUTPUT

CURRENT
OmA

VALID OUTPUT

ACTIVE MODE

Icc

------~--------------~~~~~~~--------~----290160-8

Figure 7. 5AC324 Standby and Active Mode Transitions

3-26

5AC324

ERASURE CHARACTERISTICS
Erasure time for the SAC324 is 1 hour at 12,000
mW/cm 2 with a 2S37A UV lamp.

Erasure characteristics of the device are such. that
erasure'begins to occur upon exposure to light with
wavelengths shorter than approximately 4000A. It
should be noted that sunlight and certain types !?f
flourescent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
room level flourescent lighting could erase the typical SAC324 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device ,window to prevent unintentional erasure ..
The recommended erasure procedure . for the
SAC324 is exposure' to shortwave ultraviolet .light
with a wavelength of2S37 A. The integrated dose
(i.e., UV intensity x exposure time) for erasure
should be a minimum of fifteen (1S) Wsecl cm 2. The
erasure time with this dosage is approximately 1
hour using an ultraviolet lamp with a 12,000 mWI
cm 2 power rating. The device should be placed withe
in 1, inch of the lamp tubes during exposure. The
maximum integrated dose the SAC324 can be exposed to without damage is 72S8 Wsec/cm 2 (1
week at 12,000 /l-W/cm 2 ). Exposure to high intensity
UV light for longer periods may cause permanent
damage to the device.

attempts to read the device architecture information
are prevented. This method provides a higher degree of design security than fused-based devices,
since programmed EPROM cells are invisible even
to microscopic examination. The Security Bit (also
called the Verify Protect Bit), along with all the other
EPROM cells, is reset by erasing the device.

LATCH-UP IMMUNITY
All of the input, 1/0, and clock pins of the device
have been designed ,to resist latch-up which is inherent in inferior CMOS structures. The SAC324 is designed with Intel's proprietary 1-micron CHMOS
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -O.SV to Vee + O.SV. The
programming pin is designed to resist latch-up to the
13.5V maximum device limit.

DESIGN RECOMMENDATIONS
For proper operation, it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or VOUT) < Vee. All unused inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capacitor of at
least 0.2JLF must be connected directly between
each Vee and GND pin.
As with all CMOS devices, ESD handling procedures
should be used with the SAC324 to prevent damage
to the device during programming, assembly, and
test.

inteligent ProgrammingTM Algorithm
FUNCTIONAL TESTING

The SAC324 supports the inteligent Programming Algorithm, which rapidly programs Intel EPLDs, and
many of Intel's microcontroliers and EPROMs while
maintaining a high degree of reliability. It is particularly suited for production programming environments. This method decreases the overall programming time while programming reliability is ensured as
the incremental programming margin of each bit has
been verified during programming. Programming
voltage and waveform specifications are available
by request from Intel to support programming the
device.

Since the logical operation of the SAC324 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application independent test
patterns. EPROM cells in the device are 100% tested for programming and erasure. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.

DESIGN SECURITY

The testability and reliability of EPROM-based programmable logiC devices is an important feature
over similar devices based on fuse technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure

A Security Bit provides a programmable security option to protect the data programmed in the device.
Once this bit is set during programming, subsequent

inter

5AC324

device functionality. During the manufacturing' process, tests on fuse-based parts can only be performed in very restricted ways in order to avoid preprogramming the array.

will compile SAC324 designs, and product a Logic
Equation File (LEF) and a Report File. No JEDEC file
is produc~d.
Full iPLS II support (including JEDEC generation capability) is provided by Version 2.0 of iPLS II, which
will be available during the second half of 1988. iPLS
II includes the LOC (Logic Optimizing Compiler), and
LPS (Logic Programming Software).

DESIGN SOFTWARE
Contact your local Intel sales office for evaluation
software to get you started, withSAC324 designs.
The evaluation software isa proprietary version of
iPLSIl (Intel Programmable Logic Software II) that

ORDERING INFORMATION
tpo
(ns)
. 3S

teo
(ns)

. fMAX
(MHz)

Order Code

NSAC324-3S

PLCC

PSAC324-3S

PDIP

CJSAC324-35

J LEAD CHIP CARRIER

DSAC324-3S,

CERDIP

N5AC324c40 '.

PLCC

33,

Package

PSAC324-40

PDIP

CJ5AC324-40

J LEAD CHIP CARRIER

DSAC324-40

CERDIP.

3-28

Operating Range
Commercial

Commercial

inter

5AC324

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vec)(I) ..... ~ .... -2.0V to +7.0V
Programming Supply
Voltage (Vpp)(I) .............. - 2.0V to + 13.5V
D.C. Input Voltage (VI)(1,2) .... -0.5V to Vee + 0.5V
Storage Temperature (T stg) ..... - 65°C to + 150°C
Ambient Temperature (T am b)(3) ...... -10o e to +8s'e

NOTICE Specifications contained wIthin the
fol/owing tables are subject to change.

NOTES:
1. Voltage with respect to GND.
2. Minimum D.C. input is -0.5V. During transitions,
. the inputs may undershoot to - 2.0V for periods of
less than 20 ns under no load conditions.
3. Under bias. Extended Temperature versions are
also available.
.

RECOMMENDED OPERATING CONDITIONS
Symbol

Vee
VIN
Vo
TA
tR
tF

Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise Time
Input Fall Time

D.C. CHARACTERISTICS

(TA

Symbol

Parameter

VIH(4)

High Level Input Voltage

. VIL(4)

Low Level Input Voltage

Min
4.75
0
0
0

Max
5.25

Vee
Vee
+70
500
500

= O°Cto

Unit
V
V
V
°C
ns
ns

+ 70°C, vee

5.0V ±5%)

Max

Unit

2.0

Vee +0.3

-0.3

0.8

Min

Typ

Test Conditions

10 = -4.0 mA D.C.,
Vee = min.

0.45

10 = 4.0 mA D.C.,
Vee = min.

Input Leakage Current

±10

p,A

Vee = max.,
GND < VIN < Vee

loz

Output Leakage Current

±10

p,A

Vee = max.,
GND < VOUT

Isd6)

Output Short Circuit Current

-90

Vee

IS8(7)

Standby Current

lee

Power Supply Current

VOH(S)

High Level Output Voltage

VOL

Low Level Output Voltage

2.4

-30
150

p,A

< Vee
= max., VOUT = 0.5V
Vee = max., VIN = Vee or
GND, Standby Mode
Vee = max., VIN = Vee or
GND, No Load, fiN = 1 MHz,
Active Mode (Turbo Off),
Device Prog. as Two
12-Bit Counters

NOTES:
4.
S.
. 6.
7.

Absolute values with respect to device GND; ali over and undershoots due to system or tester noise are included.
10 at eMOS levels (3.84V) = -2 mAo
.
Not more than 1 output should be tested at a time. Duration of that test should not exceed 1 second.
With Turbo Bit Off, device automatically enters standby mode approximately 100 ns after last input transition.

3-29

5AC324

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT
...----5V

INPUT

DEVICE
OUTPUT

3.°=X20 >

•

TEST POINTS

.0.8

< ~20.
.

0.8

TO TEST

O-+-.--C> SYSTEM

OUTPUT

341.n

(INCLUDES JIG
CAPACITANCE)

1~-----'TEST POINTS -~

290160-10
A.C. Testing: Inputs are driven at 3.0V for a Logic '"I'" and OV for
a Logic "'0". Timing Measurements are made at 2.0V for a Logic
"'I" and O.BV for. a Logic '"0" on inputs. Outputs are measured at
a 1.5V pOint. Device input rise and fall times are less than 6 ns.

290160-9

CAPACITANCE
Symbol

Parameter

CIN

Input Capacitance

COUT

Output Capacitance

Min

Typ

Max

Unit

VIN = OV, f = 1.0 MHz

VOUT = OV, f = 1.0 MHz

CCLK

Clock Pin Capacitance

VOUT = OV, f = 1.0 MHz

CvPp

Vpp Pin Capacitance

Vpp on UN3

3-30

Conditions

infef

5AC324

COMBINATORIAL MODE A.C. CHARACTERISTICS
(TA = O'C to + 70'C, Vcc = 5.0V ± 5%, Turbo Bit On)(8)
Symbol

5AC324-35

Parameter

Min

Typ

Max

5AC324-40
Min

Typ

Max

Non-Turbo(9)
Mode

Unit

tpD

Input or 1/0 to Output

. +15

tpZX(10)

Input or 1/0 to Output Enable

+15

tpXZ(10)

Input or 1/0 to Output Disable

+15

tClR

Asynch. Reset to Q Clear

+15

tSET

Asynch. Set to Q Set

+15

NOTES:

8. Typical·values are at TA = + 25'C, Vcc = 5V, Active Mode.
9. If device is operated with Turbo bit Off (Non-Turbo Mode), increase time by amount shown.
10. tpzx and tpxz measured at ±O.5V from steady-state voltage as driven by spec. output load. tpxz measured with CL = 5
pF.

SYNCHRONOUS CLOCK MODE (MACROCELLS) A.C. CHARACTERISTICS
(TA = (j'C to +70'C, VCC = 5.0V ±5%, Turbo Bit On)(8)
5AC324-35

Symbol Parameter

Min

Typ

5AC324-40

Max Min Typ Max

Non-Turbo(9)
Mode

Unit

fMAX

Maximum Frequency (1 Itsu)
No Feedback

33.3

(11)

MHz

fCNT

Maximum Frequency (1 ItCNT)
With Feedback

28.5

22.2

(11)

MHz

tSU1

Input Setup Time to ClK

tSU2

1/0 Setup Time to ClK

i
i

+15

Input or 1/0 Hold Time from ClK

tco

ClK

tCNT

tCH

Clock High Time

12.5

tCl

Clock low Time

tcw

Minimum Clock Width

ns
ns

+15

12.5

+15

to Output Valid

15
40

NOTE:

11. Recalculate frequency according to expression at left of table.

3-31

20
45

5AC324

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) A.C. CHARACTERISTICS
(TA

O°C to + 70°C, VCC

• Symbol

5.0V ± 5%, Turbo Bit On)(8)
5AC324-35

Parameter

Min.

5AC324-40

Typ

Max

Min

Typ

Max

33.3

Non-Turbo(9)
Mode

Unit

(11 )

MHz

fMAXI

Maximum Frequency (1 ItcWI)

tsulR

Input Register Setup Time
Before ICLK ..L-

tESUI

Input Latch Setup Time
Before ILE t

tCOI .

ICLK

tHI

Input Hold after ICLK/ILE ..L-

tEal

ILE

tCHI

ILE/ICLK High Time

12.5

tCLI

ILE/ICLK Low Time

tCWI

Minimum Input Clock Width

to Comb. Output

+15

5
40

ns
ns

+15

12.5

+15

ASYNCHRONOUS. CLOCK MODE (MACROCELLS) ~.C. CHARACTERISTICS
(TA = O°C to + 70°C, VCC = 5.0V ± 5%, Turbo Bit On)(8)
Symbol Parameter

5AC324·35

5AC324-40

Min Typ Max Min
fAMAX

Max. Frequency (1/tAcL + tACH)
No Feedback

fACNT

Max. Frequency (1 ItACNT)
With Feedback

tASU1

Input Setup Time to Asynch. CLK

16.6

16.5 14.2

(11 )

MHz

15.3 14.2

14.2 13.3

+15

MHz

+15

12.5

tASU2

liD Setup Time to Asynch. CLK

tAH

Input or liD Hold Time from Asynch. CLK

tACO

Asynch. CLK to Output Valid

tACNT

Asynch. Output Feedback to Register.
Input - Internal Path

'tACH

Asynch. CLK High Time

tACL

Asynch. CLK Low Time

tACW

Asynch. CLK Width

Typ Max

Non-Turbo(9)
Unit
Mode

12.5
25
45

+15

ris

+15

3-32

5AC324

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) A.C. CHARACTERISTICS
(TA = O°C to + 70°C, VCC
Symbol

5.0V ±5%, Turbo Bit On)(8)
5AC324·40

5AC324·35

Parameter

Min

Typ

Max

22.2

Min

Typ

Max

Non-Turbo(9)
Mode

Unit·

(11 )

MHz

fAMAXI

Maximum Frequency Input Register
(1/tACWI)

tASUIR

Input Register Setup Time
Before Asynch. IClK

tAESUI

Input latch Setup Time
Before Asynch. IlE

tACOI

Asynch. IClK to Comb. Output

+15

tAHI

Input Hold after Asynch. IClK/llE

tAEOI

Asynch. IlE toComb. Output

tACHI

Asynch. IlE/IClK High Time

22.5

+15

tACLI

Asynch. IlEIIClK low Time

22.5

+15

tACWI

Minimum Input Clock Width

+15

INPUT-CLOCK-TO-MACROCELL-CLOCK A.C. CHARACTERISTICS
(TA

O°C to + 70°C, VCC

Symbol

5.0V ± 5%, Turbo Bit On)(8)

Min
tC1C2(12)

5AC324-40

5AC324-35

Parameter

Typ

Max

Min

Typ

Max

Non-Turbo(9)
Mode

Unit

Synchronous IlE/IClK
Synchronous Macrocell ClK

+15

Synchronous IlE/IClK
Asynchronous Macrocell ClK

+15

Asynchronous IlE/IClK
Synchronous Macrocell ClK

+15

Asynchronous IlE/ClK
Asynchronous Macrocell ClK

+15

NOTE:
12. Times for SETUP, HOLD, and OUTPUT VALID are shown in previous tables.

3-33

inter

5AC324

SWITCHING WAVEFORMS
COMBINATORIAL MODE

INPUT OR I/O

'V
j\.

_lpD

COMBINATORIAL OUTPUT

IpXZ
HIGH IMPEDANCE

COMBINATORIAL OR
REGISTERED OUTPUT

3-STATE

I-----lpZX
HIGH IMPEDANCE
VALID OUTPUT

3-STATE
I--IACLRI--IASET-

ASYNCHRONOUSLY
SET OR RESET OUTPUT

VALID OUTPUT

290160-11

3-34

5AC324

SYNCHRONOUS CLOCK MODE (MACROCELLS)

I----tcw----J

CLK

INPUT

INPUT MAY CHANGE

(FROM REGISTER CLOCK
TO OUTPUT)

OUTPUT

VALID OUTPUT
290160-12

SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

ILE,ICLK

INPUT

INPUT MAY
CHANGE

INPUT MAY CHANGE

_tCOI

1----

tEOI - - - - I

INPUT LATCH/REGISTER TO
COMBINATORIAL OUTPUT

VALID OUTPUT
290160-13

NOTE:
When ILE goes high before data is valid, use tpD instead of tEOI-

3-35

inter

5AC324

ASYNCHRONOUS CLOCK MODE (MACROCELLS)

ASYNCH.
CLOCK
INPUT

FLOW
THROUGH
INPUT

INPUT MAY CHANGE

FLOW THROUGH INPUT
TO REGISTERED OUTPUT

VALID OUTPUT

290160-14

ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)

ASYNCH.
ILE/CLK
INPUT

INPUT MAY CHANGE

1---:--tAEOI - - - - - I
INPUT LATCH/REGISTER TO
COMBINATIONAL OUTPUT

VALID OUTPUT

290160-15

NOTE:
When ILE goes high before data is valid, use tpD instead of tAEOf'

3-36

.5AC324

INPUT-CLOCK-TO-MACROCELL CLOCK TIMING (CLOCKED PIPELINED DATA)

IlE,lClK

INPUTS
t C1C2

ClK

OUTPUTS

VALID
OUTPUTS
290160-16

CLOCK, SETUP, HOLD, and OUTPUT VALID times are dependent on synchronous/asynchronousc!ocking and are
listed in the specification tables.

3-37

85C508
FAST1~MICRON

CHMOS
DECODER/LATCH EPLD

•
•
•

High Performance Programmable logic
Device for High-Speed Microprocessorto-Memory Decode

16 Dedicated .Inputs for Address/Data
• .Bus
Decoding; 8 latched Outputs; 1

Upgrade Alternative to Fast Bipolar
PlAs and Fast MSI logic

•

Global latch Enable
100%

Generi~a"y

Testable logic Array·

II Available in 28-pin 300-mil CERDIP and
PDIP Packages and in PlCC Package

Extremely High Speed-tPD 7.5 ns
. (max), 133.3 MHz (max), tEO 5 ns (max)

(See Packaging Spec., Order Number # 231369)

F100111
F100112
vpp

Vee

INPl

INP16

INP2

INP15

> 3::

on
..-

a..
~

01
02
INP5

03
04
INP7

INP8

INP9

INP6

85C508

04
05

INP9

07
08

INP11
INP12
GND

INP14
N

INP13

0: 0:
~

ALE

'"0: ....0:
~

00
0

290175-2
290175-1

Figure 1. 85C508 Pinout Diagrams

3·38

October 1988
Order Number: 290175·001

infef

85C508

INTRODUCTION

ERASURE CHARACTERISTICS

The Intel 8SCS08 1-micron CHMOS EPLD (Erasable
Programmable Logic Device) is designed to support
the speeds required in fast microprocessor to memory paths. The sixteen inputs, p-term array, and eight
output latches in the 8SCS08 provide address and
data bus decoding and latching. The 8SCS08 takes
full advantage of the lightning speed of Intel's 1-micron CHMOS technology. The 8SCS08 can be used
as an upgrade to fast bipolar PLDs, and to fast AL,
ALS, HC, or HCT SSI and MSI logic devices.

Erasure time for the 8SCS08 is 1 hour at 12,000
p..Wsec/cm2 with a 2S37A UV lamp.
Erasure characteristics of the device are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 400A. It
should be noted that sunlight and certain types.of
flourescent lamps have wavelengths in the 3000A4000A range. Data shows that constant exposure to
room level flourescent lighting could erase the typical 8SCS08 in approximately six years, while it would
take approximately two weeks to erase the device
when exposed to direct sunlight. If the device is to
be exposed to these lighting conditions for extended
periods of time, conductive opaque labels should be
placed over the device window to prevent unintentional erasure.

The 8SCS08 uses advanced EPROM·celis as architecture and logic array storage elements instead of
poly-silicon fuses. Coupled with Intel's proprietary
CHMOS technology, the result is a device that offers
a fast 7.S ns tpo in flow-through mode and. a tEO of
S ns in latch mode. The inherent speed of the device
makes the 8SCS08 ideally suited for bus decoding
applications with Intel's 80386 microprocessor and
80960 embedded controller families.

The recommended erasure procedure for the.
8SCS08 is exposure to shortwave ultraviolet light
with a wavelength of 2S37A. The integrated dose
(i.e., UV intensity x exposure time) for erasure
should be a minimum of fifteen (1S) Wsec/cm 2. The
erasure time with this dosage is approximately 1
hour using an ultraviolet lamp with a 12,000
p..W/cm2 power rating. The device should be placed
within 1 inch of the lamp tubes during exposure. The
maximum integrated dose the 8SCS08 can be exposed to without damage is 72S8 Wsec/cm 2 (1
week at 12,000 p..W / cm2). Exposure to high intensity
UV light for longer periods may cause permanent
damage to the device.

ARCHITECTURE DESCRIPTION
The architecture of the 8SCS08 is designed for highspeed performance, with dedicated inputs feeding a
logic array. Outputs from the logic array feed the fast
output latches. All output latches are controlled by
the global ALE (Address Latch Enable) signal. Figure 2 shows the global architecture of the 8SCS08.
The input to each latch is a single NAND p-term that
can be connected to the true or complement state of
the dedicated inputs. All input signals are available
to all eight macrocells.

LATCH-UP IMMUNITY

Each intersecting point in the logic array is connected or not connected based on the value programmed in the EPROM array. Initially (EPROM
erased state), no connections exist between any pterm and any input. Connections can be made by
programming the appropriate EPROM cells. True
and complement connections cannot exist at the
same time. Since p-terms are implemented as
NANDs, a true condition on a p-term drives the output low.

All of the input, output, and clock pins of the device
have been designed to resist latch-Up which is inherent in inferior CMOS structures. The 8SCS08 is designed with Intel's proprietary 1-micron CHMOS
EPROM process. Thus, each of the pins will not experience latch-up with currents up to 100 rnA and
voltages ranging from -O.SV to Vee + O.SV. The
programming pin is designed to resist latch-up to the
13.SV maximum device limit.

POWER-ON CHARACTERISTICS

DESIGN RECOMMENDATIONS

On Vee power-up~ the 8SCS08 latches respond to .
the values on the input signals. No logic high/low
state is guaranteed at power up. 8SCS08 inputs and
outputs begin responding approximately S p..s after
Vee power-up or after a power-Ioss/power-up sequence'.

For proper operation; it is recommended that all input and output pins be constrained to the voltage
range GND < (VIN or VOUT) < Vee. All unused inputs should be tied to an appropriate logic level to
minimize power consumption (do not leave them
floating). A power supply decoupling capacitor of at
least 0.2 p..F must be connected directly' between
each Vee and GND pin.

3-39

85C508

>--Cl01

INP1

0--1~t:=:t-!
>-<:]02

INP2 •

...i_ _~~_"'-I-+--I-'"

>--Cl03
INP3 L..,;I--,t,..2~--4+-I-..j....:~

>--<:104

>--Cl05

•
•
•

>--<:]06

>--<::107
INP16

D---1~~_--1-+--I--I--++-_-f.'"
>--<:]08

ALE

D_--'---------------'--.....J
Figure 2, 85C508 Global Architecture

3-40

290175-3

inter

85C508

As with all CMOS. devices, ESD handling procedures
should be used with the S5C50S to prevent damage
to the device during programming, assembly, and
test.

The testability and reliability of EPROM-based programmable logic devices is an important feature
over similar devices based on fuse technology,
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
device functionality. During the manufacturing process, tests on fuse-based parts can only be performed in very restricted ways in order to avoid preprogramming the array.

FUNCTIONAL TESTING
Since the logical operation of the S5C50S is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each
programmable EPROM bit controlling the internal
logic is tested using application independent test
patterns. EPROM cells in the device are 100% tested for programming and erasure. After testing, the
devices are erased before shipments to the customers. No post-programming tests of the EPROM array
are required.

DESIGN SOFTWARE
Full software support is provided by version 2.0 of
iPLS II (Intel Programmable Logic Software II). That
version includes the LOC (Logic Optimizing Compiler), LPS (Logic Programming Software), and Macro
Librarian.
For detailed information on iPLS II, refer to the
iPLDS II Data Sheet, order number: 290134.

ORDERING INFORMATION
tpD

tEO

(n5)

f max
(MHz)

Order Code

*7.5

133.3

100

Package

Operating Range

NS5C50S-7

PLCC

Commercial

DS5C50S-7

CERDIP

PS5C50S-7

PDIP

NS5C50S-10

PLCC

DS5C50S-10

CERDIP

PS5C50S-10

PDIP

Commercial

66.5

NS5C50S-15

PLCC

DS5C50S-15

CERDIP

PS5C50S-15

PDIP

'NOTE:
Under development.

3-41

Commercial

intJ

85C508

ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (Vec)(l) .......... - 2.0V to

+- 7.0V

Programming Supply
Voltage (Vpp)(ll. ............. -2.0V to+ 13.5V
D.C. Input Voltage (VI)(l, 2) ... - 0.5V to Vee + 0.5V
Storage Temperature (T stg) ...... - 65°C to + 150°C
AmbientTemperature (Tamb)(3) ... -10°C to + 85°C

NOTES:
1. Voltages with respect to GND.
2. Minimum D.C. input is -0.5V. During transitions,
the inputs may undershoot to - 2.0V or overshoot '
to 7.0V for periods of less than 20 ns under no load
conditions.
3. Under bias. Extended Temperature versions are
also available.

NOTICE: Specifications contained within the
fol/owing tables are subject to change.

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee

Parameter
Supply Voltage

Min

Max

Units

4.75

5.25

V
V

VIN

Input Voltage

Vee

Output Voltage

Vee

+70

°C

Operating Temperature

Input Rise Time

500

Input Fall Time

500

D.C. CHARACTERISTICS
Symbol

(TA

O°Cto + 70°C, Vee

Parameter

5.0V ±5%)

Conditions

Min

Typ

Max

Units

VIH(4)

High Level Input Voltage

2.0

Vee + 0.3

VIL(4)

Low Level Input Voltage

-0.3

0.8

VOH

High Level Output Voltage

= -4.0 mA D.C., Vee = min

VOL

Low Level Output Voltage

= 4.0 mA D.C., Vee = min

0.45

II
loz
IsC<5)
lee

< VIN < Vee
< VOUT < Vee
max., VOUT = 0.5V
max., VIN = Vee or GND,
No Load, fiN = 50 MHz, Device

=
=
Output Short Circuit Current Vee =
Power Supply Current
Vee =

2.4

Input Leakage Current

Vee

max., GND

±10

p.A

Output Leakage Current

Vee

max., GND

±10

p.A

-90

-30

mA
30

Prog. as 16-8it Address Decoder
NOTES:

3-42

intJ

85C508

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

.-----SV

3'°-:A 20
o
0.8

INPUT

DEVICE
OUTPUT

c::--t--......--C> SYSTEM
TO TEST

0.8

1~~TEST POINTS-~

OUTPUT

(INCLUDES JIG
CAPACITANCE)

341.11

290175-S

A.G. Testing: Inputs are driven at 3.0V for a Logic "1" and OV for
a Logic "0". Timing Measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0" on inputs. Outputs are measured at
a I.SV point. Oevice input rise and fall times are less than 3 ns.

29017S-4

CAPACITANCE TA
Symbol

< X;.

TEST POINTS

O·Cto +70·C;Vcc = 5.0V ± 5%

Parameter

Conditions

Min

CClK

ALE Capacitance

= OV, f = 1.0 MHz
= OV, f = 1.0 MHz
VOUT = OV, f = 1.0 MHz

CvPp

Vpp Pin Capacitance

Vppon Pin 1

Typ

Max

Units

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

A.C. CHARACTERISTICS T A = O·C to + 70·C, Vcc = 5.0V ± 5%
Symbol

*S5C50S·7

Parameter
Min

Typ

S5C50S·15

S5C50S·10

Max

Min

Typ

Max

Min

Typ

Max

Units

tpD

Propagation Delay
(Flow-Through Mode)

7.5

f max

Maximum Frequency
(1/tcw)

133.3

112

100

82.5

MHz

tEO

Output Valid from ALE

tsu

Input Setup Time to ALE

Input Hold from ALE

J..

ns
ns

-3

7.5

tCH

ALE High Time

tCl

ALE Low Time

7.5

tcw

ALE Clock Width

"NOTE:
Under development.

3-43

inter

85C508

FLOW-THROUGH MODE
H--~~~~~~~~~~~~

ALE L

LATCHES ARE IN fLOW-THROUGH MODE
WHEN ALE IS HELD HIGH

.INPUT

OUTPUT
290175-6

LATCH MODE

ALE

---"1

OUTPUT __________JI~~~_',~__________~r~__
290175-7

3·44

SCBIC
PROGRAMMABLE BUS
INTERFACE CONTROLLER
- On-Chip Controls for the Bus
Management Unit
- Up to Eight Buried Registers
- Programmable Registers can be
Configured as Positive EdgeTriggered 0-, J-K, R-S or T- Types
..;... Asynchronous Preset and Clear on
All Registers
- Option of Latched Inputs

• Higher Integration Alternative to
Transceivers, Latches, Multiplexers and
PAL * Functions
• Applications Include Dual Port Control,
Multiplexed Bus Interface, DRAM
Control and Similar Functions
• Port-Oriented Bus Management Unit
Supports:
- 3-Way Asynchronous Data Transfer
on Byte-Wide Buses
- Programmable Option of Latched or
Real Time Data
- True or Complement Data Path

• Low Power: 75 p,A Typical Stand~y
• CHMOS EPROM Technology Based:
- Max Bus Port Drive Capability: 16 rnA
- Typical Data Transfer Delay Between
Ports = 45 ns

• Macrocell-Based Programmable Logic
Unit Provides:
I .
- Variable Input and Output
Architecture .

• Available in 44-Lead Package
(See Packaging Spec., Order;; 231369)

The Intel 5CBIC is useful in implementing bus interfacing logic functions that have traditionally been done
using SSI/MSI TTL components. Core bus functions are provided that can be customized using EPROM bits
for specific applications. Control logic can also be implemented through a sum of products architecture that is
included in this 44-lead package. Such levels of integration are realized utilizing the benefits of Intel's advanced CHMOSII-E process.
This general purpose architecture is supported by iPLDS II, Intel's Programmable Logic Development System, '
to develop the design and program the devices. Several methods of entry facilitate ttie design resulting in
shorter completion times.
'
~PAL

is a trademark of Monolithic Memories, Inc.

PORT A ~

\.r--v"

BUS MANAGEMENT
UNIT

A6
AS

104

Vee
IN3

INPUTS

c::::::>

LOGIC

~INPUTS/

\.r--v" OUTPUTS

44 PAD
0.650" x 0.650"

Vee

TOP VIEW

103

102

IN2

IN1

290126-1

Figure 1. Block Diagram
290126-2

Figure 2. Lead Configuration

3-45

Augusl1988
Order Number: 290126-004

inter

5CBIC

FUNCTIONAL DESCRIPTION
As the name suggests, this programmable bus interface controller offers a high integration solution to
design problems involving data transfer on bus lines
and the logic needed to control these transfers. This
integration directly translates into savings in board
space and lower system cost for, equivalent functions implemented using conventional SSIIMSI
components.
Present in the port-oriented 5CBIC are two functional blocks that enable complex bus functions to be
realized: the Bus Management Unit (BMU) and the
Programmable Logic Unit (PLU). These two units
communicate with each other through the input and
the feedback buses. A control section shown in Figure 3 steers signals from the PLU to the two units
through the control bus.

trolis illustrated in Figure 5. The Bus Management
Unit (BMU) and the Programmable Logic Unit (PLU)
interface to the feedback and the control busses.
The macrocells in the PLU feed the, input bus.

Bus Management Unit (BMU)
The Bus Management Unit (BMU) comprises three
ports: PA, PB and PC (Figure4a). Each of these
ports is bidirectional and 8 bits wide. Data can be
routed from any port to any other port.
Data into any port can be user-selected to be
latched by a port Latch Enable signal, (LE). Routing
of latched or unlatched data between ports is
achieved using a combination of EPROM architecture and dynamic control signals defined by the user.
Data out of any port can be programmed to have an
inverted sense through EPROM architecture control
(INV).

ARCHITECTURE DESCRIPTION
The innovative architecture of the 5CBIC incorporating a port-oriented approach for bus intel\face con-

Each bidirectional port can be dynamically configured as an input or an output depending on the control signals OEA, DEB and DEC. Latched data from

12
1

, 1+----+ PORTC

PORT A

H
I

INPUT
PORT

PORT
C6NTROL

.j,
FEEDBACK

OUTPUT
PORT

BUS MANAGEMENT
UNIT

/~ ~ PORTB

ll-

T
CONTROL

1 J
0001

0
0

11
0

•

PROGRAMMABLE LOGIC UNIT

L.L

1/07

1/01
INO

---+
INPUT
MACROCELL

~
AR,RAY

1/00
INPUT/OUTPUT
LOGIC
MACROCELL

r--:0

290126-3
In the tridirectional BMU. any port can be steered to any other port. In this diagram. Port A can be directed to Port B or Port C or both. The PLU
provides a 600'gate equivalent PAL function.

Figure 3. Functional Blocks in the 5CBIC

infef

5CBIC

FROM PORT C

H-C>-tHr-t--r----

PORT B
(OUTPUT PORT)

TFB2

FROM
CONTROL
BUS

TO
FEEDBACK
BUS

SELC
SELA
SELB

OEA

Each bidirectional port can be dynamically configured as an input or an output depending on the control signals DEA. DEB and DEC. The feedback to the array is controlled
by TFB1. TFB2 and port routing occurs through SELA. SELB and SELC. In the diagram. Port A is the input port with possible outputs at Port B and Port C.
290126-5

Figure 4a; Bus Management Unit Block Diagram

PORT A

PORT B

290126-23

TO fEEDBACK BUS

LEGEND:
OEA. OEB. OEC. SELA. SELB. SELC. LEA. LEB. LEC. TFB1 and TFB2 are the control outputs for the BMU derived from
the control bus.
MPCA. MPCB and MPCC are dynamic multiplexers controlled by SELA. SELB and SELC for port selection.
MUXA. MUXB. INVA. INVB and INVC are static multiplexers controlled by architecture bits (EPROM bits).
All latches are the "transparent" type.
'

Figure 4b_ BMU Logic Diagram

any incoming port can be fed internally to the array
through TFB1 and TFB2. The three ports can be
time-multiplexed, if needed. Port routing is controlled
by signals SELA, SELB and SELC (Figure 4b).

Programmable Logic Unit (PLU)
An on-Chip 600-gate-equivalent EPLD supplies the
control signals to the bus unit and related applica3-47

SCBIC

BO' 91 92 83 94 85 86 B7

BMU

CONTROL

BUS

lOGIC
(PDRr B)

SELB
LEB
DEB

SElA

LEA
DEA

Al
A2
BUS

LOGIC
(PORT 'A)

A4
A5
A6
A7

SElC
LEe
DEC
BUS

lOGIC
(PDRr C)

CO Cl C2 C3 C4 C5 C6 C7

290126-4
INMC = Input Macro Cell
_
IOMC . = Input/Output Macro Cell
p-term = Product Terms through the logic array

Figure S. The SCBIC Architecture

3-48

infef
100

¢~-

•
INa

5CBIC

101

102

103

104

105

106

E
R

,E
R

E
'R

E
R
M

INI

IN2

IN3

IN4

, INS

IN6

107

IN7

290126-21

3-49

inter

5CBIC

EPROM
CONTROL
BIT

PROGRAMMABLE AND ARRAY

PRODUCT
TERMS

~.~

INPUT AND FEEDBACK BUSES
290126-6

Figure 6. The Array Structure
be implemented by selecting the architecture bit
MARB1 and the edge-triggered flip-flop (Figure 7).
The Macrocells support D, T, S-R or J-K type registers for optimal design. Truth tables for these are
listed in Figure 8 for easy reference. Whereas all
eight of the product terms are OR-ed together at the
register input for the D- and the T- registers, the J-K
and the S-R configurations employ sharing of the
product teriTls among two OR-gates.

tion functions in the system. A dedicated input port
and a bidirectional I/O port, each 8 bits wide, allows
control logic implementation in the 5CBIC. The macrocell based architecture enables the designer to
use up to 24 inputs and 8 outputs.
The inputs, array and I/O marcrocells generate a
sum-of-products (AND-OR) representation of any
given logic. Within the AND array, there is an
EPROM connection at every intersection of an incoming signal (true and complement) and a product
term to a given macro cell (Figure 6). Before programming an erased device an EPROM connection
exists at every intersection. It is during the programming process that these connections are opened to
generate the required connections.

The registers receive inputs at its data, clock, set
and reset lines. Eight product terms are available for
the data input and one each for the set and the clear
inputs.
The clock, output enable and the latching signals
can be selected by architecture bits MARB2, 6 and 3
respectively to be outputs from the control bus or
one product term from the array. Designers thus
have more options available for asynchronous
clocking and output controls.

The bidirectional I/O port, when configured as an
input, is identical to the input port in that inputs may
be latched by a signal from the control bus as shown
in Figure 7. An additional flow-through option for the
data inputs is available in the input macrocell.

The macrocell output can be fed back to the array
through the feedback bus or to the control bus. Figure 9 summarizes the bus structure and its relationship to the relevant units in the 5CBIC.

The variable output architecture in the PLU allows
the designer to select the combinatorial or registered output types on a macrocell basis. This may

3-50

inter

5CBIC

IX>

LATCH
INPUT PIN

'"'"""..----,'-----

>+-"><::> I/o PIN

THESE SIGNALS ARE COMMON

TO ALL I/o MACROCELLS

290126-7

Figure 7. The Programmable Logic Unit

Input and Input/Output Logic Macrocell

IX>

LATCH
INPUT PIN

"...
IX>

>t-<~C::::>I/o PIN

.,"
Il.

THESE SIGNALS ARE COMMON

TO ALL I/O MACROCELLS

290126-8

Figure Sa. Combinational

3-51

SCBIC

Input and Input/Output Logic Macrocell

LATCH

INPUT PIN

I/O PI"

TO ALL

I/o

MACROCELlS

290126-9

Function Table
On

OnH

0
0
1
1

0
1
0
1

0
0
1
1

Figure 8b. OoType Flip-Flop

Input and Input/Output Logic Macrocell

INPUT PIN

I/O PI"

TO ALL' I/O MACROCELLS

290126-10

Function Table
T

Ontt

0
0
1
1

0
1
0
1

0
1
1
0

Figure 8c. Toggle Flip-Flop

3·52

inter

5CBIC

Input and Input/Output Logic Macrocell

INPUT PIN

I/O PIN

TO ALL I/O NACROCELlS

290126-11

Function Table
J

o
o

o
o
o
1
1
1
1

1
1

o
o
1
1

On+ 1

o
1
o
1
o
1
o

o
1

o
o
1
1
1

Figure ad. J-K Flip-Flop
Input and Input/Output Logic Macrocell

INPUT PIN

I/O PIN

TO All I/O NACROC£LLS

Function Table
S

On+ 1

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

0
1
0
0
1
1

1[legal

Figure 8e. S-R Flip-Flop
3-53

290126-12

5CBIC

INPUT FROM:

D-

FEEDBACK:

FROM~~
BMU
16

INPUT - ,
MACROCELLS
TO ARRAY

I/O
MACROCELLS -

TO ARRAY
FROM I/o
MACROCELLS

INPUT BUS

FEEDBACK BUS

TO BMU
,------,----'-''----'- CONTROLS

FROM INPUT

M~~~~C~~~::~
MACROCELL

M'-t--.I

Vcc
<--_~---,.....,..

CONTROL BUS

TO I/o
MACRO CELLS CONTROL
TO INPUT
MACROCELL CONTROL

290126-13

Figure 9. The 5CBIC Bus Organization
Table 2. BMU Primitive

Configuring the 5CBIC

The primitive necessary for configuring inter-port
communication is the "BMU", while the one required
for internal feedback from the BMU to the PLU is the
feedback primitive "BFMUX". Tables 1 through 4
define these primitives and their fields/bits.

MUXA, MUXB

PA
PB
PC

BMU
Name:

BMU (Bus Management (Unit)

ADF Syntax: PortA, PortB, PortC = BMU (Type,
OeA, SeIA, LeA, OeB, SeIB, LeB,
OeC, SeIC, LeC)

Table 1. BMU Architecture Bits
Architecture
Bit

8 bit
I/O
Ports

OeA
SelA
LeA
OeB
SelB
LeB
OeC
SelC
Lec

The Device Configuration Manager (DCM) in
iPLS II provides a high-level graphic design entry alternative that allows bus configurations to be implemented in minutes. A more detailed explanation is
given in the iPLS II manual. An ADF (Advanced Design File) is then automatically generated that defines the logic network using primitives.

Description:

Selects

Port A = connection to 8 parallel I/O
. pins labeled AO-A7
Port B = connection to 8 parallel I/O
pins labeled BO-B7

Latched or Flow-Through
Port Data

Port C ~ connection to 8 parallel I/O
pins labeled CO-C7

INVA, INVB, INVC . True or Inverted Data Output

OeA = output enable for Port A
SeIA= select B or C internal connection to Port A (0 = C,
1 = B)
LeA = input latch enable for Port A
OeB = output enable for Port B
SeIB= select A or C internal connection to Port B (0 = C,
1 = A)
LeB = input latch enable for Port B
OeC=output enable-for Port C
SeIC= .select A or B internal connection to Port C (0 = A,
1 = B)
LeC ';input latch enable for Port C

3-54

5CBIC

Input Latch

Inversion Control
Port:

Bit:

Invert Output

Latched A

Latched B

Latched C

No Invert

Direct A

Direct B

Latched C'

'If LeC

continually high, the C latch

transparent.

Table 3. Bus Feedback Multlpler Primitive

Table 4. PLU Architecture Bits

BFMX

i~~~ L. .I_~__~ __~...JI
C

Architecture
Bit
Fbk

[0:7]

MARBO
MARB1
MARB2
MARB3
MARB4

Name:
BFMX (Bus Feedback Multiplexer
ADFSyntax: Fbk[0:7] = BFMX (TFB1, TFB2)
Description:

Outputs.
MARB5
MARB6

Fbk= 8 parallel lines of feedback to
logic array.
Inputs:
TFB1, TFB2 = By appling 0 or 1 as
shown on the chart above, select
feedback from Port A;B, or C. TFB1
and TFB2 can be set to VCC or GND,
" or they can be connected to any inter·
nal feedback or input node. The ports
are defined in the BMU primitive sec·
tion.
.
.

3-55

Selects
Output Polarity
Combinatorial or Registered Outputs
Clock Source
Latching Signal Source
Combiriatorial or Registered
Feedback to the Logic Array
Input Source to the Control Bus
' tri-state Control Signal

5CBIC

ABSOLUTE MAXIMUM RATINGS*
Min

Max

Units

Vee

Supply Voltage{!)

-2.0

7.0

Vpp

Pr()gramming
Supply \(oltage{!)

-2.0

13.5

DC Input Voltage{!){2)

-0.5 Vce+ 0.5

tstg

Storage Temperature

-65

+150

tamb

Ambient Temperature(3) -10

+85

Symbol

Parameter

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
funCtional operation of the device at these or any
other conditions above those indicated in the opera-.
tional sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may all~ct device reliability.

NOTES:
1. Voltages with respect to ground.
2. Minimum De input is -0.5V. During transitions, the inputs may undershoot to -2.0V·for periods less than 20 ns
under no load conditions.
3. Under bias. Extended temperature' versions .are also
available.
.

D.C.·CHARACTERISTtCSTA
Parameter

= O·Cto +70·C, Vee = 5.0V ±5%

Description

Min

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

Max

0.45

TTL: IOH

PortA
-1mA

Port S, C
1,1/0
-5mA
-1 mA
Vee = Min

10L

PortA
5mA

Port S, C
16mA
Vee = Min

VIH

Input High Level

2.0

Vee +0.3

VIL

Input Low Level

-0.3

0.8

V
/LA

Input Leakage Current

10
10

/LA

80
16

mA
mA

loz

Output Leakage Current

IOS(4)

Output Short Circuit Current

IS8(5)

Operating Current
(standby, low power mode)

/LA

lee2

Operating Current
(active, low power mode)

Operating Current
(active, turbo mode)

108

CIN

Input Pin Capacitance

COUT

Output Pin Capacitance

lee3

SMU
PLU

Test Conditions

Unit

Vss ~ VIN

= Max
Vss ~ VOUT ~ Vee, Vee = Max
Vee = Max, VOUT = 0.5
VIN
VIN
f

< Vee,

1,1/0
5mA

=
VIN

Vee

Vee or Gnd,
10 = 0

= Vee or Gnd,
1 MHz, No Load
=

Vee or Gnd,

f = 1 MHz, No Load

NOTES:
4. Output shorted for no more than 1 sec. and only one output shorted at a time.
5. ehip automatically goes into standby mode if logic transitions do not occur at input pins. (Approximately 100 ns after last
transition).
.

3-56

5CBIC

.
.
32S/l
PORT A.I/O ~ 2 07SV
OUTPUT . ..L .. ~..
.
•
CL.I. SOpF

92/l

PORTB,C~193V

OUTPUT -

. ..L .. ~.
CL.I. SOpF

290126-14

290126-15

NOTES:
CL includes jig capacitance
Device input rise and fall times

6 ns

Figure 10. A.C. Testing.Load Circuit

INPUT

3.0~20. >TEST POINTS<
a

O.B

>GI
•
. O.B

1~~TEST POINTS---)E

OUTPUT

290126-16
A.C. Testing: Inputs are driven at 3.0V for a Logic "1" and OV for a Logic "0". Timing
measurements are m.ade at 2.0V for a Logic "1" and· 0.8V for a Logic "0" on inputs.
Outputs are measured at a 1.5V point.

Figure 11. A.C.Testing Input, Output Waveform

Switching Characteristics
Timing
Suffix

Notation:

Referenced to
Control From:
direct input pin

1
2
3

product term

control bus

PORT
INPUTS

VALID

~~USU1_ I-:UH01_
TUH03

TUSU3

LATCH
ENABLE

--'
I----TLEH

OUTPUT
ENABLE
~

TSUSPD

TpXZ:~

TpXZ3

I---

TplXl
TpZX3

PORT
. OUTPUTS
r---TLEPDl ~
TLEPD3

290126-17

A) Latched Port Inputs
PORT--------------~·I,--------~,-------------------INPUTS _______________J I ' -___V_A_L1_D......- J ' -_ _ _ _ _ _ _ _ _ _ ___

OUTPUT
ENABLE
TpZX1

TeuSPD

TpZX3

PORT-=====================~~====~______{:=============

OUTPUTS _

B) Direct Port Inputs
Figure 12. Bus Management Unit

3-57

290126-22

intJ

5CBIC

Switching Characteristics
INPUTS OR
I/O INPUTS

(Continued)

VALID
_TLISU2--.. ... TLlH02 .....
TLlSU3
TLlH03

LATCH
ENABLE

_ _ TCISU2

TCLEH -

TCISU3
CLOCK

OUTPUT
ENABLE

I - - - TePD - - - - - +

+- !PXZ2 .....

TpXZ3

t--

TpZX2
TpZX3

COMBINATORIAL
OUTPUT

f.- !RPD2-.....
TRPD3
~

REGISTERED
OUTPUT

290126-18

A) Latched Inputs
INPUTS OR ------'""'I,_------~
VALID
I/O INPUTS OR
REGISTERED FEEDBACK
TCISU2
T1H02
TCISU3+--+--TIH03

,_-------------

-------'1'---------' ' - - - - - - - - - - - - - -

CLOCK
t-----TCWH----to~-

OUTPUT
ENABLE

-----~-+--------""""\
TpXZ2_
TpXZ3

- TCPD -

TpZX2_
TpZX3

COMBINATORIAL
OUTPUT
TRPD2
TRPD3
REGISTERED
OUTPUT

j
TSpW

SET,RESET
INPUT

"
-------------~-PD-3:.-.~------------------__ T
SPD

ASYNCHRONOUSLY
SET,RESET
OUTPUT - - - - - - - - - - -

•

290126-19

B) Direct Inputs
Figure 13; Programmable Logic Unit·

3-58

5CBIC

AC CHARACTERISTICS
BUS MANAGEMENT UNIT
Symbol

-45

Parameter

Typ

Min

. Units
Max

_ Max

TLlSU1

Port Input Setup Time to
Latch Enable (Fast Option)

TLlSU3

Port Input Setup Time to
Latch Enable (Control Bus)

TLiHOl

Port Input Hold Time to
Latch Enable (Fast Option)

TLlH03

Port Input Hold Time to
Latch Enable (Control Bus)

TLEH

Latch Enable High Time

45
45

Valid Output to High Impedance
(OE From Control Bus)

TpZXl

High Impedance to Valid Output
(OE From Fast Option)

TpZX3

High Impedance to Valid Output
(OE From Control Bus)

TLEPD1

Latch Enable (From Fast Option)
Tei Port Output Delay

hEPD3

Latch Enable. (From Control Bus)
To Port Output Delay .

TeuSPD

Port to Port Propagation Delay

TpXZl

Valid Output to High Impedance
(OE From Fast Option)

TpXZ3

PROGRAMMABLE LOGIC UNIT
Symbol

-45

Parameter
Min

Typ

Units
Max

TLlSU2

Input Setup Time to Latch Enable
(P-Term)

TLlSU3

Input setup Time to Latch Enable
(Contrpl Bus)

TLlH02

Input Hold Time to Latch
(P-Term)

~nable

TLlH03

Input Hold Time tobtch Enable
(Control Bus)

TCISU2

Input Setup Time to Clock (P-Term)

TCISU3

Input Setup Time to Clock (Control Bus)

TCLEH

Clock to Latch Enable Hold Time

TCPD

Combinatorial Output Delay

..,

135

3-59

5CBIC

PROGRAMMABLE LOGIC UNIT (Continued)

. Symbol

-45

Parameter

Typ

Min

Units
Max

TRPD2(S)

Registered Output frol'T1 Clock (P-Term)

TRPD3(7)

Registered Output from Clock (Control Bus)

TIH02

Input Hold Time to Clock (P-Term)

TIH03

Input Hold Time to Clock
(Control Bus)

TCWH

Minimum Clock Width High

Tcwi.

Minimum Clock Width Low

TSPD

Set Output Delay

100

TRPD

Reset Output Delay

100

...

115

Tspw

SETIRESET Pulse Width

TpXZ2

Valid Output to High-Impedance .
(OE from P-Term)

43
85

'TpXZ3

Valid Output to High Impedance .
(OE from Control Bus)

TpZX2

High Impedance to Valid Output
. (OE from P-Tem;)

TpZX3

High Impedance to Valid Output
(OE from Control Bus)

TCP1

Minimum Clock Period (Register Output
to Register Input Through Feedback Path)

110

Maximum Internal Frequency

TCP2

Minimum Clock Period Between
Logic Transitions (Inputs to Outputs)

Maximum External Frequency

.9.0
,

MHz

7.0

135

ns
MHz

NOTES:
S. Data out on rising edge of clock:
7. Data out on falling edge of clock.

inteligentPrQgramming Algorithm™

FUNCTIONAL ·TESTING

The 5CBIC supports the inteligent Programming AIgorithm which rapidly programs Intel H-ELPDs (and
EPROMs) using an efficient and. reliable method ..
The inteligent Programming Algorithm is particularly
suited to the production. programming environment.
This method greatly decreases the overall programming time while programming reliability is ensured as
the incremental program margin of each bit is. continually monitored to determine when tl)e bit has
been. successfully programmed.

Since the logical operation of the. 5CBIC is controlled by EPROM elements, the device is completely testl!ible. Each programmable EPROM bit control~
ling the internal logiC is tested using application-independent test program patterns. After testing, the
devices are erased before shipment to customers.
No post-programming tests of,the EPROM array are
required.

3-60

The testability and 'reliability· of EPROM-based programmable logiC devices is an important feature

inter

5CBIC

over similar devices based on fuse. technology.
Fuse-based programmable logic devices require a
user to perform post-programming tests to insure
proper programming.

TURBO-BIT
The device will consume quiescent current (75 /-LA,
typically) if no transitions are detected in the array
for 100 ns or more. This mode, the power-down
mode, can be enabled by selecting the Turbo Bit
OFF. If this bit is enabled, however, the device consumes active current. The power-down mode will revert to its active state if a transition is detected in the
array, at an extra delay of 25 ns in speed paths.

optimize a design to benefit from architectual features). It contains comprehensive third generation
software that supports several different design entry
methods, minimizes logic, does automatic pin assignments and produces the best design fit for the
selected EPLD. It is user friendly with guided menus,
on-line Help messages and soft key inputs.
In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices
and also to graphically edit programming files. The
software generates industry standard JEDEC object
code output files which can be downloaded to other
programmers as well.
The iPLDS II has interfaces to popular schematic
capture packages to enable designs to be entered
using schematics. One low-cost schematic entry
method is provided by SCHEMA II-PLD, which supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design
Manager, which provides a single user interface to
both SCHEMA II-PLDand iPLS II software. The other design formats supported are Boolean equation
entry and State Machine design entry.
The iPLDS II operates on the IBMt PC.XT, PC/AT,
or other compatible machine with the following configuration:
1. At least one floppy disk drive and hard disk drive.

LATCH-UP IMMUNITY

2. MS-DOStt Operation System Version 3.0 or
greater.
3. 512K Memory.

All pins of the 5CBIC have been designed to resist
latch-up which is inherent in inferior CMOS structures. The 5CBIC designed with Intel's proprietary
CHMOS II-E EPROM process. Thus, pins will not experience latch-up with currents up to 100 mA and
voltages ranging from -1V to Vee + 1V. Furthermore, the programming pin is designed to resist
latch-up to the 13.5V maximum device limit.

4. Intel iUP-PC
Computer

Universal

Programmer-Personal

5. A GUPI LOGIC Adaptor
6. A color monitor is suggested.
Detailed information on the Intel Programmable Logic Developement System is contained in a separate
Intel data sheet.

INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM (iPLDS II)

tlBM Personal Computer is a registered trademark of International Business Machines Corporation.
ttMS-DOS is a registered trademark of Microsoft
Corporation.

iPLDS II provides all the tools needed to design with
Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II
insulates the user from having to know all the intricate details of EPLD architecture (the machine will

3-61

infef

APPLICATION.
NOTE

AP-317·

June 1988

Implementing a PS/2 P~S
Using the 5AC312 EPLD

PEDRO VARGAS
PROGRAMMABLE LOGIC APPLICATIONS

Order Number: 292047-001
3-62

Ap·317

INTRODUCTION

POS REQUIREMENTS

The introduction of the IBM' PS/2 (Personal
System/2*) models and the innovative Micro Chaimel*
has provided numerous opportunities to develop creative interface solutions. Although the interface requirements are new, the designer is faced with making a
familiar choice: Use discrete chips (SSI/MSI), incorporate a PLD, or go for the custom IC solution.

Each adapter must implement POS with eight registers.
Depending on the adapter function, not all of them
need to be used. The first three (POS registers 0, 1,2) are
required because they provide the adapter ID and the
adapter enable/disable function necessary during setup
and error checking. In brief, the way that the system
uses POS is as follows:
I. The system selects the adapter to be placed in setup
mode by driving its -CD SETUP signal active.
2. The adapter is identified by reading two ID bytes
from POS and POS 1 (HEX 100 and 101).
3. The adapter is, disabled by writing "0" to POS 2
(HEX 102).
4. If implemented, Option Select Data is written to
POS 3,4, S.
5. The adapter is enabled by writing "I" to POS 2.
6. The adapter is out of setup mode when the system
drives the -CD SETUP signal inactive.

In the past, using TTL on the PC/XT/ AT bus was
often a good choice, but the reduced size of the PS/2
adapters ("plug in boards") increases the cost of board
space dramatically. The custom chip solution is probably the best for companies that have a well-defined
product, large volumes, and can afford the cost of the
chip development. The third choice, using a PLD, is
one that has not been popular in PC bus interfacing due
to the limited function and performance of most PLDs.

The Intel SAC312 is a third-generation EPLD that
gives designers the resources needed to interface to buses like the Micro Channel. In addition, it provides two
benefits not completely provided by either of the other
two choices; high integration, and re-programmability.
The rest of this application note contains a detailed presentation of a basic POS (Programmable Option Select)
implementation for the PS/2 Micro Channel that is
done with the SAC312 EPLD.

The actual hardware implementation ofPOS is summarized in IBM technical documents, but the details are
left up to each designer.

ADAPTER REQUIREMENTS
The adapter used for this design is an Intel single-function card that incorporates two modems controlled by a
80C186. Since it performs only one function, there was
no need to implement the POS Option Select bytes.
(These POS bytes are used with multi- function adapters that do more than one task and reside in the system
with similar adapters.) In this case, the only require-,
ments were to provide the ID bytes and the enable/disable features, which are done with POS registers 0,1,
and 2. Figure 1 shows the POS register layout and the
typical POS hardware implementation as suggested by
IBM. Table 1 defines the POS registers.

PS/2 MICRO CHANNEL
One of the best features in the PS/2 models is the capability to do system and adapter configuration with software instead of hardware. This feature, called· POS
(Programmable Option Select), eliminates the need for
switches on the motherboard and adapters by replacing
them with programmable registers. The idea is, rather
than removing boards and manually setting switches,
all configuration information is located in files and can
be read or written to the motherboard or to the adapters through the Micro Channel. The motherboard and
each connector on the Micro Channel has a unique signal called -CD SETUP that initiates a setup mode when
it is active. Only one connector at a time can be in the
setup mode, which provides an organized way to perform initialization.

'IBM, Personal System/2 and Micro Channel are trademarks of International Business Machines Corporation.

3-63

intJ

AP-317

LOCAL
ADAPTER
CONTROL

I
!'--

c:
!'-lOR
A02

I
'--

c:
c:

2
10....,.......

AOO

t---.
I---t---.
t---.
I---t---.

'-:'--

AOt

Data
Gate

_CDSETUP

POS
Registers

Data
Gate

'--

Decode

~
~
I---t---.

'--

000-007

'--

Drivers

Decode
-CDSETUP

A02

f--I

lOW

f--I

MSBYTE

--'

I
10
Drivers

LSBYTE

f--I

C
--'
C
C
292047-1

Figure 1. Typical Adaptor Implementation of POS
Table 1. POS I/O Address Decode
Address
(hex)

0100

POS Register 0

0101
0102

-CD
SETUP

Address Bit

Function

Adapter Identification Byte (Least Significant Byte)

POS Register 1

Adapter Identification Byte (Most Significant Byte)

POS Register 2

Option Select Data (Byte 1)'

0103

POS Register 3

Option Select Data (Byte 2)

0104

POS Register 4

Option Select Data (Byte 3)

0105

POS Register 5

Option Select Data (Byte 4)'

0106

POS Register 6

Subaddress Extension' (Least Significant Byte)

0107

POS Register 7

Subaddress Extension (Most Significant Byte)

'These bytes contain one or more bits with specific value assignments

3-64

AP-317

RING 1
LOGIC ARRAY

I
I
I

1/0.1

.1
I
I
r------

CLKjlNP1

1/0.2

I
I

I
L _____ _

LlNP1

I
I

1/0.3

-,
I
I
I

r------

LlNP2

1/0.4

I
I
I
I
I
L_.:.
___ _

LlNP3

I
I

1/0.5

I
I
I

LlNP4

1/0.6

LlNP5
I
I

1/0.7

I
I

I
I
r------

LlNP6·

1/0.8

I
I
I

I
I
L _____ _

LlNP7

I
I
I

1/0.9

-,
I
I

r------

LlNP8

1/0.10

I
I
I

I
I

L _____ _

ILEjlCLKjlNP2

I
I
I

1/0.11

I
I
I

1/0.12
RING 2

Figure 2. 5AC312 Architecture.

5AC312 EPLD

DEVICE DESCRIPTION

With 12 macrocells and a host of other features, the
5AC312 is Intel's newest EPLD. The device is based on
the same CHMOS process used in other Intel devices.
This EPLD provides an abundant feature set, but its
strength lies in being able to efficiently implement one
very important function missing from most PLDs: register-logie-register functions.

The 5AC3l2 (Figure 2) contains 12 macrocells with
programmable outputs and inputs. A macrocell is the
basic block associated with each output register within
the EPLD. The 5AC312 has the following features:
• 12 I/O macrocells with dual feedback for implementing buried registers.

3-65

infef
terms per macrocell (Figure 4). Product Term Allocation takes place in two rings of six' macrocells.
Within each ring (Figure 2), individual macrocells
can allocate p-terms to/from adjacent macrocells.
This is a real benefit in bus decoding where intermediate signals can have few or many p-terms all within
the same logic function. Most designers that use
PLDs have at least one horror story of a design that
required 10 or more p-terms and a device that could
only provide 8.
3. A flexible output structure is a must for efficient bus
interfacing, which quite commonly requires lots of 1/
and complex control signals. The 5AC312 meets
these demands head-on with dual-feedback paths
and two p-terms per control signal on all I/O macrocells. This means that certain functions, like state
machines, can be buried and a pin won't be wasted
because it can be used as an additional input. Also,
output enables and register operations are frequently
generated by a combination of memory, 110, read,
and write strobes. Many times these control signals
require two p-terms or the equivalent of an external
read/write multiplexer. Prior to the 5AC312, the
only way to implement this in PLDs was to waste a
macrocell to inefficiently provide this function. Figure 5 shows the macrocell structure and details this
third benefit.

'. 8 programmable inputs that can be configured as
latches, registers, or flow through inputs. These can
be clocked synchronously or asynchronously.
• Product term allocation on each macrocell.
• 2 product terms on all macrocell control signals.
• 2 multi-function pins; a CLK/INPUT and a ILE/
ICLK/INPUT.
• 40 MHz operation.
The 5AC312 provides three major benefits that are especially important to designers working on bus inter'
faces:

1. The availability of input latches (Figure 3) makes it

easy to synchronize bus control signals synchronously or asynchronously. The latches can be clocked as a
group of 8 or individually, as is quite common on
most buses. Input latches also make state machine
designs more reliable. Since buses are prone to glitches and other transients, the ability to hold the inputs
stable while transitioning through states makes the
difference between a clean and a jittery state machine.
2. Product Term Allocation (Patent Pending) brings a
new concept to the Intel EPLD family and makes
the 5ACJ12 unique among PLDs. This feature
means that the designer can implement large designs
that contain as few as zero or as many as 16 product

INP D - - - - - . l I N
PIN

OUT~------H

LOGIC

ARRAY

P-TERM

ILE/ICLK . C>---------'----'--'-....;...-------I
PIN
292047-3

NOTE:

Flow-through input selected by connecting ILE P-Term to Vee.
Figure 3. 5AC312 Input Structure

3-66

LOGIC ARRAY

LOWER HALF
P-TERMS 1-4
MACROCELL

P-TERMS ALLOCATED TO
MACROCELL #4
(NEXT MACROCELL IN RING)

IC
C
CD

...

UPPER HALF
P-TERMS 5-8

f'>

...'U
0

a.
c

...n

-I

...

c.l
a, 3

l....

MACROCELL
#4

...... ~

"'"

0"
:::J

+
".,

+
~
UPPER HALF
P-TERMS 5-8

P-TERMS ALLOCATED TO
MACROCELL #4
(PREVIOUS MACROCELL IN RING)

MACROCELL

292047-4

(
LOGIC ARRAY

TO NEXT
MACROCELL

FROM NEXT
MACROCELL
OUTPUT
ENABLE

PRESET

::n

ca
c

iiJ

OUTPUT
MUX

...ow
I\)

til

III
a, 5"
s::

MACROCELL
REGISTER

Co)

..........

Co)

(I)

a
~

ASYNCH. CLK (CLKB)

iiJ
CLEAR
TO PREVIOUS
MACR09ELL'

FROM PREVIOUS
MACROCELL

292047-5

intJ

AP-317

Since it is a CMOS EPLD, the 5AC312 has very frugal
impact on the current allotted by the PS/2 power supplies. The device consumes much less power than an
equivalent TTL or PAL implementation.

ClK

000

001

5AC312 POS IMPLEMENTATION·
The POS requirements placed on our modem adapter
are easily met by putting the 5AC312 to some creative
.use. In terms of performance, the· 25 ns propagation .
delay and capability to operate to 40MHz is more than
adequate for the system requirements during setup
mode.

002

003
POSO, 1
004

RESOURCE ALLOCATION
POS registers 0, I, and 2 can be easily accommodated
with 12 macrocells. Eight macrocells are used to load
and output the ID bytes from POS 0 and 1. One macrocell is used as the LSB of POS register 2. The remaining
three macrocells make up a state machine that internally sequences through the setup mode. The partitioning·
used for this design is shown in Figure 6.
The state diagram shown in Figure 7 explains the operation of the design. During SO (state 0), the 5AC312
idles until -CD SETUP is driven active. The adapter is
already disabled and POS 2 is zero because during power-up and reset the 5AC312 registers come up as logic
O. When -CD SETUP is driven active, the 5AC312 goes
to S1 and loads the first ID byte, FFH. It remains in S1
while waiting for a READ POS 0 command. As soon
as POS 0 is read the state machine cycles to S2 and
outputs FFH which is the least significant byte for our
adapter. Once READ POS 0 is inactive, the 5AC312
cycles to S3 where it loads the second ID byte (7FH)
_and waits for READ POS 1 active. The last ID byte is
put on the bus when READ POS 1 comes and the
machine goes to S4. Since we know that the next two
setup operations are I/O writes, the 5AC312 remains in
S5 while PQS 2 is disabled and enabled per the Micro
Channel bus specification. This operation, which is a
bit write of a register, is easily done by using the
5AC312's dual feedback capability. While bit 0 of POS
2 uses the DOD line, internally it gets routed. to a separate register. Without dual feedback this internal transceiver function would be impossible to implement.

005

006

007

POS2

STATE
MACHINE

292047-6

Figure 6. Register Allocation

for grabs. It is conceivable that more than one company
may assign the same ID -to their own cards. In this case,
companies that implement the POS function in discrete
TTL or a custom IC may have a problem. That is,
they'll either have to re-do the design, which could be
expensive, or, cut and jumper the board, which, goes
against the Micro Channel specification and still costs.

The IBM Technical Reference Manual provides a table
for suggested ID bytes arranged by adapter type. The
modem card falls under the category of storage device,
so 7FFFH was chosen. While IBM has assigned unique
IDs for its own cards the third party choices are up

Since the 5AC312 is re-programmable, the risk of conflicting IDs is minimized since all that is needed

3-69

inter

AP-317

CDSETUP
:OUTPUTS DISABLED
:SET POS 2 0

READ POSO

:LOAD POS 0 (FFH)

READ POSO

:10 ON BUS (FFH)

READ POS 1

:LOAD POS 1 (7FH)

READ POS 1

:10 ON BUS (7FH)

CDSETUP

:WRITE DISABLE POS 2
:WRITE ENABLE POS 2
292047-7

Figure 7. State Diagram

MICRO
CHANNEL
BUS

~
A34
A32
A33
AOl
B34
A18
A17
A16

MICRO
CHANNEL
BUS
ADA PTCLK

Y
M/-IO

-so

5AC312
CL K/INPl

1/0.12~----·

(SMO) .1/0.11
LlNPl

1/0.9 _

LlNP2

-Sl
-CD SETUP
-CMD
AO
Al
A2
(SM1)

BUS
DRIVER

VCC

001

002

003

1/0.10_

LlNP3

1/0.7 - - - - :

LlNP4
LlNP5

1/0.8 1/0.6

LlNP6

1/0.5 ~

LlNP7

1/0.4

LlNP8

1/0.3

000

004

DOS

006

007

,,---

(SM2)

A37
B38
A38
B39
B40
A40
A41
A42

CDEN
1/0.2
ILE/ICLK/INP2DECODE ,

1/0.1
GND

TO/FROM
ADAPTER LOGIC
292047-8

Figure 8.

P~S

3·70

Pinout

AP-317

is to burn another EPLD with the appropriate bytes.
The pinout for the 5AC312 POS implementation is
shown in Figure 8. Note that a bus driver is required to
support the current levels on the Micro Channel. The
definition for the signals can be found in the IBM literature, but briefly is as follows:
M/-I/O
Memory or Input/Output.
-SO, -S 1
Status bits 0 and 1.
-CD SETUP Card Setup.
-CMD
Command.
AO-A3
Address bits 0-3.
DOO- D07 Eight bit data bus.
DECODE Adapter decode for the higher order 16
bit address bus.
EN/-DIS
EnablelDisable adapter.

A description of the Micro Channel Adapter Description File and the Configuration Utilities is beyond the
scope of this article. The IBM literature is very descriptive in how adapters are setup and configured, and the
reference section contains the names of the pertinent
documents.
This modem adapter POS implementation, was easily
done in one 5AC312 device. Adding other Micro Channel. interface features like arbitration or interrupt sharing would overburden it. Since this adapter did not
have those requirements it was not a problem. However, a complete POS implementation with Option Select
. Bytes and other features could be done with the
5AC312's big brother, the 5AC324.

SUMMARY
Interfacing to the PS/2 Micro Channel can be a difficult chore when using PLDs or other solutions that are
not flexible or powerful enough. However, the 5AC312
with its powerful features like product term allocation
is a giant step in the right direction to making the job
easier.

DESIGN FILES
The 5AC312 was developed and programmed using the
Intel IPLSII 1.5 EPLD software: This software provides a variety of entry methods like Boolean equation,
state !p.achine, and schematic capture. For this particular design, equation entry was the most' convenient
since the implementation was done in one IC.

ACKNOWLEDGEMENTS

The minimized and ordered .LEF (Logic Equation
File) for the 5AC312 is shown in Figure 9. A quick
glance at a few items really points out the power of the
5AC312. }<'or example, the equation for variable ENd
has 11 p-terms. Without p-term allocation this would
not· have fit unless it was done with two macrocells,
which is wasteful. Also, the output enable control signal OE contains two p-terms for each macrocell. Again,.
without the 5AC3l2 some work-around may have been
possible. But its unlikely that the design could have fit
in one device, resulting in a functional but not too optimal solution. Finally, in keeping with good state machine design practices, all of the critical bus signals
were received by registers with the EPLD primitive
RINP (Registered Input).

3-71

Many thanks to Thorn Bowns and Dan Smith for their
help with this article.

REFERENCES
1. IBM Personal System/2, Model 80, Technical Reference.

2. IBM Personal System/2, Hardware Maintenance
Reference.
3. Intel5AC312 EPLD Data Sheet.
4. Electronics "Inside Technology", September 17
1987.

AP-317

THOM BOlmS"
INTEL
DECEMBER 4, 1987
1
001
SAC312
Implements P~S for t~e PS/2 using a SAC312.
LEF Version 1.5 Baseline 4.1i 21 Nov 1987
OPTIONS: TURBO=ON
PART:
5AC312
INPUTS:
MIO@3, nSO@4, nSl@5, nCDSETUP@6, nCMD@7, AO@8, 'Al@9, A2@10, DECODE@13,
'
,
CLK@l, DO@23
OUTPUTS:
DOO@23, DOl@22, D02@2l, D03@20, D04@19, D05@l8, D06@l7, D07@l6, EN@14,
SMO@2, SMl@ll, SM2@lS
NETWORK:
IRE = CLKB(CLK)
CLK
INP (CLK)
MIO
RINP(MIO, IRE, GND, GND)
nSO
RINP(nSO, IRE, GND, GND)
nS1
RINP(nSl, IRE, GND, GND)
nCDSETUP,= RINP(nCDSETUP, IRE, GND, GND)
nCMD = RINP (nCMD, IRE, GND, GND)
'AO = RINP(AO, IRE, GND, GND)
Al = RINP (AI, IRE,GND, GND)
A2 = RINP(A2; IRE, GND, GND)
DECODE = INP(DECODE)
DO = INP (DO)
DOO
RONF(DOOd, CLK, GND, GND, OE)
DOl
RONF(DOId, CLK, GND, GND, OE)
D02
RONF(D02d, CLK, GND, GND, OE)
D03
RONF(D03d, eLK, GND, GND, OE)
,D04
RONF(D04d, CLK, GND, GND, OE)
DOS = RONF(DOSd, CLK, GND, GND, OE)
D06
RONF(D06d, CLK, GND, GND, OE)
D07
RONF(D07d, eLK, GND, GND, OE)
EN, EN = RORF(ENd, CLK, GND, GND, vee)
SMO = NORF(SMOd, CLK, GND, GND)
SMl
NORF(SMld, CLK, GND, GND)
SM2
NORF(SM2d, eLK, GND, GND)
292047-9

Figure 9. POS Design File

3-72

AP-317

EQUATIONS:
SM2d

5M2' * SMl * SMa * nCDSETUP' * MIa' * nSO' * A2' * Al' * DECODE •
nSl
+ SM2 • SMl' * nCDSETUP';

SMld

nSO' * A2'

* AI' * DECODE •

+
+
+
+
+
+
+
+
+
+
+

(5M2' * 5MO * MIO' * nSO' • n5l • A2' * AI' * DECODE
5M2 • 5MO' * MIO' * nSO' * nSl * A2' * Al' * DECODE
SMl :Ie MID' * nSQ' * n5l * A2' * AI' • DECODE
5M2 * SMl
nCD5ETUP)' ;

5MOd

ENd

* SMl' * SMa * nCDSETUP' * MIO'

SM2'
nSl
SM2'
5M2'
5M2'
5M2'
5M2'
5M2'
5M2'

:Ie

* 5Ml * 5MO' * nCD5ETUP'
* SMl * nCDSETUP' * DECODE'
* 5Ml * nCDSETUP' * Al
* SMl * nCDSETUP' * A2
* 5Ml • nCDSETUP' * nSl'
* 5Ml * nCDSETUP' * nSO
* 8Ml * nCDSETUP' * MIO;

DO * MIa' * A2'

+ n50' * EN
+ n5l * EN
+ 5MO' * EN

Al * AO'

DECODE

5M2 * 5Ml' * 5MO

n5l'

nSO

+ SMl * EN
+ 5M2' * EN
+ DECODE' * EN
+ AO * EN
+ Al' * EN
+ A2 * EN
+ MIa * EN;'

D07d

5M2' * SMO'
+ 5M2' * SMl';

D06d

(5M2

SMl)';

D05d

(5M2

5Ml)';

D04d

(5M2 • 5Ml)';

D03d

(SM2

SMl)';

D02d

(5M2

5Ml)';

(5M2

5Ml)';

DOld
OE

5M2 * 5Ml' * SMO' * MIa' * nSO' * A2' * Al' • DECODE * nSl
+ 5M2' * SMl * SMO' * MIO' * nSO' * A2' * AI' * DECODE * nSl;

DOOd

(5M2 * SMl)';

END$
292047-10

Figure 9. POS Design File (Continued)

3-73

AP-319

APPLICATION
NOTE

November 1988

Designing with the
5AC312/5AC324 EPLDs

DAVID BICKEL
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292049-001

3-74

inter

AP-319

CLEAR signals (2 p-terms per signal). The other 8 feed
the data input to the macrocell and are split into two
groups of four (upper half and lower halt). See Figure
2. Each group of four can be allocated to an adjacent
macrocell if needed.

INTRODUCTION
The Intel 5AC312 EPLD (Erasable Programmable
Logic Device) was developed to break down certain existing PLD architectural barriers and meet increased
performance needs. The Intel 5AC312 EPLD was designed by EPLD users with direct input from system
designers. In the design process, emphasis was placed
first on gate utilization, and then on density.

As shown in Figure I, the 12 macrocells of the 5AC312
are further divided into two "rings" with 6 macrocells
per ring. Allocation of p-terms to adjacent macrocells
can occur with a given ring. See Figure 3 for p-term
allocation scheme.

This application note highlights the advanced architecture and features of the 5AC312 EPLD and shows the
benefits of designing with this new device over more
traditional PLD architectures. These features include
enhanced input structure with register/latch option on
all input pins (synchronous or asynchronous operation); user-controllable, software-supported p-term allocation scheme in all macrocells; and multiple p-terms
on control functions (asynchronous CLK, SET, RESET,OE).

Each macrocell register in the 5AC312 is also equipped
with an asynchronous PRESET signal. The PRESET
function can be constructed in more traditional architectural devices such as the 5C060 and 5C090 using
combinational logic and feedback, however two macrocells are consumed in the process. To illustrate this difference, compare Figure 2 to the implementation
shown in Figure 4. The PRESET function would require additional macrocells in traditional architectures
if it were expanded beyond a single p-term.

It should also be noted that the features and information described. here also apply to the new 5AC324
EPLD. The 5AC324 isbasically a 24 macrocell version
.of the 5AC312.

MULTIPLE P-TERMS
Multiple p-terms on the control functions (asynchronous CLOCK, PRESET, RESET, and OE) increases
the efficiency of the device. Multiplexed I/O is accomplished by controlling the output buffer associated with
each macrocell using the 2 p-terms set aside for implementing an OE function. Multiple p-terms create a
means to avoid using macrocells for control logic. For
example, it would take two macrocells in the 5C060
and 5C090 EPLD to drive the OE line by a 2 p-term
signal. To illustrate, compare Figure 2, the 5AC312
macrocell structure, to Figure 5, a diagram of how a
two p-term OE signal can be implemented in a 5C060
or 5C090 EPLD.

PROGRAMMABLE INPUTS
The 5AC312 was designed with a highly flexible macrocell and I/O structure allowing the device to implement both combinational and sequential logic functions. The enhanced input structure not only allows the
device to latch and hold· incoming data, but also to
implement register-combinational-register logic to easily accommodate state machine designs. Figure 1 shows
a global view of the 5AC312 architecture.
The 5AC312 is equipped with 8 user-programmable input structures that can each be configured to work in
one of five modes: I) synchronous D-type register, 2)
async,hronous D-type register, 3) synchronous D-type
latch, 4) asynchronous D-type latch, and 5) flowthrough input. Each input can be configured independently of the others. The desired configuration is implemented through the programming of EPROM architecture control bits by the logic <;ompiler under user-control.

P-TERM ALLOCATION
P-term allocation allows for more efficient use of pterms and thus increased device utilization by raising
the number ofp-terms per macrocell to 16. P-term allocation, where p-terms are dedicated to certain macrocells, should not be confused with p-term sharing,
where several macrocells can actually use the same pterms. The p-term allocation scheme in all macrocells is
user-controllable and software supported, and provides
the ability to satisfy designs with large p-term requirements. P-term allocation is ideal Jor p-term intensive
applications such as complex counters or comparators.

MACROCELL STRUCTURE
The 5AC312 also has a unique macrocell array structure that allows for user-controllable, software-supported product term allocation in each of its 12 macrocells.
Each of the 12 macrocells also has a dual feedback option with independent feedback and I/O paths. Each
macrocell has 16 product terms, 8 of which control the
OE, PRESET, ASYNCHRONOUS CLOCK, and

P-term allocation in the 5AC312 is used when a design
requires one of the 12 macrocells to employ more than
8 p-terms. P-term allocation is simply the transfer

3-75

AP-319

RING 1
LOGIC ARRAY

CLK/INPI

•
•

••
•

•
r------

C>-------i

••

•
•L _____ _
•

LlNPl

••
-,•

.'•

•
r------

LlNP2

1/0.1

1/0.2

1/0.3

1/0.4

•

••
•l _____ _
••
•
••
•

LlNP3

LlNP4

LlNP5

•••
•
•

•
r------

LlNP6

•
••
•
•

1/0.5

1/0.6

1/0.7

1/0.8

L _____ _

.'
-,

LlNP7

1/0.9

•

••
r-----••
•
••l _____ _

LlNP8

ILE/ICLK/INP2

C>-......,------!

•
•
•

.'••,,-----'-

1/0.10

1/0.11

1/0.12

RING 2

292049-1

Figure 1. 5AC312 Architecture

3-76

i
LOGIC ARRAY

TO NEXT
MACROCELL

FROM NEXT
MACROCELL
OUTPUT

I I

PRESET

r--"'\.

cE'

...CD

!':I
U1

»
C'l

II II II II

LOWER HALF

OUTPUT
MUX

...

Co)

!XI

(,J

lO~rlS
II

III

5'
3:

~
"tI
W

,
.....

MACROCELL
REGISTER

III

...n0
n

!a
...
c

...2'CD
CLEAR
FROM PREVIOUS
MACROCELL

292049-2

,inter

AP-319

LOGIC ARRAY

LOWER HALF'
P-TERMS 1-4

MACROCEll

P-TERMS ALLOCATED TO
MACROCElL #4

(NEXT MACROCELL IN RING)

UPPER HALF
P-TERMS 5-8

MACROCELL
#4

UPPER HALF'

P-TERMS 5-8

P-TERMS ALLOCATED TO

MACROCELL #4
(PREVIOUS MACROCELL IN RING)

MACROCELL

292049-3

Figure 3. Product Term Allocation (8 + 4 +4)

3·78

AP-319

NOT
CLOCK
DATA

PRESET

-+----+-......

REG 1 OUTPUT

> .....-£::>

------+-+-------1

CLEAR

REG 2 OUTPUT

OUTPUT ENABLE

1...-----------4.....-1

~_-c> OUTPUT

CON,
292049-4

Figure 4. Implementation of D Flip-Flop with Added Preset Function Using Combinational Logic
of logic resources (p-terms) from areas they are not
being utilized to other areas within the chip where they
are needed. As shown in Figure 3, each macrocell has
the potential to borrow 4 more p-terms to add to the 8
it already has from each of its adjacent macrocells. This
increases the maximum number of p-terms per macroceil to 16. Thus, any macrocell within the 5AC312 has
the potential to satisfy logic functions requiring between 0 and 16 p-terms.

OENI

>-+--C>

OEN2

P-terms can be allocated in a "shift register" mode
within each of the two rings of the macrocell; however,
allocation of p-terms between rings is not possible. See
Table'l for a listing of adjacent macrocells within pterm allocation rings.

DATA

----t

CLOCK

----t

OUTPUT ENABLE

> ........-c>

OUTPUT

CLEAR - - - - - '
FEEDBACK - - - - - - - -.....
292049-5

Figure 5. Implementation of
2 P-Term OE Control Signal

Table 1. 5AC312 Product Term Allocation Rings
Ring 1

Ring 2

Current
Next
Previous Current
Next
Previous
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
'1
2
8
7
8
12
2
3
1
8
9
7
3
4
2
9
10
8
4
5
11
10
9
3
5
6
4
11
12
10
6
1
5
12
7
11

3-79

intJ

AP-319

A given macrocell's output structure is still available
for use when some or all of its p-terms are allocated
away. If all of the p-terms of one macrocell are allocated away to its respective adjacent macrocells, the data
input to that macrocell defaults to GND. This polarity
can be changed ihrough programming of the invert se~
lect EPROM bit. The I/O register as well as all secondary controls to this I/O control block are still available
and can be used as needed for design purposes.

POWER ON CHARACTERISTICS
Another feature of the SAC312 is its power-on characteristics: The I/O registers of the SAC312 experience a
reset to their inactive state upon Vcc power-up. Using.
the PRESET function available for each macrocell allows any particular register preset to be achieved after
power-up, The inputs and outputs of the SAC312 begin
responding approximately 10 ,.,.S (6 ,.,.S tYPiCal) after
Vcc power-up ·or after a power-Ioss/power-up sequence.

DUAL FEEDBACK
The 5AC312- contains separate input and feedback
paths (dual feedback) on each of the macrocell I/O
control blocks. This allows designs to utilize input pins
when the associated macrocells have been assigned a no
output with buried feedback primitive. Multiplexed
I/O is accomplished by controlling the output buffer
associated with each macrocell using the 2 p-terms that
implement the OE function. Registered outputs may be
clocked from the synchronous CLK/INPI pin or asynchronously -clocked by. the 2 p~terms available for
ASYNCIL-CLK.

FIRST
INPUT

LAST
INPUT

t,K

POWER DOWN MODE
A trade-off between power consumption and speed is
possible when using the SAC312 by programming the
"Turbo Bit". Left unprogrammed and with no transition occurring at the device inputs for a period of
approximately 100 ns, the device powers-down the internal array while holding the outputs at their previous
levels. _At the next- input transition occurrence, the
SAC312 powers-up the array and reacts to the change
in input conditions. If the "Turbo Bit" is programmed,
the power-down circuitry is disabled and the device will
not power-down even if there are no more transitions.
The array power-up sequence requires an additional 20
ns of propagation delay. Power supply current during
poweI'~down is no more than 120 ,.,.A.;See Figure 6.

:: )K
'V'

,V'

j--tpo-o
OUTPUT

.J~
~

CURRENT

ACTIVE MODE
Icc

.
.

t--:-tpoVALID OUTPUT

MODE
TO """"
~ANOBY

KVALIO OUTPUT

TO ACTIVE
MODE

MODE
.
IS8)

ACTIVE MODE
Icc

OmA
292049-6

Figure 6. 5AC312 Standby and Active Mode Transitions

3-80

infef

AP-319

EXAMPLE

SUMMARY

An example application for the 5AC3l2 can be shown
by replacing a PAL' 20R6 and a 374 D type flip-flop in
a design due to a power constraint. The same implementation can be achieved consuming less power using
one 5AC312 EPLD. Compare Figures 7 and 8. Straight
jumpers can be substituted in the PC board where the
374 sits, and since the clock signal is already available
on the PAL socket, it can be internally routed to clock
the input registers of the 5AC312. The 5AC312 can
then be programmed to match the existing pin assignments and therefore require no PC board re-layout. The
internal circuitry of the 5AC312 allows the EPLD to
act as both a D type flip~flop and a PAL.
.

The 5AC312 EPLD, which uses advanced CHMOS
EPROM cells as'logic control elements instead of polysilicon fuses, represents an innovative device to help
overcome the primary limitations of standard PLDs.
With its advanced features, proprietary architecture
and macro(;ell structure, the 5AC312 is capable of implementing high performance logic functions more effectively than was previously possible. The p-term allocation scheme is a unique feature, increasing the efficiency of the device immensely. The PRESET signal
and 2 p-term control lines are also features giving the
5AC312 added efficiency in many designs.
These same architectural features have been included in
the 5AC324 EPLD, making that device ideal for even
higher integration applications. Refer to the 5AC324
Data Sheet for details on that device.

(

DATA

374
18
17
14
13
8
7
4
3

D FLlP- FLOP
19
8D 80
16
7D 70
15
6D 60
12
5D 50
9
4D 40
6
3D 30
5
2D 20
2
10 10
CK
OE
1111

2DR8
23
14
11
10
9
8
7
6
5
4

---*"
,..L

112
111
110
19
18
17
16
15
14
13
12
11
CK
A.

-=1 (
(

CLOCK
SELECT

WRITE

(

RESET

~
~

*""-+
1+-+
*-+
~
~
~

OUT1
OUT2
OUT3
OUT4
OUT5
OUTS
OUT7
OUT8

OE
13

( ADDRESS

(

06
05
04
03
02
01
102
101

-==292049-7

Figure 7. Original Implementation Using a 374 0 Flip-Flop and A PAL20R6

'PAL is a registered trademark of Monolithic Memories, Inc.

3-81

Ap·319

(

DATA
5AC31.2
23
14
11
10
9
8
7
6
5
4

J-(

CLOCK

(

SELECT

-4
,..l.

112
111
110
19
18
17
16
15
14
13
12
11
CK

~
~
~
~

Q6
Q5
Q4
Q3
Q2
Ql 16
22
IQ2
15
IQl

rH--+

WRITE

(

RESET

( ADDRESS

(

OUT1
OUT2
OUT3
OUT4
OUT5
.... OUT6
OUT7
OUT8

-::'-

292049-8

Figure 8. Example Implementation Using the 5AC312

3-82

PROGRAMMABLE AND/ALLOCATABLE OR BASED EPLD
ADDRESSES THE NEEDS OF
COMPLEX COMBINATIONAL AND SEQUENTIAL DESIGNS
Todd K. Koelling
Applications Engineer
Intel Corporation
1900 Prairie City Road
101som, CA 95630
I NTRODUCTI ON
Matching programmable logic applications
with programmable. logic devices has become a
difficult task. Increasing demands for
higher integration, higher performance and
lower cost continue to drive system design
engineers on to new technologies. The
programmable logic industry has adeptly
responded by supplying a wide variety of
devices. At times, however, it is hard to
differentiate these devices and to determine
which makes the best solution for a
particular application.

GATE
AXIS

(GATES)

(FLlP·FLOPS)

In a small way, this paper will attempt to
differentiate devices and to determine
which devices make the best solutions for
groups of appfications. This task will be
accomplished by taki~g a general look at
applications, the history of PLD arrays and
a new device which solves several design
problems.

Figure 1: ' Gate/Register Coordinates
Common TTL functions are easily graphed.
Figure 2 displays a comparator, storage
register, shift register and counter. The
comparator is a combinational circuit
(purely gates) and hence lies along the gate
axis. The storage register, on the other
hand, is purely flip-flops and hence lies
along the register axis. The shift
regi ster is primaril y fl ip-fl ops -- pI aci ng
it close to the storage register -- but it
includes some gate logic, thus moving it up
the gate axis. The counter is a good
example of' a function that lies somewhere
in-between the two axes. The counter must
store its current state. and thus leans
heavily upon the registers, but it also uses
a significant amount of gate logic to
generate the next count state. The
inclination toward the gate or register
axis,depends on the features the counter
incorporates. Up and down count operation,
clear and preload functions, and count
enable/disable circuitry, . all move the.
counter increasingly toward the gate axis.
The magnitude of the counter (as with the
other functions) depends on the number of
bits and features it includes. That is, a
~6-bit counter is twice as large asari 8-bit
counter which is, twice as large as a 4-bit
counter, provided the feature set remains
the same.

APPLICATIONS
College textbooks 1 on digital design teach
that fundamentally there are only two types
of applications: combinational and
sequential. A combinational circuit
generates outputs based on the immediate
statu~ of a group of inputs.' A sequential
circuit uses some mechanism to store data
before generating the next set of outputs.
Inside combinational and sequential
circuits are. two fundamental elements:
gates and registers. Gates .are the prime
component of combinational circuits where
the output is an 'immediate function ~f .the
input. Registers are the static stor'age
element added in sequential circuits to
latch and hold dat~ until the next cycle.
Figure 1 displ~ys gates and register~
graphically. The coordinates measure
registers along the x-axis and gates along
the y-axis. In this space, any
combinational or sequential application
can be displayed.
3-83

system represents a healthy mix of both
gates and registers. This means it is
prob,ab 1y a state mach i ne or some sort of
sequential application. Hence, the middle
third region will be called the "state
maGhine" region, though some state machines
may land in the other two regions. The
coordinate system with the three regions
segmented and labelled is shown in Figure 4.

GATE
AXIS

(GATES)

GATE
AXIS
(FLIP· FLOPS)

Hoc»I.Y
COMBINATIONAL
REGION

STATE

MACHINE

AEOKlH

Figure 2:

Common Functions on Coordinates

(FLIP· FLOPS)

Figure 4:

Application Regions

ARRAY ARCHITECTURES
Through' the yea~s, programmable logic
devices have evolved by trying to meet the
needs of combinational and sequential
applications. This has been accom~lished
through higher integration, higher
flexibility and higher performance and has
resulted in the myriad of PLDs available
today. Though the features have varied and
expanded immensely, the core of the
programmable logic device has remained
virtually the same. It is this core -- the
implementation of the combinational logic
array -- which ,deserves a closer look.

GATE
AXIS

(GATES)

(FLIP· FLOPS)

H1QII.Y
REGISTERED
REO----'1

L
SELECT

BAUO

DATA

RATE
SELECT

CIRCUITRY

r:--<:J BAUDOUT
: •••r:I1If':

Figure 10:

Programmable Baud Rate Generator
Circuitry

Though not a state machine. the programmable
baud rate,generator circuitry for the Intel
8251 Universal Synchronous/Asynchronous
Receiver/Transmitter does have a good
mixture of gates and register functions,
Qualifying it for the state machine
application region. The input baud rate
(BAUOIN) is divided down to lower baud
rates through a series of toggle flip-flops.
Then, based on the select data stored in the
02, 01, 00 flip-flops, one of the
divided-dowri baud rates'is selected and sent
out on the baud rate out pin (BAUOOUT).

By using the input latches avaf1ab1e on the
5Ac312, the select data inputs can be stored
immediately at the input pin rather than
inside a macrocel1. This saves a macroce11,
saves a pin, and decreases the delay time.
Second, since the 5AC312 has separate
register and pin feedbacks on each
macrocell .. the baud rate divider can be
buried by using the register feedback paths
while the input feedback paths remain
available for use as standard inputs.
Inside the 5AC312, the circuit consumes 8 of
12 macroce11s. and 7 of 24 pins, a
siginificant I/O pin savings.

Implementing the design in a standard
24-pin PlO (exemplified here by the Intel
5C060) is very" costly. The data inputs must
be latched inside a macroce11,using not
only the macroce11 but also the pin. The
divide down toggle flip-flops cannot be
buried, resulting in the loss ofapinfor
each flip-flop. The net utilizatIon for the
5C060 implementation is 12 of 16 macrocells
and 16 of 24 pins,' virtually all of the
device.

In fact, the I/O pin savings is so
significant that, the accompanying address
decode circuitry -- which would be
implemented typically in a 2018 or second
PlO -- can be added to the 5AC312 (Figure
11). The 14 address inputs (A13 - AO),
along with the memory or I/O status signal
(M/IO) are fed into thePlO to generate the
baud rate select data clock signal' (BAUOSEl)
and the 8251 Command/Data (C/O) and Chip
Select (/CS) signals. The net result ;s a
10 of 12 macrocell, 24 of 24 pin,
single-chip solution.

Implementing the same design in the Intel
5AC312 uses a much smaller amount of space.
3-89

BALIJ AI. IE DIVIDER

SElECT

DATA

llfIUTS

00'

___.;. ~rJ.'!"! :----ciBAlOOUT

L~U..::d'::'=-l_ _--.

Figure 11:

:.~

SAC312 Implementation

Programmable Baud Rate Generator
CONCLUSION

Acknowledgements

GATE
AXIS
PLA

Sp!,!cial thanks to David Poisnerof the
Datacomm Focus Group in Folsom, CA and
U. Michael Dunlap and Robert A. Miller
Willamette University in Salem, OR for
use of ,their. designs in this paper.

PLS
22Vl'O
SACS1t

Intel
Prof.
of
the

References
(GATES) .

An Engineeri ng Approach to Di gi j;a 1
Design, William .1. Fletcher, PrenticeHall- Inc .• 1980, pp. 276, 280, 281.
(Provided as an example).

PAL is· a registered trademark of
Monolithic Memories Inc.

Product Term Allocation is an Intel
Patent Pending.

- 4..

Personal System/2 and Mi cro Channe 1
are trademarks of International
Business Machines Corp.

LeA

(FLIP·FLOPS)

Figure 12:

SAC312 Application Areas

Based around a novel programmable
AND/allocatable OR array structure, the
Intel SAC312 is uniquely suited to cover
both highly combinational and complex
seauentialdesigns (Figure 12). The SAC312
is made combinationally powerful through a 0
- 16 product term· allocation arrangement and
sequenti ally powerful through separate
. register and pin feedback and other
features. The SAC312's latched input
capab i1 i ty is an asset i.n both
combinational and sequential applications.
The net result is a combinationally
powerful, sequentially powerful 24-pin
device.

3·90

Ethernet is a trademark of Xerox
Corp .

ESPRESSO is a copyright of the
University of California at Berkeley.

IBM PC/AT is,a registered trademark of
International Business Machines Corp.

ADVANCED ARCHITECTURE PLDs ,SOLVE COMMON
STATE MACHINE PROBLEMS
Liliyas S. Koumis
Technical Marketing Engineer
, Intel
1900 Prairie City Road
Folsom. CA 95630

INTRODUCTION
function of:both the input and the present
state of the machine as shown in Figure 1.
Mathematically; this can be expressed as:

The introduction of programmable logic
devices (PLD) was a true revolution in the
hardware design----t----~~~
LlNP,

SOLUTIONS TO THESE

Cor~MON

~V02

lINP2

PI---+------'

Figure 4:· Architecturally Advanced 5AC312
and 5AC324 Global Block Diagrams
As it can be. seen in Figure 4, the 5AC312
has the architectural features of a Class C
machine but also' offers additional features
address the issues discussed earlier. The
input structure of the 5AC312 offers
several programmable options. each
'addressing a pa~ticu1ar need or problem.
To address the first problem-violation of'
setup and hold times of the output .
registers-the 5AC312 offers an additional
register/latch input with a programmable
clock. The clock can be the same as the
output register clock shifted by 180 0 , a
separate high frequency clock. or be
generated by a product term from the logic
array.

3-93

individual macrocell, ·the eight product
terms are sub-divided into two groups of
four. The oroduct term allocation is
achieved b~ allowing each of these four
product term groups to be borrowed from or
lent to adjacent macrocells. By '.llocating'
product terms between adjacent macrocells,
any. register can be driven by as many as 16
product terms by borrowing unused product
terms.from its neighbors. Conversely, as
little.as zero' product terms can be used if
a microcell lends to both of its neighbors.
The 12 macrocells. in the device have been
divided into· two .groups of six each (or two
groups of 12 for the 5AC324) called the
"rings". that help define ~djacent
macrocells for borrowing and lending
purposes.

~:D---~

Figure 5: 5AC312/5AC324 Input Structure

By using the first clock option.
synchronization is achieved. and thus the'
risk of output glitches is minimized. By
cascading the input and output registers and
shifting the input clock 180 0 from the
output register clock, an additional
advantage is gained by allowing enough time
to satisfy the setup and hold time
requirements of the output registers.
Metastaoility characteristics of the device
is of particular concern and are discussed
later in this paper.
The second uption. a separate high frequency
clock. enables the device to sample inouts
of very short time' duration. This clock
operates UP to 50MHz, with an input
regi ster setup of on 1y 5ns. I f the latch
feature is selected, the setup time is
~educed to Ons.
Of course, a mode can be
selected where the input data flows through,
bypassing the register/latch combination.
The third clock option, clocking the input
registers with the output of a product term
from the logic array. is ideal for
applications where regilters are to be
clocked only when a certain input condition
is met.

Figure~:

ProductTer~

Allocation

The efficiency of 'this configuration t~~ be
demonstrated with ~ .simple example. Assume
an excitation function needs four product
terms and anoiher function neeas10 riroduct
terms. Implementing these fu~ctions ~ith a
fixed eight-product-term PLD requires one
macrocell to implement the four-product-term
function, and two macrocells to implement
the 10 product terms function. To fit the
10 product term function, the equation needs
to be broken into two parts, thereby
increasing the delay. Therefore, out of 24
available oroduct terms (three grouos of

To address the fixed product term orob1e'm,
the 5AC312 implements an i~novative solution
called 'product term allocation.' In each

3-94

eight), 14 are. used (14/24 = 58%
efficiency). Using the 5AC312 to implement
the same functions yields the following:
the four-product~term function is
implemented with half of a macrocell,
allowing the other half to be allocated to
the adjacent macrocell for implementing the
10-product-term function. No
design-splitting is required. Therefore,
out of 16 product terms. 14 are used. This
trans 1ates to 88% product ,term util i zati on.
The product term allocation is completely
transparent to the user since it is achieved
through software. When the compiler
determines that an additi.onal number of
product terms is required, it automatically
allocates resources to fit the required
excitation function.

Additional information on the procedure used
to obtain this data and its use can be found
in references one and three.
CONCLUSION

METASTA8ILITY CHARACTERISTICS
Although metastability is a relatively rare
event, ignoring it can cause serious timing
prob 1ems. 'The input regi sters found in the
5AC312 offer excellent recovery time where
metastability is of concern. Metastability
can be simply described as the inability of
a register to decide the state of its output
within in a fixed amount of time. This event
usually occurs when synchronizing an
external event with a periodic clock. If a
flip flop is clocked nearly at the same time
as 'changing data, there is a small window of
time where the output of the register is
unknown. This window of time is the
recovery time ( e) of the flip-flop and is
typically in the order of nano-seconds.
~~sigr.crs at Intel have performed tests to
:otain the recovery time for the 5AC3xx
family of devices and have concluded that
the Intel devices have better recovery times
than familiar TTL devices such as 74F74.
Tab 1e 1 shows samp 1e data taken at a c.lock
frequency of 2MHz and data frequency of
IMHz·
DEVICE

Recovery Time (ns)
1.6
1.5
0.91
0.70
0.40
0.35

7474
i4LS74
74S374
74F373
74F74
5AC31215AC324
Table 1

3-95

Because of their internal architectural
characteristics Programmable Logic Devices
have become the ideal method to implement
state machine designs. This is evident by
the wide variety of applications 'where
programmable logic devices are found today.
The latest generation of' PLDs, with the
advantages of programmable I/O pins and
expanded number affixed product terms, are
certain to replace traditional off-the-shelf
logic as desingers discover their usefulness
in modern applications. However, to
overcome the oroblems associated with setup
and hold time violations, missed inputs and
fixed number of product terms, a new
generation of PLDs was needed. The Intel
5AC312 and 5AC324 overcome these problems by
providing selectable input register/latch
opti on wi th excellent metastabi.l i ty
characteristics and allocatable product
terms.

* CHMOS is a patented process of Intel
Corporation.

REFERENCES:
1.

Chaney, Thomas J.. "Measured Fl i p-Fl op
Responses to Marginal Triggering,"
IEEE Transaction on Computers. vol.
C-32 No. 12, December 1983.

Fletcher, William I., "An Engineering
Approach to Digital Design",
Prentice-Hall Inc., 1980.

Sto 11, Peter A., "How to Avoi d
Synchronization Problems," VLSI
Design, November/December 1982.

Weigl, Karl H., "Eliminating Cominon
, Problems ln State Machine Designs
Using Innovative PLD Architectures,"
SOUTH CON , December 1987.

Development Support Tools

iPLDS II
THE INTEL PROGRAMMABLE LOGIC
DEVELOPMENT SYSTEM VERSION II
Supports a Variety of Input Methods:
• Schematic
Entry

Hardware and Software Necessary to
• Turn
Design Concepts into Functional
Erasable Programmable Logic Devices
(EPLDs)

- TTL Library
- EPLD Primitives Library
Text Editor Entry
- State Machine
- Boolean Equations

III Menu-driven Software with On-line Help

Messages for All Stages of the Design
Process
Hardware Programs Intel
• iUP-PC
EPLD's, EPROM's, E2PROM's,

Expander Accepts TTL, and
• Macro
User-Defined Macros and Expands
Them into Equivalent EPLD Primitives
Minimizer Reduces Logic
• Espresso·'
Equations to Least Number of Product
Terms
Supports All Intel EPI..D's Including the.
• 5AC312, 5AC324, and 85C508

Peripherals, and Microcontrollers with
one PC-based System
All Equipment Interfaces with the IBM
PC/XT*, PC/AT*, and True Compatibles

•
Standard Design File, Part
• JEDEC
Utilization Report, Minimized Equation
File, and Compiler Error File All
Available as Outputs

Release 2.0 of Intel's Programmable Logic Development System II (iPLDSII) is a powerful set of tools for
transforming a logic design into customized silicon. The system provides design entry, logic compilation, and
device programming capability on a desktop using an IBM PC/XT, PC/AT, or compatible.

290134-1

iPLDS II Components Picture
'IBM PC/XT, PCI AT are registered trademarks of International Business Machines Corporation.
"ESPRESSO is a copyrighted

by the University of California at Berkeley and is used with permission.
4-1

October 1988
Order Number: 290134-004

intJ

iPLDS II

INTRODUCTION TO PROGRAMMABLE
LOGIC DESIGN

.FUNCTIONAL DESCRIPTION OF
iPLDS II
All of the design entry methods with the exception of
graphic state machine entry are supported by the
iPLDS II software. iPLDS II supports netlist and Boolean equation entry using any standard text editor.
State machine software and schematic capture libraries are also available from Intel as optional entry
methods. Depending on the entry format used, the
design may require translation into Advanced Design File (ADF) format. Once the design is in ADF
form, the Logic. Optimizing Compiler expands any
macros, minimizes all equations, and fits the design
into a device-specific JEDEC Design File. The
JEDEC Design File is programmed into the EPLD by
the Logic Programmer Software using the iUP-PC
hardware. Thus, the circuit design is transformed
into an operating EPLD on one workstation.

When performing a programmable logic design on a
CAD system, the design must first be entered using
one of a variety of entry methods. These methods
typically include schematic capture or Boolean
equation entry using a standard text editor. Less typical entry methods include netlist entry, whereby a
hand drawn schematic can be entered in a node-bynode fashion, or state machine entry in a text or
graphical mode.
Once the design has been entered into the CAD
package, several processing steps may occur. The
design is usually translated into a format usable by
the software, . logic reduction may be performed,
and, finally, some form of programming file can be
produced. Most CAD packages also produce documentation of the minimization and device fitting results, including the final pin assignments.

The Intel Programmable Logic Software II (iPLS II) is
composed of four fUnctional modules: design entry,
netlist conversion, file compilation and device programming.

Once the programming file has been generated, the
design can be transferred into silicon in a programming manner similar to that used for EPROMs.

Design Entry
Design entry is typically accomplished by creating an
ADF using an ASCII text editor, or by using a schematic capture package.

4-2

(
Intel Programmable Logic
Development System II

.LlD

T"
c.)

=a
r-

.......

GENERIC lASE MODULE

"@
290134-2

aID
IiiiiI
IF'

~
~

2.2l
c:g

inter

iPLDSIl

Netlist Conversion

File Compilation

If schematic capture of state machine entry is used,
the design must ,be converted into an ADF format.
The optional SCHEMA II-PLD schematic cap1ure
package is a low-cost way to enter schematic designs. SCHEMA II-PLD supports EPLD primitives
and TTL or user-defined macro symbols. It also outputs directly in ADF -format. SCHEMA II-PLD contains the EPLD Manager, which provides a single
user interface to both SCHEMA II-PLD and iPLS II
software.

File compilation is performed by the LOGIC OPTIMIZING COMPILER. The LOC accepts an ADF and
converts it into an industry standard JEDEC file
'which is used to program the device. As a part of
this' process, the LOC expands TTL macros into
equivalent EPLD logic, minimizes the logic equations
using the Espresso algorithm, and maps the network
and logiq equations into a cell map for the selected
device. The final output of the Loc is a JEDEC Design File. The JEDEC Design File describes the input
design for the designated EPLD in JEDEC standard
'
format.

The P-CADtt and Futurenett systems may be used
to capture EPLD symbols provided the EPLD libraries and ADF convertors are used. State machine entry may be performed via the iSTATE software and a
standard text editor.

For designs using the 5AC312 or 5AC324 iPLS II
R2.0 utilizes proprietary algorithms to efficiently uSEj
the device resources. The improved Fitter in R2.0
optimizes fitting for all devices.

tFuturenet is a registered trademark of FutureNet Corpora- ,
tion.
ttP-CAD is a registered trademark of P-CAD Corporation.

Inl.?l
LUC

Pnlf~t"clfom,:,o.b]

'"' Lu~i(.: 80f I:w.:\n~

Fl
FL

ADF Millirni;:at.lun L.EF--Hl1alysis.

*** I NFU:"LOC-'}-It,:,qi n

F4
F5
F6
F7

FB
F9

ME'~nu

XCONrRUI"
~~>l·cc.uti

Ufl

***INFO-LOC-4 mac.rrJfunctions r-esolved in XCONTROL
***INFD-LOC-ADF c:onvcrtelJ tel LEF: XCQNTROL
:U.t::INFO-LOC-Sum Of Pr"nducts

***

(S.lJ.P)

LEF pr"oduced

INF'O-LOC-LEF r'edul':E:>d
***lNFO'-LOC-LEF "itl.alyzed
*»:::f.INFO-LL1C·-Re~ourf:e dem~~lcJ 'dotcrml ne.·(j
***INFO-LOC-Design fitting complete

***

INFO-L.OC-JEDEC f i 1 e output

LOC cycle

suc:cE~~sful ~

y complet.ed

Would you like to- lFllplemenl anothftr de5:>ign (YIN]?

290134-9

Logic Optimizing Compiler Main Menu

4-4

iPLDS II

Device Programming

A: TTL SCHEMATIC ENTRY

The programming hardware is controlled by the
LOGIC PROGRAMMER SOFTWARE. LPS takes the
JEDEC file produced by the LOC and programs it
into the device. LPS can also read a programmed
device or verify that a device has been programmed
correctly.

SCHEMA II-PLD is an optional software package
that allows EPLD design to be implemented with
standard TTL functions. SCHEMA II-PLD contains a
symbol library that includes common SSI/MSI TTL
symbols. SCHEMA II-PLD also outputs directly in
ADF format. The TTL symbols appear in the ADF in
the form of macro calls. During compilation, iPLS II
automatically expands these calls from its TTL macro library. Thus, with SCHEMA II-PLD, conversion to
EPLD logic primitives is performed automatically in a
manner completely transparent to the user.

The Intel Universal Programmer for the Personal
Computer (iUP-PC) is a versatile programming solution in a PC-based system. Installed in an IBM
PC/XT,PCI AT or compatible host, the iUP.-PC emulates the performance of the standalone INTEL
iUP-200A Universal Programmers. As such, it supports the iUP Generic Universal Programmer Interface (iUP-GUPI). With the appropriate socket adapters for the iUP-GUPI, the iUP-PC supports all Intel
EPLDs. Future EPLDs will be supported by new
GUPI adapters or adapter upgrades. Many other Intel devices-EPROMs, EEPROMs, and microcontrollers-are also supported by the GUPL The iUPPC is controlled by the LPS or the iPPS (Intel PROM
Programmer Software). iPLDS II includes the iUPPC, which contains the iPPS, PCPP programming
card, interconnect cable, and the GUPI base. GUPI
adapters are available separately.
.

Only parts supported by the SCHEMA II-PLD TTL
symbol library and the iPLS II TTL macro definition
library may be used for TTL schematic entry. In most
cases, this won't be a· limitation as the most common parts are included in both libraries. Parts not in
the macro libraries may be created by the user and
stored in proprietary user libraries. SCHEMA II-PLD
also supports creating of user-defined macro symbols. The iPLS II Macro Librarian supports creation
of iPLS II macro libraries.
B. SCHEMATIC ENTRY WITH
INTEL SYMBOL LIBRARY
If the user prefers designing with EPLD logic primitives but still wants to use schematic entry,
SCHEMA II-PLD, in addition to supporting TTL schematic capture, also· supports design using EPLD
primitive symbols. Users can enter their deSign and
have both a schematic drawing and an ADF version
of the design. The logic symbols are loaded from the
Intel library and connected in the usual manner. For
quicker use of EPLD primitives, a second library,
EPLDMAC.LlB is available for use. Optional symbol
libraries are also available for PC-CAPS' by P-CAD
Corporation and DASH-2, -3, -4'* by FutureNet
(iSLlBPCAD, iSLlBFNET). The iSIMLIB optional library is available for simulating logic designs with PCAD's PC-LOGS logic simulator.

iPLS II SOFTWARE
The Intel Programmable Logic Software II (iPLS II)
has many options and enhancements for implementc
ing a logic design. iPLS II accommodates a wide variety of design input methods. Schematics, state machines or Boolean equations may all be used provided the proper formats and convertors are implemented as needed. No matter what method is chosen, the Logic Optimizing Compiler will minimize and
fit the design during compilation. Finally, iPLS II contains the Logic Programmer Software which controls
the iUP-PC programming hardware for all Intel
EPLDs.

'PC-CAPS and PC-LOGS are registered trademarks of
P-CAD Corporation.

I. Design Input

"DASH-2, -3, -4 are registered trademarks of FutureNet
Corporation.

The entire spectrum of design input methods is
available to the logiC designer in iPLS II. Everything
from TTL schematics to Boolean equations are accepted and processed by the LOC.

4-5

intJ

iPLDS II

C. TEXT EDITOR ENTRY

11_ Logic File Compilation

Designers who are familiar with the logic primitives
and the Advanced Design File format can directly
enter ADFs with a standard text editor. The bulk of
the design entry can be accomplished using Boolean
Equations obtained from a Karnaugh map or truth
table. Hence, the need for conversion to gates is
eliminated. This method of entry is useful forsub-circuits that will be incorporated into larger designs.

Before programming the part, the designer must
compile the input design file into a JEDEC standard
file. This function is performed by the Logic Optimizing Compiler.
LOGIC OPTIMIZING COMPILER (LOC)
Once the input file is in Advanced Design File (ADF)
format, the LOC will compile it into a device-specific
JEDEC Design File. The first phase of this compilation is performed by the MACRO EXPANDER. The
Macro Expander expands Intel or TTL macros into
equivalent EPLD equations: The second phase is
performed by the ESPRESSO MINIMIZER. The minimizer reduces all the logic equations to their simplest form using the ESPRESSO II-MV algorithm.
The final phase of compilation is performed by the
FITTER. The Fitter creates a cell map of the minimized equations according to the resources availablE) within the specified device.

D. STATE MACHINE ENTRY
In the past, state diagrams or. flowcharts (ASM
charts) were merely abstractions used to obtain the
logic equations necessary to implement TIL designs. With the advent of the iPLS II state machine
convertor (iSTATE), this is no longer the case. Using
an IF THEN / ELSE format, the designer may enter
the state machine description without having .to extract the logic and convert the equations into TTL
components. The state machine to Boolean logic
conversion is handled by the state machine convertor, provided the input file adheres to the specified
State Machine File (SMF) format.

MACRO EXPANDER
The input design file is initially passed through the
MACRO EXPANDER. The Macro Expander
searches the file for any non-EPLD network elements. If found, the Expander then searches the
User Libraries and TTL Library for the unidentified
element. Once the element is located, the design me
element is repla:ced by the equivalent EPLD primitive
implementation found in the library. Having the Expander search the User Libraries allows the user to
create his own macros. User macro files are created
with a standard ASCII text editor and are stored in
libraries by the iPLS II Macro Librarian.

Summary of Optional Entry Requirements:
TTL Schematic Cat:'ture
1. TTL Macro Library
2. EPLD Custom Macro Library
3. SCHEMA II-PLD
PC-CAPS
1. Intel Library used to design logic circuit
2. Component List Output

ESPRESSO MINIMIZER·

3. PCAD convertor used in LOC
(Library and convertor contained in iSLlBPCAD)

The minimization in the LOC is performed by the
ESPRESSO II-MV MINIMIZER. Developed by the
University of California at Berkeley, the ESPRESSO
II-MV algorithm is regarded by many as being the
best minimization method available. ESPRESSO 11MV uses DeMorgan's and other logic theorems to
reduce the equations. to the .Ieast number of product
terms possible. Since product terms are the key variable in the EPLD architecture, the ESPRESSO II-MV
Minimizer provides the simplest equations possible.
As a result, the success rate for fitting large designs
is dramatically increased.

DASH-2, -3, -4
1. Intel Library used to design logic circuit
2. Pin List Output
3. FutureNet convertor used·in LOC
(Library and convertor contained in iSLlBFNET)

State Machines
1. State Machine File (SMF) format used
2. Optional state machine convertor used in LOC
(Convertor contained in iSTATE)

FITTER
The FITTER examines the architecture of the specified device, then tries to map the minimized equations into the resources available. The Fitter automatically assigns pins unless pin assignments are

4-6

intJ·

iPLDS II

already specified in the design input file. The fitting
sequence continues until a successful fit is accomplished or all possible implementations are exhausted. Release 2.0 of iPLS II includes a new, faster
Fitter.that supports PGA packages and the 5AC312,
5AC324, and 85C508. Also included in this new Fitter is the capability to allocate p-terms to adjacent
macrocells for devices such as the 5AC312 and
5AC324 that support p-term allocation.
OUTPUT FILES

JEDEC Design File
A properly designed circuit results in the desired
file from the LaC-the JEDEC Design File. The
JEDEC Design File is a device-tailored EPROM
cell programming map expressed in JEDEC standard format.

Resource Utilization Report
The Resource Utilization Report gives an indepth view ·of what was used inside the EPLD.
Items such as device pinout, macrocell usage,
and feedback arrangements are all listed. Unused resources are also listed to aid the user· in
adding logic or merging EPLD designs.

LOGIC PROGRAMMER SOFTWARE

To program a device with the LPS, the user enters
the file name and device to be programmed. The
LPS checks if the device is blank, programs the device, then verifies that the device was programmed
correctly. As a part of the Intel EPLD Programming
Algorithm, each programmed cell is checked. Adding the complete device check after programming
gives double verification that the part has been sUc.. cessfully programmed.
It is also· PQssibh3 to read a pre-programmed device
. and program other devices with the program read.
The JEDEC Editor in LPS provides a hierarchical
view of the device from the pin level, to the macro~
cell level, to the product term level. At the product
term level, individual EPROM cells may be set or
reset to connect or disconnect the logic equation
inputs.
If the user does not want an EPLD to be read, the
Security bit may be set when rU\1ning the .LPS. The
Security Bit prevents a device from being examined
after it has been programmed. This function is useful
for protecting confidential designs.

Logic Equation File
The LEF file lists the logic equations after they
have passed through the minimizer. It is these
equations that are actually implemented in the
final design.
.

iUP-PC HARDWARE

The Intel Universal Programmer for the Personal
Computer consists of the PCPP programming card,
50-lead interconnect cable, GUPI base and GUPI.
adapter. Together'they form. a system for programming most. PROM-type Intel devices directly from
·the PC host.'

-:- Compiler Error File
.
If a logic circuit is incorrectly designed, messages are produced by the LaC denoting the er, rors. To assist the redesign, these errors are
placed into the Compiler Error File for later reference.

PCPP

The Personal Computer Personal Programmer
(PCPP) is the programmer interface. card that fits
Once a design is successfully implemented, the LaC
. into the IBM AT/XT or true compatible. It is capable
. of driving both the iUP-GUPI base and the iUPcan merge it with other designs by simultaneously
running the two ADF's. In this manner, LSI circuits
FAST27K personality module. The PCPP emulates
can be broken into manageable chunks that can be . the performance of the Intel iUP~200A. TheLPS or
iPPS (Intel PROM Programmer Software) controls
implemented arid tested individually. After each por,the PCPP, causing the programming. card to gener~
tion is completed, the subcircuits can be merged into
ate the control signals for the GUPI base.
one ADF to implement the total design.
FILE MERGINq

GUPIBASE

III. Device Programming

The GenericUniv'ersal Programmer Interface (GUPI)
is used for all p~ogrammable logic support. As all

After the design has been successfully entered, minimized and fitted, the designer programs his part using the JEDEC file produced by the LaC. Programming is accomplished by running the Logic Programmer Software.

4-7

intJ

iPLDS II

,------,
,

'-, ..........
I

- ......

--.
.. I

1
1
1
1
1

I
I

IUP - GUPI ADAPTER

-----------------,
.----------------------.
•
1
1

•

PCPP
PROGRAMMING CARD

1
1

I:1!"~§~~~~ii!I"-I

----_ .. ..., :
,'-----.--------~-------------.
OF
(SIDE VIEW

INTERCONNECT CABLE

P.C. HOST)

IUP - GUPI BASE MODULE
290134-7

The Intel Universal Programmer for the, Personal Computer (iUP-PC)
'

signal generation to devices is done by the GUPI,
the programming waveforms are extremely reliable.
Using the GUPI also allows upgrading for future devices with the simple addition ofa plug-in adaptor.
Future Intel EPLDs will be supported by the GUPI
system.

vice description data for,afamily of similar devices.
New devices will be supported by new adapters or
by upgrades toexistin~ adapters:
'

GUPI' ADAPTERS

Host System

Table 1 details 'the GUPI adapters required for the
logic devices. The adapters available for' programming EPROM's, E2PROM's and microcontrollers
can be found in the data sheet for the iUP-PC (Intel
order number 290130). The adapters contain the de~

The iPLDS II software requires an IBM PC/XT,
PCI AT or other true compatible computer capable
of running MS-DOS· version 3.0 or later. The computer must have a 360KB double-sided, do,uble-density diskdrive; a hard disk, and 512KB of RAM. Addi-

SPECIFICATIONS

Table 1. Intel Programmable Logic Development System II Programming Support
Device

Number of
Macrocells'

5C031,EP310

iUP-GUPI
Adapter

Package Type
Supported

GUPI LOGIC-12

20 Pin DIP

5C032,EP320

GUPI LOGIC-12

20 Pin DIP

5C060,EP600

" GUPI LOGIC-liD

24 Pin DIP

5C090,EP900

' GUPI LOGIC-liD

40 Pin DIP

5C121, EP1200

GUPI LOGIC-12

40 Pin DIP

5C180, EP1800

GUPI LOGIC-18

68 Pin PLCC and JLCC

5C180PGA

GUPI'LOGIC-18PGA

68 Pin PGA

(inPLU):8
(# of Ports):5

GUPI LOGIC-BIC

44 Pin PLCC

5AC312

GUPI LOGIC-liD

'24 Pin DIP

5AC324

GUPI40D44J

85C508

,5CBIC

GUPI85EPLD28

(EPXXX Devices from Altera Corp.)
4-8

40-Pin DIP
28-Pin DIP and PLCC

inter

iPLDS II

tional memory is recommended (640K) and is required for the optional schematic capture programs.
A color monitor is recommended, as the color graphics available provide a better representation of the
data than a monochrome display. The PCPP programming card requires one fullcsize card slot in the
host computer. iPLSIl (Intel Programmable Logic
Software) can run on the I!3M PS/2.

GUPI:
Length: 7.0 inches (17.8 cm)
Width: 5.5 inches (1.4 cm)
Height: 1.6 inches (4.1 cm)

Environmental Characteristics

*MS-DOS is a trademark of Microsoft Corporation

Operating Temperature:

Operating Environment

Equipment Supplied

Electrical Characteristics
PCPP: Worst Case Power Consumption at IBM
PC 1/0 Channel
Supply
Voltage
+5V
-12V
+12V

. Voltage
Variance

Personality Max. Current
Drain
Module

+5%, -4% FAST27K
+10%, -'9% FAST27K
+5%, -4°-4 GUPI

10·C to 40·C

Operating Relative Humidity: 85% Maximum

1.898A .
102.9 mA
530mA

HARDWARE
-

PCPP· programming card

Interconnect cable

GUpl base
(GUPI-LOGIC adaptors

purcha~ed

separately)

SOFTWARE

Physical Characteristics
PCPP::
Length: 13.3 inches (33.9 cm)

iPLSIl

iPPS
PLDUTIL

DOCUMENTATION

Height: 3.9 inches (10.0 cm)
INTERCONNECT CABLE: .
50 lead ribbon cable
Length: 3.0 feet (91.4 cm)
Width:

2.43 inches (5.5 cm)

iPLS II User's.Guide-V2.0 (order number 450196)
PCPP User's Guide (order number 168161)

iPLDS II

PLD Utilities:
Functional Simulatory
TTL Macro Library
. EPLD Custom Macro library
Intel .Universal ProgrammeriUP-GUPI
-Generic Universal Programmer
Interface: Generic programmer
base which holds GUPI adaptors
GUPI LOGIC-liD GUPI Adaptor for the 5AC312,
5C060 and 5C090.
.
PLDUTIL

ORDERING INFORMATION
Order Code
iPLDSIl

iPLSIl

iUP-PC

MUB

iSTATE

iSUBFNET

iSUBPCAD

iSIMLIB

Product Description
Intel Programmable Logic Development System II: iPLS
software, iUP-PC, iPLS II User's Guide .
Intel Programmable Logic
Software II: Logic Builder design entry, Logic Optimizing
Compiler, Logic Programmer
Software, iPLS II User's Guide
Intel Universal Programmer
for the Personal Computer:
PCPP programming card, interconnect cable, iUP-GUPI
base, Intel PROM Programming Software PCPP User's
Guide
iPLS II Macro Librarian: Macro
Librarian Software and User's
Guide Supplement for creating user-defined macro libraries.
Intel State Machine Software:
Entry format documentation,
state machine convertor for
LOC
Intel Symbol Library-FutureNet: EPLD symbol library for
FutureNet DASH-2 schematic
capture package, Futurenet
Pinlist convertor for LOC
Intel Symbol Library-PCAD:
EPLD symbol library for PCAD
PC-CAPS schematic capture
package, PCAD Component
List convertor for LOC
Intel Simulation Library (PCLOGS): EPLD simulation library for PC-LOGS simulator
by PCAD

GUPI Adaptor for the 5C031 ,
5C032, 5C121 and future 20 DIP
EPLDs
, GUPI-LOGIC-18 GUPI Adaptor for the 5C180 and
future 68 pin PLCC and JLCC
EPLDs
GUPI Adaptor for the 5C180 deGUPI LOGIC18PGA
.
vice in a 68 pin PGA package.
GUPI-LOGIC-BIC GUPI Adaptor for the 5CBIC and
follow-on products
GUPI40D44J
GUPI Adaptor for the 5AC324;
includes 40-pin DIP and 44-pin
JLCC sockets.
GUPI85.EPLD28 GUPI Adaptor for the 85C508; includes 28-pin DIP and JLCC
sockets.
Adapts 24 pin DIP socket to 28
ADAPT24T028
pin PLCC socket; for use with
GUPI LOGIC-09 and GUPI
LOGIC-liD.
ADAPT40T044
Adapts 40 pin DIP socket to 44
pin PLCC socket; for use with
GUPI LOGIC-09 and GUPI
LOGIC-liD.
GUPI LOGIC-12

4-10

iUP-PC
INTEL UNIVERSAL PROGRAMMER
FOR THE PERSONAL COMPUTER
•

Personal Computer Version of the iUP200A/201A Universal Programmers

•

Easily Upgradable for new Devices
Through Low-Cost Plug-In Adapters

•

Runs on an IBM PC/AT', PC/XT* or
True Compatible

•

GUPI and FAST27K Personality
Modules Provide Support for Numerous
Device Families

Extremely Versatile-Programs Intel or
Intel-Compatible EPROM, E2PROMs,
EPLDs, Peripherals and MicroControllers, Including the Latest Intel
EPLDs

•

Utilizes the inteligentTM and QuickPulse Programming™ Algorithms

The Intel Universal Programmer for the Personai' Computer, iUP-PC, provides a high performance programming solution from a PC host. Through plug-in adapters for the Generic Universal Programmer Interface (iUPGUPI), the iUP-PC supports all Intel EPLDs and most other Intel programmable devices. Upgrades for new
devices are made by the simple addition of a GUPI adapter or the upgrade of an existing adapter.

290130-1

NOTE:
GUPI Adapter NOT included.
"IBM PC/AT and PC/XT are registered trademarks of International Business Machines Corporation.

4-11

October 1988
Order Number: 290130-003

intJ

iUP-PC

the programming base which holds the device
adapters.

FUNCTIONAL DESCRIPTION·
The iUP-PC provides a fast, versatile and reliable
programming solution from a Personal Computer
host. Downloading to a stand-alone programmer or
moving from one workstation to another is no longer
required. With the iUP-PC, the designer may do his
development and programming on one workstation.
Through the Generic Universal Programmer Interface (iUP-GUPI), the iUP-PC is made. extremely versatile. With the ,iUP-GUPI the designer may program
across EPROM, E2PROM, Microcontroller, Peripheral and EPLD device· categories with the mere
change of a plug in adapter. No other hardware or
software addition is needed. As all of the programming signals are generated at the GUPI base, extremely reliable waveforms reach the device.

GUPI Adapters·..;...The GUPI Adapters plug-in to the
iUP-GUPI base. They carry the sockets and hardware for a particular device family.
iPPS-The Intel PROM Programmer Software (iPPS)
runs on a personal computer under DOS and controls the PCPP/host communication.

·NOTE:
Though the iUP-GUPI base is inclIJded in the iUPPC package, the GUPI Adapters are NOT included.
The desired adapters must be ordered separately.

PCPP CARD
The PCPP is an BOB5-based co-processor board.
Communication between' the host and the PCPP
may be controlled by the iPPS or LPS (Logic Programmer Software). Version 2.3 or greater of iPPS is
required for running the, iUP-PC on a personal computer. LPS is the programming softwlire included in
Intel's Programmable Logic Software II (iPLS II).

COMPONENTS·
The iUP-PC programming system consists of five
components:
.
PCPP-The Personal Computer Personal Programmer (PCPP) is an IBM PC/Xl form factor expansion
card which fits into an IBM PC/XT, PC/AT or true,
compatible.
'

The PCPP is capable of driving the iUP-GUPI and
FAST27/K modules. Future Intel EPLDs will be supported by' ari iUP-GUPI adapter or adapter upgrade.

Interconnect Cable-A 50 lead ribbon cable connects the PCPP to the iUP-GUPI,'
iUP-GUPI-The Intel Universal Programmer-Gerieric Universal Programmer Interface (iUP-GUPI) is

,------

....

', . ........
I
I
I
I

.........
......
...
,

I
I

,
,

I
I
I

,
,
,

IUP - GUPI ADAPTER

-----------------,
,.----------------------.
~-----------,

:
:
........... ", :

pCPP
I!",~§5l~~~§iiii. . .~
PROGRAMMING CARD Ii

1 _____ -

~------- ___ - - - - - - - - - - - - .

INTERCONNECT CABLE

(SIDE VIEW OF P.C. HOST)

IUP - GUPI BASE MODULE
290130-2

Figure

The Intel Universal Programmer for the Personal Computer (iUP-PC)

4-12

inter

iUP-PC

iUP-GUPI MODULE

GUPIADAPTERS

The iUP-GUPI is a generic base module that enables
the iUP-PC system to accept low-cost plug-in adapters. These adapters configure the system to support
a wide variety of programmable devices-EPROMs,
micro controllers, and EPLDs-as well as device
package types.

The iUP-GUPI adapters provide the final link of the
iUP-PC programming system. The adapters provide
the proper sockets and characteristic information for
families of Intel devices.
The iUP-GUPI LOGIC adapters complete the programming solution of the Intel Programmable Logic
Development System II (iPLDS II). The GUPI LOGIC
adapters provide support for the entire range of
Erasable Programmable Logic Devices (EPLDs).
The adapters support families EPLDs with similar architecture, such as the 5C060 and 5C090. All future
EPLDs will be supported by the GUPI LOGIC adapter system.

The iUP-GUPI module connects to the PCPP card
via a ribbon cable. An opening in the top of the iUPGUPI provides easy plug-in installation of the GUPI
adapters (refer to Figure 2).
The iUP-GUPI offers the programming performance
of earlier Intel personality modules, with the fastest
Intel programming algorithms for each device type.
For example, the iUP-GUPI uses the new QuickPulse Programming algorithm to program the 1-Meg
EPROM in seconds.

Intel's one megabit EPROMs are also supported
with GUPI adapters. Adapters are available for the
27010, 27011, and 27210. The page mode of the
27011 is supported by the GUPI 27011 adapter. Other Intel' EPROM support is provided with the
FAST27/K personality module.
Intel's first flash memory products are supported by
the GUPI FLASH Adapter.
The MCS-51 and MCS-96 microcontroller families
are supported by the GUPI MSC-51 and GUPI 8796
adapters. Supplemental adapters provide support
for the variety of microcontroller package types. The
8741 and 8742 peripheral components are supported by the GUPI 8742 adapter.
Table 1 displays a cross-reference of the EPLD
GUPI adapters and the devices they support. Table
2 displays a cross-reference of the EPROM/Microcontroller adapters and the devices they support.
Note that these tables are current at the time of'
printing. Contact your Intel sales representative for
information on current support.

iUp·GUPl
GENERIC BASE MODULE
290130-3

Figure 2. GUPI Adapter Installation

Table 1. EPLD GUPI Module Adapters
Device
Type

GUPI
Logic-liD

EPLD

GUPI
Logic-12

GUPI
40D44J

GUPI
Logic-18

GUPI
-Logic-18PGA

GUPI
85EPLD28

GUPI
Logic-BIC

5C031
5C032
5C060
5C090
5C121
5C180
5C180G
5CBIC
5AC312
5AC324
85C508

Package
Types

DIP'

DIP

DIP
PLCC

PLCC
CJ

'ADAPT umts available to adapt DIP socket for PLCC package.

4-13

PGA

DIP
PLCC

PLCC

Device
Type
EPROM

GUPI
27010

GUPI
27011

GUPI
27210

27011

27210

GUPI·
FLASH

GUPI
8742

GUPI _
··8796

GUPI
MCS-S1

GUPI
8796LCC

:GUPI
87C51GB

27010
. ....

...

27F6~

Flash

•

27F256
28F256
Peripheral

_.
;

8741AH
; 8742AH

Microcontroller

cr
iii
!"
m

8751H
,87C51
8752BH
87G51FA
87C51FB

"CJ
:D

3:
.....
·8794BH.
8795BH
8796BH
8797BH

-t"
....

§
:::s

·8796BH
8797BH

87C51GB
. 8797BH
87C196KB
Package Types

GUPI;
MCS-96LCC

DIP

DIp·

. DIP

PLCC
DIP

PGA
DIP

LeC

PLCC

PLCC
-- -

----

-...9.
iii
C)

:!!
3:

c
iii

1iii

2:
'P
"G

()

inter

iUP-PC

Low cost, plug-in upgrade kits allow addition of support for Intel's latest EPROMs. The first upgrade kit
added support for the 27512 and innovative pageprogrammable 27513 plus the 27128A and 2817 A. It
has now been replaced by a second upgrade kit,
iUP-Fast 27/K-U2 adding support for Intel's new
CMOS EPROMs. (refer to Table 3).

. The iUP-Fast 27/K Personality Module
With the iUP-Fast 27/K personality module the user
can program, read, and verify the contents of Intel's
high density EPROMs, from the page-programmable
(512K) 27513, to the CMOS 27C64, 27C256, and
87C64 EPROMs. This personality module supports
the inteligent Programming algorithms and the
inteligent IdentifierTM. The inteligent Identifier lets
the personality module interrogate the PROM device
in the program/master socket. It determines whether the type selected matches the type of PROM device installed and then selects the proper inteligent
Programming algorithm. The inteligent Programming
algorithms reduce programming time up to a factor
of 10.

As shown in Figure 3 the iUP-Fast 27/K personality
module contains two 28-pin sockets, a hexadecimal
display (0 through F), and a red LED that indicates
when power is being applied to a socket. The program socket holds the device being programmed.
The master socket will be used in future upgrades.

0-2764
2764A
1 [ 27C64
87C64
2-27128
3-27128A
4 {27256
27C256
5-27512
6-27513
7-2817A
8-27916

PIN 1 ---l1-4~--+tI=H-lI=m

PROM
OEVICE
TYPE
HEXADECIMAL
DISPLAY

SOCKIT_~~=======:~~======~====~:::=~-LJ
'--_ _ _---.;:::,...._ LOCKING

POWER
INDICATOR

ARMS

Figure 3. iUP-Fast 27/K Personality Module with U2 Upgrade

4-15

290130-4

intJ

iUP-PC

The hexadecimal display shows the PROM device
type selected.
Table 3. FAST27/K Module Device Support
Prom
Type

Fast·
27/K
Module

Fast
27/KU2
Kit

. Fast
27/K-CON*
Kit

.2764
2764A

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513

2817A

The iPPS software supports data manipulation in the
following Intel formats: 8080 hexadecimal ASCII,
8080 .absolute object, 8086 hexadecimal ASCII,
8086 absolute object, 80286 absolute object, and
80386 bootloadable object Addresses and data can
be displayed in binary, octal, decimal, or hexadecimal. The user· can. easily change default data formats as well as number bases.

EPROM

27128
27256

E2PROM

iUP-PC SPECIFICATIONS
HOST SYSTEM
The iPPS will run on an IBM PC/XT, PC/AT or other
true compatible with a DOS operating system. The
PCPP requires one full-sized card slot inside the PC.

OPERATING ENVIRONMENT

'Uses Quick-Pulse Programming Algorithm.

Electrical Characteristics

iPPS SOFTWARE

PCPP:

The iPPS software, included with the iUP-PC brings
increased flexibility to PROM programming. The
iPPS software provides user control through an
easy-to-use interactive interface and performs the
following functions to make programming quick and
easy:

Supply
Voltage

•
•
•
•

Reads PROMs, ROMs and EPLDs.
Programs PROMs directly or,from a file.
Verifies PROM data with buffer data.
Prints PROM buffer, or device file contents on the
system printer.
.

• Performs interactive formatting operations such
as interleaving, nibble swapping, bit reversal, and
block nioves.
..
.
• Programs multiplePRo.Ms from the source file,
prompting the user to insert new PROMs.
• Uses a buffer to change PROM contents.
With the iPPS software the user can load programs
from system memory or directly from a disk file. Access to the disk lets the user create and manipulate
data in a virtual buffer. This block of data can be
formatted into different PROM word sizes for program storage into several different PROM types. In
addition, a program stored in the target PROM, the
system memory, or a system disk file can be interleaved with a second program and entered into a
specific target PROM or PROMs.

Worst Case Power Consumption at
IBM PC I/O Channel
Voltage
Variance

Personality Max. Current
Drain
. Module

+5V

+5%,-4%

FAST27K

1.898A

-12V

+10%, -9%

FAST27K

102.9 mA

+12V

+5%,-4%

GUPI

530mA

.Physical Characteristics
PCPP:·
Length: 13.3 inches (33.9 cm)
Height: 3.9 inches (10.0 cm)
Interconnect Cable:
50 lead ribbon cable
Length: 3.0 feet (91.4 cm)
Width: 2.43 inches (5.5 cm)
iUP-GUPI:
Length: 7.0 inches (17.8cm)
Width: 5.5 inches (1.4 cm) .
Height: 1.6 inches (4.1 cm)

intJ

iUP-PC

Environmental Characteristics
Environmental Class:

Temperature:
Operating
10 to 40 degrees C
Non-Operating -40 to 70 degrees C
Relative Humidity:
Operating
Non-Operating

85% Maximum
95% Maximum

ADAPT24T028

28-Pin PLCC Socket Adapter
for GUPI LOGIC-liD

ADAPT40T044

44-Pin PLCC Socket Adapter
for GUPI LOGIC-liD

piUPGUPI

Generic Universal Programmer
Interface (Sase)

GUPI LOGICIID

GUPI Logic Adapter

GUPI40D44J

GUPI Logic Adapter

GUPI85EPLD28

GUPI Logic Adapter

GUPI LOGIC12

GUPI Logic Adapter

GUPI LOGIC18

GUPI Logic Adapter

DOCUMENTATION

GUPI LOGIC18PGA GUPI Logic Adapter for 5C180
PGA

168161-PCPP User's Guide

GUPI LOGICSIC

GUPI Logic Adapter

GUPI27010

iUP-GUPI EPROM Adapter

GUPI27011

iUP-GUPI EPROM Adapter

GUPI27210

iUP-GUPI EPROM Adapter

GUPI8742

iUP-GUPI Peripheral Adapter

GUPIMCS51

iUP-GUPI Microcontroller
Adapter

GUPI87C51GS

iUP-GUPI Microcontroller
Adapter

GUPI8796

iUP-GUPI Microcontroller
Adapter

GUPI8796LCC

iUP-GUPI Microcontroller
Adapter

166428-iUP-GUPI Module User's Guide
User's Guides for Adaptors, FAST 27/K Modules,
and upgrades included with respective units.

ORDERING INFORMATION
Order Code

Product Description

iUPPC

Universal Programmer for the
Personal Computer: PCPP Programming Card, 50-Lead Interconnect Cable,
iUP-GUPI,
iPPS, PCPP User's Guide

4-17

piUPFAST 27K

EPROM Personality Module

iUPFAST 27KU2

FAST 27/K Upgrade Kit

iUPFAST 27KCON

Adds Quick-Pulse
and device support

iUPFAST 27KIT

Combines piUPFAST 27K and
iUPFAST 27KU2

algorithm

iUP-200A/iUP-201A UNIVERSAL
PROM PROGRAMMERS
MAJOR IUP-200A/iUP-201A FEATURES:

•

Personality Module Plug-Ins Provide
Programming Support for Intel and
Intel-Compatible EPROMs, EPLDs,
Microcontrollers, Flash Memories, and
other Programmable Devices

•

PROM Programming Software (iPPS)
Makes Programming Easy with IBM PC,
XT, AT, and PC Compatibles '

•

Supports Personality Modules and
GUPI Base W/Adaptors

iUP-200A Provides On-Line Operation
with a Built-In Serial RS232 Interface
and Software for a PC Environment

ill iUP-201A Provides Same On-Line
Performance and Adds Keyboard and,
Display for Stand-Alone Use ,
•

iUP-201A Stand~Alone Capability
Includes Device Previewing, Editing,
Duplication, and Download from any
Source Over RS232C Port,

•

Updates and Add-Ons Have Maintained
Even the Earliest iUP-200 and iUP-201
Users at the State-of-Art

The iUP-200A and iUP-201A universal programmers program and verify data in Intel and Intel compatible,
programmable devices. The iUP-200A and iUP-201A universal programmers provide on-line programming and
verification in a growing variety of development 'enVironments using the Intel PROM programming software
(iPPS). In addition, the iUP-201A universal programmer supports off-line, st~nd-alone program editing, duplication, and memory locking. The iUP-200A universal programmer is expandable to an iUP-201A model.

210319-1

4-18

October 1988
Order Number: 210319-005

inter

iUP-200AliUP-201A

• Verifies device data with buffer data

FUNCTIONAL DESCRIPTION

• Locks device memory from unauthorized access
(on devices which support this feature)

The iUP-200A universal programmer operates in online m~de. The iU~-201 A universal programmer operates In both on-line and off-line mode.

• Prints device contents on the network or development system printer
• Performs interactive formatting operations such
as interleaving, nibble swapping, bit reversal, and
block moves

On-Line System Hardware
The iUP-200Aand iUP-201A universal programmers
are free-standing units that, when connected to a
host. compu.ter with at least 64K bytes of memory,
proVide on-line programming and verification of Intel
programmable devices. In addition, the universal
programmer can read the contents of the ROM versions of supported devices.

• Programs multiple devices from the source file
prompting the user to insert new devices
'
• Uses a buffer to change device contents
All iPPS commands, as well as program address and
data information, are entered through the host system ASCII keyboard and displayed on the system
CRT.

The universal programmer communicates with the
host through a standard RS232C serial data link. Different versions of the iUP-200A and iUP-201A are
equipped with different cables, including the cable
most commonly u~ed for interfacing to that host.
Care should be taken that the version with the correct cable for your particular system is selected as
ca~le requir~ments can vary with your host configuration. A senal converter is needed when using the
MDS 800 as a host system. (Serial converters are
available from other manufacturers.)

The iPPS software supports data manipulation in the
following Intel formats: 8080 hexadecimal ASCII,
8080 absolute object, 8086 hexadecimal ASCII
8086 absolute object, and 80286 absolute object:
Addresses and data can be displayed in binary, octal, decimal, or hexadecimal. The user can easily
change default data formats as well as number bases. iPPS can also access disk files.
For programming Intel EPLDs, the iUP-200Al201A
can be controlled by Intel's Logic Programming Software (LPS). LPS programs EPLDs from JEDEC files
produced by Intel's logic compiler. (iPPS can also
program EPLDs, but only from pre-programmed device masters.)

Each universal programmer contains the CPU, seI~ctabl.e power supply, static RAM, programmable
timer, Interface for personality modules, RS232C interface for the host system, and control firmware in
EPROM. The iUP-201A also has a keyboard and display.

System Expansion

A personality module or GUPI Adaptor adapts the
universal programmer to a family of devices· it contains all the hardware and software nece~sary to
program either'a family of Intel devices or a single
Intel device. The user inserts the personality module
into the universal programmer front panel.

The iUP-200A universal programmer can be easily
upgraded (by the user) to an iUP-201A universal programmer for off-line operation. The upgrade kit (iUPPAK-A) is available from Intel or your local Intel distributor.

On-Line System Software

Off-Line System

The iUP-200A and iUP201A includes your choice of
<:lne copy of Intel's PROM Programming software
IPPS, selected from a list of versions for different
operating systems and hosts. Each version includes
the software implementation, designed for that host
and O.S. and the RS232C cable most commonly
used. Additional versions may be purchased separately if you decide to change hosts at a later date.
The iPPS software provides user control through an
easy-to-use interactive interface. The iPPS software
performs the following functions to make EPROM
programming quick and easy:
'

The iUP-201A universal programmer has all the online features of the iUP-200A universal programmer
plus off-line editing, device duplication, program verification, and locking of device memory independent
of the host system. The iUP-201A universal programmer also accepts Intel hexadecimal programs
developed on non-Intel development systems. Just
a few keystrokes download the program into the iUP
RAM for editing and loading into a device.
Off-line commands are entered via a 16-character
keypad. A 24-character display shows programmer
status.

• Reads devices
• Programs devices directly or from a file
4-19

inter

iUP-200A/iUP-20 1A

Adaptors. GUPI Adaptors tailor the GUPI module
base signals to a family of devices or an individual
device. The GUPI module and GUPI Adaptors provide a lower-cost method of device support than if
unique Personality Modules were offered for each
device/family. Tables 2 and 3 show which Adaptors
support which devices.

SYSTEM DIAGNOSTICS
Both the iUP-200A and iUP-201A universal programmers include self-contained system diagnostics that
verify system operation and aid the user in fault isolation.

PERSONALITY MODULES
For some devices, a personality module is the interface between the iUP-200AliUP-201A universal programmer (or an iPDS system) and a selected device.
Personality modules contain all the hardware and
firmware for reading and programming a family of
Intel devices. Table 1 lists the devices supported by
the different modules.
For most devices, the GUPI module and interchangeable GUPI Adaptors provide the interface between the programmer and the device being programmed (see Figure 1). the GUPI (Generic Universal Programmer Interface) module is a base module
that intefaces to the iUP-200A/201A and GUPI

iUP-GUPI
GENERIC BASE MODULE
210319-12

Figure 1. GUPI Adaptor

4-20

intJ

iUP-200AliUP-201A

Table 1. iUP Personality Programming Modules

Device Type

Fast 27/K
Module

Fast 27/K U2
Kit

Fast 271K-CON*
Kit

EPROM

2764
2764A
27128
27256

2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513

F271128
Module

F87144A
Module

F87/51A
Module

8041A
8042
8044AH
8741H
8742
8744H

8748
8748H

2716
2732
2732A
2764

27128

2815
2816

E2PROM

2817A

Microcontroller

8755A
'Quick-Pulse Programming™ algorithm

4-21

8749H
8751
8751H
8048
8048H
8049
8049H
8050H
8051

iUP-200A/iUP-201A

Table 2. iUP-GUPI Adaptors for Programming Memories
Device
Type

GUPI GUPI GUPI GUPI
27010 27011 27210 Flash

EPROM

GUPI
8742

GUPI
MCS-51

GUPI
8796

GUPI
GUPI
GUPI
8796LCC 87C51GB MCS-96LCC

27010
27011 27210

Flash

27F64
27F256
28F256

Peripheral

8741AH
8742AH

Microcontroller

8751H
.87C51
8752BH
87C51FA 8794BH
87C51FB 8795BH
8796BH 8796BH
8797BH 8797BH
87C51GB
8797BH
87C196KB

Package
Types

DIP

PLCC
DIP

PGA
DIP

LCC

PLCC

Table 3. Programming Adaptors for EPLDs
Device
Type

GUPI·
Logic-liD

EPLD

GUPI
Logic-12

GUPI
40D44J

GUPI
Logic-18

GUPI
Logic-18PGA

GUPI
85EPLD28

GUPI
Logic-BIC

5C031
5C032
5C060
5C090
5C121
5C180
5C180G
5CBIC
5AC312
5AC324

,
Package
Types

85C508
DIP'

DIP

DIP
PLCC

PLCC
CJ

• ADAPT units available to adapt DIP socket for PLCC package.

4-22

PGA

DIP
PLCC

PLCC

intJ

iUP-200A/iUP-201A

166043-001- Getting Started with the iUP-200AI
201A (For DOS Users).
-iUP-200AI201A Universal Program164853
mer Pocket Reference.

iUP-200A/iUP201A SPECIFICATIONS
Control Processor
Intel 8085A microprocessor
6.144 MHz clock rate

ORDERING INFORMATION
Product
Order Code
iUP-200A 211A

Memory
RAM-4.3 bytes static
ROM-12K bytes EPROM

iUP-200A 212B

Interfaces
Keyboard: 16-character hexadecimal and 12-funclion keypad (iUP-201 A model only)
Display: 24-character alphanumeric (iUP-201 A
model only)

iUP-200A 213C

Software

iUP-200A 2170

Monitor- system controller in pre-programmed
EPROM
iPPS - Intel PROM programming software on
supplied diskette

iUP-201A 211A

iUP-200A 2160

iUP-201 A 212B

, Physical Characteristics
Depth:
Width:
Height:
Weight:

15 inches (38.1 cm)
15 inches (38.1 cm)
6 inches (15.2 cm)
15 pounds (6.9 kg)

iUP-201 A 213C

iUP-201A 2160

Electrical Characteristics

iUP-201A 2170

Description
On-Line PROM programmer with
iPPS rei 1.4 on Single density ISIS
II floppy
On-Line PROM programmer with
iPPS rei 1.4 on Double density
ISIS II floppy
On-Line PROM programmer with
iPPS rei 2.0 for Series IV, on minifloppy
On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for PC or XT
On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for AT
Off-Line and on-line PROM programmer with iPPS rei 1.4 on Single density ISIS II floppy
Off-Line and on-line PROM programmer with iPPS rei 1.4 on Double density ISIS II floppy
Off-Line and on-line PROM programmer with iPPS rei 2.0 for Series IV on mini-floppy
Off-Line and on-line PROM programmer with iPPS rei 2.0 for PCI
DOS, and cable for PC or XT

Off-Line and on-line PROM programmer with iPPS rei 2.0 for PCI
DOS, and cable for AT
iUP-200/201 U1 * Upgrades an iUP-200/201 univerUpgrade Kit
sal programmer to an iUP-200Al
201A universal programmer
iUP-DL
Download Support Kit for iUP200Al201 A upgrades programmer to support adaptors that use
software programming (.DSS)
files.
iUP-PAK-A
Upgrades an iUP-2001 A universal
Upgrade Kit
programmer to an iUP-201A universal programmer
'Most personality modules can be used only with
an iUP-200Al201 A universal programmer or an
iUP-200/iUP201 universal programmer upgraded to
an A with the iUP-200/iUP-201 U1 upgrade kit.

Selectable 100, 120, 200, or 240 Vac ± 10%; 50-60
Hz
Maximum power consumption-80 watts

Environmental Characteristics
Reading Temperature:
10°C to 40°C
Programming Temperature: 25°C ± 5°
Operating Humidity:
10% to 85% relative
humidity

Reference Material
166041-001- iUP-200A1201A Universal Programmer User's Guide..
166042-001- Getting Started with the iUP-200AI
201A (For ISISliNDX Users).
4-23

intJ

iUP-200AliUP-201A

Product
Order Code
piUP-GUPI

Product
Order
Code
Description

Description

Generic Universal Programmer
terface (Base)

In~

213C
2160

Software Sold Separately

2170

Product
Order
Code
Description

211A
212B

PROM programming software rei 1.4 on
Single density ISIS II floppy
PROM. programming software rei 1.4 on
Double density ISIS II floppy

4-24

PROM programming software rei 2.0 for
Series IV on mini-floppy
PROM programming software rei 2.0 for
PC/DOS with cable for PC or PC XT
PROM programming software rei 2.0 for
PC/DOS with cable for PC AT

SCHEMA II-PLD
SCHEMA /I-PLD is a low-cost schematic capture software for designing with Intel EPLDs and with
standard MSI, SSI, and discrete components. For EPLD designs, SCHEMA /I-PLD outputs Advanced
Design Files (ADFs) that can subsequently be compiled by iPLS II software. Figure 1 shows the flow
to generate a drawing file and convert it to an ADF for processing by iPLS II. SCHEMA II-PLD supports
EPLD design primitive symbols as well as MSI and SSI macro symbols, allowing designers to combine
TTL and EPLD symbols as needed. An EPLD Custom library supports groups of EPLD symbols and
"generic" function symbols such as counter, multiplexers, etc. The ability to create user-defined
symbols that can be translated into ADF macro calls adds to SCHEMA II-PLD's power and versatility.
SCHEMA II-PLD provides fast, smooth panning, combined mouse/keyboard support, instant command execution, and automatic "step and repeat" to make schematic capture as quick and easy as
possible. In addition to the symbol libraries targeted for EPLD design, SCHEMA II-PLD provides over
10 symbol libraries for standard PCB design. Its sophisticated library management routines, reentrant
object editor, and true "hierarchical" design capability makes SCHEMA /I-PLD a powerful tool for
professional designers.
The EPLD Manager software included with SCHEM II-PLD provides a single user interface to both
SCHEMA II-PLD and iPLS II software modules. EPLD Manager software is also available separately
to users who already own SCHEMA /I.
Order Codes:

SCHEMA II-PLD

(SCHEMA II and EPLD Manager)

EPLDMGR

(EPLD Manager)

r------,
1
1

1
1

EPLDMGR
MENU
______

...

r - - - - - - - - - - - -. -

_1- -

1 CAPTURE SCHEMATIC

r---

- -

--.

SCHADF

./
ADF

'-...

INTERFACE
T o iPLS II

-....,

r---

'--

NETLIST TO ADF

DRAWING
FILE

-...."

SCHDRAW

r-+

SYMBOL
LIBRARIES
~ device.LBR

rr-

~
~

TTL.LBR
EPLDMAC.LBR
user.LBR
PCB LIBRARIES (10)

Figure 1. SCHEMA II-PLD Schematic Capture Flow for EPLD Designs

4-25

Fl00139

inter
iPLS II MACRO LIBRARIAN
The iPLS II Macro Librarian (MUB) is a software package that allows designers to build user-defined
macro definition libraries for EPLD designs. Macro libraries can include TTL macros available from
Intel, or proprietary macros developed by a user. User-defined macros are developed as individual
macro files using a text editor, and then are combined into macro libraries by MUB, where they can
be accessed by the LOC. Figure 1 shows the flow to build a macro library. Use of macros in ADFs
(Advanced Design Files) allows EPLD design to proceed at a higher level than with EPLD primitives
alone.
Macro files are standard ASCII files that describe the function of the macro. The Network and Equa- .
tions sections of macro files follow ADF format. The header section, which differs from ADF format,
defines the macro name, calling sequence, and defaults; MUB combines these files into a library that
can be accessed by the macro expander in the LOC (Logic Optimizing Compiler). MUB can be invoked
from the command line, from command files, or from a combination of both. The macro expander
identifies and expands each macro call in an ADF with the corresponding macro definition from macro
libraries. The first occurrence of a macro is used.
Two preconfigured libraries are available from Intel: (1) tTL macro library, and (2) an EPLD Custom
macro Library. These libraries are described in the "PLDUTIL" Product Brief.

Order Code: MUB

r----

COMMAND
FILE

TEXT
EDITOR

'--

I'-..
TEXT
EDITOR

,
--

r
'-.

MACRO
FILES
'-.

MLiB

....-

MACRO
LIBRARY,
'-.

MACRO
LIBRARIES ARE
ACCESSED BY
LOGIC COMPILER

....-

LIBRARY
LISTING
F100138

Figure 1. Flow to Build a Macro Library

4-26

PLDUTIL
PLDUTILV1.0 contains the following utilities for designing with Intel EPLDs:'
• SIM, version 2.1 of a basic Functional Simulator for EPLD designs
• TTL.LlB, version 3.6 of Intel's TTL macro definition library
• EPLDMAC.LlB, version 1.0 of Intel's EPLD custom macro definition library.

Functional Simulator
The Functional Simulator allows designers to perform basic function simulation of EPLD designs. By
verifying proper operation' of a design with the Simulator, designers can catch logic errors before
devices are programmed and installed in products.
Design information is provided by the minimized LEF (Logic Equation File) generated by the iPLS II
logic compiler. Input stimulus for the Simulator is in the form of a user-generated ASCII vector file
containing strings of 1s and Os (see Figure 1). Vector files can also contain expected output values
to serve as a reference for the simulated outputs. The simulator produces state machine or waveform
output and supports bidirectional signals. Output registers can be preloaded to speed the process of
simulating counter and state machine transitions.'
The Functional Simulator operates on any IBM PC/XT, PC/AT, or compatible computer. A.C. timing
simulation is not supported.

STATE TABLE OUTPUT

-......

../

SCREEN
PRINTER
DISK FILE

iPLSIl
LEF

SIM
OUTPUT

SIM

-001-002-003-004-005-006-007-008-

00
01
01
00
00
01
11
01

0010100000101111-

WAVEFORM OUTPUT

-001-002-003c004-005-006-007-008-

r'-TEXT
EDITOR

./
VECTOR
FILE

Figure 1. Functional Simulator Flow

4-27

I
I

~ ~

- ,

- ,
-

TTL Macro Library
The TTL Macro Library contains macro definitions for most common 74-series TTL devices. The
library is accessed by theiPLS II macro expander module when compiling an ADF (Advanced Design
File). When the macro expander identifies a macro call in an ADF, it searches available libraries for
the respective ADF macro definition, and replaces the macro call by the ADF implementation.
Macro definitions implement the TTL functions via EPLD design primitives and Boolean equations.
In some cases, precise TTL emulation is not possible. In addtion to the built TTL macro library, the
TTL.LlB disk contains the individual device files (.DEV) used for each macro, and document files
(.DOC) describing the implementation details for each macro. The device files can be used to build
user7defined macro libraries using the iPLS II Macro Librarian.
TTL.LlB provides the ADF macro definitions for compilation. Macro symbols for use with supported
schematic capture packages are provided with the schematic capture software. A complete listing of
the contents of the TTL macros in the library is provided in Applications Brief AB-18, TTL Macro
Library Listing for EPLD Designs.

EPLD Custom Macro Library
The EPLD Custom Macro Library contains macro definitions for a set of common EPLD primitive
groups and "generic" logic functions. Included in the library are groups of INPs, CONFs, RORFs, etc.
Also included are frequently used counters, multiplexers, decoders, etc. The library is accessed by
the iPLS II macro expander module when compiling an ADF (Advanced Design File). When the macro
expander identifies a macro call in an ADF, it searches available libraries for the respective ADF macro
definition, and replaces the macro call by the ADF implementation.
'
In addition to the built library, the EPLDMAC.LlB disk contains the individual device files (.DEV) used
for each macro, and document files (.DOC) describing the implementation detail~ for each macro.
The device files can be used to build user-defined macro libraries using the iPLS II Macro Librarian.
EPLDMAC.LlB provides the ADF macro definitions for compilation. Macro symbols for use with
supported schematic capture packages are provided with the schematic capture software. A complete
listing of the contents of EPLD Custom Macro Library is provided in Applications Brief AB-21 , EPLD
Custom Macro Library Listing for EPLD Designs. .
Order Code:

PLDUTIL

(Functional Simulator, TTL.LlB, EPLDMAC.LlB and User
Documentation)

4-28

UTILITIES
PAL2ADF UTILITY
Description
This document is a brief note on the use of the PAL2ADF program in translating PALASM 1 files
into Intel's Advanced Design File (ADF) format. Descriptions for actual use can be found on the
. accompanying Manual page in the file PAL2ADF.MAN.
The PALASM file serves as a template for mapping the PALASM equations into ADF. The
translation is performed as follows:
1) Read PAL description, and set the PAL pins to their appropriate EPLD primitive
counterparts
2) Parse file and produce network description
3) Translate equations to ADF

PAL Configuration Database
When it is translating a PALASM file, PAL2ADF reads a database (defaultPAL2ADF.DAT) that
tells it:
• How many pins the PAL has .
• Which default EPLD to translate to
• What pins are special inputs (Clock and Output Enable defaults)
• What EPLD I/O primitives to use for each PAL pin
The EPLD I/O primitives specify the network. architecture that the EPLD must take on in order
to mimic the functionality of the PAL. See the PAL2ADFDAT file for more information.

Reconfiguring Outputs
In step (2) above, several checks are done in order to make. sure that the 'network is configured
appropriately. These primarily involve output pins, although input pins can be specified as well.
The first reconfiguration is for active low outputs in their equations. i.e.,
PALASM: /SIGNAL = A * /8 + C
becomes
ADF: SIGNAL = /(A * /8 + C);
The other reconfigurations are slightly more complex. Consider a PAL pin X which is an output
with a D-Iatch. The output value is f,ed back into the P-term array after the Output Enable. This
is described as a Registered Output Registered Feedback (RORF) in the Intel EPLDs. The default
network description for this pin then is:
NETWORK:
X,X = RORF (Xp,CLK;GND,GND,OE)
where CLK and OE are the default Clock and Output Enable signals.
Normally, there would be an equation that would describe Xp. (The 'p' is used to name the
P-term value.) If, however, the X feedback is never used in an equation, then the I/O macrocell
is reconfigured to a Registered Output No Feedback (RONF).

4-29

NETWORK:

RONF (Xp,CLK,GND,GND,OE)

For those 1/0 pins on the PAL which are used strictly as inputs, these use the Combinatorial
Output 1/0 Feedback (COIF) primitive, with the Output Enable shut off (GND). The P-term is tied
to the feedback, in order to satisfy the semantics of ADF.
NETWORK:
YY,YV

COIF (YYp,GND)

EQUATIONS:
YYp = YY;
If the PAL pin is being used strictly as an output and is never.used in an equation, then the
primitive is reconfigured to a Combinatorial Output No Feedback (CONF).
NETWORK:
YY,YY = COIF (YYp,GND)
This is the same as above where a RORF is reconfigured toa RONF.

Multiple PAL Designs into 1 EPLD
It is possible to incorporate multiple PALASM descriptions into one EPLD. If each PALASM
description is disjoint, (Le., they have different pin names for each pin) then you can simply
translate each file (with the pinlistinformation OFF) and compile them together with the iPLS
Logic Optimizing Compiler (LOC).
The compiler allows you to specify multiple ADF files, allowing different subnetworks within one
EPLD. You will probably want to use a larger EPLDto fit all the designs in.
If the PAL designs are not disjoint, then there are some steps that can be done by hand to
integrate the designs. A simple example would be where one PAL feeds another a signal, and
.
.
the second uses that to generate another signal.

B.PAL1. C - - - C B
PAL2. .
Z

4-30

In this case, C is an output of PAL 1, and an input to PAl2. In PAl2, C,Z, and W generate the
signal X. Suppose we have the equations:
PAl1
/C = A * /8
PAl2
X = /C*Z*W
+ C*/Z·W.
In the resulting ADFs, the following NETWORKS are produced:
ADF for PAL 1 :
NETWORK:
A = INP(A)
8 = INP(8)
C = CONF(Cp,VCC)
EQUATIONS:
C = /(A * /8);
ADF for PAL2:
NETWORK:
Z = INP(Z)
W = INP(W)
C = INP(C)
X,X = RORF(Xp, ClK, GND, GND, OE)
EQUATIONS:
Xp = /C'Z*W
+ C'/Z'W;
These can be joined together into a single ADF:
NETWORK:
A = INP(A)
8 = INP(8)
Z = INP(Z)
W = INP(W)
X,X = RORF (Xp, ClK, GND, GND, OE)
EQUATIONS:
C = /(A • /8);
Xp = /C'Z*W
+ C'/Z'W;
Notice how C is now an intermediate variable rather than an actual signal. This is obviously a
simple example, yet similar techniques can be applied to more complex cases. As much more
logic can be placed into larger EPlDs, the job of splitting functions across multiple devices is
reduced.

Availability
The PAL2ADF utility is available at no cost to Intel EPlD customers. Contact your local Intel
sales office.

4-31

JED'2HEX CONVERSION UTILITY,

.::'

Description
JED2HEX is a utility to convert JEDEC files created byiPLS (.JED) into Intellec HEX files which
can then be read by Intel's iPPS software. This allows programming of EPLDs via Intel's iUP200Al
201A using a GUP I base and the appropriate adaptor (e.g. LOGIC-12). The following diagram
represents a typical development cycle.
. ,':

iPLS

.JED

JED2HEX

·1

.HEX

·0

.TTF
INSTALLATION: To install the utility and its device specific files, place the master disk in drive
A: and invoke the JINSTALL.BAT batch file with the destination path for the utility and device
files. Example:
A: JINSTALL

C: MYPATH

When using JED2HEX, attach the package descriptiqn letter when entering thegevice type.
That is, enter 5C121 D for a 5C121 ceramic DIP when prompted for the device type. Entering
5C121 will result in:
***ERROR: Device File Missing
To determine the packages supported in your JED2HEX software, examine all the .ttt extension
fUes; it is the .ttt files which the device type command attempts to match.
..'
When using iPPS, a file format of 8080 or 8086 must be specified when copying the JED2HEX
generated HEX file to the buffer or directly into a device. If 8080 or 8086 is not specified, the
default fUe format type of 80386 will be chosen and a "GENERAL ERROR - ILLEGAL FILE
TYPE SPECIFIED" will result. An example of the proper COPY format:
PPS> COpy a: filename. HEX TO PROM 86 ..
.

Availability
The JED2HEX Conversion Utility is available at no cost to Intel EPLD Customers. Contact your
local Intel sales office.
. !.

4-32

'1.

intJ

APPLICATION
BRIEF

AB-18

October 1988

TTL Macro Library Listing'
for EPLD Designs

PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292037-003
.

4-33

inter

AB-18

TTL Macros

MSI FUNCTIONS

The following is a list of TTL macros that are in
TTL.LIB version 3.6. This libraty is available through
the Intel EPLD customer hot line.

Decoders/Demultiplexers
7442
7444
7447X

These macros are called from an Advanced Design File
(ADF). Schematic capture packages such as Schema 11PLD create ADFs with the correct macro invocation
for each TTL device listed here.

7449
Macros listed here are grouped by general function.
74138
74139
74145
74154
74155
74156

SSIGATES
7400
7402
7404
7408
7410
7411
7420
7421
7427
7430
7432
7486

2 Input
2 Input
1 Input
2 Input
3 Input
3 Input
4 Input
4 Input
3 Input
8 Input
2 Input
2 Input

NAND
NOR
INVERTER
AND
NAND
AND
NAND
AND
NOR
NAND
OR
XOR

(10) BCD to Decimal
(10) Excess-3-Gray to Decimal
(7) BCD to 7-Segment-Active Low Output
(7) BCD to 7-Segment-Active High
Output
(8) l-of-8 Decoder
(4) Single l-of-4 Decoder
(10) BCD to Decimal
(16) l-of-16 Decoder
(8) Dual l-of-4
(8) Dual l-of-4

Multiplexers

4-34

74151
74153.
74157
74158
74253
74257X

(2)
(2)
(4)
(4)
(2)
(4)

74258X

(4)

74298XA

(4)

74298XB

(4)

74352

(2)

8-to-l
Dual 4-to-l-Active High Output
Quad 2-to-l-Active High Output
Quad 2-to-I-Active Low Output
DuaI4-to-l-Three-State Output
Quad 2-to-I-Active High, ThreeState Output
Quad 2-to-l-Active Low, ThreeState Output
Quad 2-io-l-Active High with Storage
Quad 2-to-l-Active High with Storage
Dual 4-to-l-Active Low Output

inter

AB-18

Counters
7490XD
7490XQ
74160
74161
74162
74163
74168
74169
74176XD
74176XQ
74177X
74190XA
74190XB
74191XA
74290XD
74290XQ
74390X
74393XA
74393XB
S
A
9

(4)
(4)
·(5)
(5)
(5)
(5)
(5)
(5)
(4)
(4)
(4)
(6)
(6)
(7)
(4)
(4)
(4)
(4)
(4)

Type
BCD Decade
Bi-Quinary
BCD Decade
4-Bit Binary
BCD Decade
4-Bit Binary
BCD Decade
4-Bit Binary
BCD Decade
Bi-Quinary
4-Bit Binary
BCD Decade
BCD Decade
4-Bit Binary
BCD Decade
Bi-Quinary'
Bi-QuinatYfBCD
4-Bit Binary
4-Bit Binary

= Synchronous
= Asynchronous
= Synchronous Set-to-9

U/D
RCO
MM

=
=
=

Clear

Load
9
9

S
S

S
S
S
S
S
S
S
S
S
S
S
S

A
A

S
S

A
A
A

S
S

9
9

R
F

RCa
RCa
RCa
RCa
UfD,RCO
UfO, RCa

UlD,RCO,MM
UfD, RCa, MM
UfD, RCa, MM

= Rising-Edge Triggered
= Falling-Edge Triggered

Up/Down
Ripple Carry Output
Max/Min Output

7472XA
7472XB
7473X
7474X
74112XA
74112XB

Latches

(2) AND-Gated JK Master/Slave
(2) AND-Gated JK Master/Slave
(2) JK with Clear
(2)D with Preset and Clear
(3) JK with Preset and Clear
(2) JK with Clear

7475X
7477X
74259XA
74259XB
74373X

Multiple Flip-Flops (Registers)
74174X
74175X
74273X
74378

Extras

F
F
F

A
A
A

Single Flip-Flops

74377

Clk
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

(6)
(8)
(8)
(8)
(6)

Hex D
Quad D with Q and /Q
Octal D
Octal D with Common Enable
Hex D

4-35

(8)
(4)
(8)
(8)
(8)

4-Bit Bistable
Quad D-Type
Octal Addressable D-Type
Octal Addressable D-Type
Octal D-Type

AB·18

Shift Registers
7491
7495XA
7495XB
7495XC
7496X
74164
74165X

(8) 8-Bit-Serial-In, SeriaI-Out
(4) 4-Bit-Serial-InlParailel-In,
Parallel-Out
(4) 4-Bit-S~rial-InlPai-iillel-In,
Parallel-Oui'
(4) 4-Bit-SeriaJ~InlParallel-In,
Parallel-Out
(5) 5-Bit-,-Serial~In/Parallel-In,
Parallel-Out
.
(8) 8-Bit-Serial-In,
Parallel-Out
(9).8-Bit-Serial-In/Parallel-In,
Serial ~Out .
.. '

74194
74395XA
74395XB

,',

(4). 4-Bit Bi-Directional-,Serial-IniParailel-In, Parallel-Out
(5) 4-Bit CascadableSerial-IniParailel-In,. Parallel-Out
(5) 4-Bit Cascadable- ..'
Serial-In/Parallel-In" Parallel-Out

Miscellaneous
7482X
7483X
7485X
7487
74143X
74180X
74180XA
74182
74183
74280X

(4)
(8)
(7)
(4)
(17)

2-Bit Adder
4-Bit Adder
4-Bit Magnitude Comparator
4-Bit True/Complement Element
4-Bit Counter; 4-Bit Latch; 7 Seginent
Decoder
'"
(4) 8-Bit Parity Qenerlitor.(Checker
.(4) . 8-11itParity. Gen~rato~/Checker:
(5) L09k"Ah~d Carry Generator
(2) Single-Bit Full Adder
with Carry/Save
(5) 9-Bit Odd/Even Parity Generator/
Checker

DE MORGAN EQUIVALENTS
(BUBBLE GATES)
Bubble
2 Input
Sinput
4 Input
Sinput
Sinput
12 Input

AND
(NOR)
BAND2
BANDS
BAND4
BANDS
BAND8
BAND12

Bubble

. Bubble

Bubble

, NOR
NAND.
'OR
(OR)
·.(AND) (NAND)
BNAND2 EiNOR 2 ,BOR2
BNANDS ' BNORS BORS
BNAND4 BNOR4 BOR4
BNAND6 BNORS BORS
SNAND8 SNORS BORS
BNAND12 BNOR12 BOR12

INPUTIOUTPUT MACROS
INPUT

N/A Generates Input Pin. and. Node in
ADF
OUTPUT (1) Generates Enabled Output Buffer in
ADF
."
.OUTP.
74125.·
:74126

(1) Output Pi~(Used in SCHEMA 11PLD)
(1) Single Three-State Output, Active
Low Enable
(1) Single Three-State Outp~t, Active
High Enable
NOTES:

1. All TTL macros duplicate TTL function only. They

DO NOT DUPLICATE performance characteristics
such as open-collector, totem-pole, or high-drive out. . .
put.'
2. Any TTL macros which deviate in some way from
standard TTL function' are denoted with. an appended
"X" (see device .DOC· file for details). Appended
"D"s and "Q"s' indicate counters configured to Decimal or bi-Quinary mode; appended "A"s and "B"s indicate a macro configured for a. family of EPLD de. ..
vices (e.g. 5C060, 5C090, 5CI80).
3. The (#) indicates the maxhD.um number of EPLD
macrocells consumed if all' outputs are used. If an output is not used, the macro compression phase of the
Macro Expander will remove the signal ~less it is
used as feedback inside the' macro defmition.
4. /Q's should be avoided' as pin outputs if possible.
The EPLD is structured such ,that the. Q is readily
available as a pin output and both the Q and /Q are
readily available as feedbacks. Using /Q as a pin output, however, requires an extra macrocell and adds to
the propagation delay.
. .

inter

AB-21

APPLICATION
BRIEF

October 1988

EPLD Custom Macro Library
Listing for EPLD Designs

•

PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION·

Order Number: 292050-001

4-.37

AB-21

EPLD CUSTOM MACROS
The following is a list of the macros contained in version 1.0 of Intel's EPLD Custom Macro Library
(EPLDMAC.LIB). This library is available through the Intel EPLD customer hot line.
These macros are called from an Advanced Design File (ADF). Schematic capture packages such as SCHEMA 11PLD create an ADF with the correct macro invocation syntax for each macro listed here.
The macros are grouped by function. The macro name is followed by the least number of macrocells used and a
description of the macro's function.

INPUTS
21NP
41NP
61NP
81NP

(0)
(0)
(0)
(0)

2
4
6
8

Input
Input
Input
Input

Pins
Pins
Pins
Pins

BURIED FEEDBACK
4NOCF
6NOCF
8NOCF

(4)
(6)
(8)

4 "No Output Combinational Feedback" I/O Primitives
6 "No Output Combinational Feedback" I/O Primitives
8 "No Output Combinational.Feedback" I/O Primitives

COMBINATIONAL I/O
4CONF
6CONF
8CONF
4COIF
6COIF
8COIF

(4)
(6)
(8)
(4)
(6)
(8)

4 "Combinational Output
6 "Combinational Output
8 "Combinational Output
4 "Combinational Output
6 "Combinational Output
8 "Combinational Output

No Feedback" .I/O Primitives
No Feedback" I/O Primitives
No Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives
Input Feedback" I/O Primitives

REGISTERED I/O
4RONF
6RONF
8RONF
,4ROIF
6ROIF
8ROIF
4RORF
6RORF
8RORF

(4)
(6)
(8)
(4)
(6)
(8)
(4)
(6)
(8)

4 "Registered Output No Feedback" I/O Primitives
6 "Registered Output No Feedback" I/O Primitives
8 "Registered Output No Feedback" I/O Primitives
4 "Registered Output Input Feedback" I/O Primitives
6 "Registered Output Input Feedback" I/O Primitives
8 "Registered Output Input Feedback" I/O Primitives
4 "Registered Output Registered Feedback" VO Primitives
6 "Registered Output Registered Feedback" I/O Primitives
8 "Registered Output Registered Feedback" I/O Primitives

4-38

inter

AB-21

LATCHES/REGISTERS
4REG
6REG
8REG
4LATCH
6LATCH
8LATCH
8TRANS
RSLATCH
DLATCH
DFFPRE

(4)
(6)
(8)
(4)
(6)
(8)
(8)
(1)
(1)
(2)

4 Registers with Common Clock and Clear
6 Registers with Common Clock and Clear
8 Registers with Common Clock and Clear
4 Transparent Data Latches with Common Enable
6 Transparent Data Latches with Common Enable
8 Transparent Data Latches with Common Enable
8-Bit Bi-Directional Data Transceiver
Set-Reset Latch
Standard D-Type, Transparent Latch
D Flip-Flop with Preset and Clear

MULTIPLEXERS/ENCODERS
2MUX
D2MUX
Q2MUX
4MUX
8MUX
16MUX
10MUXBCD

(0)
(0)
(0)
(0)
(0)
(0)
(0)

2-to~ 1 Multiplexer
Two 2-to-l Multiplexers
with Common Select
,
Four 2-to-l Multiplexers with Common Select
4-to-l Multiplexer
8-to-l .Multiplexer
16-to-l Multiplexer
10-to-4 BCD Encoder

CONVERTERS/DECODERS
BINGRY
GRYBIN
IDEC
2DEC
4DEC
3DEC
7SEG

(0)
(0)
(0)
(0)
(0)
(0)
(0)

4-Bit Binary to Gray Code Converter
4-Bit Gray Code to Binary Converter
I-to-2 Decoder
2-to-4 Decoder
4-to-16 Decoder
3-to-8 Decoder
4-Bits to Seven Segment Display Decoder·

COUNTERS/DIVIDERS
2CNT
4CNT
8CNT
16CNT
BCDCNT
FDIV2
FDIV5

(2)
(4)
(8)
(16)
(4)
(4)
(4)

2-Bit Counter with Preload and Clear
4-Bit Counter with Preload and Clear
8-Bit Counter with Preload and Clear
16-Bit Counter with Preload and Clear
4-Bit BCD Counter with Preload and Clear
Divides Input Frequency By 2, 4, 8, and 16
Divides Input Frequency By 5, 10, 15, and 20

4-39

inter

AB-21

SHIFT REGISTERS
2SHIFT
4SHIFT
8SHIFT
16SHIFT

(2)
(4)
(8)
(16)

2-Bit Serial or Parallel In Shift Register with Enable
4-Bit Serial or Parallel In Shift Register with Enable
8-Bit Serial or Parallel In Shift Register with Enable
16-Bit Serial or Parallel In Shift Register with Enable

ARITHMETIC OPERATIONS
IADD
2MULT
4COMP
8COMP
8PAREVN
8PARODD

(0)
(0)

(0)
(2)
(2)

(2)

I-Bit Full Adder
2-Bit Multiplier
4-Bit Magnitude Comparator... Equality Only
8-Bit Magnitude Comparator... Equality Only
8-Bit Even Parity Generator
8-Bit Odd Parity Generator

4-40

APPLICATION

AP-311

NOTE.·

October 1988

Using Macros in EPLD Designs

DANIEL E. SMITH
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292039-002

4-41

Ap·311

• A Macro Expander in the LOC that expands macro
calls in ADFs with the contents of the corresponding macros from libraries.

INTRODUCTION
The iPLS II (Intel Programmable Logic Software) Logic Optimizing Compiler includes a Macro Expander
that supports the use of macros in EPLD designs. This
application note shows how to use the TTL and EPLD
Custom macros available from Intel with ADFs created
by a text editor. Included are descriptions of macro file
support, guidelines for using macros, and two design
examples.

Figure I shows text editor/ADF macro support for
iPLS II. Note that the ADF can be created by any
standard ASCII text editor (text editor supplied by
user). Creation of user-defined macros is covered in application note, AP-312 "Creating Macros for EPLD
Designs", order number 292040. Use of macros with
schematic capture software is covered in the documentation for the respective software package.

OVERVIEW

This note discusses use of macros under the following
headings:
• Macro Libraries, briefly describes the two libraries
available from Intel.
• Using Macros, describes macro files, how to call
macros, the process of macro expansion, calling
mUltiple macro calls, and some basic guidelines to
follow and pitfalls to avoid.
• Two examples showing use of TTL macros, and
mixing macros and EPLD primitives.

iPLS II allows designers to include macro calls in design files to implement common circuit functions. Macro calls are subsequently expanded by the LOC (Logic
Optimizing Compiler) into ADF network and/or equation entries required to perform the desired functions.
Use of macros allows designs to proceed at a high level,
which simplifies and shortens the design process. Macros can be connected together or used in conjunction
with standard iPLS II EPLD primitives. Designing
with macros is analogous in many ways to using subroutines in software.
Macros can be used in ADFs (Advanced Design Files)
created by a text editor, or by several schematic capture
software products. This application note covers use of
macros in ADFs created by a text editor. Macro support at this level includes the following:
• A TTL macro library (TTL.LIB) for designing with
common TTL circuit equivalents
• An EPLD custom macro library (EPLDMAC.LIB)
for designing with "generic" macros.

MACRO LIBRARIES
Intel offers two macro libraries: a TTL Library and an
EPLD Custom Library.

TTL Macro Library
A TTL macro library (TTL.LIB) is available from Intel
to support design entry using familiar 74-series logic
IPLS II LOC

TEXT
EDITOR

---.

ADF

MACRO
EXPANDER

ESPRESSO
MINIMIZER

FITTER

---.

i
.-

I
I
I
. I

JEDEC

MACRO
LIBRARIES

14-- TTL

________ !4

EPLD CUSTOM
USER
292039-1

Figure 1. Text EditorI ADF Macro Support for iPLS II

4-42

AP-311

devices. The library contains macros that implement
the most widely used 74-series device functions as well
as macros for some members of other logic families.
Each device in the library is supported by a .DOe file.
The .Doe file describes the macro syntax and lists any
notable differences between the macro implementation
and the TTL part.

EPLD Custom Macro Library
An EPLD custom macro library (EPLDMAe.LIB) is
available from Intel to support design entry using
groups of EPLD primitives or "generic" functions such
as latches, registers, counters, decoders, etc.

USING MACROS
The iPLS II Macro Expander is automatically invoked
by the Loe when an ADF is submitted to the compiler. When invoked, the Macro Expander identifies macro calls in ADFs, searches macro libraries for a corresponding macro, and expands the call with ADF network and equation entries from the macro file. The
expanded file is then compiled normally.

Macro Files
Figure 2 shows the macro file for a 74138 TTL device,
a commonly used one-of-eight decoder. Note that the
first line contains the name and 1/0 signals for the
device. Signals are listed in the order' in which they
appear on the actual TTL device, including vee and
GND (i.e., A = pin 1, B = pin 2, ... , vee = pin 16).
The sequence of signals in this line determines how the
macro is "called" from an ADF.

Some of the macros in the TTL library have an "X"
suffix appended to the filename, for example 74138X.
This suffix indicates that the macro is device-specific
(not supported on all EPLDs) or that there is some
difference from the TTL device. This information is
described in the .Doe file for each macro.
The second line of the macro file contains defaults for
each input and place holders (blanks) for each output.
The default for an input sets the input to an intelligent
level (i.e., enables are enabled, clears, preset, loads are
disabled, etc.).
Macro files can contain a Network section, an Equation
section, or both. A Network section is not needed when
the macro functions can all be implemented in Boolean
equations. When used, the Network section contains
EPLD design primitives. An Equations section is not
needed when the macro functions can all be implement- .
ed in the Network section. Macro files end with the
keyword "ENDEF".

Macro Calls
All macro calls appear in the Network section of an
ADF. Macro calls use the same part/function name
and signal sequence used on the first line of the macro
file. The signal names in the macro and the macro call
do not need to match, but the order of signals in the
call is crucial to proper implementation of the macro
function. For example, the macro cali for the 74138
device could be anyone of the following examples:

74138(A,B,C,G2A,G2B,Gl,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Yl,YO,VCC)
74138(Dl,D2,D3,EN1,EN2,EN3,07,GND,06,
05,04,03,02,Ol,OO,VCC)

74138(A,B.e.nG2A.nG2B.Gl.nY7.GND.nY6.nY5.nY4.nY3.nY2.nYl.nYO.vec)
DEFAULT: (GND.GND.GND.GND.GND.VCC •• GND •••••••• VCC)
NETWORK:
EQUATIONS:
nYO
nY1
nY2

nY3
nY4
nY5
nY6
nY7

(!A· IB • !e • !nG2A • InG2B • Gl);
(A * !B • !e • !nG2A * InG2B * Gl);
Ie * !nG2A * !nG2B * G1);
(A • B • !e • !nG2A • !nG2B • Gl);
(!A· !8 • e • InG2A • InG28 • Gl);
(A • 18 • e • !nG2A • ·!nG28 • Gl);
(!A • 8 • e • InG2A • InG28 • Gl);
(A • 8 • e • !nG2A • !nG28 • Gl);
(!A • B *

ENDEF
$

292039-2

Figure 2. Sample TTL Macro File (74138.DEV)

AP-311

74138(A,B,C,ENA,ENB,ENC,Y7,GND;Y6;Y5,
Y4,Y3,Y2,Yl,YO,VCC)

appropriate gate array input or output macro calls.
When using gate array macros with EPLDs, the I/O
macros are implemented in terms of EPLD primitives.
Note that when designs targeted .for gate arrays are
partitioned for multiple EPLDs, many internal gate array signals are transformed into EPLD input and output signals. These signals must be supported by INPUT
and OUTPUT macro calls.

In each case, the part name corresponds to the macro
part name. The names of the signals differ, but the order of signals match the macro. During processing, the
Macro expander assigns node connections between the
macro call and the macro file based on the positions of
signals, not the names of the signals. For example, note
the following macro call to macro .file signal assignments:
.
ADF MACRO CALL

MACRO FILE SYNTAX

Macro Expansion
The Macro Expander identifies and expands each macro call in an ADF with the corresponding macro definition from macro libraries (the TTL library in the case
of the 74138). The Macro Expander searches libraries
in the following order and in the directories listed:
• MACRO. LIB-first in the current directory, then
in other directories specified by the DOS "PATH"
variable.
• user libraries (filename:LIB)-names for user libraries are specified in the "IPLS" environment variable. If a pathname and filename are both specified
(SET IPLS= C:\MACLIB\USRl.LIB;), the path is
treated. as an absolute path. If a filename' alone is
specified (set IPLS = USRl.LIB;), the Macro Expander searches for that library in the. directories
specified by the "PATH" variable. (IPLS can be set
in an AUTOEXEC.BAT file.)
• TTL macro library (TTL.LIB)-first in the current
. directory, then in other directories specified by the
. DOS "PATH" variable.

74138 ( A. B. C. EN 1. EN2. EN3. YCS •...

tttt tt t

.·74138 (A. B•. C. nG2A. nG2B. G1. nY7 •.•••

292039-3

TTL macro signals originating outside the target EPLD
require a prior INPUT macro call in the Network section. All signals used as outputs require a prior OUT~
PUT macro call in the Network section. Figure 3 shows
a sample ADF that uses the 74138 macro. Eachinput is
listed in the INPUTS: declaration and has an INPUT
macro call. Outputs are listed in the OUTPUTS: declaration and have OUTPUT macro calls. (EPLD INP
and CONF primitive statements may also be used in
place of INPUT and OUTPUT macro calls, if desired.)
Gate arrays support a much richer selection of'input
and output types than EPLDs. Gate array signals originating outside the. target gate arrily device require the
YOUR NAME
YOUR COMPANY
DATE
1
A

5CD60

One-af-Elght Decoder

OPTIONS, TURBO~OFF
PART, 5C060
INPUTS, A.B.C.G2A.G2B.Gl
OUTPUTS, Y7.Y6.Y5.Y4.Y3.Y2.Yl.YO
NETWORK,
INPUT{A.A)
.INPUT{B.B)
INPUT{C.C)
INPUT{G2A.G2A)
INPUT(G2B.G2B)
INPUT{Gl.Gl )
OUTPUT{Y7.Y7)
OUTPUT{Y6.Y6)
OUTPUT(Y5.Y5)
OUTPUT(Y4.Y4)
OUTPUT(Y3.Y3)
OUTPUT{Y2.Y2)
OUTPUT{Yl. Yl)
OUTPUT{ YO. YO)
74138{A.B.C.G2A.G2B.Gl.Y7.GND.Y6.Y5.Y4;V3.Y2.Yl.YO.VCC)
END$

292039-4

Figure 3. ADF File Calling the 74138 Macro

4-44

inter

AP-311

• EPLD Custom macro library (EPLDMAC.LIBr
first in the current directory, then in other directories specified by the DOS "PATH" variable.
• reserved library (INTEL.LIBrfirst in the current
directory, then in other directories specified by the
DOS "PATH" variable.

The Macro Expander uses the ADF Network and
Equation entries from the macro libraries and assigns
the appropriate primitives for INPUT and OUTPUT
calls. INP primitives are assigned to replace the INPUT macro calls. The OUTPUT calls are assigned
primitives with output pins and output enables are supplied where needed.

Only the first occurrence of a macro is used. The names
TTL. LIB, EPLDMAC.LIB, and INTEL.LIB are reserved by Intel. They may not be used for user libraries
and may not be specified in the "IPLS" variable. The
"IPLS" variable can contain more than one 'library
name. Each library can have an absolute path or can
rely on the "PATH" variable to determine the search
path.

Combination of primitives is automatically performed
when needed. For example, when a feedback primitive
such as a NORF feeds an output primitive such as a
RONF, the Macro Expander combines the two primitives into a RORF. Combination of primitives conserves resources and results in the shortest possible delay path through the device.
During: macro expansion, unused nodes are eliminated.
For example, the VCC and GND nodes that correspond to TTL power and ground pins are eliminated. If
an input node is not connected to a node in the ADF,
the default value for that node is assigned from the

NETWORK,
%
INPUT(A,A)
%
%A% A-INP(A)
%
'INPUT(B,B)
%
%A% B=INP(B)
%
INPUT(C,C)
%
%A% C=INP(C)
%
INPUT(G2A,G2A)
%
%A% G2A=INP(G2A)
%
INPUT(G2B,G2B)
%
%A% G2B=INP(G2B)
%
INPUT(G1,G1)
,%
G1=INP(G1)
"
OUTPUT(Y7,Y7)
%
Y7=CONF{Y7,VCC)
"
OUTPUT{Y6,Y6)
"
Y6=CONF(Y6,VCC)
OUTPUT{Y5,Y5)
%
"
%A" Y5=CONF{Y5,VCC)
%
OUTPUT{Y4,Y4)
"
%A% Y4=CONF(Y4,VCC)
%
OUTPUT(Y3,Y3)
"
%A% Y3-CONF(Y3,VCC) .
%
OUTPUT(Y2,Y2)
"
%A" Y2=CONF(Y2,VCC)
"
OUTPUT(Y1,Y1)
"
"A% Y1-CONF(Y1,VCC)
"
OUTPUT{YO,YO)
"
YOsCONF(YO,VCC)
"
74138{A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,Y4,Y3,Y2,Y1,YO,VCC)

"A"
"A"
"A"

"A"

EQUATIONS,
%A% YO-I{IA*IB*IC*IG2A*IG2~*G1);
%A" Y1-I(A*IB*IC*IG2A*IG2B*G1);
%A" Y2=!{!A*B*IC*!G2A*!G2B*G1);
Y3=!(A*B*!C*!G2A*!G2B*G1);
Y4=!{IA*IB*C*!G2A*!G2B*G1);
%~" .Y5=I(A*IB*C*IG2A*!G2B*G1);
Y6=!{IA*B*C*IG2A*IG2B*G1);
"A% Y7=I{A*B*C*IG2A*IG2B*G1);

"A"
"A"
"A"

292039-5

Figure 4. Network and Equations for 74138.SDF
4-45

intJ

AP-311

DEFAULT: section of the macro file. Note, however,
that the default value for each input in the macro file
may be the, value that disables the input or, for data
inputs, is usually a logic O. To be certain of the level
used, specify a "VCC" or "GND" in the macro call for
unused inputs.

The Macro Expander uses the first three ASCII characters after the first percent sign (%), except for white
space, to create instance llUmbers. For example, internal nodes for the first three signals of each macro call
will be:

..SFAN1, •• SFAN2, •• SFAN3,
The INPUT and OUTPUT calls and the original macro.call are "commented out" by surrounding them with
percent (%) signs. The. %A% string is placed at the
start of lines where primitives are created by the Macro
Expander. The fully expanded file is written to the disk
using the original filenanie and a .SDF extension. Figure 4 shows the Network and Equation sections for the
74138 SDF.

•• SFBN1, •• SFBN2, •• SFBN3
where SFA/SFB are the user-defined instance names
and Nl, N2, N3 are the node numbers associated with
each instance. For ca~es where no internal nodes numbers are generated, the Macro Expander simply ignores
the instance name.
Outputs from one macro call can be used as inputs for
other calls, as follows:

One final note with regard to compiling ADFs .that use
macros. Warning messages are typically encountered
while compiling. files that use macros. The most common message is .. ···WARN-XLT-Node Missing Destination". This message is displayed as unused nodes
from a macro are deleted. For example, if a macro using a: NOCF primitive is combined with a CONF and
the original feedback is not needed, the warning is displayed as the feedback is deleted.

74138(A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Y1,YO,VCC)
74138(A,B,C,Y7,G3B,Gl,YF,GND,YE,YD,YC,
YB,YA;Y9,Y8,VCC)
Here the Y7 output from the first decoder feeds an
enable input of the second decoder.

Multiple Macro Calls
The Macro Expander allows use of more than one mac.ro in ADFs. Each macro must have its own call, even
when the same macro, is used more than once.

Different macros are connected in the same manner.
For example, the following macro calls connect the out~
pilts from a 74138 decoder to the inputs of 74175 latches:

For example, to implement two 74138s, each case or
"instance" must have its own call:

74138(A,B,C,G2A,G2B,G1,Y7,GND,Y6,Y5,
Y4,Y3,Y2,Y1,YO,VCC)

74175(CLR,OQ,nOQ,YO,Y1,n1Q,lQ,GND,CLK,
2Q, n2Q,Y2,Y3,n3Q,3Q,VCC)

74138(A,B,C,G3A,G3B,G1,YF,GND,YE,YD,
YC,YB,YA,Y9,Y8,VCC)

74175(CLR,4Q,n4Q,Y4,Y5,n5Q,5Q,GND,CLK,
6Q, n6Q,Y6,Y7,n7Q,7Q,VCC)

In this example, many of the inputs are routed to both
devices. The Macro Expander automatically generates
internal nodes for each instance of the macro. Each
node is assigned a unique number based on the position
of the macro in the Network section (i.e., . . 0140,
.. 0141, etc. for nodes connecting to the 14th primitive
in the Network section).

Each decoder output is routed to a 74175 input.. The
74175 macro produces both true and complement
latched outputs.

Guidelines/Pitfalls
The following paragraphs discuss some general guidelines for using macros:
• Because the Macro Expander supports only one level of hierarchy, there is a tendency for p-terms to
multiply quickly when several macros are connected
together. In many cases, 'the total number of p-terms
exceeds the capacity of the target EPLD. One method of avoiding problems with excessivep-terms is to
route the outputs from a macro function through
EPLD macrocells and ,use the feedbacks from the
macrocells as inputs to the subsequent macro func~
tions. This partitioning of functions trades off device
resources for a lower p-term count.

For traceability, you can define your own instance
names for nodes of different macros by including the
iilstance name in a comment immediately following the
macro call. For example, to call two 74161 macros, one
as Shift Register A and the other as Shift Register B,
enter the calls as follows:

·74161 (CLR, CK,A,B, C,D,ENP, ,LD,ENT ,QD,
QC,QB,QA,RD1,) % SFA %
74161(CLR,CK,E,F,G,H,ENP"LD,ENT,QH,
QG,QF,QE,RC2,) % SFB %
4-4,6

inter

AP-311

• Implementation of some TTL macros requires primitives that are not supported on. all devices. The
.DOC file for a device notes any device dependency.
In many cases, a modification to the basic TTL
functions results in device independence. For example, a NOCF, which is not supported on all EPLDs,
can be changed to a COIF, which is supported on
all devices.
• Some macros use primitives that specify an output
pin (COIF, CONF, RORF, etc.). These primitives
must be supported with a signal name in the OUTPUTS: declaration and by an OUTPUT call in the
Network Section of the ADF. Failure to provide
this support causes the following error message during compilation:

Circuit
The design is a two-stage decoder using a 74138 macro
and two 74139 macros. Figure 5 shows the schematic
for the circuit. Each 74139 macro represents one half of
. a TTL 74139 device. Note that two of the outputs from
the 74138 are routed back to enable the two 74139 decoders.

Yl
Y2
Y3

74138

***ERR-XLT-undeclared output name

YCS
YCE

If you encounter this error, check the macro file for
output primitives that require ADF support.

EN 1
EN2
EN3

o
74139

CEO
CEI
CE2
CE3

74139

CSO
CSI
CS2
CS3

L....c

Macro Usage Summary

r--

ADF macro calls must observe the following guidelines:
• Macros are called from the Network Section of an
ADF.
• The name in the call must match the name in the;:
macro file (e.g., 74138 = 74138).
• All input and output pins on the target device must
have both: (1) a corresponding signal name in the
INPUTS: or OUTPUTS: declaration, and (2) a corresponding INPUT or OUTPUT macro call in the
Network section. It is recommended that the same
node name be used on both sides of each INPUT
and OUTPUT macro call.. This is required when
macros containing CONFs ate used. (EPLD INP
and CONF primitives may also be iIsed).
• All INPUT and OUTPUT calls in the Network sec.
tion must precede any other macro call.
• Node connections within an AOF are made·based
on the names of the nodes.
• Connections between the macro call and macro files
are based on the position of signal names in the call.
Therefore, the sequence of inputs and outputs in a
macro call must match the sequence of inputs and
outputs in the corresponding macro file.

L....-c

292039-6

Figure 5. Schematic Diagram
for Two-Stage Decoder
Figure 6 shows the ADF file containing the macro calls
that implement the circuit. The two internal feedback
signals (Y.CS "and YCE) do not show up in the INPUTS: or OUTPUTS: declarations and are not represented by INPUT or OUTPUT calls in the Network
section. The sequence of signals in the INPUTS: arid
OUTPUTS: declarations of the. ADF is not important.
In the NETWORK: section, however, order is important. INPUT and OUTPUT calls must be listed before
any other macr()c"alls. This is requirement ofthc;:
Macro Expander.· The sequence of signals within the
ADF macro call is critical, as the Macro Expander autoimltically assigns macro call signals to ·macro fIle signals based on position.
.

Internal connections between macros are established by
assigning the same name to the respective signals. For
example, YCS in the 74138 macro call in Figure 7 represents the nY6 output from the 74138, while YCS in
the 74139 macro call represents the IG input to one
74139 decoder. Use of the same name establishes the
connection. In the same manner, use of the signal name
YCE connects the nY7 output from the 74138 to the
lG input of the second 74139.

EXAMPLE 1: TTL MACROS
This section provides an example design using TTL
macros.

4-47

AP-311

DANIEL E. SMITH
, INTEL CORPORATION,
2/27/87
'
'1
A

5C090
TWO":STAGE DECODER
OPTIONS: TURBO=OFF
PART: 5C090
INPUTS: A, B, C, 0, E, ENl ,EN2, EN3 '
OUTPUTS: Yo,Yl,Y2,Y3,Y4,Y5,CSO,CS1,CS2,CS3,CEO,CE1,CE2,CE3,
NETWORK:
'INPUT (A,A)
INPUT' (B,B)
INPUT (C',C)
INPUT (0,0)
INPUT (E,E),
INPUT (EN1,EN1)
INPUT (EN2,EN2)
INPUT (EN3, EN3)
OUTPUT (YO,YO)
OUTPUT (Yl, yo
,OUTPUT (Y2, Y2)
OUTPUT (Y3, Y3)
OUTPUT (Y4,Y4)
OUTPUT' (Y5"Y5)
OUTPUT (CSO,CSO)
OUTPUT (CS1,CS1)
OUTPUT (CS2,CS2)
OUTPUT' (CS3;CS3)
OUTPUT" (CEo',CEo)
OUTPUT (CE1,CEl)
OUTPUT (CE2,CE2)
OUTPUT (CE3,CE3)
,
74138(A", B ,C,EN1, EN2',EN3, YCS,GNo"YCE, Y5, Y4, Y3, Y2, Yl ,Yci~ VCC)
74139(YCS ,o,E,CSO,CSl ,CS;! ,CS3"GNo, VCC)
74139(YCE~o,E,CEo;CE1,CE2,CE3,GNo,VCC)

, ENDS

292039-7

Figure 6. ADF File for Two-Stage Decoder Using TTL Macros

Sample Session'

3. Invoke theLOC from the Main Menu by pressing

This session assumes familiarity with the iPLS II Logic
Optimizing Compiler (LOC). For detailed information
on the LOC, refer to Chapter 4 of the iPLS II User's
Guide, order number: 450196. PrOceed as follows to
implement the TTL macro'desi8!i"shownhere:
1. U~ a staild~d ASCIIte~t edit~r.t~ create the ADF
, shoWn in, Figure 7 under the nameI?ECODE.A,'Df.
2. Invoke the iPLS II Menu by entering: ,

4. Answer the LOC p!;,omtsas follows:

. .

Input Format ,?
File Name?
Minimization?
Inversion Control?
LEFAnalysis?
Error Message File

IPLS

4-48

DECODE
y
N
y,

AP-311

circuit. CS2 and CS3 are qualified by two additional
inputs (RD" and WR") to set or clear two latches. This
is a configuration commonly used in microcomputer
systems, where control signals are set and reset based
on the address and command signals but not on a data
value. A read to the port decoded by CS2 sets output
LCS2 (Latched CS2) high. A write to that same port
clears LCS2 low.

The LaC then asks:

Do you wish to run under the above
conditions [YIN]?
Enter: Y
The LaC expands the macros and compiles
the expanded. file to produce a JEDEC programming file (DECODE.JED), a utilization report file (DECODE. RPT), a minimized equation file (DECODE. LEF), and an error message file (DECODE. ERR). For tracability, a
file called DECODE.SDF is created to show
the expanded form of the ADF output by the
Macro Expander.
5. The LaC terminates execution with the following
message:

Figure 8 shows the ADF that implements the example
circuit. This is the same ADF used in Figure 6, with
the addition of several primitives and equations. The
data inputs to both latches are tied to VCC. When RD"
and the chip enable are both low, the respective clock
signal goes low. As RD" or chip enable go high, the
rising edge of the clock signal triggers the register, driving the output high.

LOC cycle successfully completed

Note that many Intel EPLDs do not support multiple
product terms for register clocks. Therefore, the clock
buffer primitive is driven by a macrocell configured as a
COIF (Combinatorial Output-Input Feedback). Control signals (Clear and Preset) for many EPLDs also
support only one product term. In this case, however,
the NOR gate driving the clear input to the RONFs
can be minimized to a single p-term. Thus a low on
WR· and chip enable clears the respective latch to logic
O. (The intermediate macrocell for the Read function
can be omitted for EPLDs that support two p-terms on
register clocks.)

You can examine the LEF file to see the minimized
form of the design. The LEF shows the EPLD primitives used to implement the design. Macro calls are not
shown. If you wish, you can also use LPS (Logic Programmer Software) to program a part.

EXAMPLE 2: MIXING MACROS AND
EPLD PRIMITIVES
This final example uses TTL macros together with
standard EPLD primitives.

The connections between the TTL macros and the
EPLD primitive are made by assigning the appropriate
names to the input and output nodes. The CS2 and CS3
signals from the first example are no longer .outputs,
-but are simply inputs to equations that feed the LCS2
and LCS3 RONF primitives.

Circuit
The example circuit here is the 74138 macro used in
example I with two of the outputs routed through additional combinatorial logic and RONF (Registered Output - No Feedback) primitives. Figure 7 shows the

4-49

AP-311

A
B
C

YO
Yl
Y2
Y3
Y4
. Y5

.74138
ENl
EN2
EN3
YCS
YCE

CEO
CEl
CE2
CE3

D
E

CSO
CSl

RD·-----+;-----~_.~

>-.....-SET2 e

">.,..-.....-

SET3 e

>------LCS2

Vee
>----LCS3

292039-11

Figure 7. Schematic of Decoder Circuit with Latched Outputs

4·50

inter

AP-311

DANIEL E. SMITH
INTEL CORPORATION
2/27/B7
1
A

SCOSO
DECODER WITH TWO LATCHED OUTPUTS
OPTIONS:
TURBO-OFF
PART:
5C090
INPUTS:
A,B,C,D,E,EN1,EN2,EN3,RD*,WR*
OUTPUTS: SET2c,SET3C,YO,Yl,Y2,Y3,Y4,Y5,CSO,CS1,LCS2,LCS3,CEO,CE1,CE2,CE3NETWORK:
INPUT (A,A)
INPUT (B,B)
INPUT (C,C)
INPUT (0,0)
-INPUT (E,E)
INPUT (ENl ,EN1)
INPUT (EN2,EN2)
INPUT (EN3,EN3)
OUTPUT (YO,YO)
OUTPUT (Yl,Y1)
OUTPUT (Y2,Y2)
OUTPUT (Y3,Y3)
OUTPUT (Y4,Y4)
OUTPUT (Y5,Y5)
OUTPUT (CSO,CSO)
OUTPUT (CSl ,CS1)
OUTPUT (CEO,CED)
OUTPUT (CE 1 ,CE 1 )
OUTPUT (CE2,CE2)
OUTPUT (CE3,CE3)
74138(A,B,C,EN1,EN2,EN3,YCS,GND,YCE,Y5,Y4,Y3,Y2,Yl,YO,VCC)
74139(YCS,D,E,CSO,CS1,CS2,CS3,GND,VCC)
74139(YCE,D,E,CEO,CE1,CE2,CE3,GND,VCC)
RD a INP(RD*)
WR = INP(WR*)
LCS2 = RONF(VCC,SET2,CLR2,GND,VCC)
LCS3 = RONF(VCC,SET3,CLR3,GND,VCC)
SET2 _ CLKB(SET2c)
SET3 = CLKB(SET3C)
SET2c,SET2c - COIF(ST2,VCC)
SET3c,SET3c - COIF(ST3;VCC)
EQUATIONS:
ST2 _ RD + CS2;
CLR2 = I(WR + CS2);
ST3 = RD + CS3;
CLR3 = I(WR + CS3);
ENDS
292039-12

Figure 8. ADF File for Decoder with Latched Outputs

port file (LDECODE.RPT), a minimized equation file
(LDECODE.LEF), and an error message file
(LDECODE.ERR). For traceability, a file called
LDECODE.SDF is created to show the expanded form
of the ADF output by the Macro Expander.

Sample Session
To implement this ADF in an actual session, follow the
steps described for Example I, substituting the name
LDECODE for DECODE. iPLS II produces a JEDEC
programming file (LDECODE.JED), a utilization re-

4-51

inter

AP-312

APPLICATION·
NOTE

October 1988

Creating Macros ..
for EPLD Designs

DANIEL E. SMITH
PROGRAMMABLE LOGIC APPLICATIONS
INTEL CORPORATION

Order Number: 292040-002
4-52

Ap·312

By following the macro file format described in this
note, users can also create their own proprietary macros with an ASCII text editor. These macro files can
then be stored in user-defined libraries by using 'Intel's
Macro Librarian software. User-defined macros can be
called from ADFs created by a text editor or by schematic capture software that supports user-defined symbols and that outputs in ADF format. User-defined
macros can optimize development of EPLD designs by
modularizing the design process and by allowing the
design process to proceed at a higher level than with
EPLD primitives alone. iPLS II support for user-defined macros (see in Figure I) includes the following:
• MLIB, the optional iPLS II Macro Librarian for
creating macro libraries from individual user-de.fined macro files.

INTRODUCTION
The iPLS II (Intel Programmable Logic Software II)
Logic Optimizing Compiler includes a Macro Expander that supports the use of macros in EPLD designs.
These macros can include TTL and EPLD custom
macros available from Intel, or proprietary macros developed by a user. This application note shows how to
create user-defined macros and how to build macro libraries with Intel's Macro Librarian, an optional software package for use with iPLS II. A design example
also shows creation of a user-defined macro and its use
in an ADF (Advanced Design File). Detailed information on using the TTL Macros in iPLS II ADFs are
described in a companion application note; AP-311
"Using Macros in EPLD Designs", Order Number:
292039. This application note concentrates on creating
macros; it assumes that you have read and understood
the discussion on using macros in AP-311.

•. a Macro Expander·in the LOC that expands macro
calls in ADFs with the contents of the corresponding macros from libraries.
This application note describes how to create macro
files, store them in libraries with MLIB, and shows how
to call them from ADFs created by a text editor. For
information on creating user-defined macro symbols
with schematic capture packages, refer to the appropriate
manual for the schematic capture package you are using. SCHEMA II-PLD available from Intel supports
user-defined symbols and outputs in ADF format.

OVERVIEW
iPLS II allows designers to include macro calls in design files to implement common circuit functions.Macros calls are subsequently expanded by the LOC (Logic
Optimizing Compiler) into the ADF network and/or
equation entries required to perform the desired functions. Macros can be connected together or used in conjunction with standard iPLS II EPLD primitives.

SCHEMATIC
CAPTURE'

r--..

1
SYMBOL
LIBRARY
iPLS II LOC

TEXT
EDITOR

ADF

I---t

TEXT
EDITOR

f-+

MACRO
FILES

MLiB

r-.

ESPRESSO
MINIMIZER

FITTER

I---t

MACRO
LIBRARIES

JEDEC
FILE

MACRO
LIBRARIAN

I--.

MACRO
EXPANDER

....

I+-- TTL. LIB
EPLDMAC.LlB
USER. -DEFINED (·.LlB)
292040-1

Figure 1. Macro Support foriPLS II
4-53

intJ

AP-312

(SCHEMA II-PLD is based on SCHEMA II from
Omation, Inc; The Intel EPLD Design Manager, also
available from Intel, allows existing . SCHEMAII users
to design with EPLDs and macros.)'

16207 (A,B,C,D,E,F,U,V,W,X,Y,Z)
16207 (B,D,A,R,Z,U,W,C,F,X,E,Y) .
16207 (Z;Y,X,W,V,U,F,E,D,C,B,A)

MACRO FILES

Note that this first line of the header forms the template used to call the Macro from the ADF. The Macro
Expander connects AUF nodes in the macro call to
I/O signals in the macro file on the basis of position,
not on the ,basis of node 'name.

This section describes iPLS II macro files. User-defined
macro files must follow the guidelines presented here to
be successfully processed by the Macro Librarian
(MLlB) and expanded by the iPLS II LOC Macro Expander.

The second line in the header specifies defaults for inputs (VCC or GND) in cases where those signals are
left unconnected. The DEFAULT: line must be included in the macro definition file, even when no defaults
are used in the ADF. The keyword DEFAULT: is the
first entry in this line. The default values for all signals
follow immediately and are.enclosed in parentheses. In~
put defaults may be VCC or GND. The position of the
default value corresponds to the signal listed in the previous line.

Macro filenames follow'DOS conventions. It is recommended that' macro filenames end with the extension
.DEV, which is the default for MLIB. Only omi macro
can be contained in a macro file. Macro files are comprised of three sections:
• Header
• Network-Section
• , Equation Section

Defaults for outputs are blank, but a comma (,) must be
present (place holder) for each output signal except the
last. For example, the 16207 black box contains six inputs (A through F) and six outputs (U through Z). The
first two lines for this macro might be:
'

All macro files must end with the literal "ENDEF".
Figure 2 shows a sample macro file for a proprietary
part (16207), a "black box" containing random logic. '
16207(A. B ,C,DIE. F ,u , v.w.

x. y ,Z)

16207 (A,B,C,D,E,F,U,V,W,X,Y,Z) ,
DEFAULT: (GND,GND,GND,VCC,VCC,VCC"",,)

OEFAULT,(GNO.GNO.GNO.VCC.Vcc.Vcc; ••••• )
EQUATIONS,
U_/(A*B);
V _ I(/E

Defaults for inputs A through Care GND; defaults for
inputs D through Fare VCC. Defaults for the outputs
are not specified, but the comma denotes the positions
for those signals.

A • B)i

W _ 1(0 • C • A

IE);

X - 1(10 * E);
Y _ I(F * 0 • A)i
Z - F * IE;

ENDEF

Defaults should be chosen with care. Clears, Presets,
Loads, etc. should be disabled in most cases. Enables
should be enabled. Input defaults can also be left blank
as long as those inputs are 'connected to nodes in the
ADF that calls the macro, but it is recommended that
they be specified in the macro file.

292040-2

Figure 2. Sample Macro File for
"Black Box" (16207.DEV)

Header
Headers for macro files contain two lines.. The first line
includes the name of the macro function and a list of
inputs'and outputs for the macro~ The second line con-'
tains defaults for the device. '
The name of the macro can be a device number (16207,
83546, etc.), function name (ADDRCNT, CMDLO,
etc.), or any name up to eight characters long. No
'
spaces or comments precede the name.
Inputs and Outputs follow immediately after the macro
name and are enclosed in parentheses. 110 signal
names may be up to eight characters long, but may not
contain pin numbers. For user-defined macros, signals
may be listed in any order desired. For example, any of
the following entries are legal: '

Network Section
The NETWORK: section lists the EPLD primitives
used to implement the desired functions. The Network
Section follows ADF syntax rules. As far as possible,
the macros should be implemented in equations to eliminate concern about feedbacks and output enables. In
the case of ,a circuit that requires macrocell registers,
the feeback-only form of the primitive should be used
so that the Macro Expander can make the correct pin
connections. The following example shows this:
OUTl= NORF (INd,CLK,GND,GND)

4-54

AP·312

During processing, the Macro Expander connects the
feedback to an output (if necessary) and supplies the
required output enable node name. The Macro Expander also eliminates unneeded Network and Equations
entries if they are not used by an ADF.

MACRO LIBRARIAN
The Macro Librarian (MLIB) is an optional software
package that combines individual macro files into macro libraries. These libraries are in turn used by the LOC
Macro Expander. MLIB can be invoked from the command line, from command files, or from a combination
of both. Figure 3 shows a block diagram of the Macro
Librarian.

If no network entries are required (i.e., a macro implemented entirely in equations), the entire Network sec"
tion may be omitted, including the keyword NETWORK:. In many cases, equations alone can implement the desired functions.

Syntax for MLIB command lines is as follows:
MUB [-options 1 [@cmdfile 1 [filel me2 ••• 1

-d
directory. Displays directory information for
the library being created.
-v
verbose. Print status during processing. When
not specified, status messages are suppressed.
-I lib
list. Lists the contents of existing macro library to console. This option may not be used
while building a library.
-oJib
name of the target macro library,
MACRO. LIB is the default when no name is
specified. TTL.LIB, EPLDMAC.UB, and
INTEL.LIB are reserved for Intel libraries
and may not be used.
-s string include version stamp in macro library. The
version string can be up to 7 characters long.
"V1.00" is the default stamp.

Equations Section
The EQUATIONS: section lists the Boolean equations
for the desired functions and follows ADF syntax rules,
with one exception; intermediate equations are not permitted in macro files. If no equation entries· are required (i.e., a macro implemented entirely in the Network Section), the entire Equation section may be omitted, including the keyword EQUATIONS:.

Comments and White Space
Comments can be placed anywhere in a macro file except before the name and signals on the first line. Comments must be enclosed in percent signs, as follows:

% THIS IS A SAMPLE COMMENT %
White space can appear on any line except the first two
lines.

TEXT
EDITOR

f-+

TEXT
EDITOR

r-.

MACRO
FILES

COMMAND
FILE

I
r-.

MUB

r-+

MACRO
LIBRARY

LIBRARY
LISTING
292040-3

Figure.3. Macro Librarian Block Diagram

4-55

AP-312

-c string

include copyright string in macro library.
The copyright string can be up to 61 characters long and, if blanks are used, must be
,contained in quotation marks, for example,
"texta textb".
, @cmdfile name of command file. The cornmand file
can include options and macro filenames.
The @ symbol must precede the filename.
file 1 . . . name of device files to be included in the
macro library. Separate files by ~paces.

-0 PROJA.LIB" macro library, name,"

-v
-$

V1.50 " version number"

-c

~'Copyr

Ight

(C)

Date. "Your Company. Your Name-

" copyright Information"
-d " display directory"

,ln~I,,:,~e

INPUT .DEV
7487.DEV
74151.DEV

the following macros"
OUTPUT. DEV
7408. DEV
'74138.DEV
74139.DEV
74157.DEV
74251.DEV

292040-4

Figure 4. Sample Command File for MUB

For example, the following command line:

The command line to process the file shown in Figure 4
is as follows:

MLIB -v -s 2.00 -0 USER.LIB @USERLIST
creates a library called USER.LIB that includes all the
individual macro files contained in the command file
USERLIST. MLIB displays status messages as it processes the macro files in USERLIST(-v). The library is
created as version 2.00 (~s).
'

MLIB @SAMPLE
where'SAMPLE is the name of the command file. ,
To list the, contents of PROJA.LIB after creation, invoke MLIB as follows:

Macro library filenames follows DOS conventions and
should end with the extension .LIB to be recognized by
the Macro Expander. TTL.LIB, EPLDMAC.LIB, and
INTEL.LIB are' reserved and may not be used.

MLIB -I PROJA.LIB
This command line lists the macros in PROJA.LIB to
the screen: The DOS file redirection capability can also
be used to create a disk file listing the contents of macro
libraries. For example:

USERLIST is the name of the command file and must
be preceded by. the@ symbol. The command, file is
simply an ASCII text file that can be modified to contain any number. of macros desired. MLIB processes
the entire list of macros on each invocation. To add a
new macro to an existing library, add the name of the
macro to USERLIST, and create the new library by
entering the command line shown above. Command file
names follow DOS conventions. MLIB supplies a .DEY
extension if no extension is specified. MLIB searches
first in the current directory, then along the DEY environment variable, and finally along the PATH environment variable for the files.

MLIB -IPROJA.LIB > PROJA.DOC

SAMPLE SESSION: COMMAND
DECODER USING MACROS
Decoding logic is one common function implemented
by programmable logic devices. The target circuit for
this, example is a device that decodes microprocessor
command. signals in selected address ranges. The target
application and decoder requirements are as follows:
• The target application is a I6-bit microcomputer
system with I-Megabyte of memory and about two
dozen I/O ports.
• ,The memory is divided into shared memory (lower
5I2K bytes) and local memory (upper 5I2K bytes).
Shared memory resides off the processor board and
requires active low memory command signals. Local
memory resides on-board and requires active high
memory command signals.
• I/O ports are also split between on-board devices
requiring active high signals and off-board devices
requiring active low signals. I/O devices between
the address range FOOO-FFFFH are on-board; dec
vices below that range (OOOO-EFFFH) are off-board.

In order to connect inut and output primitives, the files
INPUT.DEY and OUTPUT. DEY must be included in
at least one of the libraries. These files are contained in
the TTL macro library.
Figure 4 shows a sample MLIB command file that includes options, the library name, and the names of seven macro files to be included in the library in addition
to the INPUT and OUTPUT macros. The format of
the command file is free form. Note that comments can
be included in the command file and must be contained
within percent (%) signs.
Note that the -1 option cannot be included in an MLIB
command file; it can only appear on the command line.
The -1 option lists the contents of existing libraries; it
does not list library contents while building a library.

4-56

AP-312

• All interrupt requests are resolved by an on-board
interrupt controller. Therefore, only an active high
on"board interrupt acknowledge signal is needed.
• On-board control signals are always high or low,
never three-stated. Off-board control signals are
three-stated when not being used to execute a bus
cycle. An external bus arbiter accepts a request signal from the command decoder and, after gaining

control of the bus, sends address enable and command enable signals back to the command decoder.
Figure 5 shows a block diagram of the application, including the. target EPLD design. The three functional
blocks to be included in the EPLD are highlighted (not
shaded).

OFF- BOARD
SYSTEM BUS
ADDRESS AND
DATA BUS

ON- BOARD
BUS

ENABLE

292040-5

Figure 5. Block Diagram of Target Circuit and Application

4-57

AP-312

Creating the Macro

Building the Library

Figure 6 shows a schematic diagram for the active low
command decoder implemented with OR gates (low inputs enable the outputs; high inputs disable the outputs). Figure 7 shows the macro file that implements
the circuit (CMDLO.DEV). This file was created with
an ASCII text editor. Used as is, it provides the active
low outputs for the design. With inputs RD, WR, and
INTAIN inverted, it also provides the active high outputs for the design. This design uses CONF primitives
to implement the three-state outputs in the macro. As
an' alternative, equations alone could have been used
with the CONFs included in the ADF.

Use your text editor to create an MLIB command file
that includes CMDLO.DEV, INPUT.DEV, and OUTPUT.DEV. The following example shows .a sample
command file named MACLIST.
-v % show status %
-c "1987, AP-3l2 Sample Macro Library"
-0 AP3l2.LIB
-d % show the list %
% include the following macros %

CMDLO.DEV
RD __;::::::+:::r~

Invoke the Macro Librarian with the following. command line:

MRD

MLIB
MWT

lOR

:~~=:::j~_"

lOW

INTAIN - - - - - - - - - H

INTA

MIO
eMDEN

INPUT.DEV OUTPUT.DEV

@MACLIST

The Macro Librarian processes the three macro files
'and stores them in a user library named AP3l2.LIB.
The library contains the copyright statement "1987,
AP-3l2 Sample Macro Library". When processing is
complete, MLIB returns control to DOS.

CreatiQg the ADF
Figure 8, shows a schematic diagram for the target
circuit. Figure 9 shows the ADF for the circuit (COMCODE. AD F), which invokes both instances of the
CMDLO macro and contains equations used to enable
the decoders under the proper conditions. The ADF
signal named ONBEN (On-Board Enable) enables the
active high decoder). The AEN (Address Enable) input
to the on-board decoder is left unconnected. The default (always enabled) will be used.

AEN - - - - - - - - - '
.292040-6

Figure 6. Schematic Diagram of
Command Decoder

CMDLO(MIO,RD,WR,INTAIN,CMDEN,AEN,MRD,MWT.IOR,IOW,INTA)
DEFAULT:(GND.VCC.vcc.VCC.GND.GND .•... )

NETWORK,
MRD = CONF(MRDc,AEN)
MWT = CONF(MWTc,AEN)
lOR = CONF(IORc,AEN)
lOW = CONF( IOWc,AEN)
I NTA = CONF( I NTA I N, AEN)
EQUATIONS,
MRDc

IMID + RO + CMDEN;

MWTc - IMIO + WR + eMDEN;
lORe

ICE

lOWe

MID + RD
MID + WR

+ eMDEN;
+ eMDEN;

ENDEF

292040-7

Figure 7. Macro File for Command Decoder (CMDLO.DEV)

4-58

inter

AP-312

NINT

INTAIN·

Mia

MilO·

OFF- BOARD
DECODER

INTA
MRD

NRD

RD·

MWT

NWR

WR·

lOR
lOW

Vee

Mia
RD
WR

i---+--{:> MRDC·
i---+--{:> MWTC·
i---+--{:> IORC·
i---+--{:> IOWC·

CMDEN·E:>--------+--rt+---~

AEN1E:>------------~--~-rr_--------~
A13[;>----------1~~--~~~~

AF
AE .-........r---... UPPER

r.--~--r-~_t+.,

ADL...o-L-_
AC

NMIO

NA13
~----..__

OFFBDEN·

NUPPER
292040-8

Figure 8. Schematic Diagram for COMCODE.ADF

4-59

inter

AP-312

DANIEL E. SMITH
INTEL CORPORATION
417 /87
I
A

16209-001
COMMAND DECODER

OPTIONS: TURBO_ON
PART,
5C090
INPUTS'
MIO, RD, WR, INTAIN, CMDEN,AEN1, A13, AF, AE, AD, AC
OUTPUTS, MRD, MWT, lOR, lOW, INTA, MRDC, MWTC, 10RC, 10WC, OFFBDEN
NETWORK,
INPUT(MIO,MIO)
INPUT(RD,RD)
INPUT(WR,WR)
INPUT( INTAIN, INTAIN)
I NPUT(CMDEN,CMCEN)
I NPUT(AENl ,AEN1)
INPUT(A13,A13)
INPUT(AF ,AF)
INPUT (AE, AE)
INPUT(AD,AD)
INPUT(AC,AC)
OUTPUT(MRC,MRD)
OUTPUT(MWT ,MWT)
OUTPUT( lOR, lOR)
OUTPUT( lOW, lOW)
OUTPUT(INTA,INTA)
OUTPUT(MRDC,MRCC)
OUTPUT(MWTC,MWTC)
OUTPUT(IORC,IORC)
OUTPUT(IOWC,IOWC)
CMDLO(MIO,RC,WR"CMDEN,AEN1,MRDC,MWTC,IORC,IOWC,) % OFB %
CMDLO(MIO,NRD,NWR,NINT,ONBEN,VCC,MRC,MWT,IOR, 10W,iNTA) % ONB %
OFFBDEN
OFBEN
ONBEN
NRC
NWR
NINT
NMIO
NUPPER
NA13

_ CONF(OFBEN,VCC)
_ NOR(OF1,OF2,OF3,OF4)
NOR(ON1,ON2,ON3,ON4)
= NOT(RD)
_ NOT(WR)
a

.. NOTC INTAIN)

• NOT,(MIO)
- NOT( UPPER)
_ NOT(A13)

EQUAT IONS,
UPPER _ (AF • AE • AD
ONl
ON2

.., (MID· A13
_ (MIO • A13

ON3
ON4
OFl
OF2
OF3
OF4

•
_
_
_
'_

AC);

NRO);

* NWR);

(NMIO • UPPER' NRD),
(NMIO * UPPER· NWR)i
(MIO • NA13 • NRC);
(MIO • NA13 • NWR);
(NMIO • NUPPER • NRC),
("",,10 • NUPPER • NWR);

ENCS

292040-9

Figure 9. ADF for COMCODE.ADF

OFFBEN (Off-Board Enable) requests permission to
access the off-board bus from the external bus arbiter.
The bus arbiter enables the off-board 'decoder via
AENI (Address Enable I) and CMDEN (Command
Enable). CMDEN allows the appropriate signal to go
high or low, and AENI causes the outputs to independently enter or exit a high impedance state (three-state).

Note the same name is used for both nodes of each
INPUT and OUTPUT macro call. Use of the same
name ensures proper connection when the Macro Expander eliminates redundant primitives (for example, a
CONF feeding another CONF).

4-60

inter

AP-312

Compiling the Design

The LOC then asks:

Proceed as follows to compile the ADF.
1. Include AP312.LIB in the IPLS environment variable. From the DOS command prompt, type:
SET IPLS= C:\IPLSII\AP312.LIB; ...
For user-defined macro libraries that are regularly
accessed, the IPLS variable can be set in an
AUTOEXEC.BAT file.
2. Invoke the iPLS II Menu by entering:
IPLS
3. Invoke the LOC from the Main Menu by pressing
.
4. Answer the LOC prompts as follows:
Input Format?

File Name?
COMCODE
Minimization?
Y
Inversion Control? N
LEF Analysis?
Y
Error Message File COMCODE.ERR

Do you wish to run under the above conditions
[YIN]?

Enter: Y
The LOC expands the macros and compiles the
expanded file to produce a JEDEC programming file
(COMCODE.JED), a utilization report file
(COMCODE.RPT), a minimized logic equation file
(COMCODE.LEF) and an error message file (COMCODE.ERR). For traceability, a file called COMCODE.SDF is created to show the expanded form 'of
the ADF output by the Macro Expander.
5. The LOC terminates execution with the following
message:
LOC cycle successfully completed
You can examine the LEF file to see the minimized
form of the design, The LEF shows the EPLD primitives used to implement the design. Macro calls are not
shown in the LEF. If you wish, you can also use LPS
(Logic Programmer. Software) to program a part.

4-61

Tools for Optimizing PLD Designs
Alan J_ Coppola
Tool Architect
Intel Corporation
" MIS EY2-11
5200NE ElaIll Youni Pkwy_
Hillsboro, OR 97123
(503)681-2177

Intro ductiOD:
The PUlPose of this paper is to describe a design methodology for
Programmable Logic Devices(PLD's) and to survey current PLD
optimization techniques.

In the modeling area, 'extensive 'simulations must occur before
and after the device is built, as each device is custom crafted
Finally, in the CAD to,olsarea, a highly functional, but hard to use
set of tools guide and control the whole process_ The tools are
the best m terms of functionality, but the worst in terms of cost
and ease of use_
,
,

1. Perspective: Where do' PLD's fit in?

The job of ASIC vendors in the next ten years is to make the
Custom/Semi-Custom problems disappear or become acceptable
to the logic designer of the next generation. The facts are clear_
Without advanced tools which automate much of the 10ilic
designer's work, the Custom/Semi-Custom approach only works
for large scale,large volume or special PUlPose devices. Silicon
compilers and other Custom/Semi-Custom design methodologies
are working hard to overcome the inherent problems of this type
of design.

The use of Programmable, Logic Devices(PLD's) represents a
middle ground in logic design. The two common approaches to
logiC implementation in today's market are Board Design
methods(building,a solution from a selection of pre-fabricated,
standard parts -Tl'L/SSllMSI) and Custom/Semi-Custom design
methods(fabricating a cUstom logiC chip to solve the problemat
hand. and.!liml buildinl! a much simpler board).
With the Board Design approach, PCB's carry the
fruit of a deSigner's labor to the customer. Many little black boxes
and other electrical circuit components make up the brunt of a
'PCB'sload. Many times there are large islands of functionality to
be connected together via encoding/decoding and timing circuits_
The islands of functionality (le. microprocessor, microcontroller,
RAM, EPROM, transciever, etc.) all have different protocols, and
all speak dlfferent languages at different speeds.

The use of PLD's in a design is a compromise between the
flexibility of a Custom/Semi-Custom design, and the standard
Board design methodolgy .
The definition o( PLD which I am using for the PUlPoses of this
paper is very Ileneral A Pr02rarnmable L02ic Device is any
device, which can be programmed by the user, to realize a chunk
of combinatorial or sequential 'logic. A subset of the most
popular, or newest types of PLD's are: PAL's, PLE's(Monolithic
Memories), EPLD'5(1nte~ Altera), EEPLD's(Lattice), FPLA~s,
FPLS's(Signetics), LCA's(Xilinx), and ERASIC's(Exel). All
except the last two are based on some form of two- '
level(AND/OR) registered array logic: I will mainly be concerned
with two-level array logic devices_

Integrating the major devices of a board together involves much
"glue" logic. The typical designer spends time and ettort looking
through a Tl'L parts catalog to find the best fit for a design based
on functiOnality, pertomJance and price. After a preliminary
function-based board is laid out, modification passes are made
based on the parts needed and their availability. Large designs
increase the length and risk of this process. Even though most
major CAD vendors are addressing the problem of board design,
simulation, test and interface with the Custom/Semi-Custom
arena, board design and manufacturing tools are rapidly becoming
the primary practical obstacle to effective production of end-user
systems. PLD's reduce the complexity of the end-user board,
hence reducing the length and risk of the implementation and
manufacturing proce55.
'

The good points of designing with PLD's are:
1. The integration of many small chunks of Tl'L and SSIIMSI
logic into a few PLDs. Essential for efficient use of resources.

2_ An easier overall development cycle than the Custom/SemiCustom route. Also easier than standard board Tl'L development
cycle once the learning curve is passed

With the Custom/Semi-Cu5tom de5ign approach, the designer i5
free to addres5 functionality directly. The designer has much
flexibility in the functionality, speed and integration facets of logic
de5ign. Certainly, the number of parts on an end-user PCB can
be greatly reduced by integrating most of a board's function into a
few custom devices. The problems aS50ciated with the
flexibility lie in the physical de5ign, modeling, and tOOl5 area5.
SpecificalJy, in the physical design area, problems include
process specific bottlenecks, NRE charges and long lead times.

3. Much cheaper than the Custom/Semi-Custom design
method for all butlarge volume designs_ Usually cheaper than
standard board Tl'L design method.

4. The breadboard character and modifiability of PLDs makes
them an excellent Il.&D and learning vehicle in the design
environment

4-62

inter
Question 1: 15 it easy to learn and easy to use ?(User-Prtendly)
Answer: The ADP language is made easier to learn for the

5. PLD CAD development tools are available to convert
standard TIL logic representations into the complicated fixed
architectures of an individual device. The CAD tools automate
this process, to a large degree, 50 that the user can use their own
design techniques.

novice user by two items:

a. Graphil21 lntcdacc Tools

Logic Bullder(LB): A graphical netlist entry and syntax
checking aid. to the user entering designs which have already
been written down on paper in a schematic fashion.

The bad points of designing with PLDs' are:
1. Por large designs, using PLD's is not as functional or robust
as using Custom/Semi·Custom logic.

2. The CAD tools available for PLD design are not as useful in
automating the whole design process as those in the
Custom/Semi-Custom arena In fact, most of the tools are
derived from those used in Custom/Semi-Custom design.
3. The speed and function constraints of the fixed device
architectures can be inhibiting. Por example, not all types of
designs lit well into two-level array logic.
2_ The PLD Development Environment
There are three pieces in a PLD development environment F'irst
is the input part The design specification needs to be entered in
some fann, such as a schematic,a finite state machine, or a high
level language description. Second is the processing part This
must include some kind of compilation of the input into object
code(JEDEC code), and usually also includes optimization of the
design. Third is the output part This includes the object
code(JEDEC), test results/Vectors, and statistics.

Logic Programming(LP): A graphicalJEDEC file editor;
which allows the user to modify the JEDEC Ille. More
importantly, the tool allows the user to investigate and learn the
device architecture via a user-oriented graphical interface, and
then to program the part directiy from this interface.
O. Primjti~·c5:
A large(N80) set of logic and 110 Macrocell primitives which
capture all of the current standard ways to represent small chunks
of memory and combinational logic. This is useful for the novice
and occasional user, who doesn't have the time, or want to learn
the abstractions involved in more generic HDLs'.
Question 1: 15 it generic enough to support the current
applications and new devices yet to come' (HDL expressiveness
and functionality)
Answer: Yes, it is generic enough to support those current
and future architectures based on two-level registered logic,
which are produced by Intel and Mtera The large number of
primitives make the language unwieldly for support of new
devices not fallir.g into this realm. F'inaJiy, it supports only Intel
and Altera devices.

A PLD development environment has an underlying language for
representing design specifications, which is usually more general
than the intended devices. Often, the system provides means for
accepting input in other forms, which then translates into the
underlying language. We shall use the standard term "Hardware
Description Language"(HDL) when refering to this language, as
!tns is where these languages are heading in terms of complexity
and future directions.Examples of PLD HDLs' are ABEL by
Data/IO-F'uturenet, CUPL by Assisted Technology, ADP by.
Intel(Altera), PALASM by Monolithic Memories, LOG/lC by
Kontron, and AMAZE by Signetics.

Question 3: Does the compiler use optimization techniques to
produce JEDEC code? (Le. logic minimization)
An5wer: Yes, logic minin1ization, DeMorgan's inversion of
outputs, and automatic fitting of resources arId pins to the given
device are supported in an integrated fasrnon.
Question 4: Are there alternate logic entry tools, like schematic
capture and F'inte State Jv!achine entry; are !t,ere hooks for
simulation and other design methodologies, like gate arrays?
An5wer: Alternate enrty methods include schematic capture,
PSt·! entry, and Graphical Netlist entry(LB). Tl)ere are currently
no tools for functional simulation, nor is ther any way of
interiacing to other design tools. Both topics are being
considered for !t,e future.

There are four questions one can ask about a PLD development
environment and it's HDL. The answers to these questions
determine, for the user, which systems to use. The four
questions are:

The third party HDLs',like ABEL, .CUPL, and LOG/IC are, in
general, harder to learn and use ..They afford greater
expressivness and generality in addressing design problems.
Because of the need towork with most devices on the market,
these HDL's resemble more closely their high-power cousins in
!t,e Custom/Semi-Custom design arena. They have no automatic
resource fittir.g and pin-assignment, but do have a robust set of
integrated tools involving functional Simulation, schematic clay, 1985,

Portation of Custom/Semi-Custom Tools:
Available ideas rea,jy for portifJg to the PLD environment down
the HDL path include inIplementing a subset of VHDL(VHSIC
Hardware Description Language)[5]; and having the compiler
produce an EDlP(Electronic Design Interchange Pormat) [6]
intermediate format In this, way, interfacing with othertoolboxes
of any type wHlbe easier. Ne''''' device support will also be'easier,given the generic nature of VHDL, Using VHDL would also
standardize an HDL,
alia ..., desiiners to learn' one HDL :.
wruch will last for a long tirl1e., Also, PLDtools Wruch inteifac~',
with theCustornlSemi·Custom toolset involving board desigr~
testing and manufacturing IS needed now, and is being addressed
by the major CAD vendors, Standardizatior,like VHDL and·
EDIP will, eventually, lower the cost of these interfaces,

[2] M,R. Dagenais, V,K. Agarwal and N.C. Rumir~ "McBoole: A
New Procedure for Exact Logic Minimization", IEEE Trans. on
CAD, JarL 1986,229·238,
[3] H. Bartholomeus and H.D, lvfar~ "Presto·lI: Yet Another
Logic Hinimizer for Prograrnmed Logic Arrays", Proc, Int Synlp.
Circ.Syst., JWIe 1985,58.

and

[4] R. Rudell, "Multiple·Valued Logic t.1inirnization for PLA

Synthesis", HS. Thesis, University of California, Berkeley, 1986,
D. Agrawal, ed., "VHDL: The VHSIC Hardware
Description Language", IEEE Design arId Test of Computers,
Apri~ 1986,
[5] V,

The new logic minimization algorithms, like Espresso, and new
state assignment tOOls, like KISS[7] arId STASH [8]can be used in
the PLD envirOrtlTlent The algorithms arId methods of tools
involving placement and routing em be applied to the fitting/pin
assIgnment problem, On the logic s\'I1thesis side, new tools
which combine expert·systems with multi-level logic optimizatIon
can be applied to PLD de1lices wruch allow multi·levellogic to be
easily implemented.

[6] JP. Eurich, "A Tutoriallntroctuction to the Electrorric Design

Interchange Pomlat", In Proc. of 23rd Design Automation
Conference, July, 1986, 327-333.
[7] G, DeMichel~ R.K. Braytor~ and A, Sangiovanni·Vincentelli,

"Optimal State Assignment for mte·State lvfachines" IEEE
Trans, on C/l.D, July, 1985, 269·285.
'

The key poin~ imgardless of the actual tools from the
Custom/Serrri-Custom arena wtrich are productized is that the
user have an essentially transparent view of any new optimization
tools,
'

[8] A. J Coppola, "An Implementation of a State Assignment
HeuristiC", In Proc, of 23rd Design'Automation Conference, Julv,
1986,643-649.
.

Once a PLD is manufactured, the functionaliW cannot be
changed. This fact leads to the belief that tools can be created
which map logic, which 15 too big or too slow, into multiple
devices by doing ,3Ufomatlc logic partitionirJg, The converse
problem of fittirJg multiple chunks of communicating logic into one
device may also be addressed, Tools to fit multiple state
machines into one de'Jice, or to p,:.rtition a schematic or PSt.l into
two or more devices is a· first step, Por example, the Dice
Example(PJgures 1-3) has three small state macrunes, which are
mtegrated into one device and design file, Expert·s~;stems can
capture the rules for partitioning, and the database of all allowable
devices, while optumzation techniques can make the expert·
systems \')Qr~: ·j,5 weU as, or better than a logic designer.

4-65

Th. Oico Example shows the usefuln.ss ,of logic minimization.
Figu.o 2 shows lIIe FSM Languag.(Stato· M.... hin. Filel
,oores.ntation of the Dico Examplo under 1110 ,iPLDS .ystom.
Figure 3 shows 1110 AOF code which rtsuhed., as an intorm.diato
stoP. in III. compilation proco.s. '

Dice Example Description
Probl.m: O.sign a ci,cuit lIIat,wili rolllWo dic •. ,Push a .witch 10
stan III. dic. ,ollil)g. Wh.n.llle switch is ,eleased, .;i (pseudol
of numb.,s will b. di.play.d.
"
,andom

.ot

"'"'ot

Th ••ximpl. i. written u.ing III. FSM compil., modul. ofiPLDS.
This oxampl. i. a modification of ,an flIisting Application NDII![AP- ,
279] design. which is wrill.n in AOF language.
" .
The Dice Exampl. ps."do-randoinlv '011., ~o dice. Tho Oic.
Example is composod of'lIIre. FSMs'. The fi,st 1W0 'are .ss.iitiall~' '
up-count.,s, which count Irom on. to six. using 1110 notation groups
of one D' 1W0 LED's. Io,'each 01 lou, outputs. to ,epresent the six
faces 01 a dio., A pictu,o which indicatos lIIe LED g,ouping. by
listing the output signal'naine next to III. LED controll.d by ~ is
given in Diag,im 1: Th. g,oupings,lo, bolll di. a,o id.iitical and
".nc.; list.d next to .ach' otho,.
", '
. , ..

Tho
d.~ice. 'IIio 5COSo.has lSI/ii m~rocells. bUt .ach
macrocoll has only onough room fa, a p-tonns. 'Th... aro 11
oQuation.lllat .osult from the Dieo Examplo dosign .• Fou. lor 'each
die. to controlllle LED's. and lII..e Irom III. stato variabl.s of III.
Uno", Foodback Shift Rtgisto... ,
Wo p... ~nt a ~~ro'and after minimization tabl!. showing lIIe~ct
of,III0 ",i~imizatio,:, and III," a~matic OIMorgan'. Inversion stop'.

Equation,

Th. lIIi.d machino gono.at.s a short psoudo-random bit sOQunc. by
imp!omenting a Uno", F.edback Shift Rogister(LFSRI • with thre.
,.glsto.s. The ps.udo-random bit s'Qu.nces Irom tho LFSR ,art
us.d to add p.obabilistic transitions to 1110 up-count•• modol of
..ch di.. The implem.ntation of 1110 LFSR is by straight
memorization of the sl'qu'ence. bv means of the state variablf's' of an
up-counter.
.

Ib,~2b

Id,2d
Ie, 2c

e e
eee
e
la; Za

Ie, Zc

20.d

Zb.d
Za.d
Id.d
Ic.d
Ib.d
,b.d

Dice LID Encoding

"npuis

3
' .. 3
3

Sv3.d
Sv2.d
Svl.d
2d.d

6
6
6
" ,6
6
6'

p-torms p-tonns
bolo.. alit.
min
min·

3
3
,3
3

•

S
·,10
3
9

5
10

2
2
2

..3of
6

3
of
of
7,

A,noc ...ary 'condition to fit:intti,the 5Ca60 i.'lIIat all of 1110 numbers
in tIlo. last column be no mo •• lIIan B. as th.r. are no mo.o lIIan B
p-l.rms conn.cted,1o 'anv macrocoll. This particular arobl.m took Z
minute. of CP,U tini~ on
aMhz PC/AT. Rtducing'lIIeso oQuation.
by hand, ouon lor lIIis' simp/.' exampl•• would bo difficult, Tho nood
10. iIIe aUtomatic minimizer is 'cloar in this ••ampl.. ,Without it, a
d.sign., would eilll •• hav. to r.due. tho eqations r.sulting Irom 1110
FSM Languag., bv hand. Dr nol use an FSM Languag. al
and do
lIIe whole design using hand-;cralltd molllod,s.
.

Id,2d
Ib,Zb

aI'"

Die 1 Signals: la, Ib, Ie, Id
Die ZSignals: Za, Zb, Zc, Zd

figure L
!,

4-66

Dice Example
FSM Language(SMF) Description

X .

SIal. variables are used as outputs 10 d,e.
Each st.", encodes the sel of LED's 10 lighl
10 realize thaI die valuo.
X

Alan Coppola
In"'l
Jul~ 21, 1986
Pan No.: LasVegas
V.r.3.0
5C060
Roll a pair of die
LB Version 4.01. Baseline 27.1 4/9/86
PART: 5C060

STATES: [1alb Ie ld]
Resel
[0 0 0 0]
Dn.
[1000]
Two
[0 1 0 0]
Three
[1 1 0 0]
Four
[0 1 1 0]
Five
[1110]
Six
[0 1 1 1]

X No pins assigned:
Automatic Pin Assignmenl and Filling X

Coin2 is a. pSl'udo-random coin. which controls the
ulHlounler transitions. so thaI the dice roll is
pseudo-randDm.

INPUTS: elkl. clk2. Go
DUTPUTS: 1.. lb. Ie. ld, 2.. 2b. 2c, 2d

Resel:
If Go Then
. Dn.:
If Go.Coin2
Two:
, H Go.Coin2
Three:
If Go.Coin2
Four:
If Go.Coin2
Five:
If Go.Coin2
Six:
If Go.CoinZ

NETWORK:
clkl = INP(clk1)
clk2 = INP(clk2)
Go = INP(GD)
X
.
.
Throe lerm LFSR. implemenled bv sloring sequence
in stale variables. which act as flipping coins.
X
MACHINE: LFSR
CLOCK: clk2
STATES: [Coinl Coin2 Coin3]
SO
[000]
SI
[100]
S2
[110]
S3
[011]
84
[101]
S5
[010]
S6
[001]
X
Stat. equations are:
Coin2 := Coinl
Coin3 := Coin2
Coinl := /(Coin2 lCDr Coin3)

One
Then Two
Then Thr ••
Then

·Four

Then

Fiu.

Then

Six

Then One

MACHINE: Oie_RoIU

"
"

Duplieale of Dio_RoIU machin., .xcepl for

- a different die, using a differ:ent pSll!ludo,-random com.

SO:
SI
SI:
S2
S2:
S3
S3:
S4
S4:
S5
S5:
S6
S6:
SO

CLOCK: elk2
STATES:
ReselDie2
OnoDi02
TwoDi02
ThroeDie2
FourDie2
FiueDie2
SixDie2
Re ..tOie2:
If Go.Coin3
On.Die2:
If Go.Coin3
TwoDie2:
If Go.Coin3
Thre.Di.2:
If Go.Coin3
FourDie2:
" Go.Coin3
Fi.eOie2:
If Go.Coin3
8i.OieZ:
If Go.Coin3

MACHINE: DieJ\olU
CLOCK: clkl

ENDS

Figure Z.

4-67

[2a 2b 2c 2d]
[0000]
[1 000]
[0 1 0 0]
[1 1 0 0]
[0 1 1 0]
[1 1 1 0]
[0 1 1. 1]
Then OneOie2
Then T",00ie2
Then ThreeDieZ
Th.n FourDie2
Then FiveDie2

Then SixDieZ
Then Oneo;e2

inter
Dice Example
Hardware Description language(ADF)
AIUI Coppola
Intel
July 21, 1986
Pan No.: LasVegas
Ver.3.0
5C060
Roll a pair of die
LB Version 4.01, Baselin. 27.1 4/9/86
SMV Version 1.01 BETA2 Baseline 26.1 4/3/86
PART: 5COSO
INPUTS:
elk1, clk2, Go

Current Slate Equations for "Die_RolLi"
X

~~~e~ ~ ~:;~~~;:!:;~~~';
Two = 10'.1 bll c·.1 do'·
Three = 1a.lbl lc'IId';
Four = la'llb.lc"ld'·
Fi.e = h"lb"lc.ld'; ,
Six = la'llbl lc.ld;
X

OUTPUTS:
b, lb. Ie, Id, 2a, 2b, 2e, 2d
NEnoIORK:
elkl = INP[elk1)
elk2 = INP[clk2)
Go = INP[Go)
X

Three tenn LFSR, implemented by storing sequence
in stato .ariables, which act as flipping coins.
X
X

I/O's for State Machine "LFSR"

SV Oefining Equations for State Machine "Die_Roll_I"
X
h.d = One.n + Three.n + Fi.e.n;.
1 b.d' = One.n + Reset.n;
IC.d = Four.n + Fi.e.n + Six.n;
Id.d = Six.n;
X
Next State Equations for State Machine "Oie_RoIU"
X
One.n = Six I Go I CoinZ + One I (Go I CoinZ)'
+ Reset I Go;
Resel.n = Reset I (Go)';
Three.n = Thre. I (Go. CoinZ)' + Two. Go I CoinZ;
Four.n = Four. (Go. CoinZ)'
+ Three. Go • Coin2;
Fi.e.n = Fi.e • (Go. Coin2),
+ Four. Go • CoinZ;
Six.n = Six • (Go. CoinZ),
+ Fi.e • Go • Coin2;
X

Coinl = NORF(Coinl.d, elk2. GNO. GNOJ
Coin2 = NORF(Coin2.d, elk2, GNO, GNO)
Coin3 = NORF(Coin3.d, elk2. GNO. GND)
X

I/O's for State Machine "Die_RolLi"

S5 n = S4'
S6:n = S5;
X
Boolean Equations for State Machine "Die_Roil_I"
X

10, 1a = RDRF(1 a.d, clkl. GND, GND, VCC)
Ib, Ib = RORF(1b.d, elk!, GND. GND. VCC)
I c, Ie = RORF(1 c.d, clkl, GNO, GNO, VCC)
Id, Id = RORF(1d.d. clkl, GNO. GNO. VCC)
X

I/O's for State Machine "Die_RoIU"
X
2a, 2a = RORF(2a.d. clk2, GND, GNO, VCC)
2b, 2b = RORF(2b.d. clk2, GND. GND. VCC)
2•• 2c = RORF(2c .d. clk2. GNO, GNO. VCC)
2d. 2d = RORF(2d.d. clk2, GND. GNO, VCC)
EQUATIONS:
X

Boolean Equations for State Machine "LFSR"
X
X

Current State Equations for "LFSR"
X
SO = Coinl'ICoin2'ICoin3';
SI = Coin!.CoinZ'.CoinJ';
SZ = Coinl l Coin2 l Coin3';
SJ = Coinl'ICoin2"Coin3;
S4 = Co'lnI I Coin2'ICoin3;
S5 = Coinl'ICoin2 l CoinJ';
S6 = Coinl'ICoin2'ICoinJ;
X
SV Oefining Equations for State Machine "LFSR"
X

Coinl.d = SI.n + S2.n
CoinZ.d = S2.n +S3.n
Coin3.d = S3.n + S4.n
X
Next State Equations for

+ S4.n;
+ S5.n;
+ S6.n;

Boolean Equations for State Machine "Die_RolI_2"
X

X
Current State Equations for "Die_RoILZ"
X
ResetDieZ = 2a'.Zb'.2c'IZd'·
On_Die2 = 2aI Zb'12c'.Zd'; ,
TwoDieZ = 2a'.2b I Zc·.Zd'·
ThreeDie2 = Za.2b.2c'"2d:;
FourDie2 = 2a'.2b.Zc.Zd';
Fi.eDi_2= 2a.2b.2c.2d'·
SixDieZ = Za'12b.2c.2d; ,
X
SV Defining Equations for Slale Machine

OneDieZ.n = SixOi'.Z I Go • Coin3
+ OnoDieZ • (Go • CoinJ),
+ ReselDieZ • Go • CoinJ;
ResetDie2.n = ResetDieZ • (Go. CoinJ)';
ThreemoZ.n = ThreeOieZ • (Go. CoinJ)'
+ TwoOie2 - Go • Coin3;

FourDie2.n = FourDieZ • (Go • Coina),
...

Thflt~Dio2 If

Go • eoin3;

Fi.oDi.Z.n = Fi •• moZ • (Go. Coin3)'
+ FourDi.Z • Go • Coin3;
SixDi.Z.n = SixDi.2. (Go. Coina)'
+ Fi •• DieZ » Go • Coin3;
ENOS

State Machine "LFSR"

SI n = SO'
S2:n = SI;

~::~ ~ ~~~

"Die_RolI~Z"

2a.d.= OneDieZ.n + Thr.eDie2.n . + Fi.eDieZ.n;
2b.d' = OneDieZ.n + ResetDieZ.n;
2c.d = FourDie2.n + Fi.eDie2.n + SixDie2.n;
Zd.d = SixDie2.n;
X
~ext Stale Equations for Stale Machine "Oie_RolI_Z"

Figure 3.

4-68

Appendix

EPLD THIRD· PARTY PROGRAMMING SUPPORT*
Company

Model

Type

Adams/Macdonald P11
Universal
Enterprises
(Promac)
Sprint Plus Universal
Data I/O

29B

. 40

Module

Adaptor

DevIces Supported

PA-1

5C031,032,060

5C031 , 032, 060

5C090,121
Universal .LogicPack 303A-010 V.2
5C031,032,060,5AC312
V.4
303A-011AV.7
303A-01 1B (PLCC) 5C060
Universal

Chipsite (PLCC)

5C031 , 032, 060, 090, 121
5C060, 090, 180

60AlH

Logic

5C031,032,060

Unisite

Universal

Site 40

5C031 , 5C032, 5C060, 5C090,
5C121,5AC312
5C090, 180

803-LDC

PLD

803-DP5

Logic

Kontron

EPP-80

Universal UPM/B
UPM/C

Oliver Advanced
Engineering·

Omni64

Universal

Stag

ZL30
ZL30A

Chipsite (PLCC)
Digelec

5C031 , 032, 060
5C031,032,060, 090, 121

5C031 , 060, 121
5C031 , 060,121

OM-S-20 LCC
OM-S-24 LCC

5C031
5C060, 090, 121

Logic

5C031, 032, 060

Logic

30A640

5C031 , 032, 060
5C031,032,060, 090, 121,180

5C031 , 060

ZL33

Gang

PPZ

Universal ZM2200

'Clalmed by the manufacturer to support the listed devices. Not qualified by Intel.

5-1

5C031,032,060;090, 121

PLA TO EPLDREPLACEMENT
Already in wide use throughout the electronics industry are numerous different Programmable Logic
Devices. Many of these are PALs from MMI. Currently,two of our EPLD products, the 5C060 and
5C031 can functionally replace most 24-pin and 20pin PALs, respectively. A third product, the 5AC312, ,
with its architecturally, advanced features, can re- .
place most designs usirig'more complex PALs such
as the 20RA10, 22Y10, and 32V10.

The5C031
The 5C031 is a direct, drop-in replacement for most
20-pin PALs, although some PALs have an incompatible architecture.

The 5C060
The 5C060 is NOTa drop~in replacement for any 24- ,
pin PAL, though it can functibnallyreplace most. The
reason for this is that pin 1 is used as the main clock
on registered PALs and as an input on non-registered. Also, pin 13 is used'as an OE line on some
PALs, and as an input on others. The 5C060, however, uses pin 1 as the left-h'alfsynchronous clock in- ,
put and pili 13 astheright-halfsynchronOl~s clock,
input.
.
While that may not beaproblem in some PAL designs, those designs that require clocking or inputs
on pins 1 or 13 will' necessitate hardware modifications. In the caseofthe registered PALs, the connection to pin 1 must be rerouted to pin 13 and the
OE connected to one of the available inputs' (if
used). In this manner, the 5C060 can functionally
replace the PAL.

,
'
'
,

. 'The 5AC312

5C031/5C032 As a 20-Pin PAL Replacement

10H8, -2
12H6, -2
14H4, -2
16H2, -2
10L8, -2
12L6, -2
16L8, A-2, A-4
16R4, A-2, A-4
14L4, -2
16L2, -2
16R8, A-2, A-4
16R6, A-2, A-4
16P8, -2
16RP8, -2
16RP6, "2
16RP4, -2
16V8
These are
25 ns-45 ns PALs;

16R6A
16R4A
16L8A
16RP6A'
16RP4A
16P8A
16R8A
16RP8A

"These are
15 ns PALs.

5COGO As a 24-Pin PAL Replacement
',Modified
Replacement
12L10
14L8
16L6
18L4
20L2
20L10, '
20L8
20R8
20R6
20R4
,20RA10
" With, hardware
modifications

The 5AC312 is a direct, drop-in replacement for the
20RA10 as well as many of the other simple 24-pin
logic devices. The 5AC312 can also serve as a dropin replacement for most designs using the 22V10 or
32V10 devices.

Functionally
Compatible

100%
Compatible

Functiona"y
Compatible
20L8A,
20R8A
20R6A
,20R4A
"

These are
15 ns PALs.

5AC312 As a 24-Pin PAL Replacement
100%
Compatible
20L8
20R8
20R6
20R4
20RA10

5-2

100%
Compatible
(Qualified)
22V10
32V10
Dependent on the
number of product
terms used.

ORDERING INFORMATION
Intel EPLDs are identified as follows:

'-.,,-J '-.,,-J

X
)

Device

Speed

Technology
C

-CHMOS

AC -

Advanced CHMOS

Package Type
A

Hermetic, Pin Grid Array

Hermetic, Type D (Cerdip) Dip

Plastic, Leaded Chip Carrier

CJ -

Ceramic, J Leaded Chip Carrier

Plastic Dip and Plastic Flatpack

Hermetic, Leadless Chip Carrier

-.Unpackaged Device

+ 125°C)

A -

Indicates automotive operating temperature range (- 40°C to

J -

Indicates a JAN qualified device, but is for internal identification purposes only. All JAN devices must
be ordered by M38510 part number. (Example: M3851 0/42001 BOB), and will be marked in accordance with MIL-M-38510 specifications.

L -

Indicates extended operating temperature range (- 40°C to
± 8 hrs. dynamic burn-in.

M-

Indicates military operating temperature range (- 55°C to

+ 85°C)

express product with 160

+ 125°C)

0 - Indicates commercial temperature range (O°C to 70°C) express product with 160 ±8 hrs. dynamic
burn-in.
T -

Indicates extended temperature range (- 40°C to

+ 85°C) express product' without burn-in.

No letter indicates commercial temperature range (O°C to 70°C) without burn-in.

Examples:
OD5C060-45 Commercial with burn-in, cElramic Dip, 060 (600 gate) device, 45 nanosecond.
'On military temperature devices, B suffix indicates MIL-STD-883C level B processing.

5-3

Device Feature Comparison
SC031

SC032

SC060

SC090

SC121

INPUTS
Dedicated
Maximum
Input Latches

10
18

4
20

12
36

12
36
Y

12
60

I/O
Number
Tri-State
Programmable
Polarity

8
Y
Y

16
Y
Y

24
Y
Y

MACROCELLS

REGISTERS
Number
Types

D/TI

RS/JK

Y
Y
Y

Y
Y
Y
Y

. 112 .

200

394

Buried Reg. S
Preload
By-Pass
Reset
Preset

PRODUCT TERMS
Number
Sharing
Variable Prod.
Term Distribution

Y
Y
.• Y
Y

Y
Y
Y

160

Y
Y
Y

240

LOCAL/GLOBAL BUSSES

2
Y

CLOCKS
Asynchronous
Clocking
Programmable
Clock Edges
SECURITY BIT
TURBO BIT
(LOW POWER)

2
Y

4
Y
Y
Y

SC180 ·5CBIC

5AC312

5AC324

8
' 16
Y

10
22
Y

12
36
Y

48
Y
Y

32
Y
Y

12
Y
Y

24
Y
Y

236
Y
Y

480

4
Y

2
Y

Y
Y

5-4

ELPD CUSTOMER SUPPORT
Transmit/receive protocols supported are:

Hotline

ASCII
XMODEM
KERMIT
TELINK
Cyclic Redundancy on XMODEM

The Intel EPLD Technical Hotline is manned by application personnel from 8:00 a.m. to 5:00 p.m.
(PST) every business day. The number for the United States and Canada is 1-800-323-EPLD (1-800323-3753). Outside of the U.S. and Canada, contact
your local Intel Sales Office. The Hotline is provided
to assist with technical questions concerning Intel
EPLDs.

EPLD Customer Design
Support Center
Intel has a Customer Design Support Center to help
customers who are implementing EPLD designs.
Service includes answering questions, device selection assistance, and design partitioning as well as
limited prototyping, and product/design evaluation
and implementation. For more information on the
Design Support Center, contact your local Intel field
sales office.

BBS
Intel has a Bulletin Board System for registered iPLS
and iPLS II customers to electronically transfer information. Any registered person with a modem can log
onto the system. The current number is (916) 9852308. If your communication software supports file
transfers, you can receive utilities, software updates,
and the latest information on EPLDs via the Bulletin
Board.
Data format for the BBS is as follows:
Start Bits: 1
Stop Bits: 1
Data Bits: 8
Speed:
300 or 1200 BAUD

5-5

COMPATIBLE COMPUTERS FOR iPLDS II
A partial list of computers that have been verified to be software compatible with the Intel Programmable Logic
Development System (iPLDS Ii) is given below:
. . .
AT&T 6300 and 6300+
Compaq family of pes (88, 86, 286, 386)
IBM AT
IBM XT
IBM XT-286
IBM Personal System II Model 30
HP Vectra
Sperry IT
Tandy 3000 HD
...
The IBM Personal System II Models.50, 60, 70, and 80 can run iPLS II (Intel Programmable Logic Software)

5-6

inter

DOMESTIC SALES OFFICES

ALABAMA

GEORGIA

NEW MEXICO

~~~I~~ord Dr., #2

l~~'~~~ Parkway

1~m81 ~~i,1I Boulevard N.E.

Huntsville 35805
Tel: (205)830-4010

Suite 200
Norcross 30092
Tel: (404) 449-0541

ARIZONA

NEWYOAK

IUINOIS

l\~~~~8tnOr.
Suite 0-214

Phoenix 85029
Tel: (602) 669-4980

t\n~1 rroErDoradO Place
Suite 301

Tucson 85715
Tel: (602)299-6815
CAUFORNIA

tlntelCorp.

21515 Vanowen Street
Suite116

¥~~(ala8r~~~~
~JgI ~~Perial Highway

mte~~~~rt:nBa'e Road, Suite 400

b1~~~'t~~s
Office Park,
Fairport 144

INDIANA

1~~1 ~u~~e Road

Suite 125

~gJ~~~~21i~

IOWA

Suite 130

~~~(am~~t=
Intel Corp.

193051. Andrews Drive N.E.
2ndAoor
Cedar Rapids 52402
Tel: (319) 393-5510

tlntel Corp.

~~~~a~~~ro~~61~UIle 101

Tel: (916) 920-8096

tlntelCorp.
10985
Suite 1
Overland Park
Tel: (913) 345-

Suite 105

tlntelCorp."
7321 Parkway Drive SouthSuiteC
Hanover 21076

tlntelCorp."
400 N. Tustin Avenue
Suite 450
Santa Ana 92705

~~~~~b?i6~?'S:4
tlntelCorp.
Drive

~lg~~~~~
FAX: 408-727-2620

COLORADO

1-1020
UASSACHUSETIS
tlntelCorp."
Westford Corp. Center
3 Carlisle Road
2nd Floor
Westford 01886
Tel: (508) 692-3222
TWX: 710-343-8333

m~I~~Park Drive

MICHIGAN

~1:(7a,~ ~~~~~7

tbni~I~Ward Lake Road

Suite 100

~i~el~ St., Suite 915
~~b-~i'~869
CONNECTICUT
tlntelCorp.
26 Mill Plain Road
2IldFIoor

Suite 100
West Bloomfield 48322
Tel: (313) 851-8096

Bloomin~on 55431
Tet: (612 835-6722

TWX: 91 576-2867

Suite 131

Suite34D
Orlando 32822

~~~"tJj-~!~~

lintel Corp.
1300 4th Street North
Suite 170
Sl Petersburg 33716

~r:lf;i~ff Road

~~~ ~4~O Freeway
Houston 77074
Tel: (713) 988-8086
TWX: 910-881-2490
UTAH

l~Je~~rC4oo South
Suite 104

~ej~;bl'f~:8051
VIRGINIA
tlntelCorp.
1504 Santa Rosa Road
Suite 108
Richmond 23288
Tel: (804) 282-5668
WASHINGTON
tlntelCorp.
155108th Avenue N.E.
Suite 386
Bellevue 98004

~~~~~C:062

~:I'~:8r9~77~~8022
~nJ~1 ~a~rf6enter Drive
Suite 220
Dayton 45414

~~~J~~9Jo.5li208

!~ni~%~~ce Park Dr., Suite 100
Beachwood 44122

~~Jn~S:/:le68

WISCONSIN

!~nJ~.~x~Cutive

Dr.
Suite 102
Brookfield 53005
Tel: (414) 784-8087
FAX: (414) 796-2115

CANADA
BRITISH COLUMBIA
Intel Semiconductor 01 Canada, Ltd.

~~fl~~~oadway

Suite115
Oklahoma City 73162
Tel: (405) 848-8086

~~~~a~~n.Jf& ~L~' Suite 202
Tel: (604) 298-0387
FAX: (604) 298-8234
ONTARIO

OREGON

FLORIDA

t:rJgl~~lea Blvd.

~~?l~l-;3t~~

MINNESOTA

~gl~~~h St.. Suite 360

MISSOURI

~J!~:~~ ~o;uitaloo

t~nJ3llx~~tive

Center Dr.
Suite 105
Charlone28212

tlntelCorp."

OKLAHOMA

$l2*b!~~\~
Tal: (305) 771-0600
TWX: 510-956-9407
FAX: 305-772-8193

tlntelCorp."
12000 Ford Road
Suite 400
Dallas 75234

OHIO

770

t'o'oeo",
..
an Tomas 4
2700 San Tomas Expressway
2nd Floor
Santa Clara 95051

t!.~~~;arg~siness Centor
~~!~',~_~~~~~~

MARYLAND

~J{b-S:5~~

Islandia 11722
Tel: (516) 231-3300
TWX: 510-227-6236

NORTH CAROLINA

mgl&<'~utiveDrive

¥:I~ (~~~o4~~~liao

~J6J&~~;sway Dr., South

Bldg. 00, Route 9
Fishkill 12524

KANSAS

!~nJ~.~~g&rsOll

Lane
Suite 314
Austin 78752
Tol: (512)454-3628

~~~~"~~U-~~b

~~1~\~llm1

Suite 218

~~~~r~)d~~O

Suite B 295

~~~:U(~~~~2~JJ~

TEXAS

l~J~I&,,~~'City Expressway

~:rr3?~r2~~~90
NEW JERSEY

lM¥~~~~re:

Greenbrier Parkway
BUildingB
Beaverton 97006

~~~r~t7-:aoi;,
PENNSYLVANIA
tlnteICorp.455 Pennsylvania Avenue
Suite 230

~~r (~a~h~~~~~034
TWX: 510-661-2077

tlnteiCorp:
Parkway 109 Office Center
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747-2233

!~~~c,o~rate

Center
75 Uvingston Avenue
First Floor
Roseland 07068

~~f~dg!~1~

tlntel Semiconductor of Canada, Ltd.
2650 Queensview Drive
Suite 250
Onawa K2B 8H6
Tel: (613) 829-9714
TLX: 053-4115
tlntel Semiconductor of Canada, Ltd.
190 Attwell Drive
Suite 500
Rexdale M9W 6H8
Tet: (416) 675-2105
TLX: 06983574
FAX: (416)675-2438
QUEBEC

Intel Corp."
400 Penn Center Blvd .• Suite 610

t~J~t~~h~o~g~~~~r~ Canada. Ltd.

~~~:s~1Ijt81~~70

Pointe Claire H9R 3K2
tel: (514)694-9130
TWX: 514-694-9134

PUERTO RICO
tlntal Microprocessor Corp.
South Industrial Park
P.O. Box 910
Las Piedras 00671
Tel: (609) 733-8616

~~!~"~~ra:~u~

tSales and Service Office
'Fleld Applicatidr). Location

CG/SALE/ll1088

inter

EUROPEAN ·SALES OFFICES

DENMARK

WEST GERMANV·

ISRAEL

''''

Intel·

'P.O.
' ' '.

SPAIN

AtJdlm Industrial Park·Neve Sharet
Box 43202
TeI·Aviv 61430

Glentevej61,3rdFloor

~F~~

· Tel: (972) 03-498080
TLX:311215

FINLAND

Intel

InlBl

ITALY

3000 Hannover 1 .

Intel"

Hohenzorlem Strasse 5

Ruosllantle2

00390 Helsinld

~~~~f3440Bl

FRANCE

InlBl
Abraham Lincoln Struse 16-18
6200 Wiesbaden

.:;:~~~544 644

SWEDEN

Mllanoftorl Palazzo E
, , . 20090 Assago
Milano

· ~~,'3l~824"'71

:;:~~2\g:1~J7605-Q

NETHERLANDS

Intel

~~~:~~

0100
SWITZERLAND

Inter

Ri!~2~407.11.11

UNITED KINGDOM

Intel"

NORWAY

Intel

Hvamveien 4-PO Box 92

2013Skjetten

+M~~~ 8.. 420

EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA

WEST GERMANY

'UNITED kiNGDOM

NETHERLANDS

Bacher Electronics G.m.b.H.
Rotenmuehlgasse 2S
1120Wl8n
:;:~~,'m2) 83 66 46.Q
. BELGIUM

~s:t~u;o~ntGmbH

Inelco Belgium SA.
A'I. des CiW: de Guerra 94
1120BruxeIIes

=:.n~~~.:'lr~nts Ltd.

Letchworth, Harts SOS tTL

+lli~Jl':f'''''''
NORWAY

Bahnhofstrasse 44

(N""",I"S

~h~~r,lk9

Jennyn

~~~:r

PORTUGAL

DENMARK

DI1ram
Avanida Marques de Tomar, 4s.A

l000Usboa

m~~V~)734834

Sevenoaks
Kent TN14 SEU
~~~,<'y:32) 450144

MMD

Unit 8 Southview Park
ATD EIectroNIca. S.A.
Plata Cludad de Viana, 8
28040 Madrid

OYFintronlc'AB

, Melkonkatu24A
00210 Helmkl

+~~m\,"l-

, FRANCE

Caversham

· SPAIN

F1HLAND

~~~Jr~4000

IRELAND

,21-3

Generim
Z.A. de Courtaboeut
Av. de 18 Baltlque-BP 88
91943 Las Ulis Cedex

=~~reRG4OAF

~~=r)481666
RapldSUicon
Rapid House
OenmarkSIraet
High Wycombe

BUck1~hamshire HP11 2ER

llic~ed~r) 442268
SWEDEN

+li~m,l\,. C1178 78

ISRAEL

,NontiskEleklrOnlkAB

EastronlcsLtd.
11 RozanisStreet

9770

P.O.B.39300
TeI..A.'IIv61392

YUGOSLAVIA

~~~75151

SWITZERLAND

ITALY

IndustracleA.G.
Hertlstrasse31
8304 Wallisellen

~~(~~7C:1)83OS040

Rapldo EJectronlc Components S.p.a,'

~ia=-,8
ltalla

+~~=~/360SSS

TURKEY

Tekelec-Airtronic
Rue Carle Vemet - BP 2
92315 Sevres Cedex

EMPAElectronlc
Undwunnstrasse 95A

~~,=S347535

8000 Muenchen 2

~~~F80570

+~2~440012

CGfSAlEJ111088

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:03 13:57:06-08:00 Modify Date : 2013:08:03 14:35:37-07:00 Metadata Date : 2013:08:03 14:35:37-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:3cccca92-aed6-0249-aa00-ad698456e466 Instance ID : uuid:9fda62ec-9e0a-f244-bbf5-fbc1f5d0f744 Page Layout : SinglePage Page Mode : UseNone Page Count : 464
EXIF Metadata provided by EXIF.tools

1989_Microcomputer_Programmable_Logic_Handbook 1989 Microcomputer Programmable Logic Handbook

Navigation menu

Versions of this User Manual:

Views

Navigation