1989_Microprocessor_and_Peripheral_Handbook_Volume_2 1989 Microprocessor And Peripheral Handbook Volume 2
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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
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ovens, or as personal computers or supercomputers, Intel's microcomputers
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MICROPROCESSOR AND
PERIPHERAL HANDBOOK
VOLUME'll
PERIPHERAL
1989
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Table of Contents
Alphanumeric Index '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 1
Overview
ix
,
Introduction ................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
CHAPTER 2
8086 Microprocessor Family
DATA SHEETS
808616-Bit HMOS Microprocessor............. .................. ...........
80C86A 16-Bit CHMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C86AL 16-Bit CHMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8088 8-Bit HMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C88A 8-Bit CHMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
80C88AL 8-Bit CHMOS Microprocessor ..................................... ,
8087/8087 -2/8087 -1 Numeric Data Coprocessor .............................
82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors ......
82C88 CHMOS Bus Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8237 A High Performance Programmable DMA Controller
(8237A, 8237 A-4, 8237 A-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82C37A-5 CHMOS High Performance Programmable DMA Controller............
8259A18259A-2/8259A-8 Programmable Interrupt Controller. . . . .. . . . . . . . . . . . ..
82C59A-2 CHMOS Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . ..
2-1
2-31
2-60
2-89
2-119
2-151
2c 183
2-205
2-214
2-222
2-241
2-259
2-283
CHAPTER 3
80286 Microprocessor Family
DATA SHEETS
80286 High Performance Microprocessor with Memory Management and
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
80287 80-Bit HMOS Numeric Processor Extention . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-56
82258 Advanced Direct Memory Access Coprocessor .........................
3-82
82288 Bus Controller for 80286 Processor
(82288-12,82288-10,82288-8) ........................................... 3-141
82C288 Bus Controller for 80286 Processors
(82C288-12, 82C288-1 0, 82C288-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-161
82C284 Clock Generator and Ready Interface for 80286 Processors
(82C284-12, 82C284-10, 82C284-8) ....................................... 3-182
CHAPTER 4
INTEL386™ Family
DATA SHEETS
386™ High Performance Microprocessor with Integrated Memory Management. . .
80387 80-Bit CHMOS III Numeric Processor Extension. . . . . . . . . . . . . . . . . . . . . . . ..
82380 High Performance 32-Bit DMA Controller wi Integrated System
Support Peripherals.....................................................
82385 High Performance 32-Bit Cache Controller .............................
386SXTM Microprocessor ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . ..
80387SX 80-Bit Numeric Processor Extension ................................
82310/82311 Micro Channel Compatible Peripheral Family. . . . . . . . . . . . . . . . . . . ..
82303 110 Support Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82304110 Support Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82306 Local Channel Support Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82307 DMAIMicro Channel Arbitration Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82308 Micro Channel Bus Controller (BC) ................................... ,
82309 Address Bus Controller (ABC) ........................................
82077 Floppy Disk Controller ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . ..
4-1
4-133
4-171
4-292
4-354
4-450
4-488
4-509
4-519
4-534
4-545
4-557
4-588
4-617
Table of Contents (Continued)
82706 Intel Video Graphics Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82335 High Integration Interface Device for 386SX™ Microprocessor Based
PC-AT System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82230/82231 High Integration AT*-Compatible Chip Set. . . . . . . . . . . . . . . . .. . . . ..
376™ High Performance 32-Bit Embedded Processor. . . . . . . . . . . . . . . . . . . . . . . ..
82370 Integrated System Peripheral. . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . ..
4-618
4-636
4-667
4-705
4-796
CHAPTERS
Memory Controllers
DATA SHEETS
8203 64K Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
8206 Error Detection and Correction Unit. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
8207 Dual-Port Dynamic RAM Controller ....... :. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-39
82C08 CHMOS Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
APPLICATION NOTES
Interfacing the 8207 Dynamic RAM Controller to the 80186 AP-167 ...... , . . . . . .. 5-115
Interfacing the 8207 Advanced Dynamic RAM Controller to the 80286 AP-168
5-121
CHAPTER 6
Support Peripherals
DATA SHEETS
8231A Arithmetic Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . .
6-1
8253/8253-5 Programmable IntervalTimer . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 6-14
8254 Programmable Interval Timer . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
82C54 CHMOS Programmable Interval Timer..................... ............
6-46
8255A18255A-5 Programmable Peripheral Interface : . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
82C55A CHMOS Programmable Peripheral Interface .......................... 6-87
8256AH Multifunction Microprocessor Support Controller. . . . . . . . . . . . . . . . . . . . . .. 6-110
8279/8279-5 Programmable Keyboard/Display Interface. . . . . . . . . . . . . . . . . . . . . .. 6-134
82389 Message Passing Coprocessor, A MULTIBUSTM II Bus Interface Controller; 6-150
CHAPTER 7
Floppy Disk Controllers
DATA SHEETS
8272A Single/Double Density Floppy Disk Controller. . . .. . . . . . . . .. . . . . . . . . . .. .
7-1
82077 Single Chip Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
APPLICATION NOTES
An Intelligent Data Base System Using the 8272 AP-116 .......................
7-87
Software Design and Implementation of Floppy Disk Systems AP-121 ............ 7-128
CHAPTERS
Hard Disk Controllers
DATA SHEET
82064 CHMOS Winchester Disk Controller with On-Chip Error Detection and
Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATION NOTE
Multimode™ Winchester Controller Using the CHMOS 82064 AP-402............
8-1
8-33
CHAPTER 9
Universal Peripheral Interface Slave Microcontrollers
DATA SHEETS
UPITM-452 CHMOS Programmable I/O Processor (80/83/87452) .. . . . . . . . . . . . . .
UPITM-41, 42: 8041 AH/8042AH/8741 AH/8742AH Universal Peripheral Interface
8-Bit Slave Microcontroller ...............................................
9-1
9-54
Table of Contents (Continued)
8243 MCS®-48 Input/Output Expander .. . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. .
APPLICATION NOTES
Applications Using the 8042 UPITM Microco,ntroUer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complex Peripheral Control with the UPITM-42 AP-161 ;........................
An 8741 AH/8041 A Digital Cassette Controller AP-90 . . . . .. . . ... . .. . .. • . . . .. ...
UPITM-452 Accelerates iAPX 286 Bus Performance AP-281 .. ... . . .. . .. . ... .. ...
SYSTEM SUPPORT
ICETM-42 8042 In-Circuit Emulator .... 0' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ~ • • • • •
iUP-200AliUP-201A Universal PROM Programmers .........•...... :..........
9-73
9-79
9-83
9-138
9-145
9-165
9-173
CHAPTER 10
Graphics Coprocessor Family
DATA SHEETS
82706 Intel Video Graphics Array ........................................... .
82716IVSDD Video Storage and Display Device ............................. .
82786 CHMOS Graphics Coprocessor .................. : ... ; ............... .
APPLICATION NOTES
A Low Cost and High I'ltegration Graphics System Using 82716 AP-268 . . . . . . . . ..
82786 Hardware Configuration AP-270 .......................................
An Introduction to Programming the 82786 Graphics Coprocessor AP-408 ........
82786 Design Example Interfacing to the IBM PCI AT Computer AP-409 ..•. : .....
10-1
10-2
10-4
10-49
10-101
10-162
10-222
CHAPTER 11
. . .
Development Tools for the 8051, 8096, 8086/186/188, 80286, an.d 80386
LANGUAGES AND SOFTWARE DEVELOPMENT TOOLS
8051 Software Packages Fact Sheet ........................................ .
8096 Software Development Packages Fact Sheet ........................... .
VAXIVMS Resident Software Development Packages Data Sheet .............. .
8086/80186 SOftware Development Packages Fact Sheet .................... .
8087 Support Library Data Sheet ........................................... .
PSCOPE-86 for DOS High-Level Application Program Debugger Data Sheet •.....
iC-86 C Compiler Fact Sheet ............................................... .
286 Software Development Packages Data Sheet ............................ .
Ada-386 Cross Development for the 386™ Fact Sheet ........................ .
Intel386TM Development Support Family Fact Sheet .......................... .
AEDIT Source Code and Text Editor Fact Sheet ..•............................
iPATTM Performance Analysis Tool Fact Sheet. .................•..............
IN-CIRCUIT EMULATORS
ICETM 5100/452 In-Circuit Emulator Fact Sheet ............................ ; ..
ICETM 51001044 In-Circuit Emulator Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICETM 5100/252 In-Circuit Emulator Fact Sheet.. .. . . . .. ... . . .. . . . . . .. ... . .. ..
ICETM 5100/451 In-Circuit Emulator Fact Sheet. . . .... .. ... .•. . . . . . . .. . .. . .. ..
VLSiCETM-96 In-Circuit Emulator Fact Sheet... . .. .... .. . .. . .. .. . . .. . . . .. . ....
Real-Time Transparent 80C196 In-Circuit Emulator Fact Sheet. . . . . . . . . . . . . . . . ..
ICETM-196KB/xX In-Circuit Emulators Fact Sheet ................ . . . . . . . .. . ...
ICETM-186 In-Circuit Emulator Fact Sheet ;... ... . .. . . . . . . . . . . . . . . . . . . . . . . . . ..
ICETM-188 In-Circuit Emulator Fact Sheet ...................... . . . . . . . . . . . . ..
12 1CETM In-Circuit Emulation System Fact Sheet. . . . . . • . . . . . . . . . . . . . . . . . . . . . . ..
ICETM-286 In-Circuit Emulator Fact Sheet ..............................•.....
Intel386TM Family Development Support Fact Sheet ...........................
11-1
11-4
11-7
11-15
11-19 .
11-23
11-30
11-33
11-51
11-55
11-59
11-61
11-65
11-69
11-73
11-77
11-81
11-84
11-86
11-90
11-94
11-98
11"101
11-104
Alphanumeric Index
286 Software Development Packages Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
376™ High Performance 32-BitEmbedded Processor. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
386SXTM Microprocessor. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
386™ High Performance Microprocessor with Integrated Memory Management .........
80286 High Performance Microprocessor with Memory Management and Protection. . . . . .
80287 80-Bit HMOS Numeric Processor Extention ...................................
80387 80-Bit CHMOS III Numeric Processor Extension ...............................
80387SX 80-Bit Numeric Processor Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8051 Software Packages Fact Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
808616-Bit HMOS Microprocessor....................... ..........................
8086/80186 Software Development Packages Fact Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8087 Support Library Data Sheet ..................................................
8087/8087-2/8087-1 Numeric Data Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8088 8-Bit HMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8096 Software Development Packages Fact Sheet. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C86A 16-Bit CHMOS Microprocessor ............................................
80C86AL 16-Bit CHMOS Microprocessor ................. . . . . . . . . . . . . . . . . . . . . . . . . . .
80C88A 8-Bit CHMOS Microprocessor.................... ..........................
80C88AL 8-Bit CHMOS Microprocessor ............................................
8203 64K Dynamic RAM Controller ................................. " . . . . . . . . . . . . . .
8206 Error Detection and Correction Unit ...........................................
82064 CHMOS Winchester Disk Controller with On-Chip Error Detection and Correction ..
8207 Dual-Port Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .
82077 Floppy Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82077 Single Chip Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82230/82231 High Integration AT*-Compatible Chip Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82258 Advanced Direct Memory Access Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82288 Bus Controller for 80286 Processor (82288-12, 82288-10, 82288-8) . . . . . . . . . . . . ..
82303 I/O Support Chip .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
823041/0 Support Chip ..........................................................
82306 Local Channel Support Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82307 DMAIMicro Channel Arbitration Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82308 Micro Channel Bus Controller (BC) . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82309 Address Bus Controller (ABC) ................................. , . . . . . . . . . . . ..
82310/82311 Micro Channel Compatible Peripheral Family ...........................
8231 A Arithmetic Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
82335 High Integration Interface Device for 386SXTM Microprocessor Based PC-AT
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82370 Integrated System Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8237A High Performance Programmable DMA Controller (8237 A, 8237 A-4, 8237 A-5) . .. ..
82380 High Performance 32-Bit DMA Controller w/lntegrated System
Support Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . ..
82385 High Performance 32-Bit Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82389 Message Passing Coprocessor, A MULTIBUSTM II Bus Interface Controller. . . . . . ..
8243 MCS®-48 Input/Output Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8253/8253-5 Programmable Interval Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8254 Programmable Interval Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8255A18255A-5 Programmable Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8256AH Multifunction Microprocessor Support Controller .............. :..............
8259A18259A-2/8259A-8 Programmable Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . ..
82706 Intel Video Graphics Array..................................................
82706 Intel Video Graphics Array ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82716IVSDD Video Storage and Display Device.....................................
8272A Single/Double Density Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
11-33
4-705
4-354
4-1
3-1
3-56
4-133
4-450
11-1
2-1
11-15
11-19
2-183
2-89
11-4
2-31
2-60
2-119
2-151
5-1
5-17
8-1
5-39
4-617
7-32
4-667
3-82
3-141
4-509
4-519
4-534
4-545
4-557
4-588
4-488
6-1
4-636
4-796
2-222
4-171
4-292
6-150
9-73
6-14
6-25
6-63
6-110
2-259
4-618
10-1
10-2
7-1
Alphanumeric Index (Continued)
82786 CHMOS Graphics Coprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
82786 Design Example Interfacing to the IBM PC/AT Computer AP-409 ................
82786 Hardware Configuration AP-270 .............................................
8279/8279-5 Programmable Keyboard/Display Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82C08 CHMOS Dynamic RAM Controller ...........................................
82C284 Clock Generator and Ready Interface for 80286 Processors
(82C284-12, 82C284-1 0, 82C284-8) ........................................... '"
82C288 Bus Controller for 80286 Processors (82C288-12, 82C288-10, 82C288-8)........
82C37 A-5 CHMOS High Performance Programmable DMA Controller ..................
82C54 CHMOS Programmable Interval Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82C55A CHMOS Programmable Peripheral Interface .................................
82C59A-2 CHMOS Programmable Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82C84A CHMOS Clock Generator and Driver for 80C86, 80C88 Processors. . . . . .. . . . . ..
82C88 CHMOS Bus Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ..
A Low Cost and High Integration Graphics System Using 82716 AP-268. . . . . . . • . . . . . . . ..
Ada-386 Cross Development for the 386™ Fact Sheet. .. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AEDIT Source Code and Text Editor Fact Sheet ......................................
An 8741 AH/8041 A Digital Cassette Controller AP-90 . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . ..
An Intelligent Data Base System Using the 8272 AP-116 . . . . . . . . . . .. . . . . . . . . . . .. . . . . . .
An Introduction to Programming the 82786 Graphics Coprocessor AP-408 ..............
Applications Using the 8042 UPITM Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complex Peripheral Control with the UPITM-42 AP-161 ................................
iC-86 C Compiler Fact Sheet .......... : ................................. ;.........
ICETM 5100/044 In-Circuit Emulator Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICETM 5100/252 In-Circuit Emulator Fact Sheet. ." ........... " ........ ; . . . . . . . . . . . ..
ICETM 5100/451 In-Circuit Emulator Fact Sheet......................................
ICETM 5100/452 In-Circuit Emulator Fact Sheet. .....................................
ICETM-186 In-Circuit Emulator Fact Sheet ...........................................
ICETM-188 In-Circuit Emulator Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
ICETM-196KB/xX In-Circuit Emulators Fact Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICETM-286 In-Circuit Emulator Fact Sheet ...........................................
ICETM-42 8042 In-Circuit Emulator.................................................
Intel386TM Development Support Family Fact Sheet. . . . .. . . . . . .. . . . . . . . . . . . . .. . . . . . ..
Intel386™ Family Development Support Fact Sheet. .................................
Interfacing the 8207 Advanced DynamiC RAM Controller to the 80286 AP-168 . ; . . . . . . ...
Interfacing the 8207 Dynamic RAM Controller to the 80186 AP-167 . . . . . . . . . . . . . . . . . . . ..
iPATTM Performance Analysis Tool Fact Sheet ......................................
iUP-200A/iUP-201 A Universal PROM Programmers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
12 1CETM In-Circuit Emulation System Fact Sheet ....................... ;.............
Multimode™ Winchester Controller Using the CHMOS 82064 AP-402 ..................
PSCOPE-86 for DOS High-Level Application Program Debugger Data Sheet. . . . . . . . . . . ..
Real-Time Transparent 80C196 In-Circuit Emulator Fact Sheet ........................
Software Design and Implementation of Floppy Disk Systems AP-121 ..................
UPITM-41, 42: 8041 AH/8042AH/8741 AH/8742AH Universal Peripheral Interface 8-Bit
Slave Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . .
UPITM-452 Accelerates iAPX 286 Bus Performance AP-281 ..........•................
UPITM-452 CHMOS Programmable I/O Processor (80/83/87452). . . . . . . . . . . . . . . . . . . . . .
VAXIVMS Resident Software Development Packages Data Sheet ..•.....•............
VLSiCETM-96 In-Circuit Emulator Fact Sheet ........................................
x
10-4
10-222
10-101
6-134
5-86
3-182
3-161
2-241
6-46
6-87
2-283
2-205
2-214
10-49
11-51
11-59
9-138
7-87
10-162
9-79
9-83
11-30
11-69
11-73
11-77
11-65
11-90
11-94
11-86
11-101
9-165
11-55
11 c 104
5-121
5-115
11-61
9-173
11-98
8-33
11-23
11-84
7-128
9-54
9-145
9-1
11-7
11-81
Any of the following products may appear in this publication. If so, it must be noted that
such products have counterparts manufactured by Intel Puerto Rico, Inc., Intel Puerto
Rico II, Inc., and/or Intel Singapore, Ltd. The product codes/part numbers of these
counterpart products are listed below next to the corresponding Intel Corporation product
codes/part numbers.
Intel Corporation
Product Codes/
Part Numbers
376SKIT
903
904
913
914
923
924
952
953
954
ADA ICE
B386MI
B3B6M2
B386M4
B3B6M8
C044KIT
C252KIT
C28
C32
C452KIT
D86ASM
D86C86
D86EDI
DCM9111
DOSNET
FI
GUPILOGICIID
H4
1044
I252KIT
I452KIT
I86ASM
ICE386
IllOI0
Ill086
Ill086
IllIII
III 186
III 186
1II198
1II212
111286
Ill286
Ill515
III 520
Ill520
Ill531
Ill532
1II533
Ill621
III707
1II707
1II815
INA961
IPAT86
KAS
KC
KH
KMI
Intel Puerto Rico, Inc.
Intel Puerto Rico II. Inc.
Product Codes/
Part Numbers
Intel Corporation
Product Codes/
Part Numbers
Intel Singapore, Ltd.
Product Codes/
Part Numbers
p376SKIT
p903
p904
p913
p914
p923
p924
p952
p953
p954
pADAICE
pB386Ml
pB3B6M2
pB386M4
pB386MB
pC044KIT
pC252KIT
pC28
pC32
pC452KIT
pD86ASM
pD86C86
pD86EDI
pDCM9111
pDOSNET
pFI
pGUPILOGICIID
pH4
plO44
pI252KIT
pI452KIT
pI86ASM
pICE386
pIllOlO
pIll086
TIll086
pIll111
pIlI I 86
TlII186
pIlll98
pIll212
pIll286
TlII286
pIll515
TIll 520
pIlI520
pIll53 I
pIll532
pIll533
pIII62 I
pIII707
TIII707
pIll8I5
pINA96I
pIPAT86
pKAS
pKC
pKH
pKMI
KM2
KM4
KM8
KNLAN
KT60
KWI40
KW40
KW80
MI
M2
M4
M8
MDS6lO
MDX3015
MDX3015
MDX3016
MDX3016
MDX457
MDX457
MDX458
MDX458
MSA96
NLAN
PCLINK
PCX344A
R286ASM
R286EDI
R286PLM
R286SSC
R86FOR
RCB44lO
RCX920
RMX286
RMXNET
S301
S386
SBCOlO
SBCOl2
SBC020
SBC028
SBC040
SBC056
SBClO8
SBCII6
SBCI8603
SBCI86410
SBCI8651
SBCI86530
SBCI8678
SBCI8848
SBCI8856
SBC208
SBC214
SBC215
SBC220
SBC221
SBC286lO
SBC286I2
SBC28614
xi
Intel Puerto Rico, Inc.
Intel Puerto RIco II, Inc.
Product Codes/
Part Numbers
Intel Singapore, Ltd.
Product Codes /
Part Numbers
pKM2
pKM4
pKM8
pKNLAN
pKT60
pKWI40
pKW40
pKW80
pMl
pM2
pM4
pM8
pMDS6lO
pMDX3015
pMDX3015
pMDX3016
pMDX3016
pMDX457
pMDX457
pMDX458
pMDX458
pMSA96
pNLAN
sPCLINK
pPCX344A
pR286ASM
pR286EDI
pR286PLM
pR286SSC
pR86FOR
sRCB4410
pRCX920
pRMX286
pRMXNET
pS301
pS386
pSBCOlO
pSBCOl2
pSBC020
pSBC028
pSBC040
pSBC056
pSBCI08
pSBC116
pSBC18603
pSBCI86410
pSBCI8651
pSBCI86530
pSBC18678
pSBCI8848
pSBCI8856
pSBC208
pSBC214
pSBC215
pSBC220
pSBC221
pSBC286lO
pSBC28612
pSBC28614
sSBCOl2
sSBCI8603
sSBCI8651
sSBCI8848
sSBCI8856
sSBC208
sSBC220
sSBC286lO
Intel Corporation
Product Codesj
Part Numbers
SBC28616
SBC300
SBC30l
SBC302
SBC304
SBC307
SBC3l4
SBC322
SBC324
SBC337
SBC34l
SBC386
SBC386ll6
SBC386l20
SBC3862l
SBC38622
SBC38624
SBC38628
SBC3863l
SBC38632
SBC38634
SBC38638
SBC428
SBC464
SBC517
SBC5l9
SBC534
SBC548
SBC550
SBC550
SBC550
SBC552
SBC556
SBC569
SBC589
SBC604
SBC608
SBC6l4
SBC6l8
SBC655
SBC66ll
SBC8010
SBC80204
SBC8024
SBC8030
SBC8605
SBC86l2
SBC86l4
SBC8630
SBC8635
SBC86C38
SBC8825
SBC8840
SBC8845
SBC905
SBCLNKOOl
Intel Puerto Rico, Inc.
Intel Puerto Rico II, Inc.
Product Codes j
Part Numbers
pSBC286l6
pSBC300
pSBC30l
pSBC302
pSBC304
pSBC307
pSBC3l4
pSBC322
pSBC324
pSBC337
pSBC34l
pSBC386
pSBC386ll6
pSBC386l20
pSBC3862l
pSBC38622
pSBC38624
pSBC38628
pSBC3863l
pSBC38632
pSBC38634
pSBC38638
pSBC428
pSBC464
pSBC5l7
pSBC5l9
pSBC534
pSBC54S
TSBC550
pSBC550
pSBC550
pSBC552
pSBC556
pSBC569
pSBC589
pSBC604
pSBC608
pSBC6l4
pSBC6l8
pSBC655
pSBC66ll
pSBC8010
pSBC80204
pSBC8024
pSBC8030
pSBC8605
pSBC86l2
pSBC86l4
pSBC8630
pSBC8635
pSBC8825
pSBC8840
pSBC8845
pSBC905
pSBCLNKOOl
Intel Corporation
Product Codesj
Part Numbers
Intel Singapore, Ltd.
Product Codesj
Part Numbers
SBCMEM310
SBCMEM3l2
SBCMEM320
SBCMEM340
SBE96
SBX2l7
SBX2l8
SBX270
SBX3ll
SBX328
SBX33l
SBX344
SBX350
SBX35l
SBX354
SBX488
SBX586
SCHEMAIIPLD
SCOM
SDK5l
SDK85
SDK86
SXM2l7
SXM286l2
SXM386
SXM544
SXM552
SXM95l
SXM955
SYPl20
SYP30l
SYP302
SYP31090
SYP311
SYP3847
SYR286
SYR86
SYSl20
SYS3l0
SYS3ll
T60
TA096
TA252
TA452
Wl40
W280
W40
W80
XNX286DOC
XNX286DOCB
XNXIBASE
XNXIDB
XNXIDESK
XNXIPLAN
XNXIWORD
sSBC386
sSBC428
sSBC5l9
sSBC534
sSBC556
"
sSBC8024
sSBC8605
sSBC8630
sSBC8635
sSBC86C38
sSBC8825
sSBC8845
Intel Puerto Rico, Inc.
Intel Puerto Rico II, Inc.
Product Codes j
Part Numbers
Intel Singapore, Ltd •
Product Codes j
Part Numbers
pSBCMEM310
pSBCMEM3l2
pSBCMEM320
pSBCMEM340
pSBE96
pSBX2l7
pSBX2l8
pSBX270
pSBX311
pSBX328
pSBX33l
pSBX344
pSBX350
pSBX35l
pSBX354
pSBX488
sSBX586
pSCHEMAIIPLD
pSCOM
pSDK5l
pSDK85
pSDK86
pSXM2l7
pSXM286l2
pSXM386
pSXM544
pSXM552
pSXM95l
pSXM955
pSYPl20
pSYP30l
pSYP302
pSYP3l090
pSYP3ll
pSYP3847
pSYR286
pSYR86
pSYSl20
pSYS310
pSYS3ll
pT60
pTA096
pTA252
pTA452
pWl40
pW280
pW40
pW80
pXNX286DOC
pXNX286DOCB
pXNXIBASE
pXNXIDB
pXNXIDESK
pXNXIPLAN
pXNXIWORD
xii
CG/PCPN/1024BB
OVERVIEW.
I
INTRODUCTION
Intel microprocessors and peripherals provide a complete
solution in increasingly complex application environments. Quite often, a single peripheral device will replace
anywhere from 20 to 100 TTL devices (and the associated
design time that goes with them).
Built-in functions and standard Intel microprocessor/
peripheral interface deliver very real time and performance advantages to the designer of microprocessorbased systems.
REDUCED TIME TO MARKET
When you can purchase an off-the-shelf solution that
replaces a number of discrete devices, you're also replacing all the design, testing, and debug time that goes with
them.
INCREASED RELIABILITY
At Intel, the rate offailure for devices is carefully tracked.
Highest reliability is a tangible goal that translates to
higher reliability for your product, reduced downtime,
and reduced repair costs. And as more and more
functions are intergrated on a single VLSI device, the
resulting system requires less power, produces less heat,
and requires fewer mechanical connections-again resulting in greater system reliability.
LOWER PRODUCTION COST
By minimizing design time, increasing reliability, and
replacing numerous parts, microprocessor and peripheral
solutions can contribute dramatically to lower product
costs.
HIGHER SYSTEM PERFORMANCE
Intel microprocessors and peripherals provide the highest
system performance for the demands of today's (and
tomorrow's) microprocessor-based applications. Forexampie, the 80386 32 bit offers the highest performance for
multitasking, multiuser systems. Intel's peripheral products have been designed with the future in mind. They
support all of Intel's 8, 16 and 32 bit processors.
HOW TO USE THE GUIDE
The following application guide illustrates the range of
microprocessors and peripherals that can be used for the
applictions in the vertical column of the left. The
peripherals are grouped by the I/O function they control.
CRT datacommunication, universal (user programmable),
mass storage dynamic RAM controllers, and CPU/ bus
support.
An "X" in a horizontal application row indicates a
potential peripheral or CPU, depending upon the features
desired. For example, a conversational terminal could
use either of the three display controllers, depending
upon features like the number of characters per row or
font capability. A "Y" indicates a likely candidate, for
example, the 8272A Floppy Disk Controller in a small
business computer.
The Intel microprocessor and peripherals family provides
a broad range of time-saving, high performance solutions.
Get Your Kit Together!
Intel's Microsystem Components Kit Solution
MICROPROCESSOR
8088/80C88
8086/80C86
80186
80188
80286
386'·fL
386SX'·fL
SUPER CHIP SET
82310/11
82230/31
82335
82350
NUMERIC
PROCESSORS
8087
80287
80387
80387SX
CPU SUPPORT
8231A
8253
8254/82C54
8255A/82C55A
8256AH
8279
82389
82370
DMA
8253
8237
82285
82380
82560
~-,,,""
CACHE
MEMORY
DYNAMIC RAM
*
*
CACHE CONTROL
~!:.&..:;;i
MEMORY
SUPPORT
8203
8206
8207
82C08
"""""-,,,
CRT
CONTROL
82706
82716
82786
r.:.a$.
I
© Inlel1989
~."';'h'''''''''''''~f"'~
SPECIAL
PERIPHERAL
CONTROL
UPI'· 8041A/8741A
UPI ,. 8042/8742
UPI'· 80/83/87C452
~ '_A~'.
<':_
~:~:t;';:"';;;'<.';:,,~
*
*
*
*
*
*
*
*
"
FLOPPY DISK
. '
~~~~ROL
~~ 82077
[""".1"
HARD DISK
CONTROL
82064
GLOBAL
COMMUNICATIONS
8251A
82050
82510
8273
8274
8291 A/92/94
82530
;:
8044/8344/8744
':",y"
r'
,
.t
LOCAL AREA
NETWORKING
82C501
82586
82588
82560
W 82590/92
i
iMCC
L~'0.". i,)
*;'
~. INSTRUMENTATION
BUS (GPIB)
.: 8291
< 8292
,
l~LU~'L.;.,:::
!!;I TELEP, COMMUNICATIONS
2910/11/12
........... " 29C13/C14/C16/C17
4.Mt29C48
.........,...
29C53AA
ISP 188
89024
89C024XE
*11)1
JlJj
January 19B!
Order Number: 230664-00'
Memory Controllers
5
8203
64K DYNAMIC RAM CONTROLLER
•
Compatible with Intel® 8080A,
• Fully
8085A, iAPX88, and iAPX 86 Family
Provides All Signals Necessary to
Control 64K and 16K Dynamic
Memories
Microprocessors
•
•
Provides Address Multiplexing and
• Strobes
Provides a Refresh Timer and a
• Refresh
Counter
Provides Refresh! Access Arbitration
• Internal Clock Capability with the
• 8203-1 and the 8203-3
Directly Addresses and Drives Up to 64
Devices Without External Drivers
Decodes CPU Status for Advanced
Read Capability in 16K Mode with the
8203-1 and the 8203-3.
Provides System Acknowledge and
• Transfer
Acknowledge Signals
Cycles May be Internally or
• Refresh
Externally Requested (For Transparent
Refresh)
Series Damping Resistors on
• AllInternal
RAM Outputs
The Intel® 8203 is a Dynamic RAM System Controller designed to provide all signals necessary to use 64K or
16K Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed addresses and address
strobes, refresh logic, refresh/access arbitration. Refresh cycles can be started internally or externally. The
8203-1 and the 8203-3 support an internal crystal oscillator and Advanced Read Capability. The 8203-3 is a
±5% Vee part.
A~-AH7
COlUWN
ADDRESS
AlO-AL7
.ow
""'"'ss
Al,
So
0iiS0
W,
REFRESH
C"""".
iffi
OuT,
AiS2
5'======:1
R/33
""
i>CS--------l
"'"
.-0
""
GENERATOR
SACK
..ex
210444-2
Figure 2.
Pin Configuration
210444-1
Figure 1. 8203 Block Diagram
5-1
November 1987
Order Number: 210444-006
intJ
8203
Table 1. Pin Descriptions
Symbol
Pin
No.
Name and Function
Type
ALa
AL1
AL2
AL;3
AL4
ALs
AL6
6
8
10
12
14
16
18
ADDRESS LOW: CPU address inputs used to generate memory row
address.
AHa
AH1
AH2
AH3
AH4
AHs
AH6
5
4
3
2
1
39
38
ADDRESS HIGH: CPU address inputs used to generate memory
column address.
Bo/AL7
B1/0P1/
AH7
24
25
BANK SELECT INPUTS: Used to gate the appropriate RAS output for
a memory cycle. B1 /OP1 option used to select the Advanced Read
Mode. (Not available in 64K mode.) See Figure 5.
When in 64K RAM Mode, pins 24 and 25 operate as the AL7 and AH7
address inputs.
.
PCS
33
I
PROTECTED CHIP SELECT: Used to enable the memory read and
write inputs. Once a cycle is started, it will not abort even if PCS goes
inactive before cycle completion.
WR
31
I
MEMORY WRITE REQUEST.
RD/S1
32
I
MEMORY READ REQUEST: S1 function used in Advanced Read
mode selected by OP1 (pin 25).
REFRQ/
ALE
34
I
EXTERNAL REFRESH REQUEST: ALE function used in Advanced
Read mode, selected by OP1 (pin 25).
OUTo
OUT1
OUT2
OUT3
OUT4
OUTs
OUT6
7
9
11
13
15
17
19
0
0
0
0
0
0
0
OUTPUT OF THE MULTIPLEXER: These outputs are designed to
drive the addresses of the Dynamic RAM array. (Note that the OUT0-7
pins do not require inverters or drivers for proper operation.)
WE
28
0
WRITE ENABLE: Drives the Write Enable inputs of the Dynamic RAM
array.
CAS
27
0
COLUMN ADDRESS STROBE: This output is used to latch the
Column Address into the Dynamic RAM array.
RASa
RAS 1
RAS2/
OUT7
RAS3/BO
21
22
23
0
0
0
ROW ADDRESS STROBE: Used to latch the Row Address into the
bank of dynamic RAMs, selected by the 8203 Bank Select pins (Bo,
B1 /OP1). In 64K mode, only RASa and RAS1 are available; pin 23
operates as OUT7 and pin 26 operates as the Bo bank select input.
26
I/O
XACK
29
0
TRANSFER ACKNOWLEDGE: This outputis a strobe indicating valid
data during a read cycle or data written during a write cycle. XACK can
be used to latch valid data from the RAM array.
5-2
inter
8203
Table 1. Pin Descriptions (Continued)
Symbol
Pin
No.
Type
Name and Function
SACK
30
0
SYSTEM ACKNOWLEDGE: This output indicates the beginning of a
memory access cycle. It can be used as an advanced transfer
acknowledge to eliminate wait states. (Note: If a memory access
request is made during a refresh cycle, SACK is delayed until XACK in
the memory access cycle).
XO/OP2
X1/ClK
36
37
I/O
I/O
OSCILLATOR INPUTS: These inputs are designed for a quartz crystal
to control the frequency of the oscillator. If XO/OP2 is shorted to pin 40
(Vecl or if XO/OP2 is connected to + 12V through a 1 Kfl. resistor then
X1 /ClK becomes a TTL input for an external clock. (Note: Crystal
mode for the 8203-1 and the 8203-3 only).
16K/64K
35
I
Vee
40
POWER SUPPLY:
GND
20
GROUND.
MODE SELECT: This input selects 16K mode or 64K mode. Pins
23-26 change function based on the mode of operation.
+ 5V.
transitions are synchronous with respect to this
clock reference, except for the trailing edges of the
CPU handshake signals SACK and XACK.
FUNCTIONAL DESCRIPTION
The 8203 provides a complete dynamic RAM controller for microprocessor systems as well as expansion memory boards.
CPU memory requests normally use the RD and WR
inputs. The Advanced-Read mode allows ALE and
S1 to be used in place of the RD input.
The 8203 has two modes, one for 16K dynamic
RAMs and one for 64Ks, controlled by pin 35.
Failsafe refresh is provided via an internal timer
which generates refresh requests. Refresh requests
can also be generated via the REFRQ input.
,--
WE
Xo
I
cs=l=
I
I
I
RASO
X1
-=-
An on-chip synchronizer/arbiter prevents memory
and refresh requests from affecting a cycle in progress. The READ, WRITE, and external REFRESH
requests may be asynchronous to. the 8203 clock;
on-chip logiC will synchronize the requests, and the
arbiter will decide if the requests should be delayed,
pending completion of a cycle in progress.
CAS
t::I
1KU
~ 5%
CS.,L.
8203-1
T
I
_I
8203-3
68011
1·5%
RAS1
or
RAS2
-=-
RAS3
XACK
Cs<10pF
Fundamental XTAL
16K/64 Option Selection
SACK
Pin 35 is a strap input that controls the two 8203
modes. Figure 4 shows the four pins that are multi·
plexed. In 16K mode (pin 35 tied to Vee or left
open), the 8203 has two Bank Select inputs to select one of four RAS outputs. In this mode, the 8203
is exactly compatible with the Intel 8202A Dynamic
RAM Controller. In 64K mode (pin 35 tied to GND),
there is only one Bank Select input (pin 26) to select
the two RAS outputs. More than two banks of 64K
dynamic RAMs can be used with external logic.
210444-4
Figure 3. Crystal Operation for
the 8203·1 and 8203·3
All 8203 timing is generated from a single reference
clock. This clock is provided via an external oscillator or an on-chip crystal oscillator: All output signal
5-3
8203
Other Option Selections
Address Multiplexer
The 8203 has two strapping options. When OP1 is
selected (16K mode only), pin 32 changes from a
RD input to an S1 input, and pin 34 changes from a
REFRQ input to an ALE input. See "Refresh Cycles"
and "Read Cycles" for more detail. OP1 is selected
by tying pin 25 to + 12V through a 5.1 K!l. resistor
on the 8203-1 or 8203-3 only.
When OP2 is selected, the internal oscillator is disabled and pin 37 changes from a crystal input (X1) to
a ClK input for an external TTL clock. OP2 is selected by shorting pin 36 (XO/OP2) directly to pin 40
(Vee). No current limiting resistor should be used.
OP2 may. also be selected by tying pin 36 to + 12V
through a 1 K!l. resistor.
The address multiplexer· takes the address inputs
and the refresh counter outputs, and gates them
. onto the address outputs at the appropriate time.
The address outputs, in conjunction with the RAS
and CAS outputs, determine the address used by
.the dynamic RAMs for read, write, and refresh cycles. During the first part of a read or write cycle,
Alo-Al7 are gated to OUTo-OUT7, then AHo-AH7
are gated to the address outputs..
During a refresh cycle, the refresh counter is gated
onto the address outputs. All refresh cycles are
RAS-only refresh (CAS inactive, RAS active).
To minimize buffer delay, the information on the address outputs is inverted from that on the address
inputs.
Refresh Timer
The refresh timer is used to monitor the time since
the last refresh cycle occurred. When the appropriate amount of time has elapsed, the refresh timer
will request a refresh cycle. External refresh requests will reset .the refresh timer.
Refresh Counter
The refresh counter is used to sequentially refresh
all of the memory's rows. The 8-bit counter is incremented after every refresh cycle.
Pin #
16K Function
64K Function
23
24
25
26
RAS2
Bank Select (Bo)
Bank Select (B1)
RAS3
Address Output (OUT7)
Address Input (Al7)
Address Input (AH7)
Bank Select (Bo)
OUTo-OUT7 do not need inverters or buffers unless
additional drive is required.
Synchronizer!Arbiter
The 8203 has three inputs, REFRQ/ Al~in 34),
RD (pin 32) and WR (pin 31). The RD and YVR inputs
allow an external CPU to request a memory read or
write cycle, respectively. The REFRQ/ ALE input allows refresh requests to be requested external to
the 8203.
All three of these inputs may be asynchronous with
respect to the 8203's clock. The arbiter will resolve
conflicts between refresh and memory requests, for
both pending cycles and cycles in progress. Read
and write requests will be given priority over refresh
requests.
Figure 4. 16K/64K Mode Selection
System Operation
Inputs
16K
Mode
64K
Mode
Outputs
B1
Bo
RASo
RAS1
RAS2
RAS3
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
0
-.
0
1
0
1
-
-
b
1
1
1
0
-
The 8203 is always in one of the following states:
a) IDLE
b) TEST Cycle
c) REFRESH Cycle
d) READ Cycle
e) WRITE Cycle
The 8203 is normally in the IDLE state. Whenever
one of the other cycles is requested, the 8203 will
-
Figure 5. Bank Selection
Description
Pin #
Normal Function
Option Function
B1/0P1 (16K only)/ AH7
25
Bank (RAS) Select
XO/OP2
36
Crystal Oscillator (8203-1 and 8203-3) External Oscillator
Figure 6. 8203 Option Selection
, 5-4
Advanced-Read Mode (8203-1, -3)
8203
leave the IDLE state to perform the desired cycle. If
no other cycles are pending, the 8203 will return to
the IDLE state.
If the 8203 is not in the idle state then a simultaneous memory request and an external refresh request may result in the refresh request being honored first.
Test Cycle
The TEST Cycle is used to check operation of several 8203 internal functions. TEST cycles are requested by activating the PCS, RD and WR inputs. The
TEST Cycle will reset the refresh address counter
and perform a WRITE Cycle. The TEST Cycle
should not be used in normal system operation,
since it would affect the dynamic RAM refresh.
So
~r---
6085A5,
REFRO
.
8203
,
SACK 0'
CAS
210444-5
Figure 7. Hidden Refresh
Refresh Cycles
Certain system configurations require complete external refresh requests. If external refresh is requested faster than the minimum internal refresh timer
(tREF), then, in effect, all refresh cycles will be
caused by the external refresh request, and the internal refresh timer will never generate a refresh request.
The 8203 has two ways of providing dynamic RAM
refresh:
1) Internal (failsafe) refresh
2) External (hidden) refresh
Both types of 8203 refresh cycles activate all of the
RAS outputs, while CAS, WE, SACK, and XACK remain inactive.
Read Cycles
Internal refresh is generated by the on-chip refresh
timer. The timer uses the 8203 clock to ensure that
refresh of all rows of the dynamic RAM occurs every
2 milliseconds (128 cycles) or every 4 milliseconds
(256 cycles). If REFRO is inactive, the refresh timer
will request a refresh cycle every 10-16 microseconds.
The 8203 can accept two different types of memory
Read requests:
1) Normal Read, via the RD input
2) Advanced Read, using the S1 and ALE inputs
(16K mode only)
The user can select the desired Read request configuration via the B1/0P1 hardware strapping option
on pin 25.
External refresh is requested via the REFRO input
(pin 34). External refresh control is not available
when the Advanced-Read mode is selected. External refresh requests are latched, then synchronized
to the 8203 clock.
Pin 25
Pin 32
Pin 34
# RAM Banks
Ext. Refresh
The arbiter will allow the refresh request to start a
refresh cycle only if the 8203 is not in the middle of a
cycle.
When the 8203 is in the idle state a simultaneous
memory request and external refresh request will result in the memory request being honored first. This
8203 characteristic can be used to "hide" refresh
cycles during system operation. A circuit similar to
Figure 7 can be used to decode the CPU's instruction fetch status to generate an external refresh request. The refresh request is latched while the 8203
performs the instruction fetch; the refresh cycle will
start immediately after the memory cycle is completed, even if the RD input has not gone inactive. If the
CPU's instruction decode time is long enough, the
8203 can complete the refresh cycle before the next
memory request is generated.
Normal Read
Advanced Read
B11nput
RD Input
REFRO Input
4 (RASo_3)
Yes
OP1 (+12V)
S1 Input
ALE Input
2 (RAS2_3)
No
Figure 8. 8203 Read Options
Normal Reads are requested by activating the RD
input, and keeping it active until the 8203 responds
with an XACK pulse. The RD input can go inactive
as soon as the command hold time (tCHS) is met.
Advanced Read cycles are requested by pulsing
ALE while S1 is active; if S1 is inactive (low) ALE is
ignored. Advanced Read timing is similar to Normal
Read timing, except the falling edge of ALE is used
as the cycle start reference.
5-5
8203
If a Read cycle is requested while a refresh cycle is
in progress, then the 8203 will set the internal
delayed-SACK latch. When the Read cycle is eventually started, the 8203 will delay the active SACK
transition until XACK goes active, as shown in the
A.C. timing diagrams. This delay was designed to
compensate for the CPU's READY setup and hold
times. The delayed-SACK latch is cleared after every READ cycle.
designed to have a system error rate less than 1
memory cycle every three years based on the full
operating range of the 8203.
A microprocessor system is concerned when the
data is valid after RD goes low. See Figure 9. In
order to calculate memory read access times, the
dynamic RAM's A.C. specifications must be examined, especially the RAS-access.time (tRAd and the
CAS-access time (tcAd. Most configurations will be
CAS-access limited; i.e., the data from the RAM will
be stable tcc max (8203) + tCAC (RAM) after a memory read cycie is started. Be sure to add any delays
(due to buffers, data latches, etc.) to calculate the
overall read access time.
Based on system requirements, either SACK or
XACK can be used to generate the CPU READY
signal. XACK will normally be used; if the CPU can
tolerate an advanced READY, then SACK can be
used, but only if the CPU can tolerate the amount of
advance provided by SACK. If SACK arrives too early to provide the appropriate number of WAIT states,
then either XACK or a delayed form of SACK should
be used.
Since the 8203 normally performs "early-write" cycles, the data must be stable at the RAM data inputs
by the time CAS goes active, including the RAM's
data setup time. If the system does not normally
guarantee sufficient write data setup, you must either delay the WR input signal or delay the 8203 WE
output.
Write Cycles
Write cycles are similar to Normal Read cycles, except for the WE output. WE is held inactive for Read
cycles, but goes active for Write cycles. All 8203
Write cycles are "early-write" cycles; WE goes active before CAS goes active by an amount of time
sufficient to keep the dynamic RAM output buffers
turned off.
Delaying the WR input will delay all 8203 timing, including the READY handshake signals, SACK and
XACK, which may increase the number of WAIT
states generated by the CPU.
Ao~, '--------:-,- - - - - '
/
General System Considerations
f4:.---tRLDV~
,
B:
,..-----,
All memory requests (Normal Reads, Advanced
Reads, Writes) are qualified by the PCS input. PCS
should be stable, either active or inactive, prior to
the leading edge of RD, WR, or ALE. Systems which
use battery backup should pull up PCS to prevent
erroneous memory requests.
DATA-----«
,
,
,
!
,
L..--tRAC---"
RAS---',\
I
tCAC
I
!I
I
'--f
In order to minimize propagation delay, the 8203
uses an inverting address multiplexer without latches. The system must provide adequate address setup and hold times to guarantee RAS and CAS setup
and hold times for the RAM. The tAD A.C. parameter
should be used for this system calculation.
CAS------""'\
210444-6
Figure 9. Read Access Time
If the WE output is externally delayed beyond the
CAS active transition, then the RAM will use the failing edge of WE to strobe the write data into the
RAM. This WE transition should not occur too late
during the CAS active transition, or else the WE to
CAS requirements of the RAM will not be met.
The Bo-B1 inputs are similar to the address inputs in
that they are not latched. Bo andB1 should not be
changed durin~memory cycle, since they directly
control which RAS output is activated.
The 8203 uses a two-stage synchronizer for the
memory request inputs (RD, WR, ALE), and a separate two stage synchronizer for the external refresh
input (REFRQ). As with any synchronizer, there is
always a finite probability of metastable states inducing system errors. The 8203 synchronizer was
The RASo_3, CAS, OUTO_7' and WE outputs contain on-chip series damping resistors (typically 20n)
to minimize overshoot.
5-6
8203
adding pull-up resistors to the 8203's outputs. Intel
RAMs do not require pull-up resistors.
Some dynamic RAMs require more than 2.4V VIH.
Noise immunity may be improved for these RAMs by
-
DYNAMIC RAM ARRAY
A8-1S
ALE
B088
ADO_7
RD
WR
AlO-6
~
OITiO-6
AHO-6
--,I
AO-6
:::
CAS
f-
BO_1
B203
(16K MODE) WE
CAS
P
-c
RD/51
WR
-
RASO
RAS1~
RAS2
SACK
RAS3
WE
AAS
DIN DOUT
T.
Ll
-,\r---
I""
AD-6
f=:
I---
CAS
RAS
+
+
XACK
WE
DcNDOUT
T
L.....,r---
r""
L-..
D'N
DouT
~
i--o
~
AO-6
WE
CAS
RAS
OINDOUT
Tl:
-
D'N
DOUT
l...l
D'N
DOUT
D'
Ab-6
BAL
D'N
~~A
DATA BUS
~
DIN
DIN
} NDour
Dour
Dour
DoUT
~T
T-r 1 1
1
DATA IN /
LATCH
\.
-
WE
DiN
CAS
D'N
Dour
RAS
Dour
DIN DouT
\I
210444-7
Figure 10. Typical 8088 System
5-7
inter
8203
MULTlBUS·
TYPe
SYSTEM
BUS
8284A
READ
8288
"'OC
WRITE
MWTC
ROY
8086
BHEN
I
I
I
READ
WRITE
. X~:~~R I-+-+------I-~_i>_---I
UP
HIGH BYTE
WRITE
A17-419
/:--="'--"J
OTHER
IlEMORY
READY
INPUTS
.58.
BYlES
DATA
DO
OJ
,.
16
I
I
I
XACK
I
210444-8
Figure 11. 8086/256K Byte System
5-8
inter
8203
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... o·c to 70·C
+ 150·C
Storage Temperature .......... - 65·C to
Voltage On Any Pin
With Respect to Ground ......... - 0.5V to
+ 7V
Power Dissipation ...................... 1.6 Watts
D.C. CHARACTERISTICS
Symbol
T A = o·C to 70·C; Vcc = 5.0V
Parameter
Min
Max
± 10% (5.0V ± 5% for 8203-3); GND
Units
Vcc
Input Clamp Voltage
-1.0
V
Icc
Power Supply Current
290
mA
IF
Forward Input Current
ClK, 64K/16K Mode Select
All Other Inputs(3)
-2.0
-320
mA
iJ-A
VF = 0.45V
VF = 0.45V
40
iJ-A
VR = Vcd 1, 5)
0.45
0.45
V
V
IOL = 5 mA
IOL = 3 mA
V
V
VIL = 0.65V
IOH = -1 mA
IOH = -1 mA
0.8
V
Vcc = 5.0V(2)
Vcc
V
Vcc = 5.0V
Vcc
V
(4)
30
pF
F = 1 MHz(6)
VSIAS = 2.5V, Vcc = 5V
IR
Reverse Input Current(3)
VOL
Output low Voltage
SACK,XACK
All Other Outputs
VOH
VIL
Output High Voltage
SACK,XACK
All Other Outputs
2.4
2.6
Input low Voltage
VIH1
Input High Voltage
VIH2
Option Voltage
CIN
Input Capacitance
2.0
Ic= -5mA
NOTES:
1.
2.
3.
4.
= OV
Test Conditions
IR = 200 p.A for pin 37 (ClK).
For test mode RD & WR must be held at GND.
Except for pin 36 in XTAL mode.
8203-1 and 8203-3 support both OP1 and OP2, 8203 only supports OP2.
+12 Volt
5.1K\I
25
±10%
OP,
8203
lK
Resistor Tolerance:
36
:::!::
Of>:!
5%
210444-3
5. IR = 150 p.A for pin 35 (Mode Select 16K/64K).
6. Sampled not 100% tested, TA = 25°C.
5-9
inter
8203
A.C. CHARACTERISTICS
TJ = o·C to 70·C; vcc = 5V ± 10% (5.0V ±5% for 8203-3); GND = OV .
Measurements made with respect to RASa-RAS3, CAS, WE, OUTa-OUT6 are at 2.4V and 0.8V. All other pins
are measured at 1.5V. All times are in ns.
Symbol
Parameter
Notes
Min
Max
tp
Clock Period
40
54
tpH
External clock High Time
20
tpL
External Clock Low Time-:-Above (» 20 MHz
17
tpL
External Clock Low Time-Selow (";:) 20 MHz
tRC
Memory Cycle Time
tREF
Refresh Time (128 cycles)
tRP
RAS Precharge Time
4tp - 30
tRSH
RAS Hold After CAS
5tp - 30
3
tASR
Address Setup to RAS
tp - 30
3
tRAH
Address Hold From RAS
tp - 10
3
tASC
Address Setup to CAS
tp - 30
3
tCAH
Address Hold from CAS
5tp - 20
3
tCAs
CAS Pulse Width
5tp - 10
twcs
WE Setup to CAS
tp - 40
tWCH
WE Hold After CAS
5tp - 35
8
tRS
RD, WR, ALE, REFRQ Delay From RAS
5tp
2,6
tMRP
RD, WR Setup to RAS
0
5
tRMS
REFRQ Setup to RD, WR
2tp
6
tRMP
REFRQ Setup to RAS
2tp
5
tpcs
PCS Setup to RD, WR, ALE
20
tAL
S1 Setup to ALE
15
tLA
S1 Hold From ALE
30
tCR
RD, WR, ALE to RAS Delay
tp
tp
20
10tp - 30
12tp
264tp
2a8tp
+ 30
+ 25
2tp
+ 70
+ 85
4,5
2
tcc
RD, WR, ALE to CAS Delay
tsc
CMD Setup to Clock
15
1
tMRS
RD, WR Setup to REFRQ
5
2
4tp
tCA
RD, WR, ALE to SACK Delay
tcx
CAS to XACK Delay
5tp - 25
5tp
tcs
CAS to SACK Delay
5tp - 25
5tp
tACK
XACK to CAS Setup
10
txw
XACK Pulse Width
tCK
SACK, XACK Turn-Off Delay
tKCH
CMD Inactive Hold After SACK, XACK
2tp
+ 47
+ 20
+ 40
tp - 25
5-10
2,9
2, 10
7
35
10
2
inter
8203
A.C. CHARACTERISTICS (Continued)
TJ = O°C to 70°C; VCC = sv ± 10% (S.OV ±S% for 8203-3); GND = OV
Measurements made with respect to RASa-RAS3, CAS, WE, OUTa-OUT 6 are at 2.4V and 0.8V. All other pins
are measured at 1.SV. All times are in ns.
Symbol
Parameter
Min
tLL
REFRQ Pulse Width
20
tCHS
CMD Hold Time
30
tRFR
REFRQ to RAS Delay
Max
Notes
11
4tp
+
100
6
tww
WR to WE Delay
0
SO
8
tAD
CPU Address Delay
0
40
3
NOTES:
1. tsc is a reference point only. ALE, RD, WR, and REFRQ inputs do not have to be externally synchronized to 8203 clock.
2. If tRS min and tMRS min are met then tCA, tCR, and tcc are valid, otherwise tcs is valid.
3. tASR, tRAH, tASC, tCAH, and tRSH depend upon Bo-B1 and CPU address remaining stable throughout the memory cycle.
The address inputs are not latched by the 8203.
4. For back-to-back refresh cycles, tRC max = 13 tp.
5. tRC max is valid only if tRMP min is met (READ, WRITE followed by REFRESH) or tMRP min is met (REFRESH followed by
READ, WRITE).
6. tRFR is valid only if tRS min and tRMS min are met.
7. txw min applies when RD, WR has already gone high. Otherwise XACK follows RD, WR.
8. WE goes high according to tWCH or tww, whichever occurs first.
9. tCA applies only when in normal SACK mode.
10. tcs applies only when in delayed SACK mode.
11. tCHS must be met only to ensure a SACK active pulse when in delayed SACK mode. XACK will always be activated for
at least txw (tp - 25 ns). Violating tCHS min does not otherwise affect device operation.
WAVEFORMS
Normal Read or Write Cycle
210444-9
S-11
inter
8203
WAVEFORMS (Continued)
Advanced Read Mode
51 _______{
tAL·
-tLA}----------------
ALE
tRS---'-
4--~~--~-------------------J
210444-10
Memory Compatibility Timing
Al: '; ~6' ~~_-VALIDADD-RESS
AHO-AHS
.
~
_ _.
-~'A~-
-------------
•
--~~-
\
'I
tRSH
I
teAs
/
r\
_'ASR_
~
ROW
~'ASC-
I--'RAH ....
~
I---'CAH_
COLUMN
K
210444-11
5-12
intJ
8203
WAVEFORMS (Continued)
Write Cycle Timing
I
\
J
\.
.1
IC~-\
-MIN
-
.1
ICA
-MAX-
1/
\
..... twcs __
.
_tWCH
-
IWW
MAX
IWWH
MIN
'I
.
ICC
MIN
ICC
MAX
210444-12
Read or Write Followed By External Refresh
RD, ViA
\
\.
_
_IMRS _
REFRQ
j
I-:---IRS-
ILl_
/
\
\
.
tAMP
I-IAP-'--
ICA
---MAX-
1\
.
.
.
ICC
MIN
ICC
MAX
lAC
.\
.-t
X
210444-13
5-13
8203
WAVEFORMS (Continued)
External Refresh Followed By Read or Write
---l::::::::-'MR-P-=--=---~----------~----------REFRQ
i------1nc - - - - - - \
\----210444-14
Clock and System Timing.
__ tp_
elK
RD. WR,
ALE
210444-15
5-14
8203
The typical rising and fallin~haracteristic curves for
the OUT, RAS, CAS and WE output buffers can be
used to determine the effects of capacitive loading
on the A.C. Timing Parameters. Using this design
tool in conjunction with the timing waveforms, the
designer can determine typical timing shifts based
on system capacitive load.
Table 2. 8203 Output Loading. All specifications
are for the Test Load unless otherwise noted.
Test Load
Pin
SACK, XACK
OUTo-OUT6
RASo-RAS3
WE
CAS
CL
CL
CL
CL
CL
30 pF
160 pF
= 60 pF
= 224 pF
= 320 pF
=
=
Example: Find the effect on tCR and tcc using 32
64K Dynamic RAMs configured in 2 banks.
1) Determine the typical RAS and CAS capacitance:
From the data sheet RAS = 5 pF and CAS
5 pF.
A.C. TESTING LOAD CIRCUIT
:. RAS load = 80 pF
DEVICE
UNDER
TEST
CAS load
+
board capacitance.
= 160 pF + board capacitance.
Assume 2 pF/in (trace length) for board ca·
pacitance and for this example 4 inches for
RAS and 8 inches for CAS.
2) From the waveform diagrams, we determine that
the falling edge timing is needed for tCR and tcc.
Next find the curve that best approximates the
test load; i.e., 68 pF for RAS and 330 pF for CAS.
210444-16
NOTE:
CL includes jig capacitance.
3) If we use 88 pF for RAS loading, then tCR (min.)
spec should be increased by about 1 ns, and tCR
(max.) spec should be increased by about 2 ns.
Similarly if we use 176 pF for CAS, then tce (min.)
should decrease by 3 ns and tee (max.) should
decrease by about 7 ns.
5-15
8203
A.C. CHARACTERISTICS FOR DIFFERENT CAPACITIVE LOADS
1.0
r-_-,---r_ _-;_ _ _.,-_ _--r_ _ _,--_ _-,-_ _- ,_ _ __._---'C:;.;ATPA;.::.CI:;.;TA.;;.;N;.::.CE:.;.'-";PF
0 .•
I---+-~~
....311ii~~--+_--_1__--__1_--__4---'---_1__---l
o.o~--~--_t---~--~---L---~--~---L----L--~
TIME
r--In.~
210444-17
5.•
r-_ _~--t---T_--_._--.__--.__--_,_--....._--=CA:::;PA:::C::..::ITA::::N=C.~'.,.
~
~ ... t---+--;-~r'rt_~~~--+-__+--+--I_____f
o
TIME
NOTE:
210444-18
Use the Test Load as the base capacitance for estimating timing shifts for system critical timing parameters.
MEASUREMENT CONDITIONS
Pins not measured are loaded with the Test Load capacitance
TA = 25°C
Vee = +5V
tp = 50 ns
5-16
8206
ERROR DETECTION AND CORRECTION UNIT
•
Input and Output Busses.......No
• Separate
Timing Strobes Required
Detects All Single Bit, and Double Bit
and Most Multiple Bit Errors
All Single Bit Errors
• Corrects
8206-1
3 Selections
• Detection
35ns
Correction
•
8206
42ns
67 ns
55ns
Supports Read With and Without
Correction, Writes, Partial (Byte)
Writes, and Read-Modify-Writes
III Technology for Low Power
• 68HMOS
Pin Leadless JEDEC Package
•
•
Outputs for Error Logging
• Syndrome
Error Scrubbing with 8207
• Automatic
Expandable to Handle 80 Bit Memories
•
68 Pin Grid Array Package
The HMOS 8206 Error Detection and Correction Unit is a high-speed device that provides error detection and
correction for memory systems (static and dynamic) requiring high reliability and performance. Each 8206
handles 8 or 16 data bits and up to 8 check bits. 8206's can be cascaded to provide correction and detection
for up to 80 bits of data. Other 8206 features include the ability to handle byte writes, memory initialization, and
error logging.
,
DATA IN
LATCH
ST.
CBlISY1 0
.,
CHECK BIT
LATCH
•
--/-
ERR
GENERATOR
CHECK BIT
SYNDROME
PARTIAL PARITY
Cf
t
•
•
u·
SYNDROME
DECODER
ERROR
DETECTION
'llf
+
WRITE
PARTIAL PARITY
GENERATOR
-T
i----
2.0
0.8
0.45
TEST POINTS
<
2.0
0.8
x:=
DEVICE
UNDER
TEST
205220-14
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and O.8V for a Logic "0".
205220-15
CL Includes Jig Capacitance
5-29
8206
A.C. CHARACTERISTICS
= O°C to 70°C. VCC = +5V ±
TA
Symbol
10%. VSS
=
OV. RL = 220. CL
=
50 pF; all times are in ns
8206-1
Parameter
Min
Max
8206
Min
Notes
Max
TRHEV
ERROR Valid from R/Vil i
20
25
TRHCV
CE Valid from R/W i (Single 8206)
34
44
TRHQV
Corrected Data Valid from RW i
44
54
1
TRVSV
SYO/CBO/PPO Valid from R/W
32
42
1
TOVEV
ERROR Valid from Data/Check Bits In
35
42
Tovcv
CE Valid from Data/Check Bits In
50
70
TOVQV
Corrected Data Valid from Data/Check Bits In
55
67
Tovsv
SYO/PPO Valid from Data/Check Bits In
40
55
TSHQV
Corrected Data Access Time
TSXQX
Hold Time from Data/Check Bits In
TSLQZ
Corrected Data Float Delay
0
TSHIV
STB High to Data/Check Bits In Valid
30
TIVSL
Data/Check Bits In to STB
TSLIX
Data/Check Bits In from STB .J, Hold
J,
37
35
0
0
Set-Up
25
0
1
28
30
5
5
15
25
1
2
TpVEV
ERROR Valid from Partial Parity In
21
30
3
TpVQV
Corrected Data (Master) from Partial Parity In
46
61
1. :3
Tpvsv
Syndrome/Check Bits Out from Partial Parity In
32
43
1.3
TSVQV
Corrected Data (Slave) Valid from Syndrome
41
51
3
Tsvcv
CE Valid from Syndrome (Slave Number 1)
43
48
3
TQVQV
Check Bits/Partial Parity Out from Write Data In
TRHSX
Check Bits/Partial Parity Out from R/W. WZ Hold
0
0
TRLSX
Syndrome Out from R/W Hold
0
0
TQXQX
Hold Time from Write Data In
0
0
1
TSVRL
Syndrome Out to R/W J, Set-Up
5
17
3
TOVRL
Data/Check Bits to R/W Set-Up
24
39
1
44
64
TOVQU
Uncorrected Data Out from Data In
29
32
TTVQV
Corrected Data Out from CRCT J,
25
30
TWLQL
WZ J, to Zero Out
TWHQX
Zero Out from WZ i Hold
25
0
NOTES:
1. A.C. Test Levels for eso and 00 are 2.4V and O.BV.
2. TSHIV is required to guarantee output delay timings: TDVEV. TDVCV. TDVQV. TDVSV. TSHIV
pulse width of 35 ns.
3. Not required for B/16 bit systems.
5-30
1
1
30
0
0
+ TIVSL guarantees a min STS
inter
8206
WAVEFORMS
READ
STB7:
l
I:SHI~I'
N'-----4-1----I~
·1
TiVSl
RIW_--I'~
1
1
:
1
1
1
1
1
1
~
~ ---;-1: ~I
~1 ' - - - - - 1
-!'
cg:
DO
I
1
1
1
1
j--TBHOV-j
1
i
-----<} i
1•
1TRHOV
I
I
"',.
1
1
1
1
1
r--- TBlOl
~:
.1
I
~'"'..
W~MVALIO
:
I,
SYO
I
TRVSV
,
I
fC
1
1
~.+-1- - - - T D V O V ' - - - - - - J . I
1
!.
~l~TRHEV:::::;:::;:::;:~~_
ERROR
---+-i >W/ffff//A
141
14 1
x=
_ I
VALID
---f----':
I
_I
TOVEV
Tovev
~
1
l'M
1-4+-1- - _ · T O v s v _ _ _--+!.1
-I
~
1
1
----+----t-"!>0'm7hW
~
_I
1
.
_I
1
x==
_~I~I~.~~~TR~HeV~~~~~.I~------~1
W~A
eE _ _
VALID
205220-16
5-31
inter
8206
WAVEFORMS
(Continued)
READ-MASTER/SLAVE
ft'-------I
'" :),l--lTsHlv
I
1
1
,
1
Rw_~UI
V 1
,-I
'
, I
TSLlX,
TlVSL''----.l
~
1
, 1:7t '
-----',--'-,-'
----<¢ i
I
" ,
i
I'
I
~
""," I
TRVSVI:I
::.~~:~:::: _w~a
,
1
I
i
I
i
I-TDXOX_,
1
""'"
x.-'--:-
-l
,__ TP~
,
1
-WYL7$
OOIMASTER) - - - . - - - - :
I
1
VALID
I
DOISLAVE)
:
4L
1
$1I
'_TPVSV_I
SYO(MASTER)~>47//;WA///
SYI(SLAVE)-
I
'"
'{~---r:---
: I'
1
~
cg:
Ir--,
TBLOZ _ _
XI_ :
VALID
4
,
,
1_Tsvov-i
I
-----'-I-ez!7AWA
VALID
~
I
~~~,
,
Vo/~'~~TR~HEV~~.~"_ _ _ _ _ _ _ _ _ _ ~/
ERROR_/~//////&:
.
I
'I.
VALID
~I,---,_
;SVCV.I
TRHCV
CE
------>V7////00WA
I
.1
VALID
X_,_
205220-17
5-32
intJ
8206
WAVEFORMS (Continued)
FULL WRITE
~r
:z:
~
---------
z
>
!II
-l~
--
-
--
0
~
~
---,-
~
~
"'
ID
U
Q
W
~
ii:
~
r
z
>
!II
c
I~
~
o
Q
oID
U
o
>
!II
5-33
intJ
8206
WAVEFORMS (Continued)
FULL WRITE-MASTERISLAVE
en
I
~
o
C\I
ID
U
!
~
c
w
!::
~
~l-------
z
>
III
5o
S
c
~
iii
Q
....~
~
0c
!!!.
0
II.
II.
5-34
~
0
I-
!.!
0
>
III
w
II)
'"
!
ii:
II.
ID
:II
STB
J
J2f \
01 I ..
TIVSl
~r
=-vr
'{
x
\
I 1
I I
I
1
1
1
I
I I
(]I
t.J
(]I
1
I
\
1 I.
...
OOIWOI
1
:
TRHQV
TOVQV
ITRHSX
IT!
lJ
s:::
en
0a
::::I
0".
::::I
c:
(f)
S
\
---'I+,~-Bl~-i-1°1
I...
"I
I
.
..\
TRVSV
\
\
TDXQX
W/
:
4:\
CI
\
:
I
o
en
--l t- \ I
Hi
-l l -
M
I-TRlSX
I I .\ I
I I
I
TQVQV
I
x=
\
SYNX7/4
I..
:
rQXQX
.. \
.. \
\
~
X0~/%~/%-r--rZ--.-:-J'4--:...:
TOVSV
1
f :I
I
I
I'
::::j
t
____
i "u.:
II
SYO/C80
:II
<
m
"T1
0
--
I\,)
I:
I I
I"
=n
:E
-<
:el>
~
: :
\
I
,g: -{:
I
\
VAllO:
\
C
I
I
\
I
1 - TBHQV -.J
iii:
0
A----4-:-
1
TOVRl
l l
ij:
..
.. '_TRVSV-----l
I
I" I
BM
TSllX
1 \
I I
I
Joo
c
... --f'{-,;;..i_________
TS1IVI"
RfW
IT!
1
CB
I
.. \
205220-20
8206
WAVEFORMS (Continued)
READ MODIFY WRITE-MASTER/SLAVE
N
I
o
N
N
'"o
N
III
o
::;
~
T
o
~;::
::;
~
----c-
.L
UI
--i:--
- T--P!...-,rt- ~L.:..._
>
~
-_-k
Sii
u
5-36
U
8206
WAVEFORMS
(Continued)
NON-CORRECTING READ
...
...a:t>
Q
l-
a:
o
t>
Z
:)
T--o>
-------
...t;
...a:
Q
~
a:
o
t>
Z
:)
eiiit>
1M
5-37
inter
8206
WAVEFORMS (Continued)
WRITE ZERO
'"
C\J
I
~
"'
o
C\J
r--------
o
I~
o
o
o
III
(5
>
'"
5-38
8207
DUAL-PORT DYNAMIC RAM CONTROLLER
•
•
•
•
•
•
Provides All Signals Necessary to
Control 16K, 64K and 256K Dynamic
RAMs
Directly Addresses and Drives up to 2
Megabytes without External Drivers
Supports Single and Dual-Port
Configurations
Automatic RAM Initialization in All
Modes
Four Programmable Refresh Modes
Transparent Memory Scrubbing in ECC
Mode
•
•
Fast Cycle Support for 8 MHz 80286
with 8207-16
•
Provides Signals to Directly Control the
8206 Error Detection and Correction
Unit
•
•
Supports Synchronous or
Asynchronous Operation on Either Port
Slow Cycle Support for 8 MHz, 10 MHz
8086/88, 80186/188 with 8207-8,
8207-10
68 Lead JEDEC Type A Leadless Chip
Carrier (LCC) and Pin Grid Array (PGA),
Both in Ceramic.
The Intel 8207 Dual-Port Dynamic RAM Controller is a high-performance, systems-oriented, Dynamic RAM
controller that is designed to easily interface 16K, 64K and 256K Dynamic RAMs to Intel and other microprocessor systems. A dual-port interface allows two different busses to independently access memory. When
configur~d with an 8206 Error Detection and Correction Unit the 8207 supplies the necessary logic for designing large error-corrected memory arrays. This combination provides automatic memory initialization and transparent memory error scrubbing.
ERROR
LOCK
RDA
wll.
PEA
LEN
PellA
XACKAJACKA
XACKBIACKB
~~::~
DBM
EST8
ROB
WQ
MU)(JPCLK
PSEL
PSEN
WE
PCTLa
PEii
RFRQ
CAS o
J
PDI--t-~-l
~===~)Ao,.
BS o ' '---------,/1
210463-1
Figure 1. 8207 Block Diagram
5-39
September 1987
Order Number: 210463-007
inter
8207
Table 1. Pin Description
Pin
Type
LEN
Symbol
1
0
ADDRESS LATCH ENABLE: In two-port configurations, when Port A is
running with iAPX 286 Status interface mode, this output replaces the ALE _
signal from the system bus controller of port A and generates an address
latch enable signal which provides optimum setup and hold timing for the
8207. This signal is used in Fast Gycle operation only.
XAGKAI
AGKA
2
0
TRANSFER ACKNOWLEDGE PORT A/ACKNOWLEDGE PORT A: In nonEGC mode, this pin is XAGKA and indicates that data on the bus is valid
during a read cycle or that data may be removed from the bus during a write
cycle for Port A. XAGKA is a Multibus-compatible signal. In EGG mode, this
pin is AGKA which can be configured, depending on the programming of the X
program bit, as an XAGK or AAGK strobe. The SA programming bit
determines whether the AAGK will be an early EAAGKA or a late LAAGKA
interface signal.
XAGKBI
AGKB
3
0
TRANSFER ACKNOWLEDGE PORT B/ACKNOWLEDGE PORT B: In nonEGG mode, this pin is XAGKB and indicates that data on the bus is valid
during a read cycle or that data may be removed from the bus during a write
cycle for Port B. XAGKB is a Multibus-compatible signal. In EGG mode, this
pin is AGKB which can be configured, depending on the programming of the X
program bit, as an XAGK or AAGK strobe. The SB programming bit
determines whether the AAGK will be an early EAAGKB or a late LAAGKB
interface signal.
AAGKAI
4
0
ADVANCED ACKNOWLEDGE PORT A/WRITE ZERO: In non-EGG mode,
this pin is AAGKA and indicates that the processor may continue processing
and that data will be available when required. This signal is optimized for the
system by programming the SA program bit for synchronous or asynchronous
operation. In EGG mode, after a RESET, this signal will cause the 8206 to
force the data to all zeros and generate the appropriate check bits.
AAGKBI
R/W
5
0
ADVANCED ACKNOWLEDGE PORT B/READ/WRITE: In non-EGG mode,
this pin is AAGKB and indicates that the processor may continue processing
and that data will be available when required. This signal is optimized for the
system by programming the SB program bit for synchr~mous or asynchronous
operation. In EGG mode, this signal causes the 8206 EDGU to latch the
syndrome and error flags and generate check bits.
DBM
6
0
DISABLE BYTE MARKS: This is an EGG control output signal indicating that
a read or refresh cycle is occurring. This output forces the byte address
decoding logic to enable all 8206 data output buffers. In EGG mode, this
output is also asserted during memory initialization and the 8-cycle dynamic
RAM wake-up exercise. In non-EGG systems this signal indicates that either a
read, refresh or 8-cycle warm-up is in progress.
ESTB
7
0
ERROR STROBE: In EGG mode, this strobe is activated when an error is
detected and allows a negative-edge triggered flip-flop to latch the status of
the 8206 EDGU GE for systems with error logging capabilities. ESTB will not
be issued during refresh cycles.
LOGK
8
I
LOCK: This input instructs the 8207 to lock out the port not being serviced at
the time LOGK was issued.
9
I
DRIVER POWER: + 5 volts. Supplies Vee for the output drivers.
LOGIC POWER: + 5 volts. Supplies Vee for the internal logic circuits.
I
CORRECTABLE ERROR: This is an EGG input from the 8206 EDGU which
instructs the 8207 whether a detected error is correctable or not. A high input
indicates a correctable error. A low input inhibits the 8207 from activating WE
to write the data back into RAM. This should be connected to the GE output of
the 8206.
WZ
Vee
43
GE
10
Name and Function
5-40
inter
8207
Table 1. Pin Description (Continued)
Symbol
Pin
Type
ERROR
11
I
ERROR: This is an ECC input from the 8206 EOCU and instructs the 8207
that an error was detected. This pin should be connected to the ERROR
output of the 8206.
MUX/
PCLK
12
0
MULTIPLEXER CONTROL/PROGRAMMING CLOCK: Immediately after a
RESET this pin is used to clock serial programming data into the POI pin. In
normal two-port operation, this pin is used to select memory addresses from
the appropriate port. When this signal is high, port A is selected and when it is
low, port B is selected. This signal may change state before the completion of
a RAM cycle, but the RAM address hold time is satisfied.
PSEL
13
0
PORT SELECT: This signal is used to select the appropriate port for data
transfer. When this signal is high port A is selected and when it is low port B is
selected.
PSEN
14
0
PORT SELECT ENABLE: This signal used in conjunction with PSEL provides
contention-free port exchange on the data bus. When PSEN is low, port
selection is allowed to change state.
WE
15
0
WRITE ENABLE: This signal provides the dynamic RAM array the write
enable input for a write operation.
FWR
16
I
FULL WRITE: This is an ECC input signal that instructs the 8207, in an ECC
configuration, whether the present write cycle is normal RAM write (full write)
or a RAM partial write (read-modify-write) cycle.
RESET
17
I
RESET: This signal causes all internal counters and state flip-flops to be reset
and upon release of RESET, data appearing at the POI pin is clocked in by the
PCLK output. The states of the POI, PCTLA, PCTLB and RFRQ pins are
sampled by RESET going inactive and are used to program the 8207. An 8cycle dynamic RAM warm-up is performed after clocking POI bits into the
8207.
18-21
0
COLUMN ADDRESS STROBE: These outputs are used by the dynamic RAM
array to latch the column address, present on the AOO-8 pins. These outputs
are selected by the BSO and BS1 as progiammed by program bits RBO and
RB 1. These outputs drive the dynamic RAM array directly and need no
external drivers.
RASO-RAS3 22-25
0
ROW ADDRESS STROBE: These outputs are used by the dynamic RAM
array to latch the row address, present on the AOO-8 pins. These outputs are
selected by the BSO and BS1 as programmed by program bits RBO and RB1.
These outputs drive the dynamic RAM array directly and need no external
drivers.
Vss
26
60
I
I
DRIVER GROUND: Provides a ground for the output drivers.
LOGIC GROUND: Provides a ground fo~ the remainder of the device.
AOO-A08
35-27
0
ADDRESS OUTPUTS: These outputs are designed to provide the row and
column addresses of the selected port to the dynamic RAM array. These
outputs drive the dynamic RAM array directly and need no external drivers.
BSO-BS1
36-37
I
BANK SELECT: These inputs are used to select one of four banks of the
dynamic RAM array as defined by the program bits RBO and RB1.
ALO-AL8
38-42
44-47
I
ADDRESS LOW: These lower-order address inputs are used to generate the
row address for the internal address multiplexer.
AHO-AH8
48-56
I
ADDRESS HIGH: These higher-order address inputs are used to generate
the column address for the internal address multiplexer.
CASO-CAS3
Name and Function
5-41
8207
Table 1. Pin Description (Continued)
Symbol
Pin
Type
Name and Function
POI
57
I
PROGRAM DATA INPUT: This input programs the various user-selectable
options in the 8207. The PClK pin shifts programming data into the POI input
from optional external shift registers. This pin may be strapped high or low to
a default ECC (POI = logic "1") or non"ECC (POI = logic "0") mode
configuration.
RFRO
58
I
REFRESH REQUEST: This input is sampled on the falling edge of RESET. If
it is high at RESET, then the 8207 is programmed for internal refresh request
or external refresh request with failsafe protection. If it is low at RESET, then
the 8207 is programmed for external refresh without failsafe protection or
burst refresh. Once programmed the RFRO pin accepts signals to start an
external refresh with failsafe protection or external refresh without failsafe
protection or a burst refresh.
ClK
59
I
CLOCK: This input provides
ROB
61
I
READ FOR PORT 8: This pin is the read memory request command input for
port B. This input also directly accepts the S1 status line from Intel
processors.
WRB
62
I
WRITE FOR PORT 8: This pin is the write memory request command input
for port B. This input also directly accepts the SO status line from Intel
processors.
PEB
63
I
PORT ENA8LE FOR PORT 8: This pin serves to enable a RAM cycle request
for port B. It is generally decoded from the port address.
PCTlB
64
I
PORT CONTROL FOR PORT 8: This pin is sampled on the falling edge of
RESET. If low after RESET, the 8207 is programmed to accept memory read
and write commands, Multibus commands or iAPX 286 status inputs. If high
after RESET, the 8207 is p!:2flrammed to accept status inputs from iAPX 86 or
iAPX 186 processors. The S2 status line should be connected to this input if
programmed to accept iAPX 86 or iAPX 186 status inputs. When programmed
to accept commands or iAPX 286 status, it should be tied low or it may be
used as a Multibus-compatible inhibit signal.
ROA
65
I
READ FOR PORT A: This pin is the read memory request command input for
port A. This input also directly accepts the S1 status line from Intel
processors.
WRA
66
I
WRITE FOR PORT A: This pin is the write memory request command input
for port A. This input also directly accepts the SO status line from Intel
processors.
PEA
67
I
PORT ENA8LE FOR PORT A: This pin serves to enable a RAM cycle request
for port A. It is generally decoded from the port address.
PCTlA
68
I
PORT CONTROL FOR PORT A: This pin is sampled on the falling edge of
RESET. If low after RESET, the 8207 is programmed to accept memory read
and write commands, Multibus commands or iAPX 286 status inputs. If high
after RESET, the 8207 is p!:2flrammed to accept status inputs from iAPX 86 or
iAPX 186 processors. The S2 status line should be connected to this input if
programmed to accept iAPX 86 or iAPX 186 status inputs. When programmed
to accept commands or iAPX 286 status, it should be tied low or it may be
connected to INHIBIT when operating with Multibus.
5-42
th~
basic timing for sequencing the internal logic.
inter
8207
structures. The ports are independently configurable
allowing the dynamic RAM to serve as an interface
between two different bus structures.
GENERAL DESCRIPTION
The Intel 8207 Dual-Port Dynamic RAM Controller is
a microcomputer peripheral device which provides
the necessary signals to address, refresh and directly drive 16K, 64K and 256K dynamic RAMs. This
controller also provides the necessary arbitration circuitry to support dual-port access of the dynamic
RAM array.
Each port of the 8207 may be programmed to run
synchronous or asynchronous to the processor
clock. (See Synchronous/Asynchronous Mode.) The
8207 has been optimized to run synchronously with
Intel's iAPX 86, iAPX 88, iAPX 186, iAPX 188, and
iAPX 286. When the 8207 is programmed to run in
asynchronous mode, the 8207 inserts the necessary
synchronization circuitry for the RD, WR, PE, and
PCTL inputs.
The 8207 supports several microprocessor interface
options including synchronous and asynchronous
connection to iAPX 86, iAPX 88, iAPX 186,
iAPX 188, iAPX 286 and Multibus.
The 8207 achieves high performance (Le., no wait
states) by decoding the status lines directly from the
iAPX 86, iAPX 88, iAPX 186, iAPX 188 and iAPX 286
processors. The 8207 can also be programmed to
receive read or write Multibus commands or commands from a bus controller. (See Status/Command
Mode.)
This device may be used with the 8206 Error Detection and Correction Unit (EDCU). When used with
the 8206, the 8207 is programmed in the Error
Checking and Correction (ECG) mode. In this mode,
the 8207 provides all the necessary control signals
for the 8206 to perform memory initialization and
transparent error scrubbing during refresh.
The 8207 may be programmed to accept the clock
of the iAPX 86, 88, 186, 188 or 286. The 8207 adjusts its internal timing to allow for the different clock
frequencies of these microprocessors. (See Microprocessor Clock Frequency Option.)
FUNCTIONAL DESCRIPTION
Processor Interface
Figures 2A and 29 show the different processor interfaces to the 8207 using the synchronous or asynchronous mode and status or command interface.
The 8207 has control circuitry for two ports each
capable of supporting one of several possible bus
5-43
intJ
8207
1 1 - - - - - 1 Wfl CLK
1----.lRfi
8207
1-----.-4 Rl!
CLK
210463-2
Slow-Cycle SynchronousStatus Interface
=~
SO
SlH_H...J
52
ADDR.lDATA
210463-3
Slow-Cycle Asynchronous-Status Interface
210463-5
210463-4
Slow-Cycle Asynchronous-Command Interface
Slow-Cycle Synchronous-Command Interface
Figure 2A. Siow-Cycle (CFS
=
0) Port Interfaces Supported by the 8207
by the 8207. The 8207 arbitrates between each of
the processor requests and directs data to or from
the appropriate port. Selection is done on a priority
concept that reassigns priorities based upon past
history. Processor requests are internally queued.
Single-Port Operation
The use of an address latch with the iAPX 286
status interface is not needed since the 8207 can
internally latch the addresses with an internal signal
similar in behavior to the LEN output. This operation
is active only in single-port applications when the
processor is interfaced to port A.
Figure 3 shows a dual-port configuration with two
iAPX 86 systems interfacing to dynamic RAM. One
of the processor systems is interfaced synchronously using the status interface and the other is interfaced asynchronously also using the status interface.
Dual-Port Operation
The 8207 provides for two-port operation. Two independent processors may access memory controlled
5-44
intJ
8207
210463-7
210463-6
NOTE:
Address latch not required in single-port mode.
NOTE:
Address latch not required in single-port mode.
Fast-Cycle Asynchronous-Status Interface
Fast-Cycle Synchronous-Status Interface
SYNCHRONOUS 80286
210463-9
210463-6
·MULTI·BUS Option
Fast-Cycle Synchronous-Command Interface
Fast-Cycle Asynchronous-Command Interface
Figure 2B. Fast-Cycle (CFS= 1) Port Interfaces Supported by the 8207
ror scrubbing during ECC refresh cycles. RAM cycle
interleaving overlaps the start of the next RAM cycle
with the RAM Precharge period of the previous cycle. Hiding the precharge period of one RAM cycle
behind the data access period of the next RAM cycle optimizes memory bandwidth and is effective as
long as successive RAM cycles occur in alternate
banks.
Dynamic RAM Interface
The 8207 is capable of addressing 16K, 64K and
256K dynamic RAMs. Figure 4 shows the connection of the processor address bus to the 8207 using
the different RAMs.
The' 8207 divides memory into as man~ four
banks, each bank having its own Row (RAS) and
. Column (CAS) Address Strobe pair. This organization permits RAM cycle interleaving and permits er-
Successive data access to the same bank will cause
the 8207 to wait for the precharge time of the previous RAM cycle.
5-45
.......
READY ROY'
~ OTII£A ~ iNPUTS
W£
ALE
I2U- DEN
READY elK 52
cC
c
Ii
~
~
o
~
~
Q)
J
CAs",
r-
WE
T
$
t
elK
52
~
MEMORY
(Ul'PEA)
elK
"....-'
"DORIOATA
~
N
C
.....
EXTENDED MEMORY USING STATUS.
PORT A-SYNCHAONIGUS;
PORT B-ASYNCHR
<0 iii
0'
...
CMDIPEA
-
ADDR A
:J
C
VI
5'
\Q
:T
ACKA
DEN A
DTIR A
-
.
V
MUX
ADDR
ACKA
71
"-.I
III
:J
BYTE
MARK
DECODER
r-----c:
6MHz
1
0
iAPX286
~12
1
1
iAPX 286
>12 MHz
Fast Processor Clock Frequency (16 MHz)
"Most Recently Used" Priority Scheme
4 RAM banks ocuppied
5-55
Processor
Clock
Frequency
6MHz
MHz
8207
The external clock frequency must be programmed
so that the failsafe refresh repetition circuitry can
adjust its internal timing accordingly to produce a
refresh request as programmed.
tween refreshes is decreased by 0%,10%,20%, or
30% as a function of bow the count interval bits are
programmed. A 5% guardband is built-in to allow for
any clock frequency variations. Table 6 shows the
refresh period options available.
RAM Speed Option (RFS Program Bit)
The numbers tabulated under Count Interval represent the number of clock periods between internal
refresh requests. The percentages in parentheses
represent the decrease in the interval between refresh requests. Note that all intervals have a built-in
5% (approximately) safety factor to compensate for
minor clock frequency deviations 'and non-immediate response to internal refresh requests.
The RAM Speed programming option determines
whether RAM timing will be optimized for a fast or
slow RAM.
Refresh Period Options
(CIO, CI1 and PLS Program Bits)
The 8207 refreshes with either 128 rows every 2
milliseconds or 256 rows every 4 milliseconds. This
translates to one refresh cycle being executed approximately once every 15.6 microseconds. This
rate can be changed to 256 rows every 2 milliseconds or a refresh approximately once every 7.8 microseconds via the Period Long/Short, program bit
PLS, programming option. The 7.8 microsecond refresh request rate is intended for those RAMs, 64K
and above, which may require a faster refresh rate.
Extend Option (EXT Program Bit)
The Extend option lengthens the memory cycle to
allow longer access time which may be reqUired by
the system. Extend alters the RAM timing to compensate for increased loading on the Row' and Column Address Strobes, and in the multiplexed Address Out lines.
Port Priority Option and Arbitration
(PPR Program Bit)
In addition to PLS program option, two other programming bits for refresh exist: Count Interval 0
(CIO) and Count Interval 1 (CI1). These two programming bits allow the rate at which refresh requests
are generated to be increased in order to permit refresh requests to be generated close to the same
15.6 or 7.8 microsecond period when the 8207 is
operating at reduced frequencies. The interval be-
The 8207 has to internally arbitrate among three
ports: Port A, Port B and Port C-the refresh port.
Port C is an internal port dedicated to servicing refresh requests, whether they are generated internally by the refresh interval counter, or externally by the
user. Two arbitration approaches are available via
Table 6. Refresh Count Interval Table
Ref.
Period
(p.s)
CFS
PLS
FFS
15.6
1
1
7.8
1
15.6
1
Count Interval C11, CIO
(8207 Clock Periods)
00
(0%)
01
(10%)
10
(20%)
11
(30%)
1
236
212
188
164
0
1
118
106
94
82
1
0
148
132
116
100
7.8
1
0
0
74
66
58
50
15.6
0
1
1
118
106
'94
82
7.8
0
0
1
59
53
47
41
15.6
0
1
0
74
66
58
50
7.8
0
0
0
' 37
33
29
25
NOTE:
Refresh period = clock period x refresh count interval.
5-56
intJ
8207
that the other two ports are idle. Under normal operating conditions, this arbitration time is hidden behind the RAM cycle of the selected port so that as
soon as the present cycle is over a new cycle is
started. Table 7 lists the arbitration rules for both
options.
the Port Priority programming option, program bit
PPR. PPR determines whether the most recently
used port will remain selected (PPR = 1) or whether
Port A will be favored or preferred over Port B
(PPR = 0).
A port is selected if the arbiter has given the selected port direct access to the timing generators. The
front-end logic, which includes the arbiter, is designed to operate in parallel with the selected port.
Thus a request on the selected port is serviced immediately. In contrast, an unselected port only has
access to the timing generators through the frontend logic. Before a RAM cycle can start for an unselected port, that port must first become selected
(Le., the MUX output now gates that port's address
into the 8207 in the case of Port A or B). Also, in
order to allow its address to stabilize, a newly selected port's first RAM cycle is started by the front-end
logic. Therefore, the selected port has direct access
to the timing generators. What all this means is that
a request on a selected port is started immediately,
while a request on an unselected port is started two
to three clock periods after the request, assuming
Port LOCK Function
The LOCK function provides each port with the ability to obtain uninterrupted access to a critical region
of memory and, thereby, to guarantee that the opposite port cannot "sneak in" and read from or write to
the critical region prematurely.
Only one LOCK pin is present and is multiplexed
between the two ports as follows: when MUX is high,
the 8207 treats the LOCK input as originating at
PORT A, while when MUX is low, the 8207 treats
LOCK as originating at PORT B. When the 8207 recognizes a LOCK, the MUX output will remain pointed
to the locking port until LOCK is deactivated. Refresh is not affected by LOCK and can occur during
a locked memory cycle.
Table 7. The Arbitration Rules for the Most Recently Used Port Priority
and for Port A Priority Options Are As Follows:
1.
If only one port requests service, then that port-if not already selected-becomes
selected.
2a.
When no service requests are pending, the last selected processor port (Port A or B) will
remain selected. (Most Recently Used Port Priority Option.)
2b.
When no service requests are pending, Port A is selected whether it requests service or
not. (Port A Priority Option.)
3.
During reset initialization only Port C, the refresh port, is selected.
4.
If no processor requests are pending after reset initialization, Port A will be selected.
5b.
If Ports A and B simultaneously(*) request service while Port C is selected, then the next
port to be selected is Port A. (Port A Priority Option.)
6.
If a port simultaneously requests service with the currently selected port, service is granted
to the selected port.
7.
The MUX output remains in its last state whenever Port C is selected.
8.
If Port C and either Port A or Port B (or both) simultaneously request service, then service
is granted to the requester whose port is already selected. If the selected port is not
requesting service, then service is granted to Port C.
9.
If during the servicing of one port, the other port requests service before or simultaneously
with the refresh port, the refresh port is selected. A new port is not selected before the
presently selected port is deactivated.
10.
Activating LOCK will mask off service requests from Port B if the MUX output is high, or
from Port A if the MUX output is low.
NOTE:
'By "simultaneous" it is meant that two or more requests are valid at the clock edge at which the internal arbiter samples
them.
5-57
inter
8207
two latches, and the use of flip flops on the status
lines of the asynchronous processor for delaying the
status and thereby guaranteeing RAS will not be issued, even in the worst case, until address is valid.
Dual-Port Considerations
For both ports to be operated synchronously, several conditions must be met. The processors must be
the same type (Fast or Slow Cycle) as defined by
Table 8 and they must have synchronized clocks.
Also when processor types are mixed, even though
the clocks may be in phase, ~ne frequency may be
twice that of the other: So to run both portssynchronous using the status interface, the processors must
have related timings (both phase and frequency). If
these conditionscannot be met, then one port must
run synchronous and the other asynchronous.
Processor Timing
In order to run without wait states, AACK must be
used and connected to the SRDY input of the appropriate bus controller. AACK is issued relative to a
point within the RAM cycle and has no fixed relationship to the processor's request. The timing is such,
however, that the processor will run without wait
states, barring refresh cycles, bank precharge, and
RAM accesses from the other port. In non-ECC fast
cycle, fast RAM, non-extended configurations
(80286), AACK is issued on the next falling edge of
Figure 3 illustrates an example of dual-port operation using the processors in the slow cycle group.
Note the use of cross-coupled NAND gates at the
MUX output for minimizing contention between the
CLK
I
1
I
1
I
ADDRESS
~
VALID
SO,Sf
\
PE
/
/
\
I
LEN
/t,
1/
I
\
RAS'
-I
CAS
/
PSEN
/
\
/
\
/
\
/
I
1
I
I
1
1
\~
"----I
1\
\
V
V'
\
\
/
EAACK
/\
/\
;-\
\
\
/
I
I
~
I
X
PSEL
X
VALID
X
VALID
I
I
RAM DATA
I
I
I
(
I •
I
CYCLE DELAYED BY
ACCESS ON OTHER
PORT, REFRESH CYCLE
OR BANK PRECHARGE
VALID
'I1lZi
VALID
\
I
/
\
wA
VALID
~
_1-
(
CYCLE WITHOUT
WAIT STATES
yALID
~
)
C
---1
I
210463-20
NOTE:
1. The RAS and CAS shown in figure are different banks being accessed.
Figure 14. iAPX 286/8207 Synchronous-Status Timing Programmed in
non-ECC Mode, COConfiguration (Read Cycle)
5-58
inter
8207
the clock after the edge that issues RAS. In nonECC, slow cycle, non-extended, or extended with
fast RAM cycle configurations (8086, 80188, 80186),
AACK is issued on the same clock cycle that issues
RAS. Figure 14 illustrates the timing relationship between AACK, the RAM cycle, and the processor cycle for several different situations.
the internal synchronization delay to be added to the
status (or command)-to-PE delay time, thus allowing
for more external decode time that is available in
synchronous operation.
The minimum synchronization delay is the additional
amount that PE must be held valid. If PE is not held
valid for the maximum synchronization delay time, it
is possible that PE will go invalid prior to the status
or command being synchronized. In such a case the
8207 aborts the cycle. If a memory cycle intended
for the 8207 is aborted, then no acknowledge
(AACK or XACK) is issued and the processor locks
up in endless wait states. Figure 15 illustrates the
status (command) timing requirements for synchronous and asynchronous systems. Figures 16 and 17
show a more detailed hook-up of the 8207 to the
8086 and the 80286, respectively.
Port Enable (PE) setup time requirements depend
on whether the associated port is configured for synchronous or asynchronous fast or slow cycle operation. In a synchronous fast cycle configuration, PE is
required to be setup to the same clock edge as the
status or commands. If PE is true (low), a RAM cycle
is started; if not, the cycle is aborted. The memory
cycle will only begin when both valid signals (PE and
RD or WR) are recognized at a particular clock edge.
In asynchronous operation. PE is required to be setup to the same clock edge as the internally synchronized status or commands. Externally, this allows
8207 ClK
--@
-@
210463-21
(A) PE Set-Up and Hold Time Requirements for Fast Cycle,
Synchronous Operation (80286 CMD/Status)
8207 ClK
COMMAND/STATUS - - - - - - - - - - -
210463-22
(8) PE Timing Requirements for Fast or
Slow Cycle Asynchronous Operation
Figure 15
5-59
intJ
8207
8284A·
RDY 1 I~IOTHERACKINPUTS
READY
CLK
+
CLK
8288·
DEN
f---
CLK
DTiA ~
READY
RASo_3
CAS•. J
1,I
CLK
52
51
PCTL
MEMORY
(UPPER)
AOo_e
WE
~
~
v
8207
RD
SO
f-
MEMORY
(LOWER)
WR
80861
80186
VI
-
rv'
r
AHn .• ALo.. PSEN
OE
ADDRI
DATA
AACK
S2 S1S0ALE
STB
8283
LATCH
~
AD
TV~
OE
T
~
L.....
-
r-
=D-
DI
t
DO
I--
WE
r
I
DI
DO
D
ClK
Q~
~D
Y
Q~
16/
I
OE
T
16
'----
'---
~
D
8287
Vl
WE
8287
210463-23
NOTE:
'These components are not necessary when using the 80186. These functions are provided directly by the 80186.
Figure 16.8086/80186,8207 Single Port Non-ECC Synchronous Systems
Memory Acknowledge
(AACK, XACK)
(CFS = 0), while the SA and SB programming bits
optimize AACK for synchronous operation ("early"
AACK) or asynchronous operation ("late" AACK).
In system configurations without error correction,
two memory acknowledge signals per port are supplied by the 8207. They are the Advanced Acknowledge strobe (AACK) and the Transfer Acknowledge
strobe (XACK). The CFS programming bit determines for which processor AACKA and AACKB are
optimized, either 80286 (CFS = 1) or 8086/186
Both the early and late AACK strobes are three
clocks long for CFS = 1 and two clocks long for
CFS = o. The XACK strobe is asserted when data is
valid (for reads) or when data may be removed (for
writes) and meets the Multibus requirements. XACK
is removed asynchronously by the command going
5-60
8207
82284
READY SROY
~~NPUTS
ClK
+
ClK
82288
DEN
OT/R
M/iOs1S0
READY
f----
ClK
AACK
fAOOR,
STROBES
ClK
~I
51
~
M/iO
So
PCTl
==J
MEMORY
(UPPER)
8207
RO
WE
MEMORY
(lOWER)
-
WR
80286
r
AOORIN PSEN
AOOR
+
DATA
I-
AO'
+5V
TV}
T
WE
'-
".J
a
BHE'
:::D-
01
DO
WE
II
l
,--I
I
I
{r
01
DO
BO
Q~
OE
16
8287
~1
T
-
DE
'---8287
16
Ie
210463-24
NOTE:
While the 8207 does not need the input addresses latched, AO, SHE must come from the latched address bus.
Figure 17. 80286 Hook-Up to 8207 Non-ECC Synchronous System-Single Port
inactive. Since in asynchronous operation the 8207
removes read data before late AACK or XACK is
recognized by the CPU, the user must provide for
data latching in the system until the CPU reads the
data. In synchronous operation, data latching is unnecessary since the 8207 will not remove data until
the CPU has read it.
ming bit associated with each acknowledge. If the X
programming bit is active, the strobe is configured as
XACK, while if the bit is inactive, the strobe is configured as AACK. As in non-ECC, the SA and SB programming bits determine whether the AACK strobe
is early or late (EAACK or LAACK).
Data will always be valid a fixed time after the occurrence of the advanced acknowledge. Table 9 summarizes the various transfer acknowledge options.
In ECC-based systems there is one memory acknowledge (XACK or AACK) per port and a program-
5-61
8207
Table 8. Processor Interface/Acknowledge Summary
Cycle
Processor
Request Type
Sync/Async
Interface
Acknowledge
Type
80286
Status
Sync
EAACK
80286
Status
Async
LAACK
Fast
80286
Command
Sync
EAACK
Cycle
80286
Command
Async
LAACK
CFS=1
8086/80186
Status
Async
LAACK
8086/80186
Command
Async
LAACK
Multibus
Command
Async
XACK
8086/80186
Status
Sync
EAACK
Slow
8086/80186
Status
Async
LAACK
Cycle
8086/80186
Command
Sync
EAACK
CFS=O
8086/80186
Command
Async
LAACK
Multibus
Command
Async
XACK
Table 9. Memory Acknowledge Option Summary
Asynchronous
XACK
Fast Cycle
AACK Optimized
for Local 80286
Synchronous
AACK Optimized for
Remote 80286
Multibus Compatible
Slow Cycle
AACK Optimized
for Local 8086/186
AACK Optimized for
Remote 8086/186
Multibus Compatible
testing other than that covered in Test Mode 1, the
8207 will normally be set in Test Mode 2. Test Mode
2 eliminates memory initialization in ECC mode. This
allows quick examination of the circuitry which
brings the 8207 out of memory initialization and into
normal operation.
Test Modes
Two special test modes exist in the 8207 to facilitate
testing. Test Mode 1 (non-ECC mode) splits the refresh address counter into two separate counters
and Test Mode 2 (ECC mode) presets the refresh
address counter to a value slightly less than rollover.
General System Considerations
Test Mode 1 splits the address counter into two, and
increments both counters simultaneously with each
refresh address update. By generating external refresh requests, the tester is able to check for proper
operation of both counters. Once proper individual
counter operation has been established, the 8207
must be returned to normal mode and a second test
performed to check that the carry from the first
counter increments the second counter. The outputs
of the counters are presented on the address out
bus with the same timing as the row and column
addresses of a normal scrubbing operation. During
Test Mode 1, memory initialization is inhibited, since
the 8207, be definition, is in non-ECC mode.
The RASo_3, CASO_3, AOo-s, output buffers were
designed to directly drive the heavy capacitive loads
associated with dynamic RAM arrays. To keep the
RAM driver outputs from ringing excessively in the
system environment and causing noise in other output pins it is necessary to match the output impedance of the RAM output buffers with the RAM array
by using series resistors and to add series resistors
to other control outputs for noise reduction if necessary. Each application may have different impedance characteristics and may require different series
resistance values. The series resistance values
should be determined for each application. In nonECC systems unused ECC input pins should be tied
high or low to improve noise immunity.
Test Mode 2 sets the internal refresh counter to a
value slightly less than rollover. During functional
5-62
8207
34
33
32
31
3D
29
28
27
AD1
AD2
AD3
AD4
ADS
AD6
AD7
AD8
26 Vss
25 RAS3
24 RAS2
23 AAS1
22
21
20
19
1
RASO
CAS3
CAS2
CAS1
18 l:A];li
210463-25
NOTE:
Lee is mounted lid-down
into socket.
Figure 19_ 8207 Pinout Diagram
'TOP VIEW
- 68. 66- 64- 62. 60. 58- 56- 54- 52
- 1 .2 - 67- 65- 63. 61. 59. 57- 55- 53- 51
.3 .4
- 50. 49
Ceramic Pin Grid Array Package Type A
58-Lead Ceramic Pin Grid Array
Package Type A
j-- ~
1_
o
SWAGED PIN
STANDOFF
(4 PLACES)
.070 TYP.
(1.778)
(29.591) _
1.135 (28.829)
PIN 110
0
0
0
-48- 47
.7 .8
.9 .10
·46·45
-44- 43
-11-12
- 42- 41
·13-14
- 40- 39
-15-16
- 38- 37
- 17- 19- 21. 23. 25- 27- 29- 31- 33- 36- 35
- 18- 20- 22. 24. 26- 28. 30.32- 34
@@@
@@@@@@@@@
0
.5 .6
0
:~D~~ 1
o@
@@ 1.165 (29.591)
o@
@@ t135 (28.829) .122 (3.099)
o@
@@
L-[·r·m~8~(~2.4~8~9)________~
o@
@@
MAX
o@
@@ .140
(3.556)r-T
@@@@@@@@)8
@@@@@@@@@
STANDOFFIlJ
I
1
-1.000 REF
L.090 (2.286)
.060 (1.524)
210463-37
8207 Pin Grid Array (PGA) Pin-Out
e9: R 8207-8
e9: A 8207-16
LCC, 8 MHz DRAM Controller
PGA, 16 MHz DRAM Controller
NOTE:
The pin-out of the PGA is the same as the socketed pinout of the LCC.
Packaging
The 8207 is packaged in a 68 lead JEDEC Type A
Leadless Chip Carrier (LCG) and in Pin Grid Array
(PGA), both in Ceramic. The package designations
are R and A respectively.
5-63
8207
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
. extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias .................... - O·C to + 70·C
Storage Temperature .......... -.65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation (Note 2) ......•.. ; ........ 2.5W
D.C. CHARACTERISTICS
TA
=
O·C to 70·C; \Iss
Symbol
=
Vcc = 5.0V ±10% for 8207-10, 8207-8;
GND; Vcc = 5.0V ±5% for 8207-16 (Note 2)
Parameter
Min
Max
Units
Comments
Vil
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vcc +0.5
V
VOL
Output Low Voltage
0.45
V
(Note 1)
VOH
Output High Voltage
V
(Note 1)
VROl
RAM Output Low Voltage
0.45
V
(Note 1)
455
rnA
TA
±10
p,A
OV ~ VIN ~ Vcc
±0.6
V
2.4
VROH
RAM Output High Voltage
Icc
Supply Current
2.6
III
Input Leakage Current
VCl
Clock Input Low Voltage
-0.5
VCH
Clock Input High Voltage
3.8
CIN
Input Capacitance
V
. Vcc + 0.5
V
20
pF
,
(Note 1)
fc
=
=
O·C
1 MHz(2)
NOTE:
1. IOL = 5 mA and IOH = -0.2 mA (Typically IOL = 10 mA and IOH = -0.88 mAl. WE: IOL = 8 mA.
2. Sampled, not 100% tested.
.
A.C. TESTING LOAD CIRCUIT(2)
A.C. TESTING INPUT, OUTPUT WAVEFORM
U-Y20
2.4y-
~~0_.8_ _ _0._8~
'--_ _ _-'Rl
210463-27
210463-26
RRAS = 39!l
RCAS = 39!l
RAO = 22!l
RL = 39!l
CRAS = 150 pF
CcAS = 150 pF
CAO = 380 pF
CL=100pF
A.C. Testing inputs (except clock) are driven at 2.4V for a Logic
"1" and 0.45V for a Logic "0" (clock is driven at 4.0V and 0.45V
for Logic "1" and "0" respectively). Timing measurements are
made at 2.0V, 2.4V for Logic "1" and 0.8V for Logic "0" ..
5-64
8207
A.C. CHARACTERISTICS
vcc
=
5V ±10% for 8207-8; TA = OOG to 70oG; VCC =
+5V ±5% for 8207-16
Measurements made with respect to RASo_3, GASO_3, AOO_B, are a + 2.4V and 0.8V. All other pins are
measured at 2.0V and 0.8V. All times are ns unless otherwise indicated. Testing done with specified test load.
8207-16, -8
Ref
Symbol
8207-10
Parameter
Min
Max
Min
Units
Notes
Max
CLOCK AND PROGRAMMING
-
tF
Clock Fall Time
10
10
ns
3
-
tR
Clock Rise Time
10
10
ns
3
1
TClCl
Clock Period
250
ns
ns
ns
1
2
2
TClCLl2-12
ns
ns
ns
1
2
2
TClCl/3-3
ns
ns
ns
1
2
2
20
40
ns
4
4TClCl
4TClCl
ns
125
125
ns
10
10
ns
2
3
4
TCl
TCH
TRTVCl
Clock low Time
Clock High Time
B207-16
8207-10
8207-8
62.5
125
500
8207-16
8207-10
8207-8
15
180
8207-16
8207-10
8207-8
Reset to ClK J, Setup
200
100
TClCLl2-12
20
180
TClCl/3-3
5
TRTH
Reset Pulse Width
6
TPGVRTl
PCTl, POI, RFRQ to
RESET J, Setup
7
TRTlPGX
PCTl,RFRQ to
RESET J, Hold
8
TClPC
PClK from
ClK J, Delay
9
TPDVCl
PDin to
ClK J, Setup
60
60
ns
10
TClPDX
PDin to
ClK J, Hold
40
40
ns
6
ns
7
ns
2
ns
1
45
45
5
ns
RAM WARM-UP AND INITIALIZATION
64
TCLWZl
WZfrom
ClK J, Delay
40
40
SYNCHRONOUS ",p PORT INTERFACE
11
TPEVCl
PE to ClK J, Setup
27
12
TKVCl
RD, WR, PE, PCTl
to ClK J, Setup
20
13
TClKX
RD, WR, PE, PCTl
to ClK J, Hold
0
0
ns
14
TKVCH
RD, WR, PCTl to
ClK i Setup
20
20
ns
5-65
27
2
inter
8207
A.C. CHARACTERISTICS (Continued)
Vcc
=
5V ± 10% for 8207-8; TA
=
O°C to 70°C; Vcc
=
+ 5V ± 5%
for 8207-16
Measurements made with respect to RASo_3, CASO_3, AOO-B, are a + 2.4V and 0.8V. All other pins are
measured at 2.0V and 0.8V. All times are ns unless otherwise indicated. Testing done with specified test load.
8207·10
8207·16, ·8
Ref
Symbol
Parameter
Min
Max
Units
Notes
20
ns
8,9
2TCLCL+30
ns
Min
Max
ASYNCHRONOUS ",p PORT INTERFACE
15
TRWVCL
RD,WR
to CLK.j,. Setup
16
TRWL
RD, WR Pulse Width
17
TRWLPEV
PE from RD,
WR.j,. Delay
18
TRWLPEX
PEto RD,
WR.j,. Hold
19
TRWLPTV
PCTL from RD,
WR.j,. Delay
20
TRWLPTX
PCTL to RD,
WR.j,. Hold
21
TRWLPTV
PCTL from RD,
WR.j,. Delay
22
TRWLPTX
PCTL to RD,
WR.j,. Hold
20
2TCLCL+30
TCLCL-20
TCLCL-30
CFS=1
CFS=O
TCLCL-20
2TCLCL+30
2TCLCL+30
2TCLCL+30
2TCLCL+30
2TCLCL-30
2TCLCL-20
1
2
ns
TCLCL-30
TCLCL-30
ns
ns
ns
2
ns
2
ns
1
3TCLCL+30
3TCLCL+40
ns
1
10
RAM INTERFACE
23
TAVCL
AL, AH, 8Sto
CLK.j,. Setup
35+tASR
35+tASR
ns
24
TCLAX
AL, AH, 8Sto
CLK.j,. Hold
0
0
ns
25
TCLLN
LEN from
CLK.j,. Delay
35
26
TCLRSL
RAS.j,. from
CLK.j,. Delay
35
27
TRCD
RAStoCAS
Delay
28
TCLRSH
RASj from
CLK.j,. Delay
29
TRAH
Row AO to
RAS Hold
CFS=1
CFS=O
ns
35
TCLCL-25
TCLCLl2-25
CFS=1
CFS=O
50
TCLCL/2-11
TCLCLl4-11
18
0
30
TASR
Row AO to RAS Setup
0
31
TASC
Column AO to CFS=1
CAS.j,. Setup CFS=O
0
5
5
5-66
ns
ns
ns
ns
25
50
1
1, 14
11, 14
ns
ns
ns
1,13,15
11, 15
ns
ns
13,19,20
13,19,20
10, 18
8207
A.C. CHARACTERISTICS (Continued)
Vcc
=
5V ±10%for8207-8;TA
=
O'Cto70'C;Vcc
=
+5V ±5%for8207-16
Measurements made with respect to RASo_3, CASO_3, ADo-B, are a + 2.4V and O.8V. All other pins are
measured at 2.0V and O.8V. All times are ns unless otherwise indicated. Testing done with specified test load.
8207-10
8207-16, -8
Ref
Symbol
Units
Parameter
Min
Max
Min
Notes
Max
RAM INTERFACE (Continued)
32
TCAH
ColumnAO to
CAS Hold
33
TCLCSL
CAS.!. from
CLK.!. Delay
34
TCLCSL
CAS.!. from
CLK.!. Delay
35
TCLCSH
CASt from
CLK.!. Delay
(See DRAM Interface Tables)
TCLClI4+30
TCLCLI 1.8 + 53
21
100
ns
11,12
35
40
ns
1
50
50
ns
TCLClI4+30
36
TCLW
WE from CLK.!. Delay
35
35
ns
37
TCLTKL
XACK.!. from
CLK.!. Delay
35
35
ns
38
TRWLTKH
XACKt from
RD t , WR t Delay
50
50
ns
39
TCLAKL
AACK.!. from
CLK.!. Delay
35
35
ns
40
TCLAKH
AACKt from
CLK.!. Delay
50
50
ns
41
TCLDL
DBMfrom
CLK.!. Delay
35
35
ns
2TCLCL-40
TCLCL + TCL - 40
100
ns
ns
1,22
2,22
30
ns
23
ECCINTERFACE
42
TWRLFV
FWRfrom
WR.!. Delay
CFS=l
CFS=O
43
TFVCL
FWR to CLK.!. Setup
40
44
TCLFX
FWR to CLK.!. Hold
0
0
ns
24
45
TEVCL
ERROR to
CLK.!. Setup
20
20
ns
25,26
46
TCLEX
ERROR to
CLK.!. Hold
0
0
ns
47
TCLRL
R/W.!. from
CLK.!. Delay
40
40
ns
48
TCLRH
R/Wt from
CLK.!. Delay
50
50
ns
49
TCEVCL
CE to CLK.!. Setup
20
50
TCLCEX
'CE to CLK.!. Hold
0
51
TCLES
ESTB from
CLK.!. Delay
20
ns
ns
0
35
5-67
45
ns
25,27
8207
A.C. CHARACTERISTICS (Continued)
Vcc = 5V ±10% for 8207-8; TA = O°C to 70°C; VCC = +5V ±5% for 8207-16
Measurements made with respect to RASo_3. CASO_3. ADo-8. are a + 2.4V and 0.8V. All other pins are
measured at 2.0V and O.8V. All times are ns unless otherwise indicated. Testing done with specified test load.
Ref
Symbol
Parameter
8207-10
8207-16. -8
Min
Max
'Min
Max
Units
Notes
PORT SWITCHING AND LOCK
52
TClMV
MUXfrom
ClKi Delay
45
53
TClPNV
PSENfrom
ClKi Delay
54
TClPSV
PSEl from ClK i
55
TlKVCl
lOCK to ClK i Setup
30
30
ns
30,31
56
TCllKX
LOCK to ClK i Hold
10
10
ns
30,31
57
TRWllKV
LOCK from RD i ,
WRi Delay
ns
31,32
58
TRWHlKX
lOCK to RDi,
WR J, Hold
31,32
TCl
TCl+35
TCl
35
45
ns
TCl+35
ns
35
ns
2TClCl-30
2TClCl-30
28
3TClCl+30
3TClCl+30
ns
20
20
ns
10
10
ns
TClCl+30
TClCl+30
ns
33
20
20
ns
34
2TClCl+30
2TClCl+30
ns
33
REFRESH REQUEST
59
TRFVCl
RFRO to ClK J, Setup
60
TClRFX
RFRO to ClK J, Hold
61
TFRFH
Failsafe RFRO
Pulse Width
62
TRFXCl
Single RFRO Inactive
to ClK i Setup
63
TBRFH
Burst RFRO Pulse
Width
NOTES:
1. Specification when programmed in the Fast Cycle processor mode (iAPX 286 mode) .
.2. Specification when programmed in the Slow Cycle processor mode (iAPX 186 mode).
3. tR and tF are referenced from the 3.5V and 1.0V levels.
4. RESET is internally synchronized to ClK. Hence a set·up time is required only to guarantee its recognition at a particular
clock edge.
5. The first programming bit (PDO) is also sampled by RESET going low.
6. TClPDX is guaranteed if programming data is shifted using PClK.
7. WZ is issued only in ECC mode.
8. TRWVCl is not required for an asynchronous command except to guarantee its recognition at a particular clock edge.
9. Valid when programmed in either Fast or Slow Cycle mode.
10. IASR is a user specified parameter and its value should be added accordingly to TAVCL.
11. When programmed in Slow Cycle mode and 125 ns :s; TClCl < 200 ns.
12. When programmed in Slow Cycle mode and 200 ns :s; TClCL.
13. Specification for Test load conditions.
14. tRCD (actual) = tRCD (specification) + 0.06 (dCRAS) - 0.6 (dCCAS) where dC = C (test load) - C (actual) in pF
(These are first order approximations).
15. tRAH (actual) = tRAH (specification) + 0.06 (dCRAS) - 0.022 (dCAO) where dC = C (test load) - C (actual) in pF.
(These are first order approximations.)
18. tASR (actual) = IASR (specification) + 0.06 (dCAO) - 0.025 (dCRAS) where dC = C (test load) - C (actual) in pF.
(These are first order approximations.)
19. IASC (actual) = tASC (specification) + 0.06 (dCAO) - 0.025 (dCCAS) where dC = C (test load) - C (actual) in pF.
(These are first order approximations.)
5-68
8207
20. lASC is a function of clock frequency and thus varies with changes in frequency. A minimum value is specified.
21. See 8207 DRAM Interface Tables 14-18.
22. TWRlFV is defined for both synchronous and asynchronous FWR. In systems in which FWR is decoded directly from
the address inputs to the 8207, TClFV is automatically guaranteed by TCLAV.
23. TFVCl is defined for synchronous FWR.
24. TCLFV is defined for both synchronous and asynchronous FWR. In systems in which FWR is decoded directly from the
address inputs to the 8207 TClFV is automatically guaranteed by TCLAV.
25. ERROR and CE are set-up to ClK J., in fast cycle mode and elK i in slow cycle mode.
26. ERROR is set-up to the same edge as R/Vii is referenced to, in RMW cycles.
27. CE is set-up to the same edge as WE is referenced to in RMW cycles.
28. Specification when TCl < 25 ns.
29. Synchronous operation only. Must arrive by the second clock falling edge after the clock edge which recognizes the
command in order to be effective.
30. lOCK must be held active for the entire period the opposite port must be locked out. One clock after the release of
lOCK the opposite port will be able to obtain access to memory.
31. Asynchronous mode only. In this mode a synchronizer stage is used internally in the 8207 to synchronize up lOCK.
TRWllKV and TRWHlKX are only required for guaranteeing that lOCK will be recognized for the requesting port, but these
parameters are not required for correct 8207 operation.
32. TFRFH and TBRFH pertain to asynchronous operation only.
33. Single RFRQ cannot be supplied asynchronously.
WAVEFORMS
CLOCK AND PROGRAMMING TIMINGS
CLK
RESET _J)-~-'
PCTL
REFRQ
POI
210463-28
RAM WARM-UP AND MEMORY INITIALIZATION CYCLES
CLK-J\.../\-../
RESET------.~~-~+-------_+---~,~---------_+---RAS ,;-"CJ--r---,Jf....
' --"'~"--I.l
WE:J
£~'----~J~----~
wz:J
)j
RIW:J
RESET
)
PROGRAMMING
FIRST RAM WARM-UP CYCLE
, ' -_ _ _ _-J
LAST RAM WARM-UP OR
INITIALIZATION CYCLE
210463-29
NOTES:
1. When in non-ECC mode or in ECC mode with the TM2 programming bit on, there are no initialization cycles, when in
ECC mode with TM2 off, the dummy cycles are followed by initialization cycles.
2. The present example assumes a RAS four clocks long.
5-69
intJ
8207
WAVEFORMS (Continued)
SYNCHRONOUS PORT INTERFACE
COMMAND MODEl
FAST CYCLE
RD, W1f, lIE"
COMMAND MODEl
FAST CYCLE
PCTL (INHIBITI
COMMAND MODEl
FAST CYCLE
INTERNAL INHIBIT
--+---11--...
---t--t------'+------------------
SLOW CYCLE
RD.WR
SLOW CYCLE
PE
®
SLOW CYCLE
PCTL
INTERNAL
CYCLE REQUEST
210463-30
NOTE:
Actual transitions are programmable. Refer to Tables 12 and 13.
5-70
intJ
8207
WAVEFORMS (Continued)
ASYNCHRONOUS PORT INTERFACE
CLK
FAST/SLOW CYCLE
RD. WR
~~--------~I+-------_r~
~ST/SLOW CYCLE
------1f-....;;;.;:;....,.
~------------+~------~
SLOW CYCLE
PCTL
~------~-----+----GVI--~--------~
~-----QD-----+~
FAST CYCLE
PCTL (INHIBIT)
--------------~--~--~------~-----------
FAST CYCLE
INTERNAL INHIBIT
I
INTERNAL
CYCLE REQUEST
210463-31
5-71
8207
WAVEFORMS (Continued)
RAM INTERFACE TIMING
ECC AND NON-ECC MODE
CLOCK 0
ClK
COMMAND
~ ~~~ ~~
~
/
INTERNAL
CYCLE REQUEST
AlO - Ala
AHO - AHa
BS o - BS 1
lEN
/
/
~
..02.j
~@
---x
l(
~
I-®
f--®j
~
-¥-
~-Y-
H1iH-- I-@RAS
L®
ADO -ADa
CAS
® I
x:
-@
X
~
®
4-¥-
"1
-®-
~
®
WE
-X
.:fJ
I--®
~®-1
XACK
®j
AACK
~
~.Y-
1
DBM
~.J-
f--®j
-X-
210463-32
NOTE:
Actual transitions are programmable_ Refer to Tables 12 and 13.
5-72
8207
WAVEFORMS (Continued)
PORT SWITCHING AND LOCK TIMING
ClK
~g:~:ND
-r______ ____ __+-______
____~__~__
~
~
~
~-+-+'
COMMAND
PORT B
MUX~PO~R=T~A--~~I_+---------JI
RAS
, PORT B IF lOCK = 0
PORTA
~---------------
--------h
PSEN ____________-+::-::-..J'
PSEl ______________"'\1
PORT A
PORT B
,
PORTA
'--
lOCK----------~~--------~~~-----------+_-----~·
FAST CYCLE _ _ _ ----Ir--I1~
______....r_lL_______________'~-----®------~
_________________________
INTERNAL lOCK
DISABLE
210463-33
NOTE:
Transients during MUX switching.
REFRESH REQUEST TIMING
ClK
~~~~:~~ REFRES:::H.:...._ _ _ _ _.......
SINGLE REFRESH
REQUEST
- - - -_________________- '
-----e®@J f3@
BURST REFRESH
REQUEST
_ _ _ _ _ _ _ _ _ _ _ _ __
5-73
210463-34
8207
WAVEFORMS (Continued)
ECC INTERFACE TIMING
CLOCK 0
.~LJ ~~Lf'~L/\.J'.f-
ClK
COMMAND,~
(WRI
INTERNAL
CYCLE REQUEST
~
(44
[--{42J-tFAST CYCLE
FWFi
)(:
~VALID
'43
~-0-T
SLOW CYCLE
FWR
)[
- -1
X
~§1
/1
X
VALID
r~
ERROR
~61
)[
VALID
I
-~f.,-
~
RIW
JL
.Jl
,,-Xc
k®-j
XACK
\~2
@
r'
CE
@-
)[
VAUD
-®~
ESTB
:)(
~~
,y
\X-
@>
~
-210463-35
NOTES:
1. This parameter is set-up to the falling edge of clock, as shown, for fast cycle configurations. It is set-up to the rising
edge of clock if in slow cycle configurations. Table 13A shows which clock and clock edge these signals are set-up in
the R/W L column.
2. CE is set-up to the same edge as WE is referenced to in RMW cycles.
5-74
inter
8207
CONFIGURATION TIMING CHARTS
The timing charts that follow are based on 8 basic system configurations where the 8207 operates.
Tables 10 and 11 give a description of non-ECC and ECC system configurations based on the 8207's
PD3, PD4, PD10 and PD11 programming bits.
PD~,
Table 10. Non-ECC System Configurations
Non-ECC Mode:
PD~ =
0
Timing Conf.
CFS(PD3)
RFS(PD4)
EXT(PD10)
FFS(PD11)
Co
iAPX286(0)
Fast RAM(O)
Not EXT(O)
12 MHz(1)
Co
iAPX286(0)
Fast RAM(O)
EXT(1)
12 MHz(1)
Co
iAPX286(0)
Slow RAM(1)
Not EXT(O)
12MHz(1)
Co
iAPX286(0)
Slow RAM(1)
EXT(1)
12MHz(1)
Co
iAPX286(0)
Fast RAM(O)
Not EXT(O)
16 MHz(O)
C1
iAPX286(0)
Slow RAM(1)
Not EXT(O)
16 MHz(O)
C1
iAPX286(0)
Fast RAM(O)
EXT(1)
16 MHz(O)
C2
iAPX286(0)
Slow RAM(1)
EXT(1)
16 MHz(O)
C3
iAPX186(1)
Fast RAM(O)
Not EXT(O)
10,8 MHz(O)
C3
iAPX186(1)
Slow RAM(1)
Not EXT(O)
10,8 MHz(O)
C3
iAPX186(1)
Fast RAM(O)
EXT(1)
10,8 MHz(O)
C3
iAPX186(1)
Fast RAM(O)
Not EXT(O)
6 MHz(1)
C3
iAPX186(1)
Fast RAM(O)
EXT(1)
6 MHz(1)
C3
iAPX186(1)
Slow RAM(1)
Not EXT(O)
6 MHz(1)
C3
iAPX186(1)
Slow RAM(1)
EXT(1)
6 MHz(1)
C4
iAPX186(1)
Slow RAM(1)
EXT(1 )
10,8 MHz(O)
Table 11. ECC System Configurations
ECC Mode·
PD~ =
1
Timing Conf.
CFS(PD3)
RFS(PD4)
EXT(PD10)
Co
iAPX286(1)
Slow RAM(O)
MIS EDCU(O)
FFS(PD11)
Co
iAPX286(1)
Slow RAM(O)
M EDCU(1)
12 MHz(O)
Co
iAPX286(1)
Fast RAM(1)
MIS EDCU(O)
12 MHz(O)
Co
iAPX286(1)
Fast RAM(1)
M EDCU(1)
12 MHz(O)
Co
iAPX286(1)
Fast RAM(1)
M EDCU(1)
16 MHz(1)
C1
iAPX286(1)
Slow RAM(O)
M EDCU(1)
16 MHz(1)
C2
iAPX286(1)
Fast RAM(1)
MIS EDCU(O)
16MHz(1)
C3
iAPX286(1)
Slow RAM(O)
MIS EDCU(O)
16 MHz(1)
C4
iAPX186(0)
Slow RAM(O)
MIS EDCU(O)
6 MHz(O)
C4
iAPX186(0)
Fast RAM(1)
MIS EDCU(O)
6 MHz(O)
C4
iAPX186(0)
Slow RAM(O)
M EDCU(1)
10,8 MHz(1)
12 MHz(O)
C4
iAPX186(0)
Fast RAM(1)
M EDCU(1)
10,8 MHz(1)
C5
iAPX186(0)
Slow RAM(O)
MIS EDCU(O)
10,8 MHz(1)
C5
iAPX186(0)
Fast RAM(1)
MIS EDCU(O)
10,8 MHz(1)
C6
iAPX186(0)
Slow RAM(O)
M EDCU(1)
6 MHz(O)
C6
iAPX186(0)
Fast RAM(1)
M EDCU(1)
6 MHz(O)
5-75
inter
8207
2. LEN - low is given as the latest time it can occur.
LEN is only activated by port A configured in Fast
Cycle iAPX286 mode, and thus it is not activated
by a refresh cycle, although it may be activated by
port A during a refresh cycle.
3. ADDRESS - col is the time column address becomes valid.
4. In non-ECC mode the CAS, EAACK, LAACK and
XACK outputs are not issued during refresh.
5. In ECC mode there are really seven types of cycles: Read without error, read with error, full write,
partial write without error, partial write with error,
refresh without error, and refresh with error.
These cycles may be derived from the timing
chart as follows:
A. Read without error: Use row marked 'RD, RF'.
B. Read with error: Use row marked 'RMW', except for EAACK and LAACK, which. should be
taken from 'RD, RF'. If the error is uncorrectable. WE will not be issued.
C. Full write: Use row marked 'WR'.
D. Partial write without error: Use row marked
'RMW', except that DBM and ESTB will not be
issued.
E. Partial write with error: Use row marked 'RMW',
except that DBM will not be issued. If the error
is uncorrectable, WE will not be issued.
F. Refresh without error: Use row marked 'RD,
RF', except that ESTB, EAACK, LAACK, and
XACK will not be issued.
G. Refresh with error: Use row marked 'RMW',
except that EAACK, LAACK, ESTB, and XACK
will not be issued. If the error is uncorrectable
WE will not be issued.
6. XACK - high is reset asynchronously by command going inactive and not by a clock edge.
7. MUX - valid is given as the latest time it can occur.
Using the Timing Charts
The notation used to indicate which clock edge triggers an output transition is "n t" or "n J.. ", where
un" is the number of clock periods that have passed
since clock 0, the reference clock, and "t .. refers
to rising edge and" J.. " to falling edge. A clock period is defined as the interval from a clock falling edge
to the following falling edge. Clock edge_s are defined as shown below.
(n-1)1
nl
ni
(n+1)1 (n+1)1
210463-36
The clock edges which trigger transitions on each
8207 output are tabulated in Table 12 for non-ECC
mode and Table 13 for ECC mode. "H" refers to the
high-going transition, and "L" to low-going transition;"V" refers to valid, and "\I" to non-valid.
Clock 0 is defined as the clock in which the 8207
begins a memory cycle, either as a result of a port
request which has just arrived, or of a port request
which was stored previously but could not be serv"
iced at the time of its arrival because the 8207 was
performing another memory cycle. Clock 0 may be
identified externally by the leading edge of RAS,
which is always triggered on 0 J.. .
Notes for interpreting the timing charts:
1. PSEL - valid is given as the latest time it can
occur. It is entirely possible for PSEL to become
valid before the time given in a refresh cycle.
PSEL can switch as defined in the chart, but it has
no bearing on the refresh cycle itself, but only on
a subsequent cycle for one of the external ports.
5-76
intJ
8207
Table 12A. Timing Chart-Non-ECC Mode
PSEN
Cn
Co
Cycle
RD, RF
WR
C1
RD, RF
WR
C2
RD, RF
WR
C3
RD, RF
WR
C4
RD, RF
WR
H
L
a.!
a.!
a.!
oJ,
oJ,
oJ,
oJ,
a.!
oJ,
A.!
3.!
4.!
5.!
4J,
5J,
4.!
2.!
3J,
3J,
3J,
PSEL
V
a.!
a.!
a.!
oJ,
at
oJ,
a.!
oJ,
a.!
a.!
DBM
V
4.!
5.!
6.!
5J,
6J,
5J,
3J,
4J,
4.!
4J,
L
LEN
H
a.!
4.!
a.!
6.!
oJ,
6J,
a.!
3J,
a.!
4J,
L
a.!
a.!
a.!
oJ,
oJ,
oJ,
RAS
H
2.!
2.!
2.!
2.!
2.!
2J,
L
H
a.!
a.!
a.!
oJ,
oJ,
A.!
oJ,
oJ,
oJ,
oJ,
WE
CAS
3.!
5.!
4.!
5.!
4.!
5J,
3.!
4.!
4.!
4J,
L
H
1.! 4.!
1 .! 5.!
1 .! 6J,
1 J, 5J,
1J, 6J,
1J, 5J,
oJ, 3J,
oJ, 4J,
oJ, 4J,
oJ, 4J,
Table 12B. Timing Chart-Non-ECC Mode
Col Addr
Cn
Co
Cycle
RD,RF
WR
C1
RD, RF
WR
C2
RD, RF
WR
C3
RD, RF
WR
C4
RD, RF
WR
EAACK
V
V
L
A.!
A.!
a.!
oJ,
A.!
oJ,
oJ,
oJ,
a.!
oJ,
2J,
2J,
3.!
3J,
3J,
3J,
2.!
2J,
2.!
2.!
1J,
1 J,
2.!
1 J,
2J,
1 J,
oJ,
oJ,
1.!
oJ,
LAACK
H
L
4.!
4J,
5.!
4J,
5.!
4.!
2.!
2.!
3.!
2.!
2J,
1 J,
2.!
1 J,
3J,
1 J,
1J,
1j
1.!
1j
5-77
XACK
H
L
H
5.!
4.!
5.!
4J,
6.!
4.!
3.!
3j
3J,
3j
3J,
3J,
4.!
3J,
4.!
3.!
2.!
2.!
3j
2J,
RD
WR
RD
WR
RD
WR
RD
WR
RD
WR
MUX
V
V
-2.!
-2.!
-2J,
-2.!
-2.!
-2.!
-1.!
-1.!
-1J,
-1.!
2J,
2J,
2J,
2J,
2J,
2J,
2J,
2J,
2J,
2J,
H
L
2.!
5.!
2J,
5J,
2.!
5J,
2j
4J,
2j
4J,
aL-9
t9 !8 t9 !1: t9
tv !1: tv ! ~ tv
tv
tL !9 tL !8 tL
t9 !8 t9 ! ~ t9
tv
!9
tL
tL !8 tL
t9 !8 t9 ! ~ t9
tv
t ~ ~ ta t ~ ~ t9 t ~ ~
tL tv tL t~ tL
tL
t ~ ~ ta t ~ ~ t9 t ~ ~
tL tv tL t ~ tL
tL
t6 t9 t6 tv t6
t9 t8 t9 t~ t9
t9
t6 t9 t6 tv t6
t9 t8 t9 t~ t9
t9
H
1
3M
H
MIl:!
1
to
to
to
to
to
to
to
to
to
t~
t~
t~
t~
t~
t
t
t
~
~
~
t~
t
t
t
H
S\'O
1
~
~
~
t9
tv
t8
tL
t9
t8
tL
t9
t8
t ~~
tL
t9
t ~~
_tL
t9
t6
t9
tv
t6
t9
tv
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
t1:
t1:
t1:
t1:
t1:
t1:
t1:
t1:
t1:
t1:
t1:
t1:
to
to
to
to
to
to
to
to
to
to
to
to
H
1
H
1
S\,l:!
N31
t9 to t9
tv
tv to tv
tL to tL
t9
tv to tv
tL to tL
t9
tv to tv
t ~~ to t ~ ~
tL
tL to tL
t ~~ to t ~ ~
tL
tL to tL
t6 to f6
t9
t9 to t9
t6 to t6
t9
t9 to t9
H
1
weo
!!
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
"
13Sd
t9
t9
ta
t9
t9
ta
t9
t9
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
1
H
tv
t8
t8
t9
tv
t8
t9
tv
t8
to~
t9
t9
to~
MVlJI:l
I:lM
9:)
:l1:l 'Ol:l
MVlJI:l
I:lM
9:)
:lI:l'OI:l
MVlJI:l
I:lM
v:)
:lI:l'OI:l
MVlJI:l
I:lM
£:)
:lI:l'OI:l
MVlJI:l
I:lM
i::)
:l1:l 'Ol:l
MVlJI:l
I:lM
~:)
:l1:l 'Ol:l
MVlJI:l
I:lM
0:)
:lI:l'OI:l
al:>Ao
Uo
N3Sd
apow 003-IJBlIO 6u!wU. .\'&~ alqB.l
L.OZ:S
Flu!
infef
8207
Table 13B. Timing Chart-ECC Mode
Col Addr
Cn
Co
C1
C2
C3
C4
C5
C2
Cycle
V
Ii
RD, RF
WR
RMW
RD, RF
WR
RMW
RD, RF
WR
RMW
RD, RF
WR
RMW
RD, RF
WR
RMW
RD, RF
WR
RMW
RD, RF
WR
RMW
oJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJoJ-
2J2J2J3J3J3J3J3J,.
3J3J3J3J2J2J2J,.
2J,.
2J2J2J2J2J-
ESTB
L
H
6J-
BJ-
6J-
BJ-
BJ-
10 J-
BJ-
10 J-
EAACK
6j
5j
6j
3j
4j
XACK
MUX
H
L
H
L
H
V
Ii
2J2J5J3J2J5J4J3J7J4J3J7J-
5J5JBJ6J5JBJ7J6J10 J7J6J10 J,.
3J3J5J4J3J5J3J3J3J-
3J2J5J3J2J5J4J3J7J5J3J7J2j
2j
4j
3j
2j
4j
6J5JBJ6J5J,.
BJ7J6J10 JBJ6J,.
10 J4j
4j
6j
5j
4j
6j
3j
3j
4j
4J4J7J4J4J7J5J5J9J5J5J9J3j
3J5J3j
3J5J2j
2J3J-
RD
WR
WR
RD
WR
WR
RD
WR
WR
RD
WR
WR
RD
WR
WR
RD
WR
WR
RD
WR
WR
-2J-2J-2J-2J-2J-2J-2J-2J-2J-2J-2J-2J-1J-1J-1J-1J-1J-1J-1J-1J-1J-
2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J2J-
q
5j
LAACK
L
1J3J,.
2J1J3J1J1J1J-
5·79
1j
1j
2j
8207
READ & REFRESH CYCLES
tRCH: WE always goes active after CAS goes active, hence tRCH is guaranteed by tCPN.
8207-DRAM Interface Parameter
Equations
Several DRAM parameters, but not all, are a direct
function of 8207 timings, and the equations for these
parameters are given in the following tables. The following is a list of those DRAM parameters which
have NOT been included in the following tables, with
an explanation for their exclusion.
WRITE CYCLE
guaranteed by tRWC.
guaranteed by tRRW.
guaranteed by tCRW.
WE always activated after CAS is activated, except in memory initialization, hence
tWCS is always negative (this is important
for RMW only) except in memory initialization; in memory initialization tWCS is positive and has several clocks of margin.
tDS:
system-dependent parameter.
tDH:
system-dependent parameter.
tDHR: system-dependent parameter.
tRC:
tRAS:
tCAS:
tWCS:
READ, WRITE, READ-MODIFY-WRITE &
REFRESH CYCLES
tRAC:
response parameter.
tCAC:
response parameter.
tREF:
See "Refresh Period Options"
tCRP:
must be met only if CAS-only cycles, which
do not Qccur with 8207, exist.
tRAH: See "AC. Characteristics"
tRCD: See "AC. Characteristics"
tASC:
See "AC. Characteristics"
tASR:
See "AC. Characteristics"
tOFF:
response parameter.
READ-MODIFY-WRITE CYCLE
tRWD:
tCWD:
don't care in 8207
ed for 8207 RMW
don't care in 8207
ed for 8207 RMW
write cycles, but tabulatcycles.
write cycles, but tabulatcycles.
Table 14. Non-ECC Mode-RO, RF Cycles
Fast Cycle Configurations
Parameter
Slow Cycle Configurations
Notes
Co
C1
C2
C3
C4
tRP
3TCLCL-T26
4TCLCL-T26
4TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
tCPN
3TCLCL-T35
3TCLCL-T35
3TCLCL-T35
2.5TCLCL - T35
2.5TCLCL - T35
1
tRSH
2TCLCL-T34
3TCLCL-T34
3TCLCL-T34
3TCLCL-T34
4TCLCL-T34
1
tCSH
4TCLCL-T26
6TCLCL-T26
6TCLCL-T26
3TCLCL-T26
4TCLCL-T26
1
tCAH
TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
tAR
2TCLCL-T26
3TCLCL-T26
3TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
3/30
3/30
3/30
3/30
3/30
2
tT
tRC
6TCLCL
8TCLCL
8TCLCL
5TCLCL
6TCLCL
1
3TCLCL-T26
4TCLCL-T26
4TCLCL-T26
3TCLCL-T26
4TCLCL-T26
1
tCAS
3TCLCL-T34
5TCLCL-T34
5TCLCL-T34
3TCLCL-T34
4TCLCL-T34
1
tRCS
2TCLCL-TCL 2TCLCL-TCL 2TCLCL-TCL
-T36-TBUF -T36-TBUF -T36-TBUF
1.5TCLCL - TCL
-T36-TBUF
1.5TCLCL - TCL
-T36-TBUF
1
tRAS
5-80
8207
Table 15. Non-ECC Mode-WR Cycle
Fast Cycle Configurations
Parameter
Slow Cycle Configurations
C2
C3
Notes
Co
C1
tRP
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
tCPN
4TCLCL-T35
4TCLCL-T35
4TCLCL-T35
2.5TCLCL - T35
2.5TCLCL - T35
1
tRSH
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
1
tCSH
5TCLCL-T26
5TCLCL-T26
5TCLCL-T26
4TCLCL-T26
4TCLCL-T26
1
C4
tCAH
TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
tAR
2TCLCL-T26
3TCLCL-T26
3TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
tT
tRWC
3/30
3/30
3/30
3/30
3/30
2
8TCLCL
8TCLCL
8TCLCL
6TCLCL
6TCLCL
1
tRRW
5TCLCL-T26
5TCLCL-T26
5TCLCL-T26
4TCLCL-T26
4TCLCL-T26
1
tCRW
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
1
tWCH
3TCLCL+TCL
-T34
3TCLCL+TCL
3TCLCL+TCL
-T34
3TCLCL+TCL
-T34
3TCLCL+TCL
-T34
1,3
tWCR
4TCLCL+TCL
-T26
4TCLCL+TCL 4TCLCL+TCL
-T26
-T26
3TCLCL+TCL
-T26
3TCLCL+TCL
-T26
1,3
tWP
2TCLCL+TCL
-T36-TBUF
2TCLCL+TCL
-T36-TBUF
2TCLCL+TCL
-T36-TBUF
2TCLCL-T36
-TBUF
2TCLCL-T36
-TBUF
1
tRWL
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
- TBUI';
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
1
tCWL
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
1
-T34
5·81
inter
8207
Table 16A. ECC Mode-RD, RF Cycles
Fast Cycle Mode
Parameter
Co
C1
Notes
C2
Ca
tAP
4TCLCL-T26
4TCLCL-T26
4TCLCL-T26
4TCLCL-T26
1
tCPN
3TCLCL-T35
3TCLCL-T35
3TCLCL-T35
3TCLCL-T35
1
tASH
3TCLCL-T34
3TCLCL-T34
4TCLCL-T34
4TCLCL-T34
1
tCSH
6TCLCL-T26
6TCLCL-T26
7TCLCL-T26
7TCLCL-T26
1
tCAH
tAA
TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
2TCLCL-T26
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
1
3/30
3/30
8TCLCL
8TCLCL
tAAS
4TCLCL-T26
4TCLCL-T26
tCAS
5TCLCL-T34
tACS
TCLCL-T36
-TBUF
tT
tAC
3/30
3/30
2
9TCLCL
1
5TCLCL-T26
5TCLCL-T26
1
5TCLCL-T34
6TCLCL-T34
6TCLCL-T34
1
TCLCL-T36
-TBUF
TCLCL-T36
-TBUF
TCLCL-T36
-TBUF
1
9TCLCL.
Table 168. ECC Mode-RD, RF Cycles
Slow Cycle Mode
Parameter
tAP
Notes
C4
Cs
Cs
2TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
tCPN
1.5TCLCL ,- T35
1.5TCLCL - T35
1.5TCLCL - T35
1
tASH
3TCLCL-T34
3TCLCL-T34
3TCLCL-T34
1
tCSH
4TCLCL-T26
4TCLCL-T26
4TCLCL-T26
1
tCAH
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
tAR
2TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
3/30
3/30
3/30
2
tT
tRC
tRAS
5TCLCL
5TCLCL
5TCLCL
1
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
1
tCAS
4TCLCL-T34
4TCLCL-T34
4TCLCL-T34
1
tACS
0.5TCLCL - T36
-TBUF
0.5TCLCL - T36
-TBUF
0.5TCLCL - T36
-TBUF
1
5·82
8207
Table 17A ECC Mode-WR Cycle
Fast Cycle Mode
Parameter
tRP
tCPN
tRSH
tCSH
tCAH
tAR
tT
tRWC
tRRW
tCRW
tWCH
tWCR
tWP
tRWL
tCWL
Co
3TCLCL-T26
4TCLCL-T35
5TCLCL-T34
6TCLCL-T26
TCLCL-T34
2TCLCL-T26
3/30
9TCLCL
6TCLCL-T26
5TCLCL-T34
5TCLCL-T34
6TCLCL-T26
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
Parameter
tRP
tCPN
tRSH
tCSH
tCAH
tAR
tT
tRWC
tRRW
tCRW
tWCH
tWCR
tWP
tRWL
tCWL
C1
3TCLCL-T26
4TCLCL-T35
5TCLCL-T34
6TCLCL-T26
2TCLCL-T34
3TCLCL-T26
3/30
9TCLCL
6TCLCL-T26
5TCLCL-T34
5TCLCL - T34_
6TCLCL-T26
3TCLCL-T36
--TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
C2
3TCLCL-T26
4TCLCL-T35
6TCLCL-T34
7TCLCL-T26
2TCLCL-T34
3TCLCL-T26
3/30
10TCLCL
7TCLCL-T26
6TCLCL-T34
6TCLCL-T34
7TCLCL-T26
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
Notes
C3
3TCLCL-T26
4TCLCL-T35
6TCLCL-T34
7TCLCL-T26
2TCLCL-T34
3TCLCL-T26
3/30
10TCLCL
7TCLCL-T26
6TCLCL-T34
6TCLCL-T34
}TCLCL - T26
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
Table 178. ECC Mode-WR Cycle
Slow Cycle Mode
C4
2TCLCL-T26
2.5TCLCL - T35
5TCLCL-T34
5TCLCL-T26
2TCLCL-T34
2TCLCL-T26
3/30
7TCLCL
5TCLCL-T26
5TCLCL-T34
5TCLCL-T34
5TCLCL-T26
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
Cs
2TCLCL-T26
2.5TCLCL - T35
5TCLCL-T34
5TCLCL-T26
2TCLCL-T34
2TCLCL-T26
3/30
7TCLCL
5TCLCL-T26
5TCLCL-T34
5TCLCL-T34
5TCLCL-T26
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
5-83
Cs
2TCLCL-T26
2.5TCLCL - T35
4TCLCL-T34
4TCLCL-T26
2TCLCL-T34
2TCLCL-T26
3/30
6TCLCL
4TCLCL-T26
4TCLCL-T34
4TCLCL-T34
4TCLCL-T26
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
Notes
1
1
1
1
1
1
2
1
1
1
1,4
1,4
1
1
1
1
1
1
1
1
1
2
1
1
1
1,4
1,4
1
1
1
intJ
8207
Table 18A. ECC Mode-RMW
Fast Cycle Mode,
Parameter
Notes
Co
C1
C2
C3
tRP
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
1
tCPN
4TCLCL-T35
4TCLCL-T35
4TCLCL-T35
4TCLCL-T35
1
tRSH
8TCLCL-T34
. 8TCLCL - T34
1OTCLCL - T34
1OTCLCL - T34
1
tCSH
9TCLCL-T26
9TCLCL-T26
11 TCLCL - T26
11 TCLCL - T26
1
tCAH
TCLCL-T34
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
tAR
2TCLCL-T26
3TCLCL-T26
3TCLCL-T26
3TCLCL-T26
1
3/30
3/30
3/30
3/30
2
12TCLCL
12TCLCL
14TCLCL
14TCLCL
1
tRRW
9TCLCL-T26
9TCLCL-T26
11 TCLCL - T26
11TCLCL - T26
1
tCRW
8TCLCL-T34
8TCLCL-T34
1OTCLCL - T34
1OTCLCL - T34
1
tRCS
TCLCL-T36
-TBUF
TCLCL-T36
-TBUF
TCLCL-T36
-TBUF
TCLCL-T36
-TBUF
1
tRWD
6TCLCL-T26
6TCLCL-T26
8TCLCL-T26
8TCLCL-T26
1,4
tCWD
5TCLCL-T34
5TCLCL-T34
7TCLCL-T34
7TCLCL-T34
1
tWP
3TCLCL-T36
-TBUF ,
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
1
tRWL
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
1
tCWL
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
3TCLCL-T36
-TBUF
1
tT
tRWC
5-84
inter
8207
Table 188. ECC Mode-RMW
Slow Cycle Mode
Parameter
Notes
C4
Cs
C6
2TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
tCPN
2.5TCLCL - T35
2.5TCLCL - T35
2.5TCLCL - T35
1
tRSH
7TCLCL-T34
7TCLCL-T34
5TCLCL-T34
1
tRP
tCSH
7TCLCL-T26
7TCLCL-T26
5TCLCL-T26
1
tCAH
2TCLCL-T34
2TCLCL-T34
2TCLCL-T34
1
tAR
2TCLCL-T26
2TCLCL-T26
2TCLCL-T26
1
3/30
3/30
3/30
2
tT
tRWC
9TCLCL
9TCLCL
7TCLCL
1
tRRW
7TCLCL-T26
7TCLCL-T26
5TCLCL-T26
1
tCRW
7TCLCL-T34
7TCLCL-T34
5TCLCL-T34
1
tRCS
0.5TCLCL - T36
-TBUF
0.5TCLCL - T36
-TBUF
0.5TCLCL - T36
-TBUF
1
tRWD
4TCLCL+TCL
-T26
4TCLCL+TCL
-T26
2TCLCL+TCL
-T26
1
tCWD
4TCLCL+TCL
-T34
4TCLCL+TCL
-T34
2TCLCL+TCL
-T34
1
tWP
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
1
tRWL
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
- T36- TBUF
1
tCWL
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
3TCLCL-TCL
-T36-TBUF
1
NOTES:
1. Minimum.
2. Value on right is maximum; value on left is minimum.
3. Applies to the eight warm-up cycles during initialization only.
4. Applies to the eight warm-up cycles and to the memory initialization cycles during initialization only.
5. TP = TCLCL
T26 = TCLRSL
T34 = TCLCSL
T35 = TCLCSH
T36 = TCLW
TBUF = TTL Buffer delay.
5-85
82C08
CHMOS DYNAMIC RAM CONTROLLER
Wait State with INTEL I-LProcessors
• oiAPX
} 82C08-20 20 MHz
• (10,8 286
MHz)
82C08-16 16 MHz
Addresses and Drives up to
• Directly
1 Megabyte without External Drivers
•
•
iAPX 186/88 } 82C08-10 10 MHz
86/88 82C08-8 8 MHz
•
Down Mode with Programmable
• Power
Memory Refresh using Battery Backup
Supports 64K and 256K DRAMs
(256K x 1 and 256K x 4 Organizations)
Microprocessor Data Transfer and
Advance Acknowledge Signals
Five Programmable Refresh Modes
RAM Warm-up
• Automatic
Pin-Compatible with 8208
• 48 Lead Plastic DIP; 68 Lead PLCC
•
with Normal Modes of
• Compatible
Static Column and Ripplemode DRAMs
(See Intel Packaging; Order-Number: 23t369-001)
The Intel 82C08 Dynamic RAM Controller is a CMOS, high performance, systems oriented, Dynamic RAM
controller that is designed to easily interface 64K and 256K Dynamic RAMs to Intel and other microprocessors. The 82C08 also has a power down mode where only the refresh logic is activated using battery backup.
AL4
AL3
AL2
AL1
ALO
BS
ADD
ADl
AD2
AD3
AD4
Vss
ADS
AD6
AD7
AD8
POD
RASl
nc.,
11m<
VCC/VPD
ALS
AL6
AL7
AL8
AHO
AHl
AH2
AH3
AH4
AHS
AH6
Vss
AH7
AH8
POI
RFRQ
CLK
RASli
liD
CASi
WR
PE
CASD
PDCLK
RESET
Vee
PCTL
AACKlXACK
WElPCLK
231357-2
68
67
66
55
64
62
61
60
59
58
57
56
55
~
53
52
68 LEAD PLCC
82CD8
TOP VIEW
9
10
231357-1
63
11
12
13
14
15
,.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
231357-35
Figure 1. Block Diagram and Pinout Diagrams
5-86
September 1987
Order Number: 231357·006
inter
82C08
Table 1. Pin Description
Symbol
DIP
Pin
PLCC
ALO
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
5
4
3
2
1
47
46
45
44
55
56
57
58
59
63
64
66
67
ADDRESS LOW: These lower order address inputs are used to
generate the column address for the internal address multiplexer.
In iAPX 286 mode (CFS = 1), these addresses are latched
internally.
AHO
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8
43
42
41
40
39
38
37
35
34
2
3
4
5
6
7
8
12
13
ADDRESS HIGH: These higher order address inputs are used to
generate the row address for the internal address multiplexer. In
iAPX 286 mode, these addresses are latched internally.
BS
6
50
BANK SELECT: This input is used to select one of the two banks
of the dynamic RAM array.
AOO
A01
A02
A03
A04
A05
A06
A07
A08
7
8
9
10
11
13
14
15
16
49
48
47
46
45
41
40
39
38
0
0
0
0
0
0
0
0
0
ADDRESS OUTPUTS: These outputs are designed to provide the
row and column addresses, of either the CPU or the· refresh
counter, to the dynamic RAM array. These outputs drive the
dynamic RAM array directly and need no external drivers.
However, they typically need series resistors to match.
impedances.
RASO
RAS1
19
18
33
36
0
0
ROW ADDRESS STROBE: These outputs are used by the
dynamic RAM array to latch the row address, present on the AOO8 pins. These outputs are selected by the BS pin. These outputs
drive the dynamic RAM array directly and need no external drivers.
CASO
CAS1
21
20
30
31
0
0
COLUMN ADDRESS STROBE: These outputs are used by the
dynamic RAM array to latch the column address, present on the
AOO-8 pins, These outputs are selected by the BS pin. These
outputs drive the dynamic RAM array directly and need no external
drivers.
RESET
23
28
I
RESET: This active high signal causes all internal counters to be
reset. Upon release of RESET, data appearing at the POI pin is
clocked-in by the PCLK output. The states of the POI, PCTL, and
RFRQ pins are sampled by RESET going inactive and are used to
program the 82C08. An 8-cycle dynamic RAM warm-up is
performed after clocking POI bits into the 82C08.
WEI
PCLK
25
24
0
WRITE ENABLE/PROGRAMMING CLOCK: Immediately after a
RESET this pin becomes PCLK and is used to clock serial
programming data into the POI pin. After the 82C08 is programmed
this active high signal provides the dynamic RAM array the write
enable input for a write operation.
Name and Function
Type
5-87
intJ
82C08
Table 1. Pin Description (Continued)
DIP
Pin
PLCC
Type
AACKI
XACK
26
23
0
PCTl
27
22
I
PORT CONTROL: This pin is sampled on the falling edge of
RESET. It configures the 82C08 to accept command inputs or
processor status inputs. If PCTl is low after RESET the 82C08 is
programmed to accept bus/multibus command inputs or iAPX 286
status inputs. If PCTl is high after RESET the 82C08 is .
programmed to accept status inputs from iAPX 86 or iAPX 186
type processors. The S2 status line should b.e connected to this
input if programmed to accept iAPX 86 or iAPX 186 inputs. When
programmed to accept bus commands or iAPX 286 status inputs, it
should be tied low or it may be connected to INHIBIT when
operating with MUlTIBUS.
PE
28
21
I
PORT ENABLE: This pin serves to eh.able a RAM cycle request. It
is generally decoded from the address bus.
.
WR
29
20
I
WRITE: This pin is the write memory request command input. This
input also directly accepts the SO status line from Intel processors.
RO
30
19
I
READ: This pin is the read memory request'commarid pin. This
input also directly accepts the S1 status line from Intel processors.
ClK
31
16
I
CLOCK: This input provides the basic timing for sequencing the
internal logic.
RFRO
32
15
.1
REFRESH REQUEST: This input is sampled .on the falling edge of
RESET. If RFRO is high at RESET then the 82C08 is programmed
for internal-refresh request or external-refresh request with failsafe
protection. If RFRO is low at RESET then the 82C08 is
programmed for external-refresh without failsafe protection or
burst refresh: Once programmed the RFRO pin accepts Signals to
start an external-refresh with failsafe protection or external-refresh
without failsafe protection or a burst refresh. RFRO is also
sampled when POD is activated. When RFRO = 1 it will cause 3
'
burst refresh cycles.
POI
33
14
I
PROGRAM DATA INPUT: This input is sampled by RESET going
low. It programs the various user selectable options in the 82C08.
The PClK pin shifts programming data into the POI input from an
external shift register. This pin may be strapped low to a default
iAPX 186 mode configuration or high to a default iAPX 286 mode
configwation.
'POO
17
37
I
POWER DOWN DETECT: This input is sampled before every
memory cycle to inform the 82C08 of system detection of power
failure. When active, the 82C08 remains in power down mode and
performs memory refresh only (RAS-only refresh). In power down
mode the 82C08 uses POClK for timing and VPO for power.
Symbol
Name and Function
ADVANCE ACKNOWLEDGE/TRANSFER ACKNOWLEDGE:
When the X programming bit is set to logic 0 this pin is AACK and
indicates that the processor may continue processing and that
data will be available when required. This signal is optimized for
the system by programming the S program-bit for synchronous or
asynchronous operation. The S programming bit determines
whether this strobe will be early or late. If another dynamic RAM
cycle is in progress at the time of the new request, the AACK is
delayed. When the X programming bit is set to logic 1 this pin is
XACK and indicates that data on the bus is valid during a read
cycle or that data may be removed from the bus during a write
cycle. XACK is a MUlTIBUS compatible signal.
5-88
inter
82C08
Table 1. Pin Description (Continued)
Symbol
'PDCLK
DIP
Pin
PLCC
Type
22
29
I
Name and Function
POWER DOWN CLOCK: This pin is used as a clock for internal
refresh circuits during power down. The input can be
asynchronous to pin 31. Extended refresh is achieved by slowing
down this clock. This pin should be grounded if not used.
'Vee/VpD
48
61,62
I
Vee
24
26,27
I
POWER: Power supply for internal logic. This should be held
active during power down, and normal operation.
POWER: Supply for drivers. Need not be held active during power
down.
Vss
12
36
9,10,
11,42,
43,44
NC
-
17,18,
1,25,
32,34,
35,51,
53,54,
60,65,
68
Vees
I
I
52
GROUND
GROUND
Connect to Vpp, Pin 48 for PLCC package.
'Different function than the HMOS 8208.
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
The Intel 82C08 Dynamic RAM Controller is a micro·
computer peripheral device which provides the nec·
essary signals to address, refresh, and directly drive
64K and 256K dynamic RAMs. It is compatible with
static column or ripple mode DRAMs in the normal
mode. It does not support the fast transfer mode of
these DRAMs.
Processor Interface
The 82C08 has control circuitry capable of supporting one of several possible bus structures. The
82C08 may be programmed to run synchronous or
asynchronous to the processor clock. The 82C08
has been optimized to run synchronously with Intel's
iAPX 86, iAPX 88, iAPX 186/188 and iAPX 286.
When the 82C08 is programmed to run in asynchronous mode, the 82C08 inserts the necessary synch~onization circuitry for the RD, WR inputs.
The 82C08 supports several microprocessor inter·
face options including synchronous and asynchro·
nous operations for iAPX 86, iAPX 186, iAPX 286,
and MULTIBUS. The 82C08 will also interface to
non-Intel microprocessors.
The 82C08 achieves high performance (Le. no wait
states) by decoding the status lines directly from the
processor. The 82C08 can also be programmed to
receive read or write MULTIBUS commands or commands from a bus controller.
The 82C08 is a CHMOS version of the 8208 and is
pin compatible with it. Three pins-17, 22, and 48of the 82C08 are different from the 8208. They provide a power down mode that allows the system to
run at a much lower ICC. In this mode, the 82C08
refreshes the DRAM using battery backup. The power down current (lpD) that is drawn by the 82C08 is
very small compared to the IcC which allows memory to be kept alive with a battery. A separate refresh
clock, pin 22, allows the designer to take advantage
of RAMs that permit extended memory refresh.
The 82C08 may be programmed to operate synchronously to the processor. It can also be programmed
to run at various frequencies. (See Microprocessor
Clock Frequency Option.)
Figure 2 shows the different processor interfaces to
the 82C08 using the synchronous or asynchronous
mode and status or command interface. Figure 3
shows detailed interfaces to the iAPX 186 and iAPX
286 processors.
The 82C08 also has some timing changes versus
the 8208. In order to eliminate the external bus
latches, both WE and CAS timings are shortened.
These timing changes are backwards-compatible for
8208 designs.
5-89
intJ
82C08
501-----.....
S11------I~
231357-3
231357-5
Slow-Cycle Synchronous-Status Interface
Slow-Cycle Asynchronous-Status Interface
231357-4
231357-6
Slow-Cycle Synchronous-Command Interface
Figure 2A. .Slow-cycle (CFS
=
Slow-Cycle Asynchronous-Command Interface
0) Port Interfaces Supported by the 82C08
5-90
82C08
I======::I_CLJ(
AD
WA
82C08
231357-9
231357-7
Fast-Cycle Asynchronous-Status Interface
Fast-Cycle Synchronous-Status Interface
231357-10
231357-8
'MULTIBUS OPTION
Fast-Cycle Synchronous-Command Interface
Figure 2B. Fast-cycle (CFS
=
Fast-Cycle Asynchronous-Command Interface
1) Port Interfaces Supported by the 82C08
5-91
82C08
.....
LATCHED
ADDRESS BUS
SYSTEM
ADDRESS BUS
231357-11
Figure 3A. 82C08 Interface to an 80186
OTHERS~
......CK
SIGNALS
I
l
usn
1-------;11
"'~~~1==========:::lfi
"to
80286 .,:;
82288.82284
IIEMORY
~
tUPPER)
r-F ;r::::'''i'''' f-!,
~V
r------Y
MEMORY
(LOWfR)
··J=I~I-""'l.;~~r-----v'r..;·-,·~
S2COa "'00_1
.,
1--------1"\
-
"AlO!
I
.t.
r
...
I.., to-I
ADOR
'"
I---
1------'-""
1-____-,,/)
LATCHED
ADDRESS BUS
r
-.-J;'-----......J-"t<".)
-'
SYSTEM
DATA BUS
231357-12
Figure 3B. 82C08 Interface to an 80286
5-92
82C08
Table 2 shows the bank selection decoding and
corresponding RAS and CAS assignments. For
ample, if only one RAM bank is occupied, then
two RAS and CAS strobes are activated with
same timing.
Dynamic RAM Interface
The 82C08 is capable of addressing 64K and 256K
dynamic RAMs. Figure 3 shows the connection of
the processor address bus to the 82C08 using the
different RAMs.
the
exthe
the
Table 2. Bank Selection Decoding
and Word Expansion
A11-A19
256K RAM
INTERFACE
Program
Bit
RB
Bank
Input
BS
82C08
RAS/CAS Pair Allocation
0
0
RASa, 1, CAS a, 1 to Bank 0
0
1
Illegal
1
0
RASa, CASa to Bank 0
1
1
RAS 1 , CAS1 to Bank 1
Program bit RB is not used to check the bank select
input BS. The system design must protect from accesses to "illegal", non-existent banks of memory
by deactivating the PE input when addressing an "illegal", non-existent bank of memory.
64K RAM
INTERFACE
231357-13
NOTES:
1. Unassigned address input pins should be strapped
high.
2. Aa along with BHE are used to select a byte within a
processor word.
3. Low order address bit is used as a bank select input
so that consecutive memory access requests are to alternate banks allowing bank interleaving of memory
cycles.
The 82C08 adjusts and optimizes internal timings for
either the fast or slow RAMs as programmed. (See
RAM Speed Option.)
Memory Initialization
After programming, the 82C08 performs eight RAM
"wake-up" cycles to prepare the dynamic RAM for
proper device operation.
Figure 3. Processor Address Interface to the
82C08 Using 64K, and 256K RAMS
The 82C08 divides memory into two banks, each
bank having its own Row (RAS) and Column (CAS)
Address Strobe pair. This organization permits RAM
cycle interleaving. RAM cycle interleaving overlaps
the start of the next RAM cycle with the RAM precharge period of the previous cycle. Hiding the precharge period of one RAM cycle behind the data
access period of the next RAM cycle optimizes
memory bandwidth and is effective as long as successive RAM cycles occur in the alternate banks.
Refresh
The 82C08 provides an internal refresh interval
counter and a refresh address counter to allow the
82C08 to refresh memory. The 82C08 has a 9-bit
internal refresh address counter which will refresh
128 rows every 2 milliseconds, 256 rows every 4
milliseconds or 512 rows every 8 milliseconds, which
allows all RAM refresh options to be supported. In
addition, there exists the ability to refresh 256 row
address locations every 2 milliseconds via the Refresh Period programming option.
Successive data access to the same bank cause the
82C08 to wait for the precharge time of the previous
RAM cycle. But when the 82C08 is programmed in
an iAPX 186 synchronous configuration, consecutive
cycles to the same bank do not result in additional
wait states (i.e. 0 wait state).
The 82C08 may be programmed for any of five different refresh options: Internal refresh only, External
refresh with failsafe protection, External refresh
without failsafe protection, Burst refresh modes, or
no refresh. (See Refresh Options.)
If not all RAM banks are occupied, the 82C08 can
be programmed to reassign the RAS and CAS
strobes to allow using wider data words without increasing the loading on the RAS and CAS drivers.
It is possible to decrease the refresh time interval by
10%,20% or 30%. This option allows the 82C08 to
compensate for reduced clock frequencies. Note
5-93
inter
82C08
that an additional 5% interval shortening is built-in in
all refresh interval options to compensate for clock
variations and non-immediate response to the internally generated refresh request. (See Refresh Period Options.)
SYSTEM
RE~
82C08
I
.
L-
I - - - t1~
RES~I..-._ _ _ _ _ _ __
t 1~~
PROGRAMMING
TIME ~==~
OF 82C08
________
External Refresh Requests after
RESET
DIFFERENTI~TED
TRESP
TPREP
= TPROG
+
RESET
NOTES:
231357 -14
1. Required only when the synchronization option is altered from its initial default value.
2. Vcc must be stable before system reset is activated
when using this circuit.
ego 82C08 System Response:
where: TPROG
82C08
RESET
SYSTEM
RESET
External refresh requests are not recognized by the
82C08 until after it is finished programming and preparing memory for access. Memory preparation includes.8 RAM cycles to prepare and ensure proper
dynamic RAM operation. The time it takes for· the
82C08 to recognize a request is shown below.
TPREP
= (40) (TClCl) programming time
Figure 4. 82C08 Differentiated Reset Circuit
= (8) (32) (TClCl) RAM
warm-up time
Within four clocks after RESET goes active, all the
82C08 outputs will go high, except for AOO-2, which
will go low.
if TClCl = 125 ns then TRESP =37 f-ts
Reset
OPERATIONAL DESCRIPTION
RESET is an asynchronous input, its falling edge is
used by the 82C08 to directly sample the logic levels
of the PCTl, RFRQ, and PDI inputs. The internally
synchronized falling edge of reset is used to begin
programming operations (shifting in the contents of
the external shift register, if needed, into the PDI
input).
Programming the 82C08
The 82C08is programmed after reset. On the falling
edge of RESET, the logic states of several input pins
are latched internally. The falling edge of RESET actually performs the latching, which means th~t the
logic levels on these inputs must be stable pnor to
that time. The inputs whose logic levels are latched
at the end of reset are the PCTl, RFRQ, and PDI
pins.
Differentiated reset is unnecessary when the default
synchronization programming is used.
Until programming is complete the 82C08 latches
but does not respond to command or status inputs.
A problem may occur if the S bit is programmed inconsistently from the Command which was latched
before programming was completed. A simple
means of preventing commands or status from occurring during this period is to differentiate the system reset pulse to obtain a smaller reset pulse for
the 82C08.
Status/Command Mode
The processor port of the 82C08 is configured by
the states of the PCTl pin. Which interface is selected depends on the state of the PCTl pin at the end
of reset. If PCTl is high at the end of reset, the
8086/80.186 Status interface is selected; if it is low,
then the MUlTIBUS or Command irHerface is selected.
The differentiated reset pulse would be shorter than
the system reset pulse by at least the programming
period required by the 82C08. The differentiated reset pulse first resets the 82C08, and system reset
would reset the rest of the system. While the rest of
the system is still in reset, the 82C08 completes its
programming. Figure 4 illustrates a circuit to accomplish this task.
The status lines of the 80286 are similar in code and
timing to the Multibus command lines, while the
status code and timing of the 8086 and 8088 are
identical to those of the 80186 and 80188 (ignoring
the differences in clock duty cycle). Thus there exists two interface configurations, one for the 80286
status or Multibus memory commands, which is
called the Command interface, and one for _8086,
5-94
inter
82C08
8088, 80186 or 80188 status, called the 8086 Status
interface. The Command interface can also directly
interface to the command lines of the bus controllers
for the 8086, 8088, 80186 and the 80286.
generated. If the RFRO pin is low immediately after
a reset, then the user has the choice of a single
external refresh cycle without failsafe, burst refresh
or no refresh.
The 80186 Status interface allows direct decoding of
the status lines for the iAPX 86, iAPX 88, iAPX 186
and the iAPX 188. Table 3 shows how the status
lines are decoded.
Internal Refresh Only
For the 82C08 to generate internal refresh requests,
it is necessary only to strap the RFRO input pin high.
Table 3A. Status Coding of 8086,
80186 and 80286
5tatus Code
External Refresh with Failsafe
Function
52
51
50
8086/80186
80286'
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
INTERRUPT
INTERRUPT
1
0
1
1
1/0 READ
1/0 READ
1/0 WRITE
1/0 WRITE
HALT
IDLE
INSTRUCTION
FETCH
HALT
1
MEMORY
READ
MEMORY
READ
0
MEMORY
WRITE
MEMORY
WRITE
1
1
1
IDLE
..
• Refer to 80286 pin description table
To allow user,-generated refresh requests with failsafe protection, it is necessary to hOld the RFRO
input high until after reset. Tbilreafter, a low-to-high
transition on this input causes a refresh request to
be generated and the internal refresh interval counter to be reset. A high-to-Iow transition has no effect
on the 82C08. A refresh request is not recognized
until a previous request has been serviced.
External Refresh without Failsafe
To generate single external refresh requests without
failsafe protection, it is necessary to hold RFRO low
until after reset. Thereafter, bringing RFRO high for
one clock period will cause a refresh request to be
generated. A refresh request is not recognized until
a previous request has been serviced.
IDLE
Table 38. 82C08 Response
82C08
Command
Function
PCTL RD WR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8086/801116 80286 Status or
Status
Command
Interface
Interface
IGNORE
IGNORE'
IGNORE
READ
IGNORE
WRITE
IGNORE
IGNORE
READ
IGNORE
READ
INHIBIT
WRITE
INHIBIT
IGNORE
IGNORE
Burst Refresh
Burst refresh is implemented through the same procedure as a single external refresh without failsafe
(Le., RFRO is kept low until after reset). Thereafter,
bringing RFRO high for at least two clock periods
will cause a burst of up to 128 row address locations
to be refreshed. A refresh request is not recognized
until a previous request has been serviced (Le. burst
is completed).
No Refresh
*lIlegal with CFS = 0
It is necessary to hold RFRO low until after reset.
This is the same as programming External Refresh
without Failsafe. No refresh is accomplished by
keeping RFRO low.
.
Refresh Options
Immediately after system reset, the state of the
RFRO input pin is examined. If RFRO is high, the
82C08 provides the user with the choice between
self-refresh and user-generated refresh with failsafe
protection. Failsafe protection guarantees that if the
user does not come back with another refresh request before the internal refresh interval counter
times out, a refresh request will be automatically
Option Program Data Word
PROGRAMMING FOR SLOW CYCLE
The program data word consists of 9 program data
bits, PDO-PD8. If the first program data bit, PDO is
5-95
inter
82C08
such as a 74HC165. The reset pulse serves to parallel load the shift register and the 82C08 supplies the
clocking signal (PCLK) to shift the data into the POI
programming pin. Figure 6 shows a sample circuit
diagram of an external shift register circuit.
set to logic 0, the 82C08 is configured to support
iAPX 186, 188, 86, or 88 systems. The remaining
bits, P01-P08, may then be programmed to optimize a selected system configuration. A default of all
zeros in the remaining program bits optimizes the
. 82C08 timing for 8 MHz Intel CPUs using 150 ns (or
faster) dynamic RAMs with no performance penalty.
Serial data is shifted into the 82C08 via the POI pin
(33), and clock is provided by the WE/PCLK pin
(25), which generates a total of 9 clock pulses.
PROGRAMMING FOR FAST CYCLE
WE/PCLK is a dual function pin. Ouring programming, it serves to clock the external shift register,
and after programming is completed, it reverts to the
write enable RAM control output pin, As the pin
changes state to provide the write enable signal to
the dynamic RAM array, it continues to clock the
shift register. This does not present a problem because data at the POI pin is ignored after programming. Figure 7 illustrates the timing requirements of
the shift register.
If the first program data bit is set to logic 1, the
82C08 is configured to support iAPX 286 systems
(Command mode). A default of all ones in the program bits optimizes the 82C08. timing for an 8 MHz
286 using 120 ns ORAMs at zero wait states. Note
that the programming bits P01 -8 change polarity
according to POO. This ensures the same choice of
options for both default modes.
Table 4A shows the various options that can be programmedinto the 82C08.
'
Default Programming Options
Table 4A. Program Data Word
Program
Name
Data Bit POO = 0 POO = 1
CFS = 0 SLOW CYCLE
CFS = 1 FAST CYCLE
PDO
CFS
CFS
PD1
S
S
s=o
SYNCHRONOUS'
8=1
ASYNCHRONOUS
PD2
RFS
RFS
RFS = 0 FAST RAM'
RFS = 1 SLOW RAM
PD3
RB
RB
RAM BANK
OCCUPANCY
SEE TABLE 2
CI1
PO"
PD5
CIO
PD6
PLS
CI1
CIO
PLS
Fast RAM (Note 1)
2 RAM banks occupied
128 row refresh in 2 ms; 256 in 4 ms, 512 in 8 ms
Fast processor clock frequency
PLS = o LONG
REFRESH PERIOD'
PLS = 1 SHORT
REFRESH PERIOD
FFS
FFS
FFS = 0 FAST CPU
FREQUENCY'
FFS = 1 SLOW CPU
FREQUENCY
PD8
X
X
X = OAACK*
X = 1 XACK
In
Table 48. Default Programming
Synchronous interface
COUNT INTERVAL BIT 1;
SEE TABLE 6
COUNT INTERVAL BIT 0;
SEE TABLE 6
PO?
* Default
After reset, the 82C08seriaily shifts in a program
data word via the POI pin. This pin may be strapped
low or high, or connected to an external shift register. Strapping POI low causes the 82C08 to default
to the iAPX 186 system configuration, while high
causes a default to the iAPX 286 configuration. Table 4B shows the characteristics of the default configuration for Fast Cycle (POI = 1) and Slow Cycle
(POI = 0). If further system flexibility is needed, one
external shift register, like a 74HC165, can be used
to'tailor the 82C08 to its operating environment.
PolarityIFunction
Advanced ACK strobe
NOTE:
1. For iAPX 86/186 systems either slow or fast (150 or
100 ns) RAMS will run at 8 MHz with zero wait states.
Synchronous/ Asynchronous Mode
(S program bit)
The 82C08 may be configured to accept synchronous or asynchronous commands (RO, WR, PCTL)
and Port Enable (PE) via the S program bit. The
state of theS programming bit determines whether
the interface is synchronous or asynchronous.
both modes
Using an External Shift Register
The 82C08 may be programmed by using an external shift register with asynchronous load capability
5-96
82C08
+5V
0
•,
I
0--0-0
I
,• ~
0
I
I
82C08
82C08
RESET
/ , - - r - - ---,
SHJrn
Q H 1------1 POI
74HC165
WE/PCLK
1---0""'"
ClK
~----;-------------------1RESET
231357-15
Figure 6. External Shift Register Interface
NOTES:
TRTVCL TPGVCL TCLPC TLOAD -
Reset is an asychronous input, if reset occurs before TRTVCL, then it is guaranteed to be recognized.
Minimum PDI valid time prior to reset going low.
MUX/PCLK delay.
Asychronous load data propagation delay.
Figure 7. Timing Illustrating External Shift Register Requirements for Programming the 82C08
While the 82C08 may be configured with either the
Status or Command (MULTIBUS) interface in the
Synchronous mode, certain restrictions exist in the
Asynchronous mode. An Asynchronous-Command
interface is directly supported. An Asynchronous80186/80286 Status interface using the status lines
of the 80186/80286 is supported with the use of
TTL gates as illustrated in Figure 2. In the 80186
case, the TTL gates are needed to guarantee that
status does not appear at the 82C08's inputs too
much before· address, so that a cycle would start
before address was valid. In the case of the 80286,
the TTL gates are used for lengthening the Status
pulse, as required by the TRWL timing.
Microprocessor Clock Cycle Option
(CFS and FFS program bits)
The 82C08 is programmed to interface with microprocessors with "slow cycle" timing like the 8086,
8088, 80186, and 80188, and with "fast cycle" microprocessors like the 80286. The CFS bit is used to
select the appropriate timing.
The FFS option is used to select the speed of the
microprocessor clock. Table 5 shows the. various microprocessor clock frequency options that can be
programmed. The external clock frequency must be
5-97
inter
82C08
programmed so that the failsafe refresh repetition
circuitry can adjust its internal timing accordingly to
produce a refresh request as programmed.
Table 6. Refresh Count Interval Table
Count Interval
C11,C10
Ref.
Period CFS PLS FFS . (82C08 Clock Periods)
(/Ls)
00
01
10
11
(0%) (10%) (20%) (30%)
Table 5. Microprocessor Clock
Frequency Options
Program Bits
CFS
FFS
0
0
0
1
Processor
iAPX86,
88,186,188
iAPX86,
88,186,188
Clock
Frequency
~
5MHz
> 5MHz
1
0
iAPX 286
~
1
1
iAPX 286
> 10 MHz
10 MHz
RAM Speed Option (RFS program bit)
The RAM Speed programming option determines
whether RAM timing will be optimized for a fast or
slow RAM. Whether a RAM is fast or slow is measured relative to 100 ns DRAMs (fast) or 150 ns
DRAMs (slow). This option is only a factor in Fast
cycle Mode (CFS = 1).
15.6
1
1
1
236
212
188
164
7.8
1
0
1
118
106
94
82
15.6
1
1
0
148
132
116
100
7.8
1
0
0
74
66
58
50
15.6
0
1
1
118
106
94
82
7.8
0
0
1.
59
53
47
41
15.6
0
1
0
74
66
58
50
7.8
0
0
0
37
33
29
25
The refresh count interval is set up for the following
basic frequencies:
5 MHz slow cycle
8 MHz slow cycle
10 MHz fast cycle
16 MHz fast cycle
Refresh Period Options (CIO, CI1 and
PLS program bits)
Example: Best 12 MHz fast cycle performance can
be achieved using the basic frequency of 16 MHz
(CFS = 1, FFS = 1) and the appropriate count in·
terval bits (C11 = 1, CIO = 1) to reduce the frequency.
The 82C08 refreshes with either 128 rows every 2
milliseconds, with 256 rows every 4 milliseconds or
512 rows every 8 milliseconds. This translates to
one refresh cycle being executed approximately
once every 15.6 microseconds. This rate can be
changed to 256 rows every 2 milliseconds or a refresh approximately once every 7.8 microseconds
via the Period Long/Short, program bit PLS, programming option.
clock period x refresh count interval
=
refresh period
i.e. 83.3 ns x 164 = 13.6 fLs
Example: 10 MHz slow cycle
The Count Interval 0 (CIO) and Count Interval 1 (CI1)
programming options allow the rate at which refresh
requests are generated to be increased in order to
permit refresh requests to be generated close to the
15.6 or 7.8 microsecond period when the 82C08 is
operating at reduced frequencies. The interval between refreshes is decreased by 0%,10%,20%, or
30% as a function of how the count interval bits are
programmed. A 5% guardband is built·in to allow for
any clock frequency variations. Table 6 shows the
refresh period options available.
CFS = 0, FFS = 1, Cll = 0, CIO = 0
i.e. 100 ns x 118.= 11.8 fLs
Processor Timing
In order to run without wait states, AACK must be
used and connected to the SRDY input of the appropriate bus controller. AACK is issued relative to a
point within 'the RAM cycle and has no fixed relationship to the processors's request. The timing is such,
however, that the processor will run without wait
states, barring refresh cycles. In slow cycle, fast
RAM configurations (8086, 80186), AACK is issued
on the same clock cycle that issues RAS.
The numbers tabulated under Count Interval represent the number of clock periods between internal
refresh requests. The percentages in parentheses
represent the decrease in the interval between refresh requests.
Port Enable (PE) set-up time requirements depend
on whether the 82C08 is configured for synchronous
5-98
infef
82C08
or asynchronous, fast or slow cycle operation. In a
synchronous fast cycle configuration, PE is required
to be set-up to the same clock edge as the commands. If PE is true (low), a RAM cycle is started; if
not, the cycle is not started until the RD or WR line
goes inactive and active again.
If the X programming bit is high, the strobe is configured as XACK, while if the bit is low, the strobe is
configured as AACK.
Data will always be valid a fixed time after the occurrence of the advanced acknowledge. Thus, the advanced acknowledge may also serve as a RAM cycle timing indicator.
In asychronous operation, PE is required to be setup to the same clock edge as the internally synchronized status or commands. Externally, this allows
the internal synchronization delay to be added to the
status (or command) -to-PE delay time, thus allowing
for more external decode time than is available in
synchronous operation.
General System Considerations
1. The RASO, 1, CASO, 1, and AOO-8 output buffers
are designed to directly drive the heavy capacitive
loads of the dynamic RAM arrays. To keep the
RAM driver outputs from ringing excessively in the
system environment it is necessary to match the
output impedance with the RAM array by using
series resistors. Each application may have different impedance characteristics and may require
different series resistance values. The series resistance values should be determined for each
application.
The minimum synchronization delay is the additional
amount that PE must be held valid. If PE is not held
valid for the maximum synchronization delay time, it
is possible that PE will go invalid prior to the status
or command being synchronized. In such a case the
82C08 may not start a memory cycle. If a memory
cycle intended for the 82C08 is not started, then no
acknowledge (AACK or XACK) is issued and the
processor locks up in endless wait states.
2. Although the 82C08 has programmable options,
in practice there are only a few choices the designer must make. For iAPX 86/186 systems
(CFS = 0) the C2 default mode (pin 33 tied low)
is the best choice. This permits zero wait states at
8 and 10 MHz with 150 ns DRAMs. The only consideration is the refresh rate, which must be programmed if the CPU is run at less than 8 MHz.
Memory Acknowledge (AACK, XACK)
Two types of memory acknowledge signals are supplied by the 82C08. They are the Advanced Acknowledge strobe (AACK) and the Transfer Acknowledge strobe (XACK). The S programming bit
optimizes AACK for synchronous operation ("early"
AACK) or asynchronous operation ("late" AACK).
Both the early and late AACK strobes are two clocks
long for CFS = 0 and three clocks long for CFS =
For iAPX 286 systems (CFS = 1) the designer
must choose between configuration CO (RFS =
0) and C1 (RFS = 1, FFS = 0). CO permits zero
wait state, 8 MHz iAPX 286 operation with 120 ns
DRAMs. However, for consecutive reads, this performance depends on interleaving between two
banks. The C1 configuration trades off 1 wait
state performance for the ability to use 150 ns
DRAMs. 150 ns DRAMs can be supported by the
CO configuration using 7 MHz iAPX 286.
1.
The XACK strobe is asserted when data is valid (for
reads) or when data may be removed (for writes)
and meets the MULTIBUS requirements. XACK is
removed asynchronously by the command going
inactive.
3. For non-Intel microprocessors, the asynchronous
command mode would be the .best choice,. since
Intel status lines are not available. To minimize
the synchronization delay, the 82C08 should use
a 16 MHz clock. The preferred timing configuration is CO.
Since in an asynchronous operation the 82C08 removes read data before late AACK or XACK is recognized by the CPU, the user must provide for data
latching in the system until the CPU reads the data.
In synchronous operation data latching is unnecessary, since the 82C08 will not remove data until the
CPU has read it.
Table 7. Memory Acknowledge Summary
Synchronous
Asynchronous
XACK
Fast Cycle
AACK Optimized
for Local 80286 (early)
AACK Optimized for
Remote 80286 (late)
Multibus Compatible
Slow Cycle
AACK Optimized
for Local 8086/186 (early)
AACK Optimized for
Remote 8086/186 (late)
Multibus Compatible
5-99
82C08
power down immediately· without executing any
bursts.
POWER DOWN
During Power Down (PO) mode, the 82C08 will perform refresh cycles to preserve the memory content.
Two pins are dedicated to this feature, POD (Power
Down Detect) and POCLK (Power Down Clock).
POD is used to inform the 82C08 of a system power
failure, and will remain active as long as the power is
down. It is the system's responsibility to detect power failure and to supply this signal. PDCLK is used to
supply the clock during power down for the 82C08
refresh circuits. It is the system's responsibility to
supply this clock.
Power Supplies
Power down is achieved by eliminating the clock
from all the 82C08 circuits that are not participating
in the refresh generation. The 82C08 has two power
pins (Vcc's), one supplies power to the outputbuffers and the other, to 82C08 logic. All the active circuitsduring power down are connected to the logi?
Vee, including the active output buffers. Therefore, .It
is the user's choice to connect only the logic Vee pin
to the back-up power supply, or to connect both pins
to it. It is recommended, however, to connect both
pins to the same power supply in order to simplify
and to shorten the power up time.
Power Down Procedure
The 82C08 will preserve the memory content during
the entire period of the system operation. Upon detection of power down, the 82C08 will save internally
its configuration status and the refresh address
counter content, execute 3 burst refresh cycles: (If it
is programmed to failsafe mode and the RFRO Input
level is high), it will switch the internal clock from the
system clock (CLK) to the power down clock
(PDCLK) and will continue the refresh to the next
address location. (See Figure 11.)
When power is up again (POD input deactivated),
the 82C08 will issue internal reset which will. not reprogram the device and will not clear the refresh
address counter,and therefore, refresh will continue
to the next address location. After the internal reset,
82C08 performs 3 PO burst refresh cycles which refresh the whole memory, as at entering extended
PD. This is done to give the 82C08 enough time to
wake up. Notice, at the time interval of 4700 (fast
cycle) or 3100 (slow cycle) clocks after power recovering no memory access will be performed.
82C08 Outputs on Power Down
Extended Refresh at Power Down (PO)
To reduce power dissipation during PO, 82C08 will
support the extended refresh cycle of the Intel
51CXXL (e.g. 51C64L). In this mode, the refresh period can be extended up to 64 milliseconds versus
4 milliseconds in non-extended cycles. This is
achieved by slowing down the PDCLK frequency.
The user should take into consideration that when
supporting extended refresh during PO, the dynamic
RAM must be refreshed completely within 4 milliseconds, without active cycles, both before going into
and after coming out of extended refresh. The
82C08 has the option of performing burstrefresh of
all the memory whenever the user cannot guarantee
the 4 milliseconds idle interval. This is achieved by
performing 3 consecutive burst refresh cycles, activated internally by the 82C08.
The option of refreshing all the memory is enabled in
failsafe mode configuration (RFRO input high at reset). When 82C08 detects power down, (high level
at POD) it examines the RFRO input. High level at
the RFRO input will cause 3 PO burst refresh cycles
to be performed. The user should supply the power
and the system clock during the time interval of the
3 PO burst cycles, e.g. 4700 (fast cycle) or 3100
(slow cycle) clock cycles after activating POD. Low
level at RFRO input enables the 82C08 to enter
Four of the 82C08 outputs are not activated during
power down, AACK, CASO-1 and WE. All these outputs will be forced to a non-active state, AACK and
CASO-1 will be forced high and WE will be forced
low (External NAND buffer is used to drive the V-:E
DRAM inputs, hence a high level on the DRAM Inputs). The other 82C08 outputs, AOO-9 and RA?O1, will switch to perform the memory refresh In a
"RAS-ONL Y REFRESH CYCLE." The RAS outputs
internal pull-ups assure high levels on these outputs,
as close as possible to Vee, for low DRAM power.
The size of the output buffers, in power down, is
smaller than the normal size, and therefore, the
speed of these buffers is slower. It is done in order
to reduce the speed of charging and discharging the
outputs and hence reduce spikes on the power
lines. It is required especially in power down, since
there is only one power supply pin active which
drives the output buffers as well as the internal logic.
All the device inputs, beside POD, PDCLK, and RESET will be ignored during power down.
During power down burst refresh the 82C08 performs up to 256 refreshes. Whereas during standard
burst refresh the 82C08 performs up to 128 refreshes. The power down burst refresh feature allows the
82C08 to support extended refreshes of some
DRAMs, configured as 512 rows.
5-100
inter
82C08
OSC.
J
RAS#
PDCLK
AO
J
____________________ ___________
-Jx~
231357-18
Figure 8
Power Down Detect
As previously mentioned, the PDD input will be supplied by the system to inform the 82C08 of a power
failure. It can be asynchronous since the 82C08 synchronizes it internally. The PDD input will be sampled by the 82C08 before the beginning of every
memory cycle but only after the termination of programming and initialization period. The user should
guarantee Vee and CLK stable during the programming and initialization period (300 clocks after RESET). If the whole memory refresh is required (for
extended refresh) then Vee and system clock
should be available 4700 (fast cycle) or 3100 (slow
cycle) clocks after activating PDD. If it isn't required
then 82C08 should wait for present memory cycle
completion and synchronization time which will take
about 25 system clock cycles.
With PDD going inactive, the 82C08 synchronizes
the clock back to the CLK clock, issuing internal reset ana will perform 3 PD burst refresh cycles.
NOTE:
During power down, 'RAS-ONLY REFRESH' will be
performed by the 82C08. The time interval between
refreshes is 5 PDCLKs and this is fixed for all applications. However, the 82C08 can support the extended refresh (up to 64 ms) by slowing down the
PDCLK frequency.
During the power down refresh cycle, RAS will be
activated for one PDCLK cycle only. In extended refresh, the PDCLK frequency will be below 50 kHz
and this will cause a long duration of the RAS signal
which will increase the DRAM's current rapidly. To
minimize the RAS low pulse, the two RC networks
shown in Figure 9 are designed to insert one very
fast (1 /-Ls) cycle whenever RAS is low (see Figure
8). The time constant of RC1 and RC2 should be
centered around 300 ns and 100 ns respectively.
82C08
LOW FREQUENCY
OSCILLATOR
The power supplies and the CLK should go up before the PDD is deactivated. All CPU requests will
be ignored when PDD is active.
HC132
Refresh during Power Down
The 82C08 has two clock pins, CLK is the system
clock and PDCLK is the power down clock. PDCLK
should be an independent clock which has its own
crystal oscillator. When entering power down, the
82C08 will disable the system clock internally and
will run with the PDCLK. The system clock will be
enabled and the PDCLK will be disabled when power is up. The CLK and PDCLK will be switched internally for the refresh circuits.
PDCLK
(GND)
RAS.
I
Vcc~
231357-19
Figure 9. Low Frequency Oscillator
5-101
inter
82C08
time after PDD is activated is 4700 (fast cycle) or
3100 (slow cycle) clocks.
Power Down Synchronization
The 82C08 main clock (MClK) is generated internally, from the system clock (ClK) and the power down
clock (PDClK) (see Figure 10), and is driving the
circuits that are active at all times, Le.: circuits that
are active both in power down mode and in normal
operation. The system clock (ClK) is driving the circuits that are active in normal operation only, and
the PDClK is driving the circuits that are active in
power down only. The operation of the three clocks
is as follows:
When entering power down mode, and the whole
memory refresh is required, the ClK minimum active
PO __________
CLK
n
J
n
~
n
__
When it isn't required, PDClK should be active, and
ClK should remain active for at least 20 clock cycles + synchronization time. The synchronization
time is the ratio of PDClK and ClK + 1. Therefore,
the ClK minimum active time after PD is activated:
20
+ [CLK(MHz) / PDCLK(MHz) + 11 clock cycles
When the power is up again, PDClK should remain
active at least 4 clock cycles after PD is going inactive, to assure completion of refresh cycle and internal synchronization time.
\
"
~-J'
,~------------------
n r----------, n n U n U r
LJ - LJ LJ LJ __________ -LJ 'LJ
PDCLK
MCLK
231357-20
Figure 10
POWER DOWN FLOW
SET POFLAG,
DISABLE WE, AACKIf, CAS#
DISABLE elK, ENS POCLK
OUT
231357-21
Figure 11
5-102
infef
82C08
Differences Between 8208 and 82C08
The differences between the HMOS 8208 and the
CHMOS 82C08 represent forward compatible enhancements. The 82C08 can be plugged into an
8208 socket without changes.
ClK
I
1/
I
TCLCSH~V-
RAS~
\ .......- - - - - - 1 ' 1
\
CAS
LOGICAL DIFFERENCES
1. 82C08 has one new feature:
I
Power Down (PO)
2. 82C08 supports CMOS DRAMs with T RAC 100,
150
2) 82C08 has an additional timing parameter
TARH column address to RAS i hold time.
3. Address Mapping:
Outputs
8208
82C08
9 Most
Significant Bits
column address
row address
I
231357-22
2. DC parameters: The difference is in the current
consumption.
9 Least
Significant Bits
ICC
row address
column address
4. Slow cycle shortening:
1). The write cycle is two clocks shorter so consecutive writes will be executed without wait
states.
2) The WE output is two clocks shorter. Therefore, an external latch on the WE output is not
necessary.
3) CAS output is shorter by one clock on the read
cycle. This reduces one level of buffers for address/data bus needed in 8208 designs. Read
access margins are improved to support nonIntel spec. RAMs.
4) The address outputs switch from row to column address one clock cycle later in the
82C08 as compared to 8208.
5. Fast cycle shortening:
1) The write cycle in CO configuration is shortened
by one clock.
2) For both CO and C1 synchronous configuration,
the CAS signal is shorter by one clock and the
activation of RAS is tied to the <1>2 cycle of the
80286. This prevents contention on the data
bus.
6. Supports Static Column or Ripplemode DRAMs.
8208
82C08
300mA
30 mA (typical)
[10 + 2f] mA (max)
1 mA (max)
2 mA(max)
IPD
ISB
Configuration Charts
The 82C08 operates in three basic configurationsCO, C1, C2-depending upon the programming of
CFS (PDO), RFS (PD2), and FFS (PD7). Table 8
shows these configurations. These modes determine the clock edges for the 82C08's programmable
signals, as shown in Table 9. Finally, Table 10 gives
the programmable AC parameters of the 82C08 as a
function of configuration. The non-programmable
parameters are listed under AC Characteristics.
Using the Timing Charts
The notation used to indicate which clock edge triggers an output transition is "n i" or "n -.L ", where
"n" is the number of clock periods that have passed
since clock 0, the reference clock, and " i" refers
to rising edge and" -.L " to falling edge. A clock period is defined as the interval from a clock falling edge
to the following falling edge. Clock edges are defined as shown below.
ELECTRICAL DIFFERENCES
1. AC parameters:
1) CAS delay: In C2 synchronous read cycle, the
CAS is deactivated by some delay from clock
falling edge (TCLCSH timing) as in the following diagram:
In C2 write cycles the CAS activation is triggered by the clock falling edge with a delay of
35 ns from the clock. For 8208 the delay is
TP/1.8 + 53.
(n-1)1
nl
nl
(n + 1)1 (n + 1 ) 1
231357-23
The clock edges which trigger transitions on each
82C08 output are tabulated in Table 9. "H" refers to
the high-going transition, and "L" to low-going transition.
5-103
82C08
Clock a is defined as the clock in which the 82C08
begins a memory cycle, either as a result of a port
request which has just arrived, or of a port request
which was stored previously but could not be serv-
iced at the time of its arrival because the 82C08 was
performing another memory cycle. Clock a is identified externally by the leading edge of RAS, which is
always triggered onO J,.
Table 8. 82C08 Configurations
Timing Cont.
CFS(PDO)
RFS(PD2)
FFS(PD7)
Wait States'
Co
iAPX286(1)
FAST RAM(1)
20 MHz(1)
Co
iAPX286(1)
FAST RAM(1)
16 MHz(1)
a
a
C1
iAPX286(1)
SLOW RAM(O)
16 MHz(1)
1
Co
iAPX286(1)
FAST RAM(1)
10 MHz (0)
Co
iAPX286(1)
SLOW RAM(O)
10 MHz (0)
C2
iAPX186(0)
DON'T CARE
DON'T CARE
a
a
a
• USing EAACK (synchronous mode)
Table 9a. Timing Chart - Synchronous Mode
RAS
Cn
a
Cycle
L
RD,RF
oj,
oj,
oj,
oj,
oj,
oj,
WR
1
RD,RF
WR
2
RD,RF
WR
ADDRESS
H
Col
Row'
3J,
oj,
oj,
oj,
oj,
oj,
oj,
4J,
4J,
5J,
2J,
2J,
CAS
WE
L
H
3J,
1 J,
3J,
3J,
2J,
4J,
4J,
1 J,
5J,
4J,
2J,
5J,
3J,
oj,
2J,
3.J,
1 J,
3 J,.
EAACK
H
L
1 J,
4J,
1 J,
5J,
oj,
2J,
L
H
1 J,
4J,
1 J,
4.J,
2J,
5J,
2J,
5J,
oj,
2.J,
O.J,
2.J,
Table 9b. Timing Chart - Asynchronous Mode
RAS
CAS
ADDRESS
Cn
Cycle
L
H
Col
Row'
L
H
a
RD,RF
3J,
0.J,
3.J,
1.J,
4J,
4J,
oj,
oj,
oj,
oj,
oj,
3J,
2.J,
4J,
4J,
1J,
6J,
WR
oj,
oj,
oj,
oj,
RD,RF
O.J,
2J,
WR
oj,
2J,
WR
1
2
RD,RF
4J,
5J,
4J,
2J,
5J,
3J,
oj,
3J,
3J,
1J,
3J,
LAACK
WE
H
1 J,
1 J,
oj,
L
4J,
5J,
2J,
XAACK
L
H
L
H
2.J,
5J,
3.J,
RD
q,
4J,
3J,
WR
2J,
5J,
4J,
RD
1J,
4J,
3J,
WR
1 J,
3J,
2.J,
RD'
1t
3j
2.J,
WR
The only difference between the two tables IS the trailing edge of CAS for all read cycle configurations. In asynchronous mode, CAS trailing edge is one clock later than in synchronous mode.
NOTES FOR INTERPRETING THE TIMING CHART:
1. COLUMN ADDRESS is the time column address becomes valid.
2. The CAS, EAACK, LAACK and XACK outputs are not issued during refresh.
3. XACK-high is reset asynchronously by command going inactive and' not by a clock edge.
4. EAACK is used in synchronous mode, LAACK and XACK in asynchronous mode..
5. ADDRESS-Row is the clock edge where the 82C08 AO switches from current column address to
the next row address.
6. If a cycle is inhibited by PCTL = 1 (Multibus IfF mode) then CAS is not activated during write
cycle and XACK is not activated in either read or write cycles.
'Column addresses switch to row addresses for next memory cycle. The row address buffer is
transparent following this clock edge. 'TRAH' specification is guaranteed as per data sheet.
5-104
inter
82C08
82C08-0RAM Interface Parameter
Equations
Several DRAM parameters, but not all, are a direct
function of 82C08 timings, and the equations for
these parameters are given in the following tables.
The following is a list of those DRAM parameters
which have NOT been included in the following tables, with an explanation for their exclusion.
READ,
tRAC:
tCAC:
tREF:
tCRP:
WRITE REFRESH CYCLES
response parameter.
response parameter.
See "Refresh Period Options".
must be met only if CAS-only cycles,
which do not occur with 82C08, exist.
tRAH: See "A.C. Characteristics"
tRCD: See "A.C. Characteristics"
tASC: See "A.C. Characteristics"
tASR: See "A.C. Characteristics"
tOFF: response parameter.
WRITE CYCLE
tDS: system-dependent parameter.
!DH:
s~'s!e!':!~depe!"'!de!""!t f-1e.~~metl?r.
tDHR: system-dependent parameter.
Table 10. Programmable Timings
Read and Refresh Cycles
Parameter
tRP
tCPN
tCPN
tRSH
tCSH
tCSH
tCAH
tAR
IT
tRC
tRAS
tCAS
tCAS
tRCS
tRCH
C2-Slow Cycle
2TCLCL·T27
1.5TCLCL·T34
2.5TCLCL-T34
2TCLCL·T32
3TCLCL-T25
2TCLCL + T34(min)·T25
3TCLCL-T32
3TCLCL-T25
3/30
4TCLCL
2TCLCL-T25
3TCLCL-T32
2TCLCL + T34(min)-T32
TCLCL + T32(min)-T35 + TSUF
TCLCL + T36(min)-T34 + TBUF
CO-Fast Cycle
3TCLCL·T27
3TCLCL·T34
4TCLCL-T34
2TCLCL·T32
4TCLCL-T25
3TCLCL-T25
2TCLCL-T32
3TCLCL-T25
3/30
6TCLCL
3TCLCL-T25
3TCLCL-T32
2TCLCL-T25
TCLCL-T35 + TSUF
TCLCL-T34 + TSUF
C1-Fast Cycle
3TCLCL·T27
2TCLCL·T34
3TCLCL·T34
3TCLCL·T32
6TCLCL-T25
5TCLCL-T25
3TCLCL-T32
4TCLCL-T25
3/30
7TCLCL
4TCLCL-T25
5TCLCL-T32
4TCLCL-T32
2TCLCL-T35 + TSUF
2TCLCL-T34 + TSUF
Notes
1
1,5
1,4
1
1,5
1,4
1
1
2
1
1
1,5
1,4
1
1
Write Cycles
Parameter
C2-Slow Cycle
CO-Fast Cycle
tRP
2TCLCL-T27
3TCLCL-T27
tCPN
2TCLCL-T34
4TCLCL-T34
tRSH
TCLCL-T32
2TCLCL-T32
tCSH
3TCLCL-T25
4TCLCL-T25
tCAH
2TCLCL-T32
TCLCL-T32
tAR
3TCLCL-T25
3TCLCL-T25
3/30
3/30
tT
tRC
4TCLCL
7TCLCL
tRAS
2TCLCL-T25
4TCLCL-T25
tCAS
2TCLCL-T32 + TSUF
2TCLCL-T32
tWCH
TCLCL-T32 + TSUF
2TCLCL-T32 + TSUF
tWCR
2TCLCL-T25 + TSUF
4TCLCL-T25 + TSUF
3TCLCL-T36-TSUF
tWP
2TCLCL-T3.6-TSU F
tRWL
2TCLCL-T36-TSUF
3TCLCL-T36-TSUF
tCWL
3TCLCL-T36-TSUF
3TCLCL-T36-TSUF
TCLCL+ T36-T31-TSUF
TCLCL - T36-TSUF
tWCS
NOTES:
1. Minimum.
2. Value on right is maximum; value on left is minimum.
3. Applies to the eight warm-up cycles during initialization.
4. For synchronous mode only.
5. For asynchronous mode only.
5-105
C1·Fast ~cle
3TCLCL-T27
4TCLCL-T34
3TCLCL-T32
5TCLCL-T25
2TCLCL-T32
4TCLCL-T25
3/30
BTCLCL'
5TCLCL-T25
3TCLCL-T32
3TCLCL-T32 + TSUF
5TCLCL-T25 + TSUF
4TCLCL-T36-TSUF
4TCLCL-T36-TSUF
4TCLCL-T36-TSUF
TCLCL - T36-TSUF
Notes
1
1
1
1
1
1
2
1
1
1
1,3
1,3
1
1
1
1
intJ
82C08
* Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied ExposlJre to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias
-O·C to + 70·C
Storage Temperature
- 65·C to + 150·C
Voltage On Any Pin With
Respect to Ground
-0.5Vto +7V
0.5W
Power Dissipation
D.C. CHARACTERISTICS
Symbol
TA
=
O·Cto 70·C; Vee
Parameter
=
5.0V ±10%;Vss
=
GND
Min
Max
Units
Comments
Vil
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage
0.45
V
(Note 1)
VOH
Output High Voltage
V
(Note 1)
2.6
lee
Supply Current
III
Input Leakage Current
Vel
Clock Input Low Voltage
VeH
Clock Input High Voltage
CIN
Input Capacitance
VOHPD
RAS Output High
Power Down
IpD
19B
NOTE.
(Note 3)
10 + 2f
rnA
±10
,...A
-0.5
+0.6
V
3.8
Vee + 0.5
V
20
pF
fc = 1 MHz(6)
V
(Note 2)
Vee - 0.5
OV:O;: VIN
:0;:
Power Down Supply Current
-
5.0
rnA
(Note 5)
Standby Current
-
2.0
rnA
(Note 4)
1.IOL = 5 mA and IOH = -0.32 mA WE: IOL = 8 mA
2. RASOutput voltage during power down.
3; Typical value. Where f is freq. in MHz.
for CMOS: VIL max = 0.5V; VIH min = (Vcc - 0.5V)
for TTL: Icc will be higher by 30 mA
A.C. Testing Load Circuit
Vee
4. Measured at VIL -- OV and VIH -- Vcc with no loads
connected.
5. IPD = 1 mA at 32 KHz with no loads connected.
6. Sampled. not 100% tested. TA = 25'C.
A.C. Testing Input, Output Waveform
0_2_:,_---JX::
::
A. ___
231357-25
RRAS = 390
RCAS = 390
RAO = 220
231357-24
A.C. Tes1ing inpu1s (except clock) are driven at 2.4V for a Logic
CRAS = 150 pF
CCAS = 150pF
CAO = 200 pF
CL=50pF
"1" and 0.45V for a Logic "0" (clock' is driven at 4.0V and 0.45V
for Logic "1" and "0" respectively). Timing measurements are
made at 2.4V for Logic "1" and O.BV for Logic "0".
• also PDCLK
5-106
82C08
A.C. CHARACTERISTICS (TA
= ODCto 70DC; Vee = +5V ±10%, vss = OV)
Measurements made with respect to RASo_1' CASO_1, ADo-B' are at +2.4Vand 0.8V ClK at 3V, 1V. All other
pins are measured at 2.0V and 0.8V. All times are ns unless otherwise indicated. Testing done with specified
test load.
Ref
Symbol
Parameter
Min
Max
Units
Notes
CLOCK AND PROGRAMMING
-1
2
3
tF
Clock Fall Time
12
ns
3
tR
Clock Rise Time
12
ns
3
TClCl
Clock Period
TCl
TCH
~~~
tl~COil-;20
50
&:.iJV
ii3
~
82C08-16
82C08-10
82C08-8
62.5
100
125
250
500
500
ns
ns
ns
1
2
2
Clock low Time
82C08-20
82C08-16
82C08-10
82C08-8
12
15
44
TClCl/2-12
230
230
ns
ns
ns
ns
1
1
2
2
Clock High Time
82C08-20
82C08-16
82C08-10
82C08-8
16
20
44
TClCLl3+2
230
230
ns
ns
ns
ns
1
1
2
2
40
ns
4
4
TRTVCl
Reset to ClK.J, Setup
5
TRTH
Reset Pulse Width
4TClCl
ns
6
TPGVRTl
PCTl, POI, RFRO
to RESET .J, Setup
125
ns
7
TRTlPGX
PCTl, RFRO
to RESET .J, Hold
10
ns
8
TClPC
PClK from ClK.J, Delay
9
TPDICl
POI to ClK.J, Setup
60
ns
10
TClPDX
POI to ClK.J, Hold
40
ns
45
5
ns
6
SYNCHRONOUS /LP PORT INTERFACE
11
TPEVCl
PE to ClK.J, Setup
30
12
TKVCl
RD, WR, PE, PCTl
to ClK .J, Setup
20
ns
13
TClKX
RD, WR, PE,PCTl
toClK.J,Hold
0
ns
14
TKVCH
RD, WR, PCTl
to ClK i Setup
20
ns
5-107
2
1
2
inter
82C08
A.C. CHARACTERISTICS (Continued) .
Ref
Symbol
Parameter
Min
.
Max
Units
Notes
ASYNCHRONOUS ,..,p PORT INTERFACE
15
TAWVCl
AD, WAto
ClKJ.Setup
16
TAWl
AD, WAPuise
Width
17
TAWlPEV
PEfrom AD,
WAJ. Delay
CFS=1
CFS=O
. PEto AD,
WA J. Hold
18
TAWlPEX
19
TAWlPTV
.20
TAWlPTX
21
TAWlPTV
PCTl from AD,
WAJ. Delay
22
TAWlPTX
PCTl toAD,
WAJ. Hold
20
ns
?TClCl+30
ns
TClCl-20
TClCl-30
2TClCl+30
PCTl from AD,
WA J. Delay
8.9 .
1
2
ns
ns
ns
ns
2
ns
2
ns
1
3TClCl+30
ns
1
Al,AH, BSto
ClK J. Set-up
82C08-20
82C08-16
35 + tASA
ns
2
50+tASA
45+tASA
ns
ns
Al,AH, BSto
ClKJ. Hold
0
ns
PCTl to AD,
. WAJ. Hold
TClCl-30
2TClCl+30
2TClCl-20
RAM INTERFACE
23
24
TAVCl
TCLAX
25
TClASl
AAS J. from
ClK J.. Delay
26
TACO
AAS to CAS Delay
CFS=1
CFS=O
CFS=O
CFS=:O
27
TClASH
I.
25
35
60
TClCl-25
30
TClCl/2-30
60
25
60
AASj from
ClKJ. Delay
5-108
ns
ns
ns
1
2
24
ns
ns
ns
ns
1,14
23
2,11,14
2,12,14
ns
ns
24
inter
82C08
A.C. CHARACTERISTICS (Continued)
Ref
Symbol
Parameter
Min
Max
Units
Notes
ns
ns
1, 13, 15
2,11,15
23
RAM INTERFACE (Continued)
28
TRAH
CFS = 1
CFS=O
CFS=O
29
TASR
Row AD
RAS t Setup
30
TASC
Column AD to
CAS! Setup
CFS=1
CFS=O
CFS=O
31
TCAH
Column AD to
CAS Hold
32
TClCSl
CASt from
ClK! Delay
CFS=O
CFS=O
CFS=O
CFS=1
34
TClCSH
18
TClCl/4-10
18
10,16
WEt from
ClKt Delay
36
TClWH
WEi from
ClK !Delay
CFS=O
CFS=1
CFS=O
TClCl/1.8 + 56
105
35
35
ns
ns
ns
ns
2,26
23,26
2,23,27
1
50
ns
TClCl
--+50
3.2
ns
35
ns
TClCll 1.8 + 53
35
100
ns
ns
(See DRAM Interface Tables)
TClCLl4+30
50
8
TClCl/4
TClWl
i, i3, if, 10
2,13,17,18
23
5
5
CAS i from
ClK! Delay
35
ns
ns
ns
2
TClCl/4+30
50
37
TClTKl
XACK! from
ClK t Delay
35
ns
38
TRWlTKH
XACK i from RD i ,
WR i Delay
50
ns
39
TClAKl
AACK! from
ClKt Delay
35
ns
40
TClAKH
AACKi from
ClKt Delay
50
ns
49
TARH
Column Address to
RAS i Hold Time
2
5-109
22
2
1
23
1
intJ
82C08
A.C. CHARACTERISTICS (Continued)
Ref
Symbol
Parameter
Mill
Max
Units
Notes
REFRESH REQUEST
41
TRFVCl
RFRO to ClK J.- Setup
20
42
TClRFX
RFRO to ClK J.- Hold
10
43
TFRFH
Failsafe RFRO Pulse
Width
44
TRFXCl
Single RFRO Inactive
to ClK J.- Setup
45
TBRFH
Burst RFRO Pulse
Width
46
TPDDVCl
PDD Setup Time
20
47
TPDHRFX
RFRO Valid after
PDD Active
4TClCl
48
TRFVPDH
RFRO Setup Time
to PDD Active
TClCl
ns
ns
+ 30
20
2TClCl
20
+ 30
+ 20
ns
19
ns
20
ns
19
ns
24,25
24
24
The following RC loading IS assumed:
AOO-8·
R = 2211
C = 200 pF
RASo_1, CASO_1 R = 3911
C = 150 pF
AACK, WE/PClK
C = 50 pF
NOTES:
1. Specification when programmed in the Fast Cycle processor mode (iAPX 286 mode). 82C08-20, -16.
2. Specification when programmed in the Slow Cycle processor mode (iAPX 186 mode). 82C08-10, 82C08-8.
3. tR and tF are referenced from the 3.5V and 1.0V levels.
4. RESET is internally synchronized to ClK. Hence a set-up time is required only to guarantee its recognition at a particular
clock edge.
5. The first programming bit (PDO) is also sampled by RESET going low.
6. TClPDX is guaranteed if programming data is shifted using PClK.
8. TRWVCl is not required for an asynchronous command except to guarantee its recognition at a particular clock edge.
9. Valid when programmed in either Fast or Slow Cycle mode.
10. tASR is a user specified parameter and its value should be added accordingly to TAVCL.
11. When programmed in Slow Cycle mode imd 125 ns s TClCl < 200 ns.
12. When programmed in Slow Cycle mode and 200 ns s TClCL.
13. Specification for Test load conditions.
14. tRCD (actual) = tRCD (specification) +0.06 (
MEMORY
(UPPER)
PCTl
POI ~
RO 8207 WE-
74S240
230862-1
NOTE:
The 8207 requires series resistors on all outputs.
Figure 1.80286 to 8207, non-ECC, Synchronous System Single Port
5-124
inter
AP-168
T5
Tc
T5
Tc
T1
T5
Tc
Tc
Tc
16 MHz
CLOCK
SO-S1
80286
ADDR.
LEN
RASO
RAS1
CASO
DRAM WE
EAACK
230862-2
Figure 2. 80286/8207 Timing-"CO"
+5
74504
A23
A22
8207
PE
A21
74530
A20
A19
230862-3
Figure 3. Address Decode Logic
5-125
AP-168
Ts
Tc
Ts or T1
230862-4
Figure 4. Acknowledge to the 82284
Address Setup Margin
The 8207 must have stable addresses up to two clocks
after RAS goes active. This is of no concern to the user,
since LEN latches the address internally and will not
admit a new address until two clocks after RAS goes
active.
Addresses must be stable at least 35 ns (tAVCL) before
RAS goes active to allow for propagation delays
through the 8207, if a RAM cycle is not delayed by the
8207.
tASR is a RAM specification. If it is greater than zero,
tASR must be added to the address setup time of the
8207. Address setup is the interval between addresses
being issued, by the 80286, and RAS going active, minus appropriate delays.
The margin is determined from the number of clocks
between addresses being issued from the 80286 to RAS
going active. Exactly when RAS goes active is unimportant, since here we are only interested in the clock
edge.
2TClCl - 80286113 (max) - 8207 TAVCl (min) ,;; 0
125 ns - 60 ns - 35 ns = 30 ns
Acknowledge Setup Margin
The 8207 acknowledge (EAACK) can be issued at any
point in the 80286 bus cycle (end of 1 or 2 of Ts or
Tc). If EAACK is issued at the end of 2 (Ts or Tc),
the 80286 will complete the current bus cycle. If
EAACK is issued at the end of 1 ofTc, the 82284 will
not generate READY to the 80286 in time to end the
current bus cycle. A new Tc would then be generated
and EAACK would now be sampled in time to terminate the bus cycle. EAACK is 3 clocks long in order to
meet setup and hold times for either condition.
We need the margin between the 8207 issuing EAACK
and the 82284 needing it. Figure 4 shows a worst case
example.
TClCl - 8207 TClAKL max - 82284 111 ,;; 0
62.5 ns - 35 ns - 15 ns = 12.5 ns
Read Access Margin
The 8207 will typically start a memory cycle (i.e. RAS
goes low) at the end of 1 of Ts. But if the start of a
memory cycle is delayed (by a refresh cycle for instance), then RAS will be delayed. In the first case, this
represents 3 clocks and the second case could require 4
clocks to meet the data setup requirements of the
80286. In either case, data must be valid at the end of
Tc. The 8207 holds CAS active long enough to ensure
valid data is received by the 80286 in either case.
DRAMs specify two access times, RAS access (tRAC)
and CAS access (tCAC) Both access periods must be
calculated and the one with the least margin used. Also
the number of data buffers should be kept to a minimum. Too many buffers would require either faster
(more expensive) DRAMs, or a reduction in the performance of the CPU (by adding wait states).
5-126
Ap·168
RAS Access Margin
Write Data Setup and Hold Margin
3TCLCL - 8207 TCLR8L max @ 150 pF - DRAM tRAC
- 748240 propagation delay max @ 50 pF - 80286 t8 s
Write data from the processor must be valid when the
8207 issues WE to meet the DRAM specification tDS
and then held to meet the tDR requirement. Some
write cycles will be byte writes and the information to
determine which byte is decoded from AO and BREI.
Since the 80286's address bus is pipelined, these two
signals can change before the RAM cycle starts, hence
they must be latched by LEN. PSEN is used in the WE
term to shorten the WE pulse. Its use is not essential.
o
187.5 ns - 35 ns - 120 ns - 7 ns - 10 ns
=
15.5 ns
CAS Access Margin
2TCLCL - 820-7 TGLG5L max @ 150 pF - DRAM tCAA
(or tGAG - 748240 tplh max @ 50 pF - 80286 t8) S 0
-I"~
_...
lc..oJ 1 ..0>
By solving each equation for tRAC and tCAC, the
speed requirement of the RAM can be determined.
DRAM tRAG = 3 TCLGL - 8207 TGLR8L - 748240 tplh
- 82086 t8 = 135.5 ns
DRAM tCAG = 2 TCLGL - 8207 TGLG8L - 748240 tplh
- 80286 t8 = 73 ns
Data must be set up to the falling edge of WE, since
,VE occurs aiter CA.S. Tilt: 2. CiUCKS UCLWCCJl vi:ll~u w£itc
data and WE going active (at the RAM's) minus propagation delays determines the margin.
2 TCLCL - 80286 t14 (max) @ 100 pF - 748240 tplh +
8207 TGLW (min)1 + 74510 tphl @ 192 pF2 - DRAM
t08 = 0
125 ns - 50 ns - 7 ns
NOTES:
1. Not specified. Assume no delay for worst case analysis.
2. STTL derated by 0.05 ns/pF.
So any DRAM that has a RAS access period less than
135 'ns, a CAS access period less than 73 ns, and meets
all requirements in the DRAM Interface Timing (Table
IS, 16-8207 Data Sheet), will work.
+ 0 ns + 14 ns - 0 ns
=
82 ns
The timing of the 8207's acknowledge is such that data
will be kept valid by the 80286, for more than two
clocks after WE goes active. This easily meets all RAM
tDR specifications.
SUMMARY
The 8207 complements the 80286's performance and
high integration with its own performance, integration
and ease of use. No critical timings or logic design has
been left to the designer. The 80286/8207 combination
allows users to realize maximum performance from
their simpler design.
5-127
Support Peripherals
6
8231A
ARITHMETIC PROCESSING UNIT
•
•
•
•
Fixed Point Single and Double
Precision (16/32 Bit)
•
Floating Point Single Precision (32 Bit)
Direct Memory Access or Programmed
• 1/0
Data Transfers
Binary Data Formats
•
•
•+
•
•
End of Execution Signal
Add, Subtract, Multiply and Divide
and Inverse Trigonometric
• Trignometric
Functions
•
General Purpose 8-Bit Data Bus
Interface
Standard 24 Pin Package
Square Roots, Logarithms,
Exponentiation
Float to Fixed and Fixed to Float
• Conversions
•
Compatible with all Intel and most
other Microprocessor Families
12V and
+ 5V Power Supplies
Advanced N-Channel Silicon Gate
HMOS Technology
Stack Oriented Operand Storage
The Intel® 8231A Arithmetic Processing Unit (APU) is a monolithic HMOS LSI device that provides high
performance fixed and floating point arithmetic and floating point trigonometric operations. It may be used to
enhance the mathematical capability of a wide variety of processor-oriented systems. Chebyshev polynomials
are used in the implementation of the APU algorithms.
All transfers, including operand, result, status and command information, take place over an a-bit bidirectional
data bus. Operands are pushed onto an internal stack and commands are issued to perform operations on the
data and the stack. Results are then available to be retrieved from the stack.
Transfers to and from the APU may be handled by the associated processor using conventional programmed
110, or may be handled by a direct memory access controller for improved performance. Upon completion of
each command, the APU issues an end of execution signal that may be used as an interrupt by the CPU to
help coordinate program execution.
Vss
Vee
EACK
SIIACK
SVREO
DO NOTUIE
(TIE LOW)
I
DB.
I
6
' -_ _...:..I
231305-2
Figure 2. Pin Configuration
231305-1
Figure 1. Block Diagram
6-1
September 1987
Order Number: 231305-002
intJ
8231A
Table 1. Pin Description
Symbol
Pin
No.
Name and Function
Type
Vee
2
POWER:
VDD
16
POWER:
+ 5V power supply.
+ 12V power supply.
,
Vss
1
CLK
23
I
GROUND.
CLOCK: An external, TTL compatible, timing source is applied to the
CLK pin.
RESET
22
I
RESET: The active high reset signal provides initialization for the chip.
RESET also terminates any operation in progress. RESET clears the
status register and places the 8231 A into the idle state. Stack contents
and command registers are not affected (5 clock cycles).
CS
18
I
CHIP SELECT: CS is an active low input signal which selects the 8231 A
and enables communication with the data bus.
Ao
21
I
ADDRESS: In conjunction with the RD and WR signals, the Ao control
line establishes the type of communication that is to be performed with
the 8231 A as shown below:
Ao
RD
WR
0
0
1
0
0
1
0
1
1
1
1
0
Function
Enter data byte into stack
Read data byte from stack
Enter command
Read status
RD
20
I
READ: This active low input indicates that data or status is to be read
from the 8231 A if CS is low.
WR
19
I
WRITE: This active low input indicates that data or a command is to be
written into the 8231 A if CS is low.
EACK
3
I
END OF EXECUTION: This active low input clears the end of execution
output signal (END. If EACK is tied low, the END output will be a pulse
that is one clock period wide.
SVACK
4
I
SERVICE REQUEST: This active low input clears the service request
output (SVREQ).
END
24
0
END: This active low, open-drain output indicates that execution of the
previously entered command is complete. It can be used as an interrupt
request and is cleared by EACK, RESET or any read or write access to
the 8231.
SVREQ
5
0
SERVICE REQUEST: This active high output signal indicates that
command execution is complete and that post execution service was
requested in the previous command byte. It is cleared by SVACK, the
next command output to the device, or by RESET.
READY
17
0
READY: This active high output indicates that the 8231 A is able to
accept communication with the data bus. When an attempt is made to
read data, write data or to enter a new command while the 8231 A is
.executing a command, READY goes low until execution of the current
command is complete (See READY Operation, p. 6).
8-15
110
DBO-DB7
DATA BUS: These eight bidirectional lines provide for transfer of
commands, status and data between the 8231A and the CPU. The
8231A can drive the data bus only when CS and RD are low.
6-2
8231A
sion of the data to be operated upon by fixed point
commands only (if bit 5 = 0, bit 6 must be 0). If bit 6
is a 1, single-precision (16-bit) operands are assumed. If bit 6 is a 0, double-precision (32-bit) operands are indicated. Results are undefined for all illegal combinations of bits in the command byte. Bit 7
indicates whether a service request is to be issued
after the command is executed. If bit 7 is a 1, the
service request output (SVREO) will go high at the
conclusion of the command and will remain high until reset by a low level on the service acknowledge
pin (SVACK) or until completion of execution of the
succeeding command where service request (bit 7)
is O. Each command issued to the 8231A requests
post execution service based upon the state OT oit 7
in the command byte. When bit 7 is a 0, SVREO
remains low.
COMMAND STRUCTURE
Each command entered into the 8231A consists of a
single 8-bit byte having the format illustrated below:
I
SVREO IL _ _ _ _ _ _ OPERATION
IR,
1'-
S'NGLE
I
FIXED
I
I
CODE
I--~-----II
I
I
231305-3
Bits 0-4 select the operation to be performed as
shown in ir Ie lCtuit::. i3iL~ G-G 5~:.sCt tho d~t~ fc:-~~!
appropriate to the selected operation. If bit 5 is a 1, a
fixed point data format is specified. If bit 5 is 0, floating point format is specified. Bit 6 selects the preci-
Table 2. 32-Bit Floating Point Instructions
Description
Instruction
Hex(1)
Code
Stack Contents(2)
After Execution
ABCD
Status Flags(4)
Affected
ACOS
Inverse Cosine of A
06
RUUU
S,l,E
ASIN
Inverse Sine of A
05
RUUU
S,l,E
ATAN
Inverse Tangent of A
07
RBUU
CHSF
Sign Change of A
15
RBCD
COS
Cosine of A (radians)
03
RBUU
S,l
S,l
S,l
EXP
eA Function
OA
RBUU
S,l,E
FADD
Add A and B
10
RCDU
S,l,E
FDIV
Divide B by A
13
RCDU
S,l,E
FLTD
32-Bit Integer to Floating Point Conversion
1C
RBCU
FLTS
16-Bit Integer to Floating Point Conversion
1D
RBCU
S,l
S,l
FMUL
Multiply A and B
12
RCDU
S,l,E
FSUB
Subtract A from B
11
RCDU
S,l,E
LOG
Common Logarithm (base 10) of A
08
RBUU
S,l,E
LN
Natural Logarithm of A
09
RBUU
S,l,E
POPF
Stack Pop
18
BCDA
PTOF
Stack Push
17
AABC
PUPI
Push
onto Stack
1A
RABC
S,l
S,l
S,l
PWR
BA Power Function
OB
RCUU
S,l,E
SIN
Sine of A (radians)
02
RBUU
S,l
SORT
Square Root of A
01
RBCU
S,l,E
TAN
Tangent of A (radians)
04
RBUU
S,l,E
XCHF
Exchange A and B
19
BACD
S,l
7T
6-3
intJ
8231A
Table 3 32·Bit Integer Instructions
Stack Contents(2)
Hex(1)
Description
After Execution
Code
ABCD
Instruction
Status Flags(4)
Affected
CHSD
Sign Change of A
34
RBCD
S,Z,O
DADO
Add A and B
2C
RCDA
S,Z,C,E
.. S,Z, E
DDIV
Divide B byA
2F
RCDU
DMUL
Multiply A and B (R = lower 32-bits)
2E
RCDU
S,Z,O
DMUU
Multiply A andS (R = upper 32-bits)
36
RCDU
S,Z,O
DSUB
Subtract A from B
20
RCDA
S,Z,C,O
FIXD
Floating Point to Integer Conversion
1E
RBCU
S,Z,O
POPD
Stack Pop
38
BCDA
S,Z
PTOD
Stack Push
37
AABC
S,Z
XCHD
Exchange A and B
39
BACD
S,Z
Table 4 16·Bit Integer Instructions
Stack Contents(3)
Hex(1)
Status Flags(4)
Instruction
Description
After Execution
Affected
Code
DL
Au AL Bu BL Cu CL Du
CHSS
Change Sign of Au
74
R AL Bu BL Cu CL Du DL
S,Z,O
FIXS
1F
R Bu BL Cu CL U U U
S,Z,O
Floating Point to Integer Conversion
POPS
Stack Pop
78
AL Bu BL Cu CL Du DL Au
PTOS
Stack Push
77
SADD
Add Au and AL
6C
SDIV
Divide AL by Au
SMUL
Multiply AL by Au (R
Au Au AL Bu BL Cu
R Bu BL Cu CL Du
R Bu BL Cu CL Du
R Bu BL Cu CL Du
6F
S,Z
DL Au
DL U
S,Z,C,E
SMUU
=
Multiply AL by Au (R =
SSUB
Subtract Au from AL
XCHS
Exchange Au and AL
79
AL AL Bu BL Cu CL Du DL
NOP
No Operation
00
Au AL Bu BL Cu CL Du DL
lower 16-bits)
6E
upper 16-bits)
76
60
S,Z
CL Du
S,Z,E
DL U
R Bu BL Cu CL Du DL U
R Bu BL Cu CL Du DL Au
S,Z,E
S,Z,C,E
S,Z
S,Z,E
NOTES:
1. In the hex code column; SVREQ is a O.
2. The stack initially is composed of four 32-bit numbers (A, B, C, D). Ais equivalent to TopOl Stack (TOS) and B is Next
On Stack (NOS). Upon completion of a command the stack is composed of: the result (R); undefined (U); or the initial
contents (A. B, C, or D).
3. The stack initially is composed of eight 16-bit numbers (Au, AL. Bu. BL. Cu. CL. Du. DLJ. Au is the TOS and AL is NOS.
Upon completion of a command the stack is composed of: the result (R); undefined (U); or the initial contents (Au. AL. Bu.
BL··· ).
4. Nomenclature: Sign (S); Zero (Z); Overflow (0); Carry (C); Error Code Field (E).
Single Precision Fixed Point Format
DATA FORMATS
The 8231A arithmetic processing unit handles operands in both fixed point and floating point formats.
Fixed point operands may be represented in either
single (16-bit operands) or double precision (32-bit
operands). and are always represented as binary.
two's complement values.
231305-4
6-4
infef
8231A
fractional mantissa value between 0.5 and 1 multiplied by 2 raised to an appropriate power. This is
expressed as follows:
Double Precision Fixed Point Format
l:]Jil' I I 11·1 I I I I VjllE I I I I I I I I I I I I 11"11
"
value = mantissa X 2ex ponent
a
231305-5
For example, the value 100.5 expressed in this form
is 0.11001001 x 27. The decimal equivalent of this
value may be computed by summing the components (powers of two) of the mantissa and then multiplying by the exponent as shown below:
The sign (positive or negative) of the operand is located in the most significant bit (MSB). Positive values are represented by a sign bit of zero (S = 0).
Negative values are represented by the two's complement of the corresponding positive value with a
sign bit equal to 1 (::i = 1). Ine range of vaiues lhal
may be accommodated by each of these formats is
-32,768 to +32,767 for single precision and
-2,147,483,648 to +2,147,483,647 for double precision.
=
0.78515625 x 128
= 100.5
FLOATING POINT FORMAT
Floating point binary values are represented in a format that permits arithmetic to be performed in a
fashion analogous to operations with decimal values
expressed in scientific notation.
The format for floating point values in the 8231A is
given below. The mantissa is expressed as a 24-bit
(fractional) value; the exponent is expressed as a
two's complement 7-bit value having a range of - 64
to + 63. The most significant bit is the sign of the
mantissa (0 = positive, 1 = negative), for a total of
32 bits. The binary point is assumed to be the left of
th~ most significant mantissa bit (bit 23). All floating
pOint data values must be normalized. Bit 23 must
be equal to 1, except for the value zero, which is
represented by all zeros.
(5.83 X 10 2) (8.16 X 10 1) = (4.75728 X 104)
In the decimal system, data may be expressed as
values between 0 and 10 times 10 raised to a power
that effectively shifts the implied decimal point right
or left the number of places necessary to express
the result in conventional form (e.g., 47,572.8). The
value-portion of the data is called the mantissa. The
exponent may be either negative or positive.
I.
The concept of floating point notation has both a
gain and a loss associated with it. The gain is the
ability to represent the significant digits of data with
values spanning a large dynamic range limited only
by the capacity of the exponent field. For example,
in. decimal notation in the exponent field is two digits
Wide, and the mantissa is five digits, a range of values (positive or negative) from 1.0000 x 10- 99 to
9.9999 X 10+ 99 can be accommodated. The loss is
that only the significant digits of the value can be
represented. Thus there is no distinction in this representation between the values 123451 and
123452, for example since each would be expressed
as: 1.2345 x 105 . The sixth digit has been discarded. In most applications where the dynamic range of
values to be represented in large, the loss of significance, and hence accuracy of results, is a minor
consideration. For greater precision a fixed point format could be chosen, although with a loss of potential dynamic range.
EXPONENT
~I ~ I
31 30
1-
MAN",,,
IIIII IIIIIIIIIIIIIIIIIIIIIII
2423
I
0
231305-6
The range of values that can be represented in this
format is ± (2.7 x 10- 20 to 9.2 x 10 18) and zero.
FUNCTIONAL DESCRIPTION
STACK CONTROL
The user interface to the 8231A includes access to
an 8 level 16-bit wide data stack. Since single precision fixed point operands are 16-bits in length, eight
such values may be maintained in the stack. When
using double precision fixed pOint or floating point
formats four values may be stored. The stack in
these two configurations can be visualized as shown
below:
The 8231A is a binary arithmetic processor and requires that floating point data be represented by a
6-5
intJ
TOS
~
NOS
~
8231A
A'
B'
At
Bt
TOS
NOS
A4
A3
A2
Al
I--"'"' --'-'"=.'-,--,,"=--2-,--",Bt'-j
ister is cleared and the Service Request bit of the
command register is checked. If it is a "1" the service request output level (SVREQ) is raised. END is.
cleared on receipt of an active low End Acknowledge (EACK) pulse. Similarly, the service request
line is cleared by recognition of an active low Service Acknowledge (SVACK) pulse.
1
,
I--L--L--'---i!
--32--
231305-8
READY OPERATION
-16-
231305-7
An active high ready (READY) is provided. This line
is high in its quiescent state and is pulled low by the
8231A under the following conditions:
Data are written onto the stack, eight bits at a time,
in the order shown (A 1, A2, A3, ... ). Data are removed from the stack in reverse byte order (A4, A3,
A2 ... ). Data should be entered onto the stack in
multiples of the number of bytes appropriate to the
chosen data format.
1. A previouly initiated operation is in progress (device busy) and Command Entry has been attempted. In this case, the READY line will be pulled low
and remain low until completion of the current
command execution. It will then go high, permitting entry of the new command.
DATA ENTRY
2. A previously initiated operation is in progress and
stack access has been attempted. In this case,
the READY line will be pulled low, will remain in
that state until execution is complete, and will
then be raised to permit completion of the stack
access.
3. The 8231 A is not busy, and data removal has
been requested. READY will be pulled low for the
length of time necessary to transfer the byte from
the top of stack to the interface latch, and will
then go high, indicating availability of the data.
Data entry is accomplished by bringing the chip select (CS), the command/data line (Ao), and WR low,
as shown in the timing diagram. The entry of each
new data word "pushes down" the previously entered data and places the new byte on the top of
stack (TOS). Data on the bottom of the stack prior to
a stack entry are lost.
DATA REMOVAL
Data are removed from the stack in the 8231 A by
bringing chip select (CS), command/data (Ao), and
RD low as shown in the timing diagram. The removal
of each data world redefines TOS so that the next
successive byte to be removed becomes TOS. Data
removed from the stack rotates to the bottom of the
stack.
4. The 8231A is not busy, and a data entry has been
requested. READY will be pulled low for the
length of time required to ascertain if the preceding data byte, if any, has been written to the stack.
If so READY will immediately go high. If not,
READY will remain low until the interface latch is
free and will then go high.
5. When a status read has been requested, READY
will be pulled low for the length of time necessary
to transfer the status to the interface latch, and
will then be raised to permit completion of the
status read. Status may be read whether or not
the 8231A is busy.
COMMAND ENTRY
After the appropriate number of bytes of data have
been entered onto the stack, a command may be
issued to perform an operation on that data. Commands which require two operands for execution
(e.g., add) operate on the TOS and NOS values. Single operand commands operate only on the TOS.
When READY goes low, the APU expects the bus
control signals present at the time to remain stable
until READY goes high.
Commands are issued to the 8231A by bringing the
chip select (CS) line low, command data (Ao) line
high, and WR line low as indicated by the timing diagram. After a command is issued, the CPU can continue execution of its program concurrently with the
8231 A command execution.
DEVICE STATUS
Device status is provided by means of an internal
status register whose format is shown below:
I
COMMAND COMPLETION
The 8231A signals the completion of each command execution by lowering the End Execution line
(END). Simultaneously, the busy bit in the status reg-
BUSY
SIGN
ZERO
t=l
1 -1--1
ERROR CODE
CARRY
231305-9
6-6
I
infef
8231A
Busy:
Indicates that 8231 A is currently executing a command (1 = Busy)
Sign:
Indicates that the value on the top of
stack is negative (1 = Negative)
Zero:
Indicates that the value on the top of
stack is zero (1 = Value is zero)
not) by bringing the chip select (CS) low, the command/data line (Ao) high, and lowering RD. The
status register is then gated onto the data bus and
may be input by the CPU.
EXECUTION TIMES
Error Code: This field contains an indication of the
validity of the result of the last operation. The error codes are:
OOOO-No error
Timing for execution of the 8231A command set is
contained below. All times are given in terms of
clock cycles. Where substantial variation of execution times is possible, the minimum and maximum
values are quoted; otherwise, typical values are givon
!:lro nCltCl
.... ....\I~riCltinn~
-.. .. - -'--.- rlononrltlnt
--,-_ .. __ ....
1OOO-Divide by zero
1"\041"\1"\
("'0_ • • _ _ _
V I V V -....I\.tUQ11;:;;
_
............ _
~
IUV~
VI
1 __
.... ~
........ .- ....... : .......
IV~
VI
Ilv~UU.,
.....
-~.-
number
Total execution times may require allowances for
operand transfer into the APU, command execution,
and result retrieval from the APU. Except for command execution, these times will be heavily influenced by the nature of the data, the control interface
used, the speed of memory, the CPU used, the priority allotted to DMA and interrupt operations, the size
and number of operands to be transferred, and the
use of chained calculations, etc.
1100-Argument of inverse sine, cosine, or eX too large
XX10-Underflow
XX01-0verflow
Carry:
Previous operation resulted in carry or
borrow from most significant bit. (1 =
Carry/Borrow, 0 = No Carry/No Borrow).
If the BUSY bit in the status register is a one, the
other status bits are not defined; if zero, indicating
not busy the operation is complete and the other
status bits are defined as given above.
DERIVED FUNCTION DISCUSSION
Computer approximations of transcendental functions are often based on some form of polynomial
equation, such as:
READ STATUS
(1-1)
The 8231A status register can be read by the CPU
at any time (whether an operation is in progress or
Table 5. Command Execution Times
Command
Mnemonic
Clock
Cycles
Command
Mnemonic
Clock
Cycles
Command
Mnemonic
Clock
Cycles
Command
Mnemonic
Clock
Cycles
SADD
SSUB
SMUL
SMUU
SDIV
DADD
DSUB
DMUL
DMUU
DDIV
FIXS
FIXD
FLTS
FLTD
. 17
30
84-94
80-98
84-94
21
38
194-210
182-218
208
92-216
100-346
98-186
98-378
FADD
FSUB
FMUL
54-368
70-370
146-168
LN
EXP
PWR
4298-6956
3794-4878
8290-12032
POPF
XCHS
XCHD
12
18
26
FDIV
SORT
SIN
COS
154-184
800
4464
4118
NOP
CHSS
CHSD
CHSF
4
23
27
18
XCHF
PUPI
26
16
TAN
ASIN
ACOS
ATAN
LOG
5754
7668
7734
6006
4474-7132
PTOS
PTOD
PTOF
POPS
POPD
16
20
20
10
12
6-7
intJ
8231A
The primary shortcoming of an approximation is this
form is that it typically exhibi~s very large errors
when the magnitude of Ixi is large, although the errors are small when Ixl is small. With polynomials in
this form, the error distribution is markedly uneven
over any arbitrary interval.
The error for the power function is a combination of
that for the logarithm and exponential functions.
Each of the derived functions is an approximation of
the true function. Thus the result of a derived function will have an error. The absolute error is the difference between the function's result and the true
result. A more useful measure of the function's error
is relative error (absolute error/true result). This
gives a measurement of the significant digits of algorithm accuracy. For the derived functions except LN,
LOG, and PWR the relative error is typically 4 x
10- 7. For PWR the relative error is the summation
of theEXP and LN errors, 7 x 10- 7 . For LN and
LOG, the absolute error is 2 X 10- 7.
A set of approximating functions exists that not only
minimizes the maximum error but also provides an
even distribution of errors within the selected data
representation interval. These are known as Chebyshev Polynomials and are based upon cosine
functions. These functions are defined as follows:
Tn(X) = Cos n8; where n = 0, 1,2 ...
(1-2)
8=COS-1X
APPLICATION INFORMATION
The various terms of the Chebyshev series can be
computed as shown below:
To(X) = Cos (0 x 8) = Cos (0) =1
(1-4)
(1-7)
The diagram in Figure 4 shows the interface connections for the APU with operand transfers handled by
an 8237 DMA controller, and CPU coordination han~
died by an Interrupt Controller. The APU interrypts
the CPU to indicate that a command has been completed. When the performance enhancements provided by the DMA and Interrupt operations are not
required, the APU interface can be simplified as
shown in Figure 3. The 8231A APU is designed with
a general purpose 8-bit data bus and interface control so that it can be conveniently used with any general 8-bit processor.
Common logarithms are computed by multiplication
of the natural logarithm by the conversion factor
0.43429448 and the error function is therefore the
same as that for natural logarithm. The power function is realized by combination of natural log and
exponential functions according to the equation:
In many systems it will be convenient to use the microcomputer .system clock to drive the APU clock
input. In the case of 8080A systems it would be the
2TTL signal. Its cycle time will usually fall in the
range of 250 ns to 1000 ns, depending on the system speed.
T1(X) = Cos (Cos -1X) =
T2(X) = Cos 28
= 2Cos2 8
x
- 1
(1-5)
= 2Cos2(Cos -1X)
-1
(1-6)
= 2X 2 - 1
In general,. the next term in the Chebyshev series
can be recursively derived from the previous term as
follows:
.
Tn(X) = 2X [Tn - 1(X)1 - Tn - 2(X); n <: 2
xY
=
eyLnx.
r-________
~A~DD~R~ES~S~.~US~____~--~~~
,...-_1...1-_..,
lOR
CPU
IO-------.-(JI
iOW
WR
CLOCK
elK
READY
READY
~-~~]~~--~
Ao
RD
cs
8231A
ARITHMETIC
PROCESSOR
UNIT
~---~~~I~--~
""'7
....
7
SYSTEM DATA BUS
231305-10
Figure 3_ Minimum Configuration Example
6-8
cl
ADDRESS BUS
1:1
8205
DECODER
"1'1
lEi
c
Cil
CLOCK
;
iiiEMii
CD
3DI
0
w
~
..
c>w
'"
I
I II
1\
-VI
lOR
CPU
-
CI)
I'.)
...
w
iow
~
READY
~
cc'
,---0 Vee
a0'
WR
~
INTAb
.. dlNTA
m
"iD
IQ ~ I~
iiEiiW
~
=
3
~
~--_T~~~~~~~~~~
'U
CD
8231
DMA CONTROLLER
I~
HOLD 14--------------+-+-+--IHRQ
::I:
co
AB-AIS
AD-A1
HLDA ~--~~---------------------r--~--;--'iHLDA
c'
:::T
~
()
l
cs
P-
AO-AIS
~
en
,
~
~
INTI-
liNT
cs
liD
8259A
DBD-DB1
....::;-~
1l
1Z-
Ifl~I~~
IRO
END
__
EACK
INTERRUPT
CONTROLLER
DBD-DB1
+
0'0'
AD
w
>
>
'"
01)
01)
Po'
1;Ili1
ol
8231A
ARITHMETIC
PROCESSOR UNIT
~7
t...
SYSTEM DATA BUS
V
231305-11
inter
8231A
• Notice: Stresses above those listed under 'j4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature .' ......... - 65·C to + 150·C
Ambient Temperature Under Bias ...... O·C to 70·C
Voo with Respect to Vss ........ -0.5V to
+ 15.0V
Vee with Respect to Vss ......... -0.5V to + 7.0V
All Signal Voltages with Respect
to Vss ....................... -0.5V to + 7.0V
Power Dissipation .......................... 2.0W
D.C. AND OPERATING CHARACTERISTICS
o·c to 70·C, Vss = OV, Vee = +5V ±10%, voo = +12V ±10%
TA =
Parameters
Description
Min
VOH
Output HIGH Voltage
3.7
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IlL
IOFL
Typ
Units
V
IOH = -200/-LA
0.4
V
IOL = 3.2 rnA
2.0
Vee
V
~0.5
0.8
V
Input Load Current
±10
/-LA
Vss ,,;: VIN ,,;: Vee
Data Bus Leakage
±10
/-LA
Vss + 0.45 ,,;: Vour ,,;: Vee
lee
Vee Supply Current
50
95
rnA
100
Voo Supply Current
50
95
rnA
Co
Output Capacitance
8
CI
Input Capacitance
5
pF
10
pF
CIO
Test Conditions
Max
I/O Capacitance
pF
fc = 1.0 MHz, Inputs = OV(1)
NOTE:
1. Sampled, not 100% tested.
x=
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
37==>(
0.4
20
LO
>TESTPOINTS<
0.8
0.8
DEVICE
UNDER
TEST
231305-12
A.C. Testing: Inputs are driven at 3.7V for a logical "1" and O.4V
for a logic "0". Timing measurements are made at 2.0V for a logic
"1" and O.BV for a logic "0".
231305-13
6-10
inter
8231A
A.C. CHARACTERISTICS
=
TA
0·Cto70·C, vss
=
OV, vcc
=
+5V ±10%. voo
=
+12V ±10%
READ OPERATION
8231A-8
Symbol
8231A
Parameter
Units
Min
Max
Min
Max
tAR
Ao, CS Setup to RD
0
0
ns
tRA
Ao, CS Hold from RD
0
0
ns
tRY
READY
tYR
Ready
tRRR
READY Pulse Width (Note 3)
J,
t
J,
from RD
to RD
Delay (Note 2)
t
tROE
Data Bus Enable from RD J,
tORY
Data Valid to READY
tOF
Data Float after RD
150
100
ns
0
0
ns
Data
3.5 tCY
+ 50
3.5 tcy
+ 50
ns
Status
1.5 tCY
+ 50
1.5 tcy
+ 50
ns
50
50
ns
0
0
ns
t
t
50
200
50
100
ns
WRITE OPERATION
8231A-8
Symbol
Units
Min.
tAW
Ao, CS Setup to WR
tWA
Ao, CS Hold after WR
tWY
READY
J,
from WR
READY
t
t
tyW
8231A
Parameter
to WF:!
J,
Max.
0
0
ns
25
ns
150
0
READY Pulse Width (Note 4)
tWI
Write Inactive Time
(Note 4)
tow
Data Setup to WR
two
Data Hold after WR
I
I
Max.
60
Delay (Note 2)
tRRW
Min.
100
0
50
ns
ns
50
ns
Command
4tCY
4tCY
ns
Data
5tCY
5tCY
ns
150
100
ns
20
20
ns
6-11
inter
8231A
OTHER TIMINGS
Symbol
8231A-8
Parameter
Min
Max
Min
Max
5000
250
2500
tCY
Clock Period
480
tCPH
Clock Pulse High Width
200
tCPL
Clock Pulse Low Width
tEE
END Pulse Width (Note
tEAE
EACK
tAA
EACK Pulse Width
J,
to END
t
tSA
~3VACK
tss
SVACK Pulse Width
J,
5)
ns
ns
240
120
ns
400
200
200
100
J,
Units
100
Delay
to SVREQ
8231A
50
300
Delay
100
ns·
150
ns
150
50
ns
ns
ns
NOTES:
1. Typical values are for TA = 25D C, nominal supply voltages processing parameters.
2. READY is pulled low for both command and data operations.
3. Minimum values shown assume no previously entered command is being executed for the data access. If a previously
entered command is being executed, READY low pulse width is the time to complete execution plus the time shown. Status
may be read at any time without exceeding the time shown.
4. READY low pulse width is less than 50 ns when writing into the data port or the control port as long as the duty. cycle
requirement (tWI) is observed and no previous command is being executed. tWI may be safely violated as long as the
extendedtRRW that results is observed. If a previously entered command is being executed, READY low pulse width is the
time to complete execution plus the time shown. These timings refer specifically to the 8231A.
5. END low pulse width is specified for EACK tied to VSS. Otherwise tEAE applies.
6-12
inter
8231A
WAVEFORMS
READ OPERATION
CLOCK
REAOY
DATA
BUS
231305-14
WRITE OPERATION
231305-15
INTERRUPT OPERATION
,lEE"
1
IEAED~f'
_______________
-IAA-
__- - - - - - - - - - -
EACK
SVREQ
-
ISA~~~
/
_ _ _- - J
_
_
_
SVACK
4-,
_
ISS~,
Y
231305-16
6-13
8253/8253-5
PROGRAMMABLE INTERVAL TIMER
Binary or BCD
• Count
Single + 5V Supply
• Available in EXPRESS
• - Standard Temperature Range
Compatible 8253-5
• MCS-85™
3 Independent 16-Bit Counters
• DC to 2.6 MHz
• Programmable Counter Modes
•
- Extended Temperature Range
The Intel® 8253 is a programmable counter/timer device designed for use as an Intel microcomputer peripheral. It uses NMOS technology with a single + 5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a count rate of up to 2.6 MHz. All modes of
operation are software programmable.
CLK 0
D7·Do~
DATA
BUS
BUFFER
CDUNTER
=0
GATE 0
DUT 0
RD
WR
Ao
CLK 1
READ!
WRITE
LOGIC
COUNTER
=1
D7
Vee
06
D.
WR
AD
CS
03
A,
05
GATE l '
OUT 1
A,
CS
O2
Ao
0,
CLK 2
Do
CLK 0
OUTO
CLK 2
CONTROL
WORD
REGISTER
GATE 0
COUNTER
=2
GATE 2
OUT 2
GND
OUT 2
GATE 2
CLK 1
GATE 1
OUT 1
231306-2
Figure 2. Pin Configuration
INTERNAL BUS /
231306-1
Figure 1. Block Diagram
6-14
November 1986
Order Number: 231306-001
inter
8253/8253-5
FUNCTIONAL DESCRIPTION
RD (Read)
General
A "low" on this input informs the 8253 that the CPU
is inputting data in the form of a counters value.
The 8253 is programmable interval timer/counter
specifically designed for use with the Intel™ Microcomputer systems. Its function is that of a general
purpose, multi-timing element that can be treated as
an array of I/O ports in the system software.
WR (Write)
A "low" on this input informs the 8253 that the CPU
is outputting data in the form of mode information or
loading counters.
The 8253 solves one of the most common problems
in any microcomputer system,. the generation of accurate time delays under software control. Instead of
setting up timing loops in systems software, the programmer configures the 8253 to match his requirements, initializes one of. the counters of the 8253
with the desired quantity, then upon command the
8253 will count out the delay and interrupt the CPU
when it has completed its tasks. It is easy to see that
the software overhead is minimal and that multiple
delays can easily be maintained by assignment of
priority levels.
AO,A1
These inputs are normally connected to the address
bus. Their function is to select one of the three counters to be operated on and to address the control
word register for mode selection.
CS (Chip Select)
A "low" on this input enables the 8253. No reading
or writing will occur. unless the device is selected.
The CS input has no effect upon the actual operation of the counters.
Other counter/timer functions that are non-delay in
nature but also common to most microcomputers
can be implemented with the 8253.
• Programmable Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller .
Data Bus Buffer
The 3-state, bi-directional, 8-bit buffer is used to interface the 8253 to the system data bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput CPU instructions. The Data Bus
Buffer has three basic functions.
cs----~
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and in turn generates control signals for
overall device operation. It is enabled or disabled by
CS so that no operation can occur to change the
function unless the device has been selected by the
system logic.
231306-3
Figure 3. Block Diagram Showing Data Bus
Buffer and Read/Write Logic Functions
6-15
inter
CS
0
8253/8253-5
0
0
0
0
0
RD
1
1
1
1
0
0
WR
0
0
0
0
1
1
0
0
1
0
0
0
X
1
1
1
X
1
A1
0
0
1
1
0
0
1
1
X
X
Ao
.0
1
0
1
0
1
0
1
X
X
Load Counter No.. O
Load Counter No.1
Load Counter No.2
Write Mode Word
Read Counter No. 0
Read Counter No. 1
Read Counter No.2
No-Operation 3-State
Disable 3-State
No-Operation 3-State
systems software as an array of peripheral 1/0
ports; three are counters and the fourth is a control
register for MODE programming.
Basically, the select inputs AO, A1 connect to the
AO, A 1 address bus signals of the CPU. The CS can
be derived directly from the address bus using a linear select method. Or it· can be connected to the
output of a decoder, such as an Intel 8205 for larger
systems.
Control Word Register
The Control Word Register is selected when AO, A 1
are 11. It then accepts information from the data bus
buffer and stores it in a register. The information
stored in this register controls the operation MODE
of each counter, selection of binary or BCD counting
and the loading of each count register.
The Control Word Register can only be written into;
no read operation of its contents is available.
Counter #0, Counter #1, Counter #2,
These three functional blocks are identical in operation so only a single counter will be described. Each
Counter consists of a single, 16-bit, pre-settable,
DOWN counter. The counter can operate in either
binary or BCD and its input, gate and output are configured by the selection of MODES. stored in the
Control Word Register.
INTERNAL BUS
231306-4
Figure 4. Block Diagram Showing Control Word
Register and Counter Functions
The counters' are fully independent and each can
have separate MODE configuration and counting operation, binary or BCD. Also, there are special features in the control word that handle the loading of
the count value so that software overhead can be
minimized for these functions.
The reading of the contents of each counter is available to the programmer with simple READ operations for event counting applications and special
commands and logic are included in the 8253 so
. that the contents of each counter can be read "on
the fly" without having to inhibit the clock input.
8253 SYSTEM INTERFACE
The 8253 is a component of the Intel™ Microcomputer systems and interfaces in the same manner as
all other peripherals of the family. It is treated by the
.231306-5
Figure 5. 8253 System Interface
6-16
8253/8253·5
OPERATIONAL DESCRIPTION
RL-READ/LOAD:
RL 1 RLO
General
The complete functional definition of the 8253 is
programmed by the systems software. A set of control words must be sent out by the CPU to initialize
each counter of the 8253 with the desired MODE
and quantity information. Prior to initialization, the
MODE, count, and output of all counters is undefined. These control words program the MODE,
Loading sequence and selection of binary or BCD
counting.
a
a
Counter Latching operation (see
READ/WRITE Procedure Section).
1
a
Read/Load most significant byte only.
a
1
Read/Load least significant byte only.
1
1
Read/Load least significant byte first,
then most significant byte.
M-MODE:
Once programmed, the 8253 is ready to perform
whatever timing tasks it is assigned to accomplish.
M2
M1
MO
a
a
a
Mode a
a
a
1
Mode 1
X
1
a
Mode 2
The actual counting operation of each counter is
completely independent and additional logic is provided on-chip so that the usual problems associated
with efficient monitoring and management of external, asynchronous events or rates to the microcomputer system have been eliminated.
X
1
1
Mode 3
1
a
a
Mode 4
1
a
1
Mode 5
Programming the 8253
All of the MODES for each counter are programmed
by the systems software by simple I/O operations.
BCD:
a
Binary Counter 16-Bits
Each counter of the 8253 is individually programmed
by writing a control word into the Control Word Register. (Aa, A1 = 11)
1
Binary Coded Decimal (BCD) Counter
(4 Decades)
Counter Loading
Control Word Format
07
Os
05
04
03
02
01
Do
I SC1 I sca I RL 1 I RLa I M2 I M1 I Ma I BCD I
The count register is not loaded until the count value
is written (one or two bytes, depending on the mode
selected by the RL bits), followed by a rising edge
and a falling edge of the clock. Any read of the counter prior to that falling clock edge may yield invalid
data.
Definition Of Control
MODE DEFINITION
SC-SELECT COUNTER:
SC1
SCO
a
a
Select Counter a
a
1
Select Counter 1
1
a
Select Counter 2
1
1
Illegal
MODE 0: Interrupt on Terminal Count. The output
will be initially low after the mode set operation. After
the count is loaded into the selected count register,
the output will remain low and the counter will count.
When terminal count is reached, the output will go
high and remain high until the selected count register is reloaded with the mode or a new count is loaded. The counter continues to decrement after terminal count has been reached.
Rewriting a counter register during counting results
in the following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
6-17
8253/8253-5
MODE 1: Programmable One-Shot. The output will
go low on the count following the rising edge of the
gate input.
In Modes 2 and 3, if a ClK source other than the
system clock is used, GATE should be pulsed immediately following WR of a new count value.
The output will go high on the terminal count. If a
new count value is loaded while the output is low it
will not affect the duration of the one-shot pulse until
the succeeding trigger. The current count can be
read at any time without affecting the one-shot
pulse.
MODE 4: Software Triggered Strobe. After the
mode is set, the output will be high. When the count
is loaded, the counter will begin counting. On terminal count, the output will go low for one input clock
period, then will go high again.
If the count register is reloaded during counting, the
new count will be loaded on the next ClK pulse. The
count will be inhibited while the GATE input is low.
The one-shot is retriggerable, hence the output will
remain low for the full count after any rising edge of
the gate input.
MODE 5: Hardware Triggered Strobe. The counter
will start counting after the rising edge of the trigger
input and will go low for one clock period when the
terminal count is reached. The counter is retriggerable. The output will not go low until the full count
after the rising edge of any trigger.
MODE 2: Rate Generator. Divide by N counter. The
output will be low for one period of the input clock.
The period from one output pulse to the next equals
the number of input counts in the count register. If
the count register is reloaded between output pulses
the present period will not be affected, but the subsequent period will reflect the new value.
Signal
Status
Modes
The gate input, when low, will force the output high.
When the gate input goes high, the counter will start
from the initial count. Thus, the gate input can be
used to synchronize the counter.
0
1
When this mode is set, the output will remain high
until after the count register is loaded. The output
then can also be synchronized by software.
Low
Or Going
Low
Disables
counting
-
Rising
High
-
Enables
counting
1) Initiates
-
counting
2) Resets output
after next
clock
MODE 3: Square Wave Rate Generator. Similar to
MODE 2 except that the output will remain high until
one half the count has been completed (or even
numbers) and go low for the other half of the count.
This is accomplished by decrementing the counter
by two on the falling edge of each clock pulse. When
the counter reaches terminal count, the state of the
output is changed and the counter is reloaded with
.the full count and the whole process is repeated.
If the count is odd and the output is high, the first
clock pulse (after the count is loaded) decrements
the count by 1. Subsequent clock pulses decrement
the clock by 2. After timeout, the output goes low
and the full count is reloaded. The first clock pulse
(following the reload) decrements the counter by 3.
Subsequent clock pulses decrement the count by 2
until timeout. Then the whole process is repeated. In
this way, if the count is odd, the output will be high
for {N + 1)/2 counts and low for (N - 1)/2 counts.
2
1) Disables
1) Reloads
counting
counter
2) Sets output 2) Initiates
immediately
counting
high
Enables
counting
3
1) Disables
1) Reloads
counting
counter
2) Sets output 2) Initiates
counting
immediately
high
Enables
. counting
4
Disables
counting
5
-
Initiates
counting
Enables
counting
-
Figure 6. Gate Pin Operations Summary
6-18
8253/8253-5
MODE 0: INTERRUPT ON TERMINAL COUNT
MODE 3: SQUARE WAVE GENERATOR
CLOCK
i
I
WI\""~
,
,
4
OUTPUT (INTERRUPTI
3
I
2
1
a
I
I-+-n--:
(n=4)
,
,,
I
WRm~
,
,
GATE-----..:,;L-.I....-:-;- - 5
4
3
2
1
a
~
OUTPUT (INTERRUPT)
1m'" 5)
'-v--J
'--v---'
A
B
231306-6
MODE 1: PROGRAMMABLE ONE-SHOT
LOADn~r-------------
GATE
o
-.r
-4
TRIGGER
----~~--~~~~~
OUTPUT
-----,1.~~~-I---------
OUTPUT
231306-10
In = 41
MODE 5: HARDWARE TRIGGERED STROBE
TRIGGER~
CLOCK
4
OUTPUT
---,i.....::.....:......::.....::.....:...~.J-----
GATE
---.J
4
231306-7
OUTPUT In
=
41
3
2
1
0
U ....- - - - -
MODE 2: RATE GENERATOR
CLOCK
GATE~
4343210
4
OUTPUT
OUTPUT (n == 3)
RESET
3
OUTPUT (n '" 4)
2
U'----231306-11
0131
------,L___. J - - - 231306-8
Figure 7. 8253 Timing Diagrams
6-19
inter
8253/8253·5
8253 READ/WRITE PROCEDURE
MODE Control Word
Counter n
Write Operations
The systems software must program each counter
of the 8253 with the mode and quantity desired. The
programmer must write out to the 8253 a MODE
control word and the programmed number of count
register bytes (1 or 2) prior to actually using the selected counter.
LSB
Counter Register byte
Counter n
MSB
Counter Register byte
Counter n
NOTE:
Format shown is a simple example of loading the 8253
and does not imply that it is the only format that can be
used.
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection: e.g., counter #0
does not have to be first or counter # 2 last. Each
counter's MODE control word register has a separate address so that its loading is completely sequence independent. (SCO, SC1).
Figure 8. Programming Format
The loading of the Count Register with the actual
count value, however, must be done in exactly the
sequence programmed in the MODE control word
(RLO, RL 1). This loading of the counter's count register is still sequence independent like the MODE
control word loading, but when a selected count register is to be loaded it must be loaded with the number of bytes programmed in the MODE control word
(RLO, RL 1). The one or two bytes to be loaded in the
count register do not have to follow the associated
MODE control word. They can be programmed at
any time following the MODE control word loading
as long as the correct number of bytes is loaded in
order.
All counters are down counters. Thus, the value
loaded into the count register will actually be decremented. Loading all zeros into a count register will
result in the maximum count (2 16 for Binary or 104
for BCD). In MODE 0 the new count will not restart
until the load has been completed. It will accept one
of two bytes depending on how the MODE control
words (RLO, RL 1) are programmed. Then proceed
with the restart operation.
A1
AD
No.1
MODE Control Word
Counter 0
1
1
No.2
MODE Control Word
Counter 1
1
1
No.3
MODE Control Word
Counter 2
1
1
No.4
LSB
Count Register Byte
Counter 1
0
1
No.5
MSB
Count Register Byte
Counter 1
0
1
No.6
LSB
Count Register Byte
Counter 2
1
0
NO.7
MSB
Count Register Byte
Counter 2
1
0
NO.8
LSB
Count Register Byte
Counter 0
0
0
No. g
MSB
Count Register Byte
Counter 0
0
0
NOTE:
The exclusive addresses of each counter's count register make the task of programming the 8253 a very simple matter, and maximum effective use of the device
will result if this feature is fully initilized.
Figure 9. Alternate Programming Formats
6-20
inter
8253/8253-5
Read Operations
Read Operation Chart
A1
0
0
1
1
In most counter applications it becomes necessary
to read the value of the count in progress and make
a computational decision based on this quantity.
Event counters are probably the most common application that uses this function. The 8253 contains
logic that will allow the programmer to easily read
the contents of any of the three counters without
disturbing the actual count in progress.
AO
0
,1
0
1
RD
0
0
0
0
Read Counter No. 0
Read Counter No.1
Read Counter No.2
Illegal
Reading While Counting
There are two methods that the programmer can
use to read the value of the counters. The first method involves the use of simple I/O read operations of
the selected counter. By controlling the AO, A1 inputs to the 8253 the programmer can select the
counter to be read (remember that no read operation of the mode register is allowed AO, A1-11). The
only requirement with this method is that in order to
assure a stable count reading the actual operation of
the selected counter must be inhibited either by controlling the Gate input or by external logic that
inhibits the clock input. The contents of the counter
selected will be available as follows:
In order for the programmer to read the contents of
any counter without effecting or disturbing the count- ing operation the 8253 has special internal logic that
can be accessed using simple WR commands to the
MODE register. Basically, when the programmer
wishes to read the contents of a selected counter
"on the fly" he loads the MODE register with a special code which latches the present coul'lt value into
a storage register so that its contents contain an
accurate, stable quantity. The programmer then issues a normal read command to the selected counter and the contents of the latched register is
available.
First I/O Read contains the least significant byte
(LSB).
'
MODE Register for Latching Count
Second I/O Read contains the most significant byte
(MSB).
AO, A1
I :~ I
Due to the internal logic of the 8253 it is absolutely
necessary to complete the entire reading procedure.
If two bytes are programmed to be read, then two
bytes must be read before any loading WR command can be sent to the same counter.
=
11
:;0 I ~51 ~41 ~31 ~21 ~1 I ~O I
SC1, SCO- specify counter to be latched.
05,04 - 00 designates counter latching- operation.
X
- don't care.
The same limitation applies to this mode of reading
the counter as tl:1e previous method. That is, it is
mandatory to complete the entire read operation as
programmed. This command has no effect on the
counter's mode .
ClK
3MHz
f2
• 1.5MHz
8085
ClK
8253·5
231306-12
'If an 8085 clock output is to drive an 8253·5 clock input, it must be reduced to 2 MHz or less.
Figure 10. MCS-85TM Clock Interface'
6-21
inter
8253/8253-5
ABSOLUTE MAXIMUM RATINGS·
AmbientTemperature Under Bias ... : .. o·eto 70·C
Storage Temperature .......... :: 65·C to + 150·C
Voltage On Any'Pin.
with Respect to Ground ....; ........ - 0.5V to 7V
Power Dissipation .................. , ..... 1 Watt
D.C. CHARACTERISTICS
Symbol
V,L
TA
= 0·Cto70·C, Vee = 5V ±10%'
Parameter
Input Low Voltage
V,H
Input High Voltage
VOL
Output Low Voltage
VOH
Output HighVoltage
I,L
• Notice: Stresses above those listed .under '~bso
lute Maximum Ratings" may cause permanent damage to the deVice; This is a stress Iating on/yand
functional operation 01 the device at these or any
other conditions above those indicatedin the operational sections of this specification is not implied· Exposure to absolute maximum rating conditions for
eXtended periods may affect deVice. reliability.
Min
Max
Unit
-0.5·
0.8
V
2.2
Test Conditions
Vee +:5V
V
0.45
V
Input Load Current
±10
/LA
Y,N = Vee to OV
IOFL
Output Float Leakage
±10
/LA
VOUT = Vee toO.45V
Icc
Vee Supply Current
140
mA
(Note 1)
V
2.4
(Note 2)
CAPACITANCE TA = 25·C, Vee = GND = ov
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
C'N
Input Capacitance
10
pF
fc = 1 MHz
CliO
110 Capacitance
20
pF
·Unmeasured pins returned to VSS
A.C. CliARACTERISTICS TA ~
O·C to 70·C, Vee
= 5.0V ± 10%, GND= OV'
Bus Parameters(3)
READ CYCLE
Symbol
Parameter
8253-5
8253
Min
Max
Min
Max
Unit
tAR
Address Stable before READ
50
30
ns
tRA
Address Hold Time for READ
5
5
ns
tRR
READ Pulse Width,
tRD
Data Delay from READ(4)
tDF
READ to Data Floating
tRY
Recovery Time between READ
and Any Other Control Signal
400
300
300
25
1
6-22
125
ns
200
25
1
100
ns
ns
/Ls
8253/8253-5
A.C. CHARACTERISTICS
(Continued)
WRITE CYCLE
Symbol
8253
Parameter
Min
Max
50
Address Stable before WRITE
tAW
8253-5
Min
Max
Unit
30
ns
tWA
Address Hold Time for WRITE
30
30
ns
tww
WRITE Pulse Width
400
300
ns
tDW
Data Set Up Time for WRITE
300
250
ns
tWD
Data Hold Time for WRITE
40
30
ns
tRV
Recovery Time between WRITE
and Any Other Control Signal
1
1
fLs
CLOCK AND GATE TIMING
Symbol
8253
Parameter
8253-5
Min
Max
Min
Max
dc
380
dc
Unit
tCLK
Clock Period
380
tpwH
High Pulse Width
230
230
ns
tpwL
low Pulse Width
150
150
ns
tGW
Gate Width High
150
150
ns
tGL
Gate Width low
100
100
ns
100
100
ns
50
50
ns
tGS
Gate Set Up Time to ClK
tGH
Gate Hold Time after ClK
tOD
Output Delay from ClK
toDG
Output Delay from Gate
t
t
t (4)
t (4)
ns
400
400
ns
300
300
ns
NOTES:
1. IOL = 2.2 mA.
2. IOH = -400 I'A
3. AC timings measured at VOH 2.2, VOL = O.B.
4. CL = 150 pF.
'For Extended Temperature EXPRESS, use MB253 electrical parameters.
A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4
>
2.2V
TEST POINTS
0.45
0.8
A.C. TESTING LOAD CIRCUIT
<
2.2V
DEVICE
UNDER
TEST
0.8
231306-13
A.C. Testing: Inputs are driven at 2.4V lor a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.2V for a
Logic "1" and O.BV lor a Logic "0".
.
,231306-14
CL Includes Jig Capacitance
6-23
8253/8253·5 .
WAVEFORMS
WRITE TIMING
READ TIMING
Ao-l. CS_ _'1=_ _ _ _ _ _ _ _ _l--f''-_ __
DATA BUS
231306-16
231306-15
CLOCK AND GATE TIMING
231306-17
8254
PROGRAMMABLE INTERVAL TIMER
•
•
•
•
•
•
•
Compatible with All Intel. and Most
Other Microprocessors
Handles Inputs from DC to 10 MHz
- 5 MHz 8254-5
- 8 MHz 8254
-10 MHz 8254-2
• Status Read-Back Command
Six Programmable Counter Modes
Three Independent 16-Bit Counters
Binary or BCD Counting
Single
+ 5V Supply
Available in EXPRESS
- Standard Temperature Range
The Intel® 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, each capable of handling clock inputs
up to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.
The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.
231164-1
Figure 1.8254 Block Diagram
6-25
August 1987
Order Number: 231164-004
8254
Table 1. Pin Description
,
Symbol
Pin
No.
Type
Name and Function
D7- DO
1-8
I/O
DATA: Bi·directional three state data bus lines, connected to system
data bus.
ClKO
9
I
CLOCK 0: Clock input of Counter O.
OUTO
10
0
OUTPUT 0: Output of Counter O.
GATE 0
11
I
GATE O:.Gate input of Counter O.
GND
12
Vee
WR
24
23,
I
RD
22
I
READ CONTROL: This input is low during CPU read operations.
CS
21
I
CHIP SELECT: A Iowan this input enables the 8254 to respond to
RD and WR signals. RD and WR are ignored otherwise.
20-19
I
ADDRESS: Used to select one of the three Counters or the Control
Word Register for read or write operations. Normally connected to
the system address bus.
Al, Ao
GROUND: Power supply connection.
POWER: + 5V power supply connection.
WRITE CONTROL: This input is low during CPU write operations.
A1
0
0
1
1
Ao
0
1
0
1
Selects
Counter 0
Counter 1
Counter 2
Control Word Register
ClK2
18
I
CLOCK 2: Clock input of Counter 2.
OUT2
17
0
GATE 2
16
I
OUT 2: Output of Counter 2.
GATE 2: Gate input of Counter 2.
ClK 1
15
I
CLOCK 1: Clock input of Counter 1.
GATE 1
14
I
GATE 1: Gate input of Counter 1.
OUT 1
13
0
OUT 1: Output of Counter 1.
FUNCTIONAL DESCRIPTION
Some of the other counter/timer functions common
to microcomputers which can be implemented with
the 8254 are:
General
• Real time clock
The 8254 is a programmable interval timer/counter
designed for use with Intel microcomputer systems.
It is a general purpose, multi·timing element that can
be treated as an array of I/O ports in the system
software.
• Event-counter
The 8254 solves one of the most common problems
in any microcomputer system, the generation of accurate time delays under software control. Instead of
setting up timing loops in software, the programmer
configures the 8254 to match his requirements and
programs one of the counters for the desired delay.
After the desired delay, the 8254 will interrupt the
CPU. Software overhead is minimal and variable
length delays can easily be accommodated.
• Complex waveform generator
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex motor controller
Block Diagram
DATA BUS BUFFER
This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus (see Figure 3).
6-26
inter
8254
eLK 0
GATE 0
OUT 0
iil5
eLK 1
WR
GATE 1
Ao
OUT 1
A1
eLK 2
GATE 2
OUT 2
231164-3
Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions
READ/WRITE LOGIC
COUNTER 0, COUNTER 1, COUNTER 2
The Read/Write logic accepts inputs from the system bus and generates control signals for the other
functional blocks of the 8254. A1 and Ao select one
of the three counters or the Control Word Register
to be read from/written into. A "low" on the RD input tells the 8254 that the CPU is reading one of the
counters. A "low" on the WR input tells the 8254
that the CPU is writing either a Control Word or an
initial count. Both RD and WR are qualified by CS;
RD and WR are ignored unless the 8254 has been
selected by holding CS low.
These three functional blocks are identical in operation, so only a single Counter will be described. The
internal block diagram of a single counter is shown
in Figure 5.
The Counters are fully independent. Each Counter
may operate in a different Mode.
The Control Word Register is shown in the figure; it
is not part of the Counter itself, but its contents determine how the Counter operates.
The status register, shown in Figure 5, when
latched, contains the current contents of the Control
Word Register and status of the output and null
count flag. (See detailed explanation of the ReadBack command.)
CONTROL WORD REGISTER
The Control Word Register (see Figure 4) is selected
by the Read/Write logic when A1,Ao = 11. If the
CPU then does a write operation to the 8254, the
data is stored in the Control Word Register and is
interpreted as a Control Word used to define the
operation of the Counters.
The actual counter is labelled CE (for "Counting Element"). It is a 16-bit presettable synchronous down
counter.
The Control Word Register can only be written to;
status information is available with the Read-Back
Command.
OlM and Oll are two 8-bit latches. Ol stands for
"Output latch"; the subscripts M and l stand for
"Most significant byte" and "least significant byte"
6-27
inter
8254
ClK 0
GATE 0
aUTO
WI!
READI
WRITE
lOGIC
Ao
GATE 1
OUT 1
A,
l!S
ClK 2
GATE 2
OUT2
231164-4
Fi.9ure 4. Blo~k Diagram Showing Control Word. Register and Counter Functions
CONTROL
LOGIC
l+-t--+-----(
'---r-,----,-,..
GATEn
ClK n
OUT n
231164-5
Figure 5. Internal Block Diagram of aCo.unter
6·28
inter
8254
other peripherals of the family. It is treated by the
system's software as an array of peripheral 1/0
ports; three are counters and the fourth is a control
register for MODE programming.
respectively. Both are normally referred to .as one
unit and called just OL. These latches normally "follow" the CE, but if a suitable Counter latch Command is sent to the 8254, the latches "latch" the
present count until read by the CPU and then return
to "following" the CEo One latch at a time is enabled
by the counter's Control logic to drive the internal
bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself
cannot be read; whenever you read the count, it is
the Ol that is being read.
Basically, the select inputs AO.A1 connect to the Ao,
A1 address bus signals of the CPU. The CS can be
derived directly from the address bus using a linear
select method. Or it can be connected to the output
of a decoder, such as an Intel 8205 for larger systems.
Similarly, there are two 8-bit registers called CRM
and CRL (for "Count Register"). Both are normally
referred to as one unit and called just CR. When a
new count is written to the Counter, the count is
stored in the CR and later transferred to the CEo The
Control logic allows one register at a time to be
loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are
cleared when the Counter is programmed. In this
way, if the Counter has been programmed for one
byte counts (either most significant byte only or least
significant by1e only) the other byte will be zero.
Note that the CE cannot be written into; whenever a
count is written, it is written into the CR.
After power-up, the state of the 8254 is undefined.
The Mode, count value, and output of all Counters
are undefined.
The Control logic is also shown in the diagram.
ClK n, GATE n, and OUT n are all connected to the
outside world through the Control logic.
Programming the 8254
OPERATIONAL DESCRIPTION
General
How each Counter operates is determined when it is
programmed. Each Counter must be programmed
before it can be used. Unused counters need not be
programmed.
Counters are programmed by writing a Control Word
and then an initial count.
8254 SYSTEM INTERFACE
The Control Words are written into the Control Word
Register, which is selected when A1,Ao = 11. The
Control Word itself specifies which Counter is being
programmed.
The 8254 is a component of the Intel Microcomputer
Systems and interfaces in the same manner as all
ADDRESS BUS (16)
CONTROL BUS
231164-6
Figure 6. 8254 System Interface
6-29
8254
Control Word Format
Al ,Ao
=
11
CS
=
0
RD
=
1 WR
07
=
0
Os
05
04
02
03
01
00
I SC1 I sca I RW1 I Rwa I M21 M1 I MO I BCD I
SC-SeJect Counter
SC1
SCO
a
0
M-Mode
M2
M1
MO
0
a
a
Mode a
Select Counter a
a
1
Select Counter 1 .
a
a
1
Mode 1
1
a
Select Counter 2
X
1
0
Mode 2
1
1
Read-Back Command
(see Read Operations)
X
1
1
Mode 3
1
a
0
Mode 4
0
1
ModeS
1
RW-Read/Write
RW1 RWO
0
a
BCO
Counter Latch Command (see Read
Operations)
0
1
Read/Write least significant byte only
1
a
Read/Write most significant byte only
1
1
Read/Write least significant byte first,
then most significant byte
,
a
Binary Counter 16-bits
1
Binary Coded Decimal (BCD) Counter
(4 Decades)
NOTE:
Don't care bits (Xl should be 0 to insure compatibility with future Intel products.
Figure 7.. ControJ Word Format
By contrast, initial counts are written into the Counters, not the Control Word Register. The Al,Ao inputs are used to select the Counter to be written
into. The format of the initial count is determined by
the Control Word used.
Since the Control Word Register and the three
Counters have separate addresses (selected by the
Al,Ao inputs), and each Control Word specifies the
Counter it applies to (SCO,SC1 bits), no special instruction sequence is required. Any programming
sequence that follows the conventions in Figure 7 is
acceptable.
Write Operations
A new initial count may be written to a Counter at
any time without affecting the Counter's programmed Mode in any way. Counting will be affected
as described in the Mode definitions. The new count
must follow the programmed count format.
The programming procedure for the 8254 is very
flexible. Only two conventions need to be remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format
specified in the Control Word (least significant
byte only, most significant byte only, or least significant byte and then most significant byte).
If a Counter is programmed to read/write two-byte
counts, the following precaution applies: A program
must not transfer control between writing the first
and second byte to another routine which also writes
into that same Counter. Otherwise, the Counter will
be loaded with an incorrect count.
6-30
inter
8254
Control Word-Counter 0
lSB of count-Counter 0
MSB of count-Counter 0
Control Word-Counter 1
lSB of count-Counter 1
MSB of count-Counter 1
Control Word-Counter 2
LSB of count-Counter 2
MSB of count-Counter 2
Control Word-Counter 0
Control Word-Counter 1
Control Word-Counter 2
LSB of count-Counter 2
LSB of count-Counter 1
LSB of count-Counter 0
MSB of count-Counter 0
MSB of count-Counter 1
MSB of count-Counter 2
A1
1
0
0
1
0
0
Ao
1
0
0
1
1
1
0
0
Control Word-Counter 2
Control Word-Counter 1
Control Word-Counter 0
lSB of count-Counter 2
MSB of count-Counter 2
LSB of count-Counter 1
MSB of count-Counter 1
lSB of count-Counter 0
MSB of count-Counter 0
A1
1
1
1
1
0
0
0
0
Ao
1
1
1
0
1
0
0
1
0
Control Word-Counter 1
Control Word-Counter 0
LSB of count-Counter 1
Control Word-Counter 2
LSB of count-Counter 0
MSB of count-Counter 1
LSB of count-Counter 2
MSB of count-Counter 0
MSB of count-Counter 2
A1
1
1
1
Ao
1
1
1
0
0
1
1
0
0
0
0
0
0
A1
1
1
0
1
0
0
1
0
Ao
1
1
1
0
1
0
0
0
NOTE:
In all four examples, all Counters are programmed to read/write two-byte counts. These are only four of many possible
programming sequences.
Figure 8_ A Few Possible Programming Sequences
Read Operations
A1,Ao = 11; CS = 0; RD = 1; WR = 0
It is often desirable to read the value of a Counter
without disturbing the count in progress. This is easily done in the 8254.
D7
1
There are three possible methods for reading the
counters: a simple read operation, the Counter
Latch Command, and the Read-Back Command.
Each is explained below. The first method is to perform a simple read operation. To read the Counter,
which is selected with the A 1, AO inputs, the ClK
input of the selected Counter must be inhibited by
using either the GATE input or external logic. Otherwise, the count may be in the process of changing
when it is read, giving an undefined result.
SC1
D6
1
SCO
Ds
1
0
D4
1
0
D3
1
X
D2
1
D1
X'I X
Do
1
X
I
SC1,SCO-specify counter to be latched
SC1 SCO
0
0
1
1
0
1
0
1
Counter
0
1
2
Read-Back Command
05,04-00 designates Counter Latch Command
COUNTER LATCH COMMAND
X-don't care
The second method uses the "Counter Latch Command''. Like a Control Word, this command is written
to the Control Word' Register, which is selected
when A1,Ao = 11. Also like a Control Word, the
sca, SC1 bits select one of the three Counters, but
two other bits, 05 and 04, distinguish this command
from a Control Word.
NOTE:
Don't care bits (Xl should be 0 to insure compatibility
with future Intel products.
Figure 9. Counter Latching Command Format
6-31
inter
8254
The selected Counter's output latch (Ol) latches the
count at the time the Counter latch Command is
received. This count is held in the latch until it is read
by the CPU (or until the Counter is reprogrammed).
The count is then unlatched automatically and the
Ol returns to "following" the counting element (CE).
This allows reading the contents of the Counters
"on the fly" without affecting counting in progress.
Multiple Counter latch Commands may be used to
latch more than one Counter. Each latched Counter's Ol holds its count until it is read. Counter latch
Commands do not affect the programmed Mode of
the Counter in any way.
AO, A1 = 11
07 06
05
RD = 1 WR = 0
CS = 0
04
03
02
01
11 11 ICOUNTlsTATuslcNT2lcNT1IcNTOI
05:
04:
03:
02:
01:
00:
Do
0
I
0 = Latch count of selected counter(s)
0 = Latch status of selected counters(s)
1 = Select Counter 2
1 = Select Counter 1
1 = Select Counter 0
Reserved for future expansion; Must be 0
Figure 10. Read-Back Command Format
The read-back command may be used to latch multiple counter output latches (Ol) by setting the
COUNT bit 05 = 0 and selecting the desired counter(s). This single command is functionally equivalent to several counter latch commands, one for
each counter latched. Each counter's latched count
is held until it is read (or the counter is reprogrammed). The counter is automatically unlatched
when read, but other counters remain latched until
they are read. If multiple count read-back commands
are issued to the same counter without reading the
count all but the first are ignored; i.e., the count
which' will be read is the count at the time the first
read-back command was issued.
If a Counter is latched and then, some time later,
latched again before the count is read, the second
Counter latch Command is ignored. The count read
will be the count at the time the first Counter latch
Command was issued.
With either method, the count must be read according to the programmed format; specifically, if the
Counter is programmed for two byte counts, two
bytes must be read. The two bytes do not have to be
read one right after the other; read or write or p~o
gramming operations of other Counters may be Inserted between them.
Another feature of the 8254 is that reads and writes
of the same Counter may be interleaved; for example, if the Counter is programmed for two byte
counts, the following sequence is valid.
1) Read least significant byte.
2) Write new least significant byte.
3) Read most significant byte.
4) Write new most significant byte.
The read-back command may also be used to latch
status information of selected counter(s) by setting
STATUS bit 04 = O. Status must be latched to be
read; status of a counter is accessed by a read from
that counter.
If a Counter is programmed to read/write two-byte.
counts, the following precaution applies: A program
must not transfer control between reading the first
and second byte to another routine which also reads
from that same Counter. Otherwise, an incorrect
count will be read.
The counter status format is shown in Figure 11. Bits
05 through DO contain the counter's programmed
Mode exactly as written in the. last Mode Control
Word. OUTPUT bit 07 contains the current state of
the OUT pin. This allows the user to monitor the
counter's output via software, possibly eliminating
some hardware from a system.
READ-BACK COMMAND
The third. method uses the Read-Back Command.
This command allows the user to check the count
value, programmed Mode, and current states of the
OUT pin and Null Count flag of the selected counter(s).
1 = OUT Pin is 1
OUT Pin is 0
1 = Null Count
06
o = Count available for reading .
Os-Do Counter programmed mode (see Figure
o=
7)
The command is written into the Control Word Register and has the format shown in Figure 10. The
command applies to the counters selected by setting their corresponding bits 03, 02, 01 = 1.
Figure 11. Status Byte
6-32
intJ
8254
COUNT and STATUS bits 05,04 = O. This is functionally the same as issuing two separate read-back
commands at once, and the above discussions apply here also. Specifically, if multiple count and/or
status read-back commands are issued to the same
counter(s) without any intervening reads, all but the
first are ignored. This is illustrated in Figure 13.
NULL COUNT bit 06 indicates when the last count
written to the counter register (CR) has been loaded
into the counting element (CE). The exact time this
happens depends on the Mode of the counter and is
described in the Mode Definitions, but until the count
is loaded into the counting element (CE), it can't be
read from the counter. If the count is latched or read
before this time, the count value will not reflect the
new count just written. The operation of Null Count
is shown in Figure 12.
If both count and status of a counter are latched, the
first read operation of that counter will return latched
status, regardless of which was latched first. The
next one or two reads (depending on whether the
counter is programmed for one or two type counts)
return latched count. Subsequent reads return unlatched count.
This Action
Causes
A. Write to the control word register;(1) Null Count = 1
B. Write to the count register (CR);(2) Null Count = 1
C. New Count is loaded into
Null Count = 0
CE(CR-CE);
NOTE:
1. Only the counter specified by· the control word will
have its Null Count set to 1. Null count bits of other
counters are unaffected.
.
2. If the counter is programmed for two-byte counts
(least significant byte then most significant byte) Null
Count goes to 1 when the second byte is written.
Figure 12. Null Count Operation
If multiple status latch operations of the counter(s)
are performed without reading the status, all but the
first are ignored; i.e., the status that will be read is
the status of the counter at the time the first status
read-back command was issued.
Both count and status of the selected counter(s)
may be latched simultaneously by setting both
Command
07 06 05 04 03 02 01
1
00
CS
RO
WR
A1
Ao
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write Control Word
0
0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Operation (3-State)
1
X
X
X
X No-Operation (3-State)
0
1
1
X
X
No-Operation (3-State)
Figure 14. Read/Write Operations Summary
·Oescription
Result
1
0
0
0
0
1
0
Read back count and status of
Counter 0
Count and status latched
for Counter 0
0
0
Read back status of Counter 1
Status latched for Counter 1
1
1
1
0
0
1
1
1
1
0
1
1
0
0
Read back status of Counters 2, 1 Status latched for Counter
2, but not Counter 1
1
1
0
1
1
0
0
0
Read back count of Counter 2
Count latched for Counter 2
1
1
0
0
0
1
0
0
Read back count and status of
Counter 1
Count latched for Counter 1,
but not status
1
1
1
0
0
0
1
0
Read back status of Counter 1
Command ignored, status
already latched for Counter 1
Figure 13. Read-Back Command Example
6-33
intJ
8254
OUT will then go high and remain high until the ClK
pulse after the next trigger.
Mode Definitions
The following are defined for use in describing the
operation of the 8254.
ClK Pulse:
a rising edge, then a falling edge, in
that order, of a Counter's ClK input.
Trigger:
a rising edge of a Counter's GATE
input.
Counter loading: the transfer of a count from the CR
to the CE (refer to the. "Functional
Description")
After writing the Control Word and initial count, the
Counter is armed. A trigger results in loading the
. Counter and setting OUT low on the next ClK pulse,
thus starting the one-shot pulse. An initial count of N
will result in a one-shot pulse N ClK cycles in duration. The one-shot is retriggerable, hence OUT will
remain low for N ClK pulses after any trigger. The
one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on
OUT.
If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the
Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
MODE 0: INTERRUPT ON TERMINAL COUNT
Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially low, and will
remain low until the Counter reaches zero. OUT then
goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Counter.
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is
typically used to generate a Real Time Clock interrupt. OUT will initially be high: When the initial count
has decremented to 1, OUT goes low for one ClK
pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.
Mode 2 is periodic; the same sequence is repeated
indefinitely. For an initial count of N, the sequence
repeats every N ClK cycles.
.
GATE = 1 enables counting; GATE = 0 disables
counting. GATE has no effect on OUT.
After the Control Word and initial count are written to
a Counter, the initial count will be loaded on the next
ClK pulse. This ClK pulse does not decrement the
count, so for an initial count of N, OUT does not go
high until N + 1 ClK pulses after the initial count is
written.
GATE == 1 enables counting; GATE = 0 disables
counting; If GATE goes low during an output pulse,
OUT is set high immediately. A trigger reloads the
Counter with the initial count on the next ClK pulse;
OUT goes low N ClK pulses after the trigger. Thus
the GATE input can be used to synchronize the
Counter.
If a new count is written to the Counter, it will be
loaded on the next ClK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:
.
1) Writing the first byte disables counting. OUT is set
low immediately (no clock pulse required)
2) Writing the second byte allows the new count to
be loaded on the next ClK pulse.
After writing a Control Word and initial count, the
Counter will be loaded on the next ClK pulse. OUT
goes lo~ N ClK Pulses after the initial count is written. This allows the Counter to be synchronized by
software also.
This allows the counting sequence to be synchronized by software. Again, OUT does not go high until
N +1 ClK pulses after the new count of N is written.
Writing a new count while.counting does not affect
the current counting sequence. If a trigger is received after writing a new count but before the end
of the current period, the Counter will be loaded with
the new count on the next elK pulse and counting
will continue from the new count. Otherwise, the
new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
If an initial count is written while GATE = 0, it will
still be loaded on the next ClK pulse. When GATE
goes high, OUT will go high NClK pulses later; no
ClK pulse is needed to load the Counter as this has
already been done.
MODE 1: HARDWARE RETRIGGERABLE
ONE-SHOT
MODE 3: SQUARE WAVE MODE
OUT will be initially high. OUT will go low on the ClK
pulse following a trigger to begin the one-shot pulse,
and will remain low until the Counter reaches zero.
Mode 3 is typically used for Baud rate generation.
Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the
6-34
8254
FF I ofF
I FF
FE
a
a
I
FF
FF
FF
FF
231164-7
The following conventions apply to all mode timing diagrams:
1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for "Control Word"; CW = 10 means a control word of 10 HEX is written to the counter.
4. LSB stands for "Least Significant Byte" of count.
5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the
most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read.
N stands for an undefined count.
Vertical lines show transitions between count values.
Figure 15. Mode 0
6-35
8254
CW=.12
WR
LSB=3
~----------------~--
ClK
OUT
:=J
I NI NI N I NI NI ~ I ~
CW=12
o
1
LSB=3
~ ~~---------------
ClK
GATE
OUT
-------;n --
--1n------~:---
----Jr
.:..=J
L - -_ _ _
I NI NI NI,N I.N I ~ I ~ I ~
CW=12
lSB=2
o
3
o
2
~
IgI
LSB=4
r---~----------
ClK
GATE
OUT
--
-----;n --------i n------
=.J
ININ
\L...'_ _....J
INININUI~lgl~~I~~t~
o
3
231164-8
Figure 16. Mode 1
After writing a Contrpl Word and initial count, the
Counter will be loaded on the next ClK pulse. This
allows the Counter to be synchronized by software
also.
initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial
count of N results in a square wave with a period of
N ClK cycles.
Writing a new count while counting does not affect
the current counting sequence. If a trigger is received after writing a new count but before the end
of the current half-cycle of the square wave, the
Counter will be loaded with the new count on the
next ClK pulse and counting will continue from the
GATE = 1 enables counting; GATE
0 disables
counting. If GATE goes low while OUT is low, OUT is
set high immediately; no ClK pulse is required. A
trigger reloads the Counter with the initial count on
the next ClK pulse. Thus the GATE input can be
used to synchronize the Counter.
6-36
intJ
8254
CW= 14
WR
lSB=3
~--------------------~-----
ClK
GATE
OUT
I
N
I
N
I
CW=14
WR
N
I
N
0
3
I
0
0
1
2
0
3
0
2
0
1
0
3
lSB=3
LJLJ
ClK
LJ
GATE
OUT
=.:J
I
N
I
N
I
N
I
N
~
I
I
~
I
~
I
~
I ~. I ~ I
ClK
GATE
OUT~
I
N
I
N
U
I
N
I
N
I
~
o
3
I~ I~ I ~
o
3
231164-9
NOTE:
A GATE transition should not occur one clock prior to terminal count.
Figure 17. Mode 2
Odd counts: OUT is initially high. The initial count
minus one (an even number) is loaded on one ClK
pulse and then is decremented by two on succeeding ClK pulses. One ClK pulse after the count expires, OUT goes low and the Counter is reloaded
with the initial count minus one. Succeeding ClK
pulses decrement the count by two. When the count
expires, OUT goes high again and the Counter is
reloaded with the initial count minus one. The above
process is repeated indefinitely. So for odd counts,
OUT will be high for (N + 1)/2 counts and low for
(N - 1)/2 counts.
new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
Mode 3 is implemented as follows:
Even counts: OUT is initially high. The initial count is
loaded on one ClKpulse and then is decremented
by two on succeeding ClK pulses. When the count
expires OUT changes value and the Counter is reloaded with the initial count. The above process is
repeated indefinitely.
6-37
8254
CW.18
WR
LSB.4
~~. ----~--------------------
ClK
G~E-------------------------------------------
OUT
o
o
4
CW.16
I
4
LSB=5
WR~r--------~----~---------
ClK
GATE
OUT~
I NI NI NI NI
CW=18
I
\
0
4
0
2
I ~I
r
\
I: I I ~ I •
0
2
I
0
lSB=4
WliLn--1
ClK
GATE
OUT
:.=J
L-.l
LJ
ININININI:I~I:I~I
0
2
NOTE:
A GATE transition should not occur one clock prior to terminal count.
Figure 18. Mode 3
6-38
r
\
0
4
I~ I
0
2
I
231164-10
8254
initial count of N, OUT does not strobe low until N
1 ClK pulses after the initial count is written.
MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count expires, OUT will go low for one ClK pulse and then
go high again. The counting sequence is "triggered"
by writing the initial count.
If a new count is written during counting, it will be
loaded on the next ClK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:
1) Writing the first byte has no effect on counting.
GATE = 1 enables counting; GATE = 0 disables
counting. GATE has no effect on OUT.
2) Writing the second byte allows the new count to
be loaded on the next ClK pulse.
After writing a Control Word and initial count, the
Counter will be loaded on the next ClK pulse. This
ClK pulse does not decrement the count, so for an
CW=18
lSB=3~
This allows the sequence to be "retriggered" by
software. OUT strobes low N + 1 ClK pulses after
the new count of N is written.
_________________________
WR'LJL..J
ClK
GATE
u
OUT~
o
I NI N I NI NI
CW = 18
2
o1
I I I I I
0
0
FF
FF
FF
FE
FF
FD
LSB = 3~______-:-________________
WRLJU
ClK
GATE
OUT
:=J
I I NI NI NI 3 I ~ I ~ I
N
0
WI!
ClK
GATE
OUT
+
~
ININININlgl~I~1
231164-11
Figure 19. Mode 4
6-39
inter
8254
A trigger results in the Counter being loaded with the
initial count on the next ClK pulse. The counting
sequence is retriggerable. OUT will not strobe low
for N+ 1 ClK pulses after any trigger. GATE has
no effect on OUT.
MODE 5: HARDWARE TRIGGERED STROBE
(RETRIGGERABLE)
OUT will initially be high. Counting is triggered· by a
rising· edge of GATE. When the initial count has expired, OUT will go low for one ClK pulse and then
go high again.
If a new count is written during counting, the current
counting sequence· will not be affected. If a trigger
occurs after the new count is written but before the
current count expires, the Counter will be loaded
with the new count on the next ClK pulse and
counting will continue from there.
After writing the Control Word and initial count, the
counter will not be loaded until the ClK pulse after a
trigger. This ClKpulse .does not decrement the
count, so fo~ an initial count of N, OUT does not
strobe low until N + 1 ClK pulses after a trigger.
CW=lA
LSB=3
~~--~~----------ClK
GATE
-------1 rr--------lrc=
u
OUT~
o1
INININININI
CW=lA
WR
I o.I I
0
FF
FF.
0
3
lSB=3
~~---------------------
ClK
GATE
-------,...-1~----,...-....;-----
OUT~
ININININININI~I
CW=lA
lSB=3
r------.
CLK
GATE
OUT
-
-------vr----------"\n-----
=-.J
INI NI NI
U
N
I NI
~
I
~
I
~
I
Figure 20. Mode 5
6-40
g I == I =~ I
231164-12
intJ
8254
Signal
Status
Modes
Low
Or Going
Low
0
Operation CC)mmon to All Modes
Rising
High
Disables
Counting
--
Enables
Counting
1
--
1) Initiates
Counting
2) Resets Output
after Next
Clock
--
2
1) Disables
Counting
2) Sets Output
Immediately
High
3
1) Disables
Counting
2) Sets Output
Immediately
High
PROGRAMMING
When a Control Word is written to a Counter, all
Control logic is immediately reset and OUT goes to
a known initial state; no ClK pulses are required for
this.
GATE
Initiates
Counting
Enables
Counting
Initiates
Counting
Enables
Counting
4
Disables
Counting
--
Enables
Counting
5
--
Initiates
Counting
--
The GATE input is always sampled on the rising
edge of ClK. In Modes 0,2,3, and 4 the GATE input
is level sensitive, and the logic level is sampled on
the rising edge of ClK. In Modes 1, 2, 3, and 5 the
GATE input is rising-edge sensitive. In these Modes,
a rising edge of GATE (trigger) sets an edge-sensitive flip-flop in the Counter. This flip-flop is then sampled on the next rising edge of ClK; the flip-flop is
reset immediately after it is sampled. In this way, a
trigger will be detected no matter when it occurs-a
high logic level does not have to be maintained until
the next rising edge of ClK. Note that in Modes 2
and 3, the GATE input is both edge- and level-sensitive. In Modes 2 and 3, if a elK source other than
the system clock is used, GATE should be pulsed
immediately following WR of a new count value.
Figure 21. Gate Pin Operations Summary
Mode
0
1
2
3
4
5
Min
Count
Max
Count
1
1
2
2
1
1
0
0
0
0
0
0
COUNTER
New counts are loaded and Counters are decremented on the falling edge of ClK.
The largest possible initial count is 0; this is equivalent to 216 for binary counting and 104 for BCD
counting.
The Counter does not stop when it reaches zero. In
Modes 0, 1, 4, and 5 the Counter "wraps around" to
the highest count, either FFFF hex for binary counting or 9999 for BCD counting, and continues counting. Modes 2 and 3 are periodic; the Counter reloads
itself with the initial count and continues counting
from there.
NOTE:
o is equivalent to 216 for binary counting and 104 for
BCD counting.
.
Figure 22. Minimum and Maximum Initial Counts
6-41
8254
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUMRATINGS*
Ambient Temperature Under Bias ...... O°C.to 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation ........................... 1W
D.C. CHARACTERISTICS
Symbol
TA = 0°Ct070°C, Vee = 5V ±10%
Min
Max
Units
Input Low Voltage
-0:5
0.8
V
VIH
Input High Voltage
2.0
Vee +0.5V
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
IlL
Input Load Current
±10
/LA
IOFL
Output Float Leakage
±10
/LA
lee
Vee Supply Current
170
mA
VIL
Parameter
2.4
Test Conditions
= 2.0mA
IOH = - 400 /LA
IOL
V
= Vee to OV
VOUT = Vee to 0.45V
VIN
= 1 MHz
CIN
Input Capacitance
10
pF
fc
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to VSS(4)
A.C. CHARACTERISTICS
TA
= O°C to 70°C, Vee = 5V ± 10%, GND = OV
Bus Parameters(1)
READ CYCLE
Symbol
8254-5
Parameter
Min
tAR
Address Stable Before RD J,
tSR
CS Stable Before RD
tRA
Address Hold Time After RD
tRR
RD Pulse Width
tRD
Data Delay from RD
tAD
Data Delay from Address
i
J,
i
tDF
RD
Command Recovery Time
to Data Floating
8254-2
8254
Min
Max
Min
Unit
Max
45
45
30
ns
0
0
0
ns
0
0
0
ns
150
150
95
ns
J,
tRv
Max
5
200
NOTE:
1. Ae timings measured at VOH = 2.0V, VOL = O.BV.
6-42
120
120
85
ns
220
220
185
ns
65
ns
90
5
200
90
5
165
ns
8254
A.C. CHARACTERISTICS
TA
=
O'C to 70'C, vcc
=
5V ± 10%, GND
=
OV (Continued)
WRITE CYCLE
Symbol
Min
tAW
Address Stable Before WR
tsw
CS Stable Before WR
t
t
twA
Address Hold Time After WR
tww
WR Pulse Width
tow
Data Setup Time Before WR
two
Data Hold Time After WR
tRY
Command Recovery Time
t
i
Max
8254-2
8254
8254·5
Parameter
Max
Min
Min
Unit
Max
0
0
0
ns
0
0
0
ns
0
0
0
ns
150
150
95
ns
120
120
95
ns
0
0
0
ns
200
200
165
ns
i
CLOCK AND GATE
Symbol
tClK
8254-5
Parameter
8254-2
8254
Min
Max
125
DC
Min
Max
100
DC
Max
Clock Period
200
DC
60(3)
30(3)
ns
60(3)
50(3)
ns
tpWH
High Pulse Width
60(3)
tpWl
low Pulse Width
60(3)
tR
Clock Rise Time
25
25
25
tF
Clock Fall Time
25
25
25
tGW
Gate Width High
tGl
Gate Width low
tGS
Gate Setup Time to ClK
tGH
too
tOOG
twc
Unit
Min
i
Gate Setup Time After ClK
t
Output Delay from Gate t
ClK Delay for loading t
i
Gate Delay for Sampling
two
OUT Delay from Mode Write
tCl
ClK Set Up for Count latch
ns
ns
50
50
50
50
50
ns
50
50
40
ns
50(2)
50(2)
150
Output Delay from ClK
tWG
ns
-5
0
50
-5
45
50(2)
120
55
260
-40
ns
150
120
0
50
55
0
50
-5
260
-40,
45
-40
ns
100
ns
100
ns
55
ns
40
ns
240
ns
40
ns
NOTES:
2. In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 8254-2) of
the rising clock edge may not be detected.
3. low-going glitches that violate tpWH, tpWL may cause errors requiring counter reprogramming.
4. Sampled, not 100% tested. TA = 25'C.
5. If ClK present at TWC min then Count equals N + 2 ClK pulses, TWC max equals Count N + 1 ClK pulse. TWC min to
TWC max, count will be either N + lorN + 2 ClK pulses.
6. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWG
max Counter will be triggered.
7. If ClK present when writing a Counter latch or ReadBack Command, at TCl min ClK will be reflected in count value
latched, at TCl max ClK will not be reflected in the count value latched.
6-43
inter
8254
WAVEFORMS
WRITE
1....~---IAW----il.... 1
cs
DATA BUS
VALID
tDW~ . - t WO - "
231164-13
READ
Ao·t
I-..----IAR----I--I
CS
DATABUS---
231164-14
6-44
intJ
8254
WAVEFORMS (Continued)
RECOVERY
231164-15
CLOCK AND GATE
231164-16
• Last byte of count being written.
A.C. TESTING INPUT, OUTPUT WAVEFORM
"=X
2.0
0.45
0.8
>
TEST POINTS
<
2.0
0.8
A.C. TESTING LOAD CIRCUIT
x=
DEVICE
UNDER
TEST
231164-17
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0." Timing measurements are made at 2.0V for a
Logic "1" and 0.6V for a Logic "0".
231164-16
CL = 150 pF
CL Includes Jig Capacitance
6-45
82C54
CHMOS PROGRAMMABLE INTERVAL TIMER
independent 16-bit counters
• Three
Low Power CHMOS
• -Icc = 10 rnA 8 MHz Count
Compatible with all Intel and most
• other
microprocessors
High Speed, "Zero Wait State"
• Operation
with 8 MHz 8086/88 and
@
frequency
80186/188
Completely TTL Compatible
• Six
Programmable Counter Modes
• Binary
or BCD counting
• Status Read
Back Command
• Available in 24-Pin
DIP and 28-Pin PLCC
•
•
in EXPRESS
• -Available
Standard Temperature Range
Handles Inputs from DC to 8 MHz
- 10 MHz for 82C54-2
- Extended Temperature Range
The Intel 82C54 is a high-performance, CHMOS version of the industry standard 8254 counter/timer which is
designed to solve the timing control problems common in microcomputer system design. It provides three
independent 16-bit counters, each capable of handling clock inputs up to 10 MHz. All modes are software
programmable. The 82C54 is pin compatible with the HMOS 8254, and is a superset of the 8253.
Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator,
programmable one-shot, and in many other applications.
.
The 82C54 is fabricated on Intel's advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent HMOS product. The 82C54 is available in 24-pin DIP
and 28-pin plastic leaded chip carrier (PLCC) packages.
Os
06
07
Ne
Yee
WR ii6
21282726
ClK 0
07·00
82C54
elK 1
GATE 1
OUTO GATED GND NC OUT1 GATE1 eLK1
OUT 1
231244-3
PLASTIC LEADED CHIP CARRIER
cs-_ _.-..J
Vee
iVA
jffi
Cs
OUT2
AI
Ao
D,
ClK2
Do
231244-1
Figure 1. 82C54 Block Diagram
231244-2
Diagrams are for pin reference only..
Package sizes are not to scale.
Figure 2. 82C54 Pinout
6-46
October 1987
Order Number: 231244-004
inter
82C54
Table 1. Pin Description
Pin Number
Symbol
Type
Function
DIP
PlCC
1·8
2-9
ClKO
9
10
I
OUTO
10
12
0
Output 0: Output of Counter O.
GATE 0
11
13
I
Gate 0: Gate input of Counter o.
Dy-Do
I/O
Data: Bidirectional tri·state data bus lines,
connected to system data bus.
Clock 0: Clock input of Counter O.
GND
12
14
OUT1
13
16
0
Out 1: Output of Counter 1.
Ground: Power supply connection.
Gate 1: Gate input of Counter 1.
GATE 1
14
17
I
ClK 1
15
18
I
Clock 1: Clock input of Counter 1.
GATE 2
16
19
I
Gate 2: Gate input of Counter 2.
OUT2
17
20
0
Out 2: Output of Counter 2.
ClK2
18
21
I
Clock 2: Clock input of Counter 2.
A1, Ao
20-19
23-22
I
Address: Used to select one of the three Counters
or the Control Word Register for read or write
operations. Normally connected to the system
address bus.
CS
21
24
I
RD
22
26
I
WR
23
27
I
Vee
NC
24
28
1, 11, 15,25
Selects
A1
Ao
Counter 0
0
0
1
Counter 1
0
Counter 2
1
0
Control Word Register
1
1
Chip Select: A Iowan this input enables the 82C54
to respond to RD and WR signals. RD and WR are
ignored otherwise.
Read Control: This input is low during CPU read
operations.
Write Control: This input is. low during CPU write
operations.
Power: + 5V power supply connection.
No Connect
sired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and·
variable length delays can easily be accommodated.
FUNCTIONAL DESCRIPTION
General
Some of the other counter/timer functions common
to microcomputers which can be implemented with
the 82C54 are:
The 82C54 is a programmable interval timer/counter
designed for use with Intel microcomputer systems.
It is a general purpose, multi-timing element that can
be treated as an array of I/O ports in the system
software.
•
•
•
•
•
•
•
•
The 82C54 solves one of the most common problems in any microcomputer system, the generation
of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 82C54 to match his requirements and programs one of the counters for the de6-47
Real time clock
Even counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
inter
82C54
Block Diagram
CONTROL WORD REGISTER
The Control Word Register (see Figure 4) is selected
by the Read/Write Logic when Al, Ao = 11. If the
CPU then does a write operation to the 82C54, the
data is stored in the Control Word Register and is
interpreted as a Control Word used to define the
operation of the Counters.
DATA BUS BUFFER
This 3-state, bi-directional, 8-bit buffer is used to interface the 82C54 to the system bus (see Figure 3).
The Control Word Register can only be written to;
status information is available with the Read-Back
Command.
elK 0
GATE 0
0,·°0
OUT 0
elK 1
GATE 1
OUT 1
Cu( 2
GATE 2
231244-4
our 2
Figure 3. Block Diagram Showing Data Bus
Buffer and Read/Write Logic Functions
231244-5
READ/WRITE LOGIC
Figure 4. Block Diagram Showing Control Word
Register and Counter Functions
The Read/Write Logic accepts inputs from the system bus and generates control signals. for the other
functional blocks of the 82C54.Aland Ao select
one of the three counters or the Control Word Re~
ter to be read from/written into. A "low" on the RD
input tells the 82C54 that the CPU is reading one of
the counters. A "low" on the WR input tells the
82C54 that the CPU is writing either a Control Word
or an initial count. Both RD and WR are qualified by
CS; RD and WR are ignored unless the 82C54 has
.
been selected by holding CS low.
COUNTER 0, COUNTER 1, COUNTER 2
These three functional blocks are'identical in operation, so only a single Counter will be described. The
internal block diagram of a single counter is shown
in Figure 5.
The Counters are fully independent. Each Counter
may operate in a different Mode.
The Control Word Register is shown in the figure; it
is not part of the Counter itself, but its contents determine how the Counter operates.
6-48
intJ
82C54
stored in the CR and later transferred to the CEo The
Control logic allows one register at a time to be
loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRl are
cleared when the Counter is programmed. In this
way, if the Counter has been programmed for one
byte counts (either most significant byte only or least
significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a
count is written, it is written into the CR.
The Control logic is also shown in the diagram. ClK
n, GATE n, and OUT n are all connected to the outside world through the Control logic.
82C54 SYSTEM INTERFACE
231244-6
Figure 5. Internal Block Diagram of a Counter
The status register, shown in the Figure, when
latched, contains the current contents of the Control
Word Register and status of the output and null
count flag. (See detailed explanation of the ReadBack command.)
The actual counter is labelled CE (for "Counting Element"). It is a 16-bit presettable synchronous down"
counter.
The B2C54 is treated by the systems software as an
array of peripheral 110 ports; three are counters and
the fourth is a control register for MODE programming.
Basically, the select inputs Ao, A1 connect to the Ao,
A1 address bus signals of the CPU. The CS can be
derived directly from the address bus using a linear
select method. Or it can be connected to the output
of a decoder, such as an Intel B205 for larger systems.
OlM and Oll are two B-bit latches. Ol stands for
"Output latch"; the subscripts M and l stand for
"Most significant byte" and "least significant byte"
respectively. Both are normally referred to as one
unit and called just OL. These latches normally "follow" the CE, but if a suitable Counter latch Command is sent to the B2C54, the latches "latch" the
present count until read by the CPU and then return
to "following" the CEo One latch at a time is enabled
by the counter's Control logic to drive the internal
bus. This is how the 16·bit Counter communicates
over the a-bit internal bus. Note that the CE itself
cannot be read; whenever you read the count, it is
the Ol that is being read.
Similarly, there are two B-bit registers called CRM
and CRl (for "Count Register"). Both are normally
" referred to as one unit and called just CR. When a
new count is written to the Counter, the count is
231244-7
Figure 6. 82C54 System Interface
82C54
OPERATIONAL DESCRIPTION
Programming the 82C54
General
Counters are programmed by writing a Control Word
and then an initial count. The control word format is
shown in Figure 7.
After power-up, the state of the 82C54 is undefined.
The Mode, count value, and output of all Counters
are undefined.
All Control Words are written into the Control Word
Register, which is selected when A 1 , Ao = 11. The
Control Word itself specifies which Counter is being
programmed.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed
before it can be used. Unused counters need not be
programmed.
By contrast, initial counts are written into the Counters, not the Control Word Register. The Al, Ao inputs are used to select the Counter· to be written
into. The format of the initial count is determined by
the Control Word used.
Control Word Format
Al,Ao=11
CS = 0
RD = 1 WR =0
D7
D6
Ds
D4
D2
D3
D1
Do
ISC1 ISCO I RW1 I RWO I M21 M1 I MO I BCD I
SC ...,. Select Counter:
SC1
SCO
M-MODE:
M2
MO
0
0
Select Counter 0
0
0
0
Mode 0
0
1
Select Counter 1
0
0
1
Mode 1
1
0
Select Counter 2
X
1
0
Mode 2
1
Read-Back Command
(See Read Operations)
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
Mode 5
1
RW - Read/Write:
RW1 RWO
0
M1
0
BCD:
Counter Latch Command (see Read
Operations)
0
1
Read/Write least significant byte only.
1
0
Read/Write most significant byte only.
1
1
Head/Write least significant byte first,
then most significant byte.
0
Binary Counter 16-bits
1
Binary Coded Decimal (BCD) Counter
(4 Decades)
NOTE: Don't care bits (X) should be 0 to insure
compatibility with future Intel products.
Figure 7. Control Word Format
6-50
intJ
82C54
struction sequence is required. Any programming
sequence that follows the conventions above is acceptable.
Write Operations
The programming procedure for the 82C54 is very
flexible. Only two conventions need to be remembered:
1) For each Counter, the Control Word must be
written before the initial count is written.
2) The initial count must follow the count format
specified in the Control Word (least significant
byte only, most significant byte only, or least significant byte and then most significant byte).
A new initial count may be written to a Counter at
any time without affecting the Counter's programmed Mode in any way. Counting will be affected
as described in the Mode definitions. The new count
must follow the programmed count format.
If a Counter is programmed to read/write two-byte
counts, the following precaution applies: A program
must not transfer control between writing the first
and second byte to another routine which also writes
into that same Counter. Otherwise, the Counter. will
be loaded with an incorrect count.
Since the Control Word Register and the three
Counters have separate addresses (selected by the.
A1, Ao inputs), and each Control Word specifies the
Counter it applies to (SCO, SC1 bits), no special in-
Control Word LSB of countMSB of countControl Word LSB of count·MSB of count . Control Word LSB of count MSB of count -
Counter 0
Counter 0
Counter 0
Counter 1
Counter 1
Counter 1
Counter 2
Counter 2
Counter 2
Control Word Counter Word Control Word LSB of count LSB of count LSB of count MSB of countMSB of count MSB of count -
Counter 0
Counter 1
Counter 2
Counter 2
Counter 1
Counter 0
Counter 0
Counter 1
Counter 2
A1
Ao
1
0
0
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
A1
Ao
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
0
Control Word Control Word Control Word LSB of count MSB of countLSB of count MSB of countLSB of countMSB of count-
Counter 2
Counter 1
Counter 0
Counter 2
Counter 2
Counter 1
Counter 1
Counter 0
Counter 0
Control Word Control Word LSB of count Control Word LSB of count MSB of countLSB of count MSB of countMSB of count-
Counter 1
Counter 0
Counter 1
Counter 2
Counter 0
Counter 1
Counter 2
Counter 0
Counter 2
A1
Ao
1
1
1
1
1
0
O.
0
0
1
1
1
0
0
1
1
0
0
A1
Ao
1
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
0
0
NOTE:
In all four examples, all counters are programmed to read/write twO-byte counts.
These are only four of many possible programming sequences.
Figure 8. A Few Possible Programming Sequences
Latch Command, and the Read-Back Command.
Each is explained below. The first method is to perform a simple read operation ..To read the Counter,
which is selected with the A1, AO inputs, the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic. Otherwise, the count may be in the process of changing
when it is read, giving an undefined result.
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress. This is easily done in the 82C54.
There are three possible methods for reading the
counters: a simple read operation, the Counter
6-51
82C54
gramming operations of other Counters may be inserted between them.
COUNTER LATCH COMMAND
The second method uses the "Counter Latch Command". Like a Control Word, this command is written
to the Control Word Register, which is selected
when A1, Ao = 11. Also like a Control Word, the
SCO, SC1 bits select one of the three Counters, but
two other bits, 05 and 04, distinguish this command
from a Control Word.
Another feature of the 82C54 is that reads and
writes of the same Counter may be interleaved; for
example, if the Counter is programmed for two byte
counts, the following seq·uence is valid.
1.
2.
3.
4.
Al, Ao= 11; CS=O; RD= 1; WR=O
07.
06
05
04
03
02
01
I SCl I SCO I 0 I 0 I· X I X I X
DO
X
SCO
Counter
0
0
1
1
0
1
0
1
0
1
2
Read-Sack Command
least significant byte.
new least significant byte.
most significant byte.
new most significant byte.
If a Counter is programmed to read/write two-byte
counts, the following precaution applies; A program
must not transfer control between reading the first
and second byte to another routine which also reads
from that same Counter. Otherwise, an incorrect
count will be read.
I
SC1, SCO - specify counter to be latched
SCl
Read
Write
Read
Write
READ-BACK COMMAND
The third method uses the Read-Sack command.
This command allows the user to check the count
value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected counter(s).
05,04 - 00 designates Counter Latch Command
X - don't care
The command is written into the Control Word Register and has the format shown in Figure 10. The
command applies to the counters selected by setting their corresponding bits 03,02,01 = 1.
NOTE:
Don't care bits (X) should be 0 to insure compatibility
with future Intel products.
Figure 9_ Counter Latching Command Format
The selected Counter's output latch (OL) latches the
count at the time the Counter Latch Command is
received. This count is held in the latch until it is read
by the CPU (or until the Counter is reprogrammed).
The count is then unlatched automatically and the
OL returns to "following" the counting element (CE).
This allows reading the contents of the Counters
"on the fly" without affecting counting in progress.
Multiple Counter Latch Commands may be used to
latch more than one Counter. Each latched Counter's OL holds its count until it is read. Counter Latch
Commands do not affect the programmed Mode of
the Counter in any way.
AO, A 1
= 11 CS
07 06
Os
= 0
04
RO
= 1
03
WR = 0
02
01
00
\1 \1 \COUNT\STATUS\CNT2\CNT1\CNTO\ 0
05:
04:
03:
02:
01:
Do:
I
0 = Latch count of selected counter(s).
0 = Latch status of selected counter(s)
1 =c Select counter 2
1 = Select counter 1
1 = Select counter 0
Reserved for future expansion; must be 0
Figure 10. Read-Back Command Format
The read-back command may be used to latch mUltiple counter output latches (OL) by setting the
COUNT bit 05 = 0 and selecting the desired counter(s). This single command is functionally equivalent to several counter latch commands, one for
each counter latched. Each counter's latched count
is held until it is read (or the counter is reprogrammed). That counter is automatically unlatched
when read, but other counters remain latched until
they are read. If multiple count read-back commands
are issued to the same counter without reading the
If a Counter is latched and then, some time later,
latched again before the count is read, the second
Counter Latch Command is ignored. The count read
will be the count at the time the first Counter Latch
Command was issued.
With either method, the count must be read according to the programmed format; specifically, if the
Counter is programmed for two byte counts, two
bytes must be read. The two bytes do not have to be
read one right after the other; read or write or pro6-52
82C54
count, all but the first are ignored; i.e., the. count
which will be read is the count at the time the first
read-back command was issued.
THIS ACTION:
A. Write to the control
word register: [1]
B. Write to the count
register (CR); [2]
C. New count is loaded
into CE (CR ~ CE);
The read-back command may also be used to latch
status information of selected counter(s) by setting
STATUS bit D4 = O. Status must be latched to be
read; status ofa counter is accessed by a read from
that counter.
CAUSES:
Null count= 1
Null count= 1
Null count=O
[I] Only the counter specified by the control word will
have its null count set to 1. Null count bits of other
counters are unaffected.
[2] If the counter is programmed for two-byte counts
(least significant byte then most significant byte) null
count goes to 1 when the second byte is written.
The counter status format is shown in Figure 11. Bits
D5 through DO contain the counter's programmed
Mode exactly as written in the last Mode Control
Word. OUTPUT bit D7 contains the current state of
the OUT pin. This allows the user to monitor the
counter's output via software, possibly eliminating
some hardware from a system.
Figure 12. Null Count Operation
If multiple status latch operations of the counter(s)
are performed without reading the status, all but the
first are ignored; i.e., the status that will be read is
the status of the counter at the time the first status
read-back command was issued.
07 1 =
o=
06 1 =
o=
Os-Do
Out Pin is 1
Out Pin is 0
Null count
Count available for reading
Counter Programmed Mode (See Figure 7)
Both count and status of the selected counter(s)
may be latched simultaneously by setting both
COUNT and STATUS bits D5,D4=0. This is functionally the same as issuing two separate read-back
commands at once, and the above discussions apply here also. Specifically, if multiple countand/or
status read-back commands are issued to the same
counter(s) without any intervening reads, all but the
first are ignored. This is illustrated in Figure 13.
Figure 11. Status Byte
NULL COUNT bit D6 indicates when the last count
written to the counter register (CR) has been loaded
into the counting element (CE). The exact time this
happens depends on the Mode of the counter and is
described in the Mode Definitions, but until the count
is loaded into the counting element (CE), it can't be
read from the counter. If the count is latched or read
before this time, the count value will not reflect the
new count just written. The operation of Null Count
is shown in Figure 12.
If both count and status of a counter are latched, the
first read operation of that counter will return latched
status, regardless of which was latched first. The
next one or two reads (depending on whether the
counter is programmed for one or two type counts)
return latched count. Subsequent reads return unlatched count.
Command
07 06 05 04 03 02 01
Do
0
0
0
1
0
Read back count and status of
Counter 0
Count and status latched
for Counter 0
Status latched for Counter 1
0
Description
Results
1
1
1
1
1
0
0
1
0
0
Read back status of Counter 1
1
1
1
0
1
1
0
0
Read back status of Counters 2, 1 Status latched for Counter
2, but not Counter 1
1
1
0
1
1
0
0
0
Read back count of Counter 2
Count latched for Counter 2
1
1
0
0
0
1
0
0
Read back count and status of
Counter 1
Count latched for Counter 1,
but not status
1
1
1
0
0
0
1
0
Read back status of Counter 1
Command ignored, status
already latched for Counter 1
Figure 13. Read-Back Command Example
6-53
intJ
82C54
CS
RD
WR
At
Ao
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write into Counter 1
0
1
0
1
0
Write into Counter 2
0
1
0
1
1
Write Control Word
0
0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter t
0
0
1
1
0
Read from Counter 2
0
0
1
1
1
No-Operation (3-State)
1
X
X
1
1
X
X
X
X
No-Operation (3-State)
0
This allows the counting sequence to be synchronized by software. Again, OUT does not go high until N
+ 1 ClK pulses after the new count of N is written.
If an initial count is written while GATE = 0, it will
still be loaded on the next ClK .pulse. When GATE
goes high, OUT will go high N ClK pulses later; no
ClK pulse is needed to load the Counter as this has
already been done.
cw .. ,o
lSB=4
~~r-----------~-elK
No-Operation (3-State)
GATE ------------~-
Figure 14. Read/Write Operations Summary
OUT
::::I
.~
_ _ _ _ _ _ _ _ _ ____l
I I I I I : I ~ I : I ~ I ~ I ~~ I ~~ I
N
N
N
N
Mode Definitions
The following are defined for use in describing the
operation of the 82C54.
elK
ClK PULSE: a rising edge, then a falling edge, in
that order, of a Counter's ClK input.
TRIGGER: a rising edge of a Counter's GATE input.
COUNTER lOADING: the transfer of a count from
the CR to the CE (refer to
the "Functional Description")
GATE
OUT
MODE 0: INTERRUPT ON TERMINAL COUNT
-J,-
:::-:=JI..______________
elK
Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially low, and will
remain low until the Counter reaches zero. OUT then
goes high and remains high until a new count or a
new Mode 0 Control Word is written into the Counter.
-J,-
GATE - - - - - - - - - - - - - OUT
=-:JI..______________
I I I I I ~ I : I ~ I : I ~ I ~ I ~~ I
N
N
N
N
231244-8
If a new count is written to the Counter, it will be
loaded on the next ClK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:
NOTE:
The Following Conventions Apply To All Mode Timing
Diagrams:
1. Counters are programmed for binary (not aCD)
counting and for Reading/Writing least significant byte
(LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for "Control Word"; CW = 10 means a
control word of to, hex is written to the counter.
4. LSB stands for "Least Significant Byte" of count.
5. Numbers below diagrams are count values.
The lower number is the least significant byte.
The upper number is the most significant byte. Since
the counter is programmed to Read/Write LSB only,
the most significant byte cannot be read.
N stands for an undefined count.
Vertical lines show transitions between count values.
1) Writing the first byte disables counting. OUT is set
low immediately (no clock pulse required).
Figure 15. Mode 0
GATE = 1 enables counting; GATE = 0 disables
counting. GATE has no effect on OUT.
After the Control Word and initial count are written to
a Counter, the initial count will be loaded on the next
ClK pulse. This ClK pulse does not decrement the
count, so for an initial count of N, OUT does not go
high until N + 1 ClK pulses after the initial count is
written.
2) Writing the second byte allows the new count to
be loaded on the next ClK pulse.
6-54
82C54
MODE 1: HARDWARE RETRIGGERABLE
ONE-SHOT
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is
typicially used to generate a Real Time Clock interrupt. OUT will initially be high. When the initial count
has decremented to 1, OUT goes low for one ClK
pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.
Mode 2 is periodic; the same sequence is repeated
indefinitely. For an initial count of N, the sequence
repeats every N ClK cycles.
OUT will be initially high. OUT will go Iowan the ClK
pulse following a trigger to begin the one-shot pulse,
and will remain low until the Counter reaches zero.
OUT will then go high and remain high until the ClK
pulse after the next trigger.
After writing the Control Word and initial count, the
Counter is armed. A trigger results in loading the
Counter and setting OUT Iowan the next ClK pulse,
thus starting the one-shot pulse. An initial count of N
will result in a one-shot pulse N ClK cycles in duration. The one-shot is retriggerable, hence OUT will
remain low for N ClK pulses after any trigger. The
one-shot pulse can be repeated without rewriting the
same count into the counter. GATE has no effect on
OUT.
GATE = 1 enables counting; GATE = 0 disables
counting. If GATE goes low during an output pulse,
OUT is set high immediately. A trigger reloads the
Counter with the initial count on the next ClK pulse;
OUT goes low N ClK pulses after the trigger. Thus
the GATE input can be used to synchronize the
Counter.
After writing a Control Word and initial count, the
Counter will be loaded on the next ClK pulse. OUT
goes low N ClK Pulses after the initial count is written. This allows the Counter to be synchronized by
software also.
If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the Counter is retriggered. In that case, the
Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
CW;;12
CW=14
LSB=3
l$B=3
WlI~r-----------------
~ ~r-------------------
eLK
eLK
GATE
GATE ------;n--c-------~n:==
--------------------------
OUT
OUT
CW=14
L5B=3
WlI~~-------------
cw= 12
lSB
=3,--___________________
WlIl..JU
elK
eLK
GATE
GATE
-------In----ln---------OUT
OUT
r
=.J
==.i
Ll
ININININI~I~I:I:I~I:I:I
INININININI~I~I:I~I~I:I:I
eLK
GATE
eLK
GATE
-------;n--------;n==
OUT
--------------------------
~
u
ININININI~I:I:I:I:I~I~I
231244-10
OUT
I NI NI NI NI I ~ I : I : I ~~ I ~~ I ~ I ~ I
NOTE:
N
A GATE transition should not occur one clock prior to
terminal count.
231244-9
Figure 16. Mode 1
Figure 17. Mode 2
6-55
inter
82C54
OUT will be high for (N
(N -1 )/2 counts.
Writing a new count while counting does not affect
the current counting sequence. If a trigger is received after writing a new count but before the end
of the current period, the Counter will be loaded with
the new count on the next ClK pulse and counting
will continue from the new count. Otherwise, the
new count will be loaded at the end of the current
counting cycle. In mode 2, a COUNT of 1 is illegal.
CW=16
+ 1)/2 counts and low for
lse"'4r-..-_ _ _~...,.....~-~-.,___-
WliLJU
MODE 3: SQUARE WAVE MODE
1
Mode 3 is typically used for Baud rate generation.
Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence
above is repeated indefinitely. An initial count of N
results in a square wave with a period of N ClK
cycles.
~I
N1 N·I
CW",,6
N
1 :
I:
1 :.
I:
1 : ·1:
I:
1 : 1: 1 : 1
LSB=5r-..----'_ _ _ _ _ _ _'----_ _
Wl!L...JLJ
GATE -------------~-
IN 1 N1 N1
GATE = 1 enables counting; GATE = 0 disables
counting. If GATE goes low while OUT is low, OUT is
set high immediately; no ClK pulse is required. A
trigger reloads the Counter with the initial count on
the next ClK pulse. Thus the GATE input can be
used to synchronize the Counter.
N
1: 1 : 1 : 1 : 1 : 1 : 1 : 1 : 1 :
I:
1
CW .. 16
LS8=4r----_--------'----WI!~
GATE
OUT
After writing a Control Word and initial count, the
Counter will be loaded on the next ClK pulse. This
allows the Counter to be synchronized by software
also.
IN 1 N1 N1 N1 :
1 : 1 : 1 : 1 : 1 : 1 :
I: I:
1 :1
231244-11
NOTE:
A GATE transition should not occur one clock prior to
terminal count.
Writing a new count while counting does not affect
the current counting sequence. If a trigger is received after writing a new count but before the end
of the current half-cycle of the square wave, the
Counter will be loaded with the new count on the
next ClK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
Figure 18. Mode 3
MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count expires, OUT will go low for one ClK pulse and then
go high again. The counting sequence is "triggered"
by writing the initial count.
Mode 3 is implemented as follows:
Even counts: OUT is initially high. The initial count is
loaded on one ClK pulse and then is decremented
by two on succeeding ClK pulses. When the count
expires OUT changes value and the Counter is reloaded with the initial count. The above process is
repeated indefinitely,
GATE = 1 enables counting; GATE == 0 disables
counting. GATE has no effect on OUT.
After writing a Control Word and initial count, the
Counter will be loaded on the next ClK pulse. This
ClK pulse does not decrement the count, so for an
initial count of N, OUT does not strobe low until
N + 1 ClK pulses after the initial· count is written.
Odd counts: OUT is initially high. The initial count
minus one (an even number) is loaded on one ClK
pulse and then is decremented by two on succeeding ClK pulses. One ClK pulse after the count expires, OUT goes low and the Counter is reloaded
with the initial count minus one. Succeeding ClK
pulses decrement the count by two. When the count
expires, OUT goes high again and the· Counter is
reloaded with the initial count minus one. The above
process is repeated indefinitely. So for odd counts,
If a new count is written during counting, it will be
loaded on the next ClK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:
6-56
intJ
82C54
1) Writing the first byte has no effect on counting.
After writing the Control Word and initial count, the
counter will not be.loaded until the ClK pulse after a
trigger. This ClK pulse does not decrement the
count, so for an initial count of. N, OUT does not
strobe low until N + 1 ClK pulses after a trigger.
2) Writing the second byte allows the new count to
be loaded on the next ClK pulse.
This allows the sequence to be "retriggered" by
software. OUT strobes low N + 1 ClK pulses after
the new count of N is written.
CW:::1B
A trigger results in the Counter being loaded with the
initial count on the next ClK pulse. The counting
sequence is retriggerable. OUT will not strobe low
for N + 1 ClK pulses after any trigger. GATE has
no effect on OUT.
lSB",3
~~~---------------eLK
If a new count is written during counting, the current
counting sequence will not be affected. If a trigger
occurs after the new count is written but before the
current count expires, the Counter will be loaded
with the new count on the next ClK pulse and
counting will continue from there.
GATE
OUT
u
=-=-.1
I I I I I : I ~ I ~ I g I ~~ I ~~ I :~ I
N
N
CW .. 111
N
N
LSB=3i-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Wii~
CW=IA
WI>
LSB=3i-_ _ _ _ _ _ __
"1...Jl.--.1
eLK
GATE
--------------'
GATE
OUT~
-------l/r--------lfL:.=
OUT
1N 1 N 1
CW::1A
Wii
eLK
1
N
1 N 1 : 1 : 1 : 1 : 1 ~~ 1 :1
LSB"'3,.--_ _ _ _ _ _ _ _ __
"1...Jl.--.1
eLK
GATE , - - - - - - - - - , - - - - - - - - - - OUT
N
=:J
GATE
LJ
N
N
-------In=.l/l--- ------- --
OUT~
I I I I I ~ I ~ I ~ I ~ I ~ U I ~: I
N
- -
N
231244-12
Figure 19. Mode 4
MODE 5: HARDWARE TRIGGERED STROBE
(RETRIGGERABLE)
GATE
OUT will initially be high. Counting is triggered by a
rising edge of GATE. When the initial count has expired, OUT will go low for one ClK pulse and then
go high again.
OUT
--------m----------·\f-c== .
u
~
1N 1
N
1
N
1 N 1 N 1 : I : 1 : 1 : 1 ~~ 1 ~~ 1 ~ I. ~ 1
231244-13
Figure 20. Mode 5
6-57
inter
82C54
Signal
Status
Modes
Low
Or Going
Low
0
Disables
counting
3
-
Initiates
counting
Enables
counting
Initiates
counting
Enables
counting
-
Enables
counting
1) Disables
counting
2) Sets output
immediately
high
Disables
counting
5
-
Enables
counting
1) Initiates
counting
2) Resets output
after next
clock
1) Disables
counting
2) Sets output
immediately
high
4
High
Programming
-
-
1
2
Operation Common to All Modes
Rising
Initiates
counting
When a Control Word is written to a Counter, all
Control logic is immediately reset and OUT goes to
a known initial state; no ClK pulses are required for
this.
GATE
The GATE input is always sampled on the rising
edge of ClK. In Modes 0, 2, 3, and 4 the GATE input
is level sensitive, and the logic level is sampled on
the rising edge of ClK. In Modes 1, 2, 3, and 5 the
GATE input is rising-edge sensitive. In these Modes,
a rising edge of GATE (trigger) sets an edge-sensitive flip-flop in the Counter. This flip-flop is then sampled on the next rising edge of ClK; the flip-flop is
reset immediately after it is sampled. In this way, a
trigger will be detected no matter when it occurs-a
high logic level does not have to be maintained until
the next rising edge of ClK. Note that in Modes 2
and 3, the GATE input is both edge- and level-sensitive. In Modes 2 and 3, if a ClK source other than
the system clock is used, "GATE should be pulsed
immediately following WR of a new count value.
-
Figure 21. Gate Pin Operations Summary
MODE
0
COUNTER
MIN
MAX
COUNT COUNT
1
0
1
1
0
2
2
0
3
2
0
4
1
0
New counts are loaded and Counters are decremented on the falling edge of ClK.
The largest possible initial count is 0; this is equivalent to 2 16 for binary counting and 104 for BCD
counting.
The Counter does not stop when it reaches zero. In
Modes 0, 1, 4, and 5 the Counter "wraps around" to
the highest count, either FFFF hex for binary counting or 9999 for BCD counting, and continues counting. Modes 2 and 3 are periodic; the Counter reloads
itself with the initial count and continues counting
from there.
NOTE:
o is equivalent to
2 16 for binary counting and 104 for
BCD counting
Figure 22. Minimum and Maximum initial Counts
6-58
intJ
82C54
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias....... O°C to 70°C
Storage Temperature ............ -65° to + 150°C
Supply Voltage ......... ~ ......... - 0.5 to + 8.0V
Operating Voltage .................. + 4V to + 7V
Voltage on any Input .......... GND - 2V to + 6.5V
Voltage on any Output .. GND-0.5VtoVee + 0.5V
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS
(TA =O°C to 70°C, Vee=5V± 10%, GND= OV) (TA = -40°C to +85°C for Extended Temperature)·
Symbol
Min
Max
Units
Input low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Output low Voltage
Vee + 0.5
0.4
V
VOL
VOH
Output High Voltage
IlL
IOFL
Output Float leakage Current
lee
Vee Supply Current
20
IJ-A
mA
leess
Vee Supply Current-Standby
10
IJ-A
ClK Freq = DC
CS = HIGH.
AlllnputslData Bus HIGH
All Outputs Floating
leess1
Vee Supply Current-Standby
150
IJ-A
ClK Freq = DC
CS = HIGH. All Other Inputs,
1/0 Pins = low, Outputs Open
VIL
Parameter
3.0
Vee - 0.4
Input load Current
±2.0
±10
Test Conditions
V
IOL = 2.5 mA
V
V
IOH = -2.5 mA
IOH = -100 p.A
IJ-A
VIN=Vee toOV
VOUT=Vee to O.OV
8MHz 82C54
Clk Freq=
1OMHz 82C54-2
CIN
Input Capacitance
10
pF
fe = 1 MHz
CliO
1/0 Capacitance
20
pF
COUT
Output Capacitance
20
pF
Unmeasured pins
returned to GND(5)
A.C. CHARACTERISTICS
(TA = O°C to 70°C, Vee = 5V ± 10%, GND =OV) (TA = -40°C to
+ 85°C for Extended Temperature)
BUS PARAMETERS (Note 1)
READ CYCLE
Symbol
82C54-2
82C54
Parameter
Min
Max
Min
Units
Max
tAR
Address Stable Before RD!
ns
CS Stable Before RD !
45
0
30
tSR
0
ns
tRA
Address Hold Time After RD t
0
0
ns
tRR
RD Pulse Width
150
95
tRo
Data Delay from RD !
120
85
ns
tAD
Data Delay from Address
220
185
ns
tOF
RD
t
to Data Floating
Command Recovery Time
tRV
NOTE:
1. Ae timings measured at VOH = 2.0V, VOL = O.BV.
5
200
6-59
90
5
165
ns
65
ns
ns
inter
82C54
A.C. .CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
Min
tAW
82C54-2
82C54
Parameter
. Address Stable Before WR .J..
tsw
CS Stable Before WR .J..
tWA
·tww
Address Hold Time After WR
WR Pulse Width
tow
Data Setup Time Before WR
two
Data Hold Time After WR
tRY
Command Recovery Time
t
Units
Max
Min
0
0
ns
0
0
ns
.0
0
ns
150
95
ns
120
95
ns
0
0
ns
200
165
ns
t
t
Max
CLOCK AND GATE
Symbol
82C54-2 -
82C54
Parameter
Min
Max
Min
Max
DC
100
30(3)
DC
Units
ns
tClK
Clock Period
tPWH
High Pulse Width·
125
60(3)
tPWl
low Pulse Width
60(3)
TR
Clock Rise Time
25
25
ns
tF
C.iock Fall Time
25
25
ns
tGW
,Gate Width High
50
50
ns
tGl
Gate Width low
50
50
ns
tGS
Gate Setup Time to ClK
50
50(2)
40
50(2)
ns
. tGH
Too
tOOG
twc
t
Gate Hold Time After ClK
t
Output Delay from ClK .J..
Output Delay from Gate .J..
Gate Delay for Sampling(4)
two
OUT Delay from Mode Write
tCl
ClK Set Up for Count latch
ns
ns
150
120
100
ns
100
ns
0
55
0
55
ns
-5
50
-5
40
ns
240
ns
40
ns
. ClK Delay for loading(4)
tWG
ns
50(3)
260
-40
45
--'40
NOTES:
2, In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 82C54-2)
of the rising clock edge may not be detected,
.
..
3, low-going glitches that violate tpWH; tpWl may cause errors requiring counter reprogramming.
4. Except for Extended Temp., See Extended Temp. A.C. Characteristics below.
5. Sampled not 100% tested. TA = 25°C.
6. If ClK present at Twe min··then Count·equals· N + 2 CLKpulses, Twe max equals Count N + 1 ClK pulse. TWC min to,
TWC maX, count will be either N + 1 or N + 2 ClK pulses.
. .
7. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWG
max Counter will be triggered.
8.. lf ClK present when writing a Counter latch or Read8ack Command, at TCl min ClK will be reflected in count value·
latched, at TCl max ClK will not be reflected in the count value latched. Writing a Counter Latch or Read8ack Command
between TCL min and TWL max will result in a latched count vallue which is .± one least s.ignificant bit
'
EXTENDED TEMPERATURE (TA = -40·Cto
Symbol
+ 85·C for Extended Temperature)
82C54-2
82C54
Parameter
Units
Min
Max
Min
Max
twc
ClK Delay for loading
-25
25
-25
25
ns
tWG
Gate Delay for Sampling
-25
25
-25
25
ns
6-60
inter
82C54
WAVEFORMS
WRITE
A,.,
"'--IAW----"
CS
DATA BUS
WA
231244-14
READ
AG·.
I ••
cs
DATA B U S - - -
231244-15
l
~W_R~~_~_r__'~~_\~_~______~I·
R_EC__
OVE_RY_ _ _
_
__
231244-16
6-61
.
82C54
CLOCK AND GATE
----.:.......:/1"1
CUI
• GATE - - - _...._ _ _....;....:._11
OUTPUT 0
231244-17
• Last byte of count being written
A.C. TESTING INPUT, OUTPUT WAVEFORM
. >
u=x
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
2.0
TEST POINTS
0.45
_
d..
< )C.
_2.0
0.8 _ .
231244-18
A.C. Testing: Inputs are driven at2.4V for. a logic "1" and 0.45V
for a logic "0." Timing measurements are made at 2.0V for a logic
"I" and 0.8V for a logic "0."
231244-19
CL = 150 pF
CL includes jig capacitance
6-62
8255A/8255A-5
PROGRAMMABLE PERIPHERAL INTERFACE
Compatible 8255A-5
• 24MCS-85™
Programmable 1/0 Pins
• Completely TTL Compatible
• Fully
Compatible with Intel
• Microprocessor
Families
Improved Timing Characteristics
•
Direct Bit Set/Reset Capability Easing
• Control
Application Interface
Reduces System Package Count
• Improved
Driving Capability
• Available inDCEXPRESS
• - Standard·Temperature Range
- Extended Temperature Range
• 40 Pin DIP Package or 44 Lead PLCC
(See Intel Packaging: Order Number: 231369)
The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It
has 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of
operation. In the first mode (MODE 0), each group of 12 I/O pins may be programmed in sets of 4 to be input
or output. In MODE 1, the second mode, each group may be programmed to have 8 lines of input or output. Of
the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation
(MODE 2) is a bidirectional bus mode which uses 8 lines for a bidirectional bus, and 5 lines, borrowing one
from the other group, for handshaking.
POWER { _ + 5 V
SUPPLIES
GROUP
A
_GND
GROUP
A
CONTROl
'OAT
A
IS)
JV----,
, ' -_ _/
".
PC1- PC 4
BI-DIRECTIONAL OATA BUS
DATA
BUS
BuFFER
8-BIT
INTERNAL
".
OATA BUS
I'-r-_~/ pe3-P<:O
OI5--_.q
",,---.q
READ
GROOP
WRITE
A , -_ _.j c~~~
COH~AOL K:==~
GROIJP
1/'----".1
B
"lOT
B
(81,
Ao---.j
"SET---.j
231308-2
Figure 2. Pin
Configuration
231308-1
Figure 1. 8255A Block Diagram
6-63
November 1987
Order Number: 231308·002
inter
8255A/8255A-5
CPU Address and Control busses and in turn, issues
commands to both of the Control Groups.
8255A FUNCTIONAL DESCRIPTION
General
The 8255A is a programmable peripheral interface
(PPI) device designed for use in Intel microcomputer
systems. Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the 8255A is programmed by the system
software so that normally no external logic is necessary to interface peripheral devices or structures.
Chip Select. A "low" on this input pin enables the
communication between the 8255A and the CPU.
Read. A "low" on this input pin enables the 8255A
to send the data or status information to the CPU on
the data bus. In essence, it allows the CPU to "read
from" the 8255A.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface the 8255A to the system data bus. Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control
words and status information are also transferred
through the data bus buffer.
Write. A "low" on this input pin enables the CPU to
write data or control words into the 8255A.
(AO and A1)
Read/Write and Control Logic
Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the
control word registers. They are normally connected
to the least significant bits of the address bus (Ao
and Al).
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. It accepts inputs from the
POWER
SUPf'l.'"
[ - - ·5.
--aND
I/~--"
I'v--~/
K==~
I/L---".I
,:~~p
a
"0
PA,-pAo
110
PBrPBo
IS:
231308-3
Figure 3. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
6-64
intJ
8255A/8255A-5
Each of the Control blocks (Group A and Group B)
accepts "commands" from the Read/Write Control
Logic, receives "control words" from the internal
data bus and issues the proper commands to its associated ports.
8255A BASIC OPERATION
A1 Ao RD WR CS Input Operation (READ)
0
0
0
1
0
Port A --+ Data Bus
0
1
0
1
0
Port B --+ Data Bus
1
0
0
1
0
Port C. --+ Data Bus
Control Group A-Port A and Port C upper (C7 -C4)
Control Group B-Port B and Port Clower (C3-CO)
Output Operation
(WRITE)
0
0
1
0
0
Data Bus --+ PortA
0
1
1
0
0
Data Bus --+ Port B
1
0
1
0
0
Data Bus --+ PortC
1
1
1
0
0
Data Bus --+ Control
The Control Word Register can Only be written into.
No Read operation of the Control Word Register is
allowed.
Ports A, B, and C
The 8255A contains three 8-bit ports (A, B, and C).
All can be configured in a wide variety of functional
characteristics by the system software but each has
its own special features or "personality" to further
enhance the power and flexibility of the 8255A.
Disable Function
X
X
X
X
1
1
1
X
X
0
1
0
Illegal Condition
1
1
0
Data Bus --+ 3-State
Data Bus --+ 3-State
Port A. One 8-bit data output latch/buffer and one
8-bit data input latch.
(RESET)
Port B. One 8-bit data input/output latch/buffer and
one 8-bit data input buffer.
Reset A "high" on this input clears the control register and all ports (A, B, C) are set to the input mode.
Port C. One 8-bit data output latch/buffer and one
8-bit data input buffer (no latch for input). This port
can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4-bit latch and it
can be used for the control signal outputs and status
Signal inputs in conjunction with ports A and B.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the
CPU "outputs" a control word to the 8255A. The
control word contains information such as "mode",
"bit set", "bit reset", etc., that initializes the functional configuration of the 8255A.
6-65
8255A/8255A-5
POWER
SUPPLIES
{- ' "
.
_ _ GND
CONTROL
..
GROUP
PORT
GROUP
1'<------,
,B,
0/0
I'v----,/
PA 7~PAO
'''-_-0/
PC7-PC4
'''-_-0/
pel-PCO
'/0
BI-DIRECT10NAl DATA BUS
07-00
,,---,/I
DATA
BUS
BUFFER
INTERNAL
DATA BUS
110
RD
WA
WRITE
CONTROL
"
lOGIC
GROUP
GROUP
B
PORT
B
B
CONTROL
'.
0/0
PS,-PDO
,81
C,-------'
231308-4
Figure 4. 8225A Block Diagram Showing Group A and Group B Control Functions
Pin Names
Pin Configuration
PA'
PA'
PA2
PAS
PAl
PAS
PA'
WR
cs
GND
D.
A.
0,
AO
0,
0,
8255A
D.
PC'
07- 0 0
Data Bus (Bi-Directional)
RESET
Reset Input
CS
Chip Select
RD
Read Input
WR
Write Input
AO, A1
Port Address
PA7-PAO
PortA (BIT)
PB7-PBO
Port B (BID
PC7-Pca
Port C (BIT)
Vee
+5 Volts
GND
°Volts
PBll 19
PB2:-
8255A OPERATIONAL DESCRIPTION
20
231308-5
Mode Selection
There are three basic modes of operation that can
be selected by the system software:
6-66
inter
8255A/8255A-5
Mode O-Basic Input/Output
CONTROL WORD
lDj D,
Mode 1-Strobed Input/Output
Mode 2-Bi-Directional Bus
D51 Dj D1D,l D,l DoJ
J
L,J
When the reset input goes "high" all ports will be set
to the input mode (i.e., all 24 lines will be in the high
impedance state). After the reset is removed the
8255A can remain in the input mode with no additional initialization required. During the execution of
the system program any of the other modes may be
selected using a single output instruction. This allows a single 8255A to service a variety of peripheral
devices with a simple software maintenance routine.
/
GROUP B
\
PORT C (LOWER)
1 ",INPUT
0'" OUTPUT
'-----
PORT B
1" INPUT
'-------
0= OUTPUT
MODE SELECTION
O=MOOEO
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of
the output registers, including the status flip-flops,
will be reset whenever the mode is changed. Modes
may be combined so that their functional definition
can be "tailored" to almost any I/O structure. For
instance; Group B can be program mod in Mode 0 to
monitor simple switch closinrJs or display computational rosults, Group /\ could be programmed in
Mode 1 to monitor a koyboard or tapo read or on an
interrupt-drivon basis.
l=MODE 1
/
GROUP A
\
PORT C (UPPER)
1 = INPUT
0" OUTPUT
PORTA
1 '" INPUT
0= OUTPUT
MODE SELECTION
OO=MDDEO
01
=> MODE 1
lX= MODE 2
ADDRESS BUS
-'
MODE SET FlAG
1 "ACTIVE
231308-7
~.,--.-
Figure 6. Mode Definition Format
The mode definitions and possible mode combinations may seem confusing at first but after a cursory
review of the complete device operation a simple,
logical I/O approach will surface. The design of the
8255A has taken into account things such as officient PC board layout, control signal definition vs PC
layout and complete functional flexibility to support
almost any peripheral device with no external logic.
Such design represents the maximum use of the
available pins.
MOO!: 1.- -r'"-:?'g:::--1I0'rr'lllrr-l----rlllr-TTII'---:jy*-'>:'\:
PS1"PBO
C~~TI7gL
C~~TI~gL
PArPAg
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction. This feature reduces software requirements in Control-based applications.
231308-6
Figure 5_ Basic Mode Definitions and Bus
InterfaCe
6·67
8255A/8255A-5
This function allows the Programmer to disallow or
allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure.
CONTROL WORD
I
0 0, 0 0, 0,-[ 0,1 0.1 Dol
I I I
7
1
I
I X
5
1
X
I
Lr
I
X I
INTE flip-flop definition:
BIT SET/RESET
1 = SET
0" RESET
(BIT-SET)-INTE is set-Interrupt enable
DON'T
CARE
(BIT-RESET)-INTE is RESET-Interrupt disable
BIT SELECT
01234567
0101010180
001100111 8 1
000011118,1
BIT SET/RESET FLAG
0= ACTIVE
I
231308-8
Figure 7. Bit Set/Reset Format
Whim Port C is being used as status/control for Port
A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output
ports.
NOTE:
All Mask flip-flops are automatically reset during
mode selection and device Reset.
Operating· Modes
MODE 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No "handshaking"
is required, data is simply written to or read from a
specified port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-pit ports.
• Any port can be input or output.
Interrupt Control Functions
• Outputs are latched.
• Inputs are not latched.
• 16 different Input/Output configurations are possible in this Mode.
When the 8255A is programmed to operate in mode
1 or mode 2, control signals are provided that can be
used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can
be inhibited or enabled by setting or resetting the
associated INTE flip-flop, using the bit set/reset
function of port C.
MODE 0 (BASIC INPUT)
----nu
-'
....
...
--
!-tHR _
I-tlf'CINPUT
F--tAR~
-tRA~1
CS,Al.AO
° ,°
1
0- - - -
----_.-t-(
--'RO
'OF
231308-9
6-68
8255A/8255A-5
MODE 0 (BASIC OUTPUT)
fwD
~------'wA------~
CS,A1.AO
L . -~-
OUTPUT
231308-10
MODE 0 PORT DEFINITION
A
Group B
Group A
B
#
Port B
PortC
(Lower)
0
OUTPUT
OUTPUT
OUTPUT
1
OUTPUT
INPUT
OUTPUT
2
INPUT
OUTPUT
D4
D3
D1
Do
PortA
PortC
(Upper)
0
0
0
0
OUTPUT
OUTPUT
.. _...
0
0
0
1
OUTPUT
0
0
1
0
OUTPUT
0
0
1
1
OUTPUT
OUTPUT
3
INPUT
INPUT
0
1
0
0
OUTPUT
INPUT
4
OUTPUT
OUTPUT
0
1
0
1
OUTPUT
INPUT
5
OUTPUT
0
1
1
0
OUTPUT
INPUT
6
INPUT
0
1
1
1
OUTPUT
INPUT
7
INPUT
INPUT
-- ._-
~--.
"------------
~-----.
--_. -------
..... ---
.... _--
INPUT
------
OUTPUT
-_ ... _-
1
0
0
0
INPUT
OUTPUT
8
OUTPUT
OUTPUT
1
0
0
1
INPUT
OUTPUT
9
OUTPUT
INPUT
.....•....
-
1
0
1
0
INPUT
OUTPUT
10
INPUT
OUTPUT
1
0
1
1
INPUT
OUTPUT
11
INPUT
INPUT
1
1
0
0
INPUT
INPUT
12
OUTPUT
OUTPUT
1
1
0
1
INPUT
INPUT
13
OUTPUT
INPUT
14
INPUT
15
INPUT
- .---- ...
--------- --'--"--.
....
_----_.- - - - _ .._--- ---
1
1
1
0
INPUT
INPUT
1
1
1
1
INPUT
INPUT
6-69
.
OUTPUT
- -----
----
INPUT
8255A/8255A·5
MODE CONFIGURATIQNS
CONTROL WORD #2
CONTROL WORD #0
0,
I
D.
D.
D.
03
O2
0,
07
DO
1 1 10 1 10 1 0 10
06
D5
04
0
0
03
02
I I I I I I I' I I
I
8
A
8255A
C{
4
c{
·
8
A
8255A
·
00
0
4
8
B
B
Pa.,.PBO
4
4
.
,8
I
231308-12
231308-11
CONTROL WORD #1
07
06
05
Dol
CONTROL WORD #3
03
02
0,
DO
07
I I I I I I I I, I
06
Os
04
03
8
A
8
A
8255A
8255A
C{ .
·
DO
01
I I I I I I I, 1, I
0
·
02
B
4
.
,4
.
C{ .
7
8
4
I
,4
8
B
231308-13
231308-14
CONTROL WORD . .
01
Dfi
05
04
CONTROL WORD #8
D3
02
0,
00
0
0
07
II I II II II
0
0
A
06
Os
04
03
·
02
DO
0,
IIIIIII II
0
0
8
A
8255A
·
pa.,·pBo
.
,8
I
8255A
c{
B
4
.
14
8
.
C{
B
231308-15
4
4
8
231308-16
6-70
intJ
8255A/8255A-5
CONTROL WORD
#5
CONTROL WORD #9
171~1~1~171~1:1~1
8
A
A •
825sA
4
C{
.
.
I
4
c{
4
8
B
4
8
B
231308-17
231308-18
CONTROL WORD #6
CONTAOl WORD #10
I~' ID: ID: I:' I~31 ~ I ~'
D7
06
DS
04
.03
02
01
A ---- -- _/_11. _..• "A,."A"
8255A
.
.
231308-19
DC
4
.
I
£B
231308-20
CONTROL WORD #7
Os
4
c{
B
06
8
A
8255A
07
£8
8255A
CONTROL WORD #11
D3
02
D1
DO
A
r---F---
AI---f-=---
8255A
B255A
4
c{ .
B
C
(4
{I---;--'-----+
PC,-pc.
.----r-- PC3 -PCo
I
8
B 1+---;-"-- PB,-POO
231308-21
231308-22
6-71
8255A/8255A-5
CONTROL WORD #12
CONTROL WORD #14
0,
D.
05
0
0
D.
03
O2
0,
,Do
1, I I I, 1, I ~ 1, 1 I
A •
0
,8
A
J
8255A
8255A
C{
B
4
.
4
8
.
c{
PB,.PD.
.
J
.
J
B
231308-23
06
05
04
4
8
CONTROL WORD #15
03
02
0,
DO
07
l' I I I I I I l' I
0
,4
231308-24
CONTROL WORD #13
07
,8
0
Dli
04
03
02
0,
00 _
l' I I l' 1, I l' l' I
0
A
06
0
0
0
8
A·
8255A
J' II
·9255A
c{
B
4
.
,4
8
.
c{
B
231308-25
4
4
8
231308-26
Operating Modes
Input Control Signal Definition
MODE 1 (Strobed Input/Output). This functional
configuration provides a means for transferririg I/O
data to or from a specified port in conjunction with
strobes or "handshaking" signals. In mode 1, port A
and port B use the lines on port C to generate. or
accept these "handshaking" signals.
STB (Strobe Input). A "lOW" on this input loads
.
data into the input latch.
Mode 1 Basic Functional Definitions:
• Two Groups (Group A and Group B)
• Each group contains one 8-bit data port and one
4-bit control/data port.
• The 8-bit data port can be either input or output.
Both inputs and outputs are .Iatched.
• The 4·bit port is used for control and status of the
8-bit data port.
IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has
been loaded into the input latch; in essence, an acknowledgement. IBF is set by STB input being low
and is reset by the rising edge of the RD input.
INTR (Interrupt Request)
.A "high" on this output can· be used to interrupt the
CPU when· an input device is requesting service.
INTR is set by the STB is a "one", IBF is a "one"
and INTE is a "one". It is reset by the falling edge of
RD. This procedure allow~ an input device to request service from the CPU by simply strobing its
data into the port.
6-72
8255A/8255A-5
INTE A
INTE B
Controlled by bit set/reset of PC4.
Controlled by bit set/reset of PC2.
MODE 1 (PORT A)
MODE 1 (PORT B)
CONTROL WORD
2
PC" 7
--+--- I/O
231308-27
231308-28
Figure 8. MODE 1 Input
I
,~
!.IIL
fa
..
.
V
!. "''''}l
IBF
tSIT
\
·~-I
r)
J
INTR
I_'R"-~)
/
_""_1
INPUT I nOM
"I.HII'11i UAL
---
---------------------
1-
---
-.-.IPS--~----
231308-29
Figure 9. MODE 1 (Strobed Input)
6-73
8255A/8255A-5
device has accepted data transmitted by the .CPU.
INTR is set when ACK is a "one", OBF is a "one",
and INTE isa "one". It is reset by the falling edge of
WR.
Output Control Signal Definition
OBF (Output Buffer Full F/F). The OBF output will
go "low" to indicate that the CPU has written data
out to the specified port. The OBF F/F will be set by
the rising edge of the WR input and reset by ACK
input being low.
INTE A
Controlled by bit set/reset of PCs.
ACK (Acknowledge Input). A "low" on this input
informs the 8255A that the data from port A or port
B has been accepted. In essence, a response from
the peripheral device indicating that it has received
the data output by the CPU.
INTE B
Controlled by bit set/reset of PC2.
INTR (Interrupt Request). A "high" on this output
can be used to interrupt the CPU when an output
MODE 1 (PORT A)
MODE 1 (PORT B)
PA,·P"o
B
CONTflOl
CONTROL WORD
wonn
PC,
0'B'f1J
r--"
I INTE I
I __
B Jr
PC,
INTRB
WR_
231308-30
231308-31
Figure 10. MODE 1 Output
WIl
\
\ I
OBf
INTR
.
twrT-
~}
f------------ 1 AO B - -
---
7/)
//
-,.d-tA,T-
ACK
OUTPUT
H-twB
231308-32
Figure 11. MODE 1 (Strobed Output)
6-74
infef
8255A/8255A-5
PArPAo
PC,
STBA
PCs
!BFA
PC,
INTRA
PC J
2
PC6. 7
---I---
INTRA
2
I/O
PC4,5
-----r--
I/O
PC,
INTRa
PC,
1BFa
PCo
INTRa
231308-34
231308-33
PORT A-(STROBED OUTPUT)
PORT B-(STROBED INPUT)
PORT A-(STROBED INPUT)
PORT B-(STROBED OUTPUT)
Figure 12. Combinations of MODE 1
Combinations of MODE 1
Bidirectional Bus I/O Control Signal
Definition
Port A and Port B can be individually defined as input or output in MODE 1 to support a wide variety of
strobed 110 applications.
INTR (Interrupt Request). A high on this output can
be used to interrupt the CPU for both input or output
operations.
Operating Modes
Output Operations
MODE 2 (Strobed Bidirectional Bus 1/0). This
functional configuration provides a means for communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving
data (bidirectional bus 110). "Handshaking" signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1. Interrupt generation
and enable/disable functions are also available.
OBF (Output Buffer Full). The OBF output will go
"low" to indicate that the CPU has written data out
to port A.
ACK (Acknowledge). A "low" on this input enables
the tri-state output buffer of port A to send out the
data. Otherwise, the output buffer will be in the high
impedance state.
MODE 2 Basic Functional Definitions:
INTE 1 (The INTE Flip-Flop Associated with
OBF). Controlled by bit set/reset of PCe.
• Used in Group A only:
• One 8·bit, bi-directional bus Port (Port A) and a 5bit control Port (Port C).
• Both inputs and outputs are latched.
• The 5·bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port
(Port A).
Input Operations
STB (Strobe Input). A "low" on this input loads
data into the input latch.
6-75
8255A/8255A-5
IBF (Input Buffer Full F/F). A "high" on this output
indicates that data has been loaded into the input
latch.
INTE 2 (The INTE Flip-Flop, Associated with IBF).
Controlled by bit set/reset of PC4.
CONTROL WORD
PC 24
1'" INPUT
O-OUTPUT
L---_PORTB
, = INPUT
O=OUTPUT
pc"
WR_
L -_ _ _ _ GROUP B MODE
0" MODE 0
1=MQDE1
3
00-
231308-35
PC24
---f-- I/O
Figure 13. MODE Control Word
231308-36
Figure 14. MODE 2
/J
DATA FROM
CPU TO 8255A
/
INTR
IBF
PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS
/
DATA FROM
PERIPHERAL TO 8255A
DATA FROM
8255A TO 8080
231308-37
NOTE:
Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF. MASK. STB • RD + OBF • MASK. ACK • WR)
Figure 15. MODE 2 (Bidirectional)
6-76
inter
8255A/8255A-5
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC,
PA,'PAo
PC,
INTR"
~
PA,'PAo
pc.
CONTROL WORD
o,D."sD,D,D2
0, DO
I ' II !XIXD<1XJ
----.-------_ -----------1'-----,-GROUP A
PB,
pe,
PB,
------1
PC,
_ _- - GROUP B
ACK
PC,
(DEFINED BV MODE 0 OR MODE 1 SELECTION)
PC,
231308-42
CONTROL LOGIC AND DRIVERS
INTERRUPT
Figure 18. MODE 2 Status Word Format
REQUEST
231308-43
Figure 19. Printer Interface
APPLICATIONS OF THE 8255A
The 8255A is a very powerful tool for interfacing peripheral equipment to the microcomputer system. It
represents the optimum use of available pins and is
flexible enough to interface almost any lID device
without the need for additional external logie<.
INTERRUPT
REOU
EST
I
PC,
8255A
Each peripheral device in a microcomputer system
usually has a "service routine" associated with it.
The routine manages the software interface between the device and the CPU. The functional definition of the 8255A is programmed by the lID service
routine and becomes an extension of the system
software. By examining the lID devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the detailed operational description, a control
word can easily be developed to initialize the 8255A
to exactly "fit" the application. Figures 19 through
25 represent a few examples of typical applications
of the 8255A.
MODEl
!lNPUTI
PAo
PA,
Ro
R,
PA,
PA,
PA,
R,
R,
R,
PAs
PA,
PA,
CONTROL
PC,
STROBE
Pc,
ACK
FULLY
DECODED
KEYBOARD
Rs
SHIFT
~
'.Bo
PB,
MODEl
(OUTPUTI
PB,
P.,
PB,
PBs
P.,
P.,
PC.
PC,
PC,
PC,
PC,
Bo
B,
.,.,
.,
BURROUGHS
SELF-SCAN
DISPLAY
Bs
BACKSPACE
CLEAR
DATA READY
ACK
BLANKING
CANCEL WORD
UPT~
INTERR
REQUEST
231308-44
Figure 20. Keyboard and Display Interface
6-79
inter
8255A/8255A-5
INTERRUPT
INTERRUPTI
REaUEST'~
PC,
:~~T;8255"
REQUEST
R,
PA,
R,
PA,
R,
PA,
R,
FULLY
DECODED
KEYBOARD
PA,
R,
PAs
R,
PAs
SHIFT
PA,
CONTROL
PA,
MODE2
PC,
ACKNOWLEDGE
PC,
BUSY LT
PC,
TEST IT
-----,=
.....
------'b-
ttt---'bIt-I-
PB,
--'b-
PB,
PB,
PB,
PB,
PBs
T EAMINAL
AoORESS
PC,
PC,
PC,
PC,
PC,
tt-
-
231308-45
0,
0,
0,
0,
FLOPPY DISK
CONTROllER
AND DRIVE
0,
0,
0,
0,
DATA 5TS
ACK /IN)
DATA READY
ACK (OUTI
TRACK "0" SENSOR
.pc,
SYNC READY
PC,
INDEX
r
M~DE 0
(OUTPUT)
--'b--
PB,
PAo
PA,
PB,
PB,
--'b---
PB,
PA,
PA,
PA,
PA,
PA,
STROBE
PC,
~~~~T~-
PC,
PAo
ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
PB3
PB.
DISC SELECT
PB,
ENABLE CRe
P8,
TEST
PB,
BUSY LT
231308-47
Figure 23. Basic Floppy Disk Interface
Figure 21. Keyboard and
Terminal Address Interface
INTERRUP.T I
REaUEST
PAo
PA,
PA,
PA,
PA,
MaCE 0
(OUTPUT)
PA,;
PA,
PA,
PC,
.....
PA,
-
PA,
MODE 1
(OUTPUT)
12·81T
D-A
CONVERTER
(OAt)
~
ANALOG OUTPUT
PA,
PAt
PA,
R,
R,
CRT CONTROLLER
R,
R,
R,
• CHARACTER GEN.
• REFRESH BUFFER
• CURSOR CONTROL
R,
SHIFT
CONTROL
PC,
OATA READY
PC,
PC,
PC,
ACK
BLANKED
r
MSB
I25SA
PC,
PC,
PB,
BLAC~M'HITE
OUTPUT EN
SAMPLE EN
PC,
PC,
ROW STB
COLUMN STB
PC,
CURSOR HN STB
STB
PB,
LSB
P8,
a.BIT
A-D
PB,
CONVERTER
(ADe)
PB,
P8,
PB,
P8,
P8,
PC,
PC,
5TB DATA
SET/RESET
MODE 0
(INPUT)
PAo
PA,
PA,
PC,
PC,
BIT
PC,
LSS
-
MODE 0
(OUTPUTI
ANALOG INPUT
PB,
PB,
PB,
PB,
PB,
PB,
PB,
l~~-='ADDRESS
H& V
MSB
231308-48
231308-46
Figure 24. BaSIC CRT Controller Interface
Figure 22. Digital to Analog, Analog to Digital
6-80
intJ
8255A/8255A-5
INTERRUPT
REaUE
ST~
PC,
PA" - - R o
PA,
R,
----
PA,
PA,
PA,
PAS
MODE 1
(lNPUTI
R,
R,
R,
PA,
Rs
R,
R,
PC,
ST.
PA,
8 LEVEL
PAPER
TAPE
READER
PC,;
ACK
PC,
STOP/GO
12554
MODE 0
UNPUT)
MACHINE TOOL
STARTfSTQP
{PCO
PC
PC,1
LIMIT SENSOR lHNI
OUT OF FLUID
CHANGE TOOL
r
MODE 0
taUTPUTl
PS,
LEfT fRIGHT
PB,
,UP/DOWN
PB,
PB4
HOR. STEP STROBe
VERT. STEP STROBE
SLEW/STEP
PBs
PS,
PS,
.
r----
FLUID ENABLE
EMERGENCY STOP
231308-49
Figure 25. Machine Tool Controller Interface
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a -stress rating only and
functional operation of the device at these or any
other. conditions above those indicated in the opera- tional sections of this specification is not implied Exposure to absolute maxiinum ;ating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O·C to 70·C
Storage Temperature .........• - 65·C to
+ 150·C
Voltage on Any Pin
with Respect to Ground ......•... - 0.5V to
+ 7V
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS TA =
Symbol
O·C to 70·C, Vcc =
Parameter
+ 5V
± 10%, GND = OV'
Min
Max
Unit
Input Low Volt,age
-0.5
0.8
V
Test Conditions
VIH
Input High Voltage
2.0
Vcc
V
VOL (DB)
Output Low Voltage (Data Bus)
VOL (PER)
Output Low Voltage (Peripheral Port)
VOH (DB)
Output High Voltage (Data Bus)
VOH (PER)
Output High Voltage (Peripheral Port)
IDAR(1)
Darlington Drive Current
-4.0
mA
Icc
Power Supply Current
120
mA
IlL
Input Load Current
±10
/LA
VIN = Vcc toOV
IOFL
Output Float Leakage
±10
/LA
VOUT = Vcc to 0.45V
,-
VIL
\
0.45'
V
IOL =2.5mA
0.45"
-V
IOL = 1.7mA
2.4
V
IOH = -400/LA
2.4
V
IOH = - 200 /LA
-1.0
NOTE:
1. Available on any 8 pins from Port Band C.
6-81
REXT = 7500; VEXT = 1.5V
8255A/8255A-5
CAPACITANCE T A =
Symbol
25°C, Vee = GND = OV
Max
Unit
CIN
Input Capacitance
Parameter
Min
10
pF
Test Conditions
fc = 1 MHz(4)
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to GND(4)
A.C. CHARACTERISTICS TA =
Typ
+ 5V
O°C to 70·C, Vee =
± 10%, GND = OV'
Bus Parameters
READ
Symbol
8255A
Parameter
Min
8255A-5
Max
Min
Unit
Max
tAR
Address Stable before READ
0
0
ns
tRA
Address Stable after READ
0
0
ns
tRR
READ Pulse Width
tRO
Data Valid from READ(1)
300
tOF
Data Float after READ
tRY
Time between READs and/or WRITEs
300
ns
250
10
150
10
850
200
ns
100
ns
850
ns
WRITE
Symbol
8255A
Parameter
Min
8255A-5
Max
Min
Unit
Max
tAW
Address Stable before WRITE
0
0
tWA
Address Stable after WRITE
20
20
ns
ns
tww
WRITE Pulse Width
400
300
ns
tow
Data Valid to WRITE (T.E.)
100
100
ns
two
Data Valid after WRITE
30
30
ns
OTHER TIMINGS
Symbol
Min
=
8255A-5
8255A
Parameter
Min
Unit
Max
tWB
WR
tlR
Peripheral Data before RD
0
0
ns
tHR
Peripheral Data after RD
0
0
ns
tAK
ACK Pulse Width
300
300
ns
tST
STS Pulse Width
500
500
ns
tps
Per. Data before T.E. of STS
0
0
ns
tpH
Per. Data after T.E. of STS
180
180
tAD
ACK
tKO
ACK = 1 to Output Float
=
1 to Output(1)
Max
350
0 to Output(1)
350
300
20
6-82
250
20
ns
ns
300
ns
250
ns
intJ
8255A/8255A·5
A.C. CHARACTERISTICS (Continued)
OTHER TIMINGS (Continued)
Symbol
8255A
Parameter
Min
= 1 toOSF = 0(1)
= 0 to OBF = 1(1)
STB = 0 to IBF = 1(1)
RD = 1 to ISF = 0(1)
RD = 0 to INTR = 0(1)
STB = 1 to INTR = 1(1)
ACK = 1 to INTR = 1(1)
WR = 0 to INTR = 0(1,3)
twoB
tAos
tSIB
tRIBtRIT
tSIT
tAIT
tWIT
8255A·5
Max
Min
Unit
Max
WR
650
650
ns
ACK
350
350
ns
300
300
ns
300
300
ns
400
400
ns
300
300
ns
350
350
ns
850
850
ns
NOTES:
1. Test Conditions: CL = 150 pF.
2. Period of Reset pulse must be at least 50 p.s during or after power on. Subsequent Reset pulse can be 500 ns min.
3. INTR
may occur as early as WR J. .
4. Sampled, not 100% tested.
-For Extended Temperature EXPRESS, use M8255A electrical parameters.
t
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
Input/Output
2.4
2.0
0.45
0.8
.::>
TEST POINTS
<
DEVICE
UNDER
TEST
2.0
0.8
i
-=
231308-50
A.C. Testing: Inputs are driven at 2.4V for a LogiC "'1" and 0.45V
for a Logic "'0"'. Timing measurements are made at 2.0V for a
Logic "'I"' and 0.8V for a Logic "'0"'.
A
-0 YEXT'"
Ct. = 150pF
231308-51
·VEXT is set at various voltages during testing to guarantee the
specification. CL includes jig capacitance.
6-83
8255A18255A-5
WAVEFORMS
MODE 0 (BASIC INPUT)
-
'RR
-,
-. r-
CIR-
r--tHR----:-1
INPUT
I==::.t
~tRA--:1
AR -
CS, Al, AO
--"-- - - - - - - ~<
'RO
.
'OF
.
--
231308-52
MODE 0 (BASIC OUTPUT)
'w0
1-----,,"-----1
I------'''A-------I
CS,A1.AO
OUTPUT
'wB
231308-53
6-84
inter
8255A/8255A-5
WAVEFORMS (Continued)
MODE 1 (STROBED INPUT)
- - tST -
-'SlB
IBF
1
1
tSIT
INTR
J ,-)
-'RIB_,)
/
/
I-tpH-:1
INPUT FROM
PERIPHERAL
---
--------------------'PS
231308-54
MODE 1 (STROBED OUTPUT)
INTR
_twiT
OUTPUT
231308-55
6-85
inter
8255A/8255A-5
WAVEFORMS (Continued)
MODE 2 (BIDIRECTIONAL)
A
----,.
DATA FROM
BOBO TO B255
-'AO'y
\
~
INTR
j
...
/
'I
"'tWOB_~
\
L
- tAK -
//~
Ack
\
/
--'sr-V
1\
""1
IBF
1
-'l- - -
;.,
'PERIPHERAL
BUS
----------
---
/
\
'--t KO ) -
---
t.OM
DATA
PERIPHERAL TO 8255
}------ ---
- r--
/
tpH~
DATA
~OM
8255 TO PERIPHERAL
___ - t Rle
/
DATA FROM
8255 TO 8080
NOTE:
Any sequence where WR occurs before ACK and STS occurs before RD is permissible.
(INTR = ISF • MASK. STS • RD + OSF • MASK. ACK • WR)
WRITE TIMING
231308-56
READ TIMING
"-1' cs_ _.I1'__________l--'f'__ _ __
DATA BUS
--------~,~~--+---~'----
DATA BUS
HIGH IMPEDANCE
--------------4---4-----~
231308-58
231308-57
6-86
intJ
82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Word Read-Back Capability
• Control
Bit SetlReset Capability
• Direct
2.5 mA DC Drive Capability on all 1/0
with all Intel and Most
• Compatible
Other Microprocessors
High Speed, "Zero Wait State"
• Operation
with 8 MHz 8086/88 and
80186/188
,
24 Programmable 1/0 Pins
• Low Power CHMOS
• Completely TTL Compatible
•
•
•
•
Port Outputs
Available in 40-Pin DIP and 44-Pin PLCC
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The Intel 82C55A is ~ high-performance, CHMOS version of the industry standard 8255A general purpose
programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides
241/0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or. outputs. In
MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used
for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.
The 82C55A is· fabricated on Intel's advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages.
65"
POlitI" {
-'"
SUPPUES
_
_
'"'
3
2
1 4443424140
Bless.
18 19 20 21 222324 2S 28 27 28
231256-31
v.
,.,"'10
231256-1
Figure 1. 82C55A Block Diagram
231256-2
Figure 2. 82C55A Pinout
Diagrams are for pin reference only. Package
sizes are not to scale.
6-87
September 1987
Order Number: 231256.004
inter
82C55A
Table 1. Pin Description
Symbol
Pin Number.
Dip
PLCC
Name and Function
Type
1-4
2-5
I/O
RD
5
6
I
READ CONTROL: This input is low during CPU read operations.
CS
6
7
I
CHIP SELECT: A low on this input enables the 82C55A to
respond to RD and WR signals. RD and WR are ignored
otherwise.
PA3-0
GND
7
8
A1-0
8-9
9-10
PORT A, PINS 0-3: Lower nibble of an 8-bit data output latchl
buffer and an 8-bit data input latch.
System Ground
I
ADDRESS: These input signals, in conjunction RD andWR,
control the selection of one of the three ports or the control
word registers;
RD
WR
CS
Input Operation (Read)
0
0
1
0
Port A - Data Bus
0
1
0
1
0
Port B - Data Bus
1
0
0
1
0
Port C - Data Bus
1
1
0
1
0
Control Word - Data Bus
A1
0
Ao
Output Operation (Write)
0
0
1
0
0
Data Bus - Port A
0
1
1
0
0
Data Bus - Port B
1
0
1
0
0
Data Bus· Port C
1
1
1
0
0
Data Bus - Control
X
X
X
X
1
Data Bus - 3 - State
X
X
1
1
0
Data Bus - 3 - State
Disable Function
11,13-15
1/0
PORT C, PINS 4-7: Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input buffer (no latch for input). This port
can be divided into two 4-bit ports under themode control. Each
4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports
Aand B.
14-17
16-19
I/O
PORT C, PINS 0-3: Lower nibble of Port C.
18-25
20-22,
24-28
I/O
PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8bit data input buffer.
PC7-4
10-13
PCO-3
PBO.7
26
29
D7-0
27-34
30-33,
35-38
1/0
RESET
35
39
I
RESET: A high on this input clears the control register and all
ports are set to the input mode.
WR
36
40
I
WRITE CONTROL: This input is low during CPU write
operations.
37-40
41-44
I/O
PA7-4
NC
1,12,
23,34
SYSTEM POWER:
+
Vee
5V Power Supply.
DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus.
PORT A, PINS 4-7: Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input latch.
No Connect
6-88
intJ
82C55A
Each of the Control blocks (Group A and Group B)
accepts "commands" from the Read/Write Control
Logic, receives "control words" from the in.ternal
data bus and issues the proper commands to Its associated ports.
82C55A FUNCTIONAL DESCRIPTION
General
The B2C55A is a programmable peripheral interface
device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the B2C55A is programmed by the system
software so that normally no external logic is necessary to interface peripheral devices or structures.
Control Group A - Port A and Port C upper (C7 -C4)
Control Group B - Port B and Port Clower (C3-CO)
The control word register can be both written and
read as shown in the address decode table in the
pin descriptions. Figure 6 shows the control word
format for both Read and Write operations. When
the control word is read, bit 07 will always be a logiC
"1", as this implies control word mode information.
Data Bus Buffer
This 3-state bidirectional B-bit buffer is used to interface the B2C55A to the system data bus. Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control
words and status information are also transferred
through the data bus buffer.
Ports A, B, and C
The B2C55A contains three B-bit ports (A, B, and C).
All can be configured in a wide variety of functional
characteristics by the system software but each has
its own special features or "personality" to further
enhance the power and flexibility of the B2C55A.
Read/Write and Control Logic
Port A. One B-bit data output latch/buffer and one
B-bit input latch buffer. Both "pull-up" and "pulldown" bus hold devices are present on Port A.
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. It accepts inputs from the
CPU Address and Control busses and in turn, issues
commands to both of the Control Groups.
Port B. One B-bit data input! output latch/buffer.
Only "pull-up" bus hold devices are present on Port
B.
Group A and Group B Controls
Port C•. One B-bit data output latch/buffer and one
B-bit data input buffer (no latch for i!1put). This port
can be divided into two 4-bit ports under the mode
contrcil. Each 4-bit port contains a 4-bit latch and it
can be used for the control Signal outputs and status
signal inputs in conjunction with ports A and B. Only
"pull-up" bus hold d~vices are present on Port C.
The functional configuration of each port is programmed by the systems software. In essence, the
CPU "outputs" a control word to the B2C55A. The
control word contains information such as "mode",
"bit set", "bit reset", etc., that initializes the functional configuration of the B2C55A.
See Figure 4 for the bus-hold circuit configuration for
Port A, B, and C.
6-B9
inter
82C55A
"""'·1-'"
'...,LlES
_ _ _ GNO
BI.()IR£CTtONAL DATA aus
D7DD¢==~
.. ----<>I
iill_
A, _ - ' - _ - (
rUADI
WRITE
C~~~L
.. -'----I
RESfT----I
13-----'
231256-3
Figure 3. 82C55A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
RESET
--::r~~t>Ci--,
EXTERNAL
IN:~~~ -
---oq.-'c.....- - -....
WR
• NOTE:
231256-4
Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset.
Figure 4. Port A, B, C, Bus-hold Configuration
6-90
inter
82C55A
82C55A OPERATIONAL DESCRIPTION
CONTROL WORD
I0,1
Mode Selection
0.1 0.1 0, I0, I0, I 0·1
L~
There are three basic modes of operation that can
be selected by the system software:
Mode 0 Mode 1 Mode 2 -
o.
Basic input/output
Strobed Input/output
Bi-directional Bus
/
GROUPS
~
PORT C (LOWERI
'--0
When the reset input goes "high" all ports will be set
to the input mode with all 24 port lines held at a logic
"one" level by the internal bus hold devices (see
Figure 4 Note). After the reset is removed the
82C55A can remain in the input mode with no additional initialization required. This eliminates the need
for pullup or pulldown devices in "all CMOS" designs. During the execution of the system program,
any of the other modes may be selected by using a
single output instruction. This allows a single
82C55A to service a variety of peripheral devices
with a simple software maintenance routine.
1 -INPUT
Q. OUTPUT
PORTB
, -INPUT
'-------"
o -OUTPUT
MODE SElECTION
a .. MODE 0
'·MOOEl
/
GROUP A
\
PORT C (UppeR)
1 .. INPUT
O· OUTPUT
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of
the output registers, including the status flip-flops,
will be reset whenever the mode is changed. Modes
may be combined so that their functional definition
can be "tailored" to almost any I/O structure. For
instance; Group B can be programmed in Mode 0 to
monitor simple switch closings or display computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an
interrupt-driven basis.
PORTA
1 -INPUT
a-OUTPUT
MODE SELECTION
00 .. MODE 0
O'''MODE 1
lX" MODE 2
MODE SET FLAG
'-ACTIVE
231256-6
Figure 6. Mode Definition Format
ADORESS BUS
The mode definitions and possible mode combinations may seem confusing at first but after a cursory
review of the complete device operation a simple,
logical I/O approach will surface. The design of the
82C55A has taken into account things such as efficient PC board layout, control signal definition vs PC
layout and complete functional flexibility to support
almost any peripheral device with no external logic.
Such design represents the maximum use of the
available pins.
MaOEO
MODE 1
--i
8
~o
Pa,-PB o
MODE 2
'!lIt lIn
CONTROL
CONTROL
OR 110
OR I/O
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction. This feature reduces software requirements in Control-based applications.
--fl;"llB"""-'rrrr:!::::;n=r=r---:::'A,,JT
~O
PS, ·PBg
'Illl I!I!
110
I
CONtROL
j3'D"ECTlONAL
•
PA7,PAn
When Port C is being used as status/ control for Port
A or B. these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output
ports.
231256-5
Figure 5. Basic Mode Definitions and Bus
Interface
6-91
inter
82C55A
Interrupt Control Functions
CONTROL WORD
When the 82C55A is programmed to operate' in
mode 1 or mode 2, control signals are provided that
can be used as interrupt request inputs to the CPU.
The interrupt request signals, generated from port C,
can be inhibited or enabled by setting or resetting
the associated INTE flip-flop, using the bit set/reset
function of port C.
This function allows the Programmer to disallow or
allow a specific 1/0 device to interrupt the CPU without affecting any other device in the interrupt struc.
ture.
INTE flip-flop definition:
231256-7
(SIT-SET)-INTE is SET-Interrupt enable
(SIT-RESET)-INTE is RESET-Interrupt disable
Figure,7. Bit Set/Reset Format
Note:
All Mask flip-flops are automatically reset during
mode selection and device Reset.
6-92
intJ
82C55A
Operating Modes
Mode 0 Basic Functional Definitions:
Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No "handshaking"
is required, data is simply written to or read from a
specified port.
•
•
•
•
•
Two a-bit ports and two 4-bit ports.
Any port can be input or output.
Outputs are latched.
Inputs are not latched.
16 different Input/Output configurations are possible in this Mode.
MODE 0 (BASIC INPUT)
'RR
..lr-
RD
C
0
,
~
r'"R-1
'R -
INPUT
r--'AR-
_ 1 RA
_j
CS, A1, AO
---
- - ' - - - - - - - - - .(
'RD
'0'
0
231256-8
MODE 0 (BASIC OUTPUT)
'wW
~.
7f-
I---'ow
'wD---l
'wA
'AW
f$.A1,AO
OUTPUT
_'w.---.j
231256-9
6-93
inter
82C55A
MODE 0 Port Definition
S
A
GROUPS
PORTC
PORTS
(LOWER)
GROUP A
D4
D3
D1
Do
PORTA
PORTC
(UPPER)
0
)0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
1
OUTPUT
0
1
0
1
0
1
0
1
INPUT
INPUT
INPUT
INPUT
OUTPUT
11
INPUT
INPUT
INPUT
INPUT
12
OUTPUT
OUTPUT
INPUT
INPUT
13 .
OUTPUT
INPUT
INPUT
INPUT
14
INPUT
OUTPUT
INPUT
INPUT
15
INPUT
INPUT
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
#
OUTPUT
OUTPUT
0
1
2
3
INPUT
INPUT
INPUT
4
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
5
6
7
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
8
OUTPUT
OUTPUT
OUTPUT
9
OUTPUT
INPUT
OUTPUT
10
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
MODE 0 Configurations
CONTROL WORD #0
0,
0,
05
0,
CONTAOL WORD #2
0,
0,
0,
I, I I I I I I
0
o
0
0
0
o
0,
0,
I 1
0
8
A
•
•
8
8
I' I
0,
0
o
0,
0,
0
0
1
0
0
a
A
c{
PC 1-PC 4
°7-0 0
PC 3..$1CO
8
PBr'Bo
0
0,
0,
0,
0,
0,
I, I
I I Io I'I
0
0
8
A
0,
0
05
0,
0,
0,
PA,PA o
•
PC 7·PC 4
•
pel,PCa
,
(8
PBrPBo
0,
0,
I I I I I, I' 1
0
0
0
0
8
A
PA,..."
82C55A
DrOo
0,
CONTROL WORD #3
0,
I'" I
0,
PA7-PAO
CONTROL WORD.1
0,
0,
82C55A
c{
1-00
05
I, I I I I I o I I 1
0
82C55A
°
0,
82C55A
4
c{
i
8
{.
8
PC 7-PC 4
°
1,00
pel-pea
PS 7-PB o
c{
B
•
,{.
{8
i
PA,PAo
PC 7-PC 4
pel,pca
PS 1-PB Il
231256-10
6-94
82C55A
MODE 0 Configurations (Continued)
CONTROL WORD #8
CONTROL WORD '4
0,
I
,
0,
0,
0,
0,
0,
,
0
0,
0,
Do
0
0
0
0,
0,
0
,
0
0
•
A
82C55A
D7".Q(~
0,
I, I I
I I I I I I I I
0
0,
0,
0,
Do
I I Io I I I
o
o
0
PA,-PA O
,'
A
.
c{ ··
PA,-PA O
82C55A
c{
•
•
pel-pc O
•
•
PBrPB o
PC,.PC 4
°7-0 0
•
B
PC , -PC 4
PCr-PCo
PB,-PB o
CONTROL WORD 19
CONTROL WORD .5
0,
I
,
0,
0,
0,
0,
,
0,
I I I I I I
0
0
0
0
0,
0,
Do
0
1,1
I, I
B
A
0,
0
0,
0,
0,
0,
c{ ·•
B
B
PA7-P~
I
,
0,
0,
0,
0
0
D7~O
pel-pe Cl
·pBo
0,
,
0
0,
0,
Do
,
I
•
.
A
°7-0 0
c{
,,
•
,
•
' B
I
,
0,
0
0
0,
0,
pel,pc O
•
PB 7·PB o
0,
0,
0,
0,
,
0
0,
0,
Do
,
0
I I I I I I I
0
0
0
•
PAt-PAo
•
PC 7·PC 4
•
pe 3'PC a
I
A
82C55A
c{
PC r PC 4
°rDo
pel-pcO
PBl-PS a
B
Do
,
0
0,
I, I
I
0,
,'
.
0,
0,
0,
0,
0,
,'
.
PB,·PB o
Do
I I , I I I , I, I
0
0
0
0
B
A
A
PA7-PAu
c{ ,"·
PA"PA o
82C55A
82CS5A
0,-0 0
PC, .PC 4
CONTROL WORD '11
0,
,
I I I I I I I,
0
,
PA7-PAO
CONTROL WORD #7
0,
,"
PAr-PAa
CONTROL WORD .10
0,
82C55A
0,
.
•
B
P6 7
0
0,
c{
PC,'PC 4
I I I I I I I I
0
,'
A
82C55A
CONTROL WORD #6
0,
Do
0
0
0
82C55A
°7.()O
0,
I I , I I I o I, I
c{
B
•
PC 7-PC 4
0 7-0 0
,"
pel-pc O
,"
P8 7-P BO
B
•
PC r PC 4
PC 3-PC O
PB,·PS O
231256-11
6-95
82C55A
MODE 0 Configurations (Continued)
CONTROL WORD #12
01
06
Os
04
CONTROL WORD #14
0]
02
01
07
Do
;
c{
° -°
0
05
04
0
12C5IA
1
D6
03
02
0,
Do
I, 1 I 1 I I I I I
1,10101,1,1010101
i
,8
.
,
0
0
PA,-CIAo
A
.
c{
PC 7-PC 4
O~.
PC]-PCa
D5
0.
PA 7..pAO
"
PC 7-PC.
,8
PSJ-PDa
CONTROL WORD .15
03
02
00
D,
I, 1 01 0 1,1, I I, I, I
I, I 0 I 0 I I I 10 I, I
0
,
,8
12C5IA
0,-0.
i
I
CONTROL WORD #13
06
,8
PCJ-PCo
PB7-PBO
07
i
I2C5IA
c{
,
I
I
.
.
,
A
PAr"Ao
c{
PC,-<'C.
PA]-PA O
I2CIUo
Pel,PC.
°l..[)O
PC 3-PC O
PCr"CO
P8, -PB O
PB 1:.pSo
231256-12
Mode 1 Basic functional Definitions:
Operating Modes
• Two Groups (Group A and Group B).
• Each group contains one 8·bit data port and one
4-bit control/data port.
• The 8-bit data port can be either input or output
Both inputs and outputs are latched.
MODE 1 (Strobed Input/Output). This functional
c~>nfiguration provides a means for transferring I/O
data to or from a specified port in conjunction with
strobes or "handshaking" signals. In mode 1, Port A
and Port B use the lines on Port C to generate or
accept these "handshaking" signals.
• The 4-bit port is used for control and status of the
8-bit data port.
6-96
inter
82C55A
Input Control Signal Definition
MODE 1 (PORT' AI
STB (Strobe Input). A "low" on this input loads
data into the input latch.
CONTROL WORD
07 D. 0 5 D. 0 3 02
a,
Do
I, I ·1, I, I'IO]XJ)@
IBF (Input Buffer Full F/F)
L~~~PUT
A "high" on this output indicates that the data has
been loaded into the input latch; in essence, an acknowledgement. IBF is set by STB in~ being low
and is reset by the rising edge of the RD input.
O-OUTPUT
INTR (Interrupt Request)
MODE 1 (PORT 81
A "high" on this output can be used to interrupt the
CPU when an input device is requesting service.
INTR is set by the STB is a "one", IBF is a "one"
and INTE is a "one". It is reset by the falling edge of
RD. This procedure allows an input device to request service from the CPU by simply strobing its
data into the port.
CONTROL WORD
07 D. Os D4 0, D2 0, Do
I'WXMXJ,I'M
IBFa
INT",
INTEA
Controlled by bit set/reset of PC4.
231256-13
INTEB
Controlled by bit set/reset of PC2.
Figure 8; MODE 1 Input
-'u-
~'"·-I.!
I.'
J
INTR
'IIT
\
tJ
~7
IIIi
INPUT FROM
PERIPHERAL
---
~""--I
...
! - · o.. _ _ _ o
'>
/
---------------------
Figure 9. MODE 1 (Strobed Input)
6-97
inter
82C55A
Output Control Signal Definition
MUDt. 1 IPORT AI
OBF (Output Buffer Full F/F). The OBF output will
go "low" to indicate that the CPU has written data
out to the specified port. The OBF F/F will be set by.
the rising edge of the WRinput and reset by ACK
Input being low.
CONTROL WORD
~ D.
Os
D4 0 3 02
I ' I I' I
0
0
"°, Do
I'~DMXI
L~'I=PUT
O-OUTPUT
ACK (Acknowledge Input). A "low" on this input
informs the 82C55A that the data from Port A or Port
B has been accepted. In essence, a response from
the peripheral device indicating that it has received
the data output by the CPU.
MODE 1 (PORT B)
INTR (Interrupt Request). A "high" on this output
can be used to interrupt the CPU when an output
device has accepted data transmitted by the CPU.
INTR is set when ACK is a "one", OBF is a "one"
and INTE is a "one". It is reset by the falling edge of
CONTROL WORD
0, D. 05 D. 0 3 02 D1 Do
1'N>®Xl'lo~
!!PI
WR.
INTEA
Controlled by bit set/reset of PCs.
INTEB
Controlled by bit set/reset of PC2.
INT"
231256-15
Figure 10. MODE 1 Output
INTH
1---twIT
OUTPUT
231256-16
Figure 11. MODE 1 (Strobed Output)
6-98
82C55A
Combinations of MODE 1
Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed
I/O applications.
PA,·PAg
PA,-PAc»
pc.
STB...
pc,
IBFA
PC,
INTRA
PC,
8
OBFA
pc. _ A C K...
PC,
INTRA
2
PCB•1
Pa.,-PBo
--f-- I/O
PC4•5
8
PB"PBo
RO-
PC a
I/O
INTR g
PORT A - (STROBED INPUT)
PORT B -(STROBED OUTPUTI
PC,
ST"
PC,
1BFa
pc.
INTRa
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
231256-17
Figure 12. Combinations of MODE 1
Operating Modes
Output Operations
MODE 2 (Strobed Bidirectional Bus I/O).This
functional configuration provides a means for com·
municating with a peripheral device or structure on a
single S·bit bus for both transmitting and receiving
data (bidirectional bus I/O). "Handshaking" signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1. Interrupt generation
and enable/disable functions are also available.
OBF (Output Buffer Full). The OBF output will go
"low" to indicate that the CPU has written data out
to port A.
ACK (Acknowledge). A "low" on this input enables
the tri-state output buffer of Port A to send out the
data. Otherwise, the output buffer will be in the high
impedance state.
MODE 2 Basic Functional Definitions:
INTE 1 (The INTE Flip-Flop Associated with
OBF). Controlled by bit set/reset of PC6.
• Used in Group A only.
• One S·bit, bi·directional bus port (Port A) and a 5bit control port (Port C).
Input Operations
• Both inputs and outputs are latched.
• The 5·bit control port (Port C) is used for control
and status for the S·bit, bi·directional bus port
(Port A).
STB (Strobe Input). A "low" on this input loads
data into the input I~tch.
IBF (Input Buffer Full F/F). A "high" on this output
indicates that data has been loaded into the input
latch.
Bidirectional Bus I/O Control Signal Definition
INTE 2 (The INTE Flip-Flop Associated with IBF).
Controlled by bit set/reset of PC4 .
INTR (Interrupt Request). A high on this output can
be used to interrupt the CPU for input or output operations.
6·99
82C55A
CONTROL WORD
~
~'~J~~T
PORTS
1'"" INPUT
0" OUTPUT
GROUP B MODE
O=MODEO
1=MODE1
231256-18
3
pc,. --1--110
RO-
Figure 13. MODE Control Word
231256-19
Figure 14. MODE 2
INTR
- t AK _
------------------~------------~~
~rr_----~--------
_ t ST _
~----------------~
r--~-+------r_----~------~
IBF
PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS
DATAFRDM
PERIPHERAL TO 8aC.SA
DATA FROM
82CS5A TO 8080
231256-20
Figure 15. MODE 2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK, and STB occurs before RD is permissible.
(INTR = IBF. MASK. STB • RD + OBF • MASK. ACK • WR)
6·100
inter
82C55A
MODE 2 AND MODE 0 (OUTPUT)
MODE 2 AND MODE 0 (INPUT)
P C e - A C KA
CONTROL WORD
CONTROL WORe
01 De 0 5 D. 03 02 01 Do
07 0 6 05 04 OJ 02 0, Do
I, I, txlXIX1 °I JOI
I, I, txlXIX1 °I0:]"1
pc,.
pc,.
1" INPUT
0" OUTPUT
1'" INPUT
0" OUTPUT
3
PCZ.Q
-f--
I/O
RD_
WR-
MODE 2 AND MODE 1 (OUTPUT)
MODE 2 AND MODE 1 (INPUT)
OBFA
CONTROL WORD
CONTROL WORD
ACK A
D7 0 6 Os 04 OJ 02 0, Do
PC,
rnA
pc,;
IBFA
l'I,t>
TEST POINTS
D••
<::
A.C. TESTING LOAD CIRCUIT
2.D
DEVICE
UNDER
TEST
D••
0.45
231256-29
I
Co. = 1SDpF
231256-30
A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V
For A Logic 0 Timing Measurements Are Made At 2.0V For A
Logic 1 And 0.8 For A Logic O.
'VEXT Is Set At Various Voltages During Testing To Guarantee
The Specification. CL Includes Jig Capacitance.
6-109
8256AH
MULTIFUNCTION MICROPROCESSOR
SUPPORT CONTROLLER
• Programmable Serial Asynchronous
Communications Interface .for 5-, 6-, 7-,
or 8-Bit Characters, 1, 1Y:z, or 2 Stop
Bits, and Parity Generation
•
Two 8-Bit Programmable Parallel I/O
Ports; Port 1 Can Be Programmed for
Port 2 Handshake Controls and Event
Counter Inputs
• On-Board Baud Rate Generator
Programmable for 13 Common Baud
Rates up to 19.2 KBits/Second, or an
External Baud Clock Maximum of 1M
Bit/Second
•
Eight-Level Priority Interrupt Controller
Programmable for 8085 or iAPX 86,
iAPX 88 Systems and for· Fully Nested
Interrupt Capability
•
Programmable System. Clock to 1
2 X, 3 X, or 5 X 1.024 MHz
• Five 8-Bit Programmable Timer/
Counters; Four Can Be Cascaded to
Two 16-Bit Timer/Counters
x,
The Intel® 8256AH Multifunction Universal Asynchronous Receiver-Transmitter (MUART) combines five commonly used functions into a single 40-pin device. It is designed to interface to the 8086/88, iAPX 186/188, and
8051 to perform serial communications, parallel I/O, timing, event counting, and priority interrupt functions. All
of these functions are fully programmable through nine internal registers. In addition, the five timer/counters
and two parallel I/O ports can be accessed directly by the microprocessor.
ADO-AD4
ADDRESSI
DATA
BUS
BUFFERS
DBS-DB7
cs
Rii
WI!
ALE
RESET
INT
ADO
Vee
ADI
Pl0
AD2
Pl1
. ·AD3
P12
AD~
P13
DBS
P14
DB8
PIS
DB7
P18
ALE
PH
Rii
P20
WR
P21
RESET
P22
CS
P23
INTA
P24
INT
P2S
EXTINT
P28
elK
P27
~
TxD
RxD
GND
230759-2
230759-1
Figure 1. MUART Block Diagram
6-110
Figure 2. MUART Pin
Configuration
September 1987
Order Number: 230759-002
inlef
8256AH
Table 1. Pin Description
Symbol
Pin
Type
Name and Function
ADO-AD4
DB5-DB7
1-5
6-8
I/O
ADDRESS/DATA: Three·state address/data lines which interface to the lower 8
bits of the microprocessor's multiplexed address/data bus. The 5·bit address is
latched on the falling edge of ALE. In the 8·bit mode, ADO-AD3 are used to select
the proper register, while AD1-AD4 are used in the 16·bit mode. AD4 in the 8-bit
mode is ignored as an address, while ADO in the 16cbit mode is used as a second
chip select, active low.
ALE
9
I
ADDRESS LATCH ENABLE: latches the 5 address lines on ADO-AD4 and CS
on the falling edge.
RD
10
I
READ CONTROL: When this signal is low, the selected register is gated onto the
data bus.
WR
11
I
WRITE CONTROL: When this signal is low, the value on the data bus is written
into the selected register.
RESET
12
I
RESET: An active high pulse on this pin forces the chip into its initial state. The
chip remains in this state until control information is written.
CS
13
I
CHIP SELECT: A Iowan this signal enables the MUART. It is latched with the
address on the falling edge of ALE, and RD and WR have no effect unless CS
was latched low during the ALE cycle.
INTA
14
I
INTERRUPT ACKNOWLEDGE: If the MUART has been enabled to respond to
interrupts, this signal informs the MUART that its interrupt request is being
acknowledged by the microprocessor. During this acknowledgement the MUART
puts an RSTn instruction on the data bus for the 8-bit mode or a vector for the 16bit mode.
INT
15
0
INTERRUPT REQUEST: A high signals the microprocessor that the MUART
needs service.
EXTINT
16
I
EXTERNAL INTERRUPT: An external device can request interrupt service
through this input. The input is level sensitive (high), therefore it must be held high
until an INTA occurs or the interrupt address. register is read.
ClK
17
I
SYSTEM CLOCK: The reference clock for the baud rate generator and the timers.
RxC
18
I/O
RECEIVE CLOCK: If the baud rate bits in the Command Register 2 are all 0, this
pin is an input which clocks serial data into the RxD pin on the rising edge of RxC.
If baud rate bits in Command Register 2 are programmed from 1-0FH, this pin
outputs a square wave whose rising edge indicates when the data on RxD is
being sampled. This output remains high during start, stop, and parity bits.
RxD
19
I
GND
20
PS
RECEIVE DATA: Serial data input.
GROUND: Power supply and logic ground reference.
6-111
inter
8256AH
Table 1. Pin Description (Continued)
Symbol
Pin
Type
Name and Function
CTS
21
I
CLEAR TO SEND: This input enables the serial transmitter. If 1,_
.1.5, or 2 stop bits are selected CTS is level sensitive. As long as
CTS is low, any character loaded into the transmitter buffer
register will be transmitted serially. A single negative going pulse
causes the transmission of a Single character previously loaded
into the transmitter buffer register. If a baud rate from 1...,OFH is
selected, CTS must be low for at least %2 of a bit, or it will be
ignored. If the transmitter buffer is empty, this pulse will be ignored.
If this pulse occurs during the transmission of a character up to the
time where % the first (or only) stop bit is sent out" it will be
ignored. If it occurs afterwards, but before the end of the stop bits,
the next character will be transmitted immediately following the
current one. If CTS is still high when the transmitter register is
sending the last stop bit, the transmitter will enter its idle state until
the next h1gh·to-low transition on CTS occurs. If 0.75 stop bits is
chosen, the CTS input is edge sensitive. A negative edge on CTS
results in the immediate transmission of the next character. The
length of the stop bits is determined by the time interval between
the beginning of the first stop bit and the next negative edge on
CTS. A high-to-Iow transition has no effect if the transmitter buffer
is empty or if the time interval between the beginning of the stop bit
and next negative edge is less than 0.75 bits. A high or a low level
or a low-to-high transition has no effect on the transmitter for the
0.75 stop bit mode.
TxC
22
I/O
TRANSMIT CLOCK: If the baud rate bits in command register 2
are all set.to 0, this input clocks data out of the transmitter on the .
falling edge. If baud rate bits are programmed for 1 or 2, this input
permits the user to provide a 32 x or 64 X clock which is used for
the receiver and transmitter. If the baud rate bits are programmed
for 3-0FH, the internal transmitter clock is output. As an output it
delivers the transmitter clock at the selected bit rate. If 1% or 0.75
stop bits are selected, the transmitter divider will be
asynchronously. reset at the beginning of each start bit,
immediately causing a high-toclow transition on TxC. TxC makes a
high-to-Iow transition at the beginning of each serial bit, and a lowto"high transition at the center of each bit.
23
0
P27-P20
24-31
I/O
PARALLEL 1/0 PORT 2: Eight bit general purpose 110 port. Each
nibble (4 bits) of this port can be either an input or an output. The
outputs are latched whereas the input signals are not. Also, this
port can be used as an 8-bitinput or output port when using the
two-wire handshake. In the handshake mode both inputs and
outputs are latched.
P17-P10
32-39
110
PARALLEL 1/0 PORT 1: Each pin can be programmed as an
input or an output to perform general purpose lID. All outputs are
latched whereas inputs are not. Alternatively these pins can serve
as control pins which extend the functional spectrum of the chip.
40
PS
POWER:
TxD
Vee
TRANSMIT DATA: Serial data output.
+ 5V power supply.
6-112
intJ
8256AH
FUNCTIONAL DESCRIPTION
The 8256AH Multi-Function Universal Asynchronous
Receiver-Transmitter (MUART) combines five commonly used functions into a single 40-pin device.
The MUART performs asynchronous serial communications, parallel I/O, timing, event counting, and
interrupt control. For detailed application information, see Intel AP Note # 153, Designing with the
8256.
Serial Communications
The serial communications portion of the MUART
contains a full-duplex asynchronous receiver-transmitter (UART). A programmable baud rate generator
is included on the MUART to permit a variety of operating speeds without external components. The
UART can be programmed by the CPU for a variety
of character sizes, parity generation and detection,
error detection, and start/stop bit handling. The receiver checks the start and stop bits in the center of
the bit, and a break halts the reception of data. The
transmitter can send breaks and can be controlled
by an external enable pin.
Parallel If0
The MUART includes 16 bits of general purpose parallel. I/O. Eight bits (Port 1) can be individually
changed from input to output or used for special I/O
functions. The other eight bits (Port 2) can be used
as nibbles (4 bits) or as bytes. These eight bits also
include a handshaking capability using two pins on
Port 1.
CounterfTimers
There are five 8-bit counter/timers on the MUART.
The timers can be programmed to use either a 1 kHz
or 16 kHz clock generated from the system clock.
Four of the 8-bit counter/timers can be cascaded to
two 16-bit counter/timers, and one of the 8-bit counter/timers can be reset to its initial value by an external signal.
Interrupts
An eight-level priority interrupt controller can be configured for fully nested or normal interrupt priority.
Seven of the eight interrupts service functions on
the MUART (counter/timers, UART), and one external interrupt is provided which can be used for a
particular function or for chaining interrupt controllers or more MUARTs. The MUART will support
8085 and 8086/88 systems with direct interrupt vectoring, or the MUART can be polled to determine the
cause of the interrupt. If additional interrupt control
capability is needed, the MUART's interrupt controller can be cascaded into another MUART, into an
Intel 8259A Programmable Interrupt Controller, or
into the interrupt controller of the iAPX 186/188
High-Integration Microprocessor.
INITIALIZATION
In general the MUART's functions are independent
of each other and only the registers and bits associated with a particular function need to be initialized,
not the entire chip. The command sequence is arbitrary since every register is directly addressable;
however, Command Byte 1 must be loaded first. To
put the device into a fully operational condition, it is
necessary to write the following commands:
Command byte 1
Command byte 2
Command byte 3
Mode byte
Port 1 control
Set Interrupts
The modification register may be loaded if required
for special applications; normally this operation is
not necessary. The MUART should be reset before
initialization. (Either a hardware or a software reset
will do.)
INTERFACING
This section describes the hardware interface between the 8256 MUART and the 80186 microprocessor. Figure 3 displays the block diagram for
this interface. The MUART can be interfaced to
many other microprocessors using these basic principles.
In all cases the 8256 will be connected directly to
the CPU's multiplexed address/data bus. If latches
or data bus buffers are used in a system, the
MUART should be on the microprocessor side olthe
address/data bus. The MUART latches the address
internally on the falling edge of ALE. The address
consists of Chip Select (CS) and four address lines.
For 8-bit microprocessors, ADO-AD3 are the address lines. For 16-bit microprocessors, AD1-AD4
are the address lines; ADO is used as a second chip
select which is active low. Since chip select is internally latched along with the address, it does not
have to remain active during the entire instruction
cycle. As long as the chip select setup and hold
times are met, it can be derived from multiplexed ad-
6-113
8256AH
Vee
n
r
16 MHz
r'D'l
X X RESET
1 2
RD
RES
WR
INTO
iNTAO
ALE
DTIR ---,
DEN --1
+ 5 V - SRDY
-r
r
NMI
ADII-15 'r
HOLD
~STB
~AIIORIDATA
-
n-
8282
"
ADDRESS
lATCH
(2) OE
+
PCSO
80186
8286
..A
DATA
TRCYR
(16)
~QE(2)
v
TI
'-
ALE
ADII-
(8)
-y'
05_/
cs
INTA INT WR
8256
>
rl.
CLOCK 11
GENERATOR
RD RESET ClK
PORT 1
PORT 2
CTS TxD RxD TxC RxC EX TINT
.
.1'-
(8)
(8)
.)
f f t
SERIAL 110
230759-3
Figure 3. 80186/8256 Interface
dress/data lines or multiplexed address/status
lines. When the 8256 is in the 16-bit mode, AO
serves as a second chip select. As a result the
MUART's internal registers will .all have even addresses since AO must be zero to select the device.
Normally the MUART will be placed on the lower
data byte. If the MUART is placed on the upper data
byte, the internal registers will be 512 address locations apart and the chip would occupy an 8k word
address space.
DESCRIPTION OF THE REGISTERS
The following section will provide a description of
the registers and define the bits within the registers
where appropriate. Table 2 lists the registers and
their addresses.
8086-8086 MODE ENABLE
This bit selects between 8085 mode and 8086/8088
mode. In 8085 mode (8086 = 0), AO to A3 are used
to address the internal registers, and an RSTn instn:lction is generated in response to the first INTA.
In 8086 mode (8086 = 1), A1 to A4 are used to
address the internal registers, and AO is used as an
extra chip select (AO must equal zero to be enabled).
The response to INTA is for 8086 interrupts where
the first INTA is ignored, and an interrupt vector
(40H to 47H) is placed on the-bus in response to the
second INTA.
BITI-INTERRUPT ON BIT CHANGE
Command Register 1
I L1 I LO I S1 I SO I BRKI I BITI I 8086 I FRO I
(OR)
cy is shared by all the counter/timers enabled for
timing; thus, all timers must run with the. same time
base.
(OW)
FRQ-TIMER FREQUENCY SELECT
This bit selects between two frequencies for the five
timers. If FRO = 0, the timer input frequency is
16 kHz (62.5 /1-s). If FRO = 1, the timer input frequency is 1 kHz (1 ms). The selected clock frequen-
This bit selects between one of two interruptsources on Priority Level 1, either Counter/Timer 2 or Port
1 P17 interrupt. When this bit equals 0, Counter/
Timer 2 will be mapped into Priority Level 1. If BITI
equals 0 and Level 1 interrupt is enabled, a transition from 1 to 0 in Counter/Timer 2 will generate
an interrupt request on Level 1. When BITI equals 1,
Port 1 P17 external edge triggered interrupt source
is mapped into Priority Level 1. In this case if Level 1
is enabled, a low-Io-high transition on P17 generates
an interrupt request on Level 1.
6-114
inter
8256AH
Table 2. MUART Registers
Read Registers
Write Registers
8085 Mode: AD3
8086 Mode: AD4
'I-Ll-.-LO......
1 -SI--rIso-'I-BR-K-C
1 I'---B-ITI--r-SO-S-6'I-FR----'OI 0
0
AD2
AD3
0
AD1
AD2
0 'I-L1......
1 -Lo--rIS1-'I-s-0'I-BR-K-I'I-B-ITI--r-S-OS-6'I-F-RO-'I
Command 1
I PEN I EP I C1 I CO I
B3
Command 1
I
B2
I
Bl
I BO I 0
0
0
1 I PEN I EP I Cl I CO I
Command 2
I 0
I RxE IIAE I NIE I
0
ADO
AD1
I SBRK I TBRK I
0
I 0
0
1
0
1
P12
Pl1
I P10 I 0
1
0
0 1 P171 P161 P151 P141/ P13 1 P12
Port 1 Control
I
L2
ILl
I LO I 0
BO
I
1
0
1 I L7 I L6 I L5 I L4 I
1
1
0 I L7 I L6 I LS I L4 I
Interrupt Address
I
P11
I P10 I
L3
I
L2
ILl
LO
L2
ILl
LO
02
01
DO
Set Interrupts
L.I0_7-,1_0_6-,1_0_5-1.1_0_4-,-1_0_3-,1_0_2-,--_0_1-,1_0---,0I 0
L3
I
Reset Interrupts
01
02
I I
DO
0
1 1 07 I 06 I 05 I 04 I
1
Receiver Buffer
03
I
Transmitter Buffer
1....10_7--,1_0_6....J.1_0_5....1.1_0_4 -1.1_0_3--,1_0_2--,--_0_1....J.1_0---,0I 1
0
0
0 1 D7 I 06 I 05 I 04 I
Port 1
03
I
02
01
DO
I
02
01
DO
I
02
01
DO
I
02
01
DO
I
02
01
DO
I
02
01
DO
I
02
01
DO
Port 1
1....1D_7--,1_0_6....J.1_0_5....1.1_0_4-1.1_0_3--,1_0_2--,--_01---1.1_0---,011
0
0
1 107 I 06 I 05 I 04 I
Port 2
03
I
Port 1 Control
Interrupt Enable
I 07 I 06 I OS I 04 I
B1
Mode
I P171 P161 P151 P141 P13 I
03
I
1 1 T3S I T24 I TSC I CT3 I CT2 I P2C2 I P2C1 I P2CO I
Mode
I 07 I 06 I 05 I 04 I
B2
Command 3
I T35 I T24 I T5C I CT3 I CT2 I P2C2 I P2Cl I P2CO I 0
L3
I
0 1 SET I RxE IIAE I NIE I END I SBRK I TBRK I RST I
Command 3
I L7 I L6 I LS I L4 I
B3
Command 2
03
Port 2
I
02
I
01
I DO I 1
0
1
0 1 07 I 06 I OS I 04 I
1....10_7--,1_0_s....I.I_0_5-,-I_D_4-1.1_0_3......11_02--,_01--,1_0---,011
0
1
1
I 07
Timer 2
I 06 I OS I 04 I
03
Timer 2
1....10_7--'1_0_s....l.I_0_S-'-I_0_4-1.1_0_3......11_02--'_01----'1_0---'011
1
0
0
I 07
I OS I OS I 041
03
Timer 3
Timer 3
LI0_7-'I_O--'s.....I.1_0_5-'-1_0_4-'-1_0_3-'1_02-----'_01-----'1_0---'011
1
0
1
I 07
Timer 4
los I OS I 04 I
03
Timer 4
01
I DO 11
1
0 I 07 I 06 I OS I 04 I
03
Timer 5
TimerS
liNT I RBF I TBE I TRE I BO I
03
Timer 1
Timer 1
PE
OE
1 I
I FE 11
Status
0
I RS41 RS31 RS21 RS1 I RSO
Modification
6-115
TME I OSC I
8256AH
BRKI-BREAK-IN DETECT ENABLE
If this bit equals 0, Port 1 P16 is a general purpose II
When BRKI equals 1, the Break-In Detect
feature is enabled on Port 1 P16. A Break-In condition is present on the transmission line when it is
forced to the start bit voltage level by the receiving
station. Port 1 P16 must be connected externally to
the transmission line in order to detect a Break-In. A
Break-In is polled by the MUART during the transmission of the last or only stop bit of a character.
o port.
A Break-In Detect is OR-ed with Break Detect in Bit
3 of the Status Register. The distinction can be
made through the interrupt controller. If the transmit
and receive interrupts are enabled, a Break-In will
generate an interrupt on Level 5, the transmit interrupt, while Break will generate an interrupt on Level
4, the receive interrupt.
so,
provide a frequency of either 32X ,or 64X the baud
rate. The data transmission rates range from O... 32
Kbaud.
If bits 0 ... 3 are set to 0, separate clocks must be
input to pin RxC for the receiver and pin TxC for the
transmitter. Thus, different baud rates can be used
for transmission and reception. In this case, prescalers are disabled and the input serial clock frequency must match the baud rate. The input serial
clock frequency can range from 0 MHz to 1.024
MHz.
BO, B1, B2, B3-BAUD RATE SELECT
These four bits select the bit clock's source, sampling rate, and serial rate for the internal baud rate
generator.
.
S1-STOP BIT LENGTH
Stop Bit Length
S1
SO
0
0
1
0
1
1.5
1
0
2
1
1
0.75
The relationship of the number of stop bits and the
function of input CTS is discussed in the Pin Description section under "CTS".
LO, L 1-CHARACTER LENGTH
L1
LO
Character Length
0
0
8
0
1
7
1
0
6
1
1
5
(1 R)
B2
B1
BO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
a
1
1
0
0
1
1
0
1
0
1
0
1
0
1
'0
1
0
1
0
1
0
1
0
1
1
1
1
Bits 3 to
o(Hex.)
0
B2
a
Baud
Rate
TxC,RxC
TxC/64
TxC/32
19200
9600
4800
2400
1200
600
300
200
150
110
100
75
50
Sampling
Rate
1
64
32
32
64
64
64
64
64
64
64
64
64
64
64
64
The following table gives an overview of the function
of pins TxC and RxC:
Command Register 2
I PEN I EP I C1 I CO I B3
B3
B1
BO
(1W)
1,2
Programming bits 0 ... 3 with values from 3H to FH
enables the internal baud rate generator as a common clock source for the transmitter and receiver
and determines its divider ratio.
Programming bits 0 ... 3 with values of 1H or 2H
enables input TxC as a common clock source for the
transmitter and receiver. The external clock must
6-116
3to F
TxC
RxC
Input: 1 x baud
rate clock for the
transmitter
Input: 32 X or
64 X baud rate '
for transmitter
and receiver
Input: 1 x baud
rate clock for the
receiver
Output: receiver bit
clock with a low-tohigh transition at
data bit sampling
time. Otherwise:
high level
Output: as above
Output: baud rate
clock of the
transmitter
inter
8256AH
As an output, RxC outputs a low-to-high transition at
sampling time of every data bit of a character. Thus,
data can be loaded, e.g., into a shift register externally. The transition occurs only if data bits of a character are present. It does not occur for start, parity,
and stop bits (RxC = high).
As an output, TxC outputs the internal baud rate
cio"ck of the transmitter. There will be a high-to-Iow
transition at every beginning of a bit.
CO, C1-SYSTEM CLOCK PRESCAlER (BITS 4,
5)
Bits 4 and 5 define the system clock prescaler divider ratio. The internal operating frequency of
1.024 MHz is derived from the system clock.
C1
CO
Divider Ratio
Clock at Pin
ClK
0
0
5
5.12 MHz
0
1
3
3.072 MHz
1
0
2
2.048 MHz
1
1
1
1.024 MHz
any bits which were high. If any bit 0-6 is low, no
change occurs to that bit. When command Register
3 is read, bits 0, 3, and 7 will always be zero.
RST-RESET
If RST is set, the following events occur:
1. All bits in the Status Register except bits 4 and 5
are cleared, and bits 4 and 5 are set.
2. The Interrupt Enable, Interrupt Request, and Interrupt Service Registers are cleared. Pending requests and indications for interrupts in service will
be cancelled. Interrupt signal INT will go low.
3. The receiver and transmitter are reset. The transmitter goes idle (TxD is high), and the receiver
enters start bit search mode.
4. If Port 2 is programmed for handshake mode, IBF
and OBF are reset high.
RST does not alter ports, data registers or command
registers, but it halts any operation in progress. RST
is automatically cleared.
RST = 0 has no effect. The reset operation triggered by Command Register 3 is a subset of the
hardware reset.
EP-EVEN PARITY (BIT 6)
TBRK-TRANSMIT BREAK
EP = 0: Odd parity
EP = 1: Even parity
The transmission data output TxD will be set low as
soon as the transmission of the previous character
has been finished. It stays low until TBRK is cleared.
The state of CTS is of no significance for this operation. As long as break is active, data transfer from
the Transmitter Buffer to the Transmitter Register
will be inhibited. As soon as TBRK is reset, the break
condition will be deactivated and the transmitter will
be re-enabled.
PEN-PARITY ENABLE (BIT 7)
Bit 7 enables parity generation and checking.
PEN
PEN
=
=
0: No parity bit
1: Even parity bit
The parity bit according to Command Register 2 bit 6
(see above) is inserted between the last data bit of a
character and the first or only stop bit. The parity bit
ischecked during reception. A false parity bit generates an error indication in the Status Register and an
Interrupt Request on Level 4.
Command Register 3
ISET IRxE IIAE I NIW I END I SBRK I TBRK I RST I
(2R)
(2W)
Command Register 3 is different from the first two
registers because it has a bit set/reset capability.
Writing a byte with Bit 7 high sets any bits which
were also high. Writing a byte with Bit 7 low resets
SBRK-SINGlE CHARACTER BREAK
This causes the transmitter data to be set low for
one character including start bit, data bits, parity bit,
and stop bits. SBRK is automatically cleared when
time for the last data bit has passed. It will start after
the character in progress completes, and will delay
the next data transfer from the Transmitter Buffer to
the Transmitter Register until TxD returns to an idle
(marking) state. If both TBRK and SBRK are set,
break will be set as long as TBRK is set, but SBRK
will be cleared after one character time of break. If
SBRK is set again, it remains set for another character. The user can send a definite number of break
characters in this manner by clearing TBRK after
setting SBRK for the last character time.
6-117
8256AH
P2C2,P2C1, P2Co-PORT 2 CONTROL
END-END OF INTERRUPT
If fully nested interrupt mode is selected, this bit resets the currently served interrupt level in the Interrupt Service Register. This command must occur at
P2C2 P2C1 P2CO
the end of each interrupt service routine during fully
nested interrupt mode. END is automatically cleared
when the Interrupt Service Register (internal) is
cleared. END is ignored if nested interrupts are not
enabled.
NIE-NESTED INTERRUPT ENABLE
Mode
Direction
Upper Lower
a
a
a
a
a
a
a
Nibble
Input
Input
1
Nibble
Input
Output
1
a
Nibble
Output
Input
1
1
Nibble
Output Output
1
a
a
Byte
Handshake
Input
1
a
1
Byte
Handshake
Output
1
1
a
1
1
1
When NIE equals 1, the interrupt controller will operate in the nested interrupt mode. When NIE equals
0, the interrupt controller will operate in the normal
interrupt mode. Refer to the "Interrupt controller"
section of AP-153 under "Normal Mode" and "Nested Mode" for a detailed description of these operations.
NOTE:
IAE-INTERRUPT ACKNOWLEDGE ENABLE
If Port 2 is operating in handshake mode, Interrupt Level 7
is not available for Timer 5. Instead it is assigned to Port 2
:handshaking.
This bit enables an automatic response to INTA. The
particular response is determined by the 8086 bit in
Command Register 1.
DO NOT USE
Test
CT2, CT3-COUNTER/TIMER MODE
Bit 3 and 4 defines the mode of operation of event
counter/timers 2 and 3 regardless of its use as a
single unit or as a cascaded one.
RxE-RECEIVE ENABLE
This bit enables the serial receiver and its associated status bits in the status register. If this bit is reset,
the serial receiver will be disabled and the receive
status bits will not be updated.
Note that the detection of break characters remains
enabled while the receiver is disabled; i.e., Status
Register Bit 3 (BO) will be set while the receiver is
disabled whenever a break character has been recognized at the receive data input RxO.
If CT2 or CT3 are high, then counter/timer 2 or 3
respectively is configured as an event counter on bit
2 or 3 respectively of Port 1 (pins 37 or 36). The
event counter decrements the count by one on each
low-to-high transition of the external input. If CT2 or
CT3 is low, then the respective counter/timer is configured as a timer and the Port 1 pins are used for
parallel I/O.
T5C-TIMER 5 CONTROL
SET-BIT SET/RESET
If this bit is high during a write to Command Register
3, then any bit marked by a high will set. If this bitis
low, then any bit marked by a high will be cleared.
MODE REGISTER
IT351 T241 T5C ICT31 CT21 P2C21 P2C1 IP2CO I
(3R)
(3W)
If test mode is selected, the output from the internal
baud rate generator is placed on bit 4 of Port 1 (pin
35).
To achieve this, it is necessary to program bit 4 of
Port 1 as an output (Port 1 Control Register Bit P14
= 1), and to program Command Register 2 bits B3BO with a value :? 3H.
If T5C is set, then Timer 5 can be preset and started
by an external signal. Writing to the Timer 5 register
loads the Timer 5 save register and stops the timer.
A high-to-Iow transition on bit 5 of Port 1 (pin 34)
loads the timer with the saved value and starts the
timer. The next high-to-Iow transition on pin 34 re:
triggers the timer by reloading it with the initial value
and continues timing.
Following a hardware reset, the save register is reset to OOH and both clock and trigger inputs are disabled. Transferring an instruction with T5C = 1 en c
abies the trigger input; the save register can now be
loaded with an initial value. The first trigger pulse
causes the initial value to be loaded from the save
register and enables the counter to count down to
zero.
When the timer reaches zero it issues an interrupt
request, disables its interrupt level and continues
6-118
inter
8256AH
counting. A subsequent high-to-Iow transition on pin
5 resets Timer 5 to its initial value. For another timer
interrupt, the Timer 5 interrupt enable bit must be set
again.
Single event counters/timers generat~ an interrupt
request on the transition from 01 H to OOH, while cascaded ones generate it on the transition from 0001 H
to OOOOH.
T35, T24-CASCADE TIMERS
Port 1 Control Register
IP17 I P16 I P15 I P14 I P13 I P12 I P11 I P10 I
These two bits cascade Timers 3 and 5 or 2 and 4.
Timers 2 and 3 are the lower bytes, while Timers 4
and 5 are the upper bytes. It T5C is set, then both
Timers 3 and 5 can be preset and started by an
external pulse.
When a high-to-Iow transition occurs, Timer 5 is preset to its saved value, but Timer 3 is always preset to
all ones. If either CT2 or CT3 is set, then the corresponding timer pair is a 16-bit event counter.
A summary of the counter/timer control bits is given
in Table 3.
NOTE:
Interrupt levels assigned to single counters are
partly not occupied if event counters/timers are
cascaded. Level 2 will be vacated if event counters/timers 2 and 4 are cascaded. Likewise, Level
7 will be vacated if event counters/timers 3 and 5
are cascaded;
(4R)
(4W)
Each bit in the Port 1 Control Register configures the
direction of the corresponding pin. If the bit is high,
the pin is an output, and if it is low the pin is an input.
Every Port 1 pin has another function which is controlled by other registers. If that special function is
disabled, the pin functions as a general I/O pin as
specified by this register. The special functions for
each pin are described below.
Port 10, 11-HANDSHAKE CONTROL
If byte handshake control is enabled for Port 2 by
the Mode Register, then Port 10 is programmed as
STB/ ACK handshake control input, and Port 11 is
programmed as IBF/OBF handshake control output.
If byte handshake mode is enabled for output on
Port 2 OBF indicates that a character has been loaded into the Port 2 output buffer. When an external
Table 3. Event Counters/Timers Mode of Operation
Event Counter/
Timer
1
2
2
4
5
2 and4
cascaded
3 and"5
cascaded
Programming
(Mode Word)
Function
-
8-bittimer
8-bit timer
8-bit event counter
8-bit timer
8-bit event counter
8-bittimer
8-bit timer,
normal mode
8-bit timer,
retriggerable mode
16-bit timer
16-bit event counter
16-bit timer,
normal mode
16-bit event counter,
normal mode
16-bit timer,
retrig"gerable mode
=
=1
0, CT3 =
0, CT3 = 1
Internal clock
Internal clock
P12 pin 37
Internal clock
P13 pin 36
Internal clock
Internal clock
T24
T35
T35
= 0, T5C = 1
Internal clock
T24
T24
T35
CT3
T35
CT3
T35
CT3
T35
CT3
= 1, CT2
= 1, CT2
= 1, T5C
=
= 1, T5C
= 1
= 1, T5C
=
= 1, T5C
= 1
=0
= 1
= 0,
Internal clock
P12 pin 37
Internal clock
= 0,
P13 pin 36
= 1,
Internal clock
= 1,
P13 pin 36
T35
T35
6-119
°
°
=
=
=
=
=
=
T24
T24
16-bit event counter,
retriggerable mode
Clock Source
0, CT2
0, CT2
°
0, T5C
°
°
=
°
8256AH
device reads the data, it acknowledges this operation by driving ACK low. OBF is set low by writing to
Port 2 and is reset by ACK.
Interrupt Enable Register
I L7 I L6. I L5 I L4 I L3 I L2
If ~handshake mode is enabled for input on Port
2, STB is an input. IBF is driven low after STB goes
low. On the rising edge of STB the data from Port 2
is latched.
IBF is reset high when Port 2 is read.
PORT 12, 13-COUNTER 2, 3 INPUT
If Timer 2 or Timer 3 is programmed as an event
counter by the Mode Register, then Port 12 or Port
13 is the counter input for Event Counter 2 or 3,
respectively.
Priority
Highest
If test mode is enabled by the Mode Register and
Command Register 2 baud rate select is greater
than 2, then Port 14 is an output from the internal
baud rate generator.
LO
L1
L2
L3
L4
L5
L6
L7
Lowest
Source
Timer 1
Timer 2 or Port Interrupt
External Interrupt (EXTINT)
Timer 3 or Timers 3 & 5
Receive Interrupt
Transmitter Interrupt
Timer 4 or Timers 2 & 4
Timer 5 or Port 2 Handshaking
Interrupt Address Register
101010lo41oUJ1o
. (SR)
PORT 15-TIMER 5 TRIGGER
,I
0 I
Interrupt Level
Indication
230759-4
If T5C is set in the Mode Register enabling a retriggerable timer, then Port 15 is the input which starts
and reloads Timer 5.
A high-to-Iow transition on P15 (Pin 34) loads the
timer with the slave register and starts the timer.
PORT 16-BREAK-IN DETECT
If Break-In Detect is enabled by BRKI in Command
Register 1, then this input is used to sense a BreakIn. If Port 16 is low while the serial transmitter is
sending the last stop bit, then a Break-In condition is
signaled.
.
Reading the interrupt address register transfers an
identifier for the currently requested interrupt level
on the system data bus. This identifier is the number
of the interrupt level multiplied by 4. It can be used
by the CPU as an offset address for interrupt handling. Reading the interrupt address register has the
same effect as. a hardware interrupt acknowledge'
INTA; it clears the interrupt request pin (INT) and
indicates an interrupt acknowledgem.ent to the interrupt controller.
Receiver and Transmitter Buffer
I 07 I 06 I 05 I 04 I 03 I· 02 I 01 I DO
PORT 17-PORT INTERRUPT SOURCE
(7R)
If BITI in Command Register 1 is set, then a low-tohigh transition on Port 17 generates an interrupt request on Priority Level 1.
Port 17 is edge triggered.
LO
Interrupts are enabled by writing to the Set Interrupts
Register (5W). Interrupts are disabled by writing to
the Reset Interrupts Register (6W). Each bit set by
the Set Interrupts Register (5W) will enable that level
interrupt, and each bit set in the Reset Interrupts
Register (6W) will disable that level interrupt. The
user can determine which interrupts are enabled by
reading the Interrupt Enable Register (5R).
PORT 14-BAUD RATE GENERATOR OUTPUT
CLOCK
P14 in Port 1 control register must be set to 1 for the
baud . rate generator clock to be output. The baud
rate generator clock is 64 x the serial bit rate excet
at 19.2 Kbps when it is 32 x the bit rate.
L1
(5W = enable,
6W = disable)
(5R)
(7W)
Both the receiver and transmitter in the MUART are
double buffered. This means that the transmitter and
receiver have a shift register and a buffer register.
The buffer registers are directly addressable by
reading or writing to register seven. After the receiver buffer is full, the RBF bit in the status register is
set.
6-120
inter
8256AH
Reading the receive buffer clears the RBF status bit.
The transmit buffer should be written to only if the
TBE bit in the status register is set. Bytes written to
the transmit buffer are held there until the transmit
shift register is empty, assuming CTS is low. If the
transmit buffer and shift register are empty, writing to
the transmit buffer immediately transfers the byte to
the transmit shift register. If a serial character length
is less than a bits, the unused most significant bits
are set to zero when reading the receive buffer, and
are ignored when writing to the transmit buffer.
Port 1
07
06
05
04
03
(SR)
02
01
05
04
03
(9R)
02
01
DO
(9W)
Writing to Port 2 sets the data in the Port 2 output
latch. Writing to an input pin does not affect the pin,
but it does store the data in the latch. Reading Port 2
puts the input pins onto the bus or the contents of
the output latch for output pins.
Timer 1...;.5
I 07 I 06 I 05
04
03
02
01
liNT
I RBF I TBE I TRE I BO I PE I OE I FE I
(OF16R)
Reading the status register gates its contents onto
the data bus. It holds the operational status of the
serial interface as well as the status of the interrupt
in INT. The status register can be read at any time.
The flags are stable and well defined at all instants.
. FE-FRAMING ERROR, TRANSMISSION MODE
(aw)
Port 2
06
Status Register
DO
Writing to Port 1 sets the data in the Port 1 output
latch. Writing to an input pin does not affect the pin,
but the data is stored and will be output if the direc,tion of the pin is changed later. If the pin is used as a
control signal, the pin will not be affected, but the
data is stored. Reading Port 1 transfers the data in
Port 1 onto the data bus.
07
The timer/counter interrupts are automatically disabled when the interrupt request is generated.
DO
Bit 0 can be used in two modes. Normally, FE indicates framing error which can be changed to transmission mode indication by setting the TME bit in the
modification register.
If transmission mode is disabled (in Modification
Register), then FE indicates a framing error. A framing error is detected during the first stop bit. The
error is reset by reading the Status Register or by a
chip reset. A framing error does not inhibit the loading of the Receiver Buffer. If RxO remains low, the
receiver will assemble the next character. The false
stop bit is treated as the next start bit, and no highto-low transition on RxO is required to synchronize
the receiver.
When the TME bit in the Modification Register is set,
FE is used to indicate that the transmitter was active
during the reception of a character, thus· indicating
that the character received was transmitted by its
own transmitter. FE is reset when the transmitter is
not active during the reception of character. Reading
the status register will not reset the FE bit in the
transmission mode.
Reading Timer N puts the contents of the timer onto
the da~a bus. If the counter changes while RO is low,
the value on the data bus will not change. If two
timers are cascaded, reading the high-order byte will
cause the low-order byte to be latched. Reading the
low-order byte will unlatch them both. Writing to either timer or decascading them also clears the latch
condition. Writing to a timer sets the starting value of
that timer. If two timers are cascaded, writing to the
high-order byte presets the low-order byte to all
ones. Loading only the high-order byte with a value
of X leads to a count of X *256 + 255. Timers count
down continuously. If the interrupt is enabled, it occurs when the counter changes from 1 to o.
6-121
OE-OVERRUN ERROR
If the user does not read the character in the Receiver Buffer before the next character is received
and transferred to this register, then the OE bit is
set. The OE flag is set during the reception of the
first stop bit and is cleared when the Status Register
is read or when a hardware or software reset occurs.
The first character received in this case will be lost.
PE-PARITY ERROR
This bit indicates a parity error has occurred during
the reception of a character. A parity error is present
inter
8256AH
if value of the parity bit in the received character is
different from the one expected according to command word 2 bits 6 EP. The parity bit is expected
and checked only if it is enabled by command word
2 bit 7 PEN.
A parity error is set during the first stop bit and is
reset by reading the Status Register or by a chip
reset.
TBE-TRANSMITTER BUFFER EMPTY
TBE indicates the Transmitter Buffer is empty and is
ready to accept a character. TBE is set by a chip
reset or the transfer of data to the Transmitter Register, and is cleared when a character is written to
the transmitter buffer. When TBE is set, an interrupt
request is generated on Level 5 if enabled.
RBF-RECEIVER BUFFER FULL
BD-BREAK/BREAK-IN
The BD bit flags whether a break character has
been received, or a Break-In condition exists on the
transmission line. Command Register 1 Bit 3 (BRKI)
enables the Break-In Detect function.
Whenever a break character has been received,
Status Register Bit 3 will be set and in addition an
interrupt request on Level 4 is generated. The receiver will be idled. It will be started again with the
next high-to-Iow transition at pin RxD.
The break character received will not be loaded into
the receiver buffer register.
If Break-In Detection is enabled and a Break-In condition occurs, Status Register Bit 3 will be set and in
addition an interrupt request on Level 5 is generated.
.
The BD status bit will be reset on reading the status
register or on a hardware or software reset. For
more information on Break/Break-In, refer to the
"Serial Asynchronous Communication" section of
AP-153 under "Receive Break Detect" and "BreakIn Detect."
RBF is set when the Receiver Buffer has been loaded with a new character during the sampling of the
first stop bit. RBF is cleared by reading the receiver
buffer or by a chip reset.
INT-INTERRUPT PENDING
The INT bit reflects the state of .the INT Pin (Pin 15)
and indicates an interrupt is pending. It is reset by
INTA or by reading the Interrupt Address Register if
only one interrupt is pending and by a chip reset.
FE, DE, PE, RBF, and Break Detect all generate a
Level 4 interrupt when the receiver samples the first
stop bit. TRE, TBE, and Break-In Detect generate a
Level 5 interrupt. TRE generates an interrupt when
TBE is set and the Transmitter Register finished
transmitting. The Break-In Detect interrupt is issued
at the same time as TBE or TRE.
MODIFICATION REGISTER
o I RS41
RS3
IRS2 IRS1 IRSO ITME IDSC I
(OF16W)
DSC-DISABLE START BIT CHECK
TRE-TRANSMIT REGISTER EMPTY
When TRE is set the transmit register is empty and
an interrupt request is generated on Level 5 if enabled. When TRE equals O.the transmit register is in
the process of sending data. TRE is set by a chip
reset and when the last stop bit has left the transmitter. It is reset when a character is loaded into the
Transmitter Register. If CTS is low, the Transmitter
Register will be loaded during the transmission of
the start bit. If CTS is high at the end of a character,
TRE will remain high and no character will be loaded
into the Transmitter Register until CTS goes low. If
the transmitter was inactive before a character is
loaded into the Transmitter Buffer, the Transmitter
Register will be empty temporarily while the buffer is
full. However, the data in the buffer will be transferred to the transmitter register immediately and
TRE will be cleared whileTBE is set.
DSC disables the receivers start bit check. In this
state the receiver will not be reset if RxD is not low
at the center of the start bit.
TME-TRANSMISSION MODE ENABLE
TME enables transmission mode and disables framing error detection. For information on transmission
mode see the description of the framing error bit in
the status register.
RSO, RS1, RS2, RS3, RS4-RECEIVER SAMPLE
TIME
The number in RSn alters when the receiver samples RxD. The receiver sample time can be modified
only if the receiver is not clocked by RxC.
6-122
8256AH
NOTE:
The modification register cannot be read. Reading
from address OFH, 8086: 1EH gates the contents
of the status register onto the data bus.
Reset has no effect on the contents of receiver buffer register, transmitter buffer register, the intermediate latches of parallel ports, and event counters/timers, respectively.
A hardware reset (reset, Pin 12) resets all modification register bits to 0, Le.:
• The start bit check is enabled.
• Status Register Bit 0 (FE) indicates framing error.
• The sampling time of the serial receiver is the bit
center.
A software reset (Command Word 3, RST) does not
affect the modification register.
Hardware Reset
A reset signal on pin RESET (HIGH level) forces the
device 8256 into a well-defined initial state. This
state is characterized as follows:
1) Command registers 1, 2 and 3, mode register,
Port 1 control register, and modification register
are reset. Thus, all bits of the parallel interface
are set to be intputs and event counters/timers
are configured as independent 8-bit timers.
2) Status register bits are reset with the exception of
bits 4 and 5. Bits 4 and 5 are set indicating that
both transmitter register and transmitter buffer
register are empty.
3) The interrupt mask, interrupt request, and interrupt service register bits are reset and disable all
requests. As a consequence, interrupt signal INT
IS INACTIVE (LOW).
4) The transmit data output is set to the marking
state (HIGH) and the receiver section is disabled
until it is enabled by Command Register 3 Bit 6.
5) The start bit will be checked at sampling time.
The receiver will return to start bit search mode if
input RxD is not LOW at this time.
6) Status Register Bit 0 implies framing error.
7) The receiver samples input RxD at bit center.
6-123
Point of Time Between
Start of Bit and End of
RS4 RS3 RS2 RS1 RSO
Bit Measured in Steps
of %2 Bit Length
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 (Start of Bit)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (Bit center)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 (End of Bit)
8256AH
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O°C to 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin
with Respect to Ground .......... - 0.5V to + 7V
Power Dissipation ........................... 1W
'Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
NOTICE Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS
Symbol
TA = 0°Ct070°C, Vee = +5.0V ±10%
Min
Max
Units
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
IlL
Input Leakage
10
-10
JkA
JkA
VIN = Vee
VIN = OV
ILO
Output Leakage
10
-10
JkA
JkA
VOUT
VOUT
lee
Vee Supply Current
160
mA
CIN
Input Capacitance
10
pF
fc
ClIO
I/O Capacitance
20
pF
Unmeasured
Pins Returned to
VSS(1)
VIL
Parameter
Test Conditions
IOL = 2.5 mA
V
2.4
IOH = - 400 JkA
= Vee
= 0.45V
= 1 MHz(1)
NOTE:
1. Sampled, not 100% tested. TA = 25°e.
A.C. CHARACTERISTICS
Symbol
TA
= O°C to 70°C, Vee = + 5.0V -+ 10%, GND = OV
8256AH
Parameter
Min
Max
I
Units
BUS PARAMETERS
tLL
ALE Pulse Width
50
ns
tesL
CS to ALE Setup Time
0
ns
tAL
Address to ALE Setup Time
20
ns
tLA
Address Hold Time after ALE
25
ns
tLe
ALE to RD/WR
20
ns
tee
RD, WR, INTA Pulse Width
200
ns
tRD
Data Valid from RD(1)
120
6-124
ns
intJ
8256AH
A.C. CHARACTERISTICS
TA
= O°C to 70°C, VCC = + 5.0V ± 10%, GND = OV (Continued)
8256AH
Symbol
Parameter
Min
Units
Max
BUS PARAMETERS (Continued)
50
ns
tOF
Data Float after RD (2)
tow
Data Valid to WR
150
two
Data Valid after WR
50
ns
tCl
RD/WR Control to Latch Enable
25
ns
tLDR
ALE to Data Valid
tRST
Reset Pulse Width
300
ns
tRY
Recovery Time between RD/WR
500
ns
ns
150
ns
TIMER/COUNTER PARAMETERS
tCPI
Counter Input Cycle Time (P12, P13)
2.2
fLs
tCPWH
Counter Input Pulse Width High
1.1
fLs
tCPWL
Counter Input Pulse Width Low
1.1
tTPI
Counter Input i to INT i at Terminal Count
fLs
2.75
fLs
tTIH
LOAD Pulse High Time Counter 5
1.1
fLs
tTll
LOAD Pulse Low Time Counter 5
1.1
fLs
tpp
Counter 5 Load before Next Clock Pulse on P13
tCR
External Count Clock i to RD
Reflected in Count
tRC
RD i to External Count Clock i to Ensure Clock
is not Reflected in Count
tcw
External Count Clock i to WR
Written is Not Decremented
twc
WR i to External Count Clock to Ensure Count
Written is Decremented
t
i
to Ensure Clock is
to Ensure Count
1.1
fLs
2.2
fLs
0
ns
2.2
fLs
0
ns
INTERRUPT PARAMETERS
tOEX
EXTINT i to INT i
200
tOPI
Interrupt Request on P17 i to INT i
tpi
Pulse Width of Interrupt Request on P17
tHEA
INTA i or RD i to EXTINT
tHIA
INTA i or RD i to INT
2tCy+500
t
ns
ns
tCY+ 100
30
t
ns
ns
~
300
fLs
1000
ns
SERIAL INTERFACE AND CLOCK PARAMETERS
tCY
Clock Period
195
tCLKH
Clock High Pulse Width
65
ns
tClKl
Clock Low Pulse Width
65
ns
tR
Clock Rise Time
20
ns
tF
Clock Fall Time
20
ns
6-125
inter
8256AH
A.C. CHARACTERISTICS T A = O°C to 70°C , VCC = + 5 OV +
- 10% GND = OV (Continued)
Symbol
8256AH
Parameter
Min
Units
Max
SERIAL INTERFACE AND CLOCK PARAMETERS (Continued)
tSCY
Serial Clock Period (4)
975
ns
tspo
Serial Clock High (4)
350
ns
tspw
Serial Clock Low (4)
350
ns
tSTD
Internal Status Update Delay from Center of
Stop Bit (5)
300
ns
tOTX
TxC to TxD Data Valid
300
ns
tlRSF
INT Delay from Center of First Stop Bit
2tCy+500
ns
tlTSE
INT Delay from Falling Edge of Transmit Clock at
End of Start Bit
2tCy+500
ns
tCTS
Pulse Width for Single Character Transmission
0
ns
(6)
PARALLEL 1/0 PORT PARAMETERS
twp
WR j to P1/P2 Data Valid
tpR
P1/P2 Data Stable before RD J- (7)
300
ns
tRP
P1/P2 Data Hold Time
50
ns
tAK
ACK Pulse Width
150
ns
tST
Strobe Pulse Width
tSIB
ns
tps
Data Setup to STB j
50
ns
tpH
Data Hold after STB j
50
twos
WRj toOBFj
tAOS
ACK
tSIB
STB
J- to OBF JJ- to IBF J-
ns
250
ns
250
ns
250
ns
tRI
RDj to IBFt
250
ns
tSIT
STB j to INTj
2tCY
+500
ns
tAIT
ACK j to INTj
2tCY
+500
ns
tAEO
OBF J- to ACK
J-
Delay
0
NOTES:
1. CL = pF all outputs.
2. Measured from logic "one" or "zero" to 1.5V at CL = 150 pF.
3. P12, P13 are external clock inputs.
4. Note that Rxe may be used as an input only in 1 x mode, otherwise it will be an output.
5. The center of the Stop Sit will be the receiver sample time, as programmed by the modification register.
6. V,sth bit length for 32x, 64X;100 ns for 1 x.
7. To ensure tAD spec is met.
6-126
ns
intJ
8256AH
WAVEFORMS
A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4=X
0.45
2.0
2.0
TEST POINTS
_ 0.8
A.C. TESTING LOAD CIRCUIT
)C
0.8 _
230759-5
A.C. lesling: Inpuls are driven al 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measuremenls are made al 2.0V for a
Logic "1" and 0.8V for a Logic "0".
230759-6
CL = 150 pF
CL Includes Jig Capacitance
SYSTEM CLOCK
elK
tR
230759-7
WRITE CYCLE
DB 0-7
A
0·3
cs
ALE
Wii
230759-8
READ CYCLE
DB
0·7
A
0-3
Cs'
ALE
AD
(INTA)
230759-9
6·127
inter
8256AH
WAVEFORMS
(Continued)
PARALLEL PORT HANDSHAKING-INPUT MODE
P
P
20-27
to
. II
(STB)
P
tt
(IBF)
t
RI
INT
--------------------~I~\----------~
DB
A
0-7
O-J
---_::x
DATA.
VALID
>-230759-10
PARALLEL PORT HANDSHAKING-oUTPUT MODE
DB
0-7
A
0-3
WA
P
. .:x,__.....;)-
X"'------....,~:\I~--
--./"\
--v ~:[i6
~-------------~~----~I'~----------------
tt
(OBF)
P
to
(ACK)
INT
INTAOA AD
-''"-11
r>rr-1-' r'""
========:============:~~-~--->¢S
WP
OUTPUT ----------....
P
__________....
20-27
------------\,)
DATA VALID
,~_____,\-_______________
230759-11
6-128
inter
8256AH
COUNT PULSE TIMINGS
P12 • P13
(COUNTER INPUT)
INT
230759-12
LOADING TIMER (OR CASCADED COUNTER/TIMER 3 AND 5)
P13
(COUNTER INPUT)
P15
(COUNTER INPUT)
INT
230759-13
TRIGGER PULSE FOR TIMER 5 (CASCADED EVENT COUNTER/TIMER 3 AND 5)
P15
(TRIGGER INPUT)
230759-14
COUNTER TIMER TIMING
EXTERNAL CLOCK
(P12, P13)
'we
230759-15
OUTPUT FROM PORT 1 AND PORT 2
DB
0-7
____________J~~__D_A_TA_V_A_LI_D__J~~______________
A
0-3
OUTPUT
' . . . ----~.~~Ior------
Pl0·17, P20·27
230759-16
6-129
inter
8256AH
INPUT FROM PORT 1 AND PORT 2
INPUT
PII1-17. P211-27 _ _ _ __
>t- .
lM'{
DB0.7
Ao-o
_ _ _ _ _ _ _ _ _ _J
x
DATA VALID
)>------230759-17
INTERRUPT TIMING
INTAORRD
x
_ _ _ _ _ _ _ _ _ _ _ _ _..J
DATA
)>---230759-18
. CTS FOR _SINGLE CHARACTER TRANSMISSION
I
230759-19
RESET TIMING
I
.....
230759-20
6-130
8256AH
EXTERNAL BAUD RATE CLOCK FOR SERIAL INTERFACE
TxC
(64 X AND 32
BAUD RATE INPUT
-iISPW): ISPOS
I
:
/
~_...J
~---SCV
230759-21
TRANSMITTER AND RECEIVER CLOCK FROM INTERNAL CLOCK SOURCE
_112 ICCV_..J~_1/2 ICCV-
TXC,RxC
(OUTPUT)
"'1'----/
~r-----
~_.,--ICCV= l/BAUDAATE_
230759-22
TRANSMISSION OF CHARACTERS ON SERIAL INTERFACE
STATUS
REGISTER
BIT 5 (TBE)
STATUS
REGISTER
BIT 4 (TRE)
INT
(LEVEL 5)
TxD
230759-23
NOTES:
1. Load transmitter buffer register.
2. Transmitter buffer register is empty.
3. Transmitter register is empty.
4. Character format for this example: 7 Data Bits with Parity Bit and 2 Stop Bits.
5. Loading of transmitter buffer register must be complete before CTS goes low.
6. Interrupt due to transmitter buffer register empty.
7. Interrupt due to transmitter register empty.
No status bits are altered when RD is active.
6-131
8256AH
DATA BIT OUTPUT ON SERIAL INTERFACE
ToC
(1 ~ BAUD RATE INPUT)
T.C
(84 ~ BAUD RATE INPUT)
TXC
(32 x BAUD RATE INPUT)
ToD
~-----DATA 8IT-------IOoI
230759-24
CONTINUOUS RECEPTION OF CHARACTERS ON SERIAL INTERFACE
WITHOUT ERROR CONDITION
CHARACTER
RxD
1)
Wii
2)
CHARACTER
CHARACTER
CHARACTER
CHARACTER
COMMAND
REGISTER
BIT 6 (RoE)
STATUS
REGISTER
BIT 6 (RBF)
INT
(LEVEL 4)
AD
4)
CHARACTER
CHARACTER
CHARACTER
230759-25
NOTES:
1.
2.
3.
4.
Character format for this exainple: 6 data bits with parity bit and one stop bit.
Set or reset bit 6 of command register 3 (enable receiver).
Receiver buffer located.
Read receiver buffer register.
6-132
inter
8256AH
ERROR CONDITIONS DURING RECEPTION OF CHARACTERS ON THE SERIAL INTERFACE
CHARACTER
RxD
CHARACTER
CHARACTER
CHARACTER
CHARACTER
I)
STATUS
REGISTER 2)
BIT 6 (RBF)
INT
(LEVEL 4)
STATUS
REGISTER
BIT 1 (DE)
3)
...
------t+--~=
STATUS
REGISTER
BIT 0 (FE)
FRAMING ERROR
230759-26
NOTES:
1. Character format for this example: 6 data bits without parity and one stop bit.
2. Receiver buffer register loaded.
3. Overrun error.
4. Framing error.
5. Interrupt from receiver buffer register loading.
6. Interrupt from overrun error.
7. Interrupt from framing error' and loading receiver buffer register.
No status bits are altered when RD is active.
6-133
8279/8279-5
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
16-Character Display
• Single
Right or Left Entry 16-Byte Display
Keyboard Display
• Simultaneous
Operations
Keyboard Mode
• Scanned
Sensor Mode
• Scanned
Strobed Input Entry Mode
• 8-Character Keyboard FIFO
• 2-Key Lockout or N-Key Rollover with
• Contact Debounce
• Dual 8- or 16-Numerical Display
• RAM
Mode Programmable from CPU
• Programmable
Scan Timing
• Interrupt Output.on
Key Entry
• Available in EXPRESS
• - Standard Temperature Range
- Extended Temperature Range
The Intel® 8279 is a general purpose programmable keyboard and display I/O interface device designed for
use with Intel® microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key
matrix. The keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as
the hall effect and ferrite variety. Key depressions can be 2-key lockout or N-key rollover. Keyboard entries are
debounced and strobed in an 8-character FIFO. If more than 8 characters are entered, overrun status is set.
Key entries set the interrupt output line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The
8279 has 16x8 display RAM which can be organized into dual 16x4. The RAM can be loaded or interrogated
by the CPU. Both right entry, calculator and left entry typewriter display formats are possible. Both read and
write of the display RAM can be done with auto-increment of the display RAM address.
TVcc
IRQ
~)
,/
"
Rlo 7
~
DAT~
BUS
.
SHIFT
RO
Wii
CNTl/STB
KEY DATA
•
.
..1\.
.
AO
SLOJ
4
.
OUT AOJ
4
RESET
I
eLK
...
SCAN
)...
RL,
Cll<
RLo
IRQ
CNTlISTB
RL.
SHIFT
RLs
SL3
RL.
Sl2
Rl7
Sl,
Slo
AD
QUT Bo
WR
OUT B,
DBa
OUT B2
DB,
OUT B3
DB,
OUT Ao
DB3
OUT A,
DB.
qUT A2
DBs
OUT A)
DB.
m
ii!j
DB7
CS
I
Vss
Ao
OUT SOl
4
)
DISPLAY
DATA
V
J:-
VCC
RL)
RESET
CPU
INTERFACE
B
RL,
290123-2
Vss
290123-1
Figure 2. Pin Configuration
Figure 1. Logic Symbol
6-134
September 19B7
Order Number: 290123·002
inter
8279/8279-5
HARDWARE DESCRIPTION
The 8279 is packaged in a 40 pin DIP. The following is a functional description of each pin.
Table 1. Pin Description
Symbol
DBo-DB7
Pin
No.
19-12
Name and Function
BI-D1RECTIONAL DATA BUS: All data and commands between the CPU
and the 8279 are transmitted on these lines.
ClK
3
CLOCK: Clock from system used to generate internal timing.
RESET
9
RESET: A high signal on this pin resets the 8279. After being reset the 8279 is
placed in the following mode:
1) 16 8-bit character display-left entry.
2) Encoded scan keyboard-2 key lockout.
Along with this the program clock prescaler is set to 31.
CS
22
CHIP SELECT: A low on this pin enables the interface functions to receive or
transmit.
Ao
21
BUFFER ADDRESS: A high on this line indicates the signals in or out are
interpreted as a command or status. A low indicates that they are data.
RD,WR
IRQ
10-11
INPUT/OUTPUT READ AND WRITE: These signals enable the data buffers
to either send data to the external bus or receive it from the external bus.
4
INTERRUPT REQUEST: In a keyboard mode, the interrupt line is high when
there is data in the FIFO/Sensor RAM. The interrupt line goes low with each
FIFO/Sensor RAM read and returns high if there is still information in the
RAM. In a sensor mode, the interrupt line goes high whenever a change in a
sensor is detected.
Vss,Vcc
20,40
GROUND AND POWER SUPPLY PINS.
Slo-Sl3
32-35
SCAN LINES: Scan lines which are used to scan the key switch or sensor
matrix and the display digits. These lines can be either encoded (1 of 16) or
decoded (1 of 4).
Rlo-Rl7
38,39,
RETURN LINE: Return line inputs which are connected to the scan lines
1,2,5-8 through the keys or sensor switches. They have active internal pull ups to
keep them high until a switch closure pulls one low. They also serve as an 8bit input in the Strobed Input mode.
SHIFT
36
SHIFT: The shift inpllt status is stored along with the key position on key
closure in the Scanned Keyboard modes. It has an active internal pullup to
keep it high until a switch closure pulls it low.
CNTl/STB
37
CONTROL/STROBED INPUT MODE: For keyboard modes this line is used
as a control input and stored like status on a key closure. The line is also the
strobe line that enters the data into the FIFO in the Strobed Input mode.
(Rising Edge). It has an active internal pullup to keep it high until a switch
closure pulls it low.
OUT Ao-OUT A3
OUT Bo-OUT B3
BD
27-24
31-28
23
OUTPUTS: These two ports are the outputs for the 16 x 4 display refresh
registers. The data from these outputs is synchronized to the scan lines (SloSl3) for multiplexed digit displays. The two 4 bit ports may be blanked
independently. These two ports may also be considered as one 8-bit port.
BLANK DISPLAY: This output is used to blank the display during digit
switching or by a display blanking command.
6-135
8279/8279-5
FUNCTIONAL DESCRIPTION
I/O Control and Data Buffers
Since data input and display are an integral part of
many microprocessor designs, the system designer
needs an interface that can control these functions
without placing a large load on the CPU. The 8279
provides this function for 8-bit microprocessors.
The I/O control section uses the CS, Ao, RD and
WR lines to control data flow to and from the various
internal registers and buffers. All data flow to and
from the 8279 is enabled by CS. The character of
the information, given or desired by the CPU, is identified by Ao. A logio one means the information is a
command or status. AJQgic zero means the information is data. RD and WR determine the direction of
data flow through the Data Buffers. The Data Buffers
are bi-directional buffers that connect the internal··
bus to the external bus. When the chip is not selected (CS = 1), the devices are.!!:!..il h~ impedance
state. The drivers input during WR • CS and output
during RD • CS.
The 8279 has two sections: keyboard and display.
The keyboard section can interface to regular typewriter style keyboards or random toggle or thumb
switches. The display section drives alphanumeric
displays or a bank of indicator lights. Thus the CPU
is relieved from scanning the keyboard or refreshing
the display.
The 8279 is designed to directly connect to the mi- .
croprocessor bus. The CPU can program all operating modes for the 8279. These modes include:
Input Modes
Control and Timing Registers and
Timing Control
.
• Scanned Keyboard-with encoded (8 x 8 key
keyboard) or decoded (4 x 8 key keyboard) scan
lines. A key depression generates a 6-bit encoding of key position. Position and shift and control
status are stored in the FIFO. Keys are automatically debounced with 2-key lockout or N-key rollover.
• Scanned Sensor Matrix-with encoded (8 x 8 matrix switches) or decoded (4 x 8 matrix switches)
scan lines. Key status (open or closed) stored in
RAM addressable by CPU.
• Strobed Input-Data on return lines during control line strobe is transferred to FIFO.
These registers store the keyboard and display
modes and other operating conditions programmed
by the CPU. The modes are programmed by pre~
senting the proper command on the data lines with
Ao = 1 and then sending a WR. The command is
latched on the rising edge of WR. The command is
then decoded and the appropriate function is set.
The timing control contains the basic timing counter
chain. The first counter is a -;- N prescaler that can
be programmed to yield an internal frequency of 100
kHz which gives a 5.1 ms keyboard scan time and a
10.3 ms debounce time; The other counters divide
down the basic internal frequency to provide the
proper key scan, row scan, keyboard matrix scan,
and display scan times.
Output Modes
Scan Counter
• 8 or 16 character multiplexed displays that can
be organized as dual 4-bit or single 8-bit (Bo =
Do, A3 = D7)·
• . Right entry or left entry display formats.
Other features of the 8279 include:
• Mode programming from the CPU.
• Clock Prescaler
• Interrupt output to signal CPU when there is keyboard or sensor data available.
• An 8 byte FIFOto store keyboard information.
• 16 byte internal Display RAM for display refresh.
This RAM can also be read by the CPU.
The scan counter has two modes. In the encoded
mode, the counter provides a binary count that must
be externally decoded to provide the scan linesfor
the keyboard and display. In the decoded mode, the
scan counter decodes the least significant 2 bits and
provides a decoded 1 of 4 scan. Note that when the
keyboard is in decoded scan, so is the display. This
means that only the first 4 characters in the Display
RAM are displayed.
In the encoded mode, the scan lines are active high
outputs. In the decoded mode, the scan lines are
active low outputs.
PRINCIPLES OF OPERATION
The following is a description of the major elements
of the 8279 Programmable Keyboard/Display interface device. Refer to the block diagram in Figure 3.
6-136
ClK
RESET
AD
DBD-7
WA
CS
D
j
DATA
BUFFERS
FIFO/SENSOR
RAM
STATUS
110 CONTROL
r
!!
(Q
c
iil
L
a
,
CD
:J
III
"/
c.J
-..J
-
DISPLAY
ADDRESS
REGISTERS
0)
~
...
III
0n
;I\"
C
7
INTERNAL-DATA BUS (81
L
!»
L..
)
V
'----
16.8
OISPlAY
RAM
CONTROL AND
TIMING
REGISTERS
/'
1-
I
c»
I\)
......
CD
......
8.8
FIFO/SENSOR
RAM
I
.
~
...III
k
c»
I\)
TIMING
AND
CONTROL
DISPLAY
REGISTERS
CD
I
UI
/'>.
1
RETURN
.: SCAN COUNTER
J
......
KEYBOARD
DEBOUNCE
AND
CONTROL
t
3
,-/7
(
IRO
Ao
/'?,.
8
'I
OUT AO.3
.,
7
OUT B~3
liD
4
8
'7
"SLo.1
RLo.7
SHIFT
CNTL/STB
290123-3
inter
8279/8279-5
Return Buffers and Keyboard
Debounce and Control
SOFTWARE OPERATION
The 8 return lines are buffered and latched by the
Return Buffers. In the keyboard mode, these lines
are scanned, looking for key closures in that row. If
the debounce circuit detects a closed switch, it waits
about 10 ms to check if the switch remains closed. If
it does, the address of the switch in the matrix plus
the status of SHIFT and CONTROL are transferred
to the FIFO. In the scanned Sensor Matrix modes,
the contents of the return lines is directly transferred
to the corresponding row of the Sensor RAM (FIFO)
each key scan time. In Strobed Input mode, the contents of the return lines are transferred to the FIFO
on the rising edge of the CNTLlSTB line pulse.
8279 Commands
The following commands program the 8279 operating modes. The commands are sent on the Data Bus
with CS low and Ao hi~and are loaded to the 8279
on the rising edge of WR.
Keyboard/Display Mode Set
MSB
I 0 I 0 ,I
Code:
LSB
0 'I DID I K I K I K I
Where DD is the Display Mode and KKK is the Keyboard Mode.
FIFO/Sensor RAM and Status
DO
This block is a dual function 8 x 8 RAM. In Keyboard
or Strobed Input modes, it is a FIFO. Each new entry
is written into successive RAM positions and each is
then read in order of entry. FIFO status keeps track
of the number of characters in the FIFO and whether
it is full or empty. Too many reads or writes will be
recQfLnized as an error. The status can be read by
an RD with CS low and Ao high. The status logic also
provides an IRQ signal when the FIFO is not empty.
In Scanned Sensor Matrix mode, the memory is a
Sensor RAM. Each row of the Sensor RAM is loaded
with the status of the corresponding row of sensor in
the sensor matrix. In this mode, IRQ is high if a
change in a sensor is detected.
Display Address Registers and Display
RAM
o
o
o
For description of right and left entry, see Interface
Considerations. Note that when decoded scan is set
in keyboard mode, the display is reduced to 4 characters independent of display mode set.
KKK
o
0
0
0
0
The Display Address Registers hold the address of
the word currently being written or read by the CPU
and the two 4-bit nibbles being displayed. The read/
write addresses are programmed by CPU command ..
They also can be set to auto increment after each
read or write. The Display RAM can be directly read
by the CPU after the correct mode and address is
set. The addresses for the A and B nibbles are automatically updated by the 8279 to match data entry
by the CPU. The A and B nibbles can be entered
independently or as one word, according to the
mode that is set by the CPU. Data entry to the display can be set to either left or right entry. See Interface Considerations for details.
8 8-bit character display-Left entry
16 8-bit character display-Left entry'
8, 8-bit character display-Right entry
16 8-bit character display-Right entry
0
0
0
0
o
o
0
1
o
Encoded Scan Keyboard-2 Key Lockout'
Decoded Scan Keyboard-2-Key Lockout
Encoded Scan Keyboard-N-Key Rollover
Decoded Scan Keyboard-N-Key RolIover
Encoded Scan Sensor Matrix
Decoded Scan Sensor Matrix
Strobed Input, Encoded Display Scan
Strobed Input, Decoded Display Scan
'Default after reset.
Program Clock
Code:
I0 I0
P
P
P
P I.p
All timing and multiplexing signals for the 8279 are
generated by an internal prescaler. This prescaler
divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer which ranges from 2 to 31. Choosing a divisor
that yields 100 kHz will give the specified scan al")d
6-138
inter
8279/8279-5
debounce times. For instance, if Pin 3 of the 8279 is
being clocked by a 2 MHz signal, PPPPP should be
set to 10100 to divide the clock by 20 to yield the
proper 100 kHz operating frequency.
Display Write Inhibit/Blanking
Read FIFO/Sensor RAM
The IW Bits can be used to mask nibble A and nibble
B in applications requiring separate 4-bit display
ports. By setting the IW flag (IW = 1) for one of the
ports, the port becomes marked so that entries to
the Display RAM from the CPU do not affect that
port. Thus, if each nibble is input to a BCD decoder,
the CPU may write a digit to the Display RAM without affecting the other digit being displayed. It is important to note that bit Bo corresponds to bit Do on
the CPU bus, and that bit A3 corresponds to bit D7.
The CPU sets the 8279 for a read of the FIFO/Sensor RAM by first writing this command. In the Scan
Keyboard Mode, the Auto-Increment flag (AI) and
the RAM address bits (AAA) are irrelevant. The 8279
will automatically drive the data bus for each subsequent read (Ao = 0) in the same sequence in which
the data first entered the FIFO. All subsequent reads
will be from the FIFO until another command is issued.
In the Sensor Matrix Mode, the RAM address bits
AAA select one of the 8 rows of the Sensor RAM. If
the AI flag is set (AI = 1), each successive read will
be from the subsequent row of the sensor RAM.
Read Display RAM
Code:
o -r1-1-'1-'--A-1~A"""'-A--'-A-'-A--'
Ir--
The CPU sets up the 8279 for a read of the Display
RAM by first writing this command. The address bits
AAAA select one of the 16 rows of the Display RAM.
If the AI flag is set (A1 = 1), this row address will be
incremented after each following read or write to the
Display RAM. Since the same counter is used for
both reading and writing, this command sets the
next read or write address and the sense of the
Auto-Increment mode for both operations.
Write Display RAM
Code:
1'-1....
I-o-,I-o--.-A-I~A"""'-A--'-A-'-A--'
The CPU sets up the 8279 for a write to the Display
RAM by first writing this command. After writing the
command with Ao = 1, all subsequent writes with Ao
= 0 will be to the Display RAM. The addressing and
Auto-Increment functions are identical to those for
the Read Display RAM. However, this command
does not affect the source of subsequent Data
Reads; the CPU will read from whichever RAM (Display of FIFO/Sensor) which was last specified. If,
indeed, the Display RAM was last specified, the
Write Display RAM will, nevertheless, change the
next Read location.
B
A
A
B
I 1 1 0 1 1 1 X 1 IW I I BL I BL 1
IW
Code:
If the user wishes to blank the display, the BL flags
are available for each nibble. The last Clear command issued determines the code to be used as a
"blank." This code defaults to all zeros after a reset.
Note that both BL flags must be set to blank a display formatted with a single 8-bit port.
Clear
Code:
11
I I 0 I Co I CD I CD I CF I CA 1
The CD bits are available in this command to clear
all rows of the Display RAM to a selectable blanking
code as follows:
,e: I~'
ClJD
1
1
All Zeros
IX
=
Don·, Carel
= Hex 20 10010 00001
0
AB
1
All Ones
Enable clear dIsplay when::: 1 (or by CA
= 1)
290123-13
During the time the Display RAM is being cleared
(~ 160 f-Ls), it may not be written to. The most significant bit of the FIFO status word is set during this
time. When the Display RAM becomes available
again, it automatically resets.
If the CF bit is asserted (CF = 1), the FIFO status is
cleared and the interrupt output line is reset. Also,
the Sensor RAM pOinter is set to row O.
GA,
the Clear All bit, has the combined effect of CD
and CF; it uses the CD clearing code on the Display
RAM and also clears FIFO status. Furthermore, it
resynchronizes the internal timing chain.
.
6-139
inter
8279/8279-5
End Interrupt/Error Mode Set
Code:
11 11 11 IE IX IX IX IX I
X
=
Don't care
For the sensor matrix modes this command lowers
the IRQ line and enables further writing into RAM.
(The IRQ line would have been raised upon the detection of a change in a sensor value. This would
have also inhibited further writing into the RAM until
reset).
For the N-key rollover mode-if the E bit is programmed to "1" the chip will operate in the special
Error mode. (For further details, see Interface Considerations Section.)
Status Word
The status word contains the FIFO status, error, and
display unavailable signals. This word is read by the
CPU when Ao is high and CS and RD are low. See
. Interface Considerations for more detail on status
word.
Data Read
Data is read when Ao, CS and RD are all low. The
source of the data is specified by the Read FIFO or
Read Display commands. The trailing edge of RD
will cause the address of the RAM being read to be
incremented if the Auto-Increment flag is set. FIFO
reads always increment (if no error occurs) independent.of AI.
Data Write
Data .that is written with Ao, CS and WR low is always written to the Display RAM. The address is
specified by the latest Head Display or Write Display
command. Auto-Incrementing on the rising edge
of WR occurs if AI is set by the latest display
command.
INTERFACE CONSIDERATIONS
FIFO along with the status of CNTL and SHIFT lines.
If the FIFO was empty, IRQ will be set to signal the
CPU that there is an entry in the FIFO. If the FIFO
was full, the key will not be entered and the error
flag will be set. If another closed switch is encountered, no entry to the FIFO can occur. If all other
keys are released before ths one, then it will be entered to the FIFO. If this key is released before any
other, it will be entirely ignored. A key is entered to
the FIFO only once per depression, no matter how
many keys were pressed along with it or in what
order they were released. If two keys are depressed
within the debounce cycle, it is a simultaneous depression. Neither key will be recognized until one
key remains depressed alone. The last key will be
treated as a single key depression.
Scanned Keyboard Mode, N-Key
Rollover
With N-key Rollover each key depression is treated
independently from all ·others. When a key is depressed, the debounce circuit waits 2 keyboard
scans and then checks to see if the key is still down.
If it is , the key is entered into the FIFO. Any number
of keys can be depressed and another can be recognized and entered into the FIFO. If a simultaneous
depression occurs, the keys are recognized and entered according to the order the keyboard scan
found them.
Scanned Keyboard-Special Error
Modes
For N-keyrollover mode the user can program a
special error mode. This is done by the "End Interrupt/Error Mode Set" command. The debounce cycle and key-validity check are as in normal N-key
mode. If during a single debounce cycle, two keys
are found depressed, this is considered a simultaneous multiple depression, and sets an error flag.
This flag will prevent any further writing into the FIFO
and will set interrupt (if not yet set). The error flag
could be read in this mode by reading the FIFO
STATUS word. (See "FIFO STATUS" for further details.) The error flag is reset by sending the normal
CLEAR command with CF = 1.
Scanned Keyboard· Mode, 2-Key
Lockout
Sensor Matrix Mode
There are three possible combinations of conditions
that can occur during debounce scanning. When a
key is depressed, the debounce logic is set. Other
depressed keys are looked for during the nex1 two
scans. If none are encountered, it is a single key
depression and the key position is entered into the
In Sensor Matrix mode, the debounce logic is inhibited. The status of the sensor switch is inputted directly to the Sensor RAM. In this way the Sensor
RAM keeps an image of the state of the switches in
the sensor matrix. Although debouncing is not provided, this mode has the advantage that the CPU
knows how long the sensor was closed and when it
6-140
inter
8279/8279-5
was released. A keyboard mode can only indicate a
validated closure. To make the software easier, the
designer should functionally group the sensors by
row since this is the format in which the CPU will
read them.
by the rising edge of a CNTL/STB line pulse. Data
can come from another encoded keyboard or simple
switch matrix. The return lines can also be used as a
general purpose strobed input.
The IRQ line goes high if any sensor value change is
detected at the end of a sensor matrix scan. The
IRQ line is cleared by the first data read operation if
the Auto-Increment flag is set to zero, or by the End
Interrupt command if the Auto-Increment flag is set
to one.
I RL7 I RLs I
MSB
LSB
RL~
I RL4 I RL3 I RL21 RL1 I RLo I
Display
Left Entry
NOTE:
Multiple changes in the matrix Addressed by
(SLo-3 = 0) may cause multiple interrupts. (SLo =
o in the Decoded Mode.) Reset may cause the
8279 to see multiple changes.
Data Format
In the Scanned Keyboard mode, the character entered into the FIFO corresponds to the position of
the switch in the keyboard plus the status of the
CNTL and SHIFT lines (non-inverted). CNTL is the
MSB of the character and SHIFT is the next most
significant bit. The next three bits are from the scan
counter and indicate the row the key was found in.
The last three bits are from the column counter and
indicate to which return line the key was connected.
MSB
LSB
ICNTLISHIFTI
:SCAN:
~ETUR~
I
Left Entry mode is the Simplest display format in that
each display position directly corresponds to a byte
(or nibble) in the Display RAM. Address 0 in the
RAM is the left-most display character and address
15 (or address 7 in 8 character display) is the right
most display character. Entering characters from position zero causes the display to fill from the left. The
17th (9th) character is entered back in the left most
position and filling again proceeds from there.
1st entry
2nd entry
16th entry
SCANNED KEYBOARD DATA FORMAT
In Sensor Matrix mode, the data on the return lines
is entered directly in the row of the Sensor RAM that
corresponds to the row in the matrix being scanned.
Therefore, each switch position maps directly to a
. Sensor RAM position. The SHIFT and CNTL inputs
are ignored in this mode. Note that switches are not
necessarily the only thing that can be connected to
the return lines in this mode. Any logic that can be
triggered by the scan lines can enter data to the
return line inputs. Eight multiplexed input ports could
be tied to the return lines and scanned by the 8279.
MSB
LSB
I RL7 I RL6 I RL5 I RL4 I RLa I RL2 I RL1 I RLo I
In Strobed Input mode, the data is also entered to
the FIFO from the return lines. The data is entered
6-141
o
1
14 15_0isplay
RAM
o
1
14 15
QI] _- _- _- _- IT]
~=
o
1
o
1
Address
===LD
14 15
Ci:EI ====:@E]
14 15
17th entry
~ ====EE]
18th entry
~ ====EEJ
o
1
14· 15
290123-14
Left Entry Mode (Auto Increment)
Right Entry .
Right entry is the method used by most electronic
calculators. The first entry is placed in the right most
display character. The next entry is also placed in
the right most character after the display is shifted
left one character. The left most character is shifted
off the end and is lost.
intJ
8279/8279-5
2
1st entry
2
2nd entry
'3
3rd entry
01234567+-
1
14 15
ITJ ===Jill I:~~ess
15 0 1
ITJ= ===I 11121
[0====1 1121 1
O_Display
1st entry
3
4
0 'I
2nd entry
2
o
Command
10010101
===
EI== =
~=
2
18th entry
14 15 0
115i16117\
15
-1161171181
3
Right Entry Mode (Auto Increment)
0
1 234 5 6 7
11 121
3
12
I I I I II I I
o
16th entry
17thentrv
11
Display
RAM
Address
IIIIII
1 2 3 4 5 6 7
IIIIII
11 121
Enter next at Location 5 Auto Increment
o
3rd entry
1
1 234 5 6 7
11 121
II
13 1
II
o 1 234 5 6 7
290123-15
4th entry
Note that now the display position and register address do not correspond. Consequently, entering a
character to an arbitrary position in the Auto Increment mode may have unexpected results. Entry
starting at Display RAM address 0 with sequential
entry is recommended.
11 121
II
13141
I
LEFT ENTRY MODE
(AUTO INCREMENT)
In the Right Entry mode, Auto Incrementing and non
Incrementing have the same effect as in the Left
Entry except if the address sequence is interrupted.
1 2 3 4 5 6 7 0
1st entry
Auto Increment
In the Left Entry mode, Auto Incrementing causes
the address where the CPU will next write to be incremented by one and the character appears in the
next location. With non-Auto Incrementing the entry
is both to the same RAM address and display position. Entry to an arbitrary address in the Auto Increment mode has no undesirable side effects and the
result is predictable:
+-
I I I I I I I 11 I
~:~ess
234 5 6 7 0 1
2nd entry
IIIIII
11 121
2345670 1
Command
10010101
I I I I I I 11 121
Enter next at Location 5 Auto Increment
345 6 7 0 1 2
3rd entry
II
4th entry
I
131
I 11 121 I
45670 1 2 3
13141
11 121
II
RIGHT ENTRY MODE
(AUTO INCREMENT)
6-142
Display
intJ
8279/8279-5
Starting at an arbitrary location operates as shown
below:
01234567~ Display
RAM
Command 1 1 1
1
1
Address
10010101
II II
Enter next at Location 5 Auto Increment
1 234 5 670
1st entry
1 1 1 1 11 1 1 1 1
the FIFO and to indicate whether an error has occurred. There are two types of errors possible: overrun and underrun. Overrun occurs when the entry of
another character into a full FIFO is attempted. Underrun occurs when the CPU tries to read an empty
FIFO.
The FIFO status word also has a bit to indicate that
the Display RAM was unavailable because a Clear
Display or Clear All command had not completed its
clearing operation.
2 3 456 7 0 1
2nd entry
1 1 1 11 121
8th entry
141516171811 12131
9th entry
15161718191213141
In a Sensor Matrix mode, a bit is set in the FIFO
status word to indicate that at least one sensor closure indication is contained in the Sensor RAM.
1 1 1
In Special Error Mode the S/E bit is showing the
error flag and serves as an indication to whether a
simultaneous multiple closure error has occurred.
RIGHT ENTRY MODE
(AUTO INCREMENT)
FIFO STATUS WORD
Entry appears to be from the intial entry point.
8/16 Character Display Formats
If the display mode is set to an 8 character display,
the on duty-cycle is double what it would be for a 16
character display (e.g., 5.1 ms scan time for 8 characters vs. 10.3 ms for 16 characters with 100 kHz
internal frequency).
G. FIFO Status
' - - - - - Sensor Closure/Error F lag for
Multiple Closures
' - - - - - - - Display unavailable
290123-4
FIFO status is used in the Keyboard and Strobed
Input modes to indicate the number of characters in
6-143
infef
8279/8279-5
KEYBOARD
MATRIX
SHIFT
CONTROL
8 COLUMNS
B/
RETURN
LINES
8 ROWS
,.
V18
U
5V
INT
B·BIT
MICRO·
PROCESSOR
SYSTEM
SHIFT CNTl
INT
RO_7
VOO
DATA BUS
DATA
BUS
8/
AD
WR
CONTROLS {
RESET
CS
ADDRESS{
BUS
CLOCK
AO
CLK
VSS
0 0 _7
SO_3
lOR
8279
3 - 8 DECODER
lv
~
SCAN LINES
lOW
(:4
,
RESET
4 -16 DECODER
CS
AO
CLK B
3 LSS'
4/
0-3
A O_3
ITh
BLANK
DISPLAY
."-
4
/
V-
16
ADDRESSES
(DECODED)
4
/
!
DISPLAY
CHARACTERS
DATA
DISPLAY
290123-5
'Do not drive Ihe keyboard decoder with the MSB of the scan lines.
Figure 4. System Block Diagram
6-144
inter
8279/8279-5
* Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature ................ O°C to 70°C
Storage Temperature ............. - 65°C to 125°C
Voltage on any Pin with
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS
TA
=
= OV (Note 3)*
O°C to 70°C Vss
Max
Unit
VILl
Input Low Voltage for Return Lines
-0.5
1.4
V
VIL2
Input Low Voltage for All Others
-0.5
0.8
V
VIHl
Input High Voltage for Return Lines
2.2
VIH2
Input High Voltage for All Others
2.0
VOL
Output Low Voltage
VOHl
Output High Voltage on Interrupt Line
3.5
VOH2
Other Outputs
2.4
IILl
Input Current on Shift, Control and
Return Lines
IIL2
Symbol
Parameter
Min
V
V
0.45
V
(Note 1)
V
(Note 2)
I
OH -
+10
-100
/Jo A
/JoA
Input Leakage Current on All Others
±10
/JoA
IOFL
Output Float Leakage
±10
lee
Power Supply Current
120
/Jo A
mA
CIN
Input Capacitance
10
pF
COUT
Output Capacitance
20
pF
A.C. CHARACTERISTICS
TA
Test Conditions
- 400 !LA 8279-5
-100 !LA 8279
= Vee
= OV
VIN = Vee to OV
VOUT = Vee to 0.45V
VIN
VIN
fe = 1 MHz Unmeasured
Pins Returned to VSS(6)
= O°C to 70°C, Vss = OV (Note 3)*
Bus Parameters
READ CYCLE
Symbol
Parameter
8279
Min
8279·5
Max
Min
Max
Unit
tAR
Address Stable Before READ
50
0
ns
tRA
Address Hold Time for READ
5
0
ns
tRR
READ Pulse Width
tRO(4)
Data Delay from READ
420
300
150
ns
tAO(4)
Address to Data Valid
450
250
ns
tOF
READ to Data Floating
10
100
ns
tReY
Read Cycle Time
1
1
/Jos
tAW
Address Stable Before WRITE
50
0
ns
tWA
Address Hold Time for WRITE
20
0
ns
6-145
250
100
10
ns
8279/8279-5
A.C. CHARACTERISTICS
(Continued)
WRITE CYCLE
Symbol
8279-5
8279
Parameter
Min
Max
Unit
Max
Min
tww
WRITE Pulse Width
400
250
ns
tow
Data Set Up Time for WRITE
300
150
ns
two
Data Hold Time for WRITE
40
0
ns
twCY
Write Cycle Time
1
1
J-Ls
OTHER TIMINGS
Symbol
230
500
Clock Period
tCY
Max
Min
Clock Pulse Width
tq,w
8279-5
8279
Parameter
Min
Unit
Max
120
ns
320
ns
Keyboard Scan Time ...................... 5.1 ms
Digit-on Time ............................ 480 J-Ls
Keyboard Debounce Time ................ 10.3 ms
Blanking Time ........................... 160 J-Ls
Key Scan Time ...................... ~ .... 80 J-Ls
Internal Clock Cycle(5) .................... : 10 J-Ls
Display Scan Time ....................... 10.3 ms
NOTES:
1. 8279, IOl = 1.6 mA; 8279-5, IOL = 2.2 mAo
2. IOH = -100/LA
3.8279, VCC = +5V ±5%; 8279-5, VCC = +5V ±10%
4.8279, Cl = 100 pF; 8279-5, Cl = 150 pF.
5. The Prescaler should be programmed to provide a 10 /Ls internal clock cycle.
6. Sampled not 100% tested. TA = 25"C.
* For Extended Temperature EXPRESS, use M8279A electrical parameters.
A.C, TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
'.'=X >
2.0
TEST POINTS
0.45
0.8
<
2.0
0.8
x=
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
290123-6
A.C. Testing: Inputs are driven at 2.4V for a logic "1" and O.4SV
for a logic "0". Timing measurements are made at 2.0V for a
logic "1" and O.SV for a logic "0".
~Cl=
120pF
-=
290123-7
CL = 120 pF
CL Includes Jig Capacitance
6-146
intJ
8279/8279-5
WAVEFORMS
READ OPERATION
Ao.ES
~
____________________________________
_tAR_·I·.~---------tRC'"
~~
___________________________
(SYSTEM'S
ADDRE~BUSI
---+--------1
1-----'•• -----1
(READ CONTROL)
I----'Ao----I
DATA BUS
IDUTPUTI~~~~~~~~~~~~~~____________________~~~~~~~~~~~~~~
290123-8
WRITE OPERATION
~--------------------------
(SYSTEM'S
ADDRESS BUS)
i-----'ww---(WRITE CONTROLI
-'oW~ I-'wo
DATA BUS
DATA
~ -DATA VALlD- V
DATA
--'1'.
,- - - "''-________M_A_y_C_H_A_N_GE
_ _ _ _ _ __
UNPUTl________M_A_y_C_H;..A_NG_E______
290123-9
CLOCK INPUT
290123-10.
6·147
intJ
8279/8279-5
WAVEFORMS
(Continued)
SCAN
L
L
L
I
s,
ENCODED
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290123-11
6-148
intJ
8279/8279·5
WAVEFORMS
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DISPLAY
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290123-12
NOTE:
Shawn is encoded scan left entry
S2-S3 are not shown but they are simply S1 divided by 2 and 4.
6-149
82389
MESSAGE PASSING COPROCESSOR
A MULTIBUS® II BUS INTERFACE CONTROLLER
• Highly Il"ltegrated VLSI Device
....;.. Single-Chip: Interface for the pa:rallel
. System Bus (IEi:E 1296)
-Interrupt Handling/Bus Arbitration
Functions
- Dual-Buffer Input and Output DMA
Capabilities
- Nine 32-Byte High Speed FIFOs
• Multiple Interface Support
- Complete Protocol Support of the
PSB Bus (Message Passing)
- Processor Independent Interface
(8, 16, or 32-Blt .CPU)
- Low-Cost 8-Bit Microcontroller .
Interface'
- Dual~Port Memory Interface
• High Performance Coprocessing
Functions
- Offloads CPU for Communication
a:nd Bus Interfacing
- 40 Megabytes/Sec Burst Transfer
Speed
- Optimized for Real-Time Response
(Max. 900 ns for 32-Byte Interrupt'
Packet)
• Compatible with Bus Arbiter Controller
(BAC) and Message Interrupt Controller
(MIC) Interface Designs
• CMOS Technology
• 149 Pin PGA Package (15 x 15 Grid)
TheMPC 82389 is a highly integrated VLSI device that maximizes the performance of a Multibus® II based
multiprocessor system, It integrates the functions of bus arbitration, packetizing data for transmit, error handling and interrupt control. Because of these integrated functions the host CPU can be offloaded to utilize the
maximum bus performance and subsequently increase the system throughput The MPC 82389 also supports
geographic addressing by providing access to the local interconnect registers for reference and control.
The MPC 82389 is designed to interface with an 8, 16, or 32-bit processor and the Parallel System Bus
performance is not affected by the CPU buswidth or its bandwidth, The data on the Parallel System Bus is
burst transferred at the maximum bus speed of 40 Megabytes/second regardless of CPU bus performance,
Such performance is. possible due to decoupling of the CPU from the Parallel System Bus.
o
MULTIPROCESSOR ARCHITECTURE
~
LOCAL
RESOURCES
~
~
PROCESSOR
PROCESSOR
PROCESSOR
i'rLOCAL
i'rLOCAL
i'rLOCAL
.JYUS
.JYUS
.JYUS
G GGG
290145-1
Figure 1-1
6-150
October 1988
Order Number: 290145-002
82389
1.0 MPC 82389 INTRODUCTION
1.1
1.2
1.3
1.4
MPC Functional Overview
Major Operations of the MPC
Message Passing Protocol
Compatibility with BAC/MIC Interface Designs
2.0 MPC 82389 INTERFACES
2.1
2.2
2.3
2.4
2.5
2.6
Local Bus (Host)
PSB Bus
Interconnect Bus
Dual·Port Memory Interface
Basic Implementation of the MPC
Implementation with Dual-Port Memory
3.0 MPC 82389 INTERPROCESSOR COMMUNICATION
3.1 Communication Protcol
3.1.1
Unsolicited Message Passing
3.1.2 Solicited Message Passing
3.2 Bus Bandwidth
4.0 MPC 82389 PIN DESCRIPTION
4.1
4.2
4.3
4.4
4.5
PSB Signals
Dual-Port Memory Signals
Local Bus Signals
Interconnect Bus Signals
Power and Ground Signals
5.0 MPC 82389 MECHANICAL DATA
5.1
5.2
Pin Assignment
Package Dimensions
6.0 MPC 82389 ELECTRICAL DATA
6.1
6.2
6.3
Maximum Ratings
D.C. Specifications
A.C. Specifications
7.0 REFERENCE DOCUMENTS
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82389
1.0 MPC 82389 INTRODUCTION
The Message Passing coprocessor 82389 is a highly
integrated CMOS VLSI device to interconnect intelligent boards in a MULTIBUS II system environment.
The parallel system bus of the MBII architecture definition however allows existence of intelligent and
non-intelligent boards in the system.
This section of the data sheet describes the device
in general including the definition of message passing protocol and the subsequent sections will contain the detailed features of the device. Please refer
to the MPC User's Manual for more details.
1.2 Major Operations of theMPC
82389
-
-
-
1.1 MPC 82389 Functional Overview
The MPC 82389 is a Bus Interface Controller designed to offload the host CPU for interprocessor
communication on the PSB network, and it's primary
function is to support the communication protocol
standard defined for the PSB bus (message passing). The device provides both the physical and data
link support. By standardizing the signal interface
(physical), it allows multiple vendors to offer standard add-on products for the user and at the same
time it reduces costly overheads for the suppliers.
The data link protocol is completely handled by the
MPC 82389 including packetization after receiving
data from the local interface, bus arbitration, burst
transfer and error detection without the CPU intervention.
The PSB bus standard is defined for easy access
and sharing of resources in a distributed processing
environment. The MPC 82389 complements this
standard by providing an optimized interface for the
PSB bus usage at its maximum bandwidth.
The MPC 82389 also features three additional interfaces for use on a processor board.
Local Bus Interface for Host independent CPU.
The CPU can be 8, 16 or 32 bits wide.
Interconnect Bus for interfacing to a low-cost microcontroller. The interconnect bus has a local address space which can be accessed by other agents
on the PSB bus via the MPC.
Dual-Port Memory Interface to support an alternative communication approach which may coexist
with the message passing method.
-
-
Support of both unsolicited and solicited ~es
sage transfers. This interprocessor communIcation protocol allows an intelligent agent on the
PSB bus to communicate to another without any
CPU intervention and at rates approaching the
PSB bus bandwidth.
Support of single cycle accesses by the host
processor to memory and 110 locations resident
on the PSB bus. Bus architecture, parity generation and error detection is completely handled by
the MPC 82389 coprocessor.
Support of accesses to local interconnect space
by both the host processor and other agents on
the PSB bus.
Support of accesses by the host processor to
interconnect location assigned to other PSB bus
agents.
Support of accesses to local, dual-port memory
by other agents on the PSB bus.
1.3 Message Passing Protocol
The Multibus II architecture defines the data transfer
protocol between agents on the PSB bus as Message Passing.
Message Passing allows the PSB agents to transfer
variable amounts of data at rates approaching the
maximum bus speed. The MPC 82389 fully supports
the standardized data link protocol designed for the
PSB and the entire handshaking between agents on
the PSBbus is handled by the MPC 82389 without
the CPU intervention.
There are two types of messages that can be transmitted from one PSB agent to another: Unsolicited
Messages and Solicited Messages.
Unsolicited Messages-An unsolicited message is
an intelligent interrupt also called virtual interrupt.
This unsolicited message, as the name implies, is an
asynchronous event to notify the receiving agent to
prepare for the receipt of Solicited Messages. The
message is in the form of a packet and it consists of
information about the interrupt. By providing such intelligence the receiving agent's CPU do not have to
poll for information, thus resulting in minimal latency.
Solicited Messages-The solicited messages are
the actual data that are transmitted from one MPC to
another. The data is once again broken into packets
and these packets are transferred using the negotiation (handshaking) process which are synchronized
by the MPC 82389 coprocessors.
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82389
1.4 Compatibility with BAC/MIC
Interface Designs
The Bus Arbiter Controller (BAC) and Message Interrupt Contoller (MIC) were the first support components for the Parallel System Bus. The BAC implemented the full arbitration, requestor, and replier
functions of the PSB. The MIC supported the transmit and receiving of minimum size unsolicited (interrupt) messages.
To ensure future compatibility with the MPC 82389
implementation, the BAC/MIC architecture was put
on a module called the docket for direct incorporation onto the base-board. The PSB implementations
for the MPC and the BAC/MIC docket are compatible in all respects. These implementations may coexist on the PSB bus of the same system. For the
host and microcontroller interfaces, compatibility is
maintained for message and interconnect space operations. It is, thus, possible to replace the BAC/MIC
docket with the MPC at little impact to the board
design.
Software initialization of the operating parameters
for the MIC is possible through the Configuration
Register to support host widths of 8, 16 or 32 bits.
The MIC supports a host width of 8 bits only. Both
implementations present similar software interfaces
for the sending and receiving of interrupts. For details about the initialization procedures and interrupt
protocols, please refer to the MPC Users's Manual,
Part Number: 176526.
The MPC offers capabilities and performance far superior to the BAC/MIC implementation. Using the
MPC, interrupt handling at the host interface can be
improved by over an order of magnitude. Whereas
the MIC can handle only minimum 4-byte interrupts,
the MPC enables up to 28 bytes of data to be sent
and received along with each interrupt. Further, the
MPC has dedicated support for DMA based solicited
message transfer.
2.0 MPC 82389 INTERFACES
The MPC 82389 features 4 interfaces: the local CPU
bus for processor interface, the interconnect bus for
8-bit microcontroller interface, the Parallel System
Bus interface and the dual-port memory interface.
LOCAL BUS INTERFACE
INTERCONNECT
SPACE BUS
DUAL PORT MEMORY
CONTROL INTERFACE
IPSB BUS INTERFACE
290145-2
Figure 2-1. MPC Bus Interfaces
6-153
infef
82389
2.1 Local Bus
2.2 Parallel System Bus
The local bus of the MPC 82389 is used to interface
to a host processor. The CPU can be 8, 16, or 32
bits wide and the interface is processor independent.
The MPC 82389 provides a full 32-bit interface to
the PSB bus and participates in arbitration, requestor control, replier control and error handling.
The local bus interface supports direct references to
memory, I/O and interconnect address space on the
PSB bus. It also supports references to local interconnect space and the full message passing protocol. The entire local bus interface can be categorized into three sub-interfaces: register, reference
and OMA.
2.2.1 ARBITRATION
2.1.1 REGISTER INTERFACE
The MPC 82389 local bus register interface is used
for message operations and access to the interconnect space. These operations are asynchronous to
the bus clock or interconnect bus operation.
2.1.2 REFERENCE INTERFACE
The MPC 82389 local bus reference interface supports direct references to memory, I/O and interconnect address space on the PSB bus. Memory and 1/
references are initiated by the CPU to the MPC.
The MPC responds by putting the CPU on hold while
arbitrating for PSB bus access. The CPU is held in
WAIT state until the operation is complete or a bus
exception occurs on the PSB bus. The reference interface supports both read and write to the registers.
The local interconnect address space is differentiated from the interconnect address on the PSB bus by
the bit pattern stored in the slot address register of
the MPC.
o
2.1.3 DMA INTERFACE
The OMA interface transfers data between local
memory and the MPC 82389 during solicited message operations. The MPC provides both the input
and output channels to the PSB bus. The number of
transfers to or from the MPC is determined by the
maximum size of the packet buffer (32-byte) or completion of the solicited transfer, whichever is less.
The OMA interface is designed to operate on either
a read or write command to allow two-cycle operation or fly-by transfers. For two-cycle operation, the
OMA uses a read operation to fetch data from the
MPC and a write to put data into the MPC. Conversely, a fly-by read or write operation occurs correspondingly to memory write or read operation.
The OMA interface to the MPC performs best with
aligned transfers. However, for compatibility with existing software, the MPC supports operations of arbitrary byte stri ngs.
The MPC 82389 initials PSB bus access arbitration
upon request generated inside the MPC. This request couid be the result of a synchronized PSB bus
reference request (memory, 1/0 or interconnect) or·
a message packet transmit request from the CPU.
ThePSB bus arbitration specification can be referred in the document, MPC User's Manual, Part
Number: 176526.
2.2.3 REPLIER CONTROL
The MPC 82389 as a replier supports interconnect
space reference and message reception. It gets into
replier mode When a match is detected between the
assigned slot 10 and the address on the PSB bus.
The interface space microcontroller is alerted of the
replier mode condition. The address comparison is
disabled when the MPC is the bus owner.
The MPC allows interconnect space to be locked
from the PSB bus. This inhibits local bus interface
access requests.
2.2.4 ERROR HANDLING
The MPC 82389 monitors errors generated during
the transfer operation. It provides error checking on
incoming interconnect references that match the
slot 10. If an exception occurs on the PSB bus while
an interconnect operation is in progress, the MPC
provides for a graceful recovery.
2.3 Interconnect Bus
The Interconnect bus of the MPC 82389 has a simple 8-bit interface. A low-cost microcontroller can be
interfaced to perform board configuration at startup
and other tasks like local diagnostics.
The Interconnect space of an agent has a 512-byte
register range. Within this space the microcontroller
can store the local operating and configuration parameters associated with the agent. For example local diagnostics can be executed out of the microcontroller and the results posted in the Interconnect
space. IEEE 1296 specifications require the first record in the Interconnect space to contain the board
10 and Intel recommends other record types. Refer
to Interconnect Interface Specification, Part Number: 149299.
6-154
82389
The MPC 82389 provides the path to access the
local Interconnect space. The references supported
are:
2.4 Dual-Port Memory Interface
The MPC 82389 supports the dual-port memory interface for those designs that must coexist with the
memory passing architecture.
1. CPU local bus to the local Interconnect space
2. CPU local bus to the Interconnect space of another agent on the PSB bus
3. From the PSB bus to the local Interconnect space
The local Interconnect accesses are identified as
slot IDs 24-31 and the Interconnect accesses on
the PSB bus are mapped as slot IDs 0-23.
The MPC participates in PSB bus handshake protocol, parity generation and checking and agent error
generation for local Interconnect accesses from the
PSB bus.
The Interconnect microcontroller is the master device on the bus and all other devices including the
MPC are slaves.
The dual-port services supported are: Address recognition, PSB bus replier handshake, error checking,
and bus parity generation and checking. A useful recovery mechanism is provided by the MPC should a
bus exception error occur while a dual-port memory
access is in progress. Although the MPC 82389 provides bus parity check it is the responsibility of the
memory controller to generate and check data parity.
2.5 Basic Implementation with the
MPC 82389
Figure 2-2 shows a basic implementation of the
MPC 82389. Included in this implementation is the
interconnect interface to a microcontroller, the CPU
interface and the PSB bus interface.
Address Buller lor Memory
and 110 references 10 PSB
Bus. This Buller Is nol
b~~T.s~g:l ~~~gri!~~i~~roC::.IS
RSTNC*
1-_-"""=--___
1~~~'B"
l
$IyRals
Parity
<3 ..
'> . .
iPsa
Bus
SYltemConlrol
<8 .. 4>
*
290145-3
Figure 2-2. MPC Implementation to Support References
6-155
82389
2.6 Implementation with Dual-Port Memory Interface
Figure 2-3 shows the logic required to implement dual-port operations.
_.
,IIEQ-
"".
_Do.
290145-4
Figure 2-3. The MPC Implemented with Dual-Port Memory
6-156
inter
82389
Message Passing over the PSB bus is completely
handled by the MPC 82389 coprocessor without
CPU intervention. The messages (data) are packetized in blocks of 32 bytes and burst transferred over
the PSB bus.
3.0 MPC 82389 INTERPROCESSOR
COMMUNICATION
A MULTIBUS II system can have up to 20 boards in
the slot backplane. Slot zero must have a Central
Services Module (CSM) which provides bus initialization and clocking. The remaining 19 slots can have a
mix of intelligent and non-intelligent boards. The intelligent boards will typically communicate over the
high speed PSB bus. Any processor based board
may contain an MPC 82389 for high speed communication and the MPC is designed to support the system performance and the data transfer speed of the
PSB bus. The MPC has an optimized PSB bus interface.
The decoupling is achieved by using very high speed
FIFOs of the MPC 82389. Nine 32-byte FIFOs are
used in the MPC 82389. Five of these FIFOs are
used for setting up the unsolicited messages (interrupts). One is used for output set up and the other
four for input set up of up to four unsolicited messages. For data transmission (solicited messages)
over the PSB, the MPC 82389 has two dedicated
solicited output and input channels. With each channel, dual 32-byte FIFOs are used to pipeline data
during output and input operation.
tLOCAL BUS
•
.. '"
'"
f-
~ 1=
~~
f-
t:
1= l1=
1=
~ I-
II-
~~
ff- ~
~~
t- lII- ~
~~
I-
tl- II-tlf-
t-
~
~
INTERRUPT
OUT
~
...
~
SOLICITED
OUT
INTERRUPT
IN
!
...
SOLICITED
IN
PSB
290145-5
Figure 3-1. The MPC Uses Nine 32 Byte FIFOs to Couple the Local and System Buses
6-157
82389
3.1 Communication Protocol
Any device with an interface to the PSB bus is
termed as an agent. The agents communicate over
the PSB bus and they completely offload the CPU
for other tasks. Each agent is assigned an 8-bit address for identification.
The mechanism used for interprocessor communication over the PSB entails a standardized data link
protocol, and a dedicated address space. The information which is packetized is transmitted to a dedicated address space instead of the target memory.
This addressing scheme serves to decouple the
CPU from the PSB bus. Packetization serves to limit
the time an agent has an access over the bus, thus
protecting against hogging of the bus by agents
which require transmitting a large amount of data.
The data link protocol called message passing includes two kinds of messages: unsolicited and solicited.
3.1.1 UNSOLICITED MESSAGE
Unsolicited message is an intelligent interrupt. It is a
virtual interrupt for the receiving agent and includes
AD <31...24>
AD<23 .•. 16>
~~
all the information required to service the interrupt. It
takes only 900 ns to send an unsolicited message
over the PSB bus, and since the receiving agent's
processor does not have to poll for servicing the
interrupt, this mechanism is fast and efficient.
The unsolicited message is sent as a packet consisting of up to 32 bytes, as shown in Figure 3-2. The
address field is 8 bits long. Up to 255 agents can be
addressed uniquely while one address is used for
broadcast function.
The general format for unsolicited messages varies
depending on the CPU bus width. There are other
variations depending on whether the CPU is receiving or transmitting the message and the type of unsolicited message.
Unsolicited messages are asynchronous in nature.
These unsolicited messages are used to set up solicited messages and contain Control and Command
information.
An unsolicited message consisting of 32 bytes takes
a maximum of 900 ns to transmit. The unsolicited
message packet without the optional 28-byte data
will take only 200 ns to transmit.
AD<15 ..• 8>
AD <7 ... 0>
SOURCE
ADDRESS
DESTINATION
ADDRESS
V//////"'-:: V///////: V///////
00
12('/W/1=NOT USED
L...-_ _ _.aI=AVAILABLE fOR
OPTIONAL DATA
290145-6
Figure 3-2. General Interrupt Message on the PSB
6-158
infef
82389
AD<31 .• 24>
AD<23 .. 16>
AD<15 .. 8>
AD<7 .. 0>
Source Add.
Byte 1
Dest. Add.
Byte 0
10
Byte 3
Type
Byte 2
Data, Byte 6
Data, Byte 5
Data, Byte 4
Data, Byte 11
Data, Byte 10
Data, Byte 9
Data, Byte 8
Data, Byte 15
Data, Byte 14
Data, Byte 13
Data, Byte 12
Data, Byte 19
Data, Byte 18
Data, Byte 17
Data, Byte 16
Data, Byte 23
Data, Byte 22
Data, Byte 21
Data, Byte 20
Data, Byte 27
Data, Byte 26
Data, Byte 25
Data, Byte 24
Data, Byte 7
Data, Byte 31
Data, Byte 30
Data, Byte 29
Data, Byte 28
Data, Byte 35
Solic. only
Data, Byte 34
Solic. only
Data, Byte 33
Solic. only
Data, Byte 32
Solic. only
Figure 3-3. General Message Packet Format on the PSB Bus
3.1.2 SOLICITED MESSAGE
Solicited message consists of the actual data to be
transferred from one agent to another over the PSB
bus. The data is packetized in blocks of 32 bytes for
transfer. Up to 16 Megabytes of data may be transferred in a single solicited message.
The transfer of data is negotiated between the transmitting and receiving agents via unsolicited messages. By using the acknowledge response method
through the unsolicited messages, the agents complete the transfer of data.
A solicited message contains one or more data
packets. The packetization of solicited messages is
handled by the MPC. The padding of header information at the transmitting end and the stripping of
this information out of the packet is solely the MPC
responsibility. The local CPU simply fills or empties
the FIFO over the local bus. The MPC also handles
the last packet fillers to maintain the 32-byte data
packet format. If necessary, during output the bytes
are padded and during input .the padded bytes are
stripped by the MPC.
For programming details consult MPC User's Manual, Part Number: 176526.
3.2 Bus Bandwidth
The advantages of decoupling the buses can be
summarized in Figure 3-4. The effective speed performance numbers are also listed. The first advantage is that no resource is held in wait states while
arbitration for another resource is occurring.· The
second advantage is that each transfer can occur at
the full bandwidth of the associated bus.
20 MBYTES/SEC SINGLE CYCLE
40 MBYTES/SEC BURST
32 MBYTES/SEC FOR MESSAGES
(32 BYTES IN 10 CLOCKS)
290145-7
Figure 3-4. Message Passing Performance Example
6-159
82389
4.0 MPC 82389 PIN DESCRIPTION
The MPC 82389 is packaged in a 149 pin package. The signals for the device are functionally divided by their
associated interfaces as shown in Figure 4-1 .
<
LOCAL BUS
A
I~I~
A
>
'"" ~'""
lAST
IWR
IRD
IAD<7 ••• 0>
IREO
"j
;;;
290145-8
Figure 4-1. MPC Functional Blocks
6-160
inter
82389
4.1 PSB Bus Signals
This section describes each of the PSB bus signals
that interface with the MPC. For complete descriptions of these signals, see the MULTIBUS II Architecture Specification, Part Number: 146077.
The PSB bus signals interfaced by the MPC 82389
fall into five groups, depending on function:
•
•
•
•
•
Arbitration Operation Signal Group
Address/Data Bus Signal Group
System Control Signal Group
Central Control Signal Group
Exception Operation Signal Group
Unless otherwise stated, all PSB bus signals are
synchronous to the bus clock.
4.1.1 ARBITRATION OPERATION SIGNAL
GROUP
The MPC 82389 interfaces directly with the Arbitration Operation Signal Group of the PSB bus. These
are all high-current drive, open-collector signals. Below is a description of each signal.
BREQ (Bus Request)
BREQ is a bidirectional open-collector signal that
connects directly to the PSB bus. As an input to the
MPC, it indicates that agents are awaiting access to
the bus. In fair access mode, this inhibits the MPC
from activating its own request. As an output, the
MPC asserts BREQ to request access to the PSB
bus.
ARB < 5.. 0 > (Arbitration)
ARB<5 .. 0> are the arbitration signals for the PSB
bus. At the MPC interface, these are bidirectional,
open-collector signals that connect directly to the
PSB bus. ARB<5 .. 0> are used during normal operation to identify the mode and arbitration priority of
an agent during an arbitration cycle to facilitate the
arbitration process. During system initialization
(while reset is active), the Central Services Module
(CSM) drives these signals to initialize slot and arbitration IDs.
4.1.2 ADDRESS/DATA BUS SIGNAL GROUP
This signal group includes a 32-bit multiplexed address/data path that interfaces to the PSB address/
data bus. The MPC also includes the byte parity signals present on the PSB bus BPAR <3 .. 0>. All signals in this group interface with the PSB bus through
bus tranceivers. For the MPC, this signal group also
includes signals to control these bus transceivers
(ADDIR and REFADR). These signals are described
next.
6-161
BAD<31 .. 0> (Buffered Address/Data)
BAD < 31 .. 0 > are the 32 buffered, multiplexed address/data signals that are bidirectional and provide
the interface to the PSB address/data bus. At the
MPC, these lines should be connected to the equivalent PSB bus AD signals using 74F245 or equivalent transceivers.
BPAR < 3..0 > (Buffered Parity)
BPAR are four signals that provide parity for the 4
bytes of the BAD bus. These bidirectional lines connect to the PSB bus PAR<3 .. 0> signals through a
74F245 or equivalent transceiver. These signals are
used to receive byte parity for incoming operations
and to drive byte parity for outgoing operations.
ADDIR (Address/Data Direction)
ADDIR is an output that provides direction control
over the transceivers driving and receiving
BAD<31..0> and BPAR<3 .. 0>. In the high state,
this signal causes the transceivers to place address/data information along with parity onto the
PSB bus. In the low state, this Signal causes address/data information and parity to be received
from the PSB bus.
REFADR (Reference Address Enable)
REFADR is an output used to enable external address buffers. Asserting this signal places address
information from the local bus onto BAD. The address path enabled by this signal is used for memory
and I/O references to the PSB bus and is not used
during message passing or for references to interconnect space on the PSB bus.
4.1.3 SYSTEM CONTROL SIGNAL GROUP
The MPC provides signals that are used to interface
to the System Control Signal Group of the PSB bus.
These signals are described next.
BSC < 9..0 > (Buffered System Control)
BSC<9 .. 0> is a group of ten bidirectional signals
that interface to the System Control Signal Group of
the PSB bus through 74F245 or equivalent transceivers. Direction control of the transceivers is provided by SCDIR < 1,0> (discussed next). Agents on
the PSB bus use the System Control Signal Group to
define commands or report status, depending on the
phase of the operation. See the MULTIBUS II Architecture Specification for more information on these
signals.
SCOIR < 1, 0> (System Control Direction)
SCDIR < 1, 0> are output signals that provide direction control of the 74F245 transceivers driving and
receiving BSC < 9.. 0 >. SCDIRO provides control for
BSC<9, 3 .. 0>, while SCDIR1 provides control for
inter
82389
BSC < 8..4 >. When either signal is high, the corresponding five bits of the BSC signal group are driven
onto the PSB bus. When either signal is low, the
corresponding five bits on the PSB bus are driven
onto the BSC signal group.
Table 4·1. Signal State During Reset
4.1.4 CENTRAL CONTROL SIGNAL GROUP.
The MPC provides several signals that interface directly or through transceivers to the Central Control
signal group of the PSB bus. These signals are described next.
BBCLK (Buffered Bus Clock)
BBCLK is buffered from the PSB bus BCLK signal.
This signal should be connected to BCLK using a
74AS1804 or equivalent inverting buffer. This clock
is used for all synchronous internal MPC timing.
LACHn (Latch n)
LACHn is an input signal used during initialization of
slot and arbitration IDs (where un" is the slot number). When the RESET signal is active, LACHn asserted indicates to an agent that a slot or arbitration
10 is available and should be latched. LACHn is an
active high input and should be connected to the
LACHn signal on the PSB bus with a 74AS1804 or
equivalent inverting buffer.
RESET
RESET is an input that, when asserted, places the
MPC in a known state. Only the parts of the MPC
involved with initialization of slot and arbitration IDs
remain unaffected. RESET is an active high input
and should be connected to the RST signal on the
PSB bus with a 74AS1804 or equivalent inverting
buffer.
Reset Condition
Table 4-1 summarizes the states of the signals while
the RESET signal is active.
Signal
Reset State
BREQ, ARB<5 .. 0>
BAD<31..0>
ADDIR
REFADR
BSC<9 .. 0>
SCDIR<1,0>
BUSERR
RSTNC
SEL
0<31..0>
WAIT
MINT, EINT
ODREQ, IDREQ
Z
Z
L
H
Z
L
Z(H)
L
H
Z
H
L
L
NOTES:
H - Electrical High State
L - Electrical Low State
Z - High Impedence
RSTNC (Reset Not Complete)
RSTNC is a bidirectional, open-collector signal with
high-current drive. It connects directly to the PSB
bus. As an input, RSTNC inhibits the MPC from initiating PSB bus operations. As an output, the MPC
asserts RSTNC to prevent PSB bus operation until
the agent is finished with initialization. The MPC asserts RSTNC whenever the RST signal is asserted
by the Central Services Module (CSM). After the
CSM deasserts RST and initialization of the local
agent is complete, the interconnect microcontroller
writes to a register within the MPC. The MPC then
deasserts RSTNC.
4.1.5 EXCEPTION OPERATION SIGNAL GROUP
The MPC interfaces with both signals of the Exception Operation Signal Group (part of the PSB bus),
as described below.
BUSERR (Bus Error)
BUSERR is a bidirectional, open-collector signal
with high-current drive. It connects directly to the
PSB bus. As an input, the MPC uses this signal to
detect bus errors signaled by other agents. As an
output, the MPC uses BUSERR to indicate parity errors detected on either the BAD or BSC signals and
to indicate handshake protocol violations detected
on the BSC signals.
TIMOUT (Time·Out)
TIMOUT is an input from the PSB bus used to detect
a time-out condition signaled by the CSM. TIMOUT
is an active high input to the MPC and must be connected to the TIMOUT signal of the PSB bus
through a 74AS1804 or equivalent inverter buffer.
6-162
infef
82389
control to allow operation with processors using 8-,
16-, or 32-bit data buses.
4.2 Dual-Port Memory Control Signals
The MPC provides the following signals to support
dual-port memory.
SEL (Select)
The MPC asserts SEL to indicate that a dual-port
memory access is in progress. The assertion of SEL
initiates the dual-port operation and during memory
reads, can be used to enable the dual-port data buffers onto the BAD bus. When the MPC completes the
PSB bus handshake on the PSB bus, or if the MPC
detects an exception, it deasserts SEL.
COM (Complete)
COM is an input to the MPC. The dual-port memory
controller asserts COM to indicate it is ready to complete dual-port access. COM is assumed to be synchronous to the bus clock. The MPC asserts the
Replier Ready (SC4) signal on the PSB bus on the
bus clock after the memory controller has asserted
COM. The memory controller cannot deassert COM
until the end-of-transfer (EaT) handshake is complete on the PSB bus. This requires that the memory
controller monitor the PSB bus for the EaT handshake.
ERR (Error)
ERR is asserted by the dual-port memory controller
to Signal a memory data parity error. ERR must be
stable (high or low) whenever COM is asserted. The
MPC responds to this signal by completing the replier handshake on the PSB bus using a "data error"
agent error code. This signal may be asynchronous
to the bus clock since it is qualified by the COM
signal.
4.3 Local Bus Signals
The MPC provides five signal groups that together
interface to the CPU's local bus. These local bus
signal groups are:
•
•
•
•
•
data
address and select
transfer control
interrupt
OMA control
All local bus signals are assumed to be asynchronous to the bus clock.
4.3.1 DATA BUS
The local data bus (0 <31 .. 0 » is a bidirectional
group of signals that transfers data between the
host CPU, OMA controller, or memory and the MPC.
Although this is a 32-bit interface, the MPC provides
Not all processors use the same byte order when
performing multiple data byte operations. For example, for a 16-bit write to memory, one processor may
carry the least-significant byte on local bus bits
0<7 .. 0> and the most-significant byte on bits
0< 15.. 8>, while another processor may carry the
least-significant byte on bits 0 < 15 .. 8> and the
most-significant byte on bits 0<7 .. 0>. For a given
agent, be sure to implement the processor interface
to maintain consistent byte addressability with all
other agents in the system.
4.3.2 ADDRESS AND SELECT SIGNALS
The address and status signals identify all MPC operations over the local bus.
A<5 .. 2> (Address)
The address inputs select MPC registers for message and interconnect space operations. A 1 and AO
are omitted to provide a consistent register address
for all data bus width options. These Signals are
qualified by commands in the MPC (for example, RO
or WR, defined in section 4.1.3.3). To the MPC, the
state of A < 5.. 2> must be stable within the specified
setup and hold window. The address values defined
by A < 5.. 2 >, and required to access MPC registers,
are provided in, "Programming the Host Interface"
of the MPC User's Manual, Part Number: 176526.
BE<3 .. 0> (Byte Enable)
These input signals identify valid bytes for memory
and I/O reference operations and also provide data
path control for register and OMA operations. The
assertion of a byte enable signal validates a particular byte on the data bus. Signals BE < 3.. 0 > correspond to data bytes 3 through 0 on the data bus
(where byte 3 is 0<31 .. 24». Only combinations
supported by the PSB bus specification are valid.
Valid combinations are summarized in Table 4-2.
Values not shown in the table are illegal and will
result in unpredictable operation. These signals are
qualified by commands (for example, RO or WR) in
the MPC and must be stable within the specified setup and hold window.
Operation with 32-bit local buses requires that all
byte enable and data Signals are used. For 16-bit
local buses, BE2 and BE33 are deasserted, BE1 and
BE2 are used to indicate which of the two bytes will
contain valid data, and only 0 < 15 .. 0> are used. For
8-bit local bus operations, BE3 is asserted, BE2 is
deasserted, and BE1 and BEO are used to select
which byte of the PSB bus will carry the valid data
byte. This mode uses only 0<7 .. 0> (on the local
bus). Note that during all read operations, the MPC
drives 0<31 .. 0>.
6-163
inter
82389
Table 4-2. Valid Byte Enable Combinations'
Local Bus
BE3
BE2
BE1
BEO
L
L
H
L
H
H
L
H
H
H
L
L
L
L
L
L
L
H
H
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
H
H
H
L
H
L
PSB Bust
031024
023016
01508
0700
A031A024
A023A016
V3
V3
V2
V2
V2
V1
V2
V1
V1
V1
VO
V3
V3
x
x
x
V2
V2
V2
x
V2
x
x
x
x
x
x
x
x
x
x
x
V3
x
x
V3
x
x
x
x
x
x
VO
x
x
x
V2
x
x
x
x
x
V1
V1
x
VO
x
x
x
V1
x
VO
VO
VO
x
x
x
x
A015A08
A07AOO
V1
V1
V1
V3
V1
V1
V3
x
V1
x
VO
x
VO
x
x
x
x
x
VO
V2
x
VO
x
V2
x
VO
x
VO
NOTES:
L - Electrical low state (active)
H - Electrical high state (inactive)
Vx - Valid data bytes
x - Active bytes with undefined data
t - For this PSB bus, these combinations apply to reference operations, not message space operations
MEMSEL (Memory Select)
This MPC input signal, when asserted, indicates to
the MPC that the current operation is a memory reference to the PSB bus. It is qualified by the assertion
of AD or WR (defined in section 4.3.3). The state of
MEMSEL be must stable within the defined set-up
and hold window. Additionally, for MEMSEL to be
valid, the signals 10SEL, REGSEL, IDACK, and
ODACK must not be active during the same setup
and hold window. (IDACK and ODACK are defined
later in section 4.3.5.)
10SEL (110 Select)
This input signal, when asserted, indicates to the
MPC that the current operation is an I/O reference
to the PSB bus. It is qualified by the assertion of RD
or WR (defined in section 4.3.3). The state of
10SEL must be stable within the defined setup and
hold window. Additionally, for 10SEL to be valid, the
signals MEMSEL, REGSEL, IDACK, and ODACK
must not be active during the same setup and hold
window. (IDACK and ODACK are defined later in
section 4.3.5.)
REGSEL (Register Select)
This input signal, when asserted, identifies an operation as an MPC-register access. The host CPU asserts REGSEL to set up the MPC for message or
interconnect space operations and these are
mapped as register operations. REGSEL is qualified
by the assertion of AD or WR (defined in section
4.3.3). The state of REGSEL must be stable within
the defined setup and hold window. Addition-
ally, for REGSEL to be valid, the signals MEMSEL,
10SEL, IDACK, and ODACK must not be active during the same setup and hold window. (IDACK and
ODACK are defined later in section 4.3.5).
LOCK
This input signal allows back-to-back operations to
be performed on the PSB bus or to local interconnect space. When LOCK is asserted, any resource
accessed by the operation (PSB bus or local interconnect space) is locked until LOCK is deasserted.
4.3.3 TRANSFER CONTROL SIGNALS
Transfer control to the MPC over the local bus is
provided by two command signals (Read and Write)
and a wait signal. This handshake provides fully interlocked (two-sided handshake) operation.
RO (Read)
This input signal, when asserted, generally initiates a
read operation. The CPU asserts RD to initiate read
operations of MPC registers. The CPU also asserts
RD to initiate read operations of 1/0 and memory
locations present on the PSB bus. The DMA controller asserts RD to qualify DMA cycles. In this last
case, the MPC does not interpret RD as an indicator
of the data transfer direction, but only to qualify the
DMA acknowledge signal (see definitions for
ODACK and IDACK). RD must transition cleanly,
since it is used to latch other signals that define the
parameters of the operation.
6-164
82389
WR (Write)
This input signal, when asserted, ~erally initiates a
write operation. The CPU asserts WR to initiate write
operations of MPC registers. The CPU also asserts
WR to initiate write operations of I/O and memory
locations present on the PSB bus. The DMA controller asserts WR to qualify DMA cycles. In this last
case, the MPC does not interpret WR as an indicator
of the data transfer direction, but only to qualify the
DMA acknowledge s.!£!:!.al (see definitions for
ODACK and IDACK). WR must transition cleanly,
since it is used to qualify other signals that define
the parameters of the operation.
WAIT
WAIT is an MPC output signal used to delay (or suspend) a local bus operation during an access to an
asynchronous resource via the MPC. The MPC asserts WAIT to the local CPU for memory, I/O, and
interconnect accesses to the PSB bus; and for local
interconnect accesses. WAIT, when asserted, allows time for the accessed resource to become
available. The MPC asserts WAIT after the CPU has
asserted the command signal (RD or WR). On the
PSB bus, the MPC deasserts WAIT after either the
PSB bus EOT handshake or an exception has occurred. For accesses to local interconnect space,
the MPC deasserts WAIT after the interconnect operation is complete.
4.3.4 INTERRUPT SIGNALS
Interrupt signals are used to inform the host CPU
that the MPC requires service. The MPC provides
two signals: one for message operations and one for
reference errors.
MINT (Message Interrupt)
The MPC asserts this output signal for all messagerelated signaling to the host CPU. This includes the
arrival of an unsolicited message, an available transmit FIFO buffer, the completion of a solicited transfer, and an error on message transfer.
EINT (Error Interrupt)
The MPC asserts this output signal to the CPU to
indicate errors related to memory, I/O, or interconnect space operations (Le., all except message operations). Internal registers in the MPC provide details of the error via interconnect space.
4.3.5 DMA CONTROL SIGNALS
The MPC provides several DMA control signals to
support an external DMA controller. A DMA controller is required to support solicited message operations.
ODREQ (Output Channel DMA Request)
ODREO is an output signal the MPC asserts to enable DMA transfer of data to the MPC (Le., output to
the PSB bus). This signal behaves as a normal DMA
request line. For a solicited message output operation, the MPC asserts ODREO when a solicited output packet buffer is empty and as long as the MPC is
in the transfer phase (the Buffer Request unsolicited
message has been sent). The DMA controller responds by performing DMA transfers to the MPC for
transfer to the receiving agent.
IDREQ (Input Channel DMA Request)
The MPC asserts this output signal to enable DMA
transfer of data from the MPC (Le., input from the
PSB bus). This signal behaves as a normal DMA
request line. For a solicited message input operation, the MPC asserts IDREO after a solicited input
packet buffer is full and as long as the MPC is in the
transfer phase. The DMA controller responds by
performing DMA transfer from the MPC. IDREO remains asserted until the packet is transferred to
memory.
ODACK (Output Channel DMA Acknowledge)
ODACK is an input signal asserted by the DMA controller in response to the assertion of ODREO by the
MPC. The DMA controller asserts ODACK to set up
the MPC for the DMA transfer from local memory (or
the controller) to the MPC. The assertion of ODACK
is qualified by the assertion of RD or WR by the
MPC. The direction of data transfer with respect to
the MPC is controlled by the request signal (IDREO
or ODREO) and the acknowledge signal (IDACK or
ODACK). The command signal (RD or WR) only
qualifies the acknowledge signal (IDACK or
ODACK). The state of ODACK must be stable within
the defined setup and hold window. Additionally, for
0iJACR' to be valid, the signals MEMSEl, 10SEl,
REGSEl, and IDACK must not be active during the
same setup and hold window.
IDACK (Input Channel DMA Acknowledge)
IDACK is an input signal asserted by the DMA controller in response to the assertion of IDREO by the
MPC. The DMA controller asserts IDACK to set up
the MPC for the DMA transfer from the MPC to the
DMA controller (or local memory). The assertion of
IDACK is qualified by the assertion of RD or WR by
the DMA controller. The direction of data transfer
with respect to the MPC is controlled by the request
signal (IDREO or ODREO) and the acknowledge signal (IDACK or ODACK). The command signal (RD or
WR) only qualifies the acknowledge signal. The
state of IDACK must be stable within the de-
6-165
inter
82389
fined setup and hold window. Additionally, for fE5ACK
to be valid, the signals MEMSEl, IOSEl, REGSEl,
and OOACK must not be active during the same setup and hold window.
4.5 Power and Ground Signals
The MPC requires supply voltage and ground connections at the pin numbers listed below.
4.4 Interconnect Bus Signals
Vee
Ground
The interconnect bus signals provide a simple interface to a microcontroller for implementation of interconnect space. All interconnect bus signals are
asynchronous to the bus clock and to the local bus
.
signals.
04
M4
N8
M12
012
C7
J3
N4
N6
N9
N11
N13
K13
F13
C12
08
C5
C3
IAD<7 ..0> (Interconnect Address/Data)
IAO<7 .. 0> is an 8-bit, bidirectional, multiplexed address and data bus intended to. interface directly to a
microcontroller. In addition to the MPC, other interconnect registers can be connected to this bus.
IREO (Interconnect Request)
The MPC asserts this output signal when an interconnect operation has been requested from either
the local bus or the PSB bus. The MPC deasserts
IREO after the microcontroller has written to the Interconnect Reference Arbitration register.
lAST (Interconnect Address Strobe)
lAST is an input signal from the microcontroller and,
when asserted, indicates that a valid address is on
the interconnect bus. lAST may be directly connected to the ALE (Address latch Enable or equivalent)
output of most microcontrollers. lAST must provide
clean transitions.
IRD (Interconnect Bus Read)
IRO is an input signal. The microcontroller asserts
IRO to perform a read operation to one of the MPC
interconnect interface r~ters. IRO must provide
clean transitions. When IRO is asserted in conjunction with the IWR signal, all MPC outputs are disabled.
IWR (Interconnect Write)
IWR is an input signal. The microcontroller asserts
IWR to perform a write operation to one of the MPC
interconnect interface registers. IWR must provide
clean transitio~When IWR is asserted in conjunction with the IRO signal, all MPC outputs are disabled.
5.0 MPC 82389 MECHANICAL DATA
The MPC 82389 is packaged in a149 lead pin grid
array. The square package has a 15 x 15 grid layout
with the outer 3 rows used along each edge.
5.1 Pin Assignment
The MPC 82389 pinout as viewed from the top side
of the component is shown in Figure 5-1. When
viewed from the pin side, the component pin layout
is shown in Figure 5-2.
To reduce possible noise problems on the board,
Vee and Vss must be connected to multiple supplies. The board should be laid out with Vee and
Ground planes for power distribution and the components Vee and Vss must be connected to the appropriate power plane.
5.2 Package Dimensions
The 82389 is packaged in a 149-pin Ceramic Pin
Grid Array (PGA). The pins are arranged 0.100 inch
(2.54 mm) center-to-center, in a 15. x 15 matrix.
Please refer to Figure 5-3 for case outlines;
A wide variety of sockets are available including the
zero-insertion force socket for prototyping.
6-166
intJ
82389
2
3
4
5
o
o
o
o
o
o
o
o
o
o
o
o
o
02
AS
BE3
o
BE2
o
REGSEL
01
04
03
A4
Vss
o
o
A3
0
BEl
A2
07
06
05
09
DB
o
Vss
7
o
012
o
011
o
010
o
014
o
013
o
Vee
8
10
o
o
017
020
o
o
016
019
o
o
015
o
o
Vee
Vss
018
o
023
o
022
o
021·
11
o
o
12
o
026
028
025
027
o
13
o
030
14
o
031
lADS
0
000
Vss
IA03
IA04
000
o
o
IA07
A
000
029
024
Vee
15
IAOl
IA02
IA06
o
IWR
C
oiRii
o
000
BED
IAOD
lAST
IREO
METAL LID
o
10REO
o
MEMSEL
o
(TOP VIEW)
IOSEL
000
000
OOREO
10ACK
OOACK
BA02
ViR
WAIT
BA05
o
EINT
LOCK
o
ERR
BA08
Vss
o
BSC2
BSCO
o
BSC6
0
0
BSC4
Vee
'0
BScii
o
o
o
ARBl
o
BAOll
BA012'
K
000
BA013
BSCl
BSC5
H
BA01D
000
0
BSC7
BAD9
Vss
BSC3
SCOIRO
BA07
0
000
BSC9
BA06
COM
000
SEL
G
000
000
MINT
BA04
000
000
iID
BA03
o
Vss
o
ARB3
o
o
Vee
o
ARBS
o
ARB4
o
000
o
VSS
Vss
REFAOR
Vee
o
000
BREO
o
BUSERR
o
LACHn
o
SCOIRl
ARBo
ARB2
RSTNC .
AOOIR
TlMOUT
BBCLK
2
3
4
5
6
7
8
BPAR3
o
RESET
o
0
o
0
Vss
BA027
Vss
o
o
BA030
o
0
BPAR2
BA031
10
11
0
BA028
BA015
o
BA025
BAOH
o
BA019
0
BAD23
BA018
0
BA020
o
BA021
N
P
a
12
13
14
15
290145-9
Figure 5-1. MPC 82389 Pinout-View from Top Side
6-167
L
000
BA016
BPARO
BPARl
BA014
82389
15
A
o
IA07
o
lADS
14
o
031
0
lADS
13
o
030
12
o
o2S
11
o
o2S
000
029
027
025
o
023
o
022
o
o
020
o
o
0
0
0
0
o
o
IWR
IA04
IA03
VSS
024
021
o1S
oiiffi
o
0
o
IA02
IAOl
Vee
4
3
o
o
o
o
o
0"
07
04
02
DO
o
o
o
013
011
os
oos
o
o
o
o
o
o
017
014
o
019
5
7
S
10
01S
o
o
012
lAST
o
o
A4
BE3
o
o
o
o
VSS
Vee
VSS
G
VSS
o
o
o
o
o
10SEL
o
(SOTTOM VIEW)
OoACK
000
BA07
BAoS
BA09
WAIT
BA012
BAOll
VSS
o
BAolS
o
N
o
BA014
COM
0
0
0
o
BAolS
Vet
Vee
0
o
Vss
o
o
o
o
BSCl
BA017
BAD19
o
o
o
IDACK
0
lOR EO
o
OoREO
WR
iID
LOCK
MINT
ERR
EINT
000
BA013
BA020
o
MEMSEL
0
REGSEL
000
VSS
000
BAolS
o
BEl
o
BE2
000
BAoS
000
K
A3
000
BAoS
000
BAol0
A2
BEO
000
BAoO
AS
o
010
IAOO
BAol
01
VSS
Vee
000
IREO
03
05
015
o
09
o
BAD27
o
o
VSS
o
o
00
BPARO
o
BAD22
BA024
BAD2S
BA029
BAD31
BPAR2
15
14
13
12
11
10
VSS
o
Vee
RESET
o
o
REFAoR
o
o
VSS
o
o
ARBS
o
o
Vss
o
BSCO
SEL
000
BSC4
BSC3
o
0
BSCS 'SCDIRO
o
o
BSC2
o
BSC9
o
BBCLK
TIMOUT
AoolR
RSTNC
ARB2
ARBO
SColRl
BSCS
S
7
6
5
4
3
2
1
290145-10
Figure 5·2. MPC 82389 Pinout-View from Pin Side
6-168
inter
82389
Table 5·1
Signal and
Characteristic
Pin #
Vee
A5
A4
A3
A2
BE3
BE2
BE1
BEO
10SEL
MEMSEL
REGSEL
10ACK
OOACK
10REO
OOREO
WR
RO
WAIT
Vss
MINT
EINT
LOCK
ERR
SEL
COM
BSC9
BSC8
BSC7
BSC6
BSC5
BSC4
BSC3
BSC2
BSC1
BSCO
SCOIR1
SCOIRO
I
I
I
I
I
I
I
I
I
I
I
I
I
a
a
I
I
a
a
a
I
a
a
I
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
a
a
Vee
Vss
ARB5
ARB4
ARB3
ARB2
ARB1
ARBO
I/O,OC
I/O,OC
I/O,OC
I/O,OC
I/O,OC
I/O,OC
Vss
BREO
TIMOUT
IREO
Signal and
Characteristic
I/O,OC
a
a
04
B1
C2
02
03
C1
01
E2
E3
F3
F2
E1
G2
G3
F1
G1
H2
H1
H3
J3
J1
K1
J2
K2
L1
K3
N1
01
P2
P1
N3
M3
M2
M1
L3
L2
02
N2
M4
N4
A15
P5
P4
04
P3
03
N6
P6
07
E15
REFAOR
AOOIR
BPAR3
BA031
BA030
BA029
BA028
BA027
BA026
BA025
BA024
BA023
BA022
' BA021
BA020
BA019
BA018
BA017
BA016
BA015
BA014
BA013
BA012
BA011
BA010
BA09
BA08
BA07
BA06
BA05
BA04
BA03
BA02
BA01
BAOO
BPAR2
BPAR1
BPARO
a
a
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Vee
Vss
Vss
Vee
Vss
Vss
Vss
BBCLK
LACHn
RESET
RSTNC
Signal and
Characteristic
Pin #
I
I
I
IIO,OC
Vss
NOTES:
I = Input signal
= Output signal
1/0 = Input or output signal
OC = Open-collector signal
a
6-169
N7
06
P9
011
P11
012
P12
N12
013
P13
014
P14
015
P15
N15
N14
M15
M14
M13
014
L14
L13
K15
K14
J15
J14
J13
H15
H14
H13
G15
G14
G13
F15
F14
010
P10
N10
N8
N9
N11
M12
N13
F13
K13
08
P8
09
05
C3
lAST
IRO
IWR
IA07
IA06
IA05
IA04
IA03
IA02
IA01
IAOO
Pin #
I
I
I
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Vee
Vss
031
030
029
028
027
026
025
024
023
022
021
020
019
018
017
016
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
DO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
110
1/0
1/0
110
110
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Vee
Vss
Vss
BUSERR
I/O,OC
E14
015
C15
A15
B15
B14
C15
C13
014
013
E13
012
C12
A14
A13
B13
A12
B12
A11
B11
C11
A10
B10
C10
A9
B9
C9
A8
B8
C8
A7
B7
A6
B6
C6
A5
B5
A5
B4
C4
A3
B3
A2
B2
A1
C7
08
C5
P7
i
040.00
-A-
35.56
2.5.
2.22
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~
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INDEX MARK
04.0
290145-11
NOTE:
Dimensions in mm.
~
'1iiI
©
2$
~
~
C::(I
=
©
~
inter
82389
NOTE:
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only
and functional operation at these or any other conditions above those listed in the operational sections of this specification is not implied.
6.0 MPC 82389 ELECTRICAL DATA
This section provides detailed target A.C. and D.C.
specifications for the MPC 82389.
6.1 Maximum Ratings
Operating Temperature
(Under Bias) ................. -10°C to
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Although the 82389 contains protective circuitry to
resist damage from static electrical discharges, always take precautions against high static voltages
or electric fields.
+ 85°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on Any Pin .......... -0.5V to Vee
+ 0.5V
Power Dissipation .......................... 2.5W
6.2 D.C. Specifications vee =
5.0V ±10%, TA
= O°Cto + 70°C
Table 6-1_ D.C. Specifications
Symbol
Min
Max
Units
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL1
Output Low Voltage
0.45
V
IOL Max
VOL2
Output Low Voltage
Open Collector
0.55
V
IOL Max
VOH
Output High Voltage
V
IOH Max
lee
Power Supply Current
400
mA
±10
VIL
Parameter
Vee
+
0.5
2.4
Test Conditions
V
IL
Input Leakage Current
/LA
OV s VIN s Vee
1L1
Open Collector
±100
/LA
O.4V s VIN s 2.4V
Leakage Current
±400
/LA
OV s VIN s Vee
IL2
BBCLK Input Leakage Current
±100
/LA
OV s VIN s Vee
IOL
Output Low Current
4.0
mA
VOL = 0.45V
IOL1
Open Collector Output
Low Current
60.0
mA
VOL = 0.55V
IOL2
ADDIR and REFADR
Output Low Current
8.0
mA
VOL - 0.45V
IOH
Output High Current
-1.0
mA
VOH = 2.4V
CI
Input Capacitance
10
pF
fe = 1 MHz, 25°C (Note 1)
CIO
I/O Capacitance
20
pF
fe = 1 MHz, 25°C (Note 1)
CeLK
Clock Input Capacitance
15
pF
fe = 1 MHz, 25°C (Note 1)
Coe
Open Collector Capacitance
20
pF
fe = 1 MHz, 25°C (Note 1)
NOTE:
1. Sampled only. not 100% tested.
6-171
inter
82389
6.3 A.C. Specifications
The A.C. specifications for the MPC 82389 are specified in Tables 6-2, 6-3 and 6-4 and Figures 6-2, 6-3,
6-4 and 6-5. Figure 6-1 specifies the test points for
measuring the A.C. parameters. Table 6-2 and Figures 6-2 and 6-3 specify the A.C. parameters for the
local bus. Table 6-3 and Figure 6-4 specify the A.C.
parameters for the interconnect bus. Table 6-4 and
Figure 6-5 specify the A.C. parameters for the PSB
bus. Figure 6-6 defines the test load for the A.C.
specifications.
OUTPUT WAVEFORM
2.4V
0.4V
INPUT WAVEFORM
290145-12
Figure 6-1. A.C. Test Waveforms
Table 6-2. Local Bus A.C. Specifications (Vee
Symbol
Parameter
=
5V ± 10%, TA
Min
Max
=
O·C to
Units
Address and BE Setup to Command Active
30
ns
Select and DACK Setup to Command Active
24
ns
Address, BE, Select and DACK
Hold from Command Active
10
ns
t3
Time between Commands
35
4
Command Inactive to Read Data Disable
(Note 5)
ts
Read Data Hold from Command Inactive
3
ns
ta
Read Data Enable from Command Active
0
ns
t7
WAIT Active from Command Active
ta
Command Inactive from WAIT Inactive
t1
t2
0
Command Active to Write Data Valid
t11
Write Data Hold from WAIT Inactive
t12
Command Active to LOCK Active (Note 1)
t13
LOCK Hold from WAIT Inactive (Note 2)
t14
Command Active Time
t1S
Read Data Valid from Command Active
t16
Write Data Setup to Command Inactive
-Registers
-DMA
ns
ns
CL
= 50 pF
CL
= 150 pF
ns
50
200
WAIT Inactive to Read Data Valid
t10
Test
Conditions
ns
24
35
t9
+ 70· C)
0
ns
ns
ns
100
0
70
ns
ns
,
ns
60
35
25
ns
CL
= 150 pF
ns
ns
5
t17
Write Data Hold from Command Inactive
t18
Command Active to MINT or DREQ Inactive
(Notes 3, 4)
70
ns
CL
= 50 pF
t19
Command Active to DREQ Inactive
(Note 4)
45
ns
CL
= 50 pF
ns
NOTES:
1. Required to guarantee locking of resource.
2. Required to guarantee resource remains locked.
3. MINT deassertion only if no other sources are pending.
,
4. For DREQ inactive timing, t19 applies to a normal last transfer deassert condition and t1B to an error deassert condition.
5. Disable condition occurs when the output current becomes less than the input leakage specification.
6-172
82389
BE3-BEO
MEMSEL
IOSEL
REGSEL
A5-A2
"\
-f
. -1
~t1~ ~
t2
Ri5
or WR
WAIT
t3
r-
~
~
t=t8~1
~"~
~
~,.~( ~~t9-1X ~~'I
JC)t5
031-00
(OUT Of MPC)
031-00
(INTO MPC)
.
I
~t10~ ~
X
~t12j
LOCK
~
VAllO
VAllO
t"
~
r-
X
I
t '3
t:
-f
290145-13
Figure 6-2. Local Bus Reference Operation Timing
031-00
(OUT Of MPC)
031-00
(INTO MPC)
MINT
10REO.
OROEO
290145-14
Figure 6-3. Local Bus Register and DMA Operation Timing
6-173
inter
82389
Table 6·3. Interconnect Bus A.C. Specifications (Vee
Symbol
Parameter
Min
=
5V ± 10%, T A
Max
=
Units
t31
lAST Active Time
85
ns
t32
Command Active Time
250
ns
t33
Command Inactive to. lAST Active
25
ns
t33A
lAST Inactive to Command Active
120
ns
t34
Address Setup to lAST Inactive
40
ns
t35
Address Hold from lAST Inactive
20
ns
t36
Write Data Hold from Command
Inactive
120
ns
t37
Write Data Hold from Command
Inactive
5
ns
t38
Read Data Enable from Command
Active
0
ns
t39
Read Data Valid from Command
Active
t40
Read Data Hold from Command
Inactive
t41
Read Data Disable from Command
Inactive (Note 2)
30
ns
t42
EINT, IREO Inactive from Command
Active (Note 1)
100
ns
120
0
O°C to
ns
+ 70°C)
Test
Conditions
CL = 150 pF
ns
CL = 150 pF
NOTES:
1. EINT inactive only on write to error register. IREQ inactive only on write to arbitration register.
2. Disable condition occurs when the output current becomes tess than the input leakage specification.
lAST
IRD,IWR
IAD7-IADO
(INTO MPG)
IAD7-IADO
(OUT OF MPG)
EINT
290145-15
Figure 6·4. Interconnect Bus Timing
6-174
82389
Table 6-4. PSB Bus Interface A.C. Specifications (Vee
Symbol
tcp
Parameter
Min
Clock Period
= 5V ± 10%, T A = O·C to + 70·C)
Max
Units
99.9
ns
ns
tCL
BCLK Low Time
40
tCH
BCLK High Time
40
ns
tBCL
BBCLK Low Time
38
ns
tBCH
BBCLK High Time
38
tRB
BCLK Rise Time
tFB
BCLK Fall Time
tR
BBCLK Rise Time
tF
BBCLK Fall Time
tSK
BCLK to BBCLK Skew (Note 1)
tCD
Clock to Output Delay
BREQ, BUSERR, RSTNC (Note 2)
ARB5-ARBO (Notes 2, 3)
BAD31-BADO, BSC7-BSCO
BPAR3-BPARO, BSC9, BSC8
SCDIRO, SCDIR1
(H to L)
(L to H)
ADDIR
(L to H)
(H to L)
REFADR
SEL
tH
toN
toFF
ns
1
5
ns
1
2
ns
0.5
1
ns
0.5
1
ns
-0.5
4.0
ns
36
36
29
29
19
21
21
27
29
29
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
=
=
=
=
=
=
=
=
=
=
500pF
500pF
75 pF
50 pF
25pF
25 pF
50pF
50pF
75 pF
50pF
CL
CL
CL
CL
CL
CL
CL
CL
=
=
=
=
=
=
=
=
25 pF
25 pF
15 pF
15 pF
15pF
25 pF
25 pF
15 pF
Hold Time from Clock
BREQ,BUSERR,RSTNC
ARB5-ARBO (Note 3)
BAD31-BADO, BPAR3-BPARO
BSC9-BSCO
SCDIRO, SCDIR1
ADDIR
REFADR
SEL
6.5
6.5
5.0
4.0
4.0
5.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
Turn On Delay from Clock (Note 4)
BREQ,BUSERR, RSTNC
ARB5-ARBO (Note 1)
BAD31-BADO, BPAR3-BPARO
BSC9-BSCO
6.5
6.5
5.0
4.0
ns
ns
ns
ns
Turn Off Delay from Clock (Note 5)
BREQ,BUSERR,RSTNC
ARB5-ARBO (Note 3)
BAD31-BADO, BPAR3-BPARO
BSC9-BSCO
36
36
29
29
6-175
Test
Conditions
ns
ns
ns
ns
82389
Table 6-4. PSB Bus Interface A.C. Specifications (Vee = 5V ± 10%, TA = O·C to
Symbol
'tsu
tlH
Parameter
Min
Input Setup Time to Clock
. BREO, BUSERR, RSTNC
ARB5-ARBO (Note 3)
BAD31-BADO, BPAR3-BPARO
BSC9-BSCO
.
TIMEOUT, LACHn, RESET
COM,ERR
Input Hold Time from Clock
BREO,BUSERR,RSTNC
ARB5-ARBO (Note 3)
BAP31-BADO, BPAR3-BPARO
BSC9-BSCO
TIMEOUT, LACHn, RESET
COM,ERR
Max
Units
22
40
24
24
24.
40
ns
ns
ns
ns
ns
ns
0
0
ns
ns
ns
ns
ns
ns
3
2
2
3
+ 70·C) (Continued)
Test
Conditions
NOTES:
1. The clock timings are provided to reference the MPC speCification to.the PSB bus specifications. These specifications
assume a 74AS1804 or equivalent buffer.
2. The 500 pF load is a distributed load as defined in the PSB bus specification. The open drain signals are designed such
that the outpUt delay and bus loss meets the PSB specification requirement.
.
3. The ARB5-ARBO signal timings are with respect to the first and last clock of the arbitration period. Details can be found
in the PSB bus specification. Also, the arbitration logic has been designed to meet the loop delay specification accounting
for the full path of input to output plus bus loss.
.
4. Minimum turn on times are measured the same way as hold times. Specifically, the logic level driven by another device on
the previous clock cycle must not be disiurbed.
5. Maximum turn off times are measured to the condition where the output leakage current becomes less than the input
leakage specification.
6. All stated capacitances are based on design requirements. Production test limitations may require some parameters to be
tested under a different condition.
6-176
inter
82389
VALID
INPUTS
NOTHER SOURCE
______---.-.rr-_Isu~~ r----X"," ___J "'"_ _ _ __
290145-16
NOTE:
1. SAMPOINT point for BBCLK is 1.4V.
Figure 6-5. PSB Bus Interface Timing
7.0 REFERENCE DOCUMENTS
290145-17
Figure 6-6. A.C. Test Load
Part Number Title Description
176526
MPC User's Manual
146077
MULTIBUS® II Architecture Specifications
149299
Interconnect Interface Specifications
149300
MULTIBUS® II MPC External Product Specifications
149247
MULTIBUS® II Transport Protocol
Specifications
6-177
Floppy Disk Controllers
7
8272A
SINGLE/DOUBLE DENSITY FLOPPY DISK CONTROLLER
Compatible in Both Single and
• IBM
Double Density Recording Formats
Data Record Lengths:
• Programmable
128,256,512, or 1024 Bytes/Sector
Multi-Sector and Multi-Track Transfer
• Capability
•
•
•
•
•
Data Transfers in DMA or Non-DMA
Mode
Seek Operations on Up to Four
• Parallel
Drives
with all Intel and Most
• Compatible
Other Microprocessors
Drives Up to 4 Floppy or Mini-Floppy
Disks
8" , 5%" and 3%" Floppy Disk
• Controls
Drives
Single-Phase 8 MHz Clock
Single
+ 5V Power Supply (± 10%)
Plastic 40 Pin DIP or 40 Pin CERDIP
Packages
The 8272A is an LSI Floppy Disk Controller (FDG) Chip, which contains the circuitry and control functions for
interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either IBM 3740 single' density
format (FM), or IBM System 34 Double Density format (MFM) including double sided recording. The 8272A
provides control signals which simplify the design of an external phase locked loop and write precompensation
circuitry. The FDC simplifies and handles most of the burdens associated with implementing a Floppy Disk
Drive Interface. The 8272A is a pin-compatible upgrade to the 8272.
TERMINAL
COUNT
4--READY
WRITE PROTECTITWO SIDE
_ _ INDEX
FAUl.T/TRACK 0
DRIVE SELECT 0
DRIVE SELECT 1
MFM MODE
'RWISEEI<
HEAD LOAD
HEAD SELECT
LOW CURRENT/DIRECTION
FAULT RESET/STEP
210606-1
Figure 1. 8272A Internal Block Diagram
7-1
210606-2
Figure 2. Pin Configuration.
November 1986
Order Number: 210606-002
inter
8272A
Table 1. Pin Description
Pin
No.
Type
ConnectionTo
RESET
1
I
p.P
RESET: Places FDC in idle state. Resets output lines to FDD to "0"
(low). Does not clear the last specify command.
RD
2
1(1)
p.P
READ: Control signal for transfer of data from FDC to Data Bus, when
"0" (low).
WR
3
1(1 )
p.P
WRITE: Control signal for transfer of data to FDC via Data Bus, when
"0" (low).
CS
4
I
p.P
CHIP SELECT: IC selected when "0" (low) allowing RD and WR to be
enabled.
Ao
5
1(1 )
p.P
DATA/STATUS REGISTER SELECT: Selects Data Reg (Aa
Status Reg (Aa = 0) contents to be sent to Data Bus.
-p.P
DATA BUS: Bidirectional8-Bit Data Bus.
Symbol
DBa-DB?
6-13 1/0(1)
Name and Function
= 1) or
DRO
14
0
DMA
DATA DMA REQUEST: DMA Request is being made by FDC when
DRO "1".(3)
DACK
15
I
DMA
QMA ACKNOWLEDGE: DMA cycle is active when "0" (low) and
Controller is performing DMA transfer.
TC
16
I
DMA
TERMINAL COUNT: Indicates the termination of a DMA transfer when
"1" (high)(2).
IDX
17
I
FDD
INDEX: Indicates the beginning of a disk track.
p.P
INT
18
0
ClK
19
I
INTERRUPT: Interrupt Request Generated by FDC.
CLOCK: Single Phase 8 MHz (4 MHz for mini floppies) Squarewave
Clock.
GND
20
GROUND: D.C. Power Return.
Vee
40
D.C. POWER:
RWISEEK
39
0
FDD
READ WRITE/SEEK: When "1" (high) Seek mode selected and when
"0" (low) Read/Write mode selected.
lCT/DIR
38
0
FDD
LOW CURRENT/DIRECTION: lowers Write current on inner tracks in
Read/Write mode, determines direction head will step in Seek mode.
FR/STP
37
0
FDD
FAULT RESET/STEP: Resets fault FF in FDD in Read/Write mode,
provides step pulses to move head to another cylinder in Seek mode.
HDl
36
0
FDD
HEAD LOAD: Command which causes Read/Write head in FDD to
contact diskette.
RDY
35
I
FDD
READY: Indicates FDD is ready to send or receive data. Must be tied
high (gated by the index pulse) for mini floppies which do not normally
have a Ready line.
WP/TS
34
I
FDD
WRITE PROTECT/TWO-SIDE: Senses Write Protect status in Read/
Write mode, and Two Side Media in Seek mode.
FlT/TRKO
33
I
FDD
FAULT/TRACK 0: Senses FDD fault condition in Read/Write mode
and Track 0 condition in Seek mode.
31,32
0
FDD
PRECOMPENSATION (PRE-SHIFn: Write precompensation status
during MFM mode. Determines early, late, and normal times.
WR DATA
30
0
FDD
WRITE DATA: Serial clock and data bits to FDD.
DS1, DSo
28,29
0
FDD
DRIVE SELECT: Selects FDD unit.
PS1, PSa
+ 5V
7-2
8272A
Table 1. Pin Description (Continued)
Symbol
HOSEL
Pin
No.
Type
Connection To
27
0
FOO
Name and Function
HEAD SELECT: Head 1 selected when "1" (high) Head 0 selected
when "0" (low).
MFM
26
0
PLL
MFM MODE: MFM mode when "1," FM mode when "0".
WE
25
0
FDO
WRITE ENABLE: Enables write data into FDO.
VCO
24
0
PLL
VCO SYNC: Inhibits VCO in PLL when "0" (low), enables VCO when
"1. "
RD DATA
23
I
FDO
READ DATA: Read data from FDD, containing clock and data bits.
DW
22
I
PLL
DATA WINDOW: Generated by PLL, and used to sample data from
WRCLK
21
I
FDO.
= 500 kHz, MFM = 1
MHz, with a pulse width of 250 ns for both FM and MFM.
Must be enabled for all operations, both Read and Write.
WRITE CLOCK: Write data rate to FDD FM
NOTES:
1. Disabled when CS = 1.
2. TC must be activated to terminate the Execution Phase of any command.
3. ORQ is also an input for certain test modes. It should have a 5 kn pull-up resistor to prevent activation.
load a command into the FDC and all data transfers
occur under control of the 8272A and DMA controller.
I
CPU
~
There are 15 separate commands which the 8272A
will execute. Each of these commands require mUltiple 8-bit bytes to fully specify the operation which
the processor wishes the FDC to perform. The following commands are available.
SYSTEM BUS
L
r
"'"
7-
<>
ORO
~
DATA
WINDOW
RD DATA
-B-r
~
WR DATA
8237
OM>
CONTROLLER
~
8272A
FOC
A.
DRIVE
)
INTERFACE
INPUT CONTROL
~
-rc-
TERMINAL L - COUNT
Read Data
ReadlD
Read Deleted Data
Read a Track
Scan Equal
Scan High or Equal
Scan Low or Equal
Specify
1\
OUTPUT CONTROL
V
)
210606-3
For more information see the Intel Application Notes
AP-116 and AP-121.
Figure 3. 8272A System Block Diagram
DESCRIPTION
Hand-shaking signals are provided in the 8272A
which make OMA operation easy to incorporate with
the aid of an external DMA Controller chip, such as
the 8237 A. The FOC will operate in either DMA or
Non-DMA mode. In the Non-OMA mode, the FDC
generates interrupts to the processor for every
transfer of a data byte between the CPU and the
8272A.ln the OMA mode, the processor need only
Write Data
Format a Track
Write Deleted Data
Seek
Recalibrate (Restore to
Track 0)
Sense Interrupt Status
Sense Drive Status
FEATURES
Address mark detection circuitry is internal to the
FOC which simplifies the phase locked loop and
read electronics. The track stepping rate, head load
time, and head unload time may be programmed by
the user. The 8272A offers many additional features
such as multiple sector transfers in both read and
write modes with a single command, and full IBM
compatibility in both single (FM) and double density
(MFM) modes.
7-3
8272A
8272A ENHANCEMENTS
8272A REGISTERS-CPU INTERFACE
On the 8272A, after detecting the Index Pulse, the
VCO Sync output stays low for a shorter period of
time. See Figure 4a.
The 8272A contains two registers which may be accessed by the main system processor; a Status Register and a Data Register. The 8-bit· Main Status
Register contains the status information of the FDC,
and may be accessed at any time. The a-bit Data
Register (actually consists of several registers in a
stack with only one register presented to the data
bus at a time), stores data, commands, parameters,
and FDD status information. Data bytes are read out
of, or written into, the Data Register in order to program or obtain the results after execution of a command. The Status Register may only be read and is
used to facilitate the transfer of data between the.
processor and 8272A.
On the 8272 there can be a problem reading data
when Gap 4A is 00 and there is no lAM. This occurs
on some older floppy formats. The 8272A cures this
problem by adjusting the VCO Sync timing so that it
is not low during the data field .. See Figure 4b.
I I
Troell
.oOP 4A IAM
Index Pul.. ----r-----"
8272 veo Sync--'
Oap'
lID
I oap21
Da"
r----
8272A yeo Sy.;c--'
210606-4
'560 /,9 in FM mode; 527 /,9 in MFM mode
The relationship between the Status/Down registers
and the signals RD, WR, and Ao is shown in Table 2.
a. Margin on the Index Pulse
ThIck
Index Pul..
Oop 4A (001
I ID I
Oap2
Table 2. Ao, RD, WR Decoding for the Selection
of Status/Data Register Functions.
IDa ..
----r---1
1272
veo Sync
8272A
veo Sync
-------------,~r------
210606-5
Ao
RD
WR
Function
0
0
1
Read Main Status Register
0
lIIegal(l)
b. Ability to Read Data
When Gap 4A Contains 00
0
1
0
0
0
lIIegal(l)
Figure 4. 8272A Enhancements over the 8272
1
0
0
lIIegal(l)
1
0
1
Read from Data Register
1
1
0
Write into Data Register
NOTE:
1. Design must guarantee that the 8272A is not subjected
to illegal inputs.·
The Main Status Register bits are defined in Table 3.
7-4
inter
8272A
Table 3. Main Status Register Bit Description
Bit Number
Name
Symbol
Description
00
FOOO Busy
OoB
FOO number 0 is in the Seek mode.
01
FOO 1 Busy
01 B
FOO number 1 is in the Seek mode.
02
F002 Busy
02B
FOO number 2 is in the Seek mode.
03
F003 Busy
03B
FOO number 3 is in the Seek mode.
04
FOG Busy
GB
A read or write command is in process.
05
Non-OMA Mode
06
07
NOM
The FOG is in the non-OMA mode. This bit is set only
during the execution phase in non-OMA mode.
Transition to "0" state indicates execution phase has
ended.
Oata Input/Output
010
Indicates direction of data transfer between FOG and
Oata Register. If 010 = "1" then transfer is from Data
Register to the Processor. If 010 = "0", then transfer
is from the Processor to Data Register.
Request for Master
ROM
Indicates Data Register is ready to send or receive
data to or from the Processor. Both bits 010 and ROM
should be used to perform the handshaking functions
of "ready" and "direction" to the processor.
The 010 and ROM bits in the Status Register indicate when Oata is ready and in which direction data will be
transferred on the Data Bus.
NOTE:
There is a 12 {Jos or 24{JosHQM flag delay when using an 8 or 4 MHz clock respectively.
NOTES:
A-Data
B-Data
C-Data
D-Data
register
register
register
register
ready to be written into by processor
not ready to be written into by processor
ready for next data byte to be read by the processor
not ready for next data byte to be read by processor
Figure 5. Status Register Timing
7-5
inter
8272A
The 8272A always operates in a multi-sector transfer mode. It continues to transfer data until the TC
input is active. In Non-DMA Mode, the system must
supply the TC input.
The 8272A is capable of executing 15 different commands. Each "command is initiated by a multi-byte
transfer from the processor, and the result after execution of the command may also be a multi-byte
transfer back to the processor. Because of this multi-byte interchange of information between the
8272A and the processor, it is convenient to consider each command as consisting of. three phases:
Command Phase: The FDC receives all information
required to perform a particular
operation from the processor.
Execution Phase: The FDC performs the operation
it was instructed to do.
Result Phase:
After completion of the operation, status and other housekeeping .information are made
available to the processor.
If the 8272A is in the DMA Mode, no Interrupts are
generated during the Execution Phase. The 8272A
generates DRO's (DMA Requests) when each byte
of data is available. The DMA Controller responds to
this request with both a DACK = o (DMA Acknowledge) and a RD = 0 (Read signal). When the DMA
Acknowledge signal goes low (DACK = 0) then the
DMA Request is reset (DRO = 0). If a Write Command has been proll@mmed then a WR signal will
. appear instead of RD. After the Execution Phase
has been completed (Terminal Count has occurred)
then an Interrupt will occur (INT = 1). Thissignifies
the beginning of the Result Phase. When the first
byte of data is read during the Result Phase, the
Interrupt is automatically reset (INT = 0).
During Command or Result Phases the Main Status
Register (described in Table 3) must be read by the
processor before each byte of information is written
into or read. from the Data Register. Bits D6 and D7
in the Main Status. Register must be in a 0 and 1
state,respectively, before each byte of the command word may be written into the 8272A. Many of
the commands require multiple bytes, and as a re~
suit the Main Status Register must be read prior to
each byte transfer to the 8272A. On the other hand,
during the Result Phase, D6 and D7 in. the Main
Status Register must both be 1's (D6 = 1 and D7 =
1) before reading each byte from the Data Register.
It is important to note that during the Result Phase
all bytes shown in the Command Table must be
read. The Read Data Command, for example has
seven bytes of data in the Result Phase. All seven
bytes must be read in order to successfully complete
the Read Data Command. The 8272A will not accept
a new command until all seven bytes have been
read. Other commands may require fewer bytes to
be read during the Result Phase.
NOTE:
This reading of the Main Status Register before
each byte transfer to the 8272A is required in only
the Command and Result Phases, and NOT during .
the Execution Phase.
During the Execution Phase, the Main Status Register need not be read. If the 8272A is in the non-DMA
Mode, then the receipt of each data byte (if 8272A is
reading data from FDD) is indicated by an interrupt
signal on pin 18 (INT = 1). The generation of a
Read signal (RD = 0) will reset the interrupt as well
as output the Data onto the Data Bus. For example,
if the processor cannot handle Interrupts fast
enough (every 13 JLs for MFM mode) then it may poll
the Main Status Register and then bit D7 (ROM)
functions just like the Interrupt signal. If a Write
Command is in process, then the WR signal performs the reset to the Interrupt signal.
The 8272A contains five Status Registers. The Main
Status Register mentioned above may be read by
the processor at any time. The other four Status
Registers (STO, ST1, ST2, and ST3) are only available during the Result Phase, and may be read only
after successfully completing a command. The particular command which has been executed determines how many of the .Status Registers' will be
read.
The bytes of data which are sent to the 8272A to
form the Command Phase, and are read out of the
8272A in the Result Phase, must occur in the order
shown in the Table 4. That is, the Command Code
must be sent first and the other bytes sent in the
prescribed sequence. No foreshortening of the
Command or Result Phases are allowed. After the
last byte of data in the Command Phase is sent to
the 8272A, the Execution Phase automatically
starts. In a similar fashion, when the last byte of
7-6
infef
8272A
Table 4. 8272A Command Set
Phase
Data Bus
R/W
Remarks
07
06
05
04
03
02
01
Do
MT
0
MFM
0
SK
0
0
0
0
0
1
HDS
1
DS1
0
DSO
READ DATA
Command
W
W
W
W
W
W
W
W
W
-------
-----
-----
Execution
Result
-------
R
R
R
R
R
R
R
-----------
C
H
R
N
EOT
GPL
DTL
---
---
---
Sector ID Information
Prior to Command
Execution
---
---
STO
ST 1
ST2
C
H
R
N
---
Command Codes
Data Transfer
Between the FDD
and Main·System
Status Information
After Command
Execution
---
-----------
Sector ID Information
After Command
Execution
---
READ DELETED DATA
Command
W
W
W
W
W
W
W
W
W
MT
0
MFM
0
SK
0
-------
-----
-----
1
0
0
0
C
H
R
N
EOT
GPL
DTL
Execution
Result
R
R
R
R
R
R
R
---------------
STO
ST 1
ST2
C
H
R
N
7-7
1
HDS
0
DS1
-------
0
DSO
Command Codes
Sector ID Information
Prior to Command
Execution
-----
-----
-----
-----------
Data Transfer
Between the FDD
and Main·System
Status Information
After Command
Execution
Sector ID Information
After Command
Execution
inter
8272A
Table 4. 8272A Command Set (Continued)
Phase
Data Bus
R/W
Remarks
07
06
Os
04
03
02
0,
Do
MT
MFM
0
0
0
0
0
0
0
1
HOS
0
0
OS1
1
OSO
. WRITE DATA
Command
W
W
W
W
W
W
W
W
W
-----
-------
Result
---
R
R
R
R
R
R
R
---
Data Transfer
Between the MainSystem and FOO
---
STO
ST 1
ST2
C
H
R
-----------
Sector 10 Information
Prior to Command
Execution
---------
N
EOT
GPL
OTL
-----
Execution
-------
C
H
R
Status Information
After Command
Execution
---
-----------
N
Command Codes
Sector 10 Information
After Command
Execution
WRITE DELETED DATA
Command
W
W
W
W
W
W
W
W
W
Execution
Result
R
R
R
R
R
R
R
MT
MFM
0
0
0
0
---------------
-------
---
-------
0
0
C
H
R
N
EOT
' GPL
OTL
STO
ST1
ST2
C
H
R
N
7-8
1
0
0
0
HOS
OS1
---------------
1
OSO
Command Codes
Sector 10 Information
Prior to Command
Execution
Data Transfer
Between the FOO
and Main-System
-------
Status Information
After Command
Execution
-------
Sector 10 Information
After Command
Execution
---
inter
8272A
Table 4. 8272A Command Set (Continued)
Phase
Data Bus
R/W
Remarks
07
06
Os
04
03
02
01
Do
0
0
MFM
SK
0
0
0
0
0
0
0
HDS
1
DS1
DSO
READ A TRACK
Command
W
W
W
W
W
W
W
W
W
-------
C
H
R
---
N
-----
EOT
GPL
DTL
---
R
R
R
R
R
R
R
-------
-----
---
-----
-----
---
Data Transfer
Between the FDD
and Main-System.
FOC Reads all of
Cylinders Contents
from Index Hole to
EOT
-----------
STO
ST 1
ST2
C
H
R
---
Status Information
After Command
Execution
Sector ID Information
After Command
Execution
---
N
---
Command Codes
Sector ID Information
Prior to Command
Execution
---
Execution
Result
0
REAOID
Command
W
W
0
0
MFM
0
0
0
0
0
1
0
0
HDS
1
DS1
Execution
Result
0
Commands
DSO
The First Correct ID
Information on the
Cylinder is Stored in
Data Register
R
R
R
R
R
R
R
---------------
.STO
ST 1
ST2
C
H
-----
R
N
---
7-9
---
-------
Status Information
After Command
Execution
Sector ID Information
During Execution
Phase
inter
8272A
Table 4. 8272A Command Set (Continued)
Phase
Data Bus
R/W
Remarks
07
Os
05
04
03
02
01
Do
0
0
MFM
0
0
0
0
1
1
HDS
0
0
DS1
1
DSO
FORMAT A TRACK
Command
W
W
W
W
W
W
Execution
0
---------
N
SC
GPL
D
---------
Command Codes
Bytes/Sector
Sectors/Cylinder
Gap3
Filler Byte
FDC Formats an
Entire Cylinder
Result
R
R
R
R
R
R
R
-----
-----------
STO
ST 1
ST2
C
H
R
N
7·10
---------------
Status Information
After Command
Execution
In This Case, the ID
Information has no
Meaning
inter
8272A
Table 4. 8272A Command Set (Continued)
Phase
Oata Bus
R/W
Remarks
07
Os
05
04
03
02
01
00
MT
0
MFM
0
SK
0
1
0
0
0
0
HDS
0
DS1
1
DSO
SCAN EQUAL
Command
W
W
W
W
W
W
W
W
W
---
-----------
C
H
R
-----
---
N
EOT
GPL
STP
---
-----
R
R
R
R
R
R
R
---
---
-----
---
Data Compared
Between the FDD
and Main·System
---
STO
ST1
ST2
C
H
R
---
---
Sector 10 Information
Prior to Command
Execution
---
Execution
Result
Command Codes
Status Information
After Command
Execution
---
---------
N
Sector 10 Information
After Command
Execution
SCAN LOW OR EQUAL
Command
W
W
W
W
W
W
W
W
W
Execution
Result
R
R
R
R
R
R
R
MT
0
MFM
0
SK
0
-----------
-----
-----
-------
-----
1
0
1
0
C
H
R
N
EOT
GPL
STP
STO
ST1
ST2
C
H
R
N
7-11
0
HDS
0
DS1
---
-------
1
DSO
Command Codes
Sector 10 Information
Prior to Command
Execution
-----
---
-------
Data Compared
Between the FDD
and Main·System
Status Information
After Command
Execution
---
-------
Sector 10 Information
After Command
Execution
8272A·
Table 4. 8272A Command Set (Continued)
Phase
I
Data Bus
R/W
D6
Ds
D4
D3
D2
D1
Do
MFM
0
SK
0
1
0
1
0
1
HDS
0
DS1
1
DSO
D7
Remarks
SCAN HIGH OR 'EQUAL
Command
W
W
W
W
W
W
W
MT
0
---------
R
N
EaT
GPL
STP
---
---
W
Execution
Result
H
---
w
-------
R
R
R.
R
R
R
R
-----
---
STO
ST1
ST2
C
H
R
N
---
-----
---
Sector 10 Information
Prior to Command
Execution
---------
C
Command Codes
Data Compared
Between the FDD
and Main-System
---
Status Information
After Command
Execution
-----
Sector 10 Information
After Command
Execution
-------
---
RECALIBRATE
Command
W
W
0
0
0
0
0
0
0
0
0
0
1
0
1
DS1
1
DSO
Execution
Command Codes
Head Retracted to
Track 0
SENSE INTERRUPT STATUS
Command
Result
W
R
R
0
0
0
-----
0
1
STO
PCN
7-12
0
0
---
---
0
Command Codes
Status Information at
the End of Each Seek
Operation About the
FDC
intJ
8272A
Table 4. 8272A Command Set (Continued)
Phase
Data Bus
R/W
D7
06
0
0
SRT
HLT
Os
D4
0
0
Remarks
D3
02
01
0
0
1
HUT
Do
SPECIFY
Command
W
W
W
-
<---
--->
>
1
Command Codes
-
NO
SENSE DRIVE STATUS
Command
Result
W
W
R
0
0
W
W
W
0
0
0
0
0
0
0
0
0
0
1
HDS
0
DS1
0
Command Codes
DSO
ST3
Status Information
aboutFDD
SEEK
Command
0
0
0
0
0
0
1
0
1
HDS
1
DS1
1
DSO
Command Codes
NCN
Execution
Head is Positioned
Over Proper Cylinder
on Diskette
INVALID
Command
W
Invalid Codes
Result
R
STO
7-13
Invalid Command
Codes (NoOp-FDC
Goes Into Standby
State)
STO = 80
(16)
intJ
8272A
Table 5. Command Mnemonics
Symbol
Name
Description
Ao
Address Line 0
Ao controls selection' of Main Status Register (Ao = 0) Or Data Register (Ao = 1).
C
Cylinder Number
C stands for the current selected Cylinder track number 0 through 76 of
the medium.
0
Data
o stands for the data pattern which is going to be written into a Sector.
07- 0 0
Data Bus
8-bit Data bus where 07 is the most significant bit, and Do is the least
significant bit.
DSO,DS1
Drive Select
OS stands for a selected drive number 0 or 1.
DTL
Data Length
When N is defined as 00, DTL stands for the data length which users are
going to read out or write into the Sector.
EDT
End of Track
EDT stands for the final Sector number of a Cylinder.
GPL
Gap Length
GPL stands for the length of Gap 3 (spacing between Sectors excluding
VCO Sync Field).
H
Head Address
H stands for head number 0 or 1, as specified in 10 field.
HDS
Head Select
HDS stands for a selected head number 0 .or 1 (H = HDS in all command
words).
HLT
Head Load Time
HLT stands for the head load time in the FDD (2 to 254 ms in 2 ms
increments).
HUT
Head Unload Time
HUT stands for the head unload time after a read or write operation has
occurred (16 to 240 ms in 16 ms increments).
MFM
FM or MFM Mode
If MF is low, FM mode is selected and if it is high, MFM mode is selected.
MT
Multi-Track
If MT is high, a multi-track operation is to be peformed (a cylinder under
both HDO and HD1 will be read or written).
N
Number
N stands for the number of data bytes written in a Sector.
NCN
New Cylinder
Number
NCN stands for a new Cylinder number, which is going to be reached as a
result of the Seek operation. Desired position of Head.
NO
Non-DMA Mode
NO stands for operation in the Non-DMA Mode.
PCN
Present Cylinder
Number
PCN stands for the Cylinder number at the completion of SENSE
INTERRUPT STATUS Command. Position of Head at present time.
R
Record
R stands for the Sector numbei', which will be read or written.
R/W
Read/Write
R/W stands for either Read (R) or Write (W) signal.
SC
Sector
SC indicates the number of Sectors per Cylinder.
SK
Skip
SK stands for Skip Deleted Data Address Mark.
SRT
Step Rate Time
~RT
stands for the Stepping Rate for the FDD (1 to 16 ms in 1 ms
increments). The same Stepping Rate applies to all drives (F = 1 ms,
E = 2 ms, etc.).
7-14
8272A
Table 5. Command Mnemonics (Continued)
Symbol
Name
STO
ST 1
ST2
ST3
Status 0 '
Status 1
Status 2
Status 3
Description
ST 0-3 stand for one of four registers which store the status information after
a command has been executed. This information is available during the result
phase after command execution. These registers should not be confused with
the main status register (selected by Ao = 0). ST 0-3 may be read only after
a command has been executed and contain information relevant to that
particular command.
During a Scan operation, if STP = 1, the data in contiguous sectors is
compared byte by byte with data sent from the processor (or DMA), and if
STP = 2, then alternate sectors are read and compared.
STP
written into the Data Register. The DIO (DB6) and
ROM (BD7) bits in the Main Status Register must be
in the "0" and "1" states respectively, before each
byte of the command may be written into the 8272A.
The beginning of the execution phase for any of
these commands will cause DIO and ROM to switch
to "1" and "0" states respectively.
data is read out in the Result Phase, the command is
automatically ended and the 8272A is ready for a
new command. A command may be aborted by simply sending a Terminal Count signal to pin 16
(TC = 1). This is a convenient means of ensuring that
the processor may always get the 8272A's attention
even if the disk system hangs up in an abnormal
manner.
READ DATA
POLLING FEATURE OF THE 8272A
A set of nine (9) byte words are required to place the
FDC into the Read Data Mode. After the Read Data
command has been issued the FDC loads the head
(if it is in the unloaded state), waits the specified
head settling time (defined in the Specify Command), and begins reading ID Address Marks and 10
fields. When the current sector number ("R") stored
in the ID Register (IDR) compares with the sector
number read off the diskette, then the FDC outputs
data (from the data field) byte-by-byte to the main
system via the data bus.
After power-up RESET, the Drive Select Lines DSO
and DS1 will automatically go into a polling mode. In
between commands (and between step pulses in
the SEEK command) the 8272A polls all four FDDs
looking for a change in the Ready line from any of
the drives. If the Ready line changes state (usually
due to a door opening or closing) then the 8272A will
generate an interrupt. When Status Register 0 (STO)
is read (after Sense Interrupt Status is issued), Not
Ready (NR) will be indicated. The polling of the
Ready line by the 8272A occurs continuously between instructions, thus notifying the processor
which drives are on or off line. Approximate scan
timing is shown in Table 6.
Table 6. Scan Timing
DS1
DSO
Approximate Scan Timing
0
0
220 p,s
0
1
220 p,s
1
0
220 p,s
1
1
440 p,s
After completion of the read operation from the current sector, the Sector Number is incremented by
one, and the data from the next sector is read and
output on the data bus. This continuous function is
called a "Multi-Sector Read Operation." The Read
Data Command must be terminated by the receipt of
a Terminal Count signal. Upon receipt of this signal,
the FDC stops outputting data to the processor, but
will continue to read data from the current sector,
check CRC (Cyclic Redundancy Count) bytes, and
then at the end of the sector terminate the Read
Data Command.
The amount of data which can be handled with a
single command to the FDC depends upon MT (multi-track), MFM (MFM/FM), and N (Number of Bytes/
Sector). Table 7 on the next page shows the Transfer Capacity.
COMMAND DESCRIPTIONS
During the Command Phase, the Main Status Register must be polled by the CPU before each byte is
7-15
8272A
Table 7. Transfer Capacity
Maximum Transfer Capacity
(Bytes/Sector)(Number of Sectors)
Final Sector Read
from Diskette
=
=
=
=
=
=
=
=
=
=
=
=
3,328
6,656
26 afSide 0
or 26 at Side 1
6,656
13,312
26 at Side 1
3,840
7,680
15 at Side 0
or 15 at Side 1
7,680
15,360
15 at Side 1
4,096
8,192
8 at Side 0
or 8 at Side 1
8,192
16,384
8 at Side 1
Multi-Track
MT
MFM/FM
MFM
Bytes/Sector
N
0
0
0
1
00
01
(128) (26)
(256) (26)
1
1
0
1
00
01
(128)(52)
(256) (52)
0
0
0
1
01
02
(256) (15)
(512) (15)
1
1
0
1
01
02
(256) (30)
(512) (30)
0
0
0
1
02
03
(512) (8)
(1024) (8)
1
1
0
1
02
03
(512) (16)
(1024) (16)
The "multi-track" function (MT) allows the FDC to
read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at
Sector 1, Side 0 and completing at Sector L, Side 1
(Sector L = last sector on the side).
After reading the ID and Data Fields in each sector,
the FDC checks the CRC bytes. If a read error is
detected (incorrect CRC in ID field), the FDC sets
the DE (Data Error) flag in Status Register 1 to a 1
(high), and if a CRC error occurs in the Data Field
the FDC also sets the DD (Data Error in Data Field)
flag in Status Register 2 to a 1 (high), .and terminates
the Read Data Command. (Status Register 0 also
has bits 7 and 6 set to 0 and 1 respectively.)
NOTE:
This function pertains to only one cylinder (the
same track) on each side of the diskette.
If the FDC reads a Deleted Data Address Mark off
the diskette, and the SK bit (bit D5 in the first Command Word) is not set (SK = 0), then the FDC sets
the CM (Control Mark) flag in Status Register 2 to a
1 (high), and terminates the Read Data Command,
after reading all the data in the Sector. If SK = ·1,
the FDC skips the sector with the Deleted Data Address Mark and reads the next sector.
When N = 0, then DTL defines the data length
which the FDC must treat as a sector. If DTL is
smaller than the actual data length in a Sector, the
data beyond DTL in the Sector is not sent to the
Data Bus. The FDC reads (internally) the complete
Sector performing the CRC check, and depending
upon the manner of command termination, may perform a Multi-Sector Read Operation. When N is nonzero, then DTL has no meaning and should be set to
OFFH.
During disk data transfers between the FDC and the
processor, via the data bus, the FDC must be serviced by the processor every 27 fl-s in the FM Mode,
and every 13 fl-s in the MFM Mode, or the FDC sets
the OR (Over Run) flag in Status Register 1 to a 1
(high), and terminates the Read Data Command.
At the completion of the Read Data Command, the
head is not unloaded until after Head Unload Time
Interval (specified in the Specify Command) has
elapsed. If the processor issues another command
before the head unloads then the head settling time
may be saved between subsequent reads. This time
out is particularly valuable when a diskette is copied
from one drive to another.
If the processor terminates a read (or write) operation in theFDC, then the ID Information in the Result
Phase is dependenfupon the state of the MT bit and
EOT byte. Table 5 shows the values for C, H, R, and
N, when the processor terminates the Command.
If the FDC detects the Index Hole twice without finding the right sector, (indicated in "R"), then the FDC
sets the ND (No Data) flag in Status Register 1 to a
1 (high), and terminates the Read Data Command.
(Status Register 0 also has bits 7 and 6 set to 0 and
1 respectively.)
7-16
8272A
Table 8. ID Information When Processor Terminates Command
MT
0
1
EOT
ID Information at Result Phase
Final Sector Transferred to
Processor
C
H
R
N
NC
NC
R+1
NC
C+1
NC
R
= 01
NC
NC
NC
R+1
NC
C+1
NC
R
= 01
NC
NC
1A
OF
08
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
1A
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
1A
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
1A
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
1A
OF
08
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
NC
NC
R+1
1A
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
NC
LSB
R
= 01
NC
1A
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
NC
NC
R+1
NC
1A
OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
C+1
LSB
R
= 01
NC
NOTES:
1. NC (No Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.
ance of a Terminal Count signal. If a Terminal Count
signal is sent to the FOC it continues writing into the
current sector to complete the data field. If the Terminal Count signal is received while a data field is
being written then the remainder of the data field is
filled with 00 (zeros).
WRITE DATA
A set of nine (9) bytes are required to set the FOC
into the Write Oata mode. After the Write Oata command has been issued the FOC loads the head (if it
is in the unloaded state), waits the specified head
settling time (defined in the Specify Command), and
begins reading 10 Fields. When the current sector
number ("R"), stored in the 10 Register (lOR) compares with the sector number read off the diskette,
then the FOC takes data from the processor byteby-byte via the data bus, and outputs it to the FOO.
The FOC reads the 10 field of each sector and
checks the CRC bytes. If the FOC detects a read
error (incorrect CRG) in one of the 10 Fields, it sets
the OE (Oata Error) flag of Status Register 1 to a 1
(high), and terminates the Write Oata Command.
(Status Register 0 also has bits 7 and 6 set to 0 and
1 respectively.)
After writing data into the current sector, the Sector
Number stored in "R" is incremented by one, and
the next data field is written into. The FOC continues
this "Multi-Sector Write Operation" until the issu-
The Write Command operates in much the same
manner as the Read Command. The following items
7-17
8272A
a 1 (high) if there is no comparison. Multi-track or
skip operations are not allowed with this command.
are the same; refer to the Read Data Command for
details:
•
•
•
•
•
Transfer Capacity
EN (End of Cylinder) Flag
NO (No Data) Flag
Head Unload Time Interval
10 Information when the processor terminates
command (see Table 2)
• Definition of DTL when N = 0 and when N -=1= 0
This command terminates when EOT number of
sectors have been read. If the FDC does not find an
10 Address Mark on the diskette after it encounters
the INDEX HOLE for the second time, then it sets
the MA (missing address mark) flag in Status Register 1 to a 1 (high), and terminates the command.
(Status Register 0 has bits 7 and 6 set to 0 and 1
respectively.)
In the Write Data mode, data transfers between the
processor and FDC must occur every 31 p.,s in the
FM mode, and every 15 p.,s in the MFM mode. If the
time interval between data transfers is longer than
this then the FDC sets the OR (Over Run) flag in
Status Register 1 to a 1 (high), and terminates the
Write Data Command.
READID
The READ 10 Command is. used to give the present
pOSition of the recording head. The FDC stores the
values from the first 10 Field it is able to read. If no
proper 10 Address Mark is found on the diskette,
before the INDEX HOLE is encountered for the second time then the MA (Missing Address Mark) flag in
Status Register 1 is set to a 1 (high), and if no data is
found then the NO (No Data) flag is also set in
Status Register 1 to a 1 (high) and the command is
terminated.
For mini-floppies, multiple track writes are usually
not permitted. This is because of the turn-off time of
the erase head coils-the head switches tracks before the erase head turns off. Therefore the system
should typically wait 1.3 ms before attempting to
step or change sides.
FORMAT A TRACK
WRITE DELETED DATA
The Format Command allows an entire track to be
formatted. After the INDEX HOLE is detected, Data
is written on the Diskette: Gaps, Address Marks, 10
Fields and Data Fields, all per the IBM System 34
(Double Density) or System 3740 (Single Density)
Format are recorded. The particular format which
will be written is controlled by the values programmed into N (number of bytes/sector), SC (sectors/cylinder), GPL (Gap Length), and 0 (Data Pattern) which are supplied by the processor during the
Command Phase. The Data Field is filled with the
Byte of data stored in D. The 10 Field for each sector
is supplied by the processor; that is, four data requests per sector are made by the FDC for C (Cylinder Number), H(Head Number), R(Sector Number)
and N(Number of Bytes/Sector). This allows the
diskette to be formatted with nonsequential sector
numbers, if desired.
This command is the same as the Write Data Command except a Deleted Data Address Mark is written
at the beginning of the Data Field instead of the normal Data Address Mark.
READ DELETED DATA
This command is the same as the Read Data Command except that when the FDC detects a Data Address Mark at the beginning of a Data Field (and
SK = 0 (low», it will read all the data in the sector
and set the CM flag in Status Register 2 to a 1
(high), and then terminate the command. If SK = 1,
then the FDC skips the sector with the Data Address
Mark and reads the next sector.
READ A TRACK
After formatting each sector, the processor must
send new values for C, H, R, and N to the 8272A for
each sector on the track. The contents of the R Register is incremented by one after each sector is formatted, thus, the R register contains a value of R +
1 when it is read during the Result Phase. This incrementing and formatting continues for the whole
track until the FDC encounters the. INDEX HOLE for
the second time, whereupon it terminates the command.
This command is similar to READ DATA Command
except that the entire data field is read continuously
from each of the sectors of a track. Immediately after encountering the INDEX HOLE, the FDC starts
reading all data fields on the track as continuous
blocks of data. If the FDC finds an error in the 10 or
DATA CRC check bytes, it continues to read data
from the track. The FDC compares the 10 information read from each sector with the value stored in
the lOR, and sets the NO flag of Status Register 1 to
7-18
inter
8272A
mand execution phase causes command termination.
If a FAULT signal is received from the FDD at the
end of a write operation, then the FDC sets the EC
flag of Status Register 0 to a 1 (high), and terminates the command after setting bits 7 and 6 of
Status Register 0 to 0 and 1 respectively. Also the
loss of a READY signal at the beginning of a com-
Table 9 shows the relationship between N, SC, and
GPL for various sector sizes:
Table 9 Sector Size Relationships
N
Bytes/
SC GpL(1) GpL(2) Sector
N
128
256
512
1024
2048
4096
00
01
02
03
04
05
1A
OF
08
04
02
01
07
OE
1B
47
C8
C8
1B
2A
3A
8A
FF
FF
128
128
256
512
1024
2048
00
00
01
02
03
04
3%" Mini Floppy
5%" Floppy
Bytes/
SC GpL(1) GpL(2) Sector N SC GPL(1) GpL(2)
128 0 OF
07
1B
12
07
09
10
10
19
08
18
30
256
1 09
OF
2A
46
87
512
2 05
1B
3A
04
02
C8
FF
01
C8
FF
-
256
512
1024
2048
4096
8192
01
02
03
04
05
06
1A
OF
08
04
02
01
OE
1B
35
99
C8
C8
36
54
74
FF
FF
FF
256
256
512
1024
2048
4096
01
01
02
03
04
05
12
10
08
04
02
01
Bytes/
Format
Sector
FM
Mode
MPM
Mode
8" Floppy
-
OA
20
2A
80
C8
C8
OC
32
50
FO
FF
FF
256
512
1024
-
-
- -
-
-
1
2
3
-
CE
1B
35
-
36
54
74
-
OF
09
05
- -
-
NOTES:
1. Suggested values of GPL in Read or Write Commands to avoid splice point between data field and ID field of contiguous
sections.
2. Suggested values of GPL in format command.
sector of data is compared, if the conditions are not
met, the sector number is incremented (R + STP
~ R), and the scan operation is continued. The
scan operation continues until one of the following
conditions occur; the conditions for scan are met
(equal, low, or high), the last sector on the track is
reached (EOT), or the terminal count signal is received.
SCAN COMMANDS
The SCAN Commands allow data which is being
read from the diskette to be compared against data
which is being supplied from the main system (Processor in NON-DMA mode, and DMA Controller in
DMA mode). The FDC compares the data on a byteby-byte basis, and looks for a sector of data which
meets the conditions of DFDD = Dprocessor, DFDD ,s;
Dprocessor, or DFDD :20 Dprocessor. Ones complement arithmetic is used for comparison (FF = largest number, 00 = smallest number). After a whole
If the conditions for scan are met then the FDC sets
the SH (Scan Hit) flag of Status Register 2 to a 1
(high), and terminates the Scan Command. If the
Table 10. Scan Status Codes
Status Register 2
Command
Comments
Bit2 = SN
Bit3 = SH
Scan Equal
0
1
1
0
DFDD = Dprocessor
DFDD "t= DProcessor
Scan Low or Equal
0
0
1
1
0
0
DFDD = DProcessor
DFDD < Dprocessor
DFDD :I> Dprocessor
Scan High or Equal
0
0
1
1
0
0
DFDD == DProcessor
DFDD > DProcessor
DFDD 1: Dprocessor
7-19
inter
8272A
conditions for scan are not met between the starting
sector (as specified by R) and the last sector on the
cylinder (EOT), then the FDC sets the SN (Scan Not
Satisfied) flag of Status Register 2 to a 1 (high), and
terminates the Scan Command. The receipt of a
TERMINAL COUNT signal from the Processor or
DMA Controller during the scan operation will cause
the FDC to complete the comparison of the particular byte which is in process, and then to terminate
the command. Table 10 shows the status of bits SH
and SN under various conditions of SCAN.
If the FDC encounters a Deleted Data Address Mark
on one of the sectors (and SK = 0), then it regards
the sector as the last sector on the cylinder, sets CM
(Control Mark) flag of Status Register 2 to a 1 (high)
and terminates the command. If SK = 1, the FDC
skips the sector with the Deleted Address Mark, and
reads the next sector. In the second case (SK = 1),
the FDC sets the CM (Control Mark) flag of Status
Register 2 to a 1 (high) in order to show that a Deleted Sector had been encountered.
When either the STP (contiguous sectors STP = 01,
or alternate sectors STP = 02 sectors are read) or
the MT(Multi-Track) are programmed, it is necessary to remember that the last sector on the track
must be read. For example, if STP = 02, MT = 0,
the sectors are numbered sequentially 1 through 26,
and we start the Scan Command at sector 21; the
following will happen. Sectors 21, 23, and 25 will be
read, then the next sector (26) will be skipped and
the Index Hole will be encountered before the EOT
value of 26 can be read. This will result in an abnormal termination of the command. If the EOT had
been set at 25 or the scanning started at sector 20,
then the Scan Command would be completed in a
normal manner.
(New Cylinder Number), and performs the following
operation if there is a difference:
PCN < NCN: Direction signal to FDD set to a 1
(high), and Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDD set to a 0
(low), and Step Pulses are issued. (Step Out.)
The rate at which Step Pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECIFY
Command. After each Step Pulse is issued NCN is
compared against PCN, and when NCN = PCN,
then the SE (Seek End) flag is set in Status Register
o to a 1 (high); and the command is terminated.
During the Command Phase of the Seek operation
the FDC is in the FDC BUSY state, but during the
Execution Phase it is in the NON BUSY state. While
the FDC is in the NON BUSY state, another Seek
Command may be issued, and in this manner parallel seek operations may be done on up to 4 Drives at
once.
If an FDD is in a NOT READY state at the beginning
of the command execution phase or during the seek
operation, then the NR (NOT READY) flag is set in
Status Register 0 to a 1 (high), and the command is
terminated.
Note that the 8272A Read and Write Commands do
not have implied Seeks. Any R/W command should
be preceded by: 1) Seek Command; 2) Sense Interrupt Status; and 3) Read ID.
RECALIBRATE
This command causes the read/write head within
the FDD to retract to the Track 0 position. The FDC
clears the contents of the PCN counter, and checks
the status of the. Track 0 signal from the FDD. As
long as the Track 0 signal is low, the Direction signal
remains 1 (high) and Step Pulses are issued. When
the Track 0 signal goes high, the SE (SEEK END)
flag in Status Register 0 is set to a 1 (high) and the
command is terminated. If the Track 0 signal is still
low after 77 Step Pulses have been issued, the FDC
sets the SE (SEEK END) and EC (EQUIPMENT
CHECK) flags of Status Register 0 to both 1s
(highs), and terminates the command.
During the Scan Command data is supplied by either
the processor or DMA Controller for comparison
against the data read from the diskette. In order to
avoid having the OR (Over Run) flag set in Status
Register 1, it is necessary to have the data available
in less than 27 f-ts (FM Mode) or 13 f-ts (MFM Mode).
If an Overrun occurs the FDC terminates the command.
SEEK
The read/write within the FDD is moved from cylinder to cylinder under control of the Seek Command.
The FDC compares the PCN (Present Cylinder Number) which is the current head position with the NCN
The ability to overlap RECALIBRATE Commands to
multiple FDDs, and the loss of the READY signal, as
described in the SEEK Command, also applies to
the RECALIBRATE Command.
7-20
inter
8272A
mands to the head unload state. This timer is programmable from 16 to 240 ms in increments of
16 ms (01 = 16 ms, 02 = 32 ms . . . . OF =
240 ms). The SRT (Step Rate Time) defines the time
interval between adjacent step pulses. This timer is
programmable from 1 to 16 ms in increments of
1 ms (F = 1 ms, E = 2 ms, 0 = 3 ms, etc.). The
HlT (Head load Time) defines the time between
when the Head load signal goes high and when the
Read/Write operation starts. This timer is programmable from 2 to 254 ms in increments of 2 ms (01 =
2 ms, 02 = 4 ms, 03 = 6 ms .... FE = 254 ms).
SENSE INTERRUPT STATUS
An Interrupt signal is generated by the FDC for one
of the following reasons:
1) Upon entering the Result Phase. of:
a) Read Data Command
b) Read a Track Command
c) Read 10 Command
d) Read Deleted Data Command
e) Write Data Command
f) Format a Cylinder Command
The step rate should be programmed 1 ms longer
than the minimum time required by the drive.
g) Write Deleted Data Command
h) Scan Commands
The time intervals mentioned above are a direct
function of the clock (ClK on pin 19). Times indicated above are for an 8 MHz clock, if the clock was
reduced to 4 MHz (mini-floppy application) then all
time intervals are increased by a factor of 2.
2) Ready Line of FDD changes state
3) End of Seek or Recalibrate Command
4) During Execution Phase in the NON-DMA Mode
Interrupts caused by reasons 1 and 4 above occur
during normal command operations and are easily
discernible by the processor. However, interrupts
caused by reasons 2 and 3 above may be uniquely
identified with the aid of the Sense Interrupt Status
Command. This command when issued resets the
interrupt signal and via bits 5, 6, and 7 of Status
Register 0 identifies the cause of the interrupt.
The choice of DMA or NON-DMA operation is made
by the NO (NON-DMA) bit. When this bit is high
(NO = 1) the NON-DMA mode is selected, and
when NO = 0 the DMA mode is selected.
SENSE DRIVE STATUS
This command may be used by the processor whenever it wishes to obtain the status of the FDDs.
Status Register 3 contains the Drive Status information.
Neither the Seek or Recalibrate Command have a
Result Phase. Therefore, it is mandatory to use the
Sense Interrupt Status Command after these commands to effectively terminate them and to provide
verification of the head position (PCN).
INVALID
Table 11. Seek, Interrupt Codes
Seek End Interrupt Code
Bit 5
BitS
Bit7
If an invalid command is sent to the FDC (a command not defined above), then the FDC will terminate the command. No interrupt is generated.by the
8272A during this condition. Bit 6 and bit 7 (010 and
ROM) in the Main Status Register are both high
("1") indicating to the processor that the 8272A is in
the Result Phase and the contents of Status Register 0 (STO) must be read. When the processor reads
Status. Register 0 it will find an 80H indicating an
invalid command was received.
Cause
0
1
1
Ready Line Changed
State, Either Polarity
1
0
0
Normal Termination
of Seek or Recalibrate
Command
1
1
0
Abnormal Termination
of Seek or Recalibrate
Command
A Sense Interrupt Status Command must be sent
after a Seek or Recalibrate interrupt, otherwise the
FDC will consider the next command to be an Invalid
Command.
SPECIFY
In some applications the user may wish to use this
command as a No-Op command, to place the FOC
in a standby or no operation state.
The Specify Command sets the intitial values for
each of the three internal timers. The HUT (Head
Unload Time) defines the time from the end of the
Execution Phase of one of the Read/Write Com-
7-21
inter
8272A
Table 12. Status Registers
Bit
No.
Name
Description
Symbol
STATUS REGISTER 0
D7
Interrupt
Code
IC
D7 = a and D6 = a
Normal Termination of Command, (NT). Command was completed and
properly executed.
D7 = a and D6 = 1
Abnormal Termination of Command, (AT). Execution of Command was
started, but was not successfully completed.
D6
D7 =1 and D6 = a
Invalid Command issue, (lC). Command which was issued was never
started.
D7 = 1 and D6 = 1
Abnormal Termination because during command execution the ready
signal from FDD changed state.
D5
Seek End
SE
When the FDC completes the SEEK Command, this flag is set to 1
(high).
D4
Equipment
Check
EC
If a fault Signal is received from the FDD, or if the Track a Signal fails
to occur after 77 Step Pulses (Recalibrate Command) then this flag is
set.
D3
Not Ready
NR
When the FDD is in the not-ready state and a read or write command
is issued, this flag is set. If a read or write command is issued to Side 1
of a single sided drive, then this flag is set.
D2·
Head
Address
HD
This flag is used to indicate the state of the head at Interrupt.
D1
. Do
Unit Select 1
US 1
Unit Select a
usa
These flags are used to indicate a Drive Unit Number at Interrupt.
STATUS REGISTER 1
End of
Cylinder
EN
When the FDC tries to access a Sector beyond the final Sector of a
Cylinder, this flag is set.
D5
Data Error
-
DE
When the FDC detects a CRC error in either the ID field or the data
field, this flag is set.
D4
Over Run
OR
If the FDC is not serviced by the main-systems during data transfers,
within a certain time interval, this flag is set.
No Data
ND
D7
Not used. This bit is always a (low).
D6
Not used. This bit always a (low).
D3
D2
During execution of .READ DATA, WRITE DELETED DATA or SCAN
Command, if the FDC cannot find the Sector specified in the IDR
Register, this flag is set.
During executing the READ ID Command, if the FDC cannot read the
ID field without an error, then this flag is set.
During the execution of the READ A Cylinder Command, if the starting
sector cannot be found, then this flag is set. .
7-22
8272A
Table 12. Status Register (Continued)
Bit
No.
Name
Description
Symbol
STATUS REGISTER 1 (Continued)
D1
Not
Writable
NW
During execution of WRITE DATA, WRITE DELETED DATA or Format
A Cylinder Command, if the FDC detects a write protect signal from the
FDD, then this flag is set.
Do
Missing
Address
Mark
MA
If the FDC cannot detect the ID Address Mark after encountering the
index hole twice, then this flag is set.
If the FDC cannot detect the Data Address Mark or Deleted Data
Address Mark, this flag is set. Also at the same time, the MD (Missing
Address Mark in Data Field) of Status Register 2 is set.
STATUS REGISTER 2
Not used. This bit is always 0 (low).
D7
D6
Control
Mark
CM
During executing the READ DATA or SCAN Command, if the FDC
encounters a Sector which contains a Deleted Data Address Mark, this
flag is set.
Ds
Data.Error in
Data Field
DD
If the FDC detects a CRC error in the data field then this flag is set.
D4
Wrong
Cylinder
WC
This bit is related with the ND bit, and when the contents of C on the
medium is different from that stored in the IDR, this flag is set.
D3
Scan Equal
Hit
SH
During execution, the SCAN Command, if the condition of "equal" is
satisfied, this flag is set.
D2
Scan Not
Satisfied
SN
During executing the SCAN Command, if the FDC cannot find a Sector
on the cylinder which meets the condition, then this flag is set.
D1
Bad
Cylinder
BC
This bit is related with the ND bit, and when the content of C on the
medium is different from that stored in the IDR and the content of C is
FF, then this flag is set.
Do
Missing
Address
Mark in Data
Field
MD
When data is read from the medium, if the FDC cannot find a Data .
Address Mark or Deleted Data Address Mark, then this flag is set.
STATUS REGISTER 3
D7
Fault
FT
This bit is used to indicate the status of the Fault signal from the FDD.
D6
Write
Protected
WP
This bit is used to indicate the status of the Write Protected signal from
the FDD.
Ds
Ready
RDY
This bit is used to indicate the status of the Ready signal from the
FDD.
D4
Track 0
TO
This bit is used to indicate the status of the Track 0 signal from the
FDD.
D3
Two Side
TS
This bit is used to indicate the status of the Two Side signal from the
FDD.
D2
Head
Address
HD
This bit is used to indicate the status of Side Select signal to the FDD.
D1
Unit Select 1
US 1
This bit is used to indicate the status of the Unit Select 1 signal to the
FDD.
Do
Unit Select 0
USO
This bit is used to indicate the status of the Unit Select 0 signal to the
FDD.
7-23
inter
8272A
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature ............. O°C to + 70°C
Storage Temperatur~ .......... -40·C to + 125·C
All Output Voltages ................. - 0.5 to + 7V
All Input Voltages ........ : ......... -0.5 to +7V
Supply Voltage Vee ................ -0.5 to + 7V
Power Dissipation ........................ 1 Watt
'TA = 25°C
D.C. CHARACTERISTICS
TA
=
O·Cto + 70°C, Vee
+5V ±10%
Limits
Parameter
Symbol
=
Min
Unit
Max
Test
Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
Vee
V
lee
Vee Supply Current
120
mA
IlL
Input Load Current
(All Input Pins)
10
-10
/Jo A
/Jo A
VIN = Vee
VIN = OV
2.4
. IOL = 2.0mA
IOH = -400/JoA
ILOH
High Level Output
Leakage Current
10
/Jo A
Vour = Vee
IOFL
Output Float
Leakage Current
±10
/Jo A
0.45C
CAPACITANCE
Vour ~ Vee
TA = 25·C, fc = 1 MHz, Vee = OV
Limits
Symbol
s:
Parameter
Min
Unit
Max
CIN(
< )C
2.0
TEST POINTS
0.8
0.45
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
0.8
! J C l = 1 0 0 PF
210606-7
-=
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and O.BV for a Logic "0".
210606-B
CL = 100 pF
CL Includes Jig Capacitance
WAVEFORMS
=r=
=1
PROCESSOR READ OPERATION
DACK
A,.CS.
,
_-'-.R-_---~~~--~-----------------'R-R==========~~~----'R-' .
I~·_----IRD----_I
DAT~
-
-
-
-
-
-
-
-
-
-
-
- 4 - - -t OF
-
INT
210606-9
7-27
intJ
8272A
WAVEFORMS (Continued)
PROCESSOR WRITE OPERATION
Arl, CS. DACK
.....-tAW
I-----tww-------<~
tow
DATA
I.
two
'-
tNT
210606-10
DMA OPERATION
-.
DRQ
I--------IRQRW------~
WRorRD
1.----tROW----!
210606-11
7-28
8272A
WAVEFORMS
(Continued)
CLOCK TIMING
elK
210606-12
FDD WRITE OPERATION
WRITE ENABLE
(WE)
Icp
210606-13
PreshiftO
Preshift 1
Normal
0
0
Late
0
1
Early
1
0
Invalid
1
1
7-29
inter
8272A
WAVEFORMS (Continued)
SEEK OPERATION
STABLE
...--t05
tso---+-
LeTI
DIRECTION
STEP
I----------'sc----------~
210606-14
FLT RESET
.
FAULT RESET
FAIL UNSAFE RESET
INDEX
r------------------------------,
/i'-_"R __
.
-'~
'---210606-15
210606-16
7-30
intJ
8272A
WAVEFORMS (Continued)
FDD READ OPERATION
READDA~A
.
tROO-"
.
~-------------------------
READ DA_T_A_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
WINDOW
~~""'I-----IWRD--.
•
~-------------------------J-------------tWWCy--------~
210606-17
TERMINAL COUNT
RESET
RESET
TC
210606-18
210606-19
7-31
intJ
82077
CHMOS SINGLE-CHIP FLOPPY DISK CONT,ROLLER.
•
Single-Chip Floppy Disk Solution
-100% PC-AT Hardware Compatible
-100% PS/2™ Hardware Compatible
-Integrated Drive and Data Bus
Buffers
•
Integrated Analog Data Separator
- 250 Kbits/sec
- 300 Kbits/sec
- 500 Kbits/sec
-1 Mbits/sec (82077-1 only)
•
•
High Speed Processor Interface
•
•
•
•
•
•
Vertical Recording Support
12 mA Data Bus Drivers, 40 mA Disk .,
Drivers
Four Fully Decoded Drive Select and
Motor Signals
Programmable Write Precompensation
Delays
Addresses 256 Tracks Directly,
Supports Unlimited Tracks
16 Byte FIFO
68-Pin.PLCC
The 82077 floppy disk controller has completely integrated all of the logic required for floppy disk control. The
82077, a 24 MHz crystal, a resistor package and a device chip select implements a PC-AT or PS/2TM solution.
All programmable options default to compatible values. The dual PLL data separator has better performance
than most board level/discrete PLL implementations. The FIFO allows better system performance in multlmaster systems (e.g. PS/2TM).
The 82077 is fabricated with Intel's CHMOS III technology and is availabl~ in a S8-lead PLCC (plastic) pa.qkage.
A2
DBO
Vss
DB1
DB2
DB3
Vss
DB4
Vee
DB5
DB6
Vss
DB7
o
Vee
Vss
DSO
MEO
DIR
STEp·
Vss
82077
WRDATA
WE
HDSEL
Vss
DENSEL
MFM
INT
NC
AVee
AVss
ORO
TC
NC
INDX
290166-1
Figure 1. 82077 Pinout
PS/2TM is a trademark of IBM.
7·32
October 1988
Order Number: 290166-001
inter
82077
Table 1.82077 Pin Description
Symbol Pin# I/O
Description
HOST INTERFACE
32
I
RESET: A high level places the 82077 in a known idle state. All registers are cleared
except those set by the Specify command.
CS
6
I
CHIP SELECT: Decodes base address range and qualifies RD and WR inputs.
AO
A1
A2
7
8
10
I
ADDRESS: Selects one of the host interface registers:
RESET
A2 A1 AO
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
Register
0
R Status Register A
1
R Status Register B
0 R/W Digital Output Register
1
Reserved
0
R Main Status Register
0
W Data Rate Select Register
1 R/W Data (FIFO)
Reserved
0
1
R Digital Input Register
1
W Configuration Control Register
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
11
13
14
15
17
19
20
22
I/O DATA BUS: Data bus with 12 mA drive
RD
4
I
READ: Control signal
WR
5
I
WRITE: Control signal
DRO
24
0
DMA REQUEST: Requests service from a DMA controller. Normally active high, but
goes to high impedance in AT mode when the appropriate bit is set in the DOR.
DACK
3
I
DMA ACKNOWLEDGE: Control input that qualifies the RD, WR inputs in DMA cycles.
TC
25
.1
TERMINAL COUNT: Control line from a DMA controller that terminates the current disk
transfer. TC is accepted only while DACK is active. This input is active high in the AT
mode and active low in the PS/2TM mode.
INT
23
0
INTERRUPT: Signals a data transfer in non-DMA mode and when status is valid.
Normally active high, but goes to high impedance in AT mode when the appropriate bit is
set in the DOR.
X1
X2
33
34
CRYSTAL 1,2: Connection for a 24 MHz fundamental mode parallel resonant crystal. X1
may be driven with a MOS level clock and X2 would be left unconnected.
7·33
82077
Table 1.82077 Pin Description (Continued)
Symbol
Pin#
110
Description
HOST INTERFACE (Continued)
IDENT
27
I
IDENTITY: Strapping option for either PC-AT or PSI2™ compatibility. Various
signals change levels depending upon the mode.
AT MODE: The AT mode is selected by strapping IDENT to VCC. In this mode,
DMA Gate logic is enabled, TC and DENSEL become active high signals (defaults
to a 5.25" floppy disk).
PSI2™ MODE: The PSI2™ standard mode is selected by strapping IDENT to
ground. In this mode, the DMA Gate logic is disabled, TC and DENSEL become
active low signals (defaults to a 3.5" disk).
DISK CONTROL (All outputs have 40 rnA drive capability)
INVERT
35
I
INVERT: Strapping option. Determines the polartity of all signals in this section.
Should be strapped to ground when using the internal buffers and these signals
become active LOW. When strapped to VCC, these signals become active high
and external inverting drivers and receivers are Jequired.
'
MEO
ME1
ME2
ME3
57
61
63
66
0
MEO-3: Decoded Motor enables for drives 0-3. The motor enable pins are directly
controlled via the Digital Output Register.
DSO
DS1
DS2
DS3
58
62
64
67
0
DRIVE SELECT 0-3: Decoded drive selects for drives 0-3. These outputs are
decoded from the select bits in the Digital Output Register and gated by MEO-3.
HDSEL
51
0
HEAD SELECT: Selects which side of a disk is to be used. An active level selects
side 1.
STEP
55
0
STEP: Supplies step pulses to the drive.
DIR
56
0
DIRECTION: Controls the direction the head moves when a step signal is present.
The head moves toward the center if active.
WRDATA
53
0
WRITE DATA: FM or MFM serial data to the drive. Precompensation value is
selectable through software.
WE
52
0
WRITE ENABLE: Drive control signal that enables the head to write onto the disk.
DENSEL
49
0
DENSITY SELECT: Indicates whether a low (250/300 Kbps) or high (500 Kbps/1
Mbps) data rate has been selected. When PSI2™ mode is selected, a high signal
means that low density was enabled. In the AT mode, a high signal indicates high
density.
DSKCHG
31
I
DISK CHANGE: This input is reflected in the Digital Input Register.
DRV2
30
I
DRIVE2: This indicates whether a second drive is installed a'nd is reflected in
Status Register A.
82077
Table 1.82077 Pin Description (Continued)
Symbol
Pin#
Description
I/O
DISK CONTROL (All outputs have 40 mA drive capability) (Continued)
TRKO
2
I
TRACKO: Control line that indicates that the head is on track O.
WP
1
I
WRITE PROTECT: Indicates whether the disk drive is write protected.
26
I
INDEX: Indicates the beginning of the track.
READ DATA: Serial data from the disk. INVERT also affects the polarity of this
signal.
INDX
PLLSECTION
RDDATA
41
I
HIFIL
38
I/O
HIGH FILTER: Analog reference signal for internal data separator compensation.
This should be filtered by an external capacitor to LOFIL.
LOFIL
37
I/O
LOW FILTER: Low noise ground return for the reference filter capacitor.
MFM
48
0
MFM: Indication of the current data encoding/decoding mode. MFM is active high.
DRATEO
DRATE1
28
29
0
DATARATEO-1: Reflects the contents of bits 0,1 of the Data Rate Register.
MISCELLANEOUS
+ 5V
VCC
18
39
40
60
68
Voltage:
GND'
9
12
16
21
36
50
54
59
65
Ground
AVCC
46
Analog Supply
AVSS
45
. Analog Ground
NC
42
43
44
47
No Connection: These pins MUST be left unconnected; they access unsupported
internal PLL modes.
7-35
inter
82077
wide motor speed variation with exceptionally low
soft error rates. The microprocessor interface has a
12 mA drive buffer on the data bus plus 100% hardware register compatibility for PC-AT's and
PS/2TM'S. The 16-byte FIFO with programmable
thresholds is extremely useful in multi-master systems (PS/2TM) or systems with a large amount of
bus latency.
1.0 INTRODUCTION
The 82077 is a true single-chip floppy disk controller
for the PC-AT and PS/2TM. The 82077, a 24 MHz
crystal, a resistor package and a chip select implement a complete design. All drive control signals are
fully decoded and have 40 mA drive buffers with selectable polarity. Signals returned from the drive are
sent through on-chip input buffers with hysteresis for
noise immunity. The integrated analog data separator needs no external compensation yet allows for a
4
OATA
BUS
Upon reset, the 82077 defaults to 8272A functionality. New features are either selected via hardware
straps or new commands. Figure 1-1 is a block diagram of the 82077.
~I
TC-+
ORQ-+
OACK
INT
RO-+
WR-+
CS-+
AO-2-+
INTERFACE
LOGIC
WE
MFM
B
U
S
RESET-+
Xl
---OSKCHG
X2
ORV2
ORATE
WP
0-1
TRKO
....._ _ IOX
OSO-3
ME0-3
OENSEL
<--~--,..
OIR
STP
HOL
290166-2
Figure 1·1.82077 Block Diagram
7-36
82077
1.1 Oscillator
1:
2.0 MICROPROCESSOR INTERFACE
.1.
Xl
24 MHz
jCRYSTAL
82077
X2
-
GND
290166-3
The interface consists of the standard asynchronous
signals: RD, WR, CS, AO-A3, INT, DMA control and
a data bus. The address lines select between configuration registers, the FIFO and control/status registers. This interface can be switched between PC-AT
or PS/2™ normal modes. The PS/2™ register set
is a superset of the registers found in a PC-AT. For
PC-AT applications, the PS/2TM register set is located at unused locations. Note that the registers are
always present regardless of which mode is selected.
Figure 1-2. Crystal Oscillator Circuit
The 24 MHz clock can be supplied either by a crystal
or a MOS level square wave. All internal timings are
referenced to this clock or a scaled count which is
data rate dependent.
The crystal oscillator must be allowed to run for
10 ms after V'CC has reached 4.5V or exiting the
POWER DOWN mode to guarantee that it is stable.
Crystal Specifications
Frequency:
Mode:
Series Resistance:
24 MHz
Parallel Resonant
Fundamental Mode
Less than 40.0.
Shunt Capacitance: Less than 5 pF
2.1 Status, Data and Control Registers
The base address range is supplied via the CS pin.
For PC-AT or PS/2™ designs this would be 3FO
Hex to 3F7 Hex.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1.2 Perpendicular Recording Mode
An added capability of the 82077 is the ability to
interface directly to perpendicular recording floppy
drives that use the Toshiba format. Perpendicular recording differs from the traditional longitudinal method by orienting the, magnetic bits vertically. This
scheme then packs in more data bits for the same
area.
The 82077 with Toshiba perpendicular recording
drives can at a minimum, read standard 3.5" floppies as well as read and write perpendicular media.
Some manufacturers offer drives that can read and
write standard and perpendicular media in a perpendicular media drive.
A single command puts the 82077 into perpendicu·
lar mode. All other commands operate as they normally do. The perpendicular mode requires the 1
t0bps data rate of the 82077. At this data rate, the
FIFO eases the host interface bottleneck due to the
speed of data transfer, to or from the disk.
Register
A2 A1 AO
Status Register A
0 R
Status Register B
1 R
0 R/W Digital Output Register
Reserved
1
Main Status Register
0 R
0 W
Data Rate Select Register
1 R/W Data (FIFO)
Reserved
0
Digital Input Register
1 R
Configuration Control' Register
1 W
SRA
SRB
DOR
MSR
DSR
FIFO
DIR
CCR
2.1.1 STATUS REGISTER A (SRA)
This register is read-only and monitors the state of
the interrupt pin and several disk interface pins. This
register is part of the PS/2™ register set.
7
INT
PENDING
6'
5
4'
3
2'
l'
0
DAV2
STEP
TAKO
HDSEL
INDX
WP
DIA
The INT PENDING bit is used by software to monitor
the state of the 82077 INTERRUPT pin. The bits
marked with a ... " reflect the state of drive signals
on the cable and therefore are independent of the
state of the INVERT pin.
intJ
82077
As a read-only register, there is no default value associated with a reset other than some drive bits will
change with a reset. The INT PENDING, STEP,
HDSEL, and DIR bits will be low after reset.
Table 2-1. Drive Activation Values
Drive
DORValue
0
1
1CH
2DH
4EH
8FH
2
2.1.2 STATUS REGISTER B (SRB)
3
This register is read-only and monitors the state of
several disk interface pins. This register is part of the
PS/2™ register set.
7
6
1
1
5
3'
4
DRIVE
WRDATA
RDDATA
SELO
TOGGLE
TOGGLE
2
WE
1
The DMAGATE bit is enabled only if the IDENT pin
is tied to Vee (PC-AT mode). If DMAGATE is set to a
low, the INT and DRO output pins are tristated and if
set high, INT and DRO are enabled to the system. If
IDENT is tied to VSS, DMAGATE has no effect upon
the INT and DRO pins and they are always active.
0
MOT
MOT
ENl
ENO
This RESET bit clears the basic core of the 82077
and the FIFO circuits. Once set, it remains set until
the user clears this bit. This bit is set by a chip reset
and the 82077 is held in a reset state until the user
clears this bit. The RESET bit has no effect upon this
register. The RESET pin will clear this register.
As the only drive input, RDDATA TOGGLE's activity
is independent of the INVERT pin level and reflects
the level as seen on the cable.
The two TOGGLE bits do not read back the state of
their respective pins directly. Instead, the pins drive
a Flip/Flop which produces a wider and more reliably read pulse. Bits 6 and 7 are undefined and always return a 1.
2.1.4 DATARATE SELECT REGISTER (DSR)
This register is included for compatibility with the
82072 floppy controller and is write-only. Changing
the data rate changes the timings of the drive control signals. To ensure that drive timings are not violated when changing data rates, choose a drive timing such that the fastest data rate will not violate the
timing.
After any reset, the activity on the TOGGLE pins is
cleared. Drive select and Motor bits cleared by the
RESET pin and not software resets.
2.1.3 DIGITAL OUTPUT REGISTER (DOR)
The Digital Output Register contains the drive select
and motor enable bits, a reset bit and a DMA GATE
bit. This register is used in both PC-AT and PS/2™
designs.
.
7
s/w
6
POWER
RESET DOWN
7
6
5
4
3
MOT
MOT
MOT
MOT
DMA
EN3
EN2
ENl
ENO
GATE
2
RESET
1
4
PRE·
PRE·
PRE·
0
COMP
COMP
COMP
2
1
0
3
2
1
0
DRATE DRATE
SEL 1
SELO
0
This register is the same as used in the 82072 except that the internal/external PLL select bit is removed. It is recommended that bit 5 be written with
a 0 for compatibility.
DRIVE DRIVE
SELl
5
SELO
The MOT ENx bits directly control their respective
motor enable pins (MEO-3). A one means the pin is
active, the INVERT pin determines which level that
is. The DRIVE SELx bits are decoded to provide four
drive select lines and only one may be active at a
time. A one is active and the INVERT pin determines
the level on the cable. Standard programming practice is to set both MOT ENx and DRIVE SELx bits at
the same time.
S/W RESET behaves the same as DOR RESET except that this reset is self clearing.
POWER DOWN deactivates the internal clocks and
shuts off the oscillator. Disk control pins are put in
an inactive state. All input signals must be held in a
valid state (D.C. level 1 or 0). POWER DOWN is exited by activating one of the reset functions.
Table 2-1 lists a set of DOR values to activate the
drive select and motor enable for each drive.
PRECOMPO-2 adjusts the WRDATA outputto the
disk to compensate for magnetic media phenomena
known as bit shifting. The data patterns that are susceptible to bit shifting are well understood and the
7-38
inter
82077
ROM-Indicates that the host can transfer data if
set to a 1. No access is permitted if set to a O.
82077 compensates the data pattern as it is written
to the disk. The amount of precompensation is dependent upon the drive and media but in most cases
the default value is acceptable.
DIO-Indicates the direction of a data transfer once
ROM is set. A 1 indicates a read and a 0 indicates a
write is required.
The 82077 starts precompensating the data pattern
starting on Track O. The CONFIGURE command can
change the track that precompensating starts on.
Table 2-2 lists the precompensation values that can
be selected and Table 2-3 lists the default precompensation values. The default value is selected if the
three bits are zeros.
NON-DMA-This mode is selected in the SPECIFY
command and will be set to a 1 during the execution
phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.
Table 2·2. Precompensation Delays
PRECOMP
COMMAND BUSY-This bit is set to a one when a
command is in progress. This bit will go active after
the command byte has been accepted and goes inactive at the end of the results phase. If there is no
result phase (SEEK, RECALIBRATE commands),
this bit is returned to a 0 after the last command
byte.
Precompensation Delay
432
111
001
010
011
100
101
110
000
0.00 ns-DISABLED
41.67 ns
83.34 ns
125.00 ns
166.67 ns
208.33 ns
250.00 ns
DEFAULT
DRV x BUSY-These bits are set to ones when a
drive is in the seek portion of a command, including
implied and overlapped seeks, and recalibrates.
2.1.6 FIFO (DATA)
Table 2·3. Default Precompensation Delays
Data Rate
Precompensation Delays
1 Mbps
500 Kbps
300 Kbps
200 Kbps
41.67ns
125 ns
125 ns
125 ns
All command parameter information and disk data
transfers go through the FIFO. The FIFO is 16 bytes
in size and has programmable threshold values.
Data transfers are governed by the ROM and 010
bits in the Main Status Register.
The FIFO defaults to an 8272A compatible mode
after any form of reset. This maintains PC-AT hardware compatibility. The default values can be
changed through the CONFIGURE command (enable full FIFOoperation with threshold control). The
advantage of the FIFO is that it allows the system a
larger DMA latency without causing a disk error. Table 2.5 gives several examples of the delays with a
FIFO. The data is based upon the following formula:
ORATE 0-1 select one of the four data rates as
listed in Table 2-4. The default value is 250 Kbps
upon a chip reset. Other Resets do not affect the
ORATE or PRECOMP bits.
Table 2·4. Data Rates
DRATESEL
1
0
1
0
0
1
DATA RATE
MFM
FM
1
0
1
0
1 Mbps
500 Kbps
300 Kbps
250 Kbps
Threshold# x IDATA1RATE x
Illegal
250 Kbps
150 Kbps
125 Kbps
FIFO Threshold
Examples
1 byte
2 bytes
8 bytes
15 bytes
The Main Status Register is a read-only register and
is used for controlling command input and result output for all commands.
6
ROM
DIO
5
4
3
2
1
0
NON
CMD
DRV3
DRV2
DRV1
DRVO
DMA
BSY
BUSY
BUSY
BUSY
BUSY
1.5 "'s = DELAY
Table 2·5. FIFO Service Delay
2.1.5 MAIN STATUS REGISTER (MSR)
7
81-
7-39
Maximum Delay to Servicing
at 1 Mbps Data Rate
1
2
8
15
x 8 I-I-s
x 81-1-s
x 8 I-I-s
x81-1-s
- 1.5 I-I-s
-1.5I-1-s
- 1.5 I-I-s
-1.5I-1-s
=
=
=
=
6.5 I-I-s
14.51-1-s
62.5 I-I-s
118.51-1-s
82077
FIFO Threshold
Examples
1 byte
2 bytes
8 bytes
15 bytes
This pin is set high after a pin RESET and is unaffected by DOR and DSR resets.
Maximum Delay to Servicing
at 500 Kbps Data Rate
1
2
8
15
x 16p,s -1.5p,s ==
x 16 p,s - 1.5 p,s =
x 16p,s -1.5p,s =
x 16 p,s - 1.5 p,s =
All other bits are unused and returned as 1's.
14.5p,s
30.5 p,s
126.511S
238.5 p,s
2.1.8 CONFIGURATION CONTROL
REGISTER (CCR)
This register sets the datarate and is write only. In
the PC-AT it is named the DSR.
At the start of a command, the. FIFO action is always
disabled and command parameters must be sent
based upon the ROM and 010 bit settings. As the
82077 enters the command execution phase, it
clears the FIFO of any data to ensure that invalid
data is not transferred.
7
-
An overrun or underrun will terminate the current
command and the transfer of data. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase
may be entered.
DSK
CHG
5
4
3
2
1
1
1
1
1
1
1
HIGH
DENS
The RESET pin is a global reset and clears all registers except those programmed by the SPECIFY
command. The DaR Reset bit is enabled and must
be cleared by the host to exit the reset state.
Table 2-6. DENSEL Encoding
500 Kbps
300 Kbps
250 Kbps
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
DRATE DRATE
SEL 1 SELO
2.2.1 RESET PIN
Table 2-6 shows the state of the DENSEL pin when
INVERT is low.
1 Mbps
-
1
On exiting the reset state, various internal registers
are cleared, including the CONFIGURE command
information, and the 82077 waits for a new command. Drive polling will start unless disabled by a
new CONFIGURE command.
HIGH DENS is low whenever the 500 Kbps or
1 Mbps data rates are selected. This bit is independent of the effects of the IDENT and INVERT pins.
DENSEL
-
2
On entering the reset state, all operations are terminated and the 82077 enters an idle state. Activating
reset while a disk write activity is in progress will
corrupt the data and CRC.
0'
IDENT
-
3
There are three sources of reset on the 82077; the
RESET pin, a reset generated via a bit in the DOR
and a reset generated via a bit in the DSA. All resets
take the 82077 out of the power down state.
DSKCHG monitors the pin of the same name and
reflects the opposite value seen on the disk cable,
regardless of the value of INVERT.
Data Rate
-
4
2.2 RESET
This register is used to sense the state of the
DSKCHG and DENSEL inputs and is read-only.
6
-
5
Refer to the table in the Data Rate Select Register
for values. Unused bits should be set to O.
2.1.7 DIGITAL INPUT REGISTER (DIR)
7'
6
2.2.2 DOR RESET vs DSRRESET
These two resets are functionally the same. The
DSR Reset is included to maintain 82072 compatibility. Both will reset the 8272 core which affects drive
status information and the FIFO circuits. The DSR
Reset clears itself automatically while the DOR Reset requires the host to manually clear it. DaR Reset
has precedence over the DSR Reset. The DOR Reset is set automatically upon a pin RESET. The user
must manually clear this reset bit in the DOR to exit
the reset state.
7-40
inter
82077
Additionally, the two types of drives have different
electrical interfaces. Generally, the 5.25" drive uses
open collector drivers and the 3.5" drives (as used
on PS/2TM) use totem-pole drivers. The output buffers on the 82077 do not change between open collector or totem-pole, they are always totem-pole. For
design information on interfacing 5.25" and 3.5"
drives to a single 82077, refer to Section 9.
2.3 DMA Transfers
DMA transfers are enabled with the SPECIFY command and are initiated by the 82077 by activating
the ORO pin during a data transfer command. The
FIFO is enabled directly by asserting DACK and addresses need not be valid.
3.0 DRIVE INTERFACE
3.2 Data Separator
The 82077 has integrated all of the logic needed to
interface to a floppy disk drive. All drive outputs have
40 mA drive capability and all inputs use a receive
buffer with hysteresis. The internal analog data separator requires no external components, yet allows
for an extremely wide capture range with high levels
of read-data jitter. The designer needs only to run
the 82077 disk drive Signals to the disk drive connector.
The function of the data separator is to lock onto the
incoming serial read data. When lock is achieved the
serial front end logic of the chip is provided with a
clock which is synchronized to the read data. The
synchronized clock, called Data Window, is used to
internally sample the serial data. One state of Data
Window is used to sample the data portion of the bit
cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the
read data into clock and data bytes.
3.1 Cable Interface
To support reliable disk reads the data separator
must track fluctuations in the disk data frequency.
Frequency errors primarily arise from two sources:
drive rotation speed variation and instantaneous
speed variation (ISV). A second condition, and one
that opposes the ability to track frequency shifts is
the response to bit jitter.
The INVERT pin selects between using the internal
buffers on the 82077 or user supplied inverting buffers. INVERT pulled to Vee disables the internal buffers; pulled to ground will enable them. There is no
need to use external buffers with the 82077 in
PC-AT or PSI2™ applications.
The internal data separator consists of two analog
phase lock loops (PLLs) as shown in Figure 3-1. The
two PLLs are referred to as the reference PLL and
the data PLL. The reference PLL (the master PLL) is
used to bias the data PLL (the slave PLL). The reference PLL adjusts the data PLL's operating point as a
function of process, junction temperature and supply
voltage. Using this architecture it was possible to
eliminate the need for external trim components.
The selection between the PC-AT or PSI2™ interface, through the IDENT pin, also changes the definition of the DENSEL pin. The AT interface assumes
using 5.25" drives where a high on DENSEL tells
the drive that either the 500 Kbps or 1 Mbps datarate is selected. The PSI2™ interface assumes
3.5" drives and DENSEL changes to a low for the
high datarates.
REFERENCE
OSCILLATOR
REFERENCE
PHASE LOCK LOOP
1
DISK
DATA ---+
SYNC DETECT
I
!
ANALOG TRIM DATA
SYNC. DET.
DATA
1
DATA
PHASE LOCK LOOP
INTERNAL
DW
DELAYED
DATA
READ DATA
290166-4
Figure 3·1. Data Separator Block Diagram
7-41
intJ
.82077
3.2.1 PHASE LOCK LOOP OVERVIEW
PHASE
DETECTOR
. . - - - - - _ - - - - - + _ - - A N A L O G TRIM DATA
FROM REFERENCE
PHASE LOCK LOOP
LOOP
FILTER
VCO
.... _----
READ
DATA
VCO
ENABLE
DATA
WINDOW,
REF.
FREQ.
vco
L--------- x-
2- C-LO-C-K----I FEEDBACK
INTERNAL
DW
290166-5
Figure 3-2. Data PLL
3.2.2 LOCKTIME (tLOCK)
Figure 3-2 shows the data PLL. The reference PLL
has control over the loop gain by its influence on the
charge pump and the VCO. In addition the reference
PLL controls the loop filter time constant. As a result
the closed loop transfer function of the data PLL is
controlled, and immune, to the first order, to environmental factors, and process variation.
The lock, or settling time of the data PLL is designed
to be 64 bit times. This corresponds to 4 sync bytes
in the FM mode and 8 sync bytes in the MFM mode.
This value assumes that the sync field jitter is 5%
the bit cell or less. This level of jitter should be easily
achieved for a constant bit pattern, since intersym·
bol interference should be equal, thus nearly elimi·
nating random bit shifting.
Systems of this type are often very sensitive to
noise. In the design of this data separator many
steps were taken to avoid noise sensitivity problems.
The analog section of the chip has a separate VSS
pin (AVSS) which should be connected externally to
a noise free ground. This provides a clean' basis for
VSS referenced signals. In addition many analog circuit features were employed to make the overall system as insensitive to noise as possible.
3.2.3 CAPTURE RANGE
Capture Range is the maximum frequency range
over which the data separator will acquire phase
lock with the incoming RDDATA signal. In a floppy
disk environment, this frequency variation is composed of two components: drive motor speed error
and ISV. Frequency is a factor which may determine
the maximum level of the ISV (Instantaneous Speed
Variation) component. In general, as frequency increases the allowed magnitude of the ISV component will decrease. When determining the capture
range requirements, the designer should take the
maximum amount of frequency error for the disk
drive and double it to account for media switching
between drives.
3.2.1 JITTER TOLERANCE
The jitter immunity of the system is dominated by the
data PLL's response to phase impulses. This is measured as a percentage of the theoretical data window by dividing the maximum readable bit shift by a
% bitcell distance. For instance, if the maximum allowable bit shift is 300 nsfor a 500 Kbps data
stream, the jitter tolerance is 60%. The.graph in Figure 12-1 of the Data Separator Characteristics sec·
tion illustrates the jitter tolerance of the 82077
across a ± 6% frequency range.
7-42
infef
82077
PRECOMP
SELECTION FROM
DSR
WRDATA
TO OUTPUT
290166-6
NOTE:
PSO,1 are 8272A control signals but are not available as outputs on the 82077.
Figure 3-3. Precompensation Block Diagram
The top block is a 13-bit shift register with the no
delay tap being in the center. This allows 6 levels of
early and late shifting with respect to nominal. The
shift register is clocked at the main clock rate
(24 MHz). The output is fed into 2 multiplexors-one
for early and one for late. A final stage of multiplexors combines the early, late and normal data
stream back into one which is the WRDATA output.
3.2.4 REFERENCE FILTER
To provide a clean bias voltage for the internal data
separator, two pins have been provided to filter this
signal. It is recommended to place a 0.005 uF capacitor between HIFIL and LOFIL to filter the reference signal. A smaller capacitance will reduce the
effectiveness of the filter and could result in a lower
jitter tolerance. Conversely, a larger capacitance has
the potential to further improve jitter tolerance, but
will result in an increased settling time after a
change· in data rate. For instance, a filter capacitor
of 0.005 uF will yield a settling time of approximately
500 microseconds. Since HIFIL generates a relatively low current signal (approximately 10 uA), care also
needs to be taken to avoid external leakage on this
pin. The quality of the capacitor, solder flux, grease,
and dirt can all impact the amount of leakage on the
board.
4.0 CONTROLLER PHASES
For simplicity, command handling in the 82077 can
be divided into three phases: Command, Execution
and Result. Each phase is described in the following
secions.
4.1 Command Phase
After a reset, the 82077 enters the command phase
and is ready to accept a command from the host.
For each of the commands, a defined set of command code bytes and parameter bytes has to be
written to the 82077 before the command phase is
complete (Please refer to Section 5.0 for the command descriptions). These bytes of data must be
transferred in the order prescribed.
3.3 Write Precompensation
The write precompensation logic is used to minimize
bit shifts in the RDDAT A stream from the disk drive.
The shifting of bits is a known phenomena of magnetic media and is dependent upon the disk media
AND the floppy drive.
Before writing to the 82077, the host must examine
the ROM and 010 bits of the Main Status Register.
ROM, 010 must be equal to "1" and "0" respectively before command bytes may be written. ROM is
set false by the 82077 after each write cycle until the
received byte is processed. The 82077 asserts ROM
again to request each parameter byte of the com-
The 82077 monitors the bit stream that is being sent
to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late (or not at all)
relative to the surrounding bits. Figure 3-3 is a block
diagram of the internal circuit.
7-43
inter
82077
mand, unless an illegal command condition is detected. After the last parameter byte is received,
ROM remains "0", and the 82077 automatically enters the next phase as defined by the command definition.
4.2.1 NON-DMA MODE, TRANSFERS FROM THE
FIFO TO THE HOST
The INT pin and ROM bits in the Main Status Register are activated when the FIFO contains (16< threshold» bytes, or the last bytes of a full sector
transfer have been placed in the FIFO. The INT pin
can be used for interrupt driven systems and ROM
can be used for polled sytems. The host must respond to the request by reading data from the FIFO.
This process is repeated until the last byte is transferred out of the FIFO. The 82077 will deactivate the
INT pin and ROM bit when the FIFO becomes empty.
The FIFO is disabled during the command phase to
retain compatibility with· the 8272A, and to provide
for the proper handling of the "Invalid Command"
condition.
4.2 Execution Phase
All data transfers to or from the 82077 occur during
the execution phase, which can proceed in OMA or
non-OMA mode as indicated in the SPECIFY command.
After a reset, the FIFO is disabled. Each data byte is
transferred by anlNT or ORO. depending on the
OMA mode. The CONFIGURE command can enable
the FIFO and set the FIFO threshold lIalue.
The following paragraphs detal! the operation of the
FIFO flow control.
In these descriptions,
is defined as the number of bytes
available to the 82077 when service is requested
from the host, and ranges from 1 to 16. The parameter FIFOTHR whiCh the user programs is one less,
and ranges from 0 to 15.
4.2.2 NON-DMA MODE, TRANSFERS FROM THE
HOST TO THE FIFO
The INT pin and ROM bit in the Main Status Register
. are activated upon entering the execution phase of
data transfer commands. The host must respond to
the request by writing data into the FIFO. The INT
pin and ROM bit remain true until the FIFO becomes
full. They are set true again when the FIFO has
bytes remaining in the FIFO. The ·INT
pin will also be deactivated if TC and OACK # both
go inactive. The 82077 enters the result phase after
the last byte is taken by the 82077 from the FIFO
(i.e. FIFO empty condition).
4.2.3 DMA MODE,TRANSFERS FROM THE FIFO
A low threshold value (I.e. 2) results in longer periods of time between service requests, but requires
faster servicing of the request, for both read and
write cases. The host reads (writes) from (to) the
FIFO until empty (full), then the transfer request
goes inactive. The host must be very responsive to
the service request. This is the desired case for use
with a "fast" system.
TO THE. HOST
The 82077 activates the ORO pin when the FIFO
contains (16- bytes remaining in the FIFO. The
82077 will also deactivate the ORO pin when TC
becomes true (qualified by OACK#), indicating that
no more data is required. ORO goes inactive after
OACK # goes active for the last byte of a data transfer (or on the active edge of WR# of the last byte, if
no edge is present on OACK #). A data overrun may
occur if ORO is not removed in time to prevent an
unwanted cycle.
4.3 Result Phase
The generation of INT determines the beginning of
the result phase. For each of the commands, a defined set of result bytes has to be read from the
82077 before the result phase is complete. (Refer to
Section 5.0 on command descriptions.) These bytes
of data must be read out for another command to
start.
ROM and 010 must both equal "1" before the result
bytes may be read from the FIFO. After all the result
bytes have been read, the ROM and 010 bits switch
to "1" and "0" respectively, and the CB bit is
cleared. This indicates that the 82077 is ready to
accept the next command.
4.2.5 DATA TRANSFER TERMINATION
The 82077 supports terminal count explicitly through
the TC pin and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector
transfers, the EOT parameter can define the last
sector to be transferred in a single or multi sector
transfer. If the last sector to be transferred is a partia sector, the host can stop transferring the data in
mid-sector, and the 82077 will continue to complete
the sector as if a hardware TC was received. The
only difference between these implicit functions and
TC is that they return "abnormal termination" result
status. Such status indications can be ignored if they
were expected.
5.0 COMMAND SETIDESCRIPTIONS
Commands can be written whenever the 82077 is in
the command phase. Each command has a unique
set of needed parameters and status results. The
82077 checks to see that the first byte is a valid
command and, if valid, proceeds with the command.
If it was invalid, an interrupt is issued. The user
would send a SENSE INTERRUPT STATUS command which would return an invalid command error.
Table 5-1 is a summary of the Command set.
7-45
inter
82077
Table 5·1; 82077 Command Set
Phase
DATA BUS
R/W
07
06
05
04
MT
MFM
SK
0
0
0
0
03
Remarks
O2
01
Do
1
HDS
1
DS1
DSO
READ DATA
Command
W
W
W
W
W
W
W
.0
0
0
0
Sector ID information prior
to Command execution
C
H
R
N
EaT
GPL
DTL
w
W
Data transfer between the
FDD and system
Execution
Result
Command Codes
R
R
R
R
R
R
R
Status information after
Command execution
STO
ST 1
ST 2
C
H
R
Sector ID information after
Command execution
N
READ DELETED DATA
Command
W
W
W
W
W
W
W
MT
MFM
SK
0
0
0
0
0
1
0
1
HDS
0
0
DS1
DSO
Sector ID information prior
to Command execution
C
H
R
N
EaT
GPl
DTL
w
W
Data transfer between the
FDD and system
Execution
Result
Command Codes
STO
ST1
ST2
C
H
R
R
R
R
R
R
R
R
Status information after
Command execution
Sector ID information after
Command execution
N
WRITE DATA
Command
W
W
W
W
W
W
W
w
W
MT
MFM
0
0
0
0
0
0
0
0
0
DS1
1
DSO
Command Codes
Sector ID information prior
to Command execution
C
H
R
N
EaT
GPL
DTL
Execution
Result
1
HDS
Data transfer between the
system and FDD
R
R
R
R
R
R
R
STO
ST1
ST2
C
H
R
N
7-46
Status information after
Command execution
Sector ID information after
Command execution
intJ
82077
Table 5-1. 82077 Command Set (Continued)
Phase
DATA BUS
R/W
D7
D6
Ds
MT
MFM
0
0
0
0
D3
D4
Remarks
D2
D1
Do
1
OSO
WRITE DELETED DATA
Command
W
W
W
W
0
0
1
0
0
0
HOS
OS1
W
W
W
W
W
Data transfer between the
FOO and system
Execution
Result
Command Codes
Sector 10 information prior
to Command execution
C
H
R
N
EDT
GPL
OTL
Status information after
Command execution
STO
ST1
ST2
C
H
R
N
R
R
R
R
R
R
R
Sector 10 information after
Command execution
READ TRACK
Command
W
W
W
W
W
W
W
W
W
0
0
MFM
0
0
0
0
0
0
0
0
HDS
1
DS1
0
Sector ID information prior
to Command execution
C
H
R
N
EOT
GPL
DTL
Data transfer between the
FDD and system. FDC
reads all of cylinders
contents from index hole to
EDT
Execution
Result
Command Codes
DSO
Status information after
Command execution
STO
ST1
ST2
C
H
R
N
R
R
R
R
R
R
R
Sector 10 information after
Command execution
VERIFY
Command
W
W
W
W
W
W
W
W
W
MT
MFM
SK
1
0
0
0
0
0
0
1
HOS
1
DS1
0
Sector 10 information prior
to Command execu1ion
C
H
R
N
EOT
GPL
DTL
No data transfer takes
place
Execution
Result
Command Codes
DSO
R
R
R
R
R
R
R
Status information after
Command execution
STO
ST1
ST2
C
H
R
N
Sector ID information after
Command execution
VERSION
Command
Result
W
o·
R
1
0
a
0
0
1
1
0
a
7-47
0
0
0
a
0
0
Command Code
Enhanced Controller
inter
82077
Table 5-1. 820nCommand Set (Continued)
Phase
DATA BUS
R/W
07
06
05
04
0
0
MFM
0
0
0
0
0
03
Remarks
02
01
Do
1
1
0
HDS
0
DSl
DSO
FORMAT TRACK
Command
Execution
For Each
Sector
Repeat:
W
W
W
W
W
W
1
Bytes/Sector
Sectors/Cylinder
Gap3
Filler Byte
N
SC
GPL
D
W
W
W
W
Command Codes
C
H
R
N
Input Sector
Parameters
82077 formats an entire
cylinder
Result
R
R
R
R
R
R
R
Command
W
W
Status information after
Command execution
STO
STl
ST2
Undefined
Undefined
Undefined
Undefined
RECALIBRATE
0
0
0
0
0
0
0
0
0
0
1
1
1
0
DSl
DSO
Command Codes
Head retracted to Track 0
Interrupt
Execution
SENSE INTERRUPT STATUS
Command
W
Result
R
R
Command
W
W
W
0
0
0
1
0
0
0
0
STO
PCN
Command Codes
Status information at the
end of each seek operation
SPECIFY
0
0
0
0
0
1
0
SRT
1
Command Codes
HUT
HLT
ND
SENSE DRIVE STATUS
Command
W
W
Result
R
Command
W
W
W
0
0
0
0
0
0
0
0
0
0
1
HDS
0
DSl
0
DSO
Command Codes
Status information about
FDD
ST3
SEEK
0
0
0
0
0
0
0
0
1
1
1
1
0
HDS
DSl
DSO
Command Codes
NCN
Head is positioned over
proper Cylinder on Diskette
Execution
CONFIGURE
Command
W
W
W
W
0
0
0
0
0
EIS
0
0
EFIFO
W
W
W
1
DIR
0
0
0
1
0
0
0
POLL
PRETRK
0
0
1
1
0
0
FIFOTHR _ _ _._
RELATIVE SEEK
Command
0
0
0
1
1
1
1
0
HDS
DSl
DSO
RCN
7-48
Configure Information
82077
Table 5-1. 82077 Command Set (Continued)
Phase
DATA BUS
R/W
07
Os
Os
04
0
0
0
0
Remarks
0, .
O2
03
Do
DUMPREG
Command
Execution
Result
W
R
R
R
R
R
R
R
R
R
'R
1
1
1
"'Note
Registers placed in FIFO
0
PCN-Drive 0
PCN-Drive 1
PCN-Drive 2
PCN-Drive 3
SRT
HUT
0
EIS
EFIFO
0
0
MFM
0
0
HLT
SC/EOT
Undefined
POLL
PRETRK
ND
FIFOTHR
READ 10
Command
W
W
0
0
0
1
0
0
HDS
0
DSO
1
DS1
Commands
The firsl correct 10
information on the Cylinder
is stored in Data Register
Execution
Result
Status information after
Command execution
STO
ST1
ST2
C
H
R
N
R
R
R
R
R
R
R
Disk status after the
Command has completed,
PERPENDICULAR MODE
Command
W
0
0
Command
W
Invalid Codes
Result
R
STO
0
0
0
0
1
0
0
0
0
0
Command Codes
1
0
WGATEGAP
INVALID
Invalid Command Codes
(NoOp - 82077 goes into
Standby State)
STO= 80H
SC is returned If the last command that was Issued was the FORMAT command. EOT IS returned If the last command was a
READ or WRITE.
NOTE:
These bits are used internally only. They are not reflected in the Drive Select pins. It is the users responsibility to maintain
correspondence between these bits and the Drive Select pins (DOR).
Symbol
PARAMETER ABBREVIATIONS
Description
DSO, DS1 Disk Drive Select.
Symbol
Description
C
Cylinder address. The currently selected
cylinder address, 0 to 255.
D
Data pattern. The pattern to be written in
each sector data field during formatting.
DIR
Direction control. If this bit is 0, then the
head will step out from the spindle during
a relative seek. If set to a 1, the head will
step in toward the spindle.
7-49
DS1
DSO
0
0
1
1
0
1
0
1
drive 0
drive 1
drive 2
drive 3
82077
Symbol
Description
Symbol
DTL
Special sector size. By setting N to zero
(00), DTL may be used to control the
number of bytes transferred in disk
read/write commands. The sector size (N
, = 0) is set to 128. If the actual sector (on
the diskette) is larger than DTL, the remainder of the actual sector is read but is
not passed to the host during read commands; during write commands, the remainder of the actual sector is written
with all zero bytes. The CRC check code
is calculated with the actual sector. When
N is not zero, DTL has no meaning and
should be set to FF HEX.
EFIFO
Enable FIFO. When this bit is 0, the FIFO
is enabled. A "1" puts the 82077 in the
8272A compatible mode where the FIFO
is disabled.
EIS
Enable implied seek. When set, a seek
. operation will be performed before executing any read or write command that requires the C parameter in the command
phase. A "0" disables the implied seek.
EOT
End of track. The final sector number of
the current track.
GPL
Gap length. The gap 3 size. (Gap 3 is the
space between sectors excluding the
VCO synchronization field).
H/HDS
Head address. Selected head: 0 or 1
(disk side 0 or 1) as encoded in the sector
ID field.
HLT
Head load time. The time interval that
82077 waits after loading the head and
before initiating a read or write operation.
Refer to the SPECIFY command for actual delays.
HUT
Head unload time. The time interval from
the end of the execution phase (of a read
or write command) until the head is unloaded. Refer to the SPECIFY command
for actual delays.
MFM
MFM/FM mode selector. A one selects
the. double density (MFM) mode. A zero
selects single density (FM) mode.
MT
Multi-track selector: When set, this flag
selects the multi-track operating mode. In
this mode, the 82077 treats a complete
cylinder, under head 0 and 1, as a single
track. The 82077 operates as if this expanded track started at the first sector
under head 0 and ended at the last sector under head 1. With this flag set, a mUltitrack read or write operation will automatically continue to the first sector under head 1 when the 82077 finishes operating on the last sector under head o.
N
Description
Sector size code. This specifies the number of bytes in a sector. If this parameter
is "00", then the sector size is 128 bytes.
The number of bytes transferred is determined by the DTL parameter. Otherwise
the sector size is (2 raised to the "N'th"
power) times 128. All values up to "07"
hex are allowable. "07"h would equal a
sector size of 16k. It is the users responsibility to not select combinations that are
not possible with the drive.
N
Sector Size
00
01
02
03
128 bytes
256 bytes
512 bytes
1024 bytes
..
07
NCN
ND
PCN
POLL
. ..
16 Kbytes
New cylinder number. The desired cylinder number.
Non-DMA mode flag. When set to 1, indicates that the 82077 is to operate in the
non-DMA mode. In this mode, the host is
interrupted for each data transfer. When
set to 0, the 82077 operates in DMA
mode, interfacing to a DMA controller by
means of the DRO and DACK # signals.
Present cylinder number. The current position of the head at the completion of
SENSE INTERRUPT STATUS command.
Polling disable. When set, the internal
polling routine is disabled. When clear,
polling is enabled.
PRETRK Precompensation start track number.
Programmable from track 00 to FFH.
R
Sector address. The'sector number to be
read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be read or written.
RCN
Relative cylinder number. Relative cylinder offset from present cylinder as used
by the RELATIVE SEEK command.
SC
Number of sectors per track. The number
of sectors per track to be initialized by the
FORMAT command.
SK
7-50
Skip flag. When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution
of READ DATA. If READ DELETED is executed, only sectors with a deleted address mark will be accessed. When set to
"0", the sector is read or written the
same as the read and write commands.
82077
Symbol
SRT
STO
ST1
ST2
ST3
the 82077 transfers the specified number of bytes to
the host. For reads, it continues to read the entire
128 byte sector and checks for CRC errors. For
writes it completes the 128 byte sector by filling in
zeroes. If N is not set to 00 Hex, DTL should be set
to FF Hex, and has no impact on the number of
bytes transferred.
Description
Step rate interval. The time interval between step pulses issued by the 82077.
Programmable from 0.5 to 8 milliseconds,
in increments of 0.5 ms at the 1 Mbit data
rate. Refer to the SPECIFY command for
actual delays.
Status register 0-3. Registers within the
82077 that store status information after
a command has been executed. This
status information is available to the host
during the result phase after command
execution.
Table 5-2. Sector Sizes
N
Sector Size
00
01
02
03
128 bytes
256 bytes
512 bytes
1024 bytes
. ..
..
5.1 Data Transfer Commands
07
All of the READ DATA, WRITE DATA and VERIFY
type commands use the same parameter bytes and
return the same results information. The only difference being the coding of bits 0-4 in the first byte.
16 Kbytes
The amount of data which can be handled with a
single command to the 82077 depends upon MT
(multi-track) and N (Number of bytes/sector).
An implied seek will be executed if the feature was
enabled by the CONFIGURE command. This seek is
completely transparent to the user. The Drive Busy
bit for the drive will go active in the Main Status Register during the seek portion of the command. If the
seek portion fails, it will be reflected in the results
status normally returned for a READ/WRITE DATA
command. Status Register 0 (STO) would contain
the error code and C would contain the cylinder on
which the seek failed.
Table 5-3. Effects of MT and N Bits
MT
N
0
1
0
1
0
1
1
1
2
2
3
3
Max. Transfer
. Capacity
256 x 26 =
256 x 52 =
512X15=
512 x 30 =
1024 x 8=
1024 x 16 =
6,656
13,312
7,680
15,360
8,192
16,384
Final Sector
Read from Disk
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
5.1.1 READ DATA
A set of nine (9) bytes is required to place the 82077
into the Read Data Mode. After the READ DATA
command has been issued, the 82077 loads the
head (if it is in the unloaded state), waits the specified head settling time (defined in the SPECIFY command), and begins reading 10 Address Marks and 10
fields. When the sector address read off the diskette
matches with the sector address specified in the
command, the 82077 reads the sector's data field
and transfers the data to the FIFO.
The Multi-Track function (MT) allows the 82077 to
read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at
Sector 1, Side 0 and completing at the last sector of
the same track at Side 1.
After completion of the read operation from the current sector, the sector address is incremented by
one, and the data from the next logical sector is read
and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon
receipt of TC, or an implied TC (FIFO overrun/underrun), the 82077 stops sending data, but will continue to read data from the current sector, check the
CRC bytes, and at the end of the sector terminate
the READ DATA Command.
At the completion of the READ DATA Command,
the head is not unloaded until after the Head Unload
Time Interval (specified in the SPECIFY command)
has elapsed. If the host issues another command
before the head unloads then the head settling time
may be saved between subsequent reads.
If the host terminates a read or write operation in the
82077, then the 10 information in the result phase is
dependent upon the state of the MT bit and EOT
byte. Refer to Table 5-6.
If the 82077 detects a pulse on the lOX pin twice
without finding the specified sector (meaning that
the diskette's index hole passes through index detect logic, in the drive twice), the 82077 sets the IC
code in Status Register 0 to "01" (Abnormal termination), and sets the NO bit in Status Register 1 to
"1" indicating a sector not found, and terminates the
READ DATA Command.
N determines the number of bytes per sector (see
Table 5-2 below). If N is set to zero, the sector size
is set to 128. The DTL value determines the number
of bytes to be transferred. If DTL is less than 128,
7-51
82077
After reading the 10 and Data Fields in each sector,
the 82077 checks the CRC bytes. If a CRC error
occurs in the ID or data field, the 82077 sets the IC
code in Status Register 0 to "01" (Abnormal termination), sets the DE bit flag in Status Register 1 to
"1", sets the DO bit in Status Register 2 to "1" if
CRC is incorrect in the 10 field, and terminates the
READ DATA Command.
Table 5-5 describes the affect of the SK bit on the
READ DELETED DATA command execution and results.
Table 5·5. Skip Bit vs
'READ DELETED DATA Command
SKBit
Value
Table 5-4 below describes the affect of the SK bit on
the READ DATA command execution and·results.
Results
Data Address
Mark Type
Encountered
Sector
Read?
CMBitof
ST2Set?
Description
of Results
Address Not
Incremented.
Next Sector
Not
Searched
For.
Normal
Termination,
Normal
Termination
Sector Not
Read
("Skipped").
Normal
Termination,
0
Normal Data
Yes
Yes
0
Deleted Data
Yes
No
1
Normal Data
·No
Yes
1
Deleted Data
Yes
No
Table 5·4. Skip Bit vs READ DATA Command
SKBit
Value
Data Address
Results
Mark Type
eM Bit
Description of
Sector
Encountered
Results
Read? of ST2 Set?
0
Normal Data
Yes
No
0
Deleted Data
Yes
yes
1
Normal Data
Yes
No,
1
Deleted Data
No
Yes
Normal
Termination.
Address Not
Incremented.
Next Sector
Not Searched
For.
Normal
Termination.
Normal
Termination
Sector Not
Read
("Skipped").
Except where noted in Table 5-5 above, the C or R
value of the sector address is automatically incremented (See Table 5-6).
5.1.3 READ TRACK
This command is similar to the READ DATA command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the lOX pin, the
82077 starts to read all data fields on the track as
continuous blocks of data without regard to logical
sector numbers. If the 82077 finds an error in the 10
or DATA CRC check bytes, it continues to read data
from the track and sets the appropriate error bits at
the end of the command. The 82077 compares the
Except where noted in Table 5-4, the C or R value of
the sector address is automatically incremented
(see Table 5-6)~
5.1.2 READ DELETED DATA
This command is the same as the READ DATA command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data
Field. _ ,.
.
Table 5·6. Result Phase Table
MT
Head
0
0
1
0
1
1
10 Information at Result Phase
Final Sector Transferred
to Host
C
H
R
N
Less than EOT
NC
NC
R+1
NC
Equal to EOT
C+1
NC
01
NC
Less than EOT
NC
NC
R+1
NC
Equal to.EOT
C+1
NC
01
NC
Less than EOT
NC
NC
R+1
NC
Equal to EOT
NC
LSB
01
NC
Less than EOT
NC
NC
R+1
NC
Equal to EOT
C+1
LSB
01
NC
NC: no change, the same value as the one at the beginning of command execution.
LSB: least significant bit, the LSB of H is complemented.
7-52
inter
82077
10 information read from each sector with the specified value in the command, and sets the NO flag of
Status Register 1 to a "1" if there is no comparison.
Multi-track or skip operations are not allowed with
this command. The SK bit should always be set to
5.1.5 WRITE DELETED DATA
This command is almost the same as the WRITE
OAT A command except that a Deleted Data Address Mark is written at the beginning of the Data
Field instead of the normal Data Address Mark. This
command is typically used to mark a bad sector containing an error on the floppy disk.
"0".
This command terminates when the EOT specified
number of sectors have been read. If the 82077
does not find an 10 Address Mark on the diskette
after the second occurrence of a pulse on the lOX
pin, then it sets the IC code in Status Register 0 to
"01" (Abnormal termination), sets the MA bit in
Status Register 1 to "1", and terminates the command.
5.1.6 VERIFY
The VERIFY command is used to verify the data
stored on a disk. This command acts exactly like a
READ DATA command except that no data is transferred to the host. Data is read from the disk, CRC
computed and checked against the previously
stored value.
5.1.4 WRITE DATA
After the WRITE DATA command has been issued,
the 82077 loads the head (if it is in the unloaded
state), waits the specified head load time if unloaded
(defined in the SPECIFY command), and begins
reading 10 Fields. When the sector address read
from the diskette matches the sector address specified in the command, the 82077 reads the data from
the host via the FIFO, and writes it to the sector's
data field.
The EOT value should be set to the final sector to be
checked. If EOT is greater than the number of sectors on a disk, the command will stop due to an error
and no useful CRC information will be obtained.
5.1.7 FORMAT TRACK
The FORMAT command allows an entire track to be
formatted. After a pulse from the lOX pin is detected,
the 82077 starts writing data on the disk including
Gaps, Address Marks, 10 Fields and Data Fields, per
the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written
to the gap and data field are controlled by the values
programmed into N, SC, GPL, and 0 which are specified by the host during the command phase. The
data field of the sector is filled with the data byte
specified by D. The 10 Field for each sector is supplied by the host; that is, four data bytes per sector
are needed by the 82077 for C, H, R, and N (cylinder, head, sector number and sector size respectively).
After writing data into the current sector, the 82077
computes the CRC value and writes it into the CRC
field at the end of the sector transfer. The Sector
Number stored in "R" is incremented by one, and
the 82077 continues writing to the next data field.
The 82077 continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a
FIFO over/under run occurs while a data field is being written, then the remainder of the data field is
filled with zeros.
The 82077 reads the 10 field of each sector and
checks the CRC bytes. If it detects a CRC error in
one of the 10 Fields, it sets the IC code in Status
Register 0 to "01" (Abnormal termination), sets the
DE bit of Status Register 1 to "1 ", and terminates
the WRITE DATA command.
After formatting each sector, the host must send
new values for C, H, Rand N to the 82077 for the
next sector on the track. The R value (sector number) is the only value that must be changed by the
host after each sector is formatted. This allows the
disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the 82077
encounters a pulse on the lOX pin again and it terminates the command.
The WRITE DATA command operates in much the
same manner as the READ DATA command. The
following items are the same. Please refer to the
READ DATA Command for details:
• Transfer Capacity
• EN (End of Cylinder) bit
Table 5-7 contains typical values for gap fields which
are dependent upon the size of the sector and the
number of sectors on each track. Actual values can
vary due to drive electronics.
• NO (No Data) bit
• Head Load, Unload Time Interval
• 10 information when the host terminates the command.• Definition of DTL when N
not = o.
=
0 and when N does
7-53
inter
82077
Table 5-7. Typical Values for Formatting
Sector Size
N
SC
GPL1
GPL2
128
128
512
1024
2048
4096
.. .
256
256
512'
1024
2048
4096
00
00
02
03
04
05
...
12
10
08
04
02
01
07
10
18
46
C8
C8
09
19
30
87
FF
FF
...
01
01
02
03
04
05
. ..
12
10
09
04
02
01
OA
20
2A
80
C8
C8
OC
32
50
FO
FF
FF
128
256
512
256
512"
1024
0
1
2
1
2
3
OF
09
05
OF
09
05
07
OF
18
OE
18
35
18
2A
3A
36
54
74
FM
5.25" Drives
MFM
FM
3.5" Drives
MFM
GPL 1 = suggested GPL values in read and write commands to avoid splice point between data field and ID field of contiguous sections.
GPL2 = suggested GPL value in FORMAT TRACK command.
'PC-AT values (typical)
''PSI2™ values (typical)
NOTE:
All values except Sector Size are in Hex.
5.1.7.1 Format Fields
GAP4a
80x
4E
GAP4a
40x
FF
SYNC
12x
00
lAM
~
C2
GAP1
SOx
4E
SYNC
12x
00
IDAM
~
A1
C
Y
L
H
D
S
E
C
N
0
C
R
C
GAP2
22x
4E
SYNC
12x
00
DATA AM
3x
A1
I FBF8
C
DATA
R GAP3 GAP4b
C
Figure 5-1. System 34 Format Double Density
lAM
SYNC
GAP 1
f--6x
26x
FC
00
FF
SYNC
6x
00
-
IDAM
FE
C
Y
L
H
D
S
E
C
N
0
C
R
C
GAP2
11x
FF
SYNC
6x
00
DATA AM
C
DATA
FBor F8
R GAP3
GAP4b
C
Figure 5-2. System 3740 Format Single Density
GAP4a
80x
4E
SYNC
12x
00
lAM
~
C2
GAP1
SOx
4E
SYNC
12x
00
IDAM
~
A1
C
Y
L
H S
E
D
C
N
0
C
R
C
GAP2
41x
4E
SYNC
12x
00
DATA AM
3x
A1
I FBF8
Figure 5-3. Toshiba Perpendicular Format
7-54
C
DATA
R GAP3 GAP4b
C
82077
The RECALIBRATE command does not have a result phase. SENSE INTERRUPT STATUS command
must be issued after the RECALIBRATE command
to effectively terminate it and to provide verification
of the head position (PCN). During the command
phase of the recalibrate operation, the 82077 is in
the BUSY state, but during the execution phase it is
in a NON BUSY state. At this time another RECALIBRATE command may be issued, and in this manner, parallel RECALIBRATE operations may be
done on up to 4 drives at once.
5.2 Control Commands
Control commands differ from the other commands
in that no data transfer takes place. Three commands generate an interrupt when complete; READ
ID, RECALIBRATE and SEEK. The other control
commands do not generate an interrupt.
5.2.1 READ ID
The READ ID command is used to find the present
position of the recording heads. The 82077 stores
the values from the first ID Field it is able to read into
its registers. If the 82077 does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, it then sets the IC
code in Status Register 0 to "01" (Abnormal termination), sets the MA bit in Status Register 1 to "1 ",
and terminates the command.
Upon power up, the software must issue a RECALIBRATE command to properly initialize all drives and
the controller.
5.2.3 SEEK
The read/write head within the drive is moved from
track to track under the control of the SEEK Command. The 82077 compares the PCN which is the
current head position with the NCN and performs
the following operation if there is a difference:
-PCN < NCN: Direction signal to drive set to "1"
(step in), and issues step pulses.
The following commands will generate an interrupt
upon completion. They do not return any result
bytes. It is highly recommended that control commands be followed by the SENSE INTERRUPT
STATUS command. Otherwise, valuable interrupt
status information will be lost.
-PCN > NCN: Direction signal to drive set to "0"
(step out), and issues step pulses.
5.2.2 RECALIBRATE
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECIFY
command. After each step pulse is issued, NCN is
compared against PCN, and when NCN = PCN,
then the SE bit in Status Register 0 is set to "1 ", and
the command is terminated.
This command causes the read/write head within
the 82077 to retract to the track 0 position. The
82077 clears the contents of the PCN counter, and
checks the status of the TRKO pin from the FDD. As
long as the TRKO pin is low, the DIR pin remains 0
and step pulses are issued. When the TRKO pin
goes high, the SE bit in Status Register 0 is set to
"1 ", and the command is terminated. If the TRKO pin
is still low after 255 step pulses have been issued,
the 82077 sets the SE and the EC bits of Status
Register 0 to "1", and terminates the command.
Disks capable of handling more than 256 tracks per
side may require more than one RECALIBRATE
command to return the head back to physical Track
O.
During the command phase of the seek or recalibrate operation, the 82077 is in the BUSY state, but
during the execution phase it is in the NON BUSY
state. At this time another SEEK or RECALIBRATE
command may be issued, and in this manner, parallel seek operations may be done on up to 4 drives at
once.
7-55
82077
Note that if implied seek is not enabled, the read and
write commands should be preceded by:
1) SEEK command;
Step to the proper track
2) SENSE INTERRUPT Terminate the Seek
STATUS command; command
3) READ ID.
Verify head is on
proper track
4) Issue READ/WRITE
command.
SE
0
1
1
Table 5-8 Interrupt Identification
Interrupt Due To
Polling
Normal Termination of SEEK or
RECALIBRATE command
Abnormal Termination of SEEK or
01
RECALIBRATE command
IC
11
00
The SEEK, RELATIVE SEEK and the RECALIBRATE commands have no result phase. SENSE
INTERRUPT STATUS command must be issued immediately after these commands to terminate them
and to provide .verification of the head position
(PCN). The H (Head Address) bit in STO will always
return a "0". If a SENSE INTERRUPT STATUS is
not issued, the drive, will continue to be BUSY and
may effect the operation of the next command.
The SEEK command does not have a result phase.
Therefore, it is highly recommended that the SENSE
INTERRUPT STATUS Command be issued after the
SEEK command to terminate it and to provide verification of the head position (PCN). The H bit (Head
Address) in STO will always return a "0". When exiting POWER DOWN mode, the 82077 clears the PCN
value and the status information to zero. Prior to issuing the POWER DOWN command, it is highly recommended that the user service all pending interrupts through the SENSE INTERRUPT STATUS
command.
5.2.5 SENSE DRIVE STATUS
SENSE DRIVE STATUS obtains drive status information. It has no execution phase and goes directly
to the result phase from the command phase.
STATUS REGISTER 3 contains the drive status information.
5.2.4 SENSE INTERRUPT STATUS
An interrupt signal on INT pin is generated by the
82077 for one of the following reasons:
1. Upon entering the Result Phase of:
a. READ DATA Command
b. READ TRACK Commanq
c. READ ID Command
d. READ DELETED DATA Command
e. WRITE DATA Command
f. FORMAT TRACK Command
g. WRITE DELETED DATA Command
2. End of SEEK,RELATIVE SEEK or RECALIBRATE Command
3. 82077 requires a data transfer during the execution phase in the non-DMA Mode
5.2.6 SPECIFY
The SPECIFY command sets the initial values for
each of the three internal timers. The HUT (Head
Unload Time) defines the l time from the end of .the
execution phase of one of the read/write commands
to the head unload state. The SRT (Step Rate Time)
defines the time interval between adjacent step
pulses. Note that the spaCing between the first and
second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines
the time between the Head Load signal goes high
and the read, write operation starts. The values
change with the data rate speed selection and are
documented in Table 5-9. The values are the same
for MFM and FM.
The SENSE INTERRUPT STATUS command resets
the interrupt signal and via the IC code and SE bit of
Status Register 0, identifies the cause of the interrupt.
7-56
82077
{
EFIFO-A "1" puts the FIFO into the 8272A compatible mode where the FIFO is disabled. This
means data transfers are asked for on a byte by byte
basis. Defaults to "1", FIFO disabled. The threshold
defaults to one.
Table 5-9. Drive Control Delays (ms)
HUT
SRT
1M 500K 300K 2S0K 1M SOOK 300K 2S0K
0 128 256
1
8
16
"
..
E 112
F 120
426
26.7
..
..
224
240
373
400
512 8.0
32 7.5
16
15
26.7
25
..
..
..
448 1.0
480 0.5
2
1
3.33
1.67
..
32
30
..
4
2
POLL-Disable polling of the drives. Defaults to "0",
polling enabled. When enabled, a single interrupt is
generated after a RESET. No polling is performed
while the drive head is loaded and the head unload
delay has not expired.
FIFOTHR-The FIFO threshold in the execution
phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A
"00" selects one byte "OF" selects 16 bytes.
HLT
1M
SOOK
300K
2S0K
00
01
02
128
1
2
256
2
4
512
4
8
7F
7F
126
127
252
254
426
3.3
6.7
..
420
423
..
..
..
PRETRK-Pre-compensation start track number.
Programmable from track 0 to 255. Defaults to track
O. A "00" selects track 0, "FF" selects 255 .
504
508
5.2.8 VERSION
The choice of DMA or NON-DMA operations is
made by the ND bit. When this bit is "1", the NONDMA mode is selected, and when ND is "0", the
DMA mode is selected. In DMA mode, data transfers
are signalled by the DRO pin. Non·DMA mode uses
the ROM bit and the INT pin to signal data transfers.
The VERSION command checks to see if the controller is an enhanced type or the older type (8272AI
765A). A value of 90 H is returned immediately after
the command byte and no interrupts are generated.
S.2.9 RELATIVE SEEK
5.2.7 CONFIGURE
The command is coded the same as for SEEK, except for the MSB of the first byte and the DIR bit.
DIR
Head Step Direction Control.
Issued to select the special features of the 82077. A
CONFIGURE command need not be issued if the
default values of the 82077 meet the system requirements.
.
CONFIGURE DEFAULT VALUES:
RCN
EIS
-No Implied Seeks
EFIFO
-FIFO Disabled
POLL
-Polling Enabled
FIFOTHR -FIFO Threshold Set to 1 Byte
PRETRK -Pre-Compensation Set to Track 0
DIR
Action
0
1
Step Head Out
Step Head In
Relative Cylinder Number that determines
how many tracks to step the head in or out
from the current track number.
The RELATIVE SEEK command differs from the
SEEK command in that it steps the head the absolute number of tracks specified iri the command instead of making a comparison against an internal
register. The SEEK command is good for drives that
support a maximum of 256 tracks. RELATIVE
SEEKs cannot be overlapped with other RELATIVE
SEEKs. Only one RELATIVE SEEK can be active at
a time. RELATIVE SEEKs may be overlapped with
SEEKs and RECALIBRATEs. Bit 4 of Status Register 0 (EC) will be set if RELATIVE SEEK attempts to
step outward beyond Track O.
EIS-Enable implied seek. When set to "1", the
82077 will perform a SEEK operation before executing a read or write command. Defaults to no implied
seek.
7-57
82077
As an· example, assume' that a floppy drive has 300
useable tracks and that the host needs to read track
300 and the head is on any track (0-255). If a SEEK
command was issued,the head would stop at track
255. If a RELATIVE SEEK command was issued, the
82077 would move the head the specified number of
tracks, regardless of, the internal cylinder position
register (but would increment the register). If the
head had been on track 40 (D), the maximum track
that the 82077 could position the head on using
RELATIVE SEEK, would be 296 (D), the initial track,
+ 256 (D). The maximum count that the head can be
moved with a single RELATIVE SEEK command is
256 (D).
To. return to the standard floppy range (0-255) of
tracks, a RELATIVE SEEK would be issued to cross
the track 255 boundary.
'
A RELATIVE SEEK can be used instead of the normal SEEK but the host is required to calculate the
difference between ,the current head location and
the new (target) head location. This may require the
host to issue a READ ID command to ensure that
the head is physically on the track that software assumes it to be. Different 82077 commands will return
different cylinder results which may be difficult to
keep track of with software without the READ ID
command.
The internal register, PCN, would' overflow as the
cylinder number crossed track 255 and would contain 40 (D). The resulting PCN value is thus (NCN +
PCN) mod 256. Functionally, the 82077 starts counting from 0 again as the track number goes above
255(D). It is the users responsibility to compensate
82077 functions (precompensation track number)
when accessing tracks greater than 255. The 82077
does not keep track that it is working in an "extended track area'~ (greater than 255). Any command issued would use the current PCN value except for the
RECAUBRATE command which only looks for the
TRACKO signal. RECAUBRATE would return an error if the head was farther than 255 due to its limitation of issuing a maximum 256 step pulses. The user
simply needs to issue a second RECAUBRATE
command. The SEEK command and implied seeks
will function correctly within the 44 (D) track (299255) area of the "extended track area". It is the users responsibility not to issue a new track position
that would exceed the maximum track that is present in the extended area.
5.2.10 DUMPREG
The DUMPREG command is designed to support
system run-time. diagnostics and application soft~
ware development and debug.
5.2.11 PERPENDICULAR MODE COMMAND
The PERPENDICuLAR MODE command should be
issued prior to executing READ/WRITE/FORMAT
commands that access,a disk drive with perpendicuc
lar recording capability. With, t~is command, the
length of the Gap2 field and VCO enable timing can
be altered to accommodate the unique requirements
of these drives. Table 5-10 describes the effects of
the WGATE and GAP bits for the PERPENDICULAR
MODE command. Upon a reset, the 82077 will default to the conventional mode (WGATE = 0, GAP
= 0).
Table 5-10 Effects of WGATE and GAP Bits
WGATE GAP
MODE
Gap2VCO
VCOLow
Length of
Portion of Gap2
Low Time for
Time after Gap2Format Written by Write
Data Operation Read Operations
Index Pulse
Field
0
0
0
Conventional Mode
33 Bytes
22 Bytes
o Bytes
'24 Bytes
1
Reserved
(Conventional)
33 Bytes
22 Bytes
o Bytes
24 Bytes
1
,0
Perpendicular Mode
(500 Kbps Data Rate)
33 Bytes
22 Bytes
19 Bytes
24 Bytes
1
1
Perpendicular Mode.
,(1 Mbps Data Rate)
18'Bytes
41 Bytes
38 Bytes
43 Bytes
7-58
inter
82077
(WGATE = 1, GAP = 1), VCOEN goes active after
43 bytes to accommodate the increased Gap2 field
size. For both cases, an approximate 2 byte cushion
is maintained from the beginning of the sync field for
the purposes of avoiding write splices in the presence of motor speed variation.
Selection of the 500 Kbps and 1 Mbps perpendicular
modes is independent of the actual data rate selected in the Data rate Select Register. The user must
ensure that the two data rates remain consistent.
The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this
head, a pre-erase head precedes the normal read/
write head by a distance of 200 micrometers. This
works out to about 38 bytes at a 1 Mbps recording
. density. Whenever the write head is enabled by the
Write Gate signal the pre-erase head is also activated at the same time. Thus, when the write head is
initially turned on, flux transitions recorded on the
media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet
been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown in
Figure 5-3 illustrates the change in the Gap2 field
size for the perpendicular format.
For the WRITE DATA case, the 82077 activates
Write Gate at the beginning of the sync field under
the conventional mode. The controller then writes a
new sync field, data address mark, data field, and
CRC as shown in Figure 5-1. With the pre-erase
head of the perpendicular drive, the write head must
be activated in the Gap2 field to insure a proper
write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1),38 bytes will
be written in the Gap2 space. Since the bit density is
proportional to the data rate, 19 bytes will be written
in the Gap2 field for the 500 Kbps perpendicular
mode (WGATE = 1, GAP = 0).
It should be noted that none of the alterations in
Gap2 size, VCO timing, or Write Gate timing affect
normal program flow. The information provided here
is just for background purposes and is not needed
for normal operation. Once the PERPENDICULAR
MODE command is invoked, 82077 software behavior from the user standpoint is unchanged.
On the read back by the 82077, the controller must
begin synchronization at the beginning of the Sync
field. For the conventional mode, the internal PLL
VCO is enabled (VCOEN) approximately 24 bytes
from the start of the Gap2 field. But when the controller operates in the 1 Mbps perpendicular mode
6.0 STATUS REGISTER ENCODING
The contents of these registers are available only through a command sequence.
6.1 Status Register 0
Bit
No.
Symbol
7,6
IC
Interrupt
Code
OO-Normal termination of command. The specified command
was properly executed and completed without error.
01-Abnormal termination of command. Command execution
was started, but was not successfully completed.
10-lnvalid command. The requested command could not be
executed.
11-Abnormal termination caused by Polling.
5
SE
Seek End
The 82077 completed a SEEK or RECALIBRATE command,
or a READ or WRITE with implied seek command.
4
EC
Equipment
Check
The TRKO pin failed to become a "1" after:
1. 256 step pulses in the RECALIBRATE command.
2. The RELATIVE SEEK command causes the 82077 to step
outward beyond Track o.
3
-
-
Unused. This bit is always "0".
2
H
Head Address
The current head address.
1,0
DS1,0
Drive Select
The current selected drive.
Name
Description
7-59
inter
82077
6.2 Status Register 1
Bit
No.
Symbol
7
EN
6
-
5
DE
Data Error
The 82077 detected a CRC error in either the 10 field or the
data field of a sector.
4
OR
Overrun/
Underrun
Becomes set if the 82077 does not receive CPU or DMA
service within the required time interval, resulting in data
overrun or underrun.
3
-
2
NO
1
NW
Not Writable
WP pin became a "1" while the 82077 is executing a WRITE
DATA, WRITE DELETED OATA, or FORMAT TRACK
command.
0
MA
Missing
Address Mark
Anyone of the following:
1. The 82077 did not detect an 10 address mark at the
specified track after encountering the index pulse from the
lOX pin twice.
2. The 82077 cannot detect a data address mark or a deleted
data address mark on the specified track.
Name
End of
Cylinder
-
No Data
Description
The 82077 tried to access a sector beyond the final sector of
the track (2550). Will be set if TC is not issued after Read or
Write Data Command.
Unused. This bit is always "0".
Unused. This bit is always "0".
Anyone of the following:
1. READ DATA, READ DELETED DATA command, the
82077 did not find the specified sector.
2. READ 10 command, the 82077 cannot read the 10 field
without an error.
3. READ TRACK command, the 82077 cannot find the proper
sector sequence.
7-60
intJ
82077
6.3 Status Register 2
Bit
No.
Symbol
7
-
-
6
CM
Control Mark
Anyone of the following:
1. READ DATA command, the 82077 encounters a deleted
data address mark.
2. READ DELETED DATA command, the 82077 encounters
a data address mark.
5
DD
Data Error
in Data
Field.
The 82077 detected a CRC error in the data field.
4
WC
Wrong
Cylinder
The track address from the sector ID field is different from
the track address maintained inside the 82077.
3
2
-
1
BC
Bad Cylinder
The track address from the sector ID field is different from
the track address maintained inside the 82077 and is equal
to FF hex which indicates a bad track with a hard error
according to the IBM soft-sectored format.
0
MD
Missing Data
Address Mark
The 82077 cannot detect a data address mark or a deleted
data address mark.
Name
-
Description
Unused. This bit is always "0".
Unused. This bit is always "0".
Unused. This bit is always "0".
6.4 Status Register 3
Bit
No.
Symbol
Description
Name
7
-
6
WP
5
-
4
TO
3
-
-
2
HD
Head Address
Indicates the status of the HDSEL pin.
1,0
DS1,0
Drive Select
Indicates the status of the DS1, DSO pins.
Write
Protected
TRACK 0
Unused. This bit is always "0".
Indicates the status of the WP pin.
Unused. This bit is always "1 ".
Indicates the status of the TRKO pin.
Unused. This bit is always "1 ".
default to a PS/2 or PC/AT compatible operating
mode depending on how IDENT is strapped.
7.0 COMPATIBILITY
The 82077 was designed with software compatibility
in mi'nd. It is a fully backwards compatible solution
with the older generation 8272A and NEC765A1B
disk controllers. The 82077 also implements onboard registers for compatibility with the Personal
System/2 as well as PC/AT and PC/XT floppy disk
controller subsystems. Upon a hardware reset of the
82077, all registers, functions and enhancements
7.1 Register Set Compatibility
The register set contained within the 82077 is a culmination of hardware registers based on the architectural growth of the IBM personal computer line.
Table 7-1 indicates the registers required for compatibility based on the type of computer.
7-61
inter
82077
If the DMAGATE # bit is written to a "0" in the Digital Output Register (DOR), DRO and INT will tristate.
If DMAGATE# is written to a "1", then DRO and
INT will be driven appropriately by the· 82077.
Table 7-1. 82077 Register Support
82077 Register 8272A 82072 PC/XT PC/AT PS/2
SRA
X
SRB
X
DOR
MSR
X
X
X
X
X
·X
TC is an active high inpuf signal that is internally
qualified by DACK# being active low.
7.3 Compatibility with the FIFO
X
DSR
Data (FIFO)
X
X
X
X
X
DIR
CCR
X·
X
X
X
X
X
X
'eCR is emulated by DSR in an 82072 PC/AT design.
7.2 PS/2 Mode vs; AT Mode
To maintain compatibility with both the PS/2 envi·
ronment and PC/AT environment the IDENT pin is
provided. If this pin is strapped to. VSS, the 82077
will operate in the PS/2 compatible mode. Strapping
IDENT to VCC places the 82077 in the PC/AT com- .
patible mode. The differences between the two
modes are described in the following sections.
7.2.1 PS/2 MODE
The polarity of the DENSEL output Signal is designed to be compatible with the 3%" disk drive
standard. Programming the CCR or DSR to the upper data rates of 500 Kbps or 1 Mbps ~iII cause
DENSEL to go active low (assuming INVERT# is
low). A comprehensive description of the. DENSEL
behavior is given in Table 2-6.
The FIFO of the 82077 is designed to be transparent
to non-FIFO disk controller software developed on
the older generation 8272A standard. Operation of
the 82077 FIFO can be broken down into two tiers of
compatibility. For first tier compatibility, the FIFO is
left in the default disabled condition upon a reset. In
this mode the FIFO operates in a byte mode and
provides completa compability with non-FIFO based
software. For second tier compatibility, the FIFO is
enabled via the CONFIGURE command. When the
FIFO is enabled, it will temporarily enter a byte mode
during the command and result phase of disk controller operation. This allows for compatible operation when interrogating the Main Status Register
(MSR) for the purpose of transferring a byte at a .
time to or from the disk controller. For normal disk
controller applications, the system designer can still
take advantage of the FIFO for time critical data
transfers during the execution phase and not create
any conflicts with non-FIFO software during the
command or result phase.
.
In some instances, use of the FIFO in any form has
conflicted with certain specialized software. An example of a compatibility conflict using the FIFO is
with software that monitors the progress of a data
transfer during the execution phase. If the software
assumed the disk controller was operating in a single byte mode and counted the number of bytes
transferred to or from the disk controller to trigger
some time dependent event on the disk media (Le.
head position over a specific data field), the same
software will not have an identical time relationship if
the FIFO is enabled. This is because the FIFO allows data to be. queued up, and then burst transferred across the host bus. To accommodate software of this type, it is recommended that the FIFO
be disabled.
The DMAGATE # bit in the Digital Output Register
(DOR) will not cause the DRO or I/\IT output signals
to tristate. This maintains consistency with the operation of the floppy disk controller subsystem in the
PS/2 architecture.
TC is an active low input signal that is internally qualified by DACK # being active .Iow.
7.2.2 PC/AT MODE
The polarity of DENSEL is designed to be compatible with the 5%" high capacity disk drive standard.
Programming the CCR or DSR to the lower data rate
of 250 Kbps or 300 Kbps will cause DENSEL to go
active low (assuming INVERT# is low).
7-62
inter
82077
7.4 Drive POlling
8.0 PROGRAMMING GUIDELINES
The 82077 supports the polling mode of the older
generation 8272A. This mode is enabled upon a reset and can be disabled via the CONFIGURE command. This mode is supported for the sole purpose
of providing backwards compatibility with software
that expects it's presence.
Programming the 82077 is identical to any other
8272A compatible disk controller with the exception
of some additional commands. For the new designer
it is useful to provide some guidelines on how to
program the 82077. A typical disk operation involves
more than issuing a command and waiting for the
results. The control of the floppy disk drive is a low
level operation that requires software intervention at
different stages. New commands and features have
been added to the 82077 to reduce the complexity
of this software interface ..
The intended purpose of drive polling dates back to
8" drives as a means to monitor any change in
status for each disk drive present in the system.
Each of the drives is selected for a period of time
and its READY signal sampled. After a delay, the
next drive is selected. Since the 82077 does not
support READY in this capacity (internally tied true),
the polling sequence is only simulated and does not
affect the drive select lines (DSO-DS3) when it is
active. If enabled, it occurs whenever the 82077 is
waiting for a command or during SEEKs and RECALIBRATEs (but not IMPLIED SEEKs). Each drive
is assumed to be not ready after a reset and a
"ready" value for each drive is saved in an internal
register as the simulated drive is polled. An interrupt
will be generated on the first pOlling loop because of
the initial '.'not ready" status. This interrupt must be
followed with a SENSE INTERRUPT STATUS command from the host to clear the interrupt condition
for each of the four logical drives.
8.1 Command and Result Phase
Handshaking
Before a command or parameter byte can be issued
to the 82077, the Main Status Register (MSR) must
be interrogated for a ready status and proper FIFO
direction. A typical floppy controller device driver
should contain a subroutine for sending command or
parameter bytes. For this discussion, the routine will
be called "SenLbyte" with the flowchart shown in
Figure 8-1.
290166-22
Figure 8-1. SenLByte Routine
.7-63
infef
82077
The routine loops until ROM is 1 and 010 is 0 indicating a ready status and FIFO direction is inward. If
this condition is true, the 82077 is ready to accept a
command or parameter byte. A timeout counter is
used to insure software response within a reasonable amount of time in case of no response by the
82077. As a note, the programmer must be careful
how the maximum delay is chosen to avoid unnecessary timeouts. For example, if a new command is
issued when the 82077 is in the middle of a pOlling
routine, the MSR will not indicate a ready status for
the next parameter byte until the polling sequence
completes the loop. This could cause a delay between the first and second bytes of up to 250 p.s
(@ 250 Kbps). If polling is disabled, this maximum
delay is 175 p.s. There should also be enough time- .
out margin to accommodate a shift of the software
to a higher speed system. A timeout value that results in satisfactory operation on a 16 MHz CPU
might fail when the software is moved to a system
with a 25 MHz CPU. A recommended solution is to
derive the timeout counter from a system hardware
counter that is fixed in frequency from CPU clock to
CPU clock.
For reading result bytes from the 82077, a similar
routine is used. Figure 8-2 illustrates the flowchart
for the routine "GeLbyte". The MSR is polled until
ROM is 1 and 010 is 1, which indicates a ready
status and outward FIFO direction. At this point, the
host can read a byte from the FIFO. As in the
Send_byte routine, a timout counter should be incorporated in case of a disk controller lock-up condition. For example, if a disk was not inserted into the
disk drive at the time of a read operation, the controller would fail to receive the index pulse and lockup since the index pulses are required for termination of the execution phase.
8.2 Initialization
Initializing the 82077 involves setting up the appropriate configuration after a reset. Parameters set by
the SPECIFY command are undefined after a reset
and will need to be reinitialized. CONFIGURE command parameters default to a known state after a
reset but will need to be reinitialized if the system
requirements are different from the default settings.
The flowchart for the recommended initialization sequence of the 82077 is shown in Figure 8-3.
290166-23
Figure 8-2. GeLByte Routine
7-64.
inter
82077
290166-24
Figure 8-3. Initialization Flowchart
7-65
inter
82077
Following a reset of the 82077, the Configuration
Control Register (CCR) should be reinitialized for the
appropriate data rate. An external reset via the RESET pin will cause the data rate and write precompensation values to default to 250 Kbps (10b) and
125 ns (OOOb) respectively. Since the 125 ns write
precompensation value is optimal for the 5%" and
3%" disk drive environment, most applications will
not require the value to be changed in the initialization sequence. As a note, a software reset issued via
the DOR or DSR will not affect the data rate or write
precompensation values. But it is recommended as
a safe programming practice to always program the
data rate after a reset, regardless of the type.
The CONFIGURE command should also be issued if
the system requirements are different from the default settings (as described in Section 5.2.7). For example, the CONFIGURE command can be used to
enable the FIFO, set the threshold, and enable Implied Seeks.
The non-DMA mode flag, step rate (SRT), head load
(HLT), and head unload times (HUT) programmed by
the SPECIFY command do not default to a known
state after a reset. This behavior is consistent with
the 8272A and has been preserved here for compatibility.Thus, it is necessary to always issue a SPECIFY command in the initialization routine.
Since polling is enabled after a reset of the 82077,
four SENSE INTERRUPT STATUS commands need
to be issued afterwards to clear the status flags for
each drive. When issuing a SENSE INTERRUPT
STATUS command when no active interrupt condition is present, the status register STO will return a
value of 80H (invalid command). The flowchart in
Figure 8-3 illustrates how the software clears each
of the four interrupt status flags internally queued by
the 82077. It should be noted that although four
SENSE INTERRUPT STATUS commands are issued, the INT pin is only active until the first SENSE
INTERRUPT STATUS command is executed.
8.3 Recalibrates and Seeks
Commands that position the disk head are different
from the typical READ/WRITE/FORMAT command
in the sense that there is no result phase. Once a
RECALIBRATE, SEEK, or RELATIVE SEEK command has been issued, the 82077 will return a ready
status in the Main Status Register (MSR) and perform the head positioning operation as a background task. When the seek is complete, the 82077
will assert the INT signal to request service. A
SENSE INTERRUPT STATUS command should
then be asserted to clear the interrupt and read the
status. of the operation. Since the drive and motor
enable signals are directly controlled through the
Digital Output Register (DOR) on the 82077, a write
to the DOR will need to precede the RECALIBRATE
or SEEK command if the drive and motor is not already enabled. Figure 8-4 shows the flow chart for
this operation.
As a note, if the CONFIGURE command is issued
within 250 p.s of the trailing edge of reset (@ 1
Mbps), the polling mode of the 82077 can be disabled before the polling initiated interrupt occurs.
Since polling stops when the 82077 enters the command phase, it is only time critical up to the first byte
of the CONFIGURE command. If disabled in time,
the system software no longer needs to issue the
four SENSE INTERRUPT STATUS commands to
clear the internal interrupt flags normally caused by
polling.
7-66
82077
SEEK FAILURE
290166-25
Figure 8-4. Recalibrate and Seek Operations
7-67
inter
82077
If implied seeks are not enabled, the disk drive head
must be positioned over the correct cylinder by executing a SEEK command. After the seek is complete, a head settling time needs to be asserted before the read or write operation begins. For most
drives, this delay should be a minimum of 15 ms.
When using implied seeks, the minimum head settling time can b~ enforced by the head load time
(HLT) parameter designated in the SPECIFY command. For example, a HLT value of 8 will yield an
effective head settling time of 16 ms for a programmeddata rate of 500 Kbps. Of course if the
head is already positioned over the correct cylinder,
the head settling time does not need to be enforced.
8.4 Read/Write Data Operations
A read or write data operation requires several steps
to complete successfully. The motor needs to be
turned on, the head positioned to the correct cylinder, the DMA controller initialized, the read or write
command initiated, arid an error recovery scheme
implemented. The flowchart in Figure 8-5 highlights
a recommended algorithm for performing a read or
write data operation.
Before data can be transferred to or from the diskette, the disk drive motor must be brought up to
speed. For most 3%" disk drives, the spin-up time is
300 ms, while the 5%" drive usually requires about
500 ms due to the increased moment of inertia associated with the larger diameter diskette.
The DMA controller is then initialized for the data
transfer and the read or write command is executed.
Typically the DMA controller will assert Terminal
Count (TC) when the data transfer is complete. The
82077 will then. complete the current data transfer
and assert the INT signal signifying it has entered
the result phase. The result phase can also be entered by the 82077 if an error is encountered or the
last sector number equals the End of Track (EaT)
parameter'.
.
One technique for minimizing the motor spin-up delay in the read data case is to begin the read operation immediately after the motor is turned on. When
the motor is not initially up to speed, the internal
data separator will fail to lock onto the incoming data
stream and report a failure in the status registers.
The read operation is then repeated until successful
status is obtained. There is no risk of a data integrity
problem since the data field is CRC validated. But, it
is not recommended to use this technique for the
write data operation even though it requires successful reading of the ID field before the write takes
place. The data separator performance of the 82077
is such that locking to the data stream could take
place while the motor speed variation is still significant. This could result in errors when an attempt is
made to read the disk media by other disk controllers that have a narrower incoming data stream frequency bandwidth.
Based on the algorithm in Figure B-5, if an error is
encountered after reading the result bytes, two more
retries are performed by reinitializing the DMA controller and r.e-issuing the read or w~ite data command. A persisting failure could indicate the seek
operation did not achieve proper alignment between
the head and the track. The disk head should then
be recalibrated and the' seek repeated for a maximum of two more tries. Unsuccessful operation after
this point should be reported as a disk failure to the
.
operating system.
After the motor has been turned on, the matching
data rate for the media inserted into the disk drive
should then be programmed to the 82077 via the
Configuration Control Register (CCR). The 82077 is
designed to allow a diff~rent data rate to be programmed arbitrarily without disrupting the integrity of
the device. In some applications, it is required to automatically determine the recorded data rate of the
inserted media. One technique for dOing this is to
perform a READ ID operation at each available data
rate until a successful status is returned in the result
phase.
8.5 Formatting
The disk' formatting procedure involves positioning
the head on each track and creating a fixed format
field used for organizing the data fields. The flowchart in Figure 8-6 highlights the typical format procedure.
7-68
82077
290166-26
Figure 8-5. Read/Write Operation
7-69
82077
SEEK TO NEXT CYLINDER
FOC TIMEOUT ERROR
290166-27
Figure 8·6 Formatting
7-70
inter
82077
After the motor has been turned on and the correct
data rate programmed, the disk head is recalibrated
to track O. The disk is then allowed to come up to
speed via a 500 ms delay. It is important the disk
speed has stabilized before the actual formatting to
avoid any data rate frequency variations. Since the
format fields contain critical information used by the
data separator of the disk controller for synchronization purposes, frequency stability of the data stream
is imperative for media interchangeability among different systems.
The 10 field data created on the disk during the format process is provided by the DMA controller during the execution phase. The DMA controller is initialized to send the C, H, Rand N values for each
sector 10 field. For example, to format cylinder 7, on
head 1, with 9 sectors, and a sector size of 2 (512
bytes), the DMA controller should be programmed to
transfer 36 bytes (9 sectors x 4 bytes per sector)
with the following data field: 7,1,1,2, 7,1,2,2, 7,1,3,2,
... 7,1,9,2. Since the values provided to the 82077
during the execution phase of the format command
are directly recorded as the 10 fields on the disk, the
data contents can be arbitrary. Some forms of copy
protection have been implemented by taking advantage of this capability.
operation. The 82077 supports this older verify technique, but also provides a new VERIFY command
that does not require the use of the DMA controller.
To verify a write data transfer or format track operation using the VERIFY command, the software simply issues the command with the same format as a
READ DATA command but without the support of
the DMA controller. The 82077 will then perform a
disk read operation without a host data transfer. The
CRC will be calculated for each sector read and
compared against the value stored on the disk.
When the VERIFY command is complete, the status
register will report any detected CRG errors. If EOT
is programmed for the final sector number of the
track, and the multi-track (MT) bit is set, then both
heads can be checked with one VERIFY command.
9.0 DESIGN APPLICATIONS
9.1 PCI AT Floppy Disk Controller
This section presents a design application of a PCI
AT compatible floppy disk controller. With an 82077,
a 24 MHz crystal, a resistor package, and a device
chip select, a complete floppy disk controller can be
built. The 82077 integrates all the necessary building
blocks for a reliable and low cost solution. But before we discuss the design application using the
82077, it is helpful to describe the architecture. of the
ciriginallBM PCI ATfloppy disk controller design that
uses the 8272A.
After each head for a cylinder has been formatted, a
seek operation to the next cylinder is performed and
the format process is repeated. Since the FORMAT
TRACK command does not have implied seek capability, the SEEK command must be used. Also, as
discussed in Section 8-2, the head settling time
needs to be adhered to after each seek operation.
9.1.1 PC/AT FLOPPY DISK CONTROLLER
ARCHITECTURE
8.6 Verifies
The standard IBM PCI AT floppy disk controller using the 8272A requires 34 devices for a complete
solution. The block diagram in Figure 9-1 illustrates
the complexity of the disk controller. A major portion
of this logic involves the design of the data separator. The reliability of the disk. controller is primarily
dictated by the performance and stability of the data
separator. Discrete board level analog phase lock
loops generally offer good bit jitter margins but suffer
from instability and tuning problems in the manufacturing stage if not carefully designed. While digital
data separator designs offer stability and generally a
lower chip count, they suffer from poor performance
in the recovery of data.
In some applications, the sector data needs to be
verified immediately after each write operation. The
verify technique historically used with the 8272A or
82072 disk controller involved reinitializing the DMA
controller to perform a read transfer or verify transfer
(DACK# is asserted but not RD#) immediately after
each write operation. A read command is then to be
issued to the disk controller and the resulting status
indicates if the CRG validated the previously written
data. This technique has the drawback of requiring
additional software intervention by having to reprogram the DMA controller between each sector write
7-71
intJ
82077
DIR
buffer
~
l'
PC Bus
Disk Interface
r--
r-Decode
logic
-
DOR
latch
~
.....
...
~.
+
~
r---
..
8272A
...•
..
'"
..
r
Buffer
---
Buffers
...,
...
•
'"
'"
-.to
r
"'--
r----.
'"
r
_
Control
... Data
......
'"
Address ..
'--r--
Buffers
Write precomp
logic
I- ~
I-r:
Data separator
t.
~
'--
I.t
...
,'"
I......t
DSR
latch
I.--...f
.
'"-
Buffers
Request
'--
J
i4'
Clock prescale
logic
i4'-
t
290166-28
Figure 9-1. Standard IBM PCI AT Floppy Disk Controller
Table 9-1 indicates the drive and media types the
IBM PC/AT disk controller can support. This requires the data separator to operate at three different data rates: 250 Kbps. 300 Kbps and 500 Kbps.
Clocks to the data separator and disk controller
need to be prescaled correspondingly to accommodate each of these data rates. The clock prescaling
is controlled by the Data rate Select Register (DSR).
Supporting all three data rates can compromise the
performance of the phase lock loop (PLL) if steps
are not taken in the design to adjust the performance parameters of the PLL with the data rate.
Table 9-1. Standard PCIAT
Drives and Media Formats
Capacity
Drive
Speed.
Data
Rate
360 Kbyte 300 RPM 250 Kbps
·360 Kbyte 360 RPM 300 Kbps
1.2 Mbyte 360 RPM 500 Kbps
Sectors Cylinders
9
9
15
'360 Kbyte diskette In a 1.2 Mbyte drive.
7-72
40
40
80
82077
The PCI AT disk controller provides direct control of
the drive selects and motors via the Digital Output
Register (DOR). As a result, drive selects on the
8272A are not utilized. This places drive selection
and motor speed-up control responsibility with the
software. The DOR is also used to perform a software reset of the disk controller and tristate the
DR02 and IR06 output signals on the PC bus.
9.1.282077 PCIAT SOLUTION
The 82077 integrates the entire PCI AT controller
design with the exception of the address decode on
a single chip. The schematic for this solution is
shown in Figure 9-2. The chip select for the 82077 is
generated by a 16L8 PAL that is programmed to decode addresses 03FOH thru 03F7H when AEN (Address Enable) is low. The programming equation for
the PAL is shown in a ABEL file format in Figure 9~3.
An alternative address decode solution could be
provided by using a 74LS133 13 input NAND gate
and 74LS04 inverter to decode A3-A14 and AEN.
Although the PCI AT allows for a 64K 1/0 address
space, decoding down to a 32K 1/0 address space
is sufficient with the existing base of add-in cards.
The design of the disk controller also requires address decode logic for the disk controller and register set, buffering for both the disk interface and PC
bus, support for write precompensation and monitoring of the disk change signal via a separate read
only register (DIR). An 1/0 address map of the complete register set for the PCI AT floppy disk controller is shown in Table 9-2.
A direct connection between the disk interface and
the 82077 is provided by on-chip output buffers with
a 40 mA sink capability. Open collector outputs from
the disk drive are terminated at the disk controller
with a 1500. resistor pack. The 82077 disk interface
inputs contain a schmitt trigger input structure for
higher noise immunity. The host interface is a similar
direct connection with 12 mA sink capabilities on
DBO-DB7, INT and ORO.
Table 9-2.110 Address Map for the PCIAT
110
Address
3FOH
3F1H
3F2H
3F3H
3F4H
3F5H
3F6H
3F7H
3F7H
Access
Type
-
-
Write
Read
Read/Write
Write
Read
Description
Unused
Unused
Digital Output Register
Unused
Main Status Register
Data Register
Unused
Data Rate Select Register
Digital Input Register
7-73
,...-SAl
5..
SA5
SA6
SA7
SA10
SAl1
SA12
""c
iil
r!!-
•5
r!l16
8
•
~
16L8
15
~
fll12
~-l
SA''}
SA14
SA15
AEN
~
DC.2
~
SAO
co
2
7
SA'
i!i
.
6
SA8
l
+5V
1-~
lORD
IOWR
5X 150.0.
., .
m~ll
Jltol:gl ::l1:P~1 ~I ..
IIJ.
SAl
-.j
'V
'0
-.j
~
......
~
~
"g
"g
'<
c
iii"
;I;
oo
a
10
11 :0
SAl
~
fi
SDO
SDI
'" '"
IVI ltl:jO I:"::
U
0
g""'!OJ
~
a..
IItN
> :g
~ IX ~ ~ ~
~ 0
N
>UI ~ ~
lli
I~
SO<
17
SD5
SD6
SD7
I vf.
.
23
rRQ6
ORQ2
RST
5
I
:CC ~
5'
,I
STEP 55
Vss
DB"
Vee
82077
WRDATA.
WE
DBS
HOSEL
OB6
.VSS
Vss
DENSEL
OB7
WFY
~
00
ORO
AVec
~
E
o
Q
N
~
1~1~1S;
0:
;;
Iii:
I:;;
~ :; :! ~ ~ C) _
X
N
X
~
=...1
:a:s
~
>...1
~ g B8
> >
%
0:
AVss
u
oNe
Z
Z
INDEX
10
MEA
12
DSs
~
16
MES
18
DiR
20
STEP
22
WDATA
5'
24
~
51
26
TRKOO
28
wp
30
RDATA
32
HDSEL
~I
~
F-
~
~
~
:::t
"-
orR
VSS
NC
8
D~~ Fs;v
MEO ~
56
Vss
DBt
25
26 Te
lOX·
TC
.!.
jg w
~
15 083
SD.
-
0(
14 082
SD2
2-
if
°
>Vt
2 -;;;:-
~ NC
34
./
WE
-
34 PIN 0
(odd pins
~
(§
~
~
DSKCG
@
IiiiiJ
'FACE
lunded)-
~
c:::>
~
"" !;'l'l'I""
.."
.."
.."
!OJ
.."
.."
.."
..".
'iii!
••
@
2:eJ
~
.OO5p.F
22
r
.p JH'
22~
~
e::J
c:::>
-------
290166-29
©
~
inter
82077
MODULE PCAT077_LOGIC;
TITLE "82077 PC/AT FLOPPY DISK CONTROLLER' ;
PCAT077 DEVICE "PI6L8';
GND,VCC
SA3,SA4,SA5,SA6,SA7,SA8,SA9,SAI0
SAll,SAI2,SAI3,SAI4,SAI5,AEN
CS077_
PIN
PIN
PIN
PIN
10,20;
1,2,3,4,5,6,7,8;
9,11,13,14,15,16;
12;
EQUATIONS
"" CHIP SELECT FOR THE 82077 (3FOH -- 3F7H)
CS077_
=
!( !SAI5 & !SAI4 & !SAI3 & !SAI2 & !SAll & !SAI0 &
SA9 & SA8 & SA7 & SA6 & SA5 & SA4 & !SA3 & !AEN);
END PCAT077_LOGIC
Figure 9-3. PAL Equation File for a PCI AT Compatible FDC Board
9.2.1 3.5" DRIVES UNDER THE AT MODE
of the disk drive will drive both high or low voltage
levels when the drive is selected, and float only
when the drive has been deselected. These totem
pole outputs generally can only sink or source 4 mA
of current. As a result, it is recommended to replace
the 1500 termination resistor pack with a 4.7 KO
package to pull floating signals inactive. Some other
3.5" drives do have an open collector interface, but
have limited sink capability. In these cases, the drive
manufacturer manuals usually suggest a 1 KO termination.
If it is intended to interface the floppy disk controller
with a 3.5" disk drive in a PCI AT application, then it
is likely that two design changes will need to be implemented for the design discussed in Section 9.1.
Most 3.5" disk drives incorporate a totem pole interface structure as opposed to open collector. Outputs
The second change required under "AT mode" operation involves high capacity 3.5" disk drives that
utilize a density select signal to switch between media recorded at a 250 Kbps and 500 Kbps data rate.
The polarity of this signal is inverted for 3.5" drives
versus 5.25" drives. Thus, an inverter will need to
9.2 3.5" Drive Interfacing
The 82077 is designed to interface to both 3.5" and
5.25" disk drives. This is facilitated by the 82077 by
orienting the "PS/2 mode" for 3.5" drives and the
"AT mode" for 5.25" drives. But at the same time,
this does not inhibit the use of the two types of
drives in the opposite mode.
7-75
intJ
82077
be added between the OENSEL output of the 82077
and the disk drive interface connector when using
3.5" drives. But drives that do not support both data
rates or drives with an automatic density detection
feature via an optical sensor do not require the use
of the OENSEL signal.
termination resistor pack required by 5.25" drives
cannot be used with the 3.5" drive. To accommodate both drives with the same disk controller, the
outputs of the 3.5" drive should be buffered before
connecting to the 82077 disk interface inputs. The
82077 inputs are then connected to the necessary
resistive termination load for the 5.25" interface.
9.2.2 3.5" DRIVES UNDER THE PS/2 MODE
The block diagram in Figure 9-4 highlights how a
combined interface could be designed. In this example, the 5.25" drive is connected to drive select 0
(OSO) and the 3.5" drive is connected to drive select
1 (OS1). OS1 is also used to enable a 74LS244 buffer on the output signals of the 3.5" drive. The drive
select logic of the 82077 is mutually exclusive and
prevents the activation of the buffer and 5.25" drive
at the same time. Since the 74LS244 has an IOL of
24 mA, the termination resistor should be increased
to 220!l. This could impact the reliability of the 5.25"
drive interface if the cable lengths are greater than 5
feet.
Interfacing 3.5" disk drive under the "PS/2 mode"
of the 82077 has been simplified. The OENSEL output signal polarity will reflect a 3.5" drive mode of
operation. That is, OENSEL will be high for 250 Kbps
or 300 Kbps and low for 500 Kbps or 1 Mbps (assuming INVERT# is low). Thus the only change
from the disk interface shown in Figure 9-2 is to replace the 150!l termination resistor pack with a value of about 10 K!l. This will prevent excessive current consumption on the CMOS inputs of the 82077
by pulling them inactive when the drivels) are deselected.
To accommodate the polarity reversal of the OENSEL signal for 3.5" drives, it is routed through an
inverter for the 3.5" drive interface. A 1 K!l pull-up
should be placed on the output of the inverter to
satisfy the IOH requirements for the 3.5" drive when
using a 74LS04.
9.2.3 COMBINING 5.25" AND 3.5" DRIVES
If 5.25" and 3.5" drives are to be combined in a
design, then steps need to be taken to avoid contention problems on the. disk interface. Since 3.5"
drives do not have a large sink capability, the 150!l
\41----..
220.0.
R-pock
INPUTS
DENSEL
OUTPUTSI-----+--t-t
DSO~--------~--~
DS1~--------~--_r--
__--~----------~
INVERT
74LS244
290166-30
Figure 9-4. Combined 3.5" and 5.25" Drive Interface
7-76
82077
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
10.0 D.C. SPECIFICATIONS
10.1 Absolute Maximum Ratings
Storage Temperature .......... -65°C to + 150°C
Supply Voltage ................... - 0.5 to + 8.0V
Voltage on Any Input ........... GND - 2V to 6.5V
Voltage on Any Output .. GND - 0.5V to VCC + 0.5V
NOTICE Specifications contained within the
fol/owing tables are subject to change.
Power Dissipation ........................ 1 Watt
10.2 D.C. Characteristics
TA = O°C to = 70°C, Vcc = +5V ±10%, Vss = AVss = OV
Symbol
VILC
Parameter
Input Low Voltage, X1
Min
Max
Unit
-0.5
0.8
V
Test Conditions
VIHC
Input High Voltage, X1
3.9
Vcc +0.5
V
VIL
Input Low Voltage
(all pins except X1)
-0.5
0.8
V
VIH
Input High Voltage
(all pins except X1)
2.0
VCC +0~5
V
VOL
Output Low Voltage
DRATEO-1 and MFM
0.4
V
IOL = 2.5mA
DBO-7, INT and DRO
0.4
V
IOL = 12 mA
MEO-3, DSO-3, DIR, STP
WRDATA, WE, HDSEL
and DENSEL
0.4
V
IOL = 40mA
VOH
Output High Voltage
DRATEO-1 and MFM
3.0
V
IOH = -2.5mA
All Other Outputs
3.0
V
IOH = -4.0mA
Vcc - 0.4
V
IOH = -100 /-LA
All Outputs
ICC1
ICC2
ICC3
ICC4
Vcc Supply Current (Total)
1 Mbps Data Rate, VIL = Vss, VIH = Vcc
1 Mbps Data Rate, VIL = 0.45, VIH = 2.4
500 Kbps Data Rate, VIL = Vcc, VIH = Vcc
500 Kbps Data Rate, VIL = 0.45, VIH = 2.4
45
50
35
40
mA
mA
mA
mA
(Notes
(Notes
(Notes
(Notes
Iccss
Icc in Powerdown
1.5
mA
(Note 3) Typical
IlL
Input Load Current
(all input pins)
10
-10
/-LA
/-LA
VIN = Vcc
VIN = OV
IOFL
Data Bus Output Float Leakage
±10
/-LA
0.45 tt"~'''.( ")C
I~
rCload
VSS
Cload
0.8
0.45
08
290166-8
290166-7
= 50 pF for aI/logic outputs,
100 pF for the. data bus.
11.0 A.C. SPECIFICATIONS
= O°C to 70°C, Vce = +5V ±10%, VSS =
TA
Symbol
AVSS
=
Parameter
OV
Min
Max
Unit
10
ns
CLOCK TIMINGS
t1
Clock Rise Time
Clock Fall Time
t2
Clock High Time(7)
10
ns
16
26
ns
t3
Clock Low Time(7)
16
26
ns
t4
Clock Period
40
43
ns
t5
Internal Clock Period(3)
HOST READ CYCLES
t7
Address Setup to RD
t8
RD Pulse Width
t9
Address Hold from RD
t10
Data Valid from RD
5
ns
100
ns
0
ns
80
(1S
60
ns
t11
Command Inactive
t12
Output Float Delay
35
ns
t13
INT Delay from RD
t5 + 125
ns
t14
Data Hold from RD
5
7-78
ns
inter
82077
A.C. SPECIFICATIONS (Continued)
= +5V ±10%, VSS =
TA = O°C to 70°C, Vee
Symbol
AVSS
=
Parameter
OV
Min
Max
Unit
HOST WRITE CYCLES
t15
.Address Setup to WR
t16
WR Pulse Width
5
ns
100
ns
t17
Address Hold from WR
0
ns
t18
Command Inactive
60
ns
t19
Data Setup to WR
70
ns
t20
Data Hold from WR
0
ns
t21
INT Delay from WR
t5 + 125
ns
DMACYCLES
t22
DRO Cycle Period(1)
t23
DACK to DRO Inactive(1)
t24
RD to DRO Inactive(4)
t25
DACK Setup to RD, WR
5
t26
DACK Hold from RD, WR
0
t27
DRO to RD, WR Active(1)
0
t28
Terminal Count Width(10)
50
t29
TC to DRO Inactive
6.5
fJ-s
75
100
ns
ns
ns
ns
6
fJ-s
ns
150
ns
RESET
t30
Reset Width(5)
t31
Reset to Control Inactive
t4
170
2
fJ-s
WRITE DATA TIMING
t32
Write Data Width(6)
ns
DRIVE CONTROL
t35
DIR Setup to STEP
0.5
2
t36
DIR Hold from STEP
10
fJ-s
t37
STEP Active Time (High)
2.5
fJ-s
t38
STEP Cycle Time(2)
t39
INDEX Pulse Width
fJ-s
fJ-s
5
7-79
t5
Intel
82077
A.C. SPECIFICATIONS (Continued)
TA
=
0·Cto70·C, Vcc
=
+5V ±10%, Vss
Symbol
= AVss =
OV
Parameter
Min
t40
Read Data Pulse Width
50
144
Pll Data Rate 82077-1
Max
Unit
1M
bitls
500K
bitls
64
t44
READ DATA TIMING
82077
t44
Data Rate Period 11144
tlOCK
lockup Time
ns
NOTES:
1. This timing is for FIFO threshold = 1. When FIFO threshold is N bytes, the value should be multiplied by N and subtract
1.5 /Ls. The value shown is for 1 Mbps, scales linearly with data rate.
2. This value can range from 0.5 ms to 8.0 ms and is dependent upon data rate and the Specify command value.
3. Many timings are a function of the selected data rate. The nominal values for the internal clock period (t5) for the various
data rates are:
1 Mbps
500 Kbps
300 Kbps
250 Kbps
3 x oscillator period
6 x oscillator period
10 x oscillator period
12 x oscillator period
=
=
=
=
125
250
420
!:i00
ns
ns
ns
ns
4. If DACK transitions before RD, then this specification is ignored. If there is no transition on DACK, then this becomes the
DRO inactive delay. 5. Reset requires a stable oscillator to meet the minimum active period.
6. Based on the internal clock period (15). For various data rates, the Write Data Width minimum values are:
1 Mbps
500 Kbps
300 Kbps
250 Kbps
3 x oscillator period
6 x oscillator period
10 x oscillator period
12 x oscillator period
- 50
- 50
-50
-50
ns
ns
ns
ns
= 150
= 360
= 615
= 740
ns
ns
ns
ns
7. Test points for clock high time are 3.5V. Due to transitional times, clock high time max and clock low time max cannot be
met simultaneously. Clock high time min and clock low time max cannot be met simultaneously.
8. Based on internal clock period (t5).
9. Jitter tolerance is defined as: Maximum bit shift from nominal position X 100%
1/4 period of nominal data rate
.
It is a measure of the allowable bit jitter that may be present and still be correctly detected. The data separator jitter
tolerance is measured under dynamic conditions that jitters the bit stream according to a reverse precompensation algorithm.
10. TC width is defined as the time that both TC and DACK are active.
7-80
82077
CLOCK TIMINGS
290166-9
HOST READ CYCLES
AO,CS,
DACK
t7-
~-------t8--------~
t10
RD
DATA
--------<1
INT
290166-10
7-81
82077
HOST WRITE CYCLES
AO.CS.
DACK
1 - - - - - \16 - - - - - I
1----\19 ----+-1
DATA
INT
290166-11
DMA CYCLES
1--------\22---------1
ORO
1 - - - - \23 - - - - - - - I
RD. WR
290166-12
TERMINAL COUNT
290166-13
7-82
inter
82077
RESET
J;=t30~
RESET
~
_ _ _ _ _ _ _ _ _ __
''''1
ORO. INT.
WE
290166-14
WRITE DATA TIMING
WRDATA
290166-15
NOTE:
Invert high.
DRIVE CONTROL
>C
DSO.1=><:_ _ _ _
-----u.f<--
DIR
STEP
INDEX
~
----~
~t39~
~-------------290166-16
NOTE:
For overlapped seeks. only one step pulse per drive selection is issued. Non-overlapped seeks will issue all programmed
step pulses. Invert high.
7-83
inter
82077
INTERNAL PLL
,~,. --D1+-t4-0--.-~_t_44_-_-_-_-_-_-_--~--l
....
290166-17
NOTE:
Invert high.
12.0 DATA SEPARATOR CHARACTERISTICS
.---------------~
100
90
80
70
60
50
40
30
20
10
0
235240 245 250 255 260 265
...
...'"
~
...'"
0
r--
z
-<
..J
I:
..,
100
90
80
70
60
50
40
30
20
10
-
-
r- I-..
o
280285 290 295 300 305 310315320
DATA RATE (Kbps)
DATA RATE (kpbs)
290166-18
290166-19
Figure 12-1. Typical Jitter Tolerance
vs Data Rate (Fe = 250 Kbps)
...
z
...~
~
...'"
0
..J
I:
..,
100
90
80
70
60
50
40
30
20
10
Figure .12-2. Typical Jitter Tolerance
vs Data Rate (Fe = 300 Kbps)
...
z
...'"-<
~
...'"
~
0
..J
I:
..,
o
100
90
80
70
60
50
40
30
20
10
r-'"
v
......Ir- ,v
o
470480 490 500 510 520 530
940 960 980 100010201040 1060
DATA RATE (kbps)
DATA RATE (kbps)
290166-20
290166-21
Figure 12-3. Typical Jitter Tolerance
vs Data Rate (Fe = 500 Kbps)
Figure 12-4. Typical Jitter Tolerance
vs Data Rate (Fe = 1 Mbps)
7-84
inter
82077
REVISION HISTORY
DOCUMENT:
82077 Advanced Information Data Sheet
NEW REVISION NUMBER: 290166-001
OLD REVISION NUMBER: 290166-002
1. On the front page, Vertical Recording support has been added to the feature list.
2. On the front page, Figure 1 has been changed for pins 37 and 38 from NC to LOFIL and HIFIL respectively.
3. In Table 1 under the PLL section, a pin description has been added for HIFIL and LOFIL.
4. After Section 1.1, Section 1.2 has been added to describe the Perpendicular Recording Mode.
5. Under Section 2.1.3, Table 2-1 has been added that lists recommended DOR drive control values.
6. Table 5-1 has been updated to include the Perpendicular Mode command.
7. Under Section 5.1.7.1, Figure 5-3 has been added to describe the Toshiba perpendicular format.
8. Section 5.2.11 has been added to describe the Perpendicular Mode command.
9. Under Section 10.2 of the D.C. Characteristics, the Icc specifications have been reduced in value and the
testing descriptions clarified.
10. Under Section 11.0 of the A.C. Specifications, t10 has been reduced from 95 ns to 80 ns and 124 has been
reduced from 150 ns to 100 ns.
11. Section 12.0 has been added to describe the data separator characteristics of the internal PLL.
7-85
infef
AP-116
APPLICATION
NOTE
November 1986
An Intelligent Data Base System
Using the 8272
TOM ROSSI
PERIPHERALS APPLICATIONS MANAGER
Order Number: 207875-001
7-87
intJ
AP-116
tective jacket (Figure 1). The circular piece of plastic
revolves at a fixed speed (approximately 360 rpm) within its jacket in much the same manner that a record
revolves at a fixed speed on a stereo turntable. Disks
are manufactured in a variety of configurations for various storage capacities. Two standard physical disk sizes
are commonly used. The 8-inch disk (8 inches square)
is the larger of the two sizes; the smaller size (5 '14
inches square) is often referred to as a mini-floppy. Single-sided disks can record information on only one side
of the disk, while double-sided disks increase the storage capacity by recording on both sides. In addition,
disks are classified as single-density or double-density.
Double-density disks use a modified recording method
to store twice as much information in the same disk
area as can be stored on a single-density disk. Table 1
lists storage capacities for standard floppy disk media.
1.0 INTRODUCTION
Most microcomputer systems in use today require lowcost, high-density removable magnetic media for information storage. In the area of removable media, a designer's choice is limited to magnetic types and floppy
disks (flexible diskettes), both of which offer non-volatile data storage. The choice between these two technologies is relatively straight-forward for a given application. Since disk drives are designed to permit random
access to stored information, they are significantly faster than tape units. For example, locating information
on a disk requires less than a second, while tape movement (even at the fastest rewind or fast-forward speed)
often requires several minutes. This random access ability permits the use of floppy disks in on-line storage
applications (where information must be located, read,
and modified/updated in real-time under program or
operator control). Tapes, on the other hand, are ideally
suited to archival or back-up storage due to their large
storage capacities (more than 10 million bytes of data
can be archived on a cartridge tape).
A magnetic head assembly (in contact with the disk)
writes information onto the disk surface and subsequently reads the data back. This head assembly can
Table 1. Formatted Disk Capacities
A sophisticated controller is required to capitalize on
the abilities of the disk storage unit. In the past, disk
controller designs have required upwards of 150 ICs.
Today, the single-chip 8272 Floppy Disk Controller
(FDC) plus approximately 30 support devices can handle up to four million bytes of on-line data storage on
four floppy disk drives.
Single-Density Format
Byte/Sector
128
256
512
1024
Sectors/Track
26
15
8
4
77
77
77
77
Track/Disk
Bytes/Disk
256,256 295,680 315,392 315,392
. Double-Density Format
Byte/Sector
128
256
512
1024
Sectors/Track
52
30
16
8
77
77
77
77
Track/Disk
Bytes/Disk
512,512 591,360 630,784 630,784
The Floppy Disk
A floppy disk is a circular piece of thin plastic material
covered with a magnetic coating and enclosed in a pro-
move from the outside edge of the disk toward the center in fixed increments. Once the head assembly is positioned at one of these fixed positions, the head can read
or write information in a circular path as the disk revolves beneath the head assembly. This method divides
the surface into a fixed number of cylinders (as shown
in Figure 2). There are normally 77 cylinders on a standard disk. Once the head assembly is positioned at a
given cylinder, data may be read or written on either
side of the disk. The appropriate side of the disk is
selected by the read/write head address (zero or one).
Of course, a single-sided disk can only use head zero.
The combination of cylinder address and head address
uniquely specifies a single circular track on the disk.
The physical beginning of a track is located by means of
a small hole (physical index mark) punched through
the plastic near the center of the disk. This hole is optically sensed by the drive on every revolution of the
disk.
EJ~
o
. • INDEX HOLE
I
WRITE PROTECT NOTCH.,/'
207875-1
Each track is subdivided into a number of sectors (see
detailed discussion in section 3). Sectors are generally
Figure 1.A Floppy Diskette
7-89
inter
AP-116
128, 256, 512, or 1024 data bytes in length. This track
sectoring may be accomplished by one of two techniques: hard sectoring or soft sectoring. Hard sectored
disks divide each track into a maximum of 32 sectors.
The beginning of each sector is indicated by a sector
hole punched in the disk plastic. Soft sectoring, the
IBM standard method, allows software selection of sector sizes. With this technique, each data sector is preceded by a unique sector identifier that is read/written
by the disk controller.
Finally, the drive provides additional signals to the system controller regarding the status of the drive and
disk. These .signals include:
Drive Ready-Signals the system that the drive door is
closed and that a floppy disk is inserted into the drive.
Track Zero-Indicates that the head assembly is located over the outermost track of the disk. This signal may
be used for calibration of the disk drive at system initialization and after an error condition.
A floppy disk may also contain a write protect notch
punched at the edge of the outer jacket of the disk. This
notch is detected by the drive and passed to the controller as a write protect signal.
Write Protect-Indicates that the floppy disk loaded
into the drive is write protected.
Dual Sided-Indicates that the floppy disk in the drive
is dual-sided.
The Floppy Disk Drive
Write Fault-Indicates that an error occurred during a
recording operation.
The floppy disk drive is an electromechanical device
that records data on, or reads data from, the surface of
a floppy disk. The disk drive contains head control electronics that move the head assembly one increment
(step) forward (toward the center of the disk) or backward (toward the edge of the disk). Since the recording
head must be in contact with the disk material in order
to read or write information, the disk drive also contains head-load electronics. Normally the read/write
head is unloaded until it is necessary to read or write
information on the floppy disk. Once the head assembly
has been positioned over the correct track on the disk,
the head is loaded (brought into contact with the disk).
This sequence prevents excessive disk wear. A small
time penalty is paid when the head is loaded. Approximately thirty to fifty milliseconds are needed before
data may be reliably read from, or written to, the disk.
This time is known as the head load time. If desired,
the head may be moved from cylinder to cylinder while
loaded. In this manner, only a small time interval (head
settling time) is required before data may be read from
the new cylinder. The head settling time is often shorter
than the head load time. Typically, disk drives also contain drive select logic that allows more than one physical drive to be connected to the same interface cable
(from the controller). By means ofa jumper on the
drive, the drive number may be selected by the OEM or
end user. The drive is enabled only when selected; when
not selected, all control signals on the cable are ignored.
Index-Informs the system that the physical index
mark of the floppy disk (signifying the start of a data
track) has been sensed.
CURRENT TRACK
207875-2
Figure 2. Concentric Cylinders on a Floppy
Diskette
7-90
Ap·116
operation has been completed. This feature eliminates the head load time during periods of heavy
disk I/O activity.
S) Data Separation-The actual signal recorded on a
floppy disk is a combination of timing information
(clock) and data. The serial READ DATA input
(from the disk drive) must be converted into two
signal streams: clock and data. (The READ DATA
input operates at 2S0K bits/second for single-density
disks and SOOK bits/second for double-density
disks.) The serial data must also be assembled into 8bit bytes for transfer to system memory. A byte must
be assembled and transferred every 32 microseconds
for single-density disks and every 16 microseconds
for double-density.
6) Error-Checking-Information recorded on a floppy
disk is subject to both hard and soft errors. Hard
(permanent) errors are caused by media defects. Soft
errors, on the other hand, are temporary errors
caused by electromagnetic noise or mechanical interference. Disk controllers use a standard error checking technique known as a Cyclic Redundancy Check
(CRC). As data is written to a disk, a 16-bit CRC
character is computed and also stored on the disk.
When the data is subsequently read, the CRC character allows the controller to detect data errors. Typically, when CRC errors are detected, the controlling
software retries the failed operation (attempting to
recover from a soft error). If data cannot reliably be
read or written after a number of retries, the system
software normally reports the error to the operator.
Multiple CRC errors normally indicate unrecoverable media error on the current disk track. Subsequent recovery attempts must be defined by the system deisgners and tailored to meet system interfacing requirements.
2.0 SUBSYSTEM OVERVIEW
A disk subsystem consists of the following functional
electronic units:
I) Disk Controller Electronics
2) Disk Drive Electronics
3) Controller/Disk Interface (cables, drivers, terminators)
4) Controller/Microprocessor System Interface
The operation of these functional units is discussed in
the following paragraphs.
Controller Electronics
The disk controller is responsible for converting highlevel disk commands (normally issued by software executing on the system processor) into disk drive commands. This function includes:
I)Disk Drive Selection-Disk controllers typically
manage the operations of multiple floppy disk drives.
This controller function permits the· system processor to specify which drive is to be used in a particular operation.
2) Track Selection-The controller issues a timed sequence of step pulses to move the head from its current location to the proper disk cylinder from which
data is to be read or to which data is to be written.
The controller stores the current cylinder number
and computes the stepping distance from the current
cylinder to the specified cylinder. The controller also
manages the head select signal to select the correct
side of the floppy disk.
3) Sector Selection-The controller monitors the data
on a track until the requested sector is sensed.
4)Head Loading-The disk controller determines the
times at which the head assembly is to be brought in
contact with the disk surface in order to read or
write data. The controller is also responsible for
waiting until the head has settled before reading or
writing information. Often the controller maintains
the head loaded condition for up to 16 disk revolutions (approximately 2 seconds) after a read or write
Today, single-chip digital LSI floppy disk controllers
such as the 8272 perform all the above functions with
the exception of data separation. A data separation circuit (a combination of digital and analog electronics)
synchronizes itself to the actual data rate of the disk
drive. This data rate varies from drive to drive (due to
mechanical factors such as motor tolerances) and varies
from disk to disk (due to temperature effects). In order
to operate reliably with both single- and double-density
storage, the data separation circuit must be based on
phase-locked loop (PLL) technology. The phase-locked
loop data separation logic is described in section S. The
7-91
inter
AP-116
separation logic, after synchronizing with the data
stream, supplies a data window to the LSI disk control'Ier. This window differentiates data information from
clock information within the serial stream. The controller uses this window to reconstruct the data previously
recorded on the floppy disk.
'
tion in the transfer; With this method, the controller
issues an interrupt to the processor for each data transfer. (An equivalent method allows the processor to poll
an interrupt flag in the controller status word.) In the
case of a disk write operation, the processor writes a
data byte (to be encoded into the serial output stream)
to the disk controller following the receipt of each controller interrupt. During, a disk read operation, the
processor reads a data byte (previously assembled from
the input data stream) from the controller after each
interrupt. The processor must transfer a data byte from
the controller to memory or transfer a data byte from
memory to the disk controller within 16 or 32 microseconds after each interrupt (double-density and singledensity response times, respectively).
Drive Electronics
Each floppy disk drive contains digital electronic circuits that translate TTL-compatible command signals
into electromechanical operations (such as drive selection and head movement/loading) and that sense and
report disk or drive status to the controller (e.g., drive
ready, write fault, and write protect). In addition, the
drive electronics contain 'analog components to sense,
amplify, and shape data pulses read from, or written to,
the floppy disk surface by the read/write head.
If the system processor must service a variety of other
interrupt sources, this interrupt method may not be
practical, especially in double-density systems. In this
case, the disk controller may be interfaced to a Direct
Memory Access (DMA) controller. When the disk controller requires the transfer of a data byte, it simply
activates the DMA request line. The DMA controller
intenaces to the processor and, in response to the disk
controller's request, gains control of the memory interface for a short periOd of time-long enough to transfer
the requested data byte to/from memory. See section 6
for a detailed DMA interface description:
ControllerIDrive Interface
The controller/drive interface consists of high-current
line drivers, Schmitt triggered input gates,' and flat or
twisted pair cable(s) to connect the disk drive electronics to the controller electronics. Each interface signal
line is resistively terminated at the end of the cable
farthest from the line drivers. Eight-inch drives may be
directly interfaced by means of 50-conductor flat cable.
Generally, cable lengths should be less than ten feet in
order to maintain noise immunity.
3.0 DISK FORMAT
New floppy disks must be written with a fixed format
by the controller before these disks may be used to store
data. Formatting is a method of taking raw media and
adding the necessary information to permit the controller to ,read and write data without error. AIl formatting
is performed by the disk controller on a track-by-track
basis under the direction of the system processor. Generally, a track may'be formatted at any time. However,
since formatting "initializes" a complete disk track; 'all
previously written data is lost (after a format operation). A format operation is normally' used only when
initializing new floppy disks. Since soft-sectoring in
such a predominant formatting technique (due to
IBM's influence), the following discussion will limit itself to self-sectored formats.
Normally, provisions are made for up to four disk
drives to share the same interface cable. The controller
may operate as many cable assemblies as practical. LSI
floppy disk controllers typically operate' one to four
drives on 'a single cable.
ProcessorIMemory Interface
The disk controller must interface to the system processor and memory for two distinct purposes. First, the
processor must specify disk control and command parameters to the controller. These parameters include
the selection of the recording density and specification
of disk formatting information (discussed in section 3).
In addition to disk parameter specification, the processor must also send commands (e.g., read, write, seek,
and scan) to the controller. These commands require
the specification of the command code, drive number,
cylinder address, sector address, and head address.
Most LSI controllers receive commands and parameters by means of processor I/O instructions.
Data Recording Techniques
Two standard data recording techniques are used to
combine clock and data information for storage on a
floppy disk. The single-density technique is referred to
as FM encoding. In FM encoding (see Figure 3), a double frequency encoding technique is used that inserts a
data bit between two adjacent clock bits. (The presence
of a data bit represents a binary "one" while the absence of a data bit represents a binary ·"zero.") The two
adjacent clock bits are referred to as a bit cell, and
In addition to this I/O interface, the controller must
also be designed for high-speed data transfer between
memory and the disk driv.e. Two implementation methods may be used to coordinate this data transfer. The
lower-cost method requires direct processor interven-
7-92
intJ
AP-116
2) Post ID Field Gap-The post ID field gap (gap 2) is
written initially when the track is formatted. During
subsequent write operations, the drive's write circuitry is enabled within the gap and the trailing bytes of
the gap are rewritten each time the sector is updated
(written). During subsequent read operations, the
trailing bytes of the gap are used to synchronize the
data separator logic with the upcoming data field.
3) Data Field-The length (number of data bytes) of
the data field is determined by software when the
track is formatted. The first byte of the data field is
the data address mark, a unique coding that specifies
the beginning of the data field. When a sector is to be
deleted, (e.g., a hard error on the disk), a deleted
data address mark is written in place of the data
address mark. The last two bytes of the data field
comprise the eRe character.
4) Post Data Field Gap-The post data field gap (gap
3) is written when the track is formatted and separates the preceding data field from the next physical
ID field on the track. Note that a post data field gap
is not written following the last physical sector on a
track. The gap itself contains a program-selectable
number of bytes. Following a sector update (write)
operation, the drive's write logic is disabled during
the gap. The actual size of gap 3 is determined by the
maximum number of data bits that can be recorded
on a track, the number of sectors per track and the
total sector size (data plus overhead information).
The gap size must be adjusted so that it is large
enough to contain the discontinuity generated on the
floppy disk when the write current is turned on or
off (at the start or completion of a disk write operation) and to contain a synchronization field for the
upcoming ID field (of the next sector). On the other
hand, the gaps must be small enough so that the
total number of data bits required on the track (sectors plus gaps) is less than the maximum number of
data bits that can be recorded on the track. The gap
except for a unique field identifiers, all clock bits written on the disk are binary "ones." In FM encoding,
each data bit is written at the center of the bit cell and
the clock bits are written at the leading edge of the bit
cell.
The encoding used for double-density recording is
terms MFM encoding (for "Modified FM"). In MFM
encoding (Figure 3) the data bits are again written at
the center of the bit cell. However, a clock bit is written
at the leading edge of the bit cell only if no data bit was
written in the previous bit cell and no data bit will be
written in the present bit cell.
Sectors
Soft-sectored floppy disks divide each track into a number of data sectors. Typically, sector sizes of 128, 256,
512, or 1024 data bytes are permitted. The sector size is
specified when the track initially formatted by the controller. Table 1 lists the single- and double-density data
storage capacities for each of the four sector sizes. Each
sector within a track is composed of the following four
.
fields (illustrated in Figure 4):
1) Sector ID Field-This field, consisting a seven bytes,
is written only when the track is formatted. The ID
field provides the sector identification that is used by
the controller when a sector must be read or written.
The first byte of the field is the ID address mark, a
unique coding that specifies the beginning of the ID
field. The second, third, and fourth bytes are the
cylinder, head, and sector addresses, respectively,
and the fifth byte is the sector length code. The last
two bytes are the 16-bit eRe character for the ID
field. During formatting, the controller supplies the
address mark. The cylinder, head, and sector addresses and the sector length code are supplied to the
controller by the processor software. The eRe character is derived by the controller from the data in the
first five bytes.
I
DATA
1
o
I
0'
I
0
o
I
1
1
I
FM
-
1.1-11- DATA
~CLOCK
MFM
207875-3
Note:
The FM bit cell is twice the size of the MFM bit cell. Thus, the FM time scale in this figure is 4 Its/bit while the MFM time
scale is 2 Its/bit.
Figure 3. FM and MFM Encoding
7-93
inter
AP-116
size must be specified' for all read, write, and format
operation. The gap size used during disk reads and
writes must be smaller than the size used to format the
disk to avoid the splice points between contiguous
physical sectors. Suggested gap sizes are listed in Table
9.
2) Index Address Mark-Theindex address mark con'sists of a unique code that indicates the beginning of
a'data track. One index mark is written on each
track when the track is formatted.
3) Post Index GaP7The post index gap (gap I) is used
during disk read and write operations to synchronize
the data separator logic with the data to be read
from the ID field (ofthe first sector). The post index
gap is written only when the disk is formatted.
4) Sectors-11te sector information (discussed above) is
repeated OIice for each sector on ths track.
Tracks
The overall format for a track is illustrated in Figure 4.
Each track consists of the following fields:
I) Pre-Index Gap-The pre-index gap (gap 5) is written only when the track is formatted.
n
----_
PHYSICAL
INDEX
MARK
....
f~
SECTDR
DATA
FIELD
PRE.
INDEX
GAP
(GAP 5)
FINAL
GAP
(GAP 4)
INDEX
ADDRESS
MARK
,
HEXFF
I
DATA
ADDRESS
MARK
SYNC
(HEX 00)
I
I
PDST
INDEX
GAP
(GAP 1)
POST ID
FIELD
GAP
(GAP 2)
SECTDR
1
ID FIELD
SECTOR 1
DATA FIELD
I
HEX FF
I
SYNC
(HEX
00)
128 x 2" USER DATA BYTES
I
CRC
BYTE 1
I
CRC
BYTE 2
I
II
POST
DATA
FieLD
GAP
(GAP 3)
SECTOR
2
IDFIELD
PDSTID
FIELD
GAP
(GAP 2)
SECTOR 2
DATA FIELD
POST
DATA
FIELD
GAP
(GAP 3)
PDSTID
FIELD'
GAP
(GAP 2)
SECTOR
3
ID FIELD
I
HEX FF
~
ID
ADDRESS
MARK
TRACK
ADDRESS
BYTE 1
BYTE 2
J
HEAD
ADDRESS
BYTE 3
J
SECTOR
ADDRESS
BYTE 4
SYNC
(HEX
00)
~
SECTOR
LENGTH
BYTES
HEX FF
I
CRC
BYTE 1
BYTES
-
FIELD
,
I
I
"~-f
I
SYNC
(HEX
00)
I
CRC
BYTE 2
BYTE 7
I
207875-4
Figure 4. Standard Floppy Diskette Track Format (from sec 204 Manual),
7-94
Ap·116
5) Final Gap-The final gap (gap 4) is written when
the track is formatted and extends from the last
physical data field on the track to the physical index
mark. The length of this gap is dependent on the
number of bytes per sector specified, the legnths of
the program-selectable gaps specified, and the drive
speed.
Sector Interleaving
The initial formatting of a floppy disk determines
where sectors are located within a track. It is not necessary to allocate .sectors sequentially around the track
(i.e., 1,2,3,... ,26). In fact, it is often advantageous to
place the sectors on the track in non-sequential order.
Sequential sector ordering optimizes sector access times
during multi-sector transfers (e.g., when a program is
loaded) by permitting the number of sector specified
(up to an entire track) to be transferred within a single
revolution of the disk. A technique known as sector
interleaving optimizes access times when, although sectors are accessed sequentially, a small amount of processing must be performed between sector reads/writes.
For example, an editing program performing a text
search reads sectors sequentially, and after each sector
is read, performs a software search. If a match is not
found, the software issues a read request for the next
secto~. Since the floppy disk continues to rotate during
the time that the software executes, the next physical
sector is already passing under the read/write head
when the read request is issued, and the processor must
wait for another complete revolution of the disk (approximately 166 milliseconds) before the data may actually be input. With interleaving, the sectors are not
stored sequentially on a track; rather, each sector is
physically removed from the previous sector by some
number (known as the interleave factor) of physical
sectors as shown in Figure 5. This method of sector
allocation provides the processor additional execution
time between sectors on the disk. For example, with a
26 sector/track format, an interleave factor of 2 provides 6.4 milliseconds of processing time between sequential 128 byte sector accesses.
207875-5
Figure 5. Interleaved Sector
Allocation within a Track
4.0 THE 8272 FLEXIBLE DISKETTE
CONTROLLER
The 8272 is a single-chip LSI Floppy Disk Controller
(FOC) that contains the circuitry necessary to implement both single- and double-density floppy disk storage subsystems (with up to four dual-sided disk drives
per FOC). The 8272 supports the IBM 3740 single-density recording format (FM) and the IBM System 34
double-density recording format (MFM). With the
8272, less than 30 ICs are needed to implement a complete disk subsystem. The 8272 accepts and executes
high-level disk commands such as format track, seek,
read sector, write sector, and read track. All data synchronization and error checking is automatically performed by the FOC to ensure reliable data storage and
subsequent retrieval. External logic is required only for
the generation of the FOC master clock and write clock
(see Section 6) and for data separation (Section 5). The
FOC provides signals that control the startup and base
frequency selection of the data separator. These signals
greatly ease the design of a phase-locked loop data separator.
To calculate the correct interleave factor, the maximum
processor time between sector operations must be divided by the time required for a complete sector to pass
under the disk read/write head. After determining the
interleave factor, the correct sector numbers are passed
to the disk controller (in the exact order that they are to
physically appear on the track) during the execution of
a format operation.
In addition to the data separator interface signals, the
8272 also provides the necessary signals to interface to
7-95
.AP-116
Vee
RWISEEK
LCT/DIA
OB0-7
FAlSTP
HDl
RDY
WP/TS
FLT/TRKO
PSo
PS,
WRDATA
DB,
DB,
OS,
DRO
HDSEl
DiCK
Ds"
TERMINAL
COUNT
READY
MFM
WAITE PROTECTITWO SIDE
INDEX
TC
WE
'DX
'NT
elK
DW
OND
WHelk
FAULTITRACK 0
Vee
RD DATA
DRIVE SELECT 0
DRIVE SELECT 1
MFM MODE
IIWISEEK
207875:"6
HEAD LOAD
HEAD SELECT
LOW CURRENT/DIRECTION .
FAULT RESEllSTEP
elK --..
Vee_
GND ---.
207875-7
Figure 6. 8272 Pin Configuration and Internal Block Diagram
COMMAND PHASE: The executing program transfers to the FDC all the information required to perform a
particular disk operation. The
8272 automatically enters the
command phase after RESET
and following the completion
of the result phase (if any) of a
previous command.
EXECUTION PHASE: The FOC performs the operation as instructed. The execution phase is entered immediately after the last command
parameter is written to the
FOC in the preceding command phase. The execution
phase normally ends when the
last data byte is transferred
to/from the disk (signalled by
the TC input to the FDC) or
when an error occurs.
RESULT PHASE
After completion of the disk
operation, status and other
housekeepmg information are
made available to the processor. After the processor reads
this information, the FOC reenters the command phase
and is ready to accept another
command.
microprocessor systems with or without Direct Memory Access (DMA) capabilities. In order to interface to a
large number of commercially available floppy disk
drives, the FDC permits software specification of the
track stepping rate, the head load time, and the head
unload time.
The pin configuration and internal block diagram of
the 8272 is shown in Figure 6. Table 2 contains a description for each FDC interface pin.
Floppy Disk Commands
The 8272 executes fifteen high-level disk interface commands:
Specify
Write Data
Sense Drive Status
Write Deleted Data
Sense Interrupt Status Read Track
Seek
Read ID
Recalibrate
Scan Equal
Scan High or Equal
Format Track
Scan Low or Equal
Read Data
Read Deleted Data
Each command is initiated by a multi-byte transfer
from the processor to the FOC (the transferred bytes
contain command and parameter information). After
complete command specification, the FOC automatically executes the command. The command result data
(after execution of the command) may require a multibyte transfer of status information back to the processor. It is convenient to consider each FOC command as
consisting of the following three phases:
7-96
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AP-116
Table 2. 8272 FDC Pin Description
Number
Pin
Symbol
1
RST
I
J.LP
RESET: Active-high signal that places the FDC in the "idle" state and
all disk drive output signals are forced inactive (low). This input must
be held active during power on reset while the RD and WR input are
active.
2
RD
I·
J.LP
READ: Active-low control signal that enables data transfer from the
FDC to the data bus.
3
WR
I·
J.LP
WRITE: Active-low control signal that enables data transfer from the
data bus into the FDC.
4
CS
I
J.LP
CHIP SELECT: Active-low control signal that selects the FDC. No.
reading of writing will occur unless the FDC is selected.
5
Ao
I·
J.LP
ADDRESS: Selects the Data Register or Main Status Register for
input/output in conjunction with the RD and WR inputs. (See Table 3.)
J.LP
DATA BUS: Bidirectional three-state 8-bit data bus.
6-13
I/O To/From
DBo-DB7 I/O·
Description
14
DRO
0
DMA
DMA REQUEST: Active-high output that indicates an FDC request for
DMA services.
15
DACK
1
DMA
DMA ACKNOWLEDGE: Active-low control signal indicating thalthe
requested DMA transfer is in progress.
16
TC
I
DMA
TERMINAL COUNT: Active-high signal that causes the termination of
a command. Normally, the terminal count input is directly connected to
the TC/EOP output from the DMA controller, signalling that the DMA
transfer has been completed. In a non-DMA environment, the
processor must count data transfers and supply a TC signal to the
FDC.
17
IDX
I
Drive
INDEX: Indicates detection of the physical index mark (the beginning
of a track) on the selected disk drive.
18
INT
0
J.LP
19
CLK
I
20
GND
21
WRCLK
I
22
DW
I
PLL
DATA WINDOW: Data sample signal from the phase-locked loop
indicating that the FDC should sample input data from the disk drive.
INTERRUPT REQUEST: Active-high signal indicating an 8272
interrupt service request.
CLOCK: Signal phase 8 MHz clock (50% duty cycle).
GROUND: DC power return.
WRITE CLOCK: 500 kHz (FM) or 1 MHz (MFM) write clock with a
constant pulse width of 250 ns (for both FM and MFM recording). The
write clock must be present at all times.
23
RDDATA
I
Drive
READ DATA: FDC input data from the selected disk drive.
24
VCO
0
PLL
YCO SYNC: Active-high output that enables the phase-iocked loop to
synchronize with the input data from the disk drive.
25
WE
0
Drive
WRITE ENABLE: Active-high output that enables the disk drive write
gate.
26
MFM
0
PLL
MFM.MODE: Active-high output used by external logic to enable the
MFM double-density recording mode. When the MFM output is low,
single-density FM recording is indicated.
27
HDSEL
0
Drive
HEAD SELECT: Selects head 0 or head 1 on a dual-sided disk.
7-97
inter
AP-116
Table 2. 8272 FDC Pin Description (Continued)
Number
Pin
Symbol
28,29.
DS1,DSO
0
Drive
DRIVE SELECT: Selects one of four disk drives.
30
WRDATA
0
Drive
WRITE DATA: Serial data stream (combination of clock and data bits)
to be written on the disk.
'
31,32
PS1, PSo
0
Drive
PRECOMPENSATION (PRE-SHIFT) CONTROL: Write
precompensation output control during MFM mode. Specifies early,
late, and normal timing signals. See the discussion in Section 5.
33
FLT/TRKO
I
Drive
FAULT/TRACK 0: Senses the disk drive fault condition 'in the Read/
Write mode and the Track 0 condition in the Seek mode.
34
WP/TS
I
Drive
WRITE PROTECT/TWO-SIDED: Sense the disk write protect status
in the Read/Write mode and the dual-sided media status in the Seek
mode.
35
ROY
I
Drive
READY: Senses the disk drive ready status.
36
HDL
0
Drive
HEAD LOAD: Loads the disk drive read/write head. (The head is
placed in contact with, the disk.)
37
FR/STP
0
Drive
FAULT RESET/STEP:' Resets the fault flip-flop in the disk drive when
operating in the Read/Write mode. Provides head step pulses (to
move the head from one cylirider to another cylinder) in the Seek
mode.
38
LCT/DIR
0
Drive
LOW CURRENT/DIRECTION: Signals that the recording head has
been positioned over the inner cylinders (44-77) of the floppy di,sk in
the Read/Write mode. (The write current must be lowered when
recording on the physically shorter inner cylinders of the disk. Most
drives do not track the actual head position and require that the FDC
supply this signaL), Determines the head step direction in the Seek
mode. In the Seek mode, a high level on this pin steps the read/write
head toward .the spindle (step-in); a low level steps the head away
from the spindle (step-out).
39
RW/SEEK
0
Drive
READ, WRITE/SEEK MODE SELECTOR: A high level selects the
Seek mode;a low level selects the Read/Write mode.
40
• Disabled when
I/O To/From
Vee
es is high.
Description
,.
+ 5V DC Power.
In addition.' to the Main Status Register, the FOC contains four additional status registers (STO, ST!, ST2,
and ST3).These registers are :only available during the
result phase of a command.
Interface Registers
To support information transfer between the FDC and
the system processor, the 8272 contains two 8-bit registers: the Main Status Register and the Data Register.
The Main Status Register (read only), contains FDC
status information and may be accessed at any time.
The Main Status Register (Table 4) provides the system
processor with the status of each disk drive, t\le status
of the FDC, and the status of the' processor interface.
The Data Register (read/write) stores data, commands,
parameters, and disk drive status information. The
Data Register is used to program the FOC during the
command phase and to obtain result information after
completion of FDC operations. Data is read from, or
written to, the FOC registers by the combination of the
AO, RD, WR, and CS signals, as described in Table 3.
,
,
, Table 3. FDC Read/Write Interface
CS "Ao
7-98
0
0
0
0
0
0
0
1
0
'0
1
1
1
X
RD
WR
Function'
0
1
0
0
0
1
X
1
0
0
0'
1
0
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write hito Data Register
Data Bus is three-stated
X
inter
AP-116
phase is sent to the 8272 the execution phase automatically starts. In a similar fashion, when the last byte of
data is read from the 8272 in the result phase, the command is automatically ended and the 8272 is ready for a
new command. A command may be aborted by simply
raising the terminal count signal (pin 16). This is a convenient means of ensuring that the processor may always gain control of the 8272 (even if the disk system
hangs up in an abnormal manner).
Table 4. Main Status Register Bit Definitions
Bit
Numbe'r
Symbol
Description
0
DoB
DISK DRIVE 0 BUSY: Disk
Drive 0 is in the Seek mode.
1
D1B
DISK DRIVE 1 BUSY: Disk
Drive 1 is in the Seek mode.
2
D2B
DISK DRIVE 2 BUSY: Disk
Drive 2 is in the Seek mode.
3
D3B
DISK DRIVE 3 BUSY: Disk
Drive 3 is in the Seek mode.
4
GB
FDC BUSY: A read or write
command is in process.
5
NOM
NON-DMA MODE: The
FOG is in the non-DMA
mode when this bit is high.
This bit is set only during
the execution phase of
commands in the non-DMA
mode. Transition to a low
level indicates that the
execution phase has ended.
6
010
DATA INPUT/OUTPUT:
Indicates the direction of a
data transfer between the
FOG and the Data Register.
When 010 is high, data is
read from the Data Register
by the processor; when 010
is low, data is written from
the processor to the Data
Register.
7
ROM
REQUEST FOR MASTER:
Indicates that the Data
Register is read to send
data to, or receive data
from, the processor.
It is important to note that during the result phase all
bytes shown.in Table 5 must be read. The Read Data
command, for example, has seven bytes of data in the
result phase. All seven bytes must be read in order to
successfully complete the Read Data command. The
8272 will not accept a new command until all seven
bytes have been read. The number of command and
result bytes varies from command-to-command.
In order to read data from, or write data to, the Data
Register during the command and result phases, the
system processor must examine the Main Status Register to determine if the Data Register is available. The
DIO (bit 6) and RQM (bit 7) flags in the Main Status
Register must be low and high, respectively, before
each byte of the command word may be written into
the 8272. Many of the commands require multiple
bytes, and as a result, the Main Status Register must be
read prior to each byte transfer to the 8272. To read
status bytes during the result phase, DID and RQM in
the Main Status Register must both be high. Note,
checking the Main Status Register in this manner before each byte transfer to/from tqe 8272 is required
only in the command and result phases, and is NOT
required during the execution phase.
Execution Phase
All data transfers to (or from) the floppy drive occur
during the execution phase. The 8272 has two primary
modes of operation for data transfers (selected by the
specify command):
1. DMA mode
2. non-DMA mode
Command/Result Phases
Table 5 lists the 8272 command set. For each of the
fifteen commands, command and result phase data
transfers are listed. A list of abbreviations used in the
table is given in Table 6, and the contents of the result
status registers (STO-ST3) are illustrated in Table 7.
In the DMAmode, DRQ (DMA Request)'is activated
for each transfers request. The DMA controller re~nds to DRQ with DACK (DMA Acknowledge) and
RD (for read commands) or WR (for write commands). DRQ is reset by the FDC during the transfer.
INT is activated after the last data transfer, indicating
the completion of the execution phase, and the beginning of the result phase. In the DMA mode, the terminal count (TC/EOP) output of the DMA controller
should be connected to the 8272 TC input to properly
terminate disk data transfer commands.
The bytes of data which are sent to the 8272 during the
command phase, and are readout of the 8272 in the
result phase, must occur in the order shown in Table 5.
That is, the command code must be sent first and the
other bytes. sent in the prescribed sequence. All bytes of
the command and result phases must be read/written
as described. After the last byte of data in the command
7-99
inter
AP-116
Table 5. 8272 Command Set
DATA BUS
PHASE
AIW 10-,
DATA BUS
" " " '3 " "
, ,
Dol
REMARKS
PHASE
AIW
0-, Do
READ DATA
Command
W
W
W
W
W
W
W
W
W
M1 MFM SK 0
0
0
0
0
0
0
_____ C
Command Codes
Command
Sector 10 information
prior to Command
execution
H
R
~~--
Execution
Resull
Data transfer
between the FOO
and the main-system
A
STO
ST,
ST2
C
H
R
A
A
R
R
W
W
W
W
W
W
W
W
W
0
0
, ,
0
0
0
0
0
C
H
R
-
N
EC'
GPl
OTl
---
R
R
R
R
R
R
Resull
W
W
W
W
W
W
W
W
W
$ector 10 information
prior to Command
execution
I
---Data Iransfer
between the FOD
and the main-system.
FOe reads the
complete track
A
STO
ST'
ST2
C
H
R
R
N
R
R
R
R
----
-------
W
W
0 MFM 0
0
0
0
,
0
0
Sector 10 information
0
,
0
0
HDS OS1 OSO
N
MT MFM
0
0
0
0
0
0
,
,
0
0
0
HOS OS1 OSO
R
N
EOT
GPl
OTl
-----
A
A
A
A
A
----
STO
ST'
ST2
C
H
-
-
R
W
W
W
W
MT MFM
0
0
-
0
0
,
0
0
0
---
,
0
0
HOS OS1 DSO
STO
ST'
ST2
- _C __
_- -
R
R
N
R
,
0
HOS OSl OSO
-
- N
SC
_ _ GPl
Bytes/Sector
$ectorsITrack
Gap 3
Filter Byte
0
STO
ST'
ST2
C __
R
-- -
H
A
N
R
$ector 'O informalion
after Command
execution
SCAN EQUAL
Command
W
W
W
W
W
W
W
W
W
Command Codes
Result
Stalus informaUon
after Command
execution
-
MT MFM SK
0
0
0
,
0
0
0
-- ---
,
0
0
HOS OS1 050
In this case, the 10
information has no
meaning
Command Codes
Sector 10 information
prior to Command
execution
C
H
R
N
EOT
GPl
STP
Stalus information
after Command
execution
--Data compared
between the FOO
and the main-system
R
R
R
R
A
A
Seclar 10 irdormalion
after Command
execution
Command Codes
FOC formats an
entire track
A
A
A
~
H_~
0
----
R
Data transfer
between the FDD
and the main.system
A
, ,
0
0
Execution
Execution
R
R
R
0 MFM 0
0
0
0
R
Sector 10 information
prior to Command
execulion
C
___ H
A
N _ _~
EOT
GPl
OTl
A
Result
Status information
after Command
execution
-
W
W
W
W
W
W
Execution
---
N
Sector 10 informaflon
during Execution
Phase
FORMAT A TRACK
---
WRITE DELETED DATA
W
W
W
W
W
A
A
$ector 10 information
prior to Command
execution
C
H
Slatus information
alter Command
execution
STO
ST'
ST2
C
H
A
N
A
A
R
Command
Command Codes
Command Codes
The first correct ID
information on the
track is stored in
Data Register
R
R
$ector 10 informalion
after Command
execution
R
Status information
after Command
el(8cution
after Command
execution
R
READ 10
Command
Result
Data transler
between the main·
system and the FDD
R
R
Re$ull
Command Codes
Status information
after Command
execulion
STO
_ _ _ _ ST'
ST2
C
H
Execution
Command
Sector 10 information
prior to Command
execution
Execution
WAITE DATA
Result
A
N
EOT
GPl
OTl
Command Codes
HOS DS1 050
-----
Data transfer
between the FOD
and the main-system
R
Command
0
I ••MA•• S
conlents from the
physical index
mark to EOT
HOS OS1 080
0
Execution
Result
0
Do
execulion
Sector 10 information
after command
execution
N
M1 MFM SK
0
0
0
0
C
_____ H
"
,
Execution
READ DELETED DATA
Command
W
W
W
W
W
W
W
W
W
0 MFM SK
0
0
0
Status information
after Command
----
R
A
Do
READ A TRACK
0
HOS OS1 050
_ _ ~N
EOT
GPl
OTl
'. '. '3
R
-----
- --
STO
ST,
ST2
--C
H ____
__ R
__ N
----
Status information
after Command
execulion
Sector 10 information
alter Command
execution
207875-18
NOTE:
1. Ao = 1 for all operations.
7-100
inter
AP-116
Table 5. 8272 Command Set (Continued)
DATA BUS
PHASE
PHASE
R/W
I
I Dr
DATA BUS
De
SCAN LOW OR eQUAL
Command
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
-
0
,
0
-
___ R
----~-----
Command
HOS OSl DSO
C_
H
-
D.
Sector 10 information
prior Command
eltecution
-
N-=-=~
EDT
D.
W
, , ,
0
Command
W
STP
Result
R
R
-----
S10 _ _ _
-
ST'
ST2
C
H
Command Codes
STO
C
Status information al
the end 01 each seek
operation about the
FDC
W
Status Information
alter Command
MT MFM SK
W
W
W
W
W
W
W
0
HLT
Command
,
W
,
0
Sector 10 information
prior Command
execution
R
Command
W
W
-
H
Status information
about the FDD
---
, ,
- - --
C
Execution
--
R
Head IS positioned
oyer proper Cylinder
on Diskette
N
INVALID
Command
W
Status information
after Command
execution
Sector 10 information
after Command
execution
Command Codes
HDS OS1 050
W
Data compared
between the FDD
and Ihe main·system
_ _ ST'
ST2
____ C
eso
ST3
SEEK
N
STO _ _
Timer Settings
Command Codes
HOS OS,
Command Codes
HOS OS1 DSO
Execution
A
R
A
R
R
A
R
• NO
W
- --- -
EDT
GPL
STP
Command Codes
_SPT _ _ .. _ H U T
SENSE DRIVE STATUS
Result
C
H __
___ R
W
W
W
after Command
execution
-
-
, , ,
0
SPECIFY
Sector 10 intormaUon
R
W
~and
execution
_ _ _ _ N_
-
Command Codes
Head retracted to
Track 0
Data compared
between tile FDD
R
R
R
R
R
R
R
IREMARKS
OS1 050
Execution
GPL _ _ _ _ _
SCAN HIGH OR EQUAL
Resull
0,
W
and the maln-svstem
Command
02
SENSE INTERRUPT STATUS
Execution
Result
03
RECALIBRATE
Command Codes
0
05
Result
-
_ _ Invalid Codes _ _ _
STO
Inyalid Command
Codes (NoOp-FOC
goes into Standby
Slate)
STO=80
(16)
207875-19
Table 6. Command/Result Parameter Abbreviations
Symbol
C
D
DSO,DS1
Description
CYLINDER ADDRESS: The currently selected cylinder address (0 to 76) on the disk.
DATA PATTERN: Tne pattern to be written in each sector data field during formatting.
DISK DRIVE SELECT:
DS1
0
0
1
1
DSO
0
1
0
1
Drive 0
Drive 1
Drive 2
Drive 3
DTL
SPECIAL SECTOR SIZE: During the execution of disk read/write commands, this
parameter is used to temporarily alter the effective disk sector size. By setting N to zero,
DTL may be used to specify a sector size from 1 to 256 bytes in length. If the actual sector
(on the diskette) is larger than DTL specifies, the remainder of the actual s~ctor is not
passed to the system during read commands; during write commands, the remainder of
the actual sector is written with all-zeroes bytes. DTL should be set to FF hexadecimal
when N is not zero.
EOT
END OF TRACK: The final sector number of the current track.
7-101
AP-116
Table 6. Command/Result Parameter Abbreviations (Continued)
Symbol
GPL
H
Description
GAP LENGTH: The gap 3 size. (Gap 3 is the space between sectors excluding the VCO
synchronization field as defined in section 3.)
HEAD ADDRES~:Selected head: 0 or 1 (disk side 0 or 1, respectively) as encoded in the
sector 10 field.
HLT
HEAD LOAD TIME: Defines the time interval that the FOC waits after loading the head
before initiating a read or write operation. Programmable from 2 to 254 milliseconds (in
increments of 2 ms).
HUT
HEAD UNLOAD TIME: Defines the time interval from the end of the execution phase (of a
read or write command) until the head is unloaded. Programmable from 16 to 240
milliseconds (in increments of 16 ms).
MFM
MFM/FM MODE SELECTOR: Selects MFM double-density recording mode when high,
FM single-density mode when low.
MT
N
MUTLI-TRACK SELECTOR: When set, this flag selects the multi-track operating mode. In
this mode (used only with dual-sided disks), the FOC treats a complete cylinder (under
both read/write head 0 and read/write head 1) as a single track. The FOC operates as if
this expanded track started at the first sector under head 0 and ended at the last sector
under head 1. With this flag set (high), a multi-sector read operation will automatically
continue to the first sector under head 1 when FOG finishes operating on the last sector
under head o.
SECTOR SIZE: The number of data bytes within a sector. (See Table 9.)
NO
NON-DMA MODE FLAG: When set (high), this flag indicates that the FOC is to operate in
the non-OMA mode. In this mode, the processor is interrupted for each data transfer.
.When low, the FOC interfaces to a OMA controller by means of the ORQ and OACK
signals.
R
SECTOR ADDRESS: Specifies the sector number to be read or written. In mUlti-sector
transfers, this parameter specifies the sector number of first sector to be read or written.
SC
NUMBER OF SECTORS PER TRACK: Specifies the number of sectors per track to be
initialized by the Format Track command.
SK
SKIP FLAG: When this flag is set, sectors containing deleted data address marks will
automatically be skipped during the execution of multi-sector Read Data or Scan
commands. In the same manner, a sector containing a data address mark will
automatically be. skipped during the execution of a multi-sector Read Oelected Data
command.
SRT
STEP RATE INTEf;lVAL: Defines the time interval between step pulses issued by the FOG
(track-to-track access time). Programmable from 1 to 16 milliseconds (in increments of 1
ms).
7-102
inter
AP-116
Table 6. Command/Result Parameter Abbreviations (Continued)
Symbol
Description
5TO,5T3
5T2,ST3
STATUS REGISTER 0-3: Registers within the FDC that store status information after a
command has been executed. This status information is available to the processor during
the Result Phase after command execution. These registers may only be read after a
command has been executed (in the exact order shown in Table 5 for each command).
These registers should not be confused with the Main Status Register.
STP
SCAN SECTOR INCREMENT: During Scan operations, this parameter is added to the
current sector number in order to determine the next sector to be scanned.
Table 7. Status Register Definitions
Bit
Number
Symbol
Description
Status Register 0
7,6
IC
INTERRUPT CODE:
00- Normal termination of command. The specified command was properly
executed and completed without error.
01- Abnormal termination of command. Command execution was started but
could not be successfully completed.
1O-Invalid command. The requested command could not be executed.
11- Abnormal termination. During command execution, the disk drive ready
signal changed state.
5
SE
SEEK END: This flag is set (high) when the FDC has completed the Seek
command and the read/write head is positioned over the correct cylinder.
4
EC
EQUIPMENT CHECK ERROR: This flag is set (high) if a fault signal is received
from the disk drive or if the track 0 signal fails to become active after 77 step
pulses (Recalibrate command).
3
NR
NOT READY ERORR: This flag is set if a read or write command is issued and
either the drive is not ready or the command specifies side 1 (head 1) of a singlesided disk.
2
H
1,0
DS1,DSO
HEAD ADDRESS: The head address at the time of the interrupt.
DRIVE SELECT: The number of the drive selected at the time of the interrupt.
Status Register 1
7
EN
Not used. This bit is always low.
6
5
END OF TRACK ERROR: This flag is set if the FDC attempts to access a sector
beyond the final sector of the track.
DE
DATA ERROR: Set when the FDC detects a CRC error in either the 10 field or the
data field of a sector.
7-103
Ap·116
Table 7. Status Register Definitions (Continued)
Bit
Number
Symbol
Description
Status Register 1 (Continued)
4
OR
3
OVERRUN ERROR: Set (during data transfers) if the FDC does not receive DMA
or processor service within the specified time interval.
Not used. This bit is always low.
2
NO
SECTOR NOT FOUND ERROR: This flag is set by any of the following conditions.
a) The FDC cannot locate the sector specified in the Read Data, Read
Delected Data, or Scan command.
b) The FDC cannot locate the staring sector specified in the Read Track
command.
c) The FDC cannot read the 10 field without error during a Read 10 command.
1
NW
WRITE PROTECT ERROR: This flag is set if the FOC detects a write protect
signal from the disk drive during the execution of a Write Oata, Write Oeleted Oata,
or Format Track command.
0
MA
MISSING ADDRESS MARK ERROR: This flag is set by either of the following
conditions:
a) The FOC cann()t detect the 10 address mark on the specified track (after
two occurrences of the physical index mark).
b)The FOC cannot detect the data address mark or deleted data address
mark on the specified track. (See also the MO bit of Status Register 2.)
Status Register 2
7
NOT USED: This bit is always low.
6
CM
CONTROL MARK: This flag is set when the FDC encounters one of the following
conditions:
a) A deleted data address mark during the execution of a Read Oata or Scan
command.
b) A data address mark during the execution ora Read Oeleted Oata
command.
5
00
DATA ERROR: Set (high) when the FOC detects a CRC error in a sector data
field. This flag is not set when a CRC ero( is detected in the 10 field.
4
WC
CYLINDER ADDRESS ERROR: Set when the cylinder address from the disk
sector 10 field is different from the current cylinder address mainta:ined within the
FOC.
3
SH
SCAN HIT: Set during the execution of the Scan command if the scan condition is
satisfied.
2
SN
SCAN NOT SATISFIED: Set during execution of the Scan command if the FOC
cannot locate a sector on the specified cylinder that satisfies the scan condition.
1
BC
BAD TRACK ERROR: Set when the cylinder address from the disk sector 10 field
is FF hexadecimal and this cylinder address is different from the current cylinder
address maintained within the FOC. This all "ones" cylinder number indicates a
bad track (one containing hard errors) according to the IBM soft-sectored format
specifications.
0
MO
MISSING DATA ADDRESS MARK ERROR: Set if the FOC cannot detect a data
address mark or deleted data address mark on the specified track.
7-104
inter
AP-116
Table 7. Status Register Definitions (Continued)
Bit
Number
Symbol
Description
Status Register 3
7
FT
FAULT: This flag indicates the status of the fault signal from the selected disk
drive.
6
WP
WRITE PROTECTED: This flag indicates the status of the write protect signal
from the selected disk drive.
5
ROY
READY: This flag indicates the status of the ready signal from the selected disk
drive.
4
TO
TRACK 0: This flag indicates the status of the track 0 signal from the selected
disk drive.
3
TS
TWO-SIDED: This flag indicates the status of the two-sided signal from the
selected disk drive.
2
H
1,0
DS1,OSO
HEAD ADDRESS: This flag indicates the status of the side select signal for the
currently selected disk drive.
DRIVE SELECT: Indicates the currently selected disk drive number.
In the non-DMA mode, transfers requests are indicated
by activation of both the INT output signal and the
RQM flag (bit 7) in the Main Status Register. INT can
be used for interrupt-driven systems and RQM can be
used for polled systems. The system processor must respond to the transfer request by reading data from (activating RD), or writing data to (activating WR), the
FDC. This response removes the transfer request (INT
and RQM are set inactive). After completing the last
transfer, the 8272 activates the INT output to indicate
the beginning of the result phase. In the non-DMA
mode, the processor must activate the TC signal to the
FDC (normally by means of an I/O port) after the
transfer request for the last data byte has been received
(by the processor) and before the appropriate data byte
has been read from (or written to) the FDC.
In either mode of operation (DMA or non-DMA), the
execution phase ends when a terminal count signal is
sensed or when the last sector on a track (the EOT
parameter-Table 5) has been read or written. In addition, if the disk drive is in a "not ready" state at the
beginning of the execution phase, the "not ready" flag
(bit 3 in Status Register 0) is set (high) and the command is terminated.
If a fault signal is received from the disk drive at the
end of a write operation (Write Data, Write Deleted
Data, or Format), the FDC sets the "equipment check"
flag (bit 4 in Status Register 0), and terminates the
command after setting the interrupt code (bits 7 and 6
of Status Register 0) to "01" (bit 7 low, bit 6 high).
Multi-Sector and Multi-Track Transfers
During disk read/write transfers (Read Data, Write
Data, Read Deleted Data, and Write Deleted Data),
the FDC will continue to transfer data from sequential
sectors until the TC input is sensed. In the DMA mode,
the TC input is normally connected to the TC/EOP
(terminal count) output of the DMA controller. In the
non-DMA mode, the processor directly controls the
FDC TC input as previously described. Once the TC
input is received, the FDC stops requesting data transfers (from the system processor or DMA controller).
The FDC, however, continues to read data from, or
write data to, the floppy disk until the end of the current disk sector. During a disk read operation, the data
read from the disk (after reception of the TC input) is
discarded, but the data CRC is checked for errors; during a disk write operation, the remainder of the sector is
filled with all-zero bytes.
If the TC signal is not received before the last byte of
the current sector has been transferred to/from the system, the FDC increments the sector number by one and
initiates a read or write command for this new disk
sector.
The FDC is also designed to operate in a multi-track
mode for dual-sided disks. In the multi-track mode
(specified by means of the MT flag in the command
byte-Table 5) the FDC will automatically increment
the head address (from 0 to 1) when the last sector (on
the track under head 0) has been read or written. Reading or writing is then continued on the first sector (sector 1) of head 1.
7-105
AP-116
bit). When this bit is high the non-DMA mode is selected; when ND is low, the DMA mode is selected.
Drive Status Polling
After the power-on reset, the 8272 automatically enters
a drive status polling mode. If a change in drive status
is detected (all drives are assumed to be "not ready" at
power-on), an interrupt is generated. The 8272 continues this status polling between command executions
(and between step pulses in the Seek command). In this
manner, the 8272 automatically notifies. the system
processor when a floppy disk is inserted, removed, or
changed by the operator.
Sense Drive Status
This command may be used by the processor whenever
it wishes to obtain the status of the disk drives. Status
Register 3 (returned during the result phase) contains
the drive status information as described in Table 7.
Sense Interrupt Status
Command Details
During the command phase, the Main Status Register
must be polled by the CPU before each byte is written
into the Data Register. The DID (bit 6) and RQM (bit
7) flags in the Main Status Register must be low and
high, respectively, before each byte of the command
may be written into the 8272. The beginning of the
execution phase for any of these commands will cause
DIO to be set high and RQM to be set low.
An interrupt signal is generated by the FDC when one
or more of the following events occurs:
1) The FDC enters the result phase for:
a) Read Data command
b) Read Track command
c) Read ID command
d) Read Deleted Data command
e) Write Data command
The following paragraphs describe the fifteen FDC
commands in detail.
Specify
The Specify command is used prior to performing any
disk operations (including the formatting of a new disk)
to define drive/FDC operating characteristics. The
Specify command parameters set the values for three
internal timers:
I. Head Load Time (HLT)-This seven-bit value defines the time interval that the FDC waits after
loading the head before initiating a read or write operation .. This timer is programmable from 2 to 254
milliseconds in increments of 2 ms.
2. Head Unload Time (HUT)-This four-bit value defines the time from the end of the execution phase (of
a read or write command) until the head is unloaded.
This timer is programmable from 16 to 240 milliseconds in increments of 16 ms. If the processor issues
another command before the head unloads, the head
will remain loaded and the head load wait will be
eliminated.
t) Format Track command
g) Write Deleted Data command
h) Scan commands
2) The ready signal from one of the disk drives changes
state.
3) A Seek or Recalibrate command completes operation.
4) The FDC requires a data' transfer during the execution phase of a command in thenon-DMA mode.
Interrupts caused by reasons (l) and (4) above occur
during normal command operations and are easily discernible by the processor. However, interrupts caused
by reasons (2) and (3) above are uniquely identified
with the aid of the Sense Interrupt Status command.
This command, when issued, resets the interrupt signal
and by means of bits 5, 6, and 7 of Status Register 0
(returned during the result phase) identifies the cause of
the interrupf (see Table 8).
3. Step Rate Time (SRT)-This four-bit value defines
the time interval between step pulses issued by the
FDC (track-to-track access time). This timer is programmable from I to 16 milliseconds in increments
of I ms.
The time intervals mentioned above are a direct function of the FDC clock (CLK on pin 19). Times indicated above are for an 8 MHz clock.
The Specify command also indicates the choice of
DMA or non-DMA operation (by means of the ND
7-106
Table 8. Interrupt Codes
Seek End Interrupt Code
Bit 5
Cause
BitS
Bit7
0
1
1
Read Line changed
state, either polarity
1
0
0
Normal Termination
of Seek or Recalibrate
Command
1
1
0
Abnormal Termination
of Seek or Recalibrate
Command
inter
AP-116
Neither the Seek nor the Recalibrate command has a
result phase. Therefore, it is mandatory to use the Sense
Interrupt Status Command after these commands to
effectively terminate them and to provide verification of
the disk head position.
When an interrupt is received by the processor, the
FOC busy flag (bit 4) and the non-DMA (bit 5) may be
used to distinguish the above interrupt causes:
bit 5
bit 4
o
0
o
Asynchronous event-(2) or (3) above
Result phase-(1) above
Data transfer required-(4) above
A single interrupt request to the processor may, in fact,
be caused by more than one of the above events. The
processor should continue to issue Sense Interrupt
Status commands (and service the resulting conditions)
until an invalid command code is received. In this manner, all "hidden" interrupts are serviced.
Recalibrate
This command causes the read/write head of the disk
drive to retract tothe track 0 position. The FOC clears
the contents of its internal cylinder counter, and checks
the status of the track 0 signal from the disk drive. As
long as the track 0 signal is low, the direction signal
remains high and step pulses are issued. When the track
o signal goes high, the seek end flag (in Status Register
0) is set (high) and the command is terminated. If the
track 0 signal is still low after 77 step pulses have been
issued, the seek end and equipment check flags (in
Status Register 0) are both set and the Recalibrate command is terminated.
Recalibrate commands for multiple drives can be overlapped in the same manner that Seek commands are
overlapped.
Format Track
Seek
The Seek command causes the drive's read/write head
to be positioned over the specified cylinder. The Foe
determines the difference between the current cylinder
address and the desired (specified) address, and issues
the appropriate number of step pulses. If the desired
cylinder address is larger than the current address, the
direction signal (LeT/DIR, pin 38) is set high (stepin); the direction signal is set low (step-out) if the desired cylinder address is less than the current address.
No head movement occurs (no step pulses are issued) if
the desired cylinder is the same as the current cylinder.
The rate at which step pulses are issued is controlled by
the step rate time (SRT) in the Specify command. After
each step pulse is issued, the desired cylinder address is
compared against the current cylinder address. When
the cylinder addresses are equal, the "seek end" flag
(bit 5 in Status Register 0) is set (high) and the command is terminated. If the disk drive becomes "not
ready" during the seek operation, the "not ready" flag
(in Status Register 0) is set (high) and the. command is
terminated.
The Format Track command formats or "initializes" a
track on a floppy disk by writing the ID field, gaps, and .
address marks for each sector. Before issuing the Format command, the Seek command must be used to position the read/write head over the correct cylinder. In
addition, a table of ID field values (cylinder, head, and
sector addresses and sector length code) must be prepared before the command is executed. During command execution, the FDC accesses the table and, using
the values supplied, writes each sector on the track. The
10 field address mark originates from the FOC and is
written automatically as the first byte of each sector's
ID field. The cylinder, head, and sector addresses are
taken, in order, from the table. The ID field eRe character (derived from the data written in the first five
bytes) is written as the last two bytes of the ID field.
Gaps are written automatically by the FDC, with the
length of the variable gap determined by one of the
Format command parameters.
The data field address mark is generated by the FDC
and is written automatically as the first byte of the data
field. The data pattern specified in the command phase
is written into each data byte of each sector. A eRC
character is. derived from the data address mark and
the data written in the sector's data field. The two eRC
bytes are appended to the last data byte.
During the command phase of the Seek operation the
FDC is in the FDC busy state, but during the execution
phase it is in the non-busy state. While the FDC is in
the non-busy state, another Seek command may be isThe formatting of a track begins at the physical index
sued.. In this manner parallel seek operations may be in
mari(.. As previously mentioned, the order of sector asoperation on up to four floppy disk drives at o~ce. The
signment is taken directly from the formatting table.
Main Status Register contains a flag for each dnve (TaFour entries are required for each sector: a cylinder
ble 4) that indicates whether the associated drive is curaddress, a head address, a sector address, and a sector
rently operating in the seek mode. When a drive has
length code. The cylinder address in the ID field should
completed a seek operation, the FDe generates an
be equal to the cylinder address of the track currently
interrupt. In response to this interrupt, the system softbeing formatted.
ware must issue a Sense Interrupt Status command.
During the result phase of this command, Status Register 0 (containing the drive number in bits 0 and 1) is
read by the processor.
7-107
AP-116
The sector addresses must be unique (no two equal).
The order of the sector entries in the table is the se~
quence in which sector numbers appear on thetrack
when it is formatted. 'The number of entry sets (cylinder, head, and sector address and sector length code)
must equal the number of sectors allocated to the track
(spe7ified in the command phase).
Since the sector address is supplied, in order, for each
sector, tracks can be fonhatted sequentially (the first
sector following the index mark is assigned sector address 1, the adjacent sector is assigned sector address2,
and so on) or sector numbers can be interleaved ,(see
section 3) on a track.
Table 9 lists recommended gap sizes 'and sectors/track
for various sector sizes.
Read Data
Nine (9) bytes are required to complete the command
phase specification forthe Read Data command. During the execution phase, the FDe loads the head (if it is
in the unloaded state), waits the specified head load
time (defined in the Specify command), and begins
reading ID address marks and ID fields. When the requested sector address compares with the sector address read from the disk, the FOe outputs data (from
the data field) byte-by-byte to the system. The Read
Data command automatically operates in the multi-sector mode described earlier. In addition, multi-track operation may be specified by means of the MT command
flag (Table.5). The amount of data that can be transferred with a single command to the,FDe depends on
the multi-track flag, the recording density flag, and the
number of bytes per sector.
During the execution of read' and write commands, the
special sector size parameter (DTL) is used to temporarily alter the effective disk sector size. By setting the
sector size code (N) to zero, DTL may be used to specify a sector size from 1 to 256 bytes in length. If the
actual sector (on the disk) is larger than DTL specifies,
only the number of bytes specified by the DTL parameter are passed to the system; the remainder of the actual
disk sector is not, transferred (although the data is
checked for eRe errors). Multi-sector read operations
are performed.in the same manner as they are when the
sector size code is non-zero. (The Nand DTL parameters are always present in the command sequence. DTL
should be set to FF hexadecimal when N is not zero.)
If the FDe detects the physical index mark twice without finding the requested sector, the FDe sets the "sector not found error" flag (bit 2 in Status Register 1) and
terminates 'the Read Data command. The interrupt
code (bits 7 and .6 of Status Register 0) is set to "01."
Note that the FDe searches for each sector in a multisector operation. Therefore, a "sector not found'" error
may occur after successful transfer of one or more preceding sectors. This error could occur if a particular
sector number was not included when the track was
first formatted or if a hard error on the disk has invalidated a sector ID field.
After reading the ID field and data field in each sector,
the FOe checks the eRe bytes. If a read error is detected (incorrect eRe in the ID field),-the FOe sets
the "data error" flag in Status Register 1;· if a eRe
error occurs in the .data field; the FDe sets the "data
error" flag in Status Register 2. In either error condition, the FDe terminates· the Read Data command.
The interrupt code (bits 7 and 6 in Status Register 0) is
set to "01."
If the FDe reads a deleted data address mark from the
disk, and the skip flag (specified during the command
phase) is not set, the FOe sets the "control mark" flag
(bit 6 in Status Register 2) and terminates the Read
Data command (after reading'all the data in the sector).
If the skip flag is set, the FDe skips the sector with the
deleted data address mark and reads the next sector.
Thus, the skip flag may be used to cause the FOe to
ignore deleted data sectors during a multi-sector read
operation.
Table 9. Sector Size Relationships
Sector Size
N
Sector Size
Code
SC
Sectorsl
Track
GpL(1)
Gap3
Length
GpL(2)
Gap 3
Length
FM Mode
128 bytes/Sector
256
512
00
01
02
1A(16)
OF(16)
08 '
07(16)
OE(16)
1B(16)
1B(16)
2A(16)
3A(16)
IBM Diskette 1
IBM Diskette 2
MFM Mode
256
512
1024
01
02
03
1A(16)
OF(16)
08
OE(16)
1B(16)
35('16)
36(16)
54(16)
74(16)
iBM Diskette 2D
Format
Remarks
IBM Diskette 2D
NOTES:
1. Suggested values of GPL in Read or Write commands to avoid splice point between data field and ID field of contiguous
sectors,
2. Suggested values of GPL in Format command.
7-108
inter
AP-116
During disk data transfers between the FDe and the
system, the FDe must be serviced by the system (processor or DMA controller) every 27 f-Ls in the FM mode,
and every 13 f-Ls in the MFM mode. If the FDe is not
serviced within this interval, the "overrun error" flag
(bit 4 in Status Register 1) is set and the Read Data
command is terminated.
If the processor terminates a read (or write) operation
in the FDe, the ID information in the result phase is
dependent upon the state of the multi-track flag and
end of track byte. Table 11 shows the values for e, H,
R, and N, when the processor terminates the command.
Write Data
Nine (9) bytes are required to complete the command
phase specification for the Write Data command. During the execution phase the FDe loads the head (if it is
in the unloaded state), waits the specified head load
time (defined by the Specify command), and begins
reading sector ID fields. When the requested sector address compares with the sector address read from the
disk, the FDe reads data from the processor one byte
at a time via the data bus and outputs the data to the
data field of that sector. The eRe is computed on this
data and two eRe bytes are written at the end of the
data field.
The FDe reads the ID field of each sector and checks
the eRe bytes. If the FDe detects a read error (incorrect eRe) in one of the ID fields, it sets the "data
error" flag (bit 5 in Status Register 1) and terminates
the Write Data command. The interrupt code (bits 7
and 6 in Status Register 0) is set to "01."
The Write Data command operates in much the same
manner as the Read Data command. The following
items are the same; refer to the Read Data command
for details:
• Multi-sector and Multi-track operation
• Data transfer capacity
• "End of track error" flag
• "Sector not found error" flag
• "Data error" flag
• Head unload time interval
• ID information when the processor terminates the
command (see Table 11)
• Definition of DTL when N = 0 and when N =1= 0
During the Write Data execution phase, data transfers
between the processor and FDe must. occur every 31
f-Ls in the FM mode, and every 15 f-Ls in the MFM
mode. If the time interval between data transfers is
longer than this, the FDe sets the "overrun error" flag
(bit 4 in Status Register 1) and terminates the Write
Data command.
Read Deleted Data
This command operates in almost the same manner as
the Read Data command operates. The only difference
involves the treatment of the data address mark and the
skip flag. When the FOe detects a data address mark
at the beginning of a data field (and the skip flag is not
set), the FDe reads all the data in the sector, sets the
"control mark" flag (bit 6 in Status Register 2), and
terminates the command. If the skip flag is set, the
FDe skips the sector with the data address mark and
continues reading at the next sector. Thus, the skip flag
may be used to cause the FDe to read only deleted data
sectors during a multi-sector read operation.
Write Deleted Data
This command operates in the same manner as the
Write Data command operates except that a deleted
data address mark is written at the beginning of the
data field instead of the normal data address mark.
This command is used to mark a bad sector (containing
a hard error) on the floppy disk.
Read Track
The Read Track command is similar to the Read Data
command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering the physicai index mark, the
FDe starts reading all data fields on the track as continuous blocks of data. If the FDe finds an error in the
ID field or data field eRe check bytes, it continues to
. read data from the track. The FOe compares the ID
information read from each sector with the values specified during the command phase. If the specified ID
field information is not found on the track, the "sector
not found error" flag (in Status Register 1) is set. Multitrack and skip operations are not allowed with this
command.
This command terminates when the last sector on the
track has been read. (The number of sectors on the
track is specified by the end of track parameter byte
during the command phase.) If the FDe does not find
an ID address mark on the disk after it encounters the
physical index mark for the second time; it sets the
"missing address mark error"flag (bit 0 in Status Register 1) and terminates the command. The interrupt
code (bits 7 and 6 of Status Register 0) is set to. "01."
7-109
inter
AP-116
Table 10. Scan Status Codes
ReadlD
The Read IDcommand transfers (reads) the first correct ID field from the current disk track (following the
physical index mark) to the processor. If no correct ID
address mark is found on the track, the "missing address mark error" flag is set (bit 0 in Status Register 1).
If no data mark is found on the track, the "sector not
found error" flag is also set (bit 2 in Status Register 1).
Either error condition causes the command to be termi.
nated.
Scan Commands
The Scan commands allow the data being read from the
disk to be compared against data supplied by the system (by the processor in non-DMA mode, and by the
DMA controller in DMA mode). The FDe compares
the data on a byte-by-byte basis, and searches for a
sector of data that meets the conditions of "disk data
equal to system data", "disk data less than or equal to
system data", or "disk data greater than or equal to
system data". Simple binary (ones complement) arithmetic is used for comparison (FF = largest nuinber, 00
= smallest number). If, after a complete sector of data
is compared, the conditions are not met, the sector
number is incremented by the scan sector increment
(specified in the command phase), and the scan operation is continued. The scan operation continues until
one of the following conditions occurs; the conditions
for scan are met (equal, low, or high), the last sector on
the track is reached, or the terminal count signal is
received.
.
If the conditions for scan are met, the FDe sets the
"scan hit" flag (bit 3 in Status Register 2) and terminates the Scan command. If the conditions for scan are
not met between the starting sector and the last sector
on the track (specified in the command phase), the
FDe sets the "scan not satisfied" flag (bit 2 in Status
Register 2) and terminates the Scan command. The receipt of a terminal count signal from the processor or
DMA controller during the scan operation will cause
. the FDe to complete the comparison of the particular
byte which is in process, and to termiante the command. Table 10 shows the status of the "scan hit" and
"scan not satisfied" flags under various scan termination conditions.
If the FDe encounters a deleted data address mark in
one ofthe sectors and the skip flag is low, it regards the
sector as the last sector on the cylinder, sets the "control mark" flag (bit 6 in Status Register 2) and terminates the command. If the skip flag is high, the FOe
skips the sector with the deleted address mark, and
reads the next sector. In this case, the FOe also sets the
Command
. Status Register 2
Blt2 = SN Blt3
Scan Equal
= SH
Comments
0
1
1
0
DFDD
Scan Low
or Equal
0
0
1
1
0
0
DFDD
Scan High
or Equal
0
0
1
1
0
0
= Dprocessor
DFDD 0;6 Dprocessor
DFDD
= Dprocessor
< Dprocessor
DFDD
»
DFDD
= Dprocessor
DFDD
»
Dprocessor
Dprocessor
DFDD ~ Dprocessor
'control mark" flag (bit 6 in Stauts Register 2) in order
to show that a deleted seCtor had been encountered.
NOTE:
During scan command execution, the last sector on
the track must be read for the command to terminate
properly. For example if the scan sector increment is
set to 2, the end of track parameter is set to 26, and
the scan begins at sector 21, sectors 21, 23, and 25 will
. be scanned. The next sector, 27 will not be found on
the track and an abnormal command termination will
occur. The command would be completed in a normal
manner if either a) the scan had started at sector 20 or
b) the end of track parameter had been set to 25.
During the Scan command, data is supplied by the
processor or DMA controller for comparison against
the data read from the disk. In order to avoid having
the "overrun error" flag set (bit 4 in Status Register 1);
it is necessary to have the data available in less than 27
/ks (PM Mode) or 13 /ks (MFM Mode). If an overrun
error occurs, the FOe terminates the command.
Invalid Commands
If an invalid (undefined) command is sent to the FDe,
the FDe will terminate the command. No interrupt is
generated by the 8272 during this condition. Bit 6 and
bit 7 (DIO and RQM) in the Main Status Register are
both set indicating to the processor that the 8272 is in
the result phase and the contents of Status Register 0
must be read. When the processor reads Status Register
o it will find an 80H code indicating that an invalid
command was received.
A Sense Interrupt Status command must be sent after a
. Seek or Recalibrate interrupt; otherwise the FOe will
consider the next command to be an invalid command.
Also, when the last "hidden" interrupt has been serviced, further Sense Interrupt Status commands will re.
sult in invalid command codes.
7-110
intJ
AP-116
Table 11 ID Information When Processor Terminates Command
MT
EOT
1A
OF
08
1A
OF
0
08
1A
OF
08
1A
OF
08
1A
OF
08
1A
OF
1
08
1A
OF
08
1A
OF
08
10 Information at Result Phase
Final Sector Transferred
to Processor
C
H
R
N
NC
NC
R + 1
NC
C+1
NC
R = 01
NC
NC
NC
R + 1
NC
C+ 1
NC
R = 01
NC
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
NC
NC
R+ 1
NC
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
NC
LSB
R = 01
NC
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
NC
NC
R + 1
NC
C+ 1
LSB
R = 01
NC
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side 0
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
NOTES:
1. NC (No Change): The same value as the one at the beginning of command execution.
2. LSB (Least Significant Bit): The least significant bit of H is complemented.
In some applications the user may wish to use this command as a No-Op command to place the FDC in a
stand-by or no operation state.
5.0 THE DATA SEPARATOR
As briefly discussed in Section 2, LSI disk controllers
such as the 8272 require external circuitry to generate a
data window signal. This signal is used within the FDC
to isolate the data bits contained within the READ
DATA input signal from the disk drive. (The disk
READ DATA signal is a composite signal constructed
from both clock and data information.) After isolating
the data bits from this input signal, the FDC assembles
the data bits into 8-bit bytes for transfer to the system
processor or memory.
Single Density
In a single-density (FM) recording (Figure 3), the bit
cell is 4 microseconds wide. Each bit cell contains a
clock bit at the leading edge of the cell. The data bit (if
present) is always located at the center of the cell. The
job of data separation is relatively straightforward for
single-density; simply generate a data window 2 /Ls
wide starting 1 /Ls after each clock bit.. Since every cell
has a clock bit, a fixed window reference is available for
every data bit and because the window is 2 /Ls wide, a
slightly shifted data bit will still remain within the data
window.
7-111
A single-density data separator with these specifications may be easily generated using a digital or analog
one-shot triggered by the clock bit.
AP-116
data frequency very closely-unpredictable bit shifts
leave less than 50 ns margin to the window edges.
Double-Density
Double-density (MFM) bit cells are reduced to 2 JLs (in
order to double the disk data storage capacity). Clock
bits are inserted into the data stream only if data bits
are not present in both the current and preceding bit
cells (Figure 3). The data bit (if present) still occurs at
the center of the bit cell and the clock bit (if present)
still occurs at the leading edge of the bit cell.
MFM data separation has two problems. First, only
some bit cells contain a clock bit. In this manner, MFM
encoding loses the fixed bit cell reference pulse present
in FM encoding. Second, the bit cell for MFM is onehalf the size of the bit cell for FM. This shorter bit cell
means that MRM cannot tolerate as large a playback
data-shift (as FM can tolerate) without errors.
Since most playback data-shift is predictable, the FDC
can precompensate the write data stream so that datal
clock pulses will be correctly positioned for subsequent
playback. This function is completely controlled by the
FDC and is only required for MFM recording. During
write operations, the FDC specifies an early, normal, or
late bit positioning. This timing information is specified
with respect to the FDC write clock. Early and late
timing is typically 125 ns to 250 ns before or after the
write clock transition (depending on disk drive requirements).
The data separator circuitry for double-density recording must continuously analyze the total READ DATA
stream, synchronizing its operation (window generation) with the actual clockldata bits of the data stream.
The data separation circuit must track the disk input
Phase-Locked Loop
Only an analog phase-locked loop (PLL) can provide
the reliability required for a double-density data separation circuit. (A phase-locked loop is an electronic circuit that constantly analyzes the frequency of an input
signal and locks another oscillator to that frequency.)
Using analog PLL techniques, a data separator can be
designed with ± I ns resolution (this would require a
100 MHz clock in a digital phase-locked loop). The
analog PLL determines the clock and data bit positions
by sampling each bit in the serial data stream. The
phase relationship between a data bit and the PLL generated data window is· constantly fed back to adjust the
position of the data window, enabling the PLL to track·
input data frequency changes, and thereby reliably read
previously recorded data from a floppy disk.
PLL Design
A block diagram of the phase-locked loop described in
this application note is shown in Figure 7. Basically, the
phase-locked loop operates by comparing the frequency
of the input data (from the disk drive) against the frequency of a local oscillator. The difference of these frequencies is used to increase or decrease the frequency of
the local oscillator in order to bring its frequency closer
to that of the input. The PLL synchronizes the local
r-__________________________________
~
__
~READDATA
(TO FDC)
DATA WINDOW
(TO FDC)
READ DATA
(FROM DISKETTE DRIVE)
VCO (FROM FDC)
-----------------------.1
START
LOGIC
IDLE CLAMP
MFM (FROMFD~ ---------------------~
207875-8
Figure 7. Phase-Locked Loop Data Separator
7-112
inter
AP-116
oscillator to the frequency of the input during the all
"zeroes" synchronization field on the floppy disk (immediately preceding both the ID field and the data
field.
The PLL consists of nine ICs and is located on page 3
of the schematics in the Appendix. The 8272 YCO output essentially turns the PLL circuitry on and off.
When the PLL is off, it "idles" at its center frequency.
The YCO turns the PLL on only when valid data is
being received from the disk drive. The YCO turns the
PLL on after the read/write head has been loaded and
the head load time has elapsed. The PLL is turned off
in the gap between the ID field and the data field and in
the gap after the data field (before the next sector ID
field). The GPL parameter in the FDC read and write'
commands specifies the elapsed time (number of data
bytes) that the PLL is turned off in order to blank out
discontinuities that appear in the gaps when the write
current is turned on and off. The PLL operates with
either MFM or FM input data. The MFM output from
the FDC controls the PLL operation frequency.
The PLL consists of six functional blocks as follows:
I) Pulse Shaping-A 96LS02 senses a READ DATA
pulse and provides a clean output signal to the FDC
and to the PLL Phase Comparator and Frequency
Discriminator circuitry.
2) Phase Comparator-The phase difference between
the PLL oscillator and the READ DATA input is
compared. Pump up (PU) and pump down (PD) error signals are derived from this phase difference and
output to the filter. If there is no phase difference
between the PLL oscillator and the READ DATA
input, the PU and PD pulse widths are equal. If the
READ DATA pulse occurs early, the PU duration
is shorter than the PD duration. If the data pulse
occurs late, the PU duration is longer than the PD
duration.
3) Filter-This analog circuit filters the PU and PD
pulses into an error voltage. This error voltage is
buffered by an LM358 operational amplifier.
4. PLL Oscillator-This oscillator is composed of a
74LS393, 74LS74, and 96LS02. The oscillator frequency is controlled by the error voltage output by
the filter. This oscillator also generates the data window signal to the FDC.
5. Frequency Discriminator-This logic tracks the
READ DATA input from the disk drive and discriminates between the synchronization gap for FM
recording (250 KHz) and the gap for MFM recording (500 KHz). Synchronization gaps immediately
precede address marks.
6. Start Logic-The function of this logic is to clamp
the PLL oscillator to its center frequency (2 MHz)
until the FDC YCO signal is enabled and a valid
data pattern is sensed by the frequency discriminator. The start logic (consisting of a 74LS393 and
74LS74) ensures that the PLL oscillator is started
with zero phase error.
PLL Adjustments
The PLL must be initially adjusted to operate at its
center frequency with the YCO output off and the adjustment jumper removed. The 5K timepot should be
adjusted until the frequency at the test point (Q output
of the 96LS02) is 2 MHz. The jumper should then be
replaced for normal operation.
PLL Design Details
The following paragraphs describe the operational and
design details of the phase-locked loop data separator
illustrated in the appendix. Note that the analog section
is operated from a separately filtered + 5Y supply.
Initialization
As long as the 8272 maintains a low YCO signal, the
data separator logic is "turned off'. In this state, the
PLL oscillator (96LS02) is not oscillating and therefore
the 2XBR signal is constantly low. In addition, the
pump up (PU) and pump down (PD) signals are inactive (PU low and PD high), the CNT8 signal is inactive
(low), and the filter input voltage is held at 2.5 volts by
two I Mn resistors between ground and + 5 volts.
Floppy Disk Data
The data separator freqeuncy discriminator, the input
pulse shaping circuitry, and the start logic are always
enabled and respond to rising edges of the READ
DATA signal. The rising edge of every data bit from
the disk drive triggers two pulse shaping one-shots. The
first pulse shaper generates a stable and well-defined
200 ns read data pulse for input to the 8272 and other
portions of the data separator logic. The second oneshot generates a 2.5 /-Ls data pulse that is used for input
data frequency discrimination.
The frequency discriminator operates as illustrated in
Figure 8. The 2F output signal is active (high) during
reception of valid MFM (double-density) sync fields on
the disk while the IF signal is active (high) during reception of valid FM (single-density) sync fields. A multiplexer (controlled by the 8272 MFM signal) selects
the appropriate IF or 2F signal depending on the programmed mode.
7-113
AP-116
FM BEAD DATA
--.flL-----lnL....----InL....----InL....----InL....-----JrL
FREQ DISC
2F LOW, IF HIGH DURING SYNC DATA INPUT (FM)
MFM READ DATA
'~ 2F HIGH,l F LOW DURING SYNC DATA INPUT (MFM)
FREQ
DISC~
Jl~)(
x~
)(
)(
)(
)(
)(
)(
J(
207875-9
Frequency Discriminator Sample Points to Generate 1F and 2F Signals
(a) FM Operation: One-Shot Times Out between Clock Pulses
Figure 8. Input Data Frequency Discrimination
Startup
The data separator is designed to require reception of
eight valid sync bits (one sync byte) before enabling the
PLL oscillator and attempting to synchronize with the
input data stream (see Figure 9). This delay ensures
that the PLL will not erroneously synchronize outside a
valid sync field in the data stream if the VCO signal is
enabled slightly early. The sync bit counter is asynchronously reset by the CNTEN signal when valid sync
data is not being recevied by the drive.
Once the VCO signal is active and eight sync bits have
been counted, the CNT8 signal is enabled. This signal
turns on the PLL oscillator. Note that this oscillator
starts synchronously with the rising edge of the disk
input data (becasue CNT8 is synchronous with the data
rising edge) and the oscillator also starts at its center
frequency of 2 MHz (because the LM348 filter input is
held at its center voltage of approximately 2.5 volts).
This frequency is divided by two and four to generate
the 2XBR signal (I MHz for MFM and 500 KHz for
FM).
7-114
inter
AP-116
READ DATA
FREOOISC
2F~'----_ _ _ _ _ _ _ _ _ _ __
lF~
'CN-iEN~'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
...t.I_________---JJ
Vco _ _ _ _ _ _ _
CNT8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
PLCLK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~BR
nnnnnnnnnnnnnrt
____________________________
~
PDCLR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~
PUCLR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,
U U----IrLJl
PU _ _ _ _ _ _ _ _ _ _ _
U LJ
----JIL.JLJ
PD-~---------------------------_.
DW _ _ _ _ _ _ _ _ _ _ _
207875-10
Figure 9. Typical Data Separator Startup Timing Diagram
PLL Synchronization
At this point, the PLL is enabled and begins to synchronize with the input data stream. This synchronization is accomplished very simply in the following manner. The pump up (PU) signal is enabled on the rising
edge of the READ DATA from the disk drive. (When
the PLL is synchronized with the data stream, this
point will occur at the same time as the falling edge of
the 2XBR signal as shown in Figure 9). The PU Signal
is turned off and the PD signal is activated on the next
rising edge of the 2XBR clock. With this scheme, the
difference between PU active time and the PD active
time is equal to the difference between the input bit rate
and the PLL clock rate. Thus, if PU is turned on longer
than PD is on, the input bit rate is faster than the PLL
clock.
As long as PU and PD are both inactive, no charge is
transferred to or from the LM358 input holding capacitor, and the PLL output frequency is maintained (the
LM358 operational amplifier has a very high input impedance). Whenver PU is turned on, current flows from
the + 5 volt supply through a 20K resistor into the
holding capacitor. When the PD signal is turned on,
current flows from the holding capacitor to ground
through a 20K resistor. In this manner, both the pump
up and pump down charging rates are balanced.
7-115
inter
AP-116
The change in capacitor charge (and therefore voltage)
after a complete PU/PD cycle is proportional to the
difference between the PU and PD pulse widths and is
also proportional to the frequency difference between
the incoming data stream and the PLL oscillator. As
the capacitor voltage is raised (PU active longer than
PD), the PLL oscillator time constant (RC of the
96LS02) is modified by the filter output (LM358) to
raise the oscillator frequency. As the capacitor voltage
is lowered (PD active longer than PD), the oscillator
frequency is lowered. If both frequencies are equal, the
voltage on the holding capacitor does not change, and
the PLL oscillator frequency remains constant.
6.0 AN INTELLIGENT DISKETTE
DATA BASE SYSTEM
The system described in this application note is designed to function as an intelligent data base controller.
The schematics for this data base unit are presented in
Appendix A; a block diagram of the unit is illustrated
in Figure 10. As designed, the unit can access over four
million bytes of mass storage on four floppy disk drives
(using a single 8272 FDC); the system can easily be
expanded to four FDC devices (and 16 megabytes of
on-line disk storage). Three serial data links are also
included. These data links may be used by CRT terminals or other microprocessor systems to access the data
base.
Processor and Memory
A high-performance 8088.eight-bit microprocessor (operating at 5 MHz with no wait states) controls system
operation. The 8088 was selected because of its memory
addressing capabilities and its sophisticated string handling instructions. These features improve the speed of
data base search operations. In addition, these capabilities allow the system to be easily upgraded with additional memory, disk drives, and if required, a bubble
memory or Winchester disk unit.
The schematics for the basic design provide 8K bytes of
2732A high-speed EPROM program storage and 8K
bytes of disk directory and file buffer RAM. This memory can easily be expanded to I megabyte for performance upgrades.
An 8259A Programmable Interrupt Controller (PIC) is
also included in the design to field interrupts from both
the serial port and the FDC. This interrupt controller
provides a large degree of programming flexibility for
the implementation of data base function in an asynchronous, demand driven environment. The PIC allows
the system to accumulate asynchronous data base requests from all serial I/O ports while previously specified data base operations are currently in progress. This
feature is made possible by the ability of the 8251A
RXRDY signal to cause a processor interrupt. After
receiving this interrupt, the processor can temporarily
halt work on existing requests and enter the incoming
information into a data base request buffer. Once the
information has been entered into the buffer, the system
can resume its previous processing.
In addition, the PIC permits some portions of data base
requests to be processed in parallel. For example, once
a disk record has been loaded into a memory buffer, a
memory search can proceed in parallel with the loading
of the next record. After the FDC completes the record
transfer, the memory search will be interrupted and the
processor can begin another disk transfer before resuming the memory search.
The bus structure of the system is split into three functional buffered units. A 20-bit address from the processor is latched by three-state transparent 74LS373 devices. When the processor is in control of the address and
data busses, these devices are output enabled to the system buffered address bus. All I/O devices are placed
directly on the local data bus. Finally, the memory data
bus is isolated from the local data bus by an 8286 octal
transceiver. The direction of this transceiver is determined by the Memory Read signal, while its output
enable is activated by a Memory Read or M~mory
Write command.
7-116
infef
AP-116
~ Ae~:~~S ~1----;:20""B""T;-A:-:D:-;:D"'R:O;ES:-;:S-=Bc.:U,,"S-l--J.,1,-1~~..,3~_~_..L...I_'2..,~~!:'_31...J~
...
PR~;~~OR fIr~··~BI'-!.T~LO~C::!A~L..!'D~AT!.!'Ac.!B!.'!U.:!.S_-l ~
1/0 AND MEMORY COMMANDS
INTA
tNT
HOLD
t
LATCHI
~ ADDRESSl=
BUFFER
CONTROLLER
(8237'2)
t
I--
~
L-.--
~
I
110 AND
MEMORY
ADDRESS
DECODE
CS
RD,WR,CS
1
..
DATA BUS
TRANSCEIVER
(8286)
I
HLDA.
DMA
DRO
fD'R
I-I--
1
DACK
I--
RD,WR,CS
-
I}--------I
8·81T LOCAL DATA 8U,,,S_ _ _-.-_ _-,
I---+-+----'Jj ~
......-'---'........
f.--
r
FLEXIBLE DlSKETIe CONTROLLER
1-----1 PROGRAMMABlEI-+---
Q
1I
f;EAD
:~~~MFM
I
RECEIVERS
L..,~~"'-~.-T~
r1t
r---
lU:~:~
PHASE
LOCKED
LOOP
,.---.1-1.-_-..,
BAUD
d~~~~~~r~R I-+--- S~~~~i I~~:~~~S I-+-- GENReA;:TOR
(8253 pm
1.259A PICI
I-+--I -L -_
_ _- I
DATA
16272FDC)
IPLLI
DATA
L..--RxO
L..--_hD
'------R'D
SEPA·
~
READY
'----INDEX
WRITE PROTECT
'------TWO
SIDED
L..-----FAULT
L..-----_TRACK 0
L.._ _ _ _ _ _ _ READ DATA
DRIVERS
I,
I
DRIVE SElECT
L _ _ _ _ DIRECTION
L - - - - _ STEP
L
' - - - - - - _ WRITE GATE
_ _ _ _ ___. FAULT RESET
' - - - - - - - - _ LOW CURRENT
L.._ _ _ _ _ _ _ _ _ SIDE SELECT
' - - - - - - - - - - HEAD LOAD
' - - - - - - - - - - . - WRITE DATA
207875-11
Figure 10. Intelligent Data Base Block Diagram
Serial 1/0
The three RS-232-C compatible serial I/O ports operate at software-programmable baud rates to 19,2K,
Each I/O port is controlled by an 8251A USART (Universal Synchronous/Asynchronous Receiver/Transmitter), Each USART is individually programmable for
operation in many synchronous and asynchronous serial data transmission formats (including IBM Bi-sync),
In operation, USART error detection circuits can
check for parity, data overrun, and framing errors, An
8253 Programmable Interval Timer is employed to generate the baud rates for the serial I/O ports,
The Transmitter Read and Receiver Ready output signals of the 825 lAs are routed to the interrupt inputs of
the 8259A interrupt controller. These signals interrupt
processor execution when a data byte is received by a
USART and also when the USART is ready to accept
another data byte for transmission,
DMA
The 8272 FDC interfaces to system memory by means
of an 8237-2 high-speed DMA controller, Transfers between the disk controller and memory also operate with
7-117
infef
AP-116
no wait states when 2114-3 (150 ns) or faster static
RAM is used. In operation, the 8272 presents a DMA
request to the 8237 for every byte of data to be transferred. This request causes the 8273 to present a HOLD
request to the 8088. As soon as the 8088 is able to
relinquish data/address bus control, the processor signals a HOLD acknowledge to the 8237. The 8237 then
assumes control over the data and address busses. After
latching the address for the DMA transfer, the 8237
generates simultaneous I/O Read and Memory Write
commands (for a disk read) or simultaneous I/O Write
and Memory Read commands (for a disk write). At the
same time, the 8272 is selected as the I/O device by
means of the DMA acknowledge signal from the 8237.
After this single byte has been transferred between the
FDC and memory, the DMA controller releases the
data/address busses to the 8088 by deactivating the
HOLD request. In a short period of time (13 /ks for
double-density and 27 /ks for single-density) the FDC
requests a subsequent data transfer. This transfer occurs in exactly the same manner as the previous transfer. After all data transfers have been completed (specified by the word count programmed into the 8237 before the FDC operation was initiated), the 8237 signals
a terminal count (EOP pin). This terminal count signal
informs the 8272 that the data transfer is complete.
Upon reception of this terminal count signal, the 8272
halts DMA requests and initiates an "operation complete" interrupt.
Since the system is designed for a 20-bit addressing, a
four-bit DMA-address latch is included as a processor
addressable I/O port. The processor writes the upper
four DMA address bits before a data transfer. When
the DMA controller assumes bus control, the contents
of this latch are output enabled on the upper four bits
of the address bus. The only restriction in the use of
this address latch is that a single disk read or write
transfer cannot cross a 64K memory boundary.
The 8272 write clock (WR CLK) is generated by a ring
counter/multiplexer combination. The write clock frequency is I MHz for MFM recording and 500 KHz for
FM recording (selected by the MFM output of the
8272). The pulse width is a constant 250 ns. The write
clock is constantly generated and input to the FDC
(during both read and write operations). The FDC
write enable output (WE) is transmitted directly to the
write gate disk drive input.
Write data to the disk drive is preshifted (according to
the PSO, PSI FDC outputs) by the combination of a
74LSI75 four-bit latch and a 74LSI53 multiplexer. The
amount of preshift is completely controlled within the
8272 FDC. Three cases are possible: the data may be
written one clock cycle early, one clock cycle late, or
with no preshift. The datapreshift circuit is activated
by the FDC only in the double-density mode. The preshift is required to cancel predictable playback data
shifts when recorded data is later read from the floppy
disk.
A single 50-conductor flat cable connects the board to
the floppy disk drives. FDC outputs are driven by 7438 '
open collector high-current line-drivers. These drivers
are resistively terminated on the last disk drive by
means of a 1500. resistor to + 5V. The line receivers
are 7414 Schmitt triggered inverters with 1500. pull-up
resistors on board.
7.0 SPECIAL CONSIDERATIONS
This section contains a quick review of key features and
issues, most of which have been mentioned in other
sections of this application note. Before designing with
the 8272 FDC, it is advisable that the information in
this section be completely understood.
7.1 Multi-Sector Transfers
Disk Drive Interface
The 8272 FDC may be interfaced to a maximum of
four eight-inch floppy disk drives. Both single- and
double-density drives are accommodated using the data
separation circuit described in section 5. In addition,
single- or dual-sided disk drives may be used. The 8272·
is driven by an 8 MHz crystal controller clock produced by an 8224 clock generator.
Drive select signals are decoded by means of a 74LS139
from the DSO, DSI outputs of the FDC. The fault reset,
step, low current, and direction outputs to the disk
drives are generated from the FR/STEP, LCT/DIR,
and RW /SEEK FDC output signals by means of a
74LS240. The other half of the 74LS240 functions as an
input multiplexer for the disk write protect, two-sided,
fault, and track zero status signals. These signals are
multiplexed into the WP/TS and FLT/TRKO inputs to
the 8272.
The 8272 always operates in a multi-sector transfer
mode. The 8272 continues to transfer data until the TC
input is activated. In a DMA configuration, the TC
input of the 8272 must always be connected to the
EOP/TC output of the DMA controller. When multiple DMA channels are used on a single DMA controller, EOP must be gated with the select signal for the
proper FDC. If the TCD signal is not gated, a terminal
count on another channel will abort FDC operation.
In a processor driven configuration with no DMA controller, the system must count the transfers and supply
a TC signal to the FDC. In a DMA environment, ORing a programmable TC with the TC from the DMA
controller is a convenient means of ensuring that the
processor may always gain control of the FDC (even if
the diskette system hangs up in an abnormal manner).
7-118
inter
AP-116
7.2 Processor Command/Result
Phase Interface
In the command phase, the processor must write the
exact number of parameters in the exact order shown in
Table 5. During the result phase, the processor must
read the complete result status. For example, the Format Track command requires six command bytes and
presents seven result bytes. The 8272 will not accept a
new command until all result bytes are read. Note that
the number of command and result bytes varies from
command-to-command. Command and result phases
cannot be shortened.
During both the command and result phases, the Main
Status Register must be read by the processor before
each byte of information is read from, or written to, the
FDC Data Register. Before each command byte is written, DIO (bit 6) must be low (indicating a data transfer.
f~o~ t~e processor) and RQM (bit 7) must be high
(mdlcatmg that the FOC is ready for data). During the
result phase, DIO must be high (indicating a data
transfer to the processor) and RQM must also be high
(indicating that data is ready for the processor).
NOTE:
After the 8272 receives a command byte, the RQM
flag may remain set for 12 microseconds (with an 8
MHz clock). Software should not attempt to read the
Main Status Register before this time interval has
elapsed; otherwise, the software will erroneously assume that the FDC is ready to accept the next byte.
7.3 Sector Sizes
power-on, the FDC assumes that all drives are not
ready. If a drive application requires that the ready line
be strapped active, the FDC will generate an interrupt
immediately after power is applied.
7.7 Gap Length
Only the gap 3 size is software programmable. All other gap sizes are fixed. In addition, different gap 3 sizes
must be specified in format, read, write, and scan commands. Refer to Section 3 and Table 9 for gap size
recommendations.
7.8 Seek Command
The drive busy flag in the Main Status Register remains
set after a Seek command is issued until the Sense Interrupt Status command is issued (following reception
of the seek complete interrupt).
.
The FDC does not perform implied seeks. Before issuing data read or write commands, the read/write head
must be positioned over the correct cylinder. If the
head is not positioned correctly, a cylinder address error is generated.
After issuing a step pulse, the 8272 resumes drive status
polling. For correct stepper operation in this mode, the
stepper motor must be constantly enabled. (Most drives
provide a jumper to permit the stepper motor to be
constantly enabled.)
7.9 Step Rate
The 8272 does not support 128 byte sectors in the
MFM (double-density) mode.
7.4 Write Clock
The FDC Write Clock input (WR eLK) must be present at all times.
The 8272 can emit a step pulse that is one millisecond
faster than the rate programmed by the SRT parameter
in the Specify command. This action may cause subsequent sector not found errors. The step rate time should
be programmed to be 1 ms longer than the step rate
time· required by the drive.
7.10 Cable Length
7.5 Reset
The FDC Reset input (RST) must be held active during
power-on reset while the RD and WR inputs are active.
If the reset input becomes inactive while RD and WR
are still active, the 8272 enters the test mode. Once
activated, the test mode can only be deactivated by a
power-down condition.
A cable length of less than 10 feet is recommended for
drive interfacing.
7.11 Scan Commands
The current 8272 has several problems when using the
scan commands. These commands should· not be used
at this time.
7.6 Drive Status
The 8272 constantly polls (starting after the power-on
reset) all drives for changes in the drive ready status. At
7-119
infef
AP-116
7.12 Interrupts
7.14 Bad Track Maintenance
When the processor receives an interrupt from the
FDC, the FDC may be reporting one of two distinct
events:
The 8272 does not internally maintain bad track inforniation. The maintenance of this information must be
performed by system software. As an example, of typical bad track operation, assume that a media test determines that track 31 and. track 66 of a given floppy disk
are bad. When the disk is formatted for use, the system
software formats physcial track 0 as logical cylinder 0
(C = 0 in the command phase parameters), physic~1
track 1 as logical track 1 (C = 1), and so on, until
physical track 30 is formatted as logical cylinder 30 (C
= 30). Physical track 31 is bad and should be formatted as logical cylinder FF (indicating a bad track).
Next, physical track 32 is formatted as logical cylinder
31, and so on, until physical track 67 is formatted as
logical cylinder 64. Next, bad physical track 66 is formatted as logcial cylinder FF (another bad track marker), and physical track 67 is formatted as logical cylinder 65. This formatting continues until the last physical
track (77) is formatted as logical cylinder 75. Normally,
after this formatting is complete, the bad track information is stored in a prespecified area on the floppy disk
(typically in a sector on track 0) so that the system will
be able to recreate the bad track information when the
disk is removed from the drive and reinserted at some
later time.
a) The beginning of the result phase of a previously
requested read, write, or scan command.
b) An asynchronous event such as a seek/recalibrate
completion, an'attention, an abnormal command termination, or an invalid command.
These two cases are distinguished by the FDC busy flag
(bit 4) in the Main Status Register. If the FDC busy
flag is high, the interrupt is of type (a). If the FDC busy
flag is low, the interrupt was caused by an asynchronous event (b).
A single interrupt from the FDC may signal more than
one of the above events. After receiving an interrupt,
the processor must continue to issue Sense Interrupt
Status commands (and service the resulting conditions)
until an invalid command code is received. In this manner, all "hidden" interrupts are ferreted out and serviced.
7.13 Skip Flag (SK)
The skip flag is used during the execution of Read
Data, Read Deleted Data, Read Track, and various
Scan commands. This flag permits the FDC to skip
unwanted sectors on a disk track.
When performing a Read Data, Read Track, or Scan
command, a high SK flag indicates that the FDC is to
skip over (not transfer) any sector containing a deleted
data address mark. A low SK flag indicates that the
FDC is to terminate the command (after reading all the
data in the sector) when a deleted data address mark is
encountered.
When performing a Read Deleted Data command, a
high SK flag indicates that sectors containing nor!ll~1
data address marks are to be skipped. Note that hIS IS
just the opposite situation from that described in the
last paragraph. When a data address mark is encountered during a Read Deleted Data command (and the
SK flag is low), the FDC terminates the command after
reading all the data in the sector.
To illustrate how,the system software performs a transfer operation disk with bad tracks, assume that the disk
drive head is positioned at track 0 and the disk described above is loaded into the drive. If a command to
read track 36 is issued by an application program, the
system software translates this read command into a
seek to physical track 37 (since there is one bad track
between 0 and 36, namely 31) followed by a read of
logical cylinder 36. Thus, the cylinder parameter C is
set to 37 for the Seek command and 36 for the Read
Sector command.
7.15 Head Load versus Head Settle
Times
The 8272 does not permit separate specification of the
head load time and the head settle time. When the
Specify command is issued for a given disk drive, the
proper value for the HLT parameter is the maximum of
the head load time and the head settle time.
7-120
inter
AP-116
APPENDIX A
SCHEMATICS
Power Distribution
Part
Ref Desig
+5
GND
8088
8224
8237-2
8251A
8253-5
8259A
8272
8284
8286
2114
2732A
74LSOO
74LS04
74LS27
74LS32
74LS74
74LS138
74LS139
74LS153
74LS157
74LS164
74LS173
74LS175
74 LS240
74 LS257
74LS367
74LS373
74LS393
74S08
74S138
7414
7438
1488
1489
96LS02
96LS02
LM358
A2
16
A6
A9, 89, C9
A10
810
010
A1
86,F4
F1, F2, G1, G2, H1, H2, 11, 12
01,02
E1
82,E6,E8,F8
E2,E5
81
A4,G5, H6
F3
E10
13
F6
F5
G3
G4
G10
03
C3,E9
84,C4,04,C6
15, F7
E4
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REFERENCES
1) Intel, "8272 SinglelDouble Density Floppy Disk
Controller Data Sheet," Intel Corporation, 1980.
2) Intel, iSBC 208 Hardware Reference Manual, Man- .
ual Order No. 143078, Intel Corporation, 1980.
3) 'Intel, iSBC 204 Flexible Diskette Controller Hardware Reference Manual, Manual Order No.
9800568A, Intel Corporation, 1978.
7-121
+12
-12
14
1
16
8
8
4
4) Shugart, SA800/801 Diskette Storage Drive OEM
Manual, Part No. 50574, Shugart Associates, 1977.
5) Shugart, SA800/801 Diskette Storage Drive Theory
of Operations, Part No. 50664, Shugart Associates,
1977.
6) Shugart, SA800 Series Diskette Storage Drive Double Density Design Guide, Part No. 39000, Shugart
Associates, 1977.
inter
AP-116
7) Shugart, "Application Notes for Shugart Dual
VFO," Part No. 39101, Shugart Associates, 1980.
8) Pertec, "Soft'sector Formatting forPERTEC Fl~x
ible Disk Drives," Pertec Application Note, 1977.
9) Ausing Lesea and Rodnay Zaks, "Floppy-disc Controller Design Must Begin With the Basics," EDN,
May 20, 1978.
10) John Hoeppner and Larry Wall, "Encoding/Decoding Techniques Double Floppy Disc Capacity,"
Computer Design, Feb 1980.
11) John Zarrella, System Architecture, Microcomputer
Applications, 1980.
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APPLICATION
NOTE
AP-121
November 1986
Software Design and
Implementation of Floppy Disk
Subsystems
Order Number: 207885-001
7-128
inter
AP-121
1.0 INTRODUCTION
Disk interface software is a major contributor to the
efficient and reliable operation of a floppy disk subsystem. This software must be a well-designed compromise
between the needs of the application software inodules
and the capabilities of the floppy disk controller (FDC).
In an effort to meet these requirements, the implementation of disk interface software is often divided into
several levels of abstraction. The purpose of this application note is to define these software interface levels
and describe the design and implementation of a modular and flexible software driver for the 8272 FDC. This
note is a companion to AP-116, "An Intelligent Data
Base System Using the 8272".
The Physical Interface Level
The software interface level closest to the FDC hardware is referred to as the physical interface level. At
this level, interface modules (often called disk drivers or
disk handlers) communicate directly with the FDC device. Disk drivers accept floppy disk commands from
other software modules, control and monitor the FDC
execution of the commands, and finally return operational status information (at command termination) to
the requesting modules.
4) The requirement to support a software interface that
is independent of the type of disk attached to the
system. In this case, a system generated ("logical")
disk address (drive, head, cylinder, and sector num~
bers) must be mapped into a physical floppy disk
address. For example, to switch between single- and
dual-sided disks, it may be easier and more cost-effective for the software to treat the dual-sided disk as
containing twice as many sectors per track (52) rather than as having two sides. With this technique,
accesses to sectors I through 26 are mapped onto
head 0 while accesses to sectors 27 through 52 are
mapped onto head 1.
5) The necessity of supporting a bad track map. Since
bad tracks depend on the disk media, the bad track
mapping varies from disk to disk. In general, the
system and application software should not be concerned with calculating bad track parameters. Instead, these software modules should refer to cylinders logically (0 through 76). The logical interface
level procedures must map these cylinders into physical cylinder positions in order to avoid the bad
tracks.
In order to perform these functions, the drivers must
support the bitlbyte level FDC interface for status and
data transfers. In addition, the drivers must field, classify, and service a variety of FDC interrupts.
The key to logical interface software design is the mapping of the "logical disk interface" (as seen by the application software) into the "physical disk interface" (as
implemented by the floppy disk drivers). This logical to
physical mapping is tightly coupled to system software
design and the mapping serves to isolate both applications and system software from the peculiarities of the
FDC device. Typical logical interface procedures are
described in Table 1.
The Logical Interface Level
The File System Interface Level
System and application software modules often specify
disk operation parameters that are not directly compatible with the FDC device. This software incompatibility
is typically caused by one of the following:
1) The change from an existing FDC to a functionally
equivalent design. Replacing a TTL based controller
with an LSI device is an example of a change that
may result in software incompatibilities.
2) The upgrade of an existing FDC subsystem to a
higher capability design. An expansion from a single-sided, single-density system to a dual-sided, double-density system to increase .data storage capacity
is' an example of such a system change.
3) The abstraction of the disk software interface to
avoid redundancy. Many FDC parameters (in particular the density, gap size, number of sectors per
track and number of bytes per sector) are fixed for a
floppy disk (after formatting). In fact, in many systems these parameters are never changed during the
life of the system.
The file system typically comprises the highest level of
disk interface software used by application programs.
The file system is designed to treat the disk as a collection of named data areas (known as files). These files
are cataloged in the disk directory. File system interface
software permits the creation of new files and the deletion of existing files under software control. When a file
is created, its name and disk address are entered into
the directory; when a file is deleted, its name is removed from the directory. Application software requests the use of a file by executing ari OPEN function.
Once opened, a file is normally reserved for use by the
requesting program or task and'the file cannot be reopened by other tasks. When a task no longer needs to
use an open file, the task closes the file, releasing it for
use by other tasks.
Most file systems also support a s.et of file attributes
that can be specified for each file. File attributes may be
used to protect files (e.g., the WRITE PROTECT attri-
7-129
AP-121
bute ensures that an existing file cannot accidentally be
overwritten} and to supply system configuration information (e.g., a FORMAT attribute may specify that a
file should automatically be created on a new disk when
the disk is formatted).
At the file system interface level, application programs
need not be explicitly aware of disk storage allocation
techniques, block sizes,.or file coding strategies. Only a
"file name" must be presented in order to open, read or
write, and subsequently close a file. Typical file system
functions are listed in Table 2.
Table 1 Examples of Logical Interface Procedures
Description
Name
FORMAT DISK
Controls physical disk formatting for all tracks ona disk. Formatting
adds FDC recognized cylinder, head, and sector addresses as well as
address marks and data synchronization fields (gaps) to the floppy
disk media.
RECALIBRATE
Moves the disk read/write head to track 0 (at the outside edge of the
diskr
SEEK
Moves the disk read/write head to a specified logical cylinder. The
logical and physical cylinder numbers may be different if bad track
mapping is used.
READ STATUS
Indicates the status of the floppy disk drive and media. One important
use of this procedure is to determine whether a floppy disk is dual~ .
sided.
READ SECTOR
Reads one or more cOl1)plete sectors starting at a specified disk
address (drive, head, cylinder, and sector).
WRITE SECTOR
Writes one or more complete sectors starting at a specified disk
address (drive, head, cylinder, and sector).
Table 2 Disk File System Functions
Name
Description
OPEN
Prepare a file for processing. If the file is to be opened for input and the
file name is not found in the directory, an error is generated. If the file is
opened for output and the file name is not found in the directory, the
file is automatically created.
CLOSE
Terminate processing of an open file.·
READ
Transfer Data from an open file to memory. The READ function is
often designed to buffer one or more sectors of data from the disk
drive and supply this data to the requesting program, as requited.
WRITE
Transfer data from memory to an open file. The WRITE function is
often designed to buffer data from the application program until
enough data is available to fill a disk sector.
CREATE
Initial.ize a file and enter its name and attributes into the file directory.
DELETE
Remove a file from the directory and release its storage space.
RENAME
Change the name of a file in the directory.
ATIRIBUTE
Change the attributes of a file.
LOAD
Read a file of executable code into memory.
INITDISK
Initialize a disk by formatting the media and establishing the directory
file, the bit map file, and other system files.
7-130
inter
AP-121
Scope of this Note
Foe Data Transfer Interface
This application note directly addresses the logical and
physical interface levels. A complete 8272 driver (including interrupt service software) is listed in Appendix
A. In addition, examples of recalibrate, seek, format,
read, and write logical interface level procedures are
included as part of the exerciser program found in Appendix B. Wherever ,possible, specific hardware configuration dependencies are parametized to provide maximum flexibility without requiring major software
changes.
Three distinct software interface techniques may be
used to interface system memory to the FDe device
during sector data transfers:
1) DMA-In a DMA implementation, the software is
only required to set up the DMA controller memory
address and transfer count, and to initiate the data
transfer. The DMA controller hardware handshakes
with the processor/system bus in order to perform
each data transfer.
2) Interrupt Driven-The FDe generates an interrupt
when a data byte is ready to be transferred to memory, or when a data byte is needed from memory. It is
the software's responsibility to perform appropriate
memory reads/writes in order to transfer data from/
to the FDe upon receipt of the interrupt.
3) Polling-Software responsibilities in the polling
mode are identical to the responsibilities in the interrupt driven mode. The polling mode, however, is
used when interrupt service overhead (context
switching) is too large to support the disk data rate.
In this mode, the software determines when to transfer data by continually polling a data request status
flag in the FDe status register.
2.0 Disk 110 Techniques
One of the most important software aspects of disk interfacing is the fixed sector size. (Sector sizes are fixed
when the disk is formatted.) Individual bytes of disk
storage cannot be read/written; instead, complete sectors must be transferred between the floppy disk and
system memory.
Selection of the appropriate sector size involves a tradeoff between memory size, disk storage efficiency, and
disk transfer efficiency. Basically, the following factors
must be weighed:
I) Memory size. The larger the sector size, the iarger
the memory· area that must be reserved for use during disk I/O transfers. For example, a IK byte disk
sector size requires that at least one IK memory
block be reserved for disk I/O.
2) Disk Storage efficiency. Both very large and very
small sectors can waste disk storage space as follows.
In disk file systems, space must be allocated somewhere on the disk to link the sectors of each file
together. If most files are composed of many small
sectors, a large amount of linkage overhead information is required. At the other extreme, when most
files are smaller than a single disk sector, a large
amount of space is wasted at the end of each sector.
3) Disk transfer efficiency. A file composed of a few
large sectors can be transferred to/from memory
more efficiently (faster and with less overhead) than
a file composed of many small sectors.
Balancing these considerations requires knowledge of
the intended system applications. Typically, for general
purpose systems, sector sizes from 128 bytes to lK
bytes are used. For compatibility between single-density and double-density recording with the 8272 floppy
disk controller, 256 byte sectors or 512 byte sectors are
most useful.
7-131
The DMA mode has the advantage of permitting the
processor to continue executing instructions while a
disk transfer is in progress. (This capability is especially
useful in mUltiprogramming environments when the
operating system is designed to permit other tasks to
execute while a program is waiting for I/O.) Modes 2
and 3 are often combined and described as non-DMA
operating modes. Non-DMA modes have the advantage of significantly lower system cost, but are often
performance limited for double-density systems (where
data bytes must be transferred to/from the FDe every
16 microseconds).
Overlapped Operations
Some FDe devices support simultaneous disk operations on more than one disk drive. Normally seek and
recalibrate operations can be overlapped in this manner. Since seek operations on most floppy drives are
extremely slow, this mode of operation can often be
used by the system software to reduce overall disk access times.
.
inter
AP-121
Buffers
The buffer concept is an extremely important element
in· advanced disk I/O strategies. A buffer is nothing
more than a memory area containing the same amount
of data as a disk sector contains. Generally, when an
application program requests data from a disk, the system software allocates a buffer (memory area) and
transfers the data from the appropriate disk sector into
the buffer. The address of the buffer is then returned to
the application software. In the same manner, after the
application program has filled a buffer for output, the
buffer address is passed to the system software, which
writes data from the buffer into a disk sector. In multitasking systems, multiple buffers may be allocated from
I! buffer pool. In these systems, the disk controller is
often requested to read ahead and fill additional data
buffers while the application software is processing a
previous buffer. Using this technique, system software
attempts to fill buffers before they are needed by the
appliCation programs, thereby eliminating program
waits during I/O transfers. Figure 1 illustrates the use
of multiple buffers in a ring configuration.
BUFFER #4
EMPTY
BUFFER #3
EMPTY
BUFFER #2
EMPTY
BUFFER #1
BEING
FILLED
DATA FLOW FROM DISK
INTO BUFFER
DISK
DRIVE
DISK
SUBSYSTEM
207885-1
NOTE:
a) The first disk read request by the application software causes the disk subsystem to begin filling ·the first empty buffer.
The application software must wait until the buffer is filled before it may continue execution.
Figure 1. Using Multiple Memory Buffers for Disk I/O
7-132
AP-121
APPLICATION
SOFTWARE
BUFFER #1
BEING
EMPTIED
BUFFER #4
EMPTY
BUFFER #3
EMPTY
BUFFER #2
BEING
FILLED
DATA FLOW FROM DISK
INTO BUFFER
I
~_~_~_~ ~I------------~~~
L _____
DISK
SUBSYSTEM
______
207885-2
NOTE:
b) After the first buffer is filled, the disk system continues to transfer disk data into the next buffer while the application
software begins operating on the first full buffer.
Figure 1. Using Multiple Memory Buffers for Disk 1/0 (Continued)
7·133
inter
AP-121
APPLICATION
SOFTWARE
t
BUFFER #1
BEING
EMPTIED
BUFFER #2
FULL
BUFFER #3
FULL
BUFFER #4
FULL
NO DISK TRANSFER
ACTIVE
DISK
SUBSYSTEM
207885-3
NOTE:
c) When all empty buffers have been filled, disk activity is stopped until the application software releases one or more
buffers for reuse.
.
Figure 1. Using Multiple Memory Buffers for Disk 110 (Continued)
7-134
AP-121
APPLICATION
SOFTWARE
BUFFER #2
BEING
EMPTIED
BUFFER #3
FULL
BUFFER #4
FULL
BUFFER #.1
BEING
FILLED
DATA FLOW FROM
DISK INTO BUFFER
DISK
DRIVE
DISK
SUBSYSTEM
207885-4
NOTE:
d) When the application software releases a buffer (for reuse), the disk subsystem begins a disk sector read to refill the
buffer. This strategy. attempts to anticipate application software needs by maintaining a sufficient number of full data
buffers in order to minimize data transfer delays. If disk data is already in memory when the application software requests it, no disk transfer delays are incurred.
Figure 1. Using Multiple Memory Buffers for Disk I/O (Continued)
7-135
AP-121
3.0 THE 8272 FLOPPY DISK
CONTROLLER
The 8272 is a single-chip LSI Floppy Disk Controller
(FDC) that implements both single- and double-density
floppy disk storage subsystems (with up to four dualsided disk drives per FOC). The 8272 supports the
IBM 3740 single-density recording format (FM) and
the IBM System 34 double-density recording format
(MFM). The 8272 accepts and executes high-level disk
commands such as format track, seek, read sector, and
write sector. All data synchronization and error checking is automatically performed by the FOC to ensure
reliable data storage and subsequent retrieval. The 8272
interfaces to microprocessor systems with or without
Direct Memory Access (DMA) capabilities and also in- '
terfaces to a large number of commercially available
floppy disk drives.
FI~ppy
Disk Commands
The 8272 executes fifteen high-level disk interface commands:
Specify
Sense Drive Status
Sense Interrupt Status
Seek
Recalibrate
Format Track
Read Data
Read Deleted Data
Write Data
Write Deleted Data
Read Track
Read ID
Scan Equal
Scan High or Equal
Scan Low or Equal
Result Phase:
FDC in the preceding command
phase. The execution phase normally
ends when the last data byte is transferred to/from the disk or when an
error occurs.
After completion of the disk operation, status and other housekeeping
information are made available to
the driver software. After this information is read, the FOC reenters the
command phase and is ready to accept another commapd.
Interface Registers
To support information transfer between the FOC and
the system software, the 8272 contains two 8-bit registers: the Main Status Register and the Data Register.
The Main Status Register (read only) contains FCD
status information and may be accessed at any time.
The Main Status Register (Table 3) provides the system
processor with the status of each disk drive, the status
of the FOC, and the status of the processor interface.
The Data Register (read/write) stores data, commands,
parameters, and disk drive status information. The
Data Register is used to program the FDC during the
command phase and to obtain result information after
completion of FDC operations.
In addition to the Main Status Register, the FOC contains four additional status registers (STO, STl, ST2,
and ST3): These registers are only available during the
result phase of a command.
Each command is initiated· by a multi-byte transfer
from the driver software to the FOC (the transferred
bytes contain command and parameter information).
After complete command specification, the FDC automatically executes the command. The command result
data (after execution of the command) may require a
multi-byte transfer of status information back to the
driver. It is convenient to consider each FDC command
as consisting of the following three phases:
Command Phase: The driver transfers to the FDC all
the information required to perform
a particular disk operation. The 8272
automatically enters the command
phase after RESET and following the
completion of the result phase (if
any) of a previous command.
Execution Phase: The FOC performs the operation as
instructed. The execution phase is
entered immediately after the last
command parameter is written to the
Command/Result Phases
Table 4 lists the 8272 command set. For each of the
fifteen commands, command and result phase data
transfers are listed. A list of abbreviations used in the
table is given in Table 5, and the contents of the result
status registers (STO-ST3) are illustrated in Table 6.
The bytes of data which are sent to the 8272 by the
drivers during the command phase, and are read out of
the 8272 in the result phase, must occur in the order
shown in Table 4. That is, the command·code must be
sent first and the other bytes sent in the prescribed sequence. All bytes of the command and result phases
.. must be read/written as described. After the last byte of
data in the command phase is sent to the 8272 the execution phase automatically starts. In a similar fashion,
when the last byte of data is read from the 8272 in the
result phase, the result phase is automatically ended
and the 8272 reenters the command phase.
It is important to note that during the result phase all
bytes shown in Table 4 must be read. The Read Data
7-136
intJ
AP-121
command, for example, has seven bytes of data in the
result phase. All seven bytes must be read in order to
successfully complete the Read Data command. The
8272 will not accept a new command until all seven
bytes have been read. The number of command and
result bytes varies from command-to-command.
In order to read data from, or write data to, the Data
Register during the command and result phases, the
software driver must examine the Main Status Register
to determine if the Data Register is available. The DIO
(bit 6) and RQM (bit 7) flags in the Main Status Regis-
ter must be low and high, respectively, before each byte
of the command word may be written into the 8272.
Many of the commands require multiple bytes, and as a
result, the Main Status Register must be read prior to
each byte transfer to the 8272. To read status bytes
during the result phase, DIO and RQM in the Main
Status Register must both be high. Note, checking the
Main Status Register in this manner before each byte
transfer to/from the 8272 is required only in the command and result phases, and is NOT required during
the execution phase.
Table 3. Main Status Register Bit Definitions
Bit
Number
Symbol
0
DoB
Disk Drive 0 Busy. Disk Drive 0 is seeking.
Description
1
D1B
Disk Drive 1 Busy. Disk Drive 1 is seeking.
2
D2B
Disk Drive 2 Busy. Disk Drive 2 is seeking.
3
D3B
Disk Drive 3 Busy. Disk Drive 3 is seeking.
4
GB
FDG Busy. A read or write command is in progress.
5
NDM
Non-DMA Mode. The FDG is in the non-DMA mode when this flag
is set (1). This flag is set only during the execution phase of
commands in the non-DMA mode. Transition of this flag to a zero
(O) indicates that the execution phase has ended.
6
DIO
Data Input/Output. Indicates the direction of a data transfer
between the FDG and the Data Register. When DIO is set (1), data
is read from the Data Register by the processor; when DIO is reset
(0), data is written from the processor to the Data Register.
7
ROM
Request for Master. When set (1), this flag indicates that the Data
Register is ready to send data to, or receive data from, the
processor.
7-137
AP-121
Table 4. 8272 Command Set
DATA BUS
PHASE
RfW
0.,
D.
D.
D.
D.
DATA
D2
D,
DO
REMARKS
PHASE
RfW
D,
D.
D.
D.
READ DATA
Command
W
W
W
W
W
W
W
W
W
MT MFM 5K
0
0
0
0
0
_____ C
~
D.
D2
D,
DO
0
HOS OSI DSO
Command
Command Codes
Sector 10 informallon
prior to Command
execution
A
~N
EOT
_ _ _ _ GPL __ ,_ _ _
_ _ _ ~ OIL
Data transfer
Execution
between the FOD
W
W
W
W
W
W
W
W
W
0 MFM SK
0
0
0
0
0
0
0
0
HOS oSl OSO
C
______ H
A
N ______
A
STO
ST'
ST'
C _______
A
A
A
A
OTl _ _ _-_ _
Dala transfer
Elecution
between the FOD
and the main·system.
FOC reads the
complete track
contents from the
physical index
mark to EOT
execution
aller command
Result
execution
-~~-
REAO DELETED DATA
Command
W
W
W
W
W
W
W
MT MFM SK
0
0
0
0
1
Command Codes
1
0 HoS oSt 050
C _____
H _____
_ _ _ _ _~
W
W
A
N
ECI
GPl' _ _ _ _ _
DTl _ _ _ _ _ _
-r-Command
W
W
_____
A
A
A
A
A
_ _ _ _ _ H _______
A
N
W
W
W
W
W
W
W
W
W
MT MFM
0
Result
H _ _-_ _ _ _
A
AEAo 10
0 MFM 0
0
,
1
0
A
A
A
H
A
_____ N
Command
Command Codes
EOT
GPl _ _ _ _
__
- _ _ OTl
A
A
_ _ _ _ _ STO
_ _ _ _ 571
ST2
C
Seclor 10 information
alter Command
execution
WAITE DELETED OAT A
W
W
W
W
W
W
W
W
W
0
MT MFM 0
,
Result
_H _____
A
N
~.
__
A
R
A
A
A
A
STO
S71
ST2
C
H
A
N
Sector 10 information
during Execution
Phase
0 MFM 0
0
1
--
Command Codes
HOS OSI DSO
Bytes/Sector
SeClorsITrack
Gap 3
Filter Byle
N
SC
GPL
0
FDC formalS an
entire track
A
A
A
A
_ _ _ _ ~ STO
571
ST2
____ C
---~
Status information
after Command
eKecution
In this case, the ID
information has no
meaning
H
A
N
W
W
W
W
MT MFM SK
W
W
W
W
___
w
Sector 10 information
prior to Command
execution
0
0
Command Codes
0
0
Result
Stalus information
after Command
execution
Sector 10 information
after Command
eKecution
HDS OS! DSO
C
Sector 10 information
prior to Command
eKecutlon
H
A
~_N_
EOT
GPl _ _ _ _
_ _ _ _ STP
______
~
Execution
Data transfer
between the FDO
and the main-system
A
Status mformation
after Command
eKecution
SCAN EQUAL
Command
Command Codes
EOT
GPl
OTl
Execution
W
W
W
W
W
W
R
A
A
HDS DSI esc
,_ _ _ _ _ _ C
H
A
N ___
----
EKecution
Status information
aller Command
execution
STO
571
ST2
C
H
A
N
A
A
Command Codes
0 HDS DSI oSO
R
Sector 10 informalion
prior to Command
execution
C
-------
Sector 10 Informahon
alter Command
execution
The first correct 10
information on the
track is stored in
Data Register
A
A
A
A
Sector ID information
aller Command
eKecution
Data transler
between the mainsyslem and the FOD
A
A
Result
after Command
execution
FORMAT A TRACK
0
1
0 HOS 051 050
EKecution
Command
Status mformation
__________ N _ _-_ _ _
WAITE DATA
Result
STO
EKeculion
Status information
after Command
execution
STO
571
ST2
C
A
A
Command
.~
_ _ _ _ _ STl
ST 2
C __
Data transfer
between the FDD
and the main-system
Execution
Result
A
A
A
A
A
A
A
Sector 10 informalion
prior to Command
execution
Sector 10 information
prior 10 Command
execution
EOT
Stalus information
aller Command
Sector 10 information
H
A
A
A
Command Codes
_ _ _ _ GPL _ _ _ _ _ _
and the main·system
Result
I REMARKS
REAO A TRACK
, ,
____ H
____
aus
Data compared
between the FOD
and the main-system
STO
571
ST2
C
H
R
N
Stalus mformation
alter Command
execution
Sector 10 information
aller Command
eKecution
207885-34
NOTE:
1. AO = Uor all operations.
7-138
infef
AP-121
Table 4. 8272 Command Set (Continued)
DATA BUS
DATA. BUS
I-P_H_A_S_E_,-RJW_...l...D-",---D-,.,-D-,.-.:D-=.-.:D.":3,---D!,2,---D,!-D::O~_".::.E...
M_A"
..."...S_ _ _-I PHASE
RECAUBRATE
SCAN LOW OR EQUAL
Command
W
MT MFM SK
WOO
0
w
W
1
Command Codes
0
HOS OSt
C
_ _ _ _ _ . H _________
W
Command
eso
A ________ ~ __
Sector 10 information
prior Command
eKecutlon
o
Head retracted 10
Track 0
~
-.=~ ______ E~T ~=~===-_
_ _ _ _ .. ____ GPL .___ ~ __ ._______ _
Command
W
_ _ _ _ ,___ SIP
Result
A
,
Command Codes
_ _ _ _ _ _ 51 0 ___ "__ ~_~
C
_ _ _ __
Oata compared
Execution
~~~Wt~~n~~~n~~~tem
A
A
A
R
A
A
A
_______ STO ___ . _ __
___
_ _ Sf 1 _ _ _ _ _ _ _
ST 2 ____ _
Status information
alter Command
execution
HR - - - - _ _ _ _ _ _ _ N _ _ _ _ _ _~
Sector 10 informalion
after Command
execution
~
======:
_ _ _ _ _ C ______ _
SPECIFY
Command
a
HOS OSl OSO
~ ===-==-=-=-=- ~ =====
W
W
Sector 10 informalion
prior Command
execution
SENSE DRIVE STATUS
Command
R
:
R
R
W
W
Command Codes
o HOS OSl 050
_ _ _ _ _ ST 3 _ _ _ _ __
Status Information
about the FDD
II-::----:T--:-:-c-,-:--____---:-~__seEK
-:-__- ____-r:_-__:___- - j
Command
W
WOO
W
_____ C
1
1
HOS OS1 050
Command Codes
Head is pOSitioned
over proper Cylinder
Oata compared
between the FOO
and the main· system
R
NO Timer Settings
HLT
Execution
OPL
__
__
__
___
STP _
Execution
R
SPT _ ... _____ .. _ _ _ HUT
If----,.--,.------------,.-------I
_ _ _ _ _ EDT _ _ _ __
=====-
Command Codes
W
W
W
I--c::-o-m-m-.-nd-'-:-:wC-"M:-:T::-:-M~F~M~S~K---'------,-,r:c,-o-m-m-.n-d-,C,-o-,-d.-'--11 Result
WOO
0
0
W
____ C
Status information at
the end of each seek
operation about the
II------'----'------==::c----'---'--FD-C------j
r------L---L----~S~C~A~N~H~'O~H~O~R~E~a~U~A~L~~'-------------11
Result
eso
SENSE INTERRUPT STATUS
A
ResuU
OSI
EllecutlOn
W
W
Command Codes
W
W
ST 0 _ _ _ _ _
ST 1 _ _ _ _ _
ST 2 _ _ _
------
on Diskette
INVALID
II-:c,--om-m-.nd."...."w,..-,--_-_-_-:-'n-,.lid Code,
Status information
alter Command
execution
~ ~-
Sector 10 information
A
N
after Command
execution
Result
- - - - - - 5T 0 - - - - -
Invalid Command
Codes (NoOp- FOC
goes into Standby
State)
ST 0= 80
(16)
207885-35
NOTE:
1. AO = 1 for all operations.
7-139
intJ
Symbol
G
D
DSO,
DS1
DTL
EOT
GPL
H
HLT
HUT
MFM
MT
N
ND
R
SG
SK
SAT
STO,
ST1,
ST2,
ST3
STP
AP-121
Table 5 Command/Result Parameter Abbreviations
Description
CYLINDER ADDRESS. The currently selected cylinder address (0 to 76) on the disk.
DATA PATTERN. The pattern to be written in each sector data field during formatting.
DISK DRIVE SELECT.
DS1 DSO
0
0 Drive 0
0
1 Drive 1
1
0 Drive 2
1
1 Drive 3
SPECIAL SECTOR SIZE. During the execution of disk read/write commands, this parameter is used to
temporarily alter the effective disk sector size. By setting N to zero, DTL may be used to specify a sector
size from 1 to 256 bytes in length. If the actual sector (on the disk) is larger than DTL specifies, the
.
remainder of the actual sector is not passed to the system during read commands; during write
commands, the remainder of the actual sector is written with all-zeroes bytes. DTL should be set to FF
hexadecimal when N is not zero.
END OF TRACK. The final sector number of the current track.
GAP LENGTH. The gap 3 size. (Gap 3 is the space between sectors).
HEAD ADDRESS. Selected head: 0 or 1 (disk side 0 or 1, respectively) as encoded in the sector ID field.
HEAD LOAD TIME. Defines the time interval that the FOG waits after loading the head before initiating
the read or write operation. Programmable from 2 to 254 milliseconds (in increments of 2 ms).
HEAD UNLOAD TIME. Defines the time interval from the end of the execution phase (of a read or write
command) until the head is unloaded. Programmable from 16 to 240 milliseconds (in increments of 16
ms).
MFM/FM MODE SELECTOR. Selects MFM double-density recording mode when high, FM single- .
density mode when low.
MULTI-TRACK SELECTOR. When set, this flag selects the multi-track operating mode. In this mode
(used only with dual-sided disks), the FDG treats a complete cylinder (under both read/write head 0 and
read/write head 1) as a single track. The FDG operates as if this expanded track started at the first
sector under head 0 and ended at the last sector under head 1. With this flag set (high), a multi-sector
read operation will automatically continue to the first/sector under head 1 when the FDG finishes
operating on the last sector under head o.
SECTOR SIZE CODE. The number of data bytes within a sector.
NON-DMA MODE FLAG. When set (1), this flag inidcates that the FDG is to operate in the non-DMA
mode. In this mode, the processor participates in each data transfer (by means of an interrupt or by
polling the ROM flag in the Main Status Register). When reset (0), the FDG interfaces to a DMA
controller.
SECTOR ADDRESS. Specifies the sector number to be read or written. In multi-sector transfers, this
parameter specifies the sector number of the first sector to be read or written.
NUMBER OF SECTORS PER TRACK. Specifies the number of sectors per track to be initialized by the
Format Track command.
SKIP FLAG. When this flag is set, sectors containing deleted data address marks will automatically be
skipped during the execution of multi-sector Read Data or Scan commands. In the same manner, a
sector containing a data address mark will automatically be skipped during the execution of a multisector Read Deleted Data command.
STEP RAT!: INTERVAL. Defines the time interval between step pulses issued by the FDG (track-to-track
access time). Programmable from 1 to 16 milliseconds (in increments of 1 ms).
STATUS REGISTER 0-3. Registers within the FDG that store status information after a command has
been executed. This status information is available to the processor during the Result Phase after
command execution. These registers may only be read after a command has been executed (in the
exact order shown in Table 4 for each command). These registers should not be confused with the Main
Status Register.
SCAN SECTOR INCREMENT. During Scan operations, this parameter is added to the current sector
number in order to determine the next sector to be scanned ..
7-140
Ap·121
Table 6. Status Register Definitions
Bit
Number
Symbol
Description
STATUS REGISTER 0
7,6
IC
INTERRUPT CODE.
00- Normal termination of command. The specified command was
properly executed and completed without error.
01-Abnormal termination of command. Command execution was started
but could not be successfully completed.
1O-Invalid command. The requested command could not be executed.
11- Abnormal termination. During command execution, the disk drive
ready signal changed state.
5
SE
SEEK END. This flag is set (1) when the FOC has completed the Seek
command and the read/write head is positioned over the correct cylinder.
4
EC
EQUIPMENT CHECK ERROR. This flag is set (1) if a fault signal is received
from the disk drive or if the track 0 signal is not received from the disk drive
after 77 step pulses (Recalibrate command).
3
NR
NOT READY ERROR. This flag is set if a read or write command is issued and
either the drive is not ready or the command specifies side 1 (head 1) of a
single-sided disk.
2
H
1,0
OS1,OSO
HEAD ADDRESS. The head address at the time of the interrupt.
DRIVE SELECT. The number of the drive selected at the time of the interrupt.
STATUS REGISTER 1
7
EN
6
END OF TRACK ERROR. This flag is set if the FOC attempts to access a
sector beyond the final sector of the track.
UNDEFINED
5
DE
DATA ERROR. Set when the FOC detects a CRC error in either the 10 field or
the data field of a sector.
4
OR
OVERRUN ERROR. Set (during data transfers) if the FOC does not receive
OMA or processor service within the specified time interval.
3
UNDEFINED
2
NO
SECTOR NOT FOUND ERROR. This flag is set by any of the following
conditions.
a) The FOC cannot locate the sector specified in the Read Data, Read
Deleted Data, or Scan command.
b) The FOC cann,ot locate the starting sector specified in the Read Track
command.
c) The FOC cannot read the 10 field without error during a Read 10
command.
1
NW
WRITE PROTECT ERROR. This flag is set if the FOC detects a write protect
signal from the disk drive during the execution of a Write Data, Write Deleted
Data, or Format Track command.
0
MA
MISSING ADDRESS MARK ERROR. This flag is set by either of the followin!;j
conditions:
a) The FOC cannot detect the 10 address mark on the specified track (after
two rotations of the disk).
b) The FOC cannot detect the data address mark or deleted data address
mark on the specified track. (See also the MO bit of Status Register 2.)
7-141
intJ
AP-121
Table 6. Status Register Definitions (Continued)
Bit
Number
Symbol
Description
STATUS REGISTER 2
UNDEFINED
7
6
CM
CONTROL MARK. This flag is set when the FDC encounters one of the
following conditions:
a) A deleted data address mark during the execution of a Read Data or Scan
command.
b) A data address mark during the execution of a Read Deleted Data
command.
5
DD
DATA ERROR. Set (1) when theFDC detects a CRC error in a sector data
field. This flag is not set when a CRC error is detected in the ID field.
4
WC
CYLINDER ADDRESS ERROR. Set when the cylinder address from ~he disk
sector ID field is different from the current cylinder address maintained within
the FDC.
3
SH
SCAN HiT. Set during the execution of the Scan command if the scan
condition is satisfied.
2
SN
SCAN NOT SATISFIED. Set during execution of the Scan command if the
FDC cannot locate a sector on the specified cylinder that satisfies the scan
condition.
1
BC
BAD TRACK ERROR. Set when the cylinder address from the disk sector ID
field is FF hexadecimal and this cylinder address is different from the current
cylinder address maintained within the FDC. This all "ones" cylinder number
indicates a bad track (one containing hard errors) according to the IBM softsectored format specifications.
0
MD
MISSING DATA ADDRESS MARK ERROR. Set if the FDC cannot detect a
data address mark or deleted data address mark on the specified track.
STATUS REGISTER 3
7
FT
FAULT. This flag indicates the status of the fault signal from the selected disk
drive.
S
WP
WRITE PROTECTED. This flag indicates the status of the write protect signal
from the selected disk drive.
5
RDY
READY. This flag indicates the status of the ready signal from the selected
disk drive.
4
TO
3
TS
, TWO-SIDED. This flag indicates the status of the two-sided signal from the
selected disk drive.
2
H
HEAD ADDRESS. This flag indicates the status of the side select signal for
the currently selected disk drive.
1,0
DS1, DSO
TRACK o. This flag indicates the status of the track 0 signal from the selected
disk drive.
DRIVE SELECT. Indicates the currently selected disk drive number.
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Execution Phase
All data transfers to (or from) the floppy drive occur
during the execution phase. The 8272 has two primary
modes of operation for data transfers (selected by the
specify command):
I) DMA mode
2) non-DMA mode
In the DMA mode, execution phase data transfers are
handled by the DMA controller hardware (invisible to
the driver software). The driver software, however,
must set all appropriate DMA controller registers prior
to the beginning of the disk operation. An interrupt is
generated by the 8272 after the last data transfer, indicating the completion of the execution phase, and the
beginning of the result phase.
In the non-DMA mode, transfer requests are indicated
by generation of an interrupt and by activation of the
RQM flag (bit 7 in the Main Status Register). The interrupt signal can be used for interrupt-driven systems
and RQM can be used for polled systems. The driver
software must respond to the transfer request by reading data from, or writing data to, the FDC. After completing the last transfer, the 8272 generates an interrupt
to indicate the beginning of the result phase. In the
non-DMA mode, the processor must activate the "terminal count" (TC) signal to the FDC (normally by
means of an I/O port) after the transfer request for the
last data byte has been received (by the driver) and
before the appropriate data byte has been read from (or
written to) the FDe.
the TC input is normally set by the DMA controller. In
the non-DMA mode, the processor directly controls the
FDC TC input as previously described. Once the TC
input is received, the FDC stops requesting data transfers (from the system software or DMA controller).
The FDC, however, continues to read data from, or
write data to, the floppy disk until the end of the current disk sector. During a disk read operation, the data
read from the disk (after reception of the TC input) is
discarded, but the data CRC is checked for errors; during a disk write operation, the remainder of the sector is
filled with all-zero bytes.
If the TC signal is not received before the last byte of
the current sector has been transferred to/from the system, the FDC increments the sector number by one and
initiates a read or write command for this new disk
sector.
The FDC is also designed to operate in a multi-track
mode for dual-sided disks. In the multi-track mode
(specified by means of the MT flag in the command
byte-Table 4) the FDC will automatically increment
the head address (from 0 to 1) when the last sector (on
the track under head 0) has been read or written. Reading or writing is then continued on the first sector (sector 1) of head 1.
Drive Status Polling
In either mode of operation (DMA or non-DMA), the.
execution phase ends when a "terminal count" signal is
sensed by the FDC, when the last sector on a track (the
EOT parameter-Table 4) has been read or written, or
when an error occurs.
After the power-on reset, the 8272 automatically enters
a drive status polling mode. If a change in drive status
is detected (all drives are assumed to be "not ready" at
power-on), an interrupt is generated. The 8272 continues this status polling between command executions
(and between step pulses in the Seek command). In this
manner, the 8272 automatically notifies the system
software whenever a floppy disk is inserted, removed,
or changed by the operator.
Multi-Sector and Multi-Track Transfers
Command Details
During disk read/write transfers (Read Data, Write
Data, Read Deleted Data, and Write Deleted Data),
the FDC will continue to transfer data from sequential
sectors until the TC input is sensed. In the DMA mode,
During the command phase, the Main Status Register
must be polled by the driver software before each byte
is written into the Data Register. The DIO (bit 6) and
RQM (bit 7) flags in the Main Status Register must be
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low and high, respectively, before each byte of the command may be written into the 8272. The beginning of
the execution phase for any of these commands will
cause DIO to be set high and RQM to be set low.
ure the drivers for operation in a polled environment
are discussed.
INITIALIZE$DRIVERS
Operation of the FDC commands is described in detail
in Application Note AP-116, "An Intelligent Data
Base System Using the 8272".
Invalid Commands
This initialization procedure must be called before any
FDC operations are attempted. This module initializes
the DRIVE$READY, DRIVE$STATUS$CHANGE,
and
OPERAOPERATION$IN$PROGRESS,
TION$COMPLETE arrays as well as the GLOBAL$DRIVE$NO variable.
If an invalid (undefined) command is sent to the FDC,
the FDC will terminate the command. No interrupt is
generated by the 8272 during this condition. Bit 6 and
bit 7 (010 and RQM) in the Main Status Register are
both set indicating to the processor that the 8272 is in
the result phase and the contents of Status Register 0
must be read. When the processor reads Status Register
o it will find an 80H code indicating that an invalid
command was received. The driver software in Appendix B checks each requested command and will not
issue an invalid command to the 8272.
A Sense Interrupt Status command must be sent after a
Seek or Recalibrate interrupt; otherwise' the FDC will
consider the next command to be an invalid command.
Also, when the last "hidden" interrupt has been serviced, further Sense Interrupt Status commands will result in invalid command codes.
4.0 8272 PHYSICAL INTERFACE
SOFTWARE
PL/M software driver listings for the 8272 FDC are
contained in Appendix A. These drivers have been designed to operate in a DMA environment (as described
in Application Note AP-116, "An Intelligent Data
Base System Using the 8272"). In the following paragraphs, each driver procedure is described. (A description of the driver data base variables is given in Table
7.) In addition, the modifications necessary to reconfig-
EXECUTE$DOCB
This procedure contains the main 8272 driver control
software and handles the execution of a complete FDC
command. EXECUTE$DOCB is called with two parameters: a) a pointer to a disk operation control block
and b) a pointer to a result status byte. The format of
the disk operation control block is illustrated in Figure
2 and the result status codes are described in Table 8.
Before starting the command phase for the specified
disk operation, the command is checked for validity
and to determine whether the FDC is busy. (For an
overlapped operation, if the FDC BUSY flag is set-in
the Main Status Register-the command cannot be
started; non-overlapped operations cannot be started if
the FDC BUSY flag is set, if any drive is in the process
of seeking/recalibrating, or if an operation is currently
in progress on the specified drive.)
After these checks are made, interrupts are disabled in
order to set the OPERATION$IN$PROGRESS flag,
reset the OPERATION$COMPLETE flag, load a
pointer to the current operation control block into the
OPERATION$DOCB$PTR array and set GLOBAL$DRIVE$NO (if a non-overlapped operation is to
be started).
At this point, parameters from the operation control
block are output to the DMA controller and the FDC
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command phase is initiated. After completion of the
command phase, a test is made to determine the type of
result phase required for the current operation. If no
result phase is needed, control is immediately returned
to the calling program. If an immediate result phase is
required, the result bytes are input from the FOC. Otherwise, the CPU waits until the OPERA-
TION$COMPLETE flag is set (by the interrupt service
procedure).
Finally, if an error is detected in the result status code
(from the FOC), an FOC operation error is reported to
the calling program.
Table 7. Driver Data Base
Name
Description
ORIVE$REAOY
A public array containing the current "ready" status of each
drive.
ORIVE$STATUS$CHANGE
A public array containing a flag for each drive. The appropriate
flag is set whenever the ready status of a drive changes.
OPERATION$OOCB$PTR
An internal array of pointers to the operation control block
currently in progress for each drive.
OPERATION$IN$PROGRESS
An internal array used by the driver procedures to determine if a
disk operation is in progress on a given drive.
OPERATION$COMPLETE
An internal array used by the driver procedures to determine
when the execution phase of a disk operation is complete.
GLOBAL$ORIVE$NO
A data byte that records the current drive number for nonoverlapped disk operations.
VALlO$COMMANO
A constant flag array that indicates whether a specified FOC
command code is valid.
COMMANO$LENGTH
A constant byte array specifying the number of command/
parameter bytes to be transferred to the FOC during the
command phase.
ORIVE$NO$PRESENT
A constant flag array that indicates whether a drive number is
encoded into an FOC command.
OVERLAP$OPERATION
A constant flag array that indicates whether an FOC command
can be overlapped with other commands.
NO$RESULT
A constant flag array that is used to determine when an FOC
operation does not have a result phase.
IMMEO$RESULT
A constant flag array that indicates that anFOC operation has a
result phase beginning immediately after the command phase is
complete.
POSSIBLE$ERROR
A constant flag array that indicates if an FOC operation should be
checked for an error status indication during the result phase.
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Address
. Offset
Disk Operation
Control Block (DOCB)
o
DMA$OP
DMA$ADDR
3
DMA$ADDR$EXT
4
DMA$COUNT
6
DISK$COMMAND (0)
7
DISK$COMMAND (1)
8
DISK$COMMAND (2)
9
DISK$COMMAND (3)
10
DISK$COMMAND (4)
11
DISK$COMMAND (5)
12
DISK$COMMAND (6)
13
DISK$COMMAND (7)
14
DISK$COMMAND (8)
15
DISK$RESULT (0)
16
DISK$RESULT (1)
17
DISK$RESULT (2)
18
DISK$RESULT (3)
19
DISK$RESULT (4)
20
DISK$RESULT (5)
21
DISK$RESULT (6)
22
MISC
I
I
Figure 2. Disk Operation Control Block (DOC B) Format
Table 8. EXECUTE$DOCB Return Status Codes
Code
Description
0
NO ERRORS. The specified operation was completed without error.
1
FDC BUSY. The requested operation cannot be started. This error occurs if an
attempt is made to start an operation before the previous operation is completed.
2
FDC ERROR. An error was detected by the FOG during the execution phase of a
disk operation. Additional error information is contained in the result data portion of
the disk operation control block (DOGB.DISK$RESULT) as described in the 8272
data sheet. This error occurs whenever the 8272 reports an execution phase error
(e.g., missing address mark).
3
8272 COMMAND INTERFACE ERROR. An 8272 interfacing error was detected
during the command phase. This error occurs when the command phase of a disk.
operation cannot be successfully completed (e.g., incorrect setting of the 010 flag in
the Main Status Register).
4
8272 RESULT INTERFACE ERROR. An 8272 interfacing error was detected during
the result phase. This error occurs when the result phase of a disk operation cannot
be successfully completed (e.g., incorrect setting of the 010 flag in the Main Status
Register).
5
INVALID FDC COMMAND.
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FDCINT
This procedure performs all interrupt processing for the
8272 interface drivers. Basically, two types of interrupts
are generated by the 8272: (a) an interrupt that signals
the end of a command execution phase and the beginning of the result phase and (b) an interrupt that signals
the completion of an overlapped operation or the occurrence of an unexpected event (e.g., change in the
drive "ready" status).
An interrupt of type (a) is indicated when the FDC
BUSY flag is set (in the Main Status Register). When a
type (a) interrupt is sensed, the result bytes are read
from the 8272 and placed in the result portion of the
disk operation control block, the appropriate OPERATION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS flag is reset.
When an interrupt of type (b) is indicated (FDC not
busy), a sense interrupt status command is issued (to
the FDC). The upper two bits of the result status register (Status Register Zero-STO) are used to determine
the cause of the interrupt. The following four cases are
possible:
I) Operation Complete. An overlapped operation is
complete. The drive number is found in the lower
two bits of STO. The STO data is transferred to the
active operation control block, the OPERATION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS flag is reset.
2) Abnormal Termination. A disk operation has abnormally terminated. The drive number is found in the
lower two bits of STO. The STO data is transferred to
OPERAthe
active
control
block,
the
TION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS flag is reset.
3) Invalid Command. The execution of an invalid command (i.e., a sense interrupt command with no interrupt pending) has been attempted. This interrupt signals the successful completion of all interrupt
processing.
4) Drive Status Change. A change has occurred in the
"ready" status of a disk drive. The drive number is
found in the lower two bits of STO. The DRIVE$READY flag for this disk drive is set to the new
drive "ready" status and the DRIVE$STATUS$CHANGE flag for the drive is also set. In
addition, if a command is currently in progress, the
STO data is transferred to the active control block,
the OPERATION$COMPLETE flag is set, and the
OPERATION$IN$PROGRESS flag is reset.
After processing a type (b) interrupt, additional sense
interrupt status commands must be issued and
processed until an "invalid command" result is returned from the FDC. This action guarantees that all
"hidden" interrupts are serviced.
In addition to the major driver procedures described
above, a number of support procedures are required.
These support routines are briefly described in the following paragraphs.
OUTPUTSCONTROLS$TO$DMA
This procedure outputs the DMA mode, the DMA address, and the DMA word count to the 8237 DMA
controller. In addition, the upper four bits of the 20-bit
DMA address are output to the address extension
latch. Finally, the disk DMA channel is started.
OUTPUTSCOMMAND$TO$FDC
This software module outputs a complete disk command to the 8272 FDC. The number of required command/parameter bytes is found in the COMMAND$LENGTH table. The appropriate bytes are
output one at a time (by calls to OUTPUT$BYTE$TO$FDC) from the command portion of
the disk operation control block.
INPUT$RESULT$FROM$FDC
This procedure is used to read result phase status information from the disk controller. At most, seven bytes
are read. In order to read each byte, a call is made to
INPUT$BYTE$FROM$FDC. When the last byte has
been read, a check is made to insure that the FDC is no
longer busy.
OUTPUT$BVTE$TO$FDC
This software is used to output a single command/parameter byte to the FDC. This procedure waits until
the FDC is ready for a command byte and then outputs
the byte to the FDC data port.
INPUT$BVTE$FROM$FDC
This procedure inputs a single result byte from the
FDC. The software waits until the FDC is ready to
transfer a result byte and then reads the byte from the
FDC data port.
FDC$READV$FOR$COMMAND
This procedure assures that the FDC is ready to accept
a command/parameter byte by performing the following three steps. First, a small time interval (more than
20 microseconds) is inserted to assure that the RQM
flag has time to become valid (after the last byte transfer). Second, the master request flag (RQM) is polled
until it is activated by the FDC. Finally, the DIO flag is
checked to ensure that it is properly set for FDC input
(from the processor).
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FDC$READY$FOR$RESULT
The operation of this procedure is similar to the
FDC$READY$FOR$COMMAND with the following
exception. If the FDC BUSY flag (in the Main Status
Register) is not set, the result phase is complete and no
more data is available from the FDe. Otherwise, the
procedure waits for the RQM flag and checks the DIO
flag for FDC output (to the processor).
The exerciser program is written to operate a standard
single-sided 8" floppy disk drive in either the single- or
double-density recording mode. Only the eight parameters listed in Table 9 must be specified. All other parameters are derived from these 8 basic variables.
Each of these logical interface procedures is described
in the following paragraphs (refer to the listing in Appendix B).
OPERATION$CLEAN$UP
SPECIFY
This procedure is called after the execution of a disk
operation that has no result phase. OPERA TION$CLEAN$UP
resets
the
OPERA TION$IN$PROGRESS flag and the GLOBAL$DRIVE$NO variable if appropriate. This procedure is also called to
clean up after some disk operation errors.
This procedure sets the FDC signal timing so that the
FDC will interface correctly to the attached disk drive.
The SPECIFY procedure requires four parameters, the
step rate (SRT), head load time (HLT), head unload
time (HUT), and the non-DMA mode flag (ND). This
procedure builds a disk operation control block (SPECIFY$DOCB) and passes the control block to the
FDC driver module (EXECUTE$DOCB) for execution. (Note carefully the computation required to transform the step rate (SRT) into the correct 8272 parameter byte.)
Modifications for Polling Operation
To operate in the polling mode, the following modifica-·
tions should be made to the previous routines:
1) The OUTPUT$CONTROLS$TO$DMA routine
should be deleted.
2) In EXECUTE$DOCB, immediately prior to WAIT$FOR$OP$COMPLETE, a polling loop should be
inserted into the code. The loop should .test the
RQM flag (in the Main Status Register). When
RQM is set, a data byte should be written to, or read
from, the 8272. The buffer address may be computed
from the base address contained in DOCB.DMA$ADDR and DOCB.DMA$ADDR$EXT. After the
correct number of bytes have been transferred, an
operation complete interrupt will be issued by the
FDC. During data transfer in the non-DMA mode,
the NON-DMA MODE flag (bit 5 of the Main
Status Register) will be set. This flag will remain set
for the complete execution phase. When the transfer
is finished, the NON-DMA MODE flag is reset and
the result phase interrupt is issued by the FDC.
RECALIBRATE
This procedure causes the floppy disk read/write head
to retract to track O. The RECALIBRATE procedure
requires only one parameter-the drive number on
which the recalibrate operation is to be performed. This
procedure builds a disk operation control block (RECALIBRATE$DOCB) and passes the control block to
the FDC driver for execution.
SEEK
This procedure causes the disk read/write head (on the
selected drive) to move to the desired cylinder position.
The SEEK procedure is called with three parameters:
drive number (DRV), head/side number (HD), and
cylinder number (CYL). This software module builds a
disk operation control block (SEEK$DOCB) that is executed by the FDC driver.
5.0 8272 LOGICAL INTERFACE
FORMAT
SOFTWARE
Appendix B of this Application Note contains a PL/M
listing of an exerciser program for the 8272 drivers.
This program illustrates the design of logical interface
level procedures to specify disk parameters, recalibrate
a drive, seek to a cylinder, format a disk, read data, and
write data.
The FORMAT procedure is designed to initialize a
complete floppy disk so that sectors can subsequently
be read and written by system and application programs. Three parameters must be supplied to this procedure: the drive number (DR V), the recording density
(DENS), and the interleave factor (INTLVE). The
FORMAT procedure generates a data block
(FMTBLK) and a disk operation control block (FORMAT$DOCB) for each track on the floppy disk (normally 77).
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Table 9. Basic Disk Parameters
Name
Description
DENSITY
The recording mode (FM or MFM).
FILLER$BYTE
The data byte to be written in all sectors during formatting.
TRACKS$PER$DISK
The number of cylinders on the floppy disk.
BYTES$PER$SECTOR
The number of bytes in each disk sector. The exerciser accepts 128,
256, and 512 in FM mode, and 256, 512, and 1024 in MFM mode.
INTERLEAVE
The sector interleave factor for each disk track.
STEP$RATE
The disk drive step rate (1-16 milliseconds).
HEAD$LOAD$TIME
The disk drive head load time (2-254 milliseconds).
HEAD$UNLOAD$TIME
The head unload time (16-240 milliseconds).
The format data block specifies the four sector ID field
parameters (cylinder, head, sector, and bytes per sector) for each sector on the track. The sector numbers
need not be sequential; the interleave factor (INTLVE
parameter) is used to compute the logical to physical
sector mapping.
After both the format data block and the operation
control block are generated for a given cylinder, control
is passed to the 8272 drivers for execution. After the
format operation is complete, a SEEK to the next cylinder is performed, a new format table is generated, and
another track formatting operation is executed by the
drivers. This track formatting continues until all tracks
on the diskette are formatted.
In some systems, bad tracks must also be specified
when a disk is formatted. For these systems, the existing FORMAT procedure should be modified to format
bad tracks with a cylinder number of OFFR.
Write
The WRITE procedure transfers a complete sector of
data to the disk drive. Five parameters must be supplied to this software module: the drive number (DRV),
the cylinder number (CYL), the head/side number
(RD), the sector number (SEC) and the recording density (DENS). This procedure generates a disk operation
control block (WRITE$DOCB) from these parameters
and passes the control block to the 8272 driver for execution. When control returns to the calling program,
the data has been transferred to disk.
Read
This procedure is identical to the WRITE procedure
except the direction of data transfer is reversed. TheREAD procedure transfers a sector of data from the
floppy disk to system memory.
Coping with Errors
In actual practice all logical disk interface routines
would contain error processing mechanisms. (Errors
have been ignored for the sake of simplicity in the exerciser programs listed in Appendix B.) A typical error
recovery technique consists of a two-stage procedure.
First, when an error is detected, a recalibrate operation
is performed followed by a retry of the failed operation.
This procedure forces the drive to seek directly to the
requested cylinder (lowering the probability of a seek
error) and attempts to perform the requested operation
an additional time. Soft (temporary) errors caused by
mechanical or electrical interference .do not normally
recur during the retry operation; hard errors (caused by
media or drive failures), on the other hand, will continue to occur during retry operations. If, after a number
of retries (approximately 10), the operation continues
to fail, an error message is displayed to the system operator. This error message lists the drive number, type of
operation, and failure status (from the FDC). It is the
operator's responsibility to take additional action as required.
6.0 FILE SYSTEMS
The file system provides the disk I/O interface level
most familiar to users of interactive microcomputer and
minicomputer systems. In a file system, all data is
stored in named disk areas called files. The user and
applications programs need not be concerned with the
exact location of a file on the disk-the disk file system
automatically determines the file location from the file
name. Files may be created, read, written, modified,
and finally deleted (destroyed) when they are no longer
needed. Each floppy disk typically contains a directory
that lists all the files existing on the disk. A directory
entry for a file contains information such as file name,
file size, and the disk address (track and sector) of the
beginning of the file.
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File Allocation
The Intel File System
File storage is actually allocated on the disk (by the file
system) in fixed size areas called blocks. Normally a
block is the same size as a disk sector. Files are created
by finding and reserving enough unused blocks to cone
tain the data in the file. Two file allocation methods are
currently in widespread use. The first method allocates
blocks (for a file) from a sequential pool of unused
blocks. Thus, a file is always contained in a set of sequential blocks on the disk. Unfortunately, as files are
created, updated, and deleted, these free-block pools become fragmented (separated from one another). When
this fragmentation occurs, it often becomes impossible
for the file system to create a file even though there is a
sufficient number of free blocks on the disk. At this
point, special programs must be run to "squeeze" or
compact the disk, in order to re-create a single contiguous free-block pool.
The Intel file system (described in detail in the RMX80 Users Guide) uses the second disk file allocation
method (previously discussed). In order to lower the
system overhead involved in finding free data blocks,
the Intel file system incorporates a free space management data structure known as a bit map. Each disk
sector is represented by a single bit in the bit map. If a
bit in the bit map is set to I, the corresponding disk
sector ~Ia, been allocated. A zero in the bit map indicates that the corresponding sector is free. With this
technique, the process of allocating or freeing a sector is
accomplished by simply altering the bit map.
The second file allocation method uses a more flexible
technique in which individual data blocks may be located anywhere on the disk (with no restrictions). With
this technique, a file directory entry contains the disk
address of a file pointer block rather than the disk address of the first data block of the file. This file pointer
block contains pointers (disk addresses) for each data
block in the file. For example, the first pointer in the
file pointer block contains the track and sector address
of the first data block in the file; the second pointer
contains the disk address of the second data block, etc.
In practice, pointer blocks are usually the same size as
data blocks. Therefore, some files will require multiple
pointer blocks. To accommodate this requirement without loss of flexibility, pointer blocks are linked together,
that is, each pointer block contains the disk address of
the following pointer block. The last pointer block of
the file is signaled by an illegal disk address (e.g., track
0, sector 0 or track OFFH, sector OFFH).
File names consist of a basic file name (up to six characters) and a file extension (up to three characters). The
basic file name and the file extension are separated by a
period (.). Examples of valid file names are:
DRIV72.0BJ, XX.TMP, and FILE.CS. In addition,
four file attributes are supported (see Figure 3 for attri.
bute definitions).
The bit. map and the file directory are placed on prespecified disk tracks (reserved for system use) beginning at track zero.
Disk File System Functions
Table 2 illustrates the typical functions implemented by
a disk file system. As an example, the disk directory
function (DIR) lists disk file information on the console
display terminal. Figure 3 details the contents of a display entry in the Intel file system. The PL/M procedure outlined in Figure 4 illustrates a disk directory
algorithm that displays the file name, the file attributes,
and the file size (in blocks) for each file in the directory.
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'-----1
O· INVISIBLE
1· SYSTEM
2· WRITE· PROTECT
3
(RESERVED)
.1
:: f
6·
7· FORMAT
207885-5
Directory Entry
Presence is a fla~ that can contain one of three values:
OOOH- The file associated with this entry is present on the disk.
07FH- No file is associated with this entry; the content of the rest of the entry is undefined. The first
entry with its flag set to 07FH marks the current logical end of the directory and directory
searches stop at this entry.
OFFH- The file named in this entry once existed on the disk but is currently deleted. The next file added
to the directory will be placed in the first entry marked OFFH. This flag cannot, therefore, be used
to (reliably) find a file that has been deleted. A value of OFFH should be thought of as simply
marking an open directory entry.
File Name is a string of up to 6 non-blank ASCII characters specifying the name of the file associated with
the directory entry. If the file name is shorter than six characters, the remaining bytes contain binary zeros.
For example, the name ALPHA would be stored as: 414C50484100H.
Extension is a string of up to 3 non-blank ASCII characters that specifies an extension to the file name.
Extensions often identify the type of data in the file such as OBJ (object module), or PLM (PL/M source
module). As with the file name, unused positions in the extension field are filled with binary zeros.
Attributes are bits that identify certain characteristics of the file. A 1 bit indicates that the file has the
attribute, while a 0 bit means that the file does not have the attribute. The bit positions and their corresponding attributes are listed below (bit 0 is the low-order or rightmost bit, bit 7 is the leftmost bit):
0:
Invisible. Files with this attribute are not listed by the ISIS-II DIR command unless the I switch is used.
All system files are invisible.
1:
System. Files with this attribute are copied to the disk in drive 1 when the S switch is specified with the
ISIS-II FORMAT command.
2:
Write-Protect. Files with this attribute cannot be opened for output or update, nor can they be deleted
or renamed.
3-6: These positions are reserved for future use.
7:
Format. Files with this attribute are treated as though they are write-protected. In addition, these files
are created on a new diskette when the ISIS-II FORMAT command is issued. The system files all have
the FORMAT attribute and it should not be given to any other files.
Figure 3. Intel Directory Entry Format
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AP-121
EOF Count contains the number "of the last byte in the last data block qfthe file. If the value of this field is
080H, for example, the last byte in the file is byte number 128 in the last data block (the last block is full).
Number of Data Blocks is an address variable that indicates the number of data blocks currently used by the
file. ISIS-II and the RMX/80 Disk File" system both maintain a counter called LENGTH that is the current
"
number of bytes in the file. This is calculated as:
(Number of Data
Blocks - 1) x 128 + EOF Count.
, Header Block Pointer is the address of the file's header block. The high byte of the field is the sector number
and the low byte is the track number. The system "finds" a disk file by searching the directory for the name
and then using the header block pointer to seek to the beginning of the file.
Figure 3. Intel Directory Entry Format (Continued)
dir: procedure(drv,dens)
declare dry
dens
sector
size (5)
public;
byte,
byte,
byte,
byte,
byte,
based rdbptr structure (presence byte,
file$name(6) byte ,extension (3) byte,
attribute byte,eof$count byt~,
data$blocks address,header$ptr address),
byte,
invisible$f1aq
system$flaq
protected$f1aq
format$flaq
literally
literally
li terally
literally
i
dir$ptr
dir$entry
'1',
'2',
'4',
'SOH';
/. The disk directory starts at cylinder I, sector 2 ./
call seek(drv,l,O);
do sector=2 to 26;
call read(drv,l,O,sector,dens);
do dir$ptr=O to 112 by 4;
if dir$entry.presence=7FH then return;
if dir$entry.presence=O
then do;
do i=O to 5; call co(dir$ent~y.fi1e$name(i)); end;
call co(period);
do i=O to 2; call co(dir$entry.extension(i)); end;
do i=O to 4; call co(space); end;
call convert$to$decima1(@siz~,dir$entry.data$blocks);
do i=O to 4; call co(size(i)); end;
I f (dir$entrv.attribute and invisible$f1aq) <> 0 then call co('I');
If (dir$entry.attribute and system$flaq) <> 0 then call co('S'),
If (dir$entry.attribute and protected$flaq) <> 0 then call co('W');
If "(dir$entry.attribure and format$flaq) <> 0 then call co('F');
endJ
end;
end;
end dir;
207885-6
Figure 4. Sample PL/M Directory Procedure
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AP-121
7.0 KEY 8272 SOFTWARE
INTERFACING CONSIDERATIONS
This section contains a quick review of Key 8272 Software design features and issues. (Most items have been
mentioned in other sections of this application note.)
Before designing 8272 software drivers, it is advisable
that the information in this section be thoroughly understood.
1. Non-DMA Transfers
In systems that operate without a DMA controller (in
the polled or interrupt driven mode), the system software is responsible for counting data transfers to/from
the 8272 and generating a TC signal to the FDC when
the transfer is complete.
2. Processor Command/Result Phase Interface
In the command phase, the driver software must write
the exact number of parameters in the exact order
shown in Table 5. During the result phase, the driver
must read the complete result status. For example, the
Format Track command requires six command bytes
and presents seven result bytes. The 8272 will not accept a new command until all result bytes are read.
Note that the number of command and result bytes
varies from command-to-command. Command and result phases cannot be shortened.
During both the command and result phases, the Main
Status Register must be read by the driver before each
byte of information is read from, or written to, the
FDC Data Register. Before each command byte is written, DIO (bit 6) must be low (indicating a data transfer
from the processor) and RQM (bit 7) must be high
(indicating that the FDC is ready for data). During the
result phase, DIO must be high (indicating a data
transfer to the processor).
NOTE:
After the 8272 receives a command byte, the RQM
flag may remain set for approximately 16 microseconds (with an 8 MHz clock). The driver should not
attempt to read the Main Status. Register before this
time interval has elapsed; otherwise, the driver may
erroneously assume that the FDC is ready to accept
the next byte.
3. Sector Sizes
The 8272 does not support 128 byte sectors in the
MFM (double-density) mode.
4. Drive Status Changes
The 8272 constantly polls all drives for changes in the
drive ready status. This polling begins immediately fol-
lowing RESET. An interrupt is generated every time
the FDC senses a change in the drive ready status. After reset, the FDC assumes that all drives are "not
ready". If a drive is ready immediately after reset, the
8272 generates a drive status change interrupt.
5. Seek Commands
The 8272 FDC does not perform implied seeks. Before
issuing a data read or write command, the read/write
head must be positioned over the correct cylinder by
means of an explicit seek command. If the head is not
positioned correctly, a cylinder address error is generated.
6. Interrupt Processing
When the processor receives an interrupt from the
FDC, the FDC may be reporting one of two distinct
events:
a) The beginning of the result phase of a previously
requested read, write, or scan command.
b) An asynchronous event such as a seek/recalibrate
completion, an attention, an abnormal command termination, or an invalid command.
These two cases are distinguished by the FDC BUSY
flag (bit 4) in the Main Status Register. If the FDC
BUSY flag is high, the interrupt is of type (a). If the
FDC BUSY flag is low, the interrupt was caused by an
asynchronous event (b).
A single interrupt from the FDC may signal more than
one of the above events. After receiving an interrupt,
the processor must continue to issue Sense Interrupt
Status commands (and service the resulting conditions)
until an invalid command code is received. In this manner, all "hidden" interrupts are ferreted out and serviced.
7. Skip Flag (SK)
The skip flag is used during the execution of Read
Data, Read Deleted Data, Read Track, and various
Scan commands. This flag permits the FDC to skip
unwanted sectors on a disk track.
When performing a Read Data, Read Track, or Scan
command, a high SK flag indicates that the FDC is to
skip over (not transfer) any sector containing a deleted
data address mark. A low SK flag indicates that the
FDC is to terminate the command (after reading all the
data in the sector) when a deleted data address mark is
encountered.
When performing a Read Deleted Data command, a
high SK flag indicates that sectors containing normal
7-153
AP-121
data address marks are to be skipped. Note that this is
just the opposite situation from that described in the
last paragraph. When a data address mark is encountered during a Read Deleted Data command (and the
SK flag is low), the FDC terminates the command after
reading all the data in the sector.
8. Bad Track Maintenance
The 8272 does not internally maintain bad track information. The maintenance of this information must be
performed by system software. As an example of typical bad track operation, assume that a media test determines that track 31 and track 66 of a given floppy disk
are bad. When the disk is formatted for use, the system
software formats physical track 0 as logical cylinder 0
(C = 0 in the command phase parameters), physical
track 1 as logical track 1 (C = 1), and so on, until
physical track 30 is formatted as logical cylinder 30
(C = 30). Physical track 31 is bad and should be formatted as logical cylinder FF (indicating a bad track).
Next, physical track 32 isformatted as logical cylinder
31, and so on, until physical track 65 is formatted as
logical cylinder 64. Next, bad physical track 66 is formatted as logical cylinder FF (another bad track marker), and physical track 67 is formatted as logical cylinder 65. This formatting continues until the last physical
track (77) is formatted as logical cylinder 75. Normally,
after this formatting is complete, the bad track information is· stored in a prespecified area on the floppy disk
(typically in a sector on track 0) so that the system will
be able to recreate the bad track information when the
disk is removed from the drive and reinserted at some
later time.
To illustrate how the system software performs a transfer operation on a disk with bad tracks, assume that the
disk drive head is positioned at track 0 and the disk
described above is loaded into the drive. If a command
to read track 36 is issued by an application program,
the system software translates this read command into
a seek to physical track 37 (since there is one bad track
between 0 and 36, namely 31) followed by a read of
logical cylinder 36. Thus, the cylinder parameter C is
set to 37 for the Seek .command and 36 for the Read
Sector command.
REFERENCES
1. Intel, "8272 Single/Double Density Floppy Disk
Controller Data Sheet," Intel Corporation, 1980.
2. Intel, "An Intelligent Data Base System UsiIi.g the
8272," Intel Application Note," AP-116, 1981.
3. Intel, iSBC 208 Hardware Reference Manual, Manual Order No. 143078, Intel Corporation, 1980.
4. Intel, RMX/80 User's Guide, Manual· Order No.
9800522, Intel Corporation, 1978.
5. Brinch Hansen, P., Operating System Principles,
Prentice-Hall, Inc., New Jersey, 1973.
6. Flores, I., Computer Software: Programming Systems for Digital Computers, Prentice-Hall, Inc.,
New Jersey, 1965.
7. Knuth, D. E., Fundamental Algorithms, AddisonWesley Publishing Company, Massachusetts, 1975.
8. Shaw, A. C., The Logical Desig!1 of Operating Systems, Prentice-Hall, Inc., New Jersey, 1974.
9. Watson, R. W., Time Sharing System Design Concepts, McGraw-Hill, Inc., New York, 1970.
10. Zarrella, J., Operating Systems: Concepts and Principles, Microcomputer Applications, California,
1979.
7-154
intJ
AP-121
APPENDIX A
8272 FDC DEVICE DRIVER SOFTWARE
PL/M-86 COMPILER
8272 FLOPPY DISK CONTROLLER DEVICE DRIVERS
ISIS-II PL/M-86 Vl. 2 COMPILATION OF MODULE DRIVERS
OBJECT MODULE PLACED IN :F1:driv72.0BJ
COMPILER INVOKED BY, p1m86 :F1:driv72.p86 DEBUG
$title{"S272 floppy disk controller device drivers")
$nointvecto[
Soptimi ze 121
Slarge
drivers:
do~
declare
1* floppy disk port definitions */
fdc$status$nort
fdcSdata$port
1* 8272 status POtt */
/* 8272 data port */
literally '30H'",
literally "3IH";
declare
l* floppy disk commands *1
sense$int$statu9
Ii terallv "OSH":
declare
1* interrupt definitions */
fdc$intSlevel
literally '"33";
1* fde interrupt level ttl
declare
/* return status and error codes ." /
error
literally "'0"',
~ropagatp.$error
literally
literally
literally
literally
literally
literally
"'1"',
"'3",
"0" r
"1"",
"not",
""return error'" ,
stat$ok
stat$busv
stat$error
statScommand$err or
statSresult$error
stat$invalid
literally
literally
literally
literally
literally
literally
'a' •
literally
literally
literall";
literallv
literally
Ii terally
literally
"lOa"" ,
ok
complete
false
true
errorSin
declare
/* masks *1
busy$mask
DIO$mask
RQM$mask
seek$mask
result$error$mask
resutt$dr ive$mask
resutt$ready$mask
declare
1* drive numbers */
max$no$dr i ves
fdc$general
/* fdc operation completed withc;:mt errors *1
1* fde is husy, operation cannot be started *1
/* fde operation error *1
1* fdc not ready for command, phaF.le * I
/* fde not ready for tAsul t phase *1
1* invalid fdc command */
'1' •
'2' •
'3' •
'4' •
'5' ,
'40H' ,
'80H' •
'OFH'" ,
'OCOR' •
'03H' •
'"OBH'";
literally '3'" ,
literally '4' ,
neclare
1* miscellaneous control *1
any$dr ive$seeking
Ii terally , ( (input (fdc$statuB$port) and, seek$mask) <> 0)',
commandScode
literally'" (docb.disk$command(O) and IP'H)"';
DtO$setSfor$input
literallY'" «input(fdcSstatus$port) anq DIO$mask)-O) '""
DIO$set$for$output
literally '"«input(fdc$status$port) and DIO$mask)<>O''",
extract$drive$no
literally '" (docb.disk$command(l) and 038)',
fdc$busv
.literallY , «(input (fdc$status$pori:.) and bUBv$mask) <> -0)',
no$fdc$error
Ii terally 'possible$error (command$code) and «docb.disk$result (0)
and resul t$error$mask) = 0)',
wai t$for$op$complete 1 i terallv "'do while not operation$complete (drive$no): end',
wait$for$RQM'
literally 'do while (input (fdc$status$port) and RQM$mask) .. 0, end,':
declare
1* structures "*1
docb$type
literally
/* disk operation control block "*1
,. (dma$op byte,dma$addr word, dma$addr$ext bvte,dma$count word,
disk$command(9) byte.disk$result(7) byte,misc byte) "'1
Seject
10
declare
drive$statu5$change(4) byte public,
1* when set - indicates that drve status changed *1
1* current status of drives *1
drive$readyl41 byte public,
207885-7
7-155
inter
11
AP-121
declare
internal flags for; operation with multiple drives ttl
fde execution phase completed 'It/
pointers for operations in progress */
temporary docb for interrupt processing */
drive number of non-overlapped operation
operation$in$progres5 (5) byte,
operation$complete(S) byte,
operation$docb$ptr (5) pointer,
i ntee rupt$docb s tr ucture docbS type,
global$dr i ve$no byte 1
in progress 12
i f lInv */
declare
/* internal vectors that contain command operational information *1
no$r~slllt (32) byte
1* no result phase to command */
data (0,0, 0.1, 0, 0, 0,0,0, 0,0 ,0,0, 0 ,0, 0 ,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0),
immed$result(32) byte
1* immediate result phase for command *1
data (0, 0, 0, 0, 1, 0, 0,0, 1, 0,0, O. 0, 0,0, 0, 0,0, 0,0, 0,0,0,0,0,0,0 ,0,0,0 ,0,0) ,
overlap$operation(32) byte
1* command permits overlapped operation of drvies ./
data (0, 0, 0, o. 0,0,0,1, 0,0, 0, 0, o~ 0,0,1,0,0,0,0, 0,0,0.0,0,0,0,0,0,0,0,0) ,
driveSno$present (32) byte
I· drive number present in command information . /
data (0,0,1,0,1.1,1,1, 0,1,1,0,1,1,0,1,0,1,0.0,0,0.0,0,0,1,0,0,0, 1 ~ 0, a I ,
~os5ib1e$error (32) byte
/. determines if command can return with an error "/
data (0,0, 1;0,0, 1,1,1,1,1,1,0,1,1,0, I,D, 1.0,0,0, 0,0.0,0, 1,0,0,0,1,0,0) ,
command$length(32) byte
1* contains number of command bytes for each command ./
data (0, 0, 9, 3, 2,9, 9, 2, 1,9, 2, 0,9 ,6,0.3,0,9,0,0, 0,0,0 .0,0 .9,0,0,0 ,9 ,0,0) ,
valid$command (32) . bvte
I. flags inva1 id command codes "I
data (0,0, 1, 1,1,1,1,1,1,1,1, 0,1,1,0,1,0,1,0 ,0,0,0, 0.0,0,1, O. 0,0,-1,0,0) ;
$eject
I· .. • initialIzation for the 8272 fdc driver .soft .... are. This procedure must
be called prior to execution of any driver software.
·'''1
13
I'
initia1ize$drivers: procedure public;
/tt initialize 8272 drivers .. /
declare drv$no byte:
15
l6
17
18
19
20
do drv$no=O to max$no$dr i yes i
o1r ive$ready (drvSno) ::false;
r:1r ive$statusSchange (drv$no) =false;
operationS in$progress (drvSno) =false;
operationScomplete (drv$no) =false:
end;
21
22
23
operationS in$progress (fde$general) ",false;
operation$complete (fdc$general) =false;
globalSdr i veSno=O;
2.
end initialize$dr1vers;
/U •• wi!lit until the 8272 fdc is ready to receive command/parameter bytes
in the command phase. The 8272 is ready to receive command bytes
when the ROM fla9 is high and the 010 flag is low.
.. •• /
25
fdcSreadySfor$comrnand: procedure byte;
26
/ .. wait for valid flag settings in status reqister */
call time(ll;
27
/1t wait for "masteor request" flag 1t/
waitSforSRQM;
/* check data direction flag * /
30
i f DIO$set$for$input
32
then return ok;
else return error;
33
end fde$ready$for$command;
/ ..... wait unti 1 the 8272 fde is ready to
phase. The 9272 is ready to return
flags are both high. The busy flag
remain set unti t the last data byte
by the processor.
..* ... /
34
35
36
return data bytes in the result
a result byte when the ROM and DIO
in the main status register will
of the result phase has be!?n read
fde$read..,Sfor$resul t: procedure byte;
/ .. wait for valid settings in status register .. /
call time (1);
/ .. resul t phase has ended when the, 8272 busy flag is reset .. /
if no't fdc$busy
then return complete;
207885-8
7-156
inter
AP-121
1* wait for "master request" flag *1
wait$forSRQM;
36
1* check data directton flag *1
41
i f DIO$setSfor$output
then return ok;
else return
43
~rror;
end fdcSreadvSfor $[" esul t;
44
/ . . . . output a single command/parameter byte to the 8272 fde.
parameter is the byte to he output to the fde.
.*.*/
.,
The "data$byte"
outputSbyte$toSfdc: procedure (data$byte) byte,
declare data$byte byte:
46
1* check to see if fde is
47
n~ady
for command
*1
if not fdc$readvSfor$command
then propagateSerror
49
i
output (fdc$data$port) ""dataSbyte:
return ok:
50
au tputS byteS to$ fde;
en~
51
1*··· parameter
input a
singl~ result byte from the 8272 fdc.
The "data$byte$ptr"
is a pointer to the memory location that is to contain
the input byte.
.***/
52
53
54
input$byteSfromSfdc: procedure (dataSbyte$ptr) byte:
1eclare data$byteSptr pointer;
1eclare
dataSbyte based data$byte$ptr bvte,
status byte:
/*
55
56
check to see if fdc is ready */
!5tatl.ls=fdc$readySforSresult:
.
if errorS in status
then propagateSerror;
56
1* check for result phase complete */
if status=complete
then return complete;
"0
61
62
2
1
2
-iataSbyte=input (fdc$data$port);
return ok;
end input$byteSfrom$fdc:
Seject
/****
63
64
65
66
output the dma mode, the dma address, and the dma word count to the
8237 dma controller. Also output the high order four hits of the
address to the address extension latch. Finally, stal::t the disk
dma ch.!lnnel. The "docb$ptr" parameter is a ·pointer to the appropriate
disk operation contl::ol block.
****/
outputScontrolsS toSdma: procedul::e (docb$ptr) ;
declare docb$ptl:: pointer;
declal::e docb based docb$ptr structul::e docbtype;
declare
/* dma port definitions */
dma$uppel::$addr$port
literally
dmaSdiskSaddr$pol::t
literally
dmaSdisk$word$count
literally
dma$command$port
literally
drna$mode$port
literally
dma$mask$sr$port
literally
dma$clearSffSport
literally
dmaSmaster$clearSport literally
dma$mask$port
literally
dma$diskSchan$star t
dmaSextended$wr i te
dmaS sing leS trans fer
67
69
70
"'IOH",
"OOH",
"OIH"',
"aSH",
"OBH",
"OAH"',
"OCH",
"ODH",
"OFH",
literally "OOH",
literally "shl (l,s)",
literally"shl(1,6)";
/* upper 4 bits of current address */
/* current address par t ." /
/* word count port */
/* command por t * /
/* mode port */
1* mask set/reset port */
/* clear fil::st/last flip-flop port */
/* drna master clear port */
/* parallel mask set port* I
/* drna mask to start disk channel */
/* extended wr i te flag * /
/* single transfer flag */
if docb.dma$op < 3
then do;
/* set drna mode and clear first/last flip-flop */
output (dma$mode$port) ""shl (docb .dma$op, 2) or 40H:
output (dma$cleal::$ffSport) =0;
207885-9
7-157
inter
AP-121
1* set dma address */
output (dmaSdi sk$addr$port) =10w (docb.dma$addr) :
71
72
73
output (dma$disk$addr$port) =high (docb.dma$addr) ;
output (dma$upper$addr$port 1 =docb.dma$addr$ext;
/* outout disk transfer word count to dma controller ttl
74
OIJtput -(dmaSdisk$wordScount) ==low (docb.dma$count) ;
output (dmaSdi sk$wordScount) =high (dach .dma$count) ;
75
/* start dma channel 0 for fde */
76
77
78
output (dmaSmaskSsr$port) =dma$di skSchan$start t
end;
end output$controls$to$dmai
1****
79
80
81
82
output a high-level disk command to the 8272 fdc.
The number of bytes
required for each command is contained in the "cornmand$length" table.
The "docb$ptr" para!lleter is a pointer to the appropriate disk operation
control block.
*'***/
output$command$to$fdc: procedure (docb$ptr) byte;
declare docb$ptr pointer;
declare
docb based docb$ptr structure docb$type,
crnd$byte$no byte;
nisable;
;* output all command bytes to the fdc */
83
84
89
90
91
92
do cmd$byteSno=O to commandS length (command$code) -1;
if errorS in output$byteStoSfdc (docb.disIc;Scommand (cmd$byteSno))
then do, enable; propagateSerror;, end~
end;
enable;
return ok;
end output$commandStoSfdc;
;**U input the result data from the
8272 fdc during the result phase (after
command execution). The ndocb$ptr" parameter is a pointer to the
appropriate disk operation control block.
****/
93
94
95
i nput$resul t$ feamS fdc: procedure (docb$ptr) byte;
declare docb$ptr pointer;
declare
doeb based doeb$ptr structure doeb$tvpe,
result$byte$no byte,
temp byte,
status byte,
96
disable;
97
do r<::osult$byte$no=O to 7;
status=input$byte$from$fde (@temp);,
if error$in status
then do, enable; ?ropaqate$error; end;
i f status=complete
then do; enable; return ok; end;
docb.disk$resul t (resul tSbyte$no) =temp:
98
99
104
109
110
ll1
112
114
115
end;-
enable;
i f fdcSbusy
then return error;
else return OK;
end input$result$frorn$fdc,
1**** cleans up after the execution of a disk operation that has no result
phase. The 'Procedure is also used after some disk operation errors.
"drv" is the drive number. and "ce n is the command code for the'
disk operation.
****!
116
117
118
119
ol;leration$clean$up: procedure (drv ,cc) ;
declare (drv,ee) byte;
disable;
operationSin$progress (drv) =false ~
207885-10
7-158
intJ
AP-121
120
if not overlap$operation(cc)
then global$dr i ve$no=O I
122
enable:
123
end operationSclean$up:
$eject
1****
execute the disk operation
parameter "docb$ptr". The
a byte variable that is to
operation when it has been
possible on return:
control block specified by the pointer
"status$ptr n parameter is a pointer to
contain the status of the requested
completed. Six status conditions are
The specified operation was completed without error.
The rdc is busy and the requested operation cannot be started.
Fdc error (further information is contained in the result
storage portion of the disk operation control block - as
described in the 8272 data sheet).
Transfer error during output of the command bytes to the fdc.
Transfer error during input of the result bytes from the fdc.
Invalid fdc command.
****/
124
execute$docb: procedure (docb$ptr, status$ptr) public ~
/* execute a disk operation control block */
125
126
declare docb$ptr pointer, status$ptr pointer:
declare
docb based docb$ptr structure docb$type,
status based status$ptr byte,
drive$no byte~
/* check command validity */
127
if not val idScommand (command$code)
then do; status-stat$invalid: return:
end~
/* determine if command has a drive number field - if not, set the drive
number for a general fdc command *1
if driveSno$present (command$code)
then dr ive$no=extract$dr ive$no:
else dr ive$no=fdc$general:
132
134
/* an overlapped operation can not be performed if the fdc is busy *1
135
. if over lap$oper at ion (command$code) and fdc$busy
then do; status-stat$busy; return; end1
/* for a non-overlapped operation, check fdc busy or any drive seeking *1
140
if not overlap$operation(commarid$code) and (fdc$busy or
then do; status~8tat$busy; return: end;
any$drive$5e~king)
1* check for drive operation in progress - if none, set flag and start operation *1
145
disable,
if operation$in$progress (drive$no)
then do: enable~ status=stat$busYi return; end:
else operatlon$in$progress (dt ive~no) -true;
146
152
1* at this point, an fdc operation is about to begin, so:
1. reset the operation complete flag
2. set the docb pointer for the current operation
3. if this is not an overlapped operation, set the global drive
number for the subsequent result phase interrupt.
operation$complete (drive$no) =0:
operation$docb$ptr (drive$no) =docb$ptr;
153
154
i.55
157
158
159
161
162
163
164
165
167
168
169
170
2
"*1
if not overlap$operation (command$code)
then global$dr i ve$no-dr i ve$no+ l:
enable,
call output$controls$to$dma (docb$ptr) ;
if errorS in output$command$to$fdc (docb$ptr)
then dor
.
call operation$clean$up(drive$no,command$code);
status:::;stat$command$error;
return;
end;
1*. return immediately if the command has no result phase or completion interrupt - specify *1
if no$result (command$code)
then do;
call operation$clean$up(drive$no,comrnand$code)
statlJs=stat$ok:
return:
end:
1
207885-'11
7-159
intJ
AP-121
171
if immed$result (command$code)
then do:
if errorS in input$resul t$from$fdc (docb$ptr)
173
then do;
175
176
177
178
179
180
181
183
188
189
191
192
call operation$cleanSup(drlve$no,commandScoc1e);
status""stat$resul t$error 7
return;
end,
end;
else do:
wai t$for$op$complete:
if dacb.mise = error
]'
end;
then do: status"'statSresult$error: return; end:
if nO$fdcSerror
then status=stat$ok:
else status=statSerror;
end .xecute$docb:
$eject
/**** copy disk command results from the interrupt control block to the
currently active disk operation control block if a disk operation is
in pr09'ress.
****/
193
194
195
196
198
199
202
203
204
205
206
copy$ intSresult: procedure (drv) ;
declare dry byte;
declare
i byte,
docbSptr pointer,
dacb based docbSptr structure doc::bStype;
if operation$in$progress (drv)
then do:
,
docb$ptr:ooperation$docb$ptr (drv);,
do i==l to 6; docb.cHsk$result.(U=interrupt$docb.disk$result(i): end:
docb.misc=ok:
operat.ion$in$pro9ress (drv) =false:
operation$complete (drv) =true:
end;
e,nd copy$int$result;
1**** interrupt processing for 8272 fdc drivers.
Basically, two types of
interrupts are generated by the 8272: (a}when the execution phase of
an operation has been completed, an interrupt is generated to si9nal
the beginning of the result phase (the fdc busy flilC) is set
when this interrupt is received), and (b) whe-n an overlapped operation
is completed Or an unexpected interrupt is received (the ldc busy flag
is not set when this interrupt is received) ..
When internilpt type (a) is receiv~d, the result bytes from the operation
are read from the 8272 and the operation complete flag is set.
When an interrupt of type (b) is received, the- int.e-rrupt result code is
examined to determine which of the fol.lowing four· actions are indicated:
1. An overlapped 'opt'ion (recal.ibnlte or seek) has been completed. The
cesul t data is read from the 8272 and placed in the currently active
disk operation control block.
.
.
2 .. An abnormal termination of an operation has occurred. The result
data is read and placed in the currently active disk operation
control block.
_
3. The execution of an invalid command has been attempted. This
signals the successful completion of all interrupt processing.
4. The ready status ot .. drive has chang-ed. The "drive$ready" and
"drlve$ready$status" change tables are updated. If an operation
is currently in progress on the affected drive, the result data
is placed in the currently active disk operation control block ..
After an interrupt is processed, additional" sense interrupt status cOIIUIlands
must be issued and pr~cess.d until an invalid command result ill returned
from the tdc. This action guarantees that all "hidden- interrupts
are serviced.
• •.**1
207885-12
7-160
inter
AP-121
207
208
fdcint: procedure public interrupt fdc$intSlevel;
declare
i nval id byte r
dot i ve$no byte,
docb$ptr poi nter r
docb based docb$ptr structure docbStype:
209
declare
/* interrupt port definitions */
ocw2
literally "'70R",
nBeoi
literally"shl(l,S)"":
210
declare
Iff miscellaneous flags "/
result$code
result$dr iveSready
extract$result$driveSno
endSalS interrupt
1i terally "shr (interrupt$docb .disk$resul t (0) and result$ert:or$mask, 6)" ,
1i terally .. ( (interrupt.$docb.disk$result (0) and result$ready$mask) "" 0)'"
literally" (interrupt$docb.disk$result(O) and result$drive$mask)"',
1i terally "'output (ocw2) =ose01 "',
1* if the fdc is busy when an interrupt is received, then the result
phase of the previous non-overlapped operation has begun *1
if fde$busy
,
then do:
1ft process interrupt if operation 'in prOC]ress *1
if global$driveSno <> 0
then dOl
docbSptr-operationSdocb$ptr (global$dr iveSno-l) J
if errorSin inputSresultSfrom$fdc{docbSptr}
then docb.misc-ertor;
else docb.misc-ok:
operationSin$progress (globalSdrive$no-l) Dfalse;
operation$complete (global$dr i veSno-l) -true,
globalSdr ive$no:::O;
end;
end;
211
213
215
216
218
219
220
221
222
223
1* if the fdc is not busy, then either an overlapped operation has been
completed or an unexpected interrupt has occurred (e.g., drive status
change) 'III
else do;
invalid ... false:
do while not invalidr
224
225
226
I'll perform a sense interrupt status operation - if errors are detected,
in the actual fde interface, interrupt processing 1s discontinued *1
227
229
if errorSin output$byte$toStdc{sense$intSstatus) then go to ignore,
if errorS in inputSresult$from$fdc(Unterrupt$docb) then go to ignore;
231
do case resul t$code;
1* caSe
232
233
234
235
0 - oper at ion complete "I
do;
dr i ve$no=extr act$resul t$dr i veSno;
call copy$int$result (drive$no);
end;
5
6
6
6
1* case
1 - abnormal termination
*1
do;
dr i ve$no-extr actSr eBul tSdr i veSno:
call copy$int$result (drive$nol :
end;
236
237
238
239
1* case 2 - invalid command *1
invalid=true:
240
1* case 3 - drive ready change *1
do!
241
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243
244
245
dr ive$no .. extract$resul tSdr i veSno:
'call copy$int$result(drive$no),
dr ive$status$change (drive$no) .. true J
if resultSdrive$ready
then drive$ready (dr ive$no) -true:
else drive$ready (dr ive$no) =false:
end;
endr
end;
end:
247
248
249
250
251
ignore: end$of$interrupt:
end fdcint;
252
253
254
1
end drivers;
207885-13
MODULE INFORMATION:
CODE AREA SIZE
= 0615H
CONSTANT AREA SIZE"" 00008
VARIABLE AREA SIZE • 0050H
MAXIMUM STACK SIZE
564 LINES READ
o PROGRAM
= 00328
15570
OD
800
SOD
ERROR(S)
END OF PL/M-86 COMPILATION
207885-14
7-161
inter
.
"';
APPENDIX B
8272 FOC EXERCISER PROGRAM
PL/M-86 COMPILER
8272 FLOPPY DISK DRIVER EXERCISE PROGRAM
ISIS-II PL/M-86 Vl. 2 COMPILATION OF MODULE RUN72
OBJECT MODULE PLACED IN :Fl:run72.0BJ
COMPILER INVOKED BY, plm86 :Pl:run72.p86 DEBUG
$title ,'8272 floppy diSk driver exercise pr"9r ...·)
Snointvector
$optimize (2)
$large
run72: do~
declare
docb$type
/* disk.oper·ation control block */
literally
.. (dma$op byte,dma$addr word,dma$addr$e,xt byte,dma$count word,
.
disk$command (9) byte ,disk$result (7) byte,misc byte)',
declare
/* 8272 fdc commands */
fm
mfm
dma$mode
non$dma$mode
.
recallbrBte$command
speci fy$command
.
read$command
wr i te$command
format$command
seek$command
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
"'0",
"1"",
'0',
"1",
"7",
"'3",
"6",
'S',
'ODR',
'OFS',
declare
dma$verify
dma$read
dma$write
dma$noop
itterally
literally
literally
literally
'0',
"1",
"'2",
#3",
declare
1.* disk operation control blocks *1
. structure docb$~ype,
format$docb
structure docb$type,
seek$docb
structure docb$type,
recal ibrate$docb
speci fy$docb
read$docb
write$docb
declare
step$rate
head$load$time
head$unload$time
filler$byte
operation$statu8
interleave
format$gap
read$wr i te$gap
index
drive
density
multitrack
sector
cylinder
head
tracks$per$disk
sectors$per$track
bytes$per$sector$code
bytes$per$sector
struc~ure docb$type,
structure docb$tVPe,
structure docb$type;
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
word,
/* disk drive head */
/* number of bytes in a sector on the disk *t
. declare
t* read and write buffers */
byte public,
fmtblk (104)
byte public,
wrbuf(1024)
byte public,
rdbuf (1024)
declare
t* disk format initialization tables ~I
sec$trk$table(J)
byte data(26,lS,8),
.
fmt$gapStable (8)
byte data (lBS, 2AH, 3AB, 0 ,0, 36R,54R, 74R) ,
rd$wr$gap$table (8)
byte data(07R,OER,lBH,O,O,OEB,lBS,3SH) I
207885-15
7-162
AP-121
declare
1* external pointer tables and interrupt vector '. /
[dbpt[ (2)
w[bpt[ (2)
fbpt[ (2)
intpt[ (2)
intvec (80H)
word
word
word
word
word
external,
external,
external,
external,
external,
10
11
12
executeSdocb: procedure (doc~$ptr ,status$ptr) external:
declare docbSp.tr pointer, status$ptr pointer r
13
14
inltialize$drivers: procedure external;
end initialize$drivet'sr
end executeSdocb:
$eject
1**** specify step rate ("art")
r
head load time ("hlt"), head unload time ("hut"),
and dma or non-dma operation ("nd n ) .
15
16
t7
18
19
20
21
specify$docb.dma$op c dma$noop1
specify$docb. disk$command (0) -specify$command,
specify$docb.disk$command(l):;oshl«not srt)+1,4) or shr(hut,4):
specify$docb.disk$command (2) = (h1t and OFEH) o[ (nd and 1),
call execute$do~b(@specify$docb,@operation$statusl.
22
end specify;
1*.*.
23
24
recalibrate disk drive
8272 automatically steps out until the ·track 0 signal is activated
by the disk drive.
* •• */
recalibrate: procedure (drv) ,
declare dry byte: ..
recal ibr ate$docb. dma$op=rdma$noop:
recal ibrate$docb.disk$command I 0) =recalibrate$command;
reeal ibr ate$docb. d iSk$command (l) =drv;
call. execute$docb (@recalibrate$docb,@operation$status)
25
26
27
28
1
end recalibrate;
29
1·***
seek drive "drY", ~ead (side) "hd tt to cylinder ·cyl".
seek: procedure(drv,cyl,hd),
declare (drv,cyl,hd) b~te;
30
31
32
33
34
35
36
····1
seek$docb.dma$opadma$noop;
seek$docb .diskScommand (0) =seek$command;
seek$docb .disk$command (1) =drv 9r shl (hd, 2) J
seek$docb .ai sk$command (2) -cy+ J
call execute$docb (@seek$docb,@operation$status) ;
end seek;
37
1****
format a complete side ("·head") of a single floppy disk in drive "dry".
(single or doubl~) . ~s' specified by flag "dens".
*.·.1
The density.
format: procedure (drY ,dens, intlve) ;
format disk *1
declare (drv,dens,intlve) byter
declare physical$sector byte:
38
1*
39
40
41
42
call recalibrate (drv) :
do cy1inder=0 to tracks$per$disk-l;
1* set sector numbers in format block to zero before computing interleave *1
43
do physical$l;Iec:;tor=l to sectors$per$trackr fmtblk «physical$sector-l) *4+2)
physical sector' 1 equals 109'ical sector 1 *1
physical$sector.cl;
1*
46
47
48
****1
specify: procedure(srt,hlt,hut,nd):
declare (srt,hlt.,hut,nd) byte;
3
4
-0,
end;
/* assign interleaved sectors *1
do sector-l to sectors$per$track:
index= (physical$sector-ll *4 J
207885-16
AP-121
/* change sector and index if sector has already been assigned */
do while fmtblk (index+2) <> 0, indexII:inClex+4; physical$sector.physical$sectorf1l end;
49
/* set cylinder, head, sector, and size cod~ for current sector into table */
fmtblk(index)=cylinder;
fmtblk (indeX+l) =h.a~,
fmtblk (index+2) ""sector;
53
54
55
56
.
fmtblk (index+3) .byt~s$per$sector$code,
/* update physical sector nWllber by' interleave */
phys ical$sector=phys ic.al$ sector+ i ntl ve;
if physicalSsectoi:' > sectors$p,r$track.
57
58
then phys ical$sector=phys tealS sector-sector as pe r$ tr ae k,
60
end,
61
/* seek to next cylinder "!.I
call seek (drv ,cylinder ,head) ;
/* set up format· control block *1
format$docb'. dma$op",:,dmaSwr i te 1
format$docb.dma$addr=fbptr (0)+sh1 (fbptr (1) ,4) ,
format$doc:b .dma$addr$ext-O;
, format$doc:b~ dma$count .. sectot' sSper$ trBck*4-l ~
format$docb.diskScommand (0) -format$command or shl (dens, 6) :
format$docb.disk$command (1) =drv' or shl (head, 2) :
format$docb.d iSk$command (2 J -bytes$per$sector$code:
format$do~b .di sk$command (:3) =sectors$per$ track:
format~docb.d i sk$command ( .. J =format$gapr
format$docb.disk$command (5) =filler$byte,·
.'
call execute$docb (@format$docb,@operation$status) ,
end:
'
'
62
63
64
65
66
67
68
69
70
71
72
73
end format:
7.4
/****
~
write, procedure (drv,cyl,hd,sec,dens) r
decl~re (~rv,cyl,hd,sec,dens) byte:
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
write sector ·sec· on drive "drv" at head ·hd" and cylinder ·eyl"~ "The
disk recording density is specified by the "dens" flag. Data is 'expected to be
in the glob~l write buffer ("wrbuf").
****1
2
2
2
2
2
2
2
2
2
2
2
2
2
91
92
93
wr i te$docb. dma$op~dma$wr iter
write$docb.dma$addr-wrbptr (0) +shl (wrbptr (1) ,4) ,
wr i te$docb. dma$addr$ext-O;
wr i te$docb. dma$count~bytes$ per $ sector-I;
write$docb.disk$collJftand (O)=write$command or shl (dens,6) or shl (multitrack, 7) I
write$docb.disk$command(l)=drvor shl(hd,2),
wr ite$docb.disk$command (2) ~cyl,
wr i teSdocb.disk$conimand (3) =hd,
wr i te$docb.disk$comand (4) =Bec;
wr i te$docb. d i sk$command (5) IIIbytes$per$sector$code,
wr ite$docb.disk$command (6) =sectors$perStrack;
WI i te$docb.dislc$c:ommand (7) =read$wr i te$9ap~
if bytes$per$sector$code -= 0
then wr ite$doeb.disk$command (8) =bytes$per$sector:
else wri te$docb.disk$command (8) =OFPR:
cali executeSdocb ('WI Ite$docb;@operation$status) :
end
wr~te1
/ ••• " read sector ·sec· on drive "drv· at head "hd" and cylinder "cy1". The
,disk recording density is defined by the "dens· flag. Data is read into
the global r!!ad buffer ("rdbuf").
** •• /
read: procedure (drv,cyl,hd,sec,dens) ;
declare ~drv,cylrhd,sec,dens) byte:
94
95
96
97
98
99
100
101
102
103
104
105
106
107
2
2
2
2
2
2
2
2
2
2
2
2
read$docb. dma$op=dma$ read;
read$docb.dma$addr=rdbptr (OHsh1 (rdbptr (1) ,4),
read$docb.dma$addr$ext .. O;
,
read$docb. dma$count~bytes$per$sector-l r
read$docb.dlsk$command (0) -read$command or shl (dens ,6) or shl (mul ti track, 7) :
read$docb.disk$commarid (1) ..drv or shl (hd, 2):
read$docb.disk$command (2) =cyl:
read$docb.disk$command (3) -hd;
read$docb.disk$command (4) "sec,
read$docb.d i Bk$command (5) -bytes$per$ sector$code J
read$doc:b.d i sk$conunand (6) =sector aSperS tr ack J
'
read$do~b.~isk$command (7) "read$wri te$gap;
.
207885-17
7-164
AP-121
108
if bytes$per$sector$code
=
0
then read$docb.disk$command (8) =bytes$per$sector
else read$docb.disk$command (8} =OFFH;
110
111
~
call execute$docb(@read$docb,@operation$status);
112
end read;
$eject
/**** initialize system by setting up 8237 dma controller and 8259A interrupt
controller.
*",,,,*/
113
114
initialize$system: procedure;
declare
/* I/O ports */
dmaSd i sk$addr Spor t
literally "DOH'" ,
dma$clearSff$port
dma$master $clear$por t
dma$mask$por t
dma$cl$addr$port
dma$cl$wordScountSport
dma$c2$addr$port
dmaSc 2$word$count$port
dma$c3SaddrSport
dmaSc 3$word$coun t$port
iew1
icw2
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
literally
1* current address port */
/*
/*
/*
/*
/*
/*
word count port */
command por t * /
mode port *1
mask set/reset port .. /
clear first/last flip-flop port */
dma master clear port */
1* parallel mask set port*/
dmaSd i sk$word$count$por t literally '01K' •
literally "'08H'" ,
dma$command$por t
dma$mode$por t
literally "'OBH'" ,
dma$mask.$sr$port
literally "'OAH'" ,
io...,4
ocwl
ocw2
ocw3
"'OeH'" ,
""OOH'" ,
'"OFH'" ,
'"02H'" ,
'03H' •
""04H" ,
'"05H'" ,
'06H' •
'01H' •
'10H' •
'71H' •
"'71H'" ,
'71H' •
'10H' •
'10H' ,
declare
/* mise masks and literals */
dma$extended$wr ite
Ii terally "shl (l, 5) "" ,
dma$single$transfer
literally "'shl (1,6) '",
dma$disk$mode
literally" 40H'" I
dma$cl$mode
literally "41H',
dma$c2$mode
literally "42H",
dma$c3$mode
literally '"43H'",
mode$8088
literally "'1'",
interrupt$base
literally "'20H'",
single$controller
l i terally '"shl (1,1) '" ,
level$sensitive
literally '"shl(l,3)"',
control$word$4$required literally "'1"',
base$icwl
literally ""lOH'",
mask$a11
literally "'OFFH'",
disk$interrupt$mask
literally "'1"';
115
1* extended wr i te flaq * /
/* single transfer flag */
/* master reset *1
/* set dma command mode */
116
111
output (dma$master$clear$port) =0:
output (dma$mode$port) =dma$extended$write;
118
/* set all dma registers to valid values *1
output (dma$mask$port) =mask$all:
/* mask all channels */
119
120
121
122
123
124
125
126
121
2
2
2
2
2
2
2
2
1* set all addresses to zero .. /
output (dma$clear$ff$port) =0;
output (dma$disk$addr$port) =0,
output (dma$disk$addr$port) =0;
output (dma$cl$addr$port},.O;
output (dma$cl$addr$port) =0:
output (dma$c2$addr$port) =0,
output (dma$c2$addr$port) =0;
output (dma$c3$addr$port) =0:
output (dma$c3$addr$port) =0,
128
129
130
131
132
133
134
135
136
2
2
2
2
2
2
2
2
2
1* set all word counts to valid values */
output (dma$clear$ff$port)-O:
output (dma$disk$word$cQunt$port) =1;
output (dma$disk$word$count$port) =1;
output (dma$cl$word$count$port):&l
output (dma$cl$word$cQunt$port) =1
output (dma$c2$word$count$port)-1
output (dma$c2$word$count$port) =1
output (dma$c3$word$count$port) =1
output (dma$c3Sword$count$port) =1
2
/* reset first/last flip-flop */
/* reset first/last flip-flop *1
207885-18
7-165
AP-121
137
138
139
140
141
142
143
144
1* initialize all dma channel modes */
output (dma$mode$port) -dma$disk$mode;
output (dma$mode$port) =dma$cl$mode;
output (dma$mode$port) =dma$c2Smode:
output (dma$mode$port) -dma$c3$mode;
1* initialize 8259A interrupt con.troller "I
output(icwl)=singleScontroller or level$sensitive or control$word4$required Qr base$icwl;
output (icw2) =interrupt$base;
output (iew4) =mode$8088;.
1* set 8088 interrupt mode "I
output (o~wl) =not disk$interrupt$mask:
1* mask all interrupts except disk *1
I" initialize interrupt vector for fdo It/
145
146
147
intvec (40H) =intptr (0) ,
intvec (41H) =intptr (1),
end inltlalize$system;
$eject
Ift*.*
148
main program:
first format disk- (all tracks on sidl! (head) O.
read each sector on every track of the disk forever.
****1
Then
declare drive$ready(4) byte external:
1* disable until interrupt vector setup and initialization complete *1
149
150
151
152
153
154
155
156
157
158
159
disable:
1* set initial floppy disk parameters *1
density=mfm;
head=O,
multitrack=O;
. filler$byte=55H,
tracks$per$disk=77 ;
bytes$per$sector=1024 ;
inter leave=6;
step$rate=ll;
head$load$time=40,
head$unload$time=240;
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
double-density *1
single sided *1
no multitrack operation *1
for. format *1
normal floppy disk drive *1
1024 bytes in each sector *1
set track interleave factor *1
10ms for. SAeOO plus I for uncertainty *1
40ms head load for SAeOO *1
keep head loaded as long as possible *1
1* derive dependent parameters from those above *1
160
161
162
167
168
169
170
171
bytes$per$sector$code=shr (bytes$per$sector, 7) ;
do index=O to 3;
if (bytes$per$sector$code and 1) '<> 0
then do; bytes$per$sector$code=index; go to donebc; end;
else bytes$per$sector$code-shr (bytes$per$sector$code, 1) ;
end;
donebc:
sectors$per$ track-sec$ tr k$ table (bytes$per$sector$code-densi tV) ;
format$gap=fmt$gap$table.(shl (dens i ty, 2) +bytes$per$sector$code) ;
read$wr i te$gap=rd$wr$gap$table (shl (densi ty, 2) +bytes$per$sector$code) ;
1* initialize system and drivers *1
172
173
call initialize$system; .
call initialize$drivers:
1* reenable interrupts and give 8272 a chance .to· report on drive' status
before proceeding *1
174
175
enable;
call time.CIO);
176
1* specify disk drive parameters *1
call specify (step$rate,head$load$time ,head$unload$time ,dma$mode) :
177
dr ive=O:
1* run single disk drive '0 *1
1* wait until drive ready *1
178
179
181
do while 11
if drive$ready(drive)
then qo to start:
end;
182
start:
call format(drive,densitY~interleave);
i83
do while 1;
do cylinderllO to tracks$per$disk-l:
call seek (drive,cylinder ,head) I .
do sector~l to sectors$per$track:
184
185
186
1* set up wri te buffer *1
187
do
in~ex=O
to bytes$per$sector-l; wrbuf (index) =inde'x+sector+cylinder; end;
207885-19
7-166
AP-121
190
191
call wr ite (drive ,cylinder , head, sector ,densi ty);
call read (dr ive ,cy1 inder ,head,sector ,density.) ;
1* check read buffer against write- buffer */
192
194
195
196
197
if cmpw (@wrbuf,@rdbuf,shr (bytes$per$sector, 1)} <> OFFFFH
then halt:
4
3
2
end;
end;
end;
end run72:
MODULE INFORMATION:
CODE AREA SIZE
0570H
CONSTANT AREA SIZE = OOOOH
VARIABLE AREA SIZE
0907H
MAXIMUM STACK S lZE
0022H
412 LINES READ
o PROGRAM ERROR(S)
13920
00
23110
340
END OF PL/M-86 COMPILATION
207885-20
7-167
intJ
AP-121
APPENDIX C
8272 DRIVER FLOWCHARTS
NEXT
RESET
-DRIYE$READY
-DRIYESSTATUSSCHANGE
-OPERATIONSINSPROGRESS
-OPERATIONSCOMPLETE
RESET
GLOBALSDRIYESNO
207885-21
207885-22"
RETURN
207885-23
7·168
inter
AP-121
207885-24
C
~ETURN
)
, ____~E~R~R~O~R~____~
RETURN
COMPLETE
)
RETURN
207885-25
7-169
intJ
AP·121
STARTDMA
··CHANNEL
207885-26
YES
207885-27
7-170
inter
AP-121
YES
(
RETURN
ERROR
)
'---------'
(
RETURN
)
'-----ERROR
RETURN
207885-28
RESET OPERATlONSINSPROGRESS
AND GLOBALSDRIVE$NO
(
RETURN
)
"'-----
7-171
207885-29
infef
AP-121
RETURN
INVALID STATUS
~=:-------C
RETURN
)
• , ____~BU~S~Y~S~T~A~TU~S~_'
C
ReTURN
)
~~~----~~_____
BU_S_Y_S_T_A_TU_S__~
ENABLE INTERRUPTS
•
C~
RETURN
)
___B~U~SY~ST~A~T~U~S__~
YES
NO
RETURN
COMMAND ERROR STATUS
207885-30
7-172
inter
AP·121
NO
YES
RETURN
NO
RESULT ERROR STATUS
NO
C
RETURN
)
'-------'
207885-31
7-173
intJ
AP-121
COpy RESULT
PHASE DATA FROM
THE INTERRUPT
DOCB TO CALLING
DOCB
RESET OPERATION$IN$PROGRESS FLAG
SET OPERATION$COMPLETE FLAG
C
",,-_......--RETURN
)
207885-32
7-174
inter
AP-121
C
FDCINT
)
'----,-~
ASYNCHRONOUS
INTERRUPT
NO
CALL CQPYSINTSRESUL T
TO PUT OPERATION
RESULT INFORMATION
INTO THE Doca
RESET OPERATIONSINSPROGRESS
SET OPERATlON5COMPLETE
RESET GLOBAL$ORIVE$NO
CALL COPYStNTSRESULT
TO PUT OPERATION
RESULT INFORMATION
INTO THE Daca
DRIVE
READY
CHANGE
207885-33
7-175
Hard Disk Controllers
8
i~
82064
CHMOS WINCHESTER DISK CONTROLLER
WITH ON-CHIP ERROR DETECTION AND CORRECTION
Controls ST506/ST412 Interface
• Winchester
Disk Drives
5 Mbitlsec Data Transfer Rate
• Compatible with All Intel and Most
• Other Microprocessors
Speed Operation
• -High"Zero
Wait State" Operation with
•
Low Power CHMOS III
• On-Chip
Unit Automatically
• CorrectsECC
Errors
5 or 11-Bit Correction-Span Software
• Selectable
Implied Seeks with Read/Write
• Commands
Sector Transfer Capability
• Multiple
128, 256, 512 and 1024 Byte Sector
• Lengths
in 40-Lead Ceramic Dual In• Available
Line, 40-Lead Plastic Dual In-Line, and
8 MHz 80286 and 10 MHz 80186/188
- "One Wait State" Operation with
10 MHz 80286
Eight High-Level Commands: Restore,
Seek, Read Sector, Write Sector, Scan
ID, Write Format,Compute Correction,
Set Parameter
44-Lead Plastic Chip Carrier Packages
(See Packaging Spec., Order # 231369)
The 82064 Winchester Disk Controller (WDC) with on-chip error detection and correction circuitry interfaces
microprocessor systems to 5%" Winchester disk drives. The 82064 is a CHMOS version of the Western
Digital WD201 o. It is an upgrade to the Western Digital WD1 01 OA-05 Winchester Disk Controller, and includes
on-chip ECC, support for drives with up to 2k tracks, and has an additional control signal which eliminates an
external decoder.
The 82064 is fabricated on Intel's advanced CHMOS III technology and is available in 40-lead CERDIP, plastic
DIP, and 44-lead plastic leaded chip carrier packages .
....,
WAOAllo
WRClOCIl
AD DAY"
ROGATE
231242-2
8UFFEA
CO.HJlOl
6 5 .. 3
Vcc_
'11$5.-
:z
I .... 43 42 4140
o
BRDY
...,
DRUN
"
231242-1
. Figure 1. 82064 Block Diagram
181920212223 2.. 25 26 2128
. .
HHi!l'J'~13IH~
231242-29
Figure 2. 82064 Pinouts
8-1
September 1987
Order Number: 231242·005
inter
82064
Table 1. Pin Description
Pin.No.
Symbol
Type
Name and Function
DIP
·PLCC
BCS
1
1
a
BUFFER CHIP SELECT: Output used to enable reading or
writing of the external sector buffer by the 82064. When low,
the host should not be able to drive the 82064 data bus, RD,
orWR lines.
BCR
2
2
a
BUFFER COUNTER RESET: Output that is asserted by the
82064 prior to readlwrite operation. This pin is asserted
whenever BCS changes state. Used to reset the address
counter of the buffer memory.
INTRQ
3
3
0
INTERRUPT REQUEST: Interrupt generated by the 82064
upon command termination. It is reset when the STATUS
register is read, or a new command is written to the
COMMAND register. Optionally signifies when a data transfer
is required on Read Sector commands.
SDHLE
4
4
0
SDHLE is asserted when the SOH register is written by the
host.
RESET
5
7
I
RESET: Initializes the controller and clears all status flags.
Does not clear the Task Register File.
RD
6
8
1/0
READ: Tri-state, bi-directional signal. As an input, RD controls
the transfer of information from the 82064 registers to the
host. RD is an output when the 82064 is reading data from the
sector buffer (BCS low).
WR
7
9
1/0
WRITE: Tri-state, bi-directional signal. As an input, WR
controls the transfer of command or task information into the
82064 registers. WR is an output when the 82064 is writing
data to the sector buffer (BCS low).
CS
8
10
I
CHIP SELECT: Enables RD and WR as inputs for access to
the Task Registers. It has no effect once a disk command
starts.
AO-2
9-11
11-13
I
ADDRESS: Used to select a register from the task register
file.
DBo_7
12-19
14-16
18-22
110
Vss
20
23
WR DATA
21
24
0
WRITE DATA:Output that shifts out MFM data at a rate
determined by Write Clock. Requires an external 0 flip-flop
clocked at 10 MHz. The output has an active pullup and
pulldown that can sink 4.8 mA.
LATE
22
25
0
LATE: Output used to derive a delay value for write
precompensation. Valid when WR GATE is high. Active on all
cylinders.
EARLY
23
26
0
EARLY: Output used to derive a delay value for write
precompensation. Valid when WR GATE is high. Active on all
cylinders.
DATA BUS: Tri-state, bi-directionaI8-bit Data Bus with control
determined by BCS. When BCS is high the microprocessor
has full control of the data bus for reading and writing the Task
Register File. When BCS is low the 82064 controls the data
bus to transfer to or from the buffer.
Ground
8-2
inter
82064
Table 1. Pin Description (Continued)
Pin No.
Symbol
Type
Name and Function
27
0
WRITE GATE: High when write data is valid. WR GATE goes
low if the WR FAULT input is active. This output is used by the
drive to enable head write current.
25
29
I
WRITE CLOCK: Clock input used to derive the write data rate.
Frequency = 5 MHz for the ST506 interface.
DIR
26
30
0
DIRECTION: High level on this output tells the drive to move
the head inward (increasing cylinder number). The state of this
signal is determined by the 82064's internal comparison of
actual cylinder location vs. desir?d cylinder.
STEP
27
31
0
STEP: This signal is used to move the drive head to another
cylinder at a programmable frequency. Pulse width = 1.6 p.s
for a step rate of 3.2 p.s/step, and 8.4 p's for all other step
rates.
DRDY
28
32
I
DRIVE READY: If DRDY from the drive goes low, the
command will be terminated.
INDEX
29
33
I
INDEX: Signal from the drive indicating the beginning of a
track. It is used by the 82064 during formatting, and for
counting retries. Index is edge triggered. Only the rising edge
is valid.
WRFAULT
30
34
I
WRITE FAULT: An error input to the 82064 which indicates a
fault condition at the drive. If WR FAULT from the drive goes
high, the command will be terminated.
TRACK 000
31
35
I
TRACK ZERO: Signal from the drive which indicates that the
head is at the outermost cylinder. Used to verify proper
completion of a RESTORE command.
SC
;32
36
I
SEEK COMPLETE: Signal from the drive indicating to the
82064 that the drive head has settled and that reads or writes
can be made. SC is edge triggered. Only the rising edge is
valid.
RWe
33
37
0
REDUCED WRITE CURRENT: Signal goes high for all
cylinder numbers above the value programmed in the Write
Precomp Cylinder register. It is used by the precompensation
logic and by the drive to reduce the effects of bit shifting.
DRUN
34
38
I
DATA RUN: This signal informs the 82064 when a field of all
ones or all zeroes has been detected in the read data stream
by an external one-shot. This indicates the beginning of an ID
field. RD GATE is brought high when DRUN is sampled high
for 16 clock periods.
BRDY
35
39
I
BUFFER READY: Input used to signal the controller that the
buffer is ready for reading (full), or writing (empty), by the host
p.P. Only the rising edge indicates the condition.
DIP
PLCC
WRGATE
24
WRCLOCK
8·3
inter
82064
Table 1 Pin Description (Continued)
Pin No.
Symbol
Name and Function
Type
DIP
PLCC
BDRQ
36
40
0
BUFFER DATA REQUEST: Activated during Read or Write
commands when a data transfer between the host and the
82064's sector buffer is required. Typically used as a DMA
request line.
RDDATA
37
41
I
READ DATA: Single ended input that accepts MFM data from
the drive.
RDGATE
38
42
0
READ GATE: Output that is asserted when a search for an
address mark is initiated. It remains asserted until the end of
the 10 or data field.
RDCLOCK
39
43
I
READ CLOCK: Clock input derived from the external data
recovery circuits.
Vee
40
44
I
D.C. POWER:
NC
-
5,6
17,28
+ 5V.
No Connects
,
Improvements to the processor interface to provide
high-speed "zero wait state" operation with 10 MHz
80186/188 and 8 MHz 80286. High-speed "one wait
state" operation with 10 MHz 80286.
FUNCTIONAL DESCRIPTION
The Intel 82064 CHMOS Winchester Disk Controller
(WDC) interfaces microprocessor systems to Winchester disk drives that use the Seagate Technology
ST50S/ST412 interface. The device translates parallel data from the microprocessor to a 5 Mbitlsec,
MFM-encoded serial bit stream. It provides all of the
drive control logic and control signals which simplify
the design of external data separation and write precompensation circuitry. The 82064 is designed to interface to the host processor through an external
sector buffer.
The 82064 is completely socket and software compatible with the WD201 0 Winchester Disk Controller.
As with the WD2010, the 82064 is also socket and
software compatible with existing WD1010A-05 designs that do not include external ECC.
INTERNAL ARCHITECTURE
The internal architecture of the 82064 is shown in
more detail in Figure 3. It is made up of seven major
blocks as described below.
On-chip error detection algorithms include the CRCI
CCITT and a 32~bit computer generated ECC polynomial. If the ECC code is selected, the 82064 provides three possible error handling techniques if an
error is detected during a read operation:
PLA Controller
1. Automatically correCt the data in the sector buffer,
providing the host with good information. .
The PLA interprets commands and provides all con-·
trol functions. It is synchronized with WR CLOCK.
2. Provide the host with the error location and pattern, allowing the host to correct the error.
3. Take no action other than setting the error flag.
Magnitude Comparator
The Intel 820S4 is an enhanced version of the Western Digital WD2010 Winchester Disk Contrpller. The
82064 has been completely' redesigned for Intel's
advanced CHMOS III· fabrication process, allowing
Intel to offer a high quality, low power device while at
the same time maintaining complete compatibility
with the WD2010.
An 11-bit magnitude comparator is used to calculate
the direction and number of steps needed to move
the heads from the present to the desired cylinder
position. It compares the cylinder number in the task
file to the internal "present position" cylinder number.
A separate high-speed equive.lance· comparator is
used to compare 10 field bytes when searching for a
sector 10 field.
Enhancements to the basic design include:
Conversion to a CHMOS III fabrication process for
low power consumption.
.8-4
82064
0110·7
WR DATA
WR CLOCK
iiii
\Vii
.00·2
INTRa
,
.
i
f
I
RD CLOCK
HOST
IFC
iiffiT
RD DATA
Cs
PLA
CONTROLLER
, . - - " ... S'i5"H'lE
STEP
OIRC
iCR
IIROY
BORa
miC'/
LATE
BUFFER
IFC
DROY
WR FAULT
IiCI
TRACK 000
INDEX
Vcc~
SC
GND_
RWC
WRGATE
RD GATE
L-;;';"..I""r- ORUN
231242-3
Figure 3. 82064 Detailed Block Diagram
CRC and ECC Generator and Checker
data field CRC error occurs the "ECC/CRC" bit in
the error register will be set.
The 82064 provides two options for protecting the
integrity of the data field. The data field may have
either a CRC (SOH register, bit 7 = 0), or a 32-bit
ECC (SOH register, bit 7 = 1) appended to it. The 10
field is always protected by a CRC.
The ECC mode is only applicable to the data field. It
provides the user with the ability to detect and correct errors in the data field automatically. The commands and registers which must be considered
when ECC is used are:
The CRC mode provides a means of verifying the
accuracy of the data read from the disk, but does
not attempt to correct it. The CRC generator computes and checks cyclic redundancy check characters that are written and read from the disk after 10
and data fields. The polynomial used is:
1. SOH Register; bit 7 (CRC/ECC)
2. READ SECTOR Command, bit 0 (T)
3. READ SECTOR and WRITE SECTOR Commands,bit1 (L)
4. COMPUTE CORRECTION Command
5. SET PARAMETER Command
6. STATUS Register, bit 2 - error correction successful
The CRC register is preset to all one's before computation starts.
7. STATUS Register, bit 0 - error occurred
8. ERROR Register, bit 6 - uncorrectableerror
If the CRC character generated while reading the
data does not equal the one previously written an
error exists. If an 10 field CRC error occurs the "10
not found" bit in the error register will be set. If a
To enable the ECC mode, bit 7 of the SOH register
must be set to one.
8-5
intJ
82064
Bit O(T) of the READ Command controls whether or
not error correction is attempted~ When T = 0 and
an error is detected, the 82064 tries up to 10 times
to correct the error. If the error is successfully corrected, bit 2 of the STATUS Register is set. The host
can interrogate the status register and detect that an
error occurred and was corrected. If the error was
not correctable, bit 6 of the ERROR Register is set.
If the correction span was set to 5 bits, the host may
now execute the SET PARAMETER Command to
change the correction span to 11 bits, and attempt
the read again. If the error persists, the host can
read the data, but it will contain errors.
MFM ENCODER/DECODER
Encodes and decodes MFM data to be written/read
from the drive. The MFM encoder operates from
WR CLOCK, a clock having a frequency equal to the
bit rate. The MFM decoder operates from
RD CLOCK, a bit rate clock generated by the external data separator. RD CLOCK and WR CLOCK
need not be synchronous.
The MFM encoder also generates the write precompensation control signals. Depending on the bit pattern of the data, EARLY or LATE may be asserted.
External circuitry uses these signals to compensate
for drift caused by the influence one bit h~
another. More information on the use of the EARLY
and LATE control signals can be found in the section which describes the drive interface.
When T = 1 an'd an error is detected, no attempt is
made to correct it. Bit 0 of the STATUS Register and
bit 6 of the ERROR Register are set. The user now
has two choices:
1. Ignore'the error and make no attempt to correct it..
2. Use the COMPUTE CORRECTION Command to
determine the location and pattern of the error,
and correct it within the user's program.
Address Mark (AM) Detection
An address mark is comprised of two unique bytes
preceeding both the 10 field and the data field. The
first byte is used for resynchronization. The second
byte indicates whether it is an 10 field or a data field.
When the COMPUTE CORRECTION Ccimmand is
implemented, it must be done before executing any
command which can alter the contents of the ECC
Register. The READ. SECTOR, WRITE SECTOR,
SCAN 10.. and FORMAT Commands will alter this
register and correction will be impossible. The COMPUTE CORRECTION Command may determine that
the error is uncorrectable, at which point the error
bits in the STATUS and ERROR Registers are set.
The first byte, A 1H, normally has a clock pattern of
OEH; however, one clock -pulse has been suppressed, making it OAH. With this pattern, the AM
detector knows it is looking at an address mark. It
now examines the next byte to determine if it is an 10
or data field. If this byte is 111101XX or 111111XX it
is an 10 field. Bits 3, 1, and 0 are the high' order
cylinder number bits. If the second byte is F8H, it is a
data field.
Although ECC generation starts with the first bit of
the F8H byte in the data 10 field, the actual ECC
bytes written will be the same as if the A1H byte was
included. The ECC polynomial used is:
Host/Buffer Interface Control
X32+ X28+ X26+ X19+ X17 + Xl0+ X6+ X2+ 1
The primary interface between .the host processor
and the 82064 is an 8-bit bi-directional bus. This bus
is used to transmit and receive data for both the
82064 and the sector buffer. The sector buffer consists of a static RAM and counter. Since the 82064
makes the b.us active when accessing the sector
buffer, a transceiver must be used to isolate the host
during this time. Figure 4 illustrates a typical interface with a sector buffer.' Wheneverthe 82064 is not
using the sector buffer, the BUFFER CHIP SELECT
(BCS) is high (disabled). This allows the host access
to the 82064's Task Register File and to the sector
buffer. A decoder is used to generate BCS when
is '000', an unused address in..,!!!.e 82064. A
binary counter is enabled whenever RD or WR go
active. The location within the sector buffer which is
addressed by the counter will be accessed. The
counter will be incremented by the trailing edge of
the RD or WR. This allows the host to access se-
For automatic error correction,' the external sector
buffer must be implemented with a static RAM and
.
counter, not with a FIFO~
The SET PARAMETER Command is used to select
a 5-bit or 11-bit correction span.
When the L Bit (bit 1) of the READ, SECTORand
WRITE SECTOR commands is set to one, they are
referred to as READ LONG and WRITE LONG commands. For these commands, no CRe or·ECC characters are generated or checked qy the 82064. In
effect, the data field is extended by4 bytes which
are passed to/from the sector buffer.
Ao-2
With proper use of the WRITE SECTOR, READ
LONG, WRITE LONG, and READ SECTOR Commands,. a: diagnostic. routine may be developed to
test the accuracy of the error correction process.
8-6
82064
'"
'"
-
RD
WR
DATA
-
RD
~
-
-WR
l.--C
-- ~
'/.
DATA BUS (8)
'/,
'/.
tl~~
HOST
CPU
SYSTEt.4
t.iR
TC
r--
,
3/
ADDRESS
r
-
D
E
C
0
~
DB O_ 7
'/
BCR
QO
f-f-f-f--
A
o
DATA
Al
••
•
••• r-- •••
•
•
r--
QX
f--
•
AX
t
-
iiE f-
82064
WE
r--
-CS
Q
I-
BCS
-CS
I-
,
3/
~
D
DATA
INTERRUPT REQUEST
,
BDRQ
CP
Dt.4A
CONTROLLER
T
1
AO_2
BRDY
Q
I
INTRQ
231242-4
Figure 4. Host Interface Block Diagram
necting the host through the transceivers, and the
RD and WR lines become outputs from the 82064 to
allow access to the sector buffer. When the 82064 is
done using the buffer, it deasserts BCS which again
allows the host to access the local bus. The READ
SECTOR command operates in a similar manner,
except the buffer is loaded by the 82064 instead of
the host.
quential bytes within the sector buffer, The decoder
also generates a CS for the 82064 whenever AO-2
does not equal '000', allowing access to the 82064's
internal Task Register File while keeping the sector
buffer tri-stated,
During a WRITE SECTOR Command, the host processor sets up data in the Task Register File and then
issues the command. The 82064 asserts BUFFER
COUNTER RESET (BCR) to reset the counter. It
then generates a status to inform the host that it can
load the sector buffer with data to be written. When
the counter reaches its maximum count, the BUFFER READY (BRDY) signal is asserted by the carry
out of the counter, informing the 82064 that the sector buffer is full. (BRDY is a rising edge triggered
signal which will be ignored if asserted before the
82064 asserts BCR.) BCS is then asserted, discon-
Another control signal, BUFFER DATA REQUEST
(BDRQ), can be used with a DMA controller to indicate that the 82064 is ready to send or receive data.
When data transfer is via a programmed 1/0 environment, iUs the responsibility of the host to interrogate the DRQ status bit to determine if the 82064 is
ready (bit 3 of tlie status register). For further explanation, refer to the individual command descriptions
and the A.C. Characteristics.
8-7
inter
82064
When INTRa is asserted, the host is signaled that
execution of a command has terminated (either a
normal termination or an aborted command). For the
READ SECTOR command, interrupts may be programmed to be asserted either at the termination of
the command, or when BDRa is asserted. INTRa
will remain active until the host reads the STATUS
register to determine the cause of the termination, or
writes Ii new command into the COMMAND register.
Drive Interface
The drive side of the 82064 WDC requires three sections of external logic. These are the control line
buffer/receivers, data separator, and write precompensation. Figure 5 illustrates a drive interface.
The buffer/receivers condition the control lines to be
driven down the cable to the drive. The control lines
are typically single-ended, resistor terminated, TIL
levels. The data lines to and from the drive also require buffering. This is typically done with differential
RS-422 drivers. The interface specification for the
drive will be found in the drive manufacturer's OEM
The 82064 asserts SDHLE whenever the SDH register is being written. This signal can be. used to latch
the drive and head select information in an external
register for decoding. Figure 5 illustrates one method.
j,
.)
08 0 _ 4
"
0
0
0
Or--01-~~
Dl
A
T
C
H
0
E
C
0
0
E
HSElO
HSEl1
HSEl2
DSEll
-DSEl2
-
DSEl3
-DSEl4
SDHlE
RD GATE
ORUN
RD DATA
RD CLOCK
DATA
SEPARATOR
-
82064
WR DATA
HOST
t::
~
" 08 0 _ 7 "
EARlY
LATE
RWC
STEP
DIR
ORDY
WR FAULT
TRACK 000
INDEX
SC
WR GATE
WRITE
PRECOMPENSATION
AND
SYNCHRONIZA nON
DISK
DRIVE
INTERFACE/
8urrER
231242-5
Figure 5. Drive Interface Block Diagram
8-8
inter
82064
The write precompensation circuitry is designed to
reduce the drift in the data caused by interaction
between bits. It is divided into two parts, REDUCED
WRITE CURRENT (RWC) and EARLY/LATE writing
of bits. A block diagram of a typical write precompensation circuit is shown in Figure 8.
manual. The 82064 supplies TTL compatible signals,
and will interface to most buffer/driver devices.
The data recovery circuits consist of a phase locked
loop, data separator, and associated components.
The 82064 interacts with the data separator through
the DATA RUN (DRUN) and RD GATE signals. A
block diagram of a typical data separator circuit is
shown in Figure 6. Read data from the drive is presented to the RD DATA input of the 82064, the reference multiplexor, and a retriggerable one shot.
The RD GATE output will be deasserted when the
82064 is not inspecting data. The PLL should remain
locked to the reference clock.
The cylinder in which the RWC line becomes active
is controlled by the REDUCE WRITE CURRENT register in the Task Register File. When a cylinder is
written which has a cylinder number greater than or
equal to the contents of this register, the write current will be reduced. This will decrease the interaction between the bits.
Drift may also be caused by the bit pattern. With
certain combinations of ones and zeroes some of
the bits can drift far enough apart to be difficult to
read without error. This phenomenon can be minimized by using EARLY and LATE as described below. The 82064 examines three bits, the last one
written, the one being written, and the next one to be .
written. From this, it determines whether to assert
EARLY or LATE. Since the bit leaving the 82064 has
already been written, it is too late to make it early.
Therefore, the external delay circuit must be as follows:
EARLY asserted and LATE deasserted = no
delay
EARLY deasserted and LATE deasserted =
one unit delay (typically 12-15 ns)
EARLY deasserted and LATE asserted = two
units delay (typically 24-30 ns)
When any READ or WRITE command is initiated
and a search for an address mark begins, the DRUN
input is examined. The DR UN one-shot is set for
slightly longer than one bit time, allowing it to retrigger constantly on a field of all ones or all zeroes. An
internal counter times out to see that DRUN is asserted for two byte times. RD GATE is asserted by
the 82064, switching the data separator to lock on to
the incoming data stream. If DRUN is de asserted
prior to an additional seven byte times, RD GATE is
de asserted and the process is repeated. RD GATE
will remain asserted until a non-zero, non-address
mark byte is detected. The 82064 will then deassert
RD GATE for two byte times to allow the PLL to lock
back on the reference clock, and start the DRUN
search again. If an address mark is detected, RD
GATE remains asserted and the command will continue searching for the proper 10 field. This sequence is shown in the flow chart in Figure 7.
EARLY and LATE are always active, and should be
gated .externally by the RWC signal. Figure 8 illustrates one method of using these signals.
250 NSEC
RETRIGGERABLE
ONE-SHOT
IoAFIoA
DISK
DATA
~
J
-
L~"m.
A
IoAUX
I
DRUN
~
1I
f--
PHASE
COIoAP
AND
c
~ RD DATA
r~
I
vco
B
+2
82064
1-+
RD. CLOCK
RD GATE
I
I
+2
I
I
tOIoAHZ
OSC
WR CLOCK
231242-6
Figure 6. Data Separator Circuit
8-9
i~
82064
231242-7
Figure 7. PLL Control Sequence
8-10
inter
82064
DELAY LINE
WR DATAI---~
EARLY
12NS
1-----1
24NS
LATE t---'--~
WR DATA
TO DRIVE
82064
10t.lHZ
osc
RWCt-----------__-+------------------~
'-----------------------------------+
TO DRIVE
231242-9
Figure 8. Write Precompensation Circuit
TASK REGISTER FILE
Bit 6 - GRG/EGG Data Field Error (GRG/EGG)
The Task Register File is a bank of nine registers
used to hold parameter information pertaining to
each command, status information, and the command itself. These registers and their addresses are:
When in the GRG mode (SDH register, bit 7 = 0),
this bit is set when a GRG error occurs in the data
field. When retries are enabled, ten more attempts
are made to read the sector correctly. If none of
these attempts are successful bit 0 in the STATUS
register is also set. If one of the attempts is successful, the GRG/EGG error bit remains set to inform the
host that a marginal condition exists; however, bit 0
in the STATUS register is not set.
A2
A1
AO
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
READ
BUS TRI-STATED
ERROR REGISTER
SECTOR COUNT
SECTOR NUMBER
CYLINDER LOW
CYLINDER HIGH
SOH
STATUS
WRITE
BUS TAl-STATED
REDUCE WRITE CURRENT
SECTOR COUNT
SECTOR NUMBER
CYLINDER LOW
CYLINDER HIGH
SOH
COMMAND
When in the EGG mode (SDH register, bit 7 = 1),
this bit is set when the first non-zero syndrome is
detected. When retries are enabled, up to ten attempts are made to correct the error. If the error is
successfully corrected, this bit remains set; however, bit 2 of the STATUS register is also set to inform
the host that the error has been corrected. If the
error is not correctable, the GRG/EGG error bit remains set and bit 0 of the STATUS register is also
set.
NOTE:
These registers are not cleared by RESET being asserted.
ERROR REGISTER
This read only register contains specific error information after the termination of a command. The bits
are defined as follows:
I:s ICRC~ECC I ~ II~ I~ I I
:C
TKOOO
The data may be read even if uncorrectable errors
exist.
o
NOTE: If the long mode (L) bit is set in the READ or
WRITE command, no error checking is performed.
DAM
Bit 7 - Bad Block Detect (BB)
Bit 5 - Reserved
This bit is set when an ID field has been encountered that contains a bad block mark. It is used for
bad sector mapping.
Not used. Forced to zero.
8-11
intJ
82064
Bit 4 - 10 Not Found (10)
This bit is set to indicate that the correct cylinder,
head, sector, or size parameter could not be found,
or that a CRC error occurred in the 10 field. This bit
is set on the first failure and remains set even if the
error is recovered on a retry. When recovery is unsuccessful, the Error bit (bit 0) of the STATUS register is also set.
For a SCAN 10 command with retries enabled (T =
0), the Error bit in the STATUS register is set after
ten unsuccessful attempts have been made to find
the correct .10, With retries disabled (T = i), only
two attempts are made before setting the Error bit.
For a READ or WRITE command wlth retries enabled (T = 0), ten attempts are made to find the
correct 10 field. If there is still an error on the tenth
try, an auto-scan and auto-seek are performed.
Then ten more retries are made before setting the
Error bit. When Jetries are disabled (T = 1), only two
tries are made. No auto-scan or auto-seek operations are performed.
The value (OO-FFH) loaded into this cylinder is internally multiplied by four to specify the actual cylinder
where RWC is asserted. Thus a value of 01 H will
cause RWC to be asserted on cylinder 04H, 02H on
cylinder 08H, ... , 9CH on cylinder 270H, 9DH on
cylinder 274H, and so on. HWC will be asserted
when the present cylinder is greater than or equal to
four times the value of this register. For example, the
ST506 interface requires precomp on cylinder 80H
and above. Therefore, the REDUCE WRITE CURRENT register should be loaded with 20H.
A value of FFH causes RWC to remain deasserted,
regardless of the aciual cylinder number.
SECTOR COUNT REGISTER
This register is used to define the number of sectors
that need to be transferred to the buffer during a
READ MULTIPLE SECTOR or WRITE MULTIPLE
SECTOR command.
I
7
1
6
1 5. 141 31
o
2
Bit 3 - Reserved
Not used. Forced to zero.
Bit 2 - Aborted Command (AC)
Command execution is aborted and this bit is set if a
command was .issued while DRDY is deasserted or
WR FAULT is asserted. This bit will also be set ifan
undefined comrnand is written to the COMMAND
register; however, an implied seek will be executed.
Bit 1 - Track 000 Error (TKOOO)
This bit is set during the execution of a RESTORE
command if the TRACK 000 pin has not gone active
after the issuance of 2047 step pulses.
Bit 0 - Data Address Mark (DAM) Not Found
This bit is set during the execution of a READ SECTOR command if the DAM is not found following the
proper sector 10.
REDUCE WRITE CURRENT REGISTER
This register is used to define the cylinder number
where the RWC output (Pin 33) is asserted.
7
6
I
5
I
4
I
3
I
2
CYLINDER NUMBER -;- 4
1
The value contained in the register is decremented
after each sector is transferred to/from the sector
buffer. A zero represents a 256 sector transfer, a
one a one sector transfer, etc. This register is a
"don't care" when single· sector commands are
specified.
SECTOR NUMBER REGISTER
This regrster holds the sector number of the desired
sector.
17
1
6
15 1·4 1
3
1
2
I
SECTOR NUMBER
For a multiple sector command, it specifies the first
sector to be transferred. It is incremented after each
sector is transferred to/from the sector buffer. The
SECTOR NUMBER register may contain any value
from 0 to 255.
The SECTOR NUMBER register is also used to program the Gap 1 and Gap 3 lengths to be used when
formating a disk. See the WRITE FORMAT command description for further explanation.
inter
82064
the drive number recorded, but does have the bad
block mark written. The format of the SOH byte written on the disk is:
CYLINDER NUMBER LOW REGISTER
This register holds the lower byte of the desired cylinder number.
I
7
I
6
I
5
I
4
I
3
I
2
I
I
1
I
HEAD
STATUS REGISTER
It is used with the CYLINDER NUMBER HIGH register to specify the desired cylinder number over a
range of 0 to 2047.
The status register is used to inform the host of certain events performed by the 82064, as well as reporting status from the drive control lines. Reading
the STATUS register deasserts INTRO. The format
is:
CYLINDER NUMBER HIGH REGISTER
This register holds the three most significant bits of
the desired cylinder number.
Bit 7 - Busy
This bit is asserted when a command is written into
the COMMAND register and, except for the READ
command, is deasserted at the end of the command. When executing a READ command, Busy will
be deasserted when the sector buffer is full. Commands should not be loaded into the COMMAND
register when Busy is set. When the Busy bit is set,
no other bits in the STATUS or ERROR registers are
valid.
The CYLINDER NUMBER LOW/HIGH register pair
determine where the R/W heads are to be positioned. The host writes the desired cylinder number
into these registers. Internal to the 82064 is another
pair of registers that hold the present head location.
When any command other than a RESTORE is executed, the internal head location registers are compared to the CYLINDER NUMBER registers to determine how many cylinders to move the heads and in
what direction.
Bit 6 - Ready
The internal head location registers are updated to
equal the CYLINDER NUMBER registers after the
completion of the seek.
This bit reflects the status of DRDY (pin 28). When
this bit equals zero, the command is aborted and the
status of this bit is latched.
When a RESTORE command is executed, the internal head location registers are reset to zero while
DIR and STEP move the heads to track zero.
Bit 5 - Write Fault (WF)
SECTOR/DRIVE/HEAD (SDH) REGISTER
This bit reflects the status of WR FAULT (pin 30).
When this bit equals one the command is aborted,
INTRO is asserted, and the status of this bit is
latched.
The SDH register contains the desired sector size,
drive number, and head parameters. The format is
shown in Figure 9. The EXT bit (bit 7) is used to
select between the CRC or ECC mode. When bit 7
= 1 the ECC mode is selected for the data field.
When bit 7 = 0 the CRC mode is selected.
Bit 4 - Seek Complete (SC)
This bit reflects the status of SC (pin 32). When a
seek or implied seek has been initiated by a comm'and, execution of the command pauses until the
seek is complete. This bit is latched after an aborted
command error.
The SOH byte written in the 10 field of the disk by the
FORMAT command is different than the SOH register contents. The recorded SOH byte does not have
8-13
inter
82064
7
6
5
4
o
2
L DRIVE
S;IZE
,,
,
r-'
3
\
I
\
\
.
\
1....._--"'- ..
----... -------...
----..
6
5
SECTOR SIZE
4
3
DRIVE #
2
1
0
HEAD #
0
0
1
1
0
1
0
1
256
512
1024
128
0
0
1
1
0
1
0
1
OSEL1
OSEL2
OSEL3
OSEL4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HSELO
HSEL1
HSEL2
HSEL3
HSEL4
HSEL5
HSEL6
HSEL7
231242-10
NOTE:
Drive select and head select lines must be generated externally. Figure 3 represents one method of achieving this.
Figure 9. SDH Register Format
Bit 3 - Data Request (ORQ)
Bit 0 - Error
The ORQ bit reflects the status of BORQ (pin 36). It
is asserted when the sector buffer must be written
into or read from. ORQ and BORQ remain asserted
until BROY indicates that the sector buffer has been
filled or emptied, depending upon the command.
BDRQ can be used for OMA interfacing, while ORQ
is used in a programmed I/O environment.
This bit is set whenever any bits in the ERROR register are set. It is the logical 'or' of the bits in the
ERROR register and may be used by the host processor to quickly check for nonrecoverable errors.
The host must read the ERROR register to determine what type of error occurred. This bit is reset
when a new command is written into the COMMAND
register.
Bit 2 - Data Was Corrected (OWC)
When set, this bit indicates that an ECC error has
been detected during a read operation, and that the
data in the sector buffer has been corrected. This
provides the user with an indication that there may
be a marginal condition within the drive before the
errors become uncorrectable. This bit is forced to
zero when not in the ECC mode.
COMMAND REGISTER
The command to be executed is written into this.
write-only register:
I7
I
6
I
5
I
4
I
3
I
2
o
COMMAND
Bit 1 - Command In Progress (CIP)
The command sets Busy and CIP, and begins to execute as soon as it is written into this register. Therefore, all necessary information should be loaded into
the Task Register File prior to entering the command. Any attempt to write a register will be ignored
until command execution has terminated, as indicated by the CIP bit being cleared. INTRQ is deasserted when the COMMAND register is written.
When this bit is set a command is being executed
and a new command should not be loaded. Although a command is being executed, the sector
buffer is still available for access by the host. When
the 82064 is no longer Busy (bit 7 = 0) the STATUS
register can be read. If other registers are read while
CIP is set the contents of the STATUS register will
be returned.
8-14
82064
COMMAND
RESTORE
SEEK
READ SECTOR
WRITE SECTOR
SCANID
WRITE FORMAT
COMPUTE CORRECTION
SET PARAMETER
Ra-o
=
7 6 5 4 3
2
1
0 0 1 R3 R2 R1
0
0
0
0
0
0
0
0
1 1 1 R3 R2 R1
I
M
L
0 M L
0 1 0
0 1 1
1 0 0
1 0 1
0 0 0
0 0 0
0
0
1
0
0
G
0
0
0
0
0
0
0
RO
RO
T
T
T
T
=
G
=
Gap Filler Byte.
G
=
o. Gaps 1, 3 and pad bytes "4E".
1 Disable retries.
G = 1. Gaps 1, 3 and pad bytes "AA".
0
0
S
S
=
Error Correction Span
S = 0 5-bit span.
S
Stepping Rate Field
=
1 11-bit span.
For 5 MHz WR CLOCK:
RESTORE COMMAND
R3-0'= 0000 35 p.s
0001 0.5 ms
0010 1.0 ms
0011 1.5 ms
0100 2.0 ms
0101 2.5 ms
0110 3.0 ms
0111 3.5 ms
1000 4.0 ms
1001 4.5 ms
1010 5.0 ms
1011 5.5 ms
1100 6.0 ms
1101 6.5 ms
1110 3.2 p's
1111 16 p.s
The RESTORE command is used to position the
R/W heads over track zero. It is usually issued by
the host when a drive has just been turned on. The
82064 forces an auto-restore when a FORMAT
command has been issued following a drive number
change.
The actual step rate used for the RESTORE command is determined by the seek complete time. A
step pulse is issued and the 82064 waits for a rising
edge on the SC line before issuing the next pulse. If
the rising edge of SC has not occurred within ten
revolutions (INDEX pulses) the 82064 switches to
sensing the level of SC. If after 2047 step pulses the
TRACK 000 line does not go active the 82064 will
set the TRACK 000 bit in the ERROR register, assert
INTRa, and terminate execution of the command.
An interrupt will also occur if WR FAULT is asserted
on DRDY is de asserted at any time during execution.
I = Interrupt Control
I = 0 INTRa occurs with BORa/ORa indicating
the sector buffer is full. Valid only when M =
o.
The rate field specified (Ra-o) is stored in an internal
register for future use in commands with implied
seeks.
I = 1 INTRa occurs when the command is completed and the host has read the sector buffer.
M
=
Multiple Sector Flag
M
=
M
=
0 Transfer one sector. Ignore the SECTOR
COUNT register.
1 Transfer multiple sectors.
L
=
A flowchart of the RESTORE command is shown in
Figure 10.
SEEK COMMAND
The SEEK command can be used for overlapping
seeks on multiple drives. The step rate used is taken
from the Rate Field of the command, and is stored in
an internal register for future use by those commands with implied seek capability.
Long Mode
0 Normal mode. Normal CRC or ECC functions
are performed.
L = 1 Long mode. No CRC or ECC bytes are developed or error checking performed on the
data field. The 82064 appends the four additional bytes supplied by the host or disk to
the data field.
L
=
T
=
Retry Enable
T
=
0 Enable retries.
The direction and number of step pulses needed are
calculated by comparing the contents of the CYLINDER NUMBER registers in the Task Register File to
the present cylinder position stored internally. After
all the step pulses have been issued the present
cylinder position is updated, INTRa is asserted, and
the command terminated.
8-15
82064
If DRDY is deasserted or WR FAULT is asserted
during the execution of the command, INTRa is asserted and the command aborts setting the AC bit in
the ERROR register.
If an implied seek is performed, the step rate indicated by the rate· field is used for all but the last step
pulse. On the last pulse, the command execution
continues until the rising edge of SC is detected. If
10 INDEX pulses are received without a rising edge
of SC, the 82064 will switch to sensing the level of
SC.
RESET INTRD
EARORS.
SET BUSY, CIP
RESET AWe
SET DIRECTION
= OUT
STORE STEP RATE
A flowchart of the SEEK command flow is shown in
Figure 11.
READ SECTOR
PULSE ID
SET INTRQ
RESET, BUSY.CIP
The READ SECTOR command is used to transfer
one or more sectors of data from the disk to the
sector buffer. Upon receipt of the command, the
82064 checks the CYLINDER NUMBER LOW IHIGH
register pair against the internal cylinder position
register to see if they are equal. If not, the direction
and number of steps calculation takes place, and a
seek is initiated. As stated in the description of the
SEEK command, if an implied seek occurs, the step
rate specified by the rate field is used for all but the
last step pulse. On the last step pulse the seek continues until the rising edge of SC is detected.
If. the 82064 detects a change in the drive number
since the last command, an auto-scan 10 is performed. This updates the internal cylinder position
register to reflect the current drive before the seek
begins.
After the 82064 senses SC (with or without an implied seek) it must find an 10 field with the correct
cylinder number, head, sector size, and CRC. If retries are enabled (T = O), ten attempts are made to
find the correct 10 field. If there is still an error on the
tenth try, an auto-scan 10 and auto-seek are performed. Then ten more retries are attempted before
setting the 10 Not Found error bit. When retries are
disabled (T = 1) only two tries are made. No autoscan or auto-seek operations are performed.
ISSUE A
ST£PPULSE
When the data address mark (DAM) is found, the
82064 is ready to transfer data into the sector buffer.
• When the disk has filled the sector buffer, the 82064
asserts BORa and ORa and then checks the I flag.
If 1= 0, INTRa is asserted, signaling the host to
read the contents of the sector buffer. If I = 1,
INTRa· occurs after the host has read the sector
buffer and the command has terminated. If after successfully reading the 10 field, the DAM is not found (
the DAM Not Found bit in the ERROR register is set.
8-16
231242-11
Figure 10. Restore Command Flow
intJ
82064
RESET INlRQ,
ERRORS,
SET BUSY, ClP
STORE STEP RATE
YES
YES
YES
NO
231242-12
Figure 11. Seek Command Flow
8-17
intJ
82064
When M = 1 (Multiple Sector Read)
1.
HOST: Sets up parameters. Issues READ
SECTOR command.
2.
82064: Asserts BCR.
3.
82064: Finds sector specified. Asserts BGR
and BCS. Transfers data to sector buffer.
4.
82064: Asserts BCR. Deasserts BCS.
5.
82064: Asserts BDRa and DRa.
6.
HOST: Reads contents of sector buffer.
7. SECTOR
BUFFER: Indicates data has been transferred by
asserting SRDY.
8.
82064: When BRDY is asserted, decrement
SECTOR COUNT, increment SECTOR
. NUMBER. If SECTOR COUNT = 0, go
to 10.
9.
82064: Go to 2.
10. 82064: Assert INTRa.
An optional M flag can be set for multiple sector
transfers. When M = 0, one sector is transferred
and the SECTOR COUNT register is ignored. When
M = 1, multiple sectors are transferred. After each
sector is transferred, the 82064 decrements the
SECTOR COUNT register am:! increments the SECTOR NUMBER register. The next logical sector is
transferred regardless of any interleave. Sectors are
numbered during the FORMAT command by a byte
in the ID field.
For the 82064 to make multiple sector transfers to
the sector buffer, the BRDY signal must be toggled
from low to high for each sector. The transfers continue until the SECTOR COUNT register equal zero.
If the SECTOR COUNT is not zero (indicating more
sectors remain to be read), and the sector buffer is
full, BDRa will be asserted and the host must unload
the sector buffer. Once this occurs, the sector buffer
is free to accept the next sector.
WR FAULT and DRDY are monitored throughout the
command execution. If· WR FAULT is asserted or
DRDY is deasserted, the command will terminate
and the Aborted Command bit in the ERROR register will be set. For a description of the error checking
procedure on the data field see the explanation in
the section entitled "CRC and ECC Generator and
Checker."
A flowchart of the READ SECTOR command is
shown in Figure 12..
WRITE SECTOR
Both the READ and WRITE commands feature a
"simulated completion" to ease programming.
BDRa, DRa, and INTRa are generated in a normal
manner upon detection of an error condition. This
allows the same program flow for successful or unsuccessful completion of a command.
In summary then, the READ SECTOR operation is
as follows:
When M = 0 (Single Sector Read)
1.
HOST: Sets up parameters. Issues READ'
SECTOR command.
2.
82064: Asserts BCR.
3.
82064: Finds sector specified. Asserts BCR
and BCS. Transfers data to sector
buffer.
4.
82064: Asserts BCR. Deasserts BCS.
5.
82064: Asserts BDRa and DRa.
6.
82064: If I = 1 then go to 9.
7.
HOST: Read contents of sector buffer.
8.
82064: Wait for BRDY, then assert INTRa.
End.
9.
82064: Assert INTRa.
10. HOST: Read contents of sector buffer. End.
8-18
The WRITE SECTOR command is used to write one
or more sectors of data from the sector buffer to the
disk. Upon receipt of the command, the 82064
checks the CYLINDER NUMBER LOW/HIGH register pair against the internal cylinder position register
to see if they are equal. If not, the direction and number of steps calculation takes place, and a seek is
initiated. As stated in the description of the SEEK
command, if an implied seek occurs, the step rate
specified by the rate field is used for all but the last
step pulse. On the last step pulse the seek continues until the rising edge of SC is detected.
If the 82064 detects a change in the drive number
since the last command, an auto-scan ID is performed. This updates the internal cylinder position
register to reflect the current drive before the seek
begins.
After the 82064 senses SC (with or without an implied seek) BDRa and DRa are asserted and the
host begins filling the sector buffer with data. When
BRDY is asserted, a search for the ID field with .the
correct cylinder number, head, sector size, and CRC
is initiated. If retries are enabled (T = 0), ten attempts are made to find the correct ID field. If there
is still an error on the tenth try, an auto~scan ID and
auto-seek are performed. Then ten more retries are
attemp~ed before setting the ID Not Found error bit.
When retries are disabled (T = 1) only two tries are
made. No auto-scan or auto-seek operations are
performed.
.
intJ
82064
' ( READ SECTOR)
l
DE-ASSERT INTRQ,
ERRORS,
ASSERT BUSY, CIP
o
NOTE·
66
*If T bit of command = 1 then dashed path is taken after 2 index pulses.
Figure 12a. Read Sector Command Flow
8-19
231242-13
intJ
82064
NO
o
CORRECT ERROR AND
SET DWC IN STATUS
REG. (BIT 2)
*If T bit of command = 1 then dashed path is taken.
231242-14
* * If T bit of command = 1 then test is for 2 index pulses.
Figure 12b. Read Sector Command Flow (Continued)
8·20
inter
82064
When the correct 10 is found, WR GATE is asserted
and data is written to the disk. When the CRC/ECC
bit (SOH Register, bit 7) is zero, the 82064 generates a two byte CRC character to be appended to
the data. When the CRC/ECC bit is one, four ECC
bytes replace the CRC character. When L = 1, the
polynomial generator is inhibited and neither CRC or
ECC bytes are generated. Instead four bytes of data
supplied by the host are written.
change in drive numbers, only the internal position
register is updated. If a bad block is detected, the
BAD BLOCK bit will also be set.
If an 10 field is not found, or if a CRC error occurs,
and if retries are enabled (T = 0), ten attempts are
made to read it. If retries are disabled (T = 1), only
two tries are made. There is no auto-seek in this
command and the sector buffer is not disturbed.
During a WRITE MULTIPLE SECTOR command (M
= 1), the SECTOR NUMBER register is incremented and the SECTOR COUNT register is decremented. If BRDY is asserted after the first sector is read
from the sector buffer, the 82064 continues to read
data from the sector buffer for the next sector. If
BRDY is deasserted, the 82064 asserts BORa and
waits for the host to place more data in the sector
buffer.
A flowchart of the SCAN 10 command is shown in
Figure 14.
WRITE FORMAT
The WRITE FORMAT command is used to format
one track using information in the Task Register File
and the sector buffer. During execution of this command, the sector buffer is used for additional parameter information instead of data. Shown in Figure 15
is the contents of a sector buffer for a 32 sector
track with an interleave factor of two.
In summary then, the WRITE SECTOR operation is
as follows:
When M·= 0,1
Each sector requires a two byte sequence. The first
byte designates whether a bad block mark is to be
recorded in the sector's 10 field. An OOH is norma!;
an 80H indicates a bad block mark for that sector. In
the example of Figure 15, sector 04 will get a bad
block mark recorded. The second byte indicates the
logical sector number to be recorded. This allows
sectors to be recorded with any interleave factor desired. The remaining memory in the sector buffer
may be filled with any value; its only purpose is to
generate a BRDY to tell the 82064 to begin formatting the track.
1. HOST: Sets up parameters. Issues WRITE SECTOR command.
2. 82064: Asserts BORa and ORO.
3. HOST: Loads sector buffer with data.
4. 82064: Waits for rising edge of BRDY.
5.82064: Finds specified 10 field. Writes sector to
disk.
6. 82064: If M
= 0, asserts INTRO. End.
7.82064: Increments SECTOR NUMBER. Decrements SECTOR COUNT.
If the drive number has been changed since the last
command, an auto-restore is initiated, positioning
the heads to track 000. The internal cylinder position
register is set to zero and the heads seek to the
track specified in the Task Register File CYLINDER
NUMBER register. This prevents an 10 Not Found
error from occuring due to an incompatible format,
or the track having been erased. A normal implied
seek is also in effect for this command.
8. 82064: IF SECTOR COUNT = 0, assert INTRa.
End.
9. 82064: Go to 2.
A flowchart of the WRITE SECTOR command is
shown in Figure 13.
SCAN ID
The SCAN 10 command is used to update the SOH,
SECTOR NUMBER, and CYLINDER NUMBER
LOW/HIGH registers.
The SECTOR COUNT register is used to hold the
total number of sectors to be formatted (FFH = 255
sectors), while the SECTOR NUMBER register holds
the number of bytes, minus three, to be used for
Gap 1 and Gap 3. If, for example, the SECTOR
COUNT register value is 02H and the SECTOR
NUMBER register value is OOH, then 2 sectors are
formatted and 3 bytes of 4EH are written for Gap 1
and Gap 3. The data fields are filled with FFH and
the CRC or ECC is automatically generated and appended. After the last sector is written the track is
filled with 4EH.
After the command is loaded, the SC line is sampled
until it is valid. The DRDY and WR FAULT lines are
also monitored throughout execution of the command. If a fault occurs the command is aborted and
the appropriate error bits are set. When the first 10
field is found, the 10 information is loaded into the
SOH, SECTOR NUMBER, and CYLINDER NUMBER
registers. The internal cylinder position register is
also updated. If this is an auto-scan caused by a
8-21
intJ
82064
*If retries disabled then dashed path is taken after 2 index pulses.
Figure 13. Write Sector Command Flow
8-22
inter
82064
RESET INTRa.
ERRORS
SET BUSY, CIP
SET INTRQ, AC
RESET BUSY, CIP
SEARCH FOR
ANY 10 FIELD
NO
UPDATE SOH,
CYL, SECTOR,
CYL POS, REG'S
'If retries are disabled, path is taken after 2 index pulses.
231242-16
Figure 14. Scan 10 Command Flow
8-23
inter
82064
--
DATA
ADDR
0
00
08
10
18
20
28
30
38
40
00
00
80
00
00
00
00
00
FF
1
00
02
04
06
08
OA
DC
DE
FF
2
3
4
5
6
00
00
00
00
00
00
00
00
FF
10
12
14
16
18
1A
1C
1E
FF
00
00
00
00
00
00
00
00
FF
01
03
05
07
09
DB
OD
OF
FF
00
00
00
00
00
00
00
00
FF
FF
FF
FF
7
11
13
15
17
19
1B
10
1F
FF
:
:
FO
FF
FF
FF
FF
FF
Figure 15. Format Command Buffer Contents
The user may select a value of 4EH or AAH for Gaps
1, 3 and pad bytes. This is done by setting bit 2 (Gap
Filler Byte) of the format command to "0" for a value
of 4EH or "1" for a value of AAH. AAH provides
better frequency discrimination with MFM decoding,
allowing for simpler circuitry.
The COMPUTE CORRECTION command first writes
the four syndrome bytes from the internal ECC register to the sector buffer. Then the ECC register is
clocked. With each clock, a counter is incremented
and the pattern examined. If the pattern is correctable, the procedure is stopped and the count and
pattern are written to the sector buffer, following the
syndrome. The process is also stopped if the count
exceeds the sector size before a correctable pattern
is found.
The Gap 3 value is determined by the drive motor
speed variation, data sector length, and the interleave factor. The interleave factor is only important
when 1:1 interleave is used. The formula for determining the minimum Gap 3 length is:
When the command terminates the sector buffer
contains the following data:
Gap 3 = (2*M*S)+K+E
Syndrome MSB
Syndrome
Syndrome
Syndrome LSB
Error Pattern Offset
Error Pattern Offset
Error Pattern MSB
Error Pattern
Error Pattern LSB
where:
M = motor speed variation (e.g., 0.03 for + 3%)
S = sector length in bytes
K = 18 for an interleave factor of 1
o for any other interleave factor
E = 2 if ECC is enabled (SOH register, bit 7 = 1)
As for all commands, if WR FAULT is asserted or
OROY is deasserted during execution of the command, the command terminates and the Aborted
Command bit in the ERROR register is set.
As an example, when the Error Pattern Offset is zero
the following procedure may correct the error. The
first data byte of the sector is exclusive OR'd with
the MSB of the Error Pattern, the second data byte
with the second byte of the Error Pattern, and the
third data byte with the LSB of the Error Pattern.
Figure 16 shows the format which the 82064 will
write on the disk.
A flowchart of the WRITE FORMAT command is
shown in Figure 17.
If the sector buffer count exceeds the sector size, or
if the error burst length is greater than that selected
by the Set Parameter command, the ECC/CRC error
in the ERROR register and the Error bit in the
STATUS register is set.
COMPUTE CORRECTION
The COMPUTE CORRECTION command determines the location and pattern of a single burst error, but.does not correct it. The host, using the data
provided by the 82064, must perform the actual correction. The COMPUTE CORRECTION command is
used following a data field ECC error. The command
initiating the read must specify no retries (T = 1).
SET PARAMETER
This command selects the correction span to be
used for the error correction process. A 5-bit span is
selected when bit zero of the command equals 0,
and an ii-bit span when bit zero equals 1. The
82064 defaults to a 5-bitspan after a RESET.
8-24
inter
82064
REPEATED FOR EACH SECTOR
~
GAP4 GAPI
4E
4E
(1)
~'DF'ELD~
14 BYTES
'00'
A
1
I
D
E
N
T
C L
Y 0
L W
H
E
A
D
S
E
C
C
R
C
1
#
C
R
C
2
,---DATA F I E L D -
3 BYTES
12 BYTES
'00'
'00'
USER DATA
III
2 CRC
OR
4 ECC
3 BYTES
GAP3
4E
(1 )
'00'
I
I
~:~':---------+-----------+:----~L-'
I I
I
,
WRITE GATE
I
I
I
~
~
I .@/J/II/J/J/I//lIiIl
F
B
'"
I
:
DRUN-.J
A
1
I
I
j
!
t1
I
I
vIl(JiJJIII///II/d
I
I
I
'
l _____________ IL._ _ __
READ GATE----.J
231242-17
10 FIELD
A1
=
IDENT
=
A1H with OAH Clock
HEAD
=
Bits 0, 1, 2 = Head Number
Bits 3, 4 = 0
Bits 5, 6 = Sector Size
Bit 7 = Bad Block Mark
Sec #
=
Logical Sector Number
Bits 3, 1, 0 = Cylinder High
FE = 0-255 Cylinders
FF = 256-511 Cylinders
FC = 512-767 Cylinders
FD = 768-1023 Cylinders
F6 = 1024-1279 Cylinders
. F7 = 1280-1535 Cylinders
F4 = 1536-1791 Cylinders
F5 = 1792-2047 Cylinders
DATA FIELD
A1
A 1 H with OAH clock
F8
Data Address Mark; Normal Clock
USER
Data Field 128 to 1024 Bytes
NOTE:
1. GAP 1 and 3 length determined by Sector Number Register contents during formatting.
Figure 16. Track Format
8-25
intJ
82064
RESET WR GAlt, BCS
PULSE BeR, SET INTRO
RESET BUSY, ClP
231242-18
Figure 17. Write Format Command Flow
8·26
82064
*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O°C to 70°C
Storage Temperature .......... - 65°C to + 150°C
Supply Voltage ................... - 0.5V to + 8V
Voltage on Any Input ......... GND - 2V to + 6.5V
Voltage on Any Output .GND - 0.5V to Vee + 0.5V
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS
Symbol
NOTICE Specifications contained within the
following tables are subject to change.
TA = 0°Ct070°C;Vee
Parameter
=
Min
+5V +10%;GND
Max
Units
=
OV
Test Conditions
= Vee to OV
= Vee to 0.45V
IlL
Input Leakage Current
±10
p.A
VIN
IOFL
Output Leakage Current
±10
p.A
VOUT
VIH
Input High Voltage
2.0
Vee + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
VOH
Output High Voltage
VOL
Output Low Voltage
= -100 /LA
= -2.5 mA
IOL = 2.5 mA
V
Vee - 0.4
3.0
IOH
IOH
0.4
0.45
V
20
45
mA
See Note 10
See Note 11
6.0 mA P21,
22,23
lee
Supply Current
leess
Standby Supply Current
2
mA
See Note 12
CIN
Input Capacitance
10
pF
fc
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
= 1 MHz
For Pins 25, 34, 37, 39 (WR CLOCK, DRUN, READ DATA, READ CLOCK)
TRS
Rise Time
30
A.C. CHARACTERISTICS
TA
=
O°C to 70°C; Vee
=
ns
0.9Vto 4.2V
+ 5V ± 10%; GND = OV
HOST READ TIMING WR CLOCK = 5.0 MHz
Symbol
1
Parameter
Min
Address Stable Before RD
t
Max
0
t
Units
2
Data Delay from RD
3
RD Pulse Width
100
4
Data Valid after RD i
10
5
Address Hold Time after RD i
0
ns
6
Read Recovery Time
300
ns
7
CS Stable before RD
0
ns
t
150
8-27
Test Conditions
ns
ns
ns
100
ns
See Note 6
inter
82064
AO-2
~
K"-___
ADDRESS STABLE
1'-
_-1-0--
@~
- 0 ___
cs
~-+--
~_~I
-®~
RD--------~
r------
I~-lr.@
DBO-7
------c=.x
HOST WRITE TIMING WR CLOCK
Symbol
=
DATA VALID
>-
231242-19
5.0 MHz
Parameter
Min
Units
Max
,J..
0
ns
0
ns
i
75
8
Address Stable Before WR
9
CS Stable Before WR
10
Data Setup Time Before WR
11
WR Pulse Width
12
Data Hold Time After WR
13
Address Hold Time After WR
14
CS Hold Time After WR
15
47
,J..
100
i
ns
ns
10000
0
ns
0
ns
0
ns
Write Recovery Time
300
ns
SDHLE Propagation Delay
20
i
i
Test Conditions
150
See Note 7
ns
AO-2'~_ _~X,---
_-I-®-- GD
@-
cs
1'-
~-+--------~---f'
WR - - - - - ' " I"~--
DBO-7
SDHLE
-------+"""
231242-20
8-28
infef
82064
=
BUFFER READ TIMING (WRITE SECTOR COMMAND) WR CLOCK
Symbol
16
Parameter
Min
BCS..1. to RD Valid
Typ
0
400
5.0 MHz
Max
Units
100
ns
500
ns
17
RD Output Pulse Width
300
18
Data Setup to RD i
140
ns
19
Data Hold from RD i
0
ns
20
RD Repetition Rate
1.2
21
RD Float from BCS i
0
1.6
2.0
p.s
100
ns
Test Conditions
See Note 3
See Note 8
BCS~-:--_®_ _ _ _ _ _ _ _ _ _--1' ~
lm---'"
(OUTPUT)
DB0-7
~------- ®------~~
231242-21
BUFFER WRITE TIMING (READ SECTOR COMMAND) WR CLOCK
Symbol
Parameter
Typ
Min
22
BCS..1. to WR Valid
23
WR Output Pulse Width
0
300
24
Data Valid from WR ..1.
25
Data Hold from WR i
60
26
WR Repetition Rate
1.2
27
WR Float from BCS i
0
400
1,6
=
5.0 MHz
Max
Units
100
ns
500
ns
150
ns
200
ns
2.0
p.s
100
ns
Test Conditions
See Note 3
See Note 8
::~---®=22--------------------------~' ~
(OUTPUT)
®
DATA VALID
DBO-7-------+<'
"-------../
I~.~----®---~.~I
231242-22
8-29
inter
82064
MISCELLANEOUS TIMING
Symbol
Parameter
28
BDRQ Reset from BRDY
29
BRDY Pulse Width
Min
20
31
STEP Pulse Width
Units
200
ns
ns
See Note 4
Step Rate
AU other step rates,
See Notes 14, 15
1.4
1.6
1.8
1.5
1.6
1.7
JLs
JLs
7.6
8.0
8.4
JLs
32
INDEX Pulse Width
500
33
RESET Pulse Width
24
34
RESET J. to BCR J.
0
35
RESET
to WR, CS J.
6.4
36
WR CLOCK Frequency
37
RD CLOCK Frequency
t
Max
400
. BCR Pulse Width
30
Typ
Test Conditions
See Notes 9, 13, 15
=
3.2 JLs/step
ns
WRCLK
See Note 2
1.6·
3.2
JLs
JLs
0.25
5.0
5.25
MHz
50% Duty Cycle
0.25
5.0
5.25
MHz
See Note 5
See Notes 1,15
See Note 1
:::: ----6--1@~
~~
~QOCK-{
STEP----J
~~-{
INDEX~
~
~
,r
r
231242-24
231242-23
READ DATA TIMING WR CLOCK = 5.0 MHZ
Symbol
Parameter
Min
38
RD CLOCK Pulse Width
95
39
RD DATA after RD CLOCK J.
10
t
40
RD DATA before RD CLOCK
41
RD DATA Pulse Width
40
42
DRUN Pulse Width
30
Typ
'Max
Units
Test Conditions
2000
ns
50% Duty Cycle
ns
20
8-30
ns
T38/2
ns
ns
inter
82064
DRUN
231242-25
WRITE DATA TIMING WR CLOCK
Symbol
=
5.0 MHZ
Parameter
43
WR CLOCK Pulse Width
44A
WR CLOCK j to WR DATA j
Min
Typ
Max
Units
Test Conditions
95
2000
ns
50% Duty Cycle
10
65
ns
10
65
ns
10
65
ns
Propagation Delay
448
WR CLOCK J,. to WR DATA J,.
440
WR CLOCK J,. to WR DATA j
45A
WR CLOCK j to EARLY/LATE J,.
458
WR CLOCK J,. to EARLY/LATEJ,.
46A
WR CLOCK j to EARLY/LATEj
468
WR CLOCK J,. to EARLY/LATE j
f---{
36 )---~
WA CLOCK
8WRDATA
231242-26
8-31
82064
A.C. TESTING INPUT, OUTPUT WAVEFORM
.
A.C. TESTING LOAD CIRCUIT
Input Output
,
20
>
TEST POINTS
0.45
0.8
<
DEVICE
UNDER
2.0
lEST
08
231242-27
l
-=-
Cl ;50 PF
100 pF Databus
pins only
231242-28
AC Testing: Inputs Are Driven At 2.4V For A Logic .1, And
0.45V For A Logic .0. Timing Measurements Are Made At
2.0V For a Logic .1, And 0.8V For A Logic .0.
CL Includes Jig Capacitance
NOTES
1. Based on WR CLOCK = 5.0 MHz
2. 24 WR CLOCK periods = 4.a IJ-s at 5.0 MHz.
3. 2 WR CLOCK periods ± 100 ns.
4. Previous restrictions on BRDY no longer apply. There are no restrictions on when BRDY may come. BRDY may be
connected directly to BDRO.
5. WR CLOCK Frequency = RD CLOCK Frequency ± 15%.
6. RD may be asserted before CS as long as it remains active for at least the minimum T3 pulse width after CS is asserted.
7. WR may be asserted before CS as long as it remains active for at least the minimum T11 pulse width after CS is
asserted.
a. a WR CLOCK periods ± 2 WR CLOCK periods.
9. a WR CLOCK periods ± 1 WR CLOCK period.
10. VIL = GND, VIH = VCC, Outputs Open.
11. Vil = o.av, VIH = 2.0V, Outputs Open.
12. WR CLOCK & RD CLOCK = DC, VIL = OV, VIH = Vcc, all output open, CS inactive.
13. This specification is for SCR pulse width during command execution. SCR is also triggered by RESET. In this case, SCR
pulse width is greater than RESET pulse width.
14. 40 WR Clocks ± 2.
15. Specification represents actual functionality of a2064 and WD2010. Previous datasheets contain typographical errors.
8-32
APPLICATION
NOTE
AP-402
November 1987
Multimodule™
Winchester Controller
Using the CHMOS 82064
J.SLEEZER
TECHNICAL MARKETING
Order Number: 231927-001
8-33
intJ
AP-402
1.0 INTRODUCTION
The 82064 Winchester Disk Controller (WDC) was developed to ease the complex task of interfacing Winchester disk drives to microprocessor systems. Specifically, the 82064 WDC interfaces to drives that conform
to the ST506 specification, which is the dominant interface for 5'/. inch drives. This Application Note provides some background on the 82064 WDC, the drive
interfaces and generai software routines. It concludes
with a design example using the 82064 WDC interfaced
to the SBXTM bus. Appendix B contains the listing of
the software necessary to operate this controller board.
The second method of positioning the heads is to use a
voice-coil mechanism. These units do not move in steps
but swing across the disk. These mechanisms generally
permit greater track density than steppers, but also require complex feedback electronics which increases the
cost of the drive. Generally, voice-coil head positioners
use closed loop servo positioning, as compared to the
open loop positioning used with stepper motors.
The surface of a disk is divided logically into concentric
circles radiating from the center as shown in Figure 1.
Each concentric circle is called a track.
The group of tracks, all in the same position, on all of
the disks (platters) in the drive is collectively called a
cylinder. The number of tracks on a surface (which
affects storage density) is determined by the head positioners. Typically, stepper head positioners have fewer
tracks than drives that use a voice coil positioner.
Which type of positioner is used is irrelevant to the
82064 as positioners are part of the drive electronics.
The 82064 can access up to 2048 tracks per surface.
1.1 ST506 Winchester Drive Overview
Since the 82064 WDC interfaces only to drives conforming to the ST506 specification, this overview will
limit itself to those drives. A summary of the ST506
specification is shown in Appendix A for those who are
not familiar with it. The ST506 Winchester Disk contains from 1 to 8 hard disks (or platters) with the average being 2 to 3 disks. These disks are made from aluminum (hence the term hard disk) and are coated with
some type of recording media. The recording media is
typically made of magnetic-oxide, which is similar to
the material used on floppy disks and cassette tapes.
Each side of a hard disk is coated with recording media
and each side can store data. Each surface of a disk has
its own read/write head.
Once the surface is divided into cylinders it is further
divided radially (as with a pie). The area between the
radial spokes is referred to as a sector. The number of
sectors per track is determined by many variables, but
is basically determined by the number of data bytes and
the length of the ID field (which locates a sector). Figure 2 shows one manufacturer's specifications for their
drive. The manufacturer formats the drive with 32-256
byte sectors per track. Alternatively, the drive could be
reformatted to contain 17 - 512 byte sectors per track.
This second option has fewer' sectors per track but
stores more data. Determining how many bytes each
sector contains is done by extensive analysis of the
hardware and operating system. The 82064 WDC is
programmable for sector size during formatting.
Hard disk drives are sealed units because the R/W
heads actually fly above the disk surface at about 8 to
20 microinches. A piece of dust or dirt, which appears
as a boulder to the gap between the heads and the disk
surface, will wreak havoc upon the disk media.
The R/W heads are mechanically connected together
and move as a single unit across the surface of the disk.
There are 2 basic methods for positioning the heads.
The first is with stepper motors, which is the most common method and is also used on most floppy disk
drives. These positioners are used mainly because of
their low cost.
The order in which sectors are logically numbered on
the track is called interleaving. An interleave factor of
four would have three sectors separating logically se- .
quential sectors. Starting at the index pulse, an example
of four way interleaving is:
Sector 1, Sector X, Sector Y, Sector Z, Sector 2, Sector .
231927-1
Figure 1
8-34
intJ
Capacity
Unformatted
Per Drive
Per Surface
Per Track
Formatted
Per Drive
Per Surface
Per Track
Per Sector
Sectors per Track
Transfer Rate
Ap·402
Hard'disk drives tend to be faster than floppies for two
reasons. The speed at which the disk spins is about 10
times faster than the floppy (a floppy spins at 360 rpm
for the popular double density disk drives). This yields
an immediate one-tenth reduction in access times for
the same size drive. While both ST506 drives and floppies use stepper motors, the steppers utilized by the
hard disk drives are approximately twice as fast as
those used by floppies.
6.38 Megabytes
1. 59 Megabytes
10416 Bytes
5.0 Megabytes
1.25 Megabytes
8192 Bytes
256 Bytes
32
5.0 Megabits
per second
2.0 82064 WINCHESTER DISK
CONTROLLER
The 82064 WDC provides most of the functions necessary to interface between a microprocessor and an
ST506 compatible disk drive. The 82064 converts the
high level commands and parallel data of a microprocessor bus into ST506 compatible disk control signals
and serial MFM encoded data. This section presents a
detailed description of the 82064 and a discussion of
various techniques which can be used to interface the
82064 to a microprocessor.
Access Time
Track to Track
3 ms
Average (Inc. Settle)
170 ms
Maximum (Inc. Settle) 500 ms
Settling Time
15 ms
Average Latency
8.33 ms
Functional Specifications
Rotational speed
3600 rpm± 1%
Recording density
7690 bpi max
Flux density
7690 fci
Track density
255 tpi
Cylinders
153
Tracks
612
R/W Heads
4
2
Disks
Figure 2. A Typical Drive Specification
Interleaving is used primarily because one sector at a
time is transferred from disk to sector buffer to system
RAM. This transferring of data takes time, and causes
a delay between the first sector transferred and sectors
that follow it. Without interleaving, the delay in transferring data would result in sectors on the disk rotating
past the heads before they could be read. The operating
system would then have to wait one disk revolution to
get to the next sector (a 16.7 msec delay). With interleaved sectors, the next logical sector would be positioned beneath the heads after the previous sector· of
data had been transferred to the system RAM. Interleaving unfortunately slows down the overall transfer
rate from the disk. A 5 Mbit/second transfer rate averages out to a 1.25 Mbit/second transfer rate when
many sectors are transferred with four way interleaving. Again, how much interleaving to use is determined
by extensive hardware/software benchmarking.
The internal structure of the 82064 is divided into several sections as shown in Figure 3. They are:
1. the microprocessor interface which includes the
status and task registers;
2. sector buffer control;
3. the drive interface;
4. the data transfer section, which includes the MFM
encoding!decoding of microprocessor data;
5. and CRC/ECC generation and checker.
2.1 Clock Inputs
The 82064 has two clock inputs: read clock (RD
CLOCK) and write clock (WR CLOCK). The PLA
controller, the processor interface, buffer control and
MFM encoding sections operate off the WR CLOCK
input. The RD CLOCK input is used only for decoding
the MFM data stream. The clocks may be asynchronous to one another. Both clocks have non-TTL compatible inputs. The easiest method to interface to TTL
requires a pull-up resistor to satisfy their input voltage
needs. The resistor's value must be compatible with the
VIL specification of these pins. See the Pin Descriptions Section for more specific information.
2.2 Microprocessor Interface
Whenever data is stored on a multiple platter disk
drive, the same track on all surfaces whould be used
before repositioning the heads to another track. Repositioning the heads generates a longer delay due to the
mechanical delay of moving the heads. Switching to
another head incurs no mechanical positioning delay.
Only one head can be selected at a time.
The microprocessor interface of the 82064 contains the
control logic which permits commands and data to be
transferred between the host and the 82064. The interface consists of an 8 bit, tri-state, bidirectional data bus;
the task registers; a 3 to 8 address decoder for selecting
one of the seven registers; and the general read, write,
and chip select logic. Externally, the 82064 expects a
buffer equal in size to a sector on the disk, and tri-state
8-35
intJ
AP-402
DIIO-7
WA OATA
WA CLOCK
RDeLOCK
INTAO
HOST
IFC
RO DATA
L-_-;:=:::;:- iDHlE
PL'
CONTROl.LER
STEP
8cR-:::=r.=:]----i______-.J
DIRe
fAiiL'i
8RDY-
em
'DADY
aOAO
m
WR FAULT
TRACie; 000
INDEX
VC<_
SC
GHO-----...
AWC
WRGAT£
RO GATE
L,...;=_~DRUN
231927-3
Figure 3. 82064 Internal Block Diagram
transceivers between the sector buffer and the microprocessors data bus in order to isolate itself from the
microprocessor during disk data transfers.
Once a disk operation starts, CS no longer efffects the
82064. RD and WR are bidirectional lines and are used
to read or write the 82064's registers by the host microprocessor and are valid only if CS is present. The 82064
will drive RD and WR when transferring data between
the sector buffer and the disk. A signal is provided to
tri-srate the RD and WR lines from the host during a
buffer access. This is covered in the Sector Buffer Control Section.
AO-A2, Data Bus
These three address lines are active high signals and
select one of the seven register locations In the 82064.
They are not latched internally. If the three addresses
are equal to 0 and the 82064 is selected, the data bus is
kept tri-stated to ease interfacing to a sector buffer. The
82064's data bus is controlled by both the microprocessor and the 82064. The microprocessor has control for
loading the registers and command. During disk reads
or writes, control switches to the 82064 so that it may
access the local sector buffer when transferring data
between the disk and the buffer.
RD, WR, CS
The chip select (CS) is tyEi£.ally decoded from the higher order address lines. CS only permits data to be
placed into, or read from, the 82064's task registers.
Interrupts
An interrupt is issued at the end of all commands, and
the interrupt is cleared by reading any register. For the
Read Sector command only, the 82064 allows the user
the option of an interrupt either at the termination of
the command, as is the case with all other commands,
'or when data needs to be transferred to the host from
the sector buffer. This is discussed further in the Interrupt Mode Section. When selecting the data transfer
option, the interrupt line will go active at the same time
as the BDRQ line and the interrupt will be removed
only when the proper handshake occurs with the sector
buffer.
8-36
inter
AP-402
high during a multiple sector transfer indicates that the
buffer is full (or empty-depending upon the command) and the transfer should wait until the buffer is
serviced. The sector that was being transferred will finish and the 82064 will deactivate BCS and activate
BDRQ. The host microprocessor must then transfer
the data between the buffer and system memory. When
this transfer is finished, asserting BRDY will cause the
82064 to resume the command.
Task Registers
The Task Register File contains the command, status,
track number, sector number, and other information
necessary to properly execute a command. These registers are accessed with AO-A2, RD (or WR), and CS
being valid and are not cleared by a reset. The registers
are covered in detail in the Task Register File Section.
2.3 Sector Buffer Control
The handshaking between BDRQ and BRDY occurs
only in full sector increments-not on a byte basis. A
high on BDRQ indicates a full sector's worth of data is
required; BRDY going high indicates a full sector of
data is available to the 82064 without interruption.
The 82064 was designed to operate with an external
buffer equal in size to one sector. To ease the design-in
of this buffer, the 82064 provides all of the control signals it needs to operate the buffer. This buffer must be
isolated from the system bus, using tri-state buffers,
during disk transfers to prevent contention during the
period that the 82064 is accessing the buffer. A sector
buffer is generally used to ease interfacing to the system
due to the high disk data rates (625 kbytes/sec), although it is not required.
Only the rising edge of BRDY is valid. A falling edge
may occur at any time without effect. BCR will pulse
and BCS will go active eight byte times (8 bytes X 8
bits/byte X 200 ns/bit = 12.8 microsecorids) before
the first data byte is transferred from the sector buffer
to the disk.
COUNTER
~
The Buffer Chip Select (BCS) line goes active whenever
the 82064 is accessing the sector buffer. This signal
should remove the microprocessors ability to access the
82064 and sector buffer and must enable the sector
butTer for lise by the 82064.
~
RO;=DWRl
~
BROY
Y
At a 5 Mbit/sec disk data rate, the 82064 will access
the buffer every 1.6 microseconds (8 bits X 200 nslbit).
BCS will remain low the entire time the 82064 is accessing the buffer. The 82064 will pulse the appropriate RD
or WR line for each byte transferred.
82064
BCR
231927-2
Figure 4. BRDY Generation Logic
2.4 Data Transfer Logic
This section of the 82064 is responsible for conversion
of serial disk data to parallel data (and vice versa); encoding/decoding of the disk's MFM serial bit stream;
and detecting the address mark.
Buffer Counter Reset (BCR) goes active each time that
BCS changes state. Its purpose is to reset the address
counter of the sector buffer back to zero before and
after the 82064 uses the sector buffer. Its function is
optimized for single sector transfers. Multiple sector
transfers should use a software controlled buffer counter reset and not use BCR as the sector buffer will be
reset to the beginning after each sector is transferred.
Polled Interface
Since the 82064 isolates itself from the host during several commands, the host cannot read the status register
during some periods to determine what course should
be taken. In Figure 10, trying to read the status register
when BCS is active will return indeterminate data. To
prevent the microprocessor from reading this indeterminate data, a hardware generated "Busy" pattern
should be driven .onto the data bus if BCS is active.
This is shown in Figure 11. The status register contains
a data request (DRQ) bit whose timing is equal to the
BDRQ output signal, thus making a polled operation
possible. DRQ will stay set in the status register until a
BRDY is generated.
BDRQ,BRDY
BufTer Data Request (BDRQ) and Buffer Ready
(BRDY) provide the handshake needed to transfer data
between the sector buffer and the host. BDRQ signals
that data must be moved to/from the sector buffer and
the host. BRDY has two functions. Once the transfer
signaled by BDRQ is finished, asserting BRDY will
inform the 82064 that the transfer is completed and
that it may finish executing the command. BRDY is
also used in multiple sector commands. BRDY going
8-37
intJ
AP-402
I
I
o
231927-4
Figure 5. Data Address Mark
One design issue, with the polled interface occurs when
the microprocessor is polling the status and the 82064
deactivates BCS. The microprocessor would normally
read the hardware busy pattern. If BCS is deasserted,
the hardware pattern is disabled and the microprocessor will start to read the real status register. The read
cycle may almost be finished, and the read access period of the 82064 will not be satisfied. The data returned
to the microprocessor will be invalid.
Address Mark Detector
The address mark is a unique 2 byte code written at the
beginning of each ID field and data field. This address
mark serves two purposes. It tells the controller what
type of data is about to be received so that internal
computations can be performed, and to ensure that ID
fields are not sent to the host. The second purpose is to
align the serial data back to the original 8 bit boundaries that existed when data was written (there are no
byte boundaries on a disk).
Interrupt Interface
There are cases where the designer does not want to tie
up the microprocessor with polling. The typical 82064
design will need two interrupts per command. One for a
data transfer and one for the completion of the command. The 82064 has an output to issue an interrupt
when the command has finished. However for data
transfers an' interrupt must be generated from the
BDRQ line as shown in Figure 12 (whether a DMA
controller is used or not). When a data transfer is needed, the 82064 will activate the BDRQ l,ine. The microprocessor will be interrupted and do the data transfer
function. BDRQ will stay active until BRDY is generated, so the system must either use edge triggered interrupts or must not write the end-of-interrupt byte until
BDRQ is removed (this is true of Intel's 8259A).
An address mark is always preceded by the all zeros
synchronization field. The 82064 starts comparing the
incoming data stream when the synchronization field
ends. A high speed comparator is used since the 82064
does not yet know where the proper byte boundaries
, are. When a proper comparison of the address mark is
made the controller starts assembling bytes, starting
with the second byte of the address mark.
The first byte of the address mark is an "AI" Hex, but
purposely violates the MFM encoding rules by removing a clock pulse. In Figure 5, the first example is of a
normal MFM encoded AIH. The second example is of
the address mark and shows the missing clock pulse.
The non-MFM compatible Al is to prevent the host
from issuing a similar data byte and possibly confusing
detection logic.
'
MFM Encoding/Decoding
The second byte specifies either an ID or data field and
is encoded according to normal MFM rules. It is either
an "F8" Hex for a data field, or "FC" through "FF"
for an ID field. The different values correspond to a
range of cylinders on the drive in increments of 256
tracks. The 82064 makes no use of this information, but
writes it for compatibility with the ST506 specification
during formatting.
The MFM encoding section will receive 8 bit parallel
data when a valid command has been recognized and
BRDY has gone high. The parallel data is first serialized and converted to an intermediate, NRZ encoded,
data stream. The serial NRZ data is sent to the MFM
encoding section and then transferred to the disk. Decoding of the MFM bit stream (during disk reads) happens in reverse order.
PLA Control
The control logic operates off the write clock (WR
CLOCK) running at a frequency of the desired tranfer
rate. The MFM decoding portion operates off of the
read clock (RD CLOCK) input, which is supplied by
an 'external phase lock loop. The two clocks need not be
synchronized to each other. Data is written (and hence
read) with the most significant bit first.
The PLA Controller interprets command sent by the
microprocessor. Its operation is synchronized to the
WR CLOCK input. The PLA controller is started
when a command is written into the command register.
It generates control signals and operates in a handshake
mode when communicating with the MFM decoding
block.
8-38
AP-402
If the CRC character generated while reading the' data
does not equal the one previously written, an error exists. If an ID field CRC error occurs the "ID not
found" bit in the error register will be set. If a data field
CRC error occurs the "ECC/CRC" bit in the error
register will be set.
Magnitude Comparator
A 10 bit magnitude comparator is used to calculate the
direction and number of step pulses needed to move the
head from the present cylinder position to the desired
position. A separate high speed equivalence comparator
is used to compare ID field bytes when searching for a
sector ID field.
ECC Generation/Checking
The ECC mode is only applicable to the data field. It
provides the user with the ability to detect and correct
errors in the data field automatically. The commands
and registers which must be considered when ECC is
used are:
1. SDH Register, bit 7 (CRC/ECC)
2. READ SECTOR Command, bit 0 (T)
3. READ SECTOR and WRITE -SECTOR Commands, bit I (L)
2.5 CRC/ECC Generator and Checker
The 82064 provides two options for protecting the integrity of the data field. The data field may have either
a CRC (SDH register, bit 7 = 0), or a 32-bit ECC
(SDH register, bit 7 = I) appended to it. The ID field
is always protected by a CRC.
CRC Generation/Checking
4.
5.
6.
7.
8.
The CRC generator computes and checks the cyclic
redundancy check bytes that are appended to the ID
and data fields. CRC generation/checking is always
done on ID fields. Data fields have a choice between
82064 CRC, internal ECC or externally supplied ECC.
The CRC mode is chosen by setting bit 7 of the SDH
register low. The CRC mode provides a means of verifying the accuracy of the data read from the disk, but
does not attempt to correct it. The CRC generator computes and checks cyclic redundancy check characters
that are written and read from the disk after the ID and
data fields.
To enable the ECC mode, bit 7 of the SDH register
must be set to one.
Bit 0 (T) of the READ Command controls whether or
not error correction is attempted. When T = 0 and an
error is detected, the 82064 tries up to 10 times to correct the error. If the error is successfully corrected, bit
2 of the STATUS Register is set. The host can interrogate the status register and detect that an error
occurred and was corrected. If the error was not correctable, bit 6 of the ERROR Register is set. If the
correction span was set to 5 bits, the host may now
execute the SET PARAMETER Command to change
the correction span to II bits, and attempt the read
again. If the error persists, the host can read the data,
but it will contain errors.
The generator polynomial for the CRC-CCITT (CRC16) code is:
x16
x12
+
+
x12
x4
+
+
x5
x3
+
1 = (x
+ x2 +
x
+ 1)
+ 1)
(x15
+
x14
+
x13
+
The code's capability is as follows:
a) Detects all occurrences of an odd number of bits in
error.
b) Detects all single, double, and triple bit errors if the
record length (including check bits) is less than
32,767 bits.
c) Detects all single-burst errors of sixteen bits or less.
d) Detects 99.99695% of all possible 17 bit burst errors, and 99.99847% of all possible longer burst, assuming all errors are possible and equally probable.
The CRC code has some double-burst capability when
used with short records (sectors). For a 256 byte sector
the code will detect double-bursts as long as the total
number of bits in error does not exceed 7.
COMPUTE CORRECTION Command
SET PARAMETER Command
STATUS Register, bit 2-error correction successful
STATUS Register, bit O--error occurred
ERROR Register, bit 6-uncorrectable error
When T = I and an error is detected, no attempt is
made to correct it. Bit 0 of the STATUS Register and
bit 6 of the ERROR Register are set. The user now has
. two choices:
1. Ignore the error and make no attempt to correct it.
2. Use the COMPUTER CORRECTION Command
to determine the location and pattern of the error,
and correct it within the user's program.
When the COMPUTE CORRECTION Command is
implemented, it must be done before executing any
command which can alter the contents of the ECC
Register. The READ SECTOR, WRITE SECTOR,
8-39
inter
AP-402
SCAN 10, and FORMAT Commands will alter this
register and correction will be impossible. The COMPUTE CORRECTION Command may determine that
the error is uncorrectable, at which point the error bits
in the STATUS and ERROR Registers are set.
The SET PARAMETER Command is used to select a
5-bit or ll-bit correction span.
Although ECC generation starts with the first bit of the
F8H byte in the data 10 field, the actual ECC bytes
written will be the same as if the Al H byte was included. The ECC polynomial used is:
The drive interface of the 82064 contains the logic that
makes possible the storage and reliable recovery .of
data. This interface consists of the drive and head select
logic, the disk control signals, and read and write data
logic as shown in Figure 6. This section describes the
external circuitry which is required to complete the
82064's drive interface.
2.6 Drive Interface
For automatic error correction, the external sector
buffer must be implemented with a static RAM and
counter, not with a FIFO.
--n
2X
DATA RATE
EARLY
LATE
RWC
WRITE
PRECOMP
I
READ DATA
READ CLOCK
DRUN
READ GATE
PHASE
LOCK
LOOP
82064
DATA
RATE
OSC
WRCLOCK
DIR
WR.GATE
STEP
DRIVESEL
STEP
DIRECTION
READY
WRITE FAULT
TRACK 000
~ AWC
::
DRDY
READ DATA
~ SEEK COMPLETE
~
TRACK 000
------
WRITE DATA
~ INDEX
::
INDEX
WR FAULT
~
....
sc
,
'/2
~
TO NEXT
DRIVE
woe
WINCHESTER DRIVE 0
/2
~ HEAD NUMBER
~
~ WRITE GATE
...~
:::
...~
DATA BUS- D
Q,71
ADDRESS-
DAISY CHAIN TO
NEXT DRIVE
(HOLDS DRIVE AND HEAD
SELECTS)
DATA LATCH
231927-5
Figure 6. Drive Interface
8-40
inter
AP-402
D
WR DATA
Q
L
D A Q
T
D C Q
H
C
EARLY
LATE
DELAY LINE
12NS 24NS
WR DATA
TO DRIVE
82064
10~HZ
OSC
RWC
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...... TO DRIVE
231927-6
Figure 7. Write Precompensation Logic
Drive/Head Select
The 82064 has no outputs for selecting the head or
drive. Therefore these signals must be generated by the
user as shown in Figure 6. Data bits 0.,-4 should be
latched whenever the SDH register is written. Bits 0-2
would then be driven onto the drive cable with open
collector buffers. Bits 3 and 4 would be decoded after
being latched, then buffered for the cable. The head
information written to the 82064's SDH register is used
to write the proper ID fields during formatting. Changing the drive bits in the SDH register will cause a Scan
ID to be performed by the 82064 to update non user
accessible registers.
Drive Control
The drive control (STEP, DIR, WR FAULT, TRACK
000, INDEX, SC, RWC, and WR GATE) signals are
merely conditioned for transmission over the drive
cable. The purpose of each pin can be found in the
section on Pin Descriptions and their use in the Command Section.
WR DATA, EARLY, LATE
Figure 7 is a diagram of the interface required on the
write data line. The final stage of the MFM encoding
requires applying the WR DATA to an external flipflop clocked at 10 MHz. The 82064 monitors the serial
write data output for particular bit patterns that require
precompensation to prevent bit shifting. EARLY and
LATE are active on all cylinders and will normally require that RWC be factored into them to activate the
data precompensation on the proper cylinder.
A delay line is required to generate the delayed data for
precompensation since the actual delay varies between
drive manufacturers. EARLY and LATE go active in
the same clock period that generates the data bit to be
shifted.
250 NSEC
RETRIGGERABLE
ONE-SHOT
~F~ ~~_ _ _ _ _ _ _~::::::::::::~_ _ _~
DISK ,;
DATA
t---------,.. DRUN
RD DATA
82064
FILTER
AND
VCO
A
RD CLOCK
~UX
,.....-H_B_ _1~---~;::==:;---------1 RD GATE
+2
1----------+1 WR
CLOCK
231927-7
Figure 8. Data Separator Circuit
8-41
intJ
AP-402
quest input. The DMA controller will generate reads or
writes which will increment an address counter. BRDY
indicates that the data transfer has finished and is issued off the carry-out line (or high order address line)
of the counter. The 82064 will assert BDRQ at this
point and activate BCS to prevent the hostfrom intefering with disklbuffer transfers. There can be no polling
for a data transfer or a register read without an interrupt in this scheme.
RD Data, DRUN, RD Gate
The read data interface is shown in Figure 8, and consists of the data run (DR UN) signal and a phase lock
loop to generate the RD CLOCK input to decode the
serial data. DRUN is generated from a. retriggerable
one-shot with a period just exceeding one bit cell. A
sync field consisting of a string of clock pulses will continually retrigger the one-shot producing a steady high
level on DRUN. The 82064 counts off 16 clock pulses
internally, and if DRUN is still active, will make RD
GATE active. Any byte other than an address mark
will deactivate RD GATE and the sequence starts over.
The phase lock loop generates RD CLOCK which is
used to decode the incoming serial data. Until RD
GATE is activated by the 82064, the phase lock loop
(PLL) should be locked onto a local 10 MHz clock to
minimize PLL lock-up times. When RD GATE is activated, the PLL starts locking onto the incoming data
stream, which should consist of the all zeros sync field.
Once the PLL locks onto this synch field, the 82064
will start examining the serial data for a non-zero byte.
A non-zero byte will be indicated by DRUN dropping
since the address mark follows the sync field and is an
"AI" Hex. This sequence is shown in Figure 9. If the
address mark is detected, and if it was preceded by at
least 9 bytes of zeros, RD GATE will stay active. The
82064 will then assemble bytes of data, and ensure the
proper ID field is found. If a non-zero or non-address
mark byte was detected, RD GATE will go inactive for
a minimum of 2 byte times. If a data field or the wrong
ID field is detected, or the ID field was not preceded by
8 bytes of zeros, then RD GATE goes inactive and the
sequence starts over with the 82064 examining the
DRUN input.
RESET
RD GATE
2.7 Microprocessor Interfaces
This section shows the general 82064 interfaces to a
microprocessor system. There are essentially four interfaces which consist of a combination of polled, DMA,
and interrupts. While the 82064 was designed to interface directly to one type, it accommodates all with minor additional logic.
DMA Interface
The 82064 is designed to use a DMA controller for data
transfer between its sector buffer and the host system,
and to interrupt the host when the command has finished. This interface is shown in Figure 10.
231927-8
When the 82064 determines that a transfer is needed
between the sector buffer and the host (either at the
beginning of a command or through BRDY going active in a multiple sector transfer), it will assert BDRQ.
BDRQ will initiate a DMA transfer via the DMA re-
Figure 9. PLL Control Sequence
8-42
intJ
Ap·402
1----iBRDY
82064
82~A'-~~--------~+---------------~
DRQOI-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _i
INTRO
231927-9
Figure 10.82064 DMA Interface
1----iBRDY
82064
....---H-+-+----------I
BCSI
~.-f:>-----~~+_------------___IRw
231927-10
Figure 11. 82064 Polled Interface
-=
~
~~~:'
BRDY
--"
TO
uP
82064
DATA BUS
_o~
BCSI
RDI
~
WRJ
--;
INTO
WRJ
I
BDRO
INTRO
231927-11
Figure 12. 82064 Interrupt Interface
8-43
intJ
AP-402
3.0 PIN DESCRIPTIONS
Pin No.
Symbol
Type
Name and Function
DIP
PLCC
BCS
1
1
0
BUFFER CHIP SELECT: Output used to enable reading or writing
of the external sector buffer by the 82064. Whe~w, the host
should not be able to drive the 82064 data bus, RD, or WR lines.
BCR
2
2
0
BUFFER COUNTER RESET: Output that is asserted by the 82064
prior to readlwrite operation. This pin is asserted whenever BCS
changes state. Used to reset the address counter of the buffer
memory.
INTRQ
3
3
0
INTERRUPT REQUEST: Interrupt generated by the 82064 upon
command termination. It is reset when the STATUS register is
read, or a new command is written to the COMMAND register.
Optionally signifies when a data transfer is required on Read
Sector commands.
SDHLE
4
4
0
SDHLE is asserted When the SOH register is written by the host.
RESET
5
7
I
RESET: Initializes the controller and clears all status flags. Does
not clear the Task Register File.
RD
6
8
1/0
READ: Tri-state, bi-directional signal. As an input, RD contro~he
transfer of information from the 82064 registers to the host. RD is
an output when the 82064 is reading data from the sector buffer
(BCS low).
WR
7
9
1/0
WRITE: Tri-state, bi-directional signal. As an input, WR controls
the transfer of command or task information into the 82064
registers. WR is an output when the 82064 is writing data to the
sector buffer (BCS low).
CS
8
10
I
CHIP SELECT: .Enables RD and WR as inputs for access to the
Task Registers. It has no effectonce a disk command starts.
Aa- A 2
9-11
11~13
I
ADDRESS: Used to select a register from the task register file.
DBa-DB?
12-19
14-16
18-22
1/0
DATA BUS: Tri-state, bi-directionaI8-bit Data Bus with control
determined by BCS. When BCS is high the microprocessor has full
control of the data bus for reading and writing the Task Register
File. When BCS is low the 82064 controls the data bus to transfer
data to or from the buffer.
Vss
20
23
WR DATA
21
24
0
Ground
WRITE DATA: Output that shifts out MFM data at a rate
determined by Write Clock. Requires an external 0 flip-flop
·clocked at 10 MHz. The output has an active pullup and pulldown
that can sink 4.8 mA.
LATE
22
25
0
LATE: Output used to derive a delay value for write
precompensation. Valid when WR GATE is high. Active on all
cylinders.
EARLY
23
26
0
EARLY: Output used to derive a delay value for write
precompensation. Valid when WR GATE is high. Active on all
cylinders.
WRGATE
24
27
0
WRITE GATE: High when write data is valid. WR GATE goes low if
the WR FAULT input is active. This output is used by the drive to
enable head write current.
WRCLOCK
25
29
I
WRITE CLOCK: Clock input used to derive the write data rate.
Frequency = 5 MHz for the ST506 interface.
8-44
inter
AP-402
3.0 PIN DESCRIPTIONS (Continued)
Symbol
Pin No.
Type
Name and Function
DIP
PLCC
DIR
26
30
0
DIRECTION: High level on this output tells the drive to move the
head inward (increasing cylinder number). The state of this signal
is determined by the 82064's internal comparison of actual
cylinder location vs. desired cylinder.
STEP
27
31
0
STEP: This signal is used to move the drive head to another
cylinder at a programmable frequency. Pulse width = 1.6 /-Ls for a
step rate of 3.2 /-Ls/step, and 8.4 /-Ls for all other step rates.
DRDY
28
32
I
DRIVE READY: If DRDY from the drive goes low, the command
will be terminated.
INDEX
29
33
I
INDEX: Signal from the drive indicating the beginning of a track. It
is used by the 82064 during formatting, and for counting retries.
Index is edge triggered. Only the rising edge is valid.
WR FAULT
30
34
I
WRITE FAULT: An error input to the 82064 which indicates a fault
condition at the drive. If WR FAULT from the drive goes high, the
command will be terminated.
TRACK 000
31
35
I
TRACK ZERO: Signal from the drive which indicates that the head
is at the outermost cylinder. Used to verify proper completion of a
RESTORE command.
SC
32
36
I
SEEK COMPLETE: Signal from the drive indicating to the 82064
that the drive head has settled and that reads or writes can be
made. SC is edge triggered. Only the rising edge is valid.
RWC
33
37
0
REDUCED WRITE CURRENT: Signal goes high for all cylinder
numbers above the value programmed in the Write Precomp
Cylinder register. It is used by the precompensation logic and by
the drive to reduce the effects of bit shifting.
DRUN
34
38
I
DATA RUN: This signal informs the 82064 when a field of all ones
or all zeroes has been detected in the read data stream by an
external one·shot. This indicates the beginning of an 10 field. RD
GATE is brought high when DRUN is sampled high for 16 clock
periods.
BRDY
35
39
I
BUFFER READY: Input used to signal the controller that the buffer
is ready for reading (full), or writing (empty), by the host /-LP. Only
the rising edge indicates the condition.
BDRQ
36
40
0
BUFFER DATA REQUEST: Activated during Read or Write
commands when a data transfer between the host and the
82064's sector buffer is required. Typically used as a DMA request
line.
RD DATA
37
41
I
READ DATA: Single ended input that accepts MFM data from the
drive.
RDGATE
38
42
0
READ GATE: Output that is asserted when a search for an
address mark is initiated. It remains asserted until the end of the 10
or data field.
RDCLOCK
39
43
I
READ CLOCK: Clock input derived from the external data
recovery circuits.
Vee
40
44
I
D.C. POWER:
NC
-
5,6,
17,28
+ 5V.
NO CONNECTS
8·45
inter
AP-402
4.0 TASK REGISTER FILE
The data may be read even ifuncorrectable errorS exist.
The Task Register File is a bank of registers used to
hold parameter information pertaining to each command. These registers and their addresses are:
If the long mode (L) bit is set in the READ or
A2 A1 AO
Bit 5 - Reserved.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
READ
WRITE
(Bus Tri-Stated)
Error Flags
Sector Count
Sector Number
Cylinder Low
Cylinder High
SOH
Status Register
(Bus Tri-Stated)
Reduce Write Current
Sector Count
Sector Number
Cylinder Low
Cylinder High
SOH
Command Register
NOTE:
WRITE command, no error checking is performed.
Not used. Set to zero.
Bit 4 - ID Not Found
This bitis set to indicate that the correct cylinder, head,
sector, or size parameter could not be found, or that a
CRC error occurred in the ID field. Ths bit is set on the
first failure and remains set even if the error is recovered on a retry. When recovery is unsuccessful, the Error bit (bit 0) of the STATUS register is also set.
NOTE:
Registers are not cleared by RESET
For a SCAN ID command with retries enabled (T
0), the Error bit in the STATUS register is set after ten
unsuccessful attempts have been made to find the correct ID. With retries disabled (T = 1), only two attempts are made before setting the Error bit.
4.1 Error Register
This read-only register contains specific error status after the completion of a command. If any bit in this
register is set, then the Error bit in the Status Register
will also be set. The bits are defined as follows:
7
6
5432
1
For a READ or WRITE command with retries enabled
(T = 0), ten attempts are made to find the correct ID
field. If there is still an error on the tenth try, an autoscan and auto-seek are performed. Then ten more retries are made before setting the Error bit. When retries
are disabled (T = 1), only two tries are made. No autoscan or auto-seek operations are performed.
0
IBBOlcRC/ECclollololACITKOOoloMI
Bit 7 - Bad Block Detect (BBD)
Bit 3 - Reserved.
This bit is set when an ID field has been encountered
that contains a bad block mark. The bad block bit is set
only during formatting. The 82064 will terminate a
command if an attempt is made to read a sector that
contains this bit.
Not used. Set to zero.
Bit 2 - Aborted Command
This bit is set if a command was issued or in progress
while DRDY (Pin 28) was deasserted or WR FAULT
(Pin 30) was asserted. The Aborted Command bit will
also be set if an undefined command is written into the
COMMAND register, but an implied seek will be exe.
cuted.
Bit 6 - CRC/ECC Data Field Error (CRC/ECC)
When in the CRC mode (SDH register, bit 7 = 0), this
bit is set when a CRC error occurs in the data field.
When retries are enabled, ten more attempts are made
to read the sector correctly. If none of these attempts
are successful bit 0 in the STATUS register is also set.
If one of the attempts is successful, the CRC/ECC error bit remains set to inform the host that a marginal
condition exists; however, bit 0 in the STATUS register
is not set.
Bit 1 - TRACK 000 Error (TKOOO)
This bit is set only by the RESTORE command. It
indicates that TRACK 000 (Pin 31) has not gone active
after the issuance of 2048 stepping pulses.
When in the ECC mode (SDH register, bit 7 = 1), this
bit is set when the first non-zero syndrome is detected.
When retries are enabled, up to ten attempts are made
to correct the error. If the error is successfully corrected, this bit remains set; however, bit 2 of the STATUS
register is also set to inform the host that the error has
been corrected. If the error is not correctable, the
CRC/ECC error bit remains set and bit 0 of the
STATUS register is also set.
Bit 0 - Data Address Mark
This bit is set during a READ SECTOR command if
the Data Address Mark is not found after the proper
Sector ID is read.
8-46
intJ
AP-402
4.2 Reduce Write Current Register
4.5 Cylinder Number Low Register
This register is used to define the cylinder number
where RWC (Pin 33) is asserted:
This register holds the lower byte of the desired cylinder number:
.
7
6
5
4
3
2
o
7
6
5
3
4
o
2
CYLINDER NUMBER I 4
LS BYTE OF CYLINDER NUMBER
The value (0-255) written into this register is internally
multiplied by 4 to specify the actual cylinder where
RWC is asserted. Thus a value ofOIH will cause RWC
to activate on cylinder 4, 02H on cylinder 8 and so on.
RWC will be asserted when the present cylinder is
greater than or equal to the cylinder indicated by this
register. For example, one ST506 compatible drive requires precompensation on cylinder 128 (80H) and
above. Therefore the REDUCE WRITE CURRENT
register should be loaded with 32 (20H). A value of
FFH will keep the RWC output inactive regardless of
the actual cylinder number.
It is used in conjunction with the CYLINDER NUM-
BER HIGH register to specify a range of 0 to 2048
tracks.
4.6 Cylinder Number High Register
This register holds the three most significant bits of the
desired cylinder number:
7
6
543
Ix
x
x
x
x
o
2
(10)
(9)
(8)
x = ignored
4.3 Sector Count Register
The 82064 contains a pair of registers that store the
actual position where the R/W head are located. The
CYLINDER NUMBER HIGH and LOW registers are
considered the cylinder destination registers for seeks
and other commands. The 82064 compares its internal
registers to the destination registers and issues the number of steps in the right direction to make both sets of
registers equal. After a command is executed, the internal cylinder position registers' contents are equal to the
cylinder high/low registers. If a drive number change is
detected on a new command, the 82064 automatically
reads an ID field to update its internal cylinder position
registers. This affects all commands except a RESTORE.
This register is used to define the number of sectors
that need to be transferred to the buffer during a
READ MULTIPLE SECTOR or WRITE MULTIPLE SECTOR command.
7
6
5
4
3
2
o
# OF SECTORS
The value contained in the register is decremented after
each sector is transferred to/from the sector buffer. A
zero represents a 256 sector transfer, a one a 1 sector
transfer, etc. This register is ignored when single sector
commands are specified in the Command register.
When a RESTORE command is executed, the internal
head location registers are reset to zero while DIR and
STEP move the heads to track zero.
4.4 Sector Number
This register holds the sector number of the desired
sector:
7
6
543
2
4.7 Sector/Drive/Head (SOH) Register
o
The SDH register contains the desired sector size, drive
number, and head number parameters. The format is
shown below.
SECTOR NUMBER
For a multiple sector command it specifies the first sector to be transferred. It is decremented after each sector
is transferred to/from the sector buffer. The SECTOR
NUMBER register may contain any value from 0 to
255. The ID Not Found bit will be set if the desired
sector cannot be located on the track.
7
EXT
6
5
SECT
SIZE
4
3
DRIVE
2
0
HEAD #
Both head number and sector size are compared against
the disk's ID field. Head select and drive select lines are
not available as outputs from the 82064 and must be
generated externally.
The SECTOR NUMBER register is also used to program the Gap I and Gap 3 lengths to be used when
formatting a disk. See the WRITE FORMAT command description for further explanation.
8-47
inter
AP-402
Bit 3 - Data Request
Bit 7, the extension bit (EXT), is used to select between
the CRC or ECC mode. When bit 7 = I, the ECC
mode is selected for the data field. When bit 7 = 0, the
CRC mode is selected. The CRC is checked on the ID
field regardless of the state of EXT. The SDH byte
written into the ID field is different than the SDH Register contents. The recorded SDH byte does not have
the drive number (DRIVE) written but does have the
BAD BLOCK mark written.
The. Data request bit (DRQ) reflects the state of the
BDRQ (Pin 36) line. It is set when the sector buffer
should be loaded with data or read by the host processor, depending upon the command. The DRQ bit and
the BDRQ line remain high untilBRDY indicates that
the sector buffer has been filled or emptied, depending
upon the command. BRDQ can be used for DMA.
Bit 2 - Data Was Corrected (DWC)
Note that use of the extension bit requires the gap
lengths to be modified as. described in the WRITE
FORMAT command description.
When set, this bit indicates that an ECC error .has been
detected during a read operation, and that the data in
the sector buffer has been corrected. This provides the
user with an indication that there may be a marginal
condition within the drive before the errors become uncorrectable. This bit is forced to zero when not in the
ECC mode.
4.8 Status Register
The status register is a read-only register which informs
the host of certain events. This register is a flowthrough latch until the microprocessor reads it at
which point the drive· status lines are latched. The
INTRQ line will be reset when this register is read. The
format is:
Bit I - Command in Progress
76543210
IBUSY IREADY IWF ISC IORO IOWC ICIP IERROR I
Bit 7 - Busy
When this bit is set, a command is being executed and a
new command should not be loaded until it is cleared.
Although a command may be executing, the sector
buffer is still available for access by the host processor.
When the 82064 is no longer busy (bit 7 = 0) the status
register can be read. If CIP is set, only the status register can be read regardless of which register is selected.
Bit 0 - Error
This bit is asserted when a command is written into the
COMMAND register and, except for the READ command, is deasserted at the end of the command. When
executing a READ command, Busy will be deasserted
when the sector buffer is full. Commands should not be
loaded into the COMMAND register when Busy is set.
When the Busy bit is set, no other bits in the STATUS
or ERROR registers are valid.
This bit is a logical OR of the contents of the error
register. Any bit being set in the error register sets this
bit. Th~ host must read the ERROR register to determine what type of error occurred. This bit is cleared
when a new command is loaded.
4.9 Command Register
During other non-data transfer commands, Busy
should be ignored as it will go active for short periods.
This write-only register is loaded with the desired command:
Bit 6 - Ready
7
This bit reflects the state of the DRDY (Pin 28) line at
the time the microprocessor reads the status register.
Transitions on the DRDY line will abort a command
and set the aborted command bit in the error register.
6
5
4
3
2
o
COMMAND
The 82064 begins to execute immediately upon loading
any value into this register. This register should not be
written while the Busy or Command in Progress bits
are set in the STATUS register. The INTRQ line (Pin
3) if set, will be cleared by a write to the COMMAND
register.
Bit 5 - Write Fault
This bit reflects the state of the WR FAULT (Pin 30)
line. Transitions on this line will abort a command and
set the aborted command bit in the error register.
Instruction Set
Bit 4 - Seek Complete
The 82064 WDC instruction set contains six commands. Prior to loading the command register, the host
processor must first set up the Task Register File with
the information needed for the command. Except for
This bit reflects the state of the SC (Pin 32) line. Commands which initiate a seek will pause until Seek Complete is set.. This bit is latched after an aborted command error.
8-48
intJ
AP-402
the COMMAND register, the registers may be loaded
in any order. If a command is in progress, a subsequent
write to the COMMAND register will be ignored. A
command is finished when the command in progress
(CIP) bit in the STATUS register is cleared. See the
Command Section for an explanation of each command.
7654 3
COMMAND
RESTORE
o 0 0 1 R3
SEEK
o 1 1 1 R3
READ SECTOR
001 0 I
WRITE SECTOR
o0 1 1 0
SCAN 10
o1 0 0 0
WRITE FORMAT
o1 0 1 0
COMPUTE CORRECTION 0 0 0 0 1
0000 0
SET PARAMETER
2
5.0 PROGRAMMING THE 82064
This section consists of two parts. The first part gives
an explanation of each command, a flowchart showing
the 82064's sequence of events, and the commands' sequence of events as seen by the host microprocessor.
The second section shows flowcharts of general software routines and their PLM equivalent, for both
polled and interrupt driven software.
1
R2
R2
M
M
0
0
0
0
R1 RO
R1
0
0
0
0
0
0
The designer must remember that the 82064 expects a
full sector buffer that can be isolated from the host
during data transfers between the 82064 and the disk.
Since the 82064 assumes a full sector buffer is available,
it does not check for data overrun or underrun error
conditions. If such a condition occurs, corruption of
data will happen and the host will have no indication of
an error. The design must guarantee against over-run
and under-run ,conditions when not using the sector
buffer approach.
RO
T
T
T
0
0
S
R 3-0 = Rate Field
For 5 MHz WR Clock:
5.1 Commands
0000- ::::35,...s
0001-0.5 ms
0010-1:0ms
0011-1.5ms
0100-2.0 ms
0101-2.5 ms
0110-3.0 ms
0111-3.5 ms
1000-4.0 ms
1001 -4.5 ms
1010-5.0 ms
1011-5.5ms
1100-6.0 ms
1101-6.5 ms
1110'-3.2,...s
1111-16,...s
COMMAND
T =
7
A command is placed into the command register only
after the Task Registers have been written with proper
values. The Task Registers may be loaded ,in any order.
A command, once started, can only be terminated by a
hardware reset to the 82064. This may corrupt data on
the disk by removing necessary control signals out of
sequence.
The general sequence of a command is as follows:
- The host loads the Task Registers
- The host loads the Command Register
- The 82064 locates the correct cylinder
- Data transfer takes place
- The 82064 issues an interrupt
6
5
4
3
2
Restore Command -
1
o 0 0 1 R3 R2 R 1 RO
Retry Enable
The Restore command is used to position the heads to
track O. This command is usually issued to the 82064
on power-up to initialize internal registers. The user
specified rate field (R3-RO) is stored internally for FUTURE use in commands with implied seeks.
T = 0 Enable Retries
T = 1 Disable Retries
M=
Multiple Sector Flag
M=O Transfer 1 Sector
M=1 Transfer Multiple Sectors
I =
The step rate value is not used with this command. The
actual stepping rate used is dependent upon the handshake delay between the 82064 issuing a step pulse and
the drive returning a seek complete for each track. After each step pulse is issued, the 82064 waits for a rising
edge on the Seek Complete (SC) line before issuing the
next pulse. If 8 index pulses are received without a rising edge on SC, the 82064 will switch to sampling the
level of the SC line. If after 2048 step pulses the Track
00 signal has not gone active, the 82064 will terminate
Interrupt Enable
I =0 Interrupt at BORQ time
I = 1 Interrupt at end of command
S =
Error Correction Span
S = 0 5-bitSpan
S =1 11-bit Span
8-49
AP-402
RESET INTRQ.
EARORS.
SEY BUSY, CIP
RESET Awe
SET DIRECTION
-OUT
STORE STEP RATE
PULSE iiCJI
SET INTRQ
RESET BUSY,CI'
YES
231927-13
ISSUE A
STEP PULSE
Figure 14. Seek CommandFlow
her of step pulses issued is calculated by comparing the
cylinder high/low regiSters to an internal "present position" cylinder register. The present position register is
updated after all step pulses are issued aild the command is terminated.
231927-12
Figure 13. Restore Command Flow
the command, assert INTRQ and set the TRACK 000
bit in the Error Register. The command will terminate
if WR Fault goes active or DRDY goes inactive at any
time. Figure 13 is a flow chart of the command.
The actual stepping rate is taken from the rate field bits
(R3-RO) and stored for future use. The command terminates at once if WR FAULT goes active or DRDY
goes inactive at any time. Figure 14 is a flowchart of the
command.
Seek Command 1 1 1 R3 R2 R1RO
o
Since the data transfer commands feature implied
seeks, this command is of use mainly to those using
multiple drives and software that can take advantage of
overlapped seeks.
.
The Seek command positions the heads to the cylinder
specified in the Task Registers., The direction and num8-50
infef
AP-402
Scan 10 Command 0100000T
The Scan ID command is used by both the 82064 and
the host to update the SDH, the Sector Number, Cylinder and internal present position registers. Once the
command is issued, the Seek Complete line is sampled
until valid. The first ID field found, as indicated by the
address mark, is loaded into the previously mentioned
registers. The Bad Block bit will be set if detected, and
the command will terminate. ID CRC errors will start
the search sequence over for a maximum of 10 index
pulses, but the registers will be loaded with whatever
data the 82064 had perceived as ID information. Improper states on WR Fault on DRDY will terminate
the command. Figure 15 is the flow chart of the command.
SET INTRa, AC
RESET BUSY, CIP
The main use for this command is to determine where
the heads are currently located and what size the sectors are (i.e. 256, 512 etc.). Without this command, it
would be necessary to recall the heads to track zero and
then step out to the desired cylinder each time a drive
was changed. Specifying the wrong sector size would
yield an ID not found error. This command enables the
system to read the disk drive to determine what size
sectors were recorded.
Read Sector Command 0010lMOT
The READ SECTOR command is used to transfer one
or more sectors of data from the disk to the sector
buffer. Upon receipt of the READ SECTOR command, the 82064 checks the CYLINDER NUMBER
LOW /HIGH register pair against an internal cylinder
position register to see if they are equal. If not, the
direction and number of steps are calculated and a seek
takes place. If an implied seek is performed, the 82064
will search until a rising edge of SC is received. The
WR FAULT and DRDY lines are monitored throughout the command.
·IF RETRIES ARE DISABLED, PATH
IS TAKEN AFTER 2 INDEX PULSES
231927-14
Figure 15. Scan 10 Command Flow
Once the Seek Complete (SC) line is high (with or without an implied seek having occurred), the search for an
ID field begins. If T = 0 (retries enabled), the 82064
must find an ID with the correct cylinder number,
head, sector size, and CRC within 10 revolutions, or a
Scan ID and re-Seek will be performed. The search for
the proper ID will again be tried for up to 10 revolutions. If the correct sector is still not found, the appropriate error bits will be set and the command terminated. Data CRC errors will also be retried for up to 10
revolutions (if T = 0).
Both the READ SECTOR and WRITE SECTOR
commands feature a "simulated completion" to ease
programming. DRQ/BDRQ will be generated upon detecting an error condition. This allows the same program flow for successful or unsuccessful completion of
a command.
When the data address mark is found, the 82064 is
ready to tranfer data to the sector buffer. After the data
has been transferred, the I bit is checked. If I = 0,
INTRQ is made active coincident with BDRQ, indicating that a transfer of data from the buffer to the host
processor is required. If I = 1, INTRQ will occur at
the end of the command, i.e. after the buffer is unloaded by the host.
If T = 1 (retries disabled), the ID search must find the
correct sector within 2 revolutions or the appropriate
error bits will be set and the command terminated.
8-51
inter
AP-402
In summary then, READ SECTOR operation is as follows:
When M = 0 (READ SECTOR)
(
(
(
(
1)
2)
3)
4)
( 5)
( 6)
( 7)
( 8)
( 9)
(10)
( 1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Host:
82064:
82064:
82064:
82064:
82064:
Host:
82064:
82064:
Host
Sets up parameters; issues READ SECTOR command.
Strobes SCR.
Finds sector specified; asserts SCR and SCS; transfers data to buffer.
Sets BCR = 1, SCS = O.
Sets BDRa = 1; DRa = 1.
If I bit =.1 go to (9).
Reads contents of sector buffer.
Waits for BRDY, then sets INTRa = 1: END.
Sets INTRa = 1.
Reads out contents of buffer; END.
When M
=
Host:
82064:
82064:
82064:
82064:
Host:
82064:
82064:
82064:
82064:
Sets up parameters; issues READ SECTOR command.
Assert SCR.
Finds sector specified; asserts BCR and SCS; transfers data to buffer.
Strobes SCR; sets SCS = O.
Sets BDRa = 1; DRa = 1.
Reads out contents of buffer.
Waits for SRDY; Decrements SECTOR COUNT; increments SECTOR NUMBER.
When BRDY = 1, if Sector Count = 0 then go to (10).
Go to (2).
Set INTRa = 1; End.
1 (READ MULTIPLE SECTOR)
A flowchart of the READ SECTOR command is shown in Figures 16A and 16B.
The M bit is set for multiple sector transfers. When
M = 0, one sector is transferred and the SECTOR
COUNT register is ignored: When M = I, multiple
sectors are transferred. After each sector is transferred,
the 82064 decrements the SECTOR COUNT register
and increments the SECTOR NUMBER register. The
next logical sector will be transferred regardless of any
interleave. Sectors are numbered at format time.
and number of steps calculation is performed and a
seek takes place. The WR FAULT and DRDY lines
are checked throughout the command.
When the Seek Complete (SC) line is found to be true
(with or without an implied seek having occurred), the
BDRQ signal is made active and the host proceeds to
load the buffer. Once BRDY goes high, the ID field
with the specified cylinder number, head, and sector
size is searched for. Once found, WR GATE is made
active and the data is written to the disk. If retries are
enabled (T = 0), and if the ID field cannot be found
within 10 revolutions, a Scan ID and re-Seek are performed. If the correct ID field is not found within 10
additional revolutions, the. ID Not Found error bit is
set and the command is terminated. If retries are disabled, (T = I) and if the ID field cannot be found
within 2 revolutions, the ID Not Found error bit is set
and the command is .terminated.
Multiple sector transfers continue until the SECTOR
COUNT register equals zero, or the BRDY line goes
active (low to high). If the SECTOR COUNT register
is non-zero (indicating more sectors are to be transferred but the buffer is full), BDRQ will be made active
and the host must unload the buffer. After this occurs,
the buffer will again be free to accept the remaining
sectors from the 82064. This scheme enables the user to
transfer more sectors than the buffer memory has capacity for.
During a WRITE MULTIPLE SECTOR command
(M = 1), the SECTOR NUMBER register is decremented and the SECTOR COUNT register is incremented after the transfer to the disk takes place. During multiple sector transfers if BRDY is asserted after
the first sector is transferred from the buffer, the 82064
will transfer the next sector before issuing BDRQ. The
82064 will set BDRQ and wait for the host processor to
place more data in the buffer.
Write Sector Command ,....
01110MOT
The WRITE SECTOR command is used to write one
or more sectors of data to the disk from the sector
buffer. Upon receipt of a WRITE SECTOR command
the 82064 checks the CYLINDER NUMBER LOW/
HIGH register pair against the internal cylinder position register to see if they are equal. If not, the direction
8-52
intJ
AP-402
In summary then, the WRITE SECTOR operation is as follows:
When M = 0, 1 (WRITE SECTOR)
( 1)
Host:
( 2)
82064:
( 3)
Host:
( 4)
82064:
82064:
82064:
82064:
82064:
82064:
( 5)
( 6)
( 7)
( 8)
( 9)
Sets up parameters; issues WRITE SECTOR command.
Sets BORa = 1, ORa = 1.
Loads sector buffer with data.
Waits for BRDY = 0 to 1.
Finds specified 10 field; writes sector to disk.
If M = 0, then set INTRa = 1; END.
Increment SECTOR NUMBER register; decrement SECTOR COUNT register.
If SECTOR = 0, then set INTRa = 1; END.
Go to (2).
A flowchart of the WRITE SECTOR command is shown in Figure 17.
register holds the number of bytes (minus three) to be
used for Gap I and Gap 3. For instance, if the SECTOR COUNT register value is 02H and the SECTOR
NUMBER register value is OOH,theri 2 sectors are
written on a track and 3 bytes of 4EH are written for
Gap I and Gap 3. The data fields are filled with FFH
and the CRC is automatically generated and appended.
All gaps are filled with 4EH. After the last sector is
written, the track is filled with 4EH until the index
pulse terminates the write. The Gap 3 value is determined by the drive motor speed variation, data sector
length, and the interleave factor. The interleave factor
is only important when 1:1 (no) interleave is used. The
formula for determining the minimum Gap 3 length
value is:
Write Format Command
01010000
The WRITE FORMAT command is used to format
one track using the Task Register File and the sector
buffer. During execution of this command, the sector
buffer is used for additional parameter information instead of sector data. Shown in Figure 18 is the contents
of the sector buffer for a 32 sector/track format with an
interleave factor of two. Each sector requires a two byte
sequence. The first byte designates whether a bad block
mark is to be recorded in the sector's ID field. A 00
Hex is normal; an 80H indicates a bad block mark for
the sector. In the example of Figure 18, sector 04 will
get a back block mark recorded. Any attempt to access
sector 4 in the future will terminate the command.
Gap 3
The second byte indicates the logical sector number to
be recorded. This allows sectors to be recorded with
any interleave factor desired. The remaining memory in
the sector buffer may contain any value. Its only purpose is to generate a BRDY to tell the 82064 to begin
formatting the track. An implied seek is in effect on this
command. As for other commands, if the drive number
has been changed an ID field will be scanned for cylinder position information before the implied seek is performed. If no ID field can be read (because the track
had been erased or because an incomplete format had
been used), an ID Not Found error will result and the
WRITE FORMAT command will be aborted. This can
be avoided by issuing a RESTORE command before
formatting.
=
(2 * M • S)
+K+
E
= motor speed variation (e.g., 0.03 for
M
S
K
K
= 0 for any other interleave factor
E
=
± 3%)
= sector length in bytes
=
25 for interleave factor of I
7 if the sector is to be extended
As with all commands, a WR FAULT or drive not
ready condition, will terminate execution of the
WRITE FORMAT command. Figure 19 shows the
format that the 82064 will write on the disk. The extend bit in the SDH register must not be set during the
Format command.
A flowchart of the WRITE FORMAT command is
shown in Figure 20.
The SECTOR COUNT register is used to hold the total
number of sectors to be formatted (OIH = I sector;
OOH = 256 sectors), while the SECTOR NUMBER
8-53
inter
AP-402
(
READ SECTOR)
i
DE-ASSERT INTRQ,
ERRORS,
ASSERT BUSY, CIP
o
231927-15
NOTE:
• If T = 1, then "dashed" path is taken after 2 index pulses.
Figure 16A. Read Sector Command Flow
8-54
inter
AP-402
NO
231927-16
* If T bit of command = 1, then dashed path is taken.
* * If T bit of command = 1, then test is for 2 index pulses.
Figure 16B. Read Sector Command Flow (Continued)
8-55
inter
AP-402
231927-17
NOTE:
*11 retries are disabled, the "dashed" path is taken after 2 index pulses.
Figure 17. Write Sector Command Flow
8-56
AP-402
00
80
00
00
FF
AA
00
00
04
08
DC
FF
00
no
00
00
FF
AA AA
00
00
10
14
18
1C
FF
AA
00
~-----.---
00
00
00
00
FF
AA
00
01
05
09
00
FF
00
00
00
00
FF
AA AA
00
00
11
15
19
10
FF
AA
00
00
00
00
00
FF
AA
00
02
06
OA
DE
FF
AA
00
12
15
19
1E
FF
00
00
00
00
FF
AA AA AA
00
00
00
03
07
DB
OF
FF
AA
00
00
00
00
00
FF
AA
00
13
17
1B
1F
FF
AA
00
Figure 18. Sector Buffer Contents For Format
---------------------------,
...
~r---------------REPEATED
FOR EACH SECTOR
, - - - - - · · - 1 0 FIELD
GAP 4
4E
00
00
00
00
FF
I
D
GAP 1 14 BYTES A
E
4E
1
00
N
T
c------DATA F I E L D -
C
Y
L
S C
S
E R
D
C
C
H
# 1
C
R 3 BYTES 12 BYTES
C
00
00
A F
1 6
USER DATA
2
WRITE GATE
C C
R R 3 BYTES GAP 3
4E
C C
00
1 2
-1
231927-18
Figure 19. 82064 Sector Format
For commands that do make use of the sector buffer,
the size of the sector buffer will affect the software. If
the sector buffer is equal in size to one sector, then a
carry out of an address counter (for the sector buffer)
as the buffer is being filled will indicate to the 82064
that the command should continue. If the sector buffer
size is equal to two or more disk sectors, and only one
sector is being transferred, then the carry out signal
would not go active, and the 82064 will be forever waiting for BRDY In this case an I/O port would have to
be used to generate this signal for the 82064 so that
command execution can finish. Figure 22 is a flowchart
of the READ SECTOR command, and its PLM representation. The WRITE SECTOR and FORMAT
TRACK commands are equivalent in terms of software
interfacing. Their flowcharts and their PLM equivalents are shown in Figure 23.
5.2 Software Section: General
Programming
This section describes the software needed to communicate with the 82064 in order to store and retrieve data.
This chapter describes the software in a general manner
and Appendix B contains the actual implementation
used to exercise the 82064 SBX board.
Polled Mode
As discussed in the Polled Interface Section, the 82064
does not directly support polled operation for data
transfers without the addition of hardware. This section
is based upon the polled interface as described in the
Polled Interface Section.
Once the command register is written the 82064 requests a data transfer before locating the proper track.
Once the buffer is filled and BRDY is asserted, the
82064 will locate the target track and sector. If the ID
is not located before the selected number of retries have
occurred, the 82064 will terminate the command. The
data transferred to the sector buffer will not have been
used. Once the command has finished (i.e., CIP = D),
the status and error registers will inform the host of an
error.
The six 82064 commands can be divided into two
groups, those with data transfers and those without.
The commands that do not use the sector buffer are:
Restore, Seek and Scan ID. The functions of each command are explained in the Commands Section. Figure
21 is a flowchart of a polled operation and a PLM example.
The last status that was read will contain any error
conditions that might have occurred during the command.
.
8-57
inter
AP·402
231927-19
Figure 20. Write Format Command Flow
8·58
AP-402
> ___-' YES
231927-20
'*
*'
Disk$Operation: Procedure;
Call Write$82064$Task$Reg's;
Write Task Registers
Output (Command$Reg) = Command;
Status = Input (Status$Reg); /* Read Status Reg .,
Do while Status and CIP = CIP; /* Wait until command finishes .,
Status = Input (Status$Reg);
End;
End Disk$Operation;
Figure 21. Polling Status
8·59
inter
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AP-402
READ SECTOR COMMAND
231927-21
Disk$Operation: Procedure;
Call Write$82064$Task$Regs;
Output (Command $ Reg) = Command;
Status = Input (Status$Reg);
Do while Status and CIP = CIP;
If Status and DRQ = DRQ then Do;
Call Read$Data$From$Buffer;
Output (BRDY$PORT) = 01;
End;
Stat us = Input (Stat us$Port )
End;
End Disk$Operation;
Figure 22. Polling For Read Data
8-60
inter
AP-402
WRITE, FORMAT COMMANDS
NO
MOVE DATA
FROM SYSTEM
RAM TO SECTOR
BUFFER
231927-22
Disk$Operation: Procedure;
Call Write$82064$Task$Regs;
Output (Command$Reg) = Command;
Status = Input (Status$Reg);
Do while status and CIP = CIP;
I f status and DRQ = DRW then do;
Call Write$Data$to$Buffer;
Output (BRDY$Port) = 01; /* Make BRDY go active
End;
Status = Input (Status$Reg)
End;
End Disk$Operation;
Figure 23. Polling For Write Data
8-61
*'
intJ
AP-402
*'
Disk$Operation: Procedure;
Call Write$82064$Task$Regs; ,. Write registers
Output (Command$Reg) = Command;
Start command "'
Status = Input (Status$Reg); /* Read status "'
Do while' status and CIP = CIP; /* Is a command in progress .,
I f status and DRQ = DRQ then do; /* Data transfer? = yes .,
If command = Read$Sector then
Call Read'$Data$From$Buffer; /* ,Remove data .,
Else Call Write$Data$to$Buffer;
Send data
Output (BRDY$PORT) = 01; ,. Toggle BRDY 0 to 1
End;
End Disk$Operation;
'*
'*
*' *'
Figure 24. Complete Polled Flow
Start$Disk$Operation: Procedure;
Call Write$82064$Task$Reg's;
Output (Command $ Reg) = Command;
End Start$Disk$Operation;
Figure 25. Interrupt Mode; Starting a Disk Transfer
Figure 24 is the PLM routine that allows for all six of
the commands, It ditTers from the READ and WRITE
routines in that the direction that data is to be transferred is determined by the command,
only have to read the status register. If the interrupt is
issued at BDRQ the host would remove the butTer data
and generate BRDY, At this point the status and error
registers contain valid information. Generating an interrupt at BDRQ time may save some systems some
software overhead.
Figure 24 also works for mUltiple sector transfers.
However, the BRDY signal must be generated in hardware (the carry-out of an address counter).
The WRITE SECTOR and FORMAT commands do
not have this option because the sector butTer is filled
before the track and sector are located. Hence, there
can be significant delays between asking for data and
the command terminating.
Interrupt Mode
Interrupt driven software is chosen when the microprocessor must execute other tasks and cannot sit waiting for the disk to reposition its heads, as in a polled
environment. The delay in repositioning heads can be
anything from a couple of milliseconds to a second or
more.
In an, interrupt driven environment, the 82064 can interface to a DMA controller for data transfers between
the sector butTer and the ' host's RAM. If a DMA controller is not available an interrupt must be generated
via the BDRQ line. However, BDRQ can stay active
for long periods of time (until BRDY is generated), The
interrupt sensing logic must take this into account to
avoid being retriggered constantly. Intel's 8259A Interrupt Controller 8259Aprovides that capability, It
should be programmed for edge triggered interrupts or
the end of interrupt byte must not be issued until
BDRQ is removed to prevent retriggering.
The 82064's interrupt (INTRQ) pin goes active to'indicate that the command has fmished. The READ SECTOR command provides the programmable choice of
having the interrupt occur at the end of the data transfer or the normal end of the command. The reason for
this option is that when the 82064 signals that a data
transfer is required (via BDRQ, DRQ) the disk has
been read and the data has been placed in the butTer.
The host would remove the data and issue BRDY, The
82064 would then issue an interrupt indicating that the
command has finished. The interrupt procedure would
Figure 25 is a PLM example of starting a disk operation in an interrupt driven environment. The command
starts, and some indefinite amount of time later an interrupt would be generated, indicating service is required.
8-62
AP-402
End$of$Transfer: Procedure Interrupt;
Status = Input (Status$Register);
Output (8259A PIC) = End$of$Interrupt;
End End$of$Transfer;
Figure 26. Checking Status via Interrupt
Service$Disk$Controller: Procedure Interrupt;
Status = Input (Status$Port);
If Status and DRQ = DRQ then
Call Transfer$Data$To/From$Buffer;/* Enable DMAC */
Output (8259A PIC) = End$of$Interrupt;
End Service$Disk$Controller;
Figure 27. Complete Interrupt Procedure
If a DMA controller is used, it would have to be programmed and initialized before the command is issued
to the 82064. Recall that once a data transfer between
the microprocessor and 82064 has finished, BRDY
must be set high. As long as BRDY is generated from
hardware, no microprocessor intervention is needed. If
BRDY is generated by an I/O port the microprocessor
will have to perform this function (this will be the case
with any system that has a sector buffer larger than one
sector). (One option could be to generate an interrupt
from the terminal count pin of the DMA controller.
The microprocessor would then issue a BRDY.) Data
transfers between host RAM and the sector buffer
would be handled without microprocessor intervention.
The interrupt would then signal that the command has
finished as shown in Figure 26. The only operation the
host processor would perform is to check the status
register of the 82064 for any error conditions.
6.0 APPLICATION EXAMPLE
This section shows an application using the 82064 interfaced to the SBX bus. A quick overview of the SBX
bus is provided (pin descriptions, general wave forms)
as a background for the application. Designing the
82064 onto an SBX Multimodule board was chosen to
highlight the size and complexity differences between
earlier TTL, MSI, LSI-based disk controller boards and
what is possible using the 82064. Both the hardware
and software sections will be applicable to most other
designs using the 82064. This design example is called
SBX82064 and does not represent a real product offered by Intel Corporation. Appendix C contains the
schematic of the SBX board.
The advantage of the SBX Multimodule is that it permits the system to be tailored for specific needs with a
minimum of effort. The advantage of an SBX based
disk controller is that a current system can make use of
the capacity, reliability and speed of a hard disk with
no (or minimal) hardware redesign.
If BDRQ is used to generate an interrupt in addition to
the normal interrupt, then the routines shown in Figure
27 will check the status register to see if a data transfer
should be executed or if the command is finished. If
DRQ is not set, the command has finished and any
error conditions would be in the status register.
6.1 iSBX Bus Multimodule Boards
The iSBX Multimodule boards are small, specialized,
I/O mapped boards which plug onto base boards. The
iSBX boards connect to the iSBX bus connector and
convert the iSBX bus signals to a defined I/O interface.
Another possibility would be to have separate interrupt
routines for the two possible sources of interrupts
(INTRQ, BRDQ). There would then be no need to test
the status to see which interrupt had occurred.
8-63
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AP-402
ISBX BOARD
USER CONNECTOR
iSBX BOARD
INTEL SUPPLIED
CONNECTOR
~:,
~
..
ii
!! ~
~
BASE BOARD
231927-23
Figure 28. iSBX Multimodule Board Concept (Double Wide)
Base Boards
Control Lines
The base board decodes I/O addresses and generates
the chip selects for the iSBX Multimodule boards. In 8bit systems, the base board decodes all but the lower
three addresses in generating the iSBX Multimodule
board chip selects. In 16-bit systems, the base board
decodes all but the lower order four addresses in generating the iSBX Multimodule board chip selects. Thus, a
base board would normally reserve two blocks of 8 I/O
ports for each iSBX socket it provides.
The following signals are classified as control lines:
There are two classes of base boards, those with Direct
Memory Access (DMA) support and those without.
Base boards with DMA support are boards with DMA
controllers on them. These boards, in conjunction with
an iSBX Multimodule board (with DMA capability),
can perform direct I/O to memory or memory to I/O
operations.
COMMANDS:
lORD (I/O Read)
IOWRT (I/O Write)
DMA:
MDRQT (DMA Request)
MDACK (DMA Acknowledge)
TDMA (Terminate DMA)
, INITIALIZE:
RESET
CLOCK:
MCLK (iSBX Multimodule Clock)
SYSTEM CONTROL:
MWAIT
MPST (iSBX Multimodule Board Present)
iSBX Bus Interface
Command Lines (lORD, IOWRT)
The iSBX bus interface can be grouped into six functional classes:
1. Control Lines
2. Address and Chip Select Lines
3. Data Lines
4. Interrupt Lines
5. 'Option Lines
6. Power Lines
The command lines are active low signals which provide the communication link between the base board
and the iSBX Multimodule board. An active command
line, conditioned by chip select, indicates to the iSBX
Multimodule board that the address lines are valid a'nd
the iSBX Multimodule board should perform the specified operation.
8-64
inter
AP-402
DMA Lines (MDRQT, MDACK, TDMA)
Address Lines:
MAO-MA2
The DMA lines are the communication link between
the DMA controller device on the base board and the
iSBX Multimodule board. MDRQT is an active high
output signal from the iSBX Multimodule board to the
base board's DMA device requesting a DMA cycle.
MDACK is an active low input signal to the iSBX
Multimodule board from the base board DMA device
acknowledging that the requested DMA cycle has been
granted. TDMA is an active high output signal from
the iSBX Multimodule board to the base board.
TDMA is used by the iSBX Multimodule board to terminate DMA activity. The use of the DMA lines is
optional as not all base boards will provide DMA channels and not all iSBX Multimodule ,boards will be capable of supporting a DMA channel.
Chip Select Lines:
MCSO-MCS1
The base board decodes I/O addresses and generates
the chip selects for the iSBX Multimodule boards. The
base board decodes all but the lower order three addresses in generating the iSBX Multimodule board chip
selects.
Address Lines (MAO-MA2)
These positive true input lines to the iSBX Multimodule boards are generally the least three significant bits
of the I/O address. In conjunction with the command
and, chip select lines, they establish the I/O port address being accessed. In 16-bit systems, MAO-MA2
may be connected to ADR1-ADR3 of the base board
address lines.
Initialize Lines (Reset)
This input line to the iSBX Multimodule board is generated by the base board to put the iSBX Multimodule
board into a known internal state.
Chip Select Lines (MCSO-MCS1/)
In an 8-bit system, these input lines to the iSBX Multimodule board are the result of the base board I/O decode logic. MCS is an active low signal which conditions the I/O command signals and thus enables communication with the iSBX Multimodule boards.
Clock Lines (MCLK)
This input to the iSBX Multimodule board is a timing
signal. The 10 MHz (+ 0%, - 10%) frequency can
vary from base board to base board. This clock is asynchronous from all other iSBX bus signals.
6.2 The SBX82064 Design Example
The SBX82064 Multimodule board will interface an
ST506 compatible drive to any host board having an
SBX connector. Two restrictions on the disk drive are
that there is a maximum of 2048 cylinders and/or 8
heads. The SBX connector cannot supply the power-up
current requirements of the drive. The drive must be
connected directly to the power supply. The SBX82064
in Appendix C does not support DMA transfers. The
version in Appendix D does support DMA transfers.
Since this multimodule has a 2 kbyte sector buffer, the
host microprocessor must generate a BRDY by accessing an I/O port during data transfers.
System Control Lines
(MWAIT, MPSn
These output signals from the iSBX Multimodule
board control the state of the system.
An active MWAIT (Active Low) will put the CPU on
the board into wait states providing additional time for
the iSBX Multimodule board to perform the requested
operation. MWAIT must be generated from address
(address plus chip select) information only. If MWAIT
'is driven active due to a glitch on the CS line during
address transitions, MWAIT must be driven inactive in
.
less than 75 ns.
The software for communicating to the SBX board is
intended to be interrnpt driven. Polling for data transfers is not supported. Reading the status without an
interrupt is not recommended. During the times the
82064 is accessing the sector buffer, the SBX82064 will
isolate itself from the host. To support polling, a hardware generated busy pattern should be driven onto the
host's data bus as is shown in the Polled Interface section. The sector buffer stores up to 2 kbytes of disk
data, for multiple sector transfers. The SBX board only
interfaces to one drive (for space reasons), but four
drives could be used with the addition of a read data
mUltiplexor (one IC) and the drive data cables.
The iSBX Multimodule board present (MPST) is an
active low signal (tied to signal ground) that,informs
the base board I/O decode logic that an iSBX Multimodule board has been installed.
Address and Chip Select Lines
The address and chip select lines are made up of two
groups of signals.
8-65
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Ap·402
Microprocessor Interface
Sector Buffer Isolation Logic
Figure 29 is a block diagram of the SBX82064's microprocessor interface. The I/O port assignments are listed
in Table 1. The functional blocks of the interface are:
The host will be isolated from the SBX board whenever
the 82064 is accessing its sector buffer which is enabled
by BCS. The host's control signals, RD, WR, MCSO,
and MCSI and data bus are also disabled at the same
time to prevent any data in the sector buffer from being
corrupted. The host should wait for an interrupt before
reading the 82064's Status register. Attempting to read
the SBX board while BCS is active will return invalid
data, since the SBX board will have the data bus tristated.
.
Sector Buffer Isolation Logic
Wait State Logic
Sector Buffer
Sector/Drive/Head Register Logic
Table 6·1 1/0 Port Assignments
Port Address
Read
Write
BOH
B2H
B4H
BSH
BBH
BAH
BCH
BEH
90H
92H
94H
Sector Buffer
Error Reg
Sector Count
Sector Number
Cylinder Low
Cylinder High
SOH Reg
Status Reg
None
None
None
Sector Buffer
RWCReg
Sector Count
Sector Number
Cylinder Low
Cylinder High
SOH Reg
Command Reg
None
Asserts BCR
Asserts BROY
Wait State Logic
The wait state logic drives the 'not ready' line,
MWAIT, active whenever the host reads the SBX
board. MWAIT does not go active for buffer or 82064
register writes. This logic was required for two reasons.
First, a delayed read is generated, because the address
setup to RD margin of the SBX bus is less than the
82064's needs (50 ns vs 100 ns). Second, the RD to data
valid access period of the 82064 (375 ns), is greater than
the SBX bus' full speed read cycle (275 ns) permits.
NOTE:
Address assignments are determined by the host board.
MWAIT
+MFM RD DATA
-MFM AD DATA
INDEX
TRACKO
sc
READY
WR FAULT
HOO
H01
HO'
2 TO 4
DECODER
t------t
iiSo
Ds1
Ds2
DSa
231927-24
Figure 29. 82064 sex Multimodule Diagram
8-66
inter
AP-402
MWAIT is deactivated after allowing for the delayed
RD and the access period of the 82064. This delay is
accomplished with a 500 ns delay line. The first tap at
100 ns generates the read request to allow for the address setup margin. The next tap 400 ns later removes
MWAIT to allow the host to continue.
Disk Interface
Figure 30 is a block diagram of the interface between
the 82064 and the disk drive. The functional blocks are:
Write Data Logic
Read Data Logic (PLL)
Drive Control
Sector Buffer
The sector buffer consists of an address counter (using
'ls393's) and a 2 kbyte static RAM. The address counter is incremented on the trailing edge of a valid RD or
WR cycle, either host microprocessor or 82064 initiated. The counter is reset by a hardware reset, the 82064
buffer reset BCR, or by accessing an 1/0 port to provide software control. The 82064 will issue BCR each
time BCS changes state (i.e. twice per sector). Resetting
the buffer counter can be put under software control for
multiple sector transfers. BRDY going high tells the
82064 that the buffer is available for its use. BRDY is
generated by the address counter, by filling or emptying
the entire buffer in multiple sector transfers, or from an
1/0 port when single sector transfers are done (since
single sectors won't use all 2 kbytes of the buffer, the
hardware signal will not be generated). When the 82064
is using the buffer, BCS will be low, and the RD or WR
line will be pulsed every 1. 6 microseconds.
Write Data Logic
The WR DATA output requires a D flip-flop clocked
at 10 MHz to complete the conversion of data to MFM.
The output of this D flip-flop is true MFM and is sent
to a delay line. A delay line determines the amount of
delay for precompensation. No delay corresponds to
shifting the data bit early; the first tap is approximately
12 ns of delay and is the "normal", or no delay and the
second tap provides 12 ns of delay, referenced to the
"normal" write data. Which output is selected is determined by the states on RWC, Early and Late. This
function was generated with a 74s151 multiplexer.
When RWC is inactive EARLY and LATE only select
"normal" data since they are always active. The precompensated write data is then driven onto the data
cable by an RS-422 driver.
When the 82064 is using the buffer it prevents access by
the host by tristating the read, write, select and data
lines with a low on BCS.
Read Data Logic
The PLL generates the RD CLOCK that is used to
decode the serial MFM data from the drive. A selected
drive issues read data, unless WR GATE is active. A
one-shot generates a pulse of 220-270 ns to provide the
DRUN input. Only during an all zero's or one's field
will the DRUN input stay high, as it will be retriggered
every 200 ns (the minimum distance that separates continuous clock and data bits). As soon as DRUN is determined to be valid, the RD GATE output will go
active, switching the PLL from the 10 MHz local clock
input to disk data. The PLL will synchronize to the
incoming serial data and generate a Read Clock of the
proper timing and phase. The 82064 will then start to
search for the address mark which is indicated by
DRUN going low at the address mark.
SDH Register Logic
The drive and head select bits must be latched externally to the 82064, since these outputs are not provided.
An 8 bit latch is strobed on the trailing edge of the WR
pulse when the SDH register is selected. The two drive
select bits are then demultiplexed to provide a one of
four drive select line. If multiple drives are used then
these outputs would also be used to select which disk's
read data line would be gated into the PLL.
Interrupts
No detail is provided herein on PLL design, as it is
beyond the scope of this document. PLL design should
be left to experienced designers, since minute changes
in temperature and component values will drastically
affect the soft error rate. As an alternative, several companies manufacture very high speed PLL chips for
MFM encoded disk drives. Besides being fairly easy to
design in, they reduce the number of components and
board area needed for the sophisticated PLL.
While the interrupt line is programmable (to notify of
an end of command or data transfer request for the
Read Sector command only), software will ensure that
the interrupt from the 82064 signifies command termination. The BDRQ line is OR'ed with the 82064's
INTRQ line or BDRQ can generate its own interrupt.
BDRQ is also gated off-board for a DMA controller.
8-67
inter
AP-402
RD GATE
DRUN
RD DATA
DATA
RECOVERY
I-
RD CLOCK
82064
HOST (
WRITE
PRECOMPENSATION
AND
SYNCHRONIZATION
WR DATA
EARLY
DATA/CTRL
LATE
RWC
STEP
DIR
DRDY
WR FAULT
TRACK 000
·1
~
DRIVE
BUFFER!
RECEIVERS
INDEX
SC
WRGATE
231927-25
Figure 30. 82064 Disk Interface Block Diagram
The host board did not have a DMA controller available, so an interrupt is issued from the BDRQ line and
OR'ed with the 82064's interrupt line as interrupt
sources were limited by the host. When an interrupt
occurs, the interrupt procedure checks for either a data
transfer, and executes it, or the completion of the command. If the interrupt signifies command completion,
the interrupt procedure fills the command block with
the 82064's task, status and error registers.
6.3 Software Driver Overview
Presented in Appendix B is a listing of the software
used to exercise the SBX 82064 board. Communication
between the host software and the SBX driver routine is
done through a structure located in system RAM. The
host routine fills in required parameters, then passes the
address of this communication block to the SBX driver
routine. The driver routine pulls necessary values from
this command block (CBL), executes a disk operation,
then fills the CBL with the 82064's register contents,
plus status and error information. The command block
structure is shown in Figure 31.
In this example, the host software examines one byte in
the command block and until this byte is changed to a
00, no other command blocks will be passed to the disk
driver routine. An alternative would be to issue a software interrupt to notify the microprocessor that the
disk operation has finished and the command block
contains parameters from the last operation and that a
new disk command could start.
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Pointer
Command
Rwc Reg
SectorCnt.
Sector Num.
Cyl Low
Cyl High
SOH Reg
Status Reg
Error Reg
Host Buffer
The driver for this example allows polling for non-data
transfer commands, and must use interrupts for data
transfers. As mentioned earlier, microprocessor intervention is required since the sector buffer is much larger than one sector and will not generate a BRDY. The
microprocessor must write to an I/O port, which sets
BRDY, after each host to sector buffer transfer. An
Figure 31
8-68
infef
AP-402
actual software implementation wonld not include the
polling and interrupt routines together, as only one
method would generally be used.
If the interrupt driven method was chosen, the disk
driver routine returns to the calling routine. This permits other processing to be performed while the disk is
executing a command. At some point, an interrupt will
be generated, either from BRDY or INTRQ. Control
will pass to the driver and the status register will be
checked. If a data transfer is needed, either the microprocessor can transfer data or a DMA controller can
perform the function. Once the transfer .of data to the
buffer is finished the microprocessor must set BRDY
through an I/O port.
The calling routine, which would normally be a directory program, places the values for which sector, number of sectors, etc., in the CBL. The disk routine is
called and the address of this structure is passed on the
stack. The disk driver places these parameters in the
82064's Task registers and initiates a command.
8-69
AP-402
APPENDIX A
ST506 INTERFACE
The encoding rules for MFM are fairly simple:
1. A clock bit is written when the previous and the
current bit cell does not contain a data bit.
2. A data bit is written whenever there is a "one" from
the user.
THE 5T506 INTERFACE
The ST506 interface is a modified version of Shugarts
floppy disk drive interface and has been promoted by
Seagate Technology. This interface is intended to be
easy and low in cost to implement, yet provide a medium level of performance. The interface rigidly defines
several areas: the hardware interconnects, the data
transfer rate, the data encoding method, and how the
disk is formatted.
Sync fields are composed of zeroes which generates a
series of clock bits in the bit cell's. A phase lock loop
locks on to the data stream during this period and generates a signal of the proper phase and frequency which
is used to decode the combined clock and data serial
data stream.
Data Transfer Rate
The data transfer rate depends upon the linear bit density of the disk media and the speed at which the disk
spins. ST506 specifies a 5 Mbit/second transfer rate.
The typical ST506 drive has a nominal linear density of
10,416 bytes and a disk speed of 3600 rpm, which yields
a 5 Mbit/second data transfer rate. No deviation from
5 Mlbits second is allowed.
Disk Format
All disk media must be written with a specified format
so that data may be reliably stored and retrieved. The
smallest unit of controller accessible data is the sector
which typically contains sync fields, ID fields, and a
data field, and buffer fields.
Increasing the linear density to increase storage capacity would require a decrease in disk speed. Otherwise,
the data rate would increase. This decrease in disk
speed would cause access times to increase, which
many would deem unacceptable. To increase storage
capacity, and remain ST506 compatible, either the
number of cylinders and/or the number of platters can
increase.
The format of the disk required by ST506 is shown in
Figure A-2. It should be noted that this format is fixed
in the 82064. The user has options only for GAPI and
3 length (when changing sector size or EeC) and
whether to have 82064 eRe checking or user supplied
Eee syndrome bits.
Gap 1 - Index Gap
Data Encoding
Gap I serves two purposes. The first is to allow for
variations in the index pulse timing due to motor speed
variations. The second purpose is to allow a small delay
to permit a different head to be selected without missing a sector. This is more of a data transfer optimization function and requires the disk controller to know
which head is to be selected, when the last sector of a
track has been read, and the next logical sector in the
file exists on another platter. The 82064 does not switch
heads automatically. Whether this scheme can be used
or not depends upon the /A-P being able to alter one
register in the 82064, before the next sector passes beneath the heads.
ST506 requires that the serial data, sent between the
drive and the controller, be encoded according to MFM
rules. The basic unit of storage is a bit cell, which stores
one bit information. This bit cell is divided into two
halves, consisting of a clock bit and a data bit (see Figure A-I).
CLOCK BIT
I
DATA BIT
CLOCK BIT
I
DATA BIT
This gap is typically 12 bytes long and is written by the
82064 as 4E Hex.
THIS WOULD EQUAL A USER 0 THIS WOULD EQUAL A USER 1
231927-26
FigureA-1
8-70
infef
AP-402
'4E' H and is about 320 bytes when CRC and 256 byte
sectors are used. The 82064 writes this field only during
formatting. The user has no control over the number of
bytes written with the 82064.
Gap 2 - Write Splice Gap
This gap follows the CRC bytes of the ID field and
continues up to the data field address mark. When updating a previously written sector, motor speed variations could turn on the write coil, as the head was passing over the ID field. This gap prevents this from occurring. The value written is OOH and also serves as
the PLL sync field for the data field. The minimum
value is determined by the "lock up" performance of
the PLL. The 82064 writes sixteen bytes for this field
once WG is activated. The user has no control over this
field.
ID Fields
The controller uses ID fields to locate any individual
sector. An address mark of two bytes precedes the ID
field and the data field in a sector. An address mark
tells the controller the nature of the upcoming information. ID fields are used by the disk controller and are
not passed to the host.
Gap 3 - Post Data Field Gap
Sector Interleaving
Gap 3 is very similar to Gap 2 as it is used as a speed
tolerance buffer also. Without this gap, and with the
motor speed varying slightly, it would be possible for
the upcoming sector's sync field and ID field to be
overwritten. This value is '4E' H and is typically 15
bytes long. The 82064's Gap 3 length is programmable.
The exact value is dependent upon several factors. Refer to 82064 Format command, Software Section: General Programming Section.
Sector interleaving occurs when logical sectors are in a
non-sequential order, which is determined during formatting. An advantage is that there is a delay between
logically sequential sectors. This delay can be used for
data processing and then deciding if the next sector
should be read. Without interleaving, the next sector
could slip by, imposing a one revolution delay (approx.
16.7 ms). An additional benefit to this delay is that bus
utilization is reduced by spreading the data transfer
over a greater amount of time. The delay between sectors can be determined as follows:
Gap 4 - Track Buffer Gap
1 Revolution Period
Sectors/Track x (Interleave factor - 1) = Delay
This gap follows the last sector on a track and is written
until an index pulse is received. Its purpose is to prevent the last sector from overflowing past the index
gap, and absorb track length variations when ECC is
used (ECC uses more bytes than CRC). The value is
~
GAP 4
4E
For the typical ST506 drive with four-way interleaving
this yields 1.57 ms of delay.
REPEATED FOR EACH SECTOR
~IDFIELD-
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GAP 1 14 BYTES A 0 CL E
YO
1
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4E'
00
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00
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WRITE GATE
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USER DATA
C
R
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00
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10 FIELD
DATA FIELD
A1 • A1 HEX WITH OA HEX CLOCK
IDENT • 2LS.B. • CYLINDER HIGH
FE • 1).255 CYLINDERS
FF • 256-511 CYLINDERS
FC • 512-767 CYLINDERS
FD • 168-1023 CYLINDERS
F6 • 1024-1279 CYLINDERS
F7 • 1290.1535 CYLINDERS
F4 • 1536-1791 CYLINDERS
F5 • 1792·2047 CYLINDERS
AI • AI HEX WITH OA HEX CLOCK
FB • DATA ADDRESS MARK; NORMAL CLOCK
USER "" DATA FIELD 128 TO 1024 BYTES
HEAD. BITS 0, I, 2 • HEAD NUMBER
BITS 3,4 =0
BITS 5, 6 • SECTOR SIZE
BIT 7 • BAD BlOCK MARK
SEC # = LOGICAL SECTOR NUMBER
231927-27
Figure A-2. Format Field
8-71
inter
AP-402
HOST SYSTEM
FLAT CABLE OR TWISTED PAIR
20 FEET MAXIMUM
ST506
1 ..
RESERVED
-
2
RESERVED (HD SELECT 22'......;,
4
-WRITE GATE
6
-SEEK COMPLETE
8'
-TRACK 0
10
-WRITE FAULT
12
-HEAD SELECT 20
14
RESERVED
16
-HD SELECT 2'
18
-INDEX
20
-READY
22
-STEP
24
-DRIVE SELECT 1
26
-DRIVE SELECT 2
28
-DRIVE SELECT 3
30
-DRIVE SELECT 4
32
-DIRECTION IN
34
3 ..
5 ..
7
9 ..
11
13
15
oj
17 ..
19 ~
.21
23
25 ..
27"
29
31 ...
33
V
231927-28
Figure A-3
host of certain conditions. A diagram of the 34 pin
control connector is shown in Figure A-3.
The disadvantage to interleaving is that file transfers
take longer, which may slow down the overall system.
A four-way interleaved disk will have the transfer rate
reduced to an average of 1.25 Mbit/sec.
The driver/receiver logic diagram is shown in Figure
A-4 and the electrical characteristics are:
The 82064 leaves the logical sector sequence to the
user.
True
False
Voltage
0.0 VDC to 0.4 VDC
2,5 VDC to 5.25 VDC
Current
. -40 mA (IOl max.)
250 /LA (IOH open)
ELECTRICAL INTERFACE
+5V
The interface to the ST506 drive is divided into three
categories and they are:
1. control signals,
2. data signals,
3. power.
220n
7438
20 FT.
74LS14
Control Signals
231927-29
The functions of the control signals are not covered in
detail here. Their purpose can be found in the pin descriptions section. All control lines are digital in nature
and either provide signals to the drive or inform the
Figure A-4
8-72
inter
AP-402
Data Signals
The lines associated with the transfer of read/write data between the host and the drive are differential in nature and
may not be multiplexed between drives. There is one pair of balanced lines for each read and write data line per drive
and must conform to the RS-422 specification. Figure A-5 shows the receiver/transmitter combination.
20 FT.
HIGH TRUE
Z=105
231927-30
Figure A-5. E1A RS22 Driver/Receiver Pair Flat Ribbon or Twisted Pair
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inter
AP-402
APPENDIX C
This appendix contains a schematic of the previous design using PAL's to rel?lace the random logic. The previous
design could not do DMA transfers and inserted a large delay when transferring data from buffer RAM to the
system. The PAL version does do DMA transfers and buffer reads happen at full SBX bus speed. One other minor
change was to replace the 500 ns delay line with a 74LS164, which is a more cost effective solution.
This schematic is .only a paper design since only random logic was replaced with the PAL's.
PAL Equation's
PAL - Page 1:
BDRDI = (IORDI • MDACK/l + (IORDI • MCSOI • MAO • MAl • MA2) +
(DELAYED-READI • CLK) IF BCS
(MCSOI • MAOI • MAl • MA2 • IOWR/)
LTCHSDHI =
+
RAMSELI
(MCSO • MAO • MAl * MA2)
IOBRDYI
(MCS11 • MAOI • MAl • MA21 • IOWR/l
IOBCRI =
+
(MDACK/)
(MCS11 • MAO • MAlI • MA21 • IOWR/l
BDWRI =
CSI
(BCS/)
(IOWR/l IF BCS
(MCSO/) IF BCS
CLK
(MCSO/' MAO • MAlI • MA2/l + (MCSO/,' MAOI • MAl • MA2/l + (MCSOI
• MAO • MAl • MA2/l + (MCSOI • MAOI • MAlI • MA2) + (MCSOI • MAO • MAlI •
MA2) + (MCSOI • MAOI • MAl • MA2) + (MCSOI * MAO ,* MAl • MA2)
PAL - Page 2:
MINTR1/MDRQT
MINTRO =
COUNT =
=
(PIN2)·
(BDWRI
RSTCOUN,T =
+
+
(INTRQ)
BDRD/l • (RAMSELIl
(IOBCR/l
OEI = (MDACK/l
CLRI =
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231428-2
Figure 1. Architectural Block Diagram (Continued)
9-3
UPI-452
TABLE OF CONTENTS
Introduction
Table of Contents
List of Tables and Figures
Pin Description
Architectural Overview
Introduction
FIFO Buffer Interface
FIFO Programmable Features
Immediate Commands
DMA
FIFO/Slave Interface Functional Description
Overview
Input FIFO Channel
Output FIFO Channel
Immediate Commands
Host & Slave Interface Special Function Registers
Slave Interface Special Function Registers
External Host Interface Special Function Registers
FIFO Module-External Host Interface
Overview
Slave Interface Address Decoding
Interrupts to the Host
DMA Requests to the Host
FIFO Module-Internal CPU Interface
Overview
Internal CPU Access to FIFO via Software Instructions
General Purpose DMA Channels
Overview
Architecture
DMA Special Function Registers
DMA Transfer Modes
External Memory DMA
Latency
DMA Interrupt Vectors
Interrupts When DMA is Active
PMA Arbitration
Interrupts
Overview
FIFO Module Interrupts to Internal CPU
Interrupt Enabling and Priority
FIFO-External Host Interface FIFO DMA Freeze Mode
Overview
Initialization
Invoking FIFO DMA Freeze Mode During Normal Operation
FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode
Internal CPU Read & Write of the FIFO During FIFODMA Freeze Mode
. Memory Organization
Accessing External Memory
Miscellaneous Special Function Register Descriptions
9-4
UPI-452
LIST OF TABLES AND FIGURES
Figures:
1.
2.
3.
4.
5.
6.
7a.
7b.
8.
9.
10.
11.
12.
Tables:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11 a.
11 b.
12.
13.
Architectural Block Diagram
UPI-452 68-Pin PGA Pinout Diagram
UPI-452 Conceptual Block Diagram
UPI-452 Functional Block Diagram
Input FIFO Channel Functional Block Diagram
Output FIFO Channel Functional Block Diagram
Handshake Mechanisms for Handling Immediate Command IN Flowchart
Handshake Mechanisms for Handling Immediate Command OUT Flowchart
DMA Transfer from: External to External Memory
DMA Transfer from: External to Internal Memory
DMA Transfer from: Internal to External Memory
DMA Transfer Waveform: Internal to Internal Memory .
Disabling FIFO to Host Slave Interface Timing Diagram
Input FIFO Channel Registers
Output FIFO Channel Registers
UPI-452 Address Decoding
DMA Accessible Special Function Registers
DMA Mode Control - PCON SFR
Interrupt Priority
Interrupt Vector Addresses
Slave Bus Interface Status During FIFO DMA Freeze Mode
FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Threshold SFRs Range of Values and Number of Bytes to be Transferred
80C51 Special Function Registers
UPI-452 Additional Special Function Registers
Program Status Word (PSW)
PCON Special Function Register
9-5
Component Pad View-As viewed from the underside of
component when mounted on the board.
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P2.1
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P.C. Board View-As Viewed from the Component Side of the P.C. Board
(Underside of Socket)
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P4.6
P4.7
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61
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58
57
56
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55
54
53
52
51
50
49
48
47
46
45
1
2
3
4
5
6
7
8
9
68 LEAD PLCC
10
44
43
42
41
40
39
38
37
36
35
TOP VIEW
11
12
13
14
15
16
17
18
20
19
22
21
24
23
26
25
28
27
P1.6
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0..
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Pl.5
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ID
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30
29
32
31
34
33
Figure 2A. UPI 452 58-Pin PLCC Pinout Diagram
9-7
231428-32
inter
UPI-4S2
UPI MICROCONTROLLER FAMILY
The UPI-452 joins the current members of the UP!
microcontroller family. UPI's are derivatives of the
MCSTM family of microcontrollers. Because of their
on-chip system bus interface, UPI's are designed to
be system bus "slaves", while their microcontroller
counterparts are intended as system bus "masters".
These UPI Microcontrollers are fully supported by
Intel's development tools (ICE, ASM and PLM).
Packaging
The 80C452/83C452 is available in either a 68-pin
PGA (Pin Grid Array) or 68-pin PLCC package.
UPIFamlly
(Slave
Configuration)
MCSFamlly
(Master
Configuration)
80C452
80C51
12 MHz
256
-
83C452
80C51
12MHz
256
8K
80C452-1
80C51
14 MHz
256
-
83C452-1
80C51
14 MHz
256
8K
Speed
RAM
(Bytes)
ROM
(Bytes)
UPI-4S2 PIN DESCRIPTIONS
Pin #
9/43
60
Type
I
I
XTAL1
38
I
XTAL2
Port 0
(ADO-AD7)
PO.O
.1
.2
.3
.4
.5
.6
PO.7
39
Symbol
Vss
Vee
0
1/0
8
10
11
12
13
14
15
16
Name and Function
Circuit Ground.
+ 5V power supply during normal and idle mode operation. It is also
the standby power pin for power down mode.
Input to the oscillator's high gain amplifier. A crystal or external
source can be used.
Output from the.high gain amplifier.
Port 0 is an 8-bit open drain bi-directional 1/0 port. Port 0 can sink
eight LS TTL inputs. It is also the multiplexed low-order address and
data local expansion bus during accesses to external memory.
UPI-452
UPI-4S2 PIN DESCRIPTIONS (Continued)
Symbol
Port 1
Pin #
Type
1/0
Name and Function
Port 1 is an B-bit quasi-bi-directionaII/O port. Port 1 can sink four
LS TTL inputs. The alternate functions can only be activated if the
corresponding bit latch in the port SFR contains a 1. Otherwise, the
port pin is stuck at O. Pins P1.5 and P1.6 are multiplexed with HLD
and HLDA respectively whose functions are defined as below:
Port Pin
Alternate Function
P1.5
HLD -Local bus hold
input! output signal
P1.6
HLDA -Local bus hold
acknowledge input
1/0
Port 2 is an B-bit quasi-bi-directionaII/O port. It also emits the highorder B bits of address when accessing local expansion bus
external memory. Port 2 can sink four LS TTL inputs.
1/0
Port 3 is an B-bit quasi-bi-directionaII/O port. It is also multiplexed
with the interrupt, timer, local serial channel, RDI and WRI
functions that are used by various options. The alternate functions
can only be activated if the corresponding bit latch in the port SFR
contains a 1. Otherwise, the port pin is stuck at O. Port 3 can sink
four LS TTL inputs. The alternate functions assigned to the pins of
Port 3 are as follows:
Alternate Function
Port Pin
P3.0
RxD
- Serial input port
P3.1
TxD
- Serial output port
P3.2
INTO
-Interrupt 0 Input
INT1
- Interrupt 1 Input
P3.3
TO
- Input to counter 0
P3.4
P3.5
T1
- Input to counter 1
- The write control signal latches the
P3.6
WRI
data from Port 0 outputs into the
External Data Memory on the
local bus.
P3.7
RDI
- The read control signal latches the
data from Port 0 outputs on the
local bus.
(AO-A~
(HLD, HLDA)
P1.0
.1
.2
.3
.4
.5
.6
P1.7
Port 2
(AB-A15)
P2.0
.1
.2
.3
.4
.5
.6
.7
Port 3
P3.0
.1
.2
.3
.4
.5
.6
P3.7
7
6
5
4
3
2
1
6B
29
2B
27
25
24
23
22
21
67
66
65
64
63
62
61
59
9-9
inter
UPI-4S2 '
UPI-4S2 PIN DESCRIPTIONS (Continued)
Pin #
Symbol
Port 4
P4.0
.1
.2
.3
.4
.5
.6
.7
RST
Type
I/O
30
32
33
34
35
36
37
20
I
18
0
19
0
EA
17
I
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CS
AO
A1
A2
58
57
56
55
54
53
52
51
44
40
41
42
I/O
READ
46
I
WRITE
47
I
DRQIN/
INTRQIN
49
0
DRQOUT/
INTRQOUT
48
0
ALE
PSEN
,
I
I
Name and Function
Port 4 is an·8-bitquasi-bi-directionall/O port. Port 4 can sink/
source four'TTL inputs.
A high level on this pin for two machine cycles while the oscillator is
running resets the device. An internal pulldown resistor permits
Power-on reset using only a capacitor connected to Vee.
This pin does not receive the power dqwn voltage as is the case for
HMOS MCS-51 family members. This function has been transferred
to the Vee pin.
Provides Address Latch Enable output used for latching the
address into external memory during normal operation. ALE can
sink/source eight LS TIL inputs.
The Program Store Enable output is a control signal that enables
the external Program Memory to the bus during normal fetch
operation. PSEN can sink/source eight LS TIL inputs.
When held at TIL high level, the UPI-452 executes instructions
from the internal ROM when the PC is less than 8192 (8K, 2000H).
When held at a TIL low level, the UPI-452 fetches all instructions
from external Program Memory.
Host Bus Interface is an 8-bit bi-directional bus. It is used to transfer
data and commands between the UPI-452 and the host processor.
This bus can sink/source eight LS TIL inputs.
This pin is the Chip Select of the UPI-452.
These three address lines are used to interface with the host
system. They define the UPI-452 operations. The interface is'
compatible with the Intel microprocessors and the MULTIBUS.
This pin is the read strobe from the host CPU. Activating this pin
causes the UPI-452 to place the contents of the Output FIFO (either
a command or data) or the Host Status/Control Special Function
Register on the Slave Data Bus.
This pin is the write strobe from the host. Activating this pin will
cause the value on the Slave Data Bus to be written into the register
specified by AO-A2.
This pin requests an input transfer from the host system whenever
the Input Channel requires data.
This output pin requests an output transfer whenever the Output
Channel requires service. If the external host to UPI"452 DMA is
enabled, and a Data Stream Command is at the Output FIFO,
DRQOUT is deactivated and INTRQ is activated (see 'GENERAL
PURPOSE DMA CHANNELS'section).
9-10
intJ
UPI-4S2
UPI-4S2 PIN DESCRIPTIONS (Continued)
Pin #
Type
INTRQ
50
0
This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.
DACK
45
I
This pin is the DMA acknowledge for the host bus interface Input
and Output Channels. When activated, a write command will cause
the data on the Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO). A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (+ 5V) in systems which do not
have a DMA controller (see Address Decoding).
Vee
26
I
+ 5V power supply during operation.
Symbol
Name and Function
scription of the UPI-452's core CPU functional
blocks including;
ARCHITECTURAL OVERVIEW
-
Introduction
Timers/Counters
-I/O Ports
- Interrupt timirig and control (other than FIFO and
DMA interrupts)
The UPI-452 slave microcontroller incorporates an
80C51 with double the program and data memory, a
slave interface which allows it to be connected directly to the host system bus as a peripheral, a FIFO
buffer module, a two channel DMA processor, and a
fifth I/O port (Figure 3). The UPI-452 retains all of
the 80C51 architecture, and is fully compatible with
the MCS-51 instruction set.
-
The Special Function Register (SFR) interface concept introduced in the MCS-51 family of microcontrollers has been expanded in the UPI-452. To the
20 Special Function Registers of the MCS-51, the
UPI-452 adds 34 more. These additional Special
Function Registers, like those of the MCS-51, provide access to the UPI-452 functional elements including the FIFO, DMA and added interrupt capabilities. Several of the 80C51 core Special Function
Registers have also been expanded to support added features of the UPI-452.
Serial Channel
-
Local Expansion Bus
-
Program/Data Memory structure
-
Power-Saving tylodes of Operation
-
CHMOS Features
-
Instruction Set
Figure 3 contains a conceptual block diagram of the
UPI-452. Figure 4 provides a functional block diagram.
FIFO Buffer Interface
A unique feature of the UPI-452 is the incorporation
of a 128 byte FIFO array at the host-slave interface.
The FIFO allows asynchronous bi-directional trans~
fers between the host CPU and the internal CPU.
This data sheet describes the unique features of the
UPI-452. Refer to the 80C51 data sheet for a de-
231426-7
Figure 3. UPI-452 Conceptual Block Diagram
9-11
intJ
UPI-452
ADDITIONAL FEATURES:
I
-SERIAL CHANNEL
I
-EXTERNAL INTERRUPTS :
-HLD/HLDACK
-LOCAL EXPANSION
BUS
-RD
-WR
--EXTERNAL
COUNTER INPUT
-EPROM PROGRAM
AND VERIFY
CONTROL
... ----------- ..
231428-8
Figure 4. UPI·452 Functional Block Diagram
nel Boundary Pointer (CBP) SFR. This register contains the number of address locations assigned to
the Input channel. The remaining address locations
are automatically assigned to the Output FIFO. The CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External Host Interface FIFO DMA Freeze Mode description). The CBP is initialized to 40H (64 bytes)
upon reset.
The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility. If the entire 128 byte FIFO is
allocated to the Input channel, a high performance
Host can transfer up to 128 bytes at one time, then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO. Various handshake signals allow the external Host to
operate independently and without frequent monitoring of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses. Three slave bus
interface handshake methods are supported by the
UPI-452: DMA, Interrupt and Polled.
The number in the Channel Boundary Pointer SFR is
actually -the first address location of the Output
FIFO. Writing to the CBP SFR reassigns the Input
and Output FIFO address space. Whenever the CBP
is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
theCBP SFR.
-
The FIFO is nine bits wide. The ninth bit acts as a
command/data flag ..Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs. DSCs are written to
the input FIFO by the Host via a unique external
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Function Register (SFR). When encountered by the host
or internal CPU a Data Stream Command can -be
used as an address vector to user defined service
routines. DSCs provide synchronization of data and
commands between the Host and internal CPU.
Ali of the FIFO space may be assigned to one channel. In such a situation the other channel's data path
consists of a single SFR (FIFO IN/COMMAND IN or
FIFO OUT/COMMAND OUT SFR) location.
CBP
Register
0
1
2
3
4
Input FIFO
Size
1
1
2
3
4
7B
7C
7D
7E
7F
123
124
125
128
128
•
FIFO PROGRAMMABLE FEATURES
Size of Input/Output Channels
The 128 bytes of FIFO space can be allocated between the Input and Output channels via the Chan9-12
•
Output FIFO
Size
128
128
126
125
124
.
5
4
3
1
1
.
UPI-452
of the three writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memory and the Special Function Register array. The Special Function Register array appears as a set of
unique dedicated memory addresses which may be
used as either the source or destination address of a
DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Registers for mode, source and destination addresses,
and byte count to be transferred. Each DMA channel
has four programmable modes:
FIFO Read/Write Pointers
These normally operate in auto-increment (and autorollover) mode, but can be reassigned by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External Host Interface FIFO DMA Freeze Mode description).
Threshold Register
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input
FIFO to generate a Host interrupt. The Output FIFO
Threshold SFR contains the number of bytes,. data
and/or DSC(s), that must be in the FIFO before an
interrupt is generated. The Threshold feature prevents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data. The
thresholds, therefore, allow the FIFO's operation to
be adjusted to the speed of the Host, optimizing the
overall interface performance.
-
Alternate Cycle Mode
-
Burst Mode
-
FIFO or Serial Channel Demand Mode
-
External Demand Mode
A complete description of each mode and DMA operation may be found in the section titled "General
Purpose DMA Channels".
FIFO/SLAVE INTERFACE
FUNCTIONAL DESCRIPTION
Immediate Commands
The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the
external Host and internal CPU called Immediate
Commands. As the name implies, an Immediate
Command is available to the receiving CPU immediately, via an interrupt, without being entered into the
FIFO as are Data Stream Commands. Like Data
Stream Commands, Immediate Commands are written either via a unique external address by the host
CPU, or via dedicated SFR by the internal CPU.
Overview
The FIFO is a 128 Byte RAM array with recirculating
pointers to manage the read and write accesses.
The FIFO consists of an Input and an Output channel. Access cycles to the FIFO by the internal CPU
and external Host are interleaved and appear to be
occurring concurrently to both the internal CPU and
external Host. Interleaving access cycles ensures
efficient use of this shared resource. The internal
CPU accesses the FIFO in the same way it would
access any of the Special Function Registers e.g.,
direct and register indirect addressing as well as arithmetric and logical instructions.
The DSC and/or Immediate Command interface
may be defined as either Interrupt or Polled under
user program control via the Interrupt Enable (IE),
Slave Control Register (SLCON), and Interrupt Enable Priority (IEP) Special Function Registers, for the
internal CPU and via the Host Control SFR for the
external Host CPU.
Input FIFO Channel
DMA
The UPI-452 contains a two channel internal DMA
controller which allows transfer of data between any .
The Input FIFO Channel provides for data transfer
from the external Host to the internal CPU (Figure 5).
The registers associaied with the Input Channel during normal operation are listed in Table 1'.
Table 1. Input FIFO Channel Registers'
1)
2)
3)
4)
5)
6)
Register Name
Description
Input Buffer Latch
FIFO INSFR
COMMAND IN SFR
Input FIFO Read Poil)ter SFR
Input FIFO Write Pointer SFR
Input FIFO Threshold SFR
Host CPU Write only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
'See "'FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode SFR characteristics descnptlon.
9-13
inter
UPI-452
EXTERNAL HOST
CPU
EXTERNAL
ADDRESS
HOST DATA
BUS
INPUT WRITE
POINTER (IWPR)
!::
In
THRESHOLD SFR
(ITHR)
INPUT FIFO
:J:
I-
Z
Z
INPUT READ
POINTER (IRPR)
INTERNAL
BUS
TO INTERRUPT
LOGIC
231428-9
Figure 5. Input FIFO Channel Functional Block Diagram
The host CPU writes data and Data Stream Com·
mands into the Input Buffer Latch on the rising edge
of the external WR signal. External addressing de·
termines whether the byte is a data byte or Data
Stream Command and the FIFO logic sets the ninth
bit of the FIFO accordingly as the byte is moved
from the Input Buffer Latch into the FIFO. A "1" in
the ninth bit indicates that the incoming byte is a
Data Stream Command. The internal CPU reads
data bytes via the FIFO IN SFR, and Data Stream
Commands via the COMMAND IN SFR.
The Input FIFO Channel addressing is controlled by
the Input FIFO Read and Write Pointer SFRs. These
SFRs are read only registers during normal operation. However, during FIFO DMA Freeze Mode (See
FIFO-External Host Interface FIFO DMA Freeze
Mode description), the internal CPU has write access to them. Any write to these registers in normal
mode will have no effect. The 'Input Write Pointer
SFR contains the address location to which datal
commands are written from the Input Buffer Latch.
The write pointer is automatically incremented after
each write and is reset to zero'if equal to the CBP,
as the Input FIFO operates as a circular buffer.
A Data Stream Commarid will generate an interrupt
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can
then be read via the COMMAND IN SFR. Data can
only be read via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR. Attempting
to read Data Stream Commands as data by address·
ing the FIFO IN SFR will result in "OFFH" being
read, and the Input FIFO Read Pointer will remain
intact (This prevents accidental misreading of Data
Stream Commands.) Attempting to read data as
Data Stream Commands will have the same consequence.
If a write is performed on an empty FIFO, the first
byte is also written into the FIFO IN or COMMAND
IN SFR. If the Host continues writing while the Input
FIFO is full, an external interrupt, if enabled, is sent
to the host to signal the overrun condition. The
writes are ignored by the FIFO control logic. Similarly, an internal CPU read of an empty FIFO will cause
an underrun error interrupt to be generated to the
internal CPU and a value of "OFFH" will be read by
the, internal CPU.
9-14
inter
UPI-4S2
number of bytes assigned to the Input FIFO (CBP)
minus the number of bytes programmed in the Input
FIFO Threshold SFR. With this feature the Host is
assured that it can write at least a threshold number
of bytes to the Input FIFO channel without worrying
about an overrun condition. Once the Request for
Service is generated it remains active until the Input
FIFO becomes full.
The Read Pointer SFR holds the address of the next
byte to be read from the Input FIFO. An Input FIFO
read operation post-increments the Input Read
Pointer SFR and loads a new data byte into the
FIFO IN SFR or a Data Stream Command into the
COMMAND IN SFR at the end of the read cycle.
An Input FIFO Request for Service (via DMA, Interrupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a "threshold" value
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Threshold SFR can be from 0 to (CBP-3). The Request for
Service Interrupt is generated only after the Input
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total
Output FIFO Channel
The Output FIFO Channel provides data transfer
from the UPI-452 internal CPU to the external Host
(Figure 6).
The registers associated with the Output Channel
during normal operation are listed in Table 2*.
231428-10
Figure 6. Output FIFO Channel Functional Block Diagram
Table 2. Output FIFO Channel Registers
1)
2)
3)
4)
5)
6)
Register Name
Description
Output Buffer Latch
FIFOOUTSFR
COMMAND OUT SFR
Output FIFO Read Pointer SFR
Output FIFO Write Pointer SFR
Output FIFO Threshold SFR
Host CPU Read only
Internal CPU Read and Write
Internal CPU Read and Write
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
'See "FIFO·EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode register characteristics description.
9-15
intJ
UPI·452
The UPI-452 internal CPU transfers data to the Output FIFO via the FIFO OUTSFR and cornmands via
the COMMAND. OUT SFR. If the byte is written to
the COMMAND OUT SFR, the ninth bit is automatically set (= 1) to indicate a Data Stream Command.
If the byte is written to the FIFO OUT SFR the ninth
bit is cleared (= 0). Thus the FIFO OUT and COMMAND OUT SFRs are the same but the address determines whether the byte entered in the FIFO is a
DSC or data byte.
2.) The second type of Request for Service is called
"Flush Mode" and occurs when the internal CPU
writes a Data Stream Command into the Output
FIFO. Its purpose is to ensure that a data block
entered into the Output FIFO, which is less than
the programmed threshold, will generate a Request for Service interrupt, if enabled, and be
read, or "Flushed" from the Output FIFO, by the
external host CPU regardless of the status of the
OTHR SFR.
The Output FIFO preloads a byte into .the Output
,Buffer Latch. When the Host Issues a RDI signal,
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the
Output Buffer Latch, aflag is set and an interrupt, if
enabled, is generated if the byte is a DSC (ninth bit
is set). The operation is carefully timed such that an
interrupt can be generated in time for it to be recognized by the Host before its next read instruction.
Internal CPU write and external Host read operations are interleaved at the FIFO so that they appear
to be occurring concurrently.
Immediate Commands
Immediate Commands provide direct communication between the external Host and UPI-452. Unlike
Data Stream Commands which are entered into the
FIFO, the Immediate Command is available to the·
receiving CPU directly, bypassing the FIFO. The Immediate Command can serve as a program vector
pointing into a jump table in the recipients software.
Immediate Command Interrupts are generated, if enabled, and a bit in the appropriate Status Register is
set when an Immediate Command is input or output.
A similar bit is provided to acknowledge when an
Immediate Command has been read and whether
the register is available to receive another command. The bits are reset when the Immediate Com"
mands are read. Two Special Function Registers are
dedicated to the Immediate Command interface. External addressing determines whether the Host is
accessing the Input FIFO or the Immediate Command IN (IMIN) SFR. The internal CPU writes Immediate Commands to the Immediate Command OUT
(IMOUT) SFR.
The Output FIFO read and write pointer operation is
the same as for the Input Channel. Writing to the
FIFO OUT or COMMAND OUT SFRs will increment
the Output Write Pointer SFR but reading from it will
leave the write pointer unchanged. A rollover of the
Output FIFO Write Pointer causes the pOinter to be
reset to the value in the Channel Boundary Pointer
(CBP) SFR.
If the external host attempts to read a Data Stream
Command as a data byte it will result in invalid data
(OFFH) being read. The DSC is not lost because the
invalid read does not increment the pointer. Similarly
attempting to read a data byte as a Data Stream
Command has the same result.
Both processors have the ability to enable or disable
Immediate Command Interrupts. By disabling the interrupt, the recipient of the Immediate Command
can poll the status SFR and read the Immediate
Command at its convenience. Immediate Com"
mands should only be written when the appropriate
Immediate Command SFR is empty (as indicated in
the appropriate status SFR:HSTAT ISST AT). Similarly, the Immediate Command SFR should only be
read when there is data in the Register.
A Request for Service is generated to the external
Host under the following two conditions:
1.) Whenever the internal CPU has written a threshold number of bytes or more into the Output FIFO
(threshold = (OTHR) + 1). The threshold number should be chosen such that the bus latency
time for the external. Host does not result in a
FIFO overrun error condition on the internal CPU
side. The threshold limit should be large enough
to make a bus request by the UPI-452 to the external host CPU worthwhile. Once a request for
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 2 to {(80H-CBP)-1l. The threshold
number can be programmed via the OTHR SFR.
The flowcharts in Figure 7a and 7b illustrate the
proper handshake mechanisms between the external Host and internal CPU when handling Immediate
Commands.
9-16
inter
UPI~452
SET
SET
Q
\V
,
...
oil
GENERATES INTERRUPT
TO INTE,RNAL CPU
GENERATES
INTERRU~T TO HOST
,
,
,,
)
)
SET
SET
Q
\V
,
'lit
lit
,
GENERATES
INTERRU~T TO HOST
_________________ 4
GENERATES INTERRUPT
TO INTE,RNAL CPU
,,
,,
231428-11
231428-12
Figure 7a. Handshake Mechanisms for Handling
Immediate Command IN Flowchart
Figure 7b. Handshake Mechanisms for Handling
Immediate Command OUT Flowchart
9-17
inter
UPI-452
HOST & SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers:
1) Mode Special Function Register (MODE)
2) Sla"e Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAT)
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit. Only the
Slave Control Register (SLCON) is bit addressable.
1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface. It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU.
The MODE SFR can be directly modified by the internal CPU through direct address instructions. It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command, either Immediate or DSC, to vector to that routine.
Symbolic
Physical
Address
Address
MODE
MD6
MD5
MD4
OF9H
(MSB)
Status On Reset
l'
MD7
MD6
o
(LSB) ,
o
o
l'
1*
1*
l'
(reserved)"
Request for Service to external CPU via;
1 = DMA (DRQIN/DRQOUT) request to external host when the Input or Output FIFO channel requests service
o=
Interrupt (INTRQIN/INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I/O Buffer Latch
MD5
Configure DRQIN/INTRQIN and DRQOUT /INTRQOUT to be either;
1 = Enable (Actively driven)
MD4
Configure INTRQ to be either;
o=
1
Disable (Tri-state)
= Enable (Actively driven)
o=
MD3
Disable (Tri-state)
(reserved)"
MD2
(reserved)"
MD1
(reserved)"
MDO
(reserved)'*
2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface. All interrupts are to the internal
CPU.
9-18
intJ
UPI-452
Physical
Address
Symbolic
Address
SLCON
IFI
OFI
ICII
FRZ
ICOI
IFRS
(MSB)
Status On Reset:
0
IFI
0
OFRS
OEBH
(LSB)
0
0
0
l'
0
0
Enable Input FIFO Interrupt (due to Underrun Error Condition, Data Stream Command or Request
Service)
OFI
ICII
ICOI
FRZ
SC2
1 = Enable
0= Disable
Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service)
1 = Enable
0= Disable
Note: If the DMA is configured to service a FIFO demand, then the Request for Service Interrupt is
not generated.
Generate Interrupt when a command is written to the Immediate Command in Register
1 = Enable
0= Disable
Generate Interrupt when Immediate Command Out Register is Available
1 = Enable
0= Disable
Enable FIFO DMA Freeze Mode
1 = Normal operation
o = FIFO DMA Freeze Mode
(reserved) ,.
IFRS
Input FIFO Channel Request for Service
1 = Request when Input FIFO not empty
OFRS
Output FIFO Channel Request for Service
o=
1
Request when Input FIFO full
= Request when Output FIFO not full
o=
Channel Request when Output FIFO empty
NOTES:
*A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
'*'reserved'-these locations are reserved for future use by Intel Corporation.
3) Slave Status SFR (SST AT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface. It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action.
Symbolic
Address
Physical
Address
SSTAT
OE9H
o
o
o
(MSB)
(LSB)
9-19
UPI-4S2
SST?
Output FIFO Overrun Error Condition
1 = No Error
o=
SST6
Error (latched until Slave Status SFR is read)
Immediate Command Out Register Status
1 = Full (i.e. Host CPU has not read previous Immediate Command Out sent by internal CPU)
0= Available
SST5
FIFO DMA Freeze Mode Status
1
=
Normal Operation
o=
SST4
FIFO DMA Freeze Mode in Progress
Output FIFO Request for Service Flag
1 = Output FIFO does not request service
o=
SST3
o=
SST2
Immediate Command received from host CPU
Data Stream Command/Data at Input FIFO Flag
1 = Data (not DSC)
o=
SSTO
Underrun Error (latched until Slave Status SFR is read)
Immediate Command In SFR Status
1 = Empty
o=
SST1
Output FIFO requests service
Input FIFO Underrun Error Condition Flag
1 = No Underrun Error
DSC (at COMMAND IN SFR)
Input FIFO Request For Service Flag
1 = Input FIFO Does Not Request Service
o=
Input FIFO Request for Service
EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs:
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands. The protocol for implementing this is entirely determined by the user.
1) Host Control SFR (HCON)
By writing to the Host Control SFR, the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452.
Symbolic
Address
HCON
Physical
Address
HC?
HC6
HC5
HC4
HC3
HC1
(MSB)
Status On Reset:
0
0
OE?H
(LSB)
0
0
0
9-20
O'
0
O'
inter
UPI·452
HC?
Enable Output FIFO Interrupt due to Underrun Error Condition, Data Stream Command or Service
Request
1 = Enable
0= Disable
HC6
Enable Input FIFO Interrupt due to Overrun Error Condition, or Service Request
1 = Enable
0= Disable
HC5
Enable the generation of the Interrupt due to Immediate Command Out being present
= Enable
0= Disable
Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate
Command byte
1 = Enable
0= Disable
Reset UPI-452
1 = Software RESET
o = Normal Operation
(reserved)"
Select between INTRQ and INTRQINIINTRQOUT as Request for Service interrupt signal when DMA is
disabled
1 = INTRQ
o = INTRQIN or INTRQOUT
(reserved)"
1
HC4
HC3
HC2
HC1
HCO
NOTES:
• A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.
2) Host Status SFR (HST AT)
The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the
source of an external interrupt during pOlling. Like the Slave Status SFR, the Host Status SFR reflects the
current status of the FIFO-external host interface.
Symbolic
Address
Physical
Address
HSTAT
OE6H
1/0'
(MSB)
(LSB)
9-21
intJ
UPI-4S2
HST7 Output FIFO Underrun Error Condition
1 = No Underrun Error
o = Underrun Error (latched until Host
Status Register is read)
FIFO MODULE - EXTERNAL HOST
INTERFACE
Overview
HST6 Immediate Command Out SFR Status
1 = Empty
o = .immediate Command Present
The FIFO-external Host interface supports high
speed asynchronous bi-directional 8-bit data transfers. The host interface is fully compatible with Intel
microprocessor local busses and with MULTIBUS.
The FIFO has two specialized DMA request pins for
Input and Output FIFO channel DMA requests.
These are multiplexed to provide a dedicated Request for Service interrupt (DRQIN/INTRQIN,
DRQOUT /INTRQOUT).
HST5 Data Stream Command/Data at Output
FIFO Status
1 = Data (not DSC)
o = DSC (present at Output FIFO COMMAND OUT SFR)
(Note: Only if HST4 = 0, if HST4 = 1 then undetermined)
The external Host can program, under user defined
protocol, thresholds into the FIFO Input and Output
Threshold SFRs which determine when the FIFO
Request for Service interrupt is generated to the
Host CPU. The FIFO module external Host interface
is configured by the internal CPU via the MODE
SFR. "The external Host can enable and disable
Host interface interrupts via the Host Control SFR."
Data Stream Commands in the Input FIFO channel
allow the Host to influence the processing of data
blocks and are sent with the data flow to maintain
synchronization. Data Stream Commands in the
Output FIFO Channel allow the internal CPU to perform the same function, and also to set the Output
FIFO Request Service status logic to the host CPU
regardless of the programmed value in the Threshold SFR .
HST4 Output FIFO Request for Service Status
1 = No Request for Service
o = Output FIFO Request for Service due to:
a. Output FIFO containing the threshold
number of bytes or more
b. Internal CPU sending a block of data terminated by a DSC (DSC Flush Mode)
HST3 Input FIFO Overrun Erro~ Condition
1 = No Overrun Error .
o = Overrun Error (latched until Host Status
Register is read)
HST2 Immediate Command In SFR Status
1 = Full (i.e. Internal CPU has not read previous Immediate Command sent by Host)
0= Empty
• Reset value;
'1' -
Slave Interface Address Decoding
if read by the external Host
The UPI-452 determines the desired Host function
through address decoding. The lower three bits of
the address as well as the READ, WRITE, Chip Select (CS) and DMA Acknowledge (DACK) are used
for decoding. Table 3 shows the pin states and the
Read or Write operations associated with each configuration.
'0' - if read by internal CPU (reads shadow
latch - see FIFO DMA Freeze Mode description)
HST1
FIFO DMA Freeze Mode Status
1 = Freeze Mode in progress.
(In Freeze Mode, the bits of the Host Status
SFR are forced to a '1' initially to prevent the
external Host from attempting to access the
FIFO. The definition of the Host Status SFR
bits during FIFO DMA Freeze Mode can be
found in FIFO DMA Freeze Mode description)
o = Normal Operation
Interrupts to the Host
The UPI-452 interrupts the external Host via the
INTRQ pin. In addition, the DRQIN and DRQOUT
pins can be multiplexed as interrupt request lines,
INTRQIN and INTRQOUT respectively, when DMA
is disabled. This provides two special FIFO "Request for Service" interrupts.
HSTO Input FIFO Request Service Status
1 = Input FIFO does not request service
o = Input FIFO request service due to the
Input FIFO containing enough space for the
host to write the threshold number of bytes
or more
There are eight FIFO-related interrupt sources; two
from The Input FIFO; three from The Output FIFO;
one from the Immediate Command Out SFR; one
from the Immediate Command IN SFR; and one due
to FIFO DMA Freeze Mode.
INPUT FIFO: The Input FIFO interrupt is generated
whenever:
a. The Input FIFO contains space for a threshold
number of bytes.
9-22
inter
UPI-4S2
Table 3. UPI-452 Address Decoding
DACK CS A2 A1 AD
Write
Read
1
1
X
X
X No Operation
1
D 0
0
0
No Operation
Data or DMA from Output FIFO Channel
Data or DMA to Input FIFO Channel
1
0
0
0
1
Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel
1
0
0
1
0
Host Status SFR Read
Reserved
1
0
0
1
1
Host Control SFR Read
Host Control SFR Write
1
0
1
0
0
Immediate Command SFR Read
Immediate Command to SFR Write
1
0
1
1
X Reserved
0
X
X
X
X DMA Data from Output FIFO Channel
DMA Data to Input FIFO Channel
1
0
1
0
1
Reserved
Reserved
Reserved
NOTES:
1. Attempting to read a DSC as a data byte will result in invalid data being read. The read pointers are not incremented so
that the DSC is not lost. Attempting to read a data byte as a DSC has the same result.
2. If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MDS) in the MODE SFR. Care should be taken when using DACK. For proper operation, DACK must be driven
high (+ 5V) when not using DMA.
b. When an Input FIFO overrun error condition exists. The appropriate bits in the Host Status SFR
are set and the interrupt is generated only if enabled.
b. An Immediate Command IN interrupt is generated, if enabled, to the Host when the internal CPU
has read a byte from the Immediate Command IN
(IMIN) SFR. The read operation clears the Host
Status SFR Immediate Command IN Status bit
(HSTAT HST2) indicating that the Immediate
Command IN SFR is empty. The corresponding
Slave Status (SSTAT) SFR bit is also set to indicate an empty status. Setting the Slave Status
SFR bit generates a FIFO-Slave Interface interrupt, if enabled, to the internal CPU. (See Figure
7a, Immediate Command IN Flowchart.)
OUTPUT FIFO: The Output FIFO Request for Service Interrupt operates in a similar manner as the Input FIFO interrupt:
a. When the FIFO contains the threshold number of
bytes or·more.
b. Output FIFO error condition interrupts are generated when the Output FIFO is underrun.
c. Data Stream Command present in the Output
Buffer Latch.
NOTE:
Immediate Command IN and OUT interrupts are actually specific Request For Service interrupts to the
Host.
A Data Stream Command interrupt is used to halt
normal processing, using the command as a vector
to a service routine. When DMA is disabled, the user
may program (through HC1) INTRQ to include FIFO
Request for Service Interrupts or use INTRQIN and
INTRQOUT as Request for Service Interrupts.
FIFO DMA FREEZE MODE: When the internal CPU
invokes FIFO DMA Freeze Mode, for example at reset or to reconfigure the FIFO interface, INTRQ is
activated. The INTRQ can only be deactivated by
the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
is disabled by the internal CPU).
IMMEDIATE COMMAND INTERRUPTS:
a. An Immediate Command Out Interrupt is generated, if enabled, to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared,
when the internal CPU writes to the Immediate
Command OUT (IMOUT) SFR. When the Host
reads the Immediate Command OUT (IMOUT)
SFR the corresponding bit in the Host Status
(HSTAT) SFR is set. This causes the Slave Status
Immediate Command OUT Status bit (SSTAT
SST6) to be cleared indicating that the Immediate
Command OUT (IMOUT) SFR is empty. If enabled, a FIFO-Slave Interface will also be generated to the internal CPU. (See Figure 7b, Immediate Command OUT Flowchart.)
Once an interrupt is generated, INTRQ will remain
high until no interrupt generating condition exists.
For a FIFO underrun/overrun error interrupt, the interrupt condition is deactivated by the external Host
reading. the Host Status SFR. An interrupt is serviced by reading the Host Status SFR to determine
the source of the interrupt and vectoring the appropriate service routine.
9-23
infef
UPI-452
nation via the DMAO/DMA 1 Source Address or Destination Address Special Function Registers. The
FIFO module manages the transfer of data between
the external host and FIFO SFRs.
DMA Requests to the Host
The UPI-4S2 generates two DMA requests, DRQIN
and DRQOUT, to facilitate data transfer between the
Host and the Input and Output FIFO channels. A
DMA acknowledge, DACK, is used as a chip select
and initiates a data transfer. The external READ and
WRITE signals select the Input and Output FIFO respectively. The CS and address lines can also be
used as a DMA acknowledge for processors with
onboard DMA controllers which do not generate a
DACK signal.
Internal CPU Access to FIFO Via
Software Instructions
The internal CPU has access to the Input and Output FIFOs via the FIFO IN/COMMAND IN and FIFO
OUT/COMMAND OUT SFRs which reside in the
Special Function Register Array. At the end of every
instruction that involves a read of the FIFO IN/COMMAND IN SFR, the SFR is written over by a new
byte from the Input FIFO channel when available. At
the end of every instruction that involves a write to
the FIFO OUT/COMMAND OUT SFR, the new byte
is written into the Output FIFO channel and the write
pointer is incremented after the write operation (post
incremented).
The internal CPU can configure the UPI-4S2 to request service from the external host via DMA or interrupts by programming Mode SFR MD6 bit. In addition the external Host enables DMA requests
through bits 6 and 7 of the Host Control SFR. When
a DMA request is invoked the humber of bytes transferred to the Input FIFO is the total number of bytes
in the Input FIFO (as determined by the CBP SFR)
minus the value programmed in the Input FIFO
Threshold SFR. The DMA request line is activated
only when the Input FIFO has a threshold number of
bytes that can be transferred.
The internal CPU reads the Input FIFO by using the
FIFO IN/COMMAND IN SFR as the source register
in an instruction. Those instructions which read the
Input FIFO are listed below:
The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a
less than threshold size block of data (Flush Mode)
or when the Output FIFO threshold is reached. The
request remains active until the Input FIFO becomes
full or the Output FIFO becomes empty. If a DSC is
encountered during an Output FIFO DMA transfer,
the DMA request is dropped until the DSC is read.
The DMA request will be reactivated after the DSC is
read and remains active until the Output FIFO becomes empty or another DSC is encountered.
ADD A,FIFO IN/COMMAND IN
ADDC A,FIFO IN/COMMAND IN
PUSH FIFO IN/COMMAND IN
ANL A,FIFO IN/COMMAND IN
ORL A,FIFO IN/COMMAND IN
XRL A,FIFO IN/COMMAND IN
CJNE A,FIFO IN/COMMAND IN, rei
SUBB A,FIFO IN/COMMAND IN
MOV direct,FIFO IN/COMMAND IN
MOV @Ri,FIFO IN/COMMAND. IN
MOV Rn,FIFO IN/COMMAND IN
MOV A,FIFO IN/COMMAND IN
FIFO MODULE - INTERNAL CPU
INTERFACE
After each access to these registers, they are overwritten by a new byte from the FIFO.
Overview
The Input and Output FIFOs are accessed by. the
internal CPU through direct addressing of the FIFO
IN/COMMAND IN and FIFO OUT/COMMAND OUT
Special Function Registers. All of the BOCS1 instructions involving direct addressing may be used to access the FIFO's SFRs. The FIFO IN, COMMAND IN
and Immediate Command In SFRs are actually read
only registers, and their Output counterparts are
write only. Internal DMA transfers data between Internal memory, External Memory and the Special
Function Registers. The Special Function Registers
appear as another group of dedicated memory addresses and are programmed as the source or desti-
NOTE:
Instructions which use the FIFO IN or COMMAND
IN SFR as both a source and destination register
will have the data destroyed as the next data byte
is rewritten into the FIFO IN register at the end of
the instruction. These instructions are not supported by the UPI-4S2 FIFO. Data can only be read
through the FIFO IN SFR and DSCs through the
COMMAND IN SFR. Data read through the COMMAND IN SFR will be read as OFFH, and DSCs
read through the FIFO IN SFR will be read as
OFFH. The Immediate Command in SFR is read
with the same instructions as the FIFO IN and
COMMAND IN SFRs.
9-24
inter
UPI-4S2
The FIFO IN, COMMAND IN and Immediate Command In SFRs are read only registers. Any write operation performed on these registers will be ignored
and the FIFO pointers will remain intact.
dress Register (DAR). (Note: Since the FIFO IN SFR
is a read only register, the DMA transfer will be ignored if it is used as a DMA DAR. This is also true if
the FIFO OUT SFR is used as a DMA SAR.)
The internal CPU uses the FIFO OUT SFR to write
to the Output FIFO and any instruction which uses
the FIFO OUT or COMMAND OUT SFR as a destination will invoke a FIFO write. DSCs are differentiated from data by writing to the COMMAND OUT
SFR. In the FIFO, Data Stream Commands have the
ninth bit associated with the command byte set to
"1 ". The instructions used to write to the Output
FIFO are listed below:
Each DMA channel is software programmable to operate in either Block Mode or Demand Mode. In the
Block Mode, DMA transfers can be further programmed to take place in Burst Mode or Alternate
Cycle mode. In Burst Mode, the processor halts its
execution and dedicates its resources to the DMA
transfer. In Alternate Cycle Mode, DMA cycles and
instruction cycles occur alternately.
GENERAL PURPOSE DMA CHANNELS
In Demand Mode, a DMA transfer occurs only when
it is demanded. Demands can be accepted from an
external device (through External Interrupt pins,
EXTO/EXT1) or from either the Serial Channel or
FIFO flags. In this way, a DMA transfer can be synchronized to an external device, the FIFO or the Serial Port. If the External Interrupt is configured in
Edge Mode, a single by1e transfer occurs per transition. The external interrupt itself will occur if enabled. If the External Interrupt is configured in Level
Mode, DMA transfers continue until the External Interrupt request goes inactive or the by1e count becomes zero. The following flags activate Demand
Mode transfers of one byte to/from the FIFO or Serial Channel:
RI - Serial Channel Receiver Buffer Full
TI - Serial Channel Transmitter Buffer Empty
Overview
Architecture
There are two identical General Purpose DMA Channels on the UPI-452 which allow high speed data
transfer from one writeable memory space to another. As many as 64K by1es can be transferred in a
single DMA operation. The following memory
spaces can be used with DMA channels:
• Internal Data Memory
• External Data Memory
• Special Function Registers
There are three 16 bit and one 8 bit Special Function
Registers associated with each DMA channel.
• The 16 bit Source Address SFR (SAR) points to
. the source by1e.
MOV
MOV
MOV
POP
MOV
MOV
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
OUT/COMMOUT, A
OUT/COMMOUT, direct
OUT/COMMOUT, Rn
OUT/COMMOUT
OUT/COMMOUT, #data
OUT /COMMOUNT, @Ri
NOTE:
Instructions which use the FIFO OUT/COMMAND
OUT SFRs as both a source and destination register cause invalid data to be written into the Output
FIFO. These instructions are not supported by the
UPI-452 FIFO.
• The 16 bit Destination Address SFR (DAR) points
to the destination.
• The 16 bit Byte Count SFR (BCR) contains the
number of bytes to be transferred and is decremented when a by1e transfer is accomplished.
• The DMA Control SFR (DCON) is eight bits wide
and specifies the source memory space, destination memory space and the mode of operation.
The Special Function Register array appears as a
limited group of dedicated memory addresses. The
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the
source or destination address. The Special Function
Registers which may be used in DMA transfers are
listed in Table 4. Table 4 also shows whether the
SFR may be used as Source or Destination only, or
both.
In Auto Increment mode, the Source Address and/
or Destination Address is incremented when a by1e
is transferred. When a DMA transfer is complete
(SCR = 0), the DONE bit is set and a maskable
interrupt is generated. The GO bit must be set to
start any DMA transfer (also, the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freeze
Mode). The two DMA channels are designated as
DMAO and DMA 1, and their corresponding registers
are suffixed by 0 or 1; e.g. SARO, DAR1, etc.
The FIFO can be accessed during DMA by using the
FIFO IN SFR as the DMA Source Address Register
(SAR) or the FIFO OUT SFR as the Destination Ad9-25
UPI-4S2
Table 4. DMA Accessible Special Function Registers
SFR
Symbol
Accumulator
B Register
FIFO IN
COMMAND IN
FIFO OUT
COMMAND OUT
Serial Data Buffer
Port 0
Port 1
Port 2
Port 3
Port 4
AlACC
B
FIN
CIN
FOUT
COUT
SBUF
PO
P1
P2
P3
P4
Address
Source
Only
Destination
Only
Either
"-
Y
Y
OEOH
OFOH
OEEH
OEFH
·OFEH
OFFH
099H
080H
090H
OAOH
OBOH
OCOH
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
DMA Special Function Registers
DMA Control SFR: DCONO, DCON1
Symbolic
Address
Physical
Address
DCONO
092H
DCON1
093H
Reset Status: DCONO and DCON1 = OOH
Bit Definition:
DAS
IDA
0
0
1
1
0
1
0
1
SAS
ISA
0
0
1
1
0
1
0
1
OM
TM
0
0
1
1
0
1
0
1
Destination Address Space
External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory
Source Address Space
. External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory
DMA Transfer Mode
Alternate-Cycle Transfer Mode
Burst Transfer Mode
FIFO or Serial Channel Demand Mode
External Demand Mode
9-26
infef
DONE
UPI-452
DMA transfer Flag:
o
service request is generated. DMA transfer cycles
are alternated with instruction execution cycles.
DMA transfers are terminated as in FIFO Demand
Mode.
DMA transfer is not completed.
DMA transfer is complete.
NOTE:
This flag is set when contents of the Byte Count
SFR decrements to zero. It is reset automatically
when the DMA vectors to its interrupt routine.
GO
Enable DMA Transfer:
o
Output Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Output FIFO
requests service. DMA transfer cycles are alternated
with instruction execution cycles. DMA transfers are
terminated as in FIFO Demand Mode.
Disable DMA transfer (in all modes).
Enable DMA transfer. If the DMA is in
the Block mode, start DMA transfer if
possible. If it is in the Demand mode,
enable the channel and wait for a demand.
The FIFO logic resets the interrupt flag after transferring the byte, so the interrupt is never generated.
Once the DMA is programmed to service the FIFO,
the request for service interrupt for the FIFO is inhibited until the DMA is done (BCR = 0).
NOTE:
The GO bit is reset when the BCR decrements to
zero.
2. BURST MODE
In BURST mode the DMA is initiated by setting the
GO bit in the DCON SFR. The DMA operation continues until BCR decrements to zero (zero byte
count), then an interrupt is generated (if enabled).
No interrupts are recognized during this DMA operation once it has started.
DMA Transfer Modes
The following four modes of DMA operation are possible in the UPI-452.
1. ALTERNATE-CYCLE MODE
General
Input Channel
Alternate cycle mode is useful when CPU processing must occur during the DMA transfers. In this
mode, a DMA cycle and an instruction cycle occur
alternately. The interrupt request is generated (if enabled) at the end of the process, i.e. when BCR decrements to zero. The transfer is initiated by setting
the GO bit in the DCON SFR.
The FIFO Input Channel can be used in burst mode
by specifying the FIFO IN SFR as the DMA Source
Address. DMA transfers begin when the GO bit in
the DMA Control SFR is set. The number of bytes to
be transferred must be specified in the Byte Count
SFR (BCR) and auto-incrementing of the SAR must
be disabled. Once the GO bit is set nothing can interrupt the transfer of data until the BCR is zero. In
this mode, a Data Stream Command encountered in
the FIFO will be held in the COMMAND IN SFR with
the pointers frozen, and invalid data (FFH) will be
read through the FIFO IN SFR. If the input FIFO
becomes empty during the block transfer, an OFFH
will be read until BCR decrements to zero.
Alternate-Cycle FIFO Demand Mode
Alternate cycle demand mode is useful for FIFO
transfers of a less urgent nature. As mentioned before, CPU instruction cycles are interleaved with
DMA transfer cycles, allowing true parallel processing.
This mode differs from FIFO Demand Mode in that
CPU instruction cycles must be interleaved with
DMA transfers, even if the FIFO is demanding DMA.
In FIFO Demand Mode, CPU cycles would never occur if the FIFO demand was present.
Output Channel
The Output FIFO Channel can be used in burst
mode by specifying the FIFO OUT or COMMAND
OUT SFR as the DMA Destination Address. DMA
transfers begin when the GO bit is set. This mode
can be used to send a block of data or a block of
Data Stream Commands. If the FIFO becomes full
during the block transfer, the remaining data will be
lost.
Input Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Input FIFO
9-27
inter
UPI-4S2
NOTE:
All interrupts including FIFO interrupts are not recognized in Burst Mode. Burst Mode. transfers
should be used to service the FIFO only when the
user is certain that no Data Stream Commands are
in the block to be transferred (Input FIFO) and that
the FIFO contains enough space to store the block
to be transferred. In all other cases Alternate Cycle
or'Demand Mode should be used.
is not full or empty. DMA transfers begin when the
Aequest For Service Flag is activated by the FIFO
logic and continue as long as the flag is active. The
Flag remains active until one of the following occurs:
1) The FIFO becomes full
2) BCA = 0 (this generates a DMA interrupt and
.
sets the DONE bit),
As in Alternate Cycle FIFO Demand Mode, the FIFO
logic resets the interrupt flag after transferring the
byte, so the interrupt is never generated.
3. FIFO AND SERIAL CHANNEL DEMAND
MODES
After the GO bit is set, the DMA is activated if one of
the following condi.tions takes place:
<
.SAA(0/1) = FIFO IN and HIFAS flag is set
DAA(0/1) == FIFO OUT and HOFAS flag is set
NOTES:
1. If the output FIF,O is configured as a one byte
buffer and the user program consists of two-cycle
instructions only, then Alternate-Cycle Mode should
be used.
2. In non-auto increment mode for internal to external, or external to internal transfers, the lower 8 bits
of the external address should not correspond to
the FIFO or Serial Port address.
The HIFAS and HOFAS signals are internal flags
which are not accessible by software. These flags
are similar to the SSTO and SST4 flags in the Slave
Status Aegister except that they are of the opposite
polarity and once set they are not cleared until the
Input FIFO becomes empty (HIFAS) or the Output
FIFO becomes full (HOFAS).
.
FIFO Demand Mode
Although any DMA mode is possible using the FIFO
buffer, only FIFO Demand and Alternate Cycle FIFO
Demand Modes are recommended. FIFO Demand
Mode DMA transfers using the input FIFO Channel
are set-up by setting the GO bit and specifying the
FIFO IN register as the DMA Source Address Aegister. The BCA should be set to the maximum number
of expected transfers. The user must also program
bit 1 of the Slave Control Aegister (SC1) to determine whether the Slave Status (SSTAT) SFA FIFO.
Aequest For Service Flag will be activated when the
FIFO becomes not empty or full. Once the Aequest
For Service Flag is activated by the FIFO, the DMA
transfer begins, and continues until the request flag
is .deactivated. While the request is active, .nothing
can interrupt the DMA (i.e. it behaves like burst
mode). The DMA Aequest is held active until one of
the following occurs:
Serial Channel Demand Mode
Serial Channel Demand Mode is the logical choice
when using the Serial Port. The DMAs can be activated by one of the Serial Channel Flags. Aeceiver
interrupt (AI) or Transmitter Interrupt (TI).
SAA(0/1) = SBUF and AI flag is set
DAA(0/1) = SBUF and TI flag is set
..
NOTE:..
.
TI flag must beset by software to initiate the first
transfer.
When the DMA transfer begins, only one byte is
transferred at a time. The serial port hardware automatically resets the flag after completion. of the
transfer, so an interrupt will not be generated unless
DMA servicing is held off due to the DMA being
done (BCA= 0) or when the Hold/Hold Acknowledge logic is used and the DMA does not own the
bus. In this case a Serial Port interrupt may be generated if enabled because of the status of the AI or
TI flags.
1) The FIFO becomes empty.
2) A Data Stream Command is encountered (this
generates a FIFO interrupt and DMA operation
resumes after the Data Stream Command is
read).
3) BCA = 0 (this generates a DMA interrupt and
sets the DONE bit).
In FIFO demand mode, Alternate cycle FIFO demand mode or Serial Port demand mode only one of
the following registers (SBUF, FIN or FOUT) should
be used as either the SAA or DAA register~ to pre~
vent undesired transfers. For example ·if SAAO =
FIN and DAAO = SBUF in demand mode, the DMA
transfer will start if either the HIFAS or TI flags are
set.
DMA transfers to the Output FIFO Channel are similar. The FIFO OUT or COMMAND OUT SFA is the
DMA Destination Address SFA and a transfer Is
started by setting the GO bit. The user programs bit
o of the Slave· Control SFA (SCO) to determine
whether a demand occurs when the Output FIFO
9-28
UPI-4S2
ARBITER MODE: In this mode, the UPI·452 is the
bus master. It configures port pin P1.5 as HLD input
and pin P1.6.as HLDA output. When a device asserts the HLD signal to use the local bus, the UPI452 asserts the HLDA signal after current instruction
execution is complete. If the UPI-452 needs an external access via a DMA channel, it waits until the
requester releases the bus, HLD goes inactive.
4. EXTERNAL DEMAND MODE
The DMA can be initiated by an external device via
External interrupt 0 and 1 (INTO/INT1) pins. The
INTO pin demands DMAO (Channel 0) and INT1 demands DMA 1 (Channel 1). If the interrupts are configured in edge mode, a single byte transfer is accomplished for every request. Interrupts also result
(INTO and INT1) after every byte transfer (if en·
abled). If the interrupts are configured in level mode,
the DMA transfer continues until the request goes
inactive or BCR = O. In either case, a DMA interrupt
is generated (if enabled) when BCR = o. The GO bit
must be set for the transfer to begin.
DISABLE MODE: When external program memory is
accessed by an instruction or by program counter
overflow beyond the internal ROM address or exter·
nal data memory is accessed by MOVX instructions,
it is a local memory access and the HLD/HLDA logic
is not initiated. When a DMA channel attempts data
transfer to/from the external data memory, the
HLD/HLDA logic is initiated as described below.
DMA transfers from the internal memory space to
the internal memory space does not initiate the
HLD/HLDA logic.
EXTERNAL MEMORY DMA
When transferring data to or from external memory
via DMA, the HOLD (HLD) and HOLD·ACKNOWLEDGE (HLDA) signals are used for handshaking.
The HOLD and HOLD·ACKNOWLEDGE are active
low signals which arbitrate control of the local bus.
The UPI·452 can be used in a system where multimasters are connected to a single parallel Address/
Data bus. The HLD/HLDA signals are used to share
resources (memory, peripherals, etc.) among all the
processors on the local bus. The UPI·452 can be
configured in any of three different External Memory
Modes controlled by bits 5 and 6 (REQ & ARB) in
the PCON SFR (Table 5). Each mode is described
below:
The balance of the PCON SFR bits are described in
the "80C51 Register Description: Power Control
SFR" section below.
Latency
When the GO bit is set, the UPI-452 finishes the
current instruction before starting the DMA operation. Thus the maximum latency is 3.5 microseconds
(at 14 MHz).
REQUESTER MODE: In this mode, the UPI-452 is
not the bus master, but must request the bus from
another device. The UPI-452 configures port pin
P1.5 as a HLD output and pin P1.6 as a HLDA input.
The UPI-452 issues a HLD signal when it needs external access for a DMA channel. It uses the local
bus after receiving the HLDA signal from the bus
master, and will not release the bus until its DMA
operation is complete.
DMA Interrupt Vectors
Each DMA channel has a unique vectored interrupt
associated with it. There are two vectored interrupts
associated with the two DMA channels. The DMA
interrupts are enabled and priorities set via the Interrupt Enable and Priority SFR (see "Interrupts" sec·
tion). The interrupt priority scheme is similar to the
scheme in 80C51.
Table 5. DMA MODE CONTROL - PCON SFR
Physical
Address
Symbolic
Address
-*
PCON
ARB
REQ
-*
-*
(MSB)
'Defined as per MLS-51 Data Sheet
Reset Status: OOH
-*
-*
-*
(LSB)
Definition·
ARB
REO
0
0
1
1
0
1
0
1
HLD/HLDA logic is disabled.
The UPI-452 is in the Requester Mode.
The UPI-452 is in the Arbiter Mode.
Invalid
9-29
87H
intJ
UPI-4S2
When a DMA operation is complete (BCR decrements to zero), the DONE flag in the respective
DCON (DCONO or DCON1) SFR is set. If the DMA
interrupt is enabled, the DONE flag is reset automatically upon vectoring to the interrupt routine.
If the UPI-4S2 (as a Requester) asserts a HLD signal
to request a DMA transfer (see "External Memory
DMA")and its other DMA Channel requests a transfer before the HLDA signal is received, the channel
having higher priority is activated first. A Burst Mode
transfer on channel 0 can not be interrupted since
DMAO has the highest priority. A Demand Mode
transfer on channel 0 is the only type of activity that
can interrupt a block transfer on DMA 1.
Interrupts When DMA is Active
If a Burst Mode DMA transfer is in progress, the interrupts are not serviced until the DMA transfer is
complete. This is also true for level activated External Demand DMA transfers. During Alternate Cycle
DMA transfers, however, the interrupts are serViced
at the end of the DMA cycle. After that, DMA cycles
and instruction execution cycles occur alternately. In
the case of edge activated External Demand Mode
DMA transfers, the interrupt is serviced at the end of
DMA transfer of that single byte.
If, while executing a DMA transfer, the Arbiter receives a HLD signal, and then before it can acknowledge, its other DMA Channel requests a transfer, it
then completes the second DMA transfer before
sending the HLDA signal to release the bus to the
HLD request.
DMA transfers may be held off under the following
conditions:
1. A write to any of the DMA registers inhibits the
DMA for one instruction cycle:
DMA Arbitration
Only one of the two DMA channels is active at a
time, except when both are configured in the Alternate Cycle mode. In this case, the DMA cycles and
Instruction Execution cycles occur in the following
order:
1. DMA Cycle O.
2. Instruction execution.
3. DMA Cycle 1.
4. Instruction execution.
DMAO has priority over DMA 1 during simultaneous
activation of the two DMA channels. If one DMA
channel is active, the other DMA channel, if activated, waits until the first one is complete.
NOTE:
An instruction cycle may be executed in 1, 2 or 4
machine cycles dependent on the instruction being
.executed. DMA transfers are only executed after
the completion of an instruction cycle never between machine cycles of a single instruction cycle.
Similarly instruction cycles are only executed upon
completion of a DMA transfer whether it be a one
machine cycle transfer or two machine cycles (for
ext. to ext. memory transfers).
2. A single machine cycle DMA register read operation (Le. MOV A, DCa NO) will inhibit the DMA for
one instruction cycle. However a two cycle DMA
register read operation will not inhibit the DMA
(i.e. MOV P1, DCONO).
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Alternate Cycle Mode, it will
take two instruction cycles before DMA 1 is activated
(due to the priority of DMAO). Once DMA1 becomes
active, the execution will follow the normal sequence.
If the HOLD/HOLD Acknowledge logic is enabled in
requestor mode the hold request will go active once
the go bit has been set (for burst mode) and once
the demand flag is set (for demand mode) regardless of whether the DMA is h'eld off by one of the
above conditions.
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Burst Mode, the DMA 1 Burst
transfer will follow the DMAO Alternate Cycle transfer (after the completion of the next instruction).
The DMA Transfer waveforms are in Figures 8-11.
9-30
UPI-452
52
51
53
54
55
56
52
51
53
54
55
56
05C
J1. rLrL rLfl.. rLrL rLfl.. rLfl.. rLfl.. rLfl.. rLfl.. rLfl.. rLrL rLfl.. r-
ALE
r
PORT2
PORTO
r h
h
-
5 URCE "DDR ~5
X
AI5-A
A7-AO
DATA IN
r-
DES
A7- 0
NATION ADD [55
X
A15 A8
DATA OUT
r
1\
Dt.4A CYCLE
231428-13
Figure 8. DMA Transfer from External Memory to External Memory
- - - - - - - - D " A cYCLE - - - - - - - - - 1
51
52
53
54
56
55
52
51
53
CLOCK
ALE
PORT2~~~~~____+-~~~~~~~~~
______+-____ ____ ____
~
~
PORTO
RD
231428-14
Figure 9.DMA Transfer from External Memory to Internal Memory
51
52
53
54
55
56
51
52
53
CLOCK
ALE
PO~2~____-JI~
____+-__~DE~5T~IN~A~TI0_N_A_D_DR7E~55__A~I_5-~A~B-----t-----1.~----t---DATA OUT
PORTO
I - - - - - - - - D " A CYCLE---------I
231428-15
Figure 10. DMA Transfer from Internal Memory to External Memory
9-31
UPI-4S2
S1
S2
S3
S5
S4
S6
S2
S1
S3
CLOCK
ALE
-J
/
\
~
PORT2
PORTO
A15-AB
-<
INST
A15-AB
I
A7-AO
INSTRUCTION
EXECUTION
DMA CYCLE
It-I-231428-16
Figure 11. DMA Transfer from Internal Memory to .'nterna' Memory
Table 6. Interrupt Priority
Interrupt Source
Priority Level
(highest)
External Interrupt 0
o
Internal Timer/Counter 0
1
DMA Channel 0 Request
2
External Interrupt 1
3
DMA Channel 1 Request
4
Internal Timer/Counter 1
5
FIFO - Slave Bus Interface
6
7
Serial Channel
(lowest)
INTERNAL INTERRUPTS
Overview
The UPI-452 provides a total of eight interrupt sources (Table 6). Their operation is the same as in the
80C51, with the addition of three new interrupt
sources for the UPI-452 FIFO and DMA features.
These added interrupts have their enable and priority bits in the Interrupt Enable and Priority (IEP) SFR.
The IEP SFR is in addition to the 80C51 Interrupt
Enable (IE) and Interrupt Priority (IP) SFRs. The added interrupt sources are also globally enabled or disabled by the EA bit in the Interrupt Enable SFR. Table 6 lists the eight interrupt sources in order of priority. Table 7 lists the eight interrupt sources and
their respective address vector location in program
memory. (DMA interrupts are discussed in the "General Purpose DMA Channels" section. Additional interrupt information for Timer/Counter, Serial Channel, External Interrupt may be found in the Microcontroller Handbook for the 80C51.)
Table 7. Interrupt Vector Addresses
Interrupt Source
Starting Address
External Interrupt 0
3 (003H)
Internal Timer/Counter 0
11 (OOBH)
External Interrupt 1
19 (013H)
Internal Timer/Counter 1
27 (01 BH)
Serial Channel
35 (023H)
FIFO - Slave Bus Interface
43 (02BH)
51 (033H)
DMA Channel 0 Request
DMA Channel 1 Request
59 (03BH)
FIFO Module Interrupts to Internal CPU
FIFO requests service when it becomes empty or
not full as determined by bit 0 of the Slave Control
SFR (OFRS). Request for Service interrupts are
generated only if enabled by the internal CPU via the
Interrupt Enable SFR, and the Slave Control Register.
The FIFO module generates interrupts to the internal CPU whenever the FIFO requests service or
when a Data Stream Command is in the COMMAND
IN SFR. The Input FIFO will request service whenever it becomes full or not empty depending on bit 1 of
the Slave Control SFR (lFRS). Similarly, the Output
9-32
inter
UPI-452
A Data Stream Command Interrupt is generated
whenever there is a Data Stream Command in the
COMMAND IN SFR. The interrupt is generated to
ensure that the internal interrupt is recognized before another instruction is executed.
Immediate Command OUT bit (SSTAT SST6) to
be set and the corresponding Host Status bit
(HSTAT HST6) to be cleared indicating the SFR is
empty. When the internal CPU writes to the Immediate Command OUT SFR, the Host Status bit is
set and Slave Status bit is cleared to indicate the
SFR is full. (See Figure 7b, Immediate Command
OUT Flowchart.)
Immediate Command Interrupts
a. An Immediate Command IN interrupt is generated, if enabled, to the internal CPU when the Host
has written to the Immediate Command IN (IMIN)
SFR. The write operation clears the Slave Status
SFR bit (SSTAT SST2) and sets the Host Status
SFR bit (HSTAT HST2) to indicate that a byte is
present in the Immediate Command IN SFR.
When the internal CPU reads the Immediate Command IN (IMIN) SFR the Slave Status SFR status
bit is set, and the Host Status SFR status bit is
cleared indicating the IMIN SFR is empty. Clearing the Host Status SFR bit will cause a Request
For Service (INTRQ) interrupt, if enabled, to signal
the Host that the IMIN SFR is empty. (See Figure
7a, Immediate Command IN Flowchart.)
NOTE:
Immediate Command IN and OUT interrupts are actually specific FIFO-Slave Interface interrupts to the
internal CPU.
One instruction from the main program is executed
between two consecutive interrupt service routines
as in the 80C51. However, if the second interrupt
service routine is due to a Data Stream Command
Interrupt, the main program instruction is not executed (to prevent misreading of invalid data).
Interrupt Enabling and Priority
b. An Immediate Command OUT interrupt is generated, if enabled, to the internal CPU when the
Host has read the Immediate Command OUT
SFR. The Host read causes the Slave Status
Each of the three interrupt special function registers
(IE, IP and IEP) is listed below with its corresponding
bit definitions.
Interrupt Enable SFR (IE)
Symbolic
Address
IE
Physical
Address
EA
ES
ET1
EX1
ETO
(MSB)
Symbol
EXO
OA8H
(LSB)
Position
Function
EA
1E.7
-
IE.6
IE.5
IE.4
IE.3
IE.2
1E.1
lE.O
Enables all interrupts. If EA = 0, no interrupt will be
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
(reserved)
(reserved)
Serial Channel interrupt enable
Internal Timer/Counter 1 Overflow Interrupt
External Interrupt Request 1.
Internal Timer/Counter 0 Overflow Interrupt
External Interrupt Request O.
ES
ET1
EX1
E~O
EXO
9-33
inter
UPI·452
Interrupt Priority SFR (IP)
A priority level of 0 or 1 may be assigned to each interrupt source, with 1 being higher priority level, through the
IP and the IEP (Interrupt Enable and Priority) SFR. A priority level of 1 interrupt can interrupt a priority level 0
service routine to allow nesting of interrupts.
Symbolic
Address
Physical
Address
IP
PS
PT1
PX1
Symbol
PTO
PXO
OB8H
(LSB)
(MSBj
Position
Function
IP.?
IP.6
IP.5
IPA
IP.3
IP.2
IP.1
IP.O
(reserved)
(reserved)
(reserved)
Local Serial Channel
Internal Timer/Counter 1
External Interrupt Request 1
Internal Timer/Counter 0
External Interrupt Request 0
Priority Within
A Level
(lowest)
PS
PT1
PX1
PTO
PXO
O.?
0.5
0.3
0.1
0.0
(highest)
Interrupt Enable and Priority SFR (IEP)
The Interrupt Enable and Priority Register establishes the enabling and priority of those resources not covered
in the Interrupt Enable and Interrupt Priority SFRs.
Physical
Address
Symbolic
Address
I PFIFO I EDMAO I EDMA1 I PDMAO I PDMA1 I EFIFO I
IEP
(LSB)
(MSB)
Symbol
Position
Function
-
IEP.?
. IEP.6
IEP.5
IEPA
IEP.3
IEP.2
IEP.1
IEP.O
(reserved)
(reserved)
FIFO Slave Bus Interface Interrupt Priority
DMA Channel 0 Interrupt Enable
DMA Channel 1 Interrupt Enable
DMA Channel 0 Priority
DMA Channel 1 Priority
FIFO Slave Bus Interface Interrupt Enable
PFIFO
EDMAO
EDMA1
PDMAO
PDMA1
EFIFO
OF8H
9-34
Priority
Within a
Level
0.6
0.2
004
inter
UPI-452
Special Function Registers and their default power
on reset values;
FIFO-EXTERNAL HOST INTERFACE
FIFO DMA FREEZE MODE
Overview
During FIFO DMA Freeze Mode the internal CPU
can reconfigure the FIFO interface. FIFO DMA
Freeze Mode is provided to prevent the Host from
accessing the FIFO during a reconfiguration sequence. The internal CPU invokes FIFO DMA
Freeze Mode by clearing bit 3 of the Slave Control
SFR (SC3). INTRQ becomes active whenever FIFO
DMA Freeze Mode is invoked to indicate the freeze
status. The interrupt can only be deactivated by the
Host reading the Host Status SFR.
SFR Name
Label
Value
Channel Boundary Pointer
Output Channel Read Pointers
Output Channel Write Pointers
Input Channel Read Pointers
Input Channel Write Pointers
Input Threshold
Output Threshold
CBP
ORPR
OWPR
IRPR
IWPR
ITHR
OTHR
40H /640
40H / 640
40H / 640
OOH / 000
OOH / 000
80H / 1280
01H / 10
The Input and Output FIFO channels can be reconfigured by programming any of these SFRs while the
UPI-452 is in the Freeze Mode. The Host is notified
when the Freeze Mode is active by a "1" in HST1 of
the Host Status Register (HSTAT). The Host should
interrogate HST1 to determine the status of the
FIFO interface following reset before attempting to
read from or write to the UPI-452 FIFO buffer.
During FIFO DMA Freeze Mode only two operations
are possible by the Host to the UPI-452 slave, the
balance are disabled, as shown in Table 8. The internal DMA is disabled during FIFO DMA Freeze
Mode, and the internal CPU has write access to all
of the FIFO control SFRs (Table 9).
NOTE:
During the initialization sequence of the UPI-452
FIFO SFRs, the OTHR should be changed from the
default setting of 1 to a value between 2 and
!(80H-CBP)-11. Please refer to the section on Input
and Output FIFO threshold SFRs for further information.
'
Initialization
At power on reset the FIFO Host interface is automatically frozen. The Slave Control Enable FIFO
DMA Freeze Mode bit defaults to FIFO DMA Freeze
Mode (SLCON FRZ = 0). Below is a list of the FIFO
Table 8. Slave Bus Interface Status During FIFO DMA Freeze Mode
Interface Pins;
CS A2 A1
DACK
Operation In
Normal Mode
AO READ WRITE
Read Host Status SFR
Operational
1
Read Host Control SFR
Operational
0
Write Host Control SFR
Disabled
1
Data or DMA Data from
Output Channel
Disabled
1
0
Data or DMA Data to
Input Channel
Disabled
1
0
1
Data Stream Command from Disabled
Output Channel
0
1
1
0
Data Stream Command to
Input Channel
Disabled
1
0
0
0
1
Read Immediate Command
Out from Output Channel
Disabled
0
1
0
0
1
0
Write Immediate Command
In to Input Channel
Disabled
0
X
X
X
X
0
1
DMA Data from Output
Channel
Disabled
0
X
X
X
X
1
0
DMA Data to Input Channel
Disabled
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
Status In
FIFO DMA Freeze Mode
9-35
UPI·452
FIFO DMA Freeze Mode without first stopping the
external Host from accessing the UPI-452 will not
guarantee a clean break with the external Host.
The UPI-452 can also be programmed to interrupt
the Host following power on reset in order to indicate to the Host that FIFO DMA Freeze Mode is in
progress. This is done by enabling the INTRQ interrupt output pin via the MODE SFR (MD4) before the
Slave Control SFR Enable FIFO DMA Freeze Mode
bit is set to Normal Mode. At power on reset the
Mode SFR is forced to zero. This disables all interrupt and DMA output pins (INTRQ, DRQIN/
INTRQIN and DRQOUT /INTRQOUT). Because the
Host Status SFR FIFO DMA Freeze Mode In Progress bit is set, a Request For Service, INTRQ, interrupt is pending until the Host Status SFR is read.
This is because the FIFO DMA Freeze Mode interrupt is always enabled. If the Slave Control FIFO
DMA Freeze Mode bit (SLCON FRZ) is set to Normal Mode before the MODE SFR INTRQ bit is enabled, the INTRQ output will not go active when the
MODE SFR INTRQ bit is enabled if the Host Status
SFR has been read.
The proper way to invoke FIFO DMA Freeze Mode is
by issuing an Immediate Command to the external
host indicating that FIFO DMA Freeze Mode will be
invoked. Upon receiving the Immediate Command,
the external Host should complete servicing all
pending interrupts and.DMA requests, then send an
Immediate Command back to the UPI-452 acknowledging the FIFO DMA Freeze Mode request. After
issuing the first Immediate Command, the internal
CPU should not perform any action on the FIFO until
FIFO DMA Freeze Mode is invoked.
If FIFO DMA Freeze Mode is invoked without stopping the Host during Host transfers, only the last two
bytes of data written into or read from the FIFO will
be valid. The timing diagram for disabling the FIFO
module to the external Host interface is illustrated in
Figure 12. Due to this synchronization sequence, the
UPI-452 might not go into FIFO DMA Freeze Mode
immediately after SC3 is cleared. A special bit in the
Slave Status Register (SST5) is provided to indicate
the status of the FIFO DMA Freeze Mode. The FIFO
DMA Freeze Mode operations described in this section are only valid after SST5 is cleared.
The default values for the FIFO and Slave Interface
represents minimum UPI-452 internal initialization.
No specific Special Function Register initialization is
required to begin operation of theFIFO Slave Interface. The last initialization instruction must always
set the UPI-452 to Normal Mode. This causes the
UPI-452 to exit FIFO DMA Freeze Mode and enables Host read/write access of the FIFO.
As FIFO DMA Freeze Mode is invoked, the DRQIN
or DRQOUT will be deactivated (stopping the transferring of data), bit 1 of the Host Status SFR will be
set (HST1 = 1), and SST5 will be cleared (SST5 = 0)
to indicate to the external Host and internal CPU
that the slave interface has been frozen. After the
freeze becomes effective, any attempt by the external Host to access the FIFO will cause the overrun
and underrun bits to be activated (bits HST7 (for
reads) or HST3 (for writes)). These two bits, HST3
and HST7, will be set (deactivated) after the Host
Status SFR has been read. If INTRQ is used to request service, the FIFO interface is frozen upon
completion of any Host read or write operation in
progress.
Following reset, either hardware (via the RST pin) or
software (via HCON SFR bit HC3) the UPI-452 requires 2 internal machine cycles (24 TCLCL) to update all internal registers.
Invoking FIFO DMA Freeze Mode
During Normal Operation
When the UPI-452 is in normal operation, FIFO DMA
Freeze Mode should not be arbitrarily invoked by
clearing SC3 (SC3 = 0) because the external Host
runs asynchronously to the internal CPU. Invoking
DRQIN/
DRQOUT
..J
r-: - - - - - - - 5 5
I' ~.!
,
,
INTRQ
~_
S-----....,
A FIFO RD/WR AFTER INTERrACE
FREEZE IS INVOKED WILL CAUSE
HST3 OR HST7 TO BE SET
5~-------#~---~-~------~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
: nro INTERNALLY STOPPED fROM
• ACCEPTING OR OUTPUTTING DATA
SC3
HSTl _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
231428-17
Figure 12. Disabling FIFO to Host Slave Interface Timing Diagram
9-36
UPI-4S2
External Host writing to the Immediate Command In
SFR and the Host Control SFR is also inhibited
when the slave bus interface is frozen. Writing to
these two registers after FIFO DMA Freeze Mode is
invoked will also cause HST3 (overrun) to be activated (HST3 = 0). Similarly, reading the Immediate
Command Out Register by the external Host is disabled during FIFO DMA Freeze Mode, and any attempt to do so will cause the clearing (deactivating,
"0") of HST7 bit (underrun).
HCON, the Input Channel error condition flag
(HST3) will be cleared.
Input FIFO Pointer Registers
(lRPR & IWPR)
Once the FIFO module is in FIFO DMA Freeze
Mode, error flags due to overrun and underrun of the
Input FIFO pointers will be disabled. Any attempt to
create an overrun or underrun condition by changing
the Input FIFO pointers would result in an inconsistency in performance between the status flag and the
threshold counter.
After the slave bus interface is frozen, the internal
CPU can perform the following operations on the
FIFO Special Function Registers (these operations
are allowed only during FIFO DMA Freeze Mode).
For FIFO
Reconfiguration
1. Changing the Channel
Boundary Pointer SFR.
2. Changing the Input and
Output Threshold SFR.
To Enhance the
Testability
3. Writing to the read and write
pointers of the Input and
Output FIFO's.
4. Writing to and reading the
Host Control SFRs.
5. Controlling some bits of Host
and Slave Status SFRS.
6. Reading the Immediate
Command Out SFR and
Writing to the Immediate
Comand In SFR.
To enhance the speed of the UPI-452, read operations on the Input FIFO will look ahead by two bytes.
Hence, every time the IRPR is changed during FIFO
DMA Freeze Mode, two NOPs need to be executed
so that the two byte pipeline can be updated with the
new data bytes pointed to by the new IRPR. The
Threshold Counter SFR also needs to change by the
same number of bytes as the IRPR (increase
Threshold Counter if IRPR goes forward or decrease
if IRPR goes backward). This will ensure that future
interrupts will still be generated only after a threshold number of bytes are available. (See "Input and
Output FIFO Threshold SFR" section below.)
In FIFO DMA Freeze Mode, the internal CPU can
also change the content of IWPR, and each change
of IWPR also requires an update of the Threshold
Counter SFR.
Normally, the internal CPU cannot write into the Input FIFO. It can, however, during FIFO DMA Freeze
Mode by first reconfiguring the FIFO as an Output
FIFO (Refer to "Input and Output FIFO Threshold
SFR" section below). Changing the IRPR to be
equal to IWPR generates an empty condition while
changing IWPR to be equal to IRPR generates a full
condition. The order in which the pointers are written
determines whether a full or empty condition is generated.
Description of each of these special
functions are as follows:
FIFO Module SFRs During
FIFO DMA Freeze Mode
Table 9 summarizes the characteristics of all the
FIFO Special Function Registers during normal and
FIFO DMA Freeze Modes. The registers that require
special treatment in FIFO DMA Freeze Mode are:
HCON, IWPR, IRPR, OWPR, ORPR, HSTAT,
SSTAT, MIN & MOUT SFRs. They can be described
in detail as follows:
Output FIFO Pointer SFR
(ORPR and OWPR)
In FIFO DMA Freeze Mode the contents of OWPR
can be changed by the internal CPU, but each
change of OWPR or ORPR requires the Threshold
Counter SFR to be updated as described in the next
section. A NOP must be executed whenever a new
value is written into ORPR, as just described for
changes to IRPR. As before, changing ORPR to be
equal to OWPR will generate an empty condition,
Output FIFO overrun or underrun condition cannot
be generated though. The FIFO pointers should not
be set to a value outside of its range.
Host Control SFR (HCON)
During normal operation, this register is written to or
read by the external Host. However, in FIFO DMA
Freeze Mode (Le. SST5 = 0) the UPI-452 internal
CPU has write access to the Host Control SFR and
write operations to this SFR by the external Host will
not be accepted. If the Host attempts to write to
9-37
UPI-452
Table 9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Label
Normal
Operation
(SST5 = 1)
Name
FIFO DMA Freeze Mode
Operation
(SST5 = 0)
HCON
Host Control
Not Accessible
Read & Write
HSTAT
Host Status
Read Only
Read & Write 4
SLCON
Slave Control
Read & Write
Read & Write
SSTAT
Slave Status
Read Only
Read & Write 4
IEP
Interrupt Enable & Priority
Read & Write
Read & Write
MODE
Mode Register
Read & Write
Read & Write
IWPR
Input FIFO Write Pointer
Read Only
Read & Write 5
IRPR
Input FIFO Read Pointer
Read Only
Read & Write 1, 5
OWPR
Output FIFO Write Pointer
Read Only
Read & Write (5
ORPR
Output FIFO Read Pointer
Read Only
Read & Write 2, 6
CBP
Channel Boundary Pointer
Read Only
Read & Write 3
IMIN
Immediate Command In
Read Only
Read & Write
IMOUT
Immediate Command Out
Read & Write
Read & Write
FIN
FIFO IN
Read Only
Read Only
CIN
COMMAND IN
Read Only
Read Only
FOUT
FIFO OUT
Read & Write
Read & Write
COUT
COMMAND OUT
Read & Write
Read & Write
ITHR
Input FIFO Threshold
Read Only
Read & Write
OTHR
Output FIFO Threshold
Read Only
Read & Write
NOTES:
1. Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location.
2. Writing to ORPR will automatically cause the IOBl SFR to load the contents of the Output FIFO at that ORPR address.
3. Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels.
4. The internal CPU cannot directly change the status of these registers. However, by changing the status of the FIFO
channels, the internal CPU can indirectly change the contents of the status registers.
5. Changing the Input FIFO Read/Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter
SFR.
6. Changing the Output FIFO Read/Write Pointers also requires that a consistent update of the Output FIFO Threshold
Counter SFR.
9-38
inter
UPI·452
Correspondingly, the OTHR should be programmed
in the range from 2 to [(80H-CBP)-11. An OTHR
value of 1 could result in a failure to set the Output
FIFO service request after subsequent writes by the
UPI-452 have filled the Output FIFO.
Input and Output FIFO Threshold SFR
(ITHR & OTHR)
The Input and Output FIFO Threshold SFRs are also
programmable by the internal CPU during FIFO DMA
Freeze Mode. For proper operation of the Threshold
feature, the Threshold SFR should be changed only
when the Input and Output FIFO channels are empty, since they reflect the current number of bytes
available to read/write before an interrupt is generated.
NOTE:
When programming the ITHR SFR, the eighth bit
should be set to 1 (OR'd with 80H). This causes
HSTAT SFR HSTO = 0, Input FIFO Request For
Service. If ITHR bit 7 = 0 then HSTAT HSTO = 1,
Input FIFO Does Not Request Service, and no interrupt will be generated.
Table 10 illustrates the Threshold SFRs range of
values and the number of bytes to be transferred
when the Request For Service Flag is activated:
Host Status SFR (HST AT)
Table 10. Threshold SFRs Range of Values and
Number of Bytes to be Transferred
When in FIFO DMA Freeze Mode, some bits in the
Host Status SFR are forced high and will not reflect
the new status until the system returns to normal
operation. The definition of the register in FIFO DMA
Freeze Mode is as follows:
ITHR
No. of Bytes
OTHR
No. of Bytes
(lower Available to
(lower
Available to
be Read
~even bits) be Written seven bits)
0
1
2
CBP
CBP-1
CBP-2
•
•
•
•
•
•
CBP-3
3
2
3
3
4
•
•
•
•
NOTE:
The internal CPU reads this shadow latch value
when reading the Host Status SFR. The shadow
latch will keep the information for these bits so normal operation can be resumed with the right status.
The following bits are set (= 1) when FIFO DMA
Freeze Mode is invoked;
•
•
(80H-CBP)-3 (80H-CBP)-2
(80H-CBP)-2 (80H-CBP)-1
(80H-CBP)-1 (80H-CBP)
HST7 Output FIFO Error Condition Flag
1 = No error.
The eighth bit of the Input and Output FIFO Threshold SFR indicates the status of the service requests
regardless of the freeze condition. If the eighth bit is
a "1", the FIFO is requesting service from the external Host. In other words, when the Threshold SFR
value goes below zero (2's complement), a service
request is generated*. *The 8th bit of the ITHR SFR
must be set during initialization if the Host interrupt
request is desired immediately upon leaving Freeze
Mode. Normally the ITHR SFR is decremented after
each external Host write to the Input FIFO and incremented after each .internal CPU read of the Input
FIFO. The OTHR SFR is decremented by internal
CPU writes and incremented by external Host reads.
Thus if the pointers are moved when the FIFO's are
not empty, these relationships can be used to calculate the offset for the Threshold SFRs. It is best to
change the .Threshold SFRs only when the FIFO's
are empty to avoid this complication. The threshold
registers should also be updated after the pointers
have been manipulated.
o=
An invalid read has been done on the
output FIFO or the Immediate Command
Out Register by the host CPU.
NOTE:
The normal underrun error condition status is disabled. If an Immediate Command Out (IMOUT)
SFR read is attempted during FIFO DMA Freeze
Mode, the contents of the IMOUT SFR is output on
the Data Buffer and the error status is cleared
(= 0).
HST6 Immediate Command Out SFR Status
During normal operation, this bit is cleared
(= 0) when the IMOUT SFR is written by the
UPI-452 internal CPU and set (= 1) when the
IMOUT SFR is read by the external Host.
Once the host-slave interface is frozen (Le.
SST5 = 0), this bit will be read as a 1 by the
host CPU. A shadow latch will keep the information for this bit so normal operation can be
resumed with the correct status.
NOTE:
The ITHR should only be programmed in the range
from 0 to (CBP-3). An ITHR value of (CBP-2) could
result in a failure to set the Input FIFO service request signal after the Input FIFO has been emptied.
Shadow latch:
1 = Internal CPU reads the IMOUT SFR
o=
9-39
Internal CPU writes to the IMOUT SFR
intJ
UPI-4S2
HST5 Data Stream Command at Output FIFO
This bit is forced to a "1" during FIFO DMA
Freeze Mode to prevent the external host
CPU from trying to read the DSC. Once normal operation is resumed, HST5 will reflect
the Data/Command status of the current byte
in the Output FIFO.
Shadow Latch (read by the internal CPU):
Slave Status SFR (SSTA T)
The Slave Status SFR is a read-only SFR. However,
once the slave interface is frozen, most of the bits of
this SFR can be changed by the internal CPU by
reconfiguring the FIFO and accessing the FIFO Special Function Registers.
SST? Output FIFO Overrun ErrorFlag
Inoperative in FIFO DMA Freeze Mode.
SST6 Immediate Command Out SFR Status
In FIFO DMA Freeze Mode, this bit will be
cleared when the. internal CPU reads the Immediate Command Out SFR and set when
the internal CPU writes to the Immediate
Command Out Register.
SST5 FIFO-External Interface FIFO DMA Freeze
Mode Status
This bit indicates to the internal CPU that
FIFO DMA Freeze Mode is in progress and
that it has write access to the FIFO Control,
Host control and Immediate Command SFRs.
SST4 Output FIFO Request Service Status
During normal operation, this bit indicates to
the internal CPU that the Output FIFO is
ready for more data. The status of this bit reflects the position of the Output FIFO read
and write pointers. Hence, in FIFO DMA
Freeze Mode, this flag can be changed by the
internal CPU indirectly as the read and write
pointers change.
SST3 Input FIFO Underrun Flag
Inoperative during FIFO DMA Freeze Mode.
During normal operation, a read operation
clears (= 0) this bit when there are no data
bytes in the Input FIFO and deactivated (= 1)
when the Slave Status SFR is read. In FIFO
DMA Freeze Mode, this bit will not be cleared
by an Input FIFO read underrun error condition, nor will it be reset by the reading of the
Slave Status SFR.
SST2 Immediate Command In SFR Status
This bit is normally activated (= 0) when the
external host CPU writes into the Immediate
Command In SFR and deactivated (= 1)
when it is read by the internal CPU. In FIFO
DMA Freeze Mode, this bit will not be activated (= 0) by the external Host's writing of the
Immediate Command IN SFR since this function is disabled. However, this bit will be
cleared (= 0) if the internal CPU writes to the
Immediate Command In SFR and it will be set
= 1) if it reads from the register.
1 = No Data Stream Command (DSC)
Data Stream Command at Output FIFO
HST4 Output FIFO Service Request Status
When FIFO DMA Freeze Mode is invoked,
this bit no longer reflects the Output FIFO Request Service Status. This bit wll be forced to
a "1".
HST3 Input FIFO Error Condition Flag
1 = No error.
a = One of the following operations has
been attempted by the external host and
is invalid:
1) Write into the Input FIFO
2) Write into the Host Control SFR
3) Write into the Immediate Command In
SFR
a=
NOTE:
The normal Input FIFO overrun condition is disabled.
HST2 Immediate Command In SFR Status
This bit is normally cleared when the internal
CPU reads the IMIN SFR and set when the
external host CPU writes into the IMIN SFR.
When the host-slave interface is frozen, reading and writing of the IMIN by the internal
CPU will change the shadow latch of this bit.
This bit will be read as a "1" by the external
Host.
Shadow latch.
1 = Internal CPU writes into IMIN SFR
a = Internal CPU reads the IMIN SFR
HST1 FIFO DMA Freeze Mode Status·
1 = FIFO DMA Freeze Mode.
= Normal
Operation (non-FIFO DMA
Freeze Mode).
a
NOTE: .
This bit is used to indicate to the external Host that
the host-slave interface has been frozen and hence
the external Host functions are now reduced as
shown in Table 8.
HSTa Input FIFO Request Service Satus
When slave interface is frozen this bit no
longer reflects the Input FIFO Request Service Status. This bit will be forced to a "1".
9-40
UPI-452
SST1 Data Stream Command at Input FIFO Flag
In FIFO DMA Freeze Mode, this bit operates
normally. It indicates whether the next byte of
data from the Input FIFO is a DSC or data
byte. If it is a DSC byte, reading from the
FIFO IN SFR will result in reading invalid data
(FFH) and vice versa. In FIFO DMA Freeze
Mode, this bit still reflects the type of data
byte available from the Input FIFO.
ORPR SFR to zero. This generates a FIFO empty
Signal and allows internal CPU write operations to all
128 bytes of the FIFO. The Threshold registers also
need to be adjusted when the pointers are changed.
(See "Input and Output FIFO Threshold SFR" section below.)
SSTO Input FIFO Service Request Flag
During normal operation, this bit is activated
(= 0) when the Input FIFO contains bytes that
can be read by the internal CPU and deactivated (= 1) when the Input FIFO does not
need any service from the internal CPU. In
FIFO DMA Freeze Mode, the status of this bit
should not change unless the pointers of the
Input FIFO are changed. In this mode, the internal CPU can indirectly change this bit by
changing the read and write pointers of the
Input FIFO but cannot change it directly.
The UPI-452 has separate address spaces for Program Memory and Data Memory like the 80C51. The
Program Memory can be up to 64K bytes. The lower
8K of Program Memory may reside on-chip. The
Data Memory consists of 256 bytes of on-chip RAM,
up to 64K bytes. of off-chip RAM and a number of
"SFRs" (Special Function Registers) which appear
as yet another set of unique memory addresses.
MEMORY ORGANIZATION
Table 11a. Internal Memory Addressing
Memory Space
Addressing Method
Lower 128 Bytes of
Internal RAM
Direct or Indirect
Immediate Command InlOut SFR
(IMIN/IMOUT)
Upper 128 Bytes
of Internal RAM
Indirect Only
If FIFO DMA Freeze Mode is in progress, writing to
the Immediate Command In SFR by the external
host will be disabled, and any such attempt will
cause HST3 to be cleared (= 0). Similarly, the Immediate Command Out SFR read operation (by the
host) will be disabled internally and read attempts
will cause HST7 to be cleared (= 0).
UPI-452 SFR's
Direct Only
The 80C51 Special Function Registers are listed in
Table 11a, and the additional UPI-452 SFRs are listed in Table 11 b. A brief description of the 80C51
core SFRs is also provided below.
Accessing External Memory
Internal CPU Read and Write of the
FIFO During FIFO DMA Freeze Mode
As in the 80C51, accesses to ex1ernal memory are
of two types: Accesses to external Program Memory
and accesses to external Data Memory.
In normal operation, the Input FIFO can only be read
by the internal CPU and similarly, the Output FIFO
can only be written by the internal CPU. During FIFO
DMA Freeze Mode, the internal CPU can read the
entire contents of the Input FIFO by programming
the CBP SFR to 7FH, setting the IRPR SFR to zero,
and then the IWPR SFR to zero. Programming the
pointer registers in this order generates a FIFO full
signal to the FIFO logic and enables internal CPU
read operations. If the IWPR and IRPR are already
zero, the write pointer should be changed to a nonzero value to clear the empty status then the pointers can be set to zero. Writing to the IRDR SFR
automatically updates the look ahead registers.
External Program Memory is accessed under two
conditions:
1) Whenever signal EA = 0; or
2) Whenever the program counter (PC) contains a
number that is larger than 1FFFH.
This requires that the ROM less versions have EA
wired low to enable the lower 8K program bytes to
be fetched from external memory.
External Data Memory is accessed using either the
MOVX @DPTR (16 bit address) or the MOVX @Ri (8
bit address) instructions, or during external data
memory transfers.
In a similar manner, the internal CPU can write to all
128 bytes of the FIFO by setting the CBP SFR to
zero, setting OWPR SFR to zero, and then setting
9-41
UPI-4S2
Table 11b. 80C51 Special Function Registers
Symbol
'ACC
'B
'PSW
SP
DPTR
'PO
'P1
'P2
'P3
'IP
'IE
TMOD
'TCON
THO
TLO
TH1
TL1
'SCON
SBUF
PCON
Name
Accumulator
B Register
Program Status
Word
Stack Pointer
Data Pointer
(consisting of DPH
and DPL)
Port 0
Port 1
Port 2
Port 3
Interrupt Priority
Control
Interrupt Enable
Control
Timer/Counter
Mode Control
Timer/Counter
Control
Timer /Counter
o (high byte)
Timer/Counter
o (low byte)
Timer/Counter
1 (high byte)
Timer/Counter
1 (low byte)
Serial Control
Serial Data Buff
Power Control
Table 11 c. UPI·452 Additional Special
Function Registers (Continued)
Address Contents
OEOH
OFOH
ODOH
OOH
OOH
OOH
81H
82H
07H
OOOOH
80H
90H
OAOH
OBOH
OB8H
Symbol
DARLO
OFFH
·OFFH
OFFH
OFFH
OEOH
BCRLO
DMA Byte
Count Low Byte/
High Byte/
Channel 0
Low Byte/
Hi Byte/
Channel 1
Channel Boundary
Pointer
COMMAND IN
COMMAND OUT
DMA Destination
Address
BCRHO
BCRU
BCRH1
CBP
CIN
COUT
Low Byte/
OC2H
I
DARHO Hi Byte!
Channel 0
OC3H
I
DARL1
Low Byte/
OD2H
I
DARH1
Hi Byte/
Channel 1
OD3H
I
DCONO DMAO Control
92H
OOH
DCON1. DMA 1 Control
93H
OOH
I
FIN
FIFO IN
OEEH
FOUr
FIFO OUT
OFEH
I
HCON
Host Control
OE7H
OOH
HSTAT
Host Status
OE6H
OFBH
*IEP
Interrupt EnablE;l
and Priority
OF8H
OCOH
IMIN
Immediate Command
In
OFCH
I
IMOUT
Immediate Command
Out
OFDH
I
IRPR.
Input Read
Pointer
OEBH
OOH
60H
89H
OOH
88H
OOH
8CH
OOH
8AH
OOH
8DH
OOH
8BH
OOH
ITHR
Input FIFO
Threshold
OF6H
80H
98H
99H
87H
OOH
I
IOH
IWPR
Input Write
Pointer
OEAH
OOH
Table 11c. UPI·452 Additional
Special Function Registers
Name
--
Address Contents
OA8H
I = Indeterminate
The SFRs marked with an asterisk (*) are both bit- and
byte- addressable. The functions of the SFRs are as follows:
Symbol
Name
MODE
Mode Register
OF9H
8FH
ORPR
Output Read
Pointer
OFAH
40H
OTHR
Output FIFO
Threshold
OF7H
01H
OWPR
Output Write
Threshold
OFBH
40H
Port 4
DMA Source Address
OCOH
OFFH
Address Contents
OE2H
I
*P4
OE3H
I
SARLO
Low Byte/
OA2H
I
SARHO
Hi Byte/
Channel 0
OA3H
I
SARL1
Low Byte/
OB2H
I
SARH1
Hi Byte/
Channel 1
OB3H
I
OF2H
OF3H
I
I
OECH
40H
OEFH
OFFH
I
I
*SLCON Slave Control
OE8H
04H
SSTAT
OE9H
08FH
Slave Status
I = Indeterminate
The SFRs marked with an asterisk (*) are both bit- and
byte- addressable. The functions of the SFRs are as follows:
9-42
inter
UPI-452
Miscellaneous Special Function
Register Description
DATA POINTER
The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL). Its intended function is
to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent 8-bit registers.
80C51 SFRs
ACCUMULATOR
PORTS 0 TO 4
ACC is the Accumuator SFR. The mnemonics for
accumulator-specific instructions, however, refer to
the accumulator simply as A.
PO, P1, P2, P3 and P4 are the SFR latches of Ports
0, 1, 2, 3 and 4, respectively.
B REGISTER
SERIAL DATA BUFFER
The B SFR is used during multiply and divide operations. For other instructions it can be treated as another scratch pad regster.
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Moving a byte to SBUF is what initiates the
transmission.) When data is moved from SBUF, it
comes from the receive buffer.
PROGRAM STATUS WORD
The PSW SFR contains program status information
as detailed in Table 12.
TIMER/COUNTER SFR
STACK POINTER
Register pairs (THO, TLO), and (TH1, TL 1) are the
16-bit counting registers for Timer/Counters 0 and 2.
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and
CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized
to 07H after a reset. This causes the stack to begin
at location 08H.
POWER CONTROL SFR (PCON)
The PCON Register (Table 13) controls the power
down and idle modes in the UPI-4S2, as well as providing the ability to double the Serial Channel baud
rate. There are also two general purpose flag bits
available to the user. Bits 5 and 6 are used to set the
HOLD/HOLD Acknowledge mode (see "General
Purpose DMA Channels" section), and bit 4 is not
used.
9-43
UPI-452
Table 12. Program Status Word
Physical
Address
Symbolic
Address
CY
PSW
AC
FO
RSO
RS1
p
OV
ODOH
(lSB)
(MSB)
Symbol
Position
CY
AC
FO
RS1
RSO
OV
PSW.?
PSW.S
PSW.5
PSWA
PSW.3
PSW.2
PSW.1
PSW.O
P
Name
Carry Flag
Auxiliary Carry (For BCD operations)
Flag 0 (user assignable)
Register Bank Select bit 1 •
Register Bank Select bit O·
Overflow Flag
(reserved)
Parity Flag
'(RS1. RSO) enable Internal RAM register banks as follows:
RS1
RSO
0
0
0
1
1
0
Internal RAM Register Bank
BankO
Bank 1
Bank 2
Bank 3
1
1
Table 13. peON Special Function Register
Physical
Address
Symbolic
Address
PCON
SMOD
ARB
REO
GF1
(MSB)
GFO
PO
IDl
(lSB)
Symbol
Position
Function
SMOD
PCON?
ARB
REO
GF1
GFO
PO
PCONS
PCON5
PCON4
PCON3
PCON2
PCON1
IDl
PCONO
Double Baud rate bit. When set to a
1, the baud rate is doubled when the
serial port is being used in either
Mode 1, 2 or 3.
HlD/HlDA Arbiter control bit'
HlD/HlDA Requestor control bit •
(reserved)
General-purpose flag bit
General-purpose flag bit
Power Down bit. Setting this bit
activates power down operation.
Idle Mode bit. Setting this bit
activates idle mode operation.
-
'See "Ext. Memory DMA" description.
NOTE:
If 1's are written to PO and IOL at the same time, PO takes precedence. The reset value of peON is (OOOXOOOO).
9-44
08?H
inter
UPI-452
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... O°C to 70°C"!
Storage Temperature .......... -65°C to + 150°C
Voltage on Any
Pin to VSS ..... '" ....... -0.5V to Vee + 0.5V
Voltage on Vee to Vss ........... -0.5Vto +6.5V
Power Dissipation ........................ 1.0W··
NOTICE Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS
Symbol
TA
= 0°Cto70°C;Vee = 5V ±10%;Vss =
Parameter
ov
Min
Max
Units
-0.5
0.8
V
Input High Voltage
(except XTAL 1 , RST)
2;0
Vee + 0.5
V
VIHl
Input High Voltage
(XTAL 1, RST)
3.9
Vee + 0.5
V
VOL
Output Low Voltage
(Ports 1,2, 3, 4)
0.45
V
IOL
= 1.6 mA (Note 1)
VOLl
Output Low Voltage
(except Ports 1, 2, 3, 4)
0.45
V
IOL
= 3.2 mA (Note 1)
VOH
Output High Voltage
(Ports 1,2, 3, 4)
V
IOH
= -60 /-LA, Vee = 5V ± 10%
0.9 Vee
V
VOHl
Output High Voltage
(except Ports 1, 2, 3, 4 and
Host Interface (Slave) Port)
2.4
V
0.9 Vee
V
= -10/-LA
= -400/-LA, Vee = 5V ±10%
IOH = -40 /-LA (Note 2)
2.4
V
IOH
Vee - 0.4
V
VIL
Input Low Voltage
VIH
VOH2
Output High Voltage
(Host Interface (Slave) Port)
2.4
Test Conditions
IOH
IOH
= -400 /-LA, Vee = 5V ±10%
IlL
Logical 0 Input Current
(Ports 1,2, 3, 4)
-50
/-LA
= -10/-LA
VIN = 0.45V
ITL
Logical 1 to 0 Transition
Current (Ports 1,2, 3, 4)
-650
/-LA
VIN
9-45
IOH
= 2V
inter
UPI-4S2
D.C. CHARACTERISTICS
Symbol
T A = O°C to 70°C; VCC = 5V ± 10%; VSS = OV (Continued)
Max
Units
III
Input Leakage Current
(except Ports 1, 2, 3, 4)
Parameter
±10
}-LA
0.45V
< VIN < Vcc
loz
Output Leakage Current
(except Ports 1,2, 3, 4)
±10
}-LA
0.45V
< VOUT < Vcc
Icc
Operating Current
50
rnA
Vcc = 5.5V, 14 MHz (Note 4)
ICCI
Idle Mode Current
25
rnA
VCC = 5.5V, 14 MHz (Note 5)
IpD
Power Down Current
100
}-LA
VCC = 2V (Note 3)
RRST
Reset Pull down Resistor
150
KO
cia
Pin Capacitance
20
pF
Min
50
Test Conditions
1 MHz, TA = 25°C
(sampled, not tested on all parts)
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make tto-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fali before the 0.9 Vee
specification when the address bits are stabilizing.
3. Power DOWN lee is measured with. ali output pins disconnected; EA = Port 0 = Vee; XTAL2 N.C.; RST = Vss; DB =
Vce; WR = RD = DACK = CS = AD = AI = A2 = Vee. Power Down Mode is not supported on the 87C452P.
4. lee is measured with ali output pins discohnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V, VIH =
Vee - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = Vce; WR = RD = DACK = CS = AD = At = A2 = Vee. lee would be
slightly higher if a crystal osciliator is used.
5. Idle lee is measured with ali output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V,
VIH = Vee - 0.5V; XTAL2 N.C.; Port 0 = Vee; EA = RST = Vss; WR = RD = DACK = CS = AD = At = A2 = Vee·
Q: Output data.
EXPLANATION OF THE AC SYMBOLS
R: READ signal.
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for:
T: Time.
V: Valid.
W: WRITE sighal.
X: No longer a valid logic level.
Z: Float.
A: Address.
C: Clock.
EXAMPLE
D: Input data.
TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
H: Logic level HIGH.
I:
Instruction (program memory contents).
L: Logic level LOW, or ALE.
P: PSEN.
9A6
UPI-4S2
A.C. CHARACTERISTICS
Port 0, ALE, and PSEN
=;
TA = O°C to 70°C, Vee = 5V ± 10%, VSS = OV, Load Capacitance for
100 pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
14 MHzOsc
Min
Max
14
Variable Oscillator
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.5
TLHLL
ALE Pulse Width
103
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
(Note 1)
25
TCLCL-55
ns
TLLAX
Address Hold after ALE Low
36
TCLCL-35
TLLlV
ALE Low to Valid Instr In
TLLPL
ALE Low to PSEN Low
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr Hold after PSEN
TPXIZ
Input Instr Float after PSEN
(Note 1)
TAVIV
Address to Valid Instr In
TPLAZ
PSEN Low to Address Float
MHz
185
31
TCLCL-40
169
3TCLCL-45
ns
ns
ns
3TCLCL-105
110
0
ns
4TCLCL-100
0
ns
ns
57
TCLCL-25
ns
252
5TCLCL-105
ns
10
10
ns
TRLRH
RD Pulse Width
329
6TCLCL-100
ns
TWLWH
WR Pulse Width
329
6TCLCL-100
ns
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold after RD
192
0
5TCLCL-165
0
ns
ns
TRHDZ
Data Float after RD
73
2TCLCL-70
ns
TLLDV
ALE Low to Valid Data In
422
8TCLCL-150
ns
9TCLCL-165
ns
3TCLCL+50
ns
TAVDV
Address to Valid Data In
TLLWL
ALE Low to RD or WR Low
164
478
TAVWL
Address Valid to RD or WR Low
156
4TCLCL-130
ns
TOVWX
Data Valid to WR Transition
11
TCLCL-60
ns
TWHOX
Data Hold after WR
21
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
TOVWH
Data Valid to WR (Setup Time)
264
3TCLCL-50
TCLCL-50
0
31
350
111
TCLCL-40
7TCLCL-150
NOTE:
1. Use the value of 14 MHz specification or variable oscillator specification, whichever is greater.
9-47
ns
0
ns
TCLCL+40
ns
ns
inter
UPI-452
EXTERNAL DATA MEMORY READ CYCLE
rwHLH~ _______
ALE~____________________________________________~~-,
\ ~.________________
PSEN
J
/+1._ _ _ _
TLLDV _ _ _--I
J'
,'-----',
PORTO
PORT2 ____~r~----~~P2~.~O--~P2~.-7~O~R-A~8--~A~15~FR~O~M~DP_H______-J'-__
A8~_ Al~5_F_R_O_M_P_C_H
_
___
231428-19
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
~~j.---TPLPH
----I
TPXIZ
TPXIX'"
PORTO
PORT 2
INSTR IN
_______
J,~
__________________________________________'
A8-A15
231428-20
9-48
inter
UPI-452
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH-I
ALEJf
h
J
\
PSENJ
J
WR
TQVWH
PORTO
PORT2
TWHQX
OATA OUT
P2.0 - P2.7 OR A8 - A 15 FROM DPH
A8-A15 FROM PCH
231428-21
SHIFT REGISTER MODE TIMING WAVEFORMS
9-49
UPI·452
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TGLCL
Oscillator Frequency
3.5
14
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
NOTE:
External clock timings are sampled, not tested on all parts.
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: TA
. Symbol
=
O·C to 70·C; Vee
=
5V ± 1 0%; Vss
=
OV; Load Capacitance
14 MHzOsc
Parameter
Min
Max
=
80 pF
Variable Oscillator
Min
Max
Units
TXLXL
Serial Port Clock Cycle Time
857
12TCLCL
ns
TQVXH
Output Data Setup to Clock Rising Edge
581
1OTCLCL -133
ns
26
2TCLCL-117
ns
TXHQX Output Data Hold after Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge.
TXHDV
Clock Rising Edge to Input Data Valid
0
ns
0
1OTCLCL -133
581
ns
EXTERNAL CLOCK DRIVE WAVEFORM
231428-23
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC-0.5
-V
0.2 Vcc+0.9
FLOAT WAVEFORMS
)C.
TIMING REFERENCE
POINTS
0.45V -A._0_.2_V_c.,c-_0_._l- - - - - ' .
231428-25
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOLIIOH;' ±20 mAo
231428-24
AC inputs during testing are driven at Vce -0.5V for a logic "I"
and 0.45V for a logic "O'~. TIming measurements are made at VIH
min. for a logic "I" and VIL max. for a logic "0".
9-50
intJ
UPI-4S2
HLD/HLDA WAVEFORMS
Arbiter Mode
HLD _ _ _ _~t-.----THMIN
I - THLAL
'~......- - - - - - - - - -
=\I ______________
1l
THHAH
~Vr---------
\~
231428-26
Requestor Mode
HLDA
HLD
C
----..~t----- TAMIN-------+l
\~
_ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _..J/
' ' ' =\1. ._--
231428-31
HLD/HLDA TIMINGS
Test Conditions: T A = O°C to + 70°C; Vee
Symbol
Parameter
=
5V
± 10%, Vss = OV; Load Capacitance = 80 pF
14 MHzOsc
Min
Max
Variable Oscillator
Min
Max
Units
THMIN
HLD Pulse Width
386
THLAL
HLD to HLDA Delay if
HLDA is Granted
186
672
THHAH
HLD to HLDA Delay
186
672
TAMIN
HLDA Pulse Width
386
4TCLCL+l00
ns
TAHHL
HLDA Inactive to
HLD Active
186
4TCLCL-l00
ns
4TCLCL+l00
9-51
ns
4TCLCL-l00
8TCLCL+l00
4TCLCL-l00
8TCLCL+l00
ns
ns
· UPI-452
HOST PORT WAVEFORMS
TCC
READ OR
WRITE
}
'
TRV
f
TCC
TDV
DATA
t r
TDS --
~
TDR
TDH
I.-TRQ~
\
DRQIN
DRQOUT
)
231428-27
HOST PORT TIMINGS
Test Conditions: TA
Symbol
= O°C to 70°C; Vee = 5V ±10%; Vss = OV; Load Capacitance = 80 pF
Parameter
14 MHz Osc
Min
Max
Variable Oscillator
Min
Max
Units
TCC
Cycle Time
429
6TCLCL
ns
TPW·
Command Pulse Width
100
100
ns
TRV
RecoveryTime
60
60
ns
TAS
Address Setup Time
5
5
ns
TAH
Address Hold Time
30
30
ns
TDS
WRITE Data Setup Time
30
30
ns
TDHW
WRITE Data Hold Time
5
TDHR
READ Data Hold Time
5
TDV
READ Active to Read
Data Valid Delay
TDR
TRO
5
ns
92
92
ns
WRITE Inactive to Read
Data Valid Delay
(Applies only to Host
Control SFR)
343
4.8TCLCL
ns
READ or WRITE Active
to DROIN or DRQOUT
Inactive Delay
150
150
ns
9-52
5
ns
40
40
UPI-452
REVISION HISTORY
DOCUMENT:
UPI-452 Data Sheet
OLD REVISION NUMBER:
231428-004
NEW REVISION NUMBER:
231428-005
1. Maximum Clock Rate was changed from 16 MHz to 14 MHz. This change is reflected in all Maximum Timing
specifications.
2. The proper range of values for ITHR has been changed from [0 to (CBP-2) 1 to [ 0 to (CBP-3) 1 to ensure
proper setting of the Input FIFO request for service bit. See the following sections: INPUT FIFO CHANNEL,
and INPUT AND OUTPUT FIFO THRESHOLD SFR (ITHR & OTHR).
3. The proper range of values for OTHR has been changed from [ 1 to ((80H-CBP)-1 ) 1to [ 2 to ((80-CBP)-1 ) 1
to ensure proper setting of the Output FIFO request for service bit. See the following sections: OUTPUT
FIFO CHANNEL, FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE, and INPUT AND OUTPUT FIFO THRESHOLD SFR (ITHR & OTHR).
4. The following D.C. Characteristics were deleted from the data sheet:
=
=
VOH2 =
leel =
VOH
0.75* Vee
@
IOH
VOHl
0.75* Vee
@
IOH
3.0V
@
= -25/-LA,
= 150 /-LA,
IOH = 1 rnA, and
15 rnA @ Vee = 5.5V (87C452P).
See D.C. CHARACTERISTICS TABLE.
5. The parameter descriptions for THHAH and THLAL has been reversed and their maximum specification for
clock rates less than 14 MHz has been changed from [4TCLC + 100 nsl to [8TCLC + 100 ns]. See
HLD/HLDA TIMINGS.
6. TAMIN specification has been removed from the Arbiter Mode waveform diagram and added to the Requestor Mode waveform diagram. See HLD/HLDA WAVEFORMS.
9-53
intel~
UPITM-41, 42: 8041AH/8042AH/8741AH/8742AH
UNIVERSAL PERIPHERAL INTERFACE
8-BIT SLAVE MICROCONTROLLER
6 MHz; UPI-42: 12 MHz
• UPI-41:
Pin, Software and Architecturally
Fully Compatible with all Intel and Most
• Other
Microprocessor Families
ROM and EPROM
• Interchangeable
Versions
Expandable I/O
• Sync
Mode Available
• Compatible with all UPI-41 and UPI-42
Products
8-Bit CPU plus ROM/EPROM, RAM, I/O,
• Timer/Counter
and Clock in a Single
• Over 90 Instructions: 70% Single Byte
Package
• Available in EXPRESS
x 8 ROM/EPROM, 256 x 8 RAM on
• 2048
UPI-42, 1024 x 8 ROM/EPROM, 128 x 8
• - Standard Temperature Range
RAM on UPI-41, 8-Bit Timer/Counter, 18
Programmable I/O Pins
Programming™ Algorithm
• -inteligent
Fast EPROM Programming
One 8-Bit Status and Two Data
• Registers for Asynchronous Siave-toin 40-Lead Cerdip, 40-Lead
• Available
Master Interface
Plastic and 44-Lead Plastic Leaded
Chip Carrier Packages
DMA, Interrupt, or Polled Operation
• Supported
(See Packaging Spec., Order #231369)
The Intel UPI-41 and UPI-42 are general-purpose Universal Peripheral Interfaces that allow the designer to
develop customized solutions for peripheral device control.
They are essentially "slave" microcontrollers, or microcontrollers with a slave interface included on the chip.
Interface registers are included to enable the UPldevice to function as a slave peripheral controller in the
MCSTM Modules and iAPX family, as well as other 8-, 16-bit systems.
To allow full user flexibility, the program memory is available in ROM, One-Time Programmable EPROM (OTP)
and UV-erasable EPROM. All UPI-41 and UPI-42 devices are fully pin compatible for easy transition from
prototype to production level designs. These are the memory configurations available.
UPI
Device
8042AH
8742AH
8041AH
8741AH
'""
ROM
EPROM
2K
-
-
2K
1K
-
-
1K
Programming
Volt__
o:..;.':X=
T_ES_T_P_OI_N_TS_<
__
210393-14
210393-15
DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS
+ 5V
>6 MHz
470~~
XTAL1
»--+----"1 XTAl1
+ 5V
XTAl2
210393-16
210393-17
Rise and Fall Times Should Not Exceed IOns. Resistors to Vcc are Needed to Ensure VIH = 3.5V if TTL
Circuitry is Used.
LC OSCILLATOR MODE
CRYSTAL OSCILLATOR MODE
CI
L
C
45 H 20 pF
120 H 20pF
NOMINAL
5.2 MHz
3.2 MHz
.
1
f = 27TW
~ ~--+--:===r
_
I
f---'---'---:-i
9-67
XTAL2
C3
2
210393-18
Each C Should be Approximately 20 pF. including Stray Capacitance.
,1:<;;;12' XlALI
c,
-
C,=C+3Cpp
Cpp '" 5-10 pF
Pin-to-Pin Capacitance
:
C1
C2
C3
210393-19
5 pF (STRAY 5 pF)
(CRYSTAL + STRAY) 8 pF
20-30 pF INCLUDING STRAY
Crystal Series Resistance Should
be Less Than 30n at 12 MHz;
Less Than 75n at 6 MHz; Less
Than 180n at 3.6 MHz_
infef
UPI·41/42
WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER
cS OR
AO
~
X
(SYSTEM'S
ADORESS BUS)
-tA~-
'R.
-tJlA-
\
RD
V
-'.D-
(READ CONTROL:
--'OF
tAlI
210393-20
WRITE OPERATION-DATA BUS BUFFEi=l REGISTER
BOR Ao
~"----_--,--
_ _
- r~"._~~-_-=-,w_w~-_-
~
!SVSTEM'S
ADDRESS BUS)
WR
(WRITE CONTROll
DATA BUS
DATA
)
(lNPUTI _ _....,.._M_A_Y_C_HA_N...;G_'_ _ _J
DATA
--DATA VALlD_V
It\'-____M_A_Y_C_HA_N_G_'_ _ _ __
210393-21
CLOCK TIMING
2.4V
XTAL2
1.6V
.4SV
..
tCYC
210393-22
9-68
UPI-41/42
WAVEFORMS (Continued)
COMBINATION PROGRAM/VERIFY MODE
---,V
I
PROGRAM
I-tR,
VEAH ('2.5V)
EA
V,H (5V)
V,L(OV)
TO
V,H (5V)
V,L(OV)
RESET
D8 0-DB 7
V,H ,(5V)
V
V,H (5V)
V,L(OV)
V,L(OV)
'"'""""'
tWT
tww~ r-
\.
I--tAW- -tWA~
::>---
-
--~ttDO
ADDRESS
DATA IN
__
'~
- { NEXT ADDRESS
'1--
X
~
ADDRESS
tOE
END OF
PRO GRAM
OR VERIFY
PROGRAM -
-
--,
VOOH ('2.5 V).
VOO
VOOL(5 v)
PROG
-
- trw -
-
-+
'\
.....J
,L1 (OV)
V,H (5V)
P20- P22
-
VERIFY
1-
NEXT ADDRESS
tod
A
\....
t-tpw -
V,H (5V)
~
--
V,L(OV)
t ow -
-two
210393-23
NOTES:
1. Ao must be held low (OV) during program/verify modes.
2. For V,H. V,H1. V,L. V,L1. VOOH. and VOOL. please consult the D.C. Characteristics Table.
3. When programming the 8741AH/8742AH. a 0.1 fLF capacitor is required across VOO and ground to suppress spurious
voltage transients which can damage the device.
VERIFY MODE
EA
VEAH:::~~~~--------------------------------VIH
VIL
TO
RESET/
VIH
---4-----..;
,'----
VIL
VIH'
VIL'
VIH
080-087
VIL
P20-P22
~
NEXT ADDRESS
VIH==X
VIL
'---------------------------.
NOTES:
1. PROG must float if EA is low.
2. PROG must float or = 5V when EA is high.
3. P1Q-P17 = 5V or must float.
4. P24-P27 = 5V or must float.
5. Ao must be held low during programming/verify modes.
9-69
210393-29
inter
UPI-41/42
WAVEFORMS (Continued)
DMA
-
'ACC
-
-'CAC
-
DATA BUS
'ACC
--
-'CAC
-
VALID
VALID
-IACDORO
-It
-
'CRO--
210393-25
PORT 2
SYNC
EXPANDER
PORT
PORT 20.3 DATA
OUTPUT
EXPANDER
PORT
INPUT
PCRT 20-3 DATA
PROG
210393-26
PORT TIMING DURING EXTERNAL ACCESS (EA)
SYNC
P10-17
P20-22
/
PORT
DATA
X
\
/
\
X
PC
PORT
DATA
X
PC
210393-27
On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed on the Trailing Edge of Sync the
Program Counter Contents are Available_
9-70
inter
UPI-41/42
Table 2. UPITM Instruction Set
Mnemonic
Description
ACCUMULATOR
ADD A, Rr
Add register to A
ADD A, @Rr
Add data memory
toA
ADD A, #data
Add immediate to A
ADDCA,Rr
Add register to A
with carry
ADDCA,@Rr
Add data memory
to A with carry
ADDC A, #data Add immediate
to A with carry
ANLA, Rr
AND register to A
ANL,A@Rr
AND data memory
toA
ANLA, #data
AND immediate to A
ORLA, Rr
OR register to A
ORL,A,@Rr
OR data memory
toA
ORLA, #data
OR immediate to A
XRLA, Rr
Exclusive OR regis·
terto A
XRLA, @Rr
Exclusive OR data
memory to A
XRLA. #data
Exclusive OR imme·
diate to A
INCA
IncrementA
Decrement A
DECA
CLRA
Clear A
CPLA
Complement A
Decimal Adjust A
DAA
SWAP A
Swap nibbles of A
Rotate A left
RLA
RLCA
Rotate A left through
carry
RRA
Rotate A right
RRCA
Rotate A right
through carry
INPUT/OUTPUT
INA,Pp
Input port to A
OUTLPp,A
Output A to port
ANL Pp, #data AND immediate to
port
ORL Pp, #data OR immediate to
port
INA,DBB
Input DBB to A,
clearlBF
OUTDBB,A
Output A to DBB,
setOBF
MOVSTS,A
~ -A7 to Bits 4-7 of
Status
MOVDA,Pp
Input Expander
port to A
MOVDPp,A
Output A to
Expander port
ANLDPp,A
AND A to Expander
port
ORLDPp,A
OR A to Expander
port
Bytes
Cycles
Mnemonic
1
1
1
1
DATA MOVES
MOVA,Rr
MOVA,@Rr
2
2
1
1
1
1
2
2
1
1
1
1
2
2
MOV@Rr,
# data
MOVA,PSW
MOVPSW,A
XCHA, Rr
1
1
1
1
XCHA,@Rr
2
2
XCHDA,@Rr
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
2
1
2
1
2
1
2
MOVA, #data
MOVRr,A
MOV@Rr,A
MOV Rr, #data
MOVPA,@A
MOVP3,A,@A
Description
Bytes
Cycles
Move register to A
Move data memory
toA
Move immediate to A
Move A to register
Move A to data '
memory
Move immediate to
register
Move immediate to
data memory
MovePSWtoA
MoveAtoPSW
Exchange A and
register
Exchange A and
. data memory
Exchange digit of A
and register
Move to A from
current page
Move to A from
page 3
1
1
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TIMER/COUNTER
Read Timer/Counter
MOVA,T
Load Timer/Counter
MOVT, A
STRTT
Start Timer
Start Counter
STRTCNT
Stop Timer/Counter
STOP TCNT
EN TCNTI
Enable Timer/
Counter Interrupt
DIS TCNTI
Disabie Timer/
Counter Interrupt
CONTROL
ENDMA
ENI
DIS I
EN FLAGS
SELRBO
SELRB1
NOP
REGISTERS
INCRr
INC@Rr
DECRr
9-71
Enable DMA Hand·
shake Lines
Enable IBF Interrupt
Diable IBF Inter·
rupt
Enable Master
Interrupts
Select register
bank 0
Select register
bank 1
No Operation
Increment register
Increment data
memory
Decrement register
inter
UPI-41/42
Table 2. UPITM Instruction Set (Continued)
Mnemonic
Description
Bytes
Cycles
Jump to subroutine
Return
Return and restore
status
2
1
1
2
2
2
Clear Carry
Complement Carry
Clear Flag 0 .
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
1
1
1
1
1
1
1
1
1
1
1
1
Jump unconditional
Jump indirect
Decrement register
and jump
"
Jump on Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump on TO = 1
Jump on TO =
20
0 .'8
700
100
ns
100 pF Load
ns
650
ns
80 pF Load
TEST POINTS
0.45 _ _ _- J
231317-3
9-75
8243
WAVEFORMS
PROG
~~--
PORT 2
__________
~_'K
________________
~
FLOAT
FLOAT
PORT2
PORTS 4·7
PREVIOUS OUTPUT VALID
PORTS 4·7
INPUT VALID
les
'OUTPUT
VALID
les
231317-4
9-76
inter
8243
125
100
C
!
::l
9
~
...
..
..
75
Z
II:
II:
:;)
U
Z
iii
....
50
GUARANTEED WORST CASE
CURRENT SINKING CAPABILITIES
OF ANY 1/0 PORT PIN '". TOTAL
SINK CURRENT OF ALL PINS
j!
...0
25
13
MAXIMUM SINK CURRENT ON ANY PIN @ .45Y
MAXIMUM 10L WORST CASE PIN (mAl
231317-5
Figure 3
Example: This example shows how the use of the
20 mA sink capability of Port 7 affects the
sinking capability of the other 110 lines.
Sink Capability
The 8243 can sink 5 mA @ 0.45V on each of its 16
110 lines simultaneously. If, however, all lines are
not sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line increases as is shown by the accompanying curve.
An 8243 will drive the following loads
simultaneously.
2 loads-20 mA @ 1V (port 7 only)
8 10ads-4 mA @ 0.45V
6 loads-3.2 mA @ 0.45V
For example; if only 5 of the 16 lines are to sink
current at one time; the curve shows that each of
those 5 lines is capable of sinking 9 mA @ 0.45V (if
any lines are to sink 9 mA the total IOL must not
exceed 45 mA or five 9 mA loads).
Example: How may pins can drive 5 TTL loads
(1.6 mAl assuming remaining pins are unloaded?
Is this within the specified limits?
EIOL = (2 x 20) + (8 x 4) + (6 x 3.2)
= 91.2 mAo From the curve: fot IOL =
4 mA, EIOL :::: 93 rnA. Since 91.2 mA <
93 mA the loads are within specified limits.
Although the 20 mA @ 1V loads are used
in calculating EIOL, it is the largest currerit
required @ 0.45V which determines the
maximum allowable EIOL.
IOL = 5 x 1.6 mA = 8 mA
ElOL = 60 mA from curve
# pins = 60 mA + 8 mA/pin = 7.5 = 7
In this case, 7 lines can sink 8 mA for a
total of 56 inA. This leaves 4 mA sink current capability which can be divided in any
way among the remaining 8 110 lines of
the 8243.
NOTE:
A 10 Ko, to 50 Ko, pull up resistor to + 5V should
be added to 8243 outputs when driving to 5V
CMOS directly.
9-77
inter
8243
Figure 4. Expander Interface
P20·P23
--{I..._--IX'-___..J)>--ADDRESS (4-8IT5)
DATA (4·8IT51
231317-7
Figure 5. Output Expander Timing
11048
PORT 2
PROG~--------------~----------------~------~--------~--~------------~
231317-8
Figure 6. Using Multiple 8243'5
9-78
June 1985
Applications Using the
8042 UPI™ Microcontroller
1. The 8042 in the IBM PC/AT
2. Using the 8042 vs. using microcontrollers
3. Custom serial protocol with the 8042
Order Number: 231600-001
9-79
8042 UPI™ MICROCONTROLLER
APPLICATION #1
THE 8042 UPI™ MICROCONTROLLER IN THE IBM PC/AT
The following example is an important application of U PIs but there are many more. It is truly a universal device that can
be customized to all those "non-standard peripheral control problems. Applications are limited only by imagination.
Think UPIs for non-standard peripherals!!
M
... IBM PC/AT (AFTER)
IBM PC/AT (BEFORE) ...
8042
KEYBOARD
KEYBOARD
NEW FUNCTIONS
THE FUTURE IS THE KEY
The 8042 also brings new functions to the PC/AT:
Modifications and upgrades are easy because of the
8042's programmable flexibility and power:
•
•
•
•
•
•
•
Keyboard lockup security (front panel key)
CRT type input to the system
Diagnostics/ self testing of keyboard interface
Parity check and retry
PC and PC/AT keyboard interchangeability
Reset CPU to compatible mode
Address wrap-around protect in compatible
mode
•
•
Change keyboard scan codes (in 8042 ROM)
Increase functionality of keyboard interface
through software and/ or unused I/O lines on
8042
•
Control other PC/AT functions with these I/O
lines
Summary
In short, IBM used the 8042 since it:
•
•
•
•
Offloads housekeeping details from the CPU
Facilitates modular system design
Offers a customized peripheral
Provides a clean, efficient upgrade path
These benefits can apply to many of your applications
also.
.
9-80
8042 UPI'M MICROCONTROLLER
APPLICATION #2
USING THE 8042 VS. USING MICROCONTROLLERS
PROBLEM
WHY THE SWITCH
What do you db when you're making SBX and VME
modules for a voice digitizing board and you need:
After studying the four requirements for this module, it
is easy to see why they switched. The first two (A/ D
interface and 12 MHz) were met by both solutions.
However, it is clear the second alternative is much
better on board space and on overall cost. There are
fewer chips, so they could avoid a multi-layer board
and thus save a lot in total cost. Actual chip costs are
within 10% of each other (a typical microcontroller like
a Z8 or 6801 plus 2 latches compared to an 8042), and
they do the same thing.
I)
2)
3)
4)
an interface to an A/ D Converter with
12 M Hz operation,
an absolute minimum chip count, and
very low cost (for the PC market).
A leading vendor was faced with exactly this problem.
Here is what they started with, and the bottom figure
shows how they improved things with the 8042 UP!'"
microcontroller.
SOLUTION
WHAT'S THE DIFFERENCE
People tend to think of microcontrollers whenever
there is a "non-standard" device to control. CRTs, disk
drives and DRAMs all have dedicated controllers, but
printers, front panels, displays and keyboards don't,
because they are all "non-standard" devices. Microcontrollers can be customized to these applications.
BEFORE .. .
SYSTEM
The problem is when the device is a "slave" or a
peripheral, regular microcontrollers need the extra circuitry shown previously. That's why we invented U Pis.
They are simply microcontrollers with the slave interface built in. They are, therefore, more efficient to use
in peripheral-type configurations.
UPI
SLAVE INTERFACE
MICROPHONE
AFTER .. .
SYSTEM
MICROCONTROLLER
UPls may be misunderstood because of the funny
name. They shouldn't be. It's really simple. When faced
with non-standard device control, think microcontrollers.
If it's a master-only configuration, think regular microcontrollers. If it's a slave/peripheral configuration, think
UPls.
MICROPHONE
The 8042 integrates two latches and the microcontroller
into a single-chip solution.
9-81
8042 UPI™ MICROCONTROLLER
APPLICATION #3
.
CUSTOM SERIAL PROTOCOL WITH THE 8042 UPI™ MICROCONTROLLER
BACKGROUND
The 8042 UPI Microcontroller, because of its programmability is being used everywhere, and here is another
example. A leading board vendor was designing a
communications concentrator board. They wanted a
way to:
CPU would have caused tremendous system performance degradation. They needed all of these features to
offer a competitive product, so they looked to the 8042
UPI Microcontroller. Since the speed requirements were
not too great (4800 baud), they could implement the
protocol in software. The 8042's programmability gave
them all the flexibility needed to incorporate the formatting, handshaking and error checking desired. Moreover, the on-chip slave interface made communication
with the minicomputer's bus a snap.
I) interface 8 serial channels to a minicomputer bus
2) operate these at 4800 baud
3) use one board
4) provide a custom serial protocol that
--,- communicated commands and data packets
- assembled the data packets
- provided handshaking signals
- checked for framing, timing, parity, noise,
modem and synchronization errors
- provided self-test diagnostics
SUMMARY
In short, the 8042 allowed this company to implement
a custom serial communication protocol that in turn
allowed them to offer a customized, competitive interface board to their customers.
THE 8042 SOLUTION
There certainly wasn't an "off-the-shelf' chip that would
satisfy the above requirements, and using the main
.. Don't some of your applications need customized
interfaces?
9-82
inter
APPLICATION
AP-161
NOTE
November 1986
Complex Peripheral Control with
the UPI-42AH
CHRISTOPHER SCOTT
TECHNICAL MARKETING ENGINEER
Order Number: 230795-002
9-83
intJ
AP-161
Until recently, the dedicated control processor approach was usually not cost effective due to the large
number of components needed; CPU, RAM, ROM,
I/O, and Timer/Counters. To help make the approach
more cost effective, in 1977 Intel introduced the UPI41 family of Universal Peripheral Interface controllers
consisting of an 8041AH (ROM) device and an
8741AH (EPROM) device. These devices integrated
the common microprocessor system functions into one
40 pin package. The UPI-42AH family, consisting of
the 8042 and 8742AH, further extends the UPI's cost
effectiveness through more memory and higher speed.
INTRODUCTION
The UPI-42AH represents a significant growth in UPI
capabilities resulting in a broader spectrum of applications. The UPI-42AH incorporates twice the EPROM/
ROM of the UPI-41AH, 2048 vs 1024 bytes, 256 bytes
of RAM, and operates at a maximum speed twice that
of the UPI-41AH, i.e., l2MHz vs 6MHz. The ROM
based 8042 and the EPROM based 8742AH provide
more highly integrated solutions for complex stepping
motor and dot matrix printer applications. Those applications previously requiring a microprocessor plus a
UPI chip can now be implemented entirely with the
UPI-42AH.
Another member of the UPI family is the Intel 8243
Input/Output Expander chip. This chip provides the
UPI-41AH and UPI-42AH with up to 16 additional
independently programmable I/O lines, and interfaces
directly to the UPI-41AH/42AH. Up to seven 8243s
can be cascaded to provide over 100 I/O lines.
The software features of the UPI-42AH, such as indirect Data and Program Memory addressing, two
independent and selectable 8 byte register banks, and
directly software testable I/O pins, greatly simplify the
external interface and software flow. The software and
hardware design of the UPI-42AH allows a complex
peripheral to be controlled with a minimum of external
hardware.
aST 0
Vee
XTAll
TFST 1
XTAl'
P27 OACK
RFSfT
P26 ORO
SS
cs
,.
The UPI is a single chip microcomputer with a standard microprocessor interface. The UPI's architecture,
illustrated in Figure 3, features on-chip program memory, ROM (8041A/8042) or EPROM (8741A/
8742AH), data memory (RAM), CPU, timer/counter,
and I/O. Special interface registers are provided which
enable the UPI to function as a peripheral to an 8-bit
central processor.
'
Using one of the UPI devices, the designer simply codes
his proprietary peripheral control algorithm into the,
UPI device itself, rather than into the main system software. The UPI deVice then performs the peripheral
control task while the host processor simply issues
commands and transfers data. With the proliferation of
microcomputer systems, the use of UPls or slave microprocessors to off load the main system microprocessor has become quite common.
P25 IBF
P24 oaF
P17
RO
p,.
AO
P,s
WR
p,.
SYNC
P13
DO
P"
0,
P"
02
P,o
03
Voo
D.
PROG
Os
P23
Os
P22
07
P2'
V55
P20
This Application Note describes how the UPI-42AH
can be used to control dot matrix printing and the
printer mechanism, using stepper motors for carriage/
print head assembly and paper feed motion. Previous
Intel Application Notes AP-27, AP-54, and AP-9l describe using intelligent processors and peripherals to
control single solenoid driven printer mechanisms with
80 character line buffering and bidirectional printing.
This Application Note expands on these previous
themes and extends the concept of complex device control by incorporating full 80 character line buffering,
bidirectional printing, as well as drive and feedback
control of two four phase stepper motors.
230795-1
Figure 1. UPI-42AH Pin Configuration
The Application Note assumes that the reader is familiar with the 8042/8742AH and 8243 Data Sheets, and
UPI-41AH/42AH Assembly Language. Although
some background information is included, it also assumes a basic understanding of stepper motors and dot
matrix printer mechanisms. A complete software listing
is included in Appendix A.
Many microcomputer systems need real time control of
peripheral devices such as a printer, keyboard, complex
motor control or process control. These medium speed
but still time consuming tasks require a fair amount of
system software overhead. This processing burden can
be reduced by using a dedicated peripheral control
processor.
9-84
AP-161
INT(IlNAL
'"'
'"
PORT 1
WASHR
SrSTE ...
INTERfACE
l~,~
DAU
MUoilORY
"
E
"
CONTROL
lOGIC
P£RIPHERAl
IHTERH.C£
k======-
';0
PORT 2
POIlT4-1
UP"'NO£R
ItHERfAC(
lK • H ,K •
~
PIIOM AO""
NIOGR ... '"
"'f"'OA'
CRYSUL
LCOR
CLOCK
'00 -
POWE"
{
_ _ PROM PROGAA ...
SUPPL~
vee _ _ _ "'5 SUPPLY
' " - - - GROUND
8·81T
TIMER
E~ENT
COUNTER
230795-2
Figure 2. UPI-42AH Block Diagram
main CPU, UPI, RAM, ROM, and I/O onboard the
peripheral. The CPU acted as supervisor and used parallel processing to achieve accurate stepper motor control via a UPI, character buffering via the I/O device,
RAM, and ROM. The CPU performed real-time decoding of each character into a dot matrix pattern. This
Application Note demonstrates that the increased
memory and performance of the UPI-42AH facilitates
integrating these control functions to reduce the cost
and component count.
DOT MATRIX PRINTING
A dot matrix printer print head typically consists of
seven to nine solenoids, each of which drives a stiff
wire, or hammer, to impact the paper through an inked
ribbon. Characters are formed by firing the solenoids to
form a matrix of "dots" (impacts of the wires). Figure 4
shows how the character "E" is formed using a 5 X 7
matrix. The columns are labeled Cl through C5, and
the rows Rl through R7. The print head moves left-toright across the paper, so that at time Tithe head is
over column Cl. The character is formed by activating
the proper solenoid as the print head sweeps across the
character position.
THE PRINTER MECHANISM
The printer mechanism used in this application is the
Epson Model 3210. It consists of four basic sub-assemblies; the chassis or frame, the paper feed mechanism
and stepper motor, the carriage motion mechanism and
stepper motor, and the print head assembly.
Dot matrix printers are a cost effective way of providing good quality hard copy output for microcomputer
systems. There is an ever increasing demand for the
moderately priced printer to provide more functionality
with improved cost and performance. Using stepper
motors to control the paper feed and carriage/print
head assembly motion is one way of enabling the dot
matrix printer to provide more capabilities, such as expanded or contracted characters, dot or line graphics,
variable line and character spacing, and subscript or
superscript printing.
The paper feed mechanism is a tractor feed type. It
accommodates up to 8.5 inch wide paper (not including
tractor feed portion). There is no platen as such; the
paper is moved through the paper guide by two sprocketed wheels mounted on a center sprocket shaft. The
sprocket shaft is driven by a four phase stepper motor.
The rotation of the stepper motor is transmitted to the
sprocket shaft through a series of four reduction gears.
However, stepper motors require fairly complex control
algorithms. Previous solutions involved the use of a
9-85
intJ
AP-161
l
CLOCK
J
! !
1024 • 8, 2048 • 8
PROGRAM
MEMORV
(ROM/EPROM)
8-BITCPU
I
I
64.8,128.8
DATAMEMORV
II
JI
"
"
8-BIT
DATA BUS
INPUT REGISTER
I
8-BIT
TIMER/COUNTER
8-BIT
DATA BUS
OUTPUT REGISTER
8-BIT
STATUS
REGISTER
II
II
18
I/O LINES
PERIPHERAL INTERFACE
AND
I/O EXPANSION
SYSTEM
INTERFACE
230795-3
Figure 3. UPI-41AH, 42AH Functional Block Diagram
Cl
C2
C3
The carriage motion mechanism consists of another
four phase stepper motor which controls the left-toright or right-to-Ieft print head assembly motion. The
print speed is 80 CPS maximum. Both the speed of the
stepper motor and the movement of the print head' assembly .are independently controllable in, either direction. The rotation of the stepper motor is converted to
the linear motion ofthe print head assembly via a series
of reduction gears and a toothed drive belt. The drive
belt also controls a second set ofreduction gears which
advances the print ribbon as the print head assembly
moves,
CS
Rl
R2
R3
DODD
00'00
Two optical sensors provide feedback information on
the carnage assembly position and speed. The first of
these optical sensors, called the 'HOME RESET' or
HR, is mounted near the left-most physical position to
which the print head assembly can move. As the print
head assembly approaches the left-most position, a
flange on the print head assembly interferes with the
light source and sensor, causing the output of the sen"
sor to shift from a logic level one to zero. The rightmost printer position is monitored in software rather
than by another optical sensor. The right-most print
position is a function of the number of characters printed and the distance required to print them.
R4
RS
R6
0'000
DODD
R7
The second optical sensor, called the '·PRINT TIMING SIGNAL' or PTS, provides feedback on carriage
stepper motor velocity and relative position within a
230795-4
Figure 4. Character E in 5 x 7 Dot Matrix Format
9-86
inter
AP-161
STEPPER MOTOR
~
STEPPER MOTOR
FRAME
REDUCTION GEARS
230795-5
Figure 5. Carriage Stepper Motor Assembly
given step of the motor. The feedback is generated by
the optical sensor as an "encoder disk" moves across it.
Figure 5 illustrates the carriage stepper motor, optical
sensor, encoder disk and reduction gears, and drive belt
assembly. The optical sensor outputs a pulse train with
the same period as the phase shift signal used to drive
the stepper, but slightly out of phase with it when the
motor is at a constant speed (see Software Functional
Block: Phase Shift Data for additional details). The
disk acts as a timing wheel, providing feedback to the
UPI software of the carriage speed, position, and optimum position for energizing the print head solenoids.
The two optical sensors are monitored under software
and provide the critical feedback needed to control the
print head assembly and paper feed motion accurately.
The process of stepper motor drive and control via
feedback signals is called "closed loop" stepper motor
control, and is covered in more detail in the software
discussion.
to print a variety of character fonts, such as expanded
or contracted characters, as well as line or block graphics (see Appendix B, Printer Enhancements). It also
facilitates printing lower case ASCII characters with
"lower case descenders." That is to say, certain lower
case letters (e.g., y, p, etc.) will print below the bottom
part of all upper case letters.
DOT WIRE
!
MAGNETIC POLE
The print head assembly consists of nine solenoids and
nine wires or hammers. Figure 6 illustrates a print head
assembly. The available dot matrix measures 9 x 9. This
large matrix enables the Epson 3210 print mechanism
MAGNET
230795-6
Figure 6. Print Head Solenoid Assembly
9-87
inter
•
AP-161
EXTERNAL -----".. P60.62; 63
P70-73
s!T~~~~s
0'5V
0
~~
a:
.....
"''''
w'"
::>'"
In
r
~
Ii:
~
P20_23
1J
1\
~
-I
T,O
~
~
0
~ w'"
r
\
vi
CONTROL: P50-53
(CURRENT LIMITING)
-\
-V
PRINT
MECHANISM
DRIVE
CIRCUIT
PROG
I
PT3 OPTICAL SENSOR
Tl
WR
r--
a:
~
....
VI
P40-43
HR OPTICAL SENSOR
UPI·42
Il.
DATA STROBE
P20-23
PROG
0
...
......w
..:
STEPPER MOTOR
CONTROL
8243
ON LINE/SELECT
r--
~~
---vI
a:
.....
"''''
~
~
P24
PRINT HEAD TRIGGER
P27
P25
Pl0-17
::>'"
PRINT HEAD SOLENOID DATA
In
P26
~
\
-I
230795-8
Figure 7. Hardware Interface Block Diagram
Application Note followed those recommendations exactly (see Appendix C, Printer Mechanism Drive Circuit Schematics).
HARDWARE DESCRIPTION
Figure 7 shows a block diagram of the UPI-42AH and
8243 interface to the printer mechanism drive circuit. A
complete schematic is shown in Figure 8. The
UPI-42AH provides all signals necessary to control
character buffering and handshaking, paperfeed and
carriage motion stepper motor timing, print head solenoid activation, and monitoring of external status
switches.
I/O Ports
The lower half of the UPI-42AH Port 2, pins 0-3, provides an interface to the 82431 I/O expander. The
PROG pin of the UPI-42AH is used as a strobe to
clock address and data information via the Port 2 interface. The extra 16 I/O lines of the 8243 become
PORTS 4,5,6, and 7 to the UPI software. Combined,
the UPI-42AH and 8243 provide a total of 28 independently programmable I/O line. These lines are used as
shown in Figure 9.
The Epson 3210 printer mechanism manual recommends a specific interface circuit to provide proper
drive levels to the stepper motors windings and print
head solenoids. The hardware interface used for this
9-88
inter
AP-161
...
-
'-1'1'- J > - - - - -
"b
\(5'
0 .. 0"
.\. (".,
S!~~~~~5
IllG'
(.O .... !Cl0~
~il·"'·I·:~
~
,
~
"'&r- a •
"
"
' - -_ _J
u ..
'~:--"----------~
Mom
.;31111
La
1l2COl
I
CUAAENT
l'IoIIHA
ell so.
0" '"'N"~/
(FLOWCHART oS)
,"OCESS CH"AC""S
TRANSLATE CHARACTERS-TO-OOlS
(FLOWCHART "9)
(
.
.
/
>t"E ,",", HEAD
SOLE:OIO TRIGGER
N 'T
[OlH
/
I
PAPER FE EO STEPPER MOTOR CRIVI'.
(FLOWCHART" III
~
X--
/
CAR"'AGE ST""" I /
MOTOR ACCELERATION
nME STORAGE
(FLOWCHART 07)
~
N
>
DECHE"A" CA""'AGE /
STEPPER MOTOR
(FLOWCHART "10)
I
7
230795-15
Flow Chart No.1. Main Program Body
9-95
inter
AP-161
Upon power-on reset, a software and hardware initialization is perfonned. This stabilizes and sets inactive the
printer hardware and electronics. The print head assembly is then moved to establish its HOME position.
The default status registers are set for character buffering, carriage, and paper feed stepper motor drive. The
.External Status switches are checked; FORMFEED,
LINEFEED, ON/OFF LINE, and Character Print
TEST. If the printer is ON LINE; the software will
loop on filling the Data Memory Character Buffer.
Memory and Register Allocation
DATA MEMORY ALLOCATION (RAM)
The UPI-42AH has 256 bytes of Data Memory. Sixteen
bytes are used by the two 8 byte register banks (RBO
and RBI). Sixteen additional bytes are used for the Program Stack. The Stored Time Constants utilize 11
bytes, while the stepper motor phase storage requires 4
bytes. Below is a detailed description of Data and Program Memory.
Character or data input to the UPI-42AH is interrupt
driven. Characters sent by the host system set the Input
Buffer Full (IBF) interrupt and the IBF Program
Status flag. Character input servicing (completed during the paper feed and carriage stepper motor drive end
Delay subroutine) tests for various ASCII character
codes, loads characters into the Character Buffer (CB),
and repeats until one of several conditions sets the CB
Full status flag. Once the CB Full flag is set, further
character transmission by the host system is inhibited
and printing can begin.
Hex Address
2F-7FH
Description
r----...,
SO Character Line Buffer
(SO Bytes)
2S':'2EH
1-----1
Stored Time Constants Buffer
(11 Bytes)
The carriage stepper motor is initialized, and drive begins for the direction indicated. The motor is accelerated to constant speed, printable character codes are
translated to dot patterns and printed (if printing is
enabled), and the motor is decelerated to a stop. Two
timing loops guarantee both constant speed and protection (Failsafe Time) against stepper motor burn out due
to high current overload. The two optical sensors, described in the Printer Mechanism section above, are
constantly monitored to maintain constant speed, and
trigger print head solenoid firing.
24H
1-----1
Unused
23H
1-----1
Character Print Test ASCII Code
Start Temporary Storage
22H I - - - - l Pseudo Register: Paperfeed Stepper
Motor Last Phase Indirect Address
21 H I----'--l Pseudo Register: Carriage Stepper
Motor Forward/Reverse Last Phase
Once the line is printed and the carriage stepper motor
drive routine has been completed, a Linefeed is forced.
The paper feed stepper motor drive subroutine tests the
number of lines to move, and energizes the paper feed
stepper motor for the required distance. The lines per
page default is 66; if 66 lines have been received, a
Fonnfeed to Top-of-Next-Page is perfonned. The TopOf-Page is set at Power On/Reset.
20H
1-----1
Pseudo Register: Last Phase of
lS-l FH
1-----1
Register Bank 1:
Stepper Motor Not Being Driven
Character ProceSSing
S-17H
When the EOF code is received, the EOF status flag is
set. When the last line has been printed, the EOF check
will force the print head assembly to the HOME position. The EOF flag is tested following each paperfeed
stepper motor drive. The next entry to the External
Status Check subroutine begins a loop which waits for
input from either the external status switches or the
host system.
0-07H
S Level Stack
1-----1
Register Bank 0: Stepper Motor
Forward/Reverse
Acceleration/Drive
Figure 19. Data Memory Allocation Map
The software character dot matrix used in this application is 5 x 7 of the available 9 x 9 print head .solenoid
matrix. Although lower case descenders and blocklline
graphics characters are not implemented, Appendix B,
Printer Enhancements, discusses how and where these
enhancements could be added. The software imple. ments the full 95 ASCII printable characters set.
Register Bank 0 is used for stepper motor drive functions. Register Bank 1 is used for character processing.
Each register bank's register assignments is listed in
Figures 20 and 22, respectively. Each register bank has
one register allocated as a Status Register. Figures 21
and 23 detail the Status Register flag assignments. Note
9-96
inter
AP-161
that bit 7 of each Status Byte is used as a print head
assembly motion direction flag. This saves coding of the
Select Register Bank (SEL RBn) instruction at each
point the flag is checked.
Bit
Definition
CB Registers: 1::: Initialize
10="00 Not Initialize,
1~CR/(LF)/Oo Not CR/(LF)
Character Buffer
Fullo 1/Not FulioO.
1° EOF/O~ Not EOF
(unused)
Register Bank 0
Program
Register
Label
Description
RO
R1
R2
R3
R4
R5
R6
R7
TmpROO
TStrRO
GStR20
PhzR30
CntR40
TConRO
LnCtRO
OpnR70
L..._ _ _ _ _ _ Character Lookup Table Page:
RBO Temporary Register
Store Time Register
General Status Register
Stepper Motor Step Register
Count Register
Time Constant Register
Line Count Register
Available, Scratch
1o Pg. 1, OoPg. 2
Character Initialized,
1;: Done/O= Nol Done
' - - - - - - - - - Camage Stepper Motor Direction
L-to-R 1. R-to-LoO
230795-17
Figure 23. Register Bank 1 Status Byte Flag
Assignments
Figure 20. Register Bank 0 Register Assignment
PROGRAM MEMORY ALLOCATION
(EPROM/ROM)
Bit
Definition
The UPI-42AH has 2048 bytes of Program Memory
divided into eight pages, each 256 bytes. Figure 24 illustrates the Program Memory allocation map by page.
Accel/Oecelerale Drive
Ready l/NotRdy 0
1 Do Not PnntlO Print
1 Form FeedlO Line Feed
1 Fa.JSafe·Q Constant
Time Window
Aceel 'Deceleration Inlltaltzalton
1 Done/D Not Done
Stepper Motor at Speed and
Pnnt Head Not Left of Home
1 Sync/O· Not Sync"d. Print
Head Initialize and Fire
Stepper Motor Direction
L-to-R t R-to-L 0
Hex Address
Page 7
1792-2047
Character to Dot Pattern
Lookup Table; Page 2:
ASCII50H-7EH
Page 6
1536-1791
Charac1er to Dot Pattern
Lookup Table; Page 1:
ASCII 20H-4FH (sp-M)
Page 5
1280-1535
Miscellaneous Subroutines:
InitAll AIIOf!
Clear Data Memory
Home Print Head Assembly
Character Print Test
Initialize Carriage Stepper
Motor
Delay
Stepper Motor Deselect
Page 4
1024-1279
Paper Feed Stepper
Motor Drive
Page 3
768-1023
Stepper Motor Step LookUp
Table (I ndexed)
Character Processing and
Translation
Print Head Firing
Page 2
51-767
Carriage Stepper Motor
Acceleration
Time Calculation and
Storage
Stepper Motor Deceleration
Page 1
256-511
Carriage Stepper Motor Drive
Page 0
0-255
Initialization-Jump-on-Reset
Main Program Body
External Status Switch
Check
Character Buffer Fill
230795-16
Figure 21. Register Bank 0 Status Byte Flag
Assignments
Register
Program
Label Description
RO
R1
TmpR10
CAdrR1
R2
ChStR1
R3
R4
CDtCR1
CDotR1
R5
CCntR1
R6
R7
StrCR1
OpnR71
RBO Temporary Register
Character Data Memory
Address Register
Character Processing
Status Byte Register
Character Dot Count Register
Character Dot Temporary
Storage Register
Character Count Temporary
Register
Store Character Register
Available/Scratch
Figure 22. Register Bank 1 Register Assignment
Description
Page
Figure 24. Program Memory Allocation Map
9-97
intJ
Ap·161
storage locations for step data used in accurately reo.
versing the direction of the carriage stepper motor, and
stabilizing either of the stepper motors not being driven.
Software Functional Blocks
Below is a description and flow chart for each of the ten
software blocks listed.
The Data Memory locations OOH through lFH are not
cleared. These locations are Register Bank 0 (DOH07H), Program Stack (08H -17H), and Register Bank 1
(18H-IFH) (see Figure 19). Clearing the Program
Registers or Stack would cause the initialization subroutine to become lost. The registers are used from the
beginning of the program. Care is taken to initialize the
registers. and stack accurately prior to each program
subroutine as required.
1. Power-On/Reset Initialization
The first operational partin Flow Chart No. 1 is the
Power-On or Reset Initialization: Flowchart No. 2 il-·
lustrates the Initialization sequence in detail.
y
I
DISABLE INTERRUPTS
Upon power-on, it is necessary to initialize the two
stepper motors, verify their operation, and locate the
print head assembly in the left-most 'HOME' position.
This sequence serves as a system checkout. If a failure
occurs, the motors are deselected and the external
status light is turned on. Each stepper motor is selected
and energized for a sequence of four steps. This serves
to align and stabilize each stepper motor's rotor position, preventing the rotor from· skipping or binding
when the first drive sequence begins.
~
RESET PRINT HEAD TRIGGER
TURN OFF ALL PRINT HEAD SOLENOIDS
seT PRINT HEAD TRIGGER INACTIVE
SET HOST SYSTEM HANDSHAKE ACTIVE
CLEAR RBO/RB1 STATUS REGISTERS
+
I
I
CLEAR DATA MEMORY (20H-rFH)
t
INITIALIZE CARRIAGE ANO PAPER FEED STEPPER MOTORS.
1/
+
HOME PRINT HEAD ASSEMBLY
(FLOWCHART #4)
!
/
I
seT DEFAULT REGISTERS AND FLAGS
I
1
RETURN
I
At the end of each stepper motor's initialization, the
last step data address is stored in one ofthe Data Memory pseudo registers. The last step data address is recalled at the beginning of the next corresponding stepper motor drive sequence, and used as the basis of the
next step sequence. This ensures that the stepper motor
always receives the exact next step data, in sequence, to
guarantee smooth stepper motor motion. This also
guarantees the motor never skips or jerks, which would
misalign the start, stop, and character dot column positions. A stepper motor not being driven has its last
phase data output held constant to stabilize it.
I
,
230795-18
Following any stepper motor drive sequence of either
motor, a delay of 30-60 ms occurs by switching the
current to Hold Current, stabilizing the motor before it
is deselected.
Flow Chart No.2. Power-On/Reset Initialization
Initialization first disables both interrupts. This is done
as a precaution to prevent the system software from
hanging-up should an interrupt occur before the proper
registers and Data Memory values are initialized.
2. Home Print Head Assembly
At the end of the carriage stepper motor four step initialization, the output of the HR optical sensor is tested. The level of the HR signal indicates which drive
sequence will be required to 'HOME' the print head
assembly. If the print head assembly is to the right of
HR, HR is high, the print head assembly need only be
moved to from Right-to-Left until HR is low, then decelerated· to locate the physical home position. If HR is
low, the print head assembly must be moved first Leftto-Right until HR is high, then Right-to-Left to locate
both the logical and physical 'HOME' positions. In
each case, the software accelerates the carriage stepper
motor, generating the Stored Time Constants then decelerates the stepper motor using the Stored Time Con-
Initialization then deactivates the. system electronics.
This is also a precaution to protect the printer mechanism and includes the print head solenoid (trigger and
data) lines and the stepper motor select lines. The host
system handshake signals are activated to inhibit data
transfer from the host until the printer is ready to accept data.
Next, Data Memory is cleared from 20H to 7FH. This
includes the 80 byte Character Buffer, the 11 byte
Stored Time Constants buffer, and the 4 bytes used as
pseudo registers. The pseudo registers are Data Memory locations used as if they were registers. They serve as
9-98
AP-161
The flag is set by the subroutine which calls the Carriage Stepper Motor Drive subroutine. Details of the
carriage and paper feed stepper motor drive and character processing subroutines are covered separately below.
3. External Status Switch Check
Once the system is initialized and the print head is at
the HOME position, the software enters a loop which
continually monitors the four external status switches,
and exits if anyone is active. Flow Chart No.4 details
the External Status Switch Check subroutine.
Flow Chart No.4. External Status Switch Check
If the LINEFEED or FORMFEED switch is set, the
Paper Feed subroutine is called. The Paper Feed subroutine is discussed in detail below. If the ONLINE
switch is set, the Character Buffer (CB) Fill subroutine
is called.
230795-19
Flow Chart No.3. HOME Print Head Assembly
stants (see Background section above). Flow Chart No.
3 details the HOME print head assembly subroutine.
Figures 13 and 18 illustrate the components of accelera·
tion and print head assembly line motion.
If the Character Print TEST switch is set, the Data
Memory Character Buffer (CB) is automatically loaded
with the ASCII code sequence, beginning at 20H (a
Space character), the first ASCII printable character
code. The software then proceeds as if the CB had been
filled by characters received from the host system. The
The carriage stepper motor drive subroutines used to
HOME the print head assembly and to print, are the
same. A status flag, called Do· Not-Print, determines
whether the Character Processing subroutine is called.
CHARACTER BUFFER FILL
(FLOWCHART .. 5)
230795-20
Flow Chart No.4. External Status Switch Check
9-99
AP·161
External Status Switch Check subroutine is exited and
character printing begins. When the line has finished
printing, a linefeed occurs (as shown in the main program Flow Chart No.1) and the program returns to
the External Status Switch Check subroutine. If the
TEST switch remains active, the ASCII character code
is incremented and program continues as before. This
will eventually print all 95 ASCII printable characters.
An example of the TEST printer output, the complete
ASCII character code printed, is shown in Figure 25.
9
N~
I
I
ENABLE INTERRUPTS
!
<
INPUT BUFFER FULL
N
tV
4. Character Buffer Fill
"/N
CHARACTER BUFFER
INITIALIZATION DONE
The Character Buffer (CB) Fill subroutine is called
from three points within the main program; External
Status Switch subroutine, and the Delay subroutine following the carriage and paper feed stepper motor drive
subroutines. Flowchart No. 5 details the Character
Buffer Fill subroutine operation.
The approximate 80 ms total pre-deselect delay at the
end of each stepper motor drive sequence, 40 ms carriage and 40 ms paper feed stepper motor pre-deselect
delay, is' sufficient to load an entire 80 character line.
Half the CB is filled at the end of printing the current
line, and the second half is filled at the end of a paper
feed. There is no time lost in printing throughput due
to filling the character buffer.
Character input is interrupt driven. When the IBF interrupt is enabled, a transmitted character sets the IBF
interrupt and IBF Program Status flag. Three instructions make up the IBF interrupt service routine. This
short routine disables further interrupts, sets the BUSY
handshake line active, inhibiting further transmission
by the host, and returns. The subroutine can be executed at virtually any point in the software flow without
affecting the printer mechanism operation. Processing
of the received character takes place during one of the
three program segments mentioned above. The BUSY
line remains active until the character is processed by
the CB Fill subroutine.
l
9-100
t
END OF CHARACTER BUFFER
N
!'
<
I
,
>V--I
CHARACTER BUFFER PAO
SET EXIT FLAGS
LOAD CD WITH 20H
V
!N
I
ACKNOWLEDGE & READ CHARACTER
<
t
ASCII
PR~NTABlE CHARACTER ~
<
I
INITIALIZE CHARACTER
BUFFER FILL
I
DECREMENT CHARACTER
BUFFER SIZE
<
N
I
LOAD CHARACTER INTO
CHARACTER BUFFER
>1
' CR OR LF
LOAD CB WITH CR
seT CB PAD FLAG
ENABLE INTERRUPTS
REAO NEXT CHARACTER
ASSUME IT 5 IF & IGNORE
<
EO'
N
>v---t
SET EOF & CD FUll FLAGS
CLEAR CD PAD FlAG
~
l
<
FORMFEEO
/N
I
RETURN
I
>vt
SET FF & CB FULL FLAGS
CLEAR CB PAD FLAG
I
The CB is 80 bytes from the top of Data Memory
(30H-7FH). It is a FIFO for forward, left-to-right
printing, and a LIFO for reverse, right-to-left, printing.
Loading the CB always begins at the top, 7FH. One
character may be loaded into the buffer each time the
CB Fill subroutine is called. .
The CB is always filled with 80 bytes of data prior to
printing. If the total number of characters input up to a
Carriage Return (CR)/Linefeed (LF), does not completely fill the CB, the CR code is loaded into the CB
and the balance of the CB is padded with 20H (Space
Character) until the CB is full. A Linefeed (LF) character following a Carriage Return is ignored. A LF is
always forced at the end of a printed line. When the CB
is full, the CB Full status byte flag is set and printing
can begin.
V,
LOAD CB WITH 20H
t
RETURN
I
I
DECREMENT CB ADDRESS
t
CO FULL OR
CO PAD
'\.
RETURN
V
I
•N
I
ENABLE INTERRUPTS
l
RETURN
I
I
230795-21
Flow Chart No.5. Character Buffer Fill
I
I-
AP-161
) ...
t
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I
230795-22
Figure 25. ASCII Character Code TEST Output and Print Example
A LF character alone is treated as a CR/LF at the end
of a full 80 character line. This is a special case of a
printed line and is handled during character process.ing
for printing (see No.7, Processing Characters for Pnnting, below). A Formfeed (FF) character sets the FF
status byte flag. The flag is tested at each paper feed
stepper motor drive subroutine entry.
When the software is available to load the CB with a
character, entry to the CB Fill subroutine checks three
status flags; CB Full, CB Pad, and IBF flag. If the CB
Full flag is set, the program returns without entering
the body of the CB Fill subroutine. The CB Pad flag
will cause another Space character to be loaded, If the
IBF flag is not set, the program returns. If the IBF flag
is set, the character is read from the Data Bus Buffer
register, tested for printable or nonprintable ASCII
code, and, if printable, loaded into the CB. If the character is a non-printable ASCII code and not an acceptable ASCII control code (CR, LF, FF, EOF), a 20H
(Space Character) is loaded into the CB.
Exiting the CB Full subroutine with the CB Full or CB
Pad flag set does not re-enable IBF interrupts or reset
the BUSY line. If neither of these flags is set, exiting
the CB Fill subroutine sets BUSY inactive and IBF
interrupts are enabled. Once the CB Full status byte
flag is set, IBF interrupts are disabled until the CB has
been entirely emptied, the line printed, or the system
Reset.
5. Carriage Stepper Motor Drive and Line
Printing
The carriage stepper motor drive subroutine controls
both L-to-R and R-to-L print head assembly motion.
Upon entering the subroutine, the HR signal level is
tested to determine the direction of print head assembly
motion and the Direction status flag is set. The default
control register values are loaded and balance of the
default status flags are set for stepper motor control
and character processing. The default control register
values include PT and the step sequence look-up table
start address for the direction indicated.
The direction flag is tested throughout the carriage
stepper motor drive and character processing subroutines. This enables the same subroutines to control activities for either direction, simplifying and shorting the
overall program. Flow Chart No.6 illustrates the carriage stepper motor drive subroutine.
AP-161
TIMER WITH PT
"'' $11 .....P(ALOAD
F[ED LAST STEP & CARRIAGE
"EXT STEP DAtA
OUlltUT sn, OAT.
S1AIftT'''A
230795-23
Flow Chart No.6. Carriage Stepper Motor Drive/Line Printing
9-102
inter
AP-161
Next, the carriage and paper feed stepper motor step
data is initialized. The last step data output to the paper
feed stepper motor is loaded into the Last Phase pseudo
register. This data is masked with each step data output
to the carriage stepper motor. Masking the step data in
this manner guarantees the paper feed motor signals do
not change as the carriage stepper motor is being driven.
Figure 26 illustrates the carriage stepper motor· step
sequence verses the actual step data output for clockwise rotation, Left-to-Right motion, and counterclockwise rotation, Right-to-Left print head assembly motion. An eight step sequence is depicted in the figure.
Note that the sequence for Right-to-Left motion is the
reverse of the sequence for Left-to-Right motion. Note
also, that for the L-to-R sequence step 4 is the same as
step 0, step 5 the same as step 1, etc., through step 7
matching step 3. The four step sequence simply repeats
itself until the motor is stopped via the Deceleration
subroutine.
L-to-R
Motion
Sequence
Phase/Step
Data
(321 0)
R-to-L
Motion
Sequence
0
1
2
3
1001
1010
0110
0101
7
6
5
4
0000
0001
0010
0011
4
5
6
7
1001
101 0
0110
0101
3
0100
0101
0110
01 1 1
2
1
0
BCD
(321 0)
Figure 26, at location 0 the step data "1001" is stored.
This method is particularly well suited to the
UPI-42AH software. The UPI-42AH features a number of instructions which perform an indirect move or
data handling operation. One of these instructions,
MOVP3A,@A, unlike the others, allows data to be
moved from Page 3 of Program Memory to any other
page of Program Memory. This instruction allows the
step data to be centrally located on Page 3 of Program
Memory and accessed by various subroutines.
Each time the carriage stepper motor step data is output, the step data lookup table address is incremented
or decremented, depending upon the direction of rotation, and tested for restart of the sequence. The address
is tested because the actual step data, Figure 26, is not a
linear sequence and thus is not an easily testable condition for restarting the sequence. The sequence number
is tested for rollover of the sequence count from 03H to
04H and clockwise motor rotation via the Jump on Accumulator Bit instruction (JBn), with OOH loaded to
restart the sequence. The same bit is tested when decrementing the sequence count for counterclockwise motor rotation, R-to-L motion, because the count rolls
over from OOH to OFFH, with 03H loaded to restart the
sequence.
At this point the UPI-42AH Timer/Counter is loaded,
the step signal is output, and the timer started. The
next step data to be output has been determined and the
At-Speed flag is tested for entry to one of two subroutines; Stepper Motor Acceleration Time Storage or
Character Processing.
Figure 26. Carriage Stepper Motor
Phase/Step Data
When the carriage stepper motor is driven for a specific
direction of print head assembly motion, the step sequence must be consistent for the motion to be smooth
and accurate. The same holds true for the transition
from one direction of motion to the other. Since the
sequence for one direction is the opposite for the other
direction, incrementing the sequence for L-to-R and
decrementing for R-to-L provides the needed step data
flow. For example, referring to Figure 26, if the print
head assembly moved L-to-R and the last step output
was # 1, the first step for R-to-L motion would be #7.
Thus, when the carriage stepper motor is initialized for
a clockwise (L-to-R) or counterclockwise (R-to-L) rotation, the last step sequence number is incremented or
decremented to obtain the proper next step. In this
way, the smooth motion of the stepper motors is assured.
The step data is referenced indirectly via the step sequence number. The step data is stored in a Program
Memory look-up table whose addresses correspond to
the step sequence numbers. For example, as shown in
The first entry to the Acceleration Time Storage subroutine initializes the subroutine and returns. All other
entries to one of the two subroutines perform the necessary operations, detailed below (Blocks 6 and 7), and
returns. The program loops until the PT times out or
the PTS level change is detected. PTS is tied to TO of
the UPI-42AH. The level present on TO is directly tested via conditional jump instructions. The software
loops on polling the timer Time Out Program Status
flag and the TO input level.
As described in the Background section above (shown
in Figure 13), if PT times out before PTS is detected,
the software waits for PTS before outputting the next
step signal. If PT times out before PTS, a second timer
count value is loaded into the UPI-42AH timer. The
timer value is called "Failsafe." This is the maximum
time the stepper motor can be selected, with no rotor
motion, and not damage the motor. If PTS is not detected, either the carriage stepper motor is not rotating
or the' optical sensor is defective. In either case, program execution halts, the motor is deselected, and the
external status light is turned on to indicate a malfunction. A system reset is required to recover from this
condition. The Failsafe time is approximately 20 milliseconds, including PT.
9-103
AP-161
The Failsafe time loop also serves as a means of tracking the elapsed time between PT time out and PTS.
Entry to the Failsafe time loop sets the Failsafe/Constant Time Window status flag. This flag is tested by
the Acceleration Time Storage subroutine for branching to the proper time storage calculation to be performed (see Figure 13 and Block 6 below for further
,description).
During the Failsafe timer loop, if PTS is detected and
verified as true, the Failsafe timer value is read and
stored in the Time Storage register. This value is used
during the next Acceleration Time Storage subroutine
calI to calculate the Stored Time Constant (see Block .6
below). If PTS is invalid, the flow returns to the timer
loop just exited, again waiting for PTS or Failsafe time
out.
During the PT time loop, if PTS is detected and verified, the Sync flag is tested for entry to the print head
solenoid firing subroutine. This flag is set by the first
entry to the Character Processing subroutine. The flag
synchronizes the solenoid firing with character processing.Only if characters are processed for printing wilI
the solenoids be enabled, via the Sync flag, for firing.
This prevents the solenoids from being fired without
valid character dot data present.
As described in the Background section "Relationship
Between PTS and PT," PTS is the point of peek angular velocity within a step of the motor. After PTS is
detected the motor speed ramps down, compensating
for the overshoot of the rotor motion. PTS is the optimum time for print head solenoid firing, as shown in
Figure 13. This is the stable point of motor rotation
and, thus, the print head assembly motion. If PTS is
detected during PT, printing is enabled, the Sync flag is
set, and the solenoid trigger is fired.
The firing of the solenoid trigger, folIowing PTS, is very
time critical. The time between PTS and solenoid firing
must be consistent for accurate dot column alignment
throughout the printed line. The software is designed to
meet this requirement by placing all character processing and motor control overhead before the solenoid firing subroutine is called. The actual instruction sequence which fires the print head solenoid trigger is
plus or minus one instruction for any calI to the subroutine.
Once the timer loop is complete, the software tests for
Exit conditions. If the Exit conditions fail, the software
loops to output the next step signal, starts the PT timer,
and continues to accelerate the carriage stepper motor,
or process, and print characters. If the Exit test is true,
the carriage stepper motor is decelerated to a fixed position, and the program returns to the main program
flow (see Flowchart i).
The exit conditions are different for the two directions
of print head assembly motion: For L-to-R printing, if a
Carriage Return (CR) character code is read from CB,
the carriage stepper motor drive terminates and the
motor is decelerated to a fixed position. There are two
conditions for terminating carriage stepper motor drive
upon detecting a CR during L-to-R motion. If less than
half a character line (40 characters) has been printed,
the print head assembly returns to the HOME position
to start the next printed line. Otherwise, the print head
assembly continues to the right-most position for a fulI
80 character line, and then begins printing the next line
from R-to-L. R-to-L printing always returns the print
head assembly to the HOME position berore the next
line is printed L-to-R. When HR is high, character
printing always stops and the carriage stepper motor
drive subroutine exits to the deceleration subroutine.
6. Accelerate Stepper Motor Time Storage
As described above, when the carriage stepper motor is
accelerated the step time required to guarantee the motor is at a constant rate of speed translates to a specific
distance traveled by the print head assembly (see Figure
18).. In order to position the print head assembly accurately for bi-directional printing, the distance traveled
during deceleration must be the same as during acceleration. The Carriage Motor Acceleration Time Storage
subroutine calculates the step times needed to accelerate the carriage stepper motor, and stores them in Data
Memory for use as PT during deceleration.
The first call of the Carriage Stepper Motor Acceleration Time Storage subroutine initializes the required
registers and status flags. The time calculation begins
with the second carriage stepper motor step signal output. The program returns to the carriage stepper motor
drive subroutine and loops on PT. Each subsequent call
of the Acceleration Time Storage subroutine tests the
Failsafe/Constant flag and branches accordingly (see
Flow Chart 7). The Acceleration Time Storage subroutine has two parts which correspond to PTS leading or
PTS lagging PT.
If the Failsafe/Constant flag is set, PTS lagged PT. The
time from PT time out to PTS, Tx (see Figure 13), must
be added to the PT and stored in Data Memory. As
described above, if PT lagged PT, the Failsafe time is
loaded and PTS is again polled during the. time loop.
When PTS occurs within the Failsafe time, the timer is
stopped and the timer value stored. The UPI-42AH
timer is.an up timer, which means that the value stored
is the time remaining of the Failsafe time when PTS
occurred. The elapsed time must be calculated by subtracting the time remaining (the value stored) from the
Failsafe time constant. This is done in software by using two's complement arithmetic. If the Failsafe flag is
not set PTS led PT, and PT is the Stored Time Constant stored.
9-104
AP-161
y
~
TIME STORAGE INITIALIZATION DONE
~N
I
INITIALIZE TIME STORAGE REGISTERS
y
>
<
>v-
INITIALIZATION DONE
~N
I
SET SYNC STATUS FLAG
I
+
r;;<
TIME STORAGE DONE
tV
I
"'>
t
FAILSAFE TIME WINDOW ENTERED
tV
I
CALCULATE TIME TO STORE
(PT. H) RESET FAILSAFE FLAG
I
I
r
I
DECREMENT OATA MEMORY ADDRESS
DECREMENT STEPS TO SCTRE COUNT
I
t
RETURN
::.
SAME CHARACTER RE·ENTRY
N~
I
INITIALIZE CHARACTER PROCESSING
REGISTERS
<
+
rv-<
READ CHARACTER FROM CB
t
r;-<
~
I
.>
ASCII PRINTABLE
Nt
<
STORE PT
I
TRANSLATE CHARACTER
TO DOTS
IFlOWCHART 119)
~
I
Flow Chart No.7. Carriage Stepper Motor
Acceleration Time Storage
I
~OT
COLUMN DATA
l
I
IN<
I
r
+
CHARACTER DOT MATRIX
r-<
Indirect addressing of Data Memory is used to reference the Stored Time Constant Data Memory location.
The Data Memory location address is decremented
each time the Acceleration Time Storage subroutine is
exited and a Stored Time Constant has been generated.
GET CHARACTER
lESS THAN HALF OF LINE PRINTED>
N
REPLACE CHARACTER
WITH 20H (S~CE)
I
230795-24
t
V
IN
+
I
I
CR
r
RESET STATuS FLAGS
CB FULL.. REGISTER
INITIALIZATION,
SYNC, EOlN
I
~
L·TO-R PRINTING
r
STATUS FLAG
-t
I
v~
I
<
INITIALIZATION
STATUS FLAG
~
RETURN
I
I
80 CHARACTERS PRINTED
N
tV
The last Acceleration Time Storage subroutine exit sets
the At-Speed status flag and initializes the character
processing registers and flags.
l
REser STATUS FLAGS
CB FULL. SYNC.
PRINT NOT READY
I
I I
AOVANCE CB FOR
DlAECTION OF
PAINTING
.
7. Process Characters for Printing
I
+
The Character Processing subroutine is entered only if
the Home Reset (HR) optical sensor signal is high and
printing is enabled. Otherwise, the software simply returns to the Carriage Stepper Motor Drive subroutine.
There are two cases when printing is not enabled; during the HOME subroutine operation, and when the
print head assembly returns to the HOME position after printing less than half an 80 character line. If printing is enabled, the Sync status flag is set.
All character processing operations use the second
UPI-42AH Data Memory Register Bank, RBI. Register Bank 1 is independent of Data Memory Register
Bank 0, used for stepper motor control. The use of two
independent register banks greatly simplifies the software flow, and helps to ensure the accuracy of event
sequences that must be handled in parallel. Each register bank must be initialized only once for any entry to
either the Carriage Stepper Motor Drive or Character
Processing subroutines. A single UPI-42AH Assembly
Language instruction selects the appropriate register
I
SET DO NOT PRINT
COMPlETE
RESET CHARACTER
>
I
ADVANCE
CHARACTER
NI
~OT MATRIX
ADDRESS
FOR DIRECTION OF PRINTING
GET CHARACTER DOT COLUMN
DATA AND OUTPUT
I
I
RETURN
I
230795-25
Flow Chart No.8. Process
Characters for Printing
bank. Initializing the character processing registers includes loading the maximum character count (80), dot
matrix size count (6), and CB start address. The CB
start address is print direction dependent, as described
in Block 4, above.
Character processing reads a character from the CB,
tests for control codes, translates the character to dots,
9-105
intJ
AP-161
and conditionally exits, returning to the Carriage Stepper Motor Drive subroutine. FlowChart 8 details the
character processing subroutine.
.Each character requires six steps of the carriage stepper
motor to print; five for the 5 character dot columns and
1 for the blank dot column between each character.
Reading a character from the.CB and character-to-dot
pattern translation takes place during the last character
dot column, or blank column, time.
The first character line entry to the Character Processing subroutine appears to the software as if a last·character dot column (blank column) had been entered. The
next character, in this case the first character in the
line, is translated and printing can begin. This method
of initiatizing the Character Pro~essing subroutine utilizes the same software for both start-up and normal
character flow. Once a· character code has been translated to a dot. matrix pattern starting address in the
look-up table, all subsequent entries to the Character
Processing subroutine ·simply advance the dot column
data address and outputs the data.
9
-<
,
<
I
l
The dot pattern look-up table occupies two pages, or
approximately 512 bytes of Program· Memory. A printable ASCII character is tested for its dot pattern location page and the offset address, from zero, on that
page. Both the page test and page offset calculations use
two's complement arithmetic, with a jump on carry or
not carry causing the appropriate branching. Once the
pattern page and address are determined the indirect
addressing and data move instructions are used to read
and output the data to the print head solenoids. Flowchart 9 details the Character-to-Dots Translation subroutine.
In the case of R-to-L printing, although the translation
operation is the same, the character is printed in reverse. This requires that the character dot pattern address be incremented by five, before printing begins, so
that the first dot column data output is the last dot
column data of the character. The dot pattern look-up
table address is then deCremented rather· than incremented, as in L-to-R printing, for the balance of the
character. Translation still takes place during the last
or LINE
PRINTED
l
Sf' PAGE
L
n
AC".
~
l
r~
N
RfPlACE CR WITH 20H
lEST CHARACTER DOl PAGf
>Nj
SE T 00 NOT PAINT flAG
SET EOlN FLAG
1.
AETURN
I
I
J
COMPUTE CHARACTER PAGE ADDRESSQffSfT
~
r"0,, .•
"0
ADJUST OffSET ADDRESS
.
l
Characters-to-dot pattern translation involves converting the ASCII code into a look-up table address, where
the first of the five bytes of character dot column data is
stored. The address is then incremented for the next
column of dot pattern data until the full character has
been printed.
.
HAlf
I
The decision to .translate the character to dots· dUring
the blank column time was an arbitary one. As was the
. choice of the blank column following rather than preceding the actual character dot matrix printing.
8. Translate Character-to-Dots
:::J,
ASCII CHARACTER
~
SET CHARACTER INITIALIZATION FLAG
L
HfTUAN
J
230795-26
Flow Chart No.9. Translate Character-to-Dots
character dot column, the blank column, and the blank
column follows the character matrix.
Only one control code, a Carriage Return (CR), is encountered by the character translation subroutine.
Linefeed (LF) characters are stripped off by the CB Fill .
subroutine. If a CR code is detected the software tests
for a mid-line exit condition; less than half the line
printed exits the stepper motor drive subroutine and
HOMEs the print head assembly before printing the
next line. If the test fails, more than half the line has
been printed, theeR is replaced by a 20H (Space character) and printing continues for the balance of the line;
the space characterS padding the CB are printed.
As mentioned above, the character dots are printed and
the print head trigger is fired when the PTS signal is
detected and verified and the carriage stepper motor is
At Speed.
When the character to print test fails the CB Buffer size
count equals zero, the Carriage Stepper Motor Drive
subroutine exit flags are set, and the flow passes to the
Deceleration and Delay subroutines and programs returns to the main program flow.
.
9-106
inter
I
AP-161
.CTJ
INITIALIZE DECELERATION REGISTERS
Delay subroutine is called to stabilize the stepper motor
before it is deselected. During the DELAY subroutine,
the IBF interrupt is enabled and characters are processed. A paperfeed is forced following the carriage stepper
motor being deselected.
I
OUTPUT NEIlT STEP SIGNAL
lOAD A START TIMER
DECREMENT STORED TIME CONSTANT
DATA MEMQRY ADDRESS
10. Paper Feed Stepper Motor Drive
SETUP NEXT STlP
~
<
I
STEP SEQUENCE DON(
The paper feed stepper motor subroutine outputs a predefined number of step signals to advance the paper, in
one line increments, for the required number of lines.
The number of step signals per line increment is a function of the defined number of lines per inch, given the
distance the paper moves in one step. Figure 16 lists
three step (or pulse) count and line spacing configurations, as' well as the distance the paper moves in one
step. Standard 6 lines per inch spacing has been implemented in this Application Note (Appendix B details
how variable line spacing could be implemented). Flow
Chart 11 illustrates the Paper Feed subroutine.
RESTART SEQUENCE
,I"
I
LOAO HfJ.T STEP
DECElERATION D O N E >
STORE LAST STEP ADDRESS
I
RfTURN
I
230795-27
Flow Chart No. 10. Decelerate Carriage
Stepper Motor
?
L
INITIALIZE REGISTERS
<
9. Decelerate Carriage
Stepper Motor
.
The transition from the Carriage Stepper Motor Drive
subroutine to the Deceleration subroutine outputs the
next step signal in sequence; and then initializes the
Deceleration subroutine registers; Stored Time Constants Data Memory buffer end address and size. The
Stored Time Constant Buffer is a LIFO for deceleration
of the carriage stepper motor. The buffer size is used as
the step count. When the step count decrements to
zero, the step signal output is terminated, and the last
step sequence number is stored in the carriage stepper
motor Next Step pseudo register. The last step sequence
number is recalled, during initialization of the next carriage stepper motor drive, as the basis of the next step
data signal to be output. See Flow Chart 10.
When the carriage stepper motor is decelerated, Failsafe protection and PTS monitoring are not necessary.
The Deceleration subroutine acts as its own failsafe
mechanism. Should the stepper motor hang-up, the
subroutine would exit and deselect the motor in sufficient time to protect the motor from burnout. Since
neither Failsafe nor print head solenoid firing take
place during deceleration, PTS is not needed. PT is replaced by the Stored Time Constant values in Data
Memory. The Deceleration subroutine determines the
next step signal to output, loads the Timer with the
Stored Time Constant, starts the UPI-42AH Timer,
and loops until time out. The subroutine loops to output the next step until all of the Stored Time Constants
have been used. The program returns to the Carriage
Stepper Motor Drive subroutine and the motor is deselected following the Delay subroutine execution. The
9-107
<.
J.
Lf/FF
FF
+LF
LINE COUNT
r
J
END OF PAGE
Y
J
I
CALCULATE LINES
LOAD LINE COUNT
I
<.
+
OUTPUT NEXT STEP SIGNAL
LOAD AND START TIMER
SETUP NEXT STEP
..1
I
STEP SEQUENCE DONE
RESTART SEQUENCE
IN
J
LOAD NEXT STEP
I.
<'./--=PT::T=I}=='-=OU-=T'-~~""
N
1-;<
LINE DONE
;:>
LOAD LINE STEP COUNT
!
~.r~l-::IN:::'-:::CO~U::-:NT::O::O::-:N':---"":>
JY
STORE LAST STEP seQUENCE NUMBER
l
J
TO MOVE FOR TOP-OF-MGE
DELAY
DESELECT PAPEA FEED STEPPER MOTOA
J
J
RETURN
230795-28
Flow Chart No. 11. Paper Feed
Stepper Motor Drive
inter
AP-161
The number of lines the paper is to be moved is called
the "Line Count." The Line Count defaults to one unless the Formfeed flag is set, or the total number of
lines previously moved equals a full page. The default
total lines per page for this application is 66. When the
total number of lines moved equals 66, the paper is
moved to the top of the next page. The Top-of-Page is
set at power-on or reset.
If the Formfeed flag has been set in the Character Buffer Fill subroutine, the software calculates the number
of lines needed for a top of next page paper feed. The
resulting line count is loaded in the Line Count Register. The Paper Feed subroutine loops on the line count
until done and then returns to the main program body.
Once the Paper Feed subroutine is complete, the software loops to test the End of File (EOF) .Flag (see Flow
Chart 1). If EOF is set, the print head. assembly is
moved to the HOME position, the program again enters the External Status Switch Test subroutine, and
begins polling the external status switches. If EOF is
not set, the program directly calls the External Status
Switch Check subroutine, and the program repeats for
the next line.
CONCLUSION
Although the full speed, 12 MHz, of the UPI-42AH
was used, the actual speed required is approximately 89 MHz. 1400 bytes of the available 2k bytes of Program
Memory were used; 500 bytes for the 95 character ASCII code dot pattern look-up table, 900 bytes for operational software. This means that the UPI-42AH has
excess processing power and memory space for implementing the additional functions such as those listed
below and discussed in Appendix B.
Special Characters or Symbols
Lower Case Descenders
Inline Control Codes
Different Character Formats
Variable Line Spacing
The software developed for this Applicati()n Note was
not fully optimized and could be further packed by
combining functions. This would require creating another status register, which could also serve to implement some of the features listed above. Since the full 16
byte stack is not used for subroutine nesting, there are
6-8 bytes of Program Stack Data Memory that could
be used for this purpose. In several places, extra code
was added for clarity of the Application Note. For ex'
ample, each status byte flag is set with a separate instruction, using a equate label, rather than setting several flags simultaneously at the same point in the code.
This Application Note has demonstrated that the
UPI-42AH is easily capable of independently controlling a complex peripheral device requiring real time
event monitoring.· The moderate size of the· program
required to implement this application attests to the
effectiveness of the UPI-42AH for. peripheral control.
9-108
AP-161
APPENDIX A
SOFTWARE LISTING
1 SMOD42 TITLE ( 'UP I 42 APP NOTE') i
=
2 $MACROFILE NOSYMSOLS NOGEN DEBUG
3
4 $INCLUDE (: Fl: ANECD. 0\1'1,)
5
PG
6
7
••• ** ••• *.****** ••• *******.
Complex Peripheral Control With the UPI-42
= B
9
= 10
= 11
12
= 13
Intel Corporation
3065 Bow@rs Av@nu@
Santa Clara, Ca. 95051
14
Wri tten Bq
= 15
16
17
lS
19
=
=
=
=
=
=
•
•
=
=
***** •• ******* . . . . . . . ****** .... ***** .... *
20
Nohs· and Comments
21
22
23
Three Assembl'd Language files comprise the full Application
Not. source code.
24
2~
26
27
29
29
30
31
32
33
= 34
= 36
=
Christopher Scott
1.
ANECD. OVI
App Note Eq,uates. Constants. Declarations.
2.
42ANC. SRC
UPI-42 App Not. Code Source
3.
CHRTDL.OV1
Character Tabh . Ove:rlay
Overlay
(Character Lookup Tables)
i PG
3~
.********** ••• **.* •••• ** •••• *.*
37
39
****.*********.****.****.*.* •••
Equates, Constants and System Defini tions
40
Data & Program Memory Allocations
Program Memory
43
Page No.
3'i
= 41
42
Hex Addr
Description
44 ,
=
=
•
•
=
45
46
47
49
49
~o
Page 7
1792-2047
Page 6
1536-1791
Page 5
1290-1535
Page 4
Page 3
1024-1279
769-10:23
~1
-
=
=
=
=
=
•
=
-
=
=
=
=
=
=
-
=
~2
~3
54
55
~6
57
59
~9
60
61
62
63
64
65
66
67
69
69
70
Page 2
512-767
Page 1
2~6-511
Page 0
0-2"
Char to Dot pattern lookup table
Page 2:
ASCII ~OH-7FH (N-"',
Char to Dot pattern lookup table
Page 1:
ASCII 20H-4FH (sp-I'I)
l'Iise "tlled routines;
InitAl/AllOFf
Clear Data Meinor~'
CR Home
Char Print Test load Ascii char c:.odes
Initialize CR Stpr I'Itr
Delay: 5hort/long/v.r~ long
Stpr Mtr deselec:.t
Pap.rF.ed Stpr I"Itr Init and Drive
Stpr I'Itr Phase LookUp Table - Ind •• ed
Char.ct.r Translation and proe •• &ing
PrintH.ad firing
Stpr Mtr Acc:.el. Time calc. and memorization
Stpr I"'Itr Deceler.tion
SMOriv (FAcc:.el/RAccel) - For~.rd " ReveT'S.
Stpr !'Itr acceleration Ie drive
InitiaiIation ~mp-on-R.set
Program BodV - all calls
Character Input test and Char Buff.r fill loop
Int.rrupt service routin ••
230795-29
9-109
intJ
=
PG
71
72
= 73
Data Memory
74
7:;
Dec_
710
77
7B
79
BO
BI
B2
B3' ;
B4
85
810
B7
BB
B9
90
9'1
92
93
94
Description
HOI
TOP
4B-127
37-47
310
35
34
33
32
2F-7FH
25-2EH
24H
23H
22H
21H
20H
24-31
B-23
0-7
IB-IFH
B-17H
0-07H
80 Character Line Buffer
stpr MtT' Aceel/Dec.el time.
Unused
memorization
Char Print test ASCII code start tmp store
LF 8M last Phz Inderect'Addr psuedo reg
CR 8M Forward/Reverse last Phz psuedo reg
Psuedo'Reg:
Last Phase. of stpr mtr not
being driven
Register B~nk 1:
Character Handling
8 Level Stack
Stpr Mtr FIR Accel/Drive
BOTTOM
Data Memory Equates:
9:;
00:;0
0009
007F
0080
002F
0051
002F
0003
OOOA
002F
0025
007F
00:;0
0020
0021
0022
0023
EOU
Equ
50H
OD9H
ichar buffer size 0-79 = 80
;Cpl(1/2 CbBfSz) => cpl of 27H
FCBfSt
FCBfIS
RCBfIS
'ChBfIS
Equ
Equ
Equ
Equ
7fH
BOH
2FH
81
; start of char buffer
; init CB strt-allows xtra Ooc by 1
iinit CB strt-allows xtl'a Inc by 1
; I Dad char (nt reg wlchar bufr Init 5i ze
ENOBUF
ASBfSz
5MBFST
5MBEnd
OMTop
OMS! 10
EOU
EOU
Equ
EOU
Equ
Equ
Equ
2FH
OBH
OAH
2FH
2:5H
7FH
93
; END OF CHAR BUFFER
j Accelerat,e
'stpr mtr buf count
; Decelerate stpr mtr buf count
; STPR MTR BUFFER START
; Stpr Mtr Data Memorlj Address end
; Dat. Memor\! Top
; Data MemorlJ Size (less two lIIorking reg's)
LastPh
CP5Adr
LP5Adr
PTAs(S
Equ
EOU
Equ
Equ
20H
21H
22H
23H
; last phz psuedo reg addr
; CR phz psuedo T'eg
;LF phz psuedo T'eg
; ChaT' Print Test code start tmp store
910 CHBFSZ
:~ HHCpl
99
= 100
101
102
103
= 104
105
lOb OSBfSz
107
= lOB
109
= 110
III
112
113
114
= 115
009H
Ill.
= 117 PG
llB
* *
= 119
120
121
122
123
124
125
1210
* *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
All IndiT'ect Data MemoT'Y Addressing via @Rn Inst must use
on19 registers 0 & 1 of either registeT' bank.
Any otheT' will
be reJected by the Assembler
L~st character in lable indicates RegisteT' Bank refeT'enced
Register Bank 0
= 127
0000
0001
0002
0003
0004
000:;
00010
= 12B
129
130
- 131
132
133
134
=
0007
=
I
--------------------------------------------------------'-------------------
TmpROO' Equ
TStrRO EQU
GStR20 EQU
PhzR30 EQU
CntR40 Equ
RO
RI
R2
R3
R4
Equ
Equ
R5
Rio
EQU
R7
135 TeonRO'
1310 LnCtRO
137
13B OpnR70
139
140
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Register allocation
J
iRaO Temporary Register
; Store Time Register RBO
; General Status Register RBO
,Stpr MtT Phase Register RBO
; Count Reg. Phase count-Stpr !"ItT' loops
Aceel/Dscel Count
ITime constant reg RBO
; Line count
RegisteT' Bank 0 Data MemoT'1j
Ad~T'ess
= 141
230795-30
9-110
inter
0000
0001
0002
0003
0004
0005
OOOb
0007
AP-161
142
143
144
145
14b
147
148
149
150
151
152
153
= 154
TmpAOO
TStrAO
GStRAd
PhzA20
Equ
EGU
Equ
EGU
Equ
OOH
01H
02H
03H
04H
LnCtAO
Equ
Equ
05H
ObH
; Line Count Register OM address
OpnA70
EGU
07H
,available
CntRAO
TConAO
Temp orary Register OM address
Time Store Register OM address
RBO Char Status Reg OM address
i Stpr Mtr Phase Register OM address
• Count Reg. Phase CDunt-Stpr Mtr loops
Aceel/Oecel Count OM address
; Time constant reg OM address
PG
155
RBO Status Byte Bit Definition
= 156
157
158
159
lbO
lbl
lb2
lb3
Ib4
lb5
lbb
Ib7
lb8
Ib9
170
171
172
173
174
175
17b
177
178
179
180
181
182
183
184
185
18b
187
188
189
190
191
192
193
194
= 195
19b
= 197
198
199
200
0000
0001
0002
0003
0004
0005
OOOb
0007
Definition
Stpr Mtr Direction:
L-to-R = I. R-to-L = 0
1 = Sink I 0 = Not Sinked, Print Head lnit and Fire
Stpr Mtr at speed and CR not left of Home
Accel/Oecel Init, 1 = Done / 0 = Not Done
5
4
3
1 = Fai lSaf. /
2
1
1
1
o
LRPrnt
RLPrnt
SnkSet
ClrSn~
AtSpdF
NAtSpd
ADlntD
ADlntN
FsCTm
ClrFsC
FrmFd
LineFd
DoNotP
OkPrnt
Ready
NotRdy
=
=
0 = Constant. Time Window
Form Feed I 0 = Line Feed
Do Not Print I 0
Print
=
FAecel/DAccel drive Ready =
drive & decel stpr mtr)
Bit Ma'Sk'S:
Stepper Motor
Equ
Equ
Equ
Equ
Equ
Equ
Equ
Equ
80H
7FH
40H
OBFH
20H
ODFH
10H
OEFH
Equ
Equ
Equ
Equ
Equ
Equ
Equ
Equ
08H
OF7H
04H
OFBH
02H
OFDH
OIH
OFEH
l/NotRd~
o
(exit
RBO
~ontrol
bit mask'S function on GStRIO
i Left to Right Printing
(ORLl
iRight to Left Printing (ANLl
; Ready Print flag
.c.lear Ready to Print Bit
; Stpl' Mtr at constant speed
i Stpr Mtr Not at speed
'; Accel/Decel Init Done
i Accel/Decel Init Not Done
iFailSafelConstant Time
; Clear FailSafe/Canst time flag
ida formfeed
ida line feed
i set Do Not Print St"t bit
iReset - Ok to Print
; Ready drive Stpr Mtr
i Not Ready ex i t Stpr Mtr drive
PG
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Register allocation
* * * * * * * * *
(cont)
** * * * * *
*
* * * * *
*
* * * * * * * * *
Register Bank 1
= 201
202
203
204
= 205
20b
207
208
209
210
211
212
= 213
214
Bit
7
b
TmpRl0
CAdrRI
ChStRI
CDtCRI
CDotRI
CCntRI
StrCRl
Equ
EGU
EGU
EGU
Equ
Equ
EGU
RO
Rl
R2
R3
R4
R5
Rb
ichar data memory addr register
;char processing status byte register
i Char Dot count register
; Char dot temp storage register
; Char count temp register
; Store Char Register
OpnR71
EGU
R7
i
Available
Register Bank 1 Data Memory Address
230795-31
9-111
intJ
0018
0019
001A
001B
001C
001D
001E
001F
AP-161
= 215
216
217
218
219
220
221
~ 222
223
3
224
225
TmpAI0
ChARRl
ChStAd
CDtCAI
CDotAI
CentAI
StrCAI
Equ
E(lU
Equ
EtlU
Equ
Equ
EOU
24
25
26
27
28
29
30
OpnA71
EtlU
31
tempDrar~/scratch register
char data memory addr register
RBI Char Status Reg address
Char Dot count register
Char dot temp storage register
Char count temp register
Store Char Register
i
Available
= 226 PG
= 227
= 228
RBI Status Byte Bit Definition
229
230
231
232
233
234
235
= 236
237
238
239
240
=
0080
007F
0040
OOBF
0020
OODF
0010
OOEF
0009
00F7
0004
OOFS
0002
OOFD
0001
OOFE
=
=
250
251
252
253
254
= 255
= 256
257
258
= 259
260
= 261
262
263
264
= 26~
266
= 267
=
=
0004
0020
007F
00F3
00F6
00F4
00E5
OOEO
00C8
OOOD
0020
0081
0082
007F
0042
00C4
0010
=
=
=
=
=
=
269
269
270
271
272
273
274
275
276
277
278
279
280
281
282
28:3
284
285
286
287
288
289
290
291
292
29:3
294
DlI!finititin
5
Stpr Mtr Direction:
L-to-R = 1. R-to-L = 0
Char lnit. 1 = Done I 0 = Not Done
Ch.r Lookup Table Page: 1 = Pg1.. 0 = Pg2
4
1
3
I = EOF I 0 = Not EOF
Full = 1/Not Full = O. Line in Char Buffer
I = CR/(LF) I 0 = Not CR/(LF)
6
2
I
o
241
242
243
244
245
246
247
248
249
Bit
7
1
=
=
Test I
Init I
0
0
=
Norm.l char print/input
=
Do Not Init.
CB registers done
Bi t Masks:
RBI
Character printing bit masks function on ChStRl
Ch In.tD
ClntND
ChOnPI
ChOnP2
TstPrn
NrmPrn
Equ
Equ
Equ
Equ
Equ
Equ
Equ
Equ
80H
7FH
040H
OBFH
20H
ODFH
10H
OEFH
L-to-R
1
R-to-L = 0
; Set Char Ini t Done
;Reset Char Init Not Don@
; Page I char, set rentry bit (ORU
; Page 2 char, reset rentry bit (ANU
i Char print test
; Normal char input
EOF
ClrEOF
CRLF
ClrCR
CBFLn
NCBFLn
IntCBR
CllCOR
E"'lu
Equ
Equ
Equ
Equ
Equ
Equ
Equ
OBH
OF7H
04H
OFOH
02H
OFDH
OIH
OFEH
. set EOF Flag
;clear EOF flag - Not EOF
; CR/LF
;Clear CR/LF
; Full Line in Char Buff"r
, Not Full Line in ChaT' Buffer
; Jni t of CB registers done
i Ini t
of CB registers not done
ChrPrn
eIrep,.
j Stpr
I'1tr Direction':
; Stpr Mtr Direction:
PG
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Equates
* * *
(cont)
* * * * * * * * * * * * * * * * * * * * * * * * * *
Mise
RLPShf
Equ
04H
;R-to-~
Ascii
AseLst
Equ
Equ
20H
7FH
.hex nmbr of first Ascii Char
,hex nmbr of last Ascii Char
CRCpl
LFCpl
FFCpl
EscCpl
AscCpl
FTCpl
CR
Spac ..
Equ
Equ
Equ
Equ
Equ
Equ
Equ
Equ
OF:3H
OF6H
.OF4H
OE5H
OEOH
OC8H
ODH
20H
LAsEnd
PAsEnd
AscStp
PgLnCt
PgLCpl
EOFCpl
Equ
Equ
Equ
Equ
Equ
Equ
81H
82H
7fH
66
OC4H
ISH
print lookup table addr shift
;ASCII control code 2'5 complement
;Ascii code (hex)
.Asci-i code (hex)
.Ascii End 2'5 cpl - test line start
;Ascii End 2'5 cpl - within line print
; Asc i i mask. strip off MSB
;Page Line Count: Default = 66
.Printed lines per page test
iEOF ,ascii code cpl
Loop count values
230795-32
9-112
inter
AP-161
0006
OOOA
0004
295 NDtCCt
PHCntl
Equ
Equ
EQU
06H
OAH
04H
J Normal Dot Column Count
; Expand@d Dot Column Count
; NUM3ER OF SM PHASES ON INIT
ILFCnt
LPI6p6
LPI8p8
LPIIO
Equ
Equ
Equ
Equ
04
36
27
24
i Ini t
LF step/phz count
;Lines Per Inch 6.6
; Lines Per Inch 8.8
; Lines Per Inch 10
LineCt
Equ
Equ
EQU
01
66
03H
296 EDtCCt
297
298
299
300
301
302
303
304
305
306
307
308
309
0004
0024
0013
0018
0001
0042
0003
FmFdCt
Sta tus
j
1 inefeed count
j 1 ines
per formfeed count
; SEE BELOW FOR STATUS BVTE DEF.
TEST:
SET FOR CR STPR MTR CONTROL
= 310 PG
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
0080
0030
OOCC
0000
OOCC
003A
0092
OOCO
0098
OODF
0020
OOEF
DOlO
OOOC
0003
0040
OOCO
* * * *TIMER
* * *VALUES
* * * - * UPI
* * Timer/Counter
* * * * * * * is* *UP * Counter
* * * *
* *
* *12 * MHz
* * elk
* * timings
* * * * * * * * * * * * * * * * * * * * * * *
DLVCL
DLVCS
DlyTim
Fai ITm
CrTmrl
CrTmr2
CrTmr3
IntTm2
LFTMRI
NotBsy
Busy
Aok
ReSAck
StrpLF
StrpCR
0000
0003
0008
0001
0003
0002
0000
0004
oooe
0008
0000
~
80H
30H
256-52
256-256
256-52
256-70
256-110
256-64
256-104
;DELAV COUNT Lang
;DELAV COUNT Short
; TIME DELAV constant ~2.0mS
; Fai lSafe TIME = ~17. OmS
; CR Stpr Nt.,. Phase TIME = ~2. 08mS
; CR Stpr Mtr Phase TIME = ~2. 40mS
;CR Stpr Mtr Phase TIME = ""4. lamS
; Init Stpr Mtr Phase TIME = ~2.40mS
; LF Stpr Mtr Phase TIME = ~4. 16mS
I/O port bit masks
Equ
ODFH
Equ
20H
Equ
OEFH
Equ
10H
Mise
; Not BU5lJ
; Busy
; Ack
iReSet Aok
bit Masks
Equ
Equ
OCH
03H
; Str ip off all
, Strip off all
bits but LF Stp,. Mtr
bits but CR Stpr Mt,.
Print Head fires on low going edge of Trigger
bit *9 in dot column is masked off. always:
PTRGLO
PTRGHI
EQU
EQU
40H
OCOH
P2.
bit 6
;PH TRIGGER BIT - LOW
;PH TRIgGER BIT - HIGH
* * * Stepper
* * * * *Motor
* * *Phase
* * State
* * * Equates
* * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
FStCRP
RStCRP
STLFF
Stepper Motor Phase Shift Index Offset Offset
EQU
OOH
iF CR stpr mtr phase data start addr
EQU
03H
;R CR stpr mtr phase data start addr
Equ
;Paper feed stpr mtr phase data start addr
08H
CARRIAGE STEPPER MOTOR PHASE EQUATES
Forward (1 thru 4>
CRMFPI
CRMFP2
CRMFP3
CRMFP4
EQU
EQU
EGU
EQU
&
OIB
lIB
lOB
003
Reverse (4 thru 1) :
;CR
;CR
;CR
;CR
STPR
STPR
STPR
STPR
MTR
MTR
MTR
MTR
PHASE
PHASE
PHASE
PHASE
I
2
3
4
; LINE FEED STEPPER MOTOR PHASE EQUATES
Forward:
LFMFPI
LFMFP2
LFMFP3
LFMFP4
EQU
EQU
EQU
EQU
; LF
; LF
; LF
; LF
01003
1100B
1000B
00003
STPR
STPR
STPR
STPR
MTR
MTR
MTR
MTR
PHASE
PHASE
PHASE
PHASE
I
2
3
4
= 364 PG
j
230795-33
9-113
AP-161
365
* * * * * * * * * .. * * .. .. * * * * * * * * * * * * * * * .. * *
367
368
369
370
371
372
= 373
374
375
376
377
378
= 379
380
.. .. * * * * .. .. .. * * .. .. * .. * * * .. * * * * * .. * * * * * * *
= 366
STEPPER MOTOR SELECT
~
CONTROL [CURRENT LIMITING]
PORT BIT ASSIGNMENT:
\
\
\
S S S
L. C C
F R R
B 1
o
3
2
5 5 :; 5
3 2 1 0
= 381
= 382
383
= 384
= 385
386
= 387
388
= 389
390
391
= 392
393
394
395
396
397
= 39B
399
400
0008
OOOC
0006
OOOE
CODING:
SL.F
SCRBO
SCR132
SMOFF
SCRBO
EGU
08H
SCR132
EGU
OCH
SL.F
EQU
06H
SMOFF
EGU
OEH
PG
* * * .. * .. * * * * * * * * * * .. .. * .. * * * * .. * * .. * * * * * .. * * *
404
* * * * * .. * * * * * * * * * * * * * * * * * .. * * * _* ................ *
MAIN PROGRAM BODY
406
0003
0003 142:1
0005 93
0007
0007 1429
0009 C5
OOOA 83
407
408
409
410
411
412 START:
413
414
415
416 10FIV:
417
418
419
420 TMRIV:
421
422
423
Power On I Reset Program Entry
PROGRAM START
Org
OOH
-iMP
RESET
INPUT BUFFER FULL. INTERRUPT CAL.L. ENTRY AND VECTOR
ORG
03H
Call
IBFIS
RETR
TIMER OVERFLOW INTERRUPT CALL. ENTRY AND VECTOR
07H
ORG
Call
TMRIS
SEL.
RBO
Rot
424
0000
OOOC
0000
OOOF
15
35
B40F
B42F
0011 B44B
0013 9400
0015 8422
0017 8400
0019 142C
CR STPR MTR - 80 COL.
STPR MTR OFF
CR STPR MTR - 132 COL.
STPR MTR OFF
L.F STPR MTR ON
wIeR STPR MTR OFF
, SEL.ECT CR & LF STPR MTR OFF
401
405
0000 0400
,SEL.ECT
w/L.F
, SEL.ECT
.,/L.F
, SELECT
402
403
0000
0110
06H
1000
OAH
1 1 0 0
OCH
1110
OEH
W/SCRBO & SCR132 '0' [BOTH SEL.ECTED]
DEFAUL.T IS TO 80 COL..
[DO NOT KNOW WHETHER SCRBO='O' WIL.L.
SEL.ECT BO COL. ONL.Y] - REGUIRES TEST.
425
426 R.s.T:
427
428
429
430
431
432
433
INITIALIZATION
Dis
Dis
I
Call
Call
TCnt!
InitAI
ClrDM
Call
Call
InitCR
InitL.F
;5et all critical outputs inactive
itlear .11 d.ta m.mor~ - 93H to 7FH
do not clear RBO, RBI or Stack
,CALL CR SM POWER ON INIT
,CAL.L L.F 8M POWER ON INIT
434
MAIN PROGRAM LOOP
435 J
436
437 Home:
Call
43B
439
Call
440 CBlnpt: Call
441
442
All program segments are called from here
CRHome
Call Home CR routine fixes logical and ph~9ic.l CR Home
set default register value.
Defalt
E8CBfF
Stat Switch I CB Input Service Test
test foT':
CD full/fill, LF, FF,
Char Prnt Test
230795-34
9-114
intJ
0010
0010
OOIF
0020
0021
0023
AP-161
3400
9400
05
FA
7215
0419
443 Repeat:
444
445
446
447
448
449
450
SMDTiv
LFDriv
RBI
A.ChStRI
; Call Forward Stpr MtT Drive
,Call Lin.f.ed Stpr MtT Drive
.get the Char Status Register RBI
j Jump
to CR SM Home if EOF bit set
i loop to Char Buffer Input test
Home
CBlnpt
PG
* * * * * * * * * * * * * * • *
451
452
Call
Call
SEL
Mov
.J03
.Jmp
Interrupt Service Routine
i
* * * * • * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
453
4!!4
•
455
------------------------------------------------------------------------
456
Input Buffer Full Interrupt Service Routine
4!!7
-----------------------------------------------------------------------458
459 IBFIS:
460
-----------------------------------------------------------------------461
Acknowledge Char input and set Hold/Busy Active
002!! 8A20
0027 15
0028 83
ORL
P2,*Susy
.get & set DBB ACK/Busy Bits
463
Dis
I
;disable IBF interrupts
464
Ret
462
465
466
------------------------------------------------------------------------
467
0029 15
002A 35
0020 83
Timer
475
PG
476
* * * * * * * * * * * * * * * * * * * *
477
002C
0020
002E
0030
0031
05
FA
53EF
AA
C5
0032
0033
0035
0037
0039
0030
OF
1230
3245
5249
72!!E
042C
0030 FA
003E 4304
0040 AA
0041 9400
0043 042C
0045 9400
0047 042C
0049
004A
0040
0040
004E
0050
0051
0053
05
FA
4310
AA
0823
FO
0381
9657
0055
0057
0058
0059
005A
005C
0050
B020
FO
AF
10
8439
C5
83
Counter Interrupt Service Routine
I
468
-----------------------------------------------------------------------469
ITF interrupt service routine disables all tntr during
470
stpr mtr phase shifting
471 THRI5:
Dis
I
;disabl@ IBF int~rrupts
472
Dis
TCntI
idicabl@ ITF interrupts
473
Ret
474
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
Ext@rnal
Switch Check/Char. Buffer Fill
Statu~
* * * * * * * * * *
* * * * *
* * * * *
*;Prep
* * *fo~* *normal
* * * character
* * * * * handling/input
* * * * * * * *
SEL
Mov
ANL
Mov
SEL
RBI
A.ChStRI
A, 4tNrmPrn
ChStRl.A
RBO
iget the character stat reg byte
;set normal character input
;store the stat b~te
ESCBfF:
Test External Status Port
MovD
A.P7
; get the stat switch port bits
.JBO
FormFd
service Formfeed
.JBI
LinFd
service Linefeed
.JB2
ChT'Tst
service Character TEST
.JB3
service Char Buffer Check/Fill
OnLine
i Loop
.Jmp
ESCOfF
FormFd:
Mov
ORL
Mov
Call
.Jmp
A.GStR20
A. ttFrmFd
GStR20.A
LfDriv
ESCBfF
LinFd:
Call
.Jmp
LfDriv
ESCDfF
;
,get the status byte
iset the formfeed stat flag
; store trhe status byte
Ida a formfeed
ida a line drive
----------------------------------------~------------.--------------------
ChrTst: SEL
Mov
ORL
Mov
Mov
Mov
AOO
.JNZ
AscCLd:
Mov
Mov
Mov
Inc
Call
SEL
Ret
RBI
A.ChStRI
A.ttTstPrn
ChStRJ. A
TmpR10,.PTAscS
A.!!TmpRIO
A.ttLAsEnd
AscCLd
@TmpR10."Ascii
A.!!TmpRIO
OpnR71.A
PgLnCt .ot formfeed flag
616
.JNC
NoFmFd
I if nat at ond af p.ge skip
617
Mav
A.GStR20
; get the status byte
61B
ORL
A.ttFrmFd
; set tho form feed status flag
619
Mav
GStR20.A
; save tho status byte
620 NoFmFd: SEL
RBI
621
En
I
; enable the IBF service
622
ANL
P2.ttNotBslj
i output a not busy to Host
623 LFTest: .JNIDF
LFTest
; loop to next char
624
ANL
P2 •• Ack
; output ODD Ack 10"'
625
In
A.DDD
; get next Char - assume it's a LF
626
and ignor it eLF i. fOT"ced upon
627
detection of CR at print time)
62B SetPad: Mov
A.ChStRl
; get the status b~te
629
ORL
A.• CRLF
; set CRLF stat bit:
pad balance of CD
630
with Spaces until fill
631
Mov
;
store
ChStRl. A
tho status byte
632
ORL
P2.ttReSAck
; output ODD ACK High
633
.Jmp
IBfS~E
; Jmp to addr step I- eKit
634
635
fill Char Buffer with space
636 CBPadl: Mov
eCAdrRl.ttSpace; load data memor~ w/Char
637 i ----------------------------------------------------~----~-------------638
step the char address test for CB full &/or pad
639 IBFS~E: DEC
CAd~Rl
.Decrement dat memory location
640
Mov
;get the status byte
A.ChStRl
641
CBFul1
;test for CB Full
.JDl
642
;test for CB pad - exit w/Busy set
.JD2
CBFIEx
643
644
Set Busy Line Low - Not Busy
645
EN
I
646
ANL
P2,ttNotBsy
;output a not busy to Host
647
64B
eKit wi Busy Still set high
649 CBFull:
650 CBFIEK: Ret
651
652
PG
653
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
L-to-R/R-to-L Carriage Stepper Motor Drive
and Line Printing
6~4
6~~
0100
0100 3622
656
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
657
ORG
100H
658
659
660 SMDriv: JTO
RAccel
; if Print Head at left drive right
661
else drive left
662
F========================================~============ ============
663 FAceel:
iL-to-R Accelerate Stepper Motor
664
Sot the Forward acceleration/drive Entry status bits
Mov
665
A.GStR20
;get the status byte
666
ANL
A,ttClrSnk
;set not at speed flag = 0
ANL
667
A,ttNAtSpd
;set Not At Speed flag = 0
66B
ORL
A,.LRPrnt
iset L-to-R prnt stat bit = 1
669
ORL
A•• Ready
j set
stpr mtr ready - Drive On
670
ANL
A•• ADIntN
; set AID Jnit Not Done
671
Mov
GStR20,A
;store the status byte
672 CORDi r: SEL
RBI
673
Mov
A.ChStRI
;get the Char Stat Reg Dat~ Mem Addr
674
ORL
A.tlLRP~nt
iSet L-~o-R print bit
675
Mov
ChStRI.A
i save the Char Stat b~te
676
RBO
SEL
677
678
Restore the phase register indeK addresses
679
Mav
TmpROO,.CPSAdr ;get Phz Storage Addr psuedo reg
680
Mov
A,@TmpROO
j
get stored CR last phase index addr
6BI
Mov
PhzR30,A
;place last LF phase index addr in Phz, Reg
682
;
0102
0103
0105
0107
0109
0103
0100
010E
010F
0110
0112
0113
FA
S3DF
53 OF
4380
4301
53EF
AA
OS
FA
43BO
AA
C5
0114 DB21
0116 FO
0117 AD
230795-37
9-117
AP-161
0118
0119
011A
011C
011E
0120
0122
0123
0125
0127
0129
012B
012D
012E
012F
0130
0132
0133
10
FO
521E
2440
BOOO
2440
FA
530F
53DF
537F
4301
53EF
AA
D5
FA
537F
AA
C5
0134 0821
0136 FO
0137 AB
0138
0139
013A
013C
013E
0140
0142
0143
0144
0146
CB
FO
523E
2440
B003
B822
FO
E3
B820
AO
0147 BDBA
0149 2308
0140 3D
014C
014D
014E
014F
FD
62
FB
E3
0150
0152
0153
0154
B820
40
3C
55
0155 740C
0157 FA
0158 F264
015A
0153
015C
015E
0160
0162
CB
FB
5260
2462
BB03
246C
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
·763
764
765
766
Set up for next phase bit output b~~ore entering timing loops
,STEP PHASE DO ADDRESS
INC
PhzR30
MOV
A.PhzR30
; CHECK THE PHASE COUNT REG
J02
IAFZrP
;CHK FOR COUNT BIT ROLLOVER
JMP
iskip ad,. index reset
SMDflt
IAFZ,.P; MOV
PhzR30 •• FStCRP ,ZERO CR SM PHASE REGISTER
Jmp
SMDflt
; R=================================================================
iR-to-L Accelerate Stepper Motor
RAceel:
Sot the Reverse acceleration/drive Entry status bits
, get the status byte
Mov
A.GStR20
ANL
A.ttClrSnk
; clear Print ReadlJ bit
A.tlNAtSpd
-; set Not At Speed flag = 0
ANL
ANL
A.ttRLPrnt
i'set R-to-L prot status bit
ORL
A•• Ready
;'set stPT" mtr -re"ady - Drive On
ANL
A,ttADIntN
; set AID Init Not Done
Mov
GStR20.A
i store the status byte
RCBRDr: SEL
RBI
Mov
A,ChStRl
; get tho Char Stat Reg Data Mem Addr
p,.int bit
ANL
A. ttRLPr'nt
j Set R-to-L
Hov
; save the Char Stat byte
ChStRI. A
RBO
SEL
Restor. the phase register index address
TmpROO.ttCPSAd...
;get Phz Storage_Addr psuedo reg
Mov
A.@TmpROO
get sto~ed CR last phase index .ddr
Mov
PhIR30,A
;place last LF phase index addr in PhI Reg
Mo"
Set up for next phase bit output before entering timing loops·
,STEP PHASE DB ADDRESS
Ph zR30
Dec
A.PhzR30
,CHECK THE PHASE COUNT REG
MOV
IARZrP
;CHK FOR COUNT BIT ROLLOVER
.JB2
..IMP
SMDflt
IARZrP: MOV
Ph,R30.tlRStCRP ; ZERO CR SM PHASE REGISTER
SMDflt:
for stablilation of unused stpr mtr du~ing CR stpr mtr drive.
store the unused stp~ mtr current phase bits
Mov
TmpROO,*LPSAdr
iget the CR phI storeage "addr
Mov
A.@TmpROO
;get the b~ute stored there
MovP3
A.eA
.get the,phl data b~te
Mav
TmpROO.*LastPh; load Last PhI psuedo reg to Temp Reg
Mov
@TmpROO.A
;store Last Phase bits - inderect
SetUp Stpr Mtr Time Constant
MOV
TConRO •• CrTmr2 ;Load time constant Reg
Select:
MOV
MOVD
STRTT:
A.tlSCRBO
PS. A
iSelect the Stpr Mtr
,GET CR SM SELECT BITS
,SELECT SM [SCR80]
SetUp Stpr Mtr Phase Shift index address register
Output next phase and init timer to Std Time constant
MOV
A.TeDnRO
;get time constant from reg
MOV
T, A
i load the timer
MOV
A,PhIR30
;get the phI reg indirect addr index
MovP3
A.@A
ida indirect get of phI bits
patch together the CR l.st and.LF next phase bits
Mov
TmpROO,*LastPh ; load Last PhI psuedo reg to Temp Reg
A,@TmpROO
;patch together CR existing ~ new LF
ORL
MOVD
P4. A
; OUTPUTB ITS
STRT
T
,START TIMER
At "start of timing loop do all Stpr Mtr Accel/Decel or
Character SetUp overhead
Call
ADPTst
,call A~cel/Decel/Print Test
PNRdyl:
Set up for next ph.s~ bit output before entering timing loops
itest for forward I reverse phase st.rt indirect index to load
Mov
A, QStR20
.sto~e stat b~te
JB7
AclF2
reverse:
Set up for next phase bit output before entering timing loops
Dec
Ph,R30
,STEP PHASE DB ADDRESS
MOV
A.PhzR30
,CHECK THE PHASE COUNT REG
.JB2
ARZroP
,CHK FOR COUNT BIT ROLLOVER
..IMP
ARN,tP
ARZroP: MOVPh,R30.tlRStCRP ,ZERO CR SM PHASE REGISTER
ARN,tP: ..Imp
AN,tPh
230795-38
9-118
AP-161
767
768
769
0164
0165
0166
0168
016A
ID
FB
526A
246C
BBOO
;
f OTlilard:
Set up for next phase bit output before entering timing loops
PhzR30
,STEP PHASE DB ADDRESS
INC
A.PhzR30
,CHECK THE PHASE COUNT REG
MOV
772
AFZroP
,CHK FOR COUNT BIT ROLLOVER
JB'il
ANxtPh
i5kip adr index reset
773
JMP
PhzR30 •• FStCRP ,ZERO CR SM PHASE REGISTER
774 AFZroP· MOV
770 Ac IF2:
771
775 ANxtPh:
016C 1682
016E 5672
0170 246C
0172 00
0173 5677
0175 246C
776 , --------------------------------------------------------------777
stage one timer loop - T occurs before Std timeout
wait for timR out
778
,JMP ON TIME OUT-t DOES NOT OCCUR 1ST
779 TLOOP2: JTF
FAILSF
, IS T HIGH-JMP TO tCHK
780
JTI
tCHKI
,LOOP FOR JTI OR JTF·
781
JMP
TLOOP2
i delal,l.
then double check T signal
782 tCHKI:
NOP
,JUMP T TEST TRUE-WAIT FOR JTF
783
JTI
tTruWl
784
JMP
TLOOP2
785 tTruWl:
786
787
0177
0178
017A
017C
FA
D27C
247E
74CA
017E 1698
0180 247E
test for Print Ready bit - ~as Print Head Fire Setup Done?
insert acceleration time/store time count done/notdone flag bit
Mov
A.GStR20
;get the status b~te - prep for prnt
JOb
RdyPr2
; if Ready Print bit set call PHFire
Jmp
SkpPHF
else skip Print Head Fire
Call
PHFire
iprint head solenoid fire ~outine
788
789
790
791 RdyPr2:
79'il PNRd~'il:
793 SkpPHF:
794 tTruW'il: JTF
795
JMP
,JUMP TO SM ERROR
, LOOP TO TLOOP3
NXTPHZ
tTruW2
796
0182 2300
0184 62
0185 55
0186
0187
0189
018A
018C
018E
0190
0191
0193
0195
0196
0197
FA
4308
AA
5690
16AC
248A
00
5695
248A
65
42
AI
0198 FA
0199 F'ilA7
0193 26AC
0190 FA
019E 1'il4C
OIAO 4302
01A2 53BF
0lA4 AA
0lA5 244C
0lA7 FA
0lA8 1'il4C
OIAA 24AC
OIAC 5437
OIAE FA
OlAF F2B3
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
Step into failsafe/startup time~ setup - T does not
occurs before Std Time timeout. load failsafe SM p~otection
time and wait for failsafe timeout or T.
If T occurs
output phase immediately after T verify.
FAILSF: MOV
MOV
STRT
A.*FailTm
T. A
T
set the
Mov
ORL
Mov
TLOOP3: JT1
JTF
JMP
tCHK2:
NOP
JTI
JMP
StrTml: Stop
Mov
MOV
Status bit for Store time test
iget th~ status byte
A.GStR20
iset Failsafe/constant time flag
A.*FSCTm
istore the status byte
GStR20.A
,
,LOAD TIMER W/~15. OmS
SM PROTECTION TIMEOUT
,START TIMER
, 15 THIGH
,IF TIME OUT GO SM ERROR
;LOOP UNTIL T HIGH OR T-OUT
, WAIT
j Jump
out and store elapsed time
JMP TO FAILSF LOOP
istop the failSafe Timer
iread the timer
.Store the time read in indexed addr
- next entry to AID Memorize Time
routine will add time constant to it
tCHK2
DSLECT
TLOOP3
StrTml
TLOOP3
TCnt
A.T
C!TStrRO.A
Test is CR Stpr Mtr Drive is finished prior to next phase output
NXTPHZ:
test for forward I reverse phase start indirect index to load
Mov
A,GStR20
istare stat byte
.JB7
FDrive
Reverse
t~st for Reverse Stpr Mtr Drive procedure exit
ALWAYS drive the CR to the left most HOME position
~NTO
EOLn
;test if home position Jmp stop
Mav
A.GStR20
.get the status byte
.JBO
StrtT
itest Ready stat bit:
if bit 0 = 1 then Print More
A, .. DoNotP
;set the do not print flag
ORL
lclear Print Ready bit
ANL
A,"ClrSnk
Mov
GStR20.A
isave the status byte
Jmp
StrtT
icontinue CR 8M drive
- only exit is HR
Forward
test for Forward Stpr Mtr Drive procedure exit
FDrive:
Mov
A.GStR20
,get the status b~te
JEO
StrtT
,test Ready stat bit:
if bit 0 = 1 then Print More
Jmp
EOLn
else Jmp to End Of Line exit
;Jump to start timer again
841
842
843
844
845 DSLECT:
846 EOLn:
Call
DeclSM
847
848
test for fo~warJ
849
Mov
A, GStR20
850
JE7
FDrvFS
.call Sptr Mtr Deceleration
reverse phase start indirect index to load
;store stat byte
i Jrnp to f drive flag set
230795-39
9-119
inter
AP·161
0101 53FD
0103 530F
01B5 53DF
01B7 AA
01BB 83
851
ANL
A."OkPrnt
852
853
854
update tho status byte
855 FDrvFS: ANL
A."ClrSnk
B56
857
ANL
A.4INAtSpd
858
Mov
QStR20.A
859
RET
860
0200
0202 B92F
0204 BCOB
0206 FA
0207 4310
0209 AA
020A 4436
020C EC26
020E FA
020F 4320
0211 AA
0212 3226
0214
0215
0216
0218
0219
D5
FA
4340
AA
F21F
021B B92F
021D 4421
021F B980
0221 DD51
0223 BDOI
0225 C5
0226 722C
0228 FD
0229 AI
022A 4435
022C Fl
022D 03C8
022F 6D
0230 Al
0231 FA
0232 53F7
Ok Print
;clear Print Ready bit
; set the Status bit for Store time test
;Clear At Print Speed Bit
; save the status byte
861
PG
862
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
863
0200 920C
.reset print flag -
; only if printing R-to-L
Stepper Motor AmI. TimeStomge
864
* * * * * * * * * '* * * * * * *
* * *
* *' * * * * *
865
866
ORG
200H
867
Entry has G.n Stat Byte in A
868 ADMmTS: JB4
DADlnt
; is AID init done - then Jmp
869
870
1st Entry initializes, the AID Time store working registers
871
Mov
TStrRO.*SMBf5t ;Load the Stpr Mtr Buffer Start Addr
872
Mov
CntR40 •• ASBfSz .Load the Buffer Size
Mov
A.QStR20
.get the status byte
873
874
ORL
A."ADlntD
;set not 1st Accel Entr~ Flag
875
Mav
GStR20.A
.stare the status byte
876
~mp
AOExit
;exit - 1st entry has not generated
877
a closed time window
878
879
Step the AID Store count
880 DAD~nt: D~NZ
CntR40. StorCt
i dec Times to store count
881
; if not 0 store the count
ielse at end-set done fl~g
882
883
Mov
A.GStR20
.get the status byte
884
ORL
A.4IAtSpdF
;set at speed/no more to store flag
885
Mov
GStR20.A
;store the status byte
B86
887
Initialize Char Print Registers:
if printing enabl~d
B88
JBl
StorCt
; if 00 Not Print stat bit set
B89
Skip the Char register ioit
890
891
Initialize all Char Reg's
892
Test for L-to-R (forward) or R-to-L (reverse) printing
893
SEL
RBI
894
Mav
A.ChStRl
;get the status byte
895
ORL
A.4ICHlntD
iset Char Init Done flag - bypass
896
Mav
ChStRl.A
; save the status byte
897
.IB7
LdCBRI
;test Chr Stat Bvte Returned
898
if bit 7 = 1 then Print L-to-R
Mov
CAdrRl.4IRCBfIS ; load char reg w/char bufr strt R-to-L
899 LdCDR:
900
.Imp
LdCBR2
901
902 LdCBRI : Mov
CAdrR 1. 4IFCBfIS iload char reg wlchar bufr strt L-to-R
903
904 LdCBR2: Mov
CCntRI •• ChDfIS ; load char cnt reg w/char bufr size
905
;set the chr dot column cnt
Mov
CDtCRl.4I01
906
SEL
RBO
907
908
Test for t > TC or t < Tc
909 StorCt: ~B3
FailST
.test for failsafe time switch
910
911
t < Tc = store Time Constant in use
912
Mav
A.TConRO
;Get time constant currently in use
Mav
@TStrRO,A
;Memorize/Store the time - indirect addr
913
914
.Imp
ADPRet
915
916
t > Tc = store Time Constant + FailSafe Time Elapsed
917
[see Accel/Cnst Speed/Decel WaveForm]
918
e~uation is:
Trd - FailSafe Time = Tx
=> Trd + Cpl(FailSafe Time) = Tx
919
920
Tx + Tcnst = T
Store/Memorize T
921
922
923 FaUST: Mav
A.i!TStrRO
iget the stored tim~
924
Add
A,.FTCpl
;2's cpl add
A, TConRO
;Add: Time stored + Time constant
925
Add
926
currently in use
(!TStrRO.A
iMemorize/Store the time
927
Mov
928
Reset the Status lJ.it for Store time test
929
930
Mov
A.GStR20
iget the status byte
931
ANL
A.4IClrFSC
ireset F,ailsafe/cDnstant time flag
932
assumes entry via constant time
230795-40
9-120
AP-161
0234 AA
0235 C9
0236 83
933
934 ADPRet
935 AOExit:
Mov
Dec
Ret
GStR20,A
TStrRQ
i
j
store the status byte
step the AID time data store addr
936
937
PG
938
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
940
941
* * * * * * * * * * * * * * * * * * * * * * * *
939
Carriage Stepper Motor Deceleration
942 Oec: 15M:
0237 0925
0239 BCOA
02313 FB
023C E3
023D
023F
0240
0241
0242
0243
B820
40
3C
Fl
62
55
0244 19
0245 FA
0246 F252
0248
0249
024A
024C
024E
0250
CB
FB
524E
445A
BB03
445A
0252 IB
0253 FB
0254 5258
0256 445A
0258 BBOO
02~A
FB
025B E3
025C
025E
025F
0261
0263
0264
B820
40
1663
445F
3C
EC41
0266 B821
0268 FB
0269 AO
026A B478
026C B490
026E 83'
943
SetUp the Deceleration registers
944
f10v
TStrRO,8SMBEnd
iLoad the Stpr Mtr Duffer End Addr
945
Mov
CntR40.*OSBfSz
;Load the Buffer Size
946
MoV
A,PhzR30
;get phase index address
947
MovP3
A.@A
.get phase from indexed address
948
patch together the CR last and LF next phase bits
949
Mov
TmpROO.8LastPh
; load Last Phz psuedo reg to Temp Reg
950
oRL
A.@TmpROO
;patch together CR existing & new LF
951
MoVD
P4.A
;oUTPUT BITS
952 StrtTD: MoV
A.@TStrRO
;get time from indexed data memor~
953
MoV
T.A
; load timer
954
STRT
T
; START TI MER
955
Inc
TStrRO
;step the Memorized time addr index reg
956
test for forward I reverse phase start indirect index to load
957
Mev
A,GStR20
,store stat byte
958
JB7
DclF2
959
960
re .... erse:
961
Set up for next phase bit output before entering timing loops
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
PhzR30
A,PhzR30
; decrement the phase addr
;Get the phz data addr
JB2
DRZreP
;CHK FOR COUNT BIT ROLLOVER
JMP
DRZreP: 110V
Jmp
;
DNxtPh
PhzR30.8RStCRP; ZERO CR SM PHASE REGISTER
Dc IR2
forward:
Set up for next phase bit output before entering timing loops
Inc
PhzR30
; increment the phase addr
MOV
A.PhzR30
;Get the ph: data addr
JB2
DZroPh
;CHK FOR COUNT BIT ROLLOVER
JMP
DNx tPh
; skip adr index reset
DZroPh: 110V
PhzR30.8FStCRP ; ZERO CR SM PHASE REGISTER
Dc IF2:
DNx tPh:
Dc IR2:
TLoopD:
N. tPD2:
SetRN:
DMExit:
; set up for next phase shift
A,PhzR30
iget phase index address
Mo .... P3
A,@A
;get phase from indexed address
patch together the ~R last and LF next phase bits
Mov
TmpROO. ttLastPh
i load Last Phz psuedo reg to Temp Reg
oRL
A,@TmpROO
;patch together CR existing ~ new LF
MoV
JTF
JMP
MoVD
DJNZ
N.tPD2
TLeopD
P4.A
;JMP oN'TIME OUT TO NEXT PH
;LooP UNTIL TIME OUT
; OUTPUT BITS
CntR40,StrtTD
iExit Test
Set Storeage of next phase data in psuedo addr. This insures
next phase is sequence correct for stpr mtr drive direction
Mov
TmpROO,ttCPSAdr
,get Phz Storeage Addr psuedo reg
MOV
A.PhzR30
;get Phz data
Mov
@TmpROO,A
; store CR Next phase index addr
Call
DlyLng
Call
RET
DeSISM
996
PG
997
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
998
0300
Dec
MOV
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
lOll
Stepper Motor Phase Shift Definitions
All program procedures call this data.
* * * * * * * * * * * * * * * * * * * * * *
oRG
*** * *
* * * * * *.*
* *
*
300H
DEFINE PHASE ADDRESSES:
THE PHASE DATA IS ENCODED TO THE ADDRESS CALLED DURING THE
STPR MTR ENERGIZE SEQUENCE CORRESPONDING TO THE NEXT PHASE
OF THE SEQUENCE REQUIRED,
CARR AGE MOTOR ENCODING:
FORWARD
REVERSE
LEFT-to-RIGHT
RIGHT-te-LEFT
230795-41
9-121
AP-161
0300
0301
0302
0303
01
03
02
00
0308
0308
0309
030A
0300
04
OC
08
00
1012
1013
1014
1015
lOll.
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
Reverse direction ENCODINQ is t~e •• me bVtes acc •• sed in
reverse direction
DB
DB
DB
DB
CRMFPI
CRMFP2
CRMFP3
CRMF'P4
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
LF MOTOR PHASE ENCODE
~
DECODE:
ORG
308H
DB
DS
DB
DB
LFMFPI
LFMFP2
LFMFP3
LFMFP4
1034
PG
1035
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
103b
Accel/Decel I Character Handling Test
1037
* * * *TEST
* * >* * Is* CR
* *Stpr
* * Mtr* At
* *Speed
* * * 77* * * * * * * * * * * * * * *
103B
1039
Ves - SetUp do Character Proc •• sing
No - C.lculate' I Store the Acceleration Phase Shift Time (11)
1040
1041
1042
1043 ADPTst: Mov
A.GStR20
iget the st.tus bVte
1044
itest if Stpr Mtr At Speed
.ISS
PHFSot
1045
Jmp to Prnt Head Fire Setup
1046
ielse C.II Aceel/Decel M.mor~ Time Store
.Imp
ADMmTS
1047
1048
*
030C FA
0300 B211
030F 4400
1049
0311
0313
031'
0317
0318
031A
031B
031C
0310
2668
326A
D21B
FA
4340
AA
05
FA
D23A
Fi
03F3
C626
6437
FA
F22B
0329 6432
*
* *
* * ** * ** * ** * * ** * ** * * ** * ** ** * ** * ** ** * ** *
Process Characters for Printing
1050
* * * * * * * * * * * * * *
1051
1052
Character dot matrix - normal char
1053
d
Dot Column
1054
b = Blank Column
1055
b d d d d d
1056
(Char MatT'ix)
1057
1058
000 o b
1059
d
000 I
1060
001 o d
1061
001 I d
1062
010 o d
1063 I
010 I d
1064
1065
Ret,...n
1066 PHFSet: .INTO
i if R-O nat ,... •• d~ to print-exit
1067
NPRet
; if ~o Not Print stat bit s.t - EXIT
.IBI
i if bit pT'eviousl~ set-skip setting it
106B
SinkSt
.lSI.
1069
A.GStR20
iget the st.tus byte
Mov
1070
A,ISnkSet
iset P~nt Read~ Sink bit
ORL
1071
GStR20.A
isave the status bute
Mov
1072 S;nkSt: SEL
RBI
;get cha,. status registe,. addT'
1073
Mov
A.ChStRI
I test Cha~ Init Done,
1 • Print Dot
1074
PageCk
.lSI.
o .. Qat Cha~
1075
1076
1077
031F
0320
0322
0324
0326
0327
FORWARD (CLOCKWISE)
Forward direction ENCODING:
I
** *
PG
107B
Call for Individual ch.,....cter proce.sing:
mid line test 1f CR/(LF)
1079
lOBO
lOBI QetChr:
IOB2
test for CR/(LF) if it is the t.st position in the line
IOB3 CRChCk: Mov
A.@CAdrRI
iget character
Itest for Carriage Retuf'n
10B4
ADD
A•• CRCpl
if CR go .ervice it
IOB5
.IZ
CrLnCk
i if not CR Insef't Space Cha,.
AsciCl
IOB6
.Imp
A.ChStRI
.get char status register addr
IOB7 CRLnCk: Mov
itelt Chr Stat Byte Returned
.ID7
HlfLn
10BB
i f bit 7 • I th~n print L-to-R
IOB9
.Imp
SpFIIl
j if R-to-L
print skip exit upon CR detect
1090
1091
230795-42
9-122
inter
0328 FD
032C 03D9
032E F632
0330 648A
0332 97
0333 2320
0335 6438
0337 FI
0338 7498
033A
0338
0330
033F
0341
FA
8241
F4EB
6443
D4FO
AP-161
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
IIII
1112
1113
1114
1115
1116
0343 EB61
0345
0346
0348
0349
034B
034D
034F
FA
53BF
AA
ED 58
53FD
53FE
AA
0350
0351
0352
0354
0355
0356
CS
FA
53FE
AA
D5
6468
0358 FA
0359 F25E
0353
035C
035E
035F
19
6468
C9
6468
0361 FA
0362 F267
0364 CC
0365 6468
0367 IC
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
ll42
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1151.
1157
1158
1159
111.0
1161
1162
1163
1164
1165
1166
1167
1168
1169
if L-to-R printing exit the line if less than 1/2 line printed
Mev
A. CCntR 1
ADD
JC
LnPad
A,~HlfCpl
J load char cnt reg wlchar bufr size
iadd the ~'s cpt of 1/2 chr Duf size
; if CB)1/2 full set CR/LF stat bit for pad
; If CB<1/2 set buffer full stat bit
Jmp
MdLnEx
imid-line exit
Clr
Mov
Jmp
C
iclear
A,.Space
ChIsrt
i
A, I!CAdrRI
GCharl
; get character
leall the char lookup/trns table
5pFill:
LnPad:
AsciCl: Mav
ChIsrt: Call
;
i
carr~
flag
insert a space char
char inserted Jmp over get char
----------------------------------------------------------------
PageCk:
fetch the char dot column data
ipage test for balance of char
A.ChStRl
,get the status byte
J85
FxJmpl
;fix Jmp over page boundries
Call
ChrPg2
;Ascii char 50 - 7F Hex
Jmp
MtxTst
; Jump to Matrix Test
Call
ChrPgl
,Ascii char 20 - 4F Hex
fall thru to print matri.
and CB count tests
Mov
Fx.Jmpl:
PG
test the Char dot column print matrix count and Char buffer count
MtxTst:
DJNZ
CDtCRI,PrntDt
Mov
ANL
Mov
DJNZ
ANL
ANL
Mov
ChStRI,A
CCntR I, NotLCh
A,IINCBFln
A,IIClICBR
ChStRI, A
SEL
Mov
ANL
Mov
SEL
Jmp
A,Ch5tRl
A,~ClntND
R80
"A,G5tR20
A,~NotRd~
GStR20,A
RBI
Retrn
,test for dot color blank
; status b~te in A upon entry here
;get the status byte
iset Char Init NotDone stat Flag
istore the status b~te
; dec char cnt-Jmp if Not Last Char
i if 0 reset stat bit Not CD Full Line
.reset CD Reg Jnit Flag - do Init
i save the status b~te
,get Gen Status register addr
iclear the read~ bit
• store the General Status Byte
; EXi t
Test for L-to-R (forward) or R-to-L (reverse) printing
(see GCharl ASCII char code translation procedure)
NotLCh:
Mov
JB7
StpCh I:
Inc
Jmp
5tpCh2: Dec
Jmp
;A contains LR/RL bit properly set
i get char status register addr
j test Chr 5tat B~te
Returned
i f bit 7 = I then Print L-to-R
; Increment char data memory ad dr.
A,Ch5tRI
StpCh2
CAdrRI
Retrn
CAdrRI
Retrn
; Decrement char data memory addr.
fall thru to Get Char
Re-Entry E.it point for same char:
(before returning step the matri.)
Test for L~ta-R (forw.rd) or R-to-L (reverse) printing
(see GCharl ASCII char code tr~nslation procedure)
PrntDt:
PrnDir: Mov
JB7
A,ChStRI
5tpCD2
StpCDI: Dec
CDotRI
Jmp
StpCD2: INC
Retrn
CDotRI
get char status byte
test Chr Stat Byte Returned
if bit 7 = 1 then Print L-to-R
reverse step char dot col index
addr if R-ta-L print
skip over L-to-R print addr inc
for~ard step char dot -col index
addr if L-to-R print
EXIT
PG
230795-43
9-123
inter
0368 CS
0369 83
036A OS
036D FA
036C F27C
036E
036F
0370
0372
CS
FA
53BF
83
0373 027C
0375 4340
0377 AA
0378 0807
037A 6488
037C E888
037E FA
037F 530F
0381 ·AA
0382 C5
0383 FA
0384 53FE
0386 AA
0387 83
0388 C5
0389 83
038A
038B
0380
038F
0390
0391
0392
0394
0396
0397
FA
53FO
53FE
AA
C5
FA
4302
53BF
AA
83
AP-161
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
I1B2
IIB3
l1B4
IIB5
I1B6
1187
118B
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
120B
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
0398 AE
0399
0398
0390
039F
03AO
03EO
F69F
64C9
97
FE
03Al 03BO
03A3 F6AE
03AS
03A6
03A8
03A9
03AA
03AC
FA
4320
AA
FE
03EO
64B8
Character Print SetUp Exit Procedures
Clean Standard Exit
etrn:
NPRot:
SEL
Ret
RBO
,
'
.
,EXIT - return wi Reg a.nk 0 Reset
Do Not Print ex i t:
SEL
RBI
A.ChStRI
Mav
.JD7
SkpNPI
set Stpr Mtr drive routine count loop
;get"the status byte
.test print direction
Reverse
SEL
RDO
Mav
A, GStR20
j~~t the. status b~te
;reset the print read~ bit- skips PHFire call
A.lICI~Snk
ANL
Ret
Forward
..JDb
SkpNPI
; test· for first PHFSet entT'~ reg init
Initialize registeT variabltts upon" fiT'st'entr~
end of count clears char to print -bit in status
SkpNPI:
NSetEx:
NPE, i t:
ORL
Mav
Mov
A•• ChlntD
ChStRl.A
TmpRIO •• 07H
..Jmp
NPEx i t
O.JNZ
Mav
ANL
Mav
SEL
Mav
ANL
Mav
TmpRIO. NPExit
A.ChStRI
A•• ClntNO
ChStRI.A
RBO
A.QStR20
A•• NatRd~
QStR20.A
~vte
,set Char Reg lnit Done stat bit
isave the status byte
i load CR stpr mtr count during NoPrnt
,get the status byte
- chQr inlt.not done
isave t~e status byte
i~eset
iget Ge~',Stat~s register addT
,
iclear the ready bit
istore the QRner.l Status
B~te
Ret
SEL
Ret
RBO
Mid-Line Exit
MdLnEx:
EXIT Mav
ANL
ANL
Mav
SEL
Mov
ORL
ANL
Mav
Ret
if CR and nat
A.ChStRI
A.IINCDFln
A.IICIICBR
ChStRI.A
ROO
A.ClStR:10
A•• OoNotP
>
A,.CIrSn.
QStR20.A
1/2 li~.
dorie,during L-to-R print
.get the status byte
; if· 0 reset stat bit Not CB Full Line
ir~set C~ Re~ Init Flag - do Inlt
isave the status byte
;get the RBO status byte
iset the Do Not Prin~ FlagCfor RAceel)
;reset the print ready bit-exit FAceRI
; save the status byte
PG
1222
1223
Character Dot Generatar Math
1224
Look-up Table Page Vectoring
Print Head Firing
1225
1226
1227
1228 QCHARI: MOV
St~CRI. A
,STORE THE CHAR
1229
1230
SCT'een fa~ printable char (char +(cpl 20 ~e' +' 1
EO Hex))
1231
AOD
A.lIOEOH
1232
.JC
PrntCh
'.
,
,
1233
CntlCh
i Jmp ta:c~~trol char lookup table
Jmp
1234 PrntCh: Cl~
C
lclear c.r~~ flag
123~
Mav
A.St~CRl
;get the char again
1236
1237
screen for char page [char +(cpl 50 Hex + I = DO Hex)]
1238
if carrV char on page 2 ,else page 1
1239
ADD
A.lIOBOH
1240
Page2
.JC
1241
1242
Page
Character -- ASCII ,20 Hex. thru 4F Hex
1243
Correct offset for lookup table page
1244
{(char + EO He.)*5 = Page 1 indeX_.ddT)
1245
1246 Pagel:
Mov
A.ChStRI
iget the status bvte
1247
O~L
A.*ChOnPl
is.t the page rentrv flag bit
Mav
ChStRI. A
;store the,status bVte
1248
1249
iget the char _gian
A.St~CRl
Mav
12~0
ADD
A•• OEOH
,set page 1 relative 00 offset
1251
Jmp
Multi5
i Jump to address math function
1252
=
----------------------------------------------------------------
230795-44
9-124
AP-161
03AE
03AF
03BO
03B2
03B3
03B4
030b
97
FA
530F
AA
FE
03BO
b4B8
03B8
0309
03BA
03BB
03BC
AE
E7
E7
bE
AC
12S3
1254
1255
12Sb
12S7
1258 Page2:
1259
1260
12bl
12b2
12b3
1264
12bS
12bb
03BO FA
03BE F2C4
03CO FC
03CI 0304
03C3 AC
03C4
03C5
03C7
03C8
FA
4340
AA
83
03C9 83
03CA OS
03C3 FB
03CC 9602
03CE
0300
0302
0304
0305
0307
0308
0309
BBOb
6408
2340
3A
23CO
3A
CS
83
12b7
12b8
1269
1270
1271
1272
1273
1274
1275
127b
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
129b
1297
1298
1299
1300
1301
1302
1303
1304
1305
130b
1307
1308
1309
1310
1311
0400
0402
0404
0406
BC04
B822
2308
AO
0407 BEOI
0409 841B
CIT
C
; clear
Mov
AnL
Mov
Mov
ADD
Jmp
A.ChStRI
;get the status byte
.set the page rentry flag bit
; store the status byte
; get the char agian
.set page 2 relative 00 offset
ifall thru to address math function
Compute
MUL TIS; Mov
RL
RL
ADD
MDV
A •• ChOnP2
ChStRI. A
A,StrCRl
A.1I0BOH
Multi5
carr~
flag
character page offset dot pattern index addres5
.store the Iero offset char
,MULTIPLY CHR BY 5 TO
FIND THE ADDRESS
,ADD I TO COMPLETE SX
A.StrCRI
,SAVE THE ADDRESS
CDotRl. A
StrCRl. A
A
A
Test fOT L-to-R (forward) or R-to-L (reverse> printing
(see QCharl ASCII char code translation procedure)
Mov
JB7
A.ChStRl
LRPrn
MOV
ADD
A.CDotRI
A.tlRLPShf
MOV
CDotRI. A
; get char status byte
; test Chr Stat B~to Returned
i f b'i t 7 = I then Print L-toR
• get the char index addr
, .dd char offset - start at end
; -of chaT'. pT'int it R-to-L
, SAVE THE ADDRESS
Set the status byte for Character SetUp done
LRPrn:
; get the status byte
Mov
A.ChStRI
ORL
A.IIChIntD
i set 1st char col test bit
Mov
ChStRI.A
i store the status b~te
Ret
i return \II/status b~t. in A
test for non printable ch,aracters goes here
CntlCh; Ret
=0
* * * Print
* * * Head
* * *Fire
* * * * * * * * * * * * * * *
* * * * * * * * * *
* * *
* * * * *** * * * * * * * * * * * * * * * * * * * * *
Entry point for print head solenoid firing
te5t fa,. status byte for dot/blank column position
SEL
RBI
Mov
; set the chr dot column cnt
A.CDtCRI
; if char cnt not o - Fire He,ad Sol.
JNZ
Fire
; if Chr Oot Cnt O. reset the
SetCnt: Mov
CDtCRI.IINDtCCt
char dot column count
Jmp
Retrnl
; sk ip PH Fire
Fire:
MOV
A.IIPT,.gLo
'get tho Prot Head Trigger b",te
OUTL
P2.A
,FIRE PRINT HEAD
A,
..
PTrgHi
MOV
j get
the Prnt Head Trigger byte
, FIRE PRINT HEAD
P2.A
OUTL
Retrol: SEL
RBO
, EXIT - return "'/ Reg Bank o Reset
Ret
PHFire:
-
1312
PG
1313
* * * * * * * * * * * * * * * * * * • • * * * * * * * * * * * * *
1314
0400
Page 2 Character -- ASCII 20 Hex t~ru 4F Hex
Correct offset for lookup table page two's complement
of ASCII chr code LookUp Table page base char of 50H plus
char * 5 {(char + BO Hex)*5 = Page 2 index addT)
PaperFeed Stpr Mtr Drive
***
1315
* * * * * * * * * * * * * * * * * * * *** ** * * * * * * * ** * *
131b
1317
ORG
400H
1318
Init psuedo register \&lith LF inderect addr start - subse~u.nt
1319
exchanges of the psuedo register will ~ield correct value
1320
CntR40.IIILFCNT, INIT PHASE COUNT REG
1321 InitLF; MOV
Mov
TmpROO,.LP5Adr iget Phz Inderect Addr psuedo reg
1322
MOV
A,.StLFF
iget LF starting addr
1323
Mav
@TmpROO,A
istore LF phase index addr start
1324
in psu.do register
1325
Mav
LnCtRO.*LineCt iset line count reg for 1 In
132b
i
enables exit following LF SM init
1327
~mp
LfDrvl
i Jump over line/form feed amd variable
1328
line spacing tests & setups
1329
1330
LineFeed / FormFeed Drive
1331
*
230795-45
9-125
intJ
040B BCIB
0400
040E
0410
0412
0414
0415
FA
5214
BEOI
841B
FE
37
0416 0301
0418 0342
041A AE
041B
0410
041E
041F
0421
B821
FO
E3
0820
AO
040!0!
040!4
0425
040!6
0822
FO
AD
B098
0428 0!306
042A 3D
042B FB
042C E3
0420 B820
042F 40
1332
1333
load 'step count constant 90r standard line spat,iog
1334
1335
test for various line/inch spacing would go here
1336
(and removal of constant setup below)
1337
MOV
CntR40. ttLPISp8
i in i t cnt reg for standard line feed
1338
1339
LineFeed/FormFeed
Test
1340
A, GStR20
iget the-.statu5 b~te .
1341 LofDriv: t10v
i if linefeed" Jmp to cnt load
JB2
FmFd
1342
LnCtRO.tI;LineCt ;set line count reg for 1 line
1343 LnCtLd: Mav
i Jmp to Start of Drive
1344
Jmp
LfDrvl
,get the line count
1345 FmFd"
Mav
A.LnCtRO
;2'5 cpI Line Count
1346
Cpi
A
1347
A,.Ol
Add
iAdd 2's cpl fOT. Paging
1348
A... PgLnCt
Add
PgLnCt ~ LnCt = n Line. to move
1349
PgLnCt+(cpl(LnCt) = n lines to move
1350
i set the line count for FF
Mov
LnCtRO,A
1351
1352
for stablization of unused stpr mtr during CR stpr mtr drive.
1353
store the unused stpr mtr current phase bits
1354
TmpROQ,#CPSAdr
ig~t the CR phI stareage addr
1355 LFOrvl:· Mov
Mov
A,@TmpROO
;g@t the byute stored there
1356
MovP3
A.@A
;get the phz data byte
1357
Mov
TmpROO •• LastPh i load Last.Phz psuedo reg to Temp Reg
1358
Mov
@TmpROO,A
;store Last Phase bits - inde~ect
1359
exchange/store the phase register index addresses
1360
Mov
TmpROO •• LPSAd~ ;get PhI Inde~ect Addr· psuedo ~eg
1361
Mov
A,@TmpROO
;get LF last phase index addr
1362
Mov
PhzR30,A
iplace last LF phase index addr in PhI R@g
1363
MOV
TConRO,8LFTMRl ;Load time constant Reg
1364
1365
1366
Select the Stpr Mtr
,GET CR SM SELECT BITS
1367
MOV
A,ttSLF
MOVO
P5. A .
,SELECT SM [SCR80]
1368
1369
1370
1371
LineFeed / FormFeed Drive Loop
1372
1373
A.PhzR30
iget the ,hI reg indirect addr index
MOV
1374
A.@A
ido ind.irect get of phI bits
MovP3
1375
patch together the CR last and LF next phase bits
1376
TmpROO.*LastPh
i load Last PhI psuedo reg to Temp Reg
Mov
1377
ORL
A.@TmpROO
ipatch together CR existing & new LF
1378
start timer and step motor,
1379
P4.A
,OUTPUT BITS
MOVO
1380
1381 StrtLF:
;get time constant from rog
1382 STRLFT: MOV
A.TConRO
; load tho timer
1383
T.A
MOV
STRT
,START TIMER
1384
T
setup tho nlut phase to output
1385
, STEP PHASE DB ADDRESS
1386
Ph,R30
INC
1387
A,PhzR30
i get tho phase index address
MOV
; test phase
1388
Ja2
ZROPHL
1389
JMP
NXTPHL
1390 ZROPHL: MOV
Ph,R30.41STLFF
;re-init phase register
1391
1392 NXTPHL: MOV
A.PhIR30
;get the phz reg indirect addr index
1393
MovP3
A.@A
ido indirect get of phz bits
patch together the CR last and L~ next phase bits
1394
TmpROO,ttLastPh
i load Last Phz psuedo ~eg to Temp Reg
1395
Mov
1396
A.@TmpROO
ipatch together CR existing & new LF
ORL
1397
1398 TLoopL: JTF
NXPHLF
i Jrnp on time out to out~ut nxt phz
; loop until timer tim~s ·out
1399
JMP
TLOOPL
1400
1401 NXPHLF: MOVD
; step motor - OUTPUT BITS
P4.A
CntR40,St,.LFT
; test for end of phase count for line
1402
DJNZ
iprep for next line
1403
1404
test for various line/inch spacing would go here
1405
1406
MOV
CntR40 •• LPISpS ; init cnt reg for standard line feed
1407
D~NZ
LnCtRO.StrtLF
itest for end of line count
1408
iGet the status byte
1409
Mov
A.GStR20
1410
A,.LineFd
ireset for line feed
ANL
1411
GStR20.A
; save the status byte
Mov
1412
1413
store the phase. register index addresses
1414
Set LineFeed Stpr Mtr Next Phase index address
TmpROO,OLPSAdT' iget Phz StD~age Addr psuedo reg
1415 SetLRN: Mov
c
0430 3C
0431 FO
0432 62
0433 55
0434
0435
0436
0438
043A
IB
FB
523A
843C
BB08
043C FB
0430 E3
043E D820
0440 40
0441 1645
0443 8441
0445 3C
0446 EC31
0448 BCID
044A EE31
044C FA
0440 53FB
044F AA
0450 B822
230795-46
9-126
AP-161
0452
0453
0454
045b
FB
AO
B478
B490
0458 83
141b
1417
141D
141'1
1420
1421
1422
1423
1424
1425
142b ByPas 1:
1427
Mov
Mov
Call
Call
A.Ph,R30
IlTmpROO.A
DlyLng
D.SISM
iget the phase index address
LF Next phase index addr
; stOTR
Check if Char Buffer contains full line (eO char or nCh.r & CR)
exit Dther~i5e continue to r.~d in characters
Mov
A.GStR20
iget the stat byte
.JDI
B~P •• 1
; if Do Not Print Bit Set - EXIT
Call
CBFck
Ret
1428
PG
142'1
* * * * * * * * * * * * * * * * •
1430
Minor Software Subroutines
• * * * * * * * * * * * * * * • *
1431
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1432
1433
ORG
500H
1434
1435
143b
System initialization subroutines
1437
1439 Defalt:
143'1
1440
reset/set EOF status flag bit = 0
1441
SEL
RBI
1442
Mov
A,ChStRl
iget the char status b~te
1443
ANL
A•• ClrEOF
; clear the EOF flag bit
1444
Mov
ChStRl,A
i store the char status b~te
1445
Mov
TmpRI0.IPTAscS iget the Ascii code tmp store addr
144b
Mov
@TmpRIO,*Ascii
; load the tmp star reg ~/ascii start
1447
SEL
RBO
1448
144'1
reset/set Ok-to-Print status flag bit = 0
1450
Mov
A.GStR20
iget the status b~t.
1451
ANL
A•• OkPrnt
ireset print flag - Ok PTint
1452
Mov
GStR20,A
isave the status b~te
1453
RET
1454 InitAI:
1455 AllOH:
145b
1457
CLEAR all outputs
1458
SEL
ROO
145'1
MOV
A•• OFH
,FORCE PORT HI - RI OF 555
14bO
MOVD
Pb.A
14b1
MOV
A•• OFFH
,TURN ALL PRNT SOL', OFF
14b2
OUTL
PI. A
14b3
MOV
A••PTRGHI
iprint head fire tirgger inactive
14b4
OUTL
P2.A
14b5
P2,.03
·ORL
iset eomm h~5k to ACK hi/Bus~ hi
May
14bb
GStR20 •• 00H
ielear the status registers
14b7
SEL
RBI
May
14b8
ChStRl •• 00H
14b'l
SEL
RBO
1470
RET
,RETURN TO INIT ROUTINE
1471
*
0500
0500
0501
0502
0504
0505
0507
050'1
D5
FA
53F7
AA
B823
B020
C5
050A
050B
050D
050E
FA
53FD
AA
83
OSOF
0510
0512
0513
0:115
051b
0518
051'1
0518
051D
051E
0520
0521
C5
230F
3E
23FF
3'1
23CO
3A
8A03
BAOO
D5
BAOO
CS
93
1472
0522
0523
0525
052b
FA
4302
AA
3b2A
0529 3402
052A 3422
052C 0474
052E 93
052F D97F
0531 D'I5D
0533 BOOO
1473
1474
1475
147b
1477
1478
1479
1480
1481
1482
1483
1484
1485
148b
1487
1488
148'1
14'10
14'11
14'12
14'13
14'14
14'15
149b
* *
PG
* * • Home
* * * Carriage
* * * * *I *Print
* * *Head
* * A5sembl~
* * * *
* * * * * * * * * * * *
** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* *"
CRHome: May
ORL
May
.JTO
RtoL:
A.GStR20
A•• DoNotP
GStR20.A
RtoL
Cell
C.ll
FAccal
RAtcel
Cdl
Rot
DlyVLg
iget the status b~te
isat the do not print flag
isave the status bQte
itest for position of PH •••• mbl~
drive accoTdingl~
Jd~ive CR Stp~ Mt~
ifind t~e logical left home CR position
;d.la~ a long time before continuing
* * * *Claa~
* * *Data
* *Memor~
* ******* * * * * **** * * *** * * ** **
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
***
At Po~erUp or Reset, follobling CR Ie LF Stpr Mtr Init, this
procedure clears data memory above RBO. Stack and RBt.
MOV
RO •• DMTop
,GET BUFFER START LOCATION [HEX]
MOV
Rl ••DMSIZE
ClrDM1: MOV
@RO ••OOH
,ZERO MEMORY LOCATION
,
ClrDM:
230795-47
9-127
AP-161
0535 C8
0536 E933
,053883
1497
1498
1499
1500
1501
DEC
O-lNZ
RET
RO
RI.CI~DMI
; d,ec buff:er.
loop
if not zero[endl
; RETURN TO IN IT ROUTINE
PG
1502
* * * Character
* * * * * Print
* * * TEST
* * * * * * * * * * * * * * * * * * * * * *
1503
1504
*
*
*
*
*
*'
*
*
*
*
*
*
* * * * * * * * *
* * * * • * ** *** * *
1505
1506 PrnTst:
1507
TEST
load t~e char buffer with successive increments of
1508
the ascii code start.
test for end of ascii
1509
printable chars and reinit the char stream loaded.
1510
1511 CTInt:
Mev
CAdrRl, *FCBfSt
j load
char ~eg wlchar bufl' strt
1512
Mov
CCntRI.tlChBfS, ; l'lad char cnt reg wlchal' bufr sile
1513 ChTst:
; Test char buffer fill wi th ASCII Char Code
1514
Mev
A,opnr71
j get
tho ascii char
1515
Mov
C!CAdrRI. A
; load data memory wlC'hal'
1516
DEC
CAdrRI
; Decremlmt dat memory location
1517
INC
opnr?l
; Increment Ascii char numbll!T'
1518
ADD
A. ttPAsEnd
; test for ascii cade end
-INZ
ChT'TGo
1519
• if not end Jmp _over code l'estaT't
1520
Mev
OpnR71. "Asc i i
1521 ChrTGo: DJNZ
CCntRl,ChTst
J dec buffer.
loop if not zeroCendJ
SEL
1522
RBO
1523
RET
; ELSE RETURN TO INlT ROUTINE
1524
*
0539 B97F
053B B050
0530
053E
0531'
0540
0541
0543
0545
0547
0549
054A
1'1'
AI
C9
IF
03B2
9647
BF20
E030
C5
B3
1525
054B
0540
0541'
0550
0552
0554
0555
0556
0557
05SB
0:"9
055A
0553
055C
055E
0560
BC04
230B
3D
BOCO
BBOO
FB
E3
3C
I'D
62
55
IB
FB
5260
A462
BBOO
0562
0563
0564
0566
0568
0569
FB
E3
1669
A464
3C
EC57
056B
0560
056E
0561'
0571
0573
B821
FB
AO
B47B
B490
83
0574 B87F
0576 A47E
0578 BBBO
057A A47E
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
153B
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
*
*
PG
* * * *CR *Stpr
* * Mtl'
* * *Power
* * On
* * Initialization
* * * * * * * and
* * *
* • * * * ** * * ** *
* * * * * * * * * * * * * * * '. * * * * * * * * * * * * * * * * *
This routine drives the CR or LF stpr mtr for four phase
shifts for initialization.
INITCR:
MOV
MOV
MOVO
MOV
MOV
MOV
MovP3
STRTTR:
ZroRg2:
N, tPhR:
MOVD
MOV
MOV
STRT
INC
MOV
-IS2
.IMP
r10V
MOV
TLoopR:
NXPHR1:
reonRO. tUntTm2
; POWER ON INIT STPR MTR
; load phase cnt reg for INIT
; GET CR SM SELECT BITS
; SELECT SM [SCR80]
,Load time constant Reg
Ph,R30.tlFStCRP
A.PhzR30
Ad!A
P4.A
A.TConRO
;get phase ,index register byte
; load indexed phase shift byte
; OUTPUT BITS
; GET TIMER CONSTANT
CntR40.tlPhCntl
A.tlSCR80
P5. A
; zero SM phase reg -
forward
T. A
T
Ph,R30
A.PhzR30
; START TIMER
;step phase index register
; CHECK THE PHASE COUNT REG
ZroRg2
N,tPhR
Ph 'R30. tlFStCRP
A. Ph ,R30
MovP3
AdM
..JTF
-IMP
MOVD
D-INZ
NXPHRI
TLoopR
P4. A
CntR40.STRTTR
; zero, SM phase reg -
for'waT'd
iget phase index register byte
; load indexed phase shift ,byte
;-IMP ON TIME OUT TO NEXT PH
;LOOP UNTIL TIME OUT
; OUTPUT BITS
store the last phase register index addresses
Mov
TmpROO •• CPSAdr
iget Phz Storage Addr psuedo reg
Mov
A.PhzR30
iplaci last CR phase index addr in Phz Reg
Mov
@TmpROO.A
store CR last phase index addr
Call,
DlyLng
Call
DeSISM
RET
1564
PG
1565
-------------------------______________________________________ _
1566
Time Delay Subroutines
1567
-------------------------______________________________________ _
1568
1569
Very Lang
1570 DlyVLg: MOV
TmpROO.tl7FH
; LOAD DELAY COUNT IN REG,
1571
-Imp
DlyST
1572
1573
Lang
1574 DlyLng: MOV
TmpROO.tlDlyCL
; LOAD DELAY COUNT IN REG,
1575
-Imp
DlyST
1576
230795-48
intJ
057C
AP-161
B830
057E 23CC
0580 62
OS81 55
0582 1680
OS84 OS
OS8S FA
OS86 9:28A
0588
OS8A
OS80
OS8D
OS8F
1469
C5
A482
E880
83
0590 230E
OS92 3D
OS93 83
IS77
IS78
IS79
1580
Not So Long - Short
DI~Sht:
1581 DlyST:
1582
1583
1584
IS8S
IS86
1587
IS88
IS89
IS90
1591
1592
1593
1594
1595
IS96
IS97
1598
1599
1600
1601
1602
1603
1604
1605
160b
=1607
=1608
MOV
TmpROO •• DI~CS
; LOAD DELAY COUNT IN REG.
Start O@!alJ
MOV
NxtTLd: MOV
STRT
DI~Lop:
JTF
; LOOP
Dl~TO
during time loop:
Char buffer fill
SEL
Mov
JB4
Call
SEL
JMP
DJNZ
RET
SkpCI:
DI~TO:
;GET MAX TIMER DELAY
; LOAD TIMER
; START TIMER
A, ttOl\jTim
T.A
T
RB 1
A.ChStRI
SkpCI
;get the ch~racter stat reg byte
test faT' normal char input
or skip if char prot test
;service the char buffer fill
IBFSrv
ROO
Dl~LOP
TmpROO.NxtTLd
idee delay count & test for exit
stpr Mtr Deselect
Stepper Motor DeSelect Routine
DESLSM:
; DESELECT LF/CR SM
SMEROR: MOV
A•• SMOFF
;GET LF/CR SM DE-SELECT BITS
MOVD
P5.A
; DE-SELECT CR SM
RET
SINCLUDEC:Fl:CHRTBL.OV1)
=1609
* * * * * * * * * *
* * * * * *
* * * *
Character Dot Generator Look-up Table Page 1
=1610
=1611
* * * * * * * * * * * * * * * * * * * * *
* * * * * * * * *
=lbl2 .
Character Table Page I, contains
=1613
0600
=1614
=1615
=1616
=1617
=1618
=1619
=1620
=1621
=1622
=1623
20H ----------------------------------------> 4FH
C.p)· ... S'l.I<'C)*+.-. 101234S6789: ; <=>?t!ABCDEFGHIJKLM ..
ORG
600H
Page 1
=1624
asc20
asc21
a5c22
asc23
asc24
asc25
asc26
asc27
i15c28
asc29
asc2A
asc2B
asc2C
asc2D
asc2E
asc2F
asc30
asc31
asc32
asc33
asc34
asc35
asc36
asc37
asc38
Character Dot Pattern Fetch
DB
DB
DB
DB
DB
DO
DO
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
7FH. 7FH. 7FH.
7FH. 7FH. 20H.
7FH. 78H.
6BH. OOH. 6BH.
SOH. S5H. OOH.
SCH. bCH. 77H.
19H. 26H. 26H.
7FH. 7FH. 7CH.
63H. 5DH. 3EH.
7FH. 7FH. 3EH.
5DH. 6BH. OOH.
77H, 77H. 41H.
7FH. 3FH. 4FH.
77H. 77H. 77H.
7FH. IFH. IFH.
SFH. 6FH. 77H.
41H. 2EH. 36H.
7FH. 3DH. OOH.
3DH. IEH. 2EH.
5DH. 3EH. 3bH.
67H. bBH. 6DH.
S8H. 3AH. 3AH.
43H. 35H. 36H.
7EH. OEH. 76H.
49H. 36H. 36H.
7FH,
7FH. 7FH
7FH, 7FH
7FH. 78H
OOH. 6BH
S5H. 6DH
IBH. IDH
59H. 2FH
7FH. 7FH
7FH. 7FH
SDH. 63H
6BH. SDH
77H. 77H
7FH. 7FH
77H. 77H
7FH. 7FH
7BH. 7DH
3AH. 41H
3FH. 7FH
36H. 39H
36H. 49H
OOH. 6FH
3AH. 46H
36H. 4EH
7AH. 7CH
36H. 49H
230795-22
9-129
inter
AP-161
,
-1706
=1707
=1708
=1709
-1710
=1711
=1712
=1713
=1714
l1li171:5
=1716
-=1717
=1718
-1719
=1720
=17:21
=17:22
=172a
-1724
al(39:
•• c3C:
11$(30:
asc3E:
,
,
,
,
=172~
-1726
asc3F:
as(40:
.,,41 :
• 5(42:
•• c43:
a5(44:
•• c45:
a.c46':
0I1c47:
•• c48:
•• ,49:
asc4A:
lI.c48:
.. ,(4C:
•• c4D:
asc4E:
• sc4F:
-1727
"1729
-1729
-1730
.5c4E:
t1.c4F:
End Page I
-
=1735
06FO Fe
=1743
=1744
-=1745
=1746
=1747
41H •
OOH.
OOH •
OOH.
41H.
OOH •
7FH •
SFH.
OOH.
OOH•
OOH •
OaaH,
SOH •
OOH.
41H.
,<
,:>
,?
,@
,A
,B
,C
,D
,E
,F
,Q
,H
, I
,,J
,K
,L
,N
; te.t
J test
,N
,0
--
Characte" Dot Pattern Fetch
---------------------------------------------------------------
MDV
MOVP
Ai CDotRI
A.I!A
I get ch .. ,. index addl'ass off ... t
;get column dot pat ern b~t.
this bit fix neces •• ,. .. to -not underline .ach chil"act.,.
this .aves fixing each bit in the look up table
ORL
OutL
RET
.. 1748
=1749
=1750
=1751
=1752
A,*SOH
PI. A
; char bit fix
'J
output the dot pattern
; .xit ..,ith byte in ace
--
Character Dot Pattern, Fetch
---------------------------------------------------------------------
PAGE 2 -- Character Dot Generator Look-Up Table
=17~3
-1754
-=1755
---------------------------------------------------------------------
Character Table Page 2, contains
=17~6
:a1757
=17:58
=1759
=1760
OOH •
,9
a6H. 36H, 56H. 61H
7FH. 6BH. 7FH. 7FH
aFH. 4BH. 7FH. 7FH
6BH. SDH. aEH. 7FH
bBH, bBH, 6BH. 6BH
3EH. SDH. 6BH. 77H
7EH. 26H. 7AH. 7DH
aEH. 22H. a6H. 71H
6DH. 6EH. 6DH. OaH
a6H. a6H. a6H. 49H
aEH. aEH. aEH. SDH
3EH. aEH. SDH. baH
36H. a6H. a6H. a6H
7bH. 76H. 76H, 76H
aEH. aEH. 2EH. ODH
77H. 77H. 77H. OOH
3EH, OOH. 3EH, 7FH
aFH. 3FH. aFH. 40H
77H, bSH, ODH. aEH
aFH. 3FH. 3FH. 3FH
7DH. 73H. 7DH, OOH
OdfH. OeIH, Of7H. a.aH
OdfH. O.fH, Of'7H, SOH
7BH. 77H. 6FH. OOH
3EH. 3EH. !lEH. 41H
Charac ter Dot Pattern Fetch
=1736
=17a7
=1738 ChrPgl:
-17a9
=1740
-1741 J
-1742
06F2 4380
06F4 a9
06FS 8a
a9H.
7FH.
7FH.
77H •
6BH.
7FH.
79H.
41H.
OaH.
---------------------------------------------------------------------
=1731
=1732
-17a3
=17a4
06Fl A3
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
. • Ic3A:
a.c38:
:50H
I
-----------------------------------------:..>
7EH
NOPGRSTUVWXYZC \ ] .... _(7 )abcdefgh i J k ImnopqrstuvwxlJ z (I)""
=1761
=1762
=176a
0700
=1764
ORG
700H
=1765
=1766
=1767
Page 2 -- Character Dot Pattern Fetch
«<
Actual assembled chilrilcter t.ble· code not li,ted :>:>:>
a1769 I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - __________________ _
-1770 SNoLIST
-1818 .List
=1819
Listing b.low is for reference only. ,actual code is not listed
""1820
at assembly 'time.
-1768
=1821
I
-1822
------------------------------------------------------- --------------
=182a
ilsc50
ilscSI
ilsc52
ilsc53
ilsc54
asc:55
ilseS6
a.c57
ilseSe
.sc59
=1824
=1825
=-=1826
=1827
=1828
-1829
-1830
=1831
&1832
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
OOH.
41H.
OOH.
S9H.
7EH.
40H.
60H.
OOH.
ICH.
7CH.
9-130
76H. 76H.
aEH. 2EH.
76H. 66H.
a6H. a6H.
7EH. OOH,
aFH. aFH.
5FH. 3FH.
5FH. 67H.
6BH. 77H.
7BH. 07H.
76H.
5EH.
79H
P
2l<~
G
'6H, a9H
R
S
T
U
V
36H.
7EH.
3FH.
5FH.
5FH.
6BH.
7BH.
4DH
7EH
40H
60H
OOH
ICH
7CH
W
X
y
230795-50
infef
Ap·161
iI!i.c5A
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
ilscSB
ilsc5C
ascSD
ascSE
asc5F
asc60
asco1
a5(62:
asc63:
a5c64:
a5c65:
.:I5c66:
asc67;
a5c68:
a5c69:
asc6A:
asc6B:
asc6C:
ascbD:
ilsc6E:
asc6F:
a5c70:
asc71 :
asc7:2:
a5c73:
a5c74:
a5c75:
a5c76:
asc77:
asc7B:
asc79:
asc7A;
A5C7B:
A5C7C:
A5C7D:
A5C7E:
07EB FC
07EC A3
07ED 4380
07EF 39
07FO 83·
=1873
=1874
=1875 ChrPg2:
=187b
=1877
=1878
=1879
=1880
=1881
=1882
=1883
1884
1885
DB
DB
DB
DB
DB
MOV
MOVP
IEH.
OOH.
7DH.
7FH.
bFH.
3FH.
7DH.
ODFH.
OBOH.
OC7H.
OCFH.
OC7H.
OF7H •
OF7H.
080H.
OFFH,
ODFH.
OFFH.
OFFH.
087H.
OB3H.
OC7H.
084H.
OF7H.
OFFH,
OB7H.
OFBH.
OC3H.
OE3H.
OC3H.
OBBH.
OFFH.
OBBH.
07FH.
OFFH.
03EH.
Ob7H.
2EH. 3bH. 3AH. 3CH
3EH. 3EH. 3EH. 7FH
7BH. 77H. bFH. 5FH
3EH. 3EH. 3EH. OOH
77H. 7BH. 77H. bFH
3FH. 3FH. 3FH. 3FH
7BH. 77H. OFFH. OFFH
OABH. OABH. OABH. OB7H
OB7H. OB7H. OB7H. OCFH
OBBH. OBBH. OBBH. OBBH
OB7H. OB7H. OB7H. OBOH
OABH. OABH. OABH. OB7H
OBIH. OFbH. OFEH. OFDH
OABH. OABH. OABH. OC3H
OF7H. OFBH. OFBH, 087H
OBFH. 08BH. OBFH. OFFH
OBFH. OBBH. OC2H. OFFH
080H. OEFH. OD7H. OBBH
OBEH. 080H. OBFH. OFFH
OFBH. OE7H. OFBH. 087H
OF7H. OFBH. OFBH. 087H
OBBH. OBBH. OBBH. OC7H
OEBH. OEBH. OEBH. OF7H
OEBH. OEBH, OEBH. OB4H
083H. OF7H. OFBH. OFBH
OABH. OABH. OABH. ODBH
OCIH. OBBH. ODFH. OFFH
OBFH. OBFH. OBFH. OC3H
ODFH. OBFH. ODFH. OE3H
OBFH. OCFH. OBFH. OC3H
OC7H. OEFH. OC7H. OBBH
OB3H. OAFH. OAFH. OC3H
09BH. OABH. OB3H. OBBH
077H. 049H. 03EH. 03EH
OFFH. 088H. OFFH. OFFH
03EH, 009H. 077H. 07FH
07BH. Ob7H. 05FH. Ob7H
iget char index address offset
iget column dot patern b~t.
A.CDotRI
A.C!A
this bit fix nece5sar~ to not underline each character
this saves fixing each bit in the look up table
ORL
OutL
ichar bit fix
ioutput the dot pattern
b~te in ace
A.1I80H
PI. A
i . l i t with
RET
188b
1887
1888
1889
IB90
1891
A55EMBLY COMPLETE.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Program End
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
END
NO ERROR5
230795~51
9-131
AP·161
APPENDIX B
SOFTWARE PRINTER ENHANCEMENTS
This section describes several software enhancements
which could be implemented as additions to the software developed for this Application Note. Space is
available for most of the items described. Approximatec
Iy 5 bytes of Data Memory would be required to implement most of the features. Two bytes would be used for
status flags. and two bytes for temporary data or count
storage. It is possible to use less than five bytes. but this
would require the'duplicate use of some flags. or other
Data Memory stora~e. which will significantly COlpplicate the software· colling and debug taSks.·
Special Characters Qr Symbols
Dot matrix printing lends itself welI to the creation of
custom characters and symbols. There are two aspects
to. implementing special characters.· First. a character
look-up table. and second. additiorial software:for de~
coding and processing the special characters Or symbols. Special characters might be scientific· notation.
mathematical symbols; unique langltage characters. or
block and line graphics characters:
'
The character look-up table could be an additiorial page
of Program Memory dedicated to· the special characters.· or replace part. or all. of the existing look-up tables. If an additional look-up table is used; a third page
teSt would be needed /It the- begiJining of the Character
Translation subroutine. There is fundanlentally no differtmce. between the processing of special characters
and standard ASCn printable characters. If the characters require the same 5 x 7 dot matrix. the balance of
the software would remain the same. If. however. the
special characters require a different matrix. or the manipulation of the matrix. the software becomes more
complex.
.
.
In general. the major software modification required to
implement special charac~rs is the size of the dot matrix printed or the dot matrix configuration used. In the
case of scientific characters. it would often be necessary
to shiftthe 5x 7 matrix pattern within the available 9 x
9 matrix. Block or line graphics characters. on"the-other-hand. wouid require using the entire 9 x 9 print head
matrix arid printing during nornlalIy. blank dot columns.This would require suspending the blank column
blariking mechanism implementeq in this Application
Note. This would be the most complex aSpect of implementing special characters. It would possibly change
the number of required instructions. and thus the timing between i>Ts detection and print head sbienoid trig-
ger firing. This could cause the dot columns to be misa- .
Iigned within a printed line and between lines.
In the case of a matrix change. two approaches are
possible: dynamically changing the matrix. in line. as
standard ASCII characters are being printed. or isolating the special characters to a separate processing flow
where special characters are bandied as a unique and
complete line of characters only. A discussion of in line
matrix changes for special characters is beyond the
scOpe of ~is Appendix. It is sufficient to say that the
changes would require the conditions setting the EOLN
flag. character count. and dot column count software
be modified during character processing and printing.
Lower Case Descenders
The general principle of implementing lower case descend~ is to shift the 5 x 7 character dot matrix within
the available 9 x9 print head solenoid matrix. Implementing lower case descenders requires two software
modifications and the creation of status flag for the
purpose. First. the detection of characters needing de~
scenders and setting a dedicated status flag during the
character code to dot pattern translation subroutine.
Second, the character dot column data output to the
print head solenoids mu.st be shifted for each dot column of the character. At the end of the character. the
flag would be reset.
Inline Control Codes
Inline control codes are two to three character sequences. which indicate special hardware conditions or
software flow control and branching. The first character·indicates that the conirol code sequence is beginning
and is typicalIy an ASCII Escape Character (ESC)•.
IBH. Termination of the inline code sequence would be
indicated by a default number of code sequence characters. This would decrease the buffer size available for
characters.. FulI 80 character line buffering 'Yould require loading the Character Buffer with a received
character as a character is removed from it and processeq.
The Inline Control Code test would be 'performed in
two places: in the Character Buffer Fill subroutine and
in the Character Processing (translation) subroutine.
The test would be performed in the same mariner that a
Carriage Return (CR) character code test is implemented. Examples are horizontal tabs and expanded or con-
9-132
intJ
AP-161
densed character fonts. In the case of horizontal tabs,
20H (Space Character) would have to be placed in the
Character Buffer for inline processing during character
processing and printing. Unless fixed position tabs are
used, a minimum of a nibble of Data Memory would be
required to maintain a "spaces-to-tab" count. Fixed tab
positions could be set via another inline control code,
by default of the print software, or through the use of
external hardware switch settings. The control code
method of setting the tab positions. is the most desirable, but the most complex to implement.
Different Character Formats
Condensed and enlarged characters are variations in
either the number of dots and/or the space used to
print them. Thus, each character is a variation of the
stepper motor and/or print head solenoid trigger timings. It is possible to print each in bold face by printing
each dot twice per dot column position. This would
require little software modification, but would require a
status flag. Again, care must be used to ensure that the
delay in retriggering the solenoids is precisely the same
for each type of event. Without this precise timing the
dot column alignment will not be accurate. The software modifications needed to implement enlarged or
condensed characters is essentially the same. The carriage and print head solenoid firing software flow is the
same, butthe timing for each changes. For condensed
characters, the step Time Constant is doubled to approximately 4.08 ms, and the solenoids are fired four
times within each step time. The step rate actually becomes a multiple of the solenoid firing time, and a
counter incrementing once for each solenoid firing
would be needed. At the count of four, the carriage
stepper motor is stepped and the counter reset.
In the case of condensed characters, PTS does not play
the same roll as in standard or enlarged character printing. PTS is not used to indicate the optimum print head
solenoid firing time. Solenoid firing is purely a time
function for condensed characters. PTS would only be
used for Failsafe protection.
Enlarged characters would require the solenoids be
fired twice per dot column data, in two sequential dot
columns, at the same rate as standard characters. The
character dot column data and dot column count
would not be incremented at each output but at every
other output. A flag could be used for this purpose.
When printing either condensed or enlarged characters,
the maximum character count would have to compensate for the increased or decreased characters per line
count. When printing enlarged characters, the maximum characters per line would be 40.
The Character Buffer could hold two complete lines of
characters. But, condensed characters presents a quite
different situation. The avalable character per line increases to 132, well beyond the 80 character Character
Buffer size. The solution is to re-initialize the Character
Buffer Size Count register count during condensed
character processing. This will effectively inhibit the
carriage stepper motor drive EOLN detection.
Two status flags would be required; one for standard or
enlarged characters, and the second for condensed
characters. A third status flag would be required to
implement bold face printing. Activating one of the alternate character fonts could be either through the use
of external status switches or through inline control
code sequences, as detailed above. Note, that if the alternate character fonts are implemented in such a way
that format changing is to occur dynamically during
any single line being printed, the same control code
problems described above also apply. In addition, the
effect on the timing and dot column alignment must
also be investigated.
Variable Line Spacing
Variable line spacing is another feature which could be
implemented either through the use of external status
switches or inline control codes. The line spacing is a
function of the number of steps the stepper motor rotates for a given line. Figure IS, Paper Feed Stepper
Motor Predetermined Time Constants, in the Background section, lists the Time Constants required for
three different line spacings; 6, 8, and 10 lines per inch.
At the beginning of the Paper Feed Stepper Motor
Drive subroutine, the default line step count is loaded.
The software required is a conditional load for the line
spacing, indicated by a status flag set in the External
Status Switch Check subroutine or the Character Buffer Fill subroutine. Implementing the three different line
spacings would require two additional status flags.
9-133
intJ
AP-161
APPENDIX C
PRINTER MECHANISM
DRIVE CIRCUIT
R1
PRINT PULSE 1
500 • 20ps
PRINT PULSE 9
6-~~ol::~
________________a~1~----~~lI~~~s~a~LE.NaID1
I
SOLENOID 9
24V-10%
TRIGGER PULSE
200ps OR LESS
RESET PULSE
o---------------I-l
O'
GNOy
CR B
HI IU)
~
120SW~
ffi=i
LFA
i.e+-< I
.rtc+-, I
----
LFB
LFC
1
LFO
SLF
intJ
APPLICATION
NOTE
AP-90
November 1986
An 8741AH/8041ADigital
Cassette Controller
JOHN BEASTON, JIM KAHN
PERIPHERAL APPLICATIONS
Order Number: 231314-002
9-138
inter
AP-90
INTRODUCTION
in terms of development cost is to use a dedicated single-chip controller. However, a quick search through.
the literature turns up no controllers compatible with
these new transports. What to do? Enter the
UPI-4IAH family of Universal Peripheral Interfaces.
The microcomputer system designer requiring a lowcost, non-volatile storage medium has a difficult choice.
His options have been either relatively expensive, as
with floppy discs and bubble memories, or non-transportable, like battery backed-up RAMs. The full-size
digital cassette option was open but many times it was
too expensive for the application. Filling this void of
low-cost storage is the recently developed digital minicassette. These mini-cassettes are similar to, but not
compatible with, dictation cassettes. The mini-cassette
transports are inexpensive (well under $100 in quantity), small (less than 25 cu. in.), low-power (one watt),
and their storage capacity is a respectable 200K bytes
of unformatted data on a lOO-foot tape. These characteristics make the mini-cassette perfect for applications
ranging from remote datalogging to program storage
for hobbyist systems.
The UPI-4IAH family is a group of two user-programmable slave microcomputers plus a companion I/O expander. The 8741AH is the "flag-chip" of the line. It is
a complete microcomputer with 1024 bytes of EPROM
program memory, 64 bytes of RAM data memory, 16
individually programmable I/O lines, an 8-bit event
counter and timer, and a complete slave peripheral interface with two interrupts and Direct Memory Access
(DMA) control. The 804IA is the masked ROM, pin
compatible version of the 8741AH. Figure 2 shows a
block diagram common to both parts. The 8243 I/O
port expander completes the family. Each 8243 provides 16 programmable I/O lines.
The only problem associated with mini-cassette drives
is controlling them. While these drives are relatively
easy to interface to a microcomputer system, via a parallel I/O port, they can quickly overburden a CPU if
other concurrent or critical real-time I/O is required.
The cleanest and probably the least expensive solution
Using the UPI concept, the designer can develop a custom peripheral control processor for his particular I/O
problem. The designer simply develops his peripheral
control algorithm using the UPI-41AH assembly language and programs the EPROM of the 8741AH.
Voila!
231314-1.
Figure 1. Comparison of Mini-Cassette and Floppy Disk Transports and Media
9-139
Ap·90
8-BITCPU
I
I
8-BIT
DATA BUS
INPUT REGISTER
fl
1024.8
PROGRAM
MEMORY
64.8
DATA
MEMORY
II
II
II
II
8-BIT
DATA BUS
OUTPUT REGISTER
8-BIT
TIMER/COUNTER
8-BIT
STATUS
REGISTER
' II
18
I/O LINES
;..
1/
V'
SYSTEM BUS
PERIPHERAL BUS
231314-2
Figure 2_ 8741AH/8041A Block Diagram
He has a single-chip dedicated controller. Testing may
be accomplished using either an ICE-4IA or the SingleStep mode of the 874IAH. UPI-4IAH peripheral interfaces are being used to control printers, keyboards, displays, custom serial interfaces, and data encryption
units. Ofcourse , the UPI family is perfect for developing a dedicated controller for' digital mini-cassette
transports. To illustrate this application for the UPI
family let's consider the job of controlling the Braemar
CM:600 Mini-Dek*.
THE CM-600 MINI-DEK*
The Braemar CM-600 is representative of digital minicassette transports. It is a single-head, single-motor
transport which operates entirely from a single 5V power supply. Its power requirements, including the motor,
are 200 mA for read or write and 700 mA for rewind.
Tape speeds are 3 inches per second (IPS) during read
or write, S IPS fast forward, and IS IP~ rewind. With
these speeds and a maximum recording density of 800
bits per inch (BPI), the maximum data rate is 2400 bits
per second (BAUD). The data capacity usingboth sides
of a lOO-foot tape is 200K bytes. On top of this, the
transport occupies only 22.S
cubic inches
(3" x3" x2.S" ).
'All I/O for the CM-600 is TTL-compatible and can be
divided into three groups: motor control, data control,
and cassette status: The motor group controls are
GO/STOP,. FAST/SLOW, and FORWARDIREVERSE. The data 'controls are READ/WRITE,
DATA IN, and DATA OUT. The remaining group of
outputs give the transport's status: CLEAR LEADER,
CASSETTE PRESENCE, FILE PROTECT, and
SIDE SENSOR. These signals, shown schematically in
Figure 3 and Table 1, give the pin definition of the
CM-600 16~pin I/O connector.
RECORDING FORMAT
The CM-600 does not provide either encoding or decoding of the recorded data; that task is left for the,
peripheral interface. A multitude of encoding techniques from which the user may choose are available.
In this single-chip dedicated controller application, a
"self-clocking" phase encoding scheme similar to that
used in floppy discs was chosen. This scheme specifies
that a logic "0" is a bit cell with no transition; a cell
with a transition is a logic "1."
*MiniDek is a registered trademark of Braemar.
9-140
inter
AP-90
Table 1. CM-600 1/0 Pin Definition
Function
Pin 1/0
1
2
3
4
5
-
6
7
I
0
8
9
10
11
12
13
14
-
15
16
0
I
0
I
I
0
0
I
-
Index pin-not used
Signal ground
Cassette side (O-side B, 1-side A)
Data input (a-space, 1-mark)
Cassette presence (a-cassette, 1-no
cassette)
Read/Write (a-read, 1-write)
File protect (a-tab present, 1-tab
removed)
+ 5V motor power
Power ground
Chassis ground
Direction (a-forward, 1-rewind)
Speed (a-fast, 1-slow)
Data output (a-space, 1-mark)
Clear leader (O-clear leader, 1-off
clear leader)
Motion (a-go, 1-stop)
+ 5V logic power
231314-4
Figure 4. Modified Phase Encoding of
Character 3A Hex
checksum. The checksum is capable of catching 2 bit
errors. The number of data characters within a block is
limited to 64K bytes. Blocks are separated by an InterRecord Gap (IRG). The IRG is of such a length that
the transport can stop and start within an IRG, as illustrated in the data block timing, Figure 5. Braemar specifies a maximum start or stop time of ISO ms for the
transport, thus the controller uses 450 ms for the IRG.
This gives plenty of margin for controlling the transport and also for detecting IRGs while skipping blocks.
THE UPI-41AHTM CONTROLLER
INPUTS
BLOCK DIAGRAM
+5V MOTOR POWER---++5V LOGIC POWER---"
OUTPUTS
r----r---.
TAPE DIRECTION (I WD/REW) . .
BRAEMAA
CASSETTE SIDE
TAPE MOTION (STOP/GO)--.
CM-600'~
FILE PROTECT
TAPE SPEED {FAST/SLOW)---+DIGITAL
~ CASSETTE PRESENCE
SELECT AEAO/WRITE~
MINI CASSETTE
CLEAR LEADER
DATA INPUT
TRANSPORT ~ DATA OUTPUT
POWER GROUND
SIGNAL GROUND
CHASSIS GROUNO-------.
r--+-
•
231314-3
Figure 3. Braemar CM-600 Block Diagram
Figure 4 illustrates the encoding of th~ character 3~H
assuming the previous data ended wIth the data lme
high. (The least significant bit is sent first.) N oti~e t~Jat
there is always a "clocking" transition at the begmmng
of each cell. Decoding is simply a matter of triggering
on this "clocking" transition, waiting % of a bit cell
time, and determining whether a mid·cell transition has
occurred. Cells with no mid·cell transitions are data a's;
cells with transitions are data I's. This encoding technique has all the benefits of Manchester encoding with
the added advantage that the encoded data may be "decoded by eyeball:" long cells are always a's, short cells
are always I's.
Besides the encoding scheme, the data format is also up
to the user. This controller uses a variable byte length,
checksum protected block format. Every block starts
and ends with a SYNC character (AAH), and the character immediately preceding the last SYNC is the
9-141
The goal of the UPI software design for this application
was to make the UPI-4IAH microcomputer into an
intelligent cassette control processor. The host processor (8086, 8088, 808sA, etc.) simply issues a high-level
command such as READ-a-block or WRITE-a-block.
The 8741AH accepts the command, performs the requested operation, and returns to the host syst~m a result code telling the outcome of the operatIon, ego
Good-Completion, Sync Error, etc. Table 2 shows the
command and result code repertoire. The 8741AH
completely manages all the data transfers for reading
and writing.
As an example, consider the WRITE-a-block command. When this command is issued, the UPI-4IAH
expects a 16-bit number from the host telling how
many data bytes to write (up to 64K bytes per block).
Once this number is supplied in the form of two bytes,
the host is free to perform other tasks; a bit in the UPI's
STATUS register or an interrupt output will notify the
host when a data transfer is required. The 8741AH
then checks the transport's status to be sure that a cassette is present and not file protected. If either is false, a
result code is returned to the host; otherwise the transport is started. After the peripheral controller checks to
make sure that the tape is off the clear leader and past
the hole in the tape, it writes a 450 ms IRG, a SYNC
character, the block of data, the checksum, and the
final SYNC character. (The tape has a clear leader at
both ends and a small hole 6 inches from the end of
each leader.) The data transfers from the host to the
intJ
AP-90
t--"-----BlOCK WRITE OPERATION-----....~I
I
SYNC
I
DATA
~~
I
CHECKSUM
~450MS_1
I
SYNC
I
I
SYNC
I
DATA
1-450MS-1
'STOP TRANSPORT
'START TRANSPORT
231314-5
Figure 5. IRG/Block Timing Diagram (not to scale)
character is not a SYNC, that's an error and the controller returns a Bad-First-SYNC result code (42H) after advancing to the next IRG. If the SYNC is good,
the succeeding characters are read into an on-chip 30
character circular buffer. This continues until an IRG
is encountered. When this occurs, the transport is
stopped. The controller then tests that it is the last
character. If it is a SYNC, the controller then compares
the accumulated internal checksum to the block's
checksum, the second to the last character of the block.
If they match, a Good-Completion result code (DOH) is
returned to the host. If either test is bad, the appropriate error result code is returned. The READ command
also checks for the End-of-Tape (EOt) clear leader and
returns the appropriate error result code if it is found
before the read operation is complete.
Table 2. Controller Command/Result Code Set
Command
Read (01 H)
Result
Good-Completion (OOH)
. Buffer Overrun Errof(41 H)
Bad Synch1 Error (42H)
Bad Synch2 Error (43H)
Checksum Error (44H)
Command Error (45H)
End of Tape Error (46H)
Rewind (04H)
Good-Completion (OOH)
Skip (03H)
Good-Completion (OOH)
End of Tape Error (47H)
Beginning of Tape Error (48H)
Write (02H)
Good·Completion (OOH)
Buffer Underrun Error (81 H)
Command Error (82H)
End of Tape Error (83H)
UPI-4IAH slave microcomputer are double buffered.
The controller requests only the desired number of data
bytes by keeping track of the count internally.
If nothing unusual happened, such as finding clear
leader while writing, it returns a Good-Completion result code to the host. If clear leader was encountered,
the transport is stopped immediately and an End-ofTape result code is returned to the host. Another possible error would be if the host is late in supplying data.
If this occurs, the controller writes an IRG, stops the
drive, and returns the appropriate Data·Underrun result code.
The READ·a-block command also provides error
checking. Once this command is issued by the host, the
controller checks for cassette presence. If present, it
starts the transport. The data output from the transport
is then examined and decoded continuously. If the first
The 30 character circular buffer allows the host up to
30 character times of response time before the host
must collect the data. All data transfers take place thru
the UPI-4IAH Data Bus Buffer Output register
(DBBOUT). The controller continually monitors the
status of this register and moves characters from the
circular buffer to the register whenever it is empty.
The SKIP-n-blocks command allows the host to skip
the transport forward or backward up to .127 blocks.
Once the command is issued, the controller expects one
data byte specifying the number of blocks to skip. The
most significant bit of this byte selects the direction of
the skip (0 = forward, I = reverse). SKIP is a dualspeed operation in the forward direction. If the number
of blocks to skip is greater than 8, the controller uses
fast-forward (5 IPS until it is within 8 blocks of the
desired location. Once within 8 blocks, the controller
switches to the normal read speed (3 IPS) to allow accurate placement of the tape. The reverse skip uses only
the rewind speed (15 IPS). Like the READ and
WRITE commands, SKIP also checks for EOT and
beginning-of-tape (BOT) depending upon the tape's direction .. An error result code is returned if either is
9-142
Ap·90
encountered before the number of blocks skipped is
complete.
This application was developed on an Intel iSBC 80/30
single board computer. The iSBC 80/30 is controlled
by an 8085A microprocessor, contains 16K bytes of
dual-ported dynamic RAM and up to 8K bytes of either EPROM or ROM. Its I/O complement consists of
an 8255A Programmable Parallel Interface, an 8251A
Programmable Communications Interface, an 8253
Programmable Interval Timer, and an 8259A Programmable Interrupt Controller. The iSBC 80/30 is especially convenient for UPI development since it contains
an uncommitted socket dedicated to either an 8041A or
~741AH, complete with buffering for its I/O ports. The
ISBC 80/30 to 8741AH interface is reflected in Figure
8. (Optionally, an iSBC 569 Digital Controller board
could be used. The iSBC 569 board contains three uncommitted UPI sockets with an interface similar to that
in Figure 8.)
The REWIND command simply rewinds the tape to
the BOT clear leader. The ABORT command allows
the termination of any operation in progress, except a
REWIND. All commands, including ABORT, always
leave the tape positioned on an IRG.
THE HARDWARE INTERFACE
There's hardly any hardware design effort required for
the controller and transport interface in Figure 6. Since
the CM-600 is TTL compatible, it connects directly to
the I/O ports of the UPI controller. If the two are
separated (i.e'. on different PC cards), it is recommended that TTL buffers ,be provided. The only external circuitry needed is an LED driver for the DRIVE ACTIVE status indicator.
Looking at the host-to-controller interface, the host
sees the 8741AH as three registers in the host's I/O
address space: the data register, the command register,
and the status register. The decoding of these registers
is shown in Figure 7. All data and commands for the
controller are written into the Data Bus Buffer Input
register (D~BIN). The state of the register select input,
AO, determines whether a command or data is written.
(Writes with AO set to 1 are commands by
convention.) All data and results from the controller
are read by the host from the Data Bus Buffer Output
register (DBBOUT).
'
The 8741AH-to-host, interface is equally straightforward. It has a standard asynchronous peripheral interfac~: 8 data lines (Do-D7), read (RD), write (WR),
register select (AO), and chip select (CS). Thus it connects directly to an 8086, 8088, 8085A, 8080, or 8048
bus structure. Two interrupt outputs are provided for
data transfer requests if the particular system is interrupt-driven.DMA transfer capability is also available.
The clock input can be driven from a crystal directly or
with the system clock (6 MHz max). The UPI-41AH
clock may be asynchronous with respect to other clocks
within the system.
~~
c,o~ ".,' .
8041A
:T
XTAL2
VCC
VDD
CM-600
I-<
S'S
MOTOR POWER
LOGIC POWER
L
B
III
in)
:;)
Wft
III
P24
P2S
P20
:Iii
Iii>-
DO-D7
w
III
OBF
\Sf
TEST1
PIO
PII
PI2
PI3
PI4
PIS
PI6
AO
RESET
EA
VSS
DATA OUT
~
~
~
~
J
P21~
~
r
+5V
L
DIRECTION
MOTION
SPEED
READIWRITE
CLEAR LEADER
FILE PROTECT
PRESENCE
DATA IN
POWERGND
SIGNALGND
CHASSISGND
"2.DRIVE
ACTIVE
231314-6
Figure 6. Controller/Transport System Schematic
9-143
AP-90
CS
RD
WR
AO
Register
0
0
0
0
0
0
I
I
0
I
I
0
0
0
I
X
X
X
DBBOUT
STATUS
DBBIN (DATA)
DBBIN (COMMAND)
NONE
I
I
is set, any character found in DBBOUT is a result code.
Thus whenever the host finds OBF set, it should test
the BUSY flag to determine whether the character is
data or a result code.
Notice the OBF and IBF are available as interrupt outputs to the host processor, Figure 6. These outputs are
self-clearing, that is, OBF is set automatically upon the
controller loading DBBOUT and cleared automatically
by the host reading DBBOUT. Likewise IBF is cleared
to a 0 by the host writing into DBBIN: set to a 1 when
the controller reads DBBIN into the accumulator.
Figure 7. 8741AH/8041A Interface
Register Decoding
STATUS
OBF-OUTPUT BUFFER FULL
IBF-INPUT BUFFER FULL
' - - - - - FO-FLAG 0
L-_ _ _ _ F1-FLAG 1
L-_ _ _ _ _ DRIVE ACTIVE
' - - - - - - - - FILE PROTECT
' - - - - - - - - - CASSETTE PRESENCE
'-----------BUSy
,
231314-7
Figure 8. Status Register Bit Definition .
The Status register contains flags which give the host
the status of various operations within the controller.
Its format is given in Figure 8. The Input Buffer Full
(IBF) and Output Buffer Full (OBF) flags show the
Status of the DBBIN and DBBOUT registers respectively. IBF indicates when the DBBIN register contains
data written by the host. The host may write to DBBIN
only when IBF is O. Likewise, the host may read
DBBOUT only when OBF is set to a I. These bits are
handled automatically by the UPI-41AH internal hardware. FLAG 0 (Fa) and FLAG I (Fl) are general purpose flags used internally by the controller which have
no meaning externally.
The remaining four bits are user-definable. For this application they are DRIVE ACTIVE, FILE PROTECT,
CASSETTE PRESENCE, and BUSY flags. The FILE
PROTECT and CASSETTE PRESENCE flags reflect
the state of the corresponding I/O lines from the transport. DRIVE ACTIVE is set whenever the transport
motor is on and the controller is performing an operation. The BUSY flag indicates whether the contents of
the DBBOUT register is data or a result code. The
BUSY flag is set whenever a command is issued by the
host and accepted by the controller. As long as BUSY
The flow charts of Figure 9 show the flow of sample
host software assuming a polling software interface between the host and the controller. The WRITE command requires two additional count bytes which form
the 16-bit byte count. These extra bytes are "handshaked" into the controller using the IBF flag in the
STATUS register. Once these bytes are written, the
host writes data in response to IBF being cleared. This
continues until .the host finds OBF set indicating that
the operation is complete and reads the result code
from DBBOUT. No testing of BUSY is needed since
only the result code appears in the'DBBOUT register.
The READ command does require that BUSY be tested. ,Once the READ command is written into the controller, the host must test BUSY whenever OBF is set
to determine whether the contents of DBBOUT is data
from the tape. or the result code.
THE CONTROLLER SOFTWARE
The UPI-4IAH software to control the cassette can be
divided up into various commands such as WRITE
READ and ABORT. In a previous version of this ap:
plication note (May 1980), software was described that
implemented these commands. This code however did
not adequately compensate for speed variations of the
motor during record and playback nor for data distortion caused by the magnetic media. Since then, a new
code has been written to include these effects. This revised software is now available through the INTEL User's Library, INSITE. For more information on this
software or INSITE, contact your local INTEL Sales
Office.
9-144
inter
APPLICATION
NOTE
AP-281
July 1986
UPI-4S2 Accelerates iAPX 286
Bus Performance
CHRISTOPHER SCOTT
TECHNICAL MARKETING ENGINEER
INTEL CORPORATION
Order Number: 292018-001
9-145
inter
AP-281
. INTRODUCTION
The UPI-452 targets the leading problem in peripheral
to host interfacing, the interface of a slow peripheral
with a fast Host or "bus utilization". The solution is
data buffering to reduce the delay and overhead of
transferring data between the Host microprocessor and
I/O subsystem. The Intel CMOS UPI-452 solves this
problem by combining a sophisticated programmable
FIFO buffer and a slave interface with an MSC-51
based microcontroller.
The UPI-452 is Intel's newest Universal Peripheral Interface family member. The UPI-452 FIFO buffer enables Host-peripheral communications to be through
streams or bursts of data rather than by individual
bytes. In addition the FIFO provides a means of embedding commands within a stream or block of data.
This enables the system designer to manage data and
commands to further off-load the Host.
The UPI-452 interfaces to the iAPX 286 microproces-.
sor as a standard Intel slave peripheral device. READ,
WRITE, CS and address lines from the Host are used
to access all of the Host addressable UPI-452 Special
Function Registers (SFR).
The UPI-452 combines an MSC-5! microcontroller,
with 256 bytes of on-chip RAM and 8K bytes of
EPROM/ROM, twice that of the 80C51, a two channel
DMA controller and a sophisticated 128 byte, two
channel, bidirectional FIFO in a single device. The
UPI -452 retains all of the 80C5! architecture, and is
fully compatible with the MSC-51 instruction set.
This application note is a description of an iAPX 286 to
UPI-452 slave interface. Included is a discussion of the
respective timings and design considerations. This application note is meant as a supplement to the UPI-452
Advance Data Sheet. The user should consult the data
sheet for. additional details on the various UPI-452
functions and features.
UPI-4S2 iAPX 286 SYSTEM
CONFIGURATION
The interface described in this application note is
shown in Figure 1, iAPX 286 UPI-452 System Block
Diagram. The iAPX 286 system is configured in a local
bus architecture design. DMA between the Host and
the UPI-452 is supported by the 82258 Advanced
DMA Controller. The Host microprocessor accesses all
UPI-452 externally addressable registers through address decoding (see Table 3, UPI-4S2 External Address
Decoding). The timings and interface descriptions below are given in equation form with examples of specific calculations. The goal of this application note is a set
of interface analysis equations. These equations are the
tools a system designer can use to fully utilize the features of the UPI-452 to achieve maximum system performance.
HOST-UPI-4S2 FIFO SLAVE
INTERFACE
The UPI-452 FIFO acts as a buffer between the external Host 80286 and the internal CPU. The FIFO allows
the Host - peripheral interface to achieve maximum decoupling of the interface. Each of the two FIFO channels is fully user programmable. The FIFO buffer ensures that the respective CPU, Host or internal CPU,
receives data in the same order as transmitted. Three
slave bus interface handshake methods are supported
by the UPI-452; DMA, Interrupt and Polled.
The interface between the Host 80286 and the UPI-452
is accomplished with a minimum of signals. The 8 bit
data bus plus READ, WRITE, CS, and AO-2 provide
access to all of the externally addressable UPI-452 registers including the two FIFO channels. Interrupt and
DMA handshaking pins are tied directly to the interrupt controller and DMA controller respectively.
DMA transfers between the Host and UPI-452 are controlled by the Host processors DMA controller. In the
example shown in Figure 1, the Host DMA controller
is the 82258 Advanced DMA Controller. An internal
DMA transfer to or from the FIFO, as well as between
other internal elements,· is controlled by the UPI-452
internal DMA processor. The internal DMA processor
can also transfer data between Input and Output FIFO
channels directly. The description that follows details
the UPI-452 interface from both the Host processor's
and the UPI-452's internal CPU perspective.
One of the unique features of the UPI-452 FIFO is its
ability to distinguish between commands and data embedded in the same data block. Both interrupts and
status flags are provided to support this operation in
either direction of data transfer. These flags and interrupts are triggered by the FIFO logic independent of,
and transparent to either the Host or internal CPUs.
Commands embedded in the data 1:llock, or stream, are
called Data Stream Commands.
Programmable FIFO channel Thresholds are another
unique feature of the UPI-452. The Thresholds provide
for interrupting the Host only when the Threshold
number of bytes can be read or written to the FIFO
buffer. This further decouples the Host UPI-452 interface by relieving the Host of polling the buffer to determine the number of bytes that can be read or written. It
also reduces the chances of overrun and underrim errors which must be processed.
The UPI-452 also provides a means of bypassing the
FIFO, in both directions, for an immediate interrupt of
either the Host or internal CPU. These commands are
called Immediate Commands. A complete description
of the internal FIFO logic operation is given in the
FIFO Data Structure section.
9-146
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Ap·281
UPI-4S2 INITIALIZATION
The UPI-4S2 at power-on reset automatically performs
a minimum initialization of itself. The UPI-4S2 notifies
the Host that it is in the process of initialization by
setting a Host Status SFR bit. The user UPI-4S2 program must release the UPI -4S2 from initialization for
the FIFO to be accessible by the Host. This is the minimum Host to UPI-4S2 initialization sequence. All further initialization and configuration of the UPI-4S2, including the FIFO, is done by the internal CPU under
user program control. No interaction or programming
is required by the Host 80286 for UPI-4S2 initialization.
Host read/write access of the FIFO. The internal CPU
sets the Slave Control (SLCON) SFR FIFO DMA
Freeze/Normal Mode (FRZ) bit high (= 1) to activate
Normal Mode. Ths causes the Slave Status (SSTAT)
and Host Status (HSTAT) SFR FIFO DMA Freeze
Mode bits to be set to Normal Mode. Table 2, UPI-4S2
Initialization Event Sequence ExaIIlple, shows a summary of the initialization events described above.
Table 1. FIFO Special Function
Register Default Values
At power-on reset the UPI-4S2 automatically enters
FIFO DMA Freeze Mode by resetting the Slave Control (SLCON) SFR FIFO DMA FreezelNormal Mode
bit to FIFO DMA Freeze Mode (FRZ = "0"). This
forces the Slave Status (SSTAT) and Host Status
(HSTAT) SFR FIFO DMA Freeze/Normal Mode bits
to FIFO DMA FreezeMode In Progress. FIFO DMA
Freeze Mode allows the FIFO interface to be configured, by the internal CPU, while inhibiting Host access
to the FIFO.
SFRName
Label
Reset
Value
Channel Boundary Pointer
Output Channel Read Pointer
Output Channel Write Pointer
Input Channel Read Pointer
Input Channel Write Pointer
Input Threshold
Output Threshold
CBP
ORPR
OWPR
IRPR
IWPR
ITH
OTH
40H/64D
40H/64D
40H/64D
OOH/OD
OOH/OD
OOH/OD
01 H/1 D
Table 2. UPI-452 Initialization
Event Sequence Example
Event Description
The MODE SFR is forced to zero at reset. This disables, (tri-states) the DRQIN/INTRQIN, DRQOUT/
INTRQOUT and INTRQ output pins. INTRQ is inhibited from going active to reflect the fact that a Host
Status SFR bit, FIFO DMA Freeze Mode, is active. If
the MODE SFR INTRQ configure bit is enabled
( = 'I '), before the Slave Control and Host Status SFR
FIFO DMA FreezelNormal Mode bit is set to Normal
Mode, INTRQ will go active immediately.
The first action by the Host following reset is to read
the UPI-4S2 Host Status SFR Freeze/Normal Mode
bit to determine the status of the interface. This may be
done in response to a UPI-4S2 INTRQ interrupt, or by
polling the Host Status SFR. Reading the Host Status
SFR resets the INTRQ line low.
•
Any of the five FIFO interface SFRs, as well as a variety of additional features, may be programmed by the
internal CPU following reset. At power-on reset, the
five FIFO Special Function Registers are set to their
default values as listed in Table 1. All reserved location
bits are set to one, all other bits are set to zero in these
three SFRs. The FIFO SFRs listed in Table 1 can be
programmed only while the UPI-4S2 is in FIFO DMA
Freeze Mode. The balance of the UPI-4S2 SFRs default
values and descriptions are listed in the UPI-4S2 Advance Data Sheet in the Intel Microsystems Component Handbook Volume II and Microcontroller Handbook.
•
The above sequence is the minimum UPI-4S2 internal
initialization required. The last initialization instruction
must always set the UPI-4S2 to Normal Mode. This
causes the UPI-4S2 to exit Freeze Mode and enables
•
•
•
Power-on Reset
UPI-452 forces FIFO DMA
Freeze Mode (Host access to
FIFO inhibited)
UPI-452 forces Slave Status and
Host Status SFR to FIFO DMA
Freeze Mode In Progress
UPI-452 forces all SFRs,
including FIFO SFRs, to default
values.
UPI-452 user program enables
INTRa, INTRa goes active, high
Host READ's UPI-452 Host
Status (HSTAT) SFR to
determine interrupt source,
INTRa goes low
UPI-452 user program initializes
any other SFRs; FIFO, Interrupts,
Timers/Counters, etc.
User program sets Slave Control
SFR to Normal Mode (Host
access to FIFO enabled)
UPI-452 forces Slave and Host
Status SFRs bits to Normal
Operation
Host polls Host Status SFR to
determine when it can access the
FIFO
- orHost waits for UPI-452 Request
for Service interrupt to access
FIFO
• user optIOn
9-148
SFR/bit
SLCON FRZ = 0
SSTAT SST5 = 0
HSTAT HST1 = 1
MODE MD4 = 1
SLCON FRZ = 1
SSTAT SST5 = 1
HSTAT HST1 = 0
AP-281
Commands can be used to structure or dispatch the
data by defining the start and end of data blocks or
packets, or how the data following a DSC is to be processed;
FIFO DATA STRUCTURES
Overview
The UPI-452 provides three means of communication
between the Host microprocessor and the UPI-452 in
either direction;
Data
Data Stream Commands
Immediate Commands
Data and Data Stream Commands (DSC) are transferred between the Host and UPI-452 through the UPI452 FIFO buffer. The third, Immediate Commands,
provides a means of bypassing the FIFO entirely. These
three data types are in addition to direct access by either Host or Internal CPU of dedicated Status and
Control Special Function Registers (SFR).
The FIFO appears to .both the Host 80286 and the internal CPU as 8 bits wide. Internally the FIFO is logically nine bits wide. The ninth bit indicates whether the
byte is a data or a Data Stream Command (DSC) byte;
o = data, I = DSC. The ninth bit is set by the FIFO
logic in response to the address specified when writing
to the FIFO by either Host or internal CPU. The FIFO
uses the ninth bit to condition the UPI-452 interrupts
and status flags as a byte is made available for a Host or
internal CPU read from the FIFO. Figures 2 and 3
show the structure of each FIFO. channel and the logical ninth bit.
It is important to note that both data and DSCs are
actually entered into the FIFO buffer (see Figures 2
and 3). External addressing of the FIFO determines the
state ofthe internal FIFO logic ninth bit. Table 3 shows
the UPI-452 External Address Decoding used by the
Host and the corresponding action. The internal CPU
interface to the FIFO is essentially identical to the external Host interface. Dedicated internal Special Function Registers provide the interface between the FIFO,
internal CPU and the internal two channel DMA processor. FIFO read and write operations by the Host and
internal CPU are interleaved by the UPI-452 so they
appear to be occurring simultaneously.
The ninth bit provides a means of supporting two data
types within the FIFO buffer. This feature enables the
Host and UPI-452 to transfer both commands and data
while maintaining the decoupled interface a FIFO buffer provides. The logical ninth bit provides both a means
of embedding commands within a block of data and a
means for the internal CPU, or external Host, to discriminate between data and commands. Data or DSCs
may be ,written in any order desired. Data Stream
A Data Stream Command (DSC) acts as an internal
service routine vector. The DSC generates an interrupt
to a service routine which reads the DSC. The DSC
byte acts as an address vector to a user defined service
routine. The address can be any program or data memory location with no restriction on the number of DSCs
or address boundaries.
A Data Stream Command (DSC) can also be used to
clear data from the FIFO or "FLUSH" the FIFO. This
is done by appending a DSC to the end of a block of
data entered in the FIFO which is less than the programmed threshold number of bytes. The DSC will
cause an interrupt, if enabled, to the respective receiving CPU. This ensures that a less than Threshold number of bytes in the FIFO will be read. Two conditions
force a Request for Service interrupt, if enabled, to the
Host. The first is due to a Threshold number of bytes
having been written to the FIFO Output channel; the
second is if a DSC is written to the Output FIFO channel. If less than the Threshold number of bytes are written to the Output FIFO channel, the Host Status SFR
flag will not be set, and a Request for Service interrupt
will not be generated, if enabled. By appending a DSC
to end of the data block, the FIFO Request for Service
flag and!or interrupt will be generated.
An example of a FIFO Flush application is a mass storage subsystem. The UPI-452 provides the system interface to a subsystem which supports tape and disk storage. The FIFO size is dynamically changed to provide
the maximum buffer size for the direction of transfer.
Large data blocks are the norm in this application. The
FIFO Flush provides a means of purging the FIFO of
the last bytes of a transfer. This guarantees that the
block, no matter what its size, will be transmitted out of
the FIFO.
Immediate Commands allow more direct communication between the Host processor and the UPI-452 by
bypassing the FIFO in either direction. The Immediate
Command IN and OUT SFRs are two more unique
address locations externally and internally addressable.
Both DSCs and Immediate Commands have internal
interrupts and interrupt priorities associated with their
operation. The interrupts are enabled or disabled by
setting corresponding bits in the Slave Control
(SLCON), Interrupt Enable (IEC), Interrupt Priority
(IPC) and Interrupt Enable and Priority (IEP) SFRs. A
detailed description of each of these may be found in
the UPI-4S2 Advance Information Data Sheet.
9-149
AP-281
()
<5
o
...J
""o
9TH
B
I
T
INPUT
FIFO
CHANNEL
1=
z
o
()
........
...cg~------------------~
()
~I¢:=~>I
;;:
INTERNAL CPU
(DATA PROCESSOR)
292018-2
Figure 2. Input FIFO Channel Functional Diagram
9-150
inter
AP-281
u
<5
g
...J
o
9TH
B
I
OUTPUT
FIFO
CHANNEL
T
~
8
.......
§~~--------~----------t
c
~I¢::==~
;:;:
INTERNAL CPU
(DATA PROCESSOR)
292018-3
Figure 3. Output FIFO Channel Functional Diagram
9-151
inter
AP·281
Table 3. UPI·452 External Address Decoding
DACK
CS
A2
A1
AO
1
1
X
X
X
1
0
0
0
0
1
0
0
0
1
Data Stream Command
from Output FIFO
Channel
Data Stream Command
to Input FIFO
Channel
1
0
0
1
0
Host Status SFR
Read
Reserved
1
0
0
1
1
Host Control SFR
Read
Host Control SFR
Write
1
0
1
0
0
Immediate Command
SFR Read
Immediate Command
SFRWrite
1
0
0
X
1-
1
Reserved
X
X
X
Reserved
X
DMA Data from
Output FIFO Channel
DMA Data to Input
FIFO Channel
READ.
No Operation
Data or DMA from
. Output FIFO Channel
Below is a detailed description of each FIFO channel's
operation, including the· FIFO logic. response to the
ninth bit, as a byte moves through the channeL The
description covers each of the three data types for each
channeL The details below provide a picture ofthe various FIFO features and operation. By understanding the
FIFO structure and operation the user can optimize the
interface to meet the requirements of an individual design.
OUTPUT CHANNEL
This section covers the data path from the internal
CPU to the HOST. Data Stream Command or Immediate Command processing during Host DMA Operations is covered in the DMA section.
WRITE
No Operation
Data or DMA to
Input FIFO Channel
UPI·452 Internal Write to the FIFO
The internal CPU writes data and Data Stream Commands into the FIFO through the FIFO OUT (FOUT)
and Command OUT (COUT) SFRs. When a Threshold number of bytes has been written, the Host Status
SFR Output FIFO Request for Service bit is set and an
interrupt, if enabled, is generated to the Host. Either
the INTRQ or DRQOUT/INTRQOUT output pins
can be used for this interrupt as determined by the
MODE and Host Control (HCON) SFR setting. The
Host responds to the Request for Service interrupt by
reading the Host Status (HSTAT) SFR to determine
the source of the interrupt. The Host then reads the
Threshold number' of bytes from' the FIFO. The internal CPU may continue to write to the FIFO during the
Host read of the FIFO Output channeL
9-152
inter
AP-281
Data Stream Commands may be written to the Output
FIFO channel at any time during a write of data bytes.
The write instruction need only specify the Command
Out (COUT) SFR in the direct register instruction
used. Immediate Commands may also be written at any
time to the Immediate Command OUT (IMOUT) SFR.
The Host reads Immediate Commands from the Immediate Command OUT (IMOUT).
The internal CPU can determine the number of bytes to
write to the FIFO Output channel in one of three ways.
The first, and most efficient, is by utilizing the internal
DMA processor which will automatically manage the
writing of data to avoid Underrun or Overrun Errors.
The second is for the internal CPU to read the Output
FIFO channels Read and Write Pointers and compare
their values to determine the available space. The third
method for determining the available FIFO space is to
always write the programmed channel size number of
bytes to the Output FIFO. This method would use the
Overrun Error flag and interrupt to halt FIFO writing
whenever the available space was less than the channel
size. The interrupt service routine could read the channel pointers to determine or monitor the available channel space. The time required for the internal CPU to
write data to the Output FIFO channel is a function of
the individual instruction cycle time and the number of
bytes to be written.
Host Read from the FIFO
The Host reads data or Data Stream Commands (DSC)
from the FIFO in response to the Host Status
(HSTAT) SFR flags and interrupts, if enabled. AU
Host read operations access the same UPI-452 internal
I/O Buffer Latch. At the end of the previous Host
FIFO read cycle a byte is loaded from the FIFO into
the I/O Buffer Latch and Host Status (HST AT) SFR
bit 5 is set or cleared (J = DSC, 0 = data) to reflect
the state of the byte's FIFO ninth bit. If the FIFO ninth
bit is set (= 1) indicating a DSC, an interrupt isgenerated to the external Host via INTRQ pin or
INTRQIN/INTRQOUT pins as determined by Host
Control (HCON) SFR bit I. The Host then reads the
Host Status (HST AT) SFR to determine the source of
the interrupt.
The most efficient Host read operation of the FIFO
Output channel is through the use of Host DMA. The
UPI-452 fully supports external DMA handshaking.
The MODE and Host Control SFRs control the configuration of UPI-452 Host DMA handshake outputs. If
Host DMA is used the Threshold Request for Service
interrupt asserts the UPI-452 DMA Request
(DRQOUT) output. The Host DMA processor acknowledges with DACK which acts as a chip select of
the FIFO channels. The DMA transfer would stop
when either the threshold byte count had been read, as
programmed in the Host DMA processor, or when the
DRQOUT output is brought inactive by the UPI-452.
INPUT CHANNEL
This section covers the data path from the HOST to the
internal CPU or internal DMA processor. The details
of Data Stream Command or Immediate Command
processing during internal DMA operations are covered in the DMA section below.
Host Write to the FIFO
The Host writes data and Data Stream Commands into
the FIFO through the FIFO IN (FIN) and Command
IN (CIN) SFRs. When a Threshold number of bytes
has been read out of the Input FIFO channel by the
internal CPU, the Host Status SFR Input FIFO Request for Service bit is set and an interrupt, if enabled,
is generated to the Host. The Input FIFO Threshold
interrupt tells the Host that it may write the next block
of data into the FIFO. Either the INTRQ or DRQINI
INTRQIN output pins can be used for this interrupt as
determined by the MODE and Host Control (RCON)
SFR settings. ,The Host may continue to write to the
FIFO Input channel during the internal CPU read of
the FIFO. Data Stream Commands may be written to
the FIFO Input channel at any time during a write of
data bytes. Immediate Commands may also be written
at any time to the Immediate Command IN (IMIN)
SFR.
9-153
inter
AP-281
The Host also has three methods for determining the
available FIFO space. Two are essentially identical to
that of the internal CPU. They involve reading the
FIFO Input channel pointers and using the Host Status
SFR Underrun and Overrun Error flags and Request
for Service interrupts these would generate, if enabled
in combination. The third involves using the UPI-452
Host DMA controller handshake signals and the programmed Input FIFO Threshold. The Host would receive a Request for Service interrupt when an Input
FIFO channel has a Theshold number of bytes able to
be written by the Host. The Host service routine would
then write the Threshold number of bytes to the FIFO.
If a Host DMA is used to write to the FIFO Input
channel, the Threshold Request for Service interrupt
could assert the UPI-452 DRQIN output. The Host
DMA processor would assert DACK and the FIFO
write would be completed by Host the DMA processor.
The DMA transfer would stop when either the Threshold byte count had been written or the DRQIN output
was removed by the UPI-452. Additional details on
Host and internal DMA operation is given below.
Internal Read of the FIFO
At the end of an internal CPU read cycle a byte is
loaded from the FIFO buffer into the FIFO IN/Command IN SFR and Slave Status (Sst AT) SFR bit 1 is
set or cleared (I = data, 0 = DSC) to reflect the state
of the FIFO ninth bit. If the byte is a DSC, the FIFO
ninth bit is set (= 1) and an interrupt is generated, if
enabled, to the Internal CPU. The internal CPU then
reads the Slave Status (SSTAT) SFR to determine the
source of the interrupt.
Immediate Commands are written by the Host and
read by the internal CPU through the Immediate Command IN (IMIN) SFR. Once written, an Immediate
Command sets the Slave Status (SSTAT) SFR flag bit
and generates an interrupt, if enabled, to the internal
CPU. In response to the interrupt the internal CPU
reads the Slave Status (SSTAT) SFR to determine the
source of the interrupt and service the Immediate Command.
FIFO INPUTIOUTPUT CHANNEL SIZE
Host
The Host does not have direct control of the FIFO
Input or Output channel sizes or configuration. The
Host can, however, issue Data Stream Commands or
Immediate Commands to the UPI-452 instructing the
UPI-452 to reconfigure the FIFO interface by invoking
FIFO DMA Freeze Mode. The Data Stream Command or Immediate Command would be a vector to a
service routine which performs the specific reconfiguration.
UPI-4S2 Internal
The default power-on reset FIFO channel sizes are listed in the "Initialization" section and can be set only by
the internal CPU during FIFO DMA. Freeze Mode.
The FIFO channel size is selected to achieve the optimum application performance. The entire 128 byte
FIFO can be allocated to either the Input or Output
channel. In this case the other channel consists of a
single SFR; FIFO IN/Command IN or FIFO OUT/
Command OUT SFR. Figure 4 shows a FIFO division
with a portion devoted to each channel. Figure 5 shows
a FIFO configuration with all 128 bytes assigned to the
Output channel.
The FIFO channel Threshold feature allows the user to
match the FIFO channel size and the performance of
the internal and Host data transfer rates. The programmed Threshold provides an elasticity to the data
transfer operation. An example is if the Host FIFO
HOS! CPU
CHANNEL
BOUNDRY
POINTER
(CBP)
-+
FIFO
INPUT
CHANNEL
1-+1
FIFO IN SFR
FIFO
OUTPUT
CHANNEL
1+-1
FIFO OUT SFR
J-.
l+-
INTERNAL
CPU
~
HOST CPU
292018-4
Figure 4. Fu" Duplex FIFO Operation
9-154
Ap·281
HOST CPU
CHANNEL
BOUNDRY
POINTER
(CBP)
-+1
FIFO IN SFR
1-+
INTERNAL
CPU
-+
FIFO
INPUT
CHANNEL
H
FIFO OUT SFR
I+-
1
HOST CPU
292018-5
Figure 5. Entire FIFO Assigned to Output Channel
data transfer rate is twice as fast as the internal FIFO
DMA data transfer rate. In this example the FIFO Input channel size is programmed to be 64 bytes and the
Input channel Threshold is programmed to be 20 bytes.
The Host writes the first 64 bytes to the Input FIFO.
When the internal DMA processor has read 20 bytes
the Threshold interrupt, or DMA request (DRQIN), is
generated to signal the Host to begin writing more data
to the Input FIFO channel. The internal DMA processor continues to read data from the Input channel as
the Host, or Host DMA processor, writes to the FIFO.
The Host can write 40 bytes to the FIFO Input channels in the time it takes for the internal DMA processor
to read 20 more bytes from it. This will keep both the
Host and internal DMA operating at their maximum
rates without forcing one to wait for the other.
Two methods of managing the FIFO size are possible;
fixed and variable channel size. A fixed channel size is
one where the channel is configured at initialization
and remains unchanged throughout program execution.
In a variable FIFO channel size, the configuration is
changed dynamically to meet the data transmission requirements as needed. An example of a variable channel size application is the mass storage subsystem described earlier. To meet the demands of a large data
block transfer the FIFO size could be fully allocated to
the Input or Output channel as needed. The Thresholds
are also reprogrammed to match the respective data
transfer rates.
An example of a fixed channel size application might be
one which uses the UPI-4S2 to directly control a series
of stepper motors. The UPI-4S2 manages the motor
operation and status as required. This would include
pulse train, acceleration, deceleration and feedback.
The Host transmits motor commands to the UPI-4S2 in
blocks of 6- 10 bytes. Each block of motor command
data is preceded by a command to the UPI-4S2 which
selects a specific motor. The UPI-4S2 transmits blocks
of data to the Host which provides motor and overall
system status. The data and embedded commands
structure, indicating the specific motor, is the same. In
this example the default 64 bytes per channel might be
adequate for both channels.
INTERRUPT RESPONSE TIMING
Interrupts enable the Host UPI-4S2 FIFO buffer interface and the internal CPU FIFO buffer interface to
operate with a minimum of overhead on the respective
CPU. Each CPU is "interrupted" to service the FIFO
on an as needed basis only. In configuring the FIFO
buffer Thresholds and choosing the appropriate internal DMA Mode the user must take into account the
interrupt response time for both CPUs. These response
times will affect the DMA transfer rates for each channel. By choosing FIFO channel Thresholds which reflect both the respective DMA transfer rate and the
interrupt response time the user will achieve the maximum data throughput and system bus decoupling. This
in turn will mean the overall available system bus bandwidth will increase.
The following section describes the FIFO interrupt interface to the Host and internal CPU. It also describes
an analysis of sample interrupt response times for the
Host and UPI-4S2 internal CPU. These equations and
the example times shown are then used in the DMA
section to further analyze an optimum Host UPI-4S2
interface.
HOST
Interrupts to the Host processor are supported by the
three UPI-4S2 output pins; INTRQ, DRQIN/
INTRQIN and DRQOUT/INTRQOUT. INTRQ is a
general purpose Request For Service interrupt output.
DRQIN/INTRQIN and DRQOUT/INRQOUT pins
are multiplexed to provide two special "Request for
Service" FIFO interrupt request lines when DMA is
disabled. A FIFO Input or Output channel Request for
Service interrupt is generated based upon the value programmed in the respective channel's Threshold SFRs;
Input Threshold (ITHR), and Output Threshold
9-155
AP-281
(OTHR) SFRs. Addi~ional interrupts are provided for
FIFO Underrun and Overrun Errors, Data Stream
Commands,aild Immediate Commands. TableA lists
the eight UPI-452 interrupt sources as they appear in
the HSTAT SFR to the Host processor.
Table 4, UPI 452 to Host Interrupt Sources
HSTAT
Interrupt Source
SFR Bit
HST7
Output FIFO Underrun Error
HST6
Immediate Command Out SFR Status
HST5
bata Stream Command/Data at Output
FIFO Status
HST4
Output FIFO, Request for Service Status
HST3
Input FIFO Overrun Error Condition
HST2
Immediate Comamnd In SFR Status
HST1
FIFO DMA Freeze/Normal Mode
Status
HSTO
Input FIFO Request for Service
. .
The interrupt response time required by the Host processor is application' and system specific. In general, a
typical sequence of Host interrupt response eve~ts a~d
the approximate times associated with each are listed m
Equation I.
The example assumes -the hardware configuration
shown in Figure 1, iAPX 2861UP1-452 Block Diagram,
with an 8259A Programmable Interrupt Controller.
The timing analysis in Equation 1 also assumes the following; no other interrupt is either in proc,ess or pend"
ing, nor is the 286 iIi a LOCK condition. The current
instruction completion time is 8dock cycles (800 ns @
10 MHz), or 4 bus cycles. The interrupt service routine
first executes a PUSHA instruction, PUSH All General
Registers, to save all iAPX 286 internal registers. This
requires 19 clocks (or 2.0 ,""S @ 10 MHz), or 10 bus
cycles (rounded to complete bus cycle). The next service routine instruction reads the UPI-452 Host Status
SFR to determine the interrupt source.
It is important to note that any UPI-452 INTRQ interrupt service routine shohld ALWAYS mask for the
Freeze Mode bit first. This will insure that Freeze
Mode always has the highest priority. This will also
save the time required to mask for bits which are forced
inactive during Freeze Mode, before checking the
Freeze Mode bit. Access to the FIFO channels by the
Host is inhibited during Freeze Mode. Freeze Mode is
covered in more detail below.
To initiate the interrupt the UPI-452 activates the
INTRQ output. The interrupt acknowledge sequence
requires two bus cycles, 400 ns (10 MHz iAPX 286),
for the two INTA pulse sequence.
Equation 1. Host Interrupt Response Time
Action
Time
Current instruction execution
800 ns
completion
INTA sequence
400 ns
Interrupt service routine (time
to host first READ of UPI-452) 2000 ns
2.3,""s
Total Interrupt Response Time
Bus
Cycles·
4
2
10
16
NOTE:
10 MHz iAPX 286 bus cycle, 200 ns each
UPI-452 Internal
The internal CPU FIFO interrupt interface is essentially identical to that of the Host to the FIFO. T~iee
internal interrupt sources support the FIFO operation;
FIFO-Slave bus Interface Buffer, DMA Channel 0 and
DMA Channel 1 Requests. These interrupts provide a
maximum decoupling of the FIFO buffer and the internal CPU. The four different internal DMA Modes
available add flexibility to the interface.
The FIFO-Slave Bus Interface interrupt response is
also similar to the Host response to I!-Il INTRQ Request
for Service interrupt. The internal CPU responds to the
interrupt by reading the Slave Status (SSTAT) SFR to
determine the source of the interrupt. This allows the
user to prioritize the Slave Status flag response to meet
the users application needs.
The internal interrupt response time is dependent on
the current Instruction execution, whether the interrupt
is enabled; and the interrupt priority. In general, to finish execution of the current instruction, respon,d to the
interrupt request, push the Program Counter (PC) and
vector to the first instruction of the interrUpt service
routine requires from 38 to 86 oscillator periods (2.38
to 5.38 ,""S @ 16 MHz). If the interrupt is due to an
Immediate Command or DSC, additional time is required to read the Immediate Command or DSC SFR
and vector to the appropriate service routine. This
means two service routines back to back. One service
routine to read the Slave Status (SSTAT) SFR to determine the source of the Request for Service interrupt,
and second the service routine pointed to by the Immediate Command or DSC byte read from the respective
SFR.
9-156
AP·281
Table 5. Host UPI·452
Data Transfer Performance
DMA
DMA is the fastest and most efficient way for the Host
or internal CPU to communicate with the FIFO buffer.
The UPI-452 provides support for both of these DMA
paths. The two DMA paths and operations are fully
independent of each other and can function simultaneously. While the Host DMA processor is performing
a DMA transfer to or from the FIFO, the UPI-452
internal DMA processor can be doing the same.
Below are descriptions of both the Host and internal
DMA operations. Both DMA paths can operate asynchronously and at different transfer rates. In order to
make the most of this simultaneous asynchronous operation it is necessary to calculate the two transfer rates
and accurately match their operations. Matching the
different transfer rates is done by a combination of accurately programmed FIFO channel size and channel
Thresholds. This provides the maximum Host and internal CPU to FIFO buffer interface decoupling. Below
is a description of each of the two DMA operations and
sample calculations for determining transfer rates. The
next section of this application note, "Interface Latency", details the considerations involved in analyzing effective transfer rates when the overhead associated with
each transfer is considered.
HOST FIFO DMA
DMA transfers between the Host and UPI-452 FIFO
buffer are controlled by the Host CPU's DMA controller, and is independent of the UPI-452's internal two
channel DMA processor. The UPI-452's internal DMA
processor supports data transfers between the UPI-452
internal RAM, external RAM (via the Local Expansion
Bus) and the various Special Function Registers including the FIFO Input and Output chaimel SFRs.
Processor &
Speed
iAPX-186*
8MHz
10 MHz
12.5 MHz
iAPX-286*' 6 MHz
8MHz
10 MHz
Wait States:
DMA:
Back to Back
Two
Single
READI
Cycle
Cycle
WRITE's
0
0
1
0
1
2
N/A*
N/A*
N/A*
0
1
2
0
0
0
0
0
0
NOTES:
• iAPX 186 On-chip DMA processor is two cycle operation
only.
•• iAPX 286 assumes 82258 ADMA (or other DMA) running 286 bus cycles at 286 clock rate.
In this application note system example, shown in Figure I, DMA operation is assumed to be two bus cycle
I/O to memory or memory to I/O. Two cycle DMA
consists of a fetch bus cycle from the source and a store
bus cycle to the destination. The data is stored in the
DMA controller's registers before being sent to the destination. Single cycle DMA transfers involve a simultaneous fetch from the source and store to the destination. As the most common method of I/O-memory
DMA operation, two cycle DMA transfers are the focus of this application note analysis. Equation 2 illustrates a calculation of the overall transfer rate between
the FIFO buffer and external Host for a maximum
FIFO size transfer. The equation does not account for
the latency of initiating the DMA transfer.
Equation 2. Host FIFO DMA Transfer
Rate-Input or Output Channel
2
Cycle DMA Transfer-I/O (UPI-452) to System
Memory
FIFO channel size* (DMA READ/WRITE
FIFO time + DMA WRITE/READ Memory
Time)
128 bytes' (200 ns + 200 ns)
51.2 J.Ls
256 bus cycles'
The maximum DMA transfer rate is achieved by the
minimum DMA transfer cycle time to accomplish a
source to destination move. The minimum Host UPI452 FIFO DMA cycle time possible is determined by
the READ and WRITE pulse widths, UPI-452 command recovery times in relation to the DMA transfer
timing and DMA controller transfer mode used. Table
5 shows the relationship between tlie iAPX-286, iAPX186 and UPI-452 for various DMA as well as nonDMA byte by byte transfer modes versus processor frequencies.
NOTES:
'10 MHz iAPX 286, 200 ns bus cycles.
Host processor speed vs wait states required with UPI452 running at 16 MHz:
The UPI-452 design is optimized for high speed DMA
transfers between the Host and the FIFO buffer. The
9-157
intJ
AP-281
UPI-452 internal FIFO buffer control logic provides
the necessary synchronization of the external Host
event and the internal CPU machine cycle during
UPI-452 RD/WR accesses. This internal synchronization is addressed by the TCC AC specification of the
UPI-452 shown in Figure 6. TCC is the time from the
leading or trailing edge of a UPI-452 RD/WR to the
same edge of the next UPI-452 RD/WR. The TCC
time is effectively another way of measuring the system
bus cycle time with reference to UPI-452 accesses.
In the iAPX-286 10 MHz system depicted in this application note the bus cycle time is 200 ns. Alternate cycle
accesses of the UPI-452 during two cycle DMA operation yields a TCC time of 400 ns which is more than the
TCC minimum time of 375 ns. Back to back Host
UPI-452 READ/WRITE accesses may require wait
states as shown in Table 5. The difference between 10
MHz iAPX-186 and 10 MHz iAPX 286 required wait
states is due to the number of clock cycles in the respective bus cycle timings. The four clocks in.a 10 MHz
iAPX 186 bus cycle means a minimum TCC time of
400 ns versus 200 ns for a 10 MHz iAPX 286 with two
clock cycle zero wait state bus cycle.
DMA handshaking between the Host DMA controller
and the UPI-452 is supported by three pins on the UPI452; DRQIN/INTRQIN, DRQOUT/INTRQOUT
and DACK. The DRQIN/INTRQIN and DRQOUT/
INTRQOUT outputs are two multiplexed DMA or interrupt request pins. The function of these pins is controlled by MODE SFR bit 6 (MD6). DRQIN and
DRQOUT provide a direct interface to the Host system
DMA controller (see Figure 1). In response to a
DRQIN or DRQOUT request, the Host DMA controller initiates control of the system bus using HLD/
HLDA. The FIFO Input or Output channel transfer is
accomplished with a minimum of Host overhead and
system bus bandwidth.
CS#
The third handshake signal pin is DACK which is used
as a chip select during DMA data transfers. The UPI452 Host READ and WRITE input signals select the
respective Input and Output FIFO channel during
DMA transfers. The CS and address lines provide
DMA acknowledge for processors with onboard DMA
controllers which do not generate a DACK signal.
The iAPX 286 Block I/O Instructions provide an alternative to two cycle DMA data transfers with approximately the same data rate. The String Input and Output instructions (INS & OUTS) when combined with
the Repeat (REP) prefix, modifies INS and OUTS to
provide a means of transferring blocks of data between
I/O and Memory. The data transfer rate using REP
INS/OUTS instructions is calculated in the same way
as two cycle DMA transfer times. Each READ or
WRITE would be 200 ns in a 10 MHz iAPX 286 systern .. The maximum transfer rate possible is 2.5
MBytes/second. The Block I/O FIFO data transfer
calculation is the same as that shown in Equation 2 for
two cycle DMA data transfers including TCC timing
effects.
FIFO Data Structure and Host DMA
During a Host DMA write to the FIFO, if a DSC is to
be written, the DMA transfer is stopped, the DSC is
written and the DMA restarted. During a Host DMA
read from the FIFO, if a DSC is loaded into the I/O
Buffer Latch the DMA request, DRQOUT, will be deactivated (see Figure 2 above). The Host Status
(HSTAT) SFR Data Stream Command bit is set and
the INTRQ interrupt output goes active, if enabled.
The Host responds to the interrupt as described above.
'''''---,..,/
'''''---,..,/
f-I'----TCC----'----l'1
RD#/WR#
/
----j-\~
TRR/TWW
/
~
f.ot____T_R_V_~ TRR/TWW, ~
292018-6
Symbol
Description
Var.Osc.
@16MHz
TCC
Command Cycle
Time
Command Recovery
Time
6 • Tclcl
375 ns min
75
75 ns min
TRV
Figure 6. UPI-452 Command Cycle Timing
9-158
inter
AP-281
Once INTRQ is deactivated and the DSC has been read
by the Host, the DMA request, DRQOUT, is reasserted by the UPI-452. The DMA request then remains
active until the transfer is complete or another DSC is
loaded into the I/O Buffer Latch.
An Immediate Command written by the internal CPU
during a Host DMA FIFO transfer also causes the
Host Status flag and INTRQ to go active if enabled. In
this case the Immediate Command would not terminate
the DMA transfer unless terminated by the Host. The
INTRQ line remains active until the Host reads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.
The net effect of a Data Stream Command (DSC) on
DMA data transfer rates is to add an additional factor
to the data transfer rate equation. This added factor is
shown in Equation 3. An Immediate Command has the
same effect on the data transfer rate if the Immediate
Command interrupt is recognized by the Host during a
DMA transfer. If the DMA transfer is completed before the Immediate Command interrupt is recognized,
the effect on the DMA transfer rate depends on whether the block being transmitted is larger than the FIFO
channel size. If the block is larger than the programmed FIFO channel size the transfer rate depends
on whether the Immediate Command flag or interrupt
is recognized between partial block transfers.
The FIFO configuration shown in Equation 3 is arbitrary since there is no way of predicting the size relative
to when a DSC would be loaded into the I/O Buffer
Latch. The Host DMA rate shown is for a UPI-452
(Memory Mapped or I/O) to 286 System Memory
transfer as described earlier. The equations do not account for the latency of intiating the DMA transfer.
Equation 3. Minimum host FIFO DMA Transfer
Rate Including Data Stream Command(s)
Minimum Host/FIFO DMA Transfer Rate wi DSC
FIFO size' Host DMA 2 cycle time transfer rate
+ iAPX 286 interrupt response time (Eq. # 1)
(32 bytes' (200 ns + 200 ns)) + 2.3 JLs
15.1 JLs
75.5 bus cycles (@10 MHz iAPX286, 200 ns
bus cycle)
UPI-4S2 INTERNAL DMA PROCESSOR
The two identical internal DMA channels allow high
speed data transfers from one UPI·452 writable memory space to another. The following UPI-452 memory
spaces can be used with internal DMA channels:
Internal Data Memory (RAM)
External Data Memory (RAM)
Special Function Registers (SFR)
The FIFO can be accessed during internal DMA operations by specifying the FIFO IN (FIN) SFR as the
DMA Source Address (SAR) or the FIFO OUT
(FOUT) SFR as the Destination Address (DAR). Table 6 lists the four types of internal DMA transfers and
their respective timings.
Table 6. UPI-4S2 Internal DMA Controller Cycle Timings
Source
Destination
Internal Data
Mem.orSFR
Internal Data
Mem.orSFB
External Data
Mem.
'External Data
Memory
Internal Data
Mem.orSFR
External Data
Mem.
Internal Data
Mem.orSFR
External Data
Memory
Machine
Cycles"
@12MHz
@16MHz
1
1 JLs
750 ns
1
1 JLs
750 ns
1
1 JLs
750 ns
2
2 JLs
1.5 JLs
NOTES:
'External Data Memory DMA transfer applies to UPI·452 Local Bus only.
'*MSC·51 Machine cycle = 12 clock cycles (TCLCL).
9-159
intef
AP-281
FIFO Data Structure and Internal DMA
INTERFACE LATENCY
The effect of Data Stream Commands and Immediate
Commands on the internal DMA transfers is essentially
the same as the effect on Host FIFO DMA transfers.
Recognition also depends upon the programmed DMA
Mode, the interrupts enabled, and their priorities. The
net internal effect is the same for each possible internal
case. The time required to respond to the Immediate or
Data Stream Command is a function of the instruction
time required. This must be calculated by the user
based on the instruction cycle time given in the MSC·
51 Instruction Set description in the Intel Microcon·
troller Handbook.
The interface latency is the time required to accommo·
date all of the overhead associated with an individual
data transfer. Data transfer rates between the Host sys·
tem and UPI-452 FIFO, with a block size less than or
equal to the programmed FIFO channel size, are calcu·
lated using the Host system DMA rate. (see Host
DMA description above). In this case, the entire block
could be transferred in one operation. The total latency
is the time required to accomplish the block DMA
transfer, the interrupt response or poll of the Host
Status SFR response time, and the time required to ini·
tate the Host DMA processor.
It is important to note that the internal DMA processor
modes and the internal FIFO logic work together to
automatically manage internal DMA transfers as data
moves into and out of the FIFO. The two most appro·
priate internal DMA processor modes for the FIFO are
FIFO Demand Mode and FIFO Alternate Cycle Mode.
In FIFO Demand Mode, once the correct Slave Con·
trol and DMA Mode bits are set, the internal Input
FIFO channel DMA transfer occurs whenever the
Slave Control Input FIFO Request for Service flag is
set. The DMA transfer continues until the flag is
cleared or when the Input FIFO Read Pointer SFR
(IRPR) equals zero. If data continues to be entered by
the Host, the internal DMA continues until an internal
interrupt of higher priority, if enabled, interrupts the
DMA transfer, the internal DMA byte count reaches
zero or until the Input FIFO Read Pointer equals zero.
A complete description of interrupts and DMA Modes
can be found in the UPI·452 Data Sheet.
A DMA transfer between the Host and UPI·452 FIFO
with a block size greater than the programmed FIFO
channel size introduces additional overhead. This addi·
tional overhead is from three sources; first, is the time
to actually perform the DMA transfer. Second, the
overhead of initializing the DMA processor, third, the
handshaking between each FIFO block required to
transfer the entire data block. This could be time to
wait for the FIFO to be emptied and/or the interrupt
response time to restart the DMA transfer of the next
portion of the block. A fourth component may also be
the time required to respond to Underrun and Overrun
FIFO Errors.
Table 7 shows six typical FIFO Input/Output channel
sizes and the Host DMA transfers times for each. The
timings shown reflect a 10 MHz system bus two cycle
I/O to Memory DMA transfer rate of 2.5 MBytes/sec·
ond as shown in Equation 1. The times given would be
the same for iAPX 286 I/O block move instructions
REP INS and REP OUTS as described earlier.
DMA Modes
Table 7. Host DMA FIFO Data Transfer Times
The internal DMA processor has four modes of opera·
tion. Each DMA channel is software programmable to
operate in either Block Mode or Demand Mode. De·
mand Mode may be further programmed to operate in
Burst or Alternate Cycle Mode. Burst Mode causes the
internal processor to halt its execution and dedicate its
resources exclusively to the DMA transfer. Alternate
Cycle Mode causes DMA cycles and instruction cycles
to occur alternately. A detailed description of each
DMA Mode can be found in the UPI-452 Data Sheet.
FIFO Size:
32
Full or Empty
% % % % % Full or Empty
Time
43
64
85
96
128 1 bytes
12.8 17.2 25.6 34.0 38.4 51.21
p,s
Table 8 shows six typical FIFO Input/Output channel
sizes and the. internal DMA processor data transfers
times for each. The timings shown are for a UPI·452
single cycle Burst Mode transfer at 16 MHz or 750 ns
per machine cycle in or out of the FIFO channels. The
9·160
inter
AP-281
machine cycle time is that of the MSC-51 CPU; 6
states, 2 XTAL2 clock cycles each or 12 clock cycles
per machine cycle. Details on the MSC-51 machine cycle timings and operation may be found in the Intel
Microcontroller Handbook.
Table 8. UPI-452 Internal DMA FIFO
Data Transfer Times
FIFO Size:
32
43
Full or Empty
%
% % % %
Time
64
85
I
96
128 bytes
Full or Empty
24.0 32.3 48.0 64.6 72.0 96.01 ,..,s
A larger than programmed FIFO channel size data
block internal DMA transfer requires internal arbitration. The UPI-452 provides a variety of features which
support arbitration between the two internal DMA
channels and the FIFO. An example is the internal
DMA processor FIFO Demand Mode described above.
FIFO Demand Mode DMA transfers occur continuously until the Slave Status Request for Service Flag is
deactivated. Demand Mode is especially useful for continuous data transfers requiring immediate attention.
FIFO Alternate Cycle Mode provides for interleaving
DMA transfers and instruction cycles to achieve a
maximum of software flexibility. Both internal DMA
channels can be used simultaneously to provide continuous transfer for both Input and Output FIFO channels.
Byte by byte transfers between the FIFO and internal
CPU timing is a function of the specific instruction cycle time. Of the III MCS-51 instructions, 64 require 12
clock cycles, 45 require 24 clock cycles and 2 require 48
clock cycles. Most instructions involving SFRs are 24
clock cycles except accumulator (for example, MOV
direct, A) or logical operations (ANL direct, A). Typical instruction and their timings are shown in Table 9.
Oscillator Period:
@
@
12 MHz
16 MHz
=
=
83.3 ns
62.S ns
MOV directt, A
MOV direct, direct
Oscillator
@12MHz @16MHz
Periods
12
24
1 ,..,s
2,..,s
A typical effective internal FIFO channel transfer rate
using internal DMA is shown in Equation 4. Equation
5 shows the latency using byte by byte transfers with an
arbitrary factor added for internal CPU block size calculation. These two equations contrast the effective
transfer rates when using internal DMA versus individual instructions to transfer 128 bytes. The effective
transfer rate is approximately four times as fast using
DMA versus using individual instructions (96 ,..,S with
DMA versus 492 ,..,S non-DMA).
Equation 4. Effective Internal FIFO
Transfer Time Using Internal DMA
Effective Internal FIFO Transfer Rate with DMA
FIFO channel size • Internal DMA Burst Mode
Single Cycle DMA Time
128 Bytes * 750 ns
96,..,s
Equation 5. Effective FIFO Transfer
Time Using Individual Instructions
Effective Internal FIFO Transfer Rate without DMA
FIFO channel size * Instruction Cycle Time +
Block size calculation Time
128 Bytes * (24 oscillator periods @ 16 MHz) +
20 instructions (24 oscillator period each
@ 16 MHz)
128 * 1.5,..,s + 300,..,s
492,..,s
FIFO DMA FREEZE MODE
INTERFACE
Table 9. Typical Instruction Cycle Timings
Instruction
channel. As described above in the FIFO Data Structure section, the block size would have to be determined by reading the channel read and write pointer
and calculating the space available. Another alternative
uses the FIFO Overrun and Underrun Error flags to
manage the transfers by accepting error flags. In either
case the instructions needed have a significant impact
on the internal FIFO data transfer rate latency equation.
750 ns
1.5,..,s
NOTE:
t Direct = 8-bit internal data locations address. This could
be an Internal Data RAM location (0-255) or a SFR [i.e., II
o port, control register, etc.]
Byte by byte FIFO data transfers introduce an additional overhead factor not found in internal DMA operations. This factor is the FIFO block size to be transferred; the number of empty locations in the Output
channel, or the number of bytes in the Input FIFO
9-161
FIFO DMA Freeze Mode provides a means of locking
the Host out of the FIFO Input and Output channels.
FIFO DMA Freeze Mode can be invoked for a variety
of reasons, for example, to reconfigure the UPI-452 Local Expansion Bus, or change the baud rate on the serial channel. The primary reason the FIFO DMA Freeze
Mode is provided is to ensure that the Host does not
read from or write to the FIFO while the FIFO interface is being altered. ONLY the internal CPU has the
capability of altering the FIFO Special Function Registers, and these SFRs can ONLY be altered during
FIFO DMA Freeze Mode. FIFO DMA Freeze Mode
inhibits Host access of the FIFO while the internal
CPU reconfigures the FIFO.
AP-281
FIFO DMA Freeze Mode should not be arbitrarily invoked while the UPI-452 is in normal operation. Because the external CPU rnns asynchronously to the internal CPU, invoking freeze mode without first properly resolving the FIFO Host interface may have serious
consequences. Freeze Mode may be invoked only by
the internal CPU.
The internal CPU invokes Freeze Mode by setting bit 3
of the Slave Control SFR (SC3). This automatically
forces the Slave and Host Status SFR FIFO DMA
Freeze Mode to -In Progress (SSTAT SST5 = 0,
HSTAT SFR HSTl= 1). INTRQ goes active, if enabled by MODE SFR bit 4, whenever FIFO DMA
Freeze Mode is invoked to notifY the Host. The Host
reads the Host Status SFR to determine the source of
the interrupt. INTRQ and the Slave and Host Status
FIFO DMA Freeze Mode bits are reset by the Host
READ of the Host Status SFR.
During FIFO DMA Freeze Mode the Host has access
to the Host Status and Control SFRs. All other Host
FIFO interface access is inhibited. Table 10 lists the
FIFO DMA Freeze Mode status of all slave bus interface Special, Function Registers. The internal DMA
processor is disabled during FIFO DMA Freeze Mode
and the internal CPU has write access to all of the
FIFO control SFRs (Table 11).
If FIFO DMA Freeze Mode is invoked without stop-
ping the host, only the last two bytes of data written
into or read from the FIFO will be valid. The timing
diagram for disabling the FIFO module to the external
Host interface is illustrated in Figure 7. Due to this
synchronization sequence, the UPI-452 might not go
into FIFO DMA Freeze Mode immediately after the
Slave Control SFR FIFO 7 DMA Freeze Mode bit
(SC3) is set = O. A special bit in the Slave Status SFR
(SST5) is provided to indicate the status. of the FIFO
DMA Freeze Mode. The FIFO DMA Freeze Mode
INTRO OR
DROIN/DROOUT
operations described in this section are only valid after
SST5 is cleared.
Either the Host or internal CPU can request FIFO
DMA Freeze Mode. The first step is to issue an Immediate Command indicating that FIFO DMA Freeze
Mode will be invoked. Upon receiving the Immediate
Command, the external CPU should complete servicing
all pending interrupts and DMA requests, then send an
Immediate Command back to the internal CPU acknowledging the FIFO DMA Freeze Mode request.
After issuing the first Immediate Command, the internal CPU should not perform any action on the FIFO
until FIFO DMA Freeze Mode is invoked. The handshaking is the same in reverse if the HOST CPUinitiates FIFO DMA Freeze Mode.
After the slave bus interrace is frozen, the internal CPU
can perform the operations listed below on the FIFO
Special Function Registers. These operations are allowed only during FIFO DMA Freeze Mode. Table 11
summarizes the characteristics of all the FIFO Special
Function Registers' during Normal and FIFO DMA
Freeze Modes.
For FIFO
1. Changing the Channel Boundary
Reconfiguration
Pointer SFR.
2. Changing the Input and Output
Threshold SFR.
To Enhance the 3. Writing to the read and write
testability
pointers of the Input and Output
FIFO's.
4. Writing to and reading the Host
Control SFRs.
5. Controlling some bits of Host and
Slave Status SFRs.
6. Reading the Immediate Command
Out SFR and Writing to the Immediate Command in SFR.
.J
RD#/WR#
INTRO
J ______ !__________________ _
;: : A FIfO RD/WR AFTER
, • -, • INTERFACE FREEZE IS
,
INVOKED WILL CAUSE
,
HST3 OR HST7 TO BE SET
SC3
HSTI _ _ _ _ _ _ _ _ _ _ _ _ _......
292018-7
NOTE:
Timing Diagram of disabling of FIFO Module-External Host Interface.
Figure 7. Disabling FIFO to Host Slave Interface Timing Diagram
9-162
AP-281
The sequence of events for invoking FIFO DMA
Freeze Mode are listed in Figure 8.
4. The Immediate Command interrupt is responded to
immediately-highest priority-by Host and internal CPU.
1. Immediate Command to request FIFO DMA
Freeze Mode (interrupt)
5. "Respective interrupt response times
a. Host (Equation 3 above) = approximately 1.6 ).ls
b. Internal CPU is 86 oscillator periods or approximately 5.38 ).ls worst case.
2. Host/internal CPU interrupt response/service
3. Host/internal CPU clear/service all pending
interrupts and FIFO data
4. Internal CPU sets Slave Control (SLCON)
FIFO DMA
Freeze Mode bit = 0, FIFO DMA Freeze
Mode, Host Status SFR FIFO DMA Freeze
Mode Status bit = 1, INTRQ active (high)
5. Host READ Host Status SFR
Event
Immediate Command from Host
to UPI-452 to request FIFO DMA
Freeze Mode (iAPX286 WRITE)
Time
0.30 ).ls
Internal CPU interrupt response/
service
5.38 ).ls
6. Internal CPU reconfigures FIFO SFRs
Internal CPU clears FIFO-128
bytes DMA
7. Internal CPU resets Slave Control (SLCON)
FIFO DMA
Internal CPU sets Slave Control
Freeze Mode bit
0.75 ).ls
Freeze Mode bit = 1, Normal Mode, Host
Status FIFO DMA Freeze Mode Status bit =
O.
8. Internal CPU issues Immediate Command to
Host indicating that FIFO DMA Freeze Mode is
complete
Immediate Command to HostFreeze Mode in progress Host
Immediate Command interrupt
response
2.3 ).ls
Internal CPU reconfigures FIFO
SFRs
Channel Boundary Pointer SFR
Input Threshold SFR
Output Threshold SFR
or
Host polls Host Status SFR FIFO DMA Freeze
Mode bit to determine end of reconfiguration
Internal CPU resets Slave
Control (SLCON) Freeze Mode
bit = 1, Normal Mode, and
automatically resets Host Status
FIFO DMA Freeze Mode bit
Figure 8. Sequence of Events to Invoke
FIFO DMA Freeze Mode
EXAMPLE CONFIGURATION
Internal CPU writes Immediate
Command Out
An example of the time required to reconfigure the
FIFO 180 degrees, for example from 128 bytes Input to
128 bytes Output, is shown in Figure 9. The example
approximates the time based on several assumptions;
Host Immediate Command
interrupt service
1. The FIFO Input channel is full-128 bytes of data
Total Minimum Time to
Reconfigure FIFO
96.00 ).ls
0.75 ).ls
0.75 ).ls
0.75 ).ls
2.3 ).ls
0.75 ).ls
2.3 ).ls
112.33 ).ls
Figure 9. Sequence of Events to Invoke FIFO
DMA Freeze Mode and Timings
2. Output FIFO channel is empty-l byte
3. No Data Stream Commands in the FIFO.
9-163
AP·281
Table 10. Slave Bus Interface Status During FIFO DMA Freezer Mode
Interface Pln~;
A1
AO
READ
1
0
0
1
1
0
1
1
1
0
0
0
DACK
1
1
1
1
CS
0
0
0
0
A2
.0
0
0
0
1
0
0
0
0
·1
0
1
0
0
0
1
0
1
1
0
0
0
1
,1
0
1
0
1
0
0
0
.1
1
0
1
0
0
1
0
0
X
X
X
X
0
1
0
X
·X
X
X
1
0
WRITE
1
1
0
1
Operation In
Normal Mode
Read Host Status SFR
Read Host Control SFR
Write HQst Control SFR
Data or DMA data from
Output Channel
Data or DMA data to
Input Channel
Data Stream Command from
Output .Channel
Data Stream Command to
Input Channel
Read Immediate Command
Out from Output Channel
Write Immediate Command
In to Input Channel
DMA Data from Output
Channel
DMA Data to Input Channel
Status In
Freeze Mode
Operational
Operational
Disabled
Disabled
Disabled
Disabled
Disabled,
Disabled
Disabled
Disabled
Disabled
NOTE:
X = don't care
Table 11. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Label
Name
HCON
HSTAT
SLCON
SSTAT
IEP
Host Control
Host Status
Slave Control
Slave Status
Interrupt Enable
& Priority
Mod~ Register ..
InputFIFO Write Pointer
Input F!FO Read Pointer
Output FIFO Write Pointer
Output FIF.O Read Pointer
Charmel Boundary Pointer
Immediate Command In
Immediate Command Out
FIFO IN
CQMMANDIN
FIFO OUT
COMMAND OUT
Input ,FIFO Threshold
QtHer'FIFO Threshold
MODE
IWPA
IAPR
OWPR
ORPR
CBP
IMIN
IMONT
FIN
CIN
FOUT
COUT
ITHR
OTHR
Normal
Operation
(SST5 = 1)
Not Accessible
Read Only
Read & Write
Read Only
Read & Write
Read & Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read & Write
Read Only
Read Only
Read & Write
Read & Write
Read Only
Read Only
Freeze Mode
Operation
(SST5 = 0)
Read & Write
Read & Write
Re~d& Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Reacl& Write
Read & Write
Read & Write
Read Only
'Read Only
Read & Write
Read & Write
Read & Write
Read & Write
ICETM-42
8042 IN-CIRCUIT EMULATOR
•
Precise, Full-Speed, Real-Time
Emulation
- Load, Drive, Timing Characteristics
- Full-Speed Program RAM
- Parallel Ports
-Data Bus
User-Specified Breakpoints
• Execution
Trace
• - User-Specified
Qualifier Registers
- Conditional Trigger
- Symbolic Groupings and Display
-Instruction and Frame Modes
•
Full Symbolic Debugging
• Single-Line
Assembly and Disassembly
•
•
•
•
for Program Instruction Changes
Macro Commands and Conditional
Block Constructs for Automated
Debugging Sessions
HELP Facility: ICETM-42 Command
Syntax Reference at the Console
User Confidence Test of ICE-42
Hardware
Emulation Timer
The ICE-42 module resides in the Intellec Microcomputer Development System and interfaces to any user-designed 8042 or 8041A system through a cable terminating in an 8042 emulator microprocessor and a pin-compatible plug. The emulator processor, together with 2K bytes of user program RAM located in the ICE-42 buffer
box, replaces the 8042 device in the user system while maintaining the 8042 electrical and timing characteristics. Powerful Intellec debugging functions are thus extended into the user system. Using the ICE-42 module,
the designer can emulate the system's 8042 chip in real-time or single-step mode. Breakpoints allow the user
to stop emulation on user-specified conditions, and a trace qualifier feature allows the conditional collection of
1000 frames of trace data. Using the single-line 8042 assembler the user may alter program memory using the
8042 assembler mnemonics and symbolic references, without leaving the emulator environment. Frequently
used command sequences can be combined into compound commands and identified as macros with userdefined names.
210818-1
9-165
November 1986
Order Number: 210818-002
inter
ICETM_42
computer. Thus, the ICE-42 module provides the
ability to debug a prototype or production system at
any stage in its development without introducing extraneous hardware or software test tools.
FUNCTIONAL DESCRIPTION
Integrated Hardware and Software
Development
The ICE-42 emulator allows hardware and software
development to proceed interactively. This approach
is more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-42 module, prototype hardware can be added to the system
as it is designed. Software and hardware integration
occurs while the product is being developed. Figure
1 shows the ICE-42 emulator connected to a user
prototype.
The ICE-42 emulator assists four stages of development.
SOFTWARE DEBUGGING
This emulator operates without being connected to
the user's system before any of the user's hardware
is available. In this stage ICE-42 debugging capabilities can be used in conjunction with the Intellec text
editor and 8042 macro-assembler to facilitate program development.
Symbolic Debugging
The ICE-42 emulator permits the user to define and
to use symbolic, rather than absolute, references to
program and data memory addresses. Thus, there is
no need to recall or look up the addresses of key
locations in the program, or to become involved with
machine code.
When a symbol is' used for memory reference in an
ICE-42 emulator command, the emulator supplies
the corresponding location as stored in the ICE-42
emulator symbol table. This table can be loaded with
the symbol table produced by the assembler during
application program assembly. The user obtains the
symbol table during software preparation simply by
using the "DEBUG" switch in the 8042 macroassembler. Furthermore, the user interactively modi~
fies the emulator symbol table by adding new symbols or changing or deleting old ones. This feature
provides greatflexibility in debugging and minimizes
the need to work with hexadecimal values.
Through symbolic references in combination with
other features of the emulator, the user can easily:
HARDWARE DEVELOPMENT
• Interpret the results of emulation activity collected during trace.
The ICE-42 module's precise emulation characteristics and full-speed program RAM make it a valuable
tool for debugging hardware.
• Disassemble program memory to mnemonics, or
assemble mnemonic instructions to executable
code.
SYSTEM INTEGRATION
Integration of software and hardware begins when
any functional element of the user system hardware
is connected to the 8042 socket. As each section of
the user's hardware is completed, it is added to the
prototype. Thus, each section of the hardware and
software is "system" tested in real-time operation as
it becomes available.
SYSTEM TEST
When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-42 module is then used for real-time emulation of the 8042 chip to debug the system as a completed unit.
The final product verification test may be performed
using the 8742 EPROM version of the 8042 micro-
• Reference labels or addresses defined in a user
program.
Automated Debugging and Testing
MACRO COMMAND
A macro is a set of commands given a name. A
group of commands executed frequently can be defined as a macro. The user executes the group of
commands by typing a colon followed by the macro
name. Up to ten parameters may be passed to the
macro.
Macro commands can be defined at the beginning of
a debug session and then used throughout the
whole session. One or more macro definitions can
be saved on diskette for later use. The Intellec text
editor may be used to edit the macro file. The macro
definitions are easy to include in any later emulation
session.
9-166
infef
ICETM_42
The power of the development system can be applied to manufacturing testing as well as development by writing test sequences as macros. The macros are stored on diskettes for use during system
test.
Table 1. Major Emulation Commands
Command
COMPOUND COMMAND
Compound commands provide conditional execution
of commands (IF command) and execution of commands repeatedly until certain conditions are met
(COUNT, REPEAT commands).
Compound commands may be nested any number
of times, and may be used in macro commands.
GO
BRO, BR1, BR
Sets or displays either or both
Breakpoint Registers used for
stopping real-time emulation.
STEP
Performs single-step
emulation.
ORO,OR1
Specifies match conditions
for qualified trace.
TR
Specifies or displays tracedata collection conditions and
optionally sets Oualifier
Register (ORO, OR1).
Synchronization
Line Commands
Sets and displays status of
synchronization line outputs
or latched inputs. Used to
allow real-time emulation or
trace to start and stop
synchronously with external
events.
Example:
'DEFINE.I=O
;Define symbol. I to 0
'COUNT lOOH
;Repeat the following
commands lOOH times.
• 'IF. I AND 1 THEN ;Check i f . I is odd
•• 'CBYTE.I=.I
;Fill the memory at
location. I to value. I
•• 'END
Description
Begins real-time emulation
and optionally specifies break
conditions.
Breakpoints
.'.1-.1+1
;Increment • I by l.
.·END
;Command executes
upon carriage-return
after END
(The asterisks are system prompts; the dots indicate
the nesting level of compound commands.)
Operating Modes
The ICE-42 software is an Intellec RAM-based program that provides easy-to-use commands for initiating emulation, defining breakpoints, controlling trace
data collection, and displaying and controlling system parameters. ICE-42 commands are configured
with a broad range of modifiers that provide maximum flexibility in describing the operation to be per.
formed.
The ICE-42 hardware includes two breakpoint registers that allow halting of emulation when specified
conditions are met. The emulator continuously compares the values stored in the breakpoint registers
with the status of specified address, opcode, operand, or port values, and halts emulation when this
comparison is satisfied. When an instruction initiates
a break, that instruction is executed completely before the break takes place. The ICE-42 emulator
then regains control of the console and enters the
interrogation mode. With the breakpoint feature, the
user can request an emulation break when the program:
• Executes an instruction at a specific address or
within a range of addresses.
• Executes a particular opcode.
• Receives a specific signal on a port pin.
• Fetches a particular operand from the user program memory
EMULATION
The ICE-42 module can emulate the operation of
prototype 8042 system, at real-time speed (up to
12 MHz) or in single steps. Emulation commands to
the ICE-42 module control the process of setting up,
running, and halting an emulation of the user's 8042based system. Breakpoints and tracepoints enable
the ICE-42 emulator to halt emulation and provide a
detailed trace of execution in any part of the user's
program. A summary of the emulation commands is
shown in Table 1.
9-167
• Fetches an operand from a specific address in
program memory.
inter
ICETM-42
conditional trace activity. The qualifiers can be used
to condition trace data collection to take place as
follows:
Trace and Tracepoints
Tracing is used with real-time and single-step emulation to record diagnostic information in the trace
buffer as a program is executed. The information
collected includes opcodes executed, port values,
and. memory addresses. The ICE-42 emulator collects 1000 frames of trace data.
• Under all conditions (forever).
• .only while the trace qualifier is satisfied.
• For the frames or instructions preceding the time
when a trace qualifier is first satisfied (pre-trigger
trace).
If desired this information can be displayed as assembler instruction mnemonics for analysis during
interrogation or single-step mode. The trace-collection facility may be set to run conditionally or unconditionally. Two unique trace qualifier registers, specified in the same way as breakpoint registers, govern
• For the frames or instructions after a trace qualifier is first satisfied (post-triggered trace).
Table 2 shows an example of trace display.
Table 2. Trace Display (Instruction Mode)
T1
DBYIN
o
0
66H
DFH
02H
0
o
o
0
DFH
DFH
o
o
o
0
0
66H
66H
66H
,0
o
o
o
0
0
0
99H
02H
02H
02H
02H
DOH
DOH
0
0
0
0
0
0
99H
99H
01H
01H
0
0
55H
55H
o
0
99H
01H
0
o
55H
55H
55H
55H
55H
55H
o
0
0
0
0
01H
01H
01H
01H
0
0
0
0
55H
55H
55H
55H
55H
55H
o
o
99H
01H
0LH
0
0
99H
INC
R1
DJNZ R2, .LOOP
55H
55H
55H
55H
01H
01H
0
0
99H
0L1i
0
FO
Al
MOV
MOV
A,@RO
@Rl,A
55H
55H
99H
D1H
0
10FH
18
INC
RO
0060:
0062:
110H
l11H
19
EAOD
INC
Rl
DJNZ R2, .LOOP
0066:
113H
00
NOP
55H
55H
55H
55H
01H
01H
01H
01H
0LH
0
0
0
0
0
FRAME
LOC
OBJ
INSTRUCTION
Pl
P2
0000:
0004:
0008:
0012:
0014:
0016:
100H
102H
103H
104H
105H
106H
2355
39
3A
22
37
02
.
MOV
OUTL
OUTL
IN
CPL
OUT
A, # 55H
Pl, A
P2, A
A,DBB
A
DBB,A
FFH
FFH
55H
FFH
FFH
FFH
0018:
0022:
107H
109H
BA03
B840
MOV
MOV
R2,#03H
RO,#.TABLEO
55H
55H
55H
55H
55H
55H
55H
55H
55H
55H
0026:
.LOOP
0030:
10BH
B960
MOV
Rl,#.TABLEl
55H
55H
10DH
FO
MOV
A,@RO
0032:
0034:
0036:
0038:
10EH
10FH
110H
l11H
Al
18
19
EAOD
MOV
INC
INC
DJNZ
@Rl,A
RO
Rl
R2, .LOOP
55H
. 55H
• LOOP
0042:
0044:
0046:
0048:
0050:
10DH
10EH
10FH
110H
l11H
FO
Al
18
19
EAOD
MOV
MOV
A,@RO
@Rl,A
INC
RO
.LOOP
0054:
0056:
10DH
10EH
0058:
TO
o
o
o
o
0
66H
66H
99H
66H
66H
66H
0
66H
66H
55H
55H
o
o
0
55H
55H
55H
'55H
o
o
66H
0
0
0
o
o
DFH
66H
66H,
0
o
0
0
0
0
0
YOUT YSTS TOVF
99H
66H
99H
66H
66H
99H
99H
210818-2
9-168
intJ
ICETM-42
INTERROGATION AND UTILITY
Single-Line Assembler/Disassembler
Interrogation and utility commands give convenient
access to detailed information about the user program and the state of the 8042 that is useful in debugging hardware and software. Changes can be
made in memory and in the 8042 registers, flags,
and port values. Commands are also provided for
various utility operations such as loading and saving
program files, defining symbols, displaying trace
data, controlling system synchronization and returning control to ISIS-II. A summary of the basic interrogation and utility commands is shown in Table 3.
Two additional time-saving emulator features are
discussed below.
The single-line assembler/disassembler (ASM and
DASM commands) permits the designer to examine
and alter program memory using assembly language
mnemonics, without leaving the emulator environment or requiring time-consuming program reassembly. When assembling new mnemonic instructions
into program memory, previously defined symbolic
references (from the original program assembly, or
subsequently defined during the emulation session)
Table 3. Major Interrogation and Utility Commands
Command
Description
HELP
Displays help messages for ICE-42 emulator command-entry assistance.
LOAD
Loads user object program (8042 code) into user-program memory, and user symbols
into ICE-42 emulator symbol table.
SAVE
Saves ICE-42 emulator symbol table and/or user object program in ISIS-II
hexadecimal file.
LIST
Copies all emulator console input and output to ISIS-II file.
EXIT
Terminates ICE-42 emulator operation.
DEFINE
Defines ICE-42 emulator symbol or macro.
REMOVE
Removes ICE-42 emulator symbol or macro.
ASM
Assembles mnemonic instructions into user-program memory.
DASM
Disassembles and displays user-program memory contents.
Change/Display
Commands
Change or display value of symbolic reference in ICE-42 emulator symbol table,
contents of key-word references (including registers, I/O ports, and status flags), or
memory references.
EVALUATE
Evaluates expression and displays resulting value.
MACRO
Displays ICE-42 macro or macros.
INTERRUPT
Displays contents for the Data Bus and timer interrupt registers.
SECONDS
Displays contents of emulation timer, in microseconds.
Trace Commands
Position trace buffer pointer and select format for trace display.
PRINT
Displays trace data pointed to by trace buffer pointer.
MODE
Sets or displays the emulation mode, 8041 A or 8042.
9-169
intJ
ICETM_42
Table 4, HELP Command
-HELP
Helpis available for the following items. Type HELP followed by the item name·
The help items cannot be abbreviated. (for more information, type HELP HELP or
HELP INfO.• )
Emulation:
Trace Collection:
Mi sc:
GO GR SYO
TR
QR
QRO QR1 SY1 BASE
DB-ABLE
BR BROBR1
STEP
Trace Display:
ENABLE
< ICE 42 # keyword>
TRACE
MOVE
PRINT
ERROR
EVALUATE
OLDEST NEWEST
HELP
< masked#c onstant >
Change/
Display/ Define/ Remove: INfO
REMOVE
CBYTE
< LIGHTS >
< numer i c .cons tant >
SYMBOL
DBYTE
DASM
LIST
REGISTER
ASM
RESET
LOAD
MODE
SECONDS
WRITE
SAVE
'
DEFINE
STACK
SY
SUffIX
SYMBOLIC
Macro:
Compound
< trace.re ference >
DEfINE
< unl imi ted.match.cond>
DIR
Commands:
DISABLE
ENABLE COUNT
INCLUDE
PUT
If
REPEAT
--
- HELP If
IF - The conditional command allows conditional execution of one or more commands
based on the values of boolean conditions·
If 'THEN
: :=' @
;;=' @
: :=An ICE-42 command.
'ORIf
@
'ELSE
END
The s are evaluated in order as 1b-bit unsigned integers, If one is
reached whose value has low-order bit 1 (TRUEl , all commands in the
following that are then executed and all commands in the other s and in the are skipped. If all s have value with loworder bit 0 (fALSE), then all commands in all s are skipped and, i f
ELSE is present, all commands in the are executed.
(EX: If. LOOP=5 THEN
'
STEP
ELSE
GO
END)
---
H XIT
210818-3
9-170
intJ
ICETM-42
may be used in the instruction operand field. The
emulator supplies the absolute address or data values as stored in the emulator symbol table. These
features eliminate user time spent translating to and
from machine code and searching for absolute addresses, with a corresponding reduction in transcription errors.
HELP
The HELP file allows display of ICE-42 command
syntax information at the Intellec console. By typing
"HELP", a listing of all items for which help messages are available is displayed. Typing "HELP
< Item>" then displays relevant information about
the item requested, including typical usage examples. Table 4 shows some sample HELP messages.
EMULATION ACCURACY
The speed and interface demands of a high-performance single-chip microcomputer require extremely accurate emulation, including full-speed,
real-time operation with the full function of the microcomputer. The ICE-42 module achieves accurate
emulation with an 8042 emulator chip, a special configuration of the 8042 microcomputer family, as its
emulation processor.
Each of the 40 pins on the user plug is connected
directly to the corresponding 8042 pin on the emulator chip. Thus the user system sees the emulator as
an 8042 microcomputer at the 8042 socket. The resulting characteristics provide extremely accurate
emulation of the 8042 including speed, timing characteristics, load and drive values, and crystal operation. However, the emulator may draw more power
from the user system than a standard 8042 family
device.
Additional emulator processor pins provide signals
such as internal address, data, clock, and control
lines to the emulator buffer box. These signals let
static RAM in the buffer box substitute for on-chip
program ROM or EPROM. The emUlator chip also
gives the ICE module "back-door" access to internal
chip operation, allowing the emulator to break and
trace execution without interfering with the values on
the user-system pins.
9-171
210818-4
Figure 1. A typical B042 Development
Configuration. The host system is an Intellec
Series IV. The ICE-42 module is connected to a
user prototype system.
SPECIFICATIONS
ICETM-42 Operating Requirements
Intellec Model 800, Series II, Series III, or Series IV
Microcomputer Development System (64K RAM required)
System console (Model 800 only)
Inteliec Diskette Operating System: ISIS (Version
3.4 or later).
Equipment Supplied
• Printed circuit boards (2)
• Emulation buffer box, Intellec interface cables,
and user-interface cable with 8042 emulation
processor
• Crystal power accessory
• Operating instructions manuals
• Diskette-based ICE-42 software (single and double density)
ICETM-42
Emulation Clock
Electrical Characteristics
User's system clock (up to 12 MHz) or ICE-42 crystal power accessory (12 MHz)
DC Power Requirements
(from Intellec® system)
Environmental Characteristics
Operating Temperature: O°C to 40°C
Operating Humidity: Up to 95% relative humidity
without condensation.
Physical Characteristics
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Vee = +5V, ±5%
lee = 13.2A max; 11.0A typical
Voo = + 12V, ±5%
100 = 0.1 A max; 0.05A typical
Vss = -10V, ±5%
Iss = 0.05A max; 0.01A typical
User plug characteristics at 8042 socket-8ame
as 8042 or 8742 except that the user system sees
an added load of 25 pF capacitance and 50 /LA leakage from the ICE-42 emulator user plug at ports 1, 2,
TO, and T1.
ORDERING INFORMATION
Buffer Box
Part Number Description
ICE-42
Width: 8.00 in. (20.32 cm)
Length: 12.00 in. (30.48 cm)
Depth: 1.75 in. (4.44 cm)
Weight: 4.0 Ib (1.81 kg)
9-172
8042 Microcontrolier In-Circuit
Emulator, cable assembly and interactive diskette software
iUP-200A/iUP-201A UNIVERSAL
PROM PROGRAMMERS
MAJOR iUP-200A/iUP-201A FEATURES:
•
Personality Module Plug-Ins Provide
Programming Support for Intel and
Intel-Compatible EPROMs, EPLDs,
Microcontrollers, Flash Memories, and
other Programmable Devices
•
PROM Programming Software (iPPS)
Makes Programming Easy with IBM PC,
XT, AT, and PC Compatibles
•
Supports Personality Modules and
GUPI Base WI Adaptors
•
iUP-200A Provides On-Line Operation
with a Built-In Serial RS232 Interface
and Software for a PC Environment
•
iUP-201A Provides Same On-Line
Performance and Adds Keyboard and
Display for Stand-Alone Use
•
iUP-201A Stand-Alone Capability
Includes Device Previewing, Editing,
Duplication, and Download from any
Source Over RS232C Port
•
Updates and Add-Ons Have Maintained
Even the Earliest iUP-200 and iUP-201
Users at the State-of-Art
The iUP-200A and iUP-201A universal programmers program and verify data in Intel and Intel compatible,
programmable devices. The iUP-200A and iUP-201A universal programmers provide on-line programming and
verification in a growing variety of development environments using the Intel PROM programming software
(iPPS). In addition, the iUP-201A universal programmer supports off-line, stand-alone program editing, duplication, and memory locking. The iUP-200A universal programmer is expandable to an iUP-201A model.
210319-1
9-173
October 1988
Order Number: 210319-005
inter
iUP-200AliUP-201A
• Verifies device data with buffer data
FUNCTIONAL DESCRIPTION
• Locks device memory from unauthorized access
(on devices which support this feature)
The iUP-200A universal programmer operates in online mode. The iUP-201 A universal programmer operates in both on-line and off-line mode.
• Prints device contents on the network or development system printer
• Performs interactive formatting operations such
as interleaving, nibble swapping, bit reversal, and
block moves
On-Line System Hardware
The iUP-200A andiUP-201 A universal programmers
are free-standing units that, when connected to a
host. compu.ter with at least 64K bytes of memory,
provide on-line programming and verification of Intel
programmable devices. In addition, the universal
programmer can read the contents of the ROM versions of supported devices.
The universal programmer communicates with the
host through a standard RS232C serial data link. Different versions of the iUP-200A and iUP-201 A are
equipped with different cables, including the cable
most commonly used for interfacing to that host.
Care should be taken that the version with the correct cable .for your particular system is selected, as
cable requirements can vary with your host configuration. A serial converter is needed when using the
MDS 800 as a host system. (Serial converters are
available from other manufacturers.)
Each universal programmer contains the CPU, selectable power supply, static RAM, programmable
timer, interface for personality modules, RS232C interface for the host system,and control firmware in
EPROM. The iUP-201 Aalso has a keyboard and display.
A personality module or GUPI Adaptor adapts the
universal programmer to a family of devices; it contains all the hardware and software necessary to
program either a family of Intel devices or a single
Intel device. The user inserts the personality module
into the universal programmer front panel.
On-Line System Software
• Programs multiple devices from the source file,
prompting the user to insert new devices
• Uses a buffer to change device contents
All iPPS commands, as well as program address and
data information, are entered through the host system ASCII keyboard and displayed on the system
CRT.
The iPPS software supports data manipulation in the
following Intel formats: 8080 hexadecimal ASCII,
8080 absolute object, 8086 hexadecimal· ASCII,
8086 absolute object, and 80286 absolute object.
Addresses and data can be displayed in binary, octal, decimal, or hexadecimal. The user can easily
change default data formats as well as number bases. iPPS can also access disk files.
For programming Intel EPLDs, the iUP-200Al201A
can be controlled by Intel's Logic Programming Software (LPS). LPS programs EPLDs from JEDEC files
produced by Intel's logic compiler. (iPPS can also
program EPLDs, but only from pre-programmed device· masters.)
System Expansion
The iUP-200A universal programmer can be easily
upgraded (by the user) to an iUP-201 A universal programmer for off-line operation. The upgrade kit (iUPPAK-A) is available from Intel or your local Intel distributor.
Off-Line System
The iUP-200A and iUP201 A includes your choice of
one copy of Intel's PROM Programming software
iPPS, selected from a list of versions for different
operating systems and hosts. Each version includes
the software implementation designed for that host
and O.S. and the RS232C cable most commonly
used. Additional versions may be purchased separately if you decide to change hosts at a later date.
The iPPS software provides user control through an
easy-to-use interactive interface. The iPPS software
performs the following functions to make EPROM
programming quick and easy:
• Reads devices
The iUP-201A universal programmer has all the online features of the iUp c200A universal programmer
plus off-line editing, device duplication, program verification, and locking of device memory independent
of the host system. The iUP-201A universal programmer also accepts Intel hexadecimal programs
developed on non-Intel development systems. Just
a few keystrokes download the program into the iUP
RAM for editing and loading into a device.
Off-line commands are entered via a 16-character
keypad. A 24-character display shows programmer
status.
• Programs devices directly or from a file
9-174
intJ
iUP-200AliUP-201A
SYSTEM DIAGNOSTICS
Both the iUP-200A and iUP-201 A universal programmers include self-contained system diagnostics that
verify system operation and aid the user in fault isolation.
Adaptors. GUPI Adaptors tailor the GUPI module
base signals to a family of devices or an individual
device. The GUPI module and GUPI Adaptors provide a lower-cost method of device support than if
unique Personality Modules were offered for each
device/family. Tables 2 and 3 show which Adaptors
support which devices.
PERSONALITY MODULES
For some devices, a personality module is the interface between the iUP-200A/iUP-201A universal programmer (or an iPDS system) and a selected device.
Personality modules contain all the hardware and
firmware for reading and programming a family of
Intel devices. Table 1 lists the devices supported by
the different modules.
For most devices, the GUPI module and interchangeable GUPI Adaptors provide the interface between the programmer and the device being programmed (see Figure 1). the GUPI (Generic Universal Programmer Interface) module is a base module
that intefaces to the iUP-200A/201A and GUPI
iUP-GUPI
GENERIC BASE MODULE
210319-12
Figure 1_ GUPI Adaptor
9-175
inter
iUP-200A/iUP-201A
Table 1. iUP Personality Programming Modules
Device Type
Fast 27/K
Module
Fast 27/K U2
Kit
Fast 271K-CON*
Kit
EPROM
2764
2764A
27128
27256
2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513
2764
2764A
27C64
87C64
27128
27128A
27256
27C256
27512
27513
F27/128
Module
F87144A
Module
F87151A
Module
8041A
8042
8044AH
8741H
8742
8744H
8748
8748H
2716
2732
2732A
2764
27128
2815
2816
E2PROM
2817A
2817A
Microcontroller
8755A
-Quick·Pulse Programming™ algorithm
9-176
8749H
8751
8751H
8048
8048H
8049
8049H
8050H
8051
intJ
iUP-200AliUP-201A
Table 2. iUP-GUPI Adaptors for Programming Memories
Device
Type
GUPI GUPI GUPI GUPI
27010 27011 27210 Flash
EPROM
GUPI
8742
GUPI
MCS-51
GUPI
8796
GUPI
GUPI
GUPI
8796LCC 87C51GB MCS-96LCC
27010
27011 27210
Flash
27F64
27F256
28F256
Peripheral
8741AH
8742AH
Microcontroller
8751H
87C51
8752BH
87C51FA 8794BH
87C51FB 8795BH
8796BH 8796BH
8797BH 8797BH
87C51GB
8797BH
87C196KB
Package
Types
DIP
DIP
DIP
DIP
DIP
PLCC
DIP
PGA
DIP
LCC
PLCC
PLCC
Table 3. Programming Adaptors for EPLDs
Device
Type
GUPI
Logic-liD
EPLD
GUPI
Logic-12
GUPI
40D44J
GUPI
Logic-18
GUPI
Logic-18PGA
GUPI
85EPLD28
GUPI
Logic-BIC
5C031
5C032
5C060
5C090
5C121
5C180
5C180G
5CBIC
5AC312
5AC324
85C508
Package
Types
DIP'
DIP
DIP
PLCC
PLCC
CJ
• ADAPT Units available to adapt DIP socket for PLCC package.
9·177
PGA
DIP
PLCC
PLCC
intJ
iUP-200A/iUP-201A
166043-001- Geffing Started with the iUP-200A/
20tA (For DOS Users).
164853
- iUP-200A/201A Universal Programmer Pocket Reference.
iUP-200A/iUP201A· SPECIFICATIONS
Control Processor
Intel 8085A microprocessor
6.144 MHz clock rate
ORDERING INFORMATION
Product
Order Code
iUP-200A 211A
Memory
RAM-4.3 bytes static
ROM-12K bytes EPROM
Interfaces
Keyboard: 16-character hexadecimal and 12-function keypad (iUP-201A model only)
Display: 24-character alphanumeric (iUP-201A
model only)
Software
Monitor- system controller in pre-programmed
EPROM
iPPS - Intel PROM programming software on
supplied diskette
Physical Characteristics
Depth:
Width:
Height:
Weight:
15 inches (38.1 cm)
15 inches (38.1 cm)
6 inches (15.2 cm)
15 pounds (6.9 kg)
Electrical Characteristics·
Selectable 100, 120, 200, or 240 Vac ± 10%; 50-60
Hz
Maximum power consumption-80 watts
Environmental Characteristics
10·C to 40·C
Reading Temperature:
Programming Temperature: 25·C ±S·
Operating Humidity:
10% to 85% relative
humidity
Reference Material
166041-001- iUP-200A/201A Universal Programmer User's Guide.
166042-001- Geffing Started with the iUP-200A/
201A (For ISIS/iNDX Users).
Description
On-Line PROM programmer with·
iPPS rei 1.4 on Single density ISIS .
II floppy
iUP-200A 2128 On-Line PROM programmer with
iPPS rei 1.4 on Double density
ISIS II floppy
iUP-200A 213C On-Line PROM programmer with
iPPS rei 2.0 for Series IV, on minifloppy
iUP-200A 2160 On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for PC or XT
iUP-200A 2170 On-Line PROM programmer with
iPPS rei 2.0 for PC/DOS, and cable for AT
iUP-201A 211A Off-Line and on-line PROM programmer with iPPS rei 1.4 on Single density ISIS II floppy
iUP-201A 2128 Off-Line and on-line PROM programmer with iPPS rei 1.4 on Double density ISIS II floppy
iUP-201 A 213C Off-Line and on-line PROM programmer with iPPS rei 2.0 for Series IV on mini-floppy
iUP-201 A 2160 Off-Line and on-line PROM pro~
gram mer with iPPS rei 2.0 for PC/
DOS, and cable for PC or XT
iUP-201A 2170 Off-Line and on-line PROM programmer with iPPS rei 2.0 for PC/
DOS, and cable for AT
iUP-200/201 U1" Upgrades an iUP-200/201 univerUpgrade Kit
sal programmer to an iUP-200A/
201 A universal programmer
iUP-DL
Download Support Kit for iUP200Al201 A upgrades programmer to support adaptors that use
software programming (.DSS)
files.
iUP-PAK-A
Upgrades an iUP-200/ A universal
Upgrade Kit
programmer to an iUP-201A universal programmer
"Most personality modules can be used only with
an iUP-200Al201A universal programmer or an
iUP-200/iUP201 universal programmer upgraded to
an A with the iUP-200/iUP-201 U1 upgrade kit.
9-178
infef
iUP-200A/iUP-201A
Product
Order Code
piUP-GUPI
Description
Generic Universal Programmer Interface (Base)
2170
Product
Order
Code
Description
212B
213C
2160
Software Sold Separately
211A
Product
Order
Code
Description
PROM programming software rei 1.4 on
Single density ISIS II floppy
PROM programming software rei 1.4 on
Double density ISIS II floppy
9-179
PROM programming software rei 2.0 for
Series IV on mini-floppy
PROM programming software rei 2.0 for
PC/DOS with cable for PC or PC XT
PROM programming software rei 2.0 for
PC/DOS with cable for PC AT
Graphics Coprocessor
Family
10
82706
INTEL VIDEO GRAPHICS ARRAY
•
Single Chip Video Graphics Array for
IBM PC/XTlAT*, Personal System/2*
and Compatible Systems
•
Inmos IMSG 171 Palette/DAC Interface
•
Available in 132-Pin Plastic Quad Flat
Pack Package
4 mA Drive Capability on Output Pins
• Implemented
• Technology in High Speed CHMOS III
100% Gate, Register, and BIOS Level
• Compatibility
with IBM VGA
• EGA/CGA/MDA BIOS Compatibility
(See Packaging Spec. Order #231369)
The 82706 is the Intel VGA compatible display controller. It is 100% register compatible with all IBM VGA
modes and provides software compatibility at the BIOS level with EGA, CGA, and MDA. All video monitors
designed for IBM PS/2' systems are supported by the Intel VGA controller. The 82706 provides an 8-bit video
data path to any Inmos IMSG 171 compatible palette/DAC. It also acts as a CRT controller and video memory
controller. The 82706 supports 256 Kbytes of video memory.
The 82706 is designed for compatibility with the Intel 80286 and 80386 microprocessors and other microprocessors.
Implemented in low power CHMOS technology, the 82706 VGA Controller is packaged in a fine pitch (25 mil)
surface mount gull wing package. It can be enabled or disabled under software control via the 82306 Peripheral Bus Controller.
'IBM PC, XT, AT, Personal System/2, PS/2, and MicroChannel are trademarks of International Business
Machines.
OS2
For complete data sheet,
see Volume I, Chapter 4
OS3
EXTCLK
MO:7
ABO:7
AO:19
RAMEN
00:7
RASO:3#
MCS#
SETUP#
CASH
VGAEN
WED
RO#
10
WR#
BLOCK
000:7
MIO
010:7
ROY
020:7
INTR
030:7
OEN#
SFOBK#
PO:7
SENSE
ATTRIBUTE
CONTROLLER
RESET
OACR#
OACW#
HSYNC
L----I
CRT
CONTROLLER
VSYNC
BLANK
OCLK
240194-2
Figure 1. Block Diagram
10-1
November 1988
Order Number: 240194-002
82716/VSDD
VIDEO STORAGE AND DISPLAY DEVICE
•
•
•
•
•
•
•
•
•
•
•
•
•
Twin Mode Operation for Higher
Throughput
•
Powerful External Sync and Overlay
Capabilities
•
•
Video Clock Rate up to 20 MHz
Low Cost Graphics and Text Capability
Minimum Chip Count Display Controller
Displays Up to 16 Bit Map arid
Character Objects of Any Size
On-Chip 16/4096 Color Palette
On-Chip DRAM Controller
On-Chip 0/ A Converters
Arbitration of Processor RAM Requests
NAPLPS and CEPT Compatible
Objects Allow Windowing or Animation
Horizontal Resolution up to 640 4-Bit
Pixels
Up to 512K Bytes of Display Memory
Compatible with 8 and 16 Bit
Processors/Micro Controllers
System Clock Rate up to 14.3 MHz
(Cohtact FlIctory for up-to-date specifications)
82716IVSDD is a low cost, highly integrated video controller_ It displays graphics and textual information using
a minimum of chips. It allows the management of up to 16 display objects on the screen at anyone time.
These objects may be formatted as bit map or character arrays and can be used for windowing or animation.
An on-chip color palette allows the selection of up to 16 colors, from a range of 4096. The palette can be
programmed to drive a set of on-chip Df A converters. The VSDD also provides DRAM controller functions.
DH,DL ADDR
CASH,
XTALIN
MEMORY
INTERFACE UNIT
MIU
XTALOUT
VIDEO
CLOCK
t----+---J
R
G
PIXEL
UNIT
B
OVR
BUS
INTERFACE UNIT
BIU
TASK
SCHEDULER
VREF--!+
CTO
I
~--------------l-------~
RST
AD
231680-1
Figure 1. VSDD Block Diagram
10-2
October 1988
Order Number: 231680-003
inter
82716/VSDD
82716
VIDEO STORAGE AND DISPLAY DEVICE
ADDITIONAL INFORMATION
You can obtain a free copy of the most recent 82716 data sheet specs by:
• Calling your local Intel sales office and ask for Order No. 231680
• Calling tOil-free (800) 548-4725 and ask for JB12
OFFER EXPIRES 12/31/89
10-3
intJ
82786
CHMOS GRAPHICS COPROCESSOR
•
•
•
•
•
Windows
• Hardware
Fast Bit-Block Copies Between System
• and Bitmap Memories
Software Support
• Third-Party
Multi-tasking Support
• Provides
Support for Rapid Filling with
High Performance Graphics
Fast Polygon and Line Drawing
High Speed Character Drawing
Advanced DRAM/VRAM Controller for
Graphics Memory up to 4 Mbytes
•
•
•
Supports up to 200 MHz CRTs
- up to 640 by 480 by 8 Bits (DRAMs)
or 1400 by 1400 by 1 Bit (DRAMs)
or 2048 by 2048 by 8 Bits (VRAMs)
to 256 Simultaneous Colors
• Up
Integral DRAM/VRAM Controller, Shift
• Registers
and DMA Channel
International Character Support
• Interface
Designed for Device• Independent
Standards
Patterns
Programmable Video Timing
Advanced CHMOS Technology
•
•
Supports Dual Port Video DRAMs &
Sequential Access DRAMs
88 Pin Grid Array and Leadless Chip
Carrier
- (See Intel Packaging; Order Number: 231369)
The 82786 is a powerful, yet simple component designed for microcomputer graphics applications including
personal computers, engineering workstations, terminals, and laser printers. Its advanced software interface
makes applications and systems level programming efficient and straight-forward. Its performance and high-integration make it a cost-effective component while improving the performance of nearly any design. Hardware
windows provide instantaneous changes of display contents and support multiple graphics applications from
multiple graphics bitmaps. Applications programs written for the IBM Personal Computer can be run within one
or more windows of the display when used with Intel CPUs.
The 82786 works with all Intel microprocessors, and is a high-performance replacement for sub-systems and
boards which have traditionally used discrete components and/or software for graphics functions. The 82786
requires minimal support circuitry for most system configurations, and thus reduces the cost and board space
requirements of many applications. The 82786 is based on Intel's advanced CHMOS III process.
"
0
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" 0
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" '"0
.., ... . , ..,
.,
"" ... ""
0
0
0
0 -0
0
0
0
0
0
lILANK
0
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0
0
Hs,.,o
Vda:to7
",.. "'"
0
0
0
VdolGll
0
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Vdala"
Vdalo2
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0
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Vdalol
Vdotal
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'"
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0
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0
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0
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0
. . , ..
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"
'
0
0
0
0
0
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R[ADl',
D"
DO'
D"
D"
0
0
0
0
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0
0
DOl
DO.
D"
'0"
'"
0
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,~
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0
0
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"
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0
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BEHOIt BEN1,1 "
oro
Dn
RASO,
0
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0
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0
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-", ""
0
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,,,.
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DO.'
.....0 ....0 , "
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,~
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0
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0
0
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0
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DOD
DO.
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0
0
0
0
0
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D"
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'" '
.
"
"
231676-27
Figure 1.82786 Pinout-Bottom View
10-4
November 1988
Order Number: 231676-004
infef
82786
INTRODUCTION
The 82786 is an intelligent peripheral capable of
both drawing and refreshing raster displays. It has
an integrated drawing engine with a high level VOl
like graphics commands. Multiple character sets
(fonts) can be used simultaneously for text display
applications. The 82786 provides hardware support
for fast manipulation and display of multiple win·
dows on the screen. It supports high resolution dis·
plays with a 25 MHz pixel clock and can display up
to 256 colors simultaneously. Using multiple 82786s
andlor in conjunction with dual port video DRAMs
(VRAMs), the 82786 is virtually unlimited in terms of
color support and resolution.
Table 1.82786 Pin Description
Symbol
Pin
Number
Type
Description
A21:0
A09,B08,A08,B07,
A06,B06,A05,B05,
A04,B04,A03,B03,
A02,B02,B01,C02,
C01 ,002,001 ,E02,
E01, F02
015:0
N12,M12,M13,L 12, 1/0 Data Bus for the 82786 Graphics memory array and the External
L13,K12,K13,J12,
Bus.
J13,H12,H13,G12,
G13,F13,F12,E13
1/0 Address lines for the External Bus. Inputs for Slave Mode
accesses of the 82786 supported Graphics memory array or
82786 internal memory or 110 mapped registers. Driven by the
82786 when it is the External Bus Master.
BHE
B13
1/0 Byte High Enable. An input of the 82786 Slave Interface; driven
LOW by the 82786 when it is Bus Master. Determines
asynchronous vs. synchronous operation for RD, WR and HLDA
inputs at the falling (trailing) edge of RESET. A HIGH state selects
synchronous operation.
RD
013
1/0 Read Strobe. An input of the 82786 Slave Interface; driven by the
82786 when it is Bus Master. Selects normalltest mode at falling
RESET.
WR
C13
1/0 Write Strobe. An input of the 82786 Slave Interface; driven by the
82786 when it is Bus Master. Selects normalltest mode at falling
RESET.
MilO
C12
1/0 Memory or 1/0 indication. An input of the 82786 Slave Interface;
driven HIGH by the 82786 when it is the Bus Master. Determines
synchronous 80286 or 80186 interface at the falling edge of
RESET. A LOW state selects a synchronous 80286 interface.
CS
012
I
Chip Select. Slave Interface input qualifying the access.
MEN
B11
0
Master Enable. Driven HIGH when the 82786 controls the External
Bus. (Le., HLDA received in response to a 82786 HREQ.) Used to
steer the data path and select source of bus cycle status
commands.
SEN
A11
0
Slave Enable. Driven HIGH when the 82786 is executing a Slave
bus cycle for an External Master into the 82786 graphics memory
or registers. Used to enable the data path and a$ a READY
indication to the External Bus Master.
READY
E12
I
Synchronous input to the 82786 when executing External Bus
cycles. Identical to 80286 READY.
10·5
82786
Table 1.82786 Pin Description (Continued)
Pin
Number
Type
Description
HREQ
B12
0
Hold Request. Driven HIGH by the 82786 when an access is being
made to the External Bus by the Display or Graphics Processors.
Remains HIGH until the 82786 no longer needs the External Bus.
HlDA
A12
I
Hold Acknowledge. Input in response to a HREQ output.
Asynchronous vs. synchronous input determined by state of BHE
pin at falling RESET.
INTR
B10
0
Interrupt. The logical OR of a Graphics Processor and Display
Processor interrupt. Cleared with an access to the Biu Control
Register.
RESET
A10
I
Reset input, internally synchronized, halts all activity on the 82786
and brings it to a defined state. The leading edge of RESET
synchronizes the 82786 clock to phase 2. The trailing edge
latches the state of BHE to establish the type of Slave Interface. It
also latches RD, WR and MIO) t08et certain test modes.
ClK
B09
I
Double frequency clock input. Clock input to which pin timings are
referenced. 50% duty cycle.
CASO
M09
0
Column Address Strobe O. Drives the CAS inputs of the even word
Graphics memory bank if interleaved; identical to CAS1 if non
interleaved Graphics memory. Capable of driving 16 DRAMI
VRAM CAS inputs.
CAS1
N09
0
Column Address Strobe 1. Drives the CAS inputs of the odd word
Graphics memory bank if interleaved; identical to CASO if non·
interleaved Graphics memory. Capable of driving 16 DRAMI
VRAM CAS inputs.
M07,N08,M08
0
Row Address Strobe. Drives the RAS input pins of up to 16
DRAMsIVRAMs. Drives the first three rows of both banks of
Graphics memory.
DRA9/RAS3
N06
0
Multiplexed most significant Graphics memory address line and
RAS3. DRA9 when using 1 Mb DRAMS; RAS3 otherwise.
WEl
N10
0
Write Enable low Byte; Active lOW strobe to the lower order byte
of Graphics memory.
WEH
M10
0
Write Enable High Byte. Active lOW strobe to the higher order
byte of Graphics memory.
DRA8:0
M06,N05,M05,
N04,M04,N03,
M03,N02,M02
0
Multiplexed Graphics memory Address. Graphics memory row and
column address are multiplexed on these lines. Capable of driving
32 DRAMsIVRAMs.
BEN1:0
DT1:0
N11,M11
0
Multiplexed Bank Enable and Data Transfer Line. In normal
memory cycle enables the output of the Graphics memory array
on to the 82786 data bus, 015:0. In data transfer cycle, loads the
serial register in dual port video DRAMs (VRAMs). BEN1 IDT1 and
BENO/DTO control Bank1 and BankO respectively.
BLANK
F01
Symbol
RAS2:0
1/0 Output used to blank the display at particular positions on the
screen. May also be configured as input to allow the 82786 to be
synchronized with external sources.
10·6
82786
Table 1.82786 Pin Description (Continued)
Pin
Number
Symbol
Type
Description
H02,J01,J02,
K01 ,K02,L01,
L02,M01
0
Video data output.
VCLK
H01
I
Video Clock input used to drive the display section of the 82786.
Maximum frequency of 25 MHz.
HSYNC /WSO
G02
1/0 Horizontal Sync. Window status is multiplexed on this pin. May
also be configured as input to allow the 82786 to be synchronized
with external sources. May also be configured to output Window
status.
VSYNC /WS1
G01
I/O Vertical Sync. Window status is multiplexed on this pin. May also
VOATA7:0
be configured as input to allow the 82786 to be synchronized with
external sources. May also be configured to output Window status.
VSS
A01 ,N01 ,A 13,
N13
4 VSS pins.
VCC
N07,A07
2 Vcc pins.
82786
GRAPHICS
PROCESSOR
DISPLAY
PROCESSOR
SYSTEM ADDRESS BUS
.J,
SYSTEM
MEMORY
.. .
f---+
"'"
....
I ..
BUS INTERFACE
UNIT (BIU)
DISPLAY
DRAM/VRAM
CONTROLLER
CPU
~
~
82786
...
SYSTEM DATA BUS
....
.
DATA
BUS
X-CVER
1
...
~
....
....
GRAPHICS
MEMORY
231676-2
Figure 2
ARCHITECTURE
Display Processor
The 82786 is a high integration device which contains three basic modules (figure 2):
The 82786 Display Processor controls the CRT timings and generates the serial video data stream for
the display. It can assemble several windows on the
screen from different bitmaps scattered across the
memory accessible to the 82786.
1. Display Processor (DP)
2. Graphics Processor (GP)
3. Bus Interface Unit (BIU) with DRAMIVRAM
Controller.
10-7
intJ
82786
Graphics Processor
The 82786 Graphics Processor executes commands
from a Graphics Command Siock (GCMS) (placed in
memory by the host CPU) and updates the bitmap
memory for the Display Processor. The Graphics
Processor has high level VDI like commands and
can draw graphical objects and text at high speeds.
Bus Interface Unit (BIU)
The SIU controls all communication between the
82786, external CPU and memory. The SIU includes
an integrated DRAMIVRAM controller that can take
advantage of the high speed burst access modes of
page mode and fast page mode DRAMs to perform
block transfers. The Display Processor and Graphics
Processor use the SIU to access the bitmaps in
memory.
An 82786 request for the bus is indicated by a high
level on the HREQ line. The 82786 drives the external bus (A21:0, D15:0, RD, WR, Mia and SHE) only
after receiving a HLDA (acknowledge) from the external master. The HLDA line could be externally
synchronized (82786 synchronous mode) or internally synchronized (82786 asynchronous mode).
The 82786 will deactivate the HREQ line when it no
longer needs to access external memory or when it
senses an inactive HLDA. The 82786 indicates that
it is in control of the external bus by a high level on
the MEN output. Screen corruption can occur if the
master mode bus cycle, including HREQ/HLDA latency, is too long.
Slave Mode
The 82786 Slave Interface allows an external CPU
access into the graphics memory array or the 82786
Internal Registers. The external CPU directs a
(read/write~ave access to the 82786 by asserting
the 82786 CS input. When the 82786 is not driving
the external bus, the A21 :0, RD, WR, Mia and SHE
lines are inputs. The RD, WR, Mia and CS lines are
constantly monitored by the 82786 to detect a CPU
cycle directed at the 82786. After beginning a slave
access to the 82786, the external CPU must go into
a wait state. The 82786 will not process new slave
commands from the CPU before the previous command has been serviced. The 82786 initiates a slave
access by a high level on the SEN output and terminates the slave access when SEN is low. The data
bus transceivers can be enabled by SEN.
Memory Structure and Internal
Registers
The 82786 address range is 4 Mbytes. This is divided between the graphics memory directly supported
by the 82786 and external system memory. The
82786 distinguishes between graphics memory and
external system memory by assuming graphics
memory space starts at address OH and goes up to
whatever amount of graphics memory is configured.
External system memory occupies the rest of the
address space. The amount 0.1 graphics memory
configured, and therefore the graphics memory/external system memory boundary, is controlled by the
"DRAMIVRAM Control Register" in the SIU. The
upper limit of configured graphics memory is 4
Mbytes.
A 128 byte block (contiguous) of internal control registers is distributed throughout the three modules on
the 82786. This block can be either memory or I/O
mapped in the CPU address space. The base address and memory or I/O mapped for this register
block is programmable through the "Internal Relocation Register" in the SIU.
SEN as Slave Ready Indication
Inverted SEN should be connected to the 82284
. ARDY input when the Slave Interface is set in synchronous 80286 mode. The number of wait states
for a read cycle is a function of the DRAMIVRAM
speed. Write cycles execute with .2 wait states because the 82786 issues SEN with different timing
during write cycles.
The 82786 supports byte accesses to graphics
memory. The combination of SHE and AO generate
the proper WEL and WEH signals. SHE and AO are
ignored for read cycles. Since the Display and
Graphics Processors always generate word addresses, the slave cycles directed to graphics memory are the only time WEL may not exactly follow
WEH.
External Memory Access (Master
Mode)
.
The 82786 initiates "Master Mode" whenever it
needs to access a memory address that is beyond
the upper limit of configured graphics memory. This
memory is typically external memory shared between the 82786 and the external CPU. The bus timings in this mode are similar to the 80286 style bus
timings.
The 82786 will acknowledge a slave access from an
external CPU while waiting for an acknowledge
(HLDA) to its own request for the external bus. This
prevents a potential deadlock situation.
10-8
intJ
82786
Synchronous/Asynchronous
Operation
MEMORY ACCESS ARBITRATION
The BIU receives requests to access the graphics
memory from the Display Processor, the Graphics
Processor and the External CPU. Additionally the internal DRAMIVRAM Controller also generates refresh requests. The DRAMIVRAM refresh requests
are always highest priority. The other requests are
arbitrated with programmable priorities. A higher priority request can interrupt lower priority memory cycles. Block transfers however can only be interrupted on doubleword boundaries.
The synchronous/asynchronous mode is selected
by the state of the BHE input at the falling edge of
reset. A high state selects synchronous operation.
The synchronous interface requires that the 82786
and the 80286/80186 clock inputs are shared. For
the 80286 case, a common RESET ensures that the
82786 and the 80286 initialize to the same state.
With the 80186, external hardware must ensure that
the 82786 phase1 is coincident with the 80186
CLKOUT LOW. In the Master Mode, the HLDA line is
sampled synchronously or asynchronously. The
82786 slave interface provides for synchronous or
asynchronous sampling of the command lines (RD
and WR).
There are two priority levels for requests from the
Display and Graphics Processors:· a First Priority
(FPL) and a Subsequent Priority (SPL). The First Priority is the priority at which the first request of a bus
cycle is arbitrated with. The Subsequent Priority is
the priority associated with subsequent requests of a
block transfer bus cycle. This allows for block transfers to execute with a different priority level. If a
higher priority request occurs while a block transfer
is executing, the BIU suspends the current block
transfer and acknowledges the higher priority request. After completion of that higher priority memory access, the requests are arbitrated again. The
suspended block transfer is arbitrated with its SPL
priority since it is still executing a block transfer. The
External Request has no Subsequent Priority level
since it cannot execute block transfers. It does have
an Altered Priority, though, which is the priority it assumes once every 42 CLK's (maximum bus latency
for IBM PC's). The default priorities from highest to
lowest following RESET are:
EIGHT AND SIXTEEN BIT HOST
On reset, the 82786 always assumes an 8 bit host
interface. The first few accesses to the 82786 must
be 8 bit accesses. The 82786 can be switched to a
16 bit interface by setting the "BCP" bit in the "BIU
Control Register".
In 16 bit mode, the Internal Register Block is only
word addressable. Odd word or odd byte accesses
to the internal locations will not produce the desired
result. Even byte access, however will work as desired. The least significant address bit, AO, is ignored
in 16 bit mode.
In 8 bit mode, the internal registers must be accessed by two successive bus cycles. This is not
necessary for reads, but is necessary for writes to
the internal registers. The low byte (AO = 0) must be
written first, followed by the high byte (AO = 1) of
the register. A21:1 must be the same for both bus
cycles. The register is not changed until the second
byte (the high byte) is written to the 82786. There is
no restriction on the time between the two bus cycles, but if successive low bytes are written before a
high byte is written, the last low byte is the one written to the register. The BIU latches even bytes (AO
= 0) of write data in a temporary register. When an
odd byte is subsequently written to location address
+ 1, this byte and the even byte in the temporary
register are written to the desired location. A lock
out mechanism prevents a high byte write to modify
an internal register if there is no valid word in the
temporary register.
External
External
Display
Graphics
Displays
Graphics
APL
FPL
FPL
FPL
SPL
SPL
7
7
6
5
3
2
Three bits describe the priorities; 7 is the highest
and 0 is the lowest. If two priority registers are programmed with the same value, a default priority
chain is used. The default order is, from highest to
lowest priority:
1. Display Processor
2. Graphics Processor
3. External
Graphics Memory Interface
The 82786 directly supports up to 32 DRAMs without additional external logic. This capability allows
the use of cost effective memory devices and can
result in significant performance improvement
through the use of either standard Page Mode or the
newer Fast Page Mode/Static Column Decode sequential access RAMs. The Fast Page Mode/Static
There is no crossing done by the 82786 in 8 bit
mode: low bytes are transferred on the low data
lines D7:0 and the high bytes on D15:8. An external
crossover creates the 8 bit bus for the host. This is
not additional hardware since a crossover is needed
for an 8 bit host accessing of the memory array anyway.
10-9
inter
82786
Column Decode parts enable the 82786 to cycle the
DRAMs in 100 ns instead of the 200 ns used for
Page Mode parts. The 82786 also allows the memory to consist of either standard single port memory
devices or dual port Video RAM devices (VRAMs).
The 82786 supports a wide range of DRAMIVRAM
configurations. The choices include interleaving or
non-interleaving (1 or 2 banks - one CAS line/bank),
number of rows per bank (1, 2, 3 or 4 - one RAS
line/row), width (x1, x4 or x8), height (16k, 64k, 256k
or 1M) and performance (Page Mode or Fast Page
Mode/Static Column Mode). The only limitation is
the address space limit of 4Mbytes. The 82786
DRAMIVRAM address lines (DRAx) can directly
drive 32 memory devices while the RAS, CAS, WE
and BEN lines can directly drive 16 devices. When
the memory array consists of more than 32(16) devices then external drivers must be used to drive the
memory array.
DRAMs with a HEIGHT of 64k are not allowed in the
graphics memory of a system in which Master Mode
will be used. There is no limitation on the total
DRAM density (64k x 4 DRAMs cannot be used;
256k x 1 DRAMs are okay).
There are some special DRAM configurations:
i) When 1 Mb x 1 DRAMs are used, RAS3 is used
as DRA9.
ii) When only one interleaved row is configured
(32 devices), RAS1 is identical to RASO.Additional buffering on RASO is therefore not required.
iii) When two non interleaved rows are configure?
(32 devices), CAS1 is identical to CASO. Additional buffering on CASO is therefore not required.
DRAM Cycle Types
The 82786 supports two fundamental memory cycle
types: single and block. A single cycle involves a
single 16 bit word, while a block transfer is a minimum of 2 16 bit words with no maximum length. The
single cycle types supported and their cycle times
are given below. The cycle times are counted in system clocks, % the ClK input frequency.
1. Single Reads 3 cycles 300 ns
2. Single Writes 3 cycles 300 ns
3. Read-Modify- 4 cycles 400 ns
Writes
@
@
@
10 MHz
10 MHz
10 MHz
The block cycles use the high speed sequential access modes of page mode, fast page mode (ripple
mode) and static column DRAMs. Typical performance numbers for this case are:
1. Page Mode,
Non-Interleaved ,
2 cycles 10 Mb/ s @ 10 MHz
2. Page Mode,
Interleaved
3. Fast Page Mode,
Non-Interleaved
4. Fast Page Mode,
Interleaved
1 cycle 20 Mb/s
@
10 MHz
1 cycle 20 Mb/s
@
10 MHz
.5 cycles 40 Mb/s
@
10 MHz
All accesses into the graphics memory by the Display Processor use the high speed sequential access mode whenever possible. The Graphics Processor uses a single Read-Modify-Write cycles for all
pixel drawing operations. Block copy operations by
the Graphics Processor use the high speed sequential access modes. External CPU access into graphics memory is always a single read or write cycle.
When configured to interface with dual port VRAMs,
the 82786 generates Page Mode and Fast Page
Mode style control signals for memory access
through the normal random access port. It also executes a data transfer cycle when the video shift register in the VRAMs have to be loaded.
Graphics Memory Refresh
The BIU has an internal DRAMIVRAM refresh controller. The refresh period is programmable through
the "DRAMIVRAM Refresh Control" Register in the
BIU. All configured rows are. refreshed simultaneously by activating the corresponding RAS lines
periodically (RAS only refresh). The refresh row address (10 bits) is generated internally. On power up,
the refresh row address is undefined. On normal reset, the refresh row address is not affected. It is initialized only if the 82786 is reset into .the "BIU Test
Mode". Not modifying the refresh address during
RESET allows for a "warm RESET" implementation:
contents of DRAMIVRAM can be insured to remain
valid if RESET is short enough (less than three
DRAMIVRAM refresh cycles). DRAMIVRAM refresh will continue at the proper row after RESET
goes inactive again.
The graphics memory refresh cycles are always th~
highest priority cycles. There is some latency POSSIble between the internal refresh request and the actual refresh cycle. This latency is critical only in one
case: The 82786 is in a wait state while executing a
bus cycle on the External Bus.
The worst case is a refresh request occurring just
after the 82786 receives a HlDA from the host CPU
to execute a block transfer on the external bus. Refresh requests can interrupt block transfers, but only
on doubleword boundaries - the 82786 must execute 2 full bus cycles on the external bus before the
refresh cycle is run. The possibility of many wait
states when executing these two bus cycles creates
a need for a large refresh latency tolerance. The
82786 can queue up to 3 refresh requests internally.
10-10
82786
In the default mode (a refresh request occurs every
15.2 micro seconds and at 10 MHz operation), this
implies that each bus cycle to external memory
should not have more than 225 wait states.
wait states. For instance, the 80286 can execute 2
wait state synchronous write cycles. The 80186 can
execute write cycles with one less wait state than
mentioned above.
There is no warm up logic on the 82786. The system
must either wait for sufficient number of refresh cycles to execute or the boot software on the host can
quickly access the memory array for the required
number of cycles.
For asynchronous interfaces, if the CPU is operating
at the same frequency as the 82786, the number of
wait states are typically 1 more than those indicated
above. For CPUs operating at a slower frequency
than the 82786, the number of wait states are, on
the average, less than 1 greater than those given
above. In some cases, (eg. a 6 MHz 80286) an asynchronous interface acutally has less wait states than
those quoted above for the synchronous interface.
The default value of the DRAMIVRAM Control Register configures the array as 4 rows of Non-Interleaved Page Mode 256k x 1 with refresh requests
generated every 15.2 micro seconds.
INTERNAL REGISTERS
Internal Register and Graphics
Memory Slave Access
The 82786 Internal Register block is relocatable by
programming an even byte address in the "Internal
Relocation Register" in the BIU. The register block
can be memory or liD mapped based on the state
of the MilO bit. The Register Block is physically distributed between the three 82786 modules, BIU,
Graphics Processor and Display Processor.
The external master can access either 82786 internal memory liD mapped registers or the Graphics
memory. The 82786 internal address space consists
of a contiguous 128-byte block that starts on an
even byte address. It is mapped to memory or'110
space depending on the state of the MilO bit in the
"Internal Relocation Register". If the MilO bit is set
to one, the Internal Register Block is memory
mapped. If the MilO bit is zero, the Internal Register
Block is liD mapped. An address comparison is
done between the Internal Relocation Register and
the incoming address to determine if the CPU access is directed to internal memoryllO mapped registers.
Accesses to reserved locations have no effect; they
execute normally but may produce indeterminate
read data. No register is altered when a write is executed to a reserved location.
Location of Internal Registers within 128 byte block:
Byte
Address
'OO-OFH
Intel reserves the right to add functions to future versions of the 82786. Users should not use reserved
locations in order to ensure future compatibility.
PERFORMANCE
Slave performance is measured here by assuming a
request is made to an idle 82786. A synchronous
interface is assumed.
'10-1FH
reserved
'20-2B H
GP Registers
'2C-3F H
reserved
'40-4A H
DP Registers
'4B-7F H
reserved
8 words
6 words
5 words
The BIU register map is as follows:
Minimum 80286 Wait States = 3
(10 MHz 80286 and 82786)
Byte
Address
Minimum 80386 Wait States = 8
(16 MHz 80386,8 MHz 82786)
BASE
Minimum 80186 Wait States = 3
(10 MHz 80186 and 82786, WT
BASE
BASE
= 1)
BASE
Minimum 80186 Wait States = 2
(10 MHz 80186 and 82786, WT
BIU Registers
+ 8H
BASE + AH
BASE + CH
BASE + EH
BASE
= 0)
The values mentioned above are for read cycles. In
some cases, write cycles can operate with fewer
10-11
+ OH
+ 2H
+ 4H
+ 6H
Internal Relocation
Reserved
BIU Control
Refresh Control
DRAM Control
Display Priority
Graphics Priority
External Priority
inter
82786
The field definitions for the BIU Registers are as follows:
Refresh Control
6
Internal Relocation
15 14 13 12 ... 4 3 2
0
Addr =
I
Base
Ad-d-re-s-s----,-I-M-IO-.I
BASE + OH
"
"
Reset valueL.s-:xxx---:O=---The Base Address determines the location of the
128 byte Internal Register Block. The MIO bit "selects between memory or I/O mapping. If it is set (1),
the Register Block is memory mapped. At RESET,
the Base Address is set so that the Internal Relocation Register is located at every 128-byte address in
the entire liD space whenever CS is asserted. The
Bas"e Address must be written into this register before any other registers can be accessed.
WT:
BCP:
GI:
0
0 0
0
Addr=BASE+8H IRW1IRWoIDC1IDCoIHT2IHT1IHTOI
RESET value:
Write Protection Two. When set (1), all
BIU Register contents are write protected,
including WP1 and this bit, WP2. The only
way to regain write access to the" BIU registers after this bit is set, is to RESET the
82786.
o
0
RWO
o
o
0
1
0
1
1 Rows
2 Rows
3 Rows
4 Rows
DC1 :0: DRAMIVRAM" Configuration. Controls the
rate of block transfers and orientation of
" CAS1 and CASO.
DC1 DCO
o
0
1
0
1
o
1
1
Page Mode, Non"lnterleaved
Page Mode, Interleaved
Fast Page Mode, Non"lnterleaved
Fast Page Mode, Interleaved
Height.
Defines
the
HT2:0: DRAMIVRAM
HEIGHT (not size) of each DRAMIVRAM
chip in the system, All DRAMslVRAMs
must be the same size.
Graphics Processor Interrupt. Set when
the Graphics Processor issues an Interrupt. Cleared with RESET or a read of this
register.
WP2:
RW1
1
1
Determines whether the Internal Register
block is accessed as bytes or words by
the external CPU. If set (1), a 16 bit interface is selected.
Write Protection One. When set (1), all
BIU Register contents except for the WP1
and WP2 bits of this register are write protected.
o
1
RW1 :0: Number of Graphics memory Rows. One
of the variables in defining the Graphics
memorylExternal system boundary. Also
disables RAS signals not driving any
DRAMsIVRAMs.
Determines the minimum number of wait
states possible in a synchronous 80186
interface. If set (1), there is a minimum of
2 (3) wait states during memory write
(read) cycles.
WP1:
o
0
6543210
0
Display Processor Interrupt. Set when the
Display Processor issues an Interrupt.
Cleared with RESET or a read of this register.
o
o
DRAM/VRAM Control
If set (1) then the 82786 generates dual
port video DRAM (VRAM) tYpe memory
cycles for display data fetch. If reset (0)
then conventional page m"ode type memory cycles are performed to fetch display
data.
DI:
0
Refresh interval = (Scalar + 1)· 16 • Input clock
period
6543210
1
1
The Refresh Scalar is a 6 bit quantity that determines the frequency of refreshcycles to the Graphics memory.
Addr = BASE + 4H IVRlwTIBCpIGdDdWpllWP21
RESET value: 0
432
Refresh Scalar
RESET value:
BIU Control
VR:
5
Addr = BASE + 6H
HT2
HT1
HTO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8KDevices
16K Devices
32KDevices
64K Devices
128K Devices
256K Devices
512K Devices
1M Devices
Display Processor Priority
6 "5
Addr
10-12
= BASE + AH
RESET value:
4
3
2
FPL
1
SPL
0
0
0
I
infef
82786
Graphics Processor Priority
Addr
=
BASE
+
CH
-'j--F-P-L~'---S-P-L--'
RESET value:
0
0
0
External CPU Priority
Addr
=
BASE
+
EH -'j-=---F-P-L---'--A-P-L-
RESET value:
Specifies the priorities of the Display Processor,
Graphics Processor and External CPU requests for
the first request (FPL) and subsequent requests for
block transfers (SPL). Code 111 is highest priority.
Code 000 is lowest priority.
The Graphics Processor draws into a predefined
area in the memory which is referred to as a "bitmap". A bitmap can be thought of as a rectangular
drawing area composed of pixels. A coordinate system is defined for this bitmap with the origin at the
upper left corner, the x-coordinate increasing from
left to right and the y-coordinate increasing from top
to bottom. A bitmap can be up to 32K pixels wide
and 32K pixels high.
The 82786 can draw several graphics primitives
such as points, lines, arcs, circles, rectangles, polygons and characters. During the figure drawing process, the 82786 follows several programmable attributes.
The graphics attributes supported by the 82786 are:
color
depth (bits/pixel)
texture
logical operation
color bit mask
clipping rectangle
RESET AND INITIALIZATION
The state of BHE at trailing RESET determines synchronous vs. asynchronous operation. In Master
mode, synchronous/asynchronous operation affects
the sampling of the HLDA signal only. In Slave
mode, synchronous/asynchronous operation affects
the sampling of RD/WR signals. Synchronous operation is set if BHE is sensed HIGH at trailing RESET.
This enables direct connection of the 80286 BHE
pin in synchronous systems since it is driven HIGH
during RESET. The 80186 "tristates" its BHE during
RESET so a small static load on this line can select
asynchronous operation.
All internal registers are set to their default values on
reset. The first slave I/O write access to the 82786
will always be directed at the Internal Registers (ignoring the upper fifteen address bits). The Internal
Relocation Register must be programmed before
any other Internal registers can be accessed. The
DRAMIVRAM configuration registers must also be
programmed to conform to any specific environment.
The 82786 assumes an 8 bit external CPU interface
on reset. The graphics memory interface is always
16 bits wide. The BCP bit in the "BIU Control Register" must be set to 1 to enable a 16 bit external
interface. Interrupts are cleared on reset.
GRAPHICS PROCESSOR
Introduction
The Graphics Processor (Graphics Processor) is an
independent processor within the 82786. Its primary
task is to draw bitmap graphics. It executes commands residing in the memory, accessing the memory through the Bus Interface Unit (BIU). The Graphics Processor addresses 4 MB of linear memory (22
bit addresses).
Each graphics primitive can be drawn in anyone of
2,4,16 or 256 "Colors". The color details (bits/pixel
and exact color) are programmable. The "Texture"
controls the appearance of any line (or figure). The
texture pattern can be up to 16 bits long thus enabling drawing of solid, dashed, dotted, dot-dash
etc. types of lines. Each bit in the Texture corresponds to one pixel. The 82786 supports all sixteen
binary "Logical Operation" between a figure being
drawn in bitmap memory and the existing contents
of memory. It is thus possible to overlay a figure on a
background. The "Color Bit Mask" restricts the
drawing operation to only some "color planes". The
clipping rectangle restricts the drawing operation to
a specific area in the bitmap.
The pixel information is stored in the bitmap memory
in a packed pixel format. Different color bits for the
same pixel are stored in adjacent bit positions within
the same byte. Each byte represents 1, 2, 4 or 8
pixels (in one of 256, 16, 4 or 2 colors).
The Graphics Processor fetches its commands directly from a linked list Memory-resident Graphics
Processor Command Block (GCMB). The GCMB is
created and maintained by the CPU. The initial address for the GCMB is contained in a Graphics Processor Opcode Register in the 82786. Addresses for
subsequent (next) GCMBs are contained in the previous GCMBs. The Graphics Processor cah be
forced to stop by appropriate commands.
When the Graphics Processor is idle, it is said to be
in the "Poll State'~. This is the default mode after
reset. While in the Poll State, the Graphics Processor continuously monitors its internal "Opcode Register". A valid command in this register starts the
10-13
inter
82786
Graphics Processor. The first command placed in
the internal Opcode Register must always be a
Address
BASE
BASE
BASE
"LINK" command directing the Graphics Processor
to the main GCMB in memory.
Function
Register
+ 20h
+ 22h
+ 24h
I
GRO
OPCODE
GR1
Parameter 1
(Link Address Lower)
GR2
Parameter 2
(Link Address Upper)
GECL
Graphics Processor Internal Registers used in Poll State
Graphic Processor Command Format
Each command to the Graphics Processor consists
of an opcode, a Graphics End of Command List
(GECL) bit and a list of parameters as required by
the command. The opcode is 8-bits wide. The remaining 7-bits in the first word of the command must
be all zeroes to ensure future compatibility. Also,
whenever a parameter for the command is an address, 32-bits have been set aside but the 82786
uses only 22-bit addresses. The user must ensure
that the higher 10-bits in the address parameter are
always all zeroes All commands must lie at even
byte addresses.
The commands are placed (along with their parameters) sequentially in memory. Several GCMBs may
be linked together through a LINK command. All
commands have a standard format as described below:
o
8 7
15
OPCODE
10
0 0
0
0 0 01 GECL
Parameter 1
"
•
10
After fetching each command, the Graphics Processor checks the GECL bit. If the GECL bit is zero, the
command executes and the next command is then
fetched from the GCMB. If the GECL bit is set to
one, the Graphics Processor does not execute the
command and enters a POLL state.
Parameter n
etc.
Graphics Processor Status Register
One of the 82786 Internal Registers contains the Graphics Processor Status Byte. The bits in the Status Byte
are represented as:
Address
BASE + 26H
1. GPOLL - Poll State
Indicates if the Graphics Processor is in a POLL
state.
2. GRCD - Reserved Command
This bit is set if the Graphics Processor encounters an illegal opcode.
3. GINT - This bit is set as a result of the
INTR_GEN command.
4. GPSC - Pick Successful
This bit is set or cleared while the Graphics
Processor is in the PICK mode. The bit is set if
the pick operation resulted in success on "any
command.
5. GBCOV - bitmap Overflow for BitBlt or CharBlt
An attempt to execute a CHAR or a BitBlt command with any portion of the destination rectangle lying outside the clip rectangle causes this
bit to be set.
10-14
6. GBMOV - bitmap Overflow for Geometric Commands
An attempt to draw a pixel lying outside clip rectangle as a result of any geometric drawing
commands (LINE, CIRCLE etc.) causes this bit
to be set. The reason for separating these two
bits is the difference between the clipping operations for the two types of commands.
7. GCTP - Character Trap
This bit indicates that a character specified in
the character string as a parameter for the
CHAR command had its TRAP bit set.
8. GIBMD - Illegal Bit Map Definition
This bit is set if the DEF_BIT_MAP command
is executed with illegal parameters. The illegal
parameters are bits per pixel defined to be other
than 1, 2, 4 or 8, Xmax defined to be greater
than 32k-1, or the following equation not being
met: ((Xmax + 1) • Bpp) mod 16 = O.
infef
82786
All the status bits except GPOll are cleared upon
reset. The GPOll bit is set on reset.
Graphics Instruction Pointer
The Graphics Processor Instruction Pointer is a 22
bit quantity stored in two registers in the Graphics
processor. It points to the current command in the
GCMB.
Address
BASE
BASE
+ 28h
+ 2Ah
Register
Function
Character Font Storage
The character fonts are stored in memory. Starting
from an even address, the character information is
stored in consecutive words of memory forming a
character block. Each block can be of different
lengths for different characters. A character font is
selected by programming its base address into the
82786 through the DEF_CHAR_SET command.
The font could be established for 8 or 16 bit character codes. Each character block within a font has the
following format:
GCIPL
Instruction Pointer Lower
15
GCIPH
Instruction Pointer Upper
S
8
I WidthW
o
7
I T I HeightH
Dot Pattern for 1st row
Dot Pattern for 2nd row
Clipping Rectangle
The 82786 can be instructed to restrict drawing to .
certain portion of the bitmap only. This portion is
called the "Clipping Rectangle". The default clipping
rectangle is the entire bitmap. The clipping rectangle
must be redefined after a DEF_BIT_MAP command. For figures that are partially inside and partially outside the clipping rectangle, only the part inside
the clipping rectangle is updated in the bitmap. Character clipping is supported for word mode.
In order for the clipping to have predictable results,
there are some restrictions on the x,y coordinates of
each pixel. The rules to be observed are:
1. For lines, circles, polygons, polylines, BitBlts and
CharBlts, each pixel lying on the figure
(both the visible and the invisible parts) must not
have its x or y coordinate outside ± 32K range.
2. For circular arcs, the above restriction applies to
the circle of which the arc is a part.
3. If the top of characters are to be clipped, the top
row of pixels of the character must begin on an
even-numbered scan line (scan lines are numbered from.top to bottom beginning with number
0).
Pick Mode
The Graphics Processor can be put in "PICK Mode"
by executing the ENTER_PICK command. In the
PICK Mode, the Graphics Processor performs all
pixel computations for all drawing, BitBlt and Character commands. However, the bitmap memory is
not updated. Instead every computed pixel is compared against the clipping rectangle. If any computed pixel is found to lie within the clipping rectangle,
the GPSC bit in the Graphics Processor Status Register is set. Pick mode is not supported for circles
and arcs.
Dot Pattern for Hth row
s - Character Space bit
T - Trap Bit
Each character block must start at a word address
and the dot patterns for each line of the font must
reside in separate words. The height and width of
each character cannot be more than 16 pixels. In
case the width of a character is less than 16 pixels,
the dot pattern for each line must be stored as right
justified within the word.
Note that width and height of the character refer to
the difference between their limiting x and y coordinates respectively. Thus width = 0 specifies a character one pixel wide and a height = 0 specifies a
character one pixel high.
Graphics Processor Control and
Context Registers
All Control and Context Registers in the Graphics
Processor can be read from or written into, through
the Graphics Processor commands DUMP_REG
and lOAD_REG. Each register is identified by a 9bit Register Id.
These registers are not directly addressable like the
registers that are mapped into the 82786's On-ChipMemory (1/0) space, i.e., they are accessible only
through the DUMP_REG and the lOAD_REG
commands. The four user accessible graphics control registers are listed below.
10-15
REGISTER
NAME
REGISTER-ID
(# of bits)
GPOEM
GIMR
GSP
GCNT
0003 ( 6)
0004 ( 8)
010e (21)
0015 (16)
REGISTER
FUNCTION
Poll Mask
Interrupt Mask
Stack Pointer
Character Count while
drawing characters in
bitmap
inter
82786
The Graphics Processor also has Context Registers,
which are normally of no use to a user except in the
event of saving and restoring them during a CPU
context switch. Any other direct access to these registers must be avoided.
Name
10
Bits
Function
(16) Command
(2,2) Character Orientation and
Path'
GCHA
010B (21) Character Font Base
AddressGCA
0100 (21) Memory Address of Current
Position (X, Y)GBORG
010F (21) Bitmap Origin AddressGCX
0010 (16) Current X Position
0011
(16) Current Y Position
GCY
GPAT
0012 (16) Line Pattern
GSPAC
0013 (16) Spacing between Characters
and Bitblts
GN
0016 (16) Number of 16-Bit Words
Spanning Width of Bitmap
GVERS
0017 (16) Version Number'"
(D Step Value = 5)
TEMP
0019 (16) Temporary Storage
GXMAX
0090 (16) Maximum X for Clipping
Rectangle
GYMAX
0091 (16) Maximum Y for Clipping
Rectangle
GXMIN
0094 (16) Minimum X for Clipping
Rectangle'
GYMIN
0095 (16) Minimum Y for Clipping
Rectangle'
GMASK
0099 (16) Pixel Mask
009B (16) Background Color
GBGC
GFGC
009C (16) Foreground Color
(4) Function Code"
GFCOOE
009E
GCIP
01AC (21) Current Instruction PointerGBPP(RO) 009F
(4) Used with Dump Register
Command to Get Current Bits
per Pixel Value'"
GBPP(WO) 0008
(4) Used with Load Register
Command to Write Current
Bits per Pixel Value'"
GCOMM
GCHOR
0002
0007
NOTE:
The following information is not saved by saving
the state of these registers;
1) Type of character font, word, or byte.
2) Whether or not you are in pick mode.
3) Transparent or opaque drawing.
Graphics Processor Exception
Handling
The status bits GPOLL, GRCO, GINT, GPSC,
GSCOV, GSMOV, GCTP, and GISMO are capable of
generating an interrupt to the CPU depending upon
the Interrupt Mask Register (GIMR). If the corresponding bit in the GIMR is a "0" an interrupt is
generated. If another bit in the Graphics Processor
Status Register is set before an acknowledgement
for a previously generated interrupt, then another interrupt is not generated. Reading the Status Register and the SIU Control Register serves the purpose
of an Interrupt Acknowledge to the Graphics Processor. Reading the Graphics Processor Status Register clears the offending status bit(s) - bits not
masked out in the Interrupt Mask. If the interrupt is
generated due to the GPOLL bit, then this bit is not
cleared on an interrupt acknowledge. However this
does not generate repeated interrupts.
- 21-bit registers use 2 consecutive words.
'These bits are right justified in each byte of the word in
which they are stored. Two bits are stored in bits 1 and 0
and two bits are stored in bits 8 and 9; the remaining
upper bits in each byte are zeroed.
-"lnO-Step, valid after RESET and prior to drawing or drawing control commands.
'Correction to previous GXMIN 10 0096 and GYMIN 0097
assignments.
"GFCOOE 10 reassigned from 001 C to 009E in O-Step.
This code is read out inverted. The value read out must be
inverted in order to restore it properly.
'''New O-Step Bpp Registers.
The status bits GINT, GPSC, GSCOV, GSMOV,
GTRP and GISMO can also cause the Graphics
Processor to stop its normal instruction fetch/ execution and enter the POLL state. This is determined by
the contents of the POLL On Exception Mask register (GPOEM). The GPOEM is 6 bits wide. If the corresponding bit in the GPOEM is a "0", POLL state is
entered. On entering POLL state, the GECL bit in the
Opcode (GRO) register is automatically set. When
the Graphics processor is in POLL state, it can be
restarted by writing the appropriate opcode into the
Opcode register (GRO) and writing a zero into the
GECL bit. The act of clearing the GECL bit also
causes the status bits that caused the POLL state to
be cleared. Interrupt generation due to the GPOLL
bit is enabled on exit from the POLL state.
The status bit GRCO when set, always causes the
Graphics Processor to enter the Poll State. The Interrupt and the POLL mechanisms are two independent mechanisms. It is possible for the Graphics
Processor to issue an interrupt and not POLL, or to
issue an interrupt and POLL, or not to issue an interrupt and POLL or do none of them -' all depending
upon the GIMR and GPOEM Registers.
10-16
intJ
82786
Initialization And Software Abort
The ABORT signal causes the Graphics Processor
to enter POLL state after the execution of the currently executing command.
The two ways to initiate a software ABORT and
force the Graphics Processor to enter POLL state
are:
i) An attempt to write into the Graphics Processor
Status Register
ii) An attempt to write into the Graphics Current Instruction Pointer.
Upon RESET, the Graphics Processor immediately
enters a well defined state. The following events
take place:
1. Command execution is halted and the Graphics
Processor enters POLL state.
2. The GECL bit of the Opcode register (GRO) is set
to one to indicate an End of Command List.
3. All status bits except GPOLL are cleared. GPOLL
is set.
4. Interrupt Mask Register (GIMR) is set to all ones
(disabled).
5. Poll on Exception Mask register (GPOEM) is set
to all ones (disabled).
6. Graphics Processor exits pick mode.
The Graphics Processor command set is divided
into the following classes:
1.
2.
3.
4.
5.
Non-Drawing Commands
Drawing Control Commands
Geometric Commands
Bit Block Transfer (BitBlt) Commands
Character Block Transfer (CharBlt) Commands
List of Graphics Processor Commands
(Higher Byte· Hex)
Command
Opcode
Command
Opcode
LINK
NOP
DEF_TEXTURE_OPAQUE
DEF_ TEXTURE_TRANSPARENT
DEF_CHAR_SET_WORD
DEF_CHAR_SET_BYTE
INTR_GEN
CALL
RETURN
DEF_BIT_MAP
DUMP_REG
LOAD_REG
DEF_COLOR
DEF_LOGICALOP
ENTER_PICK
EXIT_PICK
DEF_CLIP_RECT
DEF_SPACE
DEF_CHAR_ORIENT
ABS_MOVE
RELMOVE
02
03
06
07
OA
OB
OE
OF
17
1A
29
34
3D
41
44
45
46
40
4E
4F
52
POINT
LINE
LlNE_OE
RECT
BIT_BLT
ARC_EXCLUSION
ARC_INCLUSION
POLYGON
POLYLINE
CIRCLE
CHAR_OPAQUE
CHAR_TRANSPARENT
CHAR_OPAQUE/REVERSE
CHAR_TRANSPARENT/REVERSE
BIT_BLT_M
INCR_POINT
HORILLINES
BIT_BLT_EO
BIT_BLT_ET
BIT_BLT_ERO
BIT_BLT_ERT
53
54
55
58
64
68
69
73
74
8E
A6
A7
A8
A9
AE
B4
BA
04
05
06
07
10-17
infef
82786
NON-DRAWING COMMANDS
NOP = No Operation
0300h
LINK = Link to Next Command
0200h
2900h
LOAD_REG = Load Register
3400h
CALL = Call Subroutine
OFOOh
=
Link Address High
I
~==O=E=O=O=h==:;-_ _ _ _ _----,-_ _ _ _ _ _, -_ _ _ _ _---,
INTR_GEN = Generate Interrupt
DUMP_REG = Dump Register
RETURN
Link Address Low
Return from Subroutine
I
IDump Address Low IDump Address High I
I Load Address Low I Load Address High I
Call Addr Low
Register 10
Register ID
Call Addr High
1700h
HALT = Enter Poll State
xx01 h
DRAWING CONTROL COMMANDS
DEF_BIT_MAP
=
DEF_CLIP _RECT
DEF_COLORS
=
Define bitmap
1AOOh
Define Clip
Rectangle
4600h
=
Define Colors
3DOOh
I
DEF_TEXTURE = Define Texture 0600/0700h
Opaque/Transparent
DEF_LOGICALOP = Define
Logic Operation
I Origin Addr Low I Origin Addr High I
xmin
ymin
Xmax
Ymax
xmax
ymax
Bits/pixel
IForeground Color IBackground Color I
I
. 4100h
Pattern
Color Bit Mask
Function Code
(see table below)
The functions performed and their codes are:
FCODE
0000
0001
0010
0011
0100
0101
0110
0111
FUNCTION
FCODE
FUNCTION
1000
1001
1010
1011
1100
1101
1110
1111
CMP (source) AND CMP (dest)
CMP (source) XOR dest
CMP (source)
CMP (source) OR dest
CMP (dest)
source OR CMP (dest)
CMP (source) OR CMP (dest)
0
source AND dest
CMP (source) AND dest
dest
source AND CMP(dest)
source
source XOR dest
source OR dest
DEF_CHAR_SET = Define Character Set
(Word/Byte mode)
DEF_CHAR_ORIENT = Define Char Orientation
I
1
OAOO/OBOOh
Font Addr Low
4000h
Path /Rotation
10-18
Font Addr High
I
inter
82786
There are four defined values for both the path and rotation. They are:
DEF_SPACE
=
Define Inter Char and
Bit Bit GCX Update Space
CODE
INCREMENT
00
01
10
11
o degrees
90 degrees
180 degrees
270 degrees
4DOOh
Space
ABS_MOV
=
Move
4FOOh
x coordinate
y coordinate
RELMOV
=
Relative Move
5200h
dx
dy
ENTER_PICK
=
Enter Pick Mode
4400h
4500h
EXIT_PICK = Exit Pick Mode
GEOMETRIC COMMANDS
POINT
=
Draw Point
INCR_POINT
=
Draw Incremental Points
5300h
dx
dy
B400h
Array Addr Low
Array Addr High
N (# of pts)
INCREMENTAL POINTS ARRAY
INC3
INC4
INC2
-
-
-
-
INCN
INCN-1
INC1
INCN-2
The largest allowable single array of incremental
points is 32K points. The upper two bits of the "inc"
field specify the increment for the x coordinate while
the lower two bits specify the increment for the y
coordinate, The encoding for the two bits is as follows:
CODE
INCREMENT
00
01
10
11
0
+1
-1
Unused
NOTE:
Transparent mode is not supported with the INCR_POINT
command if the texture is non-solid.
5400/5500h
dx
CIRCLE = Draw Circle
BEOOh
radius
RECT = Draw Rectangle
5BOOh
dx
dy
POLYLINE = Draw Polyline
7400h
Array Addr Low
Array Addr High
N (# of lines)
POLYGON
7300h
Array Addr Low
Array Addr High
N (# of lines)
LINE
=
Draw Line (With End Point!
without End Point)
=
Draw Polygon
10-19
dy
intJ
82786
POL YLiNE/POLYGON ARRAY
HORIZONTAL LINE ARRAY
dx1
dy1
dxy
dyl
deltaX1
dxN
dyN
dxN
dyn
deltaXN
ARC = Draw Arc
(Exclusion/Inclusion)
6800/6900h
dxmin
dymin
I·
dxmax
1 dymax 1 radius 1
SCAN_LlNES= Draw Series of 1 BAOO/BA01 h 1 Array Addr Low 1 Array Addr High 1 N (# of lines) 1
Horizontal Lines
NOTE:
Transparent mode is not supported with the circle and arc commands if the texture is non-solid.
BITBLT COMMANDS
BIT_BL T = Bit Block Transfer
within bitmap
1
6400h
I Source x coord I Source y coord I
AEOOh
ISource Addr LowlSource Addr Highl
BIT_BL T_M = Bit Block Transfer 1
across bitmaps
I Source Ymax I Source x coord I Source y coord I
BIT_BL T_E = Bit Block Transfer
across bitmaps
(opaque,
transparent,
opaque/reverse,
transparent!
reverse)
1 Source Ymax I Source x coord I Source y coord I
CHAR = Draw Character String
(opaque, transparent,
opaque/reverse,
transparent! reverse)
I
A600/ A700/
ABOO/A900h
dx
Mode
char1
char2
char2
char4
char1
char3
charN
charN
charN-1
String Ptr Low
I
dy
I
SourceXmax
dx
String Ptr High
I
I
I
I
I
I
dy
N( # of char)
I
I
DISPLAY PROCESSOR
CHARACTER STRING FORMAT
Byte
I
dy
I
SourceXmax
I 0400/0500/ Isource Addr Lowlsource Addr Hi9hl
0600/0700h
CHARBLT COMMANDS
Word Mode
dx
.-~---.-------.
NOTE:
In byte mode, the character code of the first character to be drawn
must reside at an even address.
Introduction
The Display Processor (Display Processor) is an independent processor responsible for controlling the
display of video data on a CRT, laser printer and
other display devices. Its functions include the generation of horizontal and vertical timing signals,
blanking signal and the control of 8 Video Data output pins.
10-20
intJ
82786
The 82786 can function in two distinct types of
graphics memory environments - i) using single port
DRAMs (normal display mode) and ii) using dual port
video DRAMs (VRAM mode). When the 82786 is
configured to interface with single port DRAMs, the
Display Processor uses the BIU to fetch the screen
parameters and display data from memory. The Display Processor then internally shifts the video data
into the video stream for screen refresh. When configured to run with VRAMs, the Display Processor
uses the BIU to load the shift registers in the VRAMs
at the beginning of every scan line. The screen refresh is then done by the second port of the VRAMs.
The BIU and Graphics Processor have the rest of
the scan line time to access the graphics memory.
Video Rates (Normal Display Mode)
The Display Processor is clocked from an external
Video Clock. In this mode, the 82786 fetches video
data from memory into an internal FIFO. An internal
shift register then generates the serial video data
stream to the display. The 82786 will support CRT
screens of up to about 640 x 480 pixels at 8 bits/pixel and 60 Hz non-interlaced, or about 1024 x 640 x 8
at 60 Hz interlaced. The Display Processor supports
Interlaced, non-interlaced and interlace-sync displays.
The Display Processor also has higher speed modes
which enable the user to trade off bits/pixel for dotrate. Thus it is possible to run at a maximum of 8 bpp
with a 25 MHz dot-rate, 4 bpp at a 50 MHz dot-rate,
2 bpp at a 100 MHz dot-rate or 1 bpp at 200 MHz
dot-rate; with corresponding increase in size and
resolution. Note that in the high speed modes, horizontal window and cursor placement resolution is reduced to 2, 4 or 8 pixel resolution at 50 MHz, 100
MHz, or 200 MHz rates respectively.
Bitmap Organization
The Display Processor is optimized to display data in
packed bitmap form. The Graphics Processor writes
pixel data in the memory in this form. The Display
Processor supports display of 1, 2, 4 or 8 bits/pixel
data, stored in sequential bitmap form, with the first
(left-hand) pixel to be displayed occupying the Most
Significant Bit(s) of a word in memory, and subsequent pixels occupying sequentially lower bits in the
word. Ascending word addresses represent subsequent pixels, moving left to rig!1t and top to bottom
on the screen.
Windows and Normal Display Mode
In the normal display mode, Windows may be displayed on the screen in a flexible format. There can
be up to 16 window segments or tiles appearing on
any single display line. There is no limit on the number of windows vertically (limited by the number of
scan lines in the active display area). At the basic
Video rate (25 MHz, 8 bpp), these windows may be
placed at pixel resolution on the screen, and
mapped at pixel resolution into the bitmap. Windows
can be made to overlap, by breaking the windows
into tiles and assembling the tiles on the screen.
Cursor (Normal Display Mode)
The Display Processor supports a single hardware
cursor which may be 8 x 8 pixels or 16 x 16 pixels.
This cursor may be positioned anywhere on the
screen with a pixel resolution. The cursor may be
defined to be transparent or opaque, and may be
either a block cursor with its hot-spot at the top-left
of the cursor pattern, or a cross-hair cursor one pixel
across, stretching the width and height of the screen
with its hot-spot at the center of the cross. The cursor color and pattern (shape) are programmable.
The cursor may be programmed off if not required,
or to implement a blinking cursor.
VRAM Mode
In the VRAM mode, the first tile for every scan line is
used to load the shift register in the VRAMs by executing a data transfer cycle. Subsequent tiles (if any)
for all strips will still be available through the VDATA
pins of the 82786. The window status bits can be
used to internally multiplex the VRAM video stream
and the 82786 generated video stream. The address
for this data transfer cycle is determined from the
Tile Descriptor. The 82786 BEN# pin is used as a
DT pin for this case. If the graphics memory banks
are interleaved, then both banks are loaded in the
transfer cycle. During the Blank period, Default VData appears on the VDATA pins.
CRT Controller
CRT timing signals HSYNC, VSYNC, and BLANK
are each programmable at a pixel resolution, giving
a maximum display size of 4096 x 4096 pixels. If
High Speed, Very High Speed, or Super High Speed
display modes are selected, the horizontal resolution
of the CRT timing signals becomes 2 pixels, 4 pixels
or 8 pixels at 50 MHz, 100 MHz and 200 MHz respectively.
Window Status
The HSync and VSync CRT timing pins may be configured to serve as Window Status output pins,
which can be programmed to present a predefined
code while the Display Processor is displaying a tile.
This code is programmable as part of the Tile De-
10-21
82786
scriptor, and may be used externally to multiplex in
video data from another source, or select a pallette
range for a particular window, etc. External logic
must be used to enable VSync and HSync as CRT
timing signals when Blank is high, and as encoded
Window Status signals when Blank is low. This is
valid in both DRAM and VRAM modes.
Zoom Support
The Display Processor allows windows to be
zoomed in the normal display mode. The zoom factor is an integer between 1 and 64. There are independent zoom factors for the x and y direction. The
zoom function results in pixel replication.
All zoomed windows on a display are zoomed by the
same amount. A window is therefore either zoomed
or not zoomed. Zoom offset is not supported-a pixel must either be fully displayed or not displayed at
all. This places a restriction on window placementa window may not be placed such that a zoomed
pixel is partially obscured. VRAM displays can be
zoomed vertically by using this feature. Horizontal
zooming of VRAM windows requires external hardware support.
Only even zoom factors are supported in the Y direction with interlaced displays. In addition, when
zooming, both descriptor lists (interlaced" systems
use two descriptor lists, one for each frame) must
point to the same place in memory, i.e., they must be
identical list.
Extended 82786 Systems
The CRT timing signal pins may be configured as
output pins (for the normal stand-alone 82786 system), or as input pins for a system in which multiple
82786's are ganged in parallel to provide a greater
number of bits/pixel, higher dot rates, larger display
area, or more windows. In multiple 82786 systems,
each of the Display Processors run in lock step, allowing the individual outputs to be combined on a
single display. The HSync, VSync and Blank pins for
the "Slave" 82786 are configured as inputs and are
driven by the "Master" 82786.
Memory Bandwidth Requirements
The memory bandwidth required by the Display
Processor depends on the display size and mode of
operation. The 82786 has a 40 Mbyte/sec maximum
bandwidth during fast block accesses to graphics
memory. In the normal display mode the Display
Processor makes use of these fast block reads for
screen refresh, thereby minimizing its use of the
memory bus, which the other 82786 modules share.
For worst-case displays, when the Display Processor is running at its maximum speed of 25 MHz and
8 bits/pixel, about 50% of the memory bandwidth is
used for display refresh. Correspondingly, at only 1
bit/pixel the Display Processor's bus requirements
are reduced to about one-eighth of its requirement
at 8 bpp. In the VRAM mode, the Display Processor
does not fetch any of the display data. The display
data is passed directly from the graphics memory to
the pixel logic. In this case about 1% of the graphics
memory bandwidth is required by the Display Processor to fetch the Strip Descriptors.
Display Processor Registers
There are two different register sets for the Display
Processor. Six of the 82786 Internal Registers are
dedicated to the Display Processor. These registers
are memory (or I/O) mapped in the external CPU
address space. They can therefore be directly accessed by the external CPU. Another set of registers
is totally local to the Display Processor. These are
the display control registers and are used for display
parameters.
82786 Registers For Display Processor
There are six of these Registers. They are listed below:
Address
External Video Source
The HSync and VSync pins on the 82786 can be
configured as inputs to synchronize the 82786 to external video sources (VCR, broadcast TV etc.). In
this case, the Blank pin is configured as output and
the active 82786 display period is determined by the
programmed 82786 parameters.
+ 40
Base
Base
+ 42
+ 44
+ 46
+ 48
Display Processor Status
Base
+ 4A
Default Video
Base
Base
"When programmed as inputs, VSync and HSync still
serve as outputs for Window Status while Blank is
inactive.
Function
Base
Display Processor Opcode
Param1
Param2
Param3
The Display Processor Opcode and the three parameter registers are used to send a command to
the Display Processor. The Display Processor Status
Register contains the status for the Display Processor. This is described in more detail later. The Default Video Register contains the data that appears
10-22
82786
on the Video Out pins during the blanking intervals.
The CPU can use this register to address an external pallette RAM while loading the pallette, thereby
eliminating a separate address path and external
logic.
sor Position registers). The register 10 must be an
even number for this command.
LOAD ALL (LD-ALL):
o
0
0
0
0
1 0 1 0 0 0 0
Mem Address lower
Mem Addr Upper
Display Control Registers
The display control registers can be loaded under
control of the Display Processor during the Vertical
Blanking interval. This synchronizes parameter updates with display refresh and ensures that the display remains clean, with no updates occurring during
data display.
The Display Processor may also be programmed to
provide a Frame Interrupt once per certain number
of frames. This may be used to facilitate blinking,
scrolling, panning, animation or other periodic functions.
This command loads the entire block of display control registers in a block read starting from the Memory Address given in the command. The Memory Address must be an even byte address. This command
must be the first command executed and has to be
executed after reset to enable the display operation.
The registers are listed below.
DUMP (DMP-REG):
o
I
I
0
I
0
I
0
I
0
Command Execution
At the beginning of each Vertical Blanking time, the
Display Processor checks the ECl bit in the Display
Processor Opcode Register. If the ECl bit is 1, the
Display Processor status remains unchanged. If the
ECl bit is 0, the Display Processor executes the
command. Only one command is executed per
frame.
On completion of the command, the Display Processor sets its ECl bit back to 1, indicating to the CPU
that a new command may be written into the Command Register. This handshake prevents the CPU
from writing a new command before the old one has
finished executing. The commands for the Display
Processor are:
1. load Register
2. load All Registers
3. Dump Register
4. Dump All Registers
The command formats are:
0
0
0
0
1 0 0 0 0 0 0
Memory Address lower
Mem Addr Upper
Register 10
I
I
I
II
1 1 0 0 0 0 0
Memory Address lower
Mem Addr Upper
Register 10
0 WP lP Eel
This command causes the Display Processor to
write the contents of the display control register pair
specified by Register 10 to the location in memory
specified by Memory Address. The Memory Address
must be an even byte address. The register 10 must
be an even number for this command.
DUMP All (DMP-ALl):
o
0
0
0
0
1 1 1 0 0 0 0
Mem Address lower
Mem Addr Upper
0 WP lP Eel
This command causes the Display Processor to
write its entire display control register block out to a
block in memory, starting at the Memory Address
specified. The Memory Address must be an even
byte address. The write occurs as a series of single
write cycles.
For any of the Display Processor's four commands,
setting the lP bit to 1 will cause that command to
execute at the start of each VSYNC period. While in
loop Mode, the DP does not set the ECl bit back to
1 at the end of each execution. Exit loop Mode by
writing 0 to the lP bit.
LOAD REGISTER (lD-REG):
o
0 WP lP Eel
0 WP lP Eel
This command loads a pair of display control registers with values stored in memory starting at the location given by Memory Address. The Memory Address must be an even byte address. The Register
10 for the register pair is given in the register block
description below. This command may be used to
update individual pairs of registers (such as the Cur-
The Write Protect bit (WP, bit 2 of the DP opcode
register) allows the user to write protect the CRT
Timing parameter registers (Display Control Register
Block registers 06h-ODh). Write protect is not enabled until after the firstDP command has executed.
This must be a lOAD ALL. Before changing the WP
bit, the user should exit loop Mode and wait for the
ECl bit to return to 1.
10-23
inter
82786
Display Control Register Block
The display control register block is shown below. Each register is 16-bits wide. The numbers in parentheses
are the number of bits per parameter.
15 14 13 12 11 10
9
OOh
VStat:
01h
02h
03h
04h
05h CRTMode:
B
7
6
5
4
3
2
1
0
C
D C- CsrOn(1); D- DspOn(1)
IntMsk
ITripPt
Frint-1
Reserved
AA
IL - Interlace(2): 00 ~ Non-Interlace
01 ~ Reserved
10 ~ Interlace
11 ~ Interlace-Sync
W - Window Status Enable(1)
S - HSYNC, VSYNC Slave Mode(1)
B - Blank Slave Enable(1)
AA - Accelerated Video (High Speed Video, etc.)(2)
00 ~ Normal (25 MHz)
01 ~ High Speed (50 MHz)
10 ~ Very High Speed (100 MHz)
11 ~ Super High Speed (200 MHz)
15 14 13 12 11 10
06h
07h
OBh
09h
OAh
OSh
OCh
ODh
OEh
OFh
10h
11h
12h
13h
14h
15h
16h
17h
9
B
7
6
5
4
3
2
HSynStp-3
HFldStrt-3
HFldStp-3
LineLen-3
VSynStp-1
VFldStrt-1
VFldStp-1
FramLen-1
Descriptor Addr. Pointer (L)
Descriptor Addr. Pointer (U)
Reserved
XZoom-1
YZoom-1
FldColor
BdrColor
1Bpp Pad
2Spp Pad
4Bpp Pad
CsrMode: SIXITI CSt
CsrPad
CSC
1 1-
CsrStyle: S - CsrSize(1): 0 ~ B x B Csr
1 ~ 16x16Csr
X - CsrX-Hair(1)
T - CsrTransparent(1)
CSt - CursorStatus (to Window Status output)(2)
CSC - CursorStatusControl(2): 00 ~ Current Window Status
01 ~ Foreground
10 ~ Background
11 ~ Block
10-24
o
82786
15 14 13 12 11 10
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
I
9
876
5
4
3
2
o
CsrPos X-2
CsrPos Y-1
GsrPatO
GsrPat1
GsrPat2
CsrPat3
CsrPat4
CsrPat5
GsrPat6
CsrPat7
CsrPat8
CsrPat9
CsrPatA
CsrPatB
GsrPatG
CsrPatD
CsrPatE
CsrPatF
The functions of the preceding registers are described in more detail below:
o. VStatGsrOn(1) DspOn(1)
If set, the internally generated display or cursor
are turned on.
1.lntMsk
Interrupt Mask Register. This register enables an
82786 interrupt whenever the corresponding bit
in the Display Processor Status Register is set. A
o for any bit enables the interrupt. This Interrupt
Mask is different from the Interrupt Mask for the
Graphics Processor. If using interrupts, mask bit
5 of this register.
2. TripPt
The Trip Point register is a reserved field and
must be programmed to OOh.
3. Frint
Frame Interrupt Register. Enter the number of
frames minus one elapsed between successive
setting of the FRINT bit in the Display Processor
Status Register.
4. Reserved field should always be set to zero.
5. GRTMode -IL(2) W(1) S(1) B(1) M(2)
These bits control the various modes of the CRT
Controller.
IL are the Interlace Control bits-if IL is 00, the
display is Non-Interlaced. If IL is 10, the display
is Interlaced (displaying the even lines (Field 1)
of the frame and then the odd lines (Field 2». If
IL is 11, the display is interlace-sync (similar to
interlace, except that the odd field display is
identical to the even field display).
W is the Window Status Enable bit. If W is 0,
HSYNG and VSYNC will have normal operation.
If W is 1, the Window Status Gode programmed
into the Tile Descriptors will be output on VSYNC
and HSYNC pins while display data for that particular window is being displayed. VSYNC represents the MSB and HSYNC the LSB of the Window Status Code.
S is the HSYNGIVSYNC Slave Mode bit. If S is
0, the VSYNC and HSYNC pins are outputs. If S
is 1, they are inputs. In the Slave Mode, if Window Status is enabled, HSYNG and VSYNG will
still be outputs while BLANK is low.
B is the Blank Slave Mode bit. If B is 0, the
BLANK pin is an output. If B is 1, it is an input.
NOTE:
Always program the slave 82786 first, then the
master. The slave VSYNC, HSYNC, and BLANK
pins must be held high until they are programmed.
AA are the Accelerated Video Mode bits. By using
an external latch or shift register, 50, 100 or 200
MHz video. data rates can be generated. In the Accelerated Video Modes, each memory byte represents 2, 4 or 8 physical pixels. The upper bit(s) of
each byte represent the pixels that appear on the
left on the display medium. Used in DRAM display
mode. Must be programmed to zero for the first tile
in the VRAM Mode.
10-25
6. HSynStp
Enter the HSYNC width in number of VClks minus 3. (For a graphical representation of all the
CRT timing signals, see Figure 3).
inter
82786
7. HFldStrt
Enter the number of VClks minus 3 between the
rising edge of HSYNC and the falling edge of
BLANK (the start of Video Data).
8. HFldStp
Enter the number of VClks minus 3 between the
rising edge of HSYNC and the rising edge of the
next BLANK (the end of Video Data).
9. LineLen
Enter the number of VClks minus 3 between the
rising edge of HSYNC and the rising edge of the
next HSYNC.
10. VSynStp
The number of Horizontal Synchronizations
(HSYNCs) between the beginning of Vertical
Synchronization (VSYNC) and the end of
VSYNC.
Enter VSYNC width as the number of HSYNC
periods minus one. In the non-interlaced mode,
VSYNC rises and falls on the rising edge of
HSYNC. In interlaced and interlace-sync mode,
VSYNC has the same timing as in non-interlace
mode at the start of each Even Field (lines 0, 2,
4, etc), but is delayed by half Line Len at the start
of each Odd Field (lines 1, 3, 5, etc). (See Figure
3.)
11. VFldStrt
Enter the number of HSYNCs minus one between the beginning of VSYNC and the end of
Vertical Blanking.
12. VFldStp
Enter the number of HSYNCs minus one between the beginning of VSYNC and the beginning of the next Vertical Blanking.
13. FramLen
Enter the number of HSYNCs minus one between the beginning of VSYNC and the beginning of the next VSYNC.
14. Descriptor Address Pointer (L)
The address of the first Strip Descriptor for the
display. After fetching the first descriptor the Display Processor uses the Link Address in the descriptor to fetch the next descriptor. The Descriptor address must be an even byte address.
15. Descriptor Address Pointer (U)
The most significant bits of the Descriptor Address Pointer.
16. Reserved field should always be set to zero.
17. ZoomX, ZoomY
Enter the x-zoom factor minus one and y-zoom
factor minus one for the zoomed windows. The
zoom factor can be any integer number between
1 and 64. In the VRAM mode, ZoomX is not
used unless additional logic is added.
18. Field Color
An 8-bit value indicating the color of the background field to be displayed in the absence of
windows.
19. Border Color
An a-bit value indicating the color of the border
to be displayed inside selected windows.
20. 1Bpp Pad
An a-bit value where the upper 7 bits represent
the upper 7 bits of video data concatenated to
the 1 bit video data from a 1 bit/pixel bitmap.
21. 2Bpp Pad
An a-bit value where the upper 6 bits represent
the upper 6 bits of video data concatenated to
the 2 bit video data from a 2 bit/pixel bitmap.
22. 4Bpp Pad
An a-bit value where the upper 4 bits represent
the upper 4 bits of video data concatenated to
the 4 bit video data from a 4 bit/pixel bitmap.
23. CsrStyle:S(1) X(1) T(1) CSt(2) CSC(2) CsrPad
The Cursor Mode Register. The Cursor Pad is an
8-bit value where the upper 7 bits are the higher
7 bits for the cursor color.
Cursor Style: S is the size bit. If S is 0 an 8 x a
pixel cursor will be displayed. If S is 1, a 16 x 16
pixel cursor will be displayed.
X is the CrossHair Mode bit. If X is 0, a block
cursor will be displayed. The pattern for the cursor is specified in the Cursor Pattern registers.
The cursor hot-spot is at the top-left of the cursor block. If X is 1, a cross hair. cursor will be
displayed. Its hot-spot is at the center of the
cross, and it will stretch the full height and width
of the display.
T is the Transparent Mode bit. If T is 0, the cursor is opaque. Its forground color is determined
by the concatenation of the cursor padding bits
(7 MSB's) with 1. The background color is determined by the concatenation of the cursor padding bits with 0. If T is 1, the cursor background
reverts to whatever bitmap data is. being displayed "behind" the cursor.
CSt is the Cursor Status. The code to be output
onto the Window Status outputs while the Cursor
is being displayed.
.
10-26
inter
82786
CSC is the Cursor Status Control (2 bits). The
cursor status may be output whenever the cursor foreground color is being output, whenever
the cursor background color is being output, or
whenever the cursor block is active, whether it is
displaying background color or foreground color
or transparent pixels (useful for inverse video),
or else the cursor status may default to the current Window Status. The code is shown in the
Display Control Register Block.
25. CsrPos Y
This is the Cursor Y-Position Register-the position of the cursor hot-spot relative to the beginning of the frame (the beginning of the previous
VSYNC). Enter the value minus one.
26. CsrPatO:F
These 16 registers contain the pattern to be displayed as a cursor. CsrPatO is the top row of the
cursor, and the MSB is the left bit of the cursor.
For an 8 x 8 cursor, the cursor pattern used is
the higher byte of the first eight cursor registers.
CsrPad: Cursor padding bits.
24. CsrPos X
This is the Cursor X-Position Register-the position of the cursor hot-spot relative to the beginning of the line (the rising edge of the previous
HSYNC). Enter the value minus 2.
(HSYNCSTRT)
I
HSYNCSTP
HFLDSTRT
HFLDSTP
I
I
L1NELEN
I
:.--....:..1- - . - : . . - - - - - - - - - - - - ' - - - - - 11
(VSYNCST,RT)
HSYNC~
BLANK
(HORIZ)
-
VSYNSTP
; - - - - - - - - - - - - - ; - - - - VFLDSTRT
ACTIVE DISPLAY
PERIOD
- VFLDSTP
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1_ FRAME LEN
231676-3
Figure 3. Timing Parameters
NOTE: In slave video mode, at least a 1-line vertical front porch and a 7-line vertical back porch are required.
Windows
The CPU creates Strip Descriptors in memory that
describe windows for the Display Processor. The
Strip Descriptors are organized as one Descriptor
per strip of window segments (tiles) as shown in Figure 4. Each Descriptor contains information for the
tiles within that strip in the order they are displayed
on the screen (left to right). The Descriptor for a
particular strip must be contiguous in memory. The
Strip Descriptors for several strips are linked to each
other in the order they are displayed (top to bottom).
The linking is done through the Link to Next Strip
Descriptor parameters in each Descriptor, which
points to the following Descriptor. The Descriptor for
the first strip is accessed during the VBlank interval,
using an address specified by the Descriptor Address Pointer, one of the Display Control Register
pairs.
The Strip Descriptor consists of a header followed
by one or more Tile Descriptors. The header and
Tile Descriptors must occupy one contiguous block
in memory.
10-27
intJ
82786
The format of the Window Strip Descriptors is:
15
14
13
12
11
Header
C
1st Tile Descr.
T
B
L
R
L
R
I
7
6
5
4
3
2
Z
PC
Bitmap Width
Mem Start Address (L)
Mem Start Address (U)
Bpp
I
StartBit
Fetch Count (bytes - 2)
I
I
WSt
0
Stop Bit
I
WSt
I
B
8
Number of Lines in Strip-1
Link to Next Strip Descr. (L)
Link to Next Strip Descr. (U)
Number of Tiles in Strip-1
Bitmap Width
Mem Start Address (L)
Mem Start Address (U)
Bpp
I
StartBit
Fetch Count (bytes - 2)
2nd Tile Descr.
T
9
10
I
I
F
Stop Bit
PC
IZ IF
etc ...
NOTE:
The first tile of any scan line must be greater than 1 pixel.
STRIP 1
TILE 1
STRIP 2
TILE 1
STRIP 3
TILE 1
-- --
-
STRIP 4
TILE 3.3
TILE 2
1
TILE 2
TILE 1
-- -STRIPS
TILE 3
TILE 2
TILE 4
-TILE 3
TILE 1
231676-26
Figure 4. Display Shows Strips and Tiles with Two Overlapping Windows
The Strip Descriptor Header is programmed with values for the number of display lines minus one and
the number of tiles in the strip minus one. There may
be any number of lines in a strip, up to the number of
lines on the display (within their restrictions imposed
by zoom, if used). The first VRAM strip must be at
least 2 lines. In DRAM mode there may be up to 16
tiles within a single strip. In" the VRAM Mode the first
tile is used to load the VRAM shift register, leaving
up to 15 tiles to be used by the Display Processor.
The header also contains Link to Nex1 Strip Descriptor parameters.
NOTE:
You must only define in the strip descriptors the
number of scan lines that will actually be displayed.
10-28
intJ
82786
The C bit (the most significant bit) in the Number of
Tiles in Strip parameter tells the DP to color the display area following the current strip with FldColor
data or link to the next strip. If the C bit is set to one,
the DP colors the remainder of the display with the
background color defined in the FldColor Register of
the Display Control Register Block. If the C bit is
zero, the DP links to the next strip.
Each Tile Descriptor contains the following parameters:
1. Bitmap Width-the width of the bitmap in bytes.
This must be an even byte address. Bitmap Width
is added to the Memory Address for each scan
line in the window (each HSync period within the
strip) to get the start address of the next display
line (if y-zoom inactive or counted out). In case of
interlaced displays, the Memory Address is incremented by twice the bitmap width. In the VRAM
Mode, the bitmap width of the first tile must be a
power of 2 and must be less than the maximum
width of the VRAM shift register.
2. Memory Start Address-the memory address for
the window. This is an even byte address, corresponding to the address of the first word of bitmap data for the window tile (top left corner). In
the VRAM mode the start address for the first tile
must guarantee that the entire scan line is contained in a single row of the VRAM.
3. Bpp-The number of bits/pixel in the current window-must be programmed to .1, 2, 4, or 8 in the
normal mode. In the VRAM mode this field should
be zero.
4. StartBit-The bit position in the corresponding
memory word for the first bit of the first pixel in the
window. Gives bit resolution to the Memory Start
Address (and pixel resolution to the start of the
window). In the normal mode this must be programmed to be consistent with the Bpp defined
for that window. In the VRAM mode, this must be
programmed to zero for the first tile.
5. StopBit-The bit position in the corresponding
memory word for the last bit of the last pixel in the
widow. Gives bit resolution to the window width. In
the normal mode this must be programmed to be
consistent with the Bpp defined for that window.
An illegal value will result in incorrect display. In
VRAM mode, this must be programmed to zero
for the first tile.
6. Fetch Count-In the DRAM mode, this specifies
the number of bytes minus two from the bitmap to
be fetched for each scan line in the current window tile. This must be an even quantity. The value
programmed in this field is 2 less than the number
of bytes to be fetched rounded off to the next
higher even number. In the VRAM mode, this
must be programmed to zero for the first tile.
7. TBLR-Border Control Bits-When a bit is set to
one, it turns on the border on Top, Bottom, Left or
Right of window tile. This is a four bit field with
one bit controlling each border. The most significant bit controls the top border and the least significant bit controls the right border. All four bits
must be programmed to zero for the first tile in
VRAM Mode.
8. WST-Window Status (2 bits)-The code to be
presented on the Window Status pins while the
window is being displayed.
9. PC-IBM PC Mode-Indicates that this window is
being displayed from a bitmap created in IBM PC
format. The Display Processor supports the IBM
Color Graphics Adapter bitmap format in which
the least significant byte of a word appears on the
left of the most significant byte on the screen as
opposed to the 82786 format in which the least
significant byte appears to the right of the most
significant byte. Also, the 2-bank and 4-bank bank
oriented bitmaps used in the PC and PCjr systems
are supported. These modes enable bitmaps created by IBM PC or PCjr (or compatible) systems to
be upward compatible with 82786 displays, with
the PC format bitmaps being displayed either as
the whole screen, or as windows on a screen together with 82786 created bitmaps. The PC mode
bitmaps can be zoomed or used with interlaced or
accelerated displays. In the VRAM mode, this
field must be programmed to zero for the first tile.
Note that although the Display Processor can display bitmaps created in these formats, the Graphics Processor always draws bitmaps in 82786 format. The vertical mapping of IBM format bitmaps
is restricted in that the Memory Start Address of
an IBM format window must be in the first of the 2
or 4 banks.
The coding for IBM PC mode is given below:
00
01
10
11
~
~
~
~
82786 Mode
Swapped Byte Mode
Swapped Byte, 2 banks'
Swapped Byte, 4 banks'
'Not supported in Interlaced mode.
Bitmap formats in 82786 and PC Modes are shown
below:
Pixel # (from left as displayed on screen):
o1 234 567S9101112131415
MOSd2::~ #H1++++019IsI71615141312111 01
10-29
p~~~de 171615141312111 OH1++++019I sl
inter
82786
ister. The format of the Display Processor Status
Register is:
ADDRESS
7
6
5
4
3
2
1
0
10. Z-Zoom-This bit if set, indicates that in the
normal display mode the window is to be
zoomed using. the zoom parameters programmed into the ZoomX and ZoomY registers.
11. F-Field-This bit if set, indicates that the window tile is background field. In the normal mode
the field color is displayed for the window. The
number of pixels of Field to be displayed should
be programmed into what would normally be the
Bpp, StartBit, StopBit fields. This bit must be set
to zero for a the first, tile in the VRAM mode.
BASE
+ 48 hL!F_R..L.I!R_C_DL!--L!F_M_T!LB_LK.,L!E_V...JN!L-0_DD..L.!E_C....JL!
Display Processor Status Register
The functions of each bit, and the action taken in the
case of exceptions is described below:
FRI-Frame Interrupt. This bit is set every n frames,
where n is a value between 1 and 256 loaded into
the Frint Register. This may be used, for example,
for timing in animation applications, or to time blink
rates.
If the Strip Descriptor list causes a window to be
displayed that extends beyond the active display
area, then only the upper left hand portion of the
window is displayed and the rest of it is truncated.
RCD-Reserved Command. This bit is set if the Display Processor does not recognize the Opcode it
has been instructed to execute. The Display Processor will not execute the command.
In interlace mode, in order to maintain a line resolution on vertical positioning of windows, a doublelength Descriptor Table must be used. The first part
contains window position information for the even
lines, the second part for the odd lines. Also note
that in interlace mode, one frame takes two fields to
display. Command execution occurs at frame
boundaries, not field boundaries, so the instruction
execution frequency will typically be 25/30 Hz instead of the non-interlaced 50/60 Hz.
Reserved
Initialization
The Display Processor is reset during the main
82786 reset process. Upon reset it enters a well defined reset state described below:
1. Any command execution is immediately halted.
2. Parameter, Descriptor, or Display Data fetches
are terminated.
3. Display Outputs VDATA7:0 are all reset to default
video.
4. HSync, VSync, Blank are tristated (Display Processor defaults to Slave Operation). These stay tristated until the first lOADJll instruction.
5. Display Processor Status Register is cleared.
6. Display Processor Interrupt Mask to set to all 1 's
(all interrupts disabled).
7. ECl bit is set to 1.
Display Processor Interrupts, Status
Register and Exception Handling
The Display Processor Status Register is an 8-bit
memory (or I/O) mapped register which indicates
the current status of the Display Processor, and allows the generation of interrupts depending on the
state of individual bits. Interrupts may be masked off
using the Display Processor Interrupt Mask Reg-
FMT-FIFO Empty. This indicates that the Display
FIFO has underrun. This forces an End of Line condition and the rest of the Display Line will display the
FldColor defined in the Display Control Register
Block. At the beginning of HBlank, the Display Processor uses the current Descriptor to start a new Display Data fetch. A FIFO underrun therefore does not
necessarily mean that the whole field is lost-just
the current display line is corrupted.
BlK-Blank. This indicates that the BLANK pin is
currently active for Vertical Sync.
EVN-Even Field. In Interlace and Interlace-Sync
modes, this bit is set during the even field (Field 1).
ODD-Odd Field. In Interlace and Interlace-Sync
modes, this bit is set during the odd field (Field 2).
The Even and Odd status bits assist in synchronizing
the 82786 with other interlaced display systems.
ECl-End of Command List. This is set at the same
time the ECl bit in the Opcode Register is set, and
allows the Display Processor to inform the CPU as
soon as it has completed execution of a command.
In loop Mode, the ECl bit is not set. It will be set
upon exiting loop Mode.
All active interrupts are OR'ed together to drive a
single 82786 interrupt line. Once set, the interrupt
line remains active until the Status Register is read.
The active bits in the Status Register (bits with 0 in
the corresponding bit in the Interrupt Mask) are reset
to zeroes after the Status Register is read.
10-30
inter
82786
Pin Conditioning
Test Modes
VOL/VOH
The 82786 implements several special modes of operation beyond normal use to aid in debug, characterization and production testing. When RESET
goes inactive, the RD and WR pins are sampled. If
either of these two pins is low, one of the special
test modes is enabled according to the state of RD,
WR and MIO pins.
The 82786 has the capability to bring all its output
pins to a constant logic high or low state. This feature can be used for testing the output buffers on the
82786.
A 16-bit Linear Feedback Shift Register signature
analyzer is placed on the Video output bus to compress the video data stream into a single signature
that is output onto the Video Data pins during Blank
time. The signature is also readable by the CPU at
the end of a Frame using the Dump_Reg command
at Register 10 3D. This signature analyzer output
onto the VDATA lines is activated in DP Test Mode.
Once in DP Test Mode, the signature Analyzer is
enabled by setting bit 14 of the DP Opcode register
to 1.
The 82786 has the ability to tristate all of its 1/0 and
output pins to effectively isolate the 82786 from any
connected circuitry. This allows testing a completely
assembled PC board by isolating the 82786. leakage on all 1/0 pins can also be tested in this mode.
The 82786 implements three global pin conditioning
features. Specifically, the 82786 can drive all output
and 1/0 pins high, or low, or can tristate all pins. The
test modes are' activated according to the following
table:
Storage Temperature
Operating Temperature
RD#
WR#
MIO
0
0
0
0
0
1
Reserved
0
1
0
DPTest Mode
Drive Output Pins High
Tristate Feature
82786 PARAMETRICS
ABSOLUTE MAXIMUM RATINGS
Voltage Vee-Vss
Voltage on Other Pins
- 65·C to + 150·C
O·Cto 70·C
-0.5Vto +6.5V
-0.5VtoVee + 0.5V
Mode
Reserved
0
1
1
1
0
0
Drive Output Pins low
1
0
1
Tristate Pins
1
1
X
Normal Operation
NOTE:
All timing numbers in the parametriC section are preliminary
and are subject to change.
D.C. CHARACTERISTICSTA = O·to 70·C, Vee = 5V ±5%
Parameter
Notes
Min
Max
Units
VILe
Input low Voltage
-0.5
+0.8
V
ClK Input
VIHe
Input High Voltage
+2.0
Vee + 0.5
V
ClK Input
Symbol
VILve
Input low Voltage
-0.5
+0.8
V
VeLK Input
VIHve
Input High Voltage
+3.9
Vee + 0.5
V
VeLK Input
VIL
Input low Voltage
-0.5
+0.8
V
All Other Pins
VIH
Input High Voltage
+2.0
Vee + 0.5
V
All Other Pins
VOL
Output low Voltage
+0.45
V
All Pins
IOL = 2.0mA
VOH
Output High Voltage
-
V
All Pins
IOH = - 400 p.A
+2.8
10-31
82786
D.C. CHARACTERISTICS TA =
Symbol
Min
-
,III
Input leakage Current
ILO
Output leakage Current
Icc
Power Supply Current
A.C. CHARACTERISTICS T A =
=
0° to 70°C, VCC
Parameter
-
0° to 70°C, Vcc
=
5V ± 5% (Continued)
Max
Units
Notes
±1
p.A
o _
231676-14
10-41
82786
DRAM SIGNALS-NON-INTERLEAVED FAST PAGE MODE WRITE
ClK
RAS
X
\~-------------------------------------------------------
CASO
DRA9:0
WEL,
WEH
015:0
ROW ADDRESS
COLUMN ADDR n+2
COLUMN ADDRESS n
-------------'1<-
------------{:::::J
',,"(0)
J,..----x::
231676-15
DRAM SIGNALS-INTERLEAVED FAST PAGE MODE READ
ClK
RAS
X
\~-----------------------------------------------------
CASO
CAS1
DRA9:0
ROW ADDRESS
COLUMN ADDRESS n
BENO
BEN1
TC~C
D15:0
TOAC(i)
___________~~r---------~.--~~IT~
____ ___
«XI
TCAA
~
231676-16
10-42
intJ
82786
DRAM SIGNALS-INTERLEAVED FAST PAGE MODE WRITE
CLK
RAS
\~------------------------------------------------------
X
CAS1
CASO
DRA9:0
ROW ADDRESS
COLUMN ADDRESS n
WEL. - - - - - - - - - - - - - - - - - - - - - - - " '
~----------------------H---~--------
WEH
D15:0
-----------------------<======J '-__
.I ' - _ - - - '
231676-17
DRAM SIGNALSNON-INTERLEAVED PAGE MODE AND FAST PAGE MODE VRAM DATA TRANSFER CYCLE
CLK
RAS X
CAS X
DRA9:0
I
,
,
X
-- TDTHj
COLUMN ADDRESS
ROW ADDRESS
~-}CDHj ~DTR-
TDLS-li.
TRDHN
DT1:0
I
y
TDTC -
231676-18
10-43
infef
82786
INTERLEAVED FAST PAGE MODE VRAM DATA TRANSFER CYCLE
-
ClK
OTO,
on
-
LJU- LrLr LrLr Lr Lr LrU-II
tTOlSf-
TRDHF
TOTR
RAS
CASO
/
\
\
CAS 1
-
DRAg: 0 ...
t
tx
231676-28
INTERLEAVED PAGE MODE VRAM DATA TRANSFER CYCLE
-
LJLrU- Lr LrLr LILr LJ LrII
ClK
OTO,
on
i. .
-
TRDHP
1\
RAS
-TOTR
-1
\
CASO
CAS 1
DRAg: 0
TDlS~
-
\
- J...
231676-29
10-44
82786
ENTERING AND LEAVING MASTER MODE
01
02
02
01
02
01
02
HREQ
HlOA
MEN
____________
~
____J
__________________-+~J
RD,WR,
A21 :0,
MIO,BHE
-----------------------C=J ~=l====)--------
D15:0
---------------~ p~~§:}------231676-19
MASTER MODE TIMINGS
02
01
02
01
02
01
02
01
02
01
02
ClK
RD,WR
A21:0
READ
CYCLE· - - - - - - - - - - -
TMB
D15:0
WRITE -------~,r_----CYCLE
D15:0
TM9
Jt----i _
__
-------------------- HC3) until the CPU has
written the correct values into DRAM. The timings
listed assume a 125 nsec clock (8.0 MHz) at XTALIN.
Most important to the initialization procedure are the
reset values of the Register and Data Windows:
After the Register Segment is completely initialized,
CPU sets the UCF bit by writing to RO.
RO 011 00000 011 1 0 0 1
6073H
The VSDD would now update its on-chip control registers with the data programmed by CPU in the Register
Segment.
The CPU then programs the display data through the
data window,. After the data has been written into
memory, the CPU enables the. display by setting DEN
bit.
RO 011 00000 011
0 1
607BH
Register Window Base Address: 00400H
Data Window Base Address: (undefined)
INITIALIZATION PROCEDURE
The first access must be a write cycle to Register RO at
00400H. In the first write cycle the CPU should program the DRAM configuration bits DSI, DSO and
DOF for 64K x 4 DRAMS employed in this design.
This first write cycle should leave DEN and UCF at O.
UCF (Update Control Flag) should be left clear till the
The register segment is programmed as follows to obtain a display shown in Figure 4. The VSDD reads the
register segment on every frame to update its on-chip
registers. The reader should refer to the user's manual
for description of the bits in the register segment. See
Appendix A for horizontal and vertical sync constants.
The VSDD DRAM is word addressable while the CPU
address space is byte addressable.
10-53
inter
AP-268
0,0
96
400
~~~~~~~~~------------------------------------------------------------~
160,20..--_ _ _ _---,288,20
VIDEO STORAGE
AND
DISPLAY DEVICE
82716
INTEL
160,70
288,70
OBJECT 3
40,115
L..J
Fl.·
.. ·.·•·•·.·
56,134
OBJECT 1
OBJECT 2
200
231679-3
Figure 4. Display Screen
REGISTER SEGMENT
OOOOH
DRAM
WORD
ADDR
OOOOOH
0002H
00001H
R1
0004H
00002H
R2
CPU
ADDR
REGISTER
CONTENTS
COMMENTS
RO
o1 1 00000 0 11 11 0 11
Duty Cycle
011
Blink Rate
00000
DS1 DSO DOF
011
HRS
1
DEN
1
SAB
0
DEI
1
UCF
1
1010 010 00 00101 0 0
Char height
1010
INL
0
MAS
1
SM
0
TMM, TMS
00
EVC
0
PCE
1
FAE
0
RE
1
PSA
0
PRE
0
0000 0000 00000 11 0
RWBA
OOOH
TF2 TF1
11
ME
0
607BH
50%
7.5 Hz for 60 Hz frame rate
64Kx4 DRAMs
640 Pixels horizontally
Display Enabled
Fast DRAM
Digital Outputs on RGB & OVR pins
Update all the registers on every frame
A414H
10 Scan lines
Non interlaced
HSYNC, VSYNC are outputs
Non composite SYNC mode
Twin mode is disabled
CKIO is O/P. Video Clk derived from XTALIN.
Priority counter enable
Use RDY as ready signal
CPU elm read the DRAM
GCLK = 1/16XTALIN
Disable pipeline read
0006H
RWBA = 0
Digital pixel codes
No margin
10-54
infef
AP-268
REGISTER SEGMENT (Continued)
REGISTER
CONTENTS
COMMENTS
0006H
DRAM
WORD
ADDR
00003H
R3
0008H
00004H
R4
OOOAH
00005H
R5
0000 00 0101000 000
DWBA
00000
Screen 0101000 111
Boundary
1 0000 00000000000
Length Mask
10000
0000 0000 0000 0000
Data
Segment
Base S16-S12 00000
Bank Select Bits
o0
0000 0000 0000 1010
PAQ 1010
0140H
A 16 Should be low
= Rt edge of the screen is at
X=327
8000H
64K byte data window
OOOOH
CPU
ADDR
OOOCH
00006H
R6
OOOEH
00007H
R7
0000 0101 0000 0000
ODTBA
0500H
0010H
00008H
R8
0012H
00009H
R9
0000 0000 0010 0000
0010H
ATBA
0000 0001 1000 0000
CTBA
0180H
0014H
OOOOAH
R10
0000 0000 0010 0011
CGBAO
0010
CGBA2
0011
0016H
OOOOBH
R11
0000 0000 0010 0000
0018H
OOOOCH
R12
000001
HCO
VCO
000100
HC1
VC1
011101
HC2
VC2
100000
001AH
001CH
001EH
OOOODH
OOOOEH
OOOOFH
R13
R14
R15
BankO
OOOAH
CPU is allowed 10 DRAM
accesses during line building
0500 H
Object descriptor table starts at
0500H in bank 0
0010 H
Access table starts at 001 OH in bank 0
0180H
The color table is not used in this
design. The space is reserved
for future use.
0023H
Char gen 0 starts at 2000H in
bank 0
Char gen 1 starts at 3000H in
bank 0
Access table address counter =
access table base address
(initially) = 0010H
0000000010B
HSYNC Width = 4 p.s
VSYNC Width = 198 p.s
0000100100B
AHZ Start = 10 p.s
AVZ Start = 2.5 ms
0011101100
0011110100
NOTE:
See Appendix I on how to program registers R12-R15.
10-55
AHZ Stop = 60 p.s
AVZ Stop = 16.17 ms
Hori. sweep rate = 66 p.s
Vert. sweep rate = 16.67 ms
AP-268
3.0 THE DATA SEGMENT
The actual object data and the different tables are
stored in the data segment by the 80186. There are 5
tables in the data segment: The access table, the object
descriptor table, the color lookup table and two character generators. Since digital outputs are used to drive
the monitor in this design, the color lookup table is left
blank.
3.1 Access Table
The access table contains the vertical start and end locations of each object. The table begins at the locations
designated by access table base address register, R8, in
the register bank. Each entry in the table contains 16
bits--each bit representing one object. Bit number 0
has the lowest priority and bit number 15 the highest.
The first entry in the table corresponds to the topmost
line on the screen and so on. Each entry indicates to the
VSDD which objects are to be present on this line of
the display. If a bit is set (1), then there is no change in
the objects display status; that is, if the object did not
appear on the previous line, it will also not appear on
this line. If the object's access flag is set to zero, then
the display status is reversed from what it was on the
previous line. The VSDD assumes that at the beginning
of a frame all objects are turned off (1 's).
The access table for the screen in Figure 4 is shown in
the following pages. The screen has 400 x 200 resolution. There are 200 entries in the table for 200 vertical
lines on the screen. Object 0 starts on line 1 and ends at
line 75. Bit 0 is set to zero at line 1 to tum the object 0
on and again set to 0 at line 76 to tum the object off.
Note that the 80186's address space is byte addressable
and the VSDD's space is word addressable.
Ib151b141b131b121b11 Ib10lb91bBlb71b61b51b41b31b21b1 IbOI
Figure 5. Access Table Word
ACCESS TABLE
CPU
ADDR
DRAM
WORD
ADDR
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
0030H
0032H
0034H
0036H
0038H
003AH
003CH
003EH
0040H
0042H
0044H
0046H
0048H
004AH
004CH
004EH
0050H
0052H
0054H
0056H
0058H
00010H
00011 H
00012H
00013H
00014H
00015H
00016H
00017H
00018H
00019H
0001AH
0001BH
0001CH
0001DH
0001EH
0001FH
00020H
00021H
00022H
00023H
00024H
00025H
00026H
00027H
00028H
00029H
0002AH
0002BH
0002CH
ACCESS FLAGS
b
b
b
b
b
15
14
13
12
11
b
10
bbbbbbbbbb
9 8 7 6 5 4 3 2
0
0
1
Line 1
1
1
.1
Line 10
1
o
1
10-56
Line 20
Turn on the
character
object
inter
AP-268
ACCESS TABLE (Continued)
CPU
ADDR
005AH
005CH
005EH
0060H
0062H
0064H
0066H
0068H
0070H
DRAM
WORD
ADDR
ACCESS FLAGS
b
15
b
14
b
13
b
12
b
11
b
bbbbbbbbbb
10
9
B 7
6
5
4
3
2
0
Line 30
0002DH
0002EH
0002FH
00030H
00031 H
00032H
00033H
00034H
00035H
Line 37
Line 38
1
1
1
1.
1
1
o
00B4H
0005AH
10-57
Line 71
(Turn off the
character object)
Line 74
AP-268
ACCESS TABLE (Continued)
CPU
ADDR
DRAM
WORD
ADDR
00B6H
0005BH
b
15
b
14
b
13
b
12
b
11
ACCESS FLAGS
b b b b b
10 9 8 7 6
b
5
b
4
b
3
b
2
b
b
0
o
1
Line 76 (Turn off
Obj.O)
1
1
1
1
OOFEH
0007FH
Line 111
10-58
inter
AP-268
ACCESS TABLE (Continued)
CPU
ADDR
DRAM
WORD
ADDR
00100H
00080H
ACCESS FLAGS
b
b
b
b
b
b
15
14
13
12
11
10
bbbbbbbbbb
9 8 7 6 5 4 3 2
0
Line 112
o
Line 115 (Turn
on Obj. 1)
Line 120
Rectangle
Object #1
Line 125
1
1
Line 130
1
1
o
.1
Line 134
Line 135 (Turn
off Obj. 1)
1
o
1
Horizontal Line
Object #2
o
Line 140 (Turn
on Obj. 2)
Line 142 (Turn
off Obj. 2)
Line 151
Up to 200 Lines
10-59
AP-268
ACCESS TABLE (Continued)
CPU
ADDR
DRAM
WORD
ADDR
b
b
b
b
b
ACCESS FLAGS
b
b b b b
b
b
b
b
15
14
13
12
11
10
5
4
3
2
9
8
7
6
b
b
0
1
1
1·
1
1
1
1
Line 200
10-60
intJ
AP-268
3.2 Object Descriptor Table:
This table contains a 4-word object descriptor field for each object in the display. The table starts at the location
specified by the OBTBA register, R7. This field specifies the base address of the object in the RAM, horizontal
position, its width and other attributes. The descriptor fields for bit-map and character objects are shown in Figure 6.
Bitmapped
I
I
I
I
I
N: qurrentlObjelct EntrylAddres~
I
I
I
I
~: XO Coprdinatel
I
I
I
0: Object Base Address
v:': O~ject yvidth
I
o
I0 I0 I
0
I
I
I C/B J R1 -'
I
RO
I
I
N15 i NO
HI
015-00
1 0 J 017 J 016 J OBL I BLA J 0 I TOE I C1 I CO
LO
Character
,Z: SIi5e NO. 1
J
I
I
I
IN: Curr~nt Objlect EntfY Add~ess
L
0: Object Base Address
~: Obj~ct Wi~th
I
Y: Slice No.
~11-NOI
I
I C/B I R1
I
RO
I
I
HI
015-00
I
I
,
X}O Coprdinatr
I
I
I
I
I CRS I PSE I FAD I OBL I BLA I HCR I TOE I C1 I CO
LO
Figure 6
Objects are rectangular windows on the screen. The object data begins in the display RAM at the object base address
specified in the object descriptor field. The length of the data file depends on the objects height, width and resolution.
The width is specified in 4-word units by the "W" field. In this design a 4 bits/pixel specification is chosen. Hence,
each 4-word unit represents 16 pixels. Objects 0 in Figure 4 is 6 x four word wide, that is 96 pixels wide. The object
descriptor field and object data for each of the objects in Figure 4 are as follows:
OBJECT 0 DESCRIPTOR FIELD
Fill 75 Lines on the Screen with One Color
DRAM
CPU
WORD
CONTENTS
ADDR
ADDR
OAOOH
00500H
OA02H
00501H
0000011000000000
C/B = 0
R1RO = 11
017,016 = 00
OBL = 0
BLA = 0
TOE = 0
C1CO = 00
0001100000000000
WIDTH:
000110
x
OA04H
00502H
OA06H
00503H
0000000000
0001 0000 0000 0000
Object base address
0001 0000 0000 0000
Current object entry
10-61
COMMENTS
0600H
Bit mapped object
4 bits/pixel
Object is in bank 0
No blinking
Object is not turned off
Non transparent pixels
Don't care for 4 bits/pixel
6 four word wide
= 96 pixels wide
Object starts at the left
edge of the screen
01000H
01000H
infef
AP-268
OBJECT DATA
OBJECT 0
OBJECT BASE ADDR = OlOOOH
CPUADDR
DRAM WORD ADDR
2000H
2002H
2004H
2006H
2008H
202EH
PIXEL DATA
01000
01001
01002
01003
01004
01005
01006
01007
01008
01009
0100A
01008
0100C
0100D
0100E
0100F
01010
01011
01012
01013
01014
01015
01016
01017
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
10-62
Line 1
24 Words = 96 Pixels
wide @ 4 bits/pixel
End of Line 1
AP-268
OBJECT 0 DATA
CPU AD DR
2060H
DRAM WORD AD DR
01030H
PIXEL DATA
8888H
016FOH
016F1H
016F2H
016F3H
016F4H
016F5H
016F6H
016F7H
016F8H
016F9H
016FA
016FB
016FC
016FD
016FE
016FG
01700
01701
01702
01703
01704
01705
01706
01707
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
8888H
2EOE
Line 3
Line 75
End of line 75
OBJECT 1 DESCRIPTOR FIELD
RECTANGLE
20 SCAN LINES/
16 PIXELS WIDE
CPU
ADDR
DRAM
WORD
ADDR
OA08H
00504H
OAOAH
00505H
OAOCH
OAOEH
00506H
00507H
CONTENTS
COMMENTS
00000 11 00 00 00 00
C/B = 0
R1RO = 11
017,016 = 00
OBL = 0
BLA = 0
TDE = 0
C1CO = 00
000001 0000010100
WIDTH = 000001
0600H
Bit Mapped Object
4 Bits/Pixel
Object in bank 0
No Blinking
Object is not turned off
Non-transparent pixels
Don't care
*X = 0000010100
0001 0111 0000 1010
0001 0111 0000 1010
1 Four word wide
= 16 Pixels wide
Objects starts at X = 20
Object base addr 0170AH
Current obj. entry 0170AH
'NOTE:
When HRS = 1, unit displacement in X direction moves the object by 2 pixels. Thus the object 1 will start at pixel number
40.
10-63
inter
AP-268
OBJECT 1 DATA
CPUADDR
2E14
DRAM WORD ADDR
01070H
0170EH '
0170FH
01710H
01711H
PIXEL DATA
7777H
7777H
7777H
7777H
7777H
7777H
7777H
7777H
01756H
01-757H
,01758H
01759H
2EB2
7777H
7777H
7777H
7777H
Line 1
Line 2
Line 2
Line 2
Line 2
Line 20
OBJECT 2 DESCRIPTOR FIELD
HORIZONTAL
CPU
ADDR
OA10H
OA12H
OA14H
OA16H
2 SCAN LINES/
240 PIXELS WIDE
DRAM
WORD'
.ADDR
00508H
00509H
0050AH
0050BH
CONTENTS
COMMENTS
0000 011 00 00 00 00
001111 00001 00 11 0
WIDTH = 001111
Same as obi 0 and obi 1
X = 38
0001 0111 0110 0000
0001 0111 01100000
10-64
15 four word wide
= 250 pixels wide
Obi base addr. 01760H
Current obi entry
= Obi base address (Initially)
inter
AP-268
OBJECT 2 DATA
CPU AD DR
DRAM WORD ADDR
PIXEL DATA
01760H
5555H
5555H
5555H
5555H
5555H
5555H
2ECOH
Line 1
60 Words
5555H
2FAEH
0179C
5555H
5555H
5555H
01707
5555H
Line 2
OBJECT 3 DESCRIPTOR FIELD
TEXT
50 SCAN LINES/
16 CHARACTERS WIDE
CPU
ADDR
DRAM
WORD
ADDR
OA18
0050CH
OA1A
OA1C
OA1FH
0050DH
0050EH
0050FH
CONTENTS
COMMENTS
1010 1 10 0 0 0 0 0 0 100
Y: Slice No. = 1010
C/B = 1
R1RO = 10
CRS = 0
PSE = 0
FAD = 0
OBl = 0
BLA = 0
HCR = 0
TOE = 1
CICO = 00
000010 0001010000
WIDTH = 000010
X = 0001010000
0001 0111 1101 1010
0001 0111 1101 1010
10-65
Start Slice Number
Character Object
8 Pixels/Character
Character Generator 0
Monospace Characters
1 Byte/Character
No blinking
Object is not turned off
Don't care
Transparent pixels
Default color bits
2 four word wide
= 16 characters wide
Object starts at X = 80
Object Base Address 017DAH
Current Object Entry 017DAH
intJ
AP-268
OBJECT 3 DATA
CPUADDR
2FB4
2FC4
DRAMADDR
ASCII CODE
0170A
01708
0170C
01700
0170E
0170F
017EO
017E1
017E2
017E3
5620
4449
4F45
5320
4F54
4152
4547
2020
2020
2020
2020
4E41
2044
2020
2020
2020
4420
5349
4C50
5941
4420
5645
4359
2045
2020
2020
2020
2020
3238
3137
2036
2020
2020
2020
2020
4E49
4554
204C
2020
2020
2F04
017EA
2FE4
017F2
2FF4
017FA
10-66
Line 1
Line 2
Line 3
Line 4
Line 5
intJ
AP-268
CHARACTER GENERATOR 0
The pixel data for characters are stored in one of 2
character generators in the display RAM. Character
generator 0 is used in this design. The base address of
character generator 0 as obtained from RIO, is 02000H
in bank O. Character height as defined in Rl is 10 scan
lines. The character set 0 consists of 10 blocks of 256
words each. Block No.1 contains the 1st slice of each
of 256 characters, block 2 has the 2nd slice of all the
256 characters and so on. In this example, 26 alphabets
and 10 numerals are defined. The VSDD addresses
character generator as shown in Figure 7. Individual
slices are addressed by concatenating the four bits of
the character generator base address with the slice
number Z and the ASCII code itself. Slice number 0 is
the bottom scan line for the character and slice number
H -1 is the top line. Each slice is encoded as a sequence
of pixel bits. If a pixel bit is 1, then the pixel is given the
foreground color. If the bit is 0, the pixel is displayed in
background color. This is shown in Figure 8.
Figure 9 shows how the pixels are encoded for character "F" (ASCII code = 46H).
CHAR GEN 1
CHAR GEN
BASE ADD R
2S6 ' H
BASE ADDR
2S6' H
SLICE
H-1
a
t-------1
SLICE
H-1
0
0
0
SLICE
2
SLICE
2
SLICE
1
SLICE
1
BASE ADDR
2S6'H
SLICE
SLICE
a
a
BASE ADDR :
BASE ADDR:
SLICE
INFORMATION
256 WORDS
(ONE FOR EACH
ASCII CODE)
1
REGISTER SEGMENT
R10
t
SLICE NO •
...L.
t--------I
t--------I
OBJECT 1
DESCRIPTOR
DATA
H
CHARACTER
HEIGHT
231679-4
Figure 7. Addressing Character Slices
10-67
inter
Ap·268
OBJECT 1
DESCRiPTOR
SLICE WORD
~
BOND
l
.I Cl I CO I 0 I bl I,
\
231679-6
TO PIXEL
PROCESSOR
b) FAD = 1
231679-5
a) FAD = 0
Cl CO 0 O-BGND Color
Cl CO 0 l-FGND Color
Figure 8. Character Generator Pixel Construction
DRAM
ADDRESS
SLICE 9
SLICE 0
PIXEL BITS
P7 P6 P5
02946H
00000000
0
0
0
02846H
00000000
1
1
0
02746H
00000000
0
0
0
02646H
00000000
0
0
0
02546H
00000000
0
0
0
02446H
00000000
0
0
0
02346H
00000000
0
0
0
02246H
00000000
0
0
0
02146H
00000000
0
0
0
02046H
00000000
0
0
0
Character Width = 8 Pixels
Character Height = 10 Scan Lines
P4
0
1
0
0
1
0
0
0
0
0
P3
0
1
0
0
1
0
0
0
0
0
P2
0
1
1
1
1
1
1
1
0
0
P1
0
1
1
1
1
1
1
1
0
0
PO
0
0'
0
0
0
0
0
0
0
0
CPU
ADDRESS
HEX DUMP
0528CH
0508CH
04E8CH
04C8CH
04A8CH
0488CH
0468CH
0448CH
0428CH,
0408CH
OOOOH
007EH
0006H
0006H
001EH
0006H
0006H
0006H
OOOOH
OOOOH
= 02000H
Character Generator Base Address
,
NOTE:
The leftmost pixel corresponds to the LSB in the slice word.
Figure 9. Bit Storage for Character "F"
The 80186 used in this design is resident on a single
board computer known as SDV-186 board. This board
is available from Red River Technology, Inc. in Addison, Texas. The VSDD board is connected to the 186
board via expansion connectors. The memory maps for
the SDV-186 board and the VSDD are shown on the
following pages. The CPU address space from
60000H-6FFFFH is used for 64K data window. This
data window maps onto the data segment in the
.VSDD's memory space.
10-68
intJ
AP-268
VSDD MEMORY MAP
VSDD DRAM AD DR
00000
CPUADDR
60000
RO
CONTROL REGISTERS
6001E
60020
OOOOFH
R15
SCAN LINE 0 FLAGS
ACCESS TABLE
601BOH
SCAN LINE 200 FLAGS
6022A
BLANK
602FE
60300
COLOR 0000
00180H
COLOR LOOKUP TABLE
6031E
COLOR 1111
60320
BLANK
603FE
00500H
60AOO
OBJECT DESCRIPTOR
TABLE
60A18
BLANK
61FFE
01000H
'62000
OBJECT DATA
63FFE
02000H
64000
CHARGENO
65FFE
03000H
66000
CHAR GEN 1
67FFE
68000
BLANK
10-69
AP-268
Memory Mapaf the SDV-186 Board
00000H-003FFH
INTERRUPT VECTORS
00400H-0076FH
PROGRAM DATA
00770H-007FFH
STACK
00800H-00FFFH
MEMORY
01 000H-1 FFFFH
VACANT
20000H -3FFFFH
VACANT
LCSI
40000H-4FFFFH
64-K MEMORY
MCSOI
50000H-5FFFFH
64-KMEMORY
MCS11
60000H-6FFFFH
64-K MEMORY (VACANT)
MCS21
70000H-7FFFFH
64-K MEMORY (VACANT)
MCS31
80000H-FBFFFH
VACANT
FCOOOH-FFFFFH
MONITOR CODE
10-70
UCSI
AP-268
APPENDIX A
PROGRAMMING HORIZONTAL AND VERTICAL
CONSTANTS FOR IBM MONITOR
The constants will be programmed for a resolution of 400 x 200 at 60 Hz, non-interlaced mode.
60 Hz givc;:s a frame period of 16.67 ms.
For IBM Color Monitor, vertical blanking = 3 ms.
Active Vertical zone = 16.67 - 3 = 13.67 ms.
There are 200 lines in one frame.
..
Line Time
13.67
"'S
= 200 = 68.35
Horizontal Blanking = 16
"'S
Active Horizontal zone = 68.35 - 16
= 52.35
",S
.
1
HOrizontal Sync Frequency = Line Time
68.35
= 14.6 kHz
Pixel CLOCK PERIOD
=
Active horizontal time
no. of pixels/ scan line
= 52.35
"'S = 130.1 ns
400
1
PIXEL CLOCK = - - = 7.7 MHz
130.1
We will use a pixel CLK of 8 mHz. As EVC
=
0, System CLK is also 8 MHz.
Horizontal Blanking for the monitor = 16 /Ls.
This blanking time includes the front porch, sync width and the back porch.
10-71
AP-268
RASTER TIMINGS
HSYNC - - - ,
i
(VSYNC)
L...J
JL
U
HCO
- 1 -I(VCO)
HC3
- - - - - - ( V C 3 ) -------~.
(A~~~"---+-----,I"""-------"'I--FP·
I--(,~g:)--l
BP-.j----
LBLANKING
I
TIME. ----I
-------.J.!
(VC2)
1---'-----'_ _ _ _ HC2
231679-7
HORIZONTAL CONSTANTS
HC2· = 60 p's
For IBM color monitor, Hsync width = 4 JLs
HC2
=
011101B
HC3
=
66 p's
Horizontal blanking = 16 p.s
=
30 GCLK Periods
33 GCLK Periods
HC3 = 100000B
Assume:
FP = 6 p.s
VERTICAL CONSTANTS
BP = 6 p.s
Vertical Blanking
HCO = 4 p's
HC1
=
4
HC3
+ 6 = 10 p.s
+
=
52.3
=
Line Time
= 66 p.s
10
=
=
+
HC1
For IBM Monitor
62.3 p's
VCO = VSYNC Width = 198 p's
68.3 p's
= 3 Line times
For 8 MHz Video Clock, the period is 125 ns.
NOW, PSA
=
VCO = 0000000010B
0
Assume, FP = 0,5 ms
GCLK PERIOD = 16 X 125 = 2000 ns
= 2 p's
BP = 2.3 ms
VC1 = VCO
HCO - HC3 are programmed in terms of GCLK
=
3 ms
=
Line Time = 33 GCLK Periods
HC2 = Active Horizontal Time
HCO
=
2 GCLK PERIODS
=
=
4 p.s
VC1
HCO = 000001 B
=
+
BP
0.198
+
2.3
= .2.5 ms =
0000100100B
VC2 = Active vertical time
NOTE:
HCO- HC3 and VCO- VC3 values are offset by 1, i.e.
if HCO is 2, then time programmed is 3 GCLK periods. HC2 and HC3 had to be tweeked to obtain a
steady display on the screen. The following values give
a flicker-free display.
HC1
=
10 p's
=
HC1
=
000100B
5 GCLK Periods
10-72
37 Line times
=
13.67
+
2.5
=
+
VC1
16.17 ms
=
237 Lines time
VC2 = 0011101100
VC3
=
VC3
= 0011110100
Vertical sweep rate
=
16.67 ms
=
245 Line times
inter
AP-268
APPENDIX B
CHARACTER GENERATOR 0
This character set is located in the VSDD's DRAM in bank O. It starts at 02000H. 26 alphabets, 10 numerals and a
blank space are defined here. The ASCII code for the characters are as follows:
CHARACTER ASCII NUMERALS ASCII CODE
41H
0
30H
A
B
42H
1
31H
43H
2
32H
C
44H
3
33H
D
45H
4
34H
E
F
46H
5
35H
47H
6
36H
G
H
48H
7
37H
49H
8
38H
I
4AH
9
39H
J
4BH
K
L
4CH
M
4DH
N
4EH
4FH
o
50H
P
Q
51H
52H
R
S
53H
T
54H
55H
U
V
56H
W
57H
X
58H
y
59H
Z
5AH
BLANK SPACE 20H
The character set has 10 blocks of 256 words each. All the locations except those corresponding to above 37
characters are blank in the display RAM. They are programmed with O's. The hex dump for the characters is as
follows:
10-73
inter
AP-268
SLICE 0
DRAM
HEX
LOCATION
DUMP
2020H
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2041
2042
2043
2044
2045
2046
2047
2048
2049
204A
204B
204C
2040
204E
204F
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
205A
OOOOOH
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
SLICE 1
DRAM
HEX
LOCATION
DUMP
2120H
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2141
2142
2143
2144
2145
2146
·2147
2148
2149
214A
214B
214C
2140
214E
214F
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
215A
OOOOOH
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
10-74
SLICE 2
DRAM
HEX
LOCATION
DUMP
2220H
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2241
2242
2243
2244
2245
2246
2247
2248
2249
224A
224B
224C
2240
224E
224F
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
225A
OOOOOH
003C
007E
007E
003C
0060
003C
.003C
0018
003C
003C
0066
003E
0038
001E
007E
0006
0038
0066
003C
003C
0066
007E
0066
0046
003C
OOOC
007C
0066
003C
0018
003C
0018
003C
0066
0018
007E
CHARACTER
BLANK SPACE
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
·V
W
X
Y
Z
intJ
AP·268
DRAM
LOCATION
HEX
DUMP
DRAM
LOCATION·
HEX
DUMP
SLICES
DRAM
HEX
LOCATION
DUMP
2320H
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2341
2342
2343
2344
2345
2346
2347
2348
2349
234A
2348
234C
234D
234E
234F
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
235A
OOOOH
0066
0018
0006
0066
0060
0066
0066
0018
0066
0066
0066
0066
006C
0036
0006
0006
006C
0066
0018
0066
0036
007E
0066
0066
0066
0006
0026
0036
0066
0018
0066
0018
007E
0066
0018
0006
2420H
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2441
2442
2443
2444
2445
2446
2447
2448
2449
244A
2448
244C
244D
244E
244F
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
245A
OOOOH
0066
0018
OOOC
0060
007E
0060
0066
0018
0066
0060
007E
0066
0006
0066
0006
0006
0046
0066
0018
0060
OOOE
0006
0066
0076
0066
0006
0036
001E
0060
0018
0066
003E
005A
003C
0018
OOOC
2520H
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2541
2542
2543
2544
2545
2546
2547
2548
2549
254A
2548
254C
254D
254E
254F
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
255A
SLICE 3
SLICE 4
10-75
OOOOH
006E
0018
0030
0038
0066
0060
003E
0018
003C
007C
0066
003E
0006
0066
001E
001E
0066
007E
0018
0060
0006
0006
0066
007E
0066
003E
0066
003E
003C
0018
0066
0024
005A
0018
003C
0018
CHARACTER
SPACE
0
1
2
3
4
5
6
7
8
9
A
8
C
D
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
Y
Z
inter
Ap·268
SLICE 6
SLICE 8
SLICE 7
DRAM
LOCATION
HEX
DUMP
DRAM
LOCATION
HEX
DUMP
2620H
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2641
2642
2643
2644
2645
2646
2647
2648
2649
264A
264B
264C
264D
264E
264F
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
265A
OOOOH
0076
001C
0060
0060
0078
003E
0006
0030
0066 '
0066.
003C
0066
0006
0066
0006
0006
0006 '
0066
0018
0060
OOOE
0006
007E
006E
0066 .
0066
0066
0066·
0006'
0018
0066
0066
0042'
003C
003C·
0030
2720H
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2741
2742
2743
2744
2745
2746
2747
2748
2749
274A
274B
274C
274D
274E
274F
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
275A
OOOOH
0066
0018
0066
0066
0070
0002
0066
0066·
0066
0066
003C·
0066
006C·
0036
0006
0006·
006C
0066
0018
0060
0036
0006
0066 .
0066· .
0066·
0066
0066·.
0066
0066
0018
0066
0042
0042
0066
0066
0060
10-76
DRAM
LOCATION.
2820H
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2841
2842
2843
2844
2845
2846
2847
2848
2849
284A
284B
284C
284D
284E
284F
2850
2851
2852
2853
2854
2855
·2856
2857
2858
2859
285A
HEX
DUMP
OOOOH
003C
0018
003C
003C·
0060
007E
003C
007E
003C
003C
0018
003E
0038
001E
007E
007E
0038
0066
003C
0070
0066
0006
0024
0062
003C
003E
003C
003E
003C
007E
0066
0042
0042
0066
0066
007E
CHARACTER
SPACE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
I
J
K'
L
M
N
0
P
Q
R
S
T
U
V
W
X
Y
Z
inter
AP-268
SLICE 9
DRAM
LOCATION
HEX
DUMP
2920H
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2941
2942
2943
2944
2945
2946
2947
2948
2949
294A
2948
294C
294D
294E
294F
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
295A
OOOOH
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000.
10-77
CHARACTER
SPACE
a
1
2
3
4
5
6
7
8
9
A
8
C
D
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
Y
Z
AP-268
APPENDIX C
ANALOG OPERATION
In the example described in the application note, digital video outputs were used.
For analog operation, DEI (digitally encoded color information) bit in register RO is set to O. The on-chip color look
table (CLUT) is loaded with 16 entries from the external DRAM. These 16 words of data are stored in the memory
starting at color look up table base address. (Register R9). Each entry is 16 bits long-with lowest 4 bits specifying
the address of the entry in the CLUT and upper 12 bits specifying the color as shown in Figure 10. Four bit pixel
code is used to address the CLUT. The pixel code is matched with the lowest four bits of the CLUT RAM and the
pixel is given the color specified by the upper 12 bits. The address entries need not be sequential from 0-15 but they
can be random. The color corresponding to address 0010 in the CLUT is reserved for the background color.
ON CHIP
COLOR lOOK UP TABLE (ClUT)
4 ~~ 4 ~...--. 4 --..
•••
•
--
ENTRY ADDR ESS
16
••
••
tCOlOR
IN THE DRAM
STARTING AT COLOR
lOOK UP TABLE
BASE ADDRESS (R9)
I R3 R2 Rl
RD:G3 G2 Gl GD:B3 B2 Bl BO:A3 A2 Al AD
I
- - - - - - 1 2 B I T S - - - - -.... - 4 BITS-
R3-Ro: Red color component
G3-GO: Green color component
B3-Bo: Blue color component
A3-Ao: Entry address
Figure 10. Filling the CLUT
10-78
231679-8
inter
AP-268
The color look up table outputs-4 bits/color-drive 3
internal DACs (digital-to-analog converter). RGB signals are generated by the DACs. An externally supplied
reference voltage (VREF) is used to drive the DACs.
The value of VREF should be between 0 and 2V. As
DACs have high output resistance, external analog
buffers are used to interface them to low input resistance monitors as shown in Figure 11.
+5V
ANALOG
SIGNAL
FROM 82716
R, G, OR B
33.[1
TO 75.[1
......-111\1\1-_ MONITOR
INPUT
100.[1
231679-9
Figure 11. Buffering 82716 Analog Output
to Low Input Resistance Monitor
10-79
inter
AP-268
APPENDIX D
CLOCKING SCHEMES
The VSDD uses two clock signals: system clock and
video clock. The video clock can be derived from the
system clock or may be external.
An external clock may also be fed to the XTALIN pin
(instead of using a crystal). For example, CLKOUT pin
of 80186 can be used to drive the VSDD system clock.
The system clock is generated by an internal oscillator
using an external crystal at XTALIN and XTALOUT
pins. The crystal frequency can be between 5 MHz and
15 MHz.
If an independent video (dot) clock is desired (EVC =
1) CKIO is used to input this clock. Maximum video
clock frequency can be 25 MHz. EVC should be set to
zero if video clock is derived from system clock.
Figure 12 explains various clocking schemes.
VSDD SYSTEM
CLOCK (T-STATES)
XTALIN
VIDEO
CLOCK
231679-10
(a) VSDD Timing Unit
82716
VSDD
~:
If:+
82716
VSDD
EXTERNAL
OSCILLATOR - - . XTALIN
SIGNAL
XTALIN
XTALOUT
-
NC- XTALOUT
231679-12
231679-11
(b) With Crystal
(c) With External Clock
Figure 12. Clocking Schemes
10-80
(
9-PIH 0
CONNECTOR
17
ADD
ADl
AD2
AD3
AD4
ADS
AD6
AD7
AD8
AD.
AD10
AD11
AD12
AD13
ADt4
1
~
~
ADO
VSYNCI
ADl
HSYNCI
"i14
AD2
OVR
AD3
R
"66
AD4
G
ADS
B
28
""i6'1o
AD6
...-----.
.---,
..,..--;;"i2"i2
ADtS
~
MC521
~
o
-
AD.
AD10
CASH/ 63
CA5LI
A012
ADORO
AD13
AORRl
ADt4
ADRR2
ADtS
ADRR3
NO 27
NO~
CKID
PLLCTL
82716
ADRR5
VSDD
ADRR6
ADRRB
OLD
VPEF
DU
eTO
DL2
DL3
~ BHEI
RDI ~ RDI
WRI ~ WRI
ALE ~ ALE
8HEI
DL4
DL5
DL6
DL7
DHO
RESET
ROY
~
~
DHl
RESET
ROY
DH2
DH3
DH4
ClKOUT
£
66
XTALIN
DH5
DH6
XTALOUT
~
GI
TO IBI.4 PC
VSYNC
~HSYNC
TYPE COLOR
IoiONITDR
~ INTENSITY
74244
~REO
~
55.
R
GREEN
BLUE
61
ADRR7
NO 68
~
~
25
WEI 62
A16
GI
~
24
RAS/ 64
~
N03t
~:
AD8
ADRR4
-'
~
23
AD7
~ AD"
~
~
~
~
I I
OH7
5.
10
58
6
57
7
56
8
55
11
54
12
53
13
52
14
34
17
35
15
36
3
37
2
38
40
41
42
44
45
46
47
48
4.
50
A6
AS
A4
A3
A2
Al
AO 4464-15
~
3.
A7
GI
-
GI
A7
A6
AS
A4
A3
A2
-Al
AD
II
rrrrrrrr-
A7
A6
AS
A4
A3
A2
Al
AD
GI
I
I-I-I-I-I-I-I-I--
I
A7
GI
»
."
A6
AS
A4
."
ITI
AJ
A2
Z
Al
o
><
AD
004
4464-15
003
ITI
002
001
004
4464-15
003
002
001
004
4464-15
003
002
001
004
003
002
001
231679-13
»
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I
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Q)
CIO
(
SERE~'':-:- i l l
8086/87/88/186 i1ACRQ ASSEMBLER V2.0 ASSEMBLY OF MODULE VSDD_PIC1UUF
',,:jQULE PLACED IN . F3: APPSQF. OBJ
O~,-'t.:
ASSEM'81_~':~~
LOC
oFr.)
INVOKED BY:
ASN86.86: F3: APPSOF. ASM
LINE
SOURCE
1 +1
$mod186
2 +1
$xref
3
4
name
YSdd_picture
5
6
7
8
9
0001
_iGfJ;":,
60n
-'
o
~
6073
A414
0006
10
11
12
13
14
15
16
17
IS
19
20
21
22
23
24
25
26
27
2B
29
30
31
32
33
34
35
30
37
3B
39
JA routine to display a simple pictuT'P on the displa~
3 bit-map and 1 character obJects al'C displaloled.
i
this routine also shows hOllJ to move windollJs.
UCF
DEN
rO_res
equ
equ
equ
Ih
Bh
6072h
014G
8000
0000
50
msb 011 dutg eye Ie 50 percent
J 00000 blink rat. 7. 5Hz
, 011 64k,4 DRAMS
;.1 HRS
o DEN
o
1
o
rO_up
equ
rO_disp equ
rl_d
r2_d
equ
equ
h-O_res OR UCf')
(rO_res OR UCr OR DEN)
OA414h
SAS
640 pixels.l!ine
display is disabled
fast DRAMS
DEI Digital video outputs
UCF No register update
; set the UCF bit
; set the DEN bit
J 1010 character height 10 scan 1 ines
; 0 INL non interlaced mode
i
1 MAS VSYNK & HSYNe are outputs
o SM Non composite sgnc mode
00 TMM TMS t~in mode is disabled
o dont care bit
J 0 EVC CKIO is output. video elk is
derived from XTALIN
1 PC~ priorttv counter enabled
1 0 FAE use RDY as- READY signal
I RE CPU can read the DRAM
o PSA GCLK = 1/16 XTALIN
o PRE disable pipeline read
0006h
40
41
42
43
44
45
46
47
48
49
Jupdate control flag
idisplay enable bit
lioitial value of RO after reset
;
1
register ~tndo~ base addr is OOOOh
11 TF2 TFt digit.l pixel codes
ME no margin
a
r3_d
equ
0140h
r4_d
equ
BOOOh
I data window length 64k bVtes
r5_d
equ
ooaOh
J
data ~indo~ base addr is OOaOh
right edge of the screen is at
x = 327
J
data segment ba •• addT i . OOaOh
note data segment and register
231679-14
»
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"tJ
m
Z
C
-><
."
.
):0
"D
N
Q)
CD
LOC
OBJ
LINE
cl
SOURCE
'I
:;'2
53
5'!
i
i
i
i
!".egment overlap, In the overlapped
region register segment will
overwrite
the data segment
00 BS1 SSO bank 0
5~
00:..'';
o=<.;,j
,~.,) ~
i--'
0180
0010
0402
::02q
....o
74EC
dOF4
Co
Ul
0000 (1
56
57
58
r6_d
equ
OOOAh
CPU. is allollled 10 accesses during each
line building process.
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
r7_d
equ
0500h
obJect descriptor table starts at
0500h in bank 0
r8_d
equ
DOIOh
access table at OOlOh
r9_d
equ
0180h
color look up table base .ddr
rlO_d
equ
0023h
char genO at 200Qh
char gen1 at 3000h
rll_d
equ
0010h
r12_d
equ
0402h
r13_d
equ
10;?4h
rl4_d
equ
74ECh
r15_d
equ
80F4h
IICO.VCO
J
HCI. VCI
»
11C2. VC2
J
l'
IiC3.VC3
I\)
;
aI
allocate memory for register and data segments
video_vsdd
CO
at 60001i
segment
rO_v
dw
dup(?)
)
0002
(1
????
85
r1_v
dw
dupe?)
0004
(1
???-?
86
r2_v
dw
dupe?)
(1
87
r3_v
dw
dupe?)
0006
?-,.~-?
)
0008
(1
7'";"'·-:">7
88
1'4_.v
dw
dupe?)
OODA
(1
????
89
r5_v
dw
dupe?)
(1
90
r6_v
dw
dUIJ(?)
91
r7_v
dw
dup (?)
OOOC
????
)
OOOE o
????
OO~O
0020 (512
????
0400
0400
100
101
102
»
"U
org
aat._v
103
104
105
(1
dOl
020h
512
.
dupe?)
N
Q)
;ObJect Access Table(m.x length)
CCI
; power up IDcations or- l"t'Histers
o1"g
400h
d ..
dupe?)
lOb
irO_v
107
irl_v
dbJ
dupe?)
108
ir2_v
dOl
dupe?)
109
ir3_v
dbJ
dupC?)
110
ir4_v
dOl
dup
III
ir5_v
dw
dupe?)
112
ir6_v
dw
dup.(?)
????
)
0402 (I
????
)
0404 (I
??77
)
0406 (1
???'?
)
0408
(1
(?)
????
040A
(1
??7?
040C (1
????
231679-16
LOC
DB.!
040E
(1
LINE
SOURCE
11:,
i1'7_v
dw
dupe?)
114
irB._v
d..
dul'(?)
115
iT'9_v
dw
dupe?)
116
irlO_v
dw
duv
117
ir-l1._v
dw
dupe?)
118
ir12_v
dw
dupe?)
119
ir13_v
dw
dupe?)
120
ir14_v
dw
dupe?)
041E (I
????
121
ir15_v
dw
dupe?)
0300
122
123
????
0410 (1
??;'"?
-.
I~
)
0'112 (1
????
)
'0414 (1
?T??
(?)
)
0416 (1
?'???
)
0418 (I
????
)
041A (I
????
)
041C
(I
????
)
'?
0)
CJ1
0300
»
.
."
(16
org
clut_v
dw
???7
OAOO
300H
16
dupe?)
124
125
QdtO_v
dw
4
dupe?)
126
odtl_v
dw
4
dupe?)
127
odt2_v
dw
4
dupe?)
129
odt3_v
dw
4
dupe?)
129
130
131
obJect_O_v
dw
1800
dupe?)
2EI4
2EI4 (80
????
132
133
org
ob Ject_l_v
dw
80
dupe?)
2ECO
2ECO (120
134
135
org
obJect_2_v
120
dupe?)
CADO (4
org
????
N
en
icolour lookup tabl.
CO
OAOOH
;ObJect descriptor table
)
OA08 (4
????
)
OAIO (4
?7??
DAIS (4
????
2000
2000 (1800
????
.org
2000H
i3.6K-bytes
i4 bits/pilei 75*96 bit mapped
2EI4H
2ECOH
dw
231679-17
--
LOC
OBJ
LINE
I
SOURCE
???-,
2FB4
org
2FIl4H
d ..
100
duVC?)
cgO_91ice_O_v
04000H
d ..
256
dupe?)
140
egO_51 ice_l_v
d ..
256
dupe?)
141
cgO_slice~_v
dOl
256
dupe?)
142
cgO_slice_3_v
do.
·256
·143
c gO_51 i c e_4_v
d ..
256
dupe?)
144
egO_sl ice_::5_v
do.
256
du,.C?)
145
egO_sl ice_6_v
do.
256
dupe?)
)0
146
cgO_slice_7_v
do.
256
dupe?)
N
01
00
147
cgO_slice_8_v
dOl
256
dup (7)
148
cgO_slice_9_v
do.
256
dupe?)
149
cgO.....;.51 ice_l0_v
dOl
256
dup(?)
150
cgO_slice_l1_v
dOl
256
dupe?)
151
cgO_slice_12_v
dOl
256
dupe?)
152
cgO_slice_13_v
dw
256
dupe?)
153
cgO_slice_14_v
dw
256
dupe?)
154
cgO_slice...:,15_v
dOl
256
dupe?)
136
2FB4 (100
(
137
ob Jec t._3_v
138
139
????
4000
4000 (256
org
;Character O.nerator 0
????
)
4200 (256
????
)
4400 (256
?"'1??
)
4600 (256
df,Jp
(?)
?7??
)
4800 (256
'????
4AOO (256
'????
)
-'"
0
Co
OJ
4COO (256
'U
????
•
)
4EOO (256
????
)
5000 (256
????
)
5200 (256
????
)
5400 (256
????
)
5600 (256
????
)
5800 (256
????
)
5AOO (256
????
)
5COO (256
????
)
5EOO (256
????
231679-18
LOC
OB~
0000 205b4944454F20
53544F52414745
2020
0010 2020202020414E
44202020202020
2020
0020 20444953504C41
59204445564943
4520
0030 20202020383237
313102020202020
2020
....
0040 20202020494E54
454C0920202020
20
LINE
155
156
157
ISB
159
160
1101
ends
video_data
segment·
obJect_3_data
, VIDEO STORAGE
db
db
1104
165
db
11010
1107
db
82711.
168
169
db
INTEL
174
Dat. fOT character generator 0
Characters are 10 scan line. high
Slice .0,1 and 9 are emptu(O~ti)
26 alphabets and 10 numbers are defined
175
171.
slice information for 10 numbers
172
173
~
video_vsdd
162
163
170
171
9Q)
l
SOURCE
AND
, DISPLAY-DEVICE'
~
N
G)
CD
177
178
179-
004F
0050
0051
0052
0053
0054
0055
00510
0057
0058
0059
005A
0058
OO:;C
005D
3C
7E
7E
3C
100
IBO
3C.
3C
18
3C
3C
lob
18
010
lob
100
lob
lob
OOSE
005F
00100 IS
00101 lob
00102 lob
numb.,.s_data
db
3Ch,· 7Eh,
7Eh.
3Ch.
181
db
3Ch, 3Ch,
ISh, 3Ch, 3Ch
182
db
66h.
183
db
I.I.h. I!.I!.h. ISh. I.I.h. I!.I!.h
tSh, 06h, 66h.
60h
J
51 tce
a
60h.J slice 3
231679-19
l
ISh, OCta. 60h. 7Eh • sUce 4
db
66h.
db
6Oh, 66h.
db
6Eh.
db
60h. 3Eh.
db
76h.
db
3Eh. 06h. 3Oh. 66h. 66h
lSh. Mh. 60h
ISh, 30h, 3Bh. 6611
J
.lice
~
lSh. 3Ch. 7Ch
lCfl, 6011, 60h, 7Bh ,".Iice 6
I I :.
"D
•
I\)
G)
CD
18h. 66h. 66h, 70h",.l1c.· 7
db
Mh.
db
02h. 66h. 66h. 66h. Mh
db
3Ch.
db
7Eh. 3Ch. 7Eh. 3Ch. 3Ch
lSh. 3Ch, XII, 60h
J
.lice
a
slice in'OTmation"'OT 26 alphabets
Icharacter_aet_O
231679-20
_.
LOC
OBJ
0095 66
0096 3E
0097 38
LINE
199
200
201
SOURCE
; !.lices 0.
slice_2_d
I
1 and 9 are O's (empty>
db
(-.611,
3EH.
202
db
3CIi.
3CH. 66H, 7EH. 66H, 46H. 3CH. OCH
203
db
7CIi. 66H. 3CH.
204
db
1E1I1.
7EH
db
b61{,
66H.
206
db
181l. 66H. 36H. 7EH. 66H. 66H. 66H. 06H
207
db
2bJ'h
36H.
db
ISH.
06H
db
7EIi. 66H. 06H. 66H. 06H, 06H. 46H.
aSH.
lEH.
7EH,
cf
06H. 38H. 66H
0098 IE
.....
<0
0099
009A
009B
009C
0090
009E
009F
OOAO
OOAI
OOA2
OOA3
OOA4
OOA5
00A6
OOA7
OOA8
00A9
OOAA
OOAB
OOAC
OOAO
OOAE
OOAF
OOBO
OOBI
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
OOBA
OOBB
OODC
OOBO
OOBE
OOBF
OOCO
OOCI
00C2
00C3
7E
06
38
66
3C
3C
66
7E
66
46
3C
OC
7C
66
3C
18
3C
18
3C
66
18
7E
66
66
6C
36
06
06
6C
66
18
66
36
7E
66
66
66
06
26
36
66
18
66
205
18H. 3CH.
ISH. 3CH. 66H
~
slice_3_d
"U
I
6CH,
66H.
36H,
II
06H. 06H. 6CH. 66H
18H. 66H.
ISH. 7EH. 66H
OOC4 18
00C5
00C6
00C7
00C8
00C9
7E
66
18
06
7E
208
209
slice_4_d
66H
231679-21
PI)
01
CI)
LOC
.....
o
~
DB.!
OOCA 66
OOCD 06
OOCC 66
OOCD 06
OOCE 06
OOCF 46
OODO 66
OODI IS
00D2 60
00D3 OE
00D4 06
OODS 66
0006 76
00D7 66
OODS 06
00D9 36
OODA IE
OODD 60
OODC IS
OODD 66
OODE 3C
OODF SA
OOEO 3C
OOEI IS
00E2 OC
00E3 66
00E4 3E
00E5 06
00E6 66
00E7 IE
OOES IE
00E9 66
OOEA 7E
OOED IS
OOEC 60
OOED 06
OOEE 06
OOEF 66
OOFO 7E
OOFI 66
00F2 3E
00F3 66
00F4 3E
OOFS 3C
OOF6 IS
00F7 66
OOFS 24
00F9 5A
OOFA IS
OOFS 3C
OOFC 18
OOFD 3C
OOFE 66
OOFF 06
0100 66
LINE
(
SOURCE
210
db
1m . . , 60H. OEH, 06H. 66H, 76H. 66H, 06H
211
db
361-1.
212
213
slice_5_d
lEH,
6OH.
ISH. 66H,' 3tH.
db
ISH. OCH
db
66", 3EH, 06H. 66H.
IEH.
~AH.
3CH
I I
lEH. 66H, 7EH
l>
'1J
•
N
G)
m
214
db
lBI-I, 6QH. 06H. 06H. 66H. 7EH. 66H.
3EH
215
db
661-1,
216
217
slice_6_d
db
3CH.
db
- XU,
3EH.
3CH.
ISH,
66H.
24H,
~H,
ISH
ObH.
66H.
06H.
06H.
06H.
66H
II
lBH
66H ,
231679-22
--
LOC
OBJ
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
010C
0100
010E
OIOF
0110
0111
0112
0113
0114
06
06
06
66
18
60
OE
06
7E
6E
66
66
66
66
06
18
66
66
42
3C
0115 3C
0116 30
0117 3C
LINE
218
db
1011.
219
db
66H. 66H. 06H.
db
::::tCH.
30H
db
3CH.
66H. 6CH. 36H. 06H. 06H. 6CH. 66H
220
221
0118 66
~
a
:'1
0119
011A
011B
011C
0110
011E
011F
6C
36
06
06
6C
66
18
I
SOURCE
slice_.7_d
bOH.
OEH. 06H. 7EH. 6EH. 66H. 66H
18H. 66H. 66H. 42H. 3CH
»
'U
I
222
db
181i. 60H. 36H. 06H.
223
db
66H.
66H. 66H.
db
6611.
60H
db
JSH,
3EH. 38H.
0120 60
I I
66H. 66H. 66H. 66H
0121 36
0122 06
0123 66
0124 66
0125 66
0126 66
0127
0128
0129
012A
012B
012C
0120
012E
012F
0130
0131
66
66
66
18
66
42
42
66
66
60
18
0132 3E
0133
0134
0135
0136
0137
t
224
225
51 ice_8_d
18H. 66H. 42H. 42H. 66H
lEH. 7EH,
7EH,
38H. 66H
38
IE
7E
7E
38
231679-23
I\)
en
~
org 0
reset
mon i
d",
1 dupe?)
i
en
01)
a label
ends
tOT'
Main routine. This routine loads the DRAM with access table
the object descriptor table. the character generator and the
actual object data. The VSDD is also initialized.
;--------------------------------------------------------------------prog_code
segment
assume
simple_display
cs: pT'og_code.
proc
ds: video_data.
es: video_vsdd
far
start:
mava •• video_data
mav ds.ax
linitializ& the data s.gm&nt
mov ax.video_vsdd
linitializ. the extra
1 segment
mav es,ax
initialize the T'egister segment. the register
segment is located at 0400h aFter re!i>et.
231679-24
_.
LOC
OBJ
OOOA 26C70600047260
0011 26C706020414A4
0018 26C70604040bOO
OOIF
0026
002D
0034
003B
0042
0049
0050
0057
26C70606044001
26C70608040080
26C70bOA040000
26C7060C040AOO
26C7060E040005
26C70610041000
26C70612048001
26C70614042300
26C70616041000
OOSE 26C70b18040204
0065 26C7061A042410
006C 26C7061C04EC74
0073 26C7061E04F480
007A 26C70600047360
.....
?CO
0081 B94700
0084 E2FE
U)
0086 26C706000AOO06
008D 26C706020AOO18
0094 26C706040A0010
009B 26C706060A0010
00A2
00A9
OOBO
00B7
26C706080AOO06
26C7060AOA1404
26C7060COAOA17
26C7060EOAOA17
OOBE
OOCS
OOCC
0003
26C706100AOO06
26C706120A263C
26C706140A6017
26C706160A6017
LINE
SOURCE
263
264
265
266
267
irl __v.
ir2_v.
mav ir3_v.
ir4_v,
irS_v.
irb_v.
mav i 1'7_VI
2b8
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
I
mov i l'O_v. rO_1"l:'s
rl_d
r2_d
r3_d
r4_d
r5_d
T'o_d
cf
1'7_d
mav irB_v.rB_d
mov ir9_v. r9_d
mav triO_v. T'10~.d
mov irll_v. rU. d
mov
mov
mov
mov
ir12_v.r12_d
ir13_v. r13_.d
ir14_v.r14_d
irIS_v. 1'15_ d
all the registers are initialized in the DRAM. Enable the UCF
flag to allow the VSDD to' update it!. on thip registers.
mov i rO_v, rO_up
wait 150U5 for the VSDD to update its em chip registers
the loop assumes that the 80186 runs ~t OMhz.
,
,
»
-a
movex.7l
loop 1:
loop loopt
the register window is initialized to bOOOOh
the cpu programs the display data thrD~gh newly
defined data window in ,R3.
I
II
iload the obJect descriptor fields for four obJects
; obJect 0
mov odtO v, bOOh
mov odtO:vC2J.leOOh
mav odtO_vC4l,IOOOh
mov odtO_vC6l.1000h
J4bits/pixel.non-transparent
lobJect starts.t x = 0
ithe width is 96 pixels
lobJect base addTess
; obJect I
mav
,maY
mov
mov
Ddtl v,600h
odtl=vC2],0414h
adt1 v[4l. t70ah
odt1:vC6],110ah
x z aO,width -
16 pixels
iobJect2
mav adt2_v.600h
mav adt2 vt2l.3c?6h
mavadt2:vt4l,1760h
mov odt2_v[6l,17bOh
,
x e 3Siwidth .240 pi.el.
231679-25
N
CD
CO
_.
LOC
on.)
OOOA 26C706180A04AC
OOEl 26C7061AOA5008.
00E8 26C7061COAOA17
OOEF 26C7061EOAOA17
00F6 BA0200
00F9 BBOOOO
OOFC B90807
OOFF B88888
...
0102 2689870020
0107 030A
0109 E2F7
0
cO
./>.
010B BBOOOO
alOE B9:1000
0111 B87777
0114 268987142E
0119 030A
011B E2F7
0110 BBOOOO
0120 B93COO
0123 B85.555
0126 268987C02E
012B 030A
0120 E2F7
012F BBOOOO
0132 892800
0135 8B07
LINE
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
339
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
I I
SOURCE
cf
; obJect :3
mav odt3_v,OAC04h
mav odt3_v[2J,OB50h
cha,..cter obJect
pixels/charact.r
transparent pixel
, = 80. Width = 16
cha'racters
e
mav odt3 vC41.J7DAh
mav odt3=v[6],1?DAh
J
set up the obJect data
mav dx,2
mav bx,a
; obJect 0
mav CI,24*75
f i II_ob J_O:
~o,.ds I1n8s,24 words(96 pixels)
; numb.,. of data
;7~
al.88aSh
ipixel data
mav obJect-=..O_.vtbxJ, ax
add bl,dx
l>
loop fi II_Db J_O
"U
I
; obJect 1
I\)
0)
bx.O
,mav cI,4*20
mav a x, 7777h
fill_obJ_l:
CD
inumber of data words
; pixel data
may obJect_l_Y[bxJ. ax
add bx,dx
loop fill_obJ_t
; ObJect 2
mav bx.a
mav ex. 15*4
ax,
fi ll_ob J_2:
5555h
mav obJect_2_YCbxJ. ax
add bx. dx
loop fi 11_ob-J_2
;obJect 3 - character object
may b x, 0
may cx,40
fil1_obL3:
Jtatal 80 char~cter.
Jin the obJact.2/~ord
moy ax, word ptr obJect_3_dataCbxl
J
read the ASCII code
for 2 char4lcters
,
231679-26
LOC
OB.!
0137 268987B42F
OI3C 03DA
OI3E E2F5
0140 B80000
0143 BBOOOO
0146 BE6000
0149 B90AOO
014C BA0700
014F
014F 8A474F
0152 2689840044
0157 43
0158 83C602
....0
cb
C11
0159 E2F2
0150 81C6ECOl
0161 B90AOO
0164 4A
0165 75E8
0167
016A
0160
0170
B80000
B80000
B91AOO
BE8200
0173 BA0700
0176
0176
017A
017F
0180
8A879500
2689840044
43
83C602
0183 E2Fl
0185
0188
018C
0180
B91AOO
81C6CCOl
4A
75E7
LINE
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
l
SOURCE
mav obJect_3_v[bxl,ax
I.dl"ite the data
add bx. dx
loop fill_obJ_3
; load the charactor generator
mavax.O
mav bliO
; load the numbers
mav si,30h*2
i.tore at proper ASCII
Jlocation. Note cpu space
ibyte addressable
mov cillO
mav dx.7
ilO numbers
J
7 slices
write_a_number:
mav
al.number~pdata[bx]
cgO_slice_2~.v[f,ii]. ill
inc bx
add si,2
loop write_8_number
; read data bljte
I~rite data ~ord in
,the DRAM
I next b~te
next location in
I
the DRAM
)0
add si. (256*2)-20
mav cx,IO
;g
inext Blice
dec dx
(J)
CD
Jnt write_a_number
istoTe the 26 alphabets
mav ax.O
mav bllQ
mav cx,26
mav si.41h*2
mav dx,7
J 26 alphabets
Jproper offset into
Jcharacter generator
J 7 slices
IIJri te_a_character:
mav al. slice_2_.d[bxl
mav cgO_slice_;!_.v[siJ, ax
inc bx
add a1.2
Jread data bljt.
J write a word
J next bgte
Jnext location
loop lII"i te_a_c haracter
mav cI,26
add 01. (256*2)-52
inext slice
dec dx
Jnz write_a_character
231679-27
LOC
OD.!
OIBF DDOOOO
0192 890002
019~ BBFFFF
019B 8A0200
019D 2bB94720
019F 03DA
OIAI E2FB
01A3 DBFEFF
OIAb 2bA32000
OIAA 2bA3DbOO
LINE
.load the acceS5 table
43b
fill_oat:
437
43B
439
440
441
442
443
444
445
l
SOURCE
427
42B
429
430
431
432
433
434
435
may br,O
may ex,leng:th oat._v
may a'x,Of,.pfh
may dx.2
fill the access table with all Is
mov ojlt_vtbxl,ax
add bx. dx
loop fill_.oat
i.nabla the obJects
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292007-4
Figure 5. Fast Page Mode Burst-Access Read Cycle
Fast-page-mode burst accesses for block transfers are
supported directly by the 82786 to take advantage of
the fast sequential addressing capability of DRAMs
(see Figure 5). Once the DRAM is set-up with the row
address, the column addresses can be quickly scanned
in for several burst-accesses to the same page. With the
82786, Fast Page Mode bursts for block transfers run at
twice the speed of page mode.
The following table shows the burst-access rate of these
various configurations for a 10 MHz 82786.
Interleaving of two banks of DRAMs is also supported
directly by the 82786. For a sequential burst access,
DRAM cycles for both banks can be initiated. Then,
during the burst access, the 82786 can alternate accesses between the two banks, thus cutting the effective
DRAM access time in half (see Figure 6).
Page Mode
Fast Page Mode
and Static Column
Noninterleaved:
10 Mbyte/ sec
(2 cycles)
20 Mbyte/sec
(1 cycle)
Interleaved:
20 Mbyte/sec
(1 cycle)
30 Mbyte/sec
(0.5 cycle)
The other cycle times, and speeds at 10 MHz, are the
same for all DRAM configurations:
Static Column DRAMs can also be used to get the
same performance as Fast Page Mode. The only difference between the two types is that Static Column
DRAMs do not latch the column address, whereas,
Fast Page Mode DRAMs do latch the column address
on the falling edge of CAS. In noninterleaved configurations, Static Column DRAMs can directly replace
Fast Page Mode. However, in an interleaved configuration, the column address must be latched externally for
Static Column DRAMs.
Single Reads
3 cycles
Single Writes
3 cycles
300 ns
300 ns
Read-Modify-Writes
4 cycles
400 ns
Burst-Access Set-Up
2 cycles
200 ns
Refresh
3 cycles
300 ns
All burst-accesses for block transfers· perform an even
number of 16-bit word accesses.
RAS~,
//--
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292007-5
Figure 6. Interleaved Fast-Page-Mode Burst-Access Read Cycle
10-106
inter
AP-270
Burst-accesses for block transfers are used by all Dis"
play Processor memory accesses except the operand for
LD_REG and DMP_REG commands. Block-read
accesses are used by the Graphics Processor for command-block fetching and to fetch the character fonts.
The Graphics Processor uses a block-read followed by a
block-write. for the read-modify-write operations of
BitBlt, Scan_Line, and Character drawing. All other
pixel drawing commands use single read-modify-write
cycles.
tions is handled internally by the 82786. This is also the
connections required for x 4 VRAMs which use the
BEN signal to control their OE/DT input which is
used to determine when to load their internal shift register (Figure 9).
If Static Column DRAMs are used in an interleaved
configuration, an external latch is required to latch the
column address for the second bank (Figure 8a). The
82786 can directly drive up to thirty-two DRAM devices. For configurations requiring more than thirty-two
devices, external buffering must be used.
3.1 DRAM Configurations
Up to 4 rows per bank, and 1 noninterleaved or 2 interleaved banks are supported (see Figure 7). Each bank
must always be 16 bits wide. If only one noninterleaved
bank is used, it must be bank 0 (using CASO and
BENO). If interleaving is used, both banks must have
the same number of rows. In either case, if only one
row is used, it must be row 0 (using RASO). For only
two rows, row 0 and 1 are used (RASO and RASI).
Similarly, three rows use row 0, I, and 2.
The 82786 can directly drive up to 32 DRAM/VRAM
chips. One 82786 pin shares two DRAM functions
DRA9/RAS3. These functions are never both used in
the same configuration. DRA9 is only used by 1M x 1
DRAMs, which limit the number of rows to only two
due to both addressing (4 Megabytes) and drive (32
chips) limitations.
Figure 8 shows a full connection diagram for thirty-two
64K x 4 DRAMs. Two interleaved banks of four rows
each are used. Unlike most DRAM/VRAM controllers, no impedance-matching resistors are usually needed between the 82786 chip and the DRAM/VRAM
chips. The impedance-matching for most configura-
DRAMs with separate data-in and data-mit pins (such
as the x 1 DRAMs) require a tristate buffer for the
data-out lines of each bank. (All of the rows within
each bank may share the same tristate buffer). Figure
10 shows a full connection diagram for thirty-two
256K x 1 DRAMs including the tristate buffers. Two
interleaved banks of one row each are used. This is a
special case for the RAS lines. Normally RASO would
drive all of the DRAMs in both banks for the one row
as in Figure 7. However, because the RAS lines have
drive capability for only 16 DRAMs, both RASO and
RASI are used. The 82786 recognizes this special case
and automatically drives RAS I identically to RASO.
The other special DRAM case is using two rows of x I
DRAMs in a noninterleaved configuration. This configuration has the advantage that only one bank of
transceivers is required, but burst access time is reduced by half from the previous example. Normally,
CASO would be used to drive all 32 DRAMs, but because of drive limitations, both CASO and CASl are
used, (one for each bank). Again the 82786 recognizes
this special case and automatically drives CASI identically to CASO.
WEH
CAS!
BEN!
RASS
--i ttl
--i
--i
--i
I
II
III
RAS2
III
RAS!
III
RAse
III
II
l-i
l-i
l-i
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II
WEL
CAse
BENe
ROW 3
III
ROW 2
II
II
ROW 1
II
DAHK 1
III
ROW
DAHK
I)
I)
292007-6
Figure 7. 82786 Supports up to 4 Rows of 2 Interleaved Banks of DRAMs
64K x 4 Video RAMs with 82876 1 Row, 2 Banks, 4 Bits/Pixel
10-107
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292007-9
inter
AP-270
The table in Figure II shows all the possible configurations for 64K bit, 256K bit and 1M DRAMs.
The critical parameters for Fast Page Mode and Static
Column DRAMs are generally:
Fast-page-mode
Single
Single wrt RMW
rd/wrt
rd/wrtlRMW
3.2 DRAM Timing Parameters
Trp
Trah
Tase
Care should be taken to ensure that all of the timings of
the DRAMs used, fit with those in the 82786 data
sheet. To make the comparisons easier, the names of
the parameter in the 82786 data sheet correspond to the
names in most DRAM data sheets. In addition, the
parameters have been broken into the same four groups
used by most DRAM data sheets.
The critical parameters for page mode DRAMs are
generally:
Single
Single wrt
rd/wrtlRMW
Teae
Trp
Tred
Trah
Tase
Ton
Trwl
Tewl
RMW
Page rd/wrt
Tds(rw)
Toft
Tds(i)
~
~
Tase
Tase
+
+
Tds(rw)
Toff
Tep
Teaa
Teap
Tds(n)
Teah(i)
Tds(i)
Tdh(i)
Ton(ri)
For interleaved Static Column DRAMs, the address
latch delay must be added to the DRAM parameters
corresponding to the row and column addresses. These
parameters are:
-Tasr
-Tasc
-Tcaa
Some of the 82786 parameters may not be found in all
Page Mode data sheets. If no corresponding DRAM
parameters for Tcaa or Tcar are specified, then the
82786 spec may be ignored. The reason is that, if no
such DRAM parameters exists, then the resulting minimum values for these parameters are at most:
Teaa
Tear
Trwl
Tewl
Teae
Trsh
Then as long as the Tasc, Tcac, and Trsh specs fit, the
82786 timings guarantee Tcaa and Tcar to fit.
A third parameter that may not be found in all Page
Mode data sheets is Ton. If x 1 DRAMs are used, the
external data transceiver is responsible for meeting this
and the DRAM is not required to meet this spec. If,
however, x 4 or x 8 DRAMs are used, without the data
transceiver, care must be taken to ensure that this spec
is met.
For all types of xl DRAMs, Page Mode, Fast Page
Mode and Static Column, the transceiver delay must be
added to the DRAM parameters which correspond to
read-data. These parameters are:
-Trac
-Tcac
-Tcaa
Notice that all of the 82786 DRAM timings are specified relative to the bus clock (eLK). This has two implications. First, a slower bus clock can be used to allow the 82786 to use slower DRAMs. Secondly, many
of the parameters are determined by the duty cycle of
the bus clock (as their specification is dependent on
clock high or low time). A slightly nonsymmetric
clock, such as the clock for the 80286, can be used for
the 82786 CLK, but care should be taken to examine
the effects on the DRAM timing. In some circumstances, it may be advantageous to use a slightly nonsymmetric clock.
Some of the specifications are relative to the 82786
clock period (Tc), while others are relative to a specific
phase (THigh, TLow).
10-111
AP-270
292007-10
Figure 10. Two Interleaved Banks of 256K x 1 DRAMs
1-row
Non-Interleaved
2-rows
3-rows
4-rows
1-row
Interleaved
2-rows
3-rows
4-rows
64Kx1
128K
16
256K
32
384K
48-
512K
64-
256K
32
512K
64*
768K
96'
1024K
128'
16Kx4
32K
4
64K
8
96K
12
128K
16
64K
8
128K
16
192K
24
256K
32
8Kx8
16K
2
32K
4
48K
6
64K
8
32K
4
64K
8
96K
12
128K
16
256K x 1
512K
16
1024K
32
1536K
48'
2048K
64'
1024K
32
2048K
64*
3072K
96*
4096K
128*
64Kx4
128K
4
256K
8
384K
12
512K
16
256K
8
512K
16
768K
24
1M
32
32Kx8
64K
2
128K
4
192K
6
256K
8
128K
4
256K
8
384K
12
512K
16
1M x1
2M
16
4M
32
-
-
4M
32
-
-
-
256K x4
512K
4
1M
8
1.5M
12
2M
16
1M
8
2M
16
3M
24
4M
32
128K x8
256K
2
512K
4
768K
6
1M
8
512K
4
1M
8
1.5M
12
2M
16
'Requires external buffering
Figure 11. Possible DRAM configurations for 64K, 256K and 1 Mbit DRAMs. The top number in each
box is total memory size in bytes, the bottom is the number of DRAM chips required.
Look at this example. Suppose you use 51C256H Fastpage-mode DRAMs with the 82786 as in Figure 10.
First, look at the critical parameters shown above.
Since it is not possible to create a precisely 50% duty
cycle clock, you must consider clocks with a few percent tolerance. The table compares the 82786 using several clock frequencies and duty cycle tolerances with two versions of the 51C256H. The table is
ordered with the tightest timings first.
From the table, you can see that the fast 120 ns access
DRAMs can be used with the 82786 with a 10 MHz
clock with as much as a 40%-60% duty cycle skew.
The slower DRAMs can be used at 9 MHz with a tighter 45%-55% duty cycle skew or at 8 MHz with a
40%-60% skew.
10-112
AP-270
292007-49
Figure 10. Two Interleaved Banks of 256K x 1 DRAMs (Continued)
82786 Specifications
Parameter
10MHz
45-55%
10 MHz
40-60%
51C256H DRAM Specs
9MHz
45-55%
8MHz
40-60%
-12
120 ns
-15
150 ns
Tdh
Min
Tph
22.5
20
25
25
20
25
Toft
Max
25.5
23
28
28
20
25
26.5
Tcah
Min
+3
Tch + 2
22
24.5
27
15
20
Tcp
Min
Tcl- 5
17.5
15
20
20
10
10
Tds
Min
Tcl- 8
14.5
12
17
17
0
0
T1
,
Tcaa
Max
2Tc - 27
73
73
83
98
55
70
Tcap
Max
2Tc - 21
79
79
89
104
60
75
Tasc
Min
Tcl- 5
17.5
15
17.5
17.5
5
5
Trp
Min
2Tc - 5
95
95
105
120
70
85
Trwl
Min
Tc - 9
41
41
46
53.5
25
30
Tcwl
Min
Tc - 12
38
38
43
50.5
25
30
+
Trah
Min
Tc
Ton
Max
Tc - 24
3
53
53
58
65.5
15
20
26
26
31
38.5
25
30
Because these x 1 DRAMs require transceivers between
their data outputs and the 82786, the transceiver delays
must also be considered. The two parameters in the
table above, that are affected are Tcaa and Tcap. The
transceiver delay must be added to the DRAM access
time for these parameters. This implies that the data-in
to data-out time of the transceivers must be 18 ns or
less for the 10 MHz -120 ns case and the 8 MHz
-150 ns case. The delay must be 28 ns or less for the
9 MHz -150 ns case and the 8 MHz -150 ns case.
3.3 Initializing the DRAM Controller
Two of the 82786 Internal Registers are used to configure the DRAM/VRAM Controller. Both of the regis-
ters are typically set once during initialization and then
never changed. The DRAM/VRAM Control Register
is set to indicate the configuration of the DRAMs/
VRAMs used. The DRAM/VRAM Refresh Control
Register is set to indicate the frequency of refresh cycles. Once programmed, the settings can be write-protected using the write-protect bits discussed in Section
4.2.
It is recommended that all fields of the DRAM/
VRAM Control Register be written simultaneously to
avoid illegal combinations. Also, no DRAM accesses
should be attempted until the DRAM/VRAM Control
Register has been set. For the configuration in Figure
10 using one row of 256K Fast Page Mode DRAMs in
two interleaved banks:
10-113
intJ
AP-270
DRAM/VRAM Control - Internal Register Offset OSh
15
7
RESERVED
6
5
4
3
2
1
0
IRW1: Rwol DCl : DCO I HT2: HTl : HTO
RESET DEFAULT:
D
1
0
I
0
I
DRAM!VRAM HEIGHT (SIZE OF DRAM CHIPS)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
aK ( 1 ROW,
0
1
16K (7 ROW,
0
32K ( 7 ROW,
1
64K ( a ROW,
0 12aK ( a ROW,
1 256K ( 9 ROW,
0 512K (9 ROW,
1
1M (10 ROW,
a
7
a
a
9
9
10
10
COLUMN)
COLUMN)
COLUMN)
COLUMN)
COLUMN)
COLUMN)
COLUMN)
COLUMN)
INTERLEAVE (1 = INTERLEAVED DRAM BANKS)
(0 = NONINTERLEAVED BANKS)
FAST PAGE MODE (1
(0
= FAST PAGE MODE DRAM)
= PAGE MODE DRAM)
DRAM!VRAM ROWS (NUMBER OF ROWS OF CHIPS CONFIGURED)
o
o
1
1
DRAM!VRAM CONTROL REGISTER
0
1
0
1
001 1 1 01
ONE ROW·
TWO ROWS
THREE ROWS
FOUR ROWS
=
292007-15
MHz 82786 CLK, we can determine the value for the
DRAMIVRAM Refresh Control register as follows:
lDH
Ul ll~L~;~~D
Refresh Count
FAST PAGE MODE
ONE ROW
=
Tref x ClK
_ 1
16 x Refresh_Rows
292007-16
DRAM!VRAM Refresh Control, Internal Register
Offset 06H, is set to 18 as shown below.
15
6 5 4 3 2 1 0
Reserved
RESET Default:
:
o
Re~res~ SC~lar:
o
0
o
The 82786 CLK input is internally divided by 16 and
then divided by the Refresh Scalar + 1 in the DRAM!
VRAM Refresh Control Register to determine the time
between refresh cycles. Only one row of each DRAM!
VRAM is refreshed at a time so refresh of the entire
DRAMIVRAM requires 128, 256, 512 or 1024 of these
refresh cycles depending on the number of rows in the
DRAMIVRAM.
For example, the 51 C256H DRAMs require a complete
refresh every 4 ms (Tref). These DRAMs consist of 512
address rows of 512 address columns. However, for refresh purposes, only 256 row addresses (AO-A7) need
to be refreshed within the 4 ms refresh time. The A8
input is not used for refresh cycles. (The 82786 maintains a full lO-bit refresh address, the upper 2 bits are
simply not used in this configuration). Assuming a 10
The result should always be rounded down, so the
DRAMIVRAM Refresh Control Register should be
programmed with 18. This result is dependent only on
the DRAMIVRAM type and the 82786 CLK frequency. The configuration of the DRAMIVRAM chips
does not matter.
There is a latency time between the refresh request generated by this count and the actual refresh cycle. The
refresh will always occur as soon as the current bus
cycle finishes. Refresh cycles can interrupt block transfers, but only at double-word boundaries. The worst
case is if a refresh request occurs just after the 82786
receives HLDA to begin a master mode block transfer.
The 82786 must complete two master cycles before the
refresh cycles can be performed. During this latency,
further refresh requests may be generated. The 82786
contains a refresh request queue that allows up to three
refresh requests to be pending. As soon as the bus is
freed, all queued refresh cycles will be run consecutively.
For the above example, refresh requests are generated
every 15.2 J-Ls which is derived using the following formula.
10-114
intJ
AP-270
.
16 x (RefreshCount + 1)
RequesLtlme =
ClK
BHE
MIO
1
1
0
0
1
X
Synchronous 80286 bus
Synchronous 80186 bus
Asynchronous bus
= 16 x (18 + 1) = 15.2 s
20 MHz
,...
The amount of latency that the DRAMs will tolerate
for each row is:
Allowed_latency = Tref- (RequestTime )( Refresh_
Rows)
= 4 ms- (15.2 ,...s )( 256) = 108.8 ,...s
But the real latency limit is that the 82786 allows only
three requests to be queued:
Maximum_latency = Queue_Size x Refresh_Time
= 3 X 15.2 = 45.6 ,...s
Therefore, the maximum number of wait-states allowed
for a 82786 master mode transfer is:
WaiLStates = «Maximum_latency x PClK) overhead)/bus-cycles
«45.6,...s x 10 MHz) - 7 cycles)/2 = 224
Clearly, in this situation, refresh latency is not a problem. If the system memory caused the 82786 to delay
over 224 wait-states for a master-mode access, not only
would DRAM/VRAM refresh be missed, but the display refresh would also be lost.
The 82786 always issues three refresh cycles following a
RESET. Besides these first three refresh cycles, the
82786 does not perform any other DRAM/VRAM initialization after cold or warm-reset. If the DRAMs/
VRAMs require other initialization cycles, the CPU
should either perform dummy cycles to the DRAM/
VRAM or wait until the refresh counter has requested
enough refresh cycles to occur.
For synchronous 80286 interfaces, the Reset and Clock
inputs into the 80286 and 82786 must be common. For
synchronous interfaces to 80186, the 80186 CLKIN
must be the same as the' 82786 CLK (so an external
clock source must be used). The RES input into the
80186 must meet a set up and hold time with respect to
the CLKIN. The RESET for the 82786 should ~en
erated from the RES (for 80186) by delaying RES by
one CLKIN cycle and inverting it. This ensures that
the 82786 phI is coincident with 80186 CLKOUT low.
These pin states are easy to achieve for the synchronous
modes. During RESET, the 80286 always drives BHE
high and MIO low.
CPUs with timings different from the 80286 must use
asynchronous mode (however, CPUs such as the 80386
can easily generate 80286 style timings). Care should be
taken in this case to ensure BHE is low during RESET.
In each of these three modes it is possible to configure
the 82786 to allow both master and slave accesses or to
simplify the logic to allow only slave access. In master
mode, the 82786 always generates 80286 style bus signals.
If the 82786 is used as a master, it will activate its
HREQ line when it needs to become the bus master to
access system memory. It waits until HLDA is received
and then begins driving the system bus. Once HLDA is
received, a 10 MHz 82786 can perform system bus accesses at the following rate (assuming 0 wait-states).
single reads/writes
4 cycles
read-modify-writes
6 cycles
burst-access read/write 2 cycles
If the DRAM/VRAM Refresh Control Register is set
to all ones, refresh cycles are disabled.
4.0 SYSTEM BUS INTERFACE
The 82786 system bus structure allows the 82786 to be
easily connected to a variety of CPUs. The 82786 can
act as both a slave and a master to the CPU's bus. As a
slave, the CPU or DMA can perform read and write
cycles to the 82786 Internal Registers or to the 82786
DRAM/VRAM. As a master, the 82786 Graphics and
Display Processors can perform read and write cycles
to the CPU's system memory.
The 82786 bus can operate in three different modes to
handle various CPU interfaces. The 82786 determines
which mode to use by sampling the BHE and MIO pins
during RESET:
5 Mbyte/sec
3.3 Mbyte/sec
10 Mbyte/sec
The 82786 will begin the first master bus access on the
cycle after HLDA is activated. The only delay is the
time between when the 82786 activates HREQ and the
system can release the bus and return HLDA. Most
synchronous CPUs require a minimum of three cycles
between the time HOLD is activated until they can return HLDA. The 82786 will keep HREQ activated until it no longer has more accesses to perform to system
memory (until either the next 82786 access is to the
dedicated graphics DRAM/VRAM or until neither the
Graphics or Display Processors require the bus.). Once
the 82786 is done using the system bus, it will remove
HREQ and is able to immediately access its Graphics
DRAM/VRAM on the next cycle.
10-115
intJ
AP-270
It is potentially possible for the 82786 to require the
system bus for a lengthy period of time. For example, if
the 82786 has been programmed to give the Graphics
Processor high priority, and the Graphics Processor executes a command that requires a lot of access to system memory, then the system bus could potentially be
held by the 82786 for several consecutive accesses.
Drawing a long vector into a bitmap residing in system
memory is such a command. In this case, the maximum
time the 82786 can potentially keep the system bus is
determined by the frequency of DRAM/VRAM refresh cycles programmed into DRAM/vRAM Refresh
Control Register.
If the CPU needs to regain control of the bus before the
82786 is done, it may remove HLDA eady. The 82786
will then complete the current access and remove
HREQ to indicate to the CPU that it may now takeover control of the bus. If the 82786 still requires more
access to the system bus, it will re-activate HREQ two
cycles after it had removed it and wait until the next
HLDA. Since the 82786 removes HREQ for only two
cycles, it is important that the CPU recognize it immediately. Otherwise a lock-out condition will occur in
which the CPU is waiting for the 82786 to remove
HREQ and the 82786 is waiting for the CPU to issue
HLDA. This is not a problem for the synchronous interfaces. Extra logic may be required to prevent this
situation if the 82786 is used as a master in an asynchronous interface and HLDA is ever removed prematurely, especially if the CPU clock is significantly slower than the 82786 clock.
4.1 Memory Map
Figure 12 shows the memory map as it appears to both
the 82786 Graphics and Display Processors. These
processors both use a 22-bit address which provides for
up to 4 Megabytes of address space. They are only allowed to make memory accesses so no I/O map is applicable.
3FFFFFh
SYSTEH
HEHOR't
GRAPHICS
HEHOR't
eeeeeeh '--______--'
292007-11
Figure 12. Memory Map for Graphics
and Display Processors
FFFFFFh
SYSTEH
HEHOR't
GRAPHICS
HEHOR't
] I NTERNAL REG I STERS
MA~ BE LOCATED IN
MENOR~ OR I/O SPACE
S'x'STEH
HEHOR't
000eSCh '--_ _ _ _ _ _- '
292007-12
Figure 13. Memory Map for System CPU
The 82786 dedicated graphics DRAM/vRAM always
starts at location OOOOOOh and grows upwards. The upper address depends on the amount of DRAM/VRAM
memory configured in the DRAM/VRAM Control
Register. The system bus memory begins where the
DRAM/vRAM ends and continues to the highest addressable memory location 3FFFFFh.
The memory map as it appears to the system CPU is
shown in Figure 13. The area that the 82786 Graphics
DRAM/vRAM is mapped into can be anywhere in the
CPU address space and is completely defined by the
address decode logic of the CPU system. Normally only
the space for the configured graphics memory is
mapped into CPU address space. If addresses above the
configured graphics memory are mapped into the CPU
address space, and the CPU writes to addresses above
the configured 82786 memory, the write is ignored. If it
reads from these locations, the data returned is undefined.
The 82786 Internal Registers may be configured to reside in memory or I/O address space. If configured to
reside in memory, then they will override a 128 byte
area of the 82786 memory address space for external
(CPU) accesses. The Internal Registers are only accessible by the external CPU and therefore are never found
in the 82786 Graphics or Display Processor memory
maps.
Suppose the 82786 is configured with 1 Megabyte of
Graphics DRAM/VRAM and is used in an 80286 system. A possible memory map and connection diagram
is shown in Figure 14. All of the 82786 memory is
m-" ~u
'139
, - - AI
88186
GRAPHICS
HEHORY
GRAPHICS
HEtiORY
\r-
0eee0h
..................... .... , ..
V .... ...................... ......
I-
SYSTEH
HEHORY
...
r - Ae
~; I.!!.!.IQ0 I-
MIlO
CS
.nl
.
174LS36~EI
I
1'119
1'118
MEN
82786
A21
1'120
1119
AIS
A17,e
A17,e
292007-17
Figure 16. Possible Memory Mapping for 80186/82786
Because graphics memory can be quite large, some sys·
tern designs might not allow all of the confignred
Graphics DRAM/VRAM to be directly mapped by the
cpu. For example, if the 82786 has 2 Megabytes of
Graphics DRAM/vRAM and is used with a 80186
processor, which can only address 1 Megabyte, then the
80186 can not directly access all of the 82786 memory.
In this case the CPU can be permitted to only access a
portion of the graphics DRAM/VRAM. Figure 16
shows a memory map and connection diagram for such
a system. Since the 82786 has two more address bits
than the 80186, a tristate buffer is used to supply the
two highest address bits when the 82786 is in slave
mode.
In many cases the CPU does not require access to all of
the graphics memory. For example, many situations
will not require the CPU to directly access the bit·
maps. If the CPU must gain access to the graphics
memory which is not directly mapped to the CPU, the
82786 Graphics Processor can be instructed (using the
BitBlt command) to move portions' of the Graphics
memory to and from the area accessible by the CPU.
Alternatively, the Graphics DRAM/VRAM areas can
be bank switched to allow the CPU direct access at any
portion of the graphics memory. Figure 17 shows the
use of an I/O port (74LS173 latch) to which the CPU
can write the highest 3 bits of the address for the 82786
slave accesses.
In both Figures 16 and 17, it is possible for the 82786 in
master mode to access the CPU memory addresses that
10·119
inter
AP-270
3FFFFFh
SYSTEM
MEHORY
20eeeeh
IFFFFFh
FFFFFh
SYSTEM
MEMORY
ce990h
IIFFFFh 82~!I.? ..1. H.'!'.~RH.~.I, .. R.E.G~
GRAPHICS
MEMORY
GRAPHICS
MEMORY
80900h
7FFFFh
SYSTEM
MEMORY
00geeh
000e00h
88186 M£HORY-MAP
82786 MEMORY-MAP
MilO
MIlO
CS
Lv-" -J
'139 ~~
--
88186
AI
A0
TO
I
QI
Q0
CPU~
MEN
74LS173OE
AIS
AIS
-l..OE
Q
D
Q D
AI?:0
-'367
II'
82786
A21
A2B
AI9
AI8
AI?:0
292007-18
Figure 17. Possible Memory Mapping for 80186/82786
Bank-Switching Allows 80186 to Access All 82786 Memory
correspond to the 82786 slave addresses. In this case,
the circuit will generate a 82786 chip-select, but the
82786 will not respond to this chip-select while it remains in master mode. As long as the READY logic
goes high (it may not since the 82786 will not perform
the slave-access) then the 82786 will complete the master-mode cycle. By the time the 82786 returns to slavemode, the chip-select will have gone away.
to control the system configuration (Figure 4). These
registers are normally set once during power-up intialization and never changed.
Two of these registers, DRAM/VRAM Refresh Control and DRAM/VRAM Control have already been
discussed in Section 3.3. The rest of the registers are
discussed in this section.
The Internal Relocation Register defines the location of
the 82786 Internal Registers anywhere in the 82786
memory or 110 address space.
4.2 BIU Registers
Within the 82786 Internal Register block, the registers
at offsets OOh-OFh are used by the Bus Interface Unit
10-120
inter
AP-270
Internal Relocation Register Orrset OOh
15
I
Reset:
14 13 12 11 10
9
8
7
B~eA~s
6
5
4
3
2
xxxxxx xxxxxxxxx
o
,
IMIlol
~
Base Address: detennines bilS 21:7 of the Internal Register Block
address (bits 6:0 of the address are used as the
offset).
o
0= VOMapped
1 = Memory Mapped
292007-86
After RESET, any CPU slave I/O address to the 82786
(which activates the 82786 Chip-Select) will access the
Internal Register Block. During initialization, a write
to the Internal Relocation Register should be performed to locate the Internal Register Block at specific
even byte memory or I/O address. Once the write to
the Internal Relocation Register occurs, the 82786 Internal Register Block no longer occupies alI of 82786 1/
o space, rather it is restricted to just the 128 memory
or I/O bytes specified. The Internal Registers can be
located anywhere accessible by the CPU. However, if
they are memory-mapped and located over configured
graphics memory, they will take precedence over the
memory for CPU accesses to those addresses. Graphics
or Display Processor accesses to these addresses will
still be directed to DRAM/VRAM. For example, writing the value of 03F8h locates the Internal Registers at
I/O addresses FEOOh - FE7Fh.
03F8h = 00 0000 1111 11100
I
I
0
SPL - Subsequent Priority Level - priority used for
processor to maintain bus. during a block
transfer. If a block transfer is interrupted, this
is also the priority used to regain the bus to
complete the burst access.
When a processor first requests' the 82786 bus, its FPL
value is used. The processor with the highest priority
gets access to the bus. Once the bus is granted, the first
access occurs. If a multiple-word block transfer is performed the SPL value is then used as the priority to
maintain the bus for subsequent cycles. As long as no
other processor of higher priority requests the bus, the
burst-access is alIowed to continue to completion. If a
higher priority request is made, the block transfer will
be suspended and the bus granted to the new request.
The suspended block transfer will not get the bus back
until its SPL value is again the highest priority request.
A separate register is used to program the priority for
each of the three processors. Because the External
Processor can not perform block transfers, no External
SPL value is required for it.
I
I/O mapped
Base Address OOFEOOh(offsets 0-7Fh)
Note that the address written to the Internal Relocation Register determines the memory or I/O address
that is required to be placed on the 82786 address pins
during a CPU access to the 82786 Internal Registers.
The actual CPU address used may be different, and is
dependent on the chip select and memory mapping logic described in Section 4.1.
There are four sources of requests for the 82786 bus:
- DRAM/VRAM refresh
- Display Processor
- Graphics Processor
- External Processor (CPU or DMA slave accesses)
TheDRAM/VRAM refresh requests are always top
priority. That is, once the DRAM/VRAM refresh request is made, the 82786 bus will complete the current
bus access and then perform the DRAM/VRAM refresh. Three BIU registers are used to set the priorities
of the other three bus requests. Two priority values are
used:
FPL - First Priority Level- priority used when processor first requests bus.
Display Priority - Internal Register Offset OAh
15
6 5 4 3
2
1
Reserved
I
FPL
o
RESET Default:
S PL
0
Graphics Priority - Internal Register Offset OCh
15
6 5 4 3
2
1
Reserved
RESET Default:
I FPL I
o
1
I FPL I
o
S PL
o
External Priority - Internal Register Offset OEh
15
6 5 4 3
2
1
Reserved
o
o
0
Reserved
RESET Default:
AlI of the priorities are programmable values from 0 to
7, with 7 being the highest priority. If two processors
10-121
AP-270
that are programmed with the same priority both request the bus, the priority in which the bus will be'
granted for the two will be (from highest to lowest):
- Display Processor
- Graphics Processor
- External Processor
the FIFO when the bus request is made. If the FIFO
drains completely before the bus has been granted, then
the FldColor Register value will be used from the current pixel through the end of the current scan line. The
TripPt may be programmed to 16 or 20 using the Display Processor LD_REG or LD_ALL commands.
There are two exceptions to these programmable priorities, If the CPU makes a slave request while one of the
82786 processors makes a master request, the CPU's
request will always be handled first by the 82786 regardless of priority settings, This is necessary to prevent
the lock-out situation where the CPU will not grant
HLDA until it completes the bus access to the 82786
and the 82786 will not complete th~ CPU bus cycle
until the higher priority master cycle completes. The
other exception is refresh cycles; they always will be
handled while the 82786 is in a HLDA loop,
The Display Processor also keeps busy during Blank
times. During Vertical Blank time it performs any command loaded into its Opcode Register. During Horizontal Blank time it loads a new Strip Descriptor if
necessary and begins fetching the first pixels on the
line. The descriptor fetch begins as soon as the last pixel
of the last line has been placed in the FIFO, If the
Display Processor priority is not high enough to allow
these fetches during Blank time, then again part of the
display can not be generated correctly and FldColor
will be used. Two bits in the Display Processor Status
Register can be used to determine if the Display Processor ever gets behind:
bit-5 - DOV -Descriptor Overrun - set if strip descriptor fetch does not complete by the time
horizontal blanking ends.
bit-4 - FMT - FIFO. Empty - set if the Display
FIFO empties.
The values programmed into these priority registers
should be selected carefully. There is a performance
penalty whenever a block transfer is interrupted. However, if block transfers are not interrupted, then it is
possible that one processor must wait a long time to get
the bus while another is finishing. A balance between
overall bus performance and maximum tolerable latency must be made.
For example, if the Display Processor is not given high
enough priority, it may not always be able to fetch the
bitmapped display data fast enough to keep up with the
CRT. When this happens, the Display Processor will
not be able to send the correct video data to the CRT
and will instead place the value in the FldColor Register on the VDATA pins. To prevent this, the Display
Processor can be programmed for the highest priority
(after DRAMlVRAM refresh).
The Display Processor internally contains a FIFO
which is used to buffer the bitmap data to be displayed.
The FIFO consists of 32-double-words of 32 bits each.
Each FIFO double-word contains the results of a 32-bit
fetch from the bitmap memory. A dQuble-word can
therefore contain as many as 32 pixels, or as few as 1
pixel (such as at window borders).
Display Control Processor Register Block 2. TripPt
Register controls when this FIFO is loaded, If the
TripPt value is set at 16, the Display Processor waits
until the FIFO is half empty (only 16 double-words
left) before it requests a new block transfer to reftli the
FIFO. The block transfer request will not end until the
FIFO is again full (although the blOCk transfer may be
interrupted by a higher priority request). If the TripPt
value is set at 20, the Display Processor will begin requesting a new block transfer after only 12 FIFO double-words are emptied (20 left remaining), A low
TripPt value generates fewer but longer block transfers
and therefore the overall Display Processor bus efficiency is increased. However, a low TripPt value also
requires that the bus latency be smaller. A low TripPt
value means that there are less double-words left in
Both bits are reset after reading the Status Register.
The setting of the External Priority Register can greatly
affect the performance of the external CPU when it
performs an access to the 82786. Unless the External
Priority is greater than the GraphicS Processor, whenever the Graphics Processor is busy with a command
stream that demands significant bus bandwidth, the
CPU may have to wait a significant amount of time
before it can complete an access to the 82786. The CPU
waits for the 82786 in the middle of a bus access until
the 82786 returns the READY signal. During this wait
time, the CPU will not be able to process anything,
including interrupts. Of course, if the application is
very graphics intensive and the CPU throughput is of
lesser concern, then the Graphics Processor can be programmed with a higher priority;
Use the following priority values during your initial design. Once the system is working properly, you may
wish to tweak the values for optimum performance.
The optimum values are dependent on the CPU and
video speeds as well as the CPU and graphics instruction mix and the window arrangement. In most cases,
these registers will be initialized once and never
changed, It may be advantageous in some specialized
applications to adjust these values when the application
changes modes.
10-122
FPL
SPL
6
6
Graphics Processor
2
2
External Processor
4
Display Processor
Trip Point
20
inter
AP-270
15
RESERVED
RESET DEFAULT:
6
5
4
3
VR
WT
BCP
GI
o
0
I I I I
0
2
0
0
0
0
I
WRITE PROTECTION 2
WHEN SET: ALL BITS OF
ALL BIU REGISTERS ARE
PREVENTED FROM CHANGING
DURING WRITES.
WRITE PROTECTION 1
WHEN SET: ALL BITS OF ALL
BIU REGISTERS ARE PREVENTED
FROM CHANGING DURING WRITES
EXCEPT WPl AND WP2.
DISPLAY PROCESSOR INTERRUPT
SET WHEN DISPLAY PROCESSOR ISSUES
AN INTERRUPT. CLEARED BY READ OF
THIS REGISTER.
GRAPHICS PROCESSOR INTERRUPT
SET WHEN GRAPHICS PROCESSOR ISSUES AN
INTERRUPT. CLEARED BY READ OF THIS
REGISTER.
EXTERNAL BUS SIZE
0=8 BIT BUS
1 = 16 BIT BUS
WAIT STATE FOR iAPX 186
0- MAX 1 (2) WAIT STATES
1 - MIN 2 (3) WAIT STATES
VRAM CONTROL
0- USING STANDARD DRAMS
1 - USING VIDEO DRAMS
The BIU Control Register contains a miscellaney of
bits.
After the BIU Registers have been initialized, the WPI
and WP2 bits can be used to protect all of the BIU
Registers (82786 Internal Register offsets OOh - OFh)
from being rewritten. This will prevent faulty software
from going wild and placing the 82786 into an unwanted state. Once WPI is set, the only way to change the
BIU registers is to reset WP I first. Once WP2 is set,
there is no way for the software to modify the BIU
registers until a 82786 hardware RESET is performed.
After the 82786 causes an interrupt, the GI and DI
interrupt bits are used to allow the software to determine whether the Graphics or Display Processor
caused the interrupt. It is possible that both of these
bits may be set if both processors have caused an interrupt by the time the interrupt handler reads this register. In this case, both interrupts should be handled by
the interrupt handler.
Although it is not absolutely necessary to allow the
82786 to interrupt the CPU, it is very desirable. Graphics Processor interrupts can inform the software when
292007-19
it has completed all the commands as well as to report
error conditions. Display Processor interrupts can inform the software when a new display field has begun.
A new command can then be loaded into the Display
Processor to be executed before the next display field.
This facilitates operations such as smooth scrolling and
blinking. The only hardware requirement to permit
82786 interrupts is that the 82786 INTR pin is tied to
one of the interrupt controller inputs.
Although the 82786 always uses 16 bits, the 82786 can
be used with both 8 and 16 bit processors. For an 8-bit
CPU, separate transceivers are required for the low and
high bytes to the 82786 (Figure 18). In both 8 and 16
bit modes, graphics memory may be accessed a byte at
a time. Although the 82786 internal registers may be
read a byte at a time, they all are considered to be 16
bits (even if some of the bits aren't used) and must
always be written in 2-byte even-word pairs. In 16-bit
mode, they must be written as a 16-bit word. In 8-bit
mode, first the lower (even-address) byte is written and
then the upper (odd-address) byte is written. With an 8bit processor such as the 8088, both of the following
assembly r~)Utines may be used to load the 16-bit BIUControl Register with AX.
10-123
AP-270
<}-
BHE
DEN
00188
Ae
~
~
SEN
/
-
DE
r---
Dls,a
'245
82786
L:f)
~
DE
D7:0
D7,e
'245
292007-20
Figure 18. 8-Bit CPU Uses Two Data Transceivers to Connect to 82786
mov
out
mov
inc
out
dX,BIUControl
dX,al
;write AL into low-byte of BIUControl
al,ah
dx
dX,al
;write AH into high-byte of BIUControl
or:
mov dX,BIUControl
out dX,ax
;write AX into BIUControl word
In 8-bit mode, an even-byte write to an 82786 Internal Register does not change any of the 82786 Internal Registers,
the data is simply saved until an odd-byte write to a 82786 internal register is performed. Then both the high and low
bytes are written into that register. In effect, the even-byte address is ignored and an odd byte write will write into
the register both the odd-byte data and whatever even byte data was last written, into the register address specified
by the odd-byte access. There is no limit to the amount of time allowed between the even byte and corresponding
odd-byte writes. An odd-byte write that is not preceded by an even byte will be ignored.
The 82786 always comes up in 8-bit mode after RESET. This means that a 16-bit CPU should change the BCP bit to
one. It must perform two byte-wide accesses to do this. The following initialization code can be used.
mov dX,BIUControl
mov al,30h
out dX,al
;write 30h into low-byte of BIUControl
xor al,al
inc dx
out dX,al
;write OOh into high-byte of BIUControl
mov dX,InternalRelocation
mov aX,03F8h
out dX,ax
;write 03F8h into InternalRelocation word
The 82786 is first placed in 16-bit mode (using two 8-bit writes), then the 82786 Internal Registers are located at the
desired address (which is done with a 16-bit write). Next, the DRAM/VRAM and priority registers should be
initialized. Byte-wide writes into the 82786 Internal Registers can not be performed while BCP ~ 1.
All the 82786 master mode operations are 16 bits wide independent of the BCP bit. This means that system memory
must be accessible 16-bits at a time if master mode is to be used. The WT bit is set to 1 on reset. The VR bit is reset to
o at reset.
10-124
infef
AP-270
4.3 80286 Synchronous Interface
The 82786 has been optimized for the 80286, which
minimizes the interface logic requirements. Figure 19
shows a 82786 connected synchronously to an 80286.
Much of the logic, such as the 82288, chip-select, and
ready, can be shared by the rest of the 80286 system.
This configuration allows both master and slave accesses. The data transceivers allow the 80286 to access the
82786 and graphics memory and the 82786 to access
the 80286 system memory. They also provide the isolation required to allow the 80286 to access system memory while the 82786 accesses graphics memory simultaneously. The tristate buffer 74LS367 is used to pull the
.80286 upper address lines, COD/INTA, LOCK and
PEACK to their proper states during master mode. If
any of these signals are not used by the rest of the
system, they need not be driven by a tristate buffer.
If master mode is not required, MEN will stay low and
three of the four gates driving the data transceivers can
be eliminated. Also, the tristate buffer, which is only
used in master mode, may be eliminated. HREQ should
be left open and the 82786 HLDA pin should be tied to
ground so that the 82786 will never enter master mode.
Both the 80286 and the 82786 internally divide-by-two
the CLK input and use both phases. For the 82786 to
run correctly with the 80286, these phases must be correlated correctly. This can easily be done by observing
the setup and hold times for rising RESET for both
chips (see 80286 data sheet specifications and 82786
data sheet specifications). The 82C284 chip will meet
this requirement.
Depending on the CLK speed and the type of DRAM/
VRAM used, the 82786 may have very stringent CLK
duty cycle requirements (see Section 3.2). It may not be
possible to use the internal oscillator of the 82C284
chip but it may be possible to use an external oscillator
to drive the 82C284 external clock (EFI) pin.
Clock skew between the 80286 and the 82786 should be
kept to a minimum so the chips should be placed as
close together as possible.
When the 82786 bus is free, the circuit in Figure 19
permits CPU slave accesses using 2 wait-states for
writes and 3 wait-states for reads. Using DRAMs/
VRAMs with slightly faster access times, the circuit in
Figure 20 permits both read and write slave accesses
using 2 wait-states. The 82C284 SRDY input is used
instead of ARDY. The 82786 SEN timing is such that a
minimum of 2-wait states are always generated for
writes but a minimum of 2 or 3 wait-states are used for
reads depending on the use of SRDY or ARDY. Notice
that with 2 wait-state reads, the SEN signal must be
qualified with CS so that SEN does not extend into the
cycle following the slave write. The most critical relationship to be satisfied in order for 2 wait-state writes
is:
Tcac < Tc + Tch - 15 - 45
For a 10 MHz 82786 the DRAM/VRAM column access time must be:
Tcac < 50 + 25 - 45
=
30 ns
Note that x 1 DRAMs have two transceiver delays.
10-125
inter
AP-270
The critical timing calculations for slave mode are calculated as follows. The actual numbers calculated are for an
80286/82786 system running at 8 MHz.
chip-select-logic
<
<
<
<
ready-logic
(if ARDY is used
as in Figure 19)
<
<
<
<
ready-logic
(ifSRDYis used
as in Figure 20)
<
<
<
<
read data valid 2 82786.Ts22
+
path from 80286 address to 82786 CS pin
2 X clock period
address valid
286.T13
2 X 286.T1
2 X 50ns
35 ns
60 ns
path from 82786 SEN to 82C284 SRDY pin
clock period
SEN active
286.T1
82786.S18
25 ns
50 ns
25 ns
path from 82786 SEN to 82C284 ARDY pin
clock period
SEN active
286.T1
82786.S18
SOns
25 ns
10 ns
from SEN active to read data valid
transceiver delay
from SEN active to write data valid
setup
82786.Tsl
5 ns
ARDY setup
82C284.T13
Ons
SRDYsetup
82C284.T11
15 ns
write data valid 2 82786.Ts20
The master mode signals generated by the 8278'6 are all within the specification range guaranteed by the 80286. In
other words, if the system memory is designed to function with the 80286, it will also be able to function with the
82786. The only signals that may not be within the range of the 80286 specifications are the data bus signals due to
the transceiver delays. Care must be taken to ensure that the memory subsystems that the 82786 is to be able to
access in master mode can meet these more stringent requirements:
read data setup
>
>
>
write data valid
<
<
<
data valid to falling clock after Tc phase 2
+
transceiver-delay
82786 read data setup
+
data in to data out
82786.T8
5 ns
+
Tprop
data valid delay from falling clock after Ts phase I
82786 write data valid
transceiver delay
82786.T14
data in to data out
40 ns
Tprop
The clock skew between the 80286 and the 82786 must be considered in all these calculations.
10-126
t
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292007-21
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292007-22
AP-270
4.4 80186 Synchronous Interface
The 82786 supports a synchronous status interface to
the 80186. The 82786 bus clock and the 80186 x 1
Crystal Input must be driven with the same external
clock (EFI). The Reset inputs to the 82786 must be
generated from the RES for the 80186 by delaying it by
one clock (input). This guarantees that the 82786 Clock
phase 1 is coincident with 80186 CLKOUT low. A synchronous 80186 interface is selected ifBHE is high and
MIO is high prior to falling 82786 RESET.
Generally this configuration will be used with a minimum of 3 wait states for the 82786 slave read and write
accesses. Therefore the WT bit in the 82786 BIU Control Register should be set. The 82786 slave accesses
will then only be initiated when the 82786 CS is actually activated.
There is, however, a way to allow this interface to use a
minimum~f 2 wait states (set WT = 0). Rather than
wait for CS to go active, the 82786 can be allowed to
request a slave access as soon as the 80186 status lines
go active. If the 82786 is not in the midst of another bus
cycle and the CPU request is the highest priority, the
bus will immediately be granted to the CPU and a bus
cycle started. If the CS then goes active the 82786 can
complete the access within 2 wait-states. If CS does not
go active (because the 80186 is not accessing the 82786
but rather its own memory or I/O) then the 82786 will
abort the bus cycle by running a dummy 82786 bus
cycle.
If there is other RAM or ROM in the system besides
the 82786 graphics DRAM/VRAM that the 80186 often accesses, then this 2 wait-state will probably hinder
rather than help performance. Every time the 80186
fetches from its own system memory (such as an opcode fetch or operand access), and the 82786 bus is idle,
the 82786 will waste time running a dummy cycle. Fortunately, the busier the 82786 bus is, the less likely it
will be free when the 80186 initiates a bus cycle, and
therefore the less likely the 82786 will waste time running a dummy cycle.
4.5 Asynchronous Interface
An asynchronous interface can be used to interface the
82786 with nearly any CPU. The CPU clock and the
82786 clock are independent and may run at different
speeds. If the 80286 is connected asynchronously with
the 82786 and both processors are run at approximately
the same clock frequency, then the minimum possible
wait-states is one more than for the corresponding synchronous mode.
Figure 21 shows a slave-only 10 MHz 82786 interface
to an 8 MHz 80186. At 10 MHz, the 82786 r~res
that the address becomes valid S17 = 80 ns after RD or
WR falls and remains valid for S16= 130 ns. Because
~80186 address disappears the same cycle RD and
WR fall, the address must be latched. This latched address can be shared by the other components on the
80186 bus.
Due to the indeterminate phase relationship between
the CPU and 82786 clocks, care must be taken to ensure the read/write data timings have enough slack.
When the read data is sampled, and when the write
data is removed is determined by the CPU's ARDY
input. The 82786 SEN signal is used to generate the
ready signal which ensures that the data is indeed available. D-flip-flops can be used to delay the SEN signal to
delay the CPU Ready signal. For a 10 MHz 82786:
from SEN active to read data valid
read data valid;;:: 82786.Ts22 + Tprop
from SEN active to write data valid
write data valid;;:: 82786.Ts20
To initially place the 82786 into the asynchronous interface mode, the 82786 BHE pin must be low during
the fallin~e of RESET. To ensure this, the 74LS373
latch for BHE is tristated and an open-collector inverter pulls down BHE during RESET.
The 80386 processor can be interfaced to the 82786
either synchronously or asynchronously. For a synchronous interface, standard logic can be used around
the 80386 to emulate a 80286 style bus for use with the
interface described in Section 4.3. IIi this configuration
the 82786 bus would run at half the clock rate of the
80386 (a 16 MHz 80386 would run with an 8 MHz
82786 bus). For an asynchronous interface, the standard local bus controller logic used by the 80386 to
interface most peripherals can be used (Figure 22).
Although the actual bus transfers of a synchronous bus
are faster than for an asynchronous bus, there are cases
where an asynchronous interface provides the highest
performance. For example, for a given display resolution, the Display Processor overhead of a 10 MHz
82786 is a lower percentage of the total bus throughput
than for an 8 MHz 82786. If the 82786 is used with a 16
MHz 80386, then an asynchronous 10 MHz 82786
would have more bandwidth for the CPU and Graphics
Processor than a synchronous 8 MHz 82786 and therefore CPU accesses, generally, will be completed faster
with the asynchronous interface.
10-129
l
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82786 DRAM/VRAM
292007-25
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82786 DRAM IV RAM
292007-85
intJ
AP-270'
4.6 Multiple 82786 Interface
For higher performance, it is possible to use several
82786 chips in the. same system. Any of the above
CPU/82786 interfaces can be used to attach multiple
82786s to one CPU in the system. Each 82786 will require its own separate DRAM/VRAM array.
The driving software for these multiple CPUs would
most likely be sending nearly the same commands to all
of the 82786s. Rather than forcing the software to write
commands to each 82786 individually, it is possible to
allow write commands to go to several or all the
82786s. One method of determining which 82786s
should receive the write command would be to first
write to an I/O port in which each bit corresponded to
a different 82786. In Figure 23, the port bits set to 0
enable the corresponding 82786 for CPU writes. When
a write to 82786 address-space occurs, all of the selected 82786s are chip-selected. The CPU will then wait for
READY from all the selected 82786s before completing
the bus cycle. In this manner, one, all, or any combination of 82786s can be written into at once.
Because it is impossible to read from several 82786s at
once, a priority scheme is used on the I/O port to allow
a read from only one of the selected 82786s. The circuit
in Figure 23 only allows slave-accesses, the 82786s may
not enter master-mode.
If master-mode operation of the multiple 82786s is desired, each 82786 must access the bus separately. A
priority scheme is used to determine which 82786 is
awarded the bus when the CPU issues HLDA. With
only two possible 82786 masters, the random circuitry
to hold one 82786 off the bus while the other is using it
is straight-forward (Figure 24). With more 82786 masters, it is more feasible to use a state-machine (possibly
implemented in PALs) to perform the arbiting.
ed to allow a color look-up table or to trade-off the
number of bits/pixel for higher display resolutions, or
to use VRAMs.
Some of the possible display configurations are shown
below. The calculations assume a 60 Hz refresh rate.
High resolution CRTs are often run at a slower rate,
which permits the 82786 to generate significantly higher resolutions than those in the following table. All eases assume a CRT horizontal retrace time of 7 ,....s, except the 512 X 512 X 8 (10 ,....s) and 640 X 400 X 8
(13 ,....s) cases.
With Standard DRAMs
Non·
Interlaced
Interlaced
8 Bits/Pixel (256 colors)
512 X 512
640X400
640X480
900X675
4 Bits/Pixel (16 colors)
870X650
1290X968
2 Bits/Pixel (4 colors)
1 Bit/Pixel
(monochrome) .
1144X860 1740X1302
11472X 1104 2288 X 1716
Multiple 82786s can be used together to generate even
higher resolutions with more colors. For example, two
82786s allow a non-interlaced 1144 X 860 sixteen color
display.
With Video DRAMs'
Non-Interlaced
8 Bits/Pixel (256 colors)
4 Bits/Pixel (16 colors)
2 Bits/Pixel (4 colors)
1 Bit/Pixel (monochrome)
1024
2048
2048
4096
X 1024
X 1024
X 2048
X 2048
'For 64K by 4 - with 256K by 4 higher resolutions are supported
5.0 VIDEO INTERFACE
5.1 Various CRT Interfaces
The video interface connects the 82786 to the video
display. The 82786 is optimized to drive CRT monitors
but may also be used to drive other types of displays.
Because CRTs provide an inexpensive. method of generating moderate and high resolution, monochrome and
color displays, this application note will concentrate on
CRT interfaces. Section 5.10 briefly describes other display interfaces.
.
CRT monitors use a wide variety of interfaces. Some
use TTL-levels on all inputs, others require analog inputs. Some use separate color inputs (red, green and
blue) and separate horizontal and vertical sync while
others require that some or all of these signals be combined into composite signals. This application note will
concentrate on the generation of separate color and
horizontal and vertical sync signals. Standard techniques can be used to convert these separate signals into
composite signals to meet the requirements of other displays.
The video interface for a CRT is very dependent on the
CRT requirements and the resolution and depth (bits/
pixel) of the image desired. The 82786 can be programmed to directly generate all the CRT signals for
up to 8 bits/pixel (256 color) displays at video rates up
to 25 MHz. In addition, external hardware can be add-
The video clock (VCLK) required 'by the 82786 may be
generated by a simple oscillator with TTL-outputs. Alternatively, the VCLK can be tied to the bus clock
(CLK) (or any other available clock) if they are to run
at the same speed..
10-132
infef
AP-270
~
f-\i~
:=-=-=-=-=-=-=-============:
~U
,--------------------------vv;i
ri~f t-= =.,~
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g
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'----------------~
Figure 23. This Configuration Allows Several 82786s to be Written by
80286 Simultaneously-Only Slave Accesses are Supported
10-133
inter
AP-270
-
Figure 24. Two 82786s Connected to 80286, Permits Slave and Master Accesses
10-134
inter
AP-270
I
VIDEO
CLOCK
GEHERA1UR
J
I
VCLK
HS'lNC
HSYNC/WSO
VSYNC/WS1
VSIINC
BLAI~K
BLANK
82786
CRT
IHTERFACE
'JDATA3
INTENSITII
')DATA2
VDATAI
RED
LJDATAO
BLUE
GREEI~
292007-28
Figure 25. 82786 Can Directly Drive TTL-Input CRT Interface
I
VIDEO
CLOCK
GEHERA1UR
I
')CLK
HSYNC/WSO
D
Q
HS'lNC
VSYNC/WS1
D
Q
LJSIINC
BLANK
D
Q
BLANK
UDATAS
D
VDATA2
,)DATAI
DFLIP/FLOpQ
Q
D
VDATAO
D
82786
CLK
748374
Q
a
CRT
IHTERFACE
INTENSITII
RED
GREEN
BLUE
292007-29
Figure 26. Buffer Used to Drive TTL-Input CRT Interface
5.2 CRTs with TTL-level Inputs
5.3 CRTs with Analog Inputs
The simplest interface is to CRTs that use TTL-level
inputs. The 82786' can generate these signals directly
(Figure 25). However, the drive requirements of the
CRT and cabling may make it necessary to buffer the
signals (Figure 26). The example monitor in both of
these cases happens to use a CRT that uses four-bits of
color information per pixel. This means that 16 different colors are available and the CRT can use the 82786
1,2, and 4 bits/pixel modes but can not take advantage
of the 8 bit/pixel (256 color) mode. A monochrome
monitor with only one TTL-level input could be connected directly to VDATAO and use the 82786 1 bit!
pixel mode but it then can not take advantage of any of
the higher bit/pixel modes.
Taking advantage of the 8 bit/pixel mode of the 82786
usually requires using a CRT with analog inputs. Signals for color CRTs with three separate analog video
inputs, (red, green, and blue) can be generated using
three digital-to-analog converters (Figure 27). Often
these digital-to-analog converters can be constructed
using simple resistor ladders (Figure 28). With 8 bits/
pixel, usually three bits are used to select red, three for
green and two for blue. This is because our eyes are
much more sensitive to variations of red and green than
of blue. These configurations can take advantage of all
the 82786 modes; 1, 2, 4, and 8 bits/pixel.
The VDATA pins may be assigned to the three colors
in any manner desired. In Figure 29 they are assigned
so that a variety of colors are available for each mode
(1, 2, 4, and 8 bits/pixel).
10-135
inter
AP-270
I
VIDEO
CLOCK
GENERATOR
J
I
VCtK
HSYNC/WSO
VSYNC/WS1
BLANK
HSIINC
USIINC
BLANK
I LEVEL I
I SHIFTER I
VDATUl
VDATA3
82786 l'DATA6
I
I
D/A
I
I
GREEN
UDATAI
l'DATA4
UDATA?
I
I
D/A
I
I
RED
IJDATA2
VDATA5
J
D/A
I
I
BLUE
CRT
INTERFACE
292007-30
Figure 27. Analog CRT Interface Allows 256 Colors
I
VCtK
HSYNC/WSO
VSYNC/WS1
BLANK
VDATA9
UDATA3
82786 UDATA6
VIDEO
CLOCK
GENERATOR
I
I
HSIINC
USIINC
BLANK
LEVEL
J SHIFTER
.~
2R
4F
1
T
r-
GREEN
CRT
INTERFACE
.~
UDATAI
UDATA4
UDATA?
--<2F
VDATA2
'JDATA5
2F
4F
1
T
.~
-.t-
ANALOG
RED
BUFFER r-
r-
BLUE
292007-31
Figure 28. Resistor-Ladder Used for 01 A
10-136
inter
VDATA7
AP-270
VDATA6
VDATA5
VDATA4
VDATA3
VDATA2
VDATA1
VDATAO
Figure 29. VDATA Pin Assignments
-
The most-significant Green bit is connected to
VDATAO so that in the one bit/pixel mode this bit
is controlled while the other bits are set to a constant level by the padding register internal to the
Display Processor. If, for example, the padding bits
are all set to zero, then a green and black image is
shown in one bit/pixel windows.
- With two bits/pixel the most significant Green and
Red bits are controlled while the rest are padded to
a constant value. If, for example, the padding bits
are set to zero then the colors black, green, red, and
yellow are available in two bits/pixel windows.
- Four bit/pixel windows contain two Green bits and
the most significant Red and Blue bits making 16
colors available.
- Eight bit/pixel windows allow control of all eight
bits to make all 256 colors available.
5.4 Using a Color Look-Up Table
Color Look-up Tables, also known as Video Palette
RAMs, allow more colors to be available with a minimal of actual bits/pixel and thus a minimal amount of
display memory is required for the bitmap. For example, in a system using 16 bits of color information,
65536 different colors are possible. In such a system it
is rarely necessary to display all 65536 colors on the
screen simultaneously. It may be feasible to support a
maximum of 256 colors simultaneously, providing that
these 256 selections can be any combination of the
65536 available colors. Color look-up tables permit
such a cost-effective system.
A block diagram of such a system is shown in Figure 30
and Figures 30a and 30b show actual circuits. The color look-up table can be loaded with up to 256 l6-bit
colors. In this wayan 8-bit/pixel bit-map can be used
to control the l6-bit colors.
The host CPU is responsible for loading the l6-bit colors into the look-up table. To load a color into a specific location in the look-up table, the 82786 Display
Processor can be programmed to output the 8-bit address on the 8 VDATA pins during the horizontal and
vertical blank times or on RESET by setting the Default Video Register. Then the CPU can load the color
value into the l6-bit latch.
The circuitry in Figure 30 wiII then automatically write
the l6-bit value into the look-up table during the next
horizontal sync time. The CPU should generate the
74AS373 latch enable input so that the latch can be
mapped into memory or I/O space and loaded by a
CPU write. The register between the 82786 and the
Palette RAM is used to allow the use of a RAM with a
slower access time. This register is not necessary if a
faster RAM is used.
The CPU program should wait until the color is loaded
into the look-up table before loading the next color.
One way to ensure this is to route the LookupLoading
signal through a port which the CPU may poll. Sample
assembly language code for this configuration follows
this section. Another way is for the CPU program to
delay a sufficient amount of time to ensure that HSync
has occurred before writing the next value.
Hybrid circuits can be used which combine the functions of the look-up table, analog-to-digital conversions,
and voltage shift for composite sync signals into one
package. Figure 30b shows such a configuration. This
particular hybrid circuit internally contains a 16 X 12bit look-up table, 4 bits for each red, green, and blue.
r---~:::U~C~L;K~============~====~==~======~~~
__Q}f-----I
____-J
r.-------------------------------l
BLANK I.-;:::;=::::===;-__~====j__:_--~
BLANK
I
eLK
HSYNC/WSO
HSl'HC
VSYNC/WS,
US'NC
f-----l
82786
CRT
IHTERFACE
FLIP/FLOP
VDATA7:
a
D15:8
Q1S:8
VIDE01S: B
292007-32
Figure 30. Block Diagram of Color Look-Up Table Used to Generate 16 Video Bits From 8
10-137
inter
AP-270
UCLKt~======l==========================={i~~~~~____~
HSYHC
USYHC
82786 BLAHK MT====j====:---~r==~==:=:l_:_--_:~~~i;~~:_--~1 BLAHK
UDATA7,e
HSYNC/WSO
VSYNC/WS1
H--------+-----------------------------j
CRT
IHTERFACE
VIDEOls,e
BIT
DATA
16
CPU IHTERFACE
292007-33
Figure 30a. Circuit for Color Look-Up Table Used to Generate 16 Video Bits From 8
VCLKr-----------~~:_----~------------~===;~_,
HSYNC/WSO f---~------\
VSYNC/WS11--_+-_ _--I
82786
)-------------------jSYNC
BLAHK f----t-----.....,~-----------------------j
CRT
IHTERFACE
VCLK
BLANK
RED VIDEO
1 - - - - - 1 GREW VIDEO
VOATA7:0 !==+:]8C§B!i1IT:§:S::::j~===========~ P7:0 INTEL
.-------j
BLUE VIDEO
81C38
R/W PALETIE
DAC
A07:0
DATA
CPU INTERFACE
292007-34
Figure 30b. Hybrid Color Look-Up Table and DAC Simplifies Interface
10-138
intJ
AP~270
Wait:
in
test
jnz
mov
mov
mov
out
al,StatusPort
al,LookupLoadingBit
Wait
ax,EightBitAddr
DefaultVDATA,ax
aX,SixteenBitColor
LookupLatch,ax
The look-up table is loaded by first writing the location
into the 82786 DefaultVDATA register. Then a 4-bit
color value is loaded into the latch along with color-select information. Therefore, in one load it is possible to
place this 4-bit color value into any combination of the
red, green, and/or blue tables.
5.5 Using the Window Status Signals
A graphics system design may require that the video
data bits for different windows be interpreted in different ways. For example, the attributes controlled by various video data bits may need to be changed between
windows for different tasks or number of bits/pixel.
For these reasons, two Window Status bits are available
externally which reflect a value which may be individually programmed for each window. These two pins always reflect the window which the display is currently
scanning. The software is responsible for placing the'
two bit values for each window in the Tile Descriptor
list.
In addition, the cursor can be programmed with a value
for the window status bits which can be programmed to
override the status bits from the windows for the portion of the display where the cursor resides.
The Window Status bits are multiplexed onto the
HSync and VSync pins. Since they are only applicable
during the visible display time, and since HSync and
VSync are only applicable during the non-visible display time, Blank can be used to de-multiplex these pins
(Figure 31).
A mode bit (bit 4 of CRTMode) in the Display Processor enables the Window Status bits so they become
multiplexed onto the HSync and VSync signals. This
bit must be set when the Window Status signals
HS\lNC/IJSe
are used. In systems where the Window Status bits are
not needed, this bit can be reset so that the HSync and
VSync pins remain low during the visible display. This
allows simpler systems to use HSync and VSync directly eliminating the need to AND these pins with Blank.
As an example, suppose the interpretation of the video
data bits by a color look-up table was to be different for
different windows. Possibly four different look-up tables are required for four different types of 8 bit/pixel
windows. A large look-up table (1024 words) could be
divided into four areas, one for each of the window
interpretations. Then the Window Status bits could be
used to select the area of the look-up table to be used
for each specific window. Essentially four look-up tables would be available, one for each of four different
types of windows. Figure 32 illustrates such a system.
The system also requires circuitry to load the look-up
table such as that in the previous section. Note that the
look-up table's Window Status inputs must be generated directly from the CPU when the RAM is to be loaded since they can not be programmed in specific states
during the blank time as the VDATA pins can.
Another use of the Window Status bits is to allow 1, 2,
4, and 8 bit/pixel windows to each use a different lookup table along with a fifth look-up table for the cursor.
A 1024 word look-up table above could be split up into
four areas as above. Two of the areas can be used for
two separate 8 bit/pixel look-up table and the other two
shared by the I, 2, and 4 bit/pixel windows for two
separate look-up table for each of I, 2, and 4 bits/pixel
(Figure 33). The padding bits can be used to sub-divide
this second area into separate tables for 1, 2 and 4 bit/
pixel windows. Finally, this same table could also be
used for twelve look-up tables, four each for 1, 2, and 4
bit/pixel windows.
rLJ
rLJ
VSIINC/lJSl
82786
;read port
;test LookupLoading bit
;wait til last load completed
;get 8-bit value to load
;make 82786 output during BLANK
;get 16-bit color
;write color into latch
BLANK
4
"
.r
IoIINDOIJ
STATUS
HSIINC
VSIINC
BLANK
CRT
IHTERFACE
292007-35
Figure 31. Using Blank to De-Multiplex Window Status
10-139
intJ
AP-270
HSYHC
USYNC
BLAN"
CRT
I HTERFACE
292007-,36
Figure 32. Four Color Look·Up Tables-Selectable by Window Status Outputs
FFh
FFh
FFh
FFh
ISh
I~h
8 BIT/PIXEL
8 BIT/PUCEL
PALE1TE 1
PALETTE 2
ISh
1 Bn/PUCEL
ISh
PALETTE I
I4h
1 BlT.tPUCEL
PALETTE I
ISh
2 BIT/PIXEL
PALETtE 1
ISh
SFh
PALETTE 1
UIEUPORT STATUS 99
; UIEUPORT STATUS 91
4 "BIT/PIXEL
PALETTE I
4-BIT/PIXEL PAD: e0e9X>O:XX'b
9Sh
aah
B6h
2-BlT/PIXEL PAD: e99109XXh
ISh
9Fh
4 BIT/PIXEL
a9h
I-BIT/PIXEL PAD: 9001818XI)
2 BIT/PIXEL
PALETTE 1
VIEWPORT STATUS. 11
VIEUPORT STATUS 18
292007-37
Figure 33. Window Status and Padding Bits Allow Two Separate Look-Up Tables for
Each of 1, 2, 4, and 8 BIt/Pixels
I
I
58
MHz
CLOCX
GENERATOR
UCLK
a--.J
a,
HSYNC
D
Q
USYNC
D
Q
BLANK
HSYNC/WSO
{>-D
D
VSYNC/WS,
BLANK
82786
UDATAa _ D
UDATAI _ D
UDATA2 _ D
UDATAS _ D
CLK
Q - IA
Q-
2A
Q-
aA
Q-
4A
FLIP/FLOP
Q~ IB
UDATA4 _ D
_
D
Q - 2B
UDATAS
Q - aB
unArAS _ D
UnATA? _ D
Q-
4B
CLK
CRT
A/B
IHTERFACE
FLIP/FLOP
IV_D
2Y _ D
av _ D
Q
INTENSITV
Q
RED
Q
GREEN
4V ' - - - D
Q
BLUE
2, I NUX
292007-38
Figure 34. External Multiplexer Allows Up to 50 MHz Video with 4 Bits/Pixel
10-140
inter
AP-270
5.6 Higher Resolutions with
Standard DRAMs
HFldStp, and LineLen registers are programmed for
half the number of dot clocks (because the 82786
VCLK is half the speed of the pixel dot clock).
The Video Clock rate on the 82786 can be a maximum
of 25 MHz. For a non-interlaced display refreshed 60
times per second this limits the resolution to 512 X 512
or 640 X 400 or equivalent displays. 640 X 480 can
also be achieved using a CRT with fast horizontal retrace. Still, some graphics system designs may require
more detailed displays and therefore more resolution. It
may very well be cost-effective to trade-off the number
of bits/pixel for higher resolution. This is especially
true in the case of monochrome displays where 256
grey-shades are not required but high resolution is.
The Strip and Tile Descriptors list also change only
slightly. Windows are programmed for same number of
bits/pixel and FetchCount as they would be for non-a~
celerated modes. However, windows may only be POSItioned horizontally to start on even pixel boundaries.
That is, they may only start at every-other pixel, not at
any pixel as permitted with non-accelerated modes.
This is because both an even and odd pixels are output
on the VData pins simultaneously and it is not possible
to mix windows during a single VCLK. The only valid
values for the start/stop bits are listed in the following
table. Notice that the Accelerated Modes do not permit
all possible bitmap depths because fewer than 8 bits/
pixel are available to the display.
The 82786 allows this trade-off to be made very effectively. Figure 34 shows how a video data rate of up to
50 MHz may be obtained with 4 bits/pixel (16 colors).
The 82786 is used to output 8 bits of video data at a
25 MHz rate. The external multiplexer switches between the low 4 bits and the high 4 bits at a rate of 50
MHz. The register before the multiplexer is used to
ensure that enough set-up time is provided for the multiplexer. The register after the multi~l~xer ensure~ th~t
the video data out has smooth transItIOns. The CIrcUIt
uses an inverter and one register stage to divide the 50
MHz clock by 2 to create the 25 MHz video clock for
the 82786. Instead of a multiplexer such as the 74S157,
a 74AS298 chip could be used which contains the multiplexer and the register iIi the same package.
The software has a minimum number of changes. The
Graphics Processor is programmed identically and manipulates the bitmaps in the conventional. man.ner (~l
though it does not make sense to use 8 bIts/pIxel bItmaps since they cannot be displayed). The display processor programming is slightly different. The Accelerated Video control bits (CRTMode bits 1,0) are set for
High Speed video (01). The HSynStp, HFldStrt,
Bitmap Depth
1 bit/pixel
None
(25 MHz)
Vertically, the windows may still be positioned at any
pixel. The programming of the one pixel horizontal and
vertical borders also does not change.
High-Speed video mode also requires that the Field
windows are programmed with half the number of actual pixels for the pixel count (BPP/Start/Stopbit) register which again restricts horizontal positioning to a
two pixel resolution.
The horizontal cursor position is programmed as half
the actual value so the positioning is also restricted to a
two pixel resolution. Vertically, the. cursor is p~o
grammed as normal. Since the cursor IS only a 1 blt/
pixel region, every other horizontal pixel reflects only
the cursor padding value so although simple cursor patterns are possible, arbitrary shapes are not possible with
the box cursor. For this reason, the programmer may
wish to create the cursor in software when using these
high-resolution modes rather than use the 82786 hard-
High-Speed
(50 MHz)
Very-High-Speed
(100 MHz)
Super-High-Speed
(200 MHz)
Start Bit
Stop Bit
Start Bit
Stop Bit
Start Bit
Stop Bit
Start Bit
Stop Bit
0-15
0-15
odd
even
15,4,7,3
12,8,4,0
15,7
8,0
15,7
8,0
2 bit/pixel
odd
even
15,11,7,3
12,8,4,0
4 bit/pixel
15,11,7,3
12,8,4,0
15,7
8,0
8 bit/pixel
15,7
8,0
-
-
10-141
AP-270
ware cursor. The crosshair cursor works well in Accelerated Mode, although the horizontal and vertical lines
become two pixels wide and horizontal positioning is
also limited to two pixels.
The timing in Figure 35 is very tight and the circuit
may not operate at 100 MHz over all operating temperatures. The limiting speed path is the 74F195 shift-register parallel-load time (delay from clock to outputs
valid) which must meet the set-up time of the 74AS374.
It is also possible to use external hardware to create the
cursor. One method is to program the cursor as invisible (transparent and all background) and use the cursor's window status signals to activate the external
hardware.
The horizontal zoom capability is also affected. Rather
than replicating each individual pixel, pairs of pixels
are replicated. Vertical zoom works as normal.
Figure 35 shows a configuration for video data rates of
up to 100 MHz with 2 bits/pixel. A shift-register is
used to multiplex the 8 video bits from the 82786 into
2-bit streams. A 74AS74 flip/flop is used to divide the
100 MHz clock by four. Every fourth clock the 82786
VCLK is raised and the shift registers are loaded with
the previous 82786 VDATA. The video data is delayed
two cycles by this circuit while the Sync and Blank are
delayed only one. This should not be a problem if the
82786 is programmed to generate the correct Sync. The
82786 is limited to positioning the sync transitions at
multiples of four pixels. If more accurate positioning is
required, extra flip/flops can be used to delay sync for
more cycles.
Figure 36 shows a configuration for video data rates of
up to 200 MHz with i bit/pixel. Unfortunately, there is
no TTL-logic available today which will run at the
speeds required for 200 MHz. Therefore ECL or some
other high-speed logic must be used to generate video at
these high rates. Figure 36 converts the video data signals from the 82786 from TTL to ECL levels and then
uses ECL shift-registers to generate the 200 MHz signal.
The software for the configurations in Figures 35 and
36 requires changes similar to the Figure 34 case. The
window StartBits and StopBits are programmed restricted as shown in the preceding table. The pixel
count for Field regions is also one-fourth or one-eighth
the actual size. Horizontal positioning is also restricted
to four and eight pixels for the 100 MHz and 200 MHz
rates respectively. The Accelerated Video control bits
must also be programmed for these configurations.
After the video signals are accelerated to these higher
speeds, color look-up tables and analog-to-digital converters may be used. The circuits in the previous sections must be adapted for these higher speeds.
I
DIVIDE
BY
FOUR
188
"Hz
CLOCK
GEHERAIDR
J
ClKIN
+40UT
VCLK
HSYNC/WSO
VSYNC/WSl
BLANK
UDATA6
IJDATA4
92786 UDATA2
IJDATA0
VDATA7
VDATA5
IJDATA3
UDATAI
D
D
D
,
CLK
Q
Q
Q
HSYNC
VSYNC
BLANK
lOADCLK
DpARALLEl
C
FL IP/FLOP
B SHIFT-REG
Q
QD _ D
A
VIDEO a
lOAD eLK
DpARALLEl
C
B SHIFT-REG
QD I - - - D
A
VIDEO 1
Q
CRT
IHTERFACE
292007-39
Figure 35. External Shift-Register Allows Up to 100 MHz Video with 2 Bits/Pixel
10-142
Ap·270
I
21111 KHz
D
TTL
Q
CONVERTER
( INUERTING)
UClK
CLOCK
GEHERAIDR
B I NAR~ COUNTER
Eel 10
_
02
01
00
I
ClK
I ~-
1
-
I
ECl
PUlLDOWN
HS~NC
HSVNC/WSO
VSVNC/WS1
U5~NC
BLANK
BLANK
82786
QD
QD TTL TO
QD
ECl
D CONUERTER Q
STB
UDATA?
VDATA£>
UDATA5
UDATA4
-
ClK 52 SI
00
D0
DI
SHIFT
D2 REGISTER
D3
TTL
CRT
IHTERFACE
DR
ClK S251
00
Q . . . - - D0
D
DI
O
r
SHIFT
D TTL TO
D
ECL
Q ' - - - ~~ REGISTER
DCOHUERTERQ I---STB
UDATA3
UDATA2
UDA!AI
VDATA0
UIDEO
J
PULLUP
292007-40
Figure 36. External ECl Shift-Register Allows Up to 200 MHz Video with 1 Bit/Pixel
I
25 KHz
CLOCK
GEHERA'lUR
j
UClK
eLK
0
HS~NC
HSVNC/WSO
D
VSYNC/WS1
D
Q
US~NC
BLANK
D
Q
BLANK
I.,.IDAfA0
D
D
D
D
D
D
D
D
82786
UDATAI
UDATA2
UDATA3
UDATA4
UDATAS
UDATA£>
~IDATA?
0
Q
Q
Q
Q
Q
Q
Q
VIDEO
UIDEO
VIDEO
VIDEO
VIDEO
VIDEO
VIDEO
VIDEO
0
2
4
£>
a
A
C
E
CRT
IHTERFACE
UClK
HSYNC/WSO
VSYNC/WS1
BLANK
82786
VDATA0
UDATAI
UDATA2
UDATA3
UDATA4
UDATAS
IJDArA6
UDATA?
FLIP/FLOP
-NO
-CONNECT
D
D
D
D
D
D
D
D
0
0
0
Q
0
Q
0
0
VIDEO
UIDEO
UIDEO
UIDEO
VIDEO
UIDEO
VIDEO
VIDEO
I
3
5
?
9
B
D
F
292007-41
Figure 37. Two 82786s Can Generate 25 MHz Video with 16 Bits/Pixel
10-143
intJ
AP-270
5.7 Multiple 827865
If more colors or resolution are required than possible
with one 82786 at a given resolution, Several 82786s can
be used together to generate the necessary bits/pixel.
Figure 37 shows two 82786s used together to generate
16 bits/pixel at a 25 MHz video rate. This configuration would Iillow a 640 X 480 display with 65536 colors.
Both 82786s' video must be kept in sync. To allow this,
one 82786 is programmed as normal to generate the
master video horizontal and vertical sync. The second
82786 is prograinmed' for slave video sync with the
Slave CRT control bit in the CRTMode Register (Display Processor register 5-bit 3 set). The HSync and
VSync lines of the shive 82786 then become inputs and
are driven by the HSync and VSync output lines of the
master 82786. If the window status signals are used, the
master's HSync and VSync signals should be qualified
with the Blank signal (similar to Figure 31) to correctly
drive the slave 82786 HSync and VSync inputs. Window Status signals are only available from the master
82786 since the slave uses these pins as inputs.
Both 82786s should have six of their eight video timing'
registers (HSyncStp, HFldStrt, HFldStp, LineLen,
VSyncStp, VFldStp, VFldStrt, FrameLen) programmed identically; HFldStrt and HFLdStp should be
programmed to be 2 less than the master. (These parameters are calculated in Section 5.1l.)
The slave 82786 will then automatically sync itself up
to the master 82786 by waiting for its HSync ,input to
fall before each scan line and waiting fpr its VSync input to fall before beginning a new display field. If a
non-interlaced display is used, the two 82786s will always be in sync.
If an interlaced display is used, care must be taken to
ensure both 82786s start on the same field. The easiest
way to ensure they lock in sync correctly is to ensure
they start scanning the display simultaneously. First set
up the slave 82786 CRTMode and video timing registers with a LD.-ALL command. The slave 82786 will
then be ready to begin scanning the display but will
wait until HSync and VSync fall. HSync and VSync
will be floating because they are tristated by all the
82786s. Then the master 82786 can be set up with a
LD.-ALL command to prograin its CRTMode and
video timing registers. Once the master starts scanning;
the HSync and YSync signals will be driven by the master and all 82786s will begin on the even interlaced
field.
To create a 16 bit/pixel bitmap, both 82786 Grap~cs
Processors should be programmed for 8-bit/pixel bitmaps of identical size. To draw in both bitmaps, a
graphics command block (GCMB) can be created for
both 82786s. These GCMBs are generally identical for
both 82786s except for the color values for the Def_
Color and the mask value for the DefJogicaLOp
commands. To display 16 bit/pixel bitmaps, both
82786s should be given an identical Strip Descriptor list
for each to display 8 bits of each 16 bit pixel.
Similarly, 8-bit/pixel bitmaps could be created by splitting the bitmaps between both 82786s having each
82786 responsible for 4 of the 8 bits/pixel. This would
split the work between the two 82786s so that the
BitBlt and ScanJine fill graphic commands will execute twice as fast. Also, because the Display Processor
bus overhead is split between the 82786s, there will be
less bus contention so all other drawing commands will
be faster.
Alternatively, 8-bit/pixe1 bitmaps could be generated
by only one of the 82786s. This would minimize .the
overheat! between the host CPU and the 82786 since
the CPU must commuuicate with only one 82786.
The method in which the 16 video data bits are mapped
into colors for the display interface will determine
which of the two above methods will be used for bitmaps of 8 bits/pixel or less. If the mapping is flexible
enough,' it may be feasible to create any bitmap depth.
For example, 9 bits/pixel bitmaps could potentially be
created using one 82786 for 8 bits and the other for
only 1 bit of each pixel.
The displays discussed in the, previous section obtained
high resolutions at' the expense of bits/pixel. Several
82786s can be combined to provide more bits/pixel at
these high resolutions.
Fignre 38 shows a configuration that uses two 82786s
to create a 4-bit/pixel display at a video rate of
100 MHz. This configuration would support a 1144 X
860 sixteen-color non-interlaced 60 Hz display. Each
, 82786 is required to generate 2 bits of each 4-bit/pixe1.
Therefore, both 82786s draw and maintain half of the
bitmap in their own graphics memory, 4-bit/pixel windows are divided into two 2-bit/pixel bitmaps, one generated by each 82786. The Graphics Processors are programmed as normal for 2-bit/pixel bitmaps. The Display Processors are programmed the way mentioned in
the previous section. Each window is programmed with
one-fourth the horizontal positioning resolution.
10-144
inter
AP-270
5.8 Video RAM Interface
The 82786 can use dual-port video DRAMs (VRAMs)
to generate the video data stream. The VR bit in the
BIU Control Register must be set to I to enable the
mode. In this mode the first tile in each strip generates
VRAM cycles; the second tile and any subsequent tiles
in the strip generate DRAM cycles. In VRAM Mode, a
minimum of two tiles must exist. The first tile is programmed for the VRAM. The second tile must be programmed to be a field tile detailed by the F bit in the
Tile Descriptor if no hardware overlays are required.
There is no limit on the number of strips. The pixel
data for every scan line in the entire display must be
contained in a single row in memory (256 words for
non-interleaved memory and 512 words for interleaved
memories). The Strip Descriptors for each VRAM tile
are set up to indicate only I pixel. The address specified
for this pixel corresponds to the first display pixel.
During the horizontal retrace period, the 82786 transfers the contents of the memory row containing the first
pixel into the VRAM shift register. The VRAM shift
clock is gated with a Blank signal. During the active
display time, the shift clock is active and periodically
clocks out the video data. External multiplexers must
be used to convert the 16-bit (32 interleaved) data
stream into a serial stream depending upon the bits per
pixel needed (Figure 9).
In this mode, pixel depth is fixed by external hardware
and all Display Processor registers referring to video
data fetch should be programmed to zero.
I
DIVIDE
BY
FOUR
lBB HHz
CLOCK
GENERATOR
I
ClKIN
"'"4 OUT
UCLK
HSYNC/WSO
VSYNC/WS1
BLANK
D
Q
Q
D
Q
UDATA?
UDATA5
82786 VDATAS
UDATAI
lOAD elK·
A PARALLEL
B
C SHIFT-REG
QD I - - - D
D
UDATA6
UDATA4
VDATA2
UDATA0
ClK
A LOAD
PARALLEL
," SHIFT-REG
QD ' - - - - D
D
UCLK
,,
HSYNC/WSO
VSYNC/WS1
BLANK
CLK
D
HS'>!NC
VS'>!NC
BLANK
CRT
INTERFACE
Q
UIDEO 0
B
-
Q
VIDEO 1
FLIP/FLOP
-
-CO~~ECT
UDATA?
~'DATA5
ClK
A lOAD
PARALLEL
c SHIFT-REG
OD I - - D
D
B
82786 VDATA3
VDATAI
Q
~'IDEO
2
I
VDATAb
UDATA4
lOAD eLK
A PARALLEL
SHIFT-REG
~'DATA2
B
C
VDATA0
D
olD I - - - D
Q
VIDEO 3
292007-42
Figure 38. Two 82786s Can Generate 100 MHz Video with 4 Bits/Pixel
10-145
AP-270
For downward compatibility reasons, however, it may
be necessary to provide the character ROM function in
a 82786 system. Figure 39. illustrates a system capable
of displaying both character ROM text and 82786
graphics. A multiplexer is used to switch between the
character ROM output and the direct 82786 output.
One of the window status bits is used to switch the
multiplexer so both the character ROM and the 82786
graphics windows can be shown simultaneously on the
same screen. It is important to delay the direct 82786
VDATA and window status signal the same number of
clocks as the character-cell video so that all signals get
to the multiplexer on the same clock. The extra D-flipl
flops before the multiplexer are used to perform the
needed delay.
5.9 External Character ROM
Few 82786 applications will require, or even benefit
froin, the use of an external character ROM.
The 82786.Graphics Processor can very rapidly draw
characters. It can fill an 80x25 character screen with
highly detailed 16x 16 characters in less than one tenth
ofa second.
The Graphics Processor is also very flexible in the way
it draws characters. Characters may be:
- formed from an unlimited number of character
fonts
- placed at any pixel. on the screen
- rotated in 4 directions with 4 paths
- combined with graphics
- drawn in any color
- have transparent or opaque J>ackground
The character ROM in Figure 39 is capable of displaying 256 characters using a 9x 14 pixel character-cell.
The characters are stored as an 8-bit pixels within a
82786 bitmap. To display the character, the window is
programmed as an 8-bit/pixel bitmap with a horizontal
zoom of 9 and a vertical zoom of 14. The 82786 will
then place the 8-bit character code on its VDATA pins
A character ROM display forces characters from a predefined fon.t to be restricted to character-cell positions
on the screen with few, if any, of the above flexibilities.
J
25 "Hz
CIJJCK
GEHERAlUR
I
UCLK
ID
HSYNe/WSD
VSYNC/WS1
~r-
01
DFLIP/F;LOP:
BLANK
82786
CLK
UDAfA9
UBArA1
IJDAtA2
UDAfA3
UDAfA4
VDAfA5
IJDATA6
UBArA?
CLK
D
0
1A
A
Q
0
•••
VIDEO S
•
CRT
B
IHTERFACE
t--
1A
A
A
A/8
4A
1Y
UIDEO 4
2'1
VIDEO e;
VIDEO Ii
~:
...:::::
I-t--
I
-t--
~
~ :~ RIJJ1
0
1
2
E•
00
.1
02
Q•
!
RO"
COUNTER
CLK
l
If rq:
.?
A.
A.
A18
All
~
51 S0 eLK
.0
P0
PI
P2 SHIFT
pa REG
Dst
SI SO CLK
00
.4 _ p e
PI
P2 SHIFT
'5_
~~=== P3
.8
DSL
VIDEO?
•
"YO
.0
.1
.2
Q3
BLANK
VIDEO 2
U2:1 MUX 3y
4Y
Ae
" - AI
A2
A3
A4 CHAR
USVHC
VIDEO e
VIDEO I
til: 2: 1 Nil>:: 3V
4Y
B
lill
-
Al8
!:74S157 ~~
•
DFLIP/FL~PQ
D
"'-L.J.
-L
HSYNC
Vee
.~
e
PI
W~
REG
J
CLK
TC
2
P3
DOT
COUNTER
~
rq:~
.'l.
292007-43
Figure 39. Support of Character-ROM and Bit-Mapped Graphics on Same Screen
10-146
inter
AP-270
during the scan lines when the character is to be displayed. The pixel counter is used to load the shift register every 9 pixels. This counter is synchronized to the
beginning pixel of the window by starting when the
window status pin falls. The row counter is used to
supply row information to the character ROM. This
counter is synchronized to the frame by starting from
the end of the VSync pulse. Therefore, any character
ROM window must begin at a multiple of 14 scan lines
after VSync.
Another situation in which a character ROM display
may be practical is if a very large character set is required. The Japanese Kanji characters are an example.
The size of this character set is so large that it may be
more practical to store the characters in a character
ROM rather than load them from disk into the 82786
graphics memory. Figure 40 illustrates a configuration
that can display up to 65536 characters from a very
detailed (32x32) font. This circuit allows both text and
graphics windows to be displayed on the screen simultaneously. One of the window status signals is used to
select between text and graphics.
broadcast TV, video recorders, and video laser disc
players. The main requirement to perform such a feat is
that both 82786 and the video source are locked in
sync.
The 82786 has two independent Video Slave modes and
HSync/VSync and Blank can be independently configured as outputs or inputs. When HSync/VSync are programmed as inputs, then they are still outputs during
the active display period if the window status is enabled. External HSync/VSync reset the 82786 horizontal and vertical counters respectively.
When Blank is configured as output, the active display
period is determined by the programmed values of
VFldStrt, VFldStp, HFldStrt, and HFidStp. When
Blank is configured as an input, the external system
determines the active display period. The internal video
shift register generates video data only during the active
display period.
HSync/VSync and Blank would normally be programmed as input/output as follows:
Such a character set requires a high resolution, generally monochrome display. The circuit in Figure 40 allows
up to 200 MHz video (one bit/pixel) for very high resolution screens. The 82786 is programmed in super
High-Speed Acceleration Mode as described in Section
5.6.
The character-codes to be displayed should be placed in
one bit/pixel bit-maps with 16 consecutive bits for each
character. The hardware combines the 8-bit VDATA
values from two consecutive pixels to generate the 16bit character-code for the Character-ROM. If less than
65536 characters are required, not all of the 16-bit
character code addresses need be used for the character-ROM. Some of these bits may be used for attributes
such as blinking and reverse video. The ROM contains
a 32x32 character font, each character is split up into
32-lines of four 8-bit bytes. The "pane" counter selects
one of the four 8-bit bytes at a time. The "row" counter
determines the current row of the character.
Character cell windows should be zoomed by 2 horizontally and by 32 vertically. The window must be
placed at a multiple of 4-pixels from HSync and a multiple of 32-lines from VSync. It is possible to place windows at non-multiples from HSync and VSync if the
"pane" and "row" counter parallel inputs are tied to
other than ground.
5.10 Combining the 82786 With Other
Video Sources
HSync/
VSync
Blank
Output
Output
Normal display generated by
82786
Input
Output
82786 generated display
superimposed on externallygenerated video or
Multiple 82786 systems
or
Input
Input
Application
The 82786 sync timing registers should be programmed
to be as close to the frequency of the video source as
possible. The 82786 should also be programmed for
slave video-sync. The sync signals from the video
source must be converted into separate TTL-level horizontal and vertical sync and fed to the 82786 HSync
and VSync pins. The 82786 will then automatically
sync itself up to the video source by waiting for its
HSync input to fall before each scan line and waiting
for its VSync input to fall before beginning a new display field.
For many applications, the 82786 video clock can be
derived directly from a crystal oscillator. Since the
82786 syncs up to the nearest pixel on every scan line,
even video sources with imperfect timings, such as video recorders where speed variations are common, will
produce an acceptable picture. The frame-to-frame deviation of the 82786 graphics information on the screen
relative to the video source will never be more than one
pixel.
It is possible to combine graphics output from the
82786 with output from other video sources such as
10-147
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US'rtlC
Vert.
Vert.
Front
Porch
Porch
Active
Back
Video
l/Ufreq _ _ _ _ _ _ _~_ _~):
HS'rtIC
BLANK
:.e:-(-
UBI "nk_----"")
292007-47
Figure 43. Vertical Sync and Blank Timing Parameters
Hfreq-horizontal frequency - the frequency at which
horizontal lines are scanned. Monitors typically range
from 15-36 kHz.
Vfreq-vertical frequency - the frequ~ncy at which
the display field is scanned. Monitors typically range
from 40-70 Hz.
BPP-bits per pixel - monitors with digital inputs restrict the number of usable bits/pixel. Monitors with
analog inputs allow a virtually unlimited range of intensities with the use of Digital-to-Analog converters. This
parameter is mainly dependent on the video interface
hardware described in the previous sections.
Color monitors generally limit the perceivable horizontal lind vertical resolution due to their shadow mask.
See the specific monitor specifications for more details.
Video interface parameters: these are dependent on the
82786 component and the video interface logic.
VCLK-video clock frequency - the video input clock
into the 82786. It has a maximum rate of 25 MHz and
may be chosen so that the frequency evenly divides by
both Hfreq and Vfreq.
Accel-82786 video acceleration - this parameter is
determined by what mode the 82786 is used in. Normally Accel = 1. If the trade-offs mentioned in Section
5.6 are used to attain higher video rates at the expense
of fewer bits/pixel, then the value for Acce1 should be
2,4, or 8.
Video
Mode
Max
Programmed
DotClk
Accel Bits
Accel = 1 Normal
25 MHz
00
Accel = 2 High Speed
50 MHz
01
Accel = 4 Very High Speed 100 MHz
10
Accel = 8 Ultra High Speed 200 MHz
11
DotClk-pixe1 dot clock frequency - this is normally
the same as VCLK. However, when accelerated video
modes are used, this is either 2, 4, or 8 times VCLK.
DotClk
=
VCLK X Accel
HSyncStp, HFidStrt, HFidStp, LineLen-these are
values programmed into the 82786 Display Processor
to determine the horizontal scan timing (Figure 42).
They may be set to any value from 0 to 4095. Their
values should also fit the formula:
HSynStp < HFldStrt < HFldStp < LineLen
VSyncStp, VFldStrt, VFldStp, FrameLen-these are
values programmed into the 82786 Display processor to
determine the vertical scan timing (Figure 43). They
may be set to any value from 0 to 4095. Their values
should also fit the formula:
VSyncStp < VFldStrt < VFldStp < FrameLen
Once the above parameters are evaluated, the video parameters can actually be calculated. The parameters interact quite heavily so that, for example, if a specific
10-152
inter
AP-270
horizontal and vertical resolution at a specific field rate
is required, the monitor frequencies and blank times
may need to be altered. It may take several iterations to
optimize all the parameters. The calculations can be
performed by hand. However, a much easier way to
manipulate these values is by using a spreadsheet program. A spreadsheet allows the parameters to be easily
manipulated with their affects immediately displayed.
A spreadsheet template for this purpose is given in Section 5.13.
The following formulas are used to determine the video
parameters. Along with the formulas is an example calculation. For the example, let's generate a 640 X 400
X 8 bit/pixel (256 color) screen at 60 Hz non-interlaced. We will assume:
Hres
Vres
Vfreq%
Hblank%
Vblank%
Accel
640 pixels
400 pixels
60 Hz
12 ,...s
= 1300,...s
1 (no external acceleration)
DotClkO/O =
1.
DotPenod%
Hres
(lIHfreq%) - Hblank%
640
(1/26.03 kHz) - 12,...s = 24.23 MHz
And then calculate the actual 82786 VCLK. Since external acceleration circuits are not used in our example,
it turns out to be the same as the DotClk.
VCLKO/O = DotClkO/O / Aceel = 24.23 MHz / 1
= 24.23 MHz
. Great, now all we need is a 24.23 MHz crystal is needed to generate VCLK. But since such a crystal is tough
to find, try a 25 MHz crystal instead and see how it
affects the rest of the parameters. First of all, the pixel
dot clock changes.
DotClk = VClk
x Accel
= 25.00 MHz
x 1
= 25.00 MHz
Now, see how many VCLK's are required for the horizontal blank time.
Variables with a percent (%) after them represent desired values, the actual value will be calculated below.
HblankClks = ROUND (VCLK x HblankO/O) = ROUND
(25 MHz x 12 ,...s) = 300
ROUND(X) will be used to denote rounding off X to
the nearest integer.
Now, calculate the actual horizontal Blank time.
Hbl
First, calculate the vertical resolution per field. Since.
our display is noninterlaced, the value is the same as
the vertical resolution.
If interlaced then: VresFld = Vres/2
else: VresFld = Vres Vresfld
= 400 pixels
The actual horizontal period is then the time required
to display one line of pixels plus the Blanking time.
Hfreq
With interlaced screens, VresFld is half the vertical resolution. For example, with 525 lines, use 262.5 for
VresFld.
Now, calculate the horizontal frequency required. Subtract the vertical Blank time from the vertical period
and divide by the active vertical lines to obtain the horizontal period. Inverting all that gives the horizontal
frequency.
1
Hfreq% = Hperiod%
k _ HblankClks _
300 _
an VCLK
- 25 MHz - 12,...s
VresFld
(1IVfreq%) - Vblank%
=
1
.
-::-:--c-=c-::::-:---:-::-:--:(Hres / DotClk) + Hblank
= (640 / 25 MHz)
+ 12,...s =
26.60 kHz
The number of horizontal lines per frame can now be
calculated:
VFrameLines = ROUND(Hfreq / Vfreq%)
= ROUND(26.60 kHz / 60 Hz) = 443
If an interlaced display is used, VFrameLines should be
rounded-off to the closest odd integer.
The number of scan lines determines the actual vertical
frequency:
400
(1/60) - 1300,...s = 26.03 kHz
In a similar manner, calculate the pixel dot clock required.
Vfreq = Hfreq / VFrameLines = 26.60 kHz / 443
= 60.05 Hz
10-153
AP-270
Now that the major parameters are calculated and we
are satisfied with them, we can break up the Blanking
times into sync, front and back porch times. Typical
monitor values are:
HSync = 21-'s
HBack = 61-'s
VSync = 300 1-'5
VBack = 800 1-'5
HSyneClks =
=
HBaekClks =
=
ROUND (VCLK x HSYNCj
ROUND (25 MHz x 2 1-'5) = 50
ROUND (VCLK x HBaek)
ROUND (25 MHz x 6 1-'5) = 150
VSyneClk5 =
=
VBaekClks =
=
ROUND
ROUND
ROUND
ROUND
=
8- 1
=
(VSyncLine5 x 2) - 1
VSyneStp + (VBackLine5 x 2)
VRes Total
VFrameLine5 - 2
VResTotal = VResFieldl
+
VResField2.
VFrameLines equals the total number of HSyncs in an
entire frame.
Make sure LineLen > HFldStp and that FrameLen >
VFrameLines. If not, your parameters are inconsistent
and you should modify your requirements and re-calculate.
FinalIy, the bits for the CRTMode Register should be
determined. For our example, non-interlaced mode is
used and no accelerated video is required. Assuming
the 82786 is used to generate the HSync, VSync and
Blank signals and assuming the window Status pins are
not used, the CRTMode registers should be loaded with
alI zeros.
VSyncStp = VSyneLine5 - 1
VFldStrt =
=
VFldStp =
=
=
=
=
=
In the preceding formula, VResTotal equals the Vertical Resolution for Field 1 plus the Vertical Resolution
for Field2 as shown below.
Now it's a simple matter to calculate the values for the
eight 82786 Display Processor video timing registers.
For noninterlaced displays:
For interlaced and interlace-sync displays:
VSyneStp
VFldStrt
VFldStp
FrameLen
(Hfreqx VSYNCj
(26.6 kHz x 300 1-'5) = 8
(Hfreq x VBaek)
(26.6 kHz X 800 1-'5) = 21
HSyncStp = HSyneClk5 - 3
= 50 - 3 = 47
HFldStrt = HSyneStp + HBaekClks
= 47 + 150 = 197
HFldStp = HFldStrt + (Hre5 / Aecel)
= 197 + (640 / 1) = 837
LineLen = HBIankClk5 + (Hres / Aceel) - 3
= 300 + (640 / 1) - 3 = 937
FrameLen = VFrameLine5 - 1
=443-1=442
7
VSyneStp + VBaekLine5
7 + 21 = 28
VFldStrt + Vres
28 + 400 = 428
10-154
inter
CRTMode -
AP-270
Display Processor Register # 5
15
7
RESERVED
6
5
I~
1
4
3
2
W
S
B
0
I
ACCELERATED VIDEO BITS
o
o
0 NORMAL SPEED
1 HIGH SPEED
VERY HIGH SPEED
1 SUPER HIGH SPEED
a
BLANK SLAVE MODE (1
(UP
(UP
(UP
(UP
TO 25 MHZ)
TO 50 MHz)
TO 100 MHz)
TO 200 MHz)
=EXTERNAL BLANK)
=EXTERNAL SYNC)
HSYNC. VSYNC SLAVE MODE (1
WINDOW STATUS PINS (1
=ENABLE)
INTERLACE
a
a
1
1
a
1
a
1
NON-INTERLACED
RESERVED
INTERLACE
INTERLACE-SYNC
The host CPU software is required to load the values of
the eight video timing registers and the CRTMode Register. Generally, this is done during system initialization. The registers should all be loaded simultaneously
using the LD_ALL command rather than using individual LD_REG commands. This ensures that the
video sync signals are never invalid while registers are
being loaded.
Some CRTs can be permanently damaged by supplying
the wrong sync frequencies to them. To prevent invalid
video sync signals, the HSync, VSync, and Blank pins
292007-48
are tristated after RESET until the CRTMode Register
has been written to.
5.13 A Spreadsheet for Calculating
Video Parameters
As seen in the previous section, quite a number of calculations are required to determine the 82786 video parameter constants. Often several iterations through the
calculations are required to optimize the display format. This process can be greatly simplified by using a
spreadsheet.
10-155
AP-270
An example of the output from such a spreadsheet is
shown below. This example illustrates a 1290 x 968 x
4-bit/pixel (16 color) interlaced 60 Hz display. The
user has supplied all of the values under the "DESIRED" column and the spreadsheet program has calculated the rest. The "ACTUAL" column shows the
closest timings and parameters that the 82786 can actually supply. The "82786 DP REGISTER VALUES"
shows the values that should be programmed into the
Display Processor Registers to generate such a display.
V IDE 0
8 2 7 8 6
The user can easily modify the "DESIRED" values until the "ACTUAL" values meet the application's needs.
Care should be taken to ensure that all "ACTUAL"
values are logically correct. If for example, any of the
calculated parameters are negative, then the set of
"DESIRED" parameters can not produce such a display, so some parameters must be adjusted.
PAR A MET E R S
Type under DESIRED column only: ACTUAL & REGISTER columns are calculated
PARAMETER
DESIRED
Video Clock
VCLK (MHz):
25
Acceleration (1,2,4 or 8) :
2
Interlacing (1
no, 2
yes): 2
Horiz Resolution (Pixels):
1290
Vert. Resolution (Pixels):
968
=
=
Horiz
Horiz
Horiz
Horiz
Line Rate
(kHz) :
Sync Width
(I-'s) :
Back Porch
(I-'s) :
Front Porch (I-'s) :
Vert.
Vert.
Vert.
Vert.
Frame Rate
Sync Width
Back Porch
Front Porch
(Hz)
(I-'s)
(I-'s)
(I-'s)
:
:
:
:
ACTUAL
25
2
2
1290
968
--- 30.487
2
2
4
4
1
1
LineLen:
HSyncStp:
HFldStrt:
HFldStp:
818
48
148
793
60 59.956
200 196.8
400 393.6
213.2
FrameLen:
VSyncStp:
VFldStrt:
VFldStp:
1015
The template follows. This template should be easily
adaptable to nearly any spreadsheet program. This particular spreadsheet program uses @ROUND(X,O) to
denote rounding to the nearest integer. If no rounding
function is available in your spreadsheet program, you
can substitute the integer function (which truncates the
fractional portion to return the next lowest integer) for
the round function:
substitute
@INT(X+O.S) for
82786 DP REGISTER VALUES
10
34
1002
After entering the template into your favorite spreadsheet, you may wish to verify that it is working correctly by entering the "DESIRED" values of the above
example and checking that the "ACTUAL" and
"REGISTER" results match ..
@ROUND(X,O)
10-156
l
1:
------------A------------ ---B--- ------------C------------- ---D--- -----------------E------------------S 2 7 S 6
V IDE 0
PAR A MET E R S
Type under DESIRED column only: ACTUAL & REGISTER columns are calculated
2:TY~~~~~~~~~~====~~~~~~~~~_ _ _ _ _ _ _ ___
3: ---- PARAMETER
4:
DESIRED ACTUAL
5:
6: Video Clock
VCLK (MHz):
+B6
+B7
7: Acceleration (1,2,4 or S) :
~
S: Interlacing (l=no, 2=yes):
9 : Horiz Resolution (Pixels):
10 : Vert. Resolution (Pixels) :
-.J
11:
()1
12 :
13 :
14 :
15 :
16 :
17 :
IS:
19 :
20:
S27S6 DP REGISTER VALUES
+BS
@ROUND(B9/C7,0)*C7
@ROUND(BIO,O)
>
l'
Horiz
Horiz
Horiz
Horiz
Line Rate
(kHz) :
Sync Width
(JLs) :
Back Porch
(/Ls) :
Front Porch (/Ls) :
(C6*1000)/(E12+2)
(E13+2)/C6
(E14-El3)/C6
(E12-El5)/C6
LineLen: @ROUND(C6*B15,0)+E15
HSyncStp: @ROUND(C6*B13,0) -3
HFldStrt: @ROUND(C6*B14,0)+E13
HFldStp: +E14+(C9/C7)
Vert.
Vert.
Vert.
Vert.
Frame Rate
Sync Width
Back Porch
Front Porch
(CS*C12*1000)/(E17+CS)
((ElS+CS)*1000)/(C12*CS)
((E19-ElS)*1000)/(C12*CS)
(E17-E20)*1000/(C12*CS)
FrameLen
VSyncStp
VFldStrt
VFldStp:
(Hz)
(/Ls)
(JLs)
(/Ls)
:
:
:
:
@ROUND((C12*1000)/B17-(CS-l)/2,0)*CS-l
(@ROUND((C12*BlS)/1000,0)-1)*CS
@ROUND((C12*B19)/1000,0)*CS+ElS
+E19+CIO
'"......o
infef
AP·270
APPENDIX A
SAMPLE INITIALIZATION CODE
Many registers within the 82786 must be initialized to
configure the 82786 for the particular hardware environment it resides in. This appendix contains assembly
language code to initialize the 82786 for one particular
configuration:
synchronous 10 MHz 80286 interface
(Sections 4.2 and 4.3, Figure 18)
one row 'of two interleaved banks of 51C256 Fast
Page Mode DRAM
(Section 3.3, Figure 9)
640 x 300 x 8-bit/pixel non-interlaced 60 Hz display, 25 MHz VCLK
(Section 5.11, Figure 27)
All of the parameters to be initialized for this configuration are calculated under their corresponding sections
in the body of this application note. To calculate the
parameters for other configurations, refer to these sections.
This example of initialization code can be used to initially test many of the hardware functions. The code
should create a stable display on the CRT. The display
will consist of a black field which covers the entire
screen (a 640 x 400 black rectangle). In the center of
the rectangle is a 16 x 16 pixel arrow-shaped red and
yellow cursor.
name Initialization82786
Memory82786 segment at OCOOOh
;segment located at start of CPU-mapped 82786 memory
;define locations of 82786 internal registers
org 0
Internalrelocation
Reserved
BIUControl
RefreshControl
DRAMControl
DisplayPriority
GraphicsPriority
ExternalPriority
dw
dw
dw
dw
dw
dw
dw
dw
?
?
?
?
?
?
?
?
;BIU registers
?
?
?
?
?
?
;Graphics Processor registers
?
?
?
?
?
?
;Display Processor registers
org 20h
GPOpcode
GPLinkAddressLower
GPLinkAddressUpper
GPStatus
GPlnstructionPtrLower
GPlnstructionPtrUpper
dw
dw
dw
dw
dw
dw
org 40h
DPOpcode
DPParameterl
DPParameter2
DPParameter3
DPStatus
DefaultVDATA
dw
dw
dw
dw
dw
dw
10-159
inter
AP-270
;location of values for Display Processor LD_ALL instruction
org 80h
DPLdAllRegs label word
dw
3
;VStat:
turn on display and cursor
dw
OFFh
;IntMask: mask all interrupts
dw
20
;TripPt:
trip point
20 FIFO dwords
dw
;Frint:
o
cause interrupt every frame (interrupt is 'masked)
reserved
dw
o
dw
o
;CRTMode: non-interlaced, non-accelerated,master sync/l:blank
47
dw
;HSyncStp: horizontal sync stop
197
;HFldStrt: horizontal field start
dw
dw
837
;HFldStp: horizontal field stop
8 video timing registers
dw
937
;LineLen: horizontal line length
are programmed for
dw
7
;VSyncStp: vertical sync stop
640 x 400 at 60 Hz
dw
28
;VFldStrt: vertical field start
with 25 MHz VCLK
dw
;VFldStp: vertical field stop
428
dw
442
;FrameLen: vertical frame length
dw offset WinDescl ;DescAddrL:descriptor address pointer lower
dw
0
;DescAddrU:descriptor address pointer upper
dw
; (Reserved)
o
db
o
;ZoomY:
no vertical zoom
db
o
;ZoomX:
no horizontal zoom
dw
;FldColor: black field color
o
dw
OFFh
;BdrColor: white border color
dw
;PadlBPP: pad with zeros for 1 bit/pixel
o
dw
;Pad2BPP: pad with zeros for 2 bits/pixel
o
dw
;Pad4BPP: pad ,with zeros for 4 bits/pixel
o
db
2
;CursorPad:pad with red for cursor (yellow cursor in red box)
80h
db
;CsrStyle: opaque l6x16 block cursor, no window status
dw
510
;CsrPosX: put cursor in middle of screen (horizontally)
220
dw
;CsrPosY: put cursor in middle of screen (vertically)
=
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
OOOOOOOllOOOOOOOb
OOOOOOllllOOOOOOb
OOOOOllllllOOOOOb
OOOOllllllllOOOOb
OOOllllllllllOOOb
OOllllllllllllOOb
OllllllllllllllOb
llllllllllllllllb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
OOOOOllllllOOOOOb
;CsrPatO:
;CsrPatl:
;CsrPat2:
;CsrPat3 :
:CsrPat4:
;CsrPat5 :'
:CsrPat6 :
:CsrPat7 :
;CsrPat8 :
:CsrPat9 :
;CsrPatA:
;CsrPatB:
:CsrPatC:
;CsrPatD:
;CsrPatE:
;CsrPatF:
create arrow-shaped cursor.pattern
;location of strip descriptor list
WinDescL label word ;strip descriptor list
, ;header of strip descriptor
dw
399
;lines in strip (400 covers entire screen)
dw
0
;lower link to next strip descr (there is none)
dw
:upper link to next strip descr (there is none)
0
dw
;number of tiles in strip (only one)
0
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AP-270
o
o
dw
dw
dw
dw
dw
dw
o
639
o
OOOOlh
;first (and only) tile descriptor
;bitmap width (not applicable, this is field)
;memory start lower addr (not applicable)
;memory start upper addr (not applicable)
;field width (640 covers entire screen)
;fetch count (not applicable, this is field)
;set field bit,use top,bottom,left,right borders
Memory82786 ends
Initialize82786 segment
mov
ax,seg BIUControl
mov
ds,ax
;code to initialize 82786
;put 82786 register segment in ds
assume cs:lnitialize82786, ds:Memory82786
mov byte ptr BIUControl, 30h
mov byte ptr BIUControl+l, 0
;convert 82786 to 16-bit bus •••
; ••• must use two 8-bit transfers
mov
InternalRelocation, Olh
;locate reg's at 82786 mem addr Oh
mov
mov
DRAMControl, IDh
RefreshControl, 18
;1 row, interleaved 51C256 DRAM
;request refresh every 15.2 uS
mov
DisplayPriority,
mov
mov
GraphicsPriority, OlOOlOb
ExternalPriority, 100000b
mov
mov
mov
DPParameterl, offset DPLdAllRegs ;address for LD_All command
DPParameter2, OCH
DPOpcode, 5
;let DP perform LD_All command
;set Display
1l01l0b
FPL, SPL = 6
;set Graphics FPL, SPL = 2
;set External FPL
=4
ret
;end of initialization subrtn
Initialize82786 ends
If the constants in the CPU-mapped 82786 memory for
the LD_ALL command and the Strip Descriptor list
(in Memory82786 segment) cannot be loaded into
82786 memory by the system's program loader, they
will have to be loaded by the initialization code. One
method is to have the loader load them into CPU system memory and use a repeat-move-string command in
the initialization code to move these constants into the
82786 graphics memory. Alternatively, it is possible to
place these constants in the 82786-mapped CPU memory and allow the 82786 to fetch them using mastermode. This method, however, is not as efficient because
the 82786 must re-fetch the Strip Descriptor list for
every display frame.
The Graphics Processor is not used in this initialization
code. To fully initialize the Graphics Processor, the following commands are required:
DeL_Bit_Map
for all drawing and BitBIt commands
Def_Logical_Op for all drawing and BitBIt commands
Def_Colors
if line/character drawing used
Def_Texture
if line drawing used
Def_Char_Set
if character drawing used
Def_Char_Orient if character drawing used
Def_Char_Space if character drawing used
Load~eg
initialize stack pointer if macros
used
Load_Reg
set poll-on-exception mask if used
Load_Reg
set interrupt mask if interrupts
used
10-161
APPLICATION
NOTE
AP-408
October 1987
An Introduction to
Programming the 82786
Graphics Coprocessor
RAY TORRES
APPLICATIONS ENGINEER
Order Number: 240048-001
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RELATED DOCUMENTATION
This software applications note should be used with the 82786 User's Manual (Order Number: 231933-002).
Other documentation available for the 82786 includes: Hardware Configuration Applications Note (Order Number:
292007-003), The 82786 Architectural Overview (Order Number: 122711-003), The 82786 Data Sheet (Order Number 231676-003), and 82786 Design Example-Interfacing to the IBM PC/AT (Order Number: 240049-001).
CHAPTER 1 INTRODUCTION
1.0 INTRODUCTION
This application note shows, by example, how to program the 82786. These software interface examples are written
for an Intel 82786-based graphics board as described in the Application Note: 82786 Design Example-Interfacing to
the IBM PC/AT. However, the concepts presented in these examples can be applied to any system using the 82786.
With the appropriate modifications, these programs will run on other .82786 systems. Contact your nearest Intel
Sales Office for more information about availability of 82786 graphics boards and availability of machine-readable
copies of the software presented in this Application Note.
Chapter 2 presents an overview of the programmers model of the 82786.
Chapter 3 presents an 80286 Assembly Language example. The objectives of this example program are:
1) Initialize the 82786 registers,
2) Program the Display Processor (DP) for one full-screen window,
3) Draw a simple graphics image using the Graphics Processor (GP).
Chapter 3 also suggest several modifications to the Example Program as exercises for the reader. Solutions to the
exercises are provided in the appendix. By working through these exercises, the reader gains an understanding of the
concepts of programming the 82786.
Chapter 4 provides a Quick Reference Section, containing information frequently used by 82786 programmers.
1.1 Hardware System Requirements
Hardware system requirements to run the programming examples:
(1) An 82786 graphics board as described in the Application Note: 82786 Design Example-Interfacing to the IBM
PC/AT.
(2) 6 MHz or 8 MHz-IBM AT computer.
NOTE:
(3) The Intel Evaluation Board cannot be used in a computer in which the EGA Graphics Adapter is installed. (For
your text display, use the Monochrome Adapter or CGA adapter.)
Any other peripheral device that uses the A-segment of CPU address space or CPU addresses C4400-C4474
cannot be used with the 82786 Evaluation Board.
(4) NEC Multisync monitor (Model No: JC-1401P3A) or
SONY Multiscan monitor (Model no: CPD-1302)
You may need to adjust the monitor controls for vertical and horizontal hold, size, position, etc.
Settings for the NEC Monitor:
Set the switches on the rear of the NEC Multisync monitor as follows:
(1) Set the "MANUAL" switch to "ON".
(2) Set the TTL-ANALOG switch to "TTL".
(3) Set DIP switch 5 to "ON".
Set DIP switch 6 to "OFF".
Settings for the SONY Monitor:
Set the Digital-Analog switch to "DIGITAL".
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CHAPTER 2 PROGRAMMER'S MODEL OF THE 82786
2.0 INTRODUCTION
This Chapter presents an explanation of the programmer's model of the 82786. There are 5 sections in this chapter:
2.1) Overview
2.2) Graphics Processor
2.3) Display Processor
2.4) Bus Interface Unit
2.5) Summary
2.1 Overview
PROGRAMMING MODEL
82786
. . • OVERVIEW
• GRAPHICS PROCESSOR (GP)
• OISPLAY PROCESSOR (OP)
• BUS INTERFACE UNIT (BIU)
240048-1
Here is a block diagram of a typical 82786 system. The Display Processor and Graphics Processor are programmed
independently. The Bus Interface Unit has programmable priority levels to control bus arbitration between the DP,
GP, Host CPU, and DRAM refresh.
The Host CPU can write directly to the 82786 registers and directly into graphics memory.
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82786 PROGRAMMING MODEL
GRAPHICS
PROCESSOR
DISPLAY IMAGE
GRAPHICS
MEMORY
CPU
240048-2
To program the Graphics Processor, the host CPU writes a GP command list into graphics memory. Then, the GP
executes the command list, drawing geometric shapes and text into the bitmaps in graphics memory.
To program the Display Processor, the host CPU writes a Screen Descriptor List into graphics memory. The DP
reads the Descriptor List and sends graphics data, in the desired format, from the bitmaps to the display device. The
DP clm simultaneously display data from many different bitmaps. This is called Hardware Windows. Hardware
Windows provides window movement, scrolling, and spanning and allows instantaneous changes in window content
and screen format.
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2.2 Graphics Processor Programming
BITMAPS
A BITMAP IS A RECTANGULAR DRAWING AREA
COMPOSED OF PIXELS
• MAXIMUM BITMAP SIZE· 32K BY 32K PIXELS
• 1, 2, 4 OR 8 BITS/PIXEL
• PACKED-PIXEL ORGANIZATION - EFFICIENT MEMORY
UTILIZATION (2, 4, 8 OR 16 PIXELSIWORD)
• NO LIMIT TO NUMBER OF BITMAPS
(0.0)
32K
••.
---~x::----
1
110111
PIXEL
LOCATION
32K Y
DISPLAY SCREEN
BITMAP IN GRAPHICS
MEMORY
240048-3
A bitmap can be thought of as a rectangular drawing area composed of pixels. Bitmaps are located in graphics
memory.
The 82786 supports:
- VERY LARGE bitmaps, up to 32K x 32K.
- Flexible color capacity: 1,2, 4, or 8 bits/pixel providing 2, 4, 16, or 256 colors
- Packed pixel organization allows for efficient memory utilization
- Unlimited number of bitmaps, limited only by amount of available graphics memory.
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Ap·40B
GRAPHIC PROCESSOR REGISTERS
INDIRECT ACCESS
REGISTERS
DIRECT ACCESS
REGISTERS
OFFSET 20H
OP CODE
I ECl
r-------------~
0
GP CONTROL
REGISTERS
PARAMETER 1
PARAMETER 2
GP CONTEXT
REGISTERS
STATUS
INSTRUCTION
POINTER (22 BITS)
2BH
1....-_ _ _ _ _ _ _ _-1
• GP INTERNAL REGISTERS
22 WORDS
• GP CONTROL REGISTERS
• GP CONTEXT REGISTERS
• DUMP_REG, lOAD_REG
240048-4
Overview of Graphics Processor Registers
The Graphics Processor has 2 sets of registers: directly accessible and indirectly accessible.
The directly accessible registers include:
An Opcode register, two parameter registers, a Status Register, and an Instruction Pointer.
The indirectly accessible registers include the GP Control registers and the Context Switching registers used in
multi-tasking systems. The indirectly accessible registers are loaded with the LOAD~G command and read with
the DUMP~G command.
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,
GRAPHICS· PROCESSOR COMMAND LIST
GECL
82786 GP
REGISTERS
1
10
OPCODE 2
10
GRO
LINK
GR1
ADDRESS
LOW
PARAM
GR2
ADDRESS
HIGH
PARAM
OPCODE
10
OPCODE 1
PARAM
PARAM
PAI;IAM
OPCODE 3
10
PARAM
PARAM
HALT
11
+
GECL
240048-5
The graphics processor command list is composed of a sequence of Graphics opcodes and· parameters. This command list is written into graphics memory by the host CPU. The GP begins execution of the command list when the
host CPU writes a LINK instruction and the address· of the command list into the GP registers. The GP halts
execution when it reaches the HALT instruction.
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GRAPHICS PROCESSOR COMMAND SET
FOUR TYPES OF COMMANDS:
GEOMETRIC
- POINT, INCR POINT, LINE, POLYLINE,
POLYGON, ARC, CIRCLE, HORIZ-LlNE
TRANSFER
- BIT-BLT, CHARACTER
DRAWING CONTROL
- DEFINES: TEXTURE, COLOR, LOGIC OPERATIONS,
CHARACTER ATTRIBUTES, DRAWING
AREA (BIT-MAP), ETC.
MOVE (DRAWING POINTER)
NON DRAWING
- NOP, LINK (JUMP), MACRO (SUBROUTINE),
INTERRUPT; LOAD/DUMP REGISTER
240048-6
Overview of Graphics Processor commands.
The Graphics Processor has 4 types of commands:
- Geometric drawing commands
- Transfer commands
- Drawing Control
- Non-drawing commands.
The GP commands provide a CGI-like graphics interface. These graphics primitives are extremely fast, since they
are implemented in hardware. The Geometric commands provide primitives for POINT, LINE, ARC, and CIRCLE. The INCREMENTAL_POINT, POLYLINE, POLYGON, and HORIZONTAL_LINE (SCAN_LINES)
commands can draw many points or lines with only one GP command for maximum efficiency. The SCAN_LINES
command is used for Area Fill.
The GP Transfer commands provide high-speed BLOCK DATA TRANSFER and Text CHARACTER support.
The Drawing Control commands provide settings for COLOR, TEXTURE, LOGICAL OPERATOR, DEFINING
BITMAPS, CLIPPING RECTANGLE, AND CHARACTER ATTRIBUTES.
,
The Non-drawing commands provide LINK, MACRO (SUBROUTINE) CALL and RETURN 'commands, as well
as an INTERRUPT and LOAD/DUMP REGISTER commands.
The LINE and CIRCLE commands are implemented by Breshenham's Algorithm (in a state machine).
10-169
AP-408
BIT BLOCK TRANSFER COMMAND
:
BIT·BLT
10
X
(0,0)
SOURCE X
SOURCE Y
DX
OX
(X,V)
DY
HALT
SOURCE
RECTANGLE
11
GCPP
OV
V
~
NEW GCPP
DESTINATION
RECTANGLE
BIT BLOCK TRANSFER
240048-7
Here is an example of a Graphics Processor command, showing the format of the Bit_Blit (Bit Block Transfer)
command. The opcode comes first followed immediately by its associated parameters, the Source X and Y co·ordinates and the width (dx) and height (dy). This command copies a block of data to the destination indicated by the
Graphics Current Position Pointer (GCPP).
10-170
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AP-408
GRAPHICS PROCESSOR DRAWING EXAMPLE
COMMAND LIST
GRO
GRl
t--.::.LlNc::.K'--J-".O-lV
ADDRESS lOW
BIT MAP
r-----------------------~
0,0
X
V
1-----1
GR2
ABSOLUTE MOVE
CIRCLE
RADIUS
ADDRESS HIGH
'----_......
RECTANGLE
OX
DV
LINE
OX
DV
RELATIVE MOVE
OX
DV
POLY LINE
AARA Y PXR LOW
ARRAY PXR HIGH
NUMOFLINES
,
,
L-.
HALT
DXl
DVl
,
DXN
DVN
240048-8
This Figure shows a specific example of a GP command list and its resultant drawing in the bit map. This. demonstrates the capability of the Graphics Processor and how easy it is to create a drawing using the built-in graphics
commands.
This GP command list example shows the ABSOLUTE_MOVE, CIRCLE, RECTANGLE, LINE, and POLYLINE commands.
First, the CPU writes the command list into graphics memory. The GP command list is executed when its address
and the LINK instruction is written into the GP opcode registers.
The ABSOLUTE~OVE instruction moves the Position Pointer to the given (x, y) coordinate, the CIRCLE
command draws the circle with the given radius, the RECTANGLE command draws a rectangle with the given
width and height, the LINE command draws a line with the given offset for the endpoint. The POLYLINE
command draws a series of lines with only one GP command. The parameter for a POLYLINE command is a
pointer to an array of endpoints for several lines.
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82786 PROGRAMMING MODEL
82786
GRAPHICS
PROCESSOR
DISPLAY
PROCESSOR
DISPLAY IMAGE
GRAPHICS
MEMORY
GP COMMAND
LIST'
CPU
240048-2
In summary, to program the 82786 OP:.f1I'St the CPU writes a command list into graphics memory, as shown here.
We have seen the details of the command list structure and details of some of tjle OP commands.
The CPU instructs the OP to execute a command list by f1I'St writing the address of the command list into the OP
registers OR! and OR2, and then writing the LINK opcode into the OP Opcode Register, ORO.
The graphics processor then executes the command list and draws the images into the bitmaps.
10-172
AP-408
2.3 Display Processor Programming
This section describes general concepts of programming the Display Processor. As mentioned earlier, the DP reads a
Screen Descriptor List that was written in graphics memory by the host CPU. This descriptor list determines how
graphics data contained in the bitmaps is displayed on the screen in windows.
82786 SCREEN CONFIGURATION
BASIS OF HARDWARE WINDOW
• SCREEN IS DIVIDED INTO STRIPS
• EACH STRIP HAS SEVERAL TILES (MAX 16/STRIP)
• EACH TILE CAN DISPLAY DATA FROM DIFFERENT BIT MAP
• EACH TILE CAN HAVE DIFFERENT DEPTH (BITS/PIXEL)
• ANY TILE CAN BE ZOOMED (PIXEL REPLICATION)
•
j
TILES
STRIP 1
TILE 1
STRIP 2
TILE 1
STRIP 3
TILE 1
TILE 4
STRIP 4
TILE 1
TILE 3
UI
a.
ir
IUI
STRIP 5
TILE 1
240048-10
Explanation of Display Processor Screen. Descriptor List.
The 82786. uses a flexible and powerful method for describing the screen composition. The screen is described in
terms of Strips, each strip is composed of Tiles. Each tile can display data from a different bitmap of a different depth
(bits/pixel). Each tile may be zoomed independently. The screen format can be completely changed every frame
refresh cycle. (This is typically every 1/60 second.)
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DISPLAY PROCESSOR REGISTERS
INDIRECT
ACCESS REGISTERS
DIRECT
ACCESS REGISTERS
OFFSET40H
OP CODE
Eel
CURSOR ON 'OFF
PARAMETER'
INTERRUPT MASK
PARAMETER 2
PARAMETER 3
tNTERLACEINON-tNTERLACE
MASTER/SLAVE MODE
r
STATUS
4BH
DEFAULT VIDEO
42
ViDEO
TIMING
WORDS
PARAMETERS
DESCRIPTOR POINTER
ZOOM FACTOR
COLOR
PAD
REGISTERS
CURSOR PQSTlON
CURSOR
BIT
PAITERN
• DP INTERNAL REGISTERS
• DISPLAY CONTROL BLOCK REGISTERS
• ACCESS BY LOAD, DUMP
REGISTER COMMANDS
240048-11
The Display Processor has 2 sets of registers: directly accessible and indirectly accessible.
The Directly accessible registers include: An Opcode register, three parameter registers, and a Status Register.
The Indirectly accessible registers are also known as the DP Control Block Registers. These registers contain
parameters for controlling DP operations such as the Video Timing Signals, location of the Descriptor list, cursor
position, cursor pattern, etc. The indirectly accessible registers are loaded with the DP LOAD and DUMP commands.
10-174
Ap·408
HOW TO CHANGE SCREEN FORMAT
GRAPHICS MEMORY
82786
DP DIRECT ACCESS
REGISTERS
OP CODE
LOAD· REG
PARAMETER 1
ADDRESS LOWER
PARAMETER 2
ADDRESS HIGHER
PARAMETER 3
REG 1.0.
}
[
DESCRIPTOR POINTER LOWER
DESCRIPTOR POINTER UPPER
NEW DP
DESCRIPTOR
LIST
240048-12
The screen format is changed by writing a new Descriptor list into graphics memory or modifying a copy of the
current descriptor list. Next, a pointer to the new descriptor list is written into graphics memory. Lastly, the address
of the pointer, the LOAD_REG command, and. register ID (OE Hex for Descriptor Address Pointer) are written
into the DP parameter and opcode registers. .
This is all that is necessary to change the screen format. The new screen appears during the next screen frame.
10-175
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HOW TO DEFINE THE STRIP
DISPLAY PROCESSOR DESCRIPTOR LIST
STRIP
HEADER
TILE
DESCRIPTOR
NUMBER OF LINES IN STRIP
LINK TO NEXT STRIP HEADER
NUMBER OF TILES IN STRIP
BITMAP WIDTH
START ADDRESS
TILE WIDTH
BORDEI:tS
I ZOOM I FIELD
240048-13
As mentioned earlier, a Screen Descriptor List is composed of Strip and Tile descriptors. Here, we see an overview of
a strip and tile descriptor. See Figure 3.2 for a more detailed diagram of a strip and tile descriptor.·
.
The Strip descriptor contains the number oflines in the strip, link to the next strip descriptor, and the number of tiles
in the strip. .
The Tile Descriptor contains the width of the source bitmap, the starting address of graphics data to be displayed,
the tile width, and settings for turning borders, zoom and field color on or off. Each tile has its own tile descriptor.
10-176
AP-408
SCREEN CONFIGURATION EXAMPLE
SCREEN
DESCRIPTOR LIST
HEADER
STRIP 1
500 LINES
LINK
2 TILES
BITMAP WIDTH
DESCRIPTOR
TILE 1
START ADDRESS
TILE WIDTH
BORDERS ZOOM
SCREEN
t-
12BO
-,
+-------PIXELS------+
600
"-'-'PIXELS----+
t
STRIP 1
500
LIT
1024
LINES
1
DESCRIPTOR
TILE 2
STRIP 2
524
524 LINES
HEADER
STRIP 2
LlTS
1 TILE'
DESCRIPTOR
TILE 1
240048-16
Here. we see an example of a Descriptor List and its resultant display screen. The first strip. containing 500 lines
vertically. is composed of two tiles. The second strip. containing 524 lines vertically. is composed of one tile.
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82786 PROGRAMMING MODEL
DISPLAY IMAGE
GRAPHICS
MEMORY
CPU
240048-2
In summary, to program the 82786 DP: first the CPU writes a DP descriptor list into graphics memory, as shown
here. We have seen the details of the descriptor list. The display processor reads this descriptor list to determine how
graphics data contained in the bitmaps is displayed on the screen in windows.
The screen format may be changed by simply writing a new ,descriptor list into graphics memory and changing the
Descriptor Pointer to point to the new Descriptor List.
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2.4 Bus Interface Unit
This section describes an overview of programming the Bus Interface Unit.
The Bus Interface Unit is programmable and controls the following functions:
o The base address for access of the 82786 registers
• The Graphics Memory Configuration
- VRAM/DRAM type
- Memory Access Mode
- Bank Configuration
- DRAM Refresh frequency.
• Memory Access Priority
- Sophisticated Bus Access Arbitration
- 8 Priority Levels
BUS INTERFACE UNIT REGISTERS
OFFSETOOH
REGISTER BASE ADDRESS
J
MIO
BIU CONTROL
REFRESH CONTROL
DRAMNRAM CONTROL
DP PRIORITY
GP PRIORITY
OE
EXT CPU PRIORITY
• SYSTEM CPU/MEMORY INTERFACE PROGRAMMING
• GRAPHICS MEMORY CONFIGURATION
• MEMORY ACCESS PRIORITY
240048-18
Programming the BIU is simple and straightforward. The programmer must simply write the correct values into
each of the seven BIU registers. After these registers have been set, they do not need to be changed unless the chip is
reset. The GP, DP and CPU priorities may be changed at any time, if desired.
2.5 Summary
This concludes the overview of the 82786 programming modeL We have seen an overview ofthe powerful Graphics
commands and how these commands are used.
We also talked about the concepts of programming the Display Processor and how to use the powerful hardware
windowing capabilities of the 82786.
Chapter 3 provides a specific programming example and more specific programming details.
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CHAPTER 3 EXAMPLE PROGRAM
3.0 INTRODUCTION
This Chapter presents an example 82786 program written in 80286 Assembly Language. The objectives of the
Example program are:
1) Initialize the 82786 registers
2) Program the Display Processor (DP) for one full-screen window
3) Draw a simple graphics image using the Graphics Processor (GP).
Section 3.1 presents an overview of the program. Section 3.2 presents a detailed explanation of the program, section
by section. Section 3.3 presents the complete source-code listing.
3.1 Overview Of Example Progra'm
3.1.0 PROGRAM OUTLINE
Constant Definitions
- Special Addresses
- DP Opcodes
- GP Opcodes
Register Segment
- Define 82786 Internal Register Block Addresses
Data Segment
- Define DP Control Block Register Values
- Define DP Descriptor List .
- Define GP Command List
Code Segment
- BIU Initialization-Load BIU Registers
- <;::lear Page 0 of Graphics Memory
- Copy DP Control Block Registers from CPU Memory to Graphics Memory
- Copy DP Descriptor List from CPU Memory to Graphics Memory
- Copy GP Command List from CPU Memory to Graphics Memory
- ·Start DP by Loading DP Control Block Registers
- Execute GP Command List to Draw Image
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Program Outline
82786 Graphics Memory
Bitmaps
IBM AT System Memory
~_:_.II
82786
Orllphh:. ProcellOr
DJ.pl.y Proc...or
Control Block
~~~~'__y.I~~R_.gl_d.r_·~1
DP_Control Block
flegl.tl,.
LCtaId_AII
DP_VCon·I~,toBrl".ktl
--
FFOOO
I
DP D•• crlptor UI'!
Real,'.r.
'I Deacrtplor Pointer
/ .
i
i
/
- i"---..
-....I..-----','-FFtOO
Unk
DP
DlI~tor I~
'-----"'--~::::::::~_[
Ult
, / FF200
GP Commlnd ust!
~
:I
,
I
J
- - - QP Command Ult
240048-19
Figure 3.1
3.1.1 OVERVIEW OF PROGRAM
Figure 3.1 shows a graphical description of the Example program.
First, the correct values are written into the 82786 BIU Registers.
Section 3.2 explains how the values for these registers have bee~ determined.
Next, Page 0 of graphics memory is cleared (used for bitmaps).
Next, values for the DP Control Block Registers, DP Descriptor List and GP Command List are copied from CPU
memory space to Graphics memory space.
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The values for the DP Control Block Registers are loaded from graphics memory into the 82786 registers by the
DP LOAD-.ALL command. Two of the DP Control Block Registers, the Descriptor Pointer Upper and Descriptor
Pointer Lower, are combined to give a 22-bit address. This is the address of a valid DP Descriptor List located at
location FFlOO in graphics memory. The DP Descriptor List instructs the DP to fetch bitmap data starting at
location 0 in graphics memory.
Now the Graphics Command list is executed by writing its address into the GP Parameter Registers and then
writing a LINK command into the GP Opcode Register. The GP now draws the image into the graphics memory
bitmap area.
3.2 A Detailed Description of the Example Program
3.2.0 TECHNICAL FACTS
This section provides technical facts used in the Example program.
Graphics Memory Addressing:
The graphics board uses 64 Kbytes of CPU address space from AOOOO to AFFFF. The page selection register
chooses one of 16 pages. This allows addressing of a total of I Megabyte of graphics memory.
The page selection register. on the graphics board is set by outputting the page number (using the 80286 OUT
instruction) to port lo~ation OxOO300. This technique will vary on other hardware systems using the 82786.
Bitmap Location:
The example program stores bitmaps in Graphics memory starting at location O.
Graphics Command Buffer Location:
Starts at Graphics memory location FF200
Display Processor Descriptor List Locatiori:
DP Descriptor list FFlOO (base address in graphics memory)
82786 Register Access:
The 82786 Internal Register Block is accessed by memory access to CPU memory locations C4400 through C447F.
The Graphics board decodes these addresses and issues an 1/0 access.
Video Timing Parameters:
The initialization values for the video timing parameters assume an 18 MHz VCLOCK.
Assembler:
The example programs were assembled with the Microsoft Macro Assembler Version 4.0
10-182
AP-40B
3.2.1 CONSTANT DEFINITIONS
SEG_GR_MEM
SEG_786_REG
DP_REG_MAP
;*****************
equ OAOOOh
equ OCOOOh
equ OFOOOh
*****************
Program Constant definitions:
Segment to access graphics memory.
Segment to access 82786 registers.
Address in graphics memory used to load
DP control values to/from DF registers
DP_REG_MAP_LO
DP_REG_MAP_HI
DESC_PTR_LO
DESC_PTR_HI
GP_LIST_PTR_LO
GP_LIST_PTR_HI
BITMAP_O_LO
BITMAP_O_HI
PAGE]ORT
equ
equ
equ
equ
equ
equ
equ
equ
equ
DP_REG_MAP
OOOOFh
OFlOOh
OOOOFh
OF200h
OOOOfh
OOOOh
OOOOh
0300h
DP Discriptor List address in graphics memory
Address in graphics memory of GP command list
Starting address of bitmap_O (lower byte)
Starting address of bi tmap_O (high byte)
I/O address for graphics mem page select reg.
;********************
Display Processor opcodes:
;********************
Graphics Processor opcodes:
LOADREG
LOADALL
DUMPREG
DUMPALL
equ
equ
equ
equ
400h
500h
600h
700h
ABS_MOV
ARC_EXCL
ARC_INCL
CIRCLE
DEF_BITMAP
DEF COLORS
DEF=LOGICAL_OP
DEF_TEXTURE_OP
LINE
LINK
POINT
~tTMOV
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
*************************
4FOOh
6800h
6900h
BEOOh
lAOOh
3DOOh
4l00h
0600h
5400h
0200h
5300h
************************
:~~ ~;g~~
240048-33
3.2.2 LOCATIONS FOR THE 82786 INTERNAL REGISTER BLOCK
The REGISTER SEGMENT defines a template of locations for access to the 82786 Internal Register Block. The
register segment is set to begin at memory location OC440 (hex). As mentioned above, the Intel board issues an I/O
access when .the CPU accesses memory at addresses C4400-C447F.
;*********** Locations for the 82786 Internal Register Block:
register SEGMENT at OC440h
INTER_RELOC
db 2 DUP(?)
dw (7)
BIU_CONTROL
db 2 DUP (7)
DRAM_REFRESH
dw (7)
DRAM_CONTROL
dw (7)
DP_PRIORITY
dw (7)
dw (7)
GP_PRIORITY
dw (7)
EXLPRIORITY
dw 8 DUP (7)
GP_OPCODE_REG
dw (7)
GP_PARM1_REG
dw (7)
GP_PARM2_REG
dw (?)
GP_STAT_REG
dw (7)
dw 12 DUP (7)
dw (?)
DP_OPCODE_REG
DP_PARM1_REG
dw (7)
DP_PARM2_REG
dw (7)
DP_PARM3_REG
dw (?)
DP_STAT_REG
dw (7)
DEF_VIDEO_REG
dw (7)
register ENDS
*************
Internal Relocation Register
reserved location 13 62786 Register Block
BIU Control Register
DRAM Refresh control register
DRAM control register
DP priority register
GP priority register
External Priority Register
reserved location. in 82786 Register Block
GP opcode register
GP Parameter 1 Register
GP Parameter 2 Register
GP Status Register
reserved locations in 82786 Register Block
DP opcode register
DP Parameter 1 Register
DP Parameter 2 Register
DP Parameter 3 Register
DP Status Register
DP Default Video Register
240048-34
10-183
inter
AP·408
3.2.3 VALUES FOR DP CONTROL BLOCK
The following program segment defines values for the Display Processor Control Block. Refer to the 82786 User's
Manual for an explanation of each register. The comments in the program explain this setting used in our example.
data SEGMENT
;************* Values for the Display Processor Control Block:
beg_dp_ctrl_blk LABEL word
REGISTER NAME
SETTING
dw
dw
dw
dw
dw
dw
3
llllh
00010h
OOOOOh
OOOOOh
OOOOOh
Video Status'
Interrupt Mask
Trip Point
Frame Interrupt
Reserved
CRT Mode
*************
cursor ON, and display ON
all interrupts disabled
controls when DP fifo is loaded
no interrupts on frame count
non-interlaced, window status off.
DP, master mode Blank master mode I
acceleration mode off
The following 8 registers contain the video timing parameters for a screen
resolution of 640 X 381 pixels.
These values assume VeLOeR = 18MHz.
These values achieve a .screen refresh of 60 Hz.
dw
dw
dw
dw
dw
dw
dw
dw
86
95
735
753
11
15
396
398
Hsyncstp
Hfldstrt
Hfldstp
Linelength
Vsynstp
Vfldstrt
Vfldstp
Framelength
dw DESC_PTR_LO ; DP de.cr ptr low
dw DESC_PTR_HI ; DP descr ptr high
Reserved
Zoom factor
X-zoom
2, Y-zoom
2
dw 00006h
Field color
dw 00003h
Border color
dw OOOOOh
1 BPP pad
dw OOOOOh
2 BPP pad
dw OOOOOh'
4 BPP pad
dw OAOFFh ; Cursor Style
Size
16 X 16, transparent, cursor pad
dw 500 ; Cursor X-position
dw 160 ; Cursor Y-position
dw OOOOOh
dw 00101h
~~eo~g~~~~i~~o6go~~~isters define the cursor bit pattern (an upward arrow):
dw OOOOOOll10000000b
dw 0000011111000000b
dw 0000111111100000b
dw 000l111111110000b
dw 0011111111111000b
dw Oll1011111011100b
dw 110000lllOOOOllOb
dw 0000001110000000b
dw OOOOOOll10000000b
dw 000000l110000000b
dw 000000l110000000b
dw OOOOOOl110000000b
dw 000000l110000000b
dw 000000ll10000000b
dw 0000001110000000b
end_DP_ctrl_blk LABEL word
240048-35
10·184
inter
AP-408
3.2.4 DISPLAY PROCESSOR DESCRIPTOR LIST
The following program segment defines a Display Processor Descriptor List. The DP reads the Descriptor List every
frame, starting over at the beginning of the Descriptor List during vertical retrace. The Descriptor List determines
the graphics memory addresses from which display data is fetched.
A Screen Descriptor List is composed of a header for each strip and a Tile Descriptor for each tile in a strip. (See
Figure 3.2)
15
14
13
12
11
10
9
B
7
6
5
4
3
2
0
HEADER
I
I
NUMBER OF UNES IN STRIP· 1
LINK TO NEXT STRIP DESCRIPTOR (LOWER)
011
15
FIRST
TILE DESCRIPTOR
Il
II
SECOND
TILE DESCRIPTOR
JII ~UIIBER
OF TILES
IN STRIP· 1
RESERVED
14
13 12
11
10
9
B
7
6
5
4
3
2
0
J
BITMAP WIDTH
MEMORY START ADORESS (LOWER)
II
II
II
II
UNK TO NEXT STRIP
DESCRIPTOR (UPPER)
111
RESERVED
III
RESERVED
RESERVED
RESERVED
T
B
L
15
14
13
II
II
'I
I
'I
R
II
II
II[
12
111
BPP
MEMORY START
ADDRESS (UPPER)
III
STARTBIT
STOPBIT
J
FETCH COUNT
WST
11
JII
10
1101010
RESERVED
9
8
7
6
5
4
3
2
J
BITMAP WIDTH
MEMORY START ADORESS (LOWER)
II T
RESERVED
II
III
RESERVED
RESERVED
B
L
R
0
111
BPP
III
STARTBIT
FETCH COUNT
WST
III
RESERVED
••
•
Figure 3.2
10-185
MEMORY START
ADORESS (UPPER)
III
STOPBIT
I
I
I
J
1101010
240048-20
inter
AP-408
3.2.4.1 Strip Header
The Strip Header defines the number of scan lines in the strip, the address of the next Strip Descriptor (link), and the
number of tiles in the strip. The descriptor list in our example defines one strip, 381 lines long, composed of one tile,
80 bytes wise (640 pixels).
3.2.4.2 Tile Descriptor
The Tile Descriptor defines the Bitmap Width, Memory Start Address, BPP, StartBit, StopBit, Fetch Count, Border
Control bits, Window Status (Window ID number), Zoom Control, and Field Tile Control.
The Bitmap Width gives the width of the source bitmap as defined by the GP DEF_BITMAP command when the
bitmap was drawn.
NOTE:
The Bitmap Width value is not related to the tile width.
The Memory Start Address determines the beginning location in graphics memory where data is to be fetched for a
given tile. This address is not necessarily the beginning address of the bitmap. If the Memory Start Address is higher
than the beginning address of the bitmap, the tile will contain an image beginning at the corresponding location in
the bitmap.
The width of a tile is determined by the FETCH COUNT value of the tile descriptor. The FETCH COUNT
determines the amount of data to be fetched from graphics memory and displayed in a given tile. The value to be
programmed into FETCH COUNT is the (Number of bytes - 2).
Fetch Count can be determined as follows:
FETCH COUNT = (Desired tile width in pixels • bpp/8) - 2
The bitmap in our example is 1 bpp and the desired tile width is 640 pixels; therefore:
FETCH COUNT
=
(640 • 1/8) - 2
=
78.
BPP is a 4-bit field containing the bpp of the source bitmap as defined by the DEF_BITMAP when the bitmap was
drawn.
The STARTBIT and STOPBIT fields are both 4-bits wide. Although FETCH COUNT is specified as a number of
bytes, STARTBIT and STOPBIT are specified as a bit location within a word (O-F). These fields give pixel
resolution to the beginning and ending of a tile. In our example, the STARTBIT is F and the STOPBIT is O. It is the
responsibility of the programmer to ensure that the STARTBIT and STOPBIT settings result in a valid number of
bits for the given bitmap depth (bpp). For example, when the bitmap is 4 bpp, the total number of bits fetched must
be a multiple of 4. See Figure 3.3.
10-186
infef
AP-408
Tile Width
60 Pixels (1 Bit/Pixel)
Stop : i t \
liS;ort Bit
F
0
I
M
I
I
I
I
I
~
J
I
Number of words fetched
240048-21
FETCH COUNT
~
~
(numbers of words fetched' 2) - 2
(number of bytes fetched) - 2
Figure 3.3. STARTBIT and STOPBIT
Valid STARTBIT and STOPBIT Values
Bits/Pixel
Valid STARTBIT
Valid STOPBIT
F,E,D,C,B,A,9,B,7,6,5,4,3,2,1,0
1
F,E,D,C,B,A,9,B,7,6,5,4,3,2,1,0
2
F,D,B,9,7,5,3,1
E,C,A,B,6,4,2,0
4
F,B,7,3
C,B,4,0
B
F,7
B,O
Field Tiles
When the field bit (bit zero of the last word) in a tile descriptor is set to one, the tile is filled with the color
programmed in the FIELD COLOR register. When the field bit is set, the STARTBIT, STOPBIT, and BPP
parameters become one 12-bit parameter that specifies the tile width in pixels. All other bits except WINDOW
STATUS and Zoom should be programmed to zero. Although field tiles are not used in our examples, they are
useful for filling a tile with a solid color. See Figure 3.4.
15 14 13 12 11 10 9 8 7 6 5 4 3 2· 1 0
BianapWidth
Memory Stan Address (U>wer)
I Mem Stan Addr (Upper)
Reserved
I
Bpp
I StanBit
I StopBit
Reserved
Fetch Cou .t - 2 (tile width in bytes)
I
T B L R I WSt I
Reserved
15 14 13 12 11 10 9 8 7 6 5
4
I PC I zl F
3 2 1 0
Normal
Tile Descriptor
i]
Reserved
Reserved
Field
TIle Decsriptor
I Reserved
Field Pixel Count - 1 (tile width in pixels)
Reserved
Reserved
Reserved
I
Reserved
Reserved
IReserv~ Z I F
WSt I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1.
~
=1
240048-22
NOTE:
Reserved fields must be programmed to zero for future compatibility.
Figure 3.4
Refer to the Intel 82786 User's Manual for more information on the Display Processor Descriptor List.
10-1 B7
inter
AP-408
;************ Definition of Display Processor Descriptor List:
************
dp_descl LABEL word
; Header of DP descriptor:
dw 380
(number of lines - 1)
dw DESC_PTR_LO+20
lower link to next strip descriptor (there is none,
but i f one were added, this is the link)
dw DESC_PTR_HI
upper link to next strip descriptor (there is none)
dw 0
; (number of tiles - 1)
First (and only) Tile Descriptor
dw 0080
Bitmap width (number of bytes)
dw OOOOh
Bi tmap start address lower
dw OOOOh
Bi tmap start address upper
dw OlFOh
1 bpp, start bit F, stop bit 0
dw 0078
Fetch count = (number of bytes - 2)
dw OFOOOh
; All 4 borders on,window status=O,PC mode off,field off
end_dp_descl LABEL word ; *********** End of DP descriptor list. *********
240048-36
3.2.5 GRAPHICS PROCESSOR COMMAND LIST
The following program segment defines a Graphics Processor Command List.
A GP command list consists of a series of GP opcodes and parameters. The Graphics Processor reads and executes
the command list, until a halt instruction is encountered.
The first command (DEF_BITMAP) sets the beginning address in graphics memory of the bitmap to be modified.
This command also sets the bitmap dimensions and the number of bits per pixel (bpp) of the bitmap. All subsequent
drawing commands will affect this bitmap until a new DEF_BITMAP command is issued. It is the resonsibility of
the programmer to ensure the BPP in the tile descriptor is the same as the BPP used by the GP when drawing the
picture.
Bitmaps must begin at a word (even byte) address. Also, a bitmap must be an integral number of words wide. The
value for xmax must satisfy the following equation:
[(xmax
+ 1) • bpp]
MOD 16 = 0
Next, the DEF_TEXTURE, DEF_COLORS, and DEF_LOGICAL_OP commands are issued. These settings
stay in effect for all subsequent drawing commands. They can be reset whenever necessary.
Next, an ABS~OVE command is issued to move the Graphic Current Position Pointer (GCPP) to the beginning
location of the drawing. The remainder of the GP Command List in our Example is composed of REL_MOV,
LINE, and ARC_INCL commands.
Figure 3.5 illustrates the result of the command list in the example program.
The HALT command at the end of the GP command list is very important. The GP continues execution until it
encounters a HALT instruction (a NOP with the ECL bit set). If the HALT instruction is not present, the GP will
continue fetching and trying to execute instructions until it reaches a "command" with the low bit set.
Several different GP command lists may be kept in graphics memory at the same time. Each command list maybe
executed by writing the appropriate address into the GP parameter registers and then writing a LINK command into
the GP Opcode Register.
10-188
inter
AP-408
(0,0)
,ASS_t.lOV, 10,10
1':' 1"'' '
REL_t.lOV, "
- 35,45:
,
,"
LINE, 35, 0
RECTANGLE,
35,135
2--:
ARCINCL,
-30,10, - 5, 35, - 5
240048-23
Figure 3.5
10-189
intJ
AP-408
;**********
Definition of Graphics Processor Command List:
gp_1i.t1 LABEL word
dwDEF_BITMAP, BITMAP_O_LO, BITMAP_O_HI, 639 , 380 , 1
address 10 . address hi
dw DEF_TEXTURE_OP, OFFFFh
dw DEF_COLORS, OFFFFh, OOOOOh
dw DEF_LOGI CAL_OP, OFFFFh, 00005h
X equ 10
Y equ 10
ABS_MOV, X, Y
LINE, 35,
0
solid texture
replace destination with source
Draw Intel logo:
************************
; Move to beginning position for drawing.
; Dot the "1"
LINE,
0, 35
LINE, -35,
0
LINE,
0, -35
REL_HOV, 0, 45
dw
LINE,
35,
dw
dw
dw
LINE,
LINE,
LINE,
0, 135
-35, 0
0, -135
dw
REL_HOV"
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
d..
dw
dw
dw
d..
d..
d..
dw
d..
dw
d..
dw
LINE, 35, 0
LINE, 0 , 12
REL_HOV, 0, 32
LINE, 0, 90
LINE, -35, 0
LINE, 0, -135
REL_HOV, 51, 47
ARC_INCL, -20, -20,
REL_HOV, 12, -4
ARC_INCL, -27, -50,
REL_HOV, 5, 3
LINE, 0, 90
LINE, 35, 0
LINE, 0, -105
REL_HOV, 15, 90
LINE, 0, -95
LINE, -12,0
LINE, 0, -25
LINE, 12, 0
LINE, 0, -45
LINE, 35,0
LINE, 0,45
LINE, 15,0
LINE, 0, 25
LINE, -15, 0
LINE, 0, 77
LINE, 15, 0
REL_HOV, 0, 30
LINE, -31, 0
REL_HOV, 5, -25
dw
xmax, ymax, bits per pixel
I
; X-coordinate of starting location for drawing
; V-coordinate of starting location for drawing
;*************************
dw
dw
dw
dw
dw
dw
************
0
42. 0
Draw body of "1"
re-po.si tion for "N"
Draw "N"
40, 0, 16
50, -10, 42
re-position to drsw "t"
ARC_INCL. -30, 10, -5, 35, 25
d.. REL_HOV, 60 , - 5
dw LINE, 45,0
dw REL_HOV, 31, 0
dw LINE, 6,0
dw LINE, 0, -150
Draw "1"
dw LINE, 35, 0
dw LINE, 0, 180
dw LINE, -120, 0
dw REL_HOV, 52, 10
dw LINE, 37, 0
dw REL_HOV, -65, -40
dw ARC_INCL, -30, -30, 30, 0, 22
dw ARC_INCL, -65, -65, 65, 0, 54
dw REL_HOV, 2, 30
dw ARC_INCL, -30, 0, 25,30,,27
dw REL_HOV, 3, 0
d" ARC_INCL, -65, 0, 59, 65 ,60
dw HALT
1en_BP_1ist1 LABEL word
; draw curve at lower left of "t"
Draw "e"
240048-37
10-190
AP·408
3.2.6 PROGRAM CODE SEGMENT HEADER
;************************
main:
mov ax. data
mav ds. ax
mav aX,register
Program execution begins here.
********~**********
Load data segment location
into DS register
mav eS,ax
240048-38
This section of code provides a standard Assembly Language program header. This code loads the DS (Data
Segment Register) and the ES (Extra Segment Register). The ES register is used to access the 82786 Internal
Registers.
3.2.7 SOFTWARE RESET
i*********************** Software Reset of 82786 ***************************
To reset the 82786 on the Intel Evaluation Board (Rev C2):
Set and then reset bit 4 at I/O location 300.
mov aX,D010h
mov dX,PAGE_PORT
out dX,ax
Set hit 4 at I/O location 300.
mav aX,OOOOh
out dX,ax
Reset bit 4 at I/O location 300.
240048-39
This section of code performs a reset of the 82786 by setting and then resetting bit 4 of the CPU I/O port 300 (hex).
.
The EVB then issues a reset signal to the 82786 RESET pin.
3.2.8. BlU INITIALIZATION
The following sections of code initialize the 82786 Bus Interface Unit (BIU). BIU initialization is accomplished by
writing the correct values into each of the BIU registers. A brief description of each register follows.
3.2.8.1 Internal Relocation Register
The following two lines write a value of 0110 (hex) into the internal
relocation register. This sets the 82786 registers for I/O - mapped
access at I/O locations 4400 through 447F.
The Intel Evaluation Board
decodes a CPU memory access at memory locations C4400 through C447F and
generates an I/O access to the 82786.
and byte mode after reset.
The 82786 comes up in I/O mode
Access to the registers must be one byte
at a time until WORD mode is set.
mov INTER_RELOC,lOh
; Write low byte into internal relocation register.
mov INTER_RELOC[l],Dlh
; Write high byte into internal relocation register.
240048-41
The INTERNAL RELOCATION register is set first. The 82786 comes up in byte mode after RESET; therefore,
this register is set by writing one byte at a time.
The desired base address for the 82786 registers is 004400 (hex). The base address must always be located on a 128
word boundary. (The registers are accessed at locations 004400 through 00447F.) An 82786 address is 22 bits long.
The upper 15 bits of the desired base address is written into the upper 15 bits of the Internal Relocation Register.
10-191
AP·408
We want to set the chip for I/O mode, therefore, a zero is written into the M/IO bit. Therefore, we write a value of
0110 (hex) into this register. See Figure 3.6.
BIU
Internal Relocation Register
00
0000
0100
0100
0
o
0
4
4
0
-----
+
Desired Location of 82786 Registers
000
=
0000
4400-447F
Upper 15 bits of Base Address
I
-----------~ I MilO
+-E
0000
0001
0001
0000
I
0
Value written in register = 0110 Hex
Figure 3.6
3.2.8.2 BIU Control Register
The following two lines write a value of 0011 (hex) into the BIU control
register. This sets the Internal Register Block for l6-bit WORD access
by the External CPU. All subsequent access to the 82786 registers i5 by
; WORD access.
mov BIU_CONTROL,lOh
; Write low byte into BIU control register
mov BIU_CONTROL[ll,OOh
; Write high byte into BIU control register
240048-42
These two lines set the BIU Control Register. Because the 82786 is in byte mode after RESET, this register is written
one byte at a time. After setting this register for word mode, all subsequent register access is by word mode.
BIU Control Register
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
o
I
Unused
6
5
4
3
2
0
0
1
0
0
0
0
VR
WT
BCP
GI
DI
WP1
WP2
0
Figure 3.7
The BIU Control Register has seven one-bit fields as shown in Figure 3.7. The settings for our Example program
follow:
VR = 0
Set for conventional DRAM memory cycles (not VRAM).
WT =0
Number of wait states in synchronous 80186 interface. The synchronous 80186 interface is not used in our example;
therefore, this is a "don't care" setting.
Bep = I
This sets the External CPU for 16-bit word access.
GI and DI
When the 82786 issues an'interrupt, these two bits can be read to determine which processor has issued the interrupt,
then either the DP or GP Status Register can be read to determine the cause of the interrupt.
10-192
AP-408
WPI and WP2
The write protect bits are not set in our Example program.
3.2.8.3 DRAM Refresh Control Register
mav DRAM_REFRESH,0018h
j
Write value into DRAM refresh control register.
240048-43
This register is programmed with a 6-bit Refresh Scalar for controlling the frequency for DRAM refresh cycles.
The value programmed in this register depends on the refresh requirements of the DRAMs, the clock speed, and the
number of DRAM row addresses. The value for the Refresh Scalar can be calculated by the following formula:
T,et xCLK
_ 1
16 x Refresh Rows
Where:
T ref = Refresh Time interval
CLK = 82786 System Clock speed
Refresh rows = Number of DRAM rows requiring refresh
In our example, we have:
4 msx20 MHz
..:...:.:.:.:...:.:-=..:...:.:.= - 1 = 18.53
16 x 256
NOTE:
DRAM refresh cycles can be turned off by programming a value of 3F (hex) into the DRAM Refresh Register.
3.2.8.4 DRAM Control Register
mov DRAM_CONTROL, OOlDh
; Write value into DRAM control register.
240048-44
Figure 3.8. DRAM/VRAM Control Register
15
14
13
12
o
o
o
o
11
10
9
8
7
o
o
o
o
o
Unused
6
5
o
o
RW1
RW2
4
3
2
DC1
DCO
HT2
o
o
HT1
HTO
The DRAM Control Register has seven one-bit fields as shown in Figure 3.7. The settings for our Example program
follow:
RWI and RWO indicate the number of rows of graphics memory.
RWI = 0, RWO = indicates one row of graphics memory.
DCl and DCO indicate DRAM/VRAM configuration.
DCl = I, DCO = 1 indicate Fast Page Mode, Interleaved.
HT2, HTl, and HTO indicate the DRAM/VRAM Height of graphics memory.
HT2 = I, HTl = 0, HTO = 1 indicates 256K x N-type DRAMs.
°
10-193
inter
AP-408
3.2.8.5 Display Processor, Graphics Processor and External Priority Registers
mov DP_PRIORITY, 003Fh
Write value into DP priority register.
mov GP_PRIORITY,0009h
Write value into GP Priority register
mov EXT_PRIORITY,0028h
Write value into External Priority register.
240048-45
DP Priority
I
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
5
I0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
First
Priority
Reserved
0
2
Second
Priority
0
First
Priority
Reserved
External
3
First
Priority
Reserved
GP Priority
4
0
Second
Priority
0
0
0
Reserved
Bus access priorities are programmable for the GP, DP and External Processor. Note that DRAM refresh is not
programmable and always has highest priority. The First Priority Level (FPL) is used to obtain bus access; Secondary Priority Level (SPL) is used to keep the bus when another processor makes a request. The highest priority is 111
(binary). The lowest priority is 000. Refer to the "82786 User's Manual" Section 4.3-Bus Cycle Arbitration.
In our Example program, DP has highest priority, External CPU has second priority, and GP has lowest priority.
NOTE:
These priorities may be changed at any time during program execution.
3.2.9 CLEAR PAGE 0 OF GRAPHICS MEMORY
j
***************
movax,SEG_GR_MEM
mov ds, ax
***************
Clear Page 0 of Graphics memory (64K bytes):
Graphics memory space is in the 'A' segment
mov ax,O
mov dx,PAGE_PORT
out dx. ax
Select page 0 of graphics memory
mov bx,O
mov cx,32767
mov 51,0
CLEAR_MEMORY:
mov (51], bx
add 51,2
loop CLEAR-HEMQRY
Clear page 0 of graphics memory (to be
32767 word. of memory to be cleared = 64K byte.
used
85
a bitmap for drawing commands.)
240048-46
Page zero of graphics memory is used for storing the bitmap. Before drawing into the bitmap, it must be cleared
(filled with zeroes).
This section of code clears page 0 of graphics memory by writing zeros into each memory location. First, the segment
address of Graphics Memory space is written into the CPU DS register. Next, page zero of graphics memory is
selected by writing a zero into the Page Select Register on the Evaluation Board. The loop command is used to clear
32767 words (64 Kbytes) of memory.
The GP bit_blit command using logical operator 0, or the scan_lines command using color 0 may also be used as a
fast technique for clearing a section of graphics memory.
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3.2.10 PREPARE DS, ES, AND DIR FLAG FOR USE WITH REP MOVSB INSTRUCTION
;****** Prepare DS. ES. and Dir Flag for use with REP MOVSB instruction.
mov ax,OFh
******
mov dx.PAGE_PORT
out dX,BX
mov Bx,SEG
mov ds,ax
Select page F of graphics memory
beg_dp_ctrl_blk
Set data segment
mov ax.SEG_GR_MEM
mav eS,ax
and extra segment.
cld
Clear Direction Flag, sets auto-increment
of 51 and DI when using REP instruction.
240048-47
This section of code performs the necessary preparation for the next three sections: moving the DP Control Block,
DP Descriptor List, and GP command list from CPU memory to Graphics Memory.
Page F of graphics memory is the desired destination of these three blocks of data, .therefore page F of graphics
memory is selected by writing to the PAGE_PORT. Next, the Data Segment and Extra Segment registers are
written. Lastly, the Direction Flag is cleared. This is necessary to cause the string instruction to auto-increment the
SJ and DJ index registers.
3.2.11 COpy DP CONTROL BLOCK REGISTERS FROM CPU MEMORY TO GRAPHICS MEMORY
:***** Copy OP CONTROL BLOCK REGISTERS
lea ex, end_DP_ctrl_blk
from CPU memory to Graphics Memory.
****
sub ex, offset beg_dp_ctrl_hlk
lea s1. beg_dp_ctrl_blk
mov d1. offset OP_REG_MAP
Move CX bytes from DS:[SI] to ES:[OI]
rep movab
thus, copying DP Control Block Registers
from CPU memory to Graphic5 memory.
240048-48
This section of code copies the values for the DP Control Block registers from CPU memory to Graphics Memory
beginning at address FFOOO (hex).
3.2.12 COpy DP DESCRIPTOR LIST FROM CPU MEMORY TO GRAPHICS MEMORY
;*******
COpy DP Descriptor List from CPU memory to Graphics memory.
lea cx, end_dp_descl
sub cx, offset dp_descl
lea 51, dp_descl
mov di, offset OESC_PTR_LO
rep movsb
********
Move CX bytes from OS:[SI] to ES:[OI]
thus copying DP descriptor list from CPU
memory to graphics memory.
240048-49
This section of code copies the values for the DP Descriptor List from CPU memory to Graphics Memory beginning
at address FFIOO (hex).
3.2.13 COpy GP COMMAND LIST FROM CPU MEMORY TO GRAPHICS MEMORY
i*********
Copy GP command list from CPU memory to graphics memory;
*********
lea ex, len_gp_listl
sub cx, offset gp_Iistl
lea si, gp_listl
mov d1. offset
rep movsb
GP_LIST~PTR_LO
Move CX bytes from OS:[SI] to ES:[OI]
thus copying GP command list from CPU
memory to graphics memory.
240048-50
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This section of code copies the GP command list from CPU memory to Graphics Memory beginning at address
FF200 (hex). The labels in the program marking the beginning (gp_listl) and ending (Iell.-gp_listl) of the GP
command list provide a convenient method for determining the length of the GP command list. Commands may be
added or deleted from the command list, the program computes the number of bytes to be copied into graphics
memory.
3.2.14 START THE DISPLAY PROCESSOR
*********************
mov
mov
mov
mov
.
Start up the Display Processor:
DP_PARM1_REG,DP_REG_MAP_LO
DP_PARM2_REG,DP_REG_MAP_HI
DEF_VIDEO_REG,O
DP_OPCODE_REG, LOADALL
********************
parameter 1 for dp command
parameter 2 for dp command
Write 0 in Default Video register
Write opcode register, thus starting up
the Display Processor
240048-51
This section of code starts up the Display Processor. First, the address of the values for the DP Control Block
Registers are written into the DP Parameter registers. The lower part of the address is written into PARAMETER 1
Register; the upper part of the address is written into PARAMETER 2 Register. The Default Video Register is
assigned zero. Lastly, the LOAD ALL opcode is written into the DP OPCODE register, thus starting operation of
the DP by loading the values for the DP Control Block.
It is important to write the address for the LOADALL command into the Parameter registers before the
LOADALL command is written into the opcode register. If the LOADALL command is written first, the registers
.will be loaded immediately, from an erroneous location.
Now, all the pointers and data structures for the Display Processor are in place. The Descriptor Pointer now points
to a valid Descriptor List which points to a valid bitmap area in graphics memory. Refer to Figure 3.9.
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82786 Graphics Memory
Bitmaps
IBM AT System Memory
82786
Graphic. Proc•••or
oJaplay Prace••or
.,
,
Valu•• tor DP
Control Block
Regll'er •
/
r -Valu
-••-forl '.J-FFOOO
DP_Control Block
Ragllt .. a
DP_Control Blockr
I-----l
DP O•• crlptor Ua.
Regilt.,.
Load All
/
I o.lcrtptor Pointer
'"
/
-~ ~-----"-YrF·F1DD
......
I
'i
GP Command uat!
Jf/'-----,
W_""'U'I/ :
Unk
'-------"......-----!;;;;;;;;;:::::::::~-_J
.1
FF211D
- j GP Command Ult
a
I
J
---
240048-19
Figure 3.9
3.2.15 EXECUTE THE GRAPHICS PROCESSOR COMMAND LIST
command list: *******************
Execute the GP parameter
mov GP_PARH1_REG.GP_LIST_PTR_LO
1 for GP command
GP_PARH2_REG.GP_LIST_PTR_HI
parameter 2 for GP command
Write ope ode register, thus starting
mov GP_OPCODE_REG. LINK
execution of the GP command list.
*********************
MOV
240048-52
This section of code starts up the Graphics Processor. First the lower and upper address of the GP command list are
written into the GP Parameter Registers I and 2, respectively. Next, the opcode for the GP LINK command is
written into the GP opcode register. When a zero is written into the End of Command List (ECL) bit (lowest bit) the
GP begins execution. The LINK command causes the GP execution to continue at the indicated address.
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It is important to write the link address into the parameter registers before writing the LINK opcode into the opcode
register. If the LINK command is written first, the GP will begin execution immediately, executing an erroneous
command list. See Figure 3.10.
.
Execute GP Command List
• Write addresses of GP Command List into GP Parameter Registers
GP Parameter Registers
Lower Part of Address
-+
Parameter Register 1
Upper Part of Address
-+
Parameter Register 2
• Write GP opcode for Link command into GP Opcode Register
Offset
Opcode
20
Opcode
Parameter 1
22
Link Address Lower
Parameter 2
24
Link Address Upper
Status
26
Figure 3.10
3.2.16 TERMINATE PROGRAM
i************************
mov ah,4Ch
Terminate program:
int 21h
*************************
Call BIOS terminate fUnction
to return to MS-DOS operating 5ystem.
code ENDS
These two lines call the BIOS routine to return control to the operating system.
3.3 Example Source Code Listing
This section provides the complete source code listing of the EXAMPLE program.
******************************************************************************
Program name' EXAMPLE1.ASM
Description:
Initialize the 82786
~egisters.
program the Display
Processor (DP) for one full-screen window. and draw a
simple graphics image using the Graphics Processor (GP).
Direct questions to your nearest Intel Sales Off ice.
******************************************************************************
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*****************
;***************** Program Constant definitions:
SEG_GR_MEM
SEG_786_REG
DP_REG_MAP
equ OAOOOh
equ OCOOOh
equ OFOOOh
DP_REG_MAP_LO
DP_REG_MAP_HI
DESC]TR_LO
DESC_PTR_HI
GP_LIST]TR_LO
GP_LIST_PTR_HI
BITMAP_O_LO
BITMAP_O_HI
PAGE_PORT
equ
equ
equ
equ
equ
equ
equ
equ
equ
DP_REG_MAP
OOOOFh
OFlOOh
OOOOFh
OF200h
OOOOfh
OOOOh
OOOOh
0300h
Segment to
Segment to
Address in
DP control
access graphics memory.
access 82786 registers.
graphics memory used to load
values to/from DP registers
Df Discriptor List address in graphics memory
Address in graphics memory of GP command list
Starting address of hi tmap_O (lower byte)
Starting address of bitmap_O (high byte)
I/O address for graphics mem page select reg.
;********************
Display Processor opcodes:
;********************
Graphics Processor opcodes:
LOADREG
LOADALL
DUMPREG
DUMPALL
equ
equ
equ
equ
400h
500h
600h
700h
ABS_MOV
ARC_EXCL
ARC_INCL
CIRCLE
DEF_BITMAP
DEF_COLORS
DEF_LOGICAL OP
DEF_TEXTURE-OP
LINE
LINK
POINT
REL_MOV
HALT
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
*************************
4FOOh
6800h
6900h
8EOOh
1AOOh
3DOOh
4l00h
0600h
5400h
0200h
5300h
5200h
0301h
************************
i*********** Locations for the 82786 Internal Register Block:
*************
register SEGMENT at OC440h
INTER_RELOC
db 2 DUP(?)
Internal Relocation Register
d .. (7)
reserved location is 82786 Register Block
BIU_CONTROL
db 2 DUP (7)
BIU Control Register
DRAM_REFRESH
d .. (7)
DRAM Refresh control register
DRAM_CONTROL
d.. (7)
DRAM control register
dw (7)
DP priority register
DP _PRIORITY
GP priority register
GP_PRIORITY
dw (7)
External Priority Register
dw (7)
EXT]RIORITY
dw 8 DUP (7)
reserved locations in 82786 Register Block
GP opcode register
GP_OPCODE_REG
dw (7)
GP Parameter 1 Register
GP_PARMl_REG
dw (7)
GP Parameter 2 Register
GP_PARM2_REG
dw (7)
GP Status Register
GP_STAT_REG
dw (7)
reserved locations in 82766 Register Block
dw 12 DUP (7)
dw (7)
DP opcode register
DP_OPCODE_REG
DP_PARMl_REG
dw (7)
DP Parameter 1 Register
DP_PARM2_REG
dw (7)
DP Parameter 2 Register
DP_PARM3_REG
dw (7)
DP Parameter 3 Register
dw (7)
DP Status Register
DP_STAT_REG
DEF_VIDEO_REG
dw (7)
DP Default Video Register
regbter ENDS
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data SEGMENT
;************* Values for the Display Processor Control Block:
beg_dp_ctrl_blk LABEL word
; REGISTER NAME
SETTING
;
d ..
dw
dw
dw
dw
dw
3
1111h
00010h
OOOOOh
OOOOOh
OOOOOh
*************
---------------
; Video Status
; Interrupt Mask
; Trip Point
; Frame Interrupt
; Reserved
; CRT Mode
;
;
: cursor ON, and display ON
: all interrupts disabled
: controls when DP fifo is loaded
: no interrupts on frame count
: non-interlaced, window status off,
: DP master mode Blank master mode,
: acceleration mode off
The following 8 registers contain the video timing parameters for a screen
resolution of 640 X 381 pixels.
These values assume
VCLOCK = 18MHz.
These values achieve a screen refresh of 60 Hz.
dw
86; Hsyncstp
d"
9 5 ; Hfldstrt
dw
735 ; Hfldstp
dw
753 ; Linelength
dw
11; Vsynstp
dw
1 5 ; Vfldstrt
dw
396 ; Vfldstp
dw
398 j Framelength
dw DESC_PTR_LO ; DP descr ptr low
dw DESC_PTR_HI • DP descr ptr high
dw OOaDOh ; Reserved
dw 00101h j Zoom factor
: X-zoom = 2, Y-zoom = 2
dw 00006h ; Field color
dw 00003h
j
Border color
d" OOOOOh ; 1 BPP pad
dw OOOOOh ; 2 BPP pad
dw OOOOOh ; 4 BPP pad
dw OAOFFh
Cursor Style
: Size = 16 X 16, transparent, cursor pad
dw 500 ; Cursor X-position
dw 180 ; Cursor Y-position
The following 16 registers define the cursor bit pattern (an upward arrow):
dw 0000000100000000b
dw 0000001110000000b
dw 0000011111000000b
dw 0000111111100000b
dw 0001111111110000b
dw 0011111111111000b
dw 0111011111011100b
dw 1100001110000110b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
dw 0000001110000000b
end_DP_ctrl_blk LABEL word
j************
Definition of Display Processor Descriptor List:
dp_desc1 LABEL word
************
; Header of DP descriptor:
dw 380
;
dw DESC_PTR_LO+20;
;
(number of lines - 1)
lower link to next strip descriptor (there is none,
but if one were added, this is the link)
upper link to next strip descriptor (there is none)
dw DESC_PTR_HI
j
dw 0
(number of tiles - 1)
; First (and only) Tile Descriptor
dw 0080
; Bitmap width (number of bytes)
dw OOOOh
; Bi tmap start address lower
dw OOOOh
j
Bi tmap start address upper
dw 01FOh
; 1 bpp. start bit F. stop bit 0
dw 0078
; Fetch count = (number of bytes -' 2)
dw OFOOOh
All 4 borders on, window status=O, PC mode off, field off
end_dp_desc1 LABEL word; *********** End of DP descriptor list. *********
10-200
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;**********
Definition of Graphics Processor Command List:
************
gp_li.t1 LABEL word
dw DEF_BITHAP, BITHAP_O_LO, BITHAP_O_HI, 639 , 380 , 1
address 10 . address hi . xmax, ymax, bits per pixel
dw DEF_TEXTURE_OP, OFFFFh
dw DEF_COLORS, OFFFFh, OOOOOh
dw DEF_LOGICAL_OP, OFFFFh, 00005h
X equ 10
Y equ 10
solid texture
replace destination with source
; X-coordinate of starting location for drawing
; Y-coordlnate of starting location for drawing
;*************************
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
ABS_HOV. X. Y
LINE,
35,
0
LINE,
0, 35
LINE, -35,
0
LINE,
0, -35
REL_HOV, 0, 45
LINE,
35,
0
LINE, 0, 135
LINE,
-35, 0
LINE, 0,
-135
Draw Intel logo:
************************
; Move to beginning position for drawing.
; Dot the "i"
Draw body of "1"
dw REL_HOV, 42, 0
re-posi tion for "N"
dw LINE, 35, 0
Draw "N"
dw LINE, 0 , 12
dw REL_HOV, 0, 32
dw LINE, 0, 90
dw LINE, -35, 0
dw LINE, 0, -135
dw REL_HOV, 51, 47
dw ARC_INCL, -20, -20, 40, 0, 16
dw REL_HOV, 12, -4
dw ARC_INCL, -27, -50, 50, -10, 42
dw REL_HOV, 5, 3
dw LINE, 0, 90
dw LINE, 35, 0
dw LINE, 0, -105
dw REL_HOV, 15. 90
re-posltion to draw "t"
dw LINE, 0, -95
dw LINE, -12,0
dw LINE, 0, -25
dw LINE, 12, 0
dw LINE, 0, -45
dw LINE, 35,0
dw LINE, 0,45
dw LINE, 15,0
dw LINE, 0, 25
dw LINE, -15, 0
dw LINE, 0, 77
dw LINE, 15, 0
dw REL_HOV, 0, 30
dw LINE, -31, 0
dw REL_HOV, 5, -25
dw ARC_INCL, -30, 10. -5, 35. 25
;draw curve at lower left of "t"
dw REL_HOV, 60, -5
dw LINE, 45,0
dw REL_HOV, 31,0
dw LINE, 6,0
dw LINE, 0, -150
Draw "1"
dw LINE, 35, 0
d" LINE, 0, 180
d" LINE, -120, 0
dw REL_HOV, 52, 10
dw LINE, 37, 0
d" REL_HOV, -65, -40
d" ARC_INCL, -30, -30, 30, 0, 22
Draw "e"
dw ARC_INCL, -65, -65, 65, 0, 54
d" REL_HOV, 2, 30
dw ARC_INCL, -30, 0, 25,30 ,27
d" REL_HOV, 3, 0
dw ARC_INCL, -65, 0, 59, 65 ,60
d" HALT
len_lP_list1 LABEL word
data ENDS
10-201
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code SEGMENT
ASSUME cs: code, ds: data.
BS:
;************************
main:
mav ax, data
register
Program execution begins here.
*******************
Load data segment location
into DS register
mav ds,ax
mev ax,register
mov eS,ax
/'
;*********************** Software Reset of 82786
***************************
To reset the 82786 on the Intel Evaluation Board (Rev C2):
Set and then reset bit 4 at I/O location 300.
mov aX,OOlOh
mov dX,PAGE_PORT
out dX,ax
Set bit 4 at 1/0 location 300.
mav aX,OOaOh
out dX,ax
Reset bit 4 at 1/0 location 300.
;***********************
BIU initialization:
***************************
The following two lines write a value of 0110 (hex) into the internal
relocation register. This sets the 82786 registers for I/O - mapped
access at I/O locations 4400 through 447F.
The Intel Evaluation Board
decodes a CPU memory access at memory locations C4400 through C447F and
generates an I/O access to the 82786. The 82786 comes up in I/O mode
and byte mode after r~set.
Access to the registers must be one byte
at a time until WORD mode is set.
mov INTER_RELOC, 10h
; Write low byte into internal relocation register.
mov INTER_RELOC[ll,Olh
; Write high byte into internal relocation register.
The following two lines write a value of 0011 (hex) into the BIU control
register. This sets the Internal Register Block for la-bit WORD access
by the External CPU. All subsequent access to the 82786 registers i5 by
WORD access.
mov BIU_CONTROL,10h
Write low byte into BIU control register
mov BIU_CONTROL[ll,OOh
Write high byte into BIU control register
mov DRAM_REFRESH,0018h
mov DRAM_CONTROL, OOlDh
Write value into DRAM refresh control register.
; Write value into ORAM control register.
mov OP_PRIORITY, 003Fh
Write value into OP priority register.
mov GP_PRIORITY,0009h
Write value into GP Priqrity register
mov EXT_PRIORITY,0028h
Write value "into External Priority register.
;***************
mav ax,SEG_GR_MEM
mov ds.ax
Clear Page 0 of Graphics memory (64K bytes):
**************~
Graphics memory space is in the 'A' segment
mav ax,O
mov dx,PAGE_PORT
out dX,ax
mov bx,O
mov cx,32767
mov si,O
CLEAR_MEMORY:
mov [siJ,bx
add si,2
loop CLEAR_MEMORY
Select page 0 of graphics memory
32767 words of memory to be cleared =" 64K bytes
Clear page 0 of graphics memory (to be
used as a bitmap for drawing commands. )
10-202
AP-408
;****** Prepare DS, ES. and Dir Flag for use with REP MOVSB instruction.
mov ax,OFh
mov dx,PAGE_PORT
out dx, ax
mov ax,SEG
******
Select page F of graphics memory
beg_dp_ctrl_blk
mov dS,BX
Set data segment
mov ax,SEG_GR_MEM
moves. ax
and extra segment.
Clear Direction Flag, seta auto-increment
cld
of SI and DI when using REP instruction.
;*****
Copy DP CONTROL BLOCK REGISTERS from CPU memory to Graphics Memory. ****
lea cx, end_DP_ctrl_blk
sub ex, offset beg_dp_ctrl_blk
lea si" beiLdp_ctrl_blk
mov di, off set DP_REG_MAP
rep' movsb
Move CX byte. from DS:[5I] to ES:[DI]
thu., copying DP Control Block Regi.ters
from CPU memory to Graphics memory.
i*******
COpy DF Descriptor List from CPU memory to Graphics memory.
lea ex, end_dp_descl
sub ex, offset dp_descl
lea si, dp_descl
mov di, off.et DESC_PTR_LO
********
Move ex bytes from DS:[SI] to ES:[DI]
thus copying DP de.criptor li.t from CPU
rep movsb
memory to graphics memory.
;********* Copy GP command list from CPU memory to graphics memory:
lea ex, len_BP_listl
sub ex, offset gp_listl
*********
lea 5i. gp_listl
mov di, offset GP_LIST_PTR_LO
rep movsb
Move CX byte. from DS:[SI] to ES:[DI]
thuB copying GP command list from CPU
memory to graphics memory.
mav ax, register
mav as.ax
********************* Start up the Display Processor: ********************
mov DP_PARM1_REG,DP_REG_MAP_LO
parameter 1 for dp command
mov DP_PARM2_REG,DP_REG_MAP_HI
parameter 2 for dp command
mov DEF_VIDEO_REG,O
Write a in De1ault Video register
mov DP_OPCODE-REG, LOADALL
Write opcode register. thus starting up
the Display Processor
*********************
Execute the GP command list:
mov GP_PARMLREG,GP_LIST_PTR_LO
mov GP_PARM2-REG,GP_LIST_PTR_HI
mov GP_OPCODE_REG, LINK
i************************
mov ah,4Ch
int 21h
*******************
parameter 1 for GP command
parameter 2 for GP command
Write opcode register, thus starting
execution of the GP command list.
Terminate program:
*************************
Call BIOS terminate function
to return to MS-DOS operating system.
code ENDS
stack SEGMENT stack
DW 64 DUP(?)
stack ENDS
Program stack segment
Define unltlalized data space for stack.
END main
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3.4 Exercises
This section provides some exercises for the reader in the form of suggested modifications to the Example 1 program.
By working through these exercises in succession, the reader will gain an understanding of important concepts and
.valuable experience in programming the 82786.
Solutions to the Exercises are provided in the Appendix.
Exercise 1:
• Tum cursor off
• Video Status Register, Register 0 in DP Control Block, controls the cursor
Register
Offset
VSTAT
IZero unused upper bits IC ID I
00
C= 1
C= 0
Cursor On
Cursor Off
D =,1 ' Display On
D = 0 Display Off
Exercise 2: "
Replac,e GP Command List· in Example 1 with' new. GP Command List to
draw the straight lines in the graphic
Center -of Circle at (200, 182)
RadiilS .= 50
50
'011
150 200
50
100
150
200
250
300
350
50
100 150 200 250 300 350 400
(640 x 381)
450 500 550 500
240048-26
Hint: Replace GP Command List in Exercise 1 with a new Command
List. See description of Abs~ov, Line, and Circle commands.
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Exercise 3:
• Modify the program from Exercise 2.
• Change from I-bit per pixel (bpp) to 4 bpp.
• Use the Def_Color Command to change the color of each line in the
drawing.
Hint: Change Def_Bitmap parameters and Tile Descriptors. Clear an additional page (Page I) of Graphics Memory to allow room for the larger
bitmap.
Exercise 4:
• Write a new DP Descriptor List and turn on the borders for two windows,
not overlapping, as shown below.
• The left window should contain the 4 bpp multi-colored image drawn in
Exercise 3.
• The right window should contain the I bpp image drawn in Exercise I (the
Intel Logo).
• Change I bpp pad register to accentuate the two different windows.
in\!
240048-27
Hint: Change Def~itmap parameters. Modify strip and tile descriptors.
Combine the two GP command lists from Exercise 3 and Example I
programs. Before starting the second command list, be sure to use a new
Def_Bitmap command. Clear page 2 of Graphics memory.
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Exercise 5:
Same as Exercise 4, except make the two windows overlap as shown below..
•
In
240048-28
Hint: Create two strips.
Strip 1: Contains 1 tile consisting of 100 lines.
Strip 2: Contains 2 tiles consisting of 281 lines; the first tile is 320 pixels wide.
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CHAPTER 4 QUICK REFERENCE SECTION
4.0 Introduction
4.1 82786 Directly Accessible (Internal) Registers
4.2 GP Indirectly Accessible (Context Switching) Registers
4.3 GP Commands, Opcodes, Parameters
4.4 DP Indirectly Accessible Registers (DP Control Block Registers)
4.5 DP Commands, Opcodes, Parameters
4.6 Strip and Tile Descriptor Formats
4.7 Example Video Timing Parameters
4.0 INTRODUCTION
This Chapter provides a compilation of data frequently used by 82786 programmers. It contains data for all 82786
registers, commands, command parameters, opcodes, strip and tile descriptor format, video timing parameters.
10-207
inter
AP-408
4.1 82786 Directly Accessible (Internal) Registers
Regist.r
Off ••1
(HI
15
.4
'3
.2
11
10
M.D
Internal Relocation
00
Base Address
Reserved
02
Reserved (zero 'or future compatibility)
BIU Control
04
06
8
DRAMJVRAM Control
Reserved (zero lor future compatlblhty)
Refresh Control
Reserved (zero for future compatibility)
••u
'OO-OFH
A
Reserved (zero for future compatibility)
GP Priotlfy
DC
Reserved (zero 'or future compatibility)
External Priority
0E
0
1• 2
Reserved (zero tor future compahbillty)
4
Reserved (zero for future compatibility)
6
Reserved (zero lor future compatibility)
[
Instruction POinter
8
Reserved (zero for future compatibIlity)
A
Reserved (zero for future compatIbIlity)
C
Reserved (zero lor luture compatIbIlity)
'2C·3FH
Opcode
WP2
DC'
FPl
FPl
FPl
OCO
HT2
HTl
SPl
SPl
HTO
Reserved
I
Reserved (zero lor future compatIbIlIty)
GECl
Lmk Address (lower)
•
lmk Address tUpper)
GPOll GRCD
Reserved
6
8
InstructIon POInter (lower)
C
E
0
2
Reserved (zero for future compatIbIlity)
4
ReserVed (zero for future compatIbIlIty)
GINT
Reserved (zero for future compatibIlity)
GPSC GBCOV GBMOV/GCTP IG.BMC
Instruchon Pomter (Upper)
Reserved (zero for future compatIbIlity)
Reserved (zero fat luIure compatIbIlity)
Reserved (zero lor future compatIbIlity)
6
Reserved (zero for future compatibIlity)
8
Reserved (zero for future compatIbIlity)
A
Reserved (zero for future compallblllty)
Reserved (zero for luture compatIbility)
3E
Reserved (zero lor lulUre compatIbility)
40
Opcode
Reserved (zero lor luture compatlblhty)
Parameter 1 42
Memory Address (lOwer)
Parameter 2
44
Reserved (zero for futurg compatibility)
Parameter 3
46
Reserved (zero for future compatlblllly)
Status Register
48
Reserved
Delault Video
4A
Reserved
A•••nH
4C
Reserved (zero for future compatIbilIty)
'4C·7FH
4E
Reserved (zero for future compatibility)
50
52
Reserved (zero for future compatibility)
S4
Reserved (zero lor luIure compatibility)
56
58
Reserved (zero lor future compatIbility)
Reserved
AWO
Reserved
3C
DP
'41>48H
WP.
Reserved (zero lor future compallblllty)
Opcode
~ ~A
R••• rv.d
D.
G'
Reserved (zero for future compaltbihlYI
E
GP
GRO Opcode 20
'2G-2BH GA1 Parameter 1 2 2
GR2 Parameter 2
BCP
Reserved (zero lor future compatibility)
-- i
Status Register IGSTAT)
WT
Refresh Scaler
AW.
Reserved (zero lor future compalibillty)
Display Pnonty
R... rved
'1D-1FH
VA
1
ECl
Memory Address (Upper)
Register Identification
FA.
ACO
OOV
I
FMT
BlK
EVN
000
ECl
Default VIdeo
Reserved (zero for future compatIbilIty)
Reserved (zero lor luture compatibIlity)
5A
Reserved (zero for future compatibility)
5C
Reserved (zero lor luture compatibIlity)
5E
Reserved (zero for future compatibility)
60
62
64
66
68
Reserved (zero for luture compatibility)
Reserved (zero for luture compahbllity)
Reserved (zero for future compahbllltYI
Reserved (zero for future compatibility)
Reserved (zero lor luture compatibility)
6A
Reserved (zero lor luture compatibIlity)
6C
6E
Reserved (zero lor luture compatibility)
Reserved (zero lor luture C:ompahblhty)
70
Reserved (zero lot luture compahblflty)
72
Reserved (zero lor future compallbthly)
7.
Reserved (zero lor future compatibility)
76
Reserved (zero lor luture compaltblhly)
78
Reserved (zero lor luture compatibility)
7A
Reserved (zero lor future compatibility)
7C
Reserved (zero for luture compalibillty)
7E
Reserved (zero tor future compatibIlity)
'5
14
'3
12
.11
'0
240048-29
82786 128-byte Internal Register Block
10-208
infef
AP-408
4.2 GP Indirectly Accessible Registers
Context Registers
10
Name
GCOMM
GPOEM
GIMR
GCHOR
GCHA
GSP
GCA
GBORG
GCX
GCY
GPAT
GSPAC
GCNT
GN
GVERS
0001
0003
0004
0007
010B
010C
010D
010F
0010
0011
0012
0013
0014
0016
0017
Bits
(16)
(6)
(6)
(2,2)
(21)
(21)
(21)
(21)
(16)
(16)
(16)
(16)
(16)
(16)
(16)
Function
Command
Poll Mask
Interrupt Mask
Character Orientation and Path'
Character Font Base Address
Stack Pointer
Memory Address of Current Position (x, Y)
Bitmap Origin Address
Current X Position
Current Y Position
Line Pattern
Spacing between Characters and All Bitblts
Character Count' ,
Number of 16-bit Words Spanning Width of Bitmap
Version Number'" (D Step Value = 5)
GXMAX
GYMAX
GXMIN
GYMIN
GMASK
GBGC
GFGC
GFCODE
GCIP
GBPP (RO)
0090
0091
0094
0095
0099
009B
009C
009E
01AC
009F
(16)
(16)
(16)
(16)
(16)
(16)
(16)
(4)
(21)
(4)
GBPP (WO)
0008
(4)
Maximum X for Clipping Rectangle
Maximum Y for Clipping Rectangle
Minimum X for Clipping Rectangle'
Minimum Y for Clipping Rectangle'
Pixel Mask
Background Color
Foreground Color
Function Code for Pixel Updates"
Current Instruction Pointer
Used with Dump Register command to get Current
Bits per Pixel Address AM
Used with Load Register command to write Current
Bits per Pixel Address AM
These bits are right justified in each byte of the word in which they are stored. Two bits are stored in bits 1 and
..,
"
AA,
o and two bits are stored in bits 8 and 9; the remaining upper bits in each byte are zeroed.
GCNT ID reassigned from 0015 to 0014 in D-Step.
In D-Step, valid after RESET and prior to drawing or drawing control commands.
Correction to previous GXMIN ID 0096 and GYMIN 0097 assignments.
GFCODE ID reassigned from OOlC to oo9F in D-Step.
New D-Step Bpp Registersd.
NOTE:
Simply saving and restoring the context registers is not sufficient to restore the state of the graphics processor.
10-209
inter
AP-408
4.3 GP Commands, Opcodes, Parameters
CjlQMljmc CCMIANJ)S
ARC_EXCL
ARC_INCL
CIRCLE
INCR_POINT
LINE
POINT
POLYGON
POLYLINE
RECTANGLE
SCAN_LINES
OPCQDI
6800
6900
8£00
8400
PAAMIUIM
dxmin, dymin, dxmax. dymax, radiu",
dxmin, dymin. dxmax. dymax, radius
radius
5800
array addre.ss low, high
dx. dy
dx. dy
array address low, high
array address low, high
dx. dy
BACO
array address low, high, number of
5400
5300
7300
1400
line"
DAn TJW(SFIR CQMMANI)S
BIT_SLT
OPCQDZ
6400
PARAMli1ZRS
source x, source y, dx, dy
301.\%,C8 addr low, l!Iource addr hiqh,
source x-max,
source y-max, source x, source y,
dx' (rect width - 1), dy (rect height
-
OPAQUE
TRANSP
REVERSE OPAQUE
REVERSE TRANSP
AEOO
source addr low, source addr high,
source x-max,
source y-max, source x, source y,
dx (rect width - 1), dy (rect height
-
1)
string pointer low, high, number of
characters
CHAR
OPAQUE
TRANSP
REVERSE OPAQUE
REVERSE TRANSP
1)
0400
0500
0600
0700
A600
A700
A800
A900
pMWIJ!G cmmtOL oms
QpCOOI
'MAMlj1lRS
ABS_MOV
4FOO
4EOO
OAOO
x, Y
path-rotation (one word)
char font addr low, char font &ddr
high
char font addr low, char font addr
hiqh
x-min, y-min, x-max, y-max
foreqround, backqrouncl
color bit mask, function code
number of pixel" of ,space
pattern
pattern
no parameters
no parameters
dx. dy
,
DEF_CHAR_ORIENT
DEF_CHAR_SET_BYTE
0800
REL_MOV
4600
3000
4100
4000
0600
0100
4400
4500
5200
HOM-DRAWING COMMANDS
OPCOO&
'ARAMIjTlItS
CALL
OFOO
2900
0301
OEOO
0200
3400
0300
1100
call addr low,
dump addr low,
no parameters
no parameters
link addr low,
load addr low,
no pArameters
no parameters
CEF_CLIP_RECT
DEF_COLORS
DEF_LOGICAL_OP
DEF SPACE
OEr-TEXTURE OPAQUE
DEF::TEX'l'UR.E::TRANSP
ENTER_PICK
EXIT_PICK
HALT
INTR_GEN
LINK
LOAD_REG
NOP
RETURN
call addr high
clump addr high, req 10
link addr high
load addr high, req ID
240048-68
10-210
intJ
AP-408
4.4 DP Indirectly Accessible Registers (DP Control Block Registers)
Regllt.r
01t•• 1
(HIlS
14
13
Video SI.luI 00
Reserved
Interrupt Mask 0 1
Reserved
02
Reserved
03
Reserved
04
Reserved
CRTllad. 05
Reserved
12
11
10
FRI
ooV
RCD
FMT
BlK
EVN
Trip POlOt
I
I
l
I
w
I
00
Nonlnterlace
10
Inlerlace
11
Interlace-Sync
lowL
HSync/VSync
Slave Mode II)
Reserved
7
Reserved
Horllontal Field SlarllHFldStrt)
8
Reserved
HOrizontal Field Stop (HFldStp)
A
Accelerated V,deo (2)
00
06
l
A
B
S
Wmdow Slatus Enable (I)
Normal (25 MHz,
01
High-Speed (50 MHZ)
10
Very Hlgh·Speed (100 MHz)
11
Super High-Speed (200 MHz)
Honzontal SynchrOnization SlOp (HSyncSlp)
09
ReseJv~d
Lme Length (lmelenl
OA
Reserved
Vertical Synchronization Stop (VSyncStp)
Vertical Field SlarllVFldSlrl)
B
Reserved
OC
Reserved
Vertical Field Stop IVFldStpl
0
Reserved
Frame Length (Framelenl
Descriptor Address Pointer (Lowerl
E
Reserved
Descripior Address POinter (Upper)
. Reserved
10
1
0
ECl
Frame Interrupt
I
Interlace ·(21Il~
01
Reserved
F
C
000
Reserved
XZoom
Reserved
YZoom
12
Reserved
Field Color (FldCOlorl
13
Reserved
Border ColOr (BdrColor)
14
Reserved
1 8pp Pad
15
Reserved
2 8pp Pad
16
Reserved
C.rMode 17
4 8pp Pad
X
S
I
T
CSI
CSC
Res.
CsrPad
I
IRe •.
I Reserved
Reserved
IRe•.
1
... Cursor Size (11
CsrSlze 0 = 8x8 Csr
1 "" 16x16 Csr
X
"'" Crosshair Cursor (11
T
""' Transparent Cursor (I)
CSt ~ Cursor Status to Wmdow Status Output (2)
CSC
Cursor Status Control (2)
00 - Current Window Status
01 ~ Foreground
10 ,.., Background
11 '" Block
CsrStyle: S
18
Reserved
19
Reserved
I
I
Cursor Position X (CsrPosXI
Cursor Position Y (CsrPosY)
lA
Cursor Pattern a (CsrPalOI
lB
lC
Cursor Pattern 1 (CsrPal1l
Cursor Pattern 2 (CsrPat2)
10
Cursor Pattern 3 (CsrPat31
IE
Cursor Pattern 4 (CsrPal")
IF
Cursor Pattern 5 (CsrPatS)
20
Cursor Pattern 6 (CsrPat6)
21
Cursor Pattern 7 (CsrPaI7)
22
Cursor Pattern 8 (CsrPatS)
23
Cursor Pattern 9 (CSrPaI91
24
Cursor Pattern A (CsrPalA)
25
Cursor Panern B (CsrPaIB)
26
Cursor Pattern C (CsrPatel
27
Cursor Pattern 0 (CsrPatDI
28
Cursor Panern E (CSrPaIEI
29
Cursor Pattern F (CsrPaiFI
15
14
13.
12
11
. 5
10
240048-30
10-211
inter
AP-408
4.5 DP Commands, Opcodes, Parameters
. pp CO"?"P'
LOAD_REG
LOAD.;,.ALL
DtJIG_REG
DUMP_ALL
gpc;gpa
'Y'MI'l'IBI
0400
0500
0600
0700
load _cicir low, load ad.clr high
clump aclciJ: 1011, load addr hlqh, :reg It)
~ add.:r low, l~ad ac1d.r hiqh
load adclr low. 10al1 aclclr high, reg ID
240048-69
4.6 Strip and Tile Descriptor Formats
Strip and Tile Descriptors
15
14
13
12
11
10
9
8
7
8
5
4
3
2
HEADER
J
J
NUMBER OF UNES IN STRIp· 1
LINK TO !EXT STRIP DESCRIPTOR (LOWER)
15
FIRST
TILE DESCRIPTOR
II
LINK TO NEXT STRIP
DESCRIPTOR (UPPER)
III
RESERVED
~II
JIl
RESERVED
14
13 12
11
10
9
0
NUllSEA OF TILES
INSTRIP·'
8
7
6
5
4
3
2
0
J
BITMAP WIDTH
MEMORY START ADORESS (LOWER)
II T
15
SECOND
TILE DESCRIPTOR
Il
II
RESERVED
BPP
RESERVED
FETCH COUNT
B
L
14
13
R
11
10
8
7
6
STOPBIT .
J~010
RESERVED
9
UI
STARTBIT
5
4
3·
2
MEMORY START ADDRESS (LOWER)
JII
RESERVED
II
RESERVED
II
RESERVED
T
B
L
II
'I
R
JII STARTBIT
BPP
Jil
RESERVED
••
•
10-212
MEMORY START
ADDRESS (UPPER)
Jil
STOPBIT
I
J
J
FETCH COUNT
WST
0
J
J
BITMAP WIDTH
Il
II
1lI
1811
12
MEMORY START
ADDRESS (UPPER)
Jil
RESERVED
JIGJl010
240048-20
infef
AP-408
Field Tile Descriptor Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bianap Widlh
Memory Stan Address (l.o~)
I Mem Stan Addr (Upper)
Reserved
I
Bpp
I StanBit
I StopBit
Reserved
I
Fetch Cou .t· 2 (tile widlh ill bytes)
Reserved
T B L R I WSt~
15 14 13 12 11 10 9 8 7 6 5
4
I PC I zl F
3 2 1 0
Normal
Tlle Descriptor
r+
=0
Reserved
Reserved
Field
Tue Deesriptor
Reserved
Fieid Pixel Count - 1 (tile widlh in pixels)
Reserved
Reserved
Reserved
I
Reserved
Reserved
IRcserv~ Z I F
WSt
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I
n
=1
240048-22
4.7 Example Video Timing Parameters
The following table of Video Timing Parameters satisfy the requirements of NEC Multisync-compatible monitors.
These parameters provide the given resolution and refresh rate when using the VCLK frequency indicated in the
table.
VCLK (MHz)
Xmax
Ymax
Screen Refresh (Hz)
25
640
480
60
25
512
512
60
20
512
512
60
20
640
350
60
20
640
455
60
HSync Stop
HFld Start
HFld Stop
Line Len
VSync Stop
VFld Start
VFld Stop
Frame Len
75
145
785
827
3
14
494
501
97
184
696
752
6
26
538
551
47
94
606
633
2
8
520
524
89
168
808
861
5
23
373
385
37
10-213
77
717
737
0
3
458
458
AP-408
APPENDIX A
SOLUTIONS TO EXERCISES
SOLUTION FOR EXERCISE 1
; ******************************************************************************
Program name: EXERl. ASH
.
; Description:
Same
88
EXAMPLE! program
J
except cursor
i3
turned off.
; ******************************************************************************
j************* Values for·the Display Processor Control Block:
beS_dp_ctrl_blk LABEL word
; REGISTER NAME
d" 1
"---------------
; Video Status
*************
------------------------------------SETTING
: cursor OFF. and display ON
240046-59
10-214
intJ
Ap·408
SOLUTION FOR EXERCISE 2
;******************************************************************************
Program name:
EXER2. ASM
Description:
Modify the program from EXER1.
Write a new GP command list to draw an interesting image as
shown in accompanying documentation.
The drawing contains
12 lines and one circle.
;
;******************************************************************************
;**********
Definition of Graphics Processor Command List:
************
gp_list1 LABEL word
dw DEF_BITMAP. BITMAP_O_LO. BITMAP_O_HI. 639 • 380 • 1
address 10 , address hi I xmax, ymax, bits per pixel
dw DEF_TEXTURE_OP. OFFFFh
dw DEF_COLORS. OFFFFh. OOOOOh
dw DEF_LOGICAL_OP. OFFFFh. 00005h
X equ 10
y equ 10
501id texture
replace destination with source
X-coordinate of starting location for drawing
Y-coordinate of starting location for drawing
dw ABS_MOV. 600.380
dw LINE. -600. -30
dw ABS_MOV. 550.380
dw LINE. -550. -80
dw ABS_MOV. 500. 380
dw LINE.
-500. -130
dw ABS_MOV. 450.360
dw LINE.
-450. -180
dw ABS~MOV. 400.380
dw LINE.
-400.-230
dw ASS_MOV. 350.380
dw LINE.
-350. -280
dw ASS_MOV. 300.380
dw LINE.
-300. -330
dw ASS_MOV. 250. 380
dw LINE.
-250. -380
dw ASS_MOV. 200. 380
dw LINE.
-150. -380
dw ASS_MOV, 150.380
dw LINE, -50, -380
dw ABS_MOV, 100.380
dw LINE, 50, -380
dw ASS_MOV. 50,360
dw LINE, 150. -380
dw ABS_MOV. 0.380
dw LINE. 250. -380
dw ABS_MOV,200.182
dw CIRCLE, 50
dw HALT
len_gp_listl LABEL word
240048-60
10-215
intJ
AP-408
SOLUTION FOR EXERCISE 3
-******************************************************************************
, Program name:
Description:
j
EXER3 . ASH
.
Modify the program from Exercise 2.
Change the hi tmap
from 1 bit 'per pixel to 4 bits per pixel.
Use the DEF COLORS command to chanse the color of each line
in the drawIng.
;*************************************************************~*****~**********
j ************
Defini tion of n"isplay Processor Descriptor List:
************
dp_descl LABEL word
Header of DP descriptor:
dw 380
(number of lines - 1)
dw DESC PTR LO+20
lower link to next strip descriptor (there is none,
but i f one were added, this is the link)
dw DESC_PTR_HI
upper link to next strip descriptor (there is none)
dw 0
(number of tiles - 1)
First (and only) Tile Descriptor
dw 0320
Bi tmap width (number of bytes)
dw OOOOh
Bi tmap start address lower
dw OOOOh
Bitmap start address upper
dw 04FOh
4 bpp, start bit F, stop bit 0
Fetch count = (number of bytes - 2)
dw 0318
dw OFOOOh
All 4 borders on,window status=O,PC mode off,field off
end_dp_desc1 LABEL word ;
End of DP descriptor list.
***********
;**********
*********
Definition of Graphics Processor Command List:
240048-61
************
gp_listl LABEL word
dw DEF_BITMAP, BITMAP_O_LO, BITMAP_O_RI, 639 , 380 , 4
;
address 10 I address hi , xmax, ymax, hits per pixel
dw DEF_TEXTURE_OP, OFFFFh
solid texture
dw DEF_COLORS, OFFFFh, 0
dw DEF_LOGICAL_OP, OFFFFh, 00005h
replace destination with source
X equ 10
Y equ 10
dw
dw
dw
dw
X-coordinate of starting location for drawing
Y-coordinate of starting location for drawing
ABS_MOV, 600,380
LINE, -600, -30
ABS_MOV, 550,380
DEF_COLORS, 1110111011101110b,
dw LINE, -550, -80
dw ABS_MOV, 500, 380
dw DEF_COLORS, 1101110111010010b,
dw LINE,
-500, -130
dw ABS_MOV, 450,380
dw DEF_COLORS, 1100110011001100b,
dw LINE,
-450, -180
dw ABS_MOV, 400,380
dw DEF_COLORS, 1011101110111011b,
dw LINE,
-400,-230
dw ABS_MOV, 350,380
dw DEF_COLORS, 1010101010101010b,
dw LINE,
-350,-280
dw ABS_HOV, 300,380
dw DEF_COLORS, 1001100110011001b,
dw LINE,
-300, -330
dw ABS_MOV, 250,380
dw DEF_COLORS, 1000100010001000b,
dw LINE,
-250, -380
dw ABS_MOV, 200,380
dw DEF_COLORS, 0111011101110111b,
dw LINE,
-150, -380
dw ABS_HOV, 150,380
dw DEF_COLORS, 0110011001100110b,
dw LINE, -50, -380
dw ABS_MOV, 100,380
dw DEF_COLORS, 0101010101010101b,
dw LINE, 50, -380
dw ABS_MOV, 50,380
dw DEF_COLORS, 01'000100010001 OOb,
dw LINE, 150,-380
dw ABS_MOV, 0,380
dw DEF_COLORS, 0011001100110011b,
dw LINE,
250, -380
dw ABS_MOV,200,182
dw DEF_COLORS, 0010001000100010b,
dw CIRCLE, 50
dw RALT
len_sp_list1 LABEL word
foreground color is 1110 (binary); must
be repeated to fill the entire word.
foreground color is 1101 (binary) .
foreground color is 1100 (binary) .
0
foreground color is 1011 (binary) .
0
foreground color is 1010 (binary) .
0
foreground color is 1001 (binary) .
0
foreground color is 1000 (binary) .
0
foreground color is 0111 (binary) .
0
foreground color is 0110 (binary) .
0
foreground color is 0101 (binary) .
0
foreground color is 0100 (binary) .
0
foreground color is 0011 (binary) .
0
foreground color is 0010 (binary) .
240048-62
10-216
inter
AP-408
;***************
mav ax,SEG_GR_MEM
Clear Page 0 of Graphics memory (64K bytes):
mav ax.O
mov dx,PAGE_PORT
out dx.ax
Select page 0 of graphics memory
mav bx,O
mav cx.32767
mav si,O
32767 words of memory to be cleared
CLEAR_MEMORY:
mov [5i],bx
add 5i,2
loop CLEAR_MEMORY
;***************
mavax.l
mov dx,PAGE_PORT
out dx.ax
mav bx,O
mov eX,32767
mav si,O
CLEAR_PAGE 1 :
mov [si],bx
**************)
Graphics memory space is in the 'A' segment
mov ds,ax
Clear Page
add 5i, 2
loop CLEAR_PAGEl
= 64K
bytes
Clear page 0 of graphics memory (to be
used as a bitmap for drawing commands. )
of Graphics memory (64K bytes):
**************)
Select page 1 of graphics memory
32767 words of memory to be cleared
=
64K bytes
Clear page 1 of graphics memory (to be
used as a bitmap)
240048-63
10-217
infef
AP-408
SOLUTION FOR EXERCISE 4
;******************************************************************************
Program -name:
EXER4 . ASH
Description:
Modify the program from Exercise 3.
Modify the DP·descriptor
list for 2 windows, not overlapping, as shown in the
accompanying documentation.
The left window should contain
the 4 BFP multi-colored image drawn in EXERCISE 3.
The right window should contain the 1 BPP image drawn in the
EXAMPLE1 program (the Intel logo).
;
;******************************************************************************
;************
Definition of Display Processor Descriptor List:
dp_descl LABEL word
Header of DP descriptor:
dw 380
dw DESC_PTR_LO+20
(number of
lower link
but if
upper link
(number of
************
lines - 1)
to next strip descriptor (there is none,
one were added, this is the link)
to next strip descriptor (there is none)
tiles - 1)
dw DESC_PTR_HI
dw 1
·First Tile Descriptor:
dw 0320
Bi tmap width (number of bytes)
dw 7720h
Bi tmap. start address lower
dw OOOOh
Bi tmap start address upper
dw 04FOh
4 bpp, start bit F, stop bit 0
dw 0158
Fetch count = (number of bytes - 2)
dw OFOOOh
borders on,window status=O,PC mode off,field off
Second Tile Descriptor:
.
dw 0080
Bitmap width (number of bytes)
dw OOOOh
Bi tmap start address lower
dw OOOOh
Bi tmap start address upper
dw 01FOh
1 bpp, start bit F, stop bit
d .. 0038
Fetch count
(number of bytes - 2)
dw OFOOOh
j A!!*!*~~!~;;S ~~d W~~d~; ~::~~~;~~~c l~~~~ ~!;*!~:;~ off
end_dp_desc1 LABEL
; All 4
=
word
10-218
240048-64
AP-408
:**********
Definition of Graphics Processor Command List:
gp_Iistl LABEL word
************
dw DEF_BITMAP. BITMAP_O_LO. BITMAP_O_HI. 639 • 380 . 1
address 10 , address hi
dw DEF_TEXTURE_OP. OFFFFh
dw DEF_COLORS. OFFFFh. OOOOOh
dw DEF_LOGICAL_OP. OFFFFh. 00005h
X equ 10
;*************************
dw
ABS_MOV. X. Y
LINE.
LINE.
xmax, ymax, bits per pixel
solid texture
replace destination with source
; X-coordinate of starting location for drawing
; Y-coordinate of starting location for drawing
Y equ 10
dw
dw
I
35.
O.
0
35
;*****************
Draw Intel logo:
************************
; Move to beginning posi tien for drawing.
; Dot the "i"
Draw figure from EXER3 program:
dw DEF_BITMAP. 1120h. O. 639 • 380 • 4
***********************
address 10 , address hi , xmax, ymax, hits per pixel
dw
dw
dw
dw
ABS_MOV. 600.380
LINE. -600. -30
ABS_MOV. 550.380
DEF_COLORS. 1110111011101110b.
dw
LINE. -550. -80
foreground color is 1110 (binary); must
be repeated to fill the entire word.
240048-65
10-219
inter
AP-408
;***************
mov ax. SEG_GR_MEM
mev ds,ax
Clear Page 0 of Graphics memory (64K bytes):
**************>
Graphics memory space is in the • A' segment
mevax,O
mov dX,PAGE_PORT
Select page 0 of gr~phic5 memory
out dx. ax
mev bx,O
mav ex, 32767
32767 words of memory to be cleared = 64K bytes
mev si,O
CLEAR_MEMORY:
mov [si],bx
add 51,2
loop CLEAR_MEMORY
;***************
movax,l
Clear Page
Clear page 0 of graphics memory (to be
used as a hi tmap for drawing commands.)
of Graphics memory (64K bytes):
**************'
mov dX,PAGE_PORT
out dx, ax
Select page 1 of graphics memory
mav bx,Q
mav cx,32767
mav si,O
32767 words of rhemory to be cleared = 64K bytes
CLEAR_PAGEl:
Clear page 1 of graphics memory (to be
mav [si].bx
add 5i,2
loop CLEAR_PAGEl
;***************
movax.2
1,lsed as a hi tmap)
Clear Page 2 of Graphics memory (64K bytes):
mov dX,PAGE_PORT
out dx, ax
mov bx,O
mov cx,32767
mov si,O
CLEAR PAGE2:
mov [si], bx
add 51, 2
loopCLEAR_PAGE2
**************)
Select page 1 of graphics memory
32767 words of memory to be cleared ::: 64K bytes
Clear page 1 of graphics memory, (to be
used as a bitmap)
240046-66
10-220
AP-408
SOLUTION FOR EXERCISE 5
;; ******************************************************************************
Program name:
EXER5. ASH
; Description:
Same as EXERCISE 4 but the 2 windows are overlapping.
;******************************************************************************
;************
Definition of Display Processor Descriptor List:
dp_desc1 LABEL word
************
Header of First Strip descriptor:
dw 99
; (number of lines - 1)
dw DESC PTR LO+20 ; lower link to next strip descriptor
dw DESC:::PTR:::HI
upper link to next strip descriptor (there is none)
dw 0
(number of tiles - 1)
First Tile Descriptor of first strip:
dw
dw
dw
dw
dw
dw
0080
OOOOh
OOOOh
01FOh
0078
OBOOOh
Bi tmap width (number of bytes)
Bitmap start address lower
Bitmap start address upper
1 bpp, start bit F, stop bit 0
Fetch count = (number of bytes - 2)
Bottom border off, window stat=O, PC mode off, field off
Header of Second Strip descriptor:
dw 280
(number of lines - 1)
dw DESC_PTR_LO+52
dw DESC_PTR_HI
dw 1
lower link
but if
Upper link
(number of
to next strip descriptor (there is none,
one were added, this is the link)
to next strip descriptor (there is none)
tiles - 1)
First Tile Descriptor of Second Strip:
dw 0080
Bitmap width (number of bytes)
dw 8000
Bi tmap start address lower
dw 0000
Bi tmap start address upper
dw 01FOh
1 bpp, start bit F, stop bit
dw 0040
Fetch count = (number of bytes - 2)
dw 07000h
Top border off, window stat=O,PC mode off,field off
Second Tile Descriptor of Second Strip:
dw 0320
Bitmap width (number of bytes)
dw 7720h
Bitmap start address lower
dw OOOOh
Bitmap start address upper
dw 04FOh
4 bpp •• tart bit F. stop bit 0
dw 0150
Fetch count = (number of bytes - 2)
dw OFOOOh
All 4 borders on. window status=O, PC mode off. field off
end_dp_descl LABEL word i *********** End of DP descriptor list.
*********
10-221
240048-67
APPLICATION
NOTE
AP-409
October 1987
82786 Design Example
Interfacing to the IBM PCIAT*
Computer.
RICHARD SHANKMAN
APPLICATIONS ENGINEER
'IBM PCI AT is a trademark of International Business Machines Corporation.
Order Number: 240049-001
10-222
infef
AP-409
1.0 INTRODUCTION
2.2 Address Map
Many applications require greater graphics capability
than is available through IBM's CGA or EGA. The
82786 allows the design of very high performance
graphics systems at low cost, both in terms of component count and development time.
When placed in Protected Mode, a full 24 bits
(16 Mbytes) of addressing are available. However, most
applications use Real Mode, providing 20 bits of addressing. This provides a usable address space of 1
Mbyte. Our design example will use Real Mode.
This application note will present a basic design interfacing a graphics board based on the 82786 to the IBM
PC/AT computer. Only those portions of the design
related to the interface itself will be covered in detail.
Other aspects of graphics system design using the
82786, such as graphics memory design and video interfacing are covered in detail in the Hardware Configuration Application Note (AP-270-refer to section 1.1 below on related literature).
As shown in Figure I, the lower 512 kb of the 1 Mb
address space is reserved for system memory. 384
kbytes of the upper 512 kb are available for our use,
although various adaptor cards which use some of this
space may be installed in the system. We need to use
care in selecting where our graphics card resides in the
PC memory space in order to remain compatible with
most system configurations.
Throughout this application note the following naming
convention applies:
The term "PC" will be used throughout this document
to refer to both IBM's 8-bit PC and their 16-bit AT
computer systems.
1.1 Related Literature
Additional material concerning the 82786 can be found
in the following Intel publications:
82786 Graphics Coprocessor User's Manual, Order
Number 231933
82786 CHMOS Graphics Coprocessor Data Sheet, Order Number 231676
82786 Hardware Configuration Application Note, Order Number 292007
An Introduction To Programming the 82786 Graphics
Coprocessor, Order Number 240048
2.0 I/O CHANNEL
2.1 Overview
There are eight connector slots on the mother board of
the PC into which peripheral cards may be inserted. All
interface to the PC is through these connectors, which
are known as the I/O CHANNEL.
The I/O CHANNEL supports 24-bit memory addresses, data accesses of either 8- of 16-bits, interrupts,
DMA channels, and wait state generation. The connectors consist of eight 62-pin and six 36-pin connector
sockets. The two positions that have only the 62-pin
connectors can only support an 8-bit IBM PC interface.
The 128 kb section of memory located at address
80000H-9FFFH is normally reserved for expansion
memory, so using this space for our design would preclude adding memory to the system. The 128 kb address range of COOOOH through DFFFFH is also available. This section of the memory space is reserved for
ROM on I/O adapters, such as our card. Since many
commercially available peripheral cards use portions of
this address space, we would like to avoid using a large
portion of this area in order to remain compatible with
them. We will map the 82786 Internal Registers into
address C4400H-C447FH.
There is one other section of memory available to us
without going into Protected Mode. This is the address
range AOOOOH-BFFFFH, which is reserved for the
graphics display adapters. The AOOO segment is used by
the EGA, whereas the BOOO segment is used by the
CGA (and MDA). Since we are designing a graphics
card, we will use a portion of this memory space. It is
desirable to use as large a portion of the PC's memory
space as possible in order to reduce the amount of paging required to access graphics memory. Let us choose
the 64 kbyte AOOO segment. This means that our design
will work along with a CGA card in the system, but not
with an EGA. This is a reasonable choice since, if people require a higher performance graphics system, the
82786 based design will provide much more power than
the EGA. The CGA can still be used for most text and
low resolution graphics applications.
The 80286 microprocessor can address a full 64 kbyte
I/O space. However, the PC only supports I/O addressing from 000-3FFH, as shown in Figure 2. I/O
addresses OOO-OFFH are reserved for the system board
I/O, leaving addresses 100H-3FFH available on the
I/O CHANNEL. A look at the I/O address map will
show that most of this space is reserved for various
peripheral devices that might be installed in the system.
Once again, if I/O addressing is required, we must be
careful in choosing which portion of I/O space we use
in order to remain compatible with these peripherals.
10-223
AP-409
Address
Name
Function
000000 to
07FFFF
512 kb System
Board
System Board Memory
080000 to
09FFFF
128 kb
I/O Channel Memory-IBM Personal
Computer AT 128 kb Memory
Expansion Option
OAOOOOto
OBFFFF
128 kb Video
RAM
Reserved for Graphics Display Buffer
OCOOOO to
ODFFFF
128 kb I/O
Expansion ROM
Reserved for ROM on I/O Adapters
OEOOOO to
OEFFFF
64 kb Reserved
on System Board
Duplicated Code Assignment at
Address FEOOOO
OFOOOO to
OFFFFF
64 kb ROM on
the System Board
Duplicated Code Assignment at
Address FFOOOO
100000 to
FDFFFF
Maximum
Memory 15 Mb
I/O Channel Memory-IBM Personal
Computer AT 512 kb Memory
Expansion Option
FEOOOO to
FEFFFF
64 kb Reserved
on System Board
Duplicated Code Assignment at
Address OEOOOO
FFOOOOto
FFFFFF
64 kb ROM on
the System Board
Duplicated Code Assignment at
Address OFOOOO
Figure 1. IBM AT System Memory Address Map
Hex Range
Device
000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
OAO-OBF
OCO-ODF
.oFO
OF1
OF8-0FF
1FO-1F8
200-207
278-27F
2F8-2FF
300-31F
360-36F
378-37F
380-38F
3AO-3AF
3BO-3BF
3CO-3CF
3DO-3DF
3FO-3F7
3F8-3FF
DMA Controller 1, 8237 A-5
Interrupt Controller 1, 8258A, Master
Timer, 8254.2
8042 (Keyboard)
Real-Time Clock, NMI (Non-Maskable Interrupt) Mask
DMA Page Register, 74LS612
Interrupt Controller 2, 8259A
DMA Controller 2, 8237 A-5
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor
Fixed Disk
Game I/O
Parallel Printer Port 2
Serial Port 2
Prototype Card
Reserved
Parallel Printer Port 1
SDLC, Bisynchronous 2
Bisynchronous 1
Monochrome Display and Printer Adapter
Reserved
Color/Graphics Monitor Adapter
Diskette Controller
Serial Port 1
Figure 2. IBM AT System I/O Address Map
10-224
infef
AP-409
I/O address range 300H-31FH is reserved for prototype cards, so we will use a portion of this space in our
design, as will be discussed later. Another possibility
would be to use the game controller address range
200H-207H, if it is known that the game controller
will not be used.
"I/O CH RDY", I/O CHANNEL ready, is pulled low
by a peripheral device in order to insert wait states.
This signal must be driven low very quickly upon detecting a valid address and a Read or Write command.
This timing will be discussed in more detail in a subsequent section. As mentioned earlier, this signal should
be held low for no more than 2.5 microseconds.
2.3 Signal Description
MEM CS16 is pulled low to signal the system board
that the current data transfer is a I wait state, 16-bit
memory cycle. If this signal is not brought low in time
to be recognized by the system, the memory access will
automatically be broken into two 8-bit accesses, even if
a 16-bit access was desired. In addition, this signal is an
input to the CMDLY pin of the 82288 bus controller
chip on the system board. It can delay the issuance of
the MEMR, MEMW, lOR, and lOW signals in order
to allow more address setup time. As will be discussed
later, this signal should be derived from the decode of
LAI7 through LA23.
Interfacing to the PC is quite simple since all address,
data, and control signals are decoded and demultiplexed for us. In addition, wait states can be inserted, in
which case these signals are held valid as long as we
wish. Wait states must last no longer than 2.5 microseconds (2.1 microseconds for the 8-bit PC), in order to
meet IBM specifications.
The signals used in this basic interface are listed in Table 1. Other signals, incorporating other features, could
be used, such as interrupt and DMA control lines. We
will discuss only the signals used in this design.
The final signal we have used in this design is RESET
DRV. This is the active high power on reset signal.
Address Latch Enable, BALE, is used on the system
board to latch valid addresses. Address lines
SAO-SAI9 are used to address the memory and I/O
devices in the system. They are gated onto the system
bus when BALE is high and are latched on the falling
edge of BALE.
There is another set of address lines, LA 17-LA23,
which gives the system up to 16 Mb of addressability.
These signals are unlatched and remain valid only as
long as BALE is high. They become valid earlier than
the SA lines and are intended to generate decodes for
memory or I/O cycles. They should be latched by I/O
adapters on the falling edge of BALE when needed.
There are 16 data lines, SDO-SDI5, which are demultiplexed (the 80286 in IBM AT computer has separate
address and data lines) and held valid as long as the
system is held in a wait state. 8-bit interfaces will only
use SDO-SD7. Data transfers on the upper byte of the
data bus are indicated by a low signal on the SBHE pin.
The control signals have been decoded and, like the
data lines, are held valid as long as the PC is held in a
wait state. lOR and lOW are active low signals that
indicate an I/O read and write, respectively. Similarly,
MEMR and MEMW indicate a memory read or write
bus cycle.
10-225
Table 1. I/O CHANNEL Signal Description
SAO-SA19
Latched Address Lines
LA17-LA23
Unlatched Address Lines Used to
Generate Decodes for 1 WaitState Memory Cycles
RESETDRV
Power On Reset Signal from the
SDO-SD15
Latched Data Lines
IIOCH ROY
Ready Signal to Generate PCI AT
Wait-States
lOR
Indicates an liD Read
lOW
Indicates an liD Write
MEMR
Indicates a Memory Read
PCIAT
MEMW
Indicates a Memory Write
MEMCS16
Signals the AT to Perform a 1
Wait-State 16-Bit Memory Cycle
SBHE
Indicates Data Transfer on Upper
Byte of Data Bus
intJ
AP-409
3.0 82786 BUS INTERFACE
3.1 Overview
The Bus Interface Unit (BIU) controls all communication between the 82786, the external bus master and
memory. The 82786 is capable of being a bus ~aster
(Master Mode) or a bus slave (Slave Mode). The 82786
operates as a master whenever it accesses external system memory and the bus timings are similar to 80286
style bus timings. It acts as a slave when the host CPU
accesses graphics memory or the 82786 registers.
In Master Mode, the 82786 drives the Hold Request
(HREQ) pin high to indicate it is requesting the bus.
The 82786 drives the external bus only after it receives
a Hold Acknowledge (HLDA) from the external bus
master and drives HREQ low when it no longer needs
the bus or when it detects an inactive HLDA. The
82786 indicates it has the bus through a high level on
the Master Enable (MEN) pin.
The state of the BHE pin at the trailing edge of RESET
determines whether the interface is synchronous or
aysnchronous. A high BHE sets the 82786 in synchronous operation. In Master Mode, synchronous/asynchronous operation affects the sampling of the HLDA
signal only. In Slave Mode, synchronous/asynchronous
operation affects the sampling of the RD and WR signals, as will be seen, and allows for direct connection to
an 80286 (80186 and 80386 can also be supported).
Every design must support Slave Mode. The great majority of applications do not require Master Mode and
it need not be supported. Our design uses an asynchronous slave interface, which we will focus on in more
detail.
3.2 Aysnchronous Slave Interface
The following pins make up the 82786 Slave Interface:
I. 22 address inputs, A21 :0.
2. BHE input used to indicate valid data on the upper
data bus, D8-DI5, of the 82786 graphics memory.
3. Bus command input signals RD, WR, and M/IO.
4. Chip select input, CS.
5. Slave Enable output, SEN, is used to signal the system that the requested slave access is currently being
serviced. This signal is used to enable the connection
of the 82786 data bus to the external data bus and
also as a source of READY to the external master.
All of the input signals, with the exception of CS, are
bidirectional pins driven by the 827.86 when it is executing Master Mode cycles. Whenever the 82786 is in
Slave Mode, these signals are monitored by the Slave
Interface logic. The correct combination of bus commands on these pins generate a slave cycle request.
Figure 4 shows the timing relations for the Asynchronous Slave interface. When either RD or WR are detected low, CS is sampled. If CS is found to be low, the
82786 will generate a slave cycle request. Note that the
address pins, along with BHE and M/IO have the same
setup and hold timing as CS. Once the setup and hold
times have been met, the valid addresses may be removed since they will have been latched internally by
the 82786.
A slave cycle request is arbitrated between DRAM refresh, Display Processor requests, and Graphics Processor requests for bus bandwidth and is serviced according to the programmed priority of each type of
request. Notice the break in Figure 4 between the control signals going active and SEN going high, indicating
the indeterminate amount of time before the 82786 begins to execute the slave cycle. Even if external slave
accesses are programmed to be higher priority than
graphics or display processor requests for the bus,
DRAM refresh cycles always have highest priority and
can occur at any time. This can hold off execution of
the slave cycle for a few clocks. Therefore, once the PC
makes a slave request to the 82786, it will have to be
held in a wait state (by pulling IOCHRDY low) until
SEN goes high and the slave cycle begins.
Figure 5 shows the timing relations for the slave cycle
during the SEN active high time. SEN remains high for
the entire cycle, which lasts four clocks. for a write and
five clocks for a read.
10-226
inter
AP-409
RESET
VCLK
-.
-.-.-.
-.
-.
-.-.
AO-21.=
DO-1S.=
BHE
__
Figure 5. 82786 SEN/DATA Slave Interface
10-227
240049-3
intJ
AP-409
SA7-19
IBM PC/AT"
82786
240049-4
Figure 6. Generating 82786 Control Signals
AO-15
r='_______
XCVR
J\.I82786
AO-15
1-_ _ _...,....._ _ _ _-./1
IBM PC/AT"
00-15
240049-5
Figure 7. Block Diagram of Data/Address Bus
S O O - 7 1 - - - - - : . - - - - - r : : : : : - " - - - - - - - - 00-7
IBM PC/AT"
1-------....,.-
S08-15 I -_ _ _ _~--_I
8 BIT INTERFACE
WRITE TO
HIGH BYTE
16 BIT INTERFACE
WRITE TO
HIGH BYTE
Figure 8. 8/16-Bit Crosser for Write Data
10-228
08-15
8/16 BIT INTERFACE
WRITE TO
LOW BYTE
240049-6
Ap·409
4.0 INTERFACING THE 82786 TO
THE 1/0 CHANNEL
4.1 General Considerations
Our graphics board will decode the address, MEMR,
MEMW, lOR, and lOW signals from the PC and, if a
slave cycle r~es~detected, generate the proper con·
trol signals (RD, WR, M/IO, BHE and CS) along with
gating the address and data to the 82786. Refer to Fig·
ure 6 for a block diagram of generating the 82786 con·
trol signals. The IOCHRDY signal will immediately be
pulled low in order to place the PC into a wait state. If
our design is to a 16·bit interface, we must also pull the
MEMCSl6 signal low. This signal is not used for an 8·
bit interface.
Once 10CHRDY has been pulled low, the PC will be
held in a wait state. This will cause the demultiplexed
address, data, and control signals to be held valid for
us. This means that we do not have to latch these sig·
nals on our board. Figure 7 shows a block diagram of
the address and data bus interface for our design. Once
our board is selected, control logic can tum on the ad·
dress and data transceivers/latches.
4.2 Loading
IBM specifies no more than two TTL loads per pin per
slot for the I/O CHANNEL. This is to assure that the
PC system board can properly drive all peripheral cards
that may be plugged into the I/O CHANNEL. In or·
der to meet this spec, it is necessary to buffer any sig.
nals that drive more than two loads in our design.
4.3 Write Data
Figure 7 shows a data path consisting of two levels of
transceivers for the write path. Working our way from
the I/O CHANNEL side, the first bank of transceivers
encountered buffer and gate the data bus onto our
board. The second bank of transceivers isolate the
82786 from the board's data bus.
Upon receiving a decode, the first transceivers will tum
on, gating data onto the board. The second transceivers
only tum on when SEN goes high, indicating the start
of the slave cycle. In this way, the PC's data can gate
onto the board without interfering with any other
82786 memory cycles in progress to the graphics mem·
ory. This allows the PC to access the Page Select regis·
ter (which will be discussed later) without disturbing
82786 memory cycles. In addition, if we were to insert a
dedicated on·board CPU, it would interface between
these two sets of transceivers, allowing the PC to talk to
the local CPU without disturbing 82786 memory activi·
ty.
A crosser network for write data is shown in Figure 8.
All three transceivers are needed only if the design will
interface to both an 8·bit and a 16·bit system, as in our
example. If the design is only to the 8·bit PC or to the
IBM AT computer, then only two transceivers are re·
quired.
4.4 Read Data
Read data from the 82786 or graphics memory must be
latched. This is shown in Figure 5, where it can be seen
that read data will only be valid for 3 -4 clocks. De·
pending upon when 10CHRDY is released, read data
may come and go before the PC can come out of its
wait state (refer to Section 4.5), so it must be latched
and held.
The read data latches shown in Figure 9 are configured
similarly to the write data transceivers of Figure 8.
Once again, all three latches are needed only if the de·
sign will interface to both a PC and an IBM AT com·
puter, as in our example.
The data latch control can be implemented by counting
82786 clocks from the rising edge of SEN until read
data is valid, as shown in Figure 5, and then latching
the data. This data can be held and made available for
when the I/O CHANNEL exits its wait state.
10·229
intJ
AP-409
SOO-7
1--------- 00-7
IBM PC/AT'
'--------'-,08-15
S08-15
8 BIT INTERFACE
READ HIGH BYTE
16 BIT INTERFACE
READ HIGH BYTE
8/16 BIT INTERFACE
READ LOW BYTE
240049-7
Figure 9. Read Data Latches
4.5 Exiting Wait States
4.6 Page Selection
There are many choices of clock speeds to run the
82786 in a graphics design. In addition, our design may
be interfaced to several different speed PC's. As a resuit, once IOCHRDY is released you cannot know exactly when the PC will come out of its wait state in
relation to SEN and the slave cycle.
As previously mentioned, our design uses the 64 kbyte
section of the PC's memory space located at the AOOO
segment. Our graphics board will contain 1 Mbyte of
memory, however. We must have some method of accessing the entire 1 Mbyte of graphics memory from
the PC's 64 kbyte window. This is accomplished
through the use of a simple paging scheme, as shown in
Figure 10.
For example, if the PC is writing to our graphics board,
write data will be held valid as long as the PC is kept in
a wait state. We need the write data to remain valid to
meet the data hold time as shown in Figure 5. If
IOCHRDY is released at the rising edge of SEN and
the PC is running at a fast clock rate, it is possible for
the PC to exit its wait state and remove the write data
too early in the SEN/DATA cycle. This can, of course,
be predicted exactly if all possible combinations of the
82786 and PC clock speeds are known. The exact time
to release IOCHRDY in order to hold data long
enough, yet not insert extra wait states, can be calculated.
A more conservative approach is to release IOCHRDY
off the falling edge of SEN, which has been done in this
design. For write cycles, this guarantees that write data
will be held past the entire SENIDATA cycle. Since we
are latching read data, it is held valid for whenever the
wait state ends. The tradeoff here is that performance
will be degraded somewhat since extra clocks. are inserted into every slave access.
10-230
827861 MEG
ADDRESS SPACE
IBM AT"
o
ADDRESS SPACE
OAOOOOht-_1-_ _ _- _
OAFFFFh
I-_.J---.a..;.;.;;.;......
OFFFFFh
240049-8
Figure 10. Page Selection
infef
AP-409
Pins SAO-SA15 directly drive 82786 pins AO-A15 to
address within a given 64 kbyte section of memory.
82786 pins A16-A19 determine which 64 kbyte memory section, or page, we address. We can drive these page
selection address lines with a latch which will contain
the desire page number from 0 to FH. Figure II shows
a block diagram of the page select circuit.
SDO-3
74374
G
IBM PC/AT"
lOW
ADDH.ES5....J
0300
f==: A16-19
Lines LA17-LA23 provide for address decoding down
to 128 kbyte resolution. Decoding addresses in 64 kbyte
sections would require an LA16 pin, which is not provided. Recall, however, that we were unable to find a
convenient 128 kbyte section of the IBM system memory space to use for our design. This means that we must
use address pin SA 16 for part of our decode. Since the
SA lines become valid later than the LA lines, we have
less time in which to decode an address and generate a
MEMCSI6.
Although both IOCHRDY and MEMCSI6 must be
brought low quickly, MEMCSI6 is the most critical
timing of the two. For an 8 MHz PC, we have 24 ns
from SAO-SAI6 valid to issue a MEMCSI6low signal
in order to cause a 16-bit access and -II ns to cause a
command delay. Fortunately we do not care about the
command delay. If we miss the window, any 16-bit accesses will automatically be broken into two 8-bit accesses.
82786
J
240049-9
Figure 11. Page Select Circuit
Our design latches the page number from data bits
DO-D3 by writing to I/O address 0300H. The output
of the latch will then drive 82786 pins A16-AI9.
5.0 SPECIAL CONSIDERATIONS
The circuit used to generate IOCHRDY and
MEMCS16 can be found in the complete board schematic in the Appendix. Figure 12 focuses on the particular circuitry of interest here. Fast logic devices are
required and the decode PAL must have a short propagation delay. This is particularly important since an
extra flip-flop is used to cause IOCHRDY to be released from the falling edge of SEN.
5.1 IOCHRDY and MEMCS16 Timing
For 16-bit accesses, IOCHRDY and MEMCS16 must
be brought low very quickly upon decoding an access to
the peripheral board. The purpose of signals
LA17-LA23 is to provide address lines for such decodes. These address lines become valid at the I/O
CHANNEL earlier than the latched address lines
SAO-SA19, providing more setup time for the decode
and generation of MEMCSI6. For this reason it is desirable to use the LA lines for decodes whenever possible.
5.2 Maximum Wait States
For medium and high resolution displays using
DRAM's, a significant portion of the available memory
bandwidth is required for the display process. To accomodate this, the display processor is programmed for
highest priority access into the graphics memory. In the
worst case the display processor can stay on the
10-231
inter
AP-409
memory bus continuously for more than 5 microseconds. This will happen while fetching 16 tile descriptors
(96 words).
The IBM AT Technical Reference Manual warns us
not to hold IOCHRDY low for more than 2.5 microseconds, which is 15 wait states in a 6 MHz machine
and 20 wait states in an 8 MHz machine. During wait
states the DMA controller can't obtain the bus to refresh memory, which results in delayed memory refresh
cycles.
If the 82786 is programmed with highest priority for
the display processor, then the external CPU will have
to stay in a wait state until the display processor releases the memory bus and SEN goes high. Although this
may not result in any erroneous operation, it will certainly violate the bus spec for wait state duration. In
order to meet the bus spec, the 82786 must be programmed with the highest priority for the external
CPU.
This will be acceptable if the CPU accesses the 82786
and graphics memory only during noncritical periods.
However, if the CPU needs to access the 82786 very
frequently, then the display processor may not be able
to refresh the screen in the required amount of time.
Therefore, if the CPU is programmed to highest priority, it must be restricted in its access to the 82786.
The latency between successive accesses from the CPU
to the 82786 can be approximated by the expression.
latency (in 82786 system clock cycles) ;0,
2' [8/((MMXR/DPXR)-1)]
where:
MMXR
maximum memory data transfer rate
(40 Mbytes/s if using interleaved, fast
page mode DRAM's at maximum
82786 bus clock speed)
DPXR = ((Xmax • Ymax • Bpp)/8) * Display
refresh rate
Xmax
=
no. of pixels in the x direction
Ymax = no. of pixels in the y direction
Bpp = no. of bits/pixel
NOTE:
"System clock cycles" refers to internal 82786 clock
cycles. 2 pin clocks = 1 system clock. For example,
20 MHz pin clock is equivalent to an 82786 10 MHz
system clock rate.
74F125
MEMCS16
A7-19
74F04
PAL
to
IOCHRDY
decode
address
AOOO
MEMW
MEMR
240049-10
Figure 12. IOCHRDY and MEMCS16 Circuitry
10-232
AP-409
One way to force this restriction on the CPU is to ensure that this latency is built into the software. This
implies that:
I) there are no block accesses into the graphics subsystem and
2) all single accesses are separated by instructions (e.g.
NaP) that will guarantee that the CPU stays away
from the 82786 for the desired time.
82786 sees the CS from the external CPU and services
it immediately since the request comes from a higher
priority source. The CPU does not stay in a wait state
for more than the maximum specified period.
This hardware method of restricting CPU accesses effectively increases the priority of the display processor
even though the external CPU is programmed for highest priority. At the same time, this method ensures adequate bus sharing between the display processor and
the external CPU.
This software method to control the CPU accesses will
allow single accesses into the graphics memory to be
serviced quickly, but at the same time, it imposes a lot
of restrictions on the programmer. Additionally, the
software becomes very specific to the hardware environment and portability of the software becomes limited. An alternative is to design the hardware to restrict
CPU access to the 82786.
A feature has been added to the D-stepping of the
82786 which allows for altered priority for external
CPU slave requests. The CPU will assume this altered
priority every 42 CLK's and will switch back to the
standard priority only upon execution of the slave CPU
bus cycle.
The scheme shown in Figure 13 delays the CS input
into the 82786 by some delay time. When the CPU
begins a memory cycle to the 82786, the address decode
logic pulls IOCHRDY low, putting the PC into a wait
state. The 82786 does not see this request immediately
and so the SEN output stays low, which will cause the
PC to remain in the wait state. Therefore, the display
processor, which is programmed for second priority,
can use the memory bus. After the delay time, the
By programming the CPU to have a standard priority
below that of the display processsor and an altered priority higher than the display processor, the previously
discussed software and hardware methods of restricting
CPU slave accesses to the 82786 are not necessary. This
new feature will allow the CPU to get a bus cycle every
2.1 microseconds (assuming an 82786 pin clock rate of
20 MHz) and still give the display processor highest
priority the rest of the time.
CPU
ADDRESS
82786 CLOCK
CPU
82786
SEN
READY
240049-11
Figure 13. Limiting the Rate of CPU Accesses to the 82786
10-233
inter
AP-409
APPENDIX A
82786 GRAPHICS BOARD DESCRIPTION
The 82786 based graphics board presented in this application note contains I Mbyte of fast page mode
DRAM's, which comprise the graphics memory for the
board. The memory is visible to the PC at address space
AOOOOH-AFFFFH, which is a 64 kbyte section of
memory. The entire I Mbyte of graphics memory is
addressable as 1664 kbyte banks, which are selected by
82786 address bits AI6-AI9. The desired bank is selected by writing the value on the lower four bits of the
data bus (DO-D3) to I/O address 0300H.
There is one other section of the PC address space that
can access the board. That is address C4400HC447FH. Accesses to this section of memory will cause
I/O accesses to be seen by the 82786. This allows access
to the Internal Registers, which reside in I/O space
when the 82786 comes out of RESET. The Internal
Registers remain I/O mapped and must be relocated to
I/O space base address 4400H (I/O space for the 82786
is only 64 kbytes-the upper address bits are ignored.
However, the upper 7 bits of the Internal Relocation
register must be programmed to O's when locating the
Internal Registers in I/O space).
The board supports a software reset. This is accomplished by writing a "I" on data bit 4 to I/O address
0300H and then a "0" on the same data bit to the same
address. When using software reset, care must be taken
to assure the proper values appear on data bits DO-D3
in order to not reprogram the page select register.
The board contains several jumpers which are described here:
I) There is a jumper to select a 16-bit vs. 8-bit interface.
16-bit interface is selected by inserting the jumper.
2) There are two jumpers to select between synchronous and asynchronous VCLK operation. In synchronous operation, VCLK is tied to CLK on the
82786. In asynchronous operation, VCLK comes
from a separate clock oscillator source. Only one of
these jumpers may be inserted at anyone time.
10-234
AP-409
APPENDIX B
82786 GRAPHICS BOARD PAL EQUATIONS
modul e UIO
title 'PAL I -- UIO
date april 2,1986'
UIOal
device 'P20l8';
PCAI9, PCAIS,PCAI7, PCAI6, PCAIS, PCAI4, PCAI3,
PCAI2, PCAII, PCAID, PCA09, PCADS, PCA07
pin I, 2, 3, 4, 5, 6, 7, 8, 9,10,11,13,14;
PCMEMR, PCP6IR, PCMEMW, PC lOW, lOCH ROY SELECT ,NCI,
NC2,PCIOR,PCP61
pin 23,22,21,20,19,18,17 ,16, 15;
equations
! PCP61
• PCAI9 & JPCAI8 & PCA17 & l PCAI6
& (PCMEMR $ PCMEMW) & PCIOR & PCIDW;
IPCP61R
• PCAI9 & PCAl8 & !PCA17 & lPCAI6 & JPCAlS & PCAl4 &
l PCA13 & l PCAl2 & ! PCAll & PCAlD & J PCAD9 & JPCACS &
l PCAD7 & (PCMEMR $ PCMEMW) & PCIDR & PCIOW;
l!DCHRDY_SELECT - (PCAI9 & lPCAlS & PCAI7 & !PCAI6) # (PCAI9 & PCAlS &
lPCA17 & !PCAI6 & lPCAIS & PCAI4 & lPCAI3 & JPCAl2
& ! PCAll & PCAIO & JPCAD9 & I PCADS & I PCA07);
end UID
240049-12
10-235
inter
AP-409
modul e Ull
title 'PAL 2 -- Ullq
date april 2, I 9S6'
Ullal
device 'P20LS';
PCA09,PCAOS, PCA07, PCA06, PCA05, PCA04,PCA03,
PCA02, PCAOI ,PCAOO,NCI
pin 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11;
PCMEMR, PAGE SELECT ,NC2,NC3,NC4,NC5, PAGE SEL, PCMEMW,NC6, PCIOW, PCIOR
pin 23,22,21,20,19, IS, 17,16,1"5,14,13;
equat ions
IPAGE_SEL
- (PCA09 & PCAOS & !PCA07 & !PCA06 & I PCA05 & !PCA04 &
! PCA03 & ! PCA02 & I PCAO I & I PCAOO & I PC I OW & PCMEMR &
PCMEMW) ;
PAGE_SELECT. PAGE_SEL;
end Ull
240049-13
modul e U26
title 'PAL 5 -- U26
date april 2, 1986'
U26al
device 'P20L8';
PCP61 ,SBHE, PCP61R, PCMEMR, P6SEN, LTCHBQ, NCI, PCAO, NCZ, NC3 ,NC4
pin 1,2,3,4,5,6,7,8,9,10,11;
NC9, CLRL TCHCNTR, PCP6CS, PCLATCHLO, PCLATCHHI, NC8, PC AT, P6BHE,
NU,~6,~5
pin 23,22,21,20,19,IS,17 ,16,15,14,13;
equations
! PCLATCHLO
. ! PCAO & (! PCP61 # ! PCP6IR) & I PCMEMR;
!PCLATCHHI
- PCAO & (!PCP61 # !PCP6IR) & !PCMEMR & PC_AT;
CLRLTCHCNTR
- (!PCP61 # IPCP6IR) & I PCMEMR & P6SEN & !LTCHBQ;
PCP6CS
- (!PCP61 # !PCP6IR);
P6BHE
- (!PC_AT & SBHE # PC_AT & !PCAO) & (IPCP61 #
! PCP6IR);
end U26
240049-14
10-236
intJ
AP-409
module U35
title 'PAL 6 -- U35
date april 2,1986'
U35al
device 'P20l8';
HC1, NC2, PCP6IR, PCP61, PCP6CS, NC3, NC4,
PCMEMR, PCMEMW,NC5,NC6
pin I, 2, 3, 4, 5, 6, 7, 8, 9,10,11;
NCIO,NC9,NC8, P6CS, P6WR, P6RD, P6RDYClK, T R, P6DEN,
NC7, P6SEN
pin 23,22,21,20,19,18,17,16,15,14,13;
equations
I P6CS
= PCP6CS;
IP6WR
• (IPCMEMW & (IPCP6IR
!P6RD
- (IPCMEMR & (IPCP6IR
IP6DEN
- «IPCP61 # IPCP6IR) & IPCMEMW & P6SEN);
T_R
((!PCP61
P6RDYClK
* IPCP61»;
* IPCP61»;
* IPCP6IR) & IPCMEMW);
• (PCP6CS S P6SEN);
end U35
240049-15
modul e U48
title 'PAL 7 -- U48
date april 2,1986'
U48al
device 'P20l8';
SBHE, PCMEMR, PC AT ,NCI, PCP6IR,PCP61 ,ClK,lAI6,
lA17, lA18, lAI9
pin 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11;
SAI7 ,ATOC,ClKI ,RESET_NOT ,RESET, NC2,NC3, P6_MIO,ACCI6,SAI9, SAI8
pin 23,22,21,20,19,18,17,16, IS, 14, 13;
equat ions
IATOC
- IS8HE & IPC_AT & IPCMEMR & (IPCP61 , IPCP6IR);
!ACCI6
= SAI9
& ISAl8 & SA17 & IlAI6 & IPC_AT;
IP6_MIO - IPCP6IR;
ClKI
- IClK;
RESET_NOT • I RESET;
end U48
240049-16
10-237
intJ
AP-409
module US2
title 'PAL S -- US2
date april 2,1986'
US2al
device 'P20LS';
NCI, PAGE_SELECT ,NC2, P6SEN, PCP6IR,PCP61 ,PCHEMW,
PCAO, PCION, PCMEMR,PCIOR
pin 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11;
~~~EmTAg~~p~:m~D:~~ s~~~L~E~~¥ET , 10CHRDV ,NC4,
-
pin 23,22,2I,20,19,IS,17,16,IS,14,13;
equations
_24ST_RI
- (PCMEMR & PCIOR) , (!PCHEMW , IPCION);
!PCDLO
- ((IPCP61 , IPCP6IR) & !PCAO & (IPCHEMW , !PCION»
, I PAGE_SELECT;
RESET
- (HANURESET , PCRESETDRV , SOFT_RESET);
!IOCHRDV
- (IPCP61 , IPCP6IR) & !P6SEN;
IADDR_ENABLE - (!PCP61 , !PCP6IR);
end US2
240049-17
module US4
title 'PAL 9 -- U54
date april 2,I9S6'
U54al
device 'P20LS';
PCP61, PCHEMR, PCP61R, NCI, NC2, NC3, PCAO,
PCMEMW ,NC4,P6SEN,SBHE
pin 1, Z, 3, 4, 5, 6, 7, 8, 9',10,11;
PCIOR,NCIO,NC9,NCS,PCD AT,PCD HI,
NC7,NC6,NCS,PC AT,PCIOW
pin 23,22,21,20,19, IS,17 ,16,IS,14,13;
equations
IPCD_HI • (IPCP61 , IPCP6IR) & PCAO & PC_AT & PCMEMR;
IPCD_AT • (IPCP61 , IPCP6IR) & fPC_AT & !SBHE & PCMEMR;
end US4
240049-18
10-238
inter
AP-409
APPENDIX C
82786 GRAPHICS BOARD SCHEMATICS
10-239
.
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Development Tools
11
805. SOFTWARE DEVELOPMENT PACKAGES
COMPLETE SOITWIIRE DEVELOPMENT SlIPPORTFOR THE
IfICS1'-51 FlllfIlLY OFIfIICROCONTROLLERS
Intel supports application development for its MCSQl-51 family of microcontrollers with a complete
set of development languages and utilities. These tools include a macrtJasspmbler, a PUM compiler,
linkerirelocator program. a librarian utility, and an object-to-hex utility. Develop code in the
language(s) you desire. then combine object modules from different languages into a single, fast
program. These tools were designed to work with each othCI~ with the MCS-51 architecture, and with
the Inte11C"5100 in-circuit emulator.
FEIlTlIRES
• Support for all members of the Intel MCS-51
family of embedded microcontrollers
• ASM-51 Macroassembler
• PUM-51 high-level language
• LinkerlRelocator program
•
•
•
•
Library utility
Object to hexadecimal converter
Hosted on IBM PC XTiAT V. 3.0 or later
Worldwide service and support
imJ-----------------------Inld COrjMlrtlllun as:';l.Iml':~ nil n'SJlonsilli1il~ rill' WI.' lL-" or nil)" (irmitr)' (Ilh('r tll.1n l'II'('ullr~ l'mhu(il{'ti in an 10l.\'lllrullll(1. Nn utlll'I' fll'I'U!lll:gisten:'C:I trall('maitl'! (If InLernational Bu:dnrKs Marhmr.'s CUllMlrallun
11-3
€OMrU'I'E SOITWIIRE DEt'EWPMENT SIJProR'I' I!OR THE
B0961196 FIIMILY OF MI€RO€ON'I'ROJ,J.ERS
Int.el supports application development for its 8096 and 80C 196 family of microcontrollers with a
complete set of development languages and utilities. These tools include a macroassembler. a PUM
compiler. a C compiler. Iinker/relocator program. noating point arithmetic library. a librarian utility.
and an object·to·hex utility. Develop code in the language(s) you desire. then combine object modules
from different languages into a single. fast program.
FEII'I'IJRES
• Software Tools support all members of Inters
MCS·96 family
• ASM·961196 macroassembler for speed
critical code
• PUM·96/196 package for the maintainability
and reliability of a high·levellanguage with
support for many low· level hardware
functions
• iC·96/196 package for structured C language
programming. with many hardware speCific
extensions
• LinkerlRelocator program for linking modules
generated in assembler. PUM or C and
assigning absolute addresses to relocatable
code. RL·96 prepares your code for execution
in target with a simple. one-step operation
• 32·bit Floating Point Arithmetic Library to
reduce your development effort and to allow
fast. highly optimiZl'U nunwrics'intrnsive
processing
• Lihrary utility for creating and maintaining
software object module lihraries
• PRO\l building utility that converts object
modules into standard hexadecimal format
for easy download into a rum·lntel PROM
Programmer
• Hosted on IBM PC XT/AT with PC-DOS 3.0 or
above
iMJ-----------------
1ntl'l GJrpuraLlOn nS:\lIm~'S nn rt'SpunSlhllll~ fur Ihr us..' ,I an} rJrC'ulll) ulhl'r lhan t'lrrullr~ t'lTlhlldil'd III .111 I1II.1'Ivm1.!LK't. Nu utht'r rirl'UlllJall'nt Ikl'nSl't! iln'
ImplKiI Inlnrmallofl ('ontalf'lrd tll.'fl'm :mpc.'r§C'drs fII't'\'lIll1Sl~ publisht'd IIp'-'C'lrl(,Cllluns un thl'Sl'Ik'\-,n,.. f","llnt,~ aud iK ,;Uhll'\'! W I'h:IIII.'I.' '101111111.1\ nuti,\'.
&·lltl'l11hl.... IfIHH
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11-4
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Floating Point
Llbrarl•• With
Figure •. \lCS@·96 Application Development Process
ASItI-96/196 ItIACROASSEItIBLER
'\S~I·96J 196
is the macroassembler For the \ICS·96 Family
of mit'roconll'Oliers. inclu(ling lIw 80CIH6 ..\SM·fJ6JI96
translat('s symbolic assemhly language mn.'monies int.o
rl'locatahle ohjl'l'l cO(lc.
'I'hl' macl'O facility in ASM+)(l1l 96 saves iI('l'l'Iopl1l1'l1I. allil
maintL'mncc tinll', sincL' I'IImmon ('mit' sL'qucnL'es l1I'I'Ii only
be IIL'VI'lopL'd oncL'. 'I'lli' "ss('mhler also SUppOl'ts symilolic
W'L'('SS to 1.I1l' Illany 1'l';,Ps~r::I~~~a~~;ntt.
;8087slock
:Wtthth. t.:rIlnput, OUTPUTVALU[lsn(lw abaut
:-0,5511280J
8087 SUPPORT
LIBRARY
231613-1
Figure 1. Use of 8087 Support Library with PL/M-86 and ASM-86
11-19
October 1988
Order Number: 231613-002
inter
8087 SUPPORT LIBRARY
CEL87.LlB
THE COMMON ELEMENTARY FUNCTION LIBRARY
mqerSNH,
FUNCTIONS
mqerAT2
CEl8?LlB contains commonly used floating point
functions. It is used along with the 808? numeric coprocessor. It provides a complete package of elementary functions, giving valid results for all appropriate inputs. Following is a summary of CEl8? functions, grouped by functionality.
mqerlEX,
mqerlAX,
mqerlCX,
mqerlE2, and mqerlE4. Round a real
number to the nearest integer; to the
even integer if there is a tie. The answer returned is real, a 16-bit integer
or a 32-bit integer respectively.
mqerlA2, mqerlA4. Round a real number to the nearest integer, to the integer away from zero if there is a tie; the
answer returned is real, a 16-bit integer or a 32-bit integer, respectively.
mqerlC2, mqerlC4. Truncate the fractional part of a real input; the answer
is real, a 16-bit integer or 32-bit integer, repectively.
Logarithmic and Exponential
Functions:
mqerlGD
mqerlGE
mqerEXP
mqerY2X
mqerY12
mqerY14
mqerYIS
computes decimal (base 10) logarithms.
computes natural base (base e) logarithms.
computes exponentials to the base e.
computes exponentials to any base.
raises an input real to a 16-bit integer
power.
'
is as mqerY12, except to a 32-bit integer power.
is as mqerY12, but it accommodates
Pl/M-286 users.
Trigonometric and Hyperbolic
Functions:
mqerSIN,
mqerASN,
Other Functions (of real variables):
mqerDIM
mqerMAX
Rounding and Truncation Functions:
mqerCOS, mqerTAN compute sine,
cosine, and tangent.
mqerACS, mqerATN compute the
corresponding inverse functions.
mqerCSH, mqerTNH compute the
corresponding hyperbolic functions.
is a special version of the arc tangent
function that accepts rectangular coordinate inputs.
mqerMIN
mqerSGH
mqerMOD
mqerRMD
is FORTRAN's positive difference
function.
returns the maximum of two real inputs.
returns the minimum of two real inputs.
combines the, sign of one, input with
the magnitude of the other input.
computes a modulus, retaining the
sign of the dividend.
computes a modulus, giving the value
closest to zero.
Complex Number Functions:
mqercCMUl, and mqercCDIV perform complex
multiplication and division of complex
numbers.
mqercCPOl converts complex numbers from rectangular to polar form. mqercCREC
converts complex numbers from polar
to rectangular form.
mqercCSQR, and mqercCABS compute the complex square root and real absolute
value (magnitude) of a complex number.
mqercCEXP, and mqercClGE compute the complex value of e raised to a complex
power and the complex natural logarithm (base e) of a complex number.
mqercCSIN, mqercCCOS, and mqercCTAN compute the complex sine, cosine, and
tangent of a complex number,
mqercCASN, mqercCACS, and mqercCATN com- '
pute the complex inverse sine, cosine, and tangent of a complex number.
mqercCSNH, mqercCCSH, and mqercCTNH compute the complex hyperbolic sine, cosine, and tangent of a complex number.
'
11-20
8087 SUPPORT LIBRARY
mqercCC2C, mqercCR2C, mqercCC2R, mqercCCl2,
mqercCCl4, and mqercCCIS return
complex values of complex (or real)
values raised to complex (real, short
integer, or long integer) values.
mqercCACH, mqercCASH, and mqercCATH compute the comples inverse hyperbolic
sine, cosine, and tangent of a complex number.
DC87.LlB
THE DECIMAL CONVERSION LIBRARY
DC87.L1B is a library of procedures which convert
binary representations of floating point numbers and
ASCII-encoded string of digits.
The binary-to-deCimal procedure mqcBIN_DECLOW accepts a binary number in any of the formats used for the representation of floating point
numbers in the 8087. Because there are so many
output formats for floating point numbers, mqcBIN_
DEC LOW does not attempt to provide a finished,
formatted text string. Instead, it provides the "building blocks" for you to use to construct the output
string which meets your exact format specification.
The decimal-to-binary procedure mqcDEC_BIN accepts a text string which consists of a decimal number with optional sign, decimal pOint, and/or powerof-ten exponent. It translates the string into the caller's choice of binary formats.
Decimal-to-binary procedure mqcDECLOW_BIN is
provided for callers who have already broken the
decimal number into its constituent parts.
The procedures mqcLONG_TEMP, mqcSHORT_
TEMP, mqcTEMP_LONG, and mqcTEMP_SHORT
convert floating point numbers between the longest
binary format, TEMP_REAL, and the shorter formats.
EH87.lIB
THE ERROR HANDLER LIBRARY
EH87.L1B is a library of five utility procedures for
writing trap handlers. Trap handlers are called when
an unmasked 8087 error occurs.
MAL in your trap handler, you eliminate the need to
write code in your application program which tests
for non-normal inputs.
The 8087 error reporting mechanism can be used
not only to report error conditions, but also to let
software implement IEEE draft standard options not
directly supported by the chip. The three such extensions to the 8087 are: normalizing mode, non-trapping not-a-number (NaN), and non-ordered comparison. The utility procedures support these extra features.
SIEVE provides two capabilities for handling the "I"
exception. It implements non-trapping NaN's and
non-ordered comparisons. These two IEEE draft
standard features are useful for diagnostic work.
DECODE is called near the beginning of the trap
handler. It preserves the complete state of the 8087,
and also identifies what function called the trap handier, and returns available arguments and/or results.
DECODE eliminates much of the effort needed to
determine what error caused the trap handler to be
called.
ENCODE is called near the end of the trap handler.
It restores the state of the 8087 saved by DECODE,
and performs a choice of concluding actions, by either retrying the offending function or returning a
specified result.
FILTER calls each of the above four procedures. If
your error handler does nothing more than detect
fatal errors and implement the features supported by
SIEVE and NORMAL, then your interface to
EH87.L1B can be accomplished with a single call to
FILTER.
NORMAL provides the "normalizing mode" capability for handling the "0" exception. By calling NOR-
11-21
8087 SUPPORT LIBRARY
SOS7.LIB, NULS7.LIB, ESOS7.L1B
INTERFACE LIBRARIES
E8087.L1B, 8087.L1B and NUL87.L1B libraries configure a user's application program for the run-time
environment; running with the 8087 component or
without floating point arithmetic, respectively.
FULL 8087 EMULATOR
SPECIFICATIONS
The Full 8087 Emulator is a 16-kilobyte object module that is linked to the application program for floating-point operations. Its functionality is identical to
the 8087 chip, and is ideal for prototyping and debugging floating-point applications. The Emulator is
an. alternative to the use of the 8087 chip, although
the latter executes floating-point applications up to
100 times faster than an 8086 with the 8087 Emulator. Furthermore, since the 8087 is a "coprocessor,"
use of the chip will allow many operations to be performed in parallel with the 8086.
Operating Environment
Intel Microcomputer Development Systems (Series
,
III, Series IV)
Documentation Package
8087 Support Library Reference Manual
ORDERING INFORMATION
8087 Support Library is included in ASM-86 Assembler package on the following hosts.
Part Number
D86ASM86NL
VVSASM86
MVVSASM86
Description
ASM-86 Assembler for PC XT or AT System (or
compatible) running DOS 3.0 or higher.
ASM-86 Assembler for VAXIVMS.
ASM-86 Assembler for Micro VAXIVMS.
Requires Software License
SUPPORT
Intel offers several levels of support for this product
which are explained in detail in the price list. Please
consult the price list for a description of the support
options available.
11-22
PSCOPE-86 FOR DOS
HIGH-LEVEL APPLICATION PROGRAM DEBUGGER
Debugs PL/M-S6, Pascal-S6, iC-S6,
• FORTRAN-S6,
and ASMS6 Programs
Program Text on the Screen
• Displays
During Debugging:
Symbolic Debugging
• Offers
Capabilities:
- Supports Access to Memory by
Program Defined Variable and
Program Names
- Maintains Type Information About
Variables
- Allows Definition of User-defined
Debugging Variables and Procedures
- Uses the Listing File to Display
Program Text
- Displays Source Code on Program
Step, at Execution Break POints, or
on User Request
Through Assembly
Memory and Provides an
• Single-steps
• Disassembles
Language Instructions, High-level
Interactive Assembler
Language Statements, or Procedures
Creation of Program Patches
• Permits
Sets
Break Points and Traces Program
Using High-level Language Constructs
• Execution
Access to DOS Operating
• Supports
Runs Under the PC-DOS Version 3.0 or
System Commands
• Greater
PSCOPE-86 for DOS is an interactive, symbolic debugger for high-level language programs written in iC-86,
PL/M-86, Pascal-86, and FORTRAN-86, and for assembly language programs written in ASM86. PSCOPE-86
for DOS runs under the PC-DOS operating system, version 3.0 or greater.
'LIST a:debug.log
"LOAD \progdir\leapyr .86
"SET :leapyr to \listdir\leapyr .1st lang pascal
"DIR LINE
DIR of :LEAPYR
#1
#5
#6
#7
#8
#9
#10
#11
#12
#13
#14
#15
#16
#17
#18
#21
#22
#23
#25
'PRESRC=O ;POSTCRC=O ;SOURCE=true ;GO TIL #13
Enter the number of a month.
2
Enter any year, like 1985.
1984
[Break at :LEAPYR#13]
=>
13
24
0
2
CASE month of
+LSTEP
[Step at LEAPYR#16]
2: (. leap year 0)
=>
16
27
0
3
IF (year mod 4 = 0) AND «year mod 100 <> 0) OR
(year mod 400 = 0))
280194-1
11-23
September 1988
Order Number: 280194-003
inter
PSCOPE-86
MAJOR FEATURES
With PSCOPE-86 for DOS, a user can load an application program, set break points at symbolic or numeric
addresses, trace program execution, and view source code text. Program bugs can be patched using high-level PSCOPE commands or assembly code. The corrections can be tested without leaving the PSCOPE software.
Other debugging aids include the ability to single-step a program through assembly language instructions,
high-level-language statements, or procedures, to display and modify program variables, to inspect files, and
to personalize the debugging environment.
The following sections describe some of the major features of PSCOPE-86 for DOS.
Source Display
With the DOS version of PSCOPE-86, a user can correlate a module under debug to a source code file. Then,
when break points are encountered, source text is displayed along with the break message and line number of
the break point. The number of source lines displayed before and after a break point can also be defined by
the user.
View all or part of the listing file on command. The following example uses the PSCOPE command to list the
current module. The asterisk (*) is the PSCOPE prompt, the command follows, and after pressing ,
PSCOPE responds with a list file.
*SHOWSRC #1 LENGTH 28
0
0 program leapyr (input,output) ;
1
1
(* Input month and year, receive number of days *)
2
:integer;
5
0
0 var year
month
:integer;
3
0
6
0
4
7
nrdays :integer;
0
0
5
9
0
0
5
6
7
11
12
13
0
0
0
1
1
1
begin
8
9
10
15
16
17
0
0
0
1
1
1
11
19
0
1
11
12
21
22
0
0
2
2
13
14
15
16
24
25
26
27
0
0
0
0
2
3
3
3
17
31
0
3
CASE month of
4,6,9,11:nrdays := 30;
1,3,5,7,8,10,12:nrdays := 31;
2: (* 1.eap year *)
IF (year mod 4 = 0) AND ((year mod 100 <> 0) OR
(year mod 400 = 0))
THEN nrdays : = 29
ELSE nrdays: = 28;
19
33
0
3
end;
21
35
0
2
22
23
37
38
0
0
2
2
25
40
0
1
month := 0;
year := 0;
nrdays .= 0;
writeln('Enter the number of a month.');
readln(month) ;
while month < > 999 do
begin
writeln('Enter any year, like 1985.');
readln(year) ;
writeln('Number of days in the month is',nrdays);
writeln('Enter the number of a month.');
readln(month)
end;
end.
11-24
PSCOPE-86
Single-Stepping
PSCOPE has two commands to single-step through high level instructions and display source code. The
commands,differ in how they handle program calls. The following example illustrates the LSTEP command.
'LSTEP
[Step at
=> 17
19
"LSTEP
[Step at
=> 21
:LEAPYR#17]
31 0 3
33 0 3
:LEAPYR#21]
35 0 2
ELSE nrdays ._ 28;
end;
write1n('The number of days in the month is',nrdays);
PSCOPE can single-step through code at assembly level and display assembly mnemonics as in the following
example which uses the ISTEP command.
'ISTEP
:LEAPYR
512A:00FEH
C70600000000
MOV WORD PTR OOOOH,O
Symbolic Debugging
With symbolic debugging, a user can examine or modify a memory location by using its symbolic reference. A
symbolic reference is a procedure name, variable name, line number, or program label that corresponds to a
location in the user program's memory space. For example, to display the value of the program variables,
users need only execute the program until the variable is active and type that variable's name.
'LSTEP
[Step at :LEAPYR#22]
=> 22 37 0 2
"month
+2
'year
+1900
"nrdays
+28
write1n('Enter the number of a month.');
Define the Debug Environment
With the PSCOPE high-level program debugger, a user can define the debugging environment within PSCOPE
software. You can define break points and trace points. With PSCOPE, you can write macros that set the
debug environment when PSCOPE is invoked, or these macros can be included at any time during the
debugging session. Shorten commands with literal definitions, try program bug fixes with patches and procedures, or write procedures to control program execution. All debug variables and procedures can be saved in
files and reused.
BREAK REGISTERS AND TRACE REGISTERS
Breaks occur at addresses in the program under execution. The user can enter physical addresses or symbolic
addresses to halt program execution. With PSCOPE, you can easily break at executable statement addresses
by using line numbers. Simply use the PSCOPE directory command with the line option (DIR LINE) to get a
directory of line numbers. Then define a break register or a trace register to stop at these addresses.
A break register (BRKREG) stops program execution and returns a PSCOPE prompt (*). A trace register
(TRCREG) displays a message and continues program execution. Following are examples of how to define a
break register and a trace register.
'DEFINE BRKREG stop = #22
*DEFINE TRCREG stop2 = #17
11-25
intJ
PSCOPE-86
DEBUGGING PROCEDURES
Debugging procedures are groups of PSCOPE commands that have been labeled. Writing procedures with
PSCOPE commands is much the same as writing high-level language procedures. A procedure can be used
for any definable function during a debugging session, and it can be used with a program under execution.
In the LEAPYR program, the while loop continues until 999 is entered for a month number. The following
example of a PSCOPE procedure (PROC) that querys the user about halting execution. If the answer is yes CY'
or 'y'), the procedure sets month to 999.
'DEFINE PROC query = DO
• 'WRITE USING ('Do you want to quit ?Enter Y for yes.')
• *DEFINE CHAR ccc = CI
• *WRITE ccc
• 'IF ccc = = 'Y' or 'y' then
• • *month = = 999
• • *RETURN = true
• • *else RETURN = false
• *endif
• *END
To call this procedure while the program is executing, define a break register and use it with the GO command
as follows:
*DEFINE BRKREG stop =
*GO USING stop
#22 CALL query.
PSCOPE PATCHES
A PSCOPE patch is used to temporarily correct run-time errors in the program under debug. A patch can be an
additional line (or lines) in a program, or can be used to replace lines in a program. PSCOPE enables both
high-level patches (the PATCH command) and assembly-level patches (the ASM command).
High-Level Patch
In the LEAPYR program, the way to exit the program is to enter 999 for the month. However, nothing instructs
the user to do this. With a high-level patch, it is simple to add a line of code to the program. Following is an
example.
'DEFINE PATCH #22 = WRITE 'To exit the program, enter 999.'
When the program is executed, the patch is used automatically. There is no need for a break register. Program
execution stops at line number 22, the patch message is displayed, and program execution continues at line
number 22. It is also possible to replace lines by using the TIL option in a high-level patch. Then program
execution continues from the line number, or address, defined after the TIL. To simply eliminate lines of code,
set the line to NOP as follows:
'DEFINE PATCH # 18 = NOP
Assembly-Level Patch
Assume there is a typo in the LEAPYR program. Instead of the else condition setting nrdays to 28, it sets
nrdays to 29, making every year leap year. Use the ASM command first to display assembly code as in the
following example.
'ASM #17 LENGTH 4
:LEAPYR
521A:01EOH
C70600001DOO
521A:01E6H
EB06
=> 17 31 0 3
521A:01E8H
C70600001DOO.
521A :OlEEH EBOO JMP $ + 0002H
MOV
JMP
WORD PTR OOOOH,OOlDH ;+29T
$+0008H
; A=OlEEH
ELSE nrdays : = 29;
MOV WORD PTR OOOOH, OOlDH ; + 29T
; A=OlFOH
11-26
intJ
PSCOPE-86
Notice that source code can be displayed to assist you in finding the ELSE statement. However, source
display can be eliminated simply by setting the variable SOURCE to false. After finding the address for the
correct line of code, use the ASM command to change the second 29 to 28. Notice in the following example,
'word' is sufficient for the assembly mnemonic. The 'ptr' mnemonic is unnecessary.
'ASM 521A:OIE8H = 'mov word OOOOH,OOlCh'
521A:OIE8H
C70600001COO
MOV WORD OOOOH,OOlDH
LlTERALLV DEFINITIONS
LITERALLY definitions are shortened names for previously defined character strings. LITERALLY definitions
save keystrokes or improve clarity. For example, the following LITERALLY definition replaces the command
DEFINE with the abbreviation DEF.
'DEFINE LITERALLY def
=
'DEFINE'
Save and Restore the Debug Environment
All debug variables and procedures can be saved in a file for future debug sessions. To save everything in a
file, use the PUT command as follows:
'PUT a:debug.mac DEBUG
The saved file can be used as a macro and invoked automatically with PSCOPE by using the following
invocation command to start PSCOPE.
C: >PSCOPE MACRO (a :debug.mac)
After PSCOPE is loaded, a list of all the commands in the macro will print to the screen and will be included in
the debug environment. It is also possible to include a macro after PSCOPE is loaded. The following example
uses the NOLIST option to prevent the commands from writing to the screen.
'INCLUDE a:debug.mac NOLIST
The Internal Editor
PSCOPE has an internal editor that is a version of Intel's Aedit. Use this editor to correct source code as
program fixes are confirmed with PSCOPE. The editor can also be used to create macros, procedures, or
correct command lines.
Escape to DOS
PSCOPE has an escape function to enable access to the DOS operating system commands. This is very
useful to verify a file location or print a file. Any DOS operating system command is accepted after entering the
'bang', explanation point, (!). The following is an example of the ESCAPE command.
• !print a:debug.mac
The DOS print message will appear on the screen, and then the PSCOPE prompt. Once the printing is
complete, you are again in PSCOPE withoutaltering the debug environment.
The PSCOPE Command Language
The syntax of PSCOPE commands resembles that of a high-level language. The PSCOPE command.language
is versatile and powerful while remaining easy to learn and use because commands are often self explanatory
like GO. GO starts execution of the user program.
11-27
inter
PSCOPE·86
The PSCOPE command language can be divided into functional categories.
• Emulation commands instruct PSCOPE to execute the user program. They consist of GO and the three
stepping commands, ISTEP, LSTEP, and PSTEP.
• Debugging environment commands define PATCHes, debugging PROCedures, debugging variables, LlTERALLYs, break registers (BRKREG), and trace registers (TRCREG) using the DEFINE command. A user
can also delete these definitions with the REMOVE command.
• Block commands consist of DO-END, COUNT-END, REPEAT-END, and IF-THEN-ELSE constructs. They
can be used alone or within debugging procedures and patches.
• String functions concatenate strings (CONcAT), return the string length (STRLEN), return a substring
(SUBSTR), and accept console input (CI).
• Utility commands are general-purpose commands for use in a debugging environment. They consist of the
following:
accesses the DOS operating system commands.
$
is a pseudo-variable that represents the current execution point.
ACTIVE
is a function that determines whether a specified dynamic variable is currently defined on
the stack.
ASM
assembles or disassembles memory.
BASE
sets or displays the current radix.
CALLSTACK
displays the dynamic calling sequence stored on the stack.
DIR
displays all objects of a specified type.
EDIT
invokes the internal, menu-driven text editor.
EVAL
returns the value of a symbol in binary, decimal, hexadecimal, and ASCII.
EXIT
returns control to the host operating system.
HELP
provides on-line help for selected topics and selected error messages.
NAMESCOPE
is pseudo-variable that represents the current scope of a variable. It gives access to
variables without requiring a fully qualified symbolic reference.
OFFSET$OF
is a function that returns the offset of a specified address (virtual or symbolic).
SELECTOR$OF is a function that returns the selector of a specified address (virtual or symbolic).
WRITE
writes variables and strings to the console's screen.
• File handling commands access disk files. The user can load program files to be debugged (LOAD), save
patches, debugging procedures, debugging variables, LlTERALLYs, and debugging registers in a disk file
(PUT and APPEND), read-in these definitions during later debugging sessions (INCLUDE), and record a
debugging session in a disk file for later analysis (LIST and NOLlST).
• Register access commands provide access to the 8086/8088 registers and flags.
The REGS command displays the 8086/8088 registers and flags. Users can also inspect or change an
individual register by specifying its mnemonic. For example, CS represents the code segment register.
The FLAG pseudo-variable represents the 8086/8088 flag word. The user can also inspect or change each
flag separately as a Boolean variable. (For example, TFL represents the trap flag).
PSCOPE provides register access for programs that perform real arithmetic. There is a built-in 8087 math
coprocessor emulator, or there is a CH8087 option with the LOAD command to tell PSCOPE to access the
hardware (8087 math coprocessor chip) registers. Access or change the 8087 registers by name.
• Source display commands are used to view a specified number of lines of source text at break points or on
demand. LPATH or SET directs PSCOPE to the source text file. SOURCE is the pseudo-variable used to
determine if source text will be displayed at break points. With PRESRC and POSTSRC, the user can
determine how many lines of source code will be displayed before and after the line at the break point. The
SHOWSRC command enables the display of source code outside of program execution.
11-28
PSCOPE-86
SPECIFICATIONS
Memory Requirements
PSCOPE-86 for DOS requires approximately 300KB of memory for PSCOPE software and buffers.
DOS Version
PSCOPE is designed to run on the DOS operating system version 3.0 or greater.
Language Support
iC-86
PLlM-86
FORTRAN-86
ASM86
PASCAL-86
ORDERING INFORMATION
Order Code
Description
D86PSC86NL High-Level Software Debugger
11-29
INTEl. 1(;-86 (; (;OMPII.ER
IN'I'E£ 1£-861l4.0 £OItlPlLEIl
Intel's ie-86 R4.0 is a new generation C compiler for the 80861186 family of mi('l'Ilpl"Ill'l'Ssors,
providing unparalleled performance for embedded micmpI'IlC('ssor designs. In addition to
, outstanding execution speed, Inters iC·86 also offers low memory consumption, RO\lability, and
easy debug.
1£-861l4.0 £OItlPlLEIl J'EA'I'IJIlES
• State-of-the-art code generation teChnology
• Built-in functions for automatic machine code
generation
• ROMabie code and libraries
• Outstanding optimization
• Inte{lrated debugging with Intel ICE'" and
12IC~'"
• Compliance with draft ANSI standard
• Supports multiple memory models: Small,
Medium. Compact, and Large
i~
• Linkable with oLilt'r Inl.l'IIlOH6 lanllua!.~'S
such as ASM-8ti amiI'I J~I-Hti
• ROMahie and rt't'ntrant lihraril's
• Ability 1.l1 mix m('mory mm\l'ls with "nt'Hr"
and "far" pointers
• Compatible with oth('r C(~lml)II('rs and PIJM
providing both standal'l! C and PIAl callinll
conventions
__~______~____~
If1'; and FICIo; an' trade'man.s Illnll'l Curpural.llln.
Intl'! rJlI"lJlltnUnn a~:o!umt':t nu n'SplllINlbllll> fnr lilt' u:II:' I~ an) I'if'j·uil.r~ !llhI'r loon t'ln'OIlr) l'IfIIlIIIII"I," an Inll'IlJrlllhK1. Nu "thl'!' I1n'llll~nl'lllIK,·n:;.,'S iln'
,"11!lit'll. InfurmallUn ('lInlalFll'd !lITt'!n ~Pl'I'N('dt'S IIA'\lllIJSI~ publlsht'd !I'II~"iraUnn!l 1m Uk':il' dl'\II't'N fmm In1l'1.
~i·hru.;u~.
@
IAIiM
OrtiL'r ·'\IImb,'S'. 2Htl7HNIU3
tml'! (~"lMlI'ilUlln 19HH
11"30
1J1J1l.1'-IN I'IlNt;I'IONS
RlIN-I'IME SlIPrtlRI'
1C-86 R4.0 is loaded with built·in functions that directly
generate machine code within the C language. iC·86·s built·
ins eliminate the need for in·line assembly language
programming by allowing you to program in a high·level
language ali the time. speeding software development and
simplifying software maintenance. The built·ins also allow
you to develop highly optimized code by extending the
compiler instruction set-with built-ins you r.an enable or
disable interrupts and directiy control hardware VO without
having to exit C for assembler. This means you can write
high performance software for real time applications without
having to keep track of every architectural detail. as you
would in assembly language. For example. to generate an
INT instruction. you simply type:
STOIO run-time libraries for iG86 are targeted to a generiC
POSIX interface. with d!lCUmentation provided for interfacing
with your embedded target system. This means you can
r.asily retarget the libraries for use in your target
application. regardless of operating system. These libraries
support the complete draft ANSI standard. For iCr86
versions on DOS. Intel provides the interface between the
STOIO libraries and the DOS operating system_ This allows
you to develop. test. and debug your embedded application
code on ~OS. or write applications directly for ~OS.
causeinterrupt(number)
Or. the following iC-86 instruction will cause thn pnlCessor
to come to a halt with interrupts enabled:
halt( )
EMIlEDDBD COMPONENI'SlIPrtlllT
ie-S6 was designed specifically for embedded
microprocessor applications. Ie-B6 produces ROMabie mde
which can be loaded directly into target systems via Intel
ICE emulators and debugged without modific1Jtion for fast.
easy. development and debugging.
HIGlUl' OPl'IMIZED
iGS6 Is based on Intel's latest code generation techniques
for developing high-performance applications. and has been
optimized for developing embedded applications. Four levels
of optimization are available. Important optimization
features include a jump optimizer and improved register
manipulation via register history. In addition. the PUM
calling convention will improve performance significantly. An
example of the optimization in iC-86 R4.0 is its outstanding
performance on the Ohrystone benchmark. Using a Compaq
386. iC-86 produced the following resulLs:
Microsoft 4.0 Microsoft 5.0 Intel iC-86
Execution
Speed
(dhrylscc)
3571
3333
3369
INI'EGR!lI'ED DEIJIJG 'I'fJfIl.S
1m
iGS6 has been designed to work with Intel's
family of
in-circuit emulators (1 2ICE. ICE-186. ICE-2B6. and ICE-386)
and performance analysis 1.!MIls (iPAT). Inlel software
debuggers. linkers. 1!lC8tors. and other software
development 1.!Xlls. In addition to the object records required
for program execution. iC-86 object code contains detailed
debug records that describe the actual symbols and variable
names you defined in your source code. A complete listing
file can also be pnlduced. Intel's "Integration by design" of
ali development tools. including iCrRB. will speed the
development of your embedded mlcnlprocessor applications.
Figure 1 illustrates the steps in going [mOl Csource code to
PROM- or ICE-loadable object elide with IC-86.
SERl'ltJE !lND SlIPPOIlI'
Intel's development tools are backed by our worldwide
service and support organization. which is set up to deal
with pmblems encountered by embedded component
designers. Our field apillir.atinn experts get you up and
running quickly. and our hands-on training workshops
ensure that you have a thorough understonding of how our
tools work. Intel compilers come with 90 days of technical
support. troubleshooting guides. applicotion newslcttcl'8.
and optional support contracts.
11-31
@
o
1--F:l
LtJ
la
ICE .........
CODE
SPEt:IFIt:ATIONS
ENnRONItIEIW'I'
II'~ Ilulilil'>llttl:'jll.'["lfk,llion.' lin 111\,:;1' d("'ln'~ frllm Imd ,1011 IS 1'I1Ihll'll ttl rhan;,:!' .... UhllUl flIlIU,'
Sq)\l'mtwf.19M
© Inll'i (mpllratlufl 19BH
flrcln
11-51
~umh:r
1HII7IlHltJ:l
MEl' tJfllfIPII.,t'I'IflN I"tttJlLf6B
1'BA.I'IJIlBS
• Tight, efficient, 32-bit 80386 code
-Generated code designed and optimized for the 80386
architecture
• BUilt-in support for the 80386
-Full representation specifications, including address
clauses
-Machine code insertion
• 80387 coprocessor support
-Full IEEE numerics support
• pragma INTERFACE
-Call modules written in other Intel languages:
ASM-386, PUM-386 & C-386
• Highly optimized interrupt handling
-Fast execution of interrupt handlers wlthont requiring a
context switch
• Pre-emptive delay
-Force synchronization at the end of programmed
"delays"
• Optional download and debug paths using the VAX-hosted
Ada debugger
-With a ROM-resident target debug monitor (included).
or
-ICE-3B6 (80386 In-Circuit Emulator) for less intrusive
debugging
• Modular, configurable runtime system
, -Linker excludes routines not required by the embedded
application (no overhead penalty)
-Easily configured for dilTerent hardware environments
IlE"1. TI_
""a I'IlfIlfI INTEl.
Inters Ada development environment makes developing real·
time embedded applications convenient and easy. All steps
in the development process can proceed, start to finish.
from a VAX terminal-from initial unit testing with the VMS·
targeted compiler to compiling and linking using the 80386targeted cross compiler. Downloading to the 80386 target
and debugging can also be accomplished from the VAX
terminal.
tJfllfIPIldTIfIN P"CILtGB
tJfllfIPflNENTS
'8
• ......JlUel'8 A Ultrary .....
Both compilers. the VMS targeted version and the 80386
cross targeted version, use the same user interface,
commands and library management tools so the
programmer learns them only once. The cross compiler
has an optional switch which directs the complier to
produce assembly language text interspersed with Ada
source text as comments. This feature gives the
programmer a convenient way to hand-inspect the code.
The assembly language text can also be assembled using
the Intel 80386 Assembler.
The cross compiler has important optimizations to help
meet real-time needs. For example. when response times
to interrupts are critical. the programmer can speed up
response times by invoking the ·"function mapped"
optimization via a special compiler directive.
"pragma INTERRUPT.· This functi~n mapping enables an
Interrupt handler to execute without first requiring a task
switch. i.e.. within the context of the interrupted task.
• 5 ..... OJltblizer
The Global Optimizer is used to reduce the size and
increase the speed of embedded application code. This
tool is invoked at the user's option. but usually after most
of the coding and debugging is complete. Some key
functions performed by the Global Optimizer include:
dead code elimination
unused subprogram
deletion
common subexpression
elimination
constant folding and
propagation
static evaluation of
conditional
expressions
removes all unnecessary
code from the application
combines and substitutes
constants where
appropriate
reduces conditional
expressions to boolean
equivalents where
possible
• ....Iler
The Linker combines separately compiled Ada modules,
imported non-Ada modules (see Importer below), and the
Ada runtime system into one executable image. To reduce
.target code size. the Linker also eliminates' subprograms
in the application code and in the runtime system that
are not actually required by the application. The
programmer may also use the Linker to produce output
in, a format suitable for burning PROMs.
• ' ....rl.er
The Importer can help preserve previous software
investments. The Importer converts object modules from
Inters OMF·386 format to a format suitable for linking
with Ada modules. An Ada application can call these
imported non-Ada modules through "pragma
I),;TERFACE." Pragma INTF.RFACE is supported for Inters
ASM-3B6. PUM-386 and C-386 languages.
• Ada lIIuIU.e SY8te.
All the necessary low-level support routines for executing
programs on a bare 80386 microprocessor are provided
in the Ada Runtime System. These routines are
responsible for managing taSking, interrupts, the realtime clock and memory. Also included are predefined Ada
packages. such as Text_UO, IO_Exceptions.
Unchecked_Conversion and Calendar. The Ada Runtime
System is written almost entirely in Ada, with a small
number of packages written in 80386 assembly language
to support key low-level functions. The Runtime System is
easily conligured for dilTerent 80386 hardware
environments, and source code Is provided for this
purpose.
11-52
•
Symltoll~
Deltuuer
A Vr,X·residem symbolic debugger is supplied for each
compiler. The debugger allows the programmer to debug
at the s{)urce level while the code is executing on the
target. Log and script files may be used to automate
rt'fJ€titivf. debug ~C&~ions. Important debugger features
include:
Feature
Be.ent
machine lewl
interface
step through machine instructions;
read/write to registers. memory. and
110 ports
singleJmultiple
stell
step through source code hy single
or multillit' statements
hreRkpoints
IJalt execution at specified points
call chain display
display til(' dynamic nesting of a
program at a particular point in
time
task status
display
dt,termine the status of a task at a
particular point in time
variable display
examine values of program
varia hies
trap unhandled
exceptions
examine state of the target program
when an unhandled exception
occurs
• Lall8uaMe Tools
Inters Ada development environment includes tools that
help development projects run more smooth Iy. A Cross
Referencer provides a cross·reFercncc listing of all source
file locations where a user·defined symbol in an Ada
compilation unit is defined. A Source Dependency Lister
produces a valid compilation order list for compilation
units in an Ada program and lists dependencies among
units. A Source PormaUer (or ··pretty printer··) takes as
input a non· formatted Ada source file anrl outputs a
formatted version of the same text that adheres to
standardized language conventions.
1\ small dehllg monitor. supplied in PROM. is used with
the Symbolic Dehugger. The code can also be downloaded
and debugged using Intel·s IO;'3H6 in·circuit emulator'.
VAXNMS HOST
CODE
GENERATION
LANGUAGE
TOOLS
PROM
PROGRAMMER
GLOBAL
OPTIMIZER
nunJ~un~rSuEnRIJA~L~~
DEBUG
MONITOR
I
11-53
ICE-386
~EJ
WORLDWIDE SERJ'ICE liND SlJrPORT
Complete hardware and software support is provided. The Ada-386 Compilation Package comes with Intel's slamlarti
gO-day warranty plus an extended one-year maintenance agreement. ensuring nninterrupted support for a full 15 months.
One-year maintenance contract renewals arc available from Intel annually.
ORDERING INI'ORMIITION
Orller c:otIIe
VVSAda386- 75
·82
-A3
-8:'
·88
llesl (;eafl8uralloR
VAX 730. 750
VAX 78X. 8200
VAX 8300
VAX 8:iXX. 86XX. 87m
VAX 8800
M\I\ISAda31l6-VS
·02
VAXStationll
MicroVAXIl
ICE386HW
N/A
ProcIuCI
Ada-386 Cross-()mlpilation Package. Included are the following tools
hosted on VAXNMS:
• 80386-targeted Ada cross compiler & lihrary tools
• VMS self-targeted Ada compiler & library tmls
• For each compiler a Symbolic Dehugger. a (liohal Optimizer and
Language Tools
• Ada-3S6 Linker and Importer
• Ada-3S6 Runtime System
The Compilation Package also includes full dOfumentation. Intel's
standard gO-day warranty. and an extended one-year maintenance
mntract.
80386 In-Circuit "mulator (hardware only). Used with the VAX-hosted
Symbolic Debugger. the Im-386 orfers the programmer an altel'llative
download method to using the ROM-reSident debug kernel supplied with
the Compilation Package.
Note: Ada-3S6 software license required for each host CPU. Multiple copies require multiple licenses.
11-54
INTEL38fP' FAMILY DEVELOPMENT SUPPORT
COMPREHENsn'E DEVELOPMENT SIJPPORT FOR THE
INTEL:JB6'" FAMILI' OF MICROPROCESSORS
The perfect complement to the Inte1386'" Family of microprocessors is the optimum development
solution. From a single source, Intel, comes a complete, synergistic hardware and software
development toolset, delivering full ac<;ess to the power of the Intel386 architecture in a way that
only Intel can.
Intel development tools are easy to use, yet powerful. with contemporary user interface techniques
and productivity boosting features sllch as symbolic debugging. And YOII'll find Intel first to market
with the tools needed to start development, and with lasting product quality and comprehensive
support to keep development on-track.
If what interests you is getting the best product to market in as little time as possible, Intel is the
choice.
FEATIJRES
• Comprehensive support for the full 32 bit
Intel386 architecture, including protected
mude and 4 gigabyte physical memory
addressing
• Source line display and symbolics allow
debugging in the context of the original
program
• Architectural extensions in Intel high·level
languages provides for manipulating
hardware directly without assemhly langllage
routines
i~
• A common object code format (OMF-386)
supports the intermixing of modules written
in various languages
• ROM-able code is output directly from the
language tools, significantly reducing the
elTort necessary to integrate software into the
final target system
• Support for the 80387 numeric coprocessor
_________________________
Intel DJrporation assumes no responsibility for tile use of any dreullry oIJJer lIlan circuitry embodied In an InLel prodllct.
~~other
Cireuit pa1.CnL llrenses are
Implied. [nfonnatlon oontaJocd herein supersedes pI'C'o'IOusly published speeirlcations on these devices from Intel and Is sllbject r.o cnanee wiUJouL notice.
September, 1008
Order Number: 28OB08{101
© IIlIeI Corporation 1968
11-55
CR£AT!AND
COIIPLE
WITH
MAINTAN
UBRARIES WITH
W
i......
@
o
LINK MODULES
}-
TOGETHER WITH
~..L-_I~N?
""are •. Intel Microprocessor Development
~:nvironment
ASM-3B6 MACRO ASSEMBLER
ASM·386 is a ··high·level" macro assembler for the
Intcl386 Family. ASM·386 offers many features
normally lbund only in high·level languages. The macro
faCility in ASM·386 saves development time hy
allowing CAlmmon program sequences to be coded only
once. The assembly language is strongly typed.
performing extensive checkS on the usage of variables
and labels.
Other ASM·386 features include:
• "High·level" assembler mnemonics to simplil'y the
language
• Structures and records for data representation
• Upward compatibility with ASM·286
PI.IM-3B6 COMPILER
PL/M·386 is a structured high· level system
implementation language for the Intel386 Family.
PUM·386 supports the implementation of prol<'cted
operating system soFtwarc by providing built·in
procedures and variables to access the Intel386
architecture.
I'lj~I·:lfl(i comiJines Ih(' h{'nerits of a high·levt'l
languag!' Ilith Ihe ahility to a['('l'ss th{'lntl'i386
archit{'['tur{'. "'n' th{'. d{'wlopm{'nL of systl'lTIs softwan'.
PiJ\I·38G is a {'Ost-em','li\{' alt{'rnatiw to assl'mhlv
languagt' programming.
.
C-3B6 COMPILER
CnSlJ>jIlIY lor the used any drcuilry other than Circuitry embodied in an Intel product. No other circuit patent licenses arc
Implied. Inrormallon oontalfftt herein supersedes previously published specifications OIl these de\'1~ rrom Inl£1.
June. 1988
Order Number: 2807B6-002
htcl Caporal.lon 1988
e
11-61
FEATURES
MOST COMPLETE REAL-TIME
ANALI'SIS AVAILABLE TODAI'
FROM ROM-WADED TO OPERATING
SYSTEM WADED APPLICATIONS
iP.-\T Performance Analysis Tools use in-circuit probes
containing proprietary chip technology to achieve full
sampling in real-time non-intrusively,
The software analysis provided by iPAT watches absolute
execution addresses in-circuit in real timc. but also supports
use of variolls iPAT utilities to determine the load locations
for load-time located software. such as applications running
under iRMXII. DOS. Microsoft Windows*. or MS*-OS/2.
MEETS THE REAL-TIME DESIGNER'S
NEEDS
The iPAT products include support for interactions between
real-time software and hardware interrupts. real-time
operating systems. "idle" time. and full analysis of real·time
process control systems.
SPEED-TIlNING 1'0llR SOFTWARE
By examining iPAT histogram and tabular information about
procedure usage (including or not including their interaction
with other procedures. hardware. operating systems. or
interrupt service routines) for critical functions. the software
engineer can quickly pinpoint trouble spots. Armed with this
information. bottlenecks can be eliminatrd by means such
as changes to algorithms. recoding in assembler. or
adjusting system interrupt priorities. Finally. iP.,\T can be
used tn prove the acceptability of the developer's results.
EFFICIENCI' AND EFFECTIVENESS IN
TESTING
With iP.AT code execution coverage information. product
evaluation with test suites can be performed more
effectively and in less time. The evaluation team can quickly
pinpoint areas of code that are executed or not executed
under real-time conditions. By this means. the evaluation
team can substantially remove the "black box" aspect of
testing and assure 100% hits on the softwace under test.
Coverage information can be used to document testing at the
module. procedure. and line level. iP.AT utilitiPB alBa support
generation of instruction-level code coverage information.
ANALI'SIS WITH OR WITHOIlT
SI'MBOLICS
IlSE STANDAWNE OR WITH ICE
The iPAT-386. iPAT-286. and iPAT-86/88 prohes. together
with an iPATCORE system. provide standalone software
analysis independent of an ICE (in-circuit emulator) system.
The iPATCORE system and DOS-hosted software also can be
used together with ICE-386. ICE-286. ICE-186. and
PICE-86/88. 186/188. or 286 in-circuit emulators and DOShosted software. Under the latter scenario. the user CHn
examine prototype software characteristics in real-time on
one DOS host while another DOS host is used to supply
input or test conditions to the prototype through an ICE. It
also is possible to use an iPATCORE and PICE system with
integrated host software on a single Intel Series III or Series
IV development system. or on a DOS computer,
IlTILlTlES FOR 1'0llR NEEDS
Various utilities supplied with iPAT products support
generation of symbolic information from map files
associated with 3rd-party software tools. extended analysis
of iPAT code execution coverage analysis data. and
convenience in the working environment. For example.
symbolics can be generated for maps produced by most
software tools. instruction-level code execution information
can be produced. and iRMXII·format disks can be readl
written in DOS floppy drives to facilitate file transfer.
WORLDWIDE SERVICE AND SlJPPORT
All iPAT Performance Analysis Tool products are supported
hy Inlel's worldwide service and support. Total hardware
and software support is available. including a hotline
number when the need is there.
If your application is developed with "debug" symbolics
generated by Intel 8086. 80286. or 80386 assemblers and
compilers. iPAT can use them-automatically. Symbolic
names aIso can be defined within the iP.-\T environment. or
conversion tools supplied with the iP.,\T products can be
used to create symbolic information from virtually any
vendor's map files for R086. 80286. and 80386 software
tools.
REAL OR PROTECTED MODE
iP.,\T supports 80286 and 80386 protected mode symbolic
information generated by Intel 80286 and 80386 software
UJols. It can work with absolute addresses. as well as
base:offset or selector:offset references to partitions in the
prototype system's execution address space,
·"Inltso't \\ indl/I\$ and
Olrpr)ralion
~lS an' tradl'mar~s
II \liff'llS(il ulrpllratiun. IHM antil'Sf2 an' tradl'marls Ilf InLl'rnatlonal Husincs:-I
Ma('hln('~. II'A1: IGI-.:, i~MK 121r;~, iRMX II. Intd381l an.~ tTfl(jI~milrls tlllntd
[FEATURES
1
CONI'lGfJllATION til/IDE
For all·of the following application requirements. the iPAT system is supported with iPAT 2.0 (or greater) or iPAT/FICE 1.2
(or greater) host sortware. as footnoted.
Application Software
80386 Embedded
iRMK on 80386
iRMXII OS·Loaded or r.mbedded on 386
OS/2· Loaded on 386
iRMXII OS·Loaded or r.mbedded
80286 Embedded
Option
OS/2 OS-Loaded 80286
801861188 r.mbedded
DOS OS· Loaded 8086/88
8086188 Embedded
Host System
iPAT386DOS 1• iPATCORE
DOS
iPAT386DOS. iPATCORE
iPAT386DOS. iPATCORE
DOS
DOS
iPAT386DOS. iPATCORE
DOS
"1
#1
"2
"3
#4
#5
iPAT286DOS. iPATCORE
iPAT286DOS. iPATCORE
ICEPATKIT2
)2ICEPATKITJ
IIIPATD. iPATCORE3
IIIPATB. iPATCORE:l
[[[PATC. iPATCORE:3
DOS
DOS
DOS
DOS4
Series 1114
Series IV4
iPAT286DOS. iPATCORr.
DOS
iPAT286DOS. iPATCORE
ICEPATKIT2
)2ICEPATKITJ
IllPATD. iPATCORE3
IllPATB. iPATCORE3
IIIPATC. iPATCORE3
DOS
DOS
DOS
DOS4
Series 1114
Series IV4
iPAT88DOS. iPATCORE
DOS
DOS
DOS
DOS4
Series 1114
Series IV4
"6
DOS OS·Loaded 80286
iPAT Order Codes
"1
"1
"1
#1
#1
#1
#1
"2
"3
#4
#5
#1
#1
"2
"3
#4
#5
iPAT88DOS. iPATCORE
FICEPATKIT3
IIIPATD. iPATCOREa
lllPATB. iPATCOREa
lllPATC. iPATCORE3
DOS
Notes:
1. Operable standalone or with ICE·386 (separate product: separate host). iPAT·386 probe connects directly to prototype
system socket. or to optional 4' probe-to·socket hinge cable (order code TA386A). or to ICE·386 probe socket.
2. Requires ICE·I86 or ICE·286 in-circuit emulat.or system.
3. Requires FICE in-circuit emulator system.
4. Includes iPAT/PICE inte{:rated software (iPAT/PICE 1.2 or greater). which only supports sequential iPAT and ICE
operation on one host. rather than in parallel on two hosts (iPAT 2.0 or greater).
11-63
SPECIFICATIONS
'I
HOST COftlPIfTER REt)IfIREftlENTS
ELECTRICAL CONSIDERATIONS
All iPAT Performance Analysis Tool products are hosted on
IBM PC AT. PC XT. or PS/2 Model 80 personal computers. or
100% compatibles. and use a serial link for host·to·iPAT
communications. At least a PC AT class system is
recommended. Th.e DOS host system must meet the
following minimum requirements:
•. 640K Bytes of Memory
• 360K Byte or I.2M Byte floppy disk drive
• Fixed disk drive
• A serial port (COM 1 ur COM2) supporting 9600 baud'
data transfer
• DOS 3.0 or later
• IBM ur 100% cumpatible BIOS
The iPATCORE system power supply uses an AC power
source at 100V, 120V, 220V, or 240V over 47Hz to 63Hz. 2
amps (AC) at 100Vor 120V; 1 amp at 220V or 240V.
PHYSICAL DESCRIPTIONS
Unit
iP.4,TCORE:
Power Supply
iP.4,T·38B probe
iPAT·286 probe
iP.4,T·86 probe
iPATCABLJ<: (to
ICE:· 186/286)
IIIPATB.C,f)
(FICE board)
Serial cables PC
AT/XT PS/2
Width
Inches Cm.
8.25
4.5
11.0
1.3
2.8
2.B
13.75
11.0
4.0
6.0
6.0
35.0
28.0
10.1
15.3
15.3
4.0
10.2
.25
.6
36.0
91.4
12.0
30.5
30.5
.5
1.3
12.0
Operating Temperature:
Length
Inches, Cm.
1.75
4.25
0.50
1.12
1.12
3.0
4.0
4.0
ENJ'IRONftlENTAL SPECIFICATIONS
Operating Humidity:
Height
Inches Cm.
21.0
20.0
7.B
10.2
10.2
7.75
iPAT·386, iPAT·286 and iPAT·86/88 probes are externally
powered, impose no power demands on the user's prototype,
and can thus be used to analyr.e software activity through
power down and power up of a prototype system. For
ICE·386, ICE·286, ICE·186, and PICE microprocessor
probes. see the appropriate in·circuit emulator factsheets.
144.0 370.0
11-64
10°C to 40°C (50?F to
104 OF) ambient
Maximum of 85% relative
humidity, non·condensing
ICE-5100/452 In-CI.,()ult Emulator
IN-CIRCIJIT EINlJLA'I'OR I'OR THE lJPI'"-452 IilINILt 01'
PROGRAIfIIfIABLE 110 PROCESSORS
The ICE-5100/452 In-Circuit Emulator IS a complete harrJwar~J~onwar~ dehug l'nvironment for
developing embedded control applic,ations hased on the IntelliPIN-4fi2 family of I/O peripherals.
With high-performance full-speed emulation, symbolic dehugging, and fiexibk 1Ill'IIlOl'Y lIlapping, the
ICE-j 100/452 emulator expedites all stages of development: hardware devclu[JIlIl'IIt. softwarl'
development, system integration, and system test; shortrning yuur projl'ct's tim!' to ITwrkl't.
FEA'TlJRES
•
•
•
•
•
Full speed to the speed of the component.
64KB of emulation mapped memory_
254 frames of execution trace.
Symbolic debug.
Serial link to an IBM PC Xl AT, 100%
compatible.
• Four address breakpoints with in-range,
out-of-range, and page breaks.
• On-line disassembler and single line
assembler,
• Full emulatiun and debug support for the
Flm Buffer.
•
•
•
•
•
•
•
•
Sourl'~
code display.
ASM-51 and PUM-:; I language support.
Pop-up help.
DOS shell escape.
On-line tutorial.
Built-in CI<'I' ha~l'lll'ditol',
System sPif-tl'st diagnlJstil'~.
\\!(Jrldwicie Sl'rVICI' and SUPP0I't.
imJ-----------------------IOld (~'rr~'r I 0014">2 ('mulaLor's
singlt'·line assernhl!'r, \Iachine' md(' can 11(' disasSt'mllll'd to
mn!'lllonics Ihl' signifi('2 elllulator is supporl['d hy Intel's
wOl'ldwilll' St'rlil't' and SIlJlJlort organiwtion, In add iLion to
an l'xt(,l1(/ed lIal'ranty, you ('an elloOS(' fmm hOllim' support..
on·sitt' system ('ngim'('J'ing assistanc(', and a I'ariely of
hands-on training lIorksliops,
FLEXIBLE BREAlt.POINTlNG ,.'OR
f)IJICIt. PROBLEM ISOLATION
The ICE·;' 100/452 cmlilator sllpporLs tim't' diffm:nl t.ypes
of break specificaLiolls: spP{'ifi{' addn'Ss breaks Iln up 10
54,000 pllssihl(~ addn'sses; range hreaks, hoth within and
outSide a user-defined range; and page tweaks, up to 2~6
pages on 256·byte tlOunoaries. 254 i'rames of execution
trare memory provide ampll' debug informali(m, wit.h each
frame divided into 16 bits of program l'xtx'ut.ion address
and Hhit.s of external event inforIllHl.ion. A maximlllli of fOllr
trarepoints al/ows qU8lifil'd trace for a varieLy of (/ehug
conditions.
SYMBOLIC DEBIJGGlNG E'OR E'AST
IJEJ'ELOPMENT
Dt'sign team prlK/tH't.ivity is mlwnc('lilly till' USt' of
sYIlI!>olic 1I1'1l11g rl'l'('I'l'IlI'('S to progl'alll line. high·levd
stat!'IlI('nts, and llIodule and varia!>le nanll'S, The terills
llSl'lI to d['wlop pmgraills <11'1' thl' salll!' us(xl I()r syst('rn
IIdlugging.
11-66
ELECTRICAL CONSIDERATIONS
'I'IIP ('mulation processor's user-pin timings ami 10arlings are
identieal to the 4~2 component l'~cept as [ollo\\s:
• L'p to 2::; pF of addltHmal pin capacitance is l'lmtl'ihulril
IJ) tilt' processor morlull' and target adaptor assemhlir's.
PROCESSOR MOD(!LE DIMENSIONS
PIN'
f'lcu~
1: Processor \Iodulf DimenSions
SPECIFICATIONS
Hosl RequlrellleRrs:
Electrical Characterisllcs:
IB\I PC-'\l .~T or compatible
PC-DOS 3.0 or later
1'0\\('1' supply
100-120\1 or nO-240\ sel{'ctahle
:'0-50 Hz
2 amps (AC max) @ 120\
I amp ('\C max) @ 240V
5 12"
R~\I
One flopp) dl'ill' and hard disk
Physical Character/sties:
E""lro".,e"tal Characterisllcs:
Opl'rating temperature: + 10°C to + 40°C niOor to 104 OF)
The ICJ-:-SI 00/452 emulator consists of the folloll ing
components:
Uull
Contl'oll('1' Pori
L'srr Cable
Processor
\lodule*
PO\I(,I'Suppl)
Serial Cable
"1\ ith
Wldlh
Helpl
te-clh
10.:11 em lo.:h C:m ID.:h (;m
8.20 21.0 1.5
:lB 1:1.~
34.3
39.0
3.8
7.6
9.7
18.1
t.:i
4.0
3.8
10.2
Operating humidit): \la\imulII of !l:i'Yr, relative humidity.
non'Clmdensing
99.0
4.0
10.2
11.0 28.0
1.J.jO 360.0
supplied target adapter.
11-67
ORDERING INFORMATION
Order Code
Description
pl452KITAD
Kit oontains ICE-51001452 user probe
assembly_ power supply and cables.
serial cables. targft. adapter. crystal
power accessory. emulator controller
pod. emulator software. DOS host
communication cables. ASM-51 and
AEDIT text editor (requires software
license).
.
pl452KITD
Kit contains the same components as
p1452KITAD. excluding ASM-51 and the
AEDIT text editor (requires software
license).
pC452KITD
Conversion kit [or ICE-51001451.
ICE-51001252. or ICE-5100/044 running
PC-OOS 3.0 or later. to provide
emulation support ror 80C452
components (requires software license).
TA452E
Target adapter [or 68-pin PLCC package
support.
D86ASM51
ASMIRL 51 package for PC-DOS
(requires software license).
D86PLM51
PIJMJRL 51 package for PC-DOS
(requires software license).
D86EDlNL
AEDIT text editor ror PC-DOS.
For direct information on Intel·s Development Tools. or for
the number of your nearest sales omce or distributor. call
8(J().874-6835 (U.S.). For inrormation or literature on
. additional Intel produCts. call8O(),548-4725 (U.S. and
Canada).
MCS is a registered trademark and ICE is a trademark of
Intel Corporation.
IBM and PCfAT are registered trademarks and PGlXT a
trademark or International Business Machines Corporation.
11-68
I~ETII-51
00/044
ID-~ir~uit
ElDulator
IN..CIIlfJIJII'EMIJ"A.I'OR FOR I'HE RIJPI"'-44 I'A.MI"" OF
PERIPHERA."S
Tht' leR·51 001044 In·Clrcuit Emulator is a complete har!lwarrJsol'I,ware rtehug environment for
developing embedded control applicatiuns uascd un the Intel RLJPI'"·44 family of peripherals.
Including the 8044·based IIITIIUS'" board products. With high·perfurmance 12 Mllz emulation.
symbolic debugging. and fiexible memory mapping. the IC«;·5100/044 emulator expedites all stages
of development: hardware development. soi'tware development. system intt'{lration. and system test:
shortening your projeCt's time to market.
I'EA.I'IJRES
Full speed to 12 MHz.
64KB of emulation mapped memory.
254 frames uf execution trace.
Symbolic debug.
Serial link to an IBM PC XT. AT. 100%
compatible.
• Four address breakpoints with in·range.
out -of· range. and page hreaks.
• On·line disassembler and single line
assembler.
•
•
•
•
•
•
•
•
•
•
•
•
•
Source cude display.
ASM·51 and PIJM·~ I language support.
Pop·up help.
DOS shell escape.
On·line tutorial.
Ruilt·in CRT based editor.
System self·test diagnostics.
Worldwide service and support.
imJ-------------------Intrl fllI'pnralllln i1s:.uml'll nil n'Spom!1btlil~ fur 11K' uS(' III a~ rJrrUIU~ ntB.'r than rlrrultr) !'mblldic'l1 in Cln Irtl'lllMlIlUI'1 Nlllltht'r rlrrUI! pall'n! 1I"'n:\l':O llI'j'
Implil>O. InIurmalmn ('umaill{'d ht'l'rln I>Upl'rl'l.'fX't'\ pn"l iml:\l~ pUhli:;htod S,n"irltilliorL'i lin tlU'l'!t' dt"wln'll rrum Irt4.'l (lfld I~ suh~'t't In ('t)'ln!;'t' ",lIhuul nulln',
,
St'plt'mbc'r, 19M
© lr1ll'l CII..pllral.iUR 19M
Ol'dl'r -'umht'r: 2H08IIH)OI
11-69
ONE TOOL FOR ENTIRE
DEJ'EWPMENT CYCLE
SYMBOl.lC DEBIJGGING FOR I'It.ST
.DI?J'ElOPItIENT
The ICE-51 00/044 emulator speeds target system
development by allowing hardware and software design to
proCl'('d simultanl~lusl~_ You can d(wlop software ('VI'n
before p['()totypl' hardware is finished. Ann hl'cause thl'
IC~;-!i 100/044 emulator pl1'cisl'iy matches till' component's
l'il'l'lri('al and timing chal'ill'lrristil's. it's a valuahif' tool for
hardwarl' (iI'Vf'lopml'llt and dehug. Thus, the IC~:·:; 100/044
emulator ran debug a prototypl' or proliuction sySU'nI at
any.slilgl' in its d(wiopml'nt. without introfiueing l'xtram'OIlS
liil{'dw:ll'l' III' softwarc tl'sl tools,
Design team productivity is l'llhanc('cI hy the USi' of
symholic dl'hug J't'f('J'I'ncl's to pJ'ogrilm lim', high·lewl
stal.em('nts. and moduli' aOiI variahl(' names. The tl'rms
uSI'd to develop programs i1l'l' till' saml' uSl'd fUI' sysh'J11
dl'llugging.
HIGH-SPEI;D, REAl-TIME EMlJllt.TION
Till' lel,;-;, I ()0/044 I'flIulalol' p[,()lidl's fllll-"JWt'd. I'I'iIHil111'
('{llUtalio{) lip to 12 ~lIlz. Ill-calise till' l'flIulatol' is fully
tr,lJlsparl'lll tothc tal'gl'l system. you haw compll't(' control
OWl' Il!lrcJII!lJ'1' and softwa['(' debug and syst('1ll intl'gratio[).
(i4f..11 (If zero wait-stah' ('Illulation memory is mailabl(' to
n'plm'e Wrget system colie Im'mory, allowing software
dl'llug W Iwgin I'v('n I)('forl' prototYJl(' hardware is finished.
I'l.EXIBlE BREA"POINTING FOR
(lIJIC" PROBLEItI ISOlATION
Thl' IC:~;-!i 100/044 emulator supports three diffen'nt types
of break specifications: speCific address breaks on up to
64,OOD possibl(~ addressl's; J'ange breuml'S no f('spHnslhllll~ [lit' (hI' us(' of an} Clrrutlr~ ulllt'f than drrultf) t'mhoKlIl'd In itO Intl'lllfllllun. Nu ulht'j" fiN U111hl!t'nt Iln'ns('l\
&'lllt'mlM.'r.l!lKfl
IINli'r Numher: 2H1179H'(XJ2
© Intel Curporaliol\ 19HH
11-73
ONE mOL FOR ENTIRE
DEJlEUJPttlEN'I' Ct'CLE
The ICE·5100/252 emulator speeds Iilrget system
development by allowing hardware and software design to
proceed simultaneously. You can develop software even
hefore prototype hardware is finished. And because the
ICE·51001252 emulator precisely matches the component"s
electrir,al and timing characteristics. it's a valuable tool for
hardware development and debug. Thus. the ICE·51001252
emulator mn debug a prototype or production system at
any stage in its development. without introducing extraneous
hardware or software test tools.
HIGH-SPEED, REAL-TIttlE EttlIJLA'I'ION
The ICE·5100/252 emulator provides full·speed. rt'r 2R()721-004
e 11M(! Q)rporauon 1988
11-84
TRAt:E BIlFFER
STANDA£ONE OPERATION
The ICr:-196KB/PC mntains a 2K (2048) entl'Y trace buffer
for keeping a history of actual instruction execution_ The
trace buffer can be conditionally turnt'd off to coliI'd H userspecified number of trace frames_ Trace information can be
displayed as disassembled instructions or, optionally,
disas..<;embled instructions and the original C-96 and
PLiM-li6 source code,
Product softwal'e can be developed prior to hardwaJ't:
availability with the optional Crystal Power Accessory (CP.")
and the ICE-l 96KBlI'C mappahle memory, The CI'" also
jlJ'()vides diagnostic te,~ting In as..~ure full functionality of the
BREAK SPEt:IFIt:ATlON
Three execution address hJ't~akpoints or one range of
addr('!;ses can hl' aClivt' at any time, Tilt' ICr:-196PC allows
any number of hreakpoints to bt' defint'd and aC'livated wht'll
1lf~'dl~1.
SI'ItIBO£It: SlfPPOIlT AND SIIlfReE
t:ODE DISPMI'
Full "SM-!lti, 1'11\1-96 and C-96 IHnguagl' symholil's,
ineluding variahle typing and S('opt', art' support(~j hy th('
ICIo:-1 !)lil\B/l'C m('mory H('(,f'SSt'S, traCt' hum'r display,
1)I,'all~linl spI'I'ifi('ation, and ass('llIhl('r/diSiISS('rnhlt'r_
.·\dditionally, C-mi allli I'IJ~H16 Sllllr('f' [,(KII' ('an hI'
IlisplaYl'd to llIalt' d('Il'lopllll'nl and ddmg msi('I',
ICI~-196KIlII)C.
J'ERSATILE AND POWERFlf£ HOST
SOFl'WARE
The IC~;'196KB/PC comes equipped with an on-line help
facility, a dynamic command entry and syntax guide. builtin editor, assemhler and disassembler, and the ability to
('uslHlnize lh(~ command St't via lilt~ral definitions and dt'hug
pl'Oc('duJ't's,
-
HOSTING
The IC~:-lf)61\BII'C is husted un the IBM PC X'I: ,\'1' ur
mmpalihlt's with PC-DOS :l.Il 01' later,
SPECIFICATIONS
REl)lflREMENTS
Host
IBM PC XI: AT (or (x)mpatihle)
5121\ hytt's RAM, Hard Disk
PC-DOS 3,0 or Later
Om' lInIlS(~dl'("'iphel'al Slot
DC Currt'nt 2,:'A
ICr:-196t.:1~/I'C 2 Bytl\~ of lISt'r Sta(,k Spac(,
TARGET INTERFAt:E BOARD
I.~ngth
Ileight
Width
2,0" (:'_lcm)
1,2" (:I_O('IlI)
2.3" (fiJlt'm)
ORDERING INFORMATION
Onle,. CfHle
IJescrl,,".B
r:mulation Iloanl. IIser mlll(', lfll'~~t inWI'[an'
IKlaJ'd (pl.eC), host, diHgnostit', and tutorial
I.ength I fi'(i" (3fHkm)
SO[tWall' on
DOS diskeUt'., 111111 Crystal
Powel' At-c('s..~OI'Y with Iltlwel' mlll('
PROBE ELEt:TRIt:A£
ICr: If)lil\BI'CB
San](' as aIKIV(' eX('('llt (Ioes not indlltl('
Crystal I'owel' A(ws.~oI'Y
50pf luwling
HOC I 961\B 1)lus lit'" pin
'Ii\ If)lipl.(XAillpGA liH pin p(;A lIlI'lWt adallll'l'
5ns JlllIpugHtion delHY
CI~-\ J!)lil\At.:B
Crystal Powel' Am~s..'i{II'Y ami P0w\'I' mhle only
50mA @ 12 Mill.
In' (frum tarlwt systt'm)
(~O(i Olillpilel'*
3,5 to 12 Mill., 12 Mllz only IlHBC[)(iNI.
Operaling f'retjllmt'Y
IlHlipl.MOliNI.
I'IJM-Oli (~lIl1pilt'I'*
with CI'A
IlHBASMfllil\ I.
ASM-f)(i Assemhlel'*
I(:r: IflHI\BI'C
lfSER t:ABLE
"V."
ENJ'IRONItlENTA£ t:HARAt:TERISTIt:S
OIK~I'ating
lIumidity
IOOG to ,10°C
:175°1,' ttl 104°1"
Ma,\imum fir, % J.1datiVt'
Ilumitlil,Y, nun-coudensing
*lndu(lt~s: J.1d(It~ltor/l.inker, Ohj(xt-to-Iwx CtlllVt'rtt'l~ Floating
Point Al'ithlll(tic I.ihrary, l,ihl'1lrian
Note: lel':- J!)lil\B/I'C USt'S two hytes of Ihl' IISt'I' starl,
11-85
[}ll[gJ~IUIli£jj~[N]ffi\IJ2dW
I (; E TM_ 1 9 .. K B /
x X I N - (; I R (; U I T EMU .. AT 0 R S
MODlILAR IN-CIRClIIT EMlILAf'fJRS FOR THE BxCI96lt.B FAMILY
OFMICROCONTROJ,LERS
The ICt<;"-196KB/\!X and IC/<:-196KBII1X in-circuit emulators deliver a complete, real-tim~, hardwm'eJ
software debug environment tor developing, inleilrating, and testing 8xC WoKR-bused designs. The
ICF:-196KB/MX emulator is a mid-range modular debugging sysLem featuring high performance 12
~IHz emulation, high-level symbolic debugging, 64k bytes zero-waitstate mappable memory, ami
emulation trace_ ICE-196KBIHX emulator is a high-end syst.em wit.h all the functionality of
ICE-196KB/MX plus additional breakltracc capabilities and expanded mappable memory, The
ICE-196KB/MX emulator can be upgraded to an ICE-196KB/HX emulator with optional add,in boards.
Both syst.ems feature an identical human interface, utilize the sHine haSt' chassis, and are serially
hosted on IBM* PC XTs and A'I's, and 100% compatibles.
ICE-196lt.BlxX IN-CIRClIl'I' EMlILAf'fJRS CORE FEA'I'lIRES
• Predsely malches the component's
electrical and tillling characteristics
• Supports the ROM less and (EP)ROM versions
or thl' 8xCHJ6KR
• Does not introduce extraneous hardware or
software O\'erhead
• ~Iodular base for future groMh and
migration
infel'--------·IBM Is a It',gistP.tOO Itoof'mark of [nt{'rnatiolllli Ruslness Machllle'S
[lllel Corpuralion aSSlimrs no rcsponsibilit~ ror till' usc of ally drcuitry (t,/)P.r than r.irruilry I'mhodk'l.i in an IOld proc1urt. ~() other circuit patt:nt licenses are
implied. Inrormalion cont.aillffi herein supersedes prcviously published specificaUons on these dL·... jr~ from Inld and Is suhjlll:l tv chan~ 'Nil1lOut nutlce
Octoher, 19R8
© Inlel Corporalion 19RB
Order Number: 28004HlOl
11-86
I
ICETII-'96IlBIMX IN-t:IRCIJIT
EMIJM'l'tJR FEA'I'IJRES
• Real·time transparent emulation of the 8xC196KB
mieroeontroller family up to 12 MHz. including ROM and
EPROM versions
• 64k byte~ uf zeru-wai~tate mappable mp,mory to allow
early software debug and (EP)ROM simulation.
expandable to 128k bytes
o 64k hardware executiun breakpoints •
• Symbolic debugging and source code display for faster
and easier access to memory location and program
variables
• 2k frame trace buffer displaying e,xecution address
• Multi·ICE synchronization to start and stop multiple
emulators in multi·processor designs
• Run·time viewable e,xecution trace
• Watch winduw feature autumatically displays variables
when breaking emulation
• Serially·hosted (RS232C) with vcry high·speed download
capability
• ONCE'" ~uppurt for on-clrcult emulation of ~urface-JIIount
target systems
• Trigger out for synchronization with external logic
analyzer or scope
• capable of suspension mounting for remote debug
• Full language support with ASM-96. PI JM-96. and C-90
• On·line di~ssembler and single-line assembler
• Context·sensitive drop-down "help" window to speed
development
• On-line tutorial
• Self·test diagnostics to ensure system integrity
• World·wide service and support
ICE ....-'96IlBIHX IN-t:IIlCIJIT
EMIJM'l'tJR FEA'I'IJRES
Includes all features In IC"'''"·196KB/MX emulator
plus fhe follow/DR:
• Additional cumplex event recognizers for bus break/trace
to allow debugging on data values, events. or addres~es
• DynamiC trace allows user to view trace buffer Without
stopping emulation
•
•
•
•
•
•
•
•
•
Fa~tbreak~ to allow the user to access program variables
and SFRs during emulation
Additional fi4k hytl'~ of zero·waitstate mapped memory
(12Bk bytes total)
Emulation timer and event timer for debugging speed·
critical applicntion~ and to allow performance analysis
capabilitit'S
Conditionaltl'. hyl('s
trace memory, and single-step program execution art' stlmilaril on t hi' ICr:- I fll) l'mulalo)', Inl('1
provides a complete development environment using assl'mhl(')' (:\S~IIIl)) aH weI! UH high-il'Il'l
languag~s such as lntd's iC86, PUM86, Pascal 86 and Fortran fl() to at,:l'il'I'all' ill'\l'lopnlt'nt
schedules,
Thl' ICE-186 emulator supports a subset of the ROC 1SCI fl'alun's at 12,;; \11170 anil at till' '1"1'1. lel'pl
characteristics of the component. The cmulatm is hosted on lB~rs l'l'l-:;onal Computl'l' II: alread~
al'ailable as a standard development solution in most of tllllay's (')1gimwing 1'llIironnll'nts, The
leR-186 emulator operates in prototype or standalonp mlKll'. a1101\ ing soft\\an' 1li'\plopnll'lil and
debug before a prototype system is available, Thl' Iq:-llIl) 1'111111<1101' i~ idmll; suitl~1 [01' ilt'll'Ioping
real-lime applications such as industrial autolTlation, (,()lTIlllilPI' pl'l'iplll'rals, COl1lmllllirations, officI'
automation, or othcl' applicatiol1s requiring thl' full pow~'r of thl' 12,~ \11170 HOC IHH l1liCl1IPI'Ol~'SSOI',
ICETM-I B6 FEATIJRES
• Full 12,5 \IHz Emulation Speed
• 21\ Frames Dl'ep Trace Memory
• Two-Lcvcl Breakpoints with Occurrenct'
Counters
• Single-Step capahilit~
• 1281\ Bytes Zcro \\'ait,Stale Mapped \Iemory
• Supports DR:\\l Re[resh
• High-Le\'el Language SUPIJOrt
i~
• Symliolic lli'liug
• RS-ZI2-C I'n'\hlu:-I~ I,ulllrslk'c! sl~'rirll';nIlUls 11!I11""~1' d,,\iI1,,, !tllm 11111'1 011111 IS s,lh~"1 tn d1.l1l/.!!' '-111111111 IiI~h1'
~, Intl'll~lrl~lra"II'l
~'IIII'llIIM·r. IlIHH
:!Jln"j21i~lm
l!IHH
111'01"1 \umln
11-90
HIGHEST EMfJLATlON SPEED
AJ'AILABLE TODAI'
fJSER-FRIENDLI' SI'MBOLICS AID IN
DEBfJG
The ICE-186 emulator supports development and debug of
time-critical hardware and software using Intel's 12.5 Mllz
ROC 1R6 microprocessor_
Symbolics allow access to program symbols by name rather
than cumhersome physical addresses. Symbolic debug
speeds the debugging process by reducing reliance on
memory maps. In a dynamic development process, user
variables can be used as parameters for Im-186 commands
resulting in a consistent debug environment.
RETRACE SOFTWARE TRACKS
This emulator captures up to 2.048 frames of processor
actil'ity_ including both execution and data bus activity. With
this trace memory_ large blocks of program code can be
traced in real time Hlill vicwed for program flow and
behavior characteristics_
HARDWARE BREAKPOINTS FOR
COMPLEX DEBfJG
User-derined "TII,-'I'HI<:N" breakpoint statements stop
emulation at speciric execution addresses or bus events.
During the hardware and software integration phase_
hreakpoint statements can be deriDed as execution
addresses and/or bus addresses and/or bus access types
such as memory and I/O reads or writes. Additionally, event
counters provide another level of breakpoint control for
sophisticated state machine constructs used to specify
emulation breakpointsltracepoints.
SMALL OR LARGE STEPS
;\ stepping command can bc used to view program
eXf(,lItion one instruction at a time or in preset instruction
blocks_ When used in conjunction with symbolic debug, code
execution can Iw monitored quickly and precisely.
DEBfJG CODE WITHOfJT A PROTOTI'PE
Even before prototype hardware is availahle, the ICE-186
emulator working in conjunction with the Crystal Power
Accessory (CPA) creates a "virtual" application environmmt.
128K bytes of zero wait-state memory is available for
mapped memory and 110 resource addressing in 4K
increments. The CPA provides er,Ilulator diagnostics as well
as the ability to usc the emulator without a prototype.
DON'T LOSE MEMORI'
The ICE-186 emulator continues DRAM refresh signals even
when emulation has been halted, thus ensuring DRAM
memory will not be lost. During interrogation mode the
ICE-186 emulator will keep the timers functioning and
correctly respond to interrupts in real-tiIllP_
SfJPPORTS FAST BREAKS
"Fastbreaks" is a feature which allows the emulatiun
processor to halt, access memory, and return to emulation
as quickly as possible, i\ fastlll'eak never takes more lIlan
5625 clock cycles (most types of fastbreaks arc
considerably less). This feature is particularly useful in
embedded applications.
MfJLTIPLE HIGH-SP':ED
COMMfJNICATlON LINKS
Two communication links are availahle for use in
conjunction with the host IBM PC AT. The ICE-186 emulator
uses either serial (RS-232-C) or a parallel (GPIB) link. A user
supplied Nationallnstruml'llts (IEI<:E-488) GPIB
communication board pmvides parallel transfers at rates up
to 300K bytes per second_
SOFTWARE ANALI'SIS (iPAT)
Intel's Performance Analysis Tool (il~\T) is designed to
incre2se team productivity with [eatur('S like interrupt
latency measurrm('Jlt, code covrraw analysis and software
modo Ie pl'rformance analysis. These fealurl'S enable the
user to dl'sign reliable, high performance embedded contml
products_ The IC~;'I H6 l'mulator has an external 60 pin
connector for iP,\T.
BllILT-IN SfJPPORT FOR LOGIC
ANALI'SIS
General-purpose logic analyzers can be used in conjunction
with the ICE-ISG to pl'OIitil'.tietaih'd timing of spccit'ic
events. The ICE-186 emulator provides an external sync
signal for triggering logi(' analysis, making complex trigger
seqUl'nCl' programming easy. :\n additional 60 pin connector
is included fill' thl' logic analyzl'r.
WORLDWIDE SERJ'lCE AND SfJPPORT
HIGH LEJ'EL LANGfJAGE SfJPPOR'I'
OPTIMIZED FOR INTEL TOOLS
The ICE-IBG l'mulator is supported by Intel's worldwide
servin' ami support organization. Total hardware and
software support is availahll' including a hotline number
when the nl'l~1 is there_
The ICF:-186 supports emulation for programs written in
Intel'S ASM86 or any of Intel's high-level languages:
['iote: This emulator dOl'S not support use of the 8087.
PUM-86
Pascal-86
Fortran-86
C-86
These languages are optimized for the Intel HOIHG180188
component architcctures to deliver a tightly integrated, high
performance development environment.
11-91
SPECIFICATIONS
PERSONAL COMPIJTER
REt)IJIREMENTS
ELECTRICAL CONSIDERA'I'IONS
The IC~·186 emulator i, hosted on an IBM PC .-\T. The
emulator has heen tt'Sted and elaluated on an IBM PC AT.
The PC :\T ITIllslllWel the folio\\'ill~ minimum requirements:
• 640l\ Byles of \Iemory
• Intel .\bole Iloard Ilith al Least I M Il~lt' of ~xpansion
1<'1' ImOm"
70w\ ~Iax,
111, - J 5m'\ ~Ia\
1,," - 1.0111:\ ~Ia,\,
1111
TIMING CONSIDERATIONS
~Iemor~
One 360l\ [J~ Ie, or One 1.2\1 Bytes floppy Disk Drive
One 20\1 Bytes Fixed·Disk Dril·e
PC DOS 3,2 or Lat!'r
.\ serial Port (CO~I J or C()~12) Supportin~ \1inimaliy al
9600 Baud Data Transfers. or a :-;ational Instruments
GPIIHC2.\ boaI'll.
• IB~I PC .\T BIOS
•
•
•
•
,'iPfiC
.
l)at,1 in ~'(lJP
11111)
IC~·186 ~mulat{)1'
""-.
ilia",.
\S\IlI' ~('wl\
11~1l\)
,
Kc'solutloll
Transit inll S!'tlJlI
'l'inll'
PHYSICAL DESCRIP'I'ION AND
CHARACTERIS'I'ICS
The
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snc
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L-,
:-i\lll'hnJrillll:-:
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(~lIlslllll
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.. \!,plil's tll1l~ "hl'l1lhl' \I.E\11111E \ilrinhh' 1:-; :-;1'1 to ST-\t.:T.
n \ppJIt'S IInl~ \\he'll Ihl' \I.E\I(JIW \.
11-92
:!i
ENI'IIlONMENf',tL SrECII'IC,tf'lONS
I
T.
T1
I
h
I
n
I
yt
I
Operating Temperature 10 0 e to 40°C Ambient
StorHge Temperature - 400C to 700C
OIlDEIlINGINI'OIlM,tf'ION
ICEl86
ICE-186 System including ICE software
DOS 3.XX PC AT with Above
Board)
(R~luires
ICE 186AB
ICE18611'AT
ICE 186 with Above Board included
ICE-186 System including ICE SIW
packages and the iPAT system (Requires
OOS 3.XX PC AT with Above Board)
D86ASM86NL
86 macro assembler 86 builderlbinderl
mapper utilities for OOS 3.XX.
D86C86NI.
116 C compiler and run time libraries for
DOS 3.XX.
D86P.AS86NL
86 Pascal Compiler fur DOS 3.XX.
D86PI.M86NL
86 PUM compiler for DOS 3.XX.
D86fOR86NL
86 I"ortran compiler for OOS 3.XX.
ICEPAT KIT
iPAT Kit (performance Analysis T(xll) fol'
ICE 186
ICRXONeE
Adapter for on-circuit emulation
ICEXLCC
Adapter fur LCe component
ICEXPGA
Adapter for PGA component
11-93
HIGH PEIlI'OIlIfI.4NCE IlE,41.-TIIflE EIfIIJ£.4TION
Inters ICE·188 emulator delivers real-tiine emulation for the 80C188 miCl'llprlK'l'ssorat Spl'l'US up to
12.5 ~IHz. The in·circuit emulator is a versatile and efficient tlXJI for dlwlolling, ul'IlUgging and
testing products designed with the Intel 80C 188 microp[,(ffSsor. Thl' IC~:·188 l'mulatlJr provides real
time, full spccd emulation in a user's system. Popular feutul'l'S such as symbolil' ul'hug, 21\ by\('s
trace memory, and single-step p['()gram execution are standard on thl' IC~:·188 I'llIulator. Intl'l
II[,(J\ iues a complete dcvclopment environment using assembler (I\SI\I86) m; \wll as higlHl'wl
languages such as Intel's iC86, PLlM86. Pascal S6 and Fortran S6 to aln'll'ratl' d('wlollml'nt
schedules.
The ICE·1SS emulator supports a subset of the SOC 188 fl'utul'l'S at 12.5 ~lIlz and at thl' TTl, I~vel
characteristics of the component. The emulatlJr is hosted on IBM's Personal Computl'r :\1 all'l'ady
a\'ailable as a standard development solution in most uf tlJday's l'ngim\'ring 1'l1\ilUTllll('ntK Thl'
ICE·IBB emulator operates in prototype or standalone modI'. allowing softwal'l' dewlopment and
debug before a prototype system is available. l'he ICE·188 l'mulatol' is illl'ally suiu'd for d~\,l'loping
real-time applications such as industrial automation, computer IIt'riphemls. mmmuniraUons, office
automation. or other applications requiring the full pow!'r of the 12.5 ~1I1~ Il(K: I RR mi('roprul'l'SSlJr.
ICE"'·'BB FE.4TIJIlES
• Full 12.5 ~IHz Emulation Speed
• 2K Frames Deep Trace Memory
• Two·Level Breakpoints with Occurrence
Counters
• Single·Step Capability
.
• 12BK Bytes Zero Walt·State \Iapped Memory
• Supports OKAM Kefresh
• High·Level Language Support
Symb~JIi(' Debug
RS·232·C and GPIIl Communil'lltion I,inks
Crystal PO\\\'I" i'll'l'l'ssory
Intl'rfact' for Inll'l I't'rformmll\' :\nalvsis TIXJI
(iPAT)
•
• Intl'rface for Optional GI'm'rall'urplJsc IAJgic
'\nalvZl'I'
• Tutlli-ial Sortwart'
• Complclt' Inu'l Srrvict' ani! SnPIIlJrt.
•
•
•
•
imJ----~-----------------10\1'1 (~lqKlriHilin ilSSUITI'~ nu rt'SJJllllslhllll~ fur Iht' 1!SI'ul' II~ "ITI'Ullr~ '1I.1ll'r lhan nr"ullr) l'mtIlMllt~lln ,UI Inll'II",.1I1I1. \II,lI.h,'r Iln'\l1I1~11I'11I. III'I'IIN'S .ITt'
1n111l1t~l.lnf',rnl :-'lIhl'~·IIIl'·hillij.~· '4IIIMIlR I\ulll,'
~
:-;"I'II'IIII.'I".IIIIUI
II,d,'r \nmh'T ~H&lKlli 11111
lit,·; 4;ur,_tralll,n 19HH
11-94
IIIGIIEST EMIlLATlON t.,PEED
A"AILAIIU'TOIMI'
IlSER-FIIIENDLI' SI'MBO£lCS AID IN
DEBIlG
The ICE·18B emulator supports develupment and dl'bug uf
lifTIf-Critical hardware and softwa['(' using Imel's 12." MHz
1l0C 1118 mic['()p['()cessor.
Symbolics allow acc~ss to pl'Ogralll symbols by naml' ratlll'r
than cllmtlt,rSollll' physical addn'ssl's. Symbolil' ddlllg
speeds th.. dt'bugging Pl'llct'ss by rc~lul'illg rt'iiallt'l' on
Illl'mory maIlS. In it tlynamil' til'\l'loplll('nl pron'ss, uSl'r
I'ariabl!'s mn bl' uSI~1 as param!'ll'rs iiII' I(XIHH t"Ollullantis
n'slilling in it I'OlisisU'nt tiebug I'm·ironment.
RETRACE SOFl'WARE TRACN.'"
This I'mulator captu['('s up tu 2,048 frallll's of Jl[,()I'I'S.~or
m:tivity, including 1~lth executiun and data hus ('\11(1
\\11
II'I';S'I'
The ICE·18B Emulator conSists o[ the following components:
Emulator
Control l nil
PIJV,t'f SlJPpl~
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t'I'IBII
list'1' pl'(Illt'lo t'OtI\('I'1 ICE·IIIlllo Sllpp"rt
BOCIBB ('(Ill1lltlllt'lll
11-97
IN-€IIltJIJI'I' BMIJI"tlYJIlIYJIl 'l'HB BOBfilBO I BfiIBOZBfiFAMI£t'
01' MIQlOPIlOt:BSSORS
The FICE- In·Circuit Emulator is a high·performanoe. cost-effective debug environment for
developing systems with the Intel 8086180186180286 family of microprocessors. With 10 MHz
emulation. a window-oriented user interfaoe. and compatibility with Intei's iPA1'"' Performanoe
Analysis Tool. the PICE Emulator gives you unmatched speed and control over all phases of
hardware/software debug.
FBA'I'IJIlBS
• Emulation speeds up to 10 MHz with
8086/88. 80186/188 and 80286
microprocessors
• 8087 and 80287 numeric coprocessor
support
• Hosted on IBM PC AT*. AT BIOS. or
compatibles
• ICEVlEW- window-oriented user interfaoe
with pull·down menus and context·sensitive
help
• Source and symbol display using all Intel
languages
i~
• 1K frame bus and execution traoe buffer
• Symbolic debugging for flexible access to
memory location and program variables
• Flexible breakpointing for quick problem
isolation
• Memory expandable to 288K with zero wait
states
• Worldwide servioe and support
• iPAT option for software speed tuning
______~_________________
121CE, ICEVIEW. Bnd i~T are lradcmarb II IIl\CI Col'JlDl'oIIllon.
"IBM IS a trademark II lrt.emaLional Business Machines cOrp.
In.Li CorporaUon assU/OOi no m!plInsiblllly for UK! If£ II an)' CII'C\lIU')' llLhcr Lhan t'lftUllly embodied in 8n IrlCl pruduct. No lllhcr circuli. patelll.lmscs are
lmplkld. InformatIOn curtained herein IIUJ)CfSlXIes Ilf'CYlOUSly publl8tJcd Ilpeclfica~~ nR these dcYlalS fr.1I1l11'lC1 and IK suhllrL 10 changr. wlthlu nWec.
JIlIY.I988
OrGer rtlmber: 2808()O.OO1
@htelOJrporatjoo 1988
11-98
Plate t. An example of the ICIWIEW'" user interface showing source.
memory. watch. and trace.
ONE TOOL FOR THE ENTIRE
DEJlELOPMENT PROCESS
St'MBOLIC DEBllG SPEEDS
DEJlELOPMENT
The 12 1CE Emulater allows hardware and software design to
proceed simultaneously. SC you can develop sofLware even
betbre prototype hardware is available. With 32K of zero
wait-state mappable memory (and an additional 256K with
optional memory boards). you can use t.he FICE Emulator to
dehug at any stage of the development cycle: hardware
development. software development. system integration or
system test.
The extensive debug symbolics generated by the Intel 8086
and 80285 assemblers and compilers can increase your
development productivity. Symbolics with allWmatic
formatting are available for all primitive types. regardless of
whether the variables arc globals. locals (stack'resident) 01'
pointers. The virtual symbol table supports all symbolies.
even in very large programs. Aliasing can be used to reduce
keystrokes and save time.
HIGH-SPEED, REAL-'I'IME EMllLA'I'ION
POWERFllL BREAK AND TRACE
CAPABILlTt' FOR FAST PROBLEM
ISOLATION
The 121CP. f:mulator delivers full-speed. real-time emulation
at spt'.:ds up to 10 MHz. Based on Intel's exclusive
microprocessor technology. the 12ICE Emulator matches
(,8eh chip's electrical and timing characteristics without
memory or interrupt intrusions. ensuring design 3cfuracy
and t'liminating surprises. Tht' performance of your
prott~ype is the performance you can expect from your nnal
prtKilKt.
EASt'-TO-llSE ICEJlIEW'" INTERFACE
The ICEVIr:W interface makes the 12ICE Emulator easy to
learn and use hy providing l'8SY access to applieation
information and ICI': functions. Pull·down menus and
window~ boost productivity for hoth new and cxpef'it'm~'d
USl'r~. Multiple on·scl't~'n wintiows allow you to access the
Sl)urce display. execution trace. register. and other
imporUmt information. all at the same time. You ran wau:h
the information change as you modify and step through your
program. You !:an even custtlmizc wilillow siw and screen
positi~)Ils.
The 121CE Emulator allows up to eight simultaneous bl't'akJ
trace condition~ ttl be set (four execution. fOllr hus). a
timesaver whtm solving hardwart'isoftware integration
problems. Break and trace points can be ~et 011 speciFied
line numbers. on procedurt's, 01' on symholic data ewnts.
such as writing a vllI'iahle to a value or rangl' of values. You
('an hreak or traL~' on specific hardware cvmts. such as 11
read or write to a specific address. data or 1/0 port. or on a
comhination of events.
ltJllLTIPROCESSOR, PROTECTED
MODE, AND COPROCESSOR SllPPORT
lip to four 12IC~: systems can be linked Wid (xlIlll'Olit'.d
simullanmusly from one PC host. enahling you to debug
multipl'tlcessor systems. The 12IC~: f:mulator with an 802H£l
[Irohe support.~ all 8028£l pl'tlttxttxl mode I'apabilitil:s. It
also supports tht' 8087 and 80287 numeric coprocessors.
II cOIllIll,mtl linl' Illter'face is also availahlt' with syntax
('hl~'killg alltil'lllltl,xt'St'lIsitivl' IlroIllPt.~. ICEVIJo:W wOl'ks
with lIIolI~X'hr1mw. (X:A and tht' Im.est ~:CII ('0101' displays.
11-99
IPA.,.." f'OIl SOFTWARE
ELECTIlICtU, CHAIlACTERISTlCS
PERFORMANCEANDCODECO~ERAGE
90-132 V or 1Il0-2ti4 V (sel('ctabll')
47-63 liz
12 ampo (AC)
ANALt'S/S
The I'ICE Emulator interfaces to Int(·i's iPAT Performance
Analysis Tixil for examining softwmil(' hast' 21(i
IIl1stidl:lssis rahl('
17.ll
II.!',
IklRhl
I.
na
('".
,.
KitOlti('
plll0101-.1'1'I)
Contl'llts
1~1(;r: system 10 Mllz HOH(i/HOHH
support kit [01' IBM PC hoot. Inl'lucll'o
probe. chassis. and host int1'l'fal'('
1ll0dlll(' anti SOn.I\'lI\·.
1~ICr: syotl'1II 10 ~ll1z HO 1!Iii support
plllllll-.ITIl
kit lill' IIl~1 I'C host. Incilld!'o proiM',
l'hasois. host illlel'fa,'!' 1II0duli' anti
soll\\w'('. "I)tt·: 1'0[' Hll I HH support.
till' IIIIOH optionlwlOl\' nUlSt also 11('
o('(It·I'c·d.
III WI!
10 -'ll1z HOIHH support ('01l1t'l'si'H1 kit
to ('011\('l't HOIBIi pl'oil(' to HOIHH
pl'olll'.
1~ICr: systl'm, I 0 ~llIz H02Hti support
pl1l2121-.ITIl
kit lill' IB~I I'C XI' IlOot. Includc's
proil('. dlassis. host int('rf,I!'I' mociuli'
and son wal\·.
1110 I tlI'·\'I'CH!iIl
1~ICr: sYst('m III ~llJz HOHG/IIllHH
support kit with iI'IIl' Perthrmance
'\nalysis 'Ihol [01' PC :\T host. Includes
!"Ief: proill'. {'hassis, hm;t intl'l'far('
module, il"\'I' toolOptiOIl, !'ailles and
:-;0[(11'<1(,['. Also inrlull('s iC-Hn (,()1lIf1ili·r.
Hn ~lat'ro :\ss('llIhl('I', Utilities. an(1
Ar:IlIT tnt 1~liltll'.
11111 W\TCHliIJ
As al>ovl'lill' 10 Mllz 110 IIIIi sllflport.
1112121WI'CHI)IJ
As al>o\1' lill' 10 Mllz H02111i sllpport.
Notl': C-2Hli alld RLL·2Hll ;md
M;M-2Hn llIust 1>1' o('[lc'n~1 separately.
1"ICr: I'C AT hOot software. Iliciudes
ICr:VII·:W'· wintilllwd hlillHIII illt(·I-I'C AT.
Thr PC AT must meet the following minimllm rt'qlliremt~nts:
• 640K Bytes or Memory
• Intrl Above Board with at Lt'llst 1M Byte OIl' r:xpansion
Memory
• Ofl(' 3601\ l3ytrs or One 1.2M llytl'S Jo'loPI)Y Disk Drive
• Ofl(' 20M Ilytrs f'ixed·Disk Driv('
• PC· DOS 3.2 or LaIN
• ,\ &'rial Port (mM I OIl' OlM2) Slipporting Minimally at
g6m B.based target
system. With iPAT·386. it is possible to speed·tune
applications. optimize use of operating systems.
determine response characteristics. and identify code
execution coverage.
.
fur direct information on Intel's Development Tools. or
for the number of your nearest sales office or
distributor. call 800-874·6835 (U.S.). fur information
or literature on additional Intel products. call
800-548·4725 (U.S. and Canada).
By examining iPA'I~386 histogram and tabular
information about procedure usage (with the option of
including Interaction with other procedures. hardware.
the operating system. or interrupt service routines) for
critical functions. performance bottlenecks can be
identified. With iPAT·386 code execution coverage
information. the completeness of testing can be
confirmed. IPAT·386 can be used in conjunction with
Intel's ICr.·386'" in-circuit emulator to control test
conditions.
IPAT·386 provides real·time analysis up to 20M Hz.
performance profiles of up to 125 partitions. and code
execution coverage analysis over 252K.
fjEllI'IfJE, SIJPPfJIl'l', .4ND
'I'Il.4ININ6
'1'0 augment Its development tools. Intel otTers a full
array uf seminars. classes. and Workshops. field
application engineering expertise. hotllne technical
support. and on·site service.
--
PIlOIIIJCI' SIJPPfJIlT ItI.4TIUX
-
ASM-386 Macro Assembler
.. --
~
...
PUM·386 C.ompilf!r
...
C-386 Complier
".
RLL-386 Relocation.
Linkage. and Library tools
".
Ada-386 CmM CrunpilaUon
".
raclage
Intel386 Family In-(''ircult
Emulators
Monl1.Or-386 Stilware
Debu_
IPAT·388 l\'rfonnal1l'l'
...
".
...
...
".
...
...
...
...
3'1.
II4IXIJ\tIS .
... ...
...
... ...
... ...
".
..
...
...
...
...
.
...
...
...
Anolyms Toul
InI7
lArrow Electronics, Inc.
Perimeter Road
ManChester 03103
NEW JERSEY
tArrow Electronics, Inc.
Four East Stow Road
Unit 11
Marlton 06053
Tel: (609) 596-6000
TWX: 710-897-oS29
~Arrow
Electronics
CenruryDrive
~:r:s'C8~)n13~~
tHamiiton/Avnet Electronics
1 Keystone Ave .• Bldg. 36
~~1~~:2
tHamilton/Avnet ElectronIcs
10lndustnal
Fairfield 07006
~i~~~51i4~3:8
1MTI ~ystems Sales
7 KuliCk Rd.
Fairfield 07006
Tel: (201) 227-5552
tP!oneerElectronics
45 Route 46
Pinebrook 07058
Tel: (201)575-3510
TWX: 710-734-4382
MICHIGAN
NEW MEXICO
Arrow Electronics, Inc.
755 Phoenix Drive
Ann Arbor 48104
Tel: (313)
TWX: 810-223-6020
Alliance Electronics Inc.
11030 Cochiti S.E
971-8220
Hamliton/Avnet Electronics
2215 29th Street S.E.
Space AS
Grand Rapids 4950S
~~~J~~~?~9~~
Pioneer Electronics
4504 Broadmoor S.E.
Grand Rapids 49508
FAX: 616-698-1831
tHamilton/Avnel ElectroniCS
32467 Schoolcraft Road
l.lvonia48150
Tel: (313) 522-4700
TWX: 810-282-8775
~~~Vb~::~t~
Hamilton/Avnet Electronics
2524 Baylor Drive S.E.
~~8~~~i~ii~
NEW YORK
tArrow Electronics, Inc.
3375 Brighton Henrietta Townline Rd.
Rochester 14623
~;Jn~I~~DJl6
Arrow Electronics. Inc.
20 Oser Avenue
~:I~fGla6ig;3~ ~ i8&
TWX: 510-227-6623
Hamiiton/Avnet
933 Motor Parkway
tPioneer Electronics
6408 Castl.&place Drive
~Hamilton/Avnet Electronics
219 Quivera Road
Overland Park 66215
~~gn:;53~:l7
~:~~"Nf~~~~~
~~Jrb~~~
~P~~~~~5~~6
~~I~ek!~~~ Drive
Arrow Electronics, Inc.
25 Upton Dr.
Carmel 46032
KANSAS
tArrow Electronics, Inc.
400 Fairway Drive
Suital02
Deerfield Beach 33441
MASSACHUSETTS
495 Directors Row. Suite H
CONNEcnCUT
Hamilton/Avne! Electronics
Commerce Industrial Park
Commerce Drive
tHamilton Electro Sales
10950 W. Washington Blvd.
~1:0Sw~t~~~~J~f:
¥~P:'~ro)19BJ'-lli.t
~~nb!~J,~~
650 Desoto Avenue
Chatsworth 91311
Tel: (818)700-1161
~~j~~~2~o,o6
tPioneerfTechnologles Group, Inc.
9100 Gaither Road
Gaithersburg 20877
Tel: (301) 921-0660
TWX: 710-S28-0545
NEW HAMPSHIRE
MINNESOTA
tArrow Electronics, Inc,
5230 W. 73rd Street
Edina 55435
~~~~b~7°6-tr,~5
l~:oJ'~hft~a~~~~:nics
Minnetonka 55434
Tel: (612) 932-0600
tPioneer Electronics
7625 Golden Trlange Dr.
SuiteG
Eden Pralri 55343
Tel: (612) 944-3355
MISSOURI
tArrow Electronics, Inc.
2380Schuelz
St. Louis 63141
Tel: (314) 567-6888
TWX: 910-764-0882
tHamiiton/Avnet Electronics
13743 Shoreline Court
Earth CI~ 63045
~314 344-1200
: 91 -762-0684
~~CJaf~~32~is
~milton/Avnet
Electronics
Metro Park
Rochester 14623
~~n~;:s'..a?o
t~~~~i~%~~~e6~~e;tronics
Syracuse 13206
~~~ibW,~~o
tMTI Systems Sales
38 Harbor Park Drive
~1~(~~)hJ~~~~66 050
1PioneetElectro.nics
8 Corporate Dnve
Blnghamton 13904
~~n:i;2?c?8DJla
Pioneer Electronics
40 Oser Avenue
~:I~fC:6)g:3~ ~~~60
~:~i(g) 2~~~U75
33102
~~Jr~5l=704
tMlcrocomputer System Technical Distributor Center
CG/SALE/l110BB
intJ
DOMESTIC DISTRIBUTORS (Cont'd.)
NEW YORK (Conl'd.)
OKLAHOMA
TEXAS (Cont'd.l
WISCONSIN
~iOn&8r
Arrow Electronics, Inc.
~HamiltonfAvnet ~tectronics
Arrow Electronics. Inc.
200 N. Patrick Blvd., Sle. 100
Electronics
Crossway Park West
~n[~\i~~and
~ioneer
11797
Electronics
o Fairport Park
Fairport 14450
1211 E.51stStreet
Suite 101
R~~~ Stf~eoltesl
~8~~~S;2~~6
Drive
~~~~~~~~~~~:~! ~r~.p, Inc.
Charlotte 28210
~919) 527-8188
: 810-621-0366
~;Jr~~~?l53ff3
tAlmac Electronics Corp.
1885 N.W.169th Place
Beaverton 97005
Tel: (503) 629-8090
TWX: 910-467-8746
~amilton/Avnet
Electronics
24 5.w. Jean Road
Bldg. C, Suite 10
~~(5~)~~J~r
TWX: 910-455-8179
Wyle Distribution Group
5250 N.E. Elam Young Parkway
Suite 600
Hillsboro 97124
Tel: (503) 640-6000
TWX: 910-460-2203
OHIO
PENNSYLVANIA
Arrow Electronics, Inc.
7620 McEwen Road
Centerville 45-459
~~J~~i9~56~
Arrow Electronics. Inc.
650 Seco Road
Monroeville 15146
Tel: (412) 85&-7000
tArrow Electronics, Inc.
6238 Cochran Road
Solon 44139
Hamilton/Avnet Electronics
~~J~~4Jli:~~
Tel:
tHamiltOn/Avnet Electronics
54 Senate Drive
~~J;~~~:'
Hamilton/Avnet Electronics
~:e~~~:7e 1~~~am21'
~~b~~beh"5~38'
(41~) 281-4150
Pioneer Electronics
259 Kappa Drive
~~~:s(~1rgh7~~~g~oo
lWX: 710-795-3122
tPioneer{TechnologiesGroup.lnc.
Delaware Valley
261 Gibralter Road
Horsham 19044
~~Jfb!'2~~~52
w~~n~~~~08
wamilton/Avnet Electronics
TEXAS
Tel: (614) 882-7004
tArrow Electronics, Inc.
3220 Commander Drive
Carrollton 75006
w:s~~~s:g881Blvd.
lmn~~=~'iro~~evard
~~J1~~~3~
~~J~~~~
tArrow Electronics. Inc.
10899 Kinghurst
Suite 100
Houston 77099
Dayton 45424
tPioneer Electronics
4800 E. 131 sl Street
Cleveland 44105
~~J~l&8b~2~
tZentronics
B Tilbury Court
Tel: (414) 784-4510
TWX: 910-262-1182
tPioneer Electronics
18260 Kramer
Austin 78758
Tel: (512) 635-4000
TWX: 910-874-1323
tPioneer Electronics
~Hamilto':l/Avnet Electronics
Hamilton/Avne! Electronics
2975 Moorland Road
OREGON
~~r~r8~W6
Napean K2E 7lS
~:t~jb?2~~~~3
i~!~:~}~f1~d~~ ~~:~9~S
60..5929
~J~~~
tArrow Electronics. Inc.
2227 W. Braker lane
Austin 78758
Tel: (512) 835-4180
TWX: 910-874-1348
b~~!~ ~5~a Road
~~~1~3:S'i5~
tPioneer Electronics
5853 Point West Drive
Houston 77036
Tel: (713) 988-5555
TWX: 910-881-1606
Wyle Distribution Group
1810 Greenville Avenue
Richardson 75081
Tel: (214) 235-9953
UTAH
Arrow Electronics
1946 Parkway Blvd.
New Berlin 53151
CANADA
ALBERTA
Hamilton/Avnet ElectrOniCS
2816 21st Street N.E.
~~~:2~7~!~286
Zentronlcs
~aooNl04t~ Avenue N.E.
~:i~(~~3I~~2~~21
BRITISH COLUMBIA
l~~~~on~~~~~~~onics
Tel: (604) 437-8667
Zentronics
~~!~~~ ~J~~wrt Road
¥:i~ (~~i ~j~::~~9
Tel: (604) 273-5575
lWX: 04-5077-89
tHamilton/Avnet ElectroniCS
1585 West 2100 South
MANITOBA
i::~ (~~i ~j~_::JJ9
Zentronics
60-1313 Border Unit 60
lWX: 910-925-4018
Wyle Distribution Group
1325 West 2200 South
Suite E
~j:s:~~!:eg'7f-~~g3
WASHINGTON
tAlmac Electronics Corp.
14380 S.E. Eastgate Way
Bellevue 98007
Tel: (206) 643-9992
lWX: 910-444-2067
~~t(~ ~~~I~~i
TWX: 05-349-71
~~f:(.rll~) 4~~~9~
TWX: 06-97&-78
tZentronics
155 Colonnade Road
Unit 17
Nepean K2E 7Kl
Tel: (613) 22&-8840
Zentronics
60-1313 Border 51.
~t(~ ~~~7~~7
QUEBEC
tArrow Electronics Inc.
4050 Jean Talon Quest
Montreal H4P lWl
~~~6~~15~9g511
Arrow Electronics, Inc.
909 Charest Blvd.
Quebec JIN 2C9
Tel: (418) 687-4231
TWX: 05-13388
Hamilton/Avnet Electronics
2795 Halpern
SI. laurent H2E 7Kl
~~~J{~2~-1~
Zentronics
~~.7~~~~~~1r 1M3
~~6~!;il.t-I500
ONTARIO
Arrow Electronics. Inc.
36 Antares Dr.
Nepean K2E 7W5
Tel: (613) 22&-6903
Arrow Electronics. Inc.
1093, Meyerside
~~~s(~f:lu~::::~~6~M4
TWX: 06-218213
Arrow Electronics. Inc.
19540 68th Ave. South
Kent 98032
Tel: (206) 575-4420
tHamilton/Avnel Electronics
6845 Rexwood Road
Units 3-4-5
t~:~il:fW~~~~tS~:~onics
lWX: 6'0-492-8867
Bellevue 98005
Tel: (206) 643-3950
lWX: 910-443-2469
Hamilton/Avnet Electronics
6845 Rexwood Road
Unit 6
'1"?i8J>~~i.b=ns~:~p
tHamilton/Avnet Electronics
190 Colonnade Road South
Tel: (613) 226-1700
r~f~jl~~~fs~n~:.~~~~or~~
: 91
ONTARIO (Cont'd.)
Brookfield 53005
Tel;
NORTH CAAOUNA
tArrOw Electronics.lnc.
240 Greensdairy Road
~75038
14~50-6111
Tulsa 74146
Tel: (918) 252-7537
Tulsa 74146
Tel: (918) 252-7297
~;J~~a:d3?lk~
111 W.Walnut HJlILane
~~n~f:)uSh~~I31R2
~~f:(~;:)u~:7~i.r2
Redmond 98052
Tel: (206) 881-1150
tHamiiton/Avnet Electronics
1807 W. Braker lane
Austin 78758
Tel: (512) 637-8911
TWX: 910-874-1319
tMicrocompute1" Sy$tem Technical Distributor Center
CG/SALEfl11088
inter
EUROPEAN SALES OFFICES
DENMARK
WEST GERMANY
ISRAEL
SPAIN
Intel
Glentevej 61, 3Td Floor
Intel·
Dornacher Strasse 1
8016 Feldkirchen bei Muenchen
Inlel
FAX: 904-3948
Intel·
Atidim Industrial Park-Neve Sharet
P.O. Box 43202
Tel-Aviv 61430
Tel: (972) 03-498060
TLX: 371215
Intel
ITALY
~!~4~ro~r:~O ~
TLX: 19567
irX~~:~g~~?90992-0
FINLAND
SWEDEN
00390 Helsinki
Hohenzollern Strasse 5
3000 Hannover 1
Tel: (49) 0511/344081
Tel: (358) 0 544 644
TLX: 9-23625
Inlel'
Milanofiori Palazzo E
20090 Assago
Milano
Intel
Abraham Lincoln Strasse 16-18
it:~~1~~~ 8244071
6200 Wiesbaden
Tel: (49) 06121/7605-0
NETHERLANDS
Intel
RuosUanlie2
Tl.X: 123332
FRANCE
Intel
'. Rue Edison-BP 303
TLX: 4_186183
78054 51. Quentin-en·Yvelines Cedex
~~~~9~~ ~O 57 70 00
Intel
Inlel·
~lli~~1fiflg8728-0
4, Quai des Etroits
69321 Lyon Cedex 05
Zurbaran,28
28010 Madrid
Tel: (34) 410 40 04
TLX: 46880
Inlel'
Zettachring IDA
i~~~1M~~! 78424089
Intel'
~7\V~~esof~a
Tel: (46) 8 734 01 00
TLX: 12261
SWITZERLAND
Intel
Zuerichstrasse
8185 Winkel·Rueli bel Zuerich
~6~eAVM~~~:~a~3
it::(~~5~VrO 62 62
Tel: (31) 10.407.11.11
TLX: 22283
UNITED KINGDOM
NORWAY
Intel'
Intel
Hvamveien 4·PO Box 92
2013 Skjetten
i~f~~o(fh 842 420
~~~Jo~.a~iltShire SN3 lRJ
i~~~~~m 696000
EUROPEAN DISTRIBUTORS / REPRESENTATIVES
AUSTRIA
WEST GERMANY
NETHERLANDS
UNITED KINGDOM
Bacher Electronics G,m.b.H.
AOlenm,uehlgasse 26
1120Wlen
i~~~W1W~i2) 83 56 46-0
Electronic 2000 AG
Koning en Hartman
Accent Electronic Components ltd.
Jubilee House. Jubilee Road
Letchworth, Herts SG6 tTL
BELGIUM
Inelco Belgium SA
Av. des Croix de Guerra 94
1120 Bruxelles
?f;boa~~~~~tenlaan, 94
~l:,~~~':n~~~~ 1~
i~f~6~g2)
ITT Multikomponent GmbH
Postiach 1265
Bahnhofstrasse 44
NORWAY
~~~hw~~~~at~lt~~ms
Nordisk Eleklronikk (Norge) A/S
Postboks 123
Smedsvingen 4
1364 Hvalstad
i~:(WJ1ll) 84 62 10
Western Road
Bracknell RG121RW
~~~(W!~~~i£S79
Jermyn GmbH
1m Dachsstueck 9
DENMARK
t
TLX: 415257-0
i~~~
!Wl 45 66 45
~~~~ 4~i:tj 1508·0
PORTUGAL
~o:,~i~~;~~~!~e.,~9
Ditram
Avenida Marques de Tomar, 46-A
1000 Lisboa
Tel: (351)(1) 73 48 34
TLX: 14182
Tel: (49) 089[78042-0
TL.X: 5213189
SPAIN
Metrologie GmbH
FINLAND
OY Fintronic AB
Melkonkatu 24A
00210 Helsinki
i::i~~~2~k 6926022
Proelectron Vertriebs GmbH
Max Planck Strasse 1-3
6072 Dreieich
Tel: (49) 06103/3040
TLX: 417903
IRELAND
FRANCE
Generim
Z.A. de Courtaboeuf
Av. de la Baltiqu&-BP 88
91943 Les Ulis Codex
m~W,9!.\'9 07 7. 7.
Micro Marketing Ltd.
Glenageary Office Park
Glenageary
Co. Dublin
Tel: (21) (353) (01) 85 63 25
TLX: 31584
ISRAEL
~3~rrl.ntue des Solels
SiUc 585
94663 Rungis Cedex
i~~~~:5 60 04 00
~:~~°ci?K!~ieres
4, avo Laurent--Cely
92606 Asnieres Cedex
Tet: (33) (1) 47 90 62 40
TLX: 611448
Tekelec·Airtronic
Rue Carle Vernel • BP 2
92315 Savres Cedex
i~:(~J.lJU5 34 75 35
686666
i~~1~2~~/42oo1'0
i~r~~o/~) 216 01 60
ITT-Multikomponenl
Naverland 29
2600 Gloslrup
16~7e~~eo~
Tel: (31) 15609906
TLX: 38250
Eastronics Ltd.
11 Rozanis Street
P.O.B.393OO
Tel·Aviv 61392
Tel: (972) 03-475151
TLX: 33638
ITALY
Intesl
Divisione In Industries GmbH
Viale Milanofiori
Palazzo
20090 Assago
Milano
E/5
i~~~~)I~~1824701
t~f! ~~I~rg~;:t~f2~'
ATC Electronica, SA
Plaza Ciudad de Viena, 6
28040 Madrid
i~:(~i7~ 40 00
ITT-SESA
~:~~oMjlad~\:ngel, 21-3
i~!~;4~~9 09 57
SWEDEN
Nordisk Elektronik AB
Huvudstagatan 1
Box 1409
171 27 Solna
i~~~~50t734 97 70
iEif~7~ogr) 55333
Jermyn
Vestry Estate
OtfOfd Road
Sevenoaks
Kent TN14 5EU
i~~t~I~I32)
450144
MMD
Unit 8 Southview Park
Caversham
Reading
.
Berkshire RG4 OAF
i~t~~Mgx:,) 4816 66
Rapid Silicon
Rapid House
Denmark Street
High Wycombe,
Buckl~hamshlre HP11 2ER
Tel: (44 (0494) 442266
TLX: 7931
Rapid Systems
Rapid House
Denmark Street
High Wycombe
Bucki~hamShir&
i~~44 7~r)
HP11 2ER
450244
YUGOSLAVIA
SWITZERLAND
Industrade A.G.
Hertistrasse 31
8304 Wallisellen
Tel: (41) (801) 83 05 04 0
TLX: 56788
Rapido Electronic Components S.p.a.
Via C. Beccaria. 8
34133 Trieste
Italia
i~~~%.t~f360555
TURKEY
EMPA Electronic
Lindwurmstrasse 95A
8000 Muenchen 2
i~!~~8~~W53 80 570
20092 Cinisello Balsamo
Milano
i~~~2~~440012
'Field Application Location
CGfSALE/111088
inter
INTERNATIONAL SALES OFFICES
AUSTRALIA
JAPAN
JAPAN (Cont'd_)
KOREA
Intel Australia Ply. Ltd.'
Intel Japan K.K.
5-6 Tokedal, Tsukuba·shi
~R~~:~~!~~~~9i Bldg.
Crows Nest, NSW, 2065
Tel: 029747-8511
Tel: (2) 957-2744
TLX: AA 20097
FAX: (2}923-2632
TL.X:3656-160
FAX: 029747-8450
Intel Technology Asia, Ltd.
Business Center 16th FlOor
61. YOi
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