1989_Motorola_MECL_System_Design_Handbook_4ed 1989 Motorola MECL System Design Handbook 4ed

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MECL
SYSTEM DESIGN HANDBOOK
Fourth Edition
Compiled by the Computer Applications Engineering Department

Author

Wilham R. Blood, Jr.

®

MOTOROLA Semiconductor Products Inc.

Circuit diagrams external to Motorola products are included as a means of
illustrating typical semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given. The
,"formation in this book has been carefully checked and is believed to be entirely
reliable. However, no responsibility is assumed for inaccuracies. Furthermore,
such information does not convey to the purchaser of the semiconductor devices
described any license under the patent rights of Motorola Inc. or others.

Motorola reserves the right to make changes Without further notice to any
products herein to Improve reliability. function or design Motorola does not
assume any liability arising out of the application or use of any product or
CirCUit described herein, neither does It convey any license under ItS patent
rights nor the rights of others Motorola and @are registered trademarks of
Motorola, Inc Motorola, Inc IS an Equal Employment Opportunity/Affirmative
Action Employer

MEeL, MEeL I, MEeL II, MEeL III, MEeL lOKI lOKH, MTTL,
MTTL III, Micro T, and MDTL are trademarks of Motorola Inc.

Fourth Edition
Fourth Printing

©MOTOROLA INC., 1988
Previous Edition ©1980

Printed in U.S.A.

ii

PREFACE
In response to the demand for higher perfonnance systems, engineers
are looking at digital integrated circuit families which are faster than the
popular TTL types. Motorola's Emitter Coupled Logic (M ECL)
circuits have the characteristics to meet the performance requirements
for present and future systems. M ECL IOKIIOKH are ideal for
computer and communications systems, while state-oj:the-art instrumentation equipment uses M ECL II! and M EeL JOKH.
As circuit speeds increase, wiring rules and system design techniques
must be adjusted accordingly. Designing with MECL is no more difficult
than designing high performance equipment with slower forms of logic.
High performance system design for any form of logic, however, does
require an understanding of the factors which affect system performance.
In fact, many of the MECL features such as transmission line drive capability, complementary outputs, Wired-OR, and versatile logic functions
can add as much to system performance as the short propagation delays
and high toggle rates.
In the past, several articles and application notes have been written
about MECL circuits and systems. However, there was a need for a book
which would completely define MEeL operation. This book has been
written to give the designer the information to establish design roles for
his own high performance systems.
The information in this book is based on equations derived from
electronic theory, laboratory tests, and inputs from MEeL users. All of
the roles and tables are for conservative system design with MEeL
circuits. It is important to realize that the circuits can operate properly
under conditions much more adverse than suggested in this book.
In addition to the technical contributors, Jon DeLaune, Jerry
Prioste and Cary R. Champlin, the author would like to thank Lloyd
Maul, Mike Lee, Reg Hamer, Don Murray, Mike Stowe and Tom
Balph whose knowledge of M ECL has added to the completeness
and accuracy of this book. Finally, great appreciation is due to the
many technicians, engineers, and managers who took their valuable
time to read all or part of this book as it was developed.

iii

Table of Contents
Introduction . . . .

vi
vi
vi
.. viii

What Is MECL?
History of MECL
Why Use MECL? .
The Advantages of MECL .
MECL Areas of Application
Purpose of This Book . . . .

ix
ix

x

CHAPTER 1 - MECL Families
The BasIc MECL Gate .
Noise Margin . . . . . .
MECL Circuit Types ..
MECL Flip-Flops . . . .
Operation of Flip-Flop
MECL Family Comparison

8
10
12
12
14

CHAPTER 2 - Using MECL

19
MECL Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 19
A. Logic Design Considerations . . .
19
B. System Layout Considerations ..
25
C. Circuit Board Layout Techniques
26
D. Backplane Wiring . . . . . .
27
E. System Considerations ..
28
MECL lOKI IOKH Design Rules .
A. General Considerations ..
B. Printed Circuit Card Layout Techniques
C. Power Supply Bypassing on Circuit Cards ..
D. Backplane and Loading Considerations
E. System Distribution and Grounding
F. Loadmg Rules for MECL lOKI IOKH .
MECL III Design Rules . . . . . . . . . . . .
A. Circuit Card Layout . . . . . . . . . .
B. Transmission Line (Microstrip Line) .
C. On-Card Clock Distribution via Transmission Lines
D. Off-Card Clock Distribu tion . . . . . . . . . . . .
E. Testing MECL III . . . . . . . . . . . . . . . . . .

CHAPTER 3 - Printed Circuit Board Connections
Transmission Line Geometries . . . .
Basic Transmission Line Operation . . . . . .
Unterminated Lines . . . . . . . . . . . . . .
Series Damped and Series Terminated Lines
Parallel Terminated Lines . . . . .
Transmission Line Comparison . . . . . . . .
Wirewrapped Cards . . . . . . . . . . . . . .

CHAPTER 4 - System Interconnections

29
29
29

30
30
31
32

35
36
36
37
38

38
41
43
48
49

52

58

59
61

63

Connectors . . . . . . . . . . . . . . . . . . .
Coaxial Cable . . . . . . . . . . . . . . . . . .
Differential Twisted Pair Lines and Receivers ..
Ribbon Cable . . . . . . . . . .
Schottky Diode Termination . . . . . . .
Parallel Wire Cables . . . . . . . . . . . .
Twisted Pair Cable, Driven Single-Ended

iv

65
65

70
76
77
82
89

CHAPTER 5 - Power Distribution

93
94
97
98
101
102
105

System Power Calculations ..
Power Supply Considerations
System Power Distribution ..
Backplane Power Distnbution
On-Card Power Distnbution ..
VTT Termination Voltage DistnbutlOn

CHAPTER 6 - Thennal Considerations

107
108

MECL Integrated Clfcuit Heat Transfer
MECL DC Thermal Characteristics.
Heat Dissipation Techniques . . . . . .
Mounting Techniques . . . . . . . . . . .

112
116

120

CHAPTER 7 - Transmission Line Theory
Transmission Line Design Information, With Examples
Signal Propagation Delay for Microstrip and Strip Lines With
Distnbu ted or Lumped Loads . . . . . . . . . . . . . . . . . . .
Mlcrostrip Transmission Line Techniques, Evaluated Using TDR
Measurements, With Examples . . . . . . . . . . . . . . . . . . . .
The Effect of Loading on a Parallel Terminated Transmission Lme,
With Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analysis: Series Terminated Lines Compared to Parallel Terminated
Lines, With Exam pie . . . . . . . . . . . .
Analysis of Series Damping Terminations .
Bibliography . . . . . . . . . . . . . .

CHAPTER 8 - MECL Applications

121
121
129
132

145
152

159
172
173

Interconnection Techniques . . . . .
AC Noise Immunity of MECL 10K . . . .
Testing MECL lOKI IOKH Logic CircUits
Interfacing With MECL 10K/IOKH .
Bussing with MECL IOKllOKH . . . . . .
IC Crystal Controlled Oscillators . . . . .
Programmable Counters Using the MCI0136 and
MCIO\37 MECL 10K Universal Counters . . . . . . .

Index of Tabulated Data .......................................................

v

173
195

201
207
216

224
229

233

Introduction
What is MECL?
The term MECL identifies Motorola's emitter coupled logic. Emitter coupled
logic is a non-saturating form of digital logic which eliminates transistor storage time
as a speed limiting characteristic, permitting very high speed operation. "Emitter
Coupled" refers to the manner in which the emitters of a differential amplifier within the integrated circuit are connected .. The differential amplifier provides high
impedance inputs and voltage gain within the circuit. Emitter follower outputs restore the logic levels and provide low output impedance for good line driving and
high fanout capability.
History of MECL
Motorola has offered MECL circuits in five logic families: MECL I, MECL II,
MECL III, MECL 10,000 (MECL 10K), and MECL IOHOOO (MECL IOKH).
The MECL I family was the first digital monolithic integrated circuit line
produced by Motorola. Introduced in 1962, MECL I was considerably beyond the
state-of-the-art at that time. Several y~ars passed before any other form of logic
could equal the 8 ns gate propagation delays and 30 MHz toggle rates of MECL I. As
a result of its reliability and performance, MECL I was designed into many advanced
systems.
In 1977 MECL I was phased out of production. Features of the more advanced
MECL III and 10K favor their being used in new designs. For example, MECL I required
a separate bias driver package to be connected to each logic function. This means increased
package count and extra circuit board wiring. Also the lO-pin packages used for MECL I
limit the number of gates per package and the number of gate inputs. No provision was
made for operation of MECL I with transmission lines, as they were unnecessary with the
8 ns rise and fall times.
In 1966 Motorola introduced the more advanced MECL II. The basic gate
featured 4 ns propagation delays and flip-flop circuits that would toggle at over
70 MHz. MECL II immediately set a new standard for performance that has been
equaled by non-ECL logic only with the introduction of Schottky TTL in 1970.
Motorola continued with the development of MECL II and flip-flop speeds
were increased first to 120 MHz for the JK circuit, and then to 180 MHz for the
type D flip-flop. To drive these high speed flip-flops, high speed line drivers were
introduced with 2 ns propagation d/elays and 2 ns rise and fall times. With 2 ns edges,
transmission lines could be used to preserve the waveforms and limit overshoot and

ringing on longer lines. Consequently, a part was designed to drive 50-ohm lines.
Because of the significant speed increase of the line drivers and high speed flip-flops
over the basic MECL II parts, these circuits are commonly called MECL 11-1/2,
although they are part of the MECL II family.
MECL II circuits have a temperature compensated bias driver internal to the
circuits (except for the line receiver which requires no internal bias). The internal
bias source simplifies circuit interconnections and tracks with both temperature and
supply voltage to retain noise margin under varied operating conditions.
Complex functions became available in MECL II when trends shifted toward
more complicated circuits. The family had adders, data selectors, multiplexers,
decoders and a Nixie* tube decoder I driver. MECL II was discontinued in 1979
superseded by MECL III, MECL 10K and MECL lOKH.
Motorola's continuing development of ECL made possible an even faster logic
family. As a result, MECL III was introduced in 1968. Its 1 ns gate propagation
delays and greater than 500 MHz flip-flop toggle rates remain the industry leaders.
The 1 ns rise and fall times require a transmission line environment for all but the
smallest systems. For this reason, all circuit outputs are designed to drive
transmission lines and all output logic levels are specified when driving 50-ohm
loads. Because of MECL Ill's fast edge speeds, multi-layer boards are recommended
above 200 MHz. For the first time with MECL, internal input pulldown resistors are
included with the circuits to eliminate the need to tie unused inputs to VEE. The
Hi-Z 50 kn input resistors are used with transmission lines for most applications.
MECL Ill's popularity is with high speed test and communications equipment.
Trends in large high speed systems showed the need for an easy to use logic family
with 2 ns propagation delays. To fill this requirement, Motorola introduced the MECL
10K series in 1971. In order to make the circuits comparatively easy to use, edge speed was
slowed to 3.5 ns (10%-90%) while the important propagation delay was held to 2.0 ns. The
slow edge speed permits use of wire wrap and standard printed circuit lines. However, the
circuits are specified to drive transmission lines for optimum performance.
Because of technological advances in processing as well as market demands for even
higher performance devices, Motorola introduced its newest high-speed ECL family,
MECL lOKH in 1981. This family provides propagation delays of 1 ns with edge speeds
slowed to 1.8 ns (10-90%). These speeds, which are attained with no increase in power over
MECL 10K, are due to both advanced circuit design techniques and Motorola's new oxide
isolated process called MOSAIC (Motorola Oxide Self Alligned Implanted Circuits). This
process allows smaller device geometries, improved fTs (greater bandwidth) and reduced
paracitic capacitances.
To enhance existing systems, many of the MECL lOKH devices are pinout I functional
duplications of the MECL 10K family. Also, MECL lOKI lOKH are provided with logic
levels that are completely compatible with MECL III and the MECL Macrocell Arrays to
facilitate using all families in the same system. Another important feature of MECLlOKI
lOKH is the significant power reduction over both MECL III and the older MECL II.
Also, because of this low gate power and advanced circuit. design techniques, the MECL
lOKH family has many new functions not available by the other families. Although MECL
10K continues to be the most widely used ECL family in the industry, MECL lOKH is
setting new standards in speed and power.
*T.M. - Burroughs Corp.
vii

Why Use MECL?

Circuit speed is, of course an obvious reason for designing with MECL. MECL
lOK/lOKH offer shorter propagation delays and higher toggle rates than any non-ECL
type of logic. Equally important to the circuit speed are the characteristics of MECL
circuits which permit entire systems to operate at high speeds.
The ability of the faster MECL families to drive transmission lines becomes
increasingly important in larger and faster systems. While a transmission line
environment imposes some additional design rules and restrictions, the advantages of
longer signal paths, better fanout, improved noise immunity, and faster operation,
often more than compensate for the restrictions.
When using MECL lOK/lOKH without transmission lines, the high input impedances permit the use of series-damping resistors to increase wiring lengths and to improve
waveforms. Unlike non-ECL forms of logic, MECL circuits have constant power
supply requirements, independent of operating frequency. This simplifies power
supply design, since circuit speed need not be considered a variable. At fast circuit
speeds MECL can offer a considerable power saving over the other types of logic.
In addition to faster operation, the line driving features of MECL circuits can
be exploited to improve system performance. For one, the parts specified to drive
transmission lines will drive coaxial cables over distances limited only by the
bandwidth of the cable. In addition, the shielding in coaxial cable gives good
isolation from external noise.
More economical than using coaxial cable, is the ability of the MECL circuits to
differentially drive and receive signals on twisted pair lines. Using this technique,
signals have been sent over twisted pair lines up to 1000 feet in length.
The complementary outputs and Wired-OR capabilities of MECL circuits result
in faster system operation with reduced package count and a power saving. The
complementary outputs are inherent in the circuit design and both outputs have
equal propagation delay. This eliminates the timing problems associated with using
an inverter to get a complement signal. The logic OR function is obtained by wiring
circuit-outputs together. The propagation delay of the Wired-OR connection is much
less than a gate function and can save power, as only one pulldown resistor or
termination is required per Wired-OR.
Another advantage when designing with MECL is the low noise generated by
the circuits. Unlike totem pole outputs, the emitter follower does not generate a
large current spike when switching logic states, so the power lines stay comparatively
noise free. The low current-switching in signal paths, relatively small voltage swing
(typically 800 mY), and low output impedances, cut down crosstalk and noise.
Generated noise is also reduced by MECL's relatively slow rise and fall times.
For each MECL family the edge speed is equal to or greater than the propagation
delay. The low noise associated with MECL is especially important when the logic
circuits are to be used in a system which contains low level analog or
communications signals.
The flexibility of the MECL line receivers and Schmitt triggers to act as linear
amplifiers leads to many functions that may be performed with standard MECL
circuits. For example, in addition to amplifying low level signals to MECL levels,
these MECL circuits can be used as crystal oscillators, zero crossing detectors, power
buffers, Schmitt triggers, RF and video amplifiers, one-shot multivibrators, etc.

viii

The Advantages of MECL
1. Highest speed IC logic available
2. Low cost
3. Low output impedance
4. High fanout capability
5. Constant supply current as a function of frequency or logic state
6. Very low noise generation
7. Complementary logic outputs save on package count
8. Low crosstalk between signal leads
9. All outputs are buffered
10. Outputs can be tied together giving the Implied-OR function
11. Common mode rejection of noise and supply variations is 1 V or greater
for differentia1line receiving
12. Bias supplies are internal, allowing MECL use with a single power
supply
13. Minimal degradation of parameters occurs with temperature

variation~

14. Large family of devices yields economical designs
15. Power dissipation can be reduced through use of Implied-OR and the
"Series Gating" technique
16. Easy data transmission over long distances by using the balanced twisted
pair technique with standard parts
17. Constant noise immunity versus temperature
18. Best speed-power product available
19. All positive logic functions are available
20. Adapts easily to MSI and LSI techniques
MECL Areas of Application
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

Instrumentation
High speed counters
Computers
Medical electronics
Military systems
Large real-time computers
Aerospace and communication satellite systems
Ground support system
High speed AID conversion
Digital communication systems
Data transmission (twisted pair)

12. Frequency syn thesizers
13. Phase array radar
14. High speed memories
15. Data delay lines

Purpose of This Book

Rules and guidelines for using the various MECL families comprise the subject
matter of this book. Because of edge speed and bit rate capabilities, each family has
differing system requirements. The family name will therefore be referenced for the
examples and figures in the text, whenever applicable. The information in this book
is meant to apply to MECL III and MECL lOK/lOKH. The information about MECL
lOK/lOKH will also apply to the M 10800 LSI processor family. This book aims at giving
the reader an understanding of the MECL families, as well as the knowledge needed to
confidently design with and use MECL.
Chapter 1 discusses the operation of MECL circuits and the characteristics of
the various families. It also shows methods for internally connecting the basic gates
to provide efficient complex functions. Of more importance to the user is Chapter 2
- a list of rules providing a condensed reference for using the various MECL
families.
Chapters 3, 4, 5, and 6 elaborate on those rules giving a technical background
for good system design and presenting test results showing MECL circuits in various
modes of operation. Chapter 3 describes circuit-to-circuit interconnections on a
card. Both open wire and transmission line techniques are covered. Chapter 4
expands the wiring techniques to show methods for card-to-card and panel-to-panel
interconnections. Chapter 5 elaborates on power distribution, showing how voltage
drops and power line noise affect noise immunity. Chapter 6 discusses thermal
considerations. Attention is given to the problems of calculating chip temperature,
removing heat from the system, and to the effect of thermal differences on noise
immunity.
Chapter 7 provides background necessary for understanding transmission lines
as they apply to MECL. Derivations of equations are shown, along with test results
correlating with the theoretical analysis. This chapter should be especially useful
when selecting a transmission line impedance and when determining the effect of
fanout or stray capacitance on the line.
Chapter 8 contains application ideas for MECL circuits. Included are methods
for interfacing various logic families with MECL, and numerous useful circuits
designed with MECL for high performance.
Finally, a brief appendix illustrates some of the peripheral hardware and
components of use in MEeL Systems.

x

MECL Families

The Basic MECL Gate
An understanding of the basic circuits used in the construction of a logic family
is important in order to successfully design and trouble-shoot a system which uses
the family. This chapter describes MECL circuits, compares MEeL families, and
gives some suggested rules for using MECL circuits in system design.
Figure 1-1 a shows a typical MECL 10K gate, - the basic gate circuit for the MECL
10K family. The figure shows the separate functional circuits within the gate.
The differential amplifier section contains the current steering element that
provides the actual logic gating of the circuit. It also provides the voltage gain
necessary for a narrow linear threshold region.
1-1a: MECL 10K Basic Gate
Internal
Temperature
and Voltage
Compensated
81as Network

Differential I nput Amplifier

r~--------------_A~--------------~ ~

RC2
RC1

217

245

Emitter
Follower
Outputs
r..-------A- - - - - - - - - \

907

--

_ _-+--o0R

18

Output

NOR
Output

4.98 k

A

8

C

D

~~----------y..-------~
Inputs

Basic MECL Gate

1-1b: MECL 10KH Basic Gate

An internal temperature and voltage compensated bias driver supplies a reference
voltage for the differential amplifier. The bias voltage, VBB, is set at the midpoint
of the signal logic swing. With the recommended - 5.2 volts supply voltage and
25° C ambient temperature, VBB is - 1.29 volts dc for either MECL lOKI lOKH or MECL
III. The diodes in the voltage divider line, together with Q6, provide temperature
compensation by maintaining a level consistent with the midpoint of the logic levels
despite changing temperatures.
One additional feature of the bias supply is its ability to track supply voltage
changes. Consequently MECL 10K gates, for example, are specified to operate from a - 5.2
volt ± 10% supply. In fact, they are capable of working over a much wider range (- 3.0 to 8.0 volts) although ac performance would be degraded.
A typical MECL lOKH gate can be seen in Fig. 1-1 b. This figure shows that both the
bias regulator and the emitter resistor source of the MECL 10K gate has been replaced by a
voltage regulator and a constant current source, respectively, in the MECL lOKH gate.
The new voltage regulator controls both variations in the output voltage as well as the
AC characteristics of the devices. The constant current source allows the use of matched
collector resistors which produces better matched delays, matched output tracking rates
with temperature and less variation in the output voltage level with changes in the power
supply. There is also a considerable improvement in noise margins over MECL 10K.
MECL lOKH is specified to operate from a - 5.2 volt ± 5% power supply.

2

MECL Current Switching

The emitter followers are output drivers. They provide level shifting from the
differential amplifier to MECL output levels, and provide a low output impedance for
driving transmission lines. MECL lOK/lOKH and MECL III circuits use open emitter
outputs. The reason is that since these circuits are designed for use with transmission lines,
and since the line termination provides an output load, internal pulldown resistors would
be a waste of power.
MECL lOK/lOKH and MECL III circuit families, designed to drive transmission
lines, have two VCC power voltage inputs. Vee I is used to supply current to the
output drivers, while VCC2 supplies the remainder of the circuit. Separate VCC lines
are used to eliminate crosstalk between circuits in a package. More important, the
use of two lines speeds up circuit performance by eliminating a voltage spike which
otherwise would occur on the bias voltage, VBB, caused by the relatively heavy
currents associated with transmission lines. Each VCC pin should be connected to
the system ground by as short a path as possible (all VCC pins are connected to the
same system ground).
The input pulldown resistors shown in Figure I-I a and b are characteristic of MECL
lOKI lOKH and MECL III. MECL lOK/lOKH and MECL III use 50 k S1 resistors to
drain off the input transistor leakage current. These resistors hold unused inputs at a fixed
zero level, so unused inputs are left open.
MECL Logic Levels
The following calculations illustrate the current switching operation of a MECL 10K
gate. Similar calculations may be performed for the other MECL families by substituting
appropriate resistor values and voltage levels.
When all gate inputs are at a voltage, Yin, equal to a logic f> level, IVIL min! ~ Vin! ~ VIL
max!, the input transistors QI through Q4 in Figure I-I a will not be conducting current,
because the commn emitter point of these four transistors is at about -2.09 V: i.e., VBB +
VBEQ5 ~-1.29 V + (-0.80 V). This is not enough forward bias (base to emitter) on Ql
through Q4 for conduction. Thus, current flows through RC2, Q5, and RE. This current,
IEf>, is:

The voltage drop at the collector resistor. RC2, may be calculated as:

The output transistor base current, IB, is small compared to the switch current,
so the second term above can be ignored.
The OR output is then obtained through an emitter-follower, Q8, which cuts
the output level by one base-emitter drop, giving a voltage level:
VOL OR = VRC2 + VBE,
where: VBE = base to emitter drop on Q8, with logic zero current level (i.e., 6 rnA
thru Q8).
3

So:
VOL OR ~ -0.98 V + (-0.77 V) ~ -1.75 V,
I

typical at T A 25°C.
The base of the NOR output emitter-follower, Q7, is at about -0.05 V, yielding
an output of -0.89 V typical, at an output device current level of 22.5 rnA and TA = 25°C.
(These output voltage and current levels assume 50-ohm loads to a terminating voltage,
VTT, of -2.0 V).
If one or more of the gate inputs is switched to a voltage level, Yin, equal to a
nominal logic 1 level, IVIH minl~IVinl~IVIH maxi, a current IE 1 flows through
RCb QI-Q4, and RE. This current is:
VEE - (V in + V BE )

~

-4.51 rnA,

RE
where:

V in

= -0.89 V

VBE = -0.80 V
The current flow through RCI produces a voltage at the collector nodes of Q I
through Q4:
VRCI ~ IEIRCI =(-4.51mA).(217Q) ~ -0.98V.
Finally, the output is obtained through an emitter follower, Q7, which drops
the collector voltage level one base-emitter drop, so that:
VOL NOR = VRCI + VBE (output device at 6 rnA)
~

-0.98 V + (-0.77 V) = -1.75 V,

typical at T A =25° C.
The transfer curves in Figures 1-2(a) and (b) indicate the behavior of the MECL 10 K
gate while switching. Note from the data in Figure 1-3 and from the NOR transfer
characteristic: for Yin increasing from VIL min to VILA max, the output remains
at a high level. When Yin increases from VILA max to VIHA min' the NOR output
will switch to a low level. Then, as the input continues more positive than
VIHA min' the output continues more negative with a slope of about -0.24. This is
caused by the collector input node going more negative because of increasing
collector current as Yin goes more positive.
If the input continues in the positive direction, saturation will be reached at an
input of about -0.4 volts. Beyond that point, the base-collector junction is forward
biased to saturation and the colle'ctor voltage and output will go more positive
with the increasing input level. Since the saturation point is well above V OH max,
operation in this mode will not occur in normal system operation. The OR output
level depends on Q5's collector voltage (cf Fig. I-la). This output is unaffected by input
levels except in the active transfer region.
Fig. 1-2 (c) and (d) demonstrates the switching behavior ofMECL IOKH and Fig. 1-3
(c) lists the DC test parameters for IOKH. As can be seen in Fig 1-2 (d) the NOR output
stays level after Yin reaches VIH min as opposed to MECL 10K which slopes downward.
4

1-2; MECL 10K Transfer Characteristic and Specification Points

au TP UT va L T AG E

- 1 3501---+----l------+--JA1-\.j---l---+----l

(VOL TS)

-1 6

-1 4 -1 2

-1 0

INPUT VOLTAGE (VOLTS)

(a) TYPICAL TRANSFER CHARACTERISTICS AS A FUNCTION
OF TEMPERATURE (MECL 10K)

t

~

Gate Output
(measured test l,m,ts)

------------------~;+--'f
1850

1 475

VO H max

0.810

1 105

---~~~~--~-~-0810

\lOHA~I~:._V..:.O~H..:.m,,:,,:,,:,:In.:....:=t======i::::\:=;::J.:t--t-----11-0 960
--~~- - ~~ -~~.. ' .--.:

0 980

~--J-~...4

V OL min

VIL min
r-

VEE~-52V

-1630
-1650

--+L----I--+--4---...L---.%1 -1.850

Test CondItIons 25° C
50n matched
Inputs and outputs

HIgh
} State

Gate Input
}_
(ApplIed test voltage)

I

--''''''\

I·V··-·---

VIH max

Vee:::::: -1.29V
(SwItchIng Threshold)

(b) MECL TRANSFER CURVES (MECL 10K EXAMPLE)
and SPECIFICATION TEST POINTS

5

--1

Vtl::~~!:'l~~ L}}'!~.T!~.J

Low
} State

1-2: MECL 10KH Transfer Characteristics Specification Points

75°C
25°C

-095

ooe

75°C

I----

DOC

I--

25°C

'7

1\

-,~\

All

1\\\ /IJ
\\' "/

OUTPUT VOLTAGE
(VOLTS)

~X

-1.35

/I

~

iff1\\
rJ /
'1\

~\.

~IJ

-1.75

-1.6

-1 4

-1.2

-1.0

INPUT VOLTAGE (VOLTS)

(c) TYPICAL TRANSFER CHARACTERISTICS AS A FUNCTION
OF TEMPERATURE (MECL 10KH)

..

MECL10KH

lW'
-195
VOH max

Lt.
I~

V OHmln

-148

VOL min

,

:.......::.t

~

\1
VOL max

-081

-113

"

)~
If
:1

I

Test Conditions 25° C
VEE
50

~

n

-5 2V

(Applied test voltage)

}

matched

VIHmln

1 29V
VSS "'"
(Switched Threshold)

Inputs and outputs

(d) MECL 10KH TRANSFER CURVES and
SPECIFICATION TEST POINTS.

6

-195
V IH max

VIL max

}

-098

-163

j

VILmln
Gate Input

-0810

}

High
State

Low
State

1-3; MECL 10K/10KH and MECL III Specified Logic Levels and Thresholds

Forcing
Function

- 55 OC 130
UJ::; 110

3~
t;;

>

c::C::

> 130
w::;: 110

>
w::; 110

~ ~

90
70

t;; ~

is is

~~

50
,; 30

3: ~

10

3~

90
70

~~

90

50

70
0 0 50

30

~ 30

3:

I

10
001020304050607080910

ABSOLUTE VALUE OF VEE GRADIENT -

~2

V

-4

~6

-8

-10

VEE REGULATION RELATIVE TO -52 V- %

~

2

~

4

-6

10

VEE GRADIENT RELATIVE TO - 5 2 V -

%

A MECL 10K DRIVING MECL 10K B MECL 10K DRIVING MECL 10KH C MECL 10KH DRIVING MECL 10K D MECL 10KH DRIVING MECL10KH

MECL Circuit Types
It is possible to connect the basic MECL differential amplifiers together within
a circuit to increase logic flexibility, speed, and power efficiency. Two techniques,
series gating and collector dotting, add the NAND and AND logic functions to the
basic OR and NOR operation of the MECL gate with very little increase in
propagation delay. A third technique, Wired-OR, gives the logic OR function by
tying together two or more emitter-follower transistors. This is used internally in
complex functions to save speed and power and, unlike collector dotting, may also
be used externally by connecting logic outputs together.
Series gating is accomplished by connecting MECL differential amplifiers in a
current-switch "tree", building up from a current source, Q1, as shown in Figure
1-6. The A input controls the switch, Q2/ Q3 through the level shifter Q~ and the
associated resistor diode network. The bias network is modified to provide the
proper voltage level at Q3, a level which is lower than that on Q7 and Q5. The two
upper switch pairs are controlled by inputs Band C. The overall circuit generates the

four logic functions: AoB, AoB, AoC, and AoC. MECL circuits use up to three levels of
series gating, permitting up to eight logic functions with one current source.
The propagation delay from an input, to a top current switch is approximately
one gate delay. The propagation delay from an input to a lower level current switch
is slightly longer because of the input level shifter Qf/J. Typically, the latter takes
about 1.5 gate delays. More specific information is found on the data sheet for a
particular part.
Series gating is an advantage in MECL logic since it provides the AND or NAND
logic functions. Together with the OR/NOR function of the basic gate, MECL has
the four basic logic functions needed for efficient logic design. Series gating is used
internally in most MECL complex functions and flip flops.
10

1-6: Series Gating

A

80--+----+----.
C 0--+---+---,

4

A. C

L--~-4--~-----~~---~-----~-------~VEE

1-7: Collector Dotting

......--1---.....- ......- - 1 - - -.....--0 vCC2
R1

A

8 0 - - - 1 - - - -....

.---"VCC1

-----..... v o

C

D

(A + 8). (C+D)

0---+----.

~--~~-~~-------~-------OVEE

II

Sequential Logic: The MECL Flip-Flop

Collector dotting is a second logic technique which is used in the MECL lOKI lOKH
series. With it, the logic AND function can be generated by interconnecting
one collector node of separate differential current switches as shown in Figure 1-7. When
connected this way the two 2-input OR gates give the logic function:

v0 = (A

+

B) • (C

+

D)

Only one collector resistor (RC) is used for the two transistors Q I and Q2. The
interconnection requires that at least one input to each gate be at a logic I level for
the output to be at the logic I level. Since it is possible to have both Q 1 and Q2
conducting at the same time (all inputs low), a clamp is used to limit the current in
RC and maintain the output (/J logic level voltage. This clamp consists of R I and Q3.
They insure that the Q I/Q2 collector node never goes more negative than
(lBBR I + VBEQ3)· Propagation delays for all inputs to collector dotted circuits are
equal and are tYPIcally about 20% greater than the basic gate delay.
To allow for temperature variations, the collector-dotted logic functions are
designed to have the same VOL as normal logic gates at T A = T max when only one
gate has all of its inputs at a logic 0 level. Therefore, when all gates have all their
inputs at a logic 0 level, VOL will be slightly more negative than a normal gate. This
does not limit device operation, but does give an increase in noise immunity for the
logic 0 level.
The collector dot (OR-AND) logic function, series gating, and the Wired-OR
characteristics of MECL combine to provide the means for designing very efficient
and fast complex logic functions.
MEeL Flip-Flops

In addition to the basic gate, the flip-flops in a logic line provide a necessary building
block. All MECL lOKI lOKH and MECL III flip-flops, use the direct coupled master-slave
circuit as shown in Figure 1-8 for the MC1670. In each direct coupled circuit the
master is updated while the clock is low, and data is transferred to the slave on the
positive excursion of the clock. This type of circuit offers better noise protection
than ac coupled circuits and is not susceptible to overshoot on the inputs. Also, the
master-slave flip-flops do not have the rise time limitations of ac coupled circuits.

Operation Of Flip-Flop
In the circuit of Figure 1-8 assume that initially Q, C 1, C2, R, S, and D are at ~
levels and that Q is at the 1 level. Since the clocks and the Rand S inputs are low,
transistors 1Q3 and 2Q3 are conducting. In the slave section only transistors 2Q6
and 2Q7 are in series with 2Q3. The output of the slave section is fed back to these
two transistors in order to form a latch. Thus, when the clock is low, the output
state of the slave is maintained. In the master section, the current path is through
lQ3 and IQ9.
Now assume that the D input goes high. The high-input signal on the base of
1Q4 causes it to conduct, and I Q9 to turn off. The voltage drop across resistor RC 1
causes a low-state voltage on the base of I Q 11 and therefore on the emitter of
I Q II. Since there is essentially no current flow through RC2, the base of transistor
12

VCC1

VCC2
(

MASTER

SLAVE

~2a15
4

C2

C1 0

+05

06
07

I

>

125 ~

125

SO~~---4----~--+---~

w

AO

I

00

I

II

~

I I

-6'

o~

A8
55

102

1::1

'----....---2--'a~

...-----------i[ 203

103

101*2013

Ap·
50k

Rp·
Rp·

50 k

272

580

·Option.

Ap

= 50 k·ohms

or Ap

$100

SA •

>5~k

50 k

201

10(1

Ap·~

50 k.

~

~

_ I_ _ _

= 2 k·ohms.

700<
1.34 k

1.34 k

Y01
700

Y02

o

VEE

1 -8: MECL III Master-Slave Type 0 Flip-Flop (MC1670j

~~O

•

1.34 k

1.34 k

Flip-Flop Operation

1Q lOis in a high state. This is reflected in the emitter of 1QI 0, and in turn is
transferred to the base of 1Q6. 1Q6 is biased for conduction but, since there is no
current path, it does not conduct.
Now assume one of the clocks goes high. As the clock signal rises, transistor
1Q2 turns on and transistor 1Q3 turns off. This provides a current path for the
common-emitter transistors 1Q5, 1Q6, 1Q7, and 1Q8. Since the bases of all these
devices except IQ6 are in the low state, current flow is through IQ6. This maintains
the base and emitter of lQll low, and the base and emitter of lQlO high. The high
state on 1Q lOis transferred to 2Q4 of the slave section.
As the clock continues to rise 2Q2 begins to turn on and 2Q3 to turn off.
(Reference voltages in the master and slave units are slightly offset to insure prior
clocking of the master section). With transistor 2Q2 conducting and the base of 2Q4
in a high state, the current path now includes 2Q2, 2Q4, and resistor RC3. The
voltage drop across the resistor places a low-state voltage on the base of 2Q 11, and
therefore on the emitter, of 2QIl. The lack of current flow through RC4 causes a
high-state input to the base of 2Q 10. Finally these states are fed back to the latch
transistors, 2Q6 and 2Q7 and appear on the Q and Q outputs.
As the clock voltage falls, transistor 2Q2 turns off and 2Q3 turns on. This
provides a current path through the latch transistors, "locking in" the slave output.
In the master section, the falling clock voltage turns on transistor 1Q3 and
turns off 1Q2. This enables the input transistor 1Q4 so that the master section will
again track the D input.
A separation of thresholds between the master and slave flip-flops is caused by
R8. The current through this resistor produces an offset between the thresholds of
the transistor pairs 1Q2/l Q3 and 2Q2/2Q3. This offset disables the D input of the
master flip-flop prior to the enabling of the information transfer from master to
slave via transistors 2Q4 and 2Q9. This disabling operation prevents false
information from being transferred directly from master to slave during the clock
transition, particularly likely if the D input changes at this time. The offsetting
resistor, R8, also allows a relatively slow-rising clock waveform to be used without
the danger of losing information during the transition of the clock.
Both set and reset inputs are symmetrically connected. Therefore, their action
is similar although results are opposite. As a logic 1 level is applied to the S input
transistor, 1Q2 begins to conduct because its base is now being driven through 1Q 19
which is in turn connected to S. Transistor IQ5 is now on, and the feedback devices
1Q6 and 1Q7 latch this information into the master flip-flop. A similar action takes
place in the slave with transistors 2Q2, 2Q5, 2Q6, and 2Q7.
MECL Family Comparison
A list of MECL circuit characteristics is tabulated in Figure 1-9. The various
families are compared with respect to both features and performance. Because of the
speed difference between the 10, 100 series and 10,200 series, these products are
given separate columns. The following paragraphs describe the MECL characteristics
in the order of Figure 1-9. Differences between standard and military products are pointed
out when significant.
1... Introduction year relates to the first year product was introduced. Several
years are normally required to fill a product line and work continues to update
MECL with new LSI, memories, and logic.
2... All MECL circuits incorporate internal VBB bias drivers. The bias circuits are
designed to operate over a wide range of temperatures, supply voltages, and circuit power
14

The MECL Families

dissipation. All MECL parts have the same logic level and threshold voltages regardless of
power dissipation. The M 10800 and MECL lOKH families feature a voltage compensation network that holds logic levels constant with supply voltage.
3... MECL lOKI lOKH and MECL III circuits feature open emitter outputs for easy
interface to terminated transmission lines. The MC1648 VCO is an exception and can be
used without an external resistor.

1-9: MECl Family Comparison
MECL 10,000 (10K)
FEATURE

MECL 10KH

10,100

10,200

10,500

10,600

10,800

MEeL III

1. Year Introduced

1981

1971

1973

1976

1968

2. Bias Dnver

VC.*

10,000

10,000

VC*

10,000

3 Output Pulldown ReSistors

No

No

No

No

No

4. Input Pu"down Resistors

Yes

Yes

Yes

Yes

Yes

5. MaXimum Input D.C
Loading Current
6. Specified Ouput Current

265/lA
",,22mA

2651lA

41O/lA

350/lA

350llA

50mA

"'22mA
50mA

"'22mA
50mA

""22mA
50mA

"'22ma
40mA

7. MaXimum Output Current

Yes

Yes

Yes

Yes

Yes

83
2.9 pf

54

63

10 Input Capacitance

83
29 pf

3.3 pf

68
33 pf

11. Output Impedance

7 ohm

7 ohm

70hm

70hm

50hm

12 Gate Progration Delay
(typical)

1.0 ns

2 ns

15 ns

1-25 ns

1 ns

8 Transmission Line
Dnve
9. DC Loading Fanout

13. Gate Edge Speed (10 to
90%)
14. Flip-Flop Toggle Speed (min)
15 Gate Power

18 ns

3.5 ns

1 ns

125 MHz

25 ns
200 MHz

35 ns

250 MHz

N.A

500 MHz

25mW

25mW

25 mW

23mW

60mW

16 Open Wire length (less
than 100 mV undershoot)

3"

6"

3"

17 Wire-wrap Capability

Yes

Yes

Yes

6"
Yes

No

18 Use of senes damping
Resistors

Yes

Yes

1"

Yes

Yes

Yes

19 Separate VCC Inputs
20 Speed-Power Product

Yes

Yes

Yes

Yes

Yes

25 pJ

50pJ

37 pJ

4.6 pJ

60pJ

21 Wire-or Capability
22. Fu" Military Temp. Range

Yes

Yes

Yes

Yes

Yes

TBO**

Yes

Yes

No

23 Flat Package

SpeCial

Yes

Yes

No
Yes

Yes

Yes

Yes

No
Quit

24 OuaHn-Llne Package

Yes

* Voltage compensated
** To be determined

4 ... All MECL single-ended inputs have internal (typical 50 kf!) input pull down
resistors. This simplifies wiring since unused inputs can be left floating and assume a
solid logic 0 VOL state. Differential devices such as line receivers and the MECL to
TTL translator do not have input pull down resistors and should be connected as described
on the individual data sheets. (Does not apply to MC12000 Series.)
15

Comments Regarding MECL Features

5 ... Maximum input DC loading current is specified on individual circuit data
sheets. The numbers here apply to a single input of a basic gate. If a package input
goes to more than one point in a circuit, such as a gate strobe line would, additional
current may be required.
Calculating the input current, lin, for MECL IOK/IOKH with a worst-case input
resistor value of 30 kQ (Rin) gives an input resistor current of:

143 pA

where: VR

voltage drop across the input resistor, Rin, with
a logic 1 input,
-5.2 V supply voltage,
-0.9 V (a typical logic 1 level).

The typical 50 kn value will use slightly less current, but either resistance value
is very high compared to the output circuit impedance or the line impedance.
6-8 . . . Output voltage levels are specified at currents representative of circuit
operation. MECL IOK/IOKH and MECL III are designed to drive 50 ntransmission lines
terminated to -2 Vdc (measured from Vee). The current, ITT, required by the line
termination is:

- VTT -V I _ (-2.0 + 0.9) V - 22 A
IT T - m .
Zo- - - 50 Q
Consequently, the outputs are specified with 50 ohm loads. The 50 ohm load
is a worst-case specification and does not require that system design be restricted to
50 Q transmission lines. MECL IOK/IOKH works well over a range of 50 to 120 ohm
environments. Full military MECL 10,500 and and 10,600 series are limited to 100 ohm
(11 rnA) loads.
The maximum permissible output currents of 50 rnA for MECL IOK/IOKH and 40
rnA for MECL III insure a good safety margin over the specified currents.
9... The dc loading fanouts for MECL IOK/IOKH and MECL III are computed by
dividing the output current by the input current. However, both ac limitations and
current needed in the transmission line termination can be expected to restrict the
system fanout to a smaller number than the one computed.
10 . . . Two techniques are used to measure circuit input capacitance. One
method uses an impedance meter, such as the H.P. 4815A RF Vector Impedance
Meter, to measure impedance and phase angle. The other technique .uses a time
domain refIectometer (TDR) to measure the effect of capacitance on the impedance
16

Comments Regarding MECL Features

of a transmission line. (The mathematical relationships used to calculate input
capacitance from TDR data are presented later in Chapter 7). Although small, the
input capacitance will affect system rise time and transmission line propagation
delay as a function of fanout at high MECL speeds.
11 . . . DC output impedance can be calculated from measurements of the
output voltage as a function of output current: Z = Il V/ Ill. The gate output impedance must be much lower than the line characteristic impedance in order to provide
full MECL signal levels when driving transmission lines. The output impedance
(resistive load) is the parallel value of the output transistor and pull down resistor. It
should be noted that capacitance charging rate during a negative transition is limited
by current flow through the pull down circuit.
12-13 . . . Gate propagation delay, edge speed, toggle rate, and power dissipation are standard data sheet information. Propagation delay (tpd) is measured from
the 50% amplitude point on the input signal to the 50% amplitude point on the output signal. Normally the edge speed given is measured between the 10 and the 90%
amplitude points on the output signal. However, because of the amount of rounding
on the upper 10% of the MECL lOKI lOKH edges, these families are specified with 20 to
SO% edge speeds for easier correlation. Nevertheless, 3.5 ns is a typical 10 to 90% figure for
MECL 10K and I.S ns is a typical 10 to 90% figure for MECL lOKH.
14 . . . Toggle speeds are minimum rates for the flip-flops in a family. For
MECL III the 500 MHz shown is for the MC 1690 D flip-flop. The family has divide
by 4 prescalers which operate at 1 GHz.
15 ... Gate power for the MECL lOKI lOKH and MECL III gates is specified with
open emitter outputs, as is usual with most ECL product lines. The wide variety of output
loads - both resistors used with transmission lines and pull down resistors - makes a
power specification under load difficult to define. In a system, the output power is added to
the gate power to find total power.
16-17. . . Open wire length and wire wrap usage are a function of edge speed
and the propagation velocity of the wire. The distances shown are maxima, selected
to give less than 100 m V undershoot at the receiving end of the line with a fanout of
one. Additional information on line driving is found in Chapter 3. Wire wrap may be
used with all families but MECL III. The 1 ns edges associated with MECL III cause
too much reflection from the wire wrap connection to permit practical use. The
open wire maximum line lengths still apply when using wire wraps, unless some form
of resistor damping or line termination is used.
18 . . . Damping resistors consist of small resistors (5 to 75 ohms) that are
placed in series with a line at the output of the driving circuit to extend the permissible line length. The resistor provides a closer match between the line and the
output impedance of the circuit than a direct connection. This match limits overshoot and ringing, and allows the use of line lengths somewhat greater than twice the
non-damped lengths.
19 ... Separate VCC inputs (VCCl, VCC2) are characteric ofMECL lOKI lOKH and
MECL III. The separate VCC pins are used to minimize any crosstalk between circuits in a
package which might occur with the high switching currents when driving transmission
lines. Separate VCC lines do not affect using the parts and only require that two package
17

Comments Regarding MECL Features

pins be connected to a single ground plane or ground bus. A few MECL lOKI lOKH parts
such as the MClO186 and the MClOH186A have only 1 VCC pin because the function
requires 14 II 0 pins. These circuits keep VCCI and V CC2 separate on the chip and use
two bonding wires to the common VCC package pin.
20 ... Speed-power product is a measure of a logic family's efficiency. Propagation delay (nanoseconds) is multipled by the gate power dissipation (milliwatts)
to get a measure of efficiency in terms of energy (picojoules). It is interesting to
note that gate efficiency has improved with each succeeding logic line introduced.
The speed-power product is slightly inaccurate because power figures are used which
do not include output loading (discussed previously). However, TTL speed-power
products can be inaccurate also as they are generally computed for the circuits
operating at a low rate. Such figures would be much worse for circuits operating
near top switching rates. Gate power and speed-power for the M10800 family are
calculated by dividing the number of equivalent gates in a logic function by the circuit power dissipation. The numbers are averages for the LSI circuits rather than
any specific gate. Internal gates use less power than output gates with 50 line drive.
21 ... Wired-OR is a technique used with all MECL circuits to obtain the logic
OR function by connecting circuit outputs together. When several (more than 5)
circuits are connected with Wired-OR outputs, it is possible to get a noise spike on
the output if all gates are at a I output, and all gates but one are simultaneously
changed to a logic 0'. The noise spike is due to the one gate suddenly having to
source the output current previously supplied by the other circuits. The pulse width
is normally less than the gate propagation delay and of insufficient amplitude to
propagate in the system.
22-25 . . . The remaining family features are self-explanatory. Packaging and
temperature range for MECL lOK/lOKH are based on initially introduced circuits. Other
configurations are being investigated to meet future requirments.

lR

UsingMECL
The design guidelines presented here are intended to assist the MECL user to
apply MECL families in a system. The rules listed have been tried out in complete
systems with good results. As rise times become less than 3 ns, special design rules
must be followed. For rise times of 1.5 ns or shorter, designing with transmission
lines is necessary.
MECL lOKI lOKH and MECL III logic families are treated separately because of the
differences in their capabilities and design techniques to be used. Reasons for the rules,
methods for applying them, and test data are found in the following chapters under
associated subjects. MECL lOK/lOKH may be used with or without transmission lines
and termination techniques. Rules for both design approaches are covered separately.
Terminated transmission lines are recommended for large printed circuit boards and larger
systems having several circuit boards.
1. MECL lOK/lOKH without terminated lines

MECL lOKI lOKH family of integrated circuits is designed to provide high circuit
speed without putting a premium on special system layout techniques. This feature
simplifies design with the emitter coupled logic family because most of the techniques used
with high-speed TTL apply to MECL lOK/lOKH .The ability of MECL lOK/lOKH to
interface with MECL III enables very high-speed systems to gain power economy, eased
design rules, a large choice of logic functions, and lower system cost.
MECL 10K rise, fall and propagation delay times are typically each 2 ns. However,
since rise and fall times are measured at 20-80% and are typically 3.5 ns 10-90%,
transmission line techniques are not mandatory. The 10-90% rise and fall times of MECL
lOKH are typically 1.8 ns, and are 1 ns 20-80%. Standard double-sized circuit boards and
backplane wiring with ground planes are commonly used with MECL 10K/lOKH.
Because of the wide variety of MECL lOKI lOKH system sizes and interfaces, not all
techniques will apply to every system. The designer should use these rules as guides,
modifying them sensibly as required for a particular system.

A. Logic Design Considerations

1. MECL rise, fall and propagation delay times are a function of fanout and
capacitive loading. Figures 2-1 through 2-8 show the reduction in speeds with load placed
near the output pin. Consequently when MECL lOKI lOKH is operating near its upper
speed limit, fanout should be restricted as indicated by the curves. Because of the emitter
follower outputs, fall time and propagation delay to a level is more affected by capacitive
loading than rise time and propagation delay to a 1 level (note that the curves in Figure 2-4
are steeper than those in Figure 2-3).

o

19

M EeL lOKI10KH Parameters versus Loading and Temperature

2-1: Rise Time versus Loading and Temperature (MECL 10K)
(50 ohm load)

50

4.0
-30°C

C/O

S
w
~

*
0

l- e.;> 30

w
~

0

~

N

a:
......

~

f

t~
250C

&

=

850C

2.0

1.0

o

10

20

30

o

2

4

6

40
70
50
60
LOAD CAPACITANCE (pF)

80

90

100

14

16

18

20

8

10

12

FANOUT

2-2: Rise Time versus Loading and Temperature (MECL 10K)
(50 ohm load)
50r-----~----~------r_----~----~------~----~----~------~----,

4.0~----~----~------~----~----~------~----~----~

__~~~~--~

CII

.s

w

~'o'!-

I- 0

~ ~ 3.0~----4-----~------~----~----~~~~~----4-----~------~----~
~o

-

«
-'

4.0~----~----_+------~----~----_4------+_----~~~~~~--~==--~

w
0

.

Z

0
I-

«
1.9
«
ll.

.5.
w 3.0~----~------1--~~~~~~+------r------1-------+------+------r----~
~

l-

0

a::

Il.

+-

2.0~-----r----~r------r------1-------r----~r-----~------1-------r----~

-0
...0.

1.0~

o

____

~

10

____

~

______

20

~

_____ L_ _ _ _
40

30

~_ _ _ _ _ _L __ _ _ __ L_ _ _ _~~_ _ _ _~_ _ _ _~

50

60

70

80

90

100

14

16

18

20

LOAD CAPACITANCE (pF)

o

2

4

6

8

10

12

FANOUT

2-4: Propagation Delay, tpd-, versus Loading (MECL 10K)
and Temperature (50 ohm load)
5.0~----~----~------~----_r----~------~----~----~r_----~----_,

>-

«

4.0

-'
w
0
Z
0
l-

«
1.9
«
Il.
0

.
e

w 3.0
~

I-

a::

Il.

i

-0
...0.

2.0

1.0~----~----~----~----

o

10

20

30

o

2

4

6

__ ____ ____ ____ ____ ______ __
70
100
40
90
60
80
50
~

~

~

~

~

~

~

LOAD CAPACITANCE (pF)

10

8

FANOUT

21

12

14

16

18

20

M EeL lOKI10KH Parameters versus Loading and Temperature
2-5: Rise Time versus Loading (MECL 10KH)
(50 ohm load)

50

Iii

.s

4.0

~8

i=a;>
wo
cn N

3.0

a:

.=2.0

1.0

l...----" ~
o

10

~

20

~

30

~

40

~

50

~

60

~

~

80

70

~

90

100

LOAD CAPACITANCE (pF)

2-6: Fall Time versus Loading Capacitance (MECL 10KH)
(50 ohm load)

6.0

50
w

~*

4.0

1-0
...JCX>
...J '

<{o

u. N
~

3.0

2.0

1.0 0

------

V
:/

10

20

V
30

V
40

V

50

V

60

LOAD CAPACITANCE (pF)

??

~

70

/

80

~

90

~

100

MECL lOKllOKH Parameters versus Loading and Temperature
2-7: Propagation Delay. tpd+. versus loading (MECl10KH)
(50 ohm load)

4.0

~

3.0

w
0
Z

0

Cii"

.s

~
<.!) w

2.0

+'t:J

1.0 .....

~

~ f=
0
a:
a..
....0.

o

-----

~

10

~

20

30

40

50

60

70

80

90

100

LOAD CAPACITANCE (pF)

2-8: Propagation Delay. tpd-. versus loading (MECl10KH)
(50 ohm load)

4.0

~

w

3.0

0

Z
0Cii"

~.s

<.!)w

~~

~

2.0

01-

a:
a..
I
't:J

....0.

./

10

/

~

~

~

~

~

~

""",-.--

"""""

""'"

o

10

20

30

40

50

60

LOAD CAPACITANCE (pF)

23

70

80

90

100

MECL lOKllOKH Logic Design

2. Fall-time and tpd- may be improved by using a smaller load resistor
between the output and -5.2 Vdc. A 240 n resistor will cut the delay caused by
capacitive loading nearly in half. Load resistors less than 180 n should not be used
because the heavy load may cause a reduction in noise immunity when the output is
in the 1 state, due to increased output emitter-follower VBE drop. Normally 510
n load resistors provide a good speed-power system design.
3. When driving flip-flops at high speed, clock driver circuits such as the MC1021O,
MC10211, MCIOH21O, MCIOH211 or MECL III gates should be used. MECL III gates
such as the MC1660 or MC1662 can provide the bandwidth necessary for clocking several
flip-flops at once - as in a shift register or synchronous counter operating at high speed.
4. When driving a long string of flip-flops at speeds lower than 80 MHz
(clock), two gates may be operated in parallel for additional drive. The MCIOllO or
MelOll1 is useful in this application since its multiple OR or NOR outputs may be
wired together.
5. The high operating speed of MECL and the effect of loading on propagation
delay must be considered when parallel circuits converge at one point, as shown in
Figure 2-9. Unequal delays along paths A and B can result in momentary outputs at
point C, each lasting a time equal to the propagation delay difference between A and
B. This can be compensated for by additional timing in the form of a strobe, or by
adjusting the fanouts along A and B. If possible, unused gate inputs can be paralleled
to simulate a larger fanout where required; otherwise a small capacitor can be
substituted for the needed fanout (about 5 pF per gate input is recommended).

2-9: Parallel Signal Paths

A

c
B

Under heavy loading, propagation delay along path A will be less than along
path B because of the use of OR outputs in A as opposed to the NOR outputs in B.
This difference (Figure 2-10) is due to the effect of loading on the fall time, rather
than being due to a timing difference between OR and NOR outputs. As a matter of
fact, under light loading, propagation delays for both. NOR and OR outputs are
identical.
When designing clocks for high-speed flip-flops, these timing differences become
increasingly important. For example, the MCI0231 flip-flops can toggle on a 2.5 ns
pulsewidth clock, consequently timing chain skewing in the order of 2.5 ns can
cause false operation.
24

M EeL lOKllOKH System Layout
2-10: Propagation Differences
Input

_________________/

A~

2

3
Input

B
4

5
6

B. System Layout Considerations

1. System grounding and propagation delays in interconnecting leads are
factors to be considered before laying out a system. Depending on the type of wire
used, the wiring propagation time of a signal can greatly affect overall system speed.
In normal backplane wiring it is realistic to expect a 2 ns per foot delay. Propagation
delay is less in coaxial cable, but more for signal conductors in a multilayer circuit
board.
2. System sections such as shift registers and synchronous counters should be
on one card. Propagation delay between shift register clocks on separate boards can
cause erroneous operation. Where timing is critical, equal length clock lines (to
shift registers or other circuits on separate cards) should be run from a common
clock to the card connectors. Such lines will also help limit overshoot and ringing
(discussed further in section D. ·'Backplane Wiring").
3. The Wire-OR capability of MECL can be a powerful tool for reducing
power, propagation delay, and package count. However, since the Wire-OR connection switches current when in operation (8 rnA for a 510 ohm pulldown resistor),
long interconnect lines can cause voltage transients due to signal line propagation
delay. It is recommended that Wire-OR outputs be kept within a package or between
nearby packages. Wire OR between circuit boards should be avoided except for bus
lines where only one output goes high at a time. Large number Wire-OR ties can
cause a loss of low-level nQise margin because all outputs supply current to the pulldown resistor. A good rule is to limit the Wire-OR number to an average of 1 rnA per
output (6 outputs for 510 ohm pulldown, 8 for 390 ohms, 10 for 330 ohms, etc.).
4. Sections of a system where high fanout may be necessary (such as adders
with lookahead carry) should be kept on one card. Signal path length should be
reduced as fanout is increased to minimize both line delay and reflections.
25

MECL lOKI lOKH Circuit Boards

C. Circuit Board Layout Techniques
1. The size of a MECL system circuit board is not restricted by the logic family.
System requirements should determine card size. Terminated transmission line
techniques should be considered for circuit boards larger than 6 by 8 inches.
2. Standard double-sided circuit boards with a good ground distribution may be used
with MECL lOK/lOKH. A low impedance ground is necessary since any noise on the
ground line may be coupled into signal lines. Also, any voltage drop across ground will
subtract from the noise immunity of the MECL circuits. Grounding techniques are
discussed at length in Chapter 5 "Power Distribution".
3. As with TTL, bypass capacitors between ground and -5.2V should be used
with MECL. A 1.0 pF capacitor should be located on the board at the power supply
inputs. Bypass capacitors, 0.01 to 0.1 pF, should be connected once every four or
five packages. When breadboarding or using MECL lOKI lOKH without a good ground
plane, a 0.1 pF bypass capacitor should be used for every two packages. RF quality
capacitors (low inductance) are recommended because of high-circuit speeds. Unlike
TTL, MECL does not have large current spikes during switching. A 510 ohm pulldown
resistor requires 8 rnA for a logic 1 and 6 rnA for a logic 0 or a delta of 2 rnA
switched current. The function of the bypass capacitors is to supply the small
switching current of the pulldown resistor, circuit input capacitance, and circuit
board stray capacitance, thus preventing spikes on the power leads.
4. As with any high-speed system, signal lines should be kept as short as
possible to minimize ringing and overshoot, as well as to simplify timing considerations
arising from the propagation delay of a signal along a conductor. Ringing and overshoot are due to the intrinsic inductance and capacitance of the line itself, as well as
lumped capacitance at the end of the line. Intrinsic inductance and capacitance are
reduced by shortening the lines. A graph of recommended maximum line length
as a function of fanout for MECL 10K is shown in Figure 2-11. Since increased fanout adds
capacitance at the end of the line, the line should be shortened as shown by the following
curve. Detailed unterminated signal line length information is found in Chapter 3,
"Printed Circuit Board Connections".

2-11: Recommended Maximum Line Length versus Fanout (MECL 10K)
8

Iii
w

G
6
2

o:r

'"~

4

2

w

..J

~ 2'
~

------r----

o

o

2

6

4
FANOUT

26

8

10

MECL lOKIIOKH Layout Techniques

5. Longer line lengths are possible if a series damping resistor is used. The
resistor is placed at the output of a gate, in series with the signal line as shown in
Figure 2-12. The resistor value depends on the fanout and the required line length.
Resistors under 150 ohms for a fanout of one, or under 30 ohms for fanouts greater
than five, are normally used for damping. Values larger than these produce rise and
fall time degradation and loss of noise immunity due to IR voltage drop in
the resistor.
2-12: Damping Resistor

6. When driving large fanouts, line lengths can be increased by running parallel
leads as shown in Figure 2-13. The distance between the parallel leads is not critical.
2-13: Parallel Signal Paths

This technique should be used for shift register clocks, counter resets, and other high
fanout applications. Of course, for synchronous clock lines, clock skew delays
should be matched. Series damping may also be used with parallel signal paths.
7. With MECL circuits, undershoot ringing on the logic 1 level is critical since
it subtracts from noise immunity. For safe operating margins undershoot should be
held to 100 m V or less.

D. Backplane Wiring
1. A ground screen is a good means for running a ground in the backplane
wiring. A ground screen is made by connecting heavy bus wires to the connectors in
a grid pattern before wiring the signal lines. The ground screen lines are wired both
parallel to the connectors (tying to the connector pins), and perpendicular to the
connectors (contacting multiple ground pins of each connector). This forms a grid
network (cf Figure 5-6) of approximately I inch squares over which signal lines are
then located.
2. Ferrite beads may be used in backplane wiring for longer signal runs. The
recommended line lengths discussed for circuit cards also apply to backplane wiring.
27

MECL IOKIIOKH Backplanes; System Grounds

A ferrite bead on a wire limits rise and fall time to about 7 ns by attenuating the
high-frequency components of the signal. With a bead, lines up to three feet long can
be driven without excessive overshoot.
3. Standard backplane wiring techniques may be used with smaller MECL
lOK/lOKH systems. Both wire-wrapped and soldered connections perform well. Pointto-point wiring is recommended instead of a laced harness, to lessen line length and
reduce crosstalk.
4. For longer signal paths (e.g. between panels or between cabinets) twisted
pair lines are recommended. The twisted pair is connected to the OR and NOR
outputs at the sending end and to an MClO115, MClO116, MCIOH lIS or MCIOH 116 line
receiver at the receiving end. With this technique, long lines (hundreds of feet) have been
driven with no system degradation other than propagation delay down the line.

E. System Considerations
I. A good system ground is required for best performance. All grounds should
be connected to a common ground point - normally near the power supply. All
logic circuits are connected to a circuit ground. All relays, solenoids, motors and
other noise generating devices are wired to a separate ground network connected to
the common ground point. Standard noise suppression techniques should be employed (i.e. diodes across relays, and capacitors across dc motor brushes).
All mechanical parts such as panels, chassis, and cabinet doors should be
grounded with a third ground. A mounting frame is often used for this if good
conduction can be made at points of contact. If some pieces of equipment in the
system are left ungrounded they may carry transient voltages that will interfere with
the rest of the system. The three separate ground systems connected to a common
2-14: Grounding System
Common Point Near Power Supply

Circuit
Ground

Logic Circuits

Relays
and
Motors

Cabinet Doors
and
Chasses

point will eliminate noise on the signal ground (cf Figure 2-14). Heavy ground leads
should be used on large systems to minimize any voltage drop along the ground line
run.
2. Twisted pair lines and line receivers are normally used between sections of a
system unless line lengths can be kept short. Twisted pair lines should always be
used between sections operating at widely differing temperatures (>30°C), or
between sections not connected with a solid ground network.
28

M ECL lOKIIOKH Design Considerations

2. MECL lOK/IOKH Design Rules
The MECL lOKI lOKH family is a high-speed, economical logic family designed to fill
the gap beneath the MECL III family and to meet the requirements for future highperformance systems. The family is designed to drive terminated transmission lines with
impedances as low as 50 ohms and as low as 25 ohms in bus applications with the
MClOl23 and the new MClOH330, MCIOH332 and the MClOH334. Also, increased
circuit complexity is possible due to high component densities and very low-speed-power
products. Finally, the relatively slow edge speeds of MECL lOKI lOKH minimize wiring
constraints on a logic system.
This section contains layout and design guidelines for power distribution,
ground planes, terminations, line lengths, fanout loading, clock distribution, thermal
considerations, and packaging, applicable to MECL lOK/lOKH.

A. General Considerations
1. Standard double-sided plated-through-hole printed circuit boards may be
used with the MECL lOKI lOKH family. However multilayer boards will permit a higher
component density for a given board area. As a result interconnect lengths are
reduced, making the highest speed systems possible.
2. Backplane wire wrapping is also acceptable using commercially available
boards. Rules and techniques will be discussed for interconnection lengths and
terminations as a function of loading.
3. Coaxial cable, ribbon cable, or twisted pair line is normally required to interface between drawers and card racks in a large system. Microstrip lines are normally
required for clock distribution with either series or parallel termination. Series
damping resistors can be used to facilitate driving long, unterminated lines.

B. Printed Circuit Card Layout Techniques
1. For double-sided boards, a ground plane is recommended on one side of the
card. This plane provides a stable ground reference for microstrip transmission lines
on the other side of the board. Such transmission lines will have a characteristic
impedance of less than 150 ohms. If a ground plane is not possible, a ground bus
must be used as part of the layout on the board, to provide a low inductance V CC
line.
2. If possible, run the interconnections on one side of the board in the
direction perpendicular to the interconnections on the other side of the board. (This
works nicely for large boards holding 100 or more packages).
3. The ground plane or bus should be connected to 10% of the edge connector
pins spaced equally apart. This reduces the ground impedance, in turn minimizing
crosstalk - since multiple signals do not have to rely on a single ground return path.
4. The VCC 1 and V CC2 package pins should be connected directly to the
ground plane or bus, as close to the package as possible. Having the two VCC pins and
connecting the collectors of emitter follower outputs to only one VCC pin is designed
to minimize internal crosstalk.
5. The ground for high current devices - relays, lamps, core drivers, etc. should be separate from the logic ground. These high current circuits should be
connected to a separate ground bus on the card and in the backplane. The separated
grounds should be connected at the system ground point.
6. Signal interconnection wires between circuits should be kept as short as
possible.
29

M EeL lOKIIOKH Power, Backplane, and Loading Guidelines

C. Power Supply Bypassing on Circuit Cards

1. A 1.0 IlF bypass capacitor is used on each board at the power supply inputs.
Decouple every 4 to 5 packages with 0.01 IlF to 0.1 IlF RF quality capacitors
(-5.2 Vdc to ground).
2. The power supply ground line noise should be limited to less than 50 ill V
peak-to-peak.
3. Maintain VEE power supply voltage with less than 100 mV difference
among all the logic cards to which signals must interconnect. (This will limit noise
margin degradation to less than 30 m V).
4. Power supply regulation should be better than ± 10% for MECL 10K and MECL
III and ± 5% for MECL IOKH.

D. Backplane and Loading Considerations
1. Wire wrapping techniques are acceptable in the backplane as long as the
interconnection rules are followed.
2. A ground screen or ground plane is recommended in the backplane. This
gives backplane wiring a characteristic impedance of approximately 140 ohms. (This
may vary as much as ±50% depending on distance from the plane and the route
taken). The capacitance of the wire over the ground screen is about 1 pF lin and the
inductance is about 20 nH/in. Parallel terminating resistors, as described in Chapters 3
and 7, may be used to increase line lengths in the backplane.
3. 10% of the card edge connector pins should be connected to the ground plane
or screen to reduce card-to-backplane ground impedance. The lowered ground
impedance resulting from many pins paralleled to ground minimizes crosstalk since
several signals do not have to rely on a single ground return path.
4. The optimum choice for backplane wiring (for maximum line impedance
continuity) is the strip line motherboard technique. In such a case, board
interconnections on the motherboard would follow the same rules as the strip line
circuit card. Strip line techniques will be discussed in later sections (Chapter 3 and
Chapter 7).
5. Series damping resistors can be used to series terminate the interconnect
wires as follows:
a. Ten inches of open wire (with a 600 n output emitter pulldown resistor
connecting to - 5.2 volts) can be driven if a 50 ohm resistor is placed in series at the
sending end. Up to eight loads may be driven using this configuration. Eighteen
inches of line with up to 4 loads may be driven by using a 100 ohm series resistor.
These resistor values will insure that any undershoot will be less than 100 m V.
b. Ten inches of open wire may be driven in series with 10 inches of printed
circuit line (in either order) if a 100 ohm resistor is placed in series at the sending
end. This arrangement can drive up to 4 loads.
6. Three inches of open wiring with a fanout of up to 4 gate loads will produce
less than 100 mV undershoot. A ferrite bead placed in the line will increase the open wiring
length to 15 inches.
7. A damping resistor or acorn bination of series/parallel terminations with
microstrip lines is required when driving flip-flops whenever fanouts exceed 4 and
whenever line lengths are greater than 3 inches.
8. Coaxial cable and twisted pair line are recommended when top speeds and
rock-bottom noise pickup is a "must" for signal paths in a backplane. An alternate

30

M EeL 10K/ lOKH System Rules

approach, ample for nearly all requirements, is to use strip lines or microstrip lines in
a backplane motherboard as in #4 above.
9. Recommended coaxial cables have characteristic impedances of 50-100 n,
and time delays of 1.5 ns/ft.
10. Twisted-pair lines may be made of standard hookup wire (A WG 24-28),
twisted about 30 turns per foot. Such twisted pair exhibits a characteristic
impedance of about 110 ohms.
11. When driving coaxial cables, the printed circuit leads from the driver and
receiver (going to the coax) should be kept as short as possible to reduce mismatch
reflections, unless microstrip or strip line is used.
12. When driving 110 ohm twisted pair, the pair line should be terminated
with a 110 ohm resistor across the differential input to a line receiver (MCI0115, MClOII6,
MC1OH115 or MCIOH116). A 390 ohm puUdown resistor should be connected to each
output of the gate driving the twisted pair.
13. Twenty feet of twisted line can be driven by a MECL lOKI 10K H OR/ NOR gate
at a frequency of 100 MHz, when received by a line receiver.
14. Twisted pair line is recommended for interconnections whenever a
temperature differential of more than 35°C exists between sections in a system.
15. Twisted pair lines are recommended when high switching-current lines are
in close proximity to the proposed signal route or when signals run between drawers
or racks. If common mode noise is greater than 1.5 volts, then shielded twisted pair
is recommended.
16. Inductance and overshoot are reduced if parallel lines are used to fanout to
various loads on different circuit boards in the backplane (this also holds for
interconnections on the circuit card). In this way, a parallel fanout of 4 will produce
very little more overshoot than a fanout of one.
17. Twisted pair lines should be used to distribute clock signals to different
logic boards and drawers in a system.

E. System Distribution and Grounding

1. High switching current lines for core drivers, relays, and motors should be
separated physically from logic lines. (cf Chapter 4, discussion of crosstalk).
2. Avoid bundled parallel runs as much as possible. Signals in bundled cables
produce crosstalk.
3. Signal distribution architecture should minimize wiring delays to permit the
highest possible system clock speed. System clock speeds of greater than 40 MHz
can be obtained in medium size computers.
4. The ground for the high switching current circuitry, should be separated
from the logic ground. All separate grounds should, however, be tied together at one
point - the system ground point. In that way, the ground buses will be at the same
potential but current cannot be looped since they are connected at only one point.
5. The cabinet should be strapped to the system ground point to make it serve
as an electrostatic shield.
6. If the system is in a high noise environment, connect the system ground
point to earth ground with a heavy conductor.
7. All the equipment in a system should be grounded.

31

MECL lOKI JOKH Loading Effects

F. Loading Rulesjor MECL 10KI10KH

1. MECL lOK/lOKH and MECL III are designed to directly interface with each
other over the full range of ambient air temperatures and power supply tolerances.
2. MECL lOK/lOKH and MECL III fanout rules are the same. Minimum output
pulldown resistor loading is 50 ohms to - 2 volts; 10 gate loads (in addition to the
50 n) will reduce noise margin by less than 20 mY. Maximum output pulldown
resistor loading is 100 ohms to - 2 volts. Larger resistors result in a loss of logic f/J
noise margin. See Figure 2-15 for typical output characteristics of MECL lOKI lOKH as a
function of output load current and the value of the output pulldown resistor.
3. It is recommended that output pulldown resistor values of from 270 n to
51Or2(connected to -5.2 V) be used when MECL lOKI lOKH drives MECL lOKI lOKH or
MECL III. Under these conditions 25 MECL lOKI lOKH gate loads or 20 MECL III gate
loads may be driven.
4. MECL lOKI lOKH fall time is primarily a function of the load capacitance and

2-15: Output Voltage Levels versus DC Loading

-0.2
150 n /100 ri/75

Vout.OUTPUT VOLTAGE
(VOL TS)

n~

V

/ I /v 50 n V
-0.6
I'-.
17 [7 V / V 3 5 n / V
/
/ / /
v
-1.0
/ V /v . / .Y
..-<....
77 7 V
-1.4
-2.0
J// /" V
' l l 77'. 7
-1.8
p'"
=
VOH

~

Load Lines
VTT =
V

NOTE:
Load line
impedance is for
parallel
terminated
transmission
line.

VOL-

-2.2
o

4.0

8.0

12

16

20

24

28

32

36

40

lout. OUTPUT CURRENT (mA)

the emitter pulldown resistor. If the emitter pulldown is connected to - 5.2 V, the
fall time is given by:
tf ~ (0.2 RC + 2) ns, (10K)
tf ~ (0.2 RC + 1) ns, (lOKH)
where R is the value of the emitter pUlldown resistor (in kr2) and C is the load
capacitance (in pF). If the emitter pulldown is connected to - 2 V, the fall time is
given by:
tf ~ (1.1 RC + 2) ns, (10K)
tf ~ (1.1 RC + I) ns, (lOKH)

32

M EeL lOKIIOKH Propagation Delay

5. The propagation delay for the output to go negative is also a function of the
load capacitance and the emitter pundown resistor. If the emitter pundown resistor
is connected to -5.2 V, the propagation delay for the output to go negative is:
tpd- ~ (0.1 RC + 2) ns, (10K)
tpd- ~ (0.1 RC + 1) ns, (lOKH)
If the emitter pundown is connected to - 2 V, the formula for the delay is:

tpd- ~ (0.47 RC + 2) ns. (10K)
tpd- ~ (0.47 RC + 1) ns, (lOKH)

6. For computing the signal path delay with either a 50 n emitter pulldown to -2
volts, or 270 n to -5.2 V, propagation delay will increase byO.l ns per gate load (assuming
5 pF per gate load).
7. For all MECL lOKI lOKH series devices, the various propagation delays listed in
the data sheets have been measured with a 50 ohm emitter pundown resistor connected
to -2 volts. Thus, these propagation delays are longer than would occur for a lighter
load condition. Consequently the propagation delays specified on the data sheet are
used to determine maximum delay paths in a system. (Of course as discussed above,
loading will increase the propagation delay and should be allowed for in delay
calculations).
8. Emitter dotting is accomplished by tying two or more outputs together.
This produces a logic OR function in positive logic. A logic AND function results if
negative logic is assigned. For either the 50 n or the 270 Q pulldown, the
propagation delay will increase by 50 picoseconds per emitter dot. For loading
purposes, each emitter dot may be considered as equivalent to 112 a gate load (more
precisely, each emitter dot is equivalent to slightly less than 2 pF of capacitive
loading).
9. The MECL lOKI lOKH circuit propagation delay is unaHected by the intrinsic line
capacitance of an unterminated line. However, overshoot at the receiving end could result
in a slightly faster rise time.
10. The M.ECL lOKI lOKH circuit propagation delay is unaffected by a transmission
line properly terminated at the receiving end. Such lines appear as purely resistive loads.
11. High fanout at the end of a terminated transmission line longer than 1.7 ns does
not increase the propagation delay of a MECL 10K circuit driving the line. Fanout loading
increases the propagation delay of a signal on the line.
12. The delay in signal propagation along a printed circuit line must be taken
into consideration. The basic delay of a signal on either a loaded (resistive loading)
or unloaded printed circuit surface line over a ground plane is about 1.8 ns per foot
or 0.15 nslin for glass epoxy boards. The exact delay can be calculated using the
formula: tpd = ~ LoCo, where Lo and Co are the intrinsic line inductance and
capacitance.

33

MECL lOK/ JOKH On-board Line Lengths

13. The signal propagation delay down the line will increase by a factor of
where Co is the intrinsic line capacitance and Cd is the capacitance
due to loading and stubs off the line:

VI + Cd/Co·

14. The increase in signal delay due to load capacitances should be calculated
for the particular transmission line characteristics. Lines with low characteristic
impedance are less affected because of their higher intrinsic capacitance per unit length.
15. The characteristic impedance of a transmission line is reduced due to load
capacitances by the fact,or
+ Cd/Co. So, the formula for the modified
characteristic impedance, Zo , of a transmission line is:

VI

Z'
o

=

~l + Cd/Co

where Zo is the original line impedance.
16. The maximum line length allowable on the circuit board can be calculated
using the data in Figure 2-16 for printed circuit line resistance.
For lines terminated to -2 Vdc at the receiving end of the line, the signal
voltage drop in the line is:

Ll V Sig

= (2 -RTIVOHI\
\

/

• (line resistance),

2-16: Resistance versus Line Width for Printed Circuit Lines

09
~

0.7

~

0.5

......

0.3
RESISTANCE
PER FT (OHMS)

~Maximum

'"

".S
.......... ~

..........

0.2

.......

t'-..

R

Average R

~

l'<"'. r:--...

......

t'>,...

L?- t'o..."'" k.. :~
~llni~~r;n

0.1

"""r---. 0

R

."""
"- ~
l:! .

.':\'I<,

So.
"'" ...... ........

0.07
0.05 r

r

Material: G-l0 1 oz Cu (Resistance
is approximately 1/2 when using 2 oz. CuI

I

003
3

I
5

I I I II
7

10

I

I
20

I

I
30

LINE WIDTH (MILS)

34

I
50

70 90

MECL III Design: Card Layout

where VOH is the logic I output voltage and RT is the terminating resistor.
Normally this signal voltage drop is small and need not be calculated. For example, 7
feet of IS-mil wide line will have less than 30 mV drop. The maximum length
allowable will be that for which ~ V remains below about 100 m V.
17. The maximum stub length off terminated lines is 3 inches with a fanout of
four gate loads on the stub, (for <100 m V undershoot). Whenever an open line
(stub) is driven by a pulse, the resultant undershoot and ring are held to about IS% of
the logic swing if the two way delay of the line is less than the rise time of the pulse.
For these conditions the maximum un terminated line length may be calculated:

.Qmax (in.)

where tr is the rise time of the pulse. Here tpd is the propagation delay of I inch of
line (cf #13 above).
18. Up to 3 parallel open lines can be driven by one gate, following the rules
given above. Parallel fanout to loads is recommended when possible, since lead
lengths longer than for a single line may then be used. However, a matched
transmission line should be used for driving loads over lines longer than shown in
Figure 3-13. Note that both stubs and terminated lines can be driven by one and the
same gate.
19. If a ground plane is used, longer lines can be driven than if no ground plane
is used; or else the value of a series damping resistor can be reduced. The best
approach for determining the permissible values of resistance, length of line, and
fanout is from the basic equations that are developed in Chapters 3 and 7.

3. MECL III Design Rules
The MECL III logic family is the widest bandwidth standard logic available. This
family is designed to fill the high speed requirements of the communication, or instrumentation system designer. MECL III, like MECL lOK/lOKH , is designed to drive
terminated transmission lines.
Motorola has successfully met the device/package requirements for a 1 ns logic
family. The ability to manufacture very fine geometry devices with reliable
multilayer metallization results in very compact circuitry and makes LSI possible for
MECL; and so, expansion with complex functions operating at higher data rates, lower
power, and smaller size than any other form of logic, has become possible with
MECL. This is a direct result of new processing technologies and the techniques
available to the MECL circuit designer. These techniques include: series gating,
collector dotting, and reducing internal logic swing.

35

MECL III Transmission Line

The ability to process data with microelectronic structures at bit rates of over
200 million per second requires a thorough understanding of device circuit design,
system interconnects, packaging, and thermal management. Specifically, the
necessary compromises and possible trade-offs must be understood. A set of layout
ground rules or guidelines will provide a first step toward this goal.
A. Circuit Card Layout
1. Leave maximum possible spacing among all parallel signal leads to reduce
crosstalk. If two signal leads are run parallel at spacings of less than 150 mils, then a
ground lead placed between the parallel wires will reduce crosstalk. Such a ground
shield will reduce crosstalk from 12 to 7 m V for two IS-mil lines spaced 115 mils
with a 35-mil ground shield centered between. If the ground shield is plated through
to the ground plane every 1/2", the crosstalk will be reduced even further - to
3mV.
2. The choice between two-layer and multilayer printed circuit board depends
upon the maximum operating frequency and the circuit complexity. With clock rates
above 250 MHz, the use of multilayer board is highly recommended. This is due to the
possibility of ground loops caused by the use of ground plane areas as signal paths on
double layer boards. One to three packages, as in a test fixture, may be used satisfactorily
above 250 MHz with two-sided printed circuit board.

B. Transmission Line (Microstrip Line)
1. Avoid sharp bends in transmission lines, to prevent reflections from abrupt
changes in the characteristic impedance of the line.
2. If two sided board is used, Figure 3-7 may be used to determine Zoo
3. For MECL systems the physical width of microstrip lines used leads to
characteristic impedances usually lying between 50 and 120 ohms. To achieve
impedance values greater than 120 ohms, line widths have to be very narrow. This
promotes two problems. One is that as dc series resistance goes up, signal level at the
receiving end of the line is reduced. The second problem is that "etch-outs" or pin
holes exist after etching narrow lines. As a result of various considerations, it happens
that 68 ohms is a wise choice of impedance.
An impedance of 68 n yields the best trade-off between delay time and power
consumption. A 50 n line would consume more power. A higher impedance would
consume less power, but delay time would increase. As a matter of fact, three
impedance levels can serve most applications: 50, 68, and 100 n. A 68 ohm stripline
is a good choice for on-board uses, while 50 and 100 n are used for single ended or
party line drive (respectively) off the board.
4. Line characteristic impedance, Zo, is inversely proportional to the square
root of the line capacitance. Therefore, known values of gate input capacitance can
be used to modify Zo, i.e.:

36

MECL III Oock Distribution On-and Off-Card

Z'o

(ohms),

where Zo is the new effective characteristic impedance, Cd is the sum of the
capacitance due to loads distributed along the line (circuit inputs and stray
capacitance), and Co is the intrinsic line capacitance.
The effect of load capacitances on signal propagation delay time, tpd, is:

t'

pd

=

tpd
--...
Z C
0 a

Pt

Cd
1 +_.
Co

If Cd and Co are in pF, and Zo in k ohms, tpd will be in ns.

These relationships show that load capacitances increase propagation delay and
will decrease the characteristic impedance. Lines with low characteristic impedance
are least affected due to their higher capacitance per unit length.
The one important advantage of transmission lines with proper termination is
that stubs have little effect on line delay times. With a Zo of 50 r2, stubs must be
limited to 1" or less to prevent excessive ringing.

C. On-Card Clock Distribution Via Transmission Lines
1. Use of the OR output for gates used as clock buffers is recommended in
developing a clock chain or tree. A small clock skew may result from using both the
OR and NOR outputs in the chain.
2. Use balanced fanouts on the clock drivers in a tree.
3. Overshoot can be reduced by using two parallel drive lines in place of one
drive line. The effect of this arrangement is to cut the load capacitance per line in
half.
4. To minimize clock skewing problems on synchronous sections of the
system, line delays should be matched to within 1 ns.
5. It is always good practice to use a buffer when driving long lines off the
card. One instance when a buffer is particularly desireable is when Q or Q outputs
from a high frequency counter are also used within the feedback logic of the
counter.

37

MECL III Test Circuit

6. Parallel drive gates are used when high clocking repetition rates are required,
and when driving high capacitance loads. The bandwidth of a MECL III gate may be
extended by paralleling both halves of a dual gate. Approximately 40 or 50 MHz of
bandwidth can be gained with the two (or three) clock driver gates in parallel.
7. Fanout limits should be applied to clock distribution drivers. Four to six
loads should be the maximum load per driver for best high speed performance.
Avoid lumped loads at the end of lines greater than 3 inches long. A lumped load, if
used, should consist of no more than four gate loads.
8. For Wired-OR (emitter dotting), two-way lines are required when connection distance is greater than 1 inch. A two-way 100 n transmission line is prod uced
by terminating both ends with 100 n impedances. Single end termination may be
used when all emitter connections are within -I inch of each other.

D. Off-Card Clock Distribution
1. The OR/NOR outputs of an MC 1660 may be used to drive into twisted pair
lines. At the far end of the twisted pair, an MC 1692 differential line receiver is used.
The line should be terminated. This may be done with approximately 110 ohms
across the differential receiver input.
Alternatively, a 56-ohm resistor from each of the receiver inputs to - 2 V dc will
provide both line termination and puBdown resistance for the MC 1660 driver. This
latter method not only provides high speed board-to-board clock distribution, but
also yields noise margin advantages for the system. That is, the noise margin from
board-to-board becomes independent of temperature differentials, due to the line
receiver operating with differential inputs.
2. MECL III interfaces directly with MECL lOK/lOKH. Use the wiring rules for
whichever family drives the line.

E. Testing MECL III

1. Keep all unshielded lead lengths as short as possible, less than 1/4".
For dual-in-line packages use AMP 16-pin low profile sockets (or equivalent)
which have no long paths from the device under test to the solder pads on the
bottom of the socket.
2. Use small RF quality parts: 1/8 W carbon composition resistors and 0.01 JlF
low inductance disc ceramic capacitors.
3. All input/output connections should be made with good quality miniature
50 n semi-ridge coax, and BNC, GR, or miniature coax fittings.
4. A solid ground plane should be used, with V CC pins 1 and 14 or 16
connected directly to the +2.0 volt plane via the shortest possible path.

38

5. Vee should be at +2.0 volts with VEE at -3.2 volts. The gate under test
should have its output connected to a 3S5/S2-50n sampling plug-in for a Tektronix
568 sampling system (or equivalent). The arrangement shown in Figure 2-17 is
recommended by Motorola for measuring subnanosecond performance.

2-17: Recommended MECl Test Setup

Channel A

Channel 8

All Input and output cables to
the 'scope are eq ual lengths of
50-ohm coaxial cable.

Coax

PULSE
GENERATOR

25J?

39

+

+2.0 V

-3.2 V

Vce

VEE

40

Printed Circuit
Board Connections
Any signal path on a circuit board may be considered a form of transmission
line. If the line propagation delay is short with respect to the rise time of the signal,
any reflections are masked during the rise time and are not seen as overshoot or
ringing. As a result, because of the high ratio of rise time to propagation delay time,
signal lines for most MOS circuits may be several feet long without signal distortion.
However, as edge speeds increase with faster forms of logic, the line lengths must be
shorter in order to retain signal integrity.
Two techniques can be used to enable high speed circuits to operate over
relatively long lines without serious wave shape deterioration. TTL uses an input
clamp for fast negative edges. The energy of the overshoot is clamped at one diode
drop below ground, and this reduces the amplitude of the following undershoot.
The slower positive-going edges are allowed to overshoot, but are damped out by the
relatively high output impedance (50 to 80 ohms) of the circuit in the logic I state.
Also, greater noise immunity in the I state makes any undershoot less critical.
The disadvantages of the TTL technique show up at higher bit rates and faster
edge speeds when fanouts along the line are used. Since the reflections are present in
the lines, they will tend to combine at high bit rates to cause signal distortions and
loss of noise immunity.
Consequently, MECL uses another approach for handling reflection problems:
matching the impedance of the line. In this way, reflections are controlled and signal
integrity is maintained.
This chapter discusses circuit interconnections as transmission lines, with the
open line treated as an unterminated line. Although MECL III is the only family
with a strict requirement for a transmission line environment, it is expected that
most MEGL lOKllOKH users will use matched impedance lines to improve interconnection distances and signal purity.
Circuit designers have a choice between transmission lines and conventional
interconnect wiring when the distances between MECL devices are short, less than
the lengths in Figure 1-9, #16 or when the rise times are greater than 3 ns. The
design decision must be made after thorough analysis of the system requirements.
Incorrect selection of conventional interconnect wiring could result in false system
operation due to a high percentage of incident pulse reflections and subsequent
lowering of the ac noise immunity.
In many cases where MECL devices are used, transmission line techniques are
advantageous. When using MECL devices with rise times less than 3 ns, transmission
lines are highly recommended. The basic factors which will affect this decision are:
A.
B.
C.
D.
E.

System rise time
Interconnect distance
Capacitive loading (fanout)
Resistive loading (line termination)
Percentage of undershoot and overshoot permissible
(reduction in ac noise immunity).
41

Overshoot and Undershoot On Open Wire 1 ine

The result of analyses shows that transmission lines should be used if the
percentages (E, above) exceed the acceptable design goal. A general rule of thumb
that can be used is that undershoot should not exceed 10%, and overshoot should
not exceed 35% of the logic swing. The 35% overshoot limit keeps the input out of
saturation and the 10% undershoot is less than 100 m V loss of noise margin.
Actually, most MECL circuits can tolerate up to 30% undershoot.
An example of a MECL 10K device driving an 8-inch open wire is shown in Figure
3-1. The oscilloscope traces, for the 8-inch open wire without a ground plane, taken at
3·1: Overshoot and Undershoot With an Open Wire Line

PULSE
GENERATOR

-2.0 Vdc

(a) Test Arrangement

(b) Ground Plane Not Used

Vertical Scale = 400 mV/cm
Horizontal Scale = 20 ns/cm

-

I . .1 Gate
I
i': Receiving
\

Input A

i\
, \. II"'\.
I

•

I
I

,

I

I

~

\ -

(e) Ground Plane Added
\

r--- :--t

Receiving Gate
Output ~

_\..

Low

'r

High

I
I

Vertical Scale = 400 mV/cm
Horizontal Scale = 10 ns/cm

42

Advantages of Transmission Line

points A and B are shown in Figure 3-1 (b). Trace A shows an overshoot condition of 60%
and an undershoot of 40%. It can be seen how this undershoot condition affects trace B
during the low level period of the signal - a small spike is produced.
By way of contrast to the open wire circuit, a ground plane is added and the
trace shown in Figure 3-1 (c) is obtained. The addition of a plane reduces overshoot
and undershoot to about 40% and 20% respectively.
Figure 3-2(a) shows an 8-inch transmission line correctly terminated. The scope
traces in Figure 3-2(b) indicate the marked advantages of using transmission lines
correctly tenninated.

3-2: Matched Transmission Line Wave shapes

.----P-U-L-S-E----..RYMC10109

.JI:"jj:C1 01 0°}-9_".j .

I",,--!
' __

GENERATOR

-

~~
r-L--/

50 ohm
Transmission Line

50
()

-2.0 Vdc

P_ut_

:.-

50

)

-2.0 Vdc

(a) Test Configuration

L

- ReLiVi
Gale
Input

--+--+--+--+--+---1----1

I

\

(b) Input and Output Waveforms

'"

(
Receiving Gate
f-

0 utput

~

I

--+--+--+---+--+------1----1

11 1
Vertical Scale
.= 400 mV/cm
Horizontal Scale = 10 ns/cm

Transmission Line Geometries
Figures 3-3 through 3-6 show some of the types of transmission lines than can
be used for interconnecting high speed logic systems. Details concerning each type
are elaborated in the following paragraphs.
43

Types of Transmission Line

Coaxial Cable and Twisted Pair
Figure 3-3 shows a twisted pair line and the cross section of a coaxial cable
transmission line. Some common types of coaxial cable have characteristic
impedances of 50, 75, 93, or 125 ohms. Twisted pairs can be made from standard
hook-up wire (AWG 24-28) twisted about 30 turns per foot. Such twisted pair has a
characteristic impedance of about 110 ohms. Coaxial cable and twisted pair are
recommended for long line lengths in the backplane.

3-3: Coaxial Cable, Twisted Pair

Wire Over Ground
Figure 3-4 shows the cross section of a wire over a ground. The characteristic
impedance of the wire is

=

Z

o

60 In(4h) ,

~

d

where er is the effective dielectric constant surrounding the wire. The wire over a
ground plane is most useful for breadboard layout and for backplane wiring. The
characteristic impedance of a wire over a ground plane in the backplane is about
120 ohms, although this may vary as much as ±40% depending on the distance from
the plane, proximity of adjacent wires, and the configuration of the ground.

idi

.

~

h

~

3-4: Wire Over Ground

vl"7""""::z.....z//'z-:;z.....z//'z-:;/.....///'/-:;/...../-r--,z'""'1J

G rou nd

Microstrip Lines
A microstrip line (Figure 3-5) is a strip conductor (signal line) separated from a
ground plane by a dielectric. If the thickness, width of the line, and the distance

t ~

3-5: Microstrip

.-t

Dielectric

f

0 0015" for 1 oz. Cu,
0.003" for 2 oz. Cu.

h

~~~~~~~~
Ground
L.....:...""':""""':""""':"""':""""':""""':"""':""""':""""':"-"--<:..-LJ

44

Microstrip Line Parameters

from the ground plane are controlled, the line will exhibit a predictable characteristic
impedance that can be controlled to within ±5%.
The characteristic impedance, Zo, of a microstrip line is:
87

In( 5.98h ) ,
0.8w + t

where:
e r = relative dielectric constant of the board material
(about 5 for G-I 0 fiber-glass epoxy boards) ,
w, h, t, = dimensions indicated in Figure 3-5.
The signal line is made by etching away the unwanted copper using photo resist
techniques. The characteristic impedance of microstrip lines for various geometries is
plotted in Figure 3-7. These values were calculated from the mathematical relation
above and closely agree with experimental time domain reflectometer measurements.
In fact, the equation proves to be very accurate for ratios of width to height between
0.1 and 3.0 and for dielectric constants between 1 and 15.
Figure 3-8 shows curves for the microstrip capacitance per foot as a function of
line wid th and spacing.
The inductance per foot may be calculated using the formula:

where:Z o
Co

characteristic impedance,
capacitance/ft.

The propagation delay of the line may be calculated by:
ns/ft .
Note that the propagation delay of the line is dependent only on the dielectric
constant and is not a function of line width or spacing. For G-IO fiber-glass epoxy
boards (e r == 5.0) the propagation delay of the microstrip line is calculated to be
1.77 ns/ft.
Strip Line
A strip line (Figure 3-6) consists of a copper ribbon centered in a dielectric
medium between two conducting planes. If the thickness and width of the line, the

3-6: Stripline
h

r t
45

Impedance and Capacitance Data for Microstrip Line

3-7: Impedance versus Line Width and Dielectric Thickness for Microstrip Lines
140

"-

120 :\.

"I\....... 1'-....

100
80
Z. IMPEDANCE
(OHMS)

I\"

..........

. . . . i"--.

..........

['..

. . . r--...

t\.

r-

.......... 1'-..

40

I"-

r-..... r-.....

I

20

20

30

40

.......

0.0015"

50

I

_

Thick~esf' h_

..........

..........

. . . . 1"-

r-....

10

--

i'r-..,

[\-..

o

Dielectric

......... r--....

.......... ~

r\

60

1 oz. Cu; t = 0.0015"
Surface Conductors. _I
G-10 Material; e r = 4.7

"-

-- ---- - --~.

0.100" - I - -

I--t J

- --

60

......,

70

80

ob3ci"-,
"

90

rI--

I--

100

110

LINE WIDTH (MILS)

3-8: Capacitance versus Line Width and Dielectric Thickness for Microstrip Lines
140

_11111111

120 _

1 oz. Cu; t = 0.0015"
Surface Conductors.
G-l0 Material; e r = 4.7
Dielectric - Thickness. h- -

100

CAPACITANCEI FT
(pF)

I I I

80
O.OlS"

60
40

. /V

- -~

20

o

V

Vi-"'"

10

20

,/

I-- ...-

30

I-- ~

-

-I-- I--

l- b.oho·
........

SO

60

70

80

LINE WIDTH (MILS)

46

-

-

0.060"

0'1
40

~

-

90

1O

100

?"
110

Impedance and Capacitance Data for Strip Line

3-9: Impedance versus Wire Width and Spacing for Strip Lines
140

I

I

I

I

II. I

I

1 .1.

1 oz. Cu; G-10 Materral; e r == 4.7
_
Spacing == Separation Between Strip
Line and Ground Plane
-

130
120
110
100
90 1\

Z, IMPEDANCE
(OHMS)

Spacing

1\'\

80

I

k"0.050"
70 ~ ~
~ r" ~ ~ J..-0.040"
60
.........
r---........ j'--... r--. J'0.030"
~ ""
50 ~ ~
.........
r- r-r~ ~ ~ -... j'--... b i-40
r-rr-- r-- r~
t'---.. j'--... t-......
r-- ~ I--t-30
"""'"

-

~

0.010"'/
~

20

L

0.013"'/
I

10

o

r'-- ~

- r--

~

~ t-~ t- t'"-:-f .......

r-

°r,.7

I

5 10 15 20 25 30 35 40 45 50 55

60 65 70 75

LINE WIDTH (MILS)

3-10: Capacitance versus Line Width and Spacing for Strip Lines
160
150
140

1 oz. Cu; G-1 0 Material; e r = 4.-,
Spacing = Separation Between
Strip Line and Ground Plane

~

I

130
120

I

110

0.010" L

100

'I'

V

CAPACITANCE (pF)
90

V

V
1/

/
L

~

/~

V

L/0.013"

V

1/ V

80

/

Spacing

,/'

V """"V
/V
V"
/
,.....,. I""'"

....... Va.020"

V

/

70
60

V

..........
/ / . /V
50
'.-'
V
/~
. /V ~
40
~
~~~~
30 ~ ;.....-20

I

--

V

..-!--

~~

~

---

,.....,.
~30"

~
0.050"

~

5 10

15 20 25 30 35 40 45

50 55

LINE WIDTH (MILS)

47

60 65 70 75

Signal Behavior On a Transmission Line

dielectric constant of the medium, and the distance between the ground planes are all
controlled, the line will exhibit a characteristic impedance that can be held constant
within ±5%. The characteristic impedance of a strip line is theoretically:

·z

=
o

~In (4b
rr

0.67 7Tw(0.8

+~)

)

.

This equation proves accurate enough for w/(b-t)<0.35 and t/b<0.25.
Figure 3-9 gives the actual characteristic impedance for various geometries of
stripline. These values were measured with a time domain reflectometer. The
measured results closely parallel those calculated from the above equ3 tion.
Figure 3-10 shows curves for the stripline capacitance per foot for various line
widths and spacings. An LC meter was used to determine the capacitance.
The inductance per foot can be calculated using the relation Lo
while the propagation delay of the line can be found from the relation:
tpd

=

1.017

rr

ns/ft.

For G-IO fiber-glass epoxy boards (e r ~ 5.0), the propagation delay of the
strip lines is 2.26 ns/ft. Again, the propagation delay is not a function of line
width or spacing.
Basic Transmission Line Operation
The behavior of signals on a transmission line is important for understanding
the methods used to terminate MECL lines. Figure 3-1 I shows a line with typical

3·11: MECL Transmission Line

- 2.0 Vdc

loads at both ends. For the purpose of discussion the line delay will be long with
respect to the rise time so that reflections will appear at their full amplitude. The
output voltage swing at point A is a function of the internal voltage swing, output
impedance, and line impedance:

Since Ro is small compared to line impedance, the output swing is nearly the same
as the input transition. The internal voltage swing is approximately 900 mY, giving a
typical output swing greater than 800 mY.
48

Signal Behavior On an Open Line (Stub)

This signal propagates down the line and is seen at point B time TD later. The
voltage reflection coefficient at the load end of the line, PL , is a function of the line
characteristic impedance and the load impedance:

Clearly, for the ideal case of RL = Zo' there is no reflection. More important, for
any value of RL close to Zo the reflection is quite small. At time 2 TD any reflection
returns to point A and is again reflected, by the sending end reflection coefficient PS:

The reflection continues bouncing back and forth between the ends of the line,
being successively reduced by the reflection coefficients and the resistance in the
line.
Un terminated Lines
Figure 3-12 shows a specific transmission line variously known as an "open
line," an "unterminated line" or a "stub." Behavior of this line is as follows. At
time zero an initial, full MECL signal starts at point A. Time TD later the signal
reaches point B and is reflected by PL discussed previously. Since the input
impedance of the driven gate is very high with respect to Zo, a large positive
reflection occurs and signal overshoot results. At time 2 TD the reflection is back at
point A and is reflected by P S. Because of the low value of Ro the reflection is in the
negative direction (refer to equation for PS), resulting in a signal at point B at time
3 TD that is in the opposite direction to the initial signal. This signal at B at 3 TD
and its subsequent reflections produce the undershoot which subtracts from signal
noise immunity. These reflections, successively smaller, cause the condition known
as "ringing" as shown in Figure 3-1 (b).

3-12: MECL Unterminated Transmission Line

If the lines are sufficiently short, the signal still will be rising at time TD, and
reflections are part of the rising edge. With longer lines, the rise of the signal will be
completed before a time TD, and reflections will appear as overshoot and
49

Maximum Open Line Lengths: MECL 10K

undershoot. For this reason, unterminated or undamped lines have maximum
recommended lengths when used with MECL logic.
The undershoot caused by an unterminated line is held to about 15% of the
logic swing if the two way delay of the line is less than the rise time of the pulse.
The maximum open line length may be calculated by expressing this rule with the
relation:

where:

tr = rise time,
tpd

=

propagation delay of the line per unit length.

(Use tpd when line is loaded, cf equation 11, Chapter 7).
It can be seen that the slower rise times of MECL 10K are compatible with open
lines, but that line lengths are important for the faster MECL III/I0KH. The other variable
for line length, tpd, is controlled by the type of line (velocity factor) and the loading on
the line. Increased loading raises the propagation delay and accounts for the decreasing
permissible line length with increasing fanout (cf Figure 2-7). The analysis of rate of
propagation with line loading is covered in Chapter 7.
Suggested maximum open line lengths for MECL 1OK/ 10KH and MECL III are
tabulated in Figures 3-13, 3-14, and 3-15 for various fanouts and line impedances.

3-13. Maximum Open Line Length for MECL 10,100 (Gate Rise Time = 3.5 ns)

Zo
(OHMS)

MICROSTRIP (
(Propagation
Delay

o 148

ns/m )

STRIPLINE
(Propagation

(

ns/m )

BACKPLANE {
(Propagation
Delay

0.140 ns/in.)

FANOUT = 2
(5.8 pF)

FANOUT = 4
(11.6 pF)

FANOUT = 8
(232 pF)

Q MAX (IN)

Q MAX (IN)

QMAX (IN)

QMAX(IN)

8.3
7.0
6.9
6.6
6.5
6.3

7.5
6.2
5.9
5.7
5.4
5.1

6.7

5.7
4.0
3.6
3.3

6.5
5.6
5.3
5.2
5.1

5.9
4.9
4.7
4.4
4.3

5.2
3.9
3.6
3.3

4.5
3.2
2.8

4.9

4.0

3.1
2.8

2.4
2.1

6.6
5.9

5.4
4.3
3.6

3.8

2.8

2.8
2.1

1.9

50
68
75
82
90
100

Delay

o 188

FANOUT ~ 1
(29 pF)

50
68
75
82
90
100

100
140
180

'"

.-

5.2

50

5.0
4.6
4.2
3.9
3.6

3.0
2.6

2.6

1.3

Maximum Open Line Lengths: MECL!lI and MECL IOKH
3·14: Maximum Open Line Length for MECL 10,200
(Gate Rise Time = 2 ns)

Zo
(OHMS)

MICROSTRIP
(Propagatlo n
Delay
0.148 nS/In.)

STRIPLINE
(Propagation
Delay
0.188 nS/1n )

BACKPLANE
(Propagation
Delay
0.140 nS/In.)

!
!
{

FANOUT = 1
(3.3 pF)

FANOUT = 2
(6.6 pF)

FANOUT = 4
(132 pF)

FANOUT = 8
(26.4 pF)

QMAX (IN)

£MAX (IN)

QMAX!lN)

QMAX (IN)

50

3.5

2.8

1.9

1.2

68

3.2

2.3

1.5

0.8
0.7
0.6
0.5
0.4

75

3.0

2.2

1.3

82
90
100

2.9
2.8
26

2.0
1.9
1.8

1.2
1.0
0.9

50
68

2.8
2.5

2.2

1.5

1.9

1.2

75

2.4

1.7

1.1

0.6

82

2.3

16

0.9

05

..

1.0
0.6

90

2.2

1-5

0.8

0.4

100

2.0

1.4

0.7

0.3

100
140

2.8
2.4

1.8

0.9
0.5

0.4

1.4

180

2.0

1.0

0.3

0.1

0.3

3·15: Maximum Open Line Length for MECL III, MECL 10H209, MECL 10H100, 10H210, 10H211
(Gate Rise Time 1.1 ns)

Zo
(OHMS)

MICROSTRIP
(Propagation
Delay
0.148 nS/In.)

STRIPLINE
(Propagation
Delay
0.188 ns/in.l

BACKPLANE
(Propagation
Delay
0.140 ns/in.l

{

!
L

FANOUT = 1
(33 pF)

FANOUT = 2
(6.6 pF)

Q MAX (IN)

QMAX (IN)

FANOUT = 4
(132 pF)

QMAX (IN)

50

1.6

1.1

0.7

68

1.4

08

0.5

FANOUT = 8
(26.4 pF)

Q MAX (IN)
0.6
0,4

75

13

0.8

0.4

0.3

82

1.2

0.7

0.4

0.2

90

1.1
1.0

0.6

0.3

0.2

0.5

0.2

0.1

1.2

0.8
0.7

0.6
0.4

0.5
0.3
0.2

100

50
68
75

1.1
1,0

0.6

0.3

82

0.9

0.6

0.3

0.2

90
100

0.9

0.5

0.2

0.1

0.8

0.4

02

0.1

100

1.1

0.6

0.2

0.1

140

0.8

0.3
0.2

a

a

a

a

180

.

0.6
"

51

Control of Waveshape On Long Lines

For these tables, line lengths are chosen to limit overshoot to 35% of logic swing and
undershoot to 12%.
Series Damped and Series Terminated Lines
Overshoot and ringing on longer lines may be controlled by using series
damping or series terminating techniques. Series damping is accomplished by
inserting a small resistor (typically 10-75.Q) in series with the output of the gate as
shown in Figure 3-16. This technique can be used with all MECL families and is
associated with lines not defined by a controlled characteristic impedance, (e.g. backplane wiring, circuit boards without ground plane, and most wire wrapped
connections).
The series termination is a specialized case of damping in which the resistor
value plus the circuit output impedance is equal to the impedance of the
transmission line. The waveforms in Figure 3-16 and the following description of
operation are for series termination. A similar analysis may be done for any value of
damping resistor and line impedance.
3-16: Driving a Series Terminated Line

The impedance looking back toward the driving gate at point B should be
equal to the characteristic impedance of the transmission line. The dc output
impedance is 5 ohms for a MECL III gate and 7 ohms for a MECL lOK/ lOKH gate. AC
output impedance is only slightly higher than the dc impedance values. Therefore, if
Zo is 75 ohms, then the value of RS must be approximately 68 ohms.
At time = 0, the internal voltage in the circuit switches to the low state which
represents a change of 0.9 volts (~VINT = -0.9 V). The voltage change at point B
can be expressed as:

where Ro is the output impedance of the MECL gate.
Since RS + Ro is made equal to Zo for a series terminated line, then the
voltage change at B is 1/2 the voltage, ~VINT' It takes the propagation delay time

Pros and Cons of Series Termination

of the transmission line, TD, for the waveform to reach point C, where the voltage
doubles due to the near unity reflection coefficient at the end of the line. The
reflected voltage, which is equal to the sending voltage, arrives at point B at a time,
TD, later. No more reflections occur if RS· + Ro is equal to Zoo Similar waveforms
occur when the driving gate switches from the low to the high state.
One of the advantages of using series terminated lines is that only the logic
power supply is required. Another advantage is the lower overall power requirements. One power supply can also be used with parallel terminated lines described in
the next section, but two resistors must be used for the total termination resistor,
resulting in the need for considerably more power. In addition, when two power
supplies are used with parallel terminated lines using one termination resistor, an
extra voltage bus or plane is required to supply - 2.0 volts to the termination
resistors.
A disadvantage of series termination is that distributed loading along the line
cannot be used, because of the half-voltage waveform travelling down the line (see
Figure 3-16, waveform B). However there is no limit on the number of lumped loads
that can be placed at the end of the series terminated line imposed by reflections at
the receiving gate, since all the reflections will be absorbed at the source.
Nevertheless, voltage drop across the series terminating resistor due to input current,
limits loading to less than 10.
The distance permitted among the receiving gates at the end of the line can be
found from Figures 3-13,3-14, or 3-15. For example, ifMECL III were used with 50
ohm microstrip lines, the maximum total separation of four gate loads at the end of
a series terminated line is 0.7 inches (see Figure 3-15).
The disadvantages of slower propagation delay and using only lumped loading
at the end of a series terminated line can be eliminated at the expense of more
transmission lines, as in Figure 3-17. For parallel fanout, n transmission lines can be
3-17: Parallel Fanout Using Series Termination

~ A
Z0tB=
--L./--r
1 'VV\~B
As

3 L:::=J

()

~

iRE
VEE

I

c

I

I

I

I

I
I

: n (Total Number of Lines)

Lo-

i

T-D-

I RS~ZO
~ ... 0_& ==)--'
2:::y

I
I

I
I

Lo53

Designing With n Parallel Lines

used. The value chosen for RS should be the same as discussed previously when n
was equal to one.
To determine the value of the emitter pulldown resistor, RE, the following
procedure is recommended.
The value of RE must be small enough to supply each transmission line with
the necessary current. If RE is made too large, the output transistor will turn off
when switching from the high to the low voltage state. The maximum value for RE
can be derived by equating the voltage point at which the output transistor turns off
with the midpoint of the logic swing:

~ VB = ~ VINT (Rs + ~o + Z )
0

where:

~ VB

= one half the logic swing

~VINT

,

0

= 400 m V,

= VEE - logic 1 level = (5.2 - 0.8) V=4,400mV, (since the
output transistor is turned off, it does not affect the
calculation),

RS

series damping resistance,

Ro

RE (because the output transistor is turned off) .

So:
RE(max) = 10 Zo - RS·
Finally, when n parallel lines are driven as in Figure 3-17:

RE(max) =

10 Zo - RS
n

For n = 4, Zo = 75 ohms, and RS = 68 ohms, this relation gives RE =
170 ohms.
Figure 3-18 shows a circuit using MC 10 109 logic gates. The driving lines have a
width of 50 mils and a board thickness of 62 mils. This geometry corresponds to a
line impedance of approximately 75 ohms. The length of each line is 8 inches, which
produces a line propagation delay of 1.2 ns. The rise and fall times of the driving
gate are about 2 ns each. Figure 3-19 shows the trace seen on a Tektronix 567
oscilloscope using the high impedance probe. The waveform of the line output when
RE = 180 ohms (close to the value calculated above) shows that the rise time and
overshoot of the rising edge are equal to that of the falling edge. The small overshoot
of about 50 mV is due to the line impedance being slightly larger than 75 ohms. This
does not affect circuit operation in any way. The rise and fall time at the line output
are each 3.3 ns.
Figure 3-20 shows the waveforms when RE = 600 ohms. In this case the value
of RE is much larger than the 170 ohms value calculated. Consequently, the fall
time of the waveform suffers since the output transistor turns off and RE is unable to
supply the proper line current. When the output transistor turns off, the output
impedance of the gate becomes that of the pulldown resistor. Calculating the voltage
54

Effects of the Emitter Pulldown Resistor, RE
3-18; Series Termination Test Set-Up Using the MC10109 Gates

Yo MC10109

600

PULSE
GENERATOR

600

600
'\n--4--_-<"l Gate Output

600

Line Output

('

+

:;:-

Line
Output

,
\ rv\

A'_
V

Gate
out:fut

VEE

3-19: Waveforms from Test Set-Up of Figure 3-18
(RE = 180 ohms, n = 4)

V- I - j

Vertical Scale = 0.2 V/cm
Horizontal Scale = 10 ns/cm

f

"'-

I

]
Line
Output

\

\ ,..

1\1,

3-20: Waveforms from Test Set-Up of Figure 3-18
(RE = 600 ohms, n = 4)

I\

.1\

Gate
Out,put

II
~

f

V
Vertical Scale = 0.2 V /cm
Horizontal Scale = 10 ns/cm

55

--

Waveforms With Series Damping

change at point B shows a d V of:

dV INT

::::; -130mV,
where d V INT is the voltage drop in millivolts across the pulldown resistor when high,
and n is the number of parallel series terminated lines.
When the waveform reaches the end of the line, the voltage will double to - 260
millivolts and a reflection of - 130 millivolts will be sent back toward the driving
gate. Since the driving gate output is turned off, the reflection coefficient at the
source is approximately 0.8. Therefore, after a time of twice the line delay, an
additional - 200 millivolts is received at the load. These reflections continue until the
voltage at the end of the line reaches the logic f/J state.
These steps in voltage can be seen in the falling edge of the line output
waveform (Figure 3-20), in close agreement with the calculations. The fall time
increases by approximately six times the line propagation delay, or 7.2 ns. If the
transmission line had been longer, the voltage step duration would have increased
correspondingly. Note that the gate output at the end of the line also has an
increased rise time and propaga tion delay.
Figure 3-21 shows the waveforms from the test setup shown in Figure 3-18,
when only one line is driven (n = 1) and with RE = 600 ohms. Using the equation

3-21: Waveforms from Test Set-Up of Figure 3-18 with Only One Line Driven
(RE = 600 ohm, n = 1)

-

Line
Output

\
n

Gate
Output
+

}

V
Vertical Scale = 0.2 V/cm
Horizontal Scale = 10 ns/cm

Series Damping: Determining the Resistor Value

for RE(max) gives a value of 680 ohms. Note that the rise and fall times are
approximately equal (2 ns) meaning that the proper pulldown resistor was chosen.
The rise and fall times at the line output are much faster in Figure 3-21 than in
Figure 3-19, due to the lighter load at the gate output and reduced nodal
capacitance at point A.
Analysis of series damping is very similar to that for a series terminated line.
Differences are the line length and the value of the series damping resistor, RS' For
series damping this resistor value is normally smaller than the characteristic
impedance of the line. Accordingly line lengths are permitted which are longer than
the worst-case open line lengths (RS = 0), as defined in Figures 3-13, 3-14, and
3-15. The same equations for voltage at point B and maximum RE apply, as did for
series terminated lines. In fact, series damping can be used to extend lines to any
length, while limiting overshoot and undershoot to a predetermined amount. Figures
3-22 and 3-23 give minimum values of RS for various line impedances for MECL
lOKI lOKH and MECL III. For these figures, overshoot was limited to 35%of signal swing
and undershoot to 12%. The technique for calculating these RS values is given in Chapter 7.
Here is an example of how Figure 3-22 and 3-23 can be used. Assume that a
MECL III gate must drive a fanout of 2 (6.6 pF) at the end of 1 foot of line in the
backplane. The characteristic impedance in the backplane is between 100 and 180

3-22: Minimum Values of RS for Any Length of Line with Specified
Limits of Overshoot and Undershoot, Using MECL 1QK/10KH

Zo (OHMS)
50
68
75
82
90
100
120
140
160
180

MIN RS (OHMS)

UNDERSHOOT

FOR Ro= 15

%

%

12
12
12
12
12
12
12
12
12
12

34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6

9
18
21
25
29
34
43
53
63
72

OVERSHOOT

3-23: Minimum Values of RS for Any Length of Line with Specified
Limits of Overshoot and Undershoot, Using MECL "I
MIN RS (OHMS)
FOR Ro = 6

UNDERSHOOT

Zo (OHMS)

%

%

50
68
75
82
90
100
120
140
160
180

18
27
30
34
38
43
52
62
72
81

12
12
12
12
12
12
12
12
12
12

34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6
34.6

57

OVERSHOOT

Parallel Terminations

ohms. An open line should not be used because it exceeds the length given in Figure
3-15: 0.6 in. Another method therefore must be used - coax, twisted pair, or series
damped line.
If series damping is used, then from Figure 3-23, a series damping resistor of 81
ohms or larger should be placed in the line at the driving end. The maximum value
of the series damping resistor that should be used is 130 ohms for a fanout of 2,
since there will be a dc level shift of 90 m V (maximum) caused by the series
resistance in the line when the driving gate is in the high state. The 90 m V figure is
based on the maximum input current, linH of the MECL III gate being 350 /1A.
(V = loR, where R = 130[2, and 1=2 x 350 /1A).
Both the maximum overshoot and undershoot that can occur are given in the
tables. If the proper value of RS (series damping resistor) is used, as given in the
tables, there is no restriction on line length or capacitance at the end of the line for
the specified undershoot and overshoot. Of course, ohmic line losses and line
propagation delay effects must be considered in the design.
Parallel Terminated Lines
Parallel terminated lines (Figure 3-24) are used for fastest circuit performance
and for driving distributed loads. MECL lOKI lOKH and MECL III are specified to drive
"50 ohm lines." This refers to a line, terminated at the receiving end through a
resistor of the characteristic line impedance to - 2 volts from the VCC supply. With
parallel terminated lines, the line termination supplies the output pulldown.
Consequently no other pulldown resistor is required at the output of the driving
gate.
3·24: Driving a Parallel Terminated Line
~-----TD------~

The operation of the parallel terminated line is comparatively simple. The
signal swing at point A is:

Since Ll VINT is approximately 0.9 volts and the output impedance is low
eRo « Zo), the signal swing at point B is typically greater than 800 millivolts. This
signal propagates down the line, undistorted, in time Tn. Since the terminating
resistor equals Zo, there is no reflection and the sequence is ended.
58

Thevenin Equivalent Parallel Termination

An important feature of parallel termination is the un distorted waveform along
the full length of the line. It should be noted that parallel termination can also be
used with wire-wrap and backplane wiring where the characteristic impedance is not
exactly defined. By approximating the characteristic impedance, the reflection
coefficient P L will be reasonably small, so overshoot and ringing will be held to
within safe limits.
For large systems where total power is a consideration, the lines are normally
terminated to a - 2 V dc supply. For power conservation, this is the most efficient
manner of terminating MECL circuits. The drawback, of course, is the requirement
of an additional supply voltage.
An alternate approach is to use two resistors in the way depicted in Figure
3-25. The Thevenin equivalent of these two resistors is one resistor equal to the

3·25: Parallel Termination with a Single Power Supply
THEVENIN EQUIVALENT RESISTORS
FOR TERMINATION
R2
Rl
Zo
(OHMS)
(OHMS)
(OHMS)
50
81
130
113
182
70
75
121
195
80
130
208
146
234
90
100
162
260
120
194
312
150
243
390

R1

-5.2

characteristic impedance of the line and terminated to -2 Vdc. RI and R2 may be
obtained as:

R2 = 2.6 Zo
RI

= R2

1.6

Transmission Line Comparison
Since there are advantages to both series and parallel lines, the decision to use
one or both methods in a system depends on the preference of the designer and on
his system requirements. Figure 3-26 lists typical cases where terminations may be
necessary, along with techniques which may be used.
Parallel terminated lines have the advantage when speed is the main factor.
Loading a long line will not affect the propagation delay of the driving gate nor its
edge speed, but loading does increase the propagation time of the signal down the
line. It will be shown in Chapter 7 that the increase in delay time with loading is
about twice as great for series damped lines as for parallel terminated lines. For short
lines the capacitive load increases the propagation delay of the gate by slowing down
the edges.
As mentioned previously, a big advantage of parallel termination is that the
signal is undistorted along the full length of the line. When driving a large fanout, the
loads may be distributed along the line with short stubs, instead of being lumped at
the end of the line as is done with series termination. On the other hand, series
59

Discussion of Line Options

3-26: Types of Lines Recommended
PARALLEL
TERMINATED LI NE

SER IES
TERMINATED LINE

OPEN
LINE

Yes

Yes

Yes

Yes

Yes

No

3. Driving gate drives 3 or more
lines of lengths greater than
specified (Fig. 3-13,-14,-15).

No

Yes

No

4. Gate loads must be distributed
along a long transmission Jine.

Yes

No

No

5. Many gates are lumped at
the end of long transmission
line.

Yes

Yes

No

6. Only one power supply is to be

No

Yes

Yes

7. Two power supplies are used and
the lowest power consumption is
desired.

Yes

Yes

Yes

8. Backplane wire lengths are shorter

Yes

Yes

Yes

Yes
(150 ohms)

Yes
(100 ohms)

No

10. Backplane wire lengths are longer
than specified (Fig. 3·13,-14,-15).
(no ground screen Is used).

Use
Twisted
Pairs,
or Coax

No

No

11. Large temperature dIfferentials
exist between card bays or racks.

Use
Twisted
Pairs

No

No

12. Driving gate drives 3 or more tines
in backplane longer than specified
(Fig.3-13,-14,-15).

No

Yes
(100 ohms)

No

13. Wires are bundled closely together
near noisy portion of system.

Use
Coax or
Twisted
Pairs

Coax

No

SITUATION
1. Line lengths are shorter than
specified (Fig. 3-13,-14,-15),

2. Driving gate drives 1 line, of
length greater than specified
(Fig. 3-13,-14,-15).

used and the LOWEST power
consumption is desired.

than specified (Fig. 3-13,-14,-15).

9. Backplane wire lengths are longer
than specified (Fig. 3·13,-14,-15)'
and a ground screen is used in
backplane.

60

Wire wrap

termination has the ability to drive several parallel lines, as long as the drive current
is compensated by the value of the output pulldown resistor. The MECL lOKI lOKH and
MECL III outputs will drive only one 50-ohm parallel terminated, or two lOO-ohm parallel
terminated lines. Exceptions to this rule include the MClOllO/21O, MClOll1/21l,
MClOH21O and MClOH211 which have multiple gate outputs for driving three parallel 50
ohm lines, and the MClO123, MClOH3301 332/ 334 which can drive 25 ohm lines.
Termination power is lowest for a parallel terminated line terminated to
-2 Vdc. However, similar power savings may be realized by connecting the pUlldown
resistor for open wire or series terminated lines to - 2 V dc. Using a smgle power
supply, the series termination and pulldown resistor uses less power than the
two-resistor parallel termination. Typical power in the terminating resistors for 50
ohm lines for signals with 50% duty- cycle is tabulated in Figure 3-27.
Additional information for calculating system power is contained in Chapter 5,
"Power Distribution."
Crosstalk on circuit boards is normally not a problem with MECL, because the
relationship of the signal line to the ground plane minimizes the energy coupled to
adjacent lines. Even so, series terminated lines have less crosstalk than parallel
terminated lines. The reason is that only one-half the logic swing is sent down the
series terminated line. As a result the switched current is only one-half that of the
larger, parallel terminated signal. This smaller signal energy results in less crosstalk.

3-27: Power Consumption for Various 50-Ohm-Line Terminations

TERMINATION
SCHEME
Parallel
Series
Parallel Combination

RESISTOR
ARRANGEMENT

RESISTOR
POWER
CONSUMPTION

50 ohm to -2 Vdc

13 mW

5100hm to VEE

30 mW

82 ohm to Vee. and
130 ohm to VEE

144mW

Wirewrapped Cards
Wirewrapped cards can be used with MECL lOKI lOKH. The fast edge speeds (l ns)
of MECL III exceed the capabilities of normal wirewrapped connections. Mismatch
at the connections causes a reflection which distorts the fast signal, reducing noise
immunity significantly or causing erroneous operation. The mismatch remains with
MECL lOKI lOKH but the distance between the wirewrap connection and the end of the
line is well within the allowable stub-length distance, so the reflections cause
no problem.
For lines longer than maximum allowable open line length for MECL lOK/lOKH,
either series or parallel termnation may be used. The parallel resistors are relatively high
(typically 100 to 150 ohms) and are normally used only with MECL lOKI lOKH because it
can supply the output current required by the pulldown resistors. Of course series damping
resistors may be used with wirewrapped lines for MECL lOKI lOKH. Twisted pair lines
may be used for longer distances across large wirewrapped cards. The twisted pair gives a
more defined characteristic impedance (than a single wire), and can be connected either
single-ended, or differently using a line receiver.
61

Wire wrap

Twisted pair line driving is an important feature of MECL circuits and is
discussed in more detail in the next chapter. The recommended wirewrapped circuit
cards have a ground plane on one side and a voltage plane on the other, to insure a
good ground and a stable voltage source for the circuits. In addition, the ground
plane near the wirewrapped lines lowers the impedance of those lines and facilitates
terminating the line. Finally, the ground plane serves to minimize crosstalk between
parallel paths in the signal lines. Point-to-point wire routing is recommended because
crosstalk will be minimized and line lengths will be shortest.

Production area for MECL Integrated Circuits

62

System
Interconnections
Signal connections between logic cards, card panels, and cabinets are important
for obtaining the maximum system performance possible with MECL circuits. To
understand how ringing and crosstalk affect system operation, it is helpful to review
guaranteed noise margins, discussed in Chapter 1.
Noise margin is defined as the difference between a worst case input logic level
and the worst case threshold closest to that logic level. Guaranteed noise margin
(N.M) for MECL 10K is:
NM 1 level

VOHA min - VIHA min
-0.980 V - (-1.105 V) = 125 mY;

NM0 level

VILA max - VOLA max
-1.475 V - (-1.630 V)

= 155 mY.

The threshold levels associated with MECL 10K (VOHA, VIHA, VILA and VOLA)
are synonomous with VOHmin, VIHmin, VILmax and VOLmax for MECL lOKH. The
guaranteed noise margins (N.M.) for MECL lOKH are therefore:
NMllevel

=VOH min - VIH

min

= -0.980 V - (-1.130 V)

= 150 mV
NM~ level

=VIL max - VOL max
=-1.48 V - (-1.63 V)
=150 mV

Thus, using the worst case design conditions, MECL lOK/lOKH have 125 m V 1150
mV respectively to guard against signal undershoot, and power or thermal disturbances.
However, using typical logic levels of -0.900 volts and -1.750 volts, the circuit noise
protection is typically greater than 200 mV for both the logic 1 and logic ~ levels. Power
and thermal design will be discussed in Chapters 5 and 6.
Good circuit interconnections should allow no more than 100 to 110m V
undershoot. The overshoot and undershoot waveform conventions are shown in
Figure 4-1.

63

System Interconnections: Delay, Attenuation, Crosstalk
4-': MECL Waveform Terminology

Overshoot {
Undershoot

1----+---1--

~---.....- - - - - - 1 Level

50%--~---------~--

Undershoot

I---\---F--~=----

0 Level

Both overshoot and undershoot are functions of many variables: line length,
capacitive/inductive loading, rise time, and so on. Thus, in general, to maintain
undershoot less than 110m V requires one or more of the following:
•
•
•

Reduction of system rise times;
Reduction of interconnect line lengths;
Use of matched, terminated transmission lines.

Reduction of rise time is easily accomplished by going to a slower MECL
family, but this reduction in rise time may limit the use of the high bit rates and
narrow pulse widths necessary for system performance goals. Interconnection line
lengths are dictated by the system design and are routinely minimized as a matter of
practice. Impedance matching of the interconnection lines remains then, the one
variable which can be exploited for limiting the undershoot and ringing.
When using the faster varieties of MECL circuits, the type of card-to-card
wiring in the system backplane area should be considered carefully. The initial
decision is between two basic methods of board-to-board interconnect:
1.

Controlled impedance, e.g., mother-daughter boards using microstrip lines,
coax, ribbon flex, or twisted pair interconnects;
2. Uncontrolled impedance, e.g., open wire backplane wiring - with possible
wide variations in characteristic impedance.
With MECL III, method 1 must be used. The entire system must be in a
transmission line environment. While MECL lOK/ lOKH is designed to drive transmission
lines, the slow edge speed allows it to operate with the more economical wire over
a ground plane layout. Wire over a ground plane or ground screen often has a
characteristic impedance between 100 and 150 ohms, and can be series damped or
parallel terminated for extended open wire lengths in the backplane area. Both
wirewrapped and soldered wire connections are suitable for connecting wires to card
connectors in MECL lOK/lOKH systems.
When designing system interconnections, four parameters must be taken into
consideration:
•
Propagation delay per unit length of line;
•
Line attenuation;
•
Crosstalk;
•
Reflections due to mismatched impedance characteristics of the line,
connectors, and line terminations.
Propagation delay of a line is important because unequal delays in parallel lines
may cause timing errors. Also, for long lines the total delay time will often seriously
affect system speed. Since the propagation delay of one foot of wire is
64

Connectors and Cable for use with MECL

approximately equal to the propagation delay of a MECL 10K gate, line length must be
minimized when total propagation time is important.
Attenuation is also a parameter of a line. It varies with frequency and is seen as
an increase in impedance for an increase in frequency. The effects of attenuation
first appear as a degradation in edge speed. This is followed by a loss of signal
amplitude for high frequencies on long lines. A rounding of the waveform occurs,
since the higher frequency components required to give sharp square waves are
attenuated more than low frequency components. Within a backplane attentuation
is seldom a problem, but it must be taken into consideration when interconnecting
among panels or cabinets.
Crosstalk is the undesired coupling of a signal on one wire to a nearby wire.
Since a coupled pulse in the direction of undershoot results in a reduction of noise
immunity, precautions should be taken to limit crosstalk. A good ground system and
shielding are the best methods for limiting crosstalk. Differential twisted pair line
interconnections can avoid problems caused by crosstalk by virtue of the common
mode rejection of the receivers used with such an arrangement. Crosstalk is discussed
in more detail under the heading "Parallel Wire Cables" later in this Chapter.
Reflections due to mismatched lines in system interconnections cause the same
loss of noise immunity as discussed in Chapter 3 for printed circuit boards. The
ability to terminate a line effectively is primarily a function of how constant the
impedance is over the length of the line. Because it has high uniformity, coaxial
cable is easier to terminate than open wire. Yet in many cases, twisted pair cable or
ribbon cable may be purchased with specifications on the impedance of the line.
Connectors
There are very few high frequency edge connectors that do not cause
waveshape distortion when rise times are under 1 ns. The few that don't are of the
"matched impedance" type in which the on-board strip transmission line flows right
into and out of the connect.or, without encountering a mismatch. Unfortunately,
this form of connector is usually expensive and is often difficult to design with.
The only forms of MECL logic which require the use of matched edge connectors are
the MECL III family and the MCIOH209. With rising edges of approximately 2 ns, the
MECL 10K families may utilize conventional edge connectors. With them, very little
mismatch occurs: typically
20 m V.
Coaxial cable connectors that have near ideal characteristics over the
bandwidths exhibited by MECL logic exist in a variety of types. The most popular
are the BNC type and the subminiature SMA, 5MB, or SMC types. The smaller
miniature types offer direct microstrip to coaxial interconnects with low voltage
standing wave ratio (VSWR), i.e. minimum reflection.

<

Coaxial Cable
Coaxial cable offers many advantages for distributing high frequency signals.
The well defined and uniform characteristic impedance of the line permits easy
matching. The ground shield on the cable minimizes crosstalk. Low attenuation at
high frequencies makes good coaxial cable very desirable for handling the fast rise
times associated with MECL signals.
The line bandwidths required for optimum MECL use are:

65

Behavior of Cable and Terminating Resistors

where:

=

so:

f

and:

f

and:

f=

0.37
1 x 10- 9
0.37 9
3.5 x 100.37
1.8 x 10-9

k
tr

0.37*,
rise time;

370 MHz for MECL III with a 50 n load

= 106 MHz for

MECL 10K with a 50n load

=206 MHz for MECL IOKH with a 50nload.

At MECL frequencies, skin effect is a primary cause of attenuation. Dielectric
losses are insignificant below 1 GHz for the common dielectric materials polyethylene or teflon. Attenuation due to skin effect is proportional to the square
root of frequency and so may be plotted conveniently on log-log paper. Figure 4-2
contains data for three cable types tested. Maximum cable lengths recommended
with the various MECL logic families can be derived from these plots as the
following example will show.
For maximum signal reductions of 100 m V in the 1 and (jJ levels (i.e. a logic
swing reduction from 800 m V pip to 600 m V p/p) the permissible attenuation
would be:
Loss (dB)

= 20 log

~

Vin) = 20 log ~0.8)
= 2.5 dB.

-Vo

0.6

For MECL III with RG58/U the loss at 370 MHz is found to be 12 dB/IOO' from
Figure 4-2. Thus, with the 100 m V restriction:
Max Length

=

100 ft. - ( 2.5 dBj
12 dB

20.8 ft.

Figure 4-3 shows curves giving maximum line length as a function of operating
frequency for the same three cable types used for Figure 4-2. Each curve assumes
2.5 dB permissible loss. It should be noted that a high bandwidth line is necessary to
preserve fast signal edges, regardless of the bit rate of the system.
Figure 4-3 and the preceding calculations assume the coaxial line is properly
terminated with a resistive load equal to the characteristic impedance of the line.
The reactive component of the termination is of increasing importance at high frequencies.
At such frequencies, reactive elements can change the terminating impedance, thus causing
reflections on the line. In addition, the effective inductance or capacitance would distort
the output waveform, causing additional reflection down the line.
Standard carbon resistors were carefully measured at high frequencies to
determine their reactive components. Results are listed in Figure 4-4. The effective
circuit is a resistor with an inductor in series. Carbon resistors display more inductive
reactance as the resistor values become smaller, and display more capacitive
reactance as the values get larger. However, 75 ohm resistors are normally close to
being purely resistive.
*0. Gene Gabbard, "High Speed Digital Logic for Satellite Communications."
Electro-Technology, April 1969, p. 59.
66

Cable Reflection
4-2: Coaxial Cable Attenuation versus Frequency
30

.... V

20

/"'"

R G 188A/U '\,..
10
9.0
8.0
ATTENUATION
dB/100Ft

v

7.0
6.0

io-""

5.0

..Y

V

./

V

~~

3.0

V
2.0
40

I/'

V

V"""

./

"-

/"

7"

.....v

:,-V

V

V,

V

V

/

/"

vI--"

4.0

P V

V

V

l/

vI--

l/V'
l/

VI--

V

RG5B/U

~

I

RG59/U

V
60

200

80 100

400

600 800 1000

FREQUENCY (MHz)

4-3: Coaxial Cable Length versus Operating Frequency:
Constant 2.5 dB Loss Curves
400
200

LENGTH
(Ft)

100
80
60

--

r-.

40

........
........t-."

...............

~

20

l""-k'..... "r---.., J""..

t-....

10
8.0
6.0
4.0
30

F}q5N~
RG58/U
RG188A/U

1 I ITT
50 70 100

200

400

7001000

3000

FREQUENCY (MHz)

TEST CONDITIOIN

Z = R + jX

112 W, 51 ohms, 500 MHz

Z=51.8+J15.5

112 W, 51 ohms, 300 MHz

Z = 51.4 + j5.6

1/4 W, 51 ohms, 500 MHz

Z = 48.8 + j6.1

114 W, 51 ohms, 300 MHz

Z = 49.4 + JO.29

1/8 W, 51 ohms, 500 MHz

Z = 51.5 + J6.7

118 W, 51 ohms, 300 MHz

Z=51.7+j1.6

4-4: Impedance Characteristics of Carbon Resistors
Measured on a GR Admittance Bridge

67

4-7: Typical Switehing Times

4-5: Line Driver Test Circuit

L

-0.8 Vdc

(Test

MC10109
Clock
NOR

-1.6 Vdc

(J, 1°_5:nr(:::~,-::Vd'

PULSE
GENERATOR

Output A

Circuit t=igure 3-5;

T A = 2SoC, f '" 20 MHz)

Output B

Output A
TEST

JTIME

(ns) 1

OR
tpd++

(50% to 50%)

2.6

tpd- -

(50% to 50%)

2.7

tr

(10% to 90%)

2.6

tf

(90% to 10%)

2.0

NOR
Trigger
To Scope

Pulse Generator: E-H Model 122 or equivalent.

0\

(50% to 50%)

2.6

(50% to 50%)

2.5

tr

(10% to 90%)

2.4

~.

tf

(90% to 10%)

2.7

g

00

~
~
~

4-6: Line Driver Test Circuit Input and Outputs, Observed Via High Impedance 'Scope Probes.
(b) NOR Output Waveforms

(a) OR Output Waveforms
Input

I,

j,"""-

I

-I

I ~ - -~

~

Output B

C--

Input

TEST

I TI ME (nsll

OR
tr
Output
A

tf
Output
A

Output
B

I/

"-L! J

'ok:

t

tr

>'
tf

Vertical Scale = 500 mVfcm
Horizontal Scale

= 5.0

nsfcm

(10% to 80%)

3.8

(10% to 90%)

5.4

(80% to 10%)

3.4

(90% to 10%)

5.4

(10% to 80%)

3.8

NOR

Output
B

Vertical Scale = 500 mV fcm
Horizontal Scale = 5.0 ns/cm

~

tpd+tpd-+

(10%to90%)

5.4

(80% to 10%)

3.7

(90% to 10%)

5.7

~

Using Coaxial Cable

The reflection at 300 MHz for a 50 ohm line using a 1/2-watt 51 ohm carbon
resistor can be calculated:
p

where: ZL

load impedance,
line impedance;

p=51.4+j5.6-50
51.4 + j5.6 + 50·

so:
Calculations yield:

p = 0.055

/72.8°

As a result, (0.055)· (800 mV logic swing) = 44 mY, is reflected back down
the transmission line. Clearly, this is much less than the 300 mV maximum
overshoot recommended for safe MECL usage. With a slow repetition rate in
relation to the propagation delay of the line (time per pulse >3TD) the reflection
appears as a small overshoot at the receiving end of the line. In high frequency
operation the reflection may subtract from the transmitted signal. The amount
would depend on the exact length of the line and the propagation velocity of the
line. Subtracting signals appear to reduce the signal on the line, as if either the signal
were attenuated, or as if the driving gate were bandwidth limited.
Standard carbon 1/8 watt resistors have been found to have good high
frequency characteristics when used with MECL III. Either 1/8 or 1/4 watt resistors
work well with MECL lOK/lOKH. When using precision wire wound or film resistors,
care should be taken to determine the high frequency properties of these devices.
Most wire wound and some film resistors become very inductive at high frequencies.
The fanout at the end of a coaxial line should also be limited at high
frequencies because of reactive loading. At 300 MHz the fanout should be limited to
four. The terminating resistor leads and circuit leads should be kept short. In many
cases it is desirable to restrict long interconnecting cables to a fanout of one to
minimize reflections and therefore to maintain a high degree of noise immunity.
The propagation velocity is very high in coaxial cable. Computing the
propagation delay as:
tpd

=

1.017

,!e;

the delay for solid teflon and polyethylene insulated cables is 1.54 ns per foot
(dielectric constant, er ~2.3). This compares with 2.2 ns per foot for stripline as
calculated in Chapter 3. For maximum propagation velocity, coaxial cables with
styrofoam or polystyrene beads in air dielectric may be used. However, many of
these cables have high characteristic impedances and are slowed by capacitive
loading. Nonetheless, coaxial cable definitely should be used when sending high
repetition rate MECL signals over long lengths.
69

Twisted Pair Line: Differential Use

Illustrated in Figure 4-5 is a circuit used to test the performance of coaxial
cable driven by an MCIOI09 gate. Figures 4-6 (a) and (b) show the waveforms of
the circuit with 95 feet of RG58/U connecting cable. Output B in each figure clearly
shows the waveform for a skin-effect limited line. Skin effect causes the waveform
to rise sharply for the first 50% of the swing, then taper off during the remaining
portion of the edge. Calculations show that the 10 to 90% waveform rise time is
30 times greater than the 0 to 50% rise time when the cable is skin effect limited.
The output amplitude of the cable is at least 200 m V pip less than the input, as
would be expected from Figure 4-3.
Figure 4-7 presents the test results for the circuit in Figure 4-5. Notice that the
numerical data show that at the output of the line, the time from 10 to 80% is much
less than 10 to 90% - because of the coaxial skin effect. When operating within the
limits discussed previously in this chapter, MECL signals are transmitted over coaxial
lines with minimum distortion.

Differential Twisted Pair Lines and Receivers
Twisted pair line, differentially driven into a MECL line receiver (Figure 4-S),
provides maximum noise immunity. This is because any noise coupled into a twisted pair
line generally appears equally on both wires (common mode). Because the receiver
responds only to the differences in voltage between the lines, crosstalk noise is ignored,
since it is picked up equally by each of the two lines of the pair. This holds true up to the
common mode noise rejection limit of the receiver. Quad line receivers, such as the
MC1692, have + 1 and -l.S volt common mode rejection limits before the receiver's output
approaches MECL input threshold levels. The Common mode rejection lower limit can be
improved to a -2.S volt limit by using MECL lOK/lOKH line receivers (e.g. MClOllS,
MClO1l6, MClOHllS or the MClOH1l6).
With devices such as these, the constant current source employed in the emitter
node of the differential pair allows the increase in common mode rejection. This
improvement is useful when signals are sent from circuits other than MECL. The
MC1650 A/D Comparator is also used as a special purpose line receiver and offers
±2.5 volts common mode rejection. However the standard line receivers have more
than adequate common mode noise rejection to handle any crosstalk between
MECL signal lines. If higher voltage signal lines are run in parallel with MECL lines,
shielded twisted pair lines may be used to reduce crosstalk further.
For low frequency operation, line length is limited by the dc resistance of the
wire used and the voltage gain of the line receiver. In order to determine line
length allowed it is first necessary to examine the required signal at the end of the
line, and the amplification possible with the receiver. The typical differential voltage gain of the circuit (Figure 4-9) may be calculated ...
Assume Q2 and Q3 are conducting. Then:
gain

= gmRC.

RC is known, and:

where:

IE

= V CS - VBE

== 4.0 rnA

RE
70

Line Receiver Gain

L~
f3+l

and

K

Boltzmann constant = 1.38 x 10- 23,

T

temperature degrees Kelvin

q

~

300,

= charge of electron = 1.602 x 10- 19.
4-8: Twisted·Pair Line Driver and Receiver
-5.2 Vdc

-5.2 Vdc

4-9: 1/4 MC10115 Schematic
r---------------~ VCC1

r----..-----Differential

-Di

Single-Ended

i+-= 1~

D-

(b) Connections

Another type of multiconductor cable is called "triax." As its name suggests,
this is a three-conductor cable with characteristics similar to coaxial cable. Triax has
a flat cross section for flexibility, and may be used with all MECL families including
MECL III. When using triax type cables, the manufacturer should be consulted for
information about the impedance and attenuation characteristics of a specific cable
type.
76

Matching Line Impedance with Schottky Diodes

Schottky Diode Termination
Under certain board interface conditions, it may be advantageous to use a
termination technique employing Schottky diodes. Several advantages are gained by
the use of diode terminations:
•
•
•
•
•

•
•

No matched impedance striplines are required;
No line matching termination resistors are required;
All signal overshoot is effectively clamped to the 1 or (/) logic level;
All external noise in excess of 1 or f/J logic levels is clamped at the receiving
gate or load;
The total cost of layout, even though diodes are more expensive than
resistors, may be less because no precise transmission line environment is
necessary;
If ringing is a problem on a drive line during system checkout, diode
termination can be used to improve the waveform;
Where line impedances are not well defined, as in breadboarding or
prototype construction of systems using MECL, use of diode terminations
is convenient and saves time.

The forward conduction characteristic of the Schottky barrier diode is used to
match the line impedance of the signal path. For instance, if a 90 ohm line is used,
the diode impedance equals 90 ohms at a forward voltage of 0.45 volts (0.45 V from
5 rnA

Figure 4-20). Therefore, the line would be terminated with only a small overshoot.
The variable conduction curve of the diode permits terminating line impedances
from 150 n to 50 n.

4-20: Schottky Diode MBD101 Forward Transfer Characteristic
100
50
/

L

20
IF. FORWARD

10

CURRENT

5.0

/

(rnA)

/

/

2.0

/
1/

1.0
0.5
/

/

0.2
0.1
0.2

/
0.3

0.4

0.5

0.6

VF. FORWARD VOLTAGE (VOLTS)

77

0.7

Using Diode Terminations

In use (cf Figure 4-21), one side of the parallel diode network is biased at the MECL
threshold VBB (-1.29 volts for MECL lOKI lOKH and MECL III). The VBB source can
be either a separate supply or a gate that supplies the required sink and source current (cf

4·21: Diode Termination
MECL Driver

MECL Receiver

Gate

Gate
Interconnect Line

Data In

Data Out

Rp

MBD101

Figure 4-18). These current requirements can be determined from the graph in Figure 4-20
as follows:

VD 1 (1 level diode drop)

VBB - logic I level

-1.29 -(-0.90) = -0.39 V.

From the graph in Figure 4-20, -0.39 V yields a diode current of approximately
-1.0 rnA (lBB}), and:

VD0

(0 level diode drop) = VBB - logic olevel

=-1.29 - (-1.70) =0.41 V,

also indicating a current of 1.0 rnA (lBB0).
Thus at the receiving end of the line the power consumed would only be
0.4 mW. The driving device must have an emitter-follower pulldown resistor, Rp, to
provide a current path to· VEE and to establish a well-defined output leveL
Consider a case when this resistor is 600 ohms, as for MECL 10K. The power
consumed in this resistor would be about 25 mW. If the resistor were 100 ohms to a
VTT of -2.0 volts, then the power consumed would only be 7 mW average.
78

Improvements Due to the Diodes

A disadvantage of the diode termination scheme is that as many as three
voltages might be required: VEE (-5.2 V), VTT (-2.0 V), and VBB (-1.3 V).

4·22: Circuit #1 - Reduction of Line Ringing by Use of Terminating Diodes

~24"-

PULSE

MC10109

>--......__ #26 Wire over a ---4I~---I
ground plane.

GENERATOR

50

600

MBD101

tr = 1.0 ns

-5.2 Vdc

-5.2 Vdc

Without Diodes

:
I
I

I

"

I

I.

'

t

I

I

I

Ii

Ii

I

I

B

I

I
I

I

I
I

f""'i.. --.I

I

I 1\
It

I

\. V

1/

.

I.

r

IOutPllt
'+

I

1\

\1
r

"

\

I :

I

I
\
I, \ ' \
,, ,'\ t;! t-:
" t 1\--+, '" I,:ii
,,}

\/

fl-Input
A

I~

"

J\

1\

With Diodes

I

I

I

I

,
I

~

I

I
I

I

1T-'"

~t,."'-II

~

,

:

!

~

:~___ ....J 1

~ Output

~

,_

iiI

I
Vertical Scale = 500 mV /cm
Horizontal Scale = 20 ns/cm

Circuit Rise Time with Diodes

I
I

!
r---

I
V

Input A

i

i
r---

!
Output B

1

J

f

r--r-

79

-

,,

:

Line Ringing Suppressed by Diodes
4-23: Circuit #2 - Stub, off Diode Terminated Line

~

=

-'ll

18"
#26 wire over a
>-A--4~- ground plane

PUL.SE
GENERATOR

tr

24"-1
IB

-5.2 Vdc

1.0 ns

MC10109

Without Diodes on Stub

--~I

Input
A

I

I

I

--

'- ~

\

I

\

Ii--

,\)'v'
/;

I

Input
B

..

I

•

-

I..

I
I

'"'"

-

..

:'

~

.

I

I

'"

I

t
..,I

iA

V\/" ~I

-~-

I

~

I
I

It u'V ~

i

\

iJ

.. .-1
". ...

A"""

"'I-"

Vertical Scale = 500 mV/cm
Horizontal Scale = 20 ns/cm

With Diodes on Stub

I--

-,

-'-

I

Input

I

A

r
I

I,~)

=

-

-

!'r---;

tl

I

I

:~

0.-. Input
I

\I

B

n

\

~.

\.~

w..I

It

I

:

:"-- .-J

Vertical Scale = 500 mV/cm
Horizontal Scale = 20 ns/cm

80

I
I

~

..

~r--

MC10109

Subnanosecond Diode Performance

Offsetting this are the elimination of the transmission line requirement, and the
economical average termination power: (0.4 + 7.0) = 7.4 mW.
Figures 4-22 through 4-24 illustrate the performance of the Schottky diodes
(MBD 101) and show their unique ability to suppress severe ringing. Both circuit # 1
(Figure 4-22) and circuit #2 (Figure 4-23) were evaluated with and without diode
terminations. The 'scope traces show that ringing is reduced to less than 100 m V,
while system rise time remains under 2.0 ns. Circuit #2 is a typical example of loads
being stubbed off along a clock distribution line to provide clocking information to
other parts of a system.
Even when dealing with subnanosecond risetimes (~400 pS), Schottky diodes
perform most satisfactorily - as shown by the waveforms derived from circuit #3 in
Figure 4-24. The conclusion is that even for card-to-card or backplane interconnects,
MECL III logic could be distributed with only a small amount of waveform
degradation when diodes are used.

4-24: Circuit # 3 - Subnanosecond Performance of Diode Terminated Line

r---------, A
PULSE
GENERATOR
EH 129

1.

0-----

24

MC10109

"

~-.-----------~~

50
MBD101

tr = 400 ps

Line I nput/Output Waveforms

..

r""

Point A

I

Waveform Rise Times

.

i--

I

I

_...

tr '" 400 ps

.---

PoirrtA

1/

\"--

~'"

~

tr'" 1.2 ns

[

.
...,
,

~

Point B

~J

\
I
I

~

/

Point B

V

Vertical Scale = 500 mV Icm
Horizontal Scale = 1.0 ns/cm

81

I

tpd "" ~.1 n~

t
Vertical Scale = 500 mV/cm
HOrizontal Scale = 20 ns/cm

~

....

Oosstalk Between Parallel Wires in Cables

Parallel Wire Cables
Multiple conductor cables as purchased, or as constructed by lacing interconnection wires together, are not normally used with MECL because of crosstalk.
Such crosstalk is due to capacitive and inductive coupling of signals among parallel
lines as symbolized in Figure 4-25.

4·25: Crosstalk Coupling in Parallel Lines

--- IC + 'L

A

Icrl L

I

I

Cm;*:.:

Lm

I
I

t

V

B

RT

......- - - - - - o V T

~

4·26: Calculated Cross Talk
tr

I

~----------~--------------Vo
(a)

Pulse On Line CO Beginning From C

0.8 V

~

(b)

Forward Crosstalk at B

-0.24 V

(c)

Backward Crosstalk at A

I

I
I

~---------2TO--~--------~

I

I

~------------~I---4--3TO------------------~1
-0.175V

(d)

I

3 TO + tr

1------ T o-----l

I

f - - - - T 0 + tr

--l---.r-----------------

(e)

Signal at 0

t =

0

TIME - -

82

Reflected Backward
Crosstalk at B

Forward and Backward Oosstalk

When a pulse propagating down line CD reaches any arbitrary point X, the
signal is capacitively coupled into line AB. The coupled voltage on AB causes current
(lC) to flow from the point of coupling to both ends of the line.
Current in the direction of A is called "backward crosstalk" and that toward
B is called "forward crosstalk." Coincident with capacitive coupling, the mutual
inductance of the parallel lines also couples current (l L) into line AB in the direction
of backward crosstalk.
The total forward crosstalk is IC - IL at point B. Since the parallel line
coupling is primarily inductive, current flows from point B causing a negative pulse
at that point (cf Figure 4-26). IC and IL are proportional in magnitude to the rate of
change of the signal propagating from C (driving function). Coupling occurs only
during the rise and fall times of the pulse as it propagates along CD.
Since the forward crosstalk propagates along AB at the same rate as the signal
on CD, the result is a pulse at point B lasting for the duration of the rise time of the
driving function. The amplitude of the resulting pulse is a function of the differenc~
between inductive and capacitive coupling. Normally, the reflection of the backward
crosstalk hides the small pulse at B.
Backward crosstalk current is IC + I L and is a function of line length and
velocity of propagation of the line. Backward crosstalk current starts at point A
simultaneously with the signal at C. The coupling continues for the duration of the
signal (TD) on line CD; at time TD the driving function is at point D, and also
appears coupled to the other line at B. The backward crosstalk then requires another
TD to reach point A. Therefore the duration of backward crosstalk is:
TB = 2 TD
The output impedance of the gate at point A (RS) is low- typically 5 ohms
compared with the line (Zo = 75 to 150 ohms), so the backward crosstalk is
reflected toward point B in proportion to the reflection coefficient.
Since the reflection coefficient for current, PI, is:

PI
if Zo

100 ohms and RS

5 ohms, then:

PI = +0.905 .

The reflected backward crosstalk reaches point B at the same time the driven signal
reaches point D, and is 2 TD in duration and about 0.9 (lc + IL) in current
amplitude. The positive reflection coefficient shows that the reflected current has
the same polarity as the backward crosstalk. This reflection results in the pulse at
point B (Figure 4-25) as shown in Figure 4-26d.
A similar analysis shows that if the gates at A and B were reversed so that the
receiving gate and terminating resistor were at point A, the results would be similar.
A positive crosstalk pulse would begin simultaneously with the driven signal at
point C and have a duration of 2 TD. The forward crosstalk would be reflected from
the gate at point B and would not appear at point A until 2 TD. This reflected signal
is normally not seen as it occurs at the trailing edge of the backward crosstalk.
83

Calculating Oosstalk Amptitude

Crosstalk amplitude V (X,t) may be calculated with the following equation (cf
reference 11, Chapter 7):
V (X, t)

=

d
KfX- [Yin (t - TD :)] +
dt
[ V.

In

where:

(t - TD X) - V· (t - 2 TD + TD X)]
Q

Q'

In

=_l(Lm
_Cm z)
2 Z
o
(Lm
--+ C Z )
4T Z
m

Kf (forward crosstalk constant)

0'

= -Q
-

Kb (backward crosstalk constant)

D

0

0'

Lm = mutual line inductance per unit length,
Cm = mutual line capacitance per unit length,
Zo
Q

X

= characteristic line impedance,
= line length = 10ft. for the following example,

arbitrary point along line,
arbitrary time,

Tn = total one-way line delay.
Also note that:
Co

= intrinsic line capacitance/unit length,

Lo = intrinsic line inductance/unit length.
Using the measured values Co ~ I pF lin, Lo ~ 20 nH/in, Cm ~ 0.446 pF lin,
and Lm ~ 10.3 nH/in for the cable under test, crosstalk can be calculated. The
calculations can then be compared with test data on the cable.

First:
and
so:

Zo
tpd
Tn

~
Co

~LoCo

141 ohms,
0.14 ns/in;

16.8 ns.

Substituting values into the appropriate equations above gives:
Kf = -0.06 ns/ft,
and:

Kb = 0.244.
84

Forward Crosstalk Calculation

Proceeding now with the calculation of the forward crosstalk,V f,in the line:

Vf(X,t) = KfX:
t

[Vin(t-TD~)J

'

where Yin (t) may be represented by:

=

Yin (t)

(fo (t) • U

(t)) -

(fo (t - t r) • U (t - t r )) .

Here U (t), the step function, has the values:
U (t) = 0, for all t

<

0,

= I, for all t

~

0.

U (t)

In this equation fo (t) describes the rising portion of the input pulse (Figure
4-26(a)), and since the pulse rises with a slope:

m::::::

Vo
tr '

Vo
then the first term,

== -

Tr

• t , for t ~ 0,

== 0,

for t

<

0.

The second term,

0, for t

<

t r.

Note that the second term of Yin (t) is zero until t == t r . The U function is being
used to "turn on" the first term at t = 0, and bring in the second term only for
t ~ tr:
Note that after time t r , the function Yin (t) remains at a value V0, for all values of t.
X
Substituting Yin (t) into the equation for V f (X,t), substituting (t - TD"Q) for
tin Yin (t), and evaluating at the end of the line (X = Q), gives:
Vf(Q, t)

=

KfQ

{d~

[fo (t - T D) U (t - T D)] -

d
dt

K fQ

[rVtrolJ • L~U

(t - Tn) - U ( t - (Tn + t r))\] .

85

Backward Crosstalk Calculation

This gives a pulse at point B equal in duration to the driven line rise time, t r , and
starting at time Tn as shown in Figure 4-26(b). The amplitude of this pulse is, for a
rise time tr = 2 ns, at point B (t = Tn):

K QV
V f (B) =

f

(-0.06) (10) (0.8) =

0

2

tr

-0.24 volt.

The backward crosstalk is calculated as follows:

Yb(X,t)

=

Kb (Yin

~ - T~X) -

For the same ramp function, fo (t)

Vo
Tr

Yin

~-

2TD +

T~X)J.

• t, as used with the forward crosstalk.

Taking X = 0 for point A:

(t - 2 TO) U (t - 2 Tn) + (t - tr - 2 Tn)

This gives a pulse at point A starting simultaneously with the driving signal at
point C. The leading edge of the backward crosstalk pulse (Figure 4-26 (c» is a ramp until
time tr. The pulse levels off until time 2 TO then slopes to the starting point at time 2 TO+
t r . The amplitude of this pulse is:
Vb (A)

=

Kb Vo

= 0.244 (0.8) = 0.195

volt.

These calculations assume the 10 foot line is terminated in its characteristic
impedance at points nand B. However, since the gate output at point A of Figure
4-25 is a low impedance, only a small voltage pulse is seen at the MEeL gate. As
previously discussed, 90% of the backward crosstalk is reflected to point B. The
amount of crosstalk at point B due to reflected backward crosstalk is calculated to
be: (- 0.9) (0.195) = -0.175 volts as shown in Figure 4-26(d).
Figure 4-27 lists measured crosstalk in a ten foot multiconductor cable for the
test circuit of Figure 4-28. Using all wires in the cable for signal lines causes a
prohibitive amount of crosstalk, as shown.
Several factors contribute to the discrepancy between calculated and measured
crosstalk. The characteristic impedance of the line is comparatively undefined
86

Measuring Crosstalk
4-27: 10Ft. Multiple Conductor Cable Crosstalk
CROSSTALK AT B
CONDUCTORS AT C

G)

(mV)

R
(OHMS)
150

1

240

2

360

75

3

420

50

1•

60

150

2' •
3'"

80

75

100

50

'With one wire in cable grounded at both ends
• 'With two wires in cable grounded at both ends
•• 'With three wires in cable grounded at both ends

G)

Compare with theoretically calculated example.

4-28: Cross Talk Test Circuit
-2.0 Vdc

MC10109

A

f-I">-----

MC10109

10'

1 or 0
Bundled Cable

50
-2.0 Vdc
-2.0 Vdc
R

MC10109

MC10109

,..--- C

o
50

-2.0 Vdc

because there is not a solid ground reference for the cable. Thus, placement of the
cable with respect to the system ground and other cables affects the characteristic
impedance. In addition, capacitive and inductive coupling will vary along the cable
due to the relative location of wires with respect to each other. The one other factor
not allowed for in the calculations is attentuation in the line which damps out the
higher frequency components of the signal, slowing the rise time of the signal as it
propagates along the line.
The 150 ohm terminating resistor gives an approximate impedance match, to
cut down overshoot and ringing. However, residual mismatch causes reflections to
return along the line. Such reflectioJ}s interfere with the signal by producing
distortion at the receiving gate input, and so limiting high speed operation of the
cable. Serious distortion occurs when the reflected signal coincides with a following
signal, i.e. when the transmitted frequency equals:
Frequency

1

=~
D
87

Reduction o[ Crosstalk

For the 10 foot line example just discussed:

f

2 (16.8)

29.8 MHz.

Test data coincides with the calculated performance to indicate that serious
distortion occurs around 30 MHz in the 10 foot cable. The previously computed
propagation speed of 1.68 ns/ft also closely agrees with the measured time of
1.65 ns/ft.
Crosstalk is reduced by supplying a ground reference in the cable. In a
multiconductor cable this may be done by grounding approximately the same
number of wires in the cable as there are signal lines. This measure reduces crosstalk
by a factor of 4 (cf Figure 4-27). Figures 4-29 and 4-30 show the crosstalk in the
circuit of Figure 4-28, and compare crosstalk of cables with and without one
grounded wire in the cable.
4·29: Crosstalk in Multiconductor Cable with No Grounded Conductor

I

I

Point B

J.
,
I,

V~

Crosstalk
Vertical Scale = 200 mV/cm

.....

r

Driving Signal
Vertical Scale = 500 mV/cm

Point C

Horizontal Scale = 20 ns/cm (both traces)

4·30: Crosstalk in Multiconductor Cable with One Grounded Conductor

r--

I

I

...

Point B

~~

r-J

,.
Point C

Horizontal Scale = 20 ns/em (both traces)

Crosstalk
Vertical Scale = 200 mV/cm

Driving Signal
Vertical Scale = 500 mV /em

Twisted Pair Cables: Single-Ended Use

The amplitude of crosstalk is independent of length for "long lines." Defining a
long line as having a propagation delay greater than 1/2 the input rise time gives a
"long line" length of 0.605 ft. for a 2 ns rise time waveshape:

Long Line Length

>

2 tpd
2
(1.65) (2)

0.605 ft. (for the cable just discussed).

4-31: Test Results for an 18 Inch Multiple Conductor Cable: Crosstalk

CROSSTALK AT B
CONDUCTORS AT C

1
2
3
1*
2**
3***

(mV)

R
(OHMS)

240
350
400
70
80
100

150
75
50
150
75
50

·With one wire in the cable grounded at both ends .
•• WIth two wires in the cable grounded at both ends .
•• ·Wlth three wires In the cable grounded at both ends.

Test results (Figure 4-31) show that crosstalk for an 18 inch multiconductor cable is
approximately equal to that for the 10 foot bundled cable shown in Figure 4-27.
However, since reflections damp-out much faster because of the lesser propagation
delay, the shorter cable is useful to 100 MHz.
Multiple conductor cables of this type (bundled) may be used successfully with
MECL lOK/lOKH if one-half the wires are grounded at both ends. However, the 100 mV
of crosstalk present with the grounded lines significantly reduces noise immunity.
The cable is also susceptible to external signals coupling to the entire cabl~. These
cause additional noise on the line. Thus, this cable should be used only when cost
or manufacturing techniques require it. Other cable types - coaxial, tri-axial,
ribbon, or twisted pair - are recommended wherever possible.
Twisted Pair Cable, Driven Single - Ended
Cables formed of twisted pair lines have a more defined characteristic
impedance than parallel wires. So, twisted pair can be terminated more accurately
at the receiving end, reducing reflections. Further, the speed of operation of
twisted pair is limited by attenuation rather than by any significant reflection
interference. Test results show a 10 foot length of twisted pair cable may be used
up to 70 MHz before attenuation reduces noise immunity by 100 mY. Propagation
delay is the same as for parallel lines - 1.65 ns/ft.
89

Measured Data: Crosstalk Between Twisted Pairs

Crosstalk for the twisted pair cable is comparable to that for the parallel wire
cable operated with half the leads grounded. This is because the higher switching
current (due to lower Zo of twisted pair) offsets the better ground of the twisted
pair. Crosstalk magnitude in a twisted pair cable is listed in Figure 4-32 for the test
circuit of Figure 4-33. If shielded -twisted pair cable is used, crosstalk is significantly
reduced (compared to unshielded) as shown in Figure 4-34 and Figure 4-35. Both
ends of the shield as well as the second wire of the pair were grounded in the test
whose results are shown in Figure 4-34.

4-32: Crosstalk for 10 Ft Multiple Twisted Pair Cable
CONDUCTORS AT C

R
(OHMS)

CROSSTALK AT 8
(mV)

1

60

75

2

80

39

3

90

27

Differential operation of twisted pair line offers advantages over the
multiconductor cable when sending higher frequency signals. When
single-ended (as shown in Figure 4-33), twisted pair is still susceptible
external to the cable_ Any noise coupled into the entire cable causes
reduction of noise immunity.

4-33: Twisted Pair Crosstalk Test Circuit

-2.0 Vdc

1 - - - - - 10'

---~

75

1 or 0
50

=

-2.0 Vdc

=

=

50

-2.0 Vdc

90

standard
operated
to noise
a direct

Shielded Twisted Pair

Since one-half the wires in a multiconductor cable should be grounded for low
crosstalk (comparable to the twisted pair), cable density is the same for both - two
wires per signal path. The use of shielded twisted pair significantly reduces crosstalk
and should be used in applications where crosstalk could be a problem. Differential
operation of twisted pair lines is definitely preferred over single-ended twisted pairs
for sending MECL signals between sections of a system.

4-34: Crosstalk for 10 Ft Multiple Shielded Twisted Pair
CONDUCTORS AT C

CROSSTALK AT 8
(mV)

R
(OHMS)

1

30

75

2

30

39

3

40

27

4-35: Crosstalk in a Multiconductor Shielded Twisted Pair Cable

_...

~

-

~

-

Crosstalk
Vertical Scale = 100 mV/cm

I-/-H

,"'-

-

Driving Signal
Vertical Scale = 500 mV/cm

Horizontal Scale = 20 ns/cm (Both Traces)

91

Conventional
pdntedsome
ci«uit
can be used
when designing
MECL 10K! IOKH. Shown is a demon_
stcation
boa,d two-sided
which ilIUSlmtes
of boaed
the capabilities
of MECL
10K seri"with
pans.
Operating
is 83
MHz.OSCHlator and a diVide by four counter, connected by a 12 inch microstrip line.
The circuitfrequency
consists of
a 'ing

Togetl>er withasan
o scillOSCo
the circuit
ilIust,. les pwpagation
dc1ay, edge specd, and synchronous flip-flop
perfo'mancc,
well
as series,pc,
parallel
and non-terminated
line connections.

92

CHAPTER

Power Distribution
Power distribution is an important factor in system design. The loss of noise
margin due to reduced power supply voltage or noise on the power supply lines
means a reduction in the circuit tolerance to crosstalk and ringing as discussed in
Chapters 3 and 4. Points to consider for overall system operation include total
circuit and termination power, voltage drops on the power buses, and noise induced
on the power distribution lines by the circuits and by external sources.
MECL circuits are designed to interface with each other over a wide power supply
voltage range without loss of noise margin (other than that due to reduced signal swing at
low voltage). However, iftwo circuits are at different supply voltages or on the same power
supply with a voltage offset between circuits, there will be a predictable loss of noise margin.
Figure 5-1 illustrates supply points for two MECL circuits (A and B). The
MECL circuits are most sensitive to voltage differences between Vees for the two
circuits. Any voltage drop on this power bus causes a direct loss of noise immunity
and should be avoided. Similarly, any noise on the VCC line not common to both
circuits may subtract from noise immunity. For this reason, VCC is normally
made to be the system ground - usually the most stable reference level in the
system.
The main causes of V CC offsets between circuits are:
•
•
•

inadequate power buses to handle the current;
separate supplies with common negative terminals operating'
slightly
different voltages (not recommended for system design);
separate positive grounded supplies with inadequate interconnecting ground
bus bars.

at

5·1: MECL Power Points

Vee
.. Circuit B .

93

Logic Level Variations
5-2: Changes in Output Levels and VBB with VEE
MECL lOKH

MECL 10K

MECL III

~VOH/~VEE

0008

0.016

0.033

~voL/4vEE

002

0.25

0.27

001

0.148

0.14

VOLTAGE

~VBB/6.VEE

A more common problem is with circuits which have a good ground, but which
operate with different VEE voltages. The loss of noise margin can be calculated from
the changes in VOH, VOL, and VBB as functions of supply voltage. Figure 5-2
shows the change in these levels as a function of VEE for the MECL families. The
change in the logic I output level is very small compared to the change in logic 0 as a
function of VEE. VBB is designed to change at one-half the logic 0 rate, to stay at
the center of the logic swing.
The following example illustrates the loss of noise margin due to circuits operating at
largely differing voltages. Worst case MECL 10K Series logic levels are used in the example.
If the driving gate is at -5.46 volts (+5% of nomina}), the output levels are:

= -0.984 volts,

VOHA min

(-0.980)

(0.016) (5.2) (0.05)

VOLA max

(-1.630)

(0.25) (5.2) (0.05) = -1.695 volts.

If the receiving gate is at -4.94 volts (-5% of nominal), the input levels are:
VIHA min

-1.105 + (0.15) (5.2) (0.05)

-1.066 volts,

VILA max

-1.475 + (0.15) (5.2) (0.05)

- 1.436 volts.

Worst case noise margin is therefore:
Logic 1: 1.066 - 0.984
Logic

0:

1.695 - 1.436

0.082 volts,

= 0.259 volts.

In this example, worst case noise margin in the logic I state was reduced from
125 mV to 82 mV by a 10% power supply difference. Although the logic 0 noise
margin here improved, it would in fact have been reduced if the receiving gate were at
the +5% supply voltage. Since the example assumed worst case voltages, an
additional 100 m V protection from noise could be expected in typical system use.
System Power Calculations
The total power required by MECL circuits consists of several parts: current
switch, bias supply (VBB), output emitter follower transistor, and terminating or
pulldown resistor power. Since the output emitter follower power and resistor power
are dependant on the method of termination for MECL lOK/lOKH and MECL III, they
are not included in the specified circuit power and must be added for total system
power.
nA

MECL Circuit Power Requirements

Gate power is calculated as the sum of the powers for each of the three sections
illustrated for the basic MECL 10K gate (Figure l-la). The bias driver, which furnishes
-1.29 volts to the base of Q5, dissipates about 5 mW / gate, as may be seen from the
following:
VEE - V BB - diode drop (0.79 V)
= -0.625 rnA
RBQ6

so:

3.24 mW (shared by 2 gates);

VEE -

and:

V BB

= -0.64 rnA ,

IQ6 • VEE

PTOTAL BIAS

3.32 mW ;

PBBI
- 2 - + P BB2

4.94 mW ,

per gate in a gate pair. For a single gate, the bias power is not shared, so the total
power for a single gate would be 6.56 mW.
Current switch power can be calculated in a similar fashion:

VEE -

V BB -

diode drop (0.79 V)

= -3.99

RE

mA ;

20.8 mW .

For one gate, the combined power dissipation would be: 20.8 mW + 6.6 mW
27.4 mW. However, the actual power dissipation is less than this on a package
basis, because the gates share a common bias driver, which is coupled through
emitter followers for isolation. A quad gate, for example, has a typical per gate
dissipation of 25 mW. Note that this power is constant over the full speed range of
operation. Transistor base currents were omitted from the above calculations as they
are beta dependent and have little effect on package power.
Typical input power may be computed when using a 50 krl input pUlldown
resistor. Input power for a logic} level (- 0.9 volts) on the input is:
(VEE -

Pin}

=

logic])2
Rp
95

=

0.37 mW .

Output Power

Input power for a logic f/J (- 1.7 volts) on the input is:

(VEE -

logic f/J )2
0.25 mW .

Rp

Totaling the input and gate power gives a typical 26.4 mW power per gate for a
dual four-input gate, with two inputs high on each gate.
The total supply current for MECL IOKH was designed to be the same as MECL 10K
thus producing the same power dissipation. For example the MC1OH101 quad OR/NOR
gate has the same current switch power dissipation of 20.8 mW per gate. Its bias driver
dissipates 25 mW or 6.25 mW / gate for a total dissipation of 27.05 mW / gate.
Output power is a function of the load network. It is usually co nputed for
circuits operating at a 50% duty cycle by calculating the I and f/J level output powers
and forming their average.
Figure 5-3 shows output transistor powers and load resistor powers for several
of the popular terminations. This power must be added to gate power when
determining system power. Unused outputs draw no power and may be ignored.
5-3: Typical Output Power

TERMINATING
RESISTOR

PQ7orQ8

P RESISTOR

P TOTAL

(mW)

(mW)

(mW)
9.3

150 ohms to -2.0 Vdc

5.0

4.3

100 ohms to -2.0 Vdc

7.5

6.5

14

75 ohms to -2.0 Vdc

10

8.7

18.7

50 ohms to -2.0 Vdc

15

13

28

2.0 k ohms to VE E

2.5

7.7

10.2

1.0k ohmto VEE

4.9

15.4

20.3

680 ohms to VEE

7.2

22.6

29.8

510 ohms to VEE

9.7

30.2

39.9

270 ohms to VEE

18.3

57.2

75.5

82 ohmsto Vee and
130 ohms to VEE

15

140

165

Calculations for power required with an external 510
resistor are:
VEE IR (logic 1)

So:

PQ7 or Q8

n

output pulldown

logic I level
= -8.43 rnA .

Rp (output)

OR logic I) (logic 1 level) = (-8.43)(-0.9) = 7.6 mW
(Q7 or Q8, depending upon which is connected to the 510
output pulldown);

and:

P5 10 ohm

(lR logic 1) (VEE - logic I level)

96

= 36.3

mW.

n

Design of the Power Supply

Similar calculations for a logic 0 state give PQ7 or Q8
P510 ohm = 24 mW. Averaging 0 and 1 level powers, gives:

11.7 mW and

P510n = 30.2 mW avg.;
PQ7 or Q8 = 9.7 mW avg.
Low impedance MECL III circuits require more input power because of their
2 kn input resistors. An average of 7.7 mW per used input must be added to the
power for the rest of the circuit:
(V EE -

logic 1 level)2
9.3 mW;

Pin 1 =

(VEE -

logic

0 level)2
6.1 mW.

Rin
Power Supply Considerations

MECL 10K and MECL III are guaranteed functionally over a + 10% power supply
regulation. Circuit speeds are optimized at a VEE of -5.2 V but other voltages may be
used. A more negative voltage will increase noise margins at a cost of increased power
dissipation. A less negative voltage will have just the opposite effect. The loss of
performance is negligible if supply voltage is held to a + 5% range. MECL lOKH however,
because of its internal voltage regulation is guaranteed both AC and DC over a 5% power
supply regulation. Therefore, noise margins and performance specifications of MECL
lOKH are unaffected by variations in VEE.
MECL lOKI lOKH, used without transmission lines, requires smaller switching current (less than 2.0 rnA) because of output pull-down resistors (typically 510 n) and
input current. Even so, worst case fluctuation in current requirements is less than 12
percent. In system use the fluctuation would normally be much less than 12%
because of complementary outputs and the low probability of all circuits being in a
logic 1 or 0 state at the same time.
Power supply requirements do become more important for MECL lOK/lOKH and
MECL III when they are used with transmission lines. In particular, a 50 ohm
parallel terminated transmission line sinks 22 rnA with a logic I output, and 6 rnA
with a logic 0. The 16 rnA differential between the two states can produce a
significant power supply current fluctuation. Such an effect should be considered
when specifying the power supply.
The current fluctuations are by no means insurmountable. Brief current
changes are smoothed by bypass capacitors at the circuits. However longer current
changes could cause noise on the supply lines unless a properly regulated supply is
used. Fortunately, the presence of complementary outputs and the typical 50%
distribution of output logic levels minimize current changes.

97

Distributing Power to MECL Circuits

High frequency noise and ripple from the power supply should be avoided
because they produce, in effect, differences in voltage levels among sections of a
system, and lead to loss of noise margin. As a rule of thumb, noise can be considered
"high frequency" whenever the mean wave length of the noise on the power lines
is not several times greater than the length of the longest power line. It is recommended that for operation with MECL, high frequency supply noise be held to
under 50 mV.
When multiple power supplies are used, the positive terminals should be
connected together with a large bus and the output voltages maintained as equal as
possible. It is desirable to keep the various supply levels within 50 m V of one
another.
System Power Distribution
When designing the system power distribution network, primary areas of
con cern are:
1. Maintaining a low impedance ground - without voltage drops;
2. Limiting VEE voltage drops;
3. Designing the supply lines to hinder external noise from coupling into the
system.
The following method is used to calculate voltage drops along a voltage bus which
has distributed loads (cf Figure 5-4).
5·4: Voltage Drops Along a Power Bus

Where:

and

S
r
n
A =
So =

average spacing of cards in inches,
resistance per inch of bus (ohms/in),
number of cards,
average card current load (amps),
distance from reference to first card (inches),
98

Calculating Power Bus Voltage Drop

the voltage drop to the first card will be:
V0

=I • R =

(n· A) (So • r).

Between cards I and 2 the voltage drop is:
V I = (n - I) A • (S • r).
Likewise:

So:

V2

(n-2)A· (S • r),

V3

etc.

V'n

n A So r +

n

I: Vn
I
n - I

n A So r + A S r I :

n.

Example:
5 inches,

let

S

= I inch,

A = 500 rnA,

r = 0.0004 ohms/inch,

n

= 10.

The voltage drop to package 10,
V,! 0

10- 2 + 2 X 10-

4

(1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9)

19mV.

This type of calculation should be performed for all voltage distribution
systems, and should also include edge connector voltage drops, etc. These
calculations will indicate the results to be expected for a proposed distribution
system, and the consequences of using a high resistance voltage bus are evident. The
equation may be modified to accommodate other conditions - such as unequal
spacing between cards or variations of loads among cards.
Laminated bus bars have advantages for power distribution to larger systems
because they minimize the effects of induced noise. Noise is reduced by the high
intrinsic capacitance of the laminated bus bars. Since each bus layer is separated by a
dielectric, the bus bar appears overall as a very large capacitor. Bus bar design using a
large width to thickness ratio ensures low self inductance. This type of power bus
system is available with various options from many manufacturers.
For large systems, power distribution should avoid ground loops. Figure 5-5
shows power distribution to a typical large system. The flow of power from the
supplies is via main bus bars directly to the ground plane or ground screen of
individual card racks and cards. This method minimizes supply losses which would
otherwise occur with power supplied through a series string of card racks.
99

Power Distribution for a MECL System

In addition to preventing large voltage drops along the supply lines, the power
distribution system must be designed to ward off external noise interference. All
noisy and high power devices such as relays and motors should use a separate power
supply and ground system. The ground systems are connected at the system ground
point which is normally at the power supply. Relays and solenoids should be diode
suppressed and motor brushes should be filtered. Other standard design practices
should also be used to eliminate these sources of noise.

5·5: Power Supply System

•

t

~

of

I

Power 2SUPPIY

+

NU~ber

+

I

_

Power

~~I~ _

I

,~
Pow", ;"pply

+

~

VCC

~

r

VCC

Electronic
System
Ground

,

,

Card Track (Gnd Plane)

I n Number
: of Cards

-

-

1

-

: n Numbe
I of Cards

(Gnd Plane or Screen)
- - - - +Card Rack Busbar 1

I

Main
Distribution
Busbar

In

Number of Busbars

I

I

+ Card Rack Busbar n

,r
+

- Card Rack B usbar 1

I

I n Number of Busbars
I

I

,.

VCC

VEE

Card Track (Gnd Plane)

Card
Busbar -

1

- Card Rack Busbar n

100

-

-

-

-

Card
Busbar
n

Backplane Power Distribution: Vcc and VEE

The mechanical sections of a system are commonly connected together with
another ground. The frame connecting the panels to the chassis is used for this
ground if good electrical conduction is made at points of mechanical contact. This
hardware ground is also connected at the common ground point (cf Figure 2-10).

Backplane Power Distribution
For systems using MECL lOK/lOKH circuits a common hard wired backplane is
often used. The wires are either soldered or wire wrapped to connectors and are
routed over a ground plane or ground screen. The ground plane is often formed by
a large printed circuit board to which the connectors are mounted, or else, the
ground plane is connected to the frame holding the card connectors. The metal is
left on one side of the board and forms the ground plane for the backplane wiring.
Alternatively, metal can be left on both sides of the board, to conduct both ground
and VEE. Ground plane circuit boards are commonly used over a metal ground
plane as a means of isolating the MECL circuit ground system from the mechanical
system component ground.
When a ground plane is not practical, a ground screen should be constructed on
the backplane. A ground screen is made by connecting bus wires (wire size
compatible with connector) to the edge connectors in a grid pattern prior to signal
wiring, as shown in Figure 5-6. About every sixth pin on the card edge connectors is
5-6: Ground Screen Construction

Edge Connectors

used as a ground, providing connection points for the ground grid. This
interconnection of ground points forms a grid network of approximately 1 inch
squares over which the signal lines are wired. A characteristic impedance for a wire
over ground screen of about 140 ohms can be expected, depending upon the exact
routing and distance from the ground screen. The capacitance of this type line will
be about 1 to 2 pF per inch, and series inductance will be about 20 nH per inch.
101

Distributing Power On a Logic Card

Point-to-point wiring is normally used instead of routing along channels, to shorten
the interconnecting paths and minimize crosstalk which would occur among parallel
signal paths. The system interconnecting methods of Chapter 4 are used in
backplane wiring over a ground screen.
The faster edges of MECL IIII I OKH require a transmission line environment for
connecting among circuit boards. One method is to use coaxial cable for interconnections,
and matched impedance connectors on the boards. Care must be taken when stubbing
off the cable using a connector' 'T" , because of the short stub length allowed with MECL
IIIIIOKH. Normally this is avoided in favor of wiring with a single output per cable.
MECL IIIIIOKH works very well with twisted pair lines if these lines are specified
to have a constant, defined impedance. Differentially driven twisted pair lines with an
MCl692 line receiver should always be used where there may be significant power supply
voltage drops or noise on the ground system. The board connectors used with the twisted
pair lines should be designed to minimize reflection from the interconnect point. Standard
edge connectors with the terminating resistor and line receiver close to the point where
the line meets the connector (within 1 inch) normally provide adequate termination points.
Although coaxial cable and twisted pair line do not require a ground plane in
the backplane for impedance matching, the ground plane must be retained in both
cases for a good circuit ground.
Multilayer backplane wiring (motherboard) is commonly used with MECL III.
Striplines and microstrip line interconnects are designed in the circuit board, along
with ground and VEE voltage planes. Matched impedance connectors are available to
permit interfacing between cards and the backplane motherboard without line
discontinuity. This technique is normally used when a system design is sufficiently
determined to minimize changes in the backplane wiring.

On - Card Power Distribu tion
Just as the backplane wiring, the method for distributing power on cards
depends on the logic family used. Standard double sided circuit boards with a good
ground may be used with MECL lOK/lOKH because of relatively slow edge speeds and
very low switching currents in the signal lines. A good ground is necessary to prevent
voltage drops and noise from reducing circuit noise margin.
Here's an example of a circuit board which would work well with MECL lOK/lOKH.
The various techniques can be modified to fit specific system requirements.
The majority of interconnecting wires would be on one side of the board. A
ground bus or modified ground plane with any remaining interconnections would be
on the other side. The -5.2 Vdc line is not as critical as the VCC line and may be
routed as necessary. The ground buses would be made of wide circuit board paths on
the card. The width should be kept as large as possible, with at least 0.15 inch of
width for each 10 packages recommended. A modified ground plane is made by
leaving the metal on one side of the board and etching only as necessary to run the
interconnecting leads for devices on the other side. The layout should be planned so
that such interconnecting paths will not cut off a section of the ground plane from
the ground inputs or isolate a section so that it is connected only with a narrow
metal strip to the rest of the ground plant.
For either method, circuit board grounding is simplified if several pins in the
edge connector are used for ground. A standard 22 pin connector could have four or
five evenly spaced pins on the connector allocated to ground.
102

On-Card MECL Design

Power supply bypass capacitors are used on the circuit boards to handle the
small current transients required by signal lines for charging stray capacitances.
Bypass capacitors also lower the supply impedance on the card, reducing noise on
the VEE line. Typically a 1 to 10 MF capacitor is placed on the board at the power
supply inputs, and a 0.1 to 0.01 MF RF type capacitor is connected between ground
and -5.2 V dc every four or five packages. RF type capacitors are recommended
because of their low inductance. Because of their nearly constant current
requirements, many MECL lOKI lOKH systems are built without using bypass capacitors,
and operate perfectly. However, the use of these capacitors will insure cleaner
supply lines, especially at top circuit operating speeds.
MECL lOKI lOKH systems use both standard double sided and multilayered circuit
boards. However, when using MECL lOKI lOKH, the ground plane described previously
is recommended. Such a ground plane permits low impedance signal lines (over the
ground plane) which may be terminated for optimum performance. Also, a ground
plane gives the solid ground necessary for suppressing the current transients arising
in parallel terminated lines and eliminates possible high frequency ground loops.
Ideally, the ground plane would fully cover one side of the circuit board. However
with MECL lOK/lOKH, ground planes covering greater than 75 percent of the board
surface area give good results.
The VCC I and VCC2 pins of MECL lOKI lOKH and MECL III packages should be
connected directly to the ground plane as closely as possible to the package. V ce 1
should equal VeC2 for best operation. If VeCl drops below VCC2 by more than
two tenths of a volt, the output devices could saturate and cause additional
propagation delays.
When designing the VEE line, care should be taken to prevent excessive voltage
drop in the line. Figure 5-7 shows the bus resistance per foot for micros trip lines.
This should be taken into consideration when designing large cards with high current
requirements. Use of bypass capacitors with MECL lOKI lOKH is strongly recommended
to handle the current transients occurring when parallel terminated transmission
lines are used. A 1.0 to 10 MF capacitor at the power supply inputs and 0.1 to
0.01 MF capacitors every four or five packages along the board give a low impedance
supply.

5-7: Bus. Resistance Per Foot for Microstrip Lines
0.50
0.40
0.30

I

~

~" """-

0.20
RESISTANCE/Ft
(OHMS)

~

,

................

'"""r-....

,~

"

~ r--.......~
Minimum

0.10

I

I

-I

I

I

I

I

I

I

1-......- f-- Maximum R

r-.......

""

I
I
./ Average R

R~ ............... ~ ".......
.........
I'-.......
.........

.........

I
r.......
.......

I ..........

r-....

-............

r--.. . .
0.05
10

1

1 oz. Cu; G 10 Material
(2 oz. Cu has resistance about 50%
lower than 1 oz. CuI

r-.......
20

30

40

50

WIRE WIDTH (MILS)

103

r-....
r-.......

60

r-......

['-.....

80

100

Multilayer Boards for MEeL III

Multilayer circuit boards are ordinarily used with MECL III. For small systems
(with few packages) or small test circuits, a double sided board with a good ground
plane may be used. With larger systems or systems operating above 200 MHz,
multilayer boards are recommended for two reasons: to eliminate ground loops
caused by the use of what would normally be ground plane areas as signal paths, and
to provide uniform transmission line characteristics. Multilayer boards can be used
for other advantages in MECL III systems - possible higher packing density and
shorter interconnecting lines.
The layout of a typical small MECL III multilayer board is shown in Figure 5-8.
When using multilayer boards, the correct use of ground and voltage planes leads to
specific benefits and eliminates serious problems. For instance, when adjacent signal
lines are switching, signal line crosstalk may occur. Crosstalk can be reduced by
using a voltage plane to separate successive layers of signal lines. Ground lines,
between parallel lines on a signal plane, connected to the ground plane via
plated-through holes, give additional protection against noise coupling.

5-8: Typical MECL III Multilayer Board Layout

Board Layer Orientation

111111111I111I111 ~------------------~

1111I1I11I111I111
Board Layout

104

The Terminating Voltage, VTT

If two successive layers are used for signal interconnects, the use of an
orthogonal system is suggested, i.e. interconnects running on one layer are
perpendicular to those on the other. This will facilitate layout and reduce crosstalk
problems. An associated ground plane can follow below to give ground reference to
the two layers of signal lines. VEE may be a separate plane or may be included with
one of the signal planes.
The multilayer board ground planes provide a non-inductive, capacitive
decoupling function. However, the thickness of the dielectric separating the voltage
planes may be too great to provide sufficient inherent low frequency decoupling. In
such a case, discrete capacitors are needed. These should be 0.1 to 0.01 J.LF in value,
and are to be placed every three to five packages, to minimize voltage transients
between the voltage planes (i.e. ground and VEE).

Vrr Termination Voltage Distribution
The generation of a separate -2 Vdc termination voltage, common to all termination resistors, may be advantageous in many system designs. This is an alternate
approach to the Thevenin equivalent resistor termination for each parallel termination,
in which two resistors are needed.
The decision to use a separate -2 volt supply will depend on the system size. If
it is feasible to provide a separate -2 volt supply, then lower termination component
count per termination (one less resistor) and a power saving (up to a factor of 4) will
be achieved. Since the VTT supply is only used to sink current through the termination
resistors, current regulation and ripple are not critical. A good rule to follow is to use
the same design practices for VTT as used for the negative supply, VEE. However,
if the system is small, cost may weigh against the use of a separate -2 volt supply. Also,
the short circuit interconnects of many small systems use only a single pulldown
resistor, and this reduces the need for a separate VTT supply.

105

Complex M ECl logic functions are exemplified by this microphotograph of the M C 10181 Arithmetic/ logic Unit die. The
array is a member of the M ECl 10K logic family - whose low power gate is permitting a higher level of sophistication in the
use of emitter coupled logic.

106

Thermal
Considerations
The electrical power dissipated in any integrated circuit forms a heat source in
the package. This heat source increases the temperature of the circuit die relative to
some reference point (normally 25 0 C ambient) in an amount which depends
upon the net thermal resistance between the heat source and the reference point.
Thermal resistance, 8, is the difference between the temperature of the junction and
the temperature of the reference point, per unit power dissipation. Thermal
resistance is the primary figure of merit for the power handling capability of any
integrated circuit package. Thermal resistance from "junction to case", 8 JC, and/ or
the thermal resistance from "junction to ambient", 8 JA, are the thermal parameters
most often specified for integrated circuit packages.
The junction temperature, T J, for a given junction-to-ambient thermal
resistance 8 JA, power dissipation PD, and ambient temperature T A, is given by:

If a heat sink with thermal resistance 8SA (sink to ambient) is used and the
thermal resistance from junction to case, 8 JC, is given, then:

where 8CS is the thermal resistance from the integrated circuit package (case) to the
heat sink. Due to the poor thermal conductivity of still air, the factor 8CS may be
significant if air voids exist. When using dual in-line MECL III packages that dissipate
more than 750 mW, 8CS should be reduced to a usable value by applying a good
thermal paste between the package and the sink.
All integrated circuits, including the high speed MECL family members, have
maximum allowable junction temperature limits. The MECL lOK/lOKH family has TJ
(max) =165°C in ceramic and 140°C in plastic, the MECL III family has TJ(max) =165°C
in ceramic and 140° C in plastic except for the MC1666 thru MC1670 which have 145° C in
ceramic. These limits are generally lower than for most other integrated circuits which may
have a TJ (max) of between 175 and 200°C. With very high speed MECL circuits, stray die
capacitances must be held to an absolute minimum. To do this, the on-chip interconnect
metallization is made narrow. Here the current density and junction temperature become a
significant concern to the integrated circuit device designer and require a lower junction
temperature limit.
Thermal resistance usually is not specified for digital integrated circuits though
maximum power dissipation is generally defined. The maximum ambient temperature rating has been the usual thermal limit of interest to the digital integrated
circuit user. The system designer using MECL should be aware of the device junction
107

Heat Flow

temperature, regardless of what his ambient temperature is. The lower the junction
temperature of a device, the higher the reliability and consequently the life of the
device; thus, system MTBF (mean time between failure) will be increased as junction
temperatures are decreased.
MECL Integrated Circuit Heat Transfer
The electrical power dissipated in an integrated circuit is the heat source for
thermal purposes. That is, the heat flow in watts equals the power dissipation in
watts. The power-dissipating circuit elements are within a very narrow region on the
top of the die (diffusion depths for MECL are shallow). The top of the die remains
isothermal within a few degrees for MECL power dissipation levels.
The major means of heat transfer from the top of the die to the outside
sur(aces of the package is by conduction through solids. Heat transfer through
bonding wires from the die to the lead frame is negligible.
Once heat is transmitted to the package, its transfer to ambient depends upon
the package mounting technique and its environment. If the integrated circuit
package is installed in, or attached to a heat sink, then heat is transferred mainly by
conduction to the heat sink, and then by convection and radiation from the heat
sink to ambient.
In the 16-pin dual in-line ceramic package (see figure 6-1b), used for MECL
lOK/lOKH and MECL III, the heat flows from the top of the die, through the chip and

6-1: MECL Package Dimensions
MECL III integrated circuits are available in the 16-lead ceramic flat package, Case 607 (suffix F), and
in the 16-lead dual in-line ceramic package, Case 620 (suffix L).
(a)

(b)

F SUFFIX
CERAMIC PACKAGE
CASE 607-04

L SUFFIX
CERAMIC PACKAGE
CASE 620-02

~tE~H==~~~~~==~~tN
~
I
I
t

.-\ I

~K~~A-l

NOTE
1 LEADS WITHIN 0 13 mm (0 005)
TOTAL OF TRUE POSITION
RELATIVE TO "A" AT MAXIMUM
MATERIAL CONDITION
MILLIMETERS
DIM MIN
MAX
A
610
699
C
076
203
0
025 048
F
oOB 015
G
1278SC
H
013 089
J
038
K
635
L 1880
N
025
R
038
S
762 83B

-

INCHES
MINt MAX
0240 I 0275
0030 oOBO
0010 10019
0003 I 0006
0050 BSC
0005 0035
0015
0250
0740
0010
0015
0300 0330

SEATING PLANE

STYLE 1
PIN
11
01 2
3
4
5
02 6
17
8
03 9
1 10
11
12
04 13
1 14

JF

COLLECTOR
BASE
EMITTER
NOT CONNECTED
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NOT CONNECTEO
EMITTER
BASE
COLLECTOR

108

NOTES
1 LEADS WITHIN 0 13 mm (0005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION
2 PKG INDEX NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT
3 DIM "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL
MILLIMETERS
DIM MIN
MAX
A
B

C
0

F
G
H

J
K
L
M
N

1905
622
406
038
140
2.54
051
020
318
737

1981
69B
50B
051
165
SSC
114
030
406
787

INCHES
MIN
MAX
0750
0245
0160
0015
0055
0.100
0020
OOOB
0125
0290

0780
0275
0200
0020
0065
BSC
0045
0012
0160
0310

-

15°

-

15°

051

102

0020

0040

Die Temperature Measurement

gold eutectic die bond, to the ceramic base. The optimum heat sink location would be in
contact with the bottom of the package. Due to the poor thermal conductivity of glass,
only a limited amount of heat is transferred from the ceramic base out through the lead
frame.
The difference between the temperature of the die and some reference point
per unit power dissipation, yields the thermal resistance. The method used to
measure the temperature of MECL devices is "internal temperature sensing" - by a
special MECL integrated circuit. It employs an independent diode diffused on the
chip. It is an easy method to use and calibrate, and has a voltage output that is very
nearly a linear function of temperature.
The sensing diode within the MECL package is calibrated as a function of
temperature by using the circuit shown in Figure 6-2. The forward VBE drop of the

6·2: Diode Calibration Circuit

v

MECL
Package

I

I
I
I

L - -

+------:--+--1

°c

Temperature Bridge

; Temperature Chamber
,

,.,.

".,..-

"~.,,

+
Control
IE

6·3: Typical Thermal Diode Calibration Curve
780
740
700
DIODE
FORWARD
VOLTAGE
DROP
(mV)

" I"-

660

...........

I"-

620

...........

~

""'"I"-

580
540
500

o

10

20

30

40

50

60

70

TEMPERATURE (OC)

109

80

...........

~

90

100

Determining Thermal Resistance

diode is recorded at stabilized oven temperatures between 0° and 1000 C with the
diode current held constant at 100 /lA. A calibration curve is plotted as shown in
Figure 6-3. This curve, along with the data recorded in the test setup of Figure 6-4,

6-4: Thermal Evaluation Test Circuit for 16-Pin
Dual In-Line Ceramic Package

I

20- 30--

Control
Circuit
Voltage
&
Current

I
oJ
I

__ -I

0.1 J.LF
L....----f-{

2

3

Control
IE

will produce data to plot TJ (OC), junction temperature, versus true power (watts).
The slope of the curve is the thermal resistance, eJ (OC/Watt), of the MECL case.
By recording the ambient temperature (T A in °C) during the test, the thermal
resistance from junction to ambient (8 JA in °C/W) may be calculated as:

where:

To obtain the thermal resistance from junction to case (() JC), an infinite heat
sink must be provided. This can be approximated by using a copper bar 3-3/4" X
110

MECL Packages - Thermal Characteristics

1-1/2" X 1/2" laid in thennal contact with the dual in-line l6-pin ceramic package.
Copper-constantin thennocouples should be placed in holes in the sink next to the
surface of the package. These thennocouples are used to measure the case temperature.
Figure 6-5 shows a sample set-up for an infinite heat sink.
The thermal characteristics are listed in Figure 6-6. This infonnation is based
on package characteristics included in the figure.

6-5: Sample Infinite Heat Sink

Printed Circuit Board

.~-=O~:::~~'B"
~~

-=

MECL Device

Thermal
Paste

6-6: Typical Thermal Characteristics for MECL Packages

THERMAL RESISTANCE VALUES FOR STANDARD MECL IC CERAMIC PACKAGES

THERMAL RESISTANCE IN STILL AIR
Package Description
No.
Leads

Body
Style

Body
Material

Body
WxL

Die
Bond

~JC

f/lJA
Die Area
(Sq. Mils)

Flag Area
(Sq. Mils)

(oC/Wattl
Avg.
Max

(oC/Watt)
Avg.
Max

8

DIL

Epoxy

1/4"

x

3/8"

Epoxy

2496

8100

102

133

50

8
14
14

DIL

Alumina

1/4"

x

3/8"

Gold

2496

N/A

140

182

35

56

Flat

Alumina

1/4" x 1/4"
1/4" x 3/4"

Gold

4096
4096

N/A

215

28

109
130
114

38
25

45
61

DIL

Epoxy

6400

165
84

14

DIL

Alumina

1/4" x 3/4"

Gold

4096

N/A

100

16

Flat

Beo

1/4" x 3/8"

Gold

4096

N/A

16

Flat

Alumina

1/4" x 3/8"

Gold

4096

N/A

88
140

'6
16

DIL

Epoxy

1/4"

x

3/4"

Epoxy

4096

12100

DIL

Alumina

1/4"

x

3/4"

Gold

N/A

3/8"

x

5/8"

Gold

4096
8192

24

Flat

Beo

24

Flat

Alumina

24

DIL

24

DIL

Epoxy

Gold

Epoxy

3/8" x 5/8"
1/2" xl 1/4"

Alumina

1/2" xl 1/4"

21

24

38

70

34

100

130

25

54
40

N/A

40

52

6

10

N/A

83
87

11
31

18
50

65

Epoxy

8192
8192

22500

64
67

Gold

8192

N/A

50

NOTES

(21 Body style DIL IS "Dual·ln-Lone"
(31 Beo body material IS only used for mlhtary temperature range products
(41 Standard mountlPQ methods
al Dual-In-Llne on Socket or PIC board wIth no contact between bottom of pkg and socket or PIC board
Bottom of package on dorect contact wIth non-metahzed area of PIC board

III

40

13

182
91

(11 All plastic packages use copper lead frames - ceramIc packages use alloy 42 frames

bl flat pack -

80

10

16

MECL dc Performance versus Temperature

MECL DC Thermal Characteristics
To fully understand the thermal effects on the characteristics of MECL circuits, an
explanation of the output level tracking and reference (VBB) tracking will be presented.
Some of the thermal equations offered are used mainly by a MECL integrated circuit
designer, but are presented here to illustrate what parameters are changing and how they
change as a function of temperature. Figure 6-7 shows the MECL III gate used for
equation derivation. For all calculations, an ambient reference temperature of25°C was
chosen. The MECL circuit has the following basic parameters which influence dc
performance: VBE, beta, and resistor variations with temperature.
The threshold voltage level (VBB) is most important and so an expression for
VBB as a function of VBE, beta, and resistor values in the bias supply is derived
first. Then, to analyze· the temperature dependence of VBB, a total derivative with
respect to temperature is found in terms of dVBE/dT, dJ31dT, dR l/dT, dR2/dT, and
dR3/dT.

6-7: Basic High Input Impedance MECL III Gate
VCC2

OR

Output

Output

Rp
50 k

VCC1

o

= VCC2 = Gnd

VEE = -5.2 Vdc

~--------~y~----------)
Inputs

If loop equations are written for the bias supply, the expression obtained for
VBB is:

R 1R 3{3 (VEE - V BE + 2eI» + R}R3 (VEE - V BE + 2eI»
{3 (R I R3 + R 2 R 3 ) +

-

(1)

112

VBB and 1 Level Dependence on Temperature

Differentiating with respect to temperature, T:
dV BB
dT

aVBB dR l
aR l
dT

= ----- +

aVBB dR

aVBB dV

aVBB dR3

aR 2

aV BE

aR 3

BE
2
----+ ------+ - - - - +
dT

dT

dT

aVBB ~
a~

(2)

dT

Solving equation (1) for VBB at 25°C using the parameters,
Rl

0.35 kn

R2

1.958 kn

R3

3.0 kn

VEE = -5.2 volts
~

VBE


=

100

= 0.745

volts

= 0.80 volts

Uunction drop)

we obtain:
VBB

=

(3)

-1.29 volts.

The partial differential equations for reducing equation (2) will not be solved
here due to their length. However a solution of (2) will show that the change of VBB
with temperature is:
dVBB/dT

+1.11 mVrC.

(4)

This threshold tracking level will always insure that VBB is centered between the
VOH and VOL output logic levels. As a result, noise immunity can be guaranteed
across the full operating temperature range.
Temperature variations in the two logic levels can be derived from the basic
equations for the MECL gate. The logic I level equation is simply a relation of VOH
to the emitter-follower base-emitter voltage drop (V BE) plus some further
dependence upon emitter-follower base current through the current-switch collector
resistor. It can be shown that the contribution by changes in ~EF and RC to the 1
logic level output is about 100 IlV
These changes subtract from the nominal
dVBE/dT of -1.5 mVrC.
The basic equation for the 1 logic level is:

rC.

(5)

Differentiating with respect to temperature and inserting the values discussed:
dV OH
dT
dV OH
dT

(-1)(-1.5mVrC)- 0.1 mVrC

+ 1.5 mVrC - 0.1 mV/oC
113

(6 )

(7)

¢ Level Dependence on Temperature
The logic f/J level can be calculated by developing the following equation from
Figure 6-7:

VOL (OR)

(8)
where:
VEE = - 5.2 volts,
V BEI

0.745 volts (bias driver transistor),

VBE2

0.870 volts (current switch transistor),

VBE3

0.810 volts (emitter-follower transistor),

ell

0.800 volts (bias driver diode drop).

Substituting values yields:
VOL (OR) = - 1.745 volts.

(9)

The logic zero level change with temperature can now be calculated from:

(10)

So,

dVO~tOR) =

(0.514) (-1.5 mV;oC)

0.771 mV;oC.

In normal operating temperature environments, the bias voltage shifts in such a
way that it always remains halfway between the logic levels. Figure 6-9 shows the logic
levels as a function of temperature for the MECL III gate.
The effects of temperature on MECL can be illustrated by a specific example.
Assume that within a panel, one card is operating near the inlet airflow duct at
25°C, and another interconnected card (remote from the air inlet) is at 35°C. Thus a
10°C thermal differential exists within the system. The 25°C device has a typical
VOH of -0.900 volts and a VOL of -1.700 volts. The 35°C device will have the
following typical levels:
114

Effect of Temperature Differentials on MECL

dV
VOH (35°C) = V OH (25°C) +

d~H (~T)
- 0.886 volts.

VOL (35°C) = (-1,700 mV) + (0.77 mVrC) (lO°C) =-1.692 volts.

This shows that a shift of only 14 m V took place in the logic 1 level and about
8 m V in the logic 0 level. The overall loss in noise immunity (N .1.) would be even
smaller than these figures - due to the positive threshold-shift. It is recommended
that thermal gradients be limited to on-card differentials under 25 0 C. If differentials
on a card get as great or greater than 25 0 C, then good thermal management has
not been employed. However when a differential of 35 0 C or greater exists between
panels or cabinets, another feature of MECL logic can be used to advantage: namely,
the availability of complementary output devices and line receivers allows a
differential mode of line driving and receiving which eliminates the loss of noise
immunity between units that have large temperature differences. The differential
transmission of signals on twisted pair is covered in detail in Chapter 4.
The change in threshold and output levels with respect to temperature for MECL 10K
and MECL IOKH are shown in fig. 6-8.
6-8: Change in levels due to Temperature

~VOH/~T

(mVrC)
~VBB/~T

(mVrC)
~VOL/~T

(mVrC)

Min

Typ

Max

10KH
10K

1.2
1.2

1.3
1.3

1.5
1.5

10KH
10K

0.8
0.8

1.0
1.0

1.2
12

10KH
10K

0
0.35
0.75

0.4
0.5
1.0

0.6
0.75
1.55

The measure of safety, noise margin (N .M.), is defined as the worst case input
threshold voltage (VIHA (min) or VILA (max) for which the output is still within
specified limits (>VOLA or >VOHA), as was indicated in Chapter I.
That is for MECL 10K and MECL III:
N.M. (logic ~ level)

=

VILA (max) - VOLA(max)

N.M. (logic I level) = VOHA (min) - VIHA (min.)
For MECL IOKH:
N.M. (logic

plevel)

N.M. (logic I level)

= VIL (max) - VOL(max)

=

VOH (min) - VIH (min.)
lIS

Worst Case Temperature Effects

As can be seen from the data in Figure 6-10, a worst case noise margin of 115 m V is
guaranteed for the dual in-line and flat ceramic package (both between -30 and 85° C with
packages at the same ambient temperature, T A). For MECL 10K, worst case noise margin
IS 125 mY and for MECL IOKH, worst case noise margin is 150 mY.
6-9: MECL III Logic levels versus Temperature
-0.6r----.-----.----.-----.----,,----.----~

VIHmax
vOHmax

-08~==+===4=~~~=t--~J_--t_--l
~---~vOHmm

vOHAmin

-1 0

-~~-vIHAmm

NI { NM{

Logic
Level
(Volts)

-1

2~--~----~----~----+-----r---~----~

- 1.4 I-----+-----t------+-----+-----I-----+-----:::l-- V I LA ma x
VOLAmax
NI{NM{ -1.6

-1.8

VOLmax

t===t==:t==+===t===1P==9;;;;;;;;::::tv

I Lmln
VOLmin

-2.0~

o

__~____- L_ _ _ _J -_ _ _ _~_ _~L-_ _~_ _ _ _~
75
25
50
TEMPERATURE

°c

6-10: MECL III DC Test Parameters
Fon:ing
Function
VIHmax

25 0 e
-0810
-0.960

85 0 e

Unit

ELECTRICAL CHARACTERISTICS

-0.700
-0890

Vdc

Each MECL III series device has been
designed to meet the dc specification

-1.065
-1.180

-0980
-1.095

-0.910
-1.025

Vdc

-1.485
-1.600

-1.440
-1.555

Vdc

VOLAmax

-1.515
-1.630

shown in the test table, after thermal
equilibrium has been established. The
circuit is in a test socket or mounted on

VOLmax
VOLmm

-1.650
-1.890

-1.620
-1.850

-1.575
-1.830

Vdc

IINLmin

0.5

0.5

0.3

/JA

VOHAmm
VIHAmm
VILAmax

VILmm
VILmln

I'

-30o e
-0.875
-1.045

Parametar
- VOHmax
VOHmln

a

printed

clrcu It

board

and

transverse

airflOW greater than 500 linear fpm
maintained. VEE = -5.2 V ± 0.10 V.

is

NOTE. All outputs loaded 50.n to -2.0 Vdc except MC1648
which has an Internal output pulldown resistor.

When calculating system noise immunity three factors must be taken into
consideration. These are: loss of immunity due to temperature differentials (as
above); power supply line losses, and power supply regulation (as shown in
Chapter 5); and signal losses due to undershoot and ringing on signal lines (as
described in Chapters 3 and 4). Proper attention must be given both to power
distribution and to thermal factors for any system. The reason is that losses derived
from these two areas directly subtract from the circuit's ability to withstand
external noise, and to function properly despite signal deterioration due to
mismatched lines.
Heat Dissipation Techniques
The majority of MECL users provide some form of air flow cooling in medium
116

Air Cooling

and large size systems. For this reason MECL lOK/lOKH and MECL III output levels are
specified with air flow at 500 linear feet per minute (or greater) across the package.
Many small systems and test circuits do not use forced air flow, but do use
convective cooling with ambient temperature air, or some form of heat conduction
- to avoid large thermal gradients.
As air passes over devices on a printed circuit board, it absorbs heat from each
package. Thus the ambient temperature of the air will increase as it flows from inlet
to outlet. The heat gradient from the first package to the last package is a function
of the package density, air flow rate, and the individual package dissipations. The
table in Figure 6-11 lists this gradient at various power levels for an air flow rate of
500 LFPM. These figures show the increase in junction temperature for each of the
16-pin DIPs as the inlet air passes over each device. Although Z-axis air flow
information is given, the figures are similar for air flow 90° from this axis, in the
plane of the PC board.
16-PIN DIP
POWER DISSIPATION
(mW)

TJ GRADIENT
(oC/PACKAGE)

200

0.4

250

0.5

300

0.63

400

0.88

6-11: Junction Temperature Thermal Gradients

DeVices mounted on 0.062" PC board
with Z axis spacing of 0.5" Air flow is
500 LFPM in the Z axis.

From the air flow curve of Figure 6-12, the 16-pin ceramic DIP has a e JA of
50°C/W (MClOlOlLQuad OR/NOR, Loaded with 4 50 ohm loads to -2 Vdc, mounted on
6-12: Typical Thermal Resistance versus Air Flow
200

~

180

'"

140

~

120

 t r/2.
The circuit of Figure 7-2 can be redrawn as shown in Figure 7-3 to include the
equivalent circuit of the MECL gate. The resistor, R o , is the output source

;-;;:e

MECL
Gate

VCC = +2.0 Vdc
VEE = -3.2 Vdc

7-2: MECL Gate Driving a Transmission Line

7-3: Equivalent MECL Gate Output, Driving a Transmission line

V?H = +1.22 Vy
I

VOL = +0.32 V ~

l.

VCC = +2.0 Vdc
VEE = -3.2 Vdc

122

Derivation of the Total Line Voltage

impedance (for MECL lOK/ lOKH it is 7 ohms, and MECL III it is 5 ohms). According to
theory, the rise time of the driving voltage source is not affected by the capacitance
of the transmission line. Except for skin effect and dielectric losses, the signal will
remain undistorted until it reaches the load. The equation representing the voltage
waveform going down the line as a function of distance and time can be written as:

V 1 (X, t) = VA (t) • V (t - Xtpd), for t

<

Tn '

(1)

where:

VA(t)

=

Es (t) (z

Zo

o + Ro

) ,

VA = voltage at point A,
X = the distance to an arbitrary point on the line,
Q

total line length,

tpd = propagation delay of the line in ns/unit distance,
Tn

Q tpd

'

Vet) = a unit step function occurring at t = 0, and
ES (t)

the source voltage at the sending end of the line.

When the incident voltage V I reaches the end of the long line, a reflected voltage,
Vi, will occur if RL =1= Zoo The reflection coefficient at the load, PL, can be
obtained by applying Ohm's Law.
The voltage at the load is V I + vi which must be equal to (11 + Ii) RL. But
11 = V I /Zo, and 1'1 = - V'I /Zo (the minus sign is due to V'I travelling toward the
source). Therefore,
(2)

By definition,

= reflected voltage

P

L
Solving for

V'

_ _1 •
incident voltage
VI

V't/V 1 in equation 2, and substituting in the relation for PL results in:
RL - Zo
PL = - - - RL + Z
0'

(3)

Similarly, the reflection coefficient at the source is:

(4)

Lattice Method for Finding Total Line Voltage

By summing the incident voltage, VI (eq. 1), together with similar voltage
contributions from the various orders of reflection (due to PL and PS), a general
equation for total line voltage can be written, and used to develop practical design
information:

(5)

Note that as time progresses, the U step function brings successively higher order
reflection coefficient terms into V (X, t). Successive terms may be. positive or
negative, depending on the resulting sign, and so damped ringing can occur. Equation
5 expresses the voltage at any point on the line, X, for any time, t. The equation can
be used graphically with a lattice diagram (as explained in References 5 and 6), to
find V (X, t).
Example 1. Figure 7-4 will be used to illustrate the lattice diagram method for

7-4: Lattice Diagram for a Typical Reflection Example

Ps

= -0.B2

PL=+0.13
Zo
V?H=+1. 22V
VOL = +0.32 V

T
J

l--

= 50 ohms

Vee = +2 0 Vdc
VEE = -3.2 Vdc

A

B

V A = 0.30 Vdc
IS = 4.6 mA

Vdc = 0.30 Vde
Ide = 4.6 mA
VB'" 0.30 Vdc
IL '" 4.6 mA

VA = 1.11 Vdc
IS = 20.B mA

t'" 0

t

= TO

VB'" 1.215 Vdc
IL = 1B.7 mA

t

=3

VB= 1.12 Vdc
IL '" 17.2 mA

VA= 1.13Vdc t=
O
2T
IS = 17.0 mA

124

TO

Typical Reflection Example: Lattice Diagram Discussion

finding V (X, t) and the use of equation 5. The source impedance of the MECL III
gate is 5 ohms, resulting in a reflection coefficient at the source of -0.82 for a line
impedance of 50 ohms.
The load resistor is arbitrarily chosen to be 30 percent greater (65 ohms) than
the characteristic impedance (50 ohms) so that reflections will occur. The resulting
reflection coefficient at the load is PL = +0.13. Two vertical lines are drawn to
represent the input of the line, point A, and the output of the line, point B. A line is
drawn from point A to point B before t = 0 to represent the steady state
conditions. Note that for V CC = +2 V and VEE = - 3.2 volts, the nominal logic
levels are approximately logic f/J = 0.3 volts, and logic 1 = 1.14 volts. (These power
supply conditions are used to permit convenient measurements when output
resistors are returned directly to ground). For steady state conditions, the line looks
like a short line with a resistance equal to Rdc. It can be assumed that Rdc is
negligible for this example.
The voltage and current at points A and B are the same initially, as shown in
the diagram. At t = 0, the voltage at the source switches from a logic 0 to a logic 1
level. The voltage term, VA (t), in equation 1 is:
I

VA(t)

(V OH

VI = 0.81 volt,

where:
VOL) = ES (t)

internal voltage swing in the circuit.

= ~VINT
Therefore, at time t = 0 a voltage waveform, V I = 0.81 volt, and a current,
11 = 16.2 rnA, travel down the line - as shown in the diagram by the line from
t = 0 to t = TD (TD is the time it takes for the wavefront to travel down the
length of line, Q). Next, a line is drawn from t = TD to t = 2TD. Voltage and
current values are indicated. Note that here the reflected current is negative,
indicating the current is flowing back toward the source; the reflection coefficient
for the current is a minus one times the reflection coefficient for the voltage.
To find the voltage at point B for t = TD all the voltages arriving at and
leaving from this point are summed. The same is done to determine the load current.
The process continues until the voltage at the load approaches the new steady state
condition - in the example, when t = 3TD. (The steady state logic I voltage is
actually 1.13 volts).
This example indicates that for a case in which the load resistor is 30% higher
than the characteristic impedance, 85 m V of overshoot and 10m V of undershoot
would occur. Generally, as far as noise immunity is concerned, only the undershoot
need be considered. The typical noise immunity (or noise margin) for a MECL
circuit is greater than 200 m V. Since the undershoot in this example was 10m V, the
typical noise immunity would exceed 190 m V. In actual system design, typically more
than 100 m V of undershoot can be tolerated. Regarding overshoot, 300 m V can
be tolerated, except in some early ac coupled flip-flops (MECL I and I I). This
restriction insures that saturation of the input transistor does not occur (if it did, the
gate would slow down). If a 100 ohm load resistor were used in Figure 74, the
resulting overshoot would be about 220 mV and the undershoot, about 80 mY. In
effect then, if the load resistor is twice the characteristic impedance, the noise
margin is typically 120 m V - which is more than acceptable for MECL circuits.
125

effect of the Termination Resistor

A slightly different situation can exist when the output of the MEeL gate
switches from a logic I to a logic 0. The output of the MEeL gate will turn off if the
termination resistor, RL, is somewhat larger than the characteristic impedance of the
line. For the conditions in Figure 7-4, the output transistor of the MEeL gate will
turn off at t = 0 for the negative going transition, when RL > 70 ohms.
An equation for the value of RL at which the gate will turn off can be derived
as follows. The maximum voltage change at point A, Figure 7-4, (due to turning off
the output transistor) is the product of the dc current in the line and the
characteristic impedance of the line:

The voltage at point A is also dependent on the internal resistance of the driving gate
Ro and the internal logic swing:

Equating the two and solving for RL:

(6)

Thus for the conditions given in Figure 7-4, the output transistor will turn off at
t

=

0 when RL =

1.22 (5 + 50)
-5
0.9

=

70n

.

IS

exceeded.

The case for which the MEeL output turns off is not in itself a serious
problem, although it makes a thorough analysis more difficult. Two reflection
coefficients must be used at the sending end, and a piecewise approach used in
determining the voltage reflections.
Example 2. The condition for a negative-going transition will now be analyzed
(cf Figure 7-5.) The steady state high logic level current is:
11.6rnA.

For the conditions shown in Figure 7-5, the use of equation 6 shows that the
load resistor is indeed larger than required to turn off the output transistor during a
negative transition.
To determine the voltage V 1 at t = 0, the following equation results from the
application of Ohm's Law to the circuit:
VA +3.2+V 1
)
V I = - ( Idc + - - - R -- - - Zo·
E
126

(7)

Lattice Diagram Method for a Negative-Going Transition

For the example shown, let RE =

00,

then:

(8)
Solving equation 8, V I = -0.58 volt. The implication of this result is that stubbing
off the line with gate loads in a distributed fashion is not recommended, due to the
reduced intital voltage swing. However, it would be acceptable to lump the loads at
the end of the line (as will be shown).
Since the value of the load resistor is greater than the characteristic impedance,
the voltage swing at the load resistor is greater than V 1 by the amount of PL V 1 (in
this example, 193 mY). When t = TD + T}, the voltage at B is equal to 0.387 volt;
so 82 m V of undershoot occurs. Undershoot on the falling edge is defined as the
amount of voltage step above the nominal logic f/J level of 0.305 volt. Overshoot in
the low logic state is defined as the amount of voltage change below the logic f/J level.

7-5: Lattice Diagram for Negative-Going Voltage Transition

PS1
+2.0 Vdc

PS2

.J

PL

c

~.82

=

+ 1.0 When

When output transistOr
is on.
transistor is off.

= +0.333

R02 =

00

Ro 1 = 5.0 ohms

MECLGate

. r; R01

c

5.0

n

Zo = 50 ohms

-3.2 Vdc

-3.2 Vdc

A

B

VA=1.16Vdc
IS = 11.6 mA
VB = 1.16 Vdc
IL = 11.6 mA
VA = 0.58 Vdc
IS = 0

VA = 0.31 Vdc
IS = 2.31 mA

t=O

t= TO

VB = 0.387 Vdc
IL = 3.87 mA

t= 3 TO

VB = 0.283 Vdc
IL = 2.83 mA

t= 2T O

127

Voltage Waveforms as a Function of Time

In Figure 7-6, the voltage waveforms at points A and B of this example are
shown as a function of time. To be more realistic, the waveform in the figure is
shown to be a negative-going ramp rather than an abrupt step function. The term,
T 1, is the amount of time it takes for the waveform at A to switch to the level at
which the output transistor turns off. The fall time of the signal would have been
longer by an amount equal to T'l

(1.16 - 0.305)
T I, if the termination resistor
(1.16 - 0.58)

had been 70 ohms or less.
The reflected voltage waveform leaving point B at t = TD arrives at point A at
t = 2TD. The source impedance is very high initially (Ps = +1.0), with the output
transistor being in the off condition until the voltage at A falls to 0.32 volt. Then,
the source impedance changes to 5 ohms (Ps = -0.82). The following formula may
be used to determine the point at which the transistor turns on:
(valid prior to transistor
conduction),
where V 1 is now the incident voltage approaching the source and
change in voltage at the source necessary to turn the transistor on.

(9)

~ V source

is the

7-6: Voltage Waveforms for Points A and B in Example 2
1.4

1.2

VA
VOLTAGE
AT A
(VOLTS)

:-~6V

1.0
0.8 0.6

,\"58 V

-

0.4 -

_0.32 V

1.2 -

0.31 V

1.16 V

1.0 +-

VB
VOLTAGE
AT B
(VOLTS)

0.8 -r

0.6

r

0.4
0.2 +-

Undershoot
82 mV

t
0.305 V J t

0.387 V

Overshoot 91 mV

rd

~

t

Steady
State
Logic
t = TO TO + T1

128

t = 2TO 2TO+T1
2TO+ 0.67 T,

0.28 V

1-:- 0 .214

V

t= 3T O 3TO + T1
3TO + 0.67 T1

Propagation Delay Calculations

In this example the actual voltage change for conduction to occur is:
= 0.32 - 0.58 = -0.26 volt. Therefore, the voltage waveform approaching the source (193 m V) can be broken into two signals, VII = -0.13, and V 12 =
-0.063 volt. The reflected voltage due to VII is V'll = -0.13 volt, and for V12,
the reflected voltage is V' 12 == (-0.82) (-0.063) == +0.052 volt. The two reflected
voltages of opposite polarity at point A going toward point B are the reason for the
.6V source

0.13)
(
3T D + ( 0.193 TI see

increased overshoot of short duration at point B, when t

Figure 7 -6).
The steady state voltage reflection that occurs after t = 2TD + T 1 is the sum
of -0.13 volt and +0.052 volt, equal to -78 mV as shown in Figure 7-5. The steady
state voltage reflection can be calculated using the relation:

V'

PS2.6 Vsource

(10)
Equation 10 may be illustrated by solving for the steady state reflection voltage
att = 2TD + Tl:

V'

(+ 1.0) (0.32 - 0.58)

(0.32 - 0.58) (

C ~)
+2

1 +
2

+ (-0.82)

~0.193

~)~
00

~= 78 mV .

From the analysis of Figure 7-5, it is concluded that the MECL gate can safely
drive the transmission line (Zo == 50 ohms) with a 100 n load resistor and with the
gate loads lumped at the end of the line, since less than 100 m V of undershoot
occurs. The remaining noise margin will be typically greater than 100 m V.
Signal Propagation Delay for Microstrip and Strip Lines with
Distribu ted or Lumped Loads
The propagation delay, t d, has been shown in Chapter 3 to be 1.77 ns/ft for
microstrip lines and 2.26 ns/n for strip lines, when a glass epoxy dielectric is the
surrounding medium. The propagation delay time of the line will increase with gate
loading and the altered delay can be derived as follows. The unloaded propagation
delay for a transmission line is tpd = LoCo . If a lumped load, Cd, is placed
along the line, then the propagation delay will be modified to tpd:

J

JLoCo
129

H
I +

d

C

o

= tpd

_red
VI + c: ' (11)
0

Effect of Capacitances on Propagation Delay

where Lo and Co are the intrinsic line inductance and capacitance per unit length.
Therefore, the signal propagation down the line will increase by the factor of:

_/Cd
VI + C":"o .
A MECL gate input should be considered to have 5 pF of capacitance for ac
loading considerations (includes stray capacitance). If 4 gate loads are placed on a
1 foot signal line, then the distributed capacitance, Cd, is equal to 20 pF/ft or
1.67 pF jin. As an example, assume that it is desired to find the propagation delay
increase for a 50-ohm microstrip line on a glass epoxy board. From Figure 3-7
assume that the line width is chosen to be 25 mils; then the dielectric material
should have a thickness of IS mils to yield Zo = son. From Figure 3-8, the
capacitance of the line is 35 pF 1ft. Therefore, the modified propagation delay would
be:

lpd

1.77 ns/fl \} +

~~

= 2.21

ns/ft .

For a 50-ohm strip line on a glass epoxy board with a IS mil spacing between
the strip line and ground plane, a 12 mil width would be required (cf Figure 3-9).
From Figure 3-10, the strip line would exhibit a capacitance of 41 pF 1ft.
The modified propagation delay for such a strip line would be:

lpd

= 2.26 ns/ft ~I

+

;~

= 2.75

ns/ft .

Notice that the propagation delay for the strip line and the microstrip line change by
approximately the same factor when the separation between the line and ground
plane, and the characteristic impedance are the same. However the line wid th of the
strip line is less (by a factor of 2) thar. the microstrip line for the same characteristic
impedance.
It should be noted that to obtain the minimum change and lowest propagation
delay as a function of gate loading, the lowest characteristic impedance line should
be used. This will result in the largest intrinsic line capacitance. With MEeL lOK/lOKH
the lowest impedance that can be used is Llbout 35 ohms (Vrr = - 2.0 volts,
RTT = 35 ohms).
According to theory (Reference 1), whenever an open line (stub) is driven by a
pulse, the resultant undershoot and ring are held to about 15 percent of the logic
swing if the two way delay of the line is less than the rise time of the pulse. The
maximum line length, Qmax, may be calculated lIsing the equality:
Qmax

=

tr
2tpd

(inches) ,

where tr is the rise time of the pulse in nanoseconds, and tpd is the modified
propagation delay in nanoseconds/inch from equation 11.
130

Maximum Line Length Calculations

A quadratic equation for maximum line length for G-l 0 fiber glass epoxy microstrip conductors may be written in terms of CD Co and tr as:

2

tt

CD

max +

C

max +

CD
C
Qmax

Qrnax - 1 1.1
= 0, (for microstrip lines), (12)
o
where CD is total gate capacitance.
An equation for maximum open line length for a strip line (using G-IO fiber
glass epoxy material) can be written in a similar fashion. The result is:
Q

2

Q

2

- 7.1 tr

=

0,

(for strip lines).

(13)

o

Using the lattice diagram, it has been found that the rule of thumb used to
derive equations 12 and 13 should be modified for an open line because the incident
voltage doubles at the end of the line. This results in a faster rise time at the
receiving end of an unloaded line than at the driving end. An approximate value of
maximum open line length can be generated from equations 12 and 13 if the rise
time that is substituted into the equations is multiplied by an adjustment factor,
0.75. This maintains an approximate overshoot and undershoot of less than 35% and
12% respectively.
To demonstrate how equations 12 and 13 may be used, the maximum open
line length will be computed for a 50 ohm line with a fanout of one MECL 10K gate.
Using the equation tpd = ZoCo, the line capacitance, Co' is found to be Co = 2.96
pF/in for microstrip, and Co = 3.76 pF/in for strip line. For a fanout of one,
CD is equal to 5 pF when the device is in a socket. The rise time for MECL 10K is 3.5 ns
which means that a value of tr =0.75 X 3.5 =2.6 ns should be used in the equations. Solving
equations 12 and 13, Q max = 7.9 inches for a 50 ohm microstrip line and Qmax = 6.2
inches for a 50 ohm strip line.
Equations 12 and 13 can be very useful in finding the approximate maximum
line length under various conditions. However if overshoot or undershoot differing
from the above values is specified, equations 95 and 103 (derived later in this
chapter) should be used for defining maximum line length. The exact voltage at the
end of an open line with loading is also derived later in this chapter, and leads to
equation 87. Using that equation, a computer program has been written in which the
maximum line length is calculated when maximum overshoot and undershoot are
specified. Figures 3-13, 3-14, and 3-15 show the results of the program. Note that
the tables give the maximum line lengths for fanouts of 1, 2, 4, and 8 for various
types of lines with a wide range of characteristic impedances.
The maximum line lengths are also given for various characteristic impedances
in the backplane. The characteristic impedance of the backplane should be between
100 and 180 ohms if aground screen is used. For MECL 10K from Table 3-13,5.9 inches of
open backplane wiring can be driven for a fanout of one.
It should be remembered that these line lengths are based on 100 m V maximum undershoot, and are not absolute maximum lengths with which MECL circuits
will operate. It is possible to use longer unterminated lines than shown - the tradeoff being an associated loss of noise immunity due to increased ringing.
From these calculations, it can be concluded that lower impedance lines result
in longer line lengths before termination is required. The lower impedance lines are
preferred over higher impedance lines because longer open lines are possible, and the
propagation delay down the line is reduced. In addition, more stubbed-off gate loads
can be driven with a terminated line due to its higher capacitance per unit length.
131

Time Domain Reflectometer Measurements of Microstrip Line

Microstrip Transmission Line Techniques,
Evaluated Using TDR Measurements
The time domain reflectometer (TDR) employs a step generator and an
oscilloscope in a system which might be described as "closed-loop radar" (cf Figure
7-7). In operation, a voltage step is propagated down the transmission line under
investigation. Both the incident and reflected voltage waves are monitored on the
oscilloscope at a particular point on the line.
OSCI LLOSCOPE

-

I

7·7: Time Domain Reflectometer (cf Reference 7)

II

STEP
GENERATOR

Transmission System Under Test
Bridging

Tee

The incident voltage step, Ei, is a positive edge with an amplitude of I volt and
a rise time of 30 ps. It is generated by a tunnel diode, which has a source impedance
of 50 ohms (HP 1817 A sampler, or equivalent). Also, the output edge has very little
overshoot (less than ±5%).
This TDR technique reveals the characteristic impedance of the line under test.
It shows both the position and the nature (resistive, inductive, or capacitive) of each
discontinuity along the line, and signifies whether losses in a transmission system are
series losses or shunt losses. All of this information is immediately available from the
oscilloscope's display (cf Reference 7). An example of a microstrip line evaluated
with TDR techniques is shown below.
TDR Example 1.

Board material:

Norplex Type G-IO;

Dielectric thickness:

h

0.062 inch;
0.0014 inch;

Copper thickness:
Dielectric constant:

5.3 .

er

The formula for the characteristic impedance given in Chapter 3 was:

87

Je r +

1.41

(
In

5.98 11 )
0.8 w + t .

(14)

For a line width, w == 0.1 inch, the characteristic impedance of the line is calculated
to be 51 ohms. A board was fabricated as shown in Figure 7-8(a) to the dimensions
specified above. Figures 7-8(b) and 7-8(c) show the incident and reflected
132

Measurements: Impedance
7-8: TDR Determination of Line Characteristic Impedance

f----------

4.5" - - - - - - - - - - - l

Input Connector

G'oundPI.n'~------------------------------------------~~~

Termination
Resistor = 50 ohms

Line for 20 = 50 ohms

(a)

Vertical Scale = 500 mV/cm
Horizontal Scale = 2.0 ns/cm

!

Connector

P/OIV = 0.2

Termination Resistor

-50-ohm Termination

I~I-----+--t---t(b)

Incident

Vertical Scale = 200 mV /div
Horizontal Scale = 0.6 ns/div

P/OIV = 0.021

Line
Under
Test

Termination Resistor

r--'r-~--+--'--.-~--~--.--~--'

(c)
50-ohm Reference

Connector

Vertical Scale = 20 mV/div
Horizontal Scale = 0.4 nsldiv

133

Oosscheck with Calculated Impedance

waveforms observed with the TDR. The vertical scale is calibrated both in terms of
the voltage and the reflection coefficient, P. Eq ua tion 3 can be rearranged to
determine the characteristic impedance of the line:

P) · Zreference

1 +
Zline == ( I-P
where:

(15)

characteristic impedance of the line under test,
Zreference

impedance of the known line.

The 50 ohm reference point is shown in Figure 7-8(c). The mean level of the
reflected waveform due to the line has a P == +0.01. Substituting values into
equation 15 permits calculation of the line impedance:
1 + 0.01)
( 1 _ 0.01 • 50 ohms

51 ohms,

which agrees closely with the calculated value.
The reflected voltage due to the connector is ±40 m V. The line reflects a
voltage of ±25 m V due to variations in the characteristic impedance of the line. The
reflection of 88 mV shown for the termination resistor (P == 0.088) is due to the
inductance of the resistor. It was calculated (by methods to be shown later) that the
inductance of the resistor was less than 0.9 nH.
In these experiments, the input waveform comes from a tunnel diode generator
which has a rise time of 28 ps. There is some attenuation of the signal noticeable as
it reaches the termination resistor (tr = 80 ps at the load). When driving the line
with a MECL III gate with a rise time of 1 ns, the reflection due to the inductance of
the resistor would be much less (about 10m V).
TDR Example 2: An equation can be derived to determine the maximum reflection
voltage due to the inductance of the resistor leads. The circuit shown in Figure 7-9
will be used in the derivation.

7-9: Circuit for Determining the Maximum Reflected Voltage
Due to the I nductance of the Resistor Leads

Ej

Ej
___

Slope=mgr~
T1

o
T1
t = 0

I

s js the LaPlace

operator

134

Derivation: Maximum Reflection Voltage due to Resistor Inductance

The reflection coefficient at the load is:

(RL + sL) - Zo
(RL + sL) + Zo

s +
s +

RL- Zo
L
RL + Zo '

(16)

L

where s is the LaPlace operator for jw. The driving voltage will be represented as:
(17)

where Vet) is a step function occurring at t = O. Taking the LaPlace transform of
equation 17 gives:

(18)

The reflected voltage at the load is then the product of the driving voltage and the
reflection coefficient (both in the transformed plane):

(19)

E refl (s)

Taking the inverse LaPlace transform yields:

(:~
[R::O~O)2 (:~:~:)

E

ren

(I) ;

[R ::O~o)2
+

+

: ::) I

-(R~:O~O)2)

e-

(RL + Zo)t]
L
mV(t) -

e

(I - T I )

(20)
135

TDR Measurement of Resistor Inductance Effect

The maximum reflection voltage occurs at t

= T I. Then , for R = Zo:
2Zo)
- TI

mL

Erefl(t

= T I ) = Ereflmax = 2Zo ( 1- e

L

.

(21)

This equation relates the maximum reflected voltage, which can be measured by
TDR,' and the inductance, which can then be calculated for the circuit of Figure
7-9.
TDR Example 3. This example indicates how to measure the effect of resistor leads
using the TDR. Figure 7-1 O(a) shows the construction of a mic~ostrip board used for
7-10: Effects Due to Termination Resistor Leads
Line Under Test

Input Connector

t

"'~

OITermination
Resistor = 50 ohms
~
(With Long Leads)

o

1
....__________________
(a)

PIDIV = 0.21

~

Ground Plane

/

Reflection Due to the Inductance
of the Resistor's Leads

V

(b)

I
i

-'--~~~_L_L......J

_

_±._L......J~_L_..L__.J

___

TI M E

Vertical Scale = 200 mV Idiv
Horizontal Scale = 0.6 ns/div

,..,

..

•

,..,.

S
5L =?

RS = 50 ohms.

)

Zo = 50 ohms

~

RL = 50 ohms
,..,
~

..

•
(c) Equivalent Circuit

136

0-----

TDR Measurement of Ground Plane Effects

determining the effects of a resistor with 1" lead lengths. The reflected voltage
determined from the TDR measurement is 480 mV (see Figure 7-10(b)). The rise
time at the input to the line is 28 ps but it is lengthened to about 80 ps as the
wavefront reaches the termination resistor.
The time, T 1, associated with the slope of the input voltage rise at the
terminating resistor can be approximated as:
tr
Tl ~ 0.80

(22)

100 ps.

The inductance can be computed by using equation 21, giving L
6 nH. Additional
information can be obtained from the decay of the reflection shown in Figure
7-l0(b). The decay lasts about 0.3 ns, implying a time constant of about
0.3 nsl5 = 60 ps (using 5 time constants as a decay time). The calculated time
constant for an inductance of 6 nH is: L/2Zo = 60 ps. The two results agree closely..
When driving the line with a MECL III gate - rise time = I ns - the reflection
would be only 50 mY. Most carbon resistor types will have less than 10 nH of
inductance. This inductance gives a reflection < 75 m V when the line is driven by a
MECL III gate. Note that the reflection is positive, indicating that the noise
immunity of a MECL gate connected at the load would be unchanged.
TDR Example 4. Experiments have also been performed to determine the effects of
a ground plane on the characteristic impedance of micros trip lines. Figure 7-11
7-11: Effects of Ground Plane Discontinuities
Ground Plane

Epoxy Glass Only

Termination
Resistor = 50 ohms

Line Under Test = 50 ohms

P/OIV = 0.05

!

Zc for

Q = 2.5"

~-r--~~--4-~--~--~~--~-.

Termination Resistor

50-ohm Reference

Connector

Horizontal Scale = 0.4 ns/div
Vertical Scale = 50 mV/div

137

Implications for Ground Plane Design

illustrates what happens when the ground plane width under the transmission line
abruptly drops to the width of an active line. The TDR waveform shows that a 12%
reflection occurs due to this discontinuity in the ground plane.
Using equation 15 the impedance of the 2-1/2 inch-long strip can be calculated
as:

+ 0.12 • 50

68 ohms.

- 0.12

Figure 7-12 shows a curve that approximates the change in the characteristic
impedance of the line for various ratios of ground plane width to active line width.
Note that when the ground width is greater than 3 times the line width, the
characteristic impedance is constant according to equation 14.
7-12: Variation of Microstrip Impedance as a Function of
Ground Wtdth -;- Line Width
1.6

,

1.4

Zc

"

'" ""

1.2

i'--

Zo

1.0

i---

Zo - Characteristic impedance of line
with OOground plane.

0.8

rZc - Characteristic impedance of line
with limited ground plane width.

0.6

I

I

I

I

o

I

I

3

2

4

Ground Width
Line Width

A related experiment was performed to find the reflection due to a ground
plane near the active line, but not directly under it. The test configuration and test
results are shown in Figure 7-13. As indicated by the TDR measurement, the
reflection is about 36%. Again using equation 15, the impedance of the 2-1/2 inch
strip can be calculated:

+ 0.36
1 - 0.36

• 50

106 ohms.

The reason for the reflection is the change in the characteristic impedance
along the line resulting from the ground plane not being under part of the active
line. In such a region, capacitance of the line to ground decreases while the
inductance of the line increases, the net result being a higher characteristic
impedance.
It must be remembered that the TDR input waveform has a rise time of 28 ps.
Consequently, in a real logic circuit situation where, perhaps, a MECL III gate with a
1 ns rise time is driving the line, the reflection would actually be less than 27%, not
36% as in this example. This can be determined by scaling the value of P found with
l38

Another Ground Plane Discontinuity

the TDR waveshape in Figure 7-13(b), with a I ns rise time. When the length of the
ground plane discontinuity is less than the distance travelled by the signal during its
rise time, then the reflection coefficient can also be calculated as:
2Q tpd
for - - tr

pI

<

(23)

the propagation delay time of the line in ns/in.

where:

the rise time of the signal in ns,
the length of the discontinuity in inches,
the reflection coefficient for 2Qt d/tr ~ I
(in this case the value found wit~ the TDR waveshape
with tr = 28 ns).
7-13: Effects of Ground Plane Discontinuity

i
I nput Connector

Q =2.5"i

/EPOXYGlaSSOnI Y

Y

!

I~----I::::L=__"'~=_==-.-----=~'
.
=
r...-

G,ound

PI,nY-

Termination
Resistor

'\;ne Unde' Te,,· 50 ohm'
(a)

P/DIV = 0.2

...

-Zc

t

r~

,,,",

tr

r

.....

\... ~

.-..A

(b)
E1

Vertical Scale = 200 mV/div
Horizontal Scale = 0.8 ns/div

139

= 50

ohms

TDR Observation of Hybrid Divider Reflections

For a discontinuity in the ground plane of 2.5 inches length, a propagation
delay of the line of 0.15 ns/in, and a MECL III gate with 1 ns rise time, the percent
reflected voltage can be calculated. From Figure 7-13(b), P is found to be 0.36.
Using equation 23,
P'

= 2(0.36) (2.5) (0.15) = 0.27 .
(1)

Therefore, the reflection would be 27%. For a MECL 10K series gate, with a rise time of 3.5
ns, the reflection would only be 7.7%, and a MECL lOKH gate with a rise time of 1.8 ns, the
reflection would be 15%.
TDR Example 5. Another measurement was performed, as shown in Figure 7-14, to
observe the reflections due to the use of a hybrid divider. The construction of the
7·14: Hybrid Divider

20 = 100 ohms

e r = 5.3

2

o

~-+--~--~~----.

t = 0.0014"
h = 0.062"
RL=1000hms

Zo-50ohm,

~--------r--------------+--~~
1-------2" - - - - - I

G round Plane

(a)

P/DIV -- 0 2

t

2

(b)

E

3

~

No Mismatches Appear
Due to the Crosstalk
Between the Lines

1

L

io'"

- - - - TIME
Horizontal Scale = 200 mV/div
Vertical Scale = 0.4 ns/div

140

Reflection Due to Crosstalk

microstrip board used is shown in the figure. Note that the 50 ohm line branches
out into two 100 ohm lines. A reflection of 4 percent is observed at point 2 where
the junction occurs. Notice that the resistor exhibits a reflection of -8%, due to
capacitance of the resistor.
Previously it was found that the 50 ohm resistor was inductive. Both results
agree with Reference 8 in which it is stated that the lower values of resistors «75 n)
exhibit inductance, while the higher values behave capacitively. These effects are
also shown in the data in Figure 4 of Chapter 4. Note that no mismatch appears due
to crosstalk between the two 100 ohm branches, because of their wide separation.
Figure 7-IS(b) shows the reflection due to the construction of Figure 7-IS(a)
where the two 100 ohm lines have been brought close together. The reflection at
point 2 is now equal to 8% arising from the cross coupling of the two lines. Crosstalk
is discussed in References 5, 9, 10, and II.
7·15: Hybrid Divider With Crosstalk Problem

f----2" --->o.f-----2" - - - - I

Er

h

Zo = 50 ohms

(a)

P/DIV = 0.2

t

1

-r-

--2

--3

r-~-~-tr-~-h-~4-~~-~~

(b)

Horizontal Scale = 200 mV/div
Vertical Scale"" 0.4 ns/div

141

= 5.3
t = 0.0014"
= 0.062" s = 0.08"

Impedance In a Qrcuit With Oosstalk

Even mode or odd mode characteristic impedance (Zoe or Zoo) can be
considered to exist in a circuit with crosstalk. One, Zoe, is due to the strips being at
the same potential and carrying equal currents in the same direction. The other,
Zoo, is due to the strips being at equal but opposite potentials and carrying equal
currents in opposite directions. The backward crosstalk voltage, VB, on a passive line
is given in Reference 10 as:

(24)

where E 1 is the signal propagating down the active line. Formulas are given in
References 9 and 12 for calculating Zoe and Zoo. The backward crosstalk voltage
shown in Figure 7-15(b) at point 2 is equal to 8% of the incident voltage EI. Since
both lines are active, the crosstalk due to one active line is 4% of E 1 for a spacing of
80 mils. Reference 5 should be consulted if information concerning crosstalk on
microstrip lines is desired. There, curves are given from which the backward
crosstalk can be predicted. (For example, Figure lOin Reference 5 may be used to
predict the backward crosstalk for Figure 7-15(a) as 11 %).
Crosstalk is not ordinarily a problem when using MECL IlIon microstrip or
strip line circuit boards, when line spacings are greater than 30 mils. Crosstalk theory
is well described in Reference 11. In it, the mutual inductance and capacitance
between two lines are used to determine the crosstalk coefficient. Crosstalk theory is
presented in some detail in this handbook in Chapter 4, "System Interconnections".
Forward crosstalk is normally much smaller than the backward crosstalk on
microstrip lines - except for very long lines (>5 feet). Forward crosstalk does not
exist at all on strip lines, since they are made with a homogeneous medium, so that
the inductively and capacitively induced currents cancel (Reference 10).
The backward crosstalk coefficients for various types of microstrip lines on
glass epoxy boards are shown in Figure 7-16 (cf also Reference 5). The backward
crosstalk coefficient is equal to:

(25)

the inductive coupling,

where:
CM
tpd

the capacitive coupling,
the propagation delay of the line per unit length.

TDR Example 6. The graph data in Figure 7-16 will be used to determine the
percent of crosstalk coupling for the circuit of Figure 7-15. From the dimensions of
the lines given in Figure 7-15(a), KB is found to be 0.055 from the graph. This
means that if one line (the active line) were driven with a signal, the other line
(passive) would have a coupled signal of 5.5% of the amplitude on the active line, in
a direction opposite to that of the driving signal. Since both 100 ohm lines are active
142

Data for Determining Microstrip Crosstalk
7-16: Backward Crosstalk Coefficient for Microstrip
Lines on Glass Epoxy Boards (G-10 Material)
1. 0

= Dielectric

h

Thicknes (MILS)

~

o.

~ ~ ~~
1~
"r--..

KS'
CROSSTALK
CONSTANT

""

'"'" 1\

"I"-" 1'\r\. I\. ]\

"-

"f\I" rd\,

I\. 1\

1\

\

0.01

1\

1\

1\

1'\

I\~ '\

1\

1\

h

= 59.0

43.5

1\ 1\\30.5
, 25.6

1\

\

\

\

1\

~
1\
8.3

0.001
10

100

1000

s, LINE SPACING (MILS)

simultaneously, the reflection observed on the TDR is twice as much, or 11 %. From
Figure 7-15, the actual crosstalk can be seen to be about 8%.
In very high speed systems, the exact shape of a line can be important, if
reflections are to be kept to a minimum. The arrangement shown in Figure 7-17(a)
has been used to investigate the behavior of two different line shapes. For one line,
corners are sharp. This permits the width of the line to be larger at corners than
elsewhere. Figure 7-17(b) shows that a -7.5% reflection occurs at point 6 due to the
lowered characteristic impedance at the corner. For the other line, the corners are
rounded to produce a constant line width. Figure 7-17( c) shows that a constant line
impedance exists for the second line. Note that an inductive reflection, as discussed
before, does occur at the end of the line due to the inductance of the resistor. In
conclusion, it is desirable to have smooth> rounded line edges and constant line
widths when designing transmission lines for high speed systems. Resistor leads
should be kept short to minimize termination inductance.
143

Effect of Microstrip Line Shapes
7-17: Reflections Caused by Signal-Line Shape Variations

RL = 50 ohms

,/

~

Gmund PI.n.

Zo = 50 ohms
I nput Connector

5

2
(a)

PIDIV =

(b)

0.051

2

A. ..... 4.~ ~

- y' '"

~A

....

4

3

r

I' ,

"

-

A.

'V'

)

\f\.i
V

'if

.,...

v

~

- - - TIME
(Relative Scale)

6
-.-

5

-,.-

(c)

... '.It,!!
'V ~¥

A

~

J

,

.l;

'(flY'

~

II

""'"

,~A I.~
...
~

.........

V"

- - - TIME
(Relative Scale)

144

Reflection Due to Loading

The Effect of Loading, on a Parallel Terminated Transmission Line
For designing high speed systems it is useful to understand the effects of
loading a transmission line with MECL circuit inputs. Some tests were performed to
determine the equivalent loading effects of a MECL gate load. The input impedance
of the MECL gate is high and may be assumed to be purely capacitive as far as
reflections are concerned.
Accurate knowledge of gate input capacitance is necessary to develop accurate
loading rules. A test setup, similar to that for a TDR, was used to determine the
amount of reflection that occurred when driving four MECL III gates (MC l660L cf Figure 7-18). The amount of reflection that occurred at the probe was found to
7-18: Test Setup for Measuring the Reflection From Four MECL III Gate Loads

1/2 MC1660

(4 Places, In
Sockets)

EH122

PULSE GENERATOR

~ 6dB Pad

510

r

VCC = 1.65 V
VEE = -3.55 V

510
510

1/2"

~

510
510

Zo = 50 ohms

10 ns

'---~----

~2.5 ns~

510
510

R
50

510
E1 = 0.85 V
Tr = 1.0 ns 10% to 90%
PW = 40 ns

be 275 mY, in a direction indicating it was due to a terminal capacitance, CT- A
formula may be derived so that the amount of this capacitance can be calculated.
Figure 7-19 shows the equivalent circuit which will be used for the derivation of
7-19: Circuit for Driving the Maximum Reflected Voltage Due
to the Capacitance of the Gate Inputs

Zo = 50 ohms

E out

*Total Gate Capacitance

145

Derivation of Maximum Reflection Amplitude

such a formula.
The reflection coefficient at the load is:

P L (s)

ZL - Zo

R
sRCT .+

- Zo

R

ZL + Zo

+ Zo

sRC T +

(R - Zo) - sRZoCT
(R

(26)

+ Zo) + sRZoC T

From equation 18, the LaPlace transform of the input voltage can be found to be:
(27)

The reflected voltage at the load, in LaPlace notation, is:

s

2(

S

R)

Zo +
+ RZ C
o T

m

(

S)

1 - e -T 1

.

(28)

Taking the inverse LaPlace transform yields:

The maximum reflection occurs at t T l , Then for R = Zo, we obtain:

m ZoC

eref! (I

=

T 1)

= E refl max = -

2

T(~ - z20~T)
- e

(30)

Equation 30 exhibits a relation between the maximum reflected voltage and the
effective capacitance causing reflection, CT, in the circuit of Figures 7-18 and 7-19.
The reflected voltage was measured to be - 275 m V and from equation 22, T I is
found to be 1.25 ns. Thus the total capacitance, obtained from equation 30, is
CT = 17.2 pF. Since stray capacitance, Cs , is approximately 4.0 pF, the capacitance
146

Determining Effective Capacitance

due to the gate loads is the difference between CT and Cs i.e., 13.2 pF, or 3.3 pF per
gate input.
For comparison, an RF vector impedance meter was used to measure the input
capacitance of a similar 4 gate setup at a frequency of 50 MHz. The total
capacitance measured 20 pF. Since the stray capacitance for this configuration
measured 6.5 pF, the capacitance due to the four gate loads is 13.5 pF, or 3.38 pF
per gate input. It is felt that the two methods agreed well enough with each other to
say that the equivalent load of a MECL III input is 3.3 pF.
MECL lOK/lOKH series elements were also tested. It was found that a MECL
lOKI lOKH gate input measured 2.9 pF using the RF vector impedance meter. Using the
reflection method of Figure 7-18 and equation 30, the capacitance of a gate input was found
to be 2.7 pF.
If printed circuit cards are used without sockets, 3.3 pF per MECL III gate input and
2.9 pF per MECL lOKI lOKH gate input should be used. These values will be used in later
calculations.
It was shown in equations 12 and 13 that the maximum length of an unterminated line (stub length) is a function of loading. Figures 3-13,3-14, and 3-15 are a
tabulation of some values of permissible lengths versus fanout and logic family.
However, in most designs it becomes necessary to increase the line length beyond
the distances specified in the table. It has been shown that for long lines, 2TD (line)
> tr (pulse), a termination resistor will reduce or eliminate reflections. In a practical
situation, a MECL gate driving a transmission line must feed other gates along that
line. So it is important to be able to determine the effects of individual gate loads on
the line.
There are two ways of placing gates on a parallel terminated transmission line:
one is called "distributed" loading, the other "lumped" loading. Figure 7-20 shows
an example of a parallel terminated line with a lumped load at the end. The term TD
7-20: Driving a Parallel Terminated Line

VTT = -2.0 Vdc

A

B

147

Distributed Loading

represents the delay of the line. Since a full logic swing is available all along the line,
parallel termination permits distributed loading to be placed anywhere along the
line.
The change in characteristic impedance of a line caused by gate loads being
distributed along the line can be calculated. For a lossless line the characteristic
impedance of a transmission line is:
(31 )

where Lo is the intrinsic inductance of the line and Co is the intrinsic capacitance of
the line, both per unit length. The MECL gate has a high input impedance so that
only the capacitive effect need be considered for ac conditions. The characteristic
impedance of a transmission line altered by gate loading, Z~, is:

(32)

where Zo is the original line impedance defined in equation 31 and Cd is the
distributed gate capacitance. The propagation delay per unit length of a lossless
transmission line is:
tpd =

J LoCo

(33)

Rearranging, and using equation 31 gives:

(34)
Example. An application of the foregoing relationships and rules can be seen in the
following design problem. Given: a 68 ohm microstrip line 8 inches long. It is
desired to drive four MECL III gate loads spaced equally at 2" intervals along this
line. These loads are, of course, "distributed" loads. The microstrip line is on a glass
epoxy board which has a dielectric constant, e r , of 5.0. It is necessary to determine a
value for a parallel terminating resistor which will essentially eliminate reflections on
the line.
First, the propagation delay of the microstrip line can be found using the
relation from Chapter 3:
tpd = 1.017 JO.4 75 e r + 0.67 ns/ft = 1.77 ns.ft = 0.148 ns/in ,
in this case. Using equation 34, the line capacitance, Co is found to be:
0.148
68

= - - = 2.18 pF/in.
14R

(35)

Terminating Distributed Loads

Four MEeL III gate loads are equivalent to a load capacitance of 13.2 pF
which is distributed along 8 inches of line. Therefore, Cd = 13.2 pF /8 in. =
1.65 pF lin. Substituting these values into equation 32 gives:
Z' =
o

68
51.5 ohms.
+ 1.65
V
2.18
Thus, a 51 ohm termination resistor would be acceptable for terminating the 8
inch 68 ohm microstrip line with four distributed MECL III gates. The resulting
circuit is shown in Figure 7-21.
The driving gate shown in Figure 7-21, besides driving the long transmission
line, can also drive many lines (no limit) as long as the length of each stub does not
exceed the limits of Figures 3-13, 3-14, or 3-15. For instance, if a 50 ohm microstrip
line were used with MECL III to connect the driving gate to 1 gate load in one
direction, and to four gate loads in another direction (in addition to the loads shown
in Figure 7-21), then from Figure 3-15 the maximum permissible stub lengths are
1.6 and 0.7 inches, respectively (of Figure 7-22). It should be noted that the four

,11

7-21: Example Illustrating Distributed Loading
Driving

Gate

Zo

~

68 ohms

- 2" -------1-- 2"

-1
51

-2.0 Vdc

7-22: MECL III Gate Driving a Long Transmission Line with Distributed
Loads, and Short Stubs at the Driving Source

Zo

~

68 ohms

B

A

-+---2" -+---2" ----t--- 2"--...j
50

-2.0 Vdc

Zo'" 50 ohms

lAO

Computing Maximum Load Capacitance

gates on the stub (Qmax = 0.7 inch) could be lumped at the end of that line,
without the need for any other changes.
In order to determine the amount of reflection which can be tolerated on a
line, the following development is presented. Reflection is, of course, caused by gate
loading which produces a change in the impedance on a section of the transmission
line. The equations to be developed use distributed line theory - an approxima te
method, but one which gives very accurate results, as verified in Reference II.
The reflection coefficient given in equation 3 can be revised to take into
account the reflection due to the altered characteristic impedance produced by
loading:

P

Substituting the expression for Z~ given in equation 32 yields:

P

_r-cct

(36)

+Vl +~

From this equation, it is possible to find the maximum load capacitance that
can be distributed or lumped on a length of transmission line. Further, the length of
transmission line for distributing loads will be assumed to be the stub length defined
in equations 12 and 13. This length of line will limit reflection discontinuities caused
by differences between distributed and lumped loads. However a rule is needed
which can be stated for a particular value of transmission line, to specify a limit for
the number of gate loads distributed or lumped along an arbitrary length of line.
For a maximum reflection of 20% (P = -0.20) equation 36 may be solved for
the ratio of Cd/Co, giving:
1.25

.

(37)

Since Cd is the distributed gate load capacitance per unit line length, it may be
written that:
(38)

where CD is the total gate load capacitance. Substituting into equation 37 yields:

1.25 Qmax .

(39)

Maximum Loads Related to Maximum Line Lengths

For a 50 ohm microstrip transmission line, on a glass epoxy board, with
MECL III gates, with Co = 2.96 pF lin, and tr = 1.1 ns, equation 12 may be used
to find Qmax ~ 2.5 inches. Then substituting into equation 39 and solving:
CD = 9.2 pF. This means that up to 9.2 pF can be distributed or lumped along any
2.5 inches of 50 ohm microstrip line using MECL III. Two MECL III gate loads can
be used along any 1.8 inches of line for a carefully laid out board, or two MECL III
gate loads and 2.6 pF of stray capacitance can be distributed or lumped along any
2.5 inches of line.
For a 50 ohm strip line on a glass epoxy board and using MECL III gates, with
Co = 3.77 pF/in and tr = 1.1 ns, equations 13 and 39 may be used to find
Qmax ~ 2.0 inches. Then substituting into equation 39 and solving, CD = 9.4 pF.
This means that up to 9.4 pF can be distributed or lumped along any 2.0 inch
portion of 50 ohm strip line when using MECL III gates. If 3.3 pF per gate input is
used, then from equation 39 two gate loads can be lumped or distributed along any
1.4 inch portion of a 50 ohm strip line.
It is seen from these calculations that strip line has an advantage over
microstrip: it can be used for driving more gate loads per unit length than
microstrip, granting the same amount of reflection in each case. This is due to strip
line having a larger capacitance per unit length. Figure 7-23 gives values for the
maximum capacitance that can be lumped or distributed over any length (Qmax) of
line for MECL III, MECL lOK/lOKH and high speed MECL II.
As an example of how Figure 7-23 can be used, suppose 68 ohm microstrip lines are to
be used with the MECL 10K series. From the Figure, 21 pF of capacitance of five gate
loads can be lumped or distributed over any 7.7 inch portion of the line. The rise times
shown in the figure are characteristic of the particular logic family and were used in the
calculations to obtain the data.

7·23: Maximum Capacitance That Can Be Lumped or Distributed
Over a Length of Terminated Transmission Line ~ax'

CHARACTERISTIC IMPEDANCE OF TRANSMISSION LINE
COAX
STRIPLINE (e r

= 5.0)

MICROSTRIP (e r

= 5.0)

(e r

= 2.2)

50n

68n

90n

50n

68 n

90n

50n

9.4

6.9

5.2

9.2

6.8

5.1

9.4

2.0

2.0

2.0

2.5

2.5

2.5

3.0

MECL III

c max

(pF)

2max (In)
tr (ns)

= 1.1

MECL 10K
C max (pF)
2max (in)
tr (ns)

29

21.5

16.2

28.6

21

15.9

29

6.2

6.2

6.2

7.7

7.7

7.7

9.3

15.1

11 0

8.4

14.8

10.9

8.2

15.0

3.2

3.2

3.2

4.0

4.0

4.0

4.8

= 3.5

MECL 10KH
C max (pF)
2max (in)
tr (ns) =1.8

151

Output from Series or Parallel Terminated Lines

Analysis: Series Terminated Lines Compared to Parallel Terminated Lines
The propagfltion delay increase due to gate loading when a line is series
terminated is about twice as large as for a comparable parallel terminated line.
Equation I I gives a fairly close approximation for the propagation delay of a
parallel terminated line with loading. This equation was:

(11 )

The output waveform at the end of a series terminated line or at the end of a
parallel terminated line can be derived from an equivalent circuit using Thevenin's
Theorem, assuming the line is long (2TD » t r ). Figure 7-24(a) shows a parallel
terminated transmission line circuit, along with the waveform driving the line.
The equivalent open circuit voltage of the line is twice the input voltage and
the Thevenin resistance is the impedance of the open line at the load looking toward
the source. The Thevenin equivalent for a parallel terminated line is shown in Figure

7-24: Parallel Terminated Transmission Line, and its Thevenin Equivalent

"Total Gate Capacitance
E'

E1 20
.
1 "" R - - - ; E1 IS the voltage change at the base of the emitter-follower driver transistor.
0+

20

(a) TransmiSSion Line

r---------------l
20

I

I
I

I

I

I::;:

=

!

2.,It)

L _______________

I

I

I

CT

= 20

~

j

r---------------l

I
I
I

I

I

I

I
I

I
I

2

I

I
I _______________
=
I
L
~

(b) Thevenin EqUivalent

152

General Derivation of Line Output Voltage

7-24(b). Figure 7-25 shows the Thevenin equivalent for a series terminated line. Note
that the impedance (Zo) of the series terminated line is twice as large as that for the
parallel terminated line. A general equation can be derived for the output voltage
assuming the impedance in the circuit to be R. Then a substitution for R will give
the equations for both types of lines.
Writing the equation around either Thevenin equivalent loop:
1
iR +--

CT

f

t

dt .

(40)

o

7-25: Thevenin Equivalent of Series Terminated Transmission Line

r---------------l
I
I

I

I

20

I

I
I
I
I

e,(t)

I
IL _______________
-=I
~

But also:
(41 )

Equating the equations and taking the LaPlace transform of both sides gives:

(42)

But:

f

t

idt

o

or

I(s)

Eout(s)::::-CTs .

(43)

Therefore:

(44)

153

Transmission Line Output Voltage: Series Terminated Line

Solving for Eout(s):

(45)

which reduces to:

(46)

Taking the inverse LaPlace transform yields:

U(t) -

(47)

Equation 47 defines the output voltage for a series terminated transmission
line when R = Zo ; it defines the output voltage for a parallel terminated transmission line when R = Zo/2.

From equation 47 the equation for the series terminated line can be written:

E'

+ _1 (t)
TI

for t

:S

T1 '

(48)

and:

for t

154

>

T 1 ' (49)

Voltage Output from Parallel Terminated Line; Line Delays

where El is defined in Figure 7-24. The equations for the parallel terminated line
can also be written:

f

E'

+

(t)

for t

1

:s T 1

.

(50)

and:

(51 )

If the input voltage is assumed to be a step function, then the equation for the
output voltage for a series terminated line can be written as:

(52)

and for a parallel terminated line:

(53)

To derive the equation for the additional propagation delay due to gate loading
at the end of the line, equations 52 and 53 will be used. A more exact equation can
be derived using equations 48 through 51 but the analysis is more difficult due to
the complexity of the equations. Letting eout(t) = 0.5 E} and solving for t, we
obtain a propagation delay time of:
tpd

= 0.7 ZoC T

for series termination,

(54)

for parallel termination.

(55)

and:
tpd = 0.35 ZoCT

These additional line delays should be added to the existing physical line delay
as expressed in equation 34 to obtain total system line delay. To derive the equation
155

Terminated Lines: Output Rise Time

for the output rise time, t ro ' knowing the input rise time, tri, equations 49 and 51
will be used. The output rise time is defined as the time it takes for the output
voltage to travel from 10 to 90% of its final value. T 1 is defined as:
(56)
Substituting into Equation 49, rearranging, and taking the natural log of both sides,
the output rise time at the end of the transmission line is obtained:

for series termination.

(57)

Doing the same thing with equation 51 :

, for parallel termination. (58)

Equations 56 and 57 may also be used to solve for the output fall time by
substituting the input fall time, tn, in place of trio
Example. An example will be shown to illustrate the use of equations 54 through
58 using MECL 10K gates. Figure 7-26(a) and (b) shows comparable setups for series and
parallel termination. The load gates at point B were placed in sockets. The total
capacitance at point B is CT = 20 pF which takes into account the gate capacitances, socket
capacitances, as well as interconnect and stray capacitances. The propagation delay due to
the transmission line from A to B is 1.75 ns. The rise and fall times at point A, due to the
MECL 10K driving gate, are tri = 3.5 ns, and tfi = 2.8 ns. From equation 54, the
propagation delay increase due to the series termination is: (0.7) (50 ohms) (20 pF) =0.7 ns.
From equation 55, the propagation delay due to the parallel terminations is half as much,
0.35 ns. Therefore, the total propagation delay from point A to B is 2.45 ns for series
termination, and 2.1 ns for parallel termination.
The rise and fall times at point B can be calculated from equations 56, 57, and
58. The mathematical 10 to 90% rise time at point B is 4.65 ns for series
termination, versus 4.1 ns for parallel termination. The fall time at point B is 4 ns
for series termination versus 3.35 ns for parallel termination. Measured test results
agreed closely with the calculated values.
Equation 11 could have been used to calculate the propagation delay from A to
B for the parallel termination arrangement. Solving for tpd:

tpd = 1.75 ns

20 pF

+ 35 pF = 2.2 ns ,

which is very close to the value of 2.1 ns that was calculated using equation 54.
156

Example: Comparison of Series and Parallel Terminations
7·26: Test Setups for Comparison of Propagation Delays from
A to 8, and the Rise and Fall Times at 8

MECL10K
Gates

MC10109
43

A

TO=1.75ns
Zo = 50-ohm Coax

430

(a) Series Termination Test

MECL 10K
Gates

MC10109
A

Zo = 50-ohm Coax

B

50

-2.0 Vdc

(b) Parallel Termination Test

Since the propagation delay increase is twice as much for a series terminated
line as for a parallel terminated line, an equation similar to equation 11 can be
derived. The propagation delay of a series terminated line can be written as:

(59)

where tpd is the modified propagation delay of the line, tpd is the original
propagation delay of the line, CT is the total capacitance at the end of the line, and
Co is the intrinsic capacitance of the transmission line.
The effective characteristic impedance of a transmission line decreases with
capacitance at the end of the series terminated line, but only half as much as for a
parallel terminated line (cf equation 32). The characteristic impedance due to
157

Determining the Emitter Pulldown Resistor Value

loading of a series terminated transmission line can be written:

l 'o

A

(60)

T
1+- +
Co

This means that the series terminating resistor should be changed in the proportion
indicated by equation 60 when the capacitance at the end of the line exceeds the
value of capacitance given in Table 7-23. Equation 60 has been verified in the
laboratory as valid for heavy loading conditions. If the resistor, RS,is not altered
according to equation 60, increased propagation delays will result from underdamping.
Furthermore, if the amount of loading at the end of a series termina ted line is
more than that shown in Table 7-23, then the emitter pulldown resistor, R E, should
be lower than the value given in equation 61 for the maximum pulldown resistor
value (Chapter 3). The maximum value of RE as stated in Chapter 3 is:

RE(max)

(61 )

n

The reason that the pUlldown resistor should be lowered is that the reflection
returning to the source contains a short positive component associated with the
slower fall rate of the negative-going signal (due to capacitance loading). Thus,
the output transistor will turn off due to this momentary positive reflection if a
value given by equation 61 is used. The value of RE should be chosen so that the
output transistor of the driving gate is furnishing enough current to supply the
maximum reflection without switching off. The maximum reflection on a series
terminated line, due to capacitance, is +0.4 volts. Therefore, the value of RE should
be reduced enough so that the output transistor will be able to supply an additional
current of OA/l o . A modified emitter pulldown resistor equation can be written as:

3.6
RE(max)

3.6

0.4'

(62)

---+-RE max

lo

where RE (max) is defined in equation 61.
There is no limit (due to reflections) on the amount of gate loading that can be
placed at the end of a series terminated line, as long as equation 60 is used to
determine the proper series terminating resistor. All reflections will be terminated at
the driving end if the proper value of RE is chosen with equation 61 or 62. This is
true even though the amount of reflection is twice as much for a series terminated
line as it is for a parallel terminated one.
lC:Q

Series Damped Lines

The maximum loading for a parallel terminated transmission line is defined in
Figure 7-23. There is no limit to the amount of distributed loading that can be
placed on the line, as long as equation 32 is used to choose the terminating resistor.
In actual practice, there seems to be no limit to the amount of lumped loading that
is placed at the end of a parallel terminated line as long as the terminating resistor is
chosen this way. This is true as long as there are no other gates stubbed off the line.
For reference purposes, the equations for the reflection that is sent back to the
driving source, with lumped loading at the end of either a series terminated line or a
parallel terminated line, can be derived from equations 48 and 50 as follows:

percent of maximum reflection

=

eout (t) - E'l
E'

at t = T 1 . (63)

I

Therefore, the maximum reflection due to lumped loading at the end of a series
terminated line is:

percent of maximum reflection

(64)

and for lumped loading at the end of a parallel terminated line:

percent of maximum reflection

(65)

Analysis of Series Damping Terminations
A series damped line is very similar to a series terminated line with the exceptions being the line length and the value of the series damping resistor, RS. The
resistor is normally much smaller than the characteristic impedance of the line, ZOo
If RS, = 0, then an open line exists for which the maximum length is defined in
Figures 3-13, 3-14, or 3-15. If a small value resistor, RS, is placed in the line, a
longer line length is possible. An example of series damping is shown in Figure 7-27

7-27: Series Damping Termination

VA

Zo

VB
PIS

r-Qmax-l

Vc
m1
Number

of

Gates

RE
Where

RS< Zo

VEE

159

Output Voltage from a Series Damped Line

where the voltage change at point B is defined in Chapter 3 as,

(66)

Series damping is primarily used where the characteristic impedance varies - as
in backplane wiring when line lengths must be longer than those specified in Figures
3-13 through 3-15. A disadvantage of series damping is that distributed loading
cannot be used. A propagation delay slightly slower than for parallel termination also
results. Parallel fanout can be used as shown in Figure 3-18.
Figures 3-22, and 3-23, described in Chapter 3, show the minimum values for
RS for any line length, corresponding to specified limits of undershoot and
overshoot. These figures were generated by a computer program based on the
equations and calculations presented in the following pages. These calculations show
how the output voltage from series-damped transmission lines may be derived.
The Thevenin equivalent circuit for a series damped transmission line is shown
in Figure 7-28. Note that the circuit is similar to the equivalent circuit for a series
terminated line except for the amplitude of the voltage waveform.

7·28: Thevenin Equivalent of a Series Damped Transmission Line

r---------------l
I

I

Zo

E',

I
I

Slope = m = -

I

T1

I
I
I
I

2ZoE1

Where E'i

=-Ro+Rs+Zo

I
IL _______________
-=
I

CT = Total Load Capacitance

~

The equations for the output voltage from a series terminated line were derived
previously (equations 48 and 49). Since the amplitude has been modified by the
factor (2Zo/Ro + RS + Zo), a simple substitution will define the output voltage at
the load. The output voltage for a series damped line can be written as:

for t

:S
160

TI '

(67)

Propagation Delay; Exact Output Voltage Derivation

and:

for t

>

(68)

TI '

where E I is the voltage change at the base of the output emitter follower in the
driving gate.
If the input voltage is assumed to be a step function, the equation for the
output voltage from a series damped line becomes:

-R_2_Z-RO_E_I_Z-O(1 _
o + S +

eZ~~T ).

(69)

The additional propagation delay due to gate loading can be found by using
equation 69, letting eout(t) = 0.5 EI, and then solving for t. The increase in the
line propagation delay which results, is:

(70)

The exact reflected voltage will now be derived by a method similar to that
used previously in deriving equation 19. The reflection coefficient at the load is:

(71)

The input voltage at point B in Figure 7-27 is:
ei (t) = mtV(t) - met - T 1) V(t - T I) ,
where:

m

slope .
161

(72)

Reflection Amplitudes (La Place Notation)

Here Ro is the output impedance of the driving gate; RS is the series damping
resistor; Zo is the characteristic impedance of the transmission line; E 1 is the voltage
change at the base of the output emitter follower of the gate at point A in Figure
7-27; and Tl = 1.2 tr where tr is the 10 to 90% rise time of the voltage at point A.
Taking the LaPlace transform of equation 72 gives:

m
E· (s) = 1
s2

(73)

The first reflected voltage waveform at the load at time TD (point C in Figure
7-27) due to the input voltage is (in LaPlace notation):

(74)

E refl 1 (s) = Ei (s) P L (s)

The second reflected voltage waveform at the load occurs a time 2TD later and can
be written as:

(, __
I ) 2pS
E refl 2 (s)

E refl 1 (s) Ps PL (s) =

ZoC T

,2 (, + _I
ZoCT

r

m

(I - e- T1S )

, (75)

where:
Ps =

Ro + RS - Zo
Ro + RS + Zo

(76)

The third reflected voltage waveform at the load is:

-(s (77)
162

Output Voltage Amplitudes (La Place Notation)

So the nth reflected voltage waveform at the load is:

Erefl (n) (s) = Erefl I PSn - I

p n - I (s)
L

(78)

The output voltage at the end of the line can be derived by using equations 73
through 78. The output voltage, Eol, due to the input voltage waveform and the
first reflection is:

Eol (s) = Ei (s) + E refl

I (s)

= Ei (s)

(I

+ PL (S))

(79)

It should be noted that equations 79 and 46 are equal (though they were
derived differently), when R = Zoo At first glance it may appear that equation 79 is
twice the value of equation 46, but the apparent discrepancy is resolved by noting
that m has been defined differently for each equation.
The output voltage, E02, due to the first reflected voltage waveform returning
from the driving source will be:

(80)

Similarly, the output voltage, E03, due to the second reflected voltage
waveform returning from the driving source is:

163

nth Output Voltage and Total Output (La Place Notation)

or:

• U

(t -

4T D )

(81)

Finally, the nth output voltage waveform will be:

(_1)n -

u~ -

I

(82)

2(n - I) T D) ;

therefore, the general equation for the output voltage at the end of the line (point C
in Figure 7-27) can be formulated as a summation of the individual reflected voltage
components:

Eout (s) = Eo I (s) + E02 (s) + E03 (s) + ... + Eon (s) + ...

:E
n = I

'-(_I)n - I

l
(83)

The inverse LaPlace transforms for equations 79, 80, and 81 can be found in
standard tables. The inverses can be written to take into account the time delays the
following way.
164

Inversion of the LaPlace Voltage Equations

The inverse LaPlace transform of equation 79 is:

e 1 (l)
o

=~-l

• U(t)

(84)

Likewise, the inverse transform of equation 80 becomes:

• U(t - 2T D - T 1) .

165

(85)

Result: Output Voltages as Functions of Time

Finally, the inverse transform of equation 81 produces:

2mPS2Z0CT

[-5

2(t - 4To)2)

t - 4TD

+

+

ZoCT

(5

4(t - 4T D )
+
ZoC T

+

- (t - 4TO]
. e

ZoC T

. U(t - 4T D ) -

(Z oCT )2

(

5 +

4( t - 4T D - T I )
Z C
+
o T

(86)

A general form equation can be established for eo (n)(t) as an extension of the
preceeding equations. Such a general equation can then be used to obtain a general
relationship for eout(t) derived from equation 83.
However, for our purposes, the output voltage needs to be defined only for a
period of time long enough to determine the maximum amount of overshoot and
undershoot. The following can be written for the first three reflections (a sufficient
time interval):
3

eout (t)

;2:

2m p

n S

I

( - 2TO (n ZoC T

I)

ZoCT

- (2n -

I).

n= I

(
(2 (t

t - 2TD (n
- e

- 2T D (n
ZoC T

ZoC T

- I)) + (n -

-I))

- (t - 2TD (n -

+ (
(n - I )e

2)

C-

2TD (n ZoC T

166

I)j)

1)))-

ZoCT

• U (t - 2(n - I)T D)

Output Voltage for Three Reflections

3

-L:
n

- TI

\

- (2n -

1»)-

=

2T D (n - 1) - T))
ZoC T

for t

<

6T D '

(87)

where:
m

and tr is the 10 to 90% rise time of the voltage at point A in Figure 7-27. Figs. 3-13
through 3-15 are generated with a computer program using an extension of equation
87 in which the first 7 reflections were considered.
An extension of equation 87 was used in generating Tables 3-22 and 3-23 and
may also be used to determine maximum line length for specified undershoot and
overshoot, instead of using equations 12 and 13. This derivation follows.
For CT = 0 and t < 6T D' equation 87 reduces to:

eout(t)

=

2mtU(t) - 2m(t - T 1) U (t - T 1) + 2mPS'

(t - 2T D) U (t - 2T D) - 2mP S (t - 2T D - T 1) U (t - 2T D - T I) +
2mP S2 (t - 4T D ) U (t - 4T D ) - 2mPS2 (t - 4TD - T 1).

(88)
167

Maximum Overshoot

This equation can also be derived by starting from equation 5.
Using a lattice diagram, it is found that the maximum overshoot occurs at
t = T I. Substituting °t = T I into equation 88 gives:
(89)
for2TD

<

TI

<

4T D ;

and:

(90)

In both cases,

m

Tl
TD

and

ZoEl
(R o + Zo + Rs)Tl

,

1.2t r ,
tpd • Q ,

line delay in nanoseconds/inch,
line length in inches.

By definition,

(100 + O.S.)
EliDa

(91)

where E 1 is the voltage change at the output of the driving gate, and O.S. is the
percent overshoot based on logic swing level. Thus by substituting into equation 89,
the percent overshoot can be obtained:
168

Percent Overshoot; Line Length Considerations

%O.S.

t

= -1 +

2 Zo
Zo

+ RS + Ro
(92)
for 2tpd

<

T1

<

4tpd .

Equation 92 gives the overshoot (as a percentage of the logic swing) that occurs
for a particular length of line, assuming zero capacitance at the end of the line. If the
two way propagation delay of the line is equal to or greater than T 1, then this
particular length of line is:
1.2 tr

Q>--

2tpd

(93)

If equation 93 is satisfied, then the overshoot reaches a maximum value which can
be solved for by using equation 90:

%o.s. max

2 Zo
100 ( Zo + RS + Ro

(94)

If the length of line is less than that specified in equation 93, the line length
can be found from equation 92, given the permissible overshoot for a given design:

Q

2 Zo
• (1 + P ) _ (100 + O.S.) ]
[ Ro + Zo + RS
S
100

(95)

In this relation, it is necessary that:

1.2 tr

Q<-2tpd
169

Maximum Line Lengths

The maximum permissible line length with capacitance loading can be
approximated in a manner similar to that used to establish a maximum open line
length in a previous section:

(96)

Solving for Qmax:

(97)

2

where CT is the total lumped capacitance in pF, Co is the intrinsic line capacitance
in pF lin, and Q is the length of line in inches defined in equation 95.
Using a lattice diagram, it has been found that the maximum undershoot occurs
when t = 2TD + T 1. Substituting this information into equation 88 produces the
relation:

for:

(99)

By definition,

E .

mm

(100 - U.S.)

= E

1

100

(100)

where U.S. is the percent undershoot. Equation 98 can be used to form a useful
170

Percent Undershoot

relationship, which expresses the undershoot in tenns of circuit parameters:

%u.S.

(

I -

2Zo
(I +
Zo + RS + Ro

P

S

+

Ps2)

+

(10 I)

for:

and:

Thus equation 101 gives the undershoot as a percentage of the logic swing - for a
particular length of line.
If equation 93 is satisfied, then the undershoot reaches a maximum value which
can be found from equation 99 to be:

(102)

On the other hand, if the length of line is less than specified in equation 93, the
line length can be found from equation 101 once the permissible undershoot has
been specified. Solving:
Q

~
2 Zo R (I + P + P 2) _ (I 00 - U.S.) )
- \ Zo + RS + 0
S
S
100

•

(103)

171

Line Lengths for Specified Undershoot or Overshoot

for:

Equations 95 and 97 can be used to find the maximum open line length
(instead of equations 12 and 13) when the maximum percentage overshoot has be~n
specified. Equations. 97 and 103 can be used when the maximum undershoot is
specified. Of course, a more exact value for the maximum permissible line length is
found when a computer program is used to generate the values using an extension of
equation 87. This was done to generate Figures 3-13, 3-14, and 3-15. The first seven
reflections (n = 7) were used to accurately define the open line length required
to limit overshoot ana undershoot for a wide range of load capacitances. Equations
94 and 102 were used to generate the values given in Figures 3-22 and 3-23 using a
computer program.

REFERENCES
1. Kaupp, H. R., "Characteristics of Microstrip Transmission Lines", IEEE
Transactions on Electronic Computers, Vol. EC-16, No.2, April 1967,
pp. 185-193.

2. Cohn, S. B., "Characteristic Impedance of the Shielded Strip Transmission
Line", Transactions IRE, Vol. MTT-2, July 1954, pp. 52-57.
3. Springfield, W. K., "Designing Transmission Lines into Multilayer Circuit
Boards", Electronics, November 1, 1965, pp. 90-96.
4. Skilling, H. H., "Electric Transmission Lines", New York, McGraw-Hill, 1951.
5. DeFalco, J. A., "Reflections and Crosstalk in Logic Circuit Interconnections",
IEEE Spectrum, July 1970, pp. 44-50.
6. Millman, J., and Taub, H., "Pulse, Digital and Switching Waveforms", New
York, McGraw-Hill, 1965, pp. 83-106.
7. "Time Domain Reflectometry", Hewlett-Packard Application Note 62, 1964.
8. Botos, Bob, "Nanosecond Pulse Handling Techniques in IIC Interconnections",
Motorola Application Note AN-270.
9. Schwarzmann, A., "Microstrip Plus Equations Adds Up to Fast Designs",
Electronics, October 2, 1967, pp. 109-112.
10. Catt, I., "Crosstalk (Noise) in Digital Systems", IEEE Transactions on
Electronic Computers, Vol. EC-16, No.6, December 1967, pp. 743-763.
11. Feller, A., H. R. Kaupp, J. J. Digiacoma, "Crosstalk and Reflections in
High-Speed Digital Systems", Proceedings, Fall Joint Computer Conference,
1965, pp. 511-525.
12. Cohn, S. B., "Shielded Coupled-Strip Transmission Line", IRE TransactionsMicrowave Theory and Techniques, October 1955, pp. 29-38.
13. Gabbard, O. G., "High-Speed Digital Logic for Satellite Communications",
Electro-Technology, April 1969, pp. 59-65.
14. Henschen, I. E. and E. M. Reyner II, "Adapting PC Connectors for Impedance
Matching", Proceedings, NEPCON, 1970.
172

MECL Applications
INTERCONNECTION TECHNIQUES
FOR MOTOROLA'S MECL 10K/10KH SERIES
EMITTER COUPLED LOGIC
considerations to be made for system interconnections are
also discussed, such as nOise margins, clock driving, wire
wrappmg, and party line techniques.

INTRODUCTION
As the digital integrated circuit market has become
more mature, the need for very high speed logic elements
has grown. Future machine designs demand a logic family
with high clock rate capability, short propagation delays,
and a minimum of layout constraints. From this need,
the MECL lOKllOKH families of emitter-coupled lOgIc have
evolved - designed to be the most usable very high speed logic
families available.
The 2.0 nanosecond gate propagation delay of MECL 10K
and 1.0 ns gate propagation delay of MECLIOKH gives the
families a speed range between the older MECL II and MECL
III families. Additional characteristics, such as low power
dissipation (25mW per gate function), and slow nse and faIl
times have eased the difficulties encountered in trying to balance
system speed versus ease of design.
A MECL 10K system has the capability for clock rates In
excess of 100 MHz, and MECL lOKH has clock rates in excess
of 200 MHz. To permit such high speed operation, gate
propagation delays must necessarily be short. However, to
simplify wiring techniques and to minimize the use of transmission lines, rise and faIl times have been kept to slower values.
The I nanosecond rise time of MECL III demands a
transmission line environment. On the other hand, MECL
lOKI lOKH have been designed to approach the higher speed
rates of MECL 1Il, but with simpler wiring requirements.
The operatIOnal behavIOr of a MECL III gate With a flSe
time of 1 nanosecond (100/0'90%) is shown in figure 1 for
comparison. Figure I a shows the difference in nse times
when either gate is driving only a pulldown resistor. Figure
lb shows the same outputs drivmg an 8 inch signal line
to a gate input. The MECL III gate shows severe ringing.
This necessitates the use of a transmission line. The effect
of the slower rise time of the MECL 10K gate is obvious in that
ringing is not as severe. Herein, lies an advantage for the system
designer using MECL 10K - that is, he may realize a very high
speed system using only a minimum of transmissIOn lines
When dnvmg long lines or large fanouts at maximum
frequency, transmission lines are needed. MECL lOK/IOKH
has the capability to drive such lines. Also, the famtlies are
specified to be completely compatible With MECL III in the
16-pln dual-in-line packages. As a result, MECL lOK/lOKH
can be used to obrttin maximum versatihty with low power and
ease of layout design.
The following discussion IS intended to give the system
designer insight into these problem areas: The use of nontransmission line interconnections; the characteristics of
transmissIOn lines which affect MECL interconnecttons;
and the techntques used for transmission lines. Other

SIGNAL LINE CONSIDERATIONS
The purpose of an interconnection line in any digital
system is to transmit information from one point of the
system to another. When information on a signal line
changes, a finite amount of time is necessary for the information to travel from the sending end to the receiving end
of the line. As the cirCUit speed becomes faster and clock
rates increase, the dynamic behavior of the interconnection
line becomes increasingly important. The rise and fall
times of the logic elements, loading effects, delay times of
the signal paths, and the various other transient characterIStiCS, all affect reltable operation of the system. The effects
of these factors and the advantages of the dynamic charactenstics ofMECL lOKI IOKH are perhaps best shown by briefly
investigating the transmission line qualities of a signal path.
In figure 2a is shown a simple interconnection circuit.
A MECL lOKI lOKB gate IS shown driVing a line length Q, to
another gate with a pulldown resistor, RL. If the loading
effect of the receivmg gate is disregarded for the moment
(input impedance is very large with respect to RL), the
same line could be model~d as shown in figure 2b.
The dnving gate is modeled as a voltage source with
output impedance, Ro. The signal line will exhibit an
impedance to a transient signal which is called its characterIstic Impedance, Zoo lfthe line is not a regular transmission
line, Zo will vary somewhat. However, for this example
let us assume Zo is constant.
When the output of the drivmg gate changes state, the
voltage at pomt A is a function of the internal voltage
swing, VI NT, output Impedance, and line impedance:

V A(t) =

VINT(t)(~---).
Ro+Zo

For MECL lOKI lOKH, Ro is small with respect to the line
impedance, so the output swing is nearly the same as the
input transition - typically 800 mY. The signal will prop-

173

MECL 10K

MECLIII
I"

-

\

I
I.

V

~-

-

I

I
~ II

[---

f-=;.... I--"
~-'--

V

J

-

--

\

I

~~

/
'\.

-

/

--

HOrizontal Scale 2 ns/dlv.
Vertical Scale 200 mV/dlv.

la) Gate Driving 510-ohm Pulldown Resistor

MECL III

1\

1\
!
I

r\

r-'--- --,--

1\ / \

\1v V'

'IV

.;0-

V

-

--

f---

h",

-

---

-

-,'-

f--

f++++- r--t-

++-f+- H-++-

I---

-

I--- r--

--

~~

~--

~-l- ~ !~- I
\ r.
~
V
~iV

-

H-+

-~

-t~-

~

f+++>

~H-!-

~~J__

-tt++ tt-t+

---

--

Comparison of MECL III and MECL 10K Waveforms

FIGURE 2 -

MECL 10K Interconnection Circuit

174

"'+tt

~--

I+++-

-

--

----

-

Ib) Gate Dnving 510-ohm Pulldown Resistor and 8 Inch Line with Gate Load

(b)

--

-

--

--~

HOrizontal Scale 5 ns/dlv
Vertical Scale 200 mV/dlv

la)

f-t+++

--

~--

i

-

------

FIGURE 1 -

r-

MECL 10K
,----

-

-

- ---

is reduced. Therefore, the slow rise tIme of MECL lOKI IOKH
permits longer line lengths to be used before trouble with
ringing is encountered.
This second signal line example IS called an open line
or an unterminated line. To lImit undershoot to about 12
percent of the logic swing, the maximum open line length
permitted would be:

agate down the hne and be seen at point B time TO later.
The signal, when reaching the end of the line (point B),
may be reflected and returned toward the sendmg end of
the line. The reflected voltage IS:

where PL is the reflection coefficient,

tr
Lmax=-- ,
2tpd
where:

In the special case where RL = Zo, then PL = 0 and the
reflected voltage is zero. In thIs situation the load resistor
exactly matches the characteristic Impedance of the line,
so no reflection occurs.
When reflection does occur, It returns to point A at
time 2 TO, where TO is the one-way line propagation delay.
The sending end will again reflect this voltage with a reflection coefficient, PS, given by:

(ns/in).
The above expression may also be used to show the
effect of loading on an interconnectIon. tpd IS dependent
on the rate of SIgnal propagation on the line; the rate is
controlled by the type of line and the loading on the lme.
MECL inputs are high impedance and capacitive in net
reactance (3 to 5 pF per input). Increased loading slows
the rate of propagation of the line and decreases allowable
open line length. That is, as fan-out increases, the maximum open line length decreases for acceptable undershoot.
To understand how ringing and undershoot affect system operation, it IS helpful to define guaranteed noise mar-

Ro- Zo

PS=--

Ro+Zo
The reflected signal will continue to bounce back and
forth between the ends of the signal line, gradually dimmished in amplitude by reflection coeffiCIents and the resistance in the line.
Now consider a second lme in which the load resistor
has been moved to the sending end of the lme (figure 3a).
This model is altered from the first only 10 that the load
resistor is seen at the driver output. When the output of
the driving gate changes state, the output swing, V A, will
be typically 800 mY.
The SIgnal reaching point B will be reflected (as discussed). The coefficient, PL, becomes worst case (::::: 1)
because the input impedance of the receiving gate is high.
In such a case the reflection will be large. As the reflection
returns to point A at time 2 TO, the reflection coefficient,
PS, comes into play. Its value will be very close to the
previous case:
RoRL

Ps =

Ro+ RL
RoRL
Ro+ RL

-Zo

Ro - Zo

::::: - - -

+Zo

tr = Rise time of dnvmg gate (ns) (20% - 80%)
tpd = PropagatIOn delay per UnIt lme length

(a)

(b)

,

Ro + Zo

(e)

since Ro is small compared to RL.
The reflections, as before, continue to bounce back and
forth on the line getting successively smaller in amplitude.
The result is that ringing appears on the signal line (figure
3c).
Rise time effects may be understood by considering the
delay time of the line. If the line length Q is sufficIently
short, the first reflections are seen at the sending end of
the line while the driver is still changing state. The reflections are hidden by the rising edge of the pulse, and ringing

Overshoot {
_ - - - - . . . - - - - - 1 Level
Undershoot I - - I - - \ -

50%-r----------1-£)

Level

U ndershoot

I--\-~-JL-~=---

FIGURE 3 - MECL 10K/10KH Interconnection with Load
Resistor at Sending End of Une

175

gInS. Noise margin is defIned as the difference between a
worst case input logic level (VOHAmIn or VOLAmax) and
the worst case threshold (VIHAmin or VlLAmax) for the
correspondIng logic level. Guaranteed noise margins (N.M.)
for MECL 10K at 25°C are.

MECL 10K Devices

=VOHAmin - VIHAmin
= -0.980 - (-1 105) = 125 mY;
Logic f/J N.M. = VlLAmax - VOLAmax
=-1.475 - (-1.630) = ISS mY.

Logic I N.M.

However, US1l1g typical logic levels of - 0.900 volts and
- 1.700 volts, the nominal voltage margins are greater than
200 mY for both logic levels. Noise margin for MECL IOKH is
ISO mY for both logic I and 0 N.M.
For system design, worst case conditions should be considered. If so, a 125 mY noise margin becomes the design limit
for MECL 10K. This voltage margin protects against signal
undershoot, power supply variations, and system noise. Good
circuit interconnections should limit maximum undershoot to
less than 100 to 110 mY to provide a design safety margin.
Other factors - such as line Impedance and placement
of loads on the line - also affect ringing of signals. A long
and elaborate discussion would be necessary to describe
all of the varying effects, and the description here is only
Intended to give a brief idea of the many factors involved.
When line lengths and fanout go beyond limits (which Will
be defIned), techniques such as twisted pair lines and terminated lines may be used.

Back Side

PRINTED CIRCUIT BOARD INTERCONNECTS
Layout rules needed for designing with MECL lOKI IOKH
depend mainly on the design goals of the system user. MECL
IOK/IOKH may be used in layouts ranging from single layer
printed circuit (PC) board with wired interconnects, to the most
elaborate multilayer board with a complete transmission line
environment. Optimization of system layout will include
considerations ofthe system size, desired performance, and cost.
Use of a ground plane is a suggested procedure whenever possible. A ground plane is beneficial for maintaining
a noise free voltage plane for the V CC supply, and for
maintaining constant characteristic Impedance whenever
transmission lInes become necessary. A ground plane may
be established by using single sided board with WIred interconnects, or by using double or multilayer PC board.

Front Side
FIGURE 4 - Printed Circuit Board for MECL 10K
System Without Ground Plane

line should be in close proximity to a Vee pin for easy
bypassing.
(3) Each device should be bypassed between the Vec
and the VEE pins with a low inductance 0.0 I I1F capacitor.
(4) Logic interconnect1l1g lines should be kept to minimum length. A maximum line length of 6 inches is suggested; ringIng Will begin to get too severe with longer line
lengths. For lIne lengths greater than 6 inches, signal lines
with series damping resistors are necessary (Similar to those
shown in figure 13).

WITHOUT GROUND PLANE
In small systems where the number of interconnects and
the package density are high, it is difficult to reserve a large
ground plane area without the use of multilayer board, a
costly approach. However, MECL lOKI IOKH may still be used
with good system performance if certain guidelines are followed:

(5) For high fanout (8 or greater) and high speed clock
distribution, twisted pair lines or coaxial cable should be
used. Both of these techmques are descnbed in detail later.

(I)

Vce should be bussed to the VCC pins of each package. Bus lines should be as Wide as possible with a width
of 0.1 inch mimmum per row of packages. If an edge
connector is used, Vec should be pInned out to several
connector pins.

Figure 4 shows a double-sided PC board in which the above
rules are illustrated. Several MECL 10K devices are used with
MITL in a high speed counter, in which the MECL and MITL
are operated by a common voltage supply. Notice that YEE and
YCC are both bussed to the package and that bus lines are as

(2) VEE should also be bussed, if possible, to pin 8 of
each package (PIn 12 of the 24 pin package). When VEE
is brought onto the board via an edge connector, the VEE

176

FIGURE 5 - MECL 10,000 PC Board With Ground Plane

177

wide as conveniently possible. Two 0.1 pF capacitors are used
for low frequency bypassing on the board. Each MECL 10K
device is bypassed with a 0.01 I1F capacitor, and additional
bypassing is scattered through the MTTL circuitry. Note that
signal lines are short and no transmission lines are used.

Wire over ground - The cross section of a wire over
a ground is shown in figure 6a. The characteristic impedance of the wire is:

(1)

60
Zo= jeT In

WITH GROUND PLANE
A ground plane allows best performance for a MECL
IOK/IOKH system. The ground plane serves two purposes.
First, it provides a constant characteristic impedance (Zo) to
signal interconnections; secondly, it provides a low inductance
path for ground currents on the VCC supply. As with systems
which have no ground plane, certain design guidelines are
recommended as follows:

(4h)
d'

where er is the effective dielectric constant surrounding
the wire. The wire over ground plane is useful for breadboard layouts (as with single-sided board) and for backplane wiring. The characteristic impedance of a wire over
ground plane will be about 120 ohms with variance depending on the wire size, type of insulation, and distance from
the ground plane ..
(2) Mlcrostrip lines --- A microstrip line (figure 6b) is a
strip conductor separated from a ground plane by a dlclcctric medium. Two-sided and most multilayer boards use
this type of transmission line. If the thickness, width, and
height of the line above the ground plane are controlled,
the line will exhibit a characteristic impedance of:

The ground plane (V CC) need not cover 100% of
the board surface. Approximately 30 to 40% of the ground
area may be removed for signal interconnections, as illustrated in figure 5. When using edge connectors, the ground
plane should be pinned out to about every seventh connector pm.
(2) The VEE supply should be bussed if possible, to pin
8 of each package. Bus line width at any point should be
a minimum of 0.1 inch. Where possible, the VEE supply
should be extended to a plane under the signal lines etched
on the ground plane Side of a two-sided CHCUlt board. If
VEE is a plane under these lines, they will exhibit a constant characteristic impedance. This technique is also
shown in figure 5.
(3) Bypassing need not be as extensive as on a board
withou t a ground plane. Provide a low inductance 0.0 I
I1F capacitor every two to six packages, depending upon
how extensive the ground plane is. As a rule if the ground
plane covers less than 50% of the board area, then bypass
every two packages. On two-sided systems or multilayer
systems where 100% ground plane is present, only one
capacitor for every four to six packages is needed.
(4) In practice, the majority of board interconnects are
shorter than six inches, with fan outs four or less. As discussed, the rise and fall times of MECL 10K allow these lines to
be treated as unterminated transmission lines requiring only a
pull-down resistor. Normally, a 51O-ohm resistor to VEE is
used. (Detailed limits for interconnections are provided as a
function offine impedance and fanout in the following section).
M ECL 10K Hallows 3 inches to be treated as an unterminated
line.
(5) For high fanout and high speed clock distribution,
terminated transmission hnes or twisted pair lines should
be used. These techniques are discussed in the following
sections.
(1)

87

Zo= - - - In

(

.fo0T4T

~v zZ

5.98h

--0.8 w + t

)

,

Z 7 7 Z Z Z 7 Z 7 7 J Ground

la) Wire Over Ground

Dlelectrtc

f

h

t>-:r-~,..-,.--,~...-r;~-i ~

Ground~~~~/~~/~~/~7~7~

Ib) Mierostrip

TRANSMISSION LINE GEOMETRIES
With a ground plane present, three types of transmission
line geometries are feasible: wire over ground; microstrip
line; and strip line. The following sections summarize the
characteristics of each type of line.

Ground Plane
StriP Line

7/

//~/2

Ground Plane

Ie) Strip Line
FIGURE 6 - Transmission Line Geometries

178

(3) Strip Line - A strip Ime (figure 6c) is a copper ribbon
centered in a dielectnc medium between two conducting
planes. ThIS type of line is used in mutlilayer boards and
is not seen in most systems. MultIlayer boards are justified
when operating MECL IOK/lOKH at top cirCUIt speed, and
when high density packaging is a system requirement. Since
most designers need not concern themselves with strip lines,
little is presented here about them.

Here er is the dielectric constant of the board. For standard
G-IO fiberglass epoxy boards the dielectric cons tan t is
about 5.0.
The signal line is obtained by etching unwanted copper
from the board using photo resist techniques. A characteristic impedance can easily be controlled to within 10 percent.
As mentioned above, board thickness and dielectric
constant affect line impedance. Figure 7 gives a table of
values for characteristic impedance versus line width for
0.031" and 0.062" G-IO board with one ounce copper
(widths for two ounce copper are nominally I to 2 mils
narrower).
The propagation delay of mIcros trip line may be calculated by:

td

= 1.017 .)0.475 er + 0.67

UNTERMINATED LINE LIMITS
As prevIOusly mentioned, a MECL signal line may be
considered as an un termina ted transmission line. Rise time,
characteristic impedance of the line, and loading affect
the maximum interconnection length for un terminated
lines. FIgure 8 shows a tabulation of suggested maximum
open line lengths for vanous fanouts and line impedances.
The tabulated values were calculated for limitmg overshoot to 35% of the logic swing, or undershoot to 12%
(whichever was the hmitmg factor under specified conditions). Severe overshoot can slow down clock rates, and
severe undershoot can result in reduced noise immunity.
The transmission line model of figure 3 was used in calculations.

ns/ft.

Note that the propagation delay of the line depends only
on the dielectric constant and is not a function of line
width or spacing. For G-IO fiberglass epoxy boards (er =
5.0) the propagation delay of the microstrip hne is calculated to be 1.77 ns/ft.

As an example of how the table of line limits may be
used, consider a system layout using 0.062" board (G-I 0
fiberglass epoxy). Assume that SIgnal interconnection
widths may be from 25 to 40 mIls wide. If a ground plane
is used on one side of the system PC board, all system
interconnects would show a corresponding characteristic
Impedance. The wide hne (40 mils) IS preferable since
Zo would be 82 ohms which is lower than that for a 25
mil line (Zo :::::: 97 ohms) and the lower impedance allows
a longer maximum length line. The lower impedance hne
with a fanout of 4 would then have a suggested maximum
length of about 4.2 inches. On normal system-sized PC
boards (5"xT), the majority of signal line interconnections
wIll be less than 4 inches in length if the system layou t is
well planned.

FIGURE 7 - Microstrip Characteristic Impedance versus Line
Width for One Ounce G·10 Fiberglass Epoxy Board
LINE WIDTH (MILS)
(D,mens,on w of F,gure 6bl

20
(OHMS)

0.062" BOARD

0.03'" BOARD

50
55
60
65
70
75
80
85
90
95
100

103
89
77
66
57
49
42
36
31
27
23

47
41
35
30
26
22
19
16
14
11
10

FIGURE 8 - Maximum Unterminated Une Length for MECL 10K to Maintain Less Than 12% Undershoot
Zo
(OHMS)

MICROSTRIP
(PropagatIon
Delay
14B ns/in I

o

I

BACKPLANE {
(PropagatIon
Delay
o 140 ns/on I

FANOUT = 1
(29 pF)

FANOUT' ~ 2
(58 pF)

2

2

MAX (IN)

MAX (IN)

"

FANOUT = 4
(116 pF)

2 MAX

(IN)

FANOUT = 8
(232pF)

Q MAX (IN)

5.1

67
5.0
46
4.2
39
36

57
40
36
33
30
2.6

54
4.3
36

38
28
21

28
19
13

50
68
75
82
90
100

83
7.0
6.9
66
6.5
63

75
62
59
5.7
54

100
140
180

66
5.9
5.2

179

An interconnection with the pulldown resistor at the
sending end of the line is the worst case situation for an
unterminated line. Ifunterminated interconnection lengths
are extended beyond the suggested limits, overshoot and

undershoot are increased. The lengths given are calculated
so that undershoot never exceeds the guaranteed noise
margins, although typically noise margins are much greater
than specified.

-r--

I~

(a) 510-ohm Resistor at Sending End

- f---- 1----

J'1

1

L"I.

~ 1

,I

\~ J..--o. t-- ~ I-f--

~

1
r---

ff

Scale' Horozontal

(b) 510-ohm Resistor at Receiving End

=5

ns/dlV., Vertical

= 200

~-~L

J

11\

f---

---

I \ I f'" ~
I

--- f - -

~

.1

mV/dlv.

++++

I

1-++++

I
Zo = 50 ohms

r--

510

f
'-----~

Scale

Horozontal

=5

__ L-L-_

ns/dlv .• Vertical

--

= 200

--

mV /dlv.

---

--

(c) 330-ohm Resistor at Receiving End

----

J\

j \ Ii'I

~

+-+-++++

1

Zo

= 50 ohms

-

330

~

---f---- f---- 1---

-Scale' Horizontal

=5

FIGURE 9 - Gate Driving a-Inch 50-ohm Line with Fanout of 4

180

ns/dlv .• Vertical

----

= 200

--

mV /dlv.

Overshoot and undershoot may also be reduced by locating the pull down resistor at the receiving end of the
line. If the pull down resistor IS moved to the receiving end,
the reflection coefficient (PL) is reduced. This reduces
ringing.
Figure 9 shows the signal at the receivmg end of an
8-mch 50-ohm line With a fanout of 4. In figure 9a, a
51 a-ohm pull down is at the sendmg end of the lme. Figure
9b has a 51 a-ohm pull down at the receiving end, while
figure 9c has a 330-ohm pull down at the receivmg end.
The overshoot and undershoot are successively reduced in
the la tter two cases.
For worst case, the reflection coefficient is approxImately equal to one (PL "'" I). For the best case shown,
using a 330-ohm pul\down, PL = (330 - 50)/330 + 50) =
0.74, which represents an improvement of about 25%. In
comparing the wavetorms, notice that overshoot IS reduced
by roughly the same percentage (9c versus 9a).
The tabulated values of figure 8 are not necessarily
absolute limits for unterminated lines. Longer unterminated lmes may be used if the pull down resistor is moved
to the receiving end of the line, or If increased overshoot
and undershoot are acceptable.

RL = Zo

lal Parallel Terminated Line With Lumped Fanout

VTT

Ib) Parallel Terminated Line with Distributed Fanout

TRANSMISSION LINE TERM INA nON TECHNIQUES
Proper transmission line termination prevents reflections
on the line, so ringing does not occur. As a result, interconnection lengths are only limited by attenuation, bandwidth, etc. MECL transmission line interconnectIOns utilIze
several techniques.
(l) Parallel TerminatIOn - A transmission line will have
a reflection coefficient, (PL), of zero when driving a load
impedance equal to its characteristic impedance. MECL
IOK/ 10KH can source current for drivmg a 50-ohm characteristic impedance hne with the lme terminated by 50 ohms to -2
volts. The termmation voltage (Vrr =-2 volts) is necessary
since 50 ohms loaded to VEE would use excessive current.
Figure 10 Illustrates parallel termmatlOn.
Gate inputs may be dIstributed along the transmission
line (I Ob), and do not have to be lumped at the end of the
line (lOa). The gate inputs appear as high impedance stubs
to the transmission line and should be as short as possible.
While mputs may appear anywhere along the line, the
terminating resistor should be at the end of the lme. As
fanout with this configuration increases, the edge of the
waveform slows down, since the signal drives an increasing
amount of capacitance. The waveform is undlstorted along
the full length of the line.
For large systems where total power is a consideration,
all lInes should be parallel terminated to a -2 volt suppl~/.
This is the most power-efficient manner for terminatmg
MECL circuits. The drawback is of course, the requuement for an additional power supply.
An alternate approach is to use two resistors - as shown
In figure 11. The Thevenin equivalent of the resistor network is a resistor equal to the charactenshc impedance of
the line, termmated to -2 Vdc. RI and R2 may be ca\cu-

I--

/.V

II
/

V
HOrizontal Scale

=2

ns/dlv.

Vertical Scale

= 200

mV/dlv.

Ie) Waveform at ReceiVing End of Line
FIGURE 10 - Parallel Termination

_~R'VCC

~L)~
_____
Z_o____~.

R2

VEE

THEVENIN EQUIVALENT RESISTORS
FOR TERMINATION
Rl
R2
Zo
(OHMS)
(OHMS)
(OHMS)
50
70
75
80
90
100
120
150

81
113
121
130
146
162
194
243

130
182
195
208
234
260
312
390

FIGURE 11 - Parallel Termination Using a Thevenin
Equivalent Resistor Network

181

lated as follows:

be expressed as:

R2

RS + Ro + Zo

= 2.6 Zo;

R2
RI =--.

where Ro is the output impedance of the gate.
Since RS + Ro is made equal to Zo, the vol tage change
at B IS 1/2 the voltage, 6VINT. It takes the propagation
delay time of the transmissIOn line, TO, for the waveform
to reach point C, where the voltage doubles due to the
unity reflection coefficient at the end of the line. The
reflected voltage, which is equal to the sendIng voltage,
arrives back at point B at time 2 TD. No more reflections
occur if RS + Ro is equal to Zoo Similar waveforms occur
when the driVIng gate switches to the high state.
An advantage of USIng series terminated lines IS that
only one power supply is reqUired. The Thevenin equivalent parallel terminatIOn technique also uses only one supply, but requires more overall power. A disadvantage of
series termination is that distributed loading along the line
cannot be used because of the half-voltage waveform traveling down this line (see figure 12, waveform B). A number
of lumped loads may be placed at the end of the terminated
line as far as reflectIOn at the receiving end is concerned,
since a full initial signal transition is observed at this point
and all subsequent reflections wi11 be absorbed at the source.
The disadvantage of usmg only lumped loadIng at the
end of a series terminated line can be elimInated at the
expense of more lines (figure 13). As shown, there are n
transmiSSIOn lines for parallel fanout. The value of RS
should be the same as discussed prevIOusly for the emitter
pull down resistor, In which case n was equal to one.
The value of RE, wi11 be determined by the number of
hnes In the following way. RE must be small enough to
supply each transmission line With the proper voltage level.
If RE IS too large, the output transistor wi11 turn off when
sWitching from the high to the low voltage state. The
maximum· value of RE is given by:

1.6

(2) Series damping and senes termInation -- A senes
terminated line ehmmates reflections at the sending end of
the line. Senes termmatIOn is accomplished by insertIng
a resistor in series with the output of the gate as shown in
figure 12. The resistor value plus the circuit output Impedance is made equal to the impedance of the transmission line.

A

RS

A

B

c

f--t -

f--

VOlt~ge All

>-lvo,,1"

10 Zo - RS

RE(max)

c/

=-- N--

•

A

RS

Zo

RS

Zo

HOYlzontal Scale = 5 ns/dlv
VertIcal Scale = 500 mV Id,v.

FIGURE 12 - Series Termination and Waveforms
RE

The dc output Impedance IS 7 ohms for a MECL lOKI IOKH
gate. Therefore, the value of RS should be equal to Zo minus 7
ohms.
At time t = 0, the internal voltage switches to the lowstate which represents a change of 0.8 to 0.9 volts (6VINT
= - 0.8 to - 0.9 volts). The voltage change at point B can

RS

VEE
RS
n

= number of

lInes

FIGURE 13 - Parallel Fanout with Series Termination

182

Figure 14a shows the gate output fall time (voltage A)
and the fall ttme at the end of the line (voltage C) when
N == 1, Zo == 50 ohms, RE == 1 k ohms, RS == 43 ohms, and
fanout == 3. The "steps" in the fall time waveform are due
to the output devIce turmng off because RE is too large.
Figure 14b shows the fall time when RE == 290 ohms
(RE < RE(max))
The fanout at the end of a serIes termInated line IS
limited by the value of the series resistor, RS. In the hIgh
state a voltage drop occurs across the serIes resIstor:

MIN RS
(OHMS)

20
(OHMS)

FIGURE 1S - Minumum Values of RS
for Any Length Line. for Less Than 3S%
Overshoot or 12% Undershoot for
MECL 10K/10KH

50

9

68

18

75

21

82

25

90

29

100

34

120

43

140

53

160

63

Vs::: (fanout) x (input current) x RS .
rather than to completely terminate nnging. The resistor
is smaller than the characteristic impedance of the lIne and
It may be Llsed to mcrease line length for the worst case
open lme (that IS, Rs == 0) as shown in fIgure 8.
Series dampmg may also be used for greatly extended
line lengths while remaining wIthin calculated limIts of
overshoot and undershoot. Figure 15 gives mimmum values
of RS needed for various Ime impedances to lImit overshoot to 35% of signal swing, or undershoot to 12%. Usmg
these values of mimmum RS, very long lines may be used.

The input current to a MECL 10K gate IS typically about
160 J.1A. If the fanout were 4 and RS were 43 ohms for a
50 ohm lIne, Vs would equal about 28 mY. NOIse margin
would typically be cut by that amount. As fanout or the
value of RS increases, Vs increases and results in lower
noise margins.
SerIes damping may also be used to reduce overshoot
and ringing. Series damping IS similar to series termination
In that a small senes resistor IS used to reduce ringIng

65

E

60
55

./

50

t--- t---

t--- t---

Voltage A "'-..

VOr

ge

..J

~

\

45
40

~

35

W

30

cr

25

...

20

~

\..,

,

~

~

.,./

.,/

.-

-

tr-

f---

'/

-/

tf-

r--

15

o

6

4

Horozontal Scale ~ 5 ns/dlv.
Vertical Scale = 500 mV/dlv.

8

10

12

14

16

18

20

FANOUT (NUMBER OF GATE INPUTS)

(a) SO-ohm to - 2.0 V

(al RE Too Large

10

E
rJl
W

:2

/V

8.0
tf/

t=

..J
..J
<{

f - - Voltage A \ ,

V

60

V

u.
0
Z

/V

4.0

<{

---

W

'-t"j"CI \

~

~

cr

2.0

...

0
0

Horozontal Scale = 5 ns/dlv.
Vertical Scale = 500 mV/dlv

V

2

....V

4

tr

f.-~~

6

8

10

r--

12

14

16

FANOUT (NUMBER OF GATE INPUTS)

(bl RE Less Than RE(maxl

(bl S10-ohm to VEE

FIGURE 14 - Series Termination Fall Times

FIGURE 16 - Rise and Fall Time (10 to 90%1 versus Fanout

183

(a) Time Parameters versus Emittf'r·Dots
MC10102 (50 ohms to -2 volts)

(b) Time Parameters versus Emitter·Dots for
MC10102 (510 ohms to -5.2 volts)

50

5.0
tpdr_+

]

-

30

~

-I---

t--

r--

20

40

I

V-

~I--"

w

i=

..4

l--- 1---1-

40

1

tpdf+--

~

]

-+L---f=:===

30

p

w
~

tf_

20

i=

~~

tl~ I-V
~~

~
tpdf+I..-::::::::: I-~

-

V

.- ~ V
V /'
1/
tf

I--- ~

tr

10

10

o

o

o
4

6

10

12

14

16

o

4

NUMBER OF EMITTER DOTS

Test

Test

POint

POint

A

I

PULSE
GENERATOR

Vee

8

10

12

14

16

NUMBER OF EMITTER DOTS

L
I
I~-{C=========~t---~

B

I

~~T--~~~Gnd
I

~,1

= 20 V

VEE=32V

50

orVEE

RL

(c) Emi,ter·Dot Test Circuit for MC10102

FIGURE 17

OTHER CONSIDERA TIONS

mated Imes driven from a single gate output (figure 13),
with lower fanout per line, will show shorter delay times
than a single parallel terminated line with an equivalent
total fanout. Multiple series terminated or damped lInes
also show greater flexibility in line routing than a single
parallel terminated line. The choice between the two
schemes will depend on the fanout number and physical
layout of the system.

Additional factors other than line length and transmls·
sion line termmations must be considered in system design.
S.ome of these are discussed here:
(I) Fanout- Thedcfanout capabllityofMECL lOKI IOKH
is very high since its high Impedance mputs require little
current (typically 160 pAl. System speed requirements
Will ordinarily be the Iimitmg factor for ac fanout. Capacitance increases with fanout and can cause rise and fall
times to slow down.
Figure 16 shows the rise and fall tImes of an MC 10K gate as a
function of fanout, both for 50
and 510
terminations. As
fanout increases, load capacitance (both device and interconnectIOn capacitance) increases, resulting in longer rise and
fall tImes.
Larger fanout will normally result in longer interconnecting lines with their longer line delays, so ringing can
become excessive. Under these conditions, use of properly
terminated lInes will result in best performance. A low
impedance (50 n) parallel terminated line has a shorter
propagation delay than a series damped or series terminated
line with equivalent fanout. However, multiple series term-

(2) Wired-OR - The outputs of several gates may be tied
together to perform the Wired-OR or emitter dot function.
One resistor is normally used to pulldown the outputs.
Figure 17 graphs typical rise and fall times and propagation delays versus the number of emitter dots for both
50 n to - 2 volts termination and 510 ohms to VEE
termination. Rise and fall times are not greatly affected
by emitter dottmg, with the exception of fall times With
the 510 n load mg. The reason for thiS is that the discharge
path for load capacitance has a longer time constant with
the 510 n resistor. The most significant effect of Wired~Ring is increased propagation delays. As for ac fanout,
deslfed system speed is the basic limiting factor for the
emitter dot.

184

(a) Load Lines for Termination to VEE (-5.2 Vdc) at 2So C
50
<{

:t

c: -

"
->
E
: t - - it

40

~

0

30

.s

r--- t--- r--r--- t---r - 200 n

::J

0

20

270 n

500 n

10

1 kn
2kn

o

o

/

,
-05

co
co

>

<{

..J

t

1 1/1Ii

rf
/

~

I

,I
~

H- t----+

/

I

I

I

I

I

i
I

/

-1.0

0

>

>

II

/

rr

I

I
r--I

..J

a

I

,

c

'E

..J

I
I
I

0,

~

)(

E

>

/

t1
7
II

r--- II
~j
/

/

-1.5

/

/

r---r - r---

-2.0

-

-25

V out (VOl. TS)

(b) Load Lines for Termination to -2.0 Vdc at 2sOC
50r-----,-------,------,-------,------,-------,------,-------,------.-------,

-2.5
V out • VOI.TS)

FIGURE 18 - MECL 10K Operating Characteristics

logic levels with output current. The ~ level shift and resulting
reduction of noise margin may be a greater limiting factor
than ac considerations. depending on system requirements.
When using Wire-OR, interconnections should be held
to minimum lengths for unterminated lInes and parallel
terminated lines. For larger numbers of distributed emitterdots and longer interconnectIOns, a doubly terminated lme
called a "data bus" may be used. Figure 19 shows an
example of a IOO-ohm data bus system. The de loading

A second limiting factor in the case of the emitter dot
is a dc level shift as the number of dots increase. The
wired emitter-followers share current through the pull down
resistor and each additIOnal wired output causes the current
in every output to decrease. The logic levels shift upward
as device current decreases. As the f/J level shifts upward,
noise margin may be lost. Figure 18 shows loading curves
for a typical MECL 10K output and illustrates the shift in

185

100

FIGURE 19 - 100·ohm Data Bus Line

50

FIGURE 20 - 50·ohm Data Bus Lme

on the line is 50 n as the 100 n terminatmg resIstors are
in paralleL However, for a transient waveform driven from
any point on the line, the waveform travels to either end
of the line and is properly terminated, so reflections are
ehminated.
A lower Impedance system is better for driving the hIgh
capacitive loading of a bus system. A so n system similar
to the 100 n system is shown in fIgure 20. Notice that
the drivers for the 50 n line must have two outputs in
parallel to drive the 25 n dc load of the paralleled 50 n
terminating resistors. The MCIOIIO/ or MClOllI multiple
output gates may be used conveniently in this application.
When considering system timing, it must be noted that
a long bus WIll add delay time to a data path. The worst
case length on the bus, plus the effects of capacitive load·
ing, should be considered for delay time. More will be
said on bussing 111 the foHowing section on board·to-board
interconnectIOns.

Clock

Clock

In

Out

(3) Clock distribution .- Clock hnes usually handle the
highest frequency in a system. For large fanout, a distribution tree should be used for maximum frequencies (fIgure
21). A good rule of thumb is to limit fanout to 4 per
line and use as Iowan impedance line as possIble. Parallel
terminated lines or series damped lines (as in fIgure 13)
may be used. A parallel terminated SO n l1l1e with a fanout
of 4 will drive a clock line to a frequency of about 110 to
120 MHz.
For higher clock frequencies, series terminated lines with
fanout limited to I or 2 may be used; line lengths should
be kept short and of equal length. A MECL III gate with
faster edges will provIde highest clock frequency capabi1Jty.

FIGURE 21 - Distribution Tree for a Clock Line
with Large Fanout

lQt;.

Conventional edge connectors may be utIlIzed to get on
and off PC boards WIth little mismatch 10 line impedances.
Coaxial cable connectors whIch have excellent characteristics across the bandwidth exhibited by MECL lOKI IOKH
eXIst in a variety of types. The most popular types are BNC,
and subminiature types such as SMA, 5MB, or SMC.

BOARD-TO-BOARD INTERCONNECTS
SIgnal connections among logic cards, card panels, and
cabinets are important for maIntaining the best possible
system performance. Ringing and crosstalk can appear
when lIne lengths are long, or when characteristIc impedance varies due to lack of a good ground. RingIng and
crosstalk, along with power supply varIatIons and system
noise, can seriously affect system operation. To be within
system noise margins (as prevIOusly mentIOned, 125 mV
worst case for MECL 10K), maximum undershoot should be
less than 100 to 110 mY.
The most practIcal means for limIting undershoot to less
than 100 mV is either to limit line lengths, or else to use
matched termInated transmission lines. Line lengths in
board-to-board applications are necessarIly long; therefore,
some kind of terminated line should be used. The edge
speeds of MECL lOKI IOKH permit a choice among several
methods for producing nominally constant impedance interconnections. Coaxial cable, mother-daughter boards, striplines, and wire over ground may be used.
When deSIgning system InterconnectIOns, four parameters must be taken into consideratIon.

(a)
(b)
(c)
(d)

SINGLE-ENDED LINES
Single ended lines are interconnections such as coaxIal
cable or other single path transmission line as opposed to
a twisted paIr of lines over whIch a differential SIgnal IS
sent. To maintain some kind of constant impedance, a
ground must be present. A ground plane may not be
present for board-to-board interconnects, and so a ground
must be run together with the SIgnal lIne.
Types of SIngle ended lines are discussed in the follow109 paragraphs.

(1) Coaxial Cable - The well defmed characterIstic impedance of coaxial cable permits easy matchIng of the
line, and the ground shield Internal to the cable minimizes
crosstalk between lines. In addition, low attenuation at
high frequencies allows the cable to transmit the rise tImes
associated WIth MECL SIgnals.
Bandwidth and attenuatIOn are the itmiting factors in
using coaxial cable. The bandwidth required for MECL 10K
IS:

propagatIon delay per unit length of lIne;
attenuatIOn of the lIne;
crosstalk between lines;
reflections due to mismatched impedance between
the line and the line termination.

0.37
f:::::---;
rise time

Propagation delay of the line is Significant because unequal delays in parallel lines cause timIng errors. Moreover,
on long Jines the total delay time wIll serIously affect
system speed. Since the propagation delay of one foot of
wire is approximately equal to the propagation delay of a
MECL 10K Series gate, line lengths must be minimized when
a total system propagation time is of concern.
Attenuation is a characteristic of the line whIch increases
for high frequency SIgnals, due to higher impedance in the
line. Attenuation first appears as a degradation in edge
speed, then as a loss of SIgnal amplitude for hIgh frequencies on long lines. WithIn a backplane attenuation seldom
is a problem, but it must be allowed for when interconnecting
panels or cabinets.
Crosstalk is the coupling of a signal from one cable to
a nearby cable. A coupled pulse in the direction of undershoot gives a reduction of noise immunity and should be
avoided. A good ground system together with shielding
is the best method for lImiting crosstalk. Differential twisted pair line connections avoid problems of crosstalk by
virtue of the common mode rejection of line receivers.
Reflections due to mismatched lines also cause loss of
noise immunity. Successful termination of a line depends
on how constant the impedance is maintained along the
line. Coaxial cable is easier to terminate than open wire
because of its constant impedance. In many cases twisted
pair cable and ribbon cable may be purchased with specificaticms on the impedance of the line.

0.37
::::: 3 x 10- 9 ;
::::: 125 MHz bandWIdth for 50

n load.

Attenuation is due mainly to sk10 effect 10 the cable.
The loss in signal amplitude due to attenuation will limit
the maximum usable length of lIne. For a maximum SIgnal
reduction of 100 mV from the logic 1 and f/J levels (800 mV
pip to 600 mV pip) the permissible attenuatIOn is 2.5 dB:

dB

=20 log ( -Yin- ) =20 log (0.8)
=2.5 dB.
Vout

0.6

The maximum line length whIch wIll produce no more
than 2.5 dB attenuation will be:

2.5 dB)
max length = 100 ft. ( - - ,
Atten.
where Atten. is the cable attenuation
opera ting frequency.

187

10

dB/! 00 ft. at the

400

IS easily wifed to connectors because of its in-line wire
arrangement. Its flexibility permits easy routing and board
removal. The slde-by-side arrangement of signal lines produces a defmed characteflShc Impedance because of the
presence of alternate ground wires.
Commercial ribbon cable IS avaIlable with a wide variety
of charactenstic impedances, and the manufacturer should
be consulted for informatIOn on such cable parameters as
attenuation, characteristic Impedance, and number of conductors.
With ubbon as With coaXial cable, the maximum permissible attenuation is 2.5 dB. Attenuation per foot is generally higher for ubbon cable than for coaxial cable. Consequently maxnllum lme lengths for ribbon are lImited by
opera tmg frequency.
(4) Pomt-to-point Wiring - A system made up of several
logic cards may be assembled usmg edge connectors to
form a card file. Pomt-to-pomt wiring via the board connectors may then be used for system mterconnections.
A ground plane IS often formed by a large prmted cirCUit
board to which the card connectors are mounted. TIle
ground plane may be connected to the frame holdmg the
card connectors. Metal is left on one Side of the PC board
to form the backplane system ground, or metal may be
left on both SIdes of the board to supply power to the
system logic cards. These card file systems are commercially
avaIlable from a number of manufacturers.
When a solId ground plane is not practical, a ground
screen should be constructed on the backplane. A ground
screen may be made by connectmg bus wires (wire size
compatIble With connector) to the edge connectors m a
gnd pattern, pnor to SIgnal wifing (figure 24). About

200

II.

:r:
f-

0
Z

w

-l

100
80
60
40

.....

r-.

...........

20
10
80
60
40
30

......

~ ~f....

...... RG59!U

........ .......

RG58/U
RG188A/U

400

7001000

r--

50 70 100

200

3000

FREOUENCY (MHz)

FIGURE 22 - Coaxial Cable Length versus Operating Frequency:
Constant 2.5 dB Loss Curves

Figure 22 shows curves for maximum line lengths versus
operating frequencies for a 2.5 dB loss Data for three
cable types are plotted. A high bandwidth lme IS necessary
to preserve fast signal edges regardless of the bIt rate of a
system.
In figure 22 It IS assumed that the coaxlallme is properly terminated with a reSIStive load equal to the characteristic impedance of the lme. Standard carbon 1/8 or 1/4
watt resistors work well for all line terminatIOns However
when using precision wire-wound or film resistors, care
should be taken to determine the high frequellcy properties
of these devices smce they may become highly mductive
at high frequencies, and thus be unusable.
Coaxial cable should be used for sendmg single-ended
signals over long Imes. The constant impedance and low
attenuation of such cable allows transmission of signals
with miIllmum distortion.
(2) Parallel Wire Cable - Multiple conductor cable as
purchased, or as constructed by lacmg mterconnectmg wires
together, is not normally used with MECL or other high
speed logiC types because of crosstalk. Such crosstalk is
due to the capacitive and inductive couplmg of SIgnals
between parallel lines. Such cable IS also susceptible to
external Signals coupling to the entlfe cable. Multiple conducJor, single-ended cable is not recommended for use
with MECL unless mdlvidual shields on each WIre are employed.
(3) Ribbon Cable - Systems requmng large numbers of
board-to-board mterconnections may take advantage of
multiconductor ubbon cable (figure 23). Ribbon cable

Ground Line

FIGURE 24 - Ground Screen Construction

every sixth pin on the card edge connectors is used as a
ground, providing connection points for the ground grid.
This interconnectIOn of ground pomts forms a grid network of approximately I mch squares over which the
Signal lines are wired. A charactenstIc impedance of about
140 ohms can be expected for a wire over ground screen,
dependmg upon the exact routing and distance from the
screen.

SIgnal Line

E@e@e@1
FIGURE 23 - Cross-Section of a Typical Multiconductor
Ribbon Cable

100

To provIde maximum sIgnal purity, a motherboard composed ot multIlayer or two layer board may be used to
mount the card connectors. Striplmes or microstnp lines
are designed on the circuIt board, along with ground and
voltage planes. Connectors are avaIlable to interface between cards and the motherboard wIth lIttle line dlscontmuity. The motherboard technique IS normally used when
the system design IS sufficlenty determIned that changes in
the backplane wIfing wIll be few.
When usmg pomt-to-pomt wifing wIth a ground plane
or screen, soldered connectIOns or wIre wrap techniques
may be used. In general one good terminatmg technique
is to parallel termInate wIth approxImately 100 to 120 n
to - 2 volts. The resistor will be near the charactenstic
impedance of the line and so mmImIze ringmg. Series
dampmg or termmation may be used, folloWIng the rules
presented previously. An unterminated line wIth a fanout
of 4 may be up to IS mches long when a ferrite bead is
placed at the sending end of the lme.
For high speed lInes, such those for clock dIstrIbution,
coaxial cable and twisted palf lines should be used between
cards. MaXImum sIgnal integrity of clock signals should be
maintained for best system performance.

B

FIGURE 25 - TWisted Pair Line Driver and Receiver

(a)

Out
1

I
1
1
1

I,
~;Rp
~

I

I

I
I

DIFFERENTIAL TWISTED PAIR LINES

6

Twisted pair lines, dIfferentIally dnven into a line receiver (figure 25), proVIde maximum noise immunity. Any
nOIse coupled into a tWIsted pair line appears equally on
both wires (common mode). Because the receiver senses
only the differentIal voltage between the lines, crosstalk
noise has no detrimental effect on the signal up to the
common mode rejection limit of the receIver. The line

VEE

In1

VEE

In2

(b)
Out

In 2

receivers MC101l5, MC101l6, MClOH1l5 and MClOH1l6
have a common mode rejection limit of I volt to a positivegoing common mode signal, and 2.5 volts to a negative-going
common mode SIgnal.
The partial schematic of an MC 10 115 line receIver is
shown in figure 26. Each receIver IS a dIfferential amplifier
whose output level is dependent on the mput voltage differential. If the inputs, INI and IN2, are at the same
voltage, the output will be at the mid pomt of a MECL
lOKI IOKH logic swing; that is, at -1.3 V =VBB (note that a
pulldown reSIstor on the output is necessary). The output
voltage wIll go more positive as input IN2 goes more POSItive than input INI; that IS when the differential voltage
from IN2 to INI is plus to minus. The inverse is also true.
The output goes more negative than VBB when the polarity
of the differential voltage from IN2 to INI is minus to
plus (cf figure 26b).
The output voltage change of the receiver IS equal to
the input voltage dIfferential times the voltage gain of the
amplifier. To have a full MECL swing, the output must
swing ±400 mV about VBB. Therefore, with the voltage
gain of the differential amplifier typIcally 6 VIV, the minimum input differential must be approximately. 0.4 V /6 =
67 mV (either plus to minus or minus to plus.)
For system design, other factors affect the miI1Imum
differential input voltage. Decreasing voltage gain with
increasing frequency (figure 27), offset voltage of the am-

In 1
V

ss

~

-1

3 V -t---:"..c---;----

FIGURE 26 - 1/4 MC10115 CirCUit Schematic

24

-:;1 >-

r---

20

c



E

j

1-0
1- 0

>!:!

HOrizontal Seale = 5 0 nstem

FIGURE 11 - VTT ac NOISE IMMUNITY WITH 2 ns
NOISE EDGE SPEED

In some cases it IS desirable to operate MECL circUits
with ground and +5 volt supplies. MECL CircUits operate

200

very well in this mode when care has been taken to keep
noise on the +5 volt supply lme to a minimum. The MECL
cirCUits are most Immune to noise on the VEE supply
line. With standard capacitor bypassing techniques, nOise
on the VEE line is controlled to safe system levels.
The amount of nOise present in a digital system IS
dependent on many factors - such as power supplies and
system enVlfonment. A primary source of nOise is crosstalk, which IS proportional to signal speed and Signal amplitude. The 800 mV logiC swing and relatively slow nse
and fall times of MECL 10K along with ItS ability to operate
in a transmission line environment, serve to reduce crosstalk
m a MECL system.
One factor contnbutmg to power supply noise IS the
amount of current "spiking" mherent in a logic family.
MECL circuits have emitter-follower outputs and differential-amplifier SWitches. Consequently MECL generates
very little noise. In fact, the high ratio of nOise Immunity
to mternally generated nOise m MECL, is a feature leading
to reliable system operation.

TESTING MECL 10K/10KH
INTEGRATED LOGIC CIRCUITS

INTRODUCTION
The use of high speed logic CIfCUltS can be very
beneficial to the system manufacturer. High speed logic
offers a better performance/cost ratio than slower logic
types, and thus an advantage In the competitive marketplace for digital ~qulp~ent Because of the high performance offered by logics such as MECL lOK/ lOKH, it may
be necessary for the user to adjust I11S test procedures to
get good test correlation between his measurements and
Motorola's device specificatIOns. Initially, correlation IS
important In the laboratory evaluation performed by a
potential circUit user. If data sheet performance can not
be venfied, It IS difficult to design with or use the parts.
After a decIsion to purchase components has been
made, the important test IS "incoming inspectIOn." This
testing IS often performed under conditIOns dlffenng from
data sheet specified operation. It IS possible to modify
Incom1l1g 1l1SpectIOn test limits to compensate for
temperature stabilization or alf flow and still insure that
parts meet data sheet speCificatIons. Motorola uses such a
technique in high speed final testing of the MECL
lOK/ lOKH and MECL III circuits.
Circuit performance must also be tested under system
operat1l1g conditIOns dunng system checkout and rework.
This testing need not be as thorough as component
evaluation, but It must not mterfere with overall system
operation. The tester should be aware of the effects of
system loading on CIfCUlt performance and possible
inaccuracies deriving from normal system checkout test
equipment operating at MECL IOK/lOKH circuit speeds.
This application note describes methods for testing MECL
lOKI lOKH circuits to obtain results which correlate with the
data sheet specifications. Test fixtures will be described and
examples of expected results from typical MECL lOK/ lOKH
circuits will be given. The parameters tested, and deviations
ofthese parameters from guaranteed values when circuits are
tested in other than the data-sheet-specified environment,
will also be discussed.

The 50-ohm transmission line system proVides several
benefits. By termmating all interconnectIOn Imes, Signal
reflectIOns are eliminated. TIllS results m waveforms
undlstorted by overshoot or ringing
With transmission line interconnections, the propagation delays of signal paths arc eaSily controlled and
matched. As an example of how cntlcal tillS can be, It
should be noted that at MECL 10K circuit speeds, signal lines
mismatched by 1.5 inches of length can cause a 10% error in
test results.
An additional advantage of the 50-ohm system is Its
capability to dnve 50-ohm test equipment mputs dlfectly
(oscilloscopes, frequency counters, etc.) Generally,
50-ohm mputs are more accurate and consistent than high
mput Impedance probes. Probe calibration is very cntlcal
when evaluating Circuits to within 100 ps accuraclCs.
Other factors influenCing test results include temperature and airflow. MECL lOKI IOKH circuits are specified at
25°C ambient air temperature, with 500 Imear feet per
minute air flow (to simulate normal system operating
conditions). The logiC outputs are defined after the CirCUit
temperature has stabilized under the above conditIOns
Because of a pOSSible different ambient elwlronment
temperature dunng testmg, MECL input and output logiC
levels may differ from speCified values by predictable,
small amounts due to a dlffermg circuit temperature
For example, testing in stili air would result m a higher
junction temperature, which would affect dc test results
slightly. In many cases this small change m parameter
values can be Ignored, because the parts have a sufflclen t
guardband to remain within speCification limits. In other
cases the logic test levels should be altered to compensate
for CirCUit temperature. Methods for calculatmg Junction
temperature and modified test logiC levels Will be shown
m the sectIOn on high speed test1l1g later in this note.

Factors Involved in Testing

A MECL 10K/I0KH Test Fixture

With circuit speeds of 2 ns for 10K and I ns for lOKH,
some of the methods used for testing and evaluating such
circuits must be modified from techniques used with lower
speed circuits. To determine circuit performance accurately
it is necessary to minimize distortion from outside sources.
The technique used with MECL lOKI lOKH and MECL III
circuits is to keep the complete test system in a controlled
50-ohm transmission-line environment.

Figure I shows the schematics for typical MECL
lOK/lOKH test fixtures. A pulse generator capable of
generating pulses with MECL lOK/lOKH edge speeds is
connected directly to the logiC CIfCUit mput. The
generator line then continues to the 50-ohm 'scope where
It IS properly terminated by the 'scope m ItS characteristic
50-ohm Impedance. The Junction pomt at the gate input is
kept as short as possible (normally under 1/2 Inch) to

201

minimize any impedance dlscontJlluities arisJllg at this
pOlO t. All interconnecting cables are 50-ohm coaxial
cable. RG 188AU or equivalent coax is commonly used
because of Its flexibihty and thll1ness.
The output of the MECL CirCUit IS connected to the
other 50-ohm 'scope input with a similar 50-ohm cable.
The cable from the circuit JIlPut to the 'scope, and the
cable from the circUit output to the 'scope, are equal JIl
length to ehmll1ate propagatIOn delay skew due to
differing signal propagation delay times 111 the cables.
Cable length from the pulse generator to gate II1pUt IS not
critical Long cable lengths should be aVOIded because of
bandwidth limitations which would arise from their
exce~Slve length. Up to S-foot cable lengths can be used
with MECL 10K circuits without problems.

OSCIlloscope

An Important feature of the test fixture is the usc of
50-ohm termJllated IJIles for all signal JIlterconnections.
Proper matched-Impedance termination minimizes reading
dIstortions which might be caused by signal reflections or
crosstalk. The 50-ohm drive capability of the MECL
IOK/IOKH families and the fact that circuits are specified
with 50-ohm loads are factors which aid in testing and
evaluaiton of the parts. By eliminating high impedance
probes, testing accuracy and repeatability of results becomes
very good.
MECL IOK/IOKH outputs are specified when driving
50-ohm loads to -2 Vdc (measured from ground). However,
the scope input is itself a 50-ohm impedance to ground. For
this reason, the normal -5.2 volt power supply for MECL
(under normal conditions) is offset by 2,0 Vdc in the test
fixture as shown in Figure la. VCC is connected to +2.0 Vdc
and VEE to -3.2 Vdc. This permits terminating all signals in
the system to ground.
The full military temperature range parts in the MECL
10K product line (MCI0500 and MCI0600) are specified for

+2V -32V

FIGURE 1B - Test Fixture Schematic for MC10,500 & 10,600
Series Parts

driving IOO-ohm (minimum) loads. To test these parts, the
test fixture is modified as shown in Figure I b, by the addition
of a 50-ohm series resistor on the gate output. This
arrangement still allows use of the oscilloscope 50-ohm input,
but does cause a 2-to-1 amplitude reduction which must be
taken into consideration when interpreting 'scope readings.
Capacitor bypassJllg at IC sockets IS used on both
power supply hnes to ehmJllate the possibilIty of voltage
noise spikes. Such nOise can be caused by the voltage
source at the cirCUit respondJllg to current fluctuatIOns
during cirCUit switching. The current fluctuations anse
from unequal output current requirements between the
logic levels, rather than from noise generated by sWItching
111 the baSIC MECL gate cirCUIt. Supply voltage spikes
could distort ac test II1formation. They can be removed by
heavy capacitor bypassing as shown 111 Figure I. The 0.0 I
~F capacitors should be an RF (low JIlductance) type.
A MECL 10K test fixture for component evaluation
IS shown in Figure 2. The front view shows the miniature
coaxial cable connectors for each circuit signal lead. The
connectors are WIred dIrectly to the IC pins with
semi-rigid 50-ohm coaxIal cable*. These cables are
matched 111 length for equal propagation delay. Outputs
are easIly observed by connectmg a cable between the pin
connector and the 'scope input. For best test results,
unused circuit outputs should be term1l1ated with 50-ohm
loads at the connector.
The output from the pulse generator is connected to
the pulse input connector of the test fixture. This signal is
routed to a terminal near the cirCUit pins via semi-rigid
coax cable (cf Figure 28). A jumper runs to the desired IC
input pin wIth a short wire. The jumper IS soldered JIl as
necessary to drive different input pins. A coaxial cable

OSCIlloscope

+2V -3.2V

*e.g., Precision Tube Co., "Coaxltube" AA50085, or
equIValent.

FIGURE 1A - MECL 10K/10KH Test Fixture Schematic

202

connected to the +2 Vdc bus close to the package. ThIs
l1l1e IS well bypassed to ground. The VEE line IS similarly
connected to pIn 8 WIth a heavy bus and bypass
capacItors.
The MECI IOK/IOKH circuits should be plugged into a
low-profIle Integrated CIrcuit socket. An alternate approach IS to remove the pins from a low-profIle socket and
connect these P1l1S to the circuit board material from
which the test set IS built. (This approach has been found
to be more appropnate when heavy use of the test fixture
IS expected.) The SIze of the test fixture IS made
compatible with the oven used for thermal testIng
ThIS type of test fixture is eaSIly constructed and IS
very good for low-volume laboratory evaluatIons. The
fixture is acceptable for testing any 16-pin MECL lOKI IOKH
circuit, and the results will be very precise. The limitation of
this type of test set comes in the handling of parts, and test
equipment controls for large volume testing. For large
volume testing an automated system is preferable.
Test Parameters
CirCUIt tests are usually performed to confirm data
sheet speCIfIcations. These tests are of two general types:
dc testing, and ac testing. DC testIng measures logic levels
or noise margIns, circuit current, and input currents. AC
testIng measures propagation delays, edge speeds, and
flip-flop toggle rates. It should be noted that MECL
IOK/lOKH dc parameters are specified with a grounded
VCC,-2 Vdctermination, and -5.2 Vdcon VEE (as the parts
are normally used in a system).
Nominal AC parameters are specified with the test fixture
at +2.0 Vdc on VCC, ground termination, and -3.2 Vdc on

2B

BOTTOM

VEE as discussed earlIer. Other cirCUit parameters not
Included in the data sheets, but often measured, include:
input capaCItance. input Impedance, and output Impedance. The dIfficulty of performing these tests with
·0650
·0850

Ul

1

·1.050

1\/

I...J

0

·1.250

:l

rI

A

?
·1.450

With emitter 1 current so urcle
l

V\

0

>

OR OUTPUT

·1.650

r--

.:':::':: I"-::

-1850

TOP

2::.

NOR OUTPUT

·2050
·20

FIGURE 2 - Views of MECL 10K Test Fixture

-18 -1.6

-14 -12

-10 -08

:.:-u

'L- With emitter
resistor

-06 -0.4

-02

0

Vm (VOLTS)

from the IC Input pin connector on the front panel of the
test jig, to the 'scope 1I1put, provIdes for observ1l1g the
1I1pUt pulse and term1l1at1l1g the pulse generator.
The three power supply Inputs are' ground; +2.0 Vdc;
and -3.2 Vdc. The Inputs are routed through standard
banana plugs, for easy connectIOn to power supplIes. The
ground Input IS connected to a reference voltage plane and
to all coaxial cable or connector shields. The +2 Vdc input
IS bussed to pInS 1 and 16 wIth a WIde bus WIre, or the
metal of a CIrCUIt board. Both pins 1 and 16* are

FIGURE 3 - Typical MECL 10K Transfer Characteristics
The solid curve shows the transfer behavior for the basic
MECL 10K OR/NOR gate_ The dotted section of the curve
describes the transferfunction for parts such as the MC1 01 07. and
most MSI circuits. These have a constant current source in the
emitter node of the internal switch.

*On a few deVices only one of these pins IS used for VCC- Consult
speCifiC part data sheets.

203

If a samplmg OSCilloscope With a digital readout IS used,
the test circuit waveforms for an OR gate function Will
look like Figure 4. The intensified zone on the waveform

high-speed fmal test equipment makes speclfymg these
parameters Impractical for standard parts.
MECL circUit transfer characterIStics arc often plotted
during device qualificatIOn. Plottmg transfer charactenstlcs IS accomplished by puttlllg a vanable mpu t
voltage on the ClfCUlt mput and measurmg the output
voltage. Figure 3 shows the typical transfer characterIStics
for MECL 10K logic functions. The test fixture previously
described in this note may be used for transfer characteristic
measurement by connecting a power supply to the input pin
through the coaxial connector and loading all output pins
with 50-ohm loads. The output of a selected load is then
connected to a voltmeter. Loads other than 50-ohms may be
used to evaluate circuit performance, but the data sheet
values are specified with 50-ohm loads*. The 50-ohm load
specification is a worst case test condition. With lighter loads,
the MECL circuits will have a larger logic swing. Since the
circuit will be operating in the linear transfer region during
these measurements, a small capacitor (0.1 J1F) on the
output of the MECL circuit Will eliminate any possible
oscillation which could cause distorted readings.
DC transfer curves for CIrCUits With mternal feedback
(wch as the MECL master-slave flip-flops) cannot be measured. However, threshold pOlllts can be determllled by
measunng the mput voltage at which sWltchmg occurs.
TI1IS is commonly done by putting a ramp signal on the
circUit input and observmg the pomt at willch the CirCUit
sWitches With an OSCilloscope.
NOise ~Ifl IS a measure of the protection against
adverse operatmg conditions bUilt into MECL. NOise

1Delay I
...-.'I

I
I

I
I

-

:1:
50%.
III
I

1111
I

~

)

-

~

II
'111: I L III
;:rTT II I
IT;

,'T~

","

~

1111
II

I

I Lli
1111

I111
111I

50%

V 1
1/

Vert,cal ~ 200 mVtcm
HOrizontal ~ 20 nstem
Test Gate = MC10109

FIGURE 4 - MECL 10K Propagation Delay

shows the time interval of measurement - about 2 ns for the
MECL 10K device under test. When a digital readout is not
used, the delay time IS determined from the scope traces by
visual methods.
I-

~

-::-

I

margin is specified as the voltage difference between the
specified input thresholds (VIHA min or VILA max for 10K,
VIH min and VILmax for IOKH) and the guaranteed output
thresholds (VOHA min or VOLA max for 10K. VOH min
and VOL max for IOKH). As shown on the device data sheet
the noise margin is 125 mV for a HIGH output logic level and
155 mV min fora LOW output logic level for MECL 10K and
150 mV for both high and low for MECL IOKH.
The noise margm values are found by calculatmg the
difference between VIHA and VOHA, and between VILA
and VOLA, respectively. Further IIlformatlon may be
found m reference I or 2. By settmg the threshold
voltages by means of a power supply, and uSlllg the same
test fixture employed to measure the transfer characteristics, the output levels can be measured and nOise
margms calculated.

III II III I I
I I

)

ilII

,'l

V-

-

f-

....i~

,~ ~III

V J

-

Test Gate

I111

r:
~

I-

80%

11I1
III

IIII
1111

III1
1111

I111
1111

1=
~

I-

~.

--=

EI-

~

~

II

20%
'VertIcal = 200 mVtcm
HOrizontal = 2 0 nstcm

MC10109

FIGURE 5 - MECL 10K Rise Time

Rise-time and fail-time testing IS Identical to propagation delay measurmg except that the output waveform IS
measured for slope. With MECL lOKI IOKH the output is
specified from the 20% to the 800/0 points, The other MECL
families are specified between 10% and 90%. Because of the
designed-in rounding of the upper 20% of a M ECL
lOKI IOKH waveshape, the 10% to 90% waveform is difficult
to measure accurately. However, the 20% to 80% time is
representative of the slope during the active transfer region of
the MECL circuit input.
A typical rIse-time test waveform for a MECL 10K circuit
IS shown in Figure 5. The intensified trace is shown for a 20%
to 80% test and is approximately 2 ns. The 10% to 90% rise
time would be about 3.2 ns. The 20% to 80% rise time of
M ECL 10K H is approximately I ns with a 10% to 90% rise
time of 1.8 ns.

Prop'?gatlon delay~ are mea~ured by connectlllg a test
CIrCUit as shown in Figure I. For all MECL circuits
propagation delay is measured from the 50% amphtude
pomt on the input signal to the 50% pomt on the .
The upperfrequency limit ofMECL lOKI 10KH flip-flops
is commonly due to the output LOW level fadmg to remalll
at specified voltages, rather than to a failure to toggle.
Figure 6 shows a MC 10 131 dual "0" flip-flop operatmg at
150 MHz The deVice still has a MECL signal sWlllg at ItS
output. However at about 160 MHz, the LOW level output

maximum of 550 /lA, a value only sltghtly more than two
slllgle gate mpu ts.
I nput current requirements for a LOW level logic Signal
IS less than for the HIGH level The Signal must stdl dflve
the Il1ternallllput pulldown reSistor, but the MECL SWitch
Il1put current consists of only a small amount of reverse
leakage current when the mput transistor IS off.
Other circuit parameters often tested but not speCified
on the data sheets Illclude output lInpedance and IllpUt
capacitance. The dc output Impedance IS measured by
changlllg the loadlllg of the MECL output and observmg
the change III output voltage. The change III output
voltage diVided by the change III output current gives an
output Impedance of about 7 ohms for a typical MECL
lOKI IOKH circuit.
!"!!put capacitance IS more difficult to measure and
normally requnes a tlIne domall1 reflectometer, a stnpltne
reflectometer setup, or a current probe transformer (e g.,
Tektrolllx CT-I, or equivalent). Testlllg has ~hown the
typical input capacitance for M ECL 10K/10K H gate clfcuits
to be about 2.9 pF. The details needed fOf testing mput
capacitance may be found in Chapter 7 of the M ECL System
DeSign Handbook, referenced at the end of thiS note.

would flse out of specified ltmlts for the part under test.

High Speed Testing
High speed testlllg techlllques are normally used when
a large volume of parts must be checked High speed
testmg usually Il1volves a mach me wlllch automatically
checks a part for all the tested parameters Without
manually settlllg controls for each test. To take advantage
of the speed of such machllles It IS normally undeSirable
to prOVide air flow or to WaIt for the circuit under test to
temperature stablltze*. Consldeflng that the test will be
performed With the chip temperature near 25°C. It may
be necessary to compensate the test parameters so the
circuit Will be with III the speCifications at stablltzed
operating conditions. Each M ECL 10K CirCUIt is designed to
have the same input and output logic levels at the specified
ambient of 25° C and 500 linear feet per minute alf flow,
regardless of power levels within the package. Therefore, the
amount of compensatIOn for high speed testing Will depend
on the power dissipation of the Circuit.

FIGURE 6 - MC10131 Toggle Rate Test

DC Considerations
Power ~RPJy current dram IS specified at the VEE
negattve supply pin of the IC package By measurlllg IE,
the current out of thiS node, the deVice can be specified
Illdependently of output loadlllg. Because of the Wide
vanety of possible output loads for MECL IOKllOKH
cirCUIts in system operation, it IS impossible to specify power
for every possible loading situation. The power supply
current drain defines power reqUIrements for the logic
current switches and bias dnvers in the package. When
calculating system power it is necessary to add power due to
input current drain and output loading, to the speCified
power for the package based on Po =IE X VEE.
!!.tp~ current requirements for a MECL lOKI IOKH par~
depend on the use of the IllpUt. The baSIC specification of
265 p,A (maximum) appJtes for a fan-Ill of one gate load.
The mput current for a HIGH logiC level IS diVided between
the mternal IllpUt pulldown reSIStor and the current
SWitch lllpUt of a MECL CircUIt. Since only one pulldown
resistor is reqUIred for a multiple fan-m pin, mput current
IS nut directly proportIOnal to the number of curren t
SWitches bemg dflven in the package. For example, a
four-gate strobe mput m the MCIOIOI IS speCified at a

JunctIOn temperature T J (under normal system operation) may be calculated

e

T J = Po J A + T A,

e

where J A IS the thermal reSIStance of the package (] unction to ambient) about 50 0 C/W With 500 llIlear feet per
mmute air flow, and TA IS the ambient temperature From
the above equatIOn, the J unctIOn temperature for a 200 mW
part Will be 35 0 C for a 25 0 C ambient temperature. TIllS
results III a stablltzed Junction temperature 100C above
the 11Igh speed test temperature for the 200 mW part.

*In about 10-15 ~ec, the deVice Will have reached 80% of
equlhbnum. A 5-mlnute delay pnor to making measurements, IS
more than adequate to Insure full stablhzatlOn.

205

For MECL 10K parts, the change in the HIGH logic
level, VOH, Isabout I 4 mV/oC and the change 111 the LOW
logic level, VOL, IS about 0.5 mWtc. USll1g the above
200 mW part, the 10°C lower Junction temperature would
shift VOH 14 mV more negative and VOL 5 mV more
negative.
The IIlput signal requlfements are controlled by the
temperature trackillg of the respective output levels. VIH
levels wIll be shifted by the VOH factor of 1.4 mVtC and
the VIL level wIll be shifted by the VOL factor of 0.5
mVtc. When calculatmg the power to determll1e thermal
slllft1l1g, It IS also necessary to mclude the power diSSipated
by the output deVices, e g. [Poutput = (No. of outputs) X
(10 X VD»)·
It can be seen that these small changes 111 output levels
would 1I0t keep the majorIty of parts from meeting
speCified performance If the test parameters are not
altered There IS suffiCient nOise marglll buIlt into the
CirCUits, plus a safety factor between Motorola fmal test
specifications and the limits specified on MECL lOKI IOKH
data sheets, to overcome most test environment differences.
However, some of the more complex MSI functions can
dissipate around 600 mW. If these parts are tested without
allowing the circuits to temperature stabilize, the logic levels
may be sufficiently different to offset incoming test yields. In
such a case, test level compensatIOn should be considered.

some overshoot and rInging may be attenuated, the speed
IS suffiCient to determme that the CIrCUits are operating
properly. USll1g OSCilloscopes With less than 100 MHz
bandWidth is not recommended because such 'scope wIll
se[lously degrade the presentatIOn of the MECL Signals
and may not see Signals which affect operatIOn of the
MECL CIrcuits.
It IS also pOSSible (and usually deSIrable) to use high
Impedance probes durmg system checkout. However, the
ground reference should be connected to the probe tiP
and kept near to the pomt under test. Havmg a separate
ground wire from the 'scope to the system (111 place of a
probe ground) Will cause distorted readll1gs because of the
length of the ground run 111 relation to Signal speed.
Other types of laboratory equipment, such as power
supplIes and voltmeters, have no speCial performance
reqUIrements Imposed on them when used for MECL
testing The ac response time of the power supply IS not
espeCially CrItical because of the large amount of capacitor
bypassll1g used on a MECL test fixture. DC voltmeters are
normally used to measure output logiC levels dUrIng dc
testmg, because of their higher accuracy than an OSCilloscope.
Conclusion
Testing MECL IOK/lOKH circuits requires special techmques to insure accurate results. However, if these techniques
are practiced, testing high speed integrated Circuits is no more
difficult than testing lower speed parts. The use of a
transmission line system greatly improves the accuracy and
consistency of high speed digital testing. By using test
techniques consistent with Motorola's component evaluation
and final test, the circuit user can obtain test results which
correlate well with Motorola's data sheet and other test
mformation.

Test Equipment
The mall1 factor when selectmg test equipment to work
With MECL CIrCUits IS the high frequency capabilIty of the
test Ulllts Pulse generators must have 50·ohm output
drIVe. III addition, edge speed and offset must be MECL
compatible The 50·ohm drIVe IS characterIstic of Virtually
all 11Igh speed pulse generators. It IS necessary to drIve
coaxial cables or other 50·ohm Imes at 11Igh speed Without
Signal distortion due to Improperly terminated lInes
When testing MECL lOKI IOKH, a pulse generator should
be set to 2.0 ns 20% to 80% edge ~peeds. The offset and
amplItude should be adjustable to MECL logiC levels.
When drIvmg a test fixture With a +2.0 Vdc supply on
VCC, the logiC levels are +1.11 volts and +0 31 volt. It IS
also deSIrable to have the pulse generator capable of
interfacing with M ECL 10K IIOK H operating with grounded
VCC In tillS mode of operation the logiC levels are
typically -0.89 volt and -1.69 volts.
The selection of an OSCilloscope depends on where the
'scope IS to be used. The reqUIrements are different for
component evaluation and for system checkout. A good
samplmg scope IS normally needed for deVice qualIficatIOn
because of the accuracy requlfements entaIled when
measurmg 100 picosecond mcrements. However, 500 MHz
real time 'scope wIll give good results. All of these 'scope
can be purchased With 50-ohm mputs which are compatible with MECL IOK/IOKH test fixtures.
When performmg system checkout, a real tlme'scope of
at least 150 MHz bandWidth IS normally adequate. WhIle
edge speed wIll be degraded by thiS bandwld th, and while

206

INTERFACING WITH MECL
10K/10KH INTEGRATED CIRCUITS

INTRODUCTION

which are not digital logical levels These may be low
amplitude mput signals which must be amplified before
they can be used and low frequency Signals which require
shapmg. The linear characteristics of the MECL lme
receivers allow these cirCUits to be used as amplifiers or
Schmitt tnggers.
Another important interface requirement is dnving optic
displays. The MECL lOKI IOKH outputs are directly compatible With light emitting diode requirements. MECL
circuits are also available for driving other types of displays.

The MECL lOKI IOKH series are high speed logic families
designed for applications where system performance is
important. Emitter coupled logic is used to obtain the
required circuit speed and provide the circuit features
necessary to optimize high speed system design. All MECL
IOK/lOKH circuits interface directly with each other. In
addition, MECL IOK/lOKH Cifcuits are completely compatible with the very fast MECL III circuits, permitting a
designer to mix all families in the same system for best
performance.
MECL lOKI IOKH circuits normally operate with ground
on VCC and a negative 5.2 Vdc power supply on VEE. While
MECL may be used with ground on VEE and +5 Vdc on
VCC, the negative supply (Iperation has noise immunity
advantages and is recommended for larger systems.
Also, emitter coupled logic operates with a relatively small
800 mV logic swing. With the -5.2 volt power supply the
normal MECL lOKI IOKH high logic level is about -0.9 volt
and the low logic level about - J. 7 volts. For these reasons
MECL lOKI IOKH and MECL III are not directly compatible with the common slower speed logic types such as TTL,
DTL, and MOS. Translators must be used when interfacing
these logic types with MECL.
In many designs it

IS

INTERFACING WITH TTL
The most common mterface requirement for MECL IS
With TTL logic levels. This occurs when a MECL system
must mterface with an eXisting TTL system or when both
MECL and TTL are used m the same system design. The
interface requirements between MECL and TTL depend
on how the circuits are being used.
The normal MECL/TTL Interface occurs when MECL
is powered with a -5.2 volt power supply and TTL with
+5 volts. The use of a common ground and separate power
supplies helps Isolate TTL generated nOise from the
MECL supply lmes. The MECL/TTL translator ClfCUltS,
MC10124, MC10125, MCIOH 124 and MCIOH 125 shown In
Figure I provide this interface.

necessary to mterface with Signals

MC10125/MClOH125
Quad MECL to TTL Translator
(With Totem Pole Outputs)

MC10124/MC10H124
Quad TTL to
MECL Translator
With Strobe

4
6

10

'--~"-~12

15
11

GND = 16
VCC (+50 Vdc)

=9

VEE (-52 Vdc)

=8

13

14

L..----_O
FIGURE 1 - MECLITTL Translators

207

1

VB B

A feature of the MCI0124jMCI0125 pair IS the abIlIty
to operate over long dlstallce~ wltll a tWIsted pau llI1e
FIgure 3 shows the fleXibilIty of using these parts With
tWisted paIr lInes as any combll1atIon of MECL and TTL
II1pUtS and outputs can be Il1terfaced with MECL signal
levels on the mterconnectmg Imes.
The complementary outputs of a MECL gate or the
MC10124 translator and the dIfferentIal inputs ofa MECL
line receiver or the MC 10 125 translator are used with a
tWisted pair line to send Signals over long distances. Since
the line receiver looks at the voltage difference between
the two Il1put Signals and not the absolute value, the
CIfcuit has good nOIse rejectIon capability. A noise pulse
couphng into the twisted pan lme appears equally on
both of the Ime receIver mputs and is rejected as common
mode nOise. The differential operatIOn IS also advantageous
when two sectIOns of a system are not connected With a
solId ground or power Ime. The power supply offset
appears as common mode signal to the receiver and IS
rejected withm the IlImts of the receiver. The MECL to
TTL translator typIcally rejects common mode Signals
greater than plus or minus 2.5 volts before the output
fails to remain within speCIfied 11J11Its.
When high speed SIgnals are transmItted on long lInes,
termination techmques should be used to mmimize reflectIOns and waveform dIstortion. These reflections cause
rll1gll1g on the slgnallll1e whIch If severe enough wIll effect
system noise lllunumty. The deSIgner should conSIder using
tenmnatIOn resistors when the two way propagatIOn tlIne
of the llI1e IS greater than the rISe tII11e of the SIgnal on the
hne for best system performance. FIgure 3 shows the use
of a parallel termll1ation reSIstor, RT, at the recelVlng end
of the lIne. The value of RT should match the line impedance whIch IS about 110 ohms for common tWIsted
palf hnes
A common applIcation for the MECL translators IS high
speed lme dnvers and receIvers 111 an all TTL system. The
TTL system sees only the translator TTL inputs and
outputs, but takes advantage of MECL lme drivll1g capabIlIties to send SIgnals from one point to another m the
system The gam of the MC 10125 IS typIcally greater than
15 volts per volt makll1g the clfcuit a useful lIlput deVIce
for interfacmg to TTL lOgIC levels

The MC10124 IS a quad TTL to MECL translator, wIth
a common TTL strobe Input and complementary MECL
outputs. The propagation delay through the CIfcuit is
typically 5 ns and the top operatIng frequency is normally
greater than 85 MHz. If maxImum operating frequency
tests are made wIth the 5.5 ns input nse and fall times
specIfIed on the component data sheets, operating speed
IS lImited to 70 MHz because of Input restrictIOns. WIth
faster rise and fall times on the mputs, CIrCUIt speed
increases untIl the output fails to reach specifIed Illmts
at about 85 MHz.
The MCIOH 124 is the MECL IOKH version of the
MC 10124. The propagation delay is typically 1.5 ns as
opposed to the 5 ns typical for the MC10124.
Motorola also offers a vanatlOn of the MC IOH 124, the
MC IOH424. It is also a TTL-to-ECL translator and has the
same pinouts as the MCIOH 124 but it has an ECL strobe
instead of TTL.
The MC10125 IS a quad MECL to TTL translator with
dIfferentIal amplifIer inputs and Schottky clamped tran·
sIstor "totem pole" TTL outputs. PropagatIOn delay
time for the circUIt is a functIon of fan-out loading as
shown by the curves in FIgure 2. As with the MC 10 124,
maximum operating frequency is lImIted by the output
falling to reach specified output levels above 85 MHz
The MCOI H 125 is the MECL IOKH version of the
MC10125. The propagation delay is typically 2.5 ns with a
fanout of 5 as opposed to 5.5 ns for the MECL 10K part.
65~----~----~------r------.----~

]

55

;;Qj
o
c:

o

~a.

~ 35~----4------+------~-----r----~

25L-____~____~______~_____L----_7

a

4

8

10

Fanout

FIGURE 2 - Propagation versus Fanout for the MC10125

vm

114 MC10125/MC10H125

1/4 MC10124/MC10H124
TTL In

=U=

VEE

0"'

1/4 MC10115/MC10H115

1/4 MC10101/MC10H101

=t>-M'CLO"'

MECLln==lX"

VEE

RT = 20

FIGURE 3 - Use of TWisted Pair Line with MECL and TTL Signals

208

Some designs are restricted to using only one power supply
thus the MClO124 and MClO125 cannot be used. Therefore
Motorola developed the MClOH350 single supply ECL to
TIL translator. The device was designed to operate from a
single power supply of either +5.0 V or -5.2V. The MC IOH350
incorporates ECL differential inputs and Schottky 3-state
outputs. The 3-state outputs produce a high impedance
output when the output enable (OE) is brought high.

INTERF ACING WITH TTL BUSSES
In many system designs it is necessary to he several
pieces of equipment together with input/output bus lines.
These lines are time shared with the various sections of
the total system, requiring that only one line driver be
active at a tIme. Three state TTL is commonly used in

MC10128
BUS DRIVER
D 1 1 0 - - -.......o.ID

Clock 100--.1--"'-'

Re~t

70---~,--~

DIsable 1 1 2 o--t-t------+-<~-------...J

50--t-t------+-<.----------,

DIsable 2

D2

6

0--+-+--1 D
02

Strobe

30-----------1

Control 2

MC10129
BUS RECEIVER

DO 7

14 00

D1 13

15 01

D3 4

HystereSIS

Control
Clock 11 U - - - - - - - - - '
Reset 1 0 o-----------4t-~
Strobe 1 2 U - - - - - - - - - - - - - . . . . J

FIGURE 4 - MECL to IBM or TTL Interface Circuits

209

3

02

2

03

when interfacmg with TTL three state dnvers since the
TTL circuits are commonly rated at 2 rnA and 2.4 volts
for a high level output. The curve In Figure 5 shows typIcal leakage current of the MCIOl28 bus driver with the
output disabled. This current should be conSidered when
figuring loading on a TTL driver. The MECL part is rated
for 50 rnA at 2.5 volts, therefore loading is not a problem
for the MClO128 drivmg disabled outputs.

these applications because of the ability to disconnect
the dnver from the line. When disabled, the driver does
not appear as a heavy load to the active driver or as a low
impedance discontinuity to the bus line. The MClO128
Bus Driver and MCIOl29 Bus Receiver shown in Figure 4
are designed to interface a high speed MECL system into
a TTL compatible bus line.
The MClO128 is a dual bus driver with MECL inputs.
Internal latches are prOVided to free the data inputs whIle
waiting for the information to be used. When the clock
input is held at a low logic level or left unconnected data
passes through the latch. Disabled inputs are provided for
each bus driver to control the three state output. A high
MECL logic level on a disable line causes the driver output
to go to a high impedance state overriding the strobe,
but the clock and data inputs can still be used with
the latch.
Leakage current mto a disabled output is important

The MC 10128 bus dnvers have control inputs which
control the mode of Clfcuit operation. When a control
input IS left open the bus driver operates in a TTL compatIble bus system. With a grounded control input the
bus driver outputs are compatible with IBM System 360
I/O bus requirements. IBM compatibility will be discussed
in a follOWIng sectIOn
The MC 10129 quad bus receiver accepts TTL or IBM
bus logic levels and translates to MECL outputs. Internal
latches are provided to free the bus lines while waiting for
the data to be used. The circuit features a hysteresis
control input which changes the threshold pomts for
circuit switching as shown in Figure 6. In normal operation the hysteresis input IS connected to VEE giving
guaranteed mput threshold pOints of 2.0 volts for a l11gh
logic level, and 0.8 volt for a low level With TTL mputs
(I.7 volts and 0.7 volt with IBM bus inputs). Figure 6a
shows the transfer characterIstics when the hysteresIs
feature IS not used.

12

10

~

.5

!
U

'"

08

06

CI

'"
''""

.><

...J

04

02

./

V'./

o

30

20

10

/

/

/

/

In a high nOise environment hysteresIs IS added to the
CirCUit by connectmg the hysteresIs control mput to
ground. In the hystereSis mode high level threshold points
are speCified at 2.6 and 1.9 volts. The cirCUit is guaranteed
to recogl1lze a high level II1put below 2.6 volts, but the
input may drop to 1.9 volts and remain a guaranteed high
level. The low level threshold points arc 1.0 volts and
1.7 volts. Typical transfer characteristics and specified
MC 10129 t1ueshold pomts m the hysteresis mode are
shown in Figure 6b. The hysteresIs IS the input difference
between the rismg and failIng output edges and is nearly
700 mV 111 the figure.

50

40

Output Voltage (Volts)

FIGURE 5 - Output Current into a Disabled MC10128 Bus Driver
No HystereSIS

o

With HysteresIs

-04

-08

::l

~ -1.2

-1 6

6b

6a
~-

-20
1 0

14

18

22

26 10
V,LA

14

18

22

V,LA

FIGURE 6 - Transfer Charactenstlcs of the MC10129 Bus Receiver

210

2 6

I
V IHA

INTERF ACING WITH TTL ON A COMMON POWER
SUPPLY

Figure 7 illustrates a bus line using both TTL and
MECL bus dnver and receiver citcUltS. Any standard pull
up or termination resistor network presently used on the
TTL bus Will be compatible with the MCIOI28. Thus
with the MClO128 and MClO129 It IS possible to directly
interface a high performance MECL system into many
existing minicomputer I/O bus lines.

In many system deSigns where a small number of
MECL circuits are used, it IS desirable to operate both
MECL and TTL on a +5 Vdc power supply. MECL works
very well in this mode if care is taken to Isolate the TTL
generated noise from the MECL +5 volt supply line.
Translators for interfacing TTL and MECL in thIS mode
are built with discrete components smce Integrated circuit
translators do not operate on a smgle +5 volt supply
The TTL to MECL translator shown in Figure 9a
consists of three resistors in series to attenuate TTL
outputs to MECL input requirements. The translation is
very fast, normally under I ns, depending on wiring
delays and stray capacitance.
Two techI1Iques for Interfaclllg MECL to TTL are
illustrated in Figures 9b and 9c. The CIrcuit m Figure 9b
takes advantage of MECL complementary outputs to drive
a differential amplIfier made from two PNP transistors.
Speed of this translator IS in excess of 100 MHz when
dnving one TTL load. The circuit in Figure 9c uses only
one PNP transistor to perform the translatIOn, but IS
slower than the differential approach Typical translatIOn
delay tJlne is less than IOns when dnvmg one high speed
TTL load. Both of the MECL to TTL translator designs
use a pull down resistor to ground to sink the low level TTL
mput current. For this reason fanout IS normally limited
to one TTL deVIce unless resistor values are changed.

Mel 0128, Three State, or
Open Collector Drtvers

~,----------v----------~
MC 1 0129's or TT L Gate Receivers
·Termlnatlon or Pull-Up ReSistors If Used

FIGURE 7 - MECL/TTL Bus Lme

The MECL bus dnver and receiver cncUlts can also be
used to build bus lInes In an all MECL system as shown
in Figure 8. The MClO128 bus dnver IS specified driVIng
50 ohms to ground or 25 ohms to +1.5 Vdc A 100 ohm
bus would be termInated by a 100 ohm resistor to ground
at each end, or a 50 n bus by 50 ohm resistors to + I 5
Vdc at each end. An alternate to the +1.5 V supply IS a
resistor eqUIvalent of 68 n to ground and 160 n to
+5 V dc. The termInated bus allows high speed data transfer
because It is not necessary to allow time for reflectIOns
on the line to settle out. Normally a TTL output is not
able to dnve a bus tenmnated as shown In Figure 8.

INTERFACING WITH IBM BUS LEVELS
High speed MECL systems, such as add-on memones or
disk storage controllers, are often required to interface
with IBM compatible 1I1put/output bus logiC levels The
MCIOl28 Bus Driver and MCI 0129 Bus Receiver, Figure 4,
are deSigned to meet IBM System 360 and System 370
I/O interface requirements. These circuits, descnbed 111 an
earlier s~ction, interface directly with MECL lOKI IOKH and
MECL III logic levels.
In the IBM mode of operation the MC I 0128 driver
meets the following guaranteed specificatIOns: The low
level output Will not exceed +0.15 volt or go below -0.5
volt wlule sourcing 240 J1.A current. The high level output
will not be below 3.11 volts with an output load of 53.9
mA or exceed 5.85 volts with an output load of 30 J1.A.
The circuits are tested aga1l1st damage from an output
shorted to ground and are speCified for a maxllnum short
CIfCUit output current of 320 mAo
Test1l1g has shown that the MC 10 128 bus dnver also
meets the follow1l1g IBM interface requirements. A 7 volt
output IS the maximum permitted With a supply overvoltage on the driver. This specification IS met because
+8 V dc (maximum recommended MECL overvoltage)
typically results in an output level less than +5.5 volts at
the speCified load of 123 mA. Testing has also shown that
the loss of either or both power supplies on the bus driver
will not cause a fault condition on the bus. Maximum load
current occurs with a positive supply shorted to ground

MECL Input MC10128 Bus Drivers

MECL Output MC10129 Bus ReceIVers
RT Termination ReSistors = Line Impedance Zo
Terminated to Ground or + 1 5 Vdc

FIGURE 8 - MECL System Bus Lme

211

+5 Vdc
+5 Vdc

+5 Vdc

180

MECL

270

TTL

820

9a

9c

9b

FIGURE 9 - Common Supply ECl/TTL Interface Circuits

and this IS typically less than 4 mA with +6 volts on the
bus lIne or less than I mA with 5 volts or less on the bus.
The MCI 0129 bus receiver IS designed to translate IBM
compatible bus lInes to MECL logic levels. The lugh and
low input logic level threshold POll1ts are speclfJed at + 1.7
volts and +0.7 volt to give IBM specified nOise margins.
The mput current requirements for the MCIOl29 are well
below IBM maXIlllum specificatIOns. At a high input level
of 3 .11 volts the MC I 0129 lI1put current is less than 95 J.1A
and the low level input current at 0.15 volt is not below
-1.0 J.1A ThiS compares with 420 J.1A and -240 J.1A for the
IBM specificatIOns
Testing has shown compahbilIty with most other IBM
specification requHements. The cirCUit will withstand 7
volts on the bus input with power applied, although input
current may be as high as 30 mA with a 7 volt input. The
MC 10 129 has no problem meetll1g the -0.15 volt on the
input either power up or power down. IBM's requHement
of 6 volts on the receiver input with no power on the
MC 10 129 IS not met If the VCC lIne on the receiver is
shorted to ground With the posItive supply open, the
6 volt requHement IS met, but input current can exceed
25 mAo This specificatIOn may be met by using a senes
reSIStor of 510 to 1000 ohms between the bus hne and
the receiver input. This itmits current into the Ime receiver
during a power down condi tion. Another I BM specificatIOn
not directly met is the input impedance requirement of
greater than 4 k ohms and less than 20 k ohms. Typical
mput impedance of the MC 10129 IS approximately 50
k ohms with a rugh level of 3.11 volts on the bus. If thiS
mterface requirement is necessary, a 20 k ohm resistor
between the MCI0129mput and ground provides an input
impedance wltrun specified hmits.
The MCI0128 and MCIOl29 bus dnvers and receivers
give the MECL system designer the capabihty to mterface
with the input/output requirements of many system types.
In addition these parts can be used for bus lines inter·
connecting sections of large MECL systems.

INTERFACING WITH ECLOPERATING AT NON·MECL
POWER SUPPLY VOLTAGES
MECL circuits are sometUl1es required to interface with
ECL systems operatll1g at power supply voltages that
differ from the standard MECL ground and -5 2 volts
These cirCUits commonly use ground for a bias reference
voltage, resultlllg III a logic swing centered around ground.
This signal can be converted to and from MECL lOKI 10K H
logic levels with MECL line receivers and proper use of
available power supplies.
MECL Signals can be shifted more positive as shown
in Figure lOa. The fmt hne receiver stage generates comphmentary signals and is unnecessary when MECL com pl!.
mentary Signals are available at the lI1put. The second
Ime receiver is powered by the MECL -5 2 volts on VEE
and the + 1.3 volts on VCC from other ECL ClfCUltS
The complimentary outputs from the first stage present a
differential Signal to the second stage wlthll1 the common
mode range of the CIfCUIt. The Ime receiver domg the
translating operates at a total supply voltage of 6.5 volts,
which IS no problem for a low power lIne receiver CIfCUlt
such as the MCI0116j MCIOH 116.
The CIfCUIt III Figure lOb may be used to translate
down to MECL mput reqUirements A Ime receiver con·
nected to + 1.3 volts and -5.2 volts is used to generate
complementary outputs and amphfy the Signal prior to
usmg a voltage divider to the second stage. Due to the
differential operatIOn of the MC 10 116 line receiver, the
+ 1.3 volt supply is not cnhcal and any value between
+ 1.0 and + 1.5 volts IS acceptable. With the power on the
ClfCUlt elevated to 6.5 volts, typical output swmg is greater
than 900 mV. The resistor divider network shifts the
Signals to MECL levels as requtred by the second Ime
receiver stage. This stage, operating at normal MECL power
supply levels, delivers normal MECL output signals. The
usc of differential Signals is recommended in the voltage
dropping network as this elimmates the need for cntlcal

212

....~-

.....-o~

}

±400 mV
Around
Ground

±400 mV

150

MECL

./1J-~J--+- } 0 utp ut
470

470

-52 V

-52 V

-52V--__~--~~--~--~

lOa
'Termination or Pulldown ResIStors to Appropriate
Supply Voltage

lOb

FIGURE 10 - Interfacing with Non-MECL Compatible EeL Using MC10116's

resistor values, and eases thermal or power supply tolerance
design restrictions. The two stage Interface circuit total
delay is typically 5 ns including wirIng and the resistor
dividers. (The MC 10 116 has a typIcal propagation delay
of 2 ns per stage.)

The MOS to MECL Interface cucuit In FIgure II uses a
Ime receiver to perform the translation. The line receIver
offers advantages over a basic MECL gate since the reference voltage can be made more negative WIth the
resistor dIvider, and the receiver mput is a lIghter load for
a P-MOS output due to the absence of Internal pulldown
resistors. The 4.7 k resistor IS used to limit input current
when the MECL mput clamps at about -6 volts m the
negative dlfection.
Modern N-channel circuits are commonly TTL compatIble, and CMOS at +5 volts operates WIth TTL logIC levels.
The MECL/TTL translators (MCIOI24 and MCl0l25) or
the MECL bus circuIts (MCIOI28 and MCIOI29) desCflbed
earher perform these mterface requuements The MC 10 129
bus receIver IS especIally useful as a MOS to MECL translator because the low mput current requIrements of the
MC10129 (typically 60 pA at 3 volts) does not load the
MOS CIrcuits as would a normal TTL circuit mput
This availability of mterface cirCUIts allows the designer
to take advantage of both MECL performance, and the
low power and lugh Clfcuit density of MOS for the slower
sectIOns of a system.

Another cIrcuIt that can be used to translate a sIgnal
SWing around ground to MECL logic levels is the MC1650.
This MECL III part is a hIgh speed dual A/D comparator
whIch IS ideal for this interface, but designers should
consider the cost and capability of the MC 1650 against
system requirements to determme the best Interface cIrcuit.
MECL/MOS INTERFACE CIRCUITS
The MECL/MOS Interface varies WIth the type of MOS
and the MOS power supply voltages. For P-channel MOS
CIrcuits operatmg between ground and a negative voltage,
the cncUIts shown In FIgure II may be used The dIOde
111 the MECL to PMOS translator biases the PNP transistor
off and on WIth MECL logIC levels, as the transistor
amplIfies the MECL logIC swing to the large P-channel
MOS requirements.
MSD6100

LOW LEVEL SIGNALS TO MECL
The differential amplifier operation of MECL line receIvers permits these circuits to amplify low level signals
to MECL logic levels. The circuit in FIgure 12 is a typical
amplifier design wluch uses the MC101l6 line receIver to
receIve signals as low as 50 m V and gIve good MECL
outputs. ThiS design features two 100 ohm resIstors In
parallel for a 50 ohm input impedance to AC SIgnals. The
resistor values can be adjusted to terminate other wire
impedances_ Capacitor couplIng IS recommended for operatIOn with signals that do not swmg around a center
pomt equal to the VBB reference voltage_

To P-MOS CirCUit

510
10 k

-52 V

ECL to P-MOS

-V

1 k

-=

47k
P-MOS Input

1/4 MC10115

1 k
-52 V

P-MOS TO MECL

FIGURE 11 - MECL/P-channel MOS Interface Circuits

213

0.001

Input
>50
mV

MC10116

~

Input

100
0001
510

510

-VI---*--t
0001

V BB

·Pulldown or Termination ReSistor

700

FIGURE 12 - Low Level Amplifier USing a MECL Line Receiver

III111

600
R'f.

Rt"rOr

=

24

500

.s

400

J

51 n
100 !l
20051

~

~
~

Vi

300

1:

100

I.-'

V
J

V

1I

1/

V 1/
IJ

IJ

/1/
II 1I

~

1/

10-

~~I.-

VI V ~ ~
P' V V-

V~
200

n" V

V V1/ ~

;;-

The maximum bandwidth of the amplifier depends on the
MECL line receiver part type as shown in the circuit gain versus
operating frequency curves in Figure 13. The lowest frequency
part that meets system requirements should be selected to lower
component cost and ease of design rules. For example, the
MC1692 should be limited to two cascaded stages and short
interconnection lines to insure circuit stability. Also, the MC1692
is more stable in the stud "S" package than the dual in-line "L"
package when used as an amplifier. Cascading three or more
stages is possible with the slower MClOl16 or MClOl15 line
receiver circuits. Any offset will lower overall gain.

~ .....

~I-'

~e~d~~d~ II

1/

i- 510 51
IOU!
:- 2 a kf!

1,1

V l/~ ~ ~ l/I-'~
~

~

0
10

50

20

100

200

500 10k 2 0 k

5 0 k 10k

Rb' alas ReSistor (Ohms)

FIGURE 14 - MECL Schmitt Trigger and HysteresIs Curves

20
18
16
14

iIi 12

.

E

CI

Vi'"

10

----

------

f...........
-..;::

...............

~80

...........

I~~......

I"-

t:)

60

r--r--...

" ~r.........

------

/"'"",

" " "'~
"
......

MC10 115
,

/~

o
10

20

30

50

70

200

100

Frequency (MHz)

''\

I

........... MC1692-

MC10114/ ' "

20

...........

MC10216

~

'"

A,

r\

300

600

FIGURE 13 - Gain versus Frequency for MECL Line Receivers

MECL line receIVer circuits can also be connected as
Schmitt triggers to shape low frequency sIgnals to MECL
rise and fall times. An MCIOI16 connected as a Schmitt
trigger is Illustrated in Figure 14. The table in the fIgure
shows the amount of hysteresis as a function of the feedback resistors. For low frequency signals below I kHz at
least I SO mV of hysteresis should be used to Insure the
circuit does not momentarily oscIllate during the output transition.

When connectmg a line receiver as a Schmitt trigger it
IS important that the feedback resistors be connected to
an inverting output from the input sIgnal. If trus is not
followed, the performance of the Input Signal will be
degraded because of nega tive, Instead of posItive, feedback.
When the SchmItt trigger must also handle higher frequenclCs it IS necessary to restrict the values of the feedback resIstors Above SO MHz the resistors should be
limited to 200 ohms or less, so stray capacitance does not

214

tance, typically 150 pF, slows the MECL nse and fall
times which can cause timing problems, and the diode
forward voltage may be small enough to clamp a MECL
low level output above ECL Input requirements.
MECL lOKI IOKH and MECL III circuits are specified
driving 50 ohm loads to -2.0 Vdc, whIch represents a
typical output current of 22 rnA for a high output.
Designing with this lImit, resistors as low as 200 ohms to
-5.2 volts can be used In series with the LED. When the
MECL circuit IS in the low logic state, a 1.6 volt drop
across the LED gives a dIOde current of 18 rnA. Larger
resistor values are used when less diode current IS deSIred.

slow the feedback path causing serious phase shift between
the two Inputs of the line receiver. Use of a Schmitt
trigger is discouraged at high frequencIes because feedback
phase shift makes bandWidth less than that of a straight
line receiver amplifier. However, the combination of a
MECL amplIfier, Figure 12, followed by a MECL Schmitt
trigger, Figure 14, gives a versatile buffer ClfCUit for many
input requlfements witiun the frequency limits of the
Schmitt tngger.
The MC 1650 AID comparator, Figure 15, also provides
a good interface between low level signals and MECL. ThiS
cirCUit features 3 /lA Input current, 20 mV bUilt In
hysteresis, 5 mV offset voltage, and an mternallatch. The
MC 1650 interfaces With a wide range of signal.types Since
this part has a plus or minus 2.5 volt common mode range.

VIn01(6)6~
D
0
2
v 1n02

(2) 00

(5) 5

CO (4) 4

c

0

3 (3) 00

m11
10
V
(12)
= t J = 0 12(14)01
V ln 12 (11) 9

C1

(13)

1

C

Q

13(15)01

Number at end of termInals denotes pIn number for S package (Case 617).
Number In parenthesIs denotes pIn number for L package (Case 620).

FIGURE 15 - MC1650 Dual AID Comparator

INTERFACING WITH LIGHT EMITTING DIODES
Light emitting diodes are used with MECL IOK/lOKH
and MECL III for both data display and troubleshooting.
When mOnitoring a MECL output for troubleshooting, the
diode is connected between the output and VCC as shown
In Figure 16. With a tYPiCal MECL low output level of
-1.7 volts, and a LED forward conduction of 1.6 volts,
the diode lIghts. The high MECL level (typically -0.9 volts)
IS insufficient forward voltage for the diode to conduct.
The use of standard MECL circuits to drive LEDs is
normally limited to system testing or low volume deSigns
because the circuit is not guaranteed worst case. (Worst
case MECL low level is -1.65 volts, and worst case diode
forward voltage is 1.8 volts at 20 rnA for a MLED 600.)
When LEDs are dnven from MECL for data display,
the MCI0123 bus driver should be used. This circuit has a
guaranteed low logic level output of -2.03 to -2.10 volts
and a worst case high level of -0.960 volt. These levels are
compatible With standard LED worst case requirements.
Generally, it IS not advisable to drive another MECL
circuit from an output dnvIng a LED. The diode capaci-

VCC

~

MLED600
or Equlv

//

200

VEE

FIGURE 16 - MECL DriVing a LED

215

BUSSING WITH MECL 10K/10KH
INTEGRATED CIRCUITS

about 2 pF. With packages soldered m and stray capacItance conSIdered, dlstnbuted capacItance averages about
5 pF per cIrcuIt connectIon.
Performance tests were made on a typical MECL bus
Ime as Illustrated 10 FIgure I. This Ime is a 75-ohm microstrip built on a 0.062 lOch double sided G-lO epoxy
cirCUIt board. Nme dnvers and nme receIvers are distributed along the 32-inch line at 4-mch mtervals.
A 50-ohm terminatIOn resistor is used at each end of
the line to mmlmlze reflections. Fanout along a SIgnal
Ime lowers the effectIve charactenstic Impedance by
the equatIOn.

INTRODUCTION
A bus lme IS designed to mterconnect several pomts m
a system wIth a common data path. Normally drivers and
receivers are located at each end of the lIne, so data can
flow in eIther dIrectIon AddItIonal drIvers and receIvers
often connect to the bus at varIOUS points along the line,
requirIng that the drIver be capable of sendmg a slgnal In
both directIOns. For thIs reason, a high speed bus drIver
must operate mto a load equal to one-half the line charactenstic Impedance. Only one drIver on a bus can send
data at any gIven time. If more than one MECL drIver
were sImultaneously transmittmg, any output at a hIgh
logIc state would predommate causmg i\ loss of data.
System busses utilize eIther a smgle ended or dIfferentIal operatmg mode. A dIfferentIal bus requIres two
wIres per sIgnal path and the receIver looks at the voltage
difference between the two lInes. The dIfferentIal lme
has nOIse immunIty advantages for longer bus runs, but
thIS approach is speed limIted when compared to a smgleended bus. A dlfferen tlal system requlfcs specIal drivers
and receivers whIch are usually slower than hIgh speed
logIC cirCUIts. Also, present approaches to dIfferentIal bus
driving sWItch only one line of the dIfferentIal paIr when
1I11tlalIzmg a data transfer. TIllS results 10 a crosstalk
condItion between the two lInes whIch may 11I11It maxImum speed.
The single-ended bus uses one wIre for each data path,
minImizmg wIre and interconnectIOn requIrements. The
SIgnal voltages on a smgle-ended bus are referenced to
some common voltage, usually ground, so standard 11Igh
speed MECL cIrcuIts functIon as both drIVers and receivers.
With the use of hIgh speed CIrCUIts as dnvers, performance
is largely determmed by the transmISSIOn Ime characterIStICS of the bus. TI1IS applIcatIOn note dIscusses the
transmIssion Ime parameters whIch should be conSIdered
in the deSIgn of a hIgh speed MECL smgle-ended bus Some
of these parameters include termmation, capacItIve loading,
stub lengths, and tlmmg considerations

where
Zo, the unloaded Ime Impedance = 75-ohms
CD, the total dIstributed capacItance = 5 pF per fanout
Co' the Ime intrinSIC capacItance per umt length = 24 pF
per foot for the 75-ohml11lcrostnp Ime
Q = length of Ime m mches.
Calculatlllg the characterIStIc Impedance of the bus Ime
III FIgure I gIves'
75
Z ,- ~====
a -~ 1 1 -90
--24 (2 67)

= 48 ohms

The two 50-ohm resIstors 10 parallel are a 25-ohm
load whIch IS beyond the speCIfIed 50-ohm dnve of a
standard MECL output. For thIS reason, MClO]]] triple
output gates are used as bus dnvers These gates have
three outputs, each capable of 50-ohm loads. ParallelIng
two outputs gIves the reqUIred 25-ohm drIve.
PropagatIOn delay tllne of the bus IS a functIOn of the
Ime type, length, and load. Unloaded mlcrostrip line has
a propagatIOn delay of 1.77 ns per foot for G-lO cirCUIt
board material with a dIelectric constant of 5.0. TIllS gIves
an unloaded propagatIOn delay tllne of (32 m -7- 12 m/ft)
X 1.77 ns/ft or 472 ns for the 32-mch bus Ime. The unloaded bus model measured 4.92 ns propagatIOn tIme.
The slIght mcrease from calculated tIme IS due to added
capacItance from the short stubs and dIfferences m the
dIelectrIC constant between the test board and the calculated 1.77 ns per foot

HIGH SPEED SINGLE-ENDED BUSSES
High speed smgle-ended busses commonly have a 11Igh
fanout density and use MECL CIrcuits as dnvers and
receivers. Fanout on a MECL bus IS not lImIted by dc
loadmg considerations, however, CIfCUlt mput and output
capacitance will slow ac performal1l:e. Input capacItance
of a MECL gate IS about 3 pF and output capacitance

216

A~------~~-------'--------~--------'-------~~------~--------~--------'

-20 V

-20 V

1. All DrJversareMC10111
2. All Receivers are MC10105
3 All Stub Lengths Less than 1/2 Inch
FIGURE 1 - MECL Bus Test Fixture

Propagation delay time of a loaded line may be
calculated from the followmg equation.
Point C

tpd'::: tpdJl + CD

Point A

CoQ

where tpd IS the unloaded Ime propagatIOn delay. The
bus line In Figure I loaded only with receivll1g gates has a
calculated delay of:
tpd'::: 4.92

tpd = 7.7 ns

/1 + __
4_5- ::: 6.42 ns
24 (2.67)

\jl

VOH ~-O.9 V

This compares with 6.62 ns for the tested bus Ime.
When the bus hne is loaded with both dnvers and
receivers, the lI1creased distributed capacitance slows the
calculated propagatIOn delay to 7.62 ns. Test waveforms
for the bus line m Figure I are shown III Figure 2.
Propagation delay for a lugh or low transition is 7.7 ns
and agrees with the calculated tllne. However, the low to
l1lgh delay is mcreased to 9.7 ns because of a step in the
risll1g edge of the waveform TIllS nsmg edge step IS due
to the output Impedance charactenstlcs of a MECL clfcuit.
When the bus hne IS at a low logic level, all dnver outputs
are sourcmg current to the termination resistors. These
MECL outputs appear as low (7 to ) 0 ohm) Impedances
along the Ime. A f1SlI1g sIgnal travelIng down the bus sees
these low Impedance outputs and reflects back to the
sendlOg pOint causing the rislIlg edge step. After the
signal rISes to a level where the nondnvlllg emItter
followers are no longer sourclllg current, these outputs
become high impedances and reflectIOns no longer occur.
The transition from 11Igh to low IS no problem because
only the active dnver IS sourcmg current and the other
CIfCUitS appear as hIgh Impedances along the hne.
In the precedll1g example, it was shown that fanout on
a bus will lower the charactenstJc Impedance of the lme.
ThIS should be taken mto consIderatIOn when determ1l1mg
termination resistor values. A low Impedance IlIle IS less
affected by Ioadmg than a hIgher Impedance lme. However, s1l1ce a bus line IS termll1ated at both ends, the
driver output current capabIlity must be conSidered as a
hmlt to millImum Ime Impedance.

VOL~-17V

tpd = 9.7 ns

POint A
POint C

VOH ~-O.9 V
VOL~-1.7

50 ns/cm

V

FIGURE 2 - Bus Waveforms With MC10111 Drivers

Standard MECL 10K circuits are specified driving a 50ohm load. This equates to a IOO-ohm bus line terminated at
each end. Therefore, when these circuits are used as drivers,
fanout density must be limited or the line will be overterminated (actual line Impedance less than 100 ohms) and
reflections will occur. For short bus lengths, typically less
than 12 inches, this is acceptable as reflections die out within a
few nanoseconds.
PropagatIOn delay mcrease with fanout must also be
conSidered when figunng bus line performance. Propagation delay IS least affected by low Impedance lInes
Therefore, It IS usually deSIrable to deSIgn long bus runs
with the lowest impedance lme that IS compatIble wIth
the dnver CIrCUItS.

217

For short bus lines the advantage of driving the bus
from any MECL circuit and not having special drIvers
overcomes any delay caused by high impedance lines.
With longer busses, the designer has the choice of using a
high impedance line with standard circuits or increasing
performance by going to a properly terminated lower Impedance line. Lower impedance lines require paralleling
MECL circuits for increased dnve or going to special
circuits within the family which have better than 50-ohm
drive. The recommended minimum bus line impedance IS
34 ohms (l7-ohm resistive load) which could be dnven
by MCI0llO or MClOlll circuits having all three outputs
wired together. The 50-ohms as in Figure 1 is a more
conservative limit.

MC10123 driven bus would have normal MECL levels with
no reflections. A second feature of the MC 10123 is the
25-ohm dove capability. Busses as low as 50 ohms can be
terminated at each end without having to use multiple
output driver circuits.
The MC10123 Bus Drivers were substituted for the
MClOlll's in Figure 1. The results of the MClO123 bus
are in the Figure 3 waveforms. When compared with
Figure 2. the step m the rismg edge is missing With the
associated improvement in propagation delay to 7.9 ns.
The oscilloscope photograph of the negative going
edge in Figure 3 shows some ringing due to reflections
at the driving end of the bus. This is because the dnver
goes below the termination voltage and becomes a high
impedance load. Therefore, any small reflectIOns are not
clamped by the low Impedance output as was the case in
Figure 2. This ringing IS not a problem and causes no loss
of noise margin because the low level output voltage of
the MCIOl23 bus in Figure 3 IS 300 mV more negative
than the normal MECL output.

Ideally. the loading on a bus line should be evenly
distributed along the line. With this type loading, the
impedance is constant along the line and reflections are
minimized. It is realized that in system design this IS not
always possible and care should be taken to aVOid lumping
too much capacitance at one point on a long line. For
example, if lump loading is held to less than 21 pF in a
7.7-inch length of 68-ohm microstrip line, reflections will
be less than 20% along the Ime. Additional information on
lump loading is available in Chapter 7. page 145. If the
loading is evenly distributed on the line. there is no
practicailimit to fanout density other than minimum line
impedance for the driver.

POint C
POint A

The low impedance outputs of standard MECL circUits
cause an impedance discontinuity on the line, and limit
rising edge performance of high speed busses. If the bus
hnes are less than 18 inches. the reflection-caused step in
the rising edge is largely tudden In the relatively slow
MECL 10K rise time and performance degradation is
minimal. However, for longer lines, this step in the rISing
edge will cause a slowing of data transfer which should be
considered in the deSign or a high speed bus system.

tpd

= 7.8

VOH
VOL

ns

~-O.9

= -2

V

0 V

t p d=7.9ns

THE MCI0123 FOR HIGH SPEED BUSSES
When using standard MECL IOK/IOKH circuits as
drivers,low impedance discontinuities on the bus line caused
a step in the waveform and limit the maximum performance
of long bus lines. If the unused outputs could be made to
have a high impedance in both the high and low logic
states. bus performance would be improved. Since MECL
busses are normally terminated with resistors to -2.0 volts,
a MECL low logic level below -2.0 volts would turn off
the emitter follower output.
The MC 10 123 is designed with a low logic level specified between -2.03 and -2.10 volts. Therefore, when the
bus is at a low level, the line is at the -2.0 terminatIOn
voltage and all drivers have a high output impedance. A
rising edge sees no reflections, so rise time is improved.
The primary difference in using the MC 10123 as a bus
driver is the bus logic levels of -2.0 and -0.9 volts instead
of the normal MECL levels of -1.7 and -0.9 volts.
Although not necessary or even recommended, the termination voltage could be raised to -1. 7 volts and the

Point A
POint C

VOH~-09V

VOL

= -2.0

50 ns/cm

V

FIGURE 3 - Bus Waveforms With MC10123 Dnvers

The advantages of a bus usmg MC 10123 dnvers become
more apparent when signals along the bus are exammed.
Figure 4 shows the waveforms for the bus in Figure 1
dnven at pOlOt A and the oscilloscope monitoring point
B. The large step in the rising edge of the MC1Oll1 driven
bus is completely eliminated in the MC 10 123 bus.
The MCIOl23 bus driver is recommended where maximum performance is required over lon p line lengths and
high fanout. This part minimizes reflections on the bus

218

lme and noticeably improves propagation delay time.
However, when maximum speed IS not requIred or lines
are kept short, usmg standard MECL circuIts as bus
drivers should not be dIsregarded as tillS minimizes part
count and still gives good system speed.

MC10111 Drivers

There IS no absolute 11I11It to the length of MECL bus
lines Lm.es of 25 feet and longer are possible If good
transmISSion hnes are used to restru.:t external nOl~C
couplIng. The delays of these long lInes wIll be signifIcant
and should be considered when calculatIl1g overall system performance.

Point A
Point 8

VOH ~-0.9 V
VOL~-1.7 V

The MCIOH330 SERIES OF 25

POint A

5

VOH ",=,-0.9 V

= -2.0

TRANSCEIVERS

The MCIOH330 series consists of three 25 ohm bus
transceiver parts. These devices drive and receive on a 25 ohm
line as well as provide useful logic functions. The MC IOH330
(Figure 5) is a quad bus driver/receiver with 2-to-1 output
multiplexers. The MClOH332 (Figure 6) is a dual bus
drIver/receiver with 4-to-1 output multiplexers. The
MCIOH334 (Figure 7) is a quad bus driver/receiver with
transmit and receiver latches.
This series of parts have receivers with 200 m V of
hysteresis on their bus inputs to insure proper operation with
a nOIsy bus. The outputs of these transceivers when low,
appear as a high impedance to the bus and thus eliminate
discontinuities in the characteristic Impedance of the bus.

POint B

VOL

n

a ns/cm

V

FIGURE 4 - Bus Waveforms at Midpoint

OE

~,

S

01----1

__________________________

~

veea;

Vec ;

Pin 24
Pin 1

VEE

Pin 12

Veea" Pin 13
Veea; Pln4
0,

)4..--------0 WBus
WI ~-------~-L-'
WlnGV,----------4-+----------+----~
XO 0 1 - - - - - - + - i - L . . - '

0,-----+-+---<-->

Xl

Xin

8'-----------+-+-----------+-------1

YO

~,-----------4-+~J

> + - - - - -......-+--@

YBus

}-------.-+-@

ZBus

YI

ZI@'--------------LJ
Z,n 15)----------------------------------4

ruE ~I--------------------~
MULTIPLEXER TRUTH TABLE
OE

S

WSUI

XBul

YS us

ZSus

H
L
L

X
L
H

-20V

-20 V

-2.0 V

-2.0 V

WO
WI

XO
Xl

YO
Yl

ZO
Zl

X - Don't care

FIGURE 5 - LOGIC DIAGRAM (MC10H330)

219

MULTIPLEXER TRUTH TABLE
OE

51

50

XBuI

YBuI

H

X

L

L

L

L
L
L

L
H
H

H

X

-2.0 V
XO
Xl
X2
X3

-20 V
VO
VI
V2
V3

L
H

x-

RECEIVER TRUTH
TABLE

Don't care

Vee = Pin 1
VCCOI - Pin 11
VCC02 - Pin 20
Vee - Pin 10

FIGURE 6 - LOGIC DIAGRAM (MC10H332)

@ee

o

OLE

~-+----_---o

BUSO

001

~------;O

o

~-+-----+-..---o

BUS'

0
0

@)

02

~------;O

o

r---+-----;-+-t---
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