1989_Motorola_Memory_Data 1989 Motorola Memory Data

User Manual: 1989_Motorola_Memory_Data
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Selector Guide and Cross Reference
MOS Dynamic RAMs

II
II

II
CMOS Fast Static RAMs II
Special Application MOS Static RAMs II
MOS EEPROM II
MECL Memories II
Military Products II
Reliability Information II
Applications Information II
General MOS Static RAMs

Mechanical Data
MOTOROLA MEMORY DATA

m

DATA CLASSIFICATION
Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of
the first page reads: "This document contains information on a product
under development. Motorola reserves the right to change or discontinue
this product without notice."

Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of
the first page reads: "This document contains information on a new product.
Specifications and information herein are subject to change without notice."

Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information on a product in full production. Guaranteed limits will not be changed
without written notice to your local Motorola Semiconductor Sales Office.

MOTOROLA
MEMORIES
Prepared by
Technical Information Center

Motorola has developed a broad range of reliable memories for virtually any digital
data processing system application. Complete specifications for the individual circuits
are provided in the form of data sheets. In addition, a selector guide is included to
simplify the task of choosing the best combination of circuits for optimum system
architecture.

New Motorola memories are being introduced continually. For the latest
releases, and additional technical information or pricing, contact your nearest
authorized Motorola distributor or Motorola sales office.

Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant
into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any
such intended end use whereupon Motorola shall determine availability and suitability of its
product or products for the use intended. Motorola and ® are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action
Employer.

Series F
©MOTOROLA INC., 1989
Previous Edition © 1988

"All Rights Reserved"

Printed in U.S.A.

iii

MOTOROLA MEMORY DATA
, iv

CONTENTS
Page
Alphanumeric Index ........................................................ viii

CHAPTER 1
Selector Guide. . . .. .. . . .. .. . . . .. . . . . . . .. . .. . .. ... .. . .. .. .. . . .. .. . . . . . .. .. 1-2
Cross Reference ......................................................... 1-5
CHAPTER 2-MOS DYNAMIC RAMs
MCM6256B
256Kx 1,100/120/150 ns, Page Mode, NMOS ................
MCM6257B
256Kx1, 100/120/150ns, Nibble Mode, NMOS ..............
MCM41464A
64K x 4, 10011201150 ns, Page Mode, NMOS .................
MCM511000A, 1M x 1, 70/80/100 ns, Page Mode, CMOS ...................
MCM51 L1000A 1M x 1, 70/80/100 ns, Page Mode, CMOS, Lower Power ......
MCM511001A 1M x 1, 70/80/100 ns, Nibble Mode, CMOS ..................
MCM511002A 1M x 1, 70/80/100 ns, Static Column, CMOS .................
MCM514256A, 256Kx4, 70/80/100 ns, Fast Page Mode, CMOS ............ , ~
MCM51L4256A256Kx4, 70/80/100 ns, Fast Page Mode, CMOS, Lower Power
MCM514258A 256Kx4, 70/80/100 ns, Static Column, CIVIOS ............•..
MCMS1000
1M x S DRAM Module, 80/100 ns, Fast Page Mode, CMOS ....
MCM91000
1Mx9 DRAM Module, 80/100 ns, Fast Page Mode, CMOS ....
CHAPTER 3-GENERAL MOS STATIC RAMs
MCM201SA
2K x S, 35/45 ns, NMOS ...................................
SKxS; 100/120 ns, CMOS .........•.•..•.....•....•.......
MCM6064,
MCM60L64
SK x S, 1001120 ns, CMOS, Lower Power ....................
MCM60256,
32KxS, 85/100/120 ns, CMOS .............................
MCM60L256 32KxS, 85/100/120 ns, CMOS, Lower Power ................
MCM60256APC 32K x S, 100 ns, CMOS, Industrial Temperature Range .........
CHAPTER 4-CMOS FAST STATIC RAMs
MCM1423
4K x 4, 40 ns, Equivalent to IMS1423 ........................
SK x S, 45/55 ns, El, E2, and G Inputs. . . . . . . . . . . . . . . . . . . . • ..
MCM6164,
MCM61L64
SKxS, 45/55 ns, Lower Power ........•....................
MCM6164C
SKxS, 55/70 ns, -40 to 85°C ..............................
MCM6168
4K x 4, 45/55170 ns .....................•..•..•...........
MCM6205-2O
32K x 9, 20/25 ns, Output Enable ...........................
MCM6206
32K x S, 35/45 ns, Output Enable ...........................
MCM6206-2O
32K x S, 20/25 ns, Output Enable ...........................
MCM6207
256K x 1, 20/25 ns, Separate Input and Output Pins .•.........
MCM6208
64K x 4, 20/25 ns .........................................
MCM6209
64K x 4, 20/25 ns, Output Enable ...............•...........
MCM6226-3O
128KxS, 30 ns, Output Enable ...........•.•.........•.....
MCM6228-25
256K x 4, 25 ns, Output Enable ...........•..•..............

MOTOROLA MEMORY DATA
v

2-3
2-15
2-27
2-39
2-39
2-54
2-69
2-84
2-84
2-99
2-114
2-116

3-3
~S

3-S
3-14
3-14
3-22

4-3
4-S
4-S
4-16
4-24
4-29
4-30

4-35
4-36
4-41
4-41

4-46
4-47

CONTENTS (Continued)
Page
MCM6264
MCM6264-25
MCM6268
MCM6268-20
MCM6269
MCM6270
MCM6287
MCM6287-15
MCM6287-20
MCM6288
MCM6288-15
MCM6288-20
MCM6290
MCM6290-15
MCM6290-20

8Kx8, 30/35/45/55 ns, Output Enable ......................
8K x 8, 25 ns, Output Enable ...............................
4Kx4, 25/35/45/55 ns ....................................
4Kx4, 20 ns ........•....................................
4K x 4, 25/35 ns, Fast Chip Select .. .. .. .. .. .. .. .. .. .. .. .. ...
4K x 4, 20/25/35 ns, Output Enable ............... ,.........
64Kx 1,25/35 ns, Separate Input and Output Pins ....•..• : ...
64K x 1, 15 ns, Separate Input and Output Pins ...............
64K x 1,20 ns, Separate Input and Output Pins ..........•....
16Kx4, 25/30/35/45 ns ...................................
16K x 4, 15 ns ....................................•.......
16K x 4, 20 ns ............................................
16Kx4, 25/30/39/45 ns, Output Enable .....................
16K x 4, 15 ns, Output Enable ..............................
16K x 4, 20 ns, Output Enable ..............................

4-48
4-53
4-58
4-63
4-58

4-68
4-73
4-81
4-81
4-86
4-91
4-96

4-86
4-91
4-96

CHAPTER 5-SPECIAL APPLICATION MOS STATJC RAMs
MCM68HC34
Dual-Port RAM ~ .............. '................•........' . •. 5-3
MC1VI4180
4Kx4, 22/25/30 ns, Cache Tag ............................. 5-11
MCM4180-20
4Kx4,20ns, Cache Tag ................................... 5-18
MCM6292
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs ...... 5-25
MCM6293
16K x 4, 20/25/30 ns, Synchronous, Output Registers ..•...... 5-33
MCM6294
16K x 4, 20/25/30 ns, Synchr,onous, Output Registers and Output
Enable .,., ............•........ , ...... '............. ,..... 5-41
MCM6295
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs and
Output Enable ..........•...............•. ,.............,5-49
MCM62350
4K x 4, 22/25/30 ns, Cache Tag .................•.......... 5-57
MCM62350-20 4K x 4, 20 ns, Cache Tag .................... . . . . . .. . . .. . ... 5-67
MCM62351
4K x 4, 22/25/30 ns, Cache Tag ............ :................ 5-n
MCM62351-20 4Kx4, 20 ns, Cache Tag, .........,..................•...... 5-87
MCM62963
4K x 10, 20/2J;/30 ns, Synchronous, Output Registers ......... 5-97
MCM62964
4K x 10, 20/25/30 ns, Synchronous, Output Registers and Output
Enable ..... '," ......................................... 5-102
MCM62965
4K x 10, 25/30/35 ns, Synchronous, Transparent Outputs and
Output Enable ......................... :; ............... 5-106
4Kx 12,20/25/30 ns, Synchronous, Output Registers ......... 5-110
MCM62973
4K x 12, 20/25/30 ns, Synchronous, Output Registers and Output
MCM62974
Enable .................... ~' ............................ 5-115
MCM62975
4K x 12, 25/30/35 ns, Synchronous, Transparent Outputs and,
Output Enable .............•....................., ....... 5-119
CHAPTER 6- MOS EEPROM
MCM2814
256 x 8 .... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .. 6-3

MOTOROLA MEMORY DATA
vi

CONTENTS (Continued)
Page
CHAPTER 7-MECL MEMORIES
MC10H145
16 x 4 Register File, 6 ns ...................................
MC10H155
8 x 2 Content Addressable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MCM10139
32x8 PROM, 20 ns .......................................
MCM10143
8x2 Multiport Register File, 15.3 ns .........................
MCM10144
256 x 1 RAM, 26 ns .......................................
MCM10145
16x4 Register File, 15 ns ..................................
MCM10146
1024 x 1 RAM, 29 ns ......................................
MCM10147
128 x 1 RAM, 15 ns .......................................
MCM10148
64x 1 RAM, 15 ns ........................................
MCM10149*10 256 x 4 PROM, 10 ns ...................................•..
MCM10149*25 256 x 4 PROM, 25 ns ......................................
MCM10152
256 x 1 RAM, 15 ns .......................................

7-3
7-6
7-11
7-16
7-20
7-24
7-18
7-32
7-36
7-38
7-42
7-45

CHAPTER 8-MILITARY CMOS PRODUCTS
Military 4180
4K x 4 CMOS Cache Tag, 35/45 ns ..........................
Military 6164
8K x 8 CMOS SRAM, 55/70 ns .............................
4Kx4 CMOS SRAM, 55/70 ns .............................
Military 6168
Military 6206
32Kx8 CMOS SRAM, 45/55/70/100 ns ....................•
Military6268
4Kx4 CMOS SRAM, 35/45 ns ....•........................
Military 6287
64K x 1 CMOS SRAM, 35/45 ns ............................
Military 6288
16Kx4 CMOS SRAM, 35/45 ns ............................
Military 93415 1024 x 1 TTL RAM, 60 ns, Open Collector ...•................
Military 93422, 256 x 4 TTL RAM, 60 ns ...................................
93L422,
256x4 TTL RAM, 75ns ...................................
93L422A
256 x 4 TTL RAM, 55 ns ...................................
Military 93425 1024 x 1 TTL RAM, 60 ns ................... , .•.......... ;.

8-3
8-5
8-10
8-15
8-17
8-22
8-27
8-32
8-36
8-36
8-36
8-41

CHAPTER 9-RELIABILITY INFORMATION ................................ 9-1
CHAPTER 10-APPLICATIONS INFORMATION
DRAMs
DRAM Refresh Modes (AN987) ...............•........................
Page, Nibble, and Static Column Modes: High-Speed, Serial-Access Options
on 1M-Bit+ DRAMs (AN986) ........................................
Fast Static RAMs
Avoiding Bus Contention in Fast Access RAM Designs (AN971) .... . . . . . . ..
Avoiding Data Errors with Fast Static RAMs (AN973) .....................
Special Application Static RAMs
25 MHz Logical Cache for an MC68020 (AN984) .........................
Designing a Cache for a Fast Processor (AR270) .........................
Enhancing System Performance Using Synchronous SRAMs (AR260) ......
High Frequency System Operation Using Synchronous SRAMs (AR258) ....
Motorola's Radical SRAM Design Speeds Systems 40% (AR256) ..........

10-2
10-4
10-8
10-12
10-15
10-29
10-35
10-39
10-46

CHAPTER 11-MECHANICAL DATA
Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . .. 11-2
Tape and Reel Data for Surface Mount Devices .......................... 11-21

MOTOROLA MEMORY DATA
vii

ALPHANUMERIC INDEX
Device
Number
MC10Hl45
MC10Hl55
MCM10139
MCM10143
MCM10144
'MCM10145
MCM10146
MCM10147
MCM10148
MCM10149*10
MCM10149*25
MCM10152
MCM1423
MCM2018A
MCM2814
MCM41464A
MCM4180
MCM4180-20
MCM51 L l000A
MCM511000A
MCM511001A
MCM511002A
MCM51 L4256A
MCM514256A
MCM514258A
MCM60L64
MCM6064
MCM60L256
MCM60256
MCM60256APC
MCM61L64
MCM6164
MCM6164C
MCM6168
MCM6205-20
, MCM6206
MCM6206-20
MCM6207
MCM6208
,MCM6209
MCM6226-30
MCM6228-25

Function

, Page
Number

16 x 4 Register File, 6 ns ................................ .
7-3
8 x 2 Content Addressable .............................. .
7-6
32x8 PROM, 20 ns ................................. .' .. . 7-11
8x2 Multiport Register File, 15.3 ns ... : .......•.......... 7-16
256 x 1 RAM, 26 ns ........................ ; ........... . 7-20
16 x 4 Register File, 15 ns ............................... . 7-24
1024 x 1 RAM,29 ns .................. '................. . 7.18
128x 1 RAM, 15 ns .................................... . 7-32
64x1 RAM, 15ns ...... :' ................. : ............ . 7-36
256x4 PROM, 10 ns .............. , ..................... . 7-38
256 x 4 PROM, 25 ns .."................ .' ................. . 7-42
7-45
256 x 1 RAM, 15 ns ................................. ;:' ..
4K x 4, 40 ns, Equivalent to IMS1423 .........•............
4-3
2Kx8, 35/45 ns, NMOS ..... ,•..............•........ : ...
3-3
6-3
256x8 .............................•...•..............
64K x 4, 100/120/150 ns, Page Mode, NMOS ............. . 2-27
4K x 4, 22/25/30 ns, Cache Tag .............. : .......... . 5-11
4K x 4, 20 ns, Cache Tag ................................ . 5-18
1M xl, 70/80/100 ns, Page Mode, CMOS, Lower Power ... . 2-39
1M x 1, 70/80/100 ns, Page Mode, 'CMOS ................ . 2-39
1M xl, 70/80/100 ns, Nibble Mode, CMOS ............... . 2-54
1M xl, 70/80/100 ns, Static Column, CMOS ............. . 2-69
256Kx4, 70/80/100 ns, Fast Page Mode, CMOS, Lower
Power .............................................. . 2-84
256K x 4, 70/80/100 ns, Fast Page Mode,' CMOS .......... . 2-84
256K x 4, 70/80/100 ns, Static Column, CMOS .....•....... 2-99
8K x 8, 100/120 ns, CMOS, Lower Power ............. : ... .
3-8
8Kx8, 100/120 ns, CMOS ..........................•....
3-8
32Kx8, 85/100/120 ns, CMOS, Lower Power ............. . 3-14
32Kx8, 85/100/120 ns, CMOS ...................•....... 3-14
32K x 8, 100 ns~ CMOS, Industrial Temperature Range ..... . 3-22
8K x 8, 45/55 ns, Lower Power .... ; ................... ; ..
4-8
8K x 8, 45/55 ns, El, E2, and G Inputs ................•...
4-8
8K x 8, 55/70 ns, -40 to 85°C ........................... . 4-16
4K x 4, 45/55/70 ns , ......•.•.............. , ........... .
4-24
32K x 9, 20/25 ns, Output Enable ..... ; .................. . 4-29
32K x 8, 35/45 ns, Output Enable ..... ; ...•..•............ 4-30
32K x 8,20/25 ns, Output Enable ........................ . '4-35
256K xl, 20/25 ns, Separate Input and Output Pins ........ . 4-36
64Kx4, 20/25 ns .............. ; ..... '.... : ......... '.•...
4-41
64K x 4, 20/25 ns, Output Enable ........................ . 4-41
128K x 8, 30 ns, Output Enable ...................... ~ ... . 4-46
256K x 4, 25 ns, Output Enable ..............•....•....... 4-47

MOTOROLA MEMORY DATA
viii

ALPHANUMERIC INDEX (Continued)
Device
Number
MCM62350-2O
MCM62351
MCM62351-20
MCM6256B
MCM6257B
MCM6264
MCM6264-25
MCM6268
MCM6268-2O
MCM6269
MCM6270
MCM6287
MCM6287-15
MCM6287-2O
MCM6288
MCM6288-15
MCM6288-2O
MCM6290
MCM6290-15
MCM6290-20
MCM6292
MCM6293
MCM6294

Function

MCM68HC34
MCM81000
MCM91000

4K x 4, 20 ns, Cache Tag ............................... .
4K x 4, 22/25/30 ns, Cache Tag .......•..................
4K x 4, 20 ns, Cache Tag ............................... .
256Kx1,100/120/150 ns, Page Mode, NMOS ............ .
256Kx 1,100/120/150 ns, Nibble Mode, NMOS ........... .
8K x 8, 30/35145/55 ns, Output Enable ................... .
8K x 8, 25 ns, Output Enable ............................ .
4Kx4, 25/35/45155 ns ................................. .
4Kx4, 20 ns .......................................... .
4K x 4, 25/35 ns, Fast Chip Select ....................... .
4K x 4, 20/25/35 ns, Output Enable ....•..•...............
64K x 1, 25/35 ns, Separate Input and Output Pins ......... .
64K x 1, 15 ns, Separate Input and Output Pins ............ .
64K x 1, 20 ns, Separate Input and Output Pins ............ .
16Kx4, 25/30/35/45 ns ................................ .
16Kx4, 15 ns ......................................... .
16Kx4,2Ons ...... .' .................................. .
16K x 4,25/30/35/45 ns, Output Enable .........•.........
16Kx4, 15 ns, Output Enable ........................... .
16K x 4, 20 ns, Output Enable ........................... .
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs ... .
16K x 4, 20125/30 ns, Synchronous, Output Registers ...... .
16K x 4, 20/25130 ns, Synchronous, Output Registers and
Output Enable ....................................... .
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs and
Output Enable ....................................... .
4K x 4, 22/25/30 ns, Cache Tag ......................... .
4K x 4, 20 ns, Cache Tag ............................... .
4K x 4, 22/25/30 ns, Cache Tag ......................... .
4K x 4, 20 ns, Cache Tag ............................... .
4K x 10, 20/25/30 ns, Synchronous, Output Registers ...... .
4K x 10, 20125/30 ns, Synchronous, Output Registers and
Output Enable .....•..................................
4K x 10, 25/30135 ns, Synchronous, Transparent Outputs and
Output Enable ....................................... .
4K x 12, 20/25/30 ns, Synchronous, Output Registers ...... .
4K x 12, 20/25/30 ns, Synchronous, Output Registers and
Output Enable ........•.•.............................
4K x 12, 25/30/35 ns, Synchronous, Transparent Outputs and
Output Enable ..............................•.........
Dual-Port RAM ........................................ .
1Mx8 DRAM Module, 80/100 ns, Fast Page Mode, CMOS ..
1M x9 DRAM Module, 80/100 ns, Fast Page Mode, CMOS ..

Military 4180
Military 6164
Military 6168
Military 6206

4K x 4 CMOS Cache Tag, 35/45 ns ...................... .
8K x 8 CMOS SRAM, 55/70 ns .......................... .
4K x 4 CMOS SRAM, 55/70 ns .......................... .
32K x 8 CMOS SRAM, 45/55/701100 ns .................. .

MCM6295
MCM62350
MCM62350-2O
MCM62351
MCM62351-20
MCM62963
MCM62964
MCM62965
MCM62973
MCM62974
MCM62975

MOTOROLA MEMORY DATA
ix

Page
Number
5-67

5-n
5-87
2-3
2-15

4-48
4-53
4-58
4-63
4-58
4-68
4-73
4-81
4-81
4-86
4-91
4-96

4-86
4-91
4-96
5-25

5-33

5-41
5-49
5-57
5-67

5-n
5-87
5-97
5-102
5-106
5-110
5-115
5-119
5-3
2-114
2-116

8-3
8-5
8-10
8-15

ALPHANUMERIC INDEX (Continued)
Device
Number
Military 6268
Military 62Ifl
Military 6288
Military 93415
Military 93422,
93L422,
93L422A
Military 93425

Function

Page
Number

4Kx4 CMOS SRAM, 35/45 ns ........................... 8-17
64Kx 1 CMOS SRAM, 35/45 ns •..•. : ............•........ 8-22
16Kx4 CMOS SRAM, 35/45 ns ... ~...................... 8-27
1024 x 1 TTL RAM, 60 ns, Open Collector ................. . 8-32
256 x4 TIL RAM, 60 ns . . . . • . . . . . . . . . . . . . . . . . . . . . . • . . . . . 8-36
256 x 4 TIL RAM; 15 ns .....•........................... 8-36
256 x 4 TIL RAM, 55 ns ................................. 8-36
1024 x 1 TIL RAM, 60 ns ................................ 8-41

MOTOROLA MEMORY DATA

x

Selector Guide and Cross Reference

Selector Guide. .. . . .. . . . . . . . .. . . . . . .. 1-2
Cross Reference ..................... 1-5

MOTOROLA MEMORY DATA
1-1

II

•

SELECTOR GUIDE
MOS/CMOS

CMOS Dynamic RAM Modules
(+ 5 V, 0

MaS/CMOS Dynamic RAMs
(+5 V, 0 to 70°C)
Organization
64Kx4

258Kxl

258Kx4

lMxl

Part Number

MCM41464AP10
MCM41464API2
MCM41484API5

(P)
(P)

Ace_Time
Ins maxi
100
~2O

I c.~

50

~oo

MCM6258BPI
MCM
MCM6257ifPl
MCM6257BPI2
MCM6257BPI5
MCM514258AP70
MCM514258APBO
MCM514258AP10
MCM514266AJ70
MCM514258AJ8O
MCM514258AJ10
MCM514258AZ70
MCM514258AZ80
MCM514258AZ10

MCM514258AP70
MCM514258APBO
MCM514258AP10
MCM514258AJ70
MCM514258AJBO
MCM514258AJ10
MCM514258AZ70
MCM514258AZ80
MCM514258AZ10
MCM511000AP70
MCM511000APBO
MCM511000AP10
MCM511000AJ70
MCM511000AJB0
MCM511000AJ10
MCM511000AZ70
MCM511000AZ80
MCM511000AZ10
MCM511oo1AP70
MCM511OO1APBO
MCM511oo1AP10
MCM511OO1AJ70
MCM511OO1AJ8O
MCM511OO1AJ10
MCM511OO1AZ70
MCM511oo1A280
MCM511oo1AZ10
MCM511002AP70
MCM511.002APBO
MCM511002AP10
MCM511002AJ70
MCM511002AJB0
MCM511002AJ10
MCM511002AZ70
MCM511002AZ80
MCM511002AZ10

IPI Page Mode
INI Nibble Mode
lSI Static Column

(P)

(N)
(N)
(N)
(PII
(PII
(PII
(PII
(PII
(Pit
(Pit
(PII
(PII
(S)
(S)
(S)
(S)
(S)
(S)
(S)
(S)
(S)
(PII
(PII
(PII
(PII
(Pit
IPII
IPII
IPII
IPII
IN)
IN)
IN)
IN)
IN)
IN)
IN)
IN)
IN)
IS)
IS)
IS)
IS)
IS)
IS)
IS)
IS)
IS)

to 70°C; 3O-Lead SIMM Package)

lMx8

MCM81000SBO
MCM81000s10

Ac_Tlme
Ins maxi
BO
100

lMx9

MCM91000SBO
MCM91000S10

100

Organization

120
150
100
120
150
70
80

100
70

Pins
18
18
18
16
16
16
16
16
16
20
20
20

100
70
80

80

100
70
BO
100
70
BO
100
70
BO
100
70

Organization
2Kx8

Organization

20
20
20
18
18
18

100
70
BO
100
70

8Kx8

20/26
20/26
20/26

80

100
70

20
20
20
18
18
18

80

100
70
80

100
70
BO
100
70
BO
100

MCM2018AN35
MCM2018AN45

Part Number

Pine
24

24

Pine

4Kx4

20/26
20/26
20/26

80

Ac_Tlme
Ins maxi
35
45

Part Number

(+ 5 V, 0 to 70°C unless otherwise noted)

20
20
20
18
18
18

100
70

30
30

80

CMOS Static RAMs

20/26
20/26
20/26

80

30
30

MaS Static RAMs

20
20
20
20
20
20

100
70

Pins

(+5 V, 0 to 70°C)

20/26
20/26
20/26

80

Part Number

20/26
20/26
20/26
20
20
20

MCM6268P20
MCM6268P25
MCM6268P35
MCM6268P45
MCM6268P56
MCM6269P25
MCM6269P35
MCM6270P20
MCM6270P25
MCM6270P35
MCM627OJ2O
MCM627OJ25
MCM627OJ35
MCM6064Pl0
MCM5084PI2
MCM60L84Pl0
MCMBOL64PI2
MCM6164C45
MCM6184C55
MCM61L64C45
MCM61L64C55
MCM6184CC55
MCM6184CC70
MCM62S4P25*
MCM6264P30
MCM6264P36
MCM6264P45
MCM6Z64P55
MCM6284J25*
MCM6284J30
MCM6264J35
MCM6284J45
MCM6284J55

20
20
20
20
20
20
20
20
20
20
20
20

(1)
(1)

20
25
35
20
25
35
100
120
100
120
45
55
45
55
(2)

55

(2)

70
25
30
35
45
55
25
30
35
35
55

22
22
22

24
24
24
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
26

(Continuedl

'Low power version avellable;

*To be introduced

order by MCM51 L•••

111 Fast chip eaIect -.Ion
121 Industrial temperatura range, -40 to 85"C

MOTOROLA MEMORY DATA
1-2

II

SELECTOR GUIDE (Continued)
CMOS Static RAMs (Continued)
Organization

Part Number

16Kx4

MCM6288PI5*
MCM6288P20*
MCM6288P25
MCM6288P30
MCM6288P35
MCM6288P45
MCM6290PI5* 131
MCM6290P20* 131
131
MCM6290P25
131
MCM6290P30
131
MCM6290P35
131
MCM6290P45
MCM629OJI5* 131
MCM629OJ2O* 131
131
MCM629OJ25
131
MCM629OJ30
131
MCM629OJ35
131
MCM6290J45
MCM6287PI5
MCM6287P20
MCM62S7P25
MCM62S7P35
MCM62S7JI5
MCM6287J2O
MCM62S7J25
MCM6287J35
MCM60256AP85
MCM60258AP10
MCM60256AP12
MCM60L256AP85
MCM60L256AP10
MCM60L256API2
MCM60256APC10 121

64Kxl

32KxS

32Kx9

64Kx4

256Kxl

128KxS
256Kx4

Synchronous Static RAMs

ACC11811 nme
(ns maxI
15
20
25
30
35
45
15
20
25
30
36
45
15
20
25
30
35
45
15
20
25
36
15
20
25
36
85
100
120
85

MCM6206P20*
MCM6206P25*
MCM6208P36*
MCM6208P45*
MCM6208J2O*
MCM6208J25*
MCM6208J35*
MCM6208J45*
MCM6205P20*
MCM6205P25*
MCM6205J2O*
MCM6205J25*
MCM6208P20"
MCM6208P25*
MCM6208J2O*
MCM6208J25*

100
120
100
20
25
36
45
20
25
36
45
20
25
20
25
20
25
20
25

MCM6209P20"
MCM6209P25*
MCM6209J2O*
MCM6209J25*
MCM6207P20*
MCM6207P25*
MCM6207J2O*
MCM6207J25*
MCM6226P30*
MCM6228J30*
MCM6228P25*
MCM6228J25*

20
25
20
25
20
25
20
25
30
30
25
25

(+5 V. 0 to 70°C unless otherwise noted)

Pins

Organization

22
22
22
22
22
22
24
24
24

16Kx4

24
24

24
24
24
24
24
24

24
22
22
22
22
24
24
24
24

4Kxl0

28
28
28
28
28
28
24

28
28
28
28
28
28
28
28

4Kx12

32
32

32

Part Number

MCM6292P25*
MCM6292P30*
MCM6292P35*
MCM6292J25*
MCM6292J30*
MCM6292J36*
MCM6293P20*
MCM6293P25*
MCM6293P30*
MCM6293J2O*
MCM6293J25*
MCM6293J30*
MCM6294P20*
MCM6294P25
MCM6294P30
MCM8294J2O*
MCM6294J25
MCM6294J30
MCM6295P25
MCM6295P30
MCM6295P35
MCM6295J25
MCM6295J30
MCM6295J36
MCM62963FN2O*
MCM62963FN25*
MCM62963FN30*
MCM62964FN20*
MCM62964FN25*
MCM62964FN30*
MCM62985FN25*
MCM62985FN30*
MCM62985FN35*
MCM62973FN20*
MCM62973FN25*
MCM62973FN30*
MCM62974FN20*
MCM62974FN25*
MCM62974FN30*
MCM62975FN25*
MCM62975FN30*
MCM62975FN36*

A_nme
Ins maxI
25
30
35
25
30
36
20
25
30
20

25
30
20
25
30
20
25

30
25
30
35
25
30
35
20
25
30
20
25
30
25
30
36
20
25
30
20
25
30
25
30
36

Pins
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44

32

24
24

CMOS Dual Port RAM

24

(+5 V. 0 to 70°C)

24
28
28
28
28
24
24

Organlzetlon

Part Number

256xS

MCM68HC34L
MCM68HC34P

CMOS EEPROMt

24
24

(+5 V. 0 to 70°C)

32
32

Part Number

MCM2814P

28
28

t Available in Europe only.

*To be introduced
(2) Industria) temperature range, - 40 to 85°C
(3) Output enable version

MOTOROLA MEMORY DATA
1-3

A_nme
Ins maxi
240
240

Pins
40
40

•

SELECTOR GUIDE (Continued)
MECL

Cache Tag RAMs
1+5 V, 0 to 70°C unless otherwise noted)
Organlatlon

Part Number

4Kx4

MCM62360P20*
MCM62360P22*
MCM62360P25
MCM62360P30
MCM6236OJ20*
MCM6236OJ22*
MCM6235OJ25
MCM6236OJ30
MCM62361P20*
MCM62361P22*
MCM62361P25
MCM62361P30
MCM62361J20*
MCM62361J22*
MCM62361J25
MCM62361J30
MCM4180P20*
MCM4180P22*
MCM4180P25
MCM4180P30
MCM518OJ20*
MCM418OJ22*
MCM418OJ25
MCM418OJ30

RAMs

Add .... to
Match Time
Inemaxl

10 to 75°C)

Pins

Organization

20
22
25
30
20
22
25
30
20

Part Number

24

24
24
24
24
24

8x2
l.,x4
16x4
84xl
128xl
256 x 1
256 x 1
1024 x 1

24
24
24

24
24

22

25
30
20
22
25
30
20
22
25
30
20

24

PROMs

24

10 to 75°C)

MCM10143
MCM10145
MC10HI45
MCM10148
MCM10147
MCM10144
MCM10152
MCM10146

24

24
24
22
22
22
22
24 '

22

24

25
30

24
24

Organization

32x8
256x4
256x4

Part Number

MCM10139
MCM10148-10
MCM10148-25

Ac_TIme
Ins maxi

15.3
16
6
15
15
26
15
29

Pine
24

18
18
16
18
16
16
18

Acc_Time
Ins maxi

Pins

20
10
25

16
16
16

Ace... Time
(na max)

Pins

36
45

22
22

Ac_Time
Ine maxi

Pins

CAM
Part Number

*To be introduced

MCM10HI65

MILITARY PRODUCTS
CMOS Static RAMs

CMOS Cache Tag RAMs

1+5V, -55 to 125°C)
Organization

4Kx4

8Kx8

16Kx4

84Kxl

32Kx8

I +5 V, -55 to 125°C)
Ace_Time
Insmaxl

Pine

Organization

8168-65/BRAJC
6168-65/BUAJC
8168-70/8RAJC
6168-70/ BUAJC

65
65
70
70

20
20
20
20

4Kx4

6268-35/BRAJC
6268-351 BUAJC
62611-451 BRAJC
62611-451 BUAJC
8164-651 BXAJC
6164-65/BUAJC
8164-70/BXAJC
8164-70/BUAJC
6268-35/BXAJC
6268-351 BUAJC
6288-451 BXAJC
62611-451 BUAJC
6287-36/BXAJC
6287-351 BUAJC
6287-45/BXAJC
6287-451 BUAJC
6206-45/BXAJC*
6206-55/BXAJC*
6206-70/BXAJC*

35
35

20

45
45
65
65
70
70
35
35

20
20
28
32
28
32
22'
22

45
45

22
22

35
35

22
22
22
22

Part Number

45
45
45
65
70

Part Number

4180-36/BXAJC*
4180-45/BXAJC*

TTL RAMs
1+5V, -55 to 125°C)

20

Organization

256Kx4

1024 x 1

Part Number

93422/BWAJC
93L422/BWAJC
93L422A/BWAJC
93416/BEAJC
93416/BFAJC
93425/BEAJC
93425/BFAJC

*To be introduced

28
28
28

MOTOROLA MEMORY DATA
1-4

80
75

65
45
45
45
45

22
22
22

16
16
16
16

•

CROSS REFERENCE
The part numbers in the first column are arranged in alphanumeric sequence. The "Motorola
Part Number" denotes what is believed to be the functional equivalent by pin function, except
for differences in selectl enable functions.
NOTE: The user must verify speed, power, and package interchangeability based on detailed
specifications.
Motorola does not assume any liability arising out of the application or use of any product
listed.
.

MOS Dynamic RAM Cross Reference
Competition
Part
Number
AM90C256
AM90C256
HM50464
HM511000
HM511001
HM511002
HM5125&
HM5125&L
HY51Cl00
HY51C256
HY51C464
HY51256L
HY51464
KM41256A
LH2125&
LH2464
LH2465
LH6425&
LH66267
M4125&N
M41256P
M441024K
M441024P
M5M4Cl000
M5M4Cl00l
M&M4Cl002
M&M44C256
M5M44C258
M&M4464
MB8125&
MB81464
MN4125&
MSM41000
MSM41001
MSM41004
MSM41005
MSM4125&
MSM41464
MTI256
MT4064
TC511000
TC511001
TC511002
TMM4125&
TMM41464A

Motorola
Part Number
MCMII2Ii6II
MCM82&8B
MCM41464
MCM&l1000A
MCM&l1OO1A
MCM&11002A
MCM82&8B
MCM82&8B
MCM&11000A
MCM82&8B
MCM41484
MCM82&8B
MCM41464
MCM82&8B
MCMtI258B
MCM41464
MCM41484
MCM&142IiIIA
MCM&142IiIIA
MCM82&8B
MCM82&8B
MCM&142IiIIA
MCM&142IiIIA
MCM&11000A
MCM&l1OO1A
MCM&11002A
MCM&142IiIIA
MCM61421i11A
MCM41464
MCM82&8B
MCM41484
MCM82&8B
MCM&11000A
MCM&11001A
MCM&142IiIIA
MCM&142IiIIA
MCM82&8B
MCM41464
MCM82&8B
MCM41464
MCMlIl1000A
MCM&l1OO1A
MCM&11002A
MCM82&8B
MCM41464

MOS DRAMs (Continued)
Competition
Part
Number
TMS425&
TMS4Cl024
TMS4Cl025
TMS4Cl027
TMS44C256
TMS44C257
TMS4464

Organization
256Kxl
256Kxl
64Kx4
lMxl
lMxl
lMxl
256Kxl
25&Kxl·
lMxl
256Kxl
64Kx4
25&Kxl
64Kx4
25&Kxl
25&Kxl
64Kx4
64Kx4
256Kx4
256Kx4
256Kxl
256Kxl
25&Kx4
25&Kx4
lMxl
lMxl
lMxl
25&Kx4
256Kx4
64Kx4
256Kxl
64Kx4
25&Kxl
lMxl
lMxl
25&Kx4
25&Kx4
25&Kxl
64Kx4
256Kxl
64Kx4
lMxl
lMxl
lMxl
25&Kxl
64Kx4

~PD41256
~PD41464

,.PD421000
,.PD421001
~PD421002

Motorola
Part Number
MCM82&8B
MCM&11000A
MCM&11001A
MCM&11002A
MCM&142IiIIA
MCM&142IiIIA
MCM41464
MCM82&8B
MCM41464
MCM&11000A
MCM&11001A
MCM&l1002A

Organization
256Kx 1
lMxl
lMxl
lMxl
256Kx4
25&Kx4
64Kx4
25&Kxl
64Kx4
lMxl
lMxl
lMxl

MOS Static RAM Cross Reference
Part
Number
Am2168
Am2169
Am9128
Am99CI64
Am99C165
Am99C641
Am99C68
Am99C88
Am99C88
Am99C88L
Am9UL68
CDM62256
CDM6284
CXK&464
CXK6814
CXI(l;82!j5
CXK5864
CXK6865
CY7CI28
CY7CI64
CY7CI66
CY7CI68
CY7Cl69
CY7Cl86
CYC7166

Motorola
Part Numb..
MCM1G3/D118/IMS1G3
MCMD1I8
MCM2018A
MCMD1I8
MCMI290
MCM6287
MCM1G3/D118
MCM8164/81L84/82114
MCMI084/811L64
MCMI164/61L84/82114
MCM1G3/D118
MCMI02Ii8A/IOUIiBA
MCM8084/80L84
MCM1288
MCM2018A
MCMI2II8
MCM8164/81L84/82114
MCM6164/61L84/82114
MCM2018A
MCM1288
MCMI290
MCMD1I8
MCM1288
MCM82114
MCMI164/61L84

Organization
4K,,4
4Kx4
2Kx8
16Kx4
16Kx4
64Kxl
4Kx4
8Kx8
8Kx8
8Kx8
4Kx4
32Kx8
8Kx8
16Kx4
2Kx8
32Kx8
8Kx8
8Kx8
2Kx8
16Kx4
16Kx4
4Kx4
4Kx4
8Kx8
8Kx8
Continued

MOTOROLA MEMORY DATA

1-5

•

CROSS REFERENCE (Continued)
MOS SRAMs (Continued)
Part
Number
CY7Cl87
CY7Cl97
CY7Cl98
Fl600
Fl620/Fl621
Fl622
GM76C88
HM3-65768
HM3-66787
HM3-65768
HM6168H
HM6168HL
HM62256
HM6264
HM6264L
HMI288
HMI288L
HMI287
HMI287L
HM-6616
HM-66162
HM-66172
HM66681
HM66768
HM8788
HM6789
HM6832
HY2116
HY61C16
HY61C68
HY61C68L
HY6116
HY62C64
HY62C87
HY62C68
HY63C266
10T6116L
10T61165
10T6168L
10T6168LA
10T6168S
10T6168SA
10T61685A
10T71268L
10T71266S
10T7164L
10T7164S
10T7187L
10T71875
10T7188L
10T7188S
10T7198l..
10T7198S
10T71256
10T712575
10T8M864L
IMSl420
IMSl420L
IMSl421
IMSl423

Mot"rola
Part Number
MCMI287
MCMI2II7
MCMII2II8
MCMI287
MCMI288
MCM62IIO
MCM8064180L64
MCM62118
MCMI287
MCMI288
MCM62118
MCM62118
MCM8D2S6A/8OI.2fi8A
MCM8164/81L64/8064tl284·
MCM8164/81L64/80L64/1284
MCMI288
MCM62118
MCMI287
MCMI287
MCMZ018A
MCMZ018A
MCMZ018A
MCMI288
MCM62118
MCMI288
MCM62IIO
MCM8II2Ii8A
MCMZ018A
MCMZ018A
MCMI288
MCM62118
MCMZ018A
MCM8164/81L64/1284
MCMI287
MCMI288
MCMII2II8
MCMZ018A
MCMZ018A
MCMI288
" ...
MCM62118
MCMl423
MCMI288
MCMI288
MCM8OI.2fi8A
MCM8II2Ii8A
MCM81L64/80L64
MCM8164/8064/1284
MCM1287
MCM1287
MCM1288
MCM1288
MCM6280
MCM6280
MCM12118
MCMII207
MCM80L64
MCM1288
MCM62118
MCM62118
MCM62118
~

Part
Number
IM51600
IM51801
IMSl620
IMSl624
IMSl630
KM6264
LH52251
MB61C71A
M.BS1C68
MBS1C68A
MBS1C68W
MB81C68A
MB81C71
MBS1C74
MBS1C711
MB8128
MBSl68
MB8171
MB6418A
MB8418A·L
MB8417A
MB8417A-L
MB8418A
MB8418A-L
MB84256
MB8464
MB8464-L
MK41H68
MK41H69
MK41 1:180
MK4802
MSM2128
MSM5128
MSM5165
MSM5165L
MSM5257
MS8168
MS8264
MS6264L
MS8287
MS8286
M5M21C68
M5M5116
M5M5117
M5MallS
M5M51·65
M5M5165-L
M5M5178P
M5M5187
M5M5168
M5M5189
MT5C2561
MT5C2568
NMC2116
NMC6164
NMC6164L
P4Cl64
P4Cl68
P4Cl87
P4Cl68

Organization
. 641< x 1
266Kxl
32Kx8
64Kxl
16Kx4
16Kx4
8Kx8
4Kx4
64Kxl
16Kx4
4Kx4
4Kx4
32Kx8
8Kx8
8Kx8
4Kx4
4Kx4
641< x 1
641< x 1
2Kx8
2Kx8
2Kx8
4Kx4
4Kx4
16Kx4
16Kx4
32Kx8
2Kx8
2Kx8
4Kx4
4Kx4
2KxS
SKxS
641< x 1
16Kx4
32KxS
2KxS
2K·xS
4Kx4
4Kl\4
4Kx4
4Kx4
4Kx4
32KxS.
32KxS.
8Kx6
SKxS
64Kxl
64Kxl
16Kx4
16Kx4
16Kx4
16Kx4·
32KxS
268Kxl
SKxS
4Kx4
4Kx4
4Kx4
4Kx4

MOTOROLA MEMORY DATA

HI

Motorola
Part Number
MCM1287
MCM1287
MCM1288
MCM6280
MCM8164/81.L64/1284
MCM8064
MCMII207
MCM1287
MCM62118
MCM62118
MCMI288
MCM621111
MCMI287
MCMI288
MCM8164/81L64/1284 .
MCMZ018A
MCMI288
MCMI287
MCMZ018A
MCMZ018A
MCMZ018A
MCMZ018A
MCMZ018A
MCMZ018A
MCM8II2Ii8A
MCM8064/80L64
MCM80L64
MCM62118
MCM621111
MCM4180
MCMz018A
MCMZ018A
MCMZ018A
MCM8064/80L64
MCM8064/80L64
MCMI2II7
MCMI288
MCM8164/11L64/1284
MCM81L64
MCMI287
MCMI288
MCM62118
MCMZ018A
MCMZ018A
MCMZ018A
MCM8164/81L64/1284
MCM8164/81L64/1284
MCM1284
MCM1287
MCM1288
MCM62IIO
MCMII207
MCM12118
MCMZ018A
MCM8164/81L64/1284
MCM8164/81L64/1284
MCM1284
MCMI288
MCMI287
MCMI288

Organization
64Kxl
64Kxl
16Kx4
16Kx4
SKxS
SKxS
256Kxl
64Kxl
4Kx4
.4K.x4
4Kx4
4Kx4
64Kxl
16Kx4
SKxS
2KxS
4Kx4
641< x 1
2KxS
2KxS
2KxS
2KxS
2Kx8
2Kx8 .
32KxS
SKxS
SKxS
4Kx4
4Kx4
4Kx4
2KxS
2KxS
2KxS
SKxS
SKl\S
256Kxl
4Kx4
SKxS
SKxS
641< x 1
16Kx4
4Kx4
2KxS
2KxS
2KxS
SKxS
SKxS
.8KxS
641< x 1
16KX4
16Kx4
266Kx 1
32KxS
·2KxS
SKxS
8KxS
8KxS
4Kx4
64Kxl
16Kx4

II

CROSS REFERENCE (Continued)
MOS SRAMs (Continued)
Part
Number
P4CI98
P4C1257
PS6168
SCM21CI6
SCM6116
SCM6116L
SMJ5617
SRM2016
SRM20266
SRM2064
SRM2261
SRM2264
SRM2268
SRM2274
SRM2275H
SR16K4
SR64E4
SR64Kl
SR64K4
SR64K8
SSL4180
SSM6168
SSM6170
SSM7164
SSM7166
SSM7168
SSM7192
SSM7193
SSM7194
SSM7195
STC2168
STC2168L
STC2168M
STCf1264
S6516
TC5617B
TC5617B-L
TC551BC
TC551BC-L
TC55257
TC55257L
TC56416
TC56417
TC5661
TC5662

Motorola
Part Numbar
MCM82lIO
MCMI2II7
MCM62118
MCM2II18A
MCM2II18A
MCM2018A
MCM2II18A
MCM2II18A
MCM802Ii8A
MCM8084/11OL64
MCM82B7
MCM8164/81L64/8084/11OL64
MCM8268
MCM8268
MCM82lIO
MCM8268
MCM82lIO
MCM82B7
MCM8268
MCM8164/61L64/f1264
MCM4180
MCM8268
MCM8210
MCMf1264
MCM82lIO
MCM8268
MCM8292
MCMII293
MCM12!14
MCMI296
MCM62118
MCM8268
MCM8268
MCM8084/80L64
MCM2II18A
MCM2II18A
MCM2018A
MCM2II18A
MCM2018A
MCM602Ii8
MCM80L2&8A
MCM8268
MCM82lIO
MCM82B7
MCM82B7

Part
Number
TC5666
TC556S-L
TMM2015A
TMM2016
TMM2016A
TMM201S
TMM2019
TMM2063
TMM2064
TMM2066
TMM2068
TMS4016
UM2128
UM2129
UM6116
UM6168
"P04016
"PD4168
"PD42832
"PD4314
I'PD43266
"PD43257-L
"PD4361
"PD4362
"PD4364
"PD4364L
"PD448
"PD4484
I'PD449
VT2OC68

Organization
16Kx4
266Kxl
4Kx4
2Kx8
2Kx8
2Kx8
2Kx8
2Kx8
32Kx8
6Kx8
64Kxl
SKxS
4Kx4
16Kx4
16Kx4
4Kx4
16Kx4
64Kxl
16Kx4
SKxS
4Kx4
4Kx4
4Kx4
8Kx8
16Kx4
16Kx4
16Kx4
16Kx4
16Kx4
16Kx4
4Kx4
4Kx4
4Kx4
8Kx8
2Kx8
2KxS
2KxS
2KxS
2KxS
32KxS
32KxS
16Kx4
16Kx4
64Kxl
64Kxl

VT2OC69

VT64KS4
VT66KS4
V61C62
V61C68
V62C64
51C68
51C69
BBOBCL
6832C

MOTOROLA MEMORY DATA
1-7

Motorola
Part Number
MCM8084/11OL64
MCM8084/11OL64
MCM2II18A
MCM2II18A
MCM2II18A
MCM2II18A
MCM2II18A
MCM8084/11OL64
MCM8084/11OL64
MCM8268
MCM8164/81L64/f1264
MCM2II18A
MCM2II18A
MCM2II16H
MCM2II18A
MCM8268
MCM2II18A
MCM8084
MCM802Ii8A
MCM8268
MCM802Ii8A
MCM8OL2&8A
MCM82B7
MCM8268
MCM8164/81L64/f1264
MCM8084/80L64
MCM2II18A
MCM8084/80L64
MCM2018A
MCM8268
MCM6289
MCM8268
MCM82lIO
MCM8268
MCM8268
MCM8164/81L64/f1264
MCM8268
MCM6288
MCM80L64
MCM80258A

Organization
SKxS
6KxS
2KxS
2KxS
2KxS
2KxS
2Kx8
SKxS
SKxS
4Kx4
SKx8
2KxS
2Kx8
2Kx8
2Kx8
4Kx4
2Kx8
SKxS
32KxS
4Kx4
32KxS
32KxS
64Kxl
16Kx4
SKxS
SKxS
2Kx8
8Kx8
2Kx8
4Kx4
4Kx4
16Kx4
16Kx4
16Kx4
4Kx4
8Kx8
4Kx4
4Kx4
8KxS
32Kx8

..

MOTOROLA MEMORY DATA
1-8

MOS Dynamic RAMs

MCM6256B
256Kx1, 100/120/150 ns, Page Mode, NMOS ... , ............
MCM6257B
256Kx1, 100/120/150 ns, Nibble Mode, NMOS ..............
MCM41464A
64Kx4, 100/120/150 ns, Page Mode, NMOS .................
MCM511000A, 1M x 1, 70/80/100 ns, Page Mode, CMOS ...................
MCM511-1000A 1M x 1, 70/80/100 ns, Page Mode, CMOS, Lower Power ......
MCM511001A 1M x 1, 70/80/100 ns, Nibble Mode, CMOS ..................
MCM511002A 1M x 1, 70/80/100 ns, Static Column, CMOS .................
MCM514256A, 256Kx4, 70/80/100 ns, Fast Page Mode, CMOS ..•...........
MCM51 L4256A 256K x 4, 70/80/100 ns, Fast Page Mode, CMOS, Lower Power
MCM514258A 256Kx4, 70/80/100 ns, Static Column, CMOS ...............
MCM81000
1M x 8 DRAM Module, 80/100 ns, Fast Page Mode, CMOS ....
MCM91000
1M x9 DRAM Module, 80/100 ns, Fast Page Mode, CMOS ....

MOTOROLA MEMORY DATA
2-1

2-3
2-15
2-27
2-39
2-39
2-54
2-69
2-84
2-84
2-99
2-114
2-116

II

II
MOS/CMOS Dynamic RAMs
I +5 V, 0 to 70°C)
Organization

A_nme
(namaxl

Part Number

64Kx4

MCM4146'4AP10
MCM4146'4AP12
MCM4146'4AP16

IP)
IP)
IP)

'266Kxl

MCM62568Pl0

'...~

Cb~~

MCM6256aP12~«:,.1 ~'\

MCM62668j'ft' . ,41:)
MCM62678i'10 O"'lN)
MCM62578P12
IN)
IN)
MCM82678P16
266Kx4

100

MCM614256AP70
MCM614256APBO
MCM514256AP10
MCM614266AJ70
MCM614266AJ80
MCM514266AJ10
MCM614266AZ1O
MCM514266A280
MCM&l4258AZ10
MCM614256AP70
MCM614256APBO
MCM614256AP10
MCM514268AJ70
MCM&l4268AJ80
MCM614268AJ10
MCM514266AZ1O
MCM614258AZ80
MCM614258AZ10

IPII
{i'll
IPII
IPII
(PII
IPII
IPII
IPII
IPII
(S)
IS)
IS)
IS)
IS)
IS)
IS)
IS)
IS)

!l>'\~

160
100
120
160
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100

PIns

Organization

Part Numbar

Ac_nme
(namaxl

18
18
18
16
16
16
'16
16
16
20
20
20

lMxl

MCM611000AP70 IPII
MCM611000APBOIP)'
MCM611000AP10 IPII
MCM511000AJ70 IPII
MCM511000AJ80 IP)'
MCM611000AJ10 IPII
MCM611000AZ70 IPII
MCM&ll000A280 IPII
MCM611000AZ10 IPII'
MCM511001AP70 IN)
MCM611001APBO IN)
MCM611001AP10 IN).
MCM611001AJ70 IN)
MCM611001AJaO IN)
MCM611001AJ10 IN)
MCM511001AZ70 IN)
MCM511001A280 IN)
MCM611001AZ10 IN)
MCM511002AP70 (S)
MCM511002APBO IS)
MCM511002AP10 IS)
MCM511002AJ70 IS)
MCM511002AJ80 IS)
MCM611002AJ10 IS)
MCM511002AZ70 IS)
MCM511002A280 IS)
MCM511002AZ10 IS)

70
80
100
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100
70
80
100

20/26
20/26
20/26
20
20
20
20
20
20

20/26
20/26
20/26
20
20
20
(PI Page Mode
(NI Nibble Mode
(SI Static Column

'Low power version available;
order by MCM51 L.•.

CMOS Dynamic RAM Modulas
I + 5 V, 0 to 70°C', 3O-Lead SIMM Package)
Organization

Part Number

Ac_nme
(namaxl

PIns

lMx8

MCM81000S80
MCM81000s10

80
100

30
30

lMx9

MCM91000s80
MCM91000s10

80
100

30
30

MOTOROLA MEMORY DATA
2-2

PIns

18
18
18

20/26
20/26
20/26
20
20
20
18
18
18

20/26
20/26
20/26
20
20
20
18
18
18

20/26
20/26
20/26
20
20
20

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

L..--M_C_M_6_2_56_B------I1

256K-Bit Dynamic RAM
The MGM6256B is a 262,144 bit, high-speed, dynamic random access memory.
Organized as 262,144 one-bit words and fabricated using N-channel silicon-gate MOS
technology, this single +5 volt supply dynamic RAM combines high performance with
low cost and improved reliability. All inputs and outputs are fully TTL compatible.
By multiplexing row and column address inputs, the MCM6256B requires only nine
address lines and permits packaging in standard IS-pin 300 mil wide dual-in-line packages.
Complete address decoding is done on-chip with address latches incorporeted. Data out
(0) is controlled by CAS allowing greGter system flexibiiity.
The MCM6256B features "page mode" which allows random column accesses of the
512 bits within the selected row.
•
•
•

Organized as 262,144 Words of 1 Bit
Single +5 Volt Operation (± 10%)
Maximum Access Time: MCM6256B-,O= 100 ns
MCM6256B-12 = 120 ns
MCM6256B-15 = 150 ns
• Low Power Dissipation: MCM6256B-l0=440 mW Maximum (Active)
MCM6256B-12=396 mW Maximum (Active)
MCM6256B-15=368 mW Maximum (Active)
2B mW Maximum (Standby)
• Three-State Data Output
• Early-Write Common 1/0 Capability
• 256 Cycle, 4 ms Refresh
• RAS-Only Refresh Mode
• CAS Before RAS Refresh
• Hidden Refresh
•

Page Mode ca~tY,

.p PACKAGE
PLASTIC

CASE848D

PIN ASSIGNMENT

Vss

AS

CAS
Q

A6
A3
A4

AS
A7

PIN NAMES

BLOCK DIAGRAM

w----------------~--~

CAS-----------+I

-

DATA OUT
SUFFER

~----"Q

AD
Al
A2
A3
A4
AS
A6
A7
AS

RAS---------~

MOTORdLA MEMORY DATA
2-3

AD-AS • • . . • • : . • • . Address Input
O • . • . • . . . . . • . . . • . . • Data In
Q . • • • . • • . • • • • • • • • • Data Out
'iN. . . . . . . . . . . . Read/Writs Input
RAS . • . • • . • • Row Address Strobe
CAS . . . . . . Column Address Strobe
VCC . • • . • • . . • . • . Power (+5V)
VSS . . . . . . . . . . . . . . . . . Ground

II

MCM6256B

ABSOLUTE MAXIMUM RATINGS (See Notel
Symbol

Rating
Power Supply Voltage
VOII8ge Relative to YSS for Any Pin Exoept VCC

Valua

Unit
V

VCC

-1 to +7

Vin, Vout

-1 to +7

V

lout

60

mA

Data Out Current
Power Dissipation

Po

600

mW

OPerating Temperatura Range

TA

Oto +70

·C

Storage Temperature Range

Teto

-56 to +160

·C

This device contains circuitry to protect the
inputs' against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltage. to this high-impedance circuit. '

NOTE: Permanent device damaga may occur If ABSOLUTE MAXIMUM RATINGS ara
axceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Expoaureto higher than recommanded voItageaforextended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V

± 10%, TA=O to 70o e,

Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

V

1

Logic 1 Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic 0 Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notaa

mA

2

Parametar
Supply Voltage (Operating Voltage Rangel

DC CHARACTERISTICS
Symbol

Characteristic
V CC Power Supply Currant
MCM6256B-l0, tRC= 190 ns
MCM6256B-12, tRC=220 ns
MCM6256B-15, tRC=280 ns

ICCI

VCC Power Supply Current (Standbyl (RAS = CAS = VIH)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles (CAS=VIHI
MCM6256B-l0, tRC = 190 ns
MCM6256B-12, tRC=220 ns
MCM6256B-15, tRC=280 ns

Icea

VCC Power Supply Current During Page Mode Cycla (RAS = VIL)
MCM6256B-l0, tpc = 100 n.
MCM6256B-12, tPC= 120 n.
MCM6256B-15, tpc = 145 n.

ICC4

V CC Power Supply Current During CAS Before RAS Refresh
MCM6256B-l0, tRC = 190 ns
MCM6256B-12, tRC=220 /1S
MCM6256B-15, tRC=280 ns

ICC5

Input Leakage Current IVSS ni the CAS clock active transition
will determine read access time. The external CAS signal is
ignored until an internal RAS signal is available. This gating
feature on the 'CAS clock will allow the external CAS signal
to become active as sOOQ as the row address hold time (tRAH)
specification has been met and defines the tRCD minimum
specification. The time difference between tRCD minimum and
tRCD maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in
generating the CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the

WRITE CYCLE
A write cycle is Similar tp a read cycle except that the Write
(iN) clock must go active (VIL levell at or before the CAS clock
goes active at a minimum twcs time. If the above condition
is met, then the cycle in progress is referred to as an early
write cycle. In an early write cycle, the write clock and the
data in are referenced to the active transition of the CAS clock
edge. There are two important parameters with respect to the
write cycle: the column strobe to write lead time (tCWL) and
the row strobe to write lead time (tRwLl. These define the
minimum time that RAS and CAS clocks need to be active
after the write operation has started (iN clock at VIL levell.
It is also possible to perform a late write cycle. For this cycle
the write clock is activated after the CAS goes low which is
beyond twcs minimum time. Thus the parameters tCWL and
tRWL must be satisfied before terminating this cycle. The
difference between an earlY'write cycle and a late write cycle
is that in a late write cycle the write (iN) clock can occur much
later in time with respect to the active transition of the CAS
clock. This time could be as long as 10 microseconds [tRWL +tRP+2tTl.
At the start of an early write cycle, the data out is in a high
impedance condition and remains inactive throughout the
cycle. The data out remains three-state because the active
transition of the write (iN) clock prevents the CAS clock from
enabling the data-out buffers. The three-state condition (high
impedance) of the data out pin' during a write cycle can be
effectively utilized in systems that have a common input/output bus. The only stipulation is that the system use only early
write mode operations for all write cycles to avoid bus
contention.
READ-MODIFY-WRITE AND READ-WHILE-WRITE
CYCLES
As the name implies, both a read and a write cycle are
accomplished at a selected bit during a single access. The
read-modify-write cycle is similar to the late write cycle discussed above.
. .
For the read-modify-write cycle a normal read cycle is initiated with the write (iN) clock at the VIH level until the read
data occurs at the device access time (tRAC)' At this time the
write (iN) clock is asserted. The·data in is setup and held with
respect to the active edge of the write clock. The cycle described assumes a zero modify time between read and write.
Another variation of the read-modify-write cycle is the readwhile-write cycle. For this cycle, tCWD plays an important
role. A read-while-write cycle starts as a normal read cycle
with the write (iN) clock being asserted at minimum tCWD
time, depending upon the application. This results in starting
a write operation to the selected cell even before data out

MOTOROLA MEMORY DATA
2-12

MCM6256B

occurs. The minimum specification on tCWD assures that data
out does occur. In this case, the data in is set up with respect
to write (iN) clock active edge.

associated internal row locations are refreshed. As the heading
implies, the CAS clock is not required and must be inactive
or at a VIH level.

PAGE-MODE CYCLES

CAS Before RAS Refresh

Page mode operation allows fast successive data operations
at the 512 column locations on a given row. Page access (tCAC)
is typically half the regular RAS clock access (tRAC) on the
Motorola 256K dynamic RAM. Page mode operation consists
of holding the RAS clock active while cycling the CAS clock
to access the column locations determined by the 9-bit column
address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column address and CAS clock. From the timing illustrated, the
initial cycle is a normal read or write cycle, that has been
previously described, followed by the shorter CAS cycles
(tpC). The CAS cycle time (tpc! consists of the CAS clock
active time (tCAS), and CAS clock precharge time (tcp) and
two transitions. In addition to read and write cycles, a readmodify-write cycle can also be performed in a page mode
operation. For a read-modify-write or read-while-write type
cycle, the conditions normal to that mode of operation will
apply in the page mode also. In practice, any combination of
read, write and read-modify-write cycles can be performed to
suit a particular application.

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR). This activates the internal refresh counter
which generates the address to be refreshed. Externally applied
addresses are ignored during the automatic refresh cycle. If
the output buffer was off before the automatic refresh cycle,
the output will stay in the high impedance state. If the output
was enabled by CAS in the previous cycle, the data out will
be maintained during the automatic refresh cycle as long as
CAS is held active (hidden refresh).
Hidden Refresh
The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing
a CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh operation of MCM6256B can be tested
by CAS before RAS refresh counter test. This cycle performs
read/write operation taking the internal counter address as
row address and the input address as column address.
The test is performed after a minimum of 8 CAS before RAS
cycles as initialization cycles. The test procedure is as follows.

REFRESH CYCLES
The dynamic RAM design is based on capecitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Therefore, to retain the
correct information, the bits need to be refreshed at least once
every 4 milliseconds. This is accomplished by sequentially cycling through the 256 row address locations every 4 milliseconds, (i.e., at least one row every 15.6 microseconds like the
64K dynamic RAM). A normal read or write operation to the
RAM will serve to refresh all the bits (1024) associated with
the particular rows decoded.

1.
2.

3.

2.
4.

RAS-Only Refresh
In this refresh method, the system must perform a RASonly cycle on 256 row addresses every 4 milliseconds. The
row addresses are latched in with the RAS clock, and the

Q -

HIGH Z

+---{

Write a "0" into all memory cells.
Select any column address and read the "O"s written in
step 1. Write a "I" into each cell of the selected column
by performing CAS before RAS Refresh Counter Test
Read-Write Cycle (see timing diagram). Repeat 256 times.
Read the "1"s (use a normal read mode) written in step

5.

Select the same column address as step 2, read the "1"s
and write a "0" into each cell by performing CAS before
RAS Refresh Counter Test Read-Write Cycle (see timing
diagram). Repeat 256 times.
Read the "O"s (use a normal read mode) written in step

4.
6.

Repeat steps 1 through 5 using complement data.

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-13

IJ

MCM6256B

fI

ORDERING INFORMATION
(Order by Full Part Number)

T. .

CM

Motorola Memory prefix _ _ _ _ _ _

Tr

Part N u , m b e r - - - - - - - - - - - - - - '

TL._,-----Speed(10='100ns, 12= 12Ons. 15= 150ns)

'---------Package (P=Plastic)

Full Part Numbers-MCM6256BP10
, MCM6256BP12
MCM6256BP15

MOTOROLA MEMORY DATA
2-14

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6257B

256K X 1 Nibble Mode Dynamic

RAM
The MCM6257B is a 262,144 bit, high-speed, dynamic random access memory.
Organized as 262,144 one-bit words and fabricated using N-channel silicon-gate MOS
technology, this single + 5 volt supply dynamic RAM combines high performarfCe with
low cost and improved reliability. All inputs and outputs are fully TTL compatible.
By multiplexing row and column address inputs, the MCM6257B requires only nine
address lines and permits packaging in standard 16-pin 300 mil wide dual-in-line packages.
Complete address decoding is done on-chip with address latches incorporated. Data out
(U) is controlled by CAS allowing greater system flexibility.
The MCM6257B features "nibble mode" which allows serial access of 4 bits of data at a
high data rate.

•
•

Single + 5 Volt Operation (± 10%)
Maximum Access Time: MCM6257B-10=100 ns
MCM6257B-12 = 120 ns
MCM6257B-15=150 ns
Low Power Dissipation: MCM6257B-10=440 mW Maximum (Active)
MCM6257B-12=396 mW Maximum (Active)
MCM6257B-15=35B mW Maximum (Active)
2B mW Maximum (Standby)
Three-State Data Output
Early-Write Common 1/0 Capability
• 256 Cycle, 4 ms Refresh
CAS Before RAS and RAS-Only Refres
Hidden Refresh
• Fast Nibble Mode Access and

'-----.------J

-

P PACKAGE

PLASTIC
CASE848D

PIN ASSIGNMENT
A8
D

•
••
•
•

BLOCK DIAGRAM

w----------~r_~

r~~~~----D

)---1-~

t-----~o

AD
A1
A2
A3
A4
A5
A6
A7
A8

RAS----~

MOTOROLA MEMORY DATA
2-15

I

1.

16
15

VSS
CAS

14

0

13 AS
12

A3

11

A4

A1

10

A5

VCC

9

A7

PIN NAMES

AD-AS . . . . . . . . . . • Address Input
o .................. Data In
Q • • . . • • . . • . • . . . • • • Data Out
Vii. . . . . . . . . . . . Read/Writs Input
ilAS . . . . . . . . Row Address Strobe
CAS . . . . . . Column Address Strobe
VCC •..•..•..... Powerl+5V)
VSS •..••••••••••••• Ground

II

MCM6257B

FI

ABSOLUTE MAXIMUM RATINGS (See Nota)
RatIng
Power Supply Voltage
Voltage Ralaliva to Vss'for Any Pin Except VCC
Data Out Currant

'Symbol

Valua

Unit

VCC
Vin, Vout

-1 to +7
-1 to +7

V
V
mA

lout
Po

Power Dissipation
Operating Temperature Range
Storage Temperature Range

50
600
o to +70

mW

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this hiQh-impadanca circuit.

.

.

·C
TA
-SSto +150 ·C
Tstg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Expoaure to higher than recommended voltages for axtended
periods of time could affect devies reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 v ±10%, TA=O to 70·C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS
VIH

0

0

0

V

1

2.4
-1.0

-

6.5
0.8

V
V

1
1

Symbol

Min

Max

-

Unit
mA

N_

ICCI

90
72
66
6.0

-

50
48
46

Input High Voltage, All Inputs
Input Low Voltage, All Inputs

VIL

DC CHARACTERISTICS
Characteristic
VCC Power Supply Currant
MCM6267B-l0, IRC=I90 na
MCM6267B-12, IRC=22O na
MCM6267B-15, tRC=260 ns
VCC Power Supply Currant (Standby) (R~=m=VIH)
VCC Power Supply Currant During liAS only Refresh Cycles (m = VIH)
MCM6257B-l0, tRC = 190 ns
MCM6267B-12, IRc = 220 ns
MCM6257B-16, IRC=260 ns

ICC2
ICC3

VCC Power Supply Currant During Nibble Mode Cycle (liAS = VIL)
MCM6257B-l0, tNC=50 ns
MCM6257B-12, tNC = 60 ns
MCM6257B-15, tNC=70 ns
VCC Power Supply Current During m Before liAS Refresh
MCM6257B-l0, tRC=I90 ns
MCM6257B-12, tRC = 220 ns
MCM6257B-15, tRC=260 ns
Input Leakage Currant (VSS :tRWD (min), the cycle is read-write cycle and the data out will contain data read from the

selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.

READ CYCLE TIMING
tRe
tRAS

iiAS

VIHVll-

m

VIHVll-

AODRESSES

VIHVll-

W

Q

(DATA oun

VIHVll-

VOH -

HIGH Z

VOl-

MOTOROLA MEMORY DATA
2-18

MCM6257B

WRITE CYCLE TIMING
~----------------------tRC------------~----------~

ADDRESSES

iii

VIH-

o IDATA INI

VIH-

VIL - L....:."-lo~:...lI:....liL-f"....liL+--f-_+-__-1-l'''-lo'-lool;,..,.lj~....liL..¥...¥.fl'-~.lL-.lL-.loL...loL...loL...IL...~

....................--.........................""'"'.............,...,.

VIL - ...............--"'--"'-i'"..........-l"---=;.;....-~r"...JoI....v.....v..

f+-------- tDHR --------+I

n IDATA DUTI

VDH- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH
VOL -

Z----------------

READ-WRITE/READ-MODIFY-WRITE CYCLE
tRWC Dr tRMW
RAS

tRAS

VIH VIL -

tAR

III
tRSH

_tRCD

tCSH

tCAS

CAS

ADDRESSES

iii

VIHVIL -

VIH VIL -

n (DATA OUT)

o {DATA INI

MOTOROLA MEMORY DATA
2-19

MCM6257B

fI

NIBBLE MODE READ CYCLE

----...... ~--------------------tR~--------------------~
m

VIH-----+~-..........

J<-+-""f"

Vll-

ADDRESSES VIHVll-""""''''''''''"-->I'

o (DATA OUT! VOH -

_ _ __

VOL-

NIBBLE MODE WRITE CYCLE (EARLY WRITE)

RAS

CAS

ADDRESSES

Vi

VIHVll-

VIHVll-

VIHVll-

VIHVll-

o (DATA IN!

VIH-

o (DATA oun

VOHVOL '-

Vll-

MOTOROLA MEMORY DATA
2-20

MCM6257B

NIBBLE MODE READ-WRITE/READY-MODIFY-WRITE CYCLE

VIHRAS

Vll-

VIHCAS

Vll-

VIH-

ADDRESSES

Vll-

W

o tDATA IN)

VIHVll-

VIH VIl-

a tDATA OUT)

VOHVOl-

RAS-ONLY REFRESH CYCLE
(D,

W, and AI ara Don't Care, CAS i8 High)
IRC

IRAS

i\
!+--lJip-

'"":::~:~--~
lASH

I--IRAH
~

CAS-BEFORE RAS REFRESH CYCLE
(W, D, and A...A8 are Don't Care)
I+-------IRC--------+/
t------IJiAS:---------t
VIHRAS

VllICSR
j 4 - - - - I C H R - - - -..

m
a (DATA OUT)

VIHVll-

VOH-----------HI6H Z- - - - - - - - - - - - VOl-

MOTOROLA MEMORY DATA
2-21

MCM6257B

FI

HIDDEN REFRESH CYCLE (READI
~_ _ _--IRC-----"'_----IRC-------I~

I+----IRAS----+j
vIH-

HAS

CAS

VIL VIHVIL VIH -7r"':I\~"'-::::::""',,"

ADDRESSES
VIL-

w

~I: ='XXXXX'IY
V

Q IDATA

OUT)

AI~ H::IRCS

OH VOL -

-J~

l:tcAC.j

---1 t_10F_F___

/--'IRAC---/

'

HIGH Z'

T

VAUO DATA

.\,;

HIDDEN REFRESH CYC,LE (WRITEI

MOTOROLA MEMORY DATA
2-22

MCM6257B

III

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

RAS

CAS

ADDRESSES

VIHVll-

VIHVllVIHVll-

READ CYCLE

o IDATA OUT!
iii

VDHVOlVIHVll-

WRITE CYCLE

o IDATA OUT!

iii

D IDATA INI

VOHVOl-

VIHVll-

VIHVll-

READ·WRlTE/READ·MODlfY·WRITE CYCLE
IOFF

oIDATA OUT!

IV

D IDATA INI

VOHVOl-

HIGH Z

VIHVll-

VIHVll-

MOTOROLA MEMORY DATA
2-23

MCM6257B

fI

DEVICE INITIALIZATION

Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the FiAS" clock and the
minimum (tCAS) period for the CAS clock. The RAS clock
must stay inactive for the minimum (tRP) time. The former is
for the completion of the cycle in progress, and the latter is
for the device internal circuitry to be precharged for the next
active cycle.
Oata out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the
write (W) input must be held at the VIH level from the time
the CAS clock makes its active transition (tRCS) to the time
when it transitions into the i,nactive (tRCH) mode.

On power-up an initial pause of 200 microseconds is required
for the internal substrate generator pump to establish the correct bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize the
various dYnamic nodes internal to the device. During an ex·
tended inactiV\l state of the device (greater than 4 milliseconds
with device powered up), the wake up sequence (8 active
cycles) will be necesssry to assure proper device operation.
ADDRESSING THE RAM
The nine address pins on the device are tme multiplexed
with two separate 9-bit address fields that are strobed at the
beginning of the memory cycle by two clocks (aCtive negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of eighteen address bits will decode one
of the 262, 144 cell locations in the device. The column address
strobe follows the row address strobe by a specified minimum
and maximum time called "tRCD:' which is the row to column
strobe delay. This time intervalis also referred to as the multiplex window which gives ~xibility to a system designer to
set up his external addresses into the RAM. These conditions
have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of
the device. There are, however, two other variations in addressing the 256K RAM, one is called the RAS only refresh
cycle (described later) where an 8-bit row address field is'presented on the input pins and latched by the RAS clock. The
most significant bit on Row Address AS (pin 1) is not required
for refresh. The other variation; which is called nibble mode,
allows the user to access 4 bits serially. (See NIBBLE MODE
section. I

WRITE CYCLE
A write cycle is similar to a read cycle except that the Write

(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition
is met, then the cycle in progress is referred to as an early
write cycle. In' an early write cycle, the write 'clock and the
data in are referenced to the active transition of the CAS clock
edge. There are two important parameters with respect to the
write cycle: the 'column strobe to write lead time (tCWL) and
the row strobe to write lead time (tRWL). These define the
minimum time that RAS and CAS clocks need to be active
after the write operation has stsrted (W clock at VIL level).
It is also possible to perform a late write cycle. FOr this cycle
the write clock is activated after the CAS goes low which is
beyond twcs minimum time. Thus the parameters tCWL and
tRWL must be satisfied before terminating this cycle. The
difference between an early write cycle and a late write cycle
is that in a late write cycle the write (W) clock can occur much
later in time with respect to the active transition of the CAS
clock. This time could be as long as 10 microseconds [tRWL +tRP+2trl.
At the start of an early write cycle, the data out is in a high
impedance condition and, remains inactive throughout the
cycle. The data out remains three-state because the active
transition of the write (W) clock prevents the CAS clock from
enabling the data-out buffers. The three-state condition (high
impedancel of the data out pin during a write cycle can be
effectively utilized in systems that have a common input/ output bus. The only stipulation is that the system use only early
write mode operations for all write cycles to avoid bus
contention.

READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, a read-while-write
cycle, and read-modify-write cycle which are covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level.
The CAS clock must also make a transition from VIH to the
VIL level at the specified tRCO timing limits when the column
addresses are latched. Both the FiAS" and CAS clocks trigger
a sequence of events which are controlled by several delayed
internal clocks. Also, these clocks are 'linked'in such a manner
that the access time of the deviCe is independent of the address
multiplex window. The only stipulation is that the CAS clock
must be active before or at the tRCD maximum specification
for an access (data valid) from the FiAS" clock edge to be
guaranteed (tRAC); If the tRCD maximum condition is not
met, the access (tCAC) from the CAS clo~k active transition
will determine read access time. The external CAS signal is
ignored until an internal RAS signal is available. This gating
feature on the CAS clock will allow the external CAS signal
to become active as soon as the row address hold time (tRAH)
specification has been met and defines the tRCO minimum
specification. The time difference between tRCO minimum and
tRCO maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in
generating the CAS clock.

READ-MODIFY-WRITE AND READ-WHILE-WRITE
CYCLES
As the name implies, both a read and a write cycle are
accomplished at a 'selected bit during a single access. The
read-modify-write cycle is similar to the late write cycle discussed above.
For the read-modify-write cycle a normal read cycle is initiated with the write (W) clock at the'VIH level until the read
data occurs at the device access time (tRAC)' At this time the
write (W) clock is asserted. The data in is setup and held with
respect to the active edge of the write clock. The cycle described assumes a zero modify time between read and write.
Another variation of the read-modify-write cycle is the readwhile-write cycle. For this cycle, tcwo plays an important

MOTOAOLAMEMORY DATA
2-24

MCM6257B

role. A read-while-write cycle starts as a normal relld cycle
with the write (W) clocle being asserted at minimum tCWD
time, depending upon the application. This results in starting
a write operation to the selected cell even before data out
occurs. The minimum specification on tCWD assures that data
out does occur. In this case, the data in is set up with respect
to write (W) clock active edge.

associated internal row locations are refreshed. As the heading
implies, the CAS clock is not required and must be inactive
or at a VIH level.
CAS Before RAS Refresh
This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR). This activates the internal refresh counter
which generates the address to be refreshed. Extemallyapplied
addresses are ignored during the automatic refresh cycle. If
the output buffer was off before the automatic refresh cycle,
the output will stay in the high impedance state. If the output
was enabled by CAS in the previous cycle, the data out will
be maintained during the automatic refresh cycle as long as
CAS is held active (hidden refresh).

NIBBLE MODE
Nibble mode allows high speed serial read, write, or readmodify-write access of 2, 3, or 4 bits of data. The bits of data
that may be accessed during nibble mode are determined by
the S row addresses and the S column addresses. The 2 bits
of addresses (CAS, RAS) are used to select 1 of the 4 nibble
bits for initial access. After the first bit is accessed by the
normal mode, the remaining nibble bits may be accessed by
toggling CAS "high" then "low" while RAS remains "low".
Toggling CAS causes RAS and CAS to be incremented internally while all other address bits are held constant and makes
the next nibble bit available for access.
If more than 4 bits are accessed during nibble mode, the
address sequence will begin to repeat. If any bit is written
during nibble mode, the new data will be read on any subsequent access. If the write operation is executed again on
subsequent access, the new data will be written into the selected cell location.

Hidden Refresh
The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing
a CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh operation of MCM6257B can be tested
by CAS before RAS refresh counter test. This cycle performs
read/write operation taking the internal counter address as
row address and the input address as column address.
The test is performed after a minimum of S CAS before RAS
cycles as initialization cycles. The test procedure is as follows.

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Therefore, to retain the
correct information, the bits need to be refreshed at least once
every 4 milliseconds. This is accomplished by sequentially cycling through the 256 row address locations every 4 milliseconds, (i.e., at least one row every 15.6 microseconds like the
64K dynamic RAM). A normal read or write operation to the
RAM will serve to refresh all the bits (1024) associated with
the particular rows decoded.

1.
2.

3.

Write a "0" into all memory cells.
Select any column address and read the "O"s written in
step 1. Write a "1" into each cell of the selected column
by performing CAS before RAS Refresh Counter Test
Read-Write Cycle (see timing diagram). Repeat 256 times.
Read the "l"s (use a normal read mode) written in step

2.
4.

RAS-Only Refresh
In this refresh method, the system must perform a RASonly cycle on 256 row addresses every 4 milliseconds. The
row addresses are latched in with the RAS clock, and the

5.

Select the same column address as step 2, read the "1 "s
and write a "0" into each cell by performing CAS before
RAS Refresh Counter Test Read-Write Cycle (see timing
diagram). Repeat 256 times.
Read the "O"s (use a normal read mode) written in step

4.
6.

Repeat steps 1 through 5 using complement data.

REFRESH CYCLE

Q -

HIGH Z

+---{

VAUD DATA.lJUT

Figure 1. Hidden Refresh Cycle

. MOTOROLA MEMORY DATA

2-25

IJ

MCM6257B

ORDERING INFORMATION
(Order by Full Part Number)
.MCM

62578

T_·_.'---·~T...J

Motorola Mem_o_ry_p_re_fix_ _ _ _ _ _
Part Number

-

X

XX

IL_T______
-

Spe8d(10=100ns. 12= 120ns. 15= lOOns)
Package (P = Plastic)

Full Part Numbers-MCM6257BP10
MCM62578P12
MCM6257BP15

MOTOROLA MEMORY DATA

2-26

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM41464A
Advance Information

64K X 4 Dynamic RAM
The MCM41464A is a 262,144 bit, high-speed, dynamic random access memory.
Organized as 66,536 words of 4 bits, and fabricated using N-channel silicon-gate MOS
technology, this new single + 5 volt supply dynamic RAM combines high performance
with low cost and improved reliability.
By multiplexing row and coluntn address inputs, the MCM41464A requires only eight
address lines and permits psckaging in standard lS-pin 3CXi mil wide dual-in-line packages.
Complete address dacoding is done on-chip with address latches incorporated.
All inputs and outputs, including clocks, are fully TTL compstible. The MCM41464A
incorporates a one transistor cell design and dynamic atoraga techniques.
The MCM41464A faatures "psge mode" which allows random column accessas of t
256 bits within the saIectad'row.
.
•
•
•

-PPACKAGE
PLASTIC
CASE 7111

PIN ASSIGNMENT

ii

Organized as 65,536 Words of 4 Bits
Single +5 Volt Operation (±10%1
Maximum Access TIma: MCM41464A-10=100 ns
MCM41464A-12 = 120 ns
MCM41464A-15= 1

001

• 256. Cycle, 4 ms Refresh
• ~ Before RAS Refresh Moda
• Hiddan Refresh
• RAS-Only Refresh Mode
• Page Mode Capability

i

4

RAS

5

18

Vss

17

DQ3

16

CAS

15

002

14

AD

A6

13

Al

A5

12

A2

A4

11

A3

YCC

10

A7

PIN NAMES
AG-A7 • . . . . . . . . • • Add""", Input
DQ()..DQ3 ••••••• Data Input/Output
G . . . . . . : . . . . . . . Output Enable
Vii. . . . . . . . . . . . Reed/Write Input
RAS . . . . . . . . Row Address Strobe
CAS . . . . . . Column Add""", Strobe
Vee •.•.......•• Power (+5 V)
VSS' ..•. .' ...•••••••. Ground

BLOCK DIAGRAM
i----------------- - - - - - - - - - - - - H I G H Z - - - - - - - - - -_ __

VoL------~

MOTOROLA MEMORY DATA
2-62

MCM511001A

HIDDEN REFRESH CYCLE (READ)

V!HRAS
V!L -

V!H~

V!L -

ADDRESSES

w
VDH -

n IDATA DUTI

----

HIDDEN REFRESH CYCLE (WRITE)

V!HRAS
V!L -

V!H-

CAS
V!L -

V!HADDRESSES
V!L -

V!H-

W
V!L -

V!H D IDATA !NI
V!L -

n IDATA OUTI

VDHH!GH Z
VOL -

MOTOROLA MEMORY DATA
2-63

MCM511001A

fI

CAS BEFORE

VIH~

------:01..

RAS REFRESH COUNTER TEST CYCLE

"'_---------IRAS--------_oi

RAS
Vll-

CAS

VIHVllVIH-

ADDRESSES
VllREAD CYCLE
VOH o (DATA Dun
VOlVIH -

iii
VllWRITE CYCLE
VOHo (DATA Dun
VOlVIH-

iii
Vil ""'
VIHD (DATA INI
VllREAD-WRITE CYCLE
VOHo (DATA Dun
VOl-

VIH-

iii
VllVIHD (DATA INI
VIL -

MOTOROLA MEMORY DATA
2-64

MCM511001A

DEVICE INITIALIZATION

Once the clocks hava becoma active, they must stay active
for the minimum (tRAS) period for the RAS clock and the
minimum (tCAS) period for the CAS clock. The RAS clock
must stay inactive for the minimum (tRP) time. The former is
for the completion of the cycle in progress, and the latter Is
for the device internal circuitry to be precharged for the next
active cycle.
Data out is not latched and is velid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the
write (W) input must be held at the VIH level from the time
the CAS clock makes its active transition (tRCS) to the time
when it transitions into the inactive (tRCH) mode.

On power-up an initial pausa of 200 microseconds is required
for the internal substrate generator pump to establish the correct bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize the
various dynamic nodes intemal to the device. During an extended inactive state of the device (greater than 4 millisaconds
with device powered up), the wake up sequence (8 active
cycles) will be necessary to assure proper device operation. '
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed
with two separate 10-bit address fields that are strobed at the
beginning of the memory cycle by two clocks (active negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of twenty address bits will decode one
of the 1,048,576 cell locations in the device. The column address strobe follows the row address strobe by a specified
minimum and maximum time called "tRCO:' which is the row
to column strobe delay. This time interval is also referred to
as the multiplex window which gives flexibility to a system
designer to set up his external addresses into the RAM. These
conditions have to be met for normal read or write cycles. This
initial portion of the cycle accomplishes the normal addressing
of the device. There are, however, two other variations in
addressing the 1M RAM, one is called the RAS only refresh
cycle (described later) where a 9-bit row address field is presented on the input pins and latched by the RAS clock. The
most significant bit on Row Address A9 is not required for
refresh. The other varietion, which is called nibble mode, allows the user to access 4 bits serially. (See NIBBLE MODE
section.)

WRITE CYCLE
A write cycle is similar to a read cycle except thet the Write
(W) clock must go active (VIL leval) at or before the CAS clock
goes active at a minimum twcs time. If the above condition
is met, then the cycle in progress is referred to as an early
write cycle. In an early write cycle, the write clock and the
data in are referenced to the active transition of the CAS clock
edge. There are two important parameters with respect to the
write cycle: the column strobe to write lead time (tCWL) and
the row strobe to write lead time (tRWL). These define the
minimum time that RAS and CAS clocks need to be active
after the write operation has started (W c,lock at VIL level).
It is also possible to perform a late write cycle. For this cycle
the write clock is activeted after the CAS goes low which is
beyond twcs minimum time. Thus the perameters tCWL and
tRWL must be satisfied before terminating this cycle. The
difference between an early write cycle and a late write cycle
is that in a late write cycle the write (W) clock can occur much
later in time with respect to the active transition of the CAS
clock. This time could be as long as 10 microseconds [tRWL +tRP+2trl.
At the start of an early write cycle, the date out is in a high
impedance condition and remains inactive throughout the
cycle. The data out remains threa-state because the active
transition of the write (W) clock prevents the CAS clock from
enabling the date-out buffers. The three-state condition (high
impedance) of the date out pin during a write cycle can be
effectively utilized in systems that have a common input/output bus. The only stipulation is thet the system use only early
write mode operations for all
cycles to avoid bus
contention.

READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, a read"while-write
cycle, and read-modify-write cycle which are covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL leval.
The CAS clock must also make a transition from VIH to the
VIL leval at the specified tRCO timing limits when the column
addresses are latched. Both the RAS and CAS clocks trigger
a sequence of events which are controlled by several delayed
internal clocks. Also, these clocks are linked in such a manner
that the access time of the device is independent of tha address
multiplex window. The only stipulation is that the CAS clock
must be activa before or at the tRCO maximum specification
for an access (date valid) from the RAS clock edge to be
guaranteed (tRAC). If the tRCO maximum condition is not
met, the access (tCAC) from the CAS clock active transition
will determine read access time. The external CAS signal is
ignored until an internal RAS signal is available. This gating
feature on the CAS clock will allow the external CAS signal
to become active as soon as the row address hold time (tRAH)
specification has been met and defines the tRCO minimum
specification. The time difference between tRCO minimum and
tRCO maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in
generating the CAS clock.

1Nrite

READ-MODIFY-WRITE AND READ-WHILE-WRITE
CYCLES
As the name implies, both a read and a write cycle are
accomplished at a selected bit during a single access. The
read-modify-write cycle is similar to the late write cycle discussed above.
For the read-modify-write cycle a normal read cycle is initiated with the write (W) clock at the VIH leval until the read
date occurs at the devica access time (tRAC). At this time the
write (W) clock is esserted. The date in is setup and held with
respect to the active edge of the write clock. The cycle described assumes a zero ,modify time between read and write.
Another variation of the read-modify-write cycle is the readplays an important
while-write cycle. For this cycle,

tcwo

MOTOROLA MEMORY
2-66

DATA

II

MCM511001A

fI

role. A reed-whDe-write cycle stans as a nonnal reed cycle
with the write (W) clock being aaeerted at minimum tCWD'
time, depending upon thti application. This results in starting
a write operation to the selected tell even before date out
occurs. The minimum specification on !CWo assures that date
out doas occur. In this case, the date in is sat up with respect
to write (W) clock active adge.
NIBBLE MODE
Nibble mode allows high speed serial reed, write, or readmodify-write access to 2, 3, or 4 bits of date. The bits of date
that may be acceaed during nibble mode are datermined by
the 9 row addresses and the 9 column addresses. The 2 bits
of addresses (CAS, RAe) are usad to select 1 of the 4 nibbla
bits for Initial access. After the first bit is acceaed bV the
normal mode, the remaining nibble bits may be accessed bV
toggllng.CAS "hlgh" then "Iow" while RAS remains "Iow".
Toggling CAS causes RA9 and CAS to be incremented internally while all other address bits are held constant and makes
the next nibble bit available for access.
If more than 4 bits are acceaed during nibble mode, the
address sequence wUl begin to repeat. If anv bit is written
during nibble mode, the nsw date will be reed on any subsequent access. If the write operstlon is executed again on
subsequent access, the n_ date will be written into the selected· call location.
REFRESH CYCLES
The dynamic RAM design'is besad on capacitor charge
storega for each bit in the arrey . This charga will tend to
degrade with time and temperstUre. Therefore, to rateln the
correct information, the bits need to be refreshed at least once
every 8 milliseconds. This is accomplished by sequentlallv cycling through the 612 row address locations every 8 mUIiseconds, (i.e., at least one row every 16.6 mlcroseconda). A
normal reed or write operation to the RAM will selVe to refresh
all the bits (2048) aasociated with the particular rows decoded.
RAS-Onlv Ref....h
In this refresh method, the system must parfonn a RASonlV cycle on ~12 row address8s every 8 milliseconda. The
row addresses ara latched in with the RA! clock, and the
associated intemal row locations ara rafra8had. As the heading
implies, the CAS clock is not required and must be' Inactive
or at a VIH level.

MEMORY CYCLE

o-

HIGH·Z -+-"--0(

CAS Before RAS Refresh
This refresh cycla is initiated when RAS falls, after CAS has
been low (bV tCSR). This activates the intemal refresh counter
which generates the address to be refreshed. Externally applied
addresses are ignored during the automatic refresh cycle. If
the output buffer was off before the automatic refresh cycla,
the output will stay in the high impedanCe state. If the output
was ensbled by CAS in the previous cycle, the date out will
be mainteined during the automatic refresh cycle as long as
CAS is held active (hidden refresh).
Hidden Refresh
The hidden refresh mathod allows refresh cycles to be perfonned while mainteining valid date at the output pin. Hidden
refresh is performed bV holding CAS at VIL and teking RAS
high and after a specified precharge period (tRP), el'8Cuting
a CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The intemal refresh counter of this device can be tested
with a CAS·before RAS ref....h counter test. This refresh
counter test is perfonned with a reed-write operation. During
this test, the internal refresh counter generates the row address, whUe the external address input supplies the column
address. The entire array is refreshad eftar 612 test cycles, as
indicated by the check date written in each row. See CAS
before RAS ref....h counter test cycle timing diagram. .
The test can be parformad onlV after a minimum of 8 CAS
before RAS initialization cycles. The test procedure Is as
follows:
1. Write "O"s into all memory cells (normal write mode).
2. Select a column eddress, read "0" out and write "1" into
the tell by performing CAS before RAS ref....h counter
test, read-write cyel•. Repeat this operstion 612 times.
3. Read "1"8 (normal ' read mode), which were written at
step 2.
4. Using the same column 88 in step 2, reed "1" out and
write "0" into the tell by perfonnlng CAS before RAS
refresh counter test. read-write cyel.. Repeat this
operation 612 times.
6. Read "O"a (normal read mode), which were written at
step 4.
6. Repeat steps 1 to 6 using complement date.

REFRESH· CYCLE

VALID OATA·OUT

Figure 1. Hidden Refresh Cvcle

MOTOROLA MEMORY DATA
2-66

REFRESH CYCLE

MCM511001A

TEST MODE

Test mode can be used in any timing cycle except nibble
mode cycles. The test mode function is enabled by holding
the "TF" pin on "supar voltage" for the specified period (tTES,
tTEHR, tTEHC; see TEST MODE CYCLEI.
"Super voltage" = VCC +4.5 V
where
4.5 V

- - - - - - - - - - - - - - - H I G H z - - -_ _ _ _ _ _ _ _ _ _ _.,...._ _

MOTOROLA MEMORY DATA
2-74

.

MCM511002A

READ-WRITE CYCLE

VIHRAS
VIL-

VIHADDRESSES
VIL-

VIH-

CS
VIL-

VIH-

Vi
VIL-

VIHo (DATA IN)
VIL-

VDHQ

IDATA OUT)
VDL-

STATIC COLUMN MODE READ CYCLE
....- - - - - - - - - - - I f t A S c - - - - - - - - - - - -..... ..r--~

----~.----~C---~~---

VIH-

COLUMN
ADDRESS

ADDRESSES

V I H - - - - + - - - - - - 4 -...

I-ol---+tcsc--....

..r--ohL

CS

VOHQ IDATA OUT)

-----HIGH

VALID
DATA

z------(I

vDL-

MOTOROLA MEMORY DATA
2-75

MCM511002A

II

STATIC COLUMN MODE WRITE CYCLE (EARLY WRITEI (AI
VIHRAS
VIL -

VIHADDRESSES
VIL -

VIH-

CS
VIL -

VIH-

W
VIL -

o IDATA INI

VIHVIL -

o IDATA DUTI

VDH----------------HI6HZ-----------------VOL -

STATIC COLUMN MODE WRITE CYCLE IEARLY WRITEIIBI

VIH-

HAS
VIl-

VIHADDRESSES
VIL-

VIH-

CS
VIL-

VIH-

W
VIl-

VIHD !DATA INI
VIl-

o IDATA Dun

VOHHI6HZ
VOL -

MOTOROLA MEMORY DATA
2-76

MCM511002A

STATIC COLUMN MODE READ-WRITE CYCLE

II

VIHRAS
VIL -

VIHADDRESSES
VIL -

VIH-

CS
VIL -

VIH-

W
VIL -

o (DATA IN)

VIHVIL -

VDH Q

(DATA OUT)
VOL -

STATIC COLUMN MODE READ/WRITE MIXED CYCLE

VIH-

iiAS
VIL-

YIH- ---f----,t. 14---

CS
VIL-

VIH----+-"\

i

VOHQ !DATA

OUT)

-------+-HIGH

Z---------~X

-.~---=r

VOL -

14----------~~----------~

MOTOROLA MEMORY DATA
2-n

........................., 1 " - - -.......

MCM511002A

II

RAS ONLY REFRESH CYCLE
(Wand A9 are Don't ~rel
1+-----------tRC:------------~

VIH- ----:~ 1"1---------

AD TO AS
VIL VOHOfDATA DUn

- - - - - - ' - - - - - - - - - HIGH Z - - - - - - - - - - - - - - -

CS BEFORE RAS REFRESH CYCLE
(Wand" AO to A9 are Don't Carel
t+--------tRC ----.,-------t00j
Jo:-----....,~ "'t-----tRAS-------..,~

J..._----.....L.

tCHR

--------..l-

VOH
o (DATA oun VOL - _ _ _ _ _....:If"

i}----------- HIGH Z - - - - - - - - - - - - -

MOTOROLA MEMORY DATA

2-78

MCM511002A

HIDDEN REFRESH CYCLE (READI .
f+------tRc;------_~------tRc--------~

VIH-

t + - - - - t R A S . - - - - - - . I #--~ 1+----tRAS;-----~

RAS
VIL i+---tCRP'------;.;
VIH-

cs

VIL -

VIHADDRESSES
VIL VIH -

W

VIL -

VOH a (DATA OUT)

- - - HIGH Z - - - - t - " ' \ I

VALID DATA

VOL -

HIDDEN REFRESH CYCLE (WRITEI

VIH-

m

VIL -

VIH-

cs

VIL -

VIHADDRESSES
VIL VIH-

W

o (DATA IN)

VOH a (DATA OUT)

HIGH Z
VOL -

MOTOROLA MEMORY OATA
2-79

II

MCM511002A

D

CS BEFORE RAS REFRESH COUNTER TEST CYCLE
I+----------IRAS----------~

~-------~~-------~~----~

VIH-----:!VIL -

cs

.J.-----.......&.. io4------tcs---_+! .Jo---t-t---------

VIHVIL VIH-

ADDRESSES

VIL READ CYClE

VOHQ IDATA Dun

---------

VOL -

WRITE CYCLE
ADDRESSES

VDHQ IDATA Dun

-----------

VOL -

VIL-~~~~~~~~~~~~~~-~~---------+__.~~~~~~~~

IDH-1

I

--l-J

Jr:-""":'VAL-ID-DAt-A

o IDATA IN)
READ-WRITE CYClE

ICAH

10""701...............1"...,.....,.....,.........,..--.

ADDRESSES

VOHQ IDATA Dun

-------

VOL -

VIH -..,.-or~'"lr~r_l!"""lr''"lr'l(''"'"l~~-X-~~~'"lrr''lr_7\

Jo---:=:--,"",,- .ft""l~r-x--X-"7r"7('""l~r-x~-,r'"

o IDATA IN)

MOTOROLA MEMORY DATA

2-80

MCM511002A

stay inactive for the minimum (tRPI time. The former is for
the complation of the cycle in progress, and the latter is for
the device internal circuitry to be precharged for the next active
cycle.
Data out is not latched and is valid as long as the CS clock
is active; the output will switch to the three·state mode when
the CS clock goes inactive. To perform a reed cycle, the write
(WI input must be held at the VIH level from the time the CS
clock makes its active transition (tRcsl to the time when it
transitions into the inactive (tRCH) mode.

DEVICE INITIALIZATION
On power·up an initial pause of 200 microseconds is required
for the internal substrate generator pump to establish the cor·
rect bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (clockl to initialize the
various dynamic nodes internal to the device. During an ex·
tended inactive state of the device (greater than 4 milliseconds
with device powered up), the wake up sequence (8 active
cycles) will be necessary to assure proper device operation.
ADDRESSING THE RAM

WRITE CYCLE

The ten address pins on the device are time multiplexed

~ write cycle is similar to a reed cycle except that the Write
(WI clock must go active (VIL level) at or before the CS clock
goes active at a minimum twcs time. If the above condition
is mat, then the cycle in progress is referred to as an early
write cycle. In an early write cycle, the write clock and the
data in are referenced to the active transition of the CS clock
edge. There are two important paramaters with reepect to the
write cycle: the column strobe to write lead time (tCWL) and
the row strobe to write lead time (tRwLI. These define the
minimum time thet RAS and CS clocks nead to be active after
the write operation has started (W clock at VIL level).
It is also possible to perform a late write cycle. For this cycle
the write clock is activated after the CS goes low which is
beyond twcs minimum time. Thus the paramaters tCWL and
tRWL must be satisfied before terminsting this cycle. The
difference between an early write cycle and a late write cycle
is that in a late write cycle the write (W) clock can occur much
later in time with reepect to the active transition of the CS
clock. This time could be as long as 10 microseconds ItRWL +tRP+ 2trl.
At the start of an early write cycle, the date out is in a high
impedance condition and remains inactive throughout the
cycle. The deta out remains three·state because the active
transition of the write (W) clock prevents the CS clock from
enabling the data·out buffers. The thre&--stete condition (high
impedance) of the date out pin during a write cycle can be
effactively utllized.in systems that have a common input/out·
put bus. The only stipulation is that the system use only early
write mode operations for all write cycles to, avoid bus
contention.

with two separate 1()"bit address fields that ara strobed at the
beginning of the memory cycle by two clocks (active negative)

row

called the
address strobe (RASI and chip select (CSI. A
total of twenty address bits will decode one of the 1,048,576
cell locations in the device. The column address strobe follows
the row address strobe by a specified minimum and maximum
time called "tRCD," which is the row to column strobe delay.
This time interval is also referred to as the multiplex window
which gives flexibility to a system designer to set up his external
addresses into the RAM. These conditions have to be met for
normal read or write cycles. This initial portion of the cycle
accomplishes the normal addressing of the device. There are,
however, two other variations in addressing the 1M RAM one
is called the RAS only refresh cycle (described later) ~re a
9--bit row address field is presented on the input pins and
latched by the RAS clock. The most sighificant bit on Row
Address A9 is not required for refresh. The other variation,
which is called static column mode, allows the user to column
access the 1024 bits within a selected row. (See STAnC COL·
UMN CYCLES section.)
READ CYCLE
A read cycle is referred to as a normal read cycle to differ·
entiate it from a pege mode read cycle, a read--whil&--write
cycle, and read·modify·write cycle which are covered in a later

section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level.
The CS clock must also make a transition from VIH to the VIL
level at the specified tRCD timing limits when the column
addresses are letched. Both the RAS and CS clocks trigger a
sequence of events which are controlled by several delayed
internal clocks. Also, these clocks are linked In such a rnanner
that the access time of the device is independent of the address
multiplex window. The only stipulation is that the CS clock
must be active before or at the tRCD maximum specification
for an access (data valid) from the RAS clock edge to be
guaranteed (tRAC). If the tRCD maximum condition is not
met, the access (tCAC) from the CS clock active transition
will datermine read access time. The external CS signal is
ignored untU an internal RAS 8ignal is available. This geting
feature on the CS clock wHl allow the external CS signal to
become active as soon as the row address hold time (tRAH)
specification has been mat and defines the tRCD minimum
specification. The time difference between tRCD minimum and
tRCD maximum can be used to absorb skew delays in switch·
ing the address bus from row to column addresses and in
generating the CS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the
minimum (tCS) period for the CS clock. The RAS clock must

READ-MODIFY·WRITE AND READ·WHILE·WRITE
CYCLES

As the name implies, both a reed and a write cycle are
accomplished at a selected bit during a single access. The
reed·modify-write cycle is similar to the late write cycle dis-cussad above.
For the read·modify-write cycle a normal read cycle is initiated with the write (W)clock at the VIH level until the read
deta oc...!:.urs at the device access time (fRAC). At this time the
write (W) clock is asserted. The data in is setup and held with
respect to the active edge of the write clock. The cycle d&-scribed assumes a zero modify time between read and write.
Another variation of the read·modify·write cycle is the read-whil&--write cycle. For this cycle, tCWD plays an important
role. A read--whil&-write cycle starts as a normal read cycle
with the write (W) clock being _rted at minimum tcwD
time, depending uPon the application. This results in starting
a write operation to the seIacted cell even before date out
occurs. The minimum specification on tCWD assures that data
out does ~r. In this case, the date in is set up with reepect
to write (WI clock active edge.

MOTOROLA MEMORY DATA
2~1

II

MCM511002A

II

STATIC COLUMN CYCLES

Hidd.n Rafreah,

Static'column operation allows fast successive data operations at the 1024 column locations within a row. Access time
is typical~ half the regular RAS clock access (t.B&;). Static
column operation is 'achieved by holding both RAS and CS
low, and selecting the column location detarmimici by the 10bit coIunin address field.
'
The static column cycle is always initiated with a row address
being provided and latched by tha RAS clOck, followed by a
column address and CS clock, as in a normsl read or write
cycle. Subsequent column addrasses are accessed at a highar
speed (tAA, tALW, tow, or tcAc, depending on the previous
and intended operation), as the' column eddresa field is
and read-write operations can be pei-changed. R8ad,
formed and mixed in any order when the device is in the atatic
COlumn mode.

The hidden refresh method allows refresh cycles to be perfanned while maintaining valid data at the output pin. Hidden
refresh is performed by hoId'mg CS at VIL and taking RAS
high and after a specified precharge period (lfIP), executing
a CS before RAS refresh cycle. (Sea Figure 1.)

CS BEFORE RAS REFRESH COUNTER TEST
The intemal refresh counter of this device can be tested
with a CS before RAS rafraah counter teet. This refresh
counter teat is performed with a read-write operation. During
this teat. the internal refresh counter ganarates the row eddress, while the axtetiIal address input supplias the column
address. The entire an8y is refreshed after 512 teat cycles, as
indicated by the ~ data written in each row. See CS
before RAS reiraah coilnter teet cYcle timing diagram.
The teat can be performed only after a minimum of 8 CS
before RAS iriitializ8tion cycles. The teat prooedure is as

wme,

REFRESH CYCLES

followa:

The dynamic RAM dasign is besed on capecitor charge
storage for each bit in the array. This charga will tend to
degrade with time and temperature., Therefolll, to retain the
correct informstion, the bits need to be refreshed at leaat once
every 8 milliseconds. T/1is is accomplished by sequentially cycling through the 512 row address locations every 8 !'lilliseconds, (i.e., at least one row every 15.6 microseconds). A
normal read or write operation to the RAM, will nifresh all the
bits (2048) aSS(ICiated with the perticular
decoded.

1.
2.

3.

step 2.

4.

row

RAi-Only Ref....h
In this refresh method, the system muat perform a RASonly cycle on 512 row addresses every 8 milliseconds. The
row addresses are latched in with the RAS clock, and the
associated intemal row locations are refreshed. As the heading
implies, the CS clock is not required and muat be inactive or
at a VIH level.

,CS Before RAS Ref....h
This refresh cycle is initiated when RAS falls, after CS has
'been low (by ttSR). This activates the internal refresh counter
which generates the row address to be refreshed. Extemally
applied addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will atay in the high impedance state. If the
output was enabled by CS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CS is hald active (hidden refreshl.

o-

HIGH·Z

Write "O"s'into all memory cella (normal write mode).
Select a column address, read "0" out and write '~1" into
the cell by performing CS before RAS rafraah counter
teet, read-write cycle. Repeat this operation 512 times.
Raad "1"s (normal read mode), which were written at

5.
6.

Using the same column 88 in slap 2, ..a.d "1" out and
"0" into the call byperfoiming CS before RAS
refresh counter teet, read-write cycle. Repeat tl)is
operation ,512 times.
'
Raad "0"8 (normal read mode), which were written at
&tap 4.
'
Repeat steps 1 to 5 using complement data.

write

TEST MODE
Internal organization of this device I256K x 4) allows it to be
tested as If it ware a 256Kx 1 DRAM. Only nine of the ten
addresses (AO-AS) are used in teat mode; AS is internally
dissbled. A teat mode write cycle writes data, D (data in), to
,a bit in each of the four 256K x 1 blocks (BO-83), in perallel.
A teat mode read cycle reads a bit in each of the four blocks.
If data is the same in all four bits, a (data out) is the same 88
the data in each bit. H data is not the same in all four bits, a
is high Z. See truth table and block ci"l8gram.
Test mode can be usild in any timing cycle, including page
mode cycles. The teat mode function Is enabled by holding

-+--0(
VALID DATA-DUT
~----~--------~--------Figure ,. Hidden R.f....h Cycl.,

MOTOROLA MEMORY
2-82

DATA

MCM511002A

the "TP' pin on "supervoltage" for the specifltld period ItrES,
trEHR, trEHC; - TEST MODE CYCLE).

Taat Mode Truth Table

"Super voItage"= VCC +4.5 V

D

10

I

11

I

B2

I

13

Q

0
1

0
1

I

0
1

I

0
1

I

0
1

0
1

-

4.6 V '"~~It"'7'''hr'''7'i~:'''?I:~_,r:""7'\"7'\7'\7'\'''~'''"r'''7'i:'''?l::r::I'\_,r:""7'\"A7'\7

Vil -

...Y..~...l!.....lL...lL....lL..r-lL....~"__l~'__lo~~~...JI....lt..~..lL....lL........lL...."'__'.......'__lo'_"'_"__"'_

I..

tDsl,,_ _ _ _ _

~---------HIGH

MOTOROLA MEMORY DATA
2-89

_"__"_...........

Z--------

MCM514256AeMCM51L4256A

II

WRITE CYCI,E Ii; CONTROLLED WRITEI

VIH-----~ ...- - - -

RAS

Vll-

VIHADDRESSES
Vll<-

VIH - "r"l~~"A'""lr''''A''''''''~~r''l~:"''IL

W

Vll-

.L..J"-lI~...lt.~loL.,;lL...l"-lo~...lt...::L.lL..IL...lH'--_ _ _+~IL...l"-lo~:..lL...lt.~~IL...l"-lo~:..lL..::L.lL...l<

VIH-~~~~~~~~~~----+~-~~~~~~~~~~~~~~~~~~-x-

Ii
Vil - ......,.............'-"-lL...................,

VIHDOO·D03
Vil ~

READ-MODIFY-WRITE CYCLE

VIHRAS
Vll-

VIHCAS
Vll-

VIH--IWHOX

..

MCM6064·MCM60L64

WRITE CYCLE 2 lEi E2 CONTROLLED)
Parameter

•

(See

Note 1)
Symbol

Write Cycle 11me

Ait
Symbol

MCM6064-10
MCM8OUI4-10

MCM6064-12
MCM801J14.12

Min

Min

tAVEll. tAVE2H

twc
tAS

100

Addl'8l8 Setup Time
Addl'8l8 Valid to End of Write

tAVE1H. tAVE2l

tAW

Chip Enable to End of Write

tEl.lE1H. tE2HE2l

tew

Data Valid to End of Write

tOVEl H- tOVE2l

tow

Data Hold 11me

tE1HOX. tE2l0X

tOH

80
80
40
0
0

tAVAV

Max

-

0

0

85
85

ns

-

ns
ns·

2
2
2.3
2
2.4
2.5

ns

-

50
0

-

Not_

-

120

-

Unit

Max

ns
ns .

-

Write Recovery11me
0
ns
tEl HAX. tE2LAX
twR
NOTES:
1. A write cycle atarts at the latest transition of a low Ei'. low W or high E2. A write cycle ends at tho earliest transition of a high Ei'. high
WorlowE2.
.
2. Ei' and E2 timings are identical when E2 signals are inverted.
3. If W goes low coincident with or prior to Ei' low or E2 high then the outputs win remain in a high impedance atate.
4. During this time the output pins may be in tho output atata. Signals of opposite ph... to·the outputs must not be applied at this time.
.
5. W must be high during an addl'8l8 transitions.

'"'14---------- IA V A V - - - - - - - - - - - - . _ ,
------~~I~
A (ADDRESSI
!r\___________________________J~lr---A
! - o 1 4 1 - - - - - - - - t AVE1H tAVE2L --------i_~,

I
I,..--~I~-----

,

IT (CHIP ENABLE)

't'-_____--Jl

!

I

I

E2 (CHIP ENABLE)

o (DATA IN)

.1..

IAVE1l
IAVE2H

.

I

{'-__
, ~:-----

I
)
----....;1--------',
I' 4

I

I

.1..

IE1lE1H
1£2HE2L

~X~XXXX""l'r7'r7'r7'rX~XX""l'r7'X~XXX~*XX~XX""""~X7'rXX~XX"'i\1

DATA VALID!

I+- tovElH

*XXXXXX
_I

IEIHDX
tovE2l
1£2LOX
Q{DATA OUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....:::HI:::GH.:.:.Z:...._ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MOTOROLA MEMORY DATA
3-12

_, ..

.I-I£IHAX
IE2lAX

MCM6064-MCM60L64

DATA RETENTION CHARACTERISTICS (TA=Oto +70oCI
Parameter

Symbol

Min

Typ

Max

VDR

2.0

-

5.5

VCC for Data Retantion (E"',VCC-0.2 V or E2s0.2 VI

Data Retantion Current (E1l!:VeC-0.2 or E2s0.2 VI

-

MCM6064: VCC=3.0 V
Vee =5.5 V
MCM60L64: VCC=3.0 V
VCe=5.5V

-

-

Chip Disable to Data Retantion Time

V
p.A

ICeDR

Operation Recovery Time

Unit

tCDR

0

tree

tAVAV*

-

50
100
15
30

-

ns

-

ns

*tAVAV = Read Cycle Time

! 4 - - - - DATA RETENTION MODE ----10.1

Vee

VDRl!:2.0 V

IT CONTROL

E2 CONTROL

~~~L~~=J------~E;;;.2;;;S;;;.O;;;..2,,;,V-------C:":"LLL.L....L:"'L

ORDERING INFORMATION
(Order by Full Part Number)

T--'CM -

Motorola Memory Prefix _ _ _ _ _ _ _
Part Number
(With L = Low Power Version)

r~

CSpeed
x

XX

.

Full Part Numbers-MCM6064Pl0
MCM6064P12

Package (P = Plastic)

MCM60L64Pl0
MCM60L64P12

MOTOROLA MEMORY DATA
3-13

(10=100 ns, 12=120 n5)

..

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM60256A
MCM60L256A

Advance Information

..

32K X 8 Bit CMOS Static Random
Access Memory
The MCM60256A is a 262,144 bit low-powar static random accaas memory organized as
32,768 words of 8 bits, fabricated using silicon-gate CMOS technology. Static design
eliminates the need forextemal clocks or timing strobes, while CMOS circuitry reduces
powar consumption and provides greater reliability. The operating current is 5 mA/MHz
(typl and the minimum cycle time is 85 ns.
Chip enable (EI controls the power-down festure. It is not a clock but rather a chip
control that affecte powar consumption. When E is a logic high, the pert is placad in low
power standby mode. The maximum standby current for MCMeOL256A is 2 pA.
(TA =25°CI. Chip enable also controis the data retention mode; Another control
feature, output enable fG) allows accaes to the memory contents as fast as 45 ns
(MCM60256A-85). Thus the MCM60256A is suiteble for usa in various microprocassor
application systams where high speed, low powar, and battery backup are required.
The MCM60256A is offered in a 600 mil,'28 pin plaatic dual-in-line package as well as
the 330 mil, 28 pin plastic small outline gullwing package.
•
•
•
•
•
•
•
•
•
•

".-..
SOG
CASE 7&1H

PIN ASSIGNMENT

Single 5 V Supply, ± 10%
32K x 8 Organization
Fully Static - No Clock or TIming Strobes Necessary
Low Power Dlssipation-27.5 mW/MHz (Typical Active)
Output Enable and Chip Enable Inputs for More Systam Design Flexibility and Low
Power Stendby Mode
Battery 8ackup Capability (MCM60L256A)
Data Retention Supply Voltage = 2.0 V to 5.5 V
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Accass TImes: MCM60256A-85 and MCM60L256A-85=85 ns (Max)
MCM60256A-10 and MCMeOL256A-10= 100 ns (Max)
MCM60256A-12 and MCM60L256A-12 = 120 ns (Max)
MSB

A5

A14
A7

A7
A14
A13

-Vee
MEMORY ARRAY
(512 ROWS AND
512 COLUMNS)

-Vss

AB

W

26

A13

25

A8

A5

5

24

A9

7

23

All

22

G

A2

21

AID

Al

20

E
007

AD

10

19

000

11

18

OOB

001

12

17

005

002

13

lB

004

VSS

14

15

003

pIN NAMES

A9

LSB

Vee

21
4

A3

BLOCK DIAGRAM

28

AB
A4

A6
A12

,.

A12

AO-AI4 . . . . . . . . . . . . Address

All

iii . . . . . . . . . . . .

Write Enable

E. . . . . . . , . . . . . . Chip Enable
13 . . . . . . . . . . . Output Enable

DOD
007

OQO-OQ7 . . . . . Oata Input/Output
V CC. • . . . . • + 5 V Power Supply
VSS . . . . . . . . . • . • . . Ground

i
6---<1.-/

This document contains information on a new product. Specifications and information herein are subject to charfge without notice.

MOTOROLA MEMORY DATA
3-14

MCM60256AeMCM60l256A

TRUTH TABLE

E

G

W

Mode

H

X

X

Not Selected

L

H

H

L

L

H

L

X

L

Supply C';rrent

I/O Pin

ISB

High Z

Output Disabled

ICC

High Z

Read

ICC

Dout

Write

ICC

Din

This device contains circuitry to protect the

inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than

maximum rated voltages to this highimpedance circuit.

II

X=don't care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Power Supply Voltage
Voltage to Any Pin with Respect to VSS
Power Dissipation (TA=25°CI
Operating Temperature
Storage Temperature

Value

Unit
V

VCC

-0.3 to 7.0

Yin' Vout

-0.5 to VCC+0.5

V

Po

1.0

W

TA

Oto+70

°C

Tstg

-55 to +150

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 70o C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Rangel

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.3*

-

0.8

V

Symbol

Min

*VIL (m,nl = - 0.3 V de; VIL (minI = - 3.0 V ac (pulse width '" 60 nsl
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin=O to VCCI

Ilkalll

Output Leakage Current (E=VIH or ~=VIH or W=VIL, Vout=O to VCCI

Ilka(OI

Operating Current (Read Cyclel
fE=VIL, W=VIH, Other Input=VIHIVIL, 10ut=0 mAl
MCM60256A, MCM60I.256A: tAVAV= 1 p.S
MCM60256A, MCM60L256A-85: tAVAV=85 ns
MCM60256A, MCM6OI.256A-l0: tAVAV= 100 ns
MCM60256A, MCM60L256A-12: tAVAV=I20 ns

ICCAI

(E=0.2 V, W=VCC-0.2 V, Other Input=Vcc-0.2 V/0.2 V,
10ut=0 mAl
MCM60256A, MCM60I.256A: tAVAV= 1 p.S
MCM60256A, MCM60L256A-85: tAVAV=85 ns
MCM60256A, MCM60L256A-l0: tAVAV=loo ns
MCM60256A, MCM60I.256A-12: tAVAV=I20 ns

ICCA2

Standby Current (E=VIHI

-

Max

Unit

±1.0

p.A

<0.01

±1.0

p.A
mA

-

-

ISBI

Typ
<0.01

-

10

5

-

-

-

70
70
70

60
60
60

-

3.0

mA

2

100
30
2

p.A

Output Low Voltage (lOL =4.0 mAl

VOL

-

V

VOH

2.4

-

0.4

Output High Voltage (lOH = -1.0 mAl

-

V

Symbol

Min

Max

Unit

Cin

-

10

pF

ClIO

-

10

pF

Standby Current (E"VCC-0.2 V. VCC=2.0 to 5.5 VI

MCM60256A
MCM60L256A
MCM60L256A (TA=25°CI

ISB2

-

Typical values are referenced to TA=25°C and VCC=5.0 V
CAPACITANCE (f -1
- MHz TA -- 25°C Periodically Sampled Rather Than 100% Tastedl
Characteristic
Input Capacitance (Vin=O VI

All Inputs Except DO

I/O Capacitance (VI/O = 0 VI

DO

MOTOROLA MEMORY DATA
3-15

MCM60256A-MCM60L256A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA=O to 70°C, Unless Otherwise Noted)

•

Output Timing Measurement Reference Levels .•••. 0.8 and 2.2 V
OutpUt Load. • . . • • • • : • • • . . • . . . • • • • • • . See Figure 1

Input Pulse Levels . . • .. • . . . • . . . • • • . • • • • • 0.6 V, 2.4 V
Input Rise/Fall Time: . . . • • • • • . . . • • . • • • • • • • • • • 5 no
Input Timing Measurement Reference Levels. • . • • . . • •• 1.5 V

READ CYCLE ISee Note 1)
Symbol

""rameter

MCM802IiIIA.a;
MCM6OI.2Ii8A.a;

Alt
Symbol

Min

MCM802IiIIA-l0
MCM80UIi6A-l0

Max

Min

85

-

100·

-

85

Read Cycle Time

tAVAV

tRC

Addreas Access Time

tAVQV

tAA

E Access Time

tELQV

tAC

G Access Time

IGLQV

taE

Output Hold from Address Change

tAXQX

tOH

-5

-

85
45·

-

-

·10

MCM802IiIIA-.12
MCM80UIi6A-12

Max

Min

-

120

100

-

100

50

-

10

Unit

Notes

-

Max

-

no

120

ns

120

ns

60

no

-

ns

2,3

Chip Enable to Output Low-Z

tELQX

tell

·10

tall

5

-

5

5

-

ns

IGLQX

-

10

Output Enable to Output Low-Z

no

2,3

Chip Enable to Output High-Z

tEHQZ

tCHZ

0

30

0

50

0

60

ns

2,3

OutpUt Enable to Output High-Z

tGHQZ

tOHZ

0

30

0

40

0

50

ns

2,3

10

NOTES:
1. Vii is high at all times for reed cycles.
2. All high-Z and Iow-Z parameters are considered in a high or low impedance stele when the 0U!l?ut .has made a 500 mV t,,!nsition from the
previous steady stele voltage.
3. These parameters are periodically sampled and not 100% tested.

~:~~~~~~~~~~~~~~~~~-t-A~-AV--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_~_~_.

t"'-....----tAvOV------I;~!

A IADDRESSI _ _ _ _
·

EICHIP ENABLE)
..

'ELOV----....

G(OUTPUT ENABLE)
_tGLOV---.j

o (DATA OUT) _ _....;;;HI,;;;GH.;,;.Z::....._ _-I...._+-___-"

4

4.5

7.5

5.5
6.5
VCC. SUPf'lY VOLTAGE IVOLTSI

Figure 1. Input High Voltage versus Supply Voltage

4

./

/

/"

4.5

~

V-

-

5.5
6
8.5
Vcc, SUPPLY VOLTAGE IVOLTSI

7.5

Figura 2. Input Low Voltage versus Supply Voltage

1.6
is

~

1.4

:IE
co

'"

...i!£a;
:::>
'"'"
.,
'"i!!

1.2

~

0.8

C

0.6

co

--

- t---

-

1.0

1l
0.4
-80

-40

-20

o 20 40 60 80
TA, AMBIENT TEMPERATURE (OCI

100

120

Figura 3. Operating Current versus Ambient
Temperature

100

I

10

'"

co

i!£

!5

1

'"
:::>
.,
'"

-

lii

Ii!

~
N
'"
.It'

j
o

-60

-40

1

-20

20
40
60
80
TA, AMBIENT TEMPERATURE (OCI

100

120

O. 1

0.0 1
-60 -40 -20

20
40
80
80
TA, AMBIENT TEMPERATURE (OCI

100

120 140

Figure 5. IS82 Standby Current versus Ambient
Temperature

Figure 4. IS81 Standby Current versus Ambient
Temperature

MOTOROLA MEMORY DATA
3-19

•

MCM60256A-MCM60L256A

1.6

I
l§

~

II

1.6

1.4

!

"

1.2

i!!i

0.8

z

0.6

..'"

1.2

i

..'"

0.8

E

0.6

i'"

1.0

.~ 0.4

~

15

"..

~ 0.2

f.-""

......

",""""

~

=>

CD

j

f.-"" i-"""

1.4

i

1.0

~~

0.4

1-

co

~ 0.2

-

,./

.....

f-- V

Jil

Jil

o
o

4

10

o
o

12

4

I. FREQUENCY IIIHzI

10

12

I. FREQUENCY IIIIIzl

Figure 7. Operating Current versus Frequency !Writal

Figure 8. Operating Current versus Frequency CReadl

1.8

~ 1.4

I

TA=25°C

,.,.,

1.2

IIii

0.8

~

0.4

j

0.2

,...,....,

1.0

0:6

/

",

"..

V
-~

o
2

2.5

3.5
4
4.5
VCe. SUPPLY VOLTAGE IVOlTSI

5.5

Figure 8. IS82 Standby Current varsus Supply Voltage

I
!

I
e

!
iii

J

1.8

1.5

::43
1.2

1.If-,

1.0

-

0.9

O. 7
4.5

4.75

5.25

--

-

0.8
5.5

0.8
-80

-40

VCe. SUPPLY VOLTAGE (VOLTSI

~

-20

~

20

-40

V

80

80

100

~

120

TA. AMBIENT TEMPERATURE lOCI

Figure 9. Acc_ Time versus Supply Voltage

Figure 10. Acc_ Tlma versuS Ambient Temperature

MOTOROLA MEMORY DATA
3-20

MCM802ti8A. MCM60L256A

r- 1

ORDERING INFORMATION

(Order by Full Part Number)

x

CM

T...J

Motorola MelTlOfY prefix _ _ _ _ _ _
Part Number
(With L= Low Power Version)

--

XX

T ...... ,.-.. ~.lO='OO~.
12=120 ns)

.

Package (P= Plastic DIP,
F=SOGI

Full Part Numbers-MCM60256AP85
MCM60256AP10
MCM60256AP12
MCM60256AF86
MCM60256AF10
MCM60256AF12

MCM60L.256AP85
MCM60L.256AP10
MCM60L.256AP12
MCM60L.256AF86
MCM60L.256AF10
MCM60L.256AF12

MOTOROLA MEMORY DATA
3-21

II

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

IMCM60256APC I

Advance Information

•

32K X 8 Bit CMOS Static Random
Access Memory
Industrial Temperature Range: - 40 to 85°C
The MCM60266APC is a 262,144 bit low-power static random access memory organized
as 32,768 words of 8 bits, fabricatsd using silicon-gats CMOS tschnology. Static design
eliminates the need for extemal clocks or timing strobes, while CMOS circuitry reduces
power consumption and provides greater reliability. The operating current is 6 mA/MHz
(typ) and the cycle time is 100 ns.
Chip enable (E) controls the power-down feature. It is not a clock ,but rather a chip
control that affects power consumption. When E is a logic high, the part is placed in low
power standby mode. The maximum standby current is 2 pA (TA=26°C). Chip enable
also controls the dats retention mode. Another control feature, output enable (6) allows
access to the memory contents as fast as 50 ns. Thus the MCM60266APC is suitable for
use in various microprocessor application systems where high speed, low power, and
battary backup are required.
The MCM60266APC is offered in a 600 mil, 28 pin plastic dual-in-line packsge.
•
•
•
•
•
•
•
•
•
•

PIN ASSIGNMENT

Single 5 V Supply, ± 10%
32K x 8 Organizetion
Fully Static - No Clock or Timing Strobes Necessary
Low Power Dissipation-27.6 mW/MHz (Typical Active)
Output Enable and Chip Enable Inputa for Mora System Design Flexibility and Low
Power Standby Mode
Battery Backup Capability (Maximum Standby Current =2 pA @ 26°C)
Data Retantion Supply Voltage =2.0 V to 5.6 V
All Inputs and Outputs Are TTL Compatible
Three Stata Outputs
Fast Access Time: MCM60266APC10 = 100 ns (Max)

AI4

1.

2B

Vee

AI2

2

27

W

A7

3

2B

A13

AB

4

25

AB

A5

5

24

AS

A4

B

23

All

A3

7

22

G

A2

B

21

AID

Al

S

20

E

AD

10

19

000

11

lB

on7
onB

Onl [ 12

17

0D5

0D2 [ 13

lB ~ on4

Vss [

15 ~ 0D3

14

BLOCK DIAGRAM

MSB

A5

PIN NAMES

A6

AO-A14 • . . • . . • • • • . • • • Address

A7
A12
A14
A13

ROW

MEMORY ARRAY
1512 ROWS AND
512 COlUMNS)

-Vee
-Vss

W . . . . . . . . . . . . . . Write Enable
'E. . . . . . . . . . . . . . . . Chip Enable

~ .. .. .. .. .. ... Output Enable
OQO-OQ7 ••.•••• Oats Input/Output
VCC .•••..•.• +6 V Power Supplv
VSS . • . . . . • . • • • . . • . • Ground

AB
AS

LSB

All
000
007

(. .1'_-_. .
W
ii----dL......l

This document contains information on • new product. Specifications and Information herein are subject to charfge without notice.

MOTOROLA MEMORY DATA
3-22

MCM60256APC

TRUTH TABLE
E

II

W

Mode

Supply Currant

I/O Pin

H

X

X

ISB

L

H

H

Not Salectad
Output Disabled

High Z

ICC

HighZ

L

L

H

Read

ICC

Dout

L

X

L

Write

ICC

Din

This device contains circuitry to protect tha
inputs against damage due to high static
voltages or electric fields; however, it is adviaad that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpadance circuit.

X=don't cara

ABSOLUTE MAXIMUM RATINGS (S.. Note)
Rating

Symbol

Power Supply Voltage
Voltaga to Any Pin with Respect to VSS

Value

Unit

VCC

-0.3 to 7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Power Dissipation (TA = 25'C) _

Po

1.0

W

Oparating Temparatura

TA

-40 toB5

·C

Storage Temperatura

TS!II

-55 to +150

·C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ara
exceedad. Functional oparation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposura to higher than recommended voltages for
extended pariods of time could affect device raliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±lO%, TA= -40 to 85°C. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.6

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.3*

O.B

V

Symbol

Min

Param_

-

*VIL (min) = -0.3 V dc; VIL (min) = -3.0 V ac (pulse width :$50 ns)

DC CHARACTERISTICS
Paramater
Input Leakage Currant (AU Inputs. Vin=O to VCC)

lucaUl

Output Leakage Currant (E=VIH or "G=VIH or W=VIL, Vout=O to VCC)

IHea(O)

Operating Currant (Reed Cycle)
(E=VIL, W=VIH, Other Input=VIHIVIL, 10ut=0 mAl

ICCAI
tAVOV=1 pJJ
tAVOV=loo na

(E=0.2 V, W=VCC-0.2 V, Other Input=Vcc-0.2 V/0.2 V,
lout=OmA)
tAVOV=1 pJJ
tAVOV=loo ns

ICCA2

-

Typ

Max

Unit

<0.01

±1.0

<0.01

±1.0

,.A
,.A

10

-

5

mA

70

-

Output Low Voltage (lOL =4.0 mAl

VOL

-

Output High Voltage (lOH = -1.0 mAl

VOH

2.4

2
-

Symbol

Min

Max

Unit

-

10

pF

10

pF

Standby Currant (E = VIH)

ISBI

Standby Currant (E~VCC-0.2 V, VCC=2.0 to 5.5 V)

ISB2
(TA=25'C)

-

60

3.0

mA

100
2

,.A

0.4

V

-

V

Typical values ara referanced to TA = 25°C and VCC = 5.0 V

CAPACITANCE (f= 1 MHz TA =25'C Periodically Sampled Rather Than 100% Tested)
Cheracterlatlc
Input Capacitance (Vin = 0 V)

All Inputs Except DO

Cin-

110 Capacitance (VIIO=O V)

DO

CliO

MOTOROLA MEMORY DATA
3-23

..

MCM60256APC

AC OPERATING CONDITIONS AND CHARACTERISTICS

!Vee =5.0 v ± 10%, TA = -40 to 85oe, Unless Otherwise Noted)
Output TIming Measurement Reference Levels '.' •.• 0.8 and 2.2 V
Output Load. • • . • • . • . • • • .... • • • • • . • . • • • See Fogure 1

Input Pulse Le\iels ••.•••••••••••••••••• 0.6 V. 2.4 V
Input Rise/FaIl TIme •.•••••.•••.•.•.•••.••••• 5 ns
Input TIming M888uremsnt Refarence Levels. . • • • • . . • • 1.6 V

•

READ CYCLE (See Note 1)
Param_.

Symbol

AIt
Symbol

Min

Max

Unit

100

Read Cycle TIIII8

tAVAV

tRC

Add.... Access TIme

tAVQV

tAA

tELQV

tAC

~ Accees Time

lGLQV

toE

-

Output Hold from Address Change

tAXQX

toH

10

Chip Enable to Output Low-Z

tELQX

tell

10

Output Enable to Output Low-Z

tGLQX

toll

5

r Accees TIme

Chip Enable to Output HIgh-Z

teHQZ

tcHZ

0

OutpUt Enable to Output High-Z

lGHQZ .

toHZ

0

-

ns

100

ns

100

ns

60

ns

-

n8

60
40

n8
ns
ns

na

111-

-

...,

2,3
2.3
2.3
2,3

NOTES:
1. W Is high at all times for read cycles.
2. All high·Z and Iow-Z paramstere 818 conaiderad in

8 high or low Irnpac!ance &tate when the output haa made a 100 mV transition from the
previous steady &tate voltage.
'
.
3. Thees paramaterll ara pariodicallv aampled and not 100% taatad.

~

---------_'AVAV

----------

A{AD{IIIESSI _ _ _ _ _ _ _~-----------

..------IAVQV-----~""
E{CliP ENABLEI
~---l£lOV---......

ii (OUTPI/T ENABLEI

+_-t----(J

Q IDATA IHITI _ _..;HI;::G:;;H.,;:.Z_ _ _

DATA VAUD

1'-~'-JJ

'ELOX5.0 V

TEST POINT

o-_~....,~--+

2.~

100 pF*

*Includes jig capacitance.

k

lN9148
OR EOUiV.

~

Figure 1. AC Teat Lo8d

MOTOROLA MEMORY DATA
3-24

HlGH-Z

MCM60256APC

WRITE CYCLE 1 AND 2 ISee Note 1)
Parameter
Write Cycle Time

Symbol

Alt
Symbol

Min

Max

Unit

Not..

-

ns

-

tAVAV

twc

100

Address Setup Time

tAVWL/tAVEL

tAS

0

Address Valid to End of Write

tAVWH/tAVEH

tAW

95

twLWH

twp

70

Data Valid to End of Write

tOVWH/tOVEH

tow

40

Data Hold TIme

Write Pulse Width

-

twHOX/tEHOX

tOH

0

-

Write Low to Output in High-Z

twLOZ

twHZ

0

60

Write High to Output Low-Z

twHOX

twLZ

10

twHAX/tEHAX

twR

tELWH/tELEH

tcw

5
90

Write Recovery Time
Chip Enable to End of Write

-

ns
ns
ns
ns
ns

2

-

ns

3,4
3,4

ns

5

ns

-

ns

NOTES:
1. Outputs are in high impedance state if "G is high during Write Cycle.
2. A write occurs during the overlap Itwp) of 8 low E and a low W. If Wgoes low prior to E low then outputs will remain in a high impedance
state.
3. All high-Z and Iow-Z parameters are considered in a high or low impedance suite when the outputs have made a 100 mV transition from
the previous steady state volta\le.
4. These parameters are periodically sempled and not 100% tested.
5. twR is measured from the earlier of E or W going high to the end of write cycle.

WRITE CYCLE 1

IW CONTROLLED)

A IADDRESSI

EICIIP ENABlEI

i iWRlTE ENABlEI

o IDATA INI

D IDATA DUn

---=.;..;..---<.

MOTOROLA MEMORY DATA
3-25

•

MCM60256APC

WRITE CYCLE 2 (e Controlled)
tAVAV
A IADDRESS)

•

'l

)~

J\.
~tAVEL

I£HAX-

tELEH
tAVEH

E(CHIP ENABLE)

J

'l

twLWH

W(WRITE ENABLE)

Q (DATA

}//////

\\\\\\\\\\\.

DUT)

HIGH IIII'EDANCE

HIGH IMPEDANCE

i=-

o (DATA IN)

I

IEHDX

I

DATA VAUD

DATA RETENTION CHARACTERISTICS (TA -- -40 to 85°C)
Parameter

Symbol

Min

VDR

2.0

Vec for Data Retention (E;;ovCC-0.2 V)
Data Retention Current (E;;oVCC-0.2 V)

VCC=3.0V
VCC=5.6V

-

ICCDR

Chip Disable to Data Ratantion Time

-

tcDR

0

trac

tAVAV*

Opsration Recovery Time

Typ

-

Max

Unit

6.5

V

60
10D

pA

-

-

ns

ns

*tAVAV = Read Cycle Time

DATA RETENTION MODE

~

~""I----

i:~~'

,-IZZ/f.. \

DATA RETENTIIlN MODE

---+j

...... ~:

....-'"

. 14\\\\\

NOTE: If the VIH of E is 2.4 V in opsration, IS81 currant flows during the period that the VCC voltage is decreasing from 4.6 V to 2.4 V.

ORDERING INFORMATION
(Order by Full Part Number)

T-'CM

Motorola Memory Prefix _ _ _ _ _ _ _
Part Number

T

x

X

XX

T ~Speed(10=100nS)

~operating
Temperature Range
(C = Industrial Range, -40 to 86°C)

-

'---------Package (P = Plastic)
Full Part Number-MCM60256APC10

MOTOROLA MEMORY DATA
3-26

CMOS Fast Static RAMs

MCM1423
MCM6164,
MCM61L64
MCM6164C
MCM6168
MCM6205-20
MCM6206
MCM6206-20
MCM6207
MCM6208
MCM6209
MCM6226-30
MCM6228-25
MCM6264
MCM6264-25
MCM6268
MCM6268-20
MCM6269
MCM6270
MCM6287
MCM6287-15
MCM6287-20
MCM6288
MCM6288-15
MCM6288-20
MCM6290
MCM6290-15
MCM6290-20

4K x 4, 40 ns, Equivalent to IMS1423 ........................
8K x 8, 45/55 ns, E1, E2, and G Inputs . . . . . . . . . . . . . . . . . . . . . ..
8K x 8, 45/55 ns, Lower Power .............................
8Kx8, 55/70 ns, -40 to 85°C ..............................
4K x 4, 45/55/70 ns •......................................
32K x 9, 20/25 ns, Output Enable ...........................
32K x 8, 35/45 ns, Output Enable •..........................
32K x 8, 20/25 ns, Output Enable ........................•..
256K x 1, 20/25 ns, Separate Input and Output Pins ...........
64Kx4, 20/25 ns .........................................
64K x 4, 20/25 ns, Output Enable ...........................
128K x 8, 30 ns, Output Enable ................•............
256K x 4, 25 ns, Output Enable •.•..........................
8Kx8, 30/35/45/55 ns, Output Enable ...............•...•...
8K x 8, 25 ns, Output Enable ...............................
4Kx4, 25/35/45/55 ns ....................................
4Kx4,20 ns .............................................
4K x 4, 25/35 ns, Fast Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . ..
4K x 4, 20/25/35 ns, Output Enable .........................
64Kx 1,25/35 ns, Separate Input and Output Pins ............
64K x 1, 15 ns, Separate Input and Output Pins ...............
64K x 1, 20 ns, Separate Input and Output Pins ...............
16K x 4, 25/30/35/45 ns ...................................
16K x 4, 15 ns ............................................
16K x 4, 20 ns ......................•...........•.........
16Kx4, 25/30/35/45 ns, Output Enable .....................
16K x 4, 15 ns, Output Enable ......................•..•...•
16K x 4, 20 ns, Output Enable ..............................

MOTOROLA MEMORY DATA
4-1

4-3
4-8
4-8
4-16
4-24
4-29
4-30
4-35
4-36
4-41
4-41
4-46
4-47

4-48
4-53
4-58
4-63
4-58
4-68
4-73
4-81
4-81
4-86
4-91
4-96
4-86
4-91
4-96

II

CMOS Static RAMs
I +5 V, 0 to 700 C unless otherwise noted)
Organization

Part Number

4Kx4

II
8Kx8

18Kx4

MCMfI268P20
MCMfI268P25
MCMfI268P36
MCMfI268P46
MCMfI268P66
MCM6289P25
MCM62S9P36
MCM6270P20
MCM6270P25
MCM6270P35
MCM627OJ20
MCM627OJ25
MCM627OJ35
MCM6164C46
MCM6164C65
MCM61L64C46
MCM61L64C66
MCM6164CC65
MCM6164CC70
MCM6264P26*
MCM6264P30
MCM6264P36
MCM6264P46
MCM6264P56
MCM6264J25*
MCM6264J30
MCM6284J36
MCMQ64J46
MCM6:l64J56
MCMfI268P15*
MCMfI268P20*
MCMfI268P26
MCM6288P30
MCM62S8P35
MCMfI268P46
MCM6280P16*
MCM6280P20*
MCM6290P26
MCM6280P30
MCM6280P36
MCM6290P46
MCM629OJ15*
MCM629OJ20*
MCM6290J25
MCM629OJ30
MCM629OJ36
MCM6290J46

(1l
(1l

25
35
20
25
35'
20
25
35
46
65
46
56

121
121

(31
{3I

{31
{31
{31
(31
{31
{31
(31
{31
(31
{31

56
70

26
30
35
46
65
26
30
35
36
65
15
20
25
30
36
46
15
20
26
30
35
46
16
20
25
30
36
46

PI""

Organization

20
20
20
20
20
20
20
20
20
20
20
20

64Kx1

32Kx8

22
22
22
24

32Kx9

24
24

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

64Kx4

256Kx1

128Kx8

22
22
22
22
22
22

266Kx4

Part Number

AccMsTime
In. maxi

MCM8287P15
MCM8287P20
MCM8287P25
MCM8287P35
MCM8287J15
MCM8287J20
MCM8287J26
MCM8287J35
MCM8206P20*
MCM6206P25*
MCM6206P35*
MCM8206P46*
MCM6206J20*
MCM6206J25*
MCM6206J35*
MCM6Z06J46*
MCM6205P20*
MCM6205P25*
MCM6205J20*
MCM6205J25*
MCM8206P20*
MCM8206P26*
MCM6Z06J20*
MCM6Z06J25*

15
20
25
35
15
20
25
35
20
25
35
46
20
25
35
46
20
25
20
25
20
25
20
25

MCM8209P20*
MCM8209P25*
MCM6209J20*
MCM6209J25*
MCM6207P20*
MCM6207P26*
MCM6207J20*
MCM6207J26*
MCM6228P30*
MCM6228J30*
MCM6228P25*
MCM6228J25*

20
25
20
26
20
25
20

*To be introduced
(1 I Feat dlip select )f8raion
(2) Industrial temperature range, - 40 to 86°C
(31 OutpUt enable verSion

24
24

24
24
24
24
24
24
24
24

24
24

MOTOROLA MEMORY DATA
4-2

PI""
22
22
22
22

24
24
24
24

28
28
28
28
28
28
28
28
32
32
32
32
24
24

24
24
28
28
28
28
24

26

24
24
24

30
30
26
26

32
32
28
28

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM1423*

4K X 4 Bit Static Random Access
Memory

-

The MCM1423 is a 16,384-bit static random access memory organized as 4096
words of 4 bits, fabricated using Motorola's second-generation high-performance silicon-gate CMOS (HCMOS III),technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption,
provides greater reliability, and provides protection against soft errors caused by alpha particles. Fast access time makes this device suitable for cache and other sub50 ns applications, especially those requiring just a little faster address access time
(40ns).
The chip enable (E) pin is not a clock. In less than a eycl!! time after E goes high,
the part enters a low-power standby mode, remaining in that state until E goes low
again. This feature reduces system power requirements without degrading access
performance.
The MCMI423 is available in a
JEDEC standard pinout.
•
•
•
•
•

•

300 mil, 20 pin plastic dual in-line packa

1

P PACKAGE
PLASTIC
CASE 738

~
.

Single 5 V Supply, ± 10%
4K x 4 Bit Organization
Fully Static-No Clock or TIming Strobes Ne
Protects Against Soft Errors caused by AI
Fast Access Time (Maximum):
Addr888
Chip
40ns

I.

20

A5

2

19

A3

A6

3

18

A2

AI

A7

4

17

AB

5

18

AD

A9

S

15

000

'" AID
All

7

14

DOl

8

13

002

E

9

12

10

11

~ 003
~ IV

PIN NAMES

(LSBI
A5-----. ..£"'---.

AD

AI
A3

Vee

A4

Vss

A2

•

PIN ASSIGNMENT

ROW
DECODER

~All

--Vce

. . . . . . . . . . . . Add~ Input
W. . . . . . . . . . . . , . . Write Enable

--VSS

E . . . . . . . . . . . . . . . . Chip Enable
000-003 . . . . . . . Data Input/Output
VCC . . . . • . . . . +5 V Power Supply
VSS . . . . . . . . . . , . . . . . Ground

MEMORY MATRIX
128 ROWS x
128 COLUMNS

AS -----. ..r----.

*This device may also be ordered as
IMSI423P-46.

A7
IMSBI

DOD

DOl

TRUTH TABLE

002

E

W

Mode

Supply Current

110 Pin

DD3

H

X

Not Selected

IS8

High-Z

L

H

Read

ICC

Dout

L

L

Write

ICC

Din

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
4-3

MCM1423

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage (VCCI
Voltage Relative to YSS for. Any Pin Except VCC

Value

Unit

-0.5to +7.0

V

-0.5 to VCC +0.5

V

±20

mA

Output Current (per 1/01
Power Dissipation
Operating Temperature

II

1.0

W

Oto+70

°C

Storage Temparature

-55 to +125

°C

Temperature Under Bias

:-10 to +85

°C

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability. .

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vec=5.0 V ± 10%, TA =0 to 70oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

Input High Voltage (See note belowl

VIH

2.0

VCC+0.3 V

V

Input low Voltage (See note belowl

Vil

-0.3*

-

0.8

V

Parameter

Supply

V~ltage

(Operating Rangel

*Vll (mini = -0.3 V de; Vil (mlnl= -3.0 V ac (pulse Width ,,;;20 ns)
NOTE: Address rise and fall times while the chip is selected are 50 ns maximum.

DC CHARACTERISTICS
Symbol

Min

Typ

Max

Unit

Input Leakage Current (All Inputs, Yin = 0 to 5.5 VI

IlL

-

-

1.0

~A

Output Leakage Current (E=VIH or W =Vll; Vout=O to VCCI**

10l

-

-

2.0

~A

Power Supply Current (E=VIL; Vin=VIL or VIH, 10ut=0 mAI**

ICC

-

80

mA

Standby Current (E = VIHI

ISBI

mA

IS82

-

20

Standby Current (E;"VCC-0.2 VI 10.2 V;"Vin;"VCC-0.2 VI

-

2

mA

Output low Voltage (lOl =8.0 mAl

VOL

-

-

0.4

Parameter

V

2.4
YOH
**Input levels less than -0.3 V or greater than VCC+0.3 V Will cause 110 and power supply currents to exceed maXimum rating.
Output High Voltage (lOH = - 4.0 mAl

V

CAPACITANCE (f = 1 0 MHz TA = 25°C periodically sampled rather than 100% testedl
Characteristic

Input Capacitance

All Inputs Except E
E

II 0 Capacitance

+5V

Symbol

Min

Typ

Max

Unit

Cin

-

3
5

5
7

pF

CliO

-

5

7

pF

AC TEST LOADS

+5V

480

480

110-....- - - -..

1 1 0 - + - - - -....

255

::.r= 30 pF

255

::.~ 5 pF

(INCLUDING
SCOPE AND JIGI

(INCLUDING
SCOPE AND JIG)

Figure 1B

Figure 1A

MOTOROLA MEMORY DATA
4-4

MCM1423

AC OPERATING CONDITIONS AND CHARACTERISTICS

± 10%, TA=O to 70°C, Unless Otherwise Noted)

(VCC=5.0 V

Input Timing Measurement Reference Level . . . . . . . 1.5 V
Input Pulse Levels. , . • . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/ Fall Time . . • . . . . . . . . . . . . . . . . . . . . . 5 ns

Output Timing Mesurement Reference Level .•....• 1.5 V
Output Load . . . . . . . . . . . . . . . . • • • . . . See Figure 1A

READ CYCLE 1 (E = Vll'
Symbol

Parameter

Standard

MCMl423P46

Alternate

Min

Max

Unit

Read Cycle Time

tAVAV

tRC

40

-

ns

Address Access Time

tAVQV

tAA

-

40

ns

Output Hold from Address Change

tAXQX

tOH

5

-

ns

Unit

Notes

tAVAV

W

"

ADDRESS

r\

_IAXOX

a

PREVIDUS DATA VALID

" XXXXX

DATA VALID

tAVOV

READ CYCLE 2 (E is Clocked)
Symbol

Param_

Standard

MCMl423P46

Alternate

Min

Max

Read Cycle Time

tAVAV

tRC

40

-

Address Access Time

tAVQV

tAA

40

ns

. tElQV

tACS

-

45

ns

-

ns

1

20

ns

1

ns
ns

E Access Time

E low to Output Active
E High to Output High-Z

tElQX

tLZ

tEHQZ

tHZ

5
0

Output Hold from Address Change

tAXQX

tOH

3

Power Up Time

tELICCH

tpu

0

-

Power Down Time

tEHICCl

tpo

-

45

ns

ns

NOTE:
1. Measured with ac load of Figure 18. PanImeter is sampled and not 100% tested. Transition measured ±500 mV from steady·state voltege.

IAVAV
ADDRESS

"r-

~

Ir...

1~
tElOV

I{

~
-

I£H QZ

tElOX"

'XIXXi..J~

a

-

DATA VALID

tAVQV

I.- tEHICel

IfUcCHVcc
SUPPLY
CURRENT

ICC
ISS

MOTOROLA MEMORY DATA
4-5

II

MCM1423

WRITE CYCLE t (IN Controlled) (See Note 1)
Symbol

Parameter

•

Standard

MCM1423P46

Unit

Alternate

Min

Max

-

n.

-

ns

Notas

Write Cycle Time

tAVAV

twc

40

Address Setup Time

tAVWL

tAS

Addr.ss Valid to End of Write

tAVWH

tAW

0
35

Write Pulse Width

twLWH

twP

~5

Data Valid to End of Write

tDVWH

tDW

Data Hold Time

twHDX

tDH

15
5

Write Low to Output High-Z

twLOZ

twz

0

20

ns

2,3

Write High to Output Active

twHQ)(

tow

6

ns

2,3

Write Recovery Time

twHAX

twR

E Low to End of Write

tELWH

tcw

5
35

-

ns
ns
ns
ns

ns
ns

NOTES:
1. A Write occurs during the overlap of a low Wand a low E.
2. Measured with the ac load of Figure lB. Parameter is sampled and not 100% tested. Transition measured ±500 mV from steady-state
voltage.
3. When the outputs are active, data of opposite logic level to an output must not be applied.

tAVAV
ADDRESS
IAVWH -------~--+- IWHAX
- - - , - - " \ l _ - - - - - I E l W H - - - - -....

IWlWH

-----I~

--~~I- tWHOX

O-------{

MOTOROLA MEMORY DATA

MCM1423

WRITE CYCLE 2 (E Controlled) (See Note 1)
Symbol

Parameter

MCMl423P45

Unit

Standard

Alternate

Min

Write Cycle Time

tAVAV

40

Address Setup Time

tAVEL

twc
tAS

Max
-

0

-

ns

Address Valid to End of Write

IAVEH

35

-

ns

Write Pulse Width

tELEH

lAW
lEW

35

-

ns

Dala Valid to End of Write

IDVEH

tow

15

-

Data Hold Time

tEHDX

tDH

5

ns
ns

Write Recovery Time

tEHAX

twR

5

-

Write Low to End of Write

twLEH

twP

35

-

NOTE:
1. If E goes low coincident with or after Vii low, and
condition.

ns

ns
ns

E goes high before or coincident with Vii high, the 1/0 will ramain in a high impedance
IAVAV ------------I~

ADDRESS
~-------- tAVEH ---------~

1......- - - - IAVEl ----+01---- tElEH --_.4001--....-1Vi -----------"\J~------tWlEH - - - - - - - . - /

a ________________

~HI~GH~.Z~

tEHAX

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

TIMING LIMITS

TIMING PARAMETER ABBREVIATIONS
t

I II

XXXX

signal name from which interval is defined -.-J
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address
setup time is shown as a minimum since the system must
supply at least that much time (even though most devices do
not require it). On the other hand, responses from the memory
are specified from the device point of view. Thus, the access
time is shown as a maximum since the device never provides
data later than that time.

The transition definitions used in this data sheet are:
H ~ transition to high
L ~ transition to low
V ~ transition to valid
X ~ transition to invalid or don't care
Z ~ transition to off (high impedance)

ORDERING INFORMATION
(Order by Full Pert Numberl

Motorola Memory prefix _ _ _ _ _ _ _T--'CM

T1423

Part Number

-

TL._T
__x_______

l

Full Part Number-MCM1423P45
NOTE: This device may also be ordered as IMS1423P-46.

MOTOROLA MEMORY DATA
4-7

speed (45=45 ns)
Package (P

~

Plastic DIP)

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

8K X 8 Bit Fast Static Random
Access Memory

II

The MCM6164/MCM61L64 is a 65,536 bit static random access memory organized as
8192 words of 8 bits, fabricated using Motorola's second-generation high-performanca silicon-gate CMOS (HCMOS III) technology. Static design eliminates the need for external
clocks or timing strobes, while CMOS circuitry reduces power consumption and provides
greater reliability.
The chip enable pins (Ei' and E21 are not clocks. Either pin, when asserted false, causes
the part to enter a low power standby mode. The part will remain in standby mode until
both pins are asserted true again. The availability of active high and active low chip enable
pins provides more system design flexibility than single chip enable devices.
The MCM6164/MCM61L64 is available in a 600 mil, 28 pin ceramic dual-in-line package,
with JEDEC standard pinout.
•
•
•
•
•
•
•
•
•

Single 5 V Supply, ± 10%
8K x 8 Organization
Fully Static - No Clock or TIming Strobes Necessary
Fast Access TIme - 46, 55 ns (Maximum I
Low Power Dissipation - 495, 440 mW (Maximum, Activel
Low Power/Data Retention Version (MCM61L641
Fu"y TTL Compatible
Three Stete Data Outputs
Also Available in Industrial Temperature Range (-40 to 85°CI as MCM6164C

BLOCK DIAGRAM

A5
A6
A7
A8
A9

MCM6164
MCM61L64

CERAMIC
CASE 733

PIN ASSIGNMENT

,.

28

VCC

2

27

Vi

A7

3

26

E2

A6

4

25

A8

A5

5

24

A9

A4

6

23

All

A3

7

22

Ii

A2

8'

21

AID

Al

9

20

AD

10

19

~IT
~D07
~D08
~D05
~D04
~D03

NC
A12

DOD! 11

18

001 ! 12

17

D02! 13

16

VSS! 14

15

_VCC
MEMORY ARRAY
(256 ROWS
256 COLUMNS)

-vss

PIN NAMES

AO-A12 . . . . . . • . • . . . Addraas

AID
A12

iN . . . . . . . . . . . . Write Enable
Ei, E2. • • • • . • • . • . Chip Enable
G .. .. . .. .. .. Output Enable

DOD

VCC . • . . . . . +5 V Power SupplV

All

007

Dab-DQ7 . • . • . Data Input/Output

I/O CIRCUITS

VSS • • • • • . • • • . • . . • Ground
NC • . • • . • • . . . . No Connection

COLUMN SELECT

IT
E2

W
ii

MOTOROLA MEMORY DATA
4-8

MCM6164·MCM61L64

TRUTH TABLE

n

E2

G

W

Mode

Supply Current

I/O Pin

H

X

X

X

Not Selected

ISB

HighZ

X

L

X

X

ISB

HighZ

L

H

H

H

Not Selected
Output Disabled

ICC

HighZ

L

H

L

H

Read

ICC

Dout

L

H

X

L

Write

ICC

Din

x = don't care
ABSOLUTE MAXIMUM RATINGS (See Nota)
Rating

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Yin. Vout

-0.5 to VCC+0.5

V

lout

±2O.

mA

Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC
Output Current (per I/O)
Power Dissipetion (TA = 25°C)
Temperature Under Bias

PD

1.0

W

Tbias

-10to+85

°c

TA

Oto +70

°c

Tstg

-66 to +150

°c

Operating Temperature
Storage Temperature

This device contains circuitry to protec1 the
inputs against damage due to high static
voltages or elec1ric fields; however. it is advised that normal precautions be taken to
avoid applicetion of any voltage higher than
maximum rated voltages to this highimpedance circuit.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENOED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extanded periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee=5.0 V ±10%, TA=O to 7Oo e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Param_r

Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

6.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.3*

-

0.8

V

Symbol

Min

Unit

*VIL (min) = -0.3 V de. VIL (min) = -3.0 V (pulse width s20 ns)
DC CHARACTERISTICS
Characteristic

Output Low Voltage (lOL = 8.0 mAl

VOL

-

Output High Voltage (lOH = - 4.0 mAl

VOH

2.4

Input Leakage Currant IAlllnputs. Vln=O to VCC)

IlkaUl

Output Leakaga Current In =VIH. E2=VIL. or ij=VIH. Vout=O to VCC)
Power Supply Currant
tAVAV=45ns
(n=VIL. E2=VIH.lout=O)
tAVAV=66ns

IlkalO)

Standby Current (n =VIH or E2=VIL)

ICC
ISBI

MCM6164
MCM61L64

Standby Current Ilf;a,VCC-0.2 V or E2:s0.2 V)

ISB2

Typ

Mex

Unit

<0.01

±1.0

<0.01

±1.0

p.A
p.A

50

90
80
3.0

mA

mA

5

1.0
50

0.16

0.4

3.0

-

p.A
V
V

Symbol

Max

Unit

Cin

6

pF

CliO

8

pF

40
1.3

-

mA

Typical values are referenced to TA=25°C and VCC=6.0 V
CAPACITANCE If= 1 0 MHz TA =25°C Periodically Sampled Rather Then 100% Tested)
Characterlatic
Input Capecitence

All Inputs Except DO
DQ

Input/Output Capecitence

MOTOROLA MEMORY DATA
4-9

II

MCM6164. MCM61 L64

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = Ii V ± 10%, TA=O to +700 (;, Unless Otherwise Noted) .
Output Timing Measurement Raference l.eveI . • . 0.8 V and 2.0 V
Output Load. . • . • . . . . • . • . • • . • . • . . • . . . . . . r'llure 1

Input TIming Measurement Raference Level • • • • • . • . • • 1.5 V
Input PuIse'LeveIs •.•.•.•.••••.•••••••••. 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns

READ CYCLE

(Sea

Note

1)

Characteristic

•

AIt

Symbol

Symbol

Read Cycle TIme
Address Cycle TIme

tAVAV
tAVQV

tRC
tAA

El A.ccess r""e
E2 Access TIme
13 AccassTIme
Output Hold from Address Change
Chip Enable to Output Low-Z
Output Enable to Output Low·Z
Chip Enable to Output High-Z
Output Enable to Output High-Z

tE1LQV
tE2HQV
tGLQV
tAXQX

tACl
tAC2
tOE

tel LQX, tE2HQX
tGLQX
tEl HQZ. tE2LQZ
tGHQZ

MCM81114-4&
MCM811J14.45

MCM81114-1&
MCM81L114-1&

Min

Max

Min

-

55

45

-

45
45

-

45

20

toH
tCLZ

5
5

-

toLZ
tCHZ

0
0
0

20
20

toHZ

NOTES:
1. Wis high at all times for read cycles.
2. AU high-Z and iow-Z parameters are considered in a high or low impedanCe state
previous steady state voltage.
3. Periodically sampled rather than 100% tastad.

-

-

55

-

55

55

Not..

ns
ns
ns

-

6

-

ns
ns
ns
ns

O·
0
0

-

ns

20
20

ns
ns

25

5

-

Unit

Max

.

. .

IADDRESSI _ _ _ _ _
·.

IT, E2 (CHIP ENABLEI

ii (OUTPUT ENABLE)

Q

(DATA oun __

+_-+___-(J

...;H.;;;I&;;;H..;;.Z_ _ _

+5V

TIMIIliG LlMJTS
The table of timing valuea shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address
setup time is shown as a minimum since the system must
supply at least that much time (8\(811 though most c!evices do
not require it). On the other hand, responsea from·the memory
are specified
the davice point of View. Thus, the access
time Is shown as a .maximum since the device never providea
data later than that time.

480

110-_----.....

from

30 pF

255

PNCLUDING
SCOPE AND JIG)

Figure 1. Test Load

MOTOROLA MEMORY DATA
4-10

2,3
2,3
.2,3
2,3

when the output has made a 600 mV transition from the

fl-o.·~~~~~~~~~~~~~~~~~~_t_A¥_AV_-_-_-_~_-_-_-_-:_-:_-:_-_-:_-:_-~
tl-o------- tAVDV ------I.~.

A

-

MCM6164-MCM61L64

WRITE CYCLE 1 (W CONTROLLED} (See Note 1)
Characteristic

Alt
Symbol

Symbol

MCM81.....
MCM81 LII4-U;

MCM81114-1i6
MCM811J14.1ili

Min

Min

Write Cycle TIme

tAVAV

twc

46

Add.... Setup TIme

tAVWL

tAS

0
40
25
20
0
0
5
0

Add.... Valid to End of Write

tAVWH

tAW

Write Pulse Width

twLWH

twp

Data Valid to End of Write

tDVWH

tDW

Data Hold TIme

twHDX

tDH

Write Low to Output in High-Z

twLOZ

twHZ

Write High to Output Low-Z

twHox

tow

Write Recovery TIme

twHAX

twR

Max

-

20

-

Unit

Not..

Max

-

55

0

-

50
30

-

25

ns

-

ns

-

ns

ns

2

ns

-

0

-

ns

0
5
0

20

ns

-

ns

3
4,5
4,5

ns

-

NOTES:
1. A write cycle atarts at the latest transition of a low Ei, low Vi or high E2. A write cycle ends at tha earliest transition of a high
high W
or low E2.
2. If W goes low coincident with or prior to Ei low or E2 high than the outputs will remain in a high impedance state.
3. During this time the output pins may be in the output state. Signals of opposite phase to the outputs must not be applied at this time.
4. All high-Z and low-Z peramatara are considered in a high or low impedance state when the output has made a 500 mV transition from the
previous steady state voltage.
5. Periodically sampled rather than 100% tested .

n,

.---------tAVAV--------~

A (ADDRESS)
, . - - - - - - - - - t A V W H - - - - - -..........~~- tWHAX
E (CHIP ENABLEI
, . . . . . - - - - tWLWH-----t

VI (WRITE ENABLE)

D (DATA IN)

a (DATA Dun ----'----~
3.4
3.2
3.0
2.8
:i!
a: 2.6
c
~ 2.4
i§ 2.2
:t:
2.0
~ 1.8
1.6
~ 1.4
i§ 1.2
1.0
0.8

!
TYPICAL
CHARACTERISTICS

VCC= 5.0 V
TA=25°C

- -

~

1/

S

0.4

0.8

1.2
1.6
2.0
ADDRESS INPUT LEVELS (V)

2.4

2.8

3.2

Figure 2. Access Time Versus Address Input Levels

MOTOROLA MEMORY DATA
4-11

II

MCM6164-MCM61 L64

WRITE CYCLE 2 (ENABLE CONTROLLED) (See Notes I and 2)
Characteristic

II

Symbol

Ait
Synibol

MCM61~

MCM811J14.4&

MCM6164-6&
MCM811J14..1i&

Min

Max

Min

Max

-

56

-

Write Cycle Time

tAVAV
tAVEIL

twc
tAS

46

Address Setup TIme

0

Address Valid to End of Write

tAVEIH

tAW

40

Chip Enable to End of Write

tEILEIH

tcw

40

Date Valid to End of Write

tDVEIH

tow

20

Date Hold Time

tEIHDX

tDH

0

Write Recovery TIme

IEIHAX

twR

0

0

-

-

50
50

-

25

-

0

-

-

0

Unit

Notes

ns

-

ns
no

ns

3

no

-

no

4

no

-

NOTES:
I. A write cycle sterts at the latest transition of a low El", low iN or high E2. A write cycle ends at the earliest transition of a high El", high iN
or low E2.
2. EI and E2 timings are identical when E2 signals are inwrted.
3. If iN goes low coincident with or prior to Ellow or E2 high then the outputs will remein in a high impedance state.
4. During this time the output pins may be in the output stete. Signals of opposite phase to the outputs must not be applied at this time.

'AVAV
A (ADDRESS)

E(CHIP ENABLE)

o{DATA IN)

DATA VALID
IDVEIH
HIGH·Z

n {DATA OUTI

LOW Vec DATA RETENTION CHARACTERISTICS {TA=O to +700 C) (MCM6IL84 Only)
Symbol

Min

Typ

Max

Unit

Vcr.!0r Data Retention
{EI«VCC-0.2 V or E2:s0.2 V, Vin«VCC-0.2 V or Vi n :s0.2 V)

VDR

2.0

1.0

7.0

V

Data Retention Current
{VCC=3.0 V, El"«2.8 V or E2:s0.2 V, Vin«2.8 V or Vin",0.2 V)

ICCDR

-

10

30

p.A

Chip Disable to Date Retention TIme {see wavefonn below)

tCDR

0

-

tAVAV*

-

-

ns

trec

Characteristic

Operation Recovery Time {see waveform below)
*tAVAV = Read Cycle Time

14---- DATA RETENTION MDDE - -.....ot
VCC

VDR«2.D V

IT CONTROL

E2 CONTROL

~.j"":L~~=J-

_____....;E;:.2.:::S;:.O;;;.2,,;V_ _ _ _---\::::":'LLL.l.~c..L

MOTOROLA MEMORY DATA
4-12

ns

MCM6164-MCM61L64

TYPICAL CHARACTERISTICS
(Continued)
1.8

2.50
2.25

1.7

.

ffi

1.6

.s

>-

1.5

IE

1.4 ............

'"

1.3

ili

B

!!J

---- -

VCC=5.5 V

'"
ill
c

1.50

>-

1.25

~

./

.

--

:: 0.75
!!J

1.1
1.0

./'

0.50
0.25

o

20

40

o

80

60

4.0

TA. AMBIENT TEMPERATURE IOC)

Figure 3. Standby Current Versus Temperature

.

1.15

.

!

/
1/

VCC= 5.5 V

12

>-

IB

1.20

18

14

.5

10

t"

N

!!J

./

:IE

c'"

/

o

15
..,IE

./'

::::0

1.00
0.95

~ 0.90

0.85
60

-- -

>-

1.00

iB

1.0

1.4
1.3
S

~

1'",,-

:iii
:IE
c
'"
;;!;

VCC=5.5 V

~

......

-- -

:--- I---

~ 0.9 8
0.9 7

o

20

40

60

1.1

.

0.8

..,

~

./

0.9

0.7

/~

/

/

I-"'"

0.6
4.0

80

V
./

TA=25°C

1.0

'"
B

V

1.2

>-

~

I--..

0.99

0.96

6.0

5.5

Figure 6. Standby Current Versus Supply Voltage

1.03

~

5.0

4.5

VCC. SUPPLY VOLTAGE IVI

1.04

~
:s'"

6.0

5.5

VCC. SUPPLY VOLTAGE IVI

~

0.80
4.0

80

Rgure 6. Standby Current Versus Temperature

1.02

5.0

4.5

TA. AMBIENT TEMPERATURE lOCI

s

/

TA=25°C

!!J

40

20

1.10
1.05

;;!;

~

o

i.--"""

"......-

Figure 4. Standby Current Versus Supply Voltage

20
16

/"

TA=25°C

~ 1.00
§5

r--- r--

1.2

2.00

~ 1.75

TA. AMBIENT TEMPERATURE lOCI

4.5

5.0

5.5

VCC. SUPPLY VOLTAGE IVI

Figure 7. Supply Current Versus Temperature

Figure 8. Supply Current Versus Supply Voltage

MOTOROLA MEMORY DATA
4-13

B.O

•

MCM6164-MCM61 L64

TYPICAL CHARACTERISTICS
(Continued)
1.3

1.3

1.2

V

1. 1
1.0

,

1.1

~ i\..

:: 1.0

;;;

;;;

./

0.7

Iii:

V

'" 0.6

B 0.5

~ 0.4

II

fa

./

::: 0.9
co 0.8

ifi

1.2

./

VCC=5.0V
TA=25°C

V

0.3
0.2

0.9

~
B
0.8

1/

"'

VCC=5.0 V
TA=25°C

I'-..
.........

r-....

I'-....

~ 0.7

O. 1

o

12

4

16

24

20

70
IAVAV. CYCLE TIME

55

28

1IIAYAY. FREOUENCY (MHz)

1.4

1.25

1.3

1.20

11.2

=

VCC=4.5 Y

1.1

!i1 1.0
gI

--!_
~ 0.9

L--~

--- ---

~ 0.8

o

~

:il!

1.15

5

1.10

Ei
:>::
gI

1.05

co
'"

80

60
40
TA. AMBIENT TEMPERATURE (OC)

1.30

Up

1.25

1.10

5

.,...,.. .......

1.00
0.95
0.90
0.85

.....

.,..

1.20
is 1.15

......... V

11.05

Ei

./

VCC=4.5 V

F=
100

85
(n.)

TA '7 25°C

'" """ ""-

4.5

~

5.0
Vcc. SUPPLY VOLTAGE (V)

............

r-..
6.0

5.5

Figure 12. Access Time Versus Supply Voltage

1.25

1.15

if

0.95

0.85
4.0

Figure 11. Access Time Versus Temperature

~

""'

~
~ 0.90
20

-..;;;

~

§ 1.00
~

0.7

0.6

r--

. Figure 10. Supply Current Versus Cycle Time

Figure 9. Supply Current Versus Frequency

is

..........

0.6

;

"'

"-

1.10

~ 1.05

V

Ei

1.00

if

0.95

V

TA=25OC

'"'" "- .............
-......:...

0.90

~
...........

0.85

o

20

40

60

0.80
4.0

80

4.5

5.0

5.5

VCC. SUPPlY VOLTAGE (V)

TA. AMBIENT TEMPERATURE (OC)

Figure 14. Access Time Versus Supply Voltage

Figure 13. Access Time Versus Temperature

MOTOROLA MEMORY DATA
4-14

6.0

MCM6164-MCM61L64

ORDERING INFORMATION
IOrder by Full Part Number)
C

T-'CM

Motorola Memory Prefix _ _ _ _ _ _ _
Part Number
(with L = Low Power Version)
Full Part Numbers-MCM6164C45

8164

air 81L64
.

MCM6164C56

XX

T ~Speed

(45=45 ns, 56=56 ns)

~paCkage (C=Ceramic DIP)
MCM61L64C45

MCM61 L64C56

II

MOTOROLA MEMORY DATA
4-15

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL
DATA

--------------

MCM6164C
Advance Information

8K X 8 Bit Fast Static Random
Access Memory
Industrial Temperature Range: - 40 to 85°C

II

The MCM6164C is a 66,536 bit static random access memory organized as 8192 words
of 8 bits, fabricated using Motorola's second-generation high-performance silicon-gate
CMOS (HCMOS III) technology. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides greater
reliability. With its operating temperature range of - 40°C to + 85°C and hermetic package, the MCM6164C is ideally suited for harsh industrial type environments.
The chip enable pins (E1 and E2) are not clocks. Either pin, whan asserted false, causes
the part to enter a low power standby mode. The part will remain in standby mode until
both pins are asserted true again. Tha availability of active high and active low chip enable
pins provides more system design flexibility than single chip enable devices.
The MCM6164C is available in a 600 mil, 2S pin ceramic dual-in-line package with the
JEDEC standard pinout.
•
•
•
•
•
•
•
•

CPACKAGE
CERAMIC
CASE 733

PIN ASSIGNMENT
NC 11.

A12 2

Single 5 V Supply, ± 10%
8K x 8 Organization
Fully Static-No Clock or Timing Strobes Necessary
Fast Access Time~55 or 70 ns (Maximum)
Low Power Dissipation-440 or 385 mW (Maximum, Active)
Fully TIL Compatible
Three State Data Outputs
Also Available in Commercial Temperature Ranga (0 to 70°C) as MCM6164/MCM61L64

BLOCK DIAGRAM

A5
A6
A1
A8
A9

~Vss

All
A12

007

VCC

21

W

A1

3

28

E2

A8

4

25

A8

A5

5

24

A9

A4

8

23

All

A3

7

22

G

A2

8

21

A1D

Al

9

20

ri

AD

10

19

007

DQO

11

18

~ 006

001

12

11~ 005

DD2

13

18

Vss

14

15

~ 004

~ 003

~VCC

MEMORY ARRAY
(266 ROWS
256 COLUMNSI

A1D

DQO •

28

PIN NAMES

AO-A 12 . • . . . • . • • . • . Address

iii . . . . . . . . . . . . Write Enable
fl, E2. . • . • . • • • • • Chip Enable
G .. .. .. .. .. . Output Enable
DOD-DQ7 ....• Data Input/Output
VCC. . . • . . .

I/O CIRCUITS

ri
E2

W
li

This document contains Information on a new product. Specifications and Infonnation herein are subject to change without notice.

4-16

Power Supply

NC • . • • . . . • • . . No Connection

COLUMN SELECT

MOTOROLA MEMORY DATA

+5 V

VSS •••.•••.•••.•. Ground

MCM6164C

TRUTH TABLE
El

E2

G

W

Mode

Supply Current

I/O Pin

H

X

X

X

Not Selected

ISB

High Z

X

L

X

X

Not Selected

ISB

High Z

L

H

H

H

Output Disabled

ICC

High Z

L

H

L

H

Read

ICC

Dout

L

H

X

L

Write

ICC

Din

X = don't care

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Power Supply Voltage

Value

Unit

VCC

-0.5 to +7.0

V

Vin, Vout

-0.5 to VCC+0.5

V

Output Current (per I/O)

lout

±2O

mA

Power Dissipation (TA = 25DC)

PD

1.0

W

Tbias

-10to +85

DC

TA

-40 to +85

DC

Tstg

-65 to +150

DC

Voltage Relative to VSS for Any
Pin Except V CC

Temperature Under Bias
Operating Temperature

Storage Temperature

This device contains circuitry to protect the
inputs against damaga due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

NOTE: ~ermanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltagas for
extended periods of time could effect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%. TA= -40 to 85°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Ranga)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.3*

-

0.8

V

Parametar

*VIL (min) = -0.3 V dc, VIL (min) = -3.0 V (pulse width s20 ns)

DC CHARACTERISTICS
Symbol

Min

Typ

Max

Unit

Input Leakaga Current (All Inputs. Yin = 0 to V CC)

IlkaUl

-

<0.01

±2.0

Output Leakaga Current (El =VIH. E2=VIL. or G=VIH. Vout=O to VCC)

Ilka(O)

<0.01

±2.0

".A
".A
mA

Charactarietlc

Standby Current (Ei = VIH or E2 = VIL)

ISBI

-

Standby Current (Ei:':VCC-0.2 V or E2s0.2 V)

ISB2

-

Output Low Voitega UOL = 8.0 rnA)

VOL

Output High Voltaga UOH = - 4.0 mAl

VOH

Power Supply Current
(Ei =VIL. E2=VIH. 10ut=0)

tAVAV=55 n.
tAVAV=70 no

ICC

40

80

35

70

1.3

3.0

mA

0.005

1.0

mA

-

0.16

0.4

V

2.4

3.0

-

V

Symbol

Max

Unit

Cin

6

pF

CI/O

8

pF

TypIcal values are referenced to TA=25DC and VCC=5.0 V

CAPACITANCE (f-l
- 0 MHz TA =25DC Periodically Sampled Rather Than 100% Tested)
Characterietlc
All Inputs Except DO

Input Capacitance
Input/ Output Capacitance

DO

MOTOROLA MEMORY DATA
4-17

II

MCM6164C

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5 V ±10%, TA= -40 to +85°C, Unless Otherwise Noted)
+5V
Input Timing Measurement Reference Level . . . . • • . . • . 1.5 V
Input Pulse Levels . . . . • . . . • . . . . . . . . . • . . . .0 to 3.0 V
Input Rise/Fall Time . . . • . . . . . . . . . . . . . . . . . • • . . 5 ns
Output Timing Measurement Reference Level ... O.S V and 2.0 V
Output Load. • • . . . . . • • • . . . . . . • • . . . . . . . • • Figure I

480
I/o----

.r:

Figure 4. Standby Current Versus Temperature

_

1.00

Q

V

20
40
60
TA. AMBIENT TEMPERATURE IOe)

TA=25°e

1.05

ii!
..,'":::>
'"Z

/

10

1.15
1.10

Q

l-

20

:;l

~

I

Q

!!}

6.0

5.0
5.5
Vee. SUPPLY VOLTAGE (VOLTS)

1.20

I-

.r:

4.5

4.0

S'

C
..:l- 30

~

.---

V
.......... f-""

Figure 3. Standby Current Versus Supply Voltage

35

z

.75

o

100

40

..,'":::>

./

/"'"

1.0

~
~

z

Figure 2. Standby Current Versus Temperature

iI!

./
/'

TA=25°e
1.25

Vee=5.5V

1.2

- 20

2.0

~

f'... .........

1.4

1.0
-40

2.25

~

1.6

§= 1.5
i:l

S

.

1.7

4.25

TA. AMBIENT TEMPERATURE 1°C)

4.50

4.75

5.00

5.25

5.50

5.75

Vee. SUPPLY VOLTAGE (VOLTS)

Figure 6. Supply Current Versus .Temperature

Figure 7. Supply Current Versus Supply Voltage

MOTOROLA MEMORY DATA

4-21

6.80

II

MCM6164C

TYPICAL CHARACTERISTICS
(Continued)

1.3

V.

1.0
0.9
0.8
0.7
0.6

II

••

i\

...-

I

1.1

i

1.3

I I

1.2

VCC=5.0 V
TA=25°C

- -

"

6

V

Ii

r..= 0.9
~

0.2
o. 1

"i'.. .......

0.8

~
16

12

4

20

24

i'--...
55

lkAVAV. FREOUENCY (MHz)

FIgure 8. Supply Current Versus Frequency

I: :
!'"
~

1.2

--.
Vc =4.5 V

1.1

.. 1.0

S

0.9

.. 0.8

~ f-'"

~

I--' ~

I
.,a:

-

~

-20

'"

!' 1.10

9. '1.05
i!:i

~

0.95

9

20
40
60
TA. AMBIENT TEMPERATURE (OC)

BO

100

V

I::::

VCC=4.5 V

./

iB 0.95

-

-20

0.85
4.0

V

"

~ ::::

V

4.5

TA=25°C

"'" '" ""-

""

1£ 1.10

!

V-

1.05

H
=

r-8.0

I
,TA=25°C

"" "-

1.00

c 0.95

I

'"

~

...........

0.90
0.B5

80

..........

5.0
5.5
VCC. SUPPLY VOLTAGE (VOLTS)

"-.

11.15

20
40
60
TA. AMBIENT TEMPERATURE (OC)

100.

1.30

f-'"'"

V

i!... 1.00

--

Figure 11.·Access Time Versus Supply Voltage

./

......

!

AccesS TIme Versus Temperature

1.20

85

""- t\..

~ 1.00

1.15

-40

70
IAVAV. CYCLE TIME In.)

>1

Figure 10.

0.80

1.20

1£ 1.15

~

~'0.85

1.25

]; 0.90

~ 06
-40

~

r--

FIgure 9. Supply Current Versus Cycle TIme

l!t 0.7

:0.90

..........

o.B

0.5
40

28

VCC=5.0 V
TA=25OC

:--....

~ 0.7
C

L

o

"-

8:

V

0.3

1.1

1£ 1.0

./

0.5
0.4

1.2

~
.,lEa:

100

0.80
4.0

4.5

5.0

........ ......

5.5

Vcc. SUPPLY VOLTAGE (VOLTS)

Figure 13. Acc_ TIme Versus Supply Voltage

FIgure 12. Acc_ TIme Versus Temperature

MOTOROLA MEMORY DATA
4-22

6.0

MCM6164C

ORDERING INFORMATION
(Order by Full Part Number)
MCM

6164

11 L,_,oo_
C

C

55

Package

Operating Temperature Range
L - - - - - - - P a r t Number
L - - - - - - - - - - M o t o r o l a Memory Prefix
Full Part Number-MCM6164CC55 or MCM6164CC70

MOTOROLA MEMORY DATA
4-23

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6168

4K X 4 Bit Static Random Access
Memory
,The MCM6168 is a 16,384-bit static random access memory organized as 4096 words of

4 bits, fabricated using Motorola's second-generation high-performance silicon-gate

II

CMOS (HCMOS 1111 technology. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides greater
reliability. Fast access time makes this device suitable for cache and other high speed
applications.
The chip enable (E) pin is not a clock. In less than a cycle time after E goes high, the
part enters a low-power standby mode, remaining in that state until E goes low again.
This feature provides reduced system power requirements without degrading access time
performance.
.
The MCM6168 is available in a 300 mil, 20 lead plastic dual-in-line package
standard JEDEC pinout.
•
•
•
•
•

Single 5 V Supply, ± 10%
4K x 4 Bit Organization
Fully Static- No Clock or Timing Strobes Necessary
Three State Output
Fast Access Time (Maximum):
Address

45

~
'~Y}P~~E
PLASTIC
CASE 738

1

PIN ASSIGNMENT
A41 I .

20

Vee

A5

19

A3

A6

16

A2
AI

A7

4

17

A8

5

18

AD

A9

15

DOO

AID

14

DOl

All

13

DD2

12

003

II

ii

E

Vss

•

10

PIN NAMES
AD-A11. . . . . • . . • . • . Add ....... Input

Vii. . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . Chip Enable

ILSBI A5

-Vee
-Vss

AD
AI
A2
A3

MEMORY MATRIX
128 ROWS x
128 COLUMNS

A8
IMSBIA7

000

DOl
DQ2

003

MOTOROLA MEMORY DATA
4-24

DOD-DOl ......• Data Input/Output
VCC '.' . . . . . . . +6 V Power Supply
VSS •••••••••••••••• Ground

MCM6168

TRUTH TABLE

E

W

Mode

VCC Current

1/0 Pin

H
L
l

X

Not Selected
Read
Write

ISB1,ISB2
ICC
ICC

High-Z
Dout
Din

H

L

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric lields; however, it is advised that normal precautions be taken to
avoid application 01 any voltage higher than
maximum rated voltages to this highimpedance circuit.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 25°C)

Po

1.0

W

Temperature Under Bias

Tbias

-10to +85

°c

Operating Temperature

TA

Storage Temperature

Tsto

Power Supply Voltage
Voltage Relative to VSS lor Any
Pin Except VCC

o to

+70

II

°c

-55 to +125

°c

NOTE: Permanent device damage may occur il ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages lor
extended periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

V,H

2.0

V

1

V,L

-0.3

-

VCC+0.3

Input Low Voltage

O.S

V

1,2

Notes

Parameter

Notes

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin=O to VCC)

Ilkalll

±1.0

~

Output Leakage Cunrent (E=V,H or W=V,L, Vout=O to VCC)

l'ka(O)

Parameter

Power Supply Cunrent (E=V,L, 10ut=0 mAl

ICC

TTL Standby Current (E=V,H)

ISSI

CMOS Standby Current (E:':VCC-0.2 V, Vin SO.2 V or :.:VCC-0.2 V)

IS82

-

Output Low Voltage (lOL =8.0 mAl

VOL

-

0.4

V

Output High Voltage (lOH = - 4.0 mAl

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cin

3
5

5
7

pF

CliO

5

7

pF

±2.0

~

3

80

mA

3

20

mA

2

mA

CAPACITANCE (I = 1.0 MHz, T A = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
All Inputs Except E
E

Input Capacitance
110 Capacitance

NOTES:
1. Address rise and fall times while the chip is selected are 50 ns maximum.
2. VIL(min)= -0.3 V de; VIL{min) = -3.0 V ac (pulse widths20 ns).
3. Input levels less than -0.3 Vor greater than VCC+0.3 V will cause 110 and power supply currents to exceed maximum rating.

MOTOROLA MEMORY DATA
4-25

MCM6168

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA=O to + 70 oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise! Fall Time . • . . • . . . . . . . . . . . . . . . . . . . . 5 ns

Output Timing Measurement Reference Level . . . . • 0.8 and 2.0 V
Output Load. . . • . . . . . . . . Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
MCM6168-Ui

MCM81~

MCM8188-70

Alternate

Min

Max

Min

Max

Min

Symbol
Parameter
Standard

II

Max

Unit

Read Cycle Time

tAVAV

tRC

46

-

55

-

70

-

Address Access Time

tAVQV

.tAA

46

ns

tACS

46

55

-

80

tELQV

-

50

E Access Time

-

70

ns

E Low to Output Active

tELOX

tLZ

10

-

10

-

10

-

E High to Output High-Z

tEHOZ

tHZ

0

15

0

20

0

25

ns

tAXOX

tOH

5

-

5

5

tELICCH

tpu

0

-

-

Power Up Time

0

-

0

-

ns
ns
ns
ns

Power Down Time

tEHICCL

tpD

-

46

-

55

-

70

ns

Output Hold from Address Change

NOTES:
1. iN is high for read cycle.
2. Trensition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
3. This parameter is sampled and not 100% tested.
4. Device is continuously selected (E=VIL).
5. Addresses valid prior to or coincident with E going low.

READ CYCLE 1 (See Note 4 Above)
tAVAV

"

W

A (ADORESS)

11\

I--- tAXQX

KXXXXX).r-

PREVIOUS DATA VALID

o (DATA DUn

DATA VALID

tAVOV

.
A (ADDRESS)

READ CYCLE 2 (See Note 5 Above)

..

tAVAV

~

,rit'--

..

tELOV

'{

E(CHIP ENABLE)

IEHOZ

- - tELQX

·(X)OOOO

o (DATA OUT)

DATA VALID

~

tAVOV

VCC
SUPPLY
CURRENT

ICC

.... tEHICCL

IELICCH -

---------

ISB

MOTOROLA MEMORY DATA
4-26

Notee

2,3
2,3

MCM6168

WRITE CYCLE 1

(iN Controlled·

See Note I)
MCM61f18..46

MCM6168-66

MCM6168-70

Standard

Symbol
Alternate

Min

Max

Min

Max

Min

Max

Write Cycle TIme

tAVAV

!Wc

40

0

tAVWH

tAW

35

66

-

ns

tAS

Write Pulse Width

twLWH

twP

35

66

-

ns

Data Valid to End of Write

tOVWH

tow

20

25

twHOX

tOH

-

3

-

3

-

ns

Data Hold TIme

15
3

-

60

tAVWL

-

50

Address Setup Time

Write Low to Output High-Z

twLQZ

twz

-

20

-

25

-

30

ns

2,3

Write High to OutpUt Active

twHOX

tow

5

5

-

5

2,3

twHAX

twR

5

5

-

5

-

ns

Write Recovery Time

-

Parameter

Address Valid to End of

Wr~e

0
46
46

0

Unit

Not";

ns
ns

ns

ns

NOTES:
1. A write occurs during the overlap of E low and iN low.
2. Transition is measured ± 500 mV from steady-state voltage with load in Figure 1B.
3. Parameter is sampled and not 100% tested.

1-4---------

tAVAV

A IADDRESS)
tAVWH

- - - - - - - t....-+_

twHAX

EICHIP ENABlE)
twLWH

" !WRITE ENABLE)
- " , 4 - I * " " twHDX

D IOATA IN)

Q IDATA OUT) --..;;;;;;;;.;;.---(

AC TEST LOADS

TIMING LIMITS

+5V

+5V

480
Q

Q -.....- - - -......

30 pF

255

480

PNCLUDING

255

==

SCOPE AND JIG)

Flgur.1A

5pF

!INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
4-27

The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a
maximum since the device never provides
data later than that time.

•

MCM6168

WRITE CYCLE 2 IE Controlled' See Note 11
Symbol

MCM8168-45

MCM8168-&6

MCM8188-1O

Standard

Alternate

Min

Max

Min

Max

Min

Write Cycle Time

tAVAV

twc

Address Setup Time

tAVEL

tAS

40
0
35
35
15
3
5

-

50
0

-

46

-

Paremeter

II

Address Valid to End of Write

tAVEH

tAW

Write Pulse Width

tELEH

tew

Date Valid to End of Write

tDVEH

tDW

Date Hold Time

tEHDX

tDH

Write Recovery Time

tEHAX

twR

-

-

46

3

-

5

-

20

60
0
55
55
25
3
5

Max

-

-

Unit

Not.

ns
ns
ns
ns

-

ns
ns

-

ns

2,3

NOTES:
1. A write occurs during the overlap of E low and Vii low.
2. If E goes low coincident with or after Vii goes low, the output will remain in a high impedence condition.
3. If Egoes high coincident with or before Vii goes high, the output will remain in a high impedence condition.

IAVAV
A (ADDRESSI
IAVEH

I (CHIP ENABlEI
tEHAX

Vi (WlUTE ENABLEI
tEHDX
D (DATA INI

HIGH·Z

o (OATA OUTI

ORDERING INFORMATION
IOrder by Full Part Number)

CM

T...J

Motorola Memory prefix _ _ _ _ _
Part Number

J TL._T
I _________
Sl68

Full Part Numbers-MCM6168P45
MCM6168P55
MCM6168P70

MOTOROLA MEMORY DATA
4-28

speed (45=45 ns, 55=55 ns,
70=70 nsl
Package (P = Plastic DIPI

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

I

Product Preview
32K X 9 Bit Fast Static Random
Access Memory
The MCM6205-20 is a 294,912 bit static random access memory organized as 32,768
words of 9 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. Static design eliminates the need for extemal clocks or timing strobes, while CMOS
circuitry reduces power consumption and provides for greater reliability.
The chip enable pins (El and E2) are not clocks. Either pin, when asserted false, causes
the part to enter a low power standby mode. This feature provides significant system-level
power savings. The part will remain in standby mode until both pins are asserted true
again. Another control feature, output enable (G), allows access to the memory contents
as fast as 10 ns (MCM6205-20).
The MCM6205-20 is packaged in a 300 mil, 32 pin plastic dual-in-line package or a 32
lead 300 mil plastic SOJ package with the JEDEC standard pinout.
•
•

•
•
•
•
•

Single 5 V Supply, ± 10%
Fast Access Time-20/25 ns (Maximum)
Low Power Dissipation
Chip Controls: Chip Enable (E!, E2) for Reduced-Power Standby Mode
Output Enable fG) for Fast Access to Data
Three State Outputs
Fully TTL Compatible
High Board Density SOJ Package Available

MCM6205-20 1

~

PPACKAGE
300 MIL PLAmC
CASETBD

~KAGE

300 MIL SOJ
CASETBD

PIN ASSIGNMENT

NC

I.

32

VCC
AI4
E2

it
AI3
AD

BLOCK DIAGRAM

AID

A

All

A

11
AI2

A

A

MEMORY ARRAY
1256 ROWS
1152 COWMNSI

ROW
~==I DECODER

ET
006
007

A

006
005
004

PIN NAMES
A . . . . . . . . . . . . . Address
Write Enable
Ei, E2 •••....• Chip Enable
II . . . . . . . . . Output Enable
DOO-DOS .. Oats input/Output
VCC . . . . +5 V Power Supply
VSS . . . . . . . . . • . Ground

w. . . . . . . . . .
E2

A

A A

A

A

A

NC . . . . . . . . No Connection

ii ----<1..---'

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
4-29

II

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6206
Advance Information

32Kx8 Bit Fast Static Random
Access Memory

II

The M,CM6206 is a 262,144 bit static random access memory organized as 32,768 words
of 8 bits, fabricated using Motorola's high-parfonnance silicon-gate CMOS technology.
Static deeign eliminates the need for external clocks or timing strobes, while CMOS circuitry raduces power consumption and providee for greater raliability.
Chip enable (EI controls the power-down festure. It is not a clock but rathar a chip
control that affects power consumption. In less than a cycla time after E goes high, tha
part automatieally reduces its power requirements and remains in this low-power standby
mode as long as E remains high. This feature provideli significant systam-Ievel power
savings. Another control feature, output enabla (GI allows access to the memory contents
as fast as 15 ns (MCM6206-35I.
The MCM6206 is packaged in a 600 mil, 28 pin plastic dual-in-line package or a 28 lead
400 mil plastic SOJ package with the JEDEC standard pinout.

~CKAGE
PLASTIC
CASE 810

PIN ASSIGNMENT

Single 5 V Supply, ± 10%
Fully Static- No Clock or Timing Strobes Necessary
Fast Access Time-35 or 46 ns (Maximuml
• Low Powar Disaipation
• Two Chip Controls; E for Automatic Power Down
, G for Fast Access to Data
• Three State Outputs
• Fully TIL Compatible
•
•
•

BLOCK DIAGRAM
A2

A14

1.

28

A12

2

27

Vee
W

A7

3

26

A13

A6

4

25

A8

A5

5

24

AD

A4

6

23

All

A3

7

22

IT

A2

8

21

Al0

Al

9

20

E

A3

AO ! 10

19

~ 007

A4

DQO ! 11

18

006

A5

DOl

!
002 !
Vss !

17~ DQ5

A6
A8

MEMORY ARRAY
1512 ROWS
512 COLUMNS)

ROW

~=:::::jOECODER

•

12
13

16

14

15

P004
PDQ3

A9
All

PIN NAMES

A13

AQ-A14 ••......•. Address

.

0001-_",,--; ,~r-:~,...,L..I--'------1"'--._

•

007-t-t-iH

AO

Al

Vii. . . . . . . . . . Write Enable
E . . . . . . . . . . . Chip Enable
G . . . . . . . .. Output Enable
000-0Q7 .. Oats Input/Output
VCC ••.• +5 V Power Supply
VSS •..•••••••• Ground

A7 Al0 A12 A14

iii
IT----d.---I

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
4-30

MCM6206

TRUTH TABLE
E

G

iN

Mode

Supply
Currant

1/0 Pin

H

X

X

Not Selected

ISB

High Z

L

H

H

Output Disabled

ICC

High Z

L

L

H

Read

ICC

Dout

L

X

L

Write

ICC

Din

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to

avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

X-Don't Care

•

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Exqept VCC

Output Current (per 1/0)
Power Dissipation (TA = 25·C)
Temperature Under Bias
Operating Temperature

Storage Temperature-Plastic

Symbol

Value

VCC

-0.5 to +7.0

Unit
V

Vin, Vout

-0.5 to VCC+0.5

V

lout

±20

rnA

Po

1.0

W

Tbias

-10to+85

·C

TA

Oto+70

·C

Tsta

-55 to +125

·C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 ± 10%, TA=O to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC + 0.3

V

VIL

-0.3*

-

0.8

V

Input Low Voltage
*VIL (min) = -0.3 V de; VIL (min) = -3.0 V ac (pulse width

s

Unit

20 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Currant (All Inputs, Yin = 0 to VCC)

Ilka(l)

±1.0

p.A

Output Leakage Current (E=VIH, or G=VIH, Vout=O to 5.5 V)

Ilka(O)

Parametar

Standby Current (E = VIH) (TTL Levels)

ISBl

Standby Current (E '" VCC-0.2 V) (CMOS Levels)

ISB2

Output Low Voltage (lOL =8.0 rnA)

VOL

-

Output High Voltage (lOH= -4.0 rnA)

VOH

2.4

Power Supply Current
(E=VIL, 10ut=0)

(tAVAV = 35 ns)
(tAVAV = 45 ns)

ICC
ICC

±1.0

p.A

120
110

rnA
rnA

20

rnA

15

rnA

0.4

V

-

V

Symbol

Max

Unit

Cin

6

pF

CliO

8

pF

CAPACITANCE (f=l 0 MHz TA=25·C periodically sampled and not 100% tested)

Characteristic
Input Capacitance
110 Capacitance

MOTOROLA MEMORY DATA
4-31

MCM6206

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5 V ±10%, TA =0 to 70°C, Unless Otherwise Noted)

Input Pulse Levels • . . . • . . • . . • • . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Input Timing Measurement Reference Levels . . . . . . • . . . 1.5 V

Output Timing Measurement Reference Levels. . . • . . . . .1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

READ CYCLE 1 .. 2 (See Note 1)
Parameter

II

Symbol

MCM8208-3Ii

Alt
Symbol

Min

MCM821J8.46

Max

Min

Max

Unit

Not..

Reed Cycle Time

tAVAV

tRC

36

-

46

ns

tAVOV

tAA

-

35

-

-

Address Access Time

46

ns

-

46

ns

-

20

ns
ns

EAccess Time

tELOV

tAC

!(oLOV

tOE

-

35

"G Access Time

15

-

Enable Low to Enable High

tELEH

tew

35

-

46

Output Hold from Address Change

tAXOX

toH

5

Chip Enable to Output Low-Z

tELOX

tCLZ

10

10

Output Enable to Output Low-Z

tGLOX

toLZ

0

-

0

-

Chip Enable to Output High-Z

tEHOZ

tCHZ

0

20

0

20

ns

2,3

Output Enable to Output High-Z

tGHOZ

toHZ

0

20

0

20

ns

2,3

5

-

ns

2

ns

2,3

ns

2,3

NOTES:
1. W is high at all times for read cycles.
2. All high-Z'and low-Z parameters are ocnsldered in a high or low impedance state when the output has made a 500 mV transition from the
previous steady state voltage.
3. Thess parameters are periodically sampled and not 100% tested.

€

READ CYCLE 1 (E=VIL, G=VIL)

A (ADDRESSI

tAVAV

,w.~:...-__

----........

XX~

a (DATA Dun

*1---------

READ CYCLE 2

A IAODRESS!

tAVOV
tElEH

tAVAV

•

EICHIP ENABLEI

tAxaX_

I
tHOV

I+--

tEHaZ -

IT (OUTPUT ENABLE I
-tGLOVa IDATA OUT I

LtGHOZ_
HIGH·Z

HIGH,Z
_tGLOX_
_

tELaX--+

J0()( "

MOTOROLA MEMORY DATA

DATA VALID

I--

MCM6206

WRITE CYCLE 1 & 2 (See Note 11
MCMB21111-35

MCM~

Symbol

Ait
Symbol

Min

Max

Min

Max

Write Cycle Time

tAVAV

twc

35

tAVWL
tAVEL

tAS

0

-

46

Address Satup to Write Low
Address Setup to Enable Low

0

Address Valid to Write High
Address Valid to Enable High

tAVWH
tAVEH

tAW

25

-

Data Valid to Write High
Date Valid to Enable High

tOVWH
tOVEH

tow

15

Date Hold From Write High
Data Hold From Enable High

twHOX
tEHOX

tOH

Write Recovery Tima
Enable Recovery Time

twHAX
tEHAX

Chip Enable to End of Write
Enable Low to Enable High
Write Pulse Width

Unit

Not..

-

ns

-

-

ns

2

35

-

ns

-

-

20

-

ns

-

Ii

-

0

-

ns

-

twR

0

-

0

-

ns

2

tELWH
tELEH

tcw

25

-

35

-

ns

1

twLWH

twP

25

-

30

-

ns

3

Write Low to Output High-Z

twLOZ

twHZ

0

20

0

20

ns

4,5

Write High to Output Low-Z

twHOX

twLZ

5

-

5

-

ns

4,5

Parameter

NOTES:
1. A write cycle starts at the latest transition of a low E or low ViI. A write cycle ends at
the earliest transition of a high E or high ViI.
2. ViI must be high during all address transitions.
3. If is enabled, allow an additional 15 ns twLWH to avoid bus contention.
4. All high-Z and low-Z parameters are considered in a high or low impedance state when
the output has made a 500 mV transition from the previous steady state voltage.
5. These parameters are pariodically sampled and not 100% testad.

n-

1.73 V

1/0-

~

165

~30PF

r

(INCLUDING
SCOPE AND JIG)

Figure 1. Test Load

WRITE CYCLE 1

(Vii Controlled)

A (ADDRESS)

E(CHIP ENABLE)

VI (WRITE

ENABLE)

D (DATA )N)

o (DATA OUT) ---..:.:::=---<

MOTOROLA MEMORY DATA

•

MCM6206

WRITE CYCLE 2 (e Controlled)
'IAVAV

)~

A (ADDRESSI'

J~

!--IAVEL

IELEH

IEHAX-

IAVEH

Il

)

E(CHIP ENABLEI

~

twLWH

•

W(WRITE ENABLEI

Q (DATA

DUTI

\\\ \ \ \ \ \ \ \~

/111111
HIGH IMPEDANCE

HIGH IMPEDANCE

.1:::::.

IIJVEH

*-

o (DATA INI

DATAVAUD

.I

IEHDX

*

ORDERING INFORMATION
(Order by Full Part Numberl
MCM

Motorola Memory Prefix

T

T1TT
6208

X

XX

XX

Part Number - - - - - - - - - - - . . . .

................ ,"'-"",...........-..""
Speed (36=36 ns, 46=46 ns)
Package (P= Plastic DIP, J = Plastic SOJ)

Full Part Numbers-MCM6206P36
MCM6206J36
MCM6206J36R2

MCM6206P46
MCM6206J46
MCM6206J46R2

MOTOROLA MEMORY DATA
4-34

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

IMCM&206-2 01

Product Preview

32Kx8 Bit Fast Static Random
Access Memory

PPACKAGE

The MCM6206-20 is a 262,144 bit static random access memory organized as 32,768
words of 8 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. Stetic design eliminates the need for external clocks or timing strobes, while CMOS
circuitry reduces power consumption and provides for greeter reliability.
Chip enable (E) controls the power-down feature. It is not a clock but rather a chip
control that affects power consumption. When asserted false, the part reduces its power
requirements and remains in this standby mode as long as E remains high. Another control feature, output enable (G), allows access to the memory contents as fast as 8 ns
(MCM6206-20).
The MCM6206-20 is packaged in a 300 mil, 28 pin plastic dual-In-line package or a
28 lead 300 mil plastic SOJ package with the JEDEC standard pinout.
•
•
•
•
•
•

BLOCK DIAGRAM
A
A
-Vee

A
A

ROW

I:!==l DECODER

MEMORY ARRAY
1258 ROWS
1024 eOWMNSI

J PACKAGE
3OOMILSOJ
CASE 1'08

PIN ASSIGNMENT

Single 5 V Supply, ± 10%
Fast Access Time-20/25 ns (Maximum)
Chip Controls: Chip Enable (E) for Reduced-Power Standby Mode
Output Enable (G) for Fast Access to Date
Three State Outputs
Fully TTL Coftlpatible
High Board Density SOJ Package Available

A

300 MIL PLASTIC
CASE710A

"Vss

A

A14 [ 1 •

28

Vee

A12 [ 2

27

i

A7 [ 3

28

AI3

A8 [ 4

25

A8

A5 [ 5

24

A9

A4 [ 8

23

All

Ii

A3 [ 7

22

A2 [ 8

21

AIO

AI [ 9

20

E

AO [ 10

19

007

DOO I 11

18

DOB

001 I 12

17

D05

002

13

18

004

Vss

14

15

003

A
A

PIN NAMES
DOO-......---i

AO-A 14 ••••••.•.• Address
W. . . . . . . . . . Wri1e Enable

D08-t-t-H

E . . . • • . . • . • • Chip Enable
c; . . . . . . .. . OmpUl Enable
OClO-OQ7 •. Oata InpUlfOutpUl
VCC •.•• + 5 V Power Supply
VSS •.••.••.•.• Ground

AAA'AAAA

This document contains information on 8 product under development. Motorola reserves the right to change or cflSCOntinue this product without notice.

MOTOROLA MEMORY DATA
4-35

•

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MCM6207

Product Preview
256Kx1 Bit Static Random
Access Memory

•

The MCM6207 is a 262,144 bit static random access memory organized as
262,144 words of 1 bit, fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption for greater reliability.
The chip enable (E) pin is not a clock. In lees than a cycle time after E goes
high, the part enters a low-power standby mode, remaining in that state until E
goes low again. This feature provides reduced system power requirements without
degrading accesa time performance.
The MCM6207 is available in a 300 mil, 24 lead plastic DIP and in a 300 mil,
surface-mount SOJ package.
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Accees TIme: 20/25 ns
Equal Address and Chip Enable Access Time
Separate Data Input and Three State Output
Fully TTL Compatible
Low Power Operation: 140/130 mA Maximum, Active AC
High Board Density SOJ Package Available

300 MIL PLASTIC
CASE7Z4

~ACKAGE
~~'MILSOJ
CASE810A

PIN ASSIGNMENT
AO

BLOCK DIAGRAM
ILSB)

-vee
-vSS

1.

23

Vee
A17

A2

22

AlB

'A3

21

A15

A4

20

A14

A5

19

A13

AB

lB

A12

A7

17

All

16

Al0

AB

MEMORY MATRIX
256 ROWS x
1024 COLUMNS

24

Al

0

10

15

A9

W

11

14

D

12

13

E

VSS

(MSBI
PIN NAMES

o

AO-A17 . . . . . . . . . , ... , .. Address Input

Vii. . . . . . . . . . . , . . . . . . . Write Enable
E., ..... , .. , ...... , .. Chip Enable

o ....... , .. , ...... , ... Data Input

Q . . . . ,., . . . . . . . . . . . , . Data Output
VCC ... ,., ... , ... +5V Power Supply
VSS ' , . . . . . . . . , . • • • . . • .. Ground

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
4-36

MCM6207

TRUTH TABLE
E

W

Mode

VCC Current

Output

Cycle

H
l
l

X
H
l

Not Selected
Read
Write

ISB1,ISB2
ICCA
ICCA

High-Z
Dout
High-Z

Read Cycle
Write Cycle

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, It is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.6 to +7.0

V

Vin, Vout

-0.5 to VCC+0.5

V

Output Current

lout

±20

mA

Power Olssipation

Po

1.0

W

Tbias

-10to+85

·C

Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC

Temperature Under Bias (TA = 25·C)
Operating Tempereture

TA

Storage Temperature-Plastic

Tata

o to

+70

-55 to + 125

This CMOS memory circuit has been designed to meet the de and ac spacifications
shown in the tables, after thermal equilibrium has been established. The circuit is in
a test sockat or mounted on a printed circuit
board and transversa air flow of at least 500
linear feet per minuta is maintained.

•

·C
·C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher then recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA=O to 700e, Unl_ Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltege (Operating Voltege Rengel

VCC

4.&

&.0

B.&

V

Input High Voltage

VIH

2.0

-

VCC+0.3

V

Input Low Voltage

Vil

-0.5*

-

O.B

V

Symbol

Min

Typ

Max

Unit

-

±1.0

pA

-

±1.0

pA

mA

Parameter

*Vll (min) = -0.5 V dc; Vll (min) = -2.0 V ac (pulse width s20 ns)

DC CHARACTERISTICS
Parameter
Input Leakage Currant (All Inputs, Vin=O to VCC)

IlkllUl

Output leakage Current (E=VIH, Vout=O to VCC)

Ilkg(O)

-

ICCA

-

110

140

100

130

TTL Standby Currant (E=VIH, No Restrictions on Other Inputs)

ISBI

-

30

40

mA

CMOS Standby Current (E .. Vcc - 0.2 V, No Restrictions on Other Inputs)

ISB2

20

30

mA

-

0.4

V

-

-

V

Symbol

Typ

Max

Unit

Cin

4

pF

5

6
7

6

7

pF

AC Supply Current (lout = 0 mAl

MCM6207-20: tAVAV=20 ns
MCM6207-25: tAVAV=25 ns

Output low Voltage (lOl = B.O mAl

VOL

-

Output High Voltage (lOH = - 4.0 mAl

VOH

2.4

CAPACITANCE (f -1
- 0 MHz dV - 3 0 V TA - 25·C Periodically Sampled Rather Than 100% Testad)
Characteristic

Input Capacitance

All Inputs Except E

E
Output Capacitance

Cout

MOTOROLA MEMORY DATA

MCM6207

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA =0 to

+ 70o e,

Input TIming Measurement Reference Level . • . . • . . . . . I.S V
Input PulSe Levels : • • • • • . • • . • • . • . '.' . . • • . .0 to 3.0 V
Input. Risel Fa" TIma • . . • . . • • . • . . . • . • . . • . . . . . . S ns

Unless Otherwise Noted)

O\ltput TIming Measurement Reference Level . . . . . . . . . 1.5 V
Output Load. . '. . . . . . . . . • . . • . • . . • . . . . Sea Figure 1A

READ CYCLE (See Note 1)
Symbol

Pansmeter

•

Standard

MCMII2II7-211

Alternata

Min

MCNlII2II7-2&

Unit

Notes

no
no

2

25
25

.no

3

-

no

Max

Min

25

-

Read' ~ycle TIma

tAVAV

tRC

20

-

Address Access Time

tAVOV

tM

-

20

Enable Access TIma

tELOV

tACS

-

20

-

Output Hold from Address Change

tAXOX

toH

4

-

S

Max

Enable Low to Output Active

tELOX

tLl

4

-

S

-

no

4,S,6

Enable High to Output High-Z

tEHOZ

tHZ

0

8

0

10

no

4,S,6

Power UpTIme

tELICCH

tpu

'0

-

0

-

ns

Power Down TIma

tEHICCL

tpo

-

20

-

25

ns

NOTES:
1. Vii is high for read cycle.
2. A" read cycle timing is referenced from the last valid address to the first transitioning address.
3. Addressee velid prior to or coincident with 'E going low.
4. At any given voltage and temperature, tEHOZ max, is less than tELOX min, both for a given davice and from davice to device.
S. Transition is measured ±600mV from steady-state voltege with load of Figura lB.
6. This parameter Is sampled and not 100% testad.
7. Device is continuously selacted (E=VIL).

READ CYCLE 1 (See Note 7 Above)
tAVAV

\it

A (AODRESSI

/

~tAXOX
Q (DATA DUTI

PREVIOUS DATA VALID

ixxxxx

DATA VALID

tAVQV

A (ADDRESS)

-

READ CYCLE 2 (See Note 3 Above)
tAvAV

1~4_--- !flQY - -....

E(CHIP ENABLEI

Q (DATA DUT!

VCC

---+----t----{

DATA VAUD

tEHICCl

ICC
ISB

MOTOROLA MEMORY DATA

\l..

MCM6207

WRITE CYCLE 1 (W Controlled See NOUI

1)

MCMII2II7-20

MCMII2II7-3i

Standard

Alternate

Min

Max

Min

Max

Write Cvele TIme

tAVAV

twc

20

-

25

Addrass Setup TIme

tAVWL

tAS

0

-

0

Symbol
Parameter

Unit

Not.

-

ns,

2

ns

Addrass Valid to End of Write

tAVWH

tAW

16

twLWH

twp

12

-

20

Write Pulse Width

15

-

Oats Valid to End of Write

tOVWH

tow

8

-

10

-

Oats Hold TIme

twHOX

tOH

0

-

0

-

ns

Write Low to Output High-Z

twLOZ

twz

0

7

0

10

ns

3,4

Write High to Output Active

twHQX

tow

,5

5

3,4

twHAX

twR

0

-

ns

Write Recovery TIme

-

0

ns
ns
ns

ns

NOTES:
1. A write occurs during the OV8IIap of E low and W low.
2. All write cycle timing is referanced from the last valid add.... to the first transitioning addrass.
3. Trsnsition is masaurad ±500 mV from staady-state voltage with load in Figura lB.
4. Paramater is sampled and not 100% tested.

IAVAV
A (ADDRESS)
IAVWH

--------t---+_

twHAX

E(CHIP ENABLE)
twLWH - - - - + I

W!WRITE ENABLE)
IDVWH - - ....."'1- twHDX

o !DATA IN)

DATA VALID

HIGH·Z

o (DATA DUT)------~

AC TEST LOADS
TIMING LIMITS
+5V

+5V
480

0 -.....- - - -..
255

q-~-----.

30 pF
(INCLUDING
SCOPE AND JIG)

Figure 1A

255

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
4-39

The table of timing values shows either
a' minimum or a maximum limit for each
parameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that m'uch time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a
maximum since the device never provides
data later than that time.

•

MCM6207

WRITE CYCLE 2 (E Controlled See Note I)
MCMI2II7-20

MCMI2II7-2&

Standard

Alternate

Min

Min

Max

Write Cycle TIme

tAVAV

twc

20

26

Address Setup Time

tAVEL

tAS

0

-

Address Valid to End of Write

tAVEH

tAW

15

-

Enable to End of Write

tELEH

12

tELWH

Write Pulse Width

twLEH

twP

12

-

15

Enable to End of Write

tcw
tcw

Date Velid to End of Write

tOVEH

tow

8

-

10

Date H,old TIme

tEHOX

tOH

0

0

Write Recovery TIme

teHAX

twR

0

-

Symbol

'Parameter

•

12

Max

-

0

Unit

Notllll

n8

2

ns

-

ns

16

...,

, ,n8

16

-

20

0

-

na

3,4

'ns
n8
n8
na

NOTES:
1. A write occurs during the oveIIap of E low and 'Ii low.
2. All write cycle timing is referenced from the last valid address to the first transitionlng address.
3. If E goes low coincident with or after 'Ii goes low, the output will ramain in a high Impadance condition.
4. If E 9088 high coincident with or befora 'Ii goes high, the output will ramain in a high impadanca condition.

IAVAV
A (ADDRESS)
IAVEH

EICHIP ENABLE)

..

IELEH
'ELWH

IAVEL

WIWRITE ENABLE)

01

'EHAX

•

twLEH
IOVEH

DATA VAUD

D (DATA IN)

Q (DATA

IEHDX

HIGH·Z

DUT)

ORDERING INFORMATION
IOrder by Full Part Numberl

MCM

Motorola Memory Prefix

T

T11 T
6207

X

XX

XX

Part Number - - - - - - - - - - - . . . .

,ShiPPing Method (R2= Tapa & Reel, Blank = Railsl
Speed (20=20 ns, 26=26 nsl
Package (P=Plastic DIP, J=Plastic SOJI

Full Part Numm,rs-MCM6207P20
MCM6207Jio
MCM6207J2OR2

MCM6207P26
MCM6207J26
MCM6207J26R2

MOTOROLA MEMORY DATA
4-40

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM620S
MCM6209

Product Preview
64K X 4 Bit Static RAMs

• Single 5 V ± 10% Power Supply
• Fast Access Tme (Maximum):

•
•

•
•

AdcI..-

MCM62xx-20

20 ns

~~!~~~::
,
P PACKAGE

'

.,.

3DO MIL PLAS11C

J PACKAGE
3DO MIL $OJ

CASE 724

CASE 81DA

M~

z~:::~'

.,

3DO MIL PLAS11C

J PACKAGE
3DO MILSOJ

CASE71DA

CASE810B

MCMII209

Chip Enable
Ciutput Enable
20 ns
10 ns
MCM62xx-25
25 ns
25 ns
12 ns
Equal Address and Chip Enable Access Time
Output Enable (3) Festure for Inc:re-' System Rexibility and to 8iminate Bus
Contention Problems (MCM62m)
Low Power Operation: 1401130 rnA Maximum, Active AC
Fully TTL Compatible-Three-State Data Output
(xx=08 or 09)

~~

MC::"

The MCM6208 and MCM62m are 262,144 bit static random access memories organized
as 65,536 words of 4 bits, fabricated using Motorola's high-perfonnance silicon-gate CMOS
technology. Static design elimina1lls the need for external clocks or timing strobes, while
CMOS circuitry reduces power consumption for greater reliabHity.
The chip enable (EI pin is not a clock. In less than a cycle time after E goes high, the
part enters a low-power standby mode, remaining in that state until E goes low again. This
feature reduces system power requirements without degrading access time perfonnance.
The MCI\II62aI has both chip enable (E) and output enable (3) inputs, allowing greater
system flexibility. E"rther input, when high, will force the outputs to high impedance.

A6
A2

BLOCK DIAGRAM

A3
A4

MEMORY MATRIX
256 ROWS x
1024 COLUMNS

A12
A13

_Vcc
_VSS

A14

PIN ASSIGNMENT
MCM82118
AD 1.

24

Al

2

VCC
23 ~A15

A2

3

22 ~A14

A3

4

21 ~A13

A4

5

20

A5

8

19

A6

7

~A12
~ All
18 ~Alo

A7

8

17 ~DQO

A8

9

18

AS

10

15

11

14

12

13

E

Vss

~ DIll
~ DII2
~ DII3
~iii

Al

MCMII209
COLUMN liD

DOD

2

28 ~VCC
27 A15

Al

3

28

A14

A2

4

25

A13

A3

5

24

A12

A4

6

23 All

A5

7

22

Alo

AS

8

21

NC

A7

9

20

NC

AS

10

19

IlQO

AS

11

18

DIll

E 12
II 13

17

DII2

IIC 1.

AD

001
002
003

iii

iMCM62D9 ONLy) ii-'"""'-L-/

PIN NAMES
AO-A15. . • . • • Addreas Input
DQO.DQ3. • Da1a Input/Output
iii .......... Wri1e Enable
~ (MCII.m)91 .. Output Enable

E..........

Chip Enable

NC....... No Connection
VCC...• +5 V Power Supply
VSS. . . . . . . . . . . . Ground

Vss

14

This documont COI1IBins informalion on a pnxlJct under daveIopmont. _ _ 1110 ~ to change or dioconIinua 1his pmduct without notice.

MOTOROLA MEMORY DATA
4-41

16

DII3

15

\Ii

II

MCM6208·MCM6209

MCM8208 TRUTH TABLE

i

W

Mode

VCC Current

Output

Cycle

H
L
L

X

Not Selected
Read
Write

ISB1,ISB2
ICCA
ICCA

High-Z
Dout
High-Z

Read Cycle
Write Cycle

H
L

This device contains circuitry to protect the
inputs against' damage due to high stetic
voltages or electric fl8lda; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

-

MCM6209 TRUTH TABLE

II

E

G

W

Mode

Vee Current

1/0 Pin

H
L
L
L

X

X

H
L

H
H'
L

Not Selected
Read
Read
Write

ISB
ICCA
ICCA
ICCA

High-Z
Hlgh-Z
Dout
Din

X

This CMOS mamory circuit has bean dosigned to meat ths de and ac spacificetions
shown in the tables, after thermal equilibrium has bean established. The circuit is in

Cycle

Read Cycle

a test socket or mounted on a printed circuit
board and tranBV8"" air flow of at least 500
linear teat per minute is maintained.

Write Cycle

ABSOLUTE MAXIMUM RAnNGS (Sea Note)
Retlng

Symbol

Value

VCC

-0.5 to +7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/0)

lout

±2O

rnA

Power Dissipation (TA = 25·C)

Po

1.0

W

Tbias

-10to +86

·C

TA

oto +70

·C

Tstg

-55to +125

·C

Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC

Temperature Under Bias
Operating Temperature
Storage Temperature

Unit

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation ahould be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70·e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.6

5.0

6.5

V

Input High Voltage

VIH

2.0

-

VCC + 0.3

V

VIL

-0.5*

-

0.8

V

Max

Unit

±1.0

p.A

Parameter

Input Low Voltage
*VIL (mini = -0.5 V de; VIL (min) = -2.0 V ac (pulse width

:s 20 ns)

Unit

DC CHARACTERISnCS
Symbol

Min

Typ

Input Leakage Current IAlilriputs, Yin =0 to VCCI

IlkaUl

-

Output Leakage Current IE=VIH, Vout=O to VCC)

Ilkg(O)

-

-

Parameter

AC Supply Current lIout = 0 mAl

tAVAV=2Ons

-

ICCA

-

tAVAv=25ns

Output Low Voltage IIOL = 8.0 rnA)

VOL

-

Output High Voltage IIOH = -4.0 rnA)

VOH

2.4

TTL Standby Current

(E = VIH,

No Rastrictions on Othsr Inputs)

CMOS Stendby Current IE:.:VCC-0.2 V, No Restrictions on Other Inputs)

ISBI
ISB2

±1.0

p.A

110

140

rnA

100

130

30

40

rnA

20

30

rnA

0.4

V

-

V

-

CAPACITANCE (f= 1.0 MHz, dV=3.0 V, TA = 25·C, Periodicelly Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance

All Inputs Except E

E

I/O Capacitsnce

Symbol

Typ

Max

Unit

Cin

4
6

6

pF

5

7

CI/O

MOTOROLA MEMORY DATA

7
pF

MCM6208-MCM6209

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA=O to +70·e, Unless Otherwise Noted)
Output Timing Measurement Reference Level . • • . • • . . • 1.5 V
Output Load .•.•.••.•••• Figure lA Unless Otherwise Noted

Input TIming Measurement Reference Level • . • . . • . • •. 1.5 V
Input Pulse Levels • • . . • • . • . • • . • . . • . • • • . . .0 to 3.0 V
Input Rise/Fall Time . • . . . • . • . • . . . . • . . • . . . • • . • 5 ns
READ CYCLE (See Nota 1)

MCM6ZQ8.211
MCMII2lI9-2O

MCMII2IJII..2Ii
MCM620f.25

Alternate

Min

Max

Min

20

Symbol
Parameter
Standard

Units Notea

Max

Read Cycle TIme

tAVAV

tRC

25

-

ns

tAVOV

tAA

-

-

Address Access TIme

20

tELOV

tACS

-

20

25
25

ns

Enable Access TIme

-

Output Hold from Address Change

tAXOX

toH

4

5

-

10

3
0

-

4
0

Output Enable Access TIme

MCM6209

tGLOV

toE

Output Enable Low to Output Active

MCM6209

tGLOX

t12

Output Enable High to Output High-Z

MCM6209

tHZ

tGHOZ

ns
ns

-

12

ns

4

-

ns

6

0

8

ns

-

5
0

-

ns

10

ns

Enable Low to Output Active

tELOX

t12

Enable High to Output High-Z

tEHOZ

tHZ

Power UpTIme

tELICCH

tpu

0

-

0

-

no

Power Down Time

tEHICCL

tpD

-

20

-

25

ns

8

2

3

4,5,6
4,5,6
4,6,6
4,5,6

NOTES: 1. W 18 high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and tamperature, tEHOZ max is less than tELOX min, and tGHOZ max is less than tGLOX min, both for a
given device and from device to device.
6. Transition is measured ± 600 mV from steady-state voltage with load of Figure 1B.
6. This parametsr is sampled and not 100% tasted.
7. Device is continuously selected (E = VIL) and G= VIL (MCM6209 only).
READ CYCLE

1 (See

Note

7

Above)

~

......- - - - - - - - - - tAVAV ------------I~~,

A (ADDRESS) _

X

~tA-X~------~---------------------J ~----

n (DATA DUn

PREVIOUS DATA VALID

DATA VALID

READ CYCLE

2 (See Note 3

Above)

tAVAV

A (ADDRESS)

___+-__.....,.1-+----

tELOV

---+I

E(CHIP ENABLE)

ii (OUTPUT ENABlE)
(MCM82D9 ONLY)

n (DATA OUT)

F

DATA VALID

~----+-- tAVOV

_____ t~~c~ ___
VCC

SUPPLY CURRENT

ICC

ISB _ _ _ _ _ _ _ _...J'_

MOTOROLA MEMORY DATA

tEHICCL1

•

MCM6208-MCM6209

WRITE CYCLE 1

(iN Controlled.

See Notes 1 and 6)
Symbol

Parameter

II

MCM62D6-20
MCM8209-20

MCMII208-2Ii
MCM6209-2Ii

Max

Min

-

25
0

Standard

Alternate

Min

Writa Cycle Time

tAVAV

twc

Address Setup TIme

tAVWL

tAS

20
0
15
15
8
0
0
5
0

Address Valid to End of Writa

tAVWH

tAW

Write Pulse Width

twLWH

twP

Data Valid to End of Write

tOVWH

tow

Data Hold TIme

twHOX

tOH

Write Low- to Output High-Z

twLCZ

twz

Write High to Output ActNa

twHQX

tow

Writa Recovery TIme
NOTES: 1.
2.
3.
4.
5.
6.

-

20
20
10
0
0
5
0

-

7

-

Units Notes

Max

-

ns

2

ns
ns

no
ns

no

10

ns

-

no
no

3.4.5
3,4,5

twHAX
twR
A write occurs during the overlap of E low and W low.
All write cycle timing is referenced from the la81 valid address to the first transltloning address.
Transition is measured ±500 mV from steady-stete voltage with load in Figure lB.
Paremeter is sampled and not 100% tested.
At anv gNan voltage and temperature. twLCZ max is less than twHQX min both for a given device and from device to device.
MCM6209. if G goes low ooincidant with or after iN goes low. the output will remain in a high impedance state.

-

14--------

tAVAV

A (ADDRESS)
tAVWH

---------l*.....-t-

tWHAX

E(CHIP ENABLE)
tWLWH

W!WRITE ENABLE)

o (DATA (N)

a (DATA Dun

-------0(
AC TEST LOADS

+5V

+5V
480

480

30 pF
(INCLUDING
SCOPE AND J(G)

255

==

255

Figu~e

Figure 1A

MOTOROLA MEMORY DATA
4-44

1B

5 pF
(INCLUDING
SCOPE AND JIG)

MCM6208-MCM6209

WRITE CYCLE 2 (e Controlled, See Notes 1 and 5)
Symbol

Parameter

MCM62118-211
MCMII2IJII..2O

MCM82OII-2Ii
MCM8ZQI-2;

Standard

Alternate

Min

Max

Min

Write Cvele TIme

tAVAV

twc

20

-

25

Add..... Satup Time

tAVEL

tAS

-

Add..... Valid to End of Write

tAVEH

tAW

Enable to End of Write

tELEH

tcw

Enable to End of Write

IELWH

tcw

Write Pulse Width

twLEH

twP

Date Valid to End of Write

toVEH

tow

Date Hold TIme

tEHDX

tDH

Write Recovery Time

tEHAX

twR

0
15
12
12
12
8
0
0

0
20
15
15
15
10
0
0

NOTES: 1.
2.
3.
4.
5.

-

-

-

Unite Not..

Max

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

2

3,4
3,4

ns
ns

A write occurs during the overlap of E low and W low.
All write cycle timing i. referenced from the last valid address to the first transitloning address.
If E goes low coincident with or attar W goes low, the output will ramsin in a high impedance condition.
If E goes high coincident with or before W goes high, the output will remain in a high Impedance condition.
MCM6209, if G goes low coincident with or attar W goes low, the output will ramsln in a high Impedance stele.

IAVAV
A (ADDRESS)
IAVEH

E(CHIP ENABLE)
IAVEL

IELEH
IELWH

IEHAX

•

IWLEH

W(WRITE ENABLEI

IDVEH
D (DATA IN)

IEHDX

DATA VALID

HIGH·Z

n IDATA DUn

ORDERING INFORMATION
(Order by Full Part Numberl
MCM
Motorola Memory Prefix

--y-

T
82XX

Part Number - - - - - - - - - - - - - '

11
x

XX

XX

T

..._

......

' ' =T.......... ""',.....

Speed 120=20 os, .25=25 na)
Package IP=Plaatic DIP, J=Plastic SOJ)

Full Part Numbers- MCM6208P2O
MCM6208P25

MCM6208J20
MCM6208J25

MCM6208J20R2
MCM6208J25R2

MCM6209P20
MCM6209P25

MCM6209J20
MCM6209J25

MCM6209J20R2
MCM6209J25R2

MOTOROLA MEMORY DATA
4-46

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6226-30 1

I

Product Preview

128K X 8 Bit Fast Static Random
Access Memory,

•

The MCM6226-30'is a 1,048,576 bit static random acc8ss memory organized as 131,072
words of 8 bits, fabricated using high-performance silicon·gate CMOS (HCMOS) tech·
nology. Stetic design eliminates the need for extemal clocks or timing strobes, while
CMOS circuitry reduces power consumption and provides for greater reliability.
The output enable (G) feature allows fast access to the memory contents •
The MCM6226-30 is packaged in a 400 mil, 32 pin plastic dual·in·line package or a
32 lead 400 mil plastic SOJ package with the JEDEC standard pinout.
Single 5 V Supply, ± 10%
Fully Static-No Clock or TIming Strobes Necessary
Fast Access TIme-30 ns (Maximum)
Low Power Dissipation-l40 rnA
Thres Chip Controls; 5 Chip Select
S Chip Select
G for Fast Access to Data
Thres State Outputs
Fully TTL Compatibla

•
•
•
•
•

•
•

'~
,

J PACKAGE
4OOMILSOJ
CASEB:10

PIN ASSIGNMENT

Ne

,.

32

Vee

A 2

31

A

A 3

30

SINe

AI 4

28

VI

AI 5

28

A

AI 8

27

A

AI 7

28

A

A

AI 8

25

A

A

AI 8

24

6

AI 10

23

A

Alii

22

BLOCK DIAGRAM
A

_Vee

A
A
A

I:e=:::::j

ROW
DECODER

•

MEMORY ARRAY
(512 ROWS
2048 COLUMNS)

-

Vss

AI 12

A
A

A

.•

~s
21 ~D07

~008

DOD

13

20

DOl

14

,18

D02

15

18

~D04

Vss

18

17

~003

~005

~~~~'-~~~~~~------------~.--
D07-H-H

I

AAAAAAAA

s
W

PIN NAMES

AD-A16. • • • • • • • • • Addreos
W. . . . . . . . . . Write Enable
! . . . . . . . . . . . Chip Enable
S • . • • • • • . • . • Chip Enable
(; • • . • • • • . • Output Enable
DQO..DQ7 •• Data Input/Output
VCC •••• +5 V Power Supply

Vss ...........

Ground
NC • • • • • • . . No Connection

1-----Z
Write High to Output Low-Z
Write Recovery Tima

Symbol

tAVAV
tAVWL
tAVWH

twc

twLWH
toVWH
twHDX

twP
tow
tDH

twLaz

twHZ
tow
twR

tAS
t/>W

twHOX
twHAX

MCMI284-3O MCMI2II4-3& MCM82II44i MCMI2lI4-liIi
Unit N _
Min M_ 'Mln M_ Min Max Min Max
30
35
45
55
ns
0
0
0
0
ns
22.6
26
35
45
ns
17.6
.20
30
26
ns
3
15
12.6
20
25
ns
0
0
0
na
0
3
16
0
15
0
16
0
15
4,6
0
1\8
4,6
6
5
5
5
ns
O·
0
0
0
ns

-

-

-

-

-

-

-

-

-

-

-

-

-

-

NOTES:
1. A writs cvcIe &ta1'l8 at the ~ transition of a low Ei', low W, or high E2. A writs cvcIe enda at the earliest transition of a high Ei', high
W,orlowE2.
2. If W g088 low coincident with or prior to Ei' low or E2 high than tha outputs will ramain in a high impedance atata.
3. Durlng this tima the output pins may be in the output atata. Signals of oppoeite phaee to the outpul8 muat not be applied at this time.
4. All higl>-Z and Iow-Z perama\8r8 are coneidered In a high or low impedance &tate when the output haa made a 500 mV traneition from
the previoua ataedy atata voltage.
6. Theee parameters are periodically sampled and not 100% teated .

I.....---------AVAV--------.....
·I

~----------------------~~I~------A (ADDRESSI --fi't.__________________...JA
- - - - - - - - ' A V W H - - - - - - ·..·~I t--··.j.I-'wHAX

......

!"'1
..

E(CHIP ENABLEI

!I \~------------_r!--~/
"'1
..
- - -

W(WRITE ENABLEI -----+i--------~~

~ IAVWL - J

IWLWH-----'l·~1

)(r--------------

,....,-IDVWH.: ... ,

---r--'

-Vce
-Vss

AI
A2 ---,~---,
A3
A4

MEMORY MATRIX
128 ROWS x
128 COlUMNS

J PACKAGE
3OOMILSOJ
CASE810A

PIN ASSIGNMENT
DUAL-IN-LiNE
A4

I.

22

Vcc

A5

2

21

A3

A8

3

20

A2

A7

4

19 AI

AB

5

lB

A9

8

17~ NC

AID

7

All

8

E 9
i! [ 10

A5 ---,~---,

Vss [

AB

PLASTIC

CASE738A

II

~ AD

18 ~ 000
15 ~ DOl
14
13

P002

~ 003

12~ W

000 --....,~---,

SMALL OUTLINE

001

A4 [ 1.

002 - - - y J ' 1 . '

A5 I 2

003

iii

s---=
a
1.10

1.2

..

;: 0.80

.. O.B

!<'" 0.70

!'" 0.7
O.B'----...L...--.....L---.L...----'---.......I
4.0
4.5
5.0
5.5
B.O
B.5

0.~04..0-l-_--':20-l-~--L-2..L0~---'40---'---'BO....JL......JBL...0-L-l0LO-L-12'&'0...J
TA. AMBIENT TEMPERATURE (DC)

VEC. SUPPLY VOLTAGE (VOLTS)

Figure 8. Address and Enable Access Times versus
Temperature

!

Figure 9. Address and Enable Access Times versus
Supply Voltage

I

1.5
.. 1.4

~

I!!

j

1.1

!!;

i

1.0

~
~

0.9

~

i

0.7 L....J..............__L-L_I_-L....L..J...........L...&.-.&.-'--'L....JL....J....I.-L...J
4.0 4.2 4.4
4.B 4.B
5.0 5.2 5.4 5.6
5.B 6.0

O.B '--L......JL......JL....JL....JL....JL....J---'---'--:':---'--:':---L~---L~:-'

-40

-20

20

40

BO

BO

100

0.8

i

120

TA. AMBIENT TEMPERATURE (DC)

VCC. SUPPLY VOLTAGE (VOLTS)

Figure 10. Data Setup Time versus Temperature

Figure ". Data Setup Time versus Supply Voltage

120

4

4
VOU!. OUTPUT VOLTAGE (VOLTS)

V""I' OUTPUT VOLTAGE (VOLTS)

Figure 12. Output Sink Current versus Output Voltage

Figure 13. Output Source Current versus Output
Voltage

MOTOROLA MEMORY DATA
4-79

•

MCM6287

ORDERING INFORMATION
(Order by Full Part Number)

T--JCM

Motorola Memory Prefix _ _ _ _ _
Part Number

j

x

XX

XX

T T_
~

Shipping Method (R2=Tape & Reel,
Blank = Rails)

Speed (25=25 ns, 35=35 ns)
' - - - - - - - - - Package (P=Plastic DIP, J=Plastic SOJ)

•

Full Part Numbers-MCM6287P25
MCM6287J25
MCM6287J25R2

MCM6287P35
MCM6287J35
MCM6287J35R2

MOTOROLA MEMORY DATA

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6287-15
MCM6287-20

Advance Information

64K X 1 Bit Static Random Access
Memory
The MCM6287-15/MCM6287-2O is a 65,536 bit static random access memory organized
as 65,536 words of 1 bit, fabricated using Motorola's high-perfonnance silicon-gate CMOS
technology. Stetic design eliminates the need for external clocks or timing strobes, while
CMOS circuitry reduces power consumption for greater reliability.
The chip enable IE) pin is not a clock. In less than a cycle time after E goes high, the
part enters a low-poWer standby mode, remaining in that state until E goes low again.
This feature provides reduced system power requirements without degrading access time
performance.
The MCM6287-15/MCM6287-2O is available in a 300 mil, 22 lead plastic DIP or a 24
lead, 300 mil, surface-mount SOJ packaga. All feature JEDEC standard pinout.
•
•
•
•
•
•
•

PLASTIC
CASE738A

~PACKAGE

~ ~MILS().J
CASE810A

PIN ASSIGNMENT

Single 5 V ± 10% Power Supply
Fast Access Time: 15/20 ns
Equal Address and Chip Enable Access TIme
Low Power Operation: 140/130 mA Maximum, Active AC
High Board Density SOJ
Three State Data Output
Fully TTL Compatible

DUAL-IN-LINE

BLOCK DIAGRAM
tLSB)

-Vee

A6

-Vss

A3

A4

MEMORY MATRIX
128 ROWS x
512 COLUMNS

A5

AO 11.

22

Vee

Al I 2

21

A15

A2 I 3

20

A14

A3

4

19

A13

A4

5

18

A12

A5

6

17

A6

7

18

A7

8

15

a

9

14

W

10

13 ~ o

11

12

Vss

A13

All

~ AID
~ A9
~ A8
E

A14
IMS8)

SMALL OUTLINE

A15

COLUMN 110

Q

PIN NAMES
AO-AI6 .•.•...•..•. Addrass Input
W. . . . . . . . . . . . . . . Write Enable

'E • . . • . • . . . • . • • . • • Chip Enable
D • . • . • . . . • . • . . . . . • Data Input
a . . . . . . . . . . . . . . . .Data Output

VCC . . . . . . . . . . . . Powar(+6V)
VSS ......•.•..•..•. Ground
NC • • • . • . • • • . • . . No Connection

this ~ment con1llins information on a new product. Spec/fk:atlona and information henrin .... subject 10 change without notice.

MOTOROLA MEMORY DATA
4-81

AO I 1.

24

Vee

Al I 2

23

A15

A2 I 3

22

A14

A3 I 4

21

A13

A4 I 5

20

A12

A5 I 6

19

Ne

Ne I

7

18

A11

A6 I 8

17

AID

A7

9

16

A9

a

10

15

A8

W[

11

14

o

Vss I

12

13

I

•

MCM6287-15·MCM6287-20

TRUTH TABLE

E'
,H
L
L

Mode

VCC Current

Output

Cycle

Not Selected
Reed
Wri1e

ISB1,ISB2
ICtA, .
ICCA

High-Z
Dout
High-Z

Read Cycle'
Wri1e Cycle

W

X
H
L'

-

",

hi!Jh-

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Power Supply' Voltage

•

Valua

shawn in the tables, after tharmel equiHb·
rium has been established. The circuit Is In
a test sockat or mounted,on a printed circuit
board and lrensvarae air flow of at Iaast 500

V

Vee

-0.5 to +7.,0
-0.5 to VCC+0.5

Ou/put Current (per 110)

lout

±2O

mA

Power DlsIIipatlon (TA =25"C)

Po

1.0

W

V,

Tblas

-10,to +85

DC

Operating Temperature

TA

Oto +70

DC

Storage Temperature- Plastic

Tsta

-55 to +125

"C

Temper8ture Undar Bias

This CMOS memory circuit has bean designed'to meat the de and ac speclflcetiona

Unit

Yin, Vout

Voltage Relative to VSS for Any
Pin Excapt VCC

This device contains circuitrY to protact the,
inputs against damage due to high ststic
voltages or electric fields; howevar, it is advised that normal preCautiona be taken to
avoid application of any voltage higher than
maximum reted voItagas to this
impedance circuit.
'

linear feet per minute, " rnitintalned.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to ?ODe, Unleaa Otherwis8 Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.0

Vee + 0.3

V

Input Low Voltaga

VIL

-0.5*

0.8

V

Param_r

-

*VIL (m,n)= -0.5 V de; VIL (min) = -2.0 V ac (pules width !S 20 na)

DC CHARACTERISTICS
Symbol

Min

.Typ

Input Leakage Cunant (All Inputs, Vin=O to VCC)

IIIc

A (ADDRESS)

ll" IOUTPUT ENABLE)

--------11------+--

D (DATA IN)
tOHOZ

o (DATA OUT) --------+ HIGH·Z

-----1---

MATCH

MOTOROLA MEMORY DATA
5-14

MCM4180

WRITE CYCLE (See Note 1)
Characteristic

Symbol
Standard Alternate

MCM4180-22

MCM4111O-2&

MCM4180-30

Min

Max

Min

Max

Min

30

35

tAVAV

twc

25

twLWH

twcvv

18

Address Setup to Beginning of Write

tAVWL

tAS

0

-

Address Valid to End of Write

tAVWH

tAW

18

-

20

Data Valid to End of Write

tOVWH

tos

10

12

Data Hold from Write End

twHOX

tOH

0

-

-

0

-

Write Cycle TIme
Wr~e

Pulse Width

20

0

Max

-

Unit

25

-

14

-

ns

0

-

ns

25

0

ns
ns
ns

Write Low to Output High-Z

twLOZ

tHZ

0

9

0

10

0

12

ns

Address Hold from Write End

twHAX

twAH

0

-

0

-

0

-

ns

Wr~e

Low to Match Assert

twLMX

twCH

0

15

0

15

0

18

ns

Wr~e

High to Match Valid

twHMV

twCA

-

22

-

25

-

30

ns

twHOX

tLl

5

-

5

-

5

-

ns

Write High to Output Active

Notes

ns

NOTES:
1. A write occurs during the overlap of Vii low and CLR high.
2. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% tested.

WRITE CYCLE
(FROM A READ CYCLEI

(FROM A COMPARE CYCLE)
. .- - - - - t A V A V - - - -.....

A (ADDRESS)

G (OUTPUT ENABLE)

Vi (WRITE ENABLE)

D (DATA IN)

-----+--<

n (DATA OUT)

MATCH

(ASSERTED)

MOTOROLA MEMORY DATA
5-15

2

2

MCM4180

CLEAR CYCLE (See Note 1)
Symbol

Charactaristlc

Standard Altarnate

0Ji Low to Inputs Recognized

A

1J
W

(Clear Cycle Time)

0
~ Pulse Width

0Ji Low to Inputs Don't Care

A

1J
0

W
0Ji Low to Match Assert
0Ji Low to Output High-Z

MCM418G-22

MCM4180-25

MCM4180-30

Min

Max

Min

Max

Min

Max

-

70

-

70

-

Unit

Not..

70

ns

2

2

tCLAV
tClGV
tclWV
tclOV

tcR
tcR
tCR
tCR

tClCH

tClP

25

-

30

-

36

tcx
tcx
tcx
tcx

0

-

0

-

0

-

ns

tClA)(
tclGX
tClOX
tclWX
tCLMX

tMH

0

15

0

18

0

20

ns

tclOZ

tcz

-

15

-

18

-

20

ns

ns

3

NOTES:
1. The add ....., date, W, and 1J inputs are a don't care during a clear cycle.
2. The clear cycle is initiated st the falling edga of 0Ji.
3. Transition is measured ±500 mV from steady state voltaga with load of Fillure lb. This parameter is sampled and not 100% tested.

II
CLEAR CYCLE

(FROM A COMPARE CYCLE)

IFROM A REAO CYCLE)

AIADDRESSI

~

r-""lx

tcLAX1

~

_...,.-----J

ICLAV

----XXXX>f=

~-

1
f4
..

II (OUTPUT ENABLE)

CUi (Cl£AR)

W(WRITE ENABLE)

D (DATA IN) ---~I---<

Q (DATA

tCLOZ:l.._ _ __
OUT) _ _ _ _ _J }-

MATCH

HlGH·Z----

---+----HIGH·Z-------

IASSERTEO)

MOTOROLA MEMORY DATA
5-16

MCM4180

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

TIT 1
4180

X

XX

XX

Part Number - - - - - - - - - - - '

"___ 102._ ..... _ - _
Speed (22=22 ns, 25=25 ns, 30=30 ns)
Package (P=Plastic DIP, J=Plastic SOJ)

Full Part Numbars-MCM4180P22
MCM418OJ22
MCM418OJ22R2

MCM4180P25
MCM418OJ25
MCM418OJ25R2

MCM4180P30
MCM418OJ30
MCM418OJ30R2

II

MOTOROLA MEMORY DATA
5-17

-

MOTOROLA

SEMICONDUCTOR - - -_ _ _ _ _ _ _ _ _ __
TECHNICAL DATA

MCM4180-20

Product Preview

4K X 4 Bit Cache Address Tag
Comparator .
.

--,
PLAmC

The MCM4180 is a 16,384 bit cache address tag comparator organized as 4096 tags of 4
bits, fabricatec:J using Motorola's high-performance sllIcon-gata CMOS technologv. The d&vice integrates a 4K x 4 SRAM core with an on-board comparator for efficient implementa..
tion of a cache memory.
The device has a CLR pin for flash clear of the RAI\!I, useful for system initialization.
The MCM4180 compares RAM contenta with current input data. The rasull is either an
active high match level for a cache hit, or an active low level for a cache miss.
The MCM4180 is available in 22 lead plastic DIP and 24 lead SOJ packages.

II

•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Address to Match Time:
Fast Data to Match TIme:
Fast Read of Tag RAM Contenta:
Flash Clear of the Tag RAM (CLR
Pin and Function Compatible with

J PACKAGE
3DOMILSOJ
CASE810A

20 ns max
PIN ASSIGNMENT

10 ns max

20 n8 max
DUAL-IN-LiNE

Pin)
MK41H80

BLOCK DIAGRAM
MEMORY
MATRIX
128 ROWS
x 128 CDWMNS

AD-A6

000-003

CASE73IA

----+---.

22

Vce

A5 I 2

21

A3

A6 I 3

20

A2

A7 I 4

19 AI

A6 I 5

18

A9

17 'CUi

jj

6

AD

AID I 7

16

DQ3

All I 8

15

DDZ

11
W

9

14

DOl

10

13

DOD

11

12

MATCH

VSS

COLUMN
DECODER

SMALL OUTLINE

~ VCC
~ A3

A4 11.

24

1.5 I 2

23

A6 I 3
1.7 14

22
21

PIN NAMES

A6 I 5

20

AD

AO-A11 •.•......•. Add..... Inputs
'Ii. . . . . . . . . . . . . . . Write Enable
G .. .. .. .. .. .. .. Output Enable
QJI. . . . . . . . . . . . Rash Clear Input
MATCH . • . . . . . . Mstch (Hit) Output
000-003 . . . . . . . Data Input/Output

A9 I 6

19

NC

NC I 7
AID I 8

18

VCC • . . . . . • . • +5 V Power Supply
VSS •....••••••••••. Ground

NC . . . . . • • . . . . . • No Connection

This document contains information on • product under

A4 11.

All I 9

11 10
W 11
Vss 12

-.,ment. Motorola raaarvaa the right to chlnge or discontinue this product without notice.
MOTOROLA MEMORY DATA
5-18

~ A2
Al

ClJi
D03
16 DDZ

17

15

DOl

14 DDD
13

MATCH

MCM4180-20

TRUTH TABLE

w

G"

CLR

DOO-DQ3

Match

Mode

H
L
H

H

X

X

H
H
H
L

Compare Din
Din
Dout
High-Z

Valid

X

Assert
Assert
Assert

Compare
Writa
Read
Claar

L

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fl8lds; however, it is advised that normal precautions be taken to
avoid application of any voltage highar than
maximum rated voltages to this high impedance circuit.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS=O V)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
ExceptVCC
Output Current

Match Output
1/0 Pins, Per 1/0

a

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

VinlVout

-0.5 to VCC+0.5

V

lout

40
20

rnA

Power Dissipation (TA = 25 C)

PD

1.0

Operating Temperature

TA

Oto +70

Storage Tempereture

Tsta

-55 to +125

Temperature Under Bias

Tbias

-10to +85

W

ac
ac
ac

II

NOTE: Permanent davioe damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extsnlled
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 7O"C, Unless Othatwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS=O V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.6

6.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.6*

-

0.8

V

Parameter

'. = - 3.0 V ac (pulse WIdth :$20 ns)
*VIL min = - 0.5 V de; VIL min
DC CHARACTERISTICS

Symbol

Min

Max

Unit

Input Leakage Current (All Inputs Vln =0 to VCC)

Charactarlatlc

IlkgUl

~

±1.0

,.A

Output Leakage Current, Except Match Output «;=VIH, Vout=O to VCC)

Ilkg(O)

-

±1.0

,.A
rnA

AC Supply Current (lout=O rnA, tAVAV=tAVQV max)

ICCA

-

140*
0.4

V

-

V

Output Low Voltage (1/0 Pin.: 10L =8.0 rnA, Match Output: 10L = 12.0 rnA)

VOL

-

Output High Voltage (l10 Pins: 10H = -4.0 rnA, Match Output: 10H = -10.0 rnA)

VOH

2.4

*ICC ectiva current for the claar cycle exceeds this specifICation. However, this Is a transient phenomenon and will not affect the power
dissipation of the device. Good decoupling of the local power supply should always be used.

CAPACITANCE (f=1.0 MHz, dV=3.0 V, TA=25aC, Periodically Sampled Rather Then 100% Tested)
Characteristic
Input Capacitance

1/0 Capecitance
Match Output Capecitance

MOTOROLA MEMORY DATA
5-19

Symbol

Typ

Max

Unit

Cin

4

5

pF

Cout

5

7

pF

Cmatch

6

7

pF

MCM4180-20

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5 V

± 10%, TA=O to + 700C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . • • • . • • .. 1.5 V
Input Pulse Levels • • . . . • . • • . • • . • • • . • . • . • • 0 to 3.0 V
Input RiselFall Time • . . . • . . • . • . . • • . . • . • . • • . . . 6 ns

Output Timing Measurement Reference Level . • . • . . • . • 1.6 V
Output Load (1/0 Pins) • . . • . . • . • • . . . . . . • . See Figure I.
Output Load (Match Output) • . . . • • • • . . • • . • See Figure Ie

READ CYCLE (See Note 1)
Symbol

Charactarlstlc

II

Standard

MCM418O-31

A1tamat.

Min

Unit

Max

-

ns

20

ns

-

9

ns

5

-

toEL

3

-

IGHQZ

10EZ

-

8

IGLMX

tcH

0

15

ns
ns
ns
ns

Read Cycle Time

tAVAV

tRC

20

Address Access Time

IAVQV

1M

-

~ Access Time

IGLQV

toEA

Output Hold from Address Change

tAXQX

10H

G Low to Output Active

IGLQX

~ High to Outpul High-Z
~ Low to Match Asasrt

No_

2
2

NOTES:
1. CLR=VIH, iiii=VIH continuously during read cycles.
2. Transition is measured ± 500 mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tasted.

READ CYCLE

Ii (CONTROLLED)

(ADDRESS CONTROLLED)

~-

IAVAV
A (ADDRESS)
IAVDV

l: (OUTPUT ENABLE)

k

IAVAV

IGLDX
Q

IOATA OUT)

DATA VALID

--HIGH·Z

IASSERTED)

MATCH

VALID

AC TEST LOADS
+5V

+5V

+5V

481

481

305

Q-.-------...
255

Q-.----~

=::30pf
(INCLUDING
SCOPE AND JIG)

Figura 1a

MATCH .....- - - -..
5 pF
IINCLUDING
SCOPE AND JIG)

255

Figura 1b

MOTOROLA MEMORY DATA
5-20

130

=~ 50pf
ONCLUOING
SCOPE AND JIG)

Flguralc

MCM4180-20

COMPARE CYCLE (Sea Note 11
MCM4180-ZO

Svmbol

Characteristic

Standard

Alternate

Min

Max

Unit

Notea

Compare Cvele TIme

tAVAV

tc

20

-

ns

Addrea Valid to Match Valid

tAVMV

tACA

-

20

ns

G High to Match Valid

IGHMV

tGCA

15

ns

Data Valid to Match Valid

tDVMV

tDCA

-

10

ns

Match Hold from ~ Low

tGLMX

tcH

0

15

ns

Match Hold from Address Change

tAXMX

tACH

5

ns

Match Hold from Data Invalid

tDXMX

tDCH

3

~ Low to Output Active

tGLOX

tLZ

3

-

ns

2

~ High to Output High-Z

tGHQZ

tHZ

-

8

ns

2

ns

NOTES:
1. A compare cycle is performed when CUI, Vii, and ~ are all high.
2. Transition is measured ± 500 mV from ateady atate voltage with load of Figure lb. This paramater is sampled and not 100% tasted.

II

COMPARE CYCLE

(ii CONTROLLED)

(ADDRESS CDNTRDLLEDI

A (ADDRESSI

ii (OUTPUT ENABLEI

---+-------+---

4--><=

- - - -.....

o (DATA IN)
'GHOZ
Q (DATA OUT)

---------+ HIGH·Z -----+--

MATCH

MOTOROLA MEMORY DATA
5-21

MCM4180-20

WRITE CYCLE (See Note 1)
Symbol
Characteristic

MCM4111O-211

Alternate

Min

Max

-

Write Cycle TIme

tAVAV

twc

20

Write Pulse Width

twLWH

twfYI

14

Address Sstup to Beginning of Write

tAVWL

tAS

0

Unit

nli

tAVWH

tAW

16

Data Valid to End of Write

IDVWH

tDS

10

-

ns

Data Hold from Write &lei

twHDX

tDH

0

-

ns

Write Low to Output High-Z

twLCZ

1HZ

0

8

ns

Address Hold from Write End

twHAX

twAH

0

-

ns

Write Low to Match Asesrt

twLMX

twCH

0

15

' ns

Write High to Match Valid

twHMV

twCA

-

20

ns

Write High to Output Active

twHQX

ILZ

3

-

ns,

Of Write

Not..

ns

-

Address Valid to End

II

Standard

ns'
'ns

NOTES:
1. A write occurs during ths overlap of W low and
high.
2. Transition is measurad ±500 mV from steady state voItaga with load of Figura lb. This paramatar is sampled and not 100% tested.

m

WRITE CYCLE
(FROM A COMPARE CYCLE)

(FROM A READ CYCLE)

A (ADDRESS)

ii (OUTPUT ENABLE)

IV (WRITE ENABLE)

o (DATA I N ) - - - - + - <

o (DATA OUT)

MATCH

(ASSERTED)

MOTOROLA MEMORY DATA
5-22

2

2

MCM4180-20

CLEAR CYCLE (See Note 11
Symbol
Characteristic

CLR Low to Inputs Recognized
(Clear Cycle Time)

A

i;

W
D

MCM41. .20
Unit

Not..

70

ns

2

2

Standard

Altarnata

Min

Max

tcLAV
tcLGV
tcLWV
tCLDV

tCR
tCR
tCR
tCR

-

tcLCH

tCLP

20

-

ns

tClA)(
tcLGX
tCLDX
tcLWX

tex
tcx
tcx
tcx

0

-

ns

CLR Low to Match Assen

tCLMX

tMH

0

15

ns

CLR Low to Output High-Z

tcLOZ

tel

-

15

ns

aJi" Pulse Wtdth
aJi" Low to Inputs Don't Care

A

i;
D

W

3

NOTES:
1. The address, data, W, and i; inputs are a don't care during a clear cycle.
2. The clear cycle is initialed at the falling edge of aJi".
3. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This paramatsr is sampled and not 100% tested .

CLEAR CYCLE
IFRDM A COMPARE CYCLE)

fFROM A READ CYCLE)

AfADDRESS)

~~-lxxxxxxxr
C""-O-----ICLAV

~-

GfDUTPUT ENABLE)

CLR fCLEAR)

W(WR)TE ENABLE)

o fDATA )N) - - - - i - - - (

Q fDATA

1CLOZ:lL-_ __
OUT) _ _ _ _--J}-

MATCH

HIGH·Z----

(ASSERTED)

MOTOROLA MEMORY DATA

•

MCM4180-20

ORDERING INFORMATION
IOrder by Full Part Number)

MCM

Motorola Memory Prefix

T

J 1T1
4180

X

XX

XX

Part Number _ _ _ _ _ _ _ _ _ _
....J

_"_'R2-T........ _="'"
Speed (20=20 ns)

,

Package (P=Plastic DIP, J=Plastic SOJ)
Full Part Numbers-MCM4180P20
MCM418OJ20
MCM418OJ2OR2

II

MOTOROLA MEMORY DATA
5-24

,

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6292

16K x 4 Bit Synchronous Static RAM
with Transparent Outputs
The MCM6292 is a 65,536 bit synchronous static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's second-generation high-performance
silicon-gate CMOS (HCMOS III) technology. The device integrates input registers, high
speed SRAM, and high-drive capability output latching onto a single monolithic circuit for
reduced perts count implementation of cache data RAM and writeable control store
applications.
Synchronous design allows precise cycle control with the use of an external clock (K),
while CMOS circuitry reduces the overall power consumption of the integrated functions
for greater reliability.
The address (AO-A13), data (00-03), write (W), and chip enable fE) inputs are all clock
(K) controlled, positive-edge-triggered, noninverting registers.
The MCM6292 provides transperent output operation when K is low for access of RAM
data within the same cycle (output data is latched when K is high).
Write operations are intemally self-timed and initiated by the rising edge of the K input.
This feature eliminates complex off-chip write pulse generation and provides increased
flexibility for incoming signals.
The MCM6292 is available in a 300-mil, 2B-pin plastic DIP as well as a 4OO-mil, 2B-pin
plastic SOJ package.
• Single 5 V ± 10% Power Supply
• Fast Access and Cycle Times: 25/30/35 ns Max
• Address, Data Input, E, and WRegisters On-Chip
• Transparent Output Latch for Access Within the Same Cycle
• High Output Drive Capability
• Internally Self-TImed Write Pulse Generation
• Separate Date Input and Data Output Pins
• High Board Density SOJ Package Available
• Typical Applications: General-Purpose Buffer Storage, Writeable Control Store, Data
Cache, or Cache Tag

~

300 MIL PLASTIC
CASE710A

~KAGE
PLASTIC
CASE 810

PIN ASSIGNMENT
A5

1.

28

A8

2

A7

3

27 ~ A4
28 ~ A3

A8

4

25

A9

5

24

AID

8

23

All

7

22

A12

8

21

A13 9

20

10

19

Dl

11

18

E 12

Vss

BLOCK DIAGRAM

14

..

~ A2
~ Al

~ AD

~ D3
~ 02
~ 03

~ 02
~ 01
17~ no

00

K 13

Vee

18 ~ W
15

~ VSSO*

*For mInImum cycle/low noise
appncations, VSSQ should be
isolated from VSS.

PIN NAMES
AO-A13. . . . . . . . . Address Inputs

w. . . . . . . . . . . . . Write Enable

E . . . . . . . . . . . . . . Chip Enable

no
01
02
D3

MOTOROLA MEMORY DATA
5-25

DO-D3 . . • . • . . . • • • Data Inputa
QO-Q3 • • • • • • . . . . Data Outputs
K . . . • . . . . . . . . . . Clock Input
Vee . . . . . . . + 5 V Power Supply
Vss . . . . . . . . . . . . • . Ground
VSSQ . . . . . Output Buffer Ground

..

MCM6292

TRUTH TABLE

w

Operadon

QO-Q3

L

L

'Write

HighZ

L

H

Read

Dout

H

X

Not Selected

HighZ

r

-

NOTE: The value. of E and
tha K rising edge.

W are valid inputs for the setup and hold times reiatova to

ABSOLUTE MAXIMUM RATINGS (Voltagea referenced to VSS = Vssa=O V)
Symbol

Value

Unit

VCC

-0.5,to +7.0

V

Vln, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA =25°CI

PD

1.0

W

Tbia.

-10 to +85

DC

Radng
Power Supply, Voltage
Voltage Relative to VsslVssa for Any
Pin Except VCC

Temperature Under Bia.

II

Operating Temperature

TA

Storage Temperature

Totg

o to

+70

-55 to +125

This device contains circuitry to protect the
inputs againat demage due to high atatic
voltages or electric fields; however, it is edvised that normal precautions be taken to '
avoid appllcatlon of any voltage higher then
maximum rated voltages to this highimpedance circuit.
This is a synchronous device. All synchronous Inputs must meat the apecified setup
and hold times with atable logic levals for
ALL rising edges of clock (K) while the device i. selected.
This device contains circuitry that will ensure the output devices are in High Z at
pOWer up. Care should be takan by the user
to ensure that all clocks are at VIL or VIH
during pOWer up to prevent spurious read
cycles from occurring.

°c
°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be reStricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%, TA=O to 70°C, Unless Otherwise Notedl

-

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss - Vssa = 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.0

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Parameter

*VIL (min) = -0.5 V de; VIL (min) = -3.0 V ac Ipulse width ",20 n.)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin=O to VCC)

Ilkg(1)

-

±1.0

p.A

OUtput Leakage Current (I=VIH, Vout=O to VCC, Outputs must be high-Z)

IlkolO)

Parameter

AC Supply Current (E=VIL. lout = 0 mA, Alllnputs=VIL or VIH, Cycle
Time"IKHKH min)

ICCA

-

Stsndby Current (E=VIH, VIH .. 3.0 V, VIL",0.4 V, lout=O mA, Cycle
TIme .. tKHKH min)

ISBI

-

55

mA

VOL

-

0.4

V

,VOH

2.4

-

V

Symbdl

Typ

Max

Unit

Cin

4

6

pF

Cout

7

10

pF

Output Low Voltage 1I0L = 12.0 mAl
Output High Voltage 1I0H = -10.0 mAl

±1.0

p.A

140

mA

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA =25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance
Output Capacitance

MOTOROLA MEMORY DATA
5-26

MCM6292

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC;5.0 V

± 10%,

TA;O to

+ 70 o C,

Input Timing Measurement Reference Level . . . . . . . . .. 1.5 V
Input Pulse Levels . . • . • . . • . . . . . . . . . . . . . . . 0 to 3.0 V
Input RiselFall Time . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns

Unless Otherwise Noted)

Output Timing Measurement Reference Level . . . . . . . . . 1.5 V
Output Load • . . . . . . . . . See Figure lA Unless Otherwise Noted

READ CYCLE (See Note 1)
Symbol

Parameter

MCM6292-25

MCM6292-30

MCM6292-35

Min

Max

Min

Max

Min

30

-

35

Reed Cycle Time

tKHKH

25

-

Clock Access Time

tKHQV

Data Valid from Clock Low

tKLQV

-

25
10

Output Hold from Clock Low

tKLOX

0

-

Clock Low to Q High Z (E; VIH)

tKLOZ

Clock Low Pulse Width

tKLKH

Clock High Pulse Width

A

W
E
A

W

10

tEVKH
tAVKH
twHKH

5

-

tKHEX
tKHAX
tKHWX

3

-

5
5

tKHKL

E

Setup Times for:

Hold Times for:

-

Max

Unit

Notas

2

30

-

-

ns

-

'35

ns

4,6

-

13

-

15

ns

5,6

-

ns

3,6,

ns

3,6

0

-

0

-

13

-

5

-

5

5

-

5

5

-

5

-

3

-

3

-

15

ns
ns
ns

7

ns

7

NOTES:
1. A read is defined by W high and 'E low for the setup and hold times.
2. All read cycle timing is raferencad from K.
3. Transition is measured ±500 mV from steady-state voltage with load of Figure lB. This parameter Is sampled not 100% tested.
4. For Reed Cycle 1 timing, clock high pulse width «tKHQV-tKLQV).
5. For Read Cycle 2 timing, clock high pulse width .. (tKHQV - tKLQV).
6. K must be at a low level for outputs to transition.
7. This Is a synchronous davica. All synchronous inputs must maet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the davice is selected.

AC TEST LOADS
+5V

+5V

305

305

Q-..-----.

Q -......- - - -..

130 pF
(INCLUDING
SCOPE AND JIG)

130

5 pF
(INCLUDING
SCOPE AND JIG)

130

Figure 1A

Figure 18

MOTOROLA MEMORY DATA
5-27

II

MCM6292

READ CYCLE 1 (See Note 1)

tKIIKL ---+114--- tKLKH

A (ADDRESSI

II

w

DO-oa - - - - - PREVIOUS HIGH.Z

READ CYCLE 2 (See Note 2)

A (ADDRESSI

w
__ _ _ _

~~_-_-~.~~=-tK-L-W-----tK-L~-----~-~---~1~

uo-ua _ _ _ _ _ _ _ PREVIOUS HIGH Z

~

NOTES:
1. For Read Cycle 1 timing, clock high pulse width «tKHQV-tKLQVI.
2. For Read Cycle 2 timing, clock high pulse width :.:(tKHQV-tKLQVI.

MOTOROLA MEMORY DATA

5-28

On

}---

MCM6292

WRITE CYCLE

fJli Controlled, See Note 1)
Parameter

Symbol

MCMI2II2-2&

MCMI2II2-30

MCMI2II2-3&

Min

Max

Min

Max

Min

Max

-

30

-

36

-

ns

2

10

-

13

-

15

3

5

-

ns
ns

3

-

ns

4

Write Cycle TIme

tKHKH

25

Clock Low to Output High Z

tKLOZ

-

~

Setup Times for:

A
W

0

E

Hold TImes for:

A
W

0

tEVKH
tAVKH
twLKH
tDVKH

5

-

tKHEX
tKHAX
tKHWX
tKHDX

3

-

5

-

3

-

Unit

Notaa

4

NOTES:
1. A write is performed when Wand E are both low for the spacifl8d setup and hold times.
2. All write cycle timing is referenced from K.
3. K must be at a low /eval for outputs to transition.
4. This is a synchronous device. All synchronous inputs must meat the specified setup and hold times with stable logic /evals for ALL rising
edges of clock (K) while the device is selected.

IKHKL - -__+-;---IKLKH

W
IKLOZ
00-03

0,,-1

j

MOTOROLA MEMORY DATA
5-29

HIGH Z

•

MCM6292

APPLICATIONS INFORMATION

be set up on the system bus prior to the next risitig clock·edge.
On the rising edge of the clock (KI signal, the output data for
the previous cycle is latched until the next falling clock edge.
When the clock (KI signal is low, the output is. allOWed to
transition relative to the most recent rising cl9ck (K) edge.
Figure 2 shows a typical system configuration using four
MCM6292 chips. The system addresses are tied to the
MCM6292s in parallel, while system data is distributed among
the four input data ports of 4 bits each. Output data is tied to
a separate output data bus to exploit the sepsrsta I/O configuration of the MCM6292. The clock (K) signal is a logicel
derivation of the system clock.
Figure 3 sho~ typical bus timing for the configuration of
Figure 2. The system bus supplies address, data, and control
signals, while accepting data from the memory on rising clock
edges. In some applications, the clock (K) signal niay need to
be a delayed system clock to allow adequate address and data
setup times.

The· Motorola· family of synchronous SRAMs is designed to
provide a performance and parts count advantage in applications such as writeable control Stores, rnamory mapping,
and cache memory. The on-boBrd input registars eliminate the
need for external latch chipa in systems where addresses and
data are not on the bus long enough to satisfy standard SRAM
setup and hold times. Latches on the output port provide
extended hold times independent of address or other device
input changes to better meet system access requirements. The
clock (KI input controls the operation of the input registers
and output latches, and provides a direct means of synchronizing the SRAM to a system clock.
The MCM6292 offers transparent output operation, which
allows output date access within the same tKHKH cycle. This
feature lends itself well to applications requiring RAM data to

II
SYSTEM
ADDRESSES

/14
.

/14

/14

)"14

.I~4

AD-AI3

AD-AI3

AO-A13

AO-AI3

'

"

SYSTEM
·CLDCK

4K

-K

*-+ E
*-w

r-

~

4

00-03·

*_1

.* '""-' w

r- 00-03

00-03
00-03

/~

MCM6292

DO-03

-

/ 4

00-03
DO-03

,,16

IN
OUTPUT

.I~

*_E
MCM6292

MCM6292

*-1

r- 00-03
SYSTEM
DATA

*_E

*- E
MCM6292

~K

4K

.•.16

4

/,~

/

" 4

DATA
BUS
*From read/write controller.

figure 2. Typical Configuration for a 16-Bit Bus

MOTOROLA MEMORY DATA

5-30

4

3:
(")
3:

SYSTEM·GEIERATED
SlBULS
SYSTEM

0

20

40

I

CLOCK~

I

60

I

80

I

100

120

160

I

200

I

240

I~--'L

ADDRESS

CONTROL

WRITE DATA

:!:

~:u

0

~

>
:!:

MCMI212 COITROL
AID OUTPUT SIIIIALS
K (CLOCK)

m

:!:
0

WRITE CYCLE

-4--

READ CYCLE

R

W

R

;vv>

~+,

:u
-<

0

!i
»

IV (WRITE ENABLE)

E(CHIP ENABLEJ

QO-Q3 (DATA OUT)

,'

,

I

Y )')


3:
m

WRITE CYCLE

3:
0

-1--

~--+----W--~+----

READ CYCLE

JJ

-<
0

,.~

W(WRITE ENABLEI

E(CHIP ENABLEI
)

00-03 (DATA OUTI

120

160

NOTES:
1. The system supplies address, data, and control information and accepts data from memory on the rising adge of the system clock.
2. The memory clock is delayed 10 ns (for this examplel to allow input information to propagate to the memory chips.

Figure 3, Pipeline System Timing

I

200

{o,,+5

m

MCM6293

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

J 11. T
&293

X

XX

Part Number - - - - - - - - - - - - '

XX

Shipping Method (R2=Tape & Reel, Blank=Rails)
Speed (20=20 ns, 25=25 ns, 30=30 ns)
Package (P=Plastic DIP, J=Plastic SOJ)

Full Part Numbers-MCM6293P20
MCM6293P25
MCM6293P30

MCM6293J2O
MCM6293J25
MCM6293J3O

II

MOTOROLA MEMORY DATA

MCM6293J2OR2
MCM6293J25R2
MCM6293J3OR2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6294

16K x 4 Bit Synchronous Static RAM
with Output Registers and Output Enable
The MCM6294 is a 65,536 bit synchronous static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's second-generation high-performance
silicon-gate CMOS (HCMOS 1111 technology. The device integrates input registers, high
speed SRAM, and high-drive capebility output registers onto a single monolithic circuit for
reduced parts count implementation of cache data. RAM arid writeable control store applications. Synchronous design allows precise cycle control with the use of an external clock
(K), while CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
The address (AO-A13), dal!! (DO-D3), and write (W) inputs are all clock (K) controlled,
positive-edge-triggered, noninverting registers.
The MCM6294 provides output register operation. At the rising edge of K, the RAM
data from the previous K high cycle is presented. This function is well suited to fully pipelined applications.
The output enable (G) provides asynchronous bus control for common I/O or bank
switch applications.
Write operations are internally self-timed and initiated by the rising edge of the K input.
This feature eliminates complex off-chip write pulse generation and provides increased
flexibility for incoming signals.
The MCM6294 is available in a 300-mil, 28-pin plastic DIP as well as a 400-mil, 28-pin
plastic SOJ peckage.
Single 5 V ± 10% Power Supply
Fast Cycle Times: 21)125/30 ns Max
• Fast Clock (K) Access Times: 10113/15 n8 Max
• Address, Data Input, and W Registers On-Chip
• Output Enable for Asynchronous Bus Control
• Output Registers for Fully Pipelined Applications
• High Output Drive Capability
• Internally Salf-Timed Write Pulse Generation
• Separate Data Input and Data Output Pins
• High Board Density SOJ Package Available
• Typical Applications: General-Purpose Buffer Storage, Writeable Control Store, Data
Cache, or Cache Tag
•
•

300 MIL PLASTIC
CASE710A

~KAGE
PLASTIC
CASE 810

PIN ASSIGNMENT
A5 [ 1 •

28

Vee

A6 [ 2

27

A4

A7 [ 3

26

A3

A8 [ 4

25

A2

A9 [ 5

24

Al

AID

6

23

AD

All

7

22

D3

A12

8

21

D2

A13

9

20

03

DO

10

01

11
13

P02
18 P01
17P 00
16 Piii

14

15P Vsso*·

ii 12

Vss

..

19

*For minimum cycla/low noise
applications, VSSQ should be
isolated from VSS.

BLOCK DIAGRAM

PIN NAMES

00
01
02
03

MOTOROLA MEMORY DATA
5-41

Ao-A 13. . . . . . . . . Address Inpuls
Vii. . . . . . . . . . . . . Writs Enable
G . . . . . . . . . . . . OUlput Enable
00-03 . . . . . . . . . . . Data Inpuls
OO-Q3 . • . . . . . . . . Oats Oulpuls
K . . . . . . . . . . . . . . Clock Input
Vec . . . . . . . +5 V Power Supply
VSS . • . • • . . . . . . . . . Ground
VSSQ . . . . . Oulput Buffer Ground

•

MCM6294

I.
I
W~
II----'---+----::R""ee"'d----t----::=-----.--t
TRUTH rABLE

Operation. .
Write

.

nftQ3
u.u-

High· Z

'--_ _,;.....;:--:::--'----:-=----.L---......:D..::o"'u...
t --_--'.
NOTE: The value W is a valid input for the satup and hold times relative to the K rising
edge.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS=VSSO=O VI
Rating
power Supply Voltage
Voltage R~ to VSSIVSSO for Any
Pin Except Vce'
Output Current (per 1/01

Symbol

Value

Unit

VCC

-0.6 to +7.0

V

Vi", Vout

-0.5toVCC+0.6

V

lout

±2O

mA

Po

1.0

W

Tbie.

-10 to +85

·C

Power Dissipetion (TA =25·Cl
Temperature Under Bias

II

Operating Temperature

TA

Oto +70

·C

Storage Temperature

T~

-56 to +125

·C

This device contains circuitry to protect the
inputs agalnet damage due to high static
voItagee or eIec:Irici fIe/da; 1Iowawr, it is adnormal preceirtiona b8 taken to
avoid application of any voltage higher than
maximum fated voItagee to this highimpedance circuit.

vised thet

This is a synchronous device. AU synchronous inputs ",ust RI88t the apecIIIed estup
and hold times with stable logic levels for
ALL rising edgee Of clock (Kl while the device is selected.

This device contains Circuitry thet will ensure the Qutput devices are In High Z at
power up. Care should be takan by the uear
to ensure thet all clocks are at VIL or VIH
.during power up to prevent spurious reed
cycles from. occurring.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ara
exceedad. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITiONS. Exposure to higher than recommended l(oItages for
extended periods of time could affect device relisbHlty.
.
.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 70·C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS=VSSO=O VI
Symbol

Min

Typ

Max

Unit

Sui>Pty Voltage {Ope"11ing Voltage Rangel

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.0

-

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Symbol

Min

Max

Unit

±1.0

pA

Parameter

*VIL {mini = -0.5 V dc; VIL (mini = -3.0 V sc {pulsa width ,,;;20 nBI

DC CHARACTERISTICS
Paramater

Output Low Voltage (lOL = 12.0 mAl

VOL

-

0.4

V

Output High Voltage (lOH = -10.0 mAl

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cln

4

6

pF

Cout

7

10

pF

Input. Leakage Current (All Inputs, Vin=O to VCCI

IlkaUl

Output Leakage Current «(;=VIH, Vout=O to VCC, Outputs must be high-Zl

Ilka{OI

AC Supply Current ,(;=VIL, lout=O mA, Cycle Time=tKHKH mini

ICCA

±1.0

pA

140

mA

CAPACITANCE If= 1.0 MHz dV =3.0 V, TA = 25·C, Periodically Sampled Rather Than 100% Testedl
Characteriatic .
Input Capecitanca
Output Capecitance

MOTOROLA MEMORY DATA

MCM6294

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to + 70D e, Unless Otherwise Noted)
Output Timing Measurement Reference Level . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . See Figure lA Unless Otheowise Noted

Input Timing Measurement Reference Level .. . . . . . . . . 1.5 V
Input Pulse Levels . • . . . . . . . . . . . . • . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns

READ CYCLE (See Note 1)

Parameter

Symbol

MCMII2lI4-2O

MCMII284-2Ii

MCM6284-30

Min

Max

Min

Max

Min

30

-

ns

2

ns

3

0

ns

4

-

-

5

-

ns

-

6
5

~

ns

20

-

25

-

-

10

-

10

-

Output Active from Clock High

tKHOX

0

0

-

Clock Low Pulse Width

tKLKH

5

tKHKL

5
5

Clock Access Time

Clock High Pulse Width
Setup Times for:

A

Hold Times for:

A

3

tGHOZ

-

10

IGLOX

0

-

tKHAX
tKHWX

W
~ High to Q High Z

G Low to Q Active
G Low to Q Valid

-

IGLQV

5

-

-

tAVKH
twHKH

W

-

6
5
3

0

-

10

Notes

13

tKHKH
'tKHQV

Read Cycle Time

Unit

Max

-

ns

5

3

-

ns

5

10

-

13

ns

-

0

-

ns

4,6
4,6

13

ns

10

-

NOTES:
1. A read is defined by W high for the setup and hold timas.
2. All read cycle timing is referenced from K or from G.
3. Valid date from K high will be tha date stored at the address of the last valid read cycle.
4. Transition is measurad ±500 mV from steady-state voltaga with load of Figure lB. This parameter is sampled not 100% tasted.
5. This is a synchronous device. All synchronous inputs must meat tha spacified satup and hold limes with stabla logic lavals for ALL rising
edges of clock (K) while the device is selected.
6. At any givan voltage and temperature, IGHOZ max is Jess than IGLOX min for a given device.

AC TEST LOADS.

+5V

+5V

305

305

o--~---------.

0 -........- - - - - - .

=r= 130 pF

lJD

5 pF
(INCLUDING
SCOPE AND JIG)

lJD

ONCLUDING
SCOPE AND JIG)

Figure 1A

Figura 18

MOTOROLA MEMORY DATA
5-43

II

MCM6294

READ CYCLE 1 (See Note 11

K (CLOCK)
IKHKH

G(OUTPUT ENABLE)

A (ADDRESS)

W!WRITE ENABLE)

•

o (DATA OUT)

0,,-3

-1

0,,-2

READ CYCLE 2 (See Note 11
---'I+--IKLKH
K (CLOCK)
f+----IKHKH------l~

G (OUTPUT ENABLE)

A (ADDRESS)

W!WRITE ENABLE)

o (DATA OUT)

'KH~l-----O"---I---0,,-3

0,,-2

NOTE:
1. The outputs Qn-3 and 00-2 are derived from two previous read cycles, where W=VIH for Ihose cycles.

MOTOROLA MEMORY DATA

MCM6294

WRITE CYCLE

(W Controlled

See Note 11
Symbol

Parametar
Write Cycle TIme
Clock High to Output High Z

tKHKH


s::

MCIII2!14 COITROL
AID OUTPUT SIGIALS
K IClOCKI

m

WRITE CYCLE

s::

0

--t-

R

RfAD CYCLE

R

W

::D

-<

!'-

W!WRITE ENABLEI

~

Ii IOUTPUT ENABLE)

00-03 IOATA OUTI
120

160

NOTES:
I. The system supplies address, data, and control infonnation and accepts data from memory on the rising edga of the system clock.
2. The memory clock is dalayed 10 ns (for this axample) to anow input information to propageta to the memory chips.

Figure 3. Pipeline System Timing

I

200

I

MCM6294

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

T1T1
6294

X

XX

Part Number'-----------'-

,
Full Part Numbers-MCM6294P2O
MCM6294P25
MCM6294P30

XX

" __ IR2~T_''''''''''R''''
Speed (20=20 ns, 25=25 ns, 30=30 nsl
Package (P= Plaatic DIP, J = Plastic SOJI

MCM6294J2O
MCM6294J25
MCM6294J30

II

MOTOROLA MEMORY DATA

MCM6294J2OR2
MCM6294J25R2
MCM6294J30R2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6295

16K x 4 Bit Synchronous Static RAM
with Transparent Outputs and Output Enable
The MCM6295 is a 65,536 bit synchronous static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's second-generation high-performance
silicon-gata CMOS (HCMOS III) technology. The device integrates input registers, high
speed SRAM, and high-drive capability output latching onto a single monolithic circuit for
reduced parts count implementation of cache data RAM and writeable control store applications. Synchronous design allows precise cycle control with the use of an external clock
(K), while CMOS circuitry reduces the overall power consumption of the intagrated functions for greater reliability.
The address (AO-A 13), data (00-03), and write (W) inputs are all clock (K) controlled,
positive-edge-triggered, noninverting registers.
The MCM6295 provides transparent output operation when K is low for access of RAM
data within the same cycle (output data is latched when K is high).
The output enable (G) provides asynchronous bus control for common 110 or bank
switch applications.
Write operations are internally self-timed and initiatad by the rising edge of the K input.
This feature eliminates complex off-chip write pulse generation and provides increased
flexibility for incoming signals.
The MCM6295 is available in a 300-mil, 28-pin plastic DIP as well as a 400-mil, 28-pin
plastic SOJ package.
•
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Access and Cycle Times: 25/30/35 ns Max
Address, Data Input, and W Registers On-Chip
Transparent Output Latch for Access Within the Same Cycle
Output Enable for Asynchronous Bus Control
High Output Drive Capability
Internally Self-Timed Write Pulse Generation
Separate Data Input and Data Output Pins
High Board Density SOJ Package Available
Typical Applications: General-Purpose Buffer Storage, Writeable Control Store, Data
Cache, or Cache Tag

~

300 MIL PLASTIC
CASE710A

~KAGE
PLASTIC
CASES10

PIN ASSIGNMENT
A5

I.

28

Vee

AS

2

27

A4

A7

3

26 ~ A3

A8

4

25

A2

A9

5

24

AI

AIO

6

23

AO

All

7

22 ~ 03

AI2

8

21

~ 02

AI3

9

20

03

DO

10

19

02

01

11

18

01

12

17

DO

13

16

14

15

W
Vsso*

G
Vss

BLOCK DIAGRAM

..
* For mInImUm

eyclellow noise
applications, VSSQ should be
isolated from VSS·

Vee
VSS

MSSO

PIN NAMES
00

01

02

03

MOTOROLA MEMORY DATA

AD-A 1.3. . . . • . • . • Address Inputs
Vii. . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . Output Enable
00-03 •••.•.•.••• Data Inputs
OO-Q3 . . . . . . . . . • . Oata Outputs
K • . . . . . . . . . . • . • Clock Input
VCC . . . . • • . +5 V Power Supply
VSS . . . . • • . . • . • . . . Ground
VSSQ . . . . . Output Buffer Ground

..

MCM6295

TRUTH TABLE

I

w

Operation

QO-Q3

L

Write

High Z

H

Reed

Dout

NOTE: The value W is a valid input for the setup and hold times relative to the K rising
edge.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss=Vssa=OV)
Rating

Symbol

Power Supply Voltage
Voltage Relative to VsslVssa for Any
Pin Except Vce
Output Current (per 110)

Unit

VCC

-0.5 to +7.0

V

Yin. Vout

-0.5 to VCC+0.5

V

lout

±2O

mA
W

Power Dissipetion (TA = 25·C)

II

Velue

Po

1.0

Temperature Under Bias

Tbias

-10 to +85

Operating Tempereture

TA

Storage Temperature

Tsto

oto

~C

This device contains Circuitry to protect the
Inpl$ againat dernBi!8 due to .high static
voItagea or alecitric foelds; however. it is advisad that normal precautions be taken to
avoid application of any voltage higher than
maximum ratad voltagea to this hlghimpedance circuit.
This is a synchronous device. All synchronous Inputa must meet tlta specified setup
and hold timas with stable logic levels for
ALL rising edges of clock (K) while tlta device is sslacted.
This device contains circuitry that will ensure the output devices are ,In High Z st
power up. Care should be taken by the ussr
to ensure that all clocks are st VIL or VIH
during power up to prevent spurious reed
cyclea from occurring.

·C

+70

·C

-55 to +125

NOTE: Pennanant device damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higltar than recommanded voltagea for
extended periods of tima could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%. TA=O to 70 o e. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss = Vssa = 0 V)
Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

,4.5

5.0,

5.5

V

Input High Voltage

VIH

2.0

-

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Symbol

Min

Max

Unit

±1.0
±1.0

p.A
p.A

140

mA

Symbol

Parameter

*VIL (min) = -0.5 V dc; VIL (min)= -3.0 V ac (pulse width ",20 no)

DC CHARACTERISTICS
Paramater
Input Leekage Current (All Inputs. Yin =0 to VCC)

Ilka(l)

Output Leekage Current (S=VIH. Vout=O to VCC. Outputs must be in high-Z)

Ilka(O) ,

-

AC Supply Current (G=VIL. 10ut=0 mAl

ICCA

Output Low Voltage UOL = 12.0 mAl

VOL

-

Output High Voltage UOH = -10.0 mAl

VOH

0.4

V

2.4

-

V

Symbol

Typ

Mex

Unit

Cin

4

6

pF

Cout

7

10

pF

CAPACITANCE (f = 1 0 MHz dV = 3 0 V TA = 25°C Periodically Sampled Rather Than 100% Tesied)
Characteristic
Input Capacitance
Output Capacitan"'!

MOTOROLA MEMORY DATA
5-50

MCM6296

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0V ±10%, TA=Oto +70o C, Unless Otherwise Notedl
Input Timing Measurement Reference Level . . . . . . . . .. 1.5 V
Input Pulse levels . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . • . . . . . . . . . . . . . . . . . . . . . 5 ns

Output Timing Measurement Reference level . . . . . . . . . 1.5 V
Output load. . . . . . . . . . See Figure 1A Unless Otherwise Noted

READ CYCLE (Sea Note 1)
Parameter

Symbol

MCM82!I&-2&

MCM82lI&-3O

MCM82I6-3&

Min

Max

Min

Max

Min

-

30

-

35

Max

Unit

No_

Read Cycle Time

tKHKH

ns

2

tKHOV

-

25

-

30

-

-

Clock Access Time

35

ns

4,6

10

-

13

-

15

ns

5,6

0

-

0

-

ns

3,6

25

Date Valid frOm Clock low

tKlOV

-

Output Hold from Clock low

tKlOX

0

Clock low Pulse Width

tKlKH

5

-

Clock High Pulse Width

tKHKl

5

-

tAVKH
twHKH

5

tKHAX
tKHWX

3

-

tGHOZ

-

tGlOX

0

Setup Times for:

A

W
Hold Times for:

A

W
G High to 0 High Z
G low to 0 Active
G low to 0 Valid

-

IGlOV

5

-

5

-

ns

5

-

5

-

ns

5

-

5

-

ns

7

3

-

3

-

ns

7

10

-

13

-

15

ns

-

0

-

0

-

ns

8
8

15

ns

10

-

13

-

NOTES:
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K or from G.
3. Transition is measured ± 500 mV from steady-stete voltege with load of Figure 1B. This parameter is sampled not 100% _ d .
4. For Read Cycle 1 timing, clock high pulse width «tKHOV-tKlOV).
6. For Read Cycle 2 timing, clock high pulse width '" (tKHOV - tKlOV).
6. K must be at a low level for outputs to transition.
7. This is a synchronous device. All synchronous inputs must meet the specified setup and hold tlmea with steble logic levels for ALL rising
edges of clock (K) while the device is saIectad.
8. At any given voltage and temparature, IGHOZ max is less than IGlOX min, both for a given device and from device to device.

AC TEST LOADS

+5V

+5V

305

305

Q--+------+

Q--~---------,

130

130 pF
PNCLUDING
SCOPE AND JIG)

5 pF
IINCWDIN6
SCOPE AND JIG)

130

Figure 1A

Figure 18

MOTOROLA MEMORY DATA
5-51

II

MCM6295

READ CYCLE 1 (See Note 1)

ii

A IADDRESSI

II

00-03 - - - PREVIOUS HIGH Z - - - - - (

READ CYCLE 2

(S~e

Note 2)

A IADDRESSI

iii
____________~.r.:-tK~--__
00-03 - - - - , . PREVIOUS HIGH Z

- - - - - - i \ , .____IIn
_____.J)I(

NOTES:
1. For Read Cycle 1 timing, clock high pulse width 

MCII6285 COITROL
AID OUTPUT SISNALS
K (CLOCK)

~

m
~

WRITE CYCLE

0

-t--

READ CYCLE

W

:II

-<
0

»~

W(WRITE ENABLE)
ii (OUTPUT ENABLE)
0.+5

00-03 (DATA OUll

'1
80

120

160

NOTES:
1. The system supplies address, data, and control information and accepts data from memory on the rising edge of the system clock.
2. The memory clock is delayed 10 ns (for this example) to allow input information to propagate to the memory chips.

Figure 3. Nonpipeline System Timing

I

240

liS
II

MCM6296

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

J 11 T
6296

X

XX

XX

Part Number - - - - - - - - - - - - '

Sh' _ _

'02=T_ ...... _ - •...,

Speed (25=25 ns, 30=30 ns, 35=35 ns)
Package (P = Plastic DIP, J = Plastic SOJ)

Full Part Numbers- MCM6295P25
MCM6295P30
MCM6295P35

MCM6295J25
MCM6295J3O
MCM6295J35

II

MOTOROLA MEMORY DATA
5-56

MCM6295J25R2
MCM6295J3OR2
MCM6295J35R2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62350

4K X 4 Bit Cache Address Tag
Comparator
with System Status Bit Functions

.,."..
~nl'~ ~.~ACKAGE
11

The MCM62350 is a 16,384 bit cache address tag comparator organized as 4096 tags
of 4 bits, fabricatad using Motorola's high-performanca silicon-gata CMOS technology.
The devica integrates a 4K x 4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit appllca,tions. These functions allow easy
interface to the MC68020 and MC68030 microproceSllcirs, or any other environment
where efficient implementation of external cache memory is required. The MCM62350 is
available in 24 lead plastic DIP and SOJ packages.
The devica has a reset IR) pin for flash clear of the RAM within two minimum cycles.
This function is useful for system initialization. Individual bits within a tag field can be
set or cleared via the BSET and BCLR control input pins for valid bit updates.
The MCM62350 has two configurable comparator modes. The comparator can be configured as standard XNOR lexclusive NOR) for address tag comparison, or AOI lANDOR-Invert) for detarmining whether specific bits in the 4-bit word are set Ifor system
status bit applications). In addition, the match output can be programmed as true high
or true low for potential logic delay savings. The configuration of these modes is accomplished by performing a writs cycle with the R pin held low.
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Address to Match Time;
22/25/30 ns max
Fast Data to Match Time;
10112/15 ns max
Fast Read of Tag RAM Contenta; 25/30/35 ns max
Flash Clear of the Tag RAM;
70170/70 ns max
Programmable Active Output Level of Mstch
Bit Manipulation of Tags via BSET and BCLR Writes
Configureble Comparator Modes: XNOR Mode for Address Tag Comparison
AOI Mode for Systam Valid Bit Comparison

r--=--.

BLOCK DIAGRAM

MEMORY
MATRIX
128 ROWS
I - - - - - - - -....- - . j x 128 COLUMNS

AO-A6---''I-+I

i i - -.......~

J PACKAGE
3OOMILSOJ
CASE810A

PIN ASSIGNMENT
A4

1.

A5

2

24 VCC
23 A3

A6

3

22

A2

A7

4

21

Al

A8

5

20

AD

A9

6

19 ii

AID

7

All

8

18 VSS
17 003

S 9
i 10
BCiii 11

16

002

15

001

14

000

BSET

13

MATCH

12

PIN NAMES

MATCH
000-003---+---'*--........

w--....--;~

LJ!!I~J-.....~-I

S
BSET----+j

BCLR
A7-All---k---;~

MOTOROLA MEMORY DATA
5-57

300 MIL PLASTIC
CASE 724

AO-A 11. . • • . • • . • • • Address Inputs
W. . . . . . . . . . . . . . . Write Enable
S' . . . . . . . . . . . . . . . . Chip Select
BCLR. . • • • . • . Bit Clear Control Input
iiSEf ......... Bit Set Control Input
R . . . . . . . . Reset IFiash Clear) Input
MATCH .•••••.• Match (Hit) Output
000-003 . • . . • . • Data Input/Output
VCC . . . . . . . . . +5 V Power Supply
VSS .••.••••.•••.••. Ground

II

MCM62350

SIGNAL DESCRIPTIONS
AO-A11-ADDRESS INPUTS
The address lines, are used for indexing into the tag RAM
portion of the chip.
'
DQO-Dcl3.,- DATA INPUTfOUTPUT
The data lines are used as input for compare" write, and,
configuration cycles, and as output for read cycles.

BSET-BIT SET CONTROL INPUT
This contml signal is used for DRing data into the tag RAM
during BSET write cycles. Independent bits within the tag can
be set using the appropriate mask, as indicated in the bit Set
truth table. The BSET input can also be used to initiate a read
cycle.

BCLR-BIT

II

CL~R

as indicated in the bit clear truth table. The BCLR input can
also be used to initiate a read cycle (note'that at least one of
the BSET fBCLR signals must be asserted to trigger a read
cycle).
'

R-RESET (FLASH CLEAR) INPUT
The reset control signal is used to initiate a clear cycle or a
configuration c~cle.
'

, S-CHIP,SELECT
This control signal is used to Chip select the device.

W-WRITE ENABLE
The write enable signal is used to initiate write cycles.

MATCH-MATCH (HIT) OUTPUT

CONmOL INPUT

This control ,signal is used for ANDing the complement of
data into the tag RAM during BCLR write cycles. Independent
bits within the tag can be cleared using the appropriate mask,

This output signal is used to indicate a match of OOO-OQ3
inputs with the contents of the tag RAM addresSed by AD-

All.

FUNCTIONAL TRUTH TABLE
S

W

B,CLR

BSET

R

DQO-DQ3

Match

Cycle

L
L
L
L
L
L
X
L
H

H
H
H
L
L
L
H
L
X

Ii

H
X
L
H
H
L
X
X
X

H
H
H
H
H
H
L
L
H

Compare Din
Read Dout
Read Dout
Write Din
Bit Clear Mask
Bit Set Mask
High-Z
Config Din*
High-Z

Valid
Assert
Assert
Assert
Assert
Assert
Ass8rt
Assert
Assert

Compare
Read
Read
Writs
BCLR Write
iimWrite
Clear (Reset)
Configuration
Deselect

L
X
H
L
H
X
X
X

*002 'and 003 are don't cares during a configuration cycle.

COMPARATOR BEHAVIORAL TABLE
Type

DQO

XNOR
XNOR
AOI
AOI'
AOI

00

00
00

DO'
Q1
01
Ql
Ql
Ql

L
H

DQ2

DQ3

RAMQO

RAMO'

RAMQ2

RAMQ3

02
02
02
02
02

03
03
03
03
03

Q()

01

Q()
Q()

Q1
Q1

X
L

Ql
Ql

02
02
02
02
02

03
03
03
03
03

BIT CLEAR TRUTH TABLE (See Notel

1

L=Low
H=High
0= False
1 = True
, X = Don't Care

0
1
1

0

BIT SET TRUTH TABLE (See Note)

Data
In

Initial
,Stored Data

Final
Storad Data

0
0

0

0

1

1

Bit
Unchanged

1
1

0

0
0

to "Zero"

1

Match

Bit Cleared

NOTE: These tables reflect the behavior of single bit positions.
The four bits in the tag can all be set or cleared in tandem,
or bits within the tag can be independently set or cleared
with the appropriate mask.

DO'

Comparator
Type

Match
True Level

L
L
H
H

L
H
L
H

XNOR
XNOR
AOI
AOI

Low
High
Low
High

Initial
Storad Data

Final
Stored Data

0
0
1
1

0
1

0
1

Bit
Unchanged

0
1

1
1

to "One"

Bit Set

AOI COMPARATOR LOGIC DIAGRAM

CONFIGURATION TABLE
DQO

Data
In

MEMORY
ARRAY

,.....•._,. "'-

MOTOROLA MEMORY DATA
5-58

MCM62350

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSs-o
- V)
Symbol

Reting
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Match OutpUt
Output Current
110 Pins, Per 110

Value

Unit

VCC

-0.5 to +7.0

V

VinlVout

-0.5 to VCC+0.5

V

lout

40
20

rnA

Po

1.0
Oto+70

W
DC

Storage Temperature

TA
Tstg

-55 to + 125

DC

Temperature Under Biaa

Tbias

-10to +85

DC

Power Dissipation ITA = 25°C)
Operating Temperature

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fielde; oo-ver, it is advieed that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
Tha power supply (VCC) should be stable
for at least 100 pS before operating the device. During this interval, tha pert will intarnally configure itsaIffor XNOR compares,
willi the match output active high. In addition, the mamory array of RAM bits will
be claared.

NOTE: Permanent device demage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher ~han recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA =0 to 7Oo e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Rafarencad to VSS -0
- V)
Symbol

Parameter

Min

Typ

Mex

Unit

Supply Voltage (Operating Vol!8ge Range)

VCC

4.5

6.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

Vil

-0.6*

-

O.B

V

Symbol

Min

Max

Unit

*Vll min = -0.5 V dc; Vil min = -3.0 Vac (pulee width :0;;20 na)
DC CHARACTERISTICS
Charactarlatlc

AC Supply Currant (S=Vll, lout=O rnA, tAVAV=tAvaV max)

ICCA

Output Low Voltage (1/0 Pins: 10l =B.O rnA, Mstch Output: 10l = 12.0 rnA)

VOL

-

Output High Voltage (1/0 Pina: 10H= -4.0 rnA, Match Output: 10H= -10.0 mAl

VOH

2.4

Input Laakege Current (All Inputs Vin=O to VCC)

Ilkam

Output Laakalllt Current, Except Match Output (S=VIH, Vout=O to VCC)

l(kalOI

±1.0

pA

±1.0

pili
rnA

140*
0.4

V

-

V

*ICC active current for the claar cycle exceada this specification. Howewr, thle is a transient phanomenon and will not affect the power
dissipation of the device. Good decoupling of the local power supply should always be used.

-

CAPACITANCE (f-l
- 0 MHz dV-3.0 V TA =25°C Periodically Samplad Rather Than 100% Tasted)
Characterlatlc

Symbol

Typ

Max

Unit

Cin

4

6

pF

Caut

5

7

pF

Crnstch

6

7

pF

Input Capecitance
110 Capacitance
Match Output Capacitance

AC TEST LOADS

+5V

+5Y

+5V

481

481

305

30 pF

255

ONCUlDING
SCOPE AND JIG)

Figure 1.

MATCH,-+----..

Q-..----~

Q -....- - - -. .

5pf
(lNCWDING
SCOPE AND JIG)

255

Figure 1b

MOTOROLA MEMORY DATA

50 pf

130

(lNCLIIOING
SCOPE AND JIG)

FIgure 10

II

MCM62350

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA=O to +70o e, Unless Otherwise Noted)

OutpUt Timing Measurement Reference level . . . . . . . . . 1.5 V
OutpUt load (I/O Pins) . . . . . . . . . . . . . . . . . See Rgure la
OutpUt Load (Match Output) . . . . . . . . . . . . . . See Figure lc

Input Timing Measurement Reference' Level . . . . . . . . . . ,1.5 V
Input Pulse levels . . . . . . . . . . . . . . • . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . • • . . . . . . . . . . . . . . . 5 ns

READ CYCLE (See Note 1)
Symbol

Characteristic

II

Standard

MCM623IiO-22 MCM62350-25 MCMII235IJ..3O
Max

Min

Max

Min

Max

-

30

-

35

25

30

35

ns

12

-

..,.

-

ns

15

-

15

ns

35

ns

2

35

ns

2

tAVAV

tRC

25

Address Access Time

tAvaV

tAA

-

Select Access Time

tSlaV

tACS

BCLR Access Time

tBclaV

tABC

-

25

-

30

BSE'f Access Time

tBslaV

tABS

-

25

-

30

-

Output Hold from Address Change

tAXax

toH

5

5

-

5

tSlax

tCSl

5

tBSlax/tBClax

tLZ

10

tSHaz

tcsz

-

9

tBSHaz/tBCHaz

tHZ

-

tBSlMX/tBClMX

tCH

0

S High to Output High-Z

BSE'fI BClR High to Output High-Z
BSE'f/BClR Low to Match Assert

-

-

BSET/BCLR Low to Output Active

Not..

Min

Read Cycle Time

Select low to Output Active

Unit

Alternate

5

-

5

10

-

10

10

9

-

10

-

15

0

18

0

-

ns
ns

3

ns

3

12'

ns

3

12

ns

3

20'

ns

NOTES:
1. ii = V'H, W= V,H continuouslv during read cycles. One of either BSE'f or BClR pins must be asserted low to activate the outputs. The
match output becomes asserted when either the BSE'f or BClR pin transitions low.
2. For brevity in signal names, BC is used to represent BClR transitions, while BS is used to represent BSE'f transitions.
3. Transition is measured ± 500 mV from steady state voltage with load of F"lgure lb. This parameter is sampled and not 100% tested.

READ CYCLE

is CONTROLLED)

IADDRESS CONTROLLED)
j+----'AVAV

-----*I

A (ADDRESS)
'AVQV-----lI~

'AXQ)(

5 ,CHIP SELECT)

BSET IBIT SET)
'BSLMX

iiW! (BIT CLEAR)

'BCLQ)(~k:=I;jI-t----t-'BCLMX
Q (DATA OUT)---HIGH·Z

MATCH

----.,r-c

MATCH VALID

MOTOROLA MEMORY DATA
5-60

MCM62350

COMPARE CYCLE (See Note 1)
Symbol
Characteristic

Standard

MCMfI235O..22 MCMfI235O..25 MCMfI235O..3O
Alternate

Min

Max

Min

Max

Min

Unit

Notes

Max

Compare Cycle Time

tAVAV

tc

25

-

30

-

36

-

ns

Address Valid to Match Valid

tAVMV

tACA

22

25

-

30

ns

BCLR High to Match Valid

tBCHMV

tBCCA

18

-

20

ns

2

BSEf High to Match Valid

tBSHMV

tBSCA

20

ns

2

Data Valid to Match Valid

tOVMV

tOCA

-

15

ns

20

ns

5

3

-

3

-

no
no

S Low to Match Valid

tSLMV

tCSCA

-

Match Hold from Address Change

tAXMX

tACH

5

Match Hold from Data Change

tOXMX

tOCH

3

-

0

10

0

12

0

15

ns

-

9

-

10

-

12

,ns

3

12

no

3

S High to Match Assert

tSHMX

tCH

BCLR High to Output High-Z

tBCHQZ

tBCZ

BSET High to Output High-Z

tBSHQZ

tBSZ

15
15
10
15

9

12

-

18

-

18

10

5

NOTES:

1. R= VIH, Vii = VIH continuously during compare cycles.
2. For brevity in signal names, BC is used to represent iiCLR transitions, while BS is used to represent BSET transitions.
3. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% tested.

COMPARE CYCLE
(ADDRESS CONTROLLED)

IS CONTROLLED)

1 + - - - - IAVAV----~

J<_ _ _>C

A IADDRESS)
~---IAVMV----l~

S ICHIP SELECT)

IS=VILI
ISHMX-+_._---IOi

liSE'i' IBIT SET)

BCLR (BIT CLEAR)

o IDATA IN) - - - - - - - - {

14--*- tovMV
o IDATA OUT)

----HIGH·Z----+----+-

MATCH

VALID

MOTOROLA MEMORY DATA

5-61

II

MCM62350

STANDARD WRITE CYCLE (See Note 1)

Symbol

Characteristic

Unit

Altamate

Min

Max

Min

Max

Min

Max

Write Cycle Time

tAVAV

twc

25

-

30

twP
twP

18

-

20

-

ns

twLWH/tSLSH
twLSH/tSLWH

-

36

Write Pulse Width

ns

25

twHox/tSHOX

tOH

0

0

-

0

-

Write Low to Output High-Z

twLOZ

twz

-

9

-

10

-

12

ns

Address Hold from Write End

twHAX/tSHAX

twR

0

-

0

-

0

-

ns

tAVWL/tAVSL

tAS

0

Address Valid to End of Write

tAVWH/tAVSH

tAW

18

Oats Valid to End Clf Wrij.

tOVWH/tOVSH

tow

10

Oats Hold from Write End

Mat~h

Assert

0
20

12

0
25
14

Notes

ns

-

Address Setup to Beginning of Write

Write Low to

II

MCM623IiO-22 MCM623&O-2& MCM82350-30

Standard

ns

ns
ns

2,3

twLMX

twCH

0

15

0

15

0

18

ns

BSET/BCLR Setup to Beginning of
Write

tBSHWL/tBSHSL
tBCHWL/tBCHSL

tBSS
tBCS

-1

-

-1

-

-1

-

ns

3

BSET/BCLR Hold Time from Wrije Stsrt

twLBsx/tSLBSX
twLBCX/tSLBCX

tBSH
tBCH

10

-

10

-

10

-

ns

Write High to Match Valid

twHMV

twCA

-

22

-

25

-

30

ns.

3

Write High to Output Active

twHOX

tow

5

-

5

-

5

-

ns

2,3

NOTES:
1. A standard write occurs during the overlap of Wand S low and BSET and BCLR high. The R pin is high continuously during a write cycle.
2. Transition is measured ±500 mV from steady state voltage wnh load of Figura lb. This paramater is sempled and not 100% tested.
3. Both the match output and QO-Q3 ara shown as valid in the W controlled cycle below to convey their timing relative to W. In raality, only
one of either match or QO-Q3 can be valid at one time, as determined by BSETand iiC[R inputs.

STANDARD WRITE CYCLE

(i CONTROllED)

(8 CONTROllED)

\ + - - - - IAVAV ------I~
A (ADDRESS)

8 (CHIP SELECT)

t+---- IAVWH ----1*'1---+1\ + - - - - IWLSH -t--~rr.,.

i (WRITE ENABLE)

BSET (BIT SET(

BCLR (BIT CLEAR)

D (DATA IN)

-----+----{
IWLOZ-t+--I~

Q

--------HIGH-Z--------

(DATA DUn
IWLMX

(ASSERTED)

MATCH

MOTOROLA MEMORY DATA
5-62

MCM62350

BSET/BCLR WRITE CYCLE (See Note 1)
Symbol

Characteristic

Standard

MCM62350-22 MCM62350-25 MCM&2350-30

Unit

Alternate

Min

Max

Min

Max

Min

Max

-

30

-

35

-

ns

-

20

-

25

-

ns

Write Cycle Time

tAVAV

twc

25

Write Pulse Width

twLWH/tSLSH
twLSH/tSLWH

twp
twp

18

Address Setup to Beginning of Write

tAVWL/tAVSL

tAS

0

-

0

-

ns

tAVWH/tAVSH

tAW

18

-

20

-

0

Address Valid to End of Write

25

ns

Data Setup to Beginning of Write

tDVWL/tDVSL

tDS

-1

-

-1

-

-1

Data Hold from Write End

twHDX/tSHDX

tDH

0

-

0

0

Address Hold from Write End

twHAX/tSHAX

twR

0

-

0

-

0

-

twLMX

twCH

0

15

0

15

0

18

ns

BSET/BCLR Setup to Beginning of
Write

tBSLWL/tBSLSL
tBCLWL/tBCLSL

tBSS
tBCS

-1

-

-1

-

-1

-

°ns

BSET/BCLR Hold Time from Write Start

twLBsx/tSLBSX
twLBCX/tSLBCX

tBSH
teCH

10

-

10

-

10

-

ns

W Low to Match Assert

ns

Notes

2

ns
ns

2

Write High to Match Valid
22
25
30
ns
twHMV
twCA
NOTES:
1. A BSET/BCLR write occurs during the overlap of Vii and S low and BSET or BCLR lowo The II pin is high continuously during a write
cycle. BSET and BCLR write cycles can be Vii controlled or S controlled. Only two of four possible cycles are shown here for brevity.
2. Data output buffer must be in high-Z prior to start of either BSET or BCLR write cycles. Note that for Vii controlled cycles, the user must
avoid excessive setup time of BSET IBCLR to avoid bus contantion. Data must be set up for tOVWL/tDVSL time to ensure the data integrity
of non-modified bits during BSET/BCLR write cycles. In the event that invalid data is presented for non-modHied bits during the BSETI
BCLR write, note that it is not possible to recover the original data state by simply presenting valid data before the end of write.
BSET WRITE CYCLE

BCLR WRITE CYCLE

!W CONTROllED)

(S CONTROllED)

A (ADDRESS)

S (CHIP SELfCT)

W (WRITE ENABLE)

BSH (BIT SET)

iil:[jf (BIT CLfAR)

o (DATA IN)

n (DATA OUT)

----+--

-------HIGH·Z - - - - - - -

(ASSERTED)

MATCH

MOTOROLA MEMORY DATA
5-63

II

MCM62360

CLEAR CYCLE (See Nota 1)
Symbol

Characterlatlc

MCM~

Unit

Alternate

Min

Max

Min

Max

Min

Max

tRLAV
tRLSV
tRLBSV
tRLBCV
tRLDV

tCR
tCR
tCR
tCR
tCR

-

70

-

70

-

70

R Pulse Width

tRLRH

tCLP

25

'RS

5

Write Hold from R High

tRHWL

twH

0

tRLAX
tRLSX
tRLBSX
tRLBCX
tRLDX

tcx
tcx
tex
tex
tex

0

0

-

35

twHRL

-

30

Read Setup to R Low

0

-

Ii Low to Match Assert

tRLMX

tMH

0

15

0

18

0

20

ns

R Low to Output High-Z

tRLOZ

tel

-

15

-

18

-

20

ns

'ii Low to Inputs Recognized
(Clear Cycle TIme)

A

5
BSE'i'
BCiJi
D

R Low to Inputs Don't Care

A

'S"
lmT
BCiJi
D

II

MCM623IiO-22 MCM623&O-2Ii

Standard

5
0

5
0

Not..

ns

ns
ns

2

ns

2

ns

3

4

NOTES:
1. The address, lI'S"ET, and ~ Inputs are don't cares during a clear cycle.
2. The clear cycle is initiated at the falling edge of'ii. The twHRL and tRHWL perameters must be satisfied to prevent an undesired configuration
'cycle.
'
3. "Inputs" for this peremeter refers to all inputs exCflpt W.
4. Trensition is measured ±500 mV from steady state voltage with load of Figure lb.' This perameter is sampled and not 100% tested.

CLEAR CYCLE
(FROM COMPARE CYCLE)
A (ADDRESS)
'RLAX ......f--_~
~-----IRLAV------~

S (CHIP SELECT)

R(RESET)

W(WRITE ENABLE)

8m' (BIT SET)

BCLA (8IT CLEAR)
f4----IRLDV---~

D (DATA I N ) - - " " " ' I - - - (
~-.....+-'RLDX

_---::.:::'::.,
.. _-Jj'RLMX
MATCH
VALID

MATCH

f4--*IRLOZ
Q (DATA OUT)

J----HIGH·Z - - - -

-------HIGH·Z - - - - - - -

MOTOROLA MEMORY DATA
5-64

MCM62350

CONFIGURATION CYCLE (See Notes 1 and 21
Symbol
Characteristic
Configuration Control Pulse Width

S

if
Data Setup to End of Configuration
Cycle
Data Hold from End of Configuration
Cycle

S

if
iii
S

if
iii

MCM62350-22 MCM62350-2S MCM823&O-30

Unit

Notes

-

ns

3

14

-

ns

-

0

-

ns

ns

Standerd

Alternate

Min

Max

Min

Max

Min

Max

tSlSH
tRlRH

tsp
tsp

20

-

25

-

30

tOVSH
tOVRH
tOVWH

tos
tos
tos

10

-

12

-

tSHOX
tRHOX
twHOX

tOH
tOH
tOH

0

-

0

R High Pulse Width

IRHRl

tcp

5

-

5

-

5

-

Write Setup to R low

twlRl

tws

5

-

5

5

S Setup to End of Configuration

tSlWH
tSlRH

tsws
tscs

20

-

25

-

30

-

R Setup to End of Configuration

tRlWH

tSR

20

-

25

-

30

R Setup to S low

tRlSl

tcss

5

5

S Setup to Beginning of Write

tSHWl

twss

0

-

S High to Output High-Z

tSHOZ

tHZ

-

9

W low to Output High-Z

twlOZ

tHZ

-

9

-

0

-

-

ns
ns

4

ns

0

-

10

-

12

ns

5

10

-

12

ns

5

5

ns

3

ns

NOTES:
1. A configuration cycle is performed during the overfap of iii low, if low, and 5 low. Address, OQ2, DOl, BSET, and BClR inputs are don't
cares during configuration cycles.
2. To ensure proper configuration of the device during power up, chip eelect must be equal to or greater than VIH.
3. A valid configuration can be performed with 5 asserted prior to if and iii low transitions. Be aware, however, that array data may be altered
under this condition.
4. Note that terminating the cycle with if while leaving iii and 5 ....rted may cauee array data to be altered.
5. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% _ d .

CONFIGURATION CYCLE

(ARRAY UNPROTECTEDI

S' (CHIP SELECT)

ii (RESET)

IV (WRITE ENABLEI

D (DATA IN

--t--{

o (DATA OUTI

)----H(GH-Z---

MOTOROLA MEMORY DATA
5-65

II

MCM62350

ORDERING INFORMATION
(Order by Full Part Numberl

MCM

Motorola Memory Prefix

T

J 1T
&23Iio

X

XX

XX

T

Part Number _ _ _ _ _ _ _ _ _ _ _
....1

"_ _ II"-T.,. ___ -..,.
Speed (22=22 ns, 25=25 ns, 30=30 ns)
Package (P=Plastic DIP, J=PIaBtic SOJ)

Full Part Numbers- MCM62360P22
MCM6235OJ22
MCM6236OJ22R2

MCM62360P25
MCM6235OJ25
MCM6236OJ25R2

II

MOTOROLA MEMORY DATA

MCM62360P30
MCM6235oJ30
MCM6236OJ30R2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62350-20

Product Preview
4K X 4 Bit Cache Address Tag
Comparator

.,.""",

lIWim~ ~ ~ 111111: PACKAGE

with System Status Bit Functions
The MCM62350 is a 16,384 bit cache address tag comparator organized as 4096 tags
of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology.
The device integrates a 4K x 4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit applications. These functions allow easy
interface to the MC68020 and MC68030 microprocessors, or any other environment
where efficient implementation of external cache memory is required. The MCM62350 is
available in 24 lead plastic DIP and SOJ packages.
The device has a resat (ii) pin for flash clear of the RAM. This function is useful for
system initialization. Individual bits within a tag flBld can be set or cleared via the BSET
and BClR control input pins for valid bit updates.
The MCM62350 has two configurable comparator modes. The comparator can be configured as standard XNOR (exclusive NOR) for address tag comparison, or AOI (ANDOR-Invert) for determining whether specific bitS in the 4-bit word are set (for system
status bit applications). In addition, the match output can be programmed as true high
or true low for potential logic delay savings. The configuration of these modes is accom~
plished by performing a write cycle with the R pin held low.
The MCM62350 is available in a 24 lead plastic or sidebrazed DIP, as well as a 24 lead
plastic SOJ package.
'
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Address to Match TIme;
20 ns max
Fast Data to Match Time;
10 ns max
Fast Read of Tag RAM Contents; 20 ns max
Flash Clear of the Tag RAM;
70 ns mex
Programmeble Activa Output Level of Match
Bit Manipulation of Tags via BSET and BClR Writes
Configurable Comparator Modes:
XNOR Mode for Address Tag Comparison
AOI Mode for System Valid Bit Comparison

J PACKAGE
300 MIL SOJ
CAsEB10A

PIN ASSIGNMENT
A4

1.

24

A5

2

23

AS

3

22 A2

VCC
A3

A7

4

21

Al

AB

5

20

AD

A9

8

19 Ii

AID [ 7
All [ 8

S 9

W 10
BCD! 11

m

12

18 Vss
17 D03
18 002
15

001

~ 000
13 ~ MATCH
14

PIN NAMES

MEMORY
MATRIX
12B ROWS
I - - - - - - -....-~x 12B COLUMNS

AO-A6--'f-~

300 MIL PLASTIC
CASE 724

AD-All. . . . . . . • . • . Address Inputs
Write Enable
~ . • . . • . . • • . . • • . ... C~ip Satect

w. . . . . . . . . . . . . . .

m:I:R. . . . . . . . Bit Clear Control Input
Rrf. . . . . . . . .Bit Set Control Input
~ • . . • : . . • R8aet (Flash Clear) Input

MATCH

000-003--+--'7----+¥I

MATCH ....•.•• Match (Hitl Output
DQO-DQ3 .. '.•.•. Data Input/Output
VCC . . . . . '...• +5 V Power Supply
VSS . . . . . . . • . • . . • . . . Ground

W-::=:!::~"I

S

'-"="'-Jr-....,..-.

BSET'-----I~

BClR
A7-All--*,,"--i~

This document contains Infonnation on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-67

II

MCM62350-20

SIGNAL DESCRIPTIONS
AO-A11-ADDRE$S INPUTS
The address lines are used ·for indexing into the tag RAM
portion of the chip.

as indicated .in the bit clear truth teble. The BCLR input can
also be used to initiate a read cycle (note that at least one of
the BSET/BCLR signals must be asserted to trigger a read
cycle).

DQO..DQ3-DATA INPUT/OUTPUT
The data lines are used as input for compare, write, and
configuration cycles, and as output for read cycles.

R-RESET (FLASH CLEAR) INPUT

The resat control signal is used to initiate a clear cycla or a
configuretiF .cycle.

BSET -BIT SET CONTROL INPUT
This control signal is used for ORing data into the tag RAM
during BSEf write cycles. Independent bits within the tag can
be sat using the appropriata mask, as indicated in the bit sat
truth table. The BSET input can also be used to initiata a read
cycle.

II

i-CHIP'.ELECT
This control signal is used to chip select the device.
W-WRITE ENABLE
The write enable signal is used to initiate write cycles.

BCLR-BIT CLEAR CONTROL INPUT

MATCH-MATCH (HIT) OUTPUT

This control signal is used for AN Ding the complement of
data into the tag RAM during BCLR write cycles. Independent
bits within the tag can be cleared using the appropriate mask,

This output signal is used to indicate a match of DQO-DQ3
inputs with the contents of·the tag RAM addressed by AOAll.

FUNCTIONAL TRUTH TABLE

I

W

BCLR

iSET

R

DQll-DQ3

Match

Cycle

L
L
L
L
L
L
X
L
H

H
H
H
L
L
L
H
L
X

H
L
X
H
L
H
X
X
X

H
X
L
H
H
L
X
X
X

H
H
H
H
H
H
L
L
H

Compare Din
Read Dout
Read Dout
Write Din
Bit Clear Mask
Bit Sat Mask
High-Z
Conflg Din*
Hlgh·Z

Valid
Aaaert
Aaaert
Aaaert
Aaaert
Aaaert
Aaaert
Aaaert
Aaaart

Compare
Read
Read
Write
UCLRWrite
li§Ef Write
Claar (Resetl
Configuration
Daaelect

* 002 and OQ3 are don't cares during a configuration cycle.
COMPARATOR BEHAVIORAL TABLE

Type

DQO

DQl

DQ2

DQ3

RAMQO

RAMQl

RAMQ2

RAMQ3

Match

XNOR
XNOR
AOI
AOI
AOI

00

01
01
01
01
01

OZ
02
02
02
02

Q3
Q3
Q3
Q3
Q3

00

01

02
02
02
02
OZ

Q3
Q3
Q3
Q3
Q3

1
0
1
1
0

ill!
QO

L
H

QO

Q1

QO

01

X
L

01

Q1

BIT CLEAR TRUTH TABLE (Sea Note)
Date
In

Initial
Stored Date

Final
Stored Data

0
0

0

0

1

1

1
1

O·

0
0

1

BIT SET TRUTH TABLE (Sea Notel
Data
In

Initial
Stored Data

Final
Stored Data

Bit
Unchanged

0
0

0

0

1

1

Bit Claared
to "Zero"

1

1

0
1

1

NOTE: These tables reflect the behavior of single bit positions.
The four bits in the tag can a" be aet or claired In tandem,
or bits within the tag can be indepandently aet or cleared
with the appropriate mask.

DQO

DQl

Comparator
Type

Match
True Leval

L
L

L
H
L
H

XNOR
XNOR
AOI
AOI

Low
High
Low
High

1

Bit
Unchanged
Bit Sa!
10 "One"

AOI COMPARATOR LOGIC DIAGRAM

CONFIGURATION TABLE

H
H

L=Low
H=Hlgh
0= Falsa
1 = True
X = Don't Care

MEMORY
ARRAY

MOTOROLA MEMORY DATA
5-68

MCM62350-20

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss = 0 V)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Match Output

Output Current

Symbol

Valua

Unit

VCC

-0.5 to +7.0

V

VinIVout

-0.5 to VCC+0.5

V

40

mA

lout

20

110 Pins, Per 110
Power Dissipation (TA=25·C)

Po

1.0

W

TA

Storage Tempsreture

Tata

Oto +10
-55 to +125

·C

TempBreture Under Bias

Tbias

-10to +85

·C

Opsreting Tempsreture

·C

The power supply (VCC) should be stable
for at least 100 pIJ before opsreting the device. During this interval, the psrt will internally configure ItseJf for XNOR compares.
In addition, the memory array of RAM bita
will be cleared.
This device contains circuitry to protect the
inputs against damaga due to high static
voltages or eJsctric fields; however, it is advised that normal pracauliOll8 be taken to
avoid application of any voltage higher than
maximum ratsd voltages to this high impedance circuit.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functionel opsrelion should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higherthan recommended voltages for extended
psriods of lime could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA=O to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSs=O V)
Symbol

Min

Typ

Mill<

Unit

Supply Voltage (Opsrating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

V

VIL

-0.6*

-

VCC+0.3

Input Low Voltage

0.8

V

Symbol

Min

Mill<

Unit

±1.0

p.A

"'nsmeter

*VIL min = -0.6 V dc; VIL min= -3.0 V ac (pulse width :520 ns)

DC CHARACTERISTICS
Cha_rJetic
Input Leakage Current (AJllnpulB Vin=O to VCC)

IlkulJ)

Output Leakege Current, Except Match Output (5=VIH, Vout=O to VCC)

Ilku(O)

AC Supply Current fS=vll.. lout=O rnA, tAVAV=tAVQV max)
Output Low Voltage
Output High Voltage

ICCA

11/0 Pins: 10L =8.0 mA, Match Output: 10L = 12.0 mAl
11/0 Pins: 10H = -4.0 rnA, Match Output: 10H = -10.0 mAl

-

VOL

-

VOH

2.4

±1.0

p.A

140*

mA

0.4

V

-

V

*ICC active current for the clear cycle exceeds this spscificalion. However, this is a transient phenomenon and will not affect the power
dissipation of the device. Good decoupling of the local power supply should always be used.

CAPACITANCE (1= 1 0 MHz dV =3 0 V T A =25·C Periodically Sampled Rather Than 100% Tested)
ChanscterJatic
Input Capacitance

110 Capacitance
Match Output Capacitance

Symbol

Typ

Mill<

Unit

Cin

4

5

pF

Cout

5

7

pF

Cmatch

6

7

pF

AC TEST LOADS

+5V

+5V

+5V

481

481

305
MATCH ....- - - -......

Q -......- - - - .

255

==30 pF

(INCLUDING
SCOPE AND JIG!

Figure Ie

5 pF
(INCLUDING
SCOPE AND JIGI

255

Figure lb

MOTOROLA MEMORY DATA
5-69

50 pF
(INCLUDING
SCOPE AND JIGI

130

Figure Ie

II

MCM62350-20

AC OPERATING CONDITIONS AND CIiARACTI;RISTICS
. (Vee=; 5V ±10%, TA=Oto +70oe, Unless Otherwlse Noted)

Input TlI11ihg Measurement Reference Level • . • • • • • . • • 1.5 V
Input Pulse Levels • . • • • • • • • • • • • • • • • • • • • • .0 to 3.0 V
Input Rise/Fall Time: . • . . • . . • • • • • • • • • • • • • • • • • ' 5 ns

Clutput Timing Measurement Reference Level .'. • • • • • • • 1.5 V
Output Load 11/0 Pins) • • • • • . • • . • • • • • • • • See Fogilre la
Output Load (Match Output) • '• • . • • . • • . . • :. See Filiure lc

READ CYCLE (See N~ 1)

II

MCM823IiO-a

.Symbol

Characteristic

. Standard

Altarnate'

Min

No_

-

ns'
ns'

11

ns

20

ns

20

ns

-

ns

5

ns

3

7

-

ns

'3

8

ns

3

8

ns

3

15

ns

tAVAV

tRC

20

tAVQV

tAA

-

Select Access Time

tSLOV

tACS

BaJi Access Time

tSCLQV

tASC

am Access Time

tSSLQV

tASS

-

Output Hold from Add....... Change

tAXOX

toH

5

Select Low to Output Active

tSLOX

tCSL

tBSLOX/tBCLOX

·tLZ

tSHOZ

tcsz

B§ETllreiJi High to Output High-Z

tSSHOZ/tSCHOZ

tHZ

am/liCiJ! Low to Match Assert

-

tSSLMX/tSCLMX

tCH

0

§ High to Output High-Z

Unit

20

Rsed Cycle Time
Add....... Access Time

am/BaJi Low to Output Active

Max

NOTES:
1. R= VIH,

2
2

iii = VIH continuously during read cycles: One of either BSET or liCiJ! pins must be aessrted low to activate the outputa. The
match output becomes asserted when either the BSET or BaJi pin transitions low.
2. For brevity in signal names, BC is used to represent BaJi transitions, while BS is used to reprasent RET transitions.
3. Transition is maasured ±500 mV fr"m stsedy &tate voltage with load of F'IIure lb. This paramater is sempled and not 100% tested.
READ CYCLE
IADORESS CONTRDllEDI

IS CDNTRoLLEDI

1+----tAVAV - - - - - + I
A IADDRESSI
tAvnV-----'l~

tAxnx

S ICHIP SELECn

~SET

IBIT SETI
tBSlMX

BCLR IBIT CLEARI
tBcLnx -+_---fio-l
tBCLMX
n loATA DUn ---HIGH·Z - - - i - l

MATCH

MATCH VALID

MOTOROLA MEMORY DATA
'5-70

MCM62350-20

COMPARE CYCLE (See Note 1)
Symbol
Characteristic

Standard

MCM823IiO-2O
Alternete

Min

Max

Unit

Notes

Compare Cycle Time

tAVAV

tc

20

-

Address Valid to Match Valid

tAVMV

tACA

-

20

ns

BCLR High to Match Valid

tBCHMV

tBCCA

-

15

ns

2

EET High to Match Valid

tBSHMV

tBSCA

15

ns

2

Data Valid to Match Valid

tOVMV

tOCA

10

ns

~ Low to Match Valid

tSLMV

tCSCA

-

12

ns

Match Hold from Address Change

tAXMX

tACH

5

ns

Match Hold from Data Change

tOXMX

tOCH

3

-

~ High

tSHMX

tCH

0

10

ns

tBCHQZ

tBCZ

8

ns

3

tBSHQZ

tBSZ

-

8

ns

3

to Match Aeeart

m:rR High to Output High-Z
1rnET High to Output High-Z

ns

ns .

NOTES:
1. R=VIH, W=VIH continuously during compare cyclas.
2. For brevity in signal namas, BC is uaad to represent m:rR transitions, while BS is uaad to represent BSE'f transitions.
3. Trensition is massured ±5OO mV from steady alate voltage with load of Figura lb. This paramatar is sampled and not 100% tastad.

COMPARE CYCLE
IS CONTROLLED)

lAO DRESS CONTROLLED)

1+---- 'AVAV - - - - - + I

J<_ _ _>C

A IAooRESSI

1-4--- 'AVMV ----1-1
S (CHIP SELECT!

IS=VIL)

iiSEi' (BIT SET)

BCLR (BIT CLEAR)

D (DATA IN) - - - - - - - - (
14---+--'DVMV
----HIGH·Z----+----+--

o (DATA OUT!

MATCH

MOTOROLA MEMORY DATA
5-71

..

MCM62350-20

STANDARD WRITE CYCLE (See Note 1)
Symbol

Charactarlstlc

Altemate

Min

Max

Write Cycle Time

tAVAV

twc

20

Write Pulse Width

twLWH/tSLSH
twLSH/tSLWH

twP
twP

14

-

Unit

ns

tAVWL/tAVSL

tAS

0

-

ns

Address Valid to End of Write

tAVWH/tAVSH·

tAW

16

-

ns

Oete Valid to End of Write

tOVWH/tOVSH

tow

10

-

ns

Oete Hold from Write End

twHox/tSHOX

tOH

0

-

ns

Write Low to Output High-Z

twLQZ

twz

-

8

n8

Address Hold from Write End

twHAX/tSHAX

twR

0

-

ns

Write Low to Match Asean

Notas

ns

Address Setup to Beginning of Write

2,3

twLMX

twCH

0

15

ns

tBSHWL/tBSHSL
tBCHWL/tBCHSL

tBSS
tBCS

-1

-

ns

twLBsx/tSLBSX
twLBcx/tSLBCX

tBSH
tBCH

10

-

ns

Write High to Match Valid

twHMV

twCA

-

20

ns

3

Write High to Output Active

twHQX

tow

3

-

ns

2,3

iiSE'fI~ Setup to Beginning of Write

II

MCM623IiCJ..2O

Standard

~1Bl:[R Hold Time from Write Sten

3

NOTES:
1. A standard write occurs during the overlap of W and ~ low and lmET and Bl:[R high. The II pin is high continuously during a write cycle.
2. Transition is measured ±500 mV from steady atete voltege with load of Figure lb. This parameter is sampled and not 100% tasted.
3. Both the match output and 00-03 are shown as valid in the W controlled cycle below to convey their timing relative to W. In reality, only
one of either match or 00-03 can be valid at one tim.., as determined by iiSE'fand iiEDi' inputs.
STANDARD WRITE CYCLE

liii CONTROLLEOI

IS CONTROLLEDI

f+----IAVAV - - - - - - 1
A IADDRESSI
IAVWH

1 ' + - - - - IWLSH -t-----..,-,-r
S ICHIP SELECn

iii IWRITE ENABLE!

BSET IBIT SET)

iirui IBIT CLEAR!.

o IDATA IN! -----+---[
twLOZ~_-+f

-------HIGH·Z--------

o IDATA DUn
IWLMX
MATCH

IASSERTED!

MOTOROLA MEMORY DATA
5-72

MCM62350-20

BSET/BCLR WRITE CYCLE (See Note 1)

MCM62350-211

Symbol

Characteristic

Unit

Standard

Alternate

Min

Max

Write Cycle Time

tAVAV

twc

20

twLWH/tSLSH
twLSH/tSLWH

twp
twp

14

-

ns

Write Pulse Width

ns

ns

Address Setup to Beginning of Write

tAVWL/tAVSL

tAS

0

Address Valid to End of Wr~e

tAVWH/tAVSH

tAW

14

-

Data Setup to Beginning of Write

tOVWL/tOVSL

tos

0

-

Data Hold from Write End

twHox/tSHOX

tOH

0

ns

Address Hold from Write End

twHAX/tSHAX

twR

0

-

twLMX

twCH

0

15

ns

tBSLWL/tBSLSL
tBCLWL/tBCLSL

tBSS
tBCS

-1

-

ns

twLBsx/tSLBSX
twLBcx/tSLBCX

tBSH
tBCH

10

-

ns

twHMV

twCA

-

211

ns

W Low to Match Assert

am1BCiJi" Setup to Beginning of Write
BSET1Bi2R Hold Time from Write Start
Wr~e

High to Match Valid

Notes

ns
ns

2

ns

2

NOTES:
1. A BSETIBCLR write occurs during the overlap of Wand S low and BSE'i' or BCLR low. The Ii pin is high continuously during a write
cycle. BSE'i' and BCLR write cycles can be W controlled or S controlled. Only two of four possible cycles are shown here for brevity.
2. Data output buffer must be in hlgh-Z p~or to start of either BSEi' or Bi2R write cycles. Note that for W controlled cycles, the user must
avoid excessive setup time of BSE'i'/BCLR to avoid bus contention. Data must be set up for tOVWL/tOVSL tima to ensure the data integrity
of non-modified bits during BSEi'/Bi2R write cycles. In the event that invalid data is presented for non-modified bits during the BSE'i'1
Bi2R write, note that it is not possible to recover the original data state by simply presenting velid data before the end of write.
BCLR WRITE CYCLE

BSET WRITE CYCLE

(W

(S

CONTROllED)

CONTROLLED)

A (ADDRESS)

S (CHIP SElECT)

W(WRITE ENABLE)

BSET (BIT SET)

BCLR (BIT CLEAR)

o !DATA IN)

a (DATA OUT) ------+--- HIGH-Z ----+-----tWLMX
MATCH

-------HIGH-Z - - - - - - - -

f4---if-- tWHMV

VALID

(ASSERTED)

MOTOROLA MEMORY DATA
5-73

..

MCM62350-20

CLEAR CYCLE (See Note 1)
Symbol

Characteristic

Max

-

70

Unit

Alterneta

tRLAV
tRLSV
tRLBSV
tRLBCV
tRLDV

teR
tCR
tCR
tCR
teR

R Pulse Width

tRLRH

tCLP

Reed Setup to if Low

twHRL

tRS

20
5

tRHWL

twH

0

tRLAX
tRLSX
tRLBSX
tRLQCX
tRLDX

tcx
tcx
tcx
tcx
tex

0

-

R Low to Match Assert

tRLMX

tMH

0

15

ns

if Low to Output Hlgh-Z

tRLOZ

tel

-

15

ns

if Low to Inputs Recognized

A

5

(Clear Cycle Tune)

em

Broi
D

Write Hold from

if High

if Low to Inputs Don't Care

A
~

EET
Broi
D

II

MCM8ZIIiO-2II
Min

Standard

-

Notee

ns

n8
ns

2

ns

2

ns

3

4

NOTES:
1. The address, EEl, and mR Inputs are don't cares during a claar cycle.
2. The clear cycle Is Initiated at the falling edge of if. The twHRL and tRHWL parematers must be satisfied to prevent an undesired cOnflguretlon
cycle.
3. "Inputs" for this paramater refers to an inputs except W.
4. Tra~sltion i,s measured ±500 mV from steady state voltage with load of Figure lb. This paramater Is sampled and not 100% tsstad.
CLEAR CYCLE
(FROM COMPARE CYCLEI
A (ADORESSI
tRLAX
tRLAV
S (CHIP SELECTI

ii (RESET!

Vi !WRITE ENABLEI

iiSEi' (BIT

SET!

BCLR (BIT CLEAR)
tRLOX
o (DATA INI
tRLDX
MATCH
VALID

MATCH
tRLDZ
o (DATA OUT!

HIGH·Z

HIGH·Z

MOTOROLA MEMORY DATA
5-74

MCM62350-20

CONFIGURATION CYCLE (See Notes 1 and 2)
Symbol
Characteristic
Configuration Control Pulse Width

S

R
Data Setup to End of Configuration
Cycle

S

R
Vi
5
R
Vi

Data Hold from End of Configuration
Cycle

MCM623IiO-2O
Unit

Notes

-

ns

3

10

-

ns

tDH
tDH
tDH

0

-

ns

-

ns

Standard

Alternate

Min

Max

tSLSH
tRLRH

tsp
tsp

20

tDVSH
tDVRH
tDVWH

tDS
tDS
tDS

tSHDX
tRHDX
twHDX

R High Pulse Width

tRHRL

tep

5

Write Setup to R Low

twLRL

tws

5

5 Satup to End of Configuration

tSLWH
tSlRH

tsws
tscs

20

R Satup to End of Configuration

tRLWH

tSR

20

tRLSL

tess

5

5 Satup to Beginning of Write
5 High to Output High-Z

tSHWL

twss

tSHOZ

W Low to Output High-Z

twLOZ

R Satup to

5 Low

ns
ns

4

ns

0

-

tHZ

-

9

ns

5

tHZ

-

9

ns

5

no
3

ns

NOTES:
I. A configuration cycle is performed during the overlap of Vi low, R low, and 5 low. Address, DOl, DQ3, B§Ef, and BCLR inputs are don't

cares during configuration cycles.
2. To ensure proper configuration of the device during power up, chip select must be equal to or greater than VIH.
3. A valid configuration can be performed with 5 asserted prior to R and Vi low transitions. Be aware, however, that array data may be altered
under this condition.
4. Note that terminating the cycle with R while leaving Vi and 5 asserted may cause array data to be altered.
5. Trensition is measured ±500 mV from steady state voltage with load of Figure lb. This paremeter is sampled and not 100% tested.

CONFIGURATION CYCLE

IARRAY PROTECTED)

IARRAY UNPROTECTED)

S ICHIP SELECn

RIRESET)

iii IWRITE ENABLE)

o IOATA IN

--+--{

o IOATA DUn

J----HIGH·Z---

MOTOROLA MEMORY DATA
5-75

II

MCM62350-20

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

T1TT
62360

X

XX

XX

Part Number _ _ _ _ _ _ _ _ _--....J_

'hl"'.. _,A2-T." ........"'=_
Speed (20=20 nsl
Package (P=Plastic DIP, J=Plastic SOJI

Full Part Numbers-MCM62350P2O
MCM6235OJ2O
MCM6235OJ2OR2

II

MOTOROLA MEMORY DATA
5-76

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62351

4K X 4 Bit Cache Address Tag
Comparator
with System Status Bit Functions
The MCM62351 is a 16,384 bit cache address tag comparator organized as 4096 tags
of 4 bits, fabricated using Motorola's high-parformance silicon-gate CMOS technology.
The device integratas a 4K x 4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit applications. Thess functions allow easy
interface to the MC68020 and MC68030 microprocessors, or any other environment
where efficient implementation of external cache memory is required.
The device has a reset (AI pin for flash clear of the RAM, which i8 useful for system
initialization. Individual bits within a tag can be sat or cleared via the BSET and BCLR
control input pins for valid bit updates.
The MCM62351 has two configurable comparator modas. The comparator can be configured as standard XNOR (exclusive NOR) for address tag comparison, or AOI (ANDOR-Invertl for determining whether specific bits in the 4-bit word are sat (for system
status applicationsl. The configuration of the comparator is accomplished by parforming
a write cycle with the A pin held low. The match output is opan drain, allowing efficient
combination of multiple match outputs using a wired-OR connection.
•
•
•
•
•
•
•
•

•

Single 5 V ± 10% Power Supply
22.125131) ns max
Fast Address to Match TIme;
10/12/15 n8 max
Fast Date to Match TIme;
Fast Read of Tag RAM Contents; 25131)135 ns max
Flash Clear of tha Tag RAM;
70170170 n8 max
Opan Drain Match Output
Bit Manipulation of Tags via BSET and BCLR Writas
Configurable Comparator Modes:
XNOR Mode for Address Tag Comparison
AOI Mode for System Valid Bit Comparison
High Board Density SOJ Package Available

r-o;;;w-...,

i i - -......~

PLASTIC
CASE 724

J PACKAGE
3OOMILSOJ
CASE810A

PIN ASSIGNMENT
A4 I

MEMORY
MATRIX
128 ROWS
-.r x 128 COLUMNS

,.

24

A5 I 2

23

VCC
A3

3

22

A2

A7 I 4

21

AI

A8 I 5

20

AD

A6

BLOCK DIAGRAM

AO-A6i--T-~

~~ ~1~
~-

A9 I 6

19

ii

Al0 I 7

18

Vss

All I 8

17

003

S:1
i il

9

16

002

10

15

001

BCLRil 11

14

000

BS£T'I 12

13

MATCH

PIN NAMES

I - - - - - - -....

AU-All. . . . . . . . . . . Address Inpuls

iii. . . . . . . . . . . . . . . Write Enable
S . . . . . . . . . . . . . . . . Chip Salect
BCLR. . . . . . . . Bit Clear Control Input

MATCH

iiSE'f. . . . . . . . . Bit Set Control Input
Ii ........

Reset (Flash Clear) Input
MATCH . . . . . . . . Match (Hit) Output
DOO-DOl . . . . . • . Data Input/Output
VCC . . . . . . . . • +5 V Power Supply
VSS . . • . . . • . . . . . . . . . Ground

000-D03--+---r--.....4lI

A7-All--~"""'oi

MOTOROLA MEMORY DATA

•

MCM62351

SIGNAL DESCRIPTIONS
AO-A11-ADDRESS INPUTS
The address lines anr used for indexing into the tag RAM
portion of the chip.
'

as indicated in the bit clear truth table. The BeLR input can
also be used to initiata a read cycle (nota that at least one of
the BSET/BeLR signals must be asserted to trigger a read
cycle).

,DQO-DQ3-DATA INPUT/OUTPUT
The'data lines are used as input for compare, .write, and
configuration cycles, and as output for read cycles.

R-RESET (FLASH CLEAR) INPUT
The reset control signal is used to initiate a clear cycle or a
configuration cycle.

BSET - BIT SET CONTROL INPUT
This control Signal is used for ORing data into the tag RAM
during BSET write cycles. Independent bits within the tag can
be set using the appropriate mask, as indicated in the bit set
truth table. The BSET input can also be used to initiate a read
cycle.

II

S-CHIP SELECT
This control signal is used to chip select tha device.
W-WRITE ENABLE
The write enable signal is used to initiate write cycles.

BCLR-BIT CLEAR CONTROL INPUT

MATCH-MATCH (Hin OUTPUT

This control signal, is used for AN Ding the complement of
data into the tag RAM during BeLR write cycles. Independent
bits within the tag can be cleared using the appropriate mask,

This output signal is used to indicata a match of DQO-DQ3
inputs with the contents of the tag RAM addressed by ADAll.
'

FUNCTIONAL TRUTH TABLE

ii

W

1RD

nET

R

DClD-D03

Match

Cycle

L
L
L
L
L
L
X
L
H

H
H
H
L
L
L
H
L
X

H
L
X
H
L
H
X
X
X

H
X
L
H
H
L
X
X
X

H
H
H
H
H
H
L
L
H

Compare Din
Read Dout
Read Dout
Write Ojn
Bit Clear Mask
Bit Set Mask
High-Z
Conflg Din*
High-Z

Valid
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert

Compare
Read
Read
Write
BCLR Write
BSET Write
Clear (Reset)
Configuration
Desalect

*001, DOl, and 003 are don't cares during a configuration evele.
COMPARATOR TRUTH TABLE
Type

DOD

DQl

002

003

RAMOD

XNOR
XNOR
Am
'AOI
AOI

ao
Oii
ao

01
01
01
01
01

Ol
Ol
Ol
Ol
Ol

03
03
03
03
03

ao
ao
ao

L
H

X
L

RAMQ1
,01
01
01
01
01

RAMQ2

RAM03

Match

Ol
02
Ol
Ol
Ol

03
03
03
03
03

1
0
1
1
0

BIT SET TRUTH TABLE (See Note)

BIT CLEAR TRUTH TABLE (See Note)
Data
In'

Initial
Storad Data

Final
Storad Data

0
0
1
1

0
1

0
1

Bit
Unchangad

0
1

0
0

Bit Cleared
to "Zaro"

NOTE: Thesa tebles reflect the bahavior of single bit positions.
The four bits in the tag can all ba sat or cleared in tendam,
or bits within the tag can ba indepandantly sat or cleared
with the appropriate mask.

Comparator
Type

L
H

XNOR
AOI

Data
In

Initial
Storad Data

Final
Stored Data

0
0
1
1

0

0
1
1
1

1

0
1

Bit
Unchangad
Bit Set
to "One"

AOI COMPARATOR LOGIC DIAGRAM

CONFIGURATION TABLE
DOD

L=Low
H=High
O=Falsa
1 =True
X = Oon't Care

MEMORY
ARRAY

MOTOROLA MEMORY DATA
5-78

MCM62351

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSs-o
- VI
Rating
Voltage Relative to VSS for Any Pin
Except VCC
Output Current

This device contains circuitry to protect the
inputs against damage due to high static

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

voltages or electric fields; however, it is ad-

VinIVout

-0.5 to VCC+0.5

V

40

mA

vised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.

Power Supply Voltage

Match Output
I/O Pins, Per I/O

lout

20

Power Dissipation (TA =25°CI

PD

Operating Temperature

TA

1.0

o to

The power supply IVCCI should be stable
for at least 100 pS before operating the device. During this interval, the part will internally configure itself for XNOR compares.
In addition, the memory array of RAM bits
will be cleared.

W

+70

°c

Storage Temperature

-55 to +125
°c
Tsta
-10 to +85
°c
Tbias
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
Temperature Under Bias

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 70o C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS=O V)
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Rangel

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

V)L

-0.5*

-

0.8

V

Parametar

Unit

*VIL min = -0.5 V dc; VIL min = -3.0 V ac (pulse width 520 nsl
DC CHARACTERISTICS

Symbol

Min

Max

Unit

Input Leakage Current (All Inputs Vin=O to VCCI

Ilka(ll

-

±1.0

,.A

Output Leakage Current ("S=VIH, Vout=O to VCCI
Match Output Leakage Current (Match Assertedl

Ilka(OI

±1.0

,.A

Characteristic

AC Supply Current ("S=VIL, lout = 0 mA, tAVAV=tAvaV maxi

II!mIMI

-

ICCA

-

Output Law Voltage (1/0 Pins: 10L =8.0 rnA, Match Output: 10L =23.0 mAl

VOL

-

Output High Voltage (110 Pins: 10H =4.0 mAl

VOH

2.4

±2.0

,.A

140*

mA

0.4

V

-

V

*ICC active current for the clear cycle exceeds this specification. Hawever, this is a transient phenomenon and will not affect the pawer dissipation
of the device. Good decoupllng of the local power supply shauld always be used.
CAPACITANCE (f=1 0 MHz dV=3 0 V TA=25°C Periodically Sampled Rather Than 100% Testad)
Characteristic

Symbal

Typ

Max

Unit

Cin

4

5

pF

Cout

5

7

pF

Cmatch

6

7

pF

Input Capacitance
I/O Capacitance
Match Output Capacitance

AC TEST LOADS

+5V

+5V

481

481

Q -.....- - - -. .

Figure 18

5 pF
(lNCWDlNG
SCOPE AND JIG)

255

Figure 1b

MOTOROLA MEMORY DATA
5-79

~

200

MATCH

Q -.....- - - -. .

30 pF
(INCLUDING
SCOPE AND JIG)

255

+5V

I

(lNCWDlNG
"::" 50PF
SCOPE AND JIG)

Figure 1e

•

MCM62351

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA=O to +70·e, Unless Otherwise Noted)

Output TIming Measurement Reference Level . • . . • . . • . 1.6 V
Output Load (l/O Pins) . • . • . • . • . • . . . . . • . See Figure la
Output Load (Match Output) • . • . • . • . . . . • • . See Figure lc

Input TIming Measurement Reference Level . . . • . • . • .. 1.5 V
Input Pulse Levels • • • • • . • . . • • • • • • . . . • • • • .0 to 3.0 V
Input Risel Fall TIme . . . • . • . . . . . . . • . . . . . • . • . . . 5 ns

READ CYCLE (See Note

1)

Svmbol

Characteristic

Stendard

II

MCM623&l-22 MCM623&l-2& MCM823Ii1-31
Alternate

Min

Max

Min

Max

Min

Max

Unit

Notee

Read Cycle TIme

tAVAV

tRC

25

-

30

-

36

-

ns

Address Access TIme

tAVQV

tM

25

no

tACS

12

15

ns

BCLR Access Time
irnE'i' Access TIme

tBCLQV

tABC

-

25

-

30

35

ns

2

tBSLQV

tABS

-

25

-

30

-

36

tSLQV

-

30

Select Access TIme

-

36

ns

2

Output Hold from Address Change

tAXOX

toH

5

5

5

ns

tSLOX

tcSL

5

-

5

-

5

-

ns

3

tBSLOX/tBCLOX

tLZ

10

-

10

-

10

-

ns

3

tSHOZ

tcsz

9

ns

3

9

10

-

12

tHZ

-

10

tSSHOZ/tBCHOZ

-

12

ns

3

tBSLMX/tBCLMX

tCH

0

16

0

18

0

20

no

Select Low to Output Active

urnIBCLR Low to Output Active
~ High to Output High-Z

BSE'i'I~ High to Output High-Z
irnE'i'/iicrR Low to Match Assart

16

NOTES:
1. R= VIH, iiii = VIH continuously during read cycles. One of either BSET or BCLR pins mUll! be asserted low to activete the outputs. The
match output becomes asserted when either the BSE'i' or ~ pin transitions low.
2. For brevity in signal names. BC is used to represent BCLR transitions, while BS is used to represent iiSET transitions.
3. Transition is mesaured ±500 mV from _dy state voltege with load,of Figure lb. This parameter is sampled and not 100% _ d .

READ CYCLE

(S CONTROLLED)

(ADDRESS CONTROllED)
!+----tAVAV - - - - - + I
A (ADDRESS)
IAyDV------IPj

IAXOX

S (CHIP SELECT)

Bm (8IT SET)
taslMX
BClR (BIT CLEAR)
IBClOX --I~:::t;t-1----1-IBClMX
o (DATA OUT) - '--HIGH·Z

MATCH

--"""'1-(

---HI6H·Z

MATCH VALID

MOTOROLA MEMORY DATA

5-80

OUTPUT VALID

MCM62351

COMPARE CYCLE (See Note

1)

Symbol

Characteristic

Standard

MCM823&1-22
Altarnata

Min

Min

30

Compare Cycle Time

tAVAV

tc

25

-

Address Valid to Match Valid

tAVMV

tACA

-

22

~ High to Match Valid

tBCHMV

tBCCA

8m High to Match Valid

tBSHMV

tBSCA

Data Valid to Match Valid

tDVMV

tDCA

S Low to Match Valid

tSLMV

Match Hold from Address Change

tAXMX

-

15

-

15

-

Min

-

35

18

-

18

-

25

-

ns

30

ns

20

ns

2

20

ns

2

18

20

ns

-

5

ns

3

3

-

-

3

-

ns

0

10

0

12

0

15

ns

-

9

-

10

-

12

ns

3

9

-

10

-

12

ns

3

-

16

tACH

5

tDXMX

tDCH

~ High to Match Assert

tSHMX

tcH

mii High to Output High-Z

tBCHOZ

tBCZ

RET High to Output High-Z

tBSHOZ

tBSZ

12

Not..

5

tcSCA

-

Unit

Max

-

10

Data Change

Max

-

~

Match Hold from

MCM823&1-25 MCM823&1-30

Max

15

ns

NOTES:
1. ii = VIH, W= VIH continuously during compare cycles.
2. For brevity in signal names, BC is ueed to repressnt mii transitions, while BS is ueed to represent RET transitions.
3. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This paramater is sampled and not 100% tested.

COMPARE CYCLE
(ADDRESS CONTRDLLEDI

IS CONTROLLEOI

1-+---- 'AVAV - - - - - t

)(~

A (ADORESSI

_ _>C

1 + - - - 'AYMV -----l-l
S (CHIP SELECTI

BSET (BIT SET)

iiC[R IBIT CLEARI

o /DATA I N I - - - - - - - {
1+-~-toYMV

o IDATA DUTI

----HI6H·Z-----I-----4-

MATCH

VALID

MOTOROLA MEMORY DATA
&81

..

MCM62361

STANDARD WRITE CYCLE (See Note 1)
Symbol

Characteristic

Alternata

Min

Max

Min

Max

Min

Max

Write Cycle Time

tAVAV

twc

25

-

30

-

35

Write Pulse Width

twLWH/tSLSH
twLSH/tSLWH

twP
twP

18

-

20

-

25

-

Add.... Setup to Beginning of Write

tAVwL/tAVSL

tAS

0

-

0

-

"0

Add .... Valid to End of Write

tAVWH/tAVSH

tAW

"18

-

20

-

25

Data Valid to End of Write

tDVWH/tDVSH

tDW

10

-

12

Data Hold from Write End

-

Notse

na
na
ns
ns

0

9

-

10

-

12

-

0

-

0

-

na
na

2,3

0

3

twHDX/tSHDX

tDH

0

twLOZ

twz

-

Add.... Hold from Write End

twHAX/tSHAX

twR

Write Low to Match Assert

-

Unit

-

Write Low to Output High-Z

14
0

ns"
ns

twLMX

twCH

0

15

0

15

0

18

ns

tBSHWL/tBSHSL
tBCHWL/tBCHSL

tBSS
tBCS

-1

-

-1

-

-1

-

ns

twLBsx/tSLBSX
twLBcx/tSLBCX

tBSH
t8CH

10

-

10

-

10

-

ns

Write High to Match Valid

IWHMV

twCA

-

22

-

25

30

ns

3

lWHax

tow

5

-

5

-

-

Write High to Output Active

-

ns

2,3

BET l!m Setup to Beginning of
Write

BSETI~ Hold Time from Write Start

II

MCM623&l-22 MCM82351-2& MCM623&l-30

Standard

5

NOTES:
1. A standard write occurs during the overlap of Vii and S low and BSE'i' and BCLR high. The Ii pin is high continuously during a write cycle.
2. Transition Is measurad ±500 mV from steady atate voltage with load of Figura lb. This parameter is sampled and not 100% taeted.
3. Both the match output and 00-03 ara shown as valid in the Vii controlled cycle below to convay their timing relativa to Vii. In reality, only
one of either match or 00-03 can be valid at one time, as determined by iiSE'i'and 8C[R inputs.

STANDARD WRITE CYCLE

Wi CDNTROLLEDI

(! CONTROLLED)

!+----tAvAV ------I~
A (ADDRESSI
tAVWH

!

1 + - - - - tWLSH -r--V--r"7'"
(CHIP SELECTI

W\WRITE ENABLEI

iiSE'f (BIT SETI

m (BIT CLEAR)

o (DATA I N I - - - - - + - - . . . . . (

Q (DATA

-------HIGH·Z--------

OUTI
twLMX

(ASSERTED)

MATCH

MOTOROLA MEMORY DATA
5-82

MCM62351

BSET/BCLR WRITE CYCLE (See Note 1)
Symbol

Characteriatlc

MCM823&I-22 MCM82351-2&

MCM823&I-30

Standard

Alternate

Min

Max

Min

Max

Min

Max

Write Cycle Time

tAVAV

twc

25

twP
twP

18

-

35

twLWH/tSLSH
twLSH/tSLWH

-

30

Write Pulse Width

25

-

20

Address Setup to Beginning of Write

tAVWL/tAVSL

tAS

0

-

0

Address Valid to End of Write

tAVWH/tAVSH

t/>W

18

-

20

-

-

ns

-

ns

-1

-

0

ns

ns

tOVWL/tOVSL

tos

-1

-

-1

twHox/tSHOX

tOH

0

-

0

Address Hold from Write End

twHAX/tSHAX

twR

0

-

0

-

0

-

twLMX

twCH

0

15

0

15

0

18

tBSLWL/tBSLSL
tBCLWL/tBCLSL

tBSS
tBCS

-1

-

-t

-

-1

twLBsx/tSLBSX
twLBcx/tSLBCX

tBSH
tBCH

10

-

10

-

10

-

twHMV

twCA

-

22

-

25

-

30

BSE'i'leaJi Setup to

Beginning of

Write

BSE'i'IBeLR

Hold TIme from Write Start

Write High to Match Valid

ns

0

Oata Hold from Write End

Notes

ns

25

Oata Setup to Beginning of Write

W Low to Match Assert

Unit

ns

2

ns

ns

2

ns
ns

NOTES:
1. A imE'i'/BCLR write occurs during the owrlap of 'iii and 5 /ow and'BSET or BeLR /ow. ,The if pin is high continuously during a write
cycle. imE'i' and BCLR write cycles can ba 'iii controlled or 5 controlled. Only two of four poasible cycles are shown here for brevity.
2. Data output buffer must be in high-Z prior to start of either BSE'i' or BCLR write cycles. Note that for 'iii controlled cycles, the user must
avoid excessive setup time of imE'i'/iiO:Ii to avoid bus contention. Oata must ba set up for tOVWL/tOVSL time to ensure the data integrity
of non-modified bits during BSE'i'/Ern write cycles. In the ewnt that invalid date is presented for non-modified bits during the imE'i'1
iiO:Ii write, note that it is not poasible to recowr the Original data state by simply presenting valid data before the end of write.

BSET WRITE CYCLE

t;lCLR WRITE CYCLE

is CONTROllED)

(Vi CONTROllED)
A (ADDRESS)

5 ICHIP SELECT)

Vi IWRITE ENABLE)

am (BIT SET)
BCDi (BIT CLEARI

D (DATA INI

n (DATA O U T l - - - - - + - -

-------HIGH·Z - - - - - - -

MATCH

!ASSERTEDI

MOTOROLA MEMORY DATA
5-83

..

MCM62351

CLEAR CYCLE (Sea Nota 1)
Symbol

Characteristic

Altarnata

tRLAV
tRLSV
tRLBSV
tRLBCV
tRLDV

teR
teR
teR
tCR
teR

Ii Pulse Width

tRLRH

tCLP

25

Read Setup to Ii Low

twHRL

tRS

5

Write Hold from R High

tRHWL

twH

0

tRLAX
tRLSX
tRLBSX
tRLBCX
tRLDX

tex
tcx
tex
tex
tcx

R Low to Metch Assart

tRLMX

Ii Low to Output Hlgh-Z

tRLOZ

Ii Low to InpulS Recognized

A

'S
BSET

(Clear Cycle Time)

BC[Ji

0

R Low to Inputs Don't Care

A

'S
8m'
BCrR
0

•

MCM823&l-22 MCM823&l-2& MCM823&l-30

Standard

Unit

N_

Min

Max

Min

Max

Min

Max

-

70

-

70

-

70

no

-

36
5

-

no

0

-

n8

2

0

-

no

3

-

30
0

0

-

tMH

0

15

0

18

0

20

no

tez

-

15

-

18

-

20

n8

-

5

-

0

no
2

4

NOTES:

1. The address, ~, and BC[Ji inputs are don't caras during a clear cycle.
2. The clear cycle is initiated at the falling edge of Ii. The twHRL and tRHWL parameters must be satisl'oeII to preventan undesired configuration
'
cycle.
3. "lnpulS" for this parameter ratars to aU inpulS excapt W.
4. Transition is measured ± 500 mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% tested.
CLEAR CYCLE

(FROM COMPARE DR WRITE CYCLE)
--------~

A!ADDRESS)

I (CHIP SELECT)

~----

tRLAX
tRLSX

If IRESEn

IV !WRITE ENABLE)
IRlBSX

BEi'lBlTsrn
tRlBCX

8CIJ! (BIT CLEAR)

o (DATA IN
IRlOX
MATCH
_ _. .;¥;;,:AU::;O____

MATCH

J/~X

tRw
Q (DATA

OUT)

-------HlGII-Z------_

HIGH·Z

MOTOROLA MEMORY DATA
5-84

MCM62351

CONFIGURATION CYCLE (See Notes 1 and 2)
Symbol

Characteristic

5

Configuration Control Pulse Width

R

5

Data Setup to End of Configuration
Cycle

R

W
Oata Hold from End of Configuration
Cycle

5
R

W

MCM62361-22 MCM82361-25 MCM82361-30

Unit

Notes

-

ns

3

14

-

ns

0

-

ns

5

-

ns

5

-

Standard

Alternate

Min

Max

Min

Max

Min

Max

tSLSH
tRLRH

tsp
tsp

20

-

25

-

30

tOVSH
tOVRH
tOVWH

tos
tos
tos

10

-

12

-

tSHOX
tRHOX
twHOX

tOH
tOH
tOH

0

-

0

-

R High Pulse Width

tRHRL

tep

5

twLRL

tws

5

-

5

Write Setup to R Low

5

-

5

Setup to End of Configuration

tSLWH
tSLRH

tsws
tscs

20

-

25

-

30

-

25

-

30

5
0

-

R Setup to End of Configuration

tRLWH

tSR

20

R Setup to "5 Low

tRLSL

tess

5

5 Setup to Beginning of Write
"5 High to Output High-Z

tSHWL

twss

0

-

tSHOZ

tHZ

-

9

-

W Low to Output High-Z

twLOZ

tHZ

-

9

-

ns
ns

4

5

-

0

-

ns

10

-

12

ns

5

10

-

12

ns

5

ns
ns

3

NOTES:
1. A configuration cycle is perfonned during the overlap of W low, R low, and 5 low. Address, 001, OOZ, OQ3, lim, and BO:R inputs are
don't cares during configuration cycles.
2. To ensure proper configuration of the device during power up, chip select must be equal to or greater than VIH.
3. A valid configuration can ba performed with "5 asserted prior to Rand W low transitions. Be aware, however, that array data may ba altered
under this condition.
4. Note that terminating the cycle with R while leaving W and "5 asserted may cause anray data to be altered.
5. Transition is measured ±600 mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% testad.

CONFIGURATION CYCLE
(ARRAY PROTECTED)

(ARRAY UNPROTECTED)

5 (CHIP SELECT)

Ii (RESET)

W(WRITE ENABLE)

D (DATA IN

--+--(

o (DATA DUn

I---HIGH·Z---

MOTOROLA MEMORY DATA

..

MCM62351

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

T1TT
62361

X

XX

XX

Part Number -----------~

.....'" -...,"= TO,.. '''', '""'=.""
Speed (22=22 ns, 25=25 ns, 30=30 nsl
Package (P ~ Plastic, J = Plastic SOJI

Full Part Numbers-MCM62351P22
MCM62351J22
MCM62351J22R2

MCM62351 P25
MCM62351J25
MCM62351J25R2

II

MOTOROLA MEMORY, DATA
5-86

MCM62351 P30
MCM62351J30
MCM62351J30R2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62351-20

Product Preview
4K X 4 Bit Cache Address Tag
Comparator

~

with System Status Bit Functions

PPACKAGE
3110 MIL PLASTIC
CASE 724

The MCM62351 is a 16,384 bit cache address tag comparator organized as 4096 tags

of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology.
The device integrates a 4K x 4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit applications. Thesa functions allow easy
interface to the MC68020 and MC68030 microprocessors, or any other environment
where efficient implementation of external cache memory is required.
The device has a reset fA) pin for flash clear of the RAM, which is useful for system
initialization. Individual bits within a teg can be sat or cleared via the BSET and BCLR
control input pins for valid bit updates.
The MCM62351 has two configurable comperator modes. The comparator can be configured as standard XNOR (exclusive NOR) for address tag comperison, or AOI (ANDOR-Invert) for determining whether specific bits in the 4-bit word are sat Itor system
status applications). The configuration of the comperator is accomplished by performing
a write cycle with the R pin held low. The match output is open drain, allowing efficient
combination of multiple match outputs using a wired-OR connection.
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
20 ns max
Fast Address to Match TIme;
10 ns max
Fast Data to Match Time;
Fast Read of Tag RAM Contents; 20 ns max
Flash Clear of the Tag RAM;
70 ns max
Open Drain Match Output
Bit Manipulation of Tags via BSET and BCLR Writes
Configurable Comparator Modes: XNOR Mode for Address Tag Comperison
AOI Mode for System Valid Bit Comperison

r-=--,
AD-AS---;'-!-I

il--_+t

~

CASE810A

PIN ASSIGNMENT
A4

MEMORY
MATRIX
128 ROWS
i - - - - - - - . . - - - . l x 128 COWMNS

1.

A5

24 VCC
23 A3

A8

22

A2

A7

21

Al

AS

20

AD

A9

19 'Ii

AIO

18

Vss

All

17

003

18

002

15

DOl

'I
W 10
11

14

mID

m'f 12

13

MATCH

mJI

BLOCK DIAGRAM

JPACKAGE

3IIOMILSOJ

PIN NAMES
AO-All •.••..••••• Add..- Inputs

W. . . . . . . . . . . . . . .

Write Enable

'!! • . . . . . . . . . . . . . . . Chip Select
MATCH

Em. . . . . . . .Bit Clear Control Input
RET. . . . . . . . .Bit Sat Control Input

mID-rnu'--;---T---~

'If . . . . . . . . Reset (Flash Clearllnpul
MATCH .•.•.•.• Match (Hitl Output
OClO-003 •••.••• Om Input/Output
VCC ••••••••• +5 V Power Supply
VSS ••.•..•.•.•.••.• Ground

A7-All-""","'--1-1

This doc\Imem contIIins infonnation on • product u _ d~. Motorola I'8NlVtlllIhe right to change or diacontInua this product without notice.

MOTOROLA MEMORY DATA

..

MCM62351-20

SIGNAL DESCRIPTIONS
AG-A11-ADDRESS INPUTS
The addres lines are used. for indexing into the tag RAM
portion of the chip.
DQO-DQ3-DATA INPUT/OUTPUT
The data lines are used as input for compare, write, and
configuration cycles, and as output for read cycles.

as indicatad in the bit clear truth table. The BClR input can
also be used to initiata a read cycle (nota that at least one of
the BSET/BClR signals must be asserted to trigger a read
cycle).
ii-RESET (FLASH CLEAR) INPUT
The reset control signal is used to initiate a clear cycle or a
configuration cycle.

BSET-BIT SET CONTROL INPUT

..

This control signal is used for ORing data into the tag RAM
during BSET write cycles. Independent bita within the tag can
be set using the approprista mask, as indicated in the bit set
truth table. The BSET input can also be used to initiata a read
cycle.

S-CHIP SELECT
This control signal is used to chip select the device.
iN-WRITE ENABLE
The write enable signal is used to initiate writa cycles.

BCLR-BIT CLEAR CONTROL INPUT

MATCH-MATCH (HIT) OUTPUT

This control signal is used for ANDing the complement of
data into the tag RAM during BClR writa cycles. Independent
bita within the tag can be cleared using the appropriata mask,

This output signal is used to indiceta a match of OOO-D03
inputs with the contants of the tag RAM addrassed by AOA11.

FUNCTIONAL TRUTH TABLE
S

W

1RD

II!'i'

R

DOO-D03

Match

L
L
L
L
L
L

H
H
H
L
L
L
H
L
X

H
L
X
H
L
H
X
X
X

H
X
L
H
H
L
X
X

H
H
H
H
H
H
L
L
H

Compare Din
Read Dcut
Read Dcut
Write Din
Bit Clear Mask
Bit Sat Maak
High·Z
Config Din*
High·Z

Valid
Asaert
Asaert
Asaert
Asaert
Asaert
Asaert
Asaert
Assert

X

L
H

X

Cycle
Compare
Read
Read
Write
~Write

nETWrlta
Clear (Resetl
Conflguration
Daaalect

* DQ1, 002, and DQ3 are don't cares during a configuration cycle.
COMPARATOR TRUTH TABLE
Type

DOD

DQ1

DOZ

DQ3

RAMOD

RAMQ1

RAMQ2

RAMQ3

Match

XNOR
XNOR
·AOI
AOI
AOI

QO

01
01
01
01
01

02
02
02
02
02

03
03
03
03
03

QO

01
01
01
01
01

02
02
02
02
02

03
03
03
03
03

1
0
1
1
0

nil

ao
L
H

ao
QO

X
L

BIT SET TRUTH TABLE (Sea Notal

BIT CLEAR TRUTH TABLE (Sea Notal
Data
In

Initial
Stored Data

Final
Stored Data

0
0
1
1

0
1
0
1

0
1
0
0

Data
In

InItial
Stored Data

Final
Stored Data

Bit
Unchanged

0
0

0
1

Bit Cleared
to "Zero"

1
1

0
1

0
1
1
1

NOTE: Theaa tables reflect tha behavior of single bit poaltions.
The four bits in tha tag can all be eat or cleared in tandem,
or bits within the tag can be indepandendy set or cleared
with the appropriate mask.

Comparetor
Type

L
H

XNOR
AOI

Bit
Unchanged
Bit Sat
to "Ona"

AOI COMPARATOR LOGIC DIAGRAM

CONFIGURATION TABLE
DOD

L=Low
H=High
0= Falea
1=Tru8
X = Don't Care

MOTOROLA MEMORY DATA

MCM62361-20

ABSOLUTE MAXIMUM RATINGS (Voltagaa referenced to VSS=O VI
RatIng
Power Supply Voltage

Symbol

Voltage Relative to VSS for Anv Pin
ExceptVCC
Output Current
Match Output
1/0 Pins, Per 1/0
Power Dissipation (TA = 25DCI
Oparating Temperature
Storage Temperature
Temperature Under Bias

VCC
VinlVout

Unit

Value
-0.5 to +7.0
-0.5 to VCC+0.5

V
V

40

rnA

lout

20

1.0
+70
-55 to +125
-10to +86

Po
TA
TtIIg

W

o to

DC
DC
DC

Tbiaa
NOTE: Permanent device damage mav occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be raetricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voItagesforextendad
periods of time could affect device reliabHitv.

This device contains circuitry to protect the
inputs against damage due to high etatlc
voltagaa or electric field.; however, It Is advilled that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.
Tha power eupply (VCCI should be stable
for at least 100 pa before operating the device. During thia intarval, the part wiD intarnsHyconfigure I18e1fforXNOR compares.
In addition, the rnemorv array of RAM bits
wiD be clsered.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V :1:10%, TA=O to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS =0 VI

Panom_

Symbol

Min

TVp

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

Input Low Voltage

VIL

-0.5*

-

Symbol·

Min

VCC+0.3

V

0.8

V

Mu
:1:1.0
:1:1.0

Unit

*VIL rmn= -0.5 V de; VIL mm= -3.0 V ac (pulse WIdth s20 nsl
DC CHARACTERISTICS
Chanoctsrlatlc
Input Leskege Current (All Inputa Vln=O to VCC)

Ilka(l)
(lka(OI

Output Leskage Current (!sVIH, Vout=O to VCCI
Match Output Leskege Current (Match "-tad)

Ilka(MI
ICCA
VOL

AC Supply Current (S = Vllo lout = 0 rnA, tAVAV = tAvaV maxi
Output Low Voltage 11/0 Pins: 10L =8.0 rnA, Match Output: 10L =23.0 rnAl
Output High Voltage 11/0 Pins: IOH=4.0 mAl

-

:1:2.0
140*
0.4

-

pA
pA
pA

rnA
V

-

2.4
V
VOH
*ICC active current for the claar evele exceed. this specification. H..-ver, this is a transiant phenomenon and will not affect the power dissipation
of the device. Good decoupling of the local power supply should always be used.
CAPACITANCE

(f = 1 0

MHz. dV = 3 0 V TA = 25DC Period'ocaHy Sampled Rather Than 100% Testadl
Chanoctsrlatlc

Input Capecitance
I/O Capecitance
Match Output Capacitance

Symbol

Typ

Mu

Cin

4
6
6

5
7
7

Cout
Cmatch

Unit
pF
pF
pF

AC TEST LOADS

+5V

+5V

481

481

0-+-----.
255

QNCUIDING
SCOPE AND JIGI

Flgura1a

5""

255

::oV

~RH---1

Il-+----~

30 pF

!

QNCLU111N6
SCOPE AND JIGI

Figure 1b

MOTOROLA MEMORY DATA

I

ftNCWDlNG
50pF
..,. SCIII'f
AND JlGI

Figure 1c

..

MCM62351-20

AC Of»ERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%. TA=O to +70oC. Unless Otherwise Notedl
Input Timing Measurement Reference Level • • • • . • • • •• 1.5 V
Input Pulse LevelS '. . . . . • . , • . . • . . . • . • . . • . .0 to 3.0 V
Input Rise/Fail Time • . • . • . • • • • • • • . • • • . • . • . • • • 5 ns

Output Timing Meesurement Reference Level • • • • • • • • • 1.5 V
Output Load 11/0 Pinsl . • . • . • . • • • • • • • • •• See Frgure la
Output Load (Match Outputl . . • . • . . . . . • • • • See Figure Ie

READ CYCLE (See Nota 1'1
Symbol

. Charactariatlc

•

Standard

MCM823&1-20
Alternata

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

20

-

ns

Address Access Time

tAVQV

tAA

-

20

ns

Sslect Access Time

tSLQV

tACS

-

11

ns

~ Access Time

tBCLQV

tABC

20

ns

2

BSET Access Time

tBSLQV

tABS

-

20

ns

2

Output Hold from Address Change

tAJ(ax

toH

5.

Select Low to Output Active

RET/ElJi Low to Output Active

tSLax

tCSL

5

-

ns

3

tBSLax/tBCLax

lU

7

-

ns

3

ns

tSHQZ

tcsz

-

8

ns

3

am/iR:iJi High to Output High,Z

tBSHQZ/tBCHQZ

tHZ

8

ns

3'

~ /~ Low to' Match Assert

-

tBSLMX/tBCLMX

tcH

0

16

ns

S" High to Output' High·Z

NOTES:

. .
, .
1. R VIH. iN VIH continuously during read cycles. One of either
or !erR pins must be aeserted low to actillate the outputs. The
match output becomes aeserted when either the ~ or ~ pin transitions low.
2. For brevity in signal names. BC is used to represent iR:iJi trensitions. while BS is used to represent iim transitions.
3. Transition is measured ± 600 mV from steady state voltage with load of Figure lb. This parameter is sempled and not 100% tested.

=

am

=

READ CYCLE
IS CONTROLLEDI

IADDRESS. CONTROLLEDI
I+----'AVAV -----+I
A fADDRESS!

'AVOV---"
~ ICIUP SELEen

'AXOX

II=VILI

ftl'fIBIT.srn

limilBlTCLEARI

'BCLOX -+--tlo-t
'BCLIIX

o IDATA OUTI ---HIGH·Z ----i-{
MATCH

---HIGH·Z

MATCH VAUD

MOTOROLA. MEMORY DATA

OUTPUT VAUD

MCM62351-20

COMPARE CYCLE (See Note 11
Symbol

Characteristic

Standard

MCM62351-20
Altarnata

Min

20

Compare Cycle Time

tAVAV

tc

Address Valid to Match Valid

tAVMV

tACA

BClR High to Match Valid

tBCHMV

tBCCA

~ High to Match Valid

IBSHMV

tBSCA

-

Max

Unit

-

ns

20

ns

Notes

15

ns

2

15

ns

2

Oata Valid to Match Valid

IOVMV

tOCA

-

10

ns

S low to Match Valid

tSlMV

tCSCA

-

12

ns

Match Hold from Address Change

IAXMX

tACH

5

Match Hold from Oata Change

IOXMX

tOCH

3

-

S High to Match Assert

tSHMX

tCH

0

10

mIi High to Output High-Z

tBCHOZ

tBCZ

8

ns

3

BSET High to Output High-Z

tBSHOZ

tBSZ

-

8

ns

3

ns
ns
ns

NOTES:
1. "R =VIH, W=VIH continuously during compare cyclas.
2. For brevity in signal names, BC is used to represent mIi transitions, while BS is used to represent ~ transitions.
3. Transition is measured ±500 mV from steady state voltage with load of Figure lb. This paramater is sampiad and not 100% tested.

COMPARE CYCLE
(ADDRESS CONTROLLEDI

IS CONTROlLED)

f 4 - - - - - tAVAV - - - - . . . . ,

)('----_ _>C

A IADDRESSI

1 + - - - tAYMY---+t

Ii ICHIP SELECTI

BSrr IBIT SET)

BCLii IBIT CLEAR)

D (DATA I N ) - - - - - - - i

----HI6H·Z~----+_---'""""'l-

Q IDATA OUT)

MATCH

MOTOROLA MEMORY DATA
5-91

II

MCM62351-20

STANDARD WRITE CYCLE (See Note 1)
Symbol
Characteristic

Max

Unit

Alternate

Min

Write Cycle Time

tAVAV

twc

20

-

ns

Write Pulse Width

twLWH/tSLSH
twLSH/tSLWH

twp
twp

14

-

ns
ns

Address Setup to Beginning of Write

tAVWL/tAVSL

tAS

0

-

Address Valid to End of Write

tAVWH/tAvSH

tAW

16

-

ns

Data Valid to End of Write

tOVWH/tOVSH

tow

10

-

ns

Data Hold from Write End

-

ns

8

ns

twHox/tSHOX

tOH

0

Write Low to Output High-Z

twLOZ

twz

-

Address Hold from Write End

twHAX/tSHAX

twR

0

-

ns

Not..

2,3

twLMX

twCH

0

15

ns

Beginning of Write

tBSHWL/tBSHSL
tBCHWL/tBCHSL

tBSS
tBCS

-1

-

ns

B5E'1'/Bm Hold Time from Write Start

twLBsx/tSLBSX
twLBcx/tSLBCX

tBSH
tBCH

10

-

ns

Write High to Match Valid

twHMV

twCA

-

20

ns

3

Write High to Output Active

twHQ)(

tow

3

-

ns

2,3

Write Low to Match Assert

B5E'1'/Bm Setup to

II

MCM823Ii1-20

Stendard

3

NOTES:
1. A standard write occurs during the overlap of Wand S low and B5E'I' and Bm high. The R pin is high continuously during a write cycle.
2. Transition is measured ± 500 mV from steady state voltage with load of Figura lb. This parameter is sampled and not 100% tested.
3. Both the match output and QO-Q3 ara shown as valid in the W controlled cycle below to convey their timing relative to W. In reality, only
one of either match or QO-Q3 can be valid at one time, as determined by B5E'I' and Bm inputa.

STANDARD WRITE CYCLE

is CONTROLLEOI

(W CONTROUED)

A IADDRESS)

S ICHIP SElfCT)

IV IWRITE ENABlE)

mil 18IT ClfAR)

o IDATA I N I - - - - - - 1 I - - - {

o (DATA OUT)

-------HIGH·Z-------

twLMX
IASSERTEO)

MATCH

MOTOROLA MEMORY DATA

MCM62351-20

BSET/BCLR WRITE CYCLE (See Note 1)
Symbol
Charactaristlc

MCM823&1-20

Unit

Stendard

Alternate

Min

Max

Write Cycle TIme

tAVAV

twc

20

twLWH/tSLSH
twLSH/tSLWH

twP
twP

14

-

ns

Write Pulse Width

ns

Address Setup to Beginning of Write

tAVWL/tAVSL

tAS

0

-

ns

Address Valid to End of Write

tAVWH/tAVSH

tAW

14

-

ns

Date Setup to Beginning of Write

tOVWL/tOVSL

tos

0

-

ns

Data Hold from Write End

twHDX/tSHOX

tOH

0

-

ns

Address Hold from Write End

twHAX/tSHAX

twR

0

-

ns

twLMX

twCH

0

15

ns

tBSLWL/tBSLSL
tBCLWL/tBCLSL

tBSS
tBCS

-1

-

ns

twLBSx/tSLBSX
twLBcx/tSLBCX

tBSH
tBCH

10

-

na

iii Low to Match Assert
BSE'i'/BCLR Setup to Beginning of Write

BSE'i'/BCLR Hold Time from Write Start

Notes

2

2

-

Write High to Match Valid
20
ns
twHMV
twCA
NOTES:
1. A !rnE'f IBCLR write occurs during the overlap of iii and "S" low and irnET or BCLR low. Tha It pin is high continuously during a write
cycle. iiSE'i' and BCLR write cycles can be iii controlled or"S" controlled. Only !we of four possible cycles are shown here for brevity.
2. Data output buffer must be in high-Z prior to start of eithar 1!m or ~ write cycles. Note that for iii controlled cycles, tha user must
avoid excessive setup time of iiSE'i'/BCLR to avoid bus contention. Data mllst be set up for tOVWL/tDVSL time to ensure the data Integrity
of non-modified bits during BSET IBCLR write cycles. In tha event that invalid data Is presented for non-modified bits during tha BSE'i'1
BCLR write, note that it is not possible to recover tha original data state by simply presenting valid data before tha end of write.

BCLR WRITE CYCLE

BSET WRITE CYCLE

(ii CONTROllED)

IS CONTROLLED!

A (ADDRESS)

S (CHIP SELECT)

Vi (WRITE ENABLE)

iiSEi' IBIT SET)

BCLR IBIT CLEAR)

o IOATA INI

o (DATA OUT!

-----+---

-------HIGH·Z - - - - - - -

MATCH

(ASSERTED!

MOTOROLA MEMORY DATA
5-93

III

MCM62361-20

CLEAR CYCLE (See Note 11
Symbol

MCM82361-20

Charactarlstlc

Unit
Standard

Altarnata

tRLAV
tRLSV
tRLBSV
tRLBCV
tRLDV

tCR
tCR
tCR
tCR
tCR

'Ii PUI88 Width

tRLRH

Read Setup to ii Low

twHRL

Write Hold from ii High

Max

-

70

tCLP

20

-

tRS

5

-

ns
ns

tRHWL

twH

0

-

ns

2

tRLAX
tRLSX
tRLBSX
tRLBCX
tRLDX

tcx
tcx
tcx
tcx
tcx

0

-

n8

3

R Low to Match Assert

tRLMX

tMH

0

15

R Low to Output High-Z

tRLOZ

tez

-

15

ns
ns

4

'Ii Low to

Inputs Recognized
(Claar Cycle Tima)

A

!
8m
~

0

R Low to Inputs Don't Care

A

!
8m
~

..

N0ta8

Min

0

n8

2

NOTES:
1. The address, ii!Ei', and BeLR inputs are don't cares during a clear cycle.
2. The clear cycle is initiated altha failing edge of it The twHRL and tRHWL parameters must be satisfied to prevent an undesired configuration

cycle.
3. "Inputs" for this parameter refers to all inputs except W.
4. Transition i. measured ± 500 mV from steady &tete voltage with load of Figura lb. This parameter is sampled and not 100% tested.

CLEAR CYCLE
(FROM COMPARE OR WRITE CYCLE)
A IADDRESS)
IftLAX
IftLAV

S (CHIP SELECn

RIRESET)

i (WtItTE ENABLE)

mIBlTSET)

mJi !BIT CLEAR)

D (DATA II
IRLDX

)IftLMX
MATCH
VALID

MATCH
IftL02
a IDATA oun

HIGH·Z

MOTOROLA MEMORY DATA

HIGH·Z

MCM62351-20

CONFIGURATION CYCLE (See Notes 1 .nd 2)
Symbol

Characteristic

MCM62351-20

Unit

Notes

-

ns

3

Standard

Altarnate

Min

Max

20

Configuration Control Pulse Width

!
R

tSLSH
tRLRH

tsp
tsp

Data Satup to End of Configuration
Cycle

!
R

tOVSH
tOVRH
tOVWH

tos
tos
tos

10

-

ns

tSHOX
tRHOX
twHOX

tOH
tOH
tOH

0

-

ns

-

ns

W
S"

O.ta Hold from End of Configuration
Cycle

R

W
R High Pulll Width

tRHRL

tcp

5

Writa Satup to R Low

twLRL

tws

5

! Setup to End of Configur.tion

tSLWH
tSLRH

tsws
tscs

20

R Setup to End of Configuration

tRLWH

tSR

20

-

ns

R Setup to S Low

tRLSL

tess

5

-

ns

S" Setup to Beginning of Writa

tSHWL

twss

0

-

ns

! High to Output High-Z

tSHOZ

tHZ

-

9

ns

5

W Low to Output High-Z

twLOZ

tHZ

-

9

ns

5

ns
ns

4

3

NOTES:
1. A configuration cycle is performad during the overl.p of W low, If low, and! low. Address, DOl, DOl, 003, ii!E1', and ~ inputs are
don't cares during configuration cycles.
2. To ensure proper configur.tion of the device during power up, chip 88iect must be equal to or greater than VIH.
3. A v.lid configuration can be performad with! ....rted prior to R .nd W low transitions. Be aware, however, that array date may be altered
under this condition.
4. Note that terminating the cycle with R while leeving W .nd 5 aseerted may caUII array data to be altered.
5. Tr.nsition is mBSaured ±500 mV from steedy stata voltege with load of Figure lb. This peramater is sampled and not 100% tested.

CONFIGURATION CYCLE
IARRAY PROTECTED)

(ARRAY UNPROTECTED)

S (CHIP SELECT)

Ii (RESET)

W (WRITE ENABLE)

o(DATA IN -+-0(

D (DATA OUT)

1---HlGH-Z---

MOTOROLA MEMORY DATA
5-95

II

MCM62351-20

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

T11 T
62361

X

XX

XX

Part Number _ _ _ _ _ _ _ _ _ _ _
..J

S_"'_."R2=T.... _ ....-,..,
Speed (20=20 ns)
Package (P = Plastic, J = Plastic SOJ)

Full Part Numbers-MCM62351P20
MCM62351J2O
MCM62351J2OR2

•

MOTOROLA MEMORY DATA
5-96

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62963

Product Preview
4K X 10 Bit Synchronous Static RAM
with Output Registers
The MCM62963 is a 40,960 bit synchronous static random access memory organized as

4096 words of 10 bits, fabricated using Motorola's second-generation high-performance
silicon-gate CMOS (HCMOS III) technology. The device integrates input registers, high
speed SRAM, and high-drive capability output registers onto a single monolithic circuit.
This allows reduced parts count implementation of cache data RAM, writeable control
store applications, and other applications that utilize long words.
Synchronous design allows precise cycle control with the use of an external clock (K),
while CMOS circuitry reduces the overall power consumption of the integrated functions
for greater reliability.
The address (AO-All), date (00-09), write (W), and chip enable (E) inco
puts are all clock (K) controlled, positive-edge-triggered, noninverting
registers.
5
The chip enable (E) input is a synchronous input clock that places the
05! 7
device in a low power mode when high at the rising edge of the clock (K).
NC! 8
The MCM62963 provides output register operation. At the rising edge of
NC
clock (K), the RAM data from the previous clock (K) high cycle is

FN PACKAGE
44-LEAD PLCC
CASEm

PIN ASSIGNMENT

... ... ... .....

presented.
Write operations are internally self-timed and initiated by the rising edge
of the clock (K) input. This feature eliminates complex off-chip write pulse
generation and provides increased flexibility for incoming signals.
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Cycle TImes: 20/25/3tJ ns Max
Fast Clock (K) Access TImes: 10110/13 ns Max
Address, Data Input, E, and W Registers On-Chip
Output Registers for Fully Pipelined Applications
High Output Drive Capability
Internally Self-Timed Write Pulse Generation
Separate Data Input and Data Output Pins

co

co

4

:l

•

e: .. .....

:;;

44 43 42 41 40
39

AD

38

DB

37

DB

D4

10

38

07

03
02

"
12

35

VSSQ

34

06

01

13

33

05

DO

14

32

NC

A7

15

31

NC

AS

16

30

04

29

03

A9 H

..:c :c

..

18 19 20 21 22 23 24 25 28 27 28
11.1.1

I•

...
~ .:! !iii c;

a

BLOCK DIAGRAM

~

PIN NAMES

DO

AO-A" •.••••.•• Add..... Inputs
W. • . • . . • • • . • . • Write Enable
~ • • . . . . . . . . . . . . Chip Enable
DD-D9 •••••.••••• Data Inputs
QIl-as . • . • • . • . • • Data Outputs
K • . • . . . . . . . . . . • Clock Input
VCC . . . . . . . +5 V Power Supply
VSS • . . • . . . . . • . • • • Ground
VSSQ ..•.• Output Buffer Ground
NC . • . • • . • . • . • No Connection

For proper operation of the devioa VSS
and both VSSQ leads must be connected to ground.
DB

This document contains Information on a product under development. Motorola reserves the right to change or discontinue thia product without notice.

MOTOROLA MEMORY DATA
5-97

II

MCM62963

TRUTH TABLE
E

W

Operation

QO-Q8

Current

L

L

Write

High Z

ICC

L

·H

Read

Dout

ICC

H

X

Not Selected

HlghZ

ISB

NOTE: The values of E and W are valid inputs for the setup and hold times relative to
the K rising adge.

-

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS-VSSQ-O
VI
, RatIng

Symbol

Value

Unit

VCC

-0.6 to +7.0

V

Vin, Vout

-0.6 to VCC+0.5

V

Output Current (per 1/01

lout

±20

mA

Power Diasipetion (TA=25·CI

Po

1.5

W

Tbias

-10 to +86

·C

Power Supply Voltage
Voltage Relativa to VSSIVSSQ for Any
Pin Except VCC

Temperature Under Bias'

II

Operating Temperature

TA

Oto +70

·C

Storage Temperature

Toto

-56 to +125

·C

This device contains circuitry to protect the
inputs against damage due to high ststic
voltages or electric fields; howewr. It is adviaad that normal precautions be taken to
avoid application of any voltage highar then
maximum rated voltages to 'this highimpedance circuit.
This is a synchronous device. All synchronous inputs must meet the specified s8tup
and hold times with stsble logic lavals for
ALL rising edges of clock (KI while the device Is selectad.
This device contains Circuitry that will ensure the output devices are In High Z at
power up. Care should be taken by the user
to ensure that all clocks are at VIL or VIH
during power up to prevent spurious read
cycles from occurring.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exoeadad. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Expoeure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%. TA =0 to 70·C. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (V0Itagas refere need to V SS= V SSQ= OV)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

6.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Peram_r

*VIL (min) = -3.0 V ac (pulse width :s20 ns)

DC CHARACTERISTICS
Param_r

Symbol

Min

Max

Unit

Input Leakege Current (All Inputs. Yin = 0 to VCC)

IlkoUl

-

±1.0

p.A

Outpui Leakege Current (E=VIH. Vout=O to VCC. Outputs must be high-zi

Ilka(O)

AC Supply Current (E=VIL. Alllnputs=VIL or VIH. 10ut=0 mAo Cycle
Time",tKHKH min)
MCM62963-20: tKHKH =20 ns
MCM62963-25: tKHKH =26 ns
MCM62963-30: tKHKH =,30 ns
Standby Current (E=VIH. VIH",3.0 V. VIL:s0.4 V. lout=O mAo Cycle
Time:.: =tKHKH min)

ICCA

ISB

-

±1.0

p.A
mA

-

170
170
160
30

mA

Output Low Voltage (lOL = 12.7 mAl

VOL

-

0.4

V

Output High Volt8ge (lOH = -1.8 mAl

VOH

2.8

-

V

Symbol

Typ

Mex

Unit

Cin

4

6

pF

Cout

5

7

pF

CAPACITANCE (f=l 0 MHz dV=30V TA=26·C Periodically Sampled Rather Than 100% Testedl
Characterlatlc
Input Capacitance
Output Capacitance

'MOTOROLA MEMORY DATA
5-98

MCM62963

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0V ±10%, TA=Oto +70o C,

Unless

Othsrwise Notedl

Output Timing Measurement Reference Level • • • . • . . . • 1.5 V
Output Load • • . • • • . . . . See Figure lA Unless Otherwise Noted

Input Timing Measurement Reference Level . . • . • • . • " 1.5 V
Input Pulse Level. • . . . . • • . . . . . . • . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . • . • . . • . . • . 5 ns

READ CYCLE (See Note I)
Parameter

Symbol

MCMII2!I83-2O

MCM82lI83-2&

Min

Max

Min

Max

Min

Max

-

25

-

30

-

10

-

10

Read Cycle Time

tKHKH

20

Clock Access TIme

tKHOV

-

Output Active from Clock High

tKHOX

3

-

3

-

Clock High to 0 High Z fE=V,H)

tKHOZ

-

10

-

10

Clock Low Pulse Width

tKLKH

5
5
5

-

-

-

-

5
5
5

3

-

3

Clock High Pulse Width

tKHKL

Setup Times for:

E

Hold TImes for:

W
E

A

A

W

tEVKH
tAVKH
twHKH
tKHEX
tKHAX
tKHWX

MCM82IJ8S.3O

-

Unit

Notaa

13

ns
ns

3

2

3

-

ns

4

-

13

ns

4

-

ns
ns

-

5
5
5

-

ns

5

-

3

-

n8

5

-

NOTES:
1. A read is defined by W high and E low for the aetup and hold times.
2. All read cycle timing is referenced from K.
3. Valid data from K high will be the data stored at the address of the last valid read cycle.
4. Transition is measured ±500 mV from S!8edy-stata voltage with load of Figure lB. This perametar is sampled not 100% taeted. At any
given voltage and temperature, tKHOZ max is less then tKHOX min for a given device.
5. This is a synchronous device. All synchronous inputs must meet the apecIfIed aetup and hold times with 818b1a logic levels for ALL rising
edges of clock (K) while the device is selected.

AC TEST LOADS
+5V

+5V

330

330

Q--------.
330

Q -.....- - - -.....

5 pF
IINCWDING
SCOPE AND JIG)

330

85 pF
UNCWDlNG
SCOPE AND JIG)

Figura 18

Figura lA

MOTOROLA MEMORY DATA
5-99

II

MCM62963

READ CYCLE 1 (See Note 1)

K (CLOCK)

E(CH(P ENABLEl

A (ADDRESS)

Vi !WRITE ENABLE)

II

.-.r---

,..-_ _ _ _ _ _ _ _ _
tK_HDZ_1
o IDATA DUn

On-3

0.- 2

tKHOX
HIGH Z - - - -

~--------------~

READ CYCLE 2 (See Note 1)

K (CLDCKl
tKHEX

E(CHIP ENABLE)
tKHAX
A (ADDRESS)

An-1
tKHWX

Vi (WRITE ENABLEl

o (DATA DUTI

0.-3

0.-2

0.-1

NOTE:
1. The outputs 0n-3 and On-2 are derived from two previous read cycles where W=VIH and E=VIL for those cycles.

MOTOROLA MEMORY DATA
5-100

MCM62963

WRITE CYCLE

(Vii Controlled

See Note 1)

Parameter

Symbol

Write Cycle Time
Clock High to Q High Z

~
A

W
0
~
A

Hold Times for:

ilii
0

MCMII29II3-3O

Max

Min

Max

Min

-

25

-

30

-

tKHOZ

Setup TImes for:

MCM62983-2&

Min
211

tKHKH

(ilii = VILI

MCM82983-211

-

10

tEVKH
tAVKH
twLKH
tOVKH

5

-

tKHEX
tKHAX
tKHWX
tKHOX

3

-

10

5

-

3

-

Unit

No_

Max

-

na

2

13

ns

5

-

ns

3
4

3

-

ns

4

-

NOTES:
1. A write is parformed when iN and ~ ara both low for the specified setup and hold times.
2. All write cycle timing is referanosd from K.
3. Transition Is measured ±500 mV from steady·stem voltega with load 01 Figura lB. This parametar Is sampled not 100% 18a18d. At any
given voltage and temparatura, tKHOZ max is leas than tKHOX min for a given devica.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stebJe logic levels for ALL rising
edges 01 clock (Kl while the davies Is selected.

WRITE CYCLE

I + - - - - - IKHKH-----+/
K (CLOCKI

A (ADDRESSI

IV (WRITE ENABLE)

o (DATA IN)
I+---+/-IKHDZ
a (DATA Dun

0,,-2

0,,-1

~

_ _ _ _ _ _ _ _ _ _ _ _ _ __ J) - - - - -

HIGH Z - - - - - -

ORDERING INFORMATION
(Order by Full Part Number)
CM

T..J

Motorola Memory PrefiX _ _ _ _ _

Tr T..------

Part Number _ _ _ _ _ _ _ _ _ _ _ _ _
....1

SPeed (20=20 ns, 25=25 ns, 30=30 ns)

L..---------Package (FN = PLCC)

Full Part Numbers-MCM62963FN2O

MCM62963FN25

MOTOROLA MEMORY DATA
5-101

MCM62963FN3O

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62964
Product Preview

4K X 10 Bit Synchronous Static RAM
with Output Register. and Output Enable

•

The MCM62964 is a 40,960 bit synchronous stadc random access memory organized as
FN PACKAGE
4096 words of 10 bIta, fabricated uaing Motorola's secondlleneradon high-perfonnance
44-LEAD PLCC
silicon-gate CMOS (HCMOS III) technology. The device integrates input regiJters, high
CASEm
speed SRAM, and high-drive capebiHty output registers onto a single monolithic. circuit for
reduced pal1ll coum implementa1lon of cache date RAM, writeable comrol store applications, and other applications that utilize long words.
Synchronous design allows pracisa cycle comrol with the usa of an external clock (K),
while CMOS circuitry reduces the averan power consumption of the imegrated funcdons
PIN ASSIGNMENT
for greater reliability.
The address (AO-A11), data (00-09), and write (W) inputS are an clock
(K) controlled, positive-edge-triggerad, noninverting registars.
85432 1 ~ U ~ ~
The MCM62964 provides output registar oparadon. At the rising edge of
clock (K), the RAM date from the previous clock (K) high cycle is

AD

presantad.

09

•

The output enable (3) provides asynchronous bus control for common
I/O or bank switch applications.
Write operations are imemaHy salf-timed and inidated by the rising edge
of the clock (K) input•. This faature eliminates complex off-chip write pulse
genaration and provides increased flexibility for incoming signals.

NC

08
07

04

10

03

11

Vsso

02

12

08

± 10% Power Supply

01

13

05

• Fast Cycle limes: 2JJ/'JJS/:Jl ns Max
• Fast Clock (K) Access limes: 10/10/13 ns Max
• Address, Data Input, and W Regiatars On-Chip

DO

14

A7

15

31

Ne

A8

18

30

04

29

03

•

Single 5 V

• Output Enable for Asynchronous BUB Control
• Output Regiatars for Fully Pipe/ined Applications
• High Output Drive Capability
• Intarnally Salf-limed Write Pulse Generadon
• Separate Data Input and Data Output Pins

NC

BLOCK DIAGRAM

PIN NAMES

AD-A11

Vce
Vss

VSSO

00-09

00

w
K

08

AO-A 11. . . • • . . . • Addrasa InpulS
W. . . . . . . . . . . . . Write Enable
G .. .. . .. .. . .. OU1PUt Enable
DO-09 • • • • • • • • • • • Data InpulS
00-09 . . . . . . . . . . Data OutpulS
K . • . • • .'. • • • . . • • Clock Input
VCC • • • . •.• • + 5 V Power Supply
VSS ..••.••••.•••. Ground
VSSQ ••..• Output Buffer Ground
NC . • . . . • • . . . • No Connection
For proper operation of the davice VSS
and both VSSQ leads must bs connected to ground.

ROW A5, M. A3. A2, AI. AD. A8
COL
A7. All. AID. A9. A8
IIS8

LSB

This clacumant conIIIino infonnsIion on • product under -.,prnant. Motomlo I8II8IV88 the right to change or diacondnua this product without notice.

MOTOROLA MEMORY DATA
5-102

MCM62964

TRUTH TABLE

W

Operation

00-08

Current

L

Write

HighZ

ICCA

H

Read

Dout

ICCA

NOTE: The value W is a valid input for tha setup and hold times relative to the K rising
edge.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss=Vssa=O VI
Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Vin, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/01

lout

±2O

rnA

Power Dissipation (TA = 25·CI

Po

1.5

W

Tbias

-10to +85

·C

Operating Temperatura

TA

Oto +70

·C

Storage Temperatura

Tstg

-55 to +125

·C

Rating
Power Supply Voltage
Voltage Relative to VsslVssa for Any
Pin Except VCC

Temperature Under Bias

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restrictad to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extanded periods of time could affect device reliability.

This device contains circuitry to protact the
inputs against demage due to high ststic
voltages or electric fields; however. it is advised that nonnal precautions be takan to
avoid application of any voltage higher than
maximum rated voltages. to this highimpedance circuit.
This is a synchronous device. All synchronous inputs must meat tha spacifled setup
and hold times with stable logic JavaIs for
All rising edges of clock (KI while tha de-

vice is selected.
This davica contains circuitry that will enaure the output devices are In High Z at
power up. Care should be takan by tha usar
to ensure that all clocks are at VIL or VIH
during power up to prevent spurious reed
cycles from occurring.
This CMOS memory circuit has bean designed to meat !he dc and ac spaclfications
shown in the tables. after. !hennal equilibrium has bean established. Tha circuit is in
a test socket or mounted on a printed circuit
board and transvares air flow of at Jeast 500
linear feat per mlnuts is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
IVCC=5.0 V ± 10%. TA=O to 70°C. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss=Vssa=O VI
Symbol

Min

Typ

Max

Unit

Supply Voltage 10perating Voltage Rangel

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

.-

VCC+0.3

V

Input low Voltage

VIL

-0.5*

-

0.8

V

Parameter

*VIL (mini = -3.0 V ac (pulse width ,,;20 nsl

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Yin = 0 to VCCI

Parameter

IlkalJl

-

±1.0

p.A

Output Leakage Current (G=VIH. Vout=O to VCC. Outputs must be high-ZI

IlklllOL

-

±1.0

AC Supply Current IG=VIL, Alllnputs=VIL orVIH.lout=O mAo Cycle
Tima;,:tKHKH mini
MCM62964-2O: tKHKH =20 ns
MCM62964-25: tKHKH =25 ns
MCM62964-30: tKHKH = 30 ns

ICCA

-

p.A
mA

170
170
150

Output Low Voltage (JOL = 12.7 mAl

VOL

-

0.4

V

Output High Voltage (JOH = -1.8 mAl

VOH

2.8

-

V

CAPACITANCE If=1.0 MHz, dV=3.0 V, TA=25·C, Periodically Sampled Rathar Than 100% Testedl
Symbol

Typ

Mex

Unit

Input Capecitance

Cin

4

6

pF

Output Capacitance

Cout

5

7

pF

ChareClaristlc

MOTOROLA MEMORY DATA
5-103

II

MCM62964

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0V ±10%, TA"'Oto +70o C, Una-Oth8IWise Noted)
Output Timing Measurament Referance Level . • . • • • • . . 1.5 V
Output Load .•••.••••. See Figura lA Unless Otherwise Noted

Input TIming Measurement Reference L.sveI • • • . • • . • • . 1.5 V
Input Pulse Levels • • •• • • . • • . • • • • • • • • • • . • .0 to 3.0 V
Input Rise/Fall TIme ••.••.••• '.' .•••.•••.•••.• 5 lIS

READ/WRITE CYCLE
Symbol

Parameter

MCMIIZ9II4.a

Min

Max

Min

Read Cycle Time

tKHKH

20

-

25

Write Cycle TIme

tKHKH

20

-

25

Clock High Access TIme

tKHQV

"G" ~ to Output Valid

lGLQV
tKHOX

Output Active from Clock High
Output Active from G Low

II

MCM62984-211

Clock Low Pulse Width

lGLOX
tKLKH

Clock High Pulse Width

tKHKL

Setup TImes for:

A
0

W
Hold TImes for:

A
0

W
Clock High to Output High Z

IW = VIU

G High to Output High Z

Min

-

30
30

Max

-

Unit

Not..

lIS

1,3

ns

-

10

-

10

-

13

n8

2,3
3,4

-

10

-

10

-

13

ns

3

0
0
5
5

-

5

3

tKHOZ
lGHOZ

5

-

-

3

-

0

10

0

13

lIS

3,6

0

10

0

13

n8

3,6,7

0
0
5
5

-

-

tAVKH
tOVKH
twvKH
tKHAX
tKHOX
tKHWX

MCM828II4-3O

Max

-

0
0
5
5

-

5

-

-

3

0

10

0

10

lIS

ns
n8
lIS

n8

1,2,6

n.

1,2,6

NOTES:
1. A read is defined by W high for the specifl8d setup and hold times.
2. A write Is .defined by W low for the specified setup and hold times.
3. All read and write Cycle timing is referenced from K or from "G".
4. Valid data from K high will be the data atored at the address of the last valid reed cycIs.
5. This is a svnchronou8 device. All svnchronous Inputs must meat the specifJ8d setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is esIected.
6. Translticn is measured ± 600 mV from staady-ststa voltage with load of Figura 1B. This parameter is sempled and not 100% taated. At any
given voltage and temperatura, tKHOZ max is less than tKHOX min and tGHOZ max is less than lGLOX min for a given device.
7. G becomes a don't cera signal for succesalve writes after the first write cycIs.

AC TEST LOADS

+5V

+5V

330

330
Q-~-----.

Q -....- - - - - .

330

85 pi'
ONCLUDING

330

=r

5p1'

ONCWIIING
SCOPE AND JIG)

SCOPE AND JIG)

Flgure1A

Flgur.1B

MOTOROLA MEMORY DATA
5-104

MCM62964

READ CYCLE

K (CLOCK)

GIOUTPUT ENABLE)

A (ADDRESS)

ii !WRITE ENABLE)

n !DATA OUT)

0n- 3

::-z r-u_
~__--'

-----on-_-z---ts-HOZ- " }
WRITE CYCLE

ICOMMOI 1/8 MODEl

ISEPAllATE I/O MODEl
-tKHKH---+l
K (CLOCK)

G(OUTPlJT ENABLE)

A (ADDRESS)

VI (WR(TE ENABLE)

D (DATA IN)

~rtGHOZ

o (DATA Dun

~)------

0.-1

HIGH-Z - - - - - - -

ORDERING INFORMATION
(Order by Full Part Number)

T-'CM

Motorola Memory PrefiX _ _ _ _ _

T

rfL.------Speed (20=20 ns, 25=25 ns, 30=30 ns)

Part Number----------------'

L.---------IPackage (FN=PLCC)

Full Part Numbers-MCM62964FN20

MCM62964FN25

MOTOROLA MEMORY DATA
£),105

MCM62964FN30

II

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM62965
Product Preview

4K X 10 Bit Synchronous Static
with Transparent Outputs and Output Enable

RAM

The MCM62966 is a 40,960 bit synchronous stetic random access memory organized as
FN PACKAGE
44-LEAD PLCC
silicon-gate CMOS (HCMOS 1111 technology. The device integrates input registers, high
CASEm
speed SRAM, and high-drive capability output latching onto a single monolithic circuit for
reduced parts count implementation of cache date RAM, writeable control store applications, and other applications that utilize long words.
Synchronous design allows precise cycla control with the use of an axternal clock (K),
while CMOS circuitry reduces the overall power consumption of the integrated functions
PIN ASSIGNMENT
for greater reliability.
The address (AO-All), date (00-09), and write (iN) inpute are all clock
(K) controlled, positive-edge-trigge~, noninverting registers.
The MCM62966 provides transparent output operation when clock (K) is
4
1 44 43 42 41 40
low for access of RAM date within the same cycle (output date is latched
05
3B
when clock (K) is high).
NC
36
The output enable (G) provides asynchronous bus control for common
37
NC
1/0 or bank switch applications.
Write operations are internally self-timed and initiated by the rising adge
D4 10
36
of the clock (K) input. This feature eliminates complex off-chip write pulse
03 11
35
generation and provides increased flexibility for incoming signals.
02 12
34
• Single 5 V ± 10% Power Supply
01 13
33
• Fast Cycle Times: 25/30/35 ns Max
DO 14
• Fast Clock (K) Access Times: 10113/15 ns Max
32
• Address, Data Input, and iN Registers On-Chip
A7 15
31
• Transparent Output Latch for Access Within the Same Cycle
A8 18
3D
• Output Enable for Asynchronous Bus Control
AB 17
29
• High Output Drive Capability
18 19 20 21 22 23 24 25 26 27 28
• Internally Self-Timed Write Pulse Generation
• Separate Data Input and Date Output Pins

4096 words of 10 bite, fabricated using Motorola's second-generation high-perfonnance

II

•

PAD
P09

pou
P07
pVSSO

P06
P05

PNC

PNC
p04
P03

BLOCK DIAGRAM
PIN NAMES

VCC

Vss

Ao-A11. . • . • • • • • Addrsss Inputs

'iii. . . . . . . . . . . . . Write Enable
G . . . . . . . . . . .. Output Enable

VSSQ

DO-DB

no

i

K

Q9

DO-D9 . . . . . . . . • . . Data Inputs
00-Q9 . . . . . : • . . . Data Outputs
K . . . • . . . . . . . . . . Clock Input
VCC • • • • • • • + 5 V Power Supply
VSS •••.••••••••.• Ground
VSSQ •...• Output Buffer Ground
NC . . • . • . • . • . • No Connection
For proper operation of the device VSS
and both VSSQ leeds must be connected to ground.

ROW A5. A4. A3. A2. AI. AD. A6
COL
A7. Al1. AID. AB. A6
MSB
LS8

This document contains Information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
&-106

MCM62965

This device contains Circuitry to protect the
inputs against demage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-

TRUTH TABLE
W

Operation

QO-Q9

L

Write

High Z

ICCA

H

Read

Dout

ICCA

Currant

NOTE: The value W is a valid input for the setup and hold times relative to the K rising
edge.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss-Vssa=O
V)
Rating

Symbol

Value

Unit

Vce

-0.5 to +7.0

V

Vi", Vout

-0.5 to VCC+0.5

V

Output Current (per 1/0)

lout

±2O

mA

Power Dissipation (TA = 25DC)

Po

1.5

W

Temperature Under Bias

Tbias

-10to +85

DC

Operating Temperature

TA

Storage Temperature

T~

Power Supply Voltege
Voltage Relative to VsslVssa for Anv
Pin Except VCC

o to

+.70

-55 to + 125

DC
DC

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periodS of time could affect device reliability.

impedance circuit.
This is a synchronous device. All synchronous inputs must meat the specified setup
and hold times with stable logic levels for
ALL rising edges of clock (K) while the device is selected.
This device contains circuitry that will ensure the output devices are in High Z at
power up. Care should be taken by the user
to ensure that all clocks are at VIL or VIH
during power up to prevent spurious read
cycles from occurring.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium has been sstablished. l1Ie circuit is in
a test socket or mounted on a printed circuit
board and transvarse air flow of at least 500

linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA=O to 7Oo e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss=Vssa=O VI
Symbol

Min

Typ

MIIX

Unit

Supply Voltage (Opereting Voltage Rangel

VCC

4.5

5.0

5.6

V

Input High Voltage

VIH

2.2

-

VCC+0:3

V

Input Low Voltage

VIL

-0.6*

-

0.8

V

Parameter

*VIL (min) = -3.0 V ac (pulse width ,,20 ns).

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Parameter

IlkaUl

±1.0

,.A

Output Leakage Current (G=V,H, Vout=O to VCC, Outputs must be high-Z)

Ilka(OI

-

±1.0

,.A
mA

AC Supply Current (G=VIL, Alllnputs=VIL or V'H, lout =0 mA, Cycle
MCMfI2966.25: tKHKH = 25 ns
Tlme"tKHKH min)
MCMfl2966.3O: IKHKH = 30 ns
MCMfI2966.35: tKHKH = 36 ns

ICCA

-

170
170
160

Output Low Voltage (/OL = 12.7 mAl

VOL

-

0.4

V

Output High Voltage (/OH = -1.8 mAl

VOH

2.8

-

V

Symbol

Typ

MIIX

Unit

Cin

4

6

pF

Cout

5

7

pF

CAPACITANCE (f = 1.0 MHz, dV =3.0 V, TA = 25°C, Periodically Sampled Rether Than 100% Tested)
Characteristic
Input Capecitance
Output Capecitance

MOTOROLA MEMORY DATA

5-107

II

MCM62965

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA=Oto +70o e, Unless Otherwise Notedl
Output Timing Measuramant Referance Level . • . . . • • • . 1.5 V
Output Load • . . . . . • . • . See Figura lA Unless Otherwise Noted

Input TIming Measurement ReferenCe Level • . • . • • . • •• 1.5 V
Input Pulse I..a\teIs • • • . • . • • • • . • • . • • • • • • . • .0 to 3.0 V
Input Rise/Fail Tima . • . • . • • • • . • • . • • • • • . . • • • • . 5 ns

READ/WRITE CYCLE
Parametar

II

Symbol

MCM628IIIi-2Ii

MCM82886-30

MCMII2III6-3Ii

Min

Max

Min

Min

Max

-

30

35

-

ns

1.3

-

30

35

-

ns

Read Cycle Tima

tKHKH

25

Write Cycle Tlma

tKHKH

25

Clock High Access Time

tKHQV

-

25

Clock Low to Output Valid

tKLQV

-

10

~ Low to Output Valid

lGLQV

-

-

10

Output Active from Clock Low

tKLOX

0

-

-

Output Active from ~ Low

lGLOX

Clock Low Pulse Width

tKLKH

0
5

-

Clock High Pulse Width

tKHKL

Setup Times for:

A

0

W

tAVKH
tOVKH
twHKH

5
6

Max

-

Notes

30

-

35

ns

2.3
3.4.5

13

-

15

ns

3,4,5

13

-

15

ns
ns
ns
ns

3

0

-

-

0
6
5
5

-

-

Unit

-

-

0
0
5
5
6

-

ns

-

ns

1,2,6

ns

1,2,8

tKHAX
tKHOX
tKHWX

3

-

3

-

3

-

Clock Low to Output High Z (iii = VIL)

lKLOZ

0

10

0

13

0

16

ns

6,7

G High to Output High Z

lGHOZ

0

10

0

13

0

15

ns

3.7,8

Hold Times for:

A

0

iii

NOTES:
1. A raad is defined by iii high for the speclfl8d setup and hold timas.
2. A write is defined by iii low for the specified setup and hold times.
3. All raad and write cycle timing is raferenced from K or from G.
4. Access time is controlled by tKLQV if the clock high pulse width ~(tKHQV-tKLQV); otherwise it is controlled by tKHQV'
5. K must be low for the outputs to transition.
'
6. This Is a synchronous device. All synchronous inputs must mset the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
7. Transition is measurad ±500 mV from steadv-state voltage with load of Figura lB. This parameter is sampled and not 100% tested. At any
given voltage and,temperatura. tKHOZ max is less than lKHOX min and tGHOZ max is less than lGLOX min for a given device.
8. ~ becomes a don't cara signal for successive writes after the first write cycle.

AC TEST LOADS

+5V

+5V

330

330

Q------..

Q -......- - - -. .

85 pF
(INCLUDING
SCOPE AND JIG)

330

5 pF

330

OIICWIJING
SCOPE AND JIG)

Figure1A

Figura 18

MOTOROLA MEMORY DATA
6-108

MCM62965

READ CYCLE

K (CLOCKI

ii (OUTPUT ENABLEI

A !ADDRESSI

iii !WRITE ENABLEI

II

n (DATA Dun ----+-==,.",.,,=-=---(

WRITE CYCLE
\+-----IKHKH ------1"1
K (CLOCKI

ii (OUTPUT ENABLEI

A (ADDRESSI

IV (WRITE ENABLEI

D (DATA INI

o (DATA OUT!
ORDERING INFORMATION
IOrder by Full Part Numberl
CM
Motorola Memory prefiX _ _ _ _ _
T...J

Tr

Part N u m b e r - - - - - - - - - - - - - - - '

TL_ _ _ _ _ _ Speed (25=25 ns, 30=30 ns, 35=35 ns)

L---------IPackage (FN= PLCC)

Full Part Numbers-MCM62966FN25

MCM62966FN3O

MOTOROLA MEMORY DATA
5-109

MCM62966FN35

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62973

Product Preview
4K X 12 Bit Synchronous Static RAM
with Output Registers
The MCM62973 is a 49,152 bit synchronous static random access memory organized as
4096 words of 12 bits, fabrlcatecj using Motorola's second-generation high-performance
silicon-gats CMOS (HCMOS III) technology. The device integrates input registers, high
speed SRAM, and high-drive capebility output registers onto a single monolithic circuit for
raduced parts count implementation of cache data RAM, writeable control stora applications, and other applications that utilize long words.
Synchronous design allows pracise cycle control with the use of an e~rnal clock (K),
while CMOS circuitry reduces the overall power consumption of the intelirated functions
for graater reliability.
The addrase (AO-A11), data (00-011), write (W), and chip enable (E)
inputs ara all clock (K) controlled, positive-edge-triggerad, noninverting
:!l
registers.
The chip enable fE) input is a synchronous input clock thet places the
device in a low power mode when high at the rising edge of the clock (K).
071 7
The MCM62973 provides output register operation. At the rising edge of
081 8
clock (K), the RAM data from the pravious clock (K) high cycle is
osl 9
prasented.
Write operations ara internally self-timed and initiated by the rising edge
041 10
of the clock (K) input. This featura eliminates complex off-chip write pulse
031 11
generation and provides incraesed flexibility for incoming signals.
021 12
• Single 5 V ± 10% Power Supply
13
Oil
• Fast Cycle Times: 20/25/00 ns Max
Dol 14
• Fast Clock (K) Access Times: 10110/13 ns Max
Addrase, Data Input, E, and W Registers On-Chip
A71 15
• Output Registers for Fully Pipalined Applications
A81 18
• High Output Drive Capebility
A91 17
• Internally Self-Timed Write Pulse Generation
18 19
Separate Data Input and Data Output Pins

...
'"

II

FN PACKAGE
44-LEAD PLCC
CASEm

PIN ASSIGNMENT
co

Ci

'"

4 .3

...c ...c

•

..

~:

:l

~

:c

44 43 42 41 40

•

•

co

:c :c

BLOCK DIAGRAM

39

AD

38

011

37

010

36

Q9

35

VSSQ

34

Q9

33

07

32

Q9

31

OS

30

Q4

29 ~Q3
20 21 22 23 24 25 26 27 28

... ,.

1~8 ;;

a

j

PIN NAMES

00

AG-A 11. • • • • • • • • Addll108 Inputs
W. . . . . . . . . . . . . Write Enable
~ • • • • • • • • • • • • • • Chip Enable
DO-Oil • . . • . . . • • . DaIs Inputs
OO-Ql1 •.•••.••• Oats Outputs
K • • • • • • • • • • • '.' • Clock Input
VCC . • . • • . . +5 V Power Supply
liss . . . . . . . . . . . . .. Grcund
VSSQ •.•.. Output Buffer Ground

For proper operation oftha device VSS
and both VSSQ leads must be
connected to grcund.

011

This document contains infonnation on a product under devetopment. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-110

MCM62973

TRUTH TABLE
E

W

Operation

00-011

Current

L

L

Write

High Z

ICC

Dout
High Z

ISB

L

H

Read

H

X

Not Selected

-

ICC

NOTE: The values of E and Ware valid inputs for the satup and hold times relativa to
the K rising edge.
ABSOLUTE MAXIMUM RATINGS (Voltage. referenced to VSS=VSSO=O VI
Symbol

Velue

Unit

VCC

-0.5 to +7.0

V

Vin, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/01

lout

±2O

mA

Power Dissipation (TA = 26°Cl

Po

1.5

W

Temperature Under Bias

Tbias

-10to +86

°C

Operating Temperature

TA

Retlng
Power Supply Voltage
Voltage Relative to VSSIVSSO for Any
Pin Except VCC

Storage Temperature

Tstg

oto

+70

°C

-55 to +126

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Expoaure to higher than recommended voltages for
extended periods of time could affect device reliability.

This device contains circuitry to protect the
inputs ageinst damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum reted voltages to this highimpedance circuit.
This ia a synchronous device. All synchronous inputs must meet the specified setup
and hold times with stable logic levals for
ALL rising edges of the clock (Kl whiia the
device is salected.
This device contains circuitry that will ensure the output devices are in High Z at
power up. care should be taken by the ussr
to ensure that all clocks are at VIL or VIH
during power up to prevant spurious read
cycles from occurring.
This CMOS memory circuit has bean designed to meet the de and ac specifications
shown in the tables, altar thermal equHibrium has bean established. The circuit is in
a ta8I socket or mounted on a printed circuit
board and transvares air flow of at least 500
linear feet per minuta is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 70°C, Unless Otherwise Notedl
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss-Vssa=O
VI
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Rangel

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Parameter

*VIL (minl- -3.0 V ac (pul.. width ",20 ns)
DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin=O to VCCI

Parameter

IlkoUl

±1.0

Output Leakage Current (~=VIH' Vout=O to VCC, Outputs must be in High Zl

Ilko(OI

-

"A
"A

-

170
170
150

AC Supply Current (~=VIL' Alllnputs=VIL or VIH, 10ut=0 mA, Cycle
Time:.:tKHKH mini
MCM62973-20: tKHKH =20 ns
MCM62973-26: tKHKH =26 ns
MCM62973-30: tKHKH =30 ns
Standby Current (E=VIH, VIH:.:3.0 V, VIL",0.4 V, 10ut=0 mA, Cycia
Time:.: =tKHKH mini

ICCA

ISB

±1.0

mA

-

30

mA

Output Low Voltage (lOL = 12.7 mAl

VOL

-

0.4

V

Output High Voltage (lOH = -1.8 mAl

VOH

2.8

-

V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA =26°C, Periodically Sampled Rather Than 100% Tested)
Characteristic

Input Capacitance
Output Capacitance

MOTOROLA MEMORY DATA
5-111

Symbol

Typ

Max

Unit

Cin

4

6

pF

Cout

5

7

pF

II

MCM62973

AC OPERATING CONDITIONS AND C.HARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to +70·C, Unless Otherwise Noted}
Input Timing Measurement Reference Level ••• . . . . • . . 1.5 V
Input Pulse Levels • . . • . . • . . • • • • • • • • • • • • • .0 to 3.0 V
Input Rise/Fall Time •....•......•.••••••••.•• 5 no

Output Timing Meesurement Reference Level . . . . . . . • • 1.5 V
Output Load •••••••..• See FlIIure lA Unless Otherwise Noted

READ CYCLE (See Note I}
Symbol

Parameter

Reed Cycle Ti.me

tKHKH

Clock Access Time

tKHQV

Output Active from Clock High

tKHOX

Clock High to Q High Z fE=VIH)

tKHOZ

Clock Low Pulsa Width

tKLKH

Clock High Pulse Width

II

tKHKL

Setup Times for:

"E

Hold Times for:

W
E

A

A

W

tEVKH
tAVKH
twHKH
tKHEX
tKHAX
tKHWX

MCMII2lI73-2O

MCMII2973-2Ii

MCM82973-30

Min

Max

Min

Max

Min

-

25

30

-

ns

2

-

-

10

10

-

13

ns

3
4

20

-

Unit

Notes

3

-

3

-

-

10

-

10

-

13

5
5
5

-

5
5
5

-

-

5
5
5

-

-

no
no
no
no

-

ns

5

3

-

3

-

3

-

ns

5

3

-

Max

4

NOTES:
1. A reed is defined by W high and E low for the setup and hold times.
2. All reed cycle timing is referenced from K.
3. Valid data from K high will ba the data etored at the address of the last valid reed cycle.
4. Transition Is measured ±500 mV from steady-atste voltage with load of Figure lB. This psramatsr is sampled not 100% teatsd. At any
given voltage and temparetura, tKHOZ max is less than tKHOX min for a given device.
5. This is a synchronous device. All synchronous Inputs must meat the specified setup and hold times with atsble logic levels for ALL rising
edges of clock (K) while the device Is eslacted.

AC TEST LOADS

+5V

+5V

330

330

D-.-----...
330

D-+------+
85 pF
(INCWDING
SCOPE AND JIG}

330

5pf

(lNCWDING
SCOPE AND JIG)

Flgur.1A

Flgur.18

MOTOROLA MEMORY DATA
5-112

MCM62973

READ CYCLE 1 (See Note 1)

K ICLOCK)

E !CHIP ENABLE)

A !ADDRESS)

IV !WRITE ENABLE)

~_________________tK_~
__~
Q

IOATA OUT)

n,,-3

n,,-2

_tKH~ _ g t
KHOV

__

n"

.J---HIGHZ

READ CYCLE 2 (See Note 1)

K ICLOCK)
'KHEX

EICHIP ENABLE)
tKHAX
A IAODRESS)
'KHWX

IV IWRITE ENABLE)

Q !DATA

OUT)

n,,-3

n,,-2

n,,-1

NOTE:
1. The outputs 0,,-3 and 0,,-2 are derived from two previous reed cycles where iiii=VIH and E=VIL for those cycles.

MOTOROLA MEMORY DATA
5-113

II

MCM62973

WRITE CYCLE

WJ Controlled, See Note 1)
Parameter

Symbol

Write Cycle Time

tKHKH

Clock High to Output High Z,(W=VIL)

tKHOZ

l

Setup Tlmos for:

A
W

0

l'

Hold Timos for:

A
W

0

MCMII29J3.2O
'Min

Max

20

-

-

MCM62lI73-2&
. Min

MCM82873-30

Unit

Notas

Max

Min

Max

2Ii

-

30

-

ns

2

10

-

10

-

13

ns

tEVKH
tAVKH
tw.LKH
tDVKH

5

-

5

-

5

-

ns

3
4

tKHEX
tKHAX
tKHWX
tKHDX

3

-

3

-

3

-

ns

4

NOTES:
1. A write is performed when W and E are both low tor the specified estup and hold timos.
2. All write cycle timlng I. referenced from K.
Transition is measured ±500 mV from ateady-state voltage with load of Figure lB. This parameter is ssmpled not 100% tested. At any
given voltage and temperature, tKHOZ max is lees than tKHOX min for a given device.
4. This is a synchronous device. All synchronous inputs must meet the specified eetup and hold limos with stable logic levels for ALL rising
edges of clock (K) while the device is selected.

3:

II

WRITE CYCLE
t+-----IKHKH-----~

K(CLOCK)

E(CHIP ENABLE)

A (AOORESS)

W(WIIITE ENABLE)

o IllATA IN)

Q IllATA

oun

0,.-2

---------Dn----l----------~.-~-~------H~HZ----------

Motorola Memory Prefix _ _ _ _ _T_M
....CM
Part Number

r-

T'--_T_______

L

Full Part Numbers-MCM62973FN20

Package (FN = PLCCI

MCM62973FN25

MOTOROLA MEMORY DATA
5-114

Speed (20=20 ns, 25=25 ns, 30=30 nsl

MCM62973FN30

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62974

Product Preview
4K X 12 Bit Synchronous Static RAM
with Output Registers and Output Enable
The MCM62974 is a 49,152 bit synchronous static random access memory organized as
FN PACKAGE
4096 words of 12 bits, fabricated using Motorola's sacond-generation high-performance
44-LEAD PLCC
silicon-gate CMOS (HCMOS 1111 technology. The davies integrates input registers, high
CASE 717
speed SRAM, and high-drive capability output registers onto a single monolithic circuit for
reduced parts count implementation of cache date RAM, writeable control store applications, and othar applications that utilize long words.
Synchronous design allows precisa cycle control with the usa of an extemal clock (KI,
while CMOS circuitry reduces the overall power consumption of the integrated functions
PIN ASSIGNMENT
for greater reliability.
The address (AO-A11), date ~DO-Dl1I, and write (WI inputs are all clock
(KI controlled, positiv&-edge-triggered, noninverting registers.
Tha MCM62974 provides output register operation. At the rising edge of
4
1 44 43 42 41 40
clock (KI, the RAM date from the previous clock (KI high cycle is
D7
38
presanted.
DS
38
The output enable «(31 provides asynchronous bus control for common
D5
37
1/0 or blink switch applications.
D4 10
3S
Write operations are intemally self-timed and initiated by tha rising edge
of the clock (KI input. This feature eliminates complex off-chip write pulse
03 11
35
generation and provides increased flexibility for incoming signals.
02 12
34
• Single 5 V ± 10% Power Supply
01 13
33
• Fast Cycle TImes: 20/25/'3fJ ns Max
DO
14
32
• Fast Clock (K) Access TImes: 10110113 ns Max
• Address, Date Input, and W Registers On-Chip
A7 15
31
• Output Enable for Asynchronous Bus Control
A8 18
30
• Output Registers for Fully Pipelined Applications
A9 17
29
• High Output Drive Capability
18 19 20 21 22 23 24 25 2S 27 28
• Internally Self-TImed Write Pulse Generation
• Separate Data Input and Oats Output Pins

•

BLOCK DIAGRAM

AD
011
010
09
VSSo
DB

07
OS

05
04
Q3

PIN NAMES

Vee
Vss

VsSQ

DO

AO-A11. . • • • • • . • Address Inputs
W. . . . . . . . . . . . . Write. Enable
G . . . . . . . . . . . . Output Enable
DO-011 . . • . . • • • • • Data Inputs
oo-Qll . . . . . . . . . Data Outputs
K • . • • . . • . • • • • • . Clock Input

VCC . . . . . . . +5 V Power Supply
VSS .......••.•••. Ground
VSSQ . . . . . Output Buffer Ground
For propsr opsration of the device VSS

011

and both VSSQ leads must be connectad to ground.

ROW A5, A4, A3, A2. A1, AD, AS
COL
A7, All, AlD. A9, A8
MS8
LS8

This document contains information on a product under development. Motorola

I'8B8MtI

the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-115

II

MCM62974

TRUTH TABLE
W

Operation

QO-Q8

Current

L

Write

HighZ

ICCA

Read

Dout

ICCA

H
NOTE: Thp value
edge.

WIs a valid input for the setup and hold times relatlva to the K rising

ABSOLUTE MAXIMUM RATINGS IVoitages referenced to Vss=Vssa=O V)
Rating

Symbol

Power Supply Voltage
Voltage Relstlva to VssIVssa for Any
Pin Except VCC
Output Current lper I/O)
Power Diaaipetion ITA = 25·C)
Temperature Under BiaI!

•

Value

Unit

VCC

-0.5 to +7.0

V

Yin. Vout

-0.5toVCC+0.5

V

lout

±20

rnA

Po

1.5

W

Tbias

-10to+B5

·C

Operating Temperature

TA

Oto +70

·C

Storege Temperature

Tstg

-55 to +125

·C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functionsl operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static
voltages or eiectric flalda; howavar. It Is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum ratsd voltages to this highimpedance circuit.
This is a synchronous device. All synchron·
ous inputs must meet tha specified setup
and hold times with stable logic lavals for
ALL rising edges of clock IK) while the d....
vice is salected.
This device contains circuitry that 'will en·
sure the output devioes ere in High Z at
power up. Care should be tskan by tha usar
to ansure that all clocks are at VIL or VIH
during power up to pravani spurious read
eycles from occurring.
This CMOS memory circuit has been d....
signed to meet the dc and ac specifications
shown in the tables. alter tharmal equilibrium has been established. Tha circuit Is in
a test socket'or mounted on a printed circuit
board and tranm. . air flow of at Iaaat 500
linear faa! per mlnuta Is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%. TA=O to 700e. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS IVoltages raferanced to vss=vssa=o V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Param_r

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+ 0•3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Symbol

Min

Max

Unit

±1.0

yA

*VIL Imln) = -3.0 V ac Ipulsa width ,.;20 ns)

DC CHARACTERISTICS
Param_r
Input Leakage Current (All Inputs. Yin = 0 to VCC)

IIkaUl

Output Leakage Current I~=VIH. Vout=O to VCC. Outputs must be high-Z)

IlkalO)

AC Supply Current I~ = VIL. All Inputs = VIL or VIH. lout = 0 rnA. Cycle
Timn:tKHKH min)
MCM62974-20: tKHKH = 20 ns
MCM62974-25: tKHKH =25 ns
MCM62974-30: tKHKH = 30 ns

ICCA

-

±1.0

yA
rnA

-

-

170
170
150

Output Low Voitaga 1I0L,= 12.7 mAl

VOL

-

0.4

V

Output High Voltage 1I0H = -1.8 rnA)

VOH

2.8

-

V

Symbol

Typ

Max

Unit

Cin

4

6

pF

Cout

5

7

pF

CAPACITANCE If=I.0 MHz. dV=3.0 V. TA=25·C. Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capecltance
Output Capecitanca

MOTOROLA MEMORY DATA
5-116

MCM62974

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V

± 10%, TA=O to

+70o C, Unless Otherwise Noted)
Output Timing Measurement Reference level . . . . . . . . . 1.5 V
Output load. . • . . . . • . • Sea Figure lA Unless Otherwise Noted

Input Timing Measurement Reference Leval • • • . . • • . .• 1.5 V
Input Pulaa Levels . . . • . . . . . . . . . . . . . . . . . . .0 to 3.0 V
Input Rise/Fall Time . • • . . . . . . . . . . . . . . • • . . . . . . 5 no

READ/WRITE CYCLE
Symbol

Parameter

MCM621174-20

MCM621174-21i

MCM621174-30

Min

Max

Min

Max

Min

Max

30

-

ns

1,3

30

-

ns

Unh

Notes

Read Cycle Time

tKHKH

20

tKHKH

20

-

25

Write Cycle Time

25

-

-

10

10

-

13

ns

10

-

2,3
3,4

10

-

13

ns

3

-

ns'

Clock High Access Time

tKHOV

"G low to Output Valid

IGLOV

Output Active from Clock High

tKHOX

Output Active from

"G Low

tGLOX

Clock Low Pulse Wtdth

tKLKH

Clock High Pulaa Width

tKHKL

Setup Times for:

A
D

IN

tAVKH
tDVKH
twvKH

0
0
5
5
5

-

0
0

-

-

5
5
5

-

-

3

-

0
0
5

-

6
5

-

ns

1,2,5

3

-

ns

1,2,5

ns
ns

no

tKHAX
tKHDX
tKHWX

3

Clock High to Output High Z IW = VIL)

tKHOZ

0

10

0

10

0

13

ns

3,6

"G High to Output High Z

IGHOZ

0

10

0

10

0

13

ns

3,6,7

Hold Times for:

A
D

W

NOTES:
1. A read is defined by IN high for the specified setup and hold times.
2. A write is defined by IN low for the specifl8d setup and hold times.
3. All read and write cycle timing is referenced from K or from "G.
4. Valid date from K high will be the data stored at the address of the last valid read cycle.
5. This is a synchronous device. All synchronous inputs must meat the specified setup and hold times with stable logic levels for ALL rising
edges of clock IK) while the device i. aelectad.
6. Transition is measured ±500 mV from staady-state voltage with load of Figure lB. This parameter .samplad and not 100% tasted. At any
given voltage and temperature, tKHOZ max i. less than tKHOX min and IGHOZ max is lass than tGLOX min for a given davioa.
7. "G becomes a don't care signal for sucosssive writes after the first write cycle.

AC TEST LOADS

+5V

+5V

330

330
Q-~----~

Q -....- - - -.....

330

85 pf
IINCWDING

5pf
ONCLUDING

330

SCOPE AND JIG)

SCOPE AND JIG)

Figure 1A

Figure 18

MOTOROLA MEMORY DATA
!>-117

II

MCM62974

READ CYCLE

KICLOCK)

ii IDUTPUT ENABLE)

A !ADDRESS)

IV !WRITE ENABLE)

II

I&HOZ y-1GLOX
o !DATA Dun

1In-3

HIGH·Z

On-2

~

lin

WRITE CYCLE
(SI:PAllATE 1/11 MODE)

(CDMMOI 1/11 MODEJ

KICLOCKI

ii IOUTPUT ENABLEI

A IADDRESSI

iii IWRITE ENABLE)

D IDATA INI
9=tGHn2

a IDATA Dun

On- 2

°n-l

HIGH.Z

ORDERING INFORMATION
(Order by Full Part Number)

T-'CM

Motorola Memory PrefiX _ _ _ _ _
Part Number

TlL._T_______
-

-

Full Part Numbers-MCM62974FN20

MCM62974FN25

MOTOROLA MEMORY DATA
5-118

speed (20=20 ns, 25=25 ns, 30=30 n81
Package (FN = PLCCI
MCM62974FN30

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62975

Product Preview

4K X 12 Bit Synchronous Static RAM
with Transparent Outputs and Output Enable
The MCM62975 is a 49,152 bit synchronous static random access memory organized as
4096 words of 12 bits, fabricated using Motorola's second-generation high-performance
Silicon-gate CMOS (HCMOS 1111 technology. The device integrates input registers, high
speed SRAM, and high-drive cepability output latching onto a single monolithic circuit for
reduced parts count implementation of ceche data RAM, writesble control store applications, and other applications that utilize long words.
Synchronous dasign allows precise cycle control with the use of an extemal clock (K),
while CMOS circuitry reducas the OV8J811 power consumption of the integrated functions
for greater reliability.
The address (AD-All), data (00-011), and write (W) inputa are all clock
(K) controlled, positive-edga-triggared, non inverting registers.
The MCM62975 providas transparent output oparation when clock (K) is
8 5
low for access of RAM data within the same cycle (output data is latched
D71 7
when clock (K) is high).
The output eneble (3) provides asynchronous bus control for common
D81 8
1/0 or bank switch applications.
D61 I
Write oparations are internally self-timed and initiated by the rising edge
041 10
of the clock (K) input. This feature eliminates complex off-chip write pulse
ganeration and provides increased flexibility for incoming signals.
031 11
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Cycle Times: 25/3tJ/35 ns Max
Fast Clock (K) Access Times: 10113/15 ns Max
Address, Data Input, and W Registers On-Chip
Transparent Output Latch for Accass Within the Same Cycle
Output Enable for Asynchronous Bus Control
High Output Drive Capability
Intemally Self-Timed Write Pulse Generation
Separate Data Input and Data Output Pins

FN PACKAGE
....LEADPLCC
CASET17

PIN ASSIGNMENT

4

3

2

1 44 43 42 41 40

•

31

AD

38

011

37

010

38

09

35

D21 12

34

VSSO
09

Dll 13

33

07

001 14

32

09

A71 15

31

05

A81 18

30

04

All 17

21 ~03
18 19 20 21 22 23 24 25 28 27 28

BLOCK DIAGRAM
PIN NAMES

AD-All

Vee
Vas

AO-All .•••••••• Address Inputs
iN. . . . . . . . . . . . . Write Enable
lL . . . . . . . . . . . Output Enable

VSSQ

00-011
00

DO-OI1 ••..•..•.• Data Inputs
00-011 . . . . . . . . . Data Outputs
K • • • • • • • • • • • • • • Clock Input
VCC . . • • . • . + 5 V Power Supply
VSS ..•...•.•.•.•• Ground
VSSO ..•.• Output Buffer Ground

w

For proper operation of the device VSS
and both VSSO laade must be con·
011

nected to ground.

ROW A5, M, A3, A2, AI. AD. A6
COL
A7. All. AID. AI. A8
MSB
LSB

This document contains information on • product under devaIopmant. Motorola nII8IV8I the right to chango or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-119

•

MCM62975

TRUTH TABLE
W

Operation

OO-Q11

Current

L

Write

High Z

ICCA

H

Read

Dout

ICCA

..

NOTE: The value W is a valid input for the setup and hold times relatove to the K nSlng
edge.:

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss=Vssa=O V)
Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Yin. Vout

-0.5 to VCC+0.6

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 26·C)

PD

1.6

W

Temperature Under Bias

Tbiss

-10to +85

·C

Operating Temperature

TA

Oto+70

·C

Tstg

-55 to +126

·C

RatIng
Power Supply VoItsge
Voitege Relative to VssIVssa for Any
Pin Except VCC

II

Storege Temperature

NOTE: Permanent devios damage may occur if ABSOLUTE MAXIMUM RATINGS are
exosedad. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
axtended periods of time could affect devios relisbility.

This device contsins circuitry to protect the
inputs against damage due to high static
voltages or electric hide; howawr. it is adviaed that normal precautiona be tsken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedanos circuit•
This is a aynchronous devios. All synchronous inputs must mast the specifisd setup
and hold times with stable logic levels for
ALL rising edges of clock (K) while the device is selected.
This devlos contslna circuitry thst will ensure the output devices are In High Z st
power up. Care should be tsken by the user
to ensure thst all clocks are st VIL or VIH
during power up to prevent spurious reed
cycles from occurring.
This CMOS memory circuit has bean deSigned to mast the de and 8C specifications
shown In the tsbles. after thermal equilibrium has bean astsblished. The circuit is in
a test sockst or mounted on a printed circuit
board and tranaveres air flow of st least 600
linear feet per minuts is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5_0 V ±10%. TA=O to 70·e. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to vSS --vssa -- 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.6*

-

0.8

V

Symbol

Min

Max

Unit

±1.0

,.A

±1.0

,.A
rnA

Parameter

*VIL (min) = -3.0 V ac (pulse width ",20 na)

DC CHARACTERISTICS
Parameter
Input Leakage Current (Allinpuis. Vln=O to VCC)

IlkAUl

Output Leaksge Current (~=VIH. Vout=O to VCC. Outputs must be high'Z)

IlkA(O)

AC Supply Current ((;=Vllo Alllnputs=VIL or VIH. 10ut=0 mAo Cycle
MCM62!175-25: tKHKH = 25 na
Time~tKHKH min)
MCM62!I75-3O: tKHKH = 30 na
MCM62!175-36: tKHKH = 36 na
Output Low Voltage (lOL = 12.7 mAl
Output High Voltage (lOH = -

1:8 mAl

ICCA

-

170
170
150

VOL

-

0.4

V

VOH

2.8

-

V

CAPACITANCE (f= 1.0 MHz. dV =3.0 V. TA = 25·C. Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capecitsnca

.Cin

4

6

pF

Output Capecitanos

Cout

6

7

pF

Characteristic

MOTOROLA MEMORY DATA
5-120

MCM62975

AC OPERATING CONDITIONS AND CHARACTERISTICS

+ 70·e,

(Vee =5.0 V ± 10%, TA=O to
Input Timing Measurement Reference Level • • • . • . • . •• 1.5 V
Input Pulse Levels . . . . . . . . . . . • . . . . . • . . • . .0 to 3.0 V
Input Rise/Fall Time . . . . • . . . . • • . . . . . . . . . . • . • • 5 ns

Unless Otherwise Noted)

Output Timing Measurement Reference Level • • • . . • . • • 1.5 V
Output Load •...•••••• See Figure lA Unless Othetwise Noted

READ/WRITE CYCLE
Symbol

Parameter

MCM8297&-2&

MCMII2875-3O

MCM8291&-3Ii

Min

Max

Min

Min

Max

-

30

35
35

-

30

35

ns

3,4,5

15

ns

3,4,5

13

-

15

ns

3

0

-

0

-

ns

Read Cycle Time

tKHKH

25

Write Cycle Time

tKHKH

25

Clock High Access Time

tKHQV
tKLQV

-

25

Clock Low to Output Valid

C3 Low to Output Valid

IGLQV

-

10

Output Active from Clock Low

tKLQ)(

0

-

Output Active from G Low

tGLQ)(

0

Clock Low Pulse WKith

tKLKH

5

30

10

Max

13

Unit

Not..

-

ns

1,3

-

ns

2,3

tKHKL

5

5

-

tAVKH
tDVKH
twHKH

5

-

5

-

5

-

tKHAX
tKHDX
tKHWX

3

-

3

-

3

-

Clock Low to Output High Z (W=Vll)

tKLQZ

0

10

0

13

0

15

ns

5,7

~ High to Output High Z

IGHQZ

0

10

0

13

0

15

ns

3,7,8

Clock High Pulse Width
Setup Times for:

A

0

W
Hold Times for:

A

0

W

-

0
5

-

0
5
5

ns
ns
ns
ns

1,2,6

ns

1,2,6

NOTES:
1. A read is defined by W high for tha specified setup and hold times.
2. A write is defined by W low for the specifoed setup and hold times.
3. All read and write cycle timing is referenced from K or from ~.
4. Access time is controlled by tKLQV if the clock high pulse width ;,,(tKHQV-tKLQV); otherwise it Is controllad by tKHQV.
5. K must be low for the outputs to transition.
6. This is a aynchronous device. All aynchronous inputs must meet the specifoed setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selacted.
7. Transition is measured ±500 mV from staady-atste voltaga with load of Figura lB. This perameter is samplad and not 100% tested. At any
given voltaga and temperatura, tKHQZ max is less than tKHQ)( min and tGHQZ mex is I... than IGLQ)( min for a given device.
8. C3 becomes a don't cere signal for successive writes attar tha firat writa cycla.

AC TEST LOADS

+5V
330

330

Q------+

Q -.....- - - -......

85 pF
PNClUDING
SCOPE AND JIG)

330

5 pF
DNCWDING
SCOPE AND JIG)

330

Figure lB

Figure lA

MOTOROLA MEMORY DATA
5-121

•

MCM62975

READ CYCLE

K(CLOCK!

ii (OUTPUT ENABLE!

A (ADDRESSI

i IWRITE ENABLEI

II

o (DATA OUTI ---+==:-::::::-::---1(

WRITE CYCLE
14-----IKHKH----~

K(CLOCKI

ii (OUTPUT ENABLEI

A(AODRESSI

i !WRITE ENABLEI

o (DATA INI

o (DATA OUTI

0,,-1

Trc'-------

ORDERING INFORMATION
(Order by Full Part Number)

---',._T
..
CM

Motorola Memory Prefix _ _ _

Pert Number _ _ _ _ _ _ _ _ _ _ _ _
..J

L_ _ _ _ _ _ _ _

Full Part Numbers-MCM62975FN25

Package (FN= PLCC)

MCM62975FN30

MOTOROLA MEMORY DATA
5-122

Speed (25=25 ns, 30=30 ns, 35=35 n8)

MCM62975FN35

MOS EEPROM.

MCM2814

MOTOROLA MEMORY DATA
6-1

256x8 .............. 6-3

II
CMOS EEPROMt
(+5 V, 0 to 700 C)
Part Number
MCM2814P
tAvailabla in Europe only.

MOTOROLA MEMORY DATA
6-2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM2814

Advance Information
258x8 arr SERIAL EEPROM

HCMOS

The MCM2814 is a 2048-bit serial electrically erasable PROM.
Designed for handling data in applications requiring both non-volatile
memory and in-system information updates.

(FLOAT1NIMATE lECHNClLOGY)

2&8x8 arr
ELEcrRlCALLV ERASABLE

PROGRAMMABLE READ
ONLVMEMORV

The MCM2814 is fabricated in an 8-pin OIL package using floatinggate HCMOS EEPROM technology.

Featu....:
• 8-pin DIP, in HCMOS for low consumption.
• 2048 bits organised as 256 bytes.
• Byte programmable.
• 3 - 6 V supply during read operations.
• On-chip Programming Voltage Generator.
• Two programming modes: two-wire serial access, M-bus/four-wire
serial access SPI.
• Data protection of %, V.. or % array with EEPROM bits.
• Simultaneous programming of 1 to 4 bytes.
• Automatic byte address increment in Read mode.
• Chip selection with separate pin.
• Single 4.5 V to 6 V supply during programming.
• Digital filtering on Clock and Data inputs.
• Bit program operation: no byte erase necessary.
• Data protection after Reset.
• Write/Erase endurance: 10000 cycles.
• Data retention: 10 years.

'.
PSUFFIX

PLASTIC PACKAGE
CASE 626-04

•

PIN ASSIGNMENT

CSO/SPISS 1

7 EXTERNALI

CSIISPlSO 2

TEST

FETMOS
(Floating-Gate EIec:tron Tunnelling MOS)

6 SCL/SPICK

5 SDA/SPISI

Thin Oxide

Poly Oxide
\

/

\
\

/

\
\

/

PIN DESCRIPnON

Voo:
VSS:
Externall

\
Field
Oxide

Field
Oxide

Test

Connected to on-chip
Voltage Multiplier output

Mode =

OM-bus

CSO
CS1
SCL

Chip Select (Hardwired)
Chip Select (Hardwired)
Serial Date 110
·Serial Clock Input

Mode =
SPISS
SPISO
SPlSI
SPICK

1SPI
Slave Select Input
Serial Data Output
Serial Data Input
Serial Clock Input

SOA

P - Subslrate

MOTOROLA MEMORY DATA
6-3

Power Supply
Ground (Ref)

MCM2814

SECTION 1. PIN DESCRIPTION
correspond to the CS J ! CS(l code for proper chip
selection. Up to four MCM 2814 can be connected on the
same ,SCI,. and SOA lines. (See Figure
41.
,

cso/sPllIs" 1

7 EXTERNALITEST

CSIISPlSO" 2

SCUSPICK"

SOAISPISI"

In SPI mode this pin is a push-pull slave data output
(SPISO).ltwill shift-out byte addresses and data as
described in Section 4.
This pin is usually connected to the data input pin of a SPI
master (MISOI.
This pin can not be pulled higher than 0.5 V above VOO,
even if VOO is at VSS level.

"M-bus/SPI

1.5

Figure 1 Pinout

1_1 VsslVoo (Pins 4/8)
VOO and VSS are used to power the circuit. In read mode
this supply voltage must be comprised in the VOOR range.
(See 5.2 Electrical Characteristics). In program mode this
supply range is limited to VOOP.

•

eso ! SPISS (Pin 1)

In M-bus mode this pin is used in conjunction with CS1 for
chip selection. (See abovel.

1.2 ExtemallTest (Pin 7) ,
This pin is used for testing the on-chip voltage multiplier
that generates the programming voltage required for a
program operation, and should be left open for 5 Volt only
operation.
An external capacitor (Low leakagelon this pin might have
a positive impact on the programming endurance, as the
Vpp rise time will be increased.
Recommendations will be issued after the
characterisation'. As this on-chip generator has a high
impedance, an external supply can be connected to this
pin. This' also allows to block any inadvertant
programl!'ing by maintaining this pin at VOO.

In SPI mode this pin isa Slave Select input. In this mode
the serial access is deselected when the SPISS input is
high, and the SPISO data output pin is forced high
impedance. Multiple chips using ,the same SPICK, SPISI
and SPISO lines, can be selected via this pin as described
in Figure 10.
After powering up the device, a falling edge of the SPISS
line is required to start the SPI serial access.
This pin is high impedance when "DO is, /It VSS level.

1.6 SCL! SPiCK (Pin 6)
The serial clock is supplied on pin SCL ! SPICK. This pin is
an input only, therefore the chip can only operate as a
slave under the control of a serial bus master.
The clock input rising edge is used to shift in data present
on the SOAISPISI pin, and the falling edge is used to shift
out data on the SOA or SPISO pin.
This pin is high impedance when Veo is at VSS level.

1.3 Mode (Pin 3)

1.7 SOAI SPiSI (Pin 5)

This pin is used to select one of two modes of operation:
M-bus mode at the low logic level or SPI mode at high
level.
This pin is usually hardwired to VSS orVOO.lt should only
be changed if the circuit is internally in a standby state.
This pin is high impedance when VOO is at VSS level.

In M-bus mode, SOA pin is used totransmit data serially in
the memory (Receiverl or from the memory (Transmitterl.
Data transmitted via this pin includes chip addresses, byte
addresses, byte data, Read/Write and acknowledge bits.
When SOA is in output, it operatas as a pull-down only
device (Open-drain). The protocol of this transmission is
described in Figures 5 and 6.

1.4 CS1! SPiSO (Pin 2)

In SPI mode, this pin is a Slave data Input (SPISI) only and
is used to receive opcodes, byte addresses and byte data.
It is usually connected to the data output pin of a SPI
master. (MOSI).

In M-bus mode, this pin is used for selecting multiple
identical chips on the same serial bus. The chip address is
formed by 5 bits predefined for this chip, followed by 2
additional' chip select'bits. These last two bits must

This pin is high impedance when VOO is at VSS level.

MOTOROLA MEMORY DATA

MCM2814

SECTION 2. EEPROM

Source

N+

N+

N+

Source

Drain

I READ
I PROGl

I PROGO

S
CG
0
OV VOO OV
OV VPP OPEN
OV
VPP OV

Figure 2 EEPROM Transistor

256 Bytes of EEPROM memory are implemented in a
floating gate double poly-silicon process. A Byte Address
register is used to select one of the bytes. Three basic state
of operation can be distinguished :

as the on-chip voltage multiplier. If there is a capacitive
load on the Vpp pin, the Vpp rise time should be added to
the minimum program time tpROG.
In SPI mode, programming could start when a write serial
transmission is ended with an SPISS rising edge. Actual
programming will only happen ifjlnabled by a Vppenable
serial command. This cominand can be transmitted
before or after the write sequence.

• Standby state.
• Read state
• Program state

2.1 EEPROM Operation

2.2 EEPROM Data Protection

2. ,. 1 Standby State
In this.state, neither a programming, nor a serial
transmission occurs, and the power consumption is
minimum. (See 3.4.1/!nd 4.5).
2.1.2' Read State
In read state the data of the selected byte is transferred
from the memory array to the data shift register used for
the serial transmission. This state is active during a serial
transmission.
.
2.1.3 Program State
In this state, a programming voltage higher than VDD is
necessary. This voltage is generated by the on-chip
voltage multiplier or can be supplied externally. During
programming VDD must be within the VDDP range. (See
5.2).
In M-bus mode, the programming starts at the end of a
write command, when a STOP or a new START condition
occurs. The programming is enabled at this time, as well

Some circuitry has been included to prevent unwanted
modification of EEPROM data, and is described below.
However, a noisy serial link is very often the cause of bad
data or data written to the wrong address. Besides
measures to reduce this noise on the board, the serial
clock and data inputs (SCL/SDA) have Schmitt triggers
and digital filters to .reject some of the noise.
2.2.1 Power Up Reset
Immediately after power is applied, programming is
inhibited to prevent EEPROM data loss during the syStem
power up.
In both modes this condition is removed when a READ is
performed.
.
In M-bus mode, the read bit with avaliel chip address giyes
the control to the MCM2814. Therefure another 8 bits read
without master acknowledge is necessary to stop ttie read
sequence.
In SPI mode, it is sufficient to send the READ opcode
before a new Vpp enable command and the write
sequence.

MOTOROLA MEMORY DATA

II

MCM2814

At Reset the following circuitry is initialised:

2.4 EEPROM Reliability

• The circuit is in standby state.
• In M-bus mode, it is waiting for a start condition.
• In SPI mode, it is waiting for a high to low SPISS
transition.
• The data outputs are high impedance (SDA, SPISO).
• The programming is disabled.
• The on-chip Vpp generator is off.
• The byte address register is cleared ($00).

Reliability figures are statistical in nature. Therefore no
minimum or maximum specifications can be applied. The
result of reliability tests will be published instead. These
tests are conducted on a regular basis during the
production life of a Circuit and reports are available upon
request.

2.2.2 Programming Voltage Enable

Typical data retention should exceed 10 years for the
specified operating temperature range. Data retention is
usually tested with the device under bias, but without
accessing the EEPROM array.

In SPI mode only, an internal programming voltage enable
flip-flop can be set or cleared with two separate opcodes,
thus reducing the risk of unwanted EEPROM
programming.
2.2.3 Array Write Protect
In both modes, byte address 255 ($FF) contains EEPROM
bits with a special function. When one or two bits of this
address are programmed at once, the programming of
EEPROM sections is inhibited according to the following
table:

•

Dlltaat

Protected

ADDRSFF

Addresses
No Write Prot.
$CO-$FB
$BO-$FB
$4O-$FB

XXXX
XXXX

OOXX
01XX

XXXX

10XX

XXXX

l1XX

No.ofBytas
Protected
60
124

188

x ~ Don't care
Table 1 EEPROM Write Protect
This protection is reversible as address 255 ($FF) can be
modified at any time.
2.3 EEPROM Properties
NO ERASE: Unlike most EEPROM's it is not necessary to
erase a byte before writing new data to it.
The program operation takes tpROG and must be
externally timed.
CUMULATIVE: As the programming operation is under
external control, it can be done at once or at various time
frames as long as the total programming time exceeds the
specified minimum tPROG value.
tPROG is defined with Vpp at its programming level.
SELF LIMITING: Excess pogramming has no positive
effect, as programmed EEPROM thresholds will
asymptotically reach their nominal values. Programming
durations above the recommended maximum tPROG
have negative impacts on the EEPROM programming
endurance.
.

2.4.1 Data Retention

2.4.2 Read Stress
Unlike some non-volatile memories, there should be no
disturbance of the stored data under continuous read of
EEPROM bytes. The life limit under continuous read
condition should therefore be similar to the normal
operati ng life of the device.
2.4.3 Program Endurance
As for all EEPROM's, there is a wearout mechanism
associated with the programming mechanism of the non
volatile memory. Mora than 10,000 programming cycles
shoulcHleilQSSible per memory bit, for the specified
operating temperature ninge. A programming cycle is
defined as a 0 to 1 to 0 programming. Unlike most
EEPROM's where the whole byte is'erased before being
re-programmed, if just one bit is modified in a byte, only
this bit will see the programming stress..
Some endurance experiments have shown that the
number of programming cycles can be increased if the
Vpp rise time is increased. This can be achieved with an
external capacitor on Vppwhen theon-chip Vpp generator
is used. In SPI mode, the Vpp should be enabled after the
write command has been transmitted.
If an external Vpp is provided, it should be ramped up only
after the write command is transmitted. In this case, a Vpp
above the maximum value has aiso a neagtive impact on
the endurance.
2.5 Vpp Voltage Multiplier
In M-bus mode, the on-chip Vpp generator is turned on or
off automatically during a program sequence.
In SPI mode, it is switched on only after a serial Vpp enable
command has been issued, independently of write or read
commands.

MOTOROLA MEMORY DATA

MCM2814

SECTION 3. M-BUS OPERATING MODE
The MODE pin can be hardwired to VDD or Vss to select
two different modes of operation. Differences are at the
serial transmission level and in the EEPROM operation.
They are called M-bus mode and SPI mode.

•
•
•
•
•
•
•
•

3.1 M-bus Mode
Only two wires are needed to control the device operation.
The serial transmission ofthis mode issimilartothe lie (*)
serial communication standard. It features :

Up to 4 identical chips on the same 2 wire bus.
CS1 / CSO pins for chip selection.
SCl clock line, input only.
SDA line used as Input and Output.
Data acknowledge bit generated.
Auto programming after reception of new data.
Programming time under external control.
Write inhibit after reset.

'IIC is a trademark of Philips

Memory
Array
256 Bytes

B-1

II
O:M-Bus

Chip
Address

M-Bus
Interface

Bit Drive
and Sense
Data Reg.

Figure 3 M-bus Block Diagram

3.2 Lexicon
This lexicon will describe some terms used in this serial
interface description.

SLAVE: This memory always operates as a slave.
TRANSMITTER: The device with its SOA pin in output is a
data transmitter. In the case of multiple devices in output,
the device sending a low level will win due to the OpenDrain connection.

MASTER: The device that initiates the serial transmission
is designated as master. In general, it is the device
generating the clock. This memory can never function as a
master.

RECEIVER: A device that has been properly selected by a
chip address follQwed by a write bit is a receiver, and will

MOTOROLA MEMORY DATA
6-7

MCM2814

,The 2 chip select bit~ must correspond to the 2 chip select
inputs for proper chip selection. By this means, up to 4
identical chips can be connected,o!) the sal)1e'SQA / SCL
lines, in order to form a mem!,ry bank of up to 8 ~Bits.

shift data present on the SDA pin in internal registersMSB : The Most Significant Bit is the first bit transmitted
and received.
START CONDITION: The start condition is·defined as a 1
to 0 transition of SDA when SCL is high. The first byte of
data following a start condition includes the chip address
followed by the RIW bit. All del(ices connected.on the
same bus receive this data to c;heck if they ~re addressed.

READIWRITE BIT: The 8th bit tr.ensmitted by the master
after the 7 bit chip address will indicate the direction of
transfer for the next bytes. (Until a new start or stop). If
low, the following bytes are transmitted by the master. If
high, the following bytes a.~e transmitted bythe.MCM
2814.

STOP CONDITION: The stop condition is defined as a 0 to
1 transition of SDA when SCL is high. In this circuit, the
stop condition is never mandatory. An EEPROM
programming can be initiated by the STOP or also by any
following START condition.
A STOP after a serial read sequence will' put the device in
standby state.

BYTE ADDRESS: The first byte of data received by the
memory after the chip address, will be latched in the byte
address register and is used to select one of the 256
EEPROM bytes.
ACKNOWLEDGE BIT: This bit is sent by the selected
receiver on the data line after a byte reception. Due to the
open drain structure, a valid acknowledge bit corresponds
to a low level. While operating as a transmitter, sending a
sequence of data bits, this device will check the
acknowledge bit generated by the master. The absence of
this bit will stop the transmission of data.

CHIP ADDRESS: The first byte transmitted after a START
contains the chip address followed by the Read/Write bit.
The 7 bit chip address is formed of 5fixed bits followed by
2 chip select bits.
Fixed bits are 1010X for this device (X is a don't care bit).

3.3 Chip Selection

II

The 2 chip select bits transmitted in the chip address must match the status of CS1 and CSO inputs.

Master
MCU

Pin Status

Mod.
0
:0
.0
0

CSl
1
1
0

0

CSO
1
0
1
'0

Chip Addr•••
Transmitted

1010
1010
1010
1010

Xll
Xl0
XOl
XOO

x ~ Don't care
VDD

--0

VSS ""}

Figure 4 M·bus Chip Selection

3.4 Protocol
made, the circuit is in standby. A STOP condition following
a read sequence or a write byte address sequence (without
data write), will put the circuit in standby. A new START
condition will wake up the deviCe, to get the chip address.
If the chip address is not valid, the device will return in
standby.
.
The power consumption is minimum in standby.

At the protocol level, the transmission of data is defined in
.the.fo.rm of sequences of Start (STA), Stop (STO)
conditions, and bytes followed.by acknowledge bits.

3.4,1 Standby State ..
When no seriaitransmission and no programMing are

MOTOROLA MEMORY DATA
6-8

MCM2814

Write One Byte

STA

CHIPADDR

o

A
S

A

BYTEADDR

DATA IN

S

I

I

PROGRAM

STA

STARTPROG.

1: ~HI~ +D~: I~I ;1
I
STOPPROG.

Write up to 4 Bytes

A

BYTEADDR

(CONT.)

DATA IN

S

I ~A~AI~: 1;I~i~1
:

:

PROGRAM

:

A

S

I I : ~HI~A~D~
STA

I

STARTPROG.

RIW BIT: 1 = Read/O = Write
INC: Increment Byte Address

S

I~I;I

:

I

STA: Start Condition
STO: Stop Condition

A

DATA IN

STOPPROG.

AS: Slave Acknowledge (2814)
AM: Master Acknowledge

F"lgure 5 M-bus Write Protocol

3.4.2 Write Sequence

It is possible to program simultaneously up to 4 bytes,
provided the 6 most significant bits of their addresses are
identical. The byte address is incremented after each new
data byte shifted in.

The serial write to the memory includes a serial
transmission of the byte address and the data to be
written. When this is completed by a stop or a new start
condition, the programming sequence is initiated.

3.4.3 Read Sequence
Reading data from the memory is made In two steps. First
the byte address must be loaded in the byte address
register. Then data can be read out of the memory. The
first step is only· required to define the byte address. If this
address was predefined from a previous read this step can
be skipped.
The byte address is automatically incremented after each
data byte transmitted.
This is also valid after the last byte of a transmission.
Therefore, the next read sequence without any byte
address specified, will transmit data ofthe next byte. A
read sequence will transmit data bytes of successive
addresses until the absence of the acknowledge bit from
the master. In this case the SDA output driver will switch
off and the circuit will go to standby.

Programming is under control of the master. It is initiated
by the write sequence just described, and stopped by any
new valid selection of the chip.
Therefore, the tpROG time is defined as the time between
these two operations, and is defined by the master.
Bad chip addresses or chip addresses for other chips on
the same bus do not suspend the programming.
The on-Chip Vpp generator is automatically turned on or
off when needed. If an external Vpp is applied, the
programming voltage is only allowed into the array during
the above defined tPROG time.

MOTOROLA MEMORY DATA
8-9

•

MCM2814

Read One Byte. (Inc. Write Byte Address)

STA

CHIPADDR

oA
S

CHIPADDR

BYTEADDR

DATA OUT

Read One More Byte. (Byte Add .... Defined)

I

..........

INC

OPTIONAL

Read Many Bytes

BYTEADDR
OPTIONAL

/

II

STA: Start Condition
STO: Stop Condition

RIW BIT: 1 = Read/O = Write
INC: Increment Byte Address

AS: Slave Acknowledge (2814)
AM: Master Acknowledge

Figure 6 Mabus Read Protocol

ST~T
7\1
r=:r.-L:]
I I
_
CHIP ADDRESS

I

READ
BIT

NO MASTER
ACK.
,
'
ST~

I,

'
2814ACK

,/

DATA OUT
r-y-y-v-y--r--'\

\'_.L.._.A._..A.'_A_..A._J

'

:rt-

L.!Jil
I

It\J1L
- J7\...f8V9\J1\J - Jilf8\J9\JTt
I _
1-,
SDA CONTROL: - - - MASTER

-

-

-

Figure 7 M-bus Read Detail

MOTOROLA MEMORY DATA
6-10

MCM 2814

MCM2814

3.4.4 Signal Levels

tHSTA

tSSDA

tHSDA

tssro

tBUF

SOA
INPUT

seL
INPUT

START

SOA

OUTPUT

_-

I

....

STOP

tCLL

I

I

1...--

START

1-tRO

Figure 8 M-bus Timings

The acknowledge bit is provided by the device receiving
data. Therefore, during this time the data transmitter must
leave the SOA line at high impedance.
As this memory has an open drain SOAoutput, an external
pull-up resistor to VOO should be included on SOA line.

Electrical and switching characteristics are described in
Section S.
During a transmission, SOA line transitions must occur
when SCL is low. A negative transition of SOA with SCL
high is recognised as a START condition, the positive
transition as a STOP condition.

SECTION 4. SPI OPERATING MODE
The serial transmission of this mode requires 4 wires to
control the device operation. It features:

• Programming under control ofthe master via serial
opcodes.
• Programming time under external control.
• Write inhibit after reset.
• Write enable/disable via serial opcodes.
• Byte address output for transparency.

• Multiple chips on same 3 wire bus with separate chip
select lines.
• SPISS chip selection.
• SPICK clock line, Input only.
• SPISlline used as Input only.
• SPISO line used as Output only.
• No acknowledge bit.

This SPI mode can be used with the SPI of Motorola
Microprocessor MC680SS2/S3, MC680SK2/L3/L8,
MC68HCOSC4 and MC68HC11.

MOTOROLA MEMORY DATA
6-11

II

MCM2814

Vpp

14--.-------,

~

1:SPI

SPI
Interface

II

Figure 9 SPI Block Diagram
4.1 SPI Serial Interface
Data OUT (MOS!)

.~ SPISI

Daui IN (MISO)

Master
MCU

~

SPICK

f--

SPISO
SPICK

MODE

2814

f---o

SPISS

I

SS3 SS2 SS1 SSO

~

>-f--

SPISI
SPISO
SPICK

MODE

--0

2814
SPISS

I

>-~

.SPISI
SPISO
SPICK

MODE

2814

""-

SPISS

I

....

VDD --<>

>---

VSSy

SPISI
SPISO
SPICK

MODE :--<'

2814
SPISS

I
Figure 10 SPI Chip Selection

MOTOROLA MEMORY DATA
6-12

MCM2814

4.3 SerialOp-Code

The serial interface via pins SPICl, SPISI and SPISO is
compatible with the SPI standard when the MODE pin is
high.

The first byte transmitted after the chip is selected with
SPISS going low, contains the opcode that defines the
operation to be performed.

4.2 Lexicon
This lexicon will describe some terms used in this serial
interface description.

Data
Transmitted
1010 0111
1010 0110
1010 0100
1010 0010

MASTER: The device that generates the serial clock on
SPICK is designated as master. This memory can never
function as a master.
SLAVE: This memory always operate as a slave as the
SPICK pin is always an input.

Table 2 SPIOpcodes

TRANSMITTER / RECEIVER: This device has separate
pins for data transmission (SPISO) and reception (SPIS!).
Simultaneous data input and output can therefore occur
when the chip is selected with SPISS and is clocked
(SPICK).

All other codes are invalid. After an invalid code is
received, no data is shifted in the MCM 2814 and the
SPISO data output is high impedance until a new SPISS
falling edge re-initialises the serial communication.
4.4 Protocol

MSB : The Most Significant Bit is the first bit transmitted
and received.

The MCM2814 SPI interface accepts both a negative or
positive clock.
The SPI protocol for this device defines the bytes
transmitted on the SPISI and SPISO data lines for proper
chip operation.
.

CHIP SELECT: The chip is selected when pin SPISS is low.
When the chip is not selected, no data will be input from
pin SPISI, and output pin SPISO is high impedance.

SPI Negative Clock

SPISS
SPICK
SPISI
SPISO

SPI Positive Clock

r

\

Operation
Read byte address followed by data.
Program enable. Vpp generator ON.
Program disable. Vpp generator OFF.
Write IPrograml data.

\

~;

~;

~:

~:

r

Positive Clock Edge: Shift IN
Negative Clock Edge: Data OUT
Figure 11 SPI Clock Phase and Polarity

4.5 Standby State
The circuit is in standby when no serial transmission takes
place, when no write is waiting for the Vpp enable
command and when the VPp generator is off.
When SPISS is high, standby state will follow:
• A power up reset.

• A Vpp disable command.
• A Read, providing no Vpp enable command has been
issued previously.
The power consumption is minimum in standby.

MOTOROLA MEMORY DATA
6-13

..

MCM2814

4.6 Read Sequence

Read One or More Bytes
SPISS
SPISI
SPISO

r

""\

:sssx~.;=RE=AD=C=OD=E~X;::B=YTE=A=D=DR=X\:;:;:::\\;::;,:;:,:;,;::;\\:;:,:;,:;:::\\;::;,:;,:;:::\\;::;,:;:,:;,:;:::,,;::;,:;:,:;,;::;\\:;:,~,......
S
--< WA'lPdI. X d'N{Jal/,fj, XBYTEADDR X DATAl") XDATAI"+l) X::::}-

Invalid Opcodes
SPISS
SPIS)
SPISO

\

fiX

--<

BAD CODE

f
)GSSSSSSS

B"m'~c!'~
Figure 12 SPI Read

II

Reading the memory via the serial SPIlink requires the
following sequence.The SPISS line is pulled low to select
the device. The read opcode is transmitted on the SPISI
line followed by the byte address. When this is done, data
on the SPISlline has no more influence on the memory. At
the beginning of an SPI transaction, the SPISO buffer is
turned on and will shift out the current byte address. This

can be used for a relative addressing of the byte address.
The new byte address is then transmitted followed by
corresponding data. If just one byte is read, SPISS can be
pulled back to the high level. It is possible to continue the
read sequence, as the byte address is automatically'
incremented. The byte address is shifted out only once, in
the beginning of a transmission.

4.7 Program Sequence
Write One to Four Bytes

SPISS
SPISI
SPISO

\~;::::::::::~==~==~==~=-=-=~r
DATAl") X DATAI"+l) C =~
-< d'N{Jal/,fj, X d'N{J.'l,'bfj, XBYTEADDR"XB.ADDR"+l C ===>-

~WRITECODEXBYTEADDR"X

VI'!' Enable/Disable
SPISS
SPISI
SPISO

\

I

\

,--

~~~~~==~~
fiX
VPPEN.
X\SS\SSSSSS\X VPPDIS. X\SS\\S\S

--{(~rv\-e~E~VJ8l~'b~fj,~)~~~~:::::~~(~d'"~~~V~~.::>
~I>.

Y2~
(51

I1-::>
Y3

MAXIMUM RATINGS
Characteristic

Symbol

Rating

Unit

= 01
= 0)

VEE

-8.0 to 0

Vdc

Input Voltage (VCC

VI

o to VEE

Vdc

Output Current -

Continuous

lout

50
100

rnA

Surge

Operating Temperature Range
Storage Temperature Range -

Al
·1(10)

i

• Open Emitter Match lines for Easy Bit Expansion

..

1

BLOCK DIAGRAM

• Single Bit Masking

-

.-

1

The MC10H155 is a 1S-bit .ECL Content Addressable Memory
(CAM). The device is organized as an array of 8 words by 2 bits
with each cell of the array containing an exclusive-OR comparator,
a Ootype latch as well as control logic. The modes of operation
possible with the MC10H155 are reading, writing, associate,
masked associate and the hybrid mode.

Power Supply (VCC

L SUFFIX
CERAMIC PACKAGE
CASE 726-04

o to

TA
Plastic
Ceramic

+75

Y4

a: I~

Y5
Y6

~~
~

16-BIT LATCH
AND COMPARATOR
ARRAY

Y7

"C

-55to +150
-55to +165

Tstg

1rlo
..J

"C
"C

ELECTRICAL CHARACTERISTICS (VEE = - 5 2 V -+ 5%1 (See Notel
25"<:

O"C

75"

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

Power Supply Current

IE

-

135

-

125

-

135

mA

Input Current High
Pins 2,3.4.5,7,
12,14,15,16,17
Pins 10,11
Pin 8

linH

Input Current Low

linL

PIN ASSIGNMENT

pA

-

-

-

240
270
250

-

240
270
250

0.5

-

0.3

-

380
435
400

-

-

0.5

-

-

VCCI
YO
pA

High Output Voltage

VOH

-1.02 -0.84 -0.98 -0.81 -0.92 -0.735 Vdc

Low Output Voltage

VOL

-1.95 -1.63 -1.95 -1.63 -1.95 -1.60

High Input Voltage

VIH

-1.17 -0.84 -1.13 -0.81 -1.07 -0.735 Vdc

Low Input Voltage
NOTE:

VIL

-1.95 -1.48 -1.95 -1.48 -1.95 -1.45

Vdc
Vdc

VCC2
Y4

Yl

Y5

Y2

Y6
Y7

Dl
11
AO

Each MECL 10KH series circuit has been designed to meet the de specifications shown in the

test table, after thermal equilibrium has been established. The circuit is in a test socket or
mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained.
Outputs are terminated through a 50 ohm resistor to - 2.0 volts.

This document contains information on a new product. Specifications and information herein is
subject to change without notice.

MOTOROLA MEMORY DATA
7-S

A1

J-

MC10H155

AC PARAMETERS
25·

0"
Characteristic
Associate Time

(I to V)
(A to V)

Disable Time

(A to V) TDl
(A to D) TD2
(V to D) TD3

Setup Time

(AtoW)
(VtoW)
(I to W)

TS2
TS3
TS4

(Wto D)
(Ito OJ

TW
TA3
TA4

Write Pulse Width
Write Access Time TS4;;.TW
TS4;;.TW

Min

Max

-

6.0
6.0

TAl
TA2

Hold Time

(WtoA) THl
(WtoV) TH2
(iNto I) TH3

Read Access Time TS4;;. TW
TS4;;. TW

(V to D)
(A to D)

-

Cycle Time, CP Rate

8.0
3.0
4.0
8.0
8.0
6.0
1.0
3.0
3.0
6.0
4.0

-

40

75"(;
Max

-

6.0
4.0
7.5

-

TA5
TA6

Min

6.0
6.0
6.0
4.0
7.5
8.0
3.0
4.0
8.0
8.0
6.0
1.0
3.0
3.0

-

6.0
4.0

40

-

Min

-

Max

Unit

7.0
7.0

ns

7.0
5.0
8.0

ns

9.0
4.0
5.0

ns

9.0
9.0
7.0

ns

1.5
4.0
4.0

ns

6.. 0
5.0

ns

-

35

MHz

TRUTH TABLE
AO

A1

10

11

W

DO

01

OnO

On1

Associate 1

1

1

1/0

1/0

X

0

0

OnO

Onl

Associate 1,2
(Masked)

1

0

1/0

X

1

0

01

OnO

Onl

OnO(BIO

Associate 1,2
(Masked)

0

1

X

1/0

1

DO

0

OnO

Onl

On1 (Bll

Mode

Yn
OnO (BIO

+ Onl (Bll

Read2,3

0

0

X

X

1

DO

01

OnO

Onl

o (Selected Address)

Write3,4

0

0

1/0

110

0

10

11

10

11

o (Selected Address)

Hybrid5

1

0

1/0

1/0

0

0

11

OnO

11·Vn

OnO(BIO

Hybrid5

0

1

1/0

1/0

0

10

0

I()oVn

Onl

Onl (Bll

x = Don't Care
anD
Qn'

= Contents of Address n, Bit 0 (n = 0 to 7)
= Contents of Address n. Bit 1

NOTES:
1. 1 (High)

= Mismatch of On (±II, 0 (low) = Match of On (±II

2. DO = OOO·YO + 010·Yl + ... + 010·V7
Dl - 001'YO + 011·Yl + ••• + 011'Y1

3. Under norma' operation, only one Y address is selected for read or write.

4. The write is transparent.
5. At all "matched" addresses there exists a simultaneous Associate and Write.

MOTOROLA MEMORY DATA
7-7

MC10H155

DESCRIPTION OF MODES OF OPERATION
The MC10H155 can be operated in any of the following modes: Read, Write, Associate, Masked Associate
and Hybrid. Lines YO-Y7 can be used as either inputs
(a linear word select in the read/write mode) or as outputs (indicating rnatch/mismatch in the associate mode).

eration only one cell is selected to be read, all V-inputs
of deselected cells must be held high. The state of the
selected cell appears on outputs DO and, 01. In the case
where more than one cell is selected, the outputs of
these cells are OR-ed together and appear on the 00-,
Dl-outputs.

Associate
Data present on the 10 and 11 inputs are compared
with the latch outputs (OnO, Onl) of each cell. If the data
input is at the same state as the latch output of a par·
ticular Y location, that Y-line goes low. Because these
Y outputs are open emitters, expansion in multiples of
2 bits is obtained by tying additional MC10H155's to the
V-bus lines.

Write
in this mode data present at the 10-, 11-inputs is transferred to the latch outputs. Since the 00-, Dl-outputs
are transparent, they follow the state of these 10-, 11inputs. The particular cells to be written into are selected
by taking their respective V-inputs low. All deselected
cells, V-inputs must be held high.

Masked Associate
This mode allows only the comparison of a single bit
which is selected by bringing the corresponding AO- or
Al-Iine high. The other bit is inhibited by holding the
corresponding AO- or Al·line low.

Hybrid
In this mode, only one of the 10- or 11-data inputs are
associated with their respective latch outputs, OnO or
Onl. If a match exists, the corresponding Yn-Iine(s) will
go low. As the Y-Iine goes low, this will address the
other half of the memory for writing new data. Thus,
when 10 matches OnO, it is possible to write 11 in Onl
or vice versa.

Read
The particular cell output to be read is selected by
bringing the associated V-input low. Under normal op-

II

MOTOROLA MEMORY DATA
7-8

MC10H155

LOGIC DIAGRAM

4~
S@]
17§]

16~
IS~
14@)

IVCC11
1

IVCC21 IVEE I
18

9

13

6

MOTOROLA MEMORY DATA
7-9

MC10H156

TIMING DIAGRAMS
READ CYCLE
A

Mode Select

Y

Selected Y

:::I:~~=::t====+~_~_!S(One Line)
Y

Unselected Y
(7 Lines)

o

Data Out

WRITE CYCLE
A

Mode Select

Y

Selected Y
(One Line)
Unselected Y
(7 Lines)

Y

'UJ..LLLLLU..L.U..L....

w

Write Pulse
Input Data

•

o

Data Out

ASSOCIATE CYCLE

-i

A
Y

.lJ.'l\...

~_TD1-:1

. Mismatch
TA:J2

I nJ;-TA1

_

Match

Mode Select

-l _____....;.J.\_ _Y Output

~rr=\.._T_A_1~
____
' ______________
,,_
Input Data

MOTOROLA MEMORY DATA
7-10

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM10139
MECL

2S6-BIT PROGRAMMABLE READ ONLY MEMORY
(PROM)
The MCM10139 is a 256·bit programmable read only memory
(PROM). The circuit is organized as 32 words of 8 bits. Prior to
programming, all. stored bits are at logic 0 (low) levels. The logic
state of each bit can then be changed by on·chip programming
circuitry. The MCM10139 has a single negative logic chip enable.
When the chip is disabled (CS = high), all outputs are forced to
a logic 0 (low).
The MCM10139 is fully compatible with the MECL 10,000
logic family. It is designed for use in microprogramming, code
conversion, logic simulation, and look·up table storage.
Po

= 520 mW typ/pkg (No Load)
= 15 ns typ (Address Inputs)

32 X 8 BIT PROGRAMMABLE
READ-ONLY MEMORY

L SUFFIX
CERAMIC PACKAGE
CASE 620

tAccess

FSUFFIX
CERAMIC PACKAGE
CASE 650

LOGIC DIAGRAM

AO 10

PIN ASSIGNMENT

A111

A212

32

Input

K

8

Decoder

ASSOC:lated Driven
A313

A414

DO

VCC

01

CS

02

A4

03

A3

04

A2

Vee" Gnd

VEE'" -5.2 Vdc

0
07

DO

os

D.

03

3
02

0'

DO

MOTOROLA MEMORY DATA
7-11

05

A1

06

AO

VEE

07

MCM10139

ABSOLUTE MAXIMUM RATINGS
Rating
Power SupplV Voltage (VCC = 0)
Base Input Voltage (VCC = 0)
Output Source Current Continuous
- Surge

Symbol

Value
-8toO

VEE

o to VEE

Vi"
10

Junction Operating Temperature

<50
<100
<165
-55 to +160

TJ
Tstg

Storage Temperature'Range

Unit
Vdc
Vdc
mAde

°c
°c

NOTE: Permanent device damage mav occur if ABSOLUTE MAXIMUM RATINGS
are exceeded.

ELECTRICAL CHARACTERISTICS
Each MECL Memorv circuit has been
designed to meet the de and ac specifications
shown in the test table, after thermal equili·
brium has been established. The circuit is in
a test socket or mounted on a printed circuit
board and transverse air flow greater than 500
linear fpm is maintained. Outputs are ter..
minated through a 5O-ohm resistor to -2.0 volts.

DC Test Voltage Values
(Volts)
Test Temperature
OoC
+ 250 C
+750 C

VIHmax
-0.840
-0.810
-0.720

VILmin
-1.870
-1.B50
-1.830

VIHAmin
-1.145
-1.105
-1.045

VEE
-5.2
-5.2
-5.2

Symbol

Min

lEE

-

MCM10139 Test Limits
+250 C
+750 C
Max
Max
Max
Min
Min
150
145
140
-

Input Current High

lin H

-

265

-

265

-

265

/lAde

Input Current Low

lin L

0.5

-

0.5

-

0.3

-

"Ado

Logic "1"
Output Voltage
Logic "0"
Output Voltage
Logic "1"
Threshold V91tage
Logic "0"
Threshold Voltage

VOH

-1.000 -0.840 -0.960 -0.810 -0.900 -0.720

Vdc

VOL

-2,010 -1.665 -1.990 -1.650 -1.970 -1.625

Vde

DoC
DC Characteristics
Power Supply Drain Current

II

VILAmax
-1.490
-1.475
-1.450

Unit
mAde

VOHA

-1.020

-

-0.980

-

-0.920

-

Vdc

VOLA

-

-1.645

-

-1.630

-

-1.605

Vdc

Conditions

TVp lEE @ 260 C = 100 mAo All out·

puts and inputs open. Measure pin 8.
Test one input at a time, all other
inputs are open. Vin "" VIH.
Test one input at a time, all other
inputs are open. Vin = VIL.
Load 50 n to -2.0 V.

Threshold testing is performed and
guaranteed on one input at a time.
Yin - ViLH or VILA.
Load 50 n to -2.0 V.

SWITCHING CHARACTERISTICS (TA = 0 0 to + 750 C. VEE = -5.2 Vdc '5%; Output Load--See Figur.l and Note 1)
Characteristic
Chip Select Access Time
Chip Select Recoverv Time
Address Access Time
QutRut Rise and Fall Time
Input Capacitance
Output Capacitance

Symbol
tACS
tRCS
tAA
tr,tf
Cin
Cout

Min

-

-

Test Limits
TVp
10
10
15
3.0
4.0
7.0

Max
15
15
20

-

5.0
8.0

Unit
ns
ns
ns
ns
pF
pF

Conditions
See Figures 2 and 3.
Measured from 50% of input to 50%
of output. See Note 2.
Measured between 20% and 80% points

Notes: 1. Contact your Motorola Sales Representative for details if extended temperature operation is desired.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the memory.

MOTOROLA MEMORY DATA
7-12

MCM10139

RGURE 1 - SWITCHING TIME TEST CIRCUIT

Vee

= Gnd

r-----t1!----.

15

10
11
12 _
13
14

I
i

:
I
I

I
I

I

I
I
I
I
I

es

J

DO

J
i

01
AO

02

A1

03

A2

D4

I
I

A3

I

05

2

3
4
tr

5

All timing measurements referenced to 50% of input levels.
All outputs loaded 50 ohms to - 2.0 Vdc.

6

I

A4

06

I
I
I
I

7

I

07

9

= tf = 2.0 ns tvp

50

I
I

L----T±~~~'
-2.0 Vdc
-5.2 Vdc

VEE

FIGURE 2 - CHIP SELECT ACCESS TIME

°out

FIGURE 3 - ADDRESS ACCESS TIME

Address

°out

MOTOROLA MEMORY DATA
7-13

MCM10139

RECOMMENDED PROGRAMMING PROCEDURE*

The MCM10139 is shipped with all bits at logical "0" (low). To write logical "1s", proceed as follows.
MANUAL ISo. Figure 4)

AUTOMATIC (So. Figure 5)

Step 1
Connect VEE IPin 8) to -5.2 V and VCC (Pin 16) to
0.0 V. Address the word to be programmed by applying
-1.2 to -0.6 volts for a logic "1" and -5.2 to -4.2 volts for a logic
"0" to the appropriate address inputs.

Step 1

Connect VEE (Pin 81 to .5.2 volts and VCC (Pin 16)

to 0.0 volts. Apply the proper address data and raise VCC
(Pin 16) to +6.8 volts.

After a minimum delay of 100 J,J.$ and a maximum delay
of 1.0 ms, apply a 2.5 mA current pulse to the first bit to
be programmed (0.1 ..;;; PW ...; 1 msL

Step 2
'Step 2

Raise VCC (Pin 16) to +6.8 volts.

3 After Vee has s~abilized at +6.8 volts (including any
ringing Which rTlE:!Y be present on the Vee line), apply
a current pulse' of 2.5 mA to the output pin corresponding to the

Step

bit to be programmed to a logic "1",
Stap 4

Step.3

Repeat Step 2 for each bit of the selected wOf,d specified
as a logic "1". (Program only one bit at a time. The delay
between output programming pulses should be equal to or less than
1.0 ms.)

'

Return VCC to 0.0 Volts,

Step 4

A fter all the desired bits of the selected word have been
programmed,
change
address
data and
repeat
Steps 2 and 3. I

CAUTION

To prevent excessive chip temperature rise, Vee should not
be allowed to remain at +6.8 volts for more than 1 second.

NOTE: If all' the maximum times listed above are maintained, the
entire memory will program in less than 1 second. Therefore, it
would be permissible for Vee to remain at +6.8 volts during the
entire programmin,] time.

Stap 5

Verify that the selected bit has programmed by connecting a 460 n resistor to -5.2 volts and measuring
the voltage at the output pin. If a logic "1" is not detected at the
output, the procedure should be repeated once. During verification
VIH should be -1.0 to -0.6 volts.

Step 6

After stepping through all address words, return Vce to
0.0 volts and verify that each bit has programmed. If one
or more bits have not programmed, repeat the entire procedure
.once. During verification VU:i should be -1.0 to -0.6 volts.
Step 5

If verification is positive, proceed to the next bit to
be programmed.

*NOTE: For devices that program incorrectly-return serialized units with individual truth tables. Noncompliance voids warranty.

PROGRAMMING SPECIFICATIONS
Limits '

Characteristic
Power Supply Voltage
To Program
To Verify

Programming Supply Current
Address Voltage
Logical "1"
Logical "0"

Symbol
VEE
VCCP
VCCV

Min
-5.46
+6.04
0

Typ

Max

Units

-5.2
+6.8
0

-4.94
+7.56
0
600
-0.6
-0.6
-4.2

Vdc
Vdc
Vdc

ICCp

-

VIH Program
,VIHVerify
VIL

-1.2
:::1.0
-5.2

-

-

2.5

Maximum Time at VCC - Vccp

200

-

Output Programming CUrrent

lOp

Output Program Pulse Width

tp

2.0
0.5

Output Pulse Rise Time

-

-

-

td
td 1

0,1
0.01

-

Programming Pulse Oalay (1)
Following V CC change

Between Output Pulses

-

-

'NOTE 1. Maximum is specified to 'minimize the amount of time V CC is at +6.8 volts.

MOTOROLA MEMORY DATA

'·14

1.0
3.0
1.0
10
1.0
1.0

mA
Vdc
Vdc
Vdc

sec
mAde
ms
I'S

ms
ms

Conditions

VCC

= +6.8 Vdc

MCM10139

FIGURE 4 - MANUAL PROGRAMMING CIRCUIT

+6.8 V 0.0 V

+16 V

1

Program
-0.8 V

3k

--,
I
I

Address

"'"

"0"

460n
Outputs

VEE
-5.2 V

CE

8

Open

7.5 k
(All Outputs)

VEE
-5.2 V

VEE
-5.2 V

VEE
-5.2 V

FIGURE 5 - AUTOMATIC PROGRAMMING CIRCUIT

Address

VCC

.J

U

I

I

-.J

,

2

3

8

~t

L

I
i

,

2

3

8

I

11

,

2

L
8

outPut~~~~

I~ ~tdl

'd-

-

t--

~tp
<1 Second

MOTOROLA MEMORY DATA
7-16

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM10143
MECL
8 x 2 MULTIPORT REGISTER FILE
(RAM)

8

The MC10143 is an 8 word by 2 bit multipart register file (RAM)
capable of reading two locations and writing one location simultaneously. Two sets of eight latches are used for data storage in
'
this LSI circuit.

X

2 MUL TIPORT REGISTER
FILE (RAM)

WRITE
A write occurs on the positive to negative transition ofthe clock.
Data is enabled by having the write enable (of each bit to be
written) low when the clock transition is made. The written information is seen at the output on the negative to positive clock
transition provided the read enable (of each bit) is at a low level.
To inhibit a bit from being written. the write enable of that bit
must be at a high level when the clock goes to a low state and
must remain high until clock goes high. The operation ofthe clock
and write enables can be reversed. While the clock is low. a positive to negative transition of the write enable will write into the
bit addressed by At;rA2. The data is seen at the output on the
negative to positive transition of the clock. provided the read
enable is low.

L SUFFIX
CERAMIC PACKAGE
CASE 623

READ

•

When the clock is high any two words may be read out simultaneously. as selected by addresses 80-92 and Co-C2. including
the word written during the preceding half clock cycle. When the
clock goes low the addressed data is stored in the slaves. level
changes on the read address lines have no effect on the output
until the clock again goes high. Read out is accomplished at any
time by enabli.ng output gates (80-91). (Co-C1).
tpd:
CLock to Data out = 5 ns (typ)
(Read Selected)
Address to Data out = 10 ns (typ)
(Clock High)
Read Enable to Data out = 2.8 ns (typ)
(Clock high. Addresses present)
Po = 610 mW/pkg (typ no load)
TRUTH TAeLE
·MODE

INPUT

··Clock
Write
Read

WEo WEI

01

Rt:s Rl'c oSo OSl

oco OCI

L ->ti
H

L

L

H

H

H

H

L

L

¢

<>

<>

L

L

H

H

L
H



L




H

Read

H"'t-

Read

<>

L-+H~

H

<>
<>
H

Write
Read

L ....H
H

L


L


..

DO

OUTPUT

<>



L

H

H

H

L

L

H

H

H
L

H
L

L
L

H
L
H

L
H
H
H

L

L

L

H

L

Note. Clock occurs _quentlally through Truth Table

• Note. Ao-A2, B0-82. and CO-C2 are al( set to same address location
throughout Table.
t/) = Don't Car.

MOTOROLA MEMORY DATA
7-16

PIN ASSIGNMENT

VCCO

VCC

OB,

VCC,

OBo

OC,

REB

OCo

B2

moc

Bo

Clock

B,

C2

~,

Co

WEo

C,

DO

A,

D,

Ao

VEE

A2

MCM10143

BLOCK DIAGRAM

4

REB 0------------------------------------------,

BO o--:---.!
B1

B20--"---.!

~----'

aBO

WEo
DO
Clock

AO
A1
A2

WE1
01

10
19
14
15
13

11

DC1
Co
C1
C2

17

16
18
aco

REc

20

MOTOROLA MEMORY DATA

7·17

•

MCM10143

ABSOLUTE MAXIMUM RATINGS
Rltlng
Power Supply Voltage (Vee = 01
Base Input Voltage (Vee = 01
Output Source Current - Continuous
- Surge
Junction Operating Temperature

Symbol

Vllu.

vee

-8toO

Vin

o to Vee
< 50
< 100
< 165
-55 to +150

10
TJ
Tstg

Storage Temperature Range

Unit
Vdc
Vdc
mAdc
°e
°e

Permanent devIce damage may occur If ABSOI.UTE MAXIMUM RATINGS are exceeded.

ELECTRICAL CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

De TEST VOLTAGE VALUES
(Volts)
Test
T emparltur.
oOe
+25 0 C
+75 0 e

VIHmax

VILmin

VIHAmin

VILAmax

VEe

-0.840
-0.810
-0.720

-1.870
-1.850

-1.145
-1.105

-1.490
-1.475

-1.830

-1.045

-1.450

-5.2
-5.2
-5.2

SWITCHING CHARACTERISTICS (TA = O· to + 75·C, VEE = - 5.2 Vdc

:t

are terminated through a 50-ohm resistor

to -2.0 volts.

5%1

DoC

+25 DC

+ 75°C

Characteristics

Symbol

Min

Max

Min

Typ

Max

Min

Max

Unit

Power Supply Drain Current

IE

-

150

-

118

150

-

150

mAdc

-

245
200

-

-

245
200

Input Current
Pins 10, 1" 19
All other pins

II

Each MECL Memory circuit has been deSigned to meet the de and ae specifications
shown in the test table, after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs

Switching Tim~s Q)
Read Mode
Address Input
Read Enable
Data
Setup
Address
Hold
Address

/JAdc

linH

-

-

-

-

-

245
200
ns
15.5

HJ

4.5
1.2
2.0

5.5

-

-

-

-1.5

-4.5

-

-

-

7.0
1.0
8.0
5.0

4.0
-2.0
5.0
2.0

-

-

5.5
1.0
1.0
1.0

2.5
-2.0
-3.0
-2.0

-

-

-

-

8.0

5.0

-

-

-

1.1

4.2

1.1

2.5

4.0

1.1

4.5

4.0
1.1
1.7

15.3
5.3
7.3

4.5
1.2
2.0

10

14.5

tRE-QB+
tClock+QB-

3.5
5.0

5.0

tsetup(B -Clock-I

-

-

8.5

thold(Clock-B+)

-

-

Setup
Write Enable
Write Disable
Address
Data
Hold

tsetupIWE-Clock+1
tsetup(WE+Clock-1
tsetup(A -Clock +1
tsetUl>{D -~Iock +1

-

-

Write Enable
Write Disable
Address
Data

thold(Clock-WE+1
thold(Clock +WE-I
thold(Clock + A +1
thold(Clock +0+1

-

'B ±. OB ±

5.5
7.6

Write Mode

Write Pulse Width
Rise Time, Fall Time
(20% to 80%1

PWWE
t r • tf

-

-

-

-

(DAC timing figures do not show all the necessary presetting conditions.

MOTOROLA MEMORY DATA
7-18

-

-

-

-

-

MCM10143

READ TIMING DIAGRAMS
FIGURE 1

Enable

FiE

t4

'"'~+1

Q

Data
(Addre.. Selected)

FIGURE 2

,""a.-

-~r-------------

Q

FIGURE 3

------------------:

Clock

Setup and Hold

CO.:.

k----------1

'Clock+QB-

--m----[~~.:~~~,~:d--m---

FIGURE 4

WRITE TIMING DIAGRAM
Enable Setup

WI'

FIGURE 5

Cto,-",

Enable Hold

FIGURE6

WE

Clock

FIGURE 1

FIGURE 8

Address

FIGURE9

Clock _ _ _ _ _ _ _ _ _ _...J

. MOTOROLA MEMORY DATA
7-19

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCMIOl44
MECL
256 x '·BIT RANDOM ACCESS MEMORY

256 X 1·BIT
RANDOM ACCESS
MEMORY

The MCM10144 is a 256 word xl-bit Read/Write Random
Access Memory. Data is accessed or stored by means of an 8-bit
address decoded on chip. It has a non-inverting data out, a separate
data in line and 3 active-low chip select lines. It has a typical access
time of 17 ns and is designed for high-speed scratch pad, control,
cache, and buffer storage applications.
•

Typical Address Access Time = 17 ns

• Typical Chip Select Access Time = 4.0 ns
• Operating Temperature Range
•

=0 0

to +750 C

Open Emitter Output Permits Wired-OR for Easy Memory
Expansion

•

50 kn Input Pulldown Resistors on Chip Select

•

Power Dissipation Decreases with Increasing Temperature

•

Fully Compatible with MECL 10,000 Logie Family

LSUFRX
CERAMIC PACKAGE
CASE 620

• 'Pin.for-Pin Replacement for Fl 041 0
PIN ASSIGNMENT

AO

•

BLOCK DIAGRAM

VCC

Al

DOUI

A2

WE

A3

csr

A7

CS2

A6

CS3

AS

A4

AO
A1
A2
A3
"4

.' .
..! '"

PIN NOTATION

';::

2

3
4
9

!I:.

~

¥
",0

"'N
«t:!

"':::
c ,
«01
a.=
·c 10

14

0

13

~:;;

"'l;

WE

es

Chip Select Input

AO thru A7

Address Inputs

Din
D out
WE

Oata Input
Oata Output

Write Enable Input

°In

TRUTH TABLE

~

Vee

= Pin 16

vee'" Pin 8

A5

A6

A1

cs·

WE

Din

Dout

Wrlie "0"

L

L

L

L

Write "1"

L

L

H

L

R..d

L

H

~

0

DI..bled

H

~

~

L

·cs • Clil + Cli2 + Ciif

MOTOROLA MEMORY DATA
7·20

OUTPUT

INPUT

MODE

~

-

Don't Care.

MCM10144

The operating mode of the RAM (CS inputs low) is
controlled by the WE input. With WE 'low the chip is
in the write mode-the output is low and the data present
at Din is stored at the selected address. With WE high the
chip is in the read mode-the data state at the selected
memory location is presented non-inverted at Dout '

FUNCTIONAL DESCRIPTION:

The MCM10144 is a 256 word x I-bit RAM_ Bit selection is achieved by means of an 8-bit address AO thru A7_
The active-low chip select allows memory expansion up
to 2048 words. The fast chip select access time allows
memory expansion without affecting system performance.

ABSOLUTE MAXIMUM RATINGS
Rltlng
Power Supply Voltage (Vee: 0)
B.se Input Voltage (Vee

=0)

Output Source Current - Continuous
- Surge
Junction Operating Temperature

Storage Temperature Range

Symbol

Value

Unit

vEE

-8toO

Vde

Vin

o to VEe

Vdc

10

<50
<100

mAde

TJ

< 165

°e

T stg

-55 to +150

°e

Permanent devle. damage may occur If ABSOLUTE MAXIMUM RATINGS are ••coeded.
DC TEST VOLTAGE VALUES
(Volts)
TIS!

Temperature

VIHmax

VILmin

VIHAmin

VILAm••

VEE

oOe

-0.840

-1.870

-1.145

-1.490

-5.2

+25 0e

-0.810

-1.850

-1.105

-1.475

-5.2

ELECTRICAL CHARACTERISTICS

+750 e

-0.720

-1.830

-1.045

-1.450

-5.2

Each MECL Memorv circuit has been

de~

signed to meet the de and ae specifications
shown in the test table. after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor
to -2.0 volts.
MeM10144 Test Limits
oOe
DC Characteristics

Power Supply Drain Current

+750 e

+250 e

Symbol

Min

Max

Min

Ma.

Min

Max

Unit

lEE

-

130

-

125

-

120

mAde

Conditions
Typ IEE@250e

=90 mA

All outputs and inputs open.
Measure pin B.
Input Current High

lin H

-

220

-

220

-

220

"Ade Test one input at a time. all

ott)er ilJputs are open.
Input Current Low

lin L

0.5

-

-

0.5

0.3

-

Vin" VIH.
"Adc Test one input at a time, all

other. inputs are open.
Logic "I"

VOH

-1.000 -0.840

-0.960

-0.810

-0.900

-0.720

Vde
Vde

Vin" VIL·
Load 50 n to -2.0 V

Output Voltage
Logic "0"

VOL

-1.870

-1.665

-1.850

-1.650

-1.830

-1.625

Logic "I"
Threshold Voltage

VOHA

-1.020

-

-0.980

-

-0.920

-

Logic "0"
Threshold Voltage

VOLA

-

-1.645

-

-1.630

-

-1.605

Output Voltage
Vdc ,Threshold testing is performed

and guaranteed on one input at

MOTOROLA MEMORY DATA

7-21

Vde

a.time. Vin " VIHA or VILA.
Load 50 n to -2.0 V.

II

MCM10144

SWITCHING CHARACTERISTICS (TA· 0 0 to +750 C vEE =-5 2 Vdc -+ 5%' Output Load see Figure l' see Note 1 & 3)
Characteristic

Min

Symbol

Read Mode
Chip Select Access Time
Chip Select Recovery Time
Addr..s Access Time
Write Mode
Write Pulse Width
DIfta Setup Time Prior to Write
Dat. Hold Time After Write
Address Setup Time Prior to Write
Addr..s Hold Time Aft.r Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Diseble Time
Write Recovery Time
Rise and Fall Time
Output Rise end Fall Time
Output Rise and Fall Time
Capacitance
Input Capacitance
Output Capacitance

Test Limits
Typ
MIX
10
10
26

tACS
tRCS
tAA

2.0
2.0
7.0

4.0
4.0
17

tw
tWSD
tWHD
tWSA
twHA
tWSCS
tWHCS
twS
tWR

25
2.0
2.0
8.0
0.0
2.0
2.0
2.5
2.5

6.0
-3.0
-3.0
0
-4.0
-3.0
-3.0
5.0
5.0

10
10

ns
ns
ns
ns
ns
ns
ns
ns
ns

t r• tf
t,. tf

1.5
1.5

3.0
3.0

7.0
5.0

ns
ns

-

4.0
7.0

6.0
8.0

pF
pF

-

-

- Conditions

Unit

ns
ns
ns

See Figur.. 2 and 3.
Measured from 50% of input to 50% of
output. Sao Nota- 2.

tWSA =8.0 ns
Measured at 50% of input to 50% of

output.
tw = 25 ns. Se. Figure 4.

Measured between 20% and 80% points.

Cin

-

Cout

When driven from Address inputs.
When driven from ~ or WE" inputs ..

Notes: U) Contact your Motorola Sales Representative for detail~ if extended temperature aperation is desired.
(2) 'The ma)(imum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
(3) For proper use of MECL Memories in 8 system enVironment. consult: "MECL System Design Handbook."

FIGURE 1 - SWITCHING TIME TEST CIRCUIT

•

VCC = Gnd

r---------l~----,
I

!
I
I

i
I
I

I
I
I
I
I
I
I

_51
1
2
3
4
9
10
11
12

61

7

INPUT LEVELS

AQCS'I C!2 CS3
A1
A2
A3

tr

A4
A5

As

Dout

A7

15

t,:

I1- 2.)

RT=500
CL" 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 psIpF for capacitive load up to 50 pF

0V

13

Din

WE

jt4

= tf = 2.0 ns typo

All timing measurements referenced to 50% of input levels.

I
I
I
I

MOTOROLA MEMORY DATA
7-22.

MCM10144

FIGURE 2 - CHIP SELECT ACCESS TIME

°out

FIGURE 3 - ADDRESS ACCESS TIME

Address

Dout

FIGURE 4 - WRITE MODE

•

Address

D out

14----tWSA

MOTOROLA Mi:MORY DATA
7-23

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCMIOl45
64-BIT REGISTER FILE
(RAM)

MECL

The MCM10145 is a 64-Bit RAM organized as a 16 x 4 array.,
This organization and the high speed make the MCM10145 particularly useful in register file or small scratch pad applications. Fully
decoded inputs, together with a chip enable, provide expansion
of memory capacity. The Write Enable input, when low, allows
data to be entered; when high, disables the data inputs. The Chip
Select input when low, allows full functional operation of the
device; when high, all outputs go to a low logic state. The Chip
Select, together with open emitter outputs allow full wire-ORing
and data bussing capability. On-chip input pulldown resistors
allow unused inputs to remain open.
• Typical Address Access Time = 10 ns
• Typical Chip Select Access Time' = 4.5 ns
• Operating Temperature Range = 00 to +750 C
• 50 k!l Pulldown Resistors on All Inputs
• Fully Compatible with MECL 10,000
• Pin-for-Pin Compatible with the Fl0145

64-BIT REGISTER
FILE

(RAMI

L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN ASSIGNMENT

BLOCK DIAGRAM

ao

a1

a2

a3

•
AO

A1

Q1

Vce (Gnd)

QO

Q2

CS

Q3

01

WE

DO

03

A3

02

A2

AO

VEE

A1

10

9

PIN NOTATION

..

cs

Chip Select Input

AOthru A3
OOthru 03
aOthru Q3

Oata Inputs
Data Outputl

EO

WE

Write Enable Input

.., .
:::~

,ll ~

Addre.. Inputs

.'"

A2

,,'
,,~

«~

A3

TRUTH TABLE

6

MODE

INPUT

CS

L"T""__r -_ _-r-_ _....-J-"";';'-o

D1

D2

WE

MOTOROLA MEMORY DATA
7-24

OUTPUT
Dn

an
L

Wrlta"O"

L

L

L

Write "1"

L

L

H

L

Read

L

H

II>

a

OIHbled

H

II>

II>

L

", .. Don·tC.....

D3

M

MCM10146

FUNCTIONAL DESCRIPTION:
The MCM10145 is a 16 word x 4·bit RAM. Bit selec·
tion is achieved by means of a 4·bit address AO thru A3.
The active·low chip select allows memory expansion up
to 32 words. The fast chip select access time allows
memory expansion without affecting system performance.

The operating mode of the RAM (CS input lowl is
controlled by the WE input. With WE low the chip is
in the write mode-the output is low and the data present
at Dn is stored at the selected address. With WE high the
chip is in the read mode-the data state at the selected
memory location is presented non·inverted at On.

ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage (Vee = 01

VEE

Value
-8 to 0

Base Input Voltage (Vee - 01

Vin

o to VEE

Vdc

Output Source Current - Continuous

10

mAde

TJ

< 50
< 100
< 165

T stg

-55 to +150

°e

Symbol

Rating

- Surge

Junction Operating Temperature
Storage Temperature Range

Unit

Vdc

°e

Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.

De TEST VOLTAGE VALues
(Voltsl
T ..t

Temperature

VIHmax

VILmin

VIHAmin

VILAmax

Vee

oOe

-0.840

-1.870

-1.145

-1.490

-5.2

+25 0 e
+7s o e

-0.810

-1.850

-1.105

-1.475

-5.2

-0.720

-1.830

-1.045

-1.450

-5.2

ELECTRICAL CHARACTERISTICS
Each MECL Memory circuit has been deSigned to meet the de and ae speCifications
shown in the test table, after thermal equi-

librium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor
to -2.0 volts.
MCM10145 Test limits
oOe

DC Characteristics

Symbol

Min

+7SoC

+250 e
Max

Max

Unit

120

mAde

-

220

IJ.Adc

-

0.3

-

-0.960

-0.810

-0.900

-0.720

-1.665

-1.850

-1.650

-1.830

-1.625

Vdc

-1.020

-

-0.980

-

-0.920

-

Vdc

-

-1.645

-

-1.630

-

-1.60S

Max

Min

Power Supply Drain Current

lEE

Input Current High

lin H

-

220

-

220

Input Current Low

IlnL

0.5

-

0.5

Logic "1"
Output Voltage

VOH

Logic "0"
Output Voltage

VOL

-1.870

Logic "1"
Threshold Voltage

VOHA

Logic "0"
Threshold Voltage

VOLA

130

Min

125

Conditions
Typ lEE @25 0 e = 90 mA
All outputs and inputs open.
Measure pin 8.

Test one input at a time, all
other inputs are open.
Vm = VIH.
"Adc Test one input at a time, all
other inputs are open.
Vin VIL.
Vdc Load 50 n to -2.0 V
0

-1.000 -0.840

MOTOROLA MEMORY DATA
7-25

Threshold testing is performed
and guaranteed on one input at
a
time. Vin = VIHA or VILA.
Vdc
Load 50 n to -2.0 V.

II

MCM10145
SWrrCHING CHARACTERISTICS (TA
Charactaristic
Read MOde
Chip salect A..... Time '
Chip salect Recoverv Time
Addres. Ace... Time
Write Mode
Write Pulse Width
Data satup Time Prior to Write
Date Hold Time After Write
Address Setup Time Prior to Write
Addre•• Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time

Write Recovery Time
Chip Enable Strobe Mode
Data Setup Prior to Chip Select
Write Enable Setup Prior to Chip
Select
Address Setup Prior to Chip Select
Data Hold Time After Chip Select
Write Enable Hold Time After Chip
Select
Address Hold Time After Chip Select
Chip Select Minimum Pulse Width

Rise and Fall Time
Address to Output
CS to Output
Capacitance
Input Capacitance
Output Capacitance

= 0° to + 75OC, VEE = - 5.2 Vdc
ott L,m,tI
Typ

+
- 5°; Output Load see Figure 1; see Note 2.)

Max

Unit

4.5
5.0
10

8.0
8.0
15

no

-

-

-6.0
0
1.0
-3.0
-5.0
-6.0
6.0
5.0

8.0
8.0

Symbol

Min

tACS
IRCS
tAA

2.0
2.0
4.0

tw
twso
tWHO
tWSA
tWHA
tWSCS
tWHCS
tws
tWR

8.0
0
3.0
5.0
1.0
0
0
2.0
2.0

tcso
tcsw

0
0

-6.0
-3.0

-

tCSA
tCHO
tCHW

0
2.0
0

-3.0
-1.0
-6.0

tCHA
tcs

4.0
18

-1.0
,12

tt

tr,tf

1.5
1.5

Cin

-

Cout

-

n.
ns

Conditio..
See Figures 2 end 3.
Measured from 60% of input to 50% of
output. See Note 1 .

n.
ns
n.
n.
n.
n.
ns
ns
ns

twSA = 5 n.
Measured at 50% of input to 60% of
output.
tw a 8 n•. sae Figure 4.

-

ns
n.

Guaranteed but not tested on standard
product. See Figure 6.

-

-

ns
ns
n.

--

n.
n.

3.0
3.0

7,0
5.0

n.
n.

4.0
5.0

6.0
8.0

pF
pF

-

Measured between 20% and 80% points.
t r•

Notes.
1. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
2. For proper use of MECl Memories in a system environment, consult MECL System Design Handbook.

Vcc
FIGURE 1 - SWITCHING TIME TEST CIRCUIT

1----,
I
I
~

I

Input Pulse
t r == tf =: 2.0 ± 0.2 ns
(20 to 80%)

I
i
I

VIH • -0.9 V

VIL=-1.7V

I

I

1
AO

CE 00

I
I

AI
A2

01

A3

I

I

DO
01

02

02
03 _
03
WE

I

I

I

I

L ____ .J

Fi·"~
LE:

Unused outputs connected to a 50-ohm resistor to ground.
A II tim Ing measurements referenced to 50% of input levels.
RT' 50 n
CL '" 5.0 pF (Including Jig and Stray Capacitance)
Delay should be derated 30 ps/pF for capacitive loeds up to 50 pF.

MOTOROLA MEMORY DATA
7-26

MCM10145

FIGURE 2 - CHIP SELECT ACCESS TIME

FIGURE 3 - ADDRESS ACCESS TIME

Address

Cout

FIGURE 4 - WRITE MDDE

Address

Oout

•

I+----'WSA

FIGURE 5 - CHIP ENABLE STROBE MODE

A
'CSD

'CHA

----

Din

'CHW

Vi

'CSA

'cs

CS

MOTOROLA MEMORY DATA
7-Zl

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM10l46
1024 x 1-81T RANDOM ACCESS MEMORY

MECL

The MCM10146 is a 1024-bit ReadlWrite Random Access Memory organized 1024 words by 1 bit. Data is selected or stored by
means of a 10-bit address (AO through A9) decoded on the chip.
The chip is designed with a separate data in line, a non-inverting
data output, and an active-low chip select.
This device is designed for use in high-speed scratch pad, control, cache and buffer storage applications.

1024 X 1-BIT
RANDOM ACCESS
MEMORY

•
•
•
•

Fully Compatible with MECL 10,000
Temperature Range of O· to 75·C (see note 1)
Emitter-Follower Output Permits Full Wire-DRing (see note 3)
Power Dissipation Decreases with Increasing Temperature

• Typical Address Access of 24 ns
• Typical Chip Select Access of 4.0 ns

L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN DESIGNATION
CS

Chip Select Input

AOto A9

Address Inputs
Data Inputs
Data Output
Write Enable Input

Din
Dout
WE

•

ORDERING INFORMATION
Suffix Denotes
MCM10146

-

L Ceramic Dual-In-Llne Package

-

F Caramlc Flat Package

PIN ASSIGNMENT
BLOCK DIAGRAM
VCC

Dout

AO

2

A1
A2

4

"

~
,,:::
c ,

0

" ¥

"ID
13':

-ee.

o •
;:.l!

A3
A4

.!i ...

""

6

13

AO

Din

Al

es

A2

WE

A3

A9

M

AS

AS

A7

VEE

A6

WE

';: «I

;:;;

'" '
SID

0

15

Din

TRUTH TABLE
MODE

INPUT
CS

Write "0"
VEE == Pin 8

A5

A6

A7

AS

A9

7-28

OUTPUT
Dout
L

~

~

L

L

H

Reed

~

H

Disabled

H

•

t/J .. Don't Care.

MOTOROLA MEMORY DATA

Din

L

Write "'"

Vee'" Pin 16

WE

••

L
Q

L

MCM10146

FUNCTIONAL DESCRIPTION:
This device is a 1024 x 1-bit RAM_ Bit selection is achieved by
means of a 10-bit address, AO to A9_
The active-low chip select is provided for memory expansion up
to 204B words_
The operating mode of the RAM (CS input low) is controlled by
the WE input_ With WE low, the chip is in the write mode, the output, Dout, is low and the data state present at Din is stored at the
selected address_ With WE high, the chip is in the read mode and the
data stored at the selected memory location will be presented noninverted at Dout . (See Truth Table)

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Power Supply Voltage IVee = 0)

VEE

Base Input Voltage (Vee - 0)

Vin
10

Output Source Current - Continuous

Value
-8 toO

TJ
T stg

Storage Temperature Range

Vde

o to VEE

Vde

< 50
< 100
< 165

mAde

-55 to +150

°e

- Surge

JunctioR.Operating Temperature

Unit

°e

De TEST VOLTAGE VALUES
(Volts)
Test

Temperature

VIHmax

V'Lmin

VIHAmin

VILAma.

VEE

oOe
+25 0 e

-0.840

-1.870

-1.145

-1.490

-5.2

-0.810

-1.850

-1.105

-1.475

-5.2

+75 0 e

-0.720

-1.830

-1.045

-1.450

-5.2

ELECTRICAL CHARACTERISTICS
Each MECL Memory circuit has been de-

signed to meet the de and ae specifications
shown in the test table. after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500linearfpm is maintained. Outputs
are terminated through a 50-ohm resistor
to -2.0 volts.
MeM10146 Test Limits
oOe

DC Characteristics
Power Supply Drain Current

Symbol

Min

Ma.

Min

150

lEE

+750 C

+250 C

Ma.

Min

145

Ma.

Unit

125

mAde

Input Current High

lin H

-

220

-

220

-

220

Input Current Low

lin L

0.5

-

0.5

-

0.3

-

Conditions
Typ lEE @250C- 100 mA

All outputs and inputs open.
Measure pin 8.
!tAde Test one input at a time, all
other inputs are open.
Vin=VIH.
!tAde Test one input at a time, all

other inputs are open.
Logic "1"
Output Voltage

VOH

-1.000

-0.840

-0.960

-0.810

-0.900

-0.720

Vde

Logic "0"

VOL

-1.920

-1.665

-1.900

-1.650

-1.880

-1.625

Vde

Logic "'"
Threshold Voltage

VOHA

-1.020

-

-0.980

-

-0_920

-

Vde

Logic "0"
Threshold Voltage

VOLA

-

-1.645

-

-1.630

-

-1.605

Vde

Vin= VIL·
Load 50 n to -2.0 V

Output Voltage

MOTOROLA MEMORY DATA
7-29

Threshold testing is performed
and guaranteed on one input at
a time. Vin = VIHA or VILALoad 50

n

to -2.0 V.

II

MCM10146

FIGURE 1 - SWITCHING TEST CIRCUIT AND WAVEFORMS
TESTING CONOITIONS

AO
Al

INPUT LEVELS

CS

A2

INPUT LEVELS

A3

A4
A5

MCM10146

Dou.I----...- - - . . . ,
tr = tf

A6
A7
AS
A9

<

All Timing Mealurements Referenced to 50% of Input Levels
VEE

CL .;;;; 5.0 pF Including Jig and Stray Capacitance

RT - 50

O.OI1' F

= 2.6 ns Typ,

n

For CapacItance Loading'" 50 pF. Delay Should be

I

Derated by 30 ps/pf

-2.0 V

Guaranteed with VEE: -5 2 Vdc •- 50% TA: OOC to 75°C (see NOle 11 Oulput Load see Figure 1
Characteristic

•

Symbol

MCM10146 Test Limits
Typ
Min
Max

Unit

Chip Select Access Time

8.0

7.0
7.0
29

n•

4.0
24

tw

25

20

-

ns

Data Setup Time Prior to Write

'wso
tWHO

0
0

-

Data Hold Time After Write
Address Setup Time Prior to Write

IWSA

5.0
5.0
8.0
2.0
5.0
5.0
2.8
2.8

0
0
0
0
5.0
5.0

ns
ns
ns
n.
ns

7.0
7.0

ns
ns
ns

1.5
1.5

2.5
4.0

4.0
8.0

ns
ns

-

4.0

-

7.0

5.0
8.0

pF
pF

Chip Select Recovery Time

'ACS
'RCS

2.0
2.0

Address Access Time

'AA

4.0

ns
ns

Rise and Fall Time
Output Rise and Fall Time
Output Rise and Fall Time
Capacitance
Input Lead Capacitance
Output Lead Capacitance
Notes:
(1)
(2)
(3)
(4)

'WSA : 8.0 ns.
Measured at 50% of input to 50% of output.

(To guarantee writing)

Address Hold Time After Write
Chip Select' Setup Time Prior to Write
Chip Select Hold Time After Write,
Write Disable Time
Write Recovery Time

Measured at 50% of input to 50% of output.
See Note 2.

See Figure 4.

Write Mode

Wrile Pulse Width

Conditions
See Figures 2 and 3.

Read Mode

'WHA
'WSCS
'WHCS
'WS
tWR
t r , tf
t r."
Cin
Cout

-

-

'W: 25 ns

Measured between 20% and 80% points.
When driven from a;: or"'iiVE' inputs.
When driven fr:om Address inputs.
Measured with a pulse technique.

Contact your Mot9ro1a SaleS Representative for details if extended temperature operati~n is desired.
The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
For proper use of MECL Memories in a system environment, consult: "MECL System Design Handbook."
Typical limits are at Vee = -5.2 Vdc, TA = 2SoC and standard loading.

MOTOROLA MEMORY DATA
7-30

MCM10146

FIGURE 2 - CHIP SELECT ACCESS TIME

t;.

o.~-tA-CS-"""\5

Chip Select

_tR_C_S__

Data Output

FIGURE 3 - ADDRESS ACCESS TIME

Address Input

A

Dout
Data Output

FIGURE 4 - WRITE STROBE MODE

Address Input

A

50%

Data Input

Write Enable

°out
Data Output

MOTOROLA MEMORY DATA
7-31

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM10147

128 x 1-BIT RANDOM ACCESS MEMORY

MECL

The MCM10147 is a 128-wordx l-bit Read/Write Random Access
Memory_ Data is accessed or stored by means of a 7-bit address
decoded on chip_ It has a non-inverting data out, a separate data in
line and 2 active-low chip select lines_ It has a typical access time
of 10 ns and is designed for high-speed scratch pads, control, cache,
and buffer storage applications_

128-BIT RANDOM ACCESS
MEMORY

•

Typical Address Access Time = 10 ns

• Typical Chip Select Access Time = 5_0 ns
•

Operating Temperature Range = 0 0 to +750 C

•

Open Emitter Output Permits Wired-OR for Easy Memory
Expansion

•

50 kU Input Pulldown Resistors on All Inputs

•
•

Power Dissipation Decreases with Increasing Temperature
Fully Compatible with MECL 10,000 Logic Family

•

Similar to Fl0405_

L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN ASSIGNMENT

•

VCC1

VCC2

AO

Dout

BLOCK DIAGRAM

Al
A2

A3
A4
A6

N_C_

PIN NOTATION

AO
Al
A2
A3

4

.
..,

.2

""
'"

11

WE

CS

Chip Select Input

AD thru A6

Address Inputs

Din

Data Input

D aut
WE

Write Enable Input

Data Output

E

"Ii

Din

TRUTH TABLE

~

VCC '
VCC2
A4

AS

A6

VEE

= Pin 1
= Pin 16
= Pin 8

OUTPUT

INPUT

MODE

CS·

WE

Din

Dout

Write "0"

L

L

L

L

Write "'"
Read

L

L

H

L

L

H

t/>

Q

Disabled

H

t/>

t/>

L

(/> - Don't Care.

MOTOROLA MEMORY DATA
7'-32

MCM10147

The operating mode of the RAM (CS inputs low) is
controlled by the WE input. With lIVE low the chip is
in the write mode-the output is low and the data present
at Din is stored at the selected address. With WE high the
chip is in the read mode-the data state at the selected
memory location is presented non-inverted at Dout .

FUNCTIONAL DESCRIPTION:
The MCM 10147 is a 128 word x I-bit RAM. 8it selection is achieved by means of a 7-bit address AO thru A6.
The active-low chip select allows memory expansion up
to 512 words. The fast chip select access time allows
memory eltpansion without affecting system performance.

ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply Vohage (Vee
Base Input Voltage (Vee

= 0)

= 0)

Output Source Current - Continuous

Symbol

V.lue

Unit

VEE

-8toO

Vde

Vin

o to VEE

Vde

10

< 50
< 100
< 165

mAde

-55 to +150

°e

- Surge

Junction Operating Temperature

TJ
T stg

Storage Temperature Range

°e

Permanent dev,ee damage may occur 'f ABSOLUTE MAXIMUM RATINGS are exceeded.
De TEST VOLTAGE VALUES
(Volts)
Test

Temperature

VIHmax

VILmin

VIHAmin

VILAmax

VEE

oOe

-0.840

-1.870

-1.145

-1.490

-5.2

+25 0 e
+750 e

-0.810

-1.850

-1.105

-1.475

-5.2

-0.720

-1.830

-1.045

.-1.450

-5.2

ELECTRICAL CHARACTERISTICS
Each MECL Memory circuit has been designed to meet the de and ae specifications
shown in the test table, after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater

than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor
to -2.0 volts.
MeMl0144 Test Limits
oOe

DC Characteristics
Power Supply Drain Current

+750 C

+250 C

Symbol

Min

Max

Min

Max

Min

Max

Unit

lEE

-

105

-

100

-

95

mAde

Input Current High

'in H

-

220

-

220

-

220

Input Current Low

lin L

0.5

-

0.5

-

0.3

-

Conditions
Typ lEE @ 250 e

= 80 mA

All outputs and inputs open.
Measure pin 8.
!JAde Test one input at a time, all
other inputs are open.
Vin = VIH.
!JAde Test one input at a time, all

other inputs are open.
Logic "1"

VOH

-1.000 -0.840

-0.960

-0.810

-0.900

-0.720

Vdc

Vin = VIL·
Load 50 n to -2.0 V

Output Voltage
Logie ··0··

VOL

-1.870

-1.665

-1.850

-1.650

-1.830

-1.625

Vde

Logic ""1""
Threshold Voltage

VOHA

-1.020

-

-0.980

-

-0.920

-

Vdc

Threshold testing is performed
and guaranteed on one input at

Logic ""0'·
Threshold Voltage

VOLA

-

-1.645

-

-1.630

-

-1.605

Vdc

a time. Vin = VIHA or VILA.
Load 50 n to -2.0 V.

Output Voltage

MOTOROLA MEMORY DATA
7-33

•

MCM10147

SWITCHING CHARACTERISTICS (TA zOo to +750 C VEE = -5 2 Vdc +- 5%· Output Load ••• Fig~re 1· ... Nota 1 "31
Characteristic

Symbol

Read Mode
Chip Select Access Time
Chip Select RICO.ery Time
Address Access Time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Addre.s Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time

Write Recovery Time
Rise and Fall Time
Output Rise and Fall Time

Min

Test Limits
Typ
MIIx

Unit

Conditions
See Figures 2 and 3.

tACS
tRCS
tAA

2.0
2.0
5.0

5.0
5.0
10

8.0
8.0
15

n.
ns
ns

Measured from 50% of input to 50% of
output. See Note 2.

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
tWR

8.0
1.0
3.0
4.0
3.0
1.0
1.0
2.0
2.0

6.0
-5.0
-2.0
0
0
·5.0
·5.0
5.0
5.0

-

tWSA

8.0
8.0

n.
n.
ns
ns
n.
n.
ns
n.
ns

tr.tf

1.5

3.0

5.0

n.

4.0
7.0

5.0
8.0

pF
pF

-

-

tw

= 4.0 ns

=8.0 ns. See Figure 4.

Measured at 50% of input to 50%
of output.

Measured between 20% and 80% points.

Capacitance
I"put Capacitance
Output Capacitance

-

Cin
C out

-

Notes: (1) Contact your Motorola Sales Representative for details if extended temperature operation is desired.
(2) The maximum Address Access Time is guaranteed to be the Wors,t.Case Bit in the Memory.
(3) For prop,er use of MECL Memories in a system environment, consult: "MECL System Design Handbook."

RGURE 1 - SWITCHING TIME TEST CIRCUIT

•

VCCI = VCC2 = Gnd

r---------J~----,
I
I

:
I

I

i
I
I

I
I
I
I
I
I
I
I

141
2
3
4
5
6
7
10

131

INPUT LEVELS

~B2
AI
A2
A3

tr

A.t
A5
A6

Ali timing measurements referenced to 50% of input levels.

15
Dout

RT=50n

tT

CLi

CL "" 5.0 pF (including jig and stray capacitancel
Delay should be derated 30 ps/pF for capacitive load up to ,50 pF

I
I

11

1- 2.OV
Din

WE

I
I
I
I

'---------'rr::
112

= tf = 2.0 ns typo

L5;VdC
VEE

MOTOROLA MEMORY DATA
7-34

MCM10147

FIGURE 2 - CHIP SELECT ACCESS TIME

Dout

FIGURE 3 - ADDRESS ACCESS TIME

Address

Cout

FIGURE 4 - WRITE MODE

II

Address

--t--I-'WHD

j4----..l-tWHCS
tWHA

°out

j 4 - - - - t WSA

MOTOROLA MEMORY DATA
7-35

------I

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCMIOl48

64 X 1 BIT RANDOM ACCESS MEMORY

MECL

The MCM10148 is a fast 64-word X 1-bit RAM. Bit selection
is achieved by means of a 6-bit address, AO through A5.
The active-low chip selects and fast chip select access time
allow easy memory expansion up to 256 words without affecting system performance. The operating mode (CS inputs low)
is controlled by the WE input. With WE low the chip is in the
write mode-the output is low and the data present at Din is
stored at the selected address. With WE high the chip is in the
read mode-the data state at the selected memory location is
presented non-inverted at Dout.

64 X 1-BIT
RANDOM ACCESS MEMORY

•
•
•
•

Typical Address Access Time of 1.0 ns
Typical Chip Select Access Time of 4.0 ns
50 kO Input Pulldown Resistors on All Inputs
Power Dissipation (420 mW typ @ 25°C) Decreases with
Increasing Temperature
• 50 kO Input Pulldown Resistors (420 mW typ) on All Inputs

L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN ASSIGNMENT

VCC1

•

AD

Dout

A1

N.C.

BLOCK DIAGRAM

WE

N.C.
A5

A4

PIN NOTATION

cs
D out

Chip Select Input
Address Inputs
Data Input
Data Output

WE

Write Enable Input

AO thru A6

Din

AO
AI

3
WE

A2
13

Din

TRUTH TABLE
INPUT

MOOE

A3

A4

A5

'CS
X

MOTOROLA MEMORY DATA
7-36

OUTPUT

cs·

WE

Din

Dout

Write "0"

L

L

L

L

Write"'"

L

L

H

L

Road

L

H

X

X

Disabled

H

X

X

L

= CSI + CS2

= Don't Care

MCM10148

ELECTRICAL CHARACTERISTICS
OOC
Ch...cterlatica
Power Supply Drain Current
Input Current High

Symbol

Min 1M."

lEE

-

1105

linH

-

J220

+26°C
Min

I Max

+76°C
95

Unit
mAde

-1 220 - J 220

p.Adc

-

1100

Min 1M."

- I

-55°C and +125°C test values apply to MC105xx devices only.

SWITCHING CHARACTERISTICS (Note 1)
MCM10148
Ch...cteriatica

Symbol

Read Mode
Chip Select Access Time
Chip Select Recovery Ti me
Address Access time
Write Mode
Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup TIme Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold TIme After Write
Write Disable Time
Write RecoveryTime

TA=Oto+76°C.
VEE = -6.2 Vdc ±5Of.
Min

M."

tACS
tRCS
tM

-

-

7.5
7.5
15

tw
twSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
twR

8.0
3.0
2.0
6.0
3.0
3.0
0
2.0
2.0

-

7.5
7.5

tr• tf

1.5

5.0

Cin
Cout

-

5.0
8.0

Rise and Fall Time
Capacitance
Input Capacitance

Output capacitance

Unit
ns

Measured from 60% of
input to 50% 01 output.
See Note 2.

ns

twSA= 6.0 ns
Measured at 50% of input
to 50% of output.
tW= 8.0 ns.

ns

Measured between 20%
and 80% points.

pF

Measured with a pulse
technique.

-

NOTES: 1. Test circuit characteristics: RT = 500. MCM1014B.
CL" 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capaciti"" load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
*To be determined; contact your Motorola representative for up-to-date information.

MOTOROLA MEMORY DATA
7.;rJ

Conditions

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

256 x 4-BIT PROGRAMMABLE
READ-ONLY MEMORY

MECL
1024·BIT PROGRAMMABLE
READ·ONLY MEMORY

This device is a 256-word x 4-bit field programmable
read only memory (PROM). Prior to programming, all
stored bits are at logic 1 (high) levels. The logic state of
each bit can then be changed by on-chip programming
circuitry. The memory has a single negative logic chip
,enable. When the chip is disabled (CS = high). all outputs
are forced to a logic 0 (low).

• Typical Address Access Time of 7.0 ns
• Typical Chip Select Access Time of 2,5 ns
• 50 kO Input Pulldown Resistors on All Inputs
• Power Dissipation (740 mW typ @ 25°C)
Decreases with Increasing Temperatl,lre

II

L SUFFI/C
CERAMIC PACKAGE
CASE 620

A12-Ll==.=
A2

A6

PIN ASSIGNMENT

3

AD ..

L..b-----l

Input

32)( 32

Decoder

Array and
Associated Drivers

S

VCP

AS 6

Al

A7

VCC
DO

A2

01

AO

CS

A6

02

7

A39

I"T-----j
Lfi-----j

Output
Decoder

1-_ _-+-_--'

A5

03

A7

A4

VEE

A3

A410

CSI3------------~~--~~---~~--,

11

12

I.

IS

03

02

01

DO

MOTOROLA MEMORY DATA
7-38

MCM10149*10

ELECTRICAL CHARACTERISTICSGl
oOC
+2SoC +7SOC
Symbol Min Max Min Max Min Max Unit
175 - 170 - 165 mAde
lEE
- 265 -- 265
265 ,/lAdC
'InH

Characteristic
Power Supply Drain Current

Input Current High

Forcing
Function

VIHmax

I

=

Parameter

OoC

VOHmax
VOHmin

VOHAmin

25°C®

75°C®

-0.840
-1.000

-0.810
-0.960

-0.720
-0.900

-1.020

-0.980

-0.920

VIHAmin

-1.130

-1.105

-1.045

VILAmax

-1.490

-1.475

-1.450

VOLAmax

-1.645

-1.630

-1.605

VOLmax

-1.665

-1.650

-1.625

VOLmin

1.870

1.850

1.830

'Nlmin

0.5

0.5

0.3

VILmin
Vilmin

=

NOTES: CD The MCM10149*10 is designed to meet the de specifications in the electrical
characteristics tables after thermal equilibrium has been established. The circuit
is in a test socket or mounted on a printed circuit board and transverse air flow
greater than 500 linear FPM is maintained. Outputs are terminated through a

50 n resistor to - 2.0 V.
® D-75OC temperature range, 50 n to -2.0 V.

SWITCHING CHARACTERISTICS (Note 11

Characteristics

Symbol

TA = 0 to 750(;,
VEE = -5.2 Vdc ±5%
Typ
Min
Max

Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time

tACS
tRCS
tAA

1.0
1.0
3.0

3.0
3.0
7.0

5.0
5.0
10

Rise and Fall Time

t r, If

1.0

2.0

5.0

Capacitance
Input Capacitance
Output Capacitance

Cin
Cout

-

-

-

-

Unit

Conditions

ns

Measured from 50% of input
to 50% of output. See Note 1.

ns

Measured between 20% and
80% points.

pF

Measured with a pulse
technique.

5.0
B.O

NOTES: 1. Test circuit characteristics: RT = 50 n
Cl """ 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capacitive load up to 50 pF
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. for proper use of MECl Memories in a system environment, consult MECL System Design Handbook.
4. VCP = Vee = Gnd for normal operation.

PROGRAMMING THE MCM10149*10
15.2 V, + 10 V - [ - 5.2 VJl. The rise time of this VCP
voltage pulse should be in the 1 - 10 p.s range, while
its pulse width (IW1) should be greater than 100 p.s but
less than 1 ms. The VCP supply current at + 10 V will
be approximately 525 rnA while current drain from VCC
will be approximately 175 rnA. A current limit should
therefore be set on both of these supplies. The current
limit on the VCP supply should be set at 700 rnA while
the VCC supply should be limited to 250 rnA. It should
be noted that the VEE supply must be capable of sinking
the combined current of the VCC and VCP supplies while
maintaining a voltage of -5.2 V ±5%.

During programming of the MCM10149*10, input
Pins 7, 9, and 10 are addressed with standard MECL
10K logic levels. However, during programming input
Pins 2, 3, 4, 5, and 6 are addressed with 0 V ,,;; VIH ,,;;
+ 0.25 V and VEE";; VIL ,,;; - 3.0 V. It should be stressed
that this deviation from standard input levels is
required only during the programming mode. During
normal operation, standard MECL 10,000 input levels
must be used.
With these requirements met, and with VCP = VCC
= 0 V and VEE = - 5.2 V ± 5%, the address is set up.
After a minimum of 100 ns delay, VCP (pin 1) is ramped
up to + 10 V ± 0.5 V (total voltage VCP to VEE is now

MOTOROLA MEMORY DATA
7-39

•

MCM10149*10

Coincident with. or at some delay after the VCP pulse
has reached its 100% level. the desired bit to be fused
can be selected. This is done by taking the corresponding output pin to a voltage of + 2.85 V ± 5%. It is to be
noted that only one bit is to be fused at a time. The
other three unselected outputs should remain terminated through their 50 ohm load resistor to - 2.0 V.
Current into the selected output is 5 mA maximum.
After the bit select pulse has been applied to the
appropriate output. the fusing current is sourced out
of the chip select pin 13. The 0% to 100% rise time of

this current pulse should be 250 ns max. It pulse width
should be greater than 100 /Ls. Pulse magnitude is
50 mA ± 5.0 mAo The voltage clamp on this current
source is to be - 6.0 V.
After the fusing current source has returned to 0 mAo
the bit select pulse is returned to its initial level. i.e .• the
output is returned through its load to - 2.0 V. Thereafter.
VCP is returned to 0 V. Strobing of the outputs to determine success in programming should occur no sooner
than 100 ns after VCP has returned to 0 V. The remaining
bits are programmed in a similar fashion.

t NOTE: units
For devices that program incorrectly. return serialized
with individual truth tables. Non compliance voids
warranty.

PROGRAMMING SPECIFICATIONS
The following timing diagrams and fusing informa·
tion represent programming specifications for the
MCM10149*10.
Vcc
Vee

= Pin 16 = 0 V
= Pin 8 = -5.2 V

Vcp

± 5%

J

= Pin 1

+ 10 V

Definition

Value

trl

--------1

twl

Pulse Width,
Programming Voltage

tOl

Delay Time,
Programming Voltage
Pulse to Bit
Select Pu Ise

;;'0

tw2

Pulse Width, Bit Select

;;. 100 f..!S

t02

Delay Time. Bit Select
Pulse to Programming
Voltage Pulse

;;'0

t03

Delay Time. Bit Select

;;. 1 f..!S

tr1 ___

~ tw1
~-

'

:;~:--±5%
+ __

+2.85V

•

Symbol

~-±O.5V
:
I "-- 0 V

I

Selected Output Open
Pin (11.12.14 or 151

Definitions and values of timing symbols are as
follows.

----+{ :
:

>--tw2

, :
tDl--1

t-+-

I

....J :I

~i--tD2

Chip Select Pin 13 0 mA - - - i - '

I
tD3

I--t04

Time.

;. 1 f..!s

Programming Voltage

~

_ _ _ SOmA
±5mA

~ise

;;. 100 f..!S

< 1 ms

Pulse to Programming

Current Pulse
tr3

The timing diagram is shown for programming
one bit. Note that only one bit is blown at a time.
All addressing must be done 100 ns prior to the
beginning of the V CP pulse, i.e.. V CP = O. V.
Likewise, strobing of the outputs to determine

tw3

success in programming should occur no sooner

t04

than 100 ns after VCP returns to 0 V.
Note that the fusing current is defined as
a positive current out of the chip select. pin 13.
A programming duty cycle of .;; 15% is to be
observed.

Rise Time, Programming

250 ns max

Current Pulse

Pulse Width,

;;. 100 f..!S

Programming
Current Pulse

Delay Time,
Programming Current

Pulse to Bit
Select Pulse

MOTOROLA MEMORY DATA

;;. 1 f..!s

MCM10149*10

MANUAL PROGRAMMING CIRCUIT
+5 V

+5 V

J'2oL r.l..----L-,

".

+5 V

a

Celev
1/2

Pulse Gen
in Single
Pulse Mode

Enable
Current

SN74LS123
Cp

Pulse

a

....r-L.-

a

>100,",s

Program
Enable

+5 V

+5 V

~
lN914
-5.2 V
(-6 V Clamp)

510
510
lN914
or Equiv.

100

-5.2 V

10.5 V

r--------e---o+5V
114

150
240

SN74LS38
180

•

+5 V
13
VCP

CS

A7
1.0 k
-5.2 V

11
A6

1.0.
-5.2 V

6

1.0 k
-5.2 V

10

03

A5
12
02

A4

680
-5.2 V

1.0 k
-5.2 V

MCM10149*10

9
A3

1.0.
-5.2 V

-5.2 V

1.0.
-5.2 V
1.0.
-5.2 V

14
01

3

680
-5.2 V

A2

1.0.
2

15
Al

C

Rotarv SW

DO

4
AO

16

MOTOROLA MEMORY DATA
7-41

680
-5.2 V

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCMI0149*25
256 x 4-BIT PROGRAMMABLE
REAO-ONL Y MEMORY

MECL
1024-BIT PROGRAMMABLE
READ-ONLY MEMORY

This device is a 256-word x 4-bit field programmable
read only memory (PROM). -Prior to programming, all
stored bits are at logic 1 (high) levels. The logic state of
each bit can then be changed by on-chip programming
circuitry. The memory has a single negative logic chip
enable. When the chip is disabled (CS = high). all outputs
are forced to a logic 0 (low).

L SUffiX

• Typical Address Access Time of 20 ns

CERAMIC PACKAGE
CASE 620

• Typical Chip Select AccessTime ot 8.0ns
• 50 k!llnput Pulldown Resistors on All Inputs
• -Power Dissipation (640 mW typ @ 26°C)
Decreases with Increasing Temperature

•

Al

2

A2

3

F SUFFIX
CERAMIC PACKAGE
CASE 650

PIN ASSIGNMENT
Input

Lfi-----j

Decoder

VCC

DO
01
CS

Ir-----I
-~~

__

~

OutPlit
DK~e.

~

02

-+___

__

03
A4
CSI3'--------------~~----~-r----~i-----,

11

12

D3

D2

A3

15

"

Dl

DO

MOTOROLA MEMORY DATA
7-42

MCM10149*25

ELECTRICAL CHARACTER ISTICS
Symbol Min Max Min Max MinlMax Unit
- 155 - 150 - 1145 mAde
265
265
1265 ",Adc

Characteristic
Power Supply Drain Current
Input Current High

-5S0C and +12SoC test values applv to Mel0Sxx devices only

Forcing

Function

!

VIHmax

OOC

VOHmax
VOHmin

-0.840
-1.000

-0.810
-0.960

-0.720
-0.900

VOHAmin

-1.020

-0.980
-1.105
-1.475
-1.630

-0.920
-1.045
-1.450
-1.605
-1.625

-1.130
-1.490

VIHAmin
VllAmax
VOLAmax
VOlmax
VILmin
VILmin

NOTES:

-

75°C CD

25°cG)

Parameter

VOLmin
INLmin

-1.645
-1.665
1.870
0.5

-1.650
-1.850
0.5

-1.830
0.3

CD 0-75°C lemperalure range, 50n 10 -2.0V.

SWITCHING CHARACTERISTICS (Note 1)

Characteristics
Read Mode
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
Rise and Fall Time

Symbol

Capacitance
Input Capacitance
Output Capacitance
NOTES.

1. Test

Circuit

characteristics. AT

MCM10149*25
TA = Oto +75"C,
VEE = -5.2 Vdc ±5%
Min
Max

lACS
IRCS
IAA
Ir,11

2.0
2.0
7.0
1.5

10
10
25
7.0

Cin
Cout

-

5.0
8.0

Unit
ns

Conditions
Measured from 50% of input
to 50% of output. See Nole 1.

ns

Measured between 20% and
80% points.

pF

Measured with a pulse
technique.

50 n, MCM10149.

CL ,.;;;; 5.0 pF (including jtg and stray capacitance)

Delay should be derated 30 ps/pF for capacitive load up to 50 pF

2. The maximum Address Access Time
3. For proper use of MECL MemOries

IS

In

guaranteed to be the Worst-Case Bit

In

the Memory.

a system enVironment, consult MECL System Design Handbook.

4. VCP = Vec ::. Gnd for normal operation.
*To be determined, contact your Motorola representative for up·to-date information.

PROGRAMMING THE MCM10149

a V and

t

VEE = - 5.2 V ± 5%, the address is set up. After
a minimum of 100 ns delay, VCP (pin 1) is ramped up to
+ 12 V ± 0.5 V (total voltage VCP to VEE is now 17.2 V,
+ 12 V - [ - 5.2 vI ). The rise time of this VCP voltage
pulse should be in the 1 - 10 j.IS range, while its pulse
width (tWl ) should be greater than 100 j.IS but less than
1 ms. The VCP supply current at + 12 V will be approximately 525 mA while current drain from VCC will be approximately 175 mAo A current limit should therefore be

During programming of the MCM 10149, input pins 7,
9, and 10 are addressed with standard MECL 10K logic
levels. However, during programming input pins 2, 3, 4,
5, and 6 are addressed with a V .;;; V IH';;; + 0.25 V and
VEE';;; V IL ';;; -3.0 v. It should be stressed that this
deviation from standard input levels is required only during
the programming mode. During normal operation, standard
MECL 10,000 input levels must be used.
With these requirements met, and with VCP = VCC =

MOTOROLA MEMORY DATA
7-43

•

MCM10149*25

After the bit select pulse has been applied to the appropriate output, the fusing current is sourced out of the
chip select pin 13. The 0% to 100% rise time of this current pulse should be 250 ns max. It pulse width should be
greater than 100 /IS. Pulse magnitude is 50 mA ± 5.0 mA.
The voltage clamp on this current source is to be - 6.0 V.
After the fusing current source has returned 0 mA, the
bit select pulse is returned to it initial level, i.e., the output
is returned through its load to - 2.0 V. Thereafter, VCP is
returned to 0 V. Strobing of the outputs to determine success in programming should OCcur no sooner than 100 ns
after VCP has returned to 0 V. The remaining bits are programmed in a similar fashion.

set on both of these supplies. The current limit on the
VCP supply should be set at 700 mA while the VCC supply should be limited to 250 mAo It should be noted
that the VEE supply must be capable of sinking the
combined current of the VCC and VCP supplies while
maintaining a voltage of - 5.2 V ± 5%.
Coincident with, or at some delay after the VCP pulse
has reached its 100% level, the desired bit to be fused can
be selected. This is done by taking the corresponding output pin to a voltage of + 2.85 V ± 5%. It is to be noted that
only one bit is to be fused at a time. The other three unselected outputs should remain terminated through their
50 ohm load resistor to - 2.0
into the selected

t

NOTE: For devices that program incorrectly, return serialized
units with individual truth tables. Non compliance voids
warranty.

/
PROGRAMMING SPECIFICATIONS
The following timing diagrams and

fusing

Definitions and values of timing symbols are

information represent programming specifications

as follows.

for the MCMl 0149.
Vee"" Pm 16 ,. 0 V

Symbol

VEE=P;n. =_5.2 V ' q 5 % ;~25VV
VCP-P,nl

tw1

tr,.....J
Selected Output Open -

II

PIn(11,12,14or15)

Rise Time,

twl

Programming Voltage
Pulse Width,
Programming Voltage

tOl

Delay Time,

OV

t

I

V
I

I~~t---

f-- t w2-..j

i
'D,-il-t-

+285 V
. 5%

i

I

+

;;. 100 /ols

<

1 ms

;;'0

Pulse to Bit
Select Pu Ise

.....-_-,+___ 50 mA

I

Value
;;. 1 /olS

Programming Voltage

t-II--tD2

ChIp Select Pm 13 0 m A . - - - + t,3

Definition

trl

tw2

Pulse Width, Bit Select

t02

Delay Time, Bit Select
Pulse to Programming
Voltage Pulse

t03

Delay Time, Bit Select
Pulse to Programming

tr3

Rise Time, Programming
Current Pulse
Pulse Width,

5mA

~w~ ~'D4

;;. 100 /ols
;;'0

;;. 1 /ols

Current Pulse

The timing diagram is shown for programming
one bit. Note that only one bit is blown at a time.
All addressing must be done 100 ns prior to the
beginning of the VCP pulse, i.e., VCP = 0 V.
Likewise, strobing of the outputs to determine

tw3

success in programming should occur no sooner

t04

250 ns max
;;. 100 /ols

Programming

than 100 ns after V CP returns to 0 V.
Note that the fusing current is defined as
a positive current out of the chip select, pin 13.
A programming duty cycle of .;; 15% is to be
observed.

Current Pulse
Delay Time,
Programming Current

Pulse to Bit
Select Pulse

FOR MANUAL PROGRAMMING CIRCUIT, SEE MCM10149*10

MOTOROLA MEMORY DATA

744

;;. 1 /ols

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM10152
MECL
256

x

1-BIT RANDOM ACCESS MEMORY

256 X 1-BIT

RANDOM ACCESS
MEMORY

The MCM10152 is a 256 word x 1-bit ReadIWrite Random
Access Memory _ Data is accessed or stored by means of an 8-bit
address decoded on chip_ It has a non-inverting data out, a separate
data in line and 3 active-low chip select lines_ It has a typical access
time of 11 ns and is designed for high-speed scratch pad, control,
cache, and buffer storage applications_
•

Typical Address Access Time = 11 ns

•

Typical Chip Select Access Time = 4_0 ns

•

Operating Temperature Range = 0 0 to +75 0 C

•

Open Emitter Output Permits Wired-OR for Easy Memory
Expansion

•

50 kfl Input Pulldown Resistors on All Inputs

•

Power Dissipation Decreases with Increasing Temperature

•

Fully Compatible with MECL 10,000 Logic Family

-

LSUFFIX
CERAMIC PACKAGE
CASE 620

PIN ASSIGNMENT

AO

BLOCK DIAGRAM

VCC

A1

Dout

A2

WE

A3

II

Din

m

A7

CS2

A6

CS3

A5

VEE

A4

PIN NOTATION

AO

~,

A1
A2
A3
A4

3

~
< ,

ID

.,,:::

~

«ID

'E~
;=;;

."
."

4

«

9

"Ec
;:

0

14

WE

13

Din

cs

Chip Select Input

AO thru A7

Address Inputs

Din

Data Input

°out

Data Output

WE

Write Enable Inp,ut

TRUTH TABLE
Vee

c

Pin 16

VEE'" Pin 8

A5

A6

A7

cs'

WE

Din

Dout

Write "0"

L

L

L

L

Write "'"

L

L

H

L

Road

L

H

Oisabled

H

= '"

'"

Q

·cs = CS1 + eS2 + CS3

MOTOROLA MEMORY DATA
7-46

OUTPUT

INPUT

MODE

(/J

'"

Don't Cara.

L

MCM10152

FUNCTIONAL D~ScRlptION:

The operating mode of the RAM (CS inputs lowl is
controlled by the WE input. With WE low the chip is
in the write mode-the' output is low and the data present
at Din is stored at the selected address. With WE high the
chip is in the read mode-the data state at the selected
memory location is presented non-inverted at Dout '

The MCM1Q152'is a 256 word x 1-bit RAM. Bit selection is achieved by means of an 8-bit address AO thru A7.
The active-low chip select allows memory expansion up
to 2048 words. The fast chip select access time allows
memory expansion without affecting system performance.

ABSOLUTE MAXIMUM RATINGS
.Rating
Power Supply Voltage (Vee
Base Input Voltage (Vee

=0)

=0)

Output Source Current - Continuous

Symbol

Value

Unit

VEe

.-8 toO

Vde

Vin

o to,VEE

Vde

10

< 50
< 100
< 165

mAde

55 to +150

°e

- Surge

Junction Operatif'9 Tempe.r~ture
Storage Temperature Range

TJ
T stg

°e

Permanent deVIce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
DC TE~T VOLTAGE VALUES
(Volts)
Test

Temperatura

VIHmax

VILmin

VIHAmin

VILAmax

VEE

oOe

-0.840

-1.870

-1.145

-1.490

-5.2

+250 e

-0.81'0

-1.850

-1.105

-1.4 75

-5.2

+750 e

-0.720

-1.830

-1.045

-1.450

-5.2

ELECTRICAL CHARACTERISTICS
Each MECL Memory circuit has been de-

signed to meet the de and ae specifications
shown in the test table. after thermal equi·
libriull,l has been established. The circuit

•

is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs
are terminated through a 50-ohm resistor
to -2.0 volts.
MeMl0152 Test Limits
+2So e

oOe

DC Ch.racteristics
Power Supply Drain Current.

Symbol

Min

Max
135

lEE

+150 e

Max

Min

Min

130

Max

Unit

125

mAde

Conditions
Typ lEE @ 250 e

=110 mA

All outputs and inputs open.
Measure pin 8.
Input Current High

lin H

-

220

-

220

-

Input Current Low

linL

0.5

-

0.5

-

0.3

Logic "1"
Output Voltage

VOH

-0.810

-0.900

-0.720

Vdc

Logic "0"
Output Voltage

VOL

-1.870

-1.665

-1.850

-1.650

-1.830

-1.625

Vdc

Logic "1"
Threshold Voltage

VOHA

-1.020

-

-0.980

-

-0.920

Logic "0"

VOLA

-

-1.645

-

-1.630

-

-1.605

Threshold testing is performed
and guaranteed on one input at
a
time. Vin '= VIHA or VILA.
Vdc

220

~Adc

Test one input at a time, all
other inputs are open.
Vin = VIH.

-1.000 -0.840

-0.960

Threshold Voltage

MOTOROLA MEMORY DATA
7-46

jlAdc Test one input at a time, aU
other inputs'are open.
Vin = VIL·
Load 50 n to -2.0 V

Vdc

Load 50

n

to -2.0 V.

MCM10152

SWITCHING CHARACTERISTICS ITA = 0° to +75 0 C VEE = -5 2 Vdc •- 5%· Output Load see Figure 1· see Not. 1 & 3.)
Test Limits

Symbol

Characteristic

Min

Typ

Ma.

Chip Select Access Time
Chip Select Recovery Time

Address Access Time

Conditions

Unit

Read Mode

'ACS
tRCS
tAA

2.0
2.0
7.0

4.0
4.0
11

7.5
7.5
15

ns
ns
ns

tw
tWSD
tWHD
tWSA
tWHA
tWSCS
tWHCS
tws
tWR

10
2.0
2.0
5.0
3.0
2.0
2.0
2.5
2.5

6.0
-3.0
-2.0
3.0
0
-3.0
-3.0
5.0
5.0

-

ns
n,

7.5
7.5

ns
ns
ns
ns
ns
ns
ns

tr,tf

1.5

3.0

5.0

ns

Cin
Cout

-

4.0
7.0

5.0
8.0

pF
pF

See Figures 2 and 3.
Measured from 50% of input to 50% of

output. See Note 2.

Write Mode

Write Pulse Width
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time Prior to Write
Address Hold Time After Write
Chip Select Setup Time Prior to Write
Chip Select Hold Time After Write
Write Disable Time
Write Recovery Time
Rise and Fall Time
Output Rise and Fall Time

-

-

tWSA = 5.0 ns
Measured at 50% of input to 50% of
output.
tw = 10 ns. See Figure 4.

Measured between 20% and 80% points.

Capacitance
I nput Capacitance

Output Capacitance

Notes. (1) Contact your Motorola Sales Representative for details if extended temperature operation is desired.
(2) The maximum Address Access TIme is guarant~ed to be the Worst-Case BIt
(31 For proper use of MECL Memones in a system environment. consult

FIGURE 1 -

VCC

~

In

the Memory.

"MECl System Design Handbook."

SWITCHING TIME TEST CIRCUIT

= Gnd

r---------l~----,
I

!
I
I

:
1
1

I

I
I
I
I
1

I

51

61

7

1 A~CS2CS3
2
AI
3
A2
4
A3
9
A.4
10
A5
15
11
A6
Dout
12
A7

I
I
I
I
1
1
I

INPUT lEVELS

I
1
1
1
1
1

lr

Din

WE
114

ns lyp.

All timing measurements referenced to 50% of input levels.

1

IRr

Cli

1
1
I :>
1-2.0 V
13

= tf = 2.0

=

RT=50n
Cl '" 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capaciiive load up to 50 pF

I
1
1

I

'---------.f1~~:

1-5~vdc
MOTOROLA MEMORY DATA
7-47

•

MCM10152

FIGURE 2 - CHIP SELECT ACCESS TIME

°out

FIGURE 3 - ADDRESS ACCESS TIME

Address

Oout

FIGURE 4 - WRITE MODE

II

Address

°out

1---- tWSA ----400j

MOTOROLA MEMORY DATA
7-48

Military Products
Military 4180
Military 6164
Military 6168
Military 6206
Military 6268
Military 62Jfl
Military 6288
Military 93415
Military 93422,
93L422,
93L422A
Military 93425

4K x 4 CMOS Cache Tag, 35/45 ns ...........
8K x 8 CMOS SRAM, 55/70 ns ..............
4Kx4 CMOS SRAM, 55/70 ns ..............
32Kx8 CMOS SRAM, 45/55/70/100 ns ......
4Kx4 CMOS SRAM, 35/45 ns ..............
64K x 1 CMOS SRAM, 35/45 ns .............
16K x4 CMOS SRAM, 35/45 ns .............
1024 x 1 TTL RAM, 60 ns, Open Collector .....
256 x 4 TTL RAM, 60 ns ....................
256 x 4 TTL RAM, 75 ns ....................
256 x 4 TTL RAM, 55 ns ....................
1024 x 1 TTL RAM, 60 ns ...................

MOTOROLA MEMORY DATA
8-1

8-3
8-5
8-10
8-15
8-17
8-22
8-27
8-32
8-36
8-36
8-36
8-41

II

CMOS Static RAMs

CMOS Cache Tag RAMs

1+5V. -55 to 125°CI

1+5 V. -55 to 125°CI

Organization

4Kx4

Part Number

8188-65/BRAJC
8188-66/BUAJC
8188-70/BRAJC
8188-70/BUAJC
~/BRAJC
~/BUAJC

8Kx8

16Kx4

84Kxl

32Kx8

6288-461 BRAJC
6288-461 BUAJC
6184-66/BXAJC
8184-661 BUAJC
8184-70/BXAJC
8184-70/ BUAJC
~/BXAJC

8288-36/BUAJC
6288-461 BXAJC
6288-46/BUAJC
6287-36/BXAJC
6287-36/BUAJC
6287-46/BXAJC
6287-46/BUAJC
8:108-46/BXAJC*
62D6-66/BXAJC*
8206-70/BXAJC*

A_11m.
' ... max)
66
66
70
70
36
36
46
46

66
66
70
70
35
36
46
46
36
35
46
46
46
66
70

Pine

Organization

:zo
:zo
:zo
:zo
:zo
:zo
:zo
:zo

4Kx4

Part Number

4180-36/BXAJC*
4180-46/BXAJC*

Ace_11m.
' ... maxl
36
46

Pine

22
22

*To be introduced

TTL RAMs
1+5V. -55 to 125D CI

28

Organization

32
28

258Kx4

32
22
22
22
22
22
22
22
22

1024 x 1

Part Number

93422/BWAJC
93L422/BWAJC
93L422A/BWAJC
93415/BEAJC
93415/BFAJC
93426/BEAJC
93426/BFAJC

*To be introduced

28
28
28

•
MOTOROLA MEMORY DATA
8-2

A_llme
'nemax)
60
75
66
46
46

46
46

Pine

22
22
22
16
16

16
16

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Military 4180
Advance Information

4K x 4 Bit Cache Address Tag
Comparator
The 4180 is a 16,384 bit cache address tag comparator organized as 4096 tags
of 4 bits, fabricated using Motorola's second generation high-performance
silicon-gate CMOS (HCMOS III) technology. The device integrates a 4K x 4
SRAM core with an on-board comparator for efficient implementation of a cache
memory.
The device has a ClR pin for flash clear of the RAM, useful for system
initialization.
The 4180 compares RAM contents with current input data. The result is either
an active high match level for a cache hit, or an active low level for a cache
miss.
The 4180 is available in 22 lead sidebraze packages.
•
•
•
•
•
•

Single 5.0 V ± 10% Supply
Fast Address to Match Time:
35/45 ns Max
Fast Data to Match Time:
15/20 ns Max
Fast Read of Tag RAM Contents: 35/45 ns Max
Flash Clear of the Tag RAM (ClR Pin)
Pin and Function Compatible with MK41H80

CASE 677-06
CERAMIC

PIN ASSIGNMENT
SIDEBRAZE

BLOCK DIAGRAM

MEMORY
MATRIX
128 ROWS
X 128 COlUMNS

Vi

OOO-OQ3 ---~'-------'

A4

1.

22

A5

2

21

PI>

3

20

A)

4

19

P VCC
~
~

A3

P2

AS

5

P AI
18 P fJJJ

A9

6

17

Al0

)

16

All

8

15

IT

9

14

Vi

10

13

~
~

Vss

11

12

~ MATCH

P Wi
P 003
P D02
DOl
000

COLUMN
DECOOER

PIN NAMES
AO-A 11 . . . . . . . . . Address Inputs
Vii. . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . Output Enable
CLR. . . . . . . . .. Flash Clear Input
MATCH . . . . .. Match (Hit) Output
DOa-DOl . . . . . . Data Input/Output
VCC . . . . . . +5.0 V Power Supply
VSS . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . No Connection

A)-All

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
8-3

II

MILITARY 4180

TRUTH TABLE

w

G

Wi

DQD-DQ3

Match

Mode

H
L
H
X

H
X
L
X

H
H
H
L

Compare Din
Din
Dout
High-Z

Valid
Assert
'Assert
Assert

Compare
Write
Read
Clear

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS
Rating
Power Supply Voltage
, Voltage Relative to VSS for Any Pin
Except VCC
Output Current

= 0 V)

Symbol

Value

Unit

VCC

-0.5 to +7,0

V

VinNout

-0.5to VCC+0.5

V

lout

40
20

mA

Match Output
1/0 Pins, Per 1/0

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of a'ny voltage
higher than maximum rated voltages to
this high-impedance drcuit.

Power Dissipation (TA = 25·C)

Po

1.0

W

Operating Temperature

TA

-55to +125

·C

Storage Temperature

Tstg

-65to +150

·C

Temperature Under Bias

Tbias

-55to +125

·C

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS afe exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDI~
TlONS. Exposure to higher than recommended voltages for extended periods of time
could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC

=

5.0 V ± 10%, TA

= - 55· to

+ 125·C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Referenced to VSS

=

•

0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

Input High Voltage

VIH

2.2

-

VCC + 0.3

V
V

Input Low Voltage

VIL

-0,5*

-

0.8

V

Max

Unit

Paramater

*VIL (mon) - -0,5 Vdc; VIL Imon) - -3.0 Vac (pulse wIdth" 20 ns) .

DC CHARACTERISTICS
Symbol

Min

Input Leakage Current (All Inputs, Vin = 0 to Vccl

Parameter

Ilkg(l)

-

±1.0

Output Leakage Current, Except Match Output (G = VIH, Vout = 0 to Vccl

Ilkg{O)

-

±1.0

Output Low Voltage (1/0 Pins: 10L = 8.0 mA, Match Output: 10L = 12 mAl

VOL

-

Output High Voltage (110 Pins: 10H = -4.0 mA, Match Output: 10H = -10mA)

VOH

2.4

AC Supply Current (lout = 0 mA, tAVAV = tAVQV max)

..

ICCA

.

.

p.A

p.A

140*

mA

0.4

V

-

V

*ICC active current for the clear cycle exceeds thiS specification. However, thiS IS a tranSient phenomenon and will not affect the power diSSipation of
the device. Good decoupling of the local power supply should always be used.

CAPACITANCE (f

= 1.0 MHz, dV = 3.0 V, TA = 25·C, Periodically Sampled Rather Than 100% Tested)

Characteristic
Input Capacitance

1/0 Capacitance
Match Output Capacitance

MOTOROLA MEMORY DATA

Symbol

Typ

Max

Unit

Cin

4,0

5.0

pF

Cout

5.0

7.0

pF

Cmatch

6.0

7.0

pF

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

1

Military 6164

8K X 8-Bit Fast Static
Random Access Memory

IJJJJIiJJI

The 6164 is a 65,536-bit static random access memory organized as 8192 words
of 8 bits, fabricated using Motorola's second-generation high-performance silicongate CMOS (HCMOS III) technology. Static design eliminates the need for external
clocks or timing strobes, while CMOS circuitry reduces power consumption and
provides greater reliability.
The chip enable pins (El and E2) are not clocks. Either pin, when asserted false,
causes the part to enter a low power standby mode. The part will remain in
standby mode until both pins are asserted true again. The availability of active
high and active low chip enable pins provides more system design flexibility than
single chip enable devices.
The 6164 is available in a 600 mil, 28-pin ceramic dual-in-line package, and a
32-terminal ceramic LCCC with .JEDEC standard pinout.
•
•
•
•
•
•
•
•

1

MPO

1111111

PIN ASSIGNMENT
NC
A12
A7
AS
AS

Single 5 V Supply, ± 10%
8K x 8 Organization
Fully Static - No Clock or Timing Strobes Necessary
Fast Access Time - 55, 70 ns (Maximum)
Low Power Dissipation - 660, 495 mW (Maximum, Active)
Fully TTL Compatible
Three-State Data Outputs
Output Enable (<3) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems

loA

A3
Iil
Al
I>fJ

DOD
DOl

D02

,1.
2
3

28
27
26
25
2.
23

4

5
6
7
8
9
10
11
12
13

VCC

Vi
E2
AS
AS
All

22

G

21
20

IT

19

18
17

16

AID
007
D06
DO'
DO.

Vss~ D03

CASE 733-04
CERAMIC

BLOCK DIAGRAM

CHIP CARRIER

~~§E~~1~8
4LJ LJ LI I , LJ LJ u 30

AS
A6
~VCC

A7
AS
A9

MEMORY ARRAY
1256 ROWS
256 COLUMNSI

~

VSS

AID

A6
A5
A.
A3
A2
A1
AD
NC

All

DOD

Al2

3 2 l..j 32 31 29~

J5

J6

1

J7
J8
J9
JlO

AS

2BC
27[
26[

A9
All
NC

25[
24L:

OE

311

23[:

EEl

::12

22[

DOl

~13 15 1617 181921 C
14r"1 rl n n n n n20

006

AlO

g §,~ ~ § g g

000
I/O CIRCUITS

CASE 766A-01
CERAMIC

007
COLUMN SElECT

PIN NAMES

Ei
E2

AO-A 12 . . . . . . . . . . . . Address

W
G

VIi .. . .. .. . .. ..
ft, E2. . . . . . . . . .

Write Enable
. Chip Enable
G .. .. .. .. .. . Output Enable
OQO-OQ7 . . . . . Data Input/Output
VCC. . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . No Connection

MOTOROLA MEMORY DATA
8-5

II

MILITARY 6164

TRUTH TABLE

'E'i

E2

G

iN

Mode

Supply Currem

1/0 Pin

H

X

X

X

Not Selected

ISB

. High Z

X

L

X

X

Not Selected

ISB

High Z

L

H

H

H

Output Disabled

ICC

High Z

L

H

L

H

Read

ICC

Pout

L

H

X

L

Write

ICC

Din

X=don t care

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Valua

Unit

VCC

-0.5 to + 7.0

V

Vin, Vout

-0.5 to VCC+0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipetion (TA = 25°C)

Po

1.0

Power Supply Voltage
Vokage Relative to VSS for Any
Pin Except VCC

Temperature Under Bia.

Tbia.

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precaution. be taken to
avoid application of any voltage higher than
maximum rated vokages to this highimpedance circuit.

W

-55 to +125

°c

Operating Temperature

TA

-55 to +125

°c

Storage Temperature

Tsta

-65 to + 150

°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended period. of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5 V ±10%, TA = -55 to + 125°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.5

V

Input High Voltage

VIH

2.2

VCC + 0.3

V

Input Low Voltage

VIL

"':0.3"

0.8

V

Symbol

Min

Max

Unit

ilL

-

2

p.A

Output leakage Current (El = VIH, E2 = Vll, or G = VIH, Vout = 0 to VCC)

IOZl

-

2

p.A

Operating Supply Current Cycle = Min, Duty = 100%

ICCA

90
120

mA

Parameter

•

'VIL (mIn) = -0.5 Vdc; VIL (mIn) = -3 Vac (pulse wIdth", 20 ns)

DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VCC)

Standby Current (El = VIH or E2 = Vll)

ISBl

Standby Current (E1 '" VCC - 0.2 V or E2 '" 0.2 V)

ISB2

Output low Voltage (lOl = 8 mAl

VOL

-

Output High Voltage (lOH = -4 mAl

VOH

2.4

+25, + 125°C
-55°C

2

mA

0.9

mA

0.4

V

-

V

CAPACITANCE (f = 1 MHz, TA = 25°C, sampled at initial device qualification and major redesigns rather than 100% tested)
Characteristic
Input Capacitance

Symbol
All Inputs Except DO

Cin

DO

CliO

Input/Output Capacitance

MOTOROLA MEMORY DATA
8-6

Min

-

Typ

Max

5

10

Unit
pF

6

12

pF

MILITARY 6164

AC OPERATING CONDITIONS AND CHARACTERISTICS
+ 125°e, Unless Otherwise Noted)

(Vee = 5 V ± 10%, TA = - 55 to
Input Timing Measurement Reference Level . . . . . . . . 1.5 V
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . 0 to 3 V
Input Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . .. 5 ns

Output Timing Measurement Reference Level . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 1

READ CYCLE (See Note 11
Characteristic

6164-55

Ait
Symbol

Symbol

Min

Max

6164-70
Min

Max

Unit

Read Cycle Time

tAVAV

tRC

55

-

70

-

ns

Address Access Time

tAVQV

tAA

55

-

70

ns

El Access Time

tE1LQV

tACl

E2 Access Time

tE2HQV

tAC2

tGLQV

tOE

-

tE1LQX, tE2HQX

tCLZ

10

tGLQX

tOLZ

5

tEl HQZ, tE2LQZ

tCHZ

tGHQZ

tOHZ

G Access Time
Chip Enable to Output Low-Z
Output Enable to Output Low-Z
Chip Enable to Output High-Z
Output Enable to Output High-Z

-

55

-

50

-

55

35
35

10

5

-

70

ns

70

ns

Notes

50

ns

-

ns
ns

2

35

ns

2,3

35

ns

2,3

2

NOTES:
1. W is high at all times for read cycles.
2. All high-Z and low-Z parameters are considered in a high or low impedance state when the output has made a 500 mV transition from the

previous steady state voltage.
3. This parameter is sampled and not 100% tested .

: .----------tAVAV-----------I·~1
...

----~~I~--------------------------,~Ir-------

A

A (ADDRESS)

A

1-01..1 - - - - - - tAVQV
n, E2 (CHIP ENABLE)

..

------""""'\1
_ ______AI
.

I

I.-W(QX'" I

I

~

--------~I~
G (OUTPUT ENABLE)

I

I

i
Q (DATA OUT)

HIGH·Z

\...

I.

1

1 ' 1

I

I

II

I

-

W

I

~tGLOX..l
---l

tE1Haz
1f2Laz -

I

I

~tGHaz_1

l-tGLQV==J

I
I

i

\if
?\.

II

•
.
I - t m o v , tE2HOV - ,

_

i

1

DATA VALID

1

~
HIGH-Z
~

I

~ tE1LQX

tE2HOX

- I

AC TEST LOADS
VLOAD = vcc

110

30 pF
(INCLUDING
SCOPE & JIG)

(Used for all propagation delay tests
except for high to high Z
transitions. I

Figure 1a.

VLOAD = GND

I/O

30pF
(INCLUDING
SCOPE & JIG)

(Used only for propagation tests
involving high to high Z transitions
orvicev.....1

Figure 1b.
MOTOROLA MEMORY DATA
8-7

TIMING LIMITS
The table 9f timing values shows
either a minimum or a maximum limit
. for each parameter. Input requirements
are specified from the external system
point of view. Thus, address setup time
is shown as a minimum since the system must supply at least that much time
(even though most devices do not
require it). On the other hand, responses
from the memory are specified from the
device point of view. Thus, the access
time is shown as a maximum since the
device never provides data later than
that time.

II

MILITARY 6164

WRITE CYCLE 1(W CONTROLLED) (See Note 1)
61&4-55

Symbol

Alt
Symbol

Min

Write Cycle Time

tAVAV

twc

55

Address Setup Time

tAVWL

tAS

15

Characteristic

6164-70

Max

Min

Max

70

-

Address Valid to End of Write

tAVWH

tAW

50

Write Pulse Width

twLWH

twp

45

-

Data Valid to End of Write,

tDVWH

tDW

30

-

40

-

Data Hold Time

twHDX

tDH

10

Write High to Output Low-Z

twHQX

twLZ

5

70

-

60

-

15

Unit

Notes

ns
ns
ns
ns

2

ns

10

-

ns

3

5

-

ns

4

NOTES:

1. A write cycle starts at the latest transition of a low E1, low Wor high E2. A write cycle ends at the earliest transition of a high

E1. high Wor low

E2.

2. If iii goes low coincident with or prior to E1low or E2 high then the outputs will remain in a high impedance state.
3. During this time the output pins may be in the output state. Signals of opposite phase to the outputs must not be applied at this time.
4. All high-Z and low-Z parameters are considered in a high or low impedance state when the output has made a 500 mV transition from the
previous steady state voltage.

AIADDRESS)

J

t " . - - - - - - - - t A V A V - - - - - - - -.~1
.

*~-----, ..
...
--------tAVWH-------~'~twHAX

EICHIP ENABLE)

!\
I
I

W IWRITE ENABLE)

:

,""'4Ir----twLWH----a'

i

~

~ tAVWL

~~---------

---r

~ tDVWH

DIDATAIN)<>¢a-:-~HIG=H-Z:..----,-____<:(XXX)__
~twHQX

AC TEST LOADS

VLOAD VCC

VLOAD = GND

=

110

30 pF
(INCLUDI
NG
SCOPE &JIGI

(Used for all propagation delay tests
except for high to high Z
transitions.)

Figure 1a.

TIMING LIMITS

110

30 pF

(INCLUDING
SCOPE &JIG}
(Used only for propagation tests
Involving high to high Z transitions
or vice versa.)

Figure 1b.

MOTOROLA MEMORY DATA
8-13

The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a
maximum since the device never provides
data later than that time.

II

MILITARY 6168

WRITE CYCLE 2 IE' Controlled· See Note 1)
Standard'

Alternate

Min

Max

Write !>fcl!! Time

tAVAV

Address Set.!lP Time

tAVEL

twC.
tAS

Address Valid to End of Write

tAVEH

tAW

tELEH

tcw

Data Valid to End of Write

tOVEH

tow

50
0
40
45
25

-

Data Hold Time

tEHOX

tOH

'3

Write Recovery TIme

tEHAX

twR

0

Write

Pul~e

Width

6168-70

6168·55

Symbol

Parameter

Min

-

60
0
60
60
30
3
0

-

-

Max

-

Unit

Notes

ns

-

ns

-

ns'

-

ns

-

2,3

ns
ns

-

ns

NOTES:
1. A write occurs during the overlap of E low and iii low.
2. If Egoes low coincident with or after iii goes low, the output will remain in a high impedance condition.
3. If E goes high coincident with or before iii goes high, the output will remain in a high impedance condition.

1+---------- tAVAV - - - - - - - - - - + \
A (ADDRESS!.

1+--------------+----------.
. .---------.1
.
tAVEH

E (CHIP ENABLE!

- - - i l * , t - - _ + - tEHAX

WIWRITE ENABLEI

-----------"'\

-~-. .- tEHDX
K""1'.~~-'-

o (DATA INI
H!GH·Z
Q(DATA

oun - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

II

ORDERING INFORMATION
(Order by Full Part Numberl

T1,

TL_C____

61

Package Type
Speed

-

Part Number

Available Speeds

55 ns
70 ns

Available Packages in All Speeds
R C·DIP
U LCCC

20 pin
20 terminal

MOTOROLA MEMORY DATA
8-14

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Military 6206
Advance Information

32K x 8 Bit Fast Static Random
Access Memory

MPO

The 6206 is a 262,144 bit static random access memory organized as 32,768
words of 8 bits, fabricated using Motorola's third-generation high-performance
silicon-gate CMOS (HCMOS IV) technology. Static design eliminates the need for
external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.
Chip enable fE) controls the power-down feature. It is not a clock but rather a
chip control that affects power consumption. In less than a cycle time after E
goes high, the part automatically reduces its power requirements and remains
in this low-power standby mode as long as E remains high. This feature provides significant system-level power savings. Another control feature, output
enable (G) allows access to the memory contents as fast as 15 ns (6206-45).
The 6206 is packaged in a 600 mil, 28 pin ceramic dual-in-line package.
•
•
•
•
•

Single 5.0 V Supply, ± 10%
Fully Static - No Clock or Timing Strobes Necessary
Fast Access Time - 45 or 55 or 70 ns or 100 ns (Maximum)
Low Power Dissipation
Two Chip Controls; E for Automatic Power Down
G for Fast Access to Data
• Three State Outputs
• Fully TTL Compatible
• Order as Part Number: 6206-45/BXAJC

1111111

CASE 733-04
CERAMIC

PIN ASSIGNMENT

1.

28

A12

21

Vee
W

A1

28

A13

AS

25

All

AS

24

A9

A4

23

An

AJ

22

il

A2

21

A10

A1

20

E

10

19

001

n

18

006

001

12

11

005

An

002 1

13

16

DQ4

A13

Vss I

14

15

DQ3

A14

BLOCK DIAGRAM
A2
AJ

A4

_Vee

!>IiJ

AS

MEMORY ARflAY
1512 ROWS
512 COLUMNS}

ROW
~=:::::j DECODfR

-VSS

AO

All

000

A9

DQ()_.......-I'--~---.-I"--I----....L,

I

__

DQ1-..-t-,H

PIN NAMES

AO

A1

A1 A10 A12 A14

W

AO-A14 . . . . . . . . . . . . . Address
Vi. . . . . . . . . . . . . . Write Enable
E ............... Chip Enable
G . . . . . . . . . . . . . Output Enable
DQO-DQ7 . . . . . . Data Input/Output
VCC . . . . . . +5.0 V Power Supply
VSS . . . . . . . . . . . . . . . Ground

il----d...-/

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROlA MEMORY DATA
8-15

II

MILITARY 6206

TRUTH TABLE
Mode

Supply
Current

110 Pin

X

Not Selected

ISB

High Z

H

Output Disabled

ICC

High Z

L

H

Read

ICC

Dout

X

L

Write

ICC

Din

E

~

iN

H

X

L

H

L
L

This .device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maxil1'lum rated voltages to
this high-impedance circuit. '

x - Don't Care

ABSOLUTE MAXIMUM RA11NGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5 to + 7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Output Current (per 110)

lout

±20

Power Dissipation (TA = 25·C)

Po

1.0

W

Tbias

-55to +125

·C

TA

-55to +125

·C

Tstg

-65to +1.50

·C

Temperature Under Bias
Operating Temperature
Storage Temperature -

Plastic

mA

NOTE. Permanent deV;lce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDI-

TIONS. Exposure to higher than recommended voltages for extended periods of time

could affect device reliability.

DC OPERA11NG CONDITIONS AND CHARACTERISTICS
(VCC

=

5.0 ± lOOk, TA

= - 55· to

+ 125·C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDI110NS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC + 0.3

V

VIL

-0.3'

-

0.8

V

Symbol

Min

Max

Unit

Parameter

Input Low Voltage
*Vll (min) -

II

-0.3 Vdc. VIL (min) -

Unit

-3.0 Vae (pulse width,,", 20 os)

DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin
Output Leakage Current (E

=

=

VIH, or G

0 to Vccl

=

VIH, Vout

Power Supply Current
(E = VIL, Yin = VIH or VIL, lout

= 0)
(E = VIH) (TIL Levels)
Standby Current (E '" VCC - 0.2 V) (CMOS Levels)
Output Low Voltage (lOL = 8.0 mAl
Output High Voltage (lOH = -4.0 mAl

Ilkg(l)

=

0 to 5.5 V)
(tAVAV
(tAVAV

Ilkg(O)

=
=

35 ns)
45 ns)

Standby Current

CAPACITANCE (f

ICC
ICC
ISBI

-

-

±2.0

,.A

±2.0

,.A

t20
110

mA

20

mA

20

mA

VOL

-

0.4

V

VOH

2.4

-

V

ISB2

= 1.0 MHz, TA = 25·C, periodically sampled and not 100% tested.)

Symbol

Max

Input Capacitance

Cin

6.0

pF

110 Capacitance

CliO

8.0

pF

Characteristic

MOTOROLA MEMORY DATA
8-16

Unit

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

\ Military 6268\
4K X 4-Bit Fast Static
Random Access Memory

IIIJIItt

The 6268 is a 16,384-bit static random access memory organized as 4096 words
of 4 bits, fabricated using Motorola's second-generation high-performance silicongate CMOS (HCMOS III) technology. Static design eliminates the need for external
clocks or timing strobes, while CMOS circuitry reduces power consumption and
provides greater reliability. Fast access time makes this device suitable for cache
and other sub-50 ns applications.
The chip enable (E) pin is not a clock. In less than a cycle time after E goes high,
the part enters a low-power standby mode, remaining in that state until E goes low
again. This device also incorporates internal power down circuitry that will reduce
active current for less than 100% duty cycle applications. These features provide
reduced system power requirements without degrading access time performance.
The 6268 is available in a 20-lead ceramic dual-in-line and 20-terminal ceramic
LCCC package and features the standard JEDEC pinout.
• Single 5 V Supply, ± 10%
• 4K x 4 Bit Organization
• Fully Static - No Clock or Timing Strobes Necessary
• Three State Output
• Fully TTL Compatible
• Fast Access Time (Maximum):
Address
Chip Enable
6268-35
35 ns
35 ns
6268-45
45 ns
45 ns
• Low Power Operation: 120 rnA Maximum, Active AC
20 rnA Maximum, Standby (TTL Levels)
0.9 rnA Maximum, Standby (Full Rail)

MPO

1111111

PIN ASSIGNMENT
A4 I 1 .

20

Vee

A5 I 2

19

A3

A6

:

3

18

A2

4

17

Al

A8 I 5

16

AO

A9

6

15

000

Al0

7

14

001

All

8

13

002

9

12

DQ3

10

11

Vi

A7

Vss

CASE 732-03
CERAMIC

BLOCK DIAGRAM
A2

IlSBlA6

A6

AO

A7

Al

Al

A6

AO

A2

A9

DOO

All

002

DOl

A3
A4

IMSBI MJ

E VSS 'Ii 0Q3
000

CASE 756C-01
CERAMIC

DOl

D02

PIN NAMES
D03

AO-All.
W ...

E

. . . . . . Address Input
Write Enable

. . . Chip Enable
OQO-OQ3
.. Data Input/Output
...... + 5 V Power Supply
VCC
...... Ground
VSS

'Ii

MOTOROLA MEMORY DATA
8-17

..

MILITARY 6268

TRUTH TABLE

'E

til

Mode

Vee Currant

I/O Pin

Cycle

H
L
L

X
H
L

Not Selected
Read
Write

ISB1,ISB2
ICC
ICC

High-Z
Dout
Din

Read Cycle
Write Cycle

-

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated
voltages to this high-impedance circuit.

ABSOLUTE'MAXlMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5 to +7

V

Yin, Vout

-0.5 to VCC+0.5

V

lout

±20

mA

Po

1

W

Tbias

-55 to +125

°c

TA

-55 to +125

°c

Tstg

-65to +150

°c

Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC
Output Current (per I/O)
Power Dissipation (TA

=

25°C)

Temperature Under Bias
Operating Temperature
Storage Temperature

NOTE: Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5 V ±10%, TA = -55 to + 125°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.5

V

Input High Voltage

VIH

2.2

VCC + 0.3

V

Input Low Voltage

VIL

-0.5'

0.8

V

Symbol

Min

Max

Unit

2

p.A

Parameter

'VIL (min)

II

=

-0.5 Vde; VIL (mm)

=

-3 Vae (pulse width", 20 ns)

DC CHARACTERISTICS
Paramater

= 0 to Vccl
Output Leakage Current (E = VIH, Vout = 0 to Vccl
AC Supply Current (lout = 0 mA, Cycle = Min, Duty = 100%)
TTL Standby Current (E = VIH, No Restrictions on Other Inputs)
Input Leakage Current (All Inputs, Yin

-

ilL

CMOS Standby Current (E '" VCe; - 0.2 V, No Restrictions on Other Inputs)

ISB2

-

= 8 mAl
Output High Voltage (lOH = -4 mAl

VOL
VOH

Output Low Voltage (lOL

10ZL
ICCA
ISB1

2

p.A

120

mA

20

mA

5.0

mA

-

0.4

V

2.4

-

V

CAPACITANCE (f = 1 MHz, TA = 25°C, sampled at initial device qualification and major redesigns rather than 100% tested)
Characteristic
Input Capacitance

All Inputs Except E
E

I/O Capacitance

MOTOROLA MEMORY DATA
8-18

Symbol

Min

Typ

Max

Unit

Cin

-

3
5

6
6

pF

CI/O

-

5

7

pF

MILITARY 6268

AC OPERATING CONDITIONS AND CHARACTERISTICS
= 5 V ± 10%, TA = -55 to + 125°e, Unless Otherwise Noted)

(Vee

Input Reference level . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input Pulse levels. . . . . . . . . . . . . . . . . . . . . . . 0 to 3 V
Input Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . .. 5 ns

Output Reference level . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output load . . . . . . . . . Figure lA Unless Otherwise Noted

READ CYCLE (See Note 1)
Symbol

Parameter

Standard

6268-35

Alternate

Min

Max

6268-45

Min

Max

Unit

Notes

2

Read Cycle Time

tAVAV

tRC

35

-

45

-

ns

Address Access Time

tAVQV

tAA

35

-

45

ns

Enable Access TIme

tElQV

tACS

-

35

-

45

ns

Output Hold from Address Change

tAXQX

tOH

3

3

tElQX

tLZ

5

5

-

ns

Enable low to Output Active

-

ns

3,4

Enable High to Output High-Z

tEHQZ

tHZ

0

15

0

20

ns

3,4,7

Power Up Time

tELICCH

tpu

0

-

ns

7

Power Down Time

tEHICCl

tpD

45

ns

7

-

0

-

35

-

NOTES;
1. W is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. At any given voltage and temperature, tEHOZ max, is less than tELQX min. both for a given device and from device to device.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
5. Device is continuously selected fE: = Vili. _
6. Addresses valid prior to or coincident with E going low.
7. This parameter is sampled and not 100% tested.

READ CYCLE 1 (See Note 5 Above)
tAVAV
A (ADDRESS)

W

J

tAXOX

o (DATA OUT)

PREVIOUS DATA VALID

WXXXXX

V

DATAVAUD

II

tAVOV

READ CYCLE 2 (See Note 6 Above)
~-------------------~VAV--------------------~

A (ADDRESS)
.....----tELOV-----J~
E (CHIP ENABLE)

o(DATA OUT) ---+-----+---0(

VCC ICC
SUPPLY
CURRENT ISB

DATA VALID

f

tEHICCL

teLiCCH
---------

MOTOROLA MEMORY DATA
8-19

\l..

.MILITARY 6268

WRrrE CYCLE 1 ('iN Controlled; See Note 1)
Symbol

Parameter

6268-35

6268-46

Unit

Notes

-

ns

2

ns

20

-

-

3

-

ns

0

15

0

20

ns

3,4,5

tow

0

0

-

ns

3,4

twR

0

-

0

-

ns

Standard

Alternete

Min

Max

Write Cycle Time

tAVAV

twc

30

Address Setup Time

tAVWL

tAS

0

Address Valid to End of Write

tAVWH

tAW

30

Write Pulse Width

twLWH

twP

30

-

Data Valid to End of Write

tOVWH

tow

20

-

Data Hold Time

twHOX

tOH

3

Write Low to Output High-Z

twLOZ

twz

Write High to Output Active

tWHQX

Write Recovery Time

twHAX

Min

-

Max

40
0
35
30

ns
ns
ns

NOTES.

,.
2.
3.
4.
5.

A write occurs during the overlap of E low and W low.
All write cycle timing is referenced from the last valid address to the first transitioning address.
Transition is measured ±500 mV from steady-state voltage with load in Figure 1B.
At any given voltage and temperature, twLQZ max, is less than !WHOX min, both for a given device and from device to device.
This parameter is sampled and not 100% tested.

""1
_ _

.. I

-------tAVAV--------~

J....-----------------....,)(

ADDRESS

"I-

.. I
1-o1--------tAVWH ---------'*--1-

1

twHAX

/
\~----------~~
""1_..----twLWH ---....;..
1

~I

w

__ ID *XXXXXX

OXXXXXXX%XXX*~D~m__~:

II

Q_.. .;.H=IGH;.::.. Z- . . .  Dout

PIN ASSIGNMENT

cs
WORD
DRIVERS

32X32
ARRAY

14

II
15
IOF32
DECODER

IOF32
DECODER

VCC

M

Din

Al

WE

f>J.

M

I.J

M

AA

A7

COUI

A6

GND

A5

PIN NAMES
13

M

Al

A2 I.J AA

A5

A6 A7 M

M

Vee ~ PIN 16
GND ~ PINS

MOTOROLA MEMORY DATA

CS .............. Chip Select
AO-A9 . . . . . . . . . . Address Inputs
WE . . . . . . . . . . . . . Write Enable
Din . . . . . . . . . . . . . . . Data Input
Dout . . . . . . . . . . .. Data Output

MILITARY 93415

FUNCTIONAL DESCRIPTION
The 93415 is a fully decoded 1024-bit Random Access
Memory organized 1024 words by one bit. Bit selection
is achieved by means of a 10-bit address, AO to A9.
The Chip Select input provides for memory array
expansion. For large memories, the fast chip select
access time permits the decoding of Chip Select (CS) from
the address without affecting system performance.
The read and write operations are controlled by the
state of the active low Write Enable (WE, Pin 14). With
WE held low and the chip selected, the data at Din is
written into the addressed location. To read, WE is held
high and the chip selected. Data in the specified location
is presented at Dout and is non-inverted.
Uncommitted collector outputs are provided to allow
wired-OR applications. In any application an external
pull-up resistor of RL value must be used to provide a

high at the output when it is off. Any RL value within the
range specified below may be used.
VcdMin)
R
Vcc(Min) - VOH
IOL - FO(l.S) '" L '" n(lCEX) + FO(O.04)
RL is in kO
n = number of wired-OR outputs tied together
FO = number of TTL Unit Loads (UL) driven
ICE X = Memory Output Leakage Current
VOH = Required Output High Level at Output Node
IOL = Output Low Current
The minimum RL value is limited by output current
sinking ability. The maximum RL value is determined by
the output and input leakage current which must be supplied to hold the output at VOH. One Unit Load = 40 p.A
High/l.S mA Low.

ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
Ceramic Package (E and F Suffix)

TRUTH TABLE
Inputs

Output

- 55°C to + 165°C

Operating Junction Temperature, TJ
Ceramic Package (E and F Suffix)

<165°C

VCC Pin Potential to Ground Pin

-0.5Vto +7.0V

Input Voltage (de)

-0.5 V to +5.5 V

Voltage Applied to Outputs
(Output High)

-0.5 V to +5.5 V

Output Current (de) (Output Low)

WE

Din

Open
Collector

Mode

H
L
L
L

X
L
L
H

X
L
H
X

H
H
H
Dout

Not Selected
Write "0"
Write "1"
Read

H = High Voltage Level
l = low Voltage Level
X = Don't Care (High or Low)

+20 mA

Input Current (de)

CS

-12 mA to +5.0 mA

NOTE 1: Device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.

GUARANTEED OPERATING RANGES (Note 2)
Supply Voltage (Vee)
Min
4.5 V

I
I

Nom
5.0 V

I
I

Max

Ambient Temperature (TAl

5.5 V

- 55'C to + 125'C

DC OPERATING CONDmONS AND CHARACTERISTICS (Full operating voltage and temperature range unless otherwise noted)
Limits
Symbol

Characteristic

VOL

Output Low Voltage

VIH

Input High Voltage

Min

Max

Unit

0.45

Vde

VCC

Vde

Guaranteed Input High Voltage for All Inputs

2.1

VIL

Input Low Voltage

0.8

Vde

IlL

Input Low Current

-400

!LAde

IIH

Input High Current

40

!LAde
!LAde

ICEX

Output Leakage Current

100

VCD

Input Diode Clamp Voltage

-1.5

Vde

ICC

Power Su pply Cu rrent

130

mAde

155

mAde

170

mAde

MOTOROLA MEMORY DATA
8-33

Conditions

=

Min. IOL

=

16 mA

Guaranteed Input Low Voltage for All Inputs

= Max, Vin = 0.4 V
= Max. Vin = 4.5 V
VCC = Max. Vout = 5.5 V
VCC = Max, lin = -12 mA
TA = +125°C
VCC = 5.5 V,
TA = 25'C
All Inputs Grounded
TA = -55'C
VCC
VCC

•

MILITARY 93415

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)

AC TEST LOAD AND WAVEFORM
INPUT PULSES

LOADING CONDmON
ALL INPUT PULSES

VCC

--'
~
~

3.5Vp-p _

31100

I

Dout
93415

- - - - - - __

I

GND-:~ ;-'Ons

,

3~~-

30pF
CAPACITANCE
IINCLUDING
SCOPE AND JIGI

6000

\~--

~\ __
I

--..!

90%
10%

I

"-10ns

',--,::::---

-- -- --

-~I,-

-10%

"... ~p-+, ----- ---1~- - 90%
:-r:
GND -=- --l ~ 10
--I I-- 10
I

I'

ns

ns

93415/BElBF
Symbol

Characteristic (Notes 2. 3)

Min

Max

READ MODE
tACS
tRCS
tAA

DELAY TIMES
Chip Select Time
Chip Select Recovery Time
Address Access Time

45
50
60

WRITE MODE
tws
twR

DELAY TIMES
Write Disable Time
Write Recovery Time

45
50

tw
tWSD
tWHD
tWSA
twHA
twscs
tWHCS

g'

Unit

Conditions

ns

See Test Circuit
and Waveforms
ns

INPUT TIMING REOUIREMENTS
Write Pulse Width (to guarantee write)
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time (at tw = Min)
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time

See Test Circuit
and Waveforms

ns
40
5.0
5.0
15
10
5.0
5.0

See Test Circuit
and Waveforms

READ OPERATION TIMING DIAGRAM
PROPAGATION DELAY FROM CHIP SELECT

cs

CHIP SELECT

~
I
I

gX~~OUTPUT

PROPAGATION DELAY FROM ADDRESS INPUTS

I
I

_ _ _ _-:-1-"'\

:

\
I

I

lACS ~

r

I

I

I'

I

'---=,---' I

AO-A9

---v

ADDRESS~_ _ _ _ _ _ _ __

I
I

V-I:'---

Dout
:
DATAOUTPUT
_ _ _-:-;_ _ _ _ _

lRCS

IALL TIME MEASUREMENTS REFERENCED TO 1.5 VI

MOTOROLA MEMORY DATA

t--- 'AA ----1

MILITARY 93415

WRITE CYCLE TIMING

'\

cs

CHIP SELECT

r-

I

I

::ESSINP-U-TS----:t--"'"""'\~

~~TA

~r---li----

~

:¥:

INPUT - -_ _-4-_ _-1_-'

~ tw

WE

~

WRITE ENABLE

I
I twSD - - '

~~t~

Dout
DATA OUTPUT

1
I

I

I

----v-t

1
I

tws -+-----I

I
:

It.-.:=. twHcs ------l

\

I

I

I

~H~H~

1
I

1'--------

I

I

1------1- twR

IALL TIME MEASUREMENTS REFERENCED TO 1.5 VI
NOTE 2: DC and AC specifications limits guaranteed with 500 linear feet per minute blown air.

flJA (Junction to
Ambient)
Package

Blown

Still

flJC (Junction to Case)

E Suffix
F Suffix

50'CIW
55'CIW

85'CIW
90'CIW

15'CIW
15'CIW

NOTE 3: The AC limits are guaranteed to be the worst case bit in the

memory.

II

MOTOROLA MEMORY DATA
8-35

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Military 93422
93L422,A

TTL 256 x 4-Bit
Random Access Memory
The 93422 Series are 1024-bit ReadlWrite RAMs, organized 256 words by 4
bits, designed for high performance main memory and control storage
applications.
They have full decoding on-chip, separate data input and data output lines, an
active low-output enable, write enable, and two chip selects, one active high,
one active low. These memories are fully compatible with standard TTL 'logic
families. A three-state output is provided to drive bus-organized systems and/or
highly capacitive loads.
•
•
•
•
•
•
•
•

Three-State Outputs
Non-Inverting Data Outputs
Power Dissipation - 0.26 mW/Bit Typical
Standard 22-Pin, 400 Mil Wide Package
Power Dissipation Decreases with Increasing Temperature
Organized 256 Words x 4 Bits
Two Chip Select Lines for Memory Expansion
Address Access Time: 93422
- 60 ns Max
93L422A - 55 ns Max
93L422 - 75 ns Max

1

WSUFFIX
CASE 736-05
CERAMIC

PIN ASSIGNMENT

BLOCK DIAGRAM
00 D1

02 03
CS1

A3

1.

22

Vee

A2

21

A4

D1

A1

20

D2

/lJJ

19

D3

AS

18

WE
CSii
OE

M.

17

CS1

A7

16

03

GND

15

D3

DO

15 L....-,_--,_....J

II

MPO

1111111

WORD
DRIVERS

DO

32X32
ARRAY

Vee ~ PIN 22
GND ~ ~N8

14

02

00

10

13

02

D1

11

12

01

PIN NAMES
1·0f.32
DECODER

A3

A4

MJ M. A7

1·0F-B
DECODER

CSO, CS1 . . . . . . . .
AO-A7 . . . . . . . . . .
OE . . . . . . . . . . . .
WE . . . . . . . . . . . .
00-03 . . . . . . . . . .
00-03. . . . . . . . . .

/lJJ A1 A2

MOTOROLA MEMORY DATA
8-36

. Chip Selects
Address Inputs
Output Enable
. Write Enable
. . Data Inputs
. Data Outputs

MILITARY 93422 e 93L422,A

FUNCTIONAL DESCRIPTION
The 93422 Series are fully decoded 1024-bit random
access memories organized 256 words by 4 bits. Word
selections are achieved by means of an B-bit address,
AO-A7.
The Chip Select (CSO and CS1) inputs provide for memory array expansion. For large memories, the fast chip
select time permits the decoding of chip select from the
address without increasing address access time.
The read and write operations are controlled by the
state of the active low Write Enable (WE, Pin 20). With
WE and CSO held low and the CSl held high, the data at
On is written into the addressed location. To read, WE
and CSl are held high and CSO is held low. Data in the
specified location is presented at the output (00-02) and
is non-inverted.
The three-state outputs provide drive capability for
higher speeds with capacitive load systems. The third
state (high impedance) allows bus-organized systems
where multiple outputs are connected to a common bus.
During writing, the output is held in a high-impedance
state.

ABSOLUTE MAXIMUM RATINGS·
Storage Temperature
Ceramic Package (W Suffix)

Supply Voltage (Veel

93422/BWAJC
93L4221BWAJC
93L422A1BWAJC

Min

-0.5Vto +7.0V

Input Voltage (de)

-0.5 V to +5.5 V

Voltage Applied to Outputs
(Output High)

-0.5 V to +5.5 V

Output Current (de) (Output Low)

4.5 V

5.0 V

-12 mA to +5.0 mA

*Devlce damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded.

TRUTH TABLE
Inputs

Output

OE

CSil

CSl

WE

DO-D3

X
X

H
X
L
L
X
L

X
L
H
H
X
H

X
X
L
L
X
H

X
X
L
H
X
X

X
X
H
L

00-03

Mode

High Z
Not Selected
High Z
Not Selected
High Z
Write "0"
High Z
Write "1"
High Z Output Disabled
00-03
Read

H = High Voltage level
L = Low Voltage Level
X = Don't Care (High or Low)

-55'C to
+ 125'C

5.5 V

+20 mA

Input Current (de)

Ambient
Temp. (TAl

Max

Nom

<165'C

VCC Pin Potential to Ground Pin

GUARANTEED OPERATING RANGES

Part Number

- 65'C to + 150'C

Operating Junction Temperature, TJ
Ceramic Package (W Suffix)

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range)
Limits
Symbol

Characteristic

Min

Max

Units

VOL

Output Low Voltage

-

0.45

Vde

VCC

VIH

Input High Voltage

2.1

-

Vde

Guaranteed Input High Voltage for All Inputs

VIL

Input Low Voltage

IlL

Input Low Current

IIH

Input High Current

loff

Output Current (High Z)

-

Vde

Guaranteed Input Low Voltage for All Inputs

!LAde

-

40

/LAde

-

50
-50

!LAde

-70

mAde

= Max, Vin = 0.45 V
= Max, Vin = 5.5 V
VCC = Max, Vout = 2.4 V
VCC = Max, Vout = 0.45 V
VCC = Max (Note 1)
VCC = Min,IOH = -5.2 mA
VCC = Max, lin = -10mA
TA = + 125'C
TA = +25'C
TA = -55'C
VCC = 5.5 V,
All Inputs Grounded
TA = +125'C
TA = + 25'C
TA = -55'C

lOS

Output Current Short Circuit to Ground

-10

Output High Voltage

2.4

VIK

Input Diode Clamp Voltage

-

-1.5

Vde

-

130

mAde

155

mAde

170

mAde

70

mAde

-

80

mAde

-

90

mAde

Power Supply Current
93L422A
93L422

= 8.0 mA

0.8

VOH

ICC

Min, 10L

-300

-0.01

93422

Conditions

=

-

-

Vdc

MOTOROLA MEMORY DATA
8-37

VCC
VCC

MILITARY 93422 e 93L422,A

AC OPERAllNG CONDITIONS AND CHARACTERISllCS
(Full operating voltage and temperature range)

AC TEST LOAD AND WAVEFORMS

INPUT PULSES

LOADING CONDmONS
ALl INPUT PULSES

Vee

30pF

LOAD A

Symbol

•

D.U.T..

(CAPACITANCE INCLUDES
SCOPE AND TEST FIXTUREI

Characteristic
(Notes 1. 2. 3. 4. 5)

READ MODE
tACS
tZRCS
tAOS
tZROS
tAA

DELAY TIMES
Chip Select Time
Chip Select to High Z
Output Enable Time
Output Enable to High Z
Address Access Time

WRITE MODE
tzws
twR

DELAY TIMES
Write Disable to High Z
Write Recovery Time

tw
twSD
twHD
tWSA
tWHA
twscs
tWHCS
NOTES:

LOADB

934221BWAJC

Min

-

-

-

,-

INPUT TIMING REQUIREMENTS
Write Pulse Width
(to guarantee write)
Data Setup n me Prior
to Write
Data Hold Time After Write
Address Setup Time
(attw = Min)
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time

Max

45
45
45
45
60
45
50

5.0
10

-

10
5.0
5.0

-

30
5.0

93L4221BWAJC

Min

-

Max

-

45
45
45
45
75

-

45
50

5.0
5.0
10
10
5.0
5.0

Min

Max

Unit
ns

-

30

93L422A1BWAJC

-

-

-

-

40
40
40
40
55

-

45
45

40

-

5.0

-

5.0
10

-

5.0
5.0
5.0

ns

ns

-

1. Output short circuit conditions must not exceed 1.0 second duration.
2. The maximum address access time is guaranteed to be the worst-case bit in the memory.
3. Load A used to measure transitions between logic le"els and from High Z state to logic Low state.
Load B used to measure transitions between High Z state to logic High state.
Load C used to measure transitions from either logic High or Low state to High Z state.
4. All time measurements are referenced to + 1.5 Vdc except transitions into the Hig~ Z state where outputs are referenced to a delta of 0.5 Vdc
from the logic level using Load C.
5. See test circuit and waveforms.

'MOTOROLA MEMORY DATA
8-38

MILITARY 93422 e 93L422,A

READ OPERATION TIMING DIAGRAM
(All Time Measurements Referenced to 1.5 V)

PROPAGATION DELAY FROM CHIP SELECT

PROPAGATION DELAY FROM ADDRESS INPUTS

CSt

CSii

3-STATE

--y

M-A7

CHIP SELECT

ADDRESS INPUTS ~

00-03

I

DATA OUTPUT
LOAD A

I

~--------------

I

00-03

0D-03

DATA OUTPUT

DATA OUTPUT
LOADB

PROPAGATION DELAY FROM OUTPUT ENABLE

~TPUTENABLE -----~\.._______
00-03
DATA OUTPUT
LOAD A

-

- HIGHZ

00-03

21~~

J.STATE

-

tAOS

DATA OUTPUT
LOADB

.... ) ; :
.

1

__ ..fr-----

WRITE CYCLE TIMING

cs

CHIP SELECT

M-A7
ADDRESS

00-03
DATA INPUT

.;

\

/\

\if
.11\

~"
)/\
V

\
j

-'1\

I--

WE
WRITE ENABLE
twSD"""!"

I--- -twscs twsA
00-03

LOAD A

~

J--

...

tw-·

-

II

j

i+- twHO

_ _ _ _ IHIGHZ

DATA OUTPUT
LOADB

-

twHA -

r--twR

(AU ABOVE MEASUREMENTS REFERENCE TO 1.5 VI

MOTOROLA MEMORY DATA
8-39

twHCS

-

•

MILITARY 93422e 93L422,A

WRITE ENABLE TO HIGH Z DELAY
SV

WE
WRITE ENABLE
7500
llO-O3

~
tzws --I
r- ___ _

DATA OUTPIJT

D.U.T.

"O"lEVEl

--"""~'''~lEVE=l-..Jf'=
~OU-TPU-T-;"';;:':':;;"-.,j -

30pF

HIGH Z
O.SV
O.SV

HIGH Z

~---lOADC

PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
CS,
CHIP SELECT

CSii
CHIP SELECT
llO-O3

DATA OUTPU7
llO-O3

DATA OUTPUT

PROPAGATION DELAY FROM OUTPUT ENABLE TO HIGH Z

liE

~

OUTPUT ENABLE

j1.5V

-~

tzRCS

"O"LEVEl

QO..03

"'" LEVEL

,..--- __

"0" lEVEL
_
---:·:::'''":'':LE:::VE::-l--'

O.S V

~

----:::::j

00-03
DATAOUTPU7
HIGH Z

tzROS

DATAOUTPU7

O.SV
~ ____ HIGHZ

(ALL tzxxx PARAMETERS ARE MEASURED AT ADELTA OF O.S VFROM THE lOGIC LEVEL AND USING lOAD C.I

•

tlJA (Junction to
Ambient)
Package

Blown·

W Suffix

50"C1W

1
1

Still

tlJC (Junction to caaa)

75°crw

15°crw

*500 hnear ft. per minute blown

81r.

MOTOROLA MEMORY DATA

f;:= __ _
[SV

HlGHZ

HIGHZ

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Military 93425

TTL 1024 x 1-Bit
Random Access Memory
The 93425 is a 1024-bit ReadlWrite RAM. organized 1024 words by 1 bit.
The 93425 is designed for high performance main memory and control storage applications and has a typical address time of 35 ns.
The 93425 has full decoding on-chip. separate data input and data output
lines. and an active low-chip select and write enable. The device is fully compatible with standard DTL and TTL logic families. A three-state output is provided
to drive bus-organized systems and/or highly capacitive loads.

MPO

1111111

Three-State Output
TTL Inputs and Output
Non-Inverting Data Output
High Speed Access Time - 35 ns Typical
Chip Select - 15 ns Typical
• Power Dissipation - 0.5 mW/Bit Typical
• Power Dissipation Decreases With Increasing Temperature
• Order as Part Number: 93425/BEAJC = Dual-In-Line
93425/BFAJC = Flat Pack
•
•
•
•

CASE 620-09
CERAMIC DUAL-IN-LiNE

BLOCK DIAGRAM
CASE 650-05
FLAT PACK
SENSE AMP
AND
WRITE DRIVERS

Dout

PIN ASSIGNMENT

WORD
DRIVERS

32 X32
ARRAY

14

WE

cs
15
~n

10F32
DECODER

cs

Vce

AO

Din

A1

WE

A2

AS

AS

AS

A4

A7

Dout

A8

GND

AS

1 OF 32
DECODER

PIN NAMES
13
/>IJ

A1

A2 A3 A4

AS

A6 A1 AS

AS

VCC

~

PIN 16

GND~~N8

NOTE: Logic driving sense amp/write drivers depicts
negative-only write used on C4m.

MOTOROLA MEMORY DATA
8-41

CS . . . . . . . . . . . . . . Chip Select
AO-A9 . . . . . . . . . . Address Inputs
WE . . . . . . . . . . . . . Write Enable
Din . . . . . . . . . . . . . . . Data Input
Dout . . . . . . . . . . .. Data Output

II

MILITARY 93425

FUNCTIONAL DESCRIPTION
The 93425 is a fully decoded 1024-bit Random Access
Memory organized 1024 words by one bit. Word selection
is achieved by means of a 10-bit address, AO-A9.
The Chip Select (<::5) input provides for memory array
expansion. For large memories, the fast chip select time
permits the decoding of chip select from the address
without increasing address access time.
The read and write operations are controlled by the
state of the active low Write Enable (WE, Pin 14). With
WE and CS held low, the data at Din is written into the

addressed location. To read, WE is held high and CS held
low. Data in the specified location is presented at Dout
and is non-inverted.
The three-state output provides drive capability for
higher speeds with capacitive load systems. The third
state (high impedance) allows bus organized systems
where multiple outputs are connected to a common bus.
During writing, the output is held in the highimpedance state.

ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
Ceramic Package (E and F Suffix)

TRUTH TABLE
Inputs

- 55°C to + 165°C

Operating Junction Temperature, TJ
Ceramic Package (E and F Suffix)

<165°C

VCC Pin Potential to Ground Pin

-0.5Vto +7.0V

Input Voltage (de)

-0.5 V to +5.5 V

Voltage Applied to Outputs
(Output High)

-0.5 V to +5.5 V

Output Current (de) (Output Low)

Output

CS

WE

Din

Dout

Mode

H
L
L
L

X

X

L
L
H

X

High Z
High Z
HighZ
Dout

Not Selected
Write "0"
Write"'"
Read

L
H

H = High Voltage level
L = Low Voltage level
X = Don't Care (High or Low)

+20 mA

Input Current (de)

-12mAto +5.0mA

NOTE 1: Device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.

GUARANTEED OPERATING RANGES (Notes 2 and 3)
Supply Voltage (Vee)
Min
4.5 V

•

I
I

Nom
5.0 V

I
I

Max

Ambient Temperatura ITA)

5.5 V

- 55°C to + 125°C

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)
Limits
Symbol

Min

Characteristic

Max

Units

0.45

Vdc

VCC = Min, 10L = 16 mA

Conditions

Vdc

Guaranteed Input High Voltage for All Inputs

VOL

Output Low Voltage

VIH

Input High Voltge

VIL

Input Low Voltage

0.8

Vdc

IlL

Input Low Current

-400

pAde

VCC = Max, Vin = 0.45 V

IIH

Input High Current

40

pAde

VCC = Max. Vin = 5.5 V

loff

Output Current (High Z)

50

pAde

VCC = Max. Vout = 4.5 V

2.1

-50
lOS

Output Current Short Circuit to Ground

-20

VOH

Output High Voltage

2.4

VCD

Input Diode Clamp Voltage

ICC

Power Supply Current

,-100

Guaranteed Input Low Voltage for All Inputs

VCC = Max. Vout = 0.45 V
mAde

VCC = Max

Vdc

10H = -5.2 mA

-1.5

Vde

VCC = Max. lin = -12mA

130

mAdc

TA = +125°C

155

mAde

TA = 25°C

170

mAde

TA = -55°C

MOTOROLA MEMORY DATA

VCC = 5.5 V.
All Inputs Grounded

MILITARY 93425

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted)

AC TEST LOAD AND WAVEFORMS

INPUT PULSES

LOADING CONDITIONS
All INPUT PULSES

~
+- i - -

---------_~
__

Vee

3.5Vp.p

I

I 1
=--t 1--'0ns
30pF

93425

~-

lOAD A

-1- ....-_'_0%_ _
I 1

--t

1--'005

-- ------1-

-r- II -- - - - --/~
1 :
'~.p-~~\
-

lOADB

I

- --I

I

90%

I

- - - -

10%
00%

t-- 10 05

--t f-- 10 ns

Units

Conditions

93425/BElBF
Symbol

Characteristic (Notes 2. 4)

Min

Max

READ MODE
tACS
tzRCS
tAA

DELAY TIMES
Chip Select Time
Chip Select to High Z
Address Access Time

ns
45
50
60

WRITE MODE
tws
twR

DELAY TIMES
Write Disable to High Z
Write Recovery Time

45
50

tw
twSD
twHD
twSA
twHA
twscs
twHCS

INPUT TIMING REQUIREMENTS
Write Pulse Width (to guarantee write)
Data Setup Time Prior to Write
Data Hold Time After Write
Address Setup Time (at tw = Min)
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time

See Test Circuit
and Waveforms
ns

See Test Circuit
and Waveforms

ns

40
5.0
5.0
15
10
5.0
5.0

See Test Circuit
and Waveforms

•

READ OPERATION TIMING DIAGRAM

PROPAGATION DELAY FROM CHIP SELECT

cs

CHIP SELECT

Dout

lOAD A
Dout

lOADB

PROPAGATION DELAY FROM ADDRESS INPUTS

;oo.,-1}==
lACS

HIGHZ

-----

:O~ESS~, ~--------------I
I

~~Aou_~_m____~i___________~
: - - 1M

(ALl llME MEASUREMENTS REFERENCED TO 1.5 VI

MOTOROLA MEMORY DATA

---i

MILITARY 93425

WRITE CYCLE TIMING

cs

\

CHIP SElECT

/

"-

J

\I

M-A9
ADDRESS

\I
/1\

/1\
\I

\I

Ojn
DATA INPUT

/1\
I--tw-

WE
WRITE ENABLE

1\

I--

twsD ~

- - twsA -

I---

twscs - - -

---

::-:- twHD

f-- twHA -.I
I--- twHCS
-1--

-

-- ~
______
rHIGHZ

LOAD A

Do",
DATA OUTPUT

~

_

twR

HIGHZ

LOADB

(ALL ABOVE MEASUREMENTS REFERENCE TO 1.5 VI

WRITE ENABLE TO HIGH Z DELAY
5V

WE
WRITE ENABLE

~1.5V~

lIOn

tZWs--1~___ _

~X¥~ OUTPUT

93425

"0" LEVEL
r- - - - --~"I::'''~LE:::VE::-L-'''f'= 0.5 V

5pF

HIGH Z

Dout
DATA OUTPUT

LOADC

•

PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

cs

-4'~

CHIP SELECT
DOUI

DATA OUTPUT
"~. LEVEL
--"'''I'''''LE~V'::EL"--"l

, . - - - - - HIGHZ
0.5V

-------..1-

Do",
DATA OUTPUT

~

0.5 V
____ HIGHZ

!ALL tzxxx PARAMETERS ARE MEASURED AT A DELTA OF 0.5 VFROM THE LOGIC LEVEL AND USING LOAD CI
NOTE 2: DC and AC specifications limits guaranteed with 500 linear feet per minute :"':own air.

/lJA (Junction to
Ambientl
Package

Blown

Still

/lJC (Junction to Casel

E Suffix
F Suffix

50·CIW
55·CIW

85·CIW
90·CIW

15·CIW
WCIW

NOTE 3: Output short circuit conditions must not exceed 1 second duration.
NOTE 4: The maximum address access time is guaranteed to be the worst case bit in the memory.

MoTOROLA MEMORY DATA
8-44

Reliability Information •

MOTOROLA MEMORY DATA
9-1

MOTOROLA CORPORATE QUALITY GOAL
IMPROVE PRODUCT AND SERVICES QUALITY TEN TIMES BY 1989
AND AT LEAST ONE HUNDRED FOLD BY 1991.
ACHIEVE SIX SIGMA CAPABILITY BY 1992.
With a deep sense of urgency, spread dedication to quality to every facet of the
corporation and achieve a culture of continual improvement to ASSURE TOTAL
CUSTOMER SATISFACTION. There is only one ultimate goal: zero defects in everything we do.
signed:

•

BOB GALVIN
Chairman

BILL WEISZ
Vice Chairman

JOHN MITCHELL
President

GEORGE FISHER
Deputy to Chief
Executive Office

GARY TOOKER
Chief to Corporate
Staff Officer

JACK GERMAIN
Motorola Director
of Quality

JIM LINCICOME
Government Electronics
Group

CARL LINDHOLM
International
Operations

LEVY KATZIR
New Enterprises

JIM NORLING
Setniconductor Products
Sector

STEVE LEVY
Japanese Operations

DON JONES
Chief Financial
Officer

JIM DONNELLY
Personnel

RAY FARMER
Communications Sector

ED STAIANO
General Systems
Group

GERHARD SCHULMEYER
Automotive & Industrial
Electronics Group

MOTOROLA MEMORY DATA
9-2

DIVISION QUALITY STATEMENT
MOTOROLA MOS MEMORY PRODUCTS DIVISION
COMMITMENT TO SIX SIGMA
WORLD CLASS
The Memory Products Division staff are pleased to announce our commitment to be a
World Class MOS Memory supplier. This means more bullet proof designs which can tolerate
handling, processes at the limit and beyond, and outstanding control of the manufacturing
processes such that a product design which is marginal will still yield consistent quality
performance.
The Memory Products Division fully endorses the Motorola Corporate goal of improving
product and service quality ten times by 1989 and one hundred fold by 1991.
Through our quality improvement process using SIX SIGMA methodology we can and will
accomplish being the best memory supplier through WORLD CLASS product margins and services in their truest sense.
ENDORSEMENTS:

t2.~
Bud Broeker

Weldon Knape

?r'~

Roger Kung

Bill Bowers

/

EJQ P&il

MOTOROLA MEMORY DATA

Bill Pfaff

Jim Eachus-

..

SIX SIGMA

~

®

MOTOROLA

OUR SIX SIGMA CHALLENGE
Approximately 2,700 parts per million parts/steps will fall
outside the normal variation of ± 3 Sigma, 888 Figure 1. This,
by itself, does not appear disconcerting. Howevar, when we
build a product containing 1,200 parts/steps, we can expect
3.24 dafects par unit (1200 x 0.0027), on an avarage. This
would result in a rolled yield of less than 4%, which means
fewer than 4 units out of evary hundred would go through the
entire manufacturing process without a defect, see Table 1.
Thus, we can see that for a product to be built virtually
defect-free, it must be designed to accept characteristics that
are Significantly more than ±3 Sigma away from the Mean.
It can be shown· that a design that can accept twice the
normal variatIon of the process, or ±6 Sigma, can be expected to hava no more than 3.4 parts per million defectiva
for each characteristic, evan if the process mean were to shift
by as much as ± 1.5 Sigma, see Figure 1. To quantify this,
Capability Index (Cp) is used, where:

WHAT IS SIX SIGMA?
Six Sigma is the required capability level to approach the
Standard. The Standard is Zero Defects. Our goal is to be
best-in-class in Product, Sales, and Service.
WHY SIX SIGMA?
The performance of a product is determined by how much
margin exists between the process characteristics required by
the design, and the actual value of those characteristics. These
cheracteristics are produced by processes in the factory,' and
at the suppliers.
Each process attempts to reproduce its cheracteristics identically from unit to unit, but within each process some variation
does occur. For some processes, such as those which use
real-time feedback to control the outcome, the variation is
quite small, and for others it may be quite large.
Variation of the proceSs is measured in Standard Deviations
(Sigma) from the Mean. The normal variation, defined as process width, is ±3 Sigma about the mean.

lOOk

~ Cp 1
-Cpk 0.5

TOTAL

Cp 1.33
Cpk 0.83
Cpk

design specification width
process width

Table 1. Rolled YIeld

• CENTERED

_ • ± 1.5 SIGMA SHIFT

10k

=== Cp

Cp

DEFECTS
PER IIIIT

1

5.:1
4.8
3.9
3.5
3.2
3.0
2.3
1.9
1.8
1.4
1.2
1.0
0.9
0.8
0.7
0.8
0.51
0.43
0.38
0.29
0.22
0.16
0.10
0.05
0.00

lk
Cp 1.87
Cpk-1.17

=== =

Cp Cpk-1.33

II

Cp-2
Cpk 1.5

Cp Cpk-l.87

O. 1

0.D1

0.00 1
2

Cp-Cpk 2

4

5

ROLLED
THROUGHPUT
YIELD 1%1
0.5
1.0
2.0
3.0
4.0
5.0 .
10
15
20
25
30
37
40
45
50

55
80
65
70
75
80
85
90

95
100

DESIGN SPECIFICATION WIDTH (SIGMA)
ROLLED THROUGHPUT YIELD Ill) = 100 e- diu

Figure 1. Stendard Deviations from Mean

MOTOROLA MEMORY DATA
9-4

A design specification width of ± 6 Sigma and a process
width of ±3 Sigma Vields a Cp of 12/6 =2. However, as shown
in Figure 2, the process mean can shift. When the process
mean is shifted with respect to the design target mean, the
Capability Index is adjusted with a factor k, and becomes Cpk.
Cpk=Cp(l-k), where:
k

Table 2. Overall Yield vs Sigma
(Distribution Shifted ± 1.5 (7)
lUMBER OF
PARTS (STEPSI

10
20
40
60
80
100
150
200
300
400
500
600
700
800
900
1000
1200
3000
17000
38000
70000
150000

proCIl8S shift
design specification width/2

The k factor for ± 6 Sigma design with a 1.5 Sigma process
shift = 1.51(12/2) =0.25, and the Cpk=2(1-0.25) = 1.5.
In the same case of a product containing 1,200 parts/steps,
we would now expect only 0.0041 defects per unit
(1200 x 0.0000034). This would mean thet 996 units out of
1,000 would go through the entire manufacturing proCIl8S without a defect (see Table 2).
It is our fIVe year goal to achieve ± 6 Sigma capability in
Product, Sales. and Service.

±3u

±4u

±5u

±Bu

93.32
61.63
50.08
25.08
6.29
1.58
0.40
0.10

99.379
95.733
93.96
88.29
77.94
68.81
60.75
53.64
39.38
28.77
15.43
8.28
4.44
2.38
1.28
0.69
0.37
0.20
0.06

99.9767
99.839
99.768
99.536
99.074
98.614
98.156
97.70
96.61
95.45
93.26
91.11
89.02
86.97
84.97
83.02
81.11
79.24
75.88
50.15
0.02

99.99966
99.9976
99.9966
99.9932
99.9864
99.9796
99.9728
99.966
99.949
99.932
99.898
99.864
99.830
99.796
99.762
99.729
99.695
99.661
99.593
98.985
94.384
87.880
78.820
80.000

_(%J
_ _ _ _(%J
_ _ _ _llW
_ _ _ _llW
__

MEAN

NUMEROUS DEFECTS
(6210 PPMI

-6u

-5u

-4u -3u
: ..

-2u

-lu

lu

2u

3u

4

u

5u

6u

± FOUR SIGMA DESIGN SPECIFICATION WIOTH----i.~i

Figure 2a. Four Sigma Capability
MEAN

Figure 2b. Six Sigma Capability

MOTOROLA MEMORY DATA
9-5

II

QUALITY MONITORING

RELIABILITY STRESS TESTS

Average Outgoing Quality (AOQ) refers to the number of
devices per million thet are outside specification limits at the
time of shipment. Motorola has continually improved its outgoing quality, and has aatabllahad a goal of zero defects. This
lavel of quality will lead to vendor certification programs with
many of our customers. The program ensuras a certain level
of quality, thus allowing a customer to either reduce or eliminate the need for incoming Inspections.
By paying strict attention to quality at an early stage, the
possibility of failuras occurring further down the line is greatly
minimized. Motorola's electrical parametric testing eliminatea
devices that do not conform to electrical specification. Additional parametric tasting on a sample basis provides date for
continued improvement.

The following summary gives brief descriptions of the various reliability teste Included In both reliability qualification and
monitor programs. Not all of the teste listed an, lierf6rmed by
each program and other teste can be performed when appropriate. Refer to Table 3.
Table 3. Stresses and Typical Str_ Conditions
Stress

Typical Str... Condition

High Temperatura Operating Life,
Dynamic or Static

125°C, 6.0 V

Temperature cYcle

- 66°C to + 150°C

Tharmal Shock

-66°C to +l50oe

Air to Air
Uquid to Uquid
Temperature Humidity Bias

AVERAGE OUTGOING QUALITY (AOQ) CALCULATION

Autoclave

AOQ in PPM = (Process Average)
-(Lot Acceptance Rate)-(106)
P
A
Totel Projected Reject Devices*
rocess wrage
Totel Number of Devices

-Lot Size

Totsl Number of Devices =Sum of all the units in each
submitted lot
pte
Rate -1
cce nce
-

Number of Lote Rejected
Number of Lots Tested

106 =Conversion to parts per million (PPM)

II

121°C, 100% RH, 15 psig

Pressure Temperature Humidity
Bias

148"e, 90% RH,
44 psig, 5.0 V

Low Temperatura Operating Life

Ooe/25°e, 6.0 V

HIGH TEMPERATURE OPERATING LIFE
High temperature operating life (HTOL or HTRBI testing is
performed to accelerate failure mechenlsms that are thermally
activated through the application of extreme temperaturas and
the use of biased opereting conditions. The temperature and
voltage conditions used in the stress will vary with the product
being strassed. However, the typical stress ambient is 125°C
with the bias applied equal to or greater than the data sheet
nominal value. All devices used in the HTOL test are sampled
directly eftar final electrical test with no prior bum-in or other
prascreening unless called out in the normal production flow.
Tasting can either be performed with dynamic signals applied
to the device or in a static bias configuration.

P . cted R'
D'
Defects in Sample
roJ8
eject evlC88 =
Sample Size

Lot A

66°C, 66% RH, 5.0 V

MARKING PERMANENCY, HERMETICITY, AND
SOLDERABILITY MONITORS
Marking permanency testing is performed per Motorola
specification. The procedure Involves soaking the device in
various solvents, brushing the markings, and then inspecting
the markings for legibility.
Hermeticity monitoring includes teste for both fine and grosa
leaks in the hermetic peckage seal.
Soiderebility testing is used to ensure that device leads can
be soldered without voids, discoloretion, flaking, dewetting,
or bridging. Typically, the test specifias steam preconditioning
followed by a 235° to 260°C solder dip and microscope inspection of the leads.

TEMPERATURE CYCLE
Temperature cycle testing acceleratea the effects of thermal
expension mismatch among the different components within
a specific die and packaging system. This test is typically
performed per MIL-STD-883 or MIL-STD-750 with the minimum end maximum temperaturas being -66°C and + 150°C.
During temperature cycle testing, devices are inserted into a
cycling system and held at the cold dwell temperature for at
least ten minutea. Following this cold dwell, the devicas are
heated to the hot dwell where they remain for another ten
minute minimum time period. The system employs a circulating
air environment to assure rapid stabilization at the specified
temperature. The dwell at each extreme, plus the two transition
times of fIVe minutea each (one up to the hot dwell temperature, another down to the cold dwell temperature), constitute
one cycle. Test duration for this test will vary with device and
peckaging system employed.

RELIABILITY MONITORING
Motorola recognizas the need to monitor established MOS
Memory products to maintein the level of quality and reliability
demonstrated through the internal and joint qualification processas. Motorola maintains a system of monitor programs thet
provide monthly feedbeck on the extensive matrix of Motorola
fabrication, assembly, and tasting technologies that produce
our products. As with qualification activity, great care Is taken
to assure the accuracy and quality of the date generated.

THERMAL SHOCK
The objective of thermal shock testing is the same as thet
for temperature cycle testing-to emphasize differences in
expansion coefficients for components of the peckaging system. However, thermel shock provides additional stresa in that

*All rejects: visual, mechanical, and electrical (dc, ac, and high/low
18mperatural.

MOTOROLA MEMORY DATA
9-6

the device is exposed to a sudden change in temperature due
to the transfer time of ten seconds maximum as well as the
increased thermal conductivity of a liquid ambient. This test
is typicelly performed per MIL-STD-883 or MIL-STD-750 with
the minimum and maximum temperetures being - 65°C and
+ 150°C. Devices are placed in a fluorocarbon bath and cooled
to minimum specified temperature. After being held in the cold
chamber for five minutes minimum, the devices are transferred
to an adjacent chamber filled with fluorocarbon at the maximum specified temperature for an equivalent time. Two fiveminute dwells plus two ten-second transitions constitute one
cycle.

VARIABLE FREQUENCY VIBRATION
This test is typically performed per MIL-STD-883 or MILSTD-750 and is used to examine the ability of the device to
withstand deterioration due to mechanicel resonance. The typical test condition is: peak acceleration = 20 g, frequency
ranga=20 Hz to 20 kHz, and t=48 minutes.
CONSTANT ACCELERATION
This test is typically performed per MIL-STD-883 or MILSTD-750 and is used to indicate structural or mechanical weak~ in a device/paclcaging system by applying a severe
mechanical stress. A typical test condition used is as follows:
stress level =30 kg, orientstion=Y1 plane, and t=1 minute.

TEMPERATURE HUMIDITY BIAS
Temperature humidity bias (THB or ti3TRB) is an environmentel test performed at a temperature of 86°C and a relative
humidity of 86%. The test is designed to measure the moisture
resistance of plastic encapsulated circuits. A nominal static
bias is applied to the device to create the electrolytic cells
necessary to accelerate corrosion of the metallization.

QUAUTY SYSTEMS
A Global Quality S~m is key to achieving our goal of
"Best In Class". Quality systems are implemented in wafer
fabrication, assembly, final test, and distribution world wide.
Figure 3 depicts Quality Assurance involvement and the techniques applied in the general flow of product and Figure 4
shows Memory Manufacturing locations world wide.

AUTOCLAVE
Autoclave is an environmentsl test which measures device
resistance to moisture penatration and the resultant effects of
galvanic corrosion. Conditions employed during the test include 121·C, 100% relative humidity, and 15 psig. Corrosion
of the die is the expected failure mechanism. Autoclave is a
highly accelerated and destructiva test.

I

INC~NG

This test is performed to accelerate the effects of moisture
penatration with the dominant effect being corrosion. The test
detects similar failure mechanisms as THB but at a greatly
accelerated rate. Conditions usually employed during the test
are a temperature of 148°C, pressure of 44 psig or greater, a
relative humidity of 90%, and a bias level which is the nominal
rating of the device.

I

WAFER FAB

I

ASSEMBLY

I

LOW TEMPERATURE OPERATING LIFE
This test is performed primarily to accelerete hot carrier
injection effects in semiconductor devices by exposing them
to room ambient or colder temperatures with the use of biased
operating conditions. Threshold shifts or other paremetric
chenges are typically the basis for failure. The length of this
test will vary with temperature and bias conditions employed.

I

MONITOR

AUDIT

X

X

X

X

I-

X

X

X

X

I-

X

X

X

X

BURN·INITEST

I-

X

X

X

X

DISTRIBUTION

1--

X

X

X

X

(WAFERS, CHEMICALS,
ETC.)

PTHB (PRESSURE-TEMPERATURE-HUMIDITY-BIASI

r-

QUALITY ASSURANCE TECHNIQUES
SAMPlING SPC

~

~

t
t

Figure 3. General Product Flow
Direct Customer interaction ensures the receipt of product
that meets all of their requirements 100% of the time. In fact,
the MOS Memories Reliability and Quality Assurance department has devised a customer advocate list that assigns key
Reliability and Quality Assurance personnel to apecific customers in order to facirrtate any inquiry regarding quality, reliability, or any other issue they may want to discuss.
All procesass and procedures that relate to the manufacturing of MOS Memories are fully documented, and regular
audits are performed to ensure continuous adherence to proper
procedures. We are always striving to produce and reproduce
the highest quality product eveilable throughout the world.
MOS Memory Products Division promotes the concept of
statisticel process controls throughout the entire manufacturing process. This is exemplified by our commitment to in-depth
statistical process control training programs for everyonefrom the line operator to upper management. Favorable resulta
have already been realized from the initial phaass of implemeirtstion, with much more to follow.

SYSTEM SOFT ERROR
S~m soft error is designed to detect errors caused by
impact ionization of silicon by high energy particles. This stress
is performed on a system level basis. The system is operated
for millions of device hours to obtain an accurate measure of
actual system soft error performance.

MECHANICAL SHOCK
This test is typically performed per MIL-STD-883 or MILSTD-750 and is used to examine the ability of the device to
withatend a sudden change in mechanical stress typically due
to abrupt changeS in motion as seen in handling, transportation, or actual use. Tha typical test condition would be as
follows: acceleration = 1500 g, orientation = Y1 plane, t = 0.5
ms, and number of pulass = 5.

MOTOROLA MEMORY DATA
9-7

Figure 4. Wafar Fab/Assembly/Flnal Test Locetions
The MOS Memory Products Division maintains a World
Wide Quality Assurance eystem that is second to none. Daily
status reports ara raceived from remota locations, and any
problems that arise are tackled on a timely basis. The MOS
Memory Products Division is also a leader in accurata and
efficient methods of quality data collection and reporting.
Every unit that the MOS Memory Products Division produces is coded 80 that complete traceability is maintained,
including visibility to the wafer and assembly lot level. The
Quality System ensures that we cen provide any specific procassing information to our customers on requeat.

issues such as device labeling, number of customers, sample
quantities, pricing and stocking levels, and open-order-entry
timing. Decisions regarding these itams are made jointly by
marketing, design, product, and reliability personnel.

JOINT QUALIFICATION
As a result of the rigorous discipline used for intamal qualificetion of Motorola MOS Memory products, our customers
can benefit from joint qualification activities. Motorola's clearly
defined qualification procedures improve the customer's ability
to comprehend the qualification results in an effective manner
which aides in their qualificetion decision making procass.
Through parallel qualificetion activities between Motorola and
its customers, this procedure can cut qualificetion costs by
reducing duplication of effort, improving resource utilization,
and shortening introduction cycle time. This helpe to ensure
competitive edge advantages for our customera.
Joint Qualification activities result in a partnership type of
intaraction between Motorola and its customers on an engineering level. This assists our customers in two critical areas.
First, it allows them to understand more clearly the strengths
and weakn_ of Motorola's products. Secondly, our customers can make clear decisions concerning which stresses
they need to concentrete on during their intamal qualificetion
activitiss.

INTERNAL QUALIFICATION DISCIPLINE

•

Motorola recognizes the need to esteblish that all MOS
Mamory devices, both new products as well as existing ones,
reach and maintain a level of quality and reliability that is
unsurpeseed in the electronics marketplace. To ensure this,
intamal qualification requirements, procedures, and methods
as well as vendor qualification specifications have been developed. These activities are intended to provide a consiatent,
comprehensive, and methodical approach to device qualificetion and to improve our customer's understanding of
Motorola's qualification results and their subsequent applicetion implications.
For qualification results to be velid and acceptable, the collected data must be proven accurate to the higheat possible
confidence level. Therefore, a complete device history and
data log is kept with any lost or missing deta potentially leading
to test ·results that are unusable for qualificetion purpoaes.
Testing conditions and peas/feU criteria are esteblished before
streaaing begins. Strict adharance to thesa criteria and the USB
of control devices insure that the test results are velid and
meaningful.
New MOS Memory devices which are under development
or in the prototype stage are subject to requirements defined
for the three levels of the development cycle. These levels are
the alpha, beta, and Introductory p~ of device development. Each phase contains guidelines and controls concerning

HISTORICAL PERFORMANCE
Over the course of the last five years, significant achievements have been made on quality and delivery performance.
The Six Sigma methodology will assist the MOS Memory
Products Division in pursuit of our standerd of aro defects
and 100% on time delivery.
Figure 5 indicat88 the product Average Outgoing Quality
performance as measured in parts per million. .
As of October 1988 our average outgoing quality was below
60 parts per million. We are striving to reach Six Sigma.

MOTOROLA MEMORY DATA
9-8

1988 MALCOLM BALDRIGE
NATIONAL QUALITY AWARD
Motorola won the first Malcolm Baldrige National Quality
Award. The award recognizes the achievements of U.S. manufacturing and service companies. The award was established
in 1987 to promote quality awareness, recognize the achievements of U.S. companies, and publicize successful quality
strategies. Our quality process was examined for corporate

quality leadership, information and analysis, planning, human
resource utilization, quality assurance, quality improvement
results, and Customer Satisfaction. Our fundamental objective- Everyone's overriding responsibility is Total Customer
Satisfaction. Six Sigma Quality is a key initiative for the
achievament of our fundamental objective.

1200.r-----------------------------------------__--------------________________- ,

- - - - ELECTRICAL ADa
- - - - - - VISUALADa

l

e,

~

600

200

1984

Figure 5. Motorola MOS Memory Products Division
Average Outgoing Quality-4 Week Average World Memory

MOTOROLA MEMORY DATA

II

II

MOTOROLA MEMORY DATA
9-10

DRAMs
DRAM Refresh Modes (AN9871 ..................•......•..•...........
Page, Nibble, and Static Column Modes: High-Speed, Serial-Access Options
on 1M-Bit+ DRAMs (AN986I ........................................
Fast Static RAMs
Avoiding Bus Contention in Fast Access RAM Designs (AN971 I ........ . . ..
Avoiding Data Errors with Fast Static RAMs (AN9731 .....•.•.•...•.......
Special Application Static RAMs
25 MHz Logical Cache for an MC68020 (AN9841 ...........•.....•.•.....
Designing a Cache for a Fast Processor (AR2701 ...................••....
EnhanCing System Performance Using Synchronous SRAMs (AR2601 .•..•.
High Frequency System Operation Using Synchronous SRAMs (AR2581 ....
Motorola's Radical SRAM Design Speeds Systems 40% (AR2561 •.•..•...•

10-2
10-4
10-8
10-12
10-15
10-29
10-35
10-39
10-46

Applications Information

MOTOROLA MEMORY DATA
10-1

II

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN987

DRAM Refresh Modes
DRAMs offer the lowest cost per bit of any memory, and
for that reason are enormously popular in a wide range of
applications. This low cost per bit is achieved with a very simple
bit cell design, among other things, but rooted in this simplicity
are some inherent drawbacks. One major limitation is the need
to refresh each memory bit at regular intervals. This note
discusses what refresh is, the reasons refresh is required for
DRAM operation, and the various types of refresh available
on the Motorola 1M x 1 and 256K x 4 DRAMs. Specific comments refer to the 1M x 1 85-ns DRAM. Refer to specific device
data sheets for analogous information on other devices.
The heart of any memory device is the bit cell. A 1M DRAM
has 1,048,576 of these cells in the memory array. Each cell
holds a single bit of information in the form of a high or low
voltage, where high voltage = a binary "1" and low voltage = a
binary "0". The DRAM bit cell consists of one transistor and
one capacitor. The transistor acts as a switch, regulating when
the capacitor will charge and discharge, while the capacitor
stores a high or low voltage charge.
All capacitors leak over time, slowly losing the charge stored
in them, regardless of how carefully they are constructed.
Junction and dielectric leakage are two capacitor discharge
paths that are characteristic of the DRAM bit cell, and both
are effected by temperature. The capacitor in the bit cell can
hold a small charge, on the order of 35-125fF (fF= 1 x 10- 15
farads). As this charge dissipates through leakage paths, the
small difference between a "1" and a "0" diminishes. If nothing
is done to restore the charge on the capacitor to its initial
value, the sensing circuitry on the DRAM will eventually be
unable to detect a charge difference and will read the cell as

a "0".
Thus, all the capacitors in the memory array must be periodically recharged, or refreshed. Refresh is accomplished by
accessing each row in the array, one row at a time. When a
row is accessed, it is turned on, and voltage is applied to the
row, recharging each capacitor on the row to ;is initial value.
Specified refresh time 0!1 the 1M x 1 DRAM is 8 milliseconds;
every row must be recharged every 8 milliseconds. This is a
vast improvement over refresh times required for earlier gen- '
erations of DRAMs. The 16K x 1 DRAM required refresh every
2 milliseconds, the 256K x 1 Di'lAM requires a refresh every 4
milliseconds. Longer refresh times mean more time available
for access to memory, and lass time required to refresh the
device.
Design and operation of the DRAM allow only one row to
be refreshed at a time; 512 refresh cycles are required to refresh
the entire 1M x 1 memory array. The array is actually 1024
rows by 1024 columns, but it operates electrically like two half
arrays of 512 rows by 1024 columns. During refresh, every row
is treated as if it runs through both halves of the array, refreshing 2048 column locations (bit cells) per row. This design
results in fewer refresh cycles required to recharge the entire
array, since only 512 rows need to be accessed, rather than
1024.

Refresh can be performed in either a single burst of 512
consecutive refresh cycles (one cycle per row) every 8 milliseconds, or distributed over time, one refresh cycle every 15
microseconds (8 milliseconds per 512 rows = 15.6 microseconds per row) on average, or some combination of these two
extremes. As long as every row is refreshed within 8 milliseconds, the actual method used is best determined by system
use of the DRAM. The burst takes 84 microseconds to complete (165 nanoseconds per row x 512 rows for 85 nanoseconds
per device). During this burst refresh time, no memory operations can be performed on the device. Distributed refresh
disables memory access for 165 nanoseconds every 15
microseconds.
The 1M x 1 DRAM can be refreshed in three ways: RAS
only refresh, CAS before RAS refresh, and hidden refresh. In
addition, any normal read or write refreshes all 2048 bit cells
on the row accessed. Regardless of the refresh method used,
the time required to refresh one row is the random read or
write (RAS) cycle time (tRC)' When operating the device in
page, nibble, or static column mode, only the row being accessed is refreshed. The device must be in normal random
mode to utilize any of these specific refresh methods.
RAS only refresh requires external row counters, to ensure
all rows are refreshed within the specified time, and externallysupplied row addresses. CAS before RAS relies on internal
row counters and internally generates the address of the next
row to be refreshed. Hidden refresh is a variation on CAS
before RAS refresh that holds valid data at the output while
refresh is occurring. Whenever the device is in a refresh cycle,
neither a read nor a write operation can be performed. Hidden
refresh allows the device to be read ahead of refresh, then
holds the valid data at the output while refresh cycles are in
progress. It appears' that the refresh is hidden among data
cycles because valid data is maintained at the' output.
RAS only refresh is performed by supplying row addresses
AO-AS and completing a RAS cycle (tRC); switching RAS
from inactive (high) to active (low),holding RAS low (tRAS),
then switching back to high, and holding RAS high (tRP). AS
is ignored during RAS only refresh, since this address normally
determines which half of the array, is to be accessed. CAS
must be held high through this RAS cycle, hence the name
RAS only refresh. An external row counter is required for this
refresh method. See Figure 1.
CAS before RAS refresh is performed by switching CAS
from high to low while RAS is high, then switching RAS low
(tCSR). This reversal of the usual clock order activates an
internal row counter that generates addresses to be refreshed;
external addresses are ignored in this cycle. CAS must be held
low (tCHR) after RAS transitions to low. After that time it can
either be held low or switched to high. See Figure 2. The CAS
before RAS refresh counter test, specified on all DRAM data
sheets that offer this type of refresh, is used to check for
proper operation of the internal row counters and correct address generation.

MOTOROLA MEMORY DATA
10-2

DRAM REFRESH MODES (AN987)

method of refresh allows refresh cycles to be mixed within
read and write cycles. During the refresh cycle, a write operation cannot be performed. See Figure 3.
Refresh is an integral and necessary part of DRAM operation. Substantial improvement has been made in increasing
the time between refresh cycles, but as long as the bit cell
design utilizes a capacitor, periodic recharging will be required.
Three methods of refresh are available on the 1M x 1 DRAM:
RAS only, CAS before RAS, and hidden refresh. The Motorola
1M x 1 and 256K x 4 wi" work in virtually a" systems as a result
of flexibility provided by this assortment of refresh methods.

Hidden refresh is a CAS before RAS refresh that has been
initiated during a read or write operation. At the end of a
typical read cycle, CAS would be switched to high before RAS,
tuming off the output. In a hidden refresh cycle, RAS is
switched to high, concluding the RAS cycle ItRC), while CAS
is held low. RAS is held high (tRP), then switched low, beginning another RAS cycle. As long as CAS is held low, data
is valid at the output, resulting in a long read cycle. Since data
can be read while the device is being refreshed, the refresh
operation(s) appears to be hidden by the read cycle. The same
refresh can be performed after a writa cycle is initiated. This

H-

iiiS

LH-

CAS
L-

:~OO<_..;.;ADD""R",,~~_SS""'J

AO-AS

Figure 1.

liAS Only Refresh Cycle

HRAS
LH-

CAS
LH-

)

Q (DATA OUTI

L-

HIGH Z

Figure 2.

CAS Before RAS

MEMORY
HRAS

REFRESH

CYCLEr'-

~

Refresh Cycle

CYCLEr'-

REFRESH
CYCLE

LH-

CA!
L-

HQ (DATA OUTI

L-

I
\c

} I-

YAUD DATA OUT

IRc

IRC

Figure 3. Hidden Refresh Cycle

MOTOROLA MEMORY DATA

10-3

IRC

MOTOROLA

-

SEMICONDUCTOR

APPLICATION NOTE

AN986

Page, Nibble, and Static Column Modes: HighSpeed, Serial-Access Options on 1 M-Bit + DRAMs
The 1M-bit ~nd higher density DRAMs offered by Motorola,
in addition'to operating in a standard mode at advertised access
times, have special operating modes that will significantly decrease access time. These are page, nibble, and static column
modes. All th,ree m9des are available in the 1M x 1 configuration; page and static column modes are also available on the
256K x 4 configuration. Read, write, and read-write operations
can be mixed and performed in any order while these devices '
are operating in either random or special mode.
The comments that follow refer specifically to successive
read operations for page, nibble, and static column modes on
the 1M x 1 device. The read operation is chosen for sake of
simplicity in illustrating these special operating modes. However, decreased access times will occur for all operations,
performed in any order, when the device is operated in any
of these modes. General operating comments apply to the
256K x 4 device as well.
'
All of theSe special operating modes are useful in applications that require high-speed serial access. Typical examples
include video bit map graphics monitors or RAM disks. Page

mode is the standard, available since the days of the 16K x 1
DRAM. Static column is the latest mode to be made available
on DRAMs, and nibble mode first appeared somewhere in
between. Page and static column offer the same column location access, but operate somewhat differently. Nibble is
unlike either of the other modes, but faster than both in its
niche. All modes are initiated eftar a standard read or write is
performed.
Page and static column modes allow access to any of 1024
column locations on a specific row, while nibble allows access
to a maximum of four bits. The location of the first bit in nibble
mode datermines the other bits to be accessed. Nibble mode
allows the fastest access of the three devices (tNCACI, all
other paramaters held equal, at about 1/4 the standard (tRACI
rate. Page and static column access times (tCAC, tAAI are,
respectively, about 1/3 ,and 1/2 the standard rate.
Cycle time' is a better indicator of relative speed improvement, since it measures the minimum time between any two
successive reads. Cycle time is approximately 1/4 for nibble
and 1/3 for page and static column modes, with respect to a

Table 1. Operating Characteristic Comparison
,Page

Paramater
Access TIme (ns)*

Cycle TIme (ns)*

tCAC
tNCAC
tAA
tRAC

25

tpc
tNC
tsc
tRC

50

RAS
CASorCS**
Addresses
Outputs"

Time to Read 4 Bits Ins)*
Time to Read 1024 Unique Bits (ns)*

x

*Values for a 1M 1 86-ns device.
Page:
4 bit read = tRAC + 3tPC
1024 bit read = tRAC + 10000pC
Nibble:

20

-

-

-

Order of Accessible Bits
Conditions

-

-

Accessible Bits

40

Static
Column

-

45
50

-

-

85
-

166

4

1024

All

Random

Fixed

Random

Random

Active
Cycle
Cycle
Cycle

Active
Cycle
N/A
Cycle

Active
Active
Cycle
Active

Cycle
Cycle
Cycle
Cycle

235

205

235

660

51,235

70,400

51,235

168,960

**CS on Static Column.

4 bit read = tRAC + 3tNc
1024 bit read=256.(tRAC+3tNC+tilP)

4 bit read = 4tRC
1024 bit read = 1024IRC

MOTOROLA MEMORY DATA
10-4

Random

1024

Static Column: 4 bit read = !RAC + 3tSC
1024 bit read = tRAC + 10000SC
Random:

Nibble

PA,GE, NIBBLE, AND STATIC COLUMN MODES ... (AN986)

random cycle time of 165 nanoseconds. When operated in
these high-speed modes, users will typically access most or
all of the bits available to that mode, once the mode has been
initiated. Thus the best measure of speed for nibble mode is
the rate at which four bits are read, while the rate at which
1024 bits are read is the best measure of page or static column
mode. When the actual operating conditions are considered,
as described elsewhere, the difference between tCAC, tNCAC,
and tM measurements hold relatively little significance.
Page mode is slightly more difficult to interface in a system
than static column mode due to extra CAS pulses that are
required in page mode. Static column generates less noise
than page mode, because output buffers and CS are always
active in this mode. Noise transients, generated every time
CAS is cycled from inactive to active, are thus eliminated in
the static column mode.

address counters increment at each CAS cycle, thus no external column addresses are required (unlike page or static
column modesl. After cycling CAS three times in nibble mode,
the address sequence repeats and the same four bits are accessed again, in serial order, upon subsequent cycles of CAS:

00,01,10, 11,00,01,10,11, ...
Nibble mode operation is initiated with a standard read or
write cycle. Row address is latched by RAS clock transition
to active, followed by column addresses and CAS clock. Performing a CAS cycle (.tNC) while RAS clock remains active
constitutes the first nibble mode cycle. Subsequent nibble
mode cycles can be performed as long as the RAS clock is
held active. The first access (data oud occurs at the standard
rate (tRAC). All of the read operations in nibble mode following
the initial operation are measured at the faster rate (tNCAC),
provided all other timing minimums are maintained (see Figure 2a). Nibble mode cycle time determines how fast successive bits are read (see Figure 2b).

PAGE MODE
Page mode allows faster access to any of the 1024 column
locations on a given row, typically at one third the standard
(tRACI rate for randomly-performed operations. Page mode
consists of cycling the CAS clock from active (lowl to inactive
(highl and back, and providing a column address, while holding
the RAS clock active (lowl. A new column location can be
accessed with each CAS cycle (tPCI.
Page mode is initiated with a standard read or write operation. Row address is latched by the RAS clock transition to
active, followed by column address and CAS clock active.
Performing a CAS cycle (tpcl and supplying a column address
while RAS clock remains active constitutes the first page mode
cycle. Subsequent page mode cycles can be performed as
long as RAS clock is active. The first access (data validl occurs
at the standard rate (tRACI. All of the read operations in page
mode following the initial operation are measured at the faster
rate (tCAcl, provided all other timing minimums are maintained
(see Figure lal. Page mode cycle time determines how fast
successive bits are read (see Figure lbl.

STATIC COLUMN MODE
This mode is useful in applications that require less noise
than page mode. Output buffers are always on when the device
is in this mode and CS clock is not cycled, resulting in fewer
transients and simpler operation. It allows faster access to any
of the 1024 column addresses on a given row, typically at half
the standard (tRAC) rate for randomly performed operations.
Static column consists of changing column addresses while
holding the RAS and CS clocks active. A new column location
can be accessed with each static column cycle (tSC).
Static column mode operation is initiated with a standard
read or write cycle. Row address is latched by RAS clock
transition to active, followed by column addresses and CS
clock. Performing an address cycle (tscl while RAS and CS
clocks remain active constitutes the first static column cycle.
Subsequent static column cycles can be performed as long as
the RAS and CS clocks are held active. The first access (data
out) occurs at the standard (tRAC) rate. All of the read operations in static column following the initial operation are
measured at the faster rate (tAAI, provided all other timing
minimums are maintained (see Figure 3a). Static column cycle
time determines how fast successive bits are read (see Figure 3bl.

NIBBLE MODE
Nibble mode allows serial access to two, three, Or four bits
of data at a much higher rate than random operations (tRACI.
Nibble mode consists of cycling the CAS clock while holding
the RAS clock active, like page mode. Internal row and column

H-

iilS

LH-

CAS
LHADDRESSES

LHQ (DATA

OUTI

LFigure 1a. Page Mode Read Cycle

MOTOROLA MEMORY DATA
10-5

PAGE, NIBBLE, AND STATIC COLUMN MODES ... (AN986)

RAS

HL- ____________________________________------------------------

I+--------tpc----___.,.........- - - - HLH

-~'Ir'"7'r""7\

: ,__..l-______--'\

L -....lC:-'¥->1..JI

,.....-;....,-.--------1

ADDR~SSES

"-l~,..JL.~~

.,....-.-_ _ _...J

"-~"_l'.~.JI..JI

1 + - - - - tCPA,-----+1

HQ (DATA OUT)

L~-----50M-----~

,Figure 1b. Page Mode Cycle Minimum Timing

,

HRAS

LHCAS

LHADDRESSES

LH-

Q (DATA OUT)

L-

BIT IDENTIFICATION

01

DO

10

Rgure 28. Nibble Mode Read Cycle

H-

ADDRESSES

o (DATA OUT)

L1+------40M---~~

Figure 2b. Nibble ,Moda Cycle Minimum TIming

MOTOROLA MEMORY DATA
10-6

11

PAGE, NIBBLE, AND STATIC COLUMN MODES ... (AN986)

HRAS

LH

CS
LHADDRESSES

LHQ (DATA OUT)

LFigure 3a. Static Column Mode Reed Cycle

H-

iM!

L-----------------------------------------__________________________
HL- ____________________________________________________________

Figure 3b. Static Column Mode Cycle Minimum nming

m
MOTOROLA MEMORY DATA
10-7

MOTOROLA

-

SEMICONDUCTOR

APPLICATION NOTE

AN971

Avoiding Bus Contention in Fast Access
RAM Designs
INTRODUCTION

SWITCHING FROM A READ TO WRITE MODE
With Elow (device selected), on the falling edge of IN (write
asserted) the RAM outPUt driver begins to turn off (highimpedance state). Depending on the input and output logic
levels, if sufficient time is not allowed for the output to fully
turn off before an input driver turns on, bus contention will
occur (see Figure 2a).
Figure 2a shows an example of a RAM trying to drive a bus
line low while an input driver is trying to drive the line high.
If the situation were reversed (RAM output high and the input
driver low), bus contention would still exist.
Of course the obvious way to avoid this type of bus contention is to make sure that the input buffer is not enabled
until the write low to output high-impedance (twLOZ) time is
satisfied (see Figure 2b). This specification is usually given on
most manufacturers' data sheets.
Another method to eliminate bus contention would be to
use E to deselect the RAM before asserting IN (low). This
allows the RAM output extra time to go into high·impedance
state before the input driver is enabled. E and IN are later
asserted low to begin a write cycle (see Figure 2c).

wti~n designing a bus oriented system, the possibility of
bus contention must be taken into consideration. Bus contention occurs when two or more devices try to output opposite
logic levels on the same common bus line.
This application note points out common causes of bus
contention when designing with fast static random access
memories and describes ways to eliminate or reduce
contention.

WHAT CAUSES BUS CONTENTION?
The most common form of bus contention occurs when
one device has not completely turned off (output in a highimpedance state) before another device is turned on (output
active). Basically, contention is a timing overlap problem that
results in large, transient current spikes. These large current
spikes not only generate system noise, but can also affect the
long term reliability of the devices on the bus (see Figure 1).

BUS CONTENTION AND FAST STATIC RAMs

SWITCHING FROM A WRITE TO A READ MODE
With E set low (device selected), on the rising edge of IN
(write terminated) the address or data-in changes before the
device has had a chance 'to terminate the write mode. If this
should occur, and depending on the input and output logic
levels, a bus contention situation could exist (see Figure 3).
To avoid address changing type bus contention requires thet
the address not change till the write recovery specification
(twHAX) is satisfied. To avoid bus contention caused by date
changing requires that the data-in remains stable for the duration of the data hold specification (twHDX)' Most of

Since memory devices are primarily used in bus oriented
systems, care must be taken to avoid bus contention in memory designs. Fast static RAMs with common I/O data lines (or
any high frequency device with common I/O pins) are the
most likely candidates to encounter bus contention. This is
due to the tight timing requirements that are needed to achieve
high-speed operation. If timing control is not well maintained,
bus contention will occur. The most common form of bus
contention for memories occurs when switching from a read
mode to a write mode or vice versa.
1 OF 4 DATA BUS LINES
01/01

Din

Dr

REV1

RAM WITH
COMMON DATA

02/02

liD

03/03
04/04

(HI

W (LI
Figure 1. Common I/O Bus Contention

MOTOROLA MEMORY DATA

10-8

TO INTERNAL
CIRCUITRY

AVOIDING BUS CONTENTION . .. (AN971)

£ LH _____________________

EH
L

IV H

ADDRESS

L
H

RAM
OUTPUT L

Vi L
_____;::IZI:....-__-.J1

INPUT
DRIVER

H

RAM H
OUTPUT L

BUS

_.J~~~C~!:)

'----

INPUT H

LINE
BUS CONTENTION

--l

DRIVER L

I--

BUS

Figure 28. Input Driver Enabled Prior to Disabling
RAM Output

H

Figure 3&. Data Setup Time Violation

£

H
L

[ H
L

H

WL

ADDRESS

RAM H

Vi

OUTPUT L
INPUT H ______~a~I____~~

DRIVER L
BUS H

LINE, L

____

H
L

RAM H
OUTPUT L

~r-

~.~----?

INPUT H
DRIVER L

- N O CONTENTlON-

, BUS

Figure 2b. Input Driver Dlsablad Prior to Enabling
RAM Output

<"'--------1---+--

al
VALID

H
L

X'--INV~~-LlD--

r!,A

BUS CONTENTION

_ H
E
L

wL

H

RAM H
OUTPUT L

_1-~~

INPUT H ____

DRIVER L

Figure 3b. Data Hold Time Violation

~a~I

_____

BUS H

LINE L

Figure 2c. Using

E to Avoid

~[~

_ H

EL

Vi

H
L

RAM H
OUTPUT L

____

~

---I

'...._-

al

I+tEHDX~

Bus Contention
Figure 3c. Using E to Avoid Bus Contention

Motorola's fast static RAMs specify write racovery and data
hold times of 0 ns. Howawr, it is always a good practice to
allow soma margin to take care of possible race conditions.
Both of these types of contention could also be avoided by
taking E high prior to taking IN high. This wi" give the RAM
output driver, time to go to a high-impedance state before IN
goes high. In this case E is used to terminate the write cycle
instead of IN (see Figure 3c).

OTHER WAYS TO ELIMINATE BUS CONTENTION
If the RAM has an output enable pin (~), synchronizing
schemes can be incorporated to help eliminate bus contention.
Taking G high wi" ensure that even when the RAM is in a read
mode the output will be in a high·impedance state. This will
allow the input driver to be enabled longer.

MOTOROLA MEMORY DATA
1~9

II

AVOIDING BUS CONTENTION . .. (AN971)

r -------- -----,
TO
INTERNAL
CIRCUITRY

I

I
I
I
I

I

I

MCM6164

ADDRESS

~k:==~====~~~
G
L

I

I

_ _ _ _ _ _ _ _ _ _ _ _ _ ..J

MC68000
Figure 4a. Using

G to Avoid

Bus Contention

Most advanced microprocessors, such as the MC68000 and
MC68020, have asynchronous bus control signals that take
advantage of fast memory devices with output enable pins.
Figure 4 shows one way to avoid bus contention using a
Motorola MC68000 interfaced to a Motorola 45-ns MCM6l64.
A more obvious way to eliminate bus contention is to use
slow memory de~ices. Slow memories have loose timing requirements that allow devices to fuliV turn off before another
device turns on. Of course this defeats the whole purpose of
fast static memory devices.
Another Obvious way to eliminate bus contention is to use
memory devices that have separata data 1/ 0 pins. In this way
the RIVii signal from the microprocessor can control a buffer
device to eliminate bus contantion (see Figure 5). However,
the industry is demanding RAM with common I/O because
these deviCes cost less and save system real estate.
Common I/O devices reduce package size since fewer pins
are needed. Smaller packages result in less PCB space requirement. Common I/O devices also eliminate the need for

Figure 4b. Timing Diagram of the MC68000
an extra buffer with its associated expense and space requirement. In general fast static RAMs configured greater than a
Xl will have common data I/O pins.
Another popular way to reduce bus contantion is to put a
current limiting series resistor on each bus line (see Figure 6).
The series resistor does not eliminata bus cdntention, but it
helps reduce the large transient currents associated with bus
contantion. However, series resistors increase access time as
well as increasing component count. The added access time
depends on the total bus capacitance (including the capacitance of the devices on the bus) and the total bus resistance.
The added delav should be added on to the point at which
bus contention ceases. The following formulas can be used
to determine the added access delav.

= R .C .In Vin(initial) - Vin(final)

t
HL
t
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VIL(max)-Vinlfinal)

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MOTOROLA

-

SEMICONDUCTOR
AR270/D

DESIGN APPLICATIONS

DESIGNING
A CACHE
FORA FAST
PROCESSOR

o wring the best perfonnance from the new
breed of superfast microprocessors, system designers frequently turn to external
caches. Direct mapped and set-associative
caches offer advantages, compaJ:ed with
fully associative caches. In designing an address-tag-and-comparator system for a direct-mapped or set-associative cache, engineers must consider issues such as the
speed of the hit, the address-bus loading, and the datablock size (see "What~ the Cache?".
Issues relating to the specific high-speed microprocessor also crop up. For instance, a system built around the
MC68030 microprocessor must support two-cycle reads
and writes related to the address-tag-comparatortiming.
Designers must also resolve questions of whether or not
and how to support a burst mode. To Sl.lpport this mode,
they must decide on address-tag and cache-data-RAM
requirements unique to the mode, such as automatically
incrementing addresses for the address tags and the
cache-data RAM. They must also consider the data setup
and hold timing requirements at the processor.

CACHE TAG RAMs

COMPARATOR CHIPS
HELP CREATE
A HIGH-SPEED CACHE
FOR THE MC68030

RICHARD CRISP, BRIAN BRANSCIi, AND RON HANSCIi
Motorola MOS Memory Products Div.,
3501 Ed Bluestein Blvd.,
Austin, TX 78762; (512) 928-6141.
Reprinted with permillion from Electronic Design © 1988 VNU _

Matching the speed of the MC68030 microprocessor,
the cache-tag comparators in the MCM4180, MCM62350,
and MCM62351, organized to handle 4 kwords by 4 bits,
compare data in the cache RAM with an external 4-bitwide data field. The comparison results appear on the
devices' Match pins. Each of the cache-tag devices is bulk
clearable and has read and write functions. Of all the
cache-system configurations pOssible with this MCM
family of RAMS, for a 32-bit-by-l6-kword system, a block
of four MCM4180s as tag valid-bits comparators and
four MCM62350s provide the fastest hardware arrangement,least bus loading, and lowest cost (Fig. 1).
The MCM4180 includes an Exclusive-Nor (XNOR)
comparator, which matches each bit position with the
stored data for a true result. This type of comparator
requires that every bit position match the stored data for
the result to be true.
The MCM62350 and MCM62351 supply a user-configurable comparator offering the .conventional XNOR
mode and an And-Or-Invert (AOI) mode. Unlike the
XNOR mode, the AOI comparator treats zeros in any bit
position as don't-care bits during the compare operation.
The AOI option is extremely useful for comparing status
bits often stored with each address tag. The status bits
can represent validating entry bits, which allow storing
multiple data entries with each address-tag entry (block
size = n), as well as individual so-called dirty bits needed
.
for copy-back caching schemes~
The MCM62350 and MCM62351 RAMs also feature bitset and bit-clear write cycles, which allow individual bits
to be unconditionally set or cleared through a mask.
Thus, any combination of the four bits in any particular
location can be set or cleared without having to read the
RAM, modify the data, and write it back as in a conventional SRAM. This feature is useful with the AOI com-

.... Publlcationa Inc. (Vol. 38 No. 23) October 13. 1988.

MOTOROLA MEMORY DATA
10-29

II

DESIGNING A CACHE ... (AR270)

1114'jijI"'QQ'ii.'iui$i

CACHE SYSTEMS
parator for storing status bits. Also. ' tag-comparator and in the data is how to generate ISTERM.
both the MCM62350 and the cache. Silice the synchronous bus
To avoid a wait state, the MC68030
MCM62351 have ground pins posi- protocol makes it possible to use asserts the worst-case Address
tioned to achieve minimum self-in- short bus cycles and supports burst- Strobe (I AS) signal 'at the same time
ductance in both DIP and small-out- mode accessing, the prudent design- that the ISTERM signal is activated.
er will also choose to use it for exter- As a result, cache designs for this
line J-type packages"
The MCM62350 differs from the mil cache interfacing to the MC68030 processor cannot generally use the
MCM62351 in that it offers a user- (see "A Synchronous Bus Proto-' I AS to signal the cache that a bus
configurable Match-output active col'~.
cycle is starting.
The primary challenge with timing
level. The MCM62351 has an active
Nevertheless, the address-tag
high open-drain Match output. Wire- the address-tag comparator is to' comparison must be qualified based
ORed connections of s'eparate Match avoid walt states when the processor on valid addre$ses that lAS anpins allow the comparison width to runs at a high frequency. Generally, nounces. Fortunately, a'signal called
expand efficiently.
'
only a hit in any given bus cycle External Cycle Start (lECS) is valid
The design of external caches for should assert the Synchronous Ter- slightly earlier than the addresses.
the MC68030 involves two major tim- mination Handshake (lSTERM) sig- ' Whenever the processor needs an ining problem areas-in the address- , nal. The first order of business, then; struction or data, it therefore asserts

W

ith a cache, when a
processor executes a
new task, it fetches
from the system's
main dynamic memory ,the first
instruction and corresponding
data, pluil the iIllltructions and
data fot several 'subsequent operations at adjacent memory addresses.
,The cache's SRAM memory
fetches the instructions and data
from the adjacent main-memory
,addresses becaU8e they have a
high probability of being used in
the operations that follow. Most
programs contain loops', and if the
cache is large enough, the needed
information will be present in the
fast cache, shortening the aver'age meniory-access time.
That's a cache hit. If the cache
doesn't contain the information; Ii
miss occurs. In this caSe, the main
memory again responds, and the
cache receives updated instructions and data. '
A cache controller circuit Be-'
, quences the necessary functional
steps. For normal program operation, the system doesn't directly
address the cache. The cache subsystem stores 'both the information and its corresponding mainmemory address. The controller
compares the stored address in
the cache, eaIled the address tag,

WHAT'S THE CACHE;!
with the address the processor
provides to determine whether
the cache contains the requested
data,
Cache types are usually delineatedbytheirplacementpolicy, or
mapping algorithm, whieb determines where new information is
stored in the cache. Most caches
are either associatively content
addressable or directly mapped,
random-aeeessible types.
Whereas ina straightRAM:, the
processor directly accesses the information, in a content-addressable memory a match with a
stored address of the information's original main-memory location causes the contents-addressable portion of the cache to respond with a pointer (see thejigUTe, ClppOIIiUl, left). The pointer,
or address, then specifies the data's location in a random-accessmemory portion of the cache system. This fully ,associative memory cache copies the information in
any main-memory location into
any location in the cache.
A direetlymapped cache, on the
other hand, uses random-aeeess
memories to store both an address
tag and the information's image
(see the.figt.lre, ClppOIIite, right).
The low-order bits of the address
from the proceSsor provide an index into the address-tag-store

MOTOROLA MEMORY DATA
10-30

portion of the caChe system,
whieb stores the hlgh-order address bits. To determinewttether
the requested informaCion reaides
in the cache, the system eornpares
the high-order addresII bita,. from
the processor'1I bus with the 'c0ntents of the address-tag-store '
RAM. If they're the 1aI'Ile, the
cache contains the requested information. Unlike in a fully &IllIGeiativecache, in a direetly ~
caehe, a meIIlOI7-addreas 1eeatioo
has its infOl'mlltion copied iBto
only one unique location.'

The fully assoeiati'fe content;.

addressable memory cache ean
have a higher hit rate tllIIn
other cache type of the aarae size
m. Bat it'll very expensin, compared with a directly mapped random-aeeess cache memory ofcornparable size.
When n directly mapped caehes
operate in paraHeI, the cache is
designated as an n-way -..soeiative type. Neverthelen, system designers may consider both
directly mapped and fuUyassoeiative types as set-associative
caches. A directly mapped cache
is simply a one-way set;.associative type, and a fully associative
one is an m-way set-associstive
type.
A four-way set-associative
cache yields about'the same hit

lUi,.

DESIGNING A CACHE ... (AR270)

CACHE SYSTEMS
lEes during the clock's high phase
when the new addresses appear.
Should the processor find what it
needs in its internal caches, it would
not assert I AS and an external bus
cycle would not run. If ISTERM activates when no bus cycle runs, the
processor ignores it.
The timing diagram of the synchronous bus shows that after addresses are valid, ISTERM must be
activated within just a half clock period minus the clock-rise time to
avoid wait states. Operating at 25
MHz, that leaves only 15 ns to check
for a cache hit and assert ISTERM if
wait states are to be avoided.

The circuit must furnish an extra
gate for the results of the tag comparator to be ANDed with a qualifier-a latched lEeS signal. A 74F64
AOI gate can AND the Match signals from the tag comparators to this
qualifier. Unfortunately, this gate
adds a 5.5-ns delay to the circuit. eonsequently, the tag comparators must
perform their comparison in 9.5 ns.
Since TTL-compatible tag comparators aren't that fast, this technique
isn't feasible. Two options remain:
Always assert ISTERM after lEeS,
and if the cache misses assert
IBERR and IHALT retry, or insert a
wait state. With retries, at 25 MHz,

the tag comparator has 35 ns to perform its function and generate
ISTERM. At 33 MHz, it has just 28
ns. For the wait-state option, 34.5 ns
is available to generate ISTERM after the addresses are valid.
Retries, however, can run into
trouble. After requesting a retry,
the processor must disable the cache
to prevent a system deadlock condition when the bus cycle reruns. Also,
before the bus cycle can rerun, a twoclock-cycle delay occurs. As a result,
the penalty incurred when the external cache misses might be greater
than it would be if the processor asserted ISTERM only on a cache hit.

AlMmsIilI

Processor

Databls

Main
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Processor

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lJIw.ordII
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CadIt
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'---

MOTOROLA MEMORY DATA
10-31

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Data bus

"--

DESIGNING A CACHE , , , (AR270)
---- - -

1"4'm:·,iQQIiH·, iUi i4'
CACHE SYSTEMS

Th(,refore a no-wait-state cache with
a low hit rate can perform worse
than a cache with a wait state.
A secondary difficulty with tag
comparators in MC6!!OaO cache designs is supporting burst'mode accesses. The address-tag-comparatot
timing is clearly a limiting factor in
the design of external caches for the
MC()!!OaO. Because, the burst-mode
cycles furnish only a first address
for the four desired long words, the
circuit must provide autoincrementing addressing to the address-tag
comparator and the cache-data
RAMs. T~is requirement, coupled
with the fact that burst transfers can
occur in single clock cycles, implies
that incrementing the addresses into
the address-tag comparator will not
be fast enough to support one-cycle
bursting.
Organizing the cache with a block
size of four is a viable one-cycle

bursting solution. Storing a valid bit but only on the initial access.
for each long word per tag, then, reThe PAL should contain a decoder
quires only checking the valid bit on to decode addresses A2 and Aa from
the fly during .the bursting portion of the processor. The resulting one-offour outputs then enter a shift registhe burst-mode transfer.
This approach can exploit the fast ter, also built into the PAL. In this
timing of the compare port.in an way, the four outputs from the PAL
MCM62af>O or MCM62::l51 to store provide the compare port of the stathe valid bits. It also allows the AOI ' tus-bit comparator with a rotating
comparator option for .the valid-bit pointer. In the AOI comparator, a
comparisons to operate effectively single valid bit compares when only
(Fig. 2).
one of the four compare inputs is at a
logic-one level. The other three valid
bits become don't cares.
A PAL POINTER
The open-drain Match pins of the
A block size of four not only allows
MCM62a51s permit wire-ORing of single-cycle bursting to work, but it
the four address-tag output.~ to the also saves components. Furthermatching circuit and thereby the more, because address-line loading
elimination of a fan-in gate. A PAL is reduc,;,d, the processor can drive
deyice makes possible a silllple, fast its address bus more quic~ly. The reinput to this circuit by providing a suIt is fast hardware.
pointer for checking only the rele, The main data-RAM issues relate
vant long word while bursting. The to burst mode. They include address
address tag still needs comparison, autoincrementing and data setup

I. WIiT-STITE ClCHE fll fiST IIMS
Data

cache,.

' 8
",

IUU""

(;~s~)1

G

MC68030

A..

Databul

Dila·bus

Add.-bus
dock

@.
genmlllr

30

MHz

Tag comparators

~

-

G

~

,

•

~

~mclack

~
~
A,
Address·lag
camparalllr,
41114

Ill...

"I"]~

A.

.Aa..111"""::ii1

...

'.~" ~

,...

~
'.'

u.

'---

./'

~ ~~~tch~l

'

""

An

I~~~
l~
Match

"'---:'

.-

Main
memory

r--

ValidbHl
camparatar

BElIR

:iIiH

Cache
contrul

'"allllllllO

. C8ACl

-

11.

CIiim
'---

A CACHE SYSTEM with four XNOR..,onfipred comparators and one AOI configured comparator-each with a depth of H ..ord

entries. a 16-1<..ord-by·32-bit cache. and a block size of four-has the lo....t cost, reduced bus loading, and fast hardware.

MOTOROLA MEMORY DATA
10-32

DESIGNING A CACHE ... (AR270)

CACHE SYSTEMS

T

he MC68030 adds a new
bus protocol-the synchronous bus cycle-to
the McesXXX family of
processors. Like its predecessors,
the MC68080 supports the standard asynchronous bus protocol.
Unlike the asynchronous bus on
the MC68020, the 60830's synchronous bus doesn't support dynamic
bus sizqlg. As a result, all synchronous bus cycles issue from a
32-bit port.
The minimum length of the
MC6803O's synchronous bus cycle
is two clock periods, whereas the
MC68020 has a minimum bus cycle of three clock Wriods. Also,
the MC68080 has on-chipmemorymanagement functions; the
MC68020 does not. Since an
MC68851 memory-management
unit requires a clock cycle to
translate logical addresses to
physical addresses, the minimum
physical bWH:Ycle length of, an
MC68020-MC68851combination
requires tour clock periods. T4e
,MC68080 bus can therefore 0perate twice as fast, as an equivalent
MC6802I).MC68851system at any
given clock frequency.
Another feature added to the
MC68030 bus, the burst-mode protocol runs only in synchronous
mode. The MC68080 has two internal caches-an instruction cache
and a data cache. Both have 16
lines with a blocksizeoffour(four
32-bit words per address tag).
, When either internal cache of the
MC68030 records a line milia from
a cachable area of main memory,
the system attempts to burstfour
long 32-bit words to fill the new
line.
The processor places the address of the first long word on the
bus and expects the return of the
corresponding data, plus three additional long words, in as little as
three clock cycles. The processor
doesn't change the address on the '
bus during these subsequent
transfers. Rather, it assumes that

A SYNCHRONOUS BUS PROTOCOL
the external memory incl'Elments
address lines AZandA3 in a modulo-four fashion, as if the the bus
were operating in nibble mode.
Thus, with no wait states, the
MC68030 reeeives as many as four
long words in just five clock cycles by using the burst-mode protocol. Because the application's
characteristics affect the type of
code the system runs, the decision
of whether or not to use the burst
mode is very important. System
designers would do well to study
the matter in depth.
A knowledge of the timing requirements of no-waitrstate operation is crucial, to understanding
how the MC68030~s synchronous
bUB operates (S66 the figure).
When a new bus cycle starts, the
processor delivers memory, addresses during a system-dock
high time, but the addresses,are
guaranteed va\id only at the end
of the c10ck high time.
,
To avoid wait atates, the Synchronous Termination Handshake signal. ISTERJ(, must assert 0 118 belen the rising edge of
the next system-doelt pulse. If
this condition la met, the pr0cessor latehes the data em the next
fa1ling edge of the clock. 'Dle pr0cessor needs a IklIl setup time for
the data withrespeettothefalling ,.
edge of the clock.
If the pIOCI!II8Or req1lires wait
states, ISTERM can be delayed
relative to the c10ck rising edge to
allow the use Of slow memories in
the synchronous mode. This featureapplies aJsotoburstrmodecy·
cles. But when the proeessor recognizes /STERM on ac10ckrising
edge, data 1atehes on the nextfaUing edge, subject; of course, toadequate setup and hold times.
When the processor runs a
burst cycle, it can aceeptnewdata
with the aame setup time to the
clock on the clock's next three falling edges. The processor also
needs an 8-118 data hold time after
the clock falls when operating at

MOTOROLA MEMORY DATA
10-33

25 MHz. Accordingly, if the processor runs burst cycles at 25
MHz, the data must be valid during the bursting portion of the cycle for 13 ns of the 4O-ns clock Wriod to meet the processor's setup
and hold time requirements.
Like its predecessors, the
MC68030 microprocessor supports bus retries and reruns. If
the bus-termination handshake
STERMi, or DSACKx/, is asserted with proper setup time relative
to a rising clock edge, activating
BERRI and HALT/with a 5-ns
setup relati,'c to the next falling
edge of the clock aborts and reruns the eurrent bus cycle. But
this action results in two dead
clocks on the bus before the bus '
cycle restarts. Nevertheless, no
waiktat.e Caches designed for the
MC68080 use this tet:hnique to
prevent the processor from latching bad data when an external
cache recordt! a milia.

00..,'.

4-tag cOtnpmtors

latched
£iiiiiijj

CJCleStaii

~t~~-J'~__+-____+-_
Mnm~~~ut~~--~-

SjiiiI8llDIIS

TerminatiDii---------.
Hllldsilm

DESIGNING A CACHE ... (AR270)

'111.'iri:l,j44'iri.iiili:~i

CACHE SYSTEMS

Yllidlils
CGmpII1bIr,

A2
AI

4h4
(1ICIII235O)
CldleHit
YIIidBils
lIafI:b

1

2. ORGANIZING THE CACHE with a hIoek &be of four is a viable IiDgie-eyele bunt"lllOde SOl.1ltion. Thiaappl'OKh .... exploit the

fut llmillfl of the eompare port in an MCM62350 or MCM62361 to store the valid bits and make it poasible to effdvely apply the AOI
comparator option for the valitHrit eomparisons. The opeIH\raiD Match pinl of the MCM62361 permit the wire-ORing of the four Iddreaoiq;
outputs to the mateblllfl cirWt, thereby e1iminatiDc a faJrin pte.
.
and hold timing to the processor. At ter a clock low at 25 MHz is merely 15 gle-cycle bursting (Fig. 3). Latching

issue is wheth& burst mode supports two-cycle write timing.
If a synchronous bus cycle is run,
the data must set up at the processor
without delay (in 5 ns), before the·
first faIling ildge of the clock after
the processor recognizes the
STERM signa\. If the cycle is two
clock periods, then the time available
to access the cache-data RAM equals
a clock period. For a 25-MHz clock,·
the time available would be 35-ns. A
33-MHz clock would yield a 25-ns interva\.
For single-clock burst cycles, also,
35 ns is available for RAM accesses
at 25 MHz. But the data hold time af-

ns. That short time interval calls for
very fast output-enable SRAMs,
such as the MCM6290.
To support the burst mode, a
74F191 counter, inserted in series
with A2 and A3 address pins, gives
two incremental addresses to the
cache-data run for autoincrement
addressing. Unfortunately, the processor's· data-hold-time requirements prevent this scheme· from
working. Besides, the counter's latency in a parallel-load mode requires a RAM faster than 35 ns.
A MCM6295 synchronous SRAM
as the cache-data RAM, with one
74F191 counter, readily supports sin-

I THUE-CYCLE a.ST REID

the data outputs when the synchronous SRAM clock is low resolves the
issue of data-hold time. Furthermore, once the synchronous SRAM
clock drives high, the addresses into
the device are registered and can be
changed for the next access in the
burst sequence.
When the MC68030 performs a
two-clock write cycle, the data and
address sent to the RAMs are simultaneously valid for only a half clock
period. For clock frequencies over 25
MHz, this tinie isn't adequate to complete a write cycle in typical fast static RAMs. In that case, it's necessary
to insert a wait state.O

Richard Crisp led the design team
for the Motorola cache-tag comparators. He has helped design several
microprocessors, including the
MC69000, MC658020, and the Intel
P7CP. Crisp, who holds a BS from
Texas A&M University, has four
u.s. patents:
. Brian Branson received a BS
from Colorado State University.
At Motorola, he designs application-specific static and dynamic
RAMs. He has one patent pending.
Ron Hanson holds a BS from
Rose-Hulman Institute ofTechnology and an MBA from Indiana
University, in Bloomington. Hanson is a product marketing engineer for fast static RAMs at Motorola.

II
1 3. AN MCM6295 SYNCHRONOUS SRAM.

a _he1Iata RAM with ODe 74F191

CODDter, reMily .pports lincJe-eyele bunts.

MOTOROLA MEMORY DATA
10-34

MOTOROLA

-

SEMICONDUCTOR
AR260/D

ENHANCING SYSTEM PERFORMANCE
USING SYNCHRONOUS SRAMs
Curt Wyman
Robert King
Motorola Inc.
3501 Ed Bluestein Blvd.
Austin, TX 78721
INTRODUCTION TO SYNCHRONOUS
SRAM ARCHITECTURE
Fast static RAMs (FSRAMs) are commanding a lot of attention from today's high performance system designers who
frequently find that the speed of their system is limited by the
performance of FSRAMs on the market. As 32-bit microprocessor-based systems become faster and more prevalent, the
demand for sub 25 ns FSRAMs will grow even more.
FSRAMs are the driving force behind semiconductor technology today: they have the smallest circuit features-as low
as 0.8 micron from some manufacturers-and use special processes like double-level metal and SIMOS. The Fast SRAM
has come a long way from its slower ancestors like the 1K x 4
Model 2114. The ease of use and dependable performance
that resulted from the asynchronous performance of SRAMs
have been replaced by the raw speed which is pacing today's
demand; however, FSRAMs are still expected to meet the
basic SRAM specifications for pure asynchronous performance. This dichotomy has caused problems as chip designers
come up with more innovative ways to speed up their circuits.
Address transition-detection circuitry, for example, caused a
number of problems when first introduced in 2K x 8 FSRAMs
under certain system conditions. With such advanced technology being used and the cost of manufacturing these chips
so high, Motorola has developed an alternative to a high-tech
15 ns access SRAM that uses conventional technology.
Motorola's newest SRAMs are the first to fully embrace the
primary purpose of Fast SRAMs. They totally abandon the
previous definition of asynchronous SRAMs. They have the
requirement of a clock signal, and are, therefore, Synchronous
SRAMs. They have separate pins for input and output data,
and do not specify standby power.
Motorola offers four different 65,536-bit Synchronous
SRAM family members organized as 16Kx4: Models
MCM6292, MCM6293, MCM6294, and MCM6295. The technology used for their implementation is the fast, low powerconsuming, and noise-immune HCMOS III, which uses a silicon gate for its fabrication. One of the main advantages to
using these devices is that they can be designed into system
cache-memory or writeable control-store applications with
fewer interfacing glue-type parts than the standard SRAM
memory. Among the reasons for this are the integrated input
and output latches that are capable of driving loads up to 130
pF. Due to the increased operating speed of the device and
the additional output-buffer loads, an extra ground pin has
been placed on the chip.
Four different devices have been specified so that all combinations of the output-latching and output-enable features
are in the offering. The MCM6292 comes equipped with latches
that are edge triggered on the inputs but transparent on the
outputs. To support systems with pipelined data, the
MCM6293 is offered with edge-triggered latches on both the

inputs and outputs. The MCM6295 and MCM6294 are outputenable versions of the two basic parts. All of the Synchronous
SRAMs come with separate data-in and data-out pins; however, some systems specify a more conventional common
I/O mode, and the asynchronous output-enable control (G)
which replaced the 5 signal on these parts can be helpful in
such a case.
In many designs using SRAMs, there is actually extra time
during the cycle that is being wasted. In more critical applications, the Synchronous SRAM offers an alternative to the
conventional SRAM. An external clock input (K) can be used
to precisely control the cycle by directing the operation of the
on-chip latches.
The designer of small personal computer systems can use
the Synchronous SRAM in a number of storage areas. One
of the primary applications, cache memory, is high-speed
memory that resides between the central processing unit (CPU)
and the main memory of the system. Accesses to this fast
cache typically require 60 ns versus the 200 ns needed to
perform an access to main memory. One way the cache is
used is to store data or instructions from main memory that
are frequently called for by an application. As an example of
this, higher-level languages often use repetitive loops: by storing the data necessary for these repeated operations and instructions in the cache, accesses to the main memory can be
avoided.
A typical system is illustrated in Figure 1. It is configured
as a cache memory residing between the CPU and the system
bus. The system bus links the main memory and I/O devices
to the CPU by way of the cache.

SYSTEM BUS

Figure 1. A primary synchronous SRAM application is
high-speed cache memory residing between the CPU
and the main memory of a personal computer system.
Accesses to the cache typically require 50 ns, whereas
main memory takes 200 ns.

Reprinted with permission from ECN, Chilton Company, October 1987.

MOTOROLA MEMORY DATA
10-35

ENHANCING SYSTEM PERFORMANCE . .. (AR280)

In operation, thera is one set of locatiQns in which data is
stored and another set of locations containing a cache tag for
each word in the cache. The cache tag identifies the main
memory location with which the data is associated. A comparison is made between the cache tags, which ara located
in the cache memory, and the addrass, which is generatad by
the microprocessor at the beginning of a cycle. If a cache tag
and the addrass match, thera is no access made to main
memory, but instead the read or write cycle is executed on
the corresponding byte of data storad in the cache. When the
addrass does n6t find a match, a miss occurs, and new locations must be read into the cache from main memory.
A cache miss is the result of a mismatch between the cache
tag and the desired addrass to be accessed by the CPU. When
this occurs, the system logic is allowed to perform a retry of
the previous access. The appropriate address is accessed from
main memory. Following an updata of the cache, the data is
then available for processing.
The cache hit rate is the actual percentage of accesses made
to the cache in which the requested address is resident. In
order to keep the hit rata as high as possible, a variety of
softwara routines ara used. The function of these routines is
to keep the cache as full as possible with the most frequently
used data. In so doing, the cache hit rate for both the data
and instruction caches will be maximized, increasing overall
information throughput.
The Harvard architectura, an efficient method used in many
currant day applications, is characteristic of a configuration
which supports peralleflSm throughout a system. Synchronous
SRAMs can be qrganized as relatively small external caches
connected to the data buses and instruction paths locatad
between the CPU and main mamory. This will allow simUltaneous instruction execution and data prafetches. The extemal cache demonstrates another system speed anhancement capability of these devices.

2. In this illustration, there ara four MCM6292 synchronous
SRAM devices configured to operate on a 16-bit data bus.
'Each memory has four deta inputs and four data outputs to
allow the transfer' to data. The addrass bus consists of 14
address bits, AO-A 13. These 14 bits ara required to decode
and access the 66,536 memory locations of each device. The
memory matrix is configured es 128 rows by 512 columns. The
system clock is connected to the (K) input of each memory
and used to latch all inputs, outputs, write enable, and chip

ADDRESSING CONSIDERATIONS FOR
READ/WRITE CYCLES

One consideration worth mentioning is that many memories
ara not able to ~ up with very high-speed MPU control
devices. This has been a problem with DRAM technology for
a number of years. MPUs operating at clock speeds of over
20 MHz ara common in both business and engineering systems

select.
In Figure 3, thera ara two different read-cycle timings being
rapresentad for the MCM6292 (transparant output latches).
Both ara examples of systems that usa the rising edge of (K)
to latch all inputs to the memory device. The states of the
outputs ara then held until the clock makes its transition to
the low state. With this Synchronous SRAM, however, it is
possible to have differant memory access times, depending
upon the condition of the clock (K). If the clock pulse is high
for less than the 25 ns access time of the memory device, the
total access time is rated at tKHQV or 25 lIS (Read Cycle 1).
On the other hend, if the high portion of the clock cycle lasts
longer then 25 ns, the total access time becomes tKLQV (10
ns maximum) plus the length of the clock high (Read Cycle
2).
Figure 4 has bean included to show the timing of a write
cycle. The timing of a write operation is similar to that of the
previously discussed read cycle. One point to consider is that
to generate a writa pulse, thera is no requirement for complex
extarnal intarfacing chips. This is accomplished through the
salf-timing mechanism which samples both the write enable
and input data when (K) rises. A high-impedance state is
entered when the clock returns low.

MPU AND MEMORY SPEED CONSIDERATIONS
AT A SYSTEM LEVEL

To batter understand the Synchronous SRAM's addrassing
capebilities in regard to read and writa cycles, rater to Figura
SYSTEM
ADDRESSES

, /1 4
)'14

SYSTEM
ClOCK

14

AO-A13

AO-A13

'-- K
MCM6292

"/
4

SYSTEM
DATA IN

/1&

OUTPUT

·16

MCM6292

00-03
00-Q3

4

I

"/
4

00-03
00-03

-K
MCM6292

'r 00-0300-03

' 4

4

14

AD-A13

AO-A13
'-- K

-K

/

"14

...; 4

MCM6292

4

00~03

00-03

V4

DATA BUS

Figure 2. An array of synchronou8 SRAMs 18 configured for a 16-bit data bus. Each MCM6292 has four data inputs,
'tour dats outpute, and fourteen address lines.

MOTOROLA MEMORY DATA
10-36

ENHANCING SYSTEM PERFORMANCE . .. (AR260)

READ CYCLE 1 (See Note 1)
IKHKL --_I+--IKLKH
K

A (ADORESSI

w

QO-Q3 - - - - - PREVIOUS HIGH Z

READ CYCLE 2 (See Note 2)

A (ADDRESSI

w
_

"'-I.+-~:_IK_LQV_ _ _ _I_KLDZ_--+_
_ ...;,.-_--i1"
~
0"

_ _ _: : _-_

00-03 - - - - - - - PREVIOUS HIGH Z

:r-

NOTES:
1. For Read Cycle 1 timing, clock high pulse width «tKHQV-tKLQVI.
2. For Read Cycle 2 timing, clock high pulse width :.:(tKHQV-tKLQVI.

Figure 3. If the system's clock high, tKHKL, is shorter than the MCM6292's 25 ns acC888 time, then the totel acc_
time will be 25 ns. However, if tKHKL Is longer than 25 ns, totel acce.. time is increased.

MOTOROLA MEMORY DATA
10-37

ENHANCING SYSTEM PERFORMANCE . .. (AR260)

IKHKL

IKLKH

ISVKH

IKHSX

ISVKH .....,....---t*"f--...-1KHSX

A IADDRESS)

DO-D3

w
IKLDZ

-+__--I~oi

--J).....------

o"_-_,_____

00-03 _ _ _ _ _ _ _

HIGH Z - - - - - - -

Figure 4. In a write cycle, the self-timing mechenlsm of the MCM8292 samples both the write enable end the input
date when the clock signal, K, rises.

WHAT'S TO COME FROM
SYNCHRONOUS SRAMs
in use today; therefore, 25 ns Synchronous SRAMs are ideal
to operate with zero wait states.
Wait states are implemented with slower SRAMs and most
DRAMs to freeze the state of the microprocessor address and
data bus for a clock cycle. As long as the signal controlling
wait states is asserted, more wait-state periods will be generated. The microprocessor resumes operation when the waitstate signal is negated.
The alternative to implementing a wait state to halt the
microprocessor for a slow memory device is to use the much
faster Synchronous SRAM. Its timing parameters can be more
exactly controlled, making the system operate more efficiently.
Faster data throughput plus an improvement in overall system
performance make the Synchronous SRAM cache a very costaffective solution in a microprocess6r-basGd system.
When performing read and write operations in a .personal
computer system, the timing relationship between a highspeed microprocessor's system clock and a typical Synchronous SRAM's cycle time constraints is very critical. These operations cou·ld be as simple as inputting console information
for CRT display outputs or as complex as supporting multitasking environments or concurrent execution of operations.
High-performance microprocessor systems with operating
frequencies of 20-25 MHz are a realistic timing example being
offered today. For microprocessors capable of operating at
these speeds, a 25 ns Synchronous SRAM is ideally suited.
These devices not· only provide precise clocked timing control,
but also will support applications requiring system clocks running at over 30 MHz. This can be accomplished without incurring any degradation of the processor by inserting wait
states.

Very high cache hit rates can be attained from a relatively
small cache store. The high-rate efficiency is primarily due to
the fact that the cache is located extemal to the CPU rather
than actually being an on-chip cache, as is the case with some
high-performance microprocessors.
In addition to the popular high-speed cache-memory applications, Synchronous SRAMs are also ideal for writeable control store environments. Date can be downloaded into a
Synchronous SRAM array, and the information can be accessed at very high speeds- much faster than from a DRAM
array.
Memories are taking on new roles. Because of this, they
are being used in a wide variety of application areas and operating to support functions previously not possible. Future
Synchronous SRAM devices will be even more complex and
some will· very likely contain higher degrees of intelligence.
Many will be designed with special system functions in mind.
Higher-speed ·operation working from lower voltage sources
is just one example. There will be enhancements allowing the
designer more fleXibility and enabling him to reach supercomputer perfonnance.
Current-day static memories support numerous applications. The synchronous SRAMs discussed above will be offered in 3OO-mil, 2B-lead CERDIP and 4OO-mil, 2B-lead plastic
SOJ peckages. These configurations satisfy the requirements
of most systems presently. As chip integration and sophistication continue to advance, the packaging technology will also
need to advance to promote future innovations within the
industry.
For more information on MCM6292-series synchronous
SRAMs, contect Memory Marketing. at Motorola, Inc., MOS
Memory Products Div., P.O. Box 6000, Austin, TX78762. (512)

928-6700.

MOTOROLA MEMORY DATA

MOTOROLA

-

SEMICONDUCTOR
AR258
HIGH FREQUENCY SYSTEM OPERATION
USING SYNCHRONOUS SRAMs
Frank Miller
Scott Remington
Richard Crisp
Senior Memory Designers
Motorola Inc.
3601 Ed Bluestein Blvd.
Austin, TX 78721
INTRODUCTION
The market for semiconductor memory products suitable
for today's high speed cache applications is changing dramatically as the demand for higher performance super mini,
ASIC, and microprocessor based computers rapidly increases.
"this development has put heavy pressure on MOS memory
suppliers for faster and faster static RAMs to support shorter
and shorter processor cycle times. To utilize their full system
performance, fast SRAMs require precise system control, long
address hold times, and have tight write pulse requirements.
They provide short data valid time, cause common 110 data
contention, and offer low drive capability. Todays high performance processors themselves have similar 110 requirements. Therefore system designers have many concems when
designing a fast memory subsystem. They must use additional
logic (latches, drivers, pulse generators, etc. I to allow the
memory subsystem to interact efficiently with the processor
at the fastest system cycle times.
A solution to gat the memory and the processor to work
well together at fast cycle and access times lies not only in
faster components, but in minimizing the need for external
glue logic and its associated delays. The Synchronous Static
RAM is defined as having on chip latches for all its inputs and
outputs, added drive capability, and a self timed write cycle
all under the control of the system clock. This eliminates the
need for most external logic chips and allows the memory to
run at higher system speeds than stendard SRAMs with comparable access times.
This paper outlines the basic architacture of a Synchronous
SRAM that Motorola plans to introduce in the first half of
1988. We will highlight its advantages over standard SRAMs
in high frequency computer system operation. This is followed
by an application example for a MC68030 cache subsystem.

ARCHITECTURE AND OPERATION
ARCHITECTURE
A block diagram of the 16K x 4 Synchronous SRAM is
shown in Figure 1. This diagram shows all inputs, outputs,
and control signals (W, 5, and KI to the part; addresses (AOA13), data in (00-03), data out (00-03), clock (KI, chip select
(5), and write enable (W). All inputs, outputs, write enable,
and chip select are latched by the clock.
The'latches are one of two types, either positive edge triggered or transparent. The positive edge triggered latches are

latched by the rising edge of clock (K). The transparent latches
are frozen when the clock is in the high state and open when
it is in the low state. Our parts feature two of the possible
combinations of input and output latches. The first part, the
MCM6292, features edge triggered latches on the inputs and
transparent latches on the outputs. Our second part, the
MCM6293, has edge triggered latches on both inputs and
outputs, to aid in pipelining data.
The output buffers on all of our parts are capable of driving
130 pF loads. The output buffers were designed to drive this
load because in some systems the latches that they replace
would be required to drive a comparable size load. Due to the
size of load that the output buffers must drive, and the speed
at which the part operates, we have added an extra ground
pin (VSSO). This pin is the ground connection for all of our
output drivers, and allows us to drive our outputs harder and
also gives us noise immunity on the ground bus.
For systems that reqUire a common I/O configuration we
expect to offer the MCM6296 and the MCM6294, which are
the MCM6292 and the MCM6293 with an asynchronous output
enable (G) option. These parts, the MCM6294 and the
MCM6296, replace the chip select, (5) buffer with an asynchronous output enable (GI buffer.
OPERATION
The operation of these parts is much the same as 8 standard
16K x 4 SRAM except for the fact that the inputs and outputs
are latched and the cycle begins with the low to high transition
of the clock. The following examples will concentrate on a
read and write cycle for both the MCM6292 and the MCM6293.
The MCM6294 and MCM6295 read and write cycles are the
same as the MCM6292 and the MCM6293 except that the
outputs can be put into a high impedance state at any time
by using output enable (GI.
During a read, see Figure 2, all inputs are latched into the
part at the rising edge of the clock (KI in both the MCM6292
and the MCM6293. ,For the MCM6292, when clock goes high,
the outputs become latched and are held in thet state until
the clock falls low. Since the output latches are transparent,
during clock low time, there are two pOssible access times,
tKHOV and tKLOV. These access times are dependent upon
the high pulse width of the clock. If the high pulse width is
less than the access time of the memory array the longer
tKHOV spec is the clock access time. However if the clock
high pulse is longer than the memory array access time, the
clock access time becomes tKLOV. For the MCM6293 the

Copyright ©Electronic Conwntions, Inc. Reprinted with permission, from MIDCON 1987, Professional Program Papers, Session ffl2.14.

MOTOROLA MEMORY DATA
10-39

HIGH FREQUENCY SYSTEM

. (AR258)

-Voo
-Vss

MEMORY MATRIX
128 ROWS x
512 COLUMNS

00

Ql

COLUMN I/O

Q2

Q3

K

w

. ~ - TliANSPARENT OR EDGE TRIGGERED LATCH

D

-POSITIVE EDGE TRIGGERED LATCH
Figure 1. Synchronous SRAM Block Dil!gram

outputs tl'Bnsitiort only when the c;loi:k sWitches from lOw to
high.
output data that is latched during the low to high
transition Of the 'clock is the data"from the previous read cycle.
For the write cycle, sea Figure 3, all inputs are handled in
the sarna manner as in the read. Since both write enable and
the input data are sampled on the rising edge of the clock the
writS becomes self timed. This aliminatss the need for complex
off chip write pulse generating circuitry. Th8 outputs are put
in a high impedance State tKU1Z after tha clock falls low for
the MCM6292. In the MCM6293 the output buffers 'will not
go into Ii high impedance state until the low to high .transition
Of the clock at the beginning of the next cycle. The MCM6294
and the MCM6295 allolll( the user to put the output buffers
into a' high impedance state asynchronously by using the output enable input. This allows the user to put the output buffers
into a high impedance state earlier in the cycle, Which eases
the data contention Pl'9blem when the part is used in a common
I/O system Configuration.

SYSTEM ADVANTAGES (SRAM

The

..

VB

SSRAM)

SYSTEM DESCRIPTION AND TIMING
Figure 7 shows two examples of a 16K x 32 bit memory using
standard parts. The systems shown require eighteen parts
each, ten latches and eight 16K x 4 SRAMs, to implement the
same function as eight synchronous SRAMs and. no glue logic.
The functional equivalent of a MCM6292 is the standard
16K x 4 SRAM with edge triggered latches on the inputs and
transparent latches on the outputs, as shown at the top of
Figure 7. The parts lised in this example are six 'F374 octal
D-typeflip flops, four 'F373 octal transparent latches, and eight
6288 16K x 4 SRAMs. The predicted timing diagram for the
system is shown in Figure 4. This timing diagram compares
the predicted system access with that of the MCM6292. In the
timing lIiagrams an approximate skew of 5 ns was added to
the address timing to allow for some propagation delay from
the MPU' or CPU. For the purpose of comparison, three timing

MOTOROLA MEMORY
10-40

DATA

HIGH FREQUENCY SYSTEM ... (AR258)

MCMIZBZ TRA.SPAREIT OUTPUT LATCHES

If0.25(0.0101 ® I TI A ® I
3.
IS SEATING PLANE.
4. DIM A AND a INCLUDES MENISCUS.
5. DIM ·L- TO CENTER OF LEADS WHEN FORMED
PARALLEL.
6. DIMENSIONING & TOLERANCING PER Y14.5, 1982.
7. CONTROLLING DIM: INCH.

rn

-I

PLASTICSOJ
CASE 810-02

1

o

14

I-F

~~ Da~LZ
D LD28PL

1.10.1810.0071 ®I TIA® I

H BRK
~----~~-r-----~

Itlo.18(0,007l®ITla® I

·s
~ 4=t=+

,
,\ f f
I-R----I ~s RAD.

DIM
A
B

C

m

D
E
F
G
H
K
L
M
N

P
R
S

MILLIMETERS
MIN
MAX
18,29
18,54
10,04
10,28
3.26
3.75
0.39
0.50
2.24
2.48
0.67
0.81
1.27 asc
0.50
0.89
1.14
0.64 asc
0'
5'
0.89
1.14
11.05
11.30
9.15
9.65
1.01

o.n

INCHES
MIN
MAX
0.720
0.730
0.395
0.405
0.128
0.148
0.015
0.020
0.088
0.098
0.026
0.032
0.050 asc
0.020
0.035
0.045
0.025 asc
0'
5'
0.035
0.045
0.435
0.445
0.360
0.380
0.040
0.030

-

I t I 0.25 (0.0101 ® I T I a ® I
NOTES:
1. DIMENSIONING AND TOLERANCING PER ,ANSI
Y14.5M, 1982.
2. DIMENSION "A" AND "S" DO NOT INCLUDE
MOLD PROTRUSION. MOLD PROTRUSION SHALL
NOT EXCEED 0.15 (0.0061 PER SIDE.
3. CONTROLLING DIMENSION: INCH.
4. DIM "R" TO BE DETl:RMINED AT DATUM ·T·.

MOTOROLA MEMORY DATA
11-16

- - - - - - - - - - 28-PIN PACKAGES ( C o n t i n u e d ) - - - - - - - - - --i

!--~
D I.-.-

15

28

1

14

o

t-- F

300-MIL PLASTIC SOJ
CASE 8108-01
DETAILZ

D 24PL

I fI 0.1810.007)

®

I T I A@I

1+10.1810.007)@ I Tle@ I

~
~

M

E

SRAD

,--1+C'T1-0.2-5-(0.0-10-)@-=-S-'I-T"I-8@-=-sI
DIM
A
B
C
D
E

F
G
H
K
L
M
N

P
R
S

MILLIMETERS
MIN
MAX
18.29
18.54
7.50
7.74
3.26
3.75
0.39
0.50
2.24
2.48
0.67
0.81
1.27 esc
- I 0.50
0.89 I 1.14
0.64 BSC
0"
10"
1.14
0.89
8.51
8.76
7.11
6.61
0.77
1.01

INCHES
MIN
MAX
0.730
0.720
0.295
0.305
0.148
0.128
0.Q15
0.020
0.088
0.098
0.026
0.032
0.050 esc
- I 0.020
0.045
0.035
0.025 esc
0"
10"
0.035
0.045
0.335
0.345
0.280
0.260
0.030
0.040

-Il

S
i-.J.J....J..L..LLLL-J..I.-I.L-U-L.L...ll-..LLLL-J..I.-I.'-IU,

[±]

'-rr-rCD~"TT'"'TT"TT"T~TT'"TT"'14 j-

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. DIMENSION A & 8 DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.1510.006) PER SIDE.
3. CONTROlliNG DIMENSION: INCH.
4. DIM RTO BE DETERMINED AT DATUM -T-.

ttE
JL
I

PLASTICSOG
CASE 751H-01

_,D,E_TA_I_L_X_-.--.

I

D

28 PL

1010.1010.004) I T I

~~~

DIM
A
B
C
D
G
J
K
L
M
S

MILLIMETERS
MIN
MAX
17.70
18.50
8.23
8.90
2.04
2.54
0.35
0.50
1.27 esc
0.14
0.32
0.40
1.27
0.05
0.35
0"
8"
11.50
12.70

INCHES
MIN
MAX
0.697
0.728
0.324
0.350
0.080
0.100
0.014
0.020
0.050 BSC
0.0060 0.0125
0.016
0.050
0.014
0.002
0"
8"
0.453
0.500

~lt,..,.l-o.2-51-0.0-10-)®-M~I-T"'1e-@=-S"'1A-@:-SI

S

14PL

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIM: MILLIMETER.

3. DIMENSION A AND BDO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

MOTOROLA MEMORY DATA
11-17

III

- - - - - - - - - - - 32-PIN P A C K A G E - - - - - - - - - - - -

.

CERAMIC
CASE 766A-Ol

ri.~~ ,.® 1,1·",1 ''''I ..l

r

DIM
A
B
C

D
F
G
H
l
N
R
U

MILUMETERS
MIN
MAX
13.85
14.22
13.34 13.58
1.91
2.26
0.56
0.71
1.91
2.41
1.27 sse
1.07
1.47
11.31
11.63
1.63
1.93
10.80
11.04
0.50

-

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTR(jlLlNG DIMENSION: INCH.

INCHES
MIN
MAX
0.545
0.560
0.525
0.535
0.075
0.089
0.022
0.028
0.075
0.095
0.050 SSC
0.042
0.058
0.445
0.458
0.064 0.076
0.425
0.435
0.020

II
MOTOROLA MEMORY DATA
11-18

4O-PIN PACKAGES

~:: :::::::::::::::::JJ CL=J

PLASTIC
CASE 711-03

I-

~I

A

C

~

J~~~L
DIM
A
B
C
D

F
G
H
J

K
L
M
N

MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 SSC
15·
0"
0.51
1.02

J-t-

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0). SHALL BE
WITHIN 0.25 mm (0.0101 AT MAXIMUM MATERIAL
CONDITION. IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION LTO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION BDOES NOT INCLUDE MOLD FLASH.

INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014 0.022
0.040
0.060
0.100 SSC
0.065 I 0.085
0.008 I 0.015
0.115 J 0.135
0.600 BSC
15·
0"
0.020
0.040

CERAMIC
CASE 734-04

DIM
A

B
C
D

F
G

J
K
L
M

N

MIWMETERS
MIN
MAX

INCHES
MIN
MAX

5.31
53.24
12.70
15.49
4.06
5.84
0.38
0.56
1.27
1.65
2.54BSC
0.20 I 0.30
3.18 J 4.06
15.24 ssc
5· I 15·
0.51 I 1.27

2.020
2.096
0.500
0.610
0.160
0.230
0.015
0.022
0.050
0.065
0.100 BSC
0.008 I 0.012
0.125 I 0.160
0.600 BSC
5· I 15·
0.020 I 0.050

NOTES:
1. DIM ·A· IS A DATuM.
2. POSITIONAL TOLERANCE FOR LEADS:
I t I pO.25 (O.0101® I TI A® I
3. ·T·IS SEATING PLANE.
4. DIM LTO CENTER OF LEADS WHEN FORMED
PARALLEL.
5. DIMENSIONS A AND' BINCLUDE MENISCUS.
6. DIMENSIONING AND TOLERANCING PER ANSI Y14.5.
1973.

MOTOROLA MEMORY DATA
11-19

III

-----------.-;:.------ 44-LEAD PACKAGE - - -..................- - - - - PLASTIC CHIP CARRIER
CASE 7T1..ffJ.

B 1.....10.18(0.007)

YBRK

I--D

®

ITI N(!)...p®1 L(!)...M®I

U 1..... 10.18(0.007)

~

®

ITI N(!)...p®1 L(!)...M®I
NOTE 1

t

Gl
t - - - - - - - - t - A 1+10.18(0.007)

.....---~-++--R

1+10.18(0.007)

1... 10.25(0.010)

®

ITI L(!)...M®I N(!)...p®1

®

ITIL(!)...M®I N(!)...p®1

®

VIEWD..o

DETAILS

1... 10.25 (0.010) ®

DIM
A

B
C
E
F

G
H
J

K
R
U

V
W

X
Y

18

Z
Gl
KI
ZI

MLUMETERS
MIN
MAX
·17.40
17.65
17.40
17.65
4.20
4.57.
2.29
2.79
0.33
0.48.
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
O.SO
2"
10"
15.SO .16.00
.1.02
2"
10"

-

-

INCHES .
MAX

MIN

. 0.685 0.695
0.685 0.695
. 0.165 .0.160
0.090 .0.110
0.013 0.019·
0.050 BSC
·0.026 0.032
0.020
0.025
0.650 0.656
0.650 0.656
0.042
0.048
0.042
0.048
0.056
0.042
0.020
2"
10"
0.610 0.630
0.040
10"
2"

NOTES:
I. DlIE TO SPACE UMITATlON, CASE
7n·02 SHALL BE REPRESENTED BY A
GENERAL (SMALLER) CASE OUTLINE
DRAWING RATHER THAN SHOWING

-

-

ALL44~DS.

2. OATUMS ·L·, ·M·, ·N·, ANO .p. DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT PLASTIC
80DYAT MOLD PARTING LINE.
3. DIM G1,.TRUE POSmON TO BE MEAsURED AT
DATUM ·T·; SEATING PLANE.
4. DIM RAND U DO NOT INCLUDE MOLD
PROTRUSION: ALLOWABLE MOLD PROTRUSION
IS 0.25 (0.010) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M, 1982.
6. CONTROLLING DIMENSION: INCH.

-

-

MOTOROLA MEMORY DATA
11·20

ITI N(!)...p®1 L(!)...M®I

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

Tape and Reel
Data for
MOS Memory
Surface Mount
Device.

Embossed Tape and Reel
Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tepe is used as the shipping conteiner for various products and requires a
minimum of handling. The antistetic/conductive tepe provides a secure cavity for the product
when sealed with the "peel-back" cavar tepe.
• 13-lnch Reel
• Used For Automatic Pick and Place Feed Systems
• Minimizes Product Handling
• EIA-481

PACKAGES
SOJ-24
SOJ-28
SOJ-20/28

• SOJ-24, SOJ-28, SOJ-20/26
Ordering Information
Use tha stendard device title and add tha required suffix R2. Note that the indMdual reels
have 1000 devices per reel. Also note the minimum lot size is one full reel for each line itam,
and orders are required to be in increments of tha single reel quantity:

c=E0GOOOOOOOOOO~

. ODD·
llJDDJDO
•

DIRECTION OF FEED

Tapa. Reel

Tape Width
Imm)

Davlce
perR..1

Reel Size
(lnchl

SOJ-24

24

1,000

13

1,000

SOJ-28

24

1,000

13

1,000

R2

SOJ-20/28

24

1,000

13

1,000

R2

Package

LotSI~

IMln)

Device
Suffix
R2

III
MOTOROLA MEMORY DATA
11-21

TAPE AND REEL DATA

CARRIER TAPE SPECIFICATIONS

01
FOR COMPONENTS

2.0 nII1X 1.2 mm

FOR MACHINE REFERENCE

AND LARGER

ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC ARO\JNO 80

USER DIRECTION OF FEED

R MIN.
TAPE AND COMPONENTS .
SHAll PASS AROUND RADIUS "R"
WITHOUT DAMAGE

CARRIER
TYPICAL
COMPONENT CAVITY
CENTER LINE

TYPICAL
\ ___ COMPONENT
,
CENTER LINE

1

100"'~
(3.937"'
T'-ln111MAX

I

EMBOSSMENT
'

,~r-:::-e'OC::=:-O~-:_0~
[(0.0~9~

,
MAX 250 mm
r-->-------------'---'---(9.843"'
CAMBER ITOP VIEW,
ALLOWABLE CAMBER TO BE 1 mm/1 00 mm NONACCUMULATIVE OVER 250 mm

DIMENSIONS
Tape
., Max
D
E
F
K
P
RMln TMax
W
D,
Po
P:z
Size
24mm 19.4mm 1.5+0.1 mm 2.0mmMin l.75tO.l mm 11.5tO.l mm 4.0mm 12'otO.l0mm 4.0tO.l mm 2.0tO.05mm Slmm O.400mm 24tO.2mm
-0.0
(0.784"'
(0.1ll!r' (O.069tO.OO4"' (O.453tO.OO4"' (0.157"' (O.472tO.OO4"' (0.157 t 0.004"' (0.019 t 0.002"' (1.1168'" 10.016"' (O.94&tO.OIB'"
(0.069+0.004"
-0.0'
Metric Dimensions Govern-English are in parentheses for reference only.
NOTE 1: Ao. BO. and Ko are determined by component size. The clearenca between the components and the cavity must be within 0.05 mm
min to 0.50 mrn max. The component cannot rotete more than 100 within the determined cavity.

II
MOTOROLA MEMORY DATA
11-22

TAPE AND REEL DATA

REEL DIMENSIONS
Metric Dimensions Govern-English are in Parentheses for Reference only.

--I

!-TMAX

13.0 mm±0.5 mm
10.512" ± 0.02"1

-.L t

T

50 mm MIN

11.989"'

---.L

G
24.400 mm, +2.0 mm, -0.0
10.981", + 0.079", - 0.001

TAPE ENDS

I.-TRAILER
----;...-(lioI.~- COMPDNENTS--~".-(I)ooI.I--lEADER
----II
INO COMPONENTS
NO COMPONENTS
CAVITY

TAPE

TOP TAPE

500 mm MIN
119.7" MINI

DIRECTION Of FEED

..

500 mm MIN
119.7" MIN'

III
MOTOROLA MEMORY DATA
11-23

. . Selector Guide and Cross Reference

II

MOS Dynamic

•

General MOS'Static RAMs

II
II
II
II

~AMs

.

CMOS Fast Static RAMs
Special Application MOS Static RAMs
MOS EEPROM'
MECL Memories

. . Military Products
•

ID
II

Reliability Information
Applications Information
Mechanical Data
MOTOROLA MEMORY DATA
Source Exif Data:
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