1989_NEC_Intelligent_Peripheral_Devices_Data_Book 1989 NEC Intelligent Peripheral Devices Data Book

User Manual: 1989_NEC_Intelligent_Peripheral_Devices_Data_Book

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INTELLIGENT PERIPHERAL DEVICES (IPD)
DATA BOOK

NEe

NEe Electronics· Inc.

NEe

Intelligent Peripheral Devices [IPD]

1989-1990
DATA BOOK

June 1989
Document No. 50051
01989 NEe Electronics Inc.lPrinted in the U.S.A.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Electronics Inc. The information in this document is subject to change without notice. Devicessold
by NEC Electronics Inc. are covered by the warranty and patent indemnification provisions appearing in NEC
Electronics Inc. Terms and Conditions of Sale only. NEC Electronics Inc. makes no warranty, express, statutory,
impll8d, or by description, regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. NEe Electronics Inc. makes no warranty of merchantability or fitness for any
purpose. NEC Electronics Inc. assumes no responsibility for any errors that may appear in this document. NEC
Electronlca Inc. makes no commitment to update or to keep current the information contained in this document.

NEe

SELECTION GUIDES

fJ
B

COMMUNICATIONS CONTROLLERS
GRAPHICS CONTROLLERS

II
II
II

ADVANCED COMPRESSION/EXPANSION ENGINE
FLOPPY-DISK CONTROLLERS
HARD-DISK CONTROLLERS

fJ
II

LCD CONTROLLERS
MEMORIES FOR GRAPHICS APPLICATIONS

PACKAGE DRAWINGS

iii

NEe

tiEC

Contents
Section 4
Advanced Compression/Expansion Engine

Section 1
Selection Guides
Single-Chip Microcomputers

1-3

V-Series Microprocessors and Peripherals

1-9

Intelligent Peripheral Devices (lPD)

1-13

DSP and Speech Products

1-15

V-Series Development Tools

1-17

"PD75XX Series Development Tools

1-21

"PD75XXX Series Development Tools

1~25

"PD78XX Series Development Tools

1-29

"PD78XXX Series Development Tools

1-31

DSP and Speech Development Tools

1-35

PG-1500 Programming Adapters

1-37

Section 2
Communications Controllers
I'fD7201A
Multiprotocol Serial Communications Controller
"PD72001
CMOS, Advanced Multiprotocol Serial
Communications Controller

2-21

Section 5
Floppy-Disk Controllers
I'fD765A/"PD765B
Single/Double Density Floppy-Disk Controller

5-3

"PD71 065/66
Floppy-Disk Interface

5-21

"PD72065/65B
CMOS Floppy-Disk Controller

5-43

"PD72067
Floppy-Disk Controller

5-57

"PD72068
Floppy-Disk Controller

5-79

"PD72069
Floppy-Disk Controller

5-105

Section 6
Hard-Disk Controllers
I'fD7261A/B
Hard-Disk Controllers

3-3

"PD72020
CMOS Graphics Display Controller

3-31

"PD72022
Intelligent Display Processor

3-57

"PD72120
Advanced Graphics Display Controller

3-97

"PD72123
Advanced Graphics Display Controller II

4-3

2-3

Section 3
Graphics Controllers
"PD7220A
High-Performance Graphics Display Controller

"PD72185
Advanced Compression/expansion Engine

6-3

"PD7262
Enhanced Small-Disk Interface Controller

6-39

"PD72061
CMOS Hard-Disk Controller

6-67

"PD72111
Small Computer System Interface Controller

6-69

3-153

Contents
Section 7
LCD Controllers

Section 9
Package Drawings

""D7225
CMOS, Intelligent Alphanumeric LCD
Controller/Driver

Package/Device Cross-Reference

9-3

28-Pin Plastic SOP (375 mil)

9-5

3D-Pin Plastic Shrink DIP (400 mil)

9-5

40-Pin Plastic DIP (600 mil)

9-6

4O-Pin Ceramic DIP With Side-Brazed Leads
(600 mil)

9-7

4O-Pin Cerdip (600 mil)

9-8

44-Pln PLCC

9-9

"PD7227
CMOS, Intelligent Dot-Matrix LCD
Controller/Driver

7·13

"PD7228/28A
CMOS, Intelligent Dot-Matrix LCD
Controller/Driver

7·21

Section 8
Memories for Graphics Applications
""D41264/42273/42274
Dual-Port Graphics Buffers

8·3

"PD421 01/421 02/42505
CMOS Line Buffers

8-5

"PD42270
NTSC Field Buffer

8-9

"PD43501
1,024-Channel Time-Division Switch

8·11

48-Pin Plastic DIP (600 mil)

9·10

52-Pin Plastic Miniflat (3.5-mm leads)

9~11

52-Pin Plastic Minlflat (1.8-mm leads)

9·12

52-Pin PLCC

9·13

64-Pin Plastic Miniflat

9·14

64-Pln Plastic Shrink DIP (750 mil)

9-15

68-Pin PLCC

9-16

74-Pin Plastic Miniflat

9-17

80-Pln Plastic Miniflat (2.35-mm leads)

9-18

8O-Pln Plastic Miniflat (1.8-mm leads)

9-19

84-Pin PLCC

94-Pin Plastic Miniflat

9-21

100-Pin Plastic Miniflat

9-22

132-Pin Ceramic PGA

9-23

ttlEC

Contents

Numerical Index
Device,

"PD

Page

41264
42101
42102

8-3
8-5
8-5

42270
42273
42274

8-9
8-3
8-3

42505
43501
71065/66

8-5
8-11
5-21

72001
7201 A
72020

2-21
2-3
3-31

72022
72061
72065/65B

3-57
6-67
5-43

72067
72068
72069

5-57
5-79
5-105

72111
72120
72123

6-69
3-97
3-153

72185
7220A
7225

4-3
3-3
7-3

7227
7228/28A
7261A/B

7-13
7-21
6-3

7262
765A/B

6-39
5-3

vii

Contents

viii

t-fEC

SELECTION GUIDES

1-1

Selection Guides
Part Numbering System

Section 1
Selection Guides

"PD72001L

Single-Chip Microcomputers

1-3

V-Series Microprocessors and Peripherals

1-9

Intelligent Peripheral Devices QPD)

1-13

DSP and Speech Products

1-15

V-Series Development Tools

1-17

~PD75XX

1-21

Series Development Tools

~PD75XXX Serls~
~PD78XX

DeveIOP!TlCllnt Tools

Series Development Tools

~PD78XXX

1-25

1-29

Series Development Tools

1-31

DSP and Speech Development Tools

1-35

PG-1500 Programming Adapters

1-37

pP
D

72001
L

Typical microdevice part number
NEC monolithic silicon Integrated circuit
Device type (D = digital MOS)
Device identifier (alphanumeric)
Package type (L = PLCC)

A part number may include an alphanumeric suffix that
identifies special device characteristics; for example.
~PD72001L-11 has an 11-MHz data clock rating.

fttIEC

Single-Chip
Microcomputers
Selection Gu ide

NEC Electronics Inc.
4-Bit, Single-Chip CMOS Microcomputers
Supply
Voltage (V)

ROM

RAM

(MHz)

(X8)

(X4)

110

• Package

Pins

LCD controller/driver

0.4

2.5 to 6.0

128

Mini.flat

LCD controller/driver

0.4

2.5 to 6.0

224

Miniflat

7507

General-purpose

0.4

2.7 to 6.0

128

40
40
52

7508

General-purpose

0.4

2.7 to 6.0

224

DIP
SDIP
Miniflat
DIP
SDiP
Miniflat

75CG08

Piggyback EPROM

0.4

4.5 to 5.5

2K or4K

224

Ceramic DIP

7514

LCD controller/driver

0.5

2.7 to 6.0

256

Miniflat

7527A

FIP controller/driver

0.6

2.7 to 6.0

128

7528A

FIP controller/driver

0.6

2.7 to 6.0

160

75CG28

Piggyback EPROM;
FIP controller/driver
AID converter

0.5

4.5 to 5.5

160

DIP
SDIP
DIP
SDIP
Ceramic DIP

42
42
42
42
42

0.5

2.7 to 6.0

160

0.5

4.5 to 5.5

160

42
42
44
42

7537A

Piggyback EPROM;
AID converter
FIP controller/driver

DIP
SDIP
Miniflat
Ceramic DIP

0.6

2.7 to 6.0

128

7538A

FIP controller/driver

0.6

2.7 to 6.0

160

75CG38

Piggyback EPROM;
FIP controller/driver

0.5

4.5 to 5.5

160

DIP
SDIP
DIP
SDIP
Ceramic DIP

42
42
42
42
42

7554

Serial I/O; external clock
or RC oscillator
Serial I/O; external clock
or RC oscillator

0.7

2.7 to 6.0

0.7

4.5 to 6.0

lK
OTPROM
lK

SDIP
SOP
SDIP
SOP
SDIP
SOP
SDIP
SOP
SDiP
SOP
SDIP
SOP

20
20
20
20
20
20
20
20
24
24
24
24

SDiP
SOP
SDIP
SOP
SDIP
Miniflat

24
24
24
24
42
44

Device,
iJ.PD

Features

7502
7503

7533

75CG33

75P54

Clock

7564

Serial I/O; ceramic oscillator

0.7

2.7 to 6.0

75P64

Serial I/O; ceramic oscillator

0.7

4.5 to 6.0

7556

Comparator; external
clock or RC oscillator

0.7

2.7 to 6.0

75P56

Comparator; external
clock or RC oscillator

0.7

4.5 to 6.0

lK
OTPROM

7566

Comparator; ceramic oscillator

0.7

2.7 to 6.0

75P66

Comparator; ceramic oscillator

0.7

4.5 to 6.0

75004

General-purpose

4.19

2.7 to 6.0

lK
OTPROM
4K

512

40
40
52

Plastic unless ceramic (or cerdip) is specified .
• Under development; consult Microcontroller Marketing for availability.

1-3

tttlEC

Singl'e..Chip
4-8it, Single-Chip CMOS Microcomputers (cont)
Device,

Clock

Supply
Voltage (V)

ROM

(MHz)

(XS)

RAM
(X4)

110

• Package

Pins

General-plirpose

4.19

2.7106.0

512

7500S·

General-purpose

4.19

2.7106.0

512

75POO8

General-purpose

4.19

4.5105.5

512

75028·

AID converter

4.19

2.7106.0

8K
OTPROM
8K

512

75P028·

AID converter

4.19

4.5106.0

512

75048·

AID converter; 0.5K EEPROM

4.19

2.7106.0

512

75104

High-end wilh 8-bit instruction

4.19

2.7106.0

4096

320

75106

High-end with 8-bit instruction .

4.19

2.7106.0

6016

320

75108

High-end wilh 8-bii inslruction

4.19

2.7106.0

8064

512

75P108

High-end wilh 8-bil inslruction;
on-chip OTPROM or UVEPROM

4.19

4.5105.5

8064

512

75112

High-end wilh 8-bil instruction

4.19

2.7106.0

12,032

512

75116

High-endwilh 8-blt instruction

4.19

2.7106.0

16,128

512 .

75P116

High-end with 8-bit inslruction

4.19

4.510.5.5

512

75206

FIP conlrollerldriver

4.19

2.710.6.0

16,128
OTPROM
6016

369

75208

FIP conlroller/driver

4..19

2.7106.•0

8064

497

75CG208

4•.19

4.5105.5

8064

512

75212A

FIP conlrollerldriver;
piggyback EPROM
FIPconlroller/driver

4.19

2.7. to 6.0

12,160'

512

75216A

FIP conlroller/driver

4.19

2.7106.0

16,256

512

75CG216A

4.19

4.5105.5

16,256

512

75P216A·

FIP controller/driver;
piggyback EPROM
FIP controller/driver

4.19

4.5105.5

512

75268·

FIP controller/driver

4.19

2.7 to 6.0

16,256
OTPROM
8064

SDiP
Miniflal
SDiP
Miniflal
SDiP
Miniflat
SOIP
Miniflal
SOIP
Miniflal
SOIP
Miniflal
SOIl'
Miniflal
SDiP
Miniflat
SDiP
Miniflal
OIP
Miniflal
Shrinkcenlip
SOIP
Miniflal
SDiP
Miniflal
OIP
Miniflat
SOIP
Miniflal
SDiP
.Miniflal
Ceramic SOIP
Ceramic flatpack
SOIP
Miniflat
SOIP
Miniflal
CeramicSOIP
Ceramic miniflal
SOIP

512

SDiP
Ralpack

75304

LCO·controller/driver

4.19

2.7106.0

512

Miniflal

512

Miniflal

I1PD

Featuree

75006

44
42
44
42

44
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64

75306

LCO conlrollerldriver

4.19

2.7106..0

75308

LCO conlrollerldriver

4.19

2.7 10 6.0

512

Miniflat

75P308

LCO conlrollerldriver;
on-chip OTPROM or UVEPROM

4.19

4.5105.5

512

Miniflat
Ceramic LCC

LCO controller/driver

4.19

Miniflat

75312

1-4

2.7 to 6.0

12K

512

tt1EC

Single-Chip

4-Bit, Single-Chip CMOS Microcomputers (cont)
Device,
J.lPD

Features

75316
75P316A'

Clock
(MHz)

Supply
VoHage(V)

ROM

RAM

(X8)

(X4)

110

LCD conlroller/driver

4.19

2.7106.0

16K

512

Miniflal

4.19

2.7 10 6.0

16K

512

4.19

2.7106.0

8064

512

Miniflal
Ceramic lCC
Miniflal

80
80
80

4.19

4.5105.5

Miniflal

4.19

2.7106.0

8064
OTPROM
1920

512

75402

LCD conlroller/driver;
on-chip OTPROM or UVEPROM
LCD controller/driver;
AID converter
LCD conlroller/driver;
AID converter
low-end

DIP
SOIP
Miniflal

28
28
44

75P402

low-end

4.19

4.5105.5

1920
OTPROM

DIP
SDIP
Miniflal

28
28
44

75516

High-end; AID converter

4.19

2.7106.0

16K

512

Miniflal

75P516

High-end; AID converter

4.19

4.5105.5

16K
OTPROM

512

Miniflal
lCC

80
80

75328
75P328

Package

Pins

a-Bit, Single-Chip NMOS/CMOS Microcomputers
Device,
J.lPD

Features

7810H

Clock
(MHz)

Supply
Voltage (V)

ROM

RAM

(X8)

I/O

NMOS; AID converter

4.5105.5

External

256

7811H

NMOS; AID converter

4.5105.5

256

78PGliH

4.5105.5

256

64
64
64
64
64

78Cl0f78Cl0A

NMOS; AID converter
piggyback EPROM
CMOS; AID converter

SDIP
QUIP
SOIP
QUIP
Ceramic QUIP

4.5105.5

Exlernal

256

78Cl1f78Cl1A

CMOS; AID converter

4.5105.5

256

78CI2A

CMOS; AID converter

4.5105.5

256

78C14

CMOS; AID converter

4.5105.5

16K

256

64
64
64
68
64
64
64
68
64
64
64
68
64
64
64
68

78CP14

CMOS; AID converter

4.5105.5

16K
OTPROM

256

16K
UVEPROM

256

QUIP
SOIP
Miniflal
PlCC
QUIP
SOIP
Miniflal
PlCC
QUIP
SDIP
Miniflal
PlCC
QUIP
SOIP
Miniflal
PlCC
QUIP
SDIP
Miniflat
PlCC
Ceramic QUIP
Shrink cerdip

Package

Pins

64
64
64
68
64
64

1-5

t-IEC

Single-Chip
8-Blt, Single-Chip NMOS/CMOS Microcomputers (cant)
Device,
ILPD

Clock
(MHz)

Supply

ROM

RAM

Voltage (V)

(X8)

110

1/ Package

78213

CMOS; AID converter;
advanced peripherals

4.5105.5

External

512

78214

CMOS; AID converter;
advanced peripherals

4.5105.5

16K

512

78P214

CMOS; AID converter;
advanced peripherals

4.5105.5

16K
OTPROM

512

640

SDIP
QUIP
Miniflal
PLCC
SDIP
QUIP
Miniflal
PLCt
SDiP
QUIP
Miniflat
PLCC
Shrink cerdip
Ceramic QUIP
PLCC
Miniflal
PLCC
Miniflal
PLCC
Miniflat
Miniflat
Miniflat
, PLCC.

78220
78224
78P224
78233·

78234·

78P234 •

Features

CMOS; analog comparalor;
large 110
CMOS; analog comparalor;
large 110
CMOS; analog comparalor;
large 110
CMOS; real-lime outputs;
AID and D/A converters

4.5105.5

16K
UVEPROM
External

12.

4.5105.5

16K

640

4.5105.5

640

4.5105.5

16K
OTPROM
External

640

CMOS; .real-lime outputs;
AID andD/A converters

CMOS; real-lime outputs;
AID and D/A converters

4.5 to 5.5

4.5105.5

16K

16K
OTPROM

640

'640

MinifJat
Miniflal
PLCC
Miniflal
Miniflat
PLCC

Pins
64
64
74
68
64
64
74
68
64
64
74
68
64
64
84
94
84
94
84

04
SO'
94
84 .

SO
94
84
,80
94
84

16-Blt, Single-Chip CMOS Microcomputers
Device,
ILPD

Features

78310A

Clock
(MHZ)

Supply
VoltageM

ROM

RAM

(X8)

110

Real-lime molor control

4.5105.5

External

256

78312A

Real-time motor control

4.5 to 5.5

256

78P312A

Real-time molor control

4.5 to 5.5

8K
UVEPROM
8K
OTPROM

256

SDIP
QUIP
Miniflat
PLCC
SDIP
QUIP
Miniflat
PLCC
Shrink cerdip
Ceramic QUIP
SDIP
(jUIP
PLCC
Miniflat
PLCC
Miniflal
PLCC

78320
78322

High-end; advanced analog
and digital peripherals
High-end; advanced analog
and digital peripherals

4.5105.5

External

640

4.5 to 5.5

16K

640

Package

Pins
64
64
64
68
64
64
64

68
64
64
64
64
68
64
68
64
68

[WEe

Single-Chip

16-Bit, Single-Chip CMOS Microcomputers (cont)
Device,
J,1PD
78P322
71P301

Features

Clock
(MHz)

Supply
Voltage (V)

ROM

RAM

(X8)

110

'Package

Pins

4.5 to 5.5

16K
OTPROM
16K

640

PLCC

PLCC
Minillat
Ceramic QUIP

44
64
64

ROM

RAM

(X8)

110

' Package

Pins

High-end; advanced analog
and digital peripherals
Port and memory extender
used with 7832X
microcomputer family;
UVEPROM or OTPROM

4.5 to 5.5

a-Bit, Single-Chip Microcomputers
Device,
J,1PD

Features

8035HL
8039HL

Clock
(MHz)

Supply
Voltage (V)

HMOS

4.5 to 5.5

External

DIP

HMOS

4.5 to 5.5

External

128

DIP

80C39H

CMOS

2.5 to 6.0

External

128

DIP
Miniflat

40
44

80C40H

CMOS

2.5 to 6.0

External

256

DIP

8041AH

NMOS; universal PPI

4.5 to 5.5

DIP

80C42

CMOS; universal PPI

4.5 to 5.5

128

DIP
Miniflat

40
44

8048H

HMOS

4.5 to 5.5

DIP

8049H

HMOS

4.5 to 5.5

128

DIP

80C49H

CMOS

2.5 to 6.0

128

DIP

49H

CMOS

2.5 to 6.0

128

Miniflat

80C50H

CMOS

2.5 to 6.0

256

DIP

50H

CMOS

2.5 to 6.0

256

Minillat

8741A

NMOS; universal PPI; UVEPROM

4.5 to 5.5

Cerdip

8748H

NMOS; OTPROM or UVEPROM

4.5 to 5.5

8749H

HMOS; OTPROM or UVEPROM

4.5 to 5.5

128

DIP
Cerdip
DIP
Cerdip

40
40
40
40

1-7

Single.-Chip

1-8

ttiEC

t't{EC

V-Series
Microprocessors and Peripherals
Selection Guide

NEG Electronics Inc.
CMOS Microprocessors
Device,
IlPD

Features

70008A

'Z80 microprocessor

Data
BHs

Clock
(MHz)

70108
(V20)

8088 compatible; enhanced

8/16

80r 10

70116
(V30)

8086 compatible; enhanced

80rl0

70208
(V40)

MS-DOS, V20 compatible CPU with peripherals

8/16

8 or 10

70216
(V50)

MS-DOS, V30 compatible CPU with peripherals

16/16

80rl0

70616
(V60)
70632
(V70)
70832
(V80)
70136
(V33)
70236
(V53)

32-bit; high-speed

16/32

32-bit; high-speed

32132

20/25

32-bit; high-speed

32132

Hardwired, enhanced V30

V33 core-based; high-integration; DMA, serial 110,
interrupt controller, etc.

70320
(V25)

MS-DOS compatible; high-integration; DMA, serial 110,
interrupt controller, etc.

8/16

50r8

70330
(V35)
70325
(V25+)
70335
(V35+)

MS-DOS compatible; high-integration; DMA, serial 110,
interrupt controller, etc.
MS-DOS compatible; high-integration; high-speed DMA

8/16

8 or 10

MS-DOS compatible; high-integration; high-speed DMA

80r 10

70327
(V25 Software Guard)
70337
(V35 Software Guard)

MS-DOS compatible; high-integration; software protection

8/16

MS-DOS compatible; high-integration; software protection

79011
(V25 RTOS)

MS-DOS compatible; high-integration; real-time operating system

8/16

79021
(V35 RTOS)
70322
(V25 ROM)

MS-DOS compatible; high-integration; real-time operating system

8/16

MS-DOS compatible; high-integration; 16K-byte ROM

Package

DIP
Miniflat
PLCC
DIP
Ceramic DIP
Miniflat
PLCC
DIP
Ceramic DIP
Miniflat
PLCC
Ceramic PGA
PLCC
Miniflat
PGA
PLCC
Miniflat
PGA

Pins
40

44
44
40
40
52

44
40
40
52
44
68
68
80
68
68
80
68

PGA

132

Ceramic PGA

208

120r16

PGA
PLCC
Ceramic PGA

68
68
132

PLCC
Miniflat
PLCC
Miniflat
PLCC
Miniflat
PLCC
Miniflat
PLCC
Miniflat
PLCC
Miniflat
PLCC
Miniflat

84
94
84
94
84
94
84
94
84
94
84
94
84
94
84
94
84

PLCC
Miniflat
PLCC

# Plastic

unless ceramic (or cerdip) is specified .
• For additional information, refer to 1987 Microcomputer Data Book.

1-9
--------

t\fEC

V-Series
CMOS Microprocessors (cont)
Device,
JlPD
70P322
70332
(V35 ROM)

Features
MS-DOS compatible; high-integration; 16K-byte UVEPROM;
V25 or vas mode
MS-DOS compatible; high-integration; 16K-byte ROM

Clock

Data
Bits

(MHz)

8/16

Ceramic LCC

PLCC

Data
Bits

(MHz)

Package

Pins

NMOS and HMOS Microprocessors
Device,
JlPD

Features

808SA

'S-bit microprocessor; NMOS or HMOS

DIP

8086

'16-bit microprocessor; HMOS

Cerdip

Ceramic DIP

Data
Bits

(MHz)

8088

'8-bit microprocessor; HMOS

Clock
/I

Package

Pins

CMOS System Support Products
Device,
JlPD

Name

Clock

71011

Clock Pulse GeneratorlDriver

71037

Programmable DMA Controller

71051

Serial Control Unit

8/10

71054

Programmable Timer/Controller

8/10

71055

Parallel Interface Unit

8/10

DIP
Miniflat
PLCC

71059

Interrupt Control Unit

8/10

DIP
Miniflat
PLCC
DIP
Ceramic DIP
Miniflat
PLCC
DIP
SOP
DIP
SOP
DIP
SOP
DIP
SOP
DIP
SOP

Package

DIP
SOP
DIP
Miniflat
PLCC
DIP
Miniflat
PLCC
DIP
Miniflat

FLee

8/16

8/10

Transparent Latch

71083

Transparent Latch

71084

Clock Pulse GeneratorlDriver

71086

Bus BufferlDriver

71087

Bus BufferlDriver

71071

DMA Controller

71082

1-10

Pins
18
20
40
40
44
28
44
28
24
44
28
40
44
44
28

44
28
48
48
52
52
20
20
20
20
18
20
18
20
20
20

NEe

V-Series

CMOS System Support Products (cont)
Device,
IJ.PD

Name

71088

System Bus Controller

82C43

-lnpuVOutput Expander

Data
Bits

Clock
(MHz)
8/10
5

Package

DIP
SOP
DIP
Skinny DIP

Pins
20
20
24
24

NMOS System Support Products
Device,
IJ.PD

Name

8155H
8156H

Data
Bits

Clock
(MHz)

-256 x 8 RAM; 110 ports and timer

3 or 5

DIP

- 256 x 8 RAM; I/O ports and timer

30r5

DIP

8237A

-Programmable DMA Controller

DIP

8243

- InpuVOutput Expander

DIP

8251A

-Programmable Communications Interface

3/5

DIP

8253

-Programmable Internal Timer

DIP

8255A

-Programmable Peripheral Interface

DIP

8257

-Programmable DMA Controller

DIP

8259A

-Programmable Interrupt Controller

DIP

8279

-Programmable Keyboard/Display Interface

DIP

Package

Pins

1-11

V-Series

1-12

t-IEC

ttlEC

Intelligent
Peripheral Devices (IPD)
Selection Guide

NEe Electronics Inc.
Communications Controllers
Device,
IlPD

Name

Description

7201A

Multiprotocol Serial
Communications Controller

72001

CMOS, Advanced Multiprotocol
Serial Communications
Controller

72002

CMOS, Advanced Multiprotocol
Serial Communications Controller

Dual full-duplex serial channels; four DMA channels;
programmable interrupt vectors; asychronous
COP and BOP support; NMOS
Functional superset of 8530; 8086N30 interface; two
full-duplex serial channels; two digital phase-locked
loops; two baud-rate generators per channel; loopback
test mode; short frame and mark idle detection
Low-cost, singlNhannel version of 72001; software
compatible; direct interface to 8237 DMA.

CMOS, HDLC Controller

Not included in 1989-1990 IPD Data Book; refer to 72002
data sheet.
Single full-duplex serial channel; on-chip DMA Controller.

72101

Data Rate

' Package

Pins

1 Mb/s

DIP
Ceramic DIP

40
40

2.2 Mb/s

DIP
Miniflat
PLCC

40
52
52

2.2 Mbls

DIP
Miniflat
PLCC

40
44
44

DIP
PLCC

64
68

4 Mbls

Not included in 1989-1990 IPD Data Book; refer to 72101
data sheet

Graphics Controllers
Device,
IlPD
7220A

72020
72022
72120

72123

Name

Description

High-Performance
Graphics Display
Controller
Graphics Display
Controller
Intelligent Display
Processor
Advanced Graphics
Display Controller

General-purpose, high-integration controller; hardwired
support for lines, arc/Circles, rectangles, and graphics
characters; 1024x1024 pixel display with four planes
CMOS 7220A with 2M video memory; dual-port RAM control;
write-masking on any bit; enhanced external synch
Display and image processing for text and sprites; three display
modes; four-way horizontal split-screen display; CMOS
High-speed graphics operations including paint, area fill,
slan~ arbitrary angle rotate, up to 16x enlargement and
reduction; dual-port RAM control; CMOS
Enhanced 72120; expanded command set; improved painting
performance; laser printer interface controls; CMOS

Advanced Graphics
Display Controller II

Drawing Rate 'Package Pins
500 ns/dot

Ceramic DIP

500 ns/dot

DIP
Miniflat
PLCC
Miniflat
PLCC
Miniflat

40
52
68
80
84
94

PLCC
Miniflat

84
94

500 ns/dot
500 ns/dot

400 ns/dot

Advanced Compression/Expansion Engine
Device,
IlPD
72185

Name

Description

'Package Pins

Advanced Compression!
Expansion Engine

High-speed CCITI Group 3/4 bit-map image compression/expansion (M test
chart, 400 PPI x 400 LPI in under 1 second); 32K-pixelline length; 32-megabyte
image memory; on-chip DMA and refresh timing generator; CMOS

SDIP
PLCC

64
68

'Plastic unless ceramic (or cerdip) is specified.

1-13

IPD
Floppy-Disk Controllers
Device,
J,lPD

Name

Description

765A1B

Floppy-Disk Controller

500 kb/s

DIP

71065/66

Floppy-Disk Interface

500 kb/s

72065/65B

CMOS Floppy-Disk
Controller

Industry-standard controller supporting IBM 3740 and IBM
System 34 double-density format; enhanced 765.B supports
multitasking applications
Compatible with 765-family controllers .and others; supports
mUltiple data rates from 125 to 500 kb/s
100% 765AIB microcode compatible; compatible with 808x
microprocessor families
.

72067

Floppy-Disk Controller

500 kb/s

72068

Floppy-Disk Controller

72069

Floppy-Disk Controller

CMOS; 765A1B microcode compatible; clock generation/
switching circuitry; selectable write precompensation;
digital phase-locked loop
All features of the 72067 plus IBM-PC, PCIXT, PC/AT, or
PS/2 style registers; 24-ma high-current drivers
All features of the 72067/68 with substitution of highperformance analog phase-locked loop for digital PLL

SOP
SDIP
DIP
PLCC
Miniflat
DIP
Miniflat
PLCC
Miniflat
PLCC
PLCC
Miniflat

28
30
40
44
52
48
52
52
80
84
84
100

Transfer
Rate

1 Mb/s

500 kb/s
1 Mb/s

Package Pins

Hard-Disk Controllers
ReadlWi'Ua

DeVice,
J,lPD

Name

Description

Clock

7261A1B

Hard-Disk Controller

23 MHz

Ceramic DIP

7262

Enhanced Small-Disk
Interface (ESDI) Controller
CMOS Hard-Disk
Controller

Supports eight drives in SMD mode, four drives in ST506
mode; error correction and detection
Serial-mode ESDI compatible; controls up to seven drives;
supports up to 80 heads; hard and soft-sector interfacing
Supports SMD/SMD-E and ST5061412 type drives

H!MHz

Ceramic DIP

24 MHz

Selectable 8/16 data bus width; 16 high-level commands
for reduced CPU load; single-command automatic
execution; 4-Mb sync/async; CMOS

16MHz

DIP
Miniflat
PLCC
SDiP
Miniflal
PLCC

40
52
52
64
74
68

72061

72111

1-14

Small Computer System
Interface (SCSI) Controller

Package Pins

t-IEC

DSPand
Speech Products
Selection Guide

NEe Electronics Inc.
Digital Signal Processors
Device,
I1PD

Description

7720A

Instruction
Cycle (n8)

Instruction
ROM (Bits)

Data ROM
(Bha)

Data RAM
(Bha)

16-bit, fixed-point DSP; NMOS

244

512x23

510x 13

128 x 16

77C20A

16-bit, fixed-point DSP; CMOS

244

512x 23

510x 13

128 x 16

77P20

16-bit, fixed-point DSP; CMOS

244

16-bit, fixed-point DSP; CMOS

122

510 x 13
UVEPROM
1024 x 16

128 x 16

77C25

512x23
UVEPROM
2048x24

77P25

16-bit, fixed-point DSP; CMOS

122

1024 x 16
OTPROM
1024 x 16
UVEPROM
1024 x 24

, Package

Pins

DIP
PLCC
DIP
PLCC
PLCC
Cerdip

28
44
28
28
44
28

DIP
PLCC
DIP
PLCC
Cerdip

28
44
28
44
28

512 x 24

Ceramic PGA
PLCC

68
68

256 x 16
256 x 16

77220

24obit, fixed-point DSP; CMOS

122

2048 x 24
OTPROM
2048 x 24
UVEPROM
2048x32

77230AR

32-bit, floating-point DSP; CMOS

150

2048x32

1024 x 32

Ceramic PGA

77230AR-oG3

150

nla

Ceramic PGA

77P230R

32-bit, floating-point DSP; CMOS;
standard library software
32-bit, floating-point OSP; CMOS

150

Ceramic PGA

16-bit fixed-point modem DSP; CMOS

181

1024 x 32
UVEPROM
1024 x 16

1024x32

77810

2048x32
UVEPROM
2048 x 24

256 x 16

7281

Image pipelined processor; NMOS

nfa

nla

512x 18

Ceramic PGA
PLCC
Ceramic DIP

68
68
40

9305

Support device for 111'07281
processors; CMOS

nla

Ceramic PGA

132

'Package

Pins

5-MHz
clock
10-MHz
clock

256 x 16

Speech Processors
DeVice,
I1PD

Name

7730
77C30

Data ROM
(Bits)

Technology

Clock
(MHz)

ADPCM Speech EncoderlDecoder
ADPCM Speech Encoder/Decoder

NMOS
NMOS

8
8

7755

ADPCM Speech Synthesizer

CMOS

0.7

96K

7756

ADPCM Speech Synthesizer

CMOS

0.7

256K

77P56

ADPCM Speech Synthesizer

CMOS

0.7

7757

ADPCM Speech Synthesizer

CMOS

0.7

256K
OTPROM
512K

7759

ADPCM Speech Synthesizer

CMOS

0.7

1024K
external

DIP
DIP
PLCC
DIP
SOP
DIP
SOP
DIP
SOP
DIP
SOP
DIP
Miniflat

28
28
44
18
24
18
24
20
24
18
24
40
52

Plastic unless ceramic (or cerdip) is specified.

1-15

DSPand Speech

1-16

tttfEC

V-Series
Development Tools
Selection Guide

NEe Electronics Inc.
V-Series Development Tools Selection Guide
Part
Number
(Note 1)

Full
Emulstor

Full
Emulator
Probe

MInI-IE
Emulstor

Mlnl-lE
Probe

Relocatable
EvaluatIon EPROM/OTP Assembler CCompller
DevIce
(Note 13)
(Note 14)
Boards

"PD70136GJ-12 IE-70136-AOI6

EP-70136L-A
(Note 2)

IE-70136-PC

EP-70136L-PC DDK-70136
(Note 2)

RA70136

CC70136

"PD70136GJ-16 IE-70136-AOI6

EP-70136L-A
(Note 2)

IE-70136-PC

EP-70136L-PC DDK-70136
(Note 2)

RA70136

CC70136

"PD70136L-16

IE-70136-AOI6

EP-70136L-A

IE-70136-PC

EP-70136L-PC DDK-70136

RA70136

CC70136

"PD70136L-12

IE-70136-AOI6

EP-70136L-A

IE-70136-PC

EP-70136L-PC DDK-70136

RA70136

CC70136

"PD70136R-12

1E-70136-AOI6

EP-70136L-A
(Note 3)

IE-70136-PC

EP-70136L-PC DDK-70136
(Note 3)

RA70136

CC70136

"PD70136R-16

IE-70136-AOI6

EP-70136L-A
(Note 3)

IE-70136-PC

EP-70136L-PC DDK-70136
(Note 3)

RA70136

CC70136

"PD70208GF-8

IE-70208-A010

(Note 12)

EB-V40MINI-IE

EB-70208

RA70116

CC70116

"PD70208GF-l0 IE-70208-A010

(Note 12)

EB-V40MINI-IE

EB-70208

RA70116

CC70116

"PD70208L-8

IE-70208-A010

IE-70000-2958 EB-V40MINI-IE

ADAPT68PGA EB-70208
68PLCC
(Note 4)

RA70116

CC70116

"PD70208L-l0

IE-70208-A010

IE-70000-2958 EB-V40MINI-IE

ADAPT68PGA EB-70208
68PLCC
(Note 4)

RA70116

CC70116

"PD70208R-8

IE-70208-A010

IE-700oo-2959 EB-V40MINI-IE

(Note 4)

EB-70208

RA70116

CC70116

"PD70208R-l0

IE-70208-A010

1E-700oo-2958 EB-V40MINI-IE

(Note 4)

EB-70208

RA70116

CC70116

"PD70216GF-8

IE-70216-A010

(Note 12)

EB-V50MINI-IE

EB70216

RA70116

CC70116

"PD70216GF-l0 IE-70216-A010

(Note 12)

EB-V50MINI-IE

EB70216

RA70116

CC70116

"PD70216L-8

IE-70216-A010

IE-700oo-2958 EB-V50MINI·IE

ADAPT68PGA EB70216
68PLCC
(Note 4)

RA70116

CC70116

"PD70216L-l0

IE-70216-A010

IE-700oo-2958 EB-V50MINI·IE

ADAPT68PGA EB70216
68PLCC
(Note 4)

RA70116

CC70116

"PD70216R-8

IE-70216-A010

IE-700oo-2958 EB-V50MINI·IE

(Note 4)

EB70216

RA70116

CC70116

"PD70216R-l0

IE-70216-A010

IE-700oo-2959 EB-V50MINI·IE

(Note 4)

EB70216

RA70116

CC70116

"PD70320GJ

IE-70320·A008

EP-70320GJ
(Note 5)

EB-V25MINI·IE·P Ep-70320GJ
(Note 6)

DDK-70320

RA70320

CC70116

"PD70320GJ-8

IE-70320-A008

EP-70320GJ
(Note 5)

EB-V25MINI·IE·P EP-70320GJ
(Note 6)

DDK-70320

RA70320

CC70116

"PD70320L

IE-70320·A008

EP-70320L

EB-V25MINI·IE·P (Note 7)

DDK-70320

RA70320

CC70116

"PD70320L-8

IE-70320-AOO8

EP-70320L

EB-V25MINI·IE·P (Note 7)

DDK-70320

RA70320

CC70116

"PD70322GJ

IE-70320·A008

Ep-70320GJ
(Note 5)

EB-V25MINI·IE·P Ep-7032OGJ
(Note 6)

DDK-70320

RA70320

CC70116

"PD70322GJ-8

IE-70320·A008

EP-70320GJ
(Note 5)

EB-V25MINI·IE·P Ep-70320GJ
(Note 6)

DDK-70320

RA70320

CC70116

"PD70322L

IE-70320-A008

Ep-70320L

EB-V25MINI·IE·P (Note 7)

DDK-70320 70P322K
(Note 10)

RA70320

CC70116

50173

1-17

t\'EC

V-Series
V-Series Development Tools Selection Guide (cont)

Relocatable
Evaluation EPROM/OTP Assembler C Complier
Boards
Device
(Nota 13)
(Note 14)

Part
Number
(Note 1)

Full
Emulator

Full
Emulator
Probe

Mlnl·IE
Emulator

"PD70322L·S

IE·70320·AOOS

EP·70320L

EB-V25MINI-IE-P (Note 7)

DDK70320

"PD70325GJ-S

IE·70325-AOOS

EP-70320GJ
(Note 5)

(Note 12)

"PD70325GJ-l0 IE-70325-AOOS
(Note S)

EP-70320GJ
(Note 5)

(Note 12)

EP-70320L

"PD70325L-S

IE-70325-AOOS

Mlnl·IE
Probe

70P322K
(Note 10)

RA70320

CC70116

DDK-70325

RA70320

CC70116

(Note 12)

DDK-70325

RA70320

CC70116

(Note 12)

DDK-70325

RA70320

CC70116

(Note 12)

DDK-70325

RA70320

CC70116

"PD70325L-l0

IE-70325-A008
(Note S)

EP-70320L

(Note 12)

/lPD70327GJ-S
(Note 9)

IE-70320'AOOS

EP-70320GJ
(Note 5)

EB-V25MINI-IE-P EP-70320GJ
(Note 6)

RA70320

CC70116

/lPD70327L-S
(Note 9)

IE-70320-AOOS

EP·70320L

EB-V25MINI-IE-P (Note 7)

RA70320

CC70116

"PD70330GJ-S

IE-70330-A008

EP-70320GJ
(Note 5)

EB-V35MINI-IE-P EP-70320GJ
(Note 6)

DDK-70330

RA70320.

CC70116

/lPD70330L-S

IE-70330-A008

EP-70320L

EB-V35MINI-IE-P (Note 7)

DDK-70330

RA70320

CC70116

/tPD70332GJ-8

IE-70SS0-AOOS

EP-70320GJ
(Note 5)

EB-V35MINI-IE-P EP-70320GJ
(Note 6)

DDK-70330

RA70320

CC70116

"PD70332L-S

IE-70330-A008

EP-70320L

EB-V35MINI-IE-P (Note 7)

DDK-70330 70P322K
(Note 10)

RA70320

CC70116

"PD70335GJ-S

IE-70335-AOOS

EP-70320GJ
(Note 5)

(Note 12)

DDK-70330

RA70320

CC70116

/lPD70335GJ-l0 IE-70335-AOOS
(Note 8)

EP-70320GJ
(Note 5)

(Note 12)

DDK-70330

RA70320

CC70116

/lPD70335L-S

IE-70335-AOOS

EP-70320L

(Note 12)

DDK-70330

RA70320

CC70116

/lPD70335L-l0

IE-70335·AOOS
(Note S)

EP-70320L

(Note 12)

DDK-70330

RA70320

CC70116

"PD70337GJ-S
(Note 9)

IE·70330-AOOS

EP-70320GJ
(Note 5)

EB-V35MINI-IE-P EP-70320GJ
(Note 6)

RA70320

CC70116

/lPD70337L-S
(Note 9)

IE-7.0330·AOOS

EP-70320L

EB-V35MINI-IE-P (Note 7)

RA70320

CC70116

"PD79011 GJ-S
(Note 11)

IE-70320·AOOS

EP-70320GJ
(Note 5)

(Note 12)

RA70320

CC70116

/lPD79011 L-S
(Note 11)

+ IE-70320-RTOS EP-70320L

(Note 12)

RA70320

CC70116

"PD79021L-S
(Note 11)

IE-70330-A00S
EP-70320L
+IE-70330-RTOS

(Note 12)

RA70320

CC70116

Notes:
( 1) Packages:
Package
GF
GJ
K
L
R

Description
SO-pin plastic mlnlflat
74-pin or 94-pin plastiC miniflat
S4'pin ceramic LCC with window
6S-pln or 84·pln plastic lCC
6S-pln PGA

e2) The EP-70136Gl,A and EP·70136L-PC contain both a 6S-pin

PlCC probe and an adapter which converts the 6S-pin PLCC
probes to a 74-pin miniflat footprint.

1-18

( 3) 6S-pln PGA parts are supported by using the Ep·70136L-A PLCC
probe or EP-70136L·PC PLCC probe, plus a PLCC socket with a
PGA-plnout. A PLCC socket of this type Is supplied with the
EP-70136L-A.
( 4) The EB-V40 MINI-IE and EB-V50 MINI-IE support PGA packages
directly; the ADAPT6SPGA6SPLCC adaptor converts the PGA·
pinout on the MINI-IE to a PlCC footprint. This adaptor Is
supplied with the MINI-IE.

t-lEC
( 5) The EP-70320GJ Is an adaptor to the EP-70320L, which converts
54-pin PLCC probes to a 94-pin mlnlflat footprint. For GJ parts,
both the PLCC probe and the adaptor are needed.
( 6) The EP-70320GJ adaptor can be used to convert the supplied
84-pln PLCC cable of the EB-V25 MINI-IE-P or EB-V35 MINI-IE-P
to a 94-pin mlniflat.

( 7) The EB-V25 MINI-IE-P and EB-V35 MINI-IE-P are supplied with an
84-pln PLCC cable.
( 8) At the current time, the emulators for the IIPD70325 and
IIPD70335 are specified to 8 MHz. Contact your local NEC Sales
Office for the latest Information on 10 MHz emulation.
( 9) Development for the "PD70327 or "PD70337 can be done using
the appropriate IIPD70320 or "PD70330 tools; however, debugging of programs In the Software Guard mode Is not supported
at this time.
(10) The "PD70P322K EPROM device can be used for both "PD70322
and IIPD70332 emulation. The IIPD70P322K EPROM device can
be programmed by using the PA-70P322L Programming Adapter
and the PG-1500 EPROM Programmer.
(11) For emulation of IIPD79011 or iiPD79021, the base emulator
~E-70320 or IE-70330) plus Real-Time Operating System software IE-70320-RTOS or IE-70330-RTOS) is required.

V-Series
(13) The following relocatable assemblers are available:
RA70116-D52 For V2rP'/V30 operating system. (ASM75-D52).

MS-DOS is registered trademark of Microsoft Corporation.

1-23

pPD75XX Series

1-24

t\fEC

NEe
NEe Electronics Inc.

pPD75XXX Series
Development Tools
Selection Guide

"PD75XXX Series Development Tools Selection Guide
Part Number
(Note 7)

Main Board
Emulator*

Add-on
Board*

Emulation
Prob,*

"PD75004CU

EVAKlT-75X

EV-75008

(Note 3)

"PD75006GB

EVAKIT-75X

EV-750OB

EP-750OBGB

"PD75006CU

EVAKIT-75X

EV-750OB

(Note 3)

"PD75006GB

EVAKIT-75X

EV-750OB

EP-750OBGB

Optional Socket
Adapter (Note 1)
EV-9200G-44

EV-9200G-44

EPROM/OTP
Device (Note 2)

R,locatable
Aseembler
(Note 5)

Structured
Anembler
(Note 6)

"PD75POO8CU/DU

RA75X

ST75X

"PD75POO8GB

RA75X

ST75X

"PD75POO8CU/DU

RA75X

ST75X

"PD75PO08G B

RA75X

ST75X

"PD75POO8CU/DU

RA75X

ST75X

"PD75POOBG B

RA75X

ST75X

"PD750OBCU

EVAKlT-75X

EV-75008

(Note 3)

"PD750OBGB

EVAKlT-75X

EV-750OB

EP-750OBGB

"PD75POO8CU

EVAKlT-75X

EV-750OB

(Note 3)

RA75X

ST75X

"PD75POOBDU

EVAKlT-75X

EV-750OB

(Note 3)

RA75X

ST75X

"PD75POOBGB

EVAKlT-75X

EV-75008

EP-750OBGB

EV-9200G-44

RA75X

ST75X

"PD75028CW

EVAKlT-75X

EV-75048

(Note 4)

"PD75P028CW

RA75X

ST75X

"PD75028GC

EVAKlT-75X

EV-75048

(Note 4)

"PD75P028GC

RA75X

ST75X

"PD75P028CW

EVAKlT-75X

EV-75048

(Note 4)

RA75X

ST75X

"PD75P028GC

EVAKlT-75X

EV-75048

(Note 4)

RA75X

ST75X

"PD75048CW

EVAKlT-75X

EV-75048

(Note 4)

RA75X

ST75X

"PD75048GC

EVAKlT-75X

EV-75048

(Note 4)

RA75X

ST75X

"PD75104CW

EVAKlT-75X

EV-751OB

(Note 3)

"PD75Pl08CW/DW

RA75X

ST75X

"PD75104G

EVAKlT-75X

EV-751OB

EP-751OBGF

EV-9200G-64

"PD75P1OBG/GF
"PD75P116GF

RA75X

ST75X

"PD75104GF

EVAKlT-75X

EV-751OB

EP-751OBGF

EV-9200G-64

"PD75P1OBG!GF
"PD75P116GF

RA75X

ST75X

"PD75104AGC

EVAKlT-75X

EV-751OB

EP-751OBGF

EV-9200G-64

"PD75106CW

EVAKlT-75X

EV-751OB

(Note 3)

"PD75106G

EVAKlT-75X

EV-751OB

EP-751OBGF

"PD75106GF

EVAKlT-75X

EV-751OB

"PD75108AG

EVAKlT-75X

"PD75108AGC

EVAKlT-75X

EV-9200G-44

RA75X

ST75X

"PD75P1OBCW/DW

RA75X

ST75X

EV-9200G-64

"PD75P1OBG/GF
"PD75Pll6GF

RA75X

ST75X

EP-751OBGF

EV-9200G-64

"PD75P1OBG/GF
"PD75Pl16GF

RA75X

ST75X

EV-751OB

EP-751OBGF

EV-9200G-64

RA75X

ST75X

EV-751OB

EP-751OBGF

EV-9200G-64

RA75X

ST75X

"PD751OBCW

EVAKlT-75X

EV-751OB

(Note 3)

"PD75Pl08CW/DW

RA75X

ST75X

"PD751OBG

EVAKlT-75X

EV-751OB

EP-751OBGF

EV-9200G-64

"PD75Pl08G!GF
"PD75Pl16GF

RA75X

ST75X

"PD751OBGF

EVAKlT-75X

EV-751OB

EP-751OBGF

EV-9200G-64

"PD75Pl08G!GF
"PD75P116GF

RA75X

ST75X

"PD75P1OBBCW

EVAKIT-75X

EV-751OB

(Note 3)

RA75X

ST75X

"PD75P1OBCW

EVAKlT-75X

EV-751OB

(Note 3)

RA75X

ST75X

"PD75P1OBDW

EVAKlT-75X

EV-751OB

(Note 3)

RA75X

ST75X

"PD75P1OBG

EVAKlT-75X

EV-751OB

EP-751OBGF

RA75X

ST75X

"PD75112CW

EVAKlT-75X

EV-751OB

(Note 3)

RA75X

ST75X

EV-9200G-64
"PD75Pl16CW

* Required Tools

110175

1-25

Stbe'

pPD75XXX Series

'j"

.".,'.

~:~'

",'

...

,;'1.'

"PD75XXX Series Development Tools Selection Guide (cont)
Part Number
(Note 7)

Main Board
Emulator*

Add-on
Board*

Op~lonal

Socket
Adapter (Note 1)

EPROM/OTP
Device (Note 2)

Relocatable
A.88mbler
(NoteS)

Structured
A••embl.r
(NOte 6) "

EV-9200G-64

"PD75P116GF

RA75X

ST75X

"PD75P116CW

RA7S)(.

ST7s)( .

"PD75P116GF

RA75X

'S17S)(

RA75X

ST7s)(

RA7S)(

ST7s)(

"PD75112GF

EVAKlJ.75X

EV~75108

Emulation
1"rob4I*
EP-75108GF

"PD75116CW

:EVAKlT-75X

EV-75108

(Nota 3)

"PD75116GF

EVAKlT-75X

EV-76108

EP-75108GF

EV-9200G-64

"PDi5P116BGF

EVAKlT-75X

EV-76108

EP-75108GF

EV-9200G-64

"PD75P11eCw

EVAKlT-75X

EV-75108

(Nota 3)

"PD75P116GF

EVAKlT-75X

EV-75108

EP-75108GF

"PD75206CW

EVAKlT-7S)(

EV·7521.6A

(NoteS)

"PD75206G

EVAKlJ.75X

EV·75216A

EP-75216AGF

"PD7520sCW

EVAKlJ.75X

EV·75216A

(Note 3)

"PD75208G

EVAKlJ.75X

EV·75216A

EP·75216AGF

"PD75CG206AE

EVAKlJ.75X

EV·75216A

(llioteS)

"PD75CG208AEA

EVAKlJ.75X

EV.75216A

EP·75216AGF

"PD75212ACW

EVAKlJ.75X

EV.75216A

(Note 3)

"PD75212AGF

EVAKI;:'75X

EV·75216A

EP·75216AGF

"PD75216ACW

EVAKlJ.75X

EV·75216A

(Note 3)

"PD75216AGF

EVAKlJ.75X

E\i·75216A

EP·75216AGF

"PD75CG216AE

EVAKlJ.75X

EV.75216A

(Note 3)

"PD75CG216AEA

EVAKlT-75X

EV·75216A

EP·75216AGF

"PD75P216ACW

EVAKlT-75X

EV·75216A

(Note 3)

"PD75P216ACW

"PD75268CW

EVAKlJ.75X

EV·75216A

(Note 3)

"PD75P216A9W

"PD75268GF

EVAKlJ.75X

EV·75216A

EP·75216AGF

EV-920OG~64

"PD75304GF

EVAKlT-75X

EV·75308

(Note 3)

EV-9200G-80

"PD753()6GF

EVAKlT-75X

EV·76308

(Nota 3)

"PD76308GF

EVAKlT-75X

EV·75308

(Note 3)

"PD75P308GF

EVAKlT-75X

EV·75308

(Note 3)

EV-9200G-90

RA75X

ST75X

"PD75P308K

EVAKlT-75X

EV·76308

(Note S)

.EV-820oG-a9 .

.RA75X

ST75X'

"PD7!l312GF

EVAKIT-75X

EV·75308

(Note 3)

EV-9200G-80

RA75X

ST75X

"PD75P316GF.

EVAfC~:~~0~.8-------]-··_t~po~ln~t·~----~0.~8~~~
CL = 150pf
Read Cycle

tAR

tRR--1P"'---

to RxC

Rx Data hold
from RxC
INT delay Time
from Tx Data

tRCRO
tlDl

tCY

7-11

tCY

INTAK Cycle

INT delay Time
from RxC
CTS, DCD,
SYNC high
pulse width

200

CTS, DCD,
SYNC low
pulse width

200

ns
PRI [2)

DB
PRO

External INT
from CTS,
DCD, SYNC

Recovery time
between
controls

4-6

500

ns
Nole: [1]
[2]

300

iNTA signal acts as 1ii5 signal.
iiiii and HAl signals act as Cs signal.

Write Cycle

WAIT delay
time from
Address

120

SYNC setup to
RxC

100

ns
C/D. B/i.

Nole: 1. RESET must be active for a minimum of one complete CLK
cycle.
2. In all modes system clock rate must be 4.5 times data rate.

=>b:

h------uf

DMA Cycle

DRO

--.-J

Note: [1 J Piii and HAl signal. act .s Cs lignal.

2-8

V--

WRtAWl=tww~

t-iEC

j.tPD7201A

Timing Waveforms (cont)
Transmit Data Cycle

Receive Data Cycle

Rxe

TxC

RxD

TxD

iNT

\NT

Clock

Other Timing

bL ~ tMH.=q

_ _ _~t-_---,tM",-F

Read/Write Cycle
(Software Block Transfer Mode)

Sync Pulse Generation
(External Sync Mode)

Last Bit of
Sync Character

SYNC

First Bit of

Data Character

---------------~
IRCS

Programming the MPSCC
Software operation of the MPSCC includes consistent
register organization and high-level command structure to help minimize the number of operations required to implement complex protocol designs. The
MPSCC also has extensive interrupt and status reporting capabilities to simplify programming.

The MPSCC Registers
The MPSCC interfaces to the system software with
a number of control and status registers associated
with each channel (see tables 1 and 2). Commonly used commands and status bits are accessed directly
through control and status register O. Other functions
are accessed indirectly with a register pOinter to
minimize the address space that must be dedicated
to the MPSCC.

r-------

All control and status registers except CR2 are
separately maintained for each channel. Control and
status register 2 are linked with the overall operation
of the MPSCC and have different meanings when addressed through different channels.
Before intializing the MPSCC, first program control
register 2A (2B if desired) to establish the MPSCC processor/bus interface mode. Each channel may then
be programmed for separate use beginning with control register 4 to set the protocol mode for that channel. The remaining registers may then be programmed in any order.

2-9

t-{EC

J.tPD7201A
Table 1.

Control Registers

Control
Register

Table 2.

Function

Frequently used commands and register pointer
control

Interrupt Vector
2
(Channel
B only)

Processor/bus interface control
Receiver control

4
5

Transmitter control

Sync/address character

Sync character

Mode control

Control Register 0
D7

CRC Control
Command

Command

Register Pointer [00-021
The register pointer specifies which register number
is accessed at the next control register write or status
register read. After a hardware or software reset, the
register pointer is set to zero. Therefore, the first control byte goes to control register O. When the register
pOinter is set to a value other than zero the next control or status (C/O 1) access is to the specified
register. The pointer is then reset to 0 by setting the
register pointer.

Commands [03-05]
Commands commonly used during the operation of
the MPSCC are grouped in control register O. Theyinclude the following:
Null (000] :This command has no effect and is used
only to set the register pointer or issue a CRC
command.
Send Abort (001] : When operating in the HOle mode,
this command causes the MPSCC to transmit the
HOle abort code by issuing 8 to 13 consecutive 1s.
Any data currently in the transmitter or the transmitter buffer is destroyed. After sending the abort, the
transmitter reverts to the idle phase (flags). When using the Tx byte count mode enable (Os of CR1), the
send abort command is automatically issued when
an underrun condition occurs.

2-10

Function

Buffer and "external/status" status
Received character error and special condition
status

Interrupt control

2
3

Status Registers

Status
Register

Tx byte count register, low byte

Tx byte count register, high byte

Reset External Status Interrupt [010] : When the external/status change flag is set, the condition of bits
03-07 of status register 0 are latched to capture the
short pulses that may occur. The reset external/status
interrupts command reenables the latches so that
new interrupts may be sensed.
Channel Reset (011] : This command has the same
effect on a single channel as an external reset at pin 2.
A channel reset command to channel A rests the
internal interrupt prioritization logic. This does not
occur when a channel reset command is issued to
channel B. All control registers associated with the
channel to be reset must be reinitialized. After a channel
reset, wait at least four system clock cycles before
writing new commands or controls to that channel.
Enable Interrupt on Next Character (100] : Issue this
command at any time when operating the MPSCC in
an interrupt on first received character mode. This
command must be issued at the end of a message
to reenable the interrupt logic for the next received.
character (first character of the next message).
Reset Pending Transmitter Interrupt/DMA Request
(101] : A pending transmitter buffer empty interrupt or
OMA request can be reset without sending another
character by issuing this command (typically at the
end of a message). A new transmitter buffer empty
interrupt or OMA request is not made until another
character has been loaded and transferred to the
transmitter shift register or when, if operating in
synchronous mode, the first CRC character has been
sent.
Error Reset [110l: This command resets a special
receive condition interrupt. It also reenables the parity
.and overrun error latches that allow error checking at
the end of a message.

ftt{EC

j.tPD7201A

End of Interrupt (111] (Channel A Only] : Once an interrupt request has been issued by the MPSCC, all
lower priority internal and external interrupts in the
daisy chain are held off to permit the current interrupt to be serviced while allowing higher priority interrupts to occur. At some point in the interrupt service routine (generally at the end), the end of the interrupt command must be issued to channel A to
reenable the daisy chain and allow any pending lower
priority internal interrupt requests to occur. The EOI
command must be sent to channel A for interrupts
that occured on either channel.

CRC Control Commands [06-07]
The following commands control the operation of the
CRC generator/checker logic:
Null (00] : This command has no effect and is used
when issuing other commands or setting the register
pointer.
Reset Receiver CRC Checker (01]: This command
resets the CRC checker to zero when the channel is
in a synchronous mode. It resets to all 1s when in an
HOLC mode.
Reset Transmitter CRC Generator (10] : This command
resets the CRC generator to zero when the channel
is in a synchronous mode. It resets to all 1s when in
an HOLC mode.
Reset Idle/CRC Latch (11] : This command resets the
idle/CRC latch so that when a transmitter underrun
condition occurs (transmitter has no more characters
to send), the transmitter enters the CRC phase of
operation and begins to send the 16-bit CRCcharacter
calculated up to that point. The latch is then set so
that if the underrun condition persists, idle characters
are sent following the CRC. After a hardware or software reset, the latch is in the set state. This latch is
automatically reset after the first character has been
loaded into the Tx buffer in the HOLC mode.

Control Register 1
07

Wait
Function
Enable
07

Tx Byte Wait all
Count Receive
Mode Trans·
Enable miller
DB

Receiver
Interrupt
Mode
0,

Condi- TransExt/
tion
miller Status
Affects Interrupt INT
Vector Enable Enable
02

Low Byte
07

External/Status Interrupt Enable [00]
When this bit is set to one, the MPSCC issues an interrupt whenever any of the following conditions occur:
- Transition of the OCO, CTS or SYNC input pin
Entering or leaving synchronous hunt phase,
break detection or termination
HOLC abort detection or termination
Idle/CRC latch set (CRC being sent)
After ending flag is sent in the HOLC mode

Transmitter Interrupt Enable [01]
When this bit is set to one, the MPSCC issues an
interrupt when the following conditions occur:
- A character currently in the transmitter buffer is
transferred to the shift register (transmitter buffer becomes empty), or
- The transmitter enters the idle phase and begins
transmitting sync or flag characters.
- The Tx byte count mode enable bit is set (06 of
CR1 = 1). The 7201A will automatically issue a Tx
interrupt or OMA request when the transmitter
becomes enabled (03 of CR5 = 1).

Condition Affects Vector [021
When this bit is set to zero, the fixed vector programmed in CR2B during MPSCC initialization is
returned in an interrupt acknowledge sequence. When
this bit is set to one, the vector is modified to reflect
the condition that caused the interrupt. (Programmed in channel B for both channels).

Receiver Interrupt Mode [03 - 04]
This field controls how the MPSCC interruptlDMA
logic handles the character received condition.
Receiver Interrupts/DMA Request Disabled (00] : The
MPSCC does not issue an interrupt or a OMA request
when a character has been received.
Interrupt/DMA on First Received Character Only (01] :
In this mode the MPSCC issues an interrupt only for
the first character received after an enable interrupt/OMA on first character command (CRO) has been
given. If the channel is in a OMA mode, a OMA request
is issued for each character received, including the
first. In general, use this mode whenever the MPSCC
is in a OMA or block transfer mode. This will signal
the processor that the beginning of an incoming
message has been received.

High Byte

2-11

t-{EC

jtPD7201A
Interrupt land Issue a DMA Request] on All Received
Characters 110] : In this mode an interrupt (and OMA
request if the OMA mode is selected) is issued
whenever there is a character present in the receiver
buffer. A parity error is considered a special receive
condition.
Interrupt land Issue a DMA Request] on All Received
Characters (11] : This mode is the same as the one
above, except that a parity error is not considered a
special receive condition. The following are considered special receive conditions:
Receive overrun error
Asynchronous framing error
- Parity error (if specified)
- HOLC end of message (final flag received)

Also, when using theTx byte count mode, a transmit
interrupt or OMA request will automatically become
active after issuing theTX enable command to CR5.
The Tx byte count mode can be cleared by either a
channel reset command or a hardware reset.

Wait Function Enable [07]
Setting this bit to one enables the wait function
selected by 05 of CR1.

Control Register 2 (Channel A)
07

Pin 10
SYNCBI
RTSB

Rx
INT
Mask

Priority
Interrupt Vector

DMA Mode
Select

Wait on ReceiverlTransmitter [05]
If the wait function is enabled for block mode
transfers, setting this bit to zero causes the MPSCC
to issue a wait (WAIT output goes low) when the processor attempts to write a character to the transmitter
while the transmitter buffer is full. Setting this bit to
one causes the MPSCC to issue a wait when the processor attempts to read a character from the receiver
while the receiver buffer is empty.

OMA Mode Select [Do - 01]
Setting this field determines whether channel A or B
is used in a OMA mode [data transfers are performed
by a OMA controller], or in a non-OMA mode where
transfers are performed by the processor in either a
polled, interrupt, or block transfer mode. The functions of some MPSCC pins are also controlled by this
field. See table 3.

Tx Byte Count Enable [06]

Priority [02]

Each channel has a 16-bit Tx byte count register used
for automatic transmit termination. When this bit is
set to one; the next two consecutive command cycle
writes will be to the byte count register. The first byte
is loaded into the lower 8 bits and the second to the
upper 8 bits of the byte count register. The byte.count
register holds the number of transfers to be performed
by the transmitter. A byte counter is incremented each
time a transfer is performed until the value of the byte
counter is equal to the value in the byte count register.
When equal, interrupts or OMA requests will be stopped until the byte count enable bit is issued and a new
byte count is loaded into the byte count register. If a
transmit underrun occurs in the HOLC mode, and the
byte count is not equal to the byte count register, an
abort sequence will be sent automatically.

This bit selects the relative priorities of the various
interrupt and OMA conditions according to the application requirements. Sse table 4.

Table 3_

Interrupt Vector Mode [03 - 05]
This field determines how the MPSCO responds to an
interrupt acknowledge sequence from the processor.
See table 5.

Rx INT Mask [06]
This option is generally used in the OMA modes.
Enabling this bit inhibits the interrupt from occuring
when the interruptIDMA request on first received
character mode is selected. In other words, only a
OMA request will be generated when the first
character is received.

DMA Mode Sele.ction
Pin Function

Channel

Non-DMA

WAITB

DTRB

PRI

PRO

DTRA

WAlTA

2-12

DMA

Non-DMA

DRQTxA

HAl

PRI

PRO

HAD

DRQRxA

DMA

DROTXA

HAl

DRQRxB

DRQTxB

HAD

DRQRxA

DMA

DRQTxA

DTRB

DRQRxB

DRQTxB

DTRA

DRQRxA

ftiEC
Table 4.

p.PD7201A

DMAllnterrupt Priorities
Mode

Channel A

Channel B

INT

OMA Priority
Relation

INT

OMA

INT

RxA>TxA

SRxA. RxA > SRxB. RxB > TxB > ExTA > ExTB

OMA

INT

RxA>TxA

SRxA. RxA >SRxB. RxB > TxB > ExTA> ExTB

OMA

RxA > TxA > RxB > TxB

SRxA. RxA>SRxB. RxB>TxB>ExTB

OMA

RxA>RxB> TxA>TxB

SRxA. RxA>SRxB. RxB> ExTA. ExTB

SRxA. RxA>SRxB. RxB>TxA>TxB>ExTA>ExTB

Table 5. Interrupt Acknowledge Sequence Response
Status Register 2B and Inler·
rupt Vector Bits Affected
When Condition Affects
Vector is Enabled

Mode

Nonvectored

04 030 2

Nonvectored

04 030 2

Nonvectored

02 0100

0
0

8085 Master

04 D30 2

8085 Slave

04 030 2

8086

020100

8085/8259A Slave

04 0302

Pin 10 SYNCB/RTSB Select [07]
Programming a zero into this bit selects RTSB as the
function of pin 10. A one selects SYNCB as the
function.

Control Register 2 (Channel B)

I~ I

Receiver Enable [Do]
Setting this bit to one after the channel has been completely initialized allows the receiver to begin operation. This bit may be set to zero at any time to disable
the receiver.

Sync Character Load Inhibit [01]

Illegal
0

Interrupt Priority Relation
SRxA. RxA>TxA>SRxB. RxB>TxB>ExTA>ExTB

Interrupt Vector

In the character synchronous modes, this bit inhibits
the transfer of sync characters to the receiver buffer,
thus performing a "sync·stripping" operation. When
using the MPSCC's CRC checking ability, use this
feature only to strip leading sync characters
preceding a message, since the load inhibit does not
exclude sync characters embedded in the message
from the CRC calculation. Synchronous protocols us·
ing other types of block checking such as checksum
or LRC are free to strip embedded sync characters.

Address Search Mode [021
In the HDLC mode, setting this bit places the MPSCC
in an address search mode. Character assembly does
not begin until the 8·bit character (secondary address
field) following the starting flag of a message matches
either the address programmed into CR6 or the global
address 11111111.

Interrupt Vector [Do . 071
When using the MPSCC in the vectored interrupt
mode, the contents of this register are placed on the
bus during the appropriate portion of the interrupt
acknowledge sequence. Its value is modified if status
affects vector is enabled. The value of SR2B can be
read at anytime. This feature is useful in determining
the cause of an interrupt when using the MPSCC in
a nonvectored interrupt mode.

Control Register 3
01

Number of
Received Bits
per Character

Auto
Enables

Enter
Hunt
Phase

Sync
ReCharceiver Address acter
CRC
Search
Load
Enable Mode Inhibit

Receiver CRC Enable [031

This bit enables and disables (1
enable) the CRC
checker in the character oriented protocol mode,
allowing characters from the CRC calculation to be
selectively included or excluded. The MPSCC has a
one·character delay between the receiver shift register
and the CRC checker so that the enabling or disabl·
ing takes affect with the last character transferred
from the shift register to the receiver buffer. Therefore,
there is one full character time in which to read the
character and decide whether or not it should be
included in the CRC calculation. In the HDLC mode,
there is no 8·bit delay.

Receiver
Enable

2-13

JLPD7201A
Enter Hunt Phase [041

Parity Even/Odd [01)

Although the MPSCC receiver automatically enters
the sync hunt phase after a reset, there are other
times when reentry is appropriate. This may occur
when synchronization has been lost or, in an HOLC
mode, to ignore the current incoming message. A one
in this bit position at any time after initialization
causes the MPSCC to reeneter the hunt phase.

Programming a zero into this bit when parity is enabled selects odd parity for the received character.
Conversely, a one in this bit selects even parity
generation and checking.

Number of Stop Bits or Sync Mode [02 • OaJ

Setting this bit to one causes the OCO and CTS inputs to act as enable inputs to the receiver and
transmitter, respectively.

This field specifies whether the channel is used in a
synchronous or an asynchronous mode. In an asynchronous mode, this field also specifies the number of
bit times used as the stop bit length by the transmitter. The receiver always checks for one stop bit.
See table 7.

Number of Received Bits per Character [06 • 07)

Sync Mode [04 . 05)

This field specifies the number of data bits assembled
to make each character. The value may be changed
while a character is being assembled and, if the
change is made before the new nl,lmber of bits has
been reached, it affects that character. Otherwise, the
new specifications take effect on the next character
received. See table 6.

When the stop bits/sync mode field is programmed
for synchronous modes (02, 03 = 00), this field
specifies the particular synchronous format to be
used. This field is ignored in an asynchronous mode.
See table 8.

Control Register 4

This field specifies the relationship between the
transmitter and receiver clock inputs (TxC, RxC) and
the actual data rates at TxO and RxO. When operating
in a synchronous mode, a 1x clock rate must be
specified. In asynchronous modes, any of the rates
may be specified. However, with a 1x clock rate, the
receiver cannot determine the center of the start bit.
In this mode, the sampling (rising) edge of Rxe must
be externally synchronized with the data. See table 9.

Auto Enables [05]

Clock Rate

Sync Mode

Number
of Stop Bits
per Sync Mode

Parity
Even/
Odd

Parity
Enable

Parity Enable [001
Setting this bit to one adds an extra data bit containing parity information to each transmitted character.
Each received character is expected to contain this
extra bit, and the receiver parity checker is enabled.

Table 6.

Received Bits per Character

Clock Rate [06 • 07)

Table 8_

Synchronous Formats

Sync
Mode 1
05

Sync
Mode 2

a-bit internal synchronization character
(monosync)

Blls per Characler

o
o

16-bit internal synchronization character
(bisync)

Stop Bits

Table 9.
Mode

Synchronous modes
Asynchronous 1 bit time (1 stop bit)
Asynchronous 1'12 bit times (1';' stop bits)
Asynchronous 2 bit times (2 stop bits)

SOLC/HOLC
External synchronization (SYNC pin becomes an
input)

Table 7.

Mode

Clock Rates

Clock
Rate 1
07

Clock
Rale 2
0&

Clock Rale

Clock Rate
Clock Rate

0
0

Clock Rate
Clock Rate

2-14

= Ix Data Rate
= 16x Data Rate
= 32x Data Rate
= 64x Data Rate

t-fEC

jLPD7201A

Control Register 5
07

OTR

Number of
Transmitted Bits
per Character

Send
Break

Trans·
mitter
Enable

CRC
Poly·
nomial
Select

RTS

Trans·
mitter
CRC
Enable

Transmitter CRC Enable [Do]
A one or a zero enables or disables (respectively) the
CRC generator calculation. The enable or disable
does not, take effect until the next character is
transferred from the transmitter buffer to the shift
register, thus allowing specific characters to be in·
cluded or excluded from the CRC calculation. By set·
ting or resetting this bit just before loading the next
character, it and subsequent characters are included
or excluded from the calculation. If this bit is zero
when the transmitter becomes empty, the MPSCC
goes to the idle phase regardless of the state of the
idle/CRC latch.

RTS [01]
In synchronous and HDLC modes, setting this bit to
one causes the RTS pin to go low, while a zero causes
it to go high. In an asynchronous mode, setting this
bit to zero causes the RTS pin to go high when the
transmitter is completely empty. This feature
facilitates programming the MPSCC for use with asyn·
chronous modems.

CRC Polynomial Select [02]
This bit selects the polynomial used by the transmitter
and receiver for CRC generation and checking. A one
selects the CRC·16 polynomial (X16 + X15 + X2 + 1).
A zero selects the CRC·CCITT polynomial (X16 + X12
+ X5 + 1). In an HDLC mode CRC·CCITT must be
selected. Either polynomial may be used in other syn·
chronous modes.

line is zero·inserted. That is, the line goes low for one
bit time out of every five.
Never disable the transmitter during the HDLC data
phase unless a reset follows immediately. In either
case, any character in the buffer register is held.
Disabling the transmitter during the CRC phase
causes the remainder of the CRC character to be bit·
substituted with the sync (or flag). The total number
of bits transmitted is correct and TxD goes high after
they are sent.
If the transmitter is disabled during the idle phase, the
remainder of the sync (flag) character is sent. TxD then
goes high.

Send Break [041
Setting this bit to one immediately forces the
transmitter output (TxD) low (spacing). This function
overrides the normal transmitter output and destroys
any data being transmitted, although the transmitter
is still in operation. Resetting this bit releases the
transmitter output.

Transmitted Bits per Character [05 . Os]
This field controls the number of data bits transmitted
in each character. The number of bits per character
may be changed by rewriting this field just before the
first character is loaded. See table 10.
Normally each character is sent to the MPSCC right·
justified and the unused bits are ignored. However,
when sending five bits or less, the data should be for·
matted as shown below to inform the MPSCC of the
precise number of bits to be sent. See table 11.

Table 10.

ll'ansmltled
Bits per
Character
05

o
o

Transmitter Enable [03]
After a reset, the transmitted data output (TxD) is held
high (marking) and the transmitter is disabled until
this bit is set.
In an asynchronous mode TxD remains high until data
is loaded for transmission.
When the transmitter is disabled in an asynchronous
mode, any character currently being sent is completed
before TxD returns to the marking state.
If the transmitter is disabled during the data phase
in a synchronous mode, the current character is sent.
TxD then goes high (marking). In an HDLC mode, the
current character is sent, but the following marking

1i'ansmitted Bits per Character

'D'ansmitled
Bits per
Character 1
Os

Bits per Character

5 or less (see below)

6
8

Table 11.
07

Transmitted Bits per Character for 5
Characters or Less

0
0

Number of Bils per Charaler

0
0
0

0
0

2
3

2-15

t-lEC

J.tPD7201A
OTR [Data Terminal Ready] [07]
When this bit is one, the OTR output is low [active].
When this bit is zero, OTR is high.

Control Register 6
DO

Sync Byte 1 [Do • 07]
Sync byte 1 is used in the following modes:
Monosync

B·bit sync character transmitted
during the idle phase
Bisync
Least significant (first) B bits of the
16·bit transmit and receive sync
character
External Sync Sync character transmitted during the
idle phase
HOLC
Secondary address value matched to
secondary address field of the HOLC
frame when the MPSCC is in the address search mode

Control Register 7

I~ I~ I~ I

HOLC

B-bit sync character matched by the
receiver
Most significant (second) B bits of
the 16-bit transmit and receive sync
characters
The flag character 01111110 must be
programmed into control register 7
for flag matching by the MPSCC
receiver

Status Register 0
07

Break/
Abort

Idle/
CRC

CTS

Sync
Status

DCD

Tx
Buffer
Empty

INT
Pend·
ing

Rec'd
Char
Available

Received Character Available [Do]
When this bit is set, it indicates that one or more
characters in the receiver buffer are available for the
processor to read. Once the processor has read all
2-16

It is not necessary to read the status registers of both
channels to determine if an interrupt is pending. If the
status affects vector is enabled and the interrupt
pending is set, the vector read from SR2 contains
valid condition information.
In a vectored interrupt mode, interrupt pending is set
during the interrupt acknowledge cycle (on the
leading edge of the second INTAK pulse) when the
MPSCC is the highest priority device requesting interrupt service (PRI is active). In either mode, if there
are no other pending interrupt requests, interrupt pending is reset when the end of the interrupt cpmmand
is issued.

Transmitter Buffer Empty [02]

Sync byte 2 is used in the fo!!o'l/ing mod as:

Bisync

Interrupt Pending [01 • Channel A Only]
The interrupt pending bit is used with the interrupt
vector register (status register 2) to make it easier to
determine the MPSCC's interrupt status. This is
useful in a nonvectored interrupt mode where the processor must poll each device to determine the interrupt source. In this mode, interrupt pending is set
when status register 28 is read, the PRI input is active
(low), and the MPSCC requests interrupt service.

Sync Byte 2

Sync Byte 2 [Do • 07]
Monosync

the available characters, the MPSCC resets this bit
until a new character is received.

This bit is set whenever the transmitter buffer is
empty - except during the transmission of CRC. The
~..~PSCC uses the buffei to facilitate this function.
After a reset, the buffer is considered empty and
transmit buffer empty is set.

External/Status Flags [03 . 07]
The following status bits reflect the state of the
various conditions that cause an external/status interrupt. The MPSCC latches all external/status bits
whenever a change occurs that would cause an
external/status interrupt, regardless of whether this
interrupt is enabled. This allows transient status
changes on these lines to be saved.
When operating the MPSCC in an interrupt-driven
mode for external/status interrupts, read status
register 0 when this interrupt occurs and issue a reset
external/status interrupt command to reenable the
interrupt and the latches. To poll these bits without
interrupts, issue the reset external/status interrupt
command to first update the status to reflect the current values.

t-fEC
OCO 1031: This bit reflects the inverted state of the
OCO input. When OCO is low the OCO status bit is
high. Any transition on this bit causes an external/
status interrupt request.
Sync Status 1041 : The meaning of this bit depends on
the operating mode of the MPSCC.
Asynchronous mode: Sync status reflects the inverted
state of the SYNC input. When SYNC is low, sync
status is high. Any transition on this bit causes an
external/status interrupt request.
External synchronization mode: Sync status operates
in the same manner as in asynchronous mode. The
MPSCC's receiver synchronization logic is also tied
to the sync status bit in an external synchronization
mode. A low-to-high transition (SYNC input going low)
informs the receiver that synchronization has started
and character assembly begins.
A low-to-high transition on the SYNC input indicates
that synchronization has been lost. The sync status
becomes zero and an external/status is generated.
The receiver remains in the receive data phase until
the enter hunt phase bit in control register 3 is set.
Monosync, bisync, HOLC modes: In these modes, sync
status indicates whether the MPSCC receiver is in the
sync hunt or receive data phase of operation. A zero
indicates that the MPSCC is in the receive data phase,
and a one indicates that the MPSCC is in the sync
hunt phase (as in after a reset or when the enter sync
hunt bit sets to 1). As in the other modes, a transition
on this bit causes an external/status interrupt. Note
that entering a sync hunt phase (when programmed)
or a reset causes an external/status interrupt request
which may be cleared immediately with a reset external/status interrupt command.
CTS 10sJ : This bit reflects the inverted state of the
CTS input. When CTS is low, the CTS status bit is
high. Any transition on this bit causes an external/
status interrupt request.
Idle/CRC 10sl (Tx Underrun/EOMJ : This bit indicates
the state of the idle/CRC latch used in the synchronous mode. After a hardware reset, this bit is set
to one, indicating that the transmitter is completely
empty. When the MPSCC enters idle phase, it
automatically transmits sync or flag characters.
In the HOLC mode, the MPSCC automatically resets
this latch after the first byte of a frame is written to
the Tx buffer.

jLPD7201A
When the transmitter is completely empty, the
M PSCC sends the 16-bit CRC character and sets the
latch again. An external/status interrupt is issued
when the latch is set, indicating that CRC is being
sent. No interrupt is issued when the latch is reset.
Break/Abort 101J : In the asynchronous mode, this bit
indicates the detection of a break sequence (a null
character plus framing error that occurs when the RxO
input is held low, spacing, for more than one
character time). Break/abort is reset when RxO returns
high (marking).
In the HOLC mode, break/abort indicates the detection of an abort sequence when seven or more ones
are received in sequence. It is reset when a zero is
received.
Any transition of the break/abort bit causes an external/status interrupt.

Status Register 1
D7

End of
CRC
SOLC Framing
Frame
Error

Over·
run
Error

Parity
Error

SOLe Residue Code

All
Sent

All Sent [Dol
This bit is set when the transmitter is empty and reset
when a character is present in the transmitter buffer
or shift register. This feature simplifies the mode control software routines. In the bit synchronous mode,
this bit sets when the ending flag pattern is sent.

Residue Code [01 - OaJ
Since the data portion of an HOLC message can consist of any number of bits and not necessarily an
integral number of characters, the MPSCC has special
logiC to determine and report when the end of frame
flag has been received (that is, the boundary between
the data field and the CRC character in the last few
data characters that were just read).
When the end of frame condition is indicated (07 of
status register 1 = 1) and there is a special receive
condition interrupt (if enabled), the last bits of the
CRC character are in the receiver buffer. The residue
code for the frame is valid in the status register 1 byte
associated with that data character. (SR1 tracks the
received data in its own buffer).
The meaning of the residue code depends upon the
number of bits per character specified for the receiver.
The previous character refers to the last character
read before the end of frame, and so on. See table 12.
2-17

ttlEC

/LPD7201A
Tab/e 12.

Residue Codes
B Bits per Character

°2

°1

0
0

1
0

0
0

Previous
Character

2nd Previous
Character

CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCC
C C C C C C C C*
CCCCCCCD
CCCCCCDD

CCCCCDDD
CCCCDDDD
CCCDDDDD
CCDDDDDD
CDDDDDDD
DDDDDDDD*
DDDDDDDD
DDDDDDDD

7 Bits per Character
03

°1

0
1

0
0

Previous
Character

2nd Previous
Character

CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCC
C C C C C C C*
CCCCCCD

CCCCCDD
CCCCDDD
CCCDDDD
CCDDDDD
CDDDDDD
DDDDDDD*
DDDDDDD

6 Bits per Character
03

°1

0
1

Previous
Character

2nd Previous

CCCCCC
CCCCCC
cceece
CCCCCC
CCCCCC
cecccc

CCCCCD
CCCCCD
CCCOOO
CCDDDD
CDDDDD
DDDDDD

5 Bits per Character
Previous

°2

°1

Character

C C e C C*
ceCCD
CCCDD
CCDDD
CDDDD

2nd Previous

D DDDD*
DDDDD
DDD DD
D DDDD
DDDDD

= CRC bit
= Valid data
• = No residue

Notes: C
D

Special Receive Condition Flags
The status bits described below-parity error (if parity
as a special receive condition is enabled), receiver overrun error, CRC/framing error, and end of HOLC frameall represent special receive conditions.

2-18

When any of these conditions occur and interrupts
are enabled, the MPSCC issues an interrupt request.
In addition, if a condition affect vector mode is en.
abled, the vector generated (and the contents of SR2B
for nonvectored interrupts) is different from that of a
received character available condition. Therefore, it
is not necessary to analyze SR1 with each character
to determine if an error has occurred.
Also, the parity error and receiver overrun error flags
are latched. That is, once one of these errors occurs,
the flag remains set for all subsequent characters
until reset by the error reset command. Therefore read
SR1 only at the end of a message to determine if
either of these errors occurred anywhere in the
message. The other flags are not latched and follow
each character available in the receiver buffer.
Parity Error [Od: This bit is set and latched when
parity is enabled and the received parity bit does not
match the sense (odd or even) calculated from the
data bits.
Receiver Overrun Error [051 : This error occurs and is
latched when the receiver buffer already contains
three characters and a fourth character is completely
received, overwriting the last character in the buffer.
CRC/Framing Error [Osl : In the asynchronous mode
a framing error is flagged (but not latched) when no
stop bit is detected at the end of a character (RxO is
low one bit time after the center of the last data or
parity bit). When this condition occurs, the MPSCC
waits an additional one·half bit time before sampling
again so that the framing error is not interpreted as
a new start bit.
In the synchronous mode, this bit indicates the result
of the comparison between the current CRC result and
the appropriate check value. It is usually set to one,
since a message rarely indicates a correct CRC result
until correctly completed with the CRC check character.
Note that a CRC error does not result in a special
receive condition interrupt.
End of HOLC Frame [EOF] [071: This status bit is used
only in the bit synchronous mode to indicate that the
end of frame flag has been received and that the CRC
error flag and residue code are valid. This flag can be
reset at any time by issuing an error reset command.
The MPSCC also automatically resets this bit when the
first character of the next message is sent.

!\fEe

ItPD7201A

Status Register 2B

Table 13.
0,

Interrupt Vector

Interrupt
Pending

Condition Affects Vector Modifications
8085 Modes

8086 Modes

(SKO.O,

Channel AI

Interrupt Vector [Do - 07 - Channel B Only]

Reading status register 2B returns the interrupt vector
that is programmed into control register 2B. If a condition affects vector mode is enabled, the value of the
vector is modified as shown in table 13.

Code 111 can mean either channel A special receive
condition or no interrupt pending. Examine the interrupt pending bit (D1 of status register 0, channel A),
to distinguish which it means. In a nonvectored interrupt mode, the vector register must be read first for
the interrupt pending to be valid.

Condition

No interrupt pending

Channel B transmitter
buffer empty

Channel B external/status
Change

Channel B received
character available

Channel B special receive
condition
0

Channel A transmitter
buffer empty

Channel A external/status
change
Channel A received
Character available
Channel A special receive
condition

Status Register Bit Functions (Sheet 1 of 2)
Control Register 2 (Channel BI

Control Register 0

Pointer for
the Selection of
a Read/Write
Register

v,
vo }

l_Jl==~~~~~~~~~~~~V2

V3
V4

Interrupt
Vector

-V5
V6
V7

Null Code
Send Abort (H DLC)
Reset EXT/Status Interrupts

Control Register 2 (Channel AI

Channel Reset
Enable INT on Next Ax Character
Reset Tx INTfDMA Pending
Error Reset
End of Interrupt (EOI - Channel A only)
Null Code
Reset Rx CAe Checker
Reset Tx CRe Generator
Reset Tx Underrun/EOM Latch

l
I

o
1

~ ~~:~~:!~ ~=: ~ ~~~ ~ ~:: ~

o
o

Control Register 1

Both Channels Interrupt
Channel A DMA, Channel B INT
BothChannelsDMA-lnternal PflofityMode
BothChannels DMA-External PnontyMode

1
1

0
1
0
1

i::

8085 Master Mode
8085 Slave Mode
8086/88 Mode
8085/8259A Slave Mode

- Interrupt Vectored/Nonvectored
Receive Interrupt Mask

~--

EXT INT Enable
Tx INT Enable
~ - - - Status Affects Vector
(Channel B only)

Rx INT and DMA Disable }
Rx INT on First Character
INT on All Rx Characters
(Parity Affects Vector)
INT on All Rx Characters
(Parity Does Not Affect
Vector)
Wait on Receiver/Transmitter
- Tx Byte Count Enable
L - - - - - W a i t Enable

RTSBPin 10
SYNCB Pin 10

Control Register 3
OR Interrupt on
Special Receive
Condition
Rx Enable
Sync Character Load Inhibit
" - - - - - Address Search Mode (HOle)
" - - - - - - - - Ax CRC Enable

_-'=========

Enter
Hunt Phase
Auto Enables

Rx5 Bits/Character
Ax7 Bits/Character
Rx6 Bits/Character
Rx8 Bits/Character

2-19

ttiEC

JLPD7201A
Status Register Bit Functions (Sheet 2 of 2)
Control Register 4

Status Register 1

I~I~I~I~I~I~I~I~I

I L

Parity Enable
o Parity = Odd
1 Parity
Even
Sync Modes Enable
1 Stop Bit/Character
l1f2 Stop Bits/Character
2 Stop Bits/Character

1o 0 0

B-bit Sync Character

16-bit Sync Character

SOLe Mode (0111111 0 Flag)
External Sync Mode
XI Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode

L
o

1
0
1

1
0
0
1

0
1
1
1

I-Fiel
Bits i
Previous
Byt

I·Field
Bits in
Second
Previous
6yte

3}
4

0
0
0
0

5
6
7
8

Parity Error

'~g,~~~~~n~r~~~r
L_-'==="---------===~End
of Frame (SOLe)

Control Register 5

All Sent - Used with External/Status
Interrupt Mode

Residue Data tor
Eight Rx Bits per
Character
Programmed

}

[lJ

Status Register 2B

Tx CRe Enable
RTS

Tx Enable
L_~=~====CRC-16ICRC-CCITT
Send Break
Tx5 Bits (or Less)/Character
Tx7 Bits/Character
ne6 Bits/Character
Tx8 Bits/Character

L--'=====

OTR

~ml} Inler upl

L_ - ' = = = = = = = = = = V4[2]
V5

Vector

L~==========V6
V7

Control Register 6

Note:

SyncBitO
Sync Bit 1

' - - - - - - S y n c Bit2

I
l~ync6"4
l_1=~=b~~~~~~~~sYnCB't3
~

Sync BitS
Sync BitS
Sync Bit 7

[1] Used with special receive condition mode.

{2] Variable If Status Affects Vector is programmed.

AlsoSOLC
Address Field

S1a1us Ragistsi 3
(Tx Byte Count Register)

Bit 0
Bit 1
'-----6iI2

Control Register 7

_-====== ~~~~::::

Sync
Sync Bit
Bit 10
11

l_1=~=~~~~~~~~~sYnc

Sync
Sync
Sync

}

_-,========Bit

Bit 34

Low

Byte

it 5
L_ - , = = = = = = = = = = = = BBit6
---------------6iI7

[1]

Bit 13
Bit 12
Bit
14
Bit 15

Status Register 4
(Tx Byte Count Register)

Note:
[1) ForSDLC it must be programmed to 01111110 for flag recognition.

Bit 8
Bit9

10
L_-,======Bit
Bitll
12
L_-,=========:::Bit
Bit 13

Status Register 0

i t 15
14
L_ - , = = = = = = = = = = = = = BBit
Rx Character Available
INT Pending (Channel A Only)

l_l=~=~~~~~~~~~~~=~·=t~~-~~~:::::mpty

CTS
}
Tx UnderrunfEOM
BreakfAbort

2-20

Extemal/Status
Used with
Interrupt Mode

High
Byte

NEe
NEe Electronics Inc.
Description
TheJlPD72001 advanced multiprotocol serial controller
(AMPSC) is a high-performance, single-chip, serial
communications controller designed to meet a wide
variety of communications requirements. The AMPSC
contains two independent full-duplex channels which
can be configured to transmit and receive data in either
asynchronous protocol or one of two synchronous
protocols: character-oriented protocol (COP) or bitoriented protocol (BOP). The COP and BOP synchronous protocols include cyclic redundancy check
(CRC) generation and checking.
The AMPSC has several interrupt modes, including
vectored and nonvectored. Separate direct memory
access (DMA) requests are available for the transmitter
and receiver on each channel, allowing high speed
operation. The AMPSC is easily interfaced to most
microprocessors with a minimum of logic.
The JlPD72001 AMPSC is an upgraded CMOS version
of the JlPD7201A MPSCC with the following additions:
four internal baud rate generator (BRG)/timers, two
digital phase-locked loops (DPLL), two crystal oscillators, and the capability of synchronous data link
control (SDLC) loop operation. The BRG's can be used
as independent timers, when they are not being used
as baud rate generators. Each timer generates its own
zero count interrupt. These features simplify design
requirements and at the same time enhance the flexible
architecture of the JlPD7201A.

Features
D
D
D
D

D
D

D
D
D
D

Advanced version of the JlPD7201 A
Functional superset of industry standard 8530
CMOS technology
Multiprotocol
- Asynchronous
- Synchronous
- Character-oriented (BISYNC/MONO-SYNC)
-.Bit-oriented (SDLC/HDLC)
Two independent full-duplex channels
Versatile host-system interface
- Software polling
- Interrupt
-DMA
I nterface to a majority of microprocessors (V-Series,
8080, 8085, 80X86/88, and others)
DC to 2.2-Mb/s data rate
Modem control signals
NRZ, NRZI, and Frill encoding/decoding, Manchester
decoding

pPD72001
CMOS, Advanced Multiprotocol,
Serial Communications
Controller

D Digital phase-locked loop per channel
D Two baud rate generator/timers per channel (receive
and transmit)
D Crystal oscillator per channel
D Loopback test mode
D SDLC loop mode
D Mark idle detection
D Short frame detection
D Single +5 V power supply
D Standby mode for reduced power consumption
D Two speed versions: 8 MHz and 11 MHz systems
and input data clocks
D Available in DIP, PLCC, and quadflat packages

Ordering Information
ParI No.

Package Type

Max Clock
Speed

pPD72001C

4O-pin plastic DIP

8 MHz

pPD72001 C-11

40-pin plastic DIP

11 MHz

pPD72001 GC-386

52-pin plastic miniflat

8 MHz

pPD72001 GC-386-11

52-pin plastic

11 MHz

pPD72001L

52-pin plastic
leaded chip carrier (PLCC)

8 MHz

pPD72001 L-11

52-pin plastic leaded
chip carrier (PLCC)

11 MHz

Pin Configurations
40-Pin Plastic DIP
DCDA

CTSA

RxDA

XI1A/STRxCA

XI2A/SYNCA

TRxCA

TdM
RTSA

D,
Do

DRQRxA
9

RESET

GND

ClK

VDD

DRQTxA

C/O

BfA:

DTRA/DRQTxB
DTRB/DRQRxB

PRO

RTSB

PRI

TxDB

INTAK
INT

XI2B/SYNCB
XI1 B/STRxCB

CTSB

RxDB

DC DB

TRxCB
83-004274A

2-21
NECEL-000501

pPD72001
Pin Configurations (cont)

Pin Identification
Symbol

Function

B/A

'" '"

Channel B or channel A select input from host
computer

C/O

Control/data input select from host computer

~ ~ ~
I-

ClK

System clock input from host computer

CTSA

Clear-to-send input for channel A

CTSB

Clear-to-send input for channel B

RTSB

DCDA

Data carrier detect input for channel A

TxOB

DCDB

Data carrier detect input for channel B

DTRA/DRQTxB

Data terminal ready output for channel A or DMA
request output for transmit channel B; determined by
control register CR2A

DTRB/DRQRxB

Data terminal ready output for channel B or DMA
request output for receive channel B; determined by
control register CR2A

DRQRxA

DMA request output for receive channel A

52-Pin Plastic Miniflat
)(

ool~
Z

)( ,l-w

oa:a:
Q

)(

I- a:
00
~

ceO I~ I~ 0 0
w ..I cca:t-ta: 0 > > c c c z z
(J)

.... ...... .... ..'" ... .,... ... .....
:;:

TxOA
TRxCA
XI2A1SYNCA

XI2B/SYNCB

XI1 AlffiiiCA

XI1 B/STRxCB

RxOA

RxDB

CTSA

TRxCB

OCOA

DCDB

CTSB

06
D5

INT

PRI

PRO

INTAK

83-004272A

NC
GND

GND
WR

AD
C/O

B/A
NC

Interrupt acknowledge input from host computer

PRI

Priority input, interrupt daisy chain control

PRO

Priority output, interrupt daisy chain control

Read control input from host computer

RESET

System reset input from host computer

RTSA

Request-to-send output for channel A

RTSB

Request-to-send output for channel _B_ _ _ _ __

RxDA

Receive data input for channel A
Receive data input for channel B
Transmit-receive clock input for channel A

RTSA

TRxCB

Transmit-receive clock input for channel B

DRQRxA

TxDA

Transmit data output for channel A

TxDB

Transmit data .output for channnel B

Write control input from host computer

Voo
Voo

XI1A/STRxCA

DRQTxA
DTRAlDRQTxB

External crystal connection for channel A or transmitreceive clock source input for channel A

XI2A/SYNCA

NC
DTRB/DRQRxB

External crystal connection for channel A or
synchronization input for channel A

XI1 B/STRxCB

External crystal connection for channel B or transmitreceive clock source input for channel B

XI2B/SYNCB

External crystal connection for channel B or
synchronization input for channel B

RESET
ClK

')("I'l-"

I-

en
a:

83-Q04273A

2-22

Interrupt request output to host computer

INTAK

TRxCA

INT

RxDB
NC

DMA request output for transmit channel A
System data bus

:!~~~~~~~~~ct~~

DRQTxA

GND

System ground

Voo

+5 V (typical)

t-iEC
Pin Functions
CPU Interface
B/A [Channel Select]. The input to this pin selects the
channel to be accessed for a write or read operation. A
low input selects channel A; a high input selects
channel B.

pPD72001
RD [Read]. The active-low RO input signal causes
status or receive (Rx) data to be read out of the
AMPSC. The data is presented on pins 00-07' The
values are dependent on the state of the B/A and
inputs and the internal state of the device.

cio

C/D [Control/Data Select]. The inputtothis pin selects
the type of data on the data bus during a write or read
access. A low input selects data; a high input selects a
control or status register.

WR [Write]. The active-low WR input signal causes
control words or transmit (Tx) data to be written into
the AMPSC, The data written is input on pins 00-07
(data bus). The destination of the data is determined by
the state of the B/A and C/O pins and the value of the
internal register pointer.

ClK [System Clock]. This input supplies the clock for
the internal operation of the device. It is separate from
the data clocks. The system clock input must be more
than five times the serial data transfer rate.

07-00 [Data Bus]. These pins constitute a three-state,
8-bit, bidirectional data bus. The bus is connected to
the host processor's data bus to transfer control words,
status information, and send/receive data.

INT [Interrupt]. The interrupt request output signal at
this pin,goes low if an interrupt cause occurs within the
AMPSC. The output is an open-drain transistor and
requires a pull-up resistor.

RxDA, RxDB [Receive Data]. Receive data enters the
AMPSC on these pins.

INTAK [Interrupt Acknowledge]. An active-low input
signal at this pin is used in response to an interrupt
request. In the Vector mode (CR2A bit 07 = 1), it
causes the interrupt vector to be placed on the data
bus. The output vector mode determines the number of
cycles of INTAK toggling that are required for each
interrupt I!cknowledge cycle (see CR2A bits 03-05). In
the Nonvector mode (07 = 0), this pin must be pulled
high. If unused, this pin must also be pulled high.
PRI [Priority Input]. The PRI signal controls interrupt
,request generation and interrupt vector output. The
pin is the input forthe interrupt priority daisy chain that
determines how interrupts from multiple devices are
resolved. A high level prevents the AMPSC from
presenting an interrupt vector during the INTAK
sequence. A low level allows the vector to be presented.
If unused, this pin must be tied low.
PRO [Priority Output]. This is an output to the interrupt
priority daisy chain. It controls interrupt requests from
lower-priority devices. It indicates the existence of a
higher-priority interrupt, either within the AMPSC or, if
no internal interrupt exists, the condition of the PRI
input.
RESET [Reset]. Applying a low signal continuously for
two or more clock cycles (tCYK) to this pin resets the
AMPSC (system reset) and places it in Standby mode.
A system reset disables the transmitter, receiver, interrupt, and OMA functions and sets the TxO and
general-purpose output pins to high. It also resets all
bits of the control registers.

Channel Interface

TxDA, TxDB [Transmit Data]. Transmit data exits the
AMPSC on these pins.
DRQTxA, DRQTxB [DMA Transmit Requests]. These
active-high outputs for channels A and Bare OMA
requests to the OMA controller. The pin is set to high
when the Tx buffer is emptied. The conditions under
which this occurs depend on the status of control
register CR1 bit 02. (ORQTxB and OTRA are dual
functions of the same pin.)
DRQRxA, DRQRxB [DMA Receive Requests]. These
active-high outputs for channels A and Bare OMA
requests to the OMA controller. The pin is set to high
when the receiver enters the Rx Character Available
state. It is reset when received data is read out of the
channel. (ORQRxB and OTRB are dual functions of the
same pin.)
TRxCA, TRxCB [Transmit/Receive ClOCk]. If bit 02 of
control register CR15 is zero, these pins are transmit or
receive clock inputs. Also, they are inputs if bits 05 and
06 or 03 and 04 are set to one and zero, respectively,
overriding the state of bit 02.
If none of the conditions above are true, the pins
function as outputs with the source selectable between
the crystal oscillator, the BRG, the OPLL, and the
transmit clock. ~election is made with bits DO and 01 of
CR15.
STRxCA, STRxCB [Clock Source]. These pins are the
transmit or receive clock source inputs for channels A
and B, respectively. They can be routed internally to
the transmitter, receiver, BRG's, or OPLL. An alternative
function as an external crystal connection point (XI) is
selected by control register CR15 bit 07.
2-23

NEe

pPD72001
XI1A, XI2A and XI1B, XI2B [Crystal Connections].
These two pin pairs may be connected to external
crystals that control the internal oscillators for channels
A and B, respectively. (See STRxCA and STRxCB.)
Modem Control
RTSA, RTSB [Request to Send]. These are generalpurpose outputs usable, as an example, for modem
control. Pin status is set by CRS bit 01 and Auto Enable
bit status (CR3 bit OS).
CTSA, CTSB [Clear to Send]. These are generalpurpose inputs usable, as an example, for modem
control. A status change on CTSA or CTSB affects E/S
bit latch operation. If E/S INT is enabled (CR1 bit DO set
to 1), an E/S interrupt occurs. If the Auto Enable mode
is selected (CR3 bit OS set to 1), CTSA and CTSB can
be used with the Tx Enable bit (CRS bit 03) to control
transmitter operation.

Crystal Recommendations
The crystals used with the pP072001 internal crystal
oscillators should be parallel resonant, fundamental
mode, with an AT cut. For frequency stability, two
capacitors can be added from the pins of the crystal to
ground (figure 1). The value of the capacitors can be
calculated by the following formula:
C
L

C1
C1

+ C2

SYNCA, SYNCB [Sync Input or Output]. In accordance
with the settings of control regsister CR4 bits 07-02,
and with CR1S bit 07 = 0, the three functions of these
pins are as follows.
(1) Asynchronous mode: general-purpose input that
functions like OCO and CTS.
(2) External sync mode: active-low input indicates to
the AMPSC that synchronization has occurred,
(3) Internal sync mode: active-low output indicates
when synchronization is detected by the AMPSC.

2-24

CL is the load capacitance of the crystal and Cs is all
stray capacitance in parallel with the crystal. The Cs
value should include the input capacitance (CIO and
CIN) of the pP072001 and any wiring or socket
capacitance.
Figure 1.

Crystal Configuration Circuit

DCDA, DC DB [Data Carrier Detect]. These are generalpurpose inputs usable, as an example, for modem
control. A status change on OCOA or OCOB affects
E/S bit latch operation. If E/S INT is enabled (CR1 bit
DO set to 1), an E/S interrupt occurs. If the Auto Enable
mode is selected (CR3 bit OS set to 1), OCOA and
OCOB can be used with the Rx Enable bit (CR3 bit ~O)
to control receiver operation.
DTRA, DTRB [Data Terminal Ready]. These are
general-purpose active-low outputs controlled by
control register CRSA bit 07. (ORQTxB and ORQRxB
have dual pin functions with OTRA and OTRB.)

,..---.----1 Xll
IlP D72001
XI2

83,-005111 A

Absolute Maximum

Rating~

TA =+25·C

Power supply voltage, Voo

-0.5 to +70 V

!nput vo!tage, Vi

-0.5 to VDn

Output voltage, Va

-0.5 to Voo

Operating temperature, TaPT
Storage temperature, TSTG

+ 0. 5 V
+ 0.5 V

-10 to +lO·C
-65 to +150·C

t-IEC

pPD72001

DC Characteristics
TA

=-10 to +70·C; V DD = + 5 V ±10%
Limits

Parameter

Symbol

Min

VIL

-0.5

Input low voltage
Input high voltage

Typ

Max

Unit

+0.8

Test Conditions
All pins except ClK

VILC

-0.5

+0.6

ClK pin

VIH

+2.2

Voo + 0.5

All pins except ClK

VIHC

+3.3

Voo + 0.5

ClK pin

+0.45

10L = 2.0 mA

+10

JlA

VOUT = Voo

Output low voltage

VOL

Output high voltage

VOH

Output leakage current, high

ILOH

0.7 Voo

10H = -400JlA

Output leakage current, low

ILOL

-10

JlA

VOUT = V

Input leakage current, high

ILiH

+10

JlA

VIN = Voo

-10

JlA

VIN

All outputs at high level; tCY = 0.125 JlS

JlA

fRxC

Standby mode

Input leakage current, low

ILiL

Voo supply current

100

Standby current

IDOl

=0 V
= fTxC = fCLK = DC

Capacitance
TA =

25·C; VDD = 0 V
Limits

Parameter

Symbol

Min

Max

Unit

Input capacitance

110 capacitance

pF
pF

Test Conditions
fC = 1 MHz; unmeasured pins returned to

av.

AC Characteristics
TA

= -10 to +70·C; VDD = +5 V ±10%
Limits, B MHz

Parameter

Symbol

Min

Max

tCYK

125

tWKH

tWKL

Limits, 11 MHz
Min

Max

Unit

Test Conditions

2000

1000

tKR

1.5 to 3.0 V

tKF

3.0 to 1.5 V

Clock
Clock cycle (Note 1)
Clock high level width
Clock low-level width
Clock rise time
Clock fall time
Notes:

(1) In all modes, the system clock frequency must be more than five
times the maximum data rate.

2-25

NEe

pPD72001
AC Characteristics (cont)
limits, 11 MHz

limits, 8 MHz
Parameter

Symbol

Min

Max

Min

Max

Unit

Test Conditions

Read Cycle
Address setup time to RD)
Address hold time from RD

tSAR

tHRA

RD pulse width

tWRL

150

Data output delay time
from address

tOAD

120

Data output delay time
from RD )

tORO

120

Data float delay time
from RD t

tFRo

Address setup time to WR )

tSAW

Address hold
time from WR

tHWA

Write Cycle

WR pulse width
Data setup time to WR

Data hold time from WR

tWWL

150

tsow

120

tHWO

160

Read/Write Cycle
RD/WR recovery time (Note 2)

tRY

Transmit or Receive Cycle
Transmit/receive data cycle
STRxC, TRxC input clock cycle

tCYO

tCYC

125

tCYK
ns

tWCH

tWCL

STRxC, TRxC input clock pulse
High-laval width
Low-level width

Transmit Cycle
TxD delay time from STRxC
TRxC)
INT delay time from TxD
DRQTx delay time from TxD

tOTCTD1

100

tOTCTD2

300

x16, x32, x64 mode

tOTDlQ

tCYK

Tx INT mode

tOTDoa

tCYK

Tx DMA mode

Notes [cont]:

(2) For all operations except Tx/Rx data transfer

2-26

xl mode

r-iEC

pPD72001

AC Characteristics (cont)
Limits, 8 MHz
Parameter

limits, 11 MHz

Symbol

Min

Max

Min

Max

Unit

Test Conditions

tSRORC

tHRCRO

140

tORCIO

tCYK

Rx IN mode

tORCOO

tCYK

Rx DMA mode

Receive Cycle

RxD setup time
to STRxC t, TRxC

RxD hold time
from STRxC t, TRxC

INTd~time

from RxC

t (Note 3)

DRORx delay time
from RxC t (Note 3)
DMA Request Control
DRORx I request
delay time from Rii I

tOROO

120

DROTx I request delay time
from WR I

tOWOO

120

Interrupt Control
INTAK low-level width

tWIAL

PRO delay time from PRI

toplPO

PRI setup time to INTAK
PRI hold time
from INTAK t
Data output
delay time from INTAK
Data fioat delay time
from INTAK t

150

150
50

tSPIiA

tHIAPI

120

to lAO

120

tFIAO

tWMH

tCYK

tWML

tCYK

When vector output
is selected.

Modem Control
CTS, DCD, SYNC pulse
High-level width
Low-level width
lliLd~

time from
CTS, DCD, SYNC

tOMIO

tCYK

Sync Control
SYNCdelaLSTRxC t, TRxC t

tOTRCSY

125

1000

tCYK

COP external
synchronization

Crystal Oscll/ator
XI1 input cycle time

tCYX

1000

Reset

RESET pulse width

tWRSL

tCYK

Noles [conI]:

(3) STRxC or 'fRXC, whichever is used for the receive clock

2-27

NEe

pPD72001
Timing Waveforms

AC Test Load Circuit

Clock Input Test Points

f3.3
0.6

Test points

-----'

3.3\
0.6 \'-._ _ __

CL= 100pF
[includes jig capacitance J

83·004286A

liD Waveform Test Points

2.4---...,X
_ _ _- J

:::

83-004267A

Test points

0.45

:::x'-___
83-004285A

Clock Timing

tCYK
tWKH--

tWKL-

ClK

tKF -+

tKR~

f483-0042886

Read Cycle

CtO,B/A

-----'X------------'f~.-~
IWRL

tSAR-I

•

-tHRA_

V
-tORO--

tOAD

.
83·0042898

2-28

t't{EC

J.lPD72001

Timing Waveforms (cont)
Write Cycle

C/O,B/A

){

-~----~,I-IHWA
tWWL
tSAw~ll.

I S D W -~

63-0042908

Read/Write Cycle (for al/ operations except Tx/Rx data transfer)

C/o,B/A

RD, ViR

\~--

\'--_ _----J/

~---------------'RV----------------~L
-----'\,-----"}.
- - - - - .

83-004291B

Transmit Cycle
1--------ICyC------------+1

STRxCA/B
TRxCA/B
tOTCTD-+

TxDA/B

ICYD

)

)
_IDTDIO ____

\
!-IDTDDO--+
DRQTxA/B
83-0042928

2-29

ttlEC

pPD72001
Timing Waveforms (coni)
Receive Cycle

•

STRxCA/B
TRxCA/B
tSRORC-

tHRCRO

\
tCye

RxDA/B

tCYC

-twCL-I-tWCH-

-tORCIQ-

\
-tORCOQDRQRxAlB
83-0042938

DMA Request Control

DRQRxAlB

_ _ _- - - , \ j - - t e R O Q _

Ri5

wo-------.t"·oJ
83-0042948

Modem Control

tWML

CTSA/B, - - - - DCDAlB,
SYNCAIB

t..

2-30

tOMIQ

tWMH

\
83-0042968

ttrEC

tJPD72001

Timing Waveforms (cont)
Interrupt Control

- '"""f_t_

F1 A D
_ _ __

07"00

----«'--_--J)>------«'--_--J)
83-0042958

Sync Control

STRxCA/B
TRxCA/8

-.-I

\~_I

Last Bit of
SYNC Character

"I..... tOTRCSY ......

1st Bit ot
Data Character

\'--

\
"SYNCA/B input must be set to 0 at the rising edge of RxC after two clock cycles
following the last bit of SYNC character.
83-0042976

Crystal Oscillator

Reset

tCYX

...JJ

Xll~----""'\\I..____

83-004299A

83-004298A

Functional Operation

System Clock Control

Refer to the jlPD72001 AM PSG block diagram (figu re 2)
for an overview of the four major functional blocks of
logic listed below.

The system clock control logic receives and manages
the system clock (GlK), which operates the internal
circuitry of the jlPD72001. The system clock and
internal circuitry must be operating in order for the
transmitters and receivers ofthejlPD72001 to function.
In standby mode, the system clock is blocked by the
clock control circuitry and the transmitters and receivers can not operate. In clocked operation, the
system clock can be used as the source for the data
clock, which is used by the transmitters and receivers.

•
•
•
•

System clock control
Interface control
Transmitter
Receiver

2-31

ttiEC

pPD72001
The internal registers of the I1PD72001 are static in
nature and do not require the system clock to retain
thei r contents.

can be used as a timer with a wide dynamic range. The
clock source for the timer can be selected from the
system clock, the data clock, an external source, or a
crystal.

Interface Control
The interface control logic contains the signals used to
control the transfer of data and status information
between the host CPU and the AMPSC. This logic
block has four types of interface lines. The read/write
and control lines (RD, WR, C/O, B/A) select what data is
to be transferred and the direction of the transfer. The
reset line (RESET) which is part of this group, resets
the internal state of the I1PD72001 when held active.
The interrupt control line (INT) sends a signal to the
host CPU when the AMPSC requires attention. The
interrupt acknowledge line (INTAK) signals the
I1PD72001 when the host CPU is ready to service its
request for attention. The interrupt priority lines (PRI,
PRO) are used to form the interrupt priority daisy
chain, which arbitrates the interrupt service priority.
The DMA control lines (DRQRxA, DRQTxA, DRQRxB,
DRQTxB), inform the DMA controller when a data
transfer is ready. The data bus buffer provides temporary storage of the data (07-00) being transferred from
the internal registers of the JlPD72001 to the host CPU.

Transmitter
Each channel's transmitter accepts parallel byte data
and sends it out serially. The data is sent out at a rate
determined by the transmit data clock (TxCLK). The
source of this c!cck is determined by the clock control

multiplexer. Bytes are loaded into the transmit buffer.
When the transmit shift register is empty, the contents
of the transm it buffer are loaded into the transm it sh itt
register.
The transmitter is also responsible for the transmit
CRC calculation and sending flags and sync characters.
The transmitter can be made to send breaks and aborts
using commands from the host CPU.
The internalloopback feature connects the transmitter
to the receiver and disconnects the receiver from the
RxD pin.
The echo loop featu re con nects the receiver to the TxD
pin and disconnects the transmitter.
The Baud Rate Generators (BRGs) divide down the
selected clock source to produce data clocks that can
be used for the transmitter and receiver. The clock
multiplexer selects the clock sources for them. By
selecting the correct value for the BRG count, the BRG

2-32

Receiver
The receivers in the AMPSC accept serial data into the
receive shift register, which in turn assembles this
serial data into parallel characters (byte). The
assembled byte is transferred into the receive buffer
(FIFO), which can contain up to three bytes. The
receive status of each byte is transferred along with it
through the receive buffer. In this way, the status
reported by the I1PD72001 is always current forthe byte
that is about to be removed from the FIFO.
The receive shift reg ister also checks for flags and sync
characters in the synchronous modes. Flags are automatically removed from the data stream, while sync
characters have the option of being retained. This is
determined by a CPU command.
The receiver in synchronous modes, calculates the
received CRC and checks it against the CRC that is
received with the data. A difference is reported to the
host processor.
The digital phase-locked loop (DPLL) is used to
separate the data from the clocking information in
the NRZI, FM, and Manchester encoded received bit
streams. It locks in on the received data and provides
an accurate and stable clock for the receiver.

Standby Mode
The I1PD72001 enters the standby mode after a hardware
reset or by issuing the standby command (CR13 bit
DO). In standby mode, the system and data clocks are
blocked internally by the clock multiplexer. This shuts
down the AMPSC and reduces power consumption
greatly. System power requirements can be further
reduced by externally stopping the input clock
transitions.
In standby mode, the I1PD72001 retains all register
values, but no internal functions operate and read
operations of the AMPSC will not transfer any data.
To release the standby mode, a write cycle must be
performed to CRO. To resume normal operation without
affecting the internal state of the device, a zero can be
written to CRO.

ttlEC
Figure 2.

tJPD72001

IlPD72001 AMPSC Block Diagram

CFrB

DTRA

I ~p+_-----------,
~

TxRx Clock

'--------------,

i - I

r--

Tx BRG

'-G~

Tx BRG

~~~-L~I~~
Rx BRG 1----;---;--.1 Rx BRG
H, l
1 '"-

I-

,--TxRx
Clock
Control

"--'-_---=.1----1
l'v~ SR12·l5

DPLL

.--1-

TxClK

/-----c:-t-r... RxClK
1

J---

tnlL-H_i-!it - i i - - - - i II-

i I p
L-------i--Osc

System
Clock

~
~
I.r"

I' ~

SRO,3,
4,7

TxRx
Control

SR1-4 kl'v----l
SR10-ll

DRQRXA!::=
DRQTxA _--DRQRX~!::=
DRQTxB.

XI2A/SYNCA

1+-+-+--RxDA

:::r

'---rT-

I~============~~====~

Receiver

Buffer
1'.
Rx
I I
I
~
r-----------~~----~

-I--

Interface
Control

XllA/STRxCA

~~4-~-~--~-1---DCDA

I~~

Clockl
CLK _____ ~~~~~i f---

TRxCA

~r-.l......-l---~

r----v~1

DMA ...
Control

~------------+-+TxDA

r--

r----"-'" Transmitter
-v

Interrupt
Control

,C)
07-00

r-f.o-I~

Data
Bus
Control

Channel B

RO'----= WR----= Readl f--C/O----- Write
Biii----- Control

I---hLt
RESET----=~
~

~ TRxCB
p....
RTSB
OTRB

~
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J -

Xll B/STRxCB
XI2B/SYNCB
CTSB
DCOB
RxDB
TxOB
49M-000146

2-33

fttIEC

pPD72001
System Configuration Example
In the system configuration example (figure 3), the
pPD72001 is used as a high-speed interface to a
modem. It controls the modem interface and serial data
flow. The AMPSC is used with a direct memory access
controller (DMAC), such as the pPD71071 in order to
speed the data transfer and reduce the host CPU
overhead. The pPD72001 directly interfaces with the
host CPU, without requiring an interrupt controller,
such as thepPD71059. Extra hardware is not required,
since the AMPSC can generate its own interrupt
vectors.
Figure 3.

70108, 70116
CPU

?--

I I
I I

Memory

?--r

rr-

The AMPSC's flexible interface to a variety of host
processors makes connection simple.

System Configuration Example

,.-.

The interface between thepPD72001 and the host CPU
is not very complex. It requires only address decoding
logic for I/O operations. A multiplexer can be used to
decode DMA acknowledge signals. However, it is not
necessary with DMA controllers, such as thepPD71071,
which are able to do their own I/O addressing.

rr-

Address Bus

i--J

)

7Data Bus

Control Bus

MUX~

/~
INTAK
INT

07·00
RD,WR
C/O
B/A

/--

'v--

72D01
AMPSC

015·00 A23·AO

.........

OMAAK

t-.
ORa
RxO

TxO STRxC

71071
DMAC
OMARa

oco

RTS

Modem
83-0043046

2-34

t\'EC

pPD72001

Programming the AMPSC

Tilbl. 1.

Software programming the AMPSC utilizes separate
data and command/status paths. The data path uses an
a-bit register. The command/status path has a set of
a-bit registers structured for efficient and complete
control with a minimum of interaction from the host
processor.

Control
Registers

Status registers (figure 5) hold device status information. The host processor can sense the AMPSC
device status by reading these registers.
Frequently used information is retained in control
register CAO and status register SAO. This information
can be sent or received by writing or reading a single
byte. In normal operation, CAO is initially loaded with a
command to reset the AMPSC. Next,CA2 is loaded to
setthe interface mode. This is followed by the remaining
registers, beginning with CA4 to set the protocol type.

CRO
CRl
CR2

Functions differ for CR2A and CR2B

CR3
CR4
CR5

The internal registers (table 1) are divided into control
registers (CAs) and status registers (SAs). Also, unless
otherwise noted in table 1, each channel has its own set
of registers; for example, CA1A and CA1 B are the CA1
control registers for channels A and B.
The control and status registers for a given channel are
all accessed through the same I/O address. The different registers are selected by using the register
pointer in CAO (bits 00-02). The register pointer is
reset to zero after each register operation. For example,
to write to CA2, a two is initially written to the control
address (C/O pin set high). After this the value to be
written into CA2 is also written to the control address.
To read from SA2, a two is written to the control
address, and then a read cycle at the control address
reads the value in SA2. A zero is not required to be
written before CAO and SAO are accessed. Control
registers (figure 4) set up the device operation mode or
control device operations. The host processor writes
control words into these registers.

AMPSC Internal Reg/.'.r Configuration

CR6
CR7
CRB; CR9

Registers for each channel are used in
pairs: CRBA/CR9A; CRBB/CR9B

CR10

CRll
CR12

lx/Rx BRG registers are loaded by
setting bits 0 and 1 of CR12

CR13
CR14
CR15
Status
Registers

SRO
SRl
SR2B

No register SR2A

SR3
SR4A

No register SR4B

SR5, SR6, SR7 'No registers
SRB
SR9
SR10
SRll
SR12, SR13

Registers for each channel are used in
pairs: SR12A/SR13A; SR12B/SR13B

SR14, SR15

Registers for each channel are used in
pairs: SR14A/SR15A; SR14B/SR15B

2-35

pPD72001
Figure 4.

Control Register Bit Functions

Control Register 0

Control Register 2 [Channel B]

1 D71 D6J D51 D41 D31 D21 Dl1 DOJ

! ! !
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

OJ Pointer
1
2 SpeCifies
3 the AMPSC
4 Register to
5 be Accessed
6
7

No Operation
High Pointer [Selacts Registers 8-15]
Reset EXTlStatu s Latches
Channel Reset
Enable INT on Next Rx Character
Resat Tx INT/D MA Pan ding,
Error Resat
End of Interrupt [Channal A Only]

l_~=~===g}lnitial
V4

L_~========:V5
V6

Control Register 3

Receiver Enable
Sync Character Load Inhibit!
,
Muitlcast Enable
'----Address Search Enable
'--'--~-Rx CRC Calculator Enable
'--------Ente~ Hunt Phase
'----~-----Auto Enable Moda
o
o
1
1

ExternaliStatus 'INT Enable
Tx INT/DMA Enable
'--,,--First Tx INTIDMA Enable

o
o
1

0
,1
0
1

5
7
6
8

BitSiRx
BilslRx
BitSiRx
BitslRx

Character
C,haracter
Character
Character

Control Register 4

o Rx INT Disable
1 Rx INT on First Rx Character

E~::'~:~ ~~:':::[~,,!e[~t

O=:rlt'f
Rx INT on All Rx Characters,
Parity Error is Not Special Rx INT

Parity Enabl.!.Parity Even/Odd

o
o

FIrst Rx INT Mask
Overrun Error Special Handling
L..----Shon Frame Detact Enable

o
o
1
1
,,0
o
0
0
1
1

0
1
,0
1

Both Channels INT
Channel A DMA; CHB INT
Both Channels DMA
Reserved, [Use Is Prohibited]

INT Priority RxB > TxAfTxA > RxB
0
0
1

0
1

1
0
0
1
1

0 Type A·l INTAK Vector [8085 Master Mode]
1 Type A·2 INTAK Vector [8085 Slave Mode]
0 Type A·3 INTAK Vector
[8085/8259 Slave Mode]
1 Type B-1 INTAK Vector [8088/86 Mode]
0 Type B-2 INTAK Vector
[8088/86, 8259 Slave Mode]
1 Reserved, [Use is Prohibited]
0 Reserved, [Use is Prohibited]
1 Reserved, [Use Is Prohibited]

INT Status Affects Vector Value
Vectored INT Enable

o
1
o
1

Control Register 2 [Channel A]

0
0
0

~------------V7

No Operation
Initialize Rx CRC Calculator
Initialize Tx CRC 'Calculator
Reset Tx Underrun/End of Message Bit

Control Register 1

Vector INT
Value

t '

0
1
0
1

Dala
Data
Data
Data

0
1
0
1

Sync Mode
Async, 1 Stop Bit
Async, 1.5 Stop Bits
Async; 2 Stop Bits

MONO Sync Mode
BISYNC Mode
HDLC Meide
External Sync Molla

Clock
Clock
Clock
Clock

Is
Is
Is
Is

xl Data Rate ,
x16'Data Rate
x32 Data Rate
x64 Data Rate,

Control Register 5

Tx CRC Calculator Enable
RTS

Transmitter Enable
l_~=~===CRC-16/CRC-CCiTT
Send BraaklAbon

o
o
1
1

o
1
o
1

5
7
6
8

BitslTx
BitslTx
BitslTx
Bits/Tx

Character
Character
Character
Character

DTR
49M·000147

NEe
Figure 4.

pPD72001

Control Register Bit Functions (cont)
Control Register 11

Control Register 6

1 D71 Dsl D51 D41 D31 D21 Dl] DO 1

Ill:

Bit
Bit 1
Bit 2

::::
Bit 5
Bit s
Bit 7

L~::'C

Bytel
Address

BRG INT Enable
Idle Detect INT Enable
' - - - - - A l l Sent INT Enable
' - - - - - - DCD INT Enable
'--------Sync/Hunt INT Enable
' - - - - - - - - - - C T S INT Enable
' - - - - - - - - - - - - T x Unde"un/EOM INT Enable
'--------------Break/Abort/GA INT Enable
Control Register 12

Control Register 7

I D71 Dsl D51 D41 D31 D21 Dl I DO I

LJ:

Bit 9
BitS
::: ~~
Bit 12
Bit 13
Bit 14

Load Rx BRG
Load Tx BRG

BRG INT Enable
L_-=:==== TxRx BRG
INT Enable

Sync
High By tel
Flag

Bit 15

Control Register 8

0 Reserved, [MUst be 01

DPLl BRG Source Tx BRG/Rx BRG
TRxe BRG Source Tx BRG/Rx BRG

Control Register 13

I D71 D61 D51 D41 D31 D21 DIlDo I

Ill:

Bit 1
BltO}
::: ~ Tx Data
Bit 4 Length,
Bit 5 Low Byte
Bit 6
Bit 7

Enter Standby Mode
Tx Data Length Counter Enable

Reserved, [Must be 0]

Control Register 14

Control Register 9

LD7J DsJ D51 D4l D31 D21 DIlDO 1

ll:

It 9 }
Its
B It 10
B it 11 Tx Data
B It 12 L~ngth,
B it 13 HIgh Byte
B It 14
B it 15

Control Register 10

Tx BRG Enable
Rx BRG Enable

_~=~====BRG
Source: Xtai·STRxCI
External Loop Enable

o
o
o
o

0
0

1
1

System Clock

loop Back Enable

No Operation
1 DPLL Enter Search Mode
o DPLL Reset Missing Clock
1 DPLL Disable
o DPLL Select BRG as Source
1 DPLL Select XTAL/STRxC as Source
o DPLL FM Mode
1 DPLL NRZI Mode

Control Register 15
1 D71 Dsl D51 D41 D31 D21 D1 1 DO
Sync Character
Length S/8

Auto Tx Enablel

o
1
1

Loop Enable
L----Abort on Tx
Underrun
' - - - - - - - M a r k Idle Enable
' - - - - - - - - - A u t o Tx on Syncl
Tx on Loop
o
o
1

0
1
0
1

NRZ Data Encoding
NRZI Data Encoding
FM1 Data Encoding
FMO Data Encoding

CRC Initial State

TRxe Source is
1 TRxC Source Is
0 TRxC Source Is
1 TRxC Source Is

XTAL
TxCLK
BRG Output
DPLL Output

TRxe is Output

o
o
1
1

o
1
o
1

RxClK
RxClK
RxClK
RxClK

TxCLK
TxCLK
TxCLK
TxCLK
Source
Source
Source
Source

is
is
Is
Is

Source
Source
Source
Source

Is
Is
Is
is

STRxC
TRxC
TxBRG Output
DPLL Output

STRxC
TRxC
RxBRG Output
DPll Output

XTAl Oscillator Enable
49M-000151

2-37

pPD72001
Figure 5.

Status Register Bit Functions

Status Register 0

Status Register 4A
1 D71 D6 1 Dsl D4 1 D31 D2 1 Dll DO 1

Channel B External/
tatus Interrupt Pending
Channel B Tx Interrupt Pending
Channel B Rx Interrupt Pending
Channel A External/
5 tatus Interrupt Pending
Channel A Tx Interrupt Pending
Channel A Rx Interrupt Pending
Channel B Special Rx
I nterrupt Pending
Channel A Special Rx
Interrupt Pending

Rx Data Available
Sending Abort
' - - - - T x Buffer Empty
' - - - - - - S h o r t Frame Detected
' - - - - - - - - Parity Error
' - - - - - - - - - - Rx Overrun Error
'------------CRClFraming Error
'-----~-------'-- End of Rx Frame
Status Register 1

Status Register 8
BRG Zero Count
Idle Detected
' - - - - A l l Sent
'-------DCD
'--------Sync/Hunt

'---------CTS

Bit 1
BitO}

' - - - - - - - - - - - - T x Underrun/End 'of Message
'--------------BreakfAbort/GA Detected

L_-=====Bit2
Bit 3

Tx Data Length

'-_~::::::::::::::"- ::: ~ Counter, Low Byte
'-----------Bit6
'--------------Bit7

Status Register 2B

Status Register 9

~~;:~}

L~====V2/A2/B2
'-_______
~!;!!

Interrupt Vector
Bit 8
9 } '
'-----B" 10
' - - - - - - B i t l l Tx Data Lenglh
' - - - - - - - - B i t 12 Counter, High Byte

'-----------V5
'-------------V6
'------------V7
Note:
[1) ,Bits A4·A2 are modified if ,Type A Vectors are selected
[2) Bits B2·BO are modified if Type B Vectors are selected
[3) If Status Affects Vector bit is set [CR2A Bit 6):
A3/Bl A2/BO
o
0
o
1
1
0
1
1
A4/B2
A4/B2

=0
=1

Condition
Tx Buffer Empty
External/Status
Rx Data Available
Special Receive

'---------~Blt13

' - - - - - - - - - - - - B i t 14
'--------------Bit15
Status Register 10
1 D71 D61 D51 D41 D31 D21 Dl

IlJ~

Indicates Channel B
Indicates Channel A

'------------Reserved, '~t~ta Unknown
' - - - - - - - - - - - - - - R e s e r v e d , State Unknown
Note:
[1] Residue Codes that Indicate No Resld;,,;:
Bits per Data Byte Residue Code
5 Bits/Character
1 0 0
6 Blls/Character
0 0 0
7 Bits/Character
0 1 1
8 Blls/Character
0 1 1

eserved, State Unknown

x Synchronized/On Loop
Raserved, State Unknown
Reserved, State Unknown
5 eildlng On Loop
RBserved, State Unknown
DPLL Missing Two Clocks
DPLL Missing' One Clock

Status Register 3

'BhO}
Bit 1
Residue Code
2
'
L_~==== Bit
Rx BRG count Is Zero
' - - - - - - - - T x BRG Count is Zero
'----------Resarvad, State Unknown

I DO 1

Status Register 11

1 D71 D61 DS

I D41 D31 D21 D1 I DO I
BRG Interrupt Enabled
I l J ldie Detect Interrupt Enabled
All Sent Interrupt Enabled
DCD Interrupt Enabled
Sync/Hunt Interrupt Enabled
CTS Interrupt Enabled
Tx Underr4n/EOM
Interrupt Enabled
Break/Abort Interrupt Enabled
49M·000152

2-38

t\'EC
Figure 5.

pPD72001

Status Register Bit Functions (cont)
SlalUS Regisler 14

SlalUs Reglsler 12

~gilH}

BH 3
Bit 4
Bil5
BH 6
'-----------BiI7

Rx BRG Time
Conslanl, Low Byte

BI11
BiIO}
'----BiI2
' - - - - - - - B i I 3 Tx BRG Time

lJ~~~~~~~~~BiI4

Bil5
Bil6
Bil7

SlalUs Reglsler 13

Conslanl,
.
Low Byle

Slalus Reglsler 15

I 071 061 051 041 031 021 01 1 00 I

Ill:

Bil9
BItS }
BI110
BII 11
BII 12
Bil13
BI114
BI115

Rx BRG Time
Conslanl, High Byte

::::

}

'----BiI10
'------BI111
' - -_ _
L..-_-_-_-_-_-_-_-_-_-_-_ : : :

Tx BRG Time
Conslanl, High Byte

'-----------BI114
'-----,--------BI115
49M-0001S3

Control Register CRO
CRC Control [07-06]
These bits are valid when the COP or BOP mode is
selected. They are not used in the asynchronous mode.
No Operation [00]. This command has no effect.
Initialize Rx CRC Calculator [01]. This command
initializes the receiver (Rx) CRC calculator. The command should be issued before data reception starts.
However, before this command is issued, the initial
value of the Rx CRC calculator must be set by the value
of CR10 bit 07.
This command is not required in the BOP mode, since
the CRC calculator is automatically initialized upon
receipt of the flag value according to the value of CR10
bit 07.
Initialize Tx CRC Calculator [10]. This command
initializes the transmit (TX) CRC calculator. It should
be issued before data transmission is started. However,
before the command is issued, the initial value of the Tx
CRC calculator must be set by the value of CR10 bit 07.
In the BOP mode, if CR10 bit D7 is set to one, the Tx
CRC calculator is automatically initialized to one,
when a flag value is loaded into the transmit shift
register within the AMPSC.
Reset Tx Underrun/EOM Bit [11]. This command
resets SR1 bit 06 from one to zero (transmit underrun/end-of-message bit). If data is not loaded into
the transmit buffer before the transmit shift register
begins transmitting its last bit, the AMPSC enters the

Tx Underrun/EOM state. At this point, the AMPSC
checks to see if a CRC SYNC/Flag or abort is to be sent,
which depends on the value of SR1 'bit 06 and the
operating mode. Therefore, SR1 bit 06 must be reset
before transmission of the last byte starts. At the
occurrence of Tx underrun, the CRG or the SYNC
character/flag is sent when the SR1 bit 06 is a zero or
one, respectively.SR1 bit 06 is set when the CRC or
SYNC/Flag byte is written to the Tx register by the
AMPSC.
In the BOP mode, bit 06 of SR1 is automatically set to
zero when the first data byte of a frame is written into
theAMPSC.
Command [05-03]
These bits control the state of the device.
No Operation [000]. This command has no effect.
High Pointer [001]. This command is used in conjunction with CRO bits 02-00 (Register Pointer) to access
status registers. 8 through 15. For example, to access
SR11, bits 05-00 of CRO are set to 001011.
Reset E/S Bit Latches [010]. This Reset External/Status
Bit Latch command is issued when an E/S bit (each bit
of SR1) latch operation has occurred. It opens the E/S
latches and prepares for the latching of a new E/S bit
status change. If E/S interrupt is enabled, an E/S
interrupt will occur and the latches will latch when an
E/S bit's status changes. Not all state transitions will
cause latching and an interrupt to occur. See the description of SR1 for details. New status will not be
available in SR1 until this command is issued.
2-39

t-IEC

pPD72001
Channel Reset [011j. This command resets an AMPSC
channel. It performs a function similar to the RESET
pin. Executing the channel reset command halts
channel operation. After a channel reset,three system
clock periods (tCY) should elapse before any further
commands or data are sent to the channel.
Enable Next Rx Character Interrupt [100j. This command is valid only when the First Rx INT mode (CR1
bits 04-03 = 01) is selected. It is issued at the end of a
message to request an additional Rx interrupt for the
first received byte of the next message. The additional
Rx interrupt occurs when the next data byte is received
after the command is issued.
This command has no effect when the First Rx INT
mask is on (CR1 bit 05 = 1), even if the First Rx INT
mode is selected.
Reset Tx Interrupt/DMA Pending [101j. This command
is used to Clear a pending Tx interrupt request or Tx
OMA request while the Tx buffer is empty (SRO bit
02 =1). It is typically used to clear a Tx interrupt or
Tx DMA request caused by the Tx buffer empty state
that occurs after the last byte is written into the AMPSC.
Error Reset [110j. This command is used to reset the
pertinent bits (SRO bits 07-D3) if a Special Rx Condition has occurred. If it occurs when the First Rx INT
mode is selected, any data that is subsequently
received is not transferred to the last stage of the
AMPSC internal Rx buffer, but will remain in the first
and second stages until this command is issued.
End of Interrupt [111j. This command is used so that
theAMPSC can recognize the end of interrupt service
propessing. It should be issued when interrupt service
for the AMPSC is completed. Command execution
resets the internal interrupt service latch and reenables lower priority interrupt requests. This
command is required when the start of interrupt
service has been indicated by either conducting an
INTAK cycle, or by reading SR2B.

Register Pointe.r [02-00]
These bits specify which AMPSC register number is to
be accessed. The bits are reset to 000 when system
reset is executed or when the AM PSC is accessed after
a Registe~ Pointer value is specified. For registers
numbered 8 and above, the High Pointer command
(05-03 =001) is used inconjunction with the Register
P~inter to acceSs them.

2-40

Control Register CR 1
Short Frame Detect [07]
Valid only in BOP mode, this bit detects short HOLC
frames (frames that are less than 32 bits long).
Short Frame Detect Disabled [OJ. Short frame detection is disabled.
Short Frame Detect Enabled [1j. Short frame detection
is enabled. If a short frame is received, SRO bit 03
(Short Frame Oetect) is set to 1, causing a Special Rx
condition interrupt.

Overrun Error INT [06]
This bit selects the timing of overrun error detection.
Normal Mode [OJ. In this mode, an overrrun error is
indicated when the received data that caused the
overtunerror is transferred to the last stage of the
receive buffer. A Special Rx Condition interrupt occurs
at this time.
Special Mode [1j. In this mode, the Rx Overrun Error
bit immediately reflects an overrun error within the
AMPSC. A Special Rx Condition interrupt also occurs
at this time. The received data that caused the overrun
error may not be the byte at the last stage of the
RxFIFO.

Receive Interrupt on First Character Mask [05]
This bit is enabled only if the First Rx INT mode (CR1
bits D4-D3 = 01) is selected. It is used to mask Rx
interrupts caused by received data. Setting this bit to 1
causes all first receive interrupts to be masked. It does
not mask Special Receive interrupts. It is used in data
transfers when no interrupt service is desired or
required, such as DMA only data transfer.

Receive Interrupt Mode [04-03]
These bits set the Rx I NT mode. They specify the way
received data is managed.
Disable Mode [OOj. This Receive Interrupt Disable
mode is used to accept received data Using status
polling, or to disable the receive interrupt request.
First Rx Character Mode [01j. In this mode, which is
typically used with DMA data transfer, an Rx interrupt
occurs orily when the first byte is received. This occurs
when Rx is enabled after initialization or after the
Enable Next Received Character interrupt command is
issued.

fttlEC

pPD72001

All Receive-1 Mode [10]. This mode causes a receive

interrupt to be generated for each byte received. In this
mode, a parity error causes a Special Rx Condition
interrupt.
All Receive-2 Mode [11]. This mode is the same as All

Receive-1, except that parity error does not cause a
Special Rx Condition interrupt.

Interrupt Status Affects Vector [06]
This bit determines if the value of an interrupt vector is
modified by the cause of interrupt. If the bit is set, the
vector is modified as specified by bits 05-03. If the bit
is reset, the vector is not modified and the cause of
interrupt must be determined by reading SRO and SR1.

Interrupt Vector Mode [05-03]
First Transmit Interrupt/OMA Enable [02]
This bit determines whether'a Tx INT/OMA request is
generated immediately after the transmitter is enabled.
It is valid when INT/OMA is enabled (CR1 bit 01 = 1).
A transmit interrupt or OMA request is issued if bit 02 is
1 when the transmitter is enabled, but not if the bit is O.
Regardless of the state of bit 02, an interrupt or OMA
request is generated when the Tx buffer makes the
full-to-empty transition.

Transmit Interrupt/OMA Enable [01]
This bit enables the transmit interrupt or OMA request.
Each time a transmit interrupt c.ondition exists and
provided bit 01 is set, an interrupt or OMA request is
generated.

External/Status Interrupt Enable

[~O]

If bitDO is set, a change in state of the external/status
bits causes. an interrupt and the state of the bits is
latched. The latc;hes must be reset with the Reset
External/Status Bit Latch command (CRO bits 05-03),
before subsequent interrupts can occur.

Control Register CR2A
Vectored Interrupt Enable [07]
This bit enables transmission of the interrupt vector. If
the bit is set, the interrupt vector is placed on the data
bus during the INTAK cycle. Ifthe bit is reset, the vector
is never placed on the bus; It can be read by the host
processor. In this mode, the INT signal is released after
the host processor reads SR2B or clears the interrupt
condition.

These bits determine the interrupt vector operation.
The bits also select which bits of an interrupt vector are
to be changed when the Status Affects Vector is set by
CR2A bit 06. For details of how the vector is modified,
refer to the description of register SR2B. Table 4 shows
the vector operation determined by bits 05-03.

Interrupt Priority Select [02]
This bit selects the priority of interrupt requests within
the AMPSC. The priority does not apply to OMA
transfer.

If bit 02 0, the priority from high-to-Iow is RxA, TxA,
RxB, TxB, E/S A, E/S B.
If bit 02 = 1, the priority from high-to-Iow is RxA, RxB,
TxA, TxB, E/S A, ElS B.

Interrupt/OMA Mode [01-00]
These bits select the data transfer mode for each
channel. The E/S, Rx, and Special Rx. Condition
interrupts can be enabled in both modes. The Tx
interrupts are disabled on any channel in OMA mode.
The three modes are as follows:
Bits 01-00
00
01
10

Mode
Both channels interrupt
OMA on channel A, interrupt on
channelB
OMA on both channels

Control RegisterCR2B
Bits 07-00 of CR2B set the initial value of an interrlJpt
vector.

2-41

ttlEC

pPD72001
'ftIble4. Interl'l,lpt VectorOperatlon Throughout INTAK Sequence

Data Boa StatuIllNTAK relponae Ot AMPSC)

CR2A
05

Mode

0
0

A2
113

B1
B2

jijjj

RCye11

1
V7

1
V6

1
M3

1
M2

low
low

1st.
2nd.
3rd.

1
VO

0
0

high
high

1st.
2nd.
3rd.

low
low

1st.
2nd.
3rd.

high
high

1st.
2nd.
3rd.

low

1st.
2nd.

high

1st.
2nd.

1
High Impedance
High Impedance

High Impedance

V7
0

High Impedance
High Impedance
High Impedance
High Impedance

High Impedance
High Impedance

Not..:

(1) •

=Don't care.

(2) When Status Affects VeC10r (bit 6 of CR2A) is set, the M data bits are modified to iridicate the interrupt source.
(3) Modes A3 and 82 ignore the state of PRJ. They are slave modes for use with an interrupt controller such as the IlPD71059.

Control Register CR3

Enter HuntPhase [D4]

Receive Character Bit Length [D7-D6]

Valid in COP or BOP mode, this bit forces the AMPSC
to enter the Hunt Phase. In the Hunt Phase, the
pP072001 searches the received data stream for either
a sync or flag before it begins loading data into the Rx
FIFO.
'

These bits determine the number of bits per character
In the received data.
Bits 07-06

Bits/Character

00
01
10
11

5
7
6
8

Receive CRC Calculator Enable [D3]

Auto Enable Mode [DS]
Bit 05 enables and disables the auto enable mode. In
this mode, the CTS and OCO pins control operation of
the transmitter and receiver, respectively. If the input
pin is high, the Tx or Rx is disabled. The RTS pin
outputs the current transmitter status. The pin remains
low during transmission and returns high only after all
characters have been sent. The auto enable mode is
enabled by setting bit 05 to one and disabled by
resetting bit 05 to zero. With bit 05 0, CTS, OCO, and
RTS function as normal inputs and outputs.

2-42

Valid only in COP or BOP mode, bit 03 determines
whether or not a CRC calculation is to be performed on
the received data. The CRC is calculated 8 bit times
afters byte is transferred into the receive FIFO. If bit 03
is reset before this time, the byte will not be included in
the CRC calculation. The bit must be set sgain after the
next byte is received to resume the CRC calculation.

Address Search Mode Enable [D2]
Valid only in BOP mode, bit 02 determines whether or
not the address field value of a received frame is to be
compared with the value set in CR6. If the bit is set to
one, Address Search is enabled and the AMPSC
checks the first byte of the frame. If the byte matches
CR6 or the global address (FFH), the frame is received.
If the byte does not match, the AMPSC enters the Hunt
mode again, and the byte and the rest of the frame are
blocked and not received. If Multicast mode is enabled
(bit 01), only the four most significant bits (07-04) of
the address byte are compared.

t\fEC

pPD72001

Sync Character Load Inhibit/Multicast
Enable [01]
Valid only in COP or BOP mode, bit 01 has a different
meaning in each mode. In COP mode, setting bit 01 to
one enables the Sync Character Load Inhibit function.
This prevents any byte that matches the value in CR6
from being loaded into the receive FIFO and being
included in the CRC calculation.
In BOP mode, bit 01 enables the Multicast function. In
this mode, which is a modified form of the address
search mode, only the most significant four bits ofthe
received address are compared with the identical bits
of CR6. Frame acceptance will function in the same
way as in the address search mode.

Receiver Enable

Tx Stop Bits/Sync Mode [03-02]
Bits 03-02 select the number of stop bits sent after
each byte in Asynchronous mode, or they select the
Synchronous mode.
Bits 03-02
00
01
10
11

Parity Select [01]
Valid in Asynchronous and COP modes, bit 01 selects
the parity type: 0 odd and 1 even. It is used only
when the Parity Enable bit 00 of CR4 is set to one.

[~O]

This bit enables and disables the receiver. Setting bit
00 enables the receiver, resetti ng it disables the receiver.

Control Register CR4
Clock Rate [07-06]
Bits 07 and 06 select the clock rate divisor. They are
ignored in the internal synchronous modes. In the
external synchronous mode, only the x1 and x16
selections are valid.
In asynchronous mode, the following values apply:
Bits 07-06

Oivisor

00
01
10
11

x1
x16
x32
x64

Mode
Sync mode
Async mode, 1 stop bit
Async mode, 1.5 stop bits
Async mode, 2 stop bits

Parity Enable

[~O]

Bit 00 enables the parity bit calculation on transmitted
data and parity checking on received data. Setting bit
00 enables parity; resetting bit 00 disables parity. If the
length of the received character is 7 bits or less, the
parity bit can be read in the received data byte. If parity
is disabled, no parity bit is transmitted and none is
expected on receipt.

Control Register CR5
OTR Control [07]
This bit controls the OTR pin status: 0 = high and 1 =
low. The OTR pin function is disabled if channel B is
operating in the OMA mode (CR2A bits 01-00 10)

li'ansmit Character Bit Length [06-05]

The divisor value is the factor by which the supplied
data clock is g reater than the data rate for the transmitter
and receiver. The data clock source is selected by the
clock multiplexer. It can be set to any of the BRG,
OPLL, or external clock sources. The divisor determines
the number of times that the received data is sampled
per bit time by the receiver. Also, it determines the
composition of the transmitter.output.

Protocol Mode [05-04]
Bits 05-04 select the synchronous protocol, which are
used when synchronous mode is selected with bits
03-02.
Bits 05-04

Mode

00
01
11
10

Mono-Sync, character synchronous
Bisync, character synchronous
External Sync, character synchronous
HOLC, bit synchronous

These bits specify the bit count per character in
transmitted data.
Bits 06-05

Bits/Character

00
01
10
11

5 or fewer

7
6
8

If the bit count per character is 6 or 7, only the low-order
bits of the byte are valid and the most significant bit(s)
are ignored. If the count is 5 bits or lower when writing
into the transmit data register, refer to the data format
that is shown.in table 5.

2-43

t-{EC

pPD72001
7IJble 5.
Bits

Parallel Data Format for One to Five Bits per
Character
07

0
0

4
5

DO
DO
DO
DO
DO
DO

Dn = Effective data bit

Send Break/Abort [04]
Bit 04 controls the break or abort transmission
according to the selected operation mode. In asynchronous mode, bit 04 controls sending the break signal
(TxO set to spacing (0) condition). Setting bit 04to one
begins sending the break signal; resetting it to zero
returns the transmitter to normal operation.
In COP mode with Tx on Loop selected (bits 4 and 1 in
CR10), setting bit 04 causes the transmitter to be
synchronized with the receiver. The bit is reset automatically when synchronization is achieved.
In BOP mode, setting bit 04 to one causes eight 1-bits
(abort sequence) to be sent. After completion of the
message, bit 04 is reset automatically and the transmitter returns to the idle state.

ll'ansmit Enable [03]
Disable. Setting bit 03 to the zero state disables the
transmitter function. If the transmitter is currently
sending a character, the AMPSC waits until the
character is completed before setting TxO to the
marking (1) state. If bit 03 is reset during transmission
of a CRC character, a SYNC character or flag is sent in
place of the CRC character.
If 03 is reset in the COP or BOP mode, the Tx
Underrun/EOM bit (SR1 bit 06) is set.
IftheAMPSC is intheSOLCLoop mode (refer to CR10)
or Echo Loop Test (refer to CR14), the TxO pin is
connected to RxO, and is not set to marking.
Enable. Setting bit 03 to the one state enables the
transmitter to start transmission. If the Auto Enable
mode is selected (CR3 bit 05 1), the signal applied to
the CTS pin controls the transmitter operation.

CRC Polynomial [02]
This bit selects the polynomial used for CRC calculation. It is valid only in COP or BOP mode. Only the
CCITT polynomial is used in BOP mode. Bit 7 of CR10
sets the initial value of the CRC calculator.

2-44

02 = 0 (CRC-CCITT): The generating polynomial
expression is X 16 + X12 + X5 + 1.
02 = 1 (CRC-16): The generating polynomial expression is X16 + X12 + X2 + 1.

RTS Control [01]
Bit 01 controls the RTS pin. Setting bit 01 to the zero
state causes RTS to be high, setting it to the one state
causes it to go low. If Auto Enable mode is selected in
Asynchronous mode, RTS operates differently. If the
bit remains at zero from the start of transmission
through to the end, RTS will stay high. If it is set to one,
it remains low. If it starts set to one and is then set to
zero while transmitting, RTS will not go high until all
data is transferred out of the Tx shift register.

ll'ansmit CRC Calculator Enable

[~O]

Valid only in the COP or BOP mode, bit 00 determines
whether or not transmitted data is included in the CRC
calculation. If bit 00 is set when the byte is transferred
into the Tx shift register, the byte is included in the Tx
CRC calculation. Bit 00 should be set or reset before
loading a data byte into the AMPSC.

Control Register CR6
Valid only in the COP or BOP mode, this byte (bits
07-00) specifies the SYNC character pattern or address
value.
In Monosync or External Sync mode, 07-00 holds the
transmit Sync character. In Bisync mode, the low-order
byte of the Sync pattern is set in 07-00.
If the sync character is 6 bits (CR10 bit 00
03-00 should be set to one.

= 1), bits

In mono or external sync bits 01 and 00 are repeated in
positions 07 and 06.
In BOP mode, this byte is the secondary address.

Control Register CR7
Valid only in the COP or BOP mode, these bits specify
the Sync character or flag.
In Monosync mode, 07-00 holds the receive Sync
character. In BISYNC mode, the high-order byte of the
Sync character is set in 07-00. These bits are not used
in External Sync mode.
In BOP mode, the flag pattern (01111110) is set in bits
07-00.

NEe

pPD72001

Control Register CRB
Valid only in the BOP mode, CR8 bits 07-00 hold the
low byte (bits 7-0) of the transmit data length. Register
pair CR8 and CR9 must be set before the Tx Oata
Length Counter Enable bit (01 of CR13) and Tx Enable
bit (03 of CR5) are set. The transmit data length
register (TxOLR) is used to automate the sending of
HOLC frames. See the description of CR13 for detail
information.

Control Register CR9
Valid only in the BOP mode, CR9 bits 07-00 hold the
high byte (bits 15-8) of the transmit data length.
Register CR9 is paired with CR8.

Control Register CR10
Initial CRC State [07]
Valid only in the COP or BOP mode, bit 07 specifies the
initial state of the CRC calculation circuit:Setting this
bit to'zero causes the CRC to be initialized to zero when
the Initialize CRC command (CRO bits 7-6) is performed.
Setting this bit to one causes the CRC to be set to all
ones.

Data Format [06- 05]
These bits specify the serial data format and enable the
corresponding encoder/decoder.
Bits 06-05

Format

00
01
10
11

NRZ
NRZI
FM1
FMO

With NRZ format, it is possible to decode Manchester
encoded data by setting the OPLL mode to FM (CR14
bits 07-05 = 110).

Auto Tx on Sync/Tx on Loop [04]
Bit 04 is valid only in the COP or BOP mode. In COP
mode, it synchronizes the receiver with the transmitter.
In BOP mode, it controls SOLC loop operation. The bit
is valid only when the Loop Enable state (CR10 bit
01
1) is selected.

In COP mode, bit 04 provides the Auto Tx on Sync
function to synchronize receiver and transmitter
operation.
(1) 04 = O. The Auto Tx on Sync function (CR10 bit
01 = 1) is disabled. Once synchronization is
established after this bit is set to 1, resetting the bit
to 0 does not affect synchronization.

(2) 04 = 1. If bit 01 (Loop Enable) is also set to one,
the transmitter is disabled and the receiver enters
the Hunt Phase. When the SYNC character is
detected, character synchronization is established,
the transmitter is enabled, and data transmission
can begin. The state of character synchronization
can be determined from the state of the Tx Sync/
GA Oetect bit (SR10 bit 01).
In BOP mode, bit 04 set to one enables or bit 04 set to
zero disables the Tx on Loop function. It is used for
data transmission during the SOLC loop operation.
(1) 04 = O. Once the AMPSC forms a loop and starts
transmission, bit 04 must be reset to zero. This
allows the CRC and flag to be automatically transmitted if a Tx Underrun/EOM occurs and allows the
AMPSC to be subsequently placed in Loop mode
with a 1-bit delay. Bit 04 must be reset before the
CRC transmission is completed.
(2) 04 = 1. When the Loop Enable bit (CR10 bit 01) is
set to one, SOLC Loop Operation mode is selected,
in which the RxO input is connected to the TxO
output within the AMPSC to form a loop. The GA
(Go Ahead) pattern detection is initiated. If the GA
pattern (11111110 = FEH) is detected, a 1-bit delay
is inserted between RxO and TxO and the GA
pattern detection is continued. At this point, the
transmitter remains disabled. The receiver can be
enabled at this point. Subsequently, if the GA
pattern is detected, the transmitter is enabled. At
this point, the GA pattern is automatically transformed into a flag so that any data in the Tx buffer
may be transmitted following the flag. Once transmission is started, bit 04 must be reset before the
end of the frame.

Idle Condition [03]
Valid only in BOP mode, bit 03 determines the type of
information to be transmitted following a closing flag
or completion of the Send Abort. If bit 03 is zero, flags
will be sent; if it is a one, continuous marks (ones) will
be sent.

li"ansmit Condition on Underrun [02]
Valid only in the BOP mode, bit 02 determines transmitter action when a Tx Underrun condition occurs. If
bit 02 is reset, Tx Underrun/EOM generates either the
CRC followed by a flag or just a flag depending on the
state of the Tx Underrun bit (SR1 bit 06) and the CRC
enable bit (CR5 bit 00). If the CRC is disabled ortheTx
underrun bit is a one, only flags are sent. Otherwise,
the CRC is sent followed by flags. If bit 02 is set, the
abort message is sent followed by flags.

2-45

~EC

pPD72001
Auto Tx/Loop Enable [01]

All Sent Interrupt Enable [02]

Valid only in the COP or BOP mode, bit 01 enables the
two types of loop operations that are set with bit 04.
This bit shou Id be set before the transmitter or receiver
is enabled.

Valid only in the Asynchronous or BOP mode, bit 02
enables interrupts generated by the All-Sent condition.

SYNC Character Length

Idle Detect Interrupt Enable [01]
Valid only in the BOP mode, bit 01 enables interrupts
caused by a change in the Idle Oetection condition.

[~O]

Valid only in the COP mode, bit 00 determines the
number of bits per SYNC character. Setting bit 00 to
zero gives a character length of 8 bits inMono-sync
and 16 bits in Bisync. With bit 00 = 1, the character
lengths are 6 and 12 bits, respectively.

Control Register CR11
Each bit of CR11 controls an E/S interrupt request
g.enerated by the AMPSC. An interrupt is set if the E/S
interrupts are enabled (CR1 bit 00 = 1). Forthe causes
of interrupts assigned to each, refer to the description
of SR1. Setting each bit to one enables it as a source of
interrupts.
.

BRG Interrupt Enable

[~O]

Bit 00 enables interrupts caused by one of the baud
rate generator/timers (BRG) counting down from one
to zero. Also, each of the BRGs must be enabled in
CR12 bits 03-02.

Control Register CR12
BRG Select for TRxC [07]
When BRG is selected as the source of the clock at the
TRxC pin (CR15 bits 01-00 = 10), and the TRxC pin is
set to output (CR15 bit 02 = 1), bit 07 selects TxBRG
(one state) or RxBRG (zero state).

Break/Abort/Go Ahead Interrupt Enable [07]
In Asynchronous and COP modes, bit 07 enables
interrupts at the beginning and end of each detected
break condition (a null character plus a framing error).
In BOP mode, when not in SOLC loop, bit 07 enables
interrupts at the beginning and end of each received
abort condition (seven or more consecutive 1-bits). In
SOLC loop mode, bit 07 also enables interrupts for
detecting the GA pattern (11111110 FEH).

l)'ansmitter Underrun/End of Message Interrupt
Enable [06]
Valid only in the COP or BOP mode, bit 06 enables
interrupts caused by transmitter underrun and Tx End
of Message detection.

Clear to Send Interrupt Enable [05]
Bit 05 enables interrupts caused by a change of state
on the CTS pin.

SYNC/Hunt Interrupt Enable [04]
Bit 04 enables interrupts caused by a change in the
SYNC/Hunt state.

Data Carrier Detect Interrupt Enable [03]
Bit 03 enables interrupts caused by a change of state
on the OCO pin.

BRG Select for OPLL [06]
Bit 06 selects the source (TxBRG or RxBRG) for the
OPLL. It is valid when the BRG is selected as the source
for the OPLL circuit (CR14 bits 07-05 = 100). Setting
bit 06 to one selects TxBRG and setting it to zero
selects RxBRG.

l)'ansmit BRG Interrupt Enable [03]
Bit 03 enables an E/S interrupt when the TxBRG
counts down from 1 to O. It is valid only when the BRG
IE bit is set (CR11 bit 00 = 1).

Receive BRGlnterrupt Enable [02]
Bit 02 enables an E/S interrupt when the RxBRG
counts down from 1 to O. It is valid only when the BRG
IE bit is set (CR11 bit 00 = 1).

l)'ansmit BRG Register Set [01]
Bit 01 is used to write the time constant value into the
TxBRG register. When 01 is set to one, the next two
bytes written to the AMPSC are assumed to be the time
constant val.ue. The lower byte is written in the first
write cycle and the upper byte in the second write
cycle. Bit 01 is automatically reset after the register is
loaded.
The ti,me constant value is calculated by using the
follovying formula,
.
Source clock frequency (Hz)
- 2
Time constant =
2 x (Oata clock rate (BPS))

2-46

tt¥EC
The data clock rate is the transmitted or received data
rate multiplied by the clock factor specified in CR4 bits
07-06.For example, if the system clock is selected as
the BRG source (CR14 bit D2 =1) at S MHz and the
BRG is the transmitter source (CR15 bits D4-D3 = 10)
with a clock factor of x16 (CR4 bits D7~D6 = 01) and
data rate of 9600 bits per second, the calculation would
be as follows.
_ 2 = 24.04 = 001S (hex)
S x 106
2 x (9600 x 16)

The loading sequence in hexadecimal for the TxBRG
would be; OC, 02, 1S, and 00.
If data is being written while the BRG is running, the
value will not be loaded into the BRG until it counts
down to zero.

pPD72001
this mode, the system clock (ClK) and the data clocks
are not circulated within the AMPSC.
The AMPSC enters the Standby mode automatically
after RESET. Writing OOH to CRO restores normal
operation. Table 6 lists the status of the pins in standby
mode.
During Standby mode, the WR and RD pins must be
held high and the CTS, DCD, and SYNC pins can not be
toggled. Read cycles that are conducted will not result
in data being driven onto the bus.
Table 6.

Pin Status In Standby Mode

Pin Symbol

Input/Output

Pin SlBtua

Input

Unchanged

Input

Unchanged

B/A

Input

Unchanged

C/D

Input

Unchanged'

Iq- Do

Input/Output

High impedance

INT

Output

Retains the current state

INTAK

Input

Unchanged

Control Register CR 13

PRI

Input

Unchanged

ll"ansmlt Data Length Counter Enable (01)

PRO

Output

Depends on PRI

Bit 01 enables the transmit data length counter
(TxDlC) that is used to determine the end of a transmitted frame and is only valid in BOP mode. When bit
01 is set to one, the TxDlC (SRS-SR9) is incremented
each time a Tx interrupt or DMA request is generated,
and the value is compared with the value in the transmit
length register (TxlR) (CRS-CR9). If the two values are
equal, Tx interrupts/DMA requests are masked.

DRQTxA

Output

Retains the current state

Receive BRG Register Set [DO)
Bit DO is used to write the count value into the RxBRG
register. It operates in the same manner as bit D1 for the
TxBRG register.

The subsequent Tx buffer empty interrupt is masked
and no interrupt or DMA request is made. This results
in a transmitter underrun. The AMPSC then sends the
CRC and a closing flag. After this the AMPSC issues an
external status interrupt with the All Sent bit setlf the
transmitter underruns and the transmit length values
do not match, then the MPSC sends an abort and sets
the Sending Abort bit (SRO bit D1). An E/S interrupt for
the All Sent is generated. The TxlC value (SRS-SR9)
can also be compared with the frame length to
determine if correct transmission occurred. After the
abort is sent, the TxDlC enable bit must be set to one
again in order to generate new Tx interrupts/DMA
requests.

Standby Mode Set [DO)
Setting bit DO to one places the AMPSC in the Standby
mode. This mode consumes very little power but saves
all internal register values. Greater power reduction is
possible by not toggling any of the AMPSC inputs. In

DRQRxA

Output

Retains the current state

DTRA/DRQTxB

Output

Retains the current state

DTRB/DRQRxB

Output

Retains the current state

TxDA.TxDB

Output

Retains the current state

RxDA, RxDB

Input

Unchanged

TRxCA, TRxCB

Input/Output

High impedance

STRxCA. XI1A

Input

Unchanged

STRxCB. XI1B

Input

Unchanged

XI2A/SYNCA

Input/Output

High impedance

XI2B/SYNCB

Input/Output

High impedance

RTSA,RTSB

Output

Retains the current state

CTSA,CTSB

Input

DCDA.DCDB

, Input

Unchanged
Unchanged.

Control Register CR14
DPLL Command [07-05)
These bits control the digital phase-locked loop
(DPLL). After reset, the DPLL is disabled, the STRxC
pin is selected as the source clock, and the NRZ1 mode
is selected. The DPll commands corresponding to the
eight states of bits D7-D5 are described below. '
No Operation [000]. This command causes no operation.
2-47

pPD72001
Enter Search [001]. This command causes the OPLL
to start the detection of edges in received data. Circuit
operation depends on the data format.
Reset Missing Clock [010]. Valid when FM mode is
selected, this command resets the Missing Clock bits
(SR10 bits 07-06).
Disable [011]. This command stops OPLL operation
and resets the Missing Clock bits.
Source BRG Select [100]. This command selects one
BRG as the clock sOurce forthe OPLL. Selection of
TxBRG or RxBRG is determined by CR12 bit 06 (BRG
Select for OPLL).
Source Xtal/STRxC Select [101]. This command is
used when the crystal-controlled oscillator or a clock
applied to the STRxC pin is to be the source clock for
the OPLL. Selection between the crystal OSC and the
STRxC input is specified by CR15 bit 07 (Xtal Select).
FM Mode [110]. This command is used when received
data is to .betreated as FM format. Setting the data
format to NRZ (CR10 bits 06-05 = 00) allows the
IlP072001 to decode Manchester encoded data.
NRZI Mode [111]. This command is used when received serial data is to be treated as NRZI format.

1i'ansmlt BRG Enable [00]
Setting bit 00 to one starts the TxBRG, which takes two
clocks to begin operating.
"

Control Register CR15
Crystal Select [071
If bit 07 is set to one, the on-chip crystal oscillator is
enabled and a crystal can be connected across pins XI1
and X12. If bit 07 is zero, the oscillator is disabled and
the pins become SYNC and STRxC.

Receive Clock Select [06-P5]
These bits select the source for the receive data clock.
Bits 06-05
00
01

Transmit Clock Select [04-03]
These bits select the source for the transmit data clock.
Bits 04-03

Local Self Test [04]

00
01

When bit 04 is set to one, the 'transmitter' output is
directly connected to the input of the receiver within
the AMPSC. Signals applied to the RxO pin. will be
ignored. In this mode, Autoenable cannot be used to
control the transmitter or receiver.

10
11

'Echo Loop Test [03]
When bit D3 is set to one, the RxO input pin is
connected to theTxO outputp.in in the AMPSC, so that
the received data is. echoed back to the remote sender
forUnetesting. The AMPSC transmitter is disabled.

BRG Source Select [02]
Bit .02 selects the source clock for the BRGs. The
selected source clock is shared by the TxBRG and the
RxBRG. If 02 is set to one, the system clock is used as
the source clock. If 02 is set to zero, the source clock
can either be the crystal oscillato((CR15 bit 07 = 1) or
the STRxCinput (CR15 bit 07!= 0).

. ' , '

Transmit Clock Source
Clock applied to STRxC pin
.Clock applied to TRxC pin (GR15
bits 02-00 are invalid.)
TxBRG output
OPLL output

TRxC Input/Output [02]
Bit 02 determines whether the TRxC pin will be an
input oran output. It is an input if bit 02 =0 or if the pin
is specified as an input bybits 06-05 or 04-03.

TRxC Source.Select [01-00]
When the TRxC pin is selected as an output, these bits
determine the output source. Refer to the preceding
descriptions for 06-05, 04-03, and 02 to determine
when the TRxCpin is an output.
Bits 01-00
00
01
10

ReceiveBRG Enable [01]
Setting bit 01to one starts the RxBRG, which takes two
clocks to begin operating.

Receive Clock Source
Clock applied to STRxC pin
Clock applied to TRxCpin (CR15
bits 02-00 are in'valid) . .
RxBRG output
OPLL output

Output at Pin

i'RXC

On-chip crystal oscillator.
. (if enabled)
Transmit data clock
TxBRG or RxBRG as selected by
CR12 bit 07
OPLL output

NEe

pPD72001

Status Register SRO

Short Frame Detect [D3]

End of Frame [D7]

Valid only in the BOP mode when Short Frame Detect
Enable is selected (CR1 bit 07 1), bit 03 is set when a
short frame is received and is reset by the Error Reset
command. A short frame has less than 32 bits between
two flags.

Valid only in the BOP mode, bit 07 indicates if reception
of a single frame is complete. When this bit is one, a
complete frame has been received and the CRC Error
bit (SRO bit 06) and Residue Code (SR3 bits 02-00) are
valid. The EOF condition causes a Special Rx Condition
interrupt. The Error Reset command resets this bit.

Detection of a short frame causes a Special Rx
Condition interrupt.

CRC/Framing Error [DS]

Transmit Buffer Empty [D2]

In the asynchronous mode, bit 06 indicates a framing
error. It is set to one if a zero is detected at the stop bit
position. It generates a Special Rx Condition interrupt.
Bit 06 is reset by an Error Reset command or reception
of a normal data byte.

A one in bit 02 indicates that the Tx buffer is empty and
can be loaded with the next Tx byte. Bit 02 is zero when
the Tx buffer contains a byte that has not been
transferred to the Tx shift register. Bit 02 is also zero in
the COP or BOP mode during CRC transmission.

In the COP or BOP mode, bit 06 set to one indicates a
CRC error. Bit 06 set to zero indicates no CRC error.

Sending Abort [D1]

In the COP mode, bit 06 is valid 20 bit times subsequent
to the last bit of the second CRC byte that is input at the
RxO pin, or 16 bit times after the second CRC byte is
transferred to the Rx buffer.
In the BOP mode, bit 06 is valid when the End-ofFrame bit (SRO bit 07) is set to one.
A CRC error does not generate a Special Rx Condition
interrupt.

Valid only in the BOP mode, a one in bit 01 indicates
that the AMPSC is sending an abort sequence.
Bit 01 is reset by the Error Reset command. Status
changes in bit 01 do not cause an interrupt.

Receive Data Available [DO]
A one in bit DO indicates the presence of valid received
data in the Rx buffer of the AMPSC.

Status Register SR1

Receive Overrun Error [D5]
A one in bit 05 indicates an Rx Overrun error. This error
occurs each time the AMPSC attempts to transfer an
additional byte from the Rx shift registerto the Rx FIFO
and the FIFO is already full.
An Rx Overrun error causes a Special Rx Condition
interrupt. The timing of the Rx Overrun Error and the
resulting Special Rx Condition interrupt will differ
depending on the setting of the Overrun Error INT bit
(CR1 bit 06). For more details, refer to the description
of control register CR1.
The Rx Overrun Error bit is reset by the Error Reset
command.

Parity Error [D4]
Valid only in the Asynchronous or COP mode when
parity is enabled (CR4 bit DO
1). A one in bit 04
indicates that a parity error occurred in a received byte.
The Parity Error bit is reset by the Error Reset command.

This register consists of external status bits that
indicate the causes of E/S interrupts. If the E/S INT is
enabled (CR1 bit DO
1) and an interrupt by an
specific E/S bit is enabled, the changes in the pertinent
E/S bit states are latched and cause an E/S interrupt. If
the E/S interrupt is disabled, changes in the E/S bit
status will not be latched.

Break/Abort/Go Ahead Detect [D7]
Bit 07 is valid only in the Asynchronous or BOP mode.
In the Asynchronous mode, a one in bit 07 indicates
that a Break (character in which the start, stop, and
data bits are all zeros) has occurred. Data received
during the Break (all zeros) are not loaded into the Rx
FIFO.
In the BOP mode, bit 07 indicates the reception of an
abort (seven or more consecutive ones). In SOLC Loop
mode, bit 07 indicates reception of the Go Ahead
message (11111110 = FEH).

In the All Receive INT-1 mode (CR1 bits 04-03 = 10), a
parity error causes a Special Rx Condition interrupt.

2-49

pPD72001
Thansmit Underrun/End of Message [06]

Idle Detect [01]

Valid only in the COP or BOP mode, a one in bit 06
indicates that all transmit data has been transferred
to the Tx shift register. CRC transmission, when the
transmitter underruns, can be controlled by manipulating this bit.

Bit 01 set to one indicates detection of the Idle state (15
or more consecutive 1's) in BOP mode. The one to zero
state transition ofthis bit does not generate an interrupt.

If CRC transmission is desired when the transmitter
underruns, bit 06 must be resettozero by the ResetTx
Underrun/EOM command bit (CRO bits 07-06 11).
Before this command is issued, the transmitter must be
enabled and at least one byte must have been transferred to the Tx buffer.

Bit DO set to one indicates that one of the BRG's has
counted down to zero. Bits 04~03 of SR3 determine
which BRG counted out. The one to zero state transition
of this bit does not generate an interrupt.

In the BOP mode, bit 06 is automatically reset to zero
when the first byte is transferred after transmission is
enabled. A status change from one to zero in this bit
does not cause an E/S interrupt.

This register indicates the value ofthe interrupt vector.
It can only be read from the B channel. The value
depends on the state of CR2A bit 06 (Status Affects
Vector bit). If bit 06 is zero, SR2B will always equal
CR2B. If bit 06 is one, the value of SR2B is modified by
the cause of the highest priority interrupt source within
the pP072001.

Clear To Send [05]
Bit 05 indicates the inverted state of the CTS pin. Any
change causes an interrupt.

Sync/Hunt [04]
In the Asynchronous or external sync COP mode, bit
04 indicates the inverted state of the SYNC pin.
In the internal sync COP or BOP mode, bit 04 indicates
the AMPSC synchronization state. A zero in bit 04
indicates that synchronization is established. A one
indicates that the AMPSC is in the Hunt Phase or that
the receiver is disabled.
Any change in state generates an interrupt.

Data Carrier Detect [03]
Bit 03 indicates the inverted state of the OCO pin. Any
.
change generates an interrupt.

All Sent [02]
Valid only in the Asynchronous or BOP mode. Bit 02
set to one indicates that all the transmit data within the
AMPSC has left the Tx shift register. The one to zero
state transition of this bit does not generate an interrupt.

2-50

BRG Zero Count

[~O]

Status Register SR2B

The bits of SR2B that are affected depend on the
Output Vector Type setting. Bits V4-V2 are affected for
Type A vectors, and bits V2-VO for Type B vectors. All
other bits remain unchanged. Table 7 gives the value
returned for the various types of interrupts.
7able 7.
V4. V2

Vector Values In SR2B
V3. VI

V2. VO

Channel

0
0
0
0

0
0
1
1

0
1
0
1

Tx buffer empty
External/status
Rx data available
Special Rx condition

Condition

1
1
1
1

0
0
1
1

0
1
0
1

Tx buffer empty
External/status
Rx data available
SpeCial Rx condition

When interrupts are available in the non-vectored
0), SR2B is read in order to
mode (CR2A bit 07
indicate to the pP072001 that interrupt service has
started. This clears the interrupt request (INT) and
prevents lower priority interrupts from being generated
until the End of Interrupt command (CRO) is issued.

t-fEC

pPD72001

Status Register SR3

Table 8.

TxBRG Zero Count [04]
Bit 04 is valid when TxBRG is enabled (CR14 bit DO =
1). A one in bit DO indicates that the TxBRG counted
down to zero. This bit in conjunction with the SR1 bit
~O, causes an external/status interrupt and is latched
on a transition from zero to one. The transition from
one to zero does not cause an interrupt.

RxBRG Zero Count [03]
Bit 03 is valid when RxBRG is enabled (CR14 bit 01 =
1). A one in bit 03 indicates that the RxBRG counted
down to zero. This bit functions in the same manner as
bit 04.

Residue Code [02-00]
Valid only in the BOP mode, bits 02-00 indicate the
number of valid bits in the last data byte received in a
frame. The meaning of these bits depends on the
number of bits per data byte. The previous character
refers to the last character read before the end of
frame, and so on. See Table 8. Figure 6 is an example of
a residue code of 000 and a character length of 8 bits. It
indicates that bits zero and one in the last byte are
valid.
Figure 6.

Example of ValidSifs in fhe I-Field (Residue
Code = 000)
MSB

pr.Ji~i~~117
Byte

LSB

02 01

Residue Codes

Previous Character
MSB
LSB

2nd Previous Character
MSB
LSB

8 Bits per Character

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
I"

0
1
0
1

C
C
C
C
C
C
C
C

C
C
C
C
C
C
C

C
C
C
C
C
C

X
X
X
X
X
X
X

C C 0
C C C
0 0 0
C C C
C 0 0
C C C

C
C
C
C
C
C

X
X
X
X
X
X

C
C
C
C
C

X
X
X
X
X

X X C
X X C
X X C
X X C
X X C

C C C C C C 0 0
C C 0 0 0 0 0 0
C C C C 0 0 0 0
0 0 0 0 0 0
C 0
0 0
0 0
0 0

C C C C
C 0 0 0
C C C 0
0 0 0 0

0 0
0 0
0 0

0 0
0 0

7 Bits per Character

X C C
X C C
X C C
I"
X C C
X C C
0
1
X C C
0
X C C
6 Bits per Character
X X C
0 0 0"
X X C
0 0 1
X X C
0 1 0
1 0 0
X X C
1 0 1
X X C
X X C
1 1 0
5 Bits per Character
X X X
0 0 0
X X X
0 0 1
X X X
0 1 0
1 0 0"
X X X
1 1 0
X X X
0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0

0 0 0 0 0 0
0 0 0
C 0 0
0 0 0
C C 0
0 0 0
0 0 0

0
0
0
0
0

0 0 0 0 0 0
C 0 0 0 0
C C C 0 0
C C C C 0
0 0 0 0 0
C C 0 0 0

C
C
C
C
C

0 0 0 0
0 0 0

C
C
C
C

C C 0
C C C
C 0 0

C=CRC bit
D = Valid data

1161151141131121 11 110 II.Field

X= Invalid

P~:~:y~: I C1 0lC1 1 IC121C131C1 4IC1;!liJ ~~i~~d

* = No residue (boundary of the last received data matches the

boundary between one byte and the CRC).

prev~:t~1

cal C9IC10Ic"IC12IC13IC14IC15IcRc.Field

F~~~! I Co I C1
,
,

10··· .17

I C21 C31 C41 C51 C61 C71

Third
Previous

Second
Previous

Byte

10· ••• 17

,
I

110 : 11 ICRC 1I

Byte
CRC 1

Final

CRC 2

Byte

Bytes received from the left
49M-000154

2-51

NEe

pPD72001
Status Register SR4A

Two Clocks Missing [06]

Each bit of this register indicates whether or not a
corresponding cause of interrupt exists within the
AMPSC. A bit is set to one when its matching interrupt
is being serviced or if a lower-priority interrupt is
pending during the servicing of a higher-priority interrupt. Otherwise, it is zero,. Although this register can
be read only on channel A, its function is shared by
both channels.
Bit
Chan
Oescription

Bit 06 indicates that two consecutive transitions in the
received data were missed.

-07
06
05
04
03
02
01
00

--A

B
A
A

A
B

B
B

Special Rx condition; INT pending
Special Rx condition; INT pending
Rx INT pending
Tx INT pending
E/S INT pending
Rx INT pending
Tx INT pending
E/S INT pending

Status Register SR8
Valid only in the BOP mode, bits 07-00 of SR8 are the
low order byte of the Tx Oata Length counter. Register
SR8 is normally used to determine ifframe transmission
completed correctly. If the value of CR8/CR9 does not
equal the value of SR8/SR9 when the transmitter
underruns, the AMPSC automatically transmits an
Abort. Registers SR8 and SR9 are cleared by a reset or
when the TxOLC enable bit (CR13 bit 08) is set to one.

Status Register SR9
Valid only in the BOP mode, bits 07-00 of SR9 are the
high order byte of the Tx Oata Length counter. Registers
SR8 and SR9 are used in conjunction with each other.

Status Register SR10

Sending on Loop [04]
Bit 04 set to the one state indicates that the AMPSC is
in the SOLC loop connection and is transmitting. It i,s
valid only in the BOP mode when the SOLC Loop is
selected (CR10 bits 04, 01 = 1,1).

Tx Sync/On Loop [01]
Bit 01 is valid only in the COP or BOP mode. In the
COP mode, a one in bit 01 indicates that the transmitter
and receiver are synchronized (SYNC character
detection on the receiver has been completed) after
both the Auto Tx on Sync and the"bit 04 Enable bits
(CR10 bits 04,01) were reset, and transmission is
enabled for the device.
In the BOP mode, a one in bit 01 indicates that a GA
pattern was detected and a 1-bit delay was inserted
between the RxO input and the TxO output. Bit 01
remains a one during the time that the SOLC loop is
formed. When 01 is zero, the TxD and RxO lines are
connected without the delay in loop mode. Bit 01 is
also zero when the AMPSC is not in the loop mode.

Status Register SR 11 .
This register directly indicates the value set in CR11 for
interrupt enables. The host processor can use SR11 to
read the interrupt enable states for the variousjnterrupt
sources within the AMPSC.

Status Register SR12
This register indicates the lower 8 bits (bits 7-0) of the
value set in the Rx BRG.

One Clock Missing [07]
This bit indicates if a transition has been detected in
the received data. It is valid when the FM data format is
selected and the OPLL is in operation. With FM data
format, a transition (riSing orfalling) must occur within
one bit time at a bit boundary or center. The OPLL uses
this transition as a reference for clock generation.

Status Register SR13

If no transitions occur, the OPLL clock generation may
not operate properly. The OPLL detects transitions
every 2 bits.

This register indicates the lower 8 bits (bits 7-0) of the
value set in the Tx BRG.

A one in bit 07 indicates no transition was detected in
the received data. This bit is latched, and is reset by the
Reset Missing Clock command (CR14 bits 07-05 =
010) or the Enter Search command (CR14 bits 07-05
001).

2-52

This register indicates the upper8 bits (bits 15-8) of the
value set in the Rx BRG.

Status Register SR14

Status Register SR15
This register indicates the upper 8 bits (bits 15-8) of the
value set in the Tx BRG.

GRAPHICS CONTROLLERS

3-1

NEe

Graphics Controllers
Section 3
Graphics Controllers
,d'0722OA
High-Performance Graphics Display Controller

3-3

,d'072020
CMOS Graphics Display Controller

3-31

,d'072022
Intelligent Display Processor

3-57

"P072120
Advanced Graphics Display Controller

"P072123
Advanced Graphics Display Controller II

3-2

3-153

t-IEC

JlPD7220A
High·Performance
Graphics Display Controller

NEG Electronics Inc.

Description

Features

The pPD7220A high-performance graphics display
controller (HGDC) is an intelligent microprocessor
peripheral designed to be the heart of a high-performance raster scan computer graphics and character
display system. Positioned between the video display
memory and the microprocessor bus, the HGDC
performs the tasks needed to generate the raster
display and manage the display memory. Processor
software overhead is minimized by the HGDC's sophisticated instruction set, graphics figure drawing, and
DMA transfer capabilities. The display memory supported by the HGDC can be configured in any number
of formats and sizes up to 256K 16-bit words. The
display can be zoomed and panned, while partitioned
screen areas can be independently scrolled. With its
light pen input and multiple controller capability, the
HGDC is ideal for advanced computer graphics
applications.

o Microprocessor interface

For a more detailed description of the HGDC's
operation, please refer to the 722017220A design
manuals.

o
o
o
o
o
o

System Considerations
The HGDC is designed to work with a general purpose
microprocessor to implement a high-performance
computer graphics system. Through the division of
labor established by the HGDC's design, each of the
system components is used to the maximum extent
through a six-level hierarchy of simultaneous tasks. At
the lowest level, the HGDC generates the basic video
raster timing, including sync and blanking signals.
Partitioning areas on the screen and zooming are also
accomplished at this level. At the next level, video
display memory is modified during the figure drawing
operations and data moves. Third, display memory
addresses are calculated pixel by pixel as drawing
progresses. Outside the HGDC at the next level,
preliminary calculations are done to prepare drawing
parameters. At the fifth level, the picture must be
represented as a list of graphics figures drawable by
the HGDC. Finally, this representation must be
manipulated, stored, and communicated. By handling
the first three levels, the HGDC takes care of the highspeed and repetitive tasks required to implement a
graphics system.

NECEL-000063

o
o
o
o

DMA transfers with 8257- or 8237-type
controllers
- FIFO command buffering
Display memory interface
- Up to 256K words of 16-bits
- Read-modify-write (RMW) display memory
cycles as fast as 500 ns
- Dynamic RAM refresh cycles for nonaccessed
memory
Light pen input
Drawing hold input
External video synchronization mode
Graphic mode
- Four megabit, bit-mapped display memory
Character mode
- 8K character code and attributes display
memory
Mixed graphics and character mode
- 64K if all characters
- 1 megapixel if all graphics
Graphics capabilities
- Figure drawing of lines, arc/circles, rectangles,
and graphics characters in 500 ns per pixel
- Display 1024-by-1024 pixels with 4 planes of
color or grayscale
- Two independently scrollable areas
Character capabilities
- Auto cursor advanced
- Four independently scrollable areas
- Programmable cursor height
- Characters per row: up to 256
- Character rows per screen: up to 100
Video display format
- Zoom magnification factors of 1 to 16
- Panning
- Command-settable video raster parameters
NMOS technology
Single +5 V power supply
DMA capability
_. Bytes or word transfers
- 4 clock periods per byte transferred
On-chip pull-up resistor for VSYNC/EXT, HSYNC
and DACK, and a pull-down resistor for LPEN/DH

3-3

~EC

pPD7220A
Ordering Information

Pin Identification

Package
Type

Max Frequency
01 OperlUon

pPD7220AD

4O-pin ceramic DIP

6MHz

pPD7220AD-1

4O-pin ceramic DIP

7 MHz

pPD7220AD-2

4O-pin ceramic DIP

8MHz

Pan
Number

Pin Configuration

Pin
No.

Symbol

2xWCLK

DBIN

Display memory read input flag

HSYNC

Horizontal video sync output

V/EXT SYNC

Vertical video sync output or external
VSYNC input

BLANK

CRT blanking output

2xWCLK

ALE

Address latch enable output

DBIN

DRO

DMA request output

V/EXTSYNC

DACK

DMA acknowledge input

BLANK

Read strobe input for microprocessor
interface

Write stobe input for microprocessor
interface

Address select input for microprocessor
interface

12-19

DBo-DB7

Bidirectional data bus to host microprocessor

GND

Ground

LPEN/DH

Light pen detect input drawing hold
input

22-34

ADo-AD12

Address data lines to ~isplay memory

35-37

AD13-AD15

Utilization varies with mode of
operation

A16

Utilization varies with mode of
operation

A17

Utilization varies with mode of
operation

Vee

+5 V ±10% power supply

HSYNe

ALE
DRQ

DACK

iii'i
WR

DB,

AD,
AD,

DB,
DB,

AD,
AD,

DB,
DB,

AD,
AD,

DB,
DB,

AD,
AD,

Character Mode Pin Utilization
Pin
No.

Symbol

Function

35-37

AD13-AD15

AD16

Line counter bit 3 output

AD17

Cursor output and line counter bit 4

Line counter bits 0 to 2 outputs

Graphics Mode Pin Utilization
Pin
No.

Mixed Mode Pin Utilization
Pin

Symbol

Funelion
Address and data bits 13 to 15
Address bit 16 output

No.

Symbol

35-37

AD13-AD15

Address and data bits 13 to 15

A16

Attribute blink and clear line counter
output

A17

Cursor and bit-map area flag output

3-4

Funellon
Clock input

Funellon

Address bit 17 output

t-{EC

pPD7220A

Pin Functions

RD [Read Strobe]

2xWCLK [Clock Input]

The host CPU clears the RD input to 0 when reading
the internal status and FIFO registers.

2xWCLK is the clock input.

DBIN [Data Bus Input Enable]
The DBIN output indicates the time the AGDC will
accept data read from display RAM during readmodify-write (RMW) cycles.

HSYNC [Horizontal Sync]
The HSYNC output indicates the time the CRT's beam
is to start its retrace back to the left side of the screen.

V/EXT SYNC [Vertical SYNC Output/External
Sync Input]
The AGDC can be programmed to output a vertical
sync signal at the start of the return of the CRT's beam
from the lower right of the screen to the upper left
during vertical retrace. The AGDC may also be
programmed to accept an external sync input when
used in slave mode.

BLANK [Blank]
BLANK is output during inactive display times (horizontal and vertical retrace) of the CRT and during a
read-modify-write memory cycle when in flash mode.

WR [Write Strobe]
The host CPU clears WR to 0 when writing to the
internal command and parameter registers.

DBO-DB7 [Data Bus]
DBo-DB7, the 8-bit, three-state bidirectional data bus
transfers data to and from the host CPU via the system
bus.

LPEN/DH [LightPen/Drawing Hold]
The LPEN/DH input can be programmed as either a
light pen input or drawing hold input. The drawing hold
input halts all read-modify-write operations.

ADO-AD17 [Address and Data Lines]
ADo-AD17 are address and data lines to display
memory. AD13-AD17 functions vary with the mode of
operation of the ADGC. ThepPD722017220A Graphics
Display Controller User's Manual describes these
functions and modes of operation.

Vee [Power Supply]
Vee is the +5 V power supply input.

ALE [Address Latch Enable]
The falling edge of ALE indicates the first clock cycle of
a display memory cycle and the availability of the
memory address on pins ADo-AD17. ALE and external
logic can generate display memory control signals.

AO [Address Bit 0]
Ao is the address select input for the microprocessor
interface.

GND [Ground]
GND is ground potential.

Block Diagram
HSVNC
V/EXTSYNC
BLANK

DREQ

DB-Oto7 8

ALE
il8ijij

A1 [Address Bit 1]
The A1 input selects registers when reading or writing
to the AGDC.

DACK [DMA Acknowledge]
DACK is the DMA acknowledge input handshake line
that directly interfaces to the pPD8257 or pPD8237
DMA controller.

A-17
A-,.
AD·15
Parameter

DRQ [DMA Request]
DRO is the DMA request output handshake line that
directly interfaces to the pPD8257 or pPD8237 DMA
controller.

Ao-14
Ao-13

RAM
16 x 8

+5Vo-GNOo---2xWCLK<:r-

LPEN

3-5

ftiEC

pPD7220A
HGDC Components
Microprocessor Bus Interface
Control of the HGDC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The
status register is readable at any time. Access to the
FIFO buffer is coordinated through flags in the status
register and operates independently of the various
internal HGDC operations, due to the separate data
bus connecting the interface and the FIFO buffer.

Applications
NEC Electronics Inc. recently learned that applicaion of the pPD7220 or pPD7220A Graphics Display
Controller in conjunction with other non-NEC
Electronics Inc. equipment to achieve panning and
zooming capabilities may infringe U.S. Patents
4,197,590 and RE 31,200 held by CADTRAK CORPORATION of Sunnyvale, Ca. Neither the pPD7220 nor
the pPD7220A Graphics Display Controllers by themselves infringe CADTRAK's patents. CUSTOMERS OF
NEC ELECTRONICS INC. ARE HEREBY GIVEN
NOTICE OF THE EXISTENCE OF THE CADTRAK
PATENTS. USER'S ARE RESPONSIBLE FOR INSURING THAT THEIR SYSTEM DESIGN, MANUFACTURE AND RESULTING PRODUCT DO NOT
VIOLATE ANY APPLICABLE PATENTS.

Command Processor
The contents of the FIFO are interpreted by the
command processor. The command bytes are decoded,
and the succeeding parameters are distributed to their
proper destinations within the HGDC. The command
processor yields to the bus interface when both access
the FIFO simultaneously.

DMA Control
The DMA control circuitry in the HGDC coordinates
transfers overthe microprocessor interface when using
an external DMA controller. The DMARequest and
Acknowledge handshake lines directly interface with a
pPD8257 or pPD8237 DMA controller, so that display
data can be moved between the microprocessor
memory and the display memory.

3-6

Parameter RAM
The 16-byte RAM stores parameters that are used
repetitively during the display and drawing processes.
In character mode, this RAM holds four sets of
partitioned display area parameters; in graphics mode,
the drawing pattern and graphics character take the
place of two of the sets of parameters.

Video Sync Generator
Based on the clock input, the sync logic generates the
raster timing signals for almost interlaced, noninterlaced, or "repeat field" interlaced video format.
The generator is programmed during the idle period
following a reset. In video sync slave mode, it
coordinates timing between multiple HGDCs.

Memory Timing Generator
The memory timing circuitry provides two memory
cycle types: a two-clock period refresh cycle and the
read-modify-write (RMW) cycle, which takes four clock
periods. The memory control signals needed to drive
the display memory devices are easily generated from
the HGDC's ALE and DBIN outputs.

Zoom & Pan Controller
Based on the programmable zoom display factor and
the display area entries in the parameter RAM, the
zoom and pan controller determines when to advance
to the next memory address for display refresh and
when to go on to the next display area. A horizontal
zoom is produced by slowing down the display refresh
rate while maintaining the video sync rates. Vertical
zoom is accomplished by repeatedly accessing each
line a number of times equal to the horizontal repeat.
Once the line count for a display area is exhausted, the
controller accesses the starting address and line count
of the next display area from the parameter RAM. The
system microprocessor, by modifying a display area
starting address, can pan in any direction, independently of the other display areas.

Drawing Controller
The drawing processor contains the logic necessary to
calculate the addresses and positions of the pixels of
the various graphics figures. Given a starting point and
the appropriate drawing parameters, the drawing
controller needs no further assistance to complete the
figure drawing.

NEe

pPD7220A

Display Memory Controller

HCDC Commands Summary

The display memory contoller's tasks are numerous.
Its primary purpose is to multiplex the address and
data information in and out of the display memory. It
also contains the 16-bit logic unit used to modify the
display memory contents during RMW cycles, the
character mode line counter, and the refresh counter
for dynamic RAMs. The memory controller apportions
the video field time between the various types of
cycles.

Video Control Commands
1. RESET1

2. RESET2

3. RESET3

Light Pen Deglitcher/Drawing Hold
Only if two rising edges on the light pen input occur at
the same point during successive video fields are the
pulses accepted as a valid light pen detection. A status
bit indicates to the system microprocessor that the
light pen register contains a valid address. If this input
is held high for a period greater than four 2xWCLK
cycles, drawing execution is halted when bit 7 of P5 of
the SYNC command is set.

Programmer's View of HGDC

Commands to the HGDC take the form of a command
byte followed by a series of parameter bytes as needed
for specifying the details of the command. The
command processor decodes the commands, unpacks
the parameters, loads them into the appropriate
registers within the HGDC, and initiates the required
operations.
The commands available in the HGDC can be organized
into five categories as described in the following
section.
HGDC Microprocessor Bus Interface Registers
READ

1. START

3. BLANK2

4. ZOOM

5. CURS
6. PRAM

7. PITCH

I I

Command Into FIFO

I I

Ends idle mode and unblanks the
display.
Controls the blanking and
unblanking of the display, along
with video resynchronization.
Controls the blanking and
unblanking of the display. Does not
blank the display.
Specifies zoom factors for the
display and graphics characters
writing.
Sets the position of the cursor in
display memory.
Defines starting addresses and
lengths of the display areas and
specifies the eight bytes for the
graphics character.
Specifies the width of the X
dimension of display memory.

Drawing Control Commands
1. WDAT

Parameter Into FIFO

FlfQRead
1

Display Control Commands

WRITE

Status Register

6. CCHAR

2. BLANK1

The HGDC occupies two addresses on the system
microprocessor bus through which the HGDC's status
register and FIFO are accessed. Commands and
parameters are written into the HGDC's FIFO and are
differentiated based on address bit Ao. The status
register or the FIFO can be read as selected by the
address line.

4. SYNC
5. VSYNC

Resets the GDC to its idle state.
Resychronizes video timing. Blanks
the display.
Resets the HGDC to its idle state.
Does not resynchronize video
timing. Blanks the display.
Resets the HGDC to its idle state.
Does not resynchronize video
timing. Does not blank the display.
Specifies the video display format.
Selects master or slave video
synchronization mode.
Specifies the cursor and character
row heights.

2. MASK
3. FIGS
4. FIGD
5. GCHRD

Writes data words or bytes into
display memory.
Sets the mask register contents.
Specifies the parameters for the
drawing controller.
Draws the figure as specified
above.
Draws the graphics character into
display memory.

3-7

pPD7220A
Data Read Commands
1. RDAT
Reads dala words or byles from
display memory.
.
2. CURD
Reads the cursor pOSition.
3. LPFiD
Reads the light pen address.
DMA Control Commands
1. DMAR
Requests a DMA read transfer.
2. DMAW
Requests a DMA write transfer.

SR-7: Light Pen Detect
When this bit is set to 1, the light pen address (LAD)
register contains a deglitched value that the system
microprocessor may read. This flag is reset after the
3-byte LAD is moved into the FIFO in response to the
light pen read command.'
..

SR-6: Horizontal Blank ActlveNertical
Blanle Active
A 1 value for this flag signifies that horizontal retrace
blanking orvertical retrace blanking is currently underway aependent on the status of the VH bit in SYNC or
the RESETx parameter 6.

SR-5: Vertical Sync
Vertical retrace sync occurs while this flag is a 1. The
vertical sync flag coordinates display format modifying
commands to the blanked interval surrounding vertical
sync. This eliminates display disturbances.

SR-4: DMA Execute
This bit is a 1 during DMA datatranfers.

SR-3: Drawing In' Progress
While the HGDC is drawing a graphicsJigure, this
status bit is a 1.
Status Register (SR)
7

I1
3-8

1 •

This bit and the FIFO-full flag coordinate system
microprocessor accesses with the HGDC FIFO. When
it is 1, the Empty flag ensures that all the commands
and parameters previously sent to the HGDq have
been interpreted.

SR-1: FIFO Full
A 1 at this flag indicates a full FIFO in the HGDC. A 0
ensures that there is room for at least one byte: This
flag needs to be checked before each write into the
• .
HGDC.

Status Register Flags

SR-2: FIFO Empty

11 1

~~~:~

Drawing in Progress
DMAExecute

Yeftlcal Sync ACtive
Horizontal Blank ActiveJ

Vertical Blank Active
Light Pen Detect

SR-O: Data Ready
When this flag is a 1, it indicates that a byte is avaiiable
to be read by the system microprocessor. This bitmust
.tie test~d before each read. operation. It drops to a 0
while the data is transferred from the' FIFO into the
microprocessor interface data register.

FIFO Operation & Command Protocol
The first-in, first-out buffer (FIFO) in the HGQC handles
the command dialogue with the system microprocessor. This flow of iriformationuses a half-duplex
technique, in which the single 16-locatioh FIFO is used
for both directions of data movement, one direction at
a time. The FIFO's direction is controlled by the system
microprocessor through the HGDC's command set.
The host microprocessor coordinates theSe transfers
by checking the appropriate status register bits.
The command protocol used by the HGDC requires
differentiation of the first byte of a command sequence
fromthesucceeding bytes. The first byte contains the
operation code and the remaining bYtes carry parameters. Writing into the HGDC causes the FIFO to
store a flag value alongside the data byte 'to signify
. whether the byte was written into the command or the
parameter address. The c.ommandprocessor in the
HGDC tests this bit as it interprets the entries. in the
FIFO.
The receipt of a command byte by the command
processor marks the end of any previous operation.
The number of parameter byteS supplied with a
com'mand is cut short by the receipt of the next
command byte. Aread operation from the HGDC to the
microprocessor can be terminated
any time by the
'
next command.

fttfEC
The FIFO changes direction under the control of the
system microprocessor. Commands written into the
HGDC always put the FI FO into write mode if it was not
in it already. If it was in read mode, any read data in the
FIFO at the time of the turnaround is lost. Commands
which require an HGDC response, such as RDAT,
CURD and LPRD, putthe FIFO into read mode after the
command is interpreted by the HGDC's command
processor. Any commands and parameters behind the
read-evoking command are discarded when the FIFO
direction is reversed.

Read-Modify-Write Cycle
Data transfers between the HGDC and the display
memory are accomplished using a read-modify-write
(RMW) memory cycle. The four-clock period timing of
the RMW cycle is used to 1. output the address, 2. read
data rom the memory, 3. modify the data, and 4. write
the modified data back into the initially selected
memory address. This type of memory cycle is used for
all interactions with display memory including DMA
transfers, except for the two-clock period display and
RAM refresh cycles.
The operations performed during the modify portion of
the RMW cycle merit additional explanation. The
circuitry in the HGDC uses three main elements: the
Pattern register, the Mask register, and the 16-bit Logic
unit. The Pattern register holds the data pattern to be
moved into memory. It is loaded by the WDAT parameters or, during drawing, from the parameter RAM.
The Mask register contents determine which bits of the
read data will be modified. Based on the contents of
these registers, the Logic unit performs the selected
operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.
The Pattern register contents are ANDed with the Mask
register contents to enable the actual modification of
the memory read data, on a bit-by-bit basis. For
graphics drawing, one bit at a time from the Pattern
register is combined with the Mask. When ANDed with
the bit set to a 1 in the Mask register, the proper single
pixel is modified by the Logic unit. Forthe next pixel in
the figure, the next bit in the Pattern register is selected
and the Mask register bit is moved to identify the pixel's
location within the word. The Execution word address
pointer register, EAD, is also adjusted as required to
address the word containing the next pixel.

pPD7220A
In character mode, all of the bits in the Pattern register
are used in parallel to form the respective bits of the
modify data word. Since the bits of the character code
word are used in parallel, unlike the one-bit-at-a-time
graphics drawing process, this facility allows any or all
of the bits in a memory word to be modified in one
RMW memory cycle. The Mask register must be loaded
with ones in the pOSitions where modification is to be
permitted.
The Mask register can be loaded in either of two ways.
In graphics mode, the CURS command contains a 4-bit
dAD field to specify the dot address. The command
processor converts this parameter into the 1-of-16
format used in the Mask register for figure drawing. A
full 16-bits can be loaded into the Mask register using
the MASK command. In addition to the character mode
use mentioned above, the 16-bit MASK load is convenient in graphics mode when all of the pixels of a
word are to be set to the same value.
The Logic unit combines the data read from display
memory, the Pattern register, and the Mask register to
generate the data to be written back into display
memory. Anyone of four operations can be selected:
REPLACE, COMPLEMENT, CLEAR or SET. In each
case, if the respective Mask bit is 0, that particu lar bit of
the read data is returned to memory unmodified. If the
Mask bit is 1, the modification is enabled. With the
REPLACE operation, the Pattern register data simply
takes the place of the read data for modification
enabled bits. For the other three operations, a 0 in the
modify data allows the read data bit to be returned to
memory. A 1 value causes the specified operation to be
performed in the bit positions with set Mask bits.

Figure Drawing
The HGDC draws graphics figures at the rate of one
pixel per read-modify-write (RMW) display memory
cycle. These cycles take four clock periods to complete.
At a clock frequency of 8 MHz, this is equal to 500 ns.
During the RMW cycle the HGDC simultaneously
calculates the address and position of the next pixel to
be drawn.
The graphics figure drawing process depends on the
display memory addressing structure. Groups of 16
horizontally adjacent pixels form the 16-bit words
which are handled by the HGDC. Display memory is
organized as a linearly addressed space of these
words. Addressing of individual pixels is handled by
the HGDC's internal RMW logic.

3-9

NEe

pPD7220A
During the drawing process, the HGDC finds the next
pixel of the figure which is one of the eight nearest
neighbors of the last pixel drawn. The HGDC assigns
each of these eight directions a number from 0 to 7,
starting with straight down and proceeding counterclockwise.
Figure drawing requires the proper manipulation of
the address and the pixel bit position according to the
drawing direction to determine the next pixel of the
figure. To move to the word above or below the current
one, it is necessary to subtract or add the number of
words per line in display memory. This parameter is
called the pitch. To move to the word to either side, the
Execute word address cursor, EAD, must be incremented or decremented as the dot address painter bit reaches
the LSB or the MSB of the Mask register. To move to a
pixel within the same word, it is necessary to rotate the
dot address pointer to the rightor left. The table below
summarizes these operations for each direction.

Whole word drawing is useful for filling areas in
memory with a single value. By setting the Mask
register to all 1s with the MASK command, both the
LSB and MSB of the dAD will always be 1, so that the
EAD value will be incremented or decremented for
each cycle regardless of direction. One RMW cycle will
be able to affect all 16 bits of the word for any drawing
type. One bit in the Pattern register is used per RMW
cycle to write all the bits of the word to the same value.
The next Pattern bit is used for the word, etc.
Forthe various figures, the effect of the initial direction
upon the resulting drawing is shown below:

Oir
000

001

010

Oir

Operations to Address the Next Pixel

000

EAD- P- EAD

001

EAD - P -,+ EAD
dAD (MSB) = tEAD - 1 -

= tEAD -

011

010

dAD (MSB)

011

EAD - P - EAD
dAD (MSB) = tEAD- 1 -

1 -+ EAD dAD -

100

EAD - P - EAD

101

EAD - P- EAD
dAD (LSB) == tEAD - 1 -

110

dAD (LSB)

111

EAD- P- EAD
dAD (LSB) = tEAD - 1 -

= tEAD -

EAD dAD - LR

101

EAD dAD -

LR
110

EAD dAD- RR

1 -+ EAD dAD EAO dAD -

RR
RR

Note:

3-10

~#
~

A
V
('

P = Pitch, LR = Left Rotate, RR = Right Rotate, EAD = Execute Word
Address, and dAD = Dot Address stored in the Maskregister.

Drawing Directions

100

Line

111

Arc

r~>,7
~

i //
/'
"

L>
C~"

/:J,

~ C
"

';,,',)

,
,-

Character SlanlChar Rectangle

Ull1J1J

[]

DMA

N\i
~

[]

~ .~ CJ
fUU1l1

~
~

~ ~,

Note that during line drawing, .the angle of the nne may
be anywhere within the shaded octant defined by the
DIR value. Arc drawing starts in the direction initially
specified by the DIR value and veers into an arc as
drawing proceeds. An arc may be up to 45° in length.
DMA transfers are done on word boundaries only, and
follow the arrows indicated in the table to find successive word addresses. The slanted paths for DMA
transfers indicate the HGDC changing both the X andY
components of the word address when moving to the
next word. It does not follow a 45° diagonal path by
pixels.

ttiEC

pPD7220A
Symbol Definitions

Drawing Parameters
In preparation for graphics figure drawing, the HGDC's
Drawing processor needs the figure type, direction and
drawing parameters, the starting pixel address, and the
pattern from the microprocessor. Once these are in
place within the HGDC, the Figure Draw command,
FIGD, initiates the drawing operation. From that pOint
on, the system microprocessor is not involved in the
drawing process. The HGDC Drawing controller coordinates the RMW circuitry and address registers to
draw the specified figure pixel by pixel.
The algorithms used by the processor for figure
drawing are designed to optimize its drawing speed. To
this end, the specific details about the figure to be
drawn are reduced by the microprocessor to form
conducive to high-speed address calculations within
the HGDC. In this way the repetitive, pixel-by-pixel
calculations can be done quickly, thereby minimizing
the overall figure drawing time. The. table below summarizes the parameters.
Drawing

Type

Initial
Vallie (1)

-1

Line

ltill

Arc (2)

rsin

r-l

2(r-l)

-1

rsin 81

A-I

B-1

-1

A~1

Area fill

B-1

Graphic
character

B-1

Rectangle

2IAOI-IAII 2(jAO I-IAII)

21AOI

(3)
Read &
write data

W-l

OMAW

0-1

C-l

OMAR

0-1

C-l

' (C-l)/2/t

Note:
All numbers are shown in base 10 fdr convenience. The HGOC
accepts base 2 numbers (2's complement notation) where
appropriate.
(1) Initial values for the various parameters remain as each drawing
process.ends.
(2) Circles are drawn with 8 arcs, each of which span 45°, so that sin
= 1/";2 and sin 8 = O.
(3) Graphic characters are a special case of bit-map area filling in
which B and A :0:; 8. If A = 8 there is no need to load 0 and 02.

-1 = All ONES value.
= No parameter bytes sent to HGDC for this
parameter.
al = The larger at ax or ay.
aD = The smaller at ax or ay.
r = Radius of curvature, in pixels.
t/J = Angle from major axis to end of the arc.
t/J:5 45°.
8 = Angle from major axis to start of the arc.
8:5 45°.
t = Round up to the next higher integer.
l = Round down to the next lower integer.
A = Number of pixels in the initially specified
direction.
B = Number of pixels in the direction at right
angles to the initially specified direction.
W = Number of words to be accessed.
C = Number of bytes to be transferred in the
initially specified direction. (Two bytes per
word if word transfer mode is selected.)
o = Number of words to be accessed in the
direction at right angles to the initially
specified direction.
DC = Drawing count parameter which is one less
than the number of RMW cycles to be
executed.
OM = Dots masked from drawing durihg arc
drawing.
t. == Ne,eded only for word reads.

Graphics Character Drawing
Graphics characters can be drawn into display memory
pixel by pixel. Th,e up to 8-by-8 character display is
loaded into the HGDC's parameter RAM by the system
microprocessor; Consequently, there are no limitations
on the character set used. By varying the drawing
parameters and drawing direction, numerous drawing
options are available. In area fill applications, a
character can be written into display memory as many
times as desired without reloading the parameter RAM.
Once the parameter RAM has been loaded with up to
eight graphics character bytes by the appropriate
PRAM command, the GCHRD command can be used
to draw the bytes into display memory starting at the
cursor. The zoom magnification factor for writing, set
by the ZOOM command, controls the size of the
character written into the display memory in integer
multiples of 1 through 16. The bit values in the PRAM
are repeated horizontally and vertically the number of
times specified by the zoom factor.

3-11

tt(EC

pPD7220A
The movement of these PRAM bytes to the display
memory is controlled by the parameters of the FIGS
command.
.
Based on the specified height and width of the area to
be drawn, the parameter RAM is scanned to fill the
required area.
For an 8-by-8 graphics character, the first pixel drawn
uses the LSB of RA-15, the second pixel uses bit 1 of
RA-15, and soon, until the MSB of RA-J5 is reached.
The HGDC jumps to the corresponding bit in RA-14 to
continue the drawing. The progression then advances
toward the LSB of RA-14. This snaking sequence is
continued for the other 6 PRAM bytes. This progression
matches the sequence of display memory addresses
calculated by the drawing processor .as shown above.
If the area is narrower than 8 pixels wide, the snaking
will advance to the next PRAM byte before the MSB is
reached. If the area is less than a lines high, fewer bytes
in the parameter RAM will be scanned. If the area is
larger than a by 8, the HGDC will repeat the contents of
the parameter RAM in two dimensions, as required to
fill the area with the a-by-a mosaic. (Fractions of the
a-by-a pattern will be used to fill areas which are not
multiples of a. by a.)

The other use for the PRAM contents is to supply the
pattern for figure drawing when in a bit-mapped
graphics 'area or mode. In these situations, PRAM
bytes a through 16 are reserved for this patterning
information. For line, arc, and rectangle drawing (linear
figures) locations a and 9 are loaded into the Pattern
register to allow the HGDC to draw dotted,dashed, etc.
lines. For area filling and graphics bit-mapped character drawing, locations a through 15 are referencedfor
the pattern or character to be drawn.'
Details ofthe bit assignments are shown forthe various
modes of operation.

Character Mode

Length of Display Partition 1

(line count) with high and
low significance fields

A Wide Display cycle width
of two words per memory cycle

'--_________ ~s.::~:_:~~h!d:!~I~

The dlsptay ~ress counter
Is then Incremented by
.
2 for each display scan
cycle. Other memory cycte

Parameter RAM Contents: RAM Address
RA-O to RA-15
The parameters stored in the parameter RAM, PRAM,
are available for the HGDC to refer to repeatedly
during figure drawing and .raster-scanning.ln each
mode of operation the values in the PRAM are interpreted by the HGDC in a predetermined fashion. The
host microprocessor must load the appropriate parameters into the proper PRAM locations. PRAM loading
command allows the host to write into any location of
the PRAM and transfer as many bytes as desired. I n this
way any stored parameter byte or bytes may be
changed without influencing the other bytes.
The PRAM stores two types of information. For
specifying the details of the display area partitions,
blocks of four bytes are used. The four parameters
stored in each block include the starting address in
display memory of each display area, and its length. In
addition, there are two mode bits for each area which
specify whether the area is a bit-mapped graphics'area
or a coded-character area, and whether a 16-bit or a
32-bit wide display cycle: is to be used for that area;

3-12

types are not influenced.
Display Partition 2
RA-4

starting address
I- and
length

SAD2L

LEN2L

Wo·1

SAD2H

LEN2H
..

Display Partition 3
RA-8

wool

address
I- starting
and length
.

SAD3L

SAD3H

LEN3L

LEN3H

Display PartHion 4
RA-12

wool

10
15

starting address
I- and
length

SAD",

LEN4L

SA .....

LE~4H

NEe

pPD7220A

Graphics and Mixed Graphics and Character
Modes
RA..

PTN l

PTN H

GCHR8

GCHR7

Command Bytes Summary
START

Pattern of 16 bits used for
figure drawing to pattern
dotted, dashed, etc. lines

ZOOM

CURS

GCHR6

GCHR5

GCHR4

GCHR3

GCHR2

GCHR1

PRAM

RA-O

_~~_~~_~~_~-'

LEN1L

I I ~~

aWOl.

WDAT

L...

PITCH

~~~dd~(~:~ ~~;r:~~)lflcance

FIGS

FIGD

I-_

____
LE_N_'_H_ _ _ _

Length of Display Partition

:~~I~C:i~~!~~~~d(r.~~hcount)

RDAT

Display Partition Area 2

LPRD

I° o I

DMAR

SAD2H
DMAW

LEN2H

Command Bytes Summary

MOD

TYPE

bit as in area 1
SAD2M

I
°I
I I° I I
I
o

CURD

starting address and
I- length
with image

SAD2L

I
I°
0

OCHRD

LEN2L

MOD

MASK

In mixed mode, a 1 indicates an
image or graphics area, and a 0
indicates a character area. In
graphics mode this bit must be O.
When 1, the DAD is incremented
every other display cycle.

WD211M

TYPE

Display Partition Area 1

SAD1 H

RA-4

I I° I

I~- starting address with low,

SAD1 L

Graphics character bytes
to be moved into display
memory with graphics
character drawing

I
I
I l'
TYPE

TYPE

MOD

Video Control Commands
Reset

RESET1
RESETX:
RESET2

L[_;;.......'-_O_··~......._~......._~~--'

Blank the display, enter
Idle mode, and initialize
within Ihe HGDC:
-FIFO
- Command Processor
-Internal Counters

RESET3

BLANK1

This command can be executed at any time and does
not modify any of the parameters already loaded into
the HGDC.

BLANK2

SYNC

VSYNC

CCHAR

I
I°

If followed by the parameter bytes, this command also
sets the sync generator parameters as described below.
Idle mode is exited with the START command.

RESET1:
RESET2:
RESET3:

Resync video timing in slave mode.
Blank the display and so not resync.
Un blank the display and do not resync.

3-13

pPD7220A
In graphics mode, a word is a group of 16 pixels. In
character mode, a word is one character code and its
attributes, if any. The number of active words per line
must be an even number from 2 to 256. An all-zero
parameter value selects a count equal to 2n where n =
number of bits in the parameter field for vertical
parameters. All horizontal widths are counted in display
words. All vertical invervals are counted in lines.
If the Drawing Hold (DH) is set to one, pin 21
(LPEN/DH) is used as the drawing hold control pin.
When the input to LPEN/DH is held high for over four 2
x WCLK clocks, the drawing address output is temporarily held and the display address is output.
The HGDC allows an even or odd number of lines per
frame. Selection is via the VL flag, the seventh bit of the
sixth parameter byte following a RESET or SYNC
command. When VL is 0, an odd number of display lines
is generated.

Blank Status Bit Dellnltlon

Status register bit 6 indicates horizontal blank
Status register bit 6 indicates vertical blank

PH is the most significant bit (9) of the display pitch
parameter. Use the PITCH command to set the lower
eight bits.

SYNC Generator Period Constraints
Horizontal.Back Porch Constraints
1. In general:
HBP!6 3 Display Word Cycles (6 clock cycles).
2. If the Image bit or WD mode changes within qne
video field:
HBP!6 5 Display Word Cycles (1Qclock cycles).
3. If interlaced, mixed mode, or split screen is used:
HBP !6 5 Display Word Cycles (10 clock cycles).

Horizontal Front Porch Constraints
PI

Mode of OperatIon . .1ect bfts
See below

Active Display Worc:ts per
line - 2 Must be evan
number with bit 0 = 0

HorIzontal Sync Width _ 1

' - - - - - - - - - Vertical Sync WJdth, towbita

"--Jr

---''--'---vs
....

L....&...-.L-H....
FP.....

1. In general:
HFP!6 2 Display Word Cycles (4 clock cycles).
2. If the GDC is used in video sync Slave mode:
HFP E 4 Display Word Cycles. (8 clock cycles).
3. Ifthe Light Pen is used:
HFP!6 6 Display Word Cycles (12 clock cycles).
4. If interlaced mode, DMA, or ZOOM is used:
HFP!6 3 Display Word Cycles (6 clock cycles).

Vertical Sync WIdth, high bUs

Horizontal Sync Constraints

, ' .....
' - - - - - - H o r i z o n l a ' Front Porch Width _1

PHl
VL

HBP

I-- Horizontal Back Porch Width _ 1

VFP

I- V,ertlcal Front Porch Width
Active Display Unes per
I- Video
Field, low bite

ALL

A4t

VBP

I-

'--"--"-'-\';:--".'--'--.1..-................

\,._---

Active Display Lines per
Vkleo Fjeld, high bUs

Vertical Back Porch Width

1. If interlaced display mode is used:
HS !6 5 Display Word Cycles (6 clock cycles).
2. If DRAM Refresh is enabled:
HS!6 2 Display Word Cycles (4 clock cycles).

Modes of. Operation Bits

c
o
o

DI.pIIY Mode

Mixed graphics and character
Graphics mode

Character mode
Invalid

Number 01 line. In Interlaced mode

Odd, as in 7220
Even

When VH =Oistatus operation is as in pPD7220;

Video Framing

o
o

Non-interlaced
Invalid

Interlaced repeat field for character lIisplays
Interlaced

3-14

t-IEC

JlPD7220A

Repeat Field Framing:

2 field sequence with 1/2
line offset between
otherwise identical fields.
Interlaced Framing:
2 field sequence with 1/2
line offset. Each field
displays alternate lines.
Non-Interlaced Framing: 1 field brings all the
information to the screen.
D

Dynamic RAM Refresh Cycles Enable

No refresh-static RAM

SYNC Format Specify
This command also loads parameters into the sync
generator. The various parameter fields and bits are
identical to those at the RESET command. The HDGC
is not reset nor does it enter idle mode.

'ID~

The display is enabled by
ai, and blanked by a 0

Refresh-dynamic RAM
Mode of Operation select bils
See below
Active display words per line
Must be ellen number with
bit 0 o.

Dynamic RAM refresh is important when high display
zoom factors or DMA are used in such a way that not all
of the rows in the RAMs are regularly accessed during
display raster generation and for otherwise inactive
. display memory.

Horizontal Sync Width _ 1
' - - - - - - - - - - Vertical Sync Width, low bits

Drawing Time Window

' - - - - - - - - Horizontal Front Porch Width _ 1

Drawing during active display time and retrace blanking
Drawing only during retrace blanking

Access to display memory can be limited to retrace
blanking intervals only, so that no disruptions of the
image are seen on the screen.
Both commands allow a reset while preventing reinitialization of the internal sync generator by an
external sync source (slave mode).

I
I

HBP
VFP

ALL

vep

f - Horizontal Back Porch Width _ 1
f - Vertical Front Porch Width
Display Lines per Video
f - Active
Field, low bits

Active Display Lines per Video

L.....~~---.,....--'~~-L_A~L_H-.J!Field, high bits

\ c . . - - - - - - V e r t l c a t Back Porch Width

RESET3! 0

o ,

RESET21

I
I

Vertical Sync Mode
When using two or more HGDCs to contribute to one
image, one HGDC is defined as the master sync
generator, and the others operate as its slaves. The
VSYNC pins of all HGDCs are connected together.

VSYNC'L0-I~,~~---1.'I..,.-J~

Slave Mode Operation
A few considerations should be observed when synchronizing two or more HGDCs to generate overlayed
video via the V/EXT SYNC pin. As mentioned above,
the Horizontal Front Porch (HFP) must be four or more
display cycles wide. This is equivalent to eight or more
clock cycles. This gives the slave HGDCs time to
initialize their internal video sync generators to the
proper point in the video field to match the incoming
vertical sync pulse (VSYNC). This resetting of the
generator occurs just after the end of the incoming
VSYNC pulse, during the HFP interval. Enough time
during HFP is required to allow the slave HGDC to
complete the operation before the start of the HSYNC
interval.

o -Accept External Vertical
Sync -

Slave Mode

1 -Generate & Output Vertical
Sync - Master Mode

3-15

t-IEC

pPD7220A
Once the HGDCs are initialized and set up as master
and slaves, they must be given time to synchronize. It is
a good idea to watch the VSYNC status bit of the
master HGDC and wait until after one or more VSYNC
pulses have been generated before the display progess
is started. The START command will begin the active
display of data and will end the video synchronization
process, so be sure there has been at least one VSYNC
pulse generated to which the slaves can synchronize.

Display Blanking Control
BLANK2 does not cause the resyncing of an HGDC in
slave mode. SLANK1 does cause the resyncing of an
HGDC in slave mode.

DE I--ThediSPl8Yisenabied
by a 1, and blanked by

aD.

Cursor and Character Characteristics
In graphics mode, LR should be set to O. The blink rate
parameter controls both the cursor and attribute blink
rates. The cursor blink-on time = blink-off time = 2 x
SR (video frames). The attribute blink rate is always
one-half the cursor rate but with a 3/4-on-1/4-off duty
cycle. All three parameter bytes must be output for
interlaced displays, regardless of mode. For interlaced
displays in graphics mode, the parameter SRL = 3.
When SE = 0, the HGDC, in slave mode, detects the
falling edge of EX. SYNC on the first frame. When SE =
1, the HGDC, in slave mode, detects the falling edge of
EX. SYNC on every frame.

BLANK2,1

0,0,.',0

Zoom Factors Specify
Zoom magnification factors of 1 through 16 are available using codes 0 through 15, respectively.

OISP

I-

GCHR

Zoom factor for graphics

L...~---'-''\~,__
:-_.L_-_-'_-_-_~-_--'_-_~r_
\
filling

character wrltmg and area

Display zoom factor

~~I_O~,_'~~~~__~~'~I

Cursor Position Specify

/~---------------IExternal

lotEG I

SYNC Enable

I - - Lines per character row - 1

~------------ Display Cursor if1

I B~~LSti

CTOP

I--~U:~~;;~PBnenumbe,

~--------O _ Blinking Cursor

1 _ Steady Cursor

In character mode, the third parameter byte is not
needed. The cursor is displayed for the word time in
which the display scan address (DAD) equals the
cursor address. In graphics mode, the cursor word
address specifies the word containing the starting
pixel of the drawing; the dot address value specifies the
pixel within that word.

~--------Blink Rate, lower bits

'---'--..LC,BO:-,T_ _

~-,--,-B_R~u--->1-- Blink Rate, upper bits

'\~'------Cursor BoHom line number in
the row CBOT < LR

Display Control Commands
Start Display and End Idle Mode

EAD

low byte

I~.~~__~~~---'-__"---'!
I-

Execute Word Address,
middle byte

L-~d...,AD,..---'~.L1W_G~O---,-I__E~,,'D--,~

The START command generates the video signals as
specified by the RESETX or SYNC command.

EAD

\~'
-

3-16

I - - Execute Word Address,

~.~~~~~~---'-_ _'----'_

(Graphics Mode only)

_ _ _ _ _ _ _ _____ •W"no"r"d A
"ddress, top bits
Dot Address within the word

tttfEC

JlPD7220A

When the WG bit is set to one, any data following the
WDAT command is written as is. When the WG bit is set
to zero, the 7220A performs as the 7220 does: The
pattern written is determined by the least significant bit
of each parameter byte following the WDAT command.
This bit is expanded into 16 identical bits which form
the pattern.

Parameter RAM Load
From the starting address, SA, any number of bytes
may be loaded into the parameter RAM at incrementing
addresses, up to location 15. The sequence of parameter bytes is determined by the next command byte
entered into the FIFO. The parameter RAM stores 16
bytes of information in predefined locations which
differ for graphics and character modes. See the
parameter RAM discussion for bit assignments.

PRAM:

' - - - - - Starting Address in
parameter RAM

l---

'--..L....~~~_~~~-.J

I
I

I
Po

1 to 16 bytes to be loaded

~~~t~~: ~~~~;~~~~~~ress

specified by SA

Pitch Specification
This value is used during drawing by the drawing
processor to find the word directly above or below the
current word, and during display to find the start of the
next line.

Drawing Control Commands
Write Data into Display Memory
Upon receiving a set of parameters (two bytes for a
word transfer, one for a byte transfer), one RMW cycle
into video memory is done at the address pointed to by
the cursor EAD. The EAD pointer is advanced to the
next word, according to the previously specified
direction. More parameters can then be accepted.
For byte writes, the unspecified byte is treated as all
zeros during the RMW memory cycle.
In graphics bit-map situations, only the LSB of the
WDAT parameter bytes is used as the pattern in the
RMW operations. Therefore it is possible to have only
an all ones or all zeros pattern. Ifthe WG bit of the third
parameter of the CURS command is set to one, any
byte following the WDAT command is written as is. In
coded character applications all the bits of the WDAT
parameters are used to establish the drawing pattern.
The WDAT command operates differently from the
other commands which initiate RMW cycle activity. It
requires parameters to set up the Pattern register while
the other commands use the stored values in the
parameter RAM. Like all of these commands, the
WDAT command must be preceded by a FIGS command and its parameters. Only the first three parameters need be given following the FIGS opcode to set
up the type of drawing, the DIR direction, and DC
value. The DC parameter +1 will be the number of
RMW cycles done by the HGDC with the first set of
WDAT parameters. Additional sets of WDAT parameters will see a DC value of 0 which will cause only
one RMW cycle to be executed per set of parameters.

The Pitch parameter (width of display memory) is set
by two different commands. In addition to the PITCH
command, the RESET (or SYNC) command also sets
the pitch value. The "active-words-per-line" parameter,
which specifies the width of the raster-scan display,
also sets the pitch of the display memory. Note that the
AW value is two less than the display window width.
The PITCH command must be used to set the proper
memory width larger than the window width.

Pl:

TYPE

I I
0

MOO

~ RMW Memory cycle
...--..

o
1

---

0
1
0
l

Logical Operation:

_ _ REPLACE with Pattern
_COMPLEMENT
_ _ _ RESET to zero
_ _ SETtol

' - - - - - - - - Data Transfer Type:

o
1
1
o

f!!£!:!:.!

0 ~~~~~~word'
Lowofthen
High byte
O.
Low Byte
the Word
High Byte of the Word
1
1,.
Invalid

IL~--,_W_O~R_OL~O_R
_BY~TE~_,---,~
Word Low
or
.
I~-- -- Smgle
ByteData
DataByte
value

0 , 1

l---

'--..L....~-L---'_.L--'--'---'

., I
etc.
Number of word addresses

WORO H

L-.- Word transfer only:
- High Data Byte

'--~~"""""~_~..L....~--,I

~nO~ii:g~~~1 ~~~~~~~n the

3-17

t¥EC

pPD7220A
Mask Register Load

Figure Drawing Parameters Specify

This command sets the value of the 16-bit Mask
register of the figure drawing processor. The Mask
register controls which bits can be modified in the
display memory during a read-modify-write cycle.
The Mask register is loaded both by the MASK command and the third parameter byte of the CURS
command. The MASK command accepts two parameter bytes to load a 16-bit value into the Mask
register. All 16-bits can be individually one or zero,
under program control. The CURS command, on the
other hand, puts a 1-of-16 pattern into the Mask
register based on the value of the Dot Address value,
dAD. If normal single-pixel-at-a-time graphics figure
drawing is desired, there is no need to do a MASK
command at all since the CURS command will set up
the proper pattern to address the proper pixels as
drawing progresses. For coded character DMA, and
screen setting and clearing operations using the WDAT
command, the MASK command should be used after
the CURS command if its third parameter byte has
been output. The Mask register should be set to all
ones for any "word-at-a-time" operation.

~Io
Pl

Drawing Direction Base
Figure Tvpe Select Bits:

L~=====Line(Vector)
Graphics Character
'----------Arc/Circle

'-----------Rectangle
' - - - - - - - - - - - - S l a n t e d Graphics

P'rl~~~D~CL~=:',r-I DC D..wlngPa'ame'e'

Gr--~---,-"--D~CH-'--'----'~

P3 'I..-i....1-1

, ' -_ _ _ _ _ _ _ Graphics Drawing flag for use in
Mixed Graphics and Character Mode

cl;=~~~~L~~CI DD,aw;ng _a,ame'e,

low significance byte

PtOd

~_~~~MH_~~~--,

High significance byte

P11l

L..I

~.-"-

:100

--,---,-_D~H--,---,---,j)

---,-0---,-1

1<-1

:1. ·

Character

:LD~H:: t~~··"-

o : o

The parameters take on

dm"'en' ;nte,.,"allono 10'
different figure types.

Valid Figure Type Select Combinations
Sl

GC
0

Character display mode drawing,
individual dot drawing, OMA, WOAT,
and ROAT

Graphics character drawing and
area filling with graphics character
pattern

Arc and circle drawing

Rectangle drawing

Slanted graphics character drawing
and slanted area filling

0
0

Operation

Straight line drawing

Only these bit combinations assure correct drawing
operation.

3-18

Figure Draw Start
On execution of this instruction, the HGDC loads the
parameters from the parameter RAM into the drawing
processor and starts the drawing process at the pixel
pointed to by the cursor, EAD, and the dot address,
dAD.

° °1

ttiEC

pPD7220A

Graphics Character Draw and Area Filling Start
Based on parameters loaded with the FIGS command,
this command initiates the drawing of the graphics
character or area filling pattern stored in parameter
RAM. Drawing begins at the address in display memory
pointed to by the EAD and dAD values.

The following bytes are returned by the HGDC through
the FIFO:

Execute Addr... (EAD).
low byte

The execute address, EAD, points to the display
memory word containing the pixel to be addressed.
The dot address, dAD, within the word is represented
as a 1-of-16 code for graphics drawing operations.
As this instruction begins to execute, the FIFO buffer
direction is reversed so that the data read from display
memory can pass to the microprocessor. Any commands or parameters in the FIFO at this time will be
lost. A command byte sent to the HGDC will immediately reverse the buffer direction back to write
mode, and all RDAT information not yet read from the
FI FO will be lost. MOD should be set to 00 if no
modification to video buffer is desired.

Da18r.an_Type:

O-.-----'WOrd,lowthenhighbyle

-.-----Low

High byte of the Word only

Invalid

byte of the Word only

LAD,

A15

LA,""

, 0

I-U9ht

~Li9ht
Pen Addr....
middle byte

I 1LAD.

Pen Address, low byte

Ughl Pen Address, high byte

The light pen address, LAD, corresponds to the display
word address, DAD, at which the light pen input signal
is detected and deglitched .

Cursor Address Read

.9!!!2:.1,

The following bytes are returned by the HGDC through
the FIFO:

~ ~ll~_O~l~I_T_Y~PE-LI_o~I_M~OD~

Light Pen Address Read

The light pen may be used in graphics, character, or
mixed modes but only indicates the word address of
light pen position.

3-19

pPD7220A
DMA Control Commands
DMA Read Request
DMAII:

I. ,

DMAWrlteF!eqlJest

• I"TYPE"I· MOD
I~o--"---,-,""---,-,-- Data Transfer Type:

R~W ~mory
O~REPLACE

o -..,.;."'-----'-'-'--- WOrd, Low then High Byte

Logical 0peraU0n:

wtth Pattem

1 -COMPLEMENT

.------Low Byte OItha WOrd

0""-

0 _ RESET to Zero

• -oO_-----High Byte of the Word

1-SETtoOne

• -..
oo_-----Invalld

i------Data Tr.n..... Type:
0 _ 0 0 - _ _ _ _ Word, Low then High Byte

o -.~----Low Byte of the Word
1

-.~~~'---High·By'teofthewotd ".0:

1 -.o------Invalld

AC Characteristics
TA =0 to +70°C; Vee = 5,0 V ±10%;GND.= 0 V
722OAD-l limits

7220AO Um"ilS.
Paramater

Symbol'

Min

Max

Min

Max

7220AD-2 limits
Min

Max

Unit TIBtConditions

Read Cycle IGDC ....-... CPUI
Address setup to

tAR

Address hold from
Riit

tRA

tR01 + 20

Rill

RD pulse width

tRH1

Data delay from
Riil

tR01

Data floating from
Riit

tOF

RD pulse cycle

tRCY
CPUI

4tCLK

4 tCLK

Address setup to
WRl

tAW

Address hold from
WRt

tWA

WR pulse width

tww

Data setup to WR"t

tow

Data hold from WR't

two

WR pulse cycle

twCY

4tClK

"4 tClK

"ns
ns

WritB CyelBIGDC

3-20

+--+

tRCY - 112 tCLK

tR01 + 20

75
75

tWCY- tCLK

tRCY -1/2 tClK

tR01 + 20

65
0

tWCy-tCLK

tRCY - 112 tCLK ns.
55·

tWCY"':' tCLK

,. :9L "",50 pF

ttlEC

pPD7220A

AC Characteristics (cont)
= 5.0 V ±10%; GND = 0 V

TA = 0 to +70°C; Vee

7220AO-l limits

7220AO limits
Parameter

Symbol

Min

Max

Min

Max

7220AO-2 limits
Min

Max

Unit Test Conditions

OMA Read Cycle (GOC - - CPU)
DACK setup to

Riil
DACK hold from RD!
RD pulse width

tR02

+ 20

Data delay from RDI tR02
DREa delay from
2xWCLK!

tREO

DREa setup to
DACKI

tOK

DACK high-level
width

tOK

tClK
4 tCldl)

DACK pulse cycle

DREal delay from
DACKI

tKO(R)

DACK low-level
width

tlK

tRK
tRR2

tKR

tR02 + 20

1.5 tClK + 80

1.5 tClK + 70

1.5 tClK + 60

Cl = 50 pF

100

Cl = 50 pF

tClK
4 tClK (1)

tClK

ns
ns

4tCldl)
tClK + 90

tClK + 100
2 tClK

tClK + 80

Cl = 50 pF

2 tClK

OMA Write Cycle (GOC - - CPU)
DACK setup to
WRI

tKW

DACK hoid from WR! tWK

RMW Cycle (GOC - - Display Memory)
Address/data
display from
2xWCLK!

tAD

105

Cl = 50 pF

Address/data
floating from
2xWCLK!

tOFF

105

Cl = 50 pF

Input data setup to
2xWCLKI

tOiS

Input data hold from
2xWCLKI

tOIH

tOE

DBIN delay from
2xWCLKI

tOE

Cl = 50 pF

ALE! delay from
2xWCLK!

tRR

Cl = 50 pF

ALEI delay from
2xWCLKI

tRF

Cl = 50 pF
Cl = 50 pF

tOE

ALE high width

tRW

1/3 tClK

ALE low width

tRl

1.5 tClK - 30

Address setup to
ALEI

tAA

Nole:

(1) For high-byte and low-byte transfers: tE = 5 telK.

3-21

pPD7220A
AC Characteristics (cont)
TA = 0 to +70·C; Vee = 5.0 V ±10%; GND = 0 V
7220AO limits
Parameter·

Symbol

Display Cycle (GDC -

Min

7220AD·l Limits

Max

Min

Max

7220AD·2 Limits
Min

Max

Unit Test Conditions

Display Memory)

Video signal display tva
from 2xWCLKI
Input Cycle (GDC -

Cl = 50 pF

Display Memory)

Input signal setup to tps
2xWCLKt
Input signal width

tpw

tClK

Clock (2xWCLK)
Clock rise time

tCR

Clock fall time

tCF

Clock high pulse
width

tCH

Clock low pulse
width

tCl

Clock cycle

tClK

165

10000

145

10000

125

10000

Capacitance

DC Characteristics (cont)

TA = 25·C; Vee = GND = 0 V

TA = 0 to HO·C; Vee = 5 V ±10%; GND = 0 V
Limits

Parameter

Symbol Min Typ Max

Input capacitance
10 capacitance

CIN
CIO

10
20

Output capacitance COUT
Clock input
CI/l
capacitance

20
20

Test
Conditions

Unit

pF fc = 1 MHz
pF VI (unmeasured)
pF =OV
pF

Absolute Maximum Ratings (Tentative)

oto +70·C

Ambient temperature under bias
Storage temperature

-65 to +150·C

Voltage on any pin with respect to ground

-0.5 to +7V

Power dissipation

1.5 W

Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC Characteristics
Limits
Symbol

Min Typ

Max

Unit

Test
'Condilions

IlL

-10

p.A vl=nv

Input low leak
current (VSYNC,
DACK)

IlL

-500

p.A VI=OV

Input high leak
current (except
LPEN/DH)

IIH

+10

p.A VI=VCC

Input high leak
current (LPEN/DH)

IIH

+500

p.A VI=VCC

Output low leak
current

IOL

-10

p.A Vo=OV

Output high leak
current

IOH

+10

p.A Vo = VCC

Clock input low
voltage

VCl

-D.5

0.6

Clock input high
voltage

VCH

3.5

VCC + 1.0

270

rnA

current(~xcePt

VSYNC, ACK)

Note:
(1) For 2xWCLK, VIL = -0.5 to +0.6 V.
(2) For 2xWCLK, VIH = +3.9 V to Vee +1.0 V.

VCC +0.5

V (Notes 2, 3)

(3) For WR, VIH = 2.5 V to Vee +0.5 V.

0.45

V IOL =2.2 rnA

Vil

-0.5

0.8

Input high voltage

VIH

2.2

Output low voltage VOL
Output high voltage VOH

2.4

V IOH = -400p.A

Test
Condilions

Unit

V (Note 1)

Input low voltage

3-22

Min Typ

Max

Input low leak

Symbol

Vcc supply current ICC

TA = 0 to +70·C; Vee = 5 V ±10%; GND = 0 V
Parameter

limits
Parameter

t-iEC

pPD7220A

AC Testing Conditions

Timing Waveforms (cont)

Input Waveform for AC Test (Except 2xCCLK)

Microprocessor Interface DMA Write Timing

2.2

2.4
0.45

2.2

==t\

x:::=1
\

Tesl Polnls

~-~---~

0.8

2xWCLK:

0.8
DREQ:

Output Waveform for AC Test

DACK:

2.0

~'----..:..:..::..:..==-----~
~r--

'\~

Tesl Poinls

0.8

WR:

0.8

IWH (WR

10 HSYNC t ) ~ ICLK

I'H (DACK j 10 HSYNC t ) ;;.ICLK

Clock Timing (2xCCLK)

-\'3.5
0.6

Microprocessor Interface DMA Read TimIng

3.5;;'-0.6

2xWCLK:

Timing Waveforms
DREQ:

Microprocessor Interface Write Timing

t
---~L~IIWA

AO:~
WR:

valid
ww

1---

~------~

j'~

DBO-7:---:-ln-v--:al:-:id:---iI-~=====ln=va=li=d===~1==

I·

1m:

DBO"7:·--;:;;;;;;;==:---(!~!DG~f-7.:~=
.- High Impedance

·1

IWe> - - - -....

Microprocessor Interface Read Timing

AO:~~_....;.;va;;;;li.;;.d__j....,.}(

-.J
RD:---""'il
tAR

Invalid

X,-___

tA~
11-:::--------..

DBO-7:.-f,;Hi~9h;;;;;;~C:X:~~-':i;";;i;:T.;;;;;;;:j;;;;;;;-t-. Impedance
High Impedance
1------- tRCY

3-23

fttfEC

pPD7220A
Timing Waveforms (cont)
Display Memory Display Cycle Timing

Display Memory RMW Timing

+-___-"-__

A16, AI7:_+-'I-+--+_ _ _ _ _ _

ALE:
_-----tRL-------;,.j

Display and RMW Cycles (1x Zoom)

2xWCLK:

ALE:

ADO-15;

A16.17:

HSYNC,
BLANK:
V/EXTSYNC:

3-24

tttfEC

tJPD7220A

Timing Waveforms (cont)
Display and RMW Cycles (2x Zoom)

;;;
0

I
~.

;(

3-25

NEe

pPD7220A
Timing Waveforms (cont)
Display and RMW Cycles (3x Zoom)

I
I

--1---11-------

I
I

~
3-26

-;;-:-+!» -

•c

NEe

pPD7220A

Timing Waveforms (cont)
Light Pen and External Sync Input Timing

Clock Timing (2xWCLK)

2XWCLK:~E==ps
LPEN,---EX. SYNC:

tpw

Video Sync Signals Timing

2 X W C L K : J \ . . r \ . . / \ . . . / \ ____

../\../V\../\J\ __ ~ ___ J\..I\..- __ J\...
----"\'---

HBLANK:J
HSYNC: _ _ _ _ _ _ _ _ _ _ _~/

X'-_......C

AOD-15::x_ _ _ _..J
LCD-4:===X

r-l~~

\'--_ _ _ _ _ _ _ _ _ _ __

- -- -- )(_---'X'-__C= ==".J<'--__)( ===x:= ====t
\

_____~- _____ ~====::_-_ -_~ ~ ~ ~~~:_-_-_~~~ ~~_- ------_-_ -

_-1

-:t:::(XX. __ JOCXJC _______________________ __ xxxx. __JOe

AOO.15:Jp(X __

---=x=
+- ___ -v--- -- - - v - - -- -- -- - - - - - -- - - -- ---- -- -- ---v-- __
_

LCD-4:-\r'-- - - - --A...-- ___ -./\....- _________________________

I _ _ _ _ _ _--------------------------~

~
.

+----------------~--

ROW:::J<~-'X
1

VBLANK:

x::: ====::J(

- - - - - - - - - - - - - - - - - - - - - - ______ 1

X,---------

--------

'--- _- __ _ _--J/

VSYNC:-,-'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~/

i'--1·--------------1V(Frame)--------------------l·1

Inter/aced Video Timing

..JLJL __ -RJ"L.. __ ~ __ .JL __ JL __ .JLJL_~.JL.JL_
I
I
I I
I I
VBLANK:l- __ ~---L __ ..r-- I I I
HBLANK:JL __

I
VSYNC: I
(Interlace) I
I

1
I

L--

Odd Field
I
I

'I'

Even Field - - - ' - - - I

VSYNC:
(No Interlace,l-)- - - - - - - - - - '

3-27

pPD7220A
Timing Waveforms (coni)
Video Horizontal Sync Generator Parameters

I~'-------------------------lH----------------------~'1
----!I

HBLANK: _ _

____________________________

I
~r--

I
1

HSYNC: _ _ _

r1...____-'-___________________......:.__

;...I_ _. . . .

1
I

I
I

1
I

~-----+-.I.

·1

---CIA

Video Vertical Sync Generator Parameters

1~·----------------------lV----------------------~

L
1

VBLANK:

1
l

-IIl...______

VSyNC:-f!______..:.'_______________________--:-_ _

I
1
1

1
1
1
VBP

~·II_·------L/F------~-I

VFP

r
i

-.jVS

Cursor-Image Bit Flag

2.CCLK

3-28

-l 1-- 1....
JUUUl

tBP--j

t-{EC

pPD7220A

Video Field Timing

DMA Request Intervals
~

H---t---;;_=:::.=YNC=u.=:--------k-+-... _ _ _ _ u.

DMA Roquoot 1.......1

~ AdcIttlGnllI DMA Requestlnt. . . .
~ When In Flleh Mode

F_ _ ......
~

:::..:::"

v.rtlcll Front Porch BlInked U .....

Drawing Intervals
~

DrawIng Interval

~ AddftkJnll Drning Interval When

_RAM_._,OthorwI..

~1n_M_

Ill188
~

......1Drawing 1.......1

3-29

NEe

pPD7220A
Block Diagram of a Gra ..hics Terminal

---------,

r-------.PD7220

GDC

DIIO-7

eo_
Host

L ___________________________

Multiplane Display Memory Diagram

GDe

AD
Ot015

Character

Vld. .

Output

3-30

t\'EC

NEC Electronics Inc.

Description
The /4PD72020 is an enhanced graphics display controller resulting from the implementation of CMOS technology on the /4PD7220A
In addition to the functions of the /4PD7220A, the
/4PD72020 incorporates address space expansion, video
RAM control, and write mask functions. It is suitable for
a wide range of applications from simple display terminals to high-resolution graphics display devices.
This data sheet covers only functions additional to those
of the /4PD7220A. For further details of the /4PD72020,
refer to the /4PD72020 User's Manual.

Features
o Enhanced functions compared with the /4PD7220A
- Video memory space: 2M bytes maximum
(1 M 16-bit words)
- Control of dual-port RAM (video RAM)
- Write-masking of any desired bit
- Enhanced external synchronization function
- CMOS technology
o /4PD7220A-compatible functions
- High-speed graphics drawing: 500 ns/dot
(operating at 8 MHz)
- Selection of drawing timing: flashless!flash mode
- Drawing of straight lines, arcs, quadrilaterals,
graphic characters
- Any kind of line specifiable
- Four different dot-correction modes
- Enlarged drawing/enlarged display
- Panning and scrolling
- Automatic cursor shifting
- Attributes assignable character by character
- Interlaced/noninterlaced scanning
- DRAM refreshing
- Master/slave operation
- Video memory control independent of main
memory
- 16 x 9-bit on-Chip input/output FIFO
- DMA control
- Single +5-volt power supply

p;PD72020
CMOS Graphics Display Controller

corresponding patents in various countries. Problems
may arise from such patents even when a different
graphics display controller or discrete circuitry is used,
and thus resolution on the basis of this product alone is
not possible. Therefore, the user is requested to undertake as his or her own responsibility an investigation of
measures to cope with this situation before designing an
application system.

Ordering Information
Part No.

Package

"PD72020C-S

40-pin plastic DIP

"PD72020GC-S-3B6

52-pin plastic miniflat

Pin Configurations
4O-Pin Plllstic DIP
2xCCLK

l5BiN
HSYNC-REF
VSYNClEX. SYNC
BLANK

RAs
DRQlA1S (A13) [A16]
DACKlA19 (A14) [A17]
RD
WR

AO
DBo
DBl
DB2
DB3
DB4
DBs
DB6
DB7
GND

VDD
A17 (CSR·LC4) [CSR-IMAGE]
A16 (LC3) [AT.BLlNK·CLC]
AD1S (LC2)
AD14 (LC1)
AD13 (LCO)
AD12
ADll
AD10
AD9
ADS
AD7
AD6
ADS
AD4
AD3
AD2
ADl

ADo
LPENlWAIT/DT

() Character mode
[) Character/graphics combined mode
83SL-5704A

Appl ications
Some application functions implemented by use of this
product in conjunction with other products may infringe
on U.S. Patent No. 4,197,590 and Re. 31,200 etc. held by
CADTRAK Corporation of the United States, and the

150081

3-31

APD7202Q
52-Pin PIII.tic Mlnitl.,

NC
AD3
AD2

AD15 (LC2)
A18 (LOS) iii:f:'B[iNK- CLC)
Al,7 (CSR-LC4) [CSR-IMAGE)

ADl

Veo

ADO

lIDo

LPENlWAIT/DT
IC

IC
2XCCLK

GND
GND

i5iiiN
HSVNC-REF
VSVNClEX.SVil/C

BLANK
NC

DB7

DBe
12
13

DBS

~~~~:!!~!iI;;;~&I~\(l

() Character mode
. : [) Character/~raphlcs combined mode
83Sl:.5705B

Pin Identification
Symbol

Function

Symbol

Func.tlon

liD

Address select In~t for microproceesor
Interface

LPENlWAIT/DT

See text and tabls. 2.

!!!AS

Row address strobe ..

ADo-AD12

Address-data lines to display memory

AD1afLCO. AD1.vLCI.
AD1s/LC2

See text and table 3.

Read strobe Input for miCroprocesSor
Interface

VSYNC/EX.SYNC

A1afLC3/AtBLINKOCCC.
A17/CSR-LC4/CSR-IMAGE

S$e text and table 3.

Vertical video sync oytput or external
VSYNC input

BLANK

CRT blanking output

Write strobe input for microprocessor
Interface

DACRiA1g/Al.vA17

See text and table 1.

2xCCLK

Clock Input

DBo-DSr

Bidirectional data bus to host
microprocessor

GND

Ground

I5BIR

Display memory read input flag

DRO/AtslAla1A18

See text and table 1.

HSYNC-REF

Horizontal video sync output

•

VDO

+5-volt power supply

Internal connection

NC.

No connection

NEe

I-tPD72020

PIN FUNCTIONS

Pin LPEN/WAIT/OT

Pins on the ",PD7220A and the ",PD72020 have similar
functions. Differences are described below.

The functions of this pin depend on the setting of the DTE
bit by the WMASK command, which validates the DT
signal generation function. See table 2.

Pins ORO and

DACK

DT (Data Transfer). When the DT signal generation
function is selected by setting DTE of the WMASK
command, the DT signal is output to indicate the display
address supply timings for the ",PD41264-type video
RAMs (VRAMs).

The functions of these pins depend on the setting of the
PN bit by the WMASK command, which validates the
address extension functions See table 1.
A13• A14. A16-A19. When the address extension function
is selected by setting PN of the WMASK command, the
upper 2 bits (of the extended address) are output in the
video memory in each display/draw mode.

After the DT signal generation function has been selected, the LPEN and WAIT functions cannot be used.
LPEN (Light Pen Strobe). When the light pen detects a
light input, the H-Ievel signal is input.

After the address extension function has been selected,
the DMA-related functions cannot be used. Use the CHR
and G bits of the SYNC command to set the display/
draw mode (as with the ",PD7220A).

After the LPEN function has been selected, the DT signal
generation function cannot be used.

DRO (DMA Request). When the DMAR or DMAW command is executed, the DMA request signal is output.
This signal is input to the DRQ pin of the DMA controller.

WAIT (Drawing Wait). When a signal that remains at the
H-Ievel for a period of at least four clocks is input in the
drawing stop mode, the ",PD72020 will stop drawing
temporarily if it is executing drawing and output a
display address.

After the DMA-related functions have been selected, the
address extension functions cannot be used.

After the WAIT function has been selected, the DT signal
generation function cannot be used.

DACK (DMA Acknowledge). A signal indicating DMA
transfer is input. This signal is output from the DACK pin
of the DMA controller.

Pins AD13-AD15. A16. and A17
The functions of some other pins depend on the operating mode: character, graphics, or character/graphics
combined. See table.3.

Table 1. Pin Functions Available Through Address Extension
Pin Symbol

PN Bit (WMASK Command)

Action

Pin Function

Output

ORO

Graphics

Output

AlB

Character

Output

A13

Combined

Output

A16

Input

OACK

Graphics

Output

A19

Character

Output

A14

Combined

Output

A17

Action similar to "P07220A
Address extension

I/O

Mode

Action similar to "P07220A
Address extension

Table 2. Pin Functions Available Through DT Signal Generation
Pin Symbol
LPE N/WAIT/ OT

DTE Bit (WMASK Command)

Action

I/O

Action similar to "P07220A

Input

LPEN/WAIT

OT signal generation

Output

Pin Function

3-33

NEe

#,PD72020

Table 3. Multifunction Pins AD,:rAD,50 A,s. and A,7
Pin Symbol

Mode

I/O

Function

AD 13-AD I5

Graphics; combined

I/O

Address-data lines 13-15 to display memory

Character

Output

Line counter bits 0-2

Graphics

Output

Address bit

LC3

Character

Output

Line counter bit 3

AT.BLlNK-CLC

Combined

Output

Atiribute blink and clear line counter

Graphics

Output

Address bit 17

CSR-LC4

Character

Output

Cursor and line counter bit 4

CSR-IMAGE

Combined

Output

Cursor and bit-map area flag

LCO-LC2
A16

A17

ADDED BLOCK FUNCTIONS
Refer to the IlPD72020 Block Diagram and the System
Configuration Diagram.

Video RAM Control
Additional blocks generate the DT signal, which indicates the display-address supply timings for the video
RAMs. Data within the RAMs can be transferred to the
serial register.

Pin Extension Control
The video memory address is extended 2 bits (with the
address space extended fourfold) in each of the character, character/graphics combined, and graphics modes.
These bits are used for both DACK pin and DRQ pin in
each mode: A14 and A13; A17 and A16; A19 and AlB'

WMASK Register
This 16-bit register is used to mask the data for multicolor synchronous drawing with one word inB/4/2/1-bit
configuration.

IMPROVED FUNCTIONS
The IlPD72020 functions have been improved while
maintaining. compatibility with the ·IlPD7220A in both
hardware and software. Table 4 compares functions of
the IlPD72020 and the IlPD7220A.
The IlPD72020 is initialized by reset input so that it can
function similarly to the IlPD7220A.

3-34

~EC

#,PD72020

"PD72020 Block Diagram
GDC-

Video Memory
Control

Drawing Address Con1rollor

DBIN

fPsl

ADO -AD12

AD14ILC1

IMool
(16)

AD1SILC2

A16ILCat
AT.BlINK. CLC.
A17ICSR.LC4f
CSR.IMAGE
LPENlWArriffi'

+5V 0

Synchronizing Signal Generator
9
8

GND 0

2xCCLK
BLANK
VSYNClEX. SYNC
HSYNC.REF

AO 0......- -__

0>----.

o---~

DRQlA1WA13/A16

0"'---000-

i5iiCRJA19/Aj4 /A 17

0 - - -__

DBO -DB7

0"'_--000-

.I.GIIlII

()

Additional to I'PD7220A
Bits
83SL-S6B1B

3-35

NEe

#,PD72020

System Configuration Diagram; pPD72020 With Video RAM Control Signal DT
Data Bus

Address Bus

jJ.PD72020
BLANK f - - - - - - I

DB7 -DBO
f - - - - - - - J AO

VSYNC
HSYNC

Memory Planes
~.L

________ _

rl----------

--,
--,

--,

K::;-;::=============~:>ID15-DO

Video RAM
(4 x
I1PD41264)

I--------~-I AAs
'-_.J.---------4_1 CAS

RASHf---t
2xCCLK

I-_ _ _ _ _~~R~~OE
G
B

G
B
lIL ________ _

t- J
____ J

63SL-56828

3-36

NEe

I'PD72020

Table 4. Comparison of pPD72020 and pPD7220A Functions
"P072020

"P07220A

WMASK Command
WMASK command is used to validate the new functions of the
"PD72020.

WMASK command is not used.

OB71 OBsl OBSJ OB4J OB3J OB2J OBI lOBO
CMD

11101111101110

WMKL

WMKH

I TM I DTE I CYI I CYO I

°I°I °

WMK

Sets the WMASK register value.

Sets the address extension function.

Changes the initializing timing of the horizontal synchronization counter in the slave mode for external synchronization, and sets the initializing function of the field
counter.

DTE

Sets the function of generating the DT signal.

Set the OT signal output mode and the BLANK signal
mask.

LPEN Command
Light pen address (LAO) is extended 2 bits by setting PN of the
WMASK command.
PN

Ught pen address (LAO) extension function is not available.

Same as IIP07220A

EAO is extended 2 bits.
OB71 OBsl OBsl OB41 OB31 OB21 OBI

I O.BO

OB71 OBsl OBsl OB41 OB31 OB21 OBI lOBO

CMO

1 11101010101010

PMD

LAOL

LADL

LADM

LADH

1 11101010101010

LAOH

CSRW Command
Oraw execution address (EAD) is extended 2 bits by setting PN of
the WMASK command.
PN

·1

Draw execution address (EAD) extension function is not available.

Same as IIP07220A
EAD is extended 2 bits.

Character Mode
OB71 OBsl OBsl OB41 OB31 OB21 OBI lOBO
PMO
PI
P2

°I
°I

1 10101110101
EADL
EADH

OB71 OBsl OBsl OB41 OB31 OB21 OBI lOBO
pMD
PI
P2

°I I°I°I
°I°I°I
1

1
EADL

°I°I

EADH

3-37

NEe

~PD72020

Table 4. Comparison ofpPD72020 and pPD7220A Functions (cont)
"P072020

"P07220A

CSRW Command (coot)
Character/Graphics Combined Mode (Character Display)
OB71 OB61 OBsl OB41 OB31 OB21 OBl lOBO

OB71 OB61 OBsl OB41 OB3 I OB21 OBl lOBO

CMD

011101011101011

PMD

EADL

EADM

° ° ° °
I

I 0

P2
I

I 1
EADL

° °
I

EADH

Character/Graphics Combined Mode (Graphics Display/Drawing)
OB71 OB61 OBsl OB4 I OB3 I OB21 OBl lOBO

OB71 OB61 OBsl OB41 OB31 OB21 OBl lOBO

CMD

011101011101011

CMO

EADL

P2
P3
P4

EADM

° °
I

° °

dAD

011

EADH

I 0

EADH

I
I
I
WGIOIOIOlololoJo

I 1 I 0
EADL

dAD

IWGIOIOIO

Graphics Mode
OB71 OB61 OBsl OB4 I OB3 I OB21 OBl lOBO

OB71 OB61 OBsl OB41 OB3 I OB21 OBl lOBO

LiMD

01110101110Jo[1

CMD

EADL

EADM

P3
P4

dAD
WG I

EADH

I 0

° °
I

011101011101011

dAD

I WG I

EADH

I 0

CSRR Command
Draw execution address (EAD) is extended 2 bits by setting PN of
the WMASK command.
PN

Draw execution address (EAD) extension function is not available.

Same as "PD7220A
EAD is extended 2 bits.
OB71 OB61 OBsl OB41 OB31 OB21 OBl lOBO

CMD

1 1 1 0

1 0

EADL

EADM

3-38

101010

OB71 OB61 OBsl DB41 DB31 OB21 OBl I DBO
LiMD

111

I
EADL

EADM

D2
EADH

° ° °I ° °

dADL

dADH

EADH

NEe

"PD72020

Table 4. Comparison of pPD72020 and.pPD7220A Functions (cont)
"PD72020

"PD7220A

SCROll Command
Display start address (SAD) is extended 2 bits by setting PN of the
WMASK command.
PN

Display start address (SAD) extension function is not available.

Same as "PD7220A
SAD is extended 2 bits.

Character Mode
Built·ln RAM Map
MSBI

0
1

I
SL1L

* 1 0

I
SL2L

1 0

,SL3L

* 1 0

1
SL4L

10JOJot
SL2H

* DAD+2

1 0

1 0
SL1L

1 0 1 a 1 0
SL3H

1 0

1 a 1
SL2L

1 0

1 0 1 o 1
SL3L

1 0 1 01
SL4H

1 0

1 0
SL1H

0 1 0

SAD2H
1 0 1 a 1
SL2H

1 0

1 0 1 a 1 0
SL3H

1 0

SAD3L

1 0

1 0 1

SAD3H

SAD4L

SAD4H

SAD2L

SAD1H

SAD4L

4
5

1 LSB

SAD1L

2
3

SAD3H

C
D

SAD3L

A
B

1 01

SAD2H

1
Contents or RAM

SAD2L

1 0 1 0
SL1H

J I

MSBI
RA

SAD1H

4
5

I LSB

SAD1L

2
3

1
1
1
Contents or RAM

1 o 1
SL4L

SAD4H
1

1 0
SL4H

1 0

* DAD +2

3-39

NEe

"PD72020
Table 4. Comparison 01 pPD72020 and pPD7220A Functions (conI)
,.PD72020

,.PD7220A

SCROU Command (cont)
Character/Graphics Combined Mode (Character Display)
Built·ln RAM Map

MSBI

RA
0

1
SL1L

3
4

SAD3L
SAD3M

SL3L

* 1

SL3H
SAD4L •
SAD4M'

SL4L

SL4H

* 1 0 1
* DAD+2

1 LSB

SL1H

SL2L

I 0 I 0 I 0 I 0

SL2H

* 1 0 1
SAD3L
SAD3H
SL3L

1 0 1 0

01 0

SL3H

* I 0 I
SAD4L
SAD4H

1 0 1 0 I SAD4H

SAD2L
SAD2H

A
B
C

1 0 1 0 1 0 1 0

1 0 1 0 1 SAD3H

0 1

SL1L

6
7

* 1 0 1

SL2H

1
2
3
4

Contents of RAM
SAD1L
SAD1H

1 0 I 0 I SAD2H

* 1 0 1

SAD2L
SAD2M
SL2L

MSBI

1 LSB

SL1H

* 1 0 1

A
B
C

1 0 1 0 1 SAD1H

Contents of RAM
SAD1L
SAD1M

SL4L

0 1 01 0

SL4H

* 1 0 1
* DAD+2

Character/Graphics Combined Mode (Graphics Display/Drawing)
Built-In RAM Map

MSBI

RA
0

1
2
3
4

SL1L

SL2L

* 1 1M 1

* DAD +2

1 SAD1H

1
2
3
4

SL2H

SL1L

*
* DAD+2
7

1 LSB

1 0 1 0 1 01 0

SL1H

* 1 1M 1
SAD2L
SAD2H

1 0 1 0 1 SAD2H

Contents of RAM
SAD1L
SAD1H

SAD2L
SAD2M

MSBI

1 LSB

SL1H

• 1 1M 1

Contents of RAM
SAD1L
SAD1M

SL2L

I 1M L

1 0 1 0 1 01 0

SL2H

t-rEC

I'PD72020

Table 4. Comparison ofpPD72020 and pPD7220A Functions (conI)
,.PD72020

"PD7220A

Scroll C"""".nd (t:OIIf)
Graphics Mode

Built-In RAM Map
MSB!

j
I
Contents or RAM

MSBI

I LSB

SAD1L

SAD1M

2
3

SL1L

1 1M

SAD1H
SL1H

2
3

SL1L

I 1M I

SAD2L

SAD2M

SL2L

• DAD+2

11M I

SAD2H

I
SL2H

SL2L

I!
7

I LSB

* DAD+2

I 1M I

SAD1H

SAD2H

0
0
SL1H

Contents or RAM

0
0
SL2H

3-41

NEe

jlPD72020

COMMANDS
The ItPD72020 supports all commands ofthe ItPD7220A.
Although command names are different, opcodes are the
same. The ItPD72020 can activate the software created
for use with the ItPD7220A.
The improved functions of the ItPD72020 can be used by
setting the new WMASK command. Once the RESET
command is input, however, the WMASK command
becomes inactive and the ItPD72020 maintains the same
functions as those of the ItPD7220A.
This section describes the WMASK command as well as
the SCROLL, LPEN, CSRW, and CSRR commands,
which are affected by the setting of the WMASK command.

WMASK Command
This new command (figure 1) controls four new functions.
• WMASK register setting
• Address extension

drawn data bit corresponding to the WMASK register
bit set to 1 is affected by drawing.
When the RESET command is input, the ItPD72020 is
set to this mode.
PN Bit. PN is used to set the address extension function
for the video memory.
(1) When PN = 0, operation is similar to the ItPD7220A.
Thus, the address extension function cannot be
used.
When the RESET command is input, the ItPD72020 is
set to this mode.
(2) When PN = 1, the video memory address is extended
2 bits (with the address space expanded fourfold).
The DRQ/A18/A1s1A16 pin and the DACK/A1g/Al4fA17
pin output the upper 2 bits of the extended address.
The DMA-related functions cannot be used.
The address to be output depends on the display and
drawing modes. See table 1. The address space is
shown in table 5.

Table 5. Address Space With Extended Address

• Selection of additional functions in the external slave
mode
Address

Character
Mode

Character/Graphics
Combined Mode

Graphics
Mode

15 bits
(32Kwords)

18 bits
(256K words)

20 bits
(1M words)

• DT signal generation

space

Figure 1. WMASK Command Format

As the address space is expanded, the following command bits are also extended.

CMD

I DB6 I DB5 I DB4 I DB3 I DB2 I DB1 I DBO
011
101 1 I 1 1 0 1 1 I 0

WMKL

WMKH

DB7

I TM J DTE I

CY1

J CYO I

• EAD bit of CSRW command

WMK Bit. The ItPD72020 is equipped with the conven·
tional MASK register and a 16-bit WMASK register. The
WMK bit is used to set this WMASK register.
The 16-bit WMASK register is used for write mask of the
multicolor, simultaneously-drawn data with one word set
in 8-, 4-, 2- and 1-bit formats. Each bit of the WMASK
register corresponds to each bit of the drawn data.
(1) When a WMASK register bit is set to 0 by the WMK,
the drawn data bit corresponding to the WMASK
register bit set to 0 is not affected by drawing.
(2) When a WMASK register bit is set to 1 by the WMK,
operation is similar to the ItPD7220A. Thus, the

3-42

• LAD bit of LPEN command

• EAD bit of CSRR command
• SAD bit of SCROLL command
Refer to the description of each command for details.
TM Bit. TM has been added to solve the following two
problems with the ItPD7220A.
• Because the vertical and horizontal counters are
initialized at the start of VFP and HFP, respectively,
when the external synchronizing signal is input to the
ItPD7220A, horizontal positioning cannot be readily
done for synchronization with the ItPD7220A by inputting a synchronizing signal from the external device.

,..,EC

"PD72020

• When the "PD7220A is operated in the interlace mode,
input of the external synchronizing signal causes no
effect on the field counter. Thus. if the synchronizing
signal is unconditionally input from the external device when the "PD7220A is in the second field, the
second and. first fields are reversed in subsequent
frames and the fields do not conform with the external
device.
When the "PD72020 operates in the slave mode for
external synchronization, the setting of the TM bit will
cause the "PD72020 to operate differently from the
"PD7220A in the following operations.
• The timing of initializing the horizontal. synchronous
counter is changed.
• The initializing function of the field counter is validated.

When TM = 0, the function similar to the external
synchronizing function of the "PD7220A is carried out.
When the RESET command is input, the "PD72020 is set
to this mode.
When TM = 1, the follOWing two operations differ from
those of the "PD7220A.
(1) When the RESET command is executed or the
EX.SYNC (external synchronizing signal) is input,
the horizontal counter is reset at the rising edge of
the HS. See figure 2.

(2) When the RESET command is executed in the interlace mode or the EX.SYNC signal is input, the field
counter is unconditionally reset to the first field
mode.
Thus, the VSYNC signal in the second field should be
removed externally so that the synchronizing Signal
applied to the EX. SYNC pin serves as the VSYNC
signal in the first field On the interlace mode).

Flgul'll 2. Hodzontlll Counter Reset Timing

Sli...---_ _--.l1
,,
:,
I

,,
:,

I-HS-!-HBP'....;..·>-------ClR
I

---i------------+:---;'

------.. t:~--;.:---:

r- - - - 1/$

------~l;-

' • I Fp.!
:

'
:

1-- - - - - - - - ~

.------t.-- ......______________--'
•

Reset posIdon when TM • 1

Reset pashlon when TM. 0

3-43

#PD72020

OlE, CY1; CYOBit$.To prevent the display screen from
becoming blur.red' during drawing operations, ,the
"PD7220A norrnally performed drawing in theflashless
drawing mode. Thus, the drawing period was limited and
it was difficult to improve the drawing efficiency.
?'

•

To solve this problem, video RAMs can be used for the
"PD72020.Through the use of VRAMs, both drawing and
display can be carried out simultaneously in the flashless
drawing mode'withthe resultthat the drawing efficiency
can be improved. OrE, CY1,'anQ CYO are llsed to control
the "PD41264-type VRAMs and the BLANK signal.

Table 6. DT Signa' Output Modes
DTE

CY1

eyO'

0
,0 "

Function
GOC mode 0
GOC mode 1 (BLAN K si'gnal mask t)

Inhibited

OT signal output mode 0 (BLANK sig·
nal mask t)

Inhibited

D'i' signal output mode 1 (BLANK signal mask t)

D'i' signal output mode 2

(BLANKslg-

nal mask t)

t If the I4P072020 has ,started drawing operations in the display
mode, the BLANK Signal is not set to H.

OlE = O. Operation is similar to the "PD7220A. The D'f
signal functions cannot be used. The LPENJWAIT/DT pin
performs the LPEN ,or WAIT functions.

3-44

The following two modes,are avai,lable by,setting CY1 or
CYO(table 6).
.
'
,',' ,,'
(1) GDC mode 0 operationJs similar to the "P07220A.
When the'RESET command, is input, the "PD72020 is
set to this mode.
(2) GDC mode 1 operation is' similar to G DC mode 0
except if the "PD72020 starts draWing operations
during the display period, the BLANK signal is not
set to H even in the flash screen mode.
OlE =1. The DT signal functions are enabled and the
DT signal is output from the LPEN/WAIT/DT pin. The DT
signal is used for display timing when the display memo
ory consists of dual-port video RAMs. the VRAMs allow
drawing during both drawing and display-cycles.
When DTE is set to 1, the "PD72020 internally tracks the
display address and outputs itand the DT signalllnder
either of two conditions.
(1) At the start of every horizontal scan line (figure 3).
(2) When the lower 8 bits of the display address (DAD)
internllllcounter are O.
The starting display address should be set before setting
DTE to 1. The "PD72020 will temporarily stop a drawing
,,operation before issuance of the Of signal, as in the case
of the "PD7220A WAIT function.
The Of signal output timing depends on the setting of
the 1M and DAO+2 bits of the SCROLL command. CYO
andCY1 determine which of the"following three DT
signal output modes is used.
'

NEe

"PD72020

Mode 0 With OTE
1_ In mode 0, the DT signal is
output as shown in figure 4.

(2) When the lower 8 bits of the DAD counter change
from FEH or FFH to OOH.

(1) At the start of every horizontal scan line.

Additionally, the DT signal active state in mode 1 has the
following qualifications.

(2) When the lower 8 bits of the DAD counter change
from FEH or FFH to OOH.
Additionally, the DT signal active state in mode 0 has the
following qualifications.
(1) DT may become active in succession; for example,
when the DAD counter changes to OOH just after the
start of a horizontal scan line as in figure 4C.

(1) DT may become active in succession.
(2) When the lower 8 bits of the DAD counter change to
OOH in succession, DT is active only during the first
cycle.
(3) DT can become active during HFP, HS, H BP, VFP, VS,
or VBP periods.

(2) When the lower 8 bits of the DAD counter become
OOH in succession, DT becomes active during the
first cycle only. See figure 4D.

(4) DT will not become active while the DMA refresh
operation is disabled (D-bit of SYNC command set to

(3) DT will not become active during HFP, HS, HBP, VFp,
VS, or VBP periods.

(5) DT becomes active every four cycles.

Mode 1 With DTE = 1_ In mode 1, the DT signal is ouput
as shown in figure 5A.

1).

Mode 2 With DTE
1_ In mode 2, the DT signal output
is the same as described for mode 1 except DT is active
every eight cycles instead of every four cycles. See figure

5B.

(1) At the start of every horizontal scan line.

Figure 3. DT Signal Output for Eat;h Horizontal Line
HBP

Display Period -

HSYNC

BLANK

Data Transfer Cycle

L-

CGOCOperations 1 E4
E2

E1 1 E21 E31 E4
E3
E4
01- 02-

0111 OT21 01-1 02-1 E1 1 E21
E2
OT1 OT2 01- 02- E1

Symbols
OT Display cycle (data transfer cycle). OT signal is active.
0- Dummy display cycle. 01 signal is Inactive.
E

Drawing cycle. If no data is drawn. display cycle is set.
83SL-S707B

3-45
---------._---

~EC

#,PD72020

Figure 4.

DT Signal Output, Mode 0 (Sheet 1 of 2)
A. Bit 1M = 0 and Bit DAD+2 = 0

AD1s - ADO (H)

VSYNC

HSYNC

HS
BLANK

HBP

~ II

D-

Cycle

D-

B. Bit 1M = 0 and Bit DAD+2 = 1

AD1s - ADo (H)

HBP

r--

VSYNC

HSYNC

HS
BLANK

1\
Cycle

D-

Symbols
DT Display cycle (data transfer cycle). DT signal is active.
D-

Dummy display cycle. DT signal is inactive.

Drawing cycle. If no data is drawn, display cycle is set.
83SL-S708B

3-46

NEe
Figure 4.

p.PD72020

DT Signal Output, Mode 0 (Sheet 2 of 2)

c.
ADts- ADo (H)

BH 1M
FF

=1 and Bit DAD+2 =0

VSYNC

HSYNC

HBP-

BLANK

\- I 1'--I!
Cyde

D-

D_ BH 1M
APis-AOO(H)

D-

=1 and Bit DAD+2 =1
FA

VSYNC

HSYNC
H

~
HBP-

r----- .

BLANK

'--V

ILl!
Cyda

D-

ttlEC

",PD72020

Figure 5.

DT Signal Output. Mode 1 Bnd Mode 2
A. Mode1
AD1s - ADO (H)
VSYNC

HSYNC

HBP

:--

[2]

[3]

BLANK
[3]

~II L /
E

Cycle

[3]

[1]

I\-!V

B. Mode2

AD1s- ADO (H)

VSYNC

HSYNC

"""""\

HBP

BLANK

Cycle

r--\
[IJ

[4]

ILV LV
OT

l\E

[2]

L II

I/
0'

Symbols
OT Display cycle (data transfer cycle). OT signal is active

Dr signal is inactive.

Dummy display cycle.

Drawing cycle. If no data is drawn, display cycle is set.

[IJ

OT becomes active at display cycle start.

[2J

Dr becomes active when counting of the DAD lower
a bits has terminated (FEH or FFH changes to DOH).

[3]

OT becomes active every four cycles as controlled by
counter that resets at diplay cycle start.

[4]

OT becomes active every eight cycles.
83SL-5710B

3-48

t-rEC

"PD72020

LPEN Command

Figure 7. CSRR Command Format

When the address extension function is set by the
WMASK command (with PN set to 1). the upper 2 bits of
the light pen address (LAD) in the LPEN command are
extended and a maximum of 20 bits can be used.

vMO

When PN = O. the light pen address (LAD) is the same as
with the I£PD7220A.

03
04

dAOL

The LPEN command format with the extended LAD is
shown in figure 6.

dAOH

PMO

I DB6 I DB5 I DB4 I DB3 I DB2 I DBl I DBO
I 1 I 0 I 0 I 0 I 0 I 0 I 0

LAOL

LAOM

I DB6 I DB5 I DB4 I DB31

111 I

EAOL

EAOM

xlxlxlxl

DB2

J DBl I DBO

1 0 1 01 0
EAOH

SCROLL Command

Figure 6. LPEN Command Format
DB7

DB7

LAOH

CSRW Command
When the address extension function is set by the
WMASK command (with PN set to 1). the upper 2 bits of
the drawing execution address (EAD) in the LPEN command are extended.

When the address extension function is set by the
WMASK command (with PN set to 1). the upper 2 bits of
the display start address (SAD) in the SCROLL command are extended.
'
When PN = O. the display start address (SAD) is the
same as with the I£PD7220A.
The SCROLL command format is shown in figure 8. The
built-in RAM map with the extended SAD is included in
table 4.

Figure 8. SCROLL Command Format

When PN = O. the drawing execution address (EAD) is
the same as with the I£PD7220A.,
Address extension causes the WG bits to be positioned
differ:ently in the character/graphics combined mode
(character display/drawing) orthe graphics. mode.
The CSRW command formats are included in table 4.

CSRR Command
When the address extension function is set by the
WMASK command (with PN set to 1). the upper 2 bits of
the drawing execution address (EAD) in the LPEN command are extended and a maximum of 20 bits can be
used.
When PN = O. the drawing execution address (EAD) is
the same as with the I£PD7220A.
The CSRR command format with the extended EAD is
shown in figure 7.

3-49

ttlEC

#,PD72020

Absolute Maximum Ratings

AC Characteristics

TA = +25"C

TA = -10 to +70"C; Voo

Supply voltage, Voo

-0.5 to +7.0 V

Item

= +5.0 V ±10%

Symbol

Min

Max

10,000

Unit Conditions

Input voltage, VI

-0.5toVoo + 0.3 V

Clock 2xCCLK

Output voltage, Va

-0.5 to Voo + 0.3 V

Clock cycle

Icy

125

High-level clock
width

IcH

Low-level clock
width

IcL

Clock ri se ti me

IcR

Clock fall time

IcF

Operating temperature, TOPT

-10 to +70"C

Storage temperature, TSTG

- 65 to + 150"C

Exposure to Absolute Maximum Ratings for extended periods may
affect device reliability; exceeding the ratings could cause permanent damage.

DC Characteristics

Read Cycle

TA = -10 to +70"C; Voo = +5.0V ±10%
Parameter

Symbol

Low-level input
voltage

VIL

High-level input
voltage

VIH

Low-level
output voltage

VOL

High-level
output voltage

VOH

Low-level input
leakage current

IUL

Address setup time tAR
to RD ~

Address hold time
from RD i

tRA

2xCCLK

Except
2xCCLK, WR

RD pulse width

tRRI

tROt
+20

Vec + 0.5

2xCCLK

Data output delay
time from RD ~

tROt

Vcc + 0.5
0.45

IOL = 2.2 mA

Data float delay
time from RD i

tOF

IOH = -400 p.A

RD pulse cycle

tRCY

Min

Max

Unit

-0.5

0.8

Except 2xCCLK

-0.5

0.6

2.2

Vcc + 0.5

3.5
2.5

0.7 Voo
-10

Conditions

p.A VI = OV;.
except
VSYNC, DACK

-500

p.A VI = OV;

p.A VI = Voo;

VSYNC, DACK
High-level input
leakage current

IUH

except
LPEN/WAIT/DT
500

p.A VI = Voo;
LPEN/WAIT/DT

Low-level
output leakage
current

ILOL

High-level
output leakage
current

ILOH

Supply current

-10

Icc

p.A Vo = OV

p.A Vo = Voo

Min

Max

Unit

Input

Output

Input/output

CliO

Clock input

3-50

CL= 50 pF

4.5 Icv

12 Icv

DE = 1

2tcv

Also valid in
DMAcycle

Address setup time tAW
to WR ~

Address hold time
from WR i

tWA

WA pulse width

tww

Data setup time to

tow

Data hold time
from WA i

two

WA pulse cycle

twcv

4.5 Icv

WR recovery time

tRV

2tcv

RD recovery
time

tRV

DE = 0

~iteCycle

WAi

Also valid in
DMAcycie

DMA Read Cycle
tAKR

Condition

DACK hold time
from RD i

tRAK

f = 1 MHz;
o V except for
tested pin

RD pulse width

tRR2

tR02
+20

Data output
delay time from
RD~

tR02

Capacitance
Symbol

DACK setup time
to RD ~

TA = + 25"C; Voo = GND = 0 V
Item

2lcv
+60

CL=50pF

t-IEC

p.PD72020

AC Characteristics (cont)

TA = -10to +70°C; VDD = +5.0 V :tl0%

TA = -10 to + 70°C; VDD = +5.0 V ±10%

Item

Symbol

Min

Max

Unit Conditions

DMA Read Cyc/e(conf)
DREQ output delay
time from
2xCCLK i

leRO

DREQ setup time
to DACK~

1f10AK

DREQ ~ delay time
from DACK~

tAKRO

Item

Symbol

Min

Max

Unit Conditions

/nputCyc/e
75

CL =50pF

0
1.5
lev +

CL =50pF

See Note.

Input signal setup
time to 2xCCLK i

!Pc

ns
Input signal puls,e
tpp
ley
width
Note: Performs two-dimensional rectangular area assignment
whereby the dc parameter is set to other than O. When byteby-byte transfer is specified, the value is 5.5 ley.

80
DACKpulse
cycle

tAKCV

4.5 ley

High-level DACK
width

tAKH

ley

Low-level DACK
width

tAKL

2.5 lev

DACK setup time
to WR~

tAKW

DACK hold time
fromWRi

twAK

Voltage Thresholds for Timing Measurements

Inputs

2.4

0.45

DMA Ht"ife Cycle

Outputs

2icCCLK Input

2 .2
0.8

2.2)C
0.8

22
.
0.8

2.2)C
0.8

3.5

Read/llodifyJVirite Cycle
Address/data
delay time from
2xCCLKt

leA

CL=50pF

Address/data float
delay time from
2xCCLKt

leAF

CL =5OpF

Data setup time to

Ioc

Data hold time
from 2xCCLK ~

leDF

leBI

DBIN delay time
from 2xCCLK ~

leBI

CL=50pF

HAS t

delay time
from2xCCLK

leRSH

CL=5OpF

RAS t

delay time
from 2xCCLK .j.

leRSL

Q=5OpF

High-level HAS
width

If1SH

1/3
ley

tRSL

1.5 ley
-30

2xCCLK~

Low-level
width

RAS

Address setup time
to ARSL.j.

tARSL

83SL-572OA

Display Cycle
Output signal
delay time from
2xCCLKj

leo

CL=50pF

3-51

NEe

~PD72020

Timing Waveforms
Clock 2x.CCLK

83SL-S7!3B

Read Cycle

Invalid

~---------------tRCY----------------~

DB7 -DBo

---------------+<
f------------tRCY------------------!
83SL-5716B

Write Cycle

Valid

".1
DB7 -DBa

Invalid

~----------------twCY ----------------~

Invalid

1-1------tWCY - - - - - - - 1 · 1
83SL·5717B

3-52

NEe

ILPD72020

Timing Waveforms (cont)
Read/Write Recovery

S3SL·5718B

DMA Read Cycle

2xCCLK

DREO

tAKRO
i*--tROAK-

l-tAKH~

tAKL

I'--

tAKR

•

RR2

tRAK

tRD2
DB7 - DBO

Invalid

Valid

tAKCY
83SL-S7148

3-53

NEe

#,PD72020

Timing Waveforms (cant)
DMA Write Cycle
2xCCLK

DREQ

83SL-571SB

Read/MOdify/Write Cycle

-_*';-.--E2--......o---E3----+_-2xCCLK

ADIS-ADo

--+--(1

Valid
Output Data

5BIN ---+---+-~r-------,

83SL-5711B

3-54

NEe

J,tPD72020

Timing Waveforms (cont)
Display Cycle

2xCCLK

A01s-AD O --t---(I

ICRSH

HSYNC-REF
BLANK
VSYNC
LCO-LC3
CSR
CSR-IMAGE
AT .BLlNK-CLC

i5'f
83SL-5719B

Input Cycle
2xCCLK

LPEN
EX. SYNC _ _ _ _ _ _ _ _-'

83SL·5712B

3-55

"PD72020

3-56

~EC

NEe

"PD72022
Intelligent Display Processor

NEG Electronics Inc.

Description
The ~PD72022 Intelligent Display Processor (lOP) performs CRT display control and image display data processing for text, static pictures, and sprites.

Features
o Three display modes: text, semigraphics, graphics
o Four-way horizontal split-screen display
o Smooth-scroll control (vertical, horizontal)
o Sprite image display
o 16-color display
o Attribute addition (7 max)
o Interlaced display through external synchronization
o Up to 256K x 16-bit word video memory addressing
o DRAM refresh
o Optional dual-port RAM
o Bus arbitration control

o CRT control signal programmable variables
- Horizontal display time, retrace time (left and
right), sync pulse width
- Vertical display time, retrace time, sync pulse
width
- Rasters/line
- Blinking time
o Variable display resolution
- Horizontal: 640 dots max (22-MHz max dot rate)
- Vertical: 512 dots max
- Display signal (4 bits/dot) serial output
o Horizontal and vertical external synchronization
o 22 screen-control/drawing commands
o CMOS
o Single + 5-volt power supply

Ordering Information
Part Number

Package

/4PD72022GF-3B9

SO-pin plastic mlniflat

/4PD72022L

58-pin PLCC

50071

3-57

t-IEC

#,PD72022

Pin Configurations
68-PinPLCC

GNP
.LPEN

iiEsET
VRD
SRD

INT
l5MARONAKiBuSRo
READY

AD
WR

Cs
DMAAKNROIBUSAK
ASTB
AD7
ADa
ADs
NC

M N ~ ~ ~ ~ ~ ~ ~ ~

VwL
VWH
VADo
VAD 1
VAD 2
VAD3
VAD4
VADs
VADa
VAD 7
VADa
VDD
GND
VADg
VAD10
VAD 11
NC

83vQ·5910B

tttfEC

p.PD72022

BO-Pin PI•• tic .lInlfl.t

ClI~ I~ ~

~ I'"

xO U Xl; x6' -' ClClCl"''''I-ClZUC:'':
Cl Cl
Cl
a.a..za.Q..m»>:::r:>
(!)zcnc..>

ClK
GND
GND
lPEN
RESET
VRD
SRD

RAS
VWl

VWH

INT

VADo
VAD1
VAD2
VAD3
VAD4

DMARONAKlBUSRO
READY

VADs

VAD6

VAD 7
VADa
VDD
GND
VADg
VAD10
VAD11

i'iMiiAKiVROIBUSAK
ASTB
NC

AD7
AD6
ADS
VDD
AD4
GND

NC
NC

VAD 12
VAD13

S3vQ.S909B

3-59

ttt{EC

pPD72022

Pin Identification
Symbol

I/O

Signal Function

Host System Inte,fsce
ADO-AD7

I/O

Three-state, bidirectional address/data bus. See
table 1.

ASTB

Address Strobe. Read address information from
AD()"AD7'

Bus Acknowledge. While this signal is active,
IIPD72022 controls the system bus.

Out
CLK

INT

READY

System clock.

Chip Select. Enables AD and

Signal Function

Video Memory Read. Strobe signal to read data
from video memory.

VWH,
VWL

Out

Video Memory Write, High and Low. Strobe
signals to write data into video memory.

CRT Inte,fsce
BLANK

Out

Blanking display signal.

DTCLK

I/O

Dot Clock. During Internal DTCLK mode, timing
pulses derlvad by dividing CLK are output.

DMA Acknowledge. Enables DMA cycle.

During external DTCLK mode, the internal
scanning subsystem derlvas a reference clock
from the DTCLK Input.

WFI signals.

Out

DMA Request.

Out

Interrupt request to host processor.

Control signal for reading data or status flag from
IIPD72022.

Out

Indicates IIPD72022 may be accessed for memory
read/Wrlte cycle or I/O read/write cycle.

I/O

Horizontal Sync. Signal output when Internal
sync Is specified; signal input when external sync
Is speciflfed.

Ught Pen Strobe. The DTCLK mode is specified
by the LPEN level when the RESET signal level
rises.

LPEN

LPEN
High
Low

Initializes p.PD72022.

DTCLKMode
Internal DTCLK output
External DTCLK input

Out

Video Memory Acknowledge. Indicates host
processor has direct control of video memory.

PXDo-PXD3 Out

Pixel Data 0-3. Display signal (four bits/dot) in
sync with DTCLK

Video Memory Request. Host processor requests
direct control of video memory.

VSYN

Vertical Sync. Signal output when internal sync is
specified; signal input when external sync Is
specified.

Control Signal for writing data, commands, or
parameters Into p.PD72022.

Out

Column Address St robe.

MOD

Mode change Signal. See

Out

DCo Display Cycle
Other than Indicated below
1
Static picture display cycle
0
Sprite display cycle
Screen start cycle
1

0" 0-

Out

Raster Address 0-1. RAe and RAI are also used for
DMo and DM1, respectively. See Display Data
Control In this table.

RAz-~

Out

Raster Address 2-3. RA:! and R~ are also used for
DCo and DC1' respectively. See Display Data
Control In this table.

RAt

Out

Row Address Strobe.

SRCLK

Out

Serial Read Clock. Used with optional dual-port
RAM.

gAO

Out

Serial Read. Actlva while data Is read from serial
port with optional dua~port RAM.

VAD()"
VAD15

I/O

Video Memory Address 0-15 output; DRAM
refresh addresss output; data Input/output.

VAI6"
VA17

Out

o
1
1

See Video Memory Interface, RA2 and RA3.
DMo,
DMI

Out

RAe,

Display Mode. Specifies the static picture display
mode.
DMI

RAt Is also used for MOD Input.

Video Memory Address 16-17. Also used for
RAI

Display Cycle. Specifies display processing cycle
when p.PD72022 is accessing video memory.
DCl

RAt.

RAe-RAI

Raster Address 4.

I/O

Displsy DBts Contl'Ol
DCo, DC1

IIfdeo lIfImory Inte,fsce

3-60

I/O
Out

Bus Request. Request for system bus control.

Symbol
VRD

0"
1
1

DMo Display Mode
Textmode
0
Semlgraphlcs mode
1
Graphics mode

See Video Memory Interface,

Othe, Pins
GND

Ground

Vee

+5-volt power supply

No Connection

RAe and RAI'

t-fEC

p.PD72022

"PD72022 Block Diagram
Host Processor
Interface Unit

Display Control Unit

Control
Processor Unit

Registers

~
INT

VWl
RAo-RA4

lOUT BUFI

READY
I STATUS

DMAfiQNAK!

VADOVAD15

BUSRQ

~NR~ ~lI-L--------~

SRClK

BUSAK

lPEN

PXDoRESET_

PXD3

VDD-

HSYN

GNDClK -----------.~
DTClK

BLANK
'83SL-5930B

Tsble 1. Functions of Addrellll/DBls Bus AD".AD,

Wit

FiD

AD2

"C!

'Oii.Wd{

ADO
x

Bus Function

Floating (hIgh impedance)

"PD72022 command Input

"PD72022 parameter input

o
0
0

Write operation via DMA transfer

"PD72022 status output

"PD72022 parameter output

o
0

Read operation via DMA transfer

x - Don't care

3-61

"PD72022
I4PD72022 In a Video Display System
IlP072022 lOP

101M
RD

RD
WR
ASTB
PXDo-PXD3

WFI
ASTB

HOS1CPU
f1I'D70108

ADo

-AD?

~:r

1
Latch

~
I--

r-:-

f1I'D71059
Interrupt I-Controller

READY

r----

INT

i-'-

READY

Control
Gate

ViID
VWH

Vw[

YAK

I--

VADO-VAD15

,,
lb~:r
VRQ

r--

V-

~
..-

Not.:
Although the IlPD72022 can execute an
required video memory control operations,
this sysiem example uses bus arbitration
for enabling direct video memory access
by the host processor.

L
16

3-62

RAo-RA4

r--_ I-r--n
,

VSYN
ADO - AD-, HSYN
RAS
CAS

Main
Memory

16124-kHz
MonitOr
TV

I-I--

AS -A19

INT
INTAK

-4--G

Color
Palette
DtA

DTCLK
BLANK

r-r--

Character

Ge:,:tar

~-~
I
Bus
Buller

J5l

t
Bus
Buller

It::=

M• P
Latch

0
Fif

La~ I~

•
Mux

00-015
Video
Memol)'

AO -A'll

-.I AS -A15

NEe

"PD72022

Absolute Maximum Ratings
= +25'C

DC Characteristics
= -10 to +70'C; voo =

Power supply voltage, Voo

-0.5 to +7.0 V

Parameter

Input voltage, VI

-0.5 to +7.0 V

Output voltage, Vo

-0.5 to +7.0 V

+5 V :tl0%

Symbol

Min

Max

Input low
voltage

Vil

-0.5

0.8

Note 1

-0.5

0.6

Note 2

Input high
voltage

VIH

2.2

Voo + 0.5

Note 1

3.5

Voo + 1.0

Note 2

Output low
voltage

VOL

0.45

10l

= 2.2 mA

Output high
voltage

VOH

10H

= -400p.A

Input
CI
10
pF Unmeasured pins
capacitance
returned to 0 V
~---------------------20
pF
Output
Co
capacitance

Input low
leakage current

Ilil

-10

p.A VI

= OV

Input high
leakage current

IliH

p.A VI

= Voo

Input/output
capacitance

Output low
leakage current

IlOl

-10

p.A VI

= OV

Clock input
capacitance

Output high
leakage current

IlOH

p.A VI

= Voo

Power supply
current

100

150

Operating temperature, TOPT

-10 to +70'C

Storage temperature, TSTG

-65 to +150'C

Capacitance
TA

= +25'C; voo = GND = OV; f = 1 MHz

Parameter

Symbol

Min

Max

Unit

Conditions

Unit Conditions

0.7Voo

Notes:
(1) Except ClK, DTClK, and RESET
(2) ClK, DTClK, and RESET

AC Characteristics
TA = -10to +70'C; voo = +5 V :tl0%
Figure

Symbol

Min

Max

Unit

System clock cycle

Icy

System clock width, high

iKKH

System clock width, low

tKKl

Dot clock cycle

IcYDK

4 Icy

Input; Cl

67.5

4 Icy

Output; Cl = 30 pF

Input; Cl

iKKH

Output;

Parameter

Conditions

Clock

Dot clock width, high

toKDKH

toKDKL

Reset
RESET pulse width

~SRSl

8 Icy + 6 IcYDK

lPEN setup time to RESET t

tslPRS

16 Icy

lPEN hold time from RESET t

~RSLP

Dot clock width, low

ns
ns

= 30 pF
= 30 pF

Q =

30 pF

CPU Rud/Write Cycle
ASTB pulse width
Address setup time to ASTB

Address hold time from ASTB

'C'S' setup time to Rl5 or WR ~

4,5

tsTSTH

4,5

tsAST

4,5

~ST

4,5

tSCSRW

3-63

~EC

#,PD72022

AC Characteristics (cont)
Parameter

Figure

Symbol

4,5

!tiRWCS

4,15

IRRL

170

Min

Max

Unit

Conditions

CPU Rad/Wrlte Cyde {cont}
~ hold time from

RI5 or WR t

Fm pulse width
Data delay time from

Fm ~

4,15

toRO

120

Data hold time from RI5 t

4,15

!tiRO

Data float time from 1m t

4,15

fFRO

WR pulse width

5,16

"vwL

180

Data setup time to WR t

5,16

'sOW

100

WFr t
READY delay time from 1m or WR ~

5,16

!tiwo

Data hold time from

4,5,
16

toRwRDV

ns
ns
ns
ns
ns
ns
ns
ns

READY delay time from 'i7ml ~

tovQRDV

1m recovery time
WFr recovery time

150

IftJR
IfIIIW

150

Read access cycle

feVA

IfIRL + 10 fey

Write access cycle

fevw

\vWL +10 fey

6-8,
11-13

tcVAAS

mwldthhlgh

6-8,
11-13

IfIASRASH

mwldthlow

6-8,
11-13

IRASRASL

~wldthhlgh

6-7,
11-13

~wldthlow

wr.ur IludIWtltfl Cyt:Ie
Random read/Wrlte cycle

Note 1; also refresh cycle

Note 2; also data transfer cycle

130

Note 1; also refresh cycle

210

Note 2; also data transfer cycle

IcAScASH

110

6-7,
11-13

fcASCASL

105

6..a,
11-13

toCASRASL

ns
ns
ns

6-7,
11-13

toRASCASL

t delay time from ~ J.

6-7,
11-13

toCASRASH

~ delay time from ~ t

~ J. delay time from m

270
360

Address setup time to m

6-8,
11-13

Address hold time from m

6-8,
11-13

185

Note 1
Note 2; also data transfer cycle

Note 1

150

Note 2; also data transfer cycle

tsw.RAS

!tiRASVA

Mode setup time to ~ J.

6-7,
11-13

'sMOCA8

Mode hold time from ~ J.

6-7,
1,;,3

IHCASMO

110

Note 1

185

Note 2

3-64

t\'EC

"PD72022

AC Characteristics (cont)
Parameter

Figure

Symbol

6,
12-13

toCASVR

CAS t delay time from i7RD t

6,
11-13

tDVRCAS

i7RD pulse width

6,
12-13

tVRVRL

VRAAf RIIBd/Write Cycle (cont)
i7RD t delay time from CAS .j,

CAS .j, delay time from VW t
VW .j, delay time from m t
VW .j, delay time from CAS t
Input data setup time to i7RD t
Input data hold time from i7RD t
i7RD t delay time from m .j,
m

.j, setup

time from VRD

i7RD .j, hold time from m

.j,

Min

MIX

Unit

Condltlonl

Note 1

150

Note 2

Note 1

150

Note 2

tOVWHCAS

toRASHVW

toCASVWL

tsDVR

tmRO

ns
30

130

Note 1

210

Note 2

tSVRRAS

6,
12-13

IHRASVR

tovRRAS

toRASVRL .

130

6,
12-13

tORASVRH

6,
12-13

VRAAf lItite Cycle
from i7RD t
i7RD .j, delay time from m .j,
m.j, delay time from ilW t
VW t delay time from m .j,
CAS .j, delay time from ilW .j,
VW t delay time from CAS .j,
ilW pulse width
Data setup time to CAS .j,
Data hold time from CAS .j,
m.j, delay time

tovwRAS

toRASLVW

-10

tovwLCAS

toCASVWH

155

tvwvwL

165

tsOCAS

IHCASO

155

toRASHCAS

VRAAf IlefrINIh Cycle

CAS .j, delay time from m

VRAAf Request

YAK setup time to CAS t
liAR hold time from CAS .j,

tsvACAS

IHCASVA

VRQ recovery time

lANa

10 Icy

READY delay time from \iRl:l.j,

tovaRDY

ns
ns
ns

t
VAD float delay time from CAS t
VAD delay time from CAS t

IHRovva

9,10

1f:CASVAD

\iRl:l

hold time from READY

9,10

toCASVAO

Interleave mode

0
30

3-65

NEC

#,PD72022

AC Characteristics (cont)
Parameter

Figure

Symbol

Min

Max

Unit

Condltlon8

ImAM Requflllf (cont)
~

J. delay time from ~ f

m:JSRO f
BiJSAi( hold time from BDSm:! J.
~ hold time from

toBASa

IHBQHBA

IHBQLBA

toSKVR

100

IHvRsK

100

tevRRASL

IHRASLVR

2000

Dual-port mode

oat. Tr."""'r Cycle
vm:i f delay time from SRCLK f
SRCLK hold time from

wm f

m Jo delay time from vm:i J.
vm:i hold time from m J.
vm:i hold time from ~ J.
f delay time from VFiO J.
~ f delay time from vm:i f
vm:i hold time from FiAS f

11
11
11

IHCASVR

tevRRASH

100

tevRCAS

120

IHRASHVR

ImAM Serl.' Rud Cyc/fI
sm:; width high

12,13

tsRSRH

200

SRI:) width low

12,13

tsRSRL

200

SRCLK J. delay time from SRI:) J.

12,13

toSRSK

SRCLK width high

12,13

tsKSKH

SRCLK width low

12,13

fsKSKL

Serial read cycle

12,13

tcVSK

tsDVR

lHvRo

ns
ns
ns
ns
ns

Data 8etup time to SRCLK f

tsOSK

Data hold time from SRCLK f

IHSKD

Data setup time to

wm f

Data hold time from vm:i f

Graphlcil display cycle

Text display cycle
Semlgraphlca display cycle

01.111, TIming
Output display time from DTCLK f

toOKDSP

. ns

Note 3;

Input setup time to DTCLK f

tslOK

Note 4

Input hold time from DTCLK t

lHoKl
1i1.

Input pulse wldt!)

6tcVOK

DIIfA Cycle

IlMAlm f delay time from m:.tO:R J.
~ J. delay time from !mAAR t

15,16

toOAOQH

15,16

toOAOQL

llliiiAAR hold time to !mARK J.
llliiiAAR setup time to AD J.
DliilAAR hold time to RD t
m.1MR setup time to WR J.
~ hold time to WR t ..

15,16

IHOOOA

tsOAR

.15

IHROA

.16

tsOAW

IHWOA

3-66

= 50 pF

NEe

#,PD72022

AC Characteristics (cant)
Paramater

Figure

Symbol

INT rising time

INT falling time

Min

Max

Unit

tlNTR

tlNTF

Conditions

Interrupt

Notes:

(1) Cycles: Text display; Semigraphics display; Display start
(2) Cycles: Graphics display; Sprite display; Command processing
(3) HSYN, VSYN, BLANK, PXDO·PXD3
(4) HSYN, VSYN, LPEN

Figure 1.

Figure 3. Reset rMlveform

Voltage Thresholds for Timing
Measurements

Output

2.2V
K=~.4V
~-=;...:.....----0.8 V

•.

0.4 V

Clock
InputJOutput

~ 2.2 V

3.SV
K=

...:0"".8:.,.::V_____

LPEN

0.6 V
49NR-478A

Figure 2.

Clock rMlveform

=~ --r"~y"'-l
~~-----tCYDK----J---.j~
49NR...t79A

3-67

"PD12022
FIgute 4. CPU ReIId Cycle

ASlB JISTSTH-=t

ISAST--J1:--IH-A-ST----------------~------------~

Hi-~(,-_ __

ADo-A07 _ HI-Z

i+------1RVR-----+j
~---------ICYRI--------~

IDRWRDY 1+---+1
READY- -

Hi-Z

HI-Z

49NR-434B

Figure 6. CPU . .lte Cycle

AQ)-A07

Valid Address

I+-----IRVW'------~
I+--------ICYW-------~

IDRWRDY 1+----+1
READY- -

Hi-Z

49NR435B

3-68

ttiEC
Figure 6.

"PD72022

VRAII Read Cycle
tCYRAS
tRASRASL

}

RAS

I--- tRASRASHIDCASRASH

-tDRASCASL

'+- tDCASRASL -

IDRASHVW-

~ICASCASL}

-.I
IDCASVWL

J1C,ASCASH
ISVARAS

VAl s [RAo]/DMl. VA17 [RA1] IDMj
RA2/DCo. RA3IDCl

IHRASVA

Valid Address

IDVWHCAS

)(

Mode
IDCASVR ---..

ISVRRAS
I

~ .1.

IHCASMD-

IDVRCAS

IDRASVRH
~

k-'HRASV~1

I--IVRVRL-

\\\\~

VRD

1/
ISDVR!==:

VA~-VAD15

RAMMOD

Hi-Z

- -

Valid Address

Hi-Z

- -

--{

Valid Data

~i-Z
:" -=<
49NR-4368

3-69

NEe

#,PD72022

Figure 7. VRAII Write Cycle
ICYRAS
IRASRASL
RAS

I-- tDCASRASL -

IDCASRASH

_IDRASCASL

I--- tRASRASH - - -

I\,l+--lCASCASL
CAS

-.I

_~C(SCASH
tSVAR'IS

)

VA16 [RAollD~. VA17 [RA111DM1
RA2IDCO. RA3/OC1

IHRASVA

Valid Address

tDRASLVW~
*--- tDVWRAS - - -

I---tHCASMD 1St=:

K>{

Mode

IDCASVWH

--tDVWLCAS-7
tvwvwr

-tDVRRAS
VRD

Hi-Z
VADo-VAD15 ~--

RAMMOD

Hi-Z

Valid Address

IDRASVRL

C
K>{
~-

\J"
tHCASD

Valid Data

- -

.t:!!:Z

Hi-Z

---(

- - -

-'-<
49NR-437B

NEe
Figure 8.

I'PD72022

VRAM Refresh Cycle
ICYRAS
lRASRASL

ISVARAS

)

VADQ-VAD1S
RA4/MOD

- -

Hi-Z

IHRASVA

Valid Address

I
VRD

1"-

I--IDRASHCAS~

LIDCASRASL -

VA16 (RAoJIDMJ, VA17 [RA1J/DMl
RA2/DCo. RAJ/DC,

I--- lRASRASH-

Mode

\
Valid Address

r-----

Hi-Z

-----49NR-438B

Figure 9.

VRAM Request; Interleave Mode

VRQ

VAK

IFCASVAD
VAD

~~:- ) -

Hi-Z

49NR·439B

3-71

NEe

~PD72022

Figure 10. VRAM Request; DuIII-PoTt lIode

IHBOLBA

~'---

_ _ _ _ ){)r'---+_----;rJ--t--.J.

IOCASVAD
VAD -

-if--

Hi-Z

- - -

-//-

C::3- --

.--IFCASVAD

Hi-Z

49NR-440B

3-72

ttlEC

"PD72022

Figure 11. Data Transfer Cycle
tCYAAS
tRASAASL

I\-

II
-tAASAASHtDCASRASH

I-- tDCASAASL -+- -tORASCASL

-tCASCASL-CAS

~
tCASCASH
tSVAAAS

VA16 [AAol 1DMl, VA17[AA11IDMj
AA2IDCO. RA31OC1

VWH. VWL

.1 ItHAASVA

Valid Address

tHCASMO-

tSt=:

---

Mode

tOVARASH

tHAASHVA

I - - 1--+

tHCASVA-

I-- tOVARASL..... I+----'-'- tHRASLVA-

\
SAD

~tDVACAS

J
tDSKVA

SACLK

VA~-VAD15

RAMMOD

r---

lHVASK

~
-

Hi-Z

\
<

Valid Address

>-----

Hi-Z

- - - - -49NR·441B

3-73

"PD72022

i+----------tCyRAS----------i
1+-----tRASRASl----~

tRASRASH
tDCASRASl--tDRASCASL---;0-/4-===~

tSVARASI+----+J

VA16 [RAoJIDt.t. VAt7[RA1J/DMj
RA2/DCa. RA3 ID01

---'"..p...---:-:-----f

1-11-------..-itSRSRL----------t

tDSRSKI4-i--~

SRCLK

VADo-VAOts

RA4IMOD -

H" Z
"-

1.---------.1
{1.-__
VaI_Id_Addr_8_SS_---'

!!!;Z_

--(~-49NR-442B

3-74

NEe
Figure 13.

#,PD72022

VRAM Serial Read Cycle; Text or Semigl'llphics Display
~-------------------tCYRAS-------------------~

t+--------tRASRASL---------~~
RAS

tDCASRASH
~ tDCASRASL-

CAS

---.I

~ tRASRASH - - - -

tDRASCASL

1r-_ _ _-++______..,.I\--tCASCASLI~------

ji
_~CASCASH

IsvARAst+-----I- j

i----tHCASMD

: tHRASVA
VA16 [RAoJ/DtvtJ. VA17 [RA1J/DM1
RA2IDCo. RA:l/DC1

)

~tSE"M_DC_A_S.....;_ _ _ _ _ _ _ _ _-'-t=_ _ _ _ __

Valid Address

Mode

----'r...p.----..,'-:----f

~tDCASVR---.
VWH. VWL

tDRASVRH

tSV~RASr-

I+-tHRASV~1

\\\\~

VRD

tSRSRL
SRD

IDVRCAS

~IVRVRL---

l--tSRSRH--j

tDSRSK

f ; - - - tCYSK

I-tSKSK~

----r-y~
SRCLK
,

y~~
/\
'--_-oJ

I - tSDVR ---0 1--0

tSKSKH~

VACo-VAD1S -

RA4/MOD -

1---

Hi-Z
-

IHVRD

Hi-Z

Valid Address

Hi-Z
Valid Data

I\.-

.~------------~

_Hi-Z_

~
~

Valid Data

I~'Z./
\,

~-----~

~---------

49NR-443B

3-75

fttIEC

"PD72022
Figure 14. OI.18y TIming

1~DKF
DTCLKtDJt.tDKDKH~
tDKDKly____. .t\\,.K
. _______)
t

BLANK. PXDo-PXDa

DTCLK J

OOKDSP

HsVN. VSYN,

- - - - - - - - -......
'--_ _ _ _ _ _ _ _...J

V--

'--_ _ _ _ _ _ _ _....." - -

'---

f-~ ~~~'3J=

-HS-Y-N,-VS-YN,- lPEN _ _ _ _ _.....

49NR·4448

FIgure 15. DMA Rud Cycle

Flgute 1t1. DMA write Cyt:le

FlguTe 17. Interrupt IIItvefcH"m
tlNTR1
INT

, tINTF

"L41NR0447A

3-76

ttrEC

"PD72022

INTERNAL STRUCTURE

Table 2. Us, of Commands (cont)

The IlPD72022 IDP consists of three units: host processor interface unit, control processor unit, and display
control unit. Refer to the IlPD72022 Block Diagram.

Name

Host Processor Interface Unit
The host processor interface unit transfers commands,
parameters, and such status information as the
IlPD72022 internal processing state, to and from the
host processor.

Function

WdBo .emory Control
DPLD

Specifies video memory operation address or address
offset.

DPRD

Determines video memory operation address.

MASK

Sets bit mask for data storage In video memory.

RDAT

Reads contents of video memory and sends data to
host processor.

WDAT

Stores transfer data In video memory.

BLKTOT

Reads the video memory contents and transfers the
data via DMA operation.

BLKTIN

Stores the data transferred via DMA operation Into
the video memory.

The control processor unit reads and executes commands and parameters from the host processor via the
host processor interface unit.

EXIT

Terminates video memory operation command
processing.

Display data processing In video memory, display address control, screen control, etc., in the display control
unit are implemented.

SPRON

Enables the sprite controller and Initiates sprite Image
display.

SPROF

Disables the sprite controller and terminates sprite
Image display.

Display Control Unit

SPRSW

Toggles the sprite display on or off for each sprite
operation.

Control functions include asynchronous bus interface
control, DMA control, and interrupt control.

Control Processor Unit

The display control unit generates and outputs video
memory display addresses, display signals, and·· CRT
control signals. It generates various timing signals required in the IlPD72022.

Sprite Control

SPRRD

Reads the sprite attribute table data.

SPRNR

Writes data Into the sprite attribute table.

SPROV

Determines the sprite controller operation status.

COMMANDS
The IlPD72022 has 22 commands for implementing initialization, display control, and sprite control operations. See table 2.

Name

.Function

,,,,,t.llzlltlon
SYNC

Selects display operation mode and IIpeclfles
scan timing.

Display Control
DSPOF

Generates screen control table base address and
border color; enables display controller; starts
display.

DSPOP

Disables display controller and terminates
display.

DSPDEF

Defines display screen Iaycutand display format.

CURDEF

Defines cursor di splay format.

ACTSCR

Selects active screen area.

CURS

Moves cursor to specified cursor display position.

LPNR

Determines light pen position.

3-77

~EC

"PD72022
INITIALIZATION COMMANDS

• EV (Enable Vertical Blank Interrupt)

SYNC Command

Parameter EV determines whether the occurrence of a
vertical blanking signal causes an interrupt signal to
be generated on the INT pin.

Command Code 10H

Parameters

I
I

EV
ES

I
I

VM
FW

I
I

I DPM I ILM
RS

LBL
LBR
HAD

• EL (Enable Light Pen Interrupt)
Parameter EL specifies whether the occurrence of a
light-pen signal causes an interrupt signal to be
generated on the INT line.
EL
o
1

RBR

RBL

TBL

TBR

VAD (H)

BBR

BBL

VAD (L)

• ILM, DPM (Interleave Mode, Dual Port Mode)
The format of the interblock interface between the
host system, lOP, and video memory is specified.
Dual-port mode can only be specified for the VAAM
serial access (VM = 1).
DPM

o
o
1
1

3-78

ILM
0
1
0
1

Operation
Standalone mode
Interleave mode
Dual-port mode
Disabled

Interrupt
Light pen interrupt disabled
Light pen interrupt enabled

• VM (VAAM Access Mode)
Parameter VM specifies the video memory access
mode for static picture display data generation.
VM

The SYNC command terminates display controller operation and defines operation mode and horizontal/vertical
scan timing with the following parameters.

Interrupt
Vertical blank interrupt disabled
Vertical blank interrupt enabled

Video Memory
Random access mode
Serial access mode

• RM (Raster Mode)
Parameter RM specifies CRT scanning mode and
display signal generation mode.
RM
00
01
10
11

CRT Scanning Mode
Noninterlace (640 x 400, 24K CRT)
Interlace (640 x 400, 15K CRT)
Vertical magnify (640 x 200, 24K CRT)
Normal (640 x 200, 15K CRT)

• RS (Resolution Select)
Parameter RS specifies the divide ratio for generation
of the display signal dot time. This ratio can be
combined with horizontal and vertical scan timing to
vary display resolution. Table 3 is an example based
on a 20-MHz source clock.

NEe

"PD72022

T.ble3. DlIIP'.Y /lestJIutlon Example (2O-IIHz Clot:k)
RS

Divide Ratio

Corresponding Resolution

HAD Setup Value

VAD Setup Value

Recommended CRT

000

Divide by 4

256 x 192

256 (63)

192

Horizontal scan frequency 15.75 kHz

001

Divide by3

320 x 200

320 (79)

200

010

Divide by 2

512x 192

512 (127)

192

011

Divide by 1.5

640 x 200

640 (159)

200

100

Divide by 1

640 x 400

640 (159)

400

Others

24.83 kHz

Disabled (dot clock Is net output)

• RIf (Reverse Screen)
Parameter RV specifies reverse display of the entire
screen. When RV is cleared to 0, normal display is
enabled; when RV is set to 1, text foreground and
background colors in the text display are reversed.
• ES (External Sync)
Parameter ES specifies use of the HSYN and VSYN
pins and external synchronization. When ES is set to
1, horizontal and vertical synchronizing Signals are
output on the HSYN and VSYN pins.
When ES is cleared to 0, the pins are placed in a
high-Impedance state, and display timing is synchronized with an input reference signal.
• EC (External Clock)
Parameter EC specifies DTClK pin operation and
determines display timing signals. When EC is set to 1,
a signal generated from the internal divider is output
on the DTClK pin as dot clock.
When EC Is cleared to 0, the DTClK pin Is placed in a
hlgh-impedance state, and display timing is based on
an Input clock reference signal.
EC an be set in external dot clock input mode (LPEN
signal is low at reset time).
• RF (Refresh Control)
Parameter RF controls video memory refresh operations. When RF Is cleared to 0, no refresh operation is
performed; when set to 1, refresh operations are
Initiated.

• LBl (left Blanking) See figure 18.
LB R (Left Border)
HAD (Horizontal Active Display)
RBR (Right Border)
RBl (Right Blanking)
HS (Horizontal Sync)
Horizontal scan timing is specified in four-dot time
(TCK) units. Each timing is generated at the time of
(specified value + 1) x TCK.
The horizontal scan parameters have the following
restrictions.
HS;;: 04H
lBl;;: 03H
HAD = odd number (bit 0 = 1)
• TBl (Top Blanking) See figure 18
TBR (Top Border)
VAD (Vertical Active Display)
B B R (Bottom Border)
B Bl (Bottom Blanking)
VS (Vertical Sync)
The number of rasters (vertical scan lines) is specified
to control vertical scan timing. An integer multiple of
2 is set In the valid display time (VAD). The vertical
border time (TBR, BBR) can be omitted if the specified value is O.
The vertical scan parameters have the following restrictions.
VS;;: 04H
TBl + TBR ;;: 10H (for non-sprite display)
TBl + TBR ;;: 20H (for sprite display)
VAD;;: 04H
BBR + BBl ;;: 02H

3-79

I'PD72022
Figure 18. Horlzonl,,' .nd "",,/a'Selln P.ramel.ra

'.'.

I
I

~,.V--16 color

83v0-5925B

FiguTe 24. Data Row in Graphlcsllode
,

Display Screen

Video Memory

-,
n rasters
m dots

n rasters
lOP

Graphics memory

~
Color specification

83vO-59269

3-92

t\'EC

"PD72022

Figure 25. 0111. Row IJrH'ing Sprite/mage Display
Display Screen
Video Memory
YP

r--'--

Sprite attribute dala
lOP
YSIZE

..-----

XSIZE II

YP
XP

SPDA
Attribute

'--

SPDM

Attribute,
color specification

Display position
control

I
Sprile pattem data

3-93

fttIEC

"PD72022
Figure 26. Example of Screen Split Displey
Video Memory

-t

J:=~==~VW~1:===~~.

VSA1 ~

RSA1

VH1

c::r
A"; L.. _ _ _

Display Screen

__~I~·__~~~0Th~~R_W_1_.2_._3::::::::::::~·1

Virtual Screen 1

(RXP 1. RYP 1)

1-------VW3------VSA3

ABC

6L..

Virtual Screen 3

1
RH1

~.-."

laJl QQ ~,
(RXP 2. RYP 2)

RSA3

-t--±.

"'"_, I

VSA2

(RXP 3. RYP 3)

RH3

Display

RSA2

&--

Real Screen 3

ILnll ®,
L.::

Virtual Screen 2

VH 2

I-------i-~
83vQ·5928B

Scan Mode Specification
The I'P072022 lOP enables specification of four scan
modes by using SYNC command parameter RM before
video signal generation. See figure 27.

To use the interlace mode, a value appropriate for the
16-kHz monitor must be set in the raster parameter and
the interlace synchronizing signal must be input from an
external source.

Noninterlace Mode.The raster address Is incremented
for each horizontal scan. The display data address is
updated every specified number of rasters.

Vertical Magnification Mode. The raster address is
incremented every two horizontal scans. The display
data address is updated every specified number of ras·
ters.

In graphics mode, the display data address is updated
each horizontal scan.

In graphics mode, the display data address is updated
every two horizontal scans.

Interlace Mode. Odd and even fields are displayed
alternately. In the odd field, the raster address starts at 0;
in the even field, it starts at 1. The raster address is
incremented by two for each horizontal scan.

Normal Mode. The raster address is incremented each
horizontal scan. The display data address is updated
every specified number of rasters.

In graphics mode, the display address is updated so that
display data in the opposite field is skipped.
In interlace mode, the MRA value must be specified so
that the numbeer of rasters is even.

3-94

In graphics mode, the display data address is updated
each horizontal scan.

NEe

"PD72022

Figure 27. Scan Modes
A. Noninterlace Mode

C. Vertical Magnification Mode

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Dot Position ICG Image]
7 6 5 4 3 2 1 076 5 4 3 2 1 0

640 x 400 data is displayed on a 24.8-kHz CRT.

640 x 200 data is displayed on a 24.8·kHz CRT.

Dot Position ICG Image]

D. Normal Mode

B. Interlace Mode

Dot Position ICG Image]

Dot Position ICG Image]
7 6 5 4 3 2 1 0 7 6 5 432 1 0

Odd 0
field

Raster
Address

++++++++-+-'-+-+-+-'e-f-+

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Even
1 field

+++-r-~r1-+-+-+~~++-r-r7

+-t-~-+-r+-~r+-r1-t-~-+7
640 x 400 data is displayed on a 15.8-kHz CRT.

640 x 200 data is displayed on a 15.8·kHz CRT.
49NR·4758

3-95

"PD72022

3-96

t-IEC

ttlEC
NEe Electronics Inc.
Description
The IlPD72120 Advanced Graphics Display Controller
(AGDC) displays characters and graphics on a raster
scan device from commands and parameters received
from a host processor or CPU. Features of the AGDC
include high-speed graphics drawing capabilities, video
timing signal generation, large capacity display memory
control Qncludlng video RAMs), and a versatile CPU
interface. These features allow the AGDC to control
graphics drawing and display of bit-mapped systems.

Features
Cl

High-speed graphics drawing functions
- Graphics drawing: dot, straight line, rectangle,
circle, are, sector, segment, ellipse, ellipse are,
ellipse sector, and ellipse segment
- Maximum drawing speed
500 ns/pixel (8 MHz, pixel mode)
500 ns/dot (8 MHz, plane mode)
- Area filling (high-speed processing in word units):
triangle, trapezoid, circle, ellipse, and rectangle
- Painting: filling of any arbitrary enclosed area (bit
boundary retrieval)
- Data transfers In display memory: multiplane
transfers; data transformation (90°/180°/270°
rotation and reversal); multiwlndow transfers;
maximum transfer speed of 500 nS/Word
-Image processing: slant, arbitrary angle rotation,
16/N enlargement, and N/16 shrinkage (N any
integer from 1 to16)
- Position specification by X-V coordinates
- logical operations between planes

"PD72120
Advanced Graphics Display Controller

Cl
Cl
Cl
Cl

Video timing Signal generation
- High-speed processing by two system clocks:
display (for video sync Signal generation) and
graphics drawing clocks
- External synchronization capability
Large-capacity display memory
- Display memory bus Interface: 24-bit address and
16-bit data bus for addressing up to 16M words,
16 bitS/Word
- Video RAM (VRAM) control
- Display memory bus arbitration
Host processor (CPU) interface
- System bus Interface: 20-bit address bus, 8- or
16-bit data bus
- Data transfer with external DMA controller: from
system memory to display memory (PUT); from
display memory to system memory (GET)
- High-speed pipeline processing with preprocessor
before drawing processor
- CPU memory or I/O mapping of Internal registers
and display memory for efficient system interface
8-MHz system clock
CMOS technology
Single +5-volt power supply
Packages: 84-pin PLCC, 94-pin plastic miniflat

Ordering Information
Part No

Package

"PD72120L

B4-pln PLCC

"PD72120GJ-5BG

94-pln plastic mlniflat

eooe8

3-97

NEe

"PD72120
Pin Identification
Symbol

I/O

Signal Function

Clock Pi".
ClK

SClK

Clock supplied to circuits other than the sync
signal generator and display processor. The
drawing processor and preprocessor speed
depend on this clock frequency.

Symbol

I/O

OA16-OA23

Out Upper 8 bits of display memory address (the lower
16 bits of the 24-blt address are output on DADoDAD1sl·

OASTB

Out Indicates that a display memory address Is
present on the falling edge.
Out Defines the dala formal for accessing the display.
RESET sets both pins low.

Clock supplied to the sync signal generator and
the display processor. This clock frequency is
determined by the CRT timing requirements:
horizontal sync frequency. number of dots per
line. etc.

DUBE
AGDC
-016-bit CPU 0
el16-blt CPU 0
8116-bit CPU 1
1
8-blt CPU

System Bus Control Pins
ADo-AD15

ASTB

Data Access Format
Word
Word
High (odd) byte
low (even) byte
High (odd) byte

I/O bus to the CPU consisting of multiplexed
16-bit address and a bidirectional data bus.

Upper four address bits of the 20-blt address.

Latches the address on A16"A19 and ADo-AD15 on
the failing edge.

DWR

Out Controls writing to the display memory by the
AGOC. Set high by RESET.

Together with ADo. defines the data access format
as shown below. UBE should be tied high when
connected to an 8-blt CPU.

HlDRQ

HlDAK

Out Indicates that the AGDC memory bus (DADoDAD15 and DA16-DA23 Is In high-impedance state
so that an external device can have access to the
display memory bus. Set high by RESET.

o
o
1
1

UBE
0
1
0
1

Data Access Format
Even-address word
Even-address byte
Odd-address byte
Odd-address byte

Performs a read of data from the AGDC by the
host CPU.

Performs a write of data to the AGDC from the
host CPU.

Enables reading/writing of the AGDC Internal
registers by the host CPU. The register Is
selected by the address input on ADo-AD7'

Enables reading/writlng of display memory
through the AGDC by the host CPU. The display
memory address Is generated by the address
Input on A16-A19 and ADo-A015 and by the bank
register.

READY

Out Activated by the data access request (lIDiWFl) for
the AGOC. During the access, the signal may be
low. RESET will set the READY line high.

INT

Out Signals an Interrupt from the AGOC.

OMARQ

Out Indicates a requestfordata transfer (PUT/GET) to
an external OMA controller. OMARQ will be low
after RESET.
In

Acknowledgment of OMA request to the AGOC by
the OMA controller.

Initializes operation of the AGOC. The Internal
parameter register Is not cleared by RESET Ot Is
Initialized by setting data).

OisplBy.IIIIfOI'Y Control Pins
DAOO-DA015 I/O

3-98

DlBE
-00
1
0
1

I/O

ADo

RESET

Signal Function

I/O pins for display memory; 16-bit address
multiplexed with dala.

Out Controls reading of the display memory by the
AGOC. Set high by RESET.

Requests control of the display memory bus by
an external device to transfer display data.

Iofdeo Timing Signal Related Pins
VS/EXVS

I/O

When the AGDC operates as the master. VS Is the
vertical sync signal output. When the AGOC
operates as a slave. the EXVS input initializes the
internal vertical sync Signal on the rising edge.

HS/EXHS

I/O

When the AGDC operates as the master. HS Is the
horizontal sync signal output When the AGDC
operates as a slave, EXHS Initializes the internal
horizontal sync signal on the rising edge.

Display Signal Related Pins
BLANK

Out Used to blank the display.

l5i/DiS'P

Out Set to OT In the OT mode (when using VRAMs)
and specifies the data transfer. In the cycle steal
mode (VRAMs not used). indicates the display
cycle.

GCSR

Out Specifies the display of the graphics cursor

GWAIT

Out Graphics walt signal

Other Pins
Voo

+5-volt power supply

GNO

Ground

Internally connected; leave unconnected

NEe

"PD72120

Pin Configurations
I14-Pin PLeC

AD12
ADS
AD13
ADs

VDD
GND
SCLK

AD14
AD7
AD1S
VDD
GND

GCSR
VSlEXVS
HSlEXHS
BLANK
DT/DISP

Au;
A17
A18
A19
ASTB
UBE
ClK
DADo
DADl
IC
DAD2
IC

HLDRQ
HLDAK
DWR

DAD
DASTB
WAIT
GND
DLBE
DUBE
DA23
DA22
IC

49NR-394B

3-99

::i

10
c

C'i

i
=
~~~o

CD ....,

CJ)

CUI...., •

en "'"

UI N

I\)

CI~»»~<~>~>~>~~
................ zc .... 0 .... 0 .... 0 .... z

~OCOr-2:l1111::CD~
'" N .... 0
"
\"II \,1 m CD

~
.....

~~~~~m~~~~w~=O~CD....,CJ)UI.""'N~

DADS
DAD4
DADs
DADs

AD4
ADll
ADs
ADl0

DA07
DADa

AD2
AD9
ADl
ADa
ADo
VDD
GND
GND

DADs
DAD10
DADll
DAD12
DAD1S
DAD14
DAD15

JC
JC

AD
CSDM

GND
GND

CSIR
GND

VDD
DA16
DA17

IC
RESET

READY
INT
DMAAK
DMARO

DA18
DA19
DA20
DA2l

tt~~~~~~~~~~8~~~~~m~mm~~

ODODOOwOOODOOOOOOOOOOODO

('1~~~~OO~~O~~~
00 0101~ ~ ~ ° °IOIZIZ 0 °lm
Z

iJPD41264
Display Memory

Character
ROM

UE~~' II II

HLDAK

cr.

t f t

t- -- I -

Dr/DE f--

HLDRO

I-

CSDM

J--.f Cursor Control Circuit

CSIR

Control
I

h
Data

Address

Display Memory Buses
49NR·3938

3-102

ttlEC

"PD72120

ELECTRICAL SPECIFICATIONS
Capacitance

Absolute Maximum Ratings

TA" +25°C;Voo - GND - OV

,TA" +25°C

Parameter

Symbol

Max

UnIt

Input

-o.5to +7.0 V

Output

Input!
output

Co
Cue

-0.5 to + 7.0 V

Supply voltage, Voo

-o.5to +7.0V

Input voltage, VI
Output voltage, Vo
Operating temperature, TOPT

-10 to +7O"C

Storage temperature, TSTG

-65 to + 15O"C

Power diSSipation, Po

1.1 W

Clock
Input

Min

Condition
f-1MHz;
unmeaeurad
pins returned
toOV

DC Characteristics
TA

= -10 to

+7O"C; voo .. +5.0 V :1:10%

Parameter

Symbol

Low-Ievel Input voltage
High-level Input voltage

VIH

Low-level output voltage

VOL

High-level output voltage

VOH

Low-level Input leakage current

ILiL

High-level Input leakage cur em
Low-Ievel output leakage current
High-level output leakage current
Supply current

Min

Max

Unit

Condition

-0.5

0.8

Except ClK or SClK

-0.5

0.6

ClK,SCLK

Voo + 0.5

Except CLK or SClK

3.5

Voo + 1.0

CLK,SClK

0.45

IOL" 22 rnA

1011 .. -400 p.A

-10

p.A

VI" OV

ILiH

p.A

VI - Voo

ILOL

-10

p.A

Vo-OV

ILOH

p.A

VO" Voo

200

rnA

100

2.4

3-103

'ttiEC

"PD72120
AC Characteristics
TA = -10 to +70"C; voo .. +5.0 V :t10%; see figure 1

Parameter

Figure

Symbol

Min

Max

UnIt·

COndition

ClocIc (CLK. SCLIC)
Clock' period

High-level clock width

Low-level clock width

Clock rise time

.Clock fall time

ClK

tcVK

125

600

SClK

tcVSK

125

600

ClK

twKH

SClK

fwSKH

ClK

twKt.

SClK

\vsKL

ClK

fKR

SClK

tsKR

ClK

fKF

SClK

tsKF

3
3

lAST
loKI

toRI

tcVK

:s tcYSK

ns
ns

"""'t,lntenupt
Reset pulse width
ClK l' to I NT

t clelay time

Rl5,J. to INT,J. delay time

tcYSK
50

CL=50pF

3tcVK + 50

STATUS read

~ = 50pF

HLDRQ•. 7IDJIf1C
ClK t to

RIDAR delay-time

toKHA

H lORa setup time to ClK t

tsKHQ

HlORQ hold time from ClK t

~KHQ

ns'

ClK l' to OMARa output delay time

5,6

toKMQ

liM7iAK J.
DWiAR setup time to Rti J.
mAAR hold time from Rl5 t
mAAR setup time to WR ,J.
mAAR hold time from WR t

5,6

DM4 RsatI/WI'lte Cyr:III
OMARa setup time to

tsMAMQ

tsRMA

~RMA

tswMA

~WMA

4,7,8

toKA

tsKo

20
0

CL=50pF

Display IIfImory _lINd Cyt:Ie
ClK t to address or data output delay time
Input data setup time to ClK t
Input data hold time from ClK t

ns
ns

~KD

ClK t to OASTB t delay time

7,8

toKDSH

elK,J. to OASTB ,J. delay time

7,8

toKDSL

toKDR

toKDW

ClK l' to
ClK t to

DIm delay time
DWR delay time

$yIIIfIm Bull lINd Cyr:III
~ setup time to

Rl5 ,J.
Rl5 l'

~ hold time from

Rl5 width, high
ASTB pulse width

3-104

~=50pF

tsRC

~RC

5,9

twRH

5,6,9.10

twAS

CL =50pF

NEe

"PD72120

AC Characteristics (cont)
Parameter
ASTB setup time to

AD .j.

Address setup time to ASTB .j.

Figure

Symbol

Min

5,9

tSRAS

Max

Unit

5,6,9,10

tsASA

Address hold time from ASTB .j.

5,9

ltiASA

Data setup time to READY i

5,9

tsRYD

5,9

IJ:RO

5,9

toRRY

5,9

IHRYR

Data float delay time from

AD i

AD .j. to READY .j. delay time
AD hold time from READY i
CLK i to READY i delay time
AD i to ASTB i delay time

Condition

Q=50pF

5,9

toKRY

5,9

toMS

tawc

IHwc

ns
ns

CL=50pF

System Bus write Cycle
~ setup time to

WFi .j.
WR i

~ hold time from

WFi width, low
WFi width, high

twWL

6,10

twwH

Data setup time to WFi

6,10

ns
ns

6,10

tswo
lHwo

50
0

6,10

toWRY

6,10

IHRYW

t
Data hold time from WFi i
WFi .j. to READY.j. delay time
WFi hold time from READY i
CLK i to READY i delay time
ASTB setup time to WFi ~
WFi i to ASTB i delay time

6,10

II
CL =50pF

6,10

toKRY

6,10

tawAS

6,10

toWAS

SCLK i to DASTB i delay time

11,12,13

toSKDASH

SCLK .j. to DASTB .j. delay time

11,12,13

toSKDASL

Ii'fii5mP delay time

11,12,13

toSKDT

SCLK i to address delay time

11,12,13

~=50pF

Display Cycle

SCLK i to

toSKA

SCLK i to output signal delay time
(HS, VS, BLANK, or GCSR)

11,12,
13

toSKD

SCLK i to WAIT delay time

11,12

toSKWT

WAIT pulse width

EXVS setup time to SCLK i

EXHS setup time to SCLK i

twWT

4tcYSK-70

tsSKEV

tsSKEH

EXVS hold time from SCLK i

IHSKEV

EXHS hold time from SCLK i

IHSKEH

Q=50pF

3-105

ttlEC

"PD72120
Figute 1.

tlbltage Thresholds for Timing

lI.sui'ements.
Input

Figure 3.

RESET

2.4 V=X2.2V
2.2 V
;.;:0:::,8.:,V_ _ _.::O'::;.8V~

[except for
CLK or SCll<] 0.45 V

Reset snd In'""upt IIfIreforms

~
-' ~tRSTj '-

CLK

[ClK.~E~
Output

. [Cl=50pF]

--v-

V--

49NR-353A

Figure 2.

INT

2.2 V
2.2 V
--1\;.;:O:::,8.:,V_ _ _.::O.:::.8V,;..A-AD - - - - - - -..[

tORI

Cloi:Ic IIfIr.forms

Figure 4. HLDRQ snd HLIJAK IIfIrelo,ms
ClK

.
t HKHO

...

HlDRO

Hl~K--------_tD~_~
DADO-DAD 15.
DA16-DA23
Note:

-l}

~rtDK_~~I

_ _ _ _ _ __

~"'~ ~__
DKA

DuiiE. i5i:iiE do not go ID high impedance
49NR--356B

3,..106

NEe

,...PD72120

Figure 5. DMA ReIJd Cycle
eLK

DMARQ

READY

ASTB

ADO-AD1S

-Jx'-__

F--_ _ _

49NR-357B

3-107

t\fEC

"PD72120
Figure 4. DJrA . .lte Cycle
elK

DMARQ

READY

ASTB

....Jx\-__

F--_ _ _

49NR·3S8B

3-108

ttlEC

I'PD72120

Figure 7. Display Memory Bus Read Cycle
elK

DASTB

DA~-DAD15

-+---<1

DA1S-DA23 - - - - { I
49NR-369B

3-109

NEe

"PD72120
Figure .. DI.",.y lIemoTy Bu. . .It. Cycle
CLK

DASTS

DADo-DAD15

-+---<1

DA16-DA23

---'
==r:>
-

1)-

-1)-

DA1S

DA17

DA16

DAD1S
DAD14
DAD13
DAD12
DADll

ADll
ADl0
ADs
ADs

DAD10
DADs
DADs
DAD 7

AD7
AD6
ADs
AD4

DADe
DADs
DAD4
DAD3

AD3
AD2
ADl

DAD2
DADl
DADo

ADo

~
83Sl.......

3-128

ttiEC

"PD72120

Figure 19. Regl.t.r For"'"
7

DBIE

PBIE

CIE

Bit

Flag Name

Abbreviation

Meaning When Bit = 1

Software Reset

RESET

Initializes "PD72120.

Processor Abort

ABORT

Not used

o
ABORT

RESET

Stops any processing being performed and clears the processor BUSY status.
Must be set to O.

Not used

Clipping Interrupt Enable

CIE

Enables the INT signal when picking (drawing In the clipped region).

Preprocessor Busy
Interrupt Enable

PBIE

Enables the INT signal when the preprocessor status changes from BUSY to NOT

Drawing Processor
Busy Interrupt Enable

DBIE

Enables the INT signal when the drawing processor status changes from BUSY to
NOT BUSY.

BUSY.

Figure 20. Rectangular Clipping Region
Y

Clipping
Rectangle

YCLMAX
YCLMIN

I
XCLMIN

XCLMAX

(0,0)

83SL-5847A

Figure 21. Display Control Regl.t.r
MSB

I DTM I OTT I

DAD +

IN I RE I SC IFCCLITCCLIMASKI MIS I SO

LSB

LFI I SPST I SVS

Bit

Flag Name

Abbreviation

Function

Slave Sync

SVS

When the AGDC Is In the alave mode. SVS determines the Initialization of the Inter·
nal horizontal and vertical counters. SVS Is Ignored In the mester mode.

SVS

Initializes the vertical and horizontal countere at the rising edge of EXVS and
EXHS. respectively.
Initializes the vertical and horizontal counters at the rising edge of EXVS.

Sync Parameter Setting

SPST

Enables the writing of the sync timing parameters (HS. HBP. HH. HD. HFP. VS. VBP.
LJF and VFP) to address 7EH-7FH. The writing should take place after SPST Is set
to O. then to 1.
SPST
-0- Disables writing of sync parameters
1 Enables writing of sync parameters

Display Unes per Frame In
Interlace Mode

LFI

Defines whether there Is an even or odd number of lines per frame In Interlaced
mode. LFlls Ignorsd in non-interlacad mode.
LFI
o Even total number of lines for the sum of even and odd fields (one frame).
1
Odd total number of lines for sum of even and odd fields.

3-129

NEe

"PD72120
Figure 21. Display Control Register (cont)
Bit

Flag Name

Abbreviation

Function

Stop Display

Defines the state of the BLAN K output signal. SO is set to 1 by a high level on the
RESET pin.
SO

MasterlSlave

MIS

BLANK signal active (hIgh) only for the non-display period defined by the
video sync signals.
BLANK signal active for display and non-display periods (on continuously),

Defines whether the AGDC Is a master or a slave In terms of video sync signal generation.

MIS

Mask

MASK

Defines the VS signal output timing In the master mode. In the slave mode, defines
the validity of the EXHS and EXVS sync timing Input.
MS

o
o
1
1
6

Timing Counter Clear

TCCl

Sets the AGDC to slave mode (video sync signals Input through EXVS and
EXHS).
Sets the AGDC to master mode (generates video sync signals and outputs
them through VS and HS).

MASK

o
1

Accepts EXHS and EXVS sync timing Input.
Ignores EXHS and EXVS sync timing Input.
Only the VS signal of the even field in Interlace mode Is output.
The VS signal Is output normally.

Defines the timing for initializing the internal display cycle counter when the AGDC
Is in slave mode. TCCl Is ignored when the AGDC Is In master mode.
TCCl

o
1

Field Counter Clear

FCCl

Does not initialize the display cycle counter on the rising edge of EXVS.
Initializes the display cycle counter on the rising edge of EXVS (sets the
counter to the 01 cycle).

Defines the timing for initializing the Internal field counter when using Interlaced
display In the slave mode. When the AGDC is In master mode or non-interlaced display, FCCl Is Ignored.
FCCl

o
1

Steal Control

Does not initialize the field counter on the rising edge of EXVS.
Initializes the field counter on the rising edge of EXVS, setting the counter to
the even field.

Defines the relationship between the ClK and SClK signals when the AGDC is in
the DT mode (using video RAMs). If the AGDC Is In cycle steal mode, SC Is Ignored.
SC
ClK does not equal SClK
ClK and SClK are the same

Refresh Enable

Defines whether the AGDC is to generate DRAM refresh addresses.
RE
The AGDC does not generate DRAM refresh addresses
1
The AGDC generates DRAM refresh address while HS Is active (high)

Interlace

Defines whether Interlaced or non-interlaced display mode Is to be used.

ill

o
1

3-130

Non-Interlaced display
interlaced display

NEe

"PD72120

Figure 21. DispillY Control Register (cont)
Bit

Flag Name

Abbreviation

Function

11,
12,
13

Display Address
Proceedings

DAD +

Defines how the AGDC's 24-bit display address register Is to be incremented during
each display cycle. The register Is not Incremented while BLANK Is active. It Is Incremented ast each display cycle (two SCLK periods) In the DT (VRAM) mode or
each time a display cycle Is started In the CS (cycle steaO mode.
DAD +
Increment
000
DAD+1
DAD ... DAD + 1 ... DAD +2 ... DAD+3'" DAD+4 .. .
001
DAD +2
DAD ... DAD +2 ... DAD +4 ... DAD+6 ... DAD +8 .. .
010
DAD+4
DAD ... DAD+4 ... DAD+8'" DAD + 12 ... DAD + 16 .. .
011
DAD+8
DAD ... DAD +8 ... DAD + 16 ... DAD +24 ... DAD +32 .. .
100
DAD+16
DAD ... DAD + 16 ... DAD +32 ... DAD +48 ... DAD+64 .. .
101
DAD +32
DAD ... DAD +32 ... DAD +64 ... DAD +96 ... DAD+128 .. .
110
DAD+1/4
DAD ... DAD .... DAD ... DAD ... DAD+1 ... DAD+1 ..... .
111
DAD + 1/2
DAD ... DAD ... DAD + 1 ... DAD+1 ... DAD +2 ... DAD+2 ..

Data Transfer Timing

DTT

Defines the output timing for the DT (data transfer) signal when using VRAMs. DTT
is Ignored in the cycle steal mode.
DTT
ODT is generated (active low) when any of the following conditions is true.
(a) At the start of the screen display (at the first rising edge of the BLANK signal in a frame)
(b) At the start of each horizontal scan line (at the failing edge of BLANK)
(c) When all 8 AC register-defined bits of the 24-blt display address are 0
(when the lower 8 bits are OOH).
DT Is generated when any of the following conditions Is true.
(a) At the start of the screen display (at the first rising edge of the BLANK signal in a frame)
(b)

Data Transfer Mode

DTM

When all 8 AC register-defined bits of the 24-bit display address are O.

Defines the display cycle generation timing. Data transfer mode is normally used
with video RAMs and cycle steal mode with other types of memories.
DTM
o Sets the cycle s~eal (SC) mode. The DT/DISP pin outputs the DISP signal (active lOW). Display and drawing cycles alternate In this mode.
Sets the data transfer (OT) mode. The DT/DISP pin outputs the DT signal (activelow).

Figure 22. Cursor Position Select
CRS=O
1 Display CYCle-j

CRS = 1
1 Display Cycle

-j

,, ,,

,,
-------tt-------

GCSRYS_
GCSRYE- -------, ,-------

,, ,,
, ,

GCSRX

GCtRX
83SL-SS4SA

3-131

ttlEC

"PD72120
Figure 23. Horizontal and VertiCIII Timing Parameters
.....
, - - - - - - 1 H ----_~I
HSYNC

...JnL..___
1--

·~L.-_ _ _ _ _ _ _ _ _ _ _ _ _ _

HFP

HBLANK
HS

-----ot.1

HBPi-HH-j

VSYNC

2nd Field _ - - - ,_ _ _ _ _ _ _ _--'-_ _ _ _ _ _ _ _ _ _ __

VSYNC

1st Field

VSYNC

"L'"

I
--~I~·~~----------------------1V---------------------------.:1-------

I~----------------~

---+-h±
II
j ll-------UF-----~~'VFP~
I

VBP

l...-

83SL-S849B

3-132

t\fEC

"PD72120

Table 3. U.' of DRAW Com""""
Commands

Absolute Coordinates

Data Read Commands

Coordinate value read

READ.J)P

Color Information read

READ_COL

Graphics Drawing
Commands

Dot
Straight line

Relative Coordlnetes

DOTJ)
AJ>OT-M

R.J)OT-M

A..LlNE-MO

ILLINE-MO

A..LINE-M1

R....LINE-M1

A..LINE-M2

R....LlNE-M2

A..LlNEJ>O

R....LlNEJ>O

A..LINEJ>1

ILLINEJ>1

A..LINEJ>2

R....LlNEJ>2

A..LINEJ>3

Fill Commands

Rectangle

A..REC

Circle

CRL

Arc

CARC

Circle sector

CSEC

Circle segment (bow)

CSEG

Blipse

ELPS

Bllpsearc

EARC

Bllpse sector

ESEC

Ellipse segment (bow)

ESEG

Arbitrary area fill

PAINT

Triangle fill

A..TRI..FILL

Trapezoid fill

A..TRA..FILL

Rectangle fill

A..REC..FILLC
A..REC..FILLA

Circle fill
Copy Commands

R....REC..FILL

CRL..FILL

ellipse fill

ELPS..FILL

Physical address to physical address

A..COPV..AA

Coordinate to physical address

A..COPV_CA

Physical address to coordinate

A..COPV..AC

Coordinate to coordinate

A..COPV_CC

Copy function extensions

R....REC

goo_COPY
SLCOPV
FR....ES..COPV
ES_COPV

PUT/GET Commands

System memory to display memory

PUT..A
PULC

Display memory to system memory

GET..A
GELC

GET function extensions

goo_GET

3-133

NEe

#,PD72120

Table 4. DRAW Command Descriptions
Commands

Name

Description

Data Read Commands

READ.J)P
Read Drawing Pointer

The current drawing pointer coordinates (X#, Y#) are output
to the X and Y registers to be read by the host CPU.
6FH

6EH

10 10 10 0 10

10101010101010101010

READ_COL
Read Color

The color information in each memory plane corresponding to
the coordinates (X, Y) pointed to by the X and Y registers is
placed in the OX register to be read by the host CPU. The
least significant bit corresponds to the first plane, the most
significant bit to the 16th plane.
6FH

o
Graphics Drawing Commands

6EH

101 0 1 0 1010101010

DOT.J)
Dot Direct

6EH

6FH

1 0 1 0 1 0 1 IP

I0I0I0I I0

6FH

BPPX

6EH
jPXENI

BPPX

0 0

6EH

1 0 1 0 1 0 1 IP 1 0

IpXENI

BPPX

10 10

Absolute Une with Move 0, 1, 2

A straight line is drawn from coordinates (X, Y) pointed to by
the X and Y registers to (XE, YE) pointed to by the XE and YE
registers. WEP determines whether the end point (XE, YE) Is
drawn. The drawing pointer (X#, Y#) changes to (XE, VEl. The
commands differ as follows.

A-LINE...MO

The X and Y registers change to the values In the XE and YE
registers. The XE, YE, XS, and YS registers do not change
value.
6FH

1 0

6EH

o 1ED

1 IP

BPPX
(PL)

3-134

A dot is drawn at the (X + OX, Y + DY) defined by the X, OX, Yo
and DY registers, respectively. The drawing pointer (X#, Y#)
changes to (X+DX, Y +DY). The bit pointer of the PNTCNT
regl ster shifts from the LSB by 1 bit toward the MSB .

FLDOT..M
Relative Dot with Move

IpXENI

A dot Is drawn at the (X, Y) coordinates pointed to by the X
and Y registers, respectively. The drawing pointer (X#, Y#)
changes to (X, Y). The bit pointer of the PNTCNT register
shifts from the LSB by 1 bit toward the MSB .

A-DOT..M
Absolute Dot with Move

A dot is drawn at the current drawing pointer coordinates (X#,
Y#). The drawing pOinter (X#, Y#) remains unchanged. The bit
pointer of the PNTCNT register shifts from the LSB by 1 bit
toward the MSB .
6FH

1ESH 1WEP 1

NEe

I'PD72120

Table 4. DRAW CtllllllMnd Descriptio". (conf)
CommandB
Graphics Drawing
Commands (cont)

NIIIII8

DeBerlptlon

A-LINE-M1

The X, Y, XE, YE, XS, and YS registers do not change value.

6FH
1·

6EH

BPPX
(PI..)

A-LINE-M2

The XS and YS registers change to the values In the X and Y
registers. The X and Y registers change to the values In the
XE and YE registers. The XE and YE registers do not change
value.

BPPX
(PI..)

Absolute Une Direct 0, 1, 2, 3

A straight line Is drawn from ths current drawing pointer (X#,
Y#) to the coordinates (XE, YE) pointed to by the XE and YE
registers, respectively. The values In the X and Y registers
should be equal to the drawing pointer (X#, Y#) In order to
execute these commands. The drawing of the end point (XE,
YE) Is determined by WEP. The commands differ as follows.

A...LINE..OO

The drawing pointer (X#, Y#) and X and Y register values
change to XE and YEo The values In the XE, YE, XS, and YS
registers do not change.
6FH

6EH
0 I ED 1 IP ·1 ES IPXENI BPPX

1ESHIWEPI

(PL)

The values In the X. Y, XE, YE, XS, and YS registers do not
change. The drawing pointer (X#, Y#) changes to (XE, VEl.

A...LINE..01
6FH

6EH

1 0 1

I ED 1 IP 1 ES IPXENI

BPPX

1 ESH IWEP

(PL)

The values In the XS and YS registers change to those In the X
and Y registers. The X and Y register values change to those
In the XE and YE registers. The XE and YE register values do
not change. The drawing pointer (X#, Y#) changeB to (XE,
YE).

A-LINE..02

6FH

0 1 1

1 1

I ED I IP

6EH

1 ES IpXENI

BPPX

1ESH 1WEP

3-135

NEe

"PD72120
Table 4. DRAW Command Descriptions (conI)
Commands

Name

Description

Graphics Drawing
Commands (cont)

A..LlNE...D3

The values in the XS and YS registers are used for the end
point of the line. The drawing pointer changes to (XS.YS). The
vaiues in the X and Y registers change to those in the XS and
YS registers. The XE. YEo XS. and YS register vaiues do not
change.
6EH

6FH

I ED I IP

BPPX I ESH I WEP I
(Pl)

Relative Line with
Move 0.1.2

A straight line is drawn from coordinates (X. Y) pointed to by
the X and Y registers to the point (X + OX. Y+DY) with OX and
DY contained in their respective registers. Drawing of the end
point is determined by the WEP bit.

FLLlNE...MO

The drawing pointer (X#. Y#) changes to (X+DX. Y +DY). The
X and Y registers change to (X + Ox, Y +DY). The OX. DY, XS.
and YS register values do not change.
6EH

6FH

I 0 I 0 I ED I IP

ES IpXENI

BPPX I ESH I WEP I
(Pl)

6EH
I ES IpXENI

BPPX
(PL)

IESH IWEP I

The drawing pointer (X#. Y#) changes to (X + OX. Y+DY). The
XS. and YS registers change to (X. Y). The X and Y registers
change to (X+DX. Y+DY). The OX and DY register vaiues do
not change.

FLLlNE...M2

6FH

I ED I

The drawing pointer (X#. Y#) changes to (X+DX. Y+DY). The
X. y, OX. DY, XS. and YS register values do not change.

FLLI NE...M 1

I ED I IP

6EH
BPPX I ESH I WEP I
(PL)

RUne Direct O. 1. 2

A straight line is drawn from the drawing pointer (X#. Y#) to
the coordinates (X + OX. Y + Dy) pointed to by the OX and DY
registers. The drawing of the end point is determined by the
WEP bit. The drawing pointer changes to (X + OX. Y+DY).

FLLlNE...DO

The X and Y registers change to (X+DX. Y+DY). The OX. DY,
XS. and YS register values do not change.
6FH

I ED I

6EH
IP

ES IpXENI

BPPX I ESH WEP I
(Pl)

NEe

"PD72120

Tsble 4. Drs.ing ComlJUlnd Descriptions (conI)
Name

Commands

Graphics Drawing
Commands (cont)

Description

FLLlNE...Ol

The X Y, OX, DY, XS, and YS register values do not change.
6FH

FLLlNE...02

6EH
EO I IP

ES IpXENI

BPPX

I ESHIWEPI

(PL)

The XS and YS registers change to (X, V). The X and Y registers change to (X +OX, Y + OV). The OX and OY register values
do not change.
6FH

6EH
EO I IP

ES IpXENI

BPPX

I ESHIWEPI

(PL)
~EC

A rectangle with horizontal and vertical sides parallel to the X
and Yaxes Is drawn with the diagonal vertices at coordinates
(X, V) and (XS, YS) pointed to by the X, Y, XS, and YS registers, respectively. The drawing pointer (X#, Y#) changes to (X,
V).

Absolute Rectangle

6FH
0

6EH
0

ES IpXENI

6FH
0

6EH

I IP I ES IpXENI

6FH
0

liP I 0 IpXENI

BPPX

A circular arc Is drawn from coordinates (XS, YS) to (XE, YE)
with the center of the circle at (XC, YC) and radius Ox. These
are pointed to by the XS, YS, XE, YE, XC, YC, and OX registers, respectively. The drawing pointer changes to (XE, VEl.
OX must be > O.
6FH
0

CSEC
Circle Sector

I CF I

6EH
IP

IpXENI

BPPX

IWEPI

A circular sector is drawn with the center at (XC, YC), OX the
radius, (XS, YS) the starting pOint, and (XE, YE) the ending
point. The drawing pointer changes to (XS, YS).
OX must be > O.
6FH

I ESH I 0

6EH
0

CARC
Circle Arc

BPPX

A circle is drawn counterclockwise with the center at (XC, YC)
pointed to by the XC and YC registers and with radius OX defined by the OX register. The drawing pointer (X#, Y#)
changes to (XC, YC+OX). The circle Is started from (XC,
YC+OX). OX must be> O.

CRL
Circle

I ESH I 0

A rectangle with horizontal and vertical sides parallel to the X
and Yaxes Is drawn with the diagonal vertices at coordinates
(X, V) and (X+OX, Y +OV). The drawing pointer (X#, Y#)
changes to (X, V).

FLREC
Relative Rectangle

BPPX

6EH
CF I IP

IpXENI

BPPX

3-137

NEe

"PD72120
Table 4. DRAW Command Descriptions (conI)
Commands

Name

Oeserl ptlon

Graphics Drawing
Commands (cont)

CSEG
Circle Segment

A circle segment is drawn with the arc starting at (XS, YS),
ending at (XE, VEl, the circle center at (XC, YC), and with radius OX. A line segment connects the arc starting and ending
point to complete the segment. The drawing pointer (X#, Y#)
changes to (XS, YS). The radius OX must be > O.
6FH

1 0 1 0 I 01

0 0

6FH

1 0

IpXENI

BPPX

1 0 1 0 I CF 1 IP

6EH

IpXENI

BPPX

An elliptical sector with major and minor axes parallel to the

ESEC
Ellipse Sector

coordinate axes is drawn from (XS, YS) to (XE, YE) with the
ellipse center at (XC, YC), Y-directlon radius OY, and the ratio
of the squares of the X- and V-direction radii OX2/0'(2 =
OH/DV. The drawing pointer (X#, Y#) changes to XS, YS).
The radius OY must be > O.
6FH

6EH
IP

An elliptical arc with major and minor axes parallel to the coordinate axes Is drawn from (XS, YS) to (XE, YE) with the ellipse
center at (XC, YC), V-direction radius OY, and the ratio of the
squares of the X- and V-direction radii OX2fDY2 = OH/DV.
The drawing pointer (X#, Y#) changes to (XE, VEl. The radius
DY must be > O.

EARC
Ellipse Arc

0 10

1 0 1 0 I CF 1 IP 1 0

6EH
IpXENI

BPPX

An elliptical segment with major and minor axes parallel to the
coordinate axes is drawn from (XS, YS) to (XE, YE) with the
ellipse center at (XC, YC), V-direction radius OY, and the ratio
of the squares of the X- and V-direction radii 0X2/0y2 =
OH/OV. The drawing pointer (X#, Y#) changes to (XS, YS).

ESEG
Ellipse Segment

6FH

3-138

BPPX

axes Is drawn counterclockwise with the center at (XC, YC), the
Y-dlrection radius OY, and the ratio of the squares of the X-axis
and Y-axis radii in OH and OV such that OX2/0'(2 = OH/DV.
The drawing pointer (X#, Y#) changes to (XC, YC+Oy). The
radius DY must be > O.
6FH

6EH
IpXENI

An ellipse with major and minor axes parallel to the coordinate

ELPS
Ellipse

1 1 1 0 I CF 1 IP 1 0

0 10

I 1
CF

6EH
IP

IpXENI

BPPX

0 0

ttlEC

#,PD72120

Table 4. DRAW Command Descriptions (cont)
Commands

Nsme

Description

Fill and Paint Commands

PAINT

A boundary-point search is carried out starting from coordinates (X, y) and the resulting enclosed area is filled with a
solid or tiling pattern. When PMOD = 0, the boundary colors
are set Into the DX register. The area to be painted must be
enclosed within the clipping rectangle and the CLIP register
must be set to 00.
6FH

6EH

a
A triangular region with vertices at (X, y), (XS, YS), and (XC,
YC) is filled with the tiling pattern. Y, YS, and YC must not be
equal to each other.

A..TRLFILL
Absolute Triangle Fill
6FH

6EH

A..TRA..FILL
Absolute Trapezoid Fill

A..REC _ FI LL C
Absolute Rectangle Fill by
Coordi nates

6EH

I Ia I I I I I I
TL

6FH

I I I

WR FAST

A rectangle with vertical and horizontal sides parallel to the
coordinate axes is filled with the tiling pattern. The rectangle
is defined by the number of dots in the horizontal direction
DH + 1, the number of dots in the vertical direction DV + 1, the
starting address (physical address) EAD1, and the bit position
In the starting address dAD1.

A..RECYILLA
Absolute Rectangle
Fill by Address

A rectangle with vertical and horizontal sides parallel to the
coordinate axes is filled with the tiling pattern. The diagonal
vertices of the rectangle are (X, Y) and (XS, YS).

6FH

A trapezoidal area with its upper parallel side defined by the
line segment connecting (X, y) to (XS, y), a height of DV + 1
dots above the lower side line segment connecting X+DX and
XS+XC, is filled with the tiing pattern.

I I WR I a

6FH

6EH

FLTRA..FILL
Relative Trapezoid Fill

A trapezoidal area with its parallel sides (upper and lower) defined by line segments connecting (X, y) to (XS, y) and (yS,
YE) to (XE, VEl, where YS is an X-axis value, is filled with the
ti Ii ng pattern.
6FH

I I Ia

6EH

3-139

t-{EC

"PD72120
Table 4. DRAW Command Descriptions (conI)
Commands

Name

Description

Fi II and Paint
Commands (cont)

RJlECJ'ILL
Relative Rectangle Fill
by Coordinates

A rectangle with vertical and horizontal sides parallel to the
coordinate axes Is filled with the tiling pattern. The rectangle
is defined by the starting point (X, y), the horizontal width OX,
and the vertical height OY. The diagonal vertices are at (X, Y)
and (X+OX, Y+DY).
6FH

CRLJ'ILL
Circle Fill

I 0 I 0 I TL I 0

A circle with its center at (XC, YC) and a radius of DX is filled
with the tiling pattern. Points on the circumference are filled.
The filling starts from the top of the circle and proceeds
downward.
6FH

6EH

I SS I WL I WR IFAST I 0

6EH

olololTL

I I1
SS

An ellipse with its major and minor axes parallel to the coordinate axes, center at (XC, YC), V-direction radius OY, and ratio
of the squares of the X- and V-direction radii DX2/Dy2 =

ELPSJ'ILL
Ellipse Fill

DH/DV Is filled with the tiling pattern. The filling starts from
the the top of the ellipse and proceeds downward.
6EH

6FH

o
Copy Commands

I 0 I 0 I TL I 0 I 1 I SS I 1 I 1 I 0

~COPY...AA

A rectangular area of memory starting from physical location
EAD2 and bit position dAD2, with horizontal size DH+l dots
and vertical size DV + 1 dots, is transferred to the rectangular
area of memory starting from EADI and bit position dAD1.

Absolute Copy Address
to Address
6FH

6EH

o
~COPY_CA

A rectangular area of display memory starting from (XS, YS),
with horizontal size DH + 1 dots and vertical size DV + 1 dots,
Is transferred to the rectangular area of memory starting from
physical address EAD1 and bit position dAD1.

Absolute Copy Coordinate
to Address
6FH

6EH

o
~COPY..AC

A rectangular area of display memory starting from physical
address EAD2 and bit position dAD2, with horizontal size
DH + 1 dots and vertical size DV + 1 dots, Is transferred to the
rectangular area of memory starting from (X, Y)'

Absolute Copy Address
to Coordinate
6FH

3-140

6EH

ttlEC

"PD72120

Table 4. DRAW Command Descriptions (conI)
Commands

Name

Description

Copy Commands (cont)

A..COPV_CC
Absolute Copy Coordinate
to Coordinate

A rectangular area of display memory starting from (XS. YS).
with horizontal size OH + 1 dots and vertical size DV + 1 dots.
is transferred to the rectangular area of memory starting
at (X. Y).

6FH

Copy Function extensions

6EH

The function of each COPY command can be extended by
changing the lower 2 bits of the command code. This exten·
sion is defined in the lower byte (6EH) of the command
register.
9O"_COPV
90" Rotation Copy

The transferred memory area Is rotated 90" counterclockwise.
6EH

IESE IREV IROT I 1 I SO_SEL
SLCOPY
Slant Copy

The data In a rectangular area of display memory Is slanted
by OX in the X·dlrectlon to the change in the Y·direction
6EH

FILES_COPY
Free Angle Rotation.
Enlarge/Shrink Copy

The rectangular data from the source area Is transferred to a
parallelogram at the destination area In display memory. OY
and OX determine the angle for the horizontal side. XE and YE
for the vertical side. MAGH and MAGV determine the horizon·
tal and vertical enlargement or shrink factore.
6EH

ES_COPV
enlarge/Shrink Copy

The rectangular data from the source area Is transferred to a
rectangular area at the destination In display memory and en·
larged or shrunk In the horizontal and/or vertical direction.
MAGH and MAGV determine the horizontal and vertical scale
factors.
6EH

IESH IREV IROT IESV I SO_SEL

3-141

NEe

"PD72120
Table 4. DRAW Command Descriptions (cont)
Commanda

Name

Description

PUT/GET Commands

PUT..A
Put Data to Address
Field

Transfers. data from the PGPORT register to a rectangular area
o! display memory starting from word address EAD1 and bit
position dAD1 with horizontal width DH + 1 dots and vertical
height DV + 1 dots.
6FH

6EH

I0
Transfers data from the PGPORT register to a rectangular area
of display memory starting from (X, y) with horizontal width
DH + 1 dots and vertical height DV + 1 dots.

PULC
Put Data to
Coordl nate Field

6EH

6FH

I I0 I0

Transfers data to the PGPORT register from a rectangular area
of display memory starting from word address EAD1 and bit
position dAD1 with horizontal width DH + 1 dots and vertical
height DV + 1 dots.

GET..A
Get Data from Address
FIeld
6FH

6EH

Transfers data to the PGPORT register from a rectangular area
of display memory starting from (X, y) with horizontal width
DH + 1 dots and vertical height DV + 1 dots.

GELC
Get Data from
Coordinate Field
6FH

6EH

I1 I0 I0 I1 I

Get Function extensions
9O"_COPV

I1 I0 I0 I0 I0 I0 I

Data in the rectangular area of display memory is rotated
through 90' and transferred to the PGPORT registet
6EH

3-142

SD_SEL

I I I I
REV ROT

SD_SEL

NEe

"PD72120

Figure 24. Graphics Dr",,'og Commands
Dot

[X+OX, Y+OYI

Circle Sector [CSEC]

~1
T

[XS, YSI
[XS, YSI

[X, Yl

~CF=1

[X, Y)

•

~[XE'YEI

1+10--- ox - - - . 1

[XC, YCII+-- OX

R_DOT
Line

[XE, VEl

-+I

[X+OX, Y+OYI

""/L:Jf
Rectangle

Circle Segment [CSEG]
[XS, YSI
[XS, YSI

~CF=1
~[XE'YEI
[XC, YCII+--

ox -+I

[XS, YSI

Ellipse Arc [EARC]

e,
[XS, YSI

[X, Yl

[XS,YSI
[jF=1
OY
[XE, VEl

T
.1

Circle [CRL]

OY
[XC, YCI

[XE, VEl
CF=O

I[j;(I

[XC, YC)

OH:OV=OX2:0y2

Ellipse Sector [ESEC]
[XS, YSI

Ellipse [ELPS]

[XE, VEl

[[NF=1

"""''::::;~CF=o

49NR-361B

3-144

t\'EC

I'PD72120

F"lIIure 26. Copy COIIIIfIIIndS; Cop", Rotate, Slant
Source

Copy [COPY]

90' Rotation Copy [90'_COPY]

"'.. ~~ 11,1..

<£Y~ ,",-'

tnI

"'-'.,",~

rII

<£Y-'

om-'

j.JJ1
49NR·362B

3-145

t\'EC

"PD72120
FIgunI 27. Copy CtlllllllllndiI; Enlatgll/ShTinlc,

Rot.,.
Source

1
Enlarge/Shrink Copy [ES_COPY]
RCV=D, ROT.O lI!'""'lK""--'

ESH.O, ESV.1

Arbitrary Angle Rotation Copy [FFLES_COPY]
ESH=D, ESV=l
DX>O,DYcO
XEcO, YE>O

~
ESH= 1, ESV.O

REV=D, ROT.1

~
REV=l, ROT_O

ESH.1, ESV.O
DXcO,DY>O
XEcO, XE>O

ESH.1, ESV-o

ESH=O, ESV-1

[IJ'

I4J

ESH.O, ESV.O

ESH-O, ESV_1
DX>O,DY>O
XEcO, YEcO

ESH.1, ESV=O

REV.1, ROT.1
ESH.1, ESV=l
DX
<==>

ASTB
AEN
MREO
MACKMROMWRREAOY-

Image
Bus

AO-/Iq

<==>

MHlMR
Analyzer
OMAC

AB-A15/0B-015.
AlB -A23/00-07

<==> <

Pack
83SL·5683B

Absolute Maximum Ratings

DC Characteristics

TA = +25"C

TA = -40to +85°C;

Power supply voltage. VOO

-0.5 to +7.0 V

Input voltage. VI

-0.5 to VOO + 0.3 V

Output voltage, Vo

-0.5 to VOO + 0.3 V

Operating tamperature, TOPT
Storage tam perature, TSTG

4-6

-40 to +85°C
-40 to +125°C

Parameter
Input voltage.
low-level
Input voltage,
high-level

voo = +5 V ±10%

Symbol

Min

Typ Max Unit

VllC

-0.5

+0.8

Vll

-0.5

+0.8

Other pins

VIHC

+3.3

VOO
+ 0.3

ClK,
pins

VIH

+2.2

VOO
+ 0.3

Other pins

+0.4

IOl = 2.5mA

IOH = -400 !'A

Output voltage,
low-level

VOL

Output voltage,
high-level

VO H

0.7Voo

Conditions
ClKpln

RESET

Input leakage
current

III

±10

!'A

VIN = Oto VOO

Output leakage
current

ILO

±10

!'A

VOUT = Oto
VOO

Supply current

100

rnA While operating

NEe

ILPD72185

AC Characteristics
= -40 to +85'C; voo = 5 V ±10%

Parameter

Min

Max

Unit

tcYK

125

1000

tKKL

tKKH

ClK rise time

iKR

ClK fall time

tKF

MREO i delay time from ClK i

tOMaH

100

MREO,l. delay time from ClK i

tOMaH

100

MACK i setup time to ClK t

tSMA

MACK ,I. hold time from ClK i

tHMA

AE N i delay time from ClK i

tOAEH

Figure

Symbol

ClKcycle

ClK low-level width

ClK high-level width

Condition

Clock
ns
ns
10

1.5 - 3.0V
3.0 -

1.5 V

Image Memory Interface

ns
ns
100

AEN ,I. delay time from ClK i

tOAEL

100

ASTB i delay time from ClK,I.

tOSTH

ASTB high-level width

tSTST

ASTB ,I. delay time from ClK i

tKKH - 15

tOSTL

100

loA

100

Address/data/MRD/MWR delay time from elK ,I.

Address/data./MRD/MWR float time from elK ,I.

tFA

Address setup time to ASTB .j;

tSAST

tKKH -35

Address hold time from ASTB ,I.

iHSTA

tKKL -20

MRD ,I. delay time from Address float

toAR

MRD ,I. delay time from elK ,I.

tORL

MRD low-level width

~RL2

MRDi delay time from elK i

IoRH

Input data setup time to MRD i

tSOR

Input data hold time from MRD i

iHRD

MWR,I. delay time from elK ,I.

tOWL

MWR low-level width

tWWL2

MWRi delay time from elK i

IoWH

READY setup time to ClK i

tSRY

READY hold time from elK i

tHRY

DACKICS' recovery time

4,5

tROC

200

lORD low-level width

4, 7

tRRL

150

tsAR

Address/CS' ,I. hold time from lORD i

tHRA

iORD ,I.

tORD

ns
70

ns
ns

2tcYK-50
70

WAIT

ns
ns
ns

ns
ns

2tcYK -50
70

Host Interface

Address/CS' ,I. setup time to

iORD ,I.

Output data delay time from

ns
120

ns
ns

Output data float time from lORD i

!fRO

IOWR low-level width

twWL

100

CS' ,I. hold time from IOWR i

tWWCS

4-7

NEe

"PD72185
AC Characteristics (cont)
= -40 to +85°C; voo = 5 V ±10%

Parameter

Figure

Symbol

Min

AddresslUEffiicS,!. setup time to iOWA ,!.

tsm

tHWA

AddressJi]'!ffi hold time from IOWA

IOWA t
Input data hold time from IOWA t
RESET low-level width
Voo setup time to RESET t
iOWRJiORD wait time from I'iE§"Ei t
iOWRJlORD recovery time
DREQ ,!. delay time from iORD ,!.
Input data setup time to

DREQ ,!. delay time from

iOWA ,!.

Max

Unit

tsow

100

tHWO

tRSTL

7lcvK

tsvoo
tsvwR

1000
2t(;VK

tR./WR

200

teROO

140

tewoo

140

Figure 1. Voltage Thresholds for Timing
Measurements

Condition

Figure 2. Clock Timing

Input I Output
2.4 V - - y . 2.2 V

2.2 V

V--

0.4V -A..;;0,;.;;.8..;.V_ _ _ _ _ _ _..;.0.;;;.8,.;..vA-

CLK

elK Input
83VL-548OA

CLK --y.3.0V

3.0 V

V--

-A~1~.5~V~_ _ _ _ _ _..;;1,;.;;5~V"___

83VL-S479A

4-8

NEe
Figure 3.

I'PD72185

DMA Transfer Timing on Image Bus

tDMOL ....

tDMOH-i

~----+---r-~---+--~-------------+------~
MREO
t sMAr

MACK

~~--+---r-~---+------------~-------r--~--+-~

tDAEH_i

r-+--r~~--r---------~-----+--+-~\
AEN

_ _ tDSTL

I--

tDSTH-

,.--.,
ASTB

II
....

-tHRY

\ Q/

READY

_ t SRY
Hi-Z
Ao-A7 ------------------r~

Address

Hi-Z

}-----------

f+-------tWWL2

MWR

--------':!!.-!--------f-J

Output Data

• MACK must remain high for at least one clock cycle after MREO
becomes high.

Hi-Z

~-----------

83YL·s.t818

4-9

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"PD72185
Figure 4.

Timing for Read from pPD72185 on Host

Figure 6.

Reset Timing

Bus

Voo
-

~t-o.I----tSVDD ---"'''00\'
tSYWR

83YL·5484A

Figure 7. Read/Write Cycle Timing

Figure 5.

Timing for Write to pPD72185 on Host
Bus

t RDC

}

Address

tWWl_

tSAW

1-+
1-+

tHWA
83YL·548SA

twwcs

\
t HWD

tSDW

10DOIOD15

Input Data

K
83YL·5483A

4-10

DREQ

NEe

"PD72185

OVERVIEW

Table 2. pPD72185 Processing Patterns

The "PD72185 encodes and decodes binary image data
in accordance with the standard system prescribed by
the CCITT (International Telegraph and Telephone Consultative Committee). See table 1.

Type

Processing

Encoding

Image memory

Decoding

Image memory

Encoding

Image memory

Host

Decoding

Host

Image memory

Table 1. CCITT Standard Systems
System

CCITT Recommendation

T.4 (G3 Facsimile)

MR
MMR

T.4 (G3 Facsimile)

Data Flow, Bus-to·Bus

Data transfer

Image memory

Host

Data transfer

Host

Image memory

Data transfer

Image memory

T.6 (G4 Facsimile)

The "PD72185 has two bus interfaces with which it
connects to the system. One interface is with the host
CPU and the other is with image memory. Data exchange
with the host CPU is by ordinary I/O accesses; data
exchange with image memory is by DMA transfers using
the on-chip DMA controller.
In this document, the bus on the host CPU side is called
the host bus, and the the bus on the image memory side
is called the image memory bus.

In addition to encoding/decoding, the "PD72185 can
perform data transfers between the image memory and
the host CPU. Also, it can perform image enlargement
and reduction on expansion and compression and logical operations (AND, OR, XOR,) while transferring data.
Table 2 and figure 8 show the processing patterns.

4-11

tttlEC

#£PD72185

Figure B. pPD72185 Processing Patterns
Host Sus

Image
Memory Sus

I I
I I
Image
Data

Host Sus

Data

I I
Codes

111'072185

Data

I'PD72185

111'072185

Codes

Image
Memory Sus

I I
Image
Data

I'PD72185

I
I

Data

I I
Codes

4-12

I I
Image
Data

83SL·SS84B

tt{EC

",PD72185

PROCESSING

Modes
The two processing modes of the I'PD72185-block and
line-are selected by commands from the host CPU. In
block mode, which is more commonly used, one command controls processing of multiple lines. In line mode,
one command is required for each line. Line mode allows
encoding/decoding methods other those prescribed by
the CCITT.

Line Processing
A compressed line consists of a header and code as
shown in figure 9. In the header, commands from the
host CPU specify the number of filler bits (0 to 65,535),
the presence/absence of the EOL code, and the number
of bits in the tag pattern (0 to 8).
The code that follows the header consists of encoded
binary image data. The encoding method can be specified per line by commands from the host CPU.
At the time of encoding, a line is generated in this order:
filler + EOL code + tag pattern + code. This filler is
appended to the immediately preceding line.
Decoding is performed one line at a time in this order:
code + fi lIer + EOL code + tag pattern. If a page starts
with an EOL code, the I'PD72185 detects the EOL code
and the following tag pattern and processes them before
starting line-by-line decoding.

Figure 9_ Line Composition (Line Mode)

The I'PD72185 processes an image area specified by the
host CPU as a unit. On completion of processing, the
I'PD72185 sends back to the host CPU in the form of a
response: memory manage ment information, processing information, counter information, etc.
As an example, consider a
encoded by one method is
method. When the recoded
image areas, the following
ployed.

case in which image data
to be recoded by another
data extends over multiple
two methods can be em-

(1) All encoded data in the multiple image areas is
decoded. This image data is then reencoded all at
once.
(2) Encoded data in multiple image areas is decoded in
small blocks. This image data is then recoded a
block at a time, processing only a section of each
image each time..
Depending on the systerrtdesign, pipe lining with method
2 may improve processing efficiency. This method can
be implemented through the host CPU's management of
responses sent back by the I'PD72185.

ENLARGEMENT/REDUCTION
The I'PD72185 can reduce an image when encoding and
enlarge image data when decoding. Reduction is performed by a simple thinning-out operation, and enlargement by repeating the same data. Enlargement/reduction
types are shown in table 3.

Table 3. Enlargement/Reduction Types
Enlargement and (Reduction) Factors
Type

1+----

Header part

-----t--

A
B

Horizontal

Vertical

(1)

1 (1)

(1)

2 (112)

2 (1/2)

EXTERNAL INTERFACE

2 (1/2)

4 (1/4)

The I'PD72185 exchanges data with image memory by
DMA transfers via the on-chip DMA controller. When the
I'PD72185 needs to access image memory, it requests
use of the image memory bus by activating MREQ. Data
is exchanged with a host CPU (including an external
DMA controller) by normal I/O accesses. The host CPU
reads and writes data through the I'PD72185 I/O addresses.

The I'PD72185 can perform white mask processing on
the right edge and left edge of image data. The amount
of white masking is specified separately for each edge in
word units (0 to 255 words)

MULTITASKING
Multitasking means using the I'PD72185 to process multiple image areas in parallel by time division.

WHITE MASK

The I'PD72185 automatically white masks data on encoding image data. It is not able to perform decoding
and white mask processing at the same time. Hence,
white mask processing is performed once decoding is
completed

4-13

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"PD72185
BIT BOUNDARY

Memory Organization

Some image areas consist of lines not terminated in
either byte or word units but with an odd number of bits.
The ",PD72185 handles image areas of this kind with bit
boundary processing.

Under control of the host CPU, image memory can be
either byte-organized (8-bit units) or word-organized
(16-bit units). One ",PD72185 address corresponds to one
byte or one word in memory. In both cases the ",PD72185
does its internal processing and writes to image memory
in 16-bit units. Thus, when image memory is byteorganized, two accesses are required, one to an oddnumbered address and one to an even-numbered address.

Lines with an odd number of bits are processed by
specifying void bits up to the byte or word boundary. See
figure 10.

Figure 10. Bit Boundary Processing (Word Units)
WOrd boundary

Word boundary

WOrd boundary

The 24-line address bus allows access to a large amount
of image memory. Table 4 shows image memory capacity for byte and word organization.

Table 4. Image Memory Capacity

+1._--

/.- Void bits ....
(0 to 15)

Organization

Part actually
processed

Start address
83YL·5649A

Size

*Capaclty

Byte

16M bytes

64 A4 sheets

WOrd

32M bytes

128 A4 sheets

*A4 sheet - 210 mm wide by 2$7 mm long
Horizontal: 8 dots/mm
Vertical: 4 dots/mm

IMAGE MEMORY
Data Storage

Image Area
Image memory means the whole area of memory accessible by the ",PD72185. An image area, on the other hand,
is a rectangular area within image memory (figure 11),
the size and location of which is specified by commands
from the host CPU. The unit of processing is an image
area.
The ",PD72185 can append and also detect the code
indicating the end·of a page using commands from the
host CPU. Page management, however, is performed by
the host CPU.

Figure 11. Image Area Examples

Image memory can store code and other general data as
well as binary image data. Binary image data is converted to white/black levels shown in table 5 and stored
as follows.
(1) The first bits scanned are packed in sequence starting from the LSB of a byte/word.
(2) The first data byte/word scanned is packed in sequence in byte/word units starting from the lower
address side.
Code transferred serially is stored as follows.
(1) The first bits transmitted are packed in sequence
starting from the LSB of a byte/word.

Origin

(2) The first data byte/word transmitted is packed in
sequence starting from the lower address side.

Image Memory
Image Area

Image Area

Table 5. Binary Image Data Levels

r::l

Level

Binary Notation

White

Black
83YL-565OA

ENCODING/DECODING SYSTEMS
Table 6 lists the encoding/decoding systems the
",PD72185 can handle, including CCITT standard systems. Figure 12 shows coded data formats for MH, MR,
and MMR systems.

4-14

NEe

J,tPD72185

Table 6. Encoding/Decoding Systems

Picture Elements

System

Image data that exceeds 2623 picture elements (pixels)
per scan line is processed using the run-length code
table expansion method stipulated in CCITT Recommendation T.6.

Summary

One-dimensional encoding/decoding system,
G3 facsimile, CCITT standard.

Two-dimensional encoding/decoding system,
G3 facsimile, CCITT standard.

MMR

Two-dimensional encoding/decoding system,
G4 facsimile, CCITT standard.

Other

Systems other than CCITT standards that can
be implemented by selecting line mode

Figure 12. Code Data Formats in MH, MR, and MMR Systems
MHSystem
Data proceeds in time ~

Code for one scan line

MRSystem
Data proceeds in time--..

Code for one scan line

MMRSystem
Data proceeds in time ~

Code for one scan line

Item

MHSystem

MR System

MMR System

Start of each scan line

EOl

No EOl

Filler

Insertable

None

RTC

Normally EOl x 6

(EOl + 1) x 6

EOLx2

K·parameter

Undefined

Present

None

Tag bits

None

Normally 1 bit

None

EOl for head of page

None

2624 run length code

Make-up code x n + termination code

EOFB

End of facsimile block

EOl

End of line

RTC

Return to control

Dummy

Variable-length string of zeros
83Yl-5651B

4-15

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"PD72185
K-Parameter
In the MR system, the K-parameter determines the coding technique and the transmission error recovery procedures. The value of the K-parameter can be specified
as a number from 1 to 255 or as infinity (00).
Whether the code for a particular line uses onedimensional encoding or two-dimensional encoding is
indicated by the value of the tag bit inserted after EOL.
See table 7.

Table 7. Relation Between Encoding System and
Tag Sit
Encoding System

Tag Bit
Val ue

EOl + 1 (tag bit)

One-dimensional
Two-dimensional

Method of Representation

EOl + 0 (tag bit)

Filler Bits
When encoding, the ~PD72185 can adjust the length of
the coded data by adding filler bits. The two methods of
adding filler bits are as follows.
(1) Specify minimum number of bits transmitted with
the BLO command
(2) Specify number of added filler bits with the LNO
command.
When decoding, the
bits.

~PD72185

ignores the added filler

Error Detection

(1) The number of normally-decoded lines (normallyprocessed line count).
(2) The number of lines in error (error line count).
(3) The maximum number of consecutive lines in which
errors occurred (consecutive error line count).
The start of error line counting and successive error line
counting can be specified in either of two ways as shown
below. The selection and setting of the initial value of
each line count is done by command.
(1) Start count from occurrence of first error.
(2) Start count from normal decoding of one line.

HOST INTERFACE
Exchanges between the ~PD72185 and the host CPU (or
an external DMA controller) are performed by 1/0 accesses over the host interface. In general, writes from
the host CPU to the ~PD72185 are in the form of commands and reads from the ~PD72185 are in the form of
responses.
The host bus width is 16 data bits but can be accessed
8 bits at a ti.me by manipulation of the logic level on pins
10Ao and USE. See table 9.

TableS.

Host Sus Width

IOAo

UBE

Bus Width

16 bits

1000-10015

8 bits

1000-1007

8 bits

100S-10015

When decoding, the ~PD72185 can detect errors in the
code and carry out appropriate processing. Table 8 lists
the types of error detection.

Table B. Types of Error Detection
Applicable
Encoding
Systems

Error Detection

Pins

To get the ~PD72185 to start processing, the following
operations are necessary.
(1) Write the command into the command registers.
(2) Write 1 into the CRQ bit of the control register.

Abnormal page end

When the CRQ bit is set, the ~PD72185 begins processing as directed by the command received. Once processing has begun, the host CPU cannot write 1 to the
CRQ bit again for the next processing operation until it
confirms that processing has been completed or interrupted.

Line Number Count

Basic Timing

Illegal code

MH, MR, MMR

Logically inconsistent code

MR, MMR

Decoded line longer than specified line length

MH, MR, MMR

Decoded line shorter than specified line length

When decoding, the
line counting.

4-16

~PD72185

performs three kinds of

Figure 13 is a timing diagram applicable to reads from
the ~PD72185 and writes by the host CPU. Figure 14
shows the timing for an external DMA controller in the
word mode and byte mode.

NEe

#£PD72185

REGISTERS
Exchanges between the ",PD72185 and the host CPU,
including commands and responses, utilize the registers
and the data FIFO area illustrated in figure 15. The
register I/O addresses are OH through DH; EH and FH are
not allowed. Note that the 1/0 addresses are shared by
corresponding registers in the read and write configurations of figure 15.

Figure 13. Read/Write Timing·

Figure 14. Read/Write Timing With Externa' DMA
Controller
Word Mode
DREO

\
I

DACK

\
\

lORD

Read From IlPD72185
IOWR

Read Data

--------------(

)-_n

Write Data

-----------<

)----

DACK

IOAO·IOA3

=x
\

lORD

Read Data

Write to IlPD72185

Byte Mode

)-----DREO

USE

----------{

DACK

;;-

iORi5

DACK
IOAO-IOA3

-IOWR
Write Data

IOWR

X
\

--------(

/
)------83SL-567fiA

Read Data

----<

Write Data

IOAO

)-__ n_-(

}-___ n~

)-)--83SL·5677A

4-17

NEe

"PD72185
Figure IS. Register Organization
Host CPU Write

Host CPU Read
I/O
Address

FIFO

Stalus Register

Command Type

Response Type

Command
Register

Input
Data

Control Register

{

Command
Parameter

rrr-

3H
4H

6H
7H

Response
Parameter

rf-

Low·Order Data

High·Order Data

High.. Order Data

"
Response
Register

Output
Data

FIFO

Control Register
7

I SFTRST IINTRST I eRQ

Status Register
7

210
INTR

I OUTRDY IINRDY I
B3SL-5678B

Control Register

Status Register

The control register is used in writes from the host CPU.
The functions of bits 0,1, and 2 are explained below.

The status register is used in reads from the host CPU.
The functions of bits 0, 1, and 2 are explained below.

Command Request (CRQ). When 1 is written to the
CRa bit after the host CPU has written a command, the
I'PD72185 begins processing according to the command. The CRa bit is automatically reset after completion of processing.

Input Ready (INRDY). A 1 in the INRDY bit indicates the
input data FIFO is ready to receive data from the host
CPU.

Interrupt Reset (INTRST). When the host CPU writes a
1 to the INTRST bit, the INT pin output and the INTR bit
are reset. After being set, the INTRST bit will be reset
automatically.
Software Reset (SFTRST). Software reset by setting
SFTRST to 1 is functionally identical to hardware reset at
the RESET pin.

4-18

Interrupt Request (INTR). The INTR bit shows the same
logic level as the INT pin. The I'PD72185 sets this bit to
notify the host CPU that processing has been completed
or interrupted.

Command· Register
The command register is used in writes from the host
CPU. It has two parts: command type and command
parameter.

ttlEC

J,tPD72185

Response Register
The response register is used in reads from the host CPU.
It has two parts: response type and response parameter.

setting the output of the INT pin to high and at the same
time setting the INTR bit in the status register. See figure
15.

Input/Output Data FIFO

The host CPU, meanwhile, confirms completion or interruption of processing either by sampling the INT signal
level or by software polling the INTR bit.

The p.PD72185 exchanges image data, code, etc., with
the host CPU via the data FIFOs. The input data FIFO and
the output data FIFO are each two bytes wide.

DMA Transfer Timing

IMAGE MEMORY INTERFACE
The image memory interface is between the p.PD72185
and the image memory, which stores image data and
code. Accesses to image memory from the p.PD72185 are
performed by DMA operations using the on-chip DMA
controller. Via the image memory interface, the
p.PD72185 directly controls image memory.
When the p.PD72185 completes command processing, it
reports completion or interruption to the host CPU by

The basic bus cycle in a DMA transfer takes three system
clock pulses: S 1, S2, and S3. In this bus cycle, the
p.PD72185 reads or writes 1 byte or 1 word. See figure 16.
If the access time to an image memory element is long,
and a read/write is not possible within the basic bus
cycle, then the p.PD72185 can insert wait states (SW)
between S2 and S3, extending the read/write pulse
width.
The two methods of inserting a wait state are:
(1) Using the READY pin.
(2) Programming wait states with a command

Figure 16. DMA Transfer Timing

1---- BusCycle'---__I _ - - - - - - - Bus C y c l e - - - - - - _ I
51

CLK

MREa~

MRD _________

\'--_--'1

'"\'--_ _ _ _----'f'\----

MWR _________

MACK

AEN

\'--_ _.....11

READY
ASTB

Ao· A7

f'\----

r-\\'--_ _ _~Ir-\\~___________________

------~I

--------------(I...._ _ _ _ _---'X~___________~)- -

A8-A15ID8~i::

-----a'--__

D_a_ta_ _

---'~I..._ _ _ _ _ _ _Da_ta_ _ _ _ _ ___1)- ---

A16-A23/Do·D7 - - - - - ( A d d r e s ' l - - - - - - G - - - - 8 - - - - - - - - - - < ' -_ _ _D_ata
_ _........) - - - - - (Read)
83SL.5680B

4-19

~EC

I-tPD72185

Bus Cycle Modes
The I4PD72185 has three modes in which it operates on
the image memory bus as a Bus Master. A command
selects the bus cycle mode.
Total Bus Monopolization Mode. The I4PD72185 completely monopolizes the bus. The MREQ and MACK
signals are not used.
Demand Mode. The I4PD72185 holds on to the busby
keeping the MREQ signal high. The length of time held
depends on the data being processed. The I4PD72185 will
always surrender the bus on completing the processing
of a line.
Eight Bus Cycle Monopolization Mode. The I4PD72185
monopolizes the bus for a maximum of eight bus cycles,
after which it releases the bus by dropping MREQ to low.
It waits at leastthree clock intervals before raising MREQ
high again.

the MACK signal level is sampled at the rising edge of
S3, there is a maximum delay of 1 bus cycle + 1/2 clock
interval from the fall of MACK until the I4PD72185 actually releases the bus.
In the total bus monopolization mode, DMA break does
not operate.

Refresh
The I4PD72185 is able to output refresh timing to image
memory, thus facilitating the connection of pseudoSRAM. However, the I4PD72185 does not output the
refresh address itself. Consequently, when DRAM is used
in image memory, a refresh address generation circuit
must be connected externally or a CAS-before-RAS
cycle must be generated.
The refresh function is enabled with a command and
performed with a read cycle to address 80000H. Pin
A23/D7 used as the refresh timing output pin decreases
the bus width to 23 bits ..

DMA Break

COMMANDS

When the I4PD72185 is monopolizing the image memory
bus (MREQ = 1), MACK is normally kept high. If MACK
falls to low while MREQ is high, the I4PD72185 immediately discontinues the DMA transfer. However, because

The I4PD72185 has five types of commands: assignment,
operation, statistical, CLB switch, and special. Table 11
describes the command types; table 12 describes the
commands

Table 11. Command Types
Type

Function

Command

Assignment

Specifies system configuration, storage locations of data processed or to be processed, and processing mode.

MOD, SCDB, SIMB, SPRS, SYS

Operation

Gives directions to I'PD72185 for start of encoding/decoding,
data transfer (composition), and similar processing.

ABT, BLO, CNT, EOl, LNO, MSK, RTAG, RTC, TRO

Statistical

Requests information on processing executed by I'PD72185.

RCLB. RPRS

CLB switch

Specifies use/non-use of compressed line buffer.'

CLB-ON, CLB-OFF

Special

Reads firmware version of the I'PD72185.

RVER

• The compressed line buffer handles compressed storage of the code for one line accordingto the coding mode.

4-20

NEe
Table 12.

ItPD72185

List of Commands

Table 12.

Name

Function

ABT
(Abort)

When a CFE interrupt' is generated, the
"P072185 resumes processing with the ABT
command. However, this is done only for the
line being processed when the interrupt was
generated. When this line is completed, the
"P072185 interrupts processing again.
If the ABT command is issued when an interrupt has not been generated, the
"P072185 cancels the continuous processing
mode.

BLO
(Block
operation)

For block mode, specifies minimum number
of bits transferred, word length of a line,
number of void bits at left/right side, word
length of white mask at left/ right side, etc.
Normally, encoding/decoding by the
"P072185 is performed through this
command.

CLB-ON/OFF
(Compression
line buffer
on/ofQ

User specifies use of compression line buffer
by CLB-ON or CLB-OFF command. Valid
only in line mode.

CNT
(Continue)

When the CNT command is issued, the
"P072185 processes the next consecutive
image area equal in size to the area previously processed using the same processing
mode and encoding/decoding system.

List of Commands (cont)

Name

Requests statistical information from
"P072185 on number of normally-processed
lines, number of error lines, etc., resulting
from processing.

RTAG
(Read tag
pattern)

During decoding, reads tag pattern attached
to start of a line.

During encoding, adds EO L code to coded
data; during decoding, detects added EO L
code.
If the detected EO L code is judged to be
part of the RTC code, the "P072185 starts
RTC search.

FILL
(Fill

During encoding, adds lill bits to coded
data.

LNO
(Line operation)

For line mode, specifies number of fill bits to
be added, word length of a line, number of
void bits at left/right side, tag bit, etc.

MOD
(Mode)

Assigns processing mode, encoding/ decoding format (transfer mode in case of a
transfer), K-parameter, RTC, enlargement/
reduction, etc.

MSK
(White mask)

For line-to-receive mask processing, specifies word length, word length of left/right
side white mask, number of void bits on left/
right, etc. Also performs white mask processing on image buffer.

RCLB
(Read compression line buffer)

When the RCLB command is received, the
"P072185 reads the contents of the compression line buffer. Provides user with pixel
distribution data for a line.

In line mode, interpretation of the tag pattern
by the host CPU allows an individual nonCCITT standard encoding/decoding system
to be implemented.

RTC
(Return to
control)

During encoding, adds RTC code to coded
data; during decoding, detects added RTC
code.

FNER
(Read version
number)

Reads firmware versions built into
"P072185

SCOB
(Set code
buffer)

Specifies start address, size, and start bit
position of image area (code buffer) that
stores code.
When the coded data is coming from the
host CPU side, the start address should be
set to O.

SIMB
(Set image
buffer)

By means of the CNT command, the
"P072185 can resume processing even
when a CFE interrupt has been generated.
EOL
(End of line)

Function

RPRS
(Read process
status)

Specifies start address of reference line in
image memory, and start address and size
of image area (image buffer) that stores image data.
When a transfer is performed, specifies
transfer source/destination address and size
of transfer.

SPRS
(Set process
status)

Specifies initialization values for normal processing line count, maximum error line
count, etc., and abort if error line count exceeds maximum.

SYS
(System)

Assigns specific system parameters such as
image memory organization, bus cycle
mode, word length of a line, etc. Also initializes internal "P072185 parameter table.

TRO
(Transfer
operation)

Performs data transfer/composition for image buffer specified by 1MB command.

* CFE

interrupt is generated if a CEMPT or CFULL response is
returned.

RESPONSES
The I£PD72185 has four types of responses: confirmation, error, statistical, and special. Table 13 describes
the response types; table 14 describes the responses.

4-21

NEe

p.PD72185

Table 13.

Response Types

Type

Function

Table 14.
Response

Reports normal completion of processing
requested by a command

BCD OK, BDCOK,ECDOK,
EDCOK, FlllOK, lCDOK,
lDCOK, MODOK,
MSKOK, POK, RCDOK,
RDCOK, SCDBOK, SIMBOK, SOK, SYSOK, TAGPAT, TRNOK, VEROK

Error

Returned when an
error occurs during
processing requested
by a command.

BlABT, CMDERR,
DBlCRQ lNABT

Statistical

Returns statistical information in response
to a
command.

PRSTBl

Other than above.

CEMPT, CFUll, ClBTBl

Confirmation

Special

List of Responses (cont)

Name
CFUll
(CDB full)

At this point, the "PD72185 enters the CFE
interrupt state and subsequently accepts
only SYS, SCDB, CNT, ABT, RPRS, and
RClB commands. If other commands are
issued, a CFE ERR response is returned.
ClBTBl
(ClBTBl table)

Reports compression line buffer contents in
response to RClB command.

CMDERR
(Command error)

Indicates that there is no command corresponding to input command code.

DBlCRQ
(Double CRQ
error)

Indicates receipt of duplicate command requests during processing, and notifies host
CPU that processing being executed is invalidated.

ECDOK
(EOl code okay)

Indicates EO l code has been added and
output to code buffer by EO l command.

Table 14. List of Responses
Name
BCD OK
(Block code okay)

BLABT
(Block abort)

Sends back to host CPU: number of lines
processed; start address of image data
buffer following processed image data
buffer; start address and start bit position of
code buffer following processed code buffer.
Indicates that during decoding by BlO command, processing was aborted because error line count exceeded maximum value set
by SPRS command.

Indicates specified code buffer has become,
empty during decoding.
At this point, the "PD72185 enters the CFE
interrupt state, and subsequently accepts
only SYS, SCDB, CNT, ABT, RPRS, and
RClB commands. If other commands are
issued, a CFE ERR response is returned.

CFEERR
(CDB full/empty
error)

4-22

EDCOK
(EOl decode
okay)

FlllOK
(FILL okay)

Indicates normal termination of decoding by
BlO command.

Sends back to host CPU: number of lines
processed; start address of image buffer
following processed image buffer; start address and start bit position of code buffer
following processed code buffer.
CEMPT
(CDB empty)

Sends back to host CPU: start address and
start bit position of code buffer following
processed code buffer.

Function
Indicates normal termination of encoding by
BlO command.

In the CFE interrupt state, indicates a command other than SYS, S CDB, C NT, ABT,
RPRS, or RClB has been issued.

Function
Indicates specified code buffer has become
full during encoding.

Indicates detection of EO l code in code
buffer by EO l command.
Sends back to host CPU: address and position of bit following detected EO l code.
Indicates that the number of fill bits specified by a FI Ll command have been output.
Sends back to host CPU: start address and
bit position of buffer code following fill bits.

lCDOK
(Une code okay)

Indicates normal termination of encoding by
lNO command.
Sends back to host CPU: number of lines
remaining in image buffer; start address of
image buffer following processed image
buffer; start address and start bit position of
code buffer following processed code buffer.

lDCOK
(Line decode okay)

Indicates normal termination of decoding by
lNO command.
Sends back to host CPU: number of lines
remaining in image buffer; start address of
image buffer following processed image
buffer; start address and start bit position of
code buffer following processed code buffer.

lNABT
(Line abort)

Indicates that during execution of decoding
by lNO command, processing was aborted
because error line count exceeded maximum value set by SPRS command.
Sends back to host CPU: number of lines
remaining in image buffer; start address of
image buffer following processed image
buffer; start address and start bit position of
code buffer following processed code buffer.

NEe

"PD72185

Table 14. List of Responses (cont)
Name

Function

MODOK
(MOD okay)

Indicates normal termination of MOD command processing.

MSKOK
(Mask okay)

Indicates normal termination of processing
by MSK command.

SYSTEM CONFIGURATION
Figure 17 is a diagram of low-end and high-end system
configurations.

Sends back to host CPU: start address of
next image buffer to be processed.
POK
(Process okay)

When the "PD72185 is in continuous
processing mode, and the object of execution by an ABT command is BlO, LN~,
RTAG, EOl, or RTC, then POK indicates continuous processing mode has been
discontinued.
Sends back to host CPU: start address and
start bit position of code buffer following
processed code buffer.

PRSTBl
(Process status
table)

Reports contents of statistical information
table before it is initialized by SPRS command.
Also reports current contents of table In response to RPRS command.

RCDOK
(RTC code okay)

Indicates RTC code has been added and
output to code buffer by RTC command.
Sends back to host CPU: start address and
start bit position of code buffer following
processed code buffer.

RDCOK
(RTC decode okay)

Indicates detection of RTC code in code
buffer by RTC command.
Sends back to host CPU: address and position of bit following detected RTC code.

SCDBOK
(SCDB okay)

Indicates normal termination of S CDB command processing.

SIMBOK
(SIMB okay)

Indicates normal termination of SIMB command processing.

SOK
(Set okay)

Indicates that when a CNT or ABT command
has been issued and the command to be
executed does not exist, the "PD72185 has
terminated processing.

SYSOK
(SYS okay)

Indicates normal termination of SYS command processing.

TAGPAT
(Tag pattern)

Indicates tag pattern specified by an RTAG
command has been read.
Sends back to host CPU: start address of
code buffer following read tag pattern and
start bit position of that code buffer.

TRNOK
(Transfer okay)

Indicates normal termination of data
transfer/composition processing by TRO
command.
Sends back to host CPU: next transfer
source/destination address.

VEROK
(FWER okay)

Returns firmware version to the host CPU.

4-23

NEe

I'PD72185

Figure 17. System Configurations
Low·End Type

Host
(V50 etc.)

lSystemBus

Hlgh·End Type

<=>

~W.Maln.

~
~

lHostBuS

4-,24

~L.. ~~_~,...~_e_...

lmage MemOty

Bus

ttlEC

FLOPPY-DISK CONTROLLERS

5-1

tt{EC

Floppy-Disk Controllers
Section 5
Floppy-Disk Controllers
""0785A/,,,,0766B
Single/Double Density Floppy-Disk Controller

5003

"P071 085/86
Floppy-Disk Interface

6-21

"P072085/e&B
CMOS Roppy-Disk Controller

6·43

",,072087
Roppy-Disk Controller

5-67

",,072068
Roppy-Disk Controller

&-79

",,072089
Roppy-Disk Controller

500105

5-2

tt{EC

pPD765A/pPD765B
Single/Double Density
Floppy-Disk Controller

NEe Electronics Inc.
Description

Features

The /iPD765A/B is an LSI floppy disk controller (FOG)
chip which contains the circuitry and control functions
for interfacing a processor to 4 floppy disk drives. It is
capable of either IBM 3740 single density format (FM), or
IBM System 34 double density format (MFM) including
double-sided recording. The /iPD765A/B provides control signals which simplify the design of an external
phase-locked loop and write precompensation circuitry.
The FDC simplifies and handles most of the burdens associated with implementing a floppy disk interface.

Address mark detection circuitry is internal to the FDC
which simplifies the phase-locked loop and read electronics. The track stepping rate, head load time, and
head unload time are user-programmable. The
/iPD765AI/iPD765B offers additional features such as
multi-track and multi-side read and write commands
and single and double density capa,pilities.

Hand-shaking signals are provided in the /iPD765A/B
which make DMA operation easy to incorporate with the
aid of an external DMA controller chip, such as the
/iPD8257. The FDC will operate in either the DMA or nonDMA mode. In the non-OM A mode the FDC generates
interrupts to the processor every time a data byte is to
be transferred. In the DMA mode, the processor need
only load the command into the FDC and all data
transfers occur under control of the FDC and DMA
controllers.
There are 16 commands which thetlPD765AltlPD765B
will execute. Most of these commands require multiple
8-bit bytes to fully specify the operation which the
processor wishes the FDC to perform. The following
commands are available.
Read Data
Read Deleted Data
Read 10
Write Data
Specify
Write 10 (Format Write)
Read Diagnostic
Write Deleted Data
Scan Equal
Seek
Scan High or Equal
Recalibrate
Scan Low or Equal
Sense Interrupt Status
Version
Sense Drive Status.

FM, MFM Control

Variable recording length: 128, 256, ... 8192 bytes I
sector

IBM-compatible format (single- and doublesided, single- and double-density)

o MUlti-sector and multi-track transfer capability
o Drive up to 4 floppy or micro floppydisk drives
o Data scan capability-will scan a single sector or
an entire cylinder comparing byte-for-byte host
memory and disk data

o
o
o

Data transfers in DMA or non-DMA mode
Parallel seek operations on up to four drives
Compatible with /iPD8080/85, /iPD8086/88, V-series
and /iPD780 (Z80®) microprocessors

o Single-phase clock: 8 MHz maximum
o +5Vonly
~}

l80 is a registered trademark of the Zilog Corporation.

Pin Configuration
RESET

RD
WR
FlTR/STEP
HOLD

Ordering Information
Device Number

Package Type

Max Freq. of Operation

pPD765AC2

40-pin plastic DIP

8 MHz

pPD765B

40-pin plastic DIP

8 MHz

DB,
DBs
DB,
DB,
DRQ

DACK
TC
INDEX
INT

ClK
GND'-'--_ _......I

NECEL-000324

WClK

5-3

NEe

/APD765A//APD765B
Pin Identification
No.

5
6-13

RD (Read Strobe)

Symbol

Function

RESET

Reset input

Read control input

Write control input

Chip select input

Data or status select input

DBa-DB7

Bidirectional data bus

DRO

DMA request output

DACK

DMA acknowledge input

Terminal count input

INDEX

Index input

INT

Interrupt request output

ClK

Clock input

GND

Ground

WClK

Write clock input

WINDOW

Read data window input

The RD input allows the transfer of data from the FDC
to the data bus when low and either CS or DACK is
asserted.

WR (Write Strobe)
The WR input allows the transfer of data to the FDC
from the data bus when low. Disabled when CS is high.

Ao (Data/Status Select)
The AO input selects the data register (AO =1) or status
register (Ao = 0) contents to be accessed through the
data bus.

CS (Chip Select)
The FDC is selected when CS is low, enabling RD and

WR.

RDATA

Read data input

DBO-DB7 (Data Bus)

SYNC

VCO sync output

Write enable output

DBo-DB? are a bidirectional a-bit data bus. Disabled
when CS is high.

MFM

MFM output

SIDE

Head select output

ORa (DMA Request)

USa, US1

FDD unit select output

WDATA

Write data output

The FDC asserts the DRO output high to request a DMA
transfer.

28,29
30
31,32

PSa, PS1

Preshift output

FlT ITRKO

Fault! track zero input

DACK (DMA Acknowledge)

WPRT 12SIDE

Write protect! two side
input

When the DACK input is low, a DMA cycle is active and
the controller is performing a DMA transfer.

READY

Ready input

HDlD

Head load output

TC (Terminal Count)

FlTRI STEP

Fault reset I step output

lCT I DIR

low current direction
output

When the TC input is high, it indicates the termination of
a DMA transfer. It terminates data transfer during Read/
Write/Scan commands in DMA or interrupt mode.

RW ISEEK

Read I write I seek output

Vee

DC power ( +5 V)

INDEX (Index)

Pin Functions

The INDEX input goes high at the beginning of a disk
track.

RESET (Reset)

INT (Interrupt)

The RESET input places the FDC in the idle state. It resets the output lines to the FDD to 0 (low), except PSO, 1
and WDATA (undefined), INT and DRO also go low;
DBO-7 goes to an input state. It does not affect SRT,
HUT, or HLT in the Specify command. If the RDY input is
held high during reset, the FDC will generate an interrupt within 1.024 ms. To clear this interrupt, use the
Sense Interrupt Status command.

The INT output is FDC's interrupt request. In Non-DMA
mode, the signal is output for each byte. In DMA mode,
it is output at the termination of a command operation.

5-4

CLK(Clock)
ClK is the input for the FOC's single-phase, TTL-level
squarewave clock: a MHz or 4 MHz. (Requires a pull-up
resistor.)

NEe

I-lPD765A/I-lPD765B

WCLK (Write Clock)
The WCLK input sets the data write rate to the FDD. It is
500 kHz for FM, 1 MHz for MFM drives, for 8 MHz operation of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz
FDC operation.

PSO

PS1

Shift
(MFMWDATA)

o
o

o
1
o

Normal
Late
Early

1
1

This signal must be input for read and write cycles.
WCLK's rising edge must be synchronized with CLK's
rising edge, except for the I-IPD765B.

READY (Ready)

WINDOW (Read Data Window)

The READY input indicates that the FDD is ready to receivedata.

The WINDOW input is generated by the phase-locked
loop (PLL). It is used to sample data from the FDD and in
distinguishing between clock and data bits in the FDC.

H OLD (Head Load)
The HDLD output is the command which causes the
read/write head in the FDD to contact the diskette.

RDATA (Read Data)
The RDATA input is the read data from the FDD,
containing clock and data bits. To avoid a deadlock
situation, input RDATA and WINDOW together.

FLT ITRKO (Fault/Track 0)
In the read/write mode, the FLT input detects FDD fault
conditions. In the seek mode, TRKO indicates track 0
head position.

WDATA (Write Data)
WDATA is the serial clock and data output to the FDD.

WPRT 12SIDE (Write Protect/Two Side)

WE (Write Enable)
The WE output enables write data into the FDD.

In the read/write mode, the WPRT input senses write
protected status (at the drive or media.) In the seek
mode, 2SIDE senses two-sided media.

SYNC (VCO Sync)

FLTRISTEP (Fault Reset/Step)

The SYNC output inhibits the VCO in the PLL when low,
enables it when high.

In the read /write mode, the FLTR output resets the fault
flip-flop in the FDD. In the seek mode, STEP outputs
step pulses to move the head to another cylinder. A fault
reset pulse is issued at the beginning or each Read or
Write command prior to the HDLD signal.

MFM (MFM Mode)
The MFM output shows the VCO's operation mode. It is
high for MFM, low for FM.

SIDE(Head Select)
Head 1 is selected when the SIDE output is 1 (high), head

ois selected when SIDE is 0 (low).
USa, US1 (Unit Select 0, 1)

LCTIDIR (Low Current/Direction)
In the read/write mode, the LCT output indicates that
the R/W head is positioned at cylinder 42 or greater. In
the seek mode, the DIR output determines the direction
the head will move in when it receives a step pulse. If
DIR is 0, seeks are performed in the outward direction;
DIR is 1, seeks are performed in the inward direction.

The USo and US1 outputs select up to 4 floppy disk drive
units using an external decoder.

RW ISEEK (Read/Write/Seek)

PSa, P~ (Preshift 0, 1)

The RW/SEEK output specifies the read/write mode
when low, and the seek mode when high.

The PSo and PS1 outputs are the write precompensation
request signals for MFM mode. They determine early,
late, and normal times forWDATA shifting.

GND (Ground)
Ground.

VCc<+5V)
+5 V power supply.

5-5

ttt{EC

IJPD765A/IJPD765B
Block Diagram

DC Characteristics
TA= -10"Cto +70"C, Vee = +5V±1O%

Umils
Pamneter

ORO
~

INT
iiij

Wil

...

write Protect!

_SIde
Index

S,mbol

Min

Input vo~age
low

VIL

-0.5

Input voltage
high

VIH

2.0

Output voltage
low

VOL

Output voltage
high

VOH

Input vo~age
low (CLK +
WCLK)

Vll("') -0.5

Inputvo~ge

VIH("')

...

+0.8

Test

unn

Condition.

Vee+0.5 V

2.4

0.45

IOL =2.0mA

Vee

IOH':: -200""

0.65

Vee+0.5 V

F.uH/'DackD

high
(CLK+WCLK)

Unit Select 0
Unit Select 1
MFMMode

Supply current
(Vee)

Icc

150
140

mA pPD765AC2
mA pPD765B

Input load
current high

IUH

Input load
current low

ILIL

-10

Output leakage
current high

ILOH

Output leakage
current low

ILOL

-10

""
""
""

CLK
Vee

RWISeek
H.... Lood

OHO

H.... SO....
Low CUrrimtI

DIrection
Fault Reeet/Step

Absolute Maximum Ratings
TA=25"C

Unn

Condition.

CIN("')

(Note 1)

Input
capacitance

CIN

(Note 1)

Output
capacitance

COUT

(Notal)

-0.5to +7V
-0.5to +7V

Capacitance

Output voltage, VA

-0.5to +7V

TA=25"C, fc=lMHz, vcc=ov

Umils

-10·C to +70·C
-65·C to +150·C

Comment: Exposing the device to stresses above those listed
In the Absolute Maximum Ratings could cause pemnanent
damage. The device should not be operated under conditions
outside the limits described in the operational sections of this
specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ParametIr
Input clock
capacitance

Spdlol

lin

Note:
(1) All pins except pin under test tied to AC ground.

5-6

VOUT=Vee
VOUT= +0.45 V

Input voltage, VI

Storage temperature, TSTG

VIN=OV

Power supply vo~age, Vee

Operating temperature, TOPT

VIN=Vee

'!'tIt

t\'EC

J,lPD765AI J,lPD765B

DIFFERENCES BETWEEN pPD765A AND
pPD765B
ThepPD765B is a functionally enhanced version ofthe
pPD765A. Differences are explained below.

Overrun Bit [OR]
In pPD765A, when executing a read- or write-type
command (except READ ID and SCAN types), the
result status OR bit is not set if there is an overrun on
the final byte of a sector. An improvement in the
pPD765B allows it to set the OR bit.in any situation.

DRQ Reset
When an overrun occurs, the pPD765A needs DACK
input to reset DRO. If DACK is not available, an
external DMA controller continues to operate even after
the FDC enters the R-Phase (Result Phase), and stored
result status may be transferred accidentally as ordinary
data.
On the other hand, the pPD765B resets DRO automatically just before the R-Phase entry and independent
of the DACK input. See AC Characteristics for DRO
reset timing.

Clock Synchronization
The pPD765B does not require synchronization
between the ClK and WClK inputs.

Version Command
The Version command distinguishes the pPD765B
from other devices. The STO response to the Version
command is:
Part No.

STO Value

pPD765A
pPD765B

80H
90H

5-7

NEe

IAPD765AJlAPD765B
AC Characteristics
TA = -10 to +70·C; Vee = +5 V ±10%
Parameter

Symbol

Min Typ (11 Max

Unit Conditions

Parameter

Symbol

Clock period

¢CY

120

125

500

ns 8-MHz ClK

WClK cycle time

tCY

240

250

500

ns 4-MHz ClK

Clock active
(high, low)

¢o

WClK aclive lime
(high)

Clock rise
time

¢R

ClK t -WClK j
delay

ICWL

Clock fall
lime

¢F

WClK, RDATA and
WINDOW rise lime

Ao, CS, DACK
selup lime 10 RD j

IAR

Ao, CS, DACK _
tRA
hold time from RD t

¢CY MFM =0

¢o

ns IIPD765AC2
only

WClK, RDATA and
WINDOW fall lime

Preshift del a?, lime
from WClK

tcp

100

WClK t - WE t
delay

tCWE

100

WDATA dela?, time
from WClK

tco

100

RDAT A active
time (high)

tROD

Window cycle time

twCY

tRR
tRO

DB to float delay
time from RD t

tOF

Ao, CS, DACK
setup time to WR j

tAW

Ao,CS, DACL
hold time to WR t

tWA

WR width

tww

200

Data setup time to
WRt

tow

100
0

140

ns CL =100pF

250

¢CY MFM = 1
ns Nole 4

RD width

Data hold time from two
WR t

Unit Conditions

16
350

Data access time
from RD j

200

Min Typ (11 Max

ns
2

liS

MFM=O

liS

MFM=1

Window hold time
from RDATA

tROW

Window selup time
to RDATA

tWRo

USo 1 setup time
to SEEK t

tus

liS

tso

liS

INT delay time from tRI
lIDt

2¢CY
+¢o
+ 135

ns Non-DMA
mode

SEEK setup time
to DlR

liS

2¢CY
+¢o
+ 135

Direction setup time tOST
10 step t

1.0

INT delay time from tWI
WRt

USO,1 hold time
from step t

tSTU

5.0

liS

Step active time
(high)

tSTP

Step cycle time

DRa cycle time

tMCY

DACK j - DRa j
delay

tAM

13
140

ORa t - DACK j
delay

tMA

200

DACK width

tAA

2 ¢CY
+15

TC width

tTC

Reset width

¢CY = 125
ns (Note 4)

tRST

tMI

INT- DACK
ineffective

tlA

liS

tsc

tFR

8.0

Write data width

twoo

to
-50

USo, 1 hold time
after seek

tsu

liS

8-MHz ClK
Notes 3, 4,
5

¢CY IIPD765B
only

SEEK hold time
from DIR

tos

liS

8-MHz ClK
Notes 4,5

¢CY

DIR hold time
after step

tsTO

liS

Index pulse width

tlOx

¢CY

ns ¢CY = 125
ns (Note 4)
ns

Note 2 Note 2 liS
10

liS

¢CY
77

Notes 4,5

Fault reset active
time (high)

¢CY

DRa j -INT
response time

5-8

liS

8-MHz ClK
Notes 4, 5

NEe

JAPD765AI JAPD765B

AC Characteristics (cont)
Min Typ (1) Max

Unit Conditions

RO j delay from ORO tMR

800

ns 8-MHz elK
Note 4

WR j delay
from ORO

tMW

250

WR t or RiJ t
response time
from ORO t

tMRW

Parameter

Symbol

Notes:
(1) Typical values for TA = 25°C and nominal supply voltage.
(2) Under software control. The range is from 1 msto 16 msat8-MHz
clock period, and 2 ms to 32 ms at 4-MHz clock period.
(3) When one device is executing a SEEK operation, SENSE DRIVE
STATUS is executed on another device.
(4) Double these values for a 4-MHz clock period.
(5) The drive side rating has a variance of -50 ns from the minimum
value.

Timing Waveforms
Processor Read Operation

Processor Write Operation

Data

--~---~.~~-

__ _ _ _ _ _ _lw_,=1

INT - - - - - - - -

INT

5-9

NEe

",PD765A/",PD765B
Timing Waveforms (Cont)

Seek Operation

Data Input Waveform for AC Test (Except CLK, WCLK)

X~::

2.4
0.45

USO•1

:::X

RWISeek

1..-_ _ __
Direction

Slep

Clock (WCLK, CLK) Input Waveform for AC Test
3.0

"
-----:------"

-----------r.,...,-----"..,-,.
12.4
2.4-\

0.3 _ _ _ _-.JfO.65

0.65\'-_ _ _ __

Overrun Operation (J.lPD7658 Only)

Oulpul Load Capacilance: 1 TTL +100pF

IMI--+i-----R.Phase'-----+i
ORO

Clock

tNT Generation

(Command Execuled)

DMA Operation
ORO

FLT Reset

olieK --I--:--"i
WRor

Fault Reset

0 ~~

-=:.j

tFR

AD
FDD Read Operation

h
("1,---.,.,-=--1 FIRDD §IWRD1
1 1RDw
Read Dala Window _ _ _ _----'C
X
Read Dala

FDD Write Operation

WrileClock

-twCy----Note: Either polarity data window is valid.

Write Enable

Terminal Count
Preshift 0 or 1 _../'-_ _....;,1'\:...1_ _./\_ _----'''---_
TC

Preshift 0
Normal
~---.-

-----=:1

Write Data

-~"-·-o

Preshift 1
0
-~---.------

83-Q02828A

Reset

Invalid - - - - - - - - - · - - - - - - - 1 - Reset

-----=:1
5-10

fttIEC

",PD765AI ",PD765B

Timing Waveforms (Cont)

Table 2. Main Status Register
Pin

Write Clock

No.

FDD number 0 is in the seek mode. If any
of the DnB bits is set FOe will not accept
read or write command.

OBI

DIB
(FDD 1 Busy)

FDD number 1is in the seek mode. If any of
the DnB bits is set FOG will not accept read
or write command.

DB2

D2B
(FDD 2 Busy)

FDD number 2 is in the seek mode. If any
of the DnB bits is set FOG will not accept
read or wrrte command.

DB3

D3B
(FDD3 Busy)

FDD number 3 is in the seek mode. If any
of the DnB bits is set FOG will not accept
read or write command.

DB4

GB
(FOG Busy)

A Read or Write command is in process.
FOG will not accept any other command.

DB5

EXM
(Execution Mode)

This bit is set only during execution phase
in non-DMA mode. When DB5 goes low.
execution phase has ended and result
phase has started. It operates only during
non-DMA mode of operation.

DBe

DID
Indicates direction of data transfer be(Data Input / Output) tween FOG and data register. If 010=1.
then transfer is from data register to the
processor. If DID = O. then transfer is from
the processor to data register.

DB?

ROM
Indicates data register is ready to send or
(Request for Master) receive data to or from the processor. Both
bits 010 and ROM should be used to perform the hand-shaking functions of
"ready" and "direction" to the processor.

----'
83-002827A

Index

Function

DOB
(FDDO Busy)

ClK

WClK

Nlme

DBO

Internal Registers
The j.lPD765A/j.lPD765B contains two registers which
may be accessed by the main system processor: a status register and a data register. The 8-bit main status
register contains the status information of the FDC, and
may be accessed at any time. The 8-bit data register
(which actually consists of four registers, STO-ST3, in a
stack with only one register presented to the data bus at
a time), stores data, commands, parameters, and FDD
status information. Data bytes are read out of, or written
into, the data register in order to program or obtain the
results after a particular command (table 3). Only the
status register may be read and used to facilitate the
transfer of data between the processor and j.lPD765A/
j.lPD765B.

The 010 and ROM bits in the status register indicate
when data is ready and in which direction data will be
transferred on the data bus. See figure 1.

The relationship between the status/data registers and
the signals RD, WR, and Ao is shown in table 1.

Figure 1.

Table 1. Status/Data Register Addressing
Function

Read mai n status register

Illegal

a
a
a

a
a

Illegal

Read from data register

Write into data register

Out FCC and Into Procesaor
Out Processor and Into FDC
Ready
I I
RaquastlorMaater
I~
Data In/Out
(010)

(ROM)

h--

I
Not
II
_IRasdyll
WR
I
u I

I I III I
IIIIII
I I
I II

RD~I

I : I : I I: I:: I
I A IaI A lal A C 10 Ie 101B! A I

Illegal

The bits in the main status register are defined in
table 2.

010 and ROM

Not•• ; ABC0-

Data register ready to be written into by processor.
Data register not ready to be written into by processor.
Data register ready for next data byte to be read by processor.
Data register not ready to be read by processor.

5-11

ttfEC

f.tPD765AI f.tPD765B
Table 3. Status Register Identification

Table 3. Status Register Identification (cont)

No.

Name

Pin
Function

Status Register 0
07,06

IC
(Interrupt Code)

No.

Name

Function

Status Register 1 (conI)
07=0 and 06=0
Normal termination of command, (NT).
Command was completed and properly executed.

NO
(No Oata)

07=Oand 06=1
Abnormal termination of command, (AT).
Execution of command was started but
was not successfu lIy completed.

During execution of Read Data, Read Deleted Data, Write Data, Write Deleted Data
or Scan command, if the FOC cannot find
the sector specified in the IDR(2) Register,
this flag is set.
During execution ofthe Read ID command,
if the FDC cannot read the ID field without
an error, then this flag is set.
During execution of the Read Diagnostic
command, if the starting sector cannot be
found, then this flag is set.

07=1 and 06=0
Invalid command issue, (IC). Command
which was issued was never started.
07=1 and 06=1
Abnormal termination because during
command execution the ready signal from
FOO changed state.

NW
(Not Writable)

During execution of Write Data, Write Deleted Data or Write 10 command, ilthe FOC
detects a write protect signal from the
FDD, then this flag is set.

MA
(Missing Address
Mark)

This bit is set if the FOC does not detect the
lOAM before 2 index pulses. It is also set if
the FDC cannot find the DAM or DDAM afterthe lOAM is found, MD bit of ST2 is also
set at this time.

SE
(Seek End)

When the FOC completes the Seek command, this flag is set to 1 (high).

EC
(Equipment Check)

If afault signal is received from the FOO, or
if the track 0 signal fails to occur after 77
step pulses (Recalibrate Command) then
this flag is set.

NR
(Not Ready)

When the FOO is in the not-ready state and
a Read or Write command is issued, this
flag is set. If a Read or Write command is
issued to side 1 of a single-sided drive,
then this flag is set.

HO
(Head Address)

This flag is used to indicate the state of the
head at interrupt.

USI
(Unit Select 1)

This flag is used to indicate a drive unit
number at interrupt.

USo
(Unit Select 0)

Status Register 2
Not used. This bit is always 0 (low).
06

CM
(Control Mark)

During execution of the Read Data or Scan
command, if the FDC encounters a sector
which contains a deleted data address
mark, this flag is set. Also set if DAM is
found during Read Deleted Data.

DO
(Data Error in
Data Field)

If the FDC detects a CRC error in the data
field then this flag is set.

This flag is used to indicate a drive unit
number at interrupt.

WC
(Wrong Cylinder)

EN
(End of Cylinder)

When the FOC tries to access a sector beyond the final sector of a cylinder, this flag
is set.

This bit is related to the NO bit, and when
the contents of C(3) on the medium is different from that stored in the IDR, this flag
is set.

SH
(Scan Equal Hit)

During execution of the Scan command, if
the condition of "equal" is satisfied, this
flag is set.

OE
(Oata Error)

When the FOC detects a CRC(1) error in eitherthe 10 field orthe data field, this flag is
set.

SN
(Scan Not Satisfied)

During execution of the Scan command, if
the FDC cannot find a sector on the cylinder which meets the condition, then this
flag is set.

OR
(Overrun)

If the FOC is not serviced by the host system during data transfers within a certain
time interval, this flag is set.

BC
(Bad Cylinder)

This bit is related to the NO bit, and when
the contents of C on the medium is different from that stored in the IDR and the contents of Cis FFH, then this flag is set.

MD
(Missing Address
Mark in Data Field)

When data is read from the medium, if the
FDC cannot find a data address mark or
deleted data address mark, then this flag
is set.

Status Register 1
07

Not used. This bit is always 0 (low).

5-12

Not used. This bit is always 0 (low).

NEe

IAPD765AllAPD765B

Table 3. Status Register Identification (cont)
No.

Function

Name

Status Register 3
(Fault)

This bit is used to indicate the status of the
fault signal from the FOO.

WP
(Write Protected)

This bit is used to indicate the status of the
write protected signal from the FOO.

RY
(Ready)

This bit is used to indicate the status of the
ready signal from the FOO.

TO
(Track 0)

This bit is used to indicate the status of the
track 0 signal from the FOD.

TS
(Two-Side)

This bit is used to indicate the status of the
two-side signal from the FOO.

HO
(Head Address)

This bit is used to indicate the status of the
side select signal to the FOO.

US1
(Unit Select 1)

This bit is used to indicate the status of the
unit select 1 signal to the FOD.

USo
(Unit Select 0)

This bit is used to indicate the status of the
unit select 0 Signal to the FOO.

Command Symbol Description
Name

Note:
(1) CRC = Cyclic Redundancy Check
(2) IDR= Internal Data Register
(3) Cylinder (C) is described more fully in the Command Symbol

Description.

Command Sequence
The flPD765A/flPD765B is capable of performing 15 different commands_ Each command is initiated by a
multibyte transfer from the processor, and the result after execution of the command may also be a multibyte
transfer back to the processor. Because of this multibyte interchange of information between the flPD765AI
flPD765B and the processor, it is convenient to consider
each command as consisting of three phases:
Command
Phase:

The FDC receives all information required to perform a particular operation from the processor.

Execution
Phase:

The FDC performs the operation it
was instructed to do.

Result Phase: After completion of the operation,
status and other housekeeping information are made available to the
processor.
Table 4 shows the required preset parameters and
results for each command. Most commands require 9
command bytes and return 7 bytes during the result
phase. The "WOO to the left of each byte indicates a command phase byte to be written, and an "ROO indicates a
result byte. The definitions of other abbriviations used
in table are given in the Command Symbol Description
table.

Function

AO
(Address Line 0)

AO controls selection of main status register
(Ao=O) or data register (Ao=I).

C
(Cylinder Number)

C stands for the current I selected cylinder
(track) numbers 0 through 76 of the medium.

ostands for the data pattern which is going to be
written into a sector during WRITE 10 operation.

(Data)

°rOo

8-bit data bus, where 07 stands for a most
significant bit, and Do stands for a least
significant bil.

OTL
(Data Length)

When N is defined as 00, OTL stands for the data
length which users are going to read out or write
into the sector.

EOT
(End of Track)

EOT stands for the final sector number on a cylinder. During read or write operations, FOC will stop
data transfer after a sector number equal to EOT.

GPL
(Gap Length)

GPL stands for the length of gap 3. During Read I
Write commands this value determines the number of bytes that VCO sync will stay low after two
CRC bytes. During Format command it determines the size of gap 3.

H
(Head Address)

H stands for the logical head number 0 or 1, as
specified in ID field.

HO
(Head)

HO stands for a the physical head number 0 or 1
and controls the polarity of pin 27. (H = HD in all
command words.)

HLT
(Head Load Time)

HLT stands for the head load time in the FOO (2 to
254 ms in 2 ms increments).

HUT
(Head Unload Time)

HUT stands for the head unload time after a Read
or Write operation has occurred (16 to 240 ms in
16 ms increments).

MF
(FM or MFM Mode)

If MF is low, FM mode is selected, and if it is high,
MFM mode is selected.

MT
(Multitrack)

IF MT is high, a multitrack operation is performed. If MT = 1 after finishing read I write operation on side 0, FOC will automatically start
searching for sector 1 on side 1.

N
(Number)

N stands for the number of data bytes written in a
sector.

NCN
(New Cylinder Number)

NCN stands for a new cylinder number which is
going to be reached as a result of the seek operation; desired position of head.

NO
(Non-OMA Mode)

NO stands for operation in the non-OMA mode.

(Data Bus)

PCN
PCN stands for the cylinder number at the
(Present Cylinder Number) completion of Sense Interrupt Status command,
position of head at present time.

R
(Record)

Rstands for the sector number which will be read
or written.

R/W
(Read I Write)

R/W stands for either Read (R) or Write (W)
signal.

SC
(Sector)

SC indicates the number of sectors per cylinder.

SK
(Skip)

SK stands for skip deleted data address mark.

5-13

NEe

!-,PD765A/!-,PD765B
Command Symbol Description (cont)

Command Symbol Description (cont)

Name

Function

SRT
(Step Rate Time)

SRT stands for the stepping rate for the FDD (1 to
16 ms in 1ms increments). Stepping rate applies
to all drives (FH =1 ms, EH=2 ms, etc.).

STO-ST3
(Status 0-3)

STO-ST3 stands for one of four registers which
store the status information after a command has
been executed. This information is available during the result phase after command execution.
These registers should not be confused with the
main status register (selected by Aa=O).
STO-ST3 may be read only after a command has
been executed and contains information relevant
to that particular command.

Function

STP

During a scan operation, if STP=1, the data in
contiguous sectors is compared byte by byte witi1
data sent from the processor (or DMA); and if
STP = 2, then alternate sectors are read and compared.

USa, US1
(Unit Select)

US stands for a selected drive number a or -3.

Table 4. Instruction Set (Notes 1, 2)
Instruction Code
Phase

Read Data
Command

w
w
w
w

MT
X

MF
X

SK
X

0
X

1
HD

1
US1

Remarks

Command codes
(Note 3)
Sector ID information priorto command execution. The 4 bytes
are compared against header on floppy disk.

USa

C
H
R
N
EDT
GPL
DTL

w
w
w
Execution
Result

Data transfer between the FDD and main system

R
R
R
R
R
R
R

--------------~O--------------

Status information after command execution

------------- ST1 - - - - - - - - - - - --------------~2--------------

--------C--------

-------H-------------

Sector ID information after command execution

------R-------------N--------

Read Deleted Data
Command

W
W

MT
X

MF
X

SK
X

0
X

1
X

1
HD

Command codes

C
H
R
N
EDT
GPL
DTL

Sector ID information prior to command execution. The 4 bytes
are compared against header on floppy disk.

R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Status information after command execution

Data transfer between the FDD and ma'in system

Note:
(1) Symbols used in this table are described at the end of this section.
(2) Ao should equal 1for all operations.
(3) X = Don't care, usually made to equal O.

5-14

a
USa

W
W
W
W
W
W
Execution
Result

0
US1

Sector ID information after command execution

t-IEC

/-lPD765AI/-lPD765B

Table 4. Instruction Set (Notes 1, 2) (cant)
Instruction Code
Phase
Wr~e

RIW

W
W
W
W
W
W
W
W
W

MT
X

MF
X

0
X

1
HD

0
US1

USa

Remarks

Data

Command

C
H
R
N
EOT
GPL
DTL

Sector ID information prior to command execution. The 4 bytes
are compared against header on floppy disk.

STO
STI
ST2
C
H
R
N

Status information after command execution

Execution
Result

Command codes

Data transfer between the main system and FDD
R
R
R
R
R
R
R

Sector ID information after command execution

Write Deleted Data
Command

W
W
W
W
W
W
W
W
W

MT
X

MF
X

0
X

1
X

0
X

0
HD

0
US1

Sector ID information priorto command execution. The 4 bytes
are compared against header on floppy disk.

C
H
R
N
EDT
GPL
DTL

Execution
Result

Command codes

USa

Data transfer between the FDD and main system
R
R
R
R
R
R
R

Status information after command execution

STO
ST1
ST2
C
H
R
N

Sector ID information after command execution

Read Diagnostic
Command

W
W
W
W
W
W
W
W
W

0
X

MF
X

SK
X

0
X

C
H
R
N
EDT
GPL
DTL

Execution
Result

0
HD

1
US1

0
USa

Command codes
Sector ID information prior to command execution

Data transfer between the FDD and main system. FDC reads ali
data fields from index hole to EDT.
R
R
R
R
R
R
R

STO
STI
ST2
C
H
R
N

Status information after command execution

Sector ID information after command execution

5-15

t\'EC

iJPD765AIiJPD765B
Table 4. Instruction Set (Notes 1, 2) (cont)

.......

iiii

W
W

0
X

MF
X

0
X

InItnIctIan CIIde
D,
D4

0
HD

US,

0
USo

RIMIrb

RIIIIID
Command

0
X

Execution
Result

Command codes
The first correct ID inlormation on the cylinder is stored in data
register.

R
R
R
R
R
R
R

Status inlormation after command execution

STO
STI
ST2
C
H
R
N

Sector 10 inlormaUon read during execution phase from fioppy
disk.

Wr\tIID [Format Write)
Command

W
W
W
W
W
W

0
X

MF
X

0
X

0
US,

N
SC
GPL
0

Bytes / sector
Sectors / track
Gap 3
Filler byte

STO
STI
ST2
C
H
R
N

Status inlormatlon after command execution

Execution
Result

Command codes

USo

FOG Iormats an entire track.
R
R
R
R
R
R
R

In this case, the 10 inlormation has no meaning

Scan Equll
Command

W
W

MT
X

MF
X

SK
X

0
X

0
HD

C
H
R
N

W
W
W
W

EOT

W
W

GPL
STP

STO
STI
ST2
C
H
R
N

Execution
Result

R
R
NCIt8~

(1) Symbols used In this table are described at the end of this section.
(2) Ao should equal 1 for all operations.
(3) X Don't care, usually made to equal O.

~16

Command codes

USo
Sector 10 inlormation prior to command execution

Data compared between the FDD and main system

R
R
R
R

0
US,

Status inlormatlon after command execution
Sector 10 Inlormation after command execution

fttfEC

IAPD765A/lAPD765B

Table 4. Instruction Set (Notes 1, 2) (cont)
Instruction Code
Pha••

R/W

W
W
W
W
W
W
W

0
HO

0
US1

1
USa

Remarks

Scan Low or Equal
Command

C
H
R
N
EaT
GPL
STP

R
R
R
R
R
R
R

STO
ST1
ST2
C
H
R
N

Sector ID information prior to command execution

Data compared between the FOD and main system

Execution
Result

Command codes

Status information after command execution

Sector ID information after command execution

Scan High or Equal
Command

W
W
W
W
W
W
W

I
HD

a
US1

I
USa

Sector ID information prior to command execution

C
H
R
N
EaT
GPL
STP

R
R
R
R
R
R
R

STa
STI
ST2
C
H
R
N

Status information after command execution

Execution
Result

Command codes

Data compared between the FDD and main system

Sector 10 information after command execution

Recalibrate
Command

W
W

0
X

I
a

I
US1

I
USa

Execution

Command codes
Head retracted to track 0

Sense Interrupt Status
Command

Result

R
R

STO
PCN

W
W
W

0
0
0
0
I
I
0
0
-SRT--HUTHLT
NO

Command codes
Status information about the FOC at the end of seek operation

Specify
Command

Command codes

Sense Drive Status
Command
Result

W
W
R

X
ST3

I
HD

0
US1

0
USa

Command codes
Status information about FDD

5-17

t-IEC

JlPD765AI JlPD765B
Table 4. Instruction Set (Notes 1, 2) (cont)
Instruction Code

Phase

R/W

Command

Result

Remarks

Version

STO

Command codes
90H indicates 765B
BOH indicates 765A / A-2

Seek

Command

W
W
W

1
HD

1
US1

1
USo

Command code

NCN

Execution

Head is positioned over proper cylinder on diskette

Invalid

Command

Invalid Codes

Result

STO

Note:
(1) Symbols used in this table are described at the end of this section.
(2) Ao should equal 1 for all operations.
(3) X = Don't care, usually made to equal O.

System Configuration
Figure 2 shows an example of a system using a
tJPD765A/B.
Figure 2.

System Configuration

08 0 _ 1

MEMR
iOR
MEMW

08 0 _

lOW

Cs
HRO
HLDA

IlPD8257
oMA
Controller

Rii

Wi'i
Cs
INT
RESET

Rea.
Data
Window
RD Data

IlPD765

FoC

Output Control

5-18

Invalid Command codes (No op
STO-BOH

FDC goes into state)

NEe

J.lPD765AI J.lPD765B

Data Format
Figure 3 shows the data transfer format for the /JPD765A
and /JPD765B in FM and MFM modes. Figure 4 shows
veo Sync timing.

Figure 3. Data Format
I'PD765A/B [FM Mode]

Index~

r------------RepeatNTimes-----------~

I'PD765A1B [MFM Mode]

Index~

Figure 4.

i-------------RepeatNTimes--------------i

veo Sync Timing

I'PD765A/B
Index

Format

GAP 48

lAM

GAP 1

GAP 2

DATA

GAP 3

10 ((
I)

------------------~{~

r------,

GAP4b

5-19

I-lPD765AII-lPD765B

5-20

ttlEC

t-fEC

pPD71 065/66
Floppy-Disk Interface

NEe Electronics Inc.

Description

Pin Configurations

The pPD71065 and pPD71066 are CMOS devices that
interface a floppy-disk drive (FDD) with a floppy-disk
controller (FDC). The controller can be pPD765A/B,
pPD7265, pPD72065/B, pPD72066, pPD7260, or one of
the FD179X series.
The floppy-disk interface can operate at various data
rates, including the 300-kb/s rate that results from
using high-density 5-inch drives with media formatted
at the standard 250-kb/s rate. Also, the pPD71065/66
generates the write clock needed by the selected
controller and provides synchronous switching when
changing data rates.

AOSR

AVoo

RDIN

AOSC

MIN/STD

o Compatible with all industry-standard controllers
o Multiple data rates: 500/300/250/150/125 kb/s
o Internal or external sync field detection logic
o Head-loading timer for FD179X-series controllers
o No analog adjustments required
o CMOS, low power consumption
o 5-volt power supply
Ordering Information
Package

Internal Timer

pPD71065G

28-pin plastic SO

Not included

pPD71066CT

3D-pin plastic shrink DIP

Implemented to
FD179X-series
controllers as headloading timer.

FDCSW2

RGATE

LPF1

MFM/FM

LPF2

SYNCSW

Voo

SYNC
RDOUT
RCLK
FDCCLK
WCLK

Features

Part Number

28-Pln Plastic SO

X1
X2
AGND

FDCSW1
VCOIN
FDDSW

cvc
IC
GND
X3
X4
83-002766A

30-Pln Plastic ShrInk DIP

AOSR

AVOD

RDIN
MIN/STD

AOSC

RGATE

FDCSW2
LPF1

MFM/FM

LPF2

SYNCSW

Voo

SYNC
GND
RDOUT
RCLK
FDCCLK
WCLK

FDCSW1
VCOIN
FDDSW
CVC
IC
TCC

TOUT

AGND

X4
83·002765A

NECEL-000587

5-21

t\'EC

J.lPD71 065/66
Pin Identification
Symbol

Input/Output

Function

ACOS

Capacitor connection pin for analog
one-shot

AGNO

Ground for analog circuits

AOSR

Resistor connection pin for analog one-shot

AVoo

Power supply for analog circuits

CVC

Capacitor connection pin for VCO

FDCSWI

FDCSW2

Floppy-Disk Controller

Open or H

pPD765A/7265

Open or H

pPD7260
FD179X series

* FDCSW1 is the trigger input to the timer circuit when FDCSW2 is
low.

FDDSW. The logic level applied to this pin selects the
data transfer rate of the FDD.

FOCCLK

Output

Clock to FDC

FDCSW1

Input*

FOC selection pin or timer trigger input

FDDSW

Data Transfer Rate

FOCSW2

Input*

FOC selection pin

FODSW

Input*

Open or H
L

500/2501125 kbls
500/2501300/150 kbls

Data transfer rate selection pin

GNO

Ground

Internally connected; should be left open
Connection pins to externallowpass filter

MFM/FM Pin. The logic level applied tothis pin and the
FDCSW2 pin selects the modulation type. Double-density
and single-density recording use MFM (modified FM)
and FM modulation, respectively.

LPF1, LPF2

Output

MFM/FM

Input*

Recording density selection pin

MIN Ism

Input*

5- or 8-inch FDD selection pin

RCLK

Output

Read data sampling clock

FDCSW2

MFM/FM

RDOUT

Output

Read data to FDC

MFM

RGATE

Input*

Read enableldisable

Modulation

RDIN

Input*

Read data from FOO

SYNC

Input*

External PLL gain selection

MFM

SYNCSW

Input*

Determines whether gain selection is
internal or external

TCC

External RC time constant connection to
internal timer (pPD71066)

TOUT

Output

Timer signal (pPD71066)

VCOIN

Input

External lowpass filter output to internal
VCO
+5-volt power supply

Voo
WCLK

Output

Write clock to FDC

X1, X2

Connection pins for 16-MHz crystal (X1, X2)
or external clock input (X1)

X3, X4

Connection pins for 19.2-MHz crystal (X3,
X4) or external clock input (X3)

*Input pin has an on-chip pull-up resistor

Pin Functions
The following paragraphs supplement the brief descriptions of certain pins in the preceding table. Pin
symbols are in alphabetical order.
FDCSW1 and FDCSW2. The pPD71065/66 is configured for the applicable FDC by applying logic levels
Land H (or open) to these pins.

5-22

MIN/STD. Logic level L on this pin selects a 5-inch
FDD. An open or H selects an 8-inch FDD.
RDIN. This is a composite read data and clock signal
input from the FDD.
RDOUT. The read data output from this pin is synchronized with the read clock (RCLK) derived from the
RDIN composite signal.
RGATE. In conjuction with FDCSW2, RGATE enables
or disables the read operation that is sent from the
FDC.
FDCSW2

RGATE

Read Operation

Enable

Disable

Enable

t-IEC

pPD71065/66

SYNC and SYNCSW. The PLL gain is determined by
the intput signal at the SYNC pin and the logic levels at
the FDCSW1 and SYNCSW pins.
FDCSWI

SYNCSW

SYNC

Open or H

H (1)

Low

L (1)

High

PLL Gain

H (2)

Low

L (2)

High

Note:
(1) Input signal at SYNC is the PLL gain selection signal between the
ID and DATA fields.
(2) Input signal at SYNC Is the SYNC field detection signal from the
FDC.

Block Diagram
AOSR AOSC

RDIN

LPFI

LPF2

VCOIN

CVC

v
Input
Data
~-----~ Generator

Charge
Pump
and Filler

Selector

1-+--<......

VollageControlled
Oscillator

- - - 0 FDDSW

RGaie 0 - - - - 0 FDCSWI

MIN/STDo-MFM/FM 0 - -

- - - - 0 FDCSW2

XI 0 - - - - 1
X20---~

Clock
X3 0 - - - - 1 Generator

Ident
Field

Output Data
Generator

Timer

hTOUT"
TCC"

t----<>

L...-_....I

X40---~

"Not on IlPD71065

FDCCLK

WCLK

SYNC SYNCSW

RCLK

RDOUT
83-0027678

Functions ofthe block diagram components are explained
below.
Clock Generator. Using both 16-MHz and 19.2-MHz
oscillators, outputs clock signals corresponding to the
mode used to the FDCCLK and WCLK pins.
Input Data Generator. According to the input data,
generates the R and V signals to be input to the phase
comparator. In addition to this, the input data generator
determines whether the analog one-shot circuit or the
digital one-shot circuit is used.

Charge Pump and Filter Selector. According to the PLL
(phase-locked loop) gain selection signal, enables or
disables the LPF2 side charge pump to control the PLL
gain.
Output Data Generator. Generates the window signal
(RCLK) and read data signal (RDOUT) depending on
the mode and FDC to be used.
Sync Byte Detector. Detects the sync field within 16 to
20 pulses regardless of FM or MFM mode.
Ident Field Detector. Determines whether the sync
field detected by the sync byte detector is ID or DATA
field and sets the PLL gain.

5-23

NEe

pPD71065/66
Basic External Circuit

veo Frequency

Figure 1 shows the basic external circuit including the
lowpass filter and crystals. The data transfer rate is
selected by strapping pins FDDSW, MIN/STD, and
MFM/FM to L (low) or open (high). See table 1.

For this procedure, the data transfer rate is undefined.
Strap RGATE to Hand RDIN to L. Adjust resistor R2 to
set the VCO frequency at the RCLK pin to the same
numerical value as the data transfer rate; for example,
500 kHz and 500 kb/s.

The VCO frequency and the phase delay between
RDIN and RDOUT can be optimized by adjusting
resistors R2 and R1, respectively.
Figure 1.

Basic External Circuit
I'PD71066

GND

AVOO Voo

GND

AVOO Voo

Cl0

C2 XTALl

Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12

22 pF
22 pF
22 pF
22 pF
10 pF
1800 pF
33,000 pF
33 pF
10,000 pF
10,000 pF
1000 pF

Rl
R2
R3
R4
R5
R6
R7

3kO
30 kO
22kO
1 kO
1.5 kO
5600
33 kO min

XTALl
XTAL2

16 MHz
19.2 MHz

l/lF

83-0040098

NEe

pPD71065/66

Data Read Phase Delay

Figure 2.

For this procedure, set the data transfer rate to 500
kb/s, set the RDIN signal to a 2-(.1s cycle time, and strap
RGATE to H. Adjust resistor R1 to set the value of tSTW
(figure 2) to 950 ns.

Read Data Timing Diagram

RDIN

~_--,n,--

RDOUT

RCLK
83-004010A

Table 1.

Data Transfer Rate Selection

Floppy·Disk Controllers

Data Transfer Rate
(kb/s)

IlPD765A,IlPD7265,
IlPD72065, IlPD72066
(Note 2)

RCLK (kHz)

WCLK (kHz)

FDDSW

MIN/STU

MFM/FM

250

500

Open

125

250

Open

500

1 MHz

Open

250

500

Open

300

4.8

300

600

Open

150

4.8

Open

500

300
1 MHz

250

500

Open

250

Open

1 MHz

Open

500

Open

300

4.8

600

Open

150

4.8

300

500

1 MHz

250

500

250

500

250
125
500
250

FD179X Series (Note 4)

150
500

250
IlPD7260 (Note 3)

Selection Pins (Note 1)

Clock Output Frequencies from IlPD71 065171 066
FDCCLK (MHz)

Open

125

250

Open

500

1 MHz

Open

250

500

Open

250

Open

300

1.2

300

600

Open

150

1.2

150

300

Open

500

1 MHz

250

500

500
250

L
Open

Nole:

(1) Selection pin states: L = low; Open

= open or H (high)

(2) IlPD765A17265172065/72066:

FDCSW1 and FDCSW2 = Open

(4) FD179X Series:
FDCSW1 = Don't care and FDCSW2 = L.
WCLK clock is not used.

(3) IlPD7260:
FDCSW1 = Land FDCSW2 = Open.
FDCLK clock is not used

5-25

tt{EC

pPD71065/66
Electrical Characteristics

Absolute Maximum Ratings
TA =+25·C

Figures 3 through 8 are test circuits for verifying
certain parameters in the dc and ac characteristics
tables.

Power supply voltage, Voo

-0.3 to +6 V

Input voltage, VI

-0.3 to Voo + 0.3 V

Output voltage, Va

-0.3 to Voo + 0.3 V

Operation temperature, TOPT
Storage temperature, TSTG

-10 to +lO·C
-40 to +125·C

DC Characteristics
TA = -10to +70·C; Voo = +5 V ±10%

limits
Parameter

Symbol

Min

Max

Unit

Input voltage, low

VIL

-0.3

Typ

0.8

Test Conditions

Input voltage, high

VIH

2.2

Voo + 0.3

Output voltage, low

VOL

0.45

IOL =2 mA

Output voltage, high

VOH

0.7 Voo

Voo

IOH = - 200 /lA

Clock input level

VKp-p

Input leakage current, low

IUL

-150

Voo
-50

/lA

VI=OV

+10

/lA

VI = Voo

/lA

Va = 0.45 V

Test Circuit

Figure 5

Input leakage current, high

IUH

-10

Output leakage current, low

ILOL

-10

Output leakage current, high

ILOH

+10

/lA

Va = Voo

Power supply current

100

XTAL: 16 MHz, 19.2 MHz

Figure 3

XTAL: 16 MHz

Figure 4

5-26

NEe

pPD71065/66

AC Characteristics
TA = -10 to +70·C; Voo = +5 V ±10%
Llmlls
Param8ler

Symbol

Max

Unll

ns
ns
ns

Fall time

Typ

Rise time
RDOUT setup time to RClK

Min

Tell Condltlonl

Tesl Circuli

For pPD7260

Figure 6
Figure 7

tSRR

ClK high/low level width

tKK

VCO oscillation Irequency

VCO Iree-run Irequency

3.6
2.1

2.4

2.7

MHz

FDDSW = l, VF = open

VCO control voltage sensitivity

2.5

3.5

4.6

MHziV

I(Voo/2) -:- VF I :5 0.5 V

Kv voltage coefficient

aKviVoO

-1

-19

-22

'IoiV

Ii power supply voltage
coefficient

aliiVOO

'Io/V

MHz

VF=VOO

4.4

MHz

FDDSW = H, VF = open

Ii temperalure coefficient

ali/lA

-500

-1000

ppm/·C

Phase detect sensitivity

0.7

0.8

0.9

V/rad

RClK jitter

tORR

900

950

1000

ICAP

537

427

kHz

500-kb/s mode

286

213

kHz

250-kb/s mode

143

107

kHz

125-kb/s mode

343

256

kHz

300-kb/s mode

172

RDIN

t to RDOUl t delay time

Capture range (Note 1)

500-kb/s mode

128

kHz

150-kb/s mode

FDCClK t to WClK t delay time tOFWR
(Note 2)

CL = 15 pF

FDCClK t to WClK I delay time tOFWF
(Note 2)

CL = 15 pF

Figure 8

Figure 1

Note:

(1) The frequencies in the Max and Min columns are the lower and upper limits, respectively, 01
the capture range. For example, in the 500-kb/s mode, the capture range is from 427 kHz (or
lower) to 537 kHz (or higher).
(2) Clock outputs to FOC.

FDCCLK

WCLK

83SL.-6072B

5-27

~EC

pPD71065/66
Figure 3.

Test Circuit 1
I'PD71 065

GNO

AVOO Voo

GND

AVOO Voo

Cl0

=
C2 XTALl

13
C3

9
14

XTAL2 C4

Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cl1
C12

22 pF
22 pF
22 pF
22 pF
10 pF
1800 pF
22,000 pF
33 pF
10,000 pF
10,000 pF
120 pF
1 ~F

Rl
R2
R3
R4
R5
R6
R7

3 kn
27 kn
10 kn
1 kO
7.5 kO
5800
33 kO min

XTALl
XTAL2

16 MHz
19.2 MHz

83-0040116

5-28

NEe
Figure 4.

pPD71065/66

Test Circuit 2
I'PD71 065

GNO

AVOO Voo

GNO

Cl0

Cl
12

17
Cl
13

13
C2
14

Cl
C2
C5
C6
C7
C8
C9
Cl0
Cll
C12

22 pF
22 pF
10 pF
1800 pF
22,000 pF
33 pF
10,000 pF
10,000 pF
120 pF
11'F

Rl
R2
R3
R4
R5
R6
R7

3 kll
27 kll
10 kll
1 kll
7.5 kll
56011

XTAL

16 MHz

33 kO min

63~OO40'28

5-29

t-IEC

pPD71085/88
Figure 5.

Tea' Circuit 3
"PD71065

GN~-D~

AVDD VDD

AVOD VOO
(5V)

-------~Ci1!f_°------__=r
C~1~0------====Jl~
~----------=:~C9~--------_===~
C9~----___==.J
(SV)

_______________

"PD71066

GND

(5V)

(SV)

~----=~

14
15

C1
C2
CS
C6
C7

ca
C9
C10
C11
C12

22 pF
22 pF
10 pF
1600 pF
22,OOOpF
33 pF
10,000pF
10,000 pF
120 pF
11'F

R1
R2
R3
R4
RS
R6
R7

3 kO
27 kO
10 kO
1 kO
7.5 kll
560 II

33 kO min

83-0040138

5-30

t-{EC
Figure 6.

pPD71065/66

Test Circuit 4
I'PD71066

GND

AVOO VOO
C10

500 kHz

JlJl o--+--_---Q

RCLKLn

I
RDOUT+

ISRR

C1
13
C3
14

=
XTAL2 C4

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12

22 pF
22 pF
22 pF
22 pF
10 pF
1800 pF
22,000pF
33 pF
10,000 pF
10,000 pF
120 pF
1 I'F

R1
R2
R3
R4
R5
R6
R7

3 kll
27 kll
10 kll
1 kll
7.5 kll
560 Il
33 kQ min

XTAL1
XTAL2

16 MHz
19.2 MHz

83-0040158

5-31

ttiEC

pPD71065/66
Figure 7.

Test Circuit 5
I'PD71066

GND

AVOO VOO
Cl0
C9

Cl
13
C3
14

=
XTAL2 C4

Ix = 81RCLK
Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12

22 pF
22 pF
22 pF
22 pF
10 pF
1800 pF
22,000 pF
33 pF
10,000 pF
10,000 pF
120 pF
1 I'F

Rl
R2
R3
R4
R5
R6
R7

3 kO
27 kO
10 kO
1 kO
7.5 kO
5600
33 kQ min

XTALl
XTAL2

16 MHz
19.2 MHz

83-0040148

5-32

NEe
FigureS.

pPD71065J'66

Test Circuit 6
I'PD71066

AVoo Voo
(5V)
(5V)

GNO
Cl0
C9
Minimum Dala
Interval

JUL
SL

RDIN

C8
2

3
RGATE
4
RGATEIu-

,,~,m

RDI"'~
RDOUTLu-t

ISTW

Cl
13
C3
14

400 x (Min Dala Inlerval)
Duly = 50%

Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12

22 pF
22 pF
22 pF
22 pF
10 pF
1800 pF
22,000pF
33 pF
10,000 pF
10,000 pF
120 pF
1 I'F

Rl
R2
R3
R4
R5
R6
R7

3 kll
27 kIl
10 kll
1 kll
7.5 kll
56011
33 kO min

XTALl
XTAL2

16 MHz
19.2 MHz

83-0040168

5-33

t\'EC

pPD71065/66
System Configurations

Table 2.

Figures 9 through 23 are system configuration examples of the pPD71065 and pPD71066 with various
floppy-disk controllers and data transfer rates. See
table 2.

FlOppy-Disk
Floppy-Disk
Interface
Controllers
pPD71065 pPD765A. pPD7265.
pPD72065. pPD72066

System Configuration Examples

For additional details and the values of resistors and
capacitors, see figure 1.

Figure

500/2501.125

300/150

500/250/125

and 300/150
pPD7260

pPD71066 pPD765A. pPD7265.
pPD72065. pPD72066

pPD7260

FD179X

Figure 9.

Dala Transler Rates
Ikb/sJ

500/250/125

300/150

500/2501125
and 300/150

500/250/125

300/150

500/250/125
and 300/150

500/250/125

3001150

500/250/125
and 300/150

500/250/125

3001150

500/250/125
and 3001150

System Example 1: pPD71065 FDI and pPD765A FDC
FDI

FDC

FDD

~PD71065

~PD765A/7265

Data transler rate Is
5001250/125 kb/s

~PD72065172066

lor
250/125 kb/s

lor
500/250 kb/s

/JPDn065 ,

FDC

MIN/STD
SYNC 1-----1 RGATE
MFM

1-----+1 MFM/FM
SYNCSW

DRQ 1 - - - - - - 1 SYNC
RDATA f + - - - - - - f RDOUT
WINDOW f + - - - - - - f RCLK

CVC

951+-----1 FDCCLK
WCLK

1-----1 WCLK

FDD

X1
X2
X3 •

• Open
•• Open or high

X4
83-0039948

5-34

NEe

pPD71065/66

System Example 2: pP071065 FOI and pP0765A FOC

Figure 10.

FDI

FDC

FDD

~PD71065

~PD765A/7265

Data transfer rate is
300/150 kb/s

~PD72065/72066

IlPD71065

FDC

AOSC
FDCSW2

*
SYNC~---~~
MFMI----~~

DRO
RDATA
WINDOW

MIN/STD

LPFl

RGATE

LPF2

MFM/FM

FDCSWl

SYNCSW

VCOIN

I-------l SYNC
1+------1 RDOUT

FDDSW

1+------1 RCLK

CVC

¢ I + - - - - - I FDCCLK
WCLK 1+------1 WCLK

FDD

Xl
X2
X3

* Open

* * Open

Figure 11.

X4
or high

l:MH~

83·0039956

System Example 3: pP071065 FOI and pP0765A FOC

FDI

FDC

FDD

~PD71065

p:PD765A/7265

Data transfer rates are both

~PD72065/72066

500/2501125 kb/s & 3001150 kb/s

for 300/150/
250/125 kb/s

? for

d, 500/250 kb/s

IlPD71065

FDC

AOSC

for
500/250/125 kb/s

? for 500/250/

th 300/150 kbfs
MIN/STD
SYNC
MFM

I-----~

RGATE

1------1 MFMfFM

FDCSWl

SYNCSW
DRO~----~

RDATA
WINDOW

SYNC

1+------1 RDOUT

FDDSW

1+------1 RCLK

¢ I - - - - - - j FDCCLK
WCLK

Mux

1+------1 WCLK
Xl
X2
X3

* Open

* * Open

X4
or high

1:MH~

83-0039968

5-35

NEe

pPD7106S/66
Figure 12.

System Example 4: pPD71065 FDI and pPD7260 FDC
FDI

FDC

FDD

~PD71065

~PD7260

Data transfer rate Is
5001250/125 kb/s

lor
2501125
kbls

lor

5001250 kbls

FDC

RGATE

1-----.-/

MFMI-----.-/

SYNC
RDATA
RCLK

1------1
1-------1 RDOUT
1-------1 RCLK
•

WCLK

FDCSWl

FDDSW
CVC

FDCCLK

1-------1 WCLK

FDD

Xl
X2
X3 •

• Open
•• Open or high

X4
83-003997B

Figure 13.

System Example 5: pPD71065 FDI and pPD7260 FDC
FDI

FDC

FDD

~PD71065

~PD7260

Data transfer rate Is
300/150 kb/s

FDC

RGATE

1-----.-/

MFM

1-----+1

SYNC
RDATA

FDCSWl

1-----+1
1 - - - - -..... RDOUT

RCLK

1+-------1 RCLK

WCLK

1-------1 WCLK

•
•

FDDSW

FDCCLK
FDD

Xl
X2
X3

• Open
•• Open or high

5-36

X4
l:Ml;l

NEe
Figure 14.

pPD71065/66

System Example 6: pPD71065 FDI and pPD7260 FDC
FDI

FDC

FDD

pPD71065

pPD7260

Data transfer rates are both
500/2501125 kb/s & 3001150 kb/s

lor 300/1501
250/125 kb/.

? lor

J, 500/250 kb/.

pPD71065

FDC

AOSC

'or
500/250/125
kb/s

? lor 500/2501

J, 300/150 kb/.
RGATEr---------~

MFM 1-----+/
SYNC

FDCSWlr------+------,

r---------~

RDATA 1+------1
RCLK 1+----------1
Mux

WCLK 1+------1

X3
X4

• Open
•• Open or high

L...._ _ _ _ _.....J 19.2 MHz
83-0039998

Figure 15.

System Example 7: pPD71066 FDI and pPD765A FDC
FDI

FDC

FDD

pPD71 066

pPD765A17265
pPD72065/72066

Data transfer rate Is
500/250/125 kb/s

'or
250/125
kb/s

? lor

J, 500/250 kb/s

FDC

MIN/STD
SYNC

1-----+/ RGATE

MFM r---------.-t MFM/FM
SYNCSW
ORO 1 - - - - - - 1 SYNC
RDATA

1+------1 RDOUT

WINDOW 1+----------1 RCLK

FDDSW
CVC

r/JI+----I FDCCLK
WCLK 1+------1 WCLK
Xl
X2

-. -Open
•• Open or high

TCC •

FDD

TOUT·
X3 •
X4

5-37

t\'EC

pPD7106S/66
System Example 8: pPD71066 FDI and pPD765A FDC

Figure 16.

FDI

FDC

FDD

~PD71066

~PD765A/7265
~PD72065172066

Data transler rate is
300/150 kb/s

FDC

SYNC

1----'-'-'---1

MFM

~----~

MFM/FM
SYNCSW

DRQ f - - - - - ' - - . j SYNC
RDATA

RDOUT

WINDOW

RCLK

FDCCLK
WCLK

WCLK

TOUT.

• Open
•• Open or high

FDD

TCC •

• Xl

= t-i

X4
L.._ _ _ _ _ _-' 19.2 MHz

83-0040018

Figure 17.

System Example 9: pPD71066 FDI andpPD765A FDC
FDI

FDC

FDD

~P071066

~PD765A/7265

Data transler rates are both
500/2501125 kb/s " 3001150 kb/s

~PD72065172066

AOSC

lor 300/1501
2501125 kb/s

Ylor
J, 500/250 kb/s

pPD71066

FOC

'or
500/250/125
kbls

Y lor 500/2501
J, 3001150 kb/.

'-----<>iMIN/STD
SYNC f------.jRGATE
MFM
DRQ

MFM/FM
SYNCSW

FDCSWl

FDD

~----~SYNC

RDATA
WINDOW

¢
WCLK

RDOUT
RCLK
FDCCLK
WCLK

Xl
X2

• Open
•• Open or high

Mux

TCC •

FDD

TOUT.
X3

L..._ _ _ _ _ _..1 19.2 MHz
83-0040028

5-38

t'tlEC
Figure 18.

pPD71065/66

System Example 10: pPD71066 FDI and pPD7260 FDC
FOI
~PD71066

FDC

FDD

~PD7260

Data transfer rate Is
500/250/125 kb/s

'l'lor

! 250/125 kb/s

lor

500/250 kb/s

pPD71066

FDC

AOSC
RDIN
MIN/STD

RGATE

\-----1

MFM~----"

SYNC~----"

MFM/FM

FDCSWl

SYNC

RDATA 1 - - - - - ; RDOUT
RCLK 1+------1 RCLK
WCLK 1 - - - - - ; WCLK
Xl

FDDSW
CVC
FDD

TCC •
TOUT.
X3 •

• Open
•• Open or high

X4
83-004U03B

Figure 19.

System Example 11: pPD71066 FDI and pPD7260 FDC
FDI

FDC

FDD

~PD7106t

~PD7260

Data transfer rate Is
300/150 kb/s

FDC

RGATE 1----"-'-1
MFM~----"

SYNC 1 - - - - - 1
RDATA I+------IRDOUT
RCLK

RCLK
•

FDCCLK

WCLK 1+------1 WCLK
•

X1
X2

TOUT·
X3

• Open
•• Open or high

FDD

TCC •

L.._ _ _ _ _ _-'

= ~
19.2 MHz
83-0040048

5-39

NEe

pPD71065/66
System Example 12: I1PD71066 FDI and I1PD7260 FDC

Figure 20.

FDI

FDC

FDD

~PD7260

"PD71066

Data transfer rates are both
500/2501125 kb/s & 3001150 kb/s

'or 300/1501
2501125 kb/s

1
t

'or
500/250 kb/s

,or
500/2501125 kb/s

/lPD71066

FDC

AOSC

RGATE 1 - - - - -..

? 'or 500/2501
rh 300/150 kb/s

lP F2 1-'VVv--~"
FDCSW11----r----,

MFMI-----i

VCOIN
SYNC 1 - - - - -..
RDATA

fo-------l

FDDSW I + - - - - - - I - - - - t - - - - '

RClK 1+------1

Mux

WClK 1+------1

TCC •
TOUT.
X3
X4

• Open
•• Open or high

'-------..1

19.2 MHz
83-0040058

Figure 21.

System Example 13: I1PD71066 FDI and FD179X FDC
FDI

FDC

FDD

FD179X series

Data transfer rate is
500/2501125 kb/s

,or
250/125 kbls

'or
500/250 kb/s

FDC

AOSC
FDCSW2

r--+----o General·Purpose Timer
Trigger Input

VFOE
DDEN

FDCSWl

General-Purpose Timer

Output

RG/SSO
RAWREAD

RDOUT

RClK

ClK

FDCClK
• WClK
Xl
X2
J=;6:

• Open
•• Open or high

FDDSW
CVC

TCC

FDD

TOUT
X3 •
X4
83-0040068

5-40

NEe
Figure 22.

pPD71065/66

System Example 14: pPD71 066 FDI and FD179X FDC
FDI

FDC

FDD

I'PD71066

FD179X series

Data transfer rate is
300/150 kb/s

I'PD71066

FDC

AOSC

r--+-----<> General-Purpose Timer
Trigger Inpul

VFOE 1-----....:.:.:-1
DDEN I-----~

General-Purpose Timer

FDCSW1~----~----~

Oulpul

RG/SSO 1---------1
RAWREAD 1+-------1RDOUT
RClK

RClK

ClK

FDCClK
- WClK
-

FDD

-Open

Figure 23.

System Example 15: pPD71066 FDI and FD179X FDC

'1> lor 300/1501

FDI

FDC

FDD

I'PD71066

FD179X series

Dala Iransler rales are bolh
500/2501125 kb/s " 3001150 kbls

AOSC

r--+--t---<> General-Purpose Timer

lor
500/250 kb/s

y lor 500/2501
rh 300/150 kb/s

Trigger Inpul

VFOE 1--------1
DDEN 1--------1

'f lor
b 500/250/125 kb/s

I'PD71066

FDC

b 250/125 kb/s

FDCSW11------~----~

General-Purpose Timer
Oulpul

FDD

RG/SSO 1---------1
RAWREAD t--------i
RClK ....- - - - - - i
ClK t--------i
Mux

FDD

- Open
83-004008B

pPD71 065/66

5-42

t-iEC

NEe

"PD72065/658
CMOS Floppy-Disk Controller

NEe Electronics Inc.

Description
The "PD72065/65B CMOS Floppy-Disk Controller (FDC)
is NEC's follow-on to the "PD765A!B.

18u
108

/IS

/IS
/IS

usa, USl hold time from STEP

STEP active time high

usa, USl hold time atter SEEK

SEEK hold time from DIR

DIR hold time atter STEP

STEP cycle time

tsro
tsc

FlTR active time high

lFR

INDEX level high

~OK

Notea:
(1) For the parameters on figures 11 and 12, the minimum values are
50 ns le88 than the values (PS) specified In the table. For _mple,
10 /IS Is actually 9.950 p.8.

(2) While the unit under test Is performing a seek operation, the
SENSE DEVICE STATUS command Is being executed for the
other devices.

16
4

= 125 ns
= 250 ns

WINDOW setup time to RDATA

DIR 8etup time to STEP

8-MHz: <'--____- :-

WDATA

49NR·426B

Figure 10. FDD Read Operation

RDATA

~'--_________

_~_IRD_DDLJ
_

WINDOW

'_ _ _

~'_=:1

!+------IWCy

l='~=::j

~
49NR-427B

Figure 11.

Seek Operation
USO, US1

RW/SEEK

DIR

STEP

49NR·428B

5-53

NEe

"PD72065/65B
Figure 12. FLTR and INDEX Ktlveforms

COMPARISON, I'PD72065/65B VS I'PD765A1B
Table 1 shows differences in the parameters and features
of the FDCs.

Table 1. pPD72065165B and pP0765AIB

49NR-429A

COMPARISON,I'PD72065 VS I'PD72065B
The ",PD72065B is a functionally enhanced version of the
I'PD72065. Differences are explained below.

Overrun Bit (OR)
In the ",PD72065, when executing a read- or write-type
command (except READ ID and SCAN types), the result
status OR bit is not set if there is an overrun on the final
byte of a sector. An improvement in the IkPD72065B
allows it to set the OR bit in any situation.

DRQ Reset
When an overrun occurs, the ",PD72065 needs the DACK
input to reset DRO. If DACK is not available, an external
DMA controller continues operating even after the FDC
enters the R-phase, and stored result status may be
transferred accidentally as ordinary data.
On the other hand, the IkPD72065B resets DRO automatically just before the R-phase entry and independent of
the DACK input. See AC Characteristics for DRO reset
timing.

Clock Synchronization
The ",PD72065 does not require synchronization between the cp clock and WCLK inputs.

VERSION Command
The VERSION command distinguishes the IkPD72065B
from other devices. The STO response to the command
is:
Part No.

STO Value

",PD72065
",PD72065B

SOH
90H

5-54

Parameter

"PD72065/65B

Track format

IBM

Tracks to be recali brated

255

Skipping time after Index
pulse detection

0.2 ms (4 MHz)

1.2 ms (4 MHz)

Input capacitance
Output capacitance

DC Characteristics
= -10 to +70'C; Voo =

Min

+5 V ±10%

Parameter

Symbol

Min

Max

Low-level input
voltage

VIL

-0.5

0.8

High-level input
voltage

VIH

2.2

Voo + 0.5

0.45

Low-level output VOL
voltage

Unit Conditions

IOL

= 2.0

rnA
Voo

IOH =
-200f.IA

IUL

-10

f.IA

VIN

= OV

IUH

+10

f.IA

VIN

= Voo

Low-level output ILOL
leakage current

-10

f.IA

VOUT =
+0.45 V

High-level
output leakage
current

ILOH

+10

f.IA

VOUT
Voo

Voo supply
current

100

rnA

Note 1

High-level
output voltage

VOH

Low-level input
leakage current
High-level input
leakage current

Standby current 1001
Oscillator
stabilization
time

tKS

0.7 Voo

100

f.IA

Notes:
(1) When a 32-MHz crystal is connected to XA 1-XA2 or a 19.2-MHz
crystal is connected to XB1-XB2.

5-62

tvEC

"PD72067

AC Characteristics 1; Standard Floppy-Disk Control
1A = -10 to +70'C;Vo o = +5V:!:10%;
MFM data transfer rate = 500 kb/s
Min

tAR

tRA

tRR

200

tRO

tOF

INT delay time from lID t

tRI

AO, ~, DACK setup time to WR

tAW

Figure

Typ

Max

Unit

Symbol

Parameter

Conditions

Msin System Side
AO, ~,
AO, ~,

l5ACR setup time to lID
l5ACR hold time from RD

lID pulse width
Data access ti me from RD

Data float delay time from RD

AO, ~, DACK hold time from

ns
140

400

tWA

WR pulse width

tww

200

Data setup time to WR

tow

100

WR
INT delay time from WR t

two

tWl

DRa cycle time

tMCY

l5ACR ~ response time from DRa t
DRa delay time from l5ACR ~
l5ACR pulse width

tMA

200

tAM

ACR J.

tMA

400

\\M

~ pulse width

m J. response tlma from ORa t

Note 1

p.8

DR1 .. O. ORO - 0

ne
140

tMR

250

"'CY
n8

WR J. relponse time from ORa t
WFI/RD response time from ORa t

tMW

500

tMRW

TC pulse width

t-rc

RESET pulse width

tRST

NoteS
OR1 =O.ORO-O

p.8

nl
"'CY

NoteS

5-65

ttlEC

"PD72067
AC Characteristics 2; Minifloppy-Disk Control (cont)
Parameter

Figure

Symbol

Min

Typ

Max

Unit

Conditions

Drive Side
RDATA high-level width

tROO

WINDOW cycle time (Note 2)

tWCY

f.\S

MFM =

f.\S

MFM = 1

WINDOW setup time to RDATA (Note 2)

tWRO

WINDOW hold time from RDATA (Note 2)

lRow

USC, USI setup time to SEEK

tus

lIS

SE EK setup time to DIR

tso

lIs

DIR setup time to STEP

tOST

lIS

USC, USI hold time from STEP

tSTU

lIS

STEP high-level width

tSTP

USC, USI hold time from SEEK (Note 4)

Isu

lIS

DIR hold time from STEP

tSTD

lIS

SEEK hold time from DIR

los

lIS

STEP cycle time

tsc

lIs

FLTR high-level width

tFR

INDEX high-level width

tlOX

Notes:
(1) For data transfer in non-DMA mode.
(2) When external VFO is used.
(3) The minimum value for drlve-side parameters Is 50 ns less
than the value expressed In f.\S. For exsmple, 12 lIs Is actually
11.950"s.
(4) While the unit under test Is performing a seek operation, the
SENSE DEVICE STATUS command Is being executed for the
other devices.
(5) CY Is a multiple of the period of a quartz crystal resonator
connected to pins XB1-XB2 or an external clock connected to pin
XB1. The multiple Is four (EXT = 0) or two (EXT = 1).
(6) See figure 1 for timing measurement voltage thresholds.

5-68

Note 3

118
11.7

13.3

"S
118

16.7

118
fJCY

Note 5

ttlEC
Figure 1.

"PD72067

MIlt... Tllre6holt/$ for Timing
1I• •uremenf.

input, Output

~ 2.2V

~2'4V

0.8 V

.....::::::..:....----

0.45 V

Output load = 1 TIL + 100 pF

83St.-5961A

Figure 2. Read Operlllion

',.

4~"i

MO.."",

., ~AAr

tRR

tOF

-tRO--

00-07 -

High-Z
-

~------.

--i

tRI

INT

83SL·S9628

Figure 3. write Opet'llflon
AO,Cs,DACK

Wi5

tww

tow
00 -07

-tW'-L

1--1·
- - -

INT

83SL·58S38

5-69

ttiEC

"PD72067
Figure 4.

DMA Operation
~------------------tMCY------------------~

DRQ

tAM

----tMA------~~~1

1 - - - - tAA -------I

1------------- tMRW -----------1

~----------tMR--------__I

~-'---------

tMW ----------I

~
-~tTC~83SL·59S4B

FIgure 5.

RESET IIItveform

,~ -11--.

--tRST

--it-

83SL-S965A

Figure 6.

Device ReIId Operation

S3Sl-5966B

5-70

tttlEC

"PD72067

Figure 7. Seek Opel'lltlon
USa-US1

RW/SEEK

IDS
DIR

STEP

I------ISC------+i
83SL-5967B

Figure B. FUR tIIId INDEX ...veforms

(2) The status register (table 2) indicates the state of the
p.PD72067. The main system can read the status
register contents at any time.

FLTR_{,,}_

INDEX

(3) The auxiliary command register temporarily stores
auxiliary commands given the p.PD72067.

----. I--

IIDX

Tsble 1. Register Selection
"CI
AO
RD
WR
Operation

'----83SL·5968A

Registers
The p.PD72067 contains three a·blt registers for Interfacing the main system-data, status, and auxiliary command. Control signals CS, AO, RD, and WR select a
particular register operation as shown in table 1.
(1) The data register temporarily stores information
(command, parameter, data, or result status) transferred between the p.PD72067 and the main system.

Read status register

Write auxiliary command register

Read data register

Write data register

Not defined

x
x - Don'tcare
Notes:

(1) When the DAOK Input Is active low, data register selection Is
Independent of OS and AO.
(2) When both CS and AD are set to 0, a write of code other than
auxiliary command code (WR .. 0) Is Inhibited.

5-71

ttlEC

p.PD72067

Table 2. Status Register Contents
Bit

Name

Symbol

Description

Request for master

ROM

Indicates "P072067 is ready to transfer data to and from the main system. Operation
depends on the 010 bit 06.
When DIO = 0, the main system sends data to IlPD72067. When the main system writes
data into "PD72067, ROM is set to 0; when IlPD72067 reads the data, ROM is set to 1.
• C-phase, wait for command
• Non-OMA write E-phase
• SE EK type E-phase
When DIO = 1, IlPD72067 sends data to the main system. When "PD72067 places data in
the data register, ROM is set to 1; when the main system reads the data, ROM Is set to O.
• R-phase
• Non-DMA read E-phase (except for READ ID)

Data input/output

DIO

Indicates the data transfer direction between the main system and IlPD72067.
DIO

Direction
Main system to IlPD72067
IlPD72067 to main system

Non-OMA mode

NOM

Indicates data is being transferred in non-DMA mode (E-phase). In C- or R-phase, bit D5 is
cleared.

"PD72067 busy

Indicates IlPD72067 is in C-phase, R-phase, or read/Wrlte command E-phase. (In SE EK type
E- phase, the CB bit D4 is not set to I.)

FD3 busy

D3B

When bit D4 is set to 1, the next command is not acknowledged.
Indicates that device 3 performs seek operation or that a seek operation termination
interrupt is pending (E-phase).When bit 03 is set to 1, a read/Write type command must not
be written.

FD2 busy

D2B

Same as bit D3 for device 2.

. FDI busy

01B

Same as bit D3 for device 1.

FDO busy

DOB

Same as bit D3 for device O.

Digital Phase-Locked Loop (DPLL)
From the external 32-MHz system clock, the DPLL
generates a WINDOW signal and synchronizes it with
the phase and frequency of read data from a disk drive.

Figure 9.

WINDOW Signal Htlveform

Read Data

The frequency correction range and peak shift margin of
the D PLL are affected by the data transfer rate (pin DR1).
DR1

o
1

Range
±25%
±25%

Margin
81.5
88.6

As shown in figure 9, read data is separated into data bits
and clock bits by sampling with the WINDOW signal. The
bits are centered in the window. If WINDOW is low for
data bits, it is high for clock bits, and vice versa.

5-72

WINDOW
(either waveform)

83SL-G034A

t-{EC

p;PD72067

Data Shift Register

System Clocks

In the read mode, the data shift register converts serial
data into parallel form and outputs it to the 8-bit internal
bus. In the write mode, the process is reversed and serial
data is output to the CRC generator/checker and output
mixer.

The system clock frequencies depend on the type of VFO
and the type of floppy-disk. See table 4.

Clock Shift Register
In the read mode, the clock shift register converts serial
clock bits into parallel form and outputs them to the 8-bit
internal bus. In the write mode, the clock shift register
converts parallel clock bits from the internal bus into a
serial stream and sends it to the output mixer.

Cyclic Redundancy Check (CRC)
The CRC generator/checker operates with the polynomial x 16 + x 12 + x5 + 1. In the read mode, the CRC of
read data is calculated and compared with the CRC byte
added following sector 10 information and data. A mismatch produces an error indication.
In the write mode, CRC is calculated and two CRC bytes
are added following 10 information and data.

Table 4. System Clocks
VFO

Floppy·Dlsk

Internal

Standard or mini

ClockXA
32 MHz

High-density

32 MHz

External

Standard or mini

16 MHz

High-density

16 MHz

ClockXB

19.2 MHz

If a 32- or 16-MHz system clock is required, connect a
quartz crystal resonator to pins XA 1 and XA2, or connect
an external clock signal to pin XA1 and leave XA2 open.
If a 19.2-MHz system clock is required, connect a quartz
crystal resonator to pins XB1 and XB2, or connect an
external clock signal to pin XB1 and leave XB2 open.

Internal Clocks
From the system clock, the /LPD72067 generates the five
internal clocks listed below.

(1) Internal system clock: controls internal operations
and determines the data transfer rate.

Precompensation
Because of the magnetic chracteristics of the media,
read data is shifted from data write timing. Because the
shift can be predicted according to the data pattern, it
can be compensated by preshifting write data in the
opposite direction.
Preshifting is used only for MFM mode, which has a data
window half the width of the window in FM mode. The
precompensation value (shift) is determined in the external mode by the input signals to pins PCSO and PCS 1, or
in the internal mode by bits PSO and PS 1 of the CONTROL INTERNAL MODE command. See table 3.

Table 3. Precompensstion lllalues
PCS1

pcso

Shift

0.0

DR1

125.0
0

187.0
250.0

0.0
208.3

0
0

312.5
416.7

(2) Write clock: frequency is twice the data transfer rate.
(3) DPLL clock: based on the 32-MHz system clock;
source of the WINDOW signal.

(4) Precompensation clock
(5) 71065/66 clock: required if /LP071065 or /LPD71066 is
the external VFO.

Clock Selection
The system clock-32 or 16 MHz at the XA input or 19.2
MHz at the XB input-is selected by the state of the DR1
pin in external mode or the OR1 bit of the CONTROL
INTERNAL MOOE command in the internal mode.
For the selected system clock, the generated internal
clock frequencies (table 5) are specified according to
mode as follows.
(1) External mode: state of ORO pin and command MFM
bit.
(2) Internal mode: state of ORO bit of CONTROL INTERNAL MODE command and MFMcommand bit.
When /LPD71065 or /LPD71066 is used as external VFO,
the clock selected by the DR1 pin is output from the
CLKOUT pin as the 71065/66 operation clock.

5-73

NEe

"PD72067
Table 5. Contl'Ol Signals and Interlllli CloCks

Internal Clocka
Data Transfer

System Clock

DR1

ORO

MFM Bit

Rate (kb/s)

System
(MHz)

125

250

500

32 MHz (Note 1) or 16 MHz (Note 2)

0
0
19,2 MHz

write
(kHz)

DPLL
(MHz)

Precomp

71065/66

16 MHz

9,6 MHz

19,2 MHz

250

500

1 MHz

2,4

150

4,8

150

2,4

300

9,6

150

4,8

300

9,6

300

4,8

500

19,2

Notes:
(1) Internal VFO; Internal mode with EXT - O. or externsl mode,
(2) External VFO; Internal mode with EXT .. 1,

Figure 10. Tnu:Ic Forlllllt.

dex

IBM Format

Gap4a SYNC

lAM

Gapl

SYNC

IDAM

'FF'
X40

'00'
x6

'Fe"
xl

'FF'
x26

'00'
x6

'FE'
xl

'4E'
xSO

'00'
x12

'4E'
x50

'00'
x12

'C2' ,'FC'
x3
x.l

C H R N CRC

Gap2

SYNC

DAM (DDAM)

xl xl xl xl

'FF'
xll

'00'
x6

'FB'
('FS')
xl

'Al','FE'
x3
xl xl xl xl xl

'4E'
x22

'00'
x12

I..

'Al'
x3

,'FB'
('FS')
xl

Data

CRC

.
.

Repeat N times

ECMAIISO Format

Gap3 Gap4b

.
.

MFM

~
FM

MFM

'FF'
x16

The sector format Is the same as the IBM format.

'FF'
x32

# One sector can be added depending on sector configuration

Missing clock part of address mark
FM

AM
lAM
IDAM
DAM
DDAM

MFM

Data

Clock

Data

Clock

FC
FF
FB
FS

D7
C7
C7
C7

C2
Al
Al
Al

OA
OA

C
H
R
N
CRC

Cylinder number (0 thru 76) lAM
IDAM
Head address (0 or 1)
Record section number
DAM
Number of sectors
DDAM
CyClic Redundancy Check"

Index Address Mark
ID Address Mark
Data Address Mark
Deleted Address Mark
User programmable

OA
83SL-60S9B

5-74

ttlEC

"PD72067

Format

Table 6. Us, of Commands

The track format (IBM or ECMA/ISO) is specified by the
FMT bit of the SELECT FORMAT command in internal
mode or by the input signal to the FMT pin in external
mode. See figure 10.

Command Name

READ DATA
Specifies a sector and transfers Its data
-R-EAD--DE-L-E-T-ED-D,6;-;r:-'A- to the host.

Commands

READ ID

Reads a sector ID.

READ DIAGNOSTIC

Checks the track formal

Table 6 describes the 15 commands and 8 auxiliary
commands of the "PD72067.

System Bus Interface
Figure 11 is a reference circuit diagram of the interface
between the "PD72067 and a system bus for data transfer in the DMA mode. The DMA controller is "PD71071. To
prevent I/O port misselection during the DMA cycle, the
Address Enable (AEN) output of "PD71071 inhibits other
I/O ports.

Function

lINd CommtInds

SCAN EQUAL
Compares esch sector data with host
-S-C-A-N-L-OW-O-R-E-Q-UA-L- data and detects a sector that satisfies
the set condition.
SCAN HIGH OR EQUAL

Write Commends
WRITE DATA
Specifies a sector and transfers Its data
-WR-IT-E-D-E-LE-T-E-D-[),6;-lI"A- to the host.
WRITEID

Writes the format of a track.

Floppy-Disk Drive Interface

RECALIBRATE

Moves the resd/Wrlte head to the outermost track (track 0).

Figure 12 is a reference circuit diagram of the interface
between a floppy-disk drive and the "PD72067 when the
VFO is internal.

SEEK

Moves the resd/Wrlte head to the
specified cylinder.

Figure 13 is a reference circuit diagram of the interface
between a floppy-disk drive and the "PD72067 when the
external VFO is "PD71065 or "PD71066. Special signal
functions for this application are described below.

SENSE INTERRUPT
STATUS

Reads the Interrupt factor (seek end!
state change) In the /lPD72067.

SENSE DEVICE STATUS

Reads the FDD status.

MFM

Recording system change signal

SYNC

Read enable/inhibit

CLKOUT
DRQ

System clock to operate "PD71065/66
Lock internal VFO (DPLL)

USO, US1

Drive select decoded by 74139
Select signal for demultiplexer (NAND
gates) and multiplexer(LS157)

RW/SEEK

InitlllllZfl Commend
SPECIFY

Defines a "PD72067 operation mode.

Au1tiliety Commends
SET STANDBY

Drives the "PD72067 In the standby
status.

RESET STANDBY

Releases the /lPD72067 from the standby
status.

SOFTWARE RESET

Initializes the /lPD72067.

ENABLE EXTERNAL
MODE

Sets the /lPD72067In External Mode.

CONTROL INTERNAL
MODE

Sets the /lPD72067 In Internal Mode and
sets both data transmission rate and
precompenestlon value.

ENABLE MOTORS

Controls On/Off of the spindle motot

SELECT FORMAT

Selects either IBM or ECMA/ISO formal

START CLOCK

Starts the clock generator operation.

5-75

NEe

"PD72067
FIfIute 11. PPD72JJ61 to System "'nter'"

I-lPD72067
INT~--~~------------------------------------------------~INT

32MHz~ XAI

",,071082

8-Bit Latch
ABS-ABI5

<~====1 DOoD07

[16MHzJ~

.A-

L.--

v-----

010- 1/--------,
017

XA2

~XBl

19.2 MHz ~

OESTe

L.--

XB2

t t
,--;-----;----------------------------------------vl 00-07
r-----::::;:=l L;::I
:!=I~~~----ICs
I-I,--_Deco
__ ---JL

OBo-DB7 L..-______--,

ABo-AB7 ' - - •

de_,

ABO

L..---------------~------------------~IAO

,---------------~RD
, - - - - - - - - - / WR
r----------,--~I

RESET

, - - - - - - 1 ORO
c:::;::::;;;;:~1 OACK

~LT_C_ _ _ _ _~
J.lPD71 071
DMA Controlier

L..-____-j ENOtTc

'---------I
L-______~..I

RESET - - - - -

OMAAK2
OMARQ2

I--~--t_----------------~~~~~------------.IRESET

10W-----

I--~--t_----------------~~~~--------------·IIOWR

lOR - - - - -

I--~--~----------------~~~----------------.IIORO

L..-------------------.ICS
L..----------------------------------------iASTB
L..---.,.------------------------------------------v'1 AS-AI5 IDO-0 7

L:===~====================~>I AO-A7

AB1S-AB23i
OBs-OBI5

LOW CURRENT
~

FAULT RESET
R--?s157
S

TWO SIDED

WP RT/2S IDE

WRITE PROTECT

FLT/TRKO

FAULT

INDEX

READY

L-

INDEX
READY
74139

usa

DRIVE SELECT 0

US1

DRIVE SELECT 1

DRIVE SELECT 2

DRIVE SELECT 3

RDATA

"""J

WRITE DATA

WDATA

EXT

READ DATA

83Sl--6032B

5-77

ttlEC

"PD72067
Figure 13. pPD72067 to FDD tnt.,'ee 2
JLPD72067

FDD Interface

HDLD

HEAD LOAD

SIDE

SIDE SELECT

WRITE ENABLE

LCTtDlR
FLTRISTEP
RWISEEK

-I

lr>

DIRECTION SELECT
STEP
LOW CURRENT

~157

FAULT RESET

TWO SIDED

WPRTI2SIDE

WRITE PROTECT

,FLTITRKO

FAULT

INDEX

READY

L-

INDEX
READY

74139

usa

DRIVE SELECT 0

US1

DRIVE SELECT 1

DRIVE SElECT 2

DRIVE SElECT 3

r
RDATA
WINDOW
MFM
SYNC

)1PD71 065/)1PD71 066
RCLK
MFMlFM
RGATE

RDIN
SYNC

DRO
CLKOUT
WDATA

RDOUT

... r-

.rr

READ DATA

J
WRITE DATA

EXT
83SL-6033B

5·78

ftt{EC

p,PD72068
Floppy-Disk Controller

NEG Electronics Inc.
PRELIMINARY
Description

Features

The I-IPD72068 FDC is one of NEC's integrated solutions
for today's floppy-disk controller designs. An outgrowth
of the I-IPD765A-long established as the industry standard for floppy-disk contol-the I-IPD72068 maintains
complete microcode compatibility and contains the latest enhancements required for multitasking applications. Additionally, the I-IPD72068 integrates the standard host-interface registers used in IBM PC, PC/XT,
PC/AT, and PS/2® designs.

o Software compatible with I-IPD765A/765B, I-IPD7265,
I-IPD72065/65B, I-IPD72066, and I-IPD72067
o Compatible with V-Series data/control bus and other
standard 8/16-bit CPUs
o IBM and ECMA/ISO formats
o Data transfer rate: 600, 500, 300, 250, 150 kb/s
o High-performance, on-chip digital PLL
o Two system clock generators
o Programmable stepping speed
o Write-compensate circuit (programmable preshift)
o FDD interface
- High-current drivers (24-mA sink)
- Schmitt receivers
o Direct control of four FDDs
- Spindle motor control
- Unit select control
o Three selectable modes support:
- PC, PC/XT, PC/AT, PS/2 registers
- Internal operating mode selection
- External operating mode selection

The I-IPD72068 incorporates a high-performance digital
PLL that is impervious to harmonic lock-on, a characteristic of analog counterparts. Being digital, the PLL requires no adjustments and supports all standard data
rates as well as 600 kb/s.
The I-IPD72068 has on-chip clock generation, selectable
write precompensation, and all the circuitry necessary
for interfacing directly to four floppy-disk drives.
IBM PC, PC/XT, PC/AT, and PS/2 are registered trademarks of International Business Machines Corp.

Ordering Information
Part Number

Package

"PD72068GF-3B9

80-pin plastic miniflat
84-pin PLCC (plastic leaded chip carrier)

50076

5-79

f'tIEC

"P0720e8
Pin Configurations
Btl-PIn

"".'ic Minllllll

"2 SIDE

GND2

"EM3

WR
CS

DSO
GND2
"DSI
"DS2
GND2
"DS3
"DEN 1
GND2
"DENO
GNDI
XB2
XBl
GNDI
XA2
XAI
GNDI
PCSI
PCSO
"INDEX

AO
NC

NC
NC

"FLT

"SIDE
GND2
"FLTR
"HOLD
GND2

NC
"LCT

VDD
VDD
"ENPCS
ACTL

ENi'iW
RSEL
MSEL
RESET

iii5

DRI

GNDI

. . 0101-1--0

O~N"'~ "''''- 9w
Q. < ~
C W
c: c:

...c: ;:

•• •

. •'"'"

* Active level I. variable.
Connect GN01 and GN02 to ground with the shortest possible wiring.

83....0-59199

5-81

~EC

#,PD72068

Pin Identification
Symbol

I/O Signal Function

Symbol

I/O Signal Function

HD LD (*)

Out Head Load. Causes the drive head to contact the
diskette.

ACTL

Address O. Selects I'PD72068 registers.
AO
Registers
Status, auxiliary command, digital out
a
1
Data, control
Active Level. Sets active level of drive interface
signal.
ACTL
Active Level
-0High
1
Low
Chip Select. Validates RD and WR signals when
MSEL = O. In Register mode (MSEL = 1), (;S'may
be used as address line 1 in a typical PC system.

1/0 Data Bus. Bidirectional, three-state data bus.
DENa,
DENI (*)

Out Density. Specifies preset data transfer rate; can be
used for FDD data transfer rate control. See table 1.

DIR (*)

Out Direction. Specifies the seek direction.
DIR Seek Direction
0- Centrifugal
1
Cent ripetal
In

DMARQ
DRO, DRI

DSO-DS3

DMA Acknowledge. Enables DMA cycle.

Out DMA Request. Requests data transfer in DMA mode.
In

INDEX (*)

INT

Out Interrupt Request. Requests main system to process.
transferred data and execution results.

LCT (*)

Out Low Current. Indicates drive head has selected a
cylinder after the 43rd.

MSEL

Mode Select. Validates IBM-PC register and on-chip
peripheral circuits.

PC SO,
PCS,

Precompensation. Selects the preshift amount in
external or register mode.
For internal mode, pull these pins low with high-value
resistors.

(*)
ENPCS
(*)

RDATA (*)

Read data (consists of clock and data bits) from FDD.

Indicates FDD is ready.

RESET

Sets I'PD72068 to idle state. FDD interface outputs
except for WDATA (undefined) are:
ACTL
Output
a
All low
All high

Data Rate. Sets data transfer rate in external mode.
For internal mode, pull these pins low with high-value
resistors.

Out Drive Select. Selects up to four FDDs.
For the main system, INT and DMARQ are set to low
and Do-D7 are set for input.

Out Enable Motor. Controls spindle motor on/off; also can
be used as a general-purpose output port.
In

Enable Precompensation.
ACTL ENPCS
Preshift Value
-0- -a-a ns
I
Assigned by mode
a
Assigned by mode
1
1
1
a ns

When MSEL = 0, I'PD72068 enters external mode
directly after a reset.
RSEL

If the preshiftamount is to be varied according to the
number of cylinders, the appropriate control signal is
input on ENPCS. When applying preshifting to
cylinders 43 and above, variable control can be
performed automatically by connecting the E NPCS
and LCT pins.
ENRW

FLT (*)
FLTR (*)
FMT

Enable Read Write. Validate RD and WR signals when
MSEL = 1. When MSEL = 0, this signal is
meaningless.
Fault. Indicates FDD is faulty.

Out Fault Reset. Releases FDD from fault state.
In

Format. Selects format in external mode.
FMT
Format

O~
1

ECMA

For internal mode, pull this pin low with a high-value
resistor.

5-82

Read. This control signal causes the main system to
read data from the I'PD72068 to the data bus.

READY (*)

(*)
EMO-EM3

lridicates drive head is positioned at physical start
point of track on the medium.

SIDE (*)

Register Select. When MSEL = " used with (;S' and
AO to select registers for IBM-PC (digital out register
and control register). Invalid when MSEL = a

OutSide Select. Selects double-sided drive head.
ACTL
SIDE
Drive Head
0Head a
a (Active high)
a
Head'
1 (Active low)
a
Head'
1
Head a
1

STEP (*)

Out Generates seek pulses.

Terminal Count. Terminates data transfer.

TRKO (*)

Indicates drive head is positioned at cylinder O.

WDATA (*) Out Write data (clock and data bits) to FDD.
WE (*)
WPRT (*)

Out Requests FDD to write data.
In

Indicates medium is write-protected.

Write. Control signal that allows the main system to
write data bus data into "PD72068.

NEe

#,PD72068

Table t. Data Transfer Rate Settings

Pin Identification (cont)
Symbol

I/O Signal Function

XA1, XA2

Crystal A. For internal oscillator frequency control, a
crystal resonator is connected to XA 1 and XA2. For
external clock input at XA 1, XA2 is open.
Frequency = 32 MHz
To support only 500/250 kb/s data rates, crystal B is
not necessary; connect XA2 to XB1.

XB1, XB2

Crystal B. For internal oscillator frequency control, a
crystal resonator is connected to XB1 and XB2. For
external clock input at XB1, XB2 is open.
Frequency
38.4 MHz
19.2 MHz

Input Pins
Mcde
Internal!
external
(Note 1)

OR1

ORO

DENO

500

o
o
o

250

500
300 (600)

500

150 (300)
0

150 (300)
300 (600)

Output Pins
OEN1

250

Data Rate
600 kb/s
Ali other rates

Indicates a medium with two usable sides has been
loaded Into the FOO.

To support only 500/250 kb/s data rates, crystal B is
not necessary; connect XA2 to XB1.
2SIDE (*)

MFM Oats
Transfer
Rate (kb/s)

250
150 (300)

a
o
o

Notes:

No Connection.

GND1

Digital system ground.

(1) In internal mode, DR1 and DRO are bits of the CONTROL
INTERNAL MODE command. In external mode, DR1 and DRO are
input pins.

Buffer system ground.

(2) In register mode, DRO input pin status is "Don't Care" (x).

+ 5-volt power supply

(3) Data transfer rates in parentheses are with a 38.4-MHz crystal
resonator connected to pins XB1 and XB2 or a 3S.4-MHz clock
connected to pin XB1.

GN02
Voo

(*) Active high when ACTL = 0; active low when ACTL = 1.

Pin Reset Status

(4) Data transfer rates are for MFM mode. In FM mode, these rates

(5) DEN1 and DNa values are when ACTL = 1 (active lOW). When
ACTL = 0 (active high), values are inverted.

Reset Statue
Input

DMARQ,INT

Low

WDATA

Undefined

DIR, OSO-DS3,
EMO-EM3, FLTR,
HDLD, LCT,
SIDE, STEP, WE

Low when ACTL =0; high when ACTL= 1.

DENO, DEN1

Output depends on the preset data transfer
rates. Value set when ACTL = 0 Is inverted
when ACTL = 1, and vice versa.

Other pins

are halved.

Operation Modes
Since I4P072068 has been developed from liP 072067,
the external and internal modes available for IIP072067
are also available for I4P072068 (exept the external VFO
mode). In addition, the register mode is available for
I4P072068. The register mode is used to operate the
IBM·PC registers and special-purpose circuits of
I4P072068. Procedures for setting the data transfer rate,
precompensation amount, etc., vary depending on the
modes. The differences in the procedures are shown in
table 2.

5-83

NEe

"PD72068
TIIb/e2. Opetatlon IIotIIM
Mode

MSa
Pin

Data Trana..r
Rata Setting

PrecompenNtIon
Drive Select Amount SettIng

Format
Change

Motor On/Off
Control

None

DO and 01 bits and
DRl pin of control
register

Digital out
register

FMTpln

Digital out register

SELECT
FORMAT
command

ENABLE MOTORS
command

.COmmencl

POSO, PCS1, and
DRl pins

Internal
mode

Note 1

CONTROL INTERNAL USl and USO CONTROL
MODE
bits In the
INTERNAL MODE
command
command
command

External
mode

Note 2

DRl and ORO pins

Notal:
(1) CONTROL INTEFINAL MODE command
(2) ENABLE EXTERNAL MODE command

5-84

POS1, Peso, and
DRl plna

FMT pin

ttlEC

I£PD72068

p.PD72068 Block Diagram
Block upgraded or added to
original!,PD765!72065
Internal signal

XB2

X!31
RESET

Reset
Control

Command

Registers
and
Timers

r'"'

,I/i

W
1-

,,-

L.J.... L'"
-y"

<"""''''

})I

DO-D7

Data Bus
Buffer

U-

Status

MUltiplexer

Data

t
~

I'""",

--y

Ii
W

From
Out

.(7

mvro::R"
rnF\W

System
Interface
Control

L- '-"

EMO
EM1
EM2
EM3

J:lilRiiil hold time from m>

RD pulse width

tRR

I'iD J.
Data float delay time from I'iD r

tRO

tOF

tRI

tAW

tWA

WR pulse width

tww

200

Data setup time to WR

tow

100

Data hold time from WR

two

tWI

Data access time from

I NT delay time from R\)

AO, ~, DMAAK.

RSEL setup time to

EJiiRiiii,
AO, ~, JmAAK, EJiiRiiii,

RSEL hold time from

For ~ when MSEL

ns
140

400

Note 1

For ~ and RSEL when MSEL

INT delay time from

WR r

DMARa cycle time
DMAAK J. response time from DMARa
DMARa delay time from

DliiIAAR J.

ns
400

tMCV

21.7

tMA

333.3

tAM

140

Note 1

tCYB

= 52.08 ns

tCYB

= 52.08 ns

Dfi.1AAR pulse width
I'iD J. response time from DMARa t

8.3

tMR

208.3

WR J. response time from DMARa r

tMW

416.7

tMRW

WRJRD response time from DMARa

TC pulse width

RESET pulse width for
crystal resonator connection

RESET pulse width for
external clock Input

tCYB

/IS

tTC

tRST

tCVA

On power-on

After standby release

tCVA

After standby release
When external clock Is Input to XBl pin

tRST

Clock hold time on standby

twc

128

tCYB

Clock setup time after standby release

tcw

tCYB

START CLOCK command write setup time to
RESET STANDBY command write

tws

tCYB

INT response time from DMARa J.

tMI

240

DliiIAAR signal Invalid from INT r

tlA

308

tCYB

During normal operation

During normal operation
On power-on

5-93

t-IEC

liP 072068
AC Characteristics 3; 300 kb/s (cont)
Parameter

Figure

Symbol

Min

Typ

Max

Unit

Conditions

Dr;". Side
RDATA high-level width

tROD

WDATA high-level width

twoo

ns
416.7

20
-=-==--________
...;p,S'--_

11 _ _toso
_D_SO_-_D_S_3_s_e_tu,"-p_t_im_e_t_o_D_IR--c(N_o_t_e_4:..)_ _ _ _ _ _
DIR setup time to STEP

tOST

1.7

tSTU

8.3

tSTP

DSO-DS3 hold time from STEP (Note 4)

STEP high-level width

DSO-DS3 hold time from DIR (Notes 3. 4)

toos

tSTD

STEP cycle time

tsc

FLTR high-level width

tFR

13.3

INDEX high-level width

tloX

Notes:
(1) For data transfer In non·DMA mode.
(2) The minimum value for drlve-slde parameters Is 50 ns less
than the value expressed In /'S. For example. 20 /'S is actually
19.950"s.
(3) While the unit under test Is performing a seek operation. the
SENSE DEVICE STATUS command Is being executed for the
other devices.
(4) Except In register mode.
(5) See figure 3 for timing measurement voltage thresholds.

5-94

p,S
p,S

11.7

13.3

p,S
p,S

/'s
16.7

/'S
tCYB

tCYB = 52.08 ns; Note 2

NEe

"PD72068

AC Characteristics 4; 150 kb/s

TA = -10 to + 70"C; voo = +5 V ±10%;
MFM data transfer rate = 150 kb/s; tCYA

= 31.25 ns (32 MHz at XA 1 pin); tCYS = 52.08 ns (19.2 MHz at XB1

Parameter

Figure

Symbol

Min

Typ

Max

Unit

DMAAK, E NRW setup time to RD

tAR

DMAAK, ENRW hold time from RD

tRA

200

pin)

Conditions

Main System Side
AO,
AO,

CS,
CS,

RD pulse width

tRR

Data access time from RD.I

tRO

tOF

INT delay time from RD i

tRI

CS, DMAAK, 'ENl'i'VV, RSEL setup time to ViR
AO, CS, DMAAK, 'ENl'i'VV, RSEL hold time from

tAW

WR pulse width
Data setup time to WR

Data float delay time from

AD i

AO,

ns
140

For ENRW when MSEL = 1

400

Note 1

For ENRW and RSEL when MSEL = 1

tWA

tww

200

tow

100

Data hold time from WR

two

INT delay time from WR i

tWI

Note 1

OMARa cycle time

tMCY

43.4

,.s

tCYS

DMAAK .I response time from OMARa i

tMA

666.6

OMARa delay time from DMAAK .I

tAM

DMAAK pulse width

ns
400

140
16.3

ns
tcys

RD .I response time from OMARa i

tMR

416.7

ViR .I response time from

tMW

833.4

OMARa i

= 52.08 ns

tCYS = 52.08 ns

WR/RD response time from OMARa i

tMRW

TC pulse width

tTC

RESET pulse width for
crystal resonator connection

tRST

tCYA

On power-on

After standby release

tCYA

After standby release

twc

256

tCYS

When external clock Is Input to XBl pin

tCYS
tCYS

RESET pulse width for
external clock input

Clock hold time on standby

tRST

Clock setup time after standby release

tcw

128

START CLOCK command write setup time to
RESET STANDBY command write

tws

128

INT response time from OMARa .I

tMI

480

DMAAK signal invalid from INT i

tlA

,.s

616

tcys

tCYS

During normal operation

During normal operation
On power-on

5-95

NEe

#,PD72068

AC Characteristics 4; 150 kb/s (cent)
Parameter

Figure

Symbol

Min

Typ

Max

Unit

Conditions

Drive Side
RDATA high-level width

tRDD

WDATA high-level width

tWDD

DSO-DS3 setup time to DIR (Note 4)

tDSD

DIR setup time to STEP

tDST

3.4

833.4

--------~------~--------------------~~-------------------

DSO-DS3 hold time from STEP (Note 4)

tSTU

16.6

STEP high-level width

tSTP

DSO-DS3 hold time from DIR (Notes 3, 4)

tDDS

DIR hold time from STEP

tSTD

STEP cycle time

tsc

110

FLTR high-level width

tFR

26.6

INDEX high-level width

tlDx

Notes:
(1) For data transfer in non-DMA mode.

(2) The minimum value for drive-slde parameters is 50 ns less
than the value expressed in "s. For example, 40 "s is actually
39. 950 l's.
(3) While the unit under test is performing a seek operation, the
SENSE DEVICE STATUS command is being executed for the
other devices.
(4) Except In register mode.
(5) See figure 3 for timing measurement voltage thresholds.

5-96

"s
23.4

26.6

33.4

1'8

1'8
tCYB

tCYB

= 62.08 ns;

Note 2

NEe

/-,PD72068

AC Characteristics 5; 600 kb/s
~ = -10 to +70"C; Voo = +5 V :t10%;
MFM data transfer rate = 600 kb/s; tCYA = 31.25 ns (32 MHz at XA 1 pin); tCYB = 26.04 ns (38.4 MHz at XB1
Parameter

Figure

Symbol

Min

Typ

Max

Unit

tAR

tRA

200

pin)

Conditions

lIain System Side
AO,
AO,

'CS, DMAAK, ENFMI setup time to AD
'CS, DMAAK, E NFMI hold time from RD

RD pulse width

tRR

Data access time from RD ~

tRO

Data float delay time from RD t

tOF

INT delay time from RD t

'CS,
AO, 'CS,

AO,

DMAAK, ENRN, RSEL setup time to

tRI

400

Note 1

For ENFMI and RSEL when MSEL

tAW

tWA

WR pulse width

tww

200

Data setup time to WR

tow

100

Data hold time from WR

two

INT delay time from WR t

tWI

OMARa cycle time

DMAAK ~ response time from OMARa t

DMAAK, ENRN, RSEL hold time from

ns
140

For ENFMI when MSEL

Note 1

tMCY

10.8

p's

tCYB

= 26.04 ns

tMA

166.7

tCYB

= 26.04 ns

400

OMARa delay time from DMAAK ~

tAM

DMMK pulse width

tAA

RD ~ response time fro~ OMARa t

tMR

104.2

WR ~ response time from OMARa t

tMW

208.3

140
8.6

ns
tCYB

WR/RD response time from OMARa t

tMRW

TC pulse width

tTC

RESET pulse width for
crystal resonator connection

tRST

tCYA

On power-on

After standby release

tCYA

After standby release
When external clock is input to XB1 pin

RESET pulse width for
external clock Input

tRST

p.s

Clock hold time on standby

twc

128

tCYB

Clock setup time after standby release

tcw

tCYB

START CLOCK command write setup time to
RESET STANDBY command write

tws

tCYB

INT response time from DMARQ ~

tMI

240

DMAAK signal invalid from INT t

tlA

308

tCYB

During normal operation

During normal operation
On power-on

5-97

NEe

"PD72068
AC Characteristics 5; 600 kb/s (cont)
Parameter

Figure

Symbol

Min

tROD

Typ

Max

Unit

Conditions

Drive Side
RDATA high-level width

WDATA high-level width

DSO-DS3 setup time to DIR (Note 4)

DIR setup time to STEP

ns
ns

208.3

twoo
toso

/IS

tOST

0.8

/IS

~----~------~--~------------~~------------~-

DSO-DS3 hold time from STEP (Note 4)

tSTU

4.2

STEP high-level width

tSTP

5.0

DSO-OS3 hold time from DIR (Notes 3, 4)

toos

12.5

tSTD

STEP cycle time

tsc

27.5

FLTR high-level width

tFR

6.7

INDEX high-level width

tlOX

Notes:
(1) For data transfer In non-DMA mode.
(2) The minimum value for drive-side parameters is 50 ns less
than the value expressed In "s. For example, 10 lIS is actually
9.950/IS.
(3) While the unit under test Is performing a seek operation, the
SENSE DEVICE STATUS command Is being executed for the
other devices.
(4) Except In register mode.
(5) See figure 3 for timing measurement voltage thresholds.

5-98

/IS
5.8

6.7

lIs
lIS

8.3
tCYB

tCYB = 26.04 ns; Note 2

NEe

I'PD72068

AC Characteristics 6; 300 kb/s

TA = -10 to +70'C; voo = +5 V :t10%;
MFM data transfer rate = 300 kb/s; tCYA

= 31.25 ns (32 MHz at XA1
Figure

Parameter

pin); tCYB

Symbol

Min

= 26.04 ns (38.4 MHz at XBl

Typ

Max

Unit

pin)

Conditions

Main System Sids
AO,

eg, DMAAK, ENRN setup time to Rl5

tAR

AO,

eg, DMAAK, ENRN hold time from Rl5

tRA

200

RD pulse width

tRR

Data access time from RD J,

tRO

tOF

Data float delay time from RD
INT delay time from RD

For ENRN when MSEL

ns
140

400

tRI

Note 1

tAW

For ~ and RSEL when MSEL

AO, CS, DMAAK, ENRw, RSEL hold time from
WR

tWA

WR pulse width

tww

200

Data setup time to WR

tow

100

two

AO,

eg, DMAAK, ENRw, RSEL setup time to WR

Data hold time from

INT delay time from WR

DMARa cycle time

tMCY

21.7

tMA

333.3

OMARQ delay time from OMAAK J,

tAM

OMAAK pulse width

t
WR J, response time from DMARa t

DMAAK J, response time from DMARa

ns
400

tWI

140

Note 1

tCYB

= 26.04 ns

tCYB

= 26.04 ns

tAA

16.6

tCYB

tMR

208.3

tMW

416.7

tMRW

TC pulse width

tTC

RESET pulse width for
crystal resonator connection

tRST

tCYA

On power-on

After standby release

tCYA

After standby release
When external clock Is Input to XB1 pin

RO J, response time from DMARa

WR/Ro response time from DMARa

RESET pulse width for
external clock Input

tRST

Clock hold time on standby

twc

256

tCYB

Clock setup time after standby release

tcw

128

tCYB

START CLOCK command write setup time to
RESET STANDBY command write

tws

128

tCYB

INT response time from DMARa J,

tMI

480

tlA

DMAAK signal invalid from INT

616

tCYB

During normal operation

During normal operation
On power-on

5-99

ttlEC

"PD72068
AC Characteristics 6; 300 kb/s (cont)
Figure

Parameter

Symbol

Min

Typ

Max

Unit

ConditIOns

Dri"eSide
RDATA high-level width

tAoo

WDATA high-level width

twoo

ns
416,7

20
-===-________
-.:..f.IS_ tcva = 26,04 ns; Note 2

11 _ _ toso
_D_S_0_-D_S_3_s_e_tu...:p_t_im_e_to_D_I_R...;{...;N_ot_e_4:..)_ _ _ _ _ _

tOST

1,7

tSTU

8,3

tSTP

toos

tSTD

DIR setup time to STEP

DSO-DS3 hold time from STEP (Note 4)

STEP high-level width

DSO-DS3 hold time from DIR (Notes 3, 4)

DIR hold time from STEP

STEP cycle time

tsc

FLTR high-level width

tFA

13,3

INDEX high-level width

tlOX

f.IS
f.IS
11,7

13,3

f.IS
f.IS

16,7

f.IS
tcva

Notes:
(1) For data transfer In non-DMA mode,
(2) The minimum value for drive-side parameters Is 50 ns less
than the value expressed in f.IS, For example, 20 f.IS is actually
19,950 /ls,
(3) While the unit under test is performing a seek operation, the
SENSE DEVICE STATUS command is being executed for the
other devices,
(4) Except In register mode,

(5) See figure 3 for timing measurement voltage thresholds,

Figure 4. Read Operation

AO'CS'=i

OMAAK,ENAW

.' r

t-AR------------tRA-

'I"

tRR

I---

'-------

tDF

tRD-

I+-

High-Z

DO-D7

---------"'1

- - - 11--'- -

INT

--L

~-------

tRI

83Sl-5759B

5-100

ttlEC
Figure 5.

I'PD72068

write Opel'llt;on
AO,05, RSEL,
OMAAK,ENRW

=> ~
,

tWA
,....-.

tww

tow

)

00-07

1---- tW'---L-t

- - - INT

Figure. II DIIA Operation
~--------tMCY--------~

OMARQ
~---tMA---~-'1
~--

tAA----i

~-----tMRW------

~----

tMR----....,

~----tMW-----~

TC_~
-~tTC~83SL-S761B

Figure 7. RESET Mllvetorm

5:101

tttlEC

"PD72068
Figure B. Standby Operlltlon (WIth Exterlllli Cloele InpufJ

)o(XXX'~-"AXXXX)O
"I=cw

External
Clock

twc

tws

Noles:
(1)

SET STANDBY command write.

(2)

START CLOCK command write.

(3)

RESET STANDBY command write.

(4)

When in standby mode the extemal clock should be
fixed low. The standby current specifications cannot
be met unless this is done.
83S\..-5755B

FIgura. Operation in Cllse of Overrun
R-Phase

IMI
DMARQ

INT

/
I---tlA

DMAAK Signal _
Invalid TIme

INT generation on completion of command
838L-5764B

FIgure 1D. RDlDlllnd WLMa IIIrveforms
RDATA.

%l\

-~ ~-:D
WDATA

%l\
- ~ ~-::83SL-5788A

5-102

NEe
Figure 11.

I-tPD72068

Seek Operanion
DSO-DS3

-X

=:ox

----- ~-t-DS-D-------------------t-DD--S~~----------

~----~------------

DIR

tSTD
tSTU

---l

STEP

~-----------tsc--------~~
83SL-5766B

Figure 12. FLTR and INDEX Waveforms

FLTR

INDEX

-t,,}'----A}
- . f-tlDX

'----

83SL·5767A

5-103

"PD72068

5-104

NEe

I'PD72069
Floppy-Disk Controller

NEe Electronics Inc.

Description

Pin Identification

The I£PD72069 Floppy-Disk Controller (FDC) is one of
NEC's integrated solutions for todayS floppy-disk controller designs. An outgrowth of the I£PD765A-long
established as the industry standard for floppy-disk
contol-the I£PD72069 maintains complete microcode
compatibility and contains the latest enhancements required for multitasking applications. Additionally, the
I£PD72069 integrates the standard host-interface registers used in IBM PC, PC/XT, PC/AT, and PS/2~ designs.

Symbol

I/O

Signal Function

Address O. Selects a register in "PD72069.

ACTL

Active Level. Sets active level of drive Interface
signal.

The I£PD72069 incorporates a high-performance analog
PLL that requires no adjustments and supports all standard data rates as well as 600 kb/s and 1 Mb/s for the
latest advances in tape and disk technology.

ACTL
0-1
CGP1,
CGP2

DE NO,
DENt (*)

Out
In

Chip Select. Validates RD and WR signals.
Data Bus. Bidirectional, three-state data bus.

Out

Density. Specifies the density of a drive that can
support more than one density. The output is a
value corresponding to the selected data
transmision rate.
DENO: When DRt = 0 and DRO = " the DENO
output Is 1. Otherwi se It Is O.
DEN1: When DRt = 1 and DRO = " the DENI
output Is o. Otherwi se it is 1.

Features

Cl
Cl
Cl
Cl
Cl
Cl
Cl

Charge Pump. Phase difference of sub PLL
devices.

I/O

The I£PD72069 has on-chip clock generation, selectable
write precompensation, and all the circuitry necessary
for interfacing directly to four· floppy-disk drives.

Active Level
High
Low

100% I£PD765A/765B software and hardware
compatible
IBM and ECMA (Sony) formats
Analog PLL (no adjustment required)
Data transfer rate: 1 Mb/s; 600, 500, 300, 250, 150
kb/s
Two system clock generators
Write precompensation (programmable shift values)
Programmable stepping speed
Direct control of four FDDs
- Spindle motor control
- Unit select control
- High-current driver outputs (open drain)
Three selectable modes support:
- PC, PC/XT, PC/AT registers
- Internal operating mode selection
- External operating· mode selection

Ordering Information
Part Number

Package

"PD72069L

84-pln PLCC (plaatlc leaded chip carrier)

tOO-pin plaatlc mlniflat

The values specified above are applicable when
ACTL = 1. The values are reversed when ACTL =

O.
DIR (*)

Out

Direction. Specifies the seek direction.
ACTL
-0-

o
1
1
In

DMARQ

DIR

01
0
1

Direction
Outward
Inward
Inward
Outward

DMA Acknowledge. Enables DMA cycle.

Out

DMA Request. Requests data transfer in DMA
mode.

DRO-DR2

Data Rate. Sets data transfer rate In external
mode.

DSO-DS3

Out

Drive Select. Selects up to four FDDs.

Out

Enable Motor. Controls FDD spindle motor on/off;
also can be used aa a general-purpose output
porl

ENIDX (*)

Enable Index. Validates I NDEX and RDATA signals
from FDD.

ENPCS

Enable Precompensatlon. This pin is usually
connected to the LCT pin

Enable Read Write. Validate i15 and WR signals
when MSEL = t. When MSEL = 0, this signal is
meaningless.

(*)
EMO-EM4

(*)

IBM PC, PCIXT, PC/AT, and PS/2 are regletered trademarks of International Business Machines Corp.
FLT (*)
FLTR (*)

In
Out

Fault. Indicates FDD is faulty.
Fault Reset. Releases FDD from fault state.

50077

5-105

ttlEC

"PD72069
Pin Identification (cont)

Pin Identification (cont)

Symbol

I/O

SI gnal Function

Symbol

I/O

'Slgnal Function

FMT

Format. Selects format in external mode.

XAl, XA2

Crystal A. For internal oscillator frequency
control, a crystal resonator is connected to XA 1
and XA2. For external clock input at XA 1, XA2 is
open.

FMT

Format

ECMMSO

O~
HOLD (*)

Out

INDEX (*)

Indicates drive head is positioned at physical
start point of track on the medium.

Out

Interrupt Request. Requests main system to
process transferred data and execution results.

INT
LCT (*)

Out

Low Current. Indicates drive head has selected a
cylinder on or after the 43rd.

LPF1,
LPF2

Out

Lowpass Filter. Phase difference of main PLL
devices.

MSEL

Mode Select Validates IBM-PC register and onchip peripheral circuit.

PCSO,
PCSI

Precompensation. Sets precompensation value
in external or register mode.

RDATA (*)

READY (*)
RESET

RSEL

In
In

STEP (*)
TC
TRKO (*)

Out

Out
In
In

I/O Signal Function
In

Crystal B. For internal oscillator frequency control, a
crystal resonator is connected to XBl and XB2. For
external clock Input at XB1, XB2 is open.
Frequency = 19.2 MHz

2SIDE (*)

Indicates a medium with two usable sides has been
loaded into the FDD.
Internal Connection. Connect to GNDI

No Connection.

Read. This control signal causes the main system
to read data from the IIPD72069 to the data bus.

GNDI

Ground for digital devices.

GND2

Ground for analog devices.

Read data (consi sts of clock and data bits) from
FDD.

GND3

Indicates FDD is ready.
Sets IIPD72069 to idle state. FDD interface
outputs except for WDATA (undefined) are;
Output
ACTL
o
All low
1
All high
For the main system, INT and DMARQ are set to
low and 00-07 are set for input.
Register Select. When MSEL = 1, used with 'OS
and AO to select register for IBM-PC (digital out
register or control register). Invalid when MSEL =
Side Select. Selects double-sided drive head.
Drive Head
ACTL
SIDE
-0-0Head 0
1
Head 1
o
1
Head 1
o
1
Head 0
1
Generates seek pulses.
Terminal Count. Terminates data transfer.
Indicates drive head is positioned at cylinder O.

WDATA (*)

Out

Write data (clock and data bits) to FDD.

WE (*)

Out

Requests FDD to write data.

WPRT (*)

Indicates medium is write-protected.

Write. Control signal that allows the main system
to write data bus data Into IIPD72069.

5-106

Symbol
XB1, XB2

SIDE (*)

Frequency = 16 MHz

Head Load. Sets drive head in the load state.

Ground for buffers.

VOOI

+5-volt power supply for digital devices.

VOO2

+ 5-volt power supply for analog devices.

(*) Active high when ACTL '" 0; active low when ACTL '" 1.

Output Pin Reset Status
Pin

Reset Status
Input

DMARQ,INT

Low

CGP1, CGP2,
LPF1, LPF2,
WDATA

Undefined

DIR, DSO-DS3,
EMO-EM3, FLTR,
HOLD, LCT,
SIDE, STEP, WE

Low when ACTL = 0; high when ACTL = 1.

DENO,DENI

Output depends on the preset data transfer
rates. Value set when ACTL '" 0 is inverted
when ACTL = 1, and vice versa.

NEe

I'PD72069

Pin Configurations
~inPLCC

'"a. a~
z g
z::t:
w
•••

-'
5 zw
..:

(.)

15
..:

;:: Ii:

;::

..:

" ~~ Z'" t;w 15
'"
• • • • '"• • • • • • • •

8z ~
~

C3
~ 0; w Q Cl
z a:
a:

0.. a:

;;::

Cl
~

GND1

GND3

CGP1

"EMO

"EM1
GND3

CGP2

"EM2

NC
GND2

"EM3

GND3

LPF2

"DSO

"DS1

LPF1

GND3

*DS2
*INDEX

VDD2
VDD1
RESET

*DS3

ENRW

GND3

*DEN1

RSEL

DENO

XB2

XB1

GND1

XA2

MSEL

XA1

O~"'''''''",2

.. ClK

..........
5-127

"PD72069

5-128

NEe

HARD-DISK CONTROLLERS

6-1

NEe

Hard·Dlsk Controllers
Section 6
Hard·Dlsk Controllers
,.pD7281 AlB

6-3

Hard-Disk Controllers
,.pD7282

8-39

Enhanced Small-Disk Interface Controller
"PD72081

8-87

CMOS Hard-Disk Controller
,.PD72111

Small Computer System Interface Controller

6-2

8-89

tt.'EC

pPD7261A/B
Hard-Disk Controllers

NEe Electronics Inc.
Description
The jJPD7261A and jJPD7261B hard-disk controllers are
intelligent microprocessor peripherals designed to control a number of different types of disk drives. They are
capable of supporting either hard-sector or soft-sector
disks and provide all control signals that interface the
controller with either SM D disk interfaces or ST506-type
drives. The sophisticated instruction set minimizes the
software overhead for the host microprocessor. By using the DMA controller, the microprocessor needs only
to load a few command bytes into the jJPD7261A/7261B
and all the data transfers associated with read, write, or
format operations are done by the jJPD7261A/7261B and
the DMA controller. Extensive error reporting, verify
commands, ECC, and CRC data error checking assure
reliable controller operation. The jJPD7261A/7261B provides internal address mark detection, ID verification,
and CRC or ECC checking and verification. An eightbyte FIFO is used for loading command parameters and
obtaining command results. This makes the structuring
of software drivers a simple task. The FIFO is also used
for buffering data during DMA read/write operations.

Pin Configuration
SYNC
RIWDATA

(RGATE)

RIWCLK

(WGATE)

RESET
INT
(PCL)

DREQ

USTG

(PCE)

SSTG

(OSO)
(SKC)
(TRKO)
(READY)
(WFLT)

(DSO)
(DS1)
(HSO)
BT5

(HS1)

BT6

(HS2)
(RWC)
(STEP)
(DIR)

Note: Signals shown in parentheses are used in the ST506 mode.
49-000954A

Ordering Information
MaxFreq.

Features
D Flexible interface to various types of hard disk
drives
D Programmable track format
o Controls up to 8 drives in SMD mode; up to 4 drives
in ST506-type mode
D Parallel seek operation capability
D Multi-sector and multi-track transfer capability
D Data scan and data verify capability
D High-level commands, including:
Read Data, Read 10, Write Data, Format, Scan Data,
Verify Data, Verify ID, Check, Seek (normal or buffered); Recalibrate (normal or buffered), Read
Diagnostic (SMD only); SpeCify, Sense Interrupt
Status, Sense Unit Status, and Detect Error
D NRZ or MFM data format
o Maximum R/W ClK frequency:
-12 MHz (7261A)
-18 MHz (7261B-18)
- 23 MHz (7261 B-23)
D Error detection and correction capability
D Simple I/O structure: compatible with most
microprocessors
D All inputs and outputs except clock pins are TTlcompatible (clock pins require pullup)
D Data transfers under DMA control
D NMOS
D Single +5-volt power supply
D 40-pin ceramic DIP
NECEL-00347

Device Number

Package Type

"PD7261AD

40-pin ceramic DIP

of Operation

12MHz

40-pin ceramic DIP

18MHz

40-pin ceramic DIP

23MHz

Pin Identification
No.

Symbol

Function

Host Interface
4

RESET

Reset input

INT

Interrupt request output

DREQ

DMA request output

Terminal count input

Chip select input

Read strobe input

Write strobe input

12-19

Do-D7

Data 1/0 bus

GND

Ground

CLOCK

External clock input

Vee

+5 V power supply

SYNC

Pll synchronization
output

R/W DATA

Read I write data I I 0

R/W ClK

Read I write clock input

SMD Interface

6-3

tt¥EC

pPD7261A/B
Pin Identification (cont)
No.

TC (Terminal Count)

Symbol

Function

BT9-BTO

Bit 9-0 outputs I Status
inputs

.The TC input goes low to signal the final DMA transfer.

8MD Interface (coni)
21-28,38, 39
29-31

TGHG3

Tag 1-3 output

BDiR

Bit direction output

SSTG

SR select tag output

USTG

Unit select tag output

SCT

Sector input

INDEX

Sector zero input

81506-1ype Interface

RD (Read Strobe)
When the RD strobe is low, data is read from the selected register.

WR (Write Strobe)
When the WR input is low, data is written to the selected
register.

SYNC

Pll lock I Read clock
enable output

R/WDATA

Read I write data I 10

Ao (Register Select)

R/WClK

Read I wrtte clock input

The Ao input is connected to a non-multiplexed address
bus line. When Ao is high, it selects the command or status register. When it is low, it selects the data buffer.

DlR

Direction in output

STEP

Step pulse output

RWC

Reduced write current
output

00-07 (Data Bus)

HS2-HSO

Head select outputs 2-0

Do-D7 are connected to the system data bus.

24-26
27,28
29

DS1, DSO

Drive select outputs 1, 0

WFlT

Write fault input

READY

Ready input

TRKO

Track zero input

SKC

Seek complete input

DSD

Drive selected input

CLOCK (Clock)
The CLOCK input is the timing clock for the on-chip
processor.

Pin Functlons-SMD Interface

PCE

Precomp early output

SYNC (Pll Synchronization)

PCl

Precomp late output

INDEX

Index input

WGATE

Write gate output

This output goes high after the read gate signal (BT1
when fG3 = 0) is high and a given number of bytes
(GPL2-2) has elapsed.

RGATE

Read gate output

Pin Functions-Host Interface
RESET (Reset)
When the RESET input is pulled high, it forces the device into an idle state. The device remains idle until a
command is issued to the system.

INT (Interrupt Request)
The ",PD7261A/7261B pulls the INT output high to request an interrupt.

DREQ (DMA Request)
The ",PD7261A/7261B pulls the DREQ output high to request a DMA transfer between the disk controller and
the memory.

6-4

CS (Chip Select)
When the CS input is low, it enables reading from or writing to the register selected by Ao.

R/W DATA (Read/Write Data)
The R/W DATA pin outputs the write data to the drive,
and inputs the read data from the drive.

R/W ClK (Read/Write Clock)
R/W ClK is the input for the read and write clocks.
BT9-BTO (Bit 9-0)
BT9-BTO output the bit signals, bit 9-0. The bit 9-0 outputs send cylinder and unit addresses to the drives.
BT9-BT2 also act as inputs for status signals from the
drives as shown in table 1.

ttiEC

tL PD7261A/B

Table 1. Bit and Control Information
No.

Bit

Control

BT9

Unit Selected

BT8

Seek End

BT7

Write Protected

R/W DATA (Read/Write Data)
The R/W DATA pin outputs the write data to the drive,
and inputs the read data from the drive.

R/W ClK (Read/Write Clock)
R/W ClK is the input for the read and write clocks.

BT6

BT5

Unit Ready

BT4

On Cylinder

BT3

Seek Error

BT2

Fault

BT7-BT2 also read the device status 2 (SR7-SR2) and
device type (OT7-0T2). The index and SCT pins read
SRO, SR1 and OTO, DTt

BDiR (Bit Direction)
The BOIR output determines whether pins 28-21 will
output BT2-BT9 or input drive status signals.

TG3-TG1 (Tag 3-1)
The TG outputs define the use of the BT pins. When TG1
is low, BT9-BTO output the cylinder address. When TG2
is low, BT7-BTO select a head address. When TG3 is
low, BT9-BTO output control signals for the disk drive.

SSTG (SR Select Tag)
When the SSTG output is low, BT7-BT2, INDEX and SCT
will be inputting SR7-SRO or DT7-DTO.

USTG (Unit Select Tag)
When the USTG output is low, BT4-BT2 will be outputting a unit address.

INDEX (Index)
The INDEX input goes high when the drive detects an
index mark. INDEX also acts as the SRO and DTO input
pin.

SCT (Sector)
The SCT input goes high when the drive detects a sector
mark. SCT also acts as the SR1 and DT1 input pin.

DIR (Direction In)
The DIR output determines the direction the read/write
head will move in when it receives a step pulse. DIR high
will cause the head to move inward, DIR low will move
the head outward.

STEP (Step Pulse)
STEP outputs the head step pulses.

RWC (Reduced Write Current)
The RWC output signals that the read/write head of the
disk drive has selected a cylinder address larger than
that specified in the SPECIFY command. This signal is
used to reduce the write current.

HS2-HSO (Head Select 2-0)
The HS2-HSO outputs select the head. Up to 8 read!
write heads can be selected per drive.

DS1, DSO (Drive Select 1,0)
The DS1 and DSO outputs select one of up to 4 drives.

WFlT (Write Fault)
The WFlT input detects write faults.

READY (Ready)
The READY input detects the drive's ready state.

TRKO (Track 0)
The TRKO input signals that the head is at track O.

SKC (Seek Complete)
The SKC input signals that a seek is complete.

DSD (Drive Selected)
The DSD input signals that the drive is selected.

Pin Functions-ST506·Type Interface

PCE (Precomp Early)

SYNC (Read Clock Enable)

When the PCE output is high, early write precompensation is required.

SYNC indicates that a sync pattern has been detected
and that synchronization has been achieved.

PCl (Precomp late)
When the PCl output is high, late write precompensation is required.

6-5

t-{EC

pPD7261A/B
INDEX (Index)

DC Characteristics

The INDEX input goes high when the drive detects the
index mark.

*I'PD7261B specifications are preliminary
TA = 0 to + 70"0, Vcc = +5.0V ±10% unless otherwise specified

Limits

WGATE (Write Gate)

VIL1

- 0.5

+0.8

VIL2

-0.5

+0.6

ClK, R/WClK

Input voltage
high

VIH1

+2.0

Vee+0.5 V

All except ClK,
R/WClK

Input voltage
high

VIH2

+3.3

Vee+0.5 V

ClK, R/WClK

Output voltage
low

VOL

Qutput voltage
high

VOHl

+2.4

IOH=-100iiA,
all except pins
21-34

Output voltage
high

VOH2

+2.4

IOH= -50iiA,
pins 21-34

Input leakage
current

IUl

iiA

VIN=Vee to
0.45 V,
all except pins
21-34

Input leakage
current

IU2

-500 iiA VIN = Vee to
(7261A)
0.45 V;
--~~--':"'--7-00-'--iiA- pins 21-34

Output leakage
current

ILO

Supply current

Icc

Input voltage

WGATE output goes high when the JlPD7261A/7261B is
writing data.

Test
Condltlons
All exceptClK,
R/WClK

Parameter

S,mbol

Min

Trp

Mall

Un"

low
Input voltage

low

RGATE (Read Gate)
The AGATE output goes high when the
7261B is reading from the disk.

JlPD7261AI

Block Diagram
R/WCLK
BT1(RGATE)

+0.45

VIOL = +2.0 mA

ClK

R/WDATA

RESET

BTO(WQATE)
SYNC

(PCL)SCT
INDEX

±10

DO-D7----~~

TC
AO
iiii

Internal
RAM

(72618)

cs
INT

DREQ
ROM
(Control Firmware)

250

±10

iiA

320

Mall

Unit

VOUT= Vee to
0.45V

Capacitance
TA=25·C, Vcc=OV

Absolute Maximum Ratings
Operating temperature, ToPT
Storage temperature, TSTG

Umlts
O·Cto +70·C
-65·Cto +150·C

VOltage on any pin with respect to ground, Vee

-0.5to +7.0V*

Input voltage, VI

-0.5to +7.0V*

Output voltage, Va

-0.5to +7.0V*

Comment: Exposing the device to stresses above those listed in
the Absolute Maximum Ratings could cause permanent damage. The device should not be operated under conditions outside
the limits described in the operational sections of this
specification. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

6-6

Input
capacitance

CIN

Test
Conditions
(Note 1)

Output
capacitance

COUT

(Note 1)

Input/Output
capacitance

CliO

(Note 1)

Parameter

S,mbol

Min

TrP

Note:
(1) f=l MHz,AII unmeasured pins tied to GND.

-- -

---------~-

t-{EC

",PD7261AIB

AC Characteristics
TA=Oto +70°C;Vcc= +5V ±to%;CL=tOOpF(50pFfor726tB-23)
Limits

7261A
Parametsr

Symbol

Min

726111-23

72611·18
Max

Min

MIx

Min

Max

Unit

Tell
Condition.

Processor Interlace

20
20

Clock cycle

tCY

Clock time. low

tCl

83
30

Clock time. high

tCH

Clock rise time

tCR

Clock fall time

tCF

AO. CS setup to RD

tAR

Ao. CS hold from RD

tRA
tRR

0
100

RD pulse width

0
200

Data delay from RD

tRD

Output float delay

tRDF

Data delay from Ao. CS

tAD

Ao. CS setup to WR

tAW

Ao. CS hold from WR

IWA

WR pulse widlh

tww

Dala setup 10 WR

low

Data hold from WR

tWD

Recovery lime from RD. WR

tRV

150
0

100
150

0
0
200
100

Reset pulse widlh

IRES

5
200
100

TC pulse width

tTC

100

85
0

75
85

0
0
100
55
5

75
85

ns
ns

0
100

55
5
70

70
100

100

ns
ns
os
ICY
ns

INT delay from WR t

IWI
tWRO

200
250

200
125

DREn delay from WR t
DREQ delay from RD t

IRROt

250

160

During disk read
operation

tRR02

150

100

After disk read
operation

DREQ delay from RD ~

130

8T506·Type Interlace

R/W CLK cycle period

tRWCY

R/W CLK lime. low

IRWCl

83
30

R/W CLK time. high
R/W CLK rise time

IRWCH

ns
ns
ns

IRWCR

R/W CLK fall lime
IRWCF
R/W DATA selup to R/W CLK IRDRC
R/W DATA hold from R/W
tRCRD

35
5

CLK

R/W DATA delay from R/W

IWCWD

300
150
110

300
150

150

CLK
RGATE delay from R/W CLK

IRCRG

WGATE delay from R/W CLK

tWCWG

PCE I PCL delay from R/W
CLK

IRWCPC

SYNC delay from R/W CLK

IRWCSY

150

300
150
10

80
150

6-7

twEe

",PD7261AIB
AC Characteristics (cont)
Limits
7281.

PIIl'llmeter

72818·18

Symbol

Min

OSO, OSlselup 10 STEP

IDSST

01 Rselup 10 STEP

IOIST

250
200

STEP pulse widlh

ISTEP

ISTDS

750

69
750

OIR hold from STEP

ISTOI

OSO, OSI hold from SKC

ISKDS

750
100

Mal

Min

72818·23

Mil

Min

Mal

Unit

Test
Condldons

ST506-~pa Interface (cont)

OSO, OSI hold from STEP

250
200
85

100
250

250
200
85

69
750

ICY

ICY
ICY

750
100

ICY

100

ICY

250
200
69

ICY

DlR hold from SKC

ISKDI

OSO, OSI selup 10 STEP

IDSSTB

DIR setup 10 STEP

IOISTB

STEP pulse widlh

ISTEPB

STEP cycle period

ISTCY

200
69
500

OSO, OSI hold from STEP

ISTDSB

200

500
200

OIR hold from STEP

ISTDIB

OSO, OSI hold from SKC

ISKDSB

200
100

OIR hold from SKC

ISKDIB

100

ICY

Index pulse widlh

IIDXF

IRWCY

43
15
17

85
660

500
200

Normal seek mode

ICY

85
660

Normal seek mode;
polling mode
Normal seek mode;
non polling
Buffered seek mode

ICY
ICY
ICY

Buffered seek mode;
polling mode

ICY
ICY

Buffered seek mode;
nonpoUing

SMD Interfaca

R/W ClK cycle period
R/W ClK lime, low
R/W ClK time, high

IRWCL

83
30

55
20

IRWCH

R/W ClK rise time

IRWCR

R/W ClK faU lime

IRWCF

R/W DATA setup 10 R/W ClK IRDRC
R/W DATA hold from R/W
IRCRD

40
5

35
5

ns
ns

ClK

R/W DATA delay from R/W

IWCWD

300
150
150

ClK
BTl delay from R/W ClK

IRCRG

BTO delay from R/W ClK

IWCWG

SYNC delay from R/W ClK

IRWCSY

BOIR setup 10 USTG

IBDUT

BOIR hold from USTG

IUTBD

Unit AOR selup 10 USTG

IUAUT

Unit AOR hold from USTG

IUTUA

BDiR setup 10 TGI

IBDn

38
15
27

BOIR hold from TGI

InBD

6-8

300
150
150
60
15

52
48

38
15
27
60

60
15
52
48

38
15
27
60

ns
ns
ICY

Unit selecl operation

ICY

ICY
ICY

Cylinder selecl
operation

---.--- ..

"--~

fttfEC

IlPD7261AIB

AC Characteristics (cont)
Umlts
72811

72811·18

72811·23

Symbol

Min

Max

Min

Max

Min

Max

Unl1

CYL. ADR selup 10 TGI

ICAT1

ICY

Panmeter

Tast
Condl1lons

SMD Interface (cont)

CYL. ADR hold from TGI

InCA

TGI pulse widlh

IT61

BDiR selup 10 TG2

IBDT2

ICY

BDIR hold from TG2

IT2BD

ICY

HEAD ADR selup TG2

IHAT2

HEAD ADR hold from TG2

IT2HA

TG2, pulse width

IT62

BDIR selup 10 TG3

IBDT3

24
36

ICY

24
36

ICY

Icy

BDIR hold from TG3

IT3BD

ICY

IT63

100

ICY

BT2, 3, 4, 6, 7, 8 seluplo
TG3

1m3

ICY

BT4, 6 hold from TG3

IT3BT1

ICY

BT2, 3, 7, 8 hold from TG3

IT3BT2

tCY

BDI Rdelay from SSTG

ISTBD

ICY

BDI Rhigh lime

IBOIR

IBTBD

.38

ICY

BT9 hold from BDiR

IBDBT

ICY

370

ICY

BT9 selup 10 BDiR

SSTG pulse widlh

ISST6

Index pulse width

IIDXH

SCT pulse widlh

ISCT

370

Head select operalion

ICY

TG3, pulse width

Cylinder seleci
operalion

RT2, FAULT CLR,
SERVO, DATA STB
conlrol timing

Sense unil slalus
liming

ICY

6-9

NEe

pPD7 261A/ B
Timing Waveforms - Host System Interface
AC Test Points (Except RIW eLK, eLK)
2.4 V
0.4SV

---v
--A.::

DMA Read Timing

V
A--

During Disk Read Operation

2.0/2.2 V Test Points 2.0/2.2V·
0 .::;:.8..!V_ _ _ _ _ _.....::0::::.8...:..V
'7216A/B

83-003478A

\'-_ _ _----'{

OREO--_tRRO'L

CLK Waveform

After Disk Read Operation

OREO
Read Timing
AO, iSS
83-003483A

Reset Waveform

00-07

---+------(1
83-003480A

Write Timing

Timing Waveforms-SMD Interface
RIWeLK Waveform

AO,CS,_ __
--..J

ttAW

DO-07
_

_
tWI=7I

L-

INT

Data Read/Write Timing

83-003481 A

RIW elK

DMA Write Timing
RIW Data

(Input)

-----'_{_twROL

WR _ _
\'----_

OREO

(Output)

83-003482A

6-10

RIW Data

NEe

pPD7261A/B

Timing Waveforms-SMD Interface (cont)
Read/Write Timing

Bit Bus Timing, Fault C/ear/Return·to·Zero

A/W CLK

BDIR

BTt

---t

tBoTa

TG3

(Read Gata)

rtBTT3~.+I.~-~

BT4,6~

BTO
(Write Gate)

T3BT1

1=
83-003491A

SYNC

Bit Bus Timing, Servo Offset/Data Strobe
83-OO3487A

BDIR

Unit Select Timing

---t tT3BoJ-----IBora

:=t=;:~:.~5

_______

BT2, 3, 7, 8

~-tB-TT-3:•.:'.::::::::---1T-3-BT-2:::::--::~j

---X_____

X-

V_81_id_ _ _ _ _

83-003492A

Bit Bus 9 Timing

83-003488A

BDIR

Seek Timing
BDIR=t
tBDT1

--'i-~tT1BD =soBT9
i+-------tsSTG'--------t

tCAT1

83-003493A

BTO·9
83-003489A

Head Select Timing
BDIR

roo
BTO-7

INO~-C

\ ;

~:_~J=_IT_UI[_'~:.~~
~

Index Waveform

Head ·Address

vall~

tlDXH

Sector Waveform

~
83-003490A

6-11

NEe

pPD7261A/B
Timing Waveforms-ST50e.Typelnterface
Normal Seek Operation

Data Read/Write Operation

Polling Mode

RIW ClK

RIW Data
(Input)

RIW Data
(Output)

Read/Write Operation

Non-Polling Mode

RIWClK

RGATE

WGATE

PCl, PCE
83-003497A

Buffered Seek Operation

SYNC
83-003496A

Polling Mode

R/W eLK Waveform

Non-Polling Mode

Index Waveform
DSD,I

IND~-C
DIR
tlDXF

SKC
83-003498A

6-12

ttiEC

pPD7261A/B

Timing Waveforms-ST508·Typelnterface
(cont)
Read/Write Sequence (Disk Command Issue)
hr...... Disk

Command

writes

....b

INT

11111

STR

Aeeull

Req. Read

Slatua

Parameter Another
wrltu
Disk

rrrtTrr

I SJ--!.!.II!..!.II:....I_":....UO_

I I -.

Iaoue

r.:-h

Command

:+~:J.-------.-111=
[If
' C
- ---I~

INT - - - - - ]

SRQ

~-fl------L-

- - - - - - f I , I - '_ _ _ _I_cLC_ECOrii_m-li"tI-_'OO_UO_)_ __

Sense Interrupt Status Request When Controller
Not Busy
INT

Roq.

-I
STR

SENSEINT
'STATUS

Command

INT

Roq.

10...

rr--,

STR

Hlgh.Level Commands
Specify
Allows user to select SMD or ST506-type mode data
block length, ending track number, end sector number,
gap length, track at which write current is reduced, ECC
or CRC function, choice of polynomial, and polling
mode enable.

Sense Interrupt Status
When a change of disk status occurs, the HOC will interrupt the host CPU. This command will reveal the cause
of interrupt, such as seek end, disk ready change, seek
error, or equipment check. The disk unit address is also
supplied.

Sense Unit Status
The host CPU specifies the drive numbers and the HOC
will return information such as write fault, ready, track
000, seek complete and drive selected, or for SMD units
fault, seek error, on cylinder, unit ready, AM found"write
protected, seek end, and unit selected.

_uR

-.
I I

Statuo

Detect Error

Sense Interrupt Status Request When Controller Busy
INT

STR

Roq. _

I I

HSRQ
COmmand

I
"""""""''----'---'---1'11
Illuo

INT

~r-11-____
I

CLCE

SENSE INT

StatuI COmmond STJmlS
100us
COmmand

1111

-~==~I~I

j~
SRa

RoouR

r.;';-;,

CB
CEH+CEL

INT

STR

I I -.

Roq. _

I.ouo

INT

Used after a read operation where ECC has been employed. The detect error command supplies the information needed to allow the host CPU to execute an error
correction routine. (Only allowed when an actual correctable error is detected by the HOC.)

Roq.

I JI----'-

_____-=~~J~

t~
r--

Recalibrate
Returns the disk drive heads to the home position or
track 000 position. Has four modes of operation: SMD,
normal, buffered, or nonpolling.

SAQ Mook (SRQM) 10 Set

6-13

NEe

pPD7261A/B
Seek

Write Data

Moves the disk drive heads to the specified cylinder. As
in recalibrate, seek has four modes of operation.

Data from the system memory, transferred by DMA;is
written onto the specified disk unit. As in the read com·
mand, data may be'written ontcisuccessive sectors and
tracks.

Format
This command is used to initialize the medium with the
desired format which includes various gap lengths,
data patterns, and CRC codes. Th is command is used in
conjunction with the specify command.

VerifylD
Used to verify the ID bytes with data from memory. Per·
forms the operation over a specified number of sectors.

ReadlD
Used to verify the position of the read/write heads.

Read Diagnostic
Used in SMDmode only, the command allows the pro·
grammerto read a sector of data even if the ID portion of
the sector is defective. Only one sector at a time can be
read.

Read Data

Auxiliary Command
Allows four additional functions to be executed: software reset, clear data buffer, mask interrupt request bit
(masks interrupts caused by change of status of drives),
and reset inte(rupt caused by command termination
(used when no further disk commands will be issued,
which would normally reset the interrupt).

Command Operation
There are three phases for most of the instructipns that
the pPD7261A/72618 can execute: command phase, execution phase, and result ph~e. During the command
phase the host CPU loads preset parameters into the
pPD7261A/72618 FIFO via the data bus and by successive write pulses to the part with Ao and CS true low.
Once the required parameter bytes are loaded the appropriate command is initiated by issuing a write pulse
with Ao high and CS low and the command code on the
data bus.

Verify Data

The pPD7261A/72618 is now in the execution phase.
can be verified by examining the status register bit
7 (the controller busy bit).The execution phase is ended
when a normal termination or ari abnormal termination
occurs. An' abnormal termination can occur due to a
read or write error, or a change of status in the addressed diSk drive. A normal termination occurs when
the command given is correctly completed. (This is indicated by bits in the status register.) The result phase is,
then entered. The host CPU may read various result pa·
rameters from the FIFO. These result parameters may
be iJseful in determining the cause of an interrupt, orthe
location of a sector causing a read error, for examp,le.

Makes a sector-by·sector comparison of data in the system memory by DMA transfer. As in read operation, mul·
tiplesectors and tracks may be verified with this
commmand.

The chart shown in table 2 illustrates the preset
parameters and result parameters that are associated
with each command. The abbreviations are defined at
the end of table 2.

Reads and transfers to the system memory the number
of sectors specified. The HDC can read multiple sectors
and multiple tracks with one instruction.

Scan
Compares a specified block of memory with specified
sectors on the disk. The 7261A/72618 continues until a
sector with matching data is found, until the sector
count reaches zero, or the end of the cylinder is
reached.

6-14

Th,i~

NEe

pPD7261A/B

Preset Parameters and Result Status Byte

Table 2.
Disk
Command

Command
Code

Detect error

0100X

Recalibrate

0101[8]

Seek

0110[8]

Preset Parameters' Result Status
1st

2nd

3rd

4th

5th

EADH

EADL

EPTI

EPT2

EPT3

SCNT

DPAT

GPLI

[GPL3]

6th

7th

8th

1ST'
PCNH

PCNL

1ST'
Format

0111(S)

Verify ID

1000(S)
1001(S)

Read ID
(Read diagnostic)

1010X

PHN

(PSN)

EST

SCNT

PHN

(PSN)

EST

SCNT

PHN

(PSN)

EST

SCNT

PHN

PSN

SCNT
SCNT

EST
1011X

Read data

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

SCNT
SCNT

Check

1100X

Scan

I100X

Verify data

1110X

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

Write data

l111X

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

Sense interrupt
status

0001X

1ST

Specify

0010X

MODE

DTLH

DTLL

ETN

ESN

GPL2

(MGPL1)
[RWCH]

[RWCL]

Sense unit status

0011X

SCNT
SCNT
SCNT

UST
Note:

(): These are omitted for soft-sector disks_
I]: These are omitted for hard-sector disks.
*: 1ST available as a result byte only when in nonpolling mode.
B: Indicates buffered mode when set.
s: Indicates Skewed mode (SMD only) when set.
X: Indicates don't care.

Mnemonic Definitions
EADH

Error address, high byte

EADL

Error address, low byte

EPT1

Error pattern, byte one

EPT2

Error pattern, byte two

EPT3

Error pattern, byte three

PCNH

Physical cylinder number, high byte

Mnemonic Definitions (cant)
Physical cylinder number, low byte
PCNL
PHN

Physical head number

PSN

Physical sector number

SCNT

Sector count

DPAT

Data pattern

GPL1

Gap length one

GPL3

Gap length three

EST

Error status byte

FLAG

Flag byte

LCNH

Logical cylinder number, high byte
6-15

t-IEC

pPD7261A/B
Mnemonic Definitions (cant)

Table 3.

Status Register Bits (cant)

LCNL

Logical cylinder number,low byte

LHN

Logical head number

No.

LSN

Logical sector number

1ST

Interrupt status byte

SRO
(Sense interrupt
status request)

When a seek end, an equipment
check condition, or a ready signal
state change Is detected, this btl is set
requesting a sense Interrupt status
command be issued to take the detailed information. This btl is cleared
by an Issue of that command or by a
reset signal.

RRO
(Reset request)

Set when controller has lost control of
the format controller (missing address
mark, for example). An auxlilary RST
command Dr RESET Signal will clear
thlsbH.

IER
(ID error)

Set when a CRC error is detected in
the ID field. An auxiliary RST Dr another disk command will reset this bit.

NCI
(Not coincident)

Set If the controller cannot find a Sector on the cylinder which meets the
comparison condHion during the execution of a scan command. This bit is
also set ndata from the disk does not
coincide with the data from the system during a verify IDor a verify data
command. This bit is cleared by adisk
command or a reset signal.

DRO
(Data request)

During execution ofwrHe ID, verify ID,
scan, verify data, Dr a write data command, this bit Is set to request that
data be written into the data buffer.
During execution of read ID, read diagnostic, Dr read data command, this
bH is set to request that data be read
from the data buffer.

MODE

Mode

DTLH

Data length, high byte

DTLL

Data length, low byte

ETN

Ending track number

ESN

Ending sector number

GPL2

Gap length two

RWCL

Write current cylinder, low byte

RWCH

Write current cylinder, high byte

UST

Unit status byte

MGPL1 Modified gap length 1

Pin
NI.

Status Register
This register is a read only register and may be read by
asserting RD and CS with Ao high. The status register
may be read at any time. It is used to determine control·
ler status and partial result status. See table 3.
Table 3.

Status Register Bits
Pin

No.

Name

Function

CB
(Controller busy)

Set by adisk command issue. Cleared
when the command is completed.
(This bit is also set by an external reo
set signal or an RST command, but
will be cleared at the completion of the
reset function.) When this bit is set, a
new disk command will not be ac·
cepted.

D6, D5

CEH, CEl
(Command end)

CEH = 0 and CEl= 0
A disk command is in process, or no
disk command is issued after the last
reset signal or the last ClCE auxiliary
command. Both the CEH and CEl bits
are cleared by a disk command, a
ClCE auxiliary command, or a reset
signal.
CEH=OandCEl=1
Abnormal termination of a disk com·
mand. Execution of a disk command
was started, but was not successfully
completed.
CEH=1 and CEl=O
Normal termination of a disk com·
mand. The execution of a disk
command was completed and properly executed.
CEH =1 and CEl = 1
Invalid command issue.

6-16

Function

NEe

J,lPD7261A/B

Error Status Byte

Interrupt Status Byte

This byte is available to the host at the termination of a
read, write, or data verification command and provides
additional error information to the host CPU. If the status register indicates a normal command termination, it
can be assumed that the command was executed without error and it is not necessary to read this byte. When
it is necessary to determine the cause of an error this
byte may be read by issuing an RD pulse with CS and AO
low. The remaining result bytes associated with a particular command may be read by issuing additional RD
pulses. Data transfer from or to the FIFO is asynchronous and may occur at rates up to 2.5 Mbytes per second.
See table 4.

This byte is made available to the host CPU by executing the Sense Interrupt Status command. This command should be issued only when the IlPD7261A/7261B
requests it, as indicated by bit D4 of the status register.
This byte reveals changes in disk drive status that have
occurred. See table 5.

Table 4.

Error Status Bits

Table 5.

Interrupt Status Bits
Pin
Name

No.

SEN
(Seek end)

A seek end or seek complete signal
has been returned after a seek or a recalibrate command was issued.

RC
(Ready change)

The state of the ready signal from the
drives has changed. The state itself is
indicated by the NR bit.

SER
(Seek error)

Seek error has been detected on seek
end.

mc
(Equipment check)

Identical to bit 4 of the error status
byte.

NR
(Not ready)

Identical to bit 3 of the error status
byte.

UA2-UAO
(Unit address)

The unit address of the drive which
caused an interrupt request on any of
the above conditions.

Pin
No.

Name

ENC
(End of cylinder)

Function

Set when the controller tries to access
a sector beyond the final sector of a
cylinder.
Cleared by a disk command or an auxiliary RSTcommand.

OVR
(Overrun)

When set, indicates that the FIFO became full during a read operation, or
empty during a write operation.

OER
(Data error)

A CRC or an ECC error was detected in
the data field.

EQC
(Equipment check)

A fault signal from the drive has been
detected or a track 0 signal has not
been returned within a certain time interval after the recalibrate command
was issued.

NR
(Not ready)

The drive is not in ready state.

NO
(No data)

The sector specified by 10 parameters
was not found on the track.

NWR
(Not writable)

Set if write protect signal is detected
when the controller tries to write on
the disk. It is cleared by a disk command or by an auxiliary RST command.

MAM
(Missing address mark)

This bit is set if during execution of
read data, check, scan, or verify data
commands, no address mark was
found in the data field or if during execution of a read 10 or verify 10 command, no address mark was detected
in the 10 field.

Function

04
03
02-00

Drive Interface
The IlPD7261A/7261B has been designed to implement
two of the more popular types of interfaces: the SMD
(Storage Module Drive) and the floppy-like Winchester
drive which has come to be known as the ST506 interface. The desired interface mode is selected by the
Specify command.

ST506·Type Interface
In the ST506 mode the IlPD7261A/7261B performs MFM
encoding and decoding at data rates to 6 MHz and provides all necessary drive interface signals. Included internally is circuitry for address mark detection, sync
area recognition, serial-to-parallel-to-serial conversion,
an 8-byte FIFO for data buffering, and circuitry for logical addressing of the drives. External circuitry required
consists of control signal buffering, a delay network for
precompensation, a phase-lock loop, a write clock oscillator and a differential transceiver for drive data. The
floppy-like interface can be implemented with as few as
7 IC's using NEC's hard-disk interface chip, the
IlPD9306A, or with 12 to 14 SSIICs. See figure 1.

6-17

NEe

JlPD7261A/B
Figure 1.

/JPD7261A17261B 5T506-Type Interlace

Figure 2_

/JPD7261A172618 5MD Interlace

SYNC~
R/WCLK 3
~-

+ READ DATA

' ' ' - - - READ DATA

R!WOATA
I""c-~~

+ WRITE DATA

V6'--~~

- WRITE DATA

BTO

r 8 - r - i - W RITE CLOCK
r-SERVQCLOCK

MPX

i-R EADCLOCK

!---9

r-W RITE DATA
r-R EADDATA

r- BITO

BT1 39

INDEX

and r- 'N OEX

SCT 35

I--S ECTOR

READY f-"3~O~~~~~~-~-READY

T01 29

I--TAGl

INDEX f-"3=-S~~~~~~--~-INDEX

TG2 30

r- TAG2

~FAULT

TG3 31

r- TAG3

eso

~DRIVESELECTED

WFLT 29

TRKO 31

TRACK 000

SKC

r3~2~~~~~74CCL-:CS1-<4 i>---$--SEEK COMPLETE

Rwe

23~REDUCEDWRITE

SSrG 33

r- S RSELECTTAG

USTG 34

_ r - u NIT SELECT TAG

BT2 28

BIT2

CURRENT

OIR 21

WGATE
HSO
HSl
HS2
STEP

DIRECTION IN

WRITE GATE

HEAD SELECT 0

BT3 27

8T5 25
816 24

HEAD SELECT 1

24
7406

HEAD SELECT 2

OSO

BT7 23
BT8 22

STEP

OSl

DRIVESEL 1

DRIVESEl2

~DRIVESEL3

i--

BT4 26

BT9 21
BOIR 32

r-B IT3
r- B114

i-8~Bjt

Latch

i--

7407

SMD Interface
In the SMD mode the /JPD7261A/7261B will support data
rates to 10 MHz/15MHz in the NRZ format. All control
functions necessary for an SMD interface are implemented on-chip with de-multiplexing of 8 data lines performed externally by a single 8-bit latch. A small amount
of logic is required to multiplex the data and clock lines,
and differential drivers and receivers are required to im·
plement the actual interface. Depending on individual
logic design and the number of drives used, the SMD interface may be implemented with as few as 12 les. See
figure 2.
Not8:
ClK (pin 37) frequency must be a minimum of 1.1 x NRZ data rate,

Internal Architecture
The /JPD7261A/7261B can be divided into three major internal logic blocks: command processor; format controller; microprocessor interface.

Command Processor
The command processor is an 8-bit microprocessor
with its own instruction set, program ROM, scratch pad
RAM, ALU, and 110 interface. Its major functions are:

I--B ITS

i--

r-B IT6

i-i--

r- B1T7
r-B ITS

~i--_I--B IT9

OE t- FAULTI(SR2)I(OT2)

EEKERRORI

~(8R3)I(OT3)

DRiVESE[4
lhLS138

6-18

I--BITl

- 'ONCYLINOERI
(SR4)I(DT4)
-u NIT READY/
(SR5)I(OT5)
RX
- (5R6)I(OT6)
- 'WRITE PROTECTEDI
(SR7)I(DT7)
- S EEKEND
UNIT SELECTED

cr:

1.1 k±10%"---

NIT SEL 0

~ NIT SEL 1
NIT SEl2

D To decode the commands from the host microcomputer that are received through the 8-bit data bus
D To execute seek and recalibrate commands
D To interface to the drives and read the drive status
lines
D To load the format controller with the appropriate
microcode, enabling it to execute the various readl
write data commands.
The command processor microprocessor is idle until it
receives the command from the host microcomputer. It
then reads the parameter bytes from the FIFO, and
loads them into its RAM. The command byte is decoded
and, depending on its opcode, the appropriate subroutine from the 2.6K internal ROM is selected and executed. Some of these commands are executed by the
command processor without involvement of the format

NEe

tlPD7261A/B

controller. When data transfers to and from the disk are
made, the command processor loads the appropriate
microcode into the format controller, then relinquishes
control. When the data transfer is complete, the command processor again takes control. One other important function that the command processor performs is
managing the interface to the disk drives. The command processor contains an I/O port structure similar
to many single-chip microcomputers in that the ports
may be configured as input or output pins. Depending
on the mode of operation selected by the Specify command; the command processor will use the bidirectional I/O lines for different functions~

Figure 3. Disk Command Byte

Command Register

D Serial-to-parallel and parallel-to-serial data
conversion
D CRC and ECC generation and checking
D M FM data decoding and encoding
D Write precompensation
D Address mark detection and generation
D ID field search in soft-sector format
D DMA data transfer control during read/write
operations.

Thisregisfer is a write only register. It is selected when
theAo input is high and the CS input is low. There are
two kinds of commands: disk commands and auxiliary
commands. Each command format is shown in figure 3.
An auxiliary command is accepted at anytime and is
immediately executed, while a disk command is ignored if the on-Chip processor is busy processing, anotherdisk command. A valid di~k command causes the
processor to begin execution using the parameters previously loaded into the data buffer. Disk commands and
the parameters needed are described in the Microprocessor Interface section.

'Command Codes
CC4-CCO

(Auxiliary Command)

Sense inC status (Note 1)
Specify (Note 1)

Sense unit status

Detect error (Note 1)

0
0

Seek

[SI

Format

[SI

Verify ID

[SI

Read ID

Read diagnostic

Read data

Check

Scan

X ' Verify data

0
0

Recalibrate

[Bl
0
0

[BI

Write data

CC4

CC3

CC2

Command Code

CCl

CCO

UA2

UAl

UAO

Unit Address (UA)

Format Controller
The format controller is built with logic that enables it to
execute instructions at very high speed: one instruction
per single clock cycle. The major functions it performs
are:

The major blocks in the format controller are the sequencer and the serial/parallel data handler. The sequencer consists of a writable control store (32 words
by 16 bits), a program counter, branch logic, and the parameter register. The serial/parallel logic consists of a
parallel-to-serial converter for disk write operations, a
serial-to-parallel converter for disk read operations, precompensation logic for writing MFM data, comparator
logic that locates sync fields, address marks, and ID
fields. There is also comparator logic that is used during
Verify Data commands. See figure 4..
Figure 4. Block Diagram of the Format Controller
write Data
Precomp., Early
Precomp. Late

RlWCIOCk-----f----+---j
ReadData .

Data
Buffer

RAM

Note:
(1) The UA field is 000,
'[B] Indicates buffered mode when'set.
[S] Indicates skewed mode when set.

6-19

fttIEC

,pPD7261AJ'B
Micropr'C)Cessor Interface
Read/Write Control. The Internal registers are selected

as shown In truth table 6.
Tab/e6.

HDC- memory: Read 10, Read Diagnostic,
Read Data

l!i

Data buffer register (Note 1)

0
0
0

Selection

Status register

Command register
Don't care

Don't care

Inhibited

Note:
(1) Preset parameters and result status information are written and
read from the result status register in the HOC through this data
buffer register.

Intenupt The Interrupt request line. is activated or Inac·
tivated according to the following equation:
INT

=CEH + CEl + SRQ • SRQM

This means that If either of the command end bits Is set
or If the sense Interrup~ status request bit Is set (and the
.SRQM mask Is not set), then an Interrupt will be gener·
ated. The command end bits, CEH and CEl, are set by
.
,
command termination.
The SRQ bit Is set when an equipment check condition
or a state change ofthe ready signal from the disk drives
Is detected. It Is also set when a seek operation Is completed. Under these condl~lons the INT line Is activated
unless the SRQM mask Is set.
Both of the CEH and CEl bits are cleared by a disk command, but both bits may be cleared before the next disk
command by Issuing a ClCE auxiliary command.
the Interrupt caused by the SRQ bit Indicates that a
sense Interrupt status command should be Issued by
the host microprocessor so that It can determine the exact cause of the Interrupt. However, the ",PD7261A/
7261B may be processing a disk command when the
Interrupt occurs. Since It Is not possible to Issue a disk
command while the ",PD7261A/7261B Is busy, an HSRQ
auxiliary command can be Issued to set the SRQM
(sense Interrupt request mask}and mask the Interrupt.
The SRQM Is reset upon completion of the disk command In progress.

DMA Control. When true, the DREQ pin and the DRQ
(data request) blf of the status register Indicate a request for data transfer between the disk controller and
external memory. These are activated during execution
of the following disk comrnands:
6-20

HOC- memory: Format, Verify 10, Scan,
Verify Data, Write Data

Data being read from a disk or external memory Is temporarily stored In the data buffer (8 bytes maximum),
and Is transferred to external memory or a disk, respectively.
Data transfers are terminated externally by a reset signal or by a read or a write data operation coinciding with
an active terminal count (Te) signal. They are also terminated Internally when an abnormal condition Is detected or all the data specified by the sector count
parameter (SCNT) has been transferred.
Data transfers are accomplished by RD or WR signals to
the ",PD7261A/7261B when DREQ Is active. During read
operatlons,DREQgoes active when the FIFO contains
three or more bytes. If the FI FO contains three bytes and
an RD pulse Is issued, DREQ goes low within tRRQ1.
DREQ will stay active on the final sector until the final
byte Is extracted. In this case, DREQ goes low within
tRRQ2. During write operations DREQ is asserted as
soon as a Write Data command is accepted. DREQ remains high until the FIFO contains six bytes, at which
time It goes low within twAI. DREQ corresponds to FI FO
almost-full and FIFO almost-empty as implemented In
the ",PD7261A/7261B. This has been done so that a fast
DMA controller may actually overrun the FIFO by one or
two bytes without harm.
"

Commands
Recalibrate

I ~B

t--I.~.- - - - - - - I

The read/write heads of the specified drive ate retracted
to the cylinderO position. 1ST is avallable.as a result byte
only If polling mode is disabled. See Specify.
Hard-Sector. An RTZ (Return to Zero) signal is asserted
on the blt-6 line with the TAG-3 bit being set. Then the
CEH bit of the status register Is set Indicating a normal
termination of the command.
After this command is given, the HOC checks the seek
end, unit ready, and fault lines onhe drive continually
until an active signal Is detected on these lines. Then
the SRQ bit of the status register is set indicating that a .
sense Interrupt status command should be performed.
Each bit of the 1ST (interrupt status) byte is set accordIng to the result, In anticipation of the sense interrupt
status command.

NEe
Soft·Sector. There are four different ways to implement
the Recalibrate command when the ST506 interface
mode has been specified. Both polling and nonpolling
modes of operation are provided, with both normal or
buffered Recalibrate commands available in either
mode.
Normal Mode with Polling. The CEH bit of EST is set to 1
immediately after the Recalibrate command is issued (a
Recalibrate command may now be issued to another
drive). The HOC now begins generating step pulses at
the specified rate. The PCN for the drive is cleared and
the TRKO signal is checked while stepping pulses are
sent to one or more drives. When TRKO is asserted, the
SEN (seek end) bit of the 1ST (interrupt status) byte is set
and the SRO bit of the status register is set. This causes
an interrupt and requests that a sense interrupt status
command be issued. If 1023 pulses have been sent and
TRKO is not asserted, then the SRO bit is again set, but
with the SER (seek error) and EOC (equipment check)
bits of the 1ST byte set. The ready signal of each drive is
checked before each step pulse is sent, and the Recalibrate command is terminated if the drive enters a notready state, whereby the N R bit of the 1ST byte is set to 1.
Normal Mode with Polling Disabled. Operation is similar to that in "Normal Mode with Polling", but the CEH
and CEl bits of the status register are not set until
either the SEN (seek end) or the SER (seek error) condition occurs. The SRO bit is not set when polling is disabled, and the 1ST byte is now available as a result byte
when the Recalibrate command is terminated (see "Preset Parameters and Result Status Bytes"). It is not possible to overlap Recalibrate operations in this mode.
Buffered Mode with Polling. This mode operates in a
manner similar to that described as "Normal Mode with
Polling", but with the following differences:
(1) 1023 step pulses are sent at a high rate of speed (approximately 50 IJs between pulses)
(2) After the required number of pulses are sent, the
CEH bit is set, and then additional Recalibrate or Seek
commands will be accepted for other drives
(3) The SRO bit is set when the drive asserts SKC,
which causes the SEN bit of the 1ST byte to be set
(4) If SEN is not set within the time it takes to send 1023
"normal" pulses (i.e., when in normal stepping mode),
then SER and EOC of the 1ST byte are set.
Buffered Mode with Polling Disabled. 1023 stepping
pulses are immediately sent after the Recalibrate command is issued. CEH and/or CEl is set when SEN or
SER occurs. SEN is set when TRKO from the addressed
drive is asserted. SER is set if TRKO is not asserted
within the time required to send 1023 "normal" pulses.
The Recalibrate command will be terminated abnormally if a not-ready condition occurs prior to SEN being

JlPD7261A/B
set. The SRO bit of the status register is not set. The 1ST
byte (interrupt status) is available as a result byte when
either CEH or CEl is set.
Seek

I ~10B
peNH
PCNL

=
=

PCNH

PCNL

1ST·
Physical Cylinder Number, High Byte
Physical Cylinder Number, Low Byte

The read/write heads of the specified drive are moved to
the cylinder specified by PCNH and PCNL.IST is available as a result byte only if polling mode is disabled. See
Specify.
Hard·Sector. The contents of PCNH and PCNl are asserted on the BITO through BIT9 output lines of the SMO
interface with the TAG1 control line being set. (The most
significant six bits of PCNH are not used.) The CEH bit
of the status register is then set, and the command is
terminated normally.
The HOC then checks. the seek end, unit ready and fault
lines of the drive continually until an active signal is detected on these lines. The SRO bit of the status register
is then set requesting that a Sense Interrupt Status
command be performed. Each bit of the 1ST (interrupt
status) byte is set appropriately in anticipation of the
Sense Interrupt Status command.
Soft·Sector (Normal Stepping, Polling Enabled). In this
mode, the CEH bit of the status register is set to 1 as
soon as the Seek command is issued. This allows a
Seek or Recalibrate command to be issued to another
drive. The HOC now sends stepping pulses at the specified rate and monitors the ready signal. Should the drive
enter a not-ready state, the SER bit of the 1ST byte is set
and the SRO bit of the status register is set, causing an
interrupt and requesting a Sense Interrupt Status command. When the drive asserts the seek complete (SKC)
signal, the SEN bit of the 1ST byte is set and the SRO bit
of the status register is set, again requesting service.
Soft·Sector (Normal Stepping, Polling Disabled). Stepping pulses to the drive begin as soon as the Seek command is accepted. The ready signal is checked prior to
each step pulse. If the drive enters a not-ready state the
seek command is terminated abnormally (CEl 1), and
SER of the 1ST byte is set. If the seek operation is successful, the seek command will be terminated normally
(CEH = 1) when the drive asserts SKC (seek complete).
The SEN (seek end) bit of the 1ST byte is set and the 1ST
(interrupt status) byte is available as a result byte. The
Sense Interrupt Status command is not allowed (SRO is
not set), nor can seek operations be overlapped in this
mode.

6-21

t-.'EC

pPD7261A/B
Soft·Sector (Buffered Stepping, Polling Enabled). As
soon as the Seek command is accepted by the HDC,
high-speed stepping pulses are generated. As soon as
the required number of pulses are sent, CEH is set to 1,
indicating a normal termination. Another Seek command in the same mode may now be issued. The drive is
now controlling its own head positioner and asserts
SKC when the target cyclinder is reached.) If the drive
has not asserted SKC (seek complete) within the time it
takes to send the required number of pulses in normal
stepping mode, or if the drive enters a not-ready state,
then the SER bit of the 1ST byte and the SRQ bit of the
status register are set. Otherwise, the SEN bit of the 1ST
byte is set, along with SRQ of the status register.
Soft·Sector (Buffered Stepping, Polling Disabled). In
this mode, the appropriate number of high-speed stepping pulses are sent as soon as the Seek command is
issued. If the drive enters a not-ready state, or if SKC
(seek complete) is not asserted within the time it takes
to send the required number of pulses in normal stepping mode, then the Seek command is terminated normally (generating an interrupt). The 1ST byte is available
as a result byte and the appropriate bit is set; i.e., SER
and EQC or NR (not ready). If the seek operation is successful, the Seek command is terminated normally
(CEH = 1) and the SEN bit of the 1ST byte is set. The 1ST
byte is available as a result byte. The Sense Interrupt
Status command is not allowed (SRQ is not set), nor can
seek operations be overlapped in this mode.

EST

PHN

(PSN)

EST

seNT

DPAT

GPl1

(GPL3)

= Physical Head Number

=
=
=
=
=

Physical Sector Number
$ector Count
Data Pattern
Gap Length 1
Gap Length 3

= Error Status

This command is used to write the desired ID and data
format on the disk.
(1) When using hard-sector drives, this command will

begin format-writing at the sector specified by PHN and
PSN, which are loaded during command phase.
When soft-sector drives are specified, this command
will begin format-writing at the sector immediately following the index pulse on the track specified by PHN.
In either case, data transmitted from the local memory
by DMA operation is written into the ID field, and the
data field is filled with the data constant specified by
DPAT until DTL (data length) is zero. DTL is established
during the specify command with DTLH and DTTL. The
sector count, SCNT, is decremented by one at the end of
the Format operation on each sector. The following
6-22

The format operation produces the various gaps with
length as specified by GPL1, GPL2 (See Specify), and
GPL3 (For soft-sector only.)
Note:
GPL3 may not exceed decimal value of 44.

(2) The above operation is repeated until SCNT is equal
to zero. The execution of the command is terminated
normally, when the content of SCNT is equal to zero and
the second index pulse has occurred.
(3) When using a hard-sector drive, it is possible to write
the ID field displaced from the normal position by 64
bytes by setting the skew bit of the command byte
«S) = 1). This is useful when defective media prevent
writing in the normal area of the sector.
(4) Items 4, 5, and 8 of the Read Data and item 4 of the
Write Data command are identical for this command.
Refer to these items (which appear later in this section)
for remaining format operation details.

Verify ID

I I

PHN

1000$

PHN
PSN

(PSN)

SCNT

-------------l

I-EST--:"'SC-N';"'T

= Physical Head Number
= Physical Sector Number

SeNT = Sector Count
EST
= Error Status

Format

PHN
PSN
SCNT
DPAT
GPL1
GPL3

bytes are required by the HDC for each sector: (FLAG),
LCNH, LCNL, LHN, and LSN. FLAG is omitted on softsector drives. These bytes are transferred by DMA.

ID bytes of specified sectors are read and compared
with the data that are accessed from local memory via
DMA control. The first sector that is verified is specified
by PHN and PSN when a hard-sector disk is used. For
soit-sector disks, only PHN is given and the Verify ID
command begins comparisons with the first physical
sector on the track.
Byte comparisons continue as long as successful or
until the sector count is zero or a CRC error is found.
When using a hard-sector drive, it is possible to have the
HDC verify a skewed ID field by setting the skew bit of
the command byte. Refer to the Format section, given
earlier, for details.

ReadlD

I 1~S I~_::_N__::_:_T_SC_N_T_ _ _ _ _ _ _ _ _ _~
PHN
PSN
SCNT

EST

= Physical Head Number

= Physical Sector Number

= Sector Count
= Error Status

t-IEC

pPD7261A/B

ID bytes of specified sectors are read and transferred to
local memory by DMA.
Hard-sector disks: Beginning with the sector specified
by PHN and PSN, the ID bytes of each sector (FLAG,
LCNH, LCNL, LHN, LSN) are read until an error is
found or the SCNT has reached zero.
It is also possible to perform the above operation with
skewed ID fields by setti ng the skew bit of the command
byte. This will allow reading ID fields that have been
shifted by 64 bytes by the Skewed Format command.
Soft·sector disks: This command will begin checking ID
fields immediately following the index pulse and will
continue until one valid ID field is read, or until the second index pulse is detected or SCNT = 0, whichever
occurs first. Four bytes per soft sector are read: LCNH,
LCNL, LHN, and LSN.

Read Diagnostic

11moxll-:..::::..:N_P:..;S;.:.N_ _ _ _ _ _ _ _ _ _ _ _- ;
PHN
PSN
EST

= Physical Head Number
= Error Status

= Physical_Number

This command is implemented only for hard-sector
disks. The desired physical sector is specified, and the
data field will be read even if the ID bytes of that sector
contain a CRCerror. Only one sector at a time may be
read by this command.

Read Data
PHN

(FLAG). LCNH

LCNL

LHN

LSN

SCNT

EST

PHN

LCNH

LCNL

LHN

LSN

(FLAG)

(3) The HDC abnormally terminates the execution of this
command if SCNT is not equal to zero when the HDC
reads out the data from the last sector (LSN ESN and
LHN ETN). The ENC (end of cylinder) bit of EST (error
status) is set to one in this situation.

(4) The HDC will terminate this command if a fault signal
is detected while reading data. The HDC will set the
EQC (equipment check) of the EST (error status) byte
when this occurs.
(5) The HDC will terminate this command abnormally if
the ready signal from the drive is not active or becomes
not active while a Read Data command is being performed. The NR (not ready) bit of the EST (error status)
register will be set to one in this case.
(6) The HDC will end this command abnormally if it cannot find an AM (address mark) (soft-sector mode) or a
SYNC byte (hard-sector mode) of the ID field before four
index pulses occur. Under these conditions, the RRQ
(reset request) bit of the STR (status register) will be s~t.
In order to perform further disk commands the HDC will
have to be reset because the format controller is hung
up looking for an AM or SYNC byte.

(7) ECC mode: If the H DC detects an EC? error dur~ng a
read operation, it will execute the following operations:
First, the HDC decides whether or not the error is correctable by checking the syndrome of the error pattern.
If the error is correctable, the HDC terminates the command in the normal mode after setting the DER (data
error) bit of EST register to one. The host system can Input the error address and the error pattern information
by issuing the Detect Error command. If it is not a c~r
rectable error, the HDC will terminate the command In
the abnormal mode after setting the DER bit of the EST
register to one.

SCNT

LHN = Loglcol Hood Number
LSN
- IJ>8Ie8ISoctor Number
SCNT - sector Number
EST - Error StatuI

This command is used to read and transfer data via
DMA from the disk to the local memory.
(1) The HDC reads data from the specified sector which
is determined by the following preset parameters: FLAG
(for hard-sector only), LCNH, LCNL, LHN, and LSN. The
drive is selected by UA (unit address) in the command
byte. The HDC then transfers the read data to the local
memory via DMA operation.
(2) After reading each sector, the HDC updates the
SCNT and LSN to point to the next sector, and repeats
the above described operation until SCNT is equal to
zero. During the above read operations, if LSN is equal
to ESN the HDC updates LSN, and continues the read
operati~ns after relocating the head (track) specified by
LHN.

CRC mode: If the HDC detects a CRC error on a sector
during the read operation, the HDC will terminate the
command in the abnormal mode after setting the DER
bit of the EST register to one.
(8) If the HDC detects an overrun condition during a
Read Data operation, the OVR (overrun) bit of the EST
register is set. (An overrun condition occurs when the internal data FIFO is full, another data byte has been received from the disk drive, and a DMA service does not
occur.) The command is then terminated in the abnormal mode.
(9) If the HDC cannot find the desired sector within.the
occurrence of three index pulses, the ND (no data) bit of
the EST register is set to one and the command is terminated in the abnormal mode.
(10) If TC (terminal count) occurs during a Read Data
command the DMA transfers to the local memory will
stop. However, the HDC does continue the read operation until the end of the sector, if SCNT 1.

6-23

tt.'EC

pPD7261A/B
If SCNT is 2 or more, OMA transfers restart when SCNT
is updated to tile next sector, and will continue until
SCNT is zero.
(11) If the Read Data command has been successfully
completed, the result status will be set indicating such,
and the result status bytes will be updated according to
the number of sectors that have been read. The logical
disk parameters-LSN, LHN, and LCN-are incremented as follows:
LSN is incremented at the end of each sector until the
value of ESN is reached. LSN is then set to 0 and LH N is
incremented. If LHN reaches the value of ETN, then
LHN is cleared and LCN is incremented.
In other words, if a Read or Write operation is terminated normally, the various parameters will point to the
n~xt logical sector.
If the command is terminated in the abnormal mode, the
result status bytes will indicate on which sector, cylinder, and head the error occurred.
(12) If the HOC cannot detect the address mark (softsector) or SYNC bytes (hard-sector) immediately following the VFO sync in the data field, the HOC will set the
MAM (missing address mark) bit of the EST register to
one, and will terminate the command in the abnormal
mode.

Check
PHN

(FLAG)

E&T

PHN

LCNH

LCNL

LHN

LSN

seNT

.(FLAG)

LCNH

LCNL

LHN

LSN

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

seNT

E&T

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

seNT

=1'hyIIca1 Head Number

r~ ~ ~"rc!;.~':::;:~ ~~~~

LCNL = LojjIcaI cylinder Number, Low Byl8
LHN =!DG!ca1 H.ad Number
LSN • Logical_Number
SCNT • Sector Number
E&T • Error SIal..

(1) In executing the Scan command, the HOC reads the
data from the sector specified by the preset parameters
of the command phase. The HOC then compares this
data with the data transmitted from the local memory.
(The purpose of this command is to locate a sector that
contains the same data as the local memory.)
This command will terminate successfully if the data
from the disk and the data from the local memory are
the same. If they are not, the HOC updates SCNT and
LSN, and executes the abovementioned operation
again.
If the HOC cannot locate a sector that satisfies the scan
conditions, the NCI bit of the STR will be set. The HOC
tries to compare data until the end of the cylinder has
been reached, or until SCNT is zero.
(2) If the value of the LSN (logical sector number) is
equal to that of ESN (ending sector number) after updating LSN, the HOC updates the contents of LHN (increas'
ing by 1) and that of LSN (LSN 0), and repeats the
operation described in item 1 after selecting the next
head.
(3) After comparing the data transferred from the host
CPU with the data in the speCified sectors, the result
bytes (FLAG, which is only for hard-sector disks, LCNH,
LCNL, LHN, and LSN) will be set equal to the sector location that satisfies the Scan command.

seNT

This command is used to confirm that the data previously written to the medium by the Write Data command contains the correct CRC or ECC.
(1) The HOC reads the data in the sector specifie,d by
FLAG (hard-sector only), LCNH, LCNL, LHN, and LSN.
The Check command differs from the Read Data command in that no OMAtransfers occur.
With the exception of the ECC mode, the Check command is the same as the Read Data command. Please
refer to items 2, 3, 4, 5, 6, 7, 8, 11, and 12 of Read Data
command for details.
(2) If in the ECC mode, the HOC detects only ECC errors
and does not execute any error correction operation
even if the ECC errors are correctable. No data transfers
h~ve been ma,de,and there is no data to correct.

6-24

Scan

(4) The descriptions in 4, 5, 6, 8, and 9 of Read Data command, and items 3 and 4 of Verify Data command are
identical for this command. Refer to these descriptions
for additional details.

Verify Data

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

seNT

E&T

PHN

(FLAG)

LONH

LCNL

LHN

LSN

• PhyaIcaI Hoed Number

r~ ~ ~~~.:.~~=g;:Z

LCNL .. ~lcal cylinder Number, LoW Byla
LHN "!DII!ca1 ""ad Number'
LSN .. Logical_Number
SCNT 1:1 SeCtor Number
EST = Error StatUI

This command is used to verify data on the disk.

seNT

tt{EC

J,lPD7261A/B

(1) The HOC reads the data from the specified sector,
and compares the data transmitted from the local memory via OMA with the data from the disk.

Write Data
PHN

(FLAG)

LCNH

LCNL

LHN

LSN

SCNT

The sector is specified by FLAG (hard-sector only),
LCNH, LCNL, LHN, and LSN, and the drive is selected
by UA. If the data transmitted from the local memory is
the same as that read from the sector, the HOC updates
the contents of LSN and SCNT, and continues the
abovementioned operation. After updating SCNT, if the
value of SCNT is equal to zero, the HOC ends the execution of the command in the normal mode. If the value of
LSN is equal to that of ESN after updating LSN, the HOC
updates the contents of LHN and LSN, and the HOC
continues the verify data operation after selecting the
head (track) specified by LHN.

EST

PHN

(FLAG)

LCNH

LCNL

LHN

LSN

If the data transmitted from the local memory is not the
same as that read from the sector, the HOC ends the execution of the command in the abnormal mode after
setting the NCI (not coincident) bit of STR to one.
(2) If after verifying the data on the last sector, the content~ of SCNT are not equal to zero, the HOC terminates
execution of the command abnormally after setting the
ENC (end of cylinder) bit of the EST register to one.
(3) After verifying the data read from a sector, the HOC
checks the CRC bytes (CRC mode) or the ECC bytes
(ECCmode).
If the HOC detects a CRC or an ECC error on a sector,
the HOC terminates execution of the command abnormally after setting the OER bit of the EST register to a
one.
(4) After detecting an active TC signal (TC = 0), the HOC
executes the above operation by comparing the read
data from the disk drive with the data 00 instead of the
data from the main system until the end of the sector.
In the case of SCNT greater than one, when SCNT is updated, OMA transfers restart and disk data is compared
against host data until SCNT is zero.
(5) After verification of the data on all the sectors, FLAG
(hard-sector only), LCNH, LCNL, LHN, and LSN are set
to the values of FLAG, LCNH, LCNL, LHN, and LSN of
the last verified sector.
(6) The descriptions in items 4, 5, 6, 8, 9, and 12 of the
Read Oata command are valid in this command. Please
refer to these items for additional detail.

PHN

= Physical Head Number

LCNL
LHN
LSN
SCNT
EST

= logical Cyllndor Number,low Byto

r~ ~ ~.:rC!YI~n"dr:;~m~~ ~~~

SCNT

g;:z

"'" ~Ical Hud Number
= L.oglcal Sector Number

:I:

S8ctor Number

= Error Status

(1) This command is used to write data into th~ data field
of the sectors specifed by FLAG (hard disks only),
LCNH, LCNL, LHN, and LSN, and to write CRC bytes or
ECC bytes according to each internally specified mode
(CRC or ECG). The data is written to the disk via OMA
transfer from the local memory.
(2) After writing data on a sector, the HOC updates the
contents of SCNT and LSN, and repeats the above described Write Oata operation until SCNT is equal to
zero.
Ouring the above Write Oata operations, if LSN is equal
to ESN, the HOC updates LHN and LSN, and continues
the Write Oata operations after selecting the new head
(track) specified by LHN.
As described above, the HOC has the capability of
mUlti-sector and multi-track write operations.
(3) The HOC abnormally terminates the execution of this
command if the SCNT is not equal to zero when the
HOC writes the data to the last sector (LSN ESN and
LHN ETN). The ENC (end of cylinder) bit of EST (error
status) register is set to one in this situation.

(4) If the write protected signal is active (high) at the beginning of the execution of this command, the HOC
ends the execution of this command in the abnormal
mode after setting the NWR (not writable) bit of the EST
register to one.

(5) After detecting an active TC signal (TC 0), the HOC
writes the data 00 to the sector, instead of the data from
the host system.
In the case of SCNT of two or more, when SCNT is updated, the OMA transfers will restart and writing of host
data will continue until SCNT O.

(6) In theST506-type mode, the HOC will set t~e reduced
write current output bit to a one when the cylinder number becomes greater than that specified by RWCH and
RWCL. These parameters are loaded during execution
of the Specify command.
The descriptions in items 4, 5, 6, 8, 9, and 11 of the Read
Oata command are applicable here also. Refer to these
items for further detail.

6-25

~EC

pPD7261A/ B
Sense Interrupt Status

Table 7.

Mode Byte Bits
SpecHied Mode

Bit Name

1 EGG is appended in data field: (x21+1) (xl1+x2+1)

EGG

Isr

Interrupt Stotus

o GRG is appended in data field
1 Generator polynomial: (xI6 +1)

GRGS

(1) The HDC transfers the new disk.status to the host
CPU at the end of a Seek or Recalibrate operation or the
new disk status resulting from a change of state of the
ready signal, which may occur at any time.

·1 Soft·sector disk (floppY'like interface), MFM data

SSEG

o Hard-sector disk (SMD interface), NRZ data
SSEC=O

(2) If the Seek or Recalibrate command in progress is
completed when this command is issued or if there has
been no change of state of the ready signal from the
drive, this command will be terminated abnormally.

SSEC=1

DSL

Data strobe late

STP3

(Note 1)

DSE

Data strobe early

STP2

(Note 1)

SDM

Servo offset minus

STP1

(Note 1)

SDP

Servo offset plus

STPO

(Note 1)

Note:
(I) Slepping rale for ST506 mode = (16-STP) X 2110 X ICY
Assuming a 10MHz processor clock: FH 2.11 ms ... OH = 33.76 ms

Specify

MODE

MODE =
DTLH
DTLL =
ErN =
ESN
OPL2 =
MGPL1 -

DTLH

DTLL

ErN

ESN

GPL2

I~~~Y

IRWCL)

Soft·Sector Mode

SoIects Operation Modo
= Modlllyto;
DolO Lli1gth, High Byte
DolO Lonjjth.Low Byte
EndIng 1IiIck Number
= Oop
Ending Sector Number
LOngth 2

Gap

Lonm

Sense Unit Status

I ~lX Iusr

(uoed In SMD modo only); Control. Raad Ootl TIming

::g~ ~ =~:d WrI:: ~:::~l!~:=:=::ft!!h:1."

SMDMode

The Specify command is used to set the operational
mode of the HDC by. presetting various parameters.
Parameters.such as MODE (figure 5, table 7), DTLH (figure 6), DTLL, ETN, ESN, GPL2, MGPL1/RWCH, and
RWCL may be programmed into .the HDC. This allows
for a high degree of versatility. Data record length is
programmable from 128 to 4095 bytes in soft-sector
mode and 256 to 4095 bytes in hard-sector mode;

Figure 5. Mode Byte

OO11X

I:sr

The Sense Unit Status (SUS) command is used to trans·
fer the Unit Status (UST) to the host. In the case of SM D
mode the SUS command may also be used to transfer
the Detail Status (DS) and Device Type (DT) by using the
appropriate preset parameter value as shown above. No
preset parameters are used in the soft-sector mode, al·
though one is required in the SMD mode. Values other
than 1, 2, or 5 do not produce valid results.
After result bytes are placed in FIFO, HDC generates a
FAULT CLEAR when in SMD mode.
The DS and DT bytes are defined by the type of drives
used. The UST is shown in table 8.

Figure 6. DTLH Byte

I I I I I I I I
CRC'

CRC'
PAD
POL

PAD

POL

DTLll

DTLl0

Dna

= Inllial value o' Potynomlol Countor, Ellhor All Zoroa or All Onn
= SoloclaID/DolOpadolOllHIIO
= Solocla ID/DoIO pad oI4EH 111

= Polling Modo 110
= Nonpoliing Modo II 1

Table 8.

Unit Status Byte
Interface Type

DTLB

Bit

No.

SMD
Unit selected

Seek end

Write protected

6-26

STS(!6

Drive selected

Unit ready

Seek complete

On cylinder

Track 000

Seek error

Ready

Fault

Write fault

ftiEC

J.lPD7261A/B

Detect Error

Figure 8. Auxiliary Command

I ~oox ~1-~-D-H---~-D-L---EP-T-1--E-P-T2---E-~-3--------------~
EACH
EAOL

= Error Address, High Byte

EPT1

Error Pattern, Byte 1
Error Pattern, Byte 2
== Error Pattern, Byte 3

EPT2
EPT3

=
=
=

Clear Data

Halt Sense Interrupt Status Request

Error Address, lDw Byte

Table 9.
This command is used to transfer the error pattern and
the error address to the host CPU, when correctable errors have occurred during the execution of a Read Data
command with the ECC mode enabled.
The error address (EADH and EADL) is calculated from
the last data byte of the sector that contained a correctable error which was indicated by the status bit of the
previous Read Data command with the ECC mode enabled_ The error pattern is used for correcting the error
data at the location where the error occurred. After receiving the error address and the error pattern, the host
CPU can correct the error data by performing an
exclusive-OR of the error pattern and the error data. See
figure 7.
The result bytes are available to the host CPU within
100l-'s.

Figure 7. Error Correction

Buffer

Auxiliary Command Bits
Operation

Bit Name

CLCE

Clears the CE bits of the status register. inactivating the
interrupt request output caused by Command End condition. This is used when no disk commands are going to be
issued and it is desired to clear the interrupt.

HSRO

Deactivates the interrupt request output caused by Sense
Interrupt Status Request condition until a Command End
occurs. However. this command has no effect on the SRO
bit of the status register.

CLB

Clears the data buffer.

RST

This has the same effect as a reset signal on the Reset input. This function is used whenever the RRO bit in the status register is set (indicating the format controller is hung
up), or when a software reset is needed.

System Example
Figure 9 shows an example of a local bus system.

Figure 9. Local Bus System

TheSecfor

Included
Correctable
Error

--OTL------j.1

1--1.

The Corrected
Data Bytes

~-EADH,EADL_.
n-1

The Error Pattern

Local Memory
RDWRDB

I EPT1 I EPT2

n-2

EPT3

AEN
.L.....__...J...__~

L._ _ _ _

Note: EDn equals error byte.

Cs
HAQ
HLDA

OMAC
(8237)

Auxiliary Command
IOOOOAAAA

--------j

1 - - 1

There are no preset parameters or result bytes associated with this command. The definitions of the 4 LSBs
(AAAA) are given in figure 8 and table 9. The auxiliary
command is accepted at any time and is immediately
executed. The auxiliary command may be used to recover from certain types of error conditions, or to mask
and clear interrupts.

6-27

NEe

pPD7261A/B
Track Format

System Example Timing Diagrams

Figure 10 shows track format for hard- and soft-sectored
disks.

Figures 11 through 22 show the interface timing (softsector and hard-sector) required to interface the hard
disk drive.

Figure 10. Track Format
Indexl

Hard Sector

Soft Sector

Seeto<

Index
HEAD
SCATTER
PLOSVNC

OOH(GPL2)
AM

19H(1)

FLAG

(')

LCN

(2)

LHN

(')

LSN

(')

(2)

IDPAD

PLOSYNC
DOH (GPL2)

19H(1)

the drive to allow the drive's read data PLO to
becomepha ..... and freque ney-synchronlzed
with the data bits recorded on the media.

4EH{GPL1)

f--

DOH (GPL2)
AM

These bytes are written by the controller and

are required by t he drive to ensure proper
recording and re coveryofthe last bits of the
~data field check codes.

PLOSYNC

10 field

DOH (2)

CRC

GAP1

- These GPL2 bytes of zeros are required by -

DOH (GPL1)

AtH

(1)

LeNH

(')

LeNL

(')

LHN

(')

LSN

(')

CRC

(2)

10 PAD

4EH/ooH(3)
PLOSVNC

---

--D,hiS byte indicatea to the c ontroller the I d } beginning of the 10 field or the data field and
it establishes bytesynchronjzation.

DATA

OOH (GPU)
AMA1H

(1)

AMFOH

(1)

DATA
(DTL)

(DTL)

ECC/CRC
(4/2)

DATA PAD
DOH (2)
END OF

Inde"

Sector

RECORD

DOH

f--

These bytes are written by the controller and
are required by the drive to enaure proper
recording and recovery of the laat bits of the
I o field check codes.

EcC/cRe
(4/2)

I--

DATA PAD
4EHlooH(3)

INTER
RECORD GAP

4EH (GPL3)
GAP4
Index

6-28

4EH

t\'EC

pPD7261A/B

Figure 11. "Unit Selection" and "State Sense" Timing (Hard Sector)
_1

.~"

TOg 2

"1"

Tog 3

Bus

.~"

D"""Ion:::"I:::-"--------.~"'_------'1

Sf' Sal. Tag

"1"

us Tag

:::.~:;;,,-----"""""\,~

BT2-11T9

:A~om~I~~~---~--~/~I~~~~-----------UnltAddr

BT1

"G"

BTO

''0"

I,,
I,
I

UnHSalOCIad
_End

BftlH!

___________\~)lr--~:~e~----------------------I

.'
.~"

I
I

~~~--~r'~~~==~\~~~~~~~--------
Undallnad __-'~ Unit Add, (BT2-BT4~ Undollnad (Others)
===

'la

Linea Device Statue 1

(Unft Roady)

unltSeloCt
2"-2"

~~U~n-.dall~.~nad~-------------

undallned
===----'
;---\

1--1
State 8fter Reset

UnftAdd~':===---------------

H
UnH
Selection

"Unit Selected" and "Unit Ready" 81gnall
are checked through BTl and BT5 pins.

ftiEC

pPD7261A/B
Figure 12. Return to Zero Timing (Hard Sector)
---------------------;Il~------------------

----------~,~r-----4\~I------------------~

BUI Direction
Sr Sol.

----------

~:
I ,
BT2-BT9
BT1
BTO

Index

\\1--;'-\_ _ _ _ _ _ _ _ __

1'0"\

I
I
I

)\-\--\\----------

BTa. 1 (Seek End)

"IUnItAddr

"0",

\ '"'\ ..

'v------------\..
. . '-

'-11----'

Unll Solected ---.../
Sosk End

BftCH!

r~
r
I '--------~

\
\
\

Sector

l..

II}
b'----~ll----"

.JX

",U_=:::I_=_ _

Bft 6-1

~oftned:>-lt=t;:::.~~~~~~~~~~~~~~~~~~~~~=

9mWsSOnH-----~~~~a-=Shd~~-1~----1111-------------Lin..

UnftSelOCl

1'-22

.c;:::::x

Und~_

UnltAddr

1--1
Unft

1--1
"Rotum to Zero"

SeIecIIon

leleeued.

1\1--------------:~~u~~~~~n~~~----
UnltAddr

Sosk End signal I••heck~
at this point.
83-003500B

6-30

fttlEC

pPD7261A/B

Figure 13. "Seek" Timing (Hard Sector)
\\

'LI
I

"1"

I
I
I

"1"

.f\

Bus Direction

Sr Sel. lIog

.'
"1"

'----------

I
I

USlIog

~"I
I

BT~T9

Unit Addr
I

Index
S8ct0,

r~
/

I Cylinder Addr 2-91

,.
I

c--=\C~lInde' Af~\-'.j.IO_ _ _ _ _ _ _ _ _--I._ _

I
I
\
\
\

Unll Addr

~cyllnde'~~'11

BT1

BTO

~~BT8=SeekEnd(lnpUI)

I
I

\
\

Unit Selected

--1

Seek End

-----------~\~X\

BItIHl

-< Undellned

~~~
l~

~~:_.....:u,;,;ndeft=,;,;ned:..:;,._ _ _ _ _ _ __
Cyllnde, Add,

\11_-------------

~~~R-------.Dw~I~~S~"'~U.~1~~---illl_------------Unit Selact
2"-22

~Undeftned
:~~U,;,;nd=~~ned~----Unit Add, ===~------_l.
Unit Add,

Unit Selection

"Seek"
I. Issued.

BT8 (Seek End) signal Is checked at this
pelnt.
83-0035018

6-31

t-{EC

pPD7261A/B
Figure 14. "Head Select" Timing (Hard Sector)
Tag 1

Tag 2
Tag 3
Bus

"I"
"1"

"I"

""'\\I.._______

Di,ection~_--_ _ _ _ _ _ _ _

5,5.'. Tag
us Tag
BT2·BT9

~
I

~
UnitAddr

Input

XH••d Add, 2.7X Input

BTl
BTO

Index

Secto,

Heed Add, 1 \

''0''

/ Heed Addr 0 \
"0"
\

\
\

Unit Selected

Seek End

BHIHI

Undefined

XH ••d Add, 1J.7X Undefined

=:Lln.. _____-=Dev='ce=SIaI=u:.:.:..l:....._~_ _~_ _ _ _ _ _ _ _ _ __
UnH SIIeCi
2"-2'

Unit selection

I· "Head Select"·1
I. Issued.
83-0035028

6-32

ttiEC
Figure 15.

pPD7261A/B

"Unit Status Sense' Timing (Hard Sector)
"1··
··1"

"1"

Bus Dlrection---""
Sr Sel. Tag

iiSTa9

BTO

Index

usn

BTa-BT9

BTl

\
"0" means that HOC Is selecting One Unit.

USf2

Devtce~pe

''0''
''0''

Index pulse
Sector pulse

I 1---1

/.
/.

SRO

I /.

OT1

SR1

OT2

Unit 5elected :::"l;;;"-::m=
..::n=.-:;:tha=t::.~U==n;:-RI==.-=••: : ; - l e c t = . " : ; d . - - - - - - - - - - - - - - - - - - i
Seek End

BlteHl

"1"

_ _ _ _.I_ll_._ _ _ _-JX~

__B_H_9-_0_~>CJ<~_~BH~9~-~1~_

Stat~~::nse _ _-=U",nl::.I.::;SI=ol:::"::.s..:.l.:;:(U;.;:ST1)=_ _- JX

Unit Status 2
Undefined

Unlt5elect
2'-22

x:::::x

Device Type

~
OS

OnCylindar .".~"',,----------------------_

Unit Statu. 1
Is read through

BTO·BT9 pin ••

Unit Status 2 Is
read through BTO-BT9,
Index, sector pins.

The Device lYpe is read
through BTa-ST9,
Index, Sector pins.
83-0035038

6-33

IIPD7261A/B
Figure 16. "Data Read" Timing (Hard Sector)

::~}-------------------------------------------;ll~-------------------

Sr Sel. Tag

"1"

Bus DI:~: } __".;:.O'_'-------------------------------------------\\ll-------------------l\l--------------------

Unll SeIac1ed }

Seek End
Sync

RD/RefClk

BTO (Writo GolO)
BTl (Road Gato)

Index/Sector

"1"

_ _ _ _ _-J1

-1Ulfl:--- -

-----Jl

(ReadClk)

~,='O'~,----------------------------------------~\'~·--------------------

_____~/r-----~'--i~-----~\'~,--------~\~___

~~---------------~H~----------~r--ECC(CRC

Format

Data
(DTL)

(4/2)

End 01

Record
83-0035048

Figure 17. "Data Write" Timing (Hard Sector)

:;~}-. -I"------------------------------------------~I\~-------------------

Sr Sel. Tag

Tag 3 }
Bus Direction
US Tag
Unit Seloctod }
Seal< End

Sync

RD/Rof Clk

~~----------------,l\~------"0"

--------------------------------------~ll~--------------"I"

"0"

\~---------~l\r_--------

I.JUlJlJ ----

(Servo Clock)

___________-JI

\'i

BTO (Wrlto Oato)
BTl (Road 0010)

Index/Sector

____--'I

\~------------------~n

~~-------------------------------------'l\l

~
ECC/CRC

Format

(:1 ~

lil~1
(4/2) (2)
83-0035058

6-34

NEe

JlPD7261A/B

Figure 18. "Drive Select" and "Unit Status Sense" Timing (Soft Sector)
Drive Select

051,050-0,

~,-...:I,,-,I'-_ _ _-t:\-~___...Jx"O::.,..;.I_ _ _ _ _ _ __

I~------------------___tl\_l--------------------Drive Select 1 _ _ _---J

~~------------tlrl----~\~-------Drive Select 3

-----------!)~--"""'\----I

"'Or"'lve=se"'"le:-:ct~4

,,11----------

,o------;lll-----' \
\

Drive seleeted - - - - - - - - ';

Vrl- - - - - - - -

x::::::=:x:=::Y____---l!~\_---...JX'-----..L.--x::::::=:x:=::Y
!~
X"-______"'--___
_ _ _ _x::::::=:x:=::Y
::
X'-_ _---+-_ _

Seek Complete _ _ _ _ _ _
Track 000 _ _ _ _ _
Ready
Write Fault

______~~

X~___~-----

--D-r-iv-el-l-s--~1-0-r-lve-2-i-s~I-D-rl-ve-3-I-S*1----D-rive-4-1.~1~1-----~-D-rl-ve-2-1.--IL----selected.

selected.

selected.
Unit Status is read through

pins 29-33 at this point.
63-0035068

Figure 19. "Normal Seek" Timing (Soft Sector)
Drive Select

===x

Stable

Direction In

Stable

Orlve select X ~
Drive Selected

>C~

===x

Step

Stable

d!=X
l\

V
I·

·1

Direction In signal and a step pulse are
issued after Ready signal Is checked.

Stable

-.-J

V
I-

dt=x
1\

0~
Stable

x==

Stable

c::=
x=::=

The rate at which step pulses are issued Is
controlled by STPn (Step Rate) In Specify

Command.
83..0035078

6-35

WEe

pPD7'281AJ'B
Figure 20. "Buffered Seek" Timing (Soft Sector)
Drive Select

=:::X~______.....;;Sta=b;;.;I.,,-_ _ _ _ _ _ _>Gp<_---,S::ta=b:::le,--_x:::=

DriveSelectX

DrlveSeIectad

=...J

m~~I~ln
Slap

_COmplete

at="'

Stable

r-c-=

_ _ _-JX~

_____________~xj~~__________

----4IU1f - - - - - - -

(,-\ r-

~\~-----------

tSTCY

----~~

~~r7

'-.--------~'l~

~b~UH~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~L1y~t=\--~-------Lr===---

!Direction In Signal and continuous step
pulses are Issued.

!•

Seek Complete, Ready and WrHe Fault
signals are polled periodically until the

seek operation Is completed.
83-0035089

Figure 21. "Data Read" Timing (Soft Sector)

Data

Format

(DTL)

(4/2)

~d~~~I------~--~'-Jr------------~II~I------~,-
Sync

'----I

'--

~~~I---------------------------------;\\~-----------

DrIve Select

n~---------

--v-----41-1- - - - - - - - - :SC'"taC ' " b l : - . - - - - - - - - - - - i l l l - - - - - - - 1
~r·------------~~----------------~nr'-----------

Reed ~ Iino ta .~lvatad altar ~dy

oIgnolle checked.

Sync line is set when bit synchronization
is established.
83-0035098

6-36

t-{EC

pPD7261A/B

Figure 22. "Data Write" Timing (So't Sector)

Format

Data
(Gap2)

Re8dGate~t
Sync
WrHe Gate

----ll~

(1) (1)

(DTL)

(412)

(3)

\~----------------~II
II
\~----------------~}-------------

------410-1----------'1

II
II

RNdy~:r---------------------~

~PRECOMP----ill~---------------~X~~~~lid~----------~:~

')C

DriWS~~~:~------------~SU==b~=-------------~11

Read Gate line Is
activated after Ready
and Write Fault signals
are checked.

Write Gate line Is activated during the
period b e _ 3 byl.s after ID fl~d~ CRC

by1es and 3 by1ea aftar data field's ECCI
CRCby1es.
83-0035108

6-37

pPD7261A/B

6-38

NEe

#,PD7262

Enhanced Smail-Disk
Interface Controller

NEe Electronics Inc.

Description
The /LPD7262 enhanced small-disk interface controller
(ESDIC) is a hard-disk drive (HDD) controller capable of
supporting up to seven HDDs. It is a single-chip solution
to ESDI controller design and conforms to ANSI Specification X3T9.3/1987, revision F.
Note: A control sequ ence that changes the state of the
write gate (WGATE) signal to function as the
write start signal for the 10 field's phase-locked
oscillator (PLO) area for hard-sector formatting
is covered in the ANSI specification, but it is not
supported by the I'PD7262.

The /LPD7262 can be controlled by a general bus like the
one provided by the V-Series family. It has 27 powerful
commands and its control interface significantly reduces host processor overhead for HODs for both software and hardware. This simplifies interfacing.
The /LP07262 uses the group drive concept to control up
to seven HDDs divided into a maximum of three groups.
Each group may be designated arbitrarily according to
common control parameters such as data length per
sector, number of sectors per track, and error correction/
detection.

o Data read function from sectors with errors
o Skew function
o CRC/ECC selection
o NMOS technology
o Single +5 V power supply
o 40-pin ceramic DIP

Ordering Information
Part Number

Max Frequency

~PD7262D18

18 MHz

~PD7262D12

12 MHz

Pin Configuration
4O-Pin Ceramic Dip
WDATA

VCC

RDATA

RGATE

RClK
RESET
INT
DMARQ

Features

TC
WClK

o Serial mode ESDI-compatible
o Capable of controlling up to seven disk drives
o Supports up to 80 heads (5 groups of 16) for each
disk drive
o Hard- and soft-sector interfacing
o Programmable track format
- Variable byte synchronization patterns: ABSP and
DBSP
- Variable data length: 128 to 65,536 bytes/sector
- Variable gap length
Intersector gap
PLO sync field
Format speed tolerance gap
o Selectable sector start signal:
sector pulse/address mark found
o Maximum clock frequency
-18 MHz (7262-18)
-12 MHz (7262-12)
o 22 disk commands available
o Parallel seek operation capability
o Multisector, multitrack, and multicylinder functions
o Implied seek function
o Data scan/verify function

Package

4O-pln ceramic DIP

WGATE
ClK
INDEX
SECP/AMF

DSD

READY

ATT

CMDC

HSOIXACK

HS,lRxD

HS2fTxD

HS3IXREQ

DS,

DS2

DS3

GND

AME
IC

RW/COM
49M·OOOO71

50031

6-39

NEe

p.PD7262

Pin Identification
Symbol

Pin Identification (cont)

I/O

Function

NOlit System Interface

Address 0 (register select); selects a register or
the data FIFO.

00-0 7

I/O

Three-state bidirectional data bus.

DMARQ

Out

DMA request

INT

Out

Interrupt request; indicates completion of command execution by the "PD7262 or completion
of a seek operation by a disk drive.

Controls reading data or status from the
"PD7262: active low.

'i'C

Terminal count; indicates completion of data
transfer; active low.

Controls writing data or commands to the
"PD7262; active low.

Symbol

I/O

RxD

Receive data; receives configuration/status
from the disk drive; see RN/COM above

SECP

Sector pulse; indicates the beginning of a sector in a hard-sector type of disk drive.

TxD

Out

Transmit data; transmits a serial command to
the disk drive; see R/W/COM above.

WClK

Out

Write clock synchronized with WDATA.

WDATA

Out

Writes data (NRZ) to the disk drive.

WGATE

Out

Write gate; signals the disk drive to write data.

XACK

Transfer acknowledge; acknowledgment by the
disk drive to a request for command or configuration/status transfer; see RN/COM above.

XREQ

Out

Transfer request; requests a command or configuration/status transfer by the disk drive; see
RN/COM above.

Disk Drive Interface
AME

Out

Address mark enable; causes the disk drive to
write or to search for an add rass mark.

AMF

Address mark found; indicates the beginning of
a sector in a soft-sector type of disk drive.

ATT

Attention; requests receipt of the standard
status byte issued by the disk drive.

CMDC

Command complete; indicates that the disk
drive has completed the execution of a serial
command and is able to receive the next
command.

DS3"DS I

Out

Drive select 3, 2, 1; binary encoded outputs
that select a disk drive.

DSD

Drive selected; indicates that the disk drive
specified with DS3'DSI is selected.

HS3"HSO

Out

Head select 3,2, 1,0; binary encoded outputs
that select a read/write head; see RN/COM
below.

INDEX

Indicates detection of the index mark in the
drive.

RClK

Read clock that samples RDATA during read
operations; also the reference clock thai determines the WClK frequency during write
operations.

RDATA

Read data (NRZ) from the disk drive.

READY

Indicates the disk drive's ready state.

RGATE

Out

Read gate; signals the disk drive to read data.

RN/COM

Out

Read-write/communicate; determines the function of pins 25-28.
Pin

25
26
27
26

6-40

RN/COM
1
0
HS3 XREQ
HS2 TxD
RxD
HSI
HSo XACK

Function

Cin:uit Control
ClK

Single-phase system clock; the frequency must
be between 0.7 and 1.8 times the RClK frequency and the clock signal must be input continuously.

RESET

Clears the internal circuits of the "PD7262.

Test mode; this pin should be grounded for
normal operation; the ground is removed for
test mode operation.

GND

Ground.

Vee

+5-volt power supply.

ttt{EC

"PD7262

Standard Signal Names

Table 2. Data Cable Connections With pPD7262

Tables 1 and 2 show the conversion between the
IlPD7262 pin symbols and the ESDI standard signal
names.

Pin Symbol

ESDI Signal Name

WDATA

± NRZ write data

RDATA

± NRZ read data

RCLK

± Read/reference clock

Table 1. Control Cable Connections With pPD7262
Symbol

ESDI Signal Name
Drive select 1-3

DS1-DSa

Head select 2(0)-2(3)

HSO'HSa
XREQ

Transfer request

XACK

Transfer acknowledge

TxD

Command data

RxD

Configuration/status data

READY

Ready

WGATE

Write gate

RGATE

Read gate

WCLK

± Write clock

CMDC

Command complete

DSD

Drive selected

AME

Address mark enable

SECP

Sector pulse

AMF

Address mark found

INDEX

Index

"PD7262 Block Diagram

Format
Control

CLK_
RESET_

Unit

MUX

Status

/L---I~

"---1111

~--------~

Disk Drive
Interface
Control Unit

;

Serial
Communications
Unit

RCLK
WCLK
RDATA
WDATA
RGATE
WGATE
INDEX
AME
SECP/AMF

RW/COM
DSD
READY
ATT
CMDC
HSO
HSl
HS2
HS 3
DSl
DS2
DS3
XREQ
TxD
RxD
XACK

AO----~----~----,

RD
WR
INT
DMARQ
TC

Host System
Interface
Control Unit

49M..(l00070

6-41

t-IEC

#,PD7262

Absolute Maximum Ratings
= +25'C

DC Characteristics
= -10to +70'C; Vee = +5.0V ±10%

Operating temperature, To- RE,AD GATE
HSOIXACK

I+-~--.-.:.-r-~-_p.-~.:....-+ HEAD 'SELECT ~
Data
Selector

HS,IRxD

r-----.....-;...;r-;...;-P...- - - - CONFIGlSTATOi "'D"'AT·A"
T

•

FiYi7eml
,,-,

HS211'XD I--__-_r-..z...-,..----+ HEAD SELECT 22

.•

...-----tiiANSFER ACK
t>--~--. HEAD SELECT 2'

Demultiplexer

HS3IXREQ r--'----~
.. '

AME

___

~---- C6MMAND DATA
HEAD SELECT ~

.....J~----TRANSFER REQ

r---ip------+ ADDReSS MARK ENABLE

···

~+WRITE

W!:LK t-----efDemultIPlexerl .:

~+WRITE

WDATA
~

, JLPD7262

L..-r-r.,."""" :

CLOCK

~.WRITE CLOCK
DATA

b:J::=,-WRITE DATA
DIFFERENTIAL DRIVER

t----,---+-+-+-' ~--

DS,
-t.......
DRIVE SELECT ,
DS2
.... .....
DRIVE SELECT 2
:
DS3 t - - - " ' - - - - + + + - -.....
'--··~i~
.....- DRIVE SELECT 3

....

~.+.READ.DA.TA

RDATA

~-REAP PATA

~---~~+READ~EFERENCE'CLOCK
RCLK I+-~----i Multiplexer

I : .•

··
··
·
•

DSD

ATT
INDEX
READY

DIFFERENTIAL RECEIVER
DRIvE SELECTED

p.o.:..:----COMMAND

CMDC
SECP/AMF

~_-READ~EFERENCECL()CK

, ..

'_I-_~_.,_____ ftCTO'RiADDRESS MARK FOUND
......

i+------aC
',A ~
~~

COMPLETE

ATTENTIoN'

iNDEX

READV

''IM-000073

NEe

I'PD7262

SECTOR FORMATS
Figure 28 shows the hard-sector and soft-sector formats for a hard-disk drive,

Figure 28.

INDEXI
SEep

Hard-Sector and Soft-Sector Formats

Hard-Seclor Formal

~ ...
- - - - - - - - - - Address A r e a - - - - - - - O o j t l 4 _ - - - - - - - - Dala Area

ISG

PLO
SYNC

ABSP

ADDRESS FIELD

"00"
"00" 'ABSI' 'LCNIr 'LCNL'j'LHN j'lSt;' j VLAG'
XGPIL XPLOL 11
11
11
11
11
11

~
ISG

ADDRESS
MARK

ADDRESS
CHECK
BYTES

ADDRESS
PAD

'CRC"

'00-

WlUTE
SPUCES

PLO
SYNC

DBSP

"00"

'DBSI'

XPLOL

Js~
---------0011.....

DATA
FJELD

L..

DATA DATA
CHECK PAD
BYTES

'CRCI
XDTLH, L ECC"

12/4

'00"
12

~ISG
GAP2

"00'
XGP2L

Soft-Sector Format

ADDRESS
MARK
PAD
Same as hard-sector format,

"00'
XGPIL

ISG
ABSP
DBSP
FSTG

Inler SSClor Gap
Address Byle Sync Pattern
Data Byte Sync Pattern
Format SpHd Tolerance Gap
49M·OOOt02

6-65

"PD7262

6-66

t-IEC

NEe

p.PD72061

NEG Electronics Inc.

Description
The p.PD72061 is a hard-disk controller featuring low
power consumption and high-speed data transfers.
Based on the p.PD7261 AlB, it provides cont rol signals for
interfacing SMD/SMD-E and ST506/412 type drives. The
sophisticated instruction set minimizes the software
overhead for the host microprocessor and gives the user
flexibility in selecting operating parameters.
The DMA interface signals of the p.PD72061 facilitate
multisector and multitrack data transfers. Extensive error reporting, verify commands, and CRC/ECC data
error checking assure reliable controller operation.
An 8-byte FIFO is used for loading command parameters
and obtaining command results. This makes structuring
of drivers a simple task. The FIFO also buffers data
during DMA read/write operations.

Features
D

D
D

Flexible interface supports SMD/SMD-E and
ST506/412 type drives
Programmable track format
Controls up to eight drives in SMD-type mode, four
drives in ST506-type mode

CMOS Hard-Disk Controller

o Parallel seek operation
o Multisector and multitrack transfer
D Data scan and data verify
D High-level commands, including:
- Read Data, Write Data, Scan Data, Verify Data
- Read ID, Verify ID
- Check, Seek (normal or buffered), Specify
- Read Diagnostic (SMD only), Detect Error
-Format
o NRZ or MFM format
o Read/write clock frequency: 24 MHz max
D Error detection and correction
D CMOS
o p.PD7261 AlB compatible
o Single +5-volt power supply
o 4O-pin plastic DIP, 52-pin plastic miniflat, 52-pin
PLCC

Ordering Information
Part Number

Package

"PD72061C

40-pin plastic DIP

"PD72061 GC-SB6

52-pin plastic minlflat

"PD72061L

52-pin PLCC

50072

6-67

t-{EC

"PD72061
"PD72061 Block Diagram
RlWCLK - - - 1 1 - - - - ,
BTl (RGATE) __--~
RIW DATA __---t..
Format
Controller

BTO(WGATE) ----~
SYNC __
--~

(POL) SOT

---I

INDEX -:--~I-

___

Processing
Unit

ClK
RESET

DaIaBuIfer

axa Bit FIFO
Disk Interface
Control

00 - 07 '\r----,;II
Internal RAM

TC
AO

iffi ----t-l
WR
CS ----t'"
INT __- - - I

OREQ __- - - I

6-68

ReadlWrite

INTIDMA
Control

ROM

L---~(Control Firmware

Multifunction

OIsk Interface
Lines

NEe

#£PD72111
Small Computer System
Interface Controller

NEG Electronics Inc.

Description

Pin Configurations

The I4PD72111 is a small computer system interface
controller (SCSIC) conforming to ANSI X3T9.2/82-2
Rev.17B. The I£PD72111 SCSI controller offers a true
16-bit CPU data bus but also can be interfaced to an
8-bit CPU data bus.

64-Pin Pillstic Shrink DIP (750 mil)

The I£PD72111 contains functions for controlling the
sequence between bus phases so that host processor
overhead can be reduced. In addition, single-ended type
bus drivers/receivers are internally provided on the SCSI
bus side so that system size can be reduced.

GN01

RST

GNOO

SEl
BSY

elK
RESET

0liE
EOP

MSG

INT

REO
ACK

10WR

The I£PD72111 was developed utilizing NECs 1.2-l£m
CMOS process technology for low power consumption. It
operates from a single 5-volt supply and is available in
plastic DIP, PLCC, and miniflat packages.

i5RD

o Conforms to ANSI X3T9.2 Rev.17B
- Arbitration function
- Disconnection/reconnection function
- Parity generation and check function
o Two different data transfer modes
- Synchronous: 4.0 Mbytes/second max; offset
value selectable from 1 to 8
- Asynchronous: 4.0 Mbytes/second max target
o 16 commands reduce host CPU load; automatic
execution of standard operation as SCSI controller
can be performed by a single command
o Operates as initiator or target
o Internal single-ended type SCSI bus drivers (48-mA)
and Schmitt-type receivers
o CPU data bus width selectable (16 bits or 8 bits)
o Programmed transfer or DMA transfer selectable
o Internal 24-bit transfer counter
o FIFO-type data buffers on SCSI bus side and CPU
bus side

GN01

OMARa

ATN

iSMAAR
'i6B

GN01

GNDO

SB6
GN01

VOO

Features

GN01

1/0
C/O

SB7

SBs

SB4
GN01

Ao
OPH
GNDO
OPL

SB3
SB2
GN01

015

SB1

014

SBO

013

SBP

D12

GN01

011

010

06
VOO

05
GNDO
83vQ.5913A

Ordering Information
Part No.

Package

"PD72111CW

54-pin plastic shrink DIP (750 mlQ

"PD72111 GJ-5BJ

74-pin plastic miniflat

58-pin PLCC

50079

6-69

ttiEC

"PD72111
BB-PlnPLCC

8 Ci

I> Ci

~ ~I@I~I~ ~ ~ ~ ~I~I~ ~ ~1218 ~I~
0.. W

I- -'

1C!l 0

ACK

iOWA

GNDl

lORD

i5MiiRQ

ATN
GNDl

DMAAK

SB 7

lSB

SBs
GNDl

GNDO

SBs
SB 4
GNDl

VDD
A2
Al
AO
DPH

SB3

GNDO

GNDl

SB2

DPl

SB 1

D1S
D14

SBo
SBP

D13

(,)

.... OcnCOr-.<00gIl)V('l')N ..... O

....

z~~~ccccizcccccc~

C!l

C!l
83vQ.59fSB

7~Pln PiIIstic MlnNlllt

I-zl~I~I~I~
21~1~1~
2 gl~l@a:
_ w
a: ~ ~
a:
::> 0

0 C!l 0Z C!l

REO

To Other SCSI

Devices

SCSI
Data Bus

L...
SCSI
Control Bus

-I--<

iORo
i5WR

Ao-A2

AO -A23

INT

I---

MWR

Do - D15

A
y

moti'C

WR
im

•

DMAAK

10WR

MemolY

flPD72111

I I I

H+

Address
Bus

Data Bus
(16/8 bits + parity bits)
....W83S.

6-73

NEe

"PD72111
Internal Blocks
Name

Description

Name

Description

SCSI bus
driver/receiver

Open-drain driver for a single-end SCSI bus
and a Schmitt-type receiver.

Arbitration!
selection
control

Controls execution sequence of arbitration,
selection, and reselectlon phases; consists of a
timing generator and a sequencer.

Host parity
generator/
checker

Generates parity that will be attached to data
output to CPU data bus; or checks parity
attached to data read out from CPU data bus.

DMA request
control

Bus phase
control

Outputs a signal that specifies bus phase type;
also monitors bus phase to detect a transition.

Generates DMA service request signal (DM7iRO)
according to FIFO status; also controls termination of command operation by l:O"P signal.

SCSI transfer
control

Controls data transfer operation on the SCSI
bus In each data transfer phase: data-In, dataout, status, message-In, and message-out.
Controls SCSI protocol according to REO and
~slgnals.

Controls data transfer sxecutlon/termlnatlon
according to SCSI FIFO status.
Contains a 24-blt transfer counter that manages
the amount of transfer data on the SCSI bus.
SCSI FIFO data
buffer

Eight-bit, elght-stage asynchronous FIFO that
adjusts difference between data transfer timing
of internal and external SCSI buses; also used
for queuing received data for synchronous data
transfer.

Command/
message
decoder

Decodes received command and message;
generates decoded signal that specifies the next
sequence.

SCSI parity
generator/
checker

Generates parity that will be attached to data
output to SCSI data bus; or checks parity
attached to data read out from SCS I data bus.

Main control

Sequencer that controls microprogram,
operation of each block, and control sequence.

Internal transfer
control

Input voltage, VI

-0.5 to Vee + 0.5 V

Output voltage, Vo

-0.5 to Vee + 0.5 V

Operating temperature, TOPT

-10 to +700C

-65 to + 1500C

Storage temperature, TSTG

DC Characteristics
TA

= -10to

Parameter
low-level
Input
voltage
Hlgh~evel

Input
voltage

+700C; vee

= +5.0 V ±10%

Symbol Min Max Unit Conditions
0

0.8

Other than ClK

Vll2

0.6

ClK

VIH1

2.2

CPU bus

VIH2

2.0

SCSI bus

ClK

SCSI bus

0.4

V
V

= 2.5 rnA; CPU bus
IOL2 = 48.0 rnA; SCSI bus
IOH = -400 p.A; CPU bus
VI

Vlll

VIH3
Input
hysteresis

VHI

0.2

Controls data transfer between SCSI FIFO and
FIFO or between registers In the Indirect access
register block.

low-level
output
voltage

VOLl

Controls 8-bltlI6-blt conversion when host CPU
is set to 16-blt bus mode.

High-level
output
voltage

VOH

Low-level
Input
leakage
current

ILIL1

-10

p.A

ILIL2

-1.0

rnA VI

= 0 V; SCSI bus

ILIHl

p.A

= Vee; CPU bus

ILlH2

0.1

rnA VI

= Vee; SCSI bus

ILOL

-10

p.A

= OV; CPU bus

Comprises registers that can be directly
accessed from host CPU, such as command
register, status register, etc.

Indirect access
registers

Comprises registers that cannot be directly
accessed from host CPU, but that can be
accessed through the window In the direct
access register.
This 16-blt, elght-stage asynchronous FIFO
Increases usage rate of host bus. In 8-blt mode,
only the lower 8 bits are used; In 16-bit mode,
accessing In 8-bit units Is not possible.

Interrupt control

Sets/resets Interrupt request signal.

Read/Write
control

Controls read/Wrlte operation of variOUS Internal
registers; also controls 8-blt accessing In 16-blt
mode.

Bus-size
converter

Converts bus size according to bus mode.

6-74

-0.5 to +7.0 V

Supply voltage, Vee

3.9

Direct access
registers

FIFO data
buffer

Absolute Maximum Ratings
TA = +25°C

High-level
Input
leakage
current
low-level
output
leakage
current

VOL2
2.4

IOL 1

= OV; CPU bus

NEe

#AoPD72111

DC Characteristics (cont)
Parameter
High-level
output
leakage
current
Supply
current

Symbol

AC Characteristics; CPU Bus Interface

TA = -10 to +70'C; Voo = +5.0V ±10%; see figure 1 for timing
measurement voltage thresholds

Min Max Unit Conditions

ILOH1

p.A

= Voo; CPU

ILOH2

0.25

rnA

= Voo; SCSI bus

100

rnA

At 16 MHz

bus

Parameter

Symbol Min Max Unit Conditions

Clock (figure 2)
ClK input cycle time
ClK input high-level width
ClK input low-level width

Capacitance
TA = +25'C; Voo
Item

= 0 V; f

= 1 Mhz

Symbol Min Max

Input
capacitance

Unit

Output
capacitance

Input/output
capacitance

CI01

C102

100

Conditions
CPU bus; unmeasured
pins at 0 V.

SCSI bus
interface pins

2.2 V
0.8V

2.0 V
O.BV

IKKH

IKKL

ClK input rise time

IKR

ClK input fall time

IKF

Reset (fIgure 3)
RESETIow-level width

lRSRSL

tcVK

~ set time to lORD .j.

tSCSR

~holdtime
from lORD t

~Res

SCSI bus; unmessured
pins at 0 V.

Address set time
to IORD.j.

tsAR

Address hold time
from lORD t

~RA

DMAAK set time to

CPU Bus RflBd (figure 4)

Figure 1. VoItIllJB Thresholds for Timing
Measurements
CPU bus
interface pins

tcvK

lORD ~

DMAAK hold time from lORD

lORD low-level width
lORD t to data output

tsoAR

~ROA

lRRL

toRO

ns
50

delay time

)C
83SL·6047A

lORD t
lORD t

to data float time

to I5IiMRt'i
delay time

IFRO

toROQ

CPU Bus write (figure 5)

Figure 2. Clock Timing

~ set time to IOWR .j.

tsesw

~ hold time from IOWR

tHweS

tsAW

~WA

DMAAK set time to IOWR .j.

tsOAW

DMAAK hold time from

~WDA

twWL

tsow

~WD

t
Address set time to IOWR .j.

Address hold time
from IOWRt
elK
tKR
83SL--6048A

IOWRt
IOWR low-level width
Data set time to IOWR
Data hold time from

Figure 3 RESET IHtvetorm

~=l.

tRSRSl

IOWR t to .DMARC:.l
delay time

IOWR t

toWOQ

Other CPU Bus (figure 6)

IOWR t

to lORD .j.
or IOWR t recovery time

'R-Iw

83SL-6049A

6-75

t-{EC

"PD72111
AC Characteristics; CPU Bus Interface (cont)
Parameter

lCRD i to 1OFiI) ~ or lOWFt ~

Symbol Min Max Unit Coridltlona
tAIR

recovery time

lCRD i
TOWR i
JOFm i
TOWR i

Symbol Min Max Unit Condlt~a
tDSLAT

tcVK

SSY' i to SSY' .j. output
delay time

toBVB1'3 10

tcVK

ID hold time from SSY' .j.

ItiBl'l02 0
ItiBVSL2 0
toSLBY 2

ns
ns

delay time

to EOJS ~ delay time

tOREP

to Ems .j. delay time

toWEP

to INT .j. delay time

tORI

to I NT .j. delay time

toWi

INT low-level width

Paramater

m i to AfIil output

"IL

40
2

ns
tcYK

m hold time from §SY .j.
SEE i to SSY'i output
delay time

tcVK

"...lfIt:fltlll . . ,.",., (IIgure 11)

AC Characteristics; SCSI Bus Interface
TA - -10 to +~C; VOO = +5.0 V ±10%; see figure 1 for timing
measurement Voltage thl'fisholds

i to ID output delay time

1osL102 20
toscra 0

SEE .j. to target output delay
time

tcVK

Symbol Min Max Unit Conditions

ID output to TJo output delay
time

101010

Bus free detection to
SSY' response time

toBFBY 14

flO Input to SSY' i

tolOBY

tcVK

SSY' .j. to ID output
delay tiMe

toBYIO

tcVK

SSY' .j.toSEE.j.
delay time

toBYSL 36

toBVSL2 2

tcVK

Paramater

AlbIt,.,1on (tigure 7)

tcVK

output delay

time

§SY i to §SY .j. Input valid delay toBYBY4

time

m i output delay

tcVK

§SY .j. to

tcVK

IltIcIIpIIon _Inltliltor In
nrodIt; dtltHn.
.'.w.."""
",...""..,n """".. (IIgure 12)

s.let:Iltin _Inltliltor fBIwre B}

time

SEE i to ID output
delay time

toSLI01 20

SEC.j.to~Am

IoSlAK 20

m i to phase Input valid delay toSLPH1

tcVK

TIO .j. to data float delay time
Phase. set time to REO .j.

SSY' i toSSY' .j.
Input valid delay time

toBYBY1 8

tcVK

Data set time to Rm .j.
REO .j. to ACR .j. output delay

SSY' .j.toSECi
output delay time

IoBYSL1 2

output delay time
~

ATR output to

SSY' i delay time

toAKBY

time
tcVK

s.let:IltIII_ ,.",., (tIgure 9)
§SY hold time from SEE ~

ID set time from §SY 1

ftiSLBY1 0
tslOBY 0

SSY' 1 to SSY' ~ output delay time toBYBY2 10

ns
ns
ns
ns

time

ns
ns
tcVK

fRo01

tsPtiRQ1 400
tsORQ1 5
toR0AK1 0

Osta hold time from ACR .j.

Itwco1

Rm hold time from ACR .j.

Itw

tDROAK5

J
tHAKR02

ACK

49TB-457B

Figure 15. SCSI Bus; Reception liS Tllrget In Async Mode

...--.
1/0

tFIOD2

_tSDAK2_

1"-

1 _ tHAKPH4

. . - - - tSPHR04_1

CtD,
MSG

)

---

tDROAK6
REO

tDAKR03
ACK

C
tHROAK2

_ t D A K R04

\
4918·4588

6-83

ttiEC

"PD72111
Figut8 1t1. SCSI Bus; Reception

.s Inltl.tor in Sync Mode

SEL-L
IIOSLPH5

:IISDR03
Hi-Z

i
l(
X'---_
----~I~::::~~JI:~R-O-03----------~

vo
c/o,
MSG ________~~----------------~----------------------~~
i+-----'-ISPHR05----+i
REO

ACK

49TIH59B

Figut8 17. SCSI Bus; Transfer.s T.rget In Sync Mode

SEL-L
10SLPHS

_ISOR04,

Hi-Z

1_---+1 101003

vo
c/o,
MSG ________~

______________~--------~------------._~

_ISPHROS_

49TB-46OB

6-84

ftt{EC

#,PD72111

Figure 18. SCSI Bus; Transfer as Initiator in Sync Mode
SEL

____~I_·___·)(H-A-KD-3-----

j~tD-IO-D-4-------"""~

,I tSDAK3

110

CID,

MSG _ _ _ _ _

________________________________

~----~~

REO

ACK

49TB-461 B

Figure 19. SCSI Bus; Reception as Target in Sync Mode

____~I_'___·)(H-A-KD-4-----

Hi-Z

-<. . .----~

,I tSDAK4

110

CID,

MSG ________

___________________

~--~~

REO

ACK

49TB-4628

6-85

ttlEC

"PD72111
Figure 20. SCSI Bus; Arbltl'lltion, Bus Free

1~-~tFSlIO
Hi-Z

Hi-Z
SBO-SB? -

1>--------

Figure 21. SCSI Bus; Selection/ReSelection, Bus Free

SEL

Hi-Z

Note:
ATN or ACK output by Initiator, or

iio, Cio, MSG, or REO output by target.

DIRECT ACCESS REGISTERS

Table 1. Direct Access Registers (coni)

Table 1 lists the 10 internal registers that can be directly
accessed from the host CPU. The register address Is
specified by pins A2-Ao.

Addre.. ArAo

7lIbie 1. Direct Access Reglst.,..
Acldre.. tvAo

R/W

Symbol

000

R/W

DFL

Data FIFO

001

R/W
R

DFH

010

CST

Controller status

011

R/W

ADR

Address

100

R/W

WlN1

Window

101

R/W
R

WlN2

Terminated phase

DID

Destination 10

110

6-86

111

R/W
R

Symbol

1ST

Interrupt status

CMD

Command

Data FIFO Register
The 16-bit data FIFO register (figure 22) is used to write
or read data (including command, status, and message
data) accessed through the SCSI bus.
In the S-bit mode, only the lower S-bit DFL register at
address OH is used. The contents of the upper S-bit DFH
register at address 1H are fixed to DOH.
In the 16-bit mode, the register is accessed to/from
address OH with signals Ao = 0 and USE = O. When data
is sent to the SCSI data bus, the DFL contents are output

t-IEC

"PD72111

first, followed by the DFH contents. When data is sent,
the first byte fills DFL and the second byte fills DFH.
The data FIFO register empties when a RESET signal is
input, the CHIP RESET command is executed, or the
CLEAR FIFO command is executed.

Figure 22. DFL and DFH Regi.'e,.

Figure 23. CST Regi.,e,
7
2H

OFH

CBSY

,.PDnll1 Command Execution Status

Idle (waiting for a command or executing a type
A command
Busy (executing type B or C command)

INTRQ

CPU Interrupt Request

Not generated
Generated

16·Blt Mode
OFH
OH

015

014 I 013 I 012 I 011

010

OFL
07

8·Blt Mode
OFL

CST1, CSTO

,.PDnlll Operating Condition

o
o

Disconnected state
Initiator state
Target state

ATNC

ATN Pin Status

Inactive(high level)
Active Oow leveQ

Controller Status Register
The 8·bit CST register (figure 23) indicates the operating
condition of the ~PD72111. This is a read· only register;
data written to CST becomes invalid.
The value of the CST register becomes 82H when a
RESET signal is input or the CHIP RESET command is
executed.

I CBSY IINTRCI CST1 I CSTO I ATNe FFUL I FEMP I ORC I

FFUL, FEMP

FIFO State

o
o

Neither full nor empty
Empty
Full

0
1
()

ORQ

DFLJDFH Register

Accessing OFLJDFH is disabled
Writing to or reading from OFLJDFH Is requested

Figure 24. ADR Regi.te,

Address Register
When accessing an indirect access register, the address
should beset to the 8-bit ADR register and the window
register (WIN1, WIN2) accessed. Bit 7 of ADR (figure 24)
specifies the mode and bits 5-0 specify the address ofthe
Indirect access register.
In the auto-Increment mode, each access automatically
increments the contents of the lower 6 bits of ADR (+ 1
for the 8-bit bus mode, +2 for the 16-bit bus mode).
The ADR register is reset to OOH by a RESET signal or by
execution of the CHIP RESET command.

7
3H

IAINC I

Read/Write
0

I ADR51 AOR41 AOR31 AOR21 AORl I AORO

AINC

Mode for Accessing an IndlreC1tAccess Register

Normal mode (address in not automatically updated
Auto-increment mode (address is automatically updated)

ADR5-ADRO

Indirect Access Reglstar Address

000000

OOH

111111

3FH

Window Register
The window register (figure 25) comprises two 8-bit
registers used as a window for accessing the indirect
access registers. With the ~PD72111 in the 8-bit mode,
WIN1 and WIN2 are accessed to/from addresses 4H and
5H, respectively.

6-87

ttlEC

"PD72111
In the 16-bit mode; WlN1 and WIN2 function as one 16-bit
register accessed to!from address 4H. WIN1 and WIN2
hold the least- and most-significant bytes of the word,
respectively. According to the settings of signals Ao and
UBE, either or both registers can be accessed.

&JOSE

Address Register Accessed
~ WIN1, WIN2
4H
WlN1
WIN2
5H

o o
o 1
1
o

Figure25.

WlN1 and WlN2 Regls,.rs

014

013 1 012 1 011

010

WlNl
07

05 1 04 1 03

1 02

TP7-TPO

Command

execution Phase

0000 0001

SCSI RESET

SCSI reset

0001 0001

SELECT

TRANSFER

Information transfer

0011 0001

AUTO
INITIATOR

Arbitration

0011 0011

Terminated Phase Register
The 8-bit TP register (figure 26) indicates the phase
executed when a command execution is terminated.
The TP register is reset to OOH by a RESET Signal or by
execution of the CHIP RESET command.

Identify messsge transmit
Command transmit

0011 0101

Data transmit/receive

0011 0110

Status receive

01000001
01

Target selection

0011 0100

WlNl
02

Arbitration
Target selection

00100001

0011 0111

04 1 03

Read Only

1 TP7 1 TP6 1 TP5 1 TP4 1 TP3 1 TP2

8·Blt Mode

WlN2
5H

0011 0010

WlN2
015

TP Regis'.r

0001 0010

la-Bit Mode
4H

Figure 26.

Command complete message receive
RESELECT

Arbitration
Initiator reselection

01000010

Information receive

0101 0001

RECEIVE

01100001

SEND

Information tJansmlt

0111 0001

AUTO
TARGET

Selected waiting

RE-RECEIVE

Arbitration

0111 0010

Identify messsge receive
Command receive

0111 0011
1000 0001
1000 0010

Initiator reselectlon

1000 0011

Identify messsge trensmlt

1000 0100

Data receive

Destination ID Register

1001 0001

Bits 2'() of the DID register (figure 27) set the 10 of the
target to be selected or the initiator to be reselected. Bit
7 of DID can be set to mask the interrupt request signal
(INT). The INTRQ bit of the CST register (figure 23)
Indicates whether the INT signal was generated or not.

1001 0010

Initiator reselectlon

1001 0011

Identify message transmit

1001 0100

Data transmit

Zeros must be written to bits 6-3 of the DID register.

Arbitration

Figure 27. DID Regis'.r
~~--------~--------------------7
Write Only
0
6H

6-88

RE-SENO

IINTM 1 0

1 0

1 0102 1 0101

DIDO 1

INTM

Interrupt Request Signal Mask Function

Does not mask Interrupt request ONT signal Is output
when Interrupt is generated
Masks Interrupt request ONT signal is not output even If
Interrupt request is generated

0102·0100

Setting 10 of SCSI Device 1b Be Selected

000

111

NEe

"PD72111

Interrupt Status Register

Table 20 Indltet:t Access Registers (cont)

The read-only 1ST register (figure 28) indicates the cause
of the interrupt request. If the current contents of 1ST are
not read out, they are retained and 1ST is not updated for
new interrupt generation.

Addre..

R/W

Symbol

24H

R/W

MOD

25H

R/W

PID

Similarly, if the previous contents were not read out, 1ST
would not have been dated for the current interrupt;
however, the current interrupt data would be retained
elsewhere internally.

26H thru 3FH
Reserved
R = Read only; W = Write only; R/W - Read/Wrlte

Bit 7 of the 1ST register indicates the group of the
interrupt request generation source. The contents of bits
6-0 depend on the value of bit 7.
The 1ST register is reset to OOH by a RESET signal or by
execution of the CHIP RESET command.

Command Register
The 8-bit CMD register (figure 29) is used by the CPU to
write commands to the #,PD72111. Commands are described later in table 3.

INDIRECT ACCESS REGISTERS
The 27 registers listed in table 2 can be directly accessed
by the CPU through a window in a direct access register.
The register address is specified by the lower 6 bits of the
ADR register (figure 24).

Table 20 Indltet:t Access Registers
R/W

Symbol

OOH

TST

Target status

01H

SBST

SCSI bus status

SID

Addre..

02H
03H
04H thru
OFH

MSG
R/W
R/W CDeoo

Source 10
Message
Command descriptor block

thru CDB11

10H

R/W

TMOD

Transfer mode

11H

CTCl

Current counter Oower 8 bits)

BTCl

Base counter Oower 8 bits)

CTCM

Current counter (middle 8 bits)

BTCM

Base counter (middle 8 bits)

CTCH

Current counter (upper 8 bits)

BTCH

12H
13H
14H thru 1FH

Base counter (upper 8 bits)
Reserved

20H

R/W

BFTOUT

Bus free timeout

21H

R/W

SRTOUT

Selectlon/reselectlon timeout

22H

R/W

RATOUT

~ handshake timeout

23H

R/W

CDBl

Command descriptor block length

6-89

NEe

#,PD72111

Figure 28. 1ST Register
7
7H

Figure 29. CMD Register

Write Only

I SRI IIST6 IIST5 IIST4 IIST3

IST2

ISTI IISTO I

SRI

Interrupt Request Type

Interrupt request caused by command termination
(normal termination or abort)
Interrupt request caused by service request issued to
CPU

SRI

o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o

IST6·ISTO

Interrupt Request Generation Source

Write Only

I CMD71 CMD61 CMD51 CMD41 CMD31 CMD21 CMDI I CMDO I

Target Status Register
The TST register (figure 30) stores the status byte of the
target received in the status phase during execution of
the AUTO INITIATOR command.

000

Command normallermination

000

001

Command break

001

000

Invalid command

010

000

FIFO overrun/underrun

010

001

Synchronous offset error

010

SCSI bus parity error

010

011

CPU bus parity error

SCSI Bus Status Register

010

100

Bus free ti me-out error

010

101

Selection/reselection timeout error

The SBST register (figure 31) indicates the status of each
signal on the SCSI control bus.

010

110

REQJ:i\CR timeout error

011

000

Data-out phase error

011

001

Data-in phase error

011

010

Command phase error

011

Status phase error

Status of Each Pin

011

110

Message-out phase error

011

111

Message-in phase error

Unsupported SCSI command group

Figure 30.

TST Register

Read Only

OOH L..I_ _ _ _ _ _ _T_ST_ _ _ _ _ _---'I

Figure 31. SBST Register
7

Read Only

01H I BSY I SEL I REO lACK I ATN I MSG I C/D

I/O

Inactive (high level)
Active(low leveQ

100

000

Reset

Source 10 Register

000

001

SCSI reset condition occurred

001

000

Disconnected

001

Reselected

The read-only SID register (figure 32) stores the ID of the
last SCSI device that selected the ~PD72111. Bits 6-3 are
always read out as zeros.

001

010

Selected

010

000

Data-out phase started

010

001

Data-in phase started

010

a1a
a11

Status phase started

010

110

Message-out phase started

010

111

Message-in phase started

100

000

Message received

Figure 32. SID Register

Read Only

Command phase started

AT bit is valid in ta rget mode only. It shows whether attention condition
has occurred (AT = 1) or not (AT = 0).

6-90

7
7H

o I

I SID2 I SIDI I SIDO I

SIR

"P072111 Select/Reselect Operation

Has neither been selected nor reselected (contents of
SID2-8IDO are invalid)
Has been selected or reselected (contents of SID2-8IDO
are valid)

S102·
SIOO

10 No. of Last SCDI Device That Selected "PD72111

000

111

NEe

I'PD72111

Message Register

Figure 35. TMOD Register

The MSG register (figure 33) sets transmit messages or
stores receive messages when the ILPD72111 is transmitting or receiving.

Figure 33. MSG Register
ReadiWrite

03H !'--_ _ _ _ _ _M_S_G_ _ _ _ _ _....J!

ReadiWrite

10H ! SYNC TP021 TP01 ! TPOO!

ITOF21 TOF1 ! TOFO!

SYNC

Data Transfer Mode

0
1

Asynchronous mode
Synchronous mode

TPD2TPDO

Cycles for Sync Mode

Transfer Rate (at 16 MHz)

000

16 clock cycles

1.00 Mbytes/s

001

Command Descriptor Block

010

4 clock cycles

4.00 Mbytes/s

The 12 COB registers (figure 34) set/store the command
descriptor blocks of SCSI commands.

011

6 clock cycles

2.67 Mbytes/s

100

8 clock cycles

2.00 Mbytes/s

Figure 34. CDS Registers

101

10 clock cycles

1.60 Mbytes/s

110

12 clock cycles

1.33 Mbytes/s

111

14 clock cycles

1.14 Mbytes/s

lfEtl, AUK Pulse Offset Value for Sync Mode

ReadiWrite

04H

COBOO

05H

COB01

TOF2TOFO

06H

COB02

000

111

07H

COB03

OSH

COB03

OSH

COB04

OAH

COB06

OBH

COB07

OCH

COBOS

OOH

COBOS

OEH

COB10

OFH

COB11

Transfer Mode Register
The TMOD register (figure 35) sets the mode for data
transfer. Zero must be written to bit 3.

Current Counter
The 24-bit CTC register (figure 36) counts the number of
data bytes transferred in the information transfer phase.
This is a read-only register; data cannot be written to it.
During execution of an information transfer command.
the CTC counter is loaded with the values in the BTC
base counter. The values loaded from BTC to CTC are
controlled by count select bits C1 and CO of the command code (table 5).

Figure 36.

err: Register

11H

12H
13H

Read Only

Base Counter
The 24-bit BTC register (figure 37) sets the number of
data transfer bytes to be loaded into the CTC current
counter. This is a write-only register; the contents cannot
be read out. The count values written to BTC are controlled by count select bits C1 and CO of the command
code. (table 5).

Bus Free Timeout Register
The BFTOUT register (figure 38) sets the bus free timeout. If DOH is written to this register, the timeout detection
function will not operate.

6-91

NEe

#,PD72111

REQ/ACK Handshake Timeout Register

Figure 37. BTe Registel'
7
Write Only
0
.---------B-TC-L.-..::..---------,

llH
12H

BTCM

13H

BTCH

The RATOUT register (figure 40) sets the timeout for
handshake operation of REQ and ACK signals during
information transfer. If OOH is written to this register, the
timeout detection function will not operate.
Figure 40. RATOUT Regilltel'

BTCH

BTCM

BTCL

OOH

FFH

255

OOH

01H

OOH

256

Number ()f !)ata Trenafer Bytea

OOH

FFH

65,635

01H

OOH

65,636

FFH

16,m,215

20H

Read/Wrlta

BFTOUT

Bua Free Timeout (at 16 MHz)

OOH

No timeout detection Is performed

01H

8.192 ms

FFH

2088.928 me

RATOUT

~ Timeout (at 16 MHz)

OOH

No timeout detection is performed

01H

128/.18

FFH

32,640"s

The COBl register (figure 41) sets parameters for the
group 6 and group 7 SCS I commands (vendor unique) of
the SCSI specifications by using the AUTOINITIATOR
command and the AUTO TARGET command.
Figure 41. COBL Regilltel'
7

Read/Wrlte

CL73oCL70

Group 7 SCSI Command; CDB Length
1 byte

Selectlon/Reselectlon Timeout Register
The SRTOUT register (figure 39) sets the timeout for the
selection or reselection operation. If OOH is written to this
register, the timeout detection function will not operate.

1100
1101

12 bytes
boes not support group 7 SCSI commands
(generates unsupported group command erro~

1111

Figure 39. SRTOUT Reglstel'

0000

Read/Write

SRTOUT

CL63-CL60
0001

SRTOUT

Selilctlon/R.aelactlon Timeout (at 16 MHz)

1100

OOH

No timeout detection Is performed

1101

01H

8.192 ns

FFH

2088.928 me

1111

6-92

~lc~lc~I~I~I~~I~~I~~I~~1
0001

21H

Command Descriptor Block Length Register

Figure 38. BFTOUT Reglstel'
7

Read/Wrlte

RATOUT

22H

0000

Group 6 SCSI Command; CDS Length
1 byte

12 bytes
Does not support group 6 SCSI commands
(generates unsupported group command erro~

NEe

I'PD72111

Mode Register

Figure 43_ PIO Register

The MOD register (figure 42) sets the p.PD72111 operation mode.

25H

Figure 42_ MOO Register

ReadJWrite

I FEN I

FE N

Controller Operation

Does not operate as Initiator

Operates as initiator
"PD72111'. Own ID Number

Data Transfer Mode (In data-In/data-out phase)

PID2PIDO

Program I/O mode

000

DMAmode
111

7
24H

ReadJWrite

I DMA I HP8 I DHP I D8P I NAM 181M IRAEN ISAEN I

DMA

HPS

DHP

CPU Bus Parity

o
o

Odd parity

x
DSP

Even pa rity
Disable parity

SCSI Bus Parity
Enable (even parity only)
Disable parity

I PID2 I PID1 I PIOO I

COMMANDS
Descriptions
The CPU controls the p.PD72111 with the 16 commands
described in table 3. Commands are listed in groups
according to mode-initiator/target, initiator, and target.

NAM

SIM

Bus Arbitration execution

Arbitration mode

Command Code

Non-arbitration mode (non..slngle-initiator mode)

Table 4 gives the command code, status, and type for
each command.

Non-arbitration mode (single-initiator mode)
RAE N Responss (when reselected as Initiator by target)

Does not respond
Responds

SAEN

Hesponss (when re.elected a. terget by Initiator)
Does not respond

Command Bits. Symbols for command bits in table 4
are explained below.
Symbol
C1, CO
AT

Responds

MG, CD

Physical ID Register
The PID register (figure 43) sets the p.PD72111 's own
physicallD on the SCSI system. Zeros must be written
to bits 6-3.

Function
Count select bits
ATN signal status selection bit. (1 means
the initiator is requesting the message-out
phase.)
Transfer information specification bits

The function of count select bits C1 and CO is to specify
the value loaded to the current transfer counter: This can
reduce the overhead of modifying the transfer counter:
See table 5.
Status. Table 4 specifies the status in effect when the
command is issued. Symbols are explained below.
Symbol
D
I
T

Status
Disconnect
Initiator
Target

Type. Table 4 classifies commands as type A, B, or C
according to the execution status defined under
"p.PD72111 Processing" below.

6-93

NEe

#,PD72111

Table 3. Command Functions
Mode

Command Name

Mnemonic

Function

Initiator or Target

CHIP RESET

CRST

Resets "PD72111 using software.

BREAK

BRK

Discontinues command execution.

DISCONNECT

DIS

Releases SCSI bus.

CLEAR FIFO

CLRF

Clears FIFO

SCSI RESET

SRST

Resets SCSI bus.

Initiator

Target

SET ATN

SETAT

Sets ATN signal.

RESET ACK

RSTAK

Resets ACK signal.

SELECT

SEL

Selects a target.

TRANSFER

TFR

Sends/receives data On initiator mode).

AUTO INITIATOR

AIN

Automatically executes initiator standard operation.

RESELECT

RSEL

Reselects initiator

RECEIVE

REC

Receives data On target mode).

SEND

SND

Sends data On target mode).

AUTO TARGET

ATG

Automatically executes target standard operation.

RE-RECEIVE

RREC

Reselects -

Continuous execution of data-receive operation

RE-SEND

RSND

Reselects -

Continuous execution of data-send operation On target mode)

Table 4. Command Codes
Command Name

Table 5. Loading the Current Transfer Counter

Command Code

CHIP RESET

0 0

BREAK

0 '0

CLEAR FIFO

o0
o0
o0

SCSI RESET

0 0

SET ATN

o
o

0
0

o
o

Cl CO 0

DISCONNECT

RESETACK
SELECT
TRANSFER

RES ELECT
RECEIVE

Cl CO

SEND

Cl CO

AUTO TARGET

Cl CO

RE-5ENO

Cl CO

Status Type

D,I, T

o
o

MG CD 0

MG CO

RE-RECEIVE

o
o
o

AUTO INITIATOR Cl CO 0

A
B

o
o

Table 5. Loading the Current Transfer Counter
C1

Load Operation
CTCH/M/L

BTCH/M/L

Counting Range

oto 16,776,960 bytes In
I-byte units

6-94

CTCH/M
CTCL

Qn target mode)

- BTCH/M
-OOH

oto 16.776.960 bytes in
256-byte units

Load Operation

Counting Range

CTCH/M
CTCL

- OOOOH
- BTCL

oto 256 bytes In I-byte

CTCH/M/L

- 00000IH

Single-byte only

units

p.PD72111 PROCESSING
Processing by the p.PD72111 is in either of two categories:
• Command processing initiated by a command from
the CPU
• Response processing executed by the SCSI bus status transition

Command Processing
Command processing operations differ depending on
the command executed.
Type A Command. Except for CHIP RESET, the command is immediately executed. Then, a new command is
awaited.
CH IP RESET Command. The /-IPD72111 is immediately reset, after which an interrupt request is generated.
Type Band C Commands. The issued command is
synchronized with the system clock and executed. After
the command is executed, an interrupt is generated.

ttlEC

p.PD72111

Response Processing

Figure 45. Interrupt Prot:eaing Row

When selected or reselected by another device, response
processing for the device is executed. If the bus status
changes during information transfer, the bus phase after
the transition is detected and reported. The ~PD72111
generates an interrupt upon completing the response
processing.

HOST CPU PROCESSING

Processing by the host CPU for the ~PD72111 is in either
of two categories.
• Command Issuance processing by request from the
CPU side. See figure 44.

Execute processing according ID

>~-+ request Indicated by 1ST register.

>-N_O_ _ Execule processing according
ID generated error.

• Interrupt processing generated when the operation
specified by the command is completed, or the SCSI
bus status changes. See figure 45.
Figure 44. COIIItnIInd

._nt:e

Prot:ealng Row

Mask interrupt request
and write dala to be set
to register in advance.

49T&491A

6-95

#£PD72111

6-96

NEe

t-IEC

LCD CONTROLLERS

7-1

NEC

LCD Controllers

Section 7
LCD Controllers
"PD7225
CMOS, Intelligent Alphanumeric LCD
Controller/Driver

7-3

"PD7227
CMOS, Intelligent Dot-Matrix LCD
Controller/Driver

7-13

"PD7228/28A
CMOS, Intelligent Dot-Matrix LCD
Controller/Driver

7-21

7-2

f'tiEC

pPD7225
CMOS, Intelligent, Alphanumeric
LCD Controller/Driver

NEe Electronics Inc.
Description

Pin Configuration

The /-IPD7225 is an intelligent peripheral device designed to interface most microprocessors with a wide
variety of alphanumeric LCDs. It can directly drive any
static or multiplexed LCD containing up to 4 backplanes
and up to 32 segments and is easily cascaded for larger
LCD applications. The /-IPD7225 communicates with a
host microprocessor through an 8-bit serial interface. It
includes a 7-segment numeric and a 14-segment alphanumeric segment decoder to reduce system software
requirements. The /-IPD7225 is manufactured with a low
power consumption CMOS process allowing use of a
single power supply between 2.7Vand 5.5V.lt is available in a space-saving 52-pin plastic flat package.

Ordering Information
Max Frequency

Part Number

Package Type

of Operation

IIPD7225G-OO

52-pin plastic miniflat

1 MHz

NECEL-000488

521

5:12

523

527

50
S:J
5:1
51
So

528

COM3

5 ..

COM2

5:1.
525

5 ..

5..,

COM,

531

COMo

CLI

Features
D Single chip LCD controller with direct LCD drive
D Low cost serial interface to most microprocessors
D Compatible with
- 7-segment numeric LCD configurations
up to 16 digits
- 14-segment alphanumeric LCD configurations
up to 8 characters
D Selectable LCD drive configuration:
- Static, biplexed, triplexed, or quadruplexed
D 32-segment drivers
D Cascadable for larger LCD applications
D Selectable LCD bias voltage configuration:
- Static, 1/2 or 1/3
D Hardware logic blocks reduce system software
requirements
- 8-bit serial interface
- Two 32 x 4-bit static RAMs for display data and
blinking data storage
- Programmable segment decoding capability:
- 16-character, 7-segment numeric decoder
- 64-character, 14-segment USASCII
alphanumeric decoder
- Programmable segment blinking capability
- Automatic synchronization of segment drivers
with sequentially multiplexed backplane
drivers
D Single power supply, variable from 2.7V to 5.5V
D Low power consumption CMOS technology
D Extended - 40°C to +85°C temperature range
available

520

8J.O02798A

Pin Identification
No.

Symbol

Function

CL2

System clock output

SYNC

Synchronization port

3-5

VLCD1VLCD3

LCD bias voltage supply inputs
Ground

Vss

7,33

VDD

Power

SCK

Serial ciock input

Serial input

Chip select

BUSY

Busy output

C/O

Command or data select input

RESET

Reset input

No connection

15-18

COMo-COM3

LCD backplane driver outputs

19-32, 34-51

SO-S31

LCD segment driver outputs

CLI

System clock input

NEe

",PD7225
Pin Functions

COMo-COMa

Chip select input. Enabies the ~PD7225 for data input
from the microprocessor. When CS is deselected, the
display can be updated.

LCD backplane driver outputs.

So-Sa1

SYNC

LCD segment driver outputs.

Synchronization port. For multichip operation, tie all
SYNC lines together.

VLCD1-VLC03
LCD bias voltage supply inputs to the LCD voltage controller. Apply appropriate voltages from a voltage ladder
connected across Voo.

CL1

CL2

Serial input from the microprocessor.

System clock output. Connect CL2 to CL1 with a 180 kQ
resistor, or leave open.

SCK
Serial clock input. Synchronizes 8-bit serial data transfer from the microprocessor to the ~PD7225.

BUSY
Handshake output indicates the ~PD7225 is ready to receive the next data byte.

c/o
Command/dataselect input. Distinguishes serially input data byte as a command or as display data.

7-4

System clock input. Connect CL1 either to CL2 with a
180 kQ resistor, or to an external clock source.

RESET
Reset input. Ric circuit or pulse initializes the ~PD7225
after power-up.
VDO
Power supply positive. Apply single voltage ranging
from 2.7 to 5.5 V for proper operation.

Vss
Ground.

fttfEC

J.tPD7225

Block Diagram
COMo-COM3

LCD Driver
32
Display Latch

32
32

VDD
VLCDI
VLCD2
VLCD3

LCD
Voltage
Controller

32.4Bll

Segment
Decoder

Display RAM

32.4Blt
Blinking RAM

VSS

CC~L21 ~L.
~

_____
a_OC
__
k ____

Oscillator

RESET _

Buffer

Interface
Controller

Command
Decoder

Sarlallnterface

C/O

iiiliY

SCK
83<103379B

7-5

t'tIEC

J-tPD7225
Absolute Maximum Ratings

DC Characteristics (cont)

TA=25°e

TA'= - ooe to + 70°C, VDD = +2.7V to 5.5 V
Limits

-0.3Vto +7V

Power supply voltage, Voo

Parameter

Output voltage, Vo

-0.3VtoVoo +0.3V

Input voltage
low

Vill

0.3 Voo

Except SCK

VIl2

0.2 Voo

SCK

Input voltage
high

VIHI

0. 7Voo

Voo

Except SCK

VIH2

0.8 Voo

Voo

SCK

Output voltage
low

VOL1

0.5

BUSY, IOl = 100 flA

VOl2

0.5

IOl =400 "A,
SYNC

Output voltage
high

VOH

BUSY, SYNC,
IOH=-7flA

Input leakage
current low

ILil

flA

Vil =0 V

Input leakage
current high

ILiH

flA

VIH=VOO
VOL = 0 V

-10°C to + 70°C
- 65°C to +150°C

Storage temperature, TSTG

Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits de·
scribed in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.

DC Characteristics
TA = -10°C to + 70°C, VDD = +5 V ±10%
Limits
Parameter

Symbol

Input voltage
low

Vil

Input voltage
high

VIH

Output voltage
low

Output voltage
high

VOH

Input leakage
current low

ILil

Input leakage
current high

ILiH

Output leakage
current

ILOl

Output short
circuit current

Typ

Max

Unit

0.3 Voo

Test
Conditions

Output leakage
current

Voo

VOL1

0.5

BUSY, IOl =1OOflA

VOl2

1.0

10l = 9OO I-'A,

0. 7Voo

SY'NC
Voo
-0.5
-2

-2

ILOH
-300

los

Backplane
driver output
impedance

RCOM

Segment
driver output
impedance

RSEG

Supply current

Min

100

250

BUSY, SYNC.
IOH= -10flA

I-'A

Vil =OV

I-'A

VIH=VOO

I-'A

VOL =OV

I-'A

VOH=VOO

I-'A

SYNC, Vos=1.0V

COMO-COM3,
VOO>VlCO
(Note 1)

I-'A

SO-S31,
VOO>VlCO
(Note 1)
CL1 external clock,
f+=200kHz

Note:
(1) Applies to static-, 112·, and 1/3-LCD bias voltage schemes.

Min

Test
Conditions

-0.3VtoVoO +0.3V

Operating temperature, TOPT

Symbol

Typ

Input voltage, VI

Max

Voo
-0.75
-2

ILOl

-2

flA

ILOH

flA

VOH=VOO

Output short
circuit current

los

-200

flA

SYNC, Vos=0.5V

Backplane
driver output
impedance

RCOM

COMo-COM3,
VOO>VlCD
(Note 1)

Segment
driver output
impedance

RSEG

SO-S31,
VOO>VlCO
(Note 1)

Supply current

100

I-'A

CL1 external clock,
Voo=3.0V ±10%,

100

f~=140kHz

Note:
(1) Applies to static-, 1/2-, and 1/3-LCD bias voltage schemes.

Capacitance
TA = 25°C, f+ = 1MHz
Limits
Parameter

Symbol

Min

Typ

Max

Unit

Test
Condilions(1)

Input
capacitance

Output
capacitance

C01

CO2

BUSY

1/0
capacitance

GIO

SYNC

Clock
capacitance

G+

CL1 input

Note:
(1) All unmeasured pins returned to 0 V.

7-6

Unit

Except BUSY

NEe

IAPD7225

AC Characteristics
TA = -10De to + 70 De, VDD = +5 V ±10%
Limits
Parameter

Symbol

Clock frequency f,

lose

Min

TyP

50
85

130

Test
Conditions

Max

Unit

200

kHz

175

kHz

R=180 kQ+5%

t,WL

I'S

CL 1, external clock

Clock pulse
width high

t,WH

fls

CL1, external clock

SCK cycle

tCYK

900

SCK pulse width tKWL
low

400

SCK pulse width tKWH
high

400

ns
ns

SI setup time to t'SK
SCK t

100

SI hold time
after SCK t

tlHK

200

8th SCK t to
BUSY + delay
time

tKOB

I'S

1.5

CS +to BUSY + tCOB
delay time
C/Ds~time

fls
I'S

tOSK

to 8th SCK t
tOHK

CS hold time
after 8th SCK t

tCHK

CS pulse width
low
CS pulse width
high

CL =50 pF

CL=50pF

lose
Clock pulse
width low

t,WL

Clock pulse
width high

t,WH

SCK cycle

I's
flS

tCWL

8/f,

tCWH

8/f,

flS
flS

Min

TyP

50
50

100

Test
Conditions

Max

Unit

140

kHz

140

kHz

R=180 kQ+5%,
Voo=3.0V ±10%

fls

CL1, external clock

I'S

CL1, external clock

tCYK

fls

SCK pulse width tKWL
low

1.8

fls

SCK pulse width tKWH
high

1.8

flS

BUSY t to SCK + tBHK
hold time

SI setup time to t'SK
SCK t

flS

SI hold time
after SCK t

t'HK

flS

8th SCK t to
BUSY + delay
time

tKOB

fls

CL=50pF

CS +to BUSY + tCOB
delay time

fls

CL =50pF

C/Ds~time

C/ Dhold time
after 8th SCK t

Symbol

Clock frequency f~

Clock pulse
width low

BUSY t to SCK + tBHK
hold time

Limits
Parameter

tOSK

fls

to 8th SCK t
C/ Dhold time
after 8th SCK t

tOHK

I'S

CS hold time
after 8th SCK t

tCHK

flS

CS pulse width
low

tCWL

8/f,

flS

CS pulse width
high

tCWH

8/1+

fls

SYNC load
capacitance

f,=200kHz

AC Timing Characteristics
All Inputs

All Outputs

\--_________ #

~'H
-------------:----------VIL

\:==========f-----------:.---~~~L
83·0027998

7-7

~EC

83-0028008

,- - --,

---- -'-

Sl--------------------~.r
I

I"
I

IDSK--------.l!.---IDHK~
C/D------~(~_______
- - - - )~-83·0028018

7-8

t¥EC

JAPD7225

Instruction Set (Note 1)
Command

Description

Mode Set

Initialize the "PD7225, including selection of:
1) LCD drive configuration
2) LCD bias voltage configuration
3) LCD frame frequency

Operation Code

Hel
Code

40-5F

Unsynchronous Data Transfer

Synchronize display RAM data transfer to display latch with CS

Synchronous Data Transfer

Synchronize display RAM data transfer to display latch with LCD
drive cycle

Interrupt Data Transfer

Interrupt display RAM data transfer to display latch

Load Data Pointer

Load data pointer with 5 bits of immediate data

0
0

EO-FF

DO-DF

d2
0

Clear Display RAM

Clear the display RAM and reset the data painter

Write Display RAM

Write 4 bits of immediate data to the display RAM location
addressed by the data pointer; increment data painter

AND Display RAM

Perform a logical AND between the display RAM data addressed by 90-9F
the data pointer and 4 bits of immediate data; write result to same
display RAM location. Increment data pointer

OR Display RAM

Perform a logical OR between the display RAM data addressed by
the data pointer and 4 bits of immediate data; write result to same
display RAM location; increment data pointer

BO-BF

Enable Segment Decoder

Start use of the segment decoder

Disable Segment Decoder

Stop use of the segment decoder

Enable Display

Turn on the LCD

Disable Display

Turn off the LCD

Clear Blinking RAM

Clear the blinking RAM and reset the data painter

Write Blinking RAM

Write 4 bits of immediate data to the blinking RAM location
addressed by the data pointer; increment data pointer

CO-CF

AND Blinking RAM

Perform a logical AND between blinking RAM data addressed by
the data pointer and 4 bits of immediate data; write result to same
blinking location; increment data pointer

SO-8F

OR Blinking RAM

Perform a logical OR between blinking RAM data addressed by the
data pointer and 4 bits of immediate data; write result to same
blinking location; increment data pointer

AO-AF

Enable Blinking

Start segment blinking at the frequency specified by 1bit of
immediate data

1A-1B

Disable Blinking

Stop segment blinking

0
0

do
0

Note:

(1) Details of operation and application examples can be found in the ~PD7225lntelligent Alphanumeric LCD Controller I Driver Technical Manual.

7-9

NEe

JAPD7225
Operating Characteristics
TA:25°C

External Resistance vs Oscillation Frequency

~ f---'-"'-+-"'~'
g200

140

""'_ _ _ _-+-_____ 1Cl2R C
Cll"

R=1~

......

..!'

Supply Voltage vs Oscillation Frequency

100~----}_------~~+-~~----------}_--_1

50 Lt~------t---~--po..,···:--l····
100

200

500

External Resistance R (kQ)

Supply Voltage vs Supply Current

100

I 50~--}_-----+-~~~--+-------1
~

I
201---+-----+-----1-------11

~~~----~------~------~~
Supply Voltage VOO (V)

7-10

/
so

~
R

Supply Voltage Voo (V)

~EC

J-lPD7225

7 ·Segment Numeric Data Decoder Character Set
Decoded Display RAM Data

Display
Byte

(HEXI
00

Character

OC
OD
OE
OF

n+l

n+1

A
6

B
5

B
0

a
B
B

a
8
a

Quadruplexed
Display RAM Address

n+2

Triplexed
Display RAM Address

6
0

7-11

~ 14·Segment Alphanumeric Data Decoder Character Set

Display
Byte
(HEX) Char.

Display RAM
Address

n+3

n+2

n+1

Display
Byte
(HEX) Char.

Invalid

B3
B4

Invalid

M
A5

Invalid

10
10
I"
10
10

n+3

I,
~

n+2

n +1

'I,

10
10
10
10

1::
Display
Byte
(HEX) Char.

Invalid

I,"
I

Invalid

it
I"
I"
110

Display RAM
Address

n+3

n+2

n+1

[N~
~L

Invalid

10
I"
10
10
·'iIJ.

0+3

n+2

n+1

II
I

"....0
~
~

I
11

I
I,

Display RAM
Address

J J

Il
I
I,

Display
Byte
(HEX) Char.

Display RAM
Address

110

10
10
10
10
10

0
8

Invalid

~
~

NEe
NEe Electronics Inc.

pPD7227
CMOS, Intelligent, Dot-Matrix
LCD Controller/Driver

Description

Pin Configuration

The /APD7227 intelligent dot-matrix LCD controllerl
driver is a peripheral device designed to interface
most microprocessors with a wide variety of dot
matrix LCDs. It can directly drive any multiplexed LCD
organized as 8 rows by 40 columns, and is easily cascaded up to 16 rows and 280 columns. The /APD7227
is equipped with several hardware logic blocks, such
as an 8-bit serial interface, ASCII character generator,
40 x 16 static RAM with full read/write capability, and
an LCD timing controller; all of which reduce microprocessor system software requirements. The
/APD7227 is manufactured with a single 5 V CMOS process, and is available in a space-saving 64-pin plastic
flat package.

C,
C2
C,
Co
R7/R15

RoIR14
Rs/R13

R.,JR'2
RalR11

C2'
C28
C2.

Features

o
o
o

o
o

Single-chip LCD controller with direct LCD drive
Compatible with most microprocessors
Eight row drives
- Designed for dot-matrix LCD configurations up
to 280 dots
- Designed for 5 x 7 dot-matrix character LCD configuration up to 8 characters
- Cascadable to 16 row drives
40 column drives
- Cascadable to 280 column drives
Hardware logic blocks reduce system software
requirements
- 8-bit serial interface for communication
- ASCII 5 x 7 dot-matrix character generator with
64-character vocabulary
- 40 x 16-bit static RAM for data storage, retrieval,
and complete back-up memory capability.
- Voltage controller generates LCD bias voltages
- Timing controller synchronizes column drives
with sequentially-multiplexed row drives
Single + 5 V power supply
CMOS technology

Pin Identification
No.

Symbol

Function

No connection

2-24,
47'57,
59-64

CO,C39

LCD column driver outputs

Vss

Ground

26, 58

VDD
CLOCK

System clock input

27
28

RESET

Reset input

Serial input

C/D

Command or data select input

SO/BUSY

Serial output or busy output

SCK

Serial clock input

Max Frequency

Chip select input

SYNC

Synchronization port

35-38

VLCD1- VLCD4
Ro/Rs-R7/ R15

LCD bias voltage supply inputs

Ordering Information
Part Number

Package Type

of Operation

IlPD7227G-12

64-pin plastic miniflat

1000 kHz

39-46

NECEL-000495

Power

LCD row driver outputs

7-13

fttfEC

J.lPD7227
Pin Functions

c/o

CO-C39

Command/data select input. Distinguishes serially in'
put data byte as a command or as display data.

LCD column driver outputs.

CS
RO/8-R7/15
LCD row driver outputs.

Chip select input. Enables the ).IPD7227 for communication with the microprocessor.

VLCD1- V LCD4

SYNC

LCD bias voltage supply inputs to the LCD voltage
controller. Apply appropriate voltages from a voltage
ladder connected across VDD.

Synchronization port. For multichip operation, tie all
SYNC lines together and configure with the MODE
SET command.

CLOCK

Serial input from the microprocessor.

System clock input. Connect to external clock source.

SO/BUSY

RESET

Serial output from the ).IPD7227 to the microprocessor
when in read mode and C/O is low. When BUSY (active low), handshake output indicates the ).IPD7227 is
ready to receive/send the next data byte.

Reset input. RC circuit or pulse initializes the ).IPD7227
after power-up.
VDD

Power supply positive. Apply single voltage 5 V± 10%
for proper operation.

SCK
Serial clock input. Synchronizes B-bit serial data
transfer between the microprocessor and ).IPD7227.

Vss
Ground.

Block Diagram

c/o

SO/BUSY

SCK

SI
83-(1()37958

7-14

ttiEC

/APD7227

Absolute Maximum Ratings

DC Characteristics

TA = 25°C

= -10°C to

-0,3 V to +7,0 V

Power supply, voo
All inputs and outputs with respect to Vec

-0,3 V to Voo +0,3 V

Storage temperature, TSTG
Operating temperature, TOPT

Parameter

25°C, VDD

Input capacitance

Unit

Output capacitance Co

Input/output
capacitance

Test
Max Unit Conditions

VIH

0,7 Voo

Vil

Input leakage
current, high

IUH

+10 I'AVIH

= Voo

Input leakage
current, low

IUl

-10 "AVIH

= OV

Output voltage, high

Output voltage, low

Max

Cia

Min

lYP

Input voltage, low

Limits
Symbol

Min

Input voltage, high

= OV

Parameter

Symbol

-10°C to + 70°C

Capacitance

± 10%

limits

-65°C to +150°C

Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage, The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification,
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability_

= +5,OV

+70 0 C, VDD

Voo

VOH1 Voo-O,5

V SO/BUSY,
IOH = -400 "A

VOH2 Voo-O,5

V SYNC,
IOH = -100 "A

VOL1

Test
Condmons

= 1 MHz

Unmeasured pins
returned to
pF
SYNC ground,

0,3 Voo V

0.45

V SO/BUSY,
IOl = +1.7 rnA

0.45

V SYNC,
IOl = + 100 "A

Output leakage
current, high

ILOH

+10 "AVOH

= Voo

Output leakage
current, low

IlOl

-10 "AVOl

= OV

LCD operating voltage

VlCO

3,0

Voo

V 8-row
multiplexed
LCD drive
configuration
V 16-row
multiplexed
LCD drive
configuration

Voo

Row drive
output impedance

RROW

Column drive
output impedance

RCOlUMN

100

200

400

"A fO = 400

Supply current

KHz

7-15

t-IEC

",PD7227

AC Characteristics
TA = -lODe to + 70 De, Voo

+5.0V :t 10%
Limits

Parameter

Clock frequency

Symbol

Ta..

Min'"

Max

UnR

100

' 1000

KHz

Clock pulse
width high

t+WH

400'

Clock pulse
width low

t+Wl

400

SCK cycle

tCYK

0.9

SCK pulse
width high

tKWH

400

SCK pUlse
width low

tKWl

400

SCK hold time
after BUSYt

tKHB

SI setup time
to SCKt

tlSK

100

SI hold time
after SCKt

tlHK

250

SO d~time
after K~

tODK

320

SO delay time
after c/TI~

tODD

SCK hold time
after C/D~

tKHD

BUSY delay
time after 8th
SCKt

tBDK

f'S

BUSY delay _
time after ClOt

tBDD

f'S

BUSY delah
time after C ~

tBDC

cill se.!!!e..time
to 8th SCKt

tDSK

C/O hold lime
after 8th SCi-------

50--------83.Q029088

7-29

t\'EC

#,PD7228/28A

PBral/ellnterfBce

c/o

BUSY---~

STB - - - - - - - - - ,

00-1l3

00-03
83OO2911B

Command Summary
Mnemonic

Operation

SFF

Set frame frequency

SMM

Set multiplexing mode

OISP OFF

Display off

OISP ON

Display on

LOPI

Load data pointer with Immediate

SRM

Set read mode

SWM

Set write mode

SORM

Set OR mode

SANOM

Set AND mode

SCML

Set character mode with left entry

SCMR

Set character mode with right entry

BRESET

Bit reset

BSET

Bit set

CLCURS

Clear cursor

Instruction Code

WRCURS

Write cursor

STOP

Set stop mode

~-Bo

Hex Code
10H-14H

1SH-1FH

aSH

SOH-B1H, CaH-F1H

SOH-63H

64H-67H

6SH-6BH

6CH-6FH

71H

a
a

Specifies a data memory bit

Os-Do

Immediate data

F~Fo

Specifies frame frequency as a submultiple of clock
frequency

11-10

Specifies modification of data pointer contents after
byte data is processed

Jl-JO

Specifies modification of data pointer contents after
bit is set or reset

M2-MO

Specifies data memory bank, number of rows, functions
of row/column drivers, and SYNC pin mode

7-30

asH

72H

2OH-3FH

4aH-5FH

7CH

70H

a1H

t-lEC

MEMORIES FOR GRAPHICS APPLICATIONS

8-1

Memories for Graphics Applications
Section 8
Memories for Graphics Applications
"PD41264/42273/42274
Dual·Port Graphics Buffers

8-3

~D421 01/421 02/42505
CMOS Une Buffers

8-1

~D42270

8..

NTSC Field Buffer
"PD43501
1,024-Channel Time-Division Switch

8-2

8-11

NEe

"PD41264/42273/42274
Dual-Port Graphics Buffers

NEe Electronics Inc.

Description
NEC's dual-port graphics buffers are equipped with a
4-bit random access port and a 4-bit serial read port. On
each device, the random access port is used by the host
CPU to read or write data addressed in any desired order.
The serial read port is connected to an internal data
register through a serial read output circuit.
The random access port also has a write-per-bit capability that allows each of the four data bits to be individually selected or masked for a write cycle. Furthermore,
a flash write option with write-per-bit control on the
"PD42274 is provided by the FWE pin and enables data
in the color register to be written to a selected row in the
random access port.
The devices feature fully asynchronous dual access,
except when transferring stored graphics data from a
selected row of the storage array to the data register.
During a data transfer, the random access port requires
a special timing cycle using a transfer clock; the serial
read port, however, continues to operate normally. Following the clock transition of a data transfer, the serial
read output data changes from an old line to a new line
and the starting location on the new line is addressable in
the data transfer cycle.
Refreshing is f1.pcomplished- by means of RAS-only refresh cycles or by normal read or write cycles. Automatic
internal refreshing, by means of either hidden refreshing
or the CAS before RAS timing and on-Chip internal
refresh circuitry, is also available. The transfer of a row of
data from the storage array to the data register also
refreshes that row automatically.
All inputs and outputs, including clocks, are TTL- compatible. All address and data-in Signals are latched onchip to simplify system design. Data-out is unlatched to
allow greater system flexibility.

Features
Cl
Cl
Cl
Cl
Cl

Two data ports: random access and serial read
Dual-port accessibility except during data transfer
Addressable start of serial read operation
Real-time data transfer
Random access port
- Two main clocks: RAS and CAS
- Multiplexed address inputs

- Direct connection of I/O and address lines
allowed by OE to simplify system design
- Read, early write, late write, read-write/readmodify-write, RAS-only refresh, and fast-page
capabilities
- Automatic internal refreshing by means of the
CAS before RAS on-chip address counter
- Hidden refreshing by means of CAS-controlled
output
- Write-per-bit capability regarding four 1/0 bits
- Write bit selection multiplexed on 100 -103
RAS-activated data transfer
- Same cycle time as for random access
- Row data transferred to data register as specified
by row address inputs
- Starting location of following serial read
operation specified by column address inputs
- Transfer of data on one row to the data register,
and the starting location of the serial read circuit,
activated by a low-to-high transition of DT
- Data transfer during real-time or standby
operation of serial port
Fast serial read operation by means of serial control
pins
- Serial data output on SOO-S03
- Direct connection of multiple serial outputs for
extension of data length

Ordering Information
Part Number

Row Access
Time (max)

Serial Acc...
Time (max)

"PD41264C-12

120 ns

40ns

0.15

150 ns

eons

"PD41264V-12

120 ns

40ns

V-15

150 ns

eons

"PD42273LE-l0

l00na

30ns

LE-12

120 n.

40ns

"PD42273V-l0

100 ns

30ns

V-12

120 ns

40ns

"PD42274LE-10

100 na

30 ns

LE-12

120 ns

40 ns

"PD42274V-10

100 na

30 ns

V-12

120 na

40 ns

Package
24-pln
plastic DIP
24-pln
plastic ZIP
28-pln
plasticSOJ
28-pln
plastic ZIP
28-pln
plastic SOJ
28-pln
plastic ZIP

Contact your NEC sales representative for copies of the complete data sheets.

8-3

NEe

"PD41264/42273/42274
Comparison of Dual-Port Graphics Buffers
Features

I'PD41264

I'PD42273

256K

1 Meg

Organization

64Kx4

256Kx4

Serial data register

Density

I'PD42274

256 x 4

512x4

Refresh period

4ms

8ms

Refresh addresses

256

512

Flash write

Yes

NMOS

CMOS

Process
Pins

Block Diagram

§=]

COunter

-·

I--

Column Decoder

I
I
I
I

Storage
Cell Array

t::==

Data
Register

• I-

SOE

.......Common

.......-

--------4t

Buffer

1
II:

W()fIOo
WI"OI
W21102
W3i103

Color
ReglS1er

J
Transfer
Gates

Ad;'
Counter

NI4'

Colo

1=
I

-'--

I N-1

Sense Amps

....--

,....-

•
•

Selector

I
~
I
IN-I N

Serial
Output

Buffer

rrr-

SOo
SOl
S02

I--- S03

RAS
CAS

ffiJii'E

wBiWE
(~PD42274

only) FWE

Timing

Generator
-~~_ _ _.J

83IH·5tl35B

8-4

t-IEC
NEG Electronics Inc.
Description

#,PD42101/42102/42505

CMOS Line Buffers

Ordering Information

NEC's dual-port line buffers are fabricated with a silicongate CMOS process and can execute asynchronous read
and write cycles at high speed. They also can be used as
a time axis converter or a digital delay line of up to the
length of the line buffer (at maximum frequency, the
minimum delay line length is 10 bits).
Applications include NTSC and PAL digital television
systems, image processing in facsimile machines, plain
paper copiers, video systems, and other optical scanners; time base correction in video playback systems;
and data communication buffering in multiprocessor
systems and local area netwOlKs.

Features
o Dual-port operation
o Image processing and data communications
systems applications
o Asynchronous and simultaneous read/write
operation

Read Cycle
Time (min)

Write Cycle
Time (max)

"PD42101C-3

34 ns

C-2

34 ns

69 ns

C-1

69 ns

"PD42101 G-3

34 ns

G·2

34 ns

69 ns
69 ns

Device

G·'

69 ns

"PD42102C-3

28 ns

C-2

28 ns

56 ns

C-1

56 ns

"PD42102G-3

28 ns

G-2

28 ns

56 ns

"PD42505C-50

G-1

50 ns

C-75

75 ns

C-50H

50 ns

C-75H

75 ns

"PD42P05\'-50

50 ns

V-75

75 ns

V-50H

50 ns

V-75H

75 ns

Package
24-pin
plastic DIP

24-pin
plastic mlniflat

24-pin
plastic DIP

24-pln
plastic mlniflat

24-pin
plastic DIP

28-pin
plastic ZIP

Contact your NEe sales representative for copies of the complete data sheets.

80021

8-5

t-IEC

"PD42101/42102/42505
Block Diagram

Read
Control

Read
Row Selector.

I--

FiE
RCK

RsTR

8
7-:r--

Data
Input
Buffers

Write
Column
Selector.

L.
WE
WCK

RSiW

Dual-Port
Storage
Cell Array

Read
Column
Selectors

Data
Output
Buffers

r+-

DOUTO - DOUT7

Write
Row Selector.

Write
Control

83SL-&1S4B

Comparison of Dual·Port Une Buffers
F.atu""
Organlzatlon

Speeds (ns)
4fsc digital television system
Maxlmum digital delay (clocks)

1'1"042101 "PD42102 "PD42505
910x8
1135x8
5048x8
34 or 69

28 or5B

NTSC

PAL

910

1135

50 or 75
5048

OPERATION
Reset Cycle
NEC's line buffers require the initialization of internal
circuits using the RSTWJRSTR reset signals before starting operation as a time axis converter or a digital delay
line.
A reset cycle can be executed at anytime and does not
depend on the state of RE or WE. However, RSTW and
RSTR must satisfy required setup and hold times as
measured from the rising edges of WCK and RCK.

WrltelRead Cycle
Write and read cycles are synchronized to their respective WCK/RCK inputs a~ executed individually when
WCK or RCK is high and WE or RE is low. Write data must
satisfy the setup and hold times as specified from the

8-6

rising edge of WCK. New data written to a particular
address is available for reading after 1/2 write cycle +
500 ns (maximum).
The access time of the read cycle is measured from the
rising edge of RCI<, either by tACR for an access during
the first cycle directly after a reset begins, or by tAcfor an
access under other conditions. Stored data is read nondestructively; data can be repeatedly read within a
prescribed time of 5 ms maximum (20 ms maximum for
H versions).

Time Axis Conversion
In order to use these line buffers as time axis converters
write and read cycles must be controlled independentl~
First, write/read ports are initialized separately using the
reset signals. Then, write cycles are executed in synchronization with WCK and write data is stored sequentially
from address 0 of the device. Afterward, when a read
cycle is executed in synchronization with RCK, stored
data can be read sequentially from address o.
Since write and read. cycles can be executed Independently, data loaded at one arbitrary drive frequency can
be read at another arbitrary drive frequency. In this
sense, the line buffer functions as a time axis converter.

1tt{EC
Digital Delay Line
NEe's line buffers can also easily be used as digital delay
lines. After initializing the internal circuits using simultaneous RSTW/RSTR signals, write/read cycles are executed simultaneously by supplying the same pulse to the
write clock (WeI<) and read clock (ReI<). The write data
is always read after the full line delay if neither write nor
read operation has been inhibited. This is the essential
delay line function.
If either WE or RE is set at a nonselected (high) level for
several cycles while the other is maintained at a selected
(low) level, the delay line length can differ from the line
length.
For example, if only WE is set to a high level (write
disable ) for a small number of cycles, read cycles are
executed continuously and the delay line length is large.
Alternatively, if only RE is set to a high level (read disable)
for a small number of cycles, write cycles are executed

"PD42101/42102/42505
continuously and the delay line length is small. Note that
the minimum delay line length is 10 bits (for maximum
frequency operation) and the maximum is the length of
the line buffer.
A data delay of less than the line length can also be
obtained by applying the RSTW and RSTR signals at
different times. For example, data is loaded for u m"
cycles after RSTW and then this data is read after
supplying RSTR. In the case, since write data can be read
from the beginning after a delay of u m" cycles, the device
can be used as an Um-bit" digital delay line.
The RSTW/RSTR reset signals can also be simultaneously loaded at every 1H (horizontal line) period. In
this case, write data loaded in the previous line cycle is
read out from the beginning as read data after the reset.
Therefore, a delay line length can be obtained according
to the length of the reset Signals supplied.

8-7

p.PD42101/42102/42505

8-8

t-IEC

!\fEe

pPD42270
NTSC Field Buffer

NEe Electronics Inc.

Preliminary Information
Description

Features

The tJPD42270 is a field buffer designed for NTSC TV
applications and for other applications where serial
data is needed. Equipped with four planes of 263-line
by 910-bit storage, the tJPD42270 can execute serial
write and read cycles on any of the 263 lines. Within a
line, four planes of 910 bits each may be written or read
at the NTSC sampling rate of 4fsc.

D Three functional blocks
- Four 263-line x 910-bit storage planes
- 910-bit write register for each plane
- 910-bit read register for each plane
D Two data ports: serial write and serial read
D Asynchronous operation
- Dual-port accessibility
- Carry-out capability to indicate position of scan
line
- Line jump, line hold, line reset, and pOinter clear
functions
D Synchronous operation
- Variable field length: 260 to 263 lines
- Variable last line length: 896 to 910 bits
D Automatic refreshing
D CMOS technology
D Fully TTL-compatible inputs, outputs, and clocks
D Three-state outputs
D Single +5-volt ±10% power supply
D On-chip substrate bias generator
D Standard 400-mil, 28-pin plastic DIP packaging

Each of the four planes in the tJPD42270 is equipped
with two ports, one each for the write and read data
registers. Each of the registers is split into two 455-bit
segments, but functions as if it were organized as one
scan line of 910 bits. Independent control of write and
read operation makes it possible for the device to
operate synchronously or asynchronously at a clock
frequency of 14.3 MHz or higher.
The synchronous option simplifies interframe luminance (Y) and chrominance (C) separation and interfield noise reduction and makes it easy to obtain a
one-field delay line for digital TV and VCR applications requiring NTSC 4fsc sampling. To obtain a very
long delay, field length can be configured from 260 to
263 lines and line length of the last line from 896 to
910 bits.
The asynchronous option is useful in applications
such as frame synchronization and time base correction, where line jump, line hold, line reset and pointer
clear functions are required to support special effects
in TV field processing.
Regular refreshing of the device's dynamic storage
cells is performed automatically by an internal arbitration circuit. All inputs and outputs, including clocks,
are TTL-compatible. The tJPD42270 is packaged in a
400-mil, 28-pin plastic DIP and is guaranteed for
operation at -20 to +70°C.

Ordering Information
Part Number

I'PD42270C-60

Access Time
(maxi

Cycle Time
(mini

40 ns

60 ns

Package

28-pin plastic DIP

Contact your NEC sales representative for a copy of the complete data sheet.
NECEL-001080

8-9

t-{EC

IIPD42270
Block Diagram

Refresh

Timer

Write Bit Pointer

BSO/WCO -

r---

BSt/RCO -

Write
Scan

Line
Pointer

BS2/WLH BS3/RLH MODE -

WCK-

Timing
WCLR- Generator
WLRST WLJ-

RCKOE-

RCDiRLRST RLJ-

Read
Seen
Line
Pointer

~
~

l.!

Write Data Register

oINO- 0 IN3

Write Bit Pointer

Write Data Register

LSO-LSt -

Data
Input

I::J-

Buffer

II
-I--

910 Bits Per Line

Storage Cen Array

Scan
Line
SeleCtor

263 Lines
Per Plane

H-~
Counter

'---

I--

l.~
il

J
Read Data Register

Read Data. Register

I
I

Read Bit Pointer

~
I-f
I

Data
Output
Buffer

DOUTO-DOUT3
83-0052008

8-10

~EC

pPD43501
1,024-Channel
Time-Division Switch

NEG Electronics Inc.
Preliminary Information
Description

Features

The,uPD43501 is a time-switch device designed for use
in a high-performance digital communications network. Features include a time-switch function by
which up to 1,024 channels can be exchanged using
a 16-bit data width, and a tone output function by which
an 8-bit tone signal can be output to an arbitrary
channel.

o Separate switch storage and control storage to

Two planes of 1-kword by 8-bit storage area and one
plane of 1-kword by 10-bit control storage area for the
time-switch function enable the ,uPD43501 to realize
switching modes in which arbitrary 1,024 or 512 input
channels can be connected to arbitrary 1,024 or 512
output channels. The configuration of the tone signal
output section, one plane of 64-word by 8-bit tone
storage area and one plane of 1-kword by 8-bit tone
control storage area, allows the device to output up to
64 different tone signals to an arbitrary output channel
as 8-bit voice/tone data.

Part Number

Data Transfer Rate [max)
8.192 Mbps

NECEL-1540V2

o
o
o
o

Ordering Information
pPD43501R

Package
132-pin ceramic pin grid
array (PGA)

o
o
o

allow construction with one VLSI device of a nonblocking switching network having a maximum
capacity of 1,024 channels
Selectable operation
- 1,024 by 1,024 serial input and output
- 1,024 by 1,024 parallel input and output
• 16.384 MHz operating frequency
• 8.192 Mbps data transfer rate
- 512 by 512 parallel input and output
• 8.192 MHz operating frequency
• 4.096 Mbps data transfer rate
Switching flexibility
- 8- or 16-bit data width
- n by 64 kbps connection
Tone signal output function
8 by 8 space switch for an 8.192 Mbps, 128-channel
multiplexed line
CPU interfaces for the control storage and tone
control storage
Low power consumption: 1000 mW (typ)
TTL-compatible inputs and outputs
132-pin ceramic pin grid array packaging

8-11

fttfEC

pPD43501.
Switching Functions
Mode 0
In this mode, the pPD43501 inputs eight 128-channel
multiplexed lines from ports 5100 through SID? (or
from ClOD through CIO?) and outputs eight 128-channel
multiplexed iines to ports 5000 through SOD? (or COoo
through COO?). Referto figure 1 for a functional pin
diagram.
Serial input data from the input ports first is converted
to parallel data by the serial-to-parallel converters in
the receive section, and then multiplexed and sent to
the input section of the switch storage area. Since the
write address counter is synchronized with input data,
the write address of the switch storage area corresponds to the time slot number of the input signal.
Writing multiplexed data to the switch address specified by the write address counter causes input data in
the time slot corresponding to the switch address
always to be stored at that address (figure 2).
Conversely, a .control storage address corresponds to
an output-side time slot number, and the data in control
storage indicates the switch storage address, i.e., the
input-side time slot number is stored at the control
storage address corresponding to the output-side time
slot to which the input-side is transferred.
The address signal is sent from the read address
counter to control storage in synchronization with
each output-side time slot. Data read out by this
operation is then sent to the switch storage area as the
address signal, and the data in the specified address
(input-side time slot) is then read out on the output side
and switched. Switched data is sent to the parallel-to-

8-12

serial converters in the transmission section, where it
is converted to serial data and then output to the
appropriate output ports.
With this switching function, the data in an arbitrary
time slot on the input side can be output as data in an
arbitrary time slot on the output side. Furthermore, in
addition to the time division switch function, a space
switch function enables switching time slots on any of
the eight input ports to be output on any of the eight
output ports. This means that a nonblocking 8 x 8
space switch for 128-channel multiplexed lines can be
realized.

Mode 1
Mode 1 makes it possible for the pPD43501 to input
512-channel multiplexed lines (4.096 Mbps by 8 bits), 8
bits in parallel, and output 512-channel multiplexed
lines, 8 bits jn parallel. The input signals received on
the input ports are sent to the switch storage area in
parallel, after which the same switching functions
described in Mode 0 are then performed.

Mode 2
In Mode 2, the pPD43501 inputs 1,024-channel multiplexed lines (8.192 Mbps by 8 bits), 8 bits in parallel,
and outputs 1,024-channel multiplexed lines, 8 bits in
parallel. The input signals received on the input ports
are sent to the switch storage area in parallel, after
which the same switching functions described in
Mode 0 are performed.

t-IEC

J,lPD43501

Block Diagram

~
WE
DIN
SIP

DOUT

PIS
or
POUT

Switch
Storage 2

orPIN

ADo

DIN

DOUT
Switch
Storage 1

SIP
or
PIN

ADl

FH
ClK
ClK1
ClK2
MODO
MOD1
TSPo
TSP1

SOooS007

DIN
WE

PIS
or
POUT

DOUT

I
I

RST

AD1

ADO

--------

COooC007

WAoo-WA09
WCOO-WC09
CTlD

Tone Storage
ADO

Write

ADl

Address
Counter

TSEl

Timing
Generator

DOUT1
Control Storage

I
Counler

DOUT2

DIN

ADl

ADo

AD1

Read Address

RAOO-RA09

f f

RCRY TRCR RCTl RCooRC09

t-r-t-

DOUTl
Tone- Control
Storage
DIN
DOUT2 tSEl: Selector
SIP: Serial-to-Parallel
Converter
PIS: Parallel-to-Serial
Converter

ADO

CPU Interface

f f f 1 1 f f t

VC5TC

TONE ADST DTST SCNl SCN2

DBBDB9

DBoDB7
83-0052188

8-13

pPD43501
Time Slot Versus Frame Configuration
ModaO
SIOO(OLO)

Sloo! (ILO)
Sarlal Data

Sarlal Data
TDSWLSI

Sloo' (IL7)

Sioo (OL7)

1024 x 1024
FH
CLK

Frame Configuration

1251'"

.Jl

•

((

Siro

TSO (ILO CHO)

TS8 (ILO CHI)

I
I
I
I

TS7(1L7CHO)

TS15 (IL7 CHI)

TSO (OLO CHO)

TS8 (OLO CHI)

TS7 (OL7 CHO)

TS15 (OL7 CHI)

r,}
-ft

I
I
I
I

TSl023 (IL7 CH127)

Sl07

~oo

TSl016 (ILO CH127)

~
I

r"I

TS1016 (OLO CHI27)

(

S007

/I
"

TS1023 (OL7 CHI27)

Tlma Slot Configuration

•

122n_

•

fJ-

FHJ

CLK

Sl oo
I
I
I
I
I

\..
87

SI 07

SOoo
I
I
I
I

so:U

\...

•I't=r:

,I't=r:

I
I
I

,
I

86
)

Notss:
[I) IL Input IIna
[2) OL output IIna
[3) TS = tima slot
[4) CH channal

=
=
=

8-14

't=r:

83IH-52158

NEe

PACKAGE DRAWINGS

9-1

Package Drawings
Section 9

Package Drawings
Package/Device Cross-Reference

9-3

28-Pin Plastic SOP (375 mil)

9-6

3O-Pin Plastic Shrink DIP (400 mil)

9-6

4O-Pin Plastic DIP (600 mil)

9-8

4O-Pin Ceramic DIP With Side-Brazed Leads
(600 mil)

9-7

4O-Pin Cerdip (600 mil)

9-8

44-Pin PLCC

9-9

48-Pin Plastic DIP (600 mil)

8·10

52-Pin Plastic Miniflat (3.5-mm leads)

8·11

52-Pin Plastic Miniflat (1.8-mm leads)

8·12

52-Pin PLCC

8·13

64-Pin Plastic Miniflat

8·14

64-Pin Plastic Shrink DIP (750 mil)

9-15

68-Pin PLCC

9-18

74-Pin Plastic Miniflat

9-17

8O-Pin Plastic Miniflat (2.35-mm leads)

9-18

8O-Pin Plastic Miniflat (1.8-mm leads)

9-18

84-Pin PLCC

9-20

94-Pin Plastic Miniflat

9-21

100-Pln Plastic Miniflat

9-22

132-Pln Ceramic PGA

9-23

9-2

ttlEC

Package Drawings

Package/Device Cross-Reference
Package

Device, ,.PD

Package

Device, ,.PD

28-Pln Plastic SO P (375 mlO

71065G

52-Pin PLCC

SO-Pin Plastic Shrink DIP (400 mil)

71066CT

40-Pin Plastic OIP (600 miO

765AC2
765B
7201AC

72001L
72001L-ll
72061L
72067L

72001C
720010.11
720200.8
72061C
72065C
72065BC
40-Pln Ceramic DIP With Side-Brazed Leads
(600 mil)

7201 AD
7220AD
7220AD-l
7220AD-2
7261AD
7261 BO-18
7261 BO-23

64-Pin Plastic Mini!lat

7227G-12

64-Pln Plastic Shrink DIP (750 mil)

72111CW
72185CW

68-Pin PLCC

72022L
72111L
72185L

74-Pin Plastic Mini!lat

72111GJ-5BJ

80-Pin Plastic Mini!lat (2.35-mm leads)

7228G-12
7228AG-12

80-Pin Plastic Mini!lat (1.8-mm leads)

72022GF-3B9
72068GF-3B9

54-Pin PLCC

72068L
72069L
72120L
72123L

40-Pin Cerdip (600 miQ

7262012
7262018

44-Pin PLCC

72065L
72065BL

94-Pln Plastic Mini!lat

72120J-5BG
72123GJ-5BG

48-Pin Plastic DIP (600 miQ

72067C

100-Pin Plastic Mini!lat

72069GF-3BA

52-Pin Plastic Mini!lat (3.5-mm leads)

7225G-OO
72065G

132-Pin Ceramic PGA

72123R

52-Pin Plastic Mini!lat (1.8-mm leads)

72001 Go.3B6
72001GC-3B6-11
7202OGo.8-3B6
72061 Go.3B6
72065GC
72065BGo.3B6
72067Go.3B6

9-3

Package Drawings

9-4

ttiEC

t-IEC

Package Drawings

28-Pin Plastic SOP (375 mil)
Item

Mlilimelers

Inches

18.07 max

.711 max

10.3±O.3

.406 ±.012

c
o

7.2

.283

2.9 max

.114max

2.50

.098

F
G

1.6

.063

1.27 [TP]

.050 [TP]

0.8±O.2

.031 ±.008

0.78 max

.031 max

0.40

~:~~

.016

~:~~~

0.15

~:~~

.006

~:~~~

0.12

.005

0.1 ±O.1

.004±.004

P28GM·5()..375R

831H·5751 B (6189)

30-Pin Plastic Shrink DIP (400 mil)

Item

Millimeters

28.46 max

1.120 max

10.16 [TP]

.400 [TP]

8.6

.339

0
E
F

5.08 max

.200 max

4.31 max

·.170 max

3.2±O.30

.126±.012

1.78 max

.070 max

1.778 [TP]

.070 [TP]

0.85 min

.033 min

Inches

0.51 min

.020 min

a.50 ±O.10

0.20 ±.004

0.25
M

0.17

S3OC·70-400B

~:6~

.010

.007

~:gg~

J u~,
!

I 'I

i~D

Gi--

0Il--i I--

--II-.
L

0-15"
83vQ.61398 (6/89)

9-5

ttlEC

Package Drawings
4D-Pln PI••tlc DIP (600 mil)

9-6

Hem

Millimeter.

A
B
C
0
E
F
G
H
I
J
K

53.34 max

0.25

15.24 [TPJ
13.2
5.72 max
4.31 max
3.6:1:0.3
2.54 max
2.54I!Pj
1.2 min
0.51 min
0.50:1:0.10

~:~~

Inch..
2.100 max
.600[TPj
.520
.225 max
.170 max
.142±.012
.100 max
.100 I!P)
.047 min
.020 min
.020:1:.004
.010

.010

~:gg:

: : : : : : : : : A: : : : : : : : : ; I

t-lEC

Package Drawings

4O-Pin Ceramic DIP With Side-Brtu.ed Leads (600 mil)
Item

Millimeters

Inches

A
B
C
0

53.34 max
2.54 max
2.54 (TP)
0.46 ±0.05
0.92 min
3.5 ±0.3

2.100 max

G
H

1.0 min
2.64
4.57 max

.100 max
.100 (TP)
.018 ± .002
.036 min

.138 ±.012
.039 min
.104
.180 max
.600 (TP)
.588

15.24 (TP)
14.93

0.25 ±0.05

.010

0.25

.010

~:gg~

* Item K to center of leads

when formed parallel.

P40D-100-s00A

49NR·526B (5/89)

9-7

t\'EC

Package Drawings
lID-PIn Cerdlp {6tJD mil}
Item

Millimeters

Inches

A
B

2.100 max

53.34 max
2.54 max
2.54 (TP)

O.SO ±0.10

1.2 min

.020 + .004
-.005
.047 min

G
H

3.5 ±0.3
0.51 min

.138 ±.012
.020 min

3.80

.150

5.08 maX

.200 max
.600 (TP)

15.24 (TP)

.100 max
.100 (TP)

13.21

.520

0.25 ±0.05

.010

0.25

.010

" Item K to center of leeds
when formed parallel.

~:gg~

I'i'

-liM

j\~
0-15°

49NR-53OB (8180)

9-8

NEe

Package Drawings

44-PinPLCC

Itam

Millimeters

A
B
C
D
E
F
G
H
I
J
K
M
N
P
Q
T

17.5 ±O.2
16.58
16.58
17.5 ±O.2
1.94 ±O.15
0.6
4.4 ±O.2
2.8 ±O.2
0.9 min
3.4
1.27 (!Pl
0.40 ±O.10
0.12
15.50 ±O.20
0.15
0.8 radius

0.20

j:rig

rF:

Inche.

.689
.653
.653
.689
.076
.024
.173
.110
.035
.134
.050
.016
.005
.610
.006
.031

.008

±.008

±.008
±.OO6

±.008
±.008
min

111

(TP)
±.004
±.008
radius

::gg:
G

P44L-SOAt

.... 83Y........

9-9

NEe

Package Drawings
48-Pln "'.,11: DIP (6110 mil)
Item

Millimeters

Inch.s

A
B
C
D
E

2.500 max
.600 [TP]
.543
.225 max
.170 max
.142:1:.012
.100 max
.100 [!P]
.043 min
.020 min
.020:1:.004

63.50 max
15.24 [TP]
13.8
5.72 max
4.31 max
3.6:1:0.3
2.54 max
2.54[TP]
1.1 min
0.51 min
0.50:1:0.10

0.25

G
H
I

:g:~~

.010

::gg:

.010

[]]

--t~
0-lSO

P48C-100-&00A

9-10

83vQ.6t388 (81891

NEe

Package Drawings

52-Pin PIe.tlc Mlnltl., (3.5-mm leads)
Item

MIllimeters

21.0 ±0.4

Inches
.827 ±.016

14.0 ±0.2

.551

~:gg~

14.0 ±0.2

.551

~:g:

0
G

21.0 ±0.4
1.0
1.0

.827 ±.016
.039
.039

0.40 ±0.10

.016

0.20
1.0 (TP)

.008
.039 (TP)

3.5 ±0.2

.138

~:gg~

2.2 ±0.2

.087

~:g:

0.15

.006

~:gg~

0.15

2.6

0.1 ±0.1

~g:6g

~g:~

~:g~

C 0

.006
.102

~:gg~

.004 ±.004

J
@l

@10
K

~mooioon]niJ+
Q
P52G-100.00

,.....

49NA·5368
)

9-11

Package· Drawings

.-PIn ",..,It: """"., (t.B-mm""j
hem
A

MIllimeters
17.6 ±0.4

Inches
.693 ±.016

~:gg:

14.0 ±0.2

.551

14.0 ±0.2

0
F
G

17.6 ±0.4
1.0
1.0

551 +.009
.
-.008
.693 ±.016
.039
.039

0.40 ±0.10

.016

0.20
1.0 (TP)

.008
.039 (TP)

1.8 ±0.2

.071

~:g:

0.8 ±0.2

.031

~:gg:

0.15

.006

~:g~

0.15
2.7
0.1 ±0.1
0.1 ±0.1
3.0 max

P
Q

R
S

C 0

~:::

~g:cig

.006
.106
.004 ±.004
.004 ±.004
.119 max

I$l

®10
Enlarged detail of lead end

EE+I+
Q

'(9NR-493B (Hit

9-12

NEe

Package Drawings

52-Pin PLCC

nam

Millimeters

A
B

K
M
N
P
Q
T

20.1 :to.2
19.12
19.12
20.1 :t02
1.94 :to.1S
0.6
4.4 :to.2
2.8 :to.2
0.9 min
3.4
127 [P!
0.40 :to.10
0.12
18.04 :to.20
0.15
0.8 radius

0.20

C
D
E
F
G
H

:+g:~

Inche.

.791
.753
.753
.791
.076
.024
.173
.110
.035
.134
.050
.016
.005
.710
.008
.031

±.008

±.008
±.008
52
±.008
±.008
min

[P!
±.004
±.008
radius

.008:,":~

P52L-sMt

9-13

Package Drawings
tJ4..Pln Pla.tlc .,,,,,,.,
Rem

Millimeters

24.7 ±0.4

.972

20.0 ±0.2

.795 : : : :

14.0 ±0.2

.551 : : : :

0
F
G

18.7 ±0.4
1.0
1.0

.736 ±.016
.039
.039

0.40 ±0.10

.016 : : : :

0,20
1.0 (TP)

.008
.039 (TP)

2.35 ±0.2

.093

1.2 ±0.2

.047

015 +0.10
_', -0.05
0.15

.006

N
P

P64G-100-12, 18

2.05 +0.2
-0.1
0.1 ±0.1

Inches

::g1~

C 0

::gg~

::gg:
::gg;

.006
·081

::gg~

1$1

@10

.004 ±.004

49NR·5438 (8189)

NEe

Package Drawings

64-Pln Plastic Shrink DIP (T50 mil)
64

~----------------------A----------------------~

P64C-7o-750A, C

@l M@1

Hem

Millimeters

58.68 max

Inches
2.310 max

19.05 (TP)

.750 (TP)

17.0

.669

D
E

5.08 max

.200 max

4.31 max

.170 max

F
G

3.2±O.3
1.78 max

.126±.012
.070 max

1.778 (TP)

.070 (TP)

0.9 min

.035 min

0.51 min

.020 min

0.50 ±O.10

.020±.004

0.25~g:ri~

:010~:gg~

0.17

.007

0-15'

518.
83YL-5560B

9-15

Package Drawings
tI,-PIn PLCC
A
B

111m
A
B
C

Mlilimete,.
25.2iO.2
24.20
24.20
25.2iO.2

1.94iO.15

.076~:g:

0.6

.024

4.4iO.2

.173~:=

2.8iO.2

.110~:=

I
J

0.9 min
3.4

.035 min
.134

1.27 !!~

.050(T~

0.40iO.10

.016~:~

0.12

.005

23.12iO.2O

.910~:::

0.15
0.8 radius

.006
.031 rBd"IUS

0.20+0·10
-0.05

008+.004
.
-.002

Ii'

Inch..
.992:1:.008
.953
.953
.992:1:.008

CC[]CCCCC

G
T

5180
83VL..&S818

9-16

ttlEC

Package Drawings

74-Pin Plastic Mlnlflat
Millimeters

23.2 ±0.4

.913

~:g~~

20.0 ±0.2

.787

~:gg:

20.0 ±0.2

.787

~:gg:

23.2 ±0.4

.913

~ :g~~

2.0
1.0
2.0
1.0

.079
.039
.079
.039

F2
G1
G2

0.40 ±0.10

.016

.008
.039 (TP)

0.20
1.0 (TP)
1.6 ±0.2

0.8 ±0.2

.031

~:gg~

0.15

.006

~:gg~

N
P

0.15
3.7
0.1 ±0.1
0.1 ±0.1
4.0 max

~:gg~

~g:~~

Inches

Item

.063 ±.002
F1

.006
.146
.004 ±.004
.004 ±.004
.158 max
Enlarged detail of lead end

H;4
Q

S74GJ·100·5BJ

49NR-347B
(6/89)

9-17

NEe

Package Drawings
IItJ-Pln PI.,ic ",nit,., (2.35mm IeIIds)
item

9-18

Mllllmet....

Inch..

24.7±OA

.972:1:.018

l!O.O±O.2

.787

14.0±O.2

.551 +.009
-.00&

0
F

1&.7±O.4

.736:1:.018

1.0

.039

0.&

.Q31

0.35±O.10

.014

0.15

.ooa

~:~

:::~

CTPI

0.8 (TP)

.Q31

2.35±o.2

.ass

l.2±O.2

J)47::~

0.15

2.05

0.1 to.l

~~g

+.009
-.00&

.ooa +.004

-.002

.006

.0&1

~:gg:

.004:1:.004

t-IEC

Package Drawings

SO-Pin Pls.tic MlniflBt (I.B-mm IfIIIds)
Millimoto ..

Inch ••

23.6±O.4

.929±,016

20.0±O.2

.7Pi7

14.0±O.2

.551 +.009

D
F
G

17.6:10.4

.693 ±.016

1.0

.039

0.8

.031

0.35:10.10

.014

0.15

.005

Item

::~
-.008

::~

0.8 (TP)

.031 (TP)

1.8±O.2

.071

::~

0.8±O.2

.031

::~

0.15

N
P

0.15
2.7

0.1 ±O.1

R
S

0.1 ±O.1

.004±.004

3.0 max

.118 max

~:~

.005 +.004
-.002

.005
.106
.004±.004

Pin Detail

PSOGF·8Q·3B9

83IH·S543B (6189)

9-19

ttlEC

Package Drawings
B4-PinPLCC

----------I3-C D

~--~----------p---------------~
P84L--50A3

9-20

83YL·SSOGB

I"'~

ttlEC

Package Drawings

94-Pin PI••tic lIinitl.t
A
Item

Millimeters

Inches

23.2 ±O.4

.913 +.017
-.016

20.0 ±O.2

.787 +.009
-.006

20.0 ±O.2

+.009
.787 -.008

23.2 ±O.4

.913

~:g~~

.063
.031
.063
.031

Fl
F2
Gl
G2

1.6
0.8
1.6
0.8

0.35 ±O.10

.014 +.004
-.005

J
K

0.15
0.8 (TP)
1.6 ±O.2

.006
.031 (TP)
.063 ±.006

0.8 ±O.2

.031 +.009
-.008

0.15

N
P

0.15
3.7
0.1 ±O.1
0.1 ±O.1
4.0 max

R
S

•

~:ci~

~~--------+--------~~

C D

.006 +.004
-.003
.006
.146
.004 ±.004
.004 ±.004
.158 max

Detail of lead end

R
S94GJ-8~5BG

6/89

83YL·5810B

9-21

ftiEC

Package Drawings

'DO-Pin Pillstic Minlfillt
A
Item

Millimeters

Inches

23.6 ±O.4

.929 ±.016

20.0 ±O.2

.787

~:gg:

14.0 ±O.2

.551

D
F
G

17.6 ±O.4
0.8
0.6

.693 ±.016
.039
.031

~:gg~

0.30 ±O.10

.014

0.15
0.65 (TP)

.006
.031 (TP)

1.8 ±O.2

.071

~:gg:

0.8 ±O.2

.031

~:gg:

0.15~:ri~

.006

~:gg~

N
P

0.15
2.7
0.1 ±O.1
0.1 ±O.1
3.0 max

.006
.106
.004 ±.004
.004 ±.004
.118 max

a
R
S

•

-l=$;:I-------+------4$~ C D

Detail 01 lead end

R
P100GF-65-38A

9-22

6/89 83YL-S811 B

t-IEC

Package Drawings

132-Pin Cer.mlc PGA
A

P N M L K J H G FED C B A

,"
r

1
1

'
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1989_NEC_Intelligent_Peripheral_Devices_Data_Book 1989 NEC Intelligent Peripheral Devices Data Book

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